1989_231658_Intel_Microcommunications_Handbook 1989 231658 Intel Microcommunications Handbook
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HANDBOOK
1989
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Table of Contents
Alphanumeric Index
Microcommunications Overvi~w AP-302 .... ~ . .. .. .. . .. . . . . .. . . . . . . . . . . . .. .. .
xi
SECTION ONE-DATA COMMUNICATIONS COMPONENTS
CHAPTER 1
Local Area Networks
CSMA/CD Access Method
DATA SHEETS
82586 Local Area Network Coprocessor .....................................
82C501 Ethernet Serial Interface ............... ; .........•.. " . . . . . . . . . • . . . .
Twisted Pair Ethernet Chip Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82560 Host Interface and Memory Controller .... ;............................
82590 Advanced CSMAlCD LAN Controller with 8-Bit Data Path ... . . . . . . . . . . . . .
82592 Advanced CSMAlCD LAN Controller with 16-Bit Data Path . . . . . . . . . . . . . ..
82588 High Integration LAN Controller ........................ '. . . . . . . . .. . . . ..
APPLICATION NOTES
An 82586 Data Link Driver AP-235 ..........................................
Implementing Ethernet/Cheapernet with the Intel 82586 AP-274 ................
Implementing StarLAN with the Intel 82588 AP-236 . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Using the Intel 82592 to Integrate a Low-Cost Ethernet Solution into a PC
Motherboard AP-320 ..............•.....................................
CSMAlCD ACCESS METHOD EVALUATION TOOLS
PC586E CSMAlCD LAN Evaluation Board ...................................
1-1
1-38
1-54
1-56
1-86
1-103
1-120
1-176
1-256
1-345
1-419
1-464
CHAPTER 2
Wide 'Area Networks
DATA SHEETS
8251A Programmable Communication Interface...............................
82050 Asynchronous Communications Controller .............................
82510 Asynchronous Serial Controller
................... '. . . . . . . .. . . . . .
8273 Programmable HDLC/SDLC Protocol Controller. . . . . . . . . . . . . . . . . .. . • . . . . .
8274 Multi-Protocol Serial Controller (MPSC) .................................
82530/82530-6 Serial Communications Controller (SCC) . . . . . . . . . . . . . . . . . . . . . ..
APPLICATION NOTES
Designing with the 82510 Asynchronous Serial Controller AP-401 .;.............
High Performance Driver for 8251 0 AP-31 0 : . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . ..
Using the 8273 SDLC/HDLC Protocol Controller AP-36 ........................
Asynchronous Communication with the 8274 Multiple Protocol Serial Controller
AP-134 ' ......................... '........................ :.. . . . . . . . .. . . ..
Synchronous Communication with the 8274 Multiple Protocol Serial Controller
AP-145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Asynchronous and SDLC Communications with the 82530 AP-222 . . . . . . . . . . . . . ..
2-1
2-26
2-40
2-80
2-112
,2-150
2-182
,2:~
{2-293 j
"~-'-'
2-345
2-383
2-421
CHAPTER 3
Other Components,
DATA SHEETS,
8291A GPIB Talker/Listener .... , ..... , .................................... .
8292 GPIB Controller ...................................................... .
8294A Data Encryption/Decryption Unit .................•....................
APPLICATION NOTES
Using the 8291A GPIB Talker/Listener AP-166................................
Using the 8292 GPIB Controller AP-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-33
3-52
3-65
3-95
Table of Contents (Continued)
SECTION TWO-TELECOMMUNICATION COMPONENTS
CHAPTER 4
Modem Products
DATA SHEETS
890242400 BPS Intelligent Modem Chip Set.................................
89C024XE High Performance 2400 BPS Intelligent Modem Chip Set. . . . . . . . . . . . .
MNP Application Package
MNP Class 5 Software for the 89C024XE Modem Chip Set .....................
EVALUATION KITS
89024 MEKPC. PC Card Modem Evaluation Kit for 89024 ......................
89024 MEK2. 89024 Enhanced Modem Evaluation Kit .. . . . . . . . . . . . . . . . . . . . . . . .
MEK3 Modem Evaluation Kit ...............................................
4-1
4-22
4-44
4-46
4-48
4-50
CHAPTER 5
IATC Advanced Telecommunications Components for Analog and ISDN
Applications
SLD Interface Specification. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
DATA SHEETS
iATC 29C48 Feature Control Combo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iATC 29C53AA Digital Loop Controller . . .. . . . .. .. . . .. .. .. .. .. . . . . .. . . .. .. .. ..
89151 T-Link Communications Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISP188 ISDN'Software Package for the 80188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC53 ISDN Board. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10K 29C53 ISDN Development Kit for 29C53 .................................
LEK 29C53 Line Card Evaluation Kit .. . . .. .. . . . .. .. .. .. .. . . . . . . . . . .. .. .. . . . . .
TEK 29C53 Terminal Evaluation Kit..........................................
APPLICATION NOTES
29C53 Transceiver Line Interfacing AP-282. .. . . .. .. . ... . .. . . .. . . . . . .. . .. . . .. .
ISDN Applications with 29C53 and 80188 AP-400 ........•....................
5-1
5-5
5-25
5-50
5-53
5-59
5-67
5-73
5-75
5-78
5-92
CHAPTER 6
PCM Codec/Fliter and Combo
DATA SHEETS
2910A PCM Codec-JA. Law8-Bit Companded AID and D/A Converter............
2911 A-1 PCM Codec-A Law 8-Bit Companded AID and 01 A Converter ..........
2912A PCM Transmit/Receive Filter.........................................
2913 and 2914 Combined Single-Chip PCM Codec and Filter ...................
2916/2917 HMOS Combined Single-Chip PCM Codec and Filter .. . . . . . . . . . . . . . .
APPLICATION NOTES
Applications Information 291 OAl2911 A/2912A .................•.............
Designing Second-Generation Digital Telephony Systems Using the Intel
2913/2914 Codec/Filter Combochip AP-142 ..........•....................
6-1
6-19
6-34
6-46
6-67
6-85
6-88
SECTION THREE-SYSTEM PRODUCTS
CHAPTER 7
Local Area Networking Boards and Software
OpenNETTM Local Area Network Family ................ :....................
7-1
CHAPTER 8
Serial Communication Boards
iSBC~ 88/45 Advanced Data Communications Processor Board . . . . . . • . . . . . . . . .
iSBC~ 188/56 Advanced Communicating Computer .........•...............•
iSBC~ 534 Four Channel Communications Expansion Board. • . . . . . . . . . . . . . . . . . .
iSBC~ 544 Intelligent Communications Controller ........................... '. .
8-1
8-10
8-19
8-24
Table of Contents, (Continued)
iSBC® 548/549 Terminal Controll~rs ........................................
iSBC® 561 SOEMI Controller Board .........................................
iSBXTM 351 Serial 110 MULTIMODULETM Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBXTM 354 Dual Channel Serial 1/0 MULTIMODULETM Board. . . . . . . . ... . . . . . . . .
iSBC® 186/41 OMULTIBUS® II Serial Communications Computer ........... : . . .
8-33
8-37
8-42
8·48
8-53
Alphanumeric Index
2910A PCM Codec-p. Law 8-Bit Companded AID and 0/ A Converter. , ............. ',' ..
2911A-1 PCM Codec-A Law 8-Bit Companded AID and 0/ A Converter ................ .
2912A PCM Transmit/Receive Filter .....................•.................... .' ... .
2913 and 2914 Combined Single-Chip PCM Codec and Filter ............. : ........... .
2916/2917 HMOS Combined Single-Chip PCM Codec and Filter ............ : ......... .
29C53 Transceiver Line Interfacing AP-282 ........................................ .
82050 Asynchronous Communications Controller ................................... .
825.1 0 Asynchronous Serial Controller (SCC) ....................................... .
8251A Programmable Communication Interface .................................... .
82530/82530-6 Serial Communications Controller (SCC) ............................. .
82560 Host Interface and Memory Controller ....................................... .
82586 Local Area Network Coprocessor .......................... : ................ .
82588 High Integration LAN Control ............................................... .
82590 Advanced CSMAlCD LAN Controller with 8-Bit Data Path ...................... .
82592 Advanced CSMAlCD LAN Controller with 16-Bit Data Path ..................... .
8273 Programmable HDLC/SDLC Protocol Controller ............................... .
8274 Multi-Protocol Serial Controller (MPSC) ....................................... .
8291A GPIB Talker/Listener ..................................................... .
8292 GPIB Controller ............................................................ .
8294A Data Encryption/Decryption Unit ........................................... .
82C501 Ethernet Serial Interface ................................................. .
890242400 BPS Intelligent Modem Chip Set ....................................... .
89024 MEK2, 89024 Enhanced Modem Evaluation Kit ............................... .
89024 MEKPC, PC Card Modem Evaluation Kit for 89024 ............................ .
89151 T-Link Communications Controller .......................................... .
89C024XE High Performance 2400 BPS Intelligent Modem Chip Set ................... .
An 82586 Data Link Driver AP-235 ................................................ .
Applications Information 291 OAl2911 Al2912A ........................•.............
Asynchronous and SDLC Communications with the 82530 AP-222 .................... .
Asynchronous Communication with the 8274 Multiple Protocol Serial Controller AP-134 .. .
DeSigning Second-Generation Digital Telephony Systems Using the Intel 2913/2914
Codec/Filter Combochip AP-142 ............................................... .
Designing with the 82510 Asynchronous Serial Controller AP-401 ..................... .
High Performance Driver for 82510 AP-31 O......................................... .
iATC 29C48 Feature Control Combo .............................................. .
iATC 29C53AA Digital Loop Controller ............................................. .
10K 29C53 ISDN Development Kitfor 29C53 ....................................... .
Implementing Ethernet/Cheapernet with the Intel 82586 AP-274 ...................... .
Implementing StarLAN with the Intel 82588 AP-236 ................................. .
iSBC® 186/410 MULTIBUS® II Serial Communications Computer ..................... .
iSBC® 188/56 Advanced Communicating Computer ................................ .
iSBC® 534 Four Channel Communications Expansion Board ......................... .
iSBC® 544 Intelligent Communications Controller ................................... .
iSBC® 548/549 Terminal Controllers .............................................. .
iSBC® 561 SOEMI Controller Board ............................................... .
iSBC® 88/45 Advanced Data Communications Processor Board ...................... .
iSBXTM 351 Serial I/O MULTIMODULETM Board .................................... .
iSBXTM 354 Dual Channel Serial I/O MULTIMODULETM Board ....................... .
ISDN Applications with 29C53 and 80188 AP-400 ................................... .
ISP188 ISDN Software Package for the 80188 ...................................... .
LEK 29C53 Line Card Evaluation Kit ............................................... .
MEK3 Modem Evaluation Kit ..................................................... .
MNP Application Package ....................................................... .
MNP Class 5 Software for the 89C024XE Modem Chip Set ........................... .
6-1
6-19
6-34
6-46
6-67
5-78.
2-26
2-40
2-1
2-150
1-56
1-1
1~120
1-86
1-103
2-80
2-112
3-1
3-33
3-52
1-38
4-1
4-48
4-46
5-50
4-22
1-176
6-85
2-421
2-345
6-88
2-182
2-262
5-5
5-25
5-67
1-256
1-345
8-53
8-10
8-19
8-24
8-33
8-37
8-1
8-42
8-48
5-92
5-53
5-73
4-50
4-44
4-44
Alphanumeric Index (Continued)
OpenNETTM Local Area Network Family
PC53 ISDN Board
~
PC586E CSMAICO LAN Evaluation Board
SLO Interface Specification
Synchronous Communication with the 8274 Multiple Protocol Serial Controller Ap·145
TEK29C53 Terminal Evaluation Kit ...............
o.
Twisted Pair Ethernet Chip Set ..
Using the 8273 SOLC/HOLC Protocol Controller Ap·36 .
Using the 8291A GPIB Talker/Listener Ap·166 .
Using the 8292 GPIB Controller AP·66 ....
Using the Intel 82592 to Integrate a Low·Cost Ethernet Solution into a PC Motherboard
Ap·320 ..
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SBC38632
SBC38634
SBC38638
SBC428
SBC464
SBCS17
SBCS19
SBC534
SBC548
SBC550
SBC5S0
SBCS50
SBC5S2
SBC5S6
SBC569
SBC589
SBC604
SBC608
SBC614
SBC618
SBC655
SBC66lt
SBC8010
SBC80204
SBC8024
SBC8030
SBC8605
SBC8612
SBC8614
SBC8630
SBC8635
SBC86C38
SBC8825
SBC8840
SBC8845
SBC90S
SBCLNKOOI
Intel, Puerto RIco, lac.
Intel Puerto RIco II, Inc.
Product Codea/
Part Numbers
pSBC28616
pSBC300
pSBC301
pSBC302
pSBC304
pSBC307
pSBC314
pSBC322
pSBC324
pSBC337
pSBC341
pSBC386
pSBC386116
pSBC386120
pSBC38621
pSBC38622
pSBC38624
pSBC38628
pSBC38631
pSBC38632
pSBC38634
pSBC38638
pSBC428
pSBC464
pSBCS17
pSBCS19
pSBCS34
pSBCS48
TSBC550
pSBC550
pSBCSSO
pSBCS52
pSBC5S6
pSBCS69
pSBCS89
pSBC604
pSBC608
pSBC614
pSBC618
pSBC6SS
pSBC66lt
pSBC8010
pSBC80204
pSBC8024
pSBC8030
pSBC860S
pSBC8612
pSBC8614
pSBC8630
pSBC8635
pSBC882S
pSBC8840
pSBC884S
pSBC90S
pSBCLNKOOl
Intel S1"",pore, Ltd.
Product Cod../
Part Numbers
sSBC386
sSBC428
sSBCS19
sSBC534
sSBC556
sSBC8024
sSBC8605
sSBC8630
sSBC863S
sSBC86C38
sSBC8825
sSBC8845
Intel Corporatina
Product Cod.. /
Part Numbers
SBCMEM310
SBCMEM312
SBCMEM320
SBCMEM340
SBE96
SBX217
SBX218
SBX270
SBX3lt
SBX328
SBX331
SBX344
SBX3S0
SBX3S1
SBX3S4
SBX488
SBXS86
SCHEMAIJPLD
SCOM
SDKSI
SDK8S
SDK86
SXM217
SXM28612
SXM386
SXMS44
SXMSS2
SXM951
SXM9S5
SYP120
SYP301
SYP302
SYP31090
SYP3lt
SYP3847
SYR286
SYR86
SYS120
SYS310
SYS3lt
T60
TA096
TA252
TA4S2
W140
W280
W40
W80
XNX286DOC
XNX286DOCB
XNXIBASE
XNXIDB
XNXIDESK
XNXIPLAN
XNXIWORD
Intel Puerto RIco, Inc.
Intel Puerto RIco II, I...
Produet Codea/
Part Numbers
Ietel Sinppore, Ltd.
Product Codea/
Part Numbers
pSBCMEM310
pSBCMEM312
pSBCMEM320
pSBCMEM340
pSBE96
pSBX217
pSBX218
pSBX270
pSBX3lt
pSBX328
pSBX33I
pSBX344
pSBX3S0
pSBX3S1
pSBX3S4
pSBX488
sSBXS86
pSCHEMAIIPLD
pSCOM
pSDKSl
pSDK8S
pSDK86
pSXM217
pSXM28612
pSXM386
pSXMS44
pSXMS52
pSXM951
pSXM95S
pSYP120
pSYP301
pSYP302
pSYP31090
pSYP3lt
pSYP3847
pSYR286
pSYR86
pSYS120
pSYS310
pSYS3lt
pT60
pTA096
pTA252
pTA452
pW140
pW280
pW40
pW80
pXNX286DOC
pXNX286DOCB
pXNXIBASE
pXNXIDB
pXNXIDESK
pXNXIPLAN
pXNXIWORD
CG/PCPN/l02488
Any of the following products may appear in this publication. If so, it must be noted that
such products have counterparts manufactured by Intel Puerto Ricp, Inc.', Intel Puerto
Rico II; Inc., and/or Intel Singapore,. Ltd. The Pnxiuct codes/part numbers of, these
counterpart produ,cts are listed 'below next to the corresponding Intel C'--:::-'::?'-:::::,,---r--r--I (STATUS)
EL
2
CMD=6
I--~~~_-L~~~~~~~~~~~~~~~~~~~-L--~-I(COMMAND)
~
~
LINK
______________
_ OFFSET
______________
~4
BUFFER
OFFSET
_________________
___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~6
231246-18
Figure 18. The DUMP Command Block
1-21
82586
Bytes 14H to 17H: Content of the Transmit CRC
generator. TXCRCRO is the' least significant byte.
The contents are dependent on the activity before
the DUMP cbmmand:
15 14
13 12
11 10
•
•
7
6
'LLLlLLLLLLLLLL
2
1
0
42
CUR"AB SIZE
46
After MC-SETUP commahd - GenEi'rated CRC value
of the last MC address, On MC-L1ST.
'0'Q<;l
NOTE:
For 16-bft CRC only TXCRCRO and TXCRCR1 are
valid.
3
44
After successful transmission - 'All Zeros'.
After unsuccessful transrnission, depends on where
it stopped.
..
NXT AS ADA (LOW)
E~
After RESET - 'All Ones.'
5
NXT All ADA (HIGH)
LA ABO ADA
48
NXT'A80AOA
4.
CUAABOADA
4C
CUA RB ESC
4£
NXT FD ADA
SO
CUA FD ADA
52
TEMPORARY
54
NXTTB CNT
56
SUF AOR
58
NXl T8 ADR
5.
NXTTBDADR
5C
5.
LA TBD ADA
£l
S
i
JIilllllll.llllI I I Illl
~~~: <~~~
NXt'CB AOR
15 14
13
12
X
XiXI~
~.
~'.
11 10
•
•
FIFO LIM
co,
s.c
1
,
JsLT TM
fU
COTF
1
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1
5
•
1
0
0
6~
..
0'
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MIN
0
0
oI 0
I0
I'co:l ii
FRM
PAlO
:,~INM
04
0
0
0
0
•
06
0
0
0
0
0
oa
0
0
0
0
0
0
•
0
0
0
010
LEN
fAR 0
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0
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O.
I"""
I~
14
rXCReR 3
TXCRCR 2
16
AICACR 1
RICACR 0
18
AXCACR 3
RICRCR 2
110
TEMPR 1
reUPR 0
lC
reMPA 3
TEMPA 2
1£
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rEMPR 4
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1
1
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1
HASHA 1
HASHRO
20
HASHA 3
HASHA 2
26
HASHR'S
HASHR 4
28
HASHR6
210
El
~ X XIX
IX X X X IX X X X X X
0
0
0
0
0' 0
0
0
0
0
0
0
0
0
0
0
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
32
0
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0
0
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0
0
0
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0
0
0
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30
0
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0
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36
1
1
lX
0
0
0
0
0
0
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XX X X
0
0
ELX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
!X X 'X X X X X X
0
0
0
0
0
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NXTRB SIZE
0
0
0
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~
0
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0
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CX FA
0
0
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0
0
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SA
0
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0
0
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0
0
0
0
0
0
0
0
0
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0
0
C/lrtA
•
0
0
°
0
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FIFO
LIM
••
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0
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0
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8C
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0
0
0
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0
aUF ADR PTR '(HIGH)
0
aUf ,lOR
90
.2
PRT (LOW)
RCVDMA8C
OJ 0
1•
01 0
94
•
ADA. H
SA·8UF
10 1°1.
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98
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RCV OMA ADR l
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62
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IAR 3
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LIN
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HASHR 7
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0'
2
SLOT TIME (LOW)
IAR 5,
<0.
3
, , , ,
,
1~1
ioCR
IHI
CRSF
,
tv,.
r:;
INTERFRAME SPACING
NUM
•
000010
~~~. IL~IADOA LEN
RETRY
7
60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
40
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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0
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0
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•
0
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9C
0
0
9E
0
0
AO
0
0
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0
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o
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0
0
0
0
A6
0
0
0
0
'8
0
0
.... ••
231246-20
231246-19
Figure 19. The DUMP Area
1"22
inter
82586
CUR-RB-EBC: Current' Receive Buffer Empty Byte
Count Let N be the currently used Receive Buffer.
Then CUR-RB·EBC indicates the Empty part of the
buffer, i.e. the ACT·COUNT of buffer N is given by
the difference between its SIZE and the CUR·RBEBC.
Bytes 18H to 1BH: Contents of Receive CRC
Checker. RXCRCRO is the least significant byte.
The contents are dependent on the activity per·
formed before the DUMP command:
After RESET· 'All Ones.'
NXT-fD-ADR: Next Frame Descriptor Address. De·
fine N as the last Receive Frame Descriptor with bits
C = 1 and B = 0, then NXT·FD·ADR is the address
of N + 2 Receive Frame Descriptor (with B = C =
0) and is equal to the LlNK·ADDRESSfield, in N + 1
~eceive Frame Descriptor.
After good frame reception1. For CRC·CCln • OIDOFH
2. For CRC-Autodin~1I • C704DD7BH
After Bad Frame reception • corresponds to the reo
ceived information.
CUR-fD-ADR: Current Frame Descrip~or Address.
Similar to next NXT-FD-ADR but refers to N + 1
Receive Frame Descriptor (with B = 1, C = 0).
After reception attempt, i.e. unsuccessful check for
address match, corresponds to the CRC performed
on the frame address.
Bytes 54H to 55H: Temporary regi$ter.
NOTE:
Any frame on the serial link modifies this register
contents.
NXT-TB-CNT: Next Transmit Buffer Count. Let N be
the last transmitted buffer of the TRANSMIT com·
mand executed recently. the NXT·TB·CNT is the
ACT·COUNT field in the Nth Transmit Buffer Descriptor. EOF • Corresponds to the EOF bit of the
Nth Transmit Buffer Descriptor. EOF = '1 indicates
that the last buffer accessed by the 82586 during
Transmit was the last Transmit Buffer in the data
buffer chain associated with the Transmit Com·
mand.
Bytes 1CH to 21H: Temporary Registers.
Bytes 22H to 23H: Receive Status Register. Bits 6,
7,8,10,11 and 13, assume the same meaning as
corresponding bits in the Receive Frame Descriptor
Status field.
Bytes 24H to 2BH: HASH TABLE.
BUF-ADR: Buffer Address. The BUF·PTR field in the
DUMp·STATUS Command Block.
Bytes 2CH to 2DH: Status bits of the last time TOR
command that was performed.
NXT-TB·AD-L: Next Transmit Buffer Address Low.
Let N be the last Transmit Buffer in the transmit buff·
er chain of the TRANSMIT Command performed
recently, then NXT·TB·AD·L are the two least signifi·
cant bytes of the Nth buffer address.
NXT-RB-SIZE: Let N be the last buffer of the last
received frame, then NXT·RB·SIZE is the number of
bytes of available. in the N + 1 buffer. EL· The EL
bit of the Receive Buffer Descriptor.
LA-TB-ADR: Look Ahead Transmit Buffer Descrip·
tor Address. Let N be the last Transmit Buffer in the
transmit buffer chain of the TRANSMIT Command
performed recently, then LA·TBD·ADR is the NEXT·
BD·ADDRESS field of the Nth Buffer Descriptor.
NXT-RB-ADR: Let N be the last Receive Buffer,
used, then NXT·RB·ADR is the BUFFER·ADDRESS
field in the N + 1 Receive·Buffer Descriptor, i.e. the
pointer to the N + 1 Receive Buffer.
CUR-!:IB-5IZE: The number of bytes in the last buff·
er of the last received frame. EL • The EL bit of the
last buffer in the last received frame.
NXT-TBD-ADR: Next Transmit Buffer Descriptor
Address. Similar in function to LA-TBD·ADR but. reo
lated to Transmit Buffer Descriptor N·1. Actually, it is
the address of Transmit Buffer Descriptor N..
.
LA-RBD-ADR: Look Ahead Buffer Descriptor, i.e.
the pointer to N + 2 Receiver Buffer DeSCriptor.
Bytes 60H, 61H: This is a copy of the 2nd wotd in
the DUMP·STATUS command presently executing.
NXT-RBD-ADR: Next Receive BiJffer Descriptor Ad·
dress. Similar to LA·RBD·ADR but points to N + 1
Receive Buffer Descriptor:'
NXT-CB-ADR: Next Command Block Address. -The
LINK·ADDRESS field in the DUMP, Command Block
p~esently executing. Points to the 'next command.
CUR-RBD-ADR: Current Receive Buffer Descriptor
Address. Similar to LA·RBD·ADR, but point to Nth
Receive Buffer Descriptor.
CUR-CB-ADR: Current Command Block Address.
The address of the DUMP Command Block currently
executing.
1·23
82586
SCB·ADR: Offset of the System Control Block
(SCB).
Bytes 7EH. 7FH:
RU·SUS·RQ (Bit 4) • Receive Unit Suspend Re·
quest.
Bytes 80H, 81H:
CU·SUS·RQ (Bit 4) • Command Unit Suspend Re·
quest.
'
,
END·OF·CBL (Bit 5) • End of Command Block List. If
"1" indicates that DUMp·STATUS is the last com·
mand in the command chain.
ABRT·IN·PROG (Bit 6) • Command Unit Abort Re·
quest.
1. If AL·LOCation = 0 then RCV·DMA·BC = (2
tImes ADDR·LEN plus 2) if the next Receive
Frame Descriptor has already been fetched.
2. If AL·LOCation = 1 thEm it contains the size of
the next Receive Buffer.
BR+BUF-PTR+96H· Sum of Base Address plus
BUF - PTR field and 96H.
RCV·DMA·ADR • Receive DMA ab~oh;lte Address.
This is the next RCV·DMA start address. The value
depends on AL.LOCation configuration bit.
1. If AL·LOCation = 0, then RCV·DMA·ADR is the
Destination Address field located in the next Re·
ceive Frame Descriptor.
2. If AL·LOCation = 1, then RCV·DMA·ADR is the
next Receive Data Buffer Address.
The following nomenclature has been used in the
DUMP table:
'
RU·SUS·FD (Bit 12) • Receive Unit Suspend Frame
Descriptor Bit. Assume N is the Receive Frame,De·
scriptor used recently, then RU·SUS·FD is equiva·
lent to the S bit of N + 1 Receive Frame Descriptor.
o
• The 82586 writes zero in this location.
1
X
• The 82586 writes one in this location.
• The 82586 writes zero or one in this
location.
• The '82586 copies this location from the
corresponding position in the memory
structure.
III
Bytes 82H, 83H:
RU·SUS (Bit 4) • Receive Unit in SUSPENDED state.
RU·NRSRC (Bit 5) • Receive Unit in NO RESOURC·
ES state.
DIAGNOSE
RU·RDY (Bit 6) • Receive Unit in READY state.
The DIAGNOSE Command triggers an internal self
test procedure of backoff related registers and coun·
ters.
RU·IDL (Bit 7) • Receive Unit in IDLE state.
RNR (Bit 12) • RNR Interrupt in Service bit.
CNA (Bit 13) • CNA Interrupt iri Service bit.
The DIAGNOSE command includes the following:'
STATUS word (written by 82586):
C
B
FR (Bit 14) • FR Interrupt in Service bit.
CX (Bit 15) • CX Interrupt in Service bit.
OK
'FAIL
(Bit 15)
(Bit 14)
(Bit 13)
(Bit 11)
Bytes 90H to 93H:
BUF·ADR·PTR • Buffer pointer is the absolute ad·
dress of the bytes following the DUMP Command
block.
• Command Completed
• Busy Executing
Command
• Error Free Completion
• Indicates that the Self
Test Procedured Failed
COMMAND word:
Bytes 94H to 95H:
RCV·DMA·BC • Receive DMA Byte Count. This field
contains number of bytes to be transferred during
the next Receive DMA operation. The value de·
pends on AL·LOCation configuration bit.
EL
S
(Bit 15)
(Bit 14)
I
(Bit 13)
CMD
(Blts 0-2)
• End of Command List
• Suspend After
'Completion
• Interrupt After
Completion
• DIAGNOSE = 7
LINK OFFSET: Address of next Command Block.
1·24
inter
82586
15
C
B
o
OK
1--t-+-+--7~".,...o;'?'""-:7"-::::O'"'"'::""'-:'?'""-:7"-::::o'"'"':::r--:7"-::::O'"'"'::""'-"'--'--; (STATUS)
EL
CMD=7
S
~
.....::......::;.....:::;.......:::.....::::.-.::;..&_-L_...L.-I (COMMAND)
1---'_-L.._.Jo::::.....::::.-.:::....::::;.......::~::......::;,.....:;;
LINK OFFSET
231246-21
Figure 20. The DIAGNOSE Command Block
TO
COMMAND
BLOCK
LIST
h
RECEIVE FRAME AREA
RECEIVE
FRAME
DESCRIPTORS
RECEIVE
BUFFER
DESCRIPTORS
RECEIVE
BUFFERS
BUFFER 1
•-
BUFFER 2
RECEIVE FRAME LIST
I
BUFFER 4
BUFFER 3
•
-.11••- - -
BUFFER 5
FREE FRAME LIST
I
231246-22
Figure 21. The Receive Frame Are.a
RECEIVE FRAME AREA (RFA)
FRAME DESCRIPTOR (FD) FORMAT
The Receive Frame Area, RFA, is prepared by the
host CPU, data is placed into the RFA by the 82586
as frames are received. ~FA consists of a list o,f
Receive Frame Descriptors (FD), eacl:'l of which is
associated with a frame. RFA-OFFSJ;:T field of SCB
points to the first FD of the chain; the last FD is
identified by the End-of-Listing flag (EL). See Figure
21.
.
The FD includes the following fields:
STATUS word (set by the 82586):
1-25
C
(Bit 15)
B
(Bit 14)
• Completed Storing
Frame.
• FD. was Consumed by
RU.
inter
82586
LINK OFFSET
RBD-OFFSET
2ND BVTE
1ST BYTE
DESTINATION ADDRESS
MC
8
10
NTH BVTE
12
2ND BVTE
1ST BVTE
14
SOURCE ADDRESS
16
NTH BVTE
18
2ND BVTE
LENGTH FIELD
1ST BYTE
20
231246-23
Figure 22. The frame Descriptor (FD) Format
OK
(Bit 13)
511
(Bit 11)
510
(Bit 10)
59
(Bit 9)
58
57
56
• Frame received
successfully. If this bit is
set, then all others ,will be
reset; if it is reset, then
the other bits will indicate
the nature of the error.
• Received F.rame
Experienced CRC Error.
• Received Frame
Experienced an
Alignment Error.
• RU ran out of resources
during reception of this
frame.
• RCV-DMA Overrun.
• Received frame had
fewer bits than
configured Minimum
Frame Length.
• No EOF flag <;Ietected
(only when configured to
(Bit 8)
(Bit 7)
(Bit 6)
Bits~uffing).
COMMAND word:
EL
5
(Bit 15)
(Bit 14)
""
; Last FD in the Ust.,
• RU should be suspended
after receiving this frame.
LINK OfFSET: Address of next FD in list.
RBD-OFFSET: (initially prepared by the CPU and lat-,
er may be updated by 82586): Address of the first,
RBD that represents the Information Field. RBDOFFSET = OFFFFH means there is no Information'
Field.
DESTINATION ADDRESS (written by 82586):
Contains Destination Address of received frame.
The length in bytes, it is determined by the Address'
Length configuration parameter.
SOURCE ADDRESS (written by 82586): Contains
Source Address of received frame. Its length is the
. same as DESTINATION ADDRESS.
LENGTH FIELD (written by 82586): Contains the 2
byte Length or Type Field of received frame.
RECEIVE BUFFER DESCAI'PTOR
FORMAT
The Receive Buffer' DeSCriptor (RBD) holds information about a buffer; size and location, and the means
for forming a chain of RBDs', (forward pointar and
e'nd-of-frame indication).
The Buffer Descriptor contains the following fields.
inter
82586
lS
o
•
EOF
o
ACT COUNT
-L----I.--'---1 (STATUS)
NEXT BD OFFSET
BUFFER ADDRESS
4
A23
SIZE
231;146-24
Figure 23. The Receive Buffer Descriptor (RBD) Format
BUFFER ADDRESS: 24-bit absolute address of
buffer.
STATUS word (written by the 82586).
EOF
(Bit 15)
F
(Bit 14)
ACT
(Bits 0-13)
COUNT
• Last buffer in received
frame.
• ACT COUNT field is valid.
• Number of bytes in the
buffer that are actually
occupied.
EL/SIZE:
EL
SIZE
NEXT RBD OFFSET: Address of next BO in list of
BO's.
1-27
(BIT 15)
(Bits 0-13)
• Last BO in list.
• Number of bytes the
buffer is capable of
holding.
inter
82586
·Notice: Stresses above those listed under ':4bsolute Maximum Ratings" may cause perma(lent damage to the device. This is a stress rating only and
.functional operation of ,the device at these or any
other conditions above those indicated in the opera. 'tiona! sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ....•. O"C to 70·C
Storage Temperature ....... '...... -65·C to 150'C
Voltage on Any Pin with .
Respect to Ground .............. -1.0V to + 7V
Power Dissipation ...................... 3.0 Watts
D.C. CHARACTERISTICS
TA = O·C to 70·C, Te = O·C to 105·C, Vee = 5V ±10%, CLK has MOS levels (See VMIL, VMIH, VMOL,
VMOH). TxO and RXO' have 82C501 compatible levels (YMIL, VTIH, VRIH). All other signals have TTL levels (see
VIL, VIH, VOL, OH)·
Symbol
Parameter
' Min
Max
Units
Test Conditions
VIL
Input Low Voltage (TTL)
-0.5
+0.8
V
VIH
Input High Voltage (TTL)
2.0
Vee + 0.5
V
VOL
Output Low Voltage (TTL)
0.45
V
IOL
VOH
Output High Voltage (TTL)
2.4
V
IOH - 400 p.A
VMIL
Input Low Voltage (MOS)
-0.5
0.6
V
VMIH
Input Hig\l Voltage (MOS)
3.9
Vee + 0.5
V
VTIH
Input High Voltage ~)
3.3
Vee + 0.5
V
VRIH
Input High Voltage (Axe)
3.0
Vee + 0.5
V
VMOL
Output Low Voltage (MOS)
0.45
V
IOL2.5mA
VMOH
Output High Voltage (MOS)
V
IOH - 400 p.A
Vee - 0.5
= 2.5~A
ILl
Input Leakage Current
±10
jJ.A
o S; VIN S; Vee
ILO
Output Leakage Current
±10
p.A
0.45
= 1 MHz
= 1 MHz
TA = O·C
TA = 70·C
CIN
Capacitance of Input Buffer
10
pF
COUT
Capacitance of Output Buffer
20
pF
Icc
Power Supply Current
550
450
mA
1-28
FC
FC
S;
VOUT
S;
Vee
82586
SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS
T A = DoC to 70°C, Te = DoC to 105°C, Vee = 5V ± 10%. Figures 24 and
25 define how the measurements
should be done.
INPUT AND OUTPUT WAVEFORMS FOR A.C. TESTS
Z . 4 = X :1.5 - - TEST POINTS - - 1 . 5
0.45
x==
231246-25
AC Testing Inputs are Driven at 2.4V for a Logic 1 and 0.45 for a Logic O. Timing measurements are made at 1.5V for both a Logic 1 and 0
Figure 24. TTL Input/Output Voltage Levels for Timing Measurements
231246-26
MOS I/O measurements are taken at 0.1 and 0.9 of the voltage swing
Figure 25. System Clock CMOS Input Voltage Levels for Timing Measurements
1-29
82586
INPUT TIMING REQUIREMENTS'
Symbol
Parameter
82586-6
(6 MHz)
82586
(8 MHz)
82586-10
(10 MHz)
Comments
Min
Max
Min
Max
Min
T1
ClK Cycle Period
166
2000
125
2000
100
200
T2
ClK low Time at 1.5V
73
1000
55
1000
44
1000
T3
ClK low Time at 0.9V
42.5
1000
42.5
1000
T4
ClK High Time at i.5V
T5
ClK High Time at 3.6V
T6
ClK Rise Time
15
15
12
Note 1
T7
ClKFaliTime
15
15
12
Note 2
T8
Data in Setup Time
73
20
55
44
42.5
42.5,
20
15
Max
T9
Data in Hold Time
10
10
10
T10
Async ROY Active Setup Time
20
20
15
Note 3
T11
Async ROY Inactive Setup Time
35
35
25
Note 3
T12
Async ROY Hold Time
15
15
15
Note 3
T13
Synchronous Ready/Active Setup
35
35
35
T14
Synchronous Ready Hold Time
0
0
0
T15
HlDA Setup Time
20
20
20
Note 3
T16
HlDA Hold Time
10
10
5
Note 3
Ti7
Reset Setup Time
20
20
20
Note 3
TiS
Reset Hold Time
10
10
10
Note 3
T19
CA Pulse Width
1 T1
1 T1
1 T1
T20
CA Setup Time
20
20
20
Note 3
T21
CAHoldTime
10
10
10
Note 3
OUTPUT TIMINGS"
Symbol
Parameter
Min
Max
Min
Max
Min
Max
44
T22
DT fR Valid Delay
0
60
0
60
0
T23
WR, DEN Active Delay
0
70
0
70
0
56
T24
WR, DEN Inactive D'elay
10
65
10
65
10
45
Comments
T25
Int. Active Delay
0
85
0
85
0
70
Note 4
T26
Int. Inactive Delay
0
85
0
85
0
70
Note 4
T27
Hold Active Delay
0
85
0
85
0
70
Note 4
T28
Hold Inactive Delay
0
85
0
85
0
70
Note 4
T29
Address Valid Delay
0
55
0
55
0
50
T30
Address Float Delay
0
50
0
50
12
50
T3i
Data Valid Delay
0
55
0
55
0
50
T32
Data Hold Time
0
T33
Status Active Delay
10
0
1·30
60
10
0
60
10
45
Note 7
82588
OUTPUT TIMINGS·· (Continued)
Symbol
82582-6
(6 MHz)
Parameter
Min
82586-10
(10 MHz)
82586
(8 MHz)
Max
Min
Max
Min
Comments
Max
T34
Status Inactive Delay
10
70
10
70
10
50
Note 8
T35
ALE Active Delay
0
45
0
45
0
35
Note 5
T36
ALE Inactive Delay
0
45
0
45
0
37
Note 5
T37
ALE Width
T38
. T2-10
T2-10
T2-10
Address Valid to ALE Low
T2-40
T2-30
T2-25
T39
Address Hold to ALE Inactive
T4-10
T4-10
T4-10
T40
RD Active Delay
10
95
10
95
10
95
T41
RD Inactive Delay
10
70
10
70
10
70
T42
RDWidth
2T1-50
2T1-50
2T1-46
T43
Address Float to RD Active
10
10
0
T44
RD Inactive to Address Active
T1-40
T1-40
T1-34
T45
WRWidth
2T1-40
2T1-40
2T1-34
T46
Data Hold After WR
T2-25
T47
Control Inactive After Reset
0
T2-25
60
Note 5
T2-25
0
60
0
60
Note 6
• All units are In ns.
··CL on all outputs is 20-200 pF unless otherwise specified.
NOTES:
1. 1.0V to 3.5V
2. 3.5V to 1.0V
3. To guarantee recognition at next clock
4.CL = 50pF
5. CL = 100 pF
6. Affects:
MIN MODE: Rl5, iNA. DTIA. DEN
MAX MODE: SO, S1
7. High address lines (A16-A24, BHE) become valid one
clock before T1 only on first memory cycle after the 82586
aC
3.3V ..;
3.0V . -
/
\
G.IIV,....-
a.lv
~-~
I--T52 ....
T.......
-
---- -
1\
-T51--
----
I~
---
~ T50
231246-35
Figure 34. TxC Input Voltage Levels for Timing Measurements
3.GY
~
HIGH LEVELS MAY VARY
WITH Vee
1 - - - - T84 ---o-t
,----"\
1- ___ -1.
I
,-
I-
,
2.7V -
Tee
231246-36
Figure 35. RxC Input Voltage Levels for Timing Measurements
1-36
82586
1m
~----~+-t-+-------+i--------~+-
231246-37
m-----
eTa--------- h.,4
eJI!-----"""
T76
-~------
231246-38
Figure 36. Transmit and Control and Data Timing
RoD
231246-39
Figure 37. RxD Timing Relative to RxC
231246-40
Figure 38. CRS Timing Relative to RxC
1-37
·nter
~OO~1l0IMJOOO~
I
82C501AD ETHERNET SERIAL INTERFACE
...... .
Rep!acement for Intel 82C501,
10
Transmit Clock Generator
• CHMOS
• Drlves/Recelves,802.3"AUI
82501 or SEEQ 8023A
• Defeatable ,Watchdog TimerCables
Conforms to IEEE 802.3 10BASE5
Circuit to
• (Ethernet)
and 10BASE2 (Cheapernat)
•
Prevent Cont,huous '
Specifications
. Diagnostic Loopback for Network Node
Direct Interface to the Intel LAN
•
Fault Detection and Isolation
• Controller
and the Attachment Unit
Replaces 8 to 12 MSI Components
Interface (Transceiver) Cable
•
10 Mbps Operation
• Manchester
and
• Receive ClockEncoding/Decoding
Recovery
MH~
The 82C501AD Ethernet Serial Interface (ESI) chip is designed to work directly with the Intel LAN Controller in
IEEE 802.3 (10BASE5 and 10BASE2), 10 Mbps, Local Area Network applications. The major functions of the
82C501AD are to generate the 10 MHz transmit clock for the Intel LAN Controller, perform Manchester
encoding/decoding of the transmitted/received frames, and provide the electrical interface to the Ethernet
transceiver cable (AUI). Diagnostic loopback control enables the 82C501AD to route the signal to be transmitted from the Intel LAN Controller through its Manchester encoding and decoding circuitry and back to the Intel
LAN Controller. The combined loopback capabilities of the Intel LAN Controller and 82C501AD result in highly
effective fault detection and isolation through sequential testing of the communications interface. A (defeatable) on-chip watchdog timer circuit prevents the station from locking up in a continuous transmit mode. The
82C501AD is pin compatible with the 82C501 and functionally compatible with the 82501 and SEEa 8023A.
Vee
GND
r
COWSlO....
PAUENCE
_RATION
INmI.
L
--
,,
,,
\
XCVRCABLE
INTERFACe.
NOISE FIUER
-,
,CLIIN
,,
,_/
"
CARRIER-PRESENCE GENERATION
I
IWICIIESfElI
DECODER AND
CLOCk
RXD
~' INTERFACE
lO:YIICAeLE
AND
,,RCY
,
(
NOtSEFIlJ'ER
RECOVERY •
I
/'-"",
',-/
-lcoutmR
CLOCk
GENERATION
MANCHESTER
ENCOOIR
TAANlCEtVER
CABLE DRIVER
~ tJi:
CRYSTAL
X,
, --, ,TRMT
,,
TXD
t-----
\,
r~
WATCHDOG TIMER
-- ,I
ENffii
NOOii
LPBK/WDTD
RCV
Rev
CRS
vee
TRMT
TRMT
TXD
TXC
TEN
XI
3
8
RXC
X2
RXD
GND
CLSN
CLIN
11
231926-2
Figure 2. Pin Configuration
I
231926-1
Figure 1. 82C501AD Functional Block Diagram
1-38
November 1988
Order Number: 231928-004
inter
82C501AD ETHERNET
Table 1. Pin Description
Symbol
Pin
No.
Type
Name and Function
ENETV1
1
I
ETHERNET VERSION 1.0: An active low, MOS-Ievel input. When ENETV1 is
asserted, the TRMTITRMT pair remains at high differential voltage at the
and of transmission, This operation is compatible with the Ethernet Version
1.0 specification. If the ENETV1 pin is left floating, an internal pull-up resistor
biases the input inactive high. When ENETV1 is high, the TRMTITRMT
differential voltage gradually approaches OV at the end of transmission.
NOOR
2
I
CRS 'OR': An active low, MOS-level inpu When ~ is low, only the
presence of a valid signal on the RCV IR V pair will force CRS active. If the
NOOR pin is floating, an internal pull-up resistor biases the input inactive
high. When NOOR is in active high, either the presence of a valid signal on
CLSN/CLSN or on RCV IRCV will force CRS active.
LPBKI
WDTD
3
I
LOOPBACK/WATCHDOG TIMER DISABLE: An active low, TTL-level
control signal that enables the loopback mode. In loopback mode serial data
on the TXD input is routed through the 82C501AD internal circuits and back
to the RXD output without driving the TRMT ITRMT output pair to the
transceiver cable. During loopback CDT is asserted at the end"of each
transmission to simulate the SQE test.
WATCHDOG TIMER DISABLE: An input voltage of 10V to 16V through a
1 KO resistor will disable the on-chip watchdog timer.
RCV
RCV
4
5
I
I
RECEIVE PAIR: A differentially driven input pair which is tied to the receive
pair' of the Ethernet transceiver cable. The first transition on RCV will be
negative-going to indicate the beginning of a frame. The last transition should
. be positive-going to indicate the end of the frame. The received bit stream is
assumed to be Manchester encoded.
CRS
6
0
CARRIER SENSE: An active low, MOS-Ievel output to notify the Intel LAN
Controller that there is activi~ the coaxial cable. The signal is asserted
when a valid signal on RCV IRCV is present. If the NOOR input is inactive
high, then CRS is also asserted when a valid Signal on CLSN/CLSN is
present. It is deasserted at the end of a frame: or when the end of the
collision-presence signal is detected, synchronous to RXC. After
transmission, once deasserted, CRS will not be reasserted again for a period
of 5 ""S minimum or 7 ""S maximum, regardless of any activity on the collisionpresence signal (CLSN/CLSN) and RCV/RCV inputs.
CDT
7
0
COLLISION DETECT: An active-low, MOS-Ievel signal which drives the CDT
input of the Intel LAN Controller. It is asserted as long as there is activity on
the collision pair (CLSN/CLSN), and during SQE (heartbeat) test in loopback.
RXC
8
0
RECEIVE CLOCK: A 10M Hz MOS level clock output with 5 ns rise and fall
times. This output is connected to the Intel LAN Controller receive clock
input RXC. There is a maximum 1.4 ""s delay at the beginning of a frame
reception before the clock recovery circuit gains lock. During idle (no
incoming frames) RXC is forced low.
.
RXD
9
0
RECEIVE OATA: A MOS-Ievel output tied directly to the RXD input of the
Intel LAN Controller and sampled by the Intel LAN Controller at the negative
edge of RXC. The bit stream received from the transceiver cable is
Manchester decoded prior to being transferred to the controller. This output
remains high during idle.
,
a
1·39
82C501AD ETHERNET
Table 1. Pin Description (Continued)
Symbol
Pin
No.
GND
10
CLSN
CLSN
12
11
I
I
COLLISION PAIR: .i\differentially driven input pair tied to the collisionpresence pair of the Ethernet transceiver cable. The collision-presence
signal is a 10 MHz square wave. The first transition at CLSN is negativegoing to indicate the beginning of the signal; the last transition is positivegoing to indicate the end of the signal.
X1
X2
14
13
I
I
CLOCK CRYSTAL: 20 MHz crystal inputs. When X2 is floated, X1 can be
used as an external MOS level input clock.
TEN
15
I
TRANSMIT ENABLE: An active low, TIL level signal synchronous to TXC
that enables data transmission to the transceiver cable and starts the
watchdog timer. TEN can be driven by the RTS from the Intel LAN Controller.
TXC
16
0
TRANSMIT CLOCK: A 10 MHz MOS level clock output with 5 ns rise and fall
times. This clock is connected directly to the TXC input of the Intel LAN
Controller.
TXD
17
I
TRANSMIT DATA: A TTL-level input signal that is directly connected to the
serial data output, TXD, of the Intel LAN Controller.
TRMT
TRMT
19
18
0
0
TRANSMIT PAIR: A differential output driver pair that drives the transmit pair
of the transceiver cable. The output bit stream is Manchester encoded.
Following the. last transmission, which is always positive at TRMT, the
differential voltage is slowly reduced to zero volts in a series of steps. If
ENETV1 is asserted this voltage stepp.ing is disabled.
Vee
20
Type
Name and Function
GROUND: Reference.
POWER: 5V ± 10%.
2. Crystek Corporation
100 Crystal Drive
Ft Myers, FL 33907
FUNCTIONAL DESCRIPTION
Clock Generation
For best operation, the total crystal load capacitance
should not exceed 20 pF. The total length of the line
on each side of the crystal (between X1 and X2, the
crystal, and the capacitor) should be less than
2.5 cm.
A 20 MHz parallel resonant crystal is used to control
the clock generation oscillator which provides the
basic 20 MHz clock source. An internal divide-bytwo counter generates the 10 MHz ± 0.01 % clock
required by the IEEE 802.3 specification.
An external, 20 MHz, MOS-Ievel clock may be applied to pin X1 while pin X2 is left floating.
It is recommended that a crystal meeting the foll()wing specifications be used:
• Quartz Crystal
• 20.00 MHz ± 0.002%
@
TRANSMIT SECTION
25°C
• Accuracy ± 0.005% Over Full Operating Temperature, 0 to 70°C
Manchester Encoder and Transceiver
Cable Driver
• Parallel resonant with 20 pF Load Fundamental
Mode
The 20 MHz clock is used to Manchester encode
data on the TXD input line. The clock is also divided
by two to produce the 10 MHz clock required by the
Several vendors have these crystals available; either
off the shelf or custom made. Two possible vendors
are:
1. M-Tron Industries, Inc
Yankton, SD 57078
1-40
82C501AD ETHERNET
20 MHz INTERNAL CLOCK
"0"
TXD
-_. __ ..',
"0"
"1"
"0"
TRMT
(MANCHESTER-ENCODED DATA)
231926-3
Figure 3. Start of Transmission and Manchester Encoding
If an active signal is present at the ENETV1 input at
the end of transmission, the TRMTITRMT pair output will remain a high differential Voltage. As a result
there will be a positive differential voltage during the
entire transmit idle time. This mode of operation is
compatible with the Ethernet Version 1.0 specification.
Intel LAN Controller for synchronizing its RTS and
TXD signals. See Figure 3. (Note that the 82586
RTS is tied to the 82C501AD TEN input as shown in
Figure 4.)
Data encoding and transmission begins with TEN
going low. Since the first bit is a '1', the first transition on the transmit output TRMT is always negative. Transmission ends with the TEN going high.
The last transition is always poisitve at TRMT and
may occUr at the center of the bit cell (last b.it = 1)
or at the boundary of the bit cell (last bit = 0). A
1.5-bit delay is introduced by the 82C501 AD between its TXD input and TRMTITRMT output as
shown in Figure 3. If the signal applied to the
ENETV1 input is inactive high, the TRMT differential
output is kept at high differential for 200 ns, then it is
gradually reduced. The TRMTITRMT differential
voltage will become less than 40 mV within 8 ,...s
after the last data transition. The undershoot for return to idle is less than 100 mV differentially. This
mode of operation is compatible with the IEEE 802.3
transceiver specifications. See Figure 4.
Immediately after the end of a transmission all signals on the receive pair are inhibited for 5 ,...S minimum to 7 ,...s maximum. This dead time is required
for proper operation of the SOE (heartbeat) test.
An internal watchdog timer is started when TEN is
asserted low at the beginning of the frame. The duration of the watchdog timer is 25 ms ± 15%. If the
transmission terminates (by deasserting the TEN)
before the timer expires, the timer is reset (and
ready for the next transmission). If the timer expires
before the transmission ends the frame is aborted.
The frame is aborted by disabling the output driver
for the TRMT ITRMT pair. RXD and RXC are not
affected. The watchdog timer is reset only when the
TEN is deasserted.
1-41
82C501AD ETHERNET
The cable driver is a differential circuit requiring external pulldown resistors of 2400 ± 5%. In addition,
high-voltage protection of + 10V maximum, and
short circuit protection to ground is provided. .
RECEIVE SECTION
Cable Interface
To provide additional high voltage protection if the
cable is shorted, an isolation transformer can be
used to isolate the TRMT and TRMT outputs from
the transceiver cable. Transmit circuit inductance
(including the IEEE .802.3 transceiver transformers) "
should be a minimum of 27
We recommend that
the transformer at the 82C501 AD end have a minimum inductance of 75 ,...H for Ethernet applications.
,...H.
The 82C501 AD input circuits' can be driven directly.
from the Ethernet transceiver cable receive pair. In
this case the cable is terminated with a resistor of
780 ± 6% for proper impedance match.ing. See Figure 4.
The,signal received on the RCV/ReV pair from the
transceiver defines both the RXC and RXD outputs
to the Intel LAN Controller. The RXC and RXD signals are recovered from the encoded RCV /RCV ,pair
signal by Manchester decode circuitry.
+5V OV
_vee GND
TXC
TXC
RTS
TXD
'mi'
TRt.lT
·TXD
ENETVI
CTS
NOoR
RxC
CRS
RxD
COT
TRt.lT
240.0.
19
18
240.0.
RxC
CRS
9
RxD
7 Cfj'f
RCV
T
r
a
4
n
s
c
INTEL
t
•
•I a
v
c
• •
LAN
82C501
ESI
CONTROLLER
I
II
78.0.
LOOP B A C K - - - - -......
INPUT FROt.l PROCESSOR
20t.lHZ
Cl~
COLLISION PAIR
C2~
231926-4
NOTE:
Cl = C2 = 20 pF ±10%
Figure 4. LAN Controller/82C501AD/Transcelver Interface
1-42
inter
82C501AD ETHERNET
jitter. Slow phase variations, such as those caused
by small differences between the data frequency
and the clock frequency, are passed unfiltered by
the low-pass filter.
The input circuits can also be driven with ECl voltage levels. In either case, the input common mode
voltage must be in the range of O-Vee volts to allow
for wide driver supply variation at the transceiver. To
provide additional high voltage protection, if the cable is shorted, an isolation transformer can be used
to isolate the RCV and RCV inputs from the cable.
The AXe generator digitally sets the phases of the
two transitions to respectively lead and lag the bitcenter transition by 1/4 bit time. RxC is used to recover RxD by sampling the incoming data with an
edge-triggered flip-flop.
Manchester Decoder and Clock
Recovery
The Frame_Detect signal informs the decoder that
the first valid negative transition of a new frame has
been detected. This signal is used to initiate the
lock-on sequence of the decoder. lock is achieved
by reducing the time constant of the digital filter to
zero at the start of a new frame. With a time constant of zero, the filter immediately outputs the
phase of the second bit-center transition. Any uncertainty in the bit-center phase of the first transition
that is caused· by jitter is subsequently removed by
gradually increasing the filter time constant during
the following preamble. By that time, the exact
phase of the bit center is output by the filter, and the
lock is achieved. lock is achieved within the first 14
bit times as seen by the RCV /RCV inputs. The maximum bit-cell timing distortion Qitter) tolerated by the
Manchester Decoder Circuitry is ± 12 ns for the preamble and ± 18 ns for the data.
The Manchester-encoded data stream is decoded to
separate the Receive Clock (RxC) and the Receive
Data (RxD) from the stream. The 82C501 AD uses
an advanced digital technique to perform the decoding function. The use of digital circuitry instead of
analog circuitry (e.g., a phase-lock loop) to perform
the decoding ensures that the decoding function is
less sensitive to variations in operating conditions.
A simplified diagram of the decoder appears in Figure 5. A high-resolution phase reference is used to
digitize the phase of the incoming data bit-center
transition. The digitizer has a phase resolution of
1/32 bit time.
The digitized phase is filtered by a digital low-pass
filter to remove rapid phase variations; Le., phase
10 MHz
HIGH RESOLUTION
D~C::::LO~C::.:K___~
PHASE
REFERENCE
1---------,
MANCHESTER .._..z._-,
ENCODED
DATA
Q
RXD
~----------+-----r~D
FRAME
DETECT-----------t-------J
231926-11
Figure 5. Manchester Decoder
1-43
inter
82C501AD ETHERNET
COLLISION·PRESENCE SECTION
Internal Loopback
The CLSN/CLSN input signal is a 10 MHz ± 15%
square-wave generated by the transceiver whenever
two or more data frames are superimposed on the
coaxial cable. The maximum asymmetry in the
CLSN/CLSN signal is 60/40% for low-to-high or
high-to-Iow levels.
When asserted, LPBKcauses the 82C501 AD to
route serial data from its TXD input through its transmit logic (retiming and Manchester encoding); returning It through the receive logic (Manchester decoding and receive clock generation) to AXD output.
The internal routing prevents the data from paSSing
through the output drivers and onto the transmit output pair TRMTITRMT. When in loopback mode all of
the transmit and receive circuits, are tested except
for the transceiver cable output driver and input receivers. Also, at the end of each frame transmitted
in loopback mode the 82C501AD generates the
SQE test (heartbeat) signal within 1 /ks after the end
of the frame. Thus, the colision Circuits, are also
tested in loopback mode.
The common-mode voltage and external termination
are identical to the RCV /RCV input. (See Figure 4.)
A valid collision presence' signal will assert the
82C501 AD COT output, which can be directly tied to
the COT input of the Intel LAN Controller. During
normal operation the 82C501 AD logically "ORs" the
collision presence signal with an internal signal, indicating valid data reception on the RCV /RCV pair to
generate CRS output. If, however, the NOOR input
is asserted low, this "OR" function is removed and
CRS is only asserted by the presence of valid data
on the RCV/ReV pair. This mode of operation is
required for repeater design.
During the time that valid cOllis~ntresence transitions are present on the CLSN/ L N input, invalid
data transitions maybe present on the receive data
pair due to the superposition of signals from two or
more stations transmitting simultaneously. It is possible for RCVIRCV to lose transitions for a few bit
times due to perfect cancellation of the signals; this
may cause the 82C501 AD to abort the reception.
The watchdog timer remains enabled in loopback
mode, terminating test frames that exceed its timeout period. The watchdog can be inhibited by connecting LPBK to a 1 kn resistor connected to 10 to
16 Volts. The loopback feature can still be used to
test the integrity of the 82C501 AD by using the circuit shown in Figure 6.
10VlO lev
82C501AD
lK
L:Pii
=>
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en
0.
""
en
0
!!!I
0
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DATA
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DACKO/llACK
LOCAL BUS
DACK!/EDP
cs
INTERFACE
I"",
DRQO
...
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CD
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IORO/UWR
DMA MACHINE
KlWR.
3
......... INT
GND
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10
Vee
...--.
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CPU INTERFACE
ill
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UNIT
.--------------------------~-----------------
il
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lOCAL BUS CONTROL
_____ w_____________________
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290180-1
~
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82560
Table
1. 82560 Pin Description
,
"
Symbol
Pin No.
' Type
Name and Function
+ 5V power supply.
Vee
5,23,57
I
Vss
ClK
10,29,43,63
I
GROUND: Ground connection.
11
I
CLOCK INPUT: This is the system clock input for the 82560. It
controls the internal operations of the 8?5~0 and its cycle timing.
RESET
42
I
RESET: Active high. When active it resets the 82560 to a known
passive state.
00-0 7
40,41,44-49
I/O
Ao-A12
26-39
I
ADDRESS LINES: The 13 address lines select either an 82560
register, or an address in the local Memory.
HFO, HF1
25,24
I
HOST FUNCTION SELECT: These two inputs indicate the type of
access requested by the host. These signals are generated by
external decode logic and are completely asynchronous to the
82560 system clock. The proper combinations for each access
type are shown below:
HOST FUNCTION,
H'F1
HFO Access Type
Idle (No Access Being Requested)
1
1
1
Request to Access Shared:Portion of local
0
Memory
Request to Access 82560 Registers or the Slave
0
1
Controller (SCS}
0
0
~esest to Access External PROMs or latches
: POWER: Co"nected to
82560 DATA BUS: Tri-state bus. Used for programmatic access to
the 82560 registers. They are also used in the tightly coupled
interface (TCI) mode.
(
)
RO
17
I
READ: Active low. This signal is used to' indicate the direction of
the host transfer. When active, data is being read from the
destination (RAM, 560, or GCS port).
HROY
20
0
HOST READY: Active high. This Signal from the 82560 is activated
when the device on the local Bus of the LAN adapter is ready to
accept data (write cycle) or to output data (read cycle). When no
access is being requested by the host (I.e., both, HFO and HF1 are
high), this signal is tri-stated in the normal mode, ~nd is driven high
in the pipeline mode.
,
XCV1
22
0
TRANSCEIVER ENABLE 1: Enables the transceiver that connects
the lower byte of the host and local data buses. In pipeline mode it
enables the transceiver during non-memory host cydles.
XCV2/PCS
21
0
TRANSCEIVER ENABLE 2: Enables tl:Je transceiver that connects
the upper,byteof the host and local data buses. In pipeline mode it
enables the latch during memory host cycles.
.
.
INT
50
0,
INTERRUPT OUT: This signal is a I~cal OR of all enabled
interrupt requests. When active it indi'ates an interrupt request to
the CPU. This signal is tristated after reset.
GCS
59
0
GENERAL CHIP SELECT: Active low. This Signal is asserted by
the 82560 when the host requests access:to external ROMs or
"
latches.
1-58
82560
Table 1. 82560 Pin Description (Continued)
Symbol
Pin No.
Type
Name and Function
BEO
18
I
BYTE ENABLE: Active low. This signal is asserted in 16- or 32-bit·
wide host memory cycles to select the lower memory bank. It may be
connected to the processor's Ao pin.
BE1
19
I
~YTE ENABLE 1: Active low. This signal is asserted in 16· or 32-bitwide host memory cycles to select the upper memory bank. It may
be connected to the processor's BHE signal. These two signals are
connected as follows:
H08tBu8
8-Bit
!;I-Bit,
16-Bit
16-Bit
32·Bit*
iEO
LocalBu8
8-Bit
16-Bit
16-Bit
32-Bit
32-Blt
0
SAO
SAO
SA1
BEO
+ BE1
BE1
0
1
SHBE
SA1
BE2 + BE3
*80386 address pins
+ stands for logical OR
DROO
54
I
DMA REQUEST CHANNEL 0: Active high. This is an input from the
LAN controller or other peripherals, it requests DMA service. The
DMA cycles are run on an on-demand basis, and are prioritized
between themselves (two channels) and with the host cycles on an
alternating basis. In 82590 Tightly Coupled mode this signal is
sampled by the 82560 at the last clock of the Read or Write signal
along with DACK1/EOP to determine the state of the transmit or
receive process (see Tightly Coupled Interface for mote details).
DRQ1
52
I
DMA REQUEST CHANNEL 1: Active high. This is an input from the
LAN controller or other peripherals, requesting DMA service. The
DMA cycles are run on an on.demand basis, and are prioritized
between-themselves (two channels) and with the host cycles on an
alternating basis. In Tightly Coupled mode this signal is sampled by
the 82560 at the last clock of the Read or Write signal (see Tightly
Coupled Interface for more details).
DACKO/DACK
55
0
Dual Function: This is a dual function pin which serves as DACKO,
DMA acknowledge for Channel 0, in all modes exceptthe Tightly,
Coupled Interface mode. It serves as DACK, DMA acknowledge for
both channels, in Tightly Coupled Interface mode.
DMA ACKNOWLEDGEO: Active low. Acknowledge DMA requests
on channel O. During special chip select cycles, this signal is
controlled by the CPU.
DMA ACKNOWLEDGE: Active low. Acknowledge DMA requests on
either channel 0, channel 1. It operates in this mode only when
programmed for Tightly Coupled Interface with the 82590 or 82592.
This pin can be directly,qonnected to the DACKO/DACK pin of the
8259q or 82592 LAN i::o~troller:s.
or
DACK1/EOP
53
1/0
Dual Function: This ,is a dual fl,inction, bidirectional pin which serve,s
as DACK1, DMA acknoWledge for channel 1, in all modes except
8259X Tightly Coupled Interface mode. It serves as EOP, End of
Process indicator, an input, during this Tightly Cc;>upled Interface
mode.
DMA ACKNOWLEDGE1: Output. Active low. DMA acknowledge for
channel 1. During Special Chip Select (SCS) cycles this signal is
controlled by the CPU and can be used for accessing the 8259X port
1. The output level is determined by the address of the SCS.
1-59
82560
Table 1.82560 Pin Description (Continued)
Symbol
Pin No.
Type
DAOO/EOP
53
1/0
END.OF PROCESS: Input. In the Tightly Coupled Interface mode,
this input, along with the DRQ pin, is sampled by the 82560 at the
last clock of the Read or Write signal. The combination of the two
pins indicates the status of ~he Transmit.or Receive process. When
low, the EOP signal indicates that the active DMA service should be
terminated. .
Name and Function
IOWR
56
0
I/O WRITE. Active low. This is the write strobe to the LAN controller
or 1/0 device. It is asserted when data is being written to the LAN
controller by either the Host CPU or the 82560 internal DMA. During
pipeline read transfers it is the write control signal to the buffer.
TOFiD/MWR
58
0
Dual Function: Active low. This signal is used for two different
operations. It is a control signal during read cycles from the LAN
controller or another 1/0 device. It is a write strobe during write
cycles to the local memory.
I/O READ: Active,low. It is asserted when data is being read from
the LAN controller by either the host CPU or the 82560 internal DMA.
During pipeline write transfers it is the read control signal to the
buffer.
MEMORY WRITE: Active low. It is asserted when data is being
written to. local.memory.
.
INTR
51
I
INTERRUPT REQUEST: This Signal when active indicates an
interrupt request. It is usually connected to the interrupt output of the
LAN controller..It may be programmed as active high or low, level or
edge triggered, and it can also be masked.
9-1,68
0
MEMORY AD.DRESS 0-12: These 13 address lines can support two
8-kilobyte or 8-kiloword banks of static memory.
esc
62
0
CSH
61
0
RAM CHIP SELECT (HIGH BANK): Active low. This signal is
activated during Odd-bYte accesses in 16-bit mode or odd-word
accesses in 32-bit mode.
MOE
60
Q
MEMORY OUTPU.T ENABLE: Active low. This Signal is used to
, enable the memory array's output buffers during memory read
cycles.
.
.
GPI
16
I
GENERAL PURPOSE: Input. This is a general purpose input pin, its
state may be read by,theCPU.
CS
12
0
CHIP SELECT: Active low. This pin is normally connected to the
Chip Sele~t input of the LAN controller or other peripherals. It is
activated during nOn-DMA accesses to the LAN controller. The CPU
activates this signal when it accesses addresses 0, 1,2, or 3 in the
Special Chip Select address space of the 82560.
13,14
I
These pins are reserve~ ~mj should be tied to Vee.
MAO-12
RSV1, RSV2
RAM CHIP SELECT (LOW BA,NK): Active low. This Signal is
activated during all static-RAM accesses in 8-bit mode, even-byte
. accesses in 16-bitmode, and even-word accesses in 32-bit mode.
1-60
intJ
82560
v••
MOE
CLK
GCS
cs
IORO/MWR
RSVI
Vee
RSV2
IOWR
NC
OACKO/OACK
GPI
OROO
Rii
OACKI/EOP
BEO
OROI
BEl
INTR
HROY
INT
XCV2/PCS
07
XCVI
06
Vee
05
HFI
04
HFO
03
AO
02
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
Sg
c
~ ~
'"
290180-2
Figure 2. 82560 PLCC Pinout
."
A
<
'I
(I)
~
'"
Q
Q
'"
I!:
Z
8
,.---- ------
:I
I
I
I
I
I
I
I
I
I
I
I
Host Bus
....
0
Host Interfoce and
Oecode Logic
1
'
....0
'"0
!z
U
I
. 1 Arbitration
1 Logic
Boot
BOM
I
I
Addre••
ROM
I.
~
Q
Q
'"
Local Bu.
._----------------------I.
1
----~
Data. Add,..... and Control
--------- ----.. --
....
0
I!:
Z
(I)
~
~
8
Q
'"
)
~
<§
Local Buffer
LAN
Controller
Memory
(82590.
82592,
82588)
0=
I
(I)
I
I
I
I
I
Physical
Interlace
Transceiver I
II<
(
I
~
------------------~
OMA
Controlier
(8 to 32 kB)
Integrated In 82560
290180-3
Figure 3. Nonintelligent, Buffered Adapter Architecture
1-61
82560
time-critical processes such as retransmission, buffer reclamation, and continuous back-to-back frame
reception without host CPU intervention. This improves the overall data throughput in the network;
and, consequently, system performance. The following discussion describes the 82560 interface to the
PC/XT 1AT bus, its support of locally buffered memory, and the operation of DMA and the Tightly Coupled Interface (including the buffer management
scheme).
FUNCTIONAL OVERVIEW
The 82560 is a dual-port memory controller using
interrupt logic and DMA to implement a noninteOigent, buffered LAN adapter for the IBM PC/XT/AT
bus.' This type of adapter uses on-board memory as
a buffer to store frames during transmission and reception. It also uses on-board DMA to transfer data
between its local memory and the LAN controller. A
block diagram of the buffered, nonintelligent LAN
adapter is shown in Figure 3. The architecture is
termed nonintelligent because it does not use an onboard CPU to process the transmit or receive
frames. The host CPU processes the frames and
programs the DMA and LAN controllers. The host
interface logic, arbitration logic, and the bus transceivers connect the host bus to the adapter's local
bus. They also control all host accesses to the local
bus. The local memory is shared by the host and the
LAN controller. It stores information that the host
wishes to transfer to the LAN controller, and information received by the LAN controller which should
be read by the host. The memory can be shared in
two ways-mapping into the host memory space, or
mapping into the host 1/0 space. The DMA controller transfers data between the local buffer memory
and the LAN controller. The host CPU may use either string move instructions or a system DMA channel to move data into the buffer memory. The host
also accesses the LAN controller registers, the DMA
controller registers the boot ROM, and the address
ROM through the local bus.
HOST INTERFACE
The host interface port connects the 82560 to the
PC-bus through external decode logic and bus transceivers. The external decode logic generates the
HFO and HF1 signals indicating the kind of access
the host desires. When the request is detected by
the 82560 (non-pipeline mode) it deasserts the
HRDY signal, thereby suspending the host cycle.
HRDY is reactivated when the local device being accessed by the host is ready to accept (Write cycle)
or output (Read cycle) data. HRDY reactivation time
is programmable as mentioned in the register section; it is described in detail in the 82560 Reference
Manual The request undergoes arbitration, and, if
granted, the 82560 activates the XCV1 and XCV2
signals. The XCV signals control the transceiver(s)
which interfaces the host data bus to the local data
bus. By using one or both transceiver control signals
the 82560 can support an 8-, 16-, or 32-bit-wide bus.
Once the arbiter grants the host access, the 82560
begins the local bus cycle by generating the appropriate address and control signals.
The 82560 integrates the host interface, arbitration
logic, memory control logic, interrupt logic, and DMA
into one component. It replaces 20-30 MSI and SSI
components (see Figure 1). It also provides a Tightly
Coupled Interface to the 82588, 82590, and 82592
LAN controllers, and an efficient buffer management
scheme, which allows the 82588/82560, 825901
82560, and 82592/82560 combinations to handle
The host CPU can access the internal registers of
the 82560, the local memory controlled by the
82560, or other devices-such as Boot ROM or external Latch-that share the same bus as the 82560.
Table 2 lists the various access types that can be
requested by the host.
Table 2. Host Access Types
HF1
HFO
Add.ress
Cycle Status Indications
82560 Registers
0
1
Between 8h and 3Fh
HRDY
Local Memory Access
1
0
User Defined
HRDY, Memory Control
Signals, XCV Signals
GCS Access (Boot ROM)
(General Chip Select)
0
0
User Defined
HRDY, ITCS, 10WR,
10RD/MWR
Special Chip Select
0
1
Less Than 8h
HRDY, DACK Lines, CS,
10WR, 10RD/MWR
Access Type
1-62
inter
82560
The 82560 provides eight semaphore ports to resolve contention in a shared resource system. Only
the most significant bit of these ports is used. The
CPU writes all O's to the port to clear it. When the
port is read, its current value is reported and the
most significant bit becomes a 1 at the end of the
cycle. The 82560 also supports devices on the local
bus other than memory and the LAN controller.
These devices can be accessed in two ways: by using the General Chip Select (GCS) signal, or by using the Special Chip Select (SCS) addresses in the
82560 register space. The first method typically supports EPROMs, external latches, and similar devices. The second method is used for accessing the
registers of controllers which use the 82560 DMA
channels; e.g., the 82590, 82592, or 82588. Each
address in the SCS port provides a unique combination of the DACKO-, DACK1-, and CS-pin output
states. The CPU activates the chip select of the device being accessed by asserting or deasserting the
appropriate Signals.
In I/O-mapped Access mode the memory is mapped
into the host I/O address space. Data is transferred
between host and local memory using host DMA or
string I/O instructions. The 82560 can be programmed to support memory accesses through a
single I/O port. The I/O port is defined by an address programmed into an 82560 register. The
82560 maintains the current address, which is updated each time a memory cycle is run. The host
does not directly access the local memory. It outputs
the I/O address onto the AO-A12 address lines,
with the HF lines indicating a memory access. If the
I/O address matches the address programmed into
the 82560, then the 82560 executes the local memory cycle by outputting the current address onto the
memory address lines MAO-12.
The 82560 can be configured to interface with the
host in a pipeline mode. In this mode, transparent or
edge-trigged latches are needed to isolate the host
and local bus during memory cycles. Data is written
to the latch (from the host bus) and copied (from the
latch) to the local memory. In the host read cycles,
data is copied from the latch to the host bus. In anticipation of the next host memory request (sequential), the 82560 then copies the next byte or word
from local memory to the latch. Thus the host CPU
can operate with 0 wait states by reading from and
writing to the latch.
The host CPU can access the 82560 registers and
other devices on the local bus at any time. However,
local memory can only be accessed by the host after
the 82560 memory control registers are initialized.
The host accesses local memory in two ways: Page
Access or Sequential (I/O mapped or pipeline) Access. After reset, the memory access is I/O-mapped
mode but host access to local memory is disabled.
The 82560 must be configured for the appropriate
memory access mode before local memory can be
accessed by the host.
.
ARBITER
All requests for access to devices on the local bus,
whether by the host or by the 82560 DMA, undergo
arbitration. The host requests are indicated on the
HF lines; the DMA requests are indicated on the
ORO lines. Figure 4 shows the basic arbitration cycle of the 82560. Arbitration for the local bus is pipelined. It can take place at any time when the 82560
is idle, or one clock before the end of the current
local bus cycle. All requests are sampled on the failing edge of the 82560 clock. Arbitration is completed
within one clock cycle. The resultant local bus cycle
is started on the falling edge of the next clock. If
more than one request is active, arbitration is resolved on an alternating priority basis.
The 82560 memory control logic provides the signals required to interface to static memory. The
82560 can address up to 32 kB of local memory.
Each memory address can refer to a byte, a word, or
a double word of local memory. Thus the 82560 with
its two memory chip selects (low to high bank) and
its MOE and MWR outputs, can support 8-, 16-, or
32-bit-wide local buses.
In Page Access mode the local memory is mapped
into the host memory space. In this mode the host
can directly access local. memory through a fixed
size window which can be moved around in local
memory space. This window is referred to as a
"page". Figure 5 shows the paging scheme. The
page size can vary from 1 kilobyte to 8. kilowords,
and can be located anywhere in local memory. The
exact location of the page in the local memory is
defined by a page register. By reprogramming the
page register the user can relocate the page in local
memory.
The 82560 deactivates its HRDY line when a host
request is detected; the request is synchronized and
then arbitrated. If the 'request is granted, the appropriate local bus cycle begins.. After a programmable
number of clock cycles HRDY will be reactivated,
and the handsl;take with the host will be complete.
DMA requests are synchronized and acknowledged
once DMA has been granted access to the local
bus. The acknowledge lines are kept inactive until
the DMA is granted access to the local bus.
1-63
intJ
82560
To
To
To
To
OMA~
(ORO)
><. .__ .,.><. .__
CYCLE ===IO=LE===:><....__HO_S_T__
D_MA__
HO_S_T__~
290180-4
This Diagram Assumes:
The default priority bit to be 1 (bit 7 of the master mode)
I/O or MEM wait states to be 1 clock (Tw = 1)
Non-Pipeline Mode
In the case of host read cycles (in any mode) or host write cycles (in pipeline mode only), "Twh" cycles
will be asserted in addition to "Tw", between "T1" and "T2" of the host cycles
Figure 4. 82560 Arbitration Cycles
Shored
.' Memory
Page
Adopter's
Locol
Memory
Space
® =, Logical OR
290180-5
Figure 5. Page Mechanism
ister. The current address register (CAR) IS Incremented after every DMA transfer except when in
double ,host bus mode~ The lower-limit register
points to the beginning of the ring buffer; the upperlimit register points to the end of the ring buffer. The
82560 performs the wraparound (lower limit, to
CAR), each time the CAR equals the upper limit.
When the contents of the CAR equal those of the
stop register, DMA transfer stops and the 82560
generates an interrupt to the, CPU. When the double
host bus mode is invoked, the DMA machine will
alternately activate low and high banks of memory
and will increment the address after each high-bank
transfer.
DMA MACHINE
The 82560 provides two DMA channels. Each channel can access 16 kb of memory address, and has
request and acknowledge lines and address registers. The DMA normally operates in the Demand
mode, and becomes active in response to a DMA
request being granted. The requests come in on the
DRO lines and, if granted, are acknowledged by the
DACK lines becoming active. Each channel has a
control register that includes an enable bit, a direction bit, and output enable bits (CS, DACKO, and
DACK1 are active low signals that can be enabled/
disabled during DMA cycles). Each channel also has
a base, current, stop, lower-limit, and upper-limit reg1-64
intJ
82560
Table 3. DMA Handshake Encoding
LOOSELY COUPLED MODE
The 82560 performs flyby DMA transfers (read from
slave and write to memory or vice versa). The operation continues until the' current address register
equals the stop register or until the ORO is removed.
When the stop register is reached, the 82560 generates an interrupt.
DRQ
EOP
0
0'
1
1
0
1
0
1
E~ent
Status
Operation Done
Idle
Retry Request
New DMA Transfer Request
If both ORO and E<5P are sampled high, the Current
Address Register' of the channel is incremented and
another DMA cycle begins. If a frame is transmitted
or received without errors, both ORO and EOP are
low at the end of the DMA cycle and the 82560 will
generate an interrupt. If ORO is high and EOP is low,
a collision occured during transmission, or an error
occurred during reception. In this case the Current
Address Register will be reloaded with the value in
the Base Address Register; and, once again, it will
point to the beginning of the frame structure in memory.
82590 TIGHTLY COUPLED MODE
The Tightly Coupled Interface is a hardware interface between the 82560 and the 82590. This interface allows transmission and reception events to be
processed without CPU intervention. It allows the
implementation of the time-critical CSMA/CD processes: automatic retransmission, buffer reclamation, and continuous frame reception and transmission. The basic interface is a two-signal DMA handshake between the 82560 and the 82590; this occurs over the ORO and EOP pins. The 82590 provides the status of the current transmit or receive
process, or requests another DMA cycle at the end
of each DMA cycle. When configured for the Tightly
Coupled Interface, the 82560 and the 82590 use a
specific interrupt scheme to minimize CPU overhead
and to improve data throughput. The 82590 will not
generate interrupts when events occur that can be
handled by the 82560 without CPU intervention. Figure 5 illustrates the Tightly Coupled Interface mechanism. Table 3 lists the various combination of the
ORO and EOP signals, and the events they represent.
The DACK1/CS1.EOP pin of the 82590 is multiplexed and requires external logic to derive the EOP
and CS1 signals (see 82590 data sheet). Because
the 82560 integrates this logic, its DACK1/EOP pin
can be connected (with a pullup resistor) directly to
the DACK1 ICS1 IEOP pin of the 82590, and its
DACKO/DACK pin can be connected directly to the
DACK pin of the 82590. For more details, see the
8259X Users Manual.
OROn
OACKn
---~S'r--'"'\.
----\5 '1----+--,.
82560 SAMPLES
ORO AND EOP
290180-6
Figure 6. 82560, 82590 DMA Handshake
1-65
82560
collision (provided that the maximum number of collisions is not reached). In this case the current address register is reloaded with the value of the base
address register, and the DMA transfer is resumed
without CPU involvement. If the maximum number of
collisions has been reached, or if transmit failed for
any other reason, the 82560 will need CPU .intervention. Thus it will generate an interrupt to the CPU. At
the end of transmission of each frame, the 82560
updates the status byte (indicating the number of
collisions) in the memory.
Transmit
The 82590 can transmit consecutive frames without
using the CPU.to.issue the Transmit command each'
time. This improves data throughput during transmission and eliminates CPU overhead. The CPU can
place multiple transmit frames in memory, with each
frame separated from the next by a Transmit Command byte. (For further information see 82590 and
82592 user manuals.) The. 82560 supports transmit
chaining. It also supports automatic retransmit on
LOWER
LIMIT
I_";';;';';';~",I
UPPER
LIMIT
»
r
..,
'"»'" »'"
~
iii:
...
DATA
04
'"z
»
'"z
!'
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STATUS
BYTE COUNT LOW
BYTE COUNT HIGH
DATA
"+
290180-7
Figure 7. Example of a 4-kB Transmit Ring Buffer
1-66
82560
frame and the 82560 generates an interrupt to the
CPU. If no error occurs, the last two bytes received
(which are always stored in 82560 internal registers)
are copied back to the first two bytes of the frame.
These are the byte counts. If the 82590 generates
an interrupt on each frame reception the 82560 will
relay that interrupt to the CPU. At this time the value
of the CAR will be copied into BAR, FF will be written into the next two bytes, and CAR will be incremented as before to point to the new frame reception area.
Receive
Immediately after a channel is enabled for receive,
the 82560 will write FFh into the first two bytes of the
frame (pointed to by the base register). The current
address register is loaded with the contents of the
base register and is incremented twice (past the two
reserved bytes). If an error occurs during reception,
and the save bad frame bit is 0, the CAR is reloaded
with the content of the BAR and incremented past
the two reserved bytes; however, if the save bad
frame bit is set, the CAR is incremented for the next
CPU HAS PROCESSED
THIS PART OF THE
RECEIVE BUFFER
\--_ _ _ _-' (FROW 82590)
DATA
STATUS BYTE ,
STATUS BYTE 2
290180-8
Figure 8. Example of a 4-kB Receive Ring Buffer
1-67
inter
82560
Table 4. Address Map
. RESERVED
.
3Fh
2Fh
HOST MODE REGISTER
2Eh
2Dh
2Ch
2Bh
STOP 0
RESERVED
2Ah
29h
28h
UPPER LIMIT REGISTER 0
RECEIVE TEMP. REGISTERS
27h
26h
25h
24h
23h
LOWER LIMIT REGISTER 0
DMA CONTROL REGISTER 0
BASE
ADDRESS
REGISTER O·
Base Current
Bit = 1
CURRENT
ADDRESS
REGISTEROt
Base
Bit = 0
22h
21h
20h
22h
21h
20h
3Eh
3Dh
3Ch
STQP1
3Bh
3Ah
39h
38h
37h
UPPER LIMIT REGISTER 1
36h
35h
34h
33h
LOWER LIMIT REGISTER 1
DMA CONTROL REGISTER 1
BASE
ADDRESS
REGISTER 1
32h
31h
30h
32h
31h
30h
Basel
Current
Bit = 1
CURRENT
. Base
ADDRESS
Bit = 0
REGISTER 1t
DMA MODE REGISTER
1Fh
HOST
ADDRESS
REGISTER H
SELECT
REGISTER
1Eh
1Dh
1Ch
• Base/Current bit refers to the read cycles
only. When writing, both base and current
are updated.
1Bh
1Ah
t 0 refers to DMA channel O.
RESERVED
19h
18h
t 1 refers to DMA channel 1.
INT MASK REGISTER
INT CONTROL/STATUS REGISTER
17h
16h
§ In the 8259X, address 03h and 05h are
82588 STATUS 2 REGISTER
82588 STATUS 1 REGISTER
15h
RESERVED
13h
12h
11 h
used for accessing Port 0 and Port 1
respectively.
14h
CONTROL REGISTER
IDENTIFICATION REGISTER
MASTER MODE REGISTER
,
10h
OFh
i
SEMAPHORES
08h
CS
1
1
SCSPORTS§
1
1
0
0
0
0
DACK1
DACKO
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
07h
06h
05h
04h
03h
02h
01h
OOh
NOTE:
When writing to 3-byte registers, the most significant byte (higher address) should be written last. The value written into the
most significant bytes should be O. The third bytes are reserved for possible future use.
1-68
82560
82588 TIGHTLY COUPLED MORE
PROGRAMMING
The 82560 supports a Tightly Coupled Interface
(TCI) with the 82588. This interface allows transmit
and receive events to be processed without CPU
intervention. It allows the combination of the 82588
and 82560 to implement time-critical, CSMAlCD
events: automatic retransmission, buffer reclamation, and continuous frame reception (see 82588
Reference Manual). When configured for the 82588
TCI mode, the 82560 uses the 82588 INT pin to determine if an event has occurred. The 82560 then
reads the 82588 status'register(s) to determine the
cause of the interrupt. If the interrupt is d,ue to a
collision during transmission, a good frame reception, or errors during frame reception then the 82560
will update its DMA address registers and issue the
82588 the commands necessary for minimizing CPU
intervention. The 82560 will regenerate all 82588 interrupts except those generated when a collision occurs during transmission (with the maximum retry
count not exceeded). Because transmit and receive
interrupts are time-critical processes the 82560 automatically acknowledges such interrupts to reduce
dependency on the CPU. It will regenerate the interrupt on its INTOUT pin unless the interrupt is due to
a transmit collision.
The 82560 registers may be logically grouped into
Device Configuration registers, Status registers and
DMA address registers. Table 4 shows all of the
82560 registers and their addresses. All registers except receive temporary registers, 82588 status 1
and 2 registers, and the identification register, which
are read only, are read/write registers.
The registers can be accessed by the host CPU. The
RD signal indicates the direction of data transfer between the 82560 and the CPU. The actual data
transfer takes place over the 82560's 8-bit data bus
lines (Dy-Oo). The address of the register being accessed is taken from the address lines A5-AO.
Since the 82560's data bus is 8-bits wide, all access
to its registers is on a byte basis. If a register is
longer than 1 byte, each byte has to be accessed
individually through its unique address in the 82560
register space.
On power-up or reset, the 82560 registers are set to
a default configuration. The user must initialize the
82560 for the proper system configuration.
The SCS ports occupy eight addresses in the 82560
register space. The SCS ports should not be thought
of as registers. They are merely addresses in the
register space which, when addressed, activate a
combination of the DACKO, DACK1 or CS pins. The
particular combination of these pins signal levels depends on the SCS port address being accessed.
The semaphore ports allow resource sharing in a
dual processor (intelligent adapter) environment.
Each port can be used as a semaphore to implement mutual exclusion.
If the 82588 issues an interrupt due to a collision
during transmission, and the maximum retry count
has not been exceeded, the 82560 will automatically
reload the Current Address Register with the value
in the Base Address Register, acknowledge the interrupt, and issue a retransmit command to the
82588. If the interrupt is due to the reception of a
good frame, the 82560 will update its Base and Current Address Registers and prepare for a new incoming frame. If the interrupt is due to a receive
frame error, the 82560 will reclaim the buffer by resetting the Current Address Register to the beginning of the frame buffer.
CONFIGURATION REGISTERS
By programming these registers, the 82560 can be
tailored to support different PCs, slaves and memories. The memory access mode (I/O or memory
mapped) and the type of OMA support (Ioosly or
tightly coupled) can also be programmed.
If the 82588 is unable to transmit due to having exceeded the maximum retry count or a Lost-CTS condition or a Lost-CRS condition, an interrupt is generated; the 82560 will not update its DMA address registers. It will, however, acknowledge the 82588 interrupt and regenerate the interrupt on its INOUT pin.
1-69
inter
82560
MASTER MODE REGISTER (10h)
1071°'1051°41°31°10dool
"
I I
Holt bus Interface
• 00 equal data bus width
• 01 double data bus width·
• 01 double data bus width·
with special recetve
• 10 reserved
Reserved
Base/Current select (1/0)
HRDY delay
.00 no delay
• 01 0.5 clock delay
• 10 1.5 clock delay
• 11 2.5 clock delay
Reserved
Host/DMA Idle priority (lor 0)
• IN SOME VERSIONS OF" 82560, THIS MODE IS NOT TESTED.
290180-9
CONTROL REGISTER (12h)
I/O access delay (0 to 3)
Early/Late write option (1/0)
L..._......_ _ _ _ _ _ _.. Memory access delay (0 to 3)
L.-.....&_-+
L.-_ _ _ _- .
.....- . . . -"'------------+
Reserved
290180-10
HOST MODE REGISTER (2Fh)
Enable/Disable pipeline mode (1/0)
....._ -..... Pipeline direction read/write (1/0)
....- .....- .....-"'--.....-----+
.....---------------+
1·70
Reserved
General purpose Input
290180-11
intJ
82560
INTERRUPT MASK REGISTER (17h)
ID71 D61 Dsl D41 D31 D21 D11 DO I
I I I I I I I I
~-"'--"""-"'--"""-"""-"""-"""-+ low byte of the host-selected address
(I/O-mapped memory access)
290160-12
SELECT REGISTER, HIGH BYTE (1Bh)
~-......-
......-
.......-
.......- . High bits of the host-selected address
~-----------+ HRDY delay reference source
~-------------+ Memory or I/O mapped (1/0)
+
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Enable/Disable memory access (1/0)
290180-13
DMA MODE REGISTER (1Fh)
Reserved
Save/Discard bod frame (1/0)
DMA Mode
• 00 loosely coupled (regular)
• 10 8259X Tightly Coupled Interfaced
• 01 82588 TCI
• 11 reserved
290180-14
1-71
inter
82560
INTERRUPT MASK REGISTER (17h)
Level/Edge sensitive (1/0)
' - - - - . - High/Low true assert (1/0)
'--.....- - - - - + .
00 no change-
• 01 enable slave Interrupt
• 10 disable slave Interrupt
• 11 reserved
' - -.....- - - - - - - - - - . Reserved
' - - - - - - - - - - - - - - - - . Disable/Enable Tx chain (1/0)
' - - - - - - - - - - - - - - - - - . Enable/Disable Interrupt trl-state (1/0)
290180-15
'Whenever one of these bits is "1" while writing to this register, other bits are not affected.
Host Address Registers
Contain the initial memory address when the host accesses memory in I/O mapped or pipeline mode.
Identification/Software Reset Register
Writing to this address will reset the chip. Reading from. it will provide the user with 82560 stepping information.
MASTER MODE REGISTER (10h) DMA Control Register" (23h or 33h)
1D71 D61 Dsl D41 D31 D21 D1 1DO 1
L
Disable/Enable DACKO during
DMA cycles (1/0)
7iE"'O;;;P during
Disable/Enable, "DA"C"'K"lj
I)MA cycles (1/0)
Disable CS during DMA cycles (1/0)
Direction bit: memory read/write (1/0)
Enable/Disable DMA channel '(1/0)
Receive/Execution channel (1/0)t
Reserved
290180-16
05
03
OMA Channel Function
0
0
1
1
0
1
0
1
Transmit
Dump (588 or 590/592)
Reserved (Do Not Use)
Receive
'Each DMA channel has its own control register.
tThe following table shows the encoding of bits 3 and 5:
1-72
82560
• Transmission failed because of a collision, and
the maximum number of Transmit retries is
reached.
• Transmission failed for a reason other than collision; e.g., lost CRS/CTS.
INTERRUPTS
In the non-tightly coupled mOde, the 82560 will generate an interrupt when the Current Address register
equals the Stop register or when the interrupt input
pin is active.
• Reception failed, and the Save Bad Frame bit is
set.
In the tightly coupled modes, the conditions for generating Stop register interrupts are the same however, the 82560 will generate 82590 interrupts only if
its source was one of the following.
• Transmission of every frame, or last frame, in the
, chain is completed (progra'mmable).
• Reception completed.
The interrupt control register is read by the interrupt
routines to determine the exact source of the interrupt.
INTERRUPT STATUS READ REGISTER (16h)
External Interrupt
......---+ Reserved
L-_ _ _ _ _• Dt.lA channel-O-dane Interrupt
L-_ _ _ _ _ _ _+ Dt.lA channel-O-stap Interrupt
.....---------+
Dt.lA channel-I-done Interrupt
+ Dt.lA channel-I-stop Interrupt
.....- ......--------------+ Reserved
L-~
__________
290180-17
NOTE: "
The interrupt control register is written to acknowledge and reset the interrupt.
INTERRUPT CONTROL WRITE REGISTER (16h)
107IoI051°41°3Iolodool
L..
rest/ACK external Interrupt
Reserved
rest/ACK Dt.lA channel-O-done Interrupt
rest/ACK Dt.lA channel-O-stop Interrupt
rest/ACK Dt.lA channel-I-done Interrupt
rest/ACK Dt.lA channel-I-stop Interrupt
Reserved
rest/ACK Interrupt control register
290180-18
1-73
inter
82560
SYSTEM INTERACTION
82560 MACHINE CYCLE
A typical 82560 system interaction is described below.
The 82560 'machine cycle can be broken down into
three basic cycles: Idle (TIDLE), Arbitration (TA) and
Transfer (TTSF). The machine cyqle. I:!egins when a
request (HF or ORO) becomes active and the 82560
is in the idle state (TIDLE). The requests are synchronized and then undergo arbitration (TA). Once arbitration is completed, the transfer cycle (TTSF) begins.
1. The CPU configures the 82560 by writing to configuration registers.
2. The CPU accesses the local memory (through the
82560) and prepares a block of transmit frames.
3. The CPU writes the proper addresses into the
82560's OMA address registers, (base, current, lower limit upper limit and stop).
Synchronization (T S) is completed on the falling
edge of the clock. If the previous cyqle was non-idle,
arbitration begins and is completed within one clock
period (by the next falling edge of the clock).
4. The CPU writes to the 82560's OMA control registers to configure and enable the channels.
5. The CPU issues a transmit command to the
82590.
The Transfer cycle consists of the following sequential states: the first transfer state (T 1)' memory or 1/0
wait ,states (Tw), and the second transfer state (T2).
There may be another transfer state, Twh (wait host),
during host read or pipeline cycles. When no requests are pending, and the 82560 is not in the
transfer or arbitration cycle, it is said to be in the idle
state (TIDLE). If the previous cycle was non-idle, the
arbitration period (TA and T 2 of the previous cycle
will be done in parallel. (See Figure 4.)
6. The 82560 responds to the 82590's OMA request
by transferring data from memory to the 82590. '
7. Upon completion of transmission, the 82560
sends an interrupt to the CPU.
8. The CPU reads the 82560 interrupt control register to find the source of the interrupt.
9. The CPU issues a command to the 82590 to clear
its interrupt. (If the source of the interrupt was the
82590.)
Tw is the programmable portion of the transfer cycle. It can be zero to three clocks long depending on
the programmed memory or 1/0 access delays. If
the programmed delay is zero, then there will be no
Tw; the first state of the transfer cycle will be T 1.
During T2 the transfer cycle is completed unless the
cycle is a host read cycle. In that case the cycle will
be extended by inserting Twho Trw 82560 will remain
in Twh until the HF lines are deasserted. Once HF
lines are deasserted, T2 will begin and one clock
period later the bus cycle is complete.
10. The CPU acknowledges the 82560 interrupt by
writing a "1" into the corresponding interrupt control
register bit(s).
APPLICATIONS
Figure 9 shows a buffered, nonintelligent Star LAN
adapter for the IBM PC bus (using the 82560 and the
82590). Figure 10 shows a buffered, nonintelligent
Ethernet adapter for the IBM PC bus (using the
82560, 82592, 82C501 and the 82502).
1-74
1/1
'"
I "
.--+I TRANSCEIVER~
13
!
c
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en
~
%
~
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....
L..+-_-I HRDY
I
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10MHz 1
r----
.!.i
UI
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~:c
10
IL
RESET 10
...
~
~
I~
b
CLK
.1
DECODER 1
"
_
CS
k---1~---IDATA
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82560
'"
Q
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3:
:z
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+5V
\13
t:L
ILIO~ ... ~OII>:IQ
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CLK
m
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82590
~
RESET
en
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N
g:
"....
t:L
L..________________-....I
VI
•
~
SRAM
;:)
III
III
OE
cs
WE
8
~
0
DATA
ADDRESS
I
i
i
ROM
L,;,,;~_ _ _ _ _-J
GCS ...._ _ _ _ _ _ _ _ _...._ _...J
\8
\8
DO - 07
MOE
CSO
.&
ADDRESS
;-----+ OE
XCVI
IVI I~ I!: g g I; I~ MAO-MA12
I~QOO~QQQQ
.:..
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CD
CO
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- - - -...........l.........-.LQ-I~O~--...,
"'1'1
~
l
~
~
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~
f
~
Q
0
I
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8
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~
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Front-End Interface
~
~
• .1_J ___ 1._.1.
I~
~
.~
"iii!
@
a2J
~
~I
tA---r-:P
TO PHONE JACK
290180-19
~
.~
@
~
PC
~
I/o
....,.
CHANNEL
"III
l
13
~2
"II
US·
...CD
c
91
m
v
...::::ICD
....
CD
t.
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I ,I
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82!,",n
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......
0
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(")
-
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L-__~"I RESET
fi
~
l'i
I~
DATA (DO - 7)
~
MOE
CSL
cs
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I
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MAO-MA12
I
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01
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ADDRESS
WE
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16
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I-
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82592
0
C»
8
o
~~TA(D8-15)
1 1·1 -::::1--+1
4
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01
ROM
II
00
~
II.)
01
CD
~N
~
I ;::::J~~TA
DO - 07
.:" CD
<»
I
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82C501
I~
\16
\
..
L...
ADDRESS
SRAM
~
~----~'I~W_E__________
l-
*
I
·wwW·
t~
__ 1
CNET XCVR
19J
~
~
©
~
IiiiiI
~
"
"iiil
@
aeJ
~
RG-58 COAX
~
BNC
T - CONNECTOR
C:lJ
290180-20
c:::o
@
~
intJ
82560
*Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Case Temperature (TC)
under Bias ...................... O·C to + 85·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on any Pin with
Respect to Ground ....... -0.5V to Vee + 0.5V
NOTICE· Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS TC = O·Cto + 85·C. Vee = +5V ±10%
ClK pin has MaS levels (see VMIL. VMIH) All other signals have TTL levels (see VIL. VIH. VOL. VOH).
Symbol
Min
Max
Units
Input low Voltage (TTl)
-0.5
+0.8
V
VIH
Input High Voltage (TTL)
2.0
Vee + 0.5
V
VOL
Output low Voltage (TTL)
0.45
V
IOL
VOH
Output High Voltage (TTL)
2.4
Vee
V
IOH
VMIL
Input low Voltage (MaS)
-0.5
0.6
V
VMIH
Input High Voltage (MaS)
III
Input leakage Current
±10
p.A
ILO
1/0 leakage Current
+10
p.A
CIN
Capacitance of Input Buffer
10
pF
COUT
Capacitance of Input/Output Buffer
20
pF
== Vee -0.45
0.45 == VOUT = Vee -0.45
FC = t MHz
FC = 1 MHz
lec
Power Supply Current
50
mA
10MHz
VIL
Parameter
Vee - 0.6 Vee + 0.5
Test Conditions
= 3.2mA
= -400 p.A
V
o=
VIN
A.C. CHARACTERISTICS CL on all outputs is 50 pF. The user should add 0.2 ns/pF up to 100 pF
Symbol
Parameter
Min
Max
Test Conditions
SYSTEM CLOCK INPUT PARAMETERS
100
(Note 1)
ClKlowTime
45
(Note 1)
ClK High Time
45
(Note 1)
T1
ClK Cycle Period
T2
T3
T4
ClK Rise Time
5
. (Note 2)
T5
ClKFaliTime
5.
(Note 3)
HOST ACCESS CYCLE-NON PIPELINE MODE PARAMETERS
T6
HF or DREQ Setup Time
T7
HF Active Time (low)
T8
HF Inactive Time (High)
T9
HF to HRDY Low
T10
HF Active to HDRY High
T11
HRDY High to HF Inactive
10
(Note 5)
2*T1 + 10
T1 +10
50
2*T1 +50
0
1-77
(Note 4)
(Note 9)
(Note 5)
82560
A.C. CHARACTERISTICS
CL on all outputs is 50 pF. The user should add 0.2 ns/pF up to 100 pF (Continued)
Symbol
Parameter
Min
Max
Test Conditions
HOST ACCESS CYCLE-NON PIPELINE MODE PARAMETERS (Continued)
T12
HF Inactive to HRDY Float
T13
HF Active to XCVR Lines Low
T1 +T2
T14
HF Inactive to XCVR Lines High
(Note 7)
T15
HF Active to RD Low
T16
RD Hold after HF Inactive
T17
HF Active to Input Add. Valid
T18
Address Hold after HF Inactive
T19
HF Active to 82560 Data Valid
T20
Data Hold after HF Inactive
T21
HF Active to 82560 Add Valid (MAn).
T22
Add Valid or Chip Select Active Time
T23
H F Active to CS Active
T24
CS Enveloping Controls
T25
Control Active Time
T26
HF to Data Valid
T27
Data Hold after HRDY High
75
2*T1 +T2+75
(Note 6)
75
T1 +T2+ 10
0
-20
(Note 8)
0
3*T1 +80
(Note 9)
2*T1 +T2+75
(Note 9)
T1+T2
2*T1
(Note 10)
2*"1 +T2+50
(Note 9)"
20
(Note 11)
(Note 11)
3*T1-30
(Note 12)
HOST ACCESS CYCLE-PIPELINE MODE PARAMETERS
T28
HF Active Time·
T29
HF Active to Port CS Active
T1 +10
(Note 13)
(Note 9)
2*T1 +75
(Note 6)
T30
HF Inactive to HRDY Low
75
T31
HRDY Low to HRDY High
(Note 14)
T32
Port CS Active Time
T33
HF Inactive to Buffer Write
T34
Write Active Time
2*T1
(Note 14)
10
T1-10
T1 +10
DMA PARAMETERS
T35
DRQn High or INTR to Clock
Low Setup Time
T36
DRQn Low to Clock Low, Hold Time
10
T37
EOP Pulse Width
T·1
D~lay
(Note 15)
50
T38
Address
T39
CS, CSn, DAKn Delay Time
T40
CSn Delay Time (Slave to SRAM Flyby)
50
T41
IORD_MWR, IOWR Delay Time
45
T42
IORD_MWR, IOWR Active Time
Time
T2+75
T2+50
(Note 16)
1-78
(Note 16)
inter
82560
A.C. CHARACTERISTICS
CL on all outputs is 50 pF. The user should add 0.2 ns/pF up to 100 pF (Continued)
Symbol
I
Parameter
I
Min
I
Max
I
I
I
75
I
I
Test Conditions
INTERRUPT PARAMETERS
T43
T44
I
I
Interrupt Delay Time
Interrupt Gap
I
I
3*T1-10
RESET PARAMETERS
T45
T46
I
I
Reset Setup Time
Reset Active Time (High)
I
I
50
4*T1
I
I
I
I
'For pin HRDY 4 mAo
NOTES:
1. Measured at Vcc/2.
2. 3.2V to 1.8V.
3. 1.8V to 3.2V.
4. The following configuration affect the HRDY output going active (high).
Legend:
TID-The configuration of HRDY delay (master mode register, TID = 0,.5,1.5,2.5).
TIO-The configuration of 1/0 access delay (Control register,
TIO = 0,1,2,3 ).
TMEM-The configuration of MEM access delay (Control register, TMEM = 0,1,2,3).
"If bit 5 of Register at Address 1BH then (TID + 2)'T1 + 75
else [TID+TIO(or TMEM)+2)'T1 +75"
5. The user should not that the XCVR lines goes inactive immediately after HF inactivation.
6. Provided that the HOST wins arbitration.
7. In the case of HOST write cycle the XCVR lines will go high at the end of the 82560 cycle even if HF lines are still active.
In the case of HOST read cycles, the 82560 will terminate the local cycle after HF lines are inactivated.
8. Address lines are latched at the end of T1 of 82560 HOST bus cycles.
9. The maximum time specified assumes that the HOST wins the arbitration. If the HOST loses the arbitration to a DMA
request two possible scenerios are:
a) Arbitration lost to a single DMA cycle. In this case [(greater of TIO and TMEM) + 2)'T1 should be added to the
max. time.
b) Arbitration lost to a DMA cycle which is followed by four locked OMA cycles. In this case [(greater of TIO and
TMEM)'5 + 10)'T1 should be added to the max. time. This might happen in the rare case when the HOST request
coincides with the last receive or transmit transfer, in the TCI mode.
10. [TIO(or TMEM)+2)'T1+ 10. .
In the case of long (HF) HOST memory read requests, it would be extended until the request is removed.
11. Min = [TIO(or TMEM)+ 1)"T1-10, Max = [TIO(or TMEM) + 1)'T1+ 10.
12. This parameter depends on T10. In terms of machine states, data remains valid until the end of the cycle (end of state
T2).
13. (TMEM + 2)'T1+75+ Tsystem.
Tsystem = delay from HROY to HF inactive.
This maximum time refers to a second memory request immediately following a first one, assuming that the first one
was not delayed by a OMA cycle.
14. [TIO(or TMEM) + 2)"T1 + 75.
15. This is an asynchronous signal (OROn only in its leading edge). It is internally synchronized. Meeting this parameter,
assures recognition on the next clock.
16. Min = [(greater of TIO and TMEM) + 1)'T1 + T2 + 10
Max = [(greater of TIO and TMEM)+ 1)"T1 +T2+ 10
1-79
82560
A.C. TESTING INPUT & OUTPUT WAVEFORM
2.4
0.45
=x:
1.5 -TEST POINTS -
1.5
SYSTEM CLOCK TIMING
x=
vee- 0.6
0.6
290180-21
A.C. Testing Inputs are Driven at 2.4V for a Logic "1"
and 0.45V for a Logic "0". Timing Measurements are
made at 1.5V for both a Logic" 1" and "0".
I---n--'-'-......
·' '
290180-22
WAVEFORMS
HOST READ CYCLE-NON PIPELINE MODE
eLK
-...
T.
To
n
~~~
-T6 I-
I--n ......
T7
---
T9HRDY
n3-
Tw
T2
TI
TI
~~ ~
H
I-oT3.
T8-
H,
--- r-- n1
,..I- ~12
no
f.1--T14
H
I
1
~~17j~
1-
AO-A12, BMn
Data Valid
i
-0
15-1
T16
I
1+
T181
VALID,
I
HOST READ FROM 82560
T---t1
I
I
I
I+r-T20-
H
'
HOST READ FROM I/O or SRAM
I
+-T21
y2
MAO-12,eSn
--T23
A2
-
f-T24
T24
r---T25-
T2j f-
r---
-T24
.....
T42- I--
I
290180-23
1·80
inter
82560
WAVEFORMS (Continued)
HOST WRITE CYCLE-NON PIPELINE MODE
ClK
~
~
Ta
T1
~ -~
-T6IT1T7
~
T2
-,..
T10
HRDY
T8-
-1
"-
~ T11
I- ~12
~+-T14
I-
T13 ....
TI
I-cT3~
I-
T6-
I--
T9-
n
~ u-" ~
H
I
~1171
AD-A12, BMn
.. T181
VALID
I
X
HOST WRITE TO 82560
Data Valid
i
T2
j-1 I
~-T27-
:1
~OST WRI~E TO I/o or SRAM
I
-t--T21
y2
MAO-12
-t--T23
CSn,GCS,Cs,DACKn
A2
-
--T24
T24
-1
I-
25 290180-24
1-81
82560
WAVEFORMS (Continued)
HOST READ CYCLE-PIPELINE MODE
eLK
-.,
Ts
To
T1
~ ~~
-
T6-I+--T28
T2
Ti
n
Lr ~ ~ WT8
I
\.
I- ~301HRDY
H
II
I
\.
4T1
8Mn
-T31-
\.
I
~Tl1--1
VALID
I
I- f--T21
T22
--
I- r-T23
T22
--
I+- r-T29
T32--
MAO-12,
...
--T24
-
-T24
.. T33 ~T3y.
~"i 4-T25[:I
--T42
I
-r
4
II
290180-25
1-82
inter
82560
WAVEFORMS (Continued)
HOST WRITE CYCLE-PIPELINE MODE
-- 30~
r T32-i-rT31-1
HRDY
--~~~-,++~~
r--+---~--~
r-i 1
17
8Mn
MAO-12
XCV2/PCS
CSn
IORD/MWR
VALID
I
_+--+f4-+-~'T::;21~::JI-T22
r---------H__+-_~
_+-~f4-+-::::.!:·T2;';'9+=::rI-T32
r--------- H--+--~
~T23 r------+---~---~~~--~~I
T"j24 Y
i
T24
_~_~_-+____~--T4T2~r
I
~-----I----!
290180-26
DMA FLYBY CYCLE-SLAVE TO SRAM
Ts
To
T1
TW
T2
TI
TI
ClK
FOP -+---~---~--~--~-1l~
MAO-12
IORD/MWR
__~
-+---+--H_-I-_-+__~J~---!
--+---+--~~~~-+----r-~
290180-27
1-83
82560
WAVEFORMS (Continued)
DMA FLYBY CYCLE-SRAM TO SLAVE
Ts
T1
TW
n
T2
TI
elK
ORO" -":'--;-+--+---+--I--f-~
l'-r-....-+--i
rop -+----+----+----+----I-~+_--~
MAO-12
T39
290180-28
1-84
intJ
82560
WAVEFORMS (Continued)
INTERRUPT
ClK
INT
INTR
-01---1--..11
290180-29
RESET
CLK
RESET
11W¥Rillrn=
-+---+-...
290180-30
1·85
I.e."
I~·n+'~'r
•
'82590
ADVANCED CSMA/CD LAN CONTROLLER
WITH 8-BIT DATA PATH
Supports Industry Standard LANs
- Ethernet and Cheapernet (IEEE 802.3
'
10BASE5 and 10BASE2),
- StarLAN (IEEE 802.3 1BASES)
-IBMTM PC Networ!<-Baseband and
Broadband
•
•
Efficient Memory Use via Buffer and
' Frame Chaining
Physical and Data Link
• Integrates
Layers of OSI Model
•
- Complete CSMA/CD Medl~m Access.
Control (MAC) Functions '
- Manchester, 'Differential Manchester,
or NRZI Encoding/Decoding
- On-Chip, Logic-Based Collision
Detection
-IEEE 802.3 or HDLC Frame Delimiting
- Broadband E,thernet (IEEE 802.3
10BROAD36,.
Two Modes of Operation
- Bit Rates up to 4 Mb/s with On-Chip
Encoder/Decoder (!:Iigh-Integratlon - ,
Mode)
-Bit-Rates up to 20 Mb/s with
External Encoder/Decoder (HighSpeed Mode)
High-Performance System Interface
• -16-MHz
Clock, 2 Clocks per Transfer
- 64 Bytes of Conflgurable FIFO
DMA Interface for Retransmission and
Continuous Reception without CPU
, Intervention
- EOP Signal Generation for 8237 and
82380
- Tightly Coupled Interface to 82560
Host Interface and Memory Manager
• 82588 Pln- and Software-Compatible
Mode
Local and Remote Power-Down Modes
Deterministic Collision Resolution
24-Blt General Purpose Timer
On-Chip Jabber Inhibit Function
~etwork Management and Diagnostics
- Monitor Mode
- CR~, Aligoment,' and Short Frame
Error Detection
- Three 16-Blt Event Counters
- Short or Open Circuit Localization
- Self-Test Diagnostics
-Internal and External Loopback
Operation
-Internal Register Dump
•
•
•
•
•
•
High-Speed CHMOS III Technology
-Brr
Figure 1.82590 Block Diagram
290147-1
·IBM, PC, PCAT, PCXT are trademarks of International Business Machines,
1·86
October 1988
Order Number: 290147-1103
inter
82590
DACKO/OACK
CSo
WR
CLK
RD
vee
DACK1/CSI/EOP
INT
RESET
TCLK/CRS
07
COT
06
CTS/LPBK
05
RTS
04
TxO
07
RxO
06
N82590
ORQl
05
ORQO
04
4<4LPLCC
(TOP VIEW)
•
NC
NC
NC
RxC/x2
TxC/xl
TCLK;CRs
COT
CTS/LPBK
RTS
T.O
RxO
NC
NC
290147-2
Figure 2. 82590,Pln Configuration (DIP)
The 82590 is a second·generation, 8-bit data path
CSMAlCD controller. Its system interface enables
efficient operation with a wide variety of Intel microprocessors (such as iAPX 188, 186, 286, or 386) and
industry standard buses (such as the IBM PC I/O
channel or PersOnal System/2™ Micro ChanneI™).
The 82590 can be configured to support a wide variety of industry standard networks, including StarLAN
and EthernetlCheapernet.
290147-3
Figure 3. 82590 Pin C~nflguratlon (PLCC)
CSMAlCD LAN adapters oriented t~ the IBM PC environment. The 82590 fully conforms to existing
IEEE 802.3 standards (1 BASE5, 10BASE5,
10BASE2, and 10BROAD36). Intel also offers the
82592, a 16-bit data path version of the 82590, for,
higher performance applications.
The 82590 provides a natural upgrade path for existing 82588 applications, since it is pin and software
compatible with its predecessor. Its rich incremental
functionality compared to the 82588 can be utilized
by selectively modifying existing software drivers.
The 82590 is available in a 28-pin Plastic DIP or a
44-pin PLCC package. It is fabricated with Intel's reliable CHMOS III technology.
Together with the 82560 (Host Interface and Memory Manager) the 82590 offers a complete solution for
1-87
82590
Table 1.82590 Pin Description
Pin No.
(DIP)
Pin No.
(PLCC)
D7
D6
D5
D4
D3
D2
D1
DO
6
7
8
9
10
11
12
13
AD
Symbol
Type
Name and Function
10
11
12
13
14
18
19
20
1/0
DATA BUS-The Data Bus lines are bidirectional, three-state lines
connected to the CPU's Data Bus for transfers of data, commands,
status, and parameters.
5
9
I
READ-Together with CSO, CS1, DACKO, or DACK1, Read controls
data or status transfers out of the 82590.
WR
3
4
I
WRITE-Together with CSO, CS1, DACKO, or DAGK1, Write
controls data or command transfers into the 82590.
~
2
3
I
CHIP SELECT (PORT O)-When lOW, the 82590 is selected by
the CPU for command or status transfer through PORT o.
RESET
25
40
I
RESET-A HIGH signal on this pin causes the 82590 to terminate
current activity. This signal is internally synchronized and must be
held HIGH for at least four Clock (ClK) cycles.
When the Clock signal is provided internally (ClKSRC is strapped
HIGH), the RESET Signal must be held HIGH for at least 50 /ks.
(PLCC version only.)
INT
26
41
0
INTERRUPT-A HIGH signal on this pin notifies the CPU that the
82590 is requesting an interrupt.
DROO.
17
26
0
DMA REQUEST (CHANNEL 0)-This pin is used by the 82590 to
request DMA transfer. DROO remains HIGH as long as the 82590
requires DMA transfers. Burst transfers are thus possible.
When the 82590 is programmed for Tightly Coupled Interface, the
82590 notifies the DMA controller of the status of transmission or
reception, using this pin together with EOP.
DR01
18
27
0
DMA REQUEST (CHANNEL 1)-This pin is used by the 82590 to
request DMA transfer. DR01 remains HIGH as long as the 82590
requires DMA transfers. Burst transfers are thus possible.
When the 82590 is programmed for Tightly Coupled Interface, the
82590 notifies the DMA controller of the status of transmission or
reception, using this pin together with EOP.
1
2
I
DMA ACKNOWLEDGE (CHANNEL O)-When lOW, this input
signal from the DMA controller notifies the 82590 that the requested
DMA cycle is in progress. This signal acts Similarly to Chip Select for
data and parameter transfers, using DMA channel o.
DMA ACKNOWLEDGE (CHANNELS 0 AND 1)-When the
DACK1/CS1/EOP pin is programmed to CS1/EOP, this pin
provides a DMA acknowledge for both channels 0 and 1. Two DMA
acknowledge signals from the DMA controller, DACKO and DACK1,
must be externally ANDed in this mode of operation.
DACKO
DACK
1·88
82590
Table 1.82590 Pin De8Crlption (Continued)
Symbol
~
Pin No. Pin No.
(DIP) (PLCC) Type
27
42
This is a multifunction, bidirectional pin which can be programmed to
DACK1 or,CS1IEOP during configuration. When it is configured for EOP, it
. provides an open-drain output.
DMA ACKNOWLEDGE (CHANNEL 1)-When lOW, this input signal from
the DMA controller notifies the 82590 that the requested DMA cycle is in
progress.· This signal acts similarly to Chip Select for data and parameter
transfers, using DMA channel 1.
1/0 CHIP SELECT (PORT 1)-When lOW, the 82590 is selected by the CPU
for command or status transfer through PORT 1.
END OF PROC~A lOW output signal requests the DMA controller to
.
terminate the active OMA serVice.
4
5
CLOCK-In the 28·pin DIP, this is only an input pin. A TTl·compatible
clock input to this pin provides the timing for the 82590 parallel
subsystem.
1/0 In the 44·pin PlCC, this pin can' be a clock input or output, depending on
the state of. ClKSRC, If ClKSRC is strapped lOW, this pin is a clock input
which provides timing for the 82590 parallel subsystem. If ClKSRC is
strapped HIGH, the clock for .the 82590 parallel subsystem is generated
from the internal clock generator. The ClK pin is then a clock output and
provides a clock signal whose frequency can ~ one·half of or identical to,
the frequenCy of the Internally generated parallel subsystem clock, .
depending on the state of FREQ. Note that the maximum frequency of the
clock Signal supplied by tfieCLI( pin is 8 MHz.
CSf/EOP
ClK
Name and Function :
CLKSRC FREQI--..........___
C_L_K_ _-i
Type
Signal
Clock for the
Parallel Subsystem
o (lOW)
Don't
Care
t
Clock·
Clock as Provided on the ClK Pin
1 (HIGH)
1
o
Internal
parallel
Subsystem
Clock Divided
by Two .
Prescaled Clock Generated from
the Internal Clock Generator
o
o
Internal'
Parallel .
Su.b&!ystem
Clock.
Prescaled Clock Generated from
the Internal Clock Generator
-
,
ClKSRC
NA
.. 6
I
CLOCK SOURCE-When st~ped lOW, a clock signal on the ClK pin
provic[8$ timing for the parallel subsystem. When strapped HIGH, timing
for the parallel subsystem js internally generated from the clock generator
provided in t~e serial subsystElI!'. The internal prescaler is programmed
during col1figura,ion to deter~ine tpe frequency of the clock for the
parallel subsystem..
" .
FREQ
NA
7
I
FREQUENCY-:-When str~pped lOW, CL.K has an output frequency equal
to that of the internal parallel subsystem clock. When strapped HIGH, ClK
has an output frequency one·half that of the internal parallel subsystem
clock. The state of this pin is relevant only when ClKSRC is strapped
HIGH.
1·89
82590
Table 1. '82590 Pin Description (Continued)
.,
Pin No. PlnNo,
Type:
(DIP) (PLeC)
Symbol
I
15/16 ' 24/25
X1/X2
;=xc
15
24
I
RXC
16
25
I'
24
36
I
,
'i'CCJ<1
5
I
GP
4
r/c
I
o
2
3
EVENT
STATUS 0
TlfolER/COUNTER STATUS
STATUS 1
TIMER/COUNTER CONFIGURATION
STATUS 2
PORT 1 COMMAND
STATUS
I
TIMER/COUNTER
CONFlG\JRATION
STATUS 3
290147-9
Timer/Counter Events
(T/C = 1)
Timer Expired
BitO
Counter 1 Expired
Bit 1
Counter 2 Expired
Bit2
Counter 3 Expired
Bit3
REM-PWR-UP
1-95
=1
=1
=1
=1
General Purpose Event
Value"
(GP = 1)
(Status 0)
"The 82590 may have more than one EVENT bit set by the time the CPU reads the status register.
Figure 8. Port 1 Status Registers
Value"
(Status 0)
9
inter·
. 82590
290147-10
Figure 9. 82590/Host CPU Interaction
Table 2. Data Bus Control Signals and ·Functions
Pin Name
CSO
CS1*
RD
WR
1
X
0
1
X
1
Function
No Transfer To/From
Command/Status
0
0
0
Illegal
0
0
1
Read from Status
Register
0
1
0
Write to Command
Register
DACKO
DACK1*
RD
WR
1
X
X
0
1
1
To initiate an operation such as Transmit or Config·
ure (see Figure 5), the command from the CPU must
first be written to the 82590. Any parameters or data
associated with the command are transferred from
memory to the 82590 using DMA. Upon completion
of the operation, the 82590 updates the appropriate
status registers and sends an interrupt to the CPU.
FRAME TRANSMISSION
To transmit a frame, the CPU prepares a Transmit
Data Block in memory as shown in Figure 10. Its first
two bytes specify the length of the rest of the block.
The next few bytes (up to six) contain the destination
address of the station the frame is being sent to.
The rest of the block is the data field. The CPU pro·
grams the DMA controller with the start address of
the block, length of the block, and other control information and then issues a Transmit command to
the 82590. Upon receiving this command, the 82590
fetches the first two bytes of the block to determine
its length. If the link is free and the first data byte
was fetched, the 82590 begins transmitting the preamble' and concurrently fetches more bytes from the
Transmit Data Block and loads them into the transmit FIFO to keep them ready for transmission.
. No DMA Transfer
0
0
0
Illegal
0
0
1
Data Read from DMA
Channel 0 (or 1)
0
1
0
Data Write to DMA
Channel 0 (or 1)
'Only one of CSO, CS1, DACKO, or DACK1 may be active
at any time.
1-96
82590
PREAMBLE
sm (BOF
BLOCK BYTE COUNT
FLAG)
DESTINATION ADDRESS
DESTINATION ADDRESS
DATA FIELD
SOURCE ADDRESS
CPU GENERATED
DATA STRUCTURE IN MEMORY
(TRANSMIT DATA BLOCK)
LENGTH FIELD
[
}
GENERATED BY 82590
FROM 82590
~ INDIVIDUAL
ADDRESS
INFORMATION FIELD
PADDING (OPTIONAL)
FRAME CHECK SEQUENCE
EOF FLAG (OPTIONAL)
PADDING (OPTIONAL)
GENERATED BY 82590
1
290147-11
Figure 10. The 82590 Frame Structure and Location of Data Element in System Memory
Tightly Coupled Interface, retransmission is performed without CPU intervention.
The destination address is transmitted after the preamble. This is followed by the source or the station
individual address, which was previously stored in
the 82590 by the lA-Setup command. After this, the
entire information field is transmitted, followed by a
CRC field calculated by the 82590. If a collision is
encountered during transmission of the frame, then
the transmission is aborted after a jam pattern is
sent. If the collision is detected during preamble or
SFD (Start Frame Delimiter) transmission, the 82590
transmits the jam pattern after the SFD is transmitted. An interrupt is then generated to inform the CPU
of the unsuccessful transmission due to a collision.
The CPU reinitializes the DMA controller and issues
a Retransmit command to the 82590. Retransmission is done by the CPU exactly as the Transmit
command is done, except the Retransmit command
keeps track of the number of collisions encountered.
When the 82590 gets the Retransmit command and
the backoff timer is expired, it transmits the frame
again. Retransmission is repeated until the attempt
is successful, or until the preprogrammed retry number expires.
FRAME RECEPTION
The 82590 can receive frames when its receiver has
been enabled. The 82590 checks for an address
match for an Individual address, a Multicast address,
or a Broadcast address. In the Promiscuous mode
the 82590 receives all frames. When the address
match is successful, the 82590 transfers the frame
to memory using the DMA controller. Before enabling the receiver, it is the CPU's responsibility to
make a memory buffer area available to the receiver
and to properly program the starting address of the
DMA controller. The received frame is· transferred to
the memory buffer in the format shown in Figure 11.
This method of reception is called Single Buffer reception; the entire frame is contained in one continuous buffer. Upon completion of reception, the status
of the· reception is appended at the end of the received frame in the memory buffer, and the total
number of bytes transferred to the memory buffer is
loaded into the internal status registers 1 and 2. An
interrupt is then generated to inform the CPU of the
frame reception.
If the 82590 is programmed to generate the EOP
signal to the 8237 or 82380 DMA controller, or if it is
used with a DMA controller which implements the
1-97
82590
BLOCK
LENGTH
BLOCK LENGTH
BL
DESTINATION
ADDRESS
DESTINATION
ADDRESS
SOURCE
ADDRESS
INFORMATION
I""U
DATA BLOCK IN MEMORY FOR
TRANSMISSION
INFORMATION
FRAME STATUS
SINGLE BUFFER RECEPTION
290147-12
Figure 11. Single Buffer Reception
If the frame size is unknown, memory usage can be
optimized by using Multiple Buffer reception. In this
mode of operation, the CPU and DMA Controller can
dynamically allocate memory space as it receives
frames. This method requires both DMA channels to
receive the frame alternately. As frame reception begins, the 82590 interrupts the CPU and automatically
requests assignment of the next available buffer.
The CPU does this and loads the second DMA
channel with the next buffers information so the
82590 can immediately switch to the other channel
when the current buffer is full. When the 82590
switches from the first to the second buffer it again
interrupts the CPU and requests another buffer to be
allocated on the previous channel: This process
continues until the entire frame is received. The received frame is spread over multiple memory buffers. The link between the buffers is easily maintained by the CPU, using a buffer chain descriptor
structure in memory as shown in Figure 12. This dynamic allocation of memory buffers results in efficient use of available storage when handling frames
of widely differing sizes.
more advanced data structures for the buffer area
can significantly improve system performance.
EOP SIGNAL TO THE DMA
CONTROLLER
The 82590 can be programmed to assert the EOP
signal to the 8237 or 82380 DMA controller when
one or more of the following occurs:
• A collision during transmission
• An error (CRC or alignment) during reception
• A good frame reception
If the 8237 or 82380 is programmed for Auto-initialize mode and if the 82590 is programmed to assert
the EOP signal on a collision during transmission,
the retransmission following a collision is done automatically by the 8237 and the 82590. The 8237 will
reinitialize itself automatically and the 82590 will retransmit the same frame from the same memory
area without CPU intervention. When the 82590 is
programmed for this mode it does not interrupt the
CPU upon a collision, and the CPU does not need to
issue a Retransmit command to the 82590. The CPU
is interrupted only after a successful transmission or
retransmission, or after a transmission failure, such
as DMA underrun.
If the 82590 is programmed to generate the EOP
signal to, the 8237 or 82380 DMA controller, or if it is
used with a DMA controller which implements the
Tightly Coupled Interface, buffer reclamatior) and
1-98
inter
82590
@
BUFFER 1
@
BUFFER 2
••
•
@
BUFFER # 2
BUFFER N
••
•
BUFFER CHAIN DESCRIPTION
(MANAGED BY CPU)
t - - - - - - 1 BUFFER #N
STATUS
290147-13
Figure 12. Multiple Buffer Reception
ble 3. As long as the 82590 generates J2£1O t:!!9!1
and EOP Floating at the rising edge of RD or WR,
the DMA controller repeats DMA transfers. If the
transmission is completed without collisions or if the
reception is good (no collision, no CRC, or no Alignment error), then DRO and EOP both become Low
at the end of a DMA transfer which follows the last
DMA data transfer. If the transmission encountered
a collision or if the reception had an error, DRO becomes High and EOP becomes Low. The DMA controller must decode these signals appropriately and
must reinitialize the DMA channel so it can retransmit the same frame or reclaim the otherwise wasted
buffer. It is the DMA controller's responsibility to reo
program itself for the next appropriate operation.
If the 82590 is programmed to assert the EOP signal
when an error occurs during reception, the 8237 or
the 82380 in Auto·initialize mode will be able to reo
claim the memory area which would otherwise be
wasted for the errored frame reception. If the 82590
is programmed to assert EOP at the end of a frame
reception, automatic buffer switching can be accom·
plished by alternating the DMA channels with the
8237 or the 82380. When the 82380 is used, the
buffer switching can be done with only one DMA
channel.
The EOP signal must be derived from the DACK1 I
CS1/EOP pin using external logic (see Figure 13).
82590/82560 TIGHTLY COUPLED
INTERFACE
The 82560 fully implements the Tightly Coupled Interface and provides very high-performance DMA
services for the 82590 with minimal CPU involve·
ment.
The 82590 has a mode of operation called "Tightly
Coupled Interface.". In this mode the 82590 provides
a tightly coupled interface to a DMA controller in or·
der to execute some of the time,critical processes of
the CSMAlCD protocol without any CPU interven·
tion. By using the 82590's companion chip, the
82560, or by implementing the Tightly Coupled Inter·
face in a DMA controller, operations such as auto·
matic . retransmission; . continuous back·to-back
frame reception,andtransmit andlor receive buffer
chaining can be accomplished.
NETWORK MANAGEMENT AND
DIAGNOSTICS
The 82590 provides a large set of diagnostic and
network management functions.including: internal
and external loopback, monitor mode, optional capture of all frames regardless of destination address
(Promiscuous mode), and time domain reflectometry
for locating fault points in the network cable. The
82590 Dump command ensures software reliabili.ty
by dumping the contents of the 82590 internal registers into the system memory.
The 82590 provides the status of the current active
transmission or reception to the DMA controller by
using the DRO and EOP signals at the end of every
DMA cycle. The status is encoded according to Ta-
1-99
inter
82.590
5V .
EOP
82590
CS1
DACK1/CS1/EOP
DACKO
DACK1
DACKO
DRQO
DRQO
DRQ1
DRQ1
Ri5
Ri5
WR
ViR
CSO
CSO
·290147-14
Figure 13. Demultiplexlng DACK/CS1/EOP Pin
Table 3 Transmit/Receive Status Encoding on DRQ and EOP
DRQ
EOP
0
Hi-Z
Status Information
..
Idle
1
Hi-Z
0
0
Transmission or Reception Terminated OK
1
0
Transmission or Reception Aborted
DMA Transfer
OTHER ENHANCEMENTS
Compared to the 82588 the 82590 has a number of
functional and performance enhancements. This
section lists some of these enhancements which are
not covered in other sections.
@
82590
CRC Transfer to Memory-The 82590 can
be programmed to transfer the CRC field of a
received frame into memory.
Loopback Signal to the 82C501-The 82590
can be programmed to provide an active High
loopback signal to the 82C501 (see Figure 14).
StarLAN-The 82590 can be configured to
recognize the IEEE 802.3 1BASE5 Collision
Presence Signal (CPS). In this mode it also delays deactivation of the RTS signal at the end
of a frame transmission in order to insert an
end-of-frame marker according to the standard.
If the desired network requires determinism, the
82590's Deterministic Collision Resolution (OCR)
method can be used.
Figure 15 shows a block diagram of an
82590/82560 High Integration adapter board. The
82560 provides the following functions: DMA for the
82590 with Tightly Coupled Interface and dual-port
memory control for the static RAM. The 82590 is
configured to High-Integration mode to minimize the
serial interface logic.
82590
APPLICATIONS
82C501
74HCT04
The 82590 can be used in a variety of applications.
When it is used in High-Integration Mode, it implements most of the Data Link and Physical Layer
functions required by the IEEE 802.3 1BASE5 (StarLAN) and the IBM PC Network-Baseband and
Broadband. When it is used in High-Speed Mode, it
can work with the 82C501 and a standard transceiver for IEEE 802.3 10BASE5 (Ethernet) and
10BASE2 (Cheapernet) implementations.
1-101
3
CTS/LPBK
I,PBK
!> 10k.Q
-
L..
290147-15
Figure 14. Loopback Output to tile 82C501
-
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290147-16
~
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intJ
82592
ADVANCEDCSMA/CD LAN CONTROLLER
WITH 16·BIT DATA PATH
Efficient Memory Use via Buffer and
Industry Standard LANs
• -Supports
• Frame
Chaining
Ethernet and Cheapernet (IEEE 802.3
10BASE5 and 10BASE2)
DMA Interface for Retransmission and
•
- Broadband Ethernet (IEEE 802.3
Contlnuoul5 Reception Without CPU
10BROAD36)
•
•
•
- StarLAN (IEEE 802.3 1BASE5)
-IBM* PC Network-Baseband and
Broadband
Integrates Physical and Data Link
Layers of OSI Model
- Complete CSMA/CD Medium Access
Control (MAC) Functions
- Manchester, Differential Manchester,
or NRZI Encoding/Decoding
- On-Chip, Logic-Based Collision
Detection
-IEEE 802.3 or HDLC Frame Delimiting
Two Modes of Operation
- Bit Rates Up to 4 Mb/s with On-Chip
Encoder/Decoder (High-Integration
Mode)
- Bit Ra~es Up to 20 Mb/s with
External Encoder/Decoder
(High-Speed Mode)
High-Performance System Interface
- 16-MHz Clock, 2 Clocks per Transfer
- 64 Bytes of Configurable FIFO
8-or1 -
•
•
•
•
Intervention
- EOP Signal Generation for 8237 and
82380
- Tightly Coupled Interface to 82560
Host Interface and Memory Manager
Supports 8- or 16-Blt DMA Transfers
Local and Remote Power-Down Modes
Deterministic Collision Resolution
24-Bit General Purpose Timer
On-Chip Jabber Inhibit Function
ill Network Management and Diagnostics
- Monitor Mode
- CRC, Alignment, and Short Frame
Error Detection
- Three 16-Blt Event Counters
- Short or Open Circuit Localization
- Self-Test Diagnostics
- Internal and External Loopback
Operation
-Internal Register Dump
High-Speed CHMOS III Technology
•
•
BUS
FIfO
Subsystem
290146-1
Figure 1.82592 Block Diagram
'IBM is a trademark of International Business Machines Corporation.
1-103
October 1988
Order Number: 290146-003
inter
82592
07
06
05
04
03
02
FREQ
01
WR
DO
CSO
•
012
013
014
011
¥SS
OACKO!OACK
¥SS
¥SS
TxC/Xl
010
015
¥CC
09
08
44L PLCC
¥CC
07
(TOP VIEW)
¥ce
OACK1/CSIjEOP
06
05
TxO
ORao
INT
04
R~O
ORal
RESET
03
NC
RxC/X2
N82592
TCLK/CRS
COT
CTS/LPBK
RTS
012
013
014
015
290146-3
TC~K/CRS
Figure 3. 82592 Pin Configuration (PLCC)
290146-2
Figure 2. 82592 Pin Configuration (DIP)
The 82592 is a second-generation, 16-bit data path
CSMA/CD controller. Its system interface enables
efficient operation with a wide variety of Intel microprocessors (e.g., 80186, 80286, or 80386) and industry standard buses (such as the IBM PC I/O
channel or Personal System/2 Micro Channel). The
82592 can be configured to support a wide variety of
industry standard networks, including StarLAN, IBM
PC Network, and EthernetiCheapernet.
The 82592 is ideal for integrated LAN on motherboard solutions. The 82592 architecture offers low
cost, high performance and minimal real estate requirements. The 82592's Tightly Coupled Interface
mode allows it to use host DMA without local buffering. An integrated 82592 Ethernet motherboard LAN
will occupy less than. five percent of the total motherboard area. The CHMOS 82592 can be used in
low power or no-fan systems such as diskless workstations and laptop PCs. The 82592 provides two
power-down modes for these environments.
Together with the 82560 (Host Interface and Memory Manager) the 82592 offers a complete solution for
CSMA/CD LAN adapters oriented to the IBM PC environment. The 82592 fully conforms to existing
IEEE 802.3 standards (1 BASE5, 10BASE5,
10BASE2, and 10BROAD36). Intel also offers the
82590 an 8-bit data path version of the 82592. The
82590' is pin and software compatible with the
82588.
The 82592 is available in a 40-pin Plastic DIP or a
44-pin PLCC package. It is fabricated with Intel's reliable CHMOS III technology.
1-104
82592
Table 1. Pin Description
Pin No.
(DIP)
Pin No.
(PLCC)
015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
00
22
23
24
25
37
38
39
40
1
2
3
4
5
6
7
8
36
37
38
39
9
10
11
12
13
14
15
16
17
18
19
20
1/0
DATA BUS: The Oata Bus lines are bidirectional, three-state lines
connected to the CPU's Oata Bus for transfers of data, commands,
status, and parameters.
RO
36
8
I
READ: Together with CSO, CS1, OACKO, or OACK1, Read controls
data or status transfers out of the 82592.
WR
34
4
I
WRITE: Together with CSO, CS1, OACKO, or OACK1, Write controls
data or command transfers into the 82592.
CSO
33
3
I
CHIP SELECT (PORT 0): When lOW, the 82592 is selected by the
CPU for command or status transfer through PORT O.
RESET
26
40
I
RESET: A HIGH signal on this pin causes the 82592 to terminate
current activity. This signal is internally synchronized and must be held
HIGH for at least four Clock (ClK) cycles.
When the Clock signal is provided internally (ClKSRC is strapped
HIGH), the RESET signal must be held HIGH for at least 50 /Ls. (PlCC
version only.)
INT
27
41
0
INTERRUPT: A HIGH signal on this pin notifies the CPU that the
82592 is requesting an interrupt.
OROO
14
27
0
DMA REQUEST (CHANNEL 0): This pin is used by the 82592 to
request OMA transfer. DROO remains HIGH as long as the 82592
requires OMA transfers. Burst transfers are thus possible.
When the 82592 is programmed for Tightly Coupled OMA Interface,
the 82592 notifies the OMA controller of the status of transmission or
reception, using this pin together with EOP.
OR01
15
28
0
DMA REQUEST (CHANNEL 1): This pin is used by the 82592 to
request DMA transfer. OR01 remains HIGH as long as the 82592
requires OMA transfers. Burst transfers are thus possible.
When the 82592 is programmed for Tightly Coupled OMA Interface,
the 82592 notifies the OMA controller of the status of transmission or
reception, using this pin together with EOP.
Symbol
Type
Name and Function
1-105
~OO~n..D!iVAlDOO~OOW
82592
oi'
'
Table 1. Pin Description (Continued)
Symbol
Pin No. Pin No.
Type
(DIP) (PLCC)
Name and Function
DACKOI
DACK
32
2
I
DMA ACKNOWLEDGE (CHANNEL 0): When lOW, this input signal
from the DMA controller notifies the 82592 that the requested DMA cycle
is in progress: This. signal acts similarly to Chip Select for data and
parameter transfers, using DMA channel O.
DMA ACKNOWLEDGE (CHANNELS 0 AND 1): When the DACK1 ICS1 I
EOP pin is programmed to CS1/EOP, this pin provides a DMA
.
acknowledge for both channels 0 and 1. Two DMA acknoWledge signals
from the DMA controller, DACKO and DACK1, must be externally ANDed
in this mode of operation.
DACK1
CS1/EOP
28
42
I
This is a multifunction, bidirectional pin which can be programmed to
DACK1 or CS1 IEOP during configuration. When it is configured for EOP,
it provides an open-drain output.
DMA ACKNOWLEDGE (CHANNEL 1): When lOW, this input signal
from the DMA controller notifies the 82592 that the requested DMA cycle
is in progress. This signal acts similarly to Chip Select for data and
parameter transfers, using DMA
channel 1.
CHIP SELECT (PORT 1): When lOW, the 82592 is selected by the CPU
for command or status transfer through PORT 1.
END OF PROCESS: A lOW output signal requests the DMA controller to
terminate the active DMA service.
1/0
ClK
35
5
I
1/0
CLOCK:1n the 40-pin DIP, this is only an input pin. A TTL-compatible
clock input to this pin provides the timing for the 82592 parallel.
subsystem.
In the 44-pin PlCC, this pin can be a clock input or output, depending on
the state of ClKSRC. If ClKSRC is strapped lOW, this pin is a clock
input which provides timing for the 82592 parallel subsystem. If ClKSRC
is strapped HIGH, the clock for the 82592 parallel subsystem is
generated from the internal clock generator. The ClK pin is then a clock
output and provides a clock signal whose frequency can be one-half of,
or identical to, the frequency of the internally generated parallel
subsystem clock, depending on the state of FREQ.
Note that the maximum frequency of the clock signal supplied by the
ClK pin is 8 MHz.
CLKSRC
o (lOW)
ClKSRC
NA
6
I
CLK
FREQ
Don't
. Care
Type
Signal
I
Clock
1 (HIGH)
1
0
. Internal Parallel
Subsystem
Clock Divided
by Two
1
0
0
Internal Parallel
Subsystem
Clock
Clock for the
Parallel Subsystem
Clock as provided on
the ClK pin.
Prescaled clock
generated from the
internal clock
generator.
Prescaled clock
generated from the
internal clock generator
CLOCK SOURCE: When strapped lOW, a clock signal on the ClK pin
provides timing for the parallel subsystem. When strapped HIGH, timing
for the parallel subsystem is internally generated from the clock
generator provided in the serial subsystem. The internal prescaler is
programmed during configuration to determine the frequency of the
clock for the parallel subsystem.
1-106
82592
The 82592 consists of a parallel subsystem, a serial
subsystem, and a FIFO subsystem (see Figure 1).
The 82592's CSMA/CD unit is highly flexible in implementing the CSMAlCD protocol. It can operate in
a variety of IEEE 802.3 and other CSMAlCD LAN
environments,
including
1BASE5
(StarLAN),
10BASE5 (Ethernet), 10BASE2 (Cheapernet), and
the IBM PC Network (Baseband and Broadband).
The programmable parameters include:
PARALLEL SUBSYSTEM
• Framing (IEEE 802.3 Framing or HDLC Framing)
• Address Field Length
.
FUNCTIONAL DESCRIPTION
Internal Architecture
• Station Priority
The parallel subsystem consists of a bus interface
unit (BIU), command and status registers, a 24-bit
general purpose timer, and three 16-bit event counters.
The BIU provides an 8- andlor 16-bit interface to the
external system bus. It handles all data transfers to
and from memory (at speeds up to 16 Mbytes/sec.),
accepts commands from the CPU, and provides
status to the CPU. There are two separate 8-bit 1/0
ports, Port 0 and Port 1; and two separate 8- or 16bit DMA channels, Channel 0 and Channel 1. The 8bit 1/0 ports are interfaced to the CPU via the data
lines Do-D7. The DMA channels can I:)e configured
for an 8- or 16-bit data path during initialization, and
are typically interfaced to an external DMA controller. When the 82592 is reset by hardware or software, the DMA channels are initialized for an 8-bit
data path. The CPU can then configure the 82592
for a 16-bit data path if desired. Once the DMA
channels are configured for a 16-bit data path all
subsequent DMA transfers are performed on the
data lines Do-D15. The two DMA channels are independent and can be used for high-performance operations such as simultaneous transmission and reception.
The 24-bit timer consists of a 24-bit maximum count
register, a 24-bit count register, and associated control bits in the command registers. Its clock source
can be the transmit clock or the parallel subsystem
clock. The timer can be programmed to halt or continue on a terminal count with or without causing an
interrupt.
The three 16-bit event counters can be programmed
to count valid frames, collided frames, and errored
(CRC or Alignment) frames. When these event
counters are used in Monitor mode, the 82592 is
capable of maintaining the network statistics by itself; i.e., without requesting DMA services or causing
interrupts to the CPU.
SERIAL SUBSYSTEM
The serial subsystem consists of a CSMAlCD unit, a
data encoder and decoder, collision detect and carrier sense logic, and a clock generator.
• Interframe Spacing
• Slot Time
• CRC-32 or CRC-16
Th~ C~MAlCD unit also has a mode of operation
which Implements deterministic collision resolution
(DCR). The DCR algorithm is fully compatible with
the MULTIBUSTM II Serial System Bus (SSB) specifications.
The encoder and decoder in the serial subsystem is
capable of NRZI, Manchester, and Differential Manchester encoding and decoding at bit rates up to 4
Mb/s in High-Integration Mode, and Manchester encoding at bit rates up to 20 Mb/s in High-Speed
Mo~e. A digital phase-lock loop is used in High-Integratl?n MOde to decode the receive data and to generate the synchronous receive clock.
The collision detect and carrier sense logic generate
the internal collision detect and carrier sense signals
for the CSMAlCD unit.
The 82592 implements several different internal,
logic-based collision detect mechanisms. Two of
these, Code V,iolation and Bit Comparison, are also
implemented in the 82588 (8-bit NMOS High Integration LAN Controller), and have been used in a variety of applications. The Code Violation method defines a collision where a transition edge occurs outside the area of normal transitions (as specified by
the data encoding method). For example, if there are
no mid-bit cell transitions in the Manchester encoded data, this method interprets that condition as a
collision. The Bit Comparison method compares the
signature of the transmitted frame to the signature of
the received frame. If the signatures are different, a
collision is assumed to have occurred. Two other
internal collision detect methods are Source Address Comparison and StarLAN CPS (Collision Presence Signal) Recognition. The Source Address
Comparison compares the source address field of
the transmitted frame to the source address field of
the receiVed frame. If the source addresses are different, it assumes that a collision has occurred resulting in data corruption in the source address field.
The StarLAN CPS Recognition method looks for the
specific collision presence signal defined by the
1-108
82592
Table 1. Pin Description (Continued)
Pin No. Pin No.
Type
Symbol
Name and Function
(DIP) (PLCC)
FREQ
NA
7
I
FREQUENCY: When strapped LOW, CLK has an output freqency
equal to that of the parallel subsystem clock. When strapped HIGH,
CLK has an output frequency one-half that of the parallel subsyst$m
clock, The state of this pin is relevant only when CLKSRC is strapped
HIGH.
X1/X2
12/13 25/26
I
HI.GH INTEGRATION MODE OSCILLATOR INPUTS: These inputs
may be used to connect a quartz crystal which controls the internal
clock generator for the serial subsystem. When CLKSRC is strapped
HIGH, the clock generator also provides a clock for the parallel
subsystem.
X1 may also be driven by a MOS-Ievel clock whose freqency is 8,10,
16, or 18 times the bit rate of Transmit/Receive data. X2 must be left
floating if X1 is connected to an external MOS clock.
12
I
HIGH SPEED MODE TRANSMIT CLOCK: This Signal provides the
25
T~
fundamental timing for the serial subsystem. The clock is also used to
transmit data synchronously on the TxD pin. For NRZ encoding, data is
transferred to the TxD pin on the HIGH to LOW clock transition. For
Manchester encoding, the transmitted bit center is aligned with the
LOW to HIGH transition.
Axe
13
26
I
RECEIVE CLOCK: This clock is used to synchronously sample data
on the RxD pin. Only NRZ data format is supported for reception. The
state of the RxD pin is sampled on the HIGH to LOW transition.
TCLK/CRS
I
CARRIER SENSE: In High-Speed Mode this pin is Carrier Sense, CRS,
21
35
and is used to notify the 82592 that the serial link is active.
0 TRANSMIT CLOCK: In High-Integration Mode this pin is Transmit
Clock, TCLK.
COT
34
I
COLLISION DETECT: This input notifies the 82592 that a collision has
20
occurred. In High-Speed Mode a collision is sensed by this pin only
when the 82592 is configured for external Collision Detect (external
means are then required for collision detection):ln High-Integration
Mode collisions are sensed by this pin regardless of the internal or
external Collision Detect configuration of the 82592.
RECEIVE DATA: This pin receives serial data. It must be HIGH when
RxD
16
30
I
not receiving.
TxD
17
31
0 TRANSMIT DATA: This pin transmits data to the serial link. It is HIGH
when not transmitting.
RTS
18
32
0 REQUEST TO SEND: When this signal is LOW the 82592 notifies the
channel that it has data to transmit. It is forced HIGH after a reset or
when transmission is stopped.
CTS/LPBK
19
I/O CLEAR TO SEND: An active LOW signal which enables the 82592 to
33
start transmitting data. Asserting this Signal HIGH stops the
transmission.
LOOPBACK: This pin, il) conjunction with a pull-down resistor, can be
programmed to provide an active HIGH loopback signal to the external
interface device.
1
POWER: + 5V ± 10%.
29
Vee
30
43
31
44
GROUND:OV.
9
21
Vss
10
22
11
~3
1-107
82592
IEEE 802.3 1 BASE5 standard. Other abnormal circumstances, such as no carrier for more than onehalf slot time in the receive channel during transmission, are interpreted as collisions by the 82592.
while in Port 0, the port logically becomes Port 1.
Software overhead associated with port switching is
eliminated if two chip select signals are supplied in
hardware.
In addition to these internal, logic-based collision detection methods, an external means of collision detection can be used in parallel by using the CDT
input pin.
The 82592 can be configured to have 4 or 6 bytes of
status registers in Port 0 (see Figures 4 and 7).
When configured to 4 bytes of status registers the
first three status registers (STATUS 0 through 2)
contain the information about the last command executed or the last frame received. The last status
register, STATUS 3, contains the state of the 82592.
When the 82592 is configured to 6 bytes of status
registers, the two additional bytes are used to report
a more complete status of the most recently received frame.
The clock generator in the serial subsystem is available only in High-Integration Mode and provides timing for the serial subsystem. The clock signal can
also be routed to the parallel subsystem, if so desired. The oscillator circuit is designed for use with
an external, parallel resonant, fundamental mode
crystal. The crystal frequency should be selected at
8X, 10X, 16X, or 18X the required serial bit rate.
The status of the timer and event counters is available in the Port 1 status registers as shown in Figure
8.
FIFO SUBSYSTEM
The FIFO subsystem is located between the parallel
subsystem and the serial subsystem. It consists of a
transmit FIFO, a receive FIFO, and FIFO control logic. The transmit and receive FIFOs are independent
of each other and individually provide. optiinal interfaces between the two subsystems which may have
different speeds. There is a total of 64 bytes that can
be used for the two separate FIFOs. During configuration these 64 bytes can be divided into ,one of four
possible combinations: 16 and 16 bytes, 16 and 48
bytes, 32 and 32 bytes, or 48 and 16 bytes for the
transmit and receive FIFO respectively. The FIFO
threshold is also programmed during configuration.
Programming Model-Register .
Overview
Figure 4 shows the 82592 internal registers that are
directly accessible through the 8-bit I/O ports: Port 0
and Port 1.
Figure 5 shows the Port 0 commands, and Figure 6
shows the Port 1 commands. The two separate I/O'
ports can be accessed at two different addresses
selecte~ CSO and CS1, or at one address.selected by CSO. When the hardware does not support
two chip select signals, port switch commands are
used to access both ports alternately at one ad, dress. If the SWT-TO-PORT-1 command is executed
82592 and Host Interaction
The CPU interacts with the 82592 through the system's memory and the 82592's on-chip registers.
The CPU creates a data structure in memory, programs the external DMA controller with the start address and byte count of the memory block, and issues a command to the 82592.
The chip select and interrupt lines are used to communicate between the 82592 and the CPU as shown
in Figure 9. The interrupt signal is used by the 82592
to attract the CPU's attention. The chip select Signal
is used by the CPU to attract the 82592's attention.
Note that the 82592 does not have any address
lines.
There are two kinds of transfers over the bus: command/ status and data transfers. The 8-bit command/status transfers are always performed by the
CPU. The 8- or 16-bit data transfers are requested
by the 82592, and are usually performed by a DMA
, controller. Table 2 shows the command/status and
data-transfer control signals. The CPU writes commands to the 82592 using the CSO (or CS1) and iNA
signals; and reads status using the CSO (or ~)
and RD signals. When data transfers are performed,
DACKO or DACK1 must be asserted by the DMA
controller instead of the Chip Select.
1-109
82592
PORT 0 COMMAND (WRITE ONLY)
7
0
COMMAND
Port 0 status (Read Only)
7
0
STATUS" 0
STATUS 0
STATUS 1-0
STATUS 1
STATUS 1-1
STATUS 2-0
60r4]
[ Bytes
St!rtus
of
STATUS 2
" Registers
STATUS 3
STATUS 2-1
PORT 1 COMMAND (WRITE ONLY)
7
0
STATUS 3
COMMAND
PARAMETER 0
PARAMETER 1
PARAMETER 2
Port 1 Status (Read Only)
7
0
STATUS 0
STATUS 1
STATUS 2
STATUS 2
Port 1 TImer/Counter Count Registers (Read Only)
23
16 15
I
8 7
0
TIMER
COU~ ~ER
1
COU~
ER 2
COU~
ER 3
Port 1 Timer/Counter Maximum Count "Registers (Read Only)
23
I
16 15
8 7
0
TIMER
COU~ ITER
1
COU~
ER 2
COU~
ER 3
290146-4
Figure 4. Programming Model-Directly Accessiblei=leglsters
(Accessible Through a-Bit 1/0 Port[sl)
1-110
82592
Port 0 Command
76543210
~r-'l
OPCODE
NOP
SWT-TOPORT -1
IA- SETUP
CONFIGURE
MC-SETUP
TRANSMIT
TOR
DUMP
DIAGNOSE
RETRANSMIT
ABORT
RCV - ENABLE,
ASSIGN-ALT-BUF
RCV -DISABLE
STOP- RCV
FIX-PTR
RLS-PTR
RESET
....- - - - - + C H N L ( CHANNEL 0
CHANNEL 1
STATUS 0
'--------+ PTR { ~~:~~; ~
STATUS 3
..______-+ IN -
0 (CHNL = 0)
O(CHNL=1)
1
2
3
4
5
6
7
12
13
8'
9
10
11
15 (CHNL =1)
15 (CHNL=O)
14
o
1
00
01
10
11
ACK { NO ACKNOWLEDGE 0
ACKNOWLEDGE
1
290146-5
Figure 5. Port 0 Commands
Port 1 Command
76543210
TC/GP { GENERAL PURPOSE
TIMER/COUNTERS
NOP
SWT-TO-PORT-O
SET-TS
RST-TS
LCL - PWR - OWN
RMT - PWR - OWN
FIX-PTR
RLS- PTR
RESET
SEL- RST
~OPCODE
(TC/GP=O)
(TC/GP
NOP
START
STOP
RESUME
LD.!cSTART
ACK-INT
COUNT
START- ALL- COUNTERS
SET-VAL
SET-CONF
RO-MAX-COUNT-VAL
RD-COUNT-VAL
RESET
=1)
STATUSO
L.._ _ _ _ _ _~ PTR { STATUS1
~~~~~~~
(TC/GP =0)
(TC/GP = 1)
{
-
1
5
7
8
9
12
13
14
15
0
1
2
3
5
7
8
9
10
11
12
13
14
00
01
10
11
00
gg~~~:~
01
10
11
ACK { NO ACKNOWLEDGE
ACKNOWLEDGE
Figure 6. Port 1 Commands
1-111
1
o
TIMER
COUNTER3
..______-+ IN -
o
o
1
290146-6
82592
7
6
5
INT I RCV I EXEC I CHNL I
EVENT
STATUS 0
~-L__~-J__~__~~__~~
RESULT 1
STATUS1.()
RESULT 2
STATUS 1·1
~----------------------~
RECEIVE BYTE COUNT (LOW)/FRAME
INT
STATUS2.()
COUNTER
CHNL I
RCV
I
EXEC
I
CHNL
I
o
EVENT
STATUS 0
RESULT 1
~_,-_,-RE_CE_I"TVE_B_YT--rE_COU_NT-r-(H_IG_H.:.,),....-_r--iSTATUS 2·1
RCV I RCVSTATE
I
I
BUF.CHAIN'GI EXEC I
EXEC
No. OF BUF. I CHNL I
STATE
~------------------------~
RCV
STATUS 3
I
RCVSTATE
CHNL I
Status Reglsters-6 Bytes
I
RESULT 2
BUF.CHAIN'G I EXEC I
EXEC
No. OF BUF. I CHNL I
STATE
Status Reglsters-4 Bytes
Value
(Status 0)
Events
o (CHNL =
CMOS·
1)
IA-Setup-Done
Configure-Done
2
MC-Setup-Done
3
Transmit-Done
4
TOR-Done
5
Dump-Done
6
Diagnose-Passed
7
End-of-Frame
8
Request-Next-Buffer
9
Reception-Abortl;ld
10
R~transmit-Done
12
Execution-Aborted
13
Diagnose-Failed
15
'Available only after Hardware or Software Reset.
Figure 7. Port 0 Status Registers
1-112
STATUS 1
STATUS 2
STATUS 3
inter
82592
7
6
5
INT
C>---------------t
82592
CSl
C~------_t
OACK1/CS1/EOP
OACKOD---t
OACK1D--L
l-_~-----I
OACKO
ORQO
<:l------------------_t ORQO
ORQl
<:1-----------------"1 ORQl
~~~----------------_t~
WR c:~----------------; WR
CSOC:~----------------~ CSO
290146-12
Figure 13. Demultiplexing DACK/CSlIEOP Pin
Table 3. Transmit/Receive Status Encoding on
DRQandEOP
DRQ
EOP
0
Hi-Z
Idle
1
Hi-Z
DMA Transfer
0
0
Transmission or Reception
Terminated OK
1
0
Transmission or
Reception Aborted
Status Information
4.
Other Enhancements
5.
Compared to the previous generation LAN controllers such as the 82588, the 82592 has many functional and performance enhancements. This section
lists some of these enhancements which are not
covered in other sections.
1. Multi-lA-The 82592 implements multiple-individual address (Multi-IA) filtering. It can receive more
than one IA frame in this mode.
2. Power Down Modes-Two power down modes,
Local Power Down and Remote Power Down, are
available. When the 82592 is in Remote Power
Down mode, it can be powered up remotely by
sending a special frame to it.
3. Automatic Padding and IEEE 802.3 Length
Field-If a frame to be transmitted is shorter than
6.
7.
8.
1-117
the configured Slot Time, the 82592 automatically
appends pad bytes up to the shortest frame greater than the Slot Time. If the data field of a received frame is longer than the byte count indicated in the Length field, the extra bytes are stripped
automatically according to the Length field. Erroneous conditions are detected and, reported by
the 82592. An example of such conditions is reception of a frame which is shorter than the byte
count indicated in the Length field.
Automatic Retransmission on Collision During
Preamble-The 82592 can be programmed to retransmit automatically if it detects a collision during transmission of the preamble.
On-Chip Jabber Inhibit Function-The 82592
can be programmed to provide an on-chip jabber
inhibit function.
CRC Transfer to Memory-The 82592 can be
programmed to transfer the CRC field of a received frame into memory.
Loopback Signal to the 82C501-The 82592
can be programmed to provide an active High
loopback Signal to the 82C501 (see Figure 14).
StarLAN-The 82592 can be configured to recognize the IEEE 802.3 1BASE5 Collision Presence Signal (CPS). In this mode it also delays deactivation of the RTS signal at the end of a frame
transmission in order to insert an end-of-frame
marker as required by the standard.
inter .
82592
APPLICATIONS
The 82592 can be used in a variety of applications.
When it is used in High-Integration Mode it implements most of the' Data Link and Physical Layer
functions required by the IEEE 802.3 1BASE5
(StarLAN) and the IBM PC Network (Baseband and
Broadband). When it is used in High-Speed Mode it
can work with the 82C501 and the 82502 for IEEE
802.3 10BASE5 (Ethernet) and 10BASE2
(Cheapernet) implementations.
for the 82592 and dual-port memory control for the
static RAM. The 82592 is interfaced to the 82C501
to provide the Ethernet channel and then to the
transceiver to provide the Cheapernet channel. Due
to the CMOS process used for these chips, such a
board uses much less power than a board based on
NMOS or bipolar chips.
82C501
82592
74HCT04
If the desired network requires determinism, the
82592's Deterministic Collision Resolution (OCR)
method can be used.
CTS/lPBK
Figure 15 shows a block ' diagram of, an
82592/82560 Cheapernet adapter board. The
82560 provides the Tightly Coupled DMA Interface
290146-13
Figure 14. Loopback Output to the 82C501
1-118
PC I/O CHANNEL
13
2
N
l-
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IC
C
CD
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HRDY
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ClK
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~
~
0
00
2i~
DECODER
I
~CS
ROM
XCVI
XCV2
GCS
\8
00-07
\8
DATA (00-7)
or
MOE
CSl
CS
-
CSH
MAO-MAI2
13
SRAM
ADDRESS
WE
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I\)
Q)
..... en
.....
0
<0
ADDRESS
DATA
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.
l
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~rt
"l1li
CD
N
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0
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CD
III
..
'-
'tI
CD
-..
liii~
:::s
CD
l>
~
III
N
\8
0
i.....:........
015-00
DATA (DB-IS)
or
CS
ADDRESS
82592
8
1<§
ClK
CL
'tI
CD
0
~
16
I~ I~
16
RESET
WE
0
x
I-
I
0
X
'"
I~
! T!
82C501
I
~ t.A.1 t.A.1 t.A.1 ~
~
~
SRAM
j
r
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~~-!
IiiiiI
IF'
c:::::J
~
CNET XCVR
RG-58 COAX
~
BNC
T - CONNECTOR
~
290146-14
2a
~
inter
82588
High Integration LAN Controller·
• Integrates ISO Layers 1 and 2
-CSMA/CD Medium Access Control
(MAC)
- On-Chip Manchester, NRZI
Encoding/Decoding
- On-Chip Logic Based Collision
Detect and Carrier Sense
• 2 Clocks per Data Transfer
• User Configurable
- Up to 2 Mb/s Bit Rates with On-Chip
Encoder/Decoder (High Integration
Mode)
- Up to 5 Mb/s with External Encoder/
Decoder (High Speed Mode)
• Supports Mid-Range Industry Standard
LANs
- StarLAN (IEEE 802.3 1BASE5)
- IBM/PC Network-Baseband and
Broadband
• No TTL Glue Required with iAPX 186
and 188 Microprocessors
• Network Management and Diagnostics
- Short or Open Circuit Localization
- Station Diagnostics (External
Loopback)
- Self Test Diagnostics
Internal Loopback
User Readable Registers
• High Level Command Interface
Offloads the CPU
• Efficient Memory Use Via Multiple
Buffer Reception
The 82588 is a highly integrated CSMAlCD controller designed for cost sensitive, mid-range Local Area
Network (LAN) applications, such as personal computer networks.
At data rates of up to 2 Mb/s, the 82588 provides a highly integrated interface and performs: CSMAlCD Data
Link Control, Manchester, Differential Manchester or NRZI encoding/decoding, clock recovery; Carrier Sense,
and Collision Detection. This mode is called "High Integration Mode." In the 82588 "High Speed Mode", the
user can transfer data at a rate of up to 5 Mb/s. In this mode the physical link functions are done external to
the 82588.
The 82588 is available in a 28 pin DIP and 44 lead PLCC package and fabricated in Intel's reliable HMOS II 5
volt technology.
..".
"
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.
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t~K
II
IIIMT
II
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CSMA/CD
iiielu
11
11 Tloon
' - -_ _...J
231161-2
MAC
Figure 2. 82588 Pin
Configuration (DIP)
CONTROLLER
" ,
"
"" "
" "
SYSTEM INTERFACE
,." "
,."
DATA LINK
SERIAL INTERFACE
231161-1
"
" "
" "
" "
"
"
"
"
"
"
"
'""
"
38
N82588
(TOP VIEW)
1819:1.02122232"25262728
'"
"
NC
El!§jTCiJ(
""
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n
!!
~
£=>
.
ii1
GND
--,.
LOCAL BUS
DACKI/EOP
--,.
I
I
INTERFACE
T
~
I
I
DMA MACHINE
T
cs--,.
DROO
OROI
CD
N
en
0)
CI
IORD/WWR
--,.
IOWR
\lOt
3
INT
Vee
DACKO/DACK
v
10
(
INTERRUPT
~
l§!
UNIT
~
.--------------------------~-----------------
©
~
i'"
~
i
I~I
IiiiiI
I~
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,
290180-1
'iiiJ
@
2.eJ
~
~
~
<=
@
~
inter
82560
Table 1.82560 Pin Description
Symbol
Pin No.
Type
Name and Function
Vee
5,23,57
I
POWER: Connected to
Vss
10,29,43,63
I
GROUND: Ground connection.
ClK
11
I
CLOCK INPUT: This is the system clock input for the 82560. It
controls the internal operations of the 82560 and its cycle timing.
RESET
42
I
RESET: Active high. When active it resets the 82560 to a known
passive state.
00- 07
40, 41, 44-49
1/0
Ao-A12
26-39
I
ADDRESS LINES: The 13 address lines select either an 82560
register, or an address in the local Memory.
HFO, HF1
25,24
I
HOST FUNCTION SELEOT: These two inputs indicate the type of
access requested by the host. These signals are generated by
external decode logic and are completely asynchronous to the
825,60 system clock. The proper combinations for each access
type are shown below:
HOST FUNCTION
HF1
HFO Access Type
1
1
Idle (No. Access 'Being Requested)
Request to Access Shared Portion of local
1
0
Memory
Request to Access 82560 Registers or the Slave
0
1
Controller (SCS)
Reguest to Access External PROMs or latches
0
0
(GCS)
RD
17
I
READ: Active low. This signal is used to indicate the direction of
the host transfer. When active, data is being read from the
destination (RAM, 560, or GCS port).
HROY
20
0
HOST READY: Active high. This Signal from the 82560 is activated
when the device on the local B~s of the LAN adapter is ready to
accept data (write cycle) or to output data (read cycle). When no
access is being requested by the host (i.e., both HFO and HF1 are
high), this signal is tri-stated in the normal mode, and is driven high
in the pipeline mode.
XCV1
22
0
TRANSCEIVER ENABLE 1:. Enables the transceiver that connects
the lower byte of the host and local data buses. In pipeline mode it
enables the transceiver during non-memory host cycles.
XCV2/PCS
21
0
TRANSCEIVER ENABLE 2: Enables the transceiver that connects
the upper byte of the host and local data buses. In pipeline mode it
enables the latch during memory host cycles.
INT
50
0
INTERRUPT OUT: This signal is a logical pR of all enabled
interrupt requests. When active it indicates an interrupt request to
the CPU. This signal is tristated after reset.
GCS
59
0
GENERAL CHIP SELECT: Active low. This signal is asserted by
the 82560 when the host requests access to external ROMs or
latches.
+- 5V power supply.
82560 DATA BUS: Tri-state bus. Used for programmatic access to
the 82560 registers. They are also used in the tightly coupled
interface (TCI) mode.
1-148
inter
82560
Table 1.82560 Pin Description (Continued)
Pin No.
Type
Name and Function
BEO
18
I
BYTE ENABLE: Active low. This signal is asserted in 16- or 32-bitwide host memory cycles to select the lower memory bank. It may be
connected to the processor's Ao pin.
BE1
19
I
BYTE ENABLE 1: Active low. This signal is asserted in 16- or 32-bitwide host memory cycles to select the upper memory bank. It may
be connected to the processor's SHE Signal. These two signals are
connected as follows:
Symbol
Host Bus
8-Bit
8-Bit
16-Bit
16-Bit
32-Bit"
Local Bus
8-Bit
16-Bit
16-Bit
32-Bit
32-Bit
BEO
0
SAO
SAO
SA1
BEO
+
BE1
BE1
0
1
SHBE
SA1
BE2 + BE3
"80386 address pins
+ stands for logical OR
DRQO
54
I
DMA REQUEST CHANNEL 0: Active high. This is an input from the
LAN controller or other peripherals, it requests DMA service. The
DMA cycles are run on an on-demand basis, and are prioritized
between themselves (two channels) and with the host cycles on an
alternating basis. In 82590 Tightly Coupled mode this signal is
sampled by the ~2560 at the last clock of the Read or Write signal
along with DAC 1IEOP to determine the state of the transmit or
receive process (see Tightly Coupled Interface for more details).
DRQ1
52
I
DMA REQUEST CHANNEL 1: Active high. This is an input from the
LAN controller or other peripherals, requesting DMA service. The
DMA cycles are run on an on-demand basis, and are prioritized
between themselves (two channels) and with the host cycles on an
alternating basis. In Tightly Coupled mode this signal is sampled by
the 82560 at the last clock of the Read or Write signal (see Tightly
Coupled Interface for more details).
DACKO/DACK
55
0
Dual Function: This is a dual function pin which serves as DACKO,
DMA acknowledge for Channel 0, in all modes except the Tightly
Coupled Interface mode. It serves as DACK, DMA acknowledge for
both channels, in Tightly Coupled Interface mode.
DMA ACKNOWLEDGEO: Active low. Acknowledge DMA requests
on channel O. During special chip select cycles, this signal is
controlled by the CPU.
DMA ACKNOWLEDGE: Active low. Acknowledge DMA requests on
either channel 0, or channel 1. It operates in this mode only when
programmed for Tightly Coupled Interface with the 82590 or 82592.
This pin can be directly connected to the DACKO/DACK pin of the
82590 or 82592 tA~ controllers.
DACK1/EOP
53
1/0
Dual Functi9n: This is a di.J?1 function, bidirectional pin which serves
as DACK1, DMA acknowledge for channel 1, in all modes except
8259X Tightly Coupled Interface mode. It serves as EOP, End of
Process indicator, an input, during this Tightly Coupled Interface
mode.
DMA ACKNOWLEDGE1: Output. Active low. DMA acknowledge for
channel 1. During Special Chip Select (SCS) cycles this signal is
controlled by the CPU and can be used for accessing the 8259X port
1. The output level is determined by the address of the SCS.
1-149
inter
82560
Table 1.82560 Pin Description (Continued)
Symbol
Pin No.
Type
DACK1/EOP
53
110
END OF PROCESS: Input. In the Tightly Coupled Interface mode,
this input, along with the DRQ pin, is sampled by the 82560 at the
last clock of the Read or Write signal. The combination of the two
pins indicates the status of the Transmit or Receive process. When
low, the EOP signal Indicates that the active DMA service should be
terminated.
10WR
56
0
I/O WRITE. Active low. This is the write strobe to the LAN controller
or 110 device. It is asserted when data is being written to the LAN
controller by either the Host CPU or the 82560 internal DMA. During
pipeline read transfers it is the write control signal to the buffer.
IqRD/MWR
58
0
Dual Function: Active low. This signal is used for two different
operations. It is a control signal during read cycles from the LAN
controller or another 110 device. It is a write strobe during write
cycles to the local memory.
I/O READ: Active low. It is asserted when data is being read from
the LAN controller by either the host CPU or the 82560 internal DMA.
During pipeline write transfers it is the read control signal to the
buffer.
MEMORY WRITE: Active low. It is asserted when data is being
written to local memory.
INTR
51
I
INTERRUPT REQUEST: This signal when active indicates an
interrupt request. It is usually connected to the interrupt output of the
LAN controller. It may be programmed as active high or low, level or
edge triggered, and it can also be masked.
9-1,68
0
MI;:MORY ADDRESS 0-12: These 13 address lines can support two
8·kilobyte or 8·kiloword banks of static memory.
CSL
62
0
RAM CHIP SELECT (LOW BANK): Active low. This Signal is
activated during all static· RAM accesses in 8·bit mode, even·byte
accesses in 16·bit mode, and even·word accesses in 32-bit mode.
CSH
61
0
RAM CHIP SELECT (HIGH BANK): Active low. This signal is
activated during odd-byte accesses in 16-bit mode or odd-word
accesses in 32-bit mode.
MOE
60
0
MEMORY OUTPUT ENABLE: Active low. This signal is used to
enable the memory array's output buffers during memory read
cycles.
GPI
16
I
GENERAL PURPOSE: Input. This is a general purpose input pin, its
state may be read by the CPU.
CS
12
0
CHIP SELECT: Active low. This pin is normally connected to the
Chip Select input of the LAN controller or other peripherals. It is
activated during non-DMA accesses to the LAN controller. The CPU
activates this signal when it accesses addresses 0, 1, 2, or 3 in the
Special ChipSelect address space of the 82560.
13,14
I
These pins are reserved and should be tied to Vee.
MAO-12
RSV1, RSV2
Name and Function
1-150
inter
82560
v..
MOE
CLK
GCS
~
10RO/MWR
RSVI
Vee
RSV2
IOWR
NC
OACKO/OACK
GPI
OROO
Rii
OACKI/EOP
BEO
OROI
BEl
INTR
HROY
INT
XCV2/PCS
07
XCVI
06
Vee
05
HFI
04
HFO
03
M
~
c
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 8 0
§~
II<
290180-2
Figure 2. 82560 PLCC Pinout
.
A
<
Host Bus
~
-'
III
III
z~
'"0
II<
4(
l
Host Interface and
Decode Logic
I.
"'
J
I Arbitration
L Logic
III
III
...J
0
'"0
....
Z
II<
0
0
4(
<. .__
CYCLE _ _IO_LE_ _
X . . __
HO_S_T_ _
><. .__ ><;
O_MA
_ _....
H_OS_T_ _
290180-4
This Diagram Assumes:
The default priority bit to be 1 (bit 7 of the master mode)
1/0 or MEM wait states to be 1 clock (Tw = 1)
Non-Pipeline Mode
In the case of host read cycles (in any mode) or host writE! cycles (in pipeline mode only), "Twh" cycles
will be asserted in addition to "Tw", between "T1" and "T2" of the host cycles
Figure 4. 82560 Arbitration Cycles
,Sh and
Transfer (TTSF). The·machine cycle, begins when. a
request (HF or ORO) becomes active and the 82560
is in the idle state (TIDLE>. The requests are synchronized and then undergo arbitration (TA). Once arbitration is completed, the transfer cycle (TTSF) begins.
1. The CPU configures the 82560 by writing to configuration registers.
2. The CPU accesses the local memory (through the
82560) and prepares a block of transmit frames.
3. The CPU writes the proper addresses into the
82560's OMA address registers, (base, current, lower limit upper limit and stop).
4. The CPU writes to the 82560's OMA control registers to configure and enable the channels.
5. The CPU issues a transmit command to the
82590.
6. The 82560 responds to the 82590's OMA request
by transferring data from memory to the 82590.
7. Upon completion of transmission, the 82560
sends an interrupt to the CPU.
8. The CPU reads the 82560 interrupt control register to find the source of the interrupt.
9. The CPU issues a command to the 82590 to clear
its interrupt. (If the source of the interrupt was the
82590.)
10. The CPU acknowledges the 82560 interrupt by
writing a "1" into the corresponding interrupt control
register bit(s).
APPLICATIONS
Figure 9 shows a buffered, non intelligent StarLAN
adapter for the IBM PC bus (using the 82560 and the
82590). Figure 10 shows a buffered, nonintelligent,
Ethernet adapter for the IBM PC bus (using the
82560, 82592, 82C501 and the 82502).
Synchronization (TS) is completed on the falling
edge of the clock. If the previous cycle was non-idle,
arbitration begins and is completed within one clock
period (by the next falling edge of the clock).
The Transfer cycle consists of the following sequential states: the first transfer state (Tl), memory or 110
wait ,states (Tw), and the second transfer state (T2).
There may be another transfer state, Twh (wait host),
during host read or pipeline cycles. When no re, quests are pending, and the 82560 is not in the
transfer or arbitration cycle, It is said to be in the idle
state (TIDLE). If the previous cycle was non-idle, the
arbitration period (TA and T2 of the previous cycle
will be done in parallel. (See Figure 4.)
Tw is the programmable portion of the transfer cycle. It can be zero to three clocks long depending on
the programmed memory or 110 access delays. If
the programmed delay is zero, then there will be no
Tw; the first state of the transfer cycle will be T 1.
Ouring T2 the transfer cycle is completed unless the
cycle is a host read cycle. In that case the cycle will
be 'extended by inserting TwHo The 82560 will remain
in Twh until the HF lines are deasserted. Once HF
Unes are deasserted, T2 will begin and one clock
period later the bus cycle is complete. '
1-164
PC I/O CHANNEl
I"
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DECODER
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.
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RESET
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290180-19
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JDECODERJ
:!!
14 I
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.........
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L-+-_-II HRDY
I~
~
I~
.:
-----":":"'1~t-t--~ ClK
~
:.:
82560
r-+-"'-~ RESETII>.
I~
. 1! ~
L
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la; ; 111 I~a°~ -~ °~ I~'" I~~
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82592
015-0014
,16
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.I' II:]C-:.
I
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290180-20
c::::J
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~
82560
*Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Case Temperature (TC)
under Bias ...................... O·C to + 85·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on any Pin with
Respect to Ground ....... - 0.5V to Vee + 0.5V
NOTICE: Specifications contained within the
fol/owing tables are subject to change.
D.C. CHARACTERISTICS TC = O·Cto + 85°C. Vee = +5V ±10%
ClK pin has MOS levels (see VMll. VMIH) All other signals have TTL levels (see Vil. VIH. VOL. VOH).
Symbol
Parameter
Min
Max
Units
V
Test Conditions
Vil
Input low Voltage (TTl)
-0.5
+0.8
VIH
Input High Voltage (TTl)
2.0
Vee + 0.5
V
IOl
IOH
= 3.2 rnA
= -400,...A
VOL
Output low Voltage (TTl)
0.45
V
VOH
Output High Voltage (TTl)
2.4
Vee
V
VMll
Input low Voltage (MOS)
-0.5
0.6
V
VMIH
Input High Voltage (MOS)
III
Input leakage Current
±10
,...A
o=
ILO
I/O leakage Current
=F10
,...A
0.45
CIN
Capacitance of Input Buffer
10
pF
COUT
Capacitance of Input/Output Buffer
20
pF
= Vee -0.45
= VOUT = Vee -0.45
FC = 1 MHz
FC = 1 MHz
Icc
Power Supply Current
50
rnA
tOMHz
A.C. CHARACTERISTICS
Symbol
Vee - 0.6 Vee + 0.5
V
VIN
Cl on all outputs is 50 pF. The user should add 0.2 ns/pF up to 100 pF
Parameter
Min
Max
Test Conditions
SYSTEM CLOCK INPUT PARAMETERS
T1
ClK Cycle Period
100
(Note 1)
T2
ClKlowTime
45
. (Note 1)
45
(Note 1)
T3
ClK High Time
T4
ClK Rise Time
5
(Note 2)
T5
ClK Fall Time
5
(Note 3)
HOST ACCESS CYCLE-NON PIPELINE MODE PARAMETERS
T6
HF or DREQ Setup Time
T7
HF Active Time (low)
T8
HF Inactive Time (High)
T9
HF to HRDY low
T10
HF Active to HDRY High
T11
HRDY High to HF Inactive
10
(Note 5)
2*T1 + 10
T1 +10
50
2*T1 +50
0
1-167
(Note 4)
(Note 9)
(Note 5)
inter
82560
A.C. CHARACTERiSTICS
CL on all outputs is 50 pF. The user should add 0.2 ns/pF up to 100 pF (Continued)
Symbol
Parameter
Min
Max
Test Conditions
HOST ACCESS CYCLE-NON PIPELINE MODE PARAMETERS (Continued)
T12
HF Inactive to HRDY Float
T13
HF Active to XCVR Lines Low
T1+T2
T14
HF Inactive to XCVR Lines High
(Note 7)
T15
HF Active to RD Low
T16
RD Hold after HF Inactive
T17
HF Active to Input Add. Valid
T18
Address Hold after HF Inactive
T19
HF Active to 82560 Data Valid
75
2"T1 +T2+75
(Note 6)
75
T1 +T2+10
0
-20
(Note 8)
0
"
T20
Data Hold after HF Inactive
T21
HF Active to 82560 Add Valid (MAn).
T22
Add Valid or Chip Select Active Time
T23
HF Active to CS Active
T24
CS Enveloping Controls
T25
Control Active Time
T26
HF to Data Valid
T27
Data Hold after HRDY High
3*T1 +80
(Note 9)
2*T1 +T2+75
(Note 9)
T1 +T2
2*T1
(Note 10)
2*T1 +T2+50
(Note 9)"
20
(Note 11)
(Note 11)
3*T1-30
(Note 12)
HOST ACCESS CYCLE-PIPELINE MODE PARAMETERS
(Note 9)
2*T1 +75
(Note 6)
HF Active Time
T29
HF Active to Port CSActive
T30
HF Inactive to HRDY Low
75
T31
HRDY Low to HRDY High
(Ncite 14)
T32
Port CS Active Time
T33
HF Inactive to Buffer Write
T34
Write Active Time
T1 +10
(Note 13)
T28
2*T1
(Note 14)
10
T1-10
T1 +10
DMA PARAMETERS
T35
DR an High or INTR to Clock
Lqw Setup Time
(Note 15)
50
T36
DROn Low to Clock Low, Hold Time
10
T37
EOP Pulse Width
T1
T38
Address Delay Time
T2+75
T39
CS, CSn, DAKn Delay Time
T2+50
T40
CSn Delay Time (Slave to SRAMFlyby)
50
T41
IORD_MWR, IOWR Delay Time
45
T42
IORD_MWR, IOWR Active Time
(Note 16) ,
1-168
(Note 16)
inter
82560
A.C. CHARACTERISTICS
CL on all outputs is 50 pF. The user should add 0.2 ns/pF up to 100 pF (Continued)
Symbol
I
Parameter
I
Min
I
Max
I
I
I
75
I
I
Test Conditions
INTERRUPT PARAMETERS
T43
T44
I
I
Interrupt Delay Time
Interrupt Gap
I
I
3'T1-10
RESET PARAMETERS
T45
T46
I
I
Reset Setup Time
Reset Active Time (High)
I
I
"For pin HRDY 4 mA.
50
4'T1
I
l
I
I
NOTES:
1.
2.
3.
4.
Measured at Vcc/2.
3.2V to 1.BV.
1.BV to 3.2V.
The following configuration affect the HRDY output going active (high).
Legend:
TID-The configuration of HRDY delay (master mode register, TID = 0,.5,1.5,2.5).
TIO-The configuration of I/O access delay (Control register,
TIO = 0,1,2,3 ).
TMEM-The configuration of MEM access delay (Control register, TMEM = 0,1,2,3).
"If bit 5 of Register at Address 1BH then (TID + 2)"Tl + 75
else [TID + TIO(or TMEM) + 2)"Tl + 75"
5. The user should not that the XCVR lines goes inactive immediately after HF inactivation.
6. Provided that the HOST wins arbitration.
7. In the case of HOST write cycle the XCVR lines will go high at the end of the B2560 cycle even if HF lines are still active.
In the case of HOST read cycles, the B2560 will terminate the local cycle after HF lines are inactivated.
B. Address lines are latched at the end of Tl of 82560 HOST bus cycles.
9. The maximum time specified assumes that the HOST wins the arbitration. If the HOST loses the arbitration to a DMA
request two possible scenerios are:
a) Arbitration lost to a single DMA cycle. In this case [(greater of TIO and TMEM) + 2)*T1 should be added to the
max. time.
b) Arbitration lost to a DMA cycle which is followed by four locked DMA cycles. In this case [(greater of TIO and
TMEM)"5 + 10)*Tl should be added to the max. time. This might happen in the rare case when the HOST request
coincides with the last receive or transmit transfer, in the TCI mode.
10. [TIO(or TMEM) + 2)"T1+ 10.
In the case of long (HF) HOST memory read requests, it would be extended until the request is removed.
11. Min = [TI0(orTMEM)+I)*Tl-l0, Max = [T10(orTMEM)+I)"Tl+10.
12. This parameter depends on Tl0. In terms of machine states, data remains valid until the end of the cycle (end of state
T2).
13. (TMEM + 2)"Tl +75+ Tsystem.
Tsystem = delay from HRDY to HF inactive.
This maximum time refers to a second memory request immediately following a first one, assuming that the first one
was not delayed by a DMA cycle.
14. [TIO(or TMEM)+2)"Tl +75.
15. This is an asynchronous signal (DROn only in its leading edge). It is internally synchronized. Meeting this parameter,
assures recognition on the next clock.
16. Min = [(greater of TIO and TMEM) + 1)*Tl + T2 + 10
Max = [(greatefof TIO and TMEM) + 1)'Tl + T2 + 10
1-169
inter
82560
A.C. TESTING INPUT & OUTPUT WAVEFORM
2.4
0.45
=x
1.5 -TEST POINTS -
1.5
SYSTEM CLOCK TIMING
x=
vee- 0.6
0.6
290180-21
A.C. Testing Inputs are Driven at 2.4V for a Logic "1"
and 0.45V for a Logic "0". Timing Measurements are
made at 1.5V for both a Logic "1" and "0".
i+---T1---1
290180-22
WAVEFORMS
HOST READ CYCLE-NON PIPELINE MODE
eLK
--,
T.
To
T1
w-" w-'
~
-Tl-.
-T6
-
T7
Tw
T2
Ti
Ti
~~
~
I-oT3~
H
T8-
-1
'\
---
I--
T9 ---
f4- TIl
f. K'12
TlO
,..~
HRDY
I--
Tl3---
f4-r---Tl4
-I
I
r
.....
I- 15-1
~~171l.
AO-A12. BMn
I
tTl 6
I
~ Tl8l
I
VALID
HOST READ FROM 82560
~Tl19--T1
Data Valid
~1-T20-
t:1
H~ST REA~ FROM I/O or SRAM
I
l- r-T21
TI2
~ f--T23
A2
MAO-12,eSn
-T21
I
f4--T24
T24
f4--
I---T25T24 f4--
f4-I---
T42-
-
290180-23
1-170
inter
82560
WAVEFORMS (Continued)
HOST WRITE CYCLE-NON PIPELINE MODE
Ts
elK
~
Ta
--TS
-
!--Tl--T7
-
Tg ...
Tw
Tl
~ Lr ~
~
TS ...
...
TI
~ ~ \..J
j....T3~
TS-
l-
H
\.
f4
Tll
f,o
TlO
,..1- K12
HRDY
Tl3 ....
n
T2
f4 r--Tl4
4-
H
I
AO-A12, eMn
"Tl
... TlS--1
I
I
VALID
HOST WRITE TO 825S0
Data Valid
r-
T2
I
j-1 I
I
"'-T27-
j
_I
HOST WRITE TO I/O or SRAM
I
I-I--T21
Tj2
i-I--T23
A2
MAO-12
...
T24
i'--T24
,
10RDjMWR,IOWR
I-
1
1---
25 290180-24
1-171
inter
82560
WAVEFORMS (Continued).
HOST READ CYCLE-PIPELINE MODE
eLK
.....,
ls
To
T1
T2
Ti
Ti
Ti
u--" ~ w-' ~ ~ ~
~
..... T6r---T28
T8
I
"-
..... 30if-T31HRDY
"-
·V 1
7
8M"
.I.
T1
1-1
VALID
.I.
-
1
I
"-
ro--r-T21
T22
r--
~+--T23
T22
r----
~-T29
T32-
MAO-12,
I--T24
I.....
I .....
I--T24
1
"'T33 I---T34
~, ~T2~!~
I--T42
I
I
I--r
4
II
290180-25
1-172
82560
WAVEFORMS (Continued)
HOST WRITE CYCLE-PIPELINE MODE
ClK
.....,
~ 0- ~
~
.... 0T6i-t-T28
T8
r
~T~I
I,
3~~ r-T31-"1
....
T32-
HROY
8Mn
u-0-
,
-T1j-1
VALID
I
I
i-r-T21
T22
r---
I-~T29
T32
I----
MAO-12
~-T23
r----
r. .
I
~
H
!-" T24
~T4i-
I
290180-26
DMA FLYBY CYCLE-SLAVE TO SRAM
T.
To
T1
TW
T2
TI
TI
ClK
OROn
...-.l.-""'-+__!-_+_--1_+..I...{
i'-I---~~__t
FOP --+---+--!--+---1-~+-
__~
MAO-12
~CKn --+---r--~~+-_-+__+-~
290180-27
1-173
inter
82560
WAVEFORMS (Continued)
DMA FLYBY CYCLE-SRAM TO SLAVE
Ts
To
T1
TW
T2
TI
, TI
elK
OROn
t.lAO-12
T39
IOWR ---+----+----~+-~
--+---1"1
290180-28
1-174
inter
82560
WAVEFORMS (Continued)
INTERRUPT
eLK
INT
INTR
_+-_-+---"
290180-29
RESET
290180-30
1-175
APPLICATION
NOTE
AP-235
November 1986
An 82586 Data Link Driver
CHARLES YAGER
Order Number: 231421-002
1-176
inter
AP-235
INTRODUCTION
This application note describes a design example of an
IEEE 802.2/802.3 compatible Data Link Driver using
the 82586 LAN Coprocessor. The design example is
based on the "Design Model" illustrated in "Programming the 82586". It is recommended that before reading this application note, the reader clearly understands
the 82586 data structures and the Design Model given
in "Programming the 82586".
"Programming the 82586" discusses two basic issues in
the design of the 82586 data link driver. The first is
how the 82586 handler fits into the operating system.
One approach is that the 82586 handler is treated as a
"special kind of interface" rather than a standard I/O
interface. The special interface means a special driver
that has the advantage of utilizing the 82586 features to
enhance performance. However the performance enhancement is at the expense of device dependent upper
layer software which precludes the use of a standard
I/O interface.
The second issue "Programming the 82586" discusses
is which algorithms to choose for the CPU to control
the 82586. The algorithms used in this data link design
are taken directly from "Programming the 82586".
Command processing uses a linear static list, while receive processing uses a linear dynamic list.
The application example is written in C and uses the
Intel C compiler. The target hardware for the Data
Link Driver is the iSBC 186/51 COMMputer, however
a version of the software is also available to run on the
LANHIB Demo board.
1.0 FITTING THE SOFTWARE INTO
THE OSI MODEL
The application example consists of four software modules:
OSI REFERENCE
MODEL LAYERS
~-----..
" ,
PRESENTATION
MAC
,
TRANSPORT
NETWORK
DATA LINK
PHYSICAL
,
,
,,
,,
The Data Link Layer, as. defined in the IEEE 802 standard documents, is divided into two sublayers: the Logical Link Control (LLC) and the Medium Access Control (MAC) sublayers. The Medium Access Control
sublayer is further divided into the 82586 Coprocessor
plus the 82586 Handler. On top of the MAC is the LLC
software module which provides IEEE 802.2 compatibility. The LLC software module implements the Station Component responses, dynamic addition and deletion of Service Access Points (SAPs), and a class I level
of service. (For more information on the LLC sublayer,
refer to IEEE 802.2 Logical Link Control Draft Standard.) The class I level of service provides a connectionless datagram interface as opposed to the class 2
level of service which provides a connection oriented
level of service similar to HDLC Asynchronous Balanced Mode.
On top of the Data Link Layer is the Upper Layer
Communications Software (ULCS). This contains the
Network, Transport, Session, and Presentation Layers.
These layers are not included in the design example,
therefore the application layer of this ap note interfaces
directly to the Data Link layer.
,,
,
,,
,,
",
USER APPLICAnON
UPPER LAYER ODMMUNICAnON SOFTWARE
LLC MODULE ~ LOGICAL LINK ODNTROL
OLD. MODULE
,
SESSION
,,
Figure I illustrates how these software modules combined with the 82586, 82501 and 82502 complete the
first two layers of the OSI model. The 82502 implements an IEEE 802.3 compatible transceiver, while the
82501 completes the Physical layer by performing the
serial interface encode/decode function.
·~~UA~P~.ULCS
M~0~D~U~LE9;::==i
_•• , •••• -'
..---
...... ··>LL·-c-f
•• '
,
APPLICATION
• Data Link Driver (DLD): drives the 82586, also
known as the 82586 Handler.
• Logical Link Control (LLC): implements the IEEE
802.2 standard.
• User Application (UAP): exercises the other software modules and runs a specific application.
• C hardware support: written in assembly language,
supports the Intel C compiler for I/O, interrupts,
and run time initialization for target hardware.
82586
82586 HANDLER
DATA LINK COPROCESSOR
ENCOOE/DECODE (ESI)
TRANSCEIVER CABLE
CL..- HARDWARE ODNNECTOR
231421-1
Figure 1. Data Link Driver's Relationship to OSI Reference Mode 1
1-177
inter
AP-235
} APPLICATION
DATA LINK
TERMINAL EMULATOR
AND
STATION MONITOR
PHYSICAL
231421-2
Figure 2. Block Diagram of the Hardware and Software
The application layer is implemented in the User Application (UAP) software module. The UAP module operates in one of three modes: Terminal Mode, Monitor
Mode, and High Speed Transmit Mode. The software
initially enters a menu driven interface which allows
the program to modify several network parameters or
enter one of the three modes.
The Terminal Mode implements a virtual terminal with
datagram capability (connectionless "class I" service).
This mode can also be thought of as an async to IEEE
802.3/802.2 protocol converter.
The Monitor Mode provides a dynamic update on the
terminal of 6 station related parameters. While in the
monitor mode, any size frame can be repeatedly transmitted to the cable in a software loop.
High Speed Transmit Mode transmits frames to the cableas fast as the software possib~y can. This mode demonstrates the throughput performance of the Data Link
Driver.
The UAP gathers network statistics in all three modes
as well as when it is in the menu. In addition, the UAP
module provides the capability to alter MAC and LLC
addresses and re-initialize the data link. (Figure 2
shows a combined software and hardware block diagram.)
The C_Assy_Support module has a run time start otT
function which loads the DLD data segment into a
global variable SEGMT_. This data segment is used
by the 82586 Handler for address translation purposes.
The 82586 uses a flat address while the 80186 uses a
segmented address. Any time a conversion between
82586 and 80186 addresses are needed the SEGMT_
variable is used.
Pointers for the 80186 in the large model are 32 bits,
segment and otTset. All the 82586 link pointers are 16
bit otTsets. Therefore when trading pointers between the
82586 and the 80186, two functions are called:
Offset (ptr), and Build_Ptr (otTset). OtTset (ptr) takes a
32 bit 80186 pointer and returns just the otTset portion
for the 82586 link pointer. While Build_Ptr (otTset)
takes an 82586 link pointer and returns a 32 bit 80186
pointer, with the segment part being the SEGMT_
variable. OtTset () and BuildJtr() are simple functions written in assembly language included in the C_
Assy_Support module.
In the small model, OtTset ( ) and Build_Ptr( ) are not
needed, but the variable SEGMT_ is still needed for
determining the SCB pointer in the ISCP, and in the
Transmit and Receive ButTer Descriptors.
3.0 THE 82586 HANDLER
2.0 LARGE MODEL COMPILATION
3.1 The Buffer Model
All the modules in this design example are compiled
under the Large Model option. This has the advantages
of using the entire 1 Mbyte address space, and allowing
the string constants to be stored in ROM. In the Large
Model it is important to consider that the 82586's data
structures, SCB, CB, TBD, FD, and RBD, must reside
within the same data segment. This data segment is
determined at locate time.
The butTer model chosen for the 82586 Handler is the
"Design Model" as described in "Programming the
82586". This is based on the 82586 driver as a special
driver rather than as a standard driver. Using this approach the ULCS directly accesses the 82586's Transmit and Receive ButTers, ButTer Descriptors and Frame
Descriptors. This eliminates butTer copying. Transmit
and receiver butTer passing is done entirely through
pointers.
1-178
inter
AP-235
The only hardware dependencies between the Data
Link and ULCS interface are the buffer structures. The
ULCS does not handle the 82586's CBs, SCB or initialization structures. To isolate the data link interface from
any hardware dependencies while still u,sing the design
model, another level of buffer copying must be introduced. For example, when the ULCS transmits a frame
it would have to pass its own buffers to the data link.
The data link then copies the data from ULCS buffers
into 82586 buffers. When a frame is received, the data
link copies the data from the 82586's buffers into the
ULCS buffers. The more copying that is done the slower the throughput. However, this may be the only way
to fit the data link into the operating system. The 82586
Handler can be made hardware independent by adding
a receive and transmit function to perform the buffer
copying.
The 82586 Handler allocates buffers from two pools of
memory: the Transmit pool, and the Receive pool as
ill\lstrated in Figure 3. The Transmit pool contains
Transmit Buffer Descriptors (TBDs) and Transmit
Buffers (TBs). The Receive pool contains Frame Descriptors (FDs), Receive Buffer Descriptors (RBDs),
and Receive Buffers (RBs).
I
RECEIVE
&-'01 0",..)
POOL
~
TB
3.2 The Handler Interface
The handler interface provides the following basic functions:
•
•
•
•
•
initialization
sending and receiving frames
adding and deleting multicast addresses
getting transmit buffers
returning receive buffers
Figure 4 lists the Handler Interface functions.
On power up, the initialization function is called. This
function initializes the 82586, and performs diagnostics.
After initialization, the handler is ready to transmit and
receive frames, and add and delete multicast addresses.
To send a frame, the ULCS gets one or more transmit
buffers from the handler, fills them with data, and calls
the send function. When a frame is received, the handler calls a receive function in the ULCS. The ULCS
receive function removes the information it needs and
returns the receive buffers to the handler. The addition
and deletion of multicast addresses can be done "on the
fly" any time after initialization. The receiver doesn't
have to be disabled when this is done.
UPPER LAYER
COMMUNICATIONS SOFTWARE
SEND
rupts the handler. The handler passes a FD pointer to
the ULCS. Linked to the FD is one or more RBDs and
RBs. The ULCS extracts what it needs from the FD,
RBDs and RBs, and returns the FD pointer back to the
handler. The handler places the FD and RBDs back
into the free RFA pool.
POOL
m
RBD
RB
82586 HANDLER
231421-3
Figure 3. 82586 Handler Memory
Management Model
When the ULCS wants to transmit, it requests a TBD
from the handler. The handler returns a pointer to a
free TBD. Each TBD has a TB attached to it. The
ULCS fills the buffer, sets the appropriate fields in the
TBD, and passes the TBD pointer back to the handler
for transmission. After the frame is transmitted, the
handler places the TBD back into the free TBD pool. If
the ULCS needs more than one buffer per frame, it
simply requests another TBD from the handler and
performs the necessary linkage to the previous TBD.
On the receive side, the RFA pool is managed by the
82586 itself. When a frame is received, the 82586 inter-
The command interface to the handler is totally asynchronous-the ULCS can issue transmit commands or
multicast address commands whenever it wants. The
commands are queued by the handler for the 82586 to
execute. If the command queue is full, the send frame
procedure returns a false status rather than true. The
size of the command queue can be set at compile time
by setting the CB-CNT constant. Typically the command queue never has more than a few commands on it
because the 82586 can execute commands faster than
the ULCS can issue them. This is not the case in a
heavily loaded network when deferrals, collisions, and
retries occur.
The command interface to the 82586 handler is hardware independent; the ouly hardware dependence is the
buffering. A hardware independent command interface
doesn't have any performance penalty, but some 82586
programmability is lost. This shouldn't be of concern
since most data links do not change configuration parameters during operation. One can simply modify a
few constants and recompile to change frame and network parameters to support other data links.
1-179
inter
Handler Interface Functions
Description.
IniL586()
.Send_Frame (ptbd, padd) .
,
Recv_Frame (pfd)
,
AdLMulticast-Address (pma)
Delete_Multicast-Address (pma)
GeLTbd()
PuLFree_Rfa (pfd)
,
Initialize the Handler
Sends a frame to the cable.
ptbd-Transmit Buffer Descriptor pOinter
padd-Destination Address pointer
Handler calls this function which resides in the ULCS.
pfLFrame Descriptor pointer
Adds one multicast address
pma-Multicast Address pointer
Deletes one multicast address
Get a Transmit Buffer Descriptor pointer
Returns a Frame Descriptor and Receive
Buffer Descriptors to the 82586.
Figure 4. List of Handler Interface Functions
231421-5
Figure 5. Free CB Pool
231421-4
Figure 6. Free Transmit Buffer Descriptor Pool
1-180
AP·235
The CBs within the list are initialized with 0 status, EL
bit set, and a link to the next CB. The TBD structures
are initialized with the buffer size, which is set at compile time with the TBUFJIZE constant, a link to the
next TBD, and an 82586 pointer to the transmit buffer.
This pointer is a 24 bit flat/physical address. The address is built by taking the transmit buffer's data segment address, shifting it to the left by 4 and adding it to
the transmit buffer offset. An 80186 pointer to the
transmit buffer is added to the TBD structure so that
the.80186 does not have to translate the address each
time it accesses the transmit buffer.
3.3 Initialization
The function which initializes the 82586 handler, Init_
586(), is called by the ULCS on power up or reinitialization. Before this function is called, an 82586 bard·
ware or software reset should occur. The Initialization
occurs in three phases. The first phase is to initialize the
memory. This includes flags, vectors, counters, and
data structures. The second phase is to initialize the
82586. The third phase is to perform self test diagnostics. Init_586() returns a status byte indicating the
results of the diagnostics.
Phase I executes initialization of all the handlers flags,
interrupt vectors, counters, and 82586 data structures.
There are two separate functions which initialize the
CB and RFA pools: BuiILCB() and Build~a().
Build....JU'a( ) builds a linear linked Frame Descriptor
list and a Receive Buffer Descriptor list as shown in
Figure 7. The status and EL bits for all the free FDs are
O. The last FD's EL bit is I and link pointer is NULL.
The first FD on the FD list points to the flI'St RBD on
the RBD list. The RBDs are initialized with both 82586
and 80186 buffer pointers. The 80186 buffer pointer is
added to the end of the RBD structure. Begin and end
pointers are used to mark the boundaries of the free
lists.
3.3.1 BUILDING THE CB AND RFA POOLS
3.3.282586 INITIALIZATION
BuilLCB() builds a stack of free linked Command
Blocks, and another stack of free linked Transmit Buffer Descriptors. (See Figures 5 and 6.) Each stack has a
Top of Stack pointer, which points to the next free
structure. The last structure on the list has a NULL
link pointer..
The 82586 initialization data structure SCP is already
set since it resides in ROM, however, the tscp must be
loaded with information. Within the SCP ROM is the
pointer to the ISCP; the ISCP is the only absolute address needed in the software. Once the ISCP address is
determined, the ISCP can be loaded. The SCB base is
obtained from the C~ssyJupport module. The
global variable SEGMT_contains the address of the
Init_586() begins by toggling the 82501100pback pin.
If the 82501 is powered up in loopback, the CRS and
CDT pin may be active. To reset this condition, the
loopback pin is toggled. The 82501 should remain in
loopback for the first part of the initialization function.
-
END FD
BEGIN FD
FD
.....
BEGIN_RBD.
L.t
...
FD
FD
=
STAT 0
EL-S=O
FD LINK
RBD OFFSET
DA
SA
LENGTH
Lr
STAT=O
EL-S-O
FD LINK
NULL
Lf
DA
SA
LENGTH
RBD
RBD
ACT. COUNT
RBD LINK
112588 BUF_PTR
RBUF_SIZE
80188 BUF_PTR
lr
RBUF'· (RBUF_SIZE)
ACT. COUNT
RBD LINK
I"'" 82588 BUF_PTR
RBlJF_SIZE
80188 BUF_PTR
RBD
lr
r-
T
STAT = 0
EL=1 S=O
NULL
NULL
DA
SA
LENGTH
r-
ACT. COUNT
NULL
112588 BUF_PTR
RBUF_SIZE
80188 BUF'_PTA
RBU,. (RBUF_SIZE)
RBUF (RBUF_SIZE)
~~~
..
Figure 7. Free RFA
1·181
231421-6
inter
AP·235
data segment of the handler. The 80186 shifts this value
to the left by 4 and loads it into the SCB base. The SCB
offset is now determined by taking the 32 bit SCB
pointer and passing it to the, Offset( ) function.
The 82586 interrupt is disabled during initialization because the interrupt function is not designed to handle
82586 reset interrupts, To determime when the 82586 is
fmished with its reset/initialization, the SCB status is
polled for both the CX and CNA bits to be set. After
the 82586 is initialized, both the CX and CNA interrupts are acknowledged.
The 82586 is now ready to execute commands. The
Configuration is executed first to place the 82586 in
internalloopback mode, followed by the IA command.
The address for the IA command is read off of a prom
on the PC board.
3.3.3 SELF TEST DIAGNOSTICS
The final phase of the handler initialization is to run the
self test diagnostics. Four tests are executed: Diagnose
command, Internal loopback, External loopback
through the 82501, and Externalloopback through the
transceiver. If these four tests pass, the data link is
ready to go on line.
The function that executes these diagnostics is called
Test_Link(). If any of the tests fail, Test_Link() returns immediately with the Self_Test global variable
set to the type of failure. This Self_Test global variable
is then returned to the function which originally called
Init_586(). Therefore Init_586() can return one of
five results: FAILED_DIAGNOSE, FAILED_
LPB~INTERNAL,
FAILED_LPBK_EXTERNAL,
FAILED~LPB~TRANSCEIVER
or
PASSED.
fAILED DIAGNOSE
FAILED INTERNAL LOOPBACK
FAILED EXTERNAL LOOPBACK
fAILED LOOPBACK
THROUGH TRANSCEIVER
231421-7
Figure 8. Initialization Diagnostics: TesLLink 0
1-182
inter
AP-235
The Diagnose( ) function, called by Test_Link( ), does
not return until the diagnose command is completed. If
the interrupt service routine detects that a Diagnose
command was completed then it sets a flag to allow the
Diagnose() function to return, and it also sets the
Self_Test variable to FAIL if the Diagnose command
failed. If the Diagnose command completed successfully, the loopback tests are performed.
the 82586's static command block list. After the 82586
executes the command, it generates an interrupt. The
interrupt routine, Isr_586(), processes the command
and returns the Command Block to the free command
block list by calling Put_Cb( ).
Before any loopback tests are executed, the Receive
Unit is enabled by calling Ru~Start( ). Loopback tests
begin by calling Send_LpbLFrame(), which sends 8
frames with known loopback'data and its own destination address. More than' one loopback frame is sent in
case one or more of them:'are lost. Also se~eral of the
frames will have been received by the time flags.lpbk_
test is checked.
Get_Cb( ) returns a pointer to a free command block.
The free command blocks are in a linear linked list
structure which is treated as a stack. The pointer cb_
tos points to the next available CB. Each time a CB is
requested, Get_Cb() pops a CB off the stack. It does
this by returning the pointer of cb_tos. cb_tos is then
updated with the CB's link pointer. When the CB list is
empty, Get_Cb() returns NULL.
Two flag bits are used for the loopback tests:
flags.lpbLmode, and flags.lpbLtest. flags.lpbL
mode is used to indicate to the receive section that the
frames received are potentially loopback frames. The
receive section will pass receive frames,to the Loopback
Check( ) function if the flags.lpbLroode bit is set. The
LoopbacLCheck( ) function first compares the source
address of the frame with its station address. If this
matches then the data is checked with the knQwn loopback data. If th!'; data matches, then the flags.lpbk_test
bit is set, indicating a successful loopback. The flow of
the Test_Link( ) function is displayed in Figure 8.
There are two types of nulls, the 82586 'NULL' is a 16
bit offset, OFFFFH, in the 82586 data structures. The
80186 null pointer, 'pNULL', is a 32 bit pointer; with
OFFFFH offset and the 82586 handler's data segment,
SEGMT_, as the base.
3.4.1 ACCESSING COMMAND BLOCKS-GET_
CBO and PUT_CBO
Put_Cb() pushes a free command block back (In the
list. It does this by placing the cb_tos variable in the
returnedCB's link pointer field, then updates cb_tos
with the pointer to the returned CB.
3.4.2 ISSUING CU COMMANDS-ISSUE_CU_
CMDO
3.4 Command Processing
Command blocks are queued up on a static list for the
82586 to execute. The flow of a command block is given in Figure 9. When the handler executes a command
it first has to get a free command block. It does this by
calling Get_CB() which returns a pointer to a free
command block. The CB structure is a generic one in
which all commands except the MC-Setup can fit in.
The handler then loads into the CB structure the type
of command and associated parameters. To issue the
command to the 82586 the Issue_CU_Cmd() function is called with the pointer to the CB passed to this
function. Issue_CU_Cmd() places the command on
INTERRUPT
This function queues up a command for the 82586 to
execute. Since static lists are used, .each command has
its EL bit set. There is a. begilL-cbl pointer and an
end_cbl pointer to delineate the 82586's static list. If
there are no CBs on the list, thel). begirL-cbl is set to
pNULL. (Figure 10 illustrates the static list.) Each
time a command is issued, a deadman timer is set.
When the 82586 interrupts the CPU with a command
completed, the deadman timer is reset.
Issue_Cu_Cmd( ) begins by disabling the 82586's interrupt. It then determines whether the list is empty or
not. If the list is empty, begin and end pointers are
loaded with the CB's address. The CU must then be
started. Before a CU_START can be issued, the SCB's
cbLoffset field must be loaded with the address of the
command, the W/lit_Scb() function must be called to
insure that the SCB is ready to accept a command, and
the deadman timer must be initialized. If the list is not
empty, then the command block is queued at the end of
the list, and the interrupt service routine Isr_586(),
will continue generating CAs for each command linked
on the CB list until the list is empty. .
231421-8
Figure 9. The Flow of a Command Block
1-183
intJ
AP-235
SCB
cel ~OINTER
231421-9
Figure 10. The Static Command Block "ist
3.4.3 INTERRUPT SERVICE ROUTINE-ISR_
5860
Isr_586( ) starts off by saving the interrupts that were
generated by the 82586 and acknowledging them. Acknowledgment must be done immediately because if a
second interrupt were generated before the acknowledgment, the second interrupt would be missed. The
interrupt status is then checked for a receive interrupt
and if one occurred the Recv_IntJrocessing() function is called. After receive processing is check the CPU
checks whether a command interrupt occurred. If one
did, then the deadman timer is reset and the results of
the command are checked. There are only two particular commands which the interrupt results are checked
for: Transmit and Diagnose: The Diagnose command
needs to be tested to see if it passed, plus the diagnose
status flag needs to be set so that the initialization process can continue.
The sqe status bit will be set if the transceiver's self test
passed. However if the sqe status bit is not set, the
transceiver may still have passed its self test. Several
events can prevent the sqe bit from being set. For example, the first transmit command status after power up
will not 'have the sqe bit set because the sqe is always
from the previous command. Also if any collisions occur, the sqe bit might not be'set. This has to do with the
timing of when the sqe signal comes from the transceiver. It is possible that a JAM signal from a remote station can overlap the sqe signal in which case the 82586
will not set the, sqestatus bit. Therefore the'sqe error
count should only be recorded when no collisions occur.
One other situation can occur which will prevent the
SQE status bit from being set. If transmit command
reaches the maximum retry count, the next transmit
command'sSQE bit will not be set.
The transmit command status provides network management and station diagnostic information which is
useful for the "Network Management" function of the
ISO model. The following statistics are gathered in the
interrupt routine: good_transmit_cnt, sqe_err_cnt,
defer_cnt, no_crs_cnt, underruIL-cnt, max_col_
cnt. To speed up transmit interrupt processing a flag is
tested to determine whether these statistics are desired,
if not this section of code is skipped.
The final phase of interrupt command processing determines if another command is linked, and returns the
CB to the free command block list. Another command
being linked is indicated by the CB link field not being
NULL. In this case the deadman timer and the 82586's
CU are re-started. If the CB link is NULL, there are no
further commands to execute, and begin_cbl is set to
pNULL.
The sqe error requires special considerations when used
for statistic gathering or diagnostics. The sqe status bit
indicates whether the transceiver passed its self test or
not. The transceiver executes a self test after each transmission. If the transceiver'S self test passed, it will activate the collision signal during the IFS time.
3.4.4 SENDING FRAMES-SEND...,..FRAME (PTBD,
PADD)
SendJrame() receives two parameters, a pointer to
the first Transmit Buffer Descriptor, and a pointer to
the destination address. There may be one or more
TBDs attached. The last TBD is indicated by its link
1-184
AP-235
field being NULL and the EOF bit set. It is the responsibility of the ULCS to make sure this is done before
calling SendJrame( ).
SendJrame( ) begins by trying to obtain a command
block. If the free command block list is empty, the send
frame function returns with a false result. It is up to the
ULCS to either continue attempting transmission or attempt at a later time. The send frame function calculates the length field by summing up the TBDs actual
count field. After the length field is determined, send
frame checks to see if padding is required. If padding is
necessary, Send Frame will change the act count field
in the TBD to meet the minimum frame requirements.
This technique transmits what ever was in the buffer as
padding data. If security is an issue, the padding data in
the buffer should be changed.
3.4.5 ACCESSING TRANSMIT BUFFERS-GET_
TBDO AND PUT_TBDO
Get_Tbd() returns a pointer to a free Transmit Buffer
Descriptor, and Put_Tbd() returns one or more
linked Transmit Buffer Descriptors to the free list. The
TBD which Get_Tbd() allocates has its link pointer
set to NULL, and its EOF bit cleared. If another buffer
is needed, the link field in the old TBD must be set.to
point to the new TBD. The last TBD used should have
its link pointer set to NULL and its EOF bit set. Figure
II shows the flow chart of getting buffers and sending a
frame.
Put_Tbd (ptbd) is called by the Isr_586() function
when the 82586 is done transmitting the buffers. A
pointer to the first TBD is passed to Put_Tbd().
Put_Tbd() finds the end of the list of TBDs and returns them to the free buffer list.
3.4.6 MULTICAST ADDRESSES
The 82586 handler maintains a table of multicast addresses. Initially this table is empty. To enable a multicast address the Add_Multicast_Address(pma) function is called; to disable a multicast address, Delete_
Multicast_Address(pma) function is called. Both functions accept a parameter which points to the multicast
address. Add and Delete functions perform linear
searches through the Multicast Address Table (MAT).
Add scans the entire MAT once to check if the address
being added is a duplicate of one already loaded. Add
will not enter a duplicate muilticast address. If there
are no duplicates Add goes to the beginning of the
MAT and looks for a free location. If it finds one, it
loads the new address into the free location and sets the
location status to INUSE. If no free locations are available, Add returns a false result.
Delete looks for a used location in the MAT. When it
finds one, it compares the address in the table with the
address passed to it. If they match, the location status is
set to FREE and a TRUE result is returned. If no
match occurs, the result returned is FALSE.
If Add or Delete change the MAT, they update the
231421-10
Figure 11. Flow Chart for Sending a Frame
82586 by calling Set-.Multicast_Address(). This
function executes an 82586 MC Setup command. Set_
Mulitcast~ddress() uses the addresses in the MAT
to build the MC Setup command. The MC Setup command is too big to be built from the free CBs. Free CB
1-185
intJ
AP-235
command blocks are 18 bytes long, while the MC Setup
command can be up to 16,392 bytes. Therefore a separate Multicast Address Command Block (ma_cb)
must be allocated and used. The size of the ma_cb and
MAT are determined at compile time based on the
MULTI_ADD~CNT constant. The design example allows up to 16 multicast addresses.
Since there is only one ma.-:.cb, and it is not compatible
with the other CBs, it must be treated differently. Only
one ma_cb can be on the 82586 command list. The
ma_cb command word is used as a semaphore. If it is
zero, the command is available. If not, Set_Multicast~ddress() must wait until the ma_cb is free.
Also the interrupt routine can't return the ma_cb to
the free CB list. It just clears the cmd field, to indicate
that ma_cb is available.
The 82586's receiver does not have to be disabled to
execute the MC Setup command. If the 82586 is receiving while this command is accessed, the 82586 will fmish reception before executing the MC Setup comand. If
the MC Setup command is executing, the 82586 automatically ignores incoming frames until the MC Setup
is completed. Therefore multicast addresses can be added and deleted on the fly.
ENTER INTERFACE FUNCTION
3.4.7 RESETTING THE 82586-RESET_5860
The 82586 rarely if ever locks up in a well behaved
network; (i.e. one that obeys IEEE 802.3 specifications). The lock-ups identified were artificially created
and would normally not occur. This data link driver
has been tested in an 8 station network under various
loading conditions. No lock-ups occurred under any of
the data link drivers test conditions. However the reset
software has been tested by simulating a lockup. This
can be done by having the 82586 transmit, and disabling the CTS pin for a time longer than the deadman
timer.
An 82586 deadlock is not a fatal error. The handler is
designed to recover from this problem. As mentioned
before, each time the 82586 is given a CA to begin
executing a command, a deadman timer is set. The
deadman timer is reset when a CNR interrupt is generated. If the CNR interrupt is not generated before the
deadman timer expires, the 82586 must be reset.
Resetting of the 82586 should not be done while the
handler software is executing. This could create a software deadlock by interrupting a critical section of code
in the handler. To insure that the Reset_586() function is not executed while the handler is executing, all
of the entry points to the handler (i.e. interface functions) set a semaphore flag bit called flags. reset_serna.
This flag is cleared when the interface functions are
exited.
If the Deadman timer interrupt occurs while
flags. reset_serna is set, another flag is set (flag. reset_
pend) indicating that the Reset_586( ) function should
be called when the interface functions are exited. However if the deadman timer interrupt occurs when
flags.reset_sema is clear, Reset_586( ) is called immediately. Figure 12 shows the logic for entering and exiting interface functions.
231421-11
Figure 12. Reset Semaphore
Reset_586() begins by disabling the 82586 interrupt,
placing the ESI in loopback, and resetting the 82586.
The reset can be a software or a hardware reset. However, there are certain lockups in the 82586 where only
a hardware reset will suffice. (The 82586 errata sheet
explicitly indicates which deadlocks require a hardware
reset.) After the reset, Reset_586() executes a Configure, lA-Setup, and a MC-Setup command; the MC_
Setup command is built from the multicast address ta- .
ble (MAT). The 82586 Command Queues and Receive
Frame Queues are left untouched so that the 82586 can
continue executing where it left off before the deadlock.
This way no frames or commands are lost. This requires that a separate reset CB and reset Multicast CB
is used, because other CBs already in use cannot be
disturbed.
1-186
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Ap·235
3.5 Receive Frame Processing
The following functions are used for Receive Frame
Processing:
Recv _Int_Processing( ) Called by Isr_586() to remove FDs and RBDs from
the 82586's RFA
Recv_Frame (pfd)
Called by Recv_Int_Processing(). This function resides in the ULCS
ChecLMulticast (Pfd) Used for perfect Multicast
filtering
Returns FDs and RBDs to
the 82586's RFA
Restarts the RU when in the
IDLE or No Resources
state.
3.5.1 RECEIVE INTERRUPT PROCESSINGRECV_INT_PROCESSINGO
The Recv_IntJrocessing() function is called by
Isr_586() when the FR bit in the SCB is set. The
Recv_Int_Processing() function checks whether any
FDs and RBDs on the free list have been used by the
82586. If they have, Recv_Int_Processing() removes
the used FOs and RBDs from the free list, and passes
them to the ULCS.
The Recv_IntJrocessing() function is a loop where
each pass removes a frame from the 82586's RFA.
When there are no more used FDs and RBDs on the
RFA, the function calls RU_Start(), then returns to
Isr_586(). The first part of the loop checks to see if
the C bit in the first FD of the free FD list is set. If the
C bit is set, the function determines if one or more
RBDs are attached. If there are RBDs attached, the
end of the RBD list is found. The last RBD's link field
is used to update begi~rbd pointer, and then it's set
to NULL.
After the receive frame has been delineated from the
RFA, some information about the frame is needed to
determine which function to pass it to. Since the save
bad frame configure bit is not set, the only bad frame
on the list could be an out of resource frame. An out of
resource frame is returned to the RFA by calling Put_
Free_RFA (pfd). If the flags.lpbLmode bit is set, the
frame is given to the loopback check function. If the
destination address of the frame indicates a multicast,
the check multicast function is called. If the frame has
passed all of the above tests and still has not been returned, it is passed to the RecvJrame() function
which resides in the ULCS.
ChecLMulticast (pfd) determines whether the multicast address received is in the multicast address table.
This is necessary because the 82586 does not have per-
fect multicast address filtering. ChecLMulticast does
a byte by byte comparison of the destination address
with the addresses in the multicast address table. If no
match occurs, it returns false, and Recv_IntJrocessing calls Put_Free_RFA( ) to return the frame to the
RFA. If there is a match, Check_Multicast() returns
TRUE and Recv_IntJrocessing() calls Recv_
Frame(), passing the pointer to the FD of the frame
received.
3.5.2 RETURNING FDs AND RBDs-PUT_
FREE_RFA (pfd)
Put_Free_RFA combines Supply_FD and Supply~BD algorithms described in "Programming the
82586" into one function. The begin and end pointers
delineate what the CPU believes is the beginning and
end of the free list. The decision of whether to restart
the RU is made when examining both the free FD list
and the free RBD list. This is why two ru_start_flags
are used, one for the FD list and one for the RBD list.
Both flags are initialized to FALSE.
The function starts off by initializing the FD so that the
EL bit is set, the status is 0, and the FD link field is
NULL. The rbd pointer is saved before the rbd pointer
field in the FD is set to NULL. The free FD list is
examined and if it's empty, begin-fd and end-fd are
loaded with the address of the FO being returned. In
this case the RU should not be restarted, because there
is only one FD on the free list. If the free FD list is not
empty, the FD being returned is placed on the end of
the list, the end pointer is updated, and the RU start
flag is set TRUE.
To begin the RBD list processing the end of the returned RBD list is determined, and this last RBD's EL
bit is set. If the free RBD list is empty, the returned
RBD list becomes the free RBD list. If there is more
than one RBD on the returned list, the ru start flag is
set TRUE. If the free RBD list is not empty, the returned RBD list is appended on the end of the free list,
the end-rbd pointer is updated, and the ru start flag is
set TRUE.
The last part of Put_Free_RFA() is to determine
whether to call RU_Start(). Both ru start flags are
ANDed together, and if the result is TRUE, the Ru_
Start() function is called.
3.5.3 RESTARTING THE RECEIVE UNIT-RU_
STARTO
The Ru_Start( ) function checks two things before it
decides to restart the RU. The first thing it checks is
whether the RU is already READY. If it is, there is no
reason to restart it. If the RU is IDLE or in NO_RESOURCES, then the second thing to check is whether
the first free FD on the free FD list has its C bit set. If
it does, then the RU should not be restarted. The reason is that the free FD list should only contain free FDs
1-187
inter
when the RU is started. If the C bit is set in the FD,
then not all the used FD have beeq removed yet. If the
RU is started when used FDs are still in the RFA, the
82586 will write over the used FDs and frames will be
lost. Therefore Ru_StartO is exited if the first FD in
the RFA has its C bit set. If the RU is not READY,
and beginJd doesn't point to a used FD, then the RU
is restarted.
(see Figure 13). The LSAP addresses are defined as
follows:
Data Link Layer (Station Component)
OOH
Transport Layer
FEH
Network Management Layer
08H
multiples of 4 in the range
User Processes
OCH < LSAP s FCH
Note that in "Programming the 82586" there are two
more conditions to be met before the RU is started: two
or more FD on the RFA, and two or more RBD on the
RFA. These conditions are checked in Put._Free_
RFAO, and Ru_StartO isn't called unless they are
met.
Each receiving process is identified by a destination
LSAP (DSAP) and each sending process is identified
by a source LSAP (SSAP). Before a destination process
can receive. a packet, its DSAP must be included in a
list of active DSAPs for the data link.
Figure 14 illustrates the relationship between the Station Component and the SAP components. (The SAP
components are user processes.) The Station Component receives all of the good frames from the Handler
and checks the DSAP address. If the DSAP address is
0, then the frame is addressed to the Station Component and a Station Component Response is generated.
If the DSAP address is on the active DSAP list, then
the Station Component passes the frame to the addressed SAP. If the DSAP address is unknown, the
frame is returned to the handler.
4.0 LOGICAL LINK CONTROL
The IEEE 802.2 LLC function completes the Data
Link Layer of the OSI model. The LLC module in this
design example implements a class 1 level of service
which provides a connectionless datagram interface.
Several data link users or processes can run on top of
the data link layer. Each user is identified by a link
service access point (LSAP). Communication between
data link users is via LSAPs. An LSAP is an address
that identifies a specific user process or another layer
TRANSPORT
. LAYER
USER
TASK
1
t
LSAP=OFEH
NElWORK
LAYER
1
~
USER
TASK
LSAP=O~
1
LS~= 10H
USER
TASK
•••
~ LSAP =14H
DATA LINK
USER
INTERFACE
LSAP=08H
1
DATA LINK INTERFACE
!
DATA LINK
CONTROLLER
1
NElWORK MEDIUM
231421-12
Figure 13. Data Link Interface
1-188
SAP
COMPONENT
SAP
COMPONENT
11°
III
•••
SAP
COMPONENT
liN
T
ULCS
~~.-----------.~
LLC MODULE
STATION COMPONENT
HANDLER
~__~82~S~86~__~. ___________ .~
PHYSICAL
231421-13
Figure 14. Station Component Relationship
There are 3 commands and 2 responses which the class
1 LLC layer must implement. Figure 15 shows IEEE
802.2 Class 1 commands and responses and Figure 16
shows the IEEE 802.2 Class 1 frame format.
Commands
Responses
Description
XID
TEST
Unnumbered
Information
ExchangelD
Remote Loopback
UI
XID
TEST
Figure 15. IEEE 802.2 Class 1, Type 1 Commands
and Responses
HEAD
..
-
-,>
(BSAP
I
I
SSAP
DATA
I
TAIL
< ......
I CONTROL I
......
Any frames addressed to active SAPs ,are passed directly to them. The Station Component will not respond to
SAP addressed frames. Therefore it is the responsibility
of the SAPs to recognize and respond to frames addressed to them. When a SAP transmits a frame, it
builds the IEEE 802.2 frame itself and calls the Handler's Send_Frame() function directly. The LLC
module is not used for SAP frame transmission. The
only functions which the LLC module implement are
the dynamic addition and deletion of DSAPs, multiplexing the frames to user SAPs, and the Station Component command recognition and responses. This is
one implementation of the IEEE 802.2 standard. Other
implementations may have the LLC module do more
functions, such as SAP command recognitions and responses. A list of the functions included in the LLC
module is as follows:
DAT:t'!
LLC Functions
231421-14
IniLLlc( )
Figure 16. IEEE 802.2 Class 1 Frame Format
From Figure 15 it can be seen that there are no LLC
class 1 UI responses because information frames are not
acknowledged at the data link level. The only command frames that may require responses are XID and
TEST. If a command frame is addressed to the Station
Component, it checks the control field to see what type
of frame it is. If it's an XID frame, the Station Component responds with a class 1 XID response frame. If it's
a TEST frame, the Station Component responds with a
TEST frame, echoing back the data it received. In both
cases, the response frame is addressed to the source of
the command frame.
1-189
Description
Initializes the DSAP
address table and calls
IniL586()
Add_Dsap_
Add a DSAP address to
Address (dsap, pfunc) the active list
dsap - DSAP address
pfunc - pointer to the
SAP function
Delete a DSAP address
Delete-DsapAddress (dsap)
dsap - DSAP address
Recv-Frame (pfd)
Receives a frame from
the 82586 Handler
pfd - Frame Descriptor
Pointer
Station-Component- Generates a response to
Response (pfd)
a frame addressed to the
Station Component
pfd - Frame Descriptor
Pointer
inter
AP-235
4.1 Adding and Deleting LSAPs
When a user process wants to add a LSAP to the active
list, the process calls Add_Dsap_Address(dsap,
pfunc). The dsap parameter is the actual DSAP address, and the pfunc parameter is the address of the
function to be called when a frame with the associated
DSAP address is received.
The LLC module maintains a table of active dsaps
which consists of an array of structures. Each structure
contains two members: stat - indicates whether the address is free or inuse, and (·p~ap_func)() contains
the address of the function to call. The index into the
array of structures is the DSAP address. This speeds up
processing by eliminating a linear search. Delete_
Dsap_Address (dsap) simply uses the DSAP index to
mark the stat field FREE.
5.0 APPLICATION LAYER
For most networks the application layer resides on top
of several other layers referred to here as ULCS. These
other layers in the OSI model run from the network
layer through the presentation layer. The implementation of the ULCS layers is beyond the scope of this
application note, however Intel provides these layers as
well as the data link layer with the OpenNET product
line. For the purpose of this application note the application layer resides on top of the data link layer and its
use is to demonstrate, exerCise and test the data link
layer design example.
There can be several processes sitting on top of the data
link layer. Each process appears as a SAP to the data
link. The UAP module, which implements the application layer, is the only SAP residing on top of the data
link layer in this application example. Other SAPs
could certainly be added such as additional "connectionless" terminals, a networking gateway, or a transport layer, however in the interest of time this was not
done.
Terminal Mode - implements a virtual terminal with
datagram capability (connectionless "class I" service).
This mode can also be thought of as an async to IEEE
802.2/802.3 protocol converter.
Monitor Mode - allows the station to repeatedly transmit any size frame to the cable. While in the Monitor
Mode, the terminal provides a dynamic update of 6
station'related parameters.
High Speed Transmit Mode - sends frames to the cable
as fast as the software possibly can. This mode demonstrates the throughput performance of the Data Link.
Driver.
Change Transmit Statistics - When Transmit Statistics
is on several transmit statistics are gathered during
transmission. If Transmit Statistics is off, statistics are
not gathered and the program jumps over the section of
code in the interrupt routine which gathers these statistics. The transmission rate is slightly increase when
Transmit Statistics is off.
Print All Counters - Provides current information on
the following, counters.
Good frames transmitted:
Good frames received:
CR C errors received:
Alignment errors received:
Out of Resource frames:
Receiver overrun frames:
Each time a frame has been successfully transmitted the
Good frames transmitted count is incremented. The
same holds true for reception. CRC, Alignment, Out of
Resources, and Overrun Errors are all obtained from
the SCB. Underrun, lost CRS, SQE error, Max retry,
and Frames that deferred are all transmit statistics that
are obtained from the Transmit command status word.
82586 Reset is a count which is incremented each time
the 82586 locks up. This count has never normally been
incremented.
5.1 Application Layer Human Interface
The UAP provides a menu driven human interface via
an async terminal connected to port B on the iSBC
186/51 board. The menu of the commands is listed in
Figure 17 along with a description that follows:
T - Terminal Mode
X· High Speed Transmit Mode
P - Print All Counters
A - Add a Multicast Address
S - Change the SSAP Address
N - Change Destination Node Address
R· Re-Initialize the Data Link
M - Monitor Mode
V - Change Transmit Statil1tics
C - Clear All Counters
Z - Delete a Multicast Address
D - Change the DSAP Address
L - Print All Addresses
B - Change the Number Base
Figure 17. Menu of Data Link Driver Commands
1-190
inter
AP-235
Clear All Counters - Resets all of the counters.
Add/Delete Multicast Address - Adds and Deletes
Multicast Addresses.
Change SSAP Address - Deletes the previous SSAP
and adds a new one to the active list. The SSAP in this
case is this stations LSAP. When a frame is received,
the DSAP address in the frame received is compared
with any active LSAPs on the list. The SSAP is also
used in the SSAP field of all transmitted frames.
Change DSAP Address - Delete the old DSAP and add
a new one. The DSAP is the address of the LSAP
which all transmit frames are sent to.
reinitialized, and the selftest diagnostic and loopback
tests are executed. The results of the diagnostics are
printed on the terminal. The possible output messages
from the 82586 se1ftest diagnostics are:
Passed Diagnostic Self Tests
Failed: Self Test Diagnose Command
Failed: Internal Loopback Self Test
Failed: External Loopback Self Test
Failed: External Loopback Through Transceiver Self
Test
Change Base - Allows all numbers to be displayed in
Hex or Decimal.
Change Destination Node Address - Address a new
node.
Print All Addresses - Display on the terminal the station address, destination address, SSAP, DSAP, and all
multicast addresses.
Re-initialize Data Link - This causes the Data Link to
completely reinitialize itself. The 82586 is reset and
5.2 A Sample Session
The following text was taken directly from running the
Data Link software on a 186/51 board. It begins with
the iSDM monitor signing on and continues into executing the Data Link Driver software.
iSDM 86 Monitor, Vl.O
Copyright 1983 Intel Corporation
.G DOOO:6
•••••••••••• ** •••••••••• ** •••• ** ••••••••••••••••••••••••••••••••
•
•
•
•
•
82586 IEEE 802.2/802.3 Compatible Data Link Driver •
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Passed Diagnostic Self Tests
Enter the Address of the Destination Node in Hex -> 00AA0000179E
Enter this Station's LSAP in Hex -> 20
Enter the Destination Node's LSAP in Hex -> 20
Do you want, to Load any Multicast Addresses?
(of or Nl -> Y
Enter the Multicast Address in Hex -> OOAAOOllllll
Would you like to add another Multicast Address? (Y or Nl - > N
This Station's Host Address is: 00AA00001868
The Address of the Destination Node is: 00AAOOOOl79E
This Station's LSAP Address is: 20
The
~ddress
of the Destination LSAP is: 20
The following Multicast Addresses are enabled: OOAAOOllllll
1-191
AP-235
Commands ,are:
T - Terminal Mode
M - Monitor Mode
X - High Speed Transmit Mode
V - Change Transmit Statistics
P - Print All Counters
C -' Clear All Counters
A - Add a Multicast Address
Z - Delete a Multicast Address
S - Change the SSAP Address
D - Change the DSAP Address
N - Change Destination Node Address
L - Print All Addresses
R - Re-Initialize the Data Link
B- Change the number Base
Enter a command, type H for Help - > P
Good frames transmitted:
24
Good frames received:
I
0
CRC errors received:
o
Alignment errors received:
Out of Resource frames:
o
Receiver overrun frames:
o
o
o
Transmit underrun frames:
0
SQE errors:
9
Frames that deferred:
4
82586
Reset:
Lost CRS:
Maximum retry:
-0
Enter a command, type H for Help --> T
Would you like the local echo on? (Y or N) --> Y
This program will now enter the terminal mode.
Press
'c then CR to return back to the menu
Hello this is a test.
,"C CR .,
Enter a command, type H for Help --> M
Do you want this station to transmit? (Y or N) --> Y
Enter the number of data bytes in the frame --> 1500
Hit any key to exit Monitor Mode.
of Good
Frames
Transmitted
#
*'
32
#
of Good
Frames
Received
o
CRC
Errors
Alignment
Errors
00000
r CR
Enter a command, type H for Help --> X
Hit any key to exit High Speed Transmit Mode.
r
CR .,
Enter a command, type H for Help --> R
Passed Diagnostic Self Tests
1-192
00000
No
Receive
Resource Overrun
Errors Errors
00000
00000
inter
AP-235
5.3 Terminal Mode
The Terminal mode buffers characters received from
the terminal and sends them in a frame to the cable.
When a frame is received from the cable, data is extracted and sent to the terminal. One of three events
initiate the UAP to send a frame providing there is data
to send: buffering more than 1500 bytes, receiving a
Carriage Return from the terminal, or receiving an interrupt from the virtual terminal timer.
The virtual terminal timer employs timer 1 in the 80130
to cause an interrupt every .125 seconds. Each time the
interrupt occurs the software checks to see if it received
one or more characters from the terminal. If it did, then
it sends the characters in a frame.
The interface to the async terminal is a 256 byte software FIFO. Since the terminal communication is full
duplex, there are two half duplex FIFOs: a Transmit
FIFO and a Receive FIFO. Each FIFO uses two functions for I/O: Fifo_In() and Fifo_Out(). A block
diagram is displayed in Figure 18.
The serial I/O for the async terminal interface is always
polled except in the Terminal mode where it is interrupt driven. The Terminal mode begins by enabling the
8274 receive interrupt but leaves the 8274 transmit interrupt disabled. This way any characters received from
the terminal will cause an interrupt. These characters
are then placed in the Transmit FIFO. The only time
the 8274 transmit interrupt is enabled is when the ReFunction
FIFO_T_IN()
FIFO_T_OUT()
FIFO_R_IN( )
FIFO_R_OUT( )
ceive FIFO has data in it. The receive FIFO is filled
from frames being received from the cable. Each time a
transmit interrupt occurs a byte is removed from the
Receive FIFO and written to the 8274. When the Receive FIFO empties, the 8274 transmit interrupt is disabled.
The flow control implemented for the terminal interface is via RTS and CTS. When the Transmit FIFO is
full, RTS goes inactive preventing further reception of
characters (see Table 1). If the Receive FIFO is full,
receive frames are lost because there is no way for the
data link using class 1 service to communicate to the
remote station that the buffers are full. Lost receive
frames are accounted for by the Out of Resources
Frame counter.
The Async Terminal bit rate sets the throughput capability of the station in the terminal mode because the
bottle neck for this network is the RS232 interface. Using this fact a simple test was conducted to verify the
data link driver's capability of switching between the
receiver's No Resource state and the Ready State. For
example if station B is sending frames in the High
Speed Transmit mode to station A which is in the Terminal mode, frames will be lost in station A. Under
these circumstances station A's receiver will be switching from Ready state to Out of Resources state. The
sum of Good frames received plus Out of Resource
frames from station A should equal Good frames transmitted from station B; unless there were any underruns
or overruns.
Table 1. FIFO State Table
Present State
Next State
Action
EMPTY
IN USE
Start Filling Transmit Buffer
IN USE
FULL
ShutOff RTS
FULL
IN USE
Enable RTS
IN USE
EMPTY
Stop Filling Transmit Buffer
EMPTY
IN USE
Turn on Txlnt
IN USE
FULL
Stop Filling FIFO from Receive Buffer
FULL
IN USE
Start Filling FIFO from Receive Buffer
Turn Off Txlnt
IN USE
EMPTY
" SEND FRAMES
RECEIVE FRAMES
ASYNC
TERMINAL
231421-15
Figure 18
1-193
inter
AP-235
5.3.1 SENDING FRAMES
The Terminal Mode is entered when the TerminaL
Mode() function is called from the Menu interface.
The TerminaL_Mode( ) function is one big loop, where
each pass sends a frame. Receiving frames in the Terminal Mode is handled on an interrupt driven basis
which will be discussed next.
The loop begins by getting a TBD-from the 82586 handler. The first three bytes of the first buffer are loaded
with the IEEE 802.2 header information. The loop then
waits for the Transmit FIFO to become not EMPTY,
at which point a byte is removed from the Transmit
FIFO and placed in the TBD. After each byte is removed from the Transmit FIFO several conditions are
tested to determine whether the frame needs to be
transmitted, or whether a new buffer must be obtained.
A frame needs to be transmitted if: a Carriage Return is
received, the maximum frame length is reached, or the
send_frame flag is set by the virtual terminal timer. A
new buffer must be obtained if none of the above is true
and the max buffer size is reached.
If a frame needs to be sent the last TBD's EOP bit is set
and its buffer count is updated. The 82586 Handler's
Send_Frame() function is called to transmit the
frame, and continues to be called until the function returns TRUE.
The loop is repeated until a
Return is recieved.
'c followed by a Carriage
5.3.2 RECEIVING FRAMES
Upon initialization the UAP module calls the Add_
Dsap_Address(dsap, pfunc) function in the LLC module. This function adds the UAP's LSAP to the active
list. The pfunc parameter is the address of the function
to call when a frame has been received with the UAP's
LSAP address. This function is Recv_Data_l().
Recv~ata_l() looks at the control field of the
frame received and determines the action required.
The commands and responses handled by Recv_
Data_l() are the same as the Station Component's
commands and responses given in Figure 15. One difference is that Recv_Data_l(J will process a UI
command while the Station Component will ignore a
UI command addressed to it.
# of Good
# of Good
.Frames
Transmitted
Frames
Received
32
0
Recv_Data_l() will discard ,any UI frames received
unless it is in the Terminal Mode. When in the Terminal Mode, Recv_Data_l() skips over the IEEE 802.2
header information and uses the length field to determine the number of bytes to place in the Receive FIFO.
Before a byte is placed in the FIFO, the FIFO status is
checked to make sure it is not full. Recv_Data_l()
will move all of the data from the frame into the Receive FIFO before returning.
When a frame is received by the 82586 handler an interrupt is generated. While in the 82586 interrupt routine the receive frame is passed to the LLC layer and
then to the UAP layer where the data is placed in the
Receive FIFO by Recv_OctaLData_l(). Since
Recv_Data_l() will not return until all of the data
from the frame has been moved into the Receive FIFO,
the 8274 transmit interrupt must be nested at a higher
priority than the 82586 interrupt to prevent a software
lock. For example if a frame is received which has more
than 256 bytes of data, the Receive FIFO will fill up.
The only way it can empty is if the .8274 interrupt can
nest the 82586 interrupt service routine. If the 8274
could not interrupt the 82586 ISR then the software
would be stuck in Recv_Data_l() waiting for the
FIFO to empty.
5.4 Monitor Mode
The Monitor Mode dynamically updates 6 station related parameters on the terminal as shown below.
The Monitor_Mode() function consists of one loop.
During each pass through the loop the counters are
updated, and a frame is sent. Any size frame can be
transmitted up to a size of the maximum number of
transmit buffers available. Frame sizes less than the
minimum frame length are automatically padded by the
82586 Handler.
The data in the frames transmitted in the Monitor
Mode are loaded with all the printable ASCII characters. This way when one station is in the Monitor Mode
transmitting to another station in the Terminal Mode,
the Terminal Mode station will display a marching pattern of ASCII characters.
CRC
Errors
Alignment
Errors
No
Resource
Errors
Receive
Overrun
Errors
00000
00000
00000
00000
1-194
inter
AP-235
5.5 High Speed Transmit Mode
The High Speed Transmit Mode demonstrates the
throughput performance of the 82586 Handler. The
Hs_Xmit~ode() function operates in a tight loop
which gets a TBD, sets the BOF bit, and calls Send_
Frame(). The flow chart for this loop is shown in Figure 19.
The loop is exited when a character is received from the
terminal. Rather than polling the 8274 for a receive
buffer full status, the 8274's receive interrupt is used.
When the Hs_Xmit_Mode( ) function is entered, the
hs~tat flag is set true. If the 8274 receive interrupt
occurs, the hs_stat flag is set false. This way the loop
only has to test the hs_stat flag rather than calling
inb( ) function each pass through the loop to determine
whether a character has been received.
The performance measured on an 8 MHz 186/51 board
is 593 frames per second. The bottle neck in the
throughput is the software and not the 82586. The size
of the buffer is not relevant to the transmit frame rate.
Whether the buffer size is 128 bytes or 1500 bytes,
linked or not, the frame rate is still the same. Therefore
assuming a 1500 byte buffer at 593 frames per second,
the effective data rate is 889,500 bytes per second.
This can easily be demonstrated by using two 186/51
boards running the Data Link software. The receiving
stations counters should be cleared then placed in the
Monitor mode. When placing it in the monitor mode,
transmission should not be enabled. When the other
station is placed in the High Speed Transmit Mode a
timer should be started. One can use a stop watch to
determine the time interval for transmission. The frame
rate is determined by dividing the number of frames
received in the Monitor station by the time interval of
transmission.
231421-16
Figure 19. High Speed Transmit Mode
FlowChart
1-195
intJ
AP·235
APPENDIX A
COMPILING, LINKING, LOCATING, AND RUNNING THE
SOFTWARE ON THE 186/51 BOARD
*********
Instructions for using the 186/51 board
*.****.**
Use 27128A for no wait state operation. 27128s can be used but wait states will have to be added.
Copy HI.BYT and LO.BYT files into EPROMs
PROMs go into U34 - HI.BYT and U39 - LO.BYT on the 186/51 board
JUMPERS REQUIRED
WIRE WRAP
Jumper the 186/51 board for 16K byte PROMs in U34
and U39 Table 2-5 in 186/51 HARDWARE REFERENCE MANUAL (Rev-001)
E36-E47IN
E39-E44IN
E79-E45IN
186/51(ES)
E1!?1-E152 OUT
E152-E150 IN
E94-E95IN
E100-E1061N
E107-E113IN
E133-E134 IN
186/51 (S)/186/51
E199-E203 OUT
E203-E191 IN
E120-E1191N
E116-E1121N
E111-E1071N
E94-E93IN
also change interrupt priority jumpers - switch 8274
and 82586 interrupt priorities
E36-E44 OUT
E39-E47 OUT
E37-E45 OUT
E43-E50 IN
E46-E47IN
E90-E48IN
E43-E47 OUT
E46-ESOOUT
E44-E48 OUT
USE SDM MONITOR
The SDM Monitor should have the 82586's SCP
burned into ROM. The ISCP is located at OFFFOH.
Therefore for the SCP the value in the SDM ROM
should be:
ADDRESS
FFFF6H
FFFF8H
FFFFAH
FFFFCH
FFFFEH
DATA
XXOOH
XXXXH
XXXXH
FFFOH
XXOOH
To run the program begin execution at ODOOO:6H
1-196
intJ
AP-235
I.E. G DOOO:6
GOOD LUCK I
••••••••••
submit file for compiling one module:
••••••••••
run
cc86.86 :F6:%O LARGE ROM DEBUG DEFINE(DEBUG) include(:F6:)
exit
••••••••••
submit file for linking and locating:
••••••••••
run
link86
:F6:assy.obj, :F6:dld.obj, :F6:11c.obj, &
:F6:uap.obj, lclib.lib to :F6:dld.lnk segsize(stack(4000h)) notype
10c86 :F6:dld.lnk to :F6:dld.loc&
initcode (ODOOOOH) start (begin) order(classes(data, stack, code)) &
addresses (classes (data(3000H) , stack(OCBOOH), code(OD0020H)))
oh86 :F6:dld.loc to :F6:dld.rom
exit
*********.
submit file for burning EPROMs uSing IPP5:
ipps
i
86
f :F6:dld.rom (OdOOOOh)
3
2
1
o to :F6:10.byt
Y
1 to :F6 :hi. byt
y
t 27128
9
c :F6:10.byt t p
n
C :F6 :hi. byt t P
n
exit
1-197
**********
inter
AP-235
IPCO/USR/CHUCK/CSRC/DLD. H
****··*·.·*--*--------_.-._.-*
1**.*******••••••*******••••**.** ••••**.** ••
*
*
*
*
*
***.*****.*.*******.****.*****
•• ***.*.**•• ***••• *.****_.__._._._-_•• _._--/
.doflno INUSE
o
.ct.,flinl EMPTY
1
2
1
1
.doflno
.dofino
.doflno
.dUino
.deflno
FULL
FREE
TRUE
FALSE
NULL
o
OIFFFF
12B /* ",cllvi buff .... ,izi */
las 1* tran •• i t bu.,f .... ,111 *1
.dofino RBUF _SIZE
.dl,ine TBUF _SIZE
.doflno ADD..L£N
.doflno IIULTI_ADDR_CNT
6
16
t .. ,.dl' unsigned ,hol't int u_Ihol'tl
/* " •• ults ""Otl Tllt_LinkC):
.doflno
.dofino
.dofino
.dofino
.doflne
10ad.d into Sllf_TI.t eh .... */
PASSED
FAILED...DIAQNOSE
FAILED_LPBK_INTERNAI..
FAILED_LP8KJOXTERNAI..
FAILEDJ-P8K_TRANSCEIVER
'* Fra•• Commlnds *1
*dlf1ne
0
1
2
3
4
1* Unnumb.",.d In'o" .... tlo" F,.,.e *1
1* Elchang. Identification *1
1* Remot. Loopback TI.t
I . Poll/Final Bit Position *1
1* (olllland/R •• pon,. bit in SSAP *1
0103
OlAF
0lE3
0110
0101
.d.'ine
.d.flne
.d.'ine
UI
XID
TEST
PJ'_BIT
C_RJlIT
Idefinl
DBAP _CNT
B
1* Numbl'" o • • 11o... bll DSAP., must be • multiple
of 2*"'" .nd DBAP add,., •••• a.signed flust be
divislbl, bV 2**(8-N>.
(i. e. tho N LSBs lOust bo 0) . ,
"define
DSAP _SHIFT
5
I•
• d,fine
UD_LENGTH
6
1* Numb.,. of Info blJte.
*dlflnl
*'
DSAP _SHIFTS must equal 8-N *1
'0,.
XID R.spon., ,,. ••• *1
1* S"stem Configul'ation Point.,. SCP *1
.tl"uct SCP
v_short I".bus, 1* 82:586 bus lIIidth, 0 1 - B bits *1
16 bit.
231421-17
1-198
intJ
AP-235
IPCO/UIR/CHUCK/CIRC/DLD. H
u_,hort .luntt2],
u_,ho,., ilep1, /. 10••,. '6 bit' 0' '.ep .......... */
U_.ftD.. '
iseph.
I . uppn 8 bits D' hep .• dd ..... • 1
).
PDI~' ...
I . Int ..... dl.h 8y.h. CDnfl,u"."Dn
.'~ue'
ISCP (
ItUIV
I
/ •••,
'*
to 1
It,
cpu b •• o .... i t ' .h·"
CA,
e l ..... d by 8liUI86 •• h ....... In. *1
u_,hort of ••• "
0"'.' of 1"lt. . control It lac l ./
u_Iho'l't b ••• l , /. b••• D' IVlt •• cont,..l Itlock . ,
.
,
v_,hol"
IICP .1
.
U_I"O.. t
)
Bv,te. Con',"ol
• t~uet ICI
11oe~
(
•••• a
I
ICI . ,
u_Iho ... '
.'a',
u_,hol't;
eb~_Df . . . t.
,. I •• tu • •D~ • • ,
,. ,Q'''.'
,.....
aceullUla,e' *,'*'* F....... 10lt"'''''1''1
*'
'* OV.,."un .,.,. • .,.,becau. ,•• o. no R.,ou!'e •• *'
u_'hol"t c.tI,
/ . CO"'". 1If.?d . /
D' fi~.t eD_n. blD" in elL 0'
v_'ho"t ",'a_o•••• t, '0 0 . . . . ' Df fi~.'
d •• e .. ip"" in RFA 01
u_'h 01" , c ... c_.... ".,
/* CRe 8'1"ftO,.,
v_Iho ... t .In_.... ''.'
Aliln••nt
u_Iho,..' "Ie_e
OY'r __ ... ".,
v_'hOT't
,..,..J
).
'0
C. . . .nd
.'~ue'
11De~
CB
.,
'*
'*
(
v_'ho1"' 1'.1u
u_'hor' c... ,
,St.tuI, of Co. . ."cf
, . -Co-.ncf
lIn~ Ii_ld .1
u_Iho,., 1 :l.nllJ
v_Ihol"'" ' .....1',
v_,ho,.,
,.,..,
u_sho,.t p.,..3.
u_sho,., p.,.M.
u_s .. o,.t p.,..S.
u_s"Ol't
I.
./* P....... , .....
*'
*'
,.1''''
Multle •• t Addu . . CD_nd
.'~ue'
*'
11De~
PIA_CI<
u_.hO... t It.t.
u_sho ... ' c.d.
v_.ha,., I1ftk.
u_.tto.....c_cnt.
PIA_C• • 1
'*
*'
*'
'* Mu."." of Me .dd,.•••••
*'
10 He
Status of Co. .and
, . Co. . ."d
, . L1ftk f1.1d */
eh.~ .e~dd~tADD~EN*MULTI~DR_CNTJ.
).
, . Tun •• 1t
.'~ue'
lu'''~
TID
.dd~ •••• ~ ••
*'
D.. e~lp'o~ TID .1
(
231421-18
1-199
Ap·235
IPCD/UBR/CHUCK/CSRC/DLD. H
U_Iho,.,
u_Ihort
u_Ihol"
u_,hoort
I'"uet
.C1:_C"tl
link,
1* Nu.bl'''' o. but •• in buf'." *1
'*~
t to n •• t TBD . ,
••
,I' o.,
bu".'"
upp." S bits 0' bu"." .dd,. •••
to" •• 16 bit. 0'
buff_I.
.dd,.. ••• *1
*1
bu'fJu
1*
_Itu" -P'1'"
1* not u •• d ltV th. ~B.· u •• d It" th.
10ft...1". to ••v • • dd,.. ••• t"tlnst_tlon
!'outin.. *1
TI
I. T".n •• lt luff ..... *1
","uc:t TB
.
0(
ch.,. •••• nBUF JlIZEl.
)
• '1'Uc'
FD
(
u_Iho,., ,tatJ
U_IltO,., .1_1'
u_,ho,..t 1 in III
/. Sot.tu. Word of FD *1
,I' Receivi bu".'"
t
d'lct'ipto1" o., ••
/. EL and B bit. *1 '
1 ink "'. n •• FD *1
u_Iho,..' 1"lItd_o" •• tJ
I.
t *1
ch.,. •••• _ ••• l'[ADDJ.EMl'/*D. . tin •• ion . . . ,. . . . *1
chal' .,.c_add"tADDJ.ENl,
u_.ho,., l.ng.h.
'*
*'
Boul"ce add,... •••
Iff L.nl.h 'hU *1
).
1* R.c.iv. luf' ... D. . c,.ip'o" RBD *1
.tl'uc' RID (
v_shoT"
.ct_cnt'
1* Actual nUMb.,.. of b\lt •• ,..ceived *1
v_'hol"
linl"
1* D, . . . t to n.xt RBD *1
1* L.o .... ,. 16 bit. of 'ltu •• I''' .dd,. ••• *1
1* upp • .,. a It i
of buff.,. add ...... *1
/* 'IiI. of buff." *1
1* not u •• d It" the 586. u •• d It" the
'I
v_Iho,., buff_II
u_'ho,,' ltv" _hi
U Ihort
lirll
1i''rUc:t R8 .buf' J''I"'
10.t...". to •• v. address t,..nsl.'Uon
'routine *1
.tl'uct RI
1
out .. (O.FFK. 0.E009I1
'*1* .".tt,ENabi.
•
,..,'1'1'" *'
0 to Ti •• rl count
Ut In n .... l "od./Control .... h .... *1
S.t
R••• t_Ti ... eout ( )
(
Int'_Ti •• ,.C» /. 186'. Tl •• ,. 2 il • ,,. •• eall ... flo,. Tl ••,. 1. Jt o-locll. Ti ...,. 1,
IV.,. .. 32.7 ••• e. Th. d ......" ti •• Dut i • • • t 'DI' 1.25 •• c: . /
ou, .. (O.FF3S. O.OOOCh
1* S.t n .... l In .... ~upt Contul · .... h .... *1
out .. (O.FFIo2. O.FFFFII
1* •• t . . . count .... h .... fo .. U .... 2 to. OFFFFH *1
out .. (O.FFIIA.
:ISh
1* •• t . . . count .... h .... II
tt .... 1,*1
aut.CO.FF... o.COOat,
, . Set
,.:a MDd./Cant"'Dl
*1
out.(O.FFIIE. 0.1000'''1
1* S.t n ..... 1 "od./Control .... 1..... *1
out.. (O.FF2S. Cln.. (O.FFael • O.FFEFlh 1* In*U. 1810 n ..... l In ....... pt *1
outblO.E2. (ln~ (0.121 • O.OOEFIII
1* .n.bI. 10130 Inh .... upt ' .. Oil S01810 *1
'0..
Ti ••
,._.i.'.,.
1* .nd bnd ....... uppo .. t 'U"ctio". *1
Cha .. _Cnt( I
231421-24
1·205
inter
IPCO/USR/CHUCK/CSRC/DLD. C
leb. CT'c_e"" • • 0,
leb .• 1" __ .,." • • 0;
leb. ".c_e,." •• OJ
leb. OV'r __ "1"5 -
OJ
good_I.! t_cnt • OJ
und.,.."u"_cnt • 0,
no_,,,,_cnt • OJ
d• .,.", _cnt - OJ
.,e_e",. _cnt -
OJ
mill_col_cnt • OJ
".cv_'"••• _cnt • 0,
r ••• t_cnt • 0,
ItT'Uct ISep .pilcp.
u_'hoT't ii
,'".uci; MAT .pmat,
NO..ESI J.OOPBACK.
I . Don.
h~ B2501.
in 10ap'.cll *1
In.ctiv.te. CRB If po .. ered up
ESIJ.00PBACK.
1* Initialilation DLDI int.rrupt veeta,., *1
init_tntv( "
Inlt_Tim.,..(
'J
fl •••. ,. ••• t_••••• OJ
fla,l. ,. ••• t..".nd - 0;
fla.l. stat_on. 1,
pilep·
OxOOOOFFFO
J
I. Initialile the ISCP point.,..1
piICp->buIV - tl
pilcp->off •• t .
Off •• t( •• ,b',
pilcp->b . . . 1 • BEO..,. « 4.
pl.cp->b ••• 2 • CBEO"T » 12) • OIOOOF •
*'
pNULL • Bui1d-"t~CNULL).
I. build. NULL pointo~ - BOBI. typ.: 32 bih *1
BuildJUa(),
/* lnlt Receive F" ••• '/"' ••
Bulld_CbCl. 1* Init Co..... nd Block I i . t . ,
ma_cb. c:md • 0,
Multic •• t add" •• " " ••• phD". init *1
'*
Cl •• ,,_Cnt()1
leb .• t.t • OJ
CA.
I • ..ait fn the 5BIo to co.ploto initiali •• tion . ,
'01' ( i • OJ
i (. OxFFOO,
i++)
231421-25
1-206
Ap·235
IPCO/USR/CHUCK/CSRC/DLD. C
if (Ieb .• 10.1: . - (ex leNA»
tn' •• ' I
i f (I >OIFFOOI
Fat.-IC"DLD: in110 - Did not get an int.,. ... upt
.'t.,.
R••• t/CA\n"),
1* Ac" the r ••• t Int ....... upt *1
leb. clld • (eX I CNA),
C....
W.lt_ScbO.
En8blo
___ Intll.
'*
aeb. (bl_off •• t • Off •• tC.cb(01)i
leb. ,,' __of, •• t • O" •• tC.'dCO]),1
'0'1" U • OJ i (ADD..LENJ 1++)
who .... iCCADD.-LEN - 1) - il -
link aeb to cb and ,d lists
*'
inbCwho.",i_io_.dd + 1*:2),
1* Initi.-lizat1on the Multica.t Add,. ••• Tab1. *1
for (pmat • •1II.-1oCO]1 p•• t
p ... 1o-),1o.-, - FREEl
<-
ldIl.tCI'IULTI_ADDR_CNT -
Can'lgun( INTERNALJ.OOPBACKI.
'* S.t
IlJ
PINt++)
1* Put 586 in internat loopbaclc *1
up the .t.tion address
*'
1* run diagnoltic. *1
r •• t_Link();
I'
(Self_T •• t
!- PASSEDI
,..turnCS.l' _T •• t),
Con'igu".CNO_L00P8ACIU;
'* Con'igu,..
the 82586 *1
,..turneS.I' _T •• t)1
Bull dJ"a ( )
{
struct
.truct
• t1'uct
unligned
FD
RBD
RB
long
.p'di
.pl'bd •
.pbu',
b8dd.
1* Build. line.r linked 'ram. d.scriptor li.t *1
'a,. (p'd • "'dtOl. pfd
<- ..utFD_CNT
- I]; pfd++)
p'd->.t_t • p.d->el_, - OJ
pfd->l1n • • O,,..tlpfd+ll.
p'd->,.bd_a,,..t • NULL.
231421-26
1-207
inter
AP-235
IPCD/USR/CHUCK/CSRC/DLD. C
--p'd;
1* paint to It'dCFD_CNT - :1 J *1
pfd->llnk - NULL,
1* last 'd link 10 NULL *1
p.d->.I_, - ELBITi
1* l •• t fd h •• EL bit •• t *1
"_111"_"d - pfd • • 'd[O],
1* point to first fd *1
pfd-)l"bd_o".et - O'f •• t(lkrbdCOJ)J
1* link first 'd to fir.t ",bd *1
end_fd •
'*
faT
Build. lin •• ,. linked receive buf'.", d •• criptor lilt *1
(prbd -
pbu, •
1c1'bdtO].
lc"bu'[Ol,
pl'bd
<-
IcrbdtRBD_CNT -
prbd->buff _1 - badd,
»
prbd->buff _h - badd
prbd->buf. J'h' - pbuf'
pT'bd->.ct_cnt.
1].
pl'bd++,
badd .. SEOMT « 41
"add +- Offs.t(pbuf);
pbuf++) {
II..
01
pT'bd->link • O'f •• t(p"bd + 1)1
prbd->.h. - RBUF _SIZE,
end_l'bd • --prbdl
prbd->lInk - NULL,
prbd->Iiu I- ELBIT,
luild_CbO
<
,tT'uct
Itruct
.t.,.uct
unsigned
1* lut rbd poinh to NULL *1
1* 1.lt ,.bd h• • • 1 bit •• t *1
1* 8uild • • tack of ,,.. •• commend block. *1
CB
.pcb;
TBD *ptbdJ
T8
*pbu',
long
baddJ
floT' (pcb. Iccb[Oll pcb <- IccbrCB_CNT - 1];
pcb->atat - OJ
pcb->cmd • ELBITJ
pcb->link • O.f •• tCpcb + 1)J
pcb++)
0(
)
--pcbl
bagin_cbl = end_cbl pcb->Unk -= NULL.
pNULLI
cb_tol - Secb COli
1* BUIld II .. tack of transmit buf'.l" d.,cl"iptors *1
for (ptbd • S.tbd[Ol. pbu' - S.tbu'[O]. ptbd <:- s.tbdnBD_CNT - 11.
ptbd++,
pbuf++)
<
• TBUF_SIZEi
ptbd->lIct_cnt
ptbd->link • O,,..t(ptbd + Il'
b.dd • SEQ"T
«
4,
231421-27
1-208
intJ
AP-235
IPCD/UBR/CHUCK/CSRC/DLD. C
badd _ Off . . tcpbuf).
ptbd->buff_l - badd.
ptbd->buff _h - badd »
ptbd->buf' -It.,. - pbu',
--ptbd.
ptbd->lInk - NULL.
1obd_1ool • • tbdCOlJ
1* l . . t tbd link Is NULL *1
1* Set the Top 0' the Stacll *1
'* get. Co. . ."d Ilock
I'ruei;
C8
u ..
'T'OIi the fr •• 1 ist *1
*O.t_CbC) /* ,..tu'I'n .. point." to • 're. co...... nd black *1
(
,tT'uct
CB .pcb.
if CO'f •• t(p.:b - cb tal> •• NULL)
.... turn (pNULL) J
cb_tol. (st"uct C8 .> 8uild_PtrCpcb-)link)J
pcb->link • NULLJ
.,..tuT'n(pcb)J
1* Put .. Coramand Iloclc bacll onto the ,.,. •• lilt *1
struet
CB .pcb,
pcb-).1o.1o • 0;
pc:b->link . 0 " •• t(cb_1ool);
cb_tol - pcb.
510.,."C1o TID
*Oet_Tbd()
'* ,..tu,.n ..
pointe" t o . fr.e t,..nlmit
d •• c"lp1oo1' */
_truet
TBD
bu"."
.ptbdJ
flagl. ,. ••• t_•• m• • 1;
Di •• ble_5S6_lnt( h
if «ptbd - tbd_too) !- pNULL) (
1obd_1ool. CltT'Uct TBD .> Build_Pt,.(ptbd->link);
ptbd->lInk a NULL.
}
En.ble_586_lntC ),
'I_g •. r ••• t_••••• O.
if (flagl. n .. t ..... nd
1)
R••• t_5Bb( ),
1'.tuJ"n(ptbd);
231421-28
1-209
inter
AP-235
IPCO/UBR/CHUCK/CBRC/DLD. C
struet
Ten
*ptbds
(
strue t
*p ,
TBD
,. find the end of the tbd lilt ",eturned. ptltd il the bltginning *1
'aT' (p • ptbd;
p->linll !- NULL,
p->.ct_cnt • TBUF_SIZE.
p->linll • O" •• t(1;b._1;olh
tbd_toft
-= ptltd,
Itruet
CB
~f
P -
C.t,.uct TBD
~)
Butld_PtrCp->link»
1* cl •• ,. EOFBIT and ",d.t. ,izlt on l •• t
tltd *1
*pcbs
«pcb. get_Cb(»
_. pNULL)
Fatal"'d1d. c - S.tAd.,.. ••• - couldn't •• t • CB'n")J
'."dlf
1* DEBUe *1
bcoP'l( (cha,. *)lcpcb->p.l'lItl • •"'ho .... iCOl, ADD_LEN)J
1* Inove the p,.Oll
add"es. to IA emd *1
pcb->clld •
IA I ELBITJ
ISlue_CU_",md (pcl));
for (stat
= FALSE,
stat . - FALSEJ
) (
foT' (1=0. i<-OxFFOO. i++)
l ' (scb.,.d
0)
b"lt.k;
1f (i > OxFFOO) (
Bug("DLD: Seb command not cl ••,,\""),
CA;
.1&.
stat· TRUE,
231421-29
1-210
inter
Ap·235
/PCO/USR/CHUCK/CSRC/DLD.C
>
J •• u._CU_C.dCpcbl /* Gu.u. up • co••• nd .nd i •• u • • • t.rt
C~
co••• nd if no
oth.r co...nds .r. tu.u.d */
<
.truct
CB
*pcb,
Di •• bl._SS~_IntC)'
if Cb.gin_cbl •• pNULLI < /. if the li.t i. in.ctiv • • t.rt CU */
b.gin_cbl • •nd_cbl • pcb,
.cb.cbl_off •• t .0ff •• tCpcbl,
W.it-.scb( I,
.cb. c.d • CU_START'
S.t_Ti •• outCI,
/* •• t d•• dm.n tim.r for CU */
.ls.
CA,
)
>
<
.nd_cbl->11nk • Off •• tCpcb),
.nd_cb 1 - pcb,
En.bl._5S~_IntCI'
>
Jsr7C)
<
>
outbCOIEO.
Jsr~C
<
>
01~711
/* EOI BOl30 */
I
Writ.C"\nlnt.rrupt
outbCOIEO. OI~6)1
~\n"),
/* EOI 80130 */
JsrSC I
<
>
Writ.C"\nlnt.rrupt 5\n"II
outbCOIEO. OI~5I,
/* EOI 80130 */
/* D•• dm.n Ti •• r Int.rrupt S.rvic. Routin. */
/* Int.rrupt 4 */
R••• t_Ti •• outCI,
if Cfl.g •. r ••• t_•••• _. 11
fl.gs.r ••• t-p.nd • 1,
.1 ••
R••• t_5B~C I,
TJI£R1..EOI_801B~I
TIMER1..E0I_80130,
>
/* Int.rrupt 0 i. U.rt 1n UAP "odul. */
/* Int.rrupt 2 1. T1m.r 1n UAP "odul. */
231421-30
1-211
AP-235
IPCD/USR/CHUCK/CSRC/DLD. C
Io~1
0
(
Wl"ite(lI\nInt.,.,.up' 1\"-).1
outb (OxEO. Ox61 I.
1* EDI 80130 *1
1* 586 Int.r ... upt •• "vic. routine;
u_sho,.t
struet
Int."rupt 3 *1
'tat_Ielt'
.pcb.
CB
Welt_ScbO,
leb. cmd • 'stat_Ieb - leb. ,tat) &.:
(ex
I CNA I FR I RNR).
CA.
If (.ht_.cb .. (FR I RNRll
Recv_lnt_Proc ••• ing (),
i'
(Itat_Ieh • eNA) (
1* end of cb ,,.oc ••• ing *1
R.I.t_Ti •• oute)J
1* cl •• " d •• d.an tim."
pcb. SUildJ'tl"Clcb chl_off •• t),
*1
i f (b.gin_cbl •• pNULLH
BUIC"OLD: b.gin_cltl •• NULL in :l.nt.1""upt ,.outin.\n l , ) ,
".tu1"n,
i f «pcb->sht .. OxeOOOI
!. Ox8OOO1
Fatal (I'DLD: C bit not .et 01' 8 bit •• t in tnt.,.,.upt 1"outin.\n"),
•• ndi'
'*
DEBUg *1
... itch (pcb->c .. d .. CMD_I'IASKI (
ce . . TRANSMIT:
1*
i'
Iq.. b i t . 0 and the,.. w..... no collilionl -> 1,- .""'01"
thil condition will occur on the fl,.,t t,.ansmi •• ian if
the,.. life". no coll'lionl, or if the p .... vioul t ... anl"it
CD_and ..... ch.d the ma. collision countl and the cu ....... nt
t.,.ansmisstDn had no coll i'lionl -,
i f «pcb->.tat .. (SOEI1ASK I I1AXCDLI'IASK I CDLLI'IASKll m= 0)
++'1 .... _ • .,. ... _cnt;
i f (pcb-:>.tat .. DEFERMASK)
++d.f • .,. _cnt;
231421-31
1-212
AP-235
IPCO/USR/CHUCK/CBRC/DLD. C
I' (pcb->.tat • NOERRBITl
++100'_1.1 '_entJ
.1 •• (
If (pcb->.ht • NQCRII11ASK)
++no_c",,_cnti
H
(pcb->.tat • UNDERRU_SK)
H
(pcb->.tat • "",XCOL"",SK)
++••• _col_c"tl
++und.,..,..u"_cnt,
~
if (pcb-:>p.".l !- NULL)
Put_lbd (Bui Id-"t~ (pcb->pa~ .. I» J
b,. •• 11I
c . . o DIAQNOBE:
'1 •••. di •• _done -
lJ
if «pcb->.tat • NOERRBIT) •• 0)
Sol' _Tnt • FAILED"pIAONOBEJ
b,.. •• lu
d."Ault:
if (pcb->Unk •• NULL)
begin_cb! • pNULLI
bogin_cbl • Build-"t~Cpcb->1ink)J
leb. cbl_o., •• t • pcb->11"1I1
Wait_ScbClJ
Icb. enid. CU_START'
CAJ
Weit_ScbClJ
Set_TlI11Route),
1* START d •• dman tim .... *1
~
'* cllock••,.. ••••
Me_SETUP emd
pha".
th.t
i f « pcb->cJld • CIID-"_) •• Me_SETUP)
pcb->emd • OJ
blO1'd,
10
this will implement a
i t won't be ,..used until
i t i . completed *1
.1 ••
Put_Ct.(pcb)J 1* Don't l'eturn Me_SETUP emd blOck. It ' , not a
•• ne",.1 pUl'po •• command block from f" •• CB list *1
dis.bl.()J
EOI_SOI30J
1* di •• bl. cpu int 10 that the 586 ill' ..,ill not nelt *1
231421-32
1-213
AP·235
IPCD/UBR/CHUCK/CBRC/DLD. C
RecY_lnt,JI'rDc ••• :lnIC)
(
•• ruet
.truet
*,.d.
FD
RBD
.... '
*,,.bd,
'*
the For •••
. . ./
'* point. to the .i .... "ltd fafo1'... thethe .,.."'.•••
*'
point. to
D.,c1'ipto1' . ,
I . point. to the 1a.t
,,~d
t
'01' (p.,I • b_.ln_.d. p,,I !- pNULL. p.d • ".gin_.d)
I' Ip'd->at.t • CIITI (
hgln_fd - lat,.uct FD
lulld...pt,.lp'd->lInkl.
P,.U - lat,.uct RID e, luild...pt,.lp.d->Y'bd_o""U,
if (p ... bd !- pNULL) (
check to ••• if • lIuf'e'r i . attach.d *1
*'
'*
i f Ip,.U !- hgln_,.bd~
Fatal« "OLD: p'I'ltd !- " •• 1"_1"1111 in Recv_lntJl'oc ••• :lng\n")J
.end I. I. DEIUg el
'0,. III - P,.U. IIl->.ct_cnt. EDFIITI !- ECFllT.
Il - lat,.uct RID e, lulld...pt,.I 1l->lInkl "
b.gln_"U - lat,.uct RID
1l->lIn~ - NULL.
*'
lulld...pt,.IIl->lInkl.
~
I' Ipfd->at.t • DUTJIFJlESOURCEB'
PutJ'.... JlFAlp.d I'
el •• (
/. i'
the OLD i . in a 100p".cll t •• t,
i f Ifl.ga. Ipb~...oood. -- 11
Loopb.c~_Chec
eheell the ,.,.•••
".ey
*'
k I p'd"
81 ••
'* i.
it ' • • •ultic •• t .dd,. ••• checll to ••• if it '.
If I
81 ••
(
in the _ultica.t add" ••• table,
IIp.d->d . . t...oodd,.[OJ .011 PutJ'.... JlFACp'd ,.
i'
not d:l.c."d the ,,. •••
*'
011 . . I!CheckJluIUcntlpfdll'
Recvj" ••• Cpfd),
++r.CY_'1" ••• _cnt,
~
~
~
81 •• (
Ru_St.","'C)J 1*
I.
RU It •• Ion. into no "' •• OU1"C • • ,'
..... t.,.,
it *1
b..... II,
Loopbeck_Ch.ck Ipfd'
at,.uct
FD
1* C.lled b\l R.cv_llI'J'1"oc ••• tngJ checll • • dd,.. •••
• nd ·dete 0' ,potentl.1
100Pb.c~
.,.••• • ,
epfd.
at,.uct RID
*p,.bd •
• t ... uct R8
.,buf,
231421-33
1-214
inter
AP·235
IPCO/UBR/CHUCK/CSRC/DLD. C
if ( bUlp«ch." .> .p.d->.", __ dd,..[O],
Put_F ..... _RFACpfd )J
.... turnJ
)
.>
,,,ltd. CltT'Uct RBD
"who •• iCOl,
ADD_LEN)
Buj,ld_PtrCp.d->rbd_o.fI •• t)J
!- 0
)
<
1* potnt to ... e,e:ava
bu"." d."T'1,to1' *1
,bu' • (struet RS .) ,l"bd->buf'Jtr, 1* point to r.ceive buff." *1
141 ( bCIII,C (cha,. .) ,buf, .I'bll_',..••• [O), LP8KjRAM_SIZE)
I.
0) .(
Put_Fuo_RFAC pfd) I
".turn,
f1alll. 1,1I1I_, •• t •
PutJuo.JIFAC p fd) I
1,.
'*
p •••• d 100, .. acll t •• t *1
CheclcJ1ultica.tCp'd)
/* ,..tu,.ns t"ua if! multic •• t addT'"."
",.uet
FD .p'd,
t. in MAT *1
,t,.uet
'01' (p.at • •matCOl, p•• t <- ... tCPfULT1.JtDDR_CNT - III pmat++)
if ( p",at->.tat •• INUSE ••
(bem, ( (ch.,. .) .pfd-)d •• t_add,.C01. 'pmat->.ddr[Ol, ADD-.L.EN) •• 0»
br •• k,
i f Cp ... t > .... tcI1ULTI_ADDR_CNT ,..tuT'n(FALSE)1
ll)
"etu1'nCTRUE)J
T. . tJ.inkC)
(
S.l f _T •• t • PASSED,
Diagno •• C) J
,
i f CSoH_Toot -- FAILEDJlIAONOSE)
1".tU1"n;
Ru_StaT'tC);
1* .taT't up th. RU foT' loopbacll t •• ts *1
flag •. lpbll_mod • • 11 1* go into loopbaclr .od. *1
'*
fl_g •. Ipblr_t •• t • OJ 1* •• t loobacll t.st to "al •• *1
S.nd_Lpbk_Fra•• C);
int."nal loopb_ck t.st *1
if (fla.s. lpblr_t •• t •• 0) (
SoH _T •• t
-
FAILEDJ.PBK_INTERNALI
'lags. lpblcJ'Qd • • 0,
r.tUT'nJ
fl_.s, lpblr_t.st • 0;
Con'i.ur.(EXTERNAL~OOPSACK);
1* external loopback test "'/ ESI In Ipbk *1
SondJ.pbk_Fn... C)1
if ('Ia ••. lpblr_t •• t •• 0) 0(
SoH _Tnt - FAILEDJ.PBK..EXTERNAL;
231421-34
1-215
intJ
AP-235
IPCO/USR/CHUCK/CSRC/DLD. C
,lA.I. IpllkJlGd • • OJ
".tuY'nl
flagl. Ipbk_hlt • 0,
NOj:SI..LODPBACK,
Sand..Lp bkjra... ( ),
If (flagl. Ipbk_tut . . 0)
Salf _Tut • FAILED..LP8K_TRANIICEIYER,
Band..Lpbkjral.. ( )
(
Itrue'
Int
fo1' U
.p'bdl
TBD
II
•
OJ
t
< a,
i++)
*'
1* .end 1,IIk ,,.••• B ti •• I.
b.lt ,'foT't d.liv .... .,
linc' it"
'!fdaf DEBUO
If «ptbd • Oat_TbdO) •• pNULL)
FatalC"clld - S.ndJ-pbkJ" ••• - couldn't g.t • TBD\nll)J
•• nd1f 1* DEBUQ *1
p'bd->act_cnt • EOFBIT I LP8KjRAI'IE_SIZE.
« char *) p'bd->buff Jtr. Iolpbk_frama[Ol. LPBKjRAI1E_SIZE),
bcap~
D1a.no •• ( )
{
st1'uct
CB
.pcbi
IUdaf DEBUG
If «pcb - Oat_Cb())
pNULL)
Fatal< "did - Diagno •• - could" 't I.t .. C8\n");
•• ls •
•• nd
l'
1* DEBUQ *1
'lagl. dia,_don • • OJ
S.lf _T.st • FALSE,
pcb->cmd - DIAONOSE I ELBIT.
Illu._CU_Clld (pcb) J
"'hil' (flagl. dial_danl •• 0)
j
1* Idait fo1' Dial ellld to finish *1
231421-35
1-216
inter
AP-235
IPCD/UBR/CHUCIVCBRC/DLD. C
Conflilu". (loop'l_g)
u_Iho,,' loop' 1•• ,
a''ruet
.pcb,
CB
Ilfd.' DEBVO
I' «pcb. CI.'_Cb II I -- pNULLI
FataIC".Ud - Con,tgu,.. - couldn't ,et. C8\n")'
•• 1 ••
pcb - CI.'_Cb( I,
'.nd I f I . DEBVO . ,
pcb-:>' ....."'1 pcb-)operoo2 pcb->p."t13 •
pcb-)p.,..1It4 •
pcb-)pa"fI' •
I ' Iloopfl_,
o.osoc,
012600 I 100pl1_.,
0.6000,
OxF2001
0.0000,
-- NDJ.CXJPBACKI
,cb-)op • .,.• • 0.0040,
e1 ••
t. I ••• ttl.. t •• than
the .lnt.u. ,,.. ••• 1enlth *1
pc b->p."' • • • 0.0006,
pcb->Uld
-
C~IClURE
/* 100P'8CIr .,,. •••
!LaIn
*'
1* Se"d a ,,.a •• to the cab 1•• p • • • • point." to the, d •• tination add,. •••
and a point." to the ft".t t,.an •• it bu"." d.'C1'jpt01'.
,*
Sendj.,.a.eCptbd, p.dd)
,..tu""s fa1 •• if i t can't g_t • Co. . .nd block
ot,.uct
TID
.ptbd,
eh."
.p.dd,
*'
(
s'"uet
C8
.pclu
if «pcb· Oat_Cit (» -- pNU...L)
., 1•••. .,. ••• ,_. . . . - O.
if ('1 •••. ,.. ••• t....P.nd •• 1)
R••• t_586C )i
,..tu,.nCFAL.8E) I
0(
pcb-)pnMl - Df, . . t(pUdl,
231421-36
1-217
inter
Ap·235
IPCO/USR/CHUCK/CSRC/DLD. C
/. Move de.tination .dd,. ••• to co. .and block */
bcoPv«cha" .'.pcb->p • .,..2, (ch.,. .)padd, ADDJ.EN)J
fo~
(Iongth - O. ptbd-:>link !- NULL. ptbd -
11n,th +- ptbd-:>.ct_cntl
l.ngth +- (ptbd->act_cnt Ie O.3FFF)J
1* chick to
I ••
i'
padding
il
'*
Bui1d.J't~(ptbd-:>lInk))
add thl 1•• t buff.,. *1
!"'lI.ulr.d, do not do padding on loopb.ck
*'
1* this .. 111 nat ..a~k i f "IN_OATA.J.EN :> TBUF_SIZE *1
If
« Iongth < "INJlATA.J.EN)....
(bCllpUcwho •• iCOl,
pcb-)cmd - TRANS"IT
ISSUI_CU_C"'d (pcb) J
fl •••. ,. ••• t_••••• 0;
if ('lag •. 1' ••• t-'.nd
R. . . t_lIS6( ),
1* . . . u. . . . 4 b~t. CRC *1
ADDJ.EN) !- 0»
(cha,.. .)padd,
ELBIT.
1)
'I'ltul'nCTRUE),1
)
Add_... ultic •• t_Add,. ••• Cp. . )
cha,.
.pm.;
_vlti, •• t
'* 1'.t",,,"lnl
, .. 1. . . . . . ns
"ultic •• " .dd,. •••
ts
*1
1* p.I - pointl" to
adel" ••• • ,
thl
t.b1.
full
1* if thl mu1tic •• t addr, •• t . . . duplicat, 0' onl all" •• dv in the HAT.
thin rltul'n *1
p •• 1:: <- ... 1::CMULTI_ADDR_CNT - III p ... 1::++)
if ( ,m.1::->_t.1:: _. INUIE ••
(be.pC .p •• 1::->.ddl'COl, (chal' *) P•• ' ADDJ-EN) _. 0»
l'etu ... n(TRUE);
for (pmilt • m.ti
fal' (pmat . . . tJ ,.at <- ... ttMULTl_ADDR_CNT - lJ, , •• t++)
if (p.at->.1::.1:: •• FREE) (
p•• t->.1::a1:: • lNUSEJ
beaPIJ( .p .... t->.dd ... COJ, (ch .... *) p.a, ADD.-LEN);
b.,. •• I"
231421-37
1-218
inter
AP-235
IPCD/USR/CHUCK/CSRC/DLD. C
If
> .... ttI1ULTlJlDDR_CNT
(p ... t
- III (
'lags. ,. ••• t_••••• OJ
if ('lags. " ••• t-P.nd •• 1)
R. . . t_'Sh(l)
.,..turnCFALSE)I
S.tJluIUc . . 'Jldd ..... ( I)
nag •. ,. ••• t_•••• - 01
if ('lag', ,.. ••• tJ.nd •• 1)
R••• t_,.( ),
",etuT'nCTRUE)J
/. ,..turning f.l . . . . . .n. the lIIultic •• t add" •••
.... not found
D.l.t._"ultic •• t-l'dd" ••• Cp •• )
'or
(p •• t
i' (
*'
.....;, , •• <- •••
,.at->.,.,
_.
t
ttf1ULTl~DDR_CNT
INUSE , .
(bc.p( 'p •• t->add ... CO], (cha,..) pM.
p •• t->.tat • FREEl
br •• lei
If (p ... ' > ••• ttI1ULTI_ADDR_CNT flagl. ", ••• t_, ••a • OJ
if ('l •••. 1" • • • tJ.nd ._1)
III
- III
p •• t++)
ADD~EN)
. - 0»
<
R••• t_~( ).
".turn (FALSE) i
Set_"ultica.t_Add" •• " );
fl ••• r ••• t_••••• 0,
if C'la.l, r ••• tJend •• 1)
R••• t_S86( ),
r.tul"nCTRUE),
st1"uct
struet
u_'hort
MAT
M"_C8
i)
.p •• t,
.p •• _c b J
i • 0;
pma_c b ...... _c b J
... hil. (p •• _cb->c.d !- 0)
pm._cb->linlr • NULLJ
f
'* if
th. MA_CB i . inu •• , .... it until it". ,f".e *1
231421-38
1-219
AP-235
IPCD/UBR/CHUCIVCBRC/DLD. C
fo1' 'pilat ••• t, ,Mat <- ..... tCtNLTJ-"DDR_CNT - III p... t++)
If ( p..at->.ta' lNUBE) <
beopv ( .p . ._cb->OIc_addrC IJ, .p_t->addrCOJ, ADD_LEN) I
I +- ADDJ-ENI
p•• _cb->.c_cnt • j,
p..a_cb->cllld - IIC_SETUP I ELBITI
Put_Fl' •• ..RFACpfd)
struet
FD
strue t
R&D
'*
R.tu .... n F...... D•• c'I'1pto1' end Receive Bu"."
O•• c"I,1;o.,.. to the F,.. •• Receive F"••• A,. •• *1
'* point. to end of ,..tu1'n.d RBD 1 tst
'* indicat ••
to " •• ta1'1;
.,J
.p,.bd~
/*
T'U_st.,.t_'l •• _'d.
1'U_st.,.t_fl·I_"bd,
point. to beginning of ,..tu1'ned RID list
*1
UIIh.t~."
RU *1
*'
'lags . .,. ••• t_...... 1,
l'U_st.l"'t_fl.U_'d • 1'u_sta,.t_'lal_"bd • FALSEI
pfd->e1_• • ELBITI
pfld->st.t - 0,
p1"bd • CstT'uct RID .) Build-pt"Cpfd-),.bd_of!, •• t), /* pick up the link to the "ltd *1
,fd->11n • • pfd-:>rbd_o,., •• t • NULL,
1* Di •• bl._~B._lntC), this co ..... nd t. anI., nee.ss.,. .. in _ multita.lling
p,..og,...m. Howeve,.. in this lingle t.sk .n'1'1,.on.ent this routine i. origin.llv
c.lled 'rom is,.. _MI6(). there'o",. inte,..,.upt • • ,.. • • l,. •• d .. , dis.bled *1
If (bogln_fd -
pNULL)
bagin_'d • end_fd - p'dJ
e1,.
<
ond_fd->link - Dff •• t(pfdl,
end_'d->el_, • OJ
end_'d • p'dJ
,.u_,t .... t_'l.g_'d - TRUE,
1* i ' th.,..e Is • rbd att.ched to the 'd then
find the baginning .nd end
the ,..bd list *1
0'
for (q =- pY"bdJ
,->link !- NULLJ
q,->act_cnt • 0,
Cl. Build_PtY"(q-:>linl!»
1* now p,..bd point. to the beginning of the ,.tld list and
Cl points to the end of the lilt *1
,->.i
z• • RBUF _SiZE I ELBITI
q,->.,1;_,n1; • 0,
231421-39
1-220
AP-235
IPCO/USR/CHUCK/CSRC/DLD. C
'*
's
if th.,..
ct' •• t • •
b.gin_"bd • ,,.1141,
end_"l:td • Il'
I f (prbd !. q)
1'u_Ita"t_.l.,_"bd • TRUE)
nothing on the 1 ilt
new l i l t *1
'*
if th.". i , flO"'. than on_ "bd
.... tu1"ned
,t."t
the RU
*'
1* if the rbd lilt e1'r' •• tlv eliltl add on
the ne ... ,..tu1"ned ,.1141, *1
a"..
.nd_rbd->lInk •
t(prbd),
.nd_rbd->o' . . . RBUF _SIZE,
end_",bd • II'
ru_,t .... '_'l •• _rlld • TRUE,
)
i ' (ru_otert_nal_'d WI ru_otert_nal_rbd)
'*
Ru_St."t () I
Enable_'S6_lnt<),
I' Di •• ble_5B6_Int() 11 uI.d aboy. *1
'1 .......... t_...... 0,
if ('I •••. ,. ••• ,-I.nd ··1)
R••• '_5fW.( ),
if «Ieb. ,tat. RU_""SK) •• RU_READY) 1* if the RU Is al" •• dv
~"' •• dtJ
I
then .,..turn *1
I'
«b.gi"_fd->stat Ie CBIT) •• CBIT)
... eturn!
begin_'d->rbd_O" •• t • O" •• t(begin_rbd)J
Ie b. r'a_o" •• t • O" •• t (beg in_'d),
*'
1* link the b •• 'nning 0' the ,.bd
list to the fi,.,t Id
Wait_BebC );
.eb. emd -
RU_START,
CA.
Softw• .,.e.-R_.et ( )
<
seb emd •
CAl
W.it_Scb
RESETl
()I
I •• u._Re.et_C",dl ()
<
W.. it_Scb( );
seb. cmd -
CU_START;
CAl
231421-40
1-221
AP-235
IPCO/UBR/CHUCK/CBRC/DLD. C
Wat t..Beb I II
DuttliCOxFFSE, 0)
i
out .. ITII1ER1_CMT. 0),
outw(OIFFIIE. OICOO911
'*
shut o'f tilt." 1 intl"l"upt
..hll. (UnwIOIFFIIE) " 010020) •• 0)
*'
I . If 11.1 ent Ht h
set hfor. eNA
il, •• t,. 586 C.d d •• dlocll.d
i f I loeb. ot.t " eMA) •• eMA)
br •• lu
*'
If (oeb. atet " eMil !. CMII)
Fat.-l e'tOLD: 1•• UIJt, •• t_C.dl - Ca. . .nd d •• dlode dUT'tng " ••• t 'T'oC::ldu".\n"),
R••• t_Ti •• oute
)J
leb. c.d • CHAI
ell,
1* Acllnowled •• (NA intll'T'upt *1
Watt_SebO,
'*
E •• cute .. ,.. ••• ,. Configu" •• SetAddT"'"
R. . .Rleliv.
t _ _ () Unit and thl Ca. . .nd Unit
*'
and t1C_SltU'.
thin
'I" • •
t • .,., the
(
I1AT
I,
++,. ••• '_cntJ
DI . . b1e_H6_Intc ),
ESI.J-OQPBACK,
So,t .... ,.._R ••• t(
),
leb .• tet • OJ
'Of'
( :i • OJ i <- OxFFOOJ i++)
if elcb.ltat _. (eX leMA»
b1" •• alJ
If I i >OIFFOO)
Fatal ("DLD: inlt - Did not •• t an interrupt
/. Ack the ,..I •• t Int.,.-"upt
Wai'_ScbC ),
leb. clftd • (eX I CNA),
*'
.ft.,.
Soft....,.e R•• ,t'n·);
ell,
Weit_Sebl ),
Ilfd.f
DEBUG
l.ndU
Fatal C"DLD: begil,_cbl • NULL in R••• t_58.")J
1* DEBUG *1
If I hgin_ebl •• pNUU.)
231421-41
inter
AP-235
IPCO/USR/CHUCIVCBRC/DLO. C
'* d.fault
1* Configur. the 586
*'••• t.".,
p.,.
Eth.rnet d.fault
p • .,. •• et.,..
Can,tlv". i . nat n.e •••• "\1 when using
*/
r.,_c b. ,.,..-2
p.,.,111 - Oloeoe,
.,..,_cb.
- 0.2600.
".,_cll. p.,...3 • 0.6000.
r.,_cb. p.,.... OIF200.
".,_cb. p.,..' • 0.0000,
".,_c". p.r....
re._cb. clld
010040.
- CONFIIlURE I ELIIT.
leb. cbl_o" •• t • 0" ••
1;(.,..,_, ... Itat),
1•• ueJ' ••• t_C ••• C ),
1* S.t tho Individual "'ddre . . *1
bcapvC (tha,.. .) "'.,_cb. p.,..l, _hoa.iCOl, ADD..LEN), 1* .ove the pro •
• dd,. ••• to IA elld
,..,_cb. eMd • JA I ELIITI
1•• u.~
...
t_C.d.(
*'
)J
t • ,. •• __ a_cll. stat. 0,
1' • • ~_cb.
11nll • NULL,
far (pm.t - .... tCOl. p ..at <- ... tUIIJLTlJlDDR_CNT - Il. p_t++)
If ( p ..at-:>.tat -- INUSE ) (
bcapv ( .r ......... _cb. IIc_.ddr[i l. .p .. at-:>addrCOl. ADD.-LEN).
I +- "'DDJ.EN.
" •• ..m._cb.lle_cnt • iJ
1' • • ~._cb.c.d
leb.
cbl_o., •• t
- Me_SETUP I ELIIT.
- 0, •••
1;'11,..,_•• _, ... Itat)J
I'lu • .ft~5.t_C.d.( ),
'* R••
t.",t the COINNnd unit end the R.,aiv. Unit
*'
flag •. " ••• t_. . . . . OJ
flag •. T ••• tJ.nd • OJ
R.cv_lntJToc: ••• ingC
)J
.cb. cbl_o •••• t • begin_cbli
W.lt_ScbO.
231421-42
1-223
inter
AP-235
IPCO/USR/CHUCK/CBRC/DLD. C
scb. cmd • CU_STARTJ
Slt_Tilt.aut () I
1* B.t D.ad,.an Tim." *1
CAl
Enab 1o_5B6_Int () I
'*bcapwell."
tlCOP\! -- b"t. COP\! .,.au'Un.
ch.,.
in.
.re, nbut •• )
-.,..c,
nllvt •• ,
*'
.dlt,
(
whil. Cnbvt'I--) *1I,t++ • • '''c++'
It",.
1* bClI, -COlllp.".
tlcltpCII, • .;z, nbut •• )
It
h."
c
Int
*.
._2,
*'
nb~h'l
(
whUI (nb\lt.,-- . . . . 1++ • • • ,:12++),
.,.,tul'n'*--,l ... *--,2),
231421-43
1-224
inter
AP-235
IPCO/UBR/CHUCK/CSRC/LLC. C
, •••••********* •••••••••** .............................*****.****••• ********* ...
•*
..
IEEE B02. 2 Log ical Link Cont~ol LaVer
(St.tion Component)
..
••••• ***•••• **•••••••••••••••••••••••• *••••••••••••***.******.*.*•••• *.* •••••• 1
4Unclud. "dld. h"
ext.,.n
.xt.,..n
.t1"uct
cha",
,. •• donl., ch."
1* OSAP, aSAP.
TBD -o.t_TbdC)J
_lui ld""p'" C"
.id_.,.••• CXID.-LENOTHl. ( O.
XID. xid c1 ••• 1 ,. •• pon.e *1
0,
XID, O.Sl, 0.01. O)J
Init.J.lc ()
<
st~uct
'or
LAT
*plat.
(plat - "lat[Ol, plat
p l.t->.t., • FREE,
<-
"at[DBAP_CNT -
ll'
plat++)
,..turnC Init_'86(»,
*'
1* Function floT' adding a new HAP
Add_O •• p_Add" ••• ed •• p,
int d •• pI
<
.t",uct
,fun.:;)
'* 2**N -
DSAP ",ust b. divisible bV a •• CS-N),
tAlh.,..
DBAP _CNT. Ii... N LBa. must bo· 01.
The function will .,..tu,.n FALSE if do •• not
••• t the above "e,ui" ••• ntl, 0" the LI.p
Add"' ••• T.bl. i . full. 0'" the .dd"' ••• h ••
al",.ad" b •• n uS.d. NULL.. DSAP .dd"' ••• i .
"' ••• "'v.d fo'" the St.tion Component *1
(*pfunc) 01
LAT
if «d.ap « (8-DSAP_SHIFT) "OxOOFF) ' . 0 : I d.ap •• 0)
",.tu",n (FALSE);
1* Ch.ck fo'" duplicate d •• p •. *1
i f ( (plat. ".tld . . p » DSAP_BHIFTl)->.tat == FREE)
P lat->.t.t • INUSEI
plat->p_•• p_func • pflunci
retu~n (TRUE"
<
.1 ••
",.tu",n(FALSE)1
1* FUnction flo", deleting DSAP. *1
O.I.t._D •• p_Add"' ••• (d •• p) 1* If the .p.cifi.d connection .:IIi.t •• it i • • ev.",.d.
If the connection do •• not .xist. the contm.nd is igno",.d, *1
231421-44
1-225
intJ
AP-235
IPCO/USR/CHUCIVCSRC/LLC. C
Recv_Frame(pfld)
.truct
FD
stT'uct
RBD
*pfdJ
FRAIIE STRUCT
stT'uct
LAT
prbd •
pIs •
.,f.,
*prbd;
.t~uct
*plat,
-
(stl"uct RBD *) BUlldJt,.(pfd-:>rbd_o'f •• t),
(stl"uct FRAHE_STRUCT *) prbd-)buff _ptT'i
l ' (pfd->l'bd_o" •• t
!- NULL) ( 1* The,..e has to be .. rbd attached
to the fd.
if (pfs->d •• p •• 0) (
01" e1&e the flrame
J.5
too short. *1
1* if the ,,..me i . add.,.e,s.d to the Station
Component. then. ,.. •• pon •• mav b. "equi,..d *1
l ' ( I (pfs-> ••• p "C_R_BIT) ) (/* l ' the f"allle ... ecelved 1~ a respons ••
lnst •• d 0' • command, then .... Ject it.
aecau •• this soft",.re do •• not Implement
DUPL.ICATE_ADDRESS_CHECK. -> no "esponse
f,..m •• should b .... ecv'd *1
Stati o"_Component_R •• pons. (pfd);
~
1* not .ddr •••• d to St.tion Component. *1
1* check to 5 •• If the d •• p .ddressed 15 .ctiVIt *1
010. i f «ph->d •• p « (B-DSAP _SHIFT! .. O,OOFF)
0 ....
(plat _ IoI.t[(·ph->d . . p) » OSAP_SHIFTJ)->.tat .- INUSE ) {
<*plat->p_sap_func)(pf'd)J
1* call the function ••• oclated
"'lth thlt dsap recltivltd *1
returnJ
~
Put_Fl'lte_RFACp'd);
&truct
.t~uct
FO
f*
r.tul'n thlt pfd
i'
not glvltn to thlt u •• r saps *1
*p'di
FRAHE_STRUCT
st1'uct TBO
stT'uct RBD
*pl'fS. *ptls.
*ptbd. *bltginJtbd. *CI.;
*prbdi
pl'bd - (stl'uct RBD *) Build_Ptr(pfd-)l'bd_offs.t);
p1". = (stl'uct FRAME_SrRUeT *) pl'bd->buff Jtl';
... itch
(p~"->c",d
10
~PJ JIlT)
{
cas.
XID:
231421-45
1-226
AP-235
IPCO/USR/CHUCK/CSRC/LLC. C
"'hile «ptbd •
O.t_TbdC»
•• pNULL.) ,
ptbd->act_cnt • EOFBIT I XIDJ.ENlITHI
bCDP., «chaT' *> ptbd-)buff...,ptl". &cxid_frametOl.
pt, • • (,t"uct FRAf'IE_STRUCT
*)
XIDJ.ENGTH).
ptbd->buff -pt".
ptfl->cmd - pr's-)cmdJ
ptf.->d •• p •
prll->".p
I C_R_BITJ
c...
1* .... turn the ,,, •••
to the aende" *1
pt,.-> ••• p • OJ
while( !Sendj,..meCptbd. BUlld_PtrCpfd-::>.rc. addT'»)'
bT" •• lu
TEST'
for (pT'bd •
(Itruct RID
,
•
*)
Build_Pt",(pfd-::>,.bd_off •• t),
beg1nJtbd -
pNULL.1
p,.bd
!- pNUL.L.
p,.bd • Build_Pt,.Cprbd->link»
while «ptbd • O.t_Tbd(» •• pNULL).
if (q, !- pNULL)
q->link • Oflf •• tCptbd),
_I ••
begin-ptbd • ptbdJ
ptbd->.ct_cnt • prbd->.ct_cnt;
bcopy«cha" .) ptbd->bu'f..,ptr.
Cl -
(chill'
*>
pT'bd->buffJtr.
ptbd->act_cnt tc Ox3FFF);
ptbdl
ptf • • (struct FRAME_STRUeT *) beglnJtbd->buff .. ptr.
ptfs-:>cmd • pr'.->cmdl
ptfs->d.ap •
prfs-)ss.p
I C_R_BITJ
1* return the frame to
the sende..,. *1
ptfs->s •• p .. 0,
.... h i 1 e ( ! SendJrame (beg In,J tbd,
bre.kl
Bui! d_ptr (p fd-)src_addT'} , ),
231421-46
1-227
AP-235
IPCD/USR/CHUCK/CSRC/UAP. C
, ••**••••••*••••••***•••••••••••••••••••••••••••••••••••••*•••**•••••**••**••
....
...
u•• ",
.••••••••••*••••••*••••••***•••••••••*••••*•••••••****••*******.*.*•••*******.1..
Application PrOI,.a•
Asunc to IEEE 802. ;!lsoa. 3 PT'otocol Conv.,.t."
I
'
.include "dId. hI!
1* ABC I 1 Ch.,..c
Idofino ESC
Idofino LF
Idofino CR
.dofino BS
Ido.ino BEL
.dofino SP
Ido'ino DEL
Idofino CTLS
1* He ... d •• .,..
Ido.ino
Ido.in.
Ido.ino
.dofin.
.defino
t.,..
*1
O.IB
OIOA
0.00
0.08
0.07
0.20
017F
0.03
*'
CHJlSTL
O.OODE
CH...A_CTL
O.OODC
CHJI_DAT
0100011
CH...A..DAT
O.OODS
UARTJlTAT --"11K
0170
1* Jnt.,.,.upt c •••• fa," &:z74' *1
.dofino UART _TXJI
0
Ido.in. UART..RECYJI
OIOS
Idofin. UART_RECY_ERRJI Oloe
Ido.ino EXT_STAT_INTJI 0104
Idofino EXT_STAT_INT...A 0.14
chu
ch.,..
fifo_U2'IIJ/
f1fo_"C2543;
cha,.
WY'a[51, ...,..bt811
unstlned
ch.r
in_'flifD_t,
out_fifo t, :l.n_fllo_", out_flfo_t", actual,
t_buf _stat, ,. _bu' _Itat,
u_ahort
cbuftB01;
1 in.Cel],
1* Co...and 1 in. buff.,. *1
"ani tal' Mod. displ." lin.
I.
*'
unslgned
cha",
d•• p, 's.p, •• nd_'I.g, 10c.I_.cho,
ch.,.
Dos'_Add"CADDJ.ENJ/
cha"
"ulh...Add"CADDJ.ENJ/
lnt tmst.t, 1* te"msn.1 tltod ... t.tus. 'a" I •• vsng t.""un.1 iliad. *1
tnt dh •• , manlto,,_'I.g, hs_st.t,
1* 'I_gs *1
.t"uct T8D
ch.,.
.,g.t_TbdO/
*Build_Pt,.C ),
.xt."n
.t'ruet FLAQS
'lags,
•• t.,,"
ch."
ch."
•• t."n
•• t."n
•• t."n
.id_'...... C]J
whoa.tC];
231421-47
1-228
AP-235
IPCD/USR/CHUCK/CSRC/UAP. C
.xt • .,."
I.t,,."
•• t,,."
..",."
...a',,."
•• t.,."
l'I'vet
1'1"UCt
cb.,.
unliln.d lonl
u_,ho,.t
U_IhD1"t
.1",."
I.t.,," un"lned
u_,ho... '
",."
.It.,.n u_,ho,.,
unl'lne"
'X""" u_'ho'l"t
.It .... "
. .UJ.
IlAT
LAT
laUJ.
*pNULL.
""uet
100._•• i '_ent.
und.,.,.u"_cnta
no_c,.,_cn'lI
d" .... _cnt,
Ionl
.,1_'"''_cntll
••• _col_ent.
,..Cy_.,. ••• _cntll
,. ••• t_ent'
lonl
sea
.clt.
a •• Uno RTI..DN8 out~ ICH..JI_CTL. 0.0111. ou"ICH..JI_CTL. ""~[IIJ-..,.btIlJ 10.021
RTIJIFF. ou" ICH..JI_CTL. 0.0111. out~ICH..JI_CTL. ",,~CIIJ ...,.~CIIJIoOIFDI
RTB..DNA outb ICH.J\_CTL. 010111. ou.~ ICH.J\_CTL ..... aCIIJ-..,.aCIIJ 101021
IITBJlFF~ out~ ICH.J\_CTL. 0.0111. out~ ICH.J\_CTL ..... aCIIJ_,..CIIJIoOIFDI
a •• U n. UAAT _TX....DI..JI out~ ICH..JI_CTL. 0101 I. outb ICH..JI_CTL ...,.b tI J_,.bC I lIoO.FDI
a •• U n. UAAT _TX...EI..JI out~ ICH..JI_CTL. 0101 I. out~ CCH..I_CTL ..... btl l_,.b C13 101021
a •• Un. UAATJlX....DI..JI out~ CCH..JI_CTL. 0101" outbCCH..JI_CTL • ..,.bC Il-..,.b [111001E71
a •• Un. ~RT.JU...EI..JI outbCCH..JI_CTL. 0.01" outbICH..JI_CTL ..... btl l-..,.btll 101101
ad.Un. IIEIIET_TX_INT ou'bICH..JI_CTL.01281
ad.Un. EOI..JI274 outbICH.J\_CTL.01381 1* 1274 in' h IR3 on B0130 *1
ad.Un* EDIJlDI3O..I274 outb101EO.01601
.d.fln. EDIJlDI30_TII'IER ou'b IDlED. 0,621
a•• Un.
a •• Un.
a•• Un.
Enabl._Ua,.t_In" I
(
int
CJ
'* ,. ••
d the 80130 int''I",..~pt . , •• 1"list." *1
autbeO,Ea. OIOOFE II: c), /* .,.it. to the BOI30 int.,. ... upt ••• k ,..gllt." *1
c • inbCOxE:!),
Dhab Io_U... '_In" I
(
int
CI
C •
lnlt (OxE2),
outbl0lE2. 010001 leI.
Enabl._Tim,,. _lnt()
(
int
CI
outb 101EA. 1251.
autlt (OlEA, 0.00),
•• nd_fla. - FALSE.
'*
Till.,. 1 int'''T'upt. eveT''' .
la, •• c
*1
e - inb COIE2"
1* ... ad tho B0130 Inh,.,.upt . . . k .... ilh~ *1
outbl0lE2. OIOOF. . . e" 1* ..,.Ito h tho B0130 into,.,.upt muk .... ilh~ *1
231421-48
1-229
' I ' , ,-
AP·2~5
IPCO/UBR/CHUCIVCBRC/IIN'. C
Dlsa_ie_Tloon _IntI I
(
int
c.
c • tnb (OIEa)J
ouU 101G. 010004 I e I,
Cole)
ch.,.
CJ
whll. I Iln_ICHJI_CTLI .41 •• 0 I,
ouU ICHJI.JlAT. e I,
CIII
<
..hll. I (In_ICHJI_CTLI •
~.tu~nlln_ICHJI.JlAT)
II •• 0
.0.7F"
),
ent, pact)
ch.,.
.p ••• '
unsigned eh.,.
ent, .pact,
R•• d(p ••••
unsilned ch.,.
Ii
ch.,.
c, bu.t200l.
II • e • 0, Ie !. CRI . . Ie !- LFI •• II
e • CIII .0.7F,
If Ie . . BS II c.-DELI
If (I > 01 (
fo~
<
1981.
I (
--I,
ColBSI, CoISP" ColBSI,
el ••
If Ie >- BP)
Coech
bull i++l •
.110/I'
CJ
«c •• CR) If (c •• L.F»
<
bu'[t++] • CRJ
buft 1++1 - LFi
)
l'
CaCeR),
(I,
,.
CoeL-F»)
tnt)
*p.ct • ent,
el ••
fa,.
• pact - il
(i • 0, i (.pact
. ,••• ++ • buftil.
i++)
231421-49
1·230
inter
AP-235
IPCO/USR/CHUCIVCSRC/UAP. C
unsigned ch.T'
iJ
R•• d (.cbu.tO], BO, "etue1) I
i • Bltp('cbuf[O]),
".tu"n( cbu'[ i]) J
W1'lh(p,ng)
ch."
.p.",
.. hil. (*PIII., !- '\0#) 0(
if (.p • • • • • '\n')
CD(eR),
CoC.p •• g++),
Fetalep ••• )
c
h."
'* .,,It •••••••g.
.plIII."
Writ.C"Fetal:
WfoiteCpm.g),
forC, J),
*'
.. ),
'* .,.1t •••••••
Dug (pmo,)
eft.,.
to the .u' •• n then .top
g. to the .u'•• n then continue *1
.p ••• ,
Writ.C "Iug.
WriteCp"' •• )'
It);
Ascii_To_Ch.",Cc) 1* conv.,.t ASCII-He. to Cha" *1
eh.,.
1:1
- .......
If
«'0' <-
c)
If
«
c)
1"eturn(c
'A'
<-
<<01371.
(e <(0
(0
- ....
l'eturn(c - 01117),
",eturnCOIFF),
".turnee
If « '.'
<-
'9') )
'0'),
c)
'F') )
If') )
Low.,. _Cas. (c)
ch.,.
c.
(
l'
l'
<- c) • • (c <- 'I'»
return (C) J
« 'A' <- c) • • (c <- 'Z'»
l'eturn(c + 0.20),
« '.'
"eturneO),
231421-50
1-231
inter
IPCO/UBR/CHUCK/CSRC/UAP. C
Ch.,,_To.Jt,sci:l.Cc, Ctl) 1* canv.,.t ch.,. to ASCIJ-H • • • /
unsigned eha"
c, chtll
unstgn.d ch.,.
:I..
i • (c Ie G.FO) » 4,
i f I i C 101
ch[O] • t + 0.30,
.1 ••
cheOl • :I. + 0137#
:I. • (c Ie DxOF) ;
i f I i C 101
chtll • :I. + 0.30,
el ••
c~tll
•
I + 0.37.
cheal. '\0',
Sklplp,.. ,1
I. lkip
c::he.,.
*PIIIS.'
tnt
i,
~l.nh
.1
fa,. (:I. • O. . , ••••• ' "
.,..turnC :I.),
R.. d_lntO
I. R•• d • 16
~It
:1.++, p ••• ++) I
Intel.~
.,
(
weI, tIIh, tIIdl, ...hl, JI
:I.,
dan"
h •• I
"OVI",
fa,. (d ani • FALSE. doni - FALSE.
R,,'ClccbufCOl, BO, •• ctu.I),!
I • Sklpl •• ~uftOll.
hovI'"
) (
'0,. Ch • • • dov.,. • hov,,. - FALSE, ...d • III" • 1IIdi • wht • 01
CJ • Asctt_To_Ch.,..Cclluft:l.J» <- le, 1++)
"I >•• TRUE.
+ J;
If IJ
"
9)
bid • wd*10
wh .: IIh*l. + JI
i f I ..d C ..d1l
dav.,. • TRUE.
If Iwh ( .. h1l
hov.,. - TRUE.
IAId1 • wd • ..,hl • wh.
)
'H' II cbuftl] •• 'h' II cbuftll •• CR II
cbufU.l •• LF II cbutt[:I.] . - '
I' (cbutti] •• 'H' II cbutti] . - 'h')
h • • • TRUEJ
1f Ch •••• TRUE •• hov." •• FALSE)
dane. TRUEs
if (cbuft,,] ••
i.
') (
Ch • • • • FALSE •• dav.,. •• FALSE)
don • • TRUE,
231421-51
1·232
intJ
Ap·235
IPCD/USR/CHUCK/CBRC/UN'. C
i f C!do".1
«
nu."e", is too
....writ.C-'"
:1.,.(.,,, Thi.
Ent."
-->
nUIlIt.,.
)
Itil. \" I" It •• to II. le.s than 65536. 'n"),
")I
)
81 ••
""t,.(11
)
111 ••• 1 Ch ....
ct.,.," Ent.,..
a nUllb.,.
->-),
i f Ch •• 1
".tu.,."C ..,,).
1"'etu'f'nCllldh
Int_To-J\scii(yalu......., 141, chi IIItdtlt) , . conv.,.t an int ...... to an ASCII at"inl
unailna" IDnl
valua.
u_sho'l"t
clta...
*'
...... lIIidth,
cht]. Id,
<
i < .. ldU, 1++1
J • valu. X ..... ,
If CJ < 101
chU]· J + 0.30,
81 •• chtil - J + 0137.
valua • valua I ......
f n Ii - 0,
>
fa,.. U • wid'''. - I. ch[t] •• '0' •• i ) 0, i--)
chtil - ld,
>
ch[.ddt"] •
'\0',
W~lh.J..on._IMCd ...
until"ad long
v_ahg,.,
i;
u_sho,.t
ch,.
II
dllt)
J'
ch[lll,
if Idhul
1",_To-".,::U('III. 16.
' "
Int_To.J\sciiCdw. 10,
' "
'chtO], 8),
al ••
'0"
(J • 0, ch[J] !- '\0"
lineti] - chtJ]'
W~U • ..sho,.t_IMI..
u_short ..1iI i i
<
u_slto,,' oJ.
ch.,.
cht61,
un.iln.d long
II. . . In
if 10 . . 1
10),
J++)
II
II,.,
'w.
In'_To..A.cU C
.1 ••
i--.'c"[O].
16, '0', .ch[O],
4)1
231421-52
1-233
IPCD/USR/CHUCK/CSRC/UAP. C
Int_To_Alcltldllh 10, '0', IcchCOl,
'01' (J • O. chCJl ,- '\0'. i--, J++)
:5),
lin.Cil • c:hCJ1J
VesC)
<
cha"
fo~
bJ
(
,)
<
b • R•• d_Cha"()1
if C(b _. 'V') II
.,.etu'rnCTRUE)J
if Ctb •• 'N') II
(b
'\1'»
(b
'n'»
return (FALSE);
Writee" Enter. Y 01" N
II)J
'*
R•• d-"ddr(pmsg, add. tnt)
cha",
-->
pms. - pOinte" to the output m•••• g.
1* .dd - point.,. to the addr ... s *1
1* cnt - numbe" of • ..,t •• in the .dd" •• s
*P.'II' addtl. cnti
foT' (
I
;
)
*'
*'
(
WTiteCp.sg );
R•• d U,cbufCO], SO • • • ctual).
'or (J ·lkipUccbufCO]), i-OJ i <: 2*cn1;:,; j++.
if (C '0' <- cbufCJJ) a.:. (cbuf[J] <- '9'»
=
cbufU]
else
i f « 'A'
cbuftJJ -
<-
.
tbulC Jl) 1.1. (cbuil[J]
- 0,37,
i' « '.' <- tbu,eJ)) .... (cbuHJ]
cbu'Hl1 = cbuf[ Jl - 0,'7,
else <
cbuilt 1]
.1 ••
J++) {
'0',
<-
'F') )
<-
'f'
cbuf[ J]
»
Wrlt.< " Illegal Char.c tel'\n").
bre.k.
If
(1
:>= 2*cnt -
1)
bre.ki
"01"
:a
(i
OJ
1
.dd[(cnt -
<=
1)
tnt - 1i i++)
1] = cbuf[2*il « 4
I:bu'[2*1 + 1J.
IWrit • .-Addr(p.dd. tnt)
ch.r
p.ddtJ. cnt.
i.
for (
J
e[3l.
cnt >0 • tnt--)
<
231421-53
1-234
inter
AP-235
IPCD/UBR/CHUCK/CBRC/UN'. C
t • pad.tent-UI
Cha~ _Ta ...... e tI U.
W~UII.ctOlll
.e tOll I
cCOJ • "n',
ctll •
>
'\0'1
~lhl'C[Olli
RI.v...Dda_lIpfdl
It~uct
FD
It~uet
FR~
It~uet
TaD
RID
It~uet
__ TRUCT
.,'f
•.
_It.gin..,,"',
-"
.,!"lIu',
ch.".
entll
Int
p~bd
p~"
.p .. ' . '
.ptlld.
. '.... d'
•
•
1 .. lteh
(It~uct RID .1 luUdJ't~lpfd->1'bd_aff . . t)1
I.t~uet FR~_STRUCT *1 luUdJ't~lp~bd->buffJt~11
• ~PJ' __ ITl
UJ:
I f l ..anlta~_f1a.1
Ip~"->c.d
ca..
"" •• Iu /* Don't put d.ta 1ft f:lfo unl ••• in t.,."ina1 11041. *1
,,.bu' • (cll.,. .) ,"',.,
, ... bu' .- 3J J* ektp ove" the h •• d.,. in'o and point to the data
ent • 3.
.n
p'd->llnlth - 31
faT' (I p ...... !I 1 ent <
>
p~bd
*'
,NULL,
ent· 0, ,,.bu' • (cha" .) p,.bd->buf'Jt,.H:
• O.03FFFI . . p'd->llnlth > 01
ent++. ,!'bv"++, p'd->lenltlt--) (
IIIhileCr_lIu'_ata' •• FULLh
FI'oJl_ln I.p~bufll
•
I,~bd->.et_.nt
luUd_Pt~(p~bd->linkll
,Ud •• DEBUII
If (,"->lonlth •• 0 ••
p~bd
!. pNULLI
FatalC"Uap. Racv_Data_tep'd)
-)I
'.nd I. I . DEBUO . ,
c...
>
b1"ealu
KID
while «ptl..1 • Qat_TbdO) •• pMA.L),
,tU->aet_cnt • EOFBlT I XlDJ.ENIITHI
lIeop, C(ch ..... ) ptbd-)bu"Jt1' • • • "d_'ram.COl, XIDJ.ENOTH) ,
pUs • Ilt~uct FRAPE_STRUCT .1 ptbd->hff-,t~.
ptf.->cmd - P,.. •• ->cmdJ
ptfs->d •• p - p,.."-)' •• '
I C_RJIITJ
'*
*'
,...tu,.n the ,,. ....
to the •• nd.,.
ptf.-> ••• , - ••• pl
whU.' !S.ndj,..••• 'pt ... , 8UlldJt,..(pfd->.,.C_8dd,.))).
231421-54
1·235
IPCD/UBR/CHUCIVCBRC/UAP. C
1111" •• 11.
ca..
TEST:
fa,. I,,.bd • lat,.uct RBD .) Build..pt,.I,fd-:>,.bd_affut).
, - 1t'I ... nJtbd • ,NULLJ ,'rbd !- ,NULL.
,,.U • BuUd..pt,.lp,.bd-:>1inkll (
..hU. lI,nd • G.t_lbdl II •• ,NULL).
I f I, !a ,NULL)
,-:>link a Df'utlpnd) •
•1,.
beglnJtbd a ,nd.
,tU-:>act_cnt a ,,.U-:>ect_cnt •
.. coPIJ«ch ....
,
,tfa
a
*)
ptbd->buf'J't1'.
(C ....,..) p"bd-:>bu •• ...,pt ... ,
pnd-:>ect_cnt II DI3FFFI.
pnd.
a
lat,.uct FR _ _BTRUCT *1 b.glnJtbd-:>buffJt,..
, ••• ->c.d • P"'.-:>C •• i
,"1->41 •• , • P'I"'.-> ••• P I C-"JUTI
ptf.-> ••• p •
'* ....th ••• nd,.,.
th • •,. •••
./
tU1"n
to
s •• p'
.. hll.1 !S.ndJ,.••• Ib.glnJtbd. 8uild..Pt,.I"d-:>.... _add,.) II.
1t1".all:;
)
Putj1'""J'FACpfd)J
'*
Fi'D_T_Out:()
(
ch....
1* 1'.tu,.n the ."'• • • • /
call.d ... ·'. . sn ,1"01"." *1
el
c • flfa_ttaut_'lfa_t++J.
Di .... l._U.,.'_lntC ),
I. laut_flfa_t - In_,tra_"
1* If the
u ••,tu *1
'_bU'_Ita' • EfGIrV,
atop 'i11lng T".nl.it
D.ICT'ipto". '1
.11.
if the fi.o .... full ."d ts no... d....atninl
l' ('_bu'_ltat •• FULL •• aut_fll'o_t - 80 - 1"_.1'0_t)
1* turn on
tho .pl.at *1
'*
'*
'1,.
lu"'"
*'
RTS_DNB.
'_bu. _Itat • I MUSE.
)
Enabl._Ua.,.'_lnt(
",.tu",n(C)J
Fifo_T_ln(e)
etl."
CJ
)J
I. c.ll.d bU u."t .... C.iV. int.l'"upt *1
fifo_i;:Cln_fifo_t++] • CJ
If It_bu. _at.t •• EMPTVI
231421-55
1-236
inter
AP-235
IPCO/USR/CHUCK/CSRC/UAP. C
.1..
.t."t
'_bu'_s'a' • INUSE, 1*
,tIU,n" n"."I"'!t Buff." D.,c1"1pto," *1
1* l ' the"e ar. on1u ao 10cationl l"t, tu,." off thl .pilot *1
if ('_bu,_,tat INUBE •• 1"_'1"0_' + 20 - Dut_'i'o_') <
RTS_OFFBI
t_bufl _,tat • FULLI
1* called b\l '".n I .. 1 t
Fi fo_R_Out ()
int'''T'upt *1
{
ch.,.
CI
if (out_'i'o_" .- In_'I'o_,,,)
.1..
,.. _bu, _It.t • Ef'tPTV,
i'
1* i'
*'
*'
:1."_'1'0_1")
1* if the ,!flo i , 1.,tV
thl fi'o .... full and , . nOIll d .... inin.
(T'_bu,_,tat •• FUlL •• out_,i'D_T - 81 ,.. _bu' _Itat • INUSEI
",.tU1""(C ))
Fi'D_R_ln(c)
cha"
CJ
'*
called b\l RlcvJ)ata_l ()
'1'D_"[1"_'1'0_,,,++l • CI
Di •• bll_Ua",t..:.,Jnt( ),
i f (r _bu' _.tat -- EI'IPTV)
UART _TX_EI_BI
>
11'1
CoCO»)
,,_bu' _,tat. INUSEI
'* prill' the
*'
int.,.,..upt *1
*'
1* if thl bu",,, i , 'ull. indicat. i t
if (T':.JIU'_st.t -- lNUSE •• in_fifD_" •• out_'i'D_")
r _buf _.tat - FUL.L.I
En.b le_U."t_lnt ()J
Isr _U.,.t()
tnt
char
st.t;
CJ
outb(CHJI_CTL.. 2)1
1* point to RR2 In 8274 *1
.wttchUnb(CH_B_CTL) " OllCH /* r •• d 82704 int."rupt vec:to" .nd •• rvic. it */
cat. UART_TX_B:
if
C... _buf_.t.t
_. EMPTY)
UART_TX_DIJh
RESET_TX_INTI
.1 ••
outb (CH_B_DAT.
br •• k;
Flfo_R_Out ( ) ,
231421-56
1-237
intJ
AP·235
IPCO/USR/CHUCIVCSRC/UAP. C
c...
UARTJlECY~RJI:
autbCCHJI_CTL. II. 1* paint ta RRI in B274 *1
otat - InbCCHJI_CTLI.
autbCCHJI_CTL. 01301.
i f Cotat • 0100101
Wrtte(lI\nPaT'itv E,.,.oT' Detected\""),
If Cotat • 0.00201
WT'itIC"\nOve1'T'un E,..1'o," Detected\"");
If Cotat • 0100401
W,.tteC"\nF,..fllinl E'f''ro1'' Detect:ed\nll)J
br •• k,
c . . . UARTJlECY_B:
c - Inb CCHJI..DATl.
if (h"'_ltat •• TRUE) -(
hl_It.t • FALSE,
1Il1" •• lu
i'
(local_echo)
CoCc).
i.
(c •• eTL C)
'* Fl ••
to
t.,. .. inate
High Sp.ed T,..nllllit mode
*'
'* a
leho the ch.,. back to thl te"mina1. could cau ••
,.,..nlmit Dv.,.,.un if Tx int • .,.,.upt tl Inabled *1
tmstat • -FALSE.
,I ••
Flfa_T_InCcl.
h- •• 11i
cu. EXT_BTAT_INT_B:
.utbCCHJI_CTL. 01101.
b,. •• k,
c ... EXT_STAT_INT..... :
.utbCCH ....._CTL. 01101.
br •• k,
)
EOI_BOI30_B274.
EO I Jl274'
)
X.,,2( )
<
.end_fl • • • TRUE.
DutbCOxEA.
12~);
DutbCOxEA. 0.00).
outb(OxEO, 0.6:2);
'*
Timl,. 1 inte"'1"upt. eve,."
1* EOI 80130 *1
125 •• e
*,
231421-57
1-238
intJ
AP-235
IPCD/UBR/CHUCK/CBRC/UN'. C
Lo.dJ. •• pO
(
in'
RecvJl.'._III.
f.,.C.
J)
(
R•• IfJlid'I"C -',,\nEnt .... thtl .t.tto,,', LSAP 'n ....
i f '!Ad.JI •• p..l\d ...... , ... p. R.c,,_Da'._1I1 (
--> ", •••• p,
1);
."., •• ("\n\nE,.p.'I': LSAP Adel,. ••• mUlt •• on. of the fol10 .. tnl=
.... 1".(·'"
2OH. 4OH, 6OH. SOH. AQH. COH, EOH \n"),
'ft"),
)
LodJlulUc •• t l l
(
fo .. C • • ) (
Add ...... 'n HI. __)on,
"'ult i..l\d." £01. AIIDJ.ENI.
if IC"ultijo.... £OI • 0.011 •• 01
W,.tt.C .. ,"So,.,. ... the LSI 0' the "ultlc •• , Atld,. ••••Ult: , . 1\,,"),
if '!A•• Jlultic . . 'jo....... ' ...ulUjo.... £O]) (
W'I":lt.C-'n\nSo,.,.v. "ultic •• ' Add,. ••• T•• l. i l full !\,,"),
R•• d..Addl"( "'nEnt ... th. Multic •• '
.10. (
)
..,.
....
.1 •• (,
.... ,t.C·'''\nWDuld vau lilt. to add .no.h.,. Multic •• t Atld"' ••• ? .. ),
""tt.c·
(V
if nV•• 1I1
.1'
N)
-->
")I
.. ,..,11.
)
)
R•• ov.JlulUc •• tC I
(
fo .. C ••
I (
R.ld-.Adth'C"\nEnt.,. the Multie •• ' Add" •••
"h.,
",ou ... nt to d.l.t. in HI. __>",
_1"jo.... £OI. AIIDJ.ENII
if (("ulUjod ... £OI • 0.011 •• 0)
W,.tt.C"\,,8.,.,.V' th. LS8 0' till. Multie,.' Addl' ••• IIU.t; .. e l\n"h
.1 . . ( if I !D.l . . .Jlu1tic ••
'~ultijodd .. tOl)1 (
W1'"it;.(·\n\nSD,.I''', t;h.' "ultic •• t Add,. ••• do •• n't; , •• t.I!!\n"h
11", •• 11,
t-".......
)
el •• (
Wrtt.(·\n\nWould ,ou I". ta del.t. enot,..", Multic •• t Add ...... ?ta)1
W1'"iteC" CY .,. N)
'»
-->
")J
If '!V••
11,.•• 11.
)
)
231421-58
1·239
AP-235
IPCD/USR/CHUc:II/CBRC/IMP. C
P,..int./tdd,.. ••••• C)
<
.t:l'uct:
int
..wAT .p . . "
.t.t,
""'1:.("\"
....
Thi. St.t'on. Ho.t: Add.,. ••• is: .. );
ih..Add~( ... bo•• itOl. ADDJ-ENII
..,.:l.t.("\" The Add ...... of the De.tination Node i.: ") •
.... it • ..Add~(Idl.a'..Add~tOl. ADDJ-ENI •
.".,,,.("\" Thi. Station. LaAP Add,. ••• i . "),
W,.i'.J\dd,..C •••• p, 1),
...,.i,e("\" The Add" ••• of the D•• tination LBAP I •. If);
.... ih..Add~l.d . . p. 1).
aht • FALSE.
fo~ IPM' . . . . U01. p ... ' <..... UI1U..TIJ\DDICCNT - 11. pm.H+1
If Ip ....-:>.,., . . lNUBEI <
.t.t • TRUE.
)
Ill"' .... '
If la'."
wrt tee "\n The fallotlling Multic •• ' Add,. ••••••,.. enalllled: ") I
'a~ IpII.' . . . . . U01. PM' <. _UI'IULTJ..ADDR_CNT - 11. pHt++1
I f IPM'-:>.'.' . . lNUBEI <
.... lh..Add~l.p ... '-:>•• d~tOl. ADDJ-ENI.
Write'"
81se
")J
W'riteC"'" The" • •,.. no l'Iultic •• t Add" ••••• enabled. \n"),
If lI.ht • InitJ-1c (II •• PASSEDI
W'l'tt.C·'n\nP••••• Di.gno.tic Self Te.t.\"\,,\,,"),
.1 ••
Ifla'.' •• FAILEDJUAONDBEI
W",iteC"\n\nFailed: aelf ,T •• t Di •• no •• Ca.end\n"),
el ••
Ifla'.' . . FAILEDJ-PBII_INTERNALI
W1"'teC H \n\nFailed. Int.,.n.l LooptJ.cll S.lf T•• t\n-)'
a1.a
,fl.t-t •• FAILEDJ-PBII.J!XTERNALI
W,.lte("\n\nF.l1ad: Exte"n.1 Loopb.cll S.lf Te.t\n").
el ••
IfC.t.t •• FAILEDJ-PBK_TRANBCEIYERI
W"itaC "\n\nF.tlad: Elta"n.l Loopb.cll Tb,.ough T".nlcaiva,. Se1' Ta.t\n")1
Dutb (OlEO. Ox31) I
au'. COlE:!. 01201 I
1.lnlhll .. 80130 pic - ICWI . ,
I . ICW:!
*'
231421-59
1-240
AP;'235
IPCO/UtlR/CHUCK/CSRC/IMP. C
I. ICwa . ,
I. IC ... • ,
I. ICW. . ,
ou."0.E2. 0.101,
au'ltCO.D. 0.001,
au'beOaEa, 0.101,
ou.bco.n. O.FF"
,.
...
..... ..,,
. . . k all int ....... upt. *1
, ,
out .. CO.FFao. 0.00201,
BOil. v •• 'o,.
I. IniUall • • • b. 110130 tl ...... '0" T..... ln.l "ode
ou.b CO.EE.
outbCO.a.
ouuco.a.
ouUCO.EE.
outbCO.EA.
aut;ItCO.EA,
0.34"
0 ••11,
0.0.1, , . avlTlCK ••• fa,. 1 ••• e .,
0.701,
1251,
0.00)1 , . Ti •• 1' 1 int • .,."upt. IV."', . 121 •• e
*'
, . IniUaU • • •b. 1274 . ,
ou.bICH...._CTL. 0.10" ouUICH...._CTL. 0128" ou.bCCH_B_CTL. 0.301,
ou.b ICH.JI_CTL. 0.3811
outbICH...._CTL. 21, o"tbICH...._CTL . . . . bl2l • Oal41,
outbCCH...._CTL. 11, o".bICH...._CTL . . . . blU • Oal51,
outbICH...._CTL. 'I, outbICH...._CTL. . . . btlll .01EAli
Wort 'eC
1I',,'"'"\"\"',,'n\n\"\"\"',,-)
J
......................................................'"");
W'I"i tiC
"',,'"',,\n\"\"'n-) I
W'I"it.Cw..iteC"
WriteCIl
• _
IEEE 1102.2/_.3 COMp.tibl. D.t. Link D,.iv.,. .'n"I,
.......................................................'n .. )J
dh • • • FALSE •
• onito'l" _.1., • TRUEJ
R•• dJ'dd'l"C"\n\nEnt.,. the A.d,. ••• of the D•• tinatiaft Noda 1n H••
--> ",
..D•• t.JIdd,.I01. ADD.-LENI.
Lo.d.-L"p I I,
R•• d..Add,.CIt\n\nEnt.,. the D.,tinatlon NOd.'. LSAP in HI.
--> " . •d •• p.
1).
W,.:t.t.C"\n\nDo tjou _n' to Load an" Multica.t Add"' ••••• ? ev or N) __ >"),
If IV. . I))
Lo •• .../IulUe •• te I,
Pr I nt.JIddr . . . . . II,
Int
'l'a__cnt. lIuf_ent'
stl'uct
cha ...
TID
.pUd.
.plluf,
"'I'
"b.gin..!'tbd,
CJ
Writ.e"\n Would IOU like tb. 10e.l echo on? (V CIT' N)_-:>N)J
l'CV •• C»)
231421-60
1·241
intJ
AP~235
IPCO/USR/CHUCK/CSRC/UAP. C
local_echo. TRUE;
el ••
local_echo. FAL.SE,
Writ.C n ," Thi. ,rag" •• wl11 now ente" the ter,.!n.1 mod •. '"'nil),
Wrl t. ("'" Pre •• ""C then CR to ,..turn bae k to the menu\"\n") I
out_'ifo_t III t"_fifo_' • out_'iflo_l" • 1"_'1'0_T' • 01
t_bu' _.tat - EMPTY, ,. _bu' _.tat • EMPTY,
EOI_BOl30_8274.
Enable_U.,.t_Jn't< JI
Enab Ie_Tilt.,. _Int (),
monitor _.la, • FALSE)
tmstat • TRUE;
wh He (toM' tat)
fCIT" (',.. ....e_,nt • 0,
f"ame_tnt
whil. «ptbd - Qat_TbdC»
pbu", -
(ch.,.
*>
<
MAX_FRAPlE_SIZEJ
11.. ptbd) (
•• pNULL);
ptbd->buf'-ptri
1* gat . . . .,1t buff." '1"011 the
data linll *1
1* paint to the buffe" *1
bu'_ent • 0;
if ('"alRa_ent •• 0) ( 1* if this i . the 'll'.t buf'e",
he.d.,. information *1
begin-ptbd -
.pbu'++
.pbu'++
*pbu'++
bu._cnt
add on I£EE 802.2
ptbd;
• d •• pi
• • • • pl
• UIJ
• 3;
,-)link. Off •• t(ptbd); 1* i. this i.n't the first buff.r
link the prevlou. buffe" with the n.w on. *1
1* fl11 up • d.t. h,nk 1III,it buffer '''0 ••• vnc transmIt fifo *1
bu. _tnt < TBUF _SIZE ..... rame_tnt < I1AX...FRAHE_SIZE.
buf _cnt++, pbu'++, flT.fAW_cnt.+) {
i ' (f".me_tnt I . 0 II• • • nd_flag)
.lse
'0' ( ;
bre.lfJ
while U_bu._stat == EMPTY);
/* ..... I t untll fifo h •• data *1
if « c . *pbuf - Fifo_T_Dut(» •• CR) (
++buf _cnt ; ++pbu'J ++f"am._cntJ
b,. ••• ,
}
!: bu._cnt < TBUF_SIZE II s.nd_flag) { 1* last buffer in lIst *1
ptbd->act_cnt - bu._cnt I EOFBIT;
if (c == CR
send_flag ... FALSE,
br •• lfl
}
wh 11. ( I Send_F,.alle (beg l"_ptbd. .De.t_Add,,(01»;
1* k Ie, trving unt:l1
successf!ul */
231421-61
1-242
inter
AP-235
IPCD/UBR/CHUCK/CBRC/UAP. C
DIo.b Io_U... t_lnt C"
Di •• bl,_Ti ••,. _lnt(),
..O":l.tol'_'I • • • TRUE,
.lulldJ...... Ctnt)
.'rutt
TID
u_Illo ... t
ent,
u_.hort
• t"Utt TID
.pbu',
I • 0.20, ,,. ... I_ent.
#0,. ( ,
'I'•••_cnt.
*,......
bu'_ent,
• p.ltd,
c ... ,.
:I. •
1n-P1; ....
01
, II. • ,tit.) (
...hil. «ptbd • Oet_TltdC)
-
pNU..L),
,bu' • (ch.,. . , ptbd->buflf-Pt....
bu._ent • 0.
if (,,. ••,_cnt •• 0) "
'*
b.gin ..... tU • ptbdl
.,bu'+• • d •• p,
"0.
1* •• 10 • • • it buff .....
data linll
*'
the
*'
1* ,oint to th. bu.f.r
l ' thtl 'I thl 'h".t bu'f.,., add on IEEE 802
h ........ in'O"r".ation
*'
Q
.,bu'++ •••• "
.,bu'++ =- UII
>
bu._ent - 31
el.1
,-)11nll. Dff •• tCptbd',
1* i ' this tln't thl
"".t
bu,fe,.
*1
linll thl p,.,viaus bu'f.,. IIIlt" the nl.., on.
'*'a .. f:l.11 bu'_tnt
up • data link ••
buf'er lIit" ASCII eh.,..ctl ... *1
< TBUF_SIZE ... tnt> O.
tt
1
CI
i++,
*pbuf •
>
buf _ent++. ,bu'++, cnt--, f", ...e_cnt++)
<
Ii
.f C. > 0.7E)
1 c O.1F;
if (ent •• 0) ( 1* l.st buff.,. in lIst *1
ptbd->act_cnt • bu' _cnt I EOFIIT,
b,. ••••
stT"uet
cnt. 1.
*8uiIdJT" •• e( ) • •ptbd.
•• It.
U_.hD",t
TBD
W,.it.(" Do 1J0u ... nt thl • • t.tion to t",.n'.lt? (V DI' N)
l'
--> "),
(Ves())
231421-62
1-243
intJ
AP-235
IPCO/UIIR/CHUCK/CBRC/UAP. C
fo,. 1.1ft" • FALSE.
.MIt -
FALSE.
I
<
W'I't.'.C"'n Ent." thl nva'e ... o. data b"t •• 'n thl '"a..1 --> ">cn' • Read_Jnt ( ) J
if lent> 204111
"""tl
8o,""". tltl nu.b ........ to bl 1••• than 20•• "nil") ,
eM,"
II ••
•a' t
• TRUE,
11, • • • :I.t • FALSE,
..,.1 •• ("\" Hit an" ... " to I . i t Monitor Modi. 'n\n"),
• F,.0'••••
Qaad
• of Qaod
F,. ••••
WrU.I" Tuns.itted
Writ.l"
.... it:.("
Rlcliv"n") I
Ov • .,.,.un\n" ).
E",.o,..\n lf ) ,
R... ived
..........
I. ·01234l167B'P01234l1678901234l167B901234l167B901234l167B'P012345.7B901234l167S901234l167B
.. •••• 111.1
••••••••25
.1 ••••••
11
I •••
33
••••
44
..111
••••
57
71 *1
fa,. It • o. i < 79. 1++1
IlnetlJ • 0.20.
Ilnot791 • CR.
1in,Caol • ~'O#,
.. hU. I ItnbICHJI_CT\..I .. 11 •• 01
'0,. U • 0, t < 72, t++)
1i notil • 0120.
<
Write...Lonl_Jntllaad_••"_ent. 11"
2')j
W!-tt'~Dn._Jnt(,..cv_f ...... _cnt,
WTtt.-.sho1't_JntCscb. C,"C_I1'''"
W'I'ltIJlho1't_lntClcb .•
.".t.t'Jiho1"t_lntClclt.
In_,,,,,•.
",C_I,." •.
33>1
44),
57),'
W1'ttl_Sho,.'_Int(ecb.ov,,_e1'''51 11"
W,.itel"Un.tOI I.
if 1 ...!.tI <
ptbd • BulldJ,.••• lentl.
whU.I !S.ndJ..... lptbd . . .D.. t....Add,.tOI II •
• ',..uc'
T&D
*,tbdi
..,.ite("\n Hit .nUl 'e, \:0 •• it High Speed 1".n •• it "ode. \n\n"),
h5_st., • TRUE;
EOI_BOl30_B274.
En.bl._U.... t_lnt(
)J
1* E •• cute this lDop until. ,..cv ch." int.,."upt: ".,p.nds .t U.... t
*'
231421-63
1·244
AP-235
IPCO/USR/CHUCK/CBRC/UAP. C
",htl. (hI_stat)
«
'* •• d.'.
8et_Tltd(») •• pN\A.L)j
t • I.it buf'.,. '1"011
the
link *1
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231421-64
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231421-65
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231421-67
1-248
inter
AP-235
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00- 015
DATA BUS
00-07
82501
LOOPBACK
82530 CONTROL SIGNALS
CONFIGURATION
PORT
292010-7
I I
'U
•
.....
~
""
Ap·274
from the two chips are connected to an OR-gate to
generate a system ALE. Multiplexed address data lines
ADO-ADI5 and address lines A15-A19 of the two
chips are also connected line by line correspondingly.
3.0 ETHERNETICHEAPERNET NODE
DESIGN
Details on LAN High Integration Board (LANHIB)
design are presented in this section. The LANHIB is an
82586/80186 shared bus board and can be configured
to Ethernet or Cheapernet. The 82586 is used in minimum mode to reduce chip count.
3.2 82586 Address Latch Interface
Figure 6 shows the timing of the address signals with
respect to the ALE signal. The ALE of the 82586 is
OR-ed with the ALE of the 80186 and the result is
connected to the latch enable inputs of Octal Transceiver Latches. The latches transfer the input data to the
output as long as the latch enable is high, and captures
the input data into the latch when the latch enable goes
low. In this timing diagram, the setup and hold times of
the input data (82586 address) required by the address
latch can be verified. Estimating 7 ns of propagation
delay in the 74S32, the setup time is T38 + 7, which is
32 ns at 8 MHz. The hold time for Al9 is shorter than
the other address lines because it is valid only during
Tl. The hold time for the Al9 is T4 - T36 - 7, which
is 3 ns. The hold time for the other address lines is T39
- 7, which is 38 ns. In this design, a 74F373 was chosen to latch address lines A16-A19 and two 74LS373s
were used to latch address lines ADO-AD15. Required
setup and hold times of the 74F and 74LS 373s are
summerized in Table 2.
.
the reader is advised to refer to the 80186, 82586,
82501, and 82502 data sheets. Basic understanding of
the 80186 microprocessor is assumed. Figure 5 shows
the block diagram of the LANHIB. Schematics are in
Appendix A.
3.1 82586 (Min Mode) Interface to the
80186
T.he 82586 can be placed in minimum mode by strappmg the MN/MX pin to Vee. In the minimum mode,
the c~directiLProvides all bus control signals-ALE,
RD, WR, DT/R, and DEN, saving the 8288 Bus Controller. The 80186, which is the only other bus master
on the shared bus, also generates these bus control signals directly. The HOLDs and HLDAs of these two
chips are connected together so that only one of the two
bus masters can exclusively drive the bus at a time under the HOLD/HLDA protocol. Except for the ALE,
all bus signals including address and data lines float
when the chip does not have control of the bus. In this
design example, RDs, WRs, DT/R and DEN from the
two chips are connected together respectively. ALEs
Note that address lines A16-A18 and BHE of the
82586 are not really needed to be latched. These lines
stay valid for an entire memory cycle.
VALID BHE. A16-A18. A20-A23
VALID A19
VALID 56
VAlLO AO-A15
T29
0-55".
------- ~
0-45"0
r----
T30
0-5Ons
AL E
T35
o-45ns
T39
I-
45"0 MIN
r
ORED ALE
DELAY IN OR GATE
f--- ~;~o MIN
~
~
0@250C
5ETUP TIME FOR
74F373 AND 74L5373
I
HOLD TIME FOR
74F373 AND 74L5373
Figure 6. 82586 Address Timing
1-262
292010-8
AP-274
Table 2. 74F and 74LS Data Setup and Hold Time Specifications at 25°C
74LS373
74F373
Min
Data Setup Time
Data Hold Time
Nom
Nom
Min
Max
Unit
Max
2..1-
5..1-
ns
3..1-
20..1-
ns
3.3 80186 Address Latch Interface
The address latch used by the 82586 is shared by the
80186. Figure 7 shows the 80186 address line timing
with respect to the ALE. Again estimating 7 ns delay in
the 74S32, the setup time for the latch is TAVAL + 7
and the hold time is TLLAX - 7. These are 37 ns and
23 ns respectively at 8 MHz. Comparing to the required
values shown in Table 2, it is quite obvious that the
setup and hold times of the latch are met by wide margins. Note that the 80186's address lines A16-A18 and
BHE are not valid for an entire memory cycle; therefore, they have to be latched.
3.4 82586 Memory Interface
The 74LS373 has a delay of 18 ns for input data to
reach the output assuming the latch enable is high. A
,
I
---'
TeLAV
5-55ns
demultiplexed valid address (output of the address
latch), therefore, becomes available after T29 + 18
measuring from the beginning of Tl (Figure 8). The
demultiplexed address remains valid until the ALE of
the next memory access becomes active. Upper address
lines, AI4 through A20, are connected to a 16L8 PAL,
which provides address decode logic for all memory
devices. The PAL truth table is in Appendix A. The
PAL has a maximum of 35 ns propagation delay, so
chip selects will become active after 55 + 18 + 35 ns
(max.) from the beginning of Tl as indicated in Figure
8. Since address decode logic is implemented by a PAL,
any memory expansion would only require a reprogramming of this PAL.
Two 74LS245 bus transceiver chips are controlled by
the DT/R: and DEN. Output enable and disable times
of the 74LS245 are 40 and 25 ns respectively. The maximum propagation delay when the output enable is active is 12 ns.
,
T1
I
T2
I
'\..._...I,""--L.J
I
I
I
TeLAX
10ns MIN
I
I
T3
VALID BHE,A1S-A191
VALID AO-A15
Te HLH
35nsMAX
TLHLL
90ns MIN
,
--
ALE
TLLAX
30ns MIN
~ TAVAL
30ns MIN
I
ORED ALE
DELAY I N OR GATE
s@25oe
9n
SETUP TIME fOR
74f373 AND 74LS373
HOLD TIME fOR
74f373 AND 74LS373
292010-9
Figure 7. 80186 Address Timing
1·263
AP-274
T1
T4
--'
I
'",_ _oJ
-
_
,
T2
I
'''' _ _..J
DELAY IN
74LS373
T3
I
,
T4
I
,
T1
I
VALID AO-A19 FROt.l ADDRESS LATCH
I-
T29
0-55 ns
I
.
~
CHIP SELECT FROt.l PAL
PAL DECODER
DELAY :: 35 ns
"I'------------------------~
I--- 20 nT:
I-- T9
t.lIN--
10ns t.lIN
DATA INTO 82586
T40
0-95ns
READ
CYCLE
RD
T42 200 ns t.lIN
FROt.l 82586
T41
T4.4_
1-,0-70 ns-1-- 85 nst.lIN
T22
o-60ns
T22
o-60ns
DT/R
I,T23
1
0-70ns
-
--
I
T24
o-65ns
I
\
DEN
rl
I
r--
131
0-55ns
T32
Ons t.lIN
DATA OUT OF 82586
T23
0-70ns
WRITE
CYCLE
ViR
FROt.l 82586
T45 210ns t.lIN -
I'
\
-
oT:~5n s
292010-10
Figure 8. 82586 Memory Interface Timing
1-264
Ap·274
,
--'
,
T1
-
I
I
T3
T4
I
',--_....,jl
t
TDVCL ~
_2_0_n_S_M_IN_ _--I~
DATA INTO
TCLRL
10-70ns
8~
TCLDX
10 ns MIN
.----
TRLRH 200 ns MIN
FROM 80186
TCLRH
10-55 ns
TCHCTV
I
_~
I
10-55ns
r----J
DT/R
TCVCTV
10-70ns
TRHAV _
85 nsMIN
TCHCTV
10-55ns
f--TCVDEX
10-70 ns
I
\
DEN
I-
TCLDO~I
TCLDV
10044ns
10ns MIN
~
DATA OUT OF 80186
TCVCTV
10-70ns
WRITE
CYCLE
_I.
TWLWH 210ns M I N -
I
\
WR FROM 80186
~
I- TCVCTV~
o
TCVCTX
5-5 5 ns
70_n_S~L___________________
_______
I_l_0__
DEN
I
PAL DECODER
DELAY:::: 35 ns
h
RD
T1
VALID AO-A 19 FROM ADDRESS LATCH
\.
CHIP SELECT FROM PAL
READ
CYCLE
,
DELAY IN
i--74LS373
r- t:I
TCLAV
S-55ns
,
T2
TCVCTX
.5-55ns
,292010-11
Figure 9. 80186 Memory Interface Timing
1-265
intJ
AP-274
Address access time is 3 X Tl - T29 - 18 - T8 12 + n X Tl, where n is the number of wait states. For
o wait states operation at 8 MHz, it is 270 ns minimum.
Chip select access time is 3 X Tl - T29 - 18 - T8
- 12 + n X Tl - 35, which is 235 ns for 0 wait state
operation. Command access time for a read cycle is 2 X
Tl - T40 - T8 - 12 + n X Tl, which is 123 ns.
Address setup time for a write cycle is Tl - T29 - 18
+ T23, which is 52 ns minimum.
OFFFFF
~,..,..,.~,...,.
OFFFFF ,..,...,...,...,...,...,..,
OFCOOO f-'~-'-"'-';.....q
OF7FFF
To meet these timing requirements, 2764-20s must be
used for ROM. Static RAM chips, HM6264P-15, offer
very wide timing margins and were selected for this
design.
....,...,.....,....,...,.....,-1
OF4000 .............4-'..........
OFOOOO f-'~-'-"'-''-'I
3.5 80186 Memory Interface
Figure 9 shows the timing of the 80186 memory interface. By comparing this figure to Figure 7, it is easy to
notice that the 80186 offers a little faster bus interface.
For example, TCLRL which is equivalent to T40 (0 to
95 ns) of the 82586 is specified as 10 to 70 ns. Since the
memory choice satisfies the 82586 memory timing parameters, it also satisfies the 80186 memory timing parameters.
3.6 Memory Map
3FFF
3FFF ......,....,....,...,....,....
292010-12
Figure 10. LANHIB Memory Map
3.7.4 82501 LOOPBACK CONFIGURATION
PORT
With 2764-20 EPROMs and 6264P-15 SRAMs, this
board has 32 K bytes of ROM space and 16 K bytes of
RAM space. Memory map is given in Figure 10. If
27128-20 EPROMs are used, the ROM space becomes
64 K bytes.
3.7 80186110 Interface
3.7.1 82586 CHANNEL ATTENTION
GENERATION
A 74LS74 D-type flip flop was used for this port. On
power up, it configures the 82501 to Non-Loopback
mode by providing a high level to pin 3 (LOOPBACK).
The chip select is~erated from the 80186's PCS2 and
the sychronized WR command of the 82530 interface.
The least significant bit of I/O output data becomes the
state of the 82501's pin 3.
3.7.5 ON-BOARD INDIVIDUAL ADDRESS PORT
The active low Peripheral Chip Select 0 (PCSO) was
used to generate a channel attention (CA) signal to the
82586. This way of CA generation satisfies the requirement that the width of a CA which must be wider than
a clock period of the system clock.
3.7.282586 HARDWARE RESET PORT
peSl of the 80186 will reset the 82586 if any I/O command is executed using this I/O chip select.
3.7.3 82530 INTERFACE
82530 interface to the 80186 was derived from the design example presented in the 82530 SCC-80186 Interface Ap Brief. This document is attached to this Ap
Note as Appendix C.
To provide the 82586 a hardware configured host address, a 32x8 ROM is connected to the bus. The chip
select for this ROM is generated from the 80186's
PCS3, so that the address for the ROM is mapped into
the I/O space. Six or two (IEEE 802,.3 specified address
lengths) consecutive I/O reads starting from the lowest
address of ROM will transfer the board address stored
in the ROM to an lA-Setup command block of the
82586.
3.8 82586 Ready Signal Generation
82586 asynchronous ready (ARDY) signal is generated
from a shift register. The shift register provides the
82586 a "normally ready" signal. When a wait state is
needed, the ready signal is dropped to the low state. As
shown in Table 3, the 82586 can be programmed to
have 0 to 8 wait states by setting the DIP switch properly. Even though the on-board memory devices are
1-266
inter
Ap·274
(IOBASE2) requires the isolation means to withstand
500V ac, rms for one minute. Ethernet (IOBASE5) requires 250 Vrms. This electrical isolation is normally
accomplished by transformer coupling of each signal
pair. The kind of transformers recommended for the
82502 are the pulse transformers which have a I: I tum
ratio and at least 50 microhenry inductance. PE64102
and PE64107 manufactured by Pulse Engineering are
found to be good selections for this purpose. The PE
64102 offers 500 Vrms isolation. The PE64107 offers
2000 Vrms isolation. Both products provide three
transformers in one package. Even though the current
Type IOBASE5 specification requires only 250 Vrms, it
is very common to have a higher isolation, at least 500
Vrms, in transceivers.
Table 3. DIP Switch Settings for Various
Numbers of 82586 Walt States
Dip Switch Setting
7
6
1
1
1
1
1
1
1
1
0
1 1
1 1
1 1
1 1
1 1
1 1
1 0
0 0
0 0
Switch
Switch
1 =
o=
5 4
3
210
Number of Walt States
the 82586 Inserts
1 1 1 1 1
1 1 1 1 0
1 1 1 0 0
1 1 o 0 0
1 0 o 0 0
0 0 o 0 0
0 0 o 0 0
0 0 o 0 0
0 0 o 0 0
Open
Closed
0
1
2
3
4
5
6
7
8
fast enough for 0 wait states operation, this program·
mabie wait state capability was added so that the effect
of wait states on the 82586 performance could be evaluated.
3.9 82501 Circuits
Since the 82501 is designed to work with the 82586, no
interfacing circuits are required.
The transceiver cable side of the 8250 I requires some
passive components. The receive and collision differential inputs must be terminated by 78.0. ± 5% resistors.
Common mode voltages on these differential inputs are
established internally. 240.0. ± 5% pull down resistors
must be connected on the TRMT and TRMT output
pins.
A 0.022 fLF ± 10% capacitor connected between pin I
and 2 of the 82501 is for the analog phase-locked loop.
Connected between the XI and X2 pins is a 20 MHz
parallel resonant quartz crystal (antiresonant with 20
pF load fundamental mode). An internal divide-by-two
counter generates the 10 MHz clock. Since both Ethernet and Cheapernet tolerate an error of only ± 0.0 1%
in bit rate, a high quality crystal is recommended. The
accuracy of a crystal should be equal to or better than
± 0.002% @ 25°C and ± 0.005% for 0- 70°C, A
30-35 pF capacitor is connected from each crystal pin
(XI and X2) to ground in order to adjust effective capacitance load for the crystal, which should be about
20 pF including stray capacitance.
3.10 82502 Circuits
3.10.1 ISOLATION AND POWER
REQUIREMENTS
The IEEE 802.3 standard requires an electrical isolation within the transceiver (MAU). Cheapernet
The standard specifies the voltage input level and maximum current allowed on the power pair of the transceiver cable. The voltage level may be between
+ 11.28V dc and + 15.75V dc. The maximum current
is limited to 500 rnA. Since the 82502 requires + IOV
± 10% and + 5V ± 10% as power, there has to be a
DC/DC converter. In addition the DC/DC converter
must be isolated due to the requirement described
above. The DCIDC converter should be able to supply
about 100 rnA on the + IOV line and 60 rnA on the 5V
line. The efficiency required in the converter is, therefore, «lIV X 100 rnA + 5.5V X 60 rnA) / «(I1.28V
- 0.5A X 4.0.) X 500 rnA)} X 100 = 31% worst
case. 4.0. is the maximum round trip resistance the power pair may have. 82502's CMOS process is the major
contributor to this low DCIDC efficiency requirement.
Since the DC/DC converter has an isolation transformer inside, the output voltages are all floating voltages.
The OV output of the converter, for example, has no
voltage relationship with the DTE's ground. The Vss
and A Vss pins of the 82502 should be connected to the
OV output of the DC/DC converter which is the
82502's ground (reference voltage).
Both Pulse Engineering and Reliability Incorporated
produce DC/DC converters that meet the 82502's requirements. The Pulse Engineering's part number is
PE64369 (enclosed in this design kit). The device measures about 1.5" x 1.5" x 0.5" and provides 2000 Vrms
breakdown. The Reliability's part number is
2EI2RIO-S. Preliminary data sheets are available from
Reliability.
3.10.2 OTHER PASSIVE AND ACTIVE DEVICES
FOR THE 82502
A 78.0. ± 5% resistor is required to terminate the transmit pair of the Transceiver cable. The chip has an internal circuit that establishes a common mode voltage,
thus no voltage divider is required. The receive and
collision pair drivers need pull up resistors. A 43.2
± I % resistor must be connected from each output pin
to + 5V.
1-267
AP·274
A 243.0 ± 0.5% precision resistor is required on the
REXT pin to the ground. The accuracy of this resistor
is very important since this resistor is a part of current
and voltage reference, circuits in the analog sections of
the 82502.
Grounding the HBD (Heartbeat Disable) pin will allow
the chip to perform Signal Quality Error check (Heartbeat) as required by the IEEE 802.3. The chip will
transmit the collision presence signal after each transmission during Interframe Spacing (IPS) time. In a repeater application, this feature is disabled (HBD =
among other MAUs on the coaxial cable." It is recommending a transceiver design that minimizes the probability of total network failure. The fusible resistor will
provide an open circuit in an event of exCess'current. A
short circuit from the CXRD pin to ground will not
bring down the network due to the blown fuse.
A 1 M.o resistor connected between the coaxial cable
shield and the Transceiver cable shield will provide a
static discharge path. The Ethernet coaxial cable
should also have an effective earth ground at one point
in a network as required by the standard. A 0.01 ,...F in
parallel to the 1 M.o resistor provides ground for RF
signals.
+5V).
Diodes connected on the CXTD pin are to reduce the
capacitive loading onto the coaxial cable. One diode is
sufficient, but two will provide a protection in case one
burns, out (Short Circuit). The diode should have about
2 pF shunt capacitance at Vd = OV and be able to
handle at least 100 rnA when biased in forward direction. A few candidates are IN5282, IN3600, and
IN4150.
3.10.3 LAYOUT CONSIDERATION FOR THE
82502 CIRCUITS
A 100.0 fusible resistor connected on the CXRD pin is
purely for protection. It is there as a fuse, not as a
resistor. The 82502 works Without this resistor. The
IEEE 802.3, however, states that "component failures
within the MAU (Media Attachment Unit 'or Transceiver) electronics should not prevent communication
It is strongly recommended that the board have a special ground plane for the 82502 (see Figure 11). The OV
(reference) output of the isolated DC/DC converter
should be connected to the ground plane. The Vss and
AVss pins of the 82502 should be counected to the
ground plane with minimum lead wires.
There should be a 0.22 ,...F capacitor connected between
the coaxial cable shield and ground. The signal path
from the coax. shield through the 0.22 ,...F capacitor to
GROUND PLANE FOR 82502
+12V
OV
ISOLATED
DC/DC
CONVERTER
-IN
+10V I---+-_~
+5Vr---.....
oVI---+.
292010-13
Figure 11. Ground Plane for the 82502
1-268
inter
Ap·274
the ground should be kept as short as possible-leads of
the 0.22 fJ-F capacitor should be as short as possible.
The path length from the CXTD pin through two diodes to the center conductor of the coax should also be
minimized.
These are recommendations which will produce a more
reliable circuit iffollowed carefully. Remember that the
82502 has analog circuits in it.
4.0 DEMONSTRATION SOFTWARE
The demonstration software included in this Ap Note is
called "Traffic Simulator and Monitor Station"
(TSMS) program. The TSMS program is written in
PL/M and has the following features:
I. Programmable network load generation
2. Network statistical monitoring capabilities
3. Interactive command execution of all 82586 commands
4. Interactive buffer monitoring
The environment created with the TSMS program was
found to be very useful for network debugging and other individual station's hardware and software debugging. The TSMS software listing is found in Appendix
B.
NOTE:
The 82586 Date Link Driver presented in AP Note
235 also runs on the LANHIB. Please refer to the Ap
Note for detailed operations of the software.
4.1 Programming PROMs to Run the
TSMS Program
By returning the card enclosed in this kit or by contacting Insite, the TSMS program and related batch files
can be obtained on a diskette. TSMS related files· that
are on the diskette are:
READ. ME
TSMS.PLM
IO.PLM
INI186.PLM
LANHIB.BAT
SBC.BAT
IUPHIB.BAT
IUPSBC.BAT
HI.BYT
LO.BYT
ROM.BAT
batch file ROM.BAT invokes the Intel PROM Programming Software (iPPS) under the DOS operation
system and programs two 2764 EPROMs. The Intel,
Universal Programmer must be placed in ON-LINE
mode.
Other files contained in the diskette are for compiling
and locating the original TSMS program. Using these
files, the original TSMS program can be changed or can
be compiled for an iSBC 186/51. 'TSMS.PLM' is the
original TSMS source program. 'IO.PLM' contains the
10 driver needed when the TSMS program is run on
the iSBC 186/51. INI186.PLM is the LANHIB initialization routine. LANHIB.BAT is the batch file that
compiles, links, and locates the TSMS program and the
LANHIB initialization routine. SBC.BAT compiles,
links, and locates the TSMS program and the 10 driver
for the iSBC 186/51. IUPHIB.BAT programs two
2764s for the LANHIB. IUPSBC.BAT programs two
2764s for the iSBC 186/51.
Therefore, if the TSMS program is to be run on the
LANHIB (Demo board), steps required are:
1. C: > LANHIB
2. C: > IUPHIB
If the TSMS program is to be run on the iSBC 186/51,
steps required are:
1. C:>SBC
2. C: > IUPSBC
4.2 Capabilities and Limits of the
TSMS Program
The TSMS program initializes the LANHIB Ethernet/
Cheapernet station by executing 82586~s Diagnose,
Configure, lA-Setup, and MC-Setup commands. The
program asks a series of questions in order to set up a
linked list of these 82586 commands. After initialization is completed, the program automatically starts the
82586's Receive Unit (monitoring capability). Transmissions are optional (traffic simulation capability).
The TSMS program has two modes of operation: Continuous mode and Interactive Command Execution
mode. The program automatically gets into the Continuous mode after initialization. The' Interactive Command Execution mode can be entered from the Contin~
uous mode. Once entered in the Continuous mode, the
software uses the format shown in Figure 12 to display
information. Detailed description of each of these fields
is as follows:
The READ.ME file contains instructions for programming PROMs. HI.BYT and LO.BYT are the files
which can be downloaded to PROMs directly. These
files are already configured for the LANHIB. The
Host Address: host (station) address used in the most
recently prepared lA-Setup command. The software
simply writes the address stored in the lA-Setup command block with its least significant bit being in the
most right position. Note that if the lA-Setup com-
1-269
inter
AP-274
**************************** station confiquration ************************
Host Address: 00 AA 00 00 18 60
Multicast Address(es): Nb Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Lenqth: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load qenerated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
82586 Confiquration Block: 08 00 26 00 60 00 F2 00 00
40
***************************** Station Activities **************************
of
1/
Good
Frames
Transmitted
10130
1/ of Good
Frames
Received.
o
CRC
Errors
Aliqnment
Errors
o
o
No
Resource
Errors
o
Receive
Overrun
Errors
o
292010-14
Figure 12. Continuous Mode Display
mand was just set up and not executed, the address
displayed in this field may not be the address stored in
the 82586.
Multicast Address(es): multicast addresses used in the
most recently prepared MC-Setup command. As in the
case of host address. the software simply writes the addresses stored in the MC-Setup command block. Note
that if the MC-Setup command was just set up and not
executed, the addresses displayed in this field may not
be the addresses stored in the 82586.
Destination Address: destination address stored in the
transmit command block if AL-LOC=O. If
AL-LOC= I. destination address is picked up from the
transmit buffer. The least significant bit is in the most
right position.
Frame Length: transmit frame byte count including
destination address. sourCe address. length, data, and
CRC field.
Time Interval Between Transmit Frames: approximate
time interval obtainable between transmit frames (Figure 13). The number is correct if there are no other
stations transmitting on the network.
Network Percent Load Generated by This Station:
approximate network percent load that is generated by
this statkm (Figure 13). The number is correct if there
are no other stations transmitting on the network.
Transmit Frame Terminal Count: number of frames
this station will transmit before it stops network traffic
load generation. If this station is transmitting indefinitely, this field will be 'Not Defined'.
82586 Configuration Block: configuration parameters
used in the most· recently prepared Configure command. As in the case of lA-Setup command, the soft-
ware simply writes the parameters from the Configure
command block. The least significant byte (FIFO Limit) of the configuration parameters is printed in the
most left position.
# of Good Frames Transmitted: number of good
frames transmitted. This is a snap shot of the 32-bit
transmit frame counter. It is incremented only when
both C and OK bits of the transmit command status are
set after an execution. The counter is 32-bit wide.
# of Good Frames Received: number of good frames
received. This is a snap shot of the 32-bit receive frame
counter. It is incremented only when both C and OK
bits of a receive frame descriptor status are set after a
reception. The counter is 32-bit wide.
CRC Errors: number of frames that had a CRC error.
This is a snap shot of the 16-bit CRC counter maintained by the 82586 in the SCB.
Alignment Errors: number of frames that had an alignment error. This is a snap shot of the 16-bit alignment
counter maintained by the 82586 in the SCB.
No Resource Errors: number of frames that had a no
resource error. This is a snap shot of the 16-bit no resource counter maintained by the 82586 in the SCB.
Receive Overrun Errors: number of frames that had a
receive overrun error. This is a snap shot of the 16-bit
receive overrun error counter maintained by the 82586
in the SCB.
If the station is actively transmitting. # of good frames
transmitted should be incrementing. If the station is
actively receiving frames, # of good frames received
should be incrementing. In this continuous mode, a
user can see the activities of the network.
1-270
AP-274
)
1-
TIME FOR ONE FRAME TRANSMISSION (X)
(
PREAMBLE, DA, SA, LENGTH, DATA, CRC
j
..
)
TIME BElWEENI
FRAMES (Y)
.
L-l~-"
292010-15
Network Percent Load = _X_
X+Y
Figure 13. Network Percent Load
Hitting any key on the keyboard while the program is
running in the Continuous mode will exit the mode.
The program will respond with a message 'Enter Com'. In this Interactive Command (H for Help) mand Execution mode, a user can set up anyone of the
82586 action commands and/or execute anyone of the
82586 SCB control commands. Setting up a Dump
command and executing a SCB Command Unit Start
command will, for example, execute the Dump command. Display commands are also available to see the
contents of the 82586's data structure blocks. A display
command will enable a user to see the contents of the
82586's dump (see Section 6.3).
Typing 'E' after 'Enter command (H for help) "
executing a SCB Command Unit Start command with a
transmit command, or executing a SCB Receive Unit
Start command will exit the Interactive Command Execution mode. The program will be back in the Continuous mode. Using this Interactive Command Execution
mode, one can, for example, reconfigure the station and
come back to the Continuous mode. Section 6 lists actual example executions of the TSMS program.
The TSMS program should be run in an 8 MHz system.
The software running at 8 MHz with a maximum of 2
wait states has been tested and verified to be able to
receive back-to-back frames separated by 9.6 microseconds and still keep track of the correct number of
frames received. This capability, for example, can be
used to find out exactly how many frames a new station
in the network had transmitted.
The software does not perform extensive loopback tests
and hardware diagnostics during the initialization. A
loopback operation can be performed interactively in
the Interactive Command Execution mode.
The software allows a user to set up only 8 multicast
addresses maximum. It is not possible with this program to set up more than 8 multicast addresses.
The command chaining feature of the 82586 is not used
in the Interactive Command Execution mode. Each
command setup performed by a'S' command after 'En'sets up a command
ter command (H for help) with its EL bit set, I bit reset, and S bit reset. Diagnose,
Configure, lA-Setup, and MC-Setup commands are
chained together during the initialization routine and
executed at once with only one CA.
The software sets up 5 Receive Frame Descriptors
linked in a circular list. Therefore, a user can see only
the last 5 frames the station has received. It also sets up
5 receive buffers, each being 1514 bytes long, linked in
circle. Therefore, the 82586 never goes into the NO
RESOURCES state.
4.3 Example Executions of the TSMS
Program
This section presents three example executions of the
TSMS program. When the TSMS program needs a
'.
command to be typed, it asks a question with' 'is what a user needs to type in on
Anything after' the keyboard. To switch from the continuous mode to
the interactive command execution mode, type any key
on the keyboard.
4.3.1 EXAMPLE 1: EXTERNAL LOOPBACK
EXECUTION
In this example, 500 external loopback transmissions
and receptions are executed (Figure 14). In order for
the software to process each loopback properly, a large
delay was given between transmissions.
4.3.2 EXAMPLE 2: FRAME RECEPTION IN
PROMISCUOUS MODE
The 82586 is configured to receive any frame that exists
in the network (Figure 15). In this example, the station
received 100 frames.
4.3.3 EXAMPLE 3: 35.7% NETWORK TRAFFIC
LOAD GENERATION
The station is programmed to transmit 118 byte long
frames with a time interval of 159.4 microseconds in
between (Figure 16). The network load is about 35.7
percent if no other stations are transmitting in the network.
A key was hit to enter the Interactive Command Execution mode. In that mode, a Dump command was
executed and the result was displayed. After the Dump
execution, a transmit command was set up again and
the station was put in the Continuous mode.
1-271
inter
AP-274
Traffic Simulator and Monitor Station Program
Initialization begun
Configure command is set up for default values.
Do you want to change any bytes? (Y or N) ==> Y
Enter byte number (1 - 11) ==> 4
Enter byte 4 (4H) ==> A6H
Any more bytes? (Y or N) =-> Y
Enter byte number (1 - 11) am> 11
Enter byte 11 (BH) -=> 6
Any more bytes? (Y or N) _a> N
Configure the 5S6 with the prewired board address ==> N
Enter this station's address in Hex _a> 000000002200
You can enter up tos Multicast. Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N =_> Y
Enter a destination address in Hex _m> 000000002200
._>
Enter TYPE
0
How many bytes of transmit data?
Enter a number
2
Transmit Data is continuous numbers (0, 1, 2, 3, .•• )
Change any data bytes? (Y or N) -=> N
Enter a delay count _a> 10000000000
The number is too big.
It has to be less than or equal to 65535 (FFFFH).
Enter a number -=> 60000
-->
Setup a transmit terminal count? (Y or N)
Enter a transmit terminal count ==> 500
==> Y
Destination Address: 00 00 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 30.1S mi1iseconds
Network Percent Load generated by this station:
.0 %
Transmit Frame Terminal Count: 500
Good enough? (Y or N)
=-> Y
Receive Unit is active.
292010-16
Figure 14. External Loopback Execution
1-272
inter
AP-274
---Transmit Command Block---
0000 at 033E
8004
FFFF
034E
2200
0000
0000
0000
Hit to countinue
transmission started!
**************************** Station Configuration *************************
Host Address: 00 00 00 00 22 00
Multicast Address(es): No Multicast Addresses Defined
Destination Address: 00 00 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 30.18 miliseconds
Network Percent Load generated by this station:
.0 %
Transmit Frame Terminal Count: 500
82586 Configuration Block: 08 00 A6 00 60 00 F2 00
00
06
***************************** Station Activities ***************************
# of Good
Frames
Transmitted
500
# of Good
Frames
Received
500
CRC
Errors
Alignment
Errors
0
0
No
Resource
Errors
0
Receive
Overrun
Errors
0
292010-17
Figure 14. External Loopback Execution (Continued)
1-273
Ap·274
Traffic Simulator and Monitor Station Program
Initialization begun
Configure command is set up for default values.
Do you want to change any bytes? (Y or N) ==> Y
Enter byte number (1 - ll) s=> 9
Enter byte 9 (9H)
1
Any more bytes? (Y or N) ==> N
Configure the 586 with the prewired board address ==> Y
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es}.
-->
Would you like to transmit?
Enter a Y or N ==> N
Receive Unit is active.
**************************** station Configuration ************************
Host Address: 00 AA 00 00 18 60
Multicast Address(es}: No Multicast Addresses Defined
82586 Configuration Block: 08 00 26 00 60 00 F2
01
00
40
***************************** station Activities **************************
# of Good
Frames
Transmitted
# of Good
CRC
Frames
Errors
Received
o
100
0
Enter command (H for help) ==> 0
Alignment
Errors
o
Command Block or Receive Area? (R or C)
Frame Descriptors:
4000 at 036C AOOO at 0382 AOOO at 0398
0000
0000
0000
0382
0398
03AE
03DA
03E4
03EE
2200
2200
2200
2200
2200
2200
0000
0000
0000
No
Resource
Errors
o
==>
Receive
OVerrun
Errors
o
R
AOOO at 03AE
0000
03C4
03F8
2200
2200
0000
AOOO at 03C4
0000
036C
0402
2200
2200
0000
292010-18
Figure 15. Frame Reception in Promiscuous Mode
1-274
intJ
0000
0000
0000
0000
AP-274
0000
0000
0000
0000
0000
0000
0000
0000
Receive Buffer Descriptors:
C064 at 030A C064 at 03E4 C064 at 03EE
03F8
03EE
03E4
OFEO
09F6
040C
0000
0000
0000
050C
050C
050C
0000
0000
0000
0000
0000
0000
0000
0000
C064 at 03F8
0402
15CA
0000
050C
C064 at 0402
030A
IBB4
0000
050C
Display the receive buffers? (Y or N) .... > Y
Receive Buffers:
Receive Buffer 0
002C:014C 00 01
002C:015C 10 11
002C:016C 20 21
002C:017C 30 31
002C:018C 40 41
002C:019C 50 51
002C:OIAC 60 61
:
02
12
22
32
42
52
62
03
13
23
33
43
53
63
04
14
24
34
44
54
05
15
25
35
45
55
06
16
26
36
46
56
07
17
27
37
47
57
08
18
28
38
48
58
09
19
29
39
49
59
OA
IA
2A
3A
4A
5A
OB
IB
2B
3B
4B
5B
OC
lC
2C
3C
4C
5C
00
10
20
3D
40
50
OE
lE
2E
3E
4E
5E
OF
IF
2F
3F
4F
5F
03
13
23
33
43
53
63
04
14
24
34
44
54
05
15
25
35
45
55
06
16
26
36
46
56
07
17
27
37
47
57
08
18
28
38
48
58
09
19
29
39
49
59
OA
lA
2A
3A
4A
5A
OB
1B
2B
3B
4B
5B
OC
1C
2C
3C
4C
5C
00
10
20
3D
40
50
OE
lE
2E
3E
4E
5E
OF
1F
2F
3F
4F
5F
03
13
23
33
43
53
63
04
14
24
34
44
54
05
15
25
35
45
55
06
16
26
36
46
56
07
17
27
37
47
57
08
18
28
38
48
58
09
19
29
39
49
59
OA
1A
2A
3A
4A
5A
OB
1B
2B
3B
4B
5B
OC
1C
2C
3C
4C
5C
00
10
20
3D
40
50
OE
1E
2E
3E
4E
5E
OF
1F
2F
3F
4F
5F
03
13
23
33
43
53
63
04
14
24
34
44
54
05
15
25
35
45
55
06
16
26
36
46
56
07
17
27
37
47
57
08
18
28
38
48
58
09
19
29
39
49
59
OA
1A
2A
3A
4A
5A
OB
1B
2B
3B
4B
5B
OC
1C
2C
3C
4C
5C
00
];0
20
3D
40
50
OE
1E
2E
3E
4E
5E
OF
1F .
2F
3F
4F
5F
Hit to countinue
Receive Buffer 1
002C:0736 00 01
002C:0746 10 11
002C:0756 20 21
002C:0766 30 31
002C:0776 40 41
002C:0786 50 51
002C:0796 60 61
:
02
12
22
32
42
52
62
Hit to countinue
Receive Buffer 2
002C:0020 00 01
002C:0030 10 11
002C:0040 20 21
002C:0050 30 31
002C:0060 40 41
002C:0070 50 51
002C:0080 60 61
:
02
12
22
32
42
52
62
Hit to countinue
Receive Buffer 3
002C:130A 00 01
002C:131A 10 11
002C:132A 20 21
002C:133A 30 31
002C:134A 40 41
002C:135A 50 51
002C:136A 60 61
:
02
12
22
32
42
52
62
Hit to countinue
292010-19
Figure 15. Frame Reception in Promiscuous Mode (Continued)
1-275
AP·274
Receive Buffer 4
002C:18F4 00 01
002C:1904 10 11
002C:1914 20 21
002C:1924 30 31
002C:1934 40 41
002C:1944 50 51
002C:1954 60 61
02
12
22
32
42
52
62
03
13
23
33
43
53
63
04
14
24
34
44
54
05
15
25
35
45
55
06
16
26
36
46
56
07
17
27
37
47
08
18
28
38
48
58
p7
09
19
29
39
49
59.
OA
lA
2A
3A
4A
SA
OB
IB
2B
3B
4B
5B
00
10
20
3D
40
50
OC
lC
2C
3C
4C
5C
OE
IE
2E
3E
4E
5E
OF
IF
2F
3F
4F
SF
Hit to countinue
Enter cODlllland (H for help) ==> E
****************************
station Cofiguration
*************************
Host Address: 00 . AA 00 00 18 60
Multicast Address(es): No Multicast Addresses Defined
82586 configuration Block: 08 00 26 00 60 00 F2
*****************************
# of Good
# of Good
Frames
Translllitted
Frallles
Received
100
o
station Activities
CRC
Errors
Alignment
Errors
o
o
01
00
40
**************************
No
Resource
Errors
o
Receive
OVerrun
Errors
o
292010-20
Figure 15. Frame Reception In Promiscuous Mode (Continued)
1-276
intJ
AP·274
Traffic Simulator and Monitor Station Program
Initialization begun
Configure command is set up for default values.
Do you want to change any bytes? (Y or N) --> N
Configure the 586 with the prewired board address --> Y
You can enter up to 8 MUlticast Addresses.
Would you like to enter a MUlticast Address? (Y or N) --> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N --> Y
Enter a destination address in Hex --> FFFFFFFFFFFF
Enter TYPE -=> 0
How many bytes of transmit data?
Enter a number --> 100
Transmit Data is continuous numbers (0, 1, 2, 3, ••• )
Change any data bytes? (Y or N)
N
-->
Enter a delay count --> 0
setup a transmit terminal count? (Y or N) ==> N
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 ,
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N) -=> Y
Receive unit is active.
---Transmit Command Block--0000 at 033E
8004
FFFF
034E
FFFF
FFFF
FFFF
0000
Hit to countinue
292010-21
Figure 16.35.7% Network Load Generation
1-277
AP-274
transmission started I
**************************** station Configuration ************************
Host Address: 00 AA 00 00 18 60
Multicast Address(es): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 15.9.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
82586 Configuration Block: 08 00 26 00 60 00 F2 00 00
40
***************************** station Activities **************************
Alignment
Errors
# of Good
# of Good
CRC
Frames
Frames
Errors
Transmitted Received
10459
0
0
Enter command (H for help) ==> H
o
No
Resource
Errors
o
Receive
OVerrun
Errors
o
Commands are:
Setup CB
S
o - Display RFD/CB
Print SCB
P
C - SCB Control CMD
ESI Loopback On
N - ESI Loopback Off
L
A Toggle Number Base
Clear Tx Frame Counter
Z
Clear RX Frame Counter
Y
Exit to Continuous Mode
E
----
Enter command (H for help) ==> S
Enter command block type
Command block type:
N - Nop
I C - Configure
MT - Transmit
R o - Diagnose
S H - Print this message
(H for help) ==> H
IA Setup
MA setup
TOR
Dump status
Enter command block type (H for help) ==> S
Enter command (H for help) ==> C
Do you want to enter any SCB commands? (Y or N) ==> Y
Enter CUC ==> 1
Enter RES bit ==> 0
Enter RUC ==>.0
Issued Channel Attention
Enter command (H for help) ==> 0
292010-22
Figure 16. 35.7% Network Load Generation (Continued)
1-278
inter
Ap·274
Command Block or Receive Area? (R or C) =-> C
---Dump status Command Block--AOOO at 0364
8006
FFFF
27D6
Dump Status Results
at 27D6
00 E8 3F 26 08 60
AA 00 40 20 00 00
62 63 3F BO 00 00
00 00 00 00 00 00
DC 05 00 00 OC 04
82 03 6C 03 F8 03
06 80 FF FF 64 03
00 00 D6 27 00 01
20 00 40 06 30 01
00 00 6A 03 OE 00
00 00 00 00 00 CO
00
00
00
00
DC
64
00
00
00
6C
00
FA
00
00
00
05
80
00
28
00
28
00
00
FF
00
00
E4
D6
D2
00
90
00
00
00
FF
00
00
03
27
02
00
00
00
00
40
FF
00
00
DA
E8
00
00
10
74
FF
FF
00
00
03
21
00
00
01
03
6D
B5
FF
70
DA
FF
00
30
00
00
18
9E
85
03
03
FF
00
26
00
00
00
EE
08
06
78
4E
00
00
6C
00
00
CF
FC
00
05
03
00
00
03
00
Enter command (H for help) ==> S
Enter command block type (H for help) ==> T
Enter a destination address in Hex -=> FFFFFFFFFFFF
Enter TYPE -=> 0
How many bytes of transmit data?
Enter a number -=> 100
Transmit Data is continuous numbers (0, 1, 2, 3, ••• )
Change any data bytes? (Y or N) --> N
Enter a delay count -=> 0
setup a transmit terminal count? (Y or N)
-->
N
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Perc,ent Load generated by this station: 35.7 ,
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N) --> Y
Enter command (H for help) _a> C
Do you want to enter any SCB commands? (Y or N)
Enter CUC ==> 1
Enter RES bit·-=> 0
Enter RUC .... > 0
Issued Channel Attention
=->
Y.
292010-23
Figure 16. 35.7% Network Load Generation (Continued)
1-279
inter
AP-274
**************************** Station configuration
~***********************
Host Address: 00 AA 00 00 18 6D
Multicast Address(es): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 ,
Transmit Frame Terminal Count: Not Defined
82586 Configuration Block: 08 00 26 00 60 00 F2 00 00
40
***************************** station Activities **************************
11 of Good
Frames
Transmitted
106020
11 of Good
Frames
Received
o
CRe
Errors
Alignment
Errors
o
o
No
Resource
Errors
o
Receive
Overrun
Errors
o
292010-24
Figure 16. 35.70/0 Network Load Generation (Continued)
5.0 IN CASE OF DIFFICULTY
This section presents methods of troubleshooting ("debugging") a LANHIB board. When a LANHIB board
is powered up with the TSMS program stored in
EPROMs, it should display "TRAFFIC SIMULATOR AND MONITOR STATION PROGRAM"
message on a terminal screen. If the message is not
displayed, the board has to be debugged. Section 5.1
describes basic 80186/82586 system troubleshooting
procedures. Section 5.2 is for troubleshooting 82501
and 82502 circuits. After the 80186/82586 system is
debugged, the 82501/82502 circuits have to be tested.
and the other debugs the 80186/82586 system. The
waveform of the TRXCB output of the 82530 determines which path to be taken. If the 82530 is getting
programmed properly, there should be 153.6 KHz
(1/f = 6.51 ""s) clock on this output pin. If there is a
clock, the problem is probably in the RS-232 interface.
If there is no clock, then the system has to be debugged
using a logic analyzer.
5.2 Troubleshooting 82501/82502
Circuits
If the TSMS program runs on the LANHIB but the
82586 is not able to transmit or receive, there must be a
problem in 82501/82502 circuits. The flow chart in
Figure 19 will guide troubleshooting in these circuits.
An oscilloscope is required.
5.1 Troubleshooting 80186/82586
System
Shown in Figure 17 is a flow chart for troubleshooting
80186/82586 system. The procedure requires an oscilloscope. A logic analyzer is needed if problems appear
to be serious. The procedures will debug the board to
the point where the 82530 is initialized properly. If the
82530 can be initialized properly, ROM and RAM interfaces must be functioning. Board initialization routines (INI186.PLM) linked to the TSMS program requires ROM and RAM accesses. Since the 82586
shares most of the system with the 80186, no special
debugging is required for the 82586. Wiring of all
82586 parallel signal pins should, however, be checked.
The flow chart branches to two major paths after the
first decision box. One path debugs the RS-232 channel
The board should be configured to Cheapernet and disconnected from the network. Two terminators will be
required to terminate a "T" BNC connector providing
an effective load resistance of 250 to the 82502.
The 82586 must have the system and transmit clocks
running upon reset. Since the transmit clock is generated by the 82501, the 82501 transmit clock output pin
(pin 16) should be checked. The TSMS program executes 82586's Diagnose, Configure, lA-Setup, and MCSetup commands during initialization. If the 82586 has
active CRS (Carrier Sense) signal, it cannot complete
execution of these commands. The 82501 should, therefore, be checked if it is generating inactive CRS signal
to the 82586 after power up. The LANHIB powers up
the 82501 in non-loopback mode.
1-280
intJ
AP-274
After making sure that the 82501 is generating proper
signals to the 82586, the TSMS program is restarted
with an initialization shown in Figure 20. The 82586 is
configured to EXT-LPBK= I, TONO-CRS= I, and
MIN-FRM-LEN = 6. The chip is also loaded with a
destination address identical to the source address. If
there are no problems in the 82501/82502 circuits, the
station will be receiving its own transmitted frames. If
problems exist, the station will only be transmitting.
Since the 82586 is configured to TONO-CRS (Transmission On NO Carrier Sense), the chip will keep trans-
(
mitting regardless of the state of carrier sense. The
82501/82502 circuits can then be probed with an oscilloscope at the locations indicated in Figure 21. Probing
will catch problems like wiring mistakes, missing load
resistors, etc.
Once the station is debugged, it can be connected to the
network. If there is a problem in the network, the
82586's TDR command can be used to find the location
and nature of the problem.
)
START
~
-
YES
IS "TRAFFIC SIMULATOR AND NO
MONITOR STATION PROGRAM"
MESSAGE ON CRT?
(HAVE AN OSCILLOSCOPE READY)
(
START DEMO
)
CHECK CLOCK WAVEFORM ON THE
TRXCB PIN(PIN 26) OF THE 82530
~ USING AN OSCILLOSCOPE.
NO
IS IT 153.6KHz(l/f=6.51 ~sec.)
SQUARE WAVE?
CHECK RS-232 DRIVER &
RECEIVER CHIPS. ARE THEY
CONNECTED 'PROPERLY? NOTE
THATTHE 1488(75188)
REQUIRES +12V & -12V AND
THAT THE 1489(75189)
REQUIRES ONLY +5V.
~
CHECK RS-232 DCE & DTE
CONNECTIONS. THE lANHIB IS
A DCE AND AN ASCII TERMINAL
IS A DTE. ONLY PIN2(TXD).
3(RXD). AND 7(GROUND) ARE
USED.
~
CHECK CONFIGURATION OF THE
ASCII TERMINAL BAUD RATE
SHOULD BE SET TO 9600.
ALSO 8 BITS/CHAR. NO PARITY.
AND 2 STOP BITS/CHAR.
~
(
START DEMO
(A LOGIC ANALYZER
MAY 8E REQUIRED.)
CHECK CLOCK WAVEFORM ON THE
FOLLOWING PINS:
1. ClKOUT PIN(PIN 56) OF 80186
THIS SHOULD 'BE 8 MHz 50% DUTY
CYCLE MOS CLOCK.
2. CLK PIN(PIN 32) OF 82586.
THIS CLOCK IS PROVIDED BY 80186.
3. ClK PIN(PIN 20) OF 82530.
THIS SHOULD BE 4MHz CLOCK.
-!
CHECK SIGNAL lEVELS OF THE FOLLOWING
80186 INPUT PINS.
1. RES PIN(PIN 24) SHOULD BE HIGH
AFTER POWER UP RESET.
2. NMI PIN(PIN 46) SHOULD BE lOW.
3. SRDY PIN(PIN 49) SHOULD BE HIGH.
4. ARDY PIN(PIN 55) SHOULD BE HIGH.
5. HOLD PIN(PIN 50) SHOULD BE LOW.
82586 IS NOT INITIALIZED YET.
~
)
292010-25
Figure 17. Flowchart for 80186/82586 System Troubleshooting
1-281
IWrW_r
"'eII
AP-274
CONNECT A LOGIC ANALYZER ON THE
MULTIPLEXED BUS.
1. f'ONNECT AD15-ADD, ALE, RD, WR, ROMHI
ROMLO, RAMHI, RAMLO, AND CS PIN(PIN 33)
or 82530.
r:1
2. USE CLKOUT or 80186 TO CLOCK THE
LOGIC ANALYZER. SAMPLE DATA ON RISING
EDGES.
3. TRIGGER THE LOGIC ANALYZER ON ALE
BECOMING HIGH.
'i'
CHECK RS-232 DRIVER I'<
RECEIVER CHIPS. ARE THEY
CONNECTED PROPERLY? NOTE
THAT THE 1488(75188)
REQUIRES +,12V I'< -12V AND
THAT THE 1489(75189)
REQUIRES ONLY +5V.
SHOWN IN rlGURE 18 IS AN EXAMPLE or A
LOGIC ANALYZER TRACE. COMPARE WHAT'S
OBTAINED TO THE ONE IN rlGURE 18.
Ir DlrrERENT, POSSIBLE PROBLEMS ARE:
1. HIGH BYTE EPROM AND LOW BYTE EPROM
ARE SWAPPED.
2. ADDRESS/DATA LINES ARE NOT CONNECTED
PROPERLY.
3. ADDRESS DECODE PAL IS NOT PROGRAMMED
PROPERLY.
J.
CHECK RS-232 DCE I'< DTE
CONNECTIONS. THE LANHIB IS
A DCE AND AN ASCII TERMINAL
IS A DTE. ONLY PIN2(TXD),
3(RXD), AND 7(GROUND) ARE
USED.
etc.
+
CHECK Ir 82530 IS GETIING INITIALIZED PROPERLY
ON THE LOGIC ANALYZER. TRY OTHER LOGIC
ANALYZER TRIGGERING EVENT, e.g. CS PIN(PIN 33)
or 82530 BECOMING LOW.
MAKE SURE THERE IS 153.6KHz(1/f=6.51 J.'sec.)
SQUARE WAVE ON TRXCB(PIN 26) or 82530.
CHECK CONrlGURATION or THE
ASCII TERMINAL. BAUD RATE
SHOULD BE SET TO 9600.
ALSO 8 BITS/CHAR, NO PARITY,
ANO 2 STOP BITS/CHAR •
(
•
START DEMO
)
292010-26
292010-27
Figure 17. Flowchart for 80186/82586 System Troubleshooting (Continued)
1-282
AP-274
, - - - - - - - - AD15-ADO
,-------ALE
, . - - - - - - RD#
,-....,
jjj
lr~
g~~: 1
~~:~~~
m= "",.,,"""
~L=
(PIN 33) OF 82530
0097 00 41 01001111
009800 41 01001111
0099 00 41 01101111
TRIG 0041 11101111 · .... LOGIC ANALYZER IS TRIGGERED ON ALE = HI.
0101 FF FO 01001111 · .... 80186 JUMPS TO fFFOH AFTER RESET.
010206 EA 00101111 · .... JMP INSTRUCTION (DIRECT INTERSEGMENT)
010306 EA 00101111
SEGMENT OFFSET 0006H
010406 EA 00101111
SEGMENT SELECTOR FFCOH
010506 EA 00101111
(80186 INSERTS 3 WAIT STATES BEFORE
010606 EA 00101111
UMCS REGISTER IS PROGRAMMED.)
010706 EA 11101111
0108 FF F2 01101111
0109 CO 40 00101111
0110 CO 00 00101111
0111 CO 00 00101111
0112 CO 00 00101111
0113 CO 00 00101111
0114 CO 00 11101111
0115 FF F4 01101111
0116 FF Ff 00101111
0117 ff ff 00101111
0118 ff ff 00101111
0119 ff ff 00101111
0120 fF ff 00101111
0121 ff ff 11101111
0122 Ff f601101111
012300 4000101111
012400 00 00101111
0125 00 00 00101111
0126 00 00 00101111
0127000000101111
012800 00 11101111
0129 fC 06 01101111 ..... JUMPED TO fC06H
0130 2E fA 00101111
0131 2E fA 00101111
0132 2E fA 00101111
0133 2E FA 00101111
0134 2E fA 00101111
0135 2E fA 11101111
0136 fC 08 01101111
0137 16 8E 00101111
0138 16 8E 00101111
=
=
Figure 18. Example of Logic Analyzer Trace
1-283
292010-28
inter
AP-274
(
START
)
l
DISCONNECT COAX. PUT TERMINATORS ON
BOTH ENDS OF' "T" CONNECTOR. MAKE SURE
THE BOARD IS CONF'IGURED TO CHEAPERNET.
UPON POWER UP, DOES
82501 GENERATE:
r -_ _ _ _.;;YE;;.;S~
1. 10MHz hC AND RxC
TO 82586?
2. INACTIVE
RUN TSMS PROGRAM.
TO 82586?
J
I
...N~O;;...._..,
ews
~
WHEN A TRANSMISSION IS
~ ATIEMPTED, DOES THE TSMS
PROGRAM DISPLAY "NO
CARRIER SENSE" MESSAGE?
POWER DOWN AND RESTART TSMS PROGRAM
WITH 82586 CONF'IGURED
TO:
1. EXT-LPBK 1
2. TONO-CRS 1
3. MIN-F'RM-LEN 6
EXECUTE LOOPBACKS BY
USING DESTINATION ADDR
SAME AS SOURCE ADDR.
TRANSMIT ONLY A FEW
DATA BYTES.
82501/82502 CIRCUITS
MUST BE WORKING O.K.
IF' THE STATION IS STILL
NOT RECEIVING, CHECK
STATION'S DESTINATION
AND SOURCE ADDRESSES,
CONF'IGURATION OF' 82586.
=
=
..!:!2.-
=
I
MAKE SURE THE 82501 IS
POWERED UP IN NONLOOPBACK MODE.
I
AN EXAMPLE EXECUTION
IS SHOWN IN F'IGURE 20 •
....-_ _..L-_ _-,
IF' THE STATION IS NOT
RECEIVING WHILE IT'S
TRANSMITIlNG, THERE IS
A PROBLEM. PROBE
SIGNALS AT LOCATIONS
SHOWN IN F'IGURE 21.
IT'S PROBABLY A WIRING
PROBLEM.
I
(
BOARD SHOULD BE FUNCTIONAL.
)
292010-29
Figure 19. Flowchart for 82501/82502 Circuits Troubleshooting
1-284
AP-274
Traffic Simulator and Monitor Station Program
Initialization begun
configure command is set up for default values.
Do you want to change any bytes? (Y or N) _a> Y
Enter byte number (1 - 11) _a> 4
Enter byte 4 (4H) _a> A6H
Any more bytes? (Y or N) _a> Y
Enter byte number (1 - 11) _a> 9
Enter byte 9 (9H) _a> 08H
Any more bytes? (Y or N) _a> Y
Enter byte number (1 - 11) _a> 11
Enter byte 11 (BH) _a> 6
Any more bytes? (Y or N) _a> N
Configure the 586 with the prewired board address _a> N
Enter this station's address in Hex _a> 000000002200
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N _a> Y
Enter a destination address in Hex _a> 000000002200
Enter TYPE _a> 0
HoW many bytes of transmit data?
Enter a number =-> 2
Transmit Data is continuous numbers (0, 1, 2, 3, ••• )
Change any data bytes? (Y or N) _a> N
Enter a delay count _a> 0
setup a transmit terminal count? (Y or N) ==> N
Destination Address: 00 00 00 00 22 00
Frame Length: 20 bytes
Time Intsrval between Transmit Frames: 159.4 seconds
Network Percent Load generated by this station: 11.0 t
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N) _a> Y
292010-77
Figure 20. TSMS Initialization for 82501182502 Circuits Troubleshooting
1-285
l
II
10V
12V
+12V
OV
ISOLATED
POWER
SUPPLY
I
t
5V
T
II
1 MD..l/4W. 750V(MIN)
O.:~F
II
."
-,,~
7
C
c
Cil
...
N
~
TXD
c:r
I ic»
I\)
(Xl
0)
TXC
N
g:
RXD
...
......
~
g:
RXC
it
tn.
26
RTS
240D.
·~II~·
10
~
240D.
8
91
Vss AVss
16
~
Vee AVec
2 TRMT
VDD
3 TRMT
CXTD
78D.
15
25
RCV 4
23
30
V
9 RXD
8 RXC
\\
28
0°
LPBK COMMAND
FROM I/O PORT
NOTE:
Numbers are probing sequence.
82501
ESI
\
78D.
6 CRS
RCV 5
I
0.22pF
·jll~·
i
15 TEN
CLSN
43D. 4
RCV
82502
ETC
CXRD
r-- LPBK
CLSN 11
1
\
78D.
~
·~II~·
"T" CONNECTOR
~
12
100D.
FUSIBLE
1/8W
43D.
]
NC
CLSN
HBD
6 CLSN
~
""
~
43D. 7
43D.
)-
.....
50D.
TERMINATOR
5 RCV
1
12
....... .......
O.22pF
5V
7 COT
Ii~~,
50D.
14
5V
CRS 31
COT
TRMT
16 TXC
82586
N
~
c
27
O.:~F
0.011~
h
1
243D.
0.57-
"i
292010-30
intJ
AP·274
APPENDIX A
LANHIB SCHEMATICS
PARTS LIST
PAL EQUATIONS
DIP SWITCH SETTINGS
WIRE WRAP SERVICES
1-287
PARTS
REFERENCES
Ul
U2
U3,
U4
US
U6,U7
U8
U9
Ule
Ull
U12. U27
U28
U13
U14
U15
U16
U17
U18 U20
U26
U22.
~
ex>
U2:·
U24
U25
U29
ua9
U31
ua2
l
LIST
DESCRIPTION
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
Pulse Transformer Pack
IC
DC/DC ConvQrte,r
IC. 64i<-Blt EPROM
IC
IC. SRAM
Ie, 256-Blt PROM
IC
IC
IC
IC
IC. IM-Jht EPROM U
W
PI - 79
PI-80
POWER SUPPLY COHHECTIONS
THE BOARD REQUIRES +5U. +12U. AND -12u
MULTI BUS POWER PINS FOR THESE VOLTAGES AND
GROUND ARE SHO~N ABOVE
HOTES:
2
EACH IC SHOULD HAVE A e luF CAPACITOR BETWEEN
POWER PIN AND GROUND PIN.
PARTS LIST DOES
NOT INCLUDE DECOUPLIN'G CAPACITORS
MTR
CODE
iHT
HIT
0iD
4
2
1
2
1
1
2
PI-81
§::::
PE
RCD
TI
MANUFACTURE
INTEL CORPORATION
HITACH AMERICA LTD
ORDER BV DESCRIPTJON
SOURCE>
PULSE ENGINEERING
RCD COMPONENTS IHC
TEXAS INSTRUMENTS
LOCATION
SANTA CLARA. CA
SAN JOSE, -CA
SAN DIEGO CA
MANCHESTER, NH
DALLAS, T:<
I
2
1
2
1
292010-78
»
'U
~
.....
~
(
.
)I-
'tI
ro
CD
N
...."""
<0
292010-79
l
[Pl1
;e......»
N
8
.j:o.
~
292010-80
l
_-_
.. .. DATA
(D1S-DB)
ADDRESS
(A14-AU
[P
'II
2764-28
Al
A2
A3
A4
A5
A"
A7
A8
A9
Ala
All
AI2
AU
AI ..
ro,
~
RD
Ie
9
B
7
6
5
4
3
26
2 ..
21
23
2
26
28
22
8
I
2
3
4
5
6
7
8
9
Ie
11
oe
01
02
03
04
05
06
07
UPP
12
AI3
11
12
13
15
I ..
17
IS
19
DB
D9
DIe
Dll
DI2
DI9
DI ..
DI5
Al
A2
A3
A4
A5
A6
A7
A8
A9
Ala
All
AI2
AU
A14
~
(PL4,S]
JIOItIIUS
[P II
B
7
2764-28
e
oe
I
01
2
02
3
03
0 ..
S
05
6
06
7
07
. ..
..
5
11
us
12
13
IS
I ..
17
18
19
D9
DIe
Dll
DI2
D13
DI4
DI5
Al
A2
A3
A4
A5
A6
A7
AS
A9
AI8
All
AI2
A13
AI"
JlOM
3
25 B
2 .. 9
21
18
23 11 upp ~
2
12
26
~13
2e
22
27 I"6iI
UI9
r
~~M U1S
Rii
Ie
B
-
- - - - -----
2764-2e
II e
oe
9
I
01
8
2
02
7
3
03
6
0 ..
5
5
05
4
6
06
3
7
07
26 S
24 9
21
18
23 I I upp
2
12
26
2. ~3
22
27 I"mi
U2a
r
--
""------- ..
..
II
12
13
15
16
17
18
19
De
DI
D2
D3
D"
D5
D6
D7
~
Al
A2
A3
A"
A5
A6
A7
AS
A9
Ale
All
AI2
AI3
AI"
~OMHJ
r
2764-2e
e
oe
01
I
02
2
3
03
0 ..
05
5
06
3
7
07
25 B
2 .. 9
21
Ie
23 11 upp
2
12
26
2e ~3
22
27 151m
U21
Ie
9
8
7
6
5
..
.. .
11
12
13
15
I"
17
18
19
De
DI
D2
D3
D"
D5
D6
D7
~
»
"P
N
...,
....
_---
292010-81
l
ADDRESS
~
(A13-AU
.
+5U
.
'litiS
b,18K
R2.
18k
r
.....
.{,
~
[P1]
D15
D14
R14
A13
HIf62S4P-16
26 82 108 18
2
12 to? 18
D?
D6
D?
D6
A12
All
DIS
D12
12
All
23
21
106 11
lOS 16
8&
D4
DS
04
AUt
D11
. A18
24
104 16
DS
us
8?
?
1&
1&
S
IS
...
loa 13
82
02
a
2
102 12
101 11
Dl
D8
81
De
2
1
1
•
A9
DI8
AS
26
A8
.7
A6
AS
D9
D8
A8
1117
A6
AS
a
8
'7
...
S
1&
S
&.
...
::
::~;
A2
Al
11\2
Al
9
~;
(Dts-Da
TIPlSSeae
Ria
AIS
11
18
DATA
...
A. 14
AS 18
1t2 12
Al II
A8 18
a
A6
,,<4
AS
A2
Al
:.
'P
~
IS '§
U24
1
e
2.
22
1m [P1.S.S]
III! [PLSI
7.32
lliI!lIIi
RD
8••~
u. 8 R
RAItaJS [PI]
292010-82
--
DATA
n
,p
I I
(D7-")
,p 2]
J:lIRIr-rR
1]
74MS."
RESET 'P
1]
I
1"--.-2
II
HRf
148.
13
12
DB?
DB6
DBS
DB ..
DB3
D82
DBI
.B.
II
Ie
9
8
usa
n
I I I I
......
lIIf
ADDRESS
S
ftX9
~
TRf
Timi
I'!D
•
1IW7IIRI"
~
15ft7IIRII
..
~
1IIlV7Imi
..
i\)
~
lEI
lEO
eLK
I I
CONI
III.
1201
TxDB
RxDB
./~
<0
c.l
601
811
3
2
I
1488
-
'111
U29
+SU
~II
\\\,
U2S
S3.CLK
SVS CLK
IN!'I
[P 11
CP Il
r=rrl ~It" ~ }r.L,
12 as::J19
U2S
704AS8''
DRQ.
l
[P 11
TII!AT 'P
1]
I II
I
,
I
I~ rrr·I~.t.
R2S
~
COH2
1-7
IK
1-8
1-7.
1-8.
I
R~21jl
I
R2 ..
IK
R2S
I
18
2.
21
22
23
2 ..
+SU
SK
R22, ~2
SK
'81:1<111
U2S
292010-83
3>
..
"U
J
N
......
inter
AP-274
OPT1OHAL 1tG!lQ (6tJCx16) NORD-NIDE £PJIJH
ADDJIBSS (A16-AU
LA 6 a?
A'& 8
A'"
A,aa
,•
A eal
A
A 2e
A
?
A
2?2'.
,& 0'&
,,..
A' ....
a'.
'2
0'2
,e
8
o,e
tt
Ott
e
?
I
08
•
08 • ?
0?12
0118 D
0 I D..
0816 D
021
2
01
I
'.
!i~
§iM~
u'"z
1m
JIQIBUS
,
Dte
0& 14
II
2&..
A"
...
8
8 2
0112 22 I
,
DATA (DiS-De)
,.
D'.
[PI]
292010-84
Nodule Addr_dec
Title 'LANHIB Address Decode Logic
Intel Corp.
Kiyoshi Nishide
Narch, 1986'
"Declarations
PALl
device
AO. Al4. Al5
A16. A17. Al8
A19. BHE
HLDA. 52
RAMLO. RAMHI
ROMLO. ROMHI
ROM
R104
pin
pin
~.
pin
pin
pin
pin
pin
pin
'P16L8' ;
2. 3;
4. 5. 6;
7,. 8;
9. 11;
18. 17;
19. 12;
13 ;
16 ;
Equations
!ROMHI
!ROMLO
!ROM =
!RAMHI
!RAMLO
A15 a: A16 a: A17 a: A18 a: A19 a: (HLDA # 52) a: R104;
IA15 a: A16 a: A17 a: Al8 a: Al9 a: (HLDA # 52) a: Rl04;
A17 a: A18 a: A19 a: (HLDA # 52) Be !Rl04;
!A14 a: !Al5 a: !A16 a: !A17 a: !A18 Be !A19 a: !BHE a: (HLDA # 52);
= !AO a: !A14 a: !A15 a: !Al6 a: IAl7 a: !A18 Be !Al9 a: (HLDA # 52) ;
=
=
PAL Equations
1-294
inter
AP-274
3. To select the 2764·20 EPROMs or 27210 EPROM:
DIP SWITCH SETTINGS FOR
VARIOUS OPERATIONS
SW3
87654321
"t" indicates ON (Switch is clOsed).
2764·20 EPROMs
27210 EPROM
"0" indicates OFF (Switch is open).
"X" indicates Don't Care.
1. To configure the board to Ethernet or Cheapernet:
SW3
87654321
4. Dip Switch Setting Examples:
SW4
SW3
87654321 87654321
Comment
XXOOOOOO
Ethernet
Cheapernet XX111111 Transceiver Cable should
not be connected.
1) To run the TSMS Program OX111111 XXXX001C
from the 2764·20 EPROMs
in Cheapernet Configuration
2. To run the TSMS program or the Data Link Driver
program:
SW4
87654321
TSMS Program XXXXOO01
or
Data Link Driver
Program
Comment
TSMS program uses
the 82530 in
Asynchronous Polling
mode. Data Link Driver
program uses the
825830 in
Asynchronous Polling
and Vectored Interrupt
modes.
OXXXXXXX
1XXXXXXX
~) To run the TSMS Program OXOOOOOO XXXX001C
from the 2764·20 EPROMs
in Ethernet Configuration
~) To run the TSMS Program
1X111111 XXXXOO01
or the Data Link Driver
program from the 27210
EPROM in Cheapernet
Configuration
~) To run the TSMS Program
1XOOOOOO XXXXOO01
or the Data Link Driver
program from the 27210
EPROM in Ethernet
Configuration
5. Dip Switch SW2 programs the number of wait states
for the 82586 (see Table 3).
1·295
AP-274
COMPANIES OFFERIN~ WIRE WRAP SERVICES
AUGAT
Interconnection Systems Division
40 Perry Avenue
P.O. Box 1037
Attleboro, MA 02703
(617) 222-2202
100935 South Wilcrest Drive
Houston, TX 77099
(713) 495-3100
Automation Delectronlcs Corporation
1650 Locust Avenue
Bohemia, NY 11716
(516) 567-7007
dataCon, Inc.
Eastern Division
60 Blanchard Road
Burlington, MA 01803
(617) 273-5800
Mid-Western Division
502 Morse Avenue
Schaunaburg,IL60193
(312) 529-7690
Western Division
20150 Sunburst Street
Chatsworth, CA 91311-6280
(818) 700-0600
South-Western Division
'1829 Monetary Lane
Carrollton, TX 75006
(214) 245-6161
European Division
In der Klinge 5
D-7100 Heilbronn, West Germany
(01731) 217 12
DATAWRAP
37 Water Street
Wakefield, MA 01880
(617) 938-8911
Elma/EMS
A Division of Sandberg Industries
Berkshire Industrial Park
Bethel, CT 06801
(203) 797-9711
1851 Reynolds Avenue
Irvine, CA 92714
(714) 261-9473
3042 Scott Boulevard
Santa Clara, CA 95054
(408) 970-8874
WRAPEX Corporation
96 Mill Street
Woonsocket, RI 02895
(401) 769-3805
1-296
intJ
AP-274
APPENDIX B
SOFTWARE LISTING8-TSMS PROGRAM AND
LANHIB INITIALIZATION ROUTINE
1-297
AP-274
1*****************************************************************************1
1*
r./
TraffIc Slmulator/~onltor Station Program
for 186/586 High Integration Board and
iSBC 186/51'
<,I
*1
*1
"I
Ver
December 17,
1. 0,
1784
Intel Corporation
*1
*1
*1
*1
1*****************************************************************************1
1* Thls software can be condltlonally complIed to work on the iSBC 186/~1 or
on the LANHIB
If 'set(SBC1865l)' lS added to the complier call statement,
thls source program will be compiled for the lSBC18651
*1
tsms'
do;
2
declare main label publiCI
1* literals *1
$IF SBC18651
declare ht
hterally
true
ht
false
lit
forever
lit
ISCP$LOC$LO
ht
ISCP$LOC$HI
ht
SCB$BASE$LO
ht
SCB$BASE$HI
ht
CA$PORT
ht
BOARD$ADDRESS$BASE lit
INT$TYPE$586
lit
INTSTYPE$TIMERO
lit
INT$CTL$TIMERO
lit
INTS7
lit
PIC$MASK$130
llt
PIC$MASK$186
llt
ENABLE$586
lit
ENABLE$586$186
lit
P IC$EOI$I30
lit
EOI$CMDO$130
lit
EOI$CMD4$130
lit
PIC$EOI$I86
ht
EOI$CMDO$186
ht
PIC$VTR$186
lit
'literally',
'1' ,
'0',
'while l ' ,
'OFFFOH' ,
'0',
'0',
'0',
'OC8H' ,
'OFOH',
'20H',
'30H',
'OFF32H' ,
'27H',
'OE2H' ,
'OFF28H' ,
'OFEH',
'OEEH' ,
'OEOH' ,
'bOH',
'64H',
'OFF22H',
'0',
'OFF20H' ,
292010-31
Traffic Simulator/Monitor Station Program
1-298
AP-274
TIMERO$CTL
TIMERO$COUNT
MAX$COUNT$A
CA
ESI$PORT
NO.LOOPBACK
LOOPBACK
lit
lit
lit
lit
lit
lit
lit
'OFF56H',
'OFF50H' ,
'OFF32H' ,
'0'.
'OCBH',
'B',
'0';
$ELSE
3
decl.r. lit
true
li tel'ally
lit
lit
forever
lit
ISCP$LOC.LO
lit
ISCP.LOC.HI
lit
SCB.BASE.LO
lit
SCBSBASE$HI
lit
CA.PORT
lit
BOARD.ADDRESS$BASE lit
INTnVPE$586
lit
I NT.TVPE.TIMERO
lit
INTSCTL.TIMERO
lit
PIC$MASK$186
lit
ENABLE.586
lit
ENABLE.586'186
lit
PIe'EOI$186
lit
EOl$CMDO$186
lit
EOI$CMD4$lB6
11t
TIMERO$CTL
lit
TIMERO$COUNT
lit
MAX'COUNTSA
lit
CA
11t
ESI$PORT
lit
NO'LOOPBACK
lit
LOOPBACK
lit
foils.
'I i teral1 y
'1' ,
'0',
'wh i 1. l' ,
'03FFSH' •
'0'.
'0'.
I I
'0',
'8000H',
'BIBOH' ,
'12',
'8'.
'OFF32H',
'OFF28H "
'OEFH'.
'OEEH'.
'OFF22H'.
'12' ,
'B',
'OFF56H' ,
'OFF50H' ,
'OFF52H' •
'0',
'8100H' •
'1' •
'0',
$ENDIF
$IF NOT SBC1B651
1* System Configuration Pointer *1
4
declare scp structure
(
sysbus byte,
unused (5) byte.
iscp$addrSlo word,
lscp$addr$hi word
I
at (OFFFF6HI data (0. O. O. O. 0. O.
ISCP$LOC$LO.
ISCP'LOC$HII.
'ENDIF
1* IntermedIate System Configuration Pointer *1
292010-32
Traffic Simulator/Monitor Station Program (Continued)
1-299
inter
5
AP·274
declare 15cpSptr pOinter,
iscp based iscpSptr structure
(
1* set to 1 by CPU before it. first CA to 586,
cleared b~ 586 after reading 1nfo from It *1
1* unused *1
scb$o WOT'd,
1* offset of system control block *1
scb$b (2) word 1* base of system control block *1
busy by te,
unused byte,
),
1* System Control Block *1
6
decla,.e scb structure
(
status WOT'd.
cmd word.
cbl$ofhet word,
rpa$offset word,
cT'c$eT'rs word,
aIn •• r1'5 word,
rlc.erT's word,
ovrnSerTs word
1*
1*
1*
1*
1*
1*
1*
1*
cause(s) of interrupt, CU state. RU state *1
int acks, CU cmd, RESET bit, RU cmd *1
offset of first command block In CBL *1
offset of first packet descr1ptor 1n RPA *1
ere error encounterd so 9a1' *1
alignment errors *1
no 1"850U1'[.5 *1
overrun errors *1
),
1* 82586 Action Commands *1
1* NOP *1
7
declare nap structure
(
status lUol'd,
cmd word,
link$offset word
),
1* Individual Address Setup *1
8
declare iaSsetup structure
(
status word,
cmd UJDl"d,
link$offset word,
ia$address (6) byte
),
1* Configure *1
9
declare configure structure
(
statuI Idord,
cmd ,word,
link$offset word,
byte$cnt byte,
.nfo (11) byte
I,
292010-33
Traffic Simulator/Monitor Station Program (Continued)
1-300
intJ
AP-274
1* MultIcast Address Setup *1
10
declare mcSsetup structure
(
status laIord,
cmd '-lord.
llnk.offset word,
mc.b~tR.count
word.
rnc$sddrRss (48) byte
1* only 8
Me
addresses are allowed *1
);
1* TransmIt *1
1* Thls transmit command is made of one transmit buffer descr1ptor and one
1518 bytes long buffer, *1
11
declare transmIt structure
(
status \liard I
cmd word,
l1nk.offset word.
bd.offset ,"ord.
dest.adr (6) byte.
tlJPe word
).
1* Transmit Buffer DescrIptor *1
12
declare tbd structure
(
ae tSc aunt word,
link.offset word.
adO word.
adl word
);
13
declare t •• buffer (1518) byte;
14
declare tdr structure
,* TDR *1
(
status word I
cmd word.
llnk.offset word,
result word
).
1* Diagnose *1
15
declare dIagnose structure
(
292010-34
Traffic Simulator/Monitor Station Program (Continued)
1-301
infel"
AP-274
status word,
cmd word,
link'off.et word
);
1* Dump Status *1
16
declare dump structure
(
status word,
cmd word,
link'offset word.
buff'ptr 1II0rd
. );
1* Dump Area *1
17
declare dump'area (170) byte;
1* Frame DescrIptor *1
1* Receive frame area is made of 5 RFDs.
buffers. *1
18
5 RBDs. and 5 1514 bytes long
declare rfd (5) structure
(
status word,
elts word,
link.offset 1II0rd.
bd'ofhet word.
dest.adr (3) word.
IreSadr (3) word,
type word
);
1* Receive Buffer Descriptor *1
19
declare rbd (5) structure
(
act.count word,
next.bd.link lIIord.
adO word,
adl word,
size word
);
1* Receive Buffer *1
20
declare rbuf (5) structure
(buffu (1514) byte);
21
declare status word,
1* global variables *1
1* UART status *1
292010-35
Traffic Simulator/Monitor Station Program (Continued)
1-302
intJ
AP-274
actual lIIord,
1* actual numbe,.. of chars UART transferred *1
c.buf (80) byte,
dh . . byte,
ch byte . t Cec.buf),
char.count b'-!tll
1* buffer for a lin. of chars *1
1* numbe,.. b•••• ",itch *1
receiv •• count dword,
1* counte,.. for received frames *1
1* count.,.. for transmItted frames *1
c aunt dillard I
pr.ambl. word,
1*
1*
1*
1*
.ddr •••• l.ngth byt.,
.d.loc byte,
cre bvte,
pre.mble l.ngth in word *1
.ddress length in byte *1
.ddre •• loc.tion control of
crc ltngth *1
82~86
*1
gob.ck byte,
r ••• t bVtll
1* if: •• t,
del,.,,, word,
cur.cbSoff •• t word,
current.frame bVtll
nostransmil.ion byte,
1* delav conunt for t,..anmi.lion delay *1
1* off •• t of current command block *1
1* off •• t of frame descriptor Just used *1
.top.count dword,
.top byte,
1*
go back to Continuous Mod. *1
1* re.et flag *1
transmit terminal frame count *1
me.count bVtll
z byte,
y byte.
22
1
read:
23
2
declaT"e (a,
c) lI.Iord,
(b,
end read;
d,
24
25
26
b,
c,
d,
,) Ixt.,,".1;
.) pOintRr;
1
2
write: procedure (a, b,
dec 1.re (a, c) \IIOT'd,
(b, d) pointer .
end write .
1
csts: procedure byte externalJ
end cstSl
27
28
29
procedure (a,
2
1*
30
utilit~
offset:
c, d) external .
procedures *1
procedure (ptr) \IIOrdi
1* ThIS pToe.dura takes a painter variable (selector offse~),
calucul~tes an
.bsolute address, lubtracts the 82586 SCD offlet from the absolute address,
and then returns the result as an offset value for the 82586 *1
31
2
32
2
declare (ptr, ptrSloc) p,olnter,
bau586 dword,
w based ptr.loc CO2) word,
.
ptr'loc = liptr.
1* 82586 SCB Base Address (20-b,t wide in this 186 based
5yst~m)
*1
292010-36
Traffic Simulator/Monitor Station Program (Continued)
1-303
AP-274
33
34
2
2
35
2
base586 = hhICdouble(15Cp scb.b(I», 16) and OOOFOOOOH) + ,scp scb$b(o),
return lo..,«sh'j(double (..,(1», 4) + ..,(0»
- baseS86);
end offset,
wTlteln
36
procedure Ca,
b,
(,
d),
1* ThlS pro~edure ..,r,tes a ~ine and put a CR/LF at the end
37
2
38
39
2
2
40
2
declare (a,
(b.
d)
pOinter.
call ",rlteCs.
call writeCO.
b. c, d);
@(ODH, OAH),
2,
@status),
end wri teln,
crSlf
41
procedure,
1* ThIs procedure writes a CR/LF.
42
2
43
2
44
call wrIte
(0,
@(ODH,
OAHL
*1
2.
@status);
end cr$lf;
pause:
p~Dcedure;
1* This procedure breaks a program flow,
45
46
47
2
2
2
48
2
*1
c) word.
and
wai~s
*1
for a char to be typed
call ..,rite(O, @(ODH, OAH, 'Hit
:2
60
61
2
:2
62
2
*1
dec lare i '-lard.
c.l1 "1f.d(l, at.buf, eo, eactual. _status),
i • skip;
returnee'bufCi»,
end read'chari
63
64
:2
65
66
67
6e;>
70
71
2
3
3
3
3
3
72
3
73
2
do fOY'.veT'i
b - re.d'chilTi
if b • '1' then return 11
els.
i' b - '0' then return 0,
else
call writ. '),
procedul"'e byte;
1* This procedure reads a character and determine, if it is a YeV) or NCn)
decla"e b
2
76
77
79
90
91
92
2
3
3
3
3
3
do fOT'everj
b = read$cha1"i
If (b = 'Y') or (b = '~/) then return true;
else
I' (b = 'N') Dr (b
'n~) then return f.1se;
93
3
end;
94
2
end yes;
=
1'15.
call writeCO,
char$to$int· procedure (c)
95
I(ODH, OAH, "
2
97
9e;>
e;>0
91
2
2
2
2
Enter a Y or N ==.> '), 22, @status)'
b~tei
1* ThIS procedure converts a byte of
96
*1
b~tei
75
ASCII integer to an Integer
*1
dec lare c bfd te;
If ('0' (= c) and (c (= '9') then return (c - 30H);
else
If('A' <= c) and (c <= 'F') th_n return (c - 37H)/
else
292010-38
Traffic Simulator/Monitor Station Program (Continued)
1·305
inter
'i'2
'i'3
2
2
'i'4
2
Ap·274
if! ('a' <= c) and (c
else return OFFH,
<=
If')
then return (c - 57H),
end cha,..ta.lnt,
'i'5
1* Th,. p,.acedure canve,.t. an ,nte,.ger < OFFFFFFFFH to an arrav of ASCII
lodes.
Input variables are
valure = Integer to be converted,
base - number base to be used for conversion,
Id = l •• dlng charact.,. to be f'lled in,
bufadr • buffer address of the arrav.
width a size of arrav. *1
'i'6
:2
declare value dword,
bufadr pointer,
(i,
J.
base,
Id, width) bVte,
cha,.. ba.ed bufad,. (1) bute,
'i'7
'i'B
'i''i'
101
102
103
104
105
106
107
lOB
10'i'
2
3
3
3
3
3
110
:2
:2
2
3
3
3
2
do i
= 1 to ~,dth,
J = value mod base;
if J'< 10 then cha,.. (~idth - ,) = J + BOH,
else cha,.. (~,dth - ,) E J + 37H,
value - value I base,
end;
1 == 0,
do Whll. chars (i) = '0' and 1
chars ( i ) • 1 d;
1 •
i + b
end;
width - 1;
cha,..caunt • width - I,
end lnt'toSasc i;
aut'wa,.d: p,.acedu,.e
111
<
'(~'pt,.,
distance),
1* An integer at (.electar of ~'pt,.) (offset of w'pt,. + distance) Is p,.inted
.s a 4 dig,t hexadecimal numb.,.,
*1
112
:2
113
114
:2
115
:2
116
2
declare cha,..(4) bute,
~'pt,. pa,nte,.,
distance byte,
W ba •• d w'pt,. (1) ward,
call Int.ta'a.cl(w(dutance), 16, '0', .char.(O), 4),
call ...ri t. (0, .chars (0), 4, @status),;
end out'word;
write.1nt: procedureCdw,
t)i
1* An Integ.,. (d .. ) i l p,.,nted In hexadeCImal (t = 1) or in decimal It = 0),
*1
292010-39
Traffic Simulator/Monitor Station Pr~ram (Continued)
1·306
intJ
117
2
118
119
120
121
122
123
2
2
3
3
3
2
124
125
126
3
3
3
127
2
AP·274
d.cl.~e
dw dillard,
ch ..... C10) bUt..
t bUte.
" t then
do.
call intStoS •• cICdw, 16. 0, IcharseO), 8)i
call "'''lteCO, .charseS-char.count), char.count. G!!statu6),
end,
.In
do;
call intStoS.SC1(dw, 10, 0, .char.CO), 10),
call 1II1'it.(O • •ch.,.s(10-charSCDunt), charScount. est.tus).
end,
end ",rit.tint,
128
1* ThIS procedure prints an 1nteger In deCImal and hexadecImal
129
2
130
131
132
133
2
2
2
2
134
2
135
declare dill dlllord,
call Wl'it • • intCd ..h 0),
call writ.CO, Ie' ('), 2, Istatus),
call .... it ••• ntCd ... 1),
call IIIriteCO, (Ie 'H) '), 2, estatus);
end outSdeethex.
.... it •• o"set
p .. ocedu .. eC"'pt .. ).
1* ThIS procedure takes a pOinter variable.
and prints It in hexadecImal
*1
136
2
137
138
139
140
2
2
2
2
141
2
conv.,.ts i,t to .. 82586 t\lpe af'fs.t.
declare wSptr pointer,
III word;
call wrlt.CO, etC
I
at '), 4, .status),
.. = o"setC"'pt .. ).
call
call
out'wDrd(.~,
IIoITlttt(O,
wrlt •• address
142
*1
@(/
0),
'),
2, @status),
procedure (ptT),
1* ThiS procedure takes a pOinter variable .nd prints it In thr
'selector offset', format
*1
143
2
144
2
declare (ptT. ptT'Sloc)
pointer,
.. based pt ... loc (2) "ord.
pt ... loc = @ptr.
292010-40
Traffic Simulator/Monitor-Station Program (Continued)
1·307
AP-'274
145
146
147
148
2
2
2
2
149
2
call out.word C@wC
call Ulrite(O,
0),
'),
@status),
1,
call out.wordC@wCO), 0),
call write(O.
@('
'),
1,
(tstatus),
end wrlte'address.
print'wds'
150
1),
@(/
procedure(w$ptr,
no'words),
1* ThIS procedure prints no.words
lSI
2
152
153
154
155
156
157
158
159
160
161
2
2
3
3
4
4
4
4
4
3
162
2
numb~r
of words starting at w$ptr.
<>
if no.words
0
th~n
do;
call cr.H.
do i
:;: 0 to no'words -
1,
call out'word (""'ptTI
if
1
:;:
1);
0 then
call writ •• offsetCw.ptr);
call crflf;
end;
end;
end print."",ds;
printf.tr· procedure Cstrfptr. len).
163
1* This procedure prints len number of bytes starting at str.ptr.
164
*1
declare ""Sptr painter,
(i. no'words) bldte,
2
*1
declare Clen. i) byte.
chars (2) byte.
str$ptr pointer,
str based str.ptr (1) byte;
166
161
168
169
170
171
2
2
3
3
3
3
2
172
:I
Ib5
if len <> 0 then
do i = 0 to (len - 1);
call intSto'asci(stl"(i),
16,
'0', echars(O), 2);
call writ.CO. @chars(O). 2. @status),
call ",rit.(O,
@('
'),
2, Istatus);
end;
call cr.lf;
end print'at,.;
printfbuff: procedure. (ptr. cnt);
173
1* This procedure prints cnt number of buffer contents starting at ptr.
174
2
*1
declare ptr pointer,
bt based ptr (1) byte.
(i. J) byte.
cnt wordi
292010-41
Traffic Simulator/Monitor Station Program (Continued)
1-308
inter
175
176
177
17S
179
ISO
lSI
182
183
184
185
IS7
ISS
189
2
2
3
3
4
4
4
4
4
3
3
3
3
2
190
191
192
3
3
3
193
2
AP-274
do;
i
shrCcnt, 4) - I,
0 to i;
call w~lto.add~o •• (.bt(16*J»'
call p~lnt •• t~(.bt(!6*J)' 16),
If (J - 20) a~ (J • 40) or (J - 60)
call p.u •• ,
•
do J •
a~
(J • SO) then
endi
I = I + I,
If cnt-16*1
<>
w~lt ••• dd~I ••
0 thon call
call pl'int.strCebt(16*i),
(.bt(16*1»,
cnt-16*i);
end.
01 . .
do,
Colli
call
w~lt •• addro ••
(@bt(O»,
cnt),
p~lnt •• tr(@bt(O),
Ind.
end
p~lnt.buff'
194
1* ThIS procedure r •• ds Integer charact.r. and forms an integer.
If thp
integer is bigger th.~ 'lImit' or an overflow error is enCDunterred,
an error me.s.ge is printed.
*1
195
2
decl.,.. (laid,
(i,
196
197
198
199
200
201
202
203
205
206
20S
210
211
214
215
216
217
21S
2
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
3
219
220
3
3
221
223
4
4
.... h, lImit) dillord,
JI k, done, hex, dover,
then
hover) byte.
do forever,
Colli road (1. @c.buf, SO, @actual, @status),
k
i,
;a
he.,
laid.
=
skip;
done,
dover,
hover -
false;
IIIh == 0;
J
char.ta.lnt(c.buf(l»,
do while J <= 15,
if J > 9 then he • • true;
if not dover then
if wd > 429496729 then dav.~
t~ue,
else if (wd
429496729) and (J > 5) then dave~
true'
wd = wd*IO + J'
if not have~ then if wh > OFFFFFFFH then hover
true,
=
=
wh
=
=
=
",h*16 + JI
- i + 1;
J - char.ta.lnt(c.buf(I»,
i
end,
1f «c.buf(l) <> 'H') oInd (c.buf(,) <> 'h') and (c.buf(1) <> ODI1) and
(cSbuf(1) <> OAH) and (e.buf(l) <> ' '» or (I = k) th.",
Colli w~lteln(O, @(ODH. OAH, ' I1hgoll character'). 20. @status),
else
do;
If (clbuf(i)·. 'H') or (c$buf(i)
i f hex then
= 'hi)
then hex
= true,
292010-42
Traffic Simulator/Monitor Station Program (Continued)
1-309
AP-274
do,
224
225
227
228
229
230
4
5
5
4
4
4
231
4
call w1'lte(O,
232
233
234
235
236
4
4
4
3
3
call DutSdec$hex"(limlt),
call w1'iteln(O, @(' ' ) , 1,
237
2
If not hover and
(~h
<=
limit) then
~eturn
wh,
end.
else
If not dover and (wd <= limit) ·then return wd.
call writeln(O, I!(ODH, OAH, 'The.number is too b.g. 'J. 25,
@('
It has to be 1es5 than or equal to '), 3b,
(!st':ttus) •
==> '),
20, @~tatu5);
end,
end read.int;
put.address:
238
@status)i
end ..
call w1'ite(O, @(' Enter a number
procedure(",here),
1* This procedure puts an address t~ped In hexadeCimal to the ·Sp~cl'led
location 'where'. *1
239
2
declare where pointer,
(i, J. m. err) b\jte,
addr based where (1) byte,
240
241
242
243
244
245
246
247
249
2
3
3
3
3
3
4
4
4
250
251
252
254
255
256
257
258
259
260
261
262
263
264
265
266
267
5
5
5
5
5
4
4
4
3
3
4
4
4
4
3
3
3
268
2
do forever;
err
= false;
call read(l, I!c$buf, 80, I!actual, estatus),
i := skip;
m = address.length;
do wh.le (m <> 0) and not err,
J
char$to$int(c$buf(i»,
if J = OFFH then err = true;
else
=
do;
addr(m-l) • shl(J' 4);
J
char$to$int(c$buf(i+l»,
=
if J = OFFH then err = true;
else addr(m-l) - addr(m-1> or
~
end,
i - i + 2;
m = m - 1,
endj
if not erT' then
do;
m = c$buf(i);
if (m = ODH) or (m
then return;
= OAH)
or (m
=
Ihl)
or (m
'HI)
or
(m
,
')
end,
call writeln(O, @(ODH, OAH, ' Illegal charac·tn'), 20, estatus),
call write(O, @(' Enter an address in Hex -=) '), 29, @status);
end;
292010-43
Traffic Simulator/Monitor Station Program (Continued)
1-310
AP-274
269
1* This procedure calculat •• and prints a network percent load generated
by this .t.tion.
Th • • qu.tion u •• d in this procedure was obtaln.d
from actual m•• surement.. *1
dec 18".
270
2
2
2
2
j word,
(J. k) dword.
pc.nt (3) byte,
J - (tbd.act'count .nd 3FFFH) *8,
if not .d.loc th.n k • (2*.ddr •••• I.ngth + 2 + crc + pr.ambl.)*8,
el •• k • (ere + p" •• mble>*BJ
if del.y (> 0 then
.IF NOT SBC18651
276
i - low«1000*(J + k»/(1805 + k + 5*double(delay) +
J»'
277
SIF NOT SBC18651
= low«1000*(J + k»/(1810 + k + J»;
i - !ow«1000*(J + k»/(2026 + k + J»'
278
279
280
281
282
2
2
2
2
2
call intttotaBei(L 10, 0, @pcent(O),
call writ.CO, .pcent(O), 2, .statul)l
@('. ' ) , 1, estatus);
call write(O. il!pcent(2). I. 'status);
call ..,,,it.ln(O, (1(' 'X'), 2, @st.tus);
3);
call ",.rit.CO,
end percent;
283
284
1* ThIS station'. address is printed with its least slgnlficant bIt
in the most right position.
*1
285
2
declare ptr pointer,
addr based ptr (1) byt ••
char (6) byt ••
i byte;
292010-44
Traffic Simulator/Monitor Station Program (Continued)
1-311
intJ
286
287
288
289
2
3
3
2
290
2
291
292
2
293
294
295
296
2
2
297
298
299
300
301
302
303
304
305
2
2
2
2
2
2
2
2
2
306
3
2
~
do , = I to addres.$length.
char(i-l) = addr(addres.'lenqth-,);
end,
call pr,nt$str (echar (0). addre.s.length).
end prlnt.networkSadd,..,
prlnt'parameters
procedure,
1* This procedure
pri~ts
dec lare
dword.
stg. (6)
tr.nsmission parameters.
*1
\AI
b~te;
call writ.(O, I( I Destination Address. '), 22, (tstatu.),
if not ad$loc then
call print'n.twork$addr(etransmit. de.t$adr(O»;
else
call print$network$addr(etx$buffer(O»;
if not ad.loc then
w
(tbd.act'count and 3FFFH) + address$length * 2 + 2 + erc;
.1 . . w
(tbd. act$count and 3FFFH) + crc;
call write(O. e(' Frame Length: '). 15. estatus),
call write$int(w. 0);
call writeIn(O, (t(' bVtes')" 6, .status)j
call writ.(O, 1(' Time Interval between TransmIt Frames: '), 40, .status);
if d.I.~ <> 0 then
do;
.IF NOT SBC18651
=
=
w = 1810 + (double(delav) - 1)
*
5;
*
5.
.ELSE
w
= 2026
+ (double(delav) - 1)
,ENDIF
307
308
309
310
311
312
313
314
315
3
3
3
4
4
4
4
4
3
316
317
318
319
320
321
322
4
4
4
4
4
3
2
call int.to.asci( ....
if w >= 10000 then
10. 0,
estgs. 6);
do;
call
call
'il11
call
wrlt.(O, @stgs(O), 2, @statvs),
call
call
call
call
write(O. I!stgs(O). 5. Istatus);
",.rit.(O, @(', '), 1, Istatus);
wr,te(O. Istgs(5). 1. estatus);
uJ'riteIn(O, @(' micT'oseconds'), 13, @status);
w1"ite(O,
@(', 1),
1 . • status);
",rit.(O, @stgs(2), 2, @st.tus);
wl"iteln(O, @(' milis.conds / ), 12, @st.tus);
end;
else
do;
end;
end;
01$1
292010-45
Traffic Simulator/Monitor Station Program (Continued)
1-312
intJ
AP·274
.IF NOT SaCla651
cell writelnCO,
1(' 1'9.4 mlc1'osltconds'),
19,
ct.t.tUS)i
.ELSE
.ENDIF
323
2
call ,...rite
0) and (I
<
'f scb. cmd <> 0 then
do,
call "'Tlt.CO, @(ODH, OAH,
call "T'It..lntCI, 0),
aOOOH),
I
Wait Time
-= '),
15, @status);
call ntH,
end waittleb;
start$timerO: procedure;
1* 80186 tlmeT'O I. started.
*1
292010-46
Traffic Simulator/Monitor Station Program (Continued)
1·313
AP-274
349
350
output(TIMEROSCTL)
2
2
351
OEOOOH,
end staT'tStlmerO;
pT'ocedure interrupt INTSTYPE$586 reentrant,
1ST"
1* interrupt service T'Dutlne for 82586 interrupt *1
352
2
declare
1
byte,
1* Enab Ie 82586 Interrupt *1
SIF SBC18651
EOISCMDOSI30,
output (PICSEOI$l30)
enable;
$ELSE
353
354
2
2
EOl$CMDO$186,
output (PIC$EOISI86)
enab 1 ej
$ENDIF
1* Frame Received Interrupt has the highest priority *1
355
356
357
358
359
360
361
362
363
364
365
367
368
369
370
371
372
373
374
375
376
377
378
379
380
382
2
2
3
3
3
3
3
3
4
4
4
4
3
3
2
2
3
3
3
3
3
3
3
4
4
4
4000H then
i f (scb. status and 4000H)
do,
disablei
scb. cmd = 4000H,
output (CA$PORT) = CA,
call 1IIaitSscbi
if rfd(currentSframel. status = OAOOOH then
do,
recelve.count = receive.count + 1,
tUT'rentSfT'ame = cUT'T'entSframe + 1,
if currentSfT'ame = 5 then current$frame
end,
0,
return;
end;
i f (scb. status and 2000H)
2000H then
do;
disable;
scb. cmd
2000H,
output(CA$PORT)
CA,
call wait$scb;
enable;
if (transmit. status and OAOOOH)
=
=
OAOOOH then
do;
count = count + 1i
if (stop and (count
=
stop.count»
then return,
else
dOl
292010-47
Traffic Simulator/Monitor Station Program (Continued)
1-314
inter
383
384
3B'
386
387
38B
3B9
390
391
392
393
394
39'
396
397
398
399
400
401
402
403
404
405
406
407
40B
409
410
411
412
413
414
415
416
417
41B
419
420
421
422
423
424
425
426
427
42B
429
430
431
432
433
434
435
436
437
43B
AP-274
,,
transmIt status = O.
if delay - 0 then
do;
disable,
5
6
6
6
6
6
6
5
6
6
6
5
4
3
3
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
2
scb. cmd .. 0100Hi
output (CA$PORT>
call wait •• cbi
CA.
" .. turn;
end;
.lsl'
do,
if (transm.t status and 0020H) - 0020H then
do;
t".nsmit. st.tus - 0;
di.able;
seb. emd
OIOOH.
output (CA.PORT>
CA,
call wait$scbi
=
end;
if (transm.t. statu. and 0400H)
do,
= 0400H
then
call wrlt.(O.
@(ODH • • No CaT'rier ,Sense!',
tl'ansmit. status = 0;
disable.
seb. emd - OIOOH.
output (CA$PORT)
call wait$scb,;
return.
OOH),
20.
@statu~).
CA.
end;
., (transmit. status and 0200H)
do;
= 0200H
then
call writeCO. @(ODH. ' Last Clear to Send!',
transm1t status = 0;
disable,
seb. emd
OIOOH.
output (CA$PORT) = CA.
call waitSscbi
return;
OOH),
22,
@status),
=
end;
., (transmit status and OIOOH) = OlOOH then
do,
call wrlte(O, (!(ODH, 'DMA Undet'runl', OOH),
transm1t. status = 0,
dIsable.
seb. emd
OlOOH,
output (CA$PORT) = CA,
call ovai t$seb,
return.
16,
@status);
=
end,
end,
I.f (seb. status and BOOOH)
BOOOH then
292010-48
Traffic Simulator/Monitor Station Program (Continued)
1-315
inter
439
440
441
442
443
444
445
446
447
44B
449
450
451
do;
2
di .. bh,
scb. cmd = BOOOH,
output (CASPORT) • CA,
cdl ..aitSscb,
3
3
3
3
3
2
2
3
3
3
3
3
452
3
453
454
455
456
457
45B
459
460
461
462
463
464
465
466
2
2
3
3
4
4
4
4
4
4
4
4
3
3
467
2
46B
.. ndJ
if (scb.status and 1000H) • 1000H ~h.n
do,
disabh'
scb. cmd • 1000H,
output (CASPORT) • CA,
caU .. aitSscb,
call .."ite(O • • (ODH• • Receive Unit became not " •• dy. '. ODH). 33.
istatus),
end,
U iscp. bUIIV then
do,
call .."ihln(O • • (ODH. OAH. 'R ••• t fa~hd. '), 16 ••• tatus),
dhabI.,
scb. cmd • OOBOH,
output (CASPORT) - CA,
call ..aitSscb,
output ICASPORT) - CA,
call .."it.ln(O. 1(' Soft... ". R... t Executed! '). 25 • • status),
end,
e1 •• ~ ••• t-- f.l •• J
end,
end
is",
tISi.,,: p"ocedu"e int.""upt I NTSTVPEST I MERO,
1* inte""upt .u"vie8 "outin. fo" BOl86 time" inte""upt_1
469
470
471
.e b. cmd • 0100H,
output (CASPORT) • CA,
edl ...tts.eb,
2
2
2
SIF BBC1B651
DutputIPICSEOIS130) • EOISCMD4S130,
.nabh,
output(PICSEOISl86) • EOISCMDOS1B6,
SELBE
472
output(PICSEOIS1B6) • EOISCMD4S1B6,
SENDIF
473
.nd
txsts",
292010-49
Traffic Simulator/Monitor Station Program (Continued)
1-316
inter
AP-274
.IF SBCIBb51
Isr.7
procedure lnterrupt INT.7.
1* ThR 80130 generates an interrupt 7 If the original interrupt
15 not
active anV more when the fIrst interrupt acknowledge 'is received. *1
call .. rih(O. @(ODH.
'Interrupt 7'. ODH).
13. @.tatus),
end isr'7;
.ENDIF
474
475
I
2
47b
477
47B
479
2
2
2
2
4BO
2
4BI
re.d.byte proc.dure (k) byte,
declare k word;
call "rlte(O. @(ODH. OAH • • Enter byte ').
call outtdoc$hex(k),
call UI'"it.CO, et(' ==) '), 5, .status);
return r •• d'lnt(OFFH)i
lnit.1Bh.tim.TO:
14. I.tatus).
proc.du"el
1* This procedure Initializes the 80186 timer O.
4B2
*1
2
tIF SBCIBb51
=
output(INT$CTL$TIMERO)
B,
.(OOH, OAH,
Enter a dela~ count ==> J), 27, @status);
delay
read$int(OFFFFH),
if (delay ( 100) and (delay <) 0) then
do,
call cr.H.
call cr$H.
call loop$charC35, '*')j
call IIIrite(O. @(' WARNING '). 9. @status),
call loop$char(35, '*'),
call IIIrlteln(O, @(ODH. OAH. 'A delay count bet .. un 0 and 100 may be verv
'dangerous when thIS station starts'>. 80, @status),
call wrltelnCO, @('to receive manv frames separated only by th~
'IFS perIod (96 mIcroseconds). '), 75, @status);
call wrltelnCO, C!( 'If thlS station never receives a frame. then
'ignore thIS warning '), 65, @status),
call loop$char(79, '*');
endi
output(MAX'CDUNTtA)
delay,
call cr$19;
output(PIC$MASK$IBb) = 3EH.
call wrlt.CO,
=
=
292010-50
Traffic Simulator/Monitor Station Program (Continued)
1-317
inter
AP-274
.EISE
4B3
4B4
4B5
4B6
4B7
4BB
:2
output(INT'CTL'TIMERO)
2
2
2
2
delav ~ re.d'.nt(OFFFFH),
output (MAX.COUNT.A) = delav,
2
~
OCH,
call wrlt.(O. @(ODH, OAH.
I
Enter a delau count
=nz)
27, @statu!lo);
'),
call cr.l,;
output(PIC'MASK'IB6) = ENABLE.5B6.186, .
$ENDIF
4B9
2
end .nit$IB6.timerO,
490
491
1
2
dec lara i bvtei
setup'IA'parameters. procedurel
492
2
c.ll wr.te(O, a(OOH, OAH,
493
494
495
496
497
2
if "es then
2
3
3
2
49B
3
call ",,,it.(O, I(ODH, OAH,
499
500
3
3
call put'address(aia'.etup. ia'.ddress(O»,
501
2
end •• tup.ia'parameters;
502
503
1
2
.etup'me'parameters: procedure;
declare (J' k, don,,) bVte,
504
505
2
2
J = OJ
call .. rihln(O, a(OOH, OAH,
506
507
2
2
done. falslt;
SOB
509
510
511
512
513
514
515
516
2
3
3
4
4
4
4
4
5
do while not done.
if V.I then
517
:HB
519
5
5
4
520
5
Configure the 586 with the prewired'
, ' board add.,..s.
==> '),
57,
~statu!.);
=
do i
0 to address$length - 1,
i •••• tup. ia •• ddresl(i) = input(BOARO.AOORESS.BASE + 10 - 2
*
i)'
end;
else
do;
' Entel' this station"s address',
, in Hex ==:> '),43, Istatus};
end;
' You can enter up to B Multicast Addresses. ' j ,
45, ti'!st"tus).
call ..rite(O, a(' Would vou like to enter. Multicast Address?',
, (V OT' N) ==) '), 59, 'status),
do;
k • J
J •
*
address'length,
J + 1;
cilll cr.lf.
if J • 9 then
do.
call write(O, a(' You alreadv entered B Multicast addresses. 'J,
43, a .. t .. tu.).
end;
else
do.
Clll1 \ll'rite(O, @(' Ent.,. a Multicast Address
=-> '),
31,
C!status)j
292010-51
Traffic Simulator/Monitor Station Program (Continued)
1-318
inter
521
522
5
5
523
524
525
526
527
529
530
531
532
533
5
4
3
3
2
2
2
2
2
2
534
2
535
536
1
2
537
538
539
540
541
542
543
544
545
546
547
548
549
2
2
2
2
2
2
2
2
2
2
2
2
2
550
551
552
2
3
4
AP-274
call put."ddr ••• I.mc ••• tup.mc •• ddresslk»,
call writ.CO, .(ODH, OAH, 'Mare Multic •• t Addr ••••• ?',
, (V or N) ~=> '), 42, I.tatus);
end;
end;
Iisl done -
truI;
end;
if J a 9 thin
-
1;
J -
me'count c address'length * Ji
mc ••• tup.mc.bvt"count ~ me'count;
call writ.CO, .CODH, OAH, ' You enterld '), 1~, est.tus),
c"ll ..rlh.lntIJ' 0),
c"ll .. rlt.lnIO • • 1' l1ultica.t Addr . . . I . . ). 'I. 23 • • ohtuo),
•• tup'configure'parameters: procedure;
declare Ik.
J)
b~h.
configu ••. b~t •• cnt - 11,
configur •. infolO) - 8,
configure. info(l) - OJ
configur •. info(2) configu ••. Info(3) =
configurl. i"'o(4) •
configu ••. info(5) •
configure. info(6) •
configur •. Info(7) •
configure. Info(8) •
conflgu.e. info(9) J • Oi
call ... It.IO • • IODH.
, valu ••. ', ODH,
26H.
0,
96;
O.
OF2Hi
0,
0,
64.
OAH.
OAH,
, Configure command is •• t up for d~f.ult/,
I
Do ~ou ",ant to change any bVtIS?',
, (V DT' N) ==::> '), 99, Istatus);
do .. hile ~n'
do .. hile J - 0,
c .. ll ... It.IO • • IODH. OAH.
'Ente. bVte number (1 - 11)
==)
'I. 34.
@st~tus) j
553
554
555
556
557
559
560
561
J ~ r •• d.int(11)j
if J
0 then
call .. rlte(O • • (ODH. OAH.
4
4
4
4
3
3
3
3
=
' Illegal byte numb.r').
22. Ihtatus).
endl
If J • I thin con'lgure. bute.cnt . . . . . d.b~t.(J).
else configu~e. info(J - 2)
~
d.bvt.(J)J
J =- Oi
c.l1 wT'ite(O, .(ODM, OAH. I AnV moT'. byt •• ? (Y DT' N) =r.:>
= ••
I).
3~,
(!statu5) •
562
563
564
565
567
568
571
3
2
2
2
2
2
2
573
2
end;
preamble - ohlO. shr«conHgu.e. info (2) .nd 30H). 4)+1).
address.length
configure. Info(2) and 07H.
If add.ess.length • 7 then address.length • O.
ad.loc
shr«configure. In'0(2) .. nd 08H). 3).
i f Ih.«configure. 1nfo(7) and 20H). 5) th.n Cf'C
2, el.e crc
i f sh.«configure. Info(7) and 10H). 4) th.n crc - O.
=
=
= 4.
end setupSconfiguT'eSparametersj
292010-52
Traffic Simulator/Monitor Station Program (Continued)
1-319
inter
AP-274
574
575
I
setupStxSparamete-rs
2
dec lare ('si ze,
576
577
578
579
580
581
2
3
3
3
3
4
582
583
584
4
4
3
585
586
587
588
589
590
591
3
3
3
4
4
4
3
i)
proced,ure,
·..,ord.
do forever,
no.transmlsslon = false.
transmit. bdSoffset = offset (@tbd act.count),
if not ad$loc then
do;
call w"lteCO, ICOOH, OAH,
, Enter a destInatIon address In Hex ==0 '), 42. @statuf,),
call put'addr ••• (@transm,t dest$adr(O»;
end ..
el •• call writ.lnCO. @(' 82586 is configured to p,ck up DA. lA.
and TYPE from TX buHer, '). 64. @.tatus).
call cr.lf;
if not ad$loc then
do;
call writ.CO. @(OOH, OAH, 'Ent • .,. TYPE =~:> ,), 18. @st,atus);
transmit, t~pe
read.intCOFFFFH);
=
end;
call blT'iteln(O, @(ODH,
OAH.' How milny bIJ,tl. of transmit data?'),
3::;,
@StCltU5),
cilll writeCO,
EnteT' a number ==:> '), 20, Istatus);
592
593
594
595
596
597
598
599
600
601
602
603
3
3
3
3
3
'4
4
4
4
5
5
4
604
4
call wT'ite(O,
605
606
4
5
do while yes.
call w1'iteCO.
607
608
609
610
611
612
613
614
5
5
5
5
5
5
5
5
615
616
617
5
4
3
618
3
(!(
I
size = read'int(1518);
tbd,act'count
size or 8000H;
if size (> 0 then
do;
tbd, 1 ink'offset = OFFFFH;
tbd,adO
offset C@t,'buffer(O».
tbd, adl
0;
do i
0 to 1517;
tx'bufferCi) = i i
=
=
=
=
end;
call,w"itelnCO,
@(ODH, OAH,
Transmit Data is continuous numbers (0.
(!('
@CODH.
OAH.
Ente~
=
i
T'ead$int(size)1
call writeCO. @CODH. OAH.
call out$dec$hR,Ci);
call writ.(O,
1,
2, 3,',
)'). 57, @status),
Change any data bytes? (V OT' N) ==:> '), ":j."
@(
I
a byte number ==) '),
'i::!./, @status),
B~te').
8.
curT'ently contains '),
Ci!status).
20. @status).
call out$dec$hR,(t,$buff.rCi»;
call writ.CO,
t,$bufferCi)
call .. r,tRCO.
,1,
@('. ' ) ,
@status);
= read$b~teCi);
@CODH.
OAH.
'An~
more bytes? (V or N) ==:> '),
32. @status»)
end;
endl
else
transmit. bd.offset - OFFFFHi
call cr.lf;
292010-53
Traffic Simulator/Monitor Station Program (Continued)
1-320
inter
619
620
3
3
621
622
623
624
3
3
4
4
625
626
627
628
629
631
4
4
3
3
3
3
3
632
634
3
3
635
2
636
637
1
2
638
639
640
2
3
3
641
2
AP·274
c.11 Inlt'186.tlme~0,
call w"it'.CO, eCODH, OAH,
'S.tup. transmit t.rminal count?',
(V or N) .sa> '), 49, estatus);
i
630
stop - true;
call' write (0, .(ODH. OAH,
'Enter a transmit',
I
terminal count :1=:> '), 39 • • status);
stop.count = ~ •• d'lnt(OFFFFFFFFH),
end;
81 •• Itop • false;
c.ll c~'lf,
c.ll c~.l',
call print'paramet.,..s,
c.ll ..~ite(O,
It(ODH,
OAH,
'Good enough? (V
o~
N)
._> '),
29,
@stat.us)j
643
2
644
645
646
647
2
2
2
2
M8
649
2
2
2
2
2
2
2
2
651
652
653
654
655
~el
then return;
loop'char: procedure (i,
dec l .. re (I, J, k) b~te,
do k -
J);
1 to i;
call ",,.ite(O, (lJ,
1, Istatus);
end;
end loop'cha,.,
init:
642
650
if
end;
procedure;
declare
i
b\ltei
call cr$lf,
call loop'cha,. (13, OAH),
call loop.cha.,.(15, I ' ) j
call ..,.it.1n(O, 1t('TRAFFIC SIMULATOR AND MONITOR',
, STATION PROGRAM '),
call loop'char(7, OAH),
call .. ,.iteln(O, It(ODH, OAH,
Initialization ,begun'),
call c~'lf,
reset
tT'Uei
cur'cb'offset = OFFFFH,
output(ESI'PORT) - NO.LOOPBACK,
output(ESI'PORT)
LOOPBACK,
dhe. =- fal.e,
46,
estatus),
23,
Istatus);
=
=
1* set up interrupt logic *1
656
657
2
2
call
call
set'inte~~upt(INT'TVPE'586,
isr),
txtl.r),
.ettlnte~,.upt(INT'TVPE'TIMERO,
.IF SBC18651
292010-54
Traffic Simulator/Monitor Station Program (Continued)
1-321
AP-274
call set$interrupt(lNT$7,
output
output
output
output
output
(PIC.MASK.130)
(PIC.EOI.130)
(PIC.EOI.130)
(PIC.EOI.186)
(PIC.VTR.186)
lsr7),
= ENABLE.586.186,
EOI.CMDO.130;
EOI.CMD4.130,
EOI.CMDO.186,
30H;
.El.SE
658
659
660
2
2
2
output (PIC'EOI'186) = EOI'CMDO'186;
output (PIC.EOI.186) = EOI,eMD4'186.
output (PIe'MASK'186) = ENADLE'586;
!liENIJIF
1* locate iscp *1
661
2
1062
1063
1064
2
2
2
2
iscp.ptr
= ISep!liLOC.LO;
1* set up fields in ISCP *1
665
iScp. busy = 1.
iscp. scb!lib(O) = SCD.DASE.LO;
i.cp. scb.b (1) = SeD.BASE.HI;
iscp. scb.o = o"set (@ocb. status);
1* set up SCD *1
1068
1069
1070
1071
1072
2
2
2
2
2
2
2
1073
1074
1075
2
2
2
676
677
678
680
2
2
2
2
681
682
683
684
2
2
2
2
1066
667
scb. status = 0;
scb. cbl!lio"set
ocb rpa'o"set
o"set (@diagnose. status),
o"set (@r'd(O). status);
scb, crc'errs = OJ
scb. ainSerrs = OJ
scb.rsc$errs = 0;
leb. ovrn'errs = 0;
1* set up Diagnose command *1
diagnose. status = OJ
diagnose cmd = 7;
diagnose link'offset = offset (@configure status),
1* set up eONFIQURE command *1
configure. status = 0,
configure cmd = 2;
configure. link'offset = offset (@ia.setup.status) •.
call setup'configure'parameters;
1* set up IA command *1
ia'setup. status = 0;
iaSsetup. cmd = 1;
ia!lisetup. link'oHset
= oHset
(@mc!lisetup. status),
call setup.ia'parameters;
292010-55
Traffic Simulator/Monitor Station Program (Continued)
1-322
AP-274
Me
1* set up
685
686
687
688
command *1
;/
mcSsetup status = 0.
mc.setup. cmd = 8003H,
mc's.tup link'o"set = OFFFFH,
2
call setup.mc.parameters.
2
1* ,set up one transmit cb linked to its.lf *1
68'1
6'10
6'11
6'12
6'13
6'14
6'15
6'16
6'17
6'18
6'1'1
2
2
2
2
2
3
3
3
3
3
2
transmit status = 0,
call IIIritoln(O, @(ODH, OAH,
call wrlte(O.
if 'des then
' Would you like to transm.t-"),
@(' Enter a V or N
do,
=
transmit cmd
8004H.
==> '),
20.
30, @status),
@status),
=
transmit I.nk'o"s.t
OFFFFH,
tr.nsm.t. bd'o"sot
6"set (@tbd act'count),
call setup$t.$parameters.
=
end.
else no.transmlsslon = true.
1* lnltlallze receive packet area *1
700
701
702
703
704
705
706
707
708
70'1
710
711
712
713
714
715
716
717
718
71'1
720
2
do i
=0
to 3,
= o.
3
r'd(l) status
3
3
3
3
3
3
3
3
3
2
2
2
2
r.d(.) .I.s = 0,
r.d(.) I.nk'o"set
o"set (@r'd(.+I) status),
r.d(i). bd'o"s.t = OFFFFH,
rbd(i) act.count = 0,
rbd(i).next.bd.l.nk = o •• set (@rbd(i+1) act'count),
rbd(.).adO
o"~et (@rbu.(i) bu"er(O»,
rbd(i) adl = 0,
rbd(.) SlIe
1500,
=
=
=
end;
2
r'd(O). bd'o •••• t = o"set (@rbd(O) actScbunt),
r'd(4) status
0,
r.d(4'. el$s = 0,
r'd(4) I.nk'o"set = o •• set (@r'd(O). status),
OFFFFH,
r'd(4). bd'o"set'
rbd(4).act$cQunt = 0,
o"sot (@rbd(O) act'count),
rbd(4) next'bd$link
rbd(4). adO = o"s.t (@rbu'(4). bu".r(O»,
rbd(4) ad1 = 0,
rbd(4). S.10 = 1500,
2
count = 0,
2
2
recelve.count
0,
current. frame
0,
2
2
2
2
2
=
=
=
1* initialize counters *1
721
722
723
1* .ssue the '.rst CA *1
292010-56
Traffic Simulator/Monitor Station Program (Continued)
1-323
inter
724
2
725
2
Ap·274
output(CA.PORT) = CA.
enrl initi
pr,ntShelp
726
procedure;
.r.'
727
728
2
2
call writ.InCO, @(OOH. OAH.
call writeIn(O, @(OOH. OAH.
729
2
call lIrrlteln(O, @(' P - Print SCB
ctstatus);
o - O,splay k~D/CD·).
45. @.tatus).
C - SCB Control CHO'). 44.
730
2
call wT'lteln(O, @( , l. - ESI l.oopback On
N - ESI l.oopback Off').
Commands
S - Setup CB
'),
16,
@~tatu&);
731
2
732
733
734
2
2
2
735
2
736
737
2
738
739
740
741
742
2
2
2
3
3
743
744
745
746
747
748
749
750
751
3
3
4
4
4
4
4
3
2
752
754
755
756
757
759
760
761
762
763
764
2
2
2
2
2
2
2
2
2
2
2
call w,.iteln(O.
call ..,.i,teln(O.
call writ.ln(O,
45.
@(. Z - Cle.,. Tx F,."me Counter'). 27. estatus>.
@(' V - Clear Rx Frame Counter'). 27. @.t .. tus).
C!( I E - Exi~ to Continuous Mod.'), 2B, @.tatus),
end p1'lnt.help,
enterSscbScmd.
procedure,
dec I .. ,.. i byte,
1* enter a command into the SCD *1
call c,..H,
if scb. cmd <> 0 then
do,
call writ.ln(O, .(' sea command talOT'd il not cllar.d'), 32, .status),
call .. rite(O. GI(' Try a Cholnnel Attention? (V 0,. N)
'I.
39. Glbtatus I,
i f yes then
==>
do,;,
output(CA.PORTI • CA,
call writeln(O, GI(' hsued channel att .. ntion'l. 25. IIstatusl,
call cr.lf,
return,;
end;:
00 you want to onte,. any SCD commands? (V 0,. NI ==>
53, Istatu!..);
if not yes then return)
call write(O. I!(OOH. OAH. 'Enter CUC
'I. 17. llI"tatusl)
i .. re.d.int(4I,
scb. cmd .. sob. cmd or shl 'H') and ( t
(t <> 'N') and (t
(t <> 'D') and (t
Ct <> ' I ') and (t
Ct <> 'S') and ( t
call write(O • • (ODH.
7B7
7BB
7B9
790
791
792
793
794
795
796
797
79B
799
BOO
BOl
B02
B03
B04
B05
3
3
3
3
2
2
3
3
3
3
3
2
2
2
declar. (t. valid) bUhl
valid
do
= false.
~hll.
not Val1dJ
<>
<>
<>
<>
<>
, Enter command block tvP. (H for',
, help) '_.> '); 45, @status,)J
'h' )
'n')
'd' )
' i ")
IS ')
OAH.
,
and Ct ..:> 'T')
and (t <> 'R / )
and Ct <> 'C')
and (t <> '1'1')
then
Illegel command
and
and
and
and'
Ct <> 't' )
(t 0 'T')
It <> 'e ')
Ct <> 'm')
and
and
and
and
block tvpe' ), 29.
(!stcstuL) ,
2
2
3
3
3
3
3
3
else
.f Ct = 'H')
o~
(t - 'h') then c.ll prlnt.tup •• help.
else valId = true,
end;
if (t ~ 'N') or (t -= 'n') then
do.
cu~'cb'offset = offset (Inop. status),
nap. status:. 0;
nap. cmd - BOOOHI
nap l.nk.offset - OFFFFH.
end;
ift (t = 'I') or
(t
=- 'i') then
do.
cu~'cb'offs.t
• o'flet ( •••••• 'up.
laSsetup. status -
st.~u.).
0;
.a •• etup cmd - B001H.
••• setup l.nk'offset * OFFFFH.
call letup.ia'parameters.
end,
292010-58
Traffic Simulator/Monitor Station Program (Continued)
1-325
inter
906
907
909
909
910
911
912
813
914
BI5
BI6
917
919
919
820
921
822
923
924
925
926
927
929
829
830
931
832
933
934
835
936
937
838
939
940
841
842
843
844
845
846
847
848
849
850
851
852
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
2
3
3
3
3
3
853
2
854
855
I
2
2
2
3
3
3
3
3
3
2
2
3
3
3
3
3
3
:2
2
3
3
3
3
3
3
2
if
(t
= 'e') or (t = 'e') then
do)
cur.cb$o"set = off.et (@configure. status);
configure. status = 0;
eon~igur •. emd = 8002H,
configure. link'offset
= OFFFFH,
call setup'configur •• parameters,
end.!
if (t ..
= 'm') thlt"
'M') or (t
do;
eur'eb'o~".t
~
o~fset
= 0,
me.setup. status
(eme's"tup. status),
me_setup. cmd - e003Hi
me.setup. link'o" •• t • OFFFFH,
call setup'mc'param.t"rs.
end;
if (t
do'
c
'T')
OT'
(t -
't') then
cur$cb$of~s.t • of, •• t
transmit. statuI C 0;
«(tt~ansmit. status),
transmit. cmd • 8004H,
transmit. link$o"s"t = OFFFFH,
call •• tup$t.'parameters)
end;
if (t
do'
-
'R') or
== ',.') then
(t
cur$cb$offs.t - off •• t (Itdr. status),
tdr .• t.tus == 0;
tdr. cmd - 8005H,
tdr. link$offset • OFFFFH)
tdr. r.sult • Oi
and;
if (t -= 'S') Dr
do;
(t
!ill
's') than
cur$cb$off •• t • off.et (Idump. Ita,us),
dump. statuI· OJ
dump, cmd - 8006H,
dump. link$offset = OFFFFH,
dump. bu~~$ptr • o~f.et (edump$are.(O»,
end;
if (t
-
'D')
DT
(t -
'd
I)
then
dOl
eur$cb$o~f •• t
• offset (ediagnose. status).
diagnose. st.tul == 0;
diagnose. emd • 8007H,
diagnose link$off •• t • OFFFFH)
and;
d i sp laV$command$b 1 oc k: procedO"",
decl.,.. (i, J) byt •.
urh pointer,
sel selector,
Uf &&ford;
Traffic Simulator/Monitor Station Program (Continued)
292010-59
inter
8:16
8:17
8:18
8:19
860
861
862
863
864
86:1
866
867
868
869
870
871
872
873
874
875
876
877
879
880
882
883
884
88:1
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
2
2
2
2
2
3
3
3
2
2
3
3
3
2
2
3
3
3
2
2
3
3
3
3
3
3
3
3
3
4
4
4
AP·274
call cr.lf;
., cur.cb.a" •• t
z
OFFFFH th.n
call writ.CO, '(,' No Command 810ck to dilpla\l'),
I' cur.cb.a".et • a" •• t
28,
I!status),
C@nap .• t.tus) th.n
do;
c.ll wrlt.CO. @C'---NOP Camm.nd Black---·). 23. @status).
c.11 prlnt ... d.C@nap .• t.tu •• 3),
end;
,
i' cur.cb.af's.t • af, •• t
(@tdr .• t.tu.) then
do;
c.ll writ.CO. @C'---TDR Camm.nd Black---·). 23. @.tatus),
call prlnt.wds(etdr. statu •• 4),
end;
i' cur.cb.a" •• t • a".et (@di.gna ••.• t.tu.) then
do,
call writ.CO, a( '---OJ.gnose Command 810cll---'), 28, est.tul);
c.11 pr int.wd. (@di.gnau .• t.tus. 3),
end;
if cur.cb.a'f •• t • af, •• t C@tr.n.mit. st.tu.) th.n
do;
call writ.CO, I('---Tranlmit Command 810cll---'), 2B, .statul);
if not .ddr •••• l.ngth then i • addres •• l.ngth,
.1 • • • • • ddr •••• length + I,
i f ad. lac th.n ca11 prlnt ... d.(etr.nsmlt .• t.tus. 4),
.1 •• c.ll print.wd.C@tr.n.mit .• t.tu •• 1/2+1),
c.11 cr.lf,
c.11 cr.lf,
if transmit bd.of,.et <> OFFFFH then
do;
c.ll writ.(O. I('---Transmlt Buffer DescriptDr---'). 33. Istatus),
call print ... dsCltbd. act.count. 4),
call .. rite(O. @CODH. OAH. OAH.
, Dilpla", the transmIt buff ..... ? (V or N) ==> '), 46, @status).!
i f ~e. then
do,
call cr.lf,
call .. rit.ln(O. 1(' Transmit Buffer: 'I. 17. estatus).
. . . tbd.act.count and 3FFFH,
call p"lnt.buf' (eh.buffe" (0). ..),
4
4
:I
5
5
5
.nd;
5
4
end;
3
end;
2
if cur.cb.o"set • offset (Ii •• setup. status) th.n
do.
call ..,.it.(O. I( '---IA Setup Command Bloc'k---'). 28. (i.tatus),
call print$wds(@i.Ssetup. status, 6),
.. nd,
1f cu".cb.a'f •• t = offset (lcanfi9u"e. status) then
do.
ca11 ""i te (0. e( '---Canflgure Command Black---'). 29. Istatus),
2
3
3
3
2
2
3
3
3
2
2
3
3
call printt",dsC@configure status, 9);
end;
i f curScb.Dffset
do;
= offset (Imc.setup. status) then
call "Tite(O. iC'---MC Setup Command Blatk---'). 28. Istatus).
i = 4 + mc$count/2;
292010-60
Traffic Slmulator/Mon.ltor Station Pr~gram (Continued)
1-327
intJ
AP-274
If me.count ) 24 then
do.
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
92"
930
931
932
933
934
q35
936
937
3
3
4
4
4
4
4
3
3
2
2
3
3
3
3
4
4
4
4
5
5
4
4
4
3
938
2
end display$commandSblock;
939
940
2
display.receive$area: procedure,
declare (i, k. J, 1) byte.
941
942
943
944
2
2
2
3
~
call prlnt$wd$(@mcSsetup. status, 16);
call paus!!;
1 = 1 16,
call pT'lnt$wds(@mc$setup.mcSaddre.5S(S),
1),
end,
else call prlnt$wds(@mcSsetup status,
i),
end.
If cur$cbSoffset = offset (@dump status) then
do.
call Ul1'1te(0.
@('---Dump Status Command Block---'),
31.
@status),
call printSwds«!:dump status. 4),
1f dump status = OAOOOH then
do.
call wTlteinCO, @(ODH. OAH, ' Dump Status Results'),
call write.off.et(edump.area(O));
call cr$lfi
do 1
0 to 9,
call pr1nt.str«!dump.area( 1b*il. 16).
end,
call pr1nt •• tr«!dump.area'(160). 10);
call cr$1f;
end;
22.
@st.atus)
=
chars(4) bvte;
945
946
947
948
949
950
95:
\153
954
955
956
957
3
3
2
2
3
4
4
4
4
3
3
2
'158
959
9bO
9b1
9b3
964
2
3
4
4
4
4
call UI"'lteln(O, @(ODH, OAH, I FTame Descriptors' '), 21, @status),
If dd$loe then
do;
call' wr1teln(O, @(ODH. OAH. 'DA. SA. and TYPE are 1n buffer, '.
OAH)
=
I
36.
OlJl1.
(h.tat.o$),
J
3,
end;
else J ~ addTessSlength + 4,
do k = 0 to J'
do i = 0 to 4;
call DutSword(@rfd(i) status. k)j
if k
0 1hen call ~rit.'offs.t(@rfd(i), .tatu.).
else call 190p$char'10. I ' ) i
end:
=
call cr$lf!,
end,
call wrlteln(O.
@(ODH,
OAH,
OAH,
, Receive Buffer DescrIptor's'
1)1
:JJ,
do k = 0 to 4.
do i = C to 4;
call out.word«!rbd(il, att.eount. k);
if!, k = 0 th,en 1;.11 write$o"f'set(C!T'bd(l). act.count"
else call loop.char (10, I ' ) ;
292010-61
Traffic Simulator/Monitor Station Program (Confinued)
1-,328
inter
965
966
967
3
3
2
""'~
970
;/
971
972
973
974
..:.;.1" erSl',
end;
call lI.Il"'ite(O,
q"'1~
3
3
3
--<>
2
980
981
;/
982
2
OAH,
#
Displ." thfl
buflf!e-:':o'
(Y
or
,..,.uve·,
N) =-= . . '),
46.
(!Jot.t.al-us);
Rocuve Buffer. '), 19. @status).
t", 4,
writ.CO, I(ODH. OAH. ' M.'caivi Buff.", '), IB, @,c;t=~.,,·.',
,...rite'lntel, 0),
"'T'lteln(O, . ( '
'), 2, Istatusl.
k • rbd(;1 .ct.count and 3FFF~.
call print'buffCerhu#{ii Duff.rCO), k)i
c.11 p.u ... '
2
2
3
3
3
977
978
I(ODH, OAH,
if not ~ •• then return,
cd1 ..,.ih1n(0. @(ODH, OAH.
do i • n
call
call
call
3
end;
displa"'cb'rpa:
det 1 a,.. 1 i b"te;
,.11
pTocedure;
w~ite(O,
@(OOH, OAH.
Command Block or Receive Area"
,i,
47,
983
~'=.:.:
2
2
i
986
987
988
989
3
3
3
2
~::.t
2
992
2
end
993
994
1
2
declaT'. \u,
995
2
;;:
.2
2
=
end.
'R'I or (i = 'T") then call display$T'RCeive$aT'ea,
e1 •• call displ.~.comm.nd'blo,~,
if (1 -
dlsp1a~.cb.rpal
~T~tess'cmd.
pT'ocedure;
i \ byte;
gob.ck = 0;
b = T'ead'chari
call cr.H,
If (b ( ) 'H') and (b <> 'h' ) and (b <> 'S') and ( b -:> 's' )
( b <> '0'1 and (b
'd'l and (b <> 'P'I and ( b (.- • p ;
'r:') and ( b '"<> 'e ') and (b <> 'E'I and (b 0- 'e ')
(b <> 'L'I and (b <> '1') and ( b <> 'N'l and (b <> 'n ')
(b <> 'Z'I and ( b (;:.. 't / ) and ( b <> 'Y'I and (b <> 'q' )
(b <> 'A') and ( b <> 'a I) then
ca 11 write(O, @(' Illegal command '), 16, @statusl,
i f (b = 'WI or (b = 'h'l then call print.help,
It
= '''''I or (b = 'a ') then
,.
999
1000
1002
1003
1004
,,:C:>
1006
2
2
2
2
2
=.=P> '),
r •• d'cha"'i
III
:;
997
998
""
do while (1 <> 'R') and (i (> ',..') end (1 <> I e ' ) anu' (i <) 'e ');
call wT'itelnCO, .CODH, OAH, ' I!lpgal command '), 18. @status\,
call ",,..iteCO, (lC I EnteT' R OT' C =-=) '), 18, @st .. tus'),i
i
r •• d'chaT";
98~
:'-:Jt,.
Ql
@statut./'
and
~"d
and
and
and
'"do,
if dhex 'then
dhex = falstti
call WT'lte(O,
'1
3
@(
I
CounteT' • • ". dIsplayed In declmal
'),
3!:),
@StictU5),
1007
1008
:3
2
end,
eJ.se
292010-62
TraffiC Simulator/Monitor Station Program (Continued)
1-329
do,
1009
1010
3
3
1011
3
2
1012
dhex = true.
call wTlte(O,
end.
1026
1027
1028
1029
1030
1031
1032
1033
1035
1037
1039
1041
1043
3
2
2
3
3
3
2
2
3
3
3
2
2
3
3
3
3
2
2
2
2
2
2
1044
2
1045
1046
I
getout:
procedure,
2
decl~re
b b\lte.
1047
1048
1049
2
2
2
1050
1051
1052
1053
1054
2
3
3
4
4
lOSS
4
1056
1058
4
i~
4
call writeCO.
1059
1060
4
3
1061
2
1020
1021
1022
1023
1024
1025
'),
:39.
end.
"3
1014
1015
1016
1017
1018
1019
Counters aT'e displayed In heJlaGeclfnal
I,f (b = 'L') or (b = '1'), t,h en
do,
1,,]12
@(/
:;
output(E5I$PORT) = LOOPBACK,
call wTlte(O. @(/ ESI 15 in Loopback Mode '),
If (b
=
or
'N"
(b
=
'n')
25.
@status),
'),
29.
then
do,
output(E5I$PORT) = NO$LOOPBACK,
call write(O. @(' ESt 15 NOT In Loopback Mode
@status),
end,
If (b = 'Z') or
'z')
(b =
then
do,
count = O.
call WT'lte(O,
end.
If
(b =
'Y')
or (b
Transmlt Frame Counter 15 c;leared
@(/
=
''l')
'),
35,
@status),
then
do,
recelve.count = 0,
5tb creSerrs. 5tb
call wTlte(Q, @(/
end,
(b,
If
'C' ) or ( b
'5') or ( b
if ( b
If ( b
'P' ) or ( b
(b
If
'0' ) or ( b
If ( b
'E') or ( b
call crSlf,
=
5cb rsc$errs. 5cb.ovrnSerrs
0.
Receive Frame Counter is cleared. '), 34, @status);
aln$e1'1'5.
I
C
I
)
then call .nt~r$scb$cmd,
's ') then call setup.cbi
'p , ) then call printS5tb,
'd ') the" call display$cb$rpa,
'£I ' ) then goback
I;
=
end process$cmd,
b == read$chari
goback
= OJ
call wrlte(O.
@eODH,
OAH,
I
Enter command (H for help) ==::> '), 34,
@SthtU5)i
do forever;
If csts then
do,
dlsablei
call processScmd,
enable,
goback then return;
@(ODH, OAH,
I
Enter command (H for help) ==:> '),
34,
end;
end.
end 9 etout;
292010-63
Traffic Simulator/Monitor Station Program (Continued)
1-330
inter
AP-274
update.
procedurel
10102
10103
I
2
10104
10105
101010
10107
10109
10109
2
call crSlf,
2
2
2
2
1070
1071
1072
1073
1074
1075
2
2
2
2
2
2
2
2
call
call
call
call
call
call
call
10710
1077
1079
1079
1090
1091
1092
1093
109S
10910
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
1094
2
1095
2
10910
2
bijh,
loop$char (10. OAHl.
loopSchar(28. '*'),
write(O. @C' Station Configuration'), 23, I:st.tus);
loopScharC27. '*'),
cr$lf.
cr$lf,
.... rite(O, @(' Host Address. '), 15. @st.tus),
call print'n.twDrk'.ddr(~i •• s.tup i ••• ddr ••• CO»i
1 = 0;
2
1097
1099
1099
1090
1091
1092
1093
call writeCO,
@(/
Multicast Addressees)'
'),
24, f!status);
if mc'setup.mcSbyt.Scount - 0
then call "'t'it.lnCO, @C'No Multicast Addresse. Defined '),
else
30,
@status),
do while i < meSsetup me'byteScount;
call printSnetwarkSaddr(@mcS.etup mcS.ddressCi»,
call loopSchar(24.
1
::It
1
I
');
+ Oi
end;
call writ.(O. @(ODH). 1. @status).
if not noStransmission then call print'parameters;
call "'''It.CO, @C' 82586 Configuration Block. '), 28, ctstatus),;
call printSstr(@configure. 1nfo(0), 10);
call cr$lfi
call loop$char(29. '*').
call UJrite(O. @(/ Station Activiti.s '). 20. @status)j
call loop$char(29. '*');
call cr$lf;
call cr$if,
call wrihln(O.
@( . . . of Goad
.. of Goad
CRC
Alignment
No
R~ceiv .. ·).
'13. @st .. tus),
call UJr1telnCO,
ResouT'ce
(J'I("T'T'un').
Errors
@:(' Frames
Errors
Frames
73, @stntuS),
call wr1telnCQ,
Errors
Ell'orE.'),
@C' TT'ansmltted Received
72, @status),
end update;
main
1097
1099
1099
1100
1101
1102
1103
1104
1105
dec lare i
I
I
call lnit,
enable.
do wh i Ie reset;
end.
d lSab leo
scb cmd = OIOOH,
output(CA$PORT)
call walt$scb.
I
enable.
I
I
2
I
I
CA,
292010-64
Traffic Simulator/Monitor Station Program (Continued)
1-331
inter
1106
1107
2
I
1108
1109
1
1110
1
1
1111
1112
1
1113
1
1114
1
1115
1
1116
I
1117
I
1118
I
1119
1
1120
1
1121
1
1122
I
1123
I
1124
I
1125
I
1126
1
1127
1
1128
2
1129
2
1130
2
1131
2
1132
2
1133
2
1134
3
1135
3
1136
:2
1137
:2
1138
:2
1139
2
1140
2
1141
2
1142
2
1143
:2
1144
I
1145
1
1146
2
1147
2
1148
3
1149
4
1150
4
1151
4
1152
4
1153
4
1154
4
1155
4
1156
3
1157
3
1158
3
1159
2
1160
2
1161
3
1162
3
1163 ,3
1164
3
1165
2
1166
AP·274
do while (dIagnose status and BOaOH)
<> BaaOH.
end,
call cr$If.
If diagnose status <> OAOOOH
then call "'TltelnCO. @(' Diagnose failttd ' '), 17 • @status),
1f~ configure. status <> OAOOOH
then call wrlteln(O, @(' Configure failed! '), 18, OAOOOH
thtrn call wrlteln(O, @(' IA Setup failed l ' ) ,
1 f me.setup. status <> OAOOOH
then call writelnCO. @(' Me Setup failed! '),
scb cbl$offset
= offset
17
@status),
17
@status)'
(@transmit. status);
call wrltelnCO, .@(ODH,. OAH,
'Receive
Unl~
IS active. '),
26, @statu!'.),
disable.
5cb. cmd = OOIOH.
output(CASPORT) = CA.
call wait$scb;
enab Ie,
output(ESISPORT) - NOSLOOPBACK.
call cr$1 "
if not no.transmisslon thIn
do.
.( '---Transm1t Command
status, 8);
call
~rite(O,
call
prlnt.~ds(@transmlt.
call crSIf.
Block-~-'),
28. @status);
=
cur$cb$offset
offset (@transmit. status);
call pause;
do 1 = 1 to 60;
call time(250);
end,
call writ.lnCO, ICODH, OAH, 'transmission st.,.ted!'),
call cr$lf,
disable;
5tb cmd • 0100Hi
output (CA'PORT) = CA;
call wal t .. scb,
enab lei
23, @statuS)i
end;
call update;
do forever,
call
@(ODH,
~rlte(O,
I
'),
2, @status);
do y = 0 to 5.
do calie lJi
call
call
call
call
call
call
wT'ite$int(count, dhex);
writ.$lntCreceive$count,
write.int(scb. erc$.rrs,
write$int(scb. a1n$err5,
"'1"iteSlntCs-cb. rsc$errs,
writ.SintCscb ovrnS.rrs,
dhex);
dhex);
dhex);
dhex)j
dhex)i
end;
char.count = 13 - char.count,
call loopScharCchar$count, , '),
end;
If csts then
do;
disable;
call getouti
292010-65
call update,
end;
endi
end tsm.,
MODULE INFORMATION:
CODE AREA SIZE
23C3H
CONSTANT AREA SIZE
OF85H
VARIABLE AREA SIZE = 265EH
MAXIMUM STACK SIZE - 0092H
1994 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS
9155D
3973D
9822D
146D
DICTIONARY SUMMARY'
159KB MEMORY AVAILABLE
23KB MEMORY USED
(147.)
OKD DISK SPACE USED
END OF PL/M-86 COMPILATION
292010-66
Traffic Simulator/Monitor Station Program (Continued)
1-332
AP·274
I***************** •• *~.**.·************************************************ .......
~I
1*
1*
186/586 H.gh Integration Board lnlti3litation Routine
(ThIS drIver IS configured for Ethernet/Cheapernet Desiqn
I.
*1
*1
*1
Kit Demo Bo .... d)
,iI
1*
1*
1*
1*
V.,.
March 14, 1986
2.0
*1
.,
~I
KI~o.hl
Nlsh.de
Intel
/***************"'ft* JI • • • • _____ *__ • __
It.
~o,pDr.tion
**_*_*_._.....________*__• __*_____ ...........
""
*1
~
I
1* rhe cond.tional comp.lat.on ~a-am.ter 'EPROM2712B' determines board ~OM
511e
If it IS true, the 80186'. ~.lt stat. oenerator 11 program•• d to
o
wait state 'or upper 64K-bute memory locations
il!~ is '.lse,
the
wait .tate generator •• programmed to 0 wait state 'or uppe- 1~8K-bytp
memorV
IDc.tlQn~
*1
.
do;
"
declare hlb_ir label publici
declare main label •• ternall
declare menu 1.Del e_tern.li
1* literals *1
declare lit
UMCS_reg
literally
lit
lit
PACS_reg
lit
MPCS_reg
lit
INT_MASK_reg
lit
ISCP.LOC.LO
lit
ISCP.LOC.HI
lit
!?Cr. ,CH_B_CMD
lit
SCC_Ct1_D_l:'."T'"
lit
SCC_CH_A_CMD
l1i.
SCC_CH_A,D"'T~
ht
NI"_
lit
CR
lit
LF
lit
BS
lit
SP
lit
OM
Itt
DEL
ht
BEL
lit
:"1"'('9_"eo
'literaBy' ,.
'OFFAOH',
'OFFA2H',
'OFFA4H',
. OFrA9"",
'OFF28H',
'03FFSH',
'0'.
'8300H',
'S302H',
't;:I'104H',
'S306H',
'0',
'ODH',
'OAH',
'OSH'.
'20H',
'3Fn ,
'07FH'.
'07H' ..
292010-67
186/586 High Integration Board Initialization Routine
1·333
AP-2-74
I*Ststem Configuration Pointer *1
declare scp structure
6
(
svsbus bVte.
unused (5) bVte.
iscp'addr.lo word.
iscp'addr.hi word
)
at (OFFFF6H) data (0. O. O. O. O. O. ISCP.LOC.LO. ISCP'LOC'H., •
.,
8
2
9
2
end init'int'clt,
10
1
11
2
rra: procedure (reg_nol bute,
declare reg_no bute,
12
14
2
2
15
2
end ,.,..,
16
17
1
:2
rrb: procedure (reg_no) bvte,
18
20
2
2
21
:2
end rrb,
wra: procedure (reg_no, v.lue)1
dec I.,.. (".,_"0, value) byte;
22
1
2:-t
2
24
26
2
2
27
2
2e
i' (reg_no and OFH) <> 0 then output(SCC_CH_A_CMDI = reg_no and OFH,
return input(8CC_CH~_CMD)'
decl.,.. ,..g_no byte,
i' (reD_no and OFH) <>0 then output CSCC_CH_B_CMDI
return input(SCC_CH_B_CMDI'
a
reg_no end OFH.
i' (reg_no and OFHI <> 0 then output (SCC_CH_A_CMDI • reg_no and OFH.
output (SCC_CH-A_CMDI • ValUe,
end "'raJ
procedure (reg_no, value);
decla,.e (,..g_"O, value) but.,
~,.b.
20
2
30
32
2
2
33
2
34
3:;
output (INT _mask_reg,) - OFFH, 1* ma.k all interrupts *1
i ' (reD_no and OFHI <> 0 then output (SCC_CH-P_CMDI • reg_no and
output (SCC_CH_B~CMDI • value,
O~H,
end wrb,
init'SCC$B: procedure,
2
call wrb(09. 01000000bl,
1* channel B re"et *1
292010-68
186/586 High Integration Board Initialization Routine (Continued)
1-334
AP-274
36
37
38
39
40
41
42
43
44
2
2
.
:I
2
2
2
2
2
4'
46
2
47
2
2
c"ll
call
call
c"ll
call
call
call
call
c.tl
..,.bI04. 01001110b) •
w.,.b(03, 11000000b) ,
.... bI05. OIIOOOOOb) •
..,.bIIO. OOOOOOOOb ) •
..,.bl II. OIOIOIIOb) •
..,.bI12. OOOOIOllb),
..,.bI13. OOOOOOOOb ) •
.... b Cl4. OOOOOOllb) •
..,.bCl5. OOOOOOOOb ) •
c .. 11 .,rbI03. 1l000001b),
c .. 11 .,,.bIO'. 1I101010b ),
1* 2 stop. no p.. ,.ity. b,.f • 16. *1
1* ,.. 8 bits/ch .. r. no .. uto-en .. bh *1
1* t. 8 bits/ch.,. *1
1* I"XC = txc • BRC:. t1"IC
1* baud rate • 9600 *1
s
BRC: out *1
1* BRQ .0U,.c • • SYS ClK. .nabh BRC: *1
/* .. 11 ext .t .. tu • int.,.rupts off *1
/* .cc-b l"eceiv• • nabl. *1
/*
scc-b transmit .n.bl., dtl' an, ,.t. on *1
end init.SCCSB.
48
= 0,
49
51
3
2
52
2
53
54
I
2
5'
57
3
2
'8
2
.nd c.out.
'9
60
I
2
,. ... d: p,.oc.du,.. I.il •• id • •s,.ptr. count ... ctu .. l.pt,.. st .. tu •• ptr) public,
d.cl",.. fil •• id wo,.d.
ms,.pt,. paint",..
do Whil. IInputISCC_CH_B_C"D) .. nd I)
,..tu,.n (inputISCC_CH-B-PATA)),
and.
c.out: p,.oc.du,.. Ich .. ,.) public;
d.cl ..,.. ch .. ,. byt ••
do .. hile (lnputISCC_CH_B_C"D) .. nd 4) = O. end,
outputISCC_CH_B-PATA) • ch .. ,.,
count lIIIord,
.. ctu .. l.ptr point",. •
• t"tu •• pt,. point.r •
•• , b.... d m.g.pt,. II) byt ••
bu' (200) byte •
.. ctu.. l b.... d .. ctu .. l.ptr .,o,.d.
st.. tus b.... d .t .. tu •• pt,. wo,.d.
i lIIord,
ch byte.
1* This p,.oc.du,.. lmpl" •• nts the ISIS ,. •• d p,.oc.du,. •. All control ch .. ,..ct.,.. *1
1* .IC.pt LF. BS... nd DEL .,.. igno,."d.' I f BS or DEL is encount",..d. "
*1
1* b"cksp"c" is don".
*1
61
62
63
64
6'
66
2
2
2
3
3
3
st.tu • • 0,
i, ch - OJ
do .. hil. (ch <> CR) .. nd (ch <> IF) .. nd (i < 198).
ch • c.in .. nd 07FH.
if (ch • BS) 0,. (ch • DEL) then
do;
292010-69
186/586 High Integration Board Initialization Routine (Continued)
1-335
inter
AP·274
4
4
67
68
69
70
71
72
73
74
75
76
5
5
5
4
77
78
4
3
79
80
81
82
83
84
3
4
4
4
4
3
85
86
87
88
89
90
3
4
4
4
4
3
91
92
93
95
96
97
98
3
2
2
2
2
3
3
99
2
if i
:> 0 then
do)
5
i = i-II
5
5
5
call
call
call
call
call
cSout(OEL»)
cSout(BS»)
cSout(SP),
cSout(OEL),
cSout (BS),
end,;
else
call cSout(BEL),
end;
else
if ch :>- SP then
do;
call cSout(ch);
buf(i) :t= Chi
i = i + 1;
end;
else
=
if (ch
CR) or (ch
do;
buf(i) = CR,
buf(i + 1)
LF,
== i + 2;
= LF)
then
=
end;
else
call cSout(BELl,
100
endJ
call cSout(CR),
if i :> count then i
actual == ii
do i == 0 to actual msg(i) = buf(i),
= count)
1;
end;
end read;
csts:
procedure b"te public,
101
2
102
2
end cst.;
103
104
1
2
write: pT'oceduT'e (fil.Sid, msgSptr, count,
declare (fileSid, count) word,
(msgSpt1', statusSptr) po inter,
msg based msg$ptr (1) bvte.
status based statusSptr word,
ch b"te,
i word,
105
2
statusSptr) publIC,
1* This procedure implements the ISIS write *1
status = OJ
292010-70
186/586 High Integration Board Initialization Routine (Continued)
t-336
AP-274
106
107
:2
:2
lOB
3
109
3
110
111
3
3
else
11:2
113
3
3
i
114
1
~
01
do while
1
< count,
ch - msgCi),
if Ilch >- SPI and Ich < DELlI Dr Ich
then
call cSoutlch I,
-
z
CRI Dr Ich
LFI Dr Cch = NUL)
call cSoutlGMI,
i + 1,
end,
end ",rit.,
115
SIF EPROM27UIB
outputlUMCS_regl - OF03BH,
1* Starting Addross - OFGOOOH.
no w.it .t.te *1
SELSE
1* Starting Address - OEOOOOH.
no ",ait stat. *1
SENDIF
117
outputlLMCS_ragl - 03FCH,
DutputlPACS_regl - OB3CH,
liB
outputlMPCS_regl - OBFH,
119
call initSintSclt,
call inUSSCCSB,
go to main,
116
120
121
122
1* 16K.
no ",ait state *1
1* PBA • BOOOH. no ",.it stata for
PSCO-3 81
1* Peripherals in 110 space. nD Al & A2
provided. 3 ",ait states for PSC4-6 *1
end inUB6,
292010-71
188/586 High Integration Board Initialization Routine (Continued)
1-337
AP-274
APPENDIX C
THE 82530 SCC - 80186 INTERFACE AP BRIEF
INTRODUCTION
INTERFACE OVERVIEW
The object of this document is to give the 82530 system
designeF an in-depth worst case design analysis of the
typical interface to a 80186 based system. This document has been revised to include the new specifications
for the 6 MHz 82530. The new specifications yield better margins and a I wait state interface to the CPU (2
wait states are required for DMA cycles). These new
specifications will appear in the 1987 data sheet and
advanced specification information can be obtained
from your local Intel sales office. The following analysis includes a discussion of how the interface TTL is
utilized to meet the timing requirements of the 80186
and the 82530. In addition, several optional interface
configurations are also considered.
The 82530 - 80186 interface requires the TTL circuitry
illustrated in Figure 1. Using five 14 pin TTL packages,
74LS74, 74AS74, 74AS08, 74AS04, and 74LS32, the
following operational modes are supported:
•
•
•
•
•
Polled
Interrupt in vectored mode
Interrupt in non-vectored mode
Half-duplex DMA on both channels
Full-duplex DMA on channel A
A brief description of the interface functional requirements during the five possible BUS operations follows
below.
DATA (D7-De)
82538
15
13
,.
=
lffiI1:li
TXDA
RXDA
§Vm!
1!I'!A
"ERA
~
~
TXDJ
OND
31
"§VRO
1!'ffJ
,1REQ!
IRES!
,.
,.
li'l'l!7'I!RW
RXDB
Jmm"
=
=
vee
A
19
2.
27
2.
2.
2'
2.
22
21
2.
'I'1UreI
ctfAHHEL
12
11
17
•
~EL
B
+50
H--1£9
HOTES
DRQl
H - PULLED HIGH THROUGH SK OHM
Ul - ?4LS14
U2 - 74ASB8
US -
INn
DRQ0
74AS04
U4 - ?"ASi''''
us - ,.04LSS2
"
?4I1se ..
~'L'
________________________
~
u.
292010-72
Figure 1.82530-80186 Interface
1-338
inter
AP·274
12SHSt'l8
CLKOUT
AD .....
DTt'1f
ALE
88186
1m
1IrFI
~
1m
.#".
825911
DATA
16*6 96"1 )::::::: .. :::::::
292010-73
Figure 2. 80186-82530 Interface Read Cycle
UHITS: 125
HS~18
CLKOUT
ADe-."
88186
ALE
Q1f
R1'I
n1'
ADDRESS
82598
DATA
292010-74
Figure 3. 80186-82530 Interface Write Cycle
READ CYCLE: The 80186 read cycle requirements are
met without any additional logic, Figure 2. At least one
wait state is required to meet the 82530 tAD access
time.
is inverted to assure that WR is active low before the D
Flip-Flop is clocked. No wait states are necessary to
meet the 82530's WR cycle requirements, but one is
assumed from the RD cycle.
WRITE CYCLE: The 82530 requires that data must be
valid while the WR pulse-is low,§Ure 3.A D FlipFlop delays the leading edge of WR until the falling
edge of CLOCKOUT when data is guaranteed valid
and WR is guaranteed active. The CLOCKOUT signal
INTA CYCLE: During an interrupt acknowledge cycle, the 80186 provides two INTA pulses, one per bus
cycle, separated by two idle states. The 82530 expects
only one long INTA ~se with a RD pulse occurring
only after the 82530 lEI/lEO daisy chain settles. As
1-339
inter
AP-274
UNITS: 125 NS/12
CLI Iii (-0.4 rnA + -0.5 rnA)
>
lih (20 /J-A
+
20/J-A)
PCS5: The PCS5 signal drives U2 and U4.
• 101 (2.0 rnA)
loh (-400 /J-A)
> iii (-0.5 rnA + -0.5 rnA)
> lih (20 /J-A + 20/J-A)
Certain symbolic conventions are adhered to throughout the analysis below and are introduced for clarity.
1. All timing variables with a lower case first letter are
82530 timing requirements or responses (i.e., tRR).
2. All timing variables with Upper case first letters are
80186 timing responses or requirements unless preceded by another device's alpha-numeric code (i.e.,
Tclel or '373 Tpd).
3. In ~ writ~cle analysis, the timing variable
TpdWR186-WR530 represents the propagation delay between the leading or traili~dge of the WR
signalleav~the 80186 and the WR edge arrival at
the 82530 WR input.
Read Cycle
INTA: The INTA signal drives 2(Ul) and U5.
• 101 (2.0 rnA) > iii (-0.4 rnA + -0.8 rnA + -0.4 rnA)
loh (-400 /J-A) > lih (20 /J-A + 40/J-A + 20/J-A)
All the 82530 I/O pins are TTL voltage level compatible.
1. tAR: Address valid to RD active set up time for the
82530. Since the propagation delay is the worst case
path in the assumed typical system, the margin is calculated only for a propagation delay constrained and not
an ALE limited path. The spec value is 0 ns minimum.
• 1 Tclcl - Tclav(max) - '245 Tpd(max)
2(U2) Tpd(min) - tAR(min)
= 125
1-341
- 55 - 20.8
+
10
+
2(2) - 0
+
Tclrl(min)
+
= 63.2 ns margin
* 3 Tclcl + 1(Tclclwait state) - Telav(max) - '373
Tpd(max) - '245 Tpd - Tdvel(min) - tAD
2. tRA: Address to RD inactive hold time. The ALE
delay is the worst case path and the 82530 requires 0 ns
minimum.
= 375
margin
* 1 Tclcl - Tclrh (max) + Tchlh(min) + '373 LE
+
125 - 55 - 20.8 -14.2 - 20 -325 = 65 ns
Tpd(min) - 2(U2) Tpd(max)
= 55 - 55
+
5
+
Write Cycle
8 - 2(5.5) = 2 ns margin
3. tCLR: CS active low to RD active low set up time.
The 82530 spec value is 0 ns minimum.
1. tAW: Address reqqired valid to WR active low set
up time. The 82530 spec is 0 ns minimum.
• 1 Tclcl - Telcsv(max) - Telrl(min) - U2
skew(AD - CS) + U2 Tpd(min)
* TelC! - Telav(max) - Tevctv(min) - '373 Tpd(max)
= 125 - 66 - 10 - 1
+
+ TpdWR186 - WR530(LOW) [Telel - Tcvctv(min)
U3 Tpd(min) + U4 Tpd(min)1 - tAW
2 = 50 ns margin
= 125 - 55 - 5 - 20.8
= 170.6 ns margin
4. tRCS: RD inactive to CS inactive hold time. The
82530 spec calls for 0 ns minimum.
* Tesesx(min) - U2 skew(AD -
= 55 - 55
margin
• 1 Tclcl + 1 Tchel - Tchcsx(max) + Tclrl(min) - U2
skew (AD - CS) + U2 Tpd(min) - tCHA
55 - 35 - 10 - 1
+
+
5
+
8 - [5.5
+
4.41 - 0
+
3
+
7.11 = -2.6 ns
1 Tclel - Tclesv(max) + Tevetv(min) - U2 Tpd(max)
TpdWR186=Vim530(LOW) [Telel - Tevetv(min) + U3
Tpd(min) + U4 Tpd(min)1
.
•
+
= 125 - 66 + 5 - 5.5
183.9 ns margin
* Trlrh(min) + 1(Tclclwait state) - 2(U2 skew) - tAR
+ 1(125)
1
3. tCLW: Chip select active low to WR active low hold
time. The 82530 spec is 0 ns.
2 - 5 = 131 ns margin
6. tRR: RD pulse active low time. One 80186 wait state
is included to meet the 150 ns minimum timing requirements of the 82530.
= (250-50)
+
• Teleh(min) - Tcvetx(max) + Tehlh(min) + '373 LE
Tpd(min) - TpdWR186=WR530(HIGH) [U2 Tpd(max) +
U3 Tpd(max) + U4 Tpd(max)]
5. tCHR: CS inactive to RD active set up time. The
82530 requires 5 ns minimum.
+
[125 - 5
2. tWA: WR inactive to address invalid hold time. The
82530 spec is 0 ns.
CS) - U2 Tpd(max)
= 35 - 1 - 5.5 = 28.5 ns margin
= 125
+
+
-2(1) - 150 = 173 ns margin
7. tRDV: RD active low to data valid maximum delay
for 80186 read data set up time (Tdvcl = 20 ns). The
margin is calculated on the Propagation delay path
(worst case).
• 2 Tclcl + 1(Tclclwait state) - Tclrl(max) - Tdvcl(min)
- '245 Tpd(max) - 82530 tRDV(max) - 2(U2) Tpd(max)
+
[125 - 5
+
+
1
4.41 =
4. tWCS: WR invalid to Chip Select invalid hold time.
82530 spec is 0 ns.
* Texesx(min) - U2 Tpd(max) TpdWR186=WA530(HIGH) [U2 Tpd(max)
Tpd(max) + U4 Tpd(max)]
= 35
+
1.5 - [5.5
+
3
+
+
U3
7.1) = 20.9 ns margin
5. tCHW: Chip Select inactive high to WR active low
set up time. The 82530 spec is 5 ns.
= 2(125) + 1(125) - 70 - 20 - 14.2 - 105 - 2(5.5)
= 154 ns margin
8. tDF: RD inactive to data output float delay. The
margin is calculated to DEN active low of next cycle.
* 1 Telcl + Tehel(min) + Tevetv(min) - Tchcsx(max) U2 Tpd(max) + TpdWR186=WR530(LOW) [Telel Tevctv(min) + U3 Tpd(min) t U4 Tpd(min)1 - tCHW
* 2 Tclcl + Tclch(min) - Telrh(max)
2(U2) Tpd(max) - 82530 tDF(max)
= 125 + 55 + 5 - 35 - 5.5
5 = 264 ns margin
= 250
+
55 -55
+
+
Tchctv(min) -
10 - 11 - 70 = 179 ns margin
9. tAD: Address required valid to read data valid maximum delay. The 82530 spec value is. 325 ns maximqm.
+
[125 -5
+
1
+
4.41 -
6. tWW: WR active low pulse. 82530 requires a minimum of 60 ns from the falling to the rising edge of WR,
This includes one wait state.
1-342
intJ
AP-274
• Twlwh [2Tclcl - 40] + 1 (Tclclwait state) - TpdiiVFll
186-WR530(LOW) [Tclcl - Tcvctv(min) + U3 Tpd(max)
+ U4 Tpd(max)] + TpdiiVFl/186 = iiVFl/530(HIGH) [U2
Tpd(min) U3 Tpd(min) + U4 Tpd{min)) - tWW
should never exist. 82530 drivers should insure that at
least one CPU cycle separates INTA and WR or RD
cycles.
= 210 + 1(125) - [125 - 5 + 4.5 + 9.21 - [1.5 + 1
+ 3.2] - 60 = '135.6 ns margin
4. tWI: WR inactive high to INTA active low minimum hold time. The spec is 0 ns and the margin assumes CLK coincident with INTA.
7. tDW: Data valid to WR active low setup time. The
82530 spec requires 0 ns.
• Tcvctv(min) - Tcldv(max) - '245 Tpd(max) +
TpdWR186-iiVFl530(lDW) [Tclcl - Tcvctv(min) + U3
Tpd(min) + U4 Tpd(min)l
= 5 - 44 - 14.2 + 125 - 5 + 1.0 + 4.4
margin
• Tclcl - Tcvctx(max) - TpdWR186 - iiVFl530(HIGH)
[U3 Tpd(max) + U4 Tpd(max)l + Tcvctv(min) + U1
Tpd(min)
= 125 - 55 - [5.5 + 3 + 7.1] + 5 + 10
margin
= 12.2 ns
=
69.4 ns
8. tWD: Data valid to WR inactive high hold time. The
82530 requires a hold time of 0 ns.
5. tIR: INTA inactive high to RD active low minimum
setup time. This spec pertains only to 82530 RD cycles
and has a value of 55 ns. The margin is calculated in
the same manner as tIW.
• Tclch - skew {Tcvctx(max) + Tcvctx(min)l + '245
DE Tpd(min) - TpdWR186-WR530(HIGH) [U2 Tpd(max)
+ U3 Tpd(max) + U4 Tpd(max)l
6. tRI: RD inactive high to INTA active low minimum
hold time. The spec is 0 ns and the margin assumes
CLK coincident with INTA.
'
= 55 - 5 + 11.25 - [5.5 + 3.0 + 7.1]
margin
•
=
-50.6 ns
Tclcl - Tclrh(max) - 2 U2 Tpd{max) + Tcvctv(mln)
+ U1 Tpd(min)
= 125 - 55 - 2(5.5) + 5 + 10 = 74 ns margin
INTA Cycle:
1. tic: This 82530 spec implies that the INTA signal is
latched internally on the rising edge of CLK (82530).
Therefore the maximum delay between the 80186 asserting INTA active low or inactive high and the 82530
internally recognizing the new state of INTA is the
propagation delay through Ul plus the 82530 CLK period.
•
U1 Tpd(max) + 82530 ClK period
= 45 + 250 = 295ns
2. tCI: rising edge of CLK to INTA hold time. This
spec requires that the state of INTA remains constant
for lOOns after the rising edge of CLK. If this spec is
violated any change in the state of INTA may not be
internally latched in the 82530. tCI becomes critical at
the end of an INTA cycle when INTA goes inactive.
When calculating margins with tCI, an extra 82530
CLK period must be added to the INTA inactive delay.
3. tIW: INTA inactive high to WR active low minimum setup time. The spec pertains only to 82530 WR
cycle and has a value of 55 ns. The margin is calculated
assuming an 82530 \VR cycle occurs immediately after
an INTA cycle. Since the CPU cycles following an
82530 INTA cycle are devoted to locating and executing the proper interrupt service routine, this condition
7. tlID: INTA active low to RD active low minimum
setup time. This parameter is system dependent. For
any SCC in. the daisy chain, tHO must be greater than
the sum of tCEQ for the highest priority device in the
daisy chain, tEl for this particular SCC, and tEIEO for
each device separating them in the daisy chain. The
typical system with only 1 SCC requires tlID to be
greater than tCEQ. Since tEl occurs coincidently with
tCEQ and it is smaller it can be neglected. Additionally, tEIEO does not have any relevance to a system with
only one SCC. Therefore tlID > tCEQ = 250 ns.
• 4 Tclcl + 2 Tidle states - Tcvctv(max) - IIC [U1
Tp(j(max) + 82530 ClK period] + Tcvctv(min) + U5
Tpd(min) + U2 Tpd(min) - 1110
=
=
500 + 250 - 70 - [45 + 250] + 5 + 6 + 2 - 250
148 ns margin
8. tIDY: RD active low to interrupt vector valid delay.
The 80186 expects the interrupt vector to be valid on
the data bus a minimum of 20 ns before T4 of the second acknowledge cycle (Tdvcl). tIDY spec is 100 ns
maximum.
• 3 Tclcl - Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) - tIDV(max) - '245 Tpd(max) - Tdvcl(min)
= 375 - 70 - 25 - 5.5 - 100 - 14.2 - 20
ns margin
1-343
=
140.3
AP-274
9. tIl: RD pulse low time. The 82530 requires a minimum of 125 ns.
• 3 Tclcl - Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) + Tcvctx(min) + U5 Tpd(min) + U2 Tpd(min)
- til (min)
= 375 - 70 - 25 - 5.5
162 ns margin
+
5
+
6
+
1.5 - 125 =
'
• Tclcl + 2(Tclclwait state) - Tcvctv(min) TpdWFi186-WFi530(LOW) [Tclcl - Tcvctv(min)
Tpd(max) + U4 Tpd(max)1 - Tdrqcl - tWRI
DMACycle
Fortunately, the 80186 DMA controller emulates CPU
read and write cycle operation during DMA transfers.
The DMA transfer timings are satisfied using the above
analysis. Because of the 80186 DMA request input requirements, two wait states are necess~o prevent
inadvertent DMA cycles. There are also CPUDMA intracycle timing considerations that need to be addressed.
1. tDRD: RD inactive high to DTRREQ (REQUEST)
inactive high delay. Unlike the READYREQ signal,
DTRREQ does not immediately go inactive after the
requested DMA transfer begins. Instead, the DTRREQ
remains active for a maximum of 5 tCY + 300 ns. This
delayed request pulse could trigger a second DMA
transfer. To avoid this undesirable condition, a D Flip
Flop is implemented to reset the DTRREQ signal inactive low following the initiation of the requested DMA
transfer. To determine if back to back DMA transfers
are required in a source synchronized configuration,
the 80186 DMA controller samples the service request
line 25 ns before Tl of the deposit cycle, the second
cycle of the transfer.
•
3. tWRI: 82530 WR active low to REQ inactive high
delay. Assuming destination synchronized DMA transfers, the 80186 needs t'Yo wa~t states to meet the tWRI
spec. This is because the 80186 DMA controller samples requests two clocks before the end of the deposit
~e. This leaves only 1 Tclcl + n(wait states) minus
WR active delay for the 82530 to inactivate its REQ
signal.
4 Tclcl - Tclcsv(max) - U4Tpd(max) - Tdrqcl(min)
=375 - 5 - [125 - 5
11.3 ns margin
+
4.5
+
+ U3
9.21 - 25 - 200 =
NOTE:
If one wait state DMA interface is required, external
logic, like that used on the DTRREQ sigllal, can be
used to force the 82530 REQ signal inactive.
4. tREC: CLK recovery time. Due to the internal data
path, a recovery period is required between SCC bus
transactions to resolve metastable conditions internal to
the SCC. The DMA request lines are marked from requesting service until after the tREC has elapsed. In
addition, the CPU should not be allowed to violate this
recovery period when interleaving DMA transfers and
CPU bus cycles. Software drivers or external logic
should orchestrate the CPU and DMA controller operation to prevent tREC violation.
Reset Operation
During hardware reset, the system RESET signal is asserted high for a minimum of four 80186 clock cycles
(1000 ns). The 82530 requires WR and RD to be simul~
taneously asserted low for a minimum of 250 ns. '
= 500 - 66 - 10.5 - 25 = 398.5 ns margin
2. tRRI: 82530 RD active low to REQ inactive high
delay. Assuming source synchronized DMA transfer,
the 80186 requires only one wait state to meet the tRRI
spec of 200 ns. Two are included for consistency with
tWRI.
• 4 Tclcl - U3 Tpd(max) - 2(U2) Tpd(inax)
Tpd(min) - tREe
= 1000 - 17.5 - 2(5.5)
margin
• 2 Tclcl + 2(iclciwait state) - Tclrl(max) - 2(U2)
Tpd(maX) - Tdrqcl - tRRI'
=2(125)
margin
+
2(125) -' 70 - 2(5.5) - 200 = 219 ns
1-344
+
+
U4
3.5 - 250 ns = 725 ns
inter
APPLICATION
NOTE
AP-236
November 1986
Implementing StarLAN with
the Intel 82588
ADIGOLBERT
DATA COMMUNICATIONS OPERATION
SHARAD GANDHI
FIELD APPLICATIONS-EUROPE
Order Number: 231422-003
1-345
inter
AP-236
1.0 INTRODUCTION
Personal computers have become the most prolific
workstation in the office, serving a wide range of needs
such as word processing, spreadsheets, and data bases.
The need to interconnect PCs in a local environment
has clearly emerged, for purposes such as the sharing of
file, print, and communication servers; downline loading of files and application programs; electronic mail;
etc. Proliferation of the PC makes it the workstation of
choice for accessing the corporate mainframe/s; this
function can be performed much more efficiently and
economically when clusters of PCs are already interconnected through Local Area Networks (LANs). According to market surveys, the installed base of PCs in
business environments reached about 10 million units
year-end '85, with only a small fraction connected via
LANs. The installed base is expected to double by
1990. There is clearly a great need for locally interconnecting these machines; furthermore, end users expect
interconnectability across vendors. Thus, there is an urgent need for industry standards to promote cost effective PC LANs.
A large number of proprietary PC LANs have become
available for the office environment over the past several years. Many of these suffer from high installed cost,
technical deficiencies, non-conformance to industry
standards, and general lack of industry backing. StarLAN, in Intel's opinion, is one of the few networks
which will emerge as a standard. It utilizes a proven
network access method, it is implemented with proven
VLSI components; it is cost effective, easily installable
and reconfigurable; it is technically competent; and it
enjoys the backing of a large cross section of the industry which is collaborating to develop a standard (IEEE
802.3, type IBASE5).
1.1 StarLAN
StarLAN is a I Mb/s network based on the CSMA/
CD access method (Carrier Sense, Multiple Access
with Collision Detection). It works over standard,
unshielded, twisted pair telephone wiring. Typically,
the wiring connects each desk to a wiring closet in a
star topology (from which the IEEE Task Force working on the standard derived the name StarLAN in
1984). In fact, telephone and StarLAN wiring can coexist in the same twisted pair bundle connecting a desk to
the wiring closet. Abundant quantities of unused phone
wiring exist in most office environments, particularly in
the U.S. The StarLAN concept of wiring and networking concepts was originated by AT&T Information Systems.
tions needed for such networks. Besides inplementing
the standard CSMA/CD functions like framing, deferring, backing off and retrying on collisions, transmitting and receiving frames, it performs data encoding
and decoding in Manshester or NRZI format, carrier
sensing and collision detection, all up to a speed of 2
Mb/s (independent of the chosen encoding scheme).
These functions make it an optimum controller for a
StarLAN node. The 82588 has a very conventional microcomputer bus interface, easing the job of interfacing
it to any processor.
1.3 Organization of the Application
Note
This application note has two objectives. One is to describe StarLAN in practical terms to prospective implementers. The other is to illustrate designing with 82588,
particularly as related to StarLAN which is expected to
emerge as its largest application area.
Section 2 of this Application Note describes the StarLAN network, its basic components, collision detection, signal propagation and network parameters. Sections 3 and 4 describe the 82588 LAN controller and its
role in the StarLAN network. Section 5 goes into the
details of designing a StarLAN node for the IBM PC.
Section 6 describes the design of the HUB. Both these
designs have been implemented and operated in an actual StarLAN environment. Section 7 documents the
software used to drive the 82588. It gives the actual
procedures used to do operations like, configure, transmit and receive frames. It also shows how to use the
DMA controller and interrupt controller in the IBM
PC and goes into the details of doing I/O on the PC
using DOS calls. Appendix A shows oscilloscope traces
of the signals at various points in the network. Appendix B describes the multiple point extension (MPE) being considered by IEEE. Appendixes C and D talk
about advanced usages of the 82588; working with only
one DMA channel, and measuring network delays with
the 82588.
1.4 References
For additional information on the 82588, see the Intel
Microcommunications Handbook. StarLAN specification are currently available in draft standard form
through the IEEE 802.3 Working Group.
2.0 StarLAN
StarLAN is a low cost 1 Mb/s networking solution
aimed at office automation applications. It uses a star
1.2 The 82588
The 82588 is a single-chip LAN controller designed for
CSMA/CD networks. It integrates in one chip all func1-346
intJ
AP·236
topology with the nodes connected in a point-to-point
fashion to a central HUB. HUBs can be connected in a
hierarchical fashion. Up to 5 levels are supported. The
maximum distance between a node and the adjacent
HUB or between two adjacent HUBs is 800 ft. (about
250 meters) for 24 gauge wire and 600 ft. (about 200
meters) for 26 gauge wire. Maximum node-to-node distance with one HUB is 0.5 km, hence IEEE 802.3 designation of type lBASE5. 1 stands for 1 Mb/s and
BASE for baseband. (StarLAN doesn't preclude the use
of more than 800 ft wiring provided 6.5 dB maximum
attenuation is met, and cable propagation delay is no
more than 4 bit times).
One of the most attractive features of StarLAN is that
it uses telephone grade twisted pair wire for the transmission medium. In fact, existing installed telephone
wiring can also be used for StarLAN. Telephone wiring
is very economical to buy and install. Although use of
telephone wiring is an obvious advantage, for small
clusters of nodes, it is possible to work around the use
of building wiring.
Factors contributing to low cost are:
1) Use of telephone grade, unshielded, 24 or 26 gauge
twisted pair wire transmission media.
2) Installed base of redundant telephone wiring in most
buildings.
3) Buildings are designed for star topology wiring.
They have conduits leading to a central location.
4) Availability of low cost VLSI LAN controllers like
the 82588 for low cost applications and the 82586 for
high performance applications.
5) Off-the-shelf, Low cost RS-422, RS-485 drivers/receivers compatible with the StarLAN analog interface requirements.
2.1 StarLAN Topology
StarLAN, as the name suggests, uses a star topology.
The nodes are at the extremities of a star and the central point is called a HUB. There can be more than one
HUB in a network. The HUBs are connected in a hierarchical fashion resembling an inverted tree, as shown
in Figure 1, where nodes are shown as PCs. The HUB
at the base (at level 3) of the tree is called the Header
Hub (HHUB) and others are called Intermediate HUBs
(IHUB). It will become apparent, later in this section,
that topologically, this entire network of nodes and
HUBs is equivalent to one where all the nodes are connected to a single HUB. Also StarLAN doesn't limit
the number of nodes or HUBS at any given level.
2.1.1 TELEPHONE NETWORK
StarLAN is structured to run parallel to the telephone
network in a building. The telephone network has, in
fact, exactly the same star topology as StarLAN. Let us
now examine how the telephone system is typically laid
out in a building in the USA. Figure 2 shows how a
typical building is wired for telephones. 24 gauge
unshielded twisted pair wires emanate from a Wiring
Closet. The wires are in bundles of 25 or 50 pairs. The
bundle is called D' inside wiring (DIW). The wires in
these cables end up at modular telephone jacks in the
wall. The telephone set is either connected directly to
HUB LEVEL 1
231422-2
'Maximum of 5 HUB levels .
• pes or DTEs can connect directly at any level.
Figure 1. StarLAN Topology
1-347
inter
AP-236
the jack or through an extension cable. Each telephone
generally needs one twisted pair for voice and another
for auxilliary power. Thus, each modular jack has 2
twisted pairs (4 wires) connected to it. A 25 pair DIW
cable can thus be used for up to 12 telephone connections. In most buildings, not all pairs in the bundle are
used. Typically, a cable is used for only 4 to 8 telephone
connections. This practice is followed by telephone
companies because it is cheaper to install extra wires
initially, rather than retrofitting to expand the existing
number of connections. As a result, a lot of extra, unused wiring exists in a building. The stretch of cable
between the wiring closet and the telephone jack is typically less than 800 ft. (250 meters). In the wiring closet
the incoming wires from the telephones are routed to
another wiring closet, a PABX or to the central office
through an interconnect matrix. Thus, the wiring closet
is a concentration point in the telephone network.
There is also a redundancy of wires between the wiring
closets.
2.1.2 StarLAN AND THE TELEPHONE
NETWORK
StarLAN does not have to run on building wiring, but
the fact that it can significantly adds to its attractiveness. Figure 3 shows how StarLAN piggybacks on telephone wiring. Each node needs two twisted pair wires
to connect to the HUB. The unused wires in the 25 pair
DIW cables provide an electrical path to the wiring
closet, where the HUB is located. Note that the telephone and StarLAN are electrically isola:ted. They only
use the wires in the same bundle cable to connect to the
wiring closet. Within the wiring closet, StarLAN wires
connect to a HUB and telephone wires are routed to a
different path. Similar cable sharing can occur in connecting HUBs to one another. See Figure 4 for a typical
office wired for StarLAN through telephone wiring.
231422-3
Figure 2. Telephone Wiring In a Building
WIRING CLOSET
80.0 fl
"-
~2
" - - BUNDlES OF
25 - 50 PAIRS
TWISTED PAIRS
~
24 GAUGE, UNSHIELDED
231422-4
'StarLAN and telephones share the same bundle, but are electrically isolated.
'StarLAN uses the unused wires in existing bundles.
Figure 3. Coexistence of Telephone and StarLAN
1-348
AP-236
WIRING CLOSET
IHUB
WIRING CLOSET
ROOM
#
ROOM
#2
ROOM
#3
1
WIRING CLOSET
TELEPHONE
WIRES TO PBX
WIRING CLOSET
231422-5
Figure 4. A Typical Office Using Telephone Wiring for StarLAN
1·349
inter
AP-236
2.1.3 StarLAN AND Ethernet
St~rLAN and Ethernet are similar CSMAlCD networks. Since Ethernet has existed 'longer and is better
understood, a comparison of Ethernet with StarLAN is
worthwhile.
1. The data rate of Ethernet is lOMb/s and that of StarLAN is 1 Mb/s.
2. Ethernet uses a bus topology with each node connected to a coaxial cable bus via a 50 meter transceiver cable containing four shielded twisted pair
wires. StarLAN uses a star topology, with each node
connected to a central HUB by a point to point link
through two pairs of unshielded twisted pair wires.
3. Collision detection in Ethernet is done by the transceiver connected to the coaxial cable. Electrically, it
is done by sensing the energy level on the coax cable.
Collision detection in StarLAN is done in the HUB
by sensing activity on more than one input line connected to the HUB.
4. In Ethernet, the presence of collision is signalled by
the transceiver to the node by a special collision detect signal. In StarLAN, it is signalled by the HUB
using a special collision presence signal on the receive data line to the node.
5.: Ethernet cable segments are interconnected using repeaters in a non-hierarchical fashion so that the distance between any two nodes does not exceed 2.8
kilometers. In StarLAN, the maximum distance between any two nodes is 2.5 kilometers. This is
achieved by wiring a maximum of five levels of
HUBs in a hierarchical fashion.
2.2 Basic StarLAN Components
A StarLAN network has three basic components:
1. StarLAN node interface
2. StarLAN HUB
3. Cable
ETHERNET
231422-6
Figure 5. Ethernet and StarLAN Similarities
1-350
inter
AP-236
as a carrier sense signal. The differential signal from the
HUB is received using a zero-crossing RS-422 receiver.
Output of the receiver, qualified by the squelch circuit,
is fed to the RxD pin of the LAN controller. The RxD
signal provides three kinds of information:
1) Normal received data, when receiving the frame.
2) Collision information in the form of the collision
presence signal from the HUB.
3) Carrier sense information, indicating the beginning
and the end of frame. This is useful during transmit
and receive operations.
2.2.1 A StarLAN NODE INTERFACE
Figure 6 shows a typical StarLAN node interface. It
interfaces to a processor on the system side. The processor runs the networking software. The heart of the
node interface is the LAN controller which does the job
of receiving and transmitting the frames in adherence
to the IEEE 802.3 standard protocol. It maintains all
the timings-like the slot time, interframe spacing
etc.-required by the network. It performs the functions of framing, deferring, backing-off, collision detection which are necessary in a CSMA/CD network. It
also does Manchester encoding of data to be transmitted and clock separation-or decoding-of the Manchester encoded data that is received. These signals before going to the unshielded twist pair wire, may undergo pulse shaping (optional) pulse shaping basically
slows down the fall/rise times of the signal. The purpose of that is to diminish the effects of cross-talk and
radiation on adjacent pairs sharing the same bundle
(digital voice, Tl trunks, etc). The shaped signal is sent
on to the twisted pair wire through a pulse transformer
for DC isolation. The signals on the wire are thus differential, DC isolated from the node and almost sinusoidal (due to shaping and the capacitance of the wire).
NOTE:
Work done by the IEEE 802.3 committee has shown
that no slew rate control on the drivers is required.
Shaping by the transformer and the cable is sufficient
to avoid excessive EMI radiation and crosstalk.
The squelch circuit prevents idle line noise from affecting the receiver circuits in the LAN controller. The
squelch circuit has a 600 mv threshold for that purpose.
Also as part of the squelch circuitry an envelope detector is implemented. Its purpose is to generate an envelope of the transitions of the RXD line. Its output serve
2.2.2 StarLAN HUB
HUB is the point of concentration in StarLAN. All the
nodes transmit to the HUB and receive from the HUB.
Figure 7 shows an abstract representation of the HUB.
It has an upstream and a downstream signal processing
unit. The upstream unit has N signal inputs and 1 signal output. And the downstream unit has 1 input and
N output signals. The inputs to the upstream unit come
from the nodes or from the intermediate HUBs
(IHUBs) and its output goes to a higher level HUB.
The downstream unit is connected the other way
around; input from an upper level HUB and the outputs to nodes or lower level IHUBs. Physically each
input and output consist of one twisted pair wire carrying a differential signal. The downstream unit essentially just re-times the signal received at the input, and
sends it to all its outputs. The functions performed by
the upstream unit are:
1. Collision detection
2. Collision Presence signal generation
3. Signal Retiming
4. Jabber Function
5. Start of Idle protection timer
PULSE
TRANSFORMER
8 BIT BUS
82588
TxD
TELEPHONE
JACK
PULSE
SHAPING
. - _...... (OPTIONAL)
CONTROL
RxD
SYS ClK
SQUELCH
+
ENABLE
CIRCUITS
231422-7
Figure 6. 82588 Based StarLAN Node
1-351
inter
AP-236
the HUB ass.ociated with ,this functi.on and their .operati.on is described in secti.on 6.
The last functi.on implemented by the HUB is the start
of Idle pr.ot~ction timer. During the end .of recepti.on,
the HUB wIll see a l.ong undersh.o.ot at its input P.ort.
This undersh.o.ot is a consequence .of the transf.ormer
discharging accumulated charge during the 2 microseconds .of high .of the idle pattern. The HUB sh.ould implement a protecti.on mechanism t.o av.oid the undesirable effects .of that undersh.o.ot.
231422-8
Figure 7. A StarLAN HUB
The c.o!Ii~i.on detect!.on in the HUB is d.one by sensing
t~~ actIvIty .on the Inputs. If there is activity (.or translttons) .on m.ore than .one input, it is assumed that m.ore
than .one node is transmitting. This is a c.olIisi.on. If a
c.olIisi.on is detected, a special signal called the C.olIisi.on
Presence Signal is generated. This signal is generated
and sent .out as l.ong as activity is sensed .on any .of the
input lines. This signal is interpreted by every n.ode as
an occurrence .of c.ollisi.on. If there is activity .only .on
.one input, tha.~ signal is re-timed-or cleaned up .of any
accumulated Jltter~and sent .out. Figure 8 sh.oWS the
input.to .output relati.ons .of the HUB as a black b.ox.
If a n.ode transmits f.or t.o.o l.ong the HUB exercises a
functi.on t.o disable the n.ode fr.om interfering
wIth traffic fr.om .other nodes. There are tW.o timers in
J~bber,
IDLE
IDLE
IDLE
VALID
MANCHESTER
Figure 9 sh.oWS a bl.ock diagram .of the HUB. A switch
positi.on determines whether the HUB is an IHUB .or a
HHUB (Header HUB). If the HUB is an IHUB the
switch dec.ouples the upstream and the d.ownst;eam
units. H!iUB is the highest level HUB; it has n.o place
t.o send Its .output signal, S.o it returns its .output signal
(through the switch) t.o the .outputs .of the d.ownstream
unit. There is .one and .only .one HHUB in a StarLAN
netw.ork and it is always at the base .of the tree. The
returned signal eventually reaches every n.ode in the
netw.ork thr.ough the intermediate n.odes (if any). StarLAN specificati.ons d.o n.ot put any restricti.ons .on the
number .of IHUBS at any level .or .on number .of inputs
t.o any HUB. The number .of inputs per HUB are typically 6 t.o 12 and is dictated by the typical size .of clusters in a given netw.orking environment.
COLLISION PRESENCE
IDLE
IDLE
VALID MANCHESTER
IDLE
VALID MANCHESTER
IDLE
VALID MANCHESTER
COLLISION PRESENCE
IDLE
IDLE
COLLISION
PRESENCE
IDLE
COLLISION
PRESENCE
COLLISION
PRESENCE
VALID MANCHESTER
231422-9
Figure S.HUB as a Black Box
1-352
intJ
AP-236
TRANSMIT PAIR /I 1
:JII
+
TO HIGHER
LEVEL HUB
JABBER
+
TRANSMIT PAIR /I N
RECEIVE PAIR
PROTECTION
TIMER
II 1
HHUB
~II
~II
RECEIVE PAIR
II N
231422-10
Figure 9. StarLAN HUB Block Diagram
2.2.3 StarLAN CABLE
Unshielded telephone grade twisted pair wires are used
to connect a node to a HUB or to connect two HUBs.
This is one of the cheapest types of wire and an important factor in bringing down the cost of StarLAN.
Although the 24 gauge wire is used for long stretches,
the actual connection between the node and the telephone jack in the wall is done using extension cable,
just like connecting a telephone to a jack. For very
short Star LAN configurations, where all the nodes and
the HUB are in the same room, the extension cable
with plugs at both ends may itself be sufficient for all
the wiring. (Extension cables must be of the twisted
pair kind, no flat cables are allowed).
The telephone twisted pair wire of 24 gauge has the
following characteristics:
Attenuation
DC Resistance
Inductance
Capacitance
Impedance
: 42.55 db/mile @ I MHz
: 823.69 o./mile
: 0.84 mH/mile
0.1 p.F/mile
: 92.60., -4 degrees @ 1 MHz
Experiments have shown that the sharing of the telephone cable with other voice and data services does not
cause any mutual harm due to cross-talk and radiation,
provided every service meets the FCC limits.
Although it is outside the scope of the IEEE 802.3
lBASE5 standard, there is considerable interest in using fiber optics and coaxial cable for node to HUB or
HUB to HUB links especially in noisy and factory environments. Both these types of cables are particularly
suited for point-to-point connections. Even mixing of
different types of cables is possible (this kind of environments are not precluded).
NOTE:
StarLAN IEEE 802.3 IBASE5 draft calls for a maximum attenuation of 6.5 dB between the transmitter
and the corresponding receiver at all frequencies between 500 KHz to I MHz. Also the maximum allowed cable propagation delay is 4 microseconds.
2.3 Framing
Figure 10 shows the format of a 802.3 frame. The beginning of the frame is marked by the carrier going
active and the end marked by carrier going inactive.
The preamble has a 56 bit sequence of 101010 ....
ending in a O. This is followed by 8 bits of start of frame
delimiter (sfd) - 10101011. These bits are transmitted
with the MSB (leftmost bit) transmitted first. Source
and destination fields are 6 bytes long. The first byte is
the least significant byte. These fields are transmitted
with LSB first. The length field is 2 bytes long and gives
the length of data in the Information field. The entire
information field is a minimum of 46 bytes and a maximum of I SOO bytes. If the data content of the Informa-
1-353
inter
AP-236
tion field is less than 46, padding bytes are used to
make the field 46 bytes long. The Length field indicates
how much real data is in the Information field. The last
32 bits of the frame is the Frame Check Sequence
(FCS) and contains the CRC for the frame. The CRC is
calculated from the beginning of the destination address to the end of the Information field. The generating polynomial (Autodin II) used for CRC is:
The frames can be directed to a specific node (LSB of
address must be 0), to a group of nodes (multicast or
group-LSB of address must be 1) or all nodes (broad~
cast-all address bits must be 1).
2.4 Signal Propagation and Collision
Figure 11 will be used to illustrate three typical situations in a StarLAN with two IHUBs and one HHUB.
Nodes A and B are connected to HUBl, nodes C and D
to HUB2 and node E to HUB3.
+ X26 + X23 + X22 + X16 + X12 + Xll +
Xl0 + X8 + X7 + X5 + X4 + X2 + X + 1
X32
No need for Figure N.
CARRIER OFF
CARRIER ON
+PREA~BLE
7
I
I
~AX=1500
1
6
6
~IN
2
I SFO I OA I SA I LEN
= 46
IINFOR~ATION
4 ...
I FCS
I
t-ol·>----FRA~E LENGTH--I
~AX
~IN
=1518
= 64
SFD = Start of Frame Delimiter
DA = Destination Address
SA = Source Address
LEN = Length
FCS = Frame Check Sequence
All numbers indicate field length In octets.
Figure 10. Framing
1-354
231422-11
inter
AP-236
231422-12
Situation # 1. A Transmitting
231422-13
Situation # 2. A & B Transmitting
231422-14
Situation # 3. A, B & C Transmitting
HUBI. HUB,2 are IHUBs
HUB3 is the HHUB
Fa. Fb. Fe-Frames from nodes A. B & C
Fx-Colilsion Presence Signal
Figure 11. Signal Propagation and Collisions
1-355
inter
AP-236
Backoff method ........ Truncated binary exponential
Encoding ............................ Manchester
2.4.1 Situation # 1
Whenever node A transmits a frame Fa, it will reach
HUBl. If node B is silent, there is no collision. 'HUBI
will send Fa to HUB3 after re-timing the signal. If
nodes C, D and E are also silent, there is no collision at
HUB2 or HUB3. Since HUB3 is the HHUB, it sends
the frame Fa to HUBl, HUB2 and to node E after retiming. HUBI and HUB2 send the frame Fa to nodes
A, B and C, D. Thus, Fa reaches all the nodes on the
network including the originator node A. If the signal
received by node A is a valid Manchester signal and not
the Collision Presence Signal (CPS) for the entire duration of the slot time, then the node A assumes that it
was a successful transmission.
2.4.2 Situation # 2
If both nodes A and B were to transmit, HUBI will
detect it as a collision and will send signal Fx (the Collision Presence Signal) to the HUB3-Note that HUBI
does not send Fx to nodes A and B yet. 'HUB 3 receives
a signal from HUBI but nothing from node E or
HUB2, thus it does not detect the situation as a collision and simply re-times the signal Fx and sends it to
node E, HUB2 and HUB1. Fx ultimately reach all the
nodes. Nodes A and B detect this signal as CPS and
call it a collision.
Clock tolerance ................ ± 0.01 % (100 ppm)
Maximum jitter per segment .............. ± 62.5 ns
3.0 LAN CONTROLLER FOR StarLAN
One of the attractive features of StarLAN is the availability of the 82588, a VLSI LAN controller, designed
to meet the needs of a StarLAN node. The main requirements of a StarLAN node controller are:
1. IEEE 802.3 compatible CSMA/CD controller.
2. Configurable to StarLAN network and system parameters.
3. Generation of all necessary clocks and timings.
4. Manchester data encoding and decoding.
5. Detection of the Collision Presence Signal.
6. Carrier Sensing.
7. Squelch or bad signal filtering.
8. Fast and easy interface to the processor.
82588 performs all these functions in silicon, providing
a minimal hardware interface between the system processor and the StarLAN physical link. It also reduces
the software needed to run the node, since a lot offunctions, like deferring, back off, counting the number of
collisions etc., are done in silicon.
2.4.3 Situation # 3
In addition to nodes A and B, if node C were also to
transmit, the situation at HUBI will be the same as in
situation #2. HUB2 will propagate Fc from C towards
HUB3. HUB3 now sees two of its inputs active and
hence generates its own Fx signal and sends it towards
each node.
These situations should also illustrate the point made
earlier in the chapter that, the StarLAN network, with
nodes connected to mUltiple HUBs is, logically, equivalent to all the nodes connected to a single HUB (Yet
there are some differences between stations connected
at different HUB levels, those are due to different delays to the header hub HHUB).
3.1 IEEE 802.3 Compatibility
The CSMA/CD control unit on the 82588 performs the
functions of deferring, maintaining the Interframe
Space (IFS) timing, reacting to collision by generating a
jam pattern, calculating the back-off time based on the
number of collisions and a random number, decoding
the address of the incoming frame, discarding a frame
that is too short, etc. All these are performed by the
82588 in accordance to the IEEE 802.3 standards. For
inter-operability of different nodes on the StarLAN network it is very important to have the controllers strictly
adhere to the same standards.
3.2 Configurability of the 82588
2.5 StarLAN System and Network
Parameters
Preamble length (incl. sfd) ........ , ......... 64 bits
Address length ............................ 6 bytes
Fes length CRC (Autodin II) ............... 32 bits
Maximum frame length ................. 1518 bytes
Minimum frame length .................... 64 bytes
Slot time ............................ 512 bit times
Interframe spacing ..................... 96 bit times
Minimum jam timing .................. 32 bit times
Maximum number of collisions .................. 16
Backoff limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 10
Almost all the networking parameters are programmable over a wide range. This means that the StarLAN
parameters form a subset of the total potential of the
82588. This is a major advantage for networks whose
standards are being defined arid are in a flux. It is also
an advantage when carrying over the experience gained
with the component in one network to other applications, with differing parameters (leveraging the design).
The 82588 is initialized or configured to its working
environment by the CONFIGURE command. After
the execution of this command, the 82588 knows its
system and network parameters. A configure block in
1-356
AP·2S6
memory is loaded into the 82588 by DMA. This block
contains all the parameters to be programmed as shown
in Figure 12. Following is a partial list Of the parameters with the programmable range and the StarLAN
value:
StarLAN
Parameter
Range
Value
Preamble length 2,4, 8, 16 bytes
8
Address length
o to 6 bytes
6
CRCtype
16,32 bit
32
Minimum frame
length
6 to 255 bytes
64
Interframe
spacing
12 to 255 bit times
96
Slot time
1 to 2047 bit times
512
Number of
retries
o to 15
15
StarLAN
Value
Parameter
Range
Data encoding
NRZI, Man.,
Diff. Man.
Code vio!.,
Bitcomp.
Collision
detection
Manch.
Code Vio!.
Beside these, there are many other options available,
which mayor may not apply to StarLAN:
Data sampling rate of 8 or 16
Operating in Promiscuous mode
Reception of Broadcast frames
Internalloopback operation
Externalloopback operation
Transmit without CRC
HDLC Framing
BIT
BYTE
7
o
5
6
4
I
I
I
I
I
I
I
I
o
2
3
I
I
BYTE COUNT (L.S.B)
I
I
I
I
I
I
I BYTE
I
COU~T (~.S.B) I
. I
2
CHNG
SERIAL
S~PLG
~ODE
RATE
FIFO
4
5
PREA~ LEN
INT
LP.BCK
BOF
~ETD
i
I
I~TER
6
i
I
NO SRC
ADD INS
P~IO
EXP
1
1
I
I
~
-I
RETRY NU~BER
I
1
i
I LIN PRIO 1
I
I
I
I
FRA~E
I'
1
I
/~AN
SPACING
i
. 1
I
1 ADD LEN 1
DIF.~AN
I
I
1
i
i
EXT
LP.BCK
ILI~IT
I
I
LENGTH
BUFFER
3
I
I
OSC
RANGE
I
1
I
I
1
1
SLOT TI~E (L)
7
8
9
PAD
10
CDT
SRC
BIT
STUFF
I
11
I
I
NCRC
INS
I
~AN
TON
NCRS
FRA~E
CON FIG
PR~
CRSF
I
I
BC
DIS
/NRZ·
CRS .
SRC
CDT~:J .
~:NI~U~
1
_I
SLOT TI~E (H)
. CDBBC
CRC16
I
I
I
I
I
I
I
I
I
LENGTH
i
I
PARA~ETER FOR~AT
231422-15
Figure 12. Configuration Block
1.357
inter
AP-236
time, Back off time, Number of collisions, Minimum
frame length, etc. These timers are started and stopped
automatically by the 82588.
3.3 Clocks and Timers
The 82588 requires two clocks; one for the operation of
the system interface and another for the serial side.
Both clocks are totally asynchronous to each other.
This permits transmitting and receiving frames at data
rates that are virtually independent of the speed at
which the system interface operates.
3.4 Manchester Data Encoding and
Decoding .
In StarLAN the data transmitted by the node must be
encoded in Manchester format. The node should also
be able to decode Manchester encoded data when re~
ceiving a frame-a process also known as clock recovery. The 82588 does the encoding and decoding of data
bits on chip for data rates up to 2 Mb/s.
The serial clock can be generated on chip using just an
external crystal of a value 8 or 16 times the desired bit
rate. An external clock may also be used.
The 82588 has a set of timers to Illaintain various timings necessary to run the CSMA/CD control unit.
These are timings for the Slot time, Interframe spacing
DATA
I
1
I0 I
1
Besides Manchester, the 82588 can also do encoding
and decoding in NRZI and Differential Manchester
formats. Figure 13 shows sll:mples of encoding in
I
1
I0 I
1
I
0
I0 I
0
I
1
I
NRZ
NRZI
MANCHESTER
DIFFERENTIAL
MANCHESTER
Encoding
Method
231422-16
Mid Bit Cell
Transitions
Bit Cell Boundary
Transitions
NRZ
Do not exist.
Identical to original data.
NRZI
Do not exist.
Exist only if original data
bit equals o.
Dependent on present
encoded signal level:
to 0 if 1
to 1 if 0
Manchester
Exist for every bit of
the original data:
from O. to 1 for 1
from 1 t() 0 for 0
Exist for consequent equal
bits· of original data:
.from 1 to 0 for 1 1
fromOt01 forOO
Differential
Manchester
Exist for every bit of
the. original.data.
Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0
Exist only if original data
bit equlllis o.
Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0
Figure 13.82588 Data Encoding Rules
1-358
inter
AP-236
these three formats. The main advantage of NRZI over
the other two is that NRZI requires half the channel
bandwidth, for any given data rate. On the other hand,
since the NRZI signal does not have as many transitions as the other two, clock recovery from it is more
difficult. The main advantage of Differential Manchester over straight Manchester is that for a signal that is
differentially driven (as in RS 422), crossing of the two
wires carrying the data does not change the data received at the receiver. In other wotds, NRZI and Differential Manchester encoding methods are polarity insensitive (Even though NRZI, Differential Manchester
are polarity instrnsitive, the 82588. expects a high lev~l
in the RXD line to detect camerinactive at the end of
. .
frames).
periodic intervals. When the 82588 decodes this signal,
it fails to see mid-cell transitions repeatedly at intervals
of2.5 bit times and hence calls it a code violation. The
edges of CPS are marked for illustration as a, b, c,
d, ... I. Let us see how the 82588 interprets the signal if
it starts calling the edge 'a' as the mid-cell transition for
'1'. Then edge at 'b' is '0'. Now the 81588 expects to see
an edge at '*' but since there is none, it is a Manchester
code violation. The edge that eventually does occur at
'd' is then used to re-synchronize and, since it is a falling edge, it is taken as a mid-cell transition for '0'. The
edge at 'e' is for a '1' and then again there is no edge at
'*'. This goes on, with the 82588 flagging code violation
and re-synchronizing again every 2.5 bit times. When a
transmitting node sees this CPS signal being returned
by the HUB (instead of a valid Manchester signal it
transmitted), it assumes that a collision occurred. The
82588 has two built-in mechanisms to detect collisions.
These mechanisms are very general and can be used for
a very broad class of applications to detect collisions in
a CSMAlCD network. Using these mechanisms, the
82588 can detect collisions (two or more nodes transmitting simultaneously) by just receiving the collided
signal during transmission, even if there was no HUB
generating the CPS signal.
3.5 Detection of the Collision
Presence Signal
In a StarLAN network, HUB informs the nodes that a
collision has occurred by sending the Collision Presence Signal (CPS) to the nodes. The CPS signal is a
special signal which contains v~olations in Manchester
encoding. Figure 14 shows the CPS signal. It has a 5 ms
period, looking very much like a valid Manchester signal except for missing transitions (or violations) at
J
ENCODING
I0 I
I
I
0
K
I
J
I0 I
0
I
K
I
J
I
CPS
EDGES:
r--:5~s
a
d
b c
PERIOD--j
I 2t I t I
e f
k
h
9
t=O.5~s
• MISSING MID-CELL TRANSITION
82588
DECODING
1
0
•
JLJL.
abc
d
o
1
LrLI
d
e f
9
1
0
•
JLJL.
J
k
m
o
*
LrLI
)
kim
Figure 14. 82588 Decoding the Collision Presence Signal
1-359
231422-17
intJ
AP-236
Collision also if:
RxD stays low for 25 samples or more
A mid cell transition is. missing
3.5.1 COLLISION DETECTION BY CODE
VIOLATION
If during transmissiori, the 82588 sees a violation in the
encoding (Manchester, NRZI or Differential Manchester) used, then it calls it a collision by aborting the
transmission and transmitting a 32 bit jam pattern. The
algorithm used to detect collisions,and to do the data
decoding, is based on finding the number ·of sampling
clocks between an edge to the next one. Suppose art
edge occurred at time 0, the sampling instant of the
next 'edge determines whether it was a collision (C), a
long pulse (L)-with a nominal width of 1 bit time-,or
a short pulse (S)-nominal width of half a bit time. The
following two charts show the decoding and collision
detection algorithm for sampling rates of 8 and 16
when using Manchester encoding. The numbers at the
bottom of the line indicate sampling instances after the
ocCurrence of the last edge (at 0). The alphabets on the
top show what would be inferred by the 82588 if the
next edge were to be there.
.Sampling rate = 8 (clock is 8x bit rate)
C
C
S
S
S
L
L
L L L C C
I I I I I I I I I I I I
0
2
3
4
5
6
7
8
9 10 11 12 13
Collision also if:
RxD stays low for 13 samples or more
A mid cell transition is missing
Sampling rate = 16 (clock is 16x' bit rate)
CCCCCSSSSSCLLLLLLLLLCCCC
A single instance of code violation can qualify as collision. The 82588 has a parameter called collision detect
filter (COT Filter) that can be configured from 0 to 7.
This parameter determines for how many bit times the
violation must-remain active to be flagged as·a collision.
For StarLAN CDT Filter must be configured to 0that is disabled.
3'.5.2 COLLISION' DETECTION BY SIGNATURE
(OR IT) COMPARISON
a
This method of collision detection compares a signature
of the transmitted data with that of the data received on
the RxD pin while transmitting. Figure IS .shows a
block diagram of the logic. As the frame is tranSmitted
it flows through the CR,C generation logic. A timer,
called the Tx slot timer, is"started at the same time that
the CRC generation starts. When the count in the timer
reaches the slot time value, the current value of the
CRC generl!:tor is latcl1ed in as the transmit signature.
As the frame is returned back (through the HUB) it
flows through the CRC checker. Another timer-'-Rx
slot timer-is started at the same time as the CRC
checker starts checking. When this timer reaches the
slot time value, the current value of the CRC checker is
latched in as the receive signature. If the received signa"
ture matches the transmitted one, then it is assumed
that there was no collision. Whereas, if the signatures
do not match, a collision is assumed to have occurred.
111111111111111111111111111
o
2
4
6
8
10 12 14 16 18 20 22 24 26
TRANSMITTED _ _-+I
FRAME
Tx SLOT
TIMER
TX CRC
1---+ TRANSMIT CHANNEL
TX SIGNATURE
LATCH
COMPARE"
Rx SLOT
TIMER
RECEIVED
FRAME
RX SIGNATURE
LATCH
RX CRC
RECEIVE CHANNEL
• MATCH = NO COLLISION
NO MATCH = COLLISION
Figure 15. Collision Detection by Signature Comparison
1-360
231422-18
inter
AP-236
b) Half a slot time + 16 bit times elapse and the opening flag (sfd) is not detected.
c) Carrier sense goes inactive after an opening flag is
received with transmitter still active.
Note that, even if the collision were to occur in the first
few bits of the frame, a slot time must elapse before it is
detected. In the code violation method, collision is detected within a few bit times. However, since the signature method compares the signatures, which are characteristic of the frame being transmitted, it is more robust. The code violation method can be fooled by returning a signal to the 82588 which is not the same as
the transmitted signal but is a valid Manchester signal-like a 1 MHz signal. Both methods can be used
simultaneously giving a combination of speed and robustness.
These mechanisms add a further robustness to the collision detection mechanism of the 82588. It is also possible to OR an externally generated collision detect signal
to the internally generated condition by bit comparison
(see Figure 17).
3.6 Carrier Sensing
NOTE:
In order to reliably detect a collision using the collision by bit comparison mode, the transmitter must
still be transmitting up to the point where the receiver
has seen enough bits to complete its signature. Otherwise, the transmitter may be done before the RX signature is completed resulting in an undetected ~ collision. A sufficient condition to avoid this situation is to
transmit frames with a minimum length of 1.5 • slottime (see Figure 16).
A StarLAN network is considered to be busy if there
are transitions on the cable. Carrier is supposed to be
active if there are transitions. Every node controller
needs to know when the carrier is active and when not.
This is done by the carrier sensing circuitry. On the
82588 this circuit is on chip. It looks at the RxD (re·
ceive data) pin and if there are transitions, it turns on
an internal carrier sense signal. It turns off the carrier
sense signal if RxD remains in idle (high) state for 13/8
bit times. This carrier sense information is used to mark
the start of the interframe space time and the back off
time. The 82588 also defers transmission when the carrier sense is active.
3.5.3 ADDITIONAL COLLISION DETECTION
MECHANISM
In addition to the collision detection mechanisms described in the preceding sections, the 82588 also flags
collision when after starting a transmission any of the
following conditions become valid:
a) Half a slot time elapses and the carrier sense of
82588 is not active.
When operating in the NRZI encoded mode, 'carrier
sense is turned off if RxD pin is in the idle state for 8 bit
times or more (see Figure 18).
82588
PO
TX
HEADEND
PO
RX
CONDITION ,OR RELIABLE CDBBC
TLIAINJRAIALLENGTH
t
SLOLTIIAE
> SLOLTIIAE+ 2*PD
~ 2*PD
TLIAINJRAIALLENGTH
> 1.5*SLOLTIIAE
231422-75
Figure 16. Limitation of CDssC Mechanism
1-361
Ap·236
COLLISION DETECTION BY BIT COMPARISON (CDBBC)
(CONFIGURE BYTE B, BIT 3)
COLLISION DETECTION SOURCE (INTERNAL, EXTERNAL)
(CONFIGURE BYTE 10, BIT 7)
231422-76
Figure 17. Mode 0, Collision Detection
3.7 Squelching the Input
Squelch circuit is used to filter idle noise on the receiver
input. Basically two types of squelch may be used: Voltage and time. Voltage squelch is done to filter out signals whose strength is below a defined voltage threshold (0.6 volts for StarLAN). It prevents idle line noise
from disturbing the receive circuits on the controller.
The voltage squelch circuit is placed right after the receiving pulse transformer. It enables the input to the
RxD pin of the 82588 only when the signal strength is
above the threshold.
If the signal received has the proper level but not the
proper timing, it should not bother the receiver. This is
accomplished by the time squelch circuit on the 82588.
Time squelching is essential to weed out spikes, glitches
and bad signal especially at the beginning of a frame.
The 82588 does not turn on its carrier sense (or receive
enable) signal until it receives three consecutive edges,
each separated by time periods greater than the fast
time clock high time but less than 13/8 bit-times as
shown in Figure 18.
MANCHESTER
~
DATA~
CARRIER
~
I
I
I.
---u-1:'':' :;0:'"1--
ED~ESj
.1....-1
13/BBTxB
25/16 BTx 16
~
DATA~
CARRIER
~
I
I
ED~E$j
231422-77
Figure 18. Carrier Sensing
1-362
AP-236
The carrier sense activation can be programmed for a
further delay by up to 7 bit times by a configuration
parameter called carrier sense filter.
3.8 System Bus Interface
The 82588 has a conventional bus interface making it
very easy to interface to any processor bus. Figure 19
shows that it has an 8 bit data bus, read, write, chip
select, interrupt and reset pins going to the processor
bus. It also needs an external DMA controller for data
transfer. A system clock of up to 8 MHz is needed. The
read and write access times of the 82588 are very
short-9S ns-as shown by Figure 20. This further facilitates interfacing the controller to almost any processor.
SERIAL CLOCK
RESET
RTS]
CTS SERIAL
Tx D INTERFACE
00-7
STANDARD
BUS
INTERFACE
RD
WR
82588
INT
28 PIN
PLASTIC/CERAMIC
cs
+--RxD
TCLK
DRQO
IlIotA [ DACKO--+
INTERFACE DRQ 1
DACKI
(MODE 0)
CRS} CSMA/CD
COT INTERFACE
CLK
SYSTEM CLOCK
231422-20
Figure 19. Chip Interface
-
BOns
(MIN)
.
95ns
(MIN)
I
55n8(MAX)
DATA
-75ns(MIN)
\
.
95ns
(MIN)
- O n s --I
(MIN)
DATA
231422-21
Figure 20. Access Times
1-363
Ap·236
The 82588 has over 50 bytes of registers, and most are
accessed only indirectly. Figure 21 shows the register
access mechanism ofthe 82588. It has oae I/O port and
2 DMA channel ports. These are the windows into the
82588 for the CPU and the DMA controller. An external CPU can write iato the Command register and read
from the Status registers using I/O instructions and
asserting chip select and write or read lines. Although
there is just one I/O port and 4 status registers, they
can be read out in a round robin fashion through the
same port as shown in Figure 22. Other registers like
the Configuration, Individual Address registers can be
accessed oaly through DMA. All the internal registers
can be dumped into memory by DMA using the Dump
command. The execution of some of the commands is
described in section 4. See the 82588 Reference Manual
for details on these commands.
3.9 Debug and Diagnostic Aids
Besides the standard functions that can be used directly
for StarLAN, the 82588 offers many debug and diag-
82588 REGISTER SET
~
__......_-4~_--1___..L--.~_-
I
COMMAND
~
STATUS
I
~
WRITE ONLY
READ ONLY
CONFIGURATION
IA
MULTICAST
READ
'"
WRITE
Tx CRC
Rx CRC
IMPLICIT REGISTERS
(OVER SO BYTES)
231422-22
Figure 21. Register Access
1-364
intJ
AP-236
4 Status registers are accessed through one read port
POINTER
CD
L
STATUS 0
STATUS 1
--+ I READ PORT
STATUS 2
I
STATUS 3
231422-23
The pointer can be changed using a command or can be automatically incremented.
'*
READ_STATUS_588: PROCEDURE;
OUTPUT (CS_588) = 15;
STATUS_588(0)=INPUT (CS_588);
STATUS_588(1)=INPUT (CS_588);
STATUS_588(2)=INPUT (CS_588);
STATUS_588(3)=INPUT (CS_588);
RETURN
END READ_STATUS_588;
*'
*'
COMMAND 15
,. RELEASE POINTER, INITIAL = 00
'*
REFRESH STATUS REGISTER IMAGE "'
/* IN MEMORY.
READING 4 STATUS REGISTERS
Figure 22. Reading the Status Register
nostics functions. The DIAGNOSE command of the
82588 does a self-test of most of the counters and timers
in the 82588 serial unit. Using the DUMP command,
all the internal registers of the 82588 can be dumped
into the memory. The TDR command does Time Domain Reflectometery on the network. The 82588 has
two loopback modes of operation. In the internal loopback mode, the TXD line is internally connected to the
RXD one. No data appears outside the chip, and the
82588 is isolated from the link. This mode enables
checking of the receive and transmit machines without
link interference. In the external loopback mode, the
82588 becomes a full duplex device, being able to receive its own transmitted frames. In this mode data
goes through the link and all CSMA/CD mechanisms
are involved.
±62.5 ns at I Mbs for both 8X, 16X Manchester encoded data.
Jitter = ± variation of an edge from its nominal poSition.
Jitter can occur on every edge.
IdWldWI
IdWldWI
r-~_j
l_::J::L-_-_-~:___
1-1.---'w----+l,1
231422-78
x8
Manchester
NAZI
±
'A.
x16
±1I16
±1/16BT
±3/32 BT
±3116BT
±3116 BT
(Code Violations Enabled)
NAZI
(Code Violations Disabled)
3.10 Jitter Performance
When the 82588 r~ives a frame from the HUB, the
signal has jitter. Jitter is the shifting of the edges of the
signal from their nominal position due to the transmission over a length of cable. Many factors like, intersymbol interference (pulses of different widths have different delays through the transmission media), rise and
fall times of drivers and receivers, cross talk etc., contribute to the jitter. StarLAN specifies a maximum jitter of ±62.5 ns whenever the signal goes from a
NODE/HUB or HUB/HUB. Figure 23 shows that the
jitter tolerance of the 82588 is exactly the required
Figure 23. 82588 JItter Performance.
4.0 THE 82588
This chapter describ~ the basic 82588 operations.
Please refer to the 82588 reference manual in Intel Microcommunications. Handbook for. a detailed description. Basic operations like transmitting Ii frame, receiving a frame, configuring the 82588 and dumping the
register contents are, discussed here to give a feel for
how the 82588 works.
1-365
inter
Ap·236
4.1 Transmit and Retransmit
Operations
To transmit a frame, the CPU prepares a block in the
memory called the transmit data block. As shown in
Figure 24, this block starts with a byte count field, indicating how long the rest ofthe block is. The destination
address field contains the node address of the destination. The rest of the block contains the information or
the data field ofthe frame. The CPU also programs the
DMA controller with the start address of the transmit
data block. The DMA byte count must be equal to or
greater than the block length. The 82588 is then issued
a TRANSMIT command-an OUT instruction to the
command port of the 82588. The 82588 starts generating DMA requests to read in the transmit da1;a block by
DMA. It also determines whether and how long it must
defer on the link and after that, it starts transmitting
the preamble. The 82588 constructs the frame on the
fly. It takes the destination address from the memory,
source address from its own individual address memory
(previously programmed), data field from the memory
and the CRC, is generated on chip, at the end of the
frame.
BYTE
COUNT
INFORMATION
To re-attempt transmission, the CPU must reinitialize
the DMA controller 7to the start of the transmit data
block and issue a RETRANSMIT command to the
82588. When the 82588 receives the retransmit command and the back-off timer has expired, it transmits
again. Interrupt and the status register contents again
indicate the success or failure of the (re)transmit attempt.
The main difference between transmit and retransmit
commands is that retransmit does not clear the internal
count for the number of collisions occurred, whereas
transmit does. Moreoever, retransmit takes effect only
when the back-off timer has expired.
4.2 Configuring the 82588
To initialize the 82588 and program its network and
system parameters, a configure operation is performed.
It is very similar to the transmit operation. Instead of a
transmit data block as in transmit command, a configure data block-shown in Figure 12-is prepared by
the CPU in the memory. The first two bytes of the
block specify the length of the rest of the block, which
specify the network and system parameters for the
82588. The DMA controller is then programmed by
the CPU to the beginning of this block and a CONFIGURE command is issued to the 82588. The 82588 reads
in the parameters by DMA and loads the parameters in
the on-chip registers. '
1. Prepare Transmit Data-Block in Memory
2. Program DMA Controller
3. Issue Transmit Command on the Desired
Channel
DESTIN.
ADDRESS
status registers to find out if the transmission was successful. If a collision occurs during transmission, the
82588 aborts transmission and generates the jam sequence, as required by IEEE 802.3, and informs the
CPU through interrupt and the status registers. It also
starts the back-off algorithm.
U
Similarly, for programming the INDIVIDUAL ADDRESS and MULTICAST ADDRESSes, the DMA
controller is used to load the 82588 registers.
231422-25
Transmit Data,Block
4.3 Frame Reception
4. Interrupt is received on completion of command or if the command was aborted or
there was a collision. The status bytes 1 and
2 indicate the result of the operation.
7
6
5
HRT MAX
DEF BEAT COll
TX
COll
OK
TX
,4
3
2
0
"
NUM. OF COLLISIONS
I lOST
CRS
STATUS 1
I
lOST IUNIER
'CTS RUN STATUS 2
231422-26
Transmit &: Retransmit Results Format
Figure 24., Transmit 'Oper~tion
At the, conclusion of transmisSion' the 82588 generates
an interrupt to the CPU. The CPU can then read the
Before enabling the 82588 for reception the CPU must
make a buffer available for the frame to be received.
The CPU must program the DMA controller with the
starting address of the buffer and then issue the R"ENABLE command to the 82588. When a frame arrives at the RxD pin of the 82588, it starts being received. Only if the address in the destination address
matches either the Individual address, Multicast address or if it is a broadcast address, is the frame deposited into memory by the 82588 using DMA. The format
of storage in the memory is shown in Figure 25.' At the
end, a two byte field is attached which shows the status
of the received frame. If CRC, alignment or.oyerrun
errors are encountered, theY.,are reported. An inter-
1·366
intJ
Ap·236
RECEIVED rRAWE
1. Prepare a Buffer for Reception
2. Program DMA Controller
3. Issue Receiver Enable Command
When a frame is received, it is deposited in the
memory. Receive status bytes (2) are appended to
the frame in the memory, byte count written in the
status registers I, 2, and an interrupt is generated.
SRT
RECEIVE rRW
STATUS
DESTIN.
ADDRESS
SOURCE
ADDRESS
NO
EOI'
RCV
O.K.
CRC
ERR
~~
RUN
.~~~
ALG
ERR
STATUS REG. 1
STATUS REG. 2
r
Bm
COUNT
X
RECEIVE
STATUS
231422-27
Figure 25. Receive Operation (Single Buffer)
rupt from 82588 occurs when all the bytes have been
transferred to the memory. This informs the CPU that
a new frame has been received.
If the received frame has errors, the CPU must recover
(or re-use) the buffer. Note that the entire frame is deposited into one buffer. The 82588 when NOT configured for the external loopback mode, will detect collisions (code violations) during receptions. If a collision
is detected, the reception is aborted and status updated.
CPU is then informed by an interrupt (if the collided
frame fragment is shorter than the address length, no
reception will be started), and no interrupt will happen.
4.3.1 Multiple Buffer Frame Reception
It is also possible to receive a frame into a number of
fixed size buffers. This is particularly economical if the
received frames vary widely in size. If the single buffer
scheme were used as described above, the buffer required would have to be bigger than the longest expected frame and would be very wasteful for very short
(typically acknowledge or control) frames. The multiple buffer reception is illustrated in Figure 26. It uses
two DMA channels for reception.
IDBurrER 1
OBurrER 2
OBUrf'ER 3
·
···
IDBUrf'ER N
Buffer
Pointer
Table
(Managed by CPU)
231422-28
Figure 26. Multiple Buffer Reception
1-367
inter
AP-236
As in single buffer reception, the one channel, say channel 0, of the DMA controller is programmed to the
start of buffer I, and the 82588 is enabled for reception
with the chaining bit set. ~s soon as the first byte is
read out of the 82588 by the DMA controller and written into the first location of buffer I, the 82588 generates an interrupt, saying that it is filling up its last available buffer and one more buffer must be allocated. The
filling up of the buffer I continues. The CPU responds
to the interrupt by programming the other DMA channel-channel I-with the start address of the second
buffer and issuing an ASSIGN ALTERNATE buffer
command with an INTACK (interrupt acknowledge).
This informs the 82588 that one more buffer is available on the other channel. When buffer I is filled up
(the 82588 knows the size of buffers from the configuration command), the 82588 starts generating the DMA
requests on the other channel. This automatically starts
fuling up buffer 2. As soon as the first byte is written
into buffer 2, the 82588 interrupts the CPU again-asking for one more buffer. The CPU programs the channel 0 of the DMA controller with the start address of
buffer 3, issues an ASSIGN ALTERNATE buffer command with INTACK. This keeps the buffer 3 ready for
the 82588. This switching of channels continues until
the entire frame is received generating an end of frame
interrupt. The CPU maintains the list of pointers to the
buffers used.
Since a new buffer is allocated at the time of filling up
of the last buffer, the 82588 automatically switches to
, the new buffer to receive the next frame as soon as the
last frame is completely received. It can start receiving
the new frame almost immediately, even before the end
offrame interrupt is serviced and acknowledged by the
CPU. If a new frame comes in, and the previous frame
interrupt is not yet acknowledged, another interrupt
needed for new buffer allocation is buffered (and not
lost). As soon as the first one is acknowledged, the interrupt line goes active again for the buffered one.
If by the time a buffer fills up no new buffer is available,
the 82588 keeps on receiving. An overrun will occur
and will be reported in the received frame status. However, ample time is available for the allocation of a new
buffer. It is roughly equal to the time to fill up a buffer.
For 128 byte buffers it is 128 X 8 = 1024 ms or approximately I millisec. You get I ms to assign a new
buffer after getting the interrupt for it. Hence the process of multiple buffer reception is not time critical for
the system performance.
This method of reception is particularly useful to guarantee the reception of back-to-back frames separated by
IFS time. This is because a new buffer is always available for the new frame after the current frame is received.
Although both the DMA channels get used up in receiving, only one channel is kept ready for reception
and the other one can be used for other commands until
the reception starts. If an execution command like
transmit or dump command is being executed on a
channel which must be allocated for reception, the
command gets automatically aborted when the ASSIGN ALTERNATE BUFFER command is issued to
the channel used for the execution command. The interrupt for command abortion occurs after the end of
frame interrupt.
1-368
inter
AP-236
the 82588 command register and knowing the results (if
any) through the status registers.
4.4 Memory Dump of Registers
All the 82588 internal registers can be dumped in the
memory by the DUMP command. A DMA channel is
used to transfer the register contents to the memory. It
is very similar to reception of a frame; instead of data
from the serial link, the data from the registers gets
written into the memory. This provides a software debugging and diagnostic tool.
4.5 Other Operations
Other 82588 operations like DIAGNOSE, TDR,
ABORT, etc. do not require any parameter or data
transfer. They are executed by writing a command to
5.0 StarLAN NODE FOR IBM PC
This chapter deals with the hardware-the StarLAN
board-to interface the IBM PC to a StarLAN Network. This is a slave board which takes up one slot on
the I/O channel of the IBM PC. Figure 27 shows an
abstract block diagram of the board. It requires the
IBM PC resources of the CPU, memory, DMA and
interrupt controller on the system board to run it. Such
a board has two interfaces. The IBM PC I/O Channel
on the system or the parallel side and the telephone
grade twisted pair wire on the serial side. Figures 28, 29
show the circuit diagram of the board.
PULSE
TRANSFORMER
8 BIT BUS
SYSTEM
BUS
82588
TxD
.-------
TELEPHONE
JACK
PULSE
.JIAr:::....--I SHAPING
CONTROL
< >
RxD
SYS ClK
SQUELCH
+
ENABLE
CIRCUITS
231422-29
Figure 27. 82588 Based StarLAN Node
1-369
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231422-80
inter
AP-236
5.1 Interfacing to the IBM PC 1/0
Channel
IBM PC has 8 slots on the system board to allow expansion of the basic system. All of them are electrically
identical and the I/O channel is the bus that links them
all to the 8088 system bus. The I/O channel contains
an 8 bit bidirectional data bus, 20 address lines, 6 levels
of interrupt, 3 channels of DMA control lines and other
control lines to do I/O and memory read/write operations. Figure 30 shows the signals and the pin assignment for the I/O Channel.
to 82588 for commands and status. address 30lH accesses an on board control port that enables the various
interrupt and DMA lines. Even though only two addresses are needed. the card uses all the 16 addresses
spaces from 300H to 30FH. This was done to keep simplicity and minimum component count. Registers address decoding is done using a PAL (16L8) and an external NAND gate (U8).
Hex Range
OOO-OOF
020-021
040-043
060-063
080-083
Rear Panel
SIGN4L N4ME
GNO
....
Bl
-
41
I-
+RESET ORV
+5V
+06
+DS
+OR02
+03
+04
-12V
+02
-
-CARD SLCTO
+12V
GNO
+01
+00
BID 410-
-t.lEWW
-t.lEMR
+1/0 CH R
300-31 F
320-32F
378-37F
380-38C··
380-389··
+4EN
-
-lOW
+419
+A18
-lOR
+417
-DACK3
+416
+OR03
-DACKI
+A14
+A15
+ORQl
3AO-3A9
+AU
+A12
-DACKO
CLOCK
B20 A20
3BO-3BF
3CO-3CF
3DO-3DF
3EO-3E7
3FO-3F7
3F8-3FF
+All
+Al0
+IR06
+IR07
+49
+IRQS
+48
+IR04
+47
+IR03
-DACK2
+ALE
+A6
+45
+M
+43
+SV
+A2
+T/C
GNO
OCX
OEX
200-20F
210-217
220-24F
278-27F
2FO-2F7
2F8-2FF
1/0 CH CK
+07
+IR02
-5VDC
+OSC
OAX"
S1GN4L NAME
--
\.
B31 431
--
• At power-on time, the Non Mask Interrupt into the
8088 is masked off.
This mask bit can be set and reset through
system software as follows:
Set mask: Write hex 80 to 1/0 Address hex AO
(enable NMI)
Clear mask: Write hex 00 to 1/0 Address hex AO
(disable NMI)
•• SDLC Communications and Secondary Binary
Synchronous Communications cannot be used
together because their hex addresses overlap.
+Al
+AO
'\
Usage
DMA Chip 8237A-5
Interrupt 8259A
Timer 8253-5
PP18255A-5
DMA Page Registers
NMI Mask Register
Reserved
Reserved
Game Control
Expansion Unit
Reserved
Reserved
Reserved
Asynchronous Communications
(Secondary)
Prototype Card
Fixed Disk
Printer
SDLC Communications
Binary Synchronous Communications
(Secondary)
Binary Synchronous Communications
(Primary)
IBM Monochrome Display/Printer
Reserved
ColorIGraphics
Reserved
Diskette
Asynchronous Communications
(Primary)
COMPONENT SIDE
231422-31
Figure 30. I/O Channel Diagram
5.1.1 REGISTER ACCESS AND DATA BUS
INTERFACE
Figure 31.1/0 Address Map
The CPU accesses the StarLAN adapter card through 2
I/O address windows. Address 300H is used to access
1-372
inter
AP-236
A4-A9 - - - .
AO~
---+ CS_ (to 588)
LOGIC
U2, U8
AEN---.
IOW_---.
---+ LOPRL (to OIo4A, INTERRUPT enable lines)
...
~---
231422-56
Register Access
Format of Following Equations Will Be According To
The Following Specifications:
INVERT
SIGNAL ACTIVE LOW
&:
LOGIC AND
#
LOGIC OR
A9NANDA8 = ! (A9 &: A8)
CS_
=I
LDPORT_
BUSEN_
!AEN &: !A9NANDA8 &: !A7 &: !AS &: !A5 &: !A4 &: !AO )
(
= ! ( !AEN &: !A9NANDA8 &: !A7 &:
=DACKl_ &: DACK2_ &: (! ( !AEN &:
The signal CS_ decodes address 300H, it is only active
when AEN is inactive meaning CPU and not DMA
cycles. LDPORT_ has exactly the same logic for address 30lH, but it is only active during I/O write cycles. The I/O port sitting on address 30lH is write
only. The data BUS lines DO to D7 are buffered from
the 82588 to the PC bus using an 74LS245 transceiver
chip.
!AS &: !A5 &: !A4 &: AO &: !IOWR_ )
!A9NANDA8 &: !A7 &: !AS &: !A5 &: !A4));
The Bus transceiver is enabled if: A DMA access is
taking place, or I/O ports 300H to 30FH are being
accessed.
5.1.2 Control Port
As mentioned the StarLAN adapter port has a 4-bit
write only control port. The purpose of this port is to
selectively enable the DMA and INTERRUPT request
lines. Also it can completely disable the transmitter.
Control Port Definition
00-07
I ENDRQ1 I ENDRQ3 I ENINTER I TXEN
x
V
E
R
BUSEN_
Data Bus Interface
TO 588
231422-57
ENDRQl, ENDRQ2 : "I" Enable DMA requests.
ENINTER
: "I" Enable INTERRUPT
request.
TXEN
: "I" Enable the transmitter.
On power up all bits default to "0".
1-373
AP·236
5.1.3 CLOCK GENERATION
The 82588 requires two clocks for operation. The system clock and the serial clock. The serial clock can be
generated on chip by putting a crystal across Xl and
X2 pins. Alternatively, an externally generated clock
can be fed in at pin XI (with X2 left open). In both
cases, the frequency must be either 8 or 16 times (sampling factor) the desired bit rate. For StarLAN, 8 or 16
MHz are the correct values to generate I Mb/s data
rate. A configuration parameter is used to tell the
82588 what the sampling factor is. An externally supplied clock must have MOS levels (0.6V -3.9V). Specifications for the crystal and the circuit are shown in Figure 32.
The system clock has to be supplied externally. It can
be up to 8 MHz. This clock runs the parallel side of the
82588. Its frequency does not have any impact on the
read and write access times but on the rate at which
data can be transferred to and from the 82588 (Maximum DMA data rate is one byte every two system
clocks). This clock doesn't require MOS levels.
The I/O channel of the IBM PC supplies a 4.77 MHz
signal of 33% duty cycle. This signal could be used as a
system clock. It was decided, however, to generate a
separate clock on the StarLAN board to be independent of the I/O channel clock so that this board can
also be used in other IBM PCs and also in some other
compatibles. The 8 MHz system clock is generated us-
ing a DIP OSCILLATOR which have the required 50
ppm tolerance to meet StarLAN. This clock is converted to MOS levels by 74HCTOO and fed into both the
system and serial clock inputs.
5.1.4 DMA INTERFACE
The 82588 requires either one or two DMA channe~s
for full operation. In this application, one channel IS
dedicated for reception and the other is used for transmissions and the other commands. Use of only one
DMA channel is possible but may require more complex software, also some RX frames may be lost during
switches of the DMA channel from the receiver to the
transmitter (Those frames will be recovered by higher
layers of the protocol). Also using only one DMA
channel will limit the 82588 loopback functionality. So
the recommendation is to operate with two DMA channels if available. Appendix C describes a method of operating with only one DMA channel without loosing
RX frames.
The IBM PC system board has one 8237 A DMA controller. Channel 0 is used for doing the refresh of
DRAMs. Channels 1, 2 and 3 are available for add-on
boards on the I/O Channel. The floppy disk controller
board uses the DMA channel 2 leaving exactly two
channels (1 and 3) for the 82588. The situation is worse
if the IBM PC/XT is used, since it uses channel 3 for
the Winchester hard disk leaving just the channel 1 for
Series Resonance
-Frequency Will Drift by About 400 PPM from Nominal
-No Capacitors Needed
-Doesn't Meet StarLAN Requirements
.=h
CRYSTALD
Meeting StarLAN 100 PPM Requirements
-Use Parallel Resonance Crystal
-Recommended For Precise Frequencies
-82588 X-TAL Oscillator Stability ± 35 PPM (0-70°C)
L
:E-:E--
Crystal: Load Capacitance
= 20 pF
Shunt Capacitance = 7 pF Maximum
Series Resistance = 30n Maximum
Frequency Tolerance = 50 PPM (0- 70°C)
CI, C2
~
27 pF or 39 pF, 5%
Figure 32. Crystal Specifications
1-374
Cl
82588
C2
231422-81
inter
AP-236
the 82588. On the other hand, the IBM PC/AT has 5
free DMA channels. We will assume that 8237A DMA
channels 1 and 3 are available for the 82588 as in the
case of the IBM PC.
Since the channel 0 of 8237A is used to do refresh of
DRAMs all the channels should be operated in single
byte transfer mode. In this mode, after every transfer
for any channel the bus is granted to the current highest priority channel. In this way, no channel can hog
the bus bandwidth and, more important, the refresh of
DRAMs is assured every 15 microseconds since the refresh channel (number 0) has the highest priority. This
mode of operation is very slow since the HOLD is
dropped by the 8237A and then asserted again after
every transfer. Demand mode of operation is a lot more
suitable to 82588 but it cannot be used because of the
refresh requirements.
5.1.5 INTERRUPT CONTROLLER
The 82588 interrupts the CPU after the execution of a
command or on reception of a frame. It uses the 8259A
interrupt controller on the system board to interrupt
the CPU. There are 6 interrupt request lines, IRQ2 to
IRQ7, on the I/O channel. Figure 34 shows the assignment of the lines. In fact, none of the lines are completely free for use. To add any new peripheral which
uses a system board interrupt, this interrupt needs to
have the capability to share the specific line, by driving
the line with a tri-state driver. The 82588 StarLAN
adapter board can optionally drive interrupt lines
IRQ3, IRQ4 or IRQ5 (An 74LS125 driver is used).
Number
Usage
NMI
Parity
Timer
Keyboard
Reserved
Asynchronous Communications
(Secondary)
SDLC .Communications
SSC (Secondary)
Asynchronous Communications
(Primary)
SDLC Communications
SSC (Primary)
Fixed Disk
Diskette
Printer
0
Whenever the 82588 interfaces to the 8237A in the single transfer mode, there is a potential 8237A lock-up
problem. The 82588 may deactivate its DMA request
line (DREQ) before receiving an acknowledge from the
DMA controller. This situation may happen during
command abortions, or aborted receptions. The 8237A
under those circumstances may lock-up. In order to
solve this potential problem, an external logic must be
used to insure that DREQ to the DMA controller is
never deactivated before the acknowledge is received.
Figure 33 shows the logic to implement this function.
This logic is implemented in the 16L8 PAL.
The 82588 DREQ lines are connected to the IBM/PC
bus through tri-state buffers which are enabled by writing to I/O port 301H. This function enables the use of
either one or two DMA channels and also the sharing
of DMA channels with other adapter boards.
1
2
3
4
5
6
7
Figure 34. IBM PC Hardware Interrupt Listing
588REO~
DREO
DACK
RESET - - - - - - - - - - '
588 REO--.J
DREO--.J
231422-82
Figure 33. DMA Request Logic
1-375
AP-236
5.2 Serial Link Interface
5.2.1 TRANSMIT PATH
A typical StarLAN adapter board is connected to the
twisted pair wiring using an extension caliIe (typically
up to 8 meters-25 ft.). See Figure 35. One end of the
cable plugs into the telephone modular jack on the StarLAN board and the other end into a modular jack in
the wall. The twisted pair wiring starts at the modular
jack in the wall and goes to the wiring closet. In the
wiring closet, another telephone extension cable is used
to connect to a StarLAN HUB. The transmitted signal
from the 82588 reach the on-board telephone jack
through a RS-422 driver with pulse shaping and a pulse
transformer. The received signals from the telephone
jack to the 82588 come through a pulse transformer,
squelch circuit and a receive enable circuit.
The single ended transmit signal on the TxD pin is
converted to a differential signal and the rise and fall
times are increased to 150 to 200 ns before feeding it to
the pulse transformer (this pulse shaping is not a requirement, but proves to give good results). Am26LS30
is a RS-422 driver which converts the TxD signal to a
differential signal. It also has slew rate control pins to
increase to rise and fall times. A large rise and fall time
reduces the possibility of crosstalk, interference and radiation. By the other hand a slower edge rate increases
the jitter. In the StarLAN adapter card, the first approach was used. The 26LS30 converts a square pulse
to a trapezoidal one-see Figure 36. The filtering effect
of the cable further adds to reduce the higher frequency
components from the waveform so that on the cable the
signal is almost sinusoidal. The pulse transformer is for
DC isolation. The pulse transformers from Pulse Engineering-type PE 64382-was used in this design. This
is a dual transformer package which introduces an additional rise and fall time of about 70-100 ns on the
signal, helping the former discussed waveshaping.
I
... ...L.L.L.".L.L.LoU
EXTENSION
CABLE
5.2.2 IDLE PATTERN GENERATION
INTO IBM PC
WIRING
PANEL
IN THE WIRING CLOSET
231422-33
StarLAN requires transmitters to generate an IDLE
pattern after the last transmitted data bit. The IDLE
pattern is defined to be a constant high level for 2-3
microseconds. The purpose of this pattern is to insure
that receivers will decode properly the last transmitted
data bits before signal,decay. Currently the 82588 needs
one external component to generate the IDLE. The operation principle is to have an external shift register
(74LSI64) that will kind of act as an envelope detector
of the TXD line. Whenever the TXD line goes low
Figure 35. Path from StarLAN Board to HUB
82588
-==:.:.;::.a
~Tx.;.;D+_ _
150n.
RISE/FALL
TIMES
231422-34
Figure 36. Wave Shaping
1-376
inter
AP-236
(first preamble bit), the output of the shift register
(third cell) will immediately go low, enabling the RS422 driver, the shift register being clocked by TCLKwill time the duration of the TXD high times. If the
high time is more than 2 microseconds, meaning that
the 82588 has gone idle, the transmitter will be disabled
(See Figure 37). Another piece of this logic is the DRing of the output of the shift register with TXEN-signal which comes from the board control port. This signal completely disables the transmitter. The other purpose of this enable signal, is to make sure that after
power-up, before the 82588 is configured, the RS-422
drivers won't be enabled (TCL~ is not active before
the configure command). See Figures 28, 29 for the
complete circuit.
5.3 RECEIVE PATH
The signal coming from the HUB over the twisted pair
wire is received on the StarLAN board through a lOOn
line termination resistor and a pulse transformer. The
pulse transformer is of the same type as for the transmit
side and its function is dc isolation. The received signal
which is differential and almost sinusoidal is fed to the
Am26LS32 RS-422 receiver. As seen from Figure 38
the pulse transformer feeds two RS-422 receivers. The
one on the bottom is for squelch filtering and the one
above is the real receiver which does real zero crossing
detection on the signal and regenerates a square digital
waveform from the sinusoidal signal that
~-~, oo~~
is received. Proper zero crossing detection is very essential; if the edges of the regenerated signal are not at zero
crossings, the resulting signal may not be a proper
Manchester encoded signal (self introduced jitter) even
if the original signal is valid Manchester. The resistors
in the lower receiver keep its differential inputs at a
voltage difference of 600 mY. These bias resistors ensure that the output remains high as long as the input
signal is more than -600 mY. It is very important that
the RxD pin remains HIGH (not LOW or floating)
whenever the receive line is idle. A violation of this may
cause the 82588 to lock-up on transmitting. Remember,
that based on the signal on the RxD pin, the 82588
extracts information on the data being received, Carrier
Sense and Collision Detect. This squelch of 600 m V
keeps the idle line noise from getting to the 82588. Figure 39 shows that when the differential input of the
receiver crosses zero, a transition occurs at the output.
It also shows that if the signal strength is higher than
-600 mY, the output does not change. (This kind of
squelching is called negative squelching, and it is done
due to the fact that the preamble pattern starts with a
going low transition). Note that the differential voltage
at the upper receiver input is zero when the line is idle.
The output of the squelch goes to a pulse stretcher
which generates an envelope ofthe received frame. The
envelope is a receive enable signal and is used to AND
the signal from the real zero crossing receiver before
feeding it to the Rill pin of the 82588.
18-22
TX - FAST CLOCKS
-
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231422-83
Figure 37. Idle Generation
1-377
inter
AP-236
FILTERING OF
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231422-86
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AP-236
6.0 THE StarLAN HUB
6.1 A StarLAN Hub for the IBM/PC
The function of a StarLAN HUB is described in section
2.0. Figure 42 shows a block diagram of a HUB. It
receives signals from the nodes (or lower level HUBs)
detects if there is a collision, generates the collision
presence signal, re-times the signal and sends it out to
the higher level HUB. It also receives signals from the
higher level HUB, re-times it and sends it to all the
nodes and lower level HUBs connected to it. If there is
no higher level HUB, a switch on the HUB routes the
upstream received signal down to all the lower nodes.
The functions performed by a HUB are:
Figure 43 shows the implemention of a 5/6 port HUB
for the IBM/PC.
The idea of the following design is to show a HUB that
plugs into the IBM/PC backplane. This HUB not only
gets its power from the backplane, but also enables the
host PC to be one NODE into the StarLAN network.
This embedded node scheme enables further savings
due to the fact that all the analog interface for this port
is saved (receiver, transmitter, transformer, etc).
This kind of board would suit very much a small cluster topology (very typical in departments and small offices) where the HUB board would be plugged into the
FILE SERVER PC (pC/XT, PC/AT).
'Receiving signals, squelch
'Carrier Sensing
• Collision Detection
'Collision Presence Signal Generation
'Signal Retiming
'Driving signals on to the cable
• Jabber Function
'Receive protection Timer
The HUB design doesn't implement the Jabber and the
protection timers as called by the IBASE5 draft standard. Those functions are optional and were not closed
during the writing of this AP-NOTE. This HUB does
implement the RETIMING circuit which is an essential requirement of StarLAN.
Figures 44 to 49 show a complete set of schematics for
the HUB design.
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231422-40
Figure 42. StarLAN HUB
1-382
inter
AP-236
PHONE JACKS
231422-87
• Low Cost HUB, Uses IBM/PC Power Supply
• 82588, Embedded Port Savings
Transformers
422 Drivers
• Functional StarLAN Cluster, For Low Cost/Small Topologies
Figure 43. IBM/PC Resident HUB
1-383
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231422-93
AP-236
6.1.1 HUB INPUT PORTS
Figure 38 shows a block diagram of an input port. Differently than the implementation in Figure 29 the HUB
input port is potentially more complex than the NODE
input port. The reason being that the HUB is a central
resource and much more sensitive to noise. For example, if the NODE input port would falsely interpret
noise on an IDLE line as valid signal, the worst case
situation would be that this noise would be filtered out
by the 82588 time squelch circuitry, on the HUB by the
other hand, this false carrier sense could trigger a COLLISION and a good frame (on another input) potentially discarded.
As shown in Figure 38 immediately after the termination resistor, there is a HIGH FREQUENCY FILTER
circuit. The purpose of this circuit is to eliminate high
frequency noise components keeping noise jitter into
the allocated budget (about ± 30 ns). A 4 MHz two
pole butterworth filter is being recommended by the
IEEE 802.3 IBASE5 task force (see Figure 50).
The time squelch for the NODE board is implemented
by the 82588 (see section 3.7) this circuit makes sure
that pulses that are shorter than a specified duration
will be filtered out.
The other components of the block diagram were explained in section 3.0.
The HUB desigu doesn't implement the HIGH FREQUENCY FILTER and TIME SQUELCH. In the
HUB design as an output of each input port, two signals are available: Rn, En, (RA, RB ... , EA, EB ... ).
The Rn signals are the receive data after the zero crossing receivers. The En lines are CARRIER SENSE signals. The HUB design supports either 5 or 6 input
ports, dependent upon if it is configured as IHUB or
HHUB. Port RE, EE (Figure 49) is bidirectional, configurable for either input or output. Port RF, EF_ is
the embedded 82588 port, and doesn't require the analog circuitry (EF is inverted, being generated from the
RTS_ signal).
RXVE~R_ _..._ _ _ _ _ _ _ _•... llf
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110A
231422-94
Figure 50. Receiver High Frequency Filter
1-390
intJ
AP-236
6.1.2 COLLISION DETECTION
Rn and En signals from each channel are fed to a 16L8
PAL, where the collision detection function is per-
formed.
Collision Detection in the StarLAN HUB is performed
by detecting the presence of activity on more than one
input channels. This means if the signal En is active for
more than one channel, a collision is said to occur. This
translates to the PAL equations:
COLLISION DETECTION:
CDT = I(EA&IEB&!EC&!ED&IEE&EF_ #
!EA&EB&IEC&IED&IEE&EF_ #
IEA&IEB&EC&IED&IEE&EF_ #
!EA&IEB&IEC&ED&!EE&EF_ #
!EA&IEB&IEC&!ED&EE&EF_ #
! EA& !EB &!EC& !ED& lEE & !EF_ #
lEA & IEB & IEC & !ED & !EE & EF_);
(only EA active)
(only EB active)
(only EC active)
(only ED active)
(only EE active)
(only EF active)
(none ofthe inputs active)
COLLISION DETECTION SR-FF:
COLLEN_ = ! (CDT # COLLEN);
(set with collision)
COLLEN_ = ! ( RESET_ # COLLEN_ #
( !CDT & lEA & !EB & !EC & !ED & lEE & EF_);
(reset when aU inputs inactive)
RECEIVE DATA OUTPUT:
RCVDAT = (
(RA # lEA) & ( RB # !EB ) & ( RC # !EC ) &
(RD # lED) & (RE # !EE)&(RF # EF_»;
( output is high if no active input)
1-391
inter
Ap·236
Manchester encoding. Section 3.5 shows that the CPS
has missing mid-cell transitions occurring every two
and a half bit cells. These are detected as Manchester
code violations. Thus, the StarLAN node is presented
with collision detection indications every two and a half
ms. This results in fast and reliable detection of collisions. CPS has a period of5 ms.
The COLLEN signal once triggered will stay active until all inputs go quiet. This signal is used externally to
either enable passing RCVDAT or the collision presence signal (CPS) to the retiming logic. An external
multiplexer using 3 nand gates is used for this function.
Note that in this specific implementation the CPS/
RCVDAT multiplexer is before the retiming logic,
which is different from Figure 42 diagram. StarLAN
provides enough BIT-BUDGET delay to allow the CPS
signal to be generated through the retiming FIFO. In
this HUB implementation it was decided to use this
option to make sure that the CPS startup is synchronized with the previously transmitted bit as required by
the IBASE5 draft.
One may wonder why such a strange looking signal was
selected for CPS. The rationale is that this CPS looks
very much like a valid Manchester signal-edges are
0.5 or 1.0 microsec. apart-resulting in identical radiation, cross-talk and jitter characteristics as a true Manchester. This also makes the re-timing logic for the signals simpler-it need not distinguish between valid
Manchester and CPS. Moreover, this signal is easy to
generate.
6.1.3 THE LOCAL 82588
As described before, the purpose ofthe local 82588 is to
enable the Host IBM/PC to also be a node into the
StarLAN network. The interface of this 82588 is exactly similar to the one explained in section 5. The RTS_
signal serves as the carrier EF_ signal, and TXD as
RF signal. This local node interfaces to the HUB without any analog interface which is a significant saving.
6.1.4 THE COLLISION PRESENCE SIGNAL
The Collision Presence Signal (CPS) is generated by the
HUB whenever the HUB detects a collision. It then
propagates the CPS to the higher level HUB. The CPS
signal pattern is shown in Figure 51. Whenever a StarLAN node receives this signal, it should be able
to detect within a very few bit times that a collision
occurred. Since the nodes detect the occurrence of a
collision by detecting violations in Manchester encoding, the CPS must obviously be a signal which violates
I 2t It I
2t
A few important requirements for CPS signal are: a) it
should be generated starting synchronized with the last
transmitted bit cell. CPS is allowed to start either low
or high, but no bif cell of more than 1 microsecond is
allowed (Avoid false idles, very long "low" bits). b)
once it starts, it should continue until all the input lines
to the HUB die out. Typically, when the collision occurs, the multiplexor in the HUB switches from RCV
signal to the CPS. This switch is completely asynchronous to the currently being transmitted data, and by
such may violate the requirement of not having bit cells
longer than 1 J.l-s. In order to avoid those long pulses,
the output of the CPS/RCVDAT multiplexer is passed
through the retiming circuitry which will correct those
long pulses to their nominal value. The reason for restriction b) is to ensure that the CPS is seen by all nodes
on the network since it is generated until every node
has finished generating the Jam pattern.
I 2t It i t =0.5 )L5
I--S)L5 PERIOD-i
• MISSING MID-CELL TRANSITION
231422-42
• Collision Presence Signal (CPS) is generated by the HUB when it detects more than one input line active.
• CPS violates Manchester encoding rules-due to missing mid-cell transitions-hence is detected as a collision by the DTE (82588).
Choice of Collision Presence Signal
• It is a Manchester look-alike signal-edges are 0.5 or 1.0 J.l-s apart.
- Identical radiation, crosstalk and jitter characteristics
- Eases retiming of the signal in the HUB
• It is easy to generate-1.5 TTL pack, or in a PAL
Figure 51. Collision Presence Signal
1-392
AP·236
CPS is generated using a 4-bit shift register and a flipflop as shown in Figure 52. It works off a 2 MHz clock.
A closer look at the CPS waveform shows that it is
inverse symmetric within the 5 ,...S period. The circuit is
a 5-hit shift register with a complementary feedback
from the last to the first bit. The bits remain in defined
states (01100) till collision occurs. On collision the bits
start rotating around generating the pattern of
0011011001, 0011011001, 00110 ... with each state
lasting for O.S ,...s.
o
6.1.6 RETIMING CIRCUIT, THEORY OF
OPERATION
o
COLLISION
. . - - - - , PRESENCE
SIGNAL
Q
COLLISION
231422-43
Figure 52. COllision Presence
Signal Generation
6.1.5 SIGNAL RETIMING
Whenever the signal goes over a cable it suffers jitter.
This means that the edges are no longer separated by
the same 0.5 or 1.0 ,...S as at the point of origin. There
are various causes of jitter. Drivers, receivers introduce
some shifting of edges because of differing rise and fall
times and thresholds. A random sequence of bits also
produces a jitter which is called intersymbol interference, which is a consequence of different propagation
delays for different frequency harmonics in the cable.
Meaning short pulses have a longer delay than long
ones. A maximum of 62.5 ns of jitter can accumulate in
a StarLAN network from a node to a HUB or from a
HUB to another HUB. The following values show what
are the jitter components:
Transmitter skew
cable Intersymbol interference
Cable Reflections
Reflections due to receiver
termination mismatch
HUB fan-in, fan-out
Noise
Total
a result of jitter, may no longer be decodable. The process of either re-aligning the edges or reconstructing the
signal or even re-generating the signal so that it once
again "looks new" is called re-timing. StarLAN requires for the signal to be re-timed after it has travelled
on a segment of cable. In a typical HUB two re-timing
circuits are necessary; one for the signals going upstream towards the higher level HUB and the other for
signals going downstream towards the nodes.
±10ns
±9ns
±8ns
±5ns
±5ns
±25.5
±62.5ns
It is important for the signal to be cleaned up of this
jitter before it is sent on the next stretch of cable because if too much jitter accumulates, the signal is no
longer meaningful. A valid Manchester signal would, as
This section will discuss the principles of designing a
re-timing circuit. Figure 53 shows the block diagram of
a re-timing circuit. The data coming in is synchronized
using an 8 MHz sampling clock. Edges in the waveform
are detected doing an XOR of two consecutive samples.
A counter counts the number of 8 MHz clocks between
two edges. This gives an indication of long (6 to 10
clocks) or short (3 to 5 clocks) pulses in the received
waveform. Pulses shorter than 3 clocks are filtered out.
Every time an edge occurs, the length-{S)hort or
(L)ong-of the pulse is fed into the FIFO. Retiming of
the waveform is done by actually generating a new
waveform based on the information being pumped into
the FIFO. The signal regeneration unit reads the FIFO
and generates the output waveform out of 8 MHz clock
pulses based on what it reads, either short or longs. In
summary every time a bit is read from the fifo, it indicates that a transition needs to occur, and when to fetch
the next bit. When idle the output of the retiming logic
starts with a "high" level.
FIFO
empty
Output
...... 1111
S
S
0000
L
L
00000000
1111
11111111
It can be seen that the output always has edges separated by 4 or 8 clock pulses-O.5 or 1.0 ,...s.
The FIFO is primarily needed to account for a difference of clock frequencies at the source and regeneration
end. Due to this difference, data can come in faster or
slower than the regeneration circuit expects. A 16 deep
FIFO can handle frequency deviations of up to 200
ppm for frame lengths up to 1600 bytes. The FIFO also
overcomes short term variations in edge separation. It
is essential that the FIFO fills in up to about half before
the process of regeneration is started. Thus, if the regeneration is done at a clock slightly faster than the
source clock, there is always data in the FIFO to work
from. That is why the FIFO threshold detect logic is
necessary, which counts 8 edges and then enables the
signal regeneration logic.
1-393
inter
AP-236
Example:
Input Waveform
'... 11110001111000000011111111110001111100 ...
I
Input into
the FIFO
I
<8> <8>
I
I I
I
. <8>
Regenerated Output:
... 111110000111100000000111111110000111 ...
Output:
FIFO:
I I I
I
I I
<8> <8>
INPUT
DATA
--+
<8> <8>
PULSE WIDTH
DISCRIMINATOR
EDGE
DETECTOR
SYNCHRONIZER
8MHZ~LOCK
INCREMENT EDGE ~
COUNTER
• FIFo ACCOMMODATES FOR FREQ •
DR IFTS (SPEC 100 PPM)
LOAD!
FIFO
FIFO
THRESHOLD
DETECT
• MAX DRIFT:
(1 500 BYTES x 8) x 200 PPM = 2.43 BT
SHORT/LONG
INFO
FIFO
FIFO OUTPUT
ENABLE SIGNAL
REGEN ERATlON
SIGNAL
REGENERATION
--+ OUTPUT
231422-95
Figure 53. Retiming Block Diagram
6.1.7 RETIMING CIRCUIT IMPLEMENTATION
The retiming circuit implementation can be seen in Figures 47, 48. Both figures implement exactly the same
function, one for the upstream, and the other for the
downstream. The retiming circuit was implemented using about 8 SSI, MSI TIL compOnents, one fifo chip
and one PAL. The purpose of implementing this function with discrete components was to show the implementation details. The discussion of the implementation will refer to Figure 47 for unit numbers.
The signal UPIMP which is an output of the HUB
multiplexing logic, is asynchronous to the local clock.
This signal is synchronized by two flip-flops and fed
into an edge generation logic (basically an XOR gate
that compares the present sample with the previous
one). On every input transition a 125 ns pulse will be
generated at the output of the edge detector (U28). This
pulse will reset the 74LS161 counter that is responsible
for measuring pulse widths (in X8' clock increments).
The output of the pulse discriminator will reflect the
previous pulse width every time a new edge is detected.
The following events will take place on every detected
edge:
1. U26 which is the threshold detector will shift one
"1" in. The outputs of U26 will be used by the control PAL to start the reconstruction process.
2. The output of U23 whis:h specifies the last pulse
width will be input into the control PAL for determining if it was a long or short pulse. The result of
this evaluation will be the LSIN signal which will be
loaded into the fifo (U22).
U22 is the retiming FIFO, it is 16x4 fifo, but only one
bit is necessary to store the SHORT/LONG information.
1-394
inter
AP-236
CONTROL LOGIC PAL functions (U25):
Terminal count of the reconstruction
counter, indicating that reconstruction
of a new bit will get started.
Output of the FIFO indicating, that the
FIFO is empty and that IDLE generation can get started.
CNTTC:
Signals definition:
INPUTS:
PDO.. PD3:
EDD_:
THRESH:
CNTEN:
CNTEND:
OUTDAT:
RESET_:
OR:
Outputs of the pulse descriminator, indicate the width of the last measured
pulse.
Output of the edge detector, pulse of 125
ns width, indicates the occurrence of an
edge in the input data.
Output of the threshold logic, indicates
at least one bit was already received.
Output of the Threshold logic, indicates
7 bits have been loaded into the FIFO,
and that signal reconstruction can begin.
The same signal as before delayed by one
clock.
Output of the retiming logic, is feedback
into the PAL to implement a clocked
T-FF.
Resets the retiming logic.
OUTPUTS:
LDFIFO_:
Loads SHORT/LONG indications into
the FIFO.
Indicates SHORT/LONG
Loads FIFO SHORT/LONG output
into the reconstruction counter.
Together with the external U21 flip-flop
and OUTDAT implement a clocked
T-FF.
LSIN:
CNTPE_:
ODAT:
Loading the FIFO will be done every time there is an
edge, we have passed the one bit filter threshold level,
and the pulse width is longer than two 8X clocks. This
one bit threshold level serves as a time domain filter
discarding the first received preamble bit.
LDFIFO_ = ! ( PDl "" PD2 "" PD3 ) &: !EDD_ &: THRESH ) ;
Whenever there is an edge, we are above the first received bi t threshold
and the pulse "idth is longer than '1' the fifo is loaded.
LSIN
=! (PD3 "" (PD2 &:
PD~)
"" (PD2 &: PD1»;
Every pulse longer than 8 is considered to be a long pulse.
CNTPE_ = ! ( (CNTEN &: !CNTEND) "" CNTTC );
The reconstruction counter is loaded in two condi tions I
Whenever eNTEH oomes aoti ve. meaning the FIFO threshold ot seven was exoeeded.
Whenever the terminal count of U24 is active meaning a new pulse is going to be reconstructed.
ODAT
= !RESET_ "" (!CNTPE_ &: !OUTDAT)
"" ( CNTPE_ &: OUTDAT)
"" (!CNTPE_ &: lOR)
(A)
(B)
(C)
Minterm (Al and (Bl implement a T-FF. whenever eNTPE.is 'low'
ODAT "ill toggle. The external U21is part of this flip-flop.
Minterm (el insures the output of the flip-flop will go inactive
'high' when the FIFO is empty. RESET. oauses the output to go
"high' on initialization.
1-395
inter
will be started, and Tl will time out after 25 to 50 ms.
T2 will time-out after 51 to 100 ms. During T2 time,
after Tl expired, the HUB will send the CP-PAT~
TERN informing any jamming stations to quit their
transmissions. If on T2 time-out there are still jamming
ports, their input is going to be disabled. A disabled
port, will be reenabled whenever its input becomes
again active and the downward side is idle.
U24 as mentioned is the reconstruction counter. This
counter is loaded by the control logic with either 8 or
12, it counts up and is reloaded on termjnal count. Essentially generating at the output n9minallength longs
and shorts.
U22 is the retiming FIFO, and its function as mentioned is to accommodate frequency skews between the
incoming and outgoing signal.
U27 is the IDLE generation logic. The purpose of this
logic is to detect when the FIFO is empty, meaning that
no more data needs to be transmitted. On detection of
this event this component will generate 2 ms of IDLE
time. On the end of IDLE the whole retiming logic will
be reset.
The following is an explanation of the requirement that
the downward side be idle to reenable an input port.
Consider the case of Figure 54. The figure shows a two
port HUB. Port A has two wires Au, Att for the up and
down paths. Port B has Bu, Bd respectively. Port C is
the output port, that broadcasts to the other HUBs
higher in the hierarchy. Consider the case as shown,
where Bu and Bd are shorted together. Suppose the case
that port Au is active. Its signal will propagate up in the
hierarchy through
and come down from Cd to Ad,
and Bd' Due to the short between Bd and Bu the signal
will start a loop, that will first cause a collision and jam
the network forever. This kind of fault is taken care of
by the jabber circuitry. Tl and T2 will expire, causing
the jabber logic to disable Bu input. Upon this disabling
Bu is going to go Idle and be a candidate for future
enabling. Suppose now that Au is once again active. If
the reenable condition would not require Cd to be
IDLE, Bu would be reenabled causing the same loop to
happen once again. Note that in this case Cd will be
active before Bu causing this port to continue to be
disabled and avoiding the jamming. situation (Figure
55) gives a formal specification of the jabber function).
en
6.1.8 DRIVER CIRCUITS
The signal coming out of the RETIMING LOGIC is
fed into 26LS30s and pulse transformers to drive the
twisted pair lines (~e section 5.0 for details).
6.1.9 HEADER/INTERMEDIATE HUB SWITCH
As seen on Figure 43 this hub can be configured as
either an intermediate hub, or a Header one. One of the
phone jacks, more specifically JACK # 5 is either an
input port or an output one. In order to implement this
function, an 8 position DIP SWITCH (SW1) is used.
The phone jacks are marked with UD, DO notation,
meaning upstream data, and downstream data respectively. As specified in the StarLAN IBASE5 draft
NODES transmit data on UD pair, and HUBS on the
DO pair. Switch SWI has the function to invert UD,
DO in PHONE JACK #5 to enable it to ·be either
input or output port.
6.1.10 JABBER FUNCTION
This design does not implement the jabber unit but it is
described here for completeness. IEEE 802.3 does not
mandate this feature, but it is "Strongly Recommended". The jabber function in the HUB protects the network from abnormally long transmissions by any node.
Two timers Tl, T2 are used by the JABBER function.
They may be implemented either as local timers (one
for each HUB port) or as global timers shared by all
ports. After detecting an input active, timers Tl, T2
1-396
231422-96
Figure 54. Jabber Function
AP·236
Power On
'"
_____ ~~B!I!..I!?L..E _____
INPUT (X) = active
+- Walt for Input oc:tlv •.
I.
+'
JABBER WATCH
.-st~rt_jo-bbe;n';.1-
-----
+- Input Is active,
activate timers 11. T2 .
If Input goe' Idle, then It was a
normal transmIssion. Otherwise If
• storLjobber Time 2
INPUT (X) = Idle
I
_____
!
Jobber Timer 1 expires, the transmIssion
JabberTimo Ldon •• INPUT(X) =actlv.
Is megol. Start generating collision
:!.A~B..EI!.. :!.A~
pattern In .tate JABBER JAM.
_____
• Jobber_collision
- , probatlon_alternotlve'
• INPUT (X) = idle
+- VarIable probation_alternative Indicates
1
two possible ways of Implementing the function.
Implementation of
«(jabber Time Ldone + INPUT(UPPER) = Idle)
.INPUT (X) = active
+ (probation altornatlv"INPUT (X) = Idle)
- T2 expires.
-INPUT(UPPER) = Idle .INPUT (X) = actlv•
It means thot the current HUB was
SHUTorr by Q higher hierarchy one.
This one will also SHUTOrr with the
purpose that a jamming input be
DISABLED at the lowest possible level.
.1INPUT (X) = Idle
-INPUT(X)" idle
Two alternatives are allowed:
Go back to JABBER IDLE, or
go to the SHUTOFF stot••
JABBER PROBATION
.-dj;;bj;,..:inP~t (x)
one Is allowed.
Conditions for going to stat. JABBER SHUTOFF
JABBER SHUTOFF
• -dj;a-bj;,..:in-p~t (X) - - - - - - -
INPUT (X) = actlve .INPUT(UPPER) = actlve1.
elth~r
-------
I INPUT (X) = active .INPUT(UPPER) = Idle
' - On stote JABBER SHUTOFF, tho
Input i~ disabled.
' - - - Input will be reenablect [f Input Is active,
and the upper port Is quiet.
231422-99
Figure 55. Jabber State Diagram
6.1.11 HUB RECEIVER PROTECTION TIMER
On the end of a transmission, during the transition
from IDLE to high impedance state, the transmitter
will exhibit an undershoot and/or ringing, as a consequence of transformer discharge. This undershoot!
ringing will be transmitted to the receiver which needs
to protect itself from false carriers due to this effect.
One way of implementing this protection mechanism is
to implement a blind timer, which upon IDLE detection will "blind" the receiver for a few microseconds.
Causes of the transmitter undershoot/ringing:
1. Difference in the magnitudes of the differential output voltage between the high and the low output
stages.
2. Waveform assymmetry due to transmitter jitter.
3. Transmitter and receiver inductance (transformer
L).
All the described elements will contribute to energy
storage into the transformer inductor, which will discharge during the transition of the driver to high impedance.
The blinding timer is currently defined to be from 20 to
30 microseconds for the HUBs, being from 0 to 30 microseconds for the nodes (optional). The 82588 has
built-in this function. It won't receive any frames for an
inter-frame-spacing (IFS) from the idle detection.
6.1.12 HUB RELIABILITY
Since the StarLAN HUBs form focal points in the network, it is important for them to be very reliable, since
they are single points of failure which can affect a number of nodes or can even bring down the whole network. StarLAN IBASE5 draft requires HUBs to have
a mean time between failures (MTBF) of at least 5
years of continuous operation.
4. Two to three microseconds of IDLE pattern.
1-397
AP-236
7.0 SOFTWARE DRIVER
7.1.1 DOING I/O ON IBM PC
The software needed to drive the 82588 in a StarLAN
environment is not different from that needed in a generic CSMAlCD environment. This section goes into
specific procedures used for pperations like TRANSMIT, RECEIVE, CONFIGURE, DUMP, ADDRESS
SET-UP, etc. A special treatment will be given to interfacing with the IBM PC-DMA, interrupt and I/O.
The safest way to use the PC monitor as an output
device and the keyboard as the input device is to use
them through DOS system calls. The following is a set
of routines which are handy to do most of the I/O:
key$stat
-to find out if a new key has been
. pressed
keyin$noecho -to read a key from the keyboard
char$out
-to display a character on the screen
-to display a character string on the
msg$out
screen
-to read in a character string from the
line$in
keyboanJ
Since all the routines were written and tried out in
PLM-86 and ASM-86, all illustrations are in these languages.
The following software examples are pieces of an 82588
exerciser program. This program's main purpose was to
exercise the 82588 functionality and provide the functions of traffic generation and monitoring. By such the
emphasis was on speed and accuracy of statistics gathering.
7.1 Interfacing to IBM PC
The StarLAN board interfaces to the CPU, DMA controller and the interrupt controller on the IBM PC system board. The software to operate the 82588 runs on
the system board CPU. The illustrated routines in this
section show exactly how the software interface works
between the system resources on the IBM PC and the
StarLAN board.
Ids dX,STRING_POINTER
mov ah,09h
int 2lh
The exact semantics and the protocol for doing these
functions through DOS system calls is shown in the
listing in Figure 56. Refer to the DOS Manual for a
more detailed description. To make a DOS system call,
register AH of 8088 is loaded with the call Function
Number and then, a software interrupt (or trap) 21 hex
is executed. Other 8088· registers are used to transfer
any parameters between DOS and the calling program.
The code is written in Assembly language for register
access. Let us see an example of the 'msg$out' routine:
load pointer to string in reg. ds:dx
9 function number for string o,p
DOS System Call
=
These procedures are called from another module, written in a higher level language like PLM-86. The parameters
are transferred to the ASM-86 routines on the stack.
Examples of using the I/O routines:
=
KEY_STATUS
key$stat;
NEW_KEY = keyin$noecho;
call line$in(@LINE_BUFFER) ;
call char$out(CHAR_OUT) ;
call msg$out (@ ( 'THIS IS A MESSAGE. $') );
,.
/*
,"
,.
/*
/*
1-398
*'*'
*'
"'*'
INQUIRE KEYBOARD STATUS
INPUT NEW KEY
STRING INPUT
TO OUTPUT CHAR_OUT ON SCREEN"'
OUTPUT STRING
NOTE $ TERMINATOR
inter
AP-236
.
..
/ ------ ----- ------------ -- - ---------------------- -- ------------- ----------_ /
Deolarations for ezternal IBli PC I/O routines
'/
/ .. ----------------------------------------------------- --------------------- */
/'
key' stat : prooedure byte ezternal;
end key' stat ;
/' key status routine ,/
!:i{Si:!~~~:~~oE~~osdure byte ezternal;
char'out: prooedure(ohar) ezternal;
deolare char byte;
end
out ;
/' oonsole input routine '/
/' oonsole output routine 'I
char'
meg.out: proosdure(msgSptr) ezternal;
deolare msgSptr pOinter;
end megSout;
I'
oonsole string output routine
l1ne$1n: prooedure(lineSptr) ezternal;
deolare lineSptr pOinter;
end l1ne.in;
I'
oonsole string input routine
Asselllbly Language implementation of the routines
STITLI!(IBlI/PC
DOS CALLS PROCEDURBS)
NAIIE
OOROtlP
DOSPROCS
CGROOP
GROUP
GROUP
DATA
DATA
SEGIIBIIT WORD PtlBLIC 'DATA'
BlIDS
Dos
B~
CoDB
DATA
CODB
21B
SBGIIBNT WORD PUBLIC 'CODE'
ASStlllB CS : CGaoup ,DB: llGaoup
231422-58
CHARSOUT: PROGEDURE(CHAR) EXTERNAL;
DECLARE CHAR BYTE;
END CHARSOUT;
OUtputs oharaoter to the soreen.
DOS system oall 2
CHAR
CHAROUT
CHAROOT
EQU
PUBLIC
PUSH
MOV
MOV
MOV
INT
pop
RET
[BP+41
PROC
NEAR
CHAROUT
BP
BP,SP
DL,CHAR
AH,2
DOS
BP
2
ENDP
STACK
+------+
I CHAR I %
+------+
lIP 10 I %-1
+_ .... _---+
lIP hi !
%-2
IBP 10
%-3
+------+
!
+------+
IBP hi I %-4
<--SP
+------+
KEYINSNOECHO: PROCEDURE BYTE EXTERNAL;
END KEYIN$NOECHO;
Reads charaoter without eohoing to display
KEYINNOECHO PROG
PUBLIC
MOV
INT
RET
KEYINNOECHO ENDP
NEAR
KEYINNOECHO
AH,6
DOS
(DOS oall 6)
Figure 7-56. 1/0 Routines for IBM/PC
Figure 56. 110 Routines for IBM/PC
1-399
(oontinued)
231422-59
intJ
AP~236
IISG$OCT: PIIOCBDtIRE(IISG$PTR) EXTIIIUIAL;
DECLARE IISG$PTR POINTER;
l!IID IISG.OCT;
/. IIOTB: IIBSSAGB IS TJIRIIINATIID WITI! A llOLLAR BIGR • /
IISG.PTR is doubls word pOinter SBG:orrsBT
IISCLL
IISGJI
PtlBLIC
PlJ811
IIOV
IIOV
PlJ811
IIOV
!IOV
IIOV
INT
POP
POP
IISGOOT
BQtJ
BQtJ
[BP+4]
[BP+8]
PROC
IISGOll'l'
BEAR
BP
BP,SP
DE,IISGJo
DB
AX,IISGJI
DS,AX
AH,9
(DOS oall 9)
DOS
DS
BP
4
INDP
RET
LIlIBUlI: PIIOClIIlURB(LIlII.PTR) ErrBRlIIAL;
DBCLARB LIlliS PTR POINTBR;
l!IID LIlIBUlI
[BP+4]
[BP+8]
LIlIIILL
LINIJI
LIlIIIN
PtlBLIC
PlJ811
!IOV
PlJ811
!IOV
IIOV
IIOV
IIOV
INT
POP
POP
RET
LIlIIIN
PROC
lIIAR
LIlIIIlI
BP
BP,SP
DS
AX,LIlIIJI
DS,AX
m:, LIlIIILL
AH,lO
DOS
(DOS oall 10)
DS
BP
4
l!IIDP
231422-60
EEY.BTAT: PRCCBDORII BY'll BrrBRlIIAL;
BND EBY$STAT;
IDd10ateB whether any keyboard key was presBed.
EBYSTAT
PROC
PUBLIC
IIOV
INT
RET
EEYBTAT
ixm
BEAR
EEYSTAT
(DOS oall 11)
AH,ll
DOS
l!IIDP
BNDB
l!IID
231422-61
Figure 56. I/O Routines for IBM/PC (Continued)
7.2 Initialization and Declarations
Figure 57 shows some declarations describing what addresses the devices have and also some literals to help
understand the other routines in this section.
Figure 58 shows the initialization routines for the IBM
PC and for the 82588. It also shows some of the typical
values taken by the memory buffers for Configure,
I~et, Multic~~t and transmit buffers.
1-400
inter
Ap-236
Following are some literal declarations that are used in the procedure examples
l'ol1ow1"11 are 80lIl8 l1teral
procedure ezample.
deolare
deolarat1ons
,0
literally '080Ob' ,
l1terally '0301b'
l1terally '081b'
11terally '02Ob'
l1terally '0&11'
11terally 'OlI!I'
l1terally 'COh'
l1terally '02b'
l1terally 'OISh'
l1terally '081Sh'
l1terally '081>.'
l1terally '07h'
11terally '082b'
l1terally 'Olb'
literally 'OISh'
11terally 'Ollb'
11terally '07h'
11terally 'OcI.fb'
11terally '08l1b'
l1terally
'1'
11terally
'0 '
11terally '04l1b'
11terally '047h'
11terally '04911'
11terally '04I>b'
tbat
are
u8ed
1n
the
0,
,0,0
,0,0,0
,0
,0,0,0
,0,0
,0
,0,0,0
,,0'*
'*
,'*'*'*
'*'*'*
8BII88 OOMMAHD'8TATUS
DIIA'III'rIIRUPT IIBAIILB PORT
8BllIIA IIASI RlGISTBII
821111A OOIIIWIII WORD 2
8215'7A lIAR RlGISTBII
8211'7A IICDlI RlGI8TBII
821S'7A ll1T'utI BY'1'I FLOP
aBIS'7A CIWIIIIIL 1 AID. RIG.
82S'7A CIWIIIIIL 1 BY'l'II comrr
CIWIIIIIL 1 PAGI RlGI8TBII
821S'7A CIIA1IlIBL II ADmI. RIG.
8Ba'7A CIIA1IlIBL 15 BY'1'I OOUJIT
CIrAIIJIIIL IS PAGI RlGI8'lIII
START CIWIIIIIL 1
START CIIA1IlIBL IS
STOP CIWIIIIIL 1
STOP CIWIIIIIL II
1J1IIIAR I1ITIRIIUPT L1VBL II
SPICIPIC IOI LIVBL 15
IIIIIORY TO 8BII88
821188 TO IIIIIORY
lilt OK CIWIIIIIL • 1
lilt OK CIrAIIJIIIL • 15
Tlt OK CIWIIIIIL • 1
Tlt OK CIWIIIIIL • IS
0,0,0,
0,0,
0,0,0,
0,0,
0,0,0,
0,0,
0,
*'*'0,
*'*'*'
*'*'
231422·62
Figure 57. Literal Declarations
Initialization Routines
Initialization rout1Des
,0 SYSTEII INITIALIZE 0,
BYB.iD1t: prooe4ure;
0811 set$1nterrupt (13,1ntr.IIBB);
output(piO.Jll&Blt) • input(pio.JII&Bk) and enalIle.1I8B;
output(piO.OOWB) seol..pJ.oo;
,0,0 ENABLE
BASE B, LIVIL II
0,
IIB8 I1ITIRII. 0,
,0
,0
,...................................................,
0,0,
,0,0
Wl'.ptr, rcLptr, fUoont-O;
ACES PB1IDING INTlIIIIIo,
RBSBT IITATUS 1'11'0
0,
OONVBRT SEG: OJ'I'SBT POlIIIAT TO 110 BIT ADDRIISSBS
POR ALL TIll! BllP1'BRB
,...................................................
1a.et_~ad4r
ODf_~ad4r
:~~
/
• oonvert_BOb1t.ad4r(01~et~ff.B88(0»;
• oonvert-2Ob1t.ad4r~OOOnf~lIa8(0»;
:• ~:=::~i~::=(=1oe!!::=~~6~~(0»;
t~~ad4r
oonvert-2Ob1t.ad4r(Ot~ffer.88B(O»;
401-oto'7;
~daa-ad4r(1)·oonvert_BOb1t.ad4r(Or~ffer(1).butf(O»;
end;
output (brcLport).Offb;
,. BNABLI DIIA
AlII)
I1ITIIRRUPT DRIVERS
0,
eDd sYB.1D1t;
BBBBB 1D1t1al1zation
1D1t_IIBB: procedure;
oont1I1.BB8(00)
OOnt1I1.IIB8(01)
oonfill.1I88(08
Oonfil-flBB(OI5)
oont11-158B(04)
oont1I1.BI5B(OB)
oont1I1.IIBB(06)
ooDf1I1.BB8(0'7)
ooDf1I1.IIBB(OB)
oantil-IIB8(OS)
oantill.IIB8(10)
oODt11-1188(11)
•
•
•
•
•
•
•
•
•
•
10;
00;
0000100()l);
bufelen'4;
0010011011;
0000000()l);
96;
0;
1111001011;
0000010011;
1000100011;
64;
,0 TO OON1'IGIJRI ALL 10 PA1IAIIlITIIRS
,0 IIODlI 0, B IOIZ CLOClt, 1 lIB'S
,0 RBCBIVB BlIPI'D LlNGTII
'*'*
,0
,.
/*
/0
,0
/.
NO LOOPBACX, AID LIN • B, PRBAIIBLI • 8
DII'1'BRDTIAL IlAllCllBSTBII - OJ'!'
Il'S • 96 '1'CLIt
SIm TlIIB • nB '1'CLIt
IIAX. NO. RII'lRIIIS - 115
IlAllCllBSTIR IINOODING
INTBIINAL ORS AlII) CD'l', ORS!' - 0
IIIN PIIAIIII LINGTII • 64 BY'l'IIS - 151B BITS
Figure 58. Initialization Routines
1-401
*/
0/
0/
0/
0/
0/
0/
*/
*/
0/
./
231422·63
inter
AP-236
1a_seLbufC588(0)
ie...set_bufC588(l)
ie...setJ>ufC888(2)
:1. .._set_buff_588(3)
i .._setJ>ufC588(4)
i .._setJ>ufC588(5)
i .._set_ufce88(6)
ie...set_bufC588(7)
-
6;
0;
OOOh
041h
OOOh
OOOh
OOOh
OOOh
multioas1;J>ufC588(00)
multioastJ>ufCS88(01)
multioastJ>ufCS88(02)
multioastJ>uff_S88(03)
multioast_bufC888(04)
multioastJ>ufC58S(08)
multioastJ>ufce88(06)
multioast_bufce8e(07)
multioast_buff_See(Oe)
multioast_bufCSee(09)
multioast_buff_see(lO)
multioast_buff_See(ll)
multioastJ>uff_5ee(12)
multioastJ>ufceee(l3)
- 12;
- OOh
- llh
- 12h
- 13h
- 14h
- lSh
- 16h
- 21h
- 22h
- 23h
-24h;
- 2Sh;
- 26h;
txJ>uffel'_588(OO) - tz-fl'&me_len mod 256;
t,,_buffel'_588(01) - tz-fl'&me_len / 256;
i~~~:;:::g~~~g:~
gg~;
INITIAL DESTINATION ADDRESS - IICO) ' /
t"J>uffel'_S88(04) - 013h;
t,,_buffel'_S88(05) - 014h;
t,,_buffel'_S88(06) - 015h;
txJ>uffel'_S88(07) - 016h;
:
/'
end :!.nit_S88;
231422-64
(Continued)
fourth parameter = pointer to a 20 bit
address of the
memory buffer
(=@CONFIG_588_ADDR)
Figure 58. Initialization Routines
7.3 General Commands
Operations like Transmit, Receive, Configure, etc. are
done by a simple sequence of loading the DMA controller with the necessary parameters and then writing
the command to the 82588.
Example: Configure Command
To configure the operating environment of the 82588.
This command must be the first one to be executed
after a RESET.
call
DMA_LOAD(1,1,12,@CONFIG_588_ADPR) ;
output (CS_588) = 12h;
The first statement is the prologue to the configure
command to the 82588 which calls a routine to load
and initialize the DMA controller for the desired operation. This routine is described in section 7.4. The parameters for DM~LOAD are:
The second statement writes 12h to the command register of the 82588 to execute a Configure command on
channel 1.
When the command execution is complete (successfully
or not), 82588 interrupts the 8088 CPU through the
8259A, on the system board. This executes the interrupt service routine, described in section 7.5, which
takes the epilogue action for the command.
Most operations are very similar in structure to Configure. The 82588 Reference Manual describes them in
detail. Figure 59 shows a listing of the most commonly
used operations like:
CONFIGURE
TRANSMIT
first parameter
= 82588 channel
number ( = 1)
second parameter = direction ( = 1,
memory > > 82588)
third parameter = length of DMA
transfer ( = 12)
DIAGNOSE
DUMP
TDR
RETRANSMIT
1-402
INDIVIDUAL-ADDRESS (IA)
SET-UP
MULTICAST-ADDRESS (MC)
SET-UP
RECEIVE (RCV)-ENABLE
RECEIVE (RCV)-DISABLE
RECEIVE (RCV)-STOP
READ-STATUS
intJ
Ap·236
/. COIIIIAJ1D - 01 • /
1e....set: procedura p1Il>l1o;
oall 4ma-l0a4(~ob&Dnal.t~41r.8 ••1&set_dae....ad4r);
/. SB:r InIA CJIAIIIIJ!L 0 011 1 ro 'I.'RA1IISJ'BR PROII IIBIIOIIY
ro 'l'BB 811S8B. 1uat_dm&..B44r VARIABLB B:rOIlBB 'l'BB
110 BI:r POIlITBR ro 'l'BB IHDIVIDtlAL AIlIlIIIIBS BtJ1ITBR 0/
i f ~oluwI.l then output (oB_888) • 1111;
a18e output(OB_1I88) • 0111;
/0 BVlRY COKIIA1ID CAN II IIBIICll'1'III) IN BI':IIBR InIA CIWOOIL 0 011 1.
'l'BB VARIABLB ~oII_l IIIDICA'l'B8 'l'BB ~IRBIl CIWOOIL 0/
eDd 1e..... .t;
'* --------------------------------------------------------------------------*'
conn.: pro0e4ure publio;
/0 COKIIA1ID - 011 0/
call dme....loa4(~OII&Dn&l. t~41r. 111 .000f_dme....ad4r) ;
i f ~oII_l tIleD output (08_888) • 1l1li;
a18a output(OB_888) • Oh;
aDd oonfi.;
'* --------------------------------------------------------------------------*/
ault10ut: pro0e4ura p1Il>l1o;
/. COKIIA1ID - 08 • /
oall dm&..loa4(~0II&Dn&1.t~4ir.14 ....0_dae....ad4r);
i f ~oII&DDal then output (os_688) • 1811;
al. . output(os_688) - 0311;
eD4 lINltioast ;
/* --------------------------------------------------------------------------*'
traulD1t: prooe4ura(bui':L'ar_lsn) p1Il>l1o;
/0 COIIIIAJ1D - 04 0/
dealara buffar_lliln wOrd;
t~ffar_8B8(00)
t~ffar_68B(01)
• low(bui':L'ar_lan);
- h1g11(buffar_lan);
oall dm&..loa4(~OII&Dn&l. t~4ir. 1636. etz_dm&..B44r) ;
~0II&Dn&1 then output (OS_888) - 1411;
al.. output (os_888) - 0411;
if
aDd translD1 t ;
231422-65
Figure 59. General Commands
1-403
inter
Ap·236
tdr: procedure publ1o:
COIIIIAND - 06
/ 0
0 /
if OIIId_ohaimel the.. output (oS_566)' - 16h:
elss output(os_566) - OSh:
end tdr:
'* --------------------------------------------------------------------------* /
dump_B66: prooedure publ1o:
/0 COIIIIAND - 06 • /
0&11 dma."':load( OIIId_ohennel. rlt_dir. 64. OdmP_dmlLaddr) :
i f omc:LOhennel the.. output (OS_666) - 16h:
else output(os_S66) - 06h:
end dump_S66:
I
*---------------------------_______________________________________________ * /
diag..ose: prooedure publ1o:
/ 0 COIIIIAND - 07 • /
~ohannel
the.. output (os_566) • 17h:
else output(os_S6S) - 07h:
if
end diag ..ose:
/ III - - - - - - - - - - - - - - - - __________________________________________________________ III
_"0 .le.. )
rov_e..al>le: prooedure (ohannel. buffer
publ1o:
I
/. COIIIIAND - 06 • /
deolare channel l:>yte:
deolare le.. word:
deolare buffer_no l:>yte:
oall dma_load( Ohennel. l'lt_dir .le... a>rx_dma_addr(buffer_..o)) :
!is!"o~~~~~s~~:~) o~tE~t (oU6S) - lSh:
/. --------------------------------------------------------------------------* /
rov_disal>le: procedure publio:
/0 COIIIIAND - 10 • /
enable_rov-Q ;
output(os_588)-Oah:
e ..d l'OV_disal>le:
231422-66
/ .. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ____________________________________ III /
rov_stop: prooedure publio:
/. COIIIIAND - 11 0/
enal>le_rov-O :
output(os_58S)- Obh:
end rov_stop:
I *--------------------------------------------------------------------------* I
retransmit: procedure publio:
/0 COIIIIAND - 12 ./
oall dmlLload(omd_oh....nel. tX_dir.1536,fPt;lt_dma_addr):
if omc:LOhennel the" output (os_688) - loh:
else output(os_5S8) - Ooh:
end retransmit;
I
*--------------------------------------------------------------------------* I
abort: procedure publio:
/0 COIIIIAND - 13 • /
~~iru~i~~8~:~~;( i~:
end abort:
1* --------------------------------------- ----------------------------------_ * I
reset_s68: prooedure publio:
/0 COIIIIAND - 14 • /
e ..al>le_l'ov-O :
output(os_586) - leh:
oall oonfil!:
'end reset_5B8:
231422-67
Figure 59. General Commands (Continued)
1~404
inter
AP-236
the listing of this procedure. It accepts 4 parameters
from the calling routine to decide the programming
configuration for the 8237A. The parameters for
DMA_LOAD are: Channel, direction, bufLJen, and
buff_addr.
7.4 DMA Routines
DMA_LOAD procedure is used to program the
8237A DMA controller for all the operations requiring
DMA service. It also starts or enables the programmed
DMA channel after programming it. Figure 60 shows
Converting a pOinter SEG: OFFSET to a 20 bit eddress
oonverL20bi Leddr : prooedure(ptr) dword publio;
deolare
ptr
ptr_eddr
pOinter,
pOinter,
f;~d20~~~e~w~~~_a.ddr ) (2)
word;
ptr_eddr-Ciptr;
ptr_20b1t-shl( (ptr_20b1t :-wrd(l)) ,4)+wrd(0);
return(ptr_20bit) ;
end oonvert_20bit_eddr;
IBM/PC DHA lOeding prooedure
dm8..-1oed: prooedure( channel, direotion, buff_len, bufCeddr) reentrant publio;
deolare
deolare
deolare
deolare
deolare
ohannel byte;
direotion byte;
bufClen word:
bufCeddr pOinter;
(wrd based buff_eddr)(2)
channel-ohannel and 1;
/' Cl!ANIIBL ., 0 or 1
/' o-ax, 588 -> !lE1I; l-TX, !lE1l
/' BYTE COUNT
/' BUFFER ADDR IN 20 BITS FORI!
word;
'/
->
688 '/
'/
/' GET LEAST SIGNIFICANT BIT
if ohannel-O then
/' EDCOTE COIIIIAND ON Cl!ANIIBL
do;
output (dma_flff) - 0;
/' CLEAR FIRST/LAST FLIP-FLOP
if direotion-O
then output(dma_mode)-dma_rz_mode_l; /' DIRECTION BIT, TELLS
else output(dm8..-mode)-dma_tx...mode_l;
/' TRANSIlIT OR RECEIVE
output (dma_eddr_l) - low (wrd(O));
/' LOAD LSB ADDRESS BYTE
output (dmB..-eddr_l) - high(wrd(O));
/' LOAD IISB ADDRESS BYTE
output(dma_eddrh_l) - low (wrd(l));
/' LOAD PAGE REGISTER
output (dma...bo_l)
- low (bufClen);
/' LOAD LSB BYTE COUNT
output (dmB..-bo_l)
- high(bufClen);
/' LOAD IISB BYTE COUNT
output(dma_m .. sk) - dm.._on_l;
/' START Cl!ANIIBL 1
'/
'/
'/
'/
,/
'/
'/
'/
'/
,/
'/
'/
end;
else do;
/' SAllE, AS BEFORE FOR CBANNEL 3
- 0;
then output(dma...mode)-dme._rx_mode_3;
else output (dm.._mode)-dmB..-tz...mode_3 ;
output (dm.._eddr_3) - low (wrd(O));
output (dma_eddr_3) - high(wrd(O));
output(dm.._eddrh_3) - low (wrd(l));
output (dm.._bo_3)
- low (bufC'len);
output (dm"_bo_3)
- h1gh(buff_len);
output(dm.._mask) - dm8..-0D.,.3;
~~t~~;~~t;~:6f)
'/
end;
end dmB..-loed;
231422-68
Figure 60. DMA Routine
1-405
intJ
AP-236
One peculiarity about this procedure is that in order to
speed up the DMA step-up, this procedure doesn't get a
pointer to the buffer, but a pointer to a 20 bit address in
the 8237 format. The 8088/8086 architecture define
pointers as 32 bits seg:offset entities, where seg and offset are 16 bit operands. By the other hand the IBMIPC
uses an 8237 A and a page register, requiring a memory
address to be a 20 bit entity. The process of converting
a seg:offset pointer to a 20 bit address is time
consuming and could negatively affect the performance
of the 82588 driver software. The decision was to make
the pointer/address conversions during initialization,
considering that the buffers are static in memory (essentially removing this calculation from the real time
response loops).
Figure 61 is a listing of the DM~OAD procedure
for the 80188 or 80188 on-chip DMA controller. It has
the same caller interface as the 8237A based one.
dma_Ioad: procedure(channel,direction,trans_len,buff_addr) reentrant;
/* To load and start the
80186 DMA controller for the desired operation */
dma_r~ode
literally '1010001001000000b'; /* rx channel */
/* src=IO, dest-M(inc), sync-src, TC, noint, priority, byte */
declare
dma_t~ode ' literally '000011010000000b'; /* tx channel */
/* src=M(inc), dest-IO, sync=dest, TC, noint, noprior, byte */
declare
declare
declare
declare
declare
channel byte;
direction byte;
trans_len word;
buff_addr pointer;
/* channel
/*
o -
'*
rx, 588
/* byte count
*/
->
mem; 1 - tx, mem
->
588 */
*/
/* buffer pointer in 20 bit addr. form
*/
declare (wrd based buff_addr)e2) word;
do case channel and 00000001b;
do case direction and OOOOOOOlb;
do;
/* channel 0, 588 to memory */
output(dma_O_dpl) = wrd(O);
output (dma_O_dph) - wrdel);
ou t pu t (dma_O_s pi) = cb...a_5~8;
output (dma_O_sph) - 0;
output (dma_O_tc)
- trans_len;
output (dma_O_cw)
- dma_r~ode or 0006h; /* Start DMA chI 0 */
end;
do;
/*
output(dma_O_dpl)
output (dma_O_dph)
output(dma_O_spl)
ou tpu t (dma_O_s ph)
ou tpu t (dma_O_t c)
output (IiInlL-O_cw)
end;
end;
channel 0, memory to 588 */
- cb...a_588;
== 0;
= wrd(O);
-wrd(!);
= trans_len;
- dma_t~ode or 0006h; /* Start DMA chI 0 *1
231422-69
Figure 61. 80186 DMA Routines
1-406
intJ
AP-236
do case direction and OOOOOOOlb;
do;
1* channell 588 to memory *1
OUtput(dma_l_dpl) - WTd(O);'
output (dma_l_dph) ~ wrd(l);
output(dma_l_spl) - cLb_588;
output (dma_l_sph) _ 0;
output (dma_l_tc)
- trans len;
output (dma_l_cw)
- dma_r~ode or 0006h; f* Start DMA chI 1 *1
end;
do;
1*
ou t pu t (dma_1_dpl)
ou t pu t (dma_1_dph)
ou t pu t (dma_1-,pl)
ou t pu t (dma_1_s ph)
ou t pu t (dma_1_t c)
OU t pu t (dma_l_cw)
end;
end;
channel 1. memory to 588 *f
- cLb_588;
-
0;
- WTd(O);
-WTd(1);
- trans_len;
= dma_t~ode
or 0006h; 1*
Star~
DMA chI 1 *f
end;
231422-70
Figure 61. 80186 DMA Routines (Continued)
7.5 Interrupt Routine
The interrupt service routine. 'intr_588'. shown in
Figure 62. is invoked whenever the 82588 interrupts.
The main difficulty in designing this interrupt routine
was to speed its performance. Fast status processing
was a basic requirement to be able to handle back to
back frames.
The interrupt handler will read 82588 status, and put
them into a 64 byte long EVENT_FIFO. Those
statuses are going to be used in the main loop for updating screen counters. All the statistics are updated as fast
as possible in the interrupt handler to fulfill the backto-back frame processing requirement.
The interrupt handler is not reentrant, interrupts are
disabled at the beginning and reenabled on exit.
1-407
inter
AP-236
Interrupt servioe routine
intr_SSS:prooedure interrupt 13;
deola.re stat
byte,
byte,
I>yte,
byte,
byte,
byte;
event
i
(stO,st1,sta,st3)
rx_stO
rz_stl
I ' FOLLOWING LITERALS HAVE TEE PtlRFOSE OF ENABLE ACTING
ON EITHER CHANNEL 1 OR 3 SELECTIVELY
,I
declare
stap_amcUlma
11 terally 'if omel_channel
then output(dmA-mask)-dmeLoff. . . 3;
else output(cIm&.-mask)-clma_ofC1',
'if rlLohannel
then output(cIma_mask)-clma_off_3;
else output(c\m&.-mask)-clma_ofC1',
'if omd_obannel
then out~ut(OS_558)-lCh;
,!~S~~~~r~~~_688)-OOh' •
then autput(OS_585)-14h;
else outputCos_588)-04h';
disable;
output (os_588)
I ' DISABLB INTERRUPTS
'I
I ' NO INTERR, NESTING
'I
I ' RLS 588 PTa, START 0 ' I
-Ofh;
event31foCwr_ptr), stO, stO-inputCos_588);
event_fifoCwr_ptr), st1, stl-inputCos_588);
event_fifoCwr_ptr). st2, st2-1nput(os_688);
event. . . f.1fo(wr_ptr). et3, st3-input(os_58S);
I'
I'
I'
I'
TIf~~~~~n:d~~~i~ 1 ~n~f~~h;
I' INCRBllBNT FIFO
I' COUNTERS
' I
' I
event-at a and Ofh;
I' GET EVEN'!'· FIELD
' I
output Cos_588)-80h;
I ' AOEN01ILEJlGE 82685
I' INTERRUPT
' I
' I
READ 82588 STATUS
REGISTERS, PASSING
THEil TO TEE IlAIN
PROGRAII ON TaE FIFO
' I
' I
' I
'I
231422-71
do ca.se event;
:~=g~
eV_02
ev_03
ev_04
1* NOP COlOfAND
/. lA_SETUP, STOP DMA
I * CONFIGURE. STOP DMA
stop_omcLd,ma;
stop_cmcLdma;
stap_omcLclma;
do:
/. MULTICAST STOP DXA
I ' TRANSMIT DONE
I
stop_omcCdma j
*/
•I
.. /
.. /
'I
I ' CHECK IF THERE WAS A COLLISION AND IS NOT TEE
IIAX COLLISION
'I
stat-Cota and 100000000) ar Cst1 and 001000000);
if Cstat-SOh)
then do;
/
* RETRANSMIT
'" /
call dm!Lloa.d.( cmcLohannel. tX_d1r .1536. II»tx_dJna._addr) ;
1ssue_rt~omd;
I ' UPDATE STATISTICS
total_tx_oount-tota1_t~coount+l
else do;
,I
;
ooll_ontO?) - cOll_ontO?) + 1; I'TOTAL COLL'I
bad.-tx-count - bacLt~oount + 1:
end:
if in_loop
then do;
I ' EXECUTING TRANSMISSIONS IN LOOP
'I
/ .. RE ISSUE TRANSMIT COMMAND
'" /
oall cIma_loadC omel_channel, tlLdir, 1636,@tx_clma_addr
1ssue_tx-omd.:
total_tx.....count ...total_tx_oount+l;
end;
if Cot2 and 001000000) - 0
then do;
:be.uff+1) &D4 000001111:>, /' INC BIJF1IR NO. IIOD B'/
11 all8l:>la_rov, >Q
/' II' IUICl1IVIR IS ON
'/
than dO,
/' PRlIPARB IIl!ltT BIIPFIR '/
0811 clu..-loec1( rz....oh&llllal. rz....d1r. 1B32. Ol'Z_c1lII._ec1c1r( 1) ) ,
i t rz....oh&llllal then output(OB_888)- 18h,
alee output(08_888)-08h,
rz....l:>uffar(1). oh81,,-ont-O,
end;
al.e oall rov_d1.aI>la ,
/' DISABLE RECEIVER
/' FIND ADDRlISS 01' END OF CORRBNTLY IUICl1IVED BIIPFIR
/' BY CALCULATING IT WITH TIIB 82S88 BYTE COUIIT REGS.
rz....l>ufCotf-(.bl(doul:>la(.t2).8) or doul:>1.(st1»,
/' READ STA'l't1S BYTES FROII IIBIIORY
rz....BtO-rz_l:>uffar( ourrant.J:>utt) .buff(rz....l>uff_off-2) ,
rz....st 1-rz....l:>utfar(ourr8llt.J:>uff) .l:>uft(rz....l:>ufCoff-1) ,
/' UPDATE AC'l'tJAL BIIPPIR SIZE
rz.J:>uftar(currant.J:>uff) . aotu81_B1za-rz....l>ufCoff,
rz....l>uff.r( ourrent.J:>uff) • 8tO-rz_stO,
rz_bufter(ourrent_l:>uff). stl-rz....st1,
curr.nt_l:>utt-1,
/' UPDATE TOTAL RECBlVED BIIPFBRS
total_rov_oount-tot81_rov_oount+1,
/' UPDATH STATISTICS
if (rz....st1 &D4 001000001:»-0
than do,
!>&eLrov_oount-!>&eLrov_oount+ 1 ,
/' INCRBllB1I'r NO END OF FRAIIB COUllTBR
tmp-sor(tmp: -rz....stO. 7) ,
~~_~~~~f fHg:T0 ~IWO! COU1l'rIR
;~r~~~~:~U~~
plUS 0,
/' INCRBllB1I'r ax OVERRUN COUlITBR
tmp-sor(tmp:-rz_st1.1) ,
'/
'/
'/
'/
'/
'/
'/
'/
~!-~~veM~~-'BRRORCOtmTIIR
'/
tmp-Bor(tmp.2) ,
~gI;=J;r~l~
'/
'/
COtmTIIR
'/
tmp-sor(tmp.l) ,
oro_err-oro_el'l' plus 0:
and,
ev_09
av_10
BV_11
ev_12
and,
231422-73
/' BV_09 REQUESTS ASSIGNIIB1I'r OF A NEW BUPPER
'/
0811 allooata_new_buffar(not(rol(Bt3.1» and 000000011:»,
/' RBCElVE DISABLE
'/
stop_rz_c1lIIa,
stop_rz_c1lII.,
/' STOP IUICl1IVE
'/
d.o ;
/. RE-TRANSNIT DONE
•I
stat-(st2 and 100000001:» or (stl &D4 001000001:»,
11 (stat-80h)
than do,
/' RETRANSIiIT
'/
oall c1lIIa..loec10. t"_41r • 1536.ot,,:"c1lIIa..ac1dr) ,
1sBua_rtz....omc1 ,
001l_ont(7) - 001LOIlt(l7) + 1,
tot.Lt,,_00unt-tot.l_tz....oount+1'
!>&eLtz....oount-!>&eLtz....oount +1,
and,
else do;
i f i"-loop
than do,
/' LOOP RBTRANSIiISSIONS
'/
0 ..11 cIm&_loec1( omc1_oh&llllal. t"_d1r. 1536 .otz....cIm&_..
1ssue_tz_omd;
tot81_t,,_oount-tot81_tz....oount+l,
end;
if (st ..t-OAOh) /, IIAX COLLISION
then do,
ooll_ont(6) - ooll_OIlt(l6)+1,
ooll_ont(l7) - ooll_ont(17)+1,
~tl'-oount-bad._tlcoount
'/
+1;
end,
/' UPDATE SPECIFIC COLLISION COU1l'rBR
else 001l_OIlt(st1 and Oth)
- ooll_ont(stl and Ofh) + 1,
'/
end.;
av_13:
::::~t
end,
end,
stop_omc1_c1lII.,
stop_omc1_cIm&'
/, EXECUTION ABORTBD
'/
/, DIAGNOSE FAILED
'/
/' AClINOWLBOOB 8259A 11I'rBRRUPT
output (pio_OOW2) - seoLp1oo,
/' SPBCIFIC EOI FOR 82B9
and 1ntr_888,
'/
'/
231422-74
Figure 62. Interrupt Routine (Continued)
1-409
inter
AP-236
APPENDIX A
STARLAN SIGNALS
1-410
AP-236
82588
TXD RTS
(1)-----
5pF'
5pF'
(2)---
24 GAUGE
800 FT TWISTED PAIR WIRE
IN 25 PAIR BUNDLE
(')~
231422-47
231422-55
Figure 63. StarLAN Signals
1-411
inter
AP·236
Eye Diagram (5 Bits), DIW Cable
Manchester Encoded Signal
Transmission Distence = 0.8 Kit.
a
a
a
N
~
a
a
2
So
eO
...
..... 01)
III
Z
~a
IX
~
~8
gor
a
8
j'
a
a
01)
"j'
a
a
a
N
I
0.0
0.2
0.6
0.4
0.8
1.0
TIME (J'SEC)
231422-48
Figure 64. Received Signal Eye Diagram
1-412
inter
AP-236
APPENDIX B
802.3 1BASES MULTI-POINT EXTENSION (MPE)
As previously stated, one of the most important advantages of StarLAN is being able to work on already installed phone wires. This advantage is considerably diminished in Europe where numerous constraints exist
to the using of those wires:
Recently the StarLAN 802.3 IBASE5 task force has
been considering the extension of the StarLAN base
topology. This extension called MULTI POINT EXTENSION (MPE) is going to be developed to address
the previously described marketing requirements.
I. Wire belongs to local PTTs.
2. Not enough spare wires.
Currently no agreement has been reached by the
StarLAN task force on the MPE exact topology and
implementation. Multiple approaches have been presented, but no consensus met. It was decided though
that the MPE is going to be an .addendum to the STAR
topology, and that its final specification will happen
after the approval of the current IBASE5 STAR topology (July 1986).
This same issue is raised when talking about small businesses where in a lot of cases no wiring closets and/or
spare wires are available.
In summary, in a lot of cases rewiring will be necessary,
in which case the STAR topology may not be the most
economical one.
1-413
_ . - _ - - THROUGH A HUB UPGRADABLE
TO THE FULL STARLAN TOPOLOGY
(2500 m. MAX END-TO-END)
HUB COST ELIMINATED
IN SMALL TOPOLOGIES.
LOWER COST PER PORT
(UP TO 8 STATIONS PER PORT)
HUB
l
....
CONNECTION OPTIONAL,
NOT NEEDED FOR SMALL
TOPOLOGIES
"1\
C
c
iiJ
G)
~
iC
~
....
.jl.
:.
l'
c
~
"0
0
..
~
Co)
S·
i•g
Q)
LOWER COST.
TERMINALS ATIRACTIVE'
,
~
t I I 'I ~\
UT/,I /
FEWER CONNECTIONS TO
WIRING CLOSETS
231422-97
intJ
AP-236
APPENDIX C
SINGLE DMA CHANNEL INTERFACE
In a typical system, the 82588 needs 2 DMA channels
to operate in a manner that no received frames are lost
as discussed in section 5.1. 3. If an existing system has
only one DMA channel available, it is still possible to
operate the 82588 in a way that no frames are lost. This
method is recommended only in situations where a second DMA channel is impossible to get.
Figure 66 shows how the 82588 DMA logic is interfaced to one channel of a DMA controller. Two DRQ
lines are ORed and go to the DMA controller DRQ
line and the DACK line from the DMA controller is
connected to DACKO and DACKI of the 82588. The
82588 is configured for multiple buffer reception
(chaining), although the entire frame is received in a
single buffer. Let us assume that channel CH-O is used
as the first channel for reception. After the ENAble
RECeive command, CH-O is dedicated to reception. As
long as no frame is received, the other channel, CH-l,
can be used for executing any commands like transmit,
multicast address, dump, etc., by programming the
DMA channel for the execution command. The status
register should be checked for any ongoing reception,
to avoid issuing an execution command when reception
is active.
ORQO
ORQ1
OACKO
OACK1
82588
..,
I
OROn
lished, as shown in Figure 67. After this, the received
bytes start filling up the on-chip FIFO. The 82588 activates the DRQ line after 15-FIFO LIMIT + 3 bytes
are ready for transfer in the FIFO (about 80 microseconds after the interrupt). The CPU should react to the
interrupt within 80 ,""S and disable the DMA controller.
It should also issue an ASSIGN ALTERNATE BUFFER command with INTACK to abort any execution
command that may be active. The FIFO fills up in
about 160 ,""S after interrupt. To prevent an underrun,
the CPU must reprogram the DMA controller for
frame reception and re-enable the DMA controller
within 160 ,""S after the interrupt (time to receive about
21 bytes). No buffer switching actually takes place, although the 82588 generates request for alternate buffer
every time it has no additional buffer. The CPU must
respond to these interrupts with an ASSIGN ALTERNATE BUFFER command with INTACK. To keep
the CPU overhead to a minimum, the buffer size must
be configured to the maximum value of 1 kbyte.
If a frame transmission starts deferring due to the re-
ception occurring just prior to an issued transmit command, the transmission can start once the link is free
after reception. A maximum of 19 bytes are transmitted
(stored in the FIFO and internal registers) followed by
a jam pattern and then an execution aborted interrupt
occurs. The aborted frame can be transmitted again.
If the transmit command is issued and the 82588 starts
transmitting just prior to receiving a frame then transmit wins over receive-but this will obviously lead to a
collision.
OACKn
OMA
CONTROLLER
231422-49
Figure 66. 82588 USing One DMA Channel
If a frame is received, an interrupt for additional buffer
occurs immediately after an address match is estab-
Note that the interrupt for additional buffer is used to
abort an ongoing execution command and to program
the DMA channel for reception just when a frame is
received. This scheme imposes real time interrupt handling requirements on the CPU and is recommended
only when a second DMA channel is not available.
1-415
inter
AP-236
ASSIGN
ALT BUFF
WITH INTACK
REQUEST
ALT BUFF
INTERRUPT
.1
1
8258B ---.J
82;;;
I
:.:==~~~_-_-__~_BO_~_S
I
_________
r"
·~II___________
rFIFO FULL
•
~160~S-----------I'1
111
ADDRESS MATCH
ON FRAME
RECEPTION
DMA CONTROLLER
MUST BE DISABLED
PRIOR TO THIS
DMA CONTROLLER
MUST BE PROGRAMMED
FOR RECEPTION AND
ENABLED PRIOR TO THIS
231422-50
Figure 67. Timing at the Beginning of Frame Reception for Single DMA Channel Operation
1-416
infef
AP-236
APPENDIX D
MEASURING NETWORK DELAYS WITH THE 82588
Knowing networks round-trip delays in local area networks is an important capability. The round-trip delay
very much defines the slot time parameter which by
itself has a direct relationship to network efficiency and
throughput. Very often the slot-time parameter is not
flexible, due to standards requirements. Whenever it is
flexible, optimization of this number may lead to significant improvement in network performance.
Another possible usage of the network delay knowledge
is in balancing the inter-frame -spacing (IFS) on broadband networks. On those networks, stations nearer to
the HEAD-END hear themselves faster than farther
ones. Effectively having a shorter IFS than stations far
from the HEAD-END. This difference causes an inbalance in network access time for different stations at
different distances from the HEAD-END. Knowing
the STATION/HEAD-END delay allows the user to
reprogram the 82588 IFS accordingly, and by that balance the effective IFS for all the stations.
The 82588 has an internal mechanism that allows the
user to measure this delay in BIT-TIME units. The
method is based on the fact that the 82588 when configured for internal collision detection, requires that the
carrier sense be active within half a slot-time after
transmission has started. If this requirement is not fulfilled the 82588 notifies that a collision has occurred.
Thus it is possible to configure the 82588 to different
slot time values, then transmit a long frame (of at least
half a slot-time). If the transmission succeeds, the network round-trip delay is less than half the programmed
slot-time. If a collision is reported, the delay is longer.
The value of the round-trip delay can be found by repeating this experiment process while scanning the slottime configuration parameter value and searching the
threshold. A binary search algorithm is used for that
purpose. First the slot-time is configured for the maximum (2048 bits) and according if there was a collision
or not, the number changed for the next try. (See Figure 68)
1-417
inter
Ap·236
8
2
5
8
8
PROPAGATION DELAY
TX
HEADEND
RX
• SCHEME IS BASED ON THE FACT THAT THE 82588 EXPECTS RX CARRIER
TO BE ACTIVE AFTER 1/2 SLOT TIME
N
K = APPROXIMATION FACTOR
231422-98
Figure 68. Network Delay Measurement using .the 82588
1-418
inter
APPLICATION
NOTE
AP-320
November 1988
Using the Inte'l 82592 to Integrate
a Low-Cost Ethernet Solution
into a PC Motherboard
MICHAEL ANZILOTTI
TECHNICAL MARKETING ENGINEER
Order Number: 290189·001
1·419
inter
AP-320
the LAN solution; e.g., system memory and DMA.
This leaves the 82592, the serial interface, and some
control logic as the only components required to complete a motherboard LAN solution.
1.0 INTRODUCTION
During the past several years office networking has become an increasingly efficient method of resource sharing for companies looking to increase productivity
while reducing cost. Networking allows multiuser access to a data base of files or programs via a network
file server; it allows sharing of expensive peripherals;
e.g., laser printers; and it offers a greater degree of data
security by centralizing the hard disk and backup facilities. This type of network allows a user to concentrate
his resources; e.g., a high-capacity, high-performance
hard disk, at the network file server, allowing the other
nodes, or PC workstations, on the network to function
with limited or no mass data storage capability.
1.1 Objective
This Application Note presents the general concept of
integrating a Local Area Networking into a PC motherboard, and how the 82592 suits this purpose. The
design of the 82592 Embedded LAN Module, which
plugs into an Intel SYP301 motherboard (or any standard PC AT style motherboard), is explained in detail-providing a demonstration of an integrated Ethernet LAN solution.
As Local Area Networks (LANs) have become more
common in the office and in industry, some clear market development trends have emerged. Possibly the
?t0st significant development in the LAN marketplace
IS the concern for cost reduction. This need is driven by
intense competition between network vendors for market share. Today's LAN marketplace requires low-cost,
simple network solutions that do not sacrifice performance. Another significant development in the LAN
marketplace is the acceptance of Ethernet, or a derivative (e.g., Cheapernet or Twisted Pair Ethernet), as the
industry standard for high-performance LANs. Because of Ethernet's popularity, there is a great need for
cost reduction in this market.
1.2 Acknowledgements
For their contributions to this Application Note, and
for their work in developing the architecture of the
82592 Embedded LAN Module, I would like to acknowledge, and thank, Uri Elzur, Dan Gavish, and
Haim Sadger, of the Intel Israel System Validation
group; and Joe Dragony, of Intel's (Folsom) Data
Communications Focus Group.
2.0 THE EVOLUTION OF LAN
SOLUTION ARCHITECTURES
Personal computers (PCs) have· also seen significant
changes over the past several years. PCs have become
firmly entrenched in the office. Their popularity, coupled with a highly competitive market, has compelled
PC vendors to both reduce costs for their LAN solutions and to attempt to distinguish their product from
the competition's. The means of this cost reduction
range from eliminating expensive hardware, such as
disk drives and their associated hardware, to using
highly integrated VLSI devices that implement the
functions of a PC in a combination chip set containing
several devices. Differentiation has been achieved by
integrating peripheral functions, normally contained on
an external adapter card, into the main processor
board, or motherboard, of the PC. Video Graphics Array (VGA) and LAN connections are examples of this
strategy.
The Intel 82592 LAN controller is uniquely suited for
integration into a PC AT style motherboard. It meets
the demands of today's market by providing the PC
v~ndor (1) a means of reducing cost while maintaining
high performance, and (2) a path for differentiation. An
82592 integrated into a PC motherboard provides a
very low cost and very simple implementation because
it uses the host system's existing resources to complete
LAN solutions have undergone an evolution in architecture-from expensive and complex to more cost-efficient and streamlined. A definite trend in office networking can be seen, as these solutions permit the host
system to perform functions that were previously included in the LAN solution.
The first LAN solutions were usually intelligent buffered adapter cards, with a CPU, large memory requirements (up to 512 kB), firmware, a LAN controller, and
a serial interface. As networking became more prevalent in the office environment-linking PCs and workstations via Ethernet-this complex architecture
evolved into simpler and more streamlined nonintelligent, buffered adapters. In this architecture the CPU is
no longer part of the LAN solution; its processing power is supplied by the host system. This architecture does
not need memory to support a local CPU. Memory is
only needed to supply a buffer space to store data before moving it to system memory or onto the serial link.
The memory requirement for nonintelligent, buffered
architectures is. typically 8 kBytes to 32 kBytes. The
firmware to boot the CPU is also no longer needed. The
evolution to a nonintelligent, buffered architecture has
resulted in significant cost savings and reduced complexity.
1-420
inter
AP-320
Significant increases in speed and processing power
have been made to PCs during the past several years.
This trend to higher performance host systems has allowed further streamlining of the LAN solution's architecture, resulting in even greater cost reduction and
simplification. This is accomplished by using host system resources whenever possible. A nonintelligent, nonbuffered architecture is the result. In this architecture,
the host system's memory and DMA are used by the
LAN controller. The complexity associated with buffered LAN solutions (e.g., supplying a dual-port arbitra-
tion scheme for local memory access by both the CPU
and the LAN controller) is reduced; this complexity is
removed from the LAN solution and returned to the
host system, which is designed for these complex tasks.
The result of this architectural optimization is a very
simple, low component count, cost-efficient solution for
a LAN connection. The 82592 Embedded LAN Module is the realization of this optimization. The trend to
optimization of LAN architectures is shown in Figure
1.
Intelligent Buffered Adapter
E1
290189-1
Nonintelligent Buffered Adapter
Nonintelligent Non-Buffered Architec:ture
Embedded Module
290189-3
290189-2
Figure 1. Architectural Optimization of LAN Solutions
1-421
inter
Ap-320
3.0 THE 82592 LAN CONTROLLER
• Internal and extemalloopback
• Internal register dump
• A TDR mechanism
• Internal diagnostics
3.1 General Features
The 82592 is a second generation, CMOS, advanced
CSMAlCD LAN controller with a 16-bit data path.
Along with its 8-bit version, the 82590, it is the followon design to the 82588 LAN controller. The 82592 is
upwards software compatible from the 82588. The
82592 has two modes of serial operation, High Speed
Mode and High Integration Mode. In High Speed
Mode (up to 20 Mb/s) the 82592 couples with the Intel
82C501 to provide an all CMOS kit for IEEE 802.3
Ethernet applications. In this mode the 82592 can also
serve as the controller for Twisted Pair Ethernet (TPE)
applications. In High Integration Mode (up to 4 Mb/s)
the 82592 performs Manchester and NRZI encoding!
decoding, collision detection, transmit clocking, and receive clock recovery on chip; in this mode it can serve
as a controller for StarLAN and other midrange LANs.
The 82592 provides several features that allow an efficient system interface to a wide variety of Intel microprocessors (e.g., iAPX 188, 186, 286, and 386) and industry standard buses (e.g., the IBM PC I/O channel
or the PSI2™ Micro ChanneI™). To issue a cOlnmand to the 82592 (e.g., TRANSMIT or CONFIGURE) the CPU only needs to set up a block in memory
that contains the parameters to be transferred to the
82592, program the DMA controller to point to that
location and issue the proper opcode to the 82592. The
82592 and DMA controller perform the functions
needed to complete the command, with the 82592 interrupting the CPU when the command is complete. The
82592 has a high-performance, 16-bit bus interface, operating at up to 16 MHz. It also implements a specialized hardware handshake with industry standard DMA
controllers (e.g., the Intel 8237, 82380, and 82370) or
the Intel 82560. This allows for back-to-back frame reception, and automatic retransmission on collisionwithout CPU intervention. The 82592 FIFOs (Rx and
Tx) can have their 64 bytes divided into combinations
of 32/32, 16/48,48/16, or 16/16.
The 82592 features a Deterministic Collision Resolution (DCR) mode. When a collision is detected while in
this mode, all nodes in a deterministic network enter
into a time-division-multiplexed algorithm where each
node has its own unique slot in which to transmit. This
ensures that the collision is resolved within a calculated
worst-case time. The 82592 also features a number of
network management and diagnostic capabilities; for
example,
• Monitor mode
• A 24-bit timer
• Three 16-bit event counters
For further information on the 82592, please refer to
the Intel Microcommunications Handbook.
3.2 Unique Features for Embedded
LAN Applications
The 82592 has several unique features that enable implementing a high-performance embedded LAN solution with minimal cost and complexity.
Peripherals on a motherboard must compete for access
to the system bus. Because there is no local buffer for
intermediate buffering of data, data transfers take place
in real-time over the system bus to the system memory.
A LAN controller must have a large internal data storage area to be able to wait for access to the system bus
while serial data is being received or transmitted. Without sufficient internal data storage, a LAN controller
cannot take advantage of the cost efficiency and simplicity of a non-buffered architecture. The 82592 has a
total of 64 bytes of FIFOs. This expanded FIFO section
allows the 82592 to tolerate long system bus latencies.
For example, during a Receive (with the Rx FIFO
length configured to 48 bytes) the 82592 can tolerate up
to 38.4 ,...S of bus latency-the time from a DMA request to reception of a DMA Acknowledge from the
DMA controller-before the possibility of a data overrun occurring in a 10 Mb/s Ethernet application. Once
access to the system bus has been obtained, the 82592's
high-performance, 16-bit bus interface provides efficient data transfer over the system bus, thus reducing
the bus utilization load for a LAN connection on the
host system.
The 82592 features a specialiZed hardware handshake
with industry standard DMA controllers. This hardware handshake between the 82592 and the DMA controller (on signal lines DRQ and EOP) relays the status
of a Receive or Transmit and allows for back-to-back
frame reception and automatic retransmission on collision without CPU intervention". This allows the 82592
and the DMA controller to perform these time-critical
operations in real-time without depending on the CPU
via an interrupt service routine, and without the time
delays inherent in such routines. For the 82592 Embedded LAN Module, this hardware handshake is enabled
by configuring the 82592 to the Tightly Coupled Interface (TCI) mode. Figure 2 shows details of the 82592's
TCI signals.
1-422
intJ
AP·S20
Transmit/Receive Status Encoding on DRQ and EOP
DRQ
EOP
0
Hi-Z
Status Information
Idle
1
Hi-Z
0
0
Transmission or Reception Terminated OK
DMA Transfer
1
0
Transmission or Reception Aborted
Tightly Coupled Interface Timings
ORQO,
ORQl
OACKO,
OACKI
~:
..
§'--
'\
--I
\.
-
Symbol
'\
- T104
-T23
Parameter
Tl 05
-
Min
-
Tloal-
290189-4
Max
Units
45
ns
CL
= 50pF
Notes
65
ns
CL
= 50pF
t23
WR or RD Low to DRQO
or DRQ1 Inactive
tlD4
WR or RD High to DRQO
or DRQ1 InactiVe
tlD5
WR or RD Low to EQj5 Active
45
ns
Open Drain I/O Pin
tl06
EOP Float after DACKO
orDACK1 Inactive
40
ns
Open Drain I/O Pin
2.5
Figure 2. TCI Encoding and Timings
1-423
inter
AP-320
These three features (FIFO depth, high-performance
bus interface, and TCI) allow the 82592 to operate successfully in a high-performance motherboard LAN
application. The application of these features will be
discussed further in Section 4.
schematics. The module consists of an 82592, two
20LlO PALs, and two 8-bit LS573 address latches that
combine to provide a 16-bit address latch. The module
contains no DMA unit or local memory.
The 82592 Embedded LAN Module is a simple, lowcost, low component count solution because it uses the
available system resources (DMA and memory) to provide for those functions normally added to a LAN solution. Removing DMA and local memory from a LAN
solution reduces cost and complexity. Two host DMA
channels, one for receive and one for transmit, are
needed to support the module. The DMA interface
from the 82592 (through PAL B) is the standard combination ofDRQ, DACK and BOP. These three signals
also provide the TCI between the 82592 and the DMA
controller. The size of the memory buffer needed to
, support the module depends on the specific application
and the amount of free memory available; the buffer
size can be specified by the programmer.
4.0 SYP301 INTERFACE
This section will discuss the details of the interface of
the 82592 Embedded LAN Module to the Intel
SYP30 I. The basic architecture will be presented, demonstrating that the 82592 Embedded LAN Module is a
low-cost, low component count Ethernet solution for
networking office PCs or workstations.
The Intel SYP301 is compatible with the IBM PC
ATTM. It features an Intel 80386TM microprocessor,
running at 16 MHz, as its CPU. Its system bus is compatible with the standard PC AT I/O-channel bus.
4.1 BasiC Architecture
Figure 3 shows the basic architecture of the 82592 Embedded LAN Module, and Figure 4 shows the module's
ADDRESS BUS AO-15
LATCH
LTCwT
DROO
DROI
DACK
EOP
INT
.
"
,r
OE
DMA INTERfACE
PAL B
CS
"r ) (ORO, DACK, EOP)
INTRO
.....
lORD
-
~
A
ADDRESS BUS AO-2 A5-9
PAL A
~I
DATA BUS 00-15
(RECEIVE)
(TRANSMIT)
(BOTH CHANNELS)
I~
82592
"
'I
lORD
lORD
IOWR
IOWR
~
"
DATA BUS 00-15
r
290189-5
Figure 3. 82592 Embedded LAN Module Baalc Architecture
1-424
8
5
5V
82592
,
DATA 0-15
CSMA/CD
R'
74ALS573
ADRS 0-15.
...
c:
J
10
1Q
2
....
20
2Q
5
A2
A3
A4
7
JQ6
JO
84D4Q9
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sa 12
14 6D
6Q 15
A8
17 70
A7
18 80
11 C
CD
01»
N
c.n
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3
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7
8
13
14
17
18
AS
cl
m
3
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A13
A14
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CI'
CD
.... a.
a.
CD
./:..
a.
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(]I
19
DO
J1!!
Dl
ii2
ii3
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ii7
Ot
ii2
ii3
0.DS
DO
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4
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10
80
12V
50
eo
70
8Q
2
5
8
9_
12
15
16
19
D'2
0'3
0"
0'5
DD
Ot
ii2
ii3
0.-
....
E3
01i"
74ALS573
1D
10
2020
30
3Q
4D
4Q
SO
80
3
5
7
0,0
OC U'
~
:Sl
70 US
eo
.
2
AD
Al
~
."
iC'
CONTROLLER
4K
Ul
Ds
DO
OREa1
ii7
11
C
DREQO
IOWR ...
1
OC U5
lORD ...
r-
)0-
z
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~
p;,AS
0
a.
c:
CD
en
n
::r
CD
3
AS
AS
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n
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21
M
A7
PALS
I~i II
LATCH
..
is
jj
p,---
II
II
17
11
5"
I
1'9
13
U3
DACia.
OACK6e
LB
IOWR.
lORD.
RESET
,
R''3K
2
INTEL DFG TECHNICAL MARKETING
1900 PRAIRIE CITI RD FOLSOM CA 95630
IA
TITL_
82592 EMBEDDED LAN MODULE
DRAWN
BV
BELR
&'i'E
FILE"
ELMI
1 or-l
290189-48
inter
AP-320
The two PALs (PAL A and B) provide two major junctions for the module: (1) address decode (PAL A), and
(2) interpreting the TCI from the 82592 (PAL B). PAL
A decodes addresses for CS to the 82592, OE for the
address latches, and an Enable/Disable of the LAN
module. PAL B interprets the TCI of the 82592. When
PAL B detects EOP from the 82592 during reception of
a frame (EOP indicates the last byte of the receive
frame) it loads the memory address of the last byte of
the receive frame (the byte count) into the Address
Latch at the time it is written into memory. This allows
back-to-back frame reception without CPU intervention, and will be covered in detail in Section 4.2. For
Auto-Retransmit on collision, PAL B passes the EOP
signal from the 82592 to the DMA controller, reinitializing the DMA controller for retransmission. This process will be discussed in more detail in Section 4.3. Both
sets of PAL equations are listed in Table 1.
Table 1. PAL Equations
PAL20L 10 MMI-PAL A (Version 1.1)
AEN A2 RESET NC AO IOWBAR A5 A6 A7 AS A9 GND IORBAR 50lLB Al 59CTS OE2BAR
OEIBAR LANRSTBAR NC NC ENLANBAR 592CSOBAR VCC
=592CTS
592CSOBAR =AEN • A9 •
OE2BAR =AEN • A9 • AS
OEIBAR =AEN • A9 • AS
LANRSTBAR =AEN • A9 •
ENLANBAR
IF (VCC) 501LB
IF (VCC)
IF (VCC)
IF
(VCC)
IF (VCC)
IF (VCC) ENLANBAR
AS • A7 • A6 • A5 • A2 • Al • AO • ENLANBAR
• A7 • A6 • A5 • A2 • Al • AO • IORBAR • ENLANBAR
• A7 • A6 • A5 • A2 • Al • AO • IORBAR • ENLANBAR
AS • A7 • A6 • A5 • A2 • Al • AO • IOWBAR •
= LANRSTBAR
• ENLANBAR + AEN • A9 • AS • A7 • A6 • A5 • A2 • Al
• AO • IOWBAR
PAL20L 10 MMI-PAL B (Version 1.1)
592DRQO RESET DACK7BAR DACK6BAR IORBAR 592DRQI 592EOPBAR ENLANBAR AEN NC
IOWBAR GND 592INT NC DRQ6BAR DRQ7 DRQ6 DISDACK IRQIO NC MSEOPBAR LTCW
592DACKBAR VCC
IF (VCC) LTCW
=
IORBAR + 592EOPBAR + DACK7BAR
IF (ENLANBAR • 592EOPBAR • DACK6BAR) MSEOPBAR = 592EOPBAR • DACK6BAR
IF (VCC) 592DACKBAR = DACK6BAR • DISDACK • ENLANBAR + DACK7BAR • ENLANBAR
IF (VCC) DISDACK = IOWRBAR • DISDACK • RESET + 592DRQO • DISDACK • RESET
+.592DRQO • IOWRBAR • RESET
IF (VCC) DRQ7
592DRQI + 592EOPBAR • DACK7BAR
IF (VCC) DRQ6BAR = 592DRQO • RESET + DACK6BAR • DRQ6BAR • RESET
IF (VCC) DRQ6 = DRQ6BAR
IF (ENLANBAR) IRQIO = 592INT
NOTE:
The suffix BAR added to the above Signal names indicates an active low signal. A signal in these equations with a line
drawn above it indicates this signal is to be in a low state for the equation.
1-426
inter
Ap·320
4.2 Back·to-Back Frame Reception
TCI signals of the 82592 (PAL B loads the address
latch with the address of the last byte of the received
frame) and the structure of the received frame transferred from the 82592 to memory. Figure 5 shows the
format of an 82592 receive frame in TCI mode. After
the information fields are written to memory, the Status
and byte count of the received frame are appended to
the frame in memory. These four bytes (two bytes of
Status and two bytes of byte count) are the last four
bytes of the receive frame written to memory. The high
byte of the byte count is the last byte transferred from
the 82592 to memory. As this last byte is transferred to
memory, the 82592 asserts the EOP signal. When PAL
B detects the assertion of EOP by the 82592, it loads
the address of the last byte of the receive frame into the
Address Latch as this byte is written into memory. This
action ensures that there will always be a pointer (the
contents of the Address Latch) to the byte count of the
last frame stored in the RFA buffer in system memory.
Based on the value of the byte count, the beginning
address of the receive frame in memory can be calculated'; i.e., Byte Count Address Pointer - Byte Count =
Beginning of Frame. The byte count of a previous receive frame" would reside one address location before
the first byte of the current receive frame. That frame,
and any additional receive frames that may have preceded it, can have their start addresses recovered by the
same calculation used to recover the last frame received. This process allows frames to be continually
stored in the RFA buffer without CPU intervention,
and to be recovered by the CPU for processing. Figure
6 illustrates the process of back-to-back frame reception.
The architecture of the 82592 Embedded LAN Module
allows it to receive back-to-back frames without CPU
intervention. It uses a contiguous Receive Frame Area
(RFA) buffer in host system memory where receive
frames can be continuously stored. This sequential storage of receive frames can continue until the buffer space
is exhausted. The size of the RFA buffer can be specified by the programmer. Its size will be programmed as
the byte count of the Rx DMA channel. The Base Address Register contents of that channel serve as the
start address of the RFA buffer. The receive frames will
be stored sequentially in the RFA buffer based on the
contents of the Current Address Register of the Rx
DMA channel. The module's architecture, and the
82592 receive frame memory structure, allows the CPU
to recover the addresses of each Receive frame in memory for processing. The CPU can also reinitialize the
RFA buffer (by reinitializing the Rx DMA channel) as
the RFA buffer fills up and its contents are processed.
Alternatively, configuring the Rx DMA channel to
Auto-Initialize mode will allow the Rx buffer to automatically wrap around, back to the beginning of the
buffer, when its end is reached. This creates a virtual
"endless" circular buffer. When using this approach,
care must be taken to avoid writing over unprocessed
Rx frames-either by the addition of a hardware Stop
Register, or by guaranteeing that the Rx frames can be
processed faster than the buffer can wrap around.
Back-to-back frame reception without CPU intervention-and eventual recovery of the frames for processing by the CPU-is based on PAL B's decoding of the
15
14
13
11
12
10
9
8
7
6
DESTINATION ADDRESS SECOND BYTE
5
4
3
o
2
DESTINATION ADDRESS FIRST BYTE
I
I
DESTINATION ADDRESS LAST BYTE
SOURCE ADDRESS SECOND BYTE
SOURCE ADDRESS FIRST BYTE
I
I
SOURCE ADDRESS LAST BYTE
INFORMATION (LENGTH FIELD, HIGH)
INFORMATION (LENGTH FIELD, LOW)
INFORMATION LAST BYTE
CRCBYTE l '
CRC BYTE 0'
CRCBYTE3'
.
CRC BYTE 2'
X
X
X
X
X
X
X
X
SHORT
FRAME
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The CRC bytes are transferred to memory only when the deVice
NO
EOF
TOO
LONG
1
NO
SFD
NO ADD
MATCH
I-A
MATCH
Rx
CLD
0
Rx
OK
LEN
ERR
CRC
ERROR
ALG
ERROR
0
OVER
RUN
BYTE COUNT LOW
BYTE COUNT HIGH
IS
so configured
Figure 5. Receive Format for the 82592 in 16-Bit Mode (Tightly Coupled Interface Enabled)
1-427
inter
AP-320
Example No.1
Example No.2
Example No.3
First Frame
Received
Second Frame
Received
nth Frame
I Rev
Frame
I
Areal
In Host Memory
Latch
1---I
I
I
Frame 1
I
Status
status
Byte Count
Byte Count
Remainder of
RFA Buffer
I
RCV Frame AreO
In Host Memory
Frome 1
I
Received
I
I
I
RCV Frame Area
In Host Memory
Frame 1
Status
Byte Count
I
I
I
Frome 2
Additional
RCV Frame.
I
I
I
I
290189-6
Frame n
Statu •
I
Latch
. t-----
Byte Count
Statu.
I
I
I
Remainder of
RFA Buffor
I
I
I
I
r
Latch
}----+
I
290189-7
Byte Count
I
I
I
RemaInder of
RFA Buffer
I
I
I
I
I
290189-8
NOTES:
The 82592 appends the byte count to the end of each RCV frame.
PAL 'B' loads the latch with the memory address of the last byte of each RCV frame.
Based on latch contents and the byte count of each frame, the CPU recovers the RCV frames.
Figure 6. Back-to-Back Frame Reception
4.3 Automatic Retransmission on
Collision
Automatic retransmission on collision detection is accomplished by the TCI between the 82592 and the host
8237 DMA controller and requires no CPU intervention. The transmit channel of the 8237 should be configured for Auto-Initialize mode. The transmit block
(data to be transmitted) starts at the location pointed to
by the Base Address Register of the Tx DMA channel.
During a Transmit command, the 82592 DMA requests begin at the start of the transmit block and work
sequentially through the block (by incrementing the
contents of the 8237'8 Current Address Register) until
the transmission is complete. Should a collision occur,
the 82592 asserts the EOP signal and DRQ* to the
8237 (these signals pass through PAL B) causing the
8237 to auto-initialize back to the beginning of the
transmit block (the Current Address Register is loaded
with the value in the Base Address Register). Internal-
ly, the 82592 generates a Retransmit command and begins making DMA requests to the 8237, which is now
pointing to the beginning of the transmit block. The
82592 also enters into a back-off algorithm (counting to
a random number to resolve the collision). When the
back-off algorithm is complete, and the 82592 regains
access to the serial link, retransmission is attempted.
The 82592 will repeat this process until the retransmission is completed successfully or until the maximum
allowable number of collisions per Transmit command
is reached-at that point all retransmit attempts stop.
No CPU involvement is required to carry out a retransmission. The process of automatic retransmission is
shown in Figure 7.
NOTE:
'For Auto-Initialization of the 8237, the signal DRQ
must be asserted to the 8237 along with assertion of
EOP. With the 82380 and 82370 DMA controllers,
Auto-Initialization can be triggered by asserting the
EOP signal alone.
1-428
inter
AP-320
Prior to Transmission
BAR = CAR
Transmit DMA Channel In
Auto-Initialize Mode
During Transmission
CAR Increments
BAR/CAR -+
BAR-+
Transmit
Buffer in
System
Memory
CAR-+
Collision:
82592 EQi5 Asserted to 8237
CAR Reset to BAR
(by 8237's Auto-Initialize)
BAR/CAR-+
Transmit
Buffer in
System
Memory
Transmit
Buffer in
System
Memory
After Back Off the 82592
Retransmits from Beginning of
Transmit Buffer.
No CPU Intervention is
Required for Retransmission
BAR = Base Address Register
CAR =' Current Address Register
Figure 7. Automatic Retransmission on Collision
4.4 Target Systems for Integration
The 82592 Embedded LAN Module is designed to be
implemented on an Intel SYP301 motherboard; thereby
demonstrating a low-cost LAN connection for a workstation. The SYP301 has an IBM PC AT style bus architecture with a 32-bit Intel 80386 as the main processor. The interface between the 82592 LAN Module and
the SYP301 is based on standard interface signals
(DRQ, DACK, BOP, IRQ, lOR, lOW, etc.) so the
basic architecture of the module can be implemented on
PC AT based systems. This design has been successfully tested in PC AT style systems produced by several
manufacturers. For some PC AT based systems, and
PS/2 Micro Channel systems, the module's design may
require some modification. IBM PC and PC XT based
systems do not have sufficient DMA bandwidth to support the non-buffered architecture of this module.
4.4.1 PC AT BASED DESIGNS
High-integration chip sets replace a large number of
discrete VLSI, LSI, and TTL components with several
integrated VLSI devices that duplicate a large portion
of the PC's functionality. PC AT compatible systems
using such chip sets may lack support for the automatic
retransmission feature of the 82592 LAN Module. This
is because many manufacturers of such chip sets have
integrated the EOP function but eliminated the EOP
input. This lack of an EOP input disables auto-initialization of the DMA controller for retransmission. In
this case retransmission can be performed in one of two
ways.
• Should a collision occur while transmitting the preamble, the 82592 (when configured to automatic retransmission mode) will automatically retransmit
without CPU intervention or auto-initialization of
the DMA. This is effective for shorter network topologies where collisions are normally detected early in the frame.
• Should a collision occur after the preamble, the
82592 will interrupt the CPU and the CPU will initiate the retransmission.
For a PC AT style architecture, logic must be implemented to accommodate DRAM refresh. DRAM refresh cycles typically occur at 15 f.Ls intervals. In a standard PC AT, any DMA user should limit the time of a
DMA burst to 15 f.Ls; this is to ensure that the system
bus is free for the refresh to take place. Any designer
using burst mode DMA.must consider this requirement
when implementing a design.
4.4.2 PS/2 MICRO CHANNEL ARCHITECTURE
DESIGNS
The IBM PS/2 and other compatibles using the Micro
Channel architecture have a different host interface to
the 82592 Embedded LAN Module; however, the basic
architecture of the module is still applicable. As in the
SYP301 solution, the TCI between the 82592 and a
1-429
inter
Ap·320
control PAL loads the address latch with a pointer to
the last receive frame. Based on the contents of the
latch and the 82592 receive memory structure, the
frames are recovered for processing by the CPU. The
differences between a PC AT architecture and a Micro
Channel architecture require different control signal
decoding. The Micro Channel requires a 24-bit address
latch, as opposed to a 16-bit latch in the 301, and to
acquire the system DMA it requires different arbitration logic to drive a 4-bit arbitration level on the Micro
Channel. The Micro Channel also does not have an
EOP input; therefore, auto-initialization of the Tx
DMA channel and support of automatic retransmission
without CPU intervention must be provided by using
one of the alternative methods recommended in the
previous section.
4.4.3 EMBEDDED CONTROL DESIGNS
The 82592 Embedded LAN Module architecture can
also be applied to an embedded control application that
contains some DMA functions. For an embedded application using an 8237, 82380 or 82370 DMA controller,
the basic architecture of the 82592 Embedded LAN
Module can be used. For an interface to DMA devices
that do not feature the EOP signal as an input (for
example, DMA units on board a CPU), the alternative
methods for retransmission given earlier can be used.
5.0 SERIAL INTERFACE MODULE
The serial interface for the Intel SYP301 82592 Embedded LAN Module is implemented as a separate module.
Since the 82592 Embedded LAN Module is intended to
be integrated into a system motherboard, implementing
the serial interface as a separate module-perhaps as a
very small PC board that plugs into a socket-allows
for easy interchangeability between different serial interface media. This modularity allows the system board
manufacturer to avoid committing his motherboard to
only one type of medium, and thus requiring a major
redesign for each different serial interface.
Modularity in the data communications field is encouraged by the Open Systems Interconnect (OSI) reference
model. The 82592 is designed to operate through the
lower half of the Data Link Layer (see Figure 8), implementing CSMA/CD Medium Access Control and interfacing directly with the Physical layer below it. By
interfacing the 82592's standard CSMA/CD interface
signals~a serial module (TxD, RxD, TxC, RxC,
CDT, CRS, and others) different Physical Link modules can be implemented without any change to software. Examples of serial interface modules that could
be interchanged by simply plugging a new module into
the motherboard are Ethernet/Cheapernet, Twisted
Pair Ethernet (TPE), StarLAN, Broadband Ethernet,
and many proprietary CSMA serial media. Figure 9
shows the schematics of an Ethernet module; and 'Figure 10 those of an Ethernet/Cheapernet module.
OSI
Reference Model Layers
7
Appllcotlon
6
Presentation
5
Session
4
Transport
:5
Network
2
Data Link
Physical
,"
,'-
,
I-----M-A-C----I
2
"
"
"
" "
LLC
Logical Link Control
Medium Access Control
#,'
PLS
Physical Signaling
290189-10
Figure 8. The 82592 Embedded LAN Module Relationship to the OSI Reference Model
1-430
l
~~~
,,~
1,
-I"'
Yl
=:J
,1~414~
2'6 PF
:II
.a
c
!D
•
"..
i..
::3
ID
I
I.
.
TXC_
TXD
RXD
RXc.
COT.
CRS.
17
16
9
8
7
6
-2
E.
~ 1.0uF
, Rl
TxD
TxC_
RxD
RxC.
COT.
CRS.
LPBK.
2
I
I
78
, R4
Ul
78
+12V
2
240
,R3
TRMT
2
TRMT.
240
, R2
TRMl 19
TR~ 18
4
RCV. 5
CLS 12
CLSN 11
X2 13
Xl 14
20
-;i- TEN_
RTS.
::3
c.> :....
-J. Cl
C2
R5
lOOK
2
, C3
C;'
82C501
SERIAL
INTERFACE
ii1
,
20.0MHZ
2
2
-'\7
RCV
I,
2
2
RCV.
I
CP
CP.
+12V
Hb-
1
3
4
10
6
5
8
12
11
2
14
9
13
E C
T 0
HN
E N
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NC
E T
T 0
R
Jl
'7
1Tz°. 1UF Tz°·1UF
~
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290169-46
:.
l
~
12VDC
J
'Cll
-i
~~
•
--i
~
g.
22
,RB
~
c:
5VOC
78
,R122
RCV
, R10 2
CPo
In
43.2
,R9
::r
CP
43.2
1
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2
~
CD
Fl~7°u
:tee
lo.olUF
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0
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1
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.
.
1
1
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C19
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.22uF
G)
"
]>
:J
I»
--i ClC2
TENo
~ TxO
, e22
~
"""""RXD9
RXCo
RxO
8 RKC.
COT...
~ CRS.
X2
~
-2 LPBK*
Xl
II
~
~
INTERFAC ~
SERIAL
2
2
C4
Ta°.
1UF
,1
'F
~
CR2
2
,
R21
10
2
5VOC
12VDC
~
E6
78
, R4
PE64102
15
15
13
12
10
9
14
.~
78
1
J
240
U2
CR3
~
l
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o
JUMPER BU<
1.0ur
, R2
18
4
5
12
11
RC'
ReV.
Cl
CLSN
TxC.
lN4'48
10
~
UI3
""-=-
lN4148
2
240
r-;-g
fiT
7
2
TRIAl
TRMT
Itt
3
4
5
6
8
R22
1001(
lN4148
,Rl
82C501 __
0'
82502
,
CR4
CD
2
TRMT.
ReV
ReV.
CPo
CP
5p>C
20.CMHZ
:J
CD
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24~RMT4 TRANSCIEVER rl-i-15
5028US
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c:
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43.2
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TRMT
1 C15
DC/DC
CONVERTER ~
16
r-ii
43.2
CD
J,.
•
SAVDC
~
~
~
15
f'O.OIUF~
TRMT*
l
2VA12U10-5
1
PULSE
TRANSFORMER
t+
II:
2
1
2
4
5
7
8
~
U3
E12
Ell
EIO
E9
E8
E7
I
1 ,---,
TRMT
r--i"
E18
TRMT.
E17
E4
RCV
E16
E3
Rev..
E15
E2
CP
E14
El
CPo
E13
E5
I----rti
H
0
E
N
~ NR
N
t---t
t---!f
22uF
E
~ T
12VDC
,age
rx buf head
he"ie
dw
dw
dw
d"
dw
d"
d"
dw
d"
dw
-
rx buf tail
rX:bufJ>tr
rx_buf_stop
rx_buf_length
r"_buf_seglMnt
curr_r"_length
rx list
nuiii of frame.
reset rx buf
padding -
dw
dw
d"
dw
d.
dw
d ..
d ..
dw
d ..
5000 dup (0)
1388h
cgroup:llP_buf
°°
°0
°°°
°00
itwice the required size
;A1-A16 of General Purpose Buffer EA
;A17-A23 of General Purpose Buffer EA
;IPX packet length plus header length
;A1-A16 of General Purpose Buffer EA
;A17-A23 of General purpose Buffer EA
;current rx head, buffer has been flushed to
;value read from 10 cent latches
;used during rx list generation
;point to reset the DMA controller
0
;calculated at init for use by IPXReceivePacket
0
0
180 dup (0)
0
0
0
Define Hardware Configuration
290189-20
1-438
Ap·320
Table 2. Declarations (Continued)
db
ConfigurationID
'NetWareDriverLAN WS
SDriverConfiguration
LABEL
reservedl
node addr
reserved2
node addr type
max data size
(512, 1024, 2048, 4096)
lan desc offset
lan-hard;ar. id
transport tiia
reserved '3
major_veision
minor version
flag bits
selected configuration
addresses, etc.)
number of configs
configJ>oInters
db
db
db
db
dw
LANOptionName
configurationO
db
dw
db
dw
db
db
db
db
o
o,
o
o,
byte
4 dup (0)
6 dup (0)
0
inon-zero means is a real driver.
;address is determined at initialization
1024 ;largest read data re~est will handle
°
dw
db
dw
db
db
db
db
db
LANOptionNama
OAAh
;Bogus Type Code
1
;transport time
11 dup (0)
Olh ;Bogus version number
OOh
0
0
iboard configuration (interrupts, IO
db
dw
01
configurationO
db
'Intel LAN-On-MOtherboard Module',O,'$'
dw
300h, 16, 0, 0
;IO ports and ranges
0
0
;memory decode
;interrupt level 10
iDMA channels 6 and 7
OFFh, 10, 0, a
OFFh, 6, orFh, 7
0,0
I
IRQ 10,
IO Addr = 300h, DNA 6 and 7, For Evaluation Only', 0
;*********************************************************
Error Counters
;********************************************************
Public DriverDiagnostieTable,DrivarDiagnosticTaxt
DriverDiagnosticTabla
DriverDebugCount
DriverVersion
StatisticsVersion
TotalTxPacketCount
TotalRxPacketCount
NOECBAvailableCount
Packet~xTooBigCount
PacketTxTooSmallCount
PacketRzOverflowCount
packetRzTooBigCount
PacketRxTooSmallCount
PacketTxMiscErrorCount
PacketRxMiscErrorCount
Retry'l'xCount
ChecksumErrorCount
LABEL
dw
db
db
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
byte
DriverDebugEnd-DriverDiagnosticTable
01,00
01,00
0,0
0,0
0
;not used
-1
;not used
-1
0
0
0
;not used
-1
; not used
-1
0
inot used
-1
290189-21
1-439
intJ
AP-320
Table 2. Declarations (Continued)
HardwareRxHismatchCount
NumberOfCUstomVariables
DrivarDebUgEndl
LABEL
o
dw
dw
(DriverDiagnosticText-DriverDebugEndl)/2
byte
:;;,';;;;;;;;;:;::::;:;;;;;;:;:;:;;;;;;;
Driver Specific Error counts
:;;;;i;;;;:;;;;;;;;:;;;;:;;;;;;;;;::;::
rx errors
under runs
no_cta
no cra
X'x-aborts
no-S90 int
false 590 int
lost ix
stop:tx
ten cent latch crash
rx disb failure
t xabort failure
rx-buff ovflw
tx:timaout
-
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
dw
DrivarDiagnosticText
db
db
db
db
db
db
db
db
db
db
db
db
db
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LABEL
byte
db
'RxErrorCount',O
'UnderrunCount' , 0
'LostCTSCount',Q
'LostCRSCount',O
'RxAbortCount',O
'NoS90XnterruptCount',0
'False590InterruptCount',O
'LostOurReceiverCount',O
'QuitTransmittingCount',O
'TencentLatchCrashCount',O
'RxDisableFailureCount',O
'TxWontAbort',O
'ReceiveBufferOverflow',O
' Tx'limeoutErrorCount' ,0
db
0,0
DriverDebugEnd
LABEL
word
290189-22
1·440
inter
AP·320
7.2 Initialization Routine
This routine, Driver Initialize, initializes the Embedded
LAN Module hardware and the system hardware needed to support the module. It also sets up the system
memory structure to support the module.
7.2.1 HARDWARE INITIALIZATION AND 82592
CONFIGURATION
Initialization of the Embedded LAN Module hardware
begins with generating an individual address for the station, initializing the interrupt line and interrupt vector,
and enabling the module by writing to port address
303h. After initializing the memory structure, the
82592 is directly programmed. This programming includes configuring the 82592 and initializing it with the
station's individual address. The 82592 is configured in
two steps. The first specifies a 16-bit-wide system bus
interface by issuing a Configure command to the 82592,
with OOh as the byte count; i.e., no parameters passed to
the device. Then ~ second· Configure command is issued; it does the following.
• The 82592 is put in High Speed Mode to support
Ethernet serial bit rates.
• It is placed in TCI mode for interface to the Embedded LAN Module architecture.
• All network parameters (e.g., Frame Length, Slot
Time, and Preamble L~ngth) are set up for default
Ethernet values.
Following this initialization and configuration of the
module's hardware, the 8259A Programmable Interrupt Controller's interrupt line for the module is enabled, allowing the interrupt-driven events frame reception and completed transmission. Then a Receive ~n
able command is issued to the 82592. Table 3 contams
the code for hardware initialization.
Table 3. Hardware Initialization
.egment 'CODIt'
publie
Dd..... dnitiali •• , Dd.... rUnJlook
no card message
db CR,LI', 'No adapt.Z' installed in PC$'
confi; failure ma ••age
db CR,LI', 'COnfiquration ... 11ure$'
i.sat failure iDa •• &g8
d]) ca, II, , IA Setup "allure$'
confiiDataUndirz:unHa..
db Cl\,Lr, 'COnfiguration underrun$'
Driver Initiali.e
aaSUl'Cl8a:
DS, SS ue ••t to CGJ:Oup ( - CS)
OI points to where to stuff node addresa
Inter:rupta an BNABLBD
The Real T.ime Ticks variable is being set, and. the
.ntira US .y.t.... i. initiali.ed.
returns:
I f initialization ia clone OK:
AX ha• • 0
Xf board malfunct.i.on:
AX qat. oft.et (in CGroup) of ' $' -ta.mdnated error string
Driverlnit1ali •• PllOC
NEAR
mov
MaxPhyal'acketSiz., 1024
eli
cld
mov ax, cs
mov cU, aa
move., as
g.t DOS tima and u •• for addre ••.
mov
ah,02Ch
int
21h
mov
ba, OrrSBtz CG&'Ou.p: node_addZ'
mov
byte pt" cgroup: [bZ], OOh
mov
byte pt" cg"oup: [1»:+1], OAAh
mov
byte pt" cg"oup: [1»:+2], ch
mov
byte pt" eq"oup: [1»:+3], ell
mov
byta pt" eq"oup: [1»:+4], cIh
mov
byte ptr egroup: [b,,+S], 711h
mov
ai, bx
; stuff address at point IPX incU.cated
move ..
move.
movsw
ati
in1tiallze the configuration table
mov
cbw
al, •• lected_configuration
ah~
ax,l
; IINltiply by two
eat o..rSE~ CGaOUP: config...,POinters
add
; ax contains the offset' va~\1e
290189-23
1-441
inter
AP-320
Table 3. Hardware Initialization (Continued)
mov
!IOV
bx/az
bx, [bx]
!IOV
!IOV
Config,bx
a1, [bx+DMAOLOC]
mov
mov
config_dmaO~loc,al
!IOV
al, [bx+DMA6LOC]
config_dma1_1oc,al
al, [bx+laQtoC]
mav
mav
mav
ax, [bx+BPOaT]
command_reg, 300h
mov
;of the default configuration
;list
config_i~10c,a1
SetThelnterruptVector:
SET UP THB IN'rEIUUlPT VECTORS
push
mav
mov
call
pop
mov
out
hlow
mov
mov
out
di
aI, config_ir'l...loc
bx, OFFSET CGroup: DriverISa
SetlnterruptVector
di
dx, EnLAN
dx, al
;enab1a LAN on MB module
dx, cODl'l\l.ftd_reg
aI, C RS'!'
dx, aT
; reset the 82592 controller
;generata 20 ~it address for DMA controller from configure block location
;this i8 necessary to accomodate the page register used in the PC DMA
iset up DNA channel for configure command
xor
out
'slow
mov
out
mov
hlow
out
mav
'slow
out
mav
'slow
out
!IOV
hlow
out
mav
hlow
out
mov
%slow
out
mav
ax, ax
DMAff, al
idata 1s don't care
a1, DMAana
DMAemdstat, al
ax, gp_buf_start
DMA6add.:, a1
al, ah
DMA6addr, a1
ax, gp_bufJ'age
DMA6page, al
ax, 1
DMA6wdeount, a1
aI, ah
DMA6wdeount, al
al, DMAtx6
;DMA page value
;make two transfers
;satup channel 6 for tx mode
DMAmode, al
al, DMA6unmsk
290189-24
1-442
intJ
Ap·320
Table 3. Hardware Initialization (Continued)
'slow
out
DKAsnglmak, al
ax, ax
mov
atoaw
atcsw
di, gp buf off.et ;mov .eroes into the byte count field of the
-;buffer to put the 82592 into 16 bit mode
,..,r
the
%&10"
mov
mov
out
hlow
dx, cOll'IDand_req
al, C CONl'IG
dz, .1
;configura the 82592 for 16 bit mode
ii.sua configure command
wide_mode_wait_loop:
xor
a1, a1
-'lIslow
out
'slow
in
and
c:mp
jz
loop
mav
jmp
dz,.l
;point to register 0
al, dz
;read register 0
al,ODl'h
; disregard exec bit
al, 82h
; is configure finished?
do_config
wide mode wait loop
ax, OFFSET OGroup: no_cArd_message
init_exit
do_config:
mav
al, C IN'rACK
out
dz, aI
xor
ax, ax
; clear interrupt
%slow
out
mov
hlow
out
mov
%slow
out
mav
%slow
out
blow
mav
out
hlow
mav
out
talow
mov
out
blow
mov
out
mov
mov
mov
mov
DMAff, al
ax, gp_buf_start
;data is don't care
DMA6addr, .1
al, ab
DMA6addr, al
ax, gp_bufJ>age
DMA6page, .1
al, DMAtx6
DMAmode, al
;DMA page value
;setup channell for tx mode
ax, 8
DMA6wdcount, al
al, ah
DMA6wdcount, al
al, DMA6unmsk
DKAsnglmak, &1
ax, da
as, ax
ai, offset cgroup:config_block
di, gp_buf_offset
290189-25
1-443
inter
Ap·320
Table 3. Hardware Initialization (Continued)
mov
rep IIIOvsb
IIIOV
IIIOV
out
blow
xor
ex, 18
dx, command_reg
al, C CONJ'IG
dx,
al
configure the 82592
ex, ex
config_wait_loop:
h10w
xor
a1, a1
hlow
out
dx, al
:point to register 0
hlow
in
al, dx
: read register 0
and
al, ODFh
:discard extraneous bits
cmp
al, 82h
: ia configura finiahed?
jz
config_done
loop
config_"ait_loop
IIIOV
ax, OFFSET CGroup: config_fai1ure_messsge
jllq>
init_exit
config_done:
clear interrupt caused by configuration
IIIOV
al, C INTACIC
out
dz,.1
do an lA_setup
IIIOV
di, gp_buf_offset
mov
stosb
mov
stoab
IIIOV
Il10''
rep movsb
out
'.low
IIIOV
out
mov
'slow
out
IIIOV
h10w
out
blo"
mov
out
h10w
mo..
out
islow
Il10''
out
'810w
IIIOV
out
al, 06b
iaddress byte count
a1, OOh
ai, OFFSET CGROUP:node addr
ex, SIZE node_addr
DMAff, al
:data is don't care
ax, gp_buf_start
DMA6addr, al
al, ah
DMA6addr, al
ax, gp_buf"'page
DMA6page, al
a1, DMAtx6
DMAmode, a1
:DHA page value
;setup channell for tx mode
ax, 3
DMA6wdcount, a1
al, ah
DMA6wdcount, a1
a1, DMA6unmsk
DMAsngllllak, a1
290189-26
1-444
inter
AP-320
Table 3. Hardware Initialization (Continued)
mov
mov
out
xor
cIx, COJlllNlnd_reg
al, C IASET
cIx,
;set up the 82592 individual address
a1
ex, ex
i. used by the loop instruction below. this
;e_u.s•• the loop to be executed 64k times max
lax
ia wait loop:
- zoral,_l
out
cIx, al
talow
in
al, cIx
al, ODFh
and
;discard extraneous bits
cmp
al, 8lh
is command finished?
jz
ia done
loop
ia wait loop
mov
ax; OFFSET CGroup:
init_exit
jmp
ia_done:
mov
al, C INTlICK
out
dx, al
;c1.a2: interrupt from ieset
;initialize the receive DHA channel
XOr
al, 81
out
DMAff, al
mov
ax, r.K_buf_start ;set dma up to point to the beginning of rx buf
%slow
out
mov
talow
out
mov
blow
out
mov
blow
out
mov
hlow
out
mov
blow
out
mov
hlow
out
DHA7addr, al
aI, ah
DHA7addr, al
ax, rx_bufJ>age
:set rx page register
DMA7page, al
aI, DMArx7
DMAmode, .1
ax, rx_buf_length
:set wordcount to proper value
DHA7wdcount, al
aI, ah
DHA7wdcount, al
al, dma7unmsk
;unmask receive DMA channel
DMAsnglmsk, al
;unmask our interrupt channel
in
al, InterruptNaskPort
mov
bl, OFBh
and
al, bl
'slow
out
InterruptMaskPort, al
;enabla the receiver
cIx, command reg
mov
al, C RXENBIIIOv
cIx, a1
out
xor
;enabla receives
ax, ax
290189-27
1·445
inter
AP-320
Table 3. Hardware Initialization (Continued)
mov
ez., 1
init exit:
ret
ConfigDataUnderxun:
mav
ax, OFFSET CGroup: ConfigDataUnderrunMess
jmp
init_exit
IASetupDataUnderrun:
mav
ax, OFFSET CGroup: IASetupDataUnderrun
jmp
init_ezit
Drivarlnitialize
endp
SetInterruptVector
Sat the interrupt vector to the interrupt procedure's address
save the old vector for the unhook procedure
assumes: bz has the ISR offset
al has the IRQ level
interrupts are disabled
SetlnterruptVector
PROC
NEAR
mask on the appropriate interrupt mask
push
ax
xchg
ax, ex
1
IDOV
d~,
shl
mav
not
mav
mav
mav
pop
old
cbw
"or
mav
add
dl, cl
int bit, dl
ahl
shl
xchg
mav
mav
mav
mav
mav
xchg
stosw
IIIOV
;get tha appropriate bit location
iset the interrupt bit variable
dl -
int mask, dl
;set the interrupt mask variable
ax,-XnterruptMaskPort
int_mAsk_register, ax
ax
ex, ex
es, ex
al, 6Sh
;adding 8 converts int number to lnt type, i.e.,
=
lint 4 - type 12, int 5
type 13 etc.
ax, 1
ax, 1
;two shifts • mul by 4 to create offset of vector
ax, di
int vector addr, di
;sava this address for unhook
ax,-as: [di]
;save old interrupt vector
word ptr old_i~vector, ax
ax, es: [di] + 2
word ptr old_i~vector + 2, ax
ax, bx
;bx has the tSR offset
ax, cs
290189-28
stosw
ret
SetInterruptVector
endp
290189-29
1-446
inter
AP-320
• No page break occurs. The buffer size is not adjusted, the Tx/GP buffer area will be in the first 1200
bytes of the 10 kB buffer, and the Rx area will use
the remainder.
• A page break occurs, and the buffer is divided so
that one fragment is' smaller than 1200 bytes. This
fragment is too small to be used and both the
Tx/GP and Rx areas will be placed in the larger
segment.
• A page break occurs that divides the 10 kB buffer
into two segments both large!; than 1200 bytes. The
software then places the Tx/GP area in the smaller
segment, and the Rx area in the larger.
7.2.2 INITIALIZING SYSTEM MEMORY
A buffer is constructed in system memory to support
the Embedded LAN Module architecture. This buffer
is divided into a receive buffer area and a transmit/general-purpose buffer area. This buffer (Tx/GP) is used as
the transmit buffer and as the parameter block for
82592 commands that require parameters.
The combined size of the buffer areas requested by the
program is 10 kB. The Tx/GP buffer should be at least
1200 bytes long. The Rx buffer should be at least 5 kB
long. The amount of memory requested is twice the size
of the minimum Rx buffer length because of the possibility of a DMA page break occurring at some point in
the 10 kB buffer area. A page break can occur because
the SYP301 (or any PC AT based architecture) uses a
static page register to supply the upper address bits
(A17-A23 for a 16-bit DMA channel) during a DMA
cycle. These upper bits of the address cannot be incremented. The software checks for a page break and adjusts the buffer size if one is found. There are three
possible page break scenarios.
Buffer
gp-.bu'-start
Start
These three scenarios are shown in Figure 12. In no
case is the Rx area less than 5 kB-half the total buffer
size. Once these calculations are made, the transmit
and receive DMA channels, along with their page registers, are programmed to point to their respective areas
in the buffer (Tx/GP and Rx). With the memory now
initialized, configuration and initialization of the 82592
can begin.
Buffer
Suffer
Start
Start
A
A
A
Unusable Portion
Transmit and
General Purpose
Buffer Space.
(Less than
Transmit and
General Purpose
Buffer Space,
gp_bu'-start
1200 Bytes)
DMA
1200 Bytes
boundary
1200 Bytes
~buf--start
B
B
Transmit and
DMA
General Purpose
Buffer Space.
Wasted Space
boundary
1200 Byte.
Receive Buffer =
Total Buffer Space
",-"u'-start
C
- 1200 Bytes
C
Receive Buffer =
-A+B
-A+B
(1200 bytes
framend)
Buffer
End
No DMA boundary in the buffer space.
Tx/GP buffer is located in the first 1200
bytes. Rx buffer occupies the balance of the
space.
latalSuffer Space
Receive Buffer =
Total Buffer Space
OL-buf_stop
rl<-buf_stop
",-"u'-stop
(1200 byte.
framend)
framend)
(1200 bytes
Buffer
Buffer
End
End
DMA boundary exists in the buffer space.
and the first fragment is to small to use (less
than 1200 bytes). The buffer start point is adjusted by adding the length of the fragment
to the original start pOint. Tx/GP buffer occupies the first 1200 bytes after the DMA
boundary, Rx buffer occupies the balance of
the buffer space.
.
DMA boundary exists in the buffer space.
The first section is the smallest section. so
the buffer is located there. The receive buffer occupies the larger section of the buffer.
Figure 12. DMA Page Break Affect on Buffer Size
1-447
inter
AP-320
The Rx buffer .area is implemented as a restartable linear buffer. As frames are stored in this buffer they are
processed by the IPX routine IPXReceivePacket. A
variable called ~BUF_STOP points to a location
1700 bytes from the end of the Rx area. On reaching
(or passing) this location in the Rx area, frame reception is temporarily disabled, and the remainder of the
receive frames ary processed. After the last frames have
been processed, the receive area is reinitialized, the receive channel DMA is initialized to point back to the
beginning of the receive area, and frame reception is
reenabled. Table 4 contains. the code that initializes the
buffer memory. Section 7.3 gives further information
on receive frame processing.
Table 4. Buffer Memory Initialization
.;
Sat up BuffetS:
This toutine genetates the page and offset addz:esses fot the
1~
bit
PMA. It checks for a page crossing and uses the smaller half of the
buffat araa fot Tz and ganetal purpose if a crossing is detected. If
no ctossing is detected the general purpose/transmit buffer is placed
at the beginning of the buffer area. This routine also generates a.
segment address tor the receive buffer which allows the value read
from the "10 cent" latches to be used as read fot the offset passed
to IPXReceivePacket. This saves soma arithmetic steps when tracing
back through the rz buffet chain.
proc
ne.:
mov
mov
ax, offset cgtoup: 9'P_buf
9'P_buf_offset, ax
mov
bx, as
dx, es
mov
shr
mov
ax, 1
ex, 3
shl bx, cl
rol dz, cl
;gat upper 3 bits for page register
and dz, 0007h
;clear all but the lowest 3 bits
add ax, bx
;ax contains EA of first location in buffer
adc dz, 0
;if addition caused a carty add it to page
mov ex, OFFFFh
;of buffer to page break
sub ex, ax
;cx contains the number of bytes to page break
""" ex, Ol388h
jb
intel_hop
jmp copacetic
iit's cool, whole buffer space is in one page
intel hop:
ciiip ex, 0258h
ja
low ok
;low fragment is a usable size, check upper fragment
add az,-cx
imove pointer past the page break to discard fragment
sub 9'P_length, ex ;adjust length variable to reflect shorter length
mov 9'P_offset_adjust, ex
shl 9'P_offset_adjust, 1
;convert to byte format
mov ex, 9'P_offset_adjust
add 9'P_buf_offset, ex
;adjust 9'P_buf starting point to reflect change
jmp copacetic
;both buffers will be ift the same page, rx bUf
shortenad
low_ok:
""" ex, 1130h
jb
high_ok
mov 9'P_length, ex iadjust length variable, discard upper buffer fragment
;both buffets will be in the same page, rx buf
jmp copacetic
shortened
high"';Ok:
ja
"""
mov
shl
inow
ex, 09C4h
z:x first
9'P:bUf,J>age,
9'P_buf.J'age,
since both fragments are usable we have to find the
;actual page break. the large half will be the receive
;buffer and the small half will be the 9'P-tx buffer.
dz
1
290189-30
1-448
inter
AP-320
Table 4. Butfer Memory Initialization (Continued)
....
IIIOV
IIIOV
add
IIIOV
.1>1
.1>1
ado
IIIOV
IIOV
....,12
a"l
D, cl
n_"
IIIOV
""_buf_.~t, D
alii>
vp_laDgtb, ba
....
, buf_laDgtb,
Vp_laDgth
__
......
.ub
."1
acid.
......
:l1IIP
IIOV
_
vp_buf_ataR, g
zoo_buf_.taR, 0100"
__but_booad, OOOOb
D,
1
__buf..,page,
: - page
__buf..,page, D
1
g, 1
D, 0
ba, ex
:.a...
of byt. . to page bnak
c'"
ox
258h
ox, 1
ox, g
~_bu.f'_.t.op,
buff...._ ••t
ex
fba":
-...... "x_buf..,page, D
.hl __buf"page, 1
IIOV
"_buf_.taxt, ...
Il109 za but' head, ...
abl _ -buf-booad, 1
IIIOV
_j.uf:lallgtb, 0"
IIIOV ",,_buf_atop, On9Z11
: 1200 byt.a f" .... end of buU."
...." vp_buf_.taR, OOOOh
acid. D , i
: _ page
IIIOV vp_buf..,page, D
.bl vp_b..f..,page, 1
add ca, 1
ahl ca, 1
IIIOV Vp_OUHt_ad:l ...t, ox
acid. vp_b..ILoffa.t, 0"
aub D, 1
ahl D, 1
.bl g , 1
ado D, 0
mo" oa, 12
.hl D, 01
Il10'9' z:.._buf_. . . .ftt,dz
:l1IIP buff."._Ht
copao.tio:
IllOV
gp_buf_ataJ:t., ax
acid. g , 258h
mo... n but ataR, ax
• 111
~.:buf:haad, ..
zoo_buf_.....d, 1
.111>
...."
...."
sbl
......
vp_lallgtb, 258b
- , vp_laDgtb
zx_buf_laDgtb, ox
D,
1
__buf..,page,
D
......
vp_buf..,page, D
IIDOV
:Ai-AU of Vp buff.", gp buff.., ia nut
: 1200 byt•• fo" Vp buff." at f..ant of buff." space
: " .. buU.., sta""a 1200 byt•• io
; COD""" .....nt. to byt.. ac!dra ••
290189-31
IIIOV
ax, 1
D, 0
ex, 12
abl
ade
aIll
dx, 01
IIIOV
IIIOV
"x_buf_HglMftt, D
add
az, cz
zoo_buf_.top, ax
: aon...R ofh.t to byte a _ . s
: ad:l ..st s _ n t fo" shift
; loacS vaz:iahl. foZ' transfers to IPX
ex, zoo_but_length
i setup n.J:keZ' :for low rx buffer: apace, >600 words
aub ox, 258h
ahl ox, 1
...."
buff.....at:
~-
290189-32
1-449
7.3 Assembly and Transmission of
Frames
Frame assembly and transmission is accomplished by
the interaction of the software driver and IPX'through
the use of IPX Event Control Blocks (ECBs). To transmit a frame, a transmit ECB is prepared that contains
address information and a list of fragments in memory
containing the frame to be transmitted. This ECB is
placed in a queue for assembly and transmission of the
frame. If the queue is empty, or when the ECB reaches
the front of the queue, a routine is called that processes
the ECB for transmission. This routine determines the
length of the frame (padding the frame if necessary)
and then constructs the frame in the Tx/GP buffer
area. The I;OIlstruction of the frame is based on the
ECB's address information and fragment list. The
transmit DMA channel is now initialized to point to
the beginning of the transmit frame in the Tx/GP area,
and the byte count for that channel is also initialized. A
Transmit command is now issued to the 82592. A separate routine monitors the transmission for a time-out
error. When an interrupt from the 82592 indicates that
the transmission attempt is complete (whether successful or unsuccessful), or if a time-out error has occurred,
the proper completion code is inserted into the frame's
ECB, and the ECB is passed back to IPX. If additional
ECBs remain in the transmit queue the processing of
the next ECB will begin. Table 5 contains the code used
for assembly and transmission of frames.
Table 5. Assembly and Transmission of Frames
Assumes
11:1: II points to a fully prepared lI:"."t COntrol Uock
DS • CS
Int.r~. ar. DISABLED but may be reanabl.d t.apor.rily if Dec••••ry
don't aeed to a.ve any ...gi.t.ra
DriverBroadca.tPaeket:
Dr!verS.nd»acket
PROC
RZAa
eli
; disabla the intarrupt.
C&, ....rd ptr send list + 2
jcza Ad4TOFrontOfLiat ••arch to the end of the list, and add. there.
IIIOV
di, word ptr .end_liat
_v
Ad4~oI.istLoop :
mov
de, c:&
oz, de: word ptr [diJ .link
je:... AddListlilftdround
IIIOV
di, de: ....rd ptr [diJ .link
jmp Ad4ToI.iatLoop
IIOY
AddLiatBndl'ound :
IIOV e.: word
IIOY • • : .... z:cl
IIOV de: .... z:cl
IIOV de: ..oz:cl
IIIOV
.oZ, ca
IIOV
de, a'"
ptr
ptr
ptr
ptr
[aiJ
[aiJ
[diJ
[diJ
+2
.link, e",
• link + 2, e",
. link, a1
. link + 2, a.
;move null pointer to ne_.t
;link fiald
sea'.
;.at de back to entry condition
"at
Ad4~ol'rODtOfI.iat :
mov
e.: ..ord pt,,[a1J . link, e",
:word pt,,[a1J . link + 2, oz
!IOV ....z:cl pt" aend liat, ai
!lOy word ptr aend-liat + 2, aa
d"op through to Bta..t Send
IIIOV
••
Drive"SendJaeket
end9
StalOt Sand
.a."'.:
11:8: SI
points to the BCB to be ••nt:.
int.rrupts are di.abl.d
.tal'!: .and
pul>l1c
eli
"ROC
RZAa
atalOt .end
di.able_ the interrupt.
290189-33
1-450
Ap·320
Table 5. Assembly and Transmission of Frames (Continued)
cld
.ave SCB addre.. in variable tx_ecb to liberate registers
IDOV
word ptr tx ecb, si
IIIOV
word ptr tx:ecb + 2, es
push de
;save de for futu~ use
gat IPX packet length out of the first fragment (IPX header)
lde bx, e.: dword ptr [sil.fragment_dascriptor_list
IDOV
a .., de: [bxl.packet_length
pop de
; ~.to~ de to CGROOP
push a..
;.ave length for later uae in 590 length field
xchg al, ah
;byte s.ap for 5'2 length field calculation
add a .., 18
;add in the overhead byte. DA,SA,CRe,length
padding, 0
ax, 64
ja
long enough
....v
paddIng, 64
;lIIin1mwD length fr .....
sub padding, a ..
;pad length
mov ax, 64
long enough:
ax, 10
;SA and CRC are dona automatically
inc a ..
and al, OI'Bb
; frame must be evan
mov tx_byte_cnt, ax
mov di, gp buf offset
IDOV
CIIIP
sub
mov
bz,
as -
JllC)V
•• ,
bz
move the byte count into the tranllJllit buffer
at.oe"
move the destination addre... from the tx IICB to the tx buffer
mov
bz, a1
lea .i, [bxl.immediate addre.s
mov de,word ptr tx_ecb-+ 2
movav
IIIOve"
mo"a"
mo"
ax,es
mov
da,ax
; gat back to the code (Dgroup) section
no. the 590 length field
pop a"
zchg ah, al
inc ax
;make su~ B-Net length field is even
and al, OI'Bh
xchg ah, al
stos.
lds ai, tx_ecb
mov ax, de: (sil.fra~nt_count
lea bx, [ail .fragment_descriptor_list
move_frall_loop:
; save the .egment
puah de
mov ex, da: [bzl.fragment_length
lde si, de: [bzl.fragment_addre.s
tfastcopy
; get the .egment back
pop de
add bx, 6
dec ax
jns move_frag_loop
290189-34
1-451
Table 5. Assembly and Transmission of Frames (ContinuEld)
letart transmittlng
mo... ex, ca
1109 de, ex
; add any nqulnd. pad.d.1ng
mo" ex, 4
; ...lee aun I!ra... end.a "lth a NOl'
add ex, pa~ng
ehr ex, 1
rap etoe"
mo" tx_actl"._flag, 1
&OZ'
ax, ax
out DHII.fI!, al
;data 1. don't can, AX baa baen zaroed.
mo" ax, gp_bul!_8tart
'.10"out
mo"
'.low
out
mo"
'.low
out
'slo"
mo"
out
mo"
add
.h~
DNA&ad.d.r, al
al, ah
DNA&addz, al
ax, gp_bufJlage
DNA&paga, al
;DNA page "alue
al, DNAtx&
; setup channal 1 I!o" tx moda
DJU.moda, a1
ax, tx_byta_cnt
ax, 4
;add two fo" byta count, two fo" tx chaln fetch
ax, 1
iconvert to .om value and account fOl: oc:lcl
ax, 0
;byte DNA transfar
DNA&vd.count, a1
ado
out
'.low
mo" a1, ah
out DNA&vd.count, a1
'.low
mo" a1, DNA6U1111U1le
out DMAsnglJaele, a1
mo" d.x, c_nd._zag
mo" a1, C TX
out d.x, al
mo" ax, Il'Xlntar..alJlarur
mo" tx start t1lll8, ax
'lnc32 -Totalizl'aclo:atCount
rat
i;············_·_··_·_····-····_-·-····_---_·_·-······ **.* ••• ****
Poll the =1"." to .ea if tha.,a is anything to do
Ie than a t.,ansmit tilll8out? If 80, abort t.,ansmiuion anci .,atUEn'
BCB "lth bad. completlon coda. Checle to saa if f.,ames an quauaci.
II! thay an .at up BS:SI and. call D.,i"..,Sand.l'ackat.
~*****************************.*********.******.***.****.********.*****
D.,iva.,Poll
PROC
cli
290189-35
1·452
inter
AP·320
Table 5. Assembly and Transmission of Frames (Continued)
amp
jz
may
.ub
amp
jb
tx active flag, 0
HorWait~Tx
dx, IPXlntarralMarker
dx, tx_atart_t~
dx, TxTiaaOutTicka
HotTimadOutYat
Thia transmit ia taking too long .0 lat'.
t.~nata
it now
Iasue an abort to the 82592
may
lIDO"
out
dx, CCllllllllnd rag
al, C UORTdx, a'1
labort transmit
inc
la.
tx t~out
ai; tz acb
as: [all.complation coda, TransmitHardwareFailura
coda of a failed tx
Il10'' ax, .s: word ptr [ail . link
Il10'' word ptr aand_list, ax
IIIOV
ax, aa: word ptr [sil.link + 2
Il10'' word ptr sand_list + 2, ax
mov
Istuff completion
Finish tba transmit
es: [sil.in uae, 0
call IPXHolcll:ve.it'
Il10''
;make sura that ezecution unit didn't lock up because of abort arrata
IIIOV
mov
out
IIIOV
'..low
out
IIIOV
%slow
out
Il10''
'slow
out
IIIOV
dx, cCllllllllnd_rag
al, C SWli'l
dz, a'1
al, C_SELRST
dz, al
al, C_SWli'O
dz, al
al, C_RXEIIB
dz, al
tx_activa_flag, 0
See if any frames ara queuad
ex, word ptr sand list + 2
jcxz queua_empty
es, ex
Il10'' si, word ptr send_liat
call start_send
100"
IIIOV
queua_empty:
HotWaitingOnTx:
HotTimadOutYet:
rat
290189-36
1·453
Ap·320
Table 5. Assembly and Transmission of Frames (Continued)
DriverPo11
endp
;****************************************************************
Interrupt Procedure
;*****.****.*****.* •••••• ** ••• **** •• *****************************
even
RxZrrorTypeCbeck,
Buffez:Overflow,
inc
rx buff ovf1v
jmp
int_ezit
not 590 int,
-1nc- no 590 int
;Imp int_ezIt
Driverlsa
public
push
push
push
push
push
push
push
PROC
DriverISR
far
ax
bz
ex
dz
si
di
bp
push ds
push ea
cld
call
mov
out
out
mov
IIIOV
IIIOV
IPXStartCr1ticalSect1on ;tel1 ABS we're busy
al, BOI
InterruptControlPort, a1
BztralnterruptControlPort, a1
ax, c.
ds, ax
;DS points to C/DGroup
dz, cOllllll&nd_reg
a1, 0
mov
;.at statue reg to point to reg 0
out dx, a1
"'lov
a1, dz
in
teat a1, SOh
not_590_int
;10:
and
81, NOT
IIIOV
ah, a1
ah, OD8h
ClOP
20h
;ignore the BXBC bit
;sava the status in AH
;did I receive a frame?
290189-37
1-454
inter
AP-320
Table 5. Assembly and Transmission of Frames (Continued)
jz
rCvcI..J>aakat
ah, 84h
:cU.d X flniah a transmit?
sent..J>aaket_jmp
ah, 8Ch
;d.id I finish a retransmit?
..nt..J>aaket.-:jmp
falae_S90_int ;unw.ntad interrupt
int_exit
cmp
jz
cmp
j.
inc
jmp
l5ent-paoket_jmp :
jmp .ent..J>aekat
sent-packat :
eli
tx_active_flag,
fal.e tx int
a1, di statualO, a1
cmp
j.
in
mov
;ahouldn't have been
t~.namitting
%slow
in
al, dx
statusl1, a1
teat atatuall, 20b.
j.
tx error
:extract the total number of retries from
JIIOV
a1; statualO
and ax, Orh
: the atatua regiat,e: and add to retry oount
ac1c1 Retry'l'xCount, ax
xor ax, ax
; atatua SI 0, good transmit
IIIOV
1..
J'inishUpTransmit:
ai, tx aob
lllOV
es: [all .completion code, a1
mov ax, •• : word ptr [aI) ,link
mov word ptr send l.ist, ax.
ax, .a: wo:c1 ptr [ail . link + 2
mov
mov word pt.r send_list
mav .s: [sl].i.n use, 0
call IPXHoldBvant
+
2, ax
push ca
pop
mov
mov
jezz
mov
cia
ex, wo.J:d. ptr oend_.liat. + 2
tx_aotive_j!lag, c1
int_axit.-:jmpl
aa, ox
i aegment of next seB in list
mqv 81, word ptr send_list
:offaet of next SCD in list
call start send
jmp finish_exit
int_axit_jmpl:
jmp int_exit
false tx int:
jiiip -int_exit
tx error:
- teat statualO, 20h
jnz QuitTran8llll.tting
test statusll, Olh
jt:
lost_cta
inc unc1erruna
:Max collisions??
;Tx underrun??
290189-38
lost cta:
teat statuall, 02h
jz
lost_ora
inc no_cta
loat crs:
test atatusll, 04h
jz
IuImu
inc no crs
hmmm:
lea
call
mov
jmp
i did
we loae clear to send??
:did we loae carrier senae??
-
ai,tx ecb
atart- senel
al, TranamitHardwareFailura
FinishUpTransmit
QuitTransmitting:
mov aI, atat.u810
and ax, on
add RetryTxCOunt, ax
inc atop tx
mov aI, TranamitHardwaraFailure
jmp FiniahUpTransmit
DriverISR
endp
290189-39
1·455
inter
Ap·320
7.4 Receive Frame Processing
Receive frame processing is triggered by an interrupt
from the 82592. If the status read from the 82592 by
the Interrupt Service Routine (ISR) indicates that a
frame has been received, a jump is made to the beginning of the code that services frames. The receive buffer
area is managed by using several variables. These variables are listed below. Please refer to Section 4.1 and
4.2 for a review of receive frame processing.
• RX_BUF_TAIL. Contains the contents of the
16-bit latch. They point to the byte count of the last
frame written into memory.
• RX_BUF_PTR. Keeps track of the current position in the buffer while the CPU recovers locations
of the received frames in the buffer processing.
• RX_BUF_HEAD. Contains the pointer to the
byte count of the last frame that was processed by
the CPU. (This differs from rlL-buf_tail, which
points to the byte count of a frame not yet processed.)
• R~BUF_STOP. Points to a location that is 1200
bytes from the end of the receive buffer (slightly
more than the maximum size of a frame).
After servicing a receive frame, the contents of the
16-bit latch are loaded into RXJUF_TAIL and
RX_BUFJTR. This value is compared with the value stored in R~BUF_STOP to determine if most of
the buffer has been used and if the buffer must be reinitialized after the current receive frames have been processed (In this case a flag called RESET_R~BUF is
set to indicate that the buffer variables and receive
DMA channel must bereinitialized before the Interrupt Service Routine is exited). To process the frame or
frames received, both the byte count and status bytes of
the frame are used. If the status indicates a receive error the frame is not passed up to IPX. The byte count is
used to index back through the chain of received
frames, using RX_BUF _PTR to keep track of the
current position in the buffer. The frames are checked
for length (maximum and minimum), and a check is
also made to verify that the Ethernet and IPX length
fields agree (including provisions for padding the
Ethernet length field). If these checks pass, the frames
are added to the list of received frames by storing their
location, length, and source address in an array of
structures called ~LIST. When the ~BUF_
PTR contains the same value as R~BUF_HEAD,
all currently received frames have been processed, and
a jump is made to a label called HAND_OFF_
PACKET. In this routine the frames are handed up to
IPX, in the order they were received, using calls to the
IPX routine IPXReceivePacket. The value stored in
~BUF_TAIL is loaded into the RX_BUF_
HEAD variable, which now holds the address of the
last location in the receive area that was processed, and
the execution of the ISR falls through to a routine to
exit the ISR. Before exiting the ISR an Interrupt Acknowledge is issued to the 82592; a check for additional
pending interrupts is made, if one is found the ISR
process is repeated; and the flag RESET_RXJUF is
checked, if it is set the receive buffer is reinitialized.
The machine states of the previous routines are restored
to their original states, and the ISR is exited. Table 6
contains the code used for receive frame processing.
1-456
inter
Ap·320
Table 6. Receive Frame Processing
;**************** •• **********************************************
Interrupt Procedure
;************************************* •• ************** •••••••••••
even
RxErrorTypaChack:
BufferOVerflo.. :
inc
rx buff ovil..
jmp
int_exit:
not 590 into
-inc- no 590 int
jmp int_exit
DriverISR
public
push
push
push
push
push
push
push
PROC
DrivarISR
far
ax
bx
cx
dx
si
di
bp
push de
push as
cld
intJ>oll_loop:
eli
call IPXStartCriticalSaction ;tall AES we'ra busy
mov al, EOI
out InterruptControlPort, al
out ExtraInterruptControlPort, al
mov ax, cs
;DS points to C/DGroup
mov de, ax
mov dx, command reg
mov a1, 0
;set status reg to point to reg 0
out dx, a1
hlow
in
al, dx
test 81, BOh
jz
Dot_590_int
290189-40
1·457
intJ
AP-320
Table 6. Receive Frame Processing (Continued)
int.J>oll_loop:
and al, NOT 20h
;ignora tha EXEC bit
mov ah, a1
;s.va the status in AH
c:mp ah, OCBh
;did I "aceive a frame?
jz
"cvcl.J>acket
c:mp ah, 84h
;did I finish a transmit?
jz
8ent.J>acket_jmp
c:mp ah, SCh
;did I finish a retransmit?
jz
sent.J>acket_jmp
inc fals8_S9 O_int ;unwanted inte"rupt
:Imp int_exit
sent.J>acket_jmp:
jmp sant.J>ackat
bad "cv:
-inc
jmp
rx errors
Rxi""orTypeChack
int exit jmp:
-jmp -int_axit
;When the address bytes a"e being read it is possible that anothe" frame
:oould coma in and cause a coherency problem with the ten-cent latches.
;1 am dealing with this possibility by "eading TenCentHi twice and making
;sura the values match. If they don't the read is redone.
rcvcl.J>acket:
eli
mav
dx, TenCentHi
in
al, dx
;read high address byte of last frame received
ah, a1
isava it in ah
dx, TenCentLo
;read low address byte of last frame received
in
al, dx
mov rx buf tail, ax
;thia is the last location containing rx data
;Read TenCentHi-agaln to make sure it hasn't changed ...... .
mov dx, TenCentHi
;read high address byte again
in
al, dx
c:mp al, ah
mov
mov
jz
addr ok
jmp rcvd:packet
addr_ok:
mov
mov
;read the latches again
ax, rx buf tail
rX_bufJ>tr:- ax
rx buf stop, ax
amp
ja
BufferOK
mav
reset rx buf, 1
BufferOK:
this is a valid address
this is the last 1ocation containing rx data
is most Of the buffer already used?
-ax, co: buf head
c:mp
ja
inc
proces8_ne;_frames
ten cent latch crash
jmp
1nt:exit-
-
do next frame:
process:new_frames:
!nOv bx, rx_buf-ptr
sub
bx, 6
moves, rx_buf_segment
end of current frame to process
set bx up to point to beginning of the status
this is necessary because latches hold EA not
offset relative to CGROUP
290189-41
1-458
inter
AP-320
Table 6. Receive Frame Processing (Continued)
a~, .a: [bx].atatua1
teat .~,20h
jnz good_rz
mov cl, ea:[bx].bc ~o
mov ch, es: [bx] .bc:hi
dec ex
and c~, Ofeh
sub hz, ex
cmp rx buf head, bx
je
hand_off-packet_jmp
mov rx_buf-ptr, bz
aub rz_buf-ptr, 2
to do next frame:
- jmp do_naxt_frame
hand_off-packet_jmp:
jmp hand_off-packat
mov
it.at for good receive
;cx has actual number of bytes re.d
; toas byte count £ status
; round up
;bx points to first
good rz:
mov cl, a.: [bz] .bc 10
mov ch, es: [b,,].bc-hi
mov
dec
and
curr_rx_length; ex
ex
cl, Ofah
sub
mov
sub
sub
cmp
bx, ex
rx_bufJtr, bx
rz_buf-ptr, 2
ex, 14
~oc.tion
of frame
;thia was tha first frame in the sequence
;ell: haa actual number of bytes read
; toss byte count , status
i
round up
;bx points to first location of frame
:rz_buf-ptr • last location of n-1
; sub
jbe
cx, 1024 + 64
not too big
inc
packetRiTooBigCount
~ength
~rame
of 802.3 header
jmp do_next_frame
not_too_big:
cmp ex, 30
jae not_too_small
inc PackatRx~ooSmallCount
jmp do_next_frame
not_too_small:
ax, as: [bx] . rx length
xchg al, ah
-
mov
inc
get IPX length
ax
and al, Ofeh
xchg al, ah
cmp ax, as: [bx].rx-physical_langth
jne
xchg
a~;
aii'
802.3 length 1
-
ja
ax, 60 - 14
lan ok
mov
ax,-60 - 14
cmp
; same as
to do next frame
; at least min
~ength
minus header
; yea, continue
; no, round up
len_ok:
cmp
jz
ax, ex
; match physical length
not_inconsistent
; yes, continue
inc HardwaraRxMismatchCount
jmp do_next_frame
not inconsistent:
-'inc32 ~otalRxPackatCount
:&nOV ax, 12
mul
Double word Increment
num_of_frames
290189-42
1-459
inter
AP-320
Table 6. Receive Frame Processing (Continued)
di, ax
rx list [di] , bx
;fir.t location of .th.m.t fr .....
; first location of ipx packet
rz:list [di], 14
ax, ""_buf_s.~nt
rx_list [di + 2], ax
ax, word ptr .s:[bx].J:Z_l.ngth
al,ah
IlIOV
rX_list [di + 4], .x
.x, word ptr •• :[bx].rx_soure._addJ: +
IlIOV
word ptr rX_list [di + 6], 'ax
IIIOV
mov .x, woJ:d ptr •• :[bx].r,,_soure._addr + 2
word ptr rx_liat [di + 8], ax
IlIOV
IIIOV
ax, word ptr .s:[bx].rx_soure._addr + 4
woJ:d ptr rX_list [di + 10], ax
IIIOV
add nWD._Of_fJ:'amas, 1
cmp rx_buf_h.ad, bx
j.
hand_off....P.ek• t
cmp ft\UlLof_framaa, 50
j.
h.nd_off....Paek• t
jmp do_n.xt_fr.....
IlIOV
mov
add
mov
mov
mov
xehg
hand_off""paekat :
mov ai, rx li.t[di]
IlIOV
.a, rX-list[di + 2]
mov ex, rx-list[di + 4]
lea bx, rx:list[di + 6]
eli
push da
eall IPXReeeivePaeket
pop dB
sub num of frames, 1
jz
adjuat-rx head
sub di, 12- jmp hand_off""packet
adjust_rx_head:
IIIOV
ax, rx buf tail
add ax, 2 mev rx buf head, ax
;set rx_buf_head to new value for next receive
; interrupt
int ezit:
-push cs
pop ds
cmp tx_active_flag, 0
jnz finish_ezit
verify that our
~ec.iver
IlIOV
dx, command_reg
mov
out
dx, a1
al, 60h
is still going.
:point to status byte 3
",slow
in
test
jnz
jmp
al, dB
al, 20h
finish ezit
LostOurRecaivaJ:'
finish exit:
elI
290189-43
1-460
inter
AP-320
Table 6. Receive Frame Processing (Continued)
call IPXJtndCriticalSac::tlon
dz, command_reg
al, C INTACK
mov
mo"
out
'alow
zor
out
'_lov
in
dx,
.1
al,
al
; issue
dx, al
intarzupt acknowledqa to the 590
; sat atatua reg to point to reg 0
al, cia
teat al, BOh
jn.
int..f8nding
cmp
resat Z'z buf, 1
no rz-bul zo•••t
:ina
!DOV
out
tslow
out
&1.;
cba7.uk
: mask race! ve meA channel
DHAanglmak, a1
;dt.ta is don't ca:r:e
DMAff', _1
bu~
mov
ax, :ex
mev
rx but-haad, ax
ahl
buf-head... 1
DMA7addr, 81
al, ah
out
mov
tslow
out
mev
at art
: eet dma up to point to the beginning of rx buf
liZ-
DNA7 ad4r I
a1
_1, DM1u:.x7
%a1.ow
out
mav
DMAmoda, &1
ax, rx_ buf_length
; set up
rz buf
%slow
out
mo'"
DMA7"deount,
out
DMA7wdcount, a1
%DOV
cIx, DMAsng.lJnsk
al, DMA7unmsk.
'.1.0"
mev
%slow
out
mov
al, ah
out
dx, a1
dx, command reg
al, C RXENBdz, .T
mav
reaet_Z'x_buf,
mov
no
al.
J:'X
buf reset:
- eli call IPXServiceEventa
pop a.
pop cia
pop
pop
pop
pop
pop
pop
bp
di
oi
cia
ex
bx
290189-44
pop
ax
oU
iret
LostOurRecaivar:
inc
lost rx
mov
al, C RXENB
dz, cOmmand_reg
out
jop
8nding:
jop intJ>oll_loop
290189-45
1-461
inter
AP-320
APPENDIX A
Expanding the 82592 Embedded LAN
Module Architecture to a Low-Cost
Non-Buffered Adapter
ADAPTER BLOCK DESCRIPTIONS
DMA Machine
The basic architecture of the 82592 Embedded LAN
Module can be expanded and applied to a low-cost,
non-buffered adapter. This requires adding a DMA
unit and some logic for a bus master handshake. Such
an adapter would contain no local buffer memory. Its
cost advantage would come from using existing system
memory, as the embedded module does. This adapter is
less complex than most existing designs because it does
not require arbitration logic for access to local memory.
This adapter becomes a bus master when data transfers
take place, either to the 82592 (Tx) from system memory or from the 82592 (Rx) into system memory.
The same features of the 82592 that make it successful
in embedded applications make it well-suited for nonbuffered adapters. As with the embedded module, there
is no intermediate buffering of data in a local memory,
therefore data transfers to and from system memory
take place in real time. The 82592's large FIFO area
allows it to tolerate long system bus latencies during
memory access. The 82592's high-performance, 16-bit
bus interface allows the adapter to efficiently transfer
data to and from system memory when it gains access
to the system bus. The TCI of the 82592 will interface
with the adapter's control logic and DMA unit to provide back-to-back frame reception and automatic retransmission on collision (both without CPU intervention). Figure 13 is a block diagram of the basic architecture of the embedded module modified for a non-buffered adapter application. The block titled "Control
PALs and Latch" together with the 82592 is the core of
the embedded module' architecture. One additional
PAL (PAL C) has been added to the basic architecture
to offer more logic for decoding additional components
added to the adapter. The address latch has also been
expanded to 24 bits. The three shaded blocks (DMA
Machine, Master Logic, and Control PALs and Latch)
show the most likely path for integration on this adapter, providing a three-chip solution of ASIC, 82592, and
'82C501. The 82C37 is common in many ASIC ce11libraries, offering a migration path for this integration.
• 8237 DMA Controller. Serves as the core for the
DMA machine. Performs addressing and control for
data transfers between the 82592 and host system
memory.
• 8-Bit Page Counter. Provides the addressing bits for
the upper bits of address (AI7-A23)'
• 8·Bit Register. Serves as the base register for the
upper bits of the Tx DMA channel for reinitialization for automatic retransmission.
• 8·Bit Multiplexer. Selects between the upper bits of
Rx- or Tx-channel DMA.
'
• 8·Bit Latch. Latches the upper bits of address from
the 8237 (Ag-Als),
Master Logic
• Master PAL. Implements a "master" handshake
with the host system bus to gain access to the bus as
a bus master.
• Timers (2). Controls the maximum time the adapter
can hold the bus, and the minimum time it must
wait before attempting to regain bus access.
Control PALs and Latch (Together
with 82592 and 82C501)
The basic architecture of the 82592 Embedded LAN
Module.
Transceivers
Used to buffer the adapter logic from the host system
bus, for drive purposes. Address consists of 24 bits; and
Data, 16 bits.
1-462
intJ
AP-320
o
zo
-'"
... -<
°"'1°/(11
"'0:'-
0.,,0
~?
N
N
&ll
il~1
(II
10 MHz
290189-15
Figure 13.82592 Non-Buffered Adapter Block Diagram (PC AT Version)
1-463
PC586E
CSMA/CD LAN EVALUATION BOARD
Established CSMA/CD LAN
• Supports
Standards:
- Ethernet (IEEE 802.3 10BASE5)
- Cheapernet (IEEE 802.3 10BASE2)
•
•
•
•
Interfaces to Popular IBIIl! and IBM
Compatible PC Systems:
-IBM PC, PC-XT, PC-AT (8-Bit Data
Transfer)
-IBM PC-AT (16-Bit Data Transfer)
Jumper Selection Offers High Degree
of Flexibility in System Configuration:
- Up to 8 Address Decode Ranges
- Up to 8 Interrupt Lines
- Ethernet (IEEE 802.3 10BASE5)
- Cheapernet (IEEE 802.3 10BASE2)
- Number Of Wait-States
Auto-Configuring for either 8-Bit or
16-Bit Bus Systems
•
•
•
•
•
•
On-Board Transceiver Provides Direct
Coaxial Connection for Cost-Effective
Cheapernet Applications
Pipelined Access in 8-Bit Mode
Increase Performance through
Reduced Wait-States
16 Kbytes of Shared Memory-Mapped
SRAM Enables Higher Performance
Network Operation
Reduces Design Complexity because
No 1/0 Address or DMA Channels
Required
High Efficiency Interleaved Memory
Access Permits Zero Wait-State Access
by Host CPU for Most Cycles
8 Kbytes of "Remote Boot" EPROM
(Optional) Eliminates Need for Disk
Drives
Provides LAN Designer with a
Complete, High-Performance CSMA/CD
Ethernet/Cheapernet Solution
The PC586E evaluation board is a non-intelligent, buffered CSMAlCD LAN adapter card designed to demonstrate Intel's high-performance EthernetiCheapernet chip set. It provides IEEE 802.3 TYPE 10BASE5 (Ethernet) and TYPE 10BASE2 (Cheapernet or thinwire Ethernet) connections for IBM PC, PC-XT, PC-AT and
compatible systems. The PC586E combines the Intel 82586 LAN Coprocessor and the Intel 82C501 Ethernet
Serial Interface with an on-board Ethernet Transceiver into a total EthernetiCheapernet solution. The card is
easily installed in either an 8-bit or 16-bit PC expansion slot and then automatically configures itself for 8-bit or
16-bit data transfers. Its jumpers offer a high degree of flexibility for system-dependent configuration. For
Ethernet applications, the 82586/82C501 pair provide the complete transceiver cable interface required by the
IEEE 802.3 standard. In addition, the PC586E's on-board transceiver provides the entire coaxial cable interface for convenient, cost-effective Cheapernet systems.
Analog
Interface
82C501
82502
Bus Interface Logic
Word Assembly/Disassembly
290196-1
Figure 1. PC586E Block Diagram
The PC586E is provided solely as an evaluation tool for use in designing with Intel's 82586 chip set. It has not been tested for compliance to FCC
requirements for EMI (Part 15, subpart j). Intel is not responsible for any misuse of this evaluation board.
1-464
October 1988
Order Number: 290196·001
intJ
PC586E
The PC586E is part of Intel's LAN Evaluation Board
program. The board is intended to demonstrate the
high-performance characteristics of the 82586 chip
set in an adapter card application. The PC586E
gives LAN engineers a head start in finding the best
solution for their specific network problem. PC586E
boards are shipped with detailed design documentation (artwork and PAL equations also available).
The PC586E is based on an Interleaved Local Memory Access scheme with Static RAM dual-ported between the 82586 LAN Coprocessor and the Host
System CPU. Access to the board is purely MemoryMapped, and therefore, no I/O ports or DMA channels are required. In additicm to the shared SRAM,
the system supports a "Remote-Boot" EPROM and
32 bytes of Address PROM. The 82586 has access
only to the Static RAM.
MEMORY
which the 82586 is never given wait-states. This precludes the need for wait-state logic for the 82586
and allows the 82586 to run at 6 MHz.
When the 82586 is inactive, the interleaving logic
becomes transparent and the Host System may access the Local Memory with no wait-states (16-bit
buses only). This provides about a 15% to 20%
boost in bus performance.
DESCRIPTION OF INTERLEAVE
LOGIC
Since the 82586's READY and HOLD ACKNOWLEDGE signals are always active, only a simple arbiter is required. The Control LogiC merely interleaves
Host System accesses with 82586 accesses. When
the 82586 is active, the Host System access will occur during the first half of the 82586 "read/write"
cycle. When the 82586 is inactive, the Host System
access will occur at the speed of the Host Bus.
The Local Memory consists of 16 Kbytes of Static
RAM, 32 bytes of Address PROM, 16 Command
Registers, and up to 8 Kbytes of "Remote Boot"
EPROM (Optional). All of the Local· Memory is
mapped into unused memory space of the Host System. Commands are issued to the PC586E by transferring the instruction to a Command Register. The
Command Registers are used for issuing the Reset
and Channel Attention signals to the 82586, enabling interrupts and configuring the board.
If the Host System initiates access to tile static RAM
during T1 or T2 of the 82586 "read/write" cycle, it
will complete operation without any additional waitstates. If the Host System should initiate access during T2 or T3 of the 82586 "read/write" cycle, a maximum of three wait-states will be inserted for an
8 MHz AT system. The maximum number of waitstates depends on the width and frequency of the
Host System.
CONFIGURATION
WORD ASSEMBLYIDISASSEMBLY
There are up to 8 jumper-selectable locations for the
Local Memory and the Command Registers (four of
these locations are mapped above the 1 Mbyte
boundary, FFFFh). In addition, the jumpers are used
for the Interrupt Request Signal which may be asSigned to anyone of eight Interrupt Request lines.
For systems with 8-bit data buses, the PC586E has
a special Word Assembly/Disassembly function. Access to the Static RAM may be made either as 8-bit
or 16-bit operations. If 8-bit transfers are made, the
Word Assembly/Disassembly logic is used to increase performance.
The PC586E automatically detects if it is placed in
an 8-bit or 16-bit expansion slot. When the PC586E
is in a 16-bit slot, a Command Register is used to
program the PC586E for either 8-bit or 16-bit data
transfers. One of the Command Registers can also
be used to disable the interrupt signal.
INTERLEAVED MEMORY ACCESS
The PC586E uses Interleaved Memory Access between the 82586 LAN Coprocessor and the Host
System CPU to increase system performance. One
read or write access is allowed by the Host System
for every read or write access by the 82586. In this
way, high utilization of local memory is achieved.
The logic used is a "cycle-stealing" approach in
WORD DISASSEMBLY
An 8-bit "read" operatiQn to an even address causes 16 bits of data to be read from the Static RAM.
The first 8 bits are transferred onto the Host bus and
the second 8 bits (corresponding to the odd address) are temporarily stored in a latch. When the
subsequent "read" is made to the odd address, the
data stored in the latch is copied onto the Host Bus.
In this way, access to the Static RAM by the Host
CPU is reduced by 50%.
WORD ASSEMBLY
An 8-bit "write" operation to an even address causes the data stored at this location to be temporarily
1-465
inter
PC586E
transferred to a latch. When the subsequent 8-bit
"write" operation is made (corresponding to the odd
address), the two 8-bit bytes are combined 'into a
16-bit word which is then transferred to the Static
RAM.
In order to take' advantage of this scheme, all ac·
cess to the Static RAM must be made on a 16-bit
word basis to even addresses. Since the 82586 data
structures are naturally designed to be 16-bits wide,
this requirement has little or no impact on software.
The bus interface of systems with 8-bit data buses
will automatically break 16-bit operations in~ two
8-bit operations. The same software can thus be
used for both 8-bitand 16-bit systems.
The Word Assembly/Disassembly function is only
used for access to the Static RAM. All accesses to
the Address PROM, Remote Boot EPROM and
Command Registers are made as 8-bit transfers
only.
REMOTE BOOT. EPROM
An optional 8192 byte EPROM may be installed for
either "Remote Boot" operation or general purpose
ROM. Upon booting the system, the Host CPU
searches 'for a 55AAh data pattern starting at ad·
dress C8000h. If the pattern is not found, additional
attempts will be made at subsequent addresses in
2 Kbyte increments. If the pattern is found, the Host
will then search for a jump instruction and a Cyclic
Redundancy Check (CRG). If these are found, the
CPU will begin executing the code at the location
specified by the jump instruction. In order to take
advantage of the 'IRemote Boot" option, the soft·
ware on the EPROM must be able to configure the
PC586E and copy the operating system through the
network. This ability removes the need for disk
drives. The EPROM may be used for general pur·
pose storage instead of remote booting. In either
case, only 8-bit "read" operations are permitted
from this device.
ETHERNET/CHEAPERNET
SELECTION
The PC586E Board is jumper·selectable to operate
in either Ethernet (IEEE 802.3 10BASE5) or Cheap·
ernet (IEEE 802.3 10BASE2) mode.
ETHERNET
In Ethernet mode, the 82586 LAN Coprocessor is
used in conjunction with the Intel 82C501 Ethernet
Serial Interface. Functions of the 82C501 include
Manchester· er:icoding/decoding of transmit and receive data, generation of the transmit and' receive,
clock and interface to the AUI/Transceiver cable. In
addition, the 82C501 has a built in watchdog timer,
internal loopback diagnostics and collision detection
circuitry. The 82586/82C501 thus provide the com·
plete transceiver cable interface required by IEEE
802.3.
CHEAPERNET
In Cheapernet mode, the Ethernet Transceiver is 10cated on·board. The transceiver works in conjunc·
tion with the 82586 and 82C501 to provide ,the com·
plete, on·board, coaxial cable interface.
COMPONENT DESCRIPTION
82586 LAN Coprocessor
- Implements a Complete CSMAlCD Data Link
- Incorporates all Logic for Executing Time Critical
Functions Independently 6f Host System
- High·Level Command Interface Simplifies Soft·
ware Programming
- Supporting Industry CSMAlCDLAN Standards
Ethernet (IEEE 802.3 10BASE5)
Cheapernet (IEEE 802.3 10BASE2)
- Provides On·Chip Memory Management with Au·
tomatic Buffer Chaining and Reclaiming
- Interfaces to Industry Standard 8-Bit and 16-Bit
Microprocessors
- Powerful System Interface
On·Chip DMA Control Allows Up to
5 Mbytes/Sec Bus Capacity
8-Bit or 16-Bit Data Bus
. Back·to·Back Frame Reception at 10 Mb/s
- Built·ln Network Management and DiagnQstics
Transmission/Reception Error Reporting
Network Activity and Error Statistics
Station, Diagnostics (External Loopback)
Self Test Diagnostics
The 82586 is an intelligent peripheral that complete·
Iy manages the processes of transmitting and
receiving frames of data over the network, thus off·
loading the Host CPU of communication manage·
ment tasks. The 82586 features an on·chip DMA
controller which allows it to'access the local memory
though an effic~nt buffer chaining mechanism. qth·
er features, of the 82~86 are the ability to Perform
network management activiti~s including error and
collision tallies lind diagnostic capabiliti~s via,the in·
ternal and external loopback function. Control ,of the
82586 is through high level commands such as
TRA~SMIT and CONFIG!JRE. ,
1-466
intJ
PC586E
All information passed between the 82586 and the
Host board is made through shared local memory.
The Host may load the memory with a command
and prompt the 82586 to execute. While receiving a
packet, the 82586 loads receive buffers in local
memory and, after completing the reception, interrupts the Host board to indicate that a packet has
been received.
-
-
Direct Interface to the 82586 LAN Coprocessor
and Ethernet Transceiver
Conforms to IEEE 802.3 10BASE5 (Ethernet)
and IEEE 802.3 10BASE2 (Cheapernet) Specifications
10 Mb/s Serial Data Rate
Manchester Encoding/Decoding and Receive
Clock Recovery
10 MHz Transmit Clock Generation
Drives and Receives IEEE 802.3 AUI (Transceiver) Cable
Optional Watchdog Timer Prevents Babbling
Internal Diagnostic Loopback for Fault Detection
and Isolation
Functionally Compatible with the SEEQ 8023A
The 82C501 provides the Ethernet (IEEE 802.3
10BASE5) or Cheapernet (IEEE 802.3 10BASE2)
Serial Interface for the 82586 LAN Coprocessor.
Major functions of the 82C501 include generation of
the transmit and receive clock (10 MHz for Ethernet
and Cheapernet), Manchester encoding/decoding
of transmit and receive data, and interfacing the
10BASE5 Access Unit Interface (AUI/Transceiver)
cable. In addition, the 82C501 provides for fault isolation with internal diagnostic loopback. An on-chip
watchdog timer prevents the station from locking up
in the continuous transmit mode Gabber control).
Hardware:
-
Network Software Drives
Currently Available for the
lowing Applications:
UNIX/TCP-IP
Novell/Netware
(Additional Drivers to be
nounced)
- IBM PC, PC-XT, PC-AT
Compatible Systems
DB-15 Connector (Ethernet)
BNC Connector (Cheapernet)
-
-
Intel 82586 LAN Coprocessor
Intel 82C501 Ethernet Serial
Interface
Static RAM
16 Kbytes
General Address
PROM
32 bytes
8 Kbytes
Bootable EPROM
-
1.0COOOOh-OC7FFFh
2.0C8000h-OCFFFFh
3.0DOOOOh-OD7FFFh
4.0D8000h-ODFFFFh
5. FOOOOOh-F3FFFFh
6. F40000h-F7FFFFh
7.F80000h-FBFFFFh
8. FCOOOOh-FFFFFFh
Board Master Clock
24 MHz
82586-6
6 MHz
Memory Address
Ranges:
Frequency:
8-Bit PC Bus
Frequency (Max.): -
4.77 MHz
are
Fol-
oAdditional
Wait-States
-8MHz
16-Bit AT Bus
Frequency (Max.): -
>8MHz
8 MHz
o Additional
Wait-States
Not Supported
o Additional
Wait-States
-10 MHz
o Additional
Wait-States
1 Additional
Wait-States
>12 MHz
Not Supported
+ 5V Input ± 5%
+12V Input ±5%
-12 MHz
Voltage Limits:
-
Current
Requirements:
PC586E Specifications*
Software:
System
Components:
-
Memory Capacity: -
82C501 ETHERNET SERIAL
INTERFACE
-
Cable
Connections:
- + 5V Input
- +12V Input
Power Dissipation:- Maximum
Temperature
Range:
- Operating
-
Storage
3.0A"
300 rnA"
18.6W"
O·Cto + 55·C
O·Cto +70·C
An-
DIMENSIONS (Not Including Mounting Bracket)
and
Length: 8.2 in. (20.8 cm)
Height: 4.2 in. (10.7 cm)
Width: 0.7 in. (1.8 cm)
"Preliminary, subject to change
1-467
Wide Area Networks
2
8251A
PROGRAMMABLE COMMUNICATION INTERFACE
•
•
•
•
•
•
•
•
•
•
•
Synchronous and Asynchronous
Operation
Synchronous 5-8 Bit Characters;
Internal or External Character
Synchronization; Automatic Sync
Insertion
Asynchronous 5-8 Bit Characters;
Clock Rate-1, 16 or 64 Times Baud
Rate; Break Character Generation; 1,
1Yz, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect and
Handling
Synchronous Baud Rate-DC to 64K
Baud
Asynchronous Baud Rate-DC to 19.2K
Baud
Full-Duplex, Double-Buffered
Transmitter and Receiver
Error Detection-Parity, Overrun and
Framing
Compatible with an Extended Range of
Intel Microprocessors
28-Pin DIP Package
All Inputs and Outputs are TTL
Compatible
Available In EXPRESS and Military
Versions
The Intel® 8251A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter
(USART), designed for data communications with Intel's microprocessor families such as MCS-48, 80, 85, and
iAPX-86, 88. The 8251A is used as a peripheral device and is programmed by the CPU to operate using
virtually any serial data transmission technique presently in use (including IBM "bi-sync"). The USART accepts
data characters from the CPU in parallel f()rmat and then converts them into a continuous serial data stream
for transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the CPU. The USART will signal the CPU whenever it can accept a new character for transmission or
whenever it has received a character for the CPU. The CPU can read the complete status of the USART at any
time. These include data transmission errors and control signals such as SYNDET, TxEMPTY. The chip is
fabricated using Intel's high performance HMOS technology.
T.D
°7-0 0
TxROY
T.E
D;
D,
D3
Dn
R.D
Vcr..
GND
A;C
D,
DTR
°5
0.
0,
hl
RxD
J'
/
INTERNAL
DATA BUS
Fbi:
RESET
ClK
WR
T,O
CS
c/o
AD
hEMPTY
RxROY
R"ROY
RTS
OSR
CTS
SVNDEt/BD
TxRDY
205222-2
Figure 2. Pin Configuration
__ SYNDET
205222-1
Figure 1. Block Diagram
2-1
November 1986
Order Number: 205222-002
inter
8251A
FEATURES AND ENHANCEMENTS
i=UNCTIONALDESCRIPTION
The 8251A is an advanced design of the industry
standard USART, the Intel® 8251. The 8251A operates with an extended range of Intel microprocessors and maintains compatibility with the 8251. Familiarization time is minimal because of compatibility
and involves only knowing the additional features
and enhancements, and reviewing the AC and DC
specifications of the 8251 A.
General
The 8251A is a Universal Synchronous! Asynchronous ReceiverITransmitter designed for a wide
range of Intel microcomputers such as 8048, 8080,
8085, 8086 and 8088. Like otherl!O devices in a
microcomputer system, its functional configuration is
programmed by the system's software for maximum
flexibility. The. 8251A can support most serial data
techniques in use, including IBM "bi-sync".
The 8251A incorporates all the key features of the
8251 and has the following additional features and
enhancements:
In a communication environment an interface device
must convert parallel format system data into serial
format for transmission and convert incoming serial
format data into parallel system data for reception.
The interface device must also delete or insert bits
or characters that are functionally unique to the
communication technique. In essence, the interface
should appear "transparent" to the CPU, a simple
input or output of byte-oriented system data.
• 8251A has double-buffered data paths with separate I!O registers for control, status, Data In, and
Data Out, which considerably simplifies control
programming and minimizes CPU overhead.
• In asynchronous operations, the Receiver detects and handles "break" automatically, relieving the CPU of this task.
• A refined Rx initialization prevents the Receiver
from starting when in "break" state, preventing
unwanted interrupts from a disconnected
USART.
Data Bus Buffer
• At the conclusion of a transmission, TxD line will
always return to the marking state unless SBRI<
is programmed.
This3-state bidirectional, 8-bit buffer is used to interface the 8251A to the system Data Bus. Data is
transmitted or received by the buffer upon execution
of INput or OUTput instructions of the CPU. Control
words, Command words and Status information are
also transferred through the Data Bus Buffer. The
Command Status, Data-In and Data-Out registers
are separate, 8-bit registers communicating with the
system bus through the Data Bus Buffer.
• Tx Enable logic enhancement prevents a Tx Disable command from halting transmission until all
data previously written has been transmitted. The
logic also prevents the transmitter from turning
off in the middle of a word.
• When
ternal
Sync
which
External Sync Detect is programmed, InSync Detect is disabled, and an External
Detect status is provided via a flip-flop
clears itself upon a status read.
This functional block accepts inputs from the system
Control bus and generates control signals for overall
device operation. It contains the Control Word Register and Command Word Register that store the
various control formats for the device functional definition.
• Possibility of false sync detect is minimized by
ensuring that if double character sync is programmed, the characters be contiguously detected and also by clearing the Rx register to all ones
whenever Enter Hunt command is issued in Sync
mode.
RESET (Reset)
• As long as the 8251A is not selected, the RD and
WR do not affect the internal operation of the
device.
A "high" on this input forces the 8251A into an
"Idle" mode. The device will remain at "Idle" until a
new set of control words is written into the 8251A to
program its functional definition. Minimum RESET
pulse width is 6 tCY (clock must be running).
• The 8251 A Status can be read at any time but the
status update will be inhibited during status read.
• The 8251A is free from extraneous glitches and
has enhanced AC and DC characteristics, providing higher speed and better operating margins.
A command reset operation also puts the device
into the "Idle" state.
• Synchronous Baud rate from DC to 64K.
2-2
intJ
8251A
0,
/
INTERNAL
DATA BUS
205222-3
Figure 3. 8251A Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions
ClK (Clock)
C/O RD WR CS
The ClK input is used to generate internal device
timing and is normally connected to the Phase 2
(TTL) output of the Clock Generator. No external inputs or outputs are referenced to ClK but the frequency of ClK must be greater than 30 times the
Receiver or Transmitter data bit rates.
0
0
1
1
X
X
WR (Write)
0
1
0
1
1
1
0
1
0
1
X
X
0
0
0
0
0
1
8251A DATA --+ DATA BUS
DATA BUS --+ 8251A DATA
STATUS --+ DATA BUS
DATA BUS --+ CONTROL
DATA BUS --+ 3-STATE
DATA BUS --+ 3-STATE
C/o (Control/Data)
A "low" on this input informs. the 8251A that the
CPU is writing data or control words to the 8251A.
This input, in conjunction with the WR and RD inputs, informs the 8251A that the word on the Data
Bus is either a data character, control word or status
information.
RD(Read)
1 = CONTROL/STATUS; 0 = DATA.
A "low" on this input informs the 8251A that the
CPU is reading data or status information from the
8251 A.
2-3
inter
8251A
CS (Chip Select)
Transmitter Buffer
A "low" on this input selects the 8251A. No reading
or writ!.':![ will occur unless the device is selected.
Whei!...9S is !:!!g!l, the Data Bus is in the float state
and RD and WR have no effect on the chip.
The Transmitter Buffer accepts parallel data from
the Data Bus Buffer, converts it to a serial bit stream,
inserts the appropriate characters or bits (based on
the communication technique) and outputs a composite serial stream of data on the TxD output pin on
the falling edge of TxC. The transmitter will begin
transmission upon being enabled if CTS = o. The
TxD line will be held in the marking state immediately upon a master Reset or when Tx Enable or CTS is
off or the transmitter is empty.
Modem Control
The 8251A has a set of control inputs and outputs
that can be used to simplify the interface to almost
any modem. The modem control signals are general
purpose in nature and can be used for functions other than modem control, if necessary.
Transmitter Control
The Transmitter Control manages all activities associated with the transmission of serial data. It accepts
and issues signals both externally and internally to
accomplish this function.
DSR (Data Set Ready)
The DSR input signal is a general-purpose, 1-bit inverting input port. Its condition can be tested by the
CPU using a Status Read operation. The DSR input
is normally used to test modem conditions such as
Data Set Ready.
TxRDY
(Transmitt~r
Ready)
This output signals the CPU that the transmitter is
ready to accept a data character. The TxRDY output
pin can be used as an interrupt to the system, since
it is masked by TxEnable; or, for Polled operation,
the CPU can check TxRDY using a Status Read operation. TxRDY is automatically reset by the leading
edge of WR when a data character is loaded from
the CPU.
DTR (Data Terminal Ready)
The DTR output signal is a general-purpose, 1-bit
inverting output port. It can be set "low" by programming the appropriate bit in the Command Instruction
word. The DTR output signal is normally used for
modem control such as Data Terminal Ready.
Note that when using the Polled operation, the
TxRDY status bit is not masked by TxEnable, but will
only indicate the Empty/Full Status of the Tx Data
Input Register.
RTS (Request to Send)
The RTS output signal is a general-purpose, 1-bit
inverting output port. It can be set "low" by programming the appropriate bit in the Command Instruction
word. The RTS output signal is normally used for
modem control such as Request to Send.
TxE (Transmitter Empty)
When the 8251A has no characters to send, the
TxEMPTY output will go "high". It resets upOn receiving a character from CPU if the transmitter is
enabled. TxEMPTY remains high when the transmitter is disabled. TxEMPTY can be used to indicate
the end of a transmission mode, so that the CPU
"knows" when to "turn the line around" in the halfduplex operational mode.
CTS (Clear to Send)
A "low" on this input enables the 8251 A to transmit
serial data if the Tx Enable bit in the Command byte
is set to a "one". If either a Tx Enable off or CTS off
condition occurs while the Tx is in operation, the Tx
will transmit all the data in the USART, written prior
to Tx Disable command before shutting down.
In the Synchronous mode, a "high" on this output
indicates that a character has not been loaded and
the SYNC character or characters are about to be or
are being transmitted automatically as "fillers". Tx
EMPTY does not go low when the SYNC characters
are being shifted out.
2-4
inter
8251A
RESET _ _
CL~ _ _ READ/WRITE
T.Roy
C/O_
RD_
TxEMPTY
CONTROL
LOGIC
f.c
WR
C5 _ _ _---'
R.o
/
INTERNAL
DATA BUS
_SYNDET/
BRKDET
205222-4
Figure 4. 8251A Block Diagram Showing Modem and Transmitter Buffer and Control Functions
TxC (Transmitter Clock)
Receiver Control
The Transmitter Clock controls the rate at which the
character is to be transmitted. In the Synchronous
transmission mode, the Baud Rate (1x) is equal to
the TxC frequency. In Asynchronous transmission
mode, the baud rate is a fraction of the actual TxC
frequency. A portion of the mode instruction selects
this factor; it can be 1, Y'6 or %4 the TxC.
This functional block manages all receiver-related
activities which consists of the following features.
The RxD initialization circuit prevents the 8251A
from mistaking an unused input line for an active low
data line in the "break condition". Before starting to
receive serial characters on the RxD line, a valid "1"
must first be detected after a chip master Reset.
Once this has been determined, a search for a valid
low (Start bit) is enabled. This feature is only active
in the asynchronous mode, and is only done once
for each master Reset.
For Example:
If Baud Rate equals 110 Baud,
TxC equals 110Hz in the 1x mode.
TxC equals 1.72 kHz in the 16x mode.
TxC equals 7.04 kHz in the 64x mode.
The falling edge of TxC shifts the serial data out of
the 8251 A.
The False Start bit detection circuit prevents false
starts due to a transient noise spike by first detecting
the falling edge and then strobing the normal center
of the Start bit (RxD = low).
Receiver Buffer
Parity error detection sets the corresponding status
bit.
The Receiver accepts serial data, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique
and sends an "assembled" character to the CPU.
Serial data is input to RxD pin, and is clocked in on
the rising edge of RxC.
The Framing Error status bit is set if the Stop bit is
absent at the end of the data byte (asynchronous
mode).
2-5
inter
8251A
when the internal transfer is occurring, overrun error
will be set and the old character will be lost.
RxRDY (Receiver Ready)
This output indicates that the 8251A contains a
character that is ready to be input to the CPU.
RxRDY can be connected to the interrupt structure
of the CPU or, for polled operation, the CPU can
check the condition of RxRDY using a Status Read
operation.
RxC (Receiver Clock)
The Receiver Clock controls the rate at which the
character is to be received. In Synchronous Mode,
the Baud Rate (1x) is equal to the actual frequency
of RxC. In Asynchronous Mode, the Baud Rate is a
fraction of the actual RxC frequency. A portion of the
mode instruction selects this factor: 1, 1,1,6 or %4 the
RxC.
RxEnable, when off, holds RxRDY in the Reset Condition. For Asynchronous mode, to set RxRDY, the
Receiver must be enabled to sense a Start Bit and a
complete character must be assembled and transferred to the Data Output Register. For Synchronous
mode, to set RxRDY, the Receiver must be enabled
and a character must finish assembly and be transferred to the Data Output Register.
For Example:
Baud Rate equals 300 Baud, if
RxC equals 300 Hz in the 1x mode;
RxC equals 4800 Hz in the 16x mode;
RxC equals 19.2 kHz in the 64x mode.
Failure to read the received charaoter from the Rx
Data Output Register prior to the assembly of the
next Rx Data character will set overrun condition error and the previous character will be written over
and lost. If the Rx Data is being read by the CPU
Baud Rate equals 2400 Baud, if
RxC equals 2400 Hz in the 1x mode;
RxC equals 38.4 kHz in the 16 mode;
RiC equals 153.6 kHz in the 64 mode.
TRANSMIT
BUFFER
TKO
(P ·S)
TxRDY
TxEMPTV
rxc
205222-5
Figure 5. 8251A Block Diagram Showing Receiver Buffer and Control Functions
2-6
inter
8251A
Data is sampled into the 8251A on the rising edge of
RxC.
character in the Receive mode. If the 8251A is programmed to use double Sync characters (bi-sync),
then SYNDET will go "high" in the middle of the last
bit of the second Sync character. SYNDET is automatically reset upon a Status Read operation.
NOTE:
In most communication systems, the 8251A will be
handling both the transmission and reception operations of a· single link. Consequently, the Receive
and Transmit Baud Rates will be the same. Both
TxC and RxC will require identical frequencies for
this operation and can be tied together and connected to a Single frequency source (Baud Rate
Generator) to simplify the interface.
When used as an input (ex1ernal SYNC detect
mode), a positive going signal will cause the 8251A
to start assemblin~ata characters on the rising
edge of the nex1 AXe. Once in SYNC, the "high"
input signal can be removed. When External SYNC
Detect is programmed, Internal SYNC Detect is disabled.
SYNDET (SYNC Detect!
BRKDET Break Detect)
BREAK (Async Mode Only)
This pin is used in Synchronous Mode for SYNDET
and may be used as either input or output, programmable through the Control Word. It is reset to output
mode low upon RESET. When used as an output
(internal Sync mode), the SYNDET pin will go "high"
to indicate that the 8251A has located the SYNC
This output will go high whenever the receiver remains low through two consecutive stop bit sequences (including the start bits, data bits, and parity
bits). Break Detect may also be read as a Status bit.
It is reset only upon a master chip Reset or Rx Data
returning to a "one" state.
'l
\
ADDRESS BUS
Ao
\
\
CONTROL BUS
1/0 R
\
1/0 W RESET
<'2
(TTL)
\
DATA BUS
/').
8
V
C/O
CS
0 7-00
RD
WR
RESET
ClK
B251A
205222-6
Figure 6. 8251A Interface to 8080 Standard System Bus
2-7
inter
8251A
DETAILED OPERATION DESCRIPTION
Programming the 8251A
Prior to starting data transmission or reception, the
8251A must be loaded with a set of control words
generated by the CPU. These control Signals define
the complete functional definition of the 8251A and
must immediately follow a Reset operation (internal
or external).
General
The complete functional definition of the 8251A is
programmed by the system's software. A set of control words must be sent out by the CPU to initialize
the 8251A to support the desired communications
format. These control words will program the: BAUD
RATE, CHARACTER LENGTH, NUMBER OF STOP
BITS, SYNCHRONOUS or ASYNCHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc. In the
Synchronous Mode, options are also provided to select either internal or external character synchronization.
The control words are split into two formats:
1. Mode Instruction
2. Command Instruction
Mode Instruction
Once programmed, the 8251A is ready to perform its
communication functions. The TxRDY output is
raised "high" to signal the CPU that the 8251A is
ready to receive a data character from the CPU. This
output (TxRDY) is reset automatically when the CPU
writes a character into the 8251A. On the other
hand, the 8251A receives serial data from the MODEM or I/O device. Upon receiving an entire character, the RxRDY output is raised "high" to signal the
CPU that the 8251A has a complete character ready
for the CPU to fetch. RxRDY is reset automatically
upon the CPU data read operation.
This instruction defines the general operational
characteristics of the 8251A. It must follow a Reset
operation (internal or external). Once the Mode Instruction has been written into the 8251A by the
CPU, SYNC characters or Command Instructions
may be written.
The 8251A cannot begin transmission until the Tx
Enable (Transmitter Enable) bit is set in the Command Instruction and it has received a Clear To
Send (CTS) input. The TxD output will be held in the
marking state upon Reset.
Both the Mode and Command Instructions must
conform to a specified sequence for proper device
operation (see Figure 7). The Mode Instruction must
be written immediately following a Reset operation,
prior to using the 8251A for data communication.
C/O'1
MODE INSTRUCTION
C/O, 1
SYNC CHARACTER 1
ciB '
SYNC CHARACTER 2
}
1
C/o' 1
COMMAND INSTRUCTION
C/O, 0
DATA
cii5
=
1
ci5,
0
cii5,
1
Command Instruction
This instruction defines a word that is used to control
the actual operation of the 8251A.
All control words written into the 8251A after the
Mode Instruction will load the Command Instruction.
Command Instructions can be written into the 8251 A
at any time in the data block during the operation of
the 8251A. To return to the Mode Instruction format,
the master Reset bit in the Command Instruction
word can be set to initiate an internal Reset operation which automatically places the 8251A back into
the Mode Instruction format. Command Instructions
must follow the Mode Instruction or Sync characters.
SYNC MODE
ONLY'
COMMAND INSTRUCTION
L
Mode Instruction Definition
DATA
1
The 8251A can be used for either Asynchronous or
Synchronous data communication. To understand
how the Mode Instruction defines the functional operation of the 8251A, the designer can best view the
device as two separate components, one Asynchronous and the other Synchronous, sharing the same
package. The format definition can be changed only
after a master chip Reset. For explanation purposes
the two formats will be isolated.
t-CO-M-M-AN-D-I~-IST-R-UC-T-IO-N-;
205222-7
'The second sync character is skipped if mode instruction has
programmed the 8251 A to single character sync mode. Both
sync characters are skipped if mode instruction has programmed
the 8251 A to async mode.
Figure 7. Typical Data Block
2-8
inter
8251A
NOTE:
When parity is enabled it is not considered as one
of the data. bits for the purpose of programming
word length. The actual parity bit received on the
Rx Data line cannot be read on the Data Bus. In
the case of a programmed character length of less
than 8 bits, the least significant Data Bus bits will
hold the data; unused bits are "don't care" when
writing data to the 8251A, and will be "zeros" when
reading the data from the 8251A.
When no data characters have been loaded into the
8251A the TxD output remains "high" (marking) unless a Break (continuously low) has been programmed.
Asynchronous Mode (Receive)
The RxD line is normally high. A falling edge on this
line triggers the beginning of a START bit. The validity of this START bit is checked by again strobing this
bit at its nominal center (16X or 64X mode only). If a
low is detected again, it is a valid START bit, and the
bit counter will start counting. The bit counter thus
locates the center of the data bits, the parity bit (if it
exists) and the stop bits. If parity error occurs, the
parity error flag is set. Data and parity bits are sampled on the RxD pin with the rising edge of the RxC.
If a low level is detected as the STOP bit the Framing Error flag will be set. The STOP bit signals the
end of a character. Note that the receiver requires
only one stop bit, regardless of the number of stop
bits programmed. This character is then loaded into
the parallel 110 buffer of the 8251A. The RxRDY pin
is raised to signal the CPU that a character is ready
to be fetched. If a previous character has not been
fetched by the CPU, the present character replaces
it in the 1/0 buffer, and the OVERRUN Error flag
Asynchronous Mode (Transmission)
Whenever a data character is sent by the CPU the
8251A automatically adds a Start bit (low level) followed by the data bits (least significant bit first), and
the programmed number of Stop bits to each character. Also, an even or odd Parity bit is inserted prior
to the Stop bit(s), as defined by the Mode Instruction. The character is then transmitted as a serial
data stream on the TxD output. The serial data is
shifted out on the falling edge of IxC at a rate equal
to 1, 1116, or 1164 that of the TxC, as defined by the
Mode Instruction. BREAK characters can be continuously sent to the TxD if cpmmanded to do so.
I I I I I
52
S,
EP
PEN
L21 L,
I
821 8,
I
L
8AUO RATE FACTOR
1
0
0
1
0
0
1
1
SYNC
MODE
(lX)
(16X)
(64X)
CHARACTER LENGTH
0
1
0
0
1
1
5
81TS
6
7
8
BITS
0
81TS
1
BITS
PARITY ENABLE
1 = ENABLE
0= DISA8LE
EVEN PARITY GENERATION/CHE CK
0=000
1 = EVEN
NUMBER OF STOP BITS
0
1
0
0
0
1
1
INVALID
1
1Y2
BIT
BITS
2
1
BITS
(ONLY AFFECTS Tx; Rx
NEVER REQUIRES MORE
THAN ONE STOP BIT)
205222-8
Figure 8. Mode Instruction Format, Asynchronous Mode
2-9
8251A
Once transmission has started, the data stream at
the TxD output must continue at the TxC rate. If the
CPU does not provide the 8251A with a data character before the 8251A Transmitter Buffers become
empty, the $YNC characters (or character if in single
SYNC character mode) will be automatically inserted
in the TxD data stream. In this case, the TxEMPTY
pin is raised high to signal that the 8251A is empty
and SYNC characters are being sent out. TxEMPTY
does not go low when the SYNC is being shifted out
(see figure below). The TxEMPTY pin is internally
reset by a data character being written into the
8251A.
is raised (thus the previous character is lost). All of
the error flags can be reset by an Error Reset Instruction. The ·occurrence of any of these errors will
not affect the operation of the 8251A.
Synchronous Mode (Transmission)
The TxD output is continuously high until the CPU
sends its first character to the 8251A which usually
is a SYNC character. When the eiS line goes low,
the first character is serially transmitted out. All characters are shifted out on the falling edge of TxC.
Data is shifted out at the same rate as the TxC.
DO 01---- Ox
TxD
STJ;i
Brrs L
MARKING
DOES NOT APPEAR
Do 01 ----Ox ON THE DATA BUS
RECEIVER INPUT
RxD
GENERATED
BY 8251A
tt
t
t
L-S_T_~_~_T~ D_A_T~~BrIT_S ~
___
__
~ Brrs L
ST;;--'
____
PROGRAMMED
CHARACTER
LENGTH
TRANSMISSION FORMAT
CPU BYTE (5·8 BITS/CHAR)
DATA
C~~RACTER
ASSEMBLED SERIAL DATA OUTPUT (TxD)
DATA CHARACTER
~
_ _ _ _- L _ _ _ _
STOD
BITS
~~
RECEIVE FORMAT
SERIAL DATA INPUT (RxD)
STOt]
BITS
"'---~----""""--f
DATA CHARACTER
CPU BYTE (5·8 BITS/CHAR)'
~
I
DATA CHA~ACTER
205222-9
°NOTE:
If character length is defired as 5, 6, or 7 bits the !Jnused bits are set to "zero".
Figure 9, Asynchronous Mode
2-10
8251A
AUTOMATICALLY INSERTED BY USART
TxD
I
I \
DATA
1DATA 1SYNC 1 1SYNC 21
TxEMPTY
/
-~'"
DATA
1- - - - -
\\\\\\\\1 ~~~~~~~~ ~~UT~~IJ~:~:
NOMINAL CENTER OF LAST BIT
the USART ends the HUNT mode and is in character synchronization. The SYNDET pin is then set
high, and is reset automatically by a STATUS READ.
If parity is programmed, SYNDET will not be set until
the middle of the parity bit instead of the middle of
the last data bit.
Synchronous Mode (Receive)
In this mode, character synchronization can be internally or externally achieved. If the SYNC mode has
been programmed, ENTER HUNT command should
be included in the first command instruction word
written. Data on the RxD pin is then sampled on the
rising edge of RiC. The content of the Rx buffer is
compared at every bit boundary with the first SYNC
character until a match occurs. If the 8251A has
been programmed for two SYNC characters, the
subsequent received character is also compared;
when both SYNC characters have been detected,
I I I I I
scs
ESD
EP
PEN
L21 L1
205222-10
In the external SYNC mode, synchronization is
aChieved by applying a high level on the SYNDET
pin, thus forcing the 8251A out of the HUNT mode.
The high level can be removed after one RxC cycle.
An ENTER HUNT command has no effect in the
asynchronous mode of operation.
I I I
0
0
I
CHARACTER LENGTH
0
1
0
5
BITS
BITS
0
1
0
1
1
6
7
BITS
8
BITS
PARITY ENABLE
(1 = ENABLE)
(0 = DISA8LE)
EVEN PARITY GENERATloN/CHEe K
1 = EVEN
0=000
EXTERNAL SYNC DETECT
1 = SYNDET IS AN INPUT
SYNDer IS AN OUTPUT
o=
SINGLE CHARACT ER SYNC
1 = SINGLE SYNC CHARACTER
0= DOUBLE SYNC CHARACTER
NOTE:
In external sync mode, programming double character sync will affect only the Tx.
Figure 10. Mode Instruction Format, Synchronous Mode
2-11
205222-11
inter
8251A
Sync characters are loaded (if in Sync Mode) then
the device is ready to be used for data communication. The Command Instruction controls the actual
operation of the selected format. Functions such as:
Enable Transmit/Receive, Error Reset and Modem
Controls are provided by the Command instruction.
Parity error and overrun error are both checked in
the same way as in the Asynchronous Rx mode.
Parity is checked when not in Hunt, regardless of
whether the Receiver is enabled or not.
The CPU can command the receiver to enter the
HUNT mode if synchronization is lost. This will also
set all the used character bits in the buffer to a
"one," thus preventing a possible false SYNDET
caused by data that happens to be in the Rx Buffer
at ENTER HUNT time. Note that the SYNDET F/F is
reset at each Status Read, regardless of whether
internal or external SYNC has been· programmed.
This does not cause the 8251A to return to the
HUNT mode. When in SYNC mode, but not in
HUNT, Sync Detection is still functional, but only occurs at the "known" word boundaries. Thus, if one
Status Read indicates SYNDET and a second
Status Read also indicates SYNDET, then the programmed SYNDET characters have been received
since the previous Status Read. (If double character
sync has been programmed, then both sync characters have been contiguously received to gate a SYNDET indication). When external SYNDET mode is
selected, internal Sync Detect is disabled, and the
SYNDET F/F may be set at any bit boundary.
Once the Mode Instruction has been written into the
8251A and Sync characters inserted, of necessary,
then all further "control writes" (C/O = 1) will load a
Command Instruction. A Reset Operation (internal or
external) will return the 8251A to the Mode Instruction format.
NOTE:
Internal Res'et on Power-up:
When power is first applied, the 8251A may come up
in the Mode, Sync character or Command format. To
guarantee that the device is in the Command Instruction format before the Reset command is issued,it is safest to execute the worst-case initialization sequence (sync mode with two sync characters). Loadin9.. three OOHs consecutively into the device with C/D = 1 configures sync operation and
writes two dummy OOH sync characters. An Internal
Reset command (40H) may then be issued to return
the device to the "idle" state.
COMMAND INSTRUCTION
DEFINITION
Once the functional definition of the 8251A has
been programmed by the Mode Instruction and the
cPU BYTES (5-8 BITS/CHARI
ASSEMBLED SERIAL DATA OUTPUT (TxDI
SYNC
CHAR 1
DATACH~~~A_CT_E_R_S
SYNC
CHAR 2
____
~
RECEIVE FORMAT
SERIAL DATA INPUT (RxDI
SYNC
CHAR 1
.SYNC·
CHAR 2
I
DATACH~R:~C_T_E_R_S
____
~
CPU BYTES (5-8 BITS/CHARI
DATA
CH~RACTERS
205222-12
Figure 11. Data Format, Synchronous Mode
2-12
intJ
8251A
I I I I ISBR~l I 1
EH
IR
RTS
ER
R.E
DTR
hEN
I
TRANSMIT ENABLE
1 = enable
0- disable
DATA TERMINAL
READY
"high" will force DTR
output to zero
RECEIVE ENABLE
1 = enable
0= disable
SEND BREAK
CHARACTER
1 = forces T.D "low"
o = normal operation
ERROR RESET
1 = reset error flags
PE, OE, FE
REOUEST TO SEND
"high" will force ATS
output to lerQ
INTERNAL RESET
"high" returns 8251A to
Mode InstructIon Format
ENTER HUNT MODE'
1 = enable search for Sync
Characters
'(HAS NO EFFECT IN
ASYNCMODE)
NOTE:
205222-13
Error Reset must be performed whenever RxEnable and Enter Hunt are programmed.
Figure 12. Command Instruction Format
A normal "read" command is issued by the CPU
with C/O = 1 to accomplish this function.
STATUS READ DEFINITION
In data communication systems it is often necessary
to examine the "status" of the active device to ascertain if errors have occurred or other conditions
that require the processor's attention. The 8251A
has facilities that allow the programmer to "read"
the status of the device at any time during the functional operation. (Status update is inhibited during
status read.)
Some of the bits in the Status Read Format have
identical meanings to external output pins so that
the 8251A can be used in a completely polled or
interrupt-driven environment. TxRDY is an excep·
tion.
2-13
intJ
8251A
Note that status update can have a maximum delay of 28 clock periods from the actual event affecting the
status.
o7
l
oSR
o6
I SYNoETI
BRKDET
I
o5
o4
o·3
FE
OE
PE
I I I
,
o2
o
J
T.EMPTVI R.RoV
1
I
o'0
TxRoy
L-.
Note 1
1
SAME DEFINITIONS AS 110 PINS
PARITY ERROR
The PE lIag IS set when a parity
error IS detected It IS reset by
the E R bIt of the Command
InstructIon PE does not InhIbIt
operatIon of the 8251 A
OVERRUN ERROR
The OE lIag IS set when the CPU
does not read a character before
'--
the next one becomes available
It IS reset by the E R bIt of the
Command InstructIon OE does
not InhlbO! operatIon of the 8251 A
however. the prevlC)usly overrun
character
IS
lost
FRAMING ERROR (Async onlyl
The FE lIag IS set when a valid
Stop b,t IS not detected at the
end of every character It
IS
reset
by the E R bIt of the Command
Instruction FE does not inhibit
the operatIon of the 8251 A
..
DATA SET READY IndIcates
that the oSR IS at a zero level
205222-14
NOTE:
1. TxRDY status bit has different meanings from the TxRDY output pin. The former is not conditioned by CTS and TxEN;
the latter is conditioned by both C'I'S and TxEN.
'
i.e. TxRDY status bit = DB Buffer Empty
TxRDY pin out = DB Buffer Empty. (C'I'S = 0) • (TxEN= 1)
Figure 13. Status Read Format
2·14
intJ
8251A
APPLICATIONS OF THE 8251A
BAUD RATE
GENERATOR
lJ)
CRT
TERMINAL
205222-15
Figure 14. Asynchronous Serial Interface to CAT Terminal, Dc-9600 Baud
'--_ _ _ _---..:.;ADDRESS BUS
SYNCHRONOUS
TERMINAL
OR PERIPHERAL
DEVICe
SYNDET ~----I
2Q5222-16
Figure 15. Synchronou81nterface to Terminal or Peripheral Device
2-15
intJ
8251A
APPLICATIONS OF THE 8251A (Continued)
PHONE
LINE
INTER
FACE
TELEPHONE
LINE
205222-18
Figure 16. Asynchronous Interface to Telephone Lines
SYNC
MODEM
PHONE
LINE
INTER·
FACE
TELEPHONE
LINE
205222-17
Figure 17. Synchronous Interface to Telephone Lines
NOTES:
1. AC timings measured VOH = 2.0 VOL = 0.8, and with load circuit of Figure 18.
2. Chip Select (CS) and Command/Data (C/O) are considered as Addresses.
3. Assumes that Address is valid before RD i.
4. This recovery time is for Mode Initialization only. Write Data is allowed only when TxRDY = 1. Recovery Time between
Writes for Asynchronous Mode is 8 Icv and for Synchronous Mode is 16 Icv.
5. The TxC and RxC frequencies have the following limitations with respect to ClK: For 1x Baud Rate, fTx or fRx :s:
1/(30 Icv): For 16x and 64x Baud Rate, fTx or fRx :s: 1/(4.5 Icv).Thls applies to Baud Rates less than or equal to 64K Baud.
6. Reset Pulse Width = 6 tcv minimum; System clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
8. In external sync mode the tes spec. requires the ratio of the system clock (clock) to receive or transmit bit ratios to be
greater than 34.
9. A float is defined as the point where the data bus falls below a logic 1 (2.0V @ IOH limit) or rises above a logic 0 (O.8V @
IOL limit).
2·16,
inter
8251A
• Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress reting only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specificetion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ...... O·C to 70·C
Storage Temperature .......... - 65·C to
+ 150·C
Voltage on Any Pin
with Respect to Ground .......... - 0.5V to
+ 7V
Power Dissipation ..........•................ 1W
D.C. CHARACTERISTICS TA = O·C to 70·C, Vee = 5.0V ± 10%, GND = OV·
Symbol
Parameter
Min
Unit
Max
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
Test Conditions
0.8
V
Vee
V
0.45
V
IOL = 2.2mA
V
IOH = -400 /LA
VOL
Output Low Voltage
VOH
Output High Voltage
IOFL
Output Float Leakage
±10
/LA
VOUT = VeetoO.45V
IlL
Input Leakage
±10
/LA
VIN = Vee toO.45V
Icc
Power Supply Current
100
ma
All Outputs = High
2.4
CAPACITANCE TA = 25·C, Vee = GND = OV
Symbol
Parameter
Min
Max
Unit
pF
fc'=1MHz
pF
Unmeasured pins returned
toGND
CIN
Input Capacitance
10
ClIO
I/O CapaCitance
20
rest Conditions
A.C. CHARACTERISTICS TA = O·C to 70·C, Vee = 5.0V ± 10%, GND = OV·
Bus Parameters (Note 1)
READ CYCLE
Symbol
tAR
tRA
Max
Unit
Test Conditions
Parameter
Min
(CS, C/D)
Address Hold Time for READ (eS, C/D)
0
ns
(Note 2)
0
ns
(Note 2)
250
ns
, Address Stable Before READ
tRR
READ Pulse Width
tRO
Data Delay from READ
tOF
READ to Data Floating
10
200
ns
3,CL = 150pF
100
ns
(Note 1, 9)
WRITE CYCLE
Symbol
Parameter
Min
Max
Unit
tAW
Address Stable Before WRITE
0
ns
tWA
Address Hold Time for WRITE
0
ns
tww
WRITE Pulse Width
250
ns
tow
Data Set-Up Time for WRITE
150
!'Is
two
Data Hold Time for WRITE
20
ns
tRY
Recovery Time Between WRITES
6
icv
2-17
Test Conditions
(Note 4)
intJ
8251A
A.C. CHARACTERISTICS (Continued)
OTHER TIMINGS
Min
Max
Unit
toy
Symbol
ClOck Period
320
1350
ns
t
Clock High Pulse Width
120
tCy-90
ns
tcf>
Clock Low Pulse Width
90
tR, tF
Clock Rise and Fall Time
20
ns
tOTx
TxD Delay from Falling Edge of TxC
1
p.s
fTx
Transmitter Input Clock Frequency
1x Baud Rate
16x Baud Rate
64x Baud Rate
DC
DC
DC
64
310
615
kHz
kHz
kHz
Transmitter Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate
12
1
toy
toy
Transmitter Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
15
3
tCY
tCY
Receiver Input Clock Frequency
1x Baud Rate
16x Baud Rate
64x Baud Rate
DC
DC
DC
Receiver Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate
12
1
tor
Receiver Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
15
3
toy
toy
tTPW
tTPO
fRx
tRPW
tRPD
Parameter
tTxRDY
TxRDY Pin Delay from Center of Last Bit
tTxRDY CLEAR
TxRDY
tRxRDY
RxRDY Pin Delay from Center of Last Bit
tRxRDY CLEAR
RxRDY
tiS
Internal SYNDET Delay from Rising
Edge of AXe
tES
External SYNDET Set-Up Time After
Rising Edge of AXe
tTxEMPTY
twc
toR
J.. from Leading Edge of WR
J.. from Leading Edg~ of RD
16tCY
TxEMPTY Delay from Center of Last Bit
. Control Delay from Rising Edge of
WRITE (TxEn, DTR, RTS)
Control to 'READ Set-Up Time (DSR, CTS)
20
·NOTE:
For Extended Temperature EXPRESS, use MIL 8251A electrical parameters.
2-18
Test Conditions
(Note 5, 6)
ns
64
310
615
kHz
kHz
kHz
toy
14
toy
(Note 7)
400
ns
(Note 7)
26
toy
(Note 7)
400
ns
(Note 7)
26
tcy
(Note 7)
tRPD-tCY
ns
(Note 7)
20
tCY
8.
toy
.'
toy
(Note 7)
(Note 7)
(Note 7)
inter
8251A
A.C. CHARACTERISTICS (Continued)
TYPICAL .1 OUTPUT DELAY VS . .1 CAPACITANCE (pF)
+20
-.;
E
>
< x=
20
.
0.45
TEST POINTS
0.8
2.0
~
8251A
0.8
OUT
205222-20
AC Testing: Inputs are driven at 2.4V for a Logic "I" and 0.45V
for a Logic "0". Timing measuremenls are made at 2.0V for a
Logic "I" and 0.8V for a Logic "0".
±"
-=
C L = 150 pF
205222-21
Figure 18
WAVEFORMS
SYSTEM CLOCK INPUT
CLOCK
¢
205222-22
2-19
~
<
m
."
o:::0
TRANSMITTER CLOCK AND DATA
l
:s:::
CJ)
'0
o
TxC Ilx MODEl
::J
do
::J
c:
~116xMODEI
--1
Tx DATA
! = tOTX
----,X
tOTX-l
1=
X - .-----x==
~
205222-23
CD
~
I\)
ro
o
en
....
»
RECEIVER CLOCK AND DATA
IRx BAUD COUNTER STARTS HEREI
RxDATA
RxC (1x MODE)
RxC (16 MODE)
tNT SAMPLING
PULSE
205222-24
inter
8251A
WAVEFORMS (Continued)
WRITE DATA CYCLE (CPU hRDY
DATA IN ID.B.I
USART)
___-JI
_ ________~DO~N~.!T~C~A~R~E____~~~~~~~~----~DO~N~.!T~C~A~R~E---
CIO
205222-25
READ DATA CYCLE (CPU
~
USART)
\Lrl - - - - - - -
--------------------,r
".----lI
If-r-;~~=~v em: I
Rci
I-'RO
DATA OUT 10.B.1
--
r'OF
-----20~AT!!A~F~L:20~AT!---___t-{JO~A~T~A~O~UT~Ae~T~lv~ED....f!;OA~T~A~F:.!:L2:0A~T
em _______________~__+-___________+--~------
205222-26
2-21
intJ
8251A
WAVEFORMS (Continued)
WRITE CONTROL OR OUTPUT PORT CYCLE (CPU -
USART)
OTR,RTS -------------------~--,r------(NOTE =1) - - - - - - - - - - -_ _ _ _ _ _ _ - - A
l:::
twc :::.j
- - - - - - - -____ I-tww-I r - - - - - - - - -
~
1-' tow - - ::1 two
'it
OATAIN(OB)
1--.. .
c/o
~
1--1
tAW
tWA
1\'---_ __
- - - - -_ _ _ _~/I:f-
-------------, 1- •
tAW
-1,..:-tW.:..:,A"'--_ _ _ _ _ __
~~----~y
205222-27
READ CONTROL OR INPUT PORT (CPU -
USART)
V
OSR,CTS
(NOTE "2) _ _ _ _--.JA'--_ _ _ _....,.,-_ _ _ _ _ _ _ _ _ _ ___
-~j
1 ,--_ _ __
.......- - tRR 1)1
__
_ -_ _
tCR
_ _ _ _ _ _ _ _1_
__
Rd
~
-+I 1-
DATA OUT
(O.B.)
---lIAR - -
c/o
tRO
-
j-10F
7.
~ tRAr---
fi
_ _ _ _ _ _ _ _- J
- \ tAR -
- - tRA
1;==
------------~~~------------~y
205222-28
NOTES:
1. T wc includes the response timing of a control byte.
2. TCR includes the effect of CTS on the TxENBL circuitry,
2·22
:IE
:.<
m
."
TRANSMITTER CONTROL AND FLAG TIMING (ASYNC MODE)
rn
'T.EMPTV
I~en
----t'=-----1
Tx EMPTY
l
t'
Tx READY
(STATUS BIT)
T'R~:'~
g.c
jJ
CD
.s
C/O
WrSBRK
w.
TxDATA
--------------~~[(IXXX)J~~~OC((((~\1)JJOJODG
DATA CHAR 1
DATA CHAR 2
'Oo~NC"l"u).
DATA CHAR 3
~ DATACHAR4
_00-
lDiD
Example Fonnat = 7 Bit Character With Parity & 2 Stop Bits.
~~
Cc
1;;0
-
:e
..
205222-29
~
...:.en~
RECEIVER CONTROL AND FLAG TIMING (ASYNC MODE)
~
BRfAKDlTH.f
f H.".'IIN(, fRAU,",
'ifA1U\d,l
-
UVERRUN ERROR
tSlATUSBlT1
All ROY
~
CHAR 2
~lR.ROY
LOST
I
cD
,..---.
RdOAlA
----i'Rd'"
W,EHR
~
Au
V
I
1
L--
~~
V
V
~
/
Illll
i~
BREAK
1
R.En
e .. Rn
.~
".
:;;0
~~
Example Format = 7 Bit Character W,th Parity & 2 Stop Bits
205222-30
! (
TRANSMITTER CONTROL AND FLAG TIMING (SYNC MODE)
m
."
o::II
s:::
en
'§
~
:::l
1
~
ciS
r1\
TIl EMPTY
r. READY
(STATUS BITI
I\)
~
h
READY
(PIN)
CD
W-tLtr-- V- tL\
{\
WI' OATA
Wi
MARKING STATE
hOATA
I
r-
f
J
~'+
I'---
i,--
~
....en
W,COMMAND
:.
saRK
I
~
CHAR 1
I
1\
Wr DATA
DATA
CHARl
I
\
Wr OATA
WrOATA
CHAR 3
C~tR'
~
SYNC
CHAR 1
~~
tHAR:I .
SYP«: CHAR 2
Wt'~OMMA'::!
\\
SBRK
DATA~
CHAR 4
I
W. DATA
CHAR 5
MA~:it~
DATA
CHAR!.
L-.'/
'I-I'N'
STATE
...
"oX-X'N' ,..,..~'H'H'J'A. ·HI,I·IIoI-I,I>I·l·I-I>I,I·
......
...."].1-1,1>1·1,....I
Example Fonnat = 5 Bit Character With Parity. 2 Sync Characters.
STATE
STATE
Sv~C
CHAR
...
lIC
...
.Y-I,Y,Y·Y 1.Y205222-31
~
RECEIVER CONTROL AND FLAG TIMING (SYNC MODE)
<
m
'TI
(
o:0
3:
en
'§
SYJ\lOf r
{PINI NOH
1
J
'IS_ li-
SVNOE TIS 81
3-
rr~DTE~
~\
tES_
I,
~\
~
5'
c:
~
r
~
OVERRUN
ERROR IS BI
J
JOATA CHAH 2 1\
lOST
r~
RI{ ROY {PINt
Rd STATUS
I\)
r\,
CD
(11
w,
EH
R.En
IIRd DATAJ
\
\
", ~
r~r-
j
Rd$TATUS
W, EHo
L
Rd STATUS
r-
1\
Rd DATA
CHAR 1
SYNC
SYNC
CHAR'
CHAR 2
DATA
CHAR 1
\l[J V
CHAR 2
DATA
CHAR 3
\~YNC
CHAR 1
\1.J ~IJ
SVNCCHAR 2
DATA
DATA
CHAR 1
OON'TCARE
LV
CHAR 2
ETC
~, ~'.moX'X'H,moX'X'H'moX'X'A>X~~H~N'H'X'I~XoX'N'H~X-X"kl"l"l·X' • Tl'l'A.'HX'X' , 'Nll XXX XX
I rTTTTTT1TTT1
TTTTT1}'~rTJ1TTTTT
~
CHAR ASSY
W
BEGINS
RII ClOC-1<
LEXIT HUNT MODE
SET SYNC DET
EXIT HUNT MODE
SET SVN DET ISTATUSBITJ
1
lIlf .M
SET SYNDET (STATUS BIT I
205222-32
NOTES:
1. Internal Sync, 2 Sync Characters, 5 Bits With Parity.
2. External Sync, 5 Bits, With Parity,
C»
...
N
01
):0
'--
Rri
R. DATA
~dSYN!
y;JR"
RdDATA
CHAR 1
CHAR 1
DON T
CARE
r-'k
~\
i
82050
ASYNCHRONOUS COMMUNICATIONS CONTROLLER
•
•
•
•
•
Asynchronous Operation
- 5-to-8-Bit Character Format
- Odd, Even or No Parity Generation
and Detection
- Baud Rate DC to 56K
Programmable, 16-Blt Baud Rate
Generator
System Clock
- On-chip Crystal Oscillator
- Externally Generated Clock
28-Lead DIP and PLCC Packages
IBM PC (INS 16450/8250A) Software
Compatible
•
Seven 1/0 Pins
- Dedicated Modem 1/0
- General Purpose 1/0
•
•
•
•
•
NO TTL Interface to Most Intel
Processors
Internal Diagnostics with Local
Loopb~ck
Complete Interrupt and Status
Reporting
CHMOS III Technology Provides
Increased Reliability and Reduced
Power Consumption
Line Break Generation and Detection
The Intel CHMOS 82050 Asynchronous Communications Controller is a low cost, higher performance alternative to the INS 16450-it emulates the INS 16450 and provides 100% compatibility with IBM PC software. Its
28-lead package provides all the functionality necessary for an IBM PC environment while substantially decreasing board space. The 82050's simpler system interface reduces TTL glue-especially for higher frequency PC bus designs. The 82050 is specifically designed to provide a low cost, high-performance integrated
modem solution when combined with Intel's 89024 modem chip set. The compact 28-pin 82050 is fabricated
using CHMOS III technology for decreased power consumption and increased reliability.
vee
vss
TxD
A(2-0)
0(7-0)
RxD
INT
RESET
RD
BUS
INTERFACE
UNIT
16X
RxC
16X
TxC
WR
CS
OUT2
Ri
MODEM
CLKXl
X2
I/o
DSR
DCD
DTR
RTS
CTS
290137-1
Figure 1. Block Diagram
2-26
September 1987
Order Number: 290137-002
inter
82050
iii
Rii
04
05
06
07
·INT
TXO
VSS
OUT2/X2
ClK/Xl
OSR
WR
iii
WR
OSR
OCO
RXO
CTS
cs
INT
TXO
VSS
OUT2/X2
ClK/Xl
00
A2
Al
AO
VCC
290137-2
03
02
01
00
A2
Al
AO
VCC
Rii
RESET
RTS
OTR
290137-3
Figure 2. PLCC Pinout
Figure 3. DIP Pinout
82050 PINOUT DEFINITION
Pin
No.
Type
RESET
17
I
RESET: A high on this input pin resets the 82050.
CS
18
I
CHIP SELECT: A low on this input pin enabLes the 82050 and allows
read or write operations.
A2-AO
24-22
I
ADDRESS PINS: These inputs interface with three bits of the system
address bus to select one of the internal registers for read or write.
07-00
1-4
25-28
1/0
RO
20
I
READ: A low on this input pin allows the CPU to read. data or status
bytes from the 82050.
WR
19
I
WRITE: A low on this input allows the CPU to write data or control
bytes to the 82050.
INT
5
0
INTERRUPT: A high on this output pin signals an interrupt request to
the CPU. The CPU may determine the particular source and cause of
the interrupt by reading the 82050 status registers.
ClK/X1
9
I
MULTIFUNCTION: This input pin serves as a source for the internal
system clock. The clock may be asynchronous to the serial clocks and
to the processor clock. This pin may be used in one of two modes:
ClK-in this mode an externally generated clock should be used to
drive this input pin; X 1-in this mode the clock is generated by a crystal
to be connected between this pin (X1) and the X2 pin. (See system
clock generation.)
OUT2/X2
8
0
MULTIFUNCTION: This is a dual-function pin which may be configured
to one of the following functions: OUT2-a general purpose output pin
controlled by the CPU is only available when the ClK/X1 pin is driven
by an externally generated clock; X2-this pin serves as an output pin
for the crystal oscillator. Note: The configuration of pin is done during
hardware reset. For more details refer to the system clock generation.
Symbol
Name and Description
DATA BUS: Bi·directional, three state, 8-Bit Data Bus. These pins
allow transfer of bytes between the CPU and the 82050.
2-27
inter
82050
82050 PINOUT DEFINITION (Continued)
Pin
No.
Type
Name and Description
TXD
6
0
TRANSMIT DATA: Serial data is transmitted via this output pin starting
at the least significant bit.
AXD
13
I
RECEIVE DATA: Serial data is received on this input pin starting at the
least significant bit.
AI
10
I
RING INDICATION: AI- Aing indicator-input, active low. This is a
general purpose input accessible by the CPU.
DTA
15
0
DTR-DATA TERMINAL READY: Output, active low. This isa general
purpose output pin controlled by the CPU. During hardware reset, this
pin is an input used to determine the system clock mode. (See System
Clock Generation.)
DSA
11
1/0
DSR-DATA SET READY: Input, active low. This is a general purpose
input pin accessible by the CPU.
ATS
16
0
RTS-REQUEST TO SEND: Output, active low. This is a general
purpose output pin controlled by the CPU. During hardware reset, this
pin is an input used to determine the system clock mode. (See system
clock generation)
CTS
14
I
CLEAR TO SEND: Input active low. This is a general purpose input pin
accessible by the CPU.
DCD
12
I/O
VCC
21
P
VCC: Device power supply.
VSS
7
P
VSS: Ground.
Symbol
DCD-DATA CARRIER DETECTED: Input, active low. This is a
general purpose input pin accessible by the CPU.
CRYSTAL OSCILLATOR
SYSTEM INTERFACE
The 82050 has a simple demultiplexed bus interface
which consists of a bidirectional, three-state, 8-bit
data bus and a 3-bit address bus. The Aeset, Chip
Select, Aead, and Write pins, along with the Interrupt
pin, provide the remaining signals necessary to interface to the CPU. The 82050's system clock can be
generated externally and provided through the ClK
pin; or its on-chip crystal oscillator can be used by
attaching a crystal to the X1 and X2 pins. For compatibility with IBM PC software, a system clock of
18.432 MHz (with divide by two enabled) is recommended. The 82050, along with a transceiver, address decoder, and a crystal, complete the interface
to the IBM PC Bus.
~rrfi
DrLLJ
290137-4
Parallel Resonant Crystal Freq. Max = 18.432 MHz
(Divided by 2)
Figure 4. Crystal Oscillator
X2 pins. The oscillator frequency is divided by two
before being inputted into the chip circuitry. If an
18.432 MHz crystal is used, then the actual system
clock frequency of the 82050 will be 9.216 MHz.
This mode is configured via a strapping option on
the ATS pin.
SYSTEM CLOCK OPTIONS
It is very important to distinguish between the clock
frequency being supplied into the 82050 and the
system clock frequency. The term system clock refers to the clock frequency being supplied to the
82050 circuitry (divided or undivided). The following
examples delineate the three options for clock usage and their effect on the 82050 system clock as
well as on the BRG source frequency:
The 82050 has two modes of system clock operation. It can accept an externally gE1nerated clock, or
use a crystal to internally generate its system clock
by using the on-chip oscillator.
The 82050 has an on-chip oscillator which can be
used to generate its system clock. The oscillator will
take the input from a crystal attached to the X1 and
2-28
82050
1. Crystal Oscillator: (Maximum 18.432 MHz)
- System Clock Frequency = Crystal
Frequency/2
-
BRG Source Clock Frequency
Frequency /10
NOTE:
The use of the Divide by Two strapping option in
the crsytal oscillator mode is forbidden.
= Crystal
BAUD RATE GENERATION
2. External Clock (Divide by Two Enabled):
The 82050 has a programmable 16-bit Baud Rate
Generator (BRG). The 16X baud rate is generated
by dividing the source clock with the divisor count
from the BRG divisor registers (BAL, BAH). The
BRG source clock is the 82050 system clock divided
by five. If using an actual 82050 system clock of
9.216 MHz, then the BRG source clock will be 9.216
MHz/5 = 1.8432 MHz, which is compatible with the
BRG source clock fed into the IBM PC serial port
BRG. This allows the 82050, while using a faster
system clock, to maintain full compatibility with software divisor calculations based on the 1.8432 MHz
clock used in the IBM PC.
(Maximum 18.432 MHz)
-
System Clock Frequency = External Clock
Frequency/2
-
BRG Source Clock Frequency = External
Clock Frequency/10
3. External Clock (Divide by Two Disabled):
(Maximum 9.216 MHz)
-
System Clock Freq. =
quency
External Clock Fre-
-
BRG Source Clock Freq. = External Clock
Frequency/5
RESET
The 82050 can be reset by asserting the RESET pin.
The RESET pin must be held high for at least 8 system clock cycles. I.f using crystal oscillator, a reset
pulse at least 1 ms should be used to ensure oscillator start ·up. Upon reset, all 82050 registers (except
TXD and RXD) are returned to their default states.
During reset, the 82050's system clock mode of operation is also selected by strapping options on the
RTS and DTR pins (see system clock generation).
290137-5
Figure 5. Strapping
During the power up or reset the RTS pin is an input;
it is weakly pulled high internally and sampled by the
falling edge of reset. If it is driven low externally,
then the 82050 is configured for a crystal oscillator;
otherwise an externally generated clock is expected.
INTERRUPTS
The INT pin will go high, or active, whenever one of
the following conditions occurs provided it is enabled in the interrupt enable register (IER):
a. Receive Machine Error or Break Condition
EXTERNALLY GENERATED SYSTEM
CLOCK
b. Receive Data Available
c. Transmit Data Register Empty
d. Change in the State of the Modem Input Pins
OSC.
ClK1
The INT pin will be reset (low) when the interrupt
source is serviced. The Interrupt Identification Register (IIR) along with the Line Status Register (LSR)
and the Modem Status Register (MSR) can be used
to identify the source requesting service. The IIR
register identifies one of the four conditions listed
above. The particular event or status, which triggers
the interrupt mechanism, can be identified by reading either the Line Status Register or the Modem
Status register. If multiple interrupt sources become
active at anyone time, then highest priority interrupt
source is reflected in the lIR register when the interrupt pin becomes active. Once the highest priority
interrupt is serviced, then the next highest priority
290137-6
Figure 7. External Clock
This is the default mode of system clock operation.
The system clock is divided by two; however, the
user may disable the divide by two by a hardware
strapping option on the DTR pin. The strapping option is similar to the one used on the RTS pin.
2-29
inter
82050
(HIGHEST PRIORITY)
r - - - Rx CONDITION
INTERRUPT
__ _ _ _-11---
Rx DATA AVAILABLE
I - - - Tx DATA REGISTER STATUS
, - - - - MODEM
E
E
------1
--------1
(LOWEST PRIORITY)
Rx PARITY ERROR
OVERRUN ERROR
BREAK DETECTED
FRAMING ERROR
DCD STATE CHANGE
RI STATE CHANGE
DSR STATE CHANGE
CTS STATE CHANGE
290137-7
Figure 8. Interrupt Structure
interrupt source is decoded into the IIR register; the
whole procedure is repeated until there are no more
pending interrupt sources.
'
TRANSMIT
The 82050 transmission mechanism involves the TX
Machine and the TXD Register. The TX Machine
reads characters from the TXD Register, 'serializes
the bits, and transmits them over the TXD pin according to signals provided for transmission by the
Baud Rate Generator. It also generates parity, and
break transmissions upon CPU request.
The falling edge of the start bit triggers the RX Machine, which then starts sampling the RXD input (3
samples). If the samples do not indicate a start bit,
then a false start bit is determined and the RX Machine returns to the start bit search mode. Once a
start bit is detected, the RX Machine starts sampling
for data bits.
If the RXD input is low for the entire character time,
including stop bits, then the RX Machine sets Break
Detect and Framing Error bits in the Line Status
Register (LSR). It loads a NULL character into the
RXD register. The RX Machine then enters the idle
state. When it detects a MARK It resumes normal
operation.
RECEIVE
The 82050 reception mechanism involves the RX
Machine and the RXD Register. The RX Machine
assembles the incoming characters, and loads them
onto the RXD Register. The RX Machine synchronizes the data, passes it ,through a digital filter to filter
out spikes, and then uses three samples to generate
the bit polarity.
SOFnNAREINTERFACE
Like other 110 based peripherals, the 82050 is programmed through its registers to support a variety of
functions. The 82050, register set is identical to the
16450 register set to provide compatibility with software written for the IBM PC. The 82050 register set
occupies eight addresses and includes control,
status, and data registers. The three address lines
and'the Divisbr Latch Access Bit are used to select
the 82050 registers.
2-30
REGISTER DESCRIPTION
RegIster Map
Register
7
6
5
4
2
3
1
0
TxD
TxData
Bit 7
TxData
Bit 6
TxData
Bit 5
TxData
Bit 4
TxData
Bit 3
TxData
Bit 2
TxData
Bit 1
TxData
Bit 0
RxD
RxData
Bit 7
RxData
Bit 6
RxData
Bit 5
RxData
Bit 4
RxData
Bit 3
RxData
Bit 2
RxData
Bit 1
RxData
Bit 0
BAL
BRGA LSB Divide Count (DLAB = 1)
BAH
BRGA MSB Divide Count (DLAB = 1)
IER
0
0
0
IIR
0
0
0
0
Parity
Mode
Bit 2
Parity
Mode
Bit 1
Parity
Mode
Bit 0
Loopback
Control Bit
OUT2
Complement
Modem
Interrupt
Enable
0
AcIIIress
Default
0
-
0
-
0
02H
1
OOH
RxMachine
Interrupt
Enable
TxData
Interrupt
Enable
RxData
Interrupt
Enable
1
OOH
Active
Interrupt
Bit 1
Active
Interrupt
Bit 0
Interrupt
Pending
2
01H
Stop Bit
Length
Bit 0
Character
Length
Bit 1
Character
Length
Bit 0
3
OOH
RTS
Complement
DTR
Complement
4
OOH
CD
I\)
II
......
LCR
DLAB
Divisor
Latch
Access Bit
MCR
0
LSR
0
MSR
DCD Input
Inverted
SCR
Set
Break
0
0
0
TxM
Status
TxD
Empty
Break
Detected
Framing
Error
Parity
Error
Overrun
Error
RxData
Available
5
60H
Rllnput
Inverted
DSR Input
Inverted
CTSlnput
Inverted
State
Change
inDCD
State(H -+ L)
Change
inRI
State
Change
inDSR
State
Change
inCTS
6
OOH
7
OOH
Scratch-Pad Register
-------
-----
Figure 9. Regis~er Description Table
l
~
~
i~
82050
TRANSMIT DATA REGISTER (TXD)
BRG DIVISOR LOW BYTE (BAL)
This register holds the next data byte to be transmitted. When the transmit shift register becomes empty, the contents of the Transmit Data Register are
loaded into the shift register and the Transmit Data
Register Empty condition becomes true.
This register contains the least significant byte of the
Baud Rate Generator's 16-bit divisor. This register is
accessible only when the DLAB bit is set in the LCR
register.,
290137-10
BAL-BRG Divisor Low Byte
290137-8
TXD-Transmit Data Register
BRG DIVISOR HIGH BYTE (BAH)
RECEIVE DATA REGISTE.R (RXD)
This register contains the most significant byte of
the Baud Rate Generator's 16-bit divisor. This register is accessible ony when the DLAB bit is set in the
LCR register.
This register holds the last character received by the
RX Machine. The character is right justified and the
leading bits are zeroed. Reading the register empties the register and resets the Received Character
Available condition.
290137-11
BAH-BRG Divisor High Byte
290137-9
RXD-Recelve Data Register
2-32
82050
INTERRUPT ENABLE REGISTER (IER)
This register enables four types of interrupts which independently activate the INT pin. Each of the four
interrupt types can be disabled by resetting the appropriate bit of the IER register. Similarly by setting the
appropriate bits, selected interrupts can be enabled. If all interrupts are disabled, then the interrupt requests
are inhibited from the IIR register and the INT pin. All other' functions, including Status Register and the Line
Status Register bits continue to operate normally.
[~ I III
76151413121 ~O'
RESERVED
RXDA-RXDATA INTERRUPT ENABLE
TXDE-TXDATA EMPTY ENABLE
....- -.. . RXIE- RX INTERRUPT ENABLE
_.
L..-_ _ _- .
MIE - MODEM INTERRUPT ENABLE
290137-12
IER-Interrupt Enable Register
MIE-MODEM Interrupt Enable
RXIE-RX Machine Interrupt Enable
TXDE-TX Data Register Empty
RXDA-RX Data Available
INTERRUPT IDENTIFICATION REGISTER (IIR)
This register holds the highest priority enabled and active interrupt request. The source of the interrupt request
can be identified by reading bits 2-1.
290137-13
IIR-Interrupt Identification Register
B1, BO-Interrupt Bits, 2-1. These two bits reflect the highest priority, enabled and pending interrupt request.
11: RX Error Condition (Highest Priority)
10: RX Character Available
01: TXD Register Empty
00: Modem Interrupt (Lowest Priority)
lPN-Interrupt Pending-This bit is active low, and indicates that there is an interrupt pending. The interrupt
logic asserts the INT pin as soon as this bit goes active (NOTE: the IIR register is continuously updated; so
while the user is serving one interrupt source, a new interrupt with higher priority may enter IIR and replace the
older interrupt vector).
2-33
inter
82050
LINE CONTROL REGISTER (LCR)
This is a read/write register which defines the basic configuration of the serial link.
DLAB
CLO) CHARACTER
,CLl LENGTH
SBK - SET BACK
PARI1Y [
,
::~
......--. SBLO - STOP BIT LENGTH
. - - - -.....
Pt.iO . - - - - - - - '
290137-14
LCR~Llne Configure Register
DLAB-Dlvisor Latch Access Bit-This bit, when set, allows access to the Divisor Count Registers SAL and
BAH.
SBK-Set Break-This will force the TXD pin low. The TXD pin will remain low until this bit is reset.
PM2-PMD-Parity Mode BIts-These three bits are used to select the various parity modes of the 82050.
PMO
PM2
PM1
Function
0
1
1
1
1
1
X
0
0
1'
1
X
X
0
1
0
1
X
No Parity
Odd Parity
Even Parity
High Parity
Low Parity
Software Parity
SBL-Stop Bit Length-This bit defines the Stop Bit lengths for transmission. The RX Machine can identify
3/4 stop bit or more.
SBL
0
1
1
, Character Length '
X
5·Bit
(6, 7, or 8·Bit)
Stop Bit Length
1
11/2
2
"
CLO-CL1-Character Length-These bits define the character length ,used on the serial link.
CL1
CLO
0
0
1
1
0
1
0
1
Character Length
5 Bits
6 Bits
7 Bits
8 Bits
2·34
inter
82050
LINE STATUS REGISTER (LSR)
This register holds the status of the serial link. When read, all bits of the register are reset to zero.
~ I III
76151413121~O
RESERVED
TXST-TX MACHINE STATUS
TXDE - TXD EMPTY _ .
•
RXDA - RX DATA AVAILABLE
OE-OVERRUN ERROR
-
BKD - BREAK DETECTED
PE - PARITY ERROR
FE - FRAMING ERROR
290137-15
LSR-Llne StatUI Register
RXDA-RX Data Available-This bit, indicates that the RXD register has data available for the CPU to read.
OE-overrun Error-Indicates that a received character was lost because the RXD register was not empty.
PE Parity Error-Indicates that a received character had a parity error.
FE-Framing Error-Indicates that a received character had a framing error.
BkD-Break Detected-This bit indicates that a break condition was detected, i.e., RxD input was held low
for two character times.
TXDE-TXD Empty-This indicates that the 82050 is ready to accept a new character for transmission. In
addition, this bit causes an interrupt request to be generated if the TXD register Empty interrupt is enabled.
TXST- TX Machine Status-When set, this bit indicates that the TX Machine is Empty, i.e., both the TXD
register and the TX Shift Register are empty.
MODEM CONTROL REGISTER (MCR)
This register controls the modem output pins. All the outputs invert the data, i.e., their output will be the
complement of the data written into this register.
290137-16
MCR-Modem Control Register
2-35
inter
82050
LC-Loopback Control-This bit puts the 82050 into a Local Loopback mode.
OUT2-oUT2 Output-This bit controls the QUT2 pin. The output signal is the complement of this bit.
NOTE:
This bit is only effective when the 82050 is being used with an externally generated clock.
RT5-RTS Output Bit-This bit controls the RTS pin. The output signal is the complement of this bit.
DTR-DTR Output Bit-This bit controls the
DTR pin. The output signal
is the complement of this bit.
.
.
MODEM STATUS REGISTER (MSR)
This register holds the status of the modem input pins (CTS, DCD, DSR, RI). It is the source of Modem
interrupts (bits 3-0) when enabled in the IER register. If any of the above input pins change levels, then the
appropriate bit in MSR is set. Reading MSR will clear the status bits.
=
~I+H'I~
OC~;
IIII ~AIT
ro."w,",
COMPLEMENT RI
COMPLEMENT
STATE . CHANGE
CHANGE CTS
DSR
5SR
(H --> L) RI
COMPLEMENT CTS
STATE CHANGE DCD
290137-17
MSR-Mode Status Register
DCDC-DCD Complement-Holds the complement of the DCD pin.
DRIC-RI Complement-Holds the complement of the RI pin.
DSRC-DSR Complement-Holds the complement of the DSR pin.
CTSC-CTS Complement-Holds the complement of the CTS pin.
DDeD-Delta DCD-Indicates that the DCD pin has changed state since this register was last read.
DRI-Delta RI-Indicates that the RI pin has changed state from high to low since this register was last read.
DDSR-Delta DSR-Indicates that the DSR pin has changed state since this register was last read.
DCT5-Delta CT5-lndicates that the CTS pin has changed state since this register was last read.
SCRATCH PAD REGISTER (SCR)
The 8-bit Read/Write register does not control the ACC. It is intended as' a scratch pad register for use by the
programmer.
2-36
infef
82050
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ..•...
D.C. SPECIFICATIONS
o·c to 70·C
Storage Temperature .........• - 6S·C to + 1S0·C
Voltage on any Pin (w.r.t. Vss . -O.SV to Vcc + O.SV
Voltage on Vee Pin (w.r.t. Vss) ...... -O.SV to + 7V
Power Dissipation .•..................... 300 mW
D.C. CHARACTERISTICS
Symbol
(TA = O·TO 70·C, Vee = SV ±10%)
Parameter
Notes
Min
Max
Units
0.8
V
Vee
+0.5
V
0.45
V
(4)
±10
p.A
Vil
Input Low Voltage
(1 )
-0.5
VIH
Input High Voltage
(1), (7)
2.0
Val
Output Low Voltage
(2), (9)
VOH
Output High Voltage
(3), (9)
III
Input Lea~age Current
ILO
3-State Leakage Current
(5)
±10
p.A
IOHR
Input High for DTR RTS
(10)
0.4
mA
IOlR
Input Low for DTR, pRTS
(10)
LXTAl
X1, X2 Load
Icc
Power Supply Current
(6)
Cin
Input Capacitance
(8)
10
Cio
1/0 Capacitance
(8)
10
2.4
11
NOTES:
1. Does not apply to elK/X1 pin, when configured as crystal oscillator input (X1).
2. @ 101 = 2 rnA.
3. @ loh = -0.4 rnA.
4. 0 < Yin < Vee.
5. 0.45V < You! < 01ee - 0.45).
6. Vee = 5.5V; V,I - 0.5V (max); Vih = Vee - 0.5V (min); 101 = loh = 0; 9.2 MHz (max).
7. VIH = 2.4V on AD and AXD pins.
8. Freq = 1 MHz.
9. Does not apply OUT2/X2 pin, when configured as crystal oscillator output (X2).
10. Input current for DTR. ATS pins during Reset for Clock Mode Configuration.
2-37
V
mA
10
pF
3.8
35
mAIMHz
mA (max)
pF
pF
82050
A.C. SPECIFICATIONS
SYSTEM CLOCK SPECIFICATIONS
Max
Notes
250
(2)
TCH1CH2 ClK Rise Time
10
(1 )
TCl2Cl1
ClK Fall Time
10
(1 )
FXTAl
External Crystal
4.0 18.432
Frequency Rating
MHz
Symbol
Testing Conditions:
Parameter
Min
DIVIDE BY TWO OPTION-ACTIVE
• All AC output parameters are under output load
of 20 to 100 pF, unless otherwise specified.
• AC testing inputs are driven at 2.4 for logic '1',
and 0.45V for logic '0'. Output timing measurements are made at 1.5V for both a logical '0' and
'1' .
• In the following tables, the units are ns, unless
otherwise specified.
System Interface Specification-System Clock
Specification:
Tcy/2
ClK Period
54
TClCH
ClKlowTime
25
TCHCl
ClK High Time
25
DIVIDE BY TWO OPTION-INACTIVE
The 82050 system clock is supplied via the ClK pin
or generated by on-Chip crystal oscillator. The clock
is optionally divided by two. The ClK parameters are
given separately for internal divide-by-two option
ACTIVE and INACTIVE.
The system clock (after division by two, if active)
must be at least 16X the Tx or Rx baud rate (the
faster of the two).
Tcy
ClK Period
108
TClCH
ClKlowTime
54
TCHCl
ClK High Time
44
250
TCH1CH2 ClK Rise Time
15
(1)
TCl2Cl1
15
(1)
ClK Fall Time
NOTES:
1. Rise/fall times are measured between 0.8 and 2.0V.
2. Tcy in ACTIVE divide by two option is TWICE the input
clock period.
RESET SPECIFICATION
Symbol
Parameter
Min
TRSHl
Reset Width-ClK/X1 Configured to ClK
8Tcy
TTlRSl
RTS/OTR lOW Setup to Reset Inactive
6Tcy
TRSlTX
RTS/OTR low Hold after Reset Inactive
0
RESET
DTR/RTS
Max
Notes
(1 )
(2)
Tcy - 20
(2)
=t
------.......~
i--- TRSHL
---------
~
TTLRSL
TRSLTXl
--------------------~------------~------290137-18
NOTES:
1. In case of CLK/X1 configured as X1, additional time is required to guarantee crystal oscillator wake-up.
2. RTS/DTR are internally driven HIGH during RESET active time. The pin should be either left OPEN or externally
driven LOW during RESET according to the required configuration of the system clock. These parameters specify the
timing requirements on. these pins, in case they are externally driven LOW during RESET. The maximum spec on
TRSLTX requires that the RTS/DTR pins not be forced later than TRSLTX maximum.
2-38
infef
82050
READ CYCLE SPECIFICATIONS
Symbol
Parameter
Min
+ 65
TRLRH
RD Active Width
TAVRL
Address/CS Setup Time to AD Active
7
TRHAX
Address/CS Hold Time after RD Inactive
0
TRLDV
Data Out Valid after RD Active
TCIAD
Command Inactive to Active Delay
TRHDZ
Data Out Float Delay after RD Inactive
2Tcy
2Tcy
Tcy
Notes
Max
+ 65
(1)
+ 15
(2)
40
NOTES:
1. C1 = 20 pF to 100 pF.
2. Command refers to either Read or Write signals.
A2-0
CS
07-0.
VALID
------t:;1~)-_:~-:---------------290137-19
WRITE CYCLE SPECIFICATION
Symbol
Parameter
WR Active Width
Address CS Setup Time to WR Active
7
TWHAX
Address and CS Hold Time after WR
0
TDVWH
Data in Setup Time toWR Inactive
90
TWHDX
Data in Hold Time after WR Inactive
12
A2-0
CS
Notes
15
I--TWLWH--:-- TCIAD-...
- TWHAX.I-::,
I-
}{
VALID
TDVWH
07-0
2Tcy
+
TWLWH
TAVWL
TAVWL
Max
Min
1
.1
VALID
TWHDX
VALID
-TCIAD.:1
\
290137-20
2-39
inter
82510
ASYNCHRONOUS SERIAL CONTROLLER
Operation
• -Asynchronous
5- to 9-Blt Character Format
MCS-51 9-Blt Protocol Support
• IBM
PC AT® (INS 8250AI16450®)
• Software
Compatible
Control Character Recognition
•
III with Power Down Mode
• CHMOS
Interrupts Maskable at Two Levels
• Auto Echo and Loopback Modes
• Seven 1/0 Pins, Dedicated and General
• Purpose
• 28-Lead DIP and PLCC Packages
- Baud Rate DC to 288k
- Complete Error Detection
• Multiple Sampling Windows
Two, Independent, Four-Byte Transmit
and Receive FIFOs
- Programmable Threshold
Two, 16-blt Baud Rate Generatorsl
Timers
System Clock Options
- On-Chip Crystal Oscillator
- External Clocks, LowlHlgh Speed
•
•
•
(See Packaging Spec., Order #: 231369)
The Intel CHMOS 82510 is designed to increase system eH:iciency in asynchronous environments such as
modems, serial port&-including expanding performance areas: MCS-51 9-bit format and high speed async.
The functional support provided in tne 82510 is unpa~aller~d-2 baud rate gen~rators/timers provide independent data rates or protocol timeouts; a crystal oscillator and smart modem 1/0 simplify system logic. New
features, dual FIFOs and Control Character Recognition (CCR), dramatically reduce CPU interrupts and increase software efficiency. The 82510's software versatility allows emulation of the INS8250A/16450® for
IBM PC AT® compatibility or a high performance mode, configured by 35 control registers. All interrupts are
maskable at 2 levels. The multi-personality 1/0 pins are configurable as desired. A DPLL and multiple sampling
of serial data improve data reliability for high speed asynchronous communication. The compact 28-pin 82510
is fabricated in CHMOS III technology and includes a software powerdown option.
~
SERIAL MODULE
r+
- r+
Vee -:
A(2-0)
0(7-0)
INT
........
-+ ~
+
TX
MACHINE
,
TXD
"
'
r--
-- ...
es - :::
- ....
1m
WR
TX
rlFO
INT
BUS
INTERFACE
UNIT
RX
FIFO
'4
H
TJRTS
RESET
+-
1, Jx Jx
T
' f M - r Rt
INT
'2
INTE~ BUS
I
I
RX
MACHINE
TIMING
BLOCK
(BRGS, SYS CLOCK)
MODEM
INTERFACE
MODULE
IX
RXC
RXD
1X
TXC
~
-,CLK/Xl
-,
I:::: :::-
0IlT2/X2
I'I/SCLK
C!R/TA/lltJTl!
... m
-...
I
~/ICLK/mm
DTII/TB
~
~ -,1m
290116-1
Figure 1. Block Diagram
2-40
April 1988
Order Number: 290118-003
82510
D3
02
"321282726
TXD
o
VSS
82510
DO
DO
A2
A2
TXD
vss
AO
ClK/XI
21
~/SClK
vee
Rii
WR
DSR/TA/i5lTfO
ClK/X1
ill/SClK
DSR/TA/OUTO
DCD/IClK/OUTl
RXD
C'i'S
cs
RESET
ii'iS
iifR/TB
290116-3
290116-2
Figure 2. PLCC Pinout
Figure 3. DIP Pinout
82510 PINOUT DEFINITION
Pin
No.
Type
Name and Description
RESET
17
I
RESET: A high on this input pin resets the 82510 to the Default Wake-up mode.
CS
18
I
CHIP SELECT: A low on this input pin enables the 82510 and allows read or
write operations.
A2-AO
2422
I
ADDRESS PINS: These inputs interface with three bits of the System Address
Bus to select one of the internal registers for read or write.
07-00
4"
25
1/0
RD
20
I
READ: A low on this input pin allows the CPU to read Data or Status bytes from
the 82510.
WR
19
I
WRITE: A low on this input allows the CPU to write Data or Control bytes to the
82510.
INT
5
0
INTERRUPT: A high on this output pin signals an interrupt request to the CPU.
The CPU may determine the particular source and cause of the interrupt by
reading the 82510 Status registers.
CLK/X1
9
I
MULTIFUNCTION: This input pin serves as a source for the internal system
clock. The clock may be asynchronous to the serial clocks and to the processor
clock. This pin may be used in one of two modes: CLK - in this mode an
externally generated TIL compatible clock should be used to drive this input pin;
X1 - in this mode the clock is internally generated by an on-chip crystal
oscillator. This mode requires a crystal to be connected between this pin (X1)
and the X2 pin. (See System Clock Generation.)
OUT2/X2
8
0
MULTIFUNCTION: This is a dual function pin which may be configured to one of
the following functions: OUT2 - a general purpose output pin controlled by the
CPU, only available when CLK/X1 pin is driven by an externally generated clock;
X2 - this pin serves as an output pin for the crystal oscillator. Note: The
configuration of the pin is done only during hardware reset. For more details
refer to the System Clock Generation.
TXD
6
0
TRANSMIT DATA: Serial data is transmitted via this output pin starting at the
Least Significant bit.
Symbol
DATA BUS: Bi-directional, three state, eight-bit Data Bus. These pins allow
transfer of bytes between the CPU and the 82510.
'Pins 28-25 and Pins 4-1.
2-41
82510
82510 PINOUT DEFINITION (Continued)
Pin
No.
Type
RXD
13
I
RECEIVE DATA: Serial data is received on this input pin starting at the least
Significant bit.
RI/SClK
10
I
MULTIFUNCTION: This is a dual function pin which can be configured to one of
the following functions. RI - Ring Indicator - Input, active low. This is a general
purpose input pin accessible by the CPU. SClK - This input pin may serve as a
source for the internal serial clock(s), RxClk and/or TxClk. See Figure 12, BRG
sources and outputs.
DTR/TB
\
15
0
MULTIFUNCTION: This is a dual function pin which may be configured to one of
the following functions. DTR - Data Terminal Ready. Output, active low. This is a
general purpose output .pin controlled by the CPU. TB - This pin outputs the
BRGB output signal when configured as either a clock generator or as a timer.
When BRGB is configured as a timer this pin outputs a "timer expired pulse."
When BRGB is configured as a clock generator it outputs the BRGB output
clock.
DSR/TAI
OUTO
11
I/O
MULTIFUNCTION: This is a multifunction pin which may be configured to one of
the following functions. DSR - Data Set Ready. Input, active low. This is a
general purpose input pin accessible by the CPU. TA - This pin is similar in
function to pin TB except it outputs the signals from BRGA instead of BRGB.
OUTO - Output pin. This is a general purpose output pin controlled by the CPU.
RTS
16
0
REQUEST TO SEND: Output pin, active low. This is a general purpose output
pin controlled by the CPU. In addition, in automatic transmission mode this pin,
along with CTS, controls the transmission of data. (See Transmit modes for
further detail.) During hardware reset this pin is an input. It is used to determine
the System Clock Mode. (See System Clock Generation for further detail.)
CTS
14
I
CLEAR TO SEND: Input pin, active low. In automatic transmission mode it
directly controls the Transmit Machine. (See transmission mode for further
details.) This pin can be used as a General Purpose Input.
DCD/IClK/
OUT1
12
I/O
Vee
Vss
21
P
Vee: Device power supply.
7
P
Vss: Ground.
Symbol
Name and Description
MULTIFUNCTION: This is a multifunction pin which may be configured to one of
the following functions. DCD - Data Carrier Detected; Input pin, active low. This
is a general purpose input pin accessible by the CPU. IClK - This pin is the
output of the internal system clock. OUT1 - General purpose output pin.
Controlled by the CPU.
Table 1. Multifunction Pins
110
Timing
Modem
8
*OUT2
X2
9
"ClK/X1
10
-
-
11
12
14
Pin #
15
16
SClK
'RI
OUTO
TA
'DSR
OUT1
IClK
"DCD
-
-
"CTS
TB
*DTR
-
°RTS
'Default
2-42
intJ
82510
Its register set can be used in 8250A/16450 compatibility or High Performance modes. The 8250Al
16450 mode is the default wake-up mode in which
only the 8250Al16450 compatible registers are accessible. The remaining registers are default configured to support 8250Al16450 emulation.
GENERAL DESCRIPTION
The 82510 can be functionally divided into seven
major blocks (See Fig 1): Bus Interface Unit, Timing
Unit, Modem Module, Tx FIFO, Rx FIFO, Tx Machine, and Rx Machine. Six of these blocks (all except Bus Interface Unit) can generate block interrupts. Three of these blocks can generate secondlevel interrupts which reflect errors/status within the
block (Receive Machine, Timing Unit, and the Modem Module).
Software Interface
HIGH PERrORMANCE MODE
ALL BANKS rUNCTION
The Bus interface unit allows the 82510 to interface
with the rest of the system. It controls access to
device registers as well as generation of interrupts
to the external world. The FIFOs buffer the CPU
from the Serial Machines and reduce the interrupt
overhead normally required for serial operations.
The threshold (level of occupancy in the FIFO which
will generate an interrupt) is programmable for each
FIFO. The timing unit controls generation of the system clock through either its on-chip crystal oscillator,
or an externally generated clock. It also provides two
Baud Rate Generators/Timers with various options
and modes to support serial communication.
8250 MODE
~
I
I
290116-4
FUNCTIONAL DESCRIPTION
Figure 4. 82510 Register Architecture
CPU Interface
The 82510 is configured and controlled through its
35 registers which are divided into four banks. Only
one bank is accessible at anyone time. The bank
switching is done by changing the contents of the
bank pointer (GIR/BANK-BANKO, BANK1). The
banks are logically grouped into 8250Al16450 compatible (0), General Work Bank (1), General Configuration (2), and Modem Configuration (3). The
8250A/16450 compatible bank (Bank 0) is the default bank upon power up.
The 82510 has a simple demultiplexed Bus Interface, which consists 'Of a bidirectional three-state
eight-bit, data bus and a three-bit address bus. An
Interrupt pin along with the Read, Write and Chip
Select are the remaining signals used to interface
with the CPU. The three address lines along with the
Bank Pointer register are used to select the registers. The 82510 is deSigned to interface to all Intel
microprocessor and microcontroller families. Like
most other I/O based peripherals it is programmed
through its registers to support a variety of functions.
The 82510 registers can be categorized under the
following:
Table 2. 82510 Register/Block Functions
FIFO
MODEM
RX
TX
TIMER
DEVICE
8250
Status
FLR
MSR
Enable
RST,RXF
LSR
TMST
RIE
LSR
TMIE
GSR, GIR
LSR, MSR, GIR
GER
GER
MIE
Configuration
FMD
PMD
Command
Data
-
-
RMD
TMD
CLCF,
BACF,BBCF
IMD
LCR, MCR
RCM
TCM
TMCR
2-43
MCR
ICM
MCR
RXD, RXF
TXD,TXF
BBL, BBH
BAL, BAH
TXD,RXD
BAL, BAH
inter
82510
8250 Compatibility
Upon power up or reset, the 82510 comes up in the default wake up mode. The 8250A/16450 compatible
bank, bank zero, is the accessible bank and all the other registers are configured, via their default values to
support this mode. An 18.432 MHz crystal frequency is necessary.
Table 3. 8250A/16450 Compatible Registers
82510 Registers
(Bank 0)
Address
00 (DLAB
01 (DLAB
00 (DLAB
01 (DLAB
Read
= 0)
= 0)
= 1)
= 1)
8250A Registers
Write
Read
Write
THR
RxD
TxD
RBR
GER
GER
IER
IER
BAL
BAL
DLL
DLL
BAH
BAH
DLM
DLM
02
GIR/BANK
BANK
IIR
-
03
LCR
.LCR
LCR
LCA
04
MCR
MCR
MCR
MCR
05
LSR
LSR
LSR
LSR
06
MSR
MSR
MSR
MSR
07
ACRO
ACRO
SCR
SCR
Table 4. Default Wake-Up Mode
ACR1
TxD
-
RIE
1EH
TxF
BAL
02H
RMD
OOH
TMST
BAH
OOH
CLCF
OOH
TMCR
GER
OOH
BACF
04H
FLR
GIR/BANK
01H
BBCF
84H
RCM
LCR
OOH
PMD
FCH
rCM
-
MCR
OOH
MIE
OFH
GSR
12H
RxD
OOH
RxF
30H
OOH
LSR
60H
TMIE
OOH
ICM
-
MSR
OOH
BBL
05H
FMD
OOH
ACRO
OOH
BBH
OOH
TMD
OOH
RST
OOH
IMD
OCH
2-44
82510
(HIGHEST PRIORITY)
TIMER
s=
Tc
TIMER A EXPIRED
TIMER B EXPIRED
TX MACHINE IDLE
RX PARITY ERROR
OVERRUN ERROR
BREAK DETECTED
BREAK TERMINATED
ADDRESS/CONTROL
CHAR. RECEIVED
ADDRESS/CONTROL
CHAR. MATCH
TX CONDITION
RX CONDITION
INTERRUPT
FRAMING ERROR
RX FIFO - - - - RX FIFO LEVEL ABOVE
THRESHOLD
TX FIFO - - - - TX FIFO LEVEL EQUAL
TO OR BELOW THRESHOLD
MODEM
(LOWEST PRIORITY)
----E
DCD CHANGE STATE
RI CHANGE STATE
DSR CHANGE STATE
CTS CHANGE STATE
290116-5
Figure 5. Interrupt Structure
The CPU must issue an explicit Interrupt Acknowledge command via the Interrupt Acknowledge bit of
the Internal Command register. As a result the INT
pin is forced low for two clocks and then updated.
Interrupts
There are two levels of interrupt/status reporting
within the 82510. The first level is the block level
interrupts such as RX FIFO, Tx FIFO, Rx Machine,
Tx Machine, Timing unit, and Modem Module. The
status of these blocks is reported in the General
Status and General Interrupt Registers. The second
level is the various sources within each block; only
three of the blocks generate second level interrupts
(Rx Machine, Timing Unit, and Modem Module). Interrupt requests are maskable at both the block level
and at the individual source level within the module.
If more than one unmasked block requests interrupt
service an on-chip interrupt controller will resolve
contention on a priority basis (each block has a fixed
priority). An interrupt request from a particular block
is activated if one of the unmasked status bits within
the status register for the block is set. A CPU service
operation, e.g., reading the appropriate status register, will reset the status bits.
2. Automatic Acknowledge
As opposed to the Manual Acknowledge mode,
when the CPU must issue an explicit interrupt acknowledge command, an interrupt service operation
is considered as an automatic acknowledgment.
This forces the INT pin low for two clock cycles.
After two cycles the INT pin is updated, i.e., if there
is still an active non-masked interrupt request the
INT pin is set HIGH.
INTERRUPT SERVICE
A service operation is an operation performed by the
CPU, which causes the source of the 82510 interrupt
to be reset (it will reset the particular status bit causing the interrupt). An interrupt request within the
82510 will not reset until the interrupt source has
been serviced. Each source can be serviced in two
or three different ways; one general way is to disable
the particular status bit causing the interrupt, via the
corresponding block enable register. Setting the appropriate bit of the enable register to zero will mask
off the corresponding bit in the status register, thus
causing an edge on the input line to the interrupt
logic. The same effect can be achieved by masking
ACKNOWLEDGE MODES
The interrupt logic will assert the INT pin when an
interrupt is coded into the General Interrupt register.
The INT pin is forced low upon acknowledgment.
The 82510 has two modes of interrupt acknowledgment:
1. Manual Acknowledge
2-45
inter
82510
off the particular block interrupt request in GSR via
the General Enable Register. Another method,
which is applicable to all sources, is to issue the
Status Clear command from the Internal Command
Register. The detailed service requirements for each
source are given below:
The 82510 has an on-Chip oscillator to generate its
system clock. The oscillator will take the inputs from
a crystal attached to the Xi and X2 pins. This mode
is configured'via a hardware strapping option on
RTS.
Table 5. Service Procedures
Interrupt Status Bits Interrupt
Source & Registers Masking
Timers
Specific
Service
TMST (1-0) TMIE (1-0) ReadTMST
GSR (5)
GER (5)
GSR (4)
Tx
Machine LSR (6)
GER (4)
Write Character
totX FIFO
LSR (4-1)
Rx
Machine RST (7-1)
GSR (2)
RIE (7-1)
GER (2)
Read RSTor
LSRWriteO
to bit in
RST/LSR
Rx FIFO RST/LSR (0) GER (0)
GSR (0)
Write 0 to
LSR/RST
Bit zero.
Read Character
TxFIFO LSR (5)
GSR (1)
GER (1)
Write to FIFO
Read GIR(l)
Modem
MIE (3-0)
GER (3)
Read MSR
write 0 into the
appropriate bits
of MSR (3-0).
MSR (3-0)
GSR (3)
290116-7
Figure 7. Strapping Option
During hardware reset the RTS pin is an input; it is'
weakly pulled high from within and then checked. If it
is driven low externally then the 82510 is configured
for the ,Crystal Oscillator; otherwise an external
clock is expected.
EXTERNALLY GENERATED SYSTEM CLOCK
I I•
OS<
T'" I
OUT2'
290116-8
NOTE:
1. Only if pending interrupt is Tx FIFO.
Figure 8. External Clock
This is the default configuration. Under normal conditions the system clock is divided by two; however,
the user may disable divide by two via a hardware
strapping option on the DTR pin. The Hardware
strapping option is similar to the one used on the
RTS pin. It is forbidden, to strap both DTR and RTS.
System Clock Generation
The 82510 has two modes of System Clock Operation. It can accept an externally generated clock, or
it can use a crystal to internally generate its system
clock.
Transmit
CRYSTAL OSCILLATOR
~~
The two major blocks involved in transmission are
the Transmit FIFO and the Transmit Machine. The
Tx FIFO acts as a buffer between the CPU and the
Tx Machine. Whenever a data character is written to
the Transmit Data register, it, along with the Transmit Flags (if applicable), is loaded into the Tx FIFO.
Parallel Resonanl Crystal
ri~
290116-6
Figure 6. Crystal Oscillator
2-46
inter
82510
TRANSMIT CLOCKS
TX FIFO
TXF REGISTER
There are two modes of transmission clocking, 1X
and 16X. In the 1X mode the transmitted data is
synchronous to the transmit clock as supplied by the
SCLK pin. In this mode stop-bit length is restricted to
one or two bits only. In the 16X mode the data is not
required to be synchronous to the clock. (Note: The
Tx clock can be generated by the BRGs or from the
SCLK pin.)
TXD REGISTER
DATA
FLAGS
I
1
---1--------11 ..
POINTER t--
MODEM HANDSHAKING
The transmitter has three modes of handshaking.
POINTER
[
~I
______
CH_A_RA_C_T_ER_F_R_A_ME____
Manual Mode-In this mode the CTS and RTS pins
are not used by the Tx Machine (transmission is
started regardless of the CTS state, and RTS is not
forced low). The CPU may manage the handshake
itself, by accessing the CTS and RTS signals
through the MODEM CONTROL and MODEM
STATUS registers.
~~TXD
290116-9
Figure 9_ Tx FIFO
The Tx FIFO can hold up to four, .eleven-bit characters (nine-bits data, parity, and address flag). ,It has
separate read and write mechanisms. The read and
write pointers are incremented after every oper~tion
to allow data transfer to occur in a First In First Out
fashion. The Tx FIFO will generate a maskable interrupt when the level in the FIFO is below, or equal to,
the Threshold. The threshold is user programmable.
Semi-Automatic Mode-In this mode. the RTS pin
is activated whenever the transmitter is enabled.
The CTS pin's state controls transmission. Trans·
mission is enabled only if
is active. If
becomes inactive during transmission, the Tx Machine
will complete transmission of the current character
becomes
and then go to the inactive state until
active again.
rn
rn
rn
For example, if the threshold equals two, and the
number of characters in the Tx FIFO decreases from
three to two, the FIFO will generate an interrupt. The
threshold should be selected with regard to the system's interrupt service latency.
Automatic Mode-This mode is similar to the semiautomatic mode, except that RTS will be activated
as long as the transmitter is enabled and there are
more characters to transmit. The CPU need only fill
the FIFO, the hal)dshake is done by the Tx Machine.
When both the shift register and the FIFO are empty
RTS automatically goes inactive. (Note: The RTS pin
can be forced to the active state by the CPU, regardless of the handshaking mode, via the MODEM
CONTROL register.)
NOTE:
There is a one character transmission delay between FIFO empty and Transmitter Idle, so a
threshold of zero may be selected without getting
an underrun condition. Also if more than four characters are written to the FIFO an overrun will occur
and the extra character will not be written to the Tx
FIFO. This error will not be reported to the CPU.
Receive
The 82510 reception mechanism involves two major
blocks; the Rx Machine and the Rx FIFO. The Rx
Machine will assemble the incoming character and
its associated flags and then LOAD them on to the
Rx FIFO. The top of the FIFO may be read by reading the Receive Data register and the Receive Flags
Register. The receive operation can be done in two
modes. In the normal mode the characters are reo
ceived in thl;) standard Asynchronous format and
only control characters are recognized. In the ulan
mode, the nine bit protocol of the MCS-51 family is
supported and the ulan Address characters, rather
than Control Characters are recognized.
TX MACHINE
The Tx Machine reads characters from the Tx FIFO,
serializes the bits, and transmits them over the TXD
pin according to the timing signals provided for
transmission. It will also generate parity, transmit
break (upon CPU request), and manage the modem
handshaking signals (CTS and RTS) if configured
so. The Tx machine can be enabled or disabled
through the Transmit Command register or CTS. If
the transmitter is disabled in the middle of a character transmission the transmission will continue until
the end of the character; only then will it enter the
disable state.
2·47
inter
82510
Manual Mode-In this mode the Rx Machine does
not control the FIFO automatically; however, the
user may UNLOCK/LOCK the FIFO by using the
RECEIVE COMMAND register.
RX FIFO
I
RXD REGISTER
RXf REGISTER
DATA
fLAGS
ro~ I~-
RX MACHINE
The RX Machine has two modes of clocking the incoming data-16X or lX. In l6X synchronization is
done internally; in the 1X mode the data must be
synchronous to the SCLK pin input. The Rx Machine
synchronizes the data, passes it through a digital filter to filter out the spikes, and then uses the voting
counter to generate the data bit (multiple sampling
of input RXD). Bit polarity decisions are made on the
basis of majority voting; i.e., if the majority of the
samples are "1" the result is a "1" bit. If all samples
are not in agreement then the bit is also reported as
a noisy bit in the RECEIVE FLAGS register. The
sampling window is programmable for either 3/16 or
7/16 samples. The 3/16 mode is useful for high frequency transmissions, or when serious RC delays
are expected on the channel. The 7/16 is best suited for noisy media. The Rx machine also has a
DPLL to overcome frequency shift problems; however, using it in a very noisy environment may increase
the error, so the user can disable the DPLL via the
Receive Mode register. The Rx Machine will generate the parity and the address marker as well as any
framing error indications.
I
RXD
-+ 1
...___C_HA_R_AC_TE_R_f_RA_M_E_ _..I
290116-10
Figure 10. Rx FIFO
The Rx FIFO is very similar in structure and basic
operation to the Tx FIFO. It will generate a maskable
interrupt when the FIFO level is above, the threshold. The Rx FIFO can also be configured to operate
as a one-byte buffer. This mode is used for 8250
compatible software drivers. An overrun will occur
when the FIFO is full and the Rx Machine has a new
character for the FIFO. In this situation the oldest
character is discarded and the new character is
loaded from the Rx Machine. An Overrun error bit
will also be set in the RECEIVE STATUS and LINE
STATUS registers.
Start Bit Detection-The falling edge of the Start
bit resets the DPLL counter and the Rx Machine
starts sampling the input line (the number of samples is determined by the configuration of the sampling window mode). The Start bit verification can be
done through either a majority voting system or an
absolute voting system. The absolute voting requires
that all the samples be in agreement. If one of the
samples does not agree then a false Start bit is determined and the Rx Machine returns to the Start Bit
search Mode. Once a Start bit is detected the Rx
Machine will use the majority voting sampling window to receive the data bits..
The user has the option to disable the loading of
incoming characters on to the Rx FIFO by using the
UNLOCK/LOCK FIFO commands. (See RECEIVE
COMMAND register.) When the Rx FIFO is locked, it
will ignore load requests from the Rx Machine, and
thus the received characters will not be loaded into
the FIFO and may be lost (if another character is
received). These two commands are useful when
the CPU is not willing to receive characters, or is
waiting for specific Control/Address characters. In
uLAN mode there are three options of address recognition, each of these options varies in the amount
of CPU offload, and degree of FIFO control through
OPEN/LOCK FIFO commands.
Break Detection-If the input is low for the entire
character frame including the stop Bit, then the Rx
Machine will set Break Detected as well as Framing
Error in the RECEIVE STATUS and LINE .STATUS
registers. It will push a NULL character onto the Rx
FIFO with a framing-error and Break flag (As part .of
the Receive Flags). The Rx Machine then enters the
Idle state. When it sees a mark it will set Break Terminated in RECEIVE STATUS and LINE STATUS
registers and resume normal operation.
.
Automatic Mode-In this mode the Rx Machine will
open the FIFO whenever an Address Match occurs;
it will LOCK the J=I FO if an address mismatch occurs.
Semi-Automatic Mode-In this mode the Rx Machine will open the FIFO Whenever an address character is received. It will not lock the FIFO if the Address does not match. The user is responsible for
locking the Rx FIFO.
2-48
inter
82510
4 BIT DPLL
COU NTER
15
0
1
2
3
4
5
6
I I I
-- 1>. .
8
9
10
~ V~ V~
NARROW WINDOW
WIDE WINDOW
7
V// V~ V~ t// ~/
11
12
13
14
15
301' 16
0
V~
701'16
~
DATA INPUT LINE
III
290116-11
Figure 11. Sampling Windows
SOFTWARE
CONTROLLED
Control Characters-The Rx machine can generate a maskable interrupt upon reception of standard
ASCII or EBCDIC control characters, or an Address
marker is received in the uLAN mode. The Rx machine can also generate a maskable interrupt upon a
match with programmed characters in the Address/
Control Character 0 or Address/Control Character 1
registers.
GATE
SYS ClK
XTAl ClK
SClK
SClK
SYS ClK
XTAl ClK
SRGA
OUTPUT
CONTROL CHARACTER RECOGNITION
STANDARD SET
OOOX XXXX
• ASCII:
(00 - 1FH
•
BJ
+
OUT
Rx ClK
Tx ClK
SRGS
SOURCE
OUT
RxClK
TxClK
·A·
SOFTWARE
CONTROllED
Table 6. Control Character Recognition
AJ
SOURCE
+ 0111
1111
(ASCII DEL)
7 FH)
GATE
SOURCE
·B·
Figure 12. BRG Sources and Outputs
OR
BAUD RATE GENERATION
EBCDIC: OOXX XXXX
(00 - 3FH)
The Baud Rate is generated by dividing the source
clock with the divisor count. The count is loaded
from the divisor count registers into a count down
register. A 50% duty cycle is generated by counting
down in steps of two. When the count is down to 2
the entire count is reloaded and the output clock is
toggled. Optionally the two BRGs may be cascaded
to provide a larger divisor. Note that this is the default configuration and used for 8250Al16450 emulation.
User Programmed
• ACRO, ACR1 XXXX XXXX
REGISTERS
Baud-Rate Generators/Timers
f 0 = !i".IDivisor
The 82510 has two-on-chip, 16-bit baud-rate generators. Each BRG can also be configured as a Timer,
and is completely independent of the other. This can
be used when the Transmit and Receive baud rates
are different. The mode, the output, and the source
of each BAG is configurable, and can also be optionally output to external devices via the TA, TB
pins (see Fig. 12. BRG Sources and Outputs).
where fin is the input clock frequency and Divisor is
the count loaded into the appropriate count registers. System clock frequencies can be selected
(4 9.216 MHz) to eliminate baud rate error for
high baud rates.
'
2-49
inter
82510
delay between the trigger and the terminal count is
given by the following equation:
Table 7. Standard Baud Rates
%
16x Divisor
Bit Rate
Error
Delay = Count. (System Clock Period)
To start counting, the Timer has to be triggered via
the Start Timer Command. To restart the Timer after
terminal count or while counting, the software has to
issue the trigger command again. While counting the
Timer can be enabled or disabled by using a software controlled Gate. It is also possible to output a
pulse generated upon terminal count through the TA
or TB pins.
110
5236 (1474h)
.007%
300
1,920 (780h)
38,400
15 (OFh)
-
56,000
10 (OAh)
2.8%
288,000
2 (02h)
1200
480 (1 EOh)
2400
240 (FOh)
9600
60 (3Ch)
19,200
30 (1 Eh)
-
Source ClK = Internal Sys. Clk
= 18.432 MHz/2 (Crystal)
= 9.21 MHz (External 1X clock)
e
NOTE:
Internal system clock is % crystal frequency or
clock frequency when using + 2 clock option.
% external
The BRG counts down in increments of two and
then is divided by two to generate a 50% duty cycle;
however, for odd divisors it will count down the first
time by one. All subsequent countdowns will then
continue in steps of two. In those cases the duty
cycle is no longer exactly 50%. The deviation is given by the fOllowing equation:
In 1X clock mode the only clock source available is
the SCLK pin. The serial machines (both Tx Machine
and Rx Machine) can independently use one of two
clock modes, either 1X or 16X. Also no configuration
changes are allowed during operation as each write
in the BRG configuration registers causes a reset
signal to be sent to the BRG logic. The mode or
source clocks may be changed only after a Hardware or Software reset. The Divisor (or count, depending upon the mode) may be updated during operation unless the particular BRG machine is being
used as a clock source for one of the serial machines, and the particular serial machine is in operation at the time. Loading the count registers with "0"
is forbidden in all cases, and loading it with a "1" is
forbidden in the Timer Mode only.
SERIAL DIAGNOSTICS
The 82510 supports two modes of Loopback operation, Local Loopback and Remote Loopback as well
as an Echo mode for diagnostics and improved
throughput.
deviation = 11 (2 • divisor)
The BRG can operate with any divisor between 1
and 65,535; however, for divisors between 1 and 3
the duty cycle is as follows:
LOCAL LOOPBACK
Table 8. Duty Cycles
Divisor
Duty Cycle
3
33%
2
50%
1
Same as Source
a
FORBIDDEN
-+~~~~PIN
~EJ)~PIN
290116-12
Figure 13. Local Loopback
Timer Mode
The Tx Machine output and Rx Machine input are
shorted internally, TXD pin output is held. at Mark.
This feature allows simulation of Transmission/Reception of characters and. checks the Tx FIFO, Tx
Machine, Rx Machine, and Rx FIFO along with the
software without any external side effects. The modem outputs OUT1, OUT2, DTR and RTS are internally shorted to RI, DCD, DSR and CTS respectively.
OUTO is held at a mark state.
Each of the 82510 BRGs can be Llsed as Timers.
The Timer is used to generate time delays by counting the internal system clock. When enabled the
Timer uses the count from the Divisor/Count registers to count down to 1. Upon terminal count a
maskable Timer Expired interrupt is generated. The
2-50
inter
82510
The 82510 powers down when the power down
command is issued via the Internal Command Register (ICM). There are two modes of power down,
Sleep and Idle.
REMOTE LOOPBACK
~[§J
=:I
I.!!!!..I
r-:
~PIN
~~
In Sleep mode, even the system clock of the 82510
is shut down. The system clock source of the 82510
can either be the Crystal Oscillator or an external
clock source. If the Crystal Oscillator 'is being used
and the power down command is issued, then the
82510 will automatically enter the Sleep mode. If an
external clock is being used, then the, user must disable the external clock in addition to issuing the
Power Down command, to enter the Sleep mode.
The benefit of this mode is the increas~ savings in
power consumption (typical power consumption in
the Sleep mode is in the ranges of 100s of microAmps). However, upon wake up, the user must
reprogram the device. To exit this mode the user
can either issue a Hardware reset, or read the FIFO
Level Register (FLR) and then issue a software reset. In either case the contents of the 82510 registers are not preserved and the device must be reprogrammed prior to operation. If the Crystal Oscillator
is being used then the user must allow enough time
for the oscillator to wake up before issuing the software reset.
PIN
290116-13
Figure 14. Remote Loopback
The TXD pin and RXD pin are shorted internally (the
data is not sent on to the RX Machine). This feature
allows the user to check the communications channel as well as the Tx and Rx pin circuits not checked
in the Local Loopback mode.
AUTO ECHO
~
r=::1
•
~ L!!!J4-4
RXD PIN
290116-14
The 82510 is in the idle mode when the Power Down
command is issued and the system clock is still running (I. e. the system clock Is generated externally
and not disabled by the user). In this mode the contents of all registers and memory cells are preserved, however, the power consumption in this
mode is greater than in the Sleep mode. Reading
FLR will take the 82510 out of this mode.
Figure 15. Auto Echo
In Echo Mode the received characters are automatically transmitted back. When the characters are
read from the Rx FIFO they are automatically
pushed back onto the Tx FIFO (the flags are also
included). The Rx Machine baud rate must be equal
to, or less than, the Tx Machine baud rate or some
of the characters may be lost. The user has an option of preventing, echo of special characters; 'Control Characters and characters with Errors.
NOTE:
The data read from FLR when exiting Power Down
is invalid and should be ignored.
Power Down Mode
The 82510 has a "power down" mode to reduce'
power consumption when the device is not in use.
2-51
inter
82510
DETAILED REGISTER DESCRIPTION
Table 9. Register Map
Bank
Read
Register
Address
o (NAS)
o (DLAB = 0)
8250Al16450
1 (DLAB
o (DLAB
1 (DLAB
2
3
=
=
=
0)
1)
1)
4
5
"
6
7
1 (WORK)
0,
1
2
3
4
5
6
7
2 (GENERAL CONF)
4
5
6
7
3 (MODEM CONF)
o (DLAB = 0)
1 (DLAB
o (DLAB
1 (DLAB
2
3
RXD
GER
BAL
BAH
GIR/BANK
LCR
MCR
LSR
MSR
ACRO
TXD
GER
BAL
BAH
BANK
LCR
MCR
LSR
MSR
ACRO
RXD
RXF
GIR/BANK
TMST
FLR
RST
MSR
GSR
TXD
TXF
BANK
TMCR
MCR
RCM
TCM
ICM
-
0
1
2
3
=
=
=
0)
1)
1)
4
5
6
7
Write
Register
-
FMO,
GIR/BANK
TMD
IMD
ACR1
RIE
RMD
FMD
BANK
TMD
IMD
ACR1
RIE
RMD
CLCF
BACF
BBL
BBH
GIR/BANK
BBCF
PMD
MIE
TMIE
CLCF
BACF
BBL
BBH
BANK
BBCF
PMD
MIE
TMIE
-
-
(1) ACRO is used in INS8250 as a Scratch-Pad Register
(2) DLAB = LCR Bit #7
The 82510 has thirty-five registers which are divided into four banks of register banks. Only one bank is
accessible at anyone time. The bank is selected through the BANK1-0 bits in the GIR/BANK register. The
individual registers within a bank are selected by the three address lines (A2-0). The 82510 registers can be
grouped into the following categories.
2-52
inter
82510
BANK ZERO 8250Al1845O-COMPATIBLE BANK
Register
7
5
6
4
3
2
1
0
xD(33)
Tx Data
bit 7
Tx Data Tx Data
bitS
bit 5
Tx Data
bit 4
Tx Data
bit 3
TxData
bit2
Tx Data
bit 1
Tx Data
bit 0
0
-
RxD (35)
Rx Data
bit 7
Rx Data Rx Data
bitS
bit 5
Rx Data
bit 4
Rx Data
bit 3
Rx Data
bit2
Rx Data
bit 1
RxData
bit 0
0
-
BAL (11)
BRGA LSB Divide Count (DLAB
BAH (12)
BRGA MSB Divide Count (DLAB
GER (lS)
0
GIR/BANK
21)
0
LCR (2)
0
DLAB
Set
Divisor
Break
Latch
Access bit
0
0
LSR (22)
0
TxM
Idle
Parity
Mode
bit 2
0
Parity
Mode
bit 1
0
02H
1
OOH
Rx Machine
Interrupt
Enable
TxFIFO
Interrupt
Enable
RxFIFO
Interrupt
Enable
1
OOH
Active
Block Int
bit2
Active
Block Int
bit 1
Active
Block Int
bitO
Interrupt
Pending
2
01H
Parity
Mode
bitO
Stop bit
Length
bit 0
Character
Length
bit 1
Character
Length
bit 0
3
OOH
Tx Machine Modem
Interrupt
Interrupt
Enable
Enable
BANK BANK
Pointer Pointer
bit 1
bitO
MCR (32)
MSR (27)
Timer
Interrupt
Enable
= 1)
= 1)
Address Defaul
OUTO
Loopback OUT 2
OUTl
Complement Control bit Complement Complement
RTS
DTR
Complement Complement
4
OOH
TxFIFO
Interrupt
Overrun
Error
RxFIFO
Int Req
5
SOH
State (H - . l) State
Change
Change
inRI
inDSR
State
Change
inCTS
S
OOH
7
OOH
DCD Input Rllnput DSR Input
Inverted Inverted Inverted
f'>,CRO(5)
Break
Detected
Framing
Error
CTS Input State
Change
Inverted
inDCD
Parity
Error
Address or Control Character Zero
BANK ONE-GENERAL WORK BANK
7
2
1
Tx Data
bit 7
Tx Data Tx Data
bitS
bit 5
Tx Data
bit 4
Tx Data
bit 3
Tx Data
bit 2
Tx Data
bit 1
Tx Data
bit 0
0
-
RxD (35)
Rx Data
bit7
Rx Data Rx Data
bitS
bit5
Rx Data
bit 4
Rx Data
bit 3
Rx Data
bit 2
Rx Data
bit 1
Rx Data
bit 0
0
-
RxF (24)
-
Rx Char RxChar
OK
Noisy
RxChar
Parity
Error
Address or
Control
Character
Break
Flag
RxChar
Framing
Error
Ninth
Data bit
of Rx Char
1
-
1
-
TxF(34)
6
5
TxD(33)
Register
Address Software Ninth bit
Marker bit Parity bit of Data Char
4
0
3
0
0
0
0
0
GIR/BANK
(21)
0
BANK
Pointer
bit 1
BANK
Pointer
bitO
TMST (2S)
-
-
GateB
State
Gate A
State
-
TMCR (31)
0
0
Trigger
GateB
Trigger
Gate A
0
MCR (32)
0
0
DTR
OUTO
Loopback OUT2
OUT 1
RTS
Complement Control bit Complement Complement Complement Complement
0
Active
Block Int
bit 2
Active
Block Int
bit 0
Interrupt
Pending
2
01H
-
TimerB
Expired
Timer A
Expired
3
30H
0
Start
TimerB
Start
Timer A
3
-
4
OOH
Active
Block Int
bit 1
NOTE:
The register number is provided as a reference number for the register description.
2-53
Address Default
intJ
82510
BANK ONE-GENERAL WORK BANK (Continued)
Register
7
FLR(25)
-
6
4
5
3
Address! Break
Break
Framing
Control
Terminated Detected Error
Character
Match
Parity
Error
ReM (30) Rx
Enable
Rx
Disable
Open Rx
FIFO
Rllnput
MSR (27) DCD
Complement Inverted
TCM (29)
0
0
GSR (20)
-
-
ICM (28)
0
0
Flush
RxFIFO
DSR Input
Inverted
CTS Input State
Inverted Change
inDCD
Lock Rx
FIFO
0
0
State
State
Change Change
inDSR inCTS
Flush Tx Tx
FIFO
Enable
TxM
Interrupt
Modem
Interrupt
RxM
TxFIFO RxFIFO
Interrupt Interrupt Interrupt
Software
Reset
Manuallnt
Status
Acknowledge Clear
Command
0
0
State
Change
inRI
Overrun RxFIFO
Error
Interrupt
Requested
FlushTx
Machine
0
Timer
Interrupt
Address Default
Tx FIFO Level
RST(23) Address!
Control
Character
Received
Flush
RxM
0
1
2
-
Rx FIFO Level
Tx
Disable
Power
Down
Mode
0
4
OOH
5
OOH
5
-
6
OOH
6
-
7
12H
7
-
BANK TWO-GENERAL CONFIGURATION
7
6
FMD (4)
0
0
GIR!BANK
(21)
0
BANK
Pointer
bit 1
Regleter
TMD(3)
IMD (1)
BANK
Pointer
bit 0
RMD (7)
0
Control
9-bit
Character
Character
Echo Disable Length
Error
Echo
Disable
0
0
3
2
0
0
Active
Block Int
bit 2
Transmit Mode
0
ACR1 (6)
RIE (17)
4
5
Rx FIFO Threshold
0
0
1
Address Default
Tx FIFO Threshold
1
OOH
Interrupt
Active
Active
Block Int Block Int Pending
bit 0
bit 1
2
01H
Software
Parity
Mode
3
OOH
4
OCH
Stop Bit Length
Interrupt
RxFIFO ulan
Acknowledge Depth
Mode
Mode
Select
Loopbackor
Echo Mode
of Operation
Address or Control Character 1
Address!
Control
Character
Recognition
Interrupt
Enable
Address!
Control
Character
Match
Interrupt
Enable
Address!Control
Character Mode
Break
Terminate
Interrupt
Enable
Break
Detect
Interrupt
Enable
Framing
Error
Interrupt
Enable
Disable
DPLL
Sampling Start bit
Window Sampling
Mode
Mode
5
OOH
Parity
Error
Interrupt
Enable
Overrun
Error
Interrupt
Enable
0
6
1EH
0
0
0
7
OOH
BANK THREE-MODEM CONFIGURATION
Register
7
6
5
4
3
2
1
0
Address
Default
CLCF(8)
RxClock
Mode
RxClock
Source
TxClock
Mode
TxClock
Source
0
0
0
0
0
OOH
BACF(9)
0
0
0
0
BRGA
Mode
0
0
1
04H
BRGA
Clock
Source
BBL (13)
BRGB LSB Divide Count (DLAB = 1)
0
05H
BBH (14)
BRGB MSB Divide Count (DLAB = 1)
1
OOH
2-54
intJ
82510
BANK THREE-MODEM CONFIGURATION (Continued)
Register
7
6
GIR/BANK
(21)
0
BANK
Pointer
bit 1
BBCF(10)
PMD (15)
BRGB Clock Source
5
4
BANK
Pointer
bitO
0
0
0
3
Active
Block Int
bit 2
0
DCDI/ClKI DCDI/ClKI DSR/TAI DSR/TAI RIISClK
aUT1
Direction
aUT 1
Function
aUTO
aUTO
Direction Function
MIE(19)
0
0
0
0
TMIE (18)
0
0
0
0
Function
2
Active
Block Int
bit 1
1
Active
Block Int
bit 0
0
Interrupt
Pending
Address Default
2
01H
BRGB
Mode
0
0
3
84H
DTR/TB
Function
0
0
4
FCH
5
OFH
6
OOH
DCDState RI State
DSR State CTS State
Change Int Change Int Change Int Changelnt
Enable
Enable
Enable
Enable
0
0
TimerB
Interrupt
Enable
Timer A
Interrupt
Enable
CONFIGURATION
These read/write registers are used to configure the device. They may be read at anytime; however, they may
be written to only when the device is idle. Typically they are written to only once after system power up. They
are set to default values upon Hardware or Software Reset (Default Wake-Up Mode). The default values are
chosen so as to allow the 82510 to be fully software compatible with the IBM PC Async Adapter (INS 8250Al
16450) when in the default wakeup mode. The 82510 can operate in the High Performance mode by programming the configuration registers as necessary.
The configuration options available to the user are listed below.
Table 11. Configuration Options
Interrupt Acknowledge Mode
• Automatic
• Manual
Receive
• Sampling Window Size
• Start Bit Detection Mode
• DPLL Disable/Enable
""LAN (8051)
Address Recognition
• Manual, Semi-Automatic,
Automatic
Diagnostics
• Loopback
• Remote
• Local
• Echo
• Yes/No
• Disable Error Echo
• Disable Controll Address
Char. Echo
FIFO
• RX FIFO Depth
• RX, TX Threshold
Clock Options
• RX, TX Clock Mode
• 1X
• 16X
• RX, TX Clock Source
• SRGA
• BRGB
• BRGAIB Operation Mode
• Timer
• BRG
• BRGAIB Divide Count
• BRGAIB Source
• Sys Clock
• SCLK Pin
• BRGA Output (BRGB
Only)
2-55
Control Character
Recognition
• None
• Standard
• ASCII
• EBCDIC
• Two User Programmed
TX Operation
• RTS/CTS Control
Manual, Semi-Automatic,
Automatic
• Parity Mode
• Stop Bit Length
• Character Size
I/O Pins
• Select Function for Each
Multifunction Pin
• Select Direction for Multifunction Pin (If Applicable)
82510
1. IMD-INTERNAL MODE REGISTER
~ I III
).ILM - ).ILAN MODE
Rf"D - RxFIFO DEPTH
~
lAM - INTERRUPT ACKNOWLEDGE MODE
76151413121~O
RESERVED
LEM - LOOBACK/ECHO
....---~
IM~lnternal
This register defines the general device mode of operation. The bit functions are as follows:
7-4:
Reserved
lAM:
Interrupt Acknowledge Mode Bit
ULM:
uLAN Mode
o1-
Normal Mode
uLAN Mode
This bit, enables the 82510 to recognize and/or
match address using the 9-bit MCS-51 asynchronous protocol.
LEM:
Loopback/Echo Mode Select
o-
Manual acknowledgement of pending interrupts
1 - Automatic acknowledgement of
pending interrupts (upon CPU service)
This bit selects the mode of loopback operation, or
the mode of echo operation; depending upon which
operation mode is selected by the Modem Control
register bit LC.
This bit, when set, configures the 82510 for the automatic acknowledge mode. This causes the 82510
INT line to go low for two clock cycles upon service
of the interrupt. After two clock cycles it is then updated. It is useful in the edge triggered mode. In
manual acknowledgement mode the CPU must explicitly issue a command to clear the INT pin. (The
INT pin then goes low for a minimum of two clock
cycles until another enabled status register bit is
set.)
RFD:
In loopback mode (Modem Control register bit
LC = 1) it selects between local and remote loopback.
o1-
Local Loopback
Remote Loopback
In echo mode (Modem Control register bit LC = 0) it
selects between echo or non-echo operation.
Receive FIFO Depth
o1-
290116-15
Mode Register
0 - No Echo
1 - Echo Operation
Four Bytes
One Byte
This bit configures the depth of the Rx FIFO. With a
FIFO depth of one, the FIFO will act as a 1-byte
buffer to emulate the 8250A.
2-56
82510
2. LCR-LINE CONFIGURE REGISTER
DlAB
SBK - SET BACK
PARITY [
ClD} CHARACTER
Cll lENGTH
::~
a...._ _• SBlD - STOP BIT lENGTH
....- - -....
PMD ...._ _ _ _-...1
290116-16
LCR-Llne Configure Register
This register defines the basic configuration of the
serial link.
Table 13. Stop Bit Length
DLAB-Dlvlsor Latch Access Bit-This bit, when
sE!lt, allows access to the Divisor Count registers
BAl,BAH;BBl,BBH registers.
SBK-Set Break Bit-This bit will force the TxD pin
low. The TxD pin will remain low (regardless of all
activities) until this bit is reset.
PM2.
PM1
Function
0
X
X
X
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
No Parity
Odd Parity
Even Parity
High Parity
low Parity
Software Parity
1
1
SBLO
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
1
1
Stop Bit Length
16X
1X
4/4
6/4 or 8/4*
3/4
4/4
5/4
S/4
7/4
8/4
-1
1
1
1
1
2
"6/4 if character length is 5 bits; else 814
CLO-Cl1-Character Length Bit....These bits,
together with the Transmit Mode register bit NBCL,
define the character length. See Table 14.
Table 12. Parity Modes
SPF
SBL1
0
1
1
1
1
PM2-PMo-:.Parlty Mode Bits-These three bits
combine with the SPF bit of the Transmit Mode register to define the various parity modes. See Table
1~
-
PMO
SBL2
Table 14. Character Length
NBCl
SBLO-Stop Bit Length-This bit, together with
SBl1 and SBl2 bits of the Transmit Mode register,
defines the Stop-bit lengths for transmission. The Rx
machine can identify 3/4 stop bit or more. See Table
13.
2-57
,Cl1
CLO
0
,0
0
0
0
0
0
1
1
0
1
0
0
1
1
Chara~ter
Length
5 BITS
SBITS
7 BITS
8 BITS
9 BITS
inter
82510
3. TMD-Transmit Machine Mode Register
EED - ERROR ECHO' DISABLE
'" -"'''''V'''"'''
"'0 .,,""
NBCl - NINTH BIT CHAR lENGTH
21'I+H~
'
,
1111
'
.Tml
SBll - STOP BIT lENGTH
'''' -""""'''''"
. SPF - S!W PARITY
TmO
TRANSMIT MODE
290116-17
TMD-Transmit Machine Mode Register
This register together with the Line Configure Register defines the Tx machine mode of operation.
01-Reserved
EED-Error Echo Disable--Disables Echo of characters received with errors (valid in echo mode
only).
1O-Semi-Automatic Mode-In this mode the
82510 transmits only when CfS input is active. The
82510 activates the RTS output as long as transmission is enabled.
CED-Control Character Echo Disable-Disables
Echo of characters recognized as control characters
(or address characters in uLAN mode). Valid in echo
mode only.
11-Automatlc Mode-In this mode the 82510
transmits only when CTS input is active. The RTS
output is activated only when transmission is enabled and there is more data to transmit.
NBCl-Nine-Blt length-This, bit, coupled with
LCR (CLO, CL 1), selects Transmit/Receive character length of nine bits. See Table 14.
SPF-Software Parity Force-This bit defines the
parity modes along with the PMO, PM 1, and PM2 bits
of the LCR register. When software parity is enabled
,the software must determine the parity .bit through
the TxF register on transmission, or check the parity
bit in RxF upon reception. See Table 12.
TM1-TMo-Transmit Mode-These bits select
one of three modes of control over the CTS and
RTS lines.
SBl2-8Bl i-Stop Bit length-These bits, together with the SBlO bit of the LCR register define
the stop bit length. See Table 13.
Oo-Manual Mode-In this mode the CPU has full
control of the Transmit operation. The CPU has to
explicitly enable/disable transmission, and activate/
check the RTS/CTS pins.
2-58
intJ
82510
4. FMD-FIFO MODE REGISTER
~ I III
76151413121~O
RESERVED
RECEIVE FIFO [RFT1
THRESHOLD RFTO
+-___...J
~~~}
TxFlFO THRESHOLD
} RESERVED
290116-18
FMD-FIFO Mode Register
This register configures the Tx and Rx FIFO's
threshold levels-the occupancy levels that can
cause an interrupt.
cated by these bits the Rx FIFO Interrupt is activated.
3-2-Reserved
7-6-Reserved
TFT1-TFTo-Transmlt FIFO Threshold-When
the TX FIFO occl,lpancy is less than or equal to the
level indicated by these bits the Tx FIFO Interrupt is
activated.
RFT1-RFTo-Recelve FIFO Threshold-When
the Rx FIFO occupancy is greater than the level indi-
5. ACRo-ADDRESS/CONTROL CHARACTER REGISTER 0
290116-47
ARCo-Address/Control Character Register 0
This register contains a byte which is compared to
each received character. The exact function depends on the configuration of the IMD register.
character must be right justified and the leading bits
be filled with zeros.
In uLAN mode this register contains the eight-bit station address for recognition. In this mode only incoming address characters (Le., characters with address bit set) will be compared to these register. The
PCRF bit in the RECEIVE STATUS register will be
set when an Address or Control Character match
occurs.
In normal mode this register may be used to program a special control character; a matched character will be reported in the RECEIVE STATUS register. The maximum length of the control characters is
eight bits. If the length is less than eight bits then the
6. ACR1-ADDRESS/CONTROL CHARACTER REGISTER 1
290116-48
ARC1-Address/Control Character Register 1
NOTE:
This register is identical in function to ACRO.
2-59
inter
82510
7. RMD-RECEIVE MACHINE MODE REGISTER
~LA~;~N~~g~ [:~~~
~
76151413121;~
11.11
]RESERVED
DISABLE DPLL - DPD ~---SAMPLING WINDOW - SWM MODE
START BIT SAMPLING MODE
290116-19
RMD-Recelve Machine Mode Register
This register defines the Rx Machine mode of operation.
11-Reserved
In normal Mode: selects the mode of Standard Set
Control Character Recognition (programmed control
characters are always recognized).
00- No Standard Set Control Characters Recognized.
01- ASCII Control Characters
(00H-1 FH + 7FH).
10- Reserved.
11- EBCDIC Control Character Recognized
.(OOH - 3FH).
uCMO, uCM1-uLAN/Control Character RecognitionMode-ln normal mode it defines the Control
Character recognition mode. In ulan mode they define modes of address recognition.
In uLAN mode: selects the mode of address recognition.
Oo-Manual Mode-Rx Machine reports reception
of any address character, via CRF bit of RECEIVE
STATUS register, and writes it to the Rx FIFO.
DPD-Disable Digital Phase Locked Loop-When
set, disables the DPLL machine. (Note: using the
DPLL in a very noisy media, may increase the error
rate.)
01-Semi-Automatic Mode-Operates the same
as Manual Mode but, in addition, the Rx Machine
OPENS (unlocks) the Rx FIFO upon reception of any
address characters. Subsequent received characters will be written into the FIFO. (Note: it is the user's responsibility to LOCK the FIFO if the address
character does not match the station's address.)
SWM-Sampling Window Mode-This bit controls
the mode of data sampling:
O-Small Window, 3/16 sampling.
1-Large Window, 7/16 sampling.
1O-Automatic Mode-The Rx Machine will OPEN
(unlock) the Rx FIFO upon Address Match. In addition the Rx Machine LOCKs the Rx FIFO upon recognition of address mismatch; i.e., it controls the
flow of characters into the Rx FIFO depending upon
the results of the address comparison. If a match
occurs it will allow characters to be sent to the FIFO;
if a mismatch occurs it will keep the characters out
of the FIFO by LOCKING it.
SSM-Start Bit Sampling Mode.,....This bit controls
the mode of Start Bit sampling.
0- Majority Voting for start bit. In this mode a majority of the samples determines the bit.
1-ln this mode if one of the bit samples is not
'0', the start bit will not be detected.
2-60
intJ
82510
8. CLCF-CLOCKS CONFIGURE REGISTER
Rx CLOCK MODE- RxCM
~76 111411
5
Rx CLOCK SOURCE - R x C S '
TxClOCK MODE- TxC'" ...
----....
Tx elK SOURCE - TxCS
3
1
1
211
~o 1
RESERVED
' -
+----......
290116-20
CLCF-Clocks Configure Register
TxCM-Transmit Clock Mode-This bit selects the
mode of the Transmit Data Clock, which is used to
clock out the Transmit Data.
0-16X Mode
1- 1X Mode. In this mode the Transmit data is
synchronous to the Serial Clock; supplied via
the SCLK pin.
This register defines the Transmit and Receive Code
modes and sources.
RxCM-Rx Clock Mode-This bit selects the mode
of the receive clock which is used to sample the
received data.
0-16X Mode.
1- 1X Mode. In this mode the receive data must be
synchronous to the Rx Clock; supplied via the
SCLK pin.
TxCS-Transmit Clock Source-Selects the
source of internal Transmit Clock in case of 16X
mode.
O-BRGB Output.
1-BRGA Output.
RxCS-Rx Clock Source-This bit selects the
source of the internal receive clock in the case of
16X mode (as programmed by the RxCM bit above).
O-BRGB Output
1-BRGA Output
9. BACF-BRGA CONFIGURATION REGISTER
.~
eeoc,
= 2
~I"'I+I~
w"'~-~~ IIII ,''ow,,
RESERVED
RESERVED
RESERVED
RESERVED
BAM- BRGA MODE
RESERVED
290116-21
BACF-BRGA Configuration Register
BAM-BRGA Mode of Operation-Selects between the Timer mode or the Baud Rate Generator
Mode.
This register defines the BRGA clock sources and
the mode of operation.
BACS-BRGA Clock Source-Selects the input
clock source for Baud Rate Generator A.
0- Timer Mode (in this mode the input clock
source is always the system clock).
1- Baud Rate Generator Mode
O-System Clock
1-SCLK Pin
This bit has no effect if BRGA is configured as a
timer.
2-61
inter
82510
10. BBCF-BRGB CONFIGURATION REGISTER
~I+I+I~ ~""rn
-,;~~(~~ ;IIII}
.
. ..
. [
RESERVED
.
•
'.'
.
BBt.f .. BRGB MODE
RESERVED
290116-22
BBCF-BRGB Configuration Register
This register defines the BAGB clock sources and
mode of operation. (Note: BAGB can also take its
Input Clock from the output of BAGA.)
... '.,
10- BAGA Output
11- Aeserved
BBM-BAGB Mode of Operation.
BBCS1, BBCSO-These two bits together define the
input Clock Sources for BAGB. These bits have no
effect when in the timer mode.
00- System Clock
01- SCLK Pin
0- Timer Mode (In this mode the input clock
source is always the system clock.)
1- BAG Mode
11. BAl-BRGA DIVIDE COUNT lEASTSIGNIFfCANT BYTE
290116-49
BAl-BRGA Divide Count low Byte
This register contains the least significant byte of the BAGA divisor/count.
12. BAH-BRGA DIVIDE COUNT MOST SIGNIFICANT BYTE
.~#pTj'jT§~
290116-50
BAH-BRGA Divide Count. High Byte
This register contains the most significant byte of the SAGA divisor/count.
13. BBl-BRGB DIVIDE COUNT lEAST SIGNIFICANT BYTE
290116-51
BBl-BRGB Divide Count low Byte
This register contains the least significant byte of the BAGB divisor/count.
2-62
inter
82510
14. BBH-BRGB DIVIDE COUNT MOST SIGNIFICANT BYTE
290116-52
BBH-BRGB Divide Count High Byte
This register contains the most significant byte of the BRGB divisor/count.
15. PMD-I/O PIN MODE REGISTER
~'M'"" .,,~,-
DCD/ICLK/OUT1 DIRECTION - 0100
OCO/ICLK/OUT1 FUNCTION _ OIOF
~I'I'I'I'I~
.".;
DSR/TA/OUTO FUNCTION - DTAF"
I III
}
~~ '"'~"
RESERVED
w-
RRF - RI/SCLK FUNCTION
290116-23
PMD-I/O Pin Mode Register
O-IClK (Output of the Internal System Clock).
1- OUT1 general purpose output. Controlled by
MODEM CONTROL Register
DTAD-DSR/TAlOUTO Direction.
0- Output: TA or OUTO (Dependent upon
DTAF).
1- Input: DSR.
DTAF-DSR/TAlQUTO Direction (output
mode only).
0- TA (BRGA Output or Timer A Termination
Pulse).
1- OUTO (general purpose output, controlled by
MODEM CONTROL).
RRF-RI/SClK Function
0- SClK (Receive and/or Transmit Clock)
1-RI
DTF-DTR/TB Function
0- TB (BRGB Output Clock on Timer B termination pulse depending upon the mode of
BRGB).
1-DTR
This register is used to configure the direction and
function of the multifunction pins. The following options are available on each pin.
1. Direction: Input or Output Pin.
0- Defines the Pin as an output pin (general purpose or special function).
1- Defines the pin as an input pin.
2. Function: General purpose or special purpose pin
(no effect if the pin is programmed as an Input).
0- special function output pin.
1- general purpose output pin.
DIOD-DCD/IClK/OUT1 Direction.
0- Output: IClK or OUT1 (depending on bit
DIOF)
1- Input: DCD.
DIOF-DCDIIClK/OUT1 Function (output
mode only).
2-63
inter
82510
Interrupt Masking
INTERRUPTISTATUS REGISTERS
The 82510 ~as a device enable register, GER, which
can be used to enable or mask-out any block interrupt request. Some of the blocks (Rx Machine, Modem, Timer) have an enable register associated with
their status register which can be used to mask out
the individual sources within the block. Interrupts are
enabled when programmed high.
The 82510 uses a two layer approach to handle interrupt and status generation. Device level registers
show the status of the major 82510 functional block
(MODEM, FIFO, Tx MACHINE, Rx MACHINE, TIMERS, etc.). Each block may be examined by reading
its individual block level registers. Also each block
has interrupt enable/generation logic: which may
generate a request to the built-in interrupt controller,
the interrupt requests are then resolved on a priority
basis.
16. GER-GENERAL ENABLE REGISTER
'''~,"m,"~,"_'_~: IIII 2~, - . ,~. "~''''~
RESERVED [
~I"'I'I'I~
Tx INTERRUPT ENABLE - TxlE
RFiE - Rx FIFO INTERRUPT ENABLE
TFlE - FIFO INTERRUPT ENABLE
MIE - MODEM INTERRUPT ENABLE
290116-24
GER-General Enable Register
This register enables or disables the bits of the GSR
register from being reflected in the GIR register. It
serves as the device enable register and is used to
mask the interrupt requests from any of the 82510
block (See Figure 1).
MIE-Modem Interrupt Enable.
RxIE-Rx Machine Interrupt Enable.
TFIE-Transmit FIFO Interrupt Enable.
TIE-Timers Interrupt Enable
RFIE-Receive FIFO Interrupt Enable.
TxlE-Transmit Machine Interrupt Enable.
17.RIE-RECEIVE INTERRUPT ENABLE REGISTER
76151413121~O
CONTROL/ADDRES. S RECOGNITION
CONTROL/ADDRESS MATCH
BREAK TERMINATED
~ I III
BREAK DETECTED
RESERVED
OVERRUN ERROR
PARITY ERROR
FRAMING ERROR
290116-25
RIE-Receive Interrupt Enable Register
This register enables interrupts from the Rx Machine. It is used to mask out interrupt requests generated by the status bits of the RST register.
BkDE-Break Detection Interrupt
Enable Interrupt on BkD bit of RST.
Enable-
FEE-Framing Error Enable-Enable Interrupt on
FE bit of RST.
CRE-Control/uLAN Address Character Recognition Interrupt Enable.-Enables Interrupt when
CRF bit of RST register is set.
PEE-Parity Error Enable-Enable Interrupt on PE
bit of RST.
PCRE-Programmable Controll Address Character Match Interrupt Enable.-Enables Interrupt on
PCRF bit of RST.
OEE-overrun Error Enable-Enable Interrupt on
OE bit of RST.
BkTe-Break Termination Interrupt Enable.
2-64
intJ
82510
18. TMIE-TIMER INTERRUPT ENABLE REGISTER
290116-26
TMIE-Tlmers/lnterrupt Enable Register
This is the enable register for the Timer Block. It is
used to mask out interrupt requests generated by
the status bits of the TMST register.
TBIE-Timer B Expired Interrupt
Enables Interrupt on TBEx bit of TMST.
Enable-
TAlE-Timer A Expired Interrupt
Enables Interrupt on TAEx bit of TMST.
Enable-
19. MIE-MODEM INTERRUPT ENABLE REGISTER
290116-27
MIE-Modem Interrupt Enable Register
CTSE-Delta CTS Interrupt Enable-Enables Interrupt on DCTS bits of MODEM STATUS.
This register enables interrupts from the Modem
Block. It is used to mask out interrupt requests generated by the status bits of the MODEM STATUS
register.
STATUS/INTERRUPT
DCDE-Delta DCD Interrupt Enable-Enables Interrupt on DDCD bit of MODEM STATUS.
The 82510 has two device status registers, which
reflect the overall status of the device, and five block
status registers. The two device status registers,
GSR and GIR, and supplementary in function. GSR
reflects the interrupt status of all blocks, whereas
GIR depicts the highest priority interrupt only. GIR is
updated after the GSR register; the delay is of approximately two clock cycles.
RIE-Delta RI Interrupt Enable-Enables Interrupt
on DRI bit of MODEM STATUS.
DSRE-Delta DSR Interrupt Enable-Enables Interrupt on DSR bit of MODEM STATUS.
2-65
intJ
82510
20. GSR-GENERAL STATUS REGISTER
~I'I'I'I'I~
"'" OIT""~::
RESERVED
.
RESERVED
Tx MACHINE INTERRUPT
, ' '"' ' '~"~
Rx FIFO INTERRUPT
Tx FIFO INTERRUPT
1111 :
MODEM INTERRUPT
290116-28
GSR-General Status Register
This register reflects all the pending block-level Interrupt requests. Each bit in GSR reflects the status
of a block and may be individually enabled by GEA.
GER masks-out interrupts from GIR; it does not
have any effect on the bits in GSA. The only way
that the bits can be masked out in GSR (Le., not
appear in GSR) is if they are masked out at the lower
level.
MIR-Modem Interrupt 'Request-This bit, if set,
indicates an interrupt from the Mod~m Module. (As
reflected in MODEM STATUS.)
RxlR-Receive Machine Interrupt Request-(As
reflected in RST.)
TFIR--Transmit FIFO Interrupt Request-Tx
FIFO occupancy is below or equal to threshold.
TIR-Timers Interrupt Request-This bit indicates
that one of the timers has expired. (See TMST)
RFIR-Receive FIFO Interrupt Request-Rx FIFO
Occupancy is above threshold.
.
TxlR-Transmit Machine Interrupt RequestIndicates that the Transmit Machine is either empty
or disabled (Idle).
21. GIR/BANK-GENERAL INTERRUPT REGISTER/BANK REGISTER
;jg1+I'PI~ ~:::"~
"'~:~::
BANKO .
RESERVED
1.11 1 :
:,:-
".,,"'
B11] BLOCK
BI2 INTERRUPT
.
290116-29
General Interrupt Register/Bank Register
This register holds the highest priority enabled pending interrupt from GSA. In addition it holds a pointer
to the current register segment. Writing into this register will update only the BANK bits.
101:
100:
011:
010:
001:
000:
BANK1, BANKO-Bank Pointer Bits-These two
bits point to the currently accessible register bank.
The user can read and write to these bits. The address of this register is always two within all four
register ba~ks.
Timer Interrupt (highest priority)
Tx Machine Interrupt
Rx Machine Interrupt
Rx FIFO Interrupt
Tx FIFO interrupt
Modem Interrupt (lowest priority)
lPN-Interrupt Pending-This bit is active low. It
indicates that there is an interrupt pending. The interrupt logic asserts the INT pin as soon as this bit
goes active. (Note: the GIR register is continuously
updated; so that, while the user is serving one interrupt source, a new interrupt with higher priority may
enter GIR and replace the older interrupt.)
B12, B11, BIO,-Interrupt Bits 0-2-These three
bits reflect the highest priority enabled pending interrupt from GSA.
2-66
intJ
825.10
22. LSR-LINE STATUS REGISTER
~~"mrn' = II %
"~., .o .
RESERVED
TxST
~I'I'I'I'I~
I I
TFST
Rx fiFO INT.
OVERRUN ERROR
PARITY ERROR
290116-30
LSR-Llne Status Register
This register holds the status of the serial link. It
shares five of its bits with the RST register (BkD, FE,
PE, OE, and RFIR). When this register is read, the
RST register (BITS 1-7) and LSR register (BITS 14) are cleared. This register is provided for compatibility with the INS8250A.
TFIR bit of GSR by writing a character to Tx FIFO, or
drop TFIE bit of GER (Disable Tx FIFO).
TxSt-Transmit Machine Status Blt-Same as
TxlR bit of GSR register. If high it indicates that the
Transmit Machine is in Idle State. (Note: Idle may
indicate that the TxM is either empty or disabled.
FE-Framing Error Detected-5ee FE bit in RST
register for a full explanation. The FE bit in RST register is the same as this bit.
Bkd-Break Detected-See Bkd bit in RST register
for full explanation. The BkD bit in RST register is
the same as this bit.
PE-Parlty Error Detected-See PE bit in RST
register for full explanation. The PE bit in RST register is the same as. this bit.
TFSt-Transmlt FIFO StatuS-Same as TFIR bit of
GSR. It indicates that the Transmit FIFO level is
equal to or below the Transmit FIFO Threshold.
There are two ways to disable the transmit FIFO
status from being reflected in GIR:
1. Writing a "0" to the TFIE bit of the GER register
2. Dynamically by using the Tx FIFO HOLD INTERRUPT logic. When the Tx FIFO is in the
Hold State, no interrupts are generated regardless of the TFIR and TFIE bits.
OE-overrun Error-See OE bit in RST register for
full explanation. The OE bit in RST register is the
same as this bit.
RFIR-Recelve FIFO Interrupt Request-This bit
is identical to RFIR bit of GSR. It indicates that the
RX FIFO level is above the Rx FIFO Threshold. This
bit is forced LOW during any READ from the Rx
FIFO. A zero written to this bit will acknowledge an
Rx FIFO interrupt.
The Transmit FIFO enters the Hold State when the
CPU reads the GIR register and the source of the
interrupt is Tx FIFO. To Exit, the CPU must drop the
2-67
inter
82510
23. RST-RECEIVE MACHINE STATUS REGISTER
~76ISI413121~O
,
ADDRESS/CONTROL CHAR. RCVD.
ADDRESS/CONTROL CHAR. MATCH
I'
II'
1
Rx FIFO INT.
OVERRUN ERROR
'
BREAK TERMINATED - '
•
-
BREAK DETECTED
PARITY ERROR
FRAMING ERROR
290116-31
RST-Receive Machine Status Register
This register displays the status of the Receive Ma·
chine. It reports events that have occurred since the
RST was cleared. This register is cleared when it is
read except for BITO, Rx FIFO interrupt. Each bit in
this register, when set, can cause an interrupt. Five
bits of this register are shared with the LSR register.
In normal Mode: indicates that a character which
matches the registers ACRO or ACR 1 has been
received.
BkT-Break Terminated-This bit indicates that a
break condition has been terminated.
CRF-Control/ Address Character Received-
BkD-Break Detected-This bit indicates that a
When enabled, this bit can cause an interrupt if a
control character or address character is received.
Break Condition has been detected, i.e., RxD input
was held low for one character frame plus a stop
BIT.
In uLAN Mode: indicates that an address charac·
ter has been received.
In normal Mode: indicates that a standard control
character (either ASCII or EBCDIC) has been received.
FE-Framing Error-This bit indicates that are·
ceived character did not have a valid stop bit.
PE-Parlty Error-Indicates that a received character had a parity error.
PCRF-Programmed Controll Address Character
Received-This bit, when enabled, will cause an interrupt when an address or control character match
occurs.
OE-overrun Error-Indicates that a received
character was lost because the Rx FIFO was full.
RFIR-Receive FIFO Interrupt Request-5ame
In uLAN Mode: indicates that an address charac·
ter equal to one of the registers ACRO or ACR1
has been received.
as the RFIR bit of LSR register.
2-68
inter
82510
24. RXF-RECEIVED CHARACTER FLAGS
RESERVED
Rx CHARACTER OK - ROK
I I
~I'I'I*I~
Rx NOISY - RxN
","" '''"' "00' -'"
II
RND- RxCHAR NINTH DATA BIT
'"-
RI'E - Rx CHAR fRAMING ERROR
BREAK fLAG
"""'/00.,.",,".. ""
290116-32
RxF-Recelve Flags Register
This register contains additional information about
the character in the RXD register. It is loaded by the
Rx Machine simultaneously with the RXD register.
A control Character-in normal Mode.
An Address Character in uLAN Mode.
RFE-Recelve Character Framing ErrorIndicates that no Stop bit was found for the character in RXD.
ROK-Recelved Character OK-This bit indicates
that the character in RXD no parity or framing error.
The parity error is not included in the s/w parity
mode.
NOTE:
A Framing Error will be generated for the first character of the Break sequence.
RxN-Received Character Noisy-The character
in RXD was noisy. This bit, valid only in 16X sampling mode, indicates that the received character
had non-identical samples for at least one of its bits.
RND-Nlnth Bit of Received Character-The
most significant bit of the character in RXD is written
into this bit. This bit is zero for characters with less
than nine bits.
RPE-Recelve Character Parity Error-This bit indicates that the RxD character had a Parity Error.
However, in S/W Parity mode it holds the received
parity bit as is.
BKF-Break Flag-Indicates that the character is
part of a "break" sequence.
ACR-Address/Control Character Marker-This
bit indicates that the character in RXD is either:
25. FLR-FIFO LEVEL REGISTER
[~~; IIII :
RESERVED
Rx 1'11'0
OCCUPANCY
LEVEL
~I'I'I'I'I~
TI'LO
Tx 1'11'0
RI'L 1
IT" lOCCUPANCY
TF"L2 LEVEL
RF"LO
RESERVED
290116-33
FLR-FIFO Level Register
This register holds the current Receive and Transmit
FIFO occupancy levels.
pancy of the Rx FIFO. The valid range is zero (000)
to four (100).
RFL2, RFL 1, RFLD-Receive FIFO Level of Occupancy-These three bits indicate the level of Occu-
TFL2, TFL 1, TFLD-Transmit FIFO Level of Occupancy-These three bits indicate the level of occupancy in the transmit FIFO. The valid range is zero
(000) to four (100).
2-69
inter
82510
26. TMST-TIMER STATUS REGISTER
.~." ~I'I+I'I~
I III "".. ~ffi"
RESERVED
GATE B STATE
TIMER B EXPIRED
RESERVED
GATE A STATE
RESERVED
290116-34
TMST-Timer Status Register
This register holds the status of the timers. Bits
TBEx and TAEx generate interrupts which are reflected in bit TIR of GSA. Bits GBS and GAS just
display the counting status, they do not generate interrupts.
GAs-Gate-A State-This bit does not generate
an interrupt. It reflects the state of the software gate
of Timer A, as written through the TMCR register.
O-counting disabled
1-counting enabled
GBs-Gate B State-This bit does not generate an
interrupt. It indicates the counting state of the software gate of Timer B, as written through the TMCR
register.
O-counting disabled
1-counting enabled
TBEx-Timer B Expired-When Set generates an
interrupt through TIR bit. of GSA. Indicates that Timer B count has expired. This bit is set via the terminal
count pulse generated by the timer when it terminates counting.
TAEx-Timer A Expired-Same as TBEx except it
refers to Timer A.
27. MSR-MODEM/I/O PINS REGISTER
~ ~,', ~""I'I'I~ ~.~~~~.
...
COMPLEMENT
!iCO
COMPLEMENT DSR
'
IIII
COMPLEMENT CTS
STATE CHANGE
C'fS
(H --> L) RI
STATE CHANGE DCD
290116-35
MSR-Modem/I/O Pins Status Register
DRI-Delta RI-Indicates that there was a high-tolow transition on the RI input pin since the register
was last read.
This register holds the status of the Modem input
pins (CTS, DCD, DSR, RI). It is the source of interrupts (MSR 0-3) for the MIA bit of GSA. If any of the
above inputs change levels the appropriate bit in
MODEM STATUS is set. Reading MODEM STATUS
will clear the status bits.
DDSR-Delta DSR-Indicates that the DSR input
pin has changed state since this register was last
read.
DCDC-DCD Complement-Holds the complement of the DCD input pin if programmed as an input
in PMD.
DCT5-Delta CT5-lndicates that the CTS input
pin has changed state since this register was last
read.
DRIC-Holds the complement of the RI input pin if
programmed as an input in PMD.
COMMAND REGISTERS
DSRC-DSR Complement-Holds the complement
of the DSR input pin if configured as an input in
PMD.
The command registers are write only; they are used
to trigger an operation by the device. Once the operation is started the register is automatically reset.
There is a device level register as well as four block
command registers. It is recommended that only one
command be issued during a write cycle.
CTSC-CTS Complement-Holds the complement
of the CTS pin.
DDCD-Delta DCD-Indicates that the DCD input
pin has changed state since this register was last
read.
2-70
inter
82510
28. ICM-INTERNAL COMMAND REGISTER
~ I III
76151413121~O
RESERVED [
•
•
S!W RESET-SRST
:~~E~~:ER
DOWN
STC-STATUS CLEAR
INrA-INTERRUPT ACKNOWLEDGE
290116-36
ICM-Intemal Command Register
clocks; afterwards, the INT pin may again go active if
other enabled interrupts are pending. This command
is provided for the Manual Acknowledge mode of
the 82510.
This register activates the device's general functions.
SRST-Device Software RESET-Causes a total
device reset; the effect is identical to the hardware
reset (except for strapping options). The reset lasts
four clocks and puts the device into the Default
Wake-up Mode.
StC-Status Clear-Glears the following status registers: RST, MSR, and TMST.
PDM-Power Down-This command forces the device into the power-down mode. Refer to the functional description for details;
INTA-Interrupt Acknowledge-This command is
an explicit acknowledgement of the 82510's Interrupt request. It forces the INT pin inactive for two
29. TCM-TRANSMIT COMMAND REGISTER
290116-37
TCM-Transmlt Command Register
This register controls the operation of the Transmit
Machine.
TxEN-Transmit Enable-Enables Transmission
by the Transmit Machine.
FTM-Flush Transmit Machine-Resets the
Transmit Machine logic (but not the registers or
F!FO) and enables transmission.
TxDi-Transmit Disable-Disables transmission. If
transmission is occurring when this command is issued the Tx Machine will complete transmission of
the current character before disabling transmission.
FTF-Flush Transmit FIFO-Ciears the Tx FIFO.
2-71
intJ
82510
30. RCM-RECEIVE COMMAND REGISTER
.
rL~H ~H,"E-'~
RECEIVE ENABLE'- RxE
Rx DISABLE" RxDI,
~I+I'I'I§
b
FLUSH Rx 1'"11'"0 - I'"RF
IIII
,
~-_ ~WO
} RESERVED
LRI'" - LOCK Rx 1'"11'"0
290116-38
RCM-Receive Command Register
This' register controls the operation of the Rx machine.
FRF-Flush Receive FIFO-Ciears the Rx FIFO.
LRF-Locks Rx FIFO-Disables the write mechanism of the RxFIFO so that characters subsequently
received are not written to the Rx FIFO but are lost.
However, reception is not disabled and complete
status/event reporting continues. (This command
may be used in the uLAN mode to disable loading of
characters into the Rx FIFO until an address match
is detected.)
RxE-Recelve Enable-Enables the reception of
characters.
RxDI-Recelve Disable-Disables reception of
data on RXD pin.
FRM-Flush Receive Machine-Resets the Rx
Machine logic (but not registers and FIFOs), enables
reception, and unlocks the receive FIFO.
ORF-open (Unlock) Rx FIFO-This command'enabies or unlocks the write mechanism of the Rx
FIFO.
31. TMCR-TIMER CONTROL REGISTER
290116-39
TMCR-Timer Control Register
This register controls the operation of the two 82510
timers. It has no effect when the timers are configured as baud-ratEl generators. TGA and TGB are
not reset after commahd execution.
1-enables counting
O-disables counting
STB-Start Timer B-This command triggers'timer
B. At terminal count a status bit is set in TMST
(TBEx).
TGB-Tlmer-B Gate-This bit serves as a gate for
Timer B operation:
STA-Start Timer A-This command triggers timer
A. At terminal count a status bit is set in TMST
(TAEx).
1-enables counting
O-disables counting
TGA-Timer-A Gate-This bit serves as a gate for
Timer·A operation:
2·72
inter
82510
32. MCR-MODEM CONTROL REGISTER
ournou~",:':'ou:; IIII :;:;":~
[
~1"'1'121~
LOOPBACK CONTROL - LC
OTR - OTR OUTPUT BIT
'0
OUT2 - OUT2 OUTPUT BIT
290116-40
MCR-Modem Control Register
This register controls the modem output pins. With
multi-function pins it affects only the pins configured as general purpose output pins. All the output
pins invert the data, i.e. their output will be the complement of the data written into this register.
OUT1-OUT1 Output Bit-This bit controls the
QUT1 pin. The output signal is the complement of
this bit.
RTS-RTS Output Bit-This bit controls the RTS
pin. The output signal is the complement of this bit.
OUTo--oiJ"fii Output Bit-This bit controls the
OUTO pin. The output signal is the complement of
this bit.
DTR-DTR Output Bit-This bit controls the OTR
pin. The output signal is the complement of this bit.
LCB Loopback Control Bit-This bit puts the
82510' into loopback mode. The particular type of
loopback is selected via the IMO register.
DATA REGISTERS
The data registers hold data or other information
and may be accessed at any time.
OUT2-oUT2 Output Bit-This bit controls the
OUT2 pin. The output Signal is the complement of
this bit.
33. TXD-TRANSMIT DATA REGISTER
290116-53
TXD-Transmit Data Register
This register holds the next data byte to be pushed
into the Transmit FIFO. For character formats with
more than eight bits of data, or with additional components (S/W Parity, Address Marker Bit) the additional data bits should be written into the TxF regis-
ter. When a byte is written to this register its contents, along with the contents of the TxF register,
are pushed to the top of the Transmit FIFO. This
register is write only.
2-73
inter
82510
34. TXF-TRANSMIT FLAGS REGISTER
290116-41
TxF-Transmit Flags Register
This register holds some additional components of
the next character to be pushed into the Tx FIFO.
The contents of this register are pushed into the Tx
FIFO with the Transmit Data register whenever the
TxO register is written to by the CPU.
SP-Software Parity Bit-This bit is transmitted in
S/W parity mode as the character's parity bit.
OS-Ninth Bit of Data-In nine-bit character length
mode this bit is transmitted as the MSB (08) bit.
uLAN-uLAN Address Marker Bit-This bit is
transmitted in uLAN mode as the address marker
bit.
35. RXD"":RECEIVE DATA REGISTER
290116-54
RXD-Receive Data Register
This register holds the earliest received character in
the Rx FIFO. The character is right justified and
leading bits are zeroed. This register is loaded by the
Rx Machine with the first received character. Reading the register causes the next register from the Rx
FIFO to be loaded into RxO and RxF registers.
2-74
82510
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ...... O·C to 70·C
+ 150·C
+ 0.5V
Voltage on Vee Pin (w.r.t. Vss) ...... -0.5V to + 7V
Storage Temperature ............ - 65· to
Voltage on any Pin (w.r.t. VSS) -0.5V to Vee
Power Dissipation ....................... 300 mW
D.C. SPECIFICATIONS
D.C. CHARACTERISTICS
Symbol
Vil
(TA = O· to 70·C, Vee = 5V ± 10%)
Parameter
Input Low Voltage
Notes
Min
Max
Units
(1 )
-0.5
0.8
V
2.0
Vee- 0.5
V
0.45
V
IlA
VIH
Input High Voltage
(1 )
VOL
Output Low Voltage
(2), (9)
VOH
Output High Voltage
(3), (9)
III
Input Leakage Current
(4)
±10
IlO
3-State Leakage Current
(5)
±10
IlA
Icc
Power Supply Current
(6)
3.8
mA/MHz
Ipd
Power Down Supply
(7)
2
mA
ISTBY
Standby Supply Current
(10)
500
IlA
IOHA
RTS, DTR Strapping Current
(11)
0.4
mA
lOLA
RTS, DTR Strapping Current
(12)
11
mA
Cin
Input Capacitance
(8)
10
pF
Cio
1/0 Capacitance
(8)
10
CXTAl
X1, X2 Load
V
2.4
pF
10
pF
NOTES:
1. Does not apply to elK/X1 pin, when configured as crystal oscillator input (X1).
2.@IOl=2mA.
3. @ IOH = -0.4 rnA.
4. 0 < VIN < Vee.
5. 0.45V < VOUT < (Vee - 0.45).
6. Vee = 5.5V; Vil = 0.5V (max); VIH = Vee - 0.5V (min); 35 rnA (max); Typical value = 2.5 rnA/MHz (Not Tested); Ext
1X elK (9 MHz max); IOl = IOH = O.
7. Vee = 5.5V; Vil = GND; VIH = Vee; IOl = IOH = 0; device at power down mode, clock running.
8. Freq = 1 MHz.
9. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).'
10. Same as 7, but input clock not running.
11. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH.
12. Applies only during hardware reset for clock configuration. Strapping current for logic lOW.
2-75
82510
A.C. SPECIFICATIONS
SYSTEM CLOCK SPECIFICATIONS
Symbol
Testing Conditions:
• All AC output parameters are under output load
of 20 to 100 pF, unless otherwise specified.
• AC testing inputs are driven at 2.4 for logic '1',
and 0.45V for logic '0'. Output timing measurements are made at 1.5V for both a logical '0'
and '1'.
Parameter
Min
Max
Notes
250
(2)
DIVIDE BY TWO OPTION-ACTIVE
• In the following tables, the units are ns, unless
otherwise specified.
System Interface Specificatlon-System Clock
Specification:
Tcy/2
ClK Period
54
TClCH
ClKlowTime
25
TCHCl
ClK High Time
25
TCH1CH2
ClK Rise Time
10
(1 )
TCl2Cl1
ClK Fall Time
10
(1 )
FXTAl
External Crystal
Frequency Rating
18.432
MHz
4.0
DIVIDE BY TWO OPTION-INACTIVE
The 82510 system clock is supplied via the elK pin
or generated by an on-chip crystal oscillator. The
clock is optionally divided by two. The ClK parameters are given separately for internal divide-by-two
option ACTIVE and INACTIVE.
Tcy
ClK Period
108
TClCH
ClK lowTme
54
TCHCl
ClK High Time
44
TCH1CH2
ClK Rise Time
15
(1 )
TCl2Cll
ClK Fall Time
15
(1 )
250
NOTES:
1. Rise/fall times are measured between 0.8 and 2.0V.
2. Tcy in ACTIVE divide by two option is TWICE the input·
clock period.
The system clock (after division by two, if active)
must be at least 16X the Tx or Rx baud rate (the
faster of the two).
RESET SPECIFICATION
Symbol
Parameter
Min
Max
Notes
TRSHl
Reset Width-ClK/X1 Configured to ClK
8 Tcy
(1 )
TTlRSl
RTS/OTR lOW Setup to Reset Inactive
6Tcy
(2)
TRSlTX
RTS/OTR low Hold after Reset Inactive
0
Tcy - 20
(2)
RESET ______J!
L
_________________________i=ITLRSL~-TR-S-LT-X-1---======~~~
DTR/RTS
--------------------+-------------~-------290116-43
NOTES:
1. In case of ClK/Xl configured as XI, 1 Ms is required to guarantee crystal oscillator wake-up.
2. RTS/DTR are internally driven HIGH during RESET active time. The pin should be either left OPEN or externally driven
lOW during RESET according to the required configuration of the system clock. These parameters specify the timing requirements on these pins, in case they are externally driven lOW during RESET.
The maximum spec on TRSlTX requires that the RTS/DTR pins not be forced later than TRSlTX maJdmum.
2-76
infef
82510
READ CYCLE SPECIFICATIONS
Symbol
TALAH
Parameter
Min
AD Active Width
2Tcy
Max
Notes
+ 65
TAVAL
Address/CS Setup Time to AD Active
7
TAHAX
Address/CS Hold Time after AD Inactive
0
TALDV
Data Out Valid Delay after AD Active
TCIAD
Command Inactive to Active Delay
TAHDZ
Data Out Float Delay after AD Inactive
+ 65
Tcy + 15
2Tcy
(1 )
40
NOTE:
1. Command refers to either Read or Write signals.
A2-0
CS
VALID
D7-0-------------(~~~~----------------------------------290116-44
WRITE CYCLE SPECIFICATION
Symbol
Parameter
Min
TWLWH WA Active Width
2Tcy
TAVWL Address CS Setup Time to WR Active
0
TDVWH Data in Setup Time to WA Inactive
90
TWHDX Data in Hold Time after WA Inactive
12
...
I--TWLWHA2-0
cs
~
_
TCIAO ___
TWHAX.t-_
}{
VALID
TOVWH
07-0
7
TWHAX Address and CS Hold Time after WR
TAVWL
Max Notes
+ 15
I.
.1
VALID
TWHDX
VALID
i-TCIA0..:1
\.
290116-45
NOTE:
Many of the serial interface pins have more than one function; sometimes the different functions have different timings. In
such a case, the timing of each function of a pin is given separately.
2-77
82510
SCLK PIN SPECIFICATION-16x CLOCKING MODE
Parameter
Symbol
Min
Txcy
SCLK Period
TXLXH
SCLK Low Time
93
TXHXL
SCLK High Time
93
Max
Notes
216
TXH1XH2
SCLK Rise Time
15
(1 )
TXL2XL1
SCLK Fall Time
15
(1 )
Max
Notes
NOTE:
1. Rise/fall times are measured between O.BV and 2.0V.
SCLK PIN SPECIFICATION-1x CLOCK MODE
Symbol
Parameter
Min
Txcy
SCLK Period
3500
TXLXH
SCLK Low Time
1650
TXHXL
SCLK High Time
1650
TXH1XH2
SCLK Rise Time
15
(1)
TXL2XL1
SCLK Fall Time
15
(1)
NOTE:
1. Rise/fall times are measured between O.BV and 2.0V.
RXD SPECIFICATION (1x MODE)
Symbol
SCLK
RXD
Parameter
Min
TRPW
RXD Setup Time to SCLK High
250
TRPD
RXD Hold Time After SCLK High
250
I
\
--------1 '"'. ~j..~---TRPD
Max
Notes
'''''___..J!
*:::::::::::::=
290116-46
TXD SPECIFICATION (1x MODE)
r--~-~~---------------r---~--~----~
Parameter
TXD Valid Delay after SCLK Low
REMOTE LOOPBACK SPECIFICATION
Symbol
Parameter
TRXDTXD
TXD Delay after RXD
2-7a
intJ
82510
CHAR 4
CHAR 3
CHAR 5
RXD pin
RD
pin
RST (7-0)
DOH
FLR (6-4) _ _ _-.:.._ _ _" -_ _......._ _.A__--='----\~--lr_--....::....---_t........~.a..;:;.a..::.a...:..A-:.....I'-'-
....JrI.'-______-..J
INT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
BREAK
DETECTED
INTERRUPT
RX FIFO
THRESHOLD
INTERRUPT
290116-55
Receive Logic Diagram
INT=GSR (1)
GSR (4)
TXD _ _ _.....,STR DO
02
D1
os
04
03
CHAR 1
05
STR DO
02
D4
06
STR DO
02
0.4
06
STPI'-''-'':D~,~D::;3r-'~D5~S·TP
CHAR 2
STR DO
D-4
02
01
03
CHAR 4
06
D5 STP
STR 00
02
01
0.4
03
06
05 STP
CHAR 5
290116-56
Transmit Logic Diagram
2-79
8273
PROGRAMMABLE HOLC/SOLC
PROTOCOL CONTROLLER
" CCITT X.25 Compatible
•
Programmable NRZI Encode/Decode
•
HDLC/SDLC Compatible
•
•
Full Duplex, Half Duplex, or Loop SDLC
Operation
Two Programmable Modem Control
Ports
•
Digital Phase Locked Loop Clock
Recovery
•
Minimum CPU Overhead
•
Fully compatible with 8048/8080/
8085/8088/8086/80188/80186CPUs
•
Single
•
Up to 64K Baud Synchronous Transfers
•
Automatic FCS (CRC) Generation and
Checking
•
Up to 9.6K Baud with On-Board Phase
Locked Loop
+ 5V Supply
The Intel 8273 Programmable HOLC/SOLC Protocol Controller is a dedicated device designed to support the
ISO/CCln's HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new high
performance microcomputer systems such as the MCS 188/ 186TM. A frame level command set is achieved by
a unique microprogrammed dual processor chip architecture. The processing capability supported by the 8273
relieves the system CPU of the low level real·time tasks normally associated with controllers.
REGISTERS
TxlNT RESULT
COMMAND
RxlNT RESULT
PARAMETER
TEST MODE
STATUS
RESULT
FLAG OET
OB0- 7
Pr.
CLK
JII3
PIlI
I'll
RESET
DATA
BUS
BUFFER
TiiDAcK
TKD
r.c
TxORQ
Ril!Afl(
1m
RxORQ
PAl
PA2
iiii
TxDRD _ _ _- - ,
6PLl
i'iiiiAci - - - - ,
WR
I'A4
fIi
Rx INT
rn
iiTs
OBO
TxO
PB,-4
OBI
TxC
OB2
RxC
32iACK
32'X'CLi(
R.DRQ
RTS
R.DACK
PBI _ 4
r.INT
CTS
R.INT
CO
Ri5
WR
PA 2 _ 4
READ/
WRITE
DMA/
CONTROL
lOGIC
Al
R.D
RESET
R.C
cs
ClK - - - - - - - - '
FLAG DET
INTERNAL DATA BUS
CPU INTERFACE
MODEM INTERFACE
210479-3
Figure 4. 8273 Block Diagram Showing CPU Interface Functions
2-85
inter
8273
Register Description
RxDRQ: RECEIVE DMA REQUEST
COMMAND
Requests .a transfer of data between the 8273 and
memory for a receive operation.
Operations are initiated by writing an appropriate
command in the Command Register.
RxDACK: RECEIVE DMA ACKNOWLEDGE
The RxDACK signal notifies the 8273 that a receive
DMA cycle has been granted. It is also used with RD
to read data from the 8273 in non-DMA mode. Note:
~ must not be asserted while RxDACK is active.
PARAMETER
Parameters of commands that require additioal information are written to this register.
RD, WR: READ, WRITE
RESULT
The RD and WR signals are used to specify the direction of the data transfer.
Contains an immediate result describing an outcome
of an executed command.
DMA transfers require the use of a DMA controller
such as the Intel 8257. The function of the DMA
controller is to provic!e sequential addresses and
timing for the transfer, at a starting address determined by the CPU. Counting of data blocks lengths
is performed by the 8273.
TRANSMIT INTERRUPT RESULT
Contains the outcome of 8273 transmit operation
(good/bad completion).
RECEIVE INTERRUPT RESULT
To request a DMA transfer the 8273 raises the appropriate DMA REQUEST. DMA ACKNOWLEDGE
and READ enables DMA data onto the bus (independently of CHIP SELECn. DMA ACKNOWLEDGE
and WRITE transfers DMA data to the 8273 (independent of CHIP SELECn.
Contains the outcome of 8273 receive operation
(good/bad completion), followed by additional results which detail the reason for interrupt.
STATUS
The status register reflects the state of the 8273·
CPU Interface.
DMA Data Transfers
It is also possible to configure the 8273 in the nonDMA data transfer mode. In this mode the CPU
module must pass data to the 8273 in response to
non-DMA data requests indicated by status word.
Modem Interface
The 8273 CPU interface supports two independent
data interfaces: receive data and transmit data. At
high data transmission speeds the data transfer rate
of the 8273 is great enough to justify· the use of direct memory access (DMA) for the data transfers.
When the 8273 is configured in DMA mode, the elements of the DMA interfaces are: -
The 8273 Modem interface provides both dedicated
and user defined modem control functions. All the
control signals are active low so that EIA RS-232C
inverting drivers (MC 1488) and inverting receivers
(MC 1489) may be used to interface to standard modems. For asynchronous operation, this interface
supports programmable NRZI data encode/decode,
a digital phase locked loop for efficient clock extraction from NRZI data, and modem control ports with
automatic CTS, CD monitoring and RTS generation.
This interface also allows the 8273 to operate in
PRE-FRAME SYNC mode in which the 8273 prefixes 16 transitions to a frame to synchronize idle lines
before transmission of the first flag.
TxDRQ: TRANS",IT DMA REQUEST
Requests a transfer of data between memory and
the 8273 for a transmit operation.
TxDACK: TRANSMIT DMA ACKNOWLEDGE
The TxDACK Signal notifies the 8273 that a transmit
DMA cycle has been granted. It is also used with
WR to transfer data to the 8273 in non-DMA mode.
Note: AD must not be asserted while TxDACK is
active.
It should be noted that all the 8273 port operations
deal with logical values, for instance, bit DO of Port A '
will be a one when CTS (Pin 30) is a physical zero
(logical one).
2-86
inter
8273
PORT A -
Serial Data Logic
INPUT PORT
During operation, the 8273 interrogates inp~ns
CTS (Clear to Send) and CD (Carrier Detect). CTS is
used to condition the start of a transmission. If during transmission CfS is lost the 8273 generates an
interrupt. During reception, if CD is lost, the 8273
generates an interrupt.
~
~
~
Ix
x
Ix
~
~
~
~
The Serial data is s)'!!Qhronized by the user transmit
(TxC) and receive (AXC) clocks. The leading edge of
TxC generates new transmit data and the trailing
edge of Axe is used to capture receive data. The
NRZI encoding/decoding of the receive and transmit data is programmable.
~
The diagnostic features included in the Serial Data
logiC are programmable loop back of data and selectable clock for the receiver. In the loop-back
mode, the data presented to the TxD pin is internally
routed to the receive data input circuitry in place of
the RxD pin, thus allowing a CPU to send a message
to itself to verify operation of the 8273.
I
ICTS - CLEAR TO SEND
CD - CARRIER DETECT
210479-38
In the selectable clock diagnostic feature, when the
data is looped back, the receiver may be presented
incorrect sample timing by the external circuitry. The
user may select to substitute the TxC pin for the RxC
input on-chip so that the clock used to generate the
loop back data is used to sample it. Since TxD is
generated off the leading edge of TxC and RxD is
sampled on the trailing edge, the selected clock allows bit synchronism.
The user defined input bits correspond to the 8273
P~, PAs and PA2 pins. The 8273 does not interrogate or manipulate these bits.
PORT B - OUTPUT PORT
During normal operation, if the CPU sets RTS active,
the 8273 will not change this pin; however, if the
CPU sets R'i'S inactive, the 8273 will activate it before each transmission and deactivate it one byte
time after transmission. While the receiver is active
the flag detect pin is pulsed each time a flag sequence is detected in the receive data stream. Following an 8273 reset, all pins of Port B are set to a
high, inactive level.
~
~
~
~
~
Ix Ix
~
~
ASYNCHRONOUS MODE INTERFACE
Although the 8273 is fully compatible with the
HDLC/SDLC communication line protocols, which
are primarily designed for sychronous communication, the 8273 can also be used in asynchronous
applications by using this interface. The interface
employs a digital phase locked loop (DPLL) for clock
recovery from a receive data stream' and programmable NRZI encoding and decoding of data. The
use of NRZI coding with SDLC transmission guarantees that within a frame, data transitions will occur at
least every five bit times-the longest sequence of
ones which may be transmitted without zero-bit insertion. The DPLL should be used only when NRZI
coding is used since the NRZI coding will transmit
zero sequence as line transitions. The digital phase
locked loop also facilitates full-duplex and half-duplex asynchronous implementation with, or without
modems.
~
I
L-...J....---'IL=~~~~j-ll~RTs _REQUEST TQ SEND
USER DEFINED OUTPUT PB4. P83. P82. PB,
FLAG DETECT
210479-39
The user defined output bits correspond to the state
of PB4-PB1 pins. The 8273 does not interrogate or
manipulate these bits.
2-87
inter
8273
OBO_ 7
TxD
be
TICD~a
om
32XCij(
TxDiCK
RICDRQ
ATs
R;'DAci(
;a,-.
TxlNT
ffi
CD
PA2_.
RKINT
Rli
WR
Ao
A,
RxD
RESET
~
OS
elK
Fi:AGDiT
CPU INTERFACE
MODEM INTERFACE
210479-4
Figure 5. 8273 Block Diagram Showing Control Logic Functions
TxD
\
X
/
\
/
X
\
/
X
210479-5
Figure 6. Transmit/Receive Timing
2-88
intJ
8273
quadrant A 1, it is apparent that the DPll sample
"A" was placed too close to the trailing edge of the
data cell; sample "8" will then be placed at T =
(T nominal - 2 counts) = 30 counts of the 32X ClK to
move the sample pulse "8" toward the nominal center of the next bit cell. A data edge occuring in quadrant 81 would cause a smaller adjustment of phase
with T = 31 counts of the 32X ClK. Using this technique the DPll pulse will converge to nominal bit
center within 12 data bit times, worst case, with constant incoming RxD edges.
DIGITAL PHASE LOCKED LOOP
In asynchronous applications, the clock is derived
from the receiver data stream by the use of the digital phase locked loop (DPll). The DPll requires a
clock input at 32 times the required baud rate. The
receive data (RxD) is sampled with this 32X ClK and
the 8273 DPll supplies a sample pulse nomminally
centered on the RxD bit cells. The DPll has a builtin "stiffness" which reduces sensitivity to line noise
and bit distortion. This is accomplished by making
phase error adjustments in discrete increments.
Since the nominal pulse is made to occur at 32
counts of the 32X ClK, these counts are subtracted
or added to the nominal, depending upon which
quadrant of the four error quadrants the data edge
occurs in. For example if an RxD edge is detected in
RxD
A method of attaining bit synchronism following a
line idle is to use PRE-FRAME SYNC mode of transmission.
_----JX'-____---JX_____ X____
-J
i5PII
SAMPLES
A
QUADRANT
ADJUSTMENT
B
Al
I:
Bl
B2
A2
·1· ·1· ·1·
-2
T-
-1
+1
+2
:1
210479-6
Figure 7. DPLL Sample Timing
2-89
intJ
8273
SYNOHRONOUS MODEM-DUPLEX OR HALF DUPLEX OPERATION
8273
RxC
R.C
R.D
T.C
TxD
32.CLK
f
GND
MODEM
V
",,/
~
11.0
MODEM
8273
TiCc
"TxD
l5JiIT
om
32xCLK
1
l
f
N.C.
GND
N.C.
210479-7.
ASYNCHRONOUS MODES-DUPLEX OR HALF DUPLEX OPERATION
8273
8273
MODEM
MODEM
.----1-...... RxD
210479-8
ASYNCHRONOUS-NO MODEMS-DUPLEX OR HALF DUPLEX
8273
32xCLK
T.C
TxD
I--
r-
RxC
RxD
I---<
~ T.C
RxC
RxD
8273
TxD
OPIT
32.CLK
DPLL
I
I
32.
CLOCK
32x
CLOCK
I
210479-33
2-90
intJ
8273
ondary station finding its address in the A field captures the frame for action at that station. All received
frames are relayed to the next station on the loop.
SOLC LOOP
The OPLL simplifies the SOLe loop station implementation. In this application, each secondary station on a loop data link is a repeater set in one-bit
delay mode. The signals sent out on the loop by the
loop controller (primary station) are relayed from station to station then, back to the controller. Any sec-
Loop stations are required to derive bit timing from
the incoming NRZI data stream. The OPLL generates sample Rx clock timing for reception and uses
the same clock to implement Tx clock timing.
32.
CLOCK
1
32.CLK
1X LOOP
OSCILLATOR
r--
TxC
OPLL
RxC
8273
LOOP
CONTROLLER
TxO
R.O
t
RxO RxC
TxC TxO
8273
LOOP
TERMINAL
32xCLK
TxO
8273
LOOP
TERMINAL
RxO
TxC
RxC
OPLL
OPLL
I
I
32.
CLOCK
32.CLK
32x
CLOCK
210479-9
Figure 8. SOLC Loop Application
2-91
inter
8273
PRINCIPLES OF OPERATION
Bit 7 CBSY (Command Busy)
Indicates in-progress command, set for CPU poll
when Command Register is full, reset upon command phase completion. It is improper to write a
command when CBSY is set; it results in incorrect
operation.
The 8273 is an intelligent peripheral controller which
relieves the CPU of many of the rote tasks associated with constructing and receiving frames. It is fully
compatible with the MCS-80/85™ system bus. As a
peripheral device, it accepts commands from a CPU,
executes these commands and provides an Interrupt
and Result back to the CPU at the end of the execution. The communication with the CPU is done by
activation of CS, RD, WR, pins while the A1, Ao se" lect the appropriate registers on the chip as de~cribed in the Hardware Description Section.
""
The 8273 operation is composed of the following
sequence of events:
YES
I COMMAND PHASE I
~~3 ~:J~~~g~~~N.:i~:~:~R::iri~~~~Ns~O THE
I
II EXECUTION PHASE I
II
I
RESULT PHASE
I
THE 8273 IS ON ITS OWN TO CARRY OUT THE COMMAND
THE 8273 SIGNALS THE CPU THAT THE EXECUTION
HAS FINISHED. THE CPU MUST PERFORM A READ
OPERATION OF ONE OR MORE OF THE REGISTERS.
210479-40
NO
The Command Place
END OF COMMAND PHASE
During the command phase, the software writes a
command to the command register. The command
bytes provide a general description of the type of
operation requested. Many commands require more
detailed information about the command. In such a
case up to four parameters are written into the parameter register. The flowchart of the command
phase indicates that a command may not be issued
if the Status Register indicates that the device is
busy. Similarly if a parameter is issued when the Parameter Buffer shows full, incorrect operation will occur.
YES
210479-10
The 8273 is a duplex device and both transmitter
and receiver may each be executing a command or
passing results at any given time. For this reason
separate interrupt pins are provided. However, the
command register must be used for one command
sequence at a time.
Figure 9. Command Phase Flowchart
Bit 6 CBF (Command Buffer Full)
Indicates that the command register is full, it is reset
when the 8273 accepts the command byte but does
not imply that execution has begun.
STATUS REGISTER
The status register contains the status of the 8273
activity. The description is as follows.
D7
De
Ds
D4
D3
D2
D1
Bit 5 CPBF (Command Parameter Buffer Full)
CPBF is set when the parameter buffer is full, and is
reset by the 8273 when it accepts the parameter.
The CPU may' poll CPBF to determine when additional parameters may be written.
Do
I~YI~I~I~~I~mlhMI~Mlh~1
2-92
intJ
8273
Bit 4 CRBF (Command Result Buffer Full)
Bit 0 TxlRA (Transmitter Interrupt Result
Available)
Indicates that an executed command immediate result is present in the Result Register. It is set by
8273 and reset when CPU reads the result.
The TxlRA is set by the 8273 when an interrupt result byte is placed in the TxlNT register. It is reset
when the CPU has read the TxlNT register.
Bit 3 RxlNT (Receiver Interrupt)
THE EXECUTION PHASE
RxlNT indicates that the receiver requires CPU attention. It is identical to RxlNT (pin 11) and is set by
the 8273 either upon good/bad completion of a
specified command or by Non-DMA data transfer. It
is reset only after the CPU has read the result byte
or has received a data byte from the 8273 in a NonDMA data transfer.
Upon accepting the last parameter, the 8273 enters
into the Execution Phase. The execution phase may
consist of a DMA or other activity, and mayor may
not require CPU intervention. The CPU intervention
is eliminated in this phase if· the system utilizes DMA
for the data transfers, otherwise, for non-DMA data
transfers, the CPU is interrupted by the 8273 via
TxlNT and RxlNT pins, for each data byte request.
Bit 2 TxlNT (Transmitter Interrupt)
The TxlNT indicates that the transmitter requires
CPU attention. It is identical to TxlNT (pin 2). It is set
by 8273 either upon good/bad completion of a specified command or by Non-DMA data transfer. It is
reset only after the CPU has read the result byte or
has transferred transmit data byte to the 8273 in a
Non-DMA transfer.
THE RESULT PHASE
Bit 1 RxlRA (Receiver Interrupt Result
Available)
To facilitate quick networis software decisions, two
types of execution results are provided:
1. An Immediate Result
2. A Non-Immediate Result
During the result phase, the 8273 notifies the CPU of
the execution outcome of a command. This phase is
initiated by:
1. The successful completion of an operation
2. An error detected during an operation.
The RxlRA is set by the 8273 when an interrupt result byte is placed in the RxlNT register. It is reset
after the CPU has read the RxlNT register.
°1
\
I
D7
D8
DS
1
o
0
1
0
1
0
o
o
o
0
0
0
1
1
1
I
·'~-. . / '{'
D7
·~~l
Dl- DO received
D2- DO received
',,,,,-- J
04-00 received
05-00 received
06-00 received
0
0
·
0
0
0
0
0
0
*Partial
De
I
DS
.
.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D4
D3
D2
Dl
DO
Ree....r Interrupt R.lull Code
R. Stetu. Aftor INT
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
Active
Active
Active
Active
Disabled
Disabled
Active
0
0
0
1
A1 match or general receive
A2 match
CRC error
Abort detected
Idle detect
EOP detected
Frame less than 32 bits
DMA overrun detected
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
Memory buffer overflow
Corrler detect failure
Receive Interrupt overrun
Byte Received
Disabled
Disabled
Disabled
Disabled
210479-11
Figure 10. Rx Interrupt Result Byte Format
2-93
8273
o
06
05
o
o
01
Early transmit interrupt
Frame transmit complete
DMA underrun
Clear to Send (CTS) error
Abort complete
D.
03
02
0,
Do
0
0
0
0
1
1
0
0
0
1
0
1
1
0
0
0
1
0
Do
210479-12
Figure 11. Tx Interrupt Result Byte Format
Immediate result is provided by the 8273 for commands such as Read Port A and Read Port B which
have information (CTS, CO, RTS, etc.) that the network software needs to make quick operational decisions.
interrupt and, if required, one or more bytes which
detail the condition.
Tx and Rx Interrupt Result Registers
The Result Registers have a result code, the three
high order bits 07-05 of which are set to zero for all
but the receive command. This command result contains a count that indicates the number of bits received in the last byte. If a partial byte is received,
the high order bits of the last data byte are indeterminate.
A command which cannot provide an immediate result will generate an interrupt to signal the beginning
of the Resultphase. The immediate results are provided in the Result Register; all non-immediate results are available upon device interrupt, through Tx
Interrupt Result Register Txl/R or Rx Interrupt Result Register Rxl/R. The result may consist of a onebyte interrupt code indicating the condition for the
All results indicated in the command summary must
be read during the result phase.
2-94
inter
8273
INTERRUPT
r----
N~~g~AI
+
----.,
I
I DMA
I MODE
READ STATUS
REGISTER
I
I
I
I
YES
I
I
NO
READ STATUS
REGISTER
DATA REQUEST
NON·DMA MODE
USE DAC~+ RD OR
WR TO READ OR
WRITE DATA
(
NO
END)
YES
READ IIR
REGISTER
210479-13
Figure 12. Result Phase Flowchart-Interrupt Results
2-95
inter
8273
AFTER COMMAND PHASE COMPLETION (READ PORT A. PORT B)
READ STATUS
READ RESULT
REGISTER
REGISTER
210479-14
Figure 13. (Rx Interrupt Service)
Since Address/Control field extension is normally
done with software to maximize extension flexibility,
the 8273 does not create or operate upon contents
of the extended HDLC Address/Control fields. Extended fields are transparently passed by the 8273
to user as either interrupt results or data transfer
requests. Software must' assemble the fields for
transmission and interrogate them upon reception.
DETAILED COMMAND DESCRIPTION
General
The 8273 HDLC/SDLC controller supports a comprehensive set of high level commands which allows
the 8273 to be readily used in full-duplex, half-duplex, synchronous, asynchronous and SDLC loop
configuration, with or without modems. These framelevel commands minimize CPU and software overhead. The 8273 has address and control byte buffers which allow the receive and transmit commands
to be used in buffered or non-buffered modes.
However, the user can take advantage of the powerful 8273 commands to minimize CPU/Software
overhead and simplify buffer management in handling extended fields. For instance buffered mode
can be used to separate the first two bytes, then
interrogate the others from buffer. Buffered mode is
perfect for a two byte address field.
In buffered transmit mode, the 8273 transmits a flag
automatically, reads the Address and Control buffer
registers and transmits the fields, then via DMA, it
fetches the information field. The 8273, having
transmitted the information field, automatically appends the Frame Check Sequence (FCS) and the
end flag. Correspondingly, in buffered read mode,
the Address and Control fields are stored in their
respective buffer registers and only Information
Field is transferred to memory.
The 8273 when programmed, recognizes protocol
characters unique to HDLC such as Abort, which is a
string of seven or more ones (01111111). Since
Abort character is the same as the GA (EOP) character used in SDLC Loop applications., Loop Transmit and Receive commands are not recommended
to be used in HDLC. HDLC does not support Loop
mode.
Initialization Set/Reset Commands
In non-buffered transmit mode, the 8273 transmits
the beginning flag automatically, then fetches and
transmits the Address, Control and Information
fields from the memory, appends the FCS character
and an end flag. In the non-buffered receive mode
the entire contents of a frame are sent to memory
with the exception of the flags and FCS.
These commands are used to manipulate data within the 8273 registers. The Set commands have a
single parameter which is a mask that corresponds
to the bits to be set. (They perform a logical-OR of
the specified register with the mask provided as a
parameter). The Register commands have a single
parameter which is a mask that has a zero in the bit
positions that are to be reset. (They perform a logical-AND of the specified register with the mask).
HDLC Implementation
HDLC Address and Control field are extendable. The
extension is selected by setting the low order bit of
the field to be extended to a one, a zero in the low
order bit indicates the last byte of the respective
field.
SET ONE-BIT DELAY (CMD CODE A4)
!
~: I~' I~ I~71 ~ I~51 ~41 I~21 ~' I~ I
2-96
intJ
8273
When one bit delay is set, 8273 retransmits the received data stream one bit delayed. This mode is
entered at a receiver character boundary, and
should only be used by Loop Stations.
RESET OPERATING MODE (CMD CODE 51)
A1 Ao 07 06 05 04 03 02 01 00
~~~: 1~ 10 10 1 1 10 1 1 10 10 10 1
1
RESET ONE·BIT DELAY (CMD CODE 64)
A1
Ao
07 06 05 04 03 02 01 00
~~~: I ~ 10 1~ 11 11 10 10 1
10 10 1
(D5) HDLC MODE
The 8273 stops the one bit delayed retransmission
mode.
In HOLC mode, a bit sequence of seven ones
(01111111) is interpreted as as an abort character.
Otherwise, eight ones (011111111) signal an abort.
SET DATA TRANSFER MODE (CMD CODE 97)
A1 Ao 07 06 05 04 03 02 01 00
~~~: I ~ 10 1: 1~ 1~ 1: 1~ 1: 1: 1 1 1
When the data transfer mode is set, the 8273 will
interrupt when data bytes are required for transmission or are available from a receive. If a transmit
interrupt occurs and the status indicates that there is
no Transmit Result (TxIRA = 0), the interrupt is a
transmit data request. If a receive interrupt occurs
and the status indicates that there is no receive result (RxIRA = 0), the interrupt is a receive data request.
A1 Ao 07 06 05 04 03 02 01 00
~~~: I ~ 10 10 11 10 11 1 0 11 1 : 1: 1
If the Oata Transfer Mode is reset, the 8273 data
transfers are performed through the OMA requests
without interrupting the CPU.
:::' I:' I~·I :I0: I~ I~'I : I:: I0; I~·I
=
In EOP interrupt mode, an interrupt is generated
whenever an EOP character (01111111) is detected
by an active receiver. This mode is useful for the
implementation of an SOLC loop controller in detecting the end of a message stream after a loop poll.
The early interrupt mode is specified to indicate
when the 8273 should generate an end of frame interrupt. When set, an early interrupt is generated
when the last data character has been passed to the
8273. If the user software responds with another
transmit command before the final flag is sent, the
final flag interrupt will not be generated and a new
frame will immediately begin when the current frame
is complete. This permits frames to be separated by
a single flag. If no additional Tx commands are provided, a final interrupt will follow.
NOTE:
In buffered mode, if a supervisory frame (no Information) Transmit command is sent in response to
an early Transmit Interrupt, the 8273 will repeatedly
transmit the same supervisory frame with one flag
in between, until a non-supervisory transmit is issued.
SET OPERATING MODE (CMD CODE 91)
1,
(D4) EOP INTERRUPT MODE
(D3) TRANSMITTER EARLY INTERRUPT MODE
(Tx)
RESET DATA TRANSFER MODE (CMD CODE
57)
I
Any mode switches set in CMO code 91 can be reset using this command by placing zeros in the appropriate positions.
Early transmitter interrupt can be used in buffered
mode by waiting for a transmit complete interrupt
instead of early Transmit Interrupt before issuing a
transmit frame command for a supervisory frame.
See Figure 14.
FLAG STREAM MODE
1 = PREFRAME SYNC MODE
1 = BUFFERED MODE
1 .. EARLY INTERRUPT MODE
1" EOP INTERRUPT MODE
1'" HOle MODE
210479-34
2-97
8273
(DO) FLAG STREAM MODE
Tx INTERRUPT PROCEDURE
If this bit is set to a one, the following table outlines.
the operation of the transmitter.
TRANSMIT COMPLETION
(ODH)
INTERRUPT
OTHER
Transmitter State
Action
Idle
Send Flags Immediately.
Transmit or Transmit}
Transparent Active
Send Flags After the
Transmission Complete
Loop Transmit Active
Ignore Command.
1 Bit Delay Active
Ignore Command.
If this bit is reset to zero the following table outlines
the operation of the transmitter
Transmitter State
Action
IDLE
Sends Idles on Next
Character boundary.
NO
Transmit or Transmit- }
Transparent Active
Send Idles after the
Transmission
is Complete.
Loop Transmit Active
Ignore Command.
1 Bit Delay Active
Ignore Command.
SET SERIAL 1/0 MODE (CMD CODE AO)
OTHER PROCESSING
210479-15
~
Figure 14
~
~
~
~
~
~
~
~
~
:::: I : I : 1: 1: I : I : I : 1°1°1°1
I , • NRZ, MODE
If this bit is zero, the interrupt will be generated only
after the final flag has been transmitted.
1· TxC-Rxe
, =
(D2) BUFFERED MODE
LOOP BACK T)lO _ RxD
210479-16 '
If the buffered mode bit is set to a one, the first two
bytes (normally the address (A) and control (C)
fields) of a frame are buffered by the 8273. If this bit
is a zero the address and control fields are passed
to and from memory.
RESET SERIAL 1/0 MODE (CMD CODE 60)
This command allows bits set in CMD code AO to be
reset by plaCing zeros in the appropriate positions.
~~~ I~ I~ I~ I~f I~f I~21 ~' I~ I
(D1) PREFRAME SYNC MODE
If this bit is set to a one the 8273 will transmit two
characters before the first flag of a frame.
(D2) LOOP BACK
To guarantee sixteen line transitions, the 8273
sends two bytes of data (OO)H if NRZI is set or data
(55)H if NRZI is not set.
If this bit is set to a one, the transmit data is internally routed to the receive data circuitry.
2-98
inter
8273
(D1) TxC -+ RxC
Receive Commands
If this bit is set to a one, the transmit clock is internally routed to the receive clock circuitry. It is normally used with the loop back bit (02).
The 8273 supports three receive commands: General Receive, Selective Receive, and Selective Loop
Receive.
(DO) NRZI MODE
GENERAL RECEIVE (CMD CODE CO)
If this bit is set to a one, NRZI encoding and decoding of transmit and receive data is provided. If this bit
is a zero, the transmit and receive data is treated as
a normal positive logic bit stream.
General receive is a receive mode in which frames
are received regardless of the contents of the address field.
A1 Ao 07 06 05 04 03 02 01 00
NRZI encoding specifies that a zero causes a
change in the polarity of the transmitted Signal and a
one causes no polarity change. NRZI is used in all
asynchronous operations. Refer to IBM document
GA27-3093 for details.
Reset Device Command
CMO:
0
PAR:
0
PAR:
0
0
11 1 101 0 1 0 JoJOJO
1 LEAST SIGNIFICANT BYTE
OF THE RECEIVE BUFFER
LENGTH (BO)
1 MOST SIGNIFICANT BYTE
OF RECEIVE
BUFFER LENGTH (B1)
A1 Ao 07 06 05 04 03 02 01 00
~~:~ ~ ~ ~ ~
I
I
I
I
1 ;
1
~ ~ ~ ~ ~
1
1-
1
1
I
An 8273 reset command is executed by outputting a
(01)H followed by (OO)H to the reset register (TMR).
See 8273 AC timing characteristics for Reset pulse
specifications.
The reset command emulates the action of the reset
pin.
1) The modem control signals are forced high (inactive level).
2) The 8273 status register flags are cleared.
3) Any commands in progress are terminated immediately.
4) The 8273 enters an idle state until the next command is issued.
5) The Serial I/O and Operating Mode registers arEi
set to zero and OMA data register transfer mode
is selected.
6) The device assumes a non-loop SOLC terminal
role.
2-99
NOTES:
1. If buffered mode is specified, the RO, R1 receive
frame length (result) is the number of data bytes received.
2. If non-buffered mode is specified, the RO, R1 receive frame length (result) is the number of data
bytes received plus two (the count includes the address and control bytes).
3. The frame check sequence (FCS) is not transferred to -memory.
4. Frames with less than 32 bits between flags are
ignored (no interrupt generated) if the buffered
mode is specified.
5. In the non-buffered mode an interrupt is generated when a less than 32 bit frame is received, since
data transfer requests have occurred.
6. The 8273 receive is always disabled when an
Idle is received after a valid frame. The CPU module must issue a receive command to re-enable the
receiver.
7. The intervening ABORT character between a final flag and an 10LE does not generate an interrupt.
8. If an ABORT Character is not preceded by a flag
and is fallowed by an 10LE, an interrupt will be generated for the ABORT followed by an 10LE interrupt
one character time later. The reception of an
ABORT will disable the receiver.
intJ
8273
RECEIVE DISABLE (CMD CODE 5)
SELECTIVE RECEIVE (CMD CODE C1)
CMD:
A1
'0
PAR:
0
Ao D7 D6 D5 D4 D3 D2 D1 Do
0
1
Terminates an active receive command immediately.
A1 Ao D7 D6 D5 D4 D3 D2 D1 Do
111.101010101011
CMD: 1 0 1 0 1 1 1 1 1 0 1 0' 1 0 I' 1 1 0 1 1 I
LEAST SIGNIFICANT BYTE
OF THE RECEIVE
BUFFER LENGTH (BO)
PAR:
NONE
PAR:
0
1
MOST SIGNIFICANT BYTE
OFRECENE
BUFFER LENGTH (B1)
PAR:
0
1
RI;CEIVE FRAME ADDRESS
MATCH FIELD ONE (A1)
The 8273 supports three transmit comm!lnds:
Transmit Frame, Loop Transmit, Transmit Transparent.
PAR:
0
1
RECEIVE FRAME ADDRESS
MATCH FIELD TWO (A2)
TRANSMIT FRAME (CMD CODE CS)
Transmit Commands
Selective receive is a receive mode in which .frames
are ignored unless the address field matches any
one of two address fields given to the 8273 as parameters.
When selective receive is used in HDLC the 8273
looks at the first character, if extended,software
must then decide if the message is for this unit.
SELECTIVE LOOP RECEIVE (CMD CODE C2)
A1
Ao D7 D6 D5 D4 D3 D2 D1 Do
CMD:
0
0
PAR:
0
0
111101010101110
0
1
MOST SIGNIFICANT BYTE
OF RECEIVE
BUFFER LENGTH (B1)
PAR:
0
1
RECEIVE FRAME ADDRESS
MATCH FIELD ONE (A1)
PAR:
0
1 ' RECEIVE FRAME ADDRESS
MATCH FIELD TWO (A2)
Ao
CMD:
0
0
PAR:
0
1
LEAST SIGNIFICANT BYTE OF
FRAME LENGTH (LO)
PAR:
0
1
MOST SIGNIFICANT BYTE OF
FRAME LENGTH (L 1)
PAR:
0
1
ADDRESS FIELD OF TRANSMIT
FRAME (A)
PAR:
0
1
CONTROL FIELD OF TRANSMIT
FRAME (C)
D7 D6 D5 D4 D3 D2 D1 Do
111101011101010
Transmits one frame including: initial flag, frame
check sequence, and the final flag.
LEAST SIGNIFICANT BYTE
OF THE RECEIVE
BUFFER LENGTH (I;JO)
PAR:
A1
If the buffered mode is specified, the LO, L 1, frame
length provides as a parameter is the length of the
information field and the address and control fields
must be input.
In unbuffered mode the frame length provided must
be the length of the information field plus two and
the address and control fields must be the first two
bytes, of data. Thus only the frame length bytes are
required as parameters.
Selective loop receive operates like selective receive except that the transmitter is placed in flag
stream mode automatically after detecting an EOP
(01111111) following a valid received frame. The
one bit delay mode is also resetst the end of a
selective loop receive.
2-100
inter
8273
After an abort character (eight contiguous ones) is
transmitted, the transmitter reverts to sending flags
or idles as a function of the flag stream mode specified.
LOOP TRANSMIT (CMD CODE CAl
A1 Ao 07 06 05 04 03 02 01 Do
CMO:
0
0
PAR:
0
1
PAR:
0
1
111101011101110
LEAST SIGNIFICANT BYTE OF
FRAME'LENGTH (LO)
ABORT LOOP TRANSMIT (CMD CODE CE)
A1
MOST SIGNIFICANT BYTE OF
FRAME LENGTH (L1)
PAR:
0
1
ADDRESS FIELD OF TRANSMIT
FRAME (A)
PAR:
0
1
CONTROL FIELD OF TRANSMIT
FRAME (C)
CMO:
PAR:
Ao 07 06 05 04 03 02 01
Do
I0 I0 I I 1 I0 I0 I 1 I 1 I 1 I0 I
NONE
After a flag is transmitted the transmitter reverts to
one bit delay mode.
ABORT TRANSMIT TRANSPARENT (CMD CODE
CD)
Transmits one frame in the same manner as the
transmit frame command except:
A1
1) If the flag stream mode is not active transmission
will begin after a.received EOP has been converted to a flag.
2) If the flag stream mode is active transmission will
begin at the next flag boundary for buffered mode
or at the third flag boundary for non-buffered
mode.
CMO:
Ao 07 06 05 04 03 02 01
Do
I0 I0 I 1 I 1 I0 I0 I 1 I 1 I0 I 1 I
PAR: NONE
The transmitter reverts to sending flags or idles as a
function of the flag stream mode specified.
3) At the end of a loop transmit the one-bit delay
Modem Control Commands
mode is entered and the flag stream mode is reset. .
The modem control commands are used to manipulate the modem control ports.
TRANSMIT TRANSPARENT (CMD CODED C9)
A1
Ao 07 06 05 04 03 02 01 Do
CMO:
0
0
PAR:
0
1
LEAST SIGNIFICANT BYTE OF
FRAME LENGTH (LO)
PAR:
0
1
MOST SIGNIFICANT BYTE OF
FRAME LENGTH (L 1)
When read Port A or Port B commands are executed
the result of the command is returned in the result
register. The Bit Set Port B command requires a parameter that is a mask that corresponds to the bits
to be set. The Bit Reset Port B command requires a
mask that has a zero in the bit positions that are to
be reset.
111101011101011
The 8273 will transmit a block of raw data without
protocol, i.e., no zero bit insertion, flags, or frame
check sequences.
. READ PORT A (CMD CODE 22)
A1
CMO:
PAR:
Ao 07 06 05 04 03 02 01
I0 I0 I0
0
Do
I0 I0 I0 I1 I0 I
NONE
Abort Transmit Commands
An abort command is supp6rted for each type of
transmit command. The abort commands are ignored if a transmit command is not in progress.
CMO:
A1
CMO:
PAR:
ABORT TRANSMIT FRAME (CMD CODE CC)
A1 Ao 07 06 05 04 03 02 01 Do
PAR:
READ PORT B (CMD CODE 23)
I0 I0 I 1 I 1 I0 I0 I 1 I 1 I0 I0 I
NONE
2-101
Ao 07 06 05 04 03 02 01
I0 I0 I0
NONE
0
Do
I0 I0 I0 I1 I1 I
inter
8273
SET PORT B BITS (CMD CODE A3)
(Do) REQUEST TO SEND.
This command allows user defined Port B pins to be
set.
This is a dedicted 8273 modem control Signal, and
reflects the same logical state of RTS pin.
~
~
::~:I:I~I
~
~
~
~
~
~
~
~
RESET PORT B BITS (CMD CODE 63)
:1:1'1 01016 1'1 '1
IRTS -
This command allows Port B user defined bits to be
reset.
REQUEST TO SEND
USER DEFINED
I
.
l
FLAG DETECT
:::'1: 1~ 1~ 1: 1' 101 01 01 ' 1'
210479-35
,I ATS -
(Ds) FLAG DETECT
AEQUEST TO SEND
USER DEFINED
This bit can be used to set the flag detect pin. However, it will be reset when the next flag is detected.
FLAG DeTECT
210479-36
This command allows Port B (D4-D1) user defined
bits to be reset. These bits correspond to Output
Port pins (PB4-PB1)'
(D4-D1) USER DEFINED OUTPUTS
These bits correspond to the state of the PB4 - PB1
output pins.
8273 Command Summary
Command Description
Command
HEX
Parameter
Results
Set One Bit Delay
A4
Set Mask
None
Reset One Bit Delay
64
Reset Mask
None
Set Data Transfer Mode
97
Set Mask
None
Reset Data Transfer Mode
57
Reset Mask
None
Set Operating Mode
91
Set Mask
None
Reset Operating Mode
51
. Reset Mask
None
Set Serial 110 Mode
AO
Set Mask
None
Reset Serial 1/0 Mode
60
Reset Mask
None
Result
Port
Completion
Interrupt
-
No
No
No
No
No
No
No
No
General Receive
CO
BO,B1
RIC,RO,A1,(A,C)(2)
RXI/R
Yes
Selective Receive
C1
BO,B 1,A1,A2
RIC,RO,Ri ,(A,C)(2)
RXI/R
Yes
RXI/R
Yes
Selective Loop Receive
C2
BO,B1,A1,A2
RIC,RO,R1,(A,C)(2)
Receive Disable
C5
None
None
Transmit Frame
C8
LO,L 1,(A,C)(1)
-
No
TIC
TXI/R
Yes
Loop Transmit
CA
LO,L 1,(A,C)(1)
TIC
TXI/R
Yes
Transmit Transparent
C9
LO,L1
TIC
TXI/R
Yes
Abort Transmit Frame
CC
None
TIC
TXI/R
Yes
2-102
intJ
8273
8273 Command Summary (Continued)
Command
HEX
Command Description
Parameter
Results
Result
Port
Completion
Interrupt
Abort Loop Transmit
CE
None
TIC
TXI/R
Yes
Abort Transmit Transparent
CD
None
TIC
TXI/R
Yes
Read PortA
22
None
Port Value
Result
No
Result
No
-
No
Read Port B
23
None
Port Value
Set Port B Bit
A3
Set Mask
None
Reset Port B Bit
63
Reset Mask
None
No
NOTES:
1. Issued only when in buffered mode.
2. Read as results only in buffered mode.
8273 Command Summary Key
80- Least significant byte of the receiver buffer length.
81- Most significant byte of the receive buffer
length.
LO- Least significant byte of the Tx frame
length.
L 1- Most significant byte of the Tx frame
length.
A 1- Receive frame address match field one.
A2- Receive frame address match field two.
A- Address field of received frame. If nonbuffered mode is specified, this result is
not provided.
COMMANO
I
t
C- Control field of received frame. If nonbuffered mode is specified this result is
not provided.
RXIIR- Receive interrupt result register.
TXIIR- Transmit interrupt result register.
RO- Least significant byte of the length of the
frame received.
R1- Most significant byte of the length of the
frame received.
RIC- Receiver interrupt result code.
TIC- Transmitter interrupt result code.
GENERAL
RECEIVE
(Ro. R,I
DATA IN
t t t
DMA REQUESTS
I ,:......_ _ _ _ _ _ _ __
DATA ~~ERRUPTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _l-A_--L-:-C_ _.l!
!
NDNBUFFERED MDDE
FRAME
CPU INTERRUPTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _C:.:Q;;;M;;.P:.:LE;.;.T,;;.E.....I..;;..~...;.._ _~_
210479-17
Figure 15_ Typical Frame Reception
NOTE:
In order to ensure proper operation to the maximum baud rate, Receive commands or Read/Write Port commands should
be written only when either the transmitter or the receiver is inactive. In full duplex systems, it is recommended that these
commands be issued after servicing a transmitter interrupt but before a new transmit command is issued. When operating in
full Duplex (active transmitter or receiver) with commands, the maximum data rate decreases to 49K Baud.
2-103
inter
8273
LAST PARAMETER
OF To COMMAND
l
1--2 BYTES-j
I 7
RTS
eTS
DRQ
BUFFER MODE
INT
------------------------------------------~~~R~~~--------------------~FI~N~A~L---TolNT
TolNT
210479-18
Figure 16a. Typical Frame Transmission, Buffered Mode
LAST PARAMETER
l
1--3 BYTES---j
,J,'_...J!
ATS _ _
eTS
-------...1
DRQ
NON·BUFFER MODE
INT
~RLY
TolNT
FINAL
TolNT
210479-19
Figure 16b. Typical Frame Transmission, Non-Buffered Mode
2-104
inter
8273
I
'I
MEMORIES
~
I
."
SVSTEMBUS
•
~
~AO.A.
'"
?'OBo-7
MEMR
lOW
MEMW
lOR
CS
HRQ
OBa-7
RO
WR
CS
TXINT
RXINT
~HACK
~
~
Rxe
RXO
TXC
TXO
TxORQ
8257
OMA
CONTROLLER
TxOACK
MODEM
8273
RxORQ
RxOACK
A
MODEM CONTROLS
".
210479-20
Figure 17.8273 System Diagram
WAVEFORMS
COMMAND PHASE
'--_oJ I
I
i--n--tool
I
CBSY
/
_.....J
I
I
I
I--T4-1
I
I
1+-T3--1
:~~~
_CP_B_F______________________
______
~/
210479-21
Table 2. Command Phase Timing (Full Duplex)
Symbol
T1
T2
T3
BuHered
Timing Parameter
Between Command & First Parameter
Between Consecutive Parameters
Command Parameter Buffer Full Bit
Reset after Parmeter Loaded
Non-BuHered
Unit
Min
Max
Min
Max.
13
10
10
756
604
604
13
10
10
857
705
705
tcy
tcy
tcy
T4
Command Busy Bit Reset after Last
Parameter
128
702
128
803
tcy
T5
CPBF Bit Reset after Last Parameter
10
604
10
705
tcy
2-105
8273
WAVEFORMS (Continued)
RECEIVER INTERRUPT
RD
__ \
LAST
INTERRRUPT RESULj ,
\'---r: \\---
RxlRA
I
I
- - - , T2
/
RxlNT
---'
210479-22
Table 3. Receiver Interrupt Result Timing
Symbol
Timing Parameter (Clock Cycles)
T1
T2
RxlRA Bit Set after RIC Read
RxlNT Goes Away after Last Int. Result
Read
Buffered
Non-Buffered
Min
Max
Min
Max
18
16
29
27
18
16
29
27
Unit
tcy
tcy
TRANSMIT INTERRUPT
RD
TxlRA
TxlNT
/
---'
210479-23
Table 4. Transmit Interrupt Result
Symbol
Buffered
Timing (Clock Cycle)
Min
T1
TxlNT Inactive after llit. Results Read
2·106
13
I
I
Non-Buffered
Max
Min
353
13
I
I
Unit
Max
454
tcy
inter
8273
• Notice: Stresses above those listed under "Absa.
lute Maximum Ratings" may cause permanent dam·
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the opsra.
tional sections of this specification is not implied. Ex·
posure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ...... O·C to 700C
Storage Temperature .......... - 65·C to + 1500C
Voltage on Any Pin With
Respect to Ground .............. - 0.5V to + 7V
Power Dissipation ........................ 1 Watt
D.C. CHARACTERISTICS 8273
Symbol
Min
Max
Unit
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee + 0.5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
Vil
Parameter
(TA = O·Cto 70·C, Vee = +5.0V ±5%)
2.4
V
III
Input Load Current
±10
poA
IOFl
Output Leakage Current
±10
poA
Icc
Vee Supply Current
180
mA
T.et Conditione
= 2.0 mA for Data Bus Pins
= 1.0 mA for Output Port Pins
= 1.6 mA for All Other Pins
IOH = - 200 poA for Data Bus Pins
IOH = -100 poA for All Other Pins
VIN = Vee to OV
VOUT = VeetoO.45V
IOl
IOl
IOl
CAPACITANCE 8273 (TA = 25·C, Vcc = GND = OV)
Symbol
Parameter
Min
Typ
Max
Unit
Teet Conditione
CIN
Input Capacitance
10
pF
te = 1 MHz
CliO
1/0 Capacitance
20
pF
Unmeasured Pins
Returned to GND
Max
Unit
Teet Conditions
1000
ns
,
A.C. CHARACTERISTICS
(TA = OOC to 70·C, Vcc = + 5.0V ± 5%)
CLOCK TIMING (8273)
Symbol
Parameter
Min
Typ
tCY
Clock
250
tel
Clock Low
120
ns
tCH
Clock High
120
ns
2-107
64KBaud Max
Operating Rate
8273
A.C. CHARACTERISTICS 8273 (TA
=
OOCt0700C, vcc';" +5.0V ± 5%)
READ CYCLE
Symbol
Parameter
Max
Min
Unit
Test Conditions
tAC
Select Setup to RD
0
ns
(Note 2)
tCA.
Select Hold from RD
tAA
RD Pulse Width
0
ns
(Note 2)
250
ns
tAD
Data Delay from Address
300
ns
(Note 2)
tAD
Data Delay from RD
200
ns
CL = 150 pF, (Note 2)
tOF
Output Float Delay
20
100
ns
CL = 20 pF For Minimum;
150 pF for Maximum
toe
DACK Setup to RD
25
ns
!co
DACK Hold from RD
25
ns
tKO
Data Delay from DACK
300
ns
WRITE CYCLE
Symbol
tAC
Parameter
Select Setup to WR
Min
Max
Unit
0
ns
tCA
Select Hold from WR
0
ns
tww
WR Pulse Width
250
ns
tow
Data Setup to WR
150
ns
two
Data Hold from WR
0
ns
toe
DACK Setup to WR
25
ns
teo
DACK Hold from WR
25
ns
Test Conditions
DMA
Symbol
tea
Parameter
Min
Request Hold from WR or RD
(for Non-Burst Mode)
Max
Unit
200
ns
Max
Unit
Test Conditions
OTHER TIMING
Symbol
Parameter
tRSTW
Reset Pulse Width
tr
Input Signal Rise Time
tf
Input Signal Fall Time
tRSTS
Reset to First IOWR
tCV32
Min
Icy
10
20
ns
20
ns
2
Icy
32X Clock Cycle Time
13.02xtcv
ns
tCL32
32X Clock Low Time
4x!cv
ns
tCH32
32X Clock High Time
tOPLL
DPLL Output Low
4x!cv
ns
1 x!cv-5O
ns
2-108
Test Conditions
intJ
8273
A.C. CHARACTERISTICS 8273
(TA = O°C to 70°C, VCC =
+ 5.0V ± 5%) (Continued)
OTHER TIMING (Continued)
Symbol
Min
Parameter
Max
Unit
tOCL
Data Clock Low
1 xtCy-50
ns
tOCH
Data Clock High
2xtCY
ns
tOCY
Data Clock
62.5xtCY
ns
tTo
Transmit Data Delay
tos
Data Setup Time
200
tOH
Data Hold Time
tFLO
FLAG DET Output Low
Test Conditions
(Note 3)
ns
200
ns
100
ns
8xtCY ± 50
ns
NOTES:
1. All timing measurements are made at the reference voltages unless otherwise specified: Input "1" at 2.0V, "0" at O.BV;
Output "1" at 2.0V, "0" at O.BV.
2. tAD, tRD, tAC, and tCA are not concurrent specs.
3. If receive commands or Read/Write Port commands are issued while both the transmitter and receiver are active, this
specification will be B1.5 TCY min.
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
"=X
2.0
0.45
>
TEST POINTS
0.8
< )C
2.0
DEVICE
UNDER
TEST
0.8
~cc~"."
210479-24
-=
A.C. Testing: Inputs are driven at 2.4V for a logic "1" and 0.45V
for a logic "0". Timing measurements are made at 2.0V for a logic
"1" and O.BV for a logic "0".
210479-25
CL = 150pF
CL Includes Jig Capacitance
WAVEFORMS
READ
DACK
---Y
X
I--;--toc-
)
I+--tAC-
-- -
1--1cA-l
'RR
~
DATA BUS
l(
~CO
r------ - --
'RO
'AD
'KO
2-109
~
JI
,~-'OF-J
)-------210479-26
inter
8273
WAVEFORMS (Continued)
WRITE
~I
DACK
I
ID~
~
I---'AC-~_
X
I--'CA --l
'WW
:x
)(
DATA BUS
I
..___tWO--J
'OW
210479-27
DMA
DRQ
I
\
5AcK
ifij DR
ViR
r =+
tco
~
tCtCL=JC~:
~
CHIP CLOCK
32X CLOCK
3
I
L.~l~.J
I
j
1\
210479-28
TRANSMIT
~---tDCL----1
----
- toCY-
TxD
·DCH-----·
.
~
...... tTD ......
210479-29
2-110
inter
8273
WAVEFORMS (Continued)
RECEIVE
RXO===t.] E~J======
210479-30
DPLL OUTPUT
210479-31
FLAG DETECT OUTPUT
210479-1
2-111
intJ
8274
MULTI-PROTOCOL SERIAL CONTROLLER (MPSC)
Synchronous:
Byte Synchronous and
• Asynchronous,
• -ByteCharacter
Synchronization, Int. or
Bit Synchronous Operation
Ext.
Two Independent Full Duplex
• Transmitters
- One or Two Sync Characters
and Receivers
- Automatic CRC Generation and
Fully Compatible with 8048, 8051, 8085,
Checking (CRC-16)
• 8088,
8086, 80188 and 80186 CPU's;
-IBM Bisync Compatible
8257 and 8237 DMA Controllers; and
Synchronous:
8089 1/0 Proc.
• -BitSDLCIHDLC
Flag Generation and
Independent DMA Channels
Recognition
• 4Baud
- 8 Bit Address Recognition
Rate: DC to 880K Baud
• Asynchronous:
- Automatic Zero Bit Insertion and
Deletion
• - 5-8 Bit Character; Odd, Even, or No
- Automatic CRC Generation and
Parity; 1, 1.5 or 2 Stop Bits
- Error Detection: Framing, Overrun,
and Parity
•
Checking (CCITT-16)
- CCITT X.25 Compatible
Available in EXPRESS and Military
The Intel 8274 Multi-Protocol Series Controller (MPSC) is designed to interface High Speed Communications
Lines using Asynchronous, IBM Bisync, and SOLC/HOLC protocol to Intel microcomputer systems. It can be
interfaced with Intel's MCS-48, -85, -51; iAPX-86, -88, -186 and -188 families, the 8237 OMA Controller, or the
8089 1/0 Processor in polled, interrupt driven, or OMA driven modes of operation.
The MPSC is a 40 pin device fabricated using Intel's High Performance HMOS Technology.
bD,
TiC",
D8 0 •7
CD",
IIrRT
,
m,
CLK
m,
IIH!T
lVI'mn,
OTII,
RxDe
R'fS,JIVIIIlft,
!POIT.DAO.
9
10
II'I/A.DfiO.
INf_---Q
1N'fl<--_CI
.,---....
',---"'L__~
et-----'
IID-----'
II/II _ _ _ _ _....J
DTRe
FIKes
INTERNAL DATA BUS
SYSTEM INTERFACE
......_ _ _ _ _....r~--R.D.
NETWO~K
170102-2
Figure 2. Pin Configuration
INTERFACE
170102-1
Figure 1. Block Diagram
2-112
November 1986
qrder Number: 170102·002
intJ
8274
Table 1. Pin Description
Symbol
Pin
No.
Type
Name and Function
ClK
1
I
CLOCK: System clock, TTL compatible.
RESET
2
I
RESET: A low signal on this pin will force the MPSC to
an idle state. TxDA and TxDe are forced high. The
modem interface output signals are forced high. The
MPSC will remain idle until the control registers are
initialized. Reset must be true for one complete ClK
cycle.
CDA
3
I
CARRIER DETECT (CHANNEL A): This interface signal
is supplied by the modem to indicate that a data carrier
signal has been detected and that a valid data signal is
present on the RxDA line. If the auto enable control.!!...
set the 8274 will not enable the serial receiver until CDA
has been activated.
Axee
4
I
RECEIVE CLOCK (CHANNEL B): The serial data are
shifted into the Receive Data input (RxDe) on the rising
edge of the Receive Clock.
CDe
5
I
CARRIER DETECT (CHANNEL B): This interface signal
is supplied by the modem to indicated that a data carrier
signal has been detected and that a valid data signal is
present on the RxDe line. If the auto enable control is
set the 8274 will not enable the serial receiver until CDe
has been activated.
CTSe
6
I
CLEAR TO SEND (CHANNEL B): This interface signal
is supplied by the modem in response to an active RTS .
signal. C'i'S indicates that the data terminal/computer
equipment is permitted to transmit data. In addition, if
the auto enable control is set, the 8274 will not transmit
data bytes until C'i'S has been activated.
f,(T S·
~
W~ ~
TxCe
7
I
TRANSMIT CLOCK (CHANNEL B): The serial data are
shifted out from the Transmit Data output (TxDe) on the
falling edge of the Transmit Clock.
TxDe
8
0
TRANSMIT DATA (CHANNEL B): This pin transmits
serial data to the communications channel (Channel B) .
RxDe
9
I
. RECEIVE DATA (CHANNEL B): This pin receives serial
data from the communications channel (Channel B).
SYNDETe
/RTSe
10
I/O
SYNCHRONOUS DETECTION (CHANNEL B): This pin
is used in byte synchronous mode as either an internal
sync detect (output) or as a means to force external
synchronization (input). In SDlC mode, this pin is an
output indicating Flag detection. In asynchronous mode
it is a general purpose input (Channel B).
REQUEST TO SEND (CHANNEL B): General purpose
output, generally used to signal that Channel B is ready
to send 'Clata. When the RTS bit is reset in asynchronous
mode, the signal does not go inactive (High) until the
. transmitter is empty.
SYNDETe or RTSe selection is done by WR2; D7.
(Channel A).
2-113
inter
8274
Table 1. Pin Description (Continued)
Symbol
,
Pin
No.
RDYe/
TxDRQA
11
DB7
12
DB6
13
DB5
14
DB4
15
DB3
16
DB2'
17
DB1
18
Type
Name and Function
0
READY (CHANNEL B)/TRANSMITTER DMA
REQUEST (CHANNEL A): In mode 0 this pin is RDYe
and is used to synchronize data transfers between the
processor and the MPSC (Channel B). In modes 1 and 2
this pin is TxDRQA and is used by the Channel A
transmitter to request a DMA transfer.
,
DBO
19
GND
20
I/O
DATA BUS: The Data Bus lines are bidirectional three
state lines which interface with the system's Data Bus.
GROUND.
+ 5V Supply
Vee
-40
rnA
39
I
CLEAR TO SEND (CHANNEL A): This interface signal
is supplied by the Modem in response to an active RTS
signal. CTS indicates that the data terminal/computer
equipment is permitted to transmit data. In addition, if
the auto enable control is set, the 8274 will not transmit
data bytes until C'i'S has been activated.
RTSA
38
0
REQUEST TO SEND (CHANNEL A): General purpose
output commonly used to signal that Channel A is ready
to send data. When the RTS bit is reset in asynchronous
mode, the signal does not go inactive (High) until the
transmitter is empty.
TxDA
37
0
TRANSMIT DATA (CHANNEL A): This pin transmits
serial data to the commmunications channE11 (Channel
A).
TxCA
36
I
TRANSMIT CLOCK (CHANNEL A): The serial data are
shifted out from the Transmit Data output (TxDA> on the
falling edge of the Transmit Clock.
R'XCA
35
I
RECEIVE CLOCK (CHANNEL A): The serial data are
shifted into the Receive Data input (RxDA) on the rising
edge of the Receive Clock.
RxDA
34
I
RECEIVE DATA (CHANNEL A): This pin receives serial
data from the communications channel (Channel A).
SYNDETA'
33
I/O
SYNCHRONOUS DETECTION (CHANNEL A): This pin
is used in byte synchronous mode as either an internal
sync detect (output) or as a means to force external
synchronization (input). In SDLC mode, this pin is an
output indicating flag detection. In asynchronous mode it
is a general purpose input (Channel A).
-.
POWER:
2-114
inter
8274
Table 1. Pin Description (Continued)
Pin
No.
Type
RDYAI
RxDRQA
32
0
READY: In mode 0 this pin is RDYA and is used to
synchronize data transfers between the processor and
the MPSC (Channel A). In modes 1 and 2 this pin is
RxDRQA and is used by the channel A receiver to
request a DMA transfer.
DTRA
31
0
DATA TERMINAL READY (CHANNEL A): General
purpose output.
IPOI
TxDRQB
30
0
INTERRUPT PRIORITY OUT/TRANSMITTER DMA
REQUEST (CHANNEL B): In modes 0 and 1, this pin is
Interrupt Priority Out. It is used to establish a hardware
interrupt priority scheme with IPI. It is low only if IPI is low
and the controlling processor is not servicing an
interrupt from this MPSC. In mode 2 it is TxDRQB and is
used to request a DMA cycle for a transmit operation
(Channel B).
IPII
RxDRQB
29
1/0
INTERRUPT PRIORITY IN/RECEIVER DMA
REQUEST (CHANNEL B): In modes 0 and 1, iPi is
Interrupt Priority In. A low on iPi means that no higher
priority device is being serviced by the controlling
processor's interrupt service routine. In mode 2 this pin
is RxDRQB and is used to request a DMA cycle for a
receive operation (Channel B).
INT
28
0
INTERRUPT: The interrupt Signal indicates that the
highest priority internal interrupt requires service (open
collector). Priority can be resolved via an external
interrupt controller or a daisy-chain scheme.
INTA
27
I
INTERRUPT ACKNOWLEDGE: This Interrupt
Acknowledge signal allows the highest priority
interrupting device to generate an interrupt vector. This
pin must be pulled high (inactive) in non-vector mode.
DTRB
26
0
DATA TERMINAL READY (CHANNEL B): This is a
general purpose output.
Ao
25
I
ADDRESS: This line selects Channel A or B during data
or command transfers. A low selects Channel A.
A1
24
I
ADDRESS: This line selects between data or command
information transfer. A low means data.
CS
23
I
CHIP SELECT: This signal selects the MSPC and
enables reading from or writing into registers.
RD
22
I
READ: Read controls a data byte or status byte transfer
from the MPSC to the CPU.
WR
21
I
WRITE: Write controls transfer of data or commands to
the MPSC.
Symbol
Name and Function
2-115
8274
ASYNCHRONOUS OPERATIONS
RESET
When the 8274 RESET line isactivitated, both
MPSC channels enter the idle state. The serial output lines are forced to the marking state (high) and
the modem interface signals (RTS, OTR) are forced
. high. In addition, the pointers registers are set to
zero.
GENERAL DESCRIPTION
The Intel 8274 Multi-Protocol Serial Controller is a
microcomputer peripheral device which supports
Asynchronous, Byte Synchronous (Monosync, .IBM
Bisync), and Bit Synchronous (ISO's HOLC, IBM's
SOLC) protocols. This controller's flexible architecture allows easy implementation of many variations
of these three protocols with low software and hardware overhead.
The Multi-Protocol Serial controller (MPSC) implements two independent serial receiver/transmitter
channels.
The MPSC supports several microprocessor interface options: Polled, Wait, Interrupt driven and OMA
driven. The MPSC is designed to support INTEL's
MCS-85 and iAPX 86, 88, 186, 188 families.
FUNCTIONAL DESCRIPTION
Additional information on Asynchronous and Synchronous Communications with the 8274 is available
respectively in the Applications Notes AP 134 and
AP 145.
TransmitterIReceiver Initialization
(See Detailed Command Description Section for
complete information)
In order to operate in asynchronous mode, each
MPSC channel must be initialized with the following
information:
1. Transmit/Receive Clock Rate. This parameter is
specified by bits 6 and 7 of WR4. The clock rate
may be set to 1, 16, 32, or 64 times the data-link
bit rate. If the Xl clock mode is selected, the bit
synchronization must be accomplished externally.
2. Number of Stop Bits. This parameter is specified
by bits 2 and 3 of WR4. The number of stop bits
may be set to 1, 1%, or 2.
3. Parity Selection. Parity may be set for odd, even,
or no parity by bits 0 and 1 of WR4.
4. Receiver Character Length. This parameter sets
the length of received characters to 5, 6, 7, or 8
bits. This parameter is specified by bits 6 and 7 of
WR3.
5. Receiver Enable. The serial-channel receiver operation may be enabled or disabled by setting or
clearing bit 0 of WR3.
6. Transmitter Character Length. This parameter
sets the length of transmitted characters to 5, 6,
7, or 8 bits. This parameter is specified by bits 5
and 6 of WR5. Characters of less than 5 bits in
length may be transmitted by setting the transmitted length to five bits (set bits 5 and 6 of WR5 to
0).
The MPSC then determines the actual number of
bits to be transmitted from the character data
byte. The bits to be transmitted must be right justified in the data byte, the next three bits must be
set to 0 and all remaining bits must be set to 1.
The following table illustrates the data formats for
transmission of 1 to 5 bits of data.
Command, parameter, and status information is
stored in 21 registers within the MPSC (8 writable
registers for each channel., 2 readable registers for
Channel A and 3 readable registers for Channel B).
In the following discussion, the writable registers will
be referred to as WRO through WR7 and the readable registers will be referred to as RRO through
RR2.
Byte Written
07
1
1
1
1
0
This section of the data sheet describes how the
Asynchronous and Synchronous protocols are implemented in the MPSC. It describes general considerations, transmit operation, and receive operation
. for Asynchronous, Byte Synchronous, and Bit Synchronous protocols.
06
1
1
1
0
0
05
1
1
0
0
0
04
1
0
0
0
c
03
0
0
0
c
c
02
0
0
c
c
c
Number of
Bits Transmitted·
01 DO (Character Length)
0 c
1
c c
2
3
c c
c c
4
c c
5
7. Transmitter Enable. The serial channel transmitter operation may be enabled or disabled by setting or clearing bit 3 of WR5.
8. Interrupt Mode. Specified by bits 3 and 4 of WR1.
2-116
inter
8274
For data transmission via a modem or RS-232-C interface, the following information must also be specified:
1. The Request To Send (RTS) (WR5; 01) and Data
Terminal Ready (OTR) (WR5; 07) bits must be set
along with the Transmit Enable bit (WR5; 03).
The Transmit Buffer Empty bit (RRO; 02) is set by
the MPSC when the data byte from the buffer is
loaded in the transmit shift register. Data should be
written to the MPSC only when the Tx buffer becomes empty to prevent overwriting.
2. Auto Enable may be set to allow the MPSC to
automatically enable the channel transmitter
when the clear-to-send signal is active and to automatically enable the receiver when the carrierdetect signal is active. However, the Transmit Enable bit (WR3; 03) and Receive Enable bit (WR3;
01) must be set in order to use the Auto Enable .
mode. Auto Enable is controlled by bit 5 of W'3!.
Receive
fc.
-
When loading Initialization parameters into the
MPSC, WR4 information must be written before the
WR1,, WR3,
WR5 parameters ' commands.
,
During initialization, it is desirable to guarantee that
the external/ status latches reflect the latest interface information. Since up to two state changes are
internally stored by the MPSC, at least two Reset
External/Status Interrupt commands must be issued. This procedure is most easily accomplished by
simply issuing this reset command whenever the
pointer register is set during initialization.
An MPSC initialization procedure (MPSC$RX$INIT) ,
for asynchronous communication is listed in Intel
Application Note AP 134.
TRANSMIT
The transmit function begins when the Transmit Enable bit (WR5; 03) is set. The MPSC automatically
adds the start bit, the programmed parity bit (odd,
even or no parity) and the programmed number of
stop bits (1, 1.5 or 2 bits) to the data character being
transmitted. 1.5 stop bits option must be used with
X16, X32 or X64 clock options only. The data character is transmitted least significant bit first.
The serial data are shifted out from the Transmit
Data (TxO) output on the falling edge of the Transmit
Clock (TxC) input at a rate programmable to 1, Y16th,
Y32nd, or %4th of the clock rate supplied to the TxC
input.
The TxO output is held high when the transmitter
has no data to send, unless, under program control,
the Send Break (WR5; 04) command is issued to
hold the TxO low.
If the External/Status Interrupt bit (WA1; ~O) is set,
the status of CD, CTS and SYNOET are monitored
and, if any changes occur for a period of time greater than the minimu'!!.!e.ecified pulse width, an interrupt is generated. CTS is usually monitored using
this interrupt feature (e.g., Auto Enable option).
The receive function begins when the Receive Enable (WR3; ~O) bit is set. If the Auto Enable (WR3;
05) option is selected, then Carrier Detect (CD)
must also be. low. A valid start bit is detected if a low
persists for at least % bit time on the Receive Data
(RxO) input.
The data is sampled at mid-bit time, on the rising
edge of RxC, until the entire character is assembled.
The receiver inserts 1's when a character is less
than 8 bits. If parity (WR4; DO) is enabled and the
character is less than 8 bits the parity bit is not
stripped from the character.
Error Reporting
The receiver also stores error status for each of the
3 data characters in the data buffer. Three error conditions may be encountered during data reception in
the asynchronous mode:
1. Parity. If parity bits are computed and transmitted
with each character and the MPSC is set to check
parity (bit 0 in WR4 is set), a parity error will occur
whenever the number of "1" bits within the character (including the parity bit) does not match the
odd/even setting of the parity check flag (bit 1 in
WR4). When a parity error is detected, the parity
error flag (RR1; 04) is set and remains set until it
is reset by the Error Reset command (WRO; 05,
04,03).
2. Framlng_ A framing error will occur if a stop bit is
not detected immediately following the parity bit (if
parity checking is enabled) or immediately following the most"significant data bit (if parity checking
is not enabled). When a Framing Error is detected, the Framing Error bit (RR1; 06) is set and
remains set until reset by the Error Reset Command (WRO; 05, 04, 03). The detection of a
Framing Error adds an additional % bit time to the
character time so the Framing Error is not interpreted as a new start bit.
3. Overrun. If the CPU fails to read a data character
while more than three characters have been received, the Receive bverrun bit (RR1; 05) is set.
When this occurs, the fourth character assembled
replaces the third character in the receive buffers.
Only the overwritten character is flagged with the
Receive Overrun bit. The Receive Overrun bit
(RR1; 05) is reset by the Error Reset command
(WRO; 05, 04, 03).
2-117
inter
8274
ternal/Status interrupts (WRO; OS, 04, 03) will
clear Break Detect and Carrier Detect bits if they
are set.
External/Status Latches
The MPSC' continuously monitors the state of five
external/status conditions:
1. CTS-clear-to-send input pin'.
2. CD-<:arrier-detect input pin.
3. SYNOET-sync-detect input pin. This pin may be
used as a general-purpose input in the asynchronous communication mode.
4. BREAK-a break condition (series of space bits
on the receiver input pin).
S. TxUNOERRUN/EOM-Transmitter Underrun/
End of Message.
A change of state in any of these monitored conditions will cause the associated status bit in RRO
to be latched (and optionally cause an interrupt).
If the Externa:I/Status Interrupt bit (WR1; DO) is
enabled, Break Detect (RRO; 07) and Carrier Detect (RRO; 03) will cause an interrupt. Reset Ex-
Command, parameter, and status information is
stored in 21 registers within the MPSC (8 writable
registers for each channel, 2 readable registers for
Channel A ahd 3 readable registers for Channel B).
They are all accessed via the command ports.
An internal pointer register selects which of the command or status registers will be read or written during a commmand/status access of an MPSC channel.
After reset, the contents of the pointer registers are
zero. The first write to a command register causes
the data to be loaded into Write Register 0 (WRO).
The three least significant bits of WRO are loaded
into the Command/Status Pointer. The next read or
write operation accesses the read or write register
selected by the pointer. The pointer is reset after the
read or write operation is completed.
COMMAND/STATUS
POINTER
j
________-----JI I
1 I·
L.-_ _ _ _ _..,......_ _ _--..I
R
R
MSB
A
2'
1
LSB
R••d Aeglsten
'--____--'1
'ChanneI B only
LSB.
170102-3
Figure 3: Command/Status Register Architecture (each serial channel)
2-118
intJ
8274
Asynchronous Mode Register Setup
07
06
00 Rx 5 b/char
01 Rx 7 b/char
10 Tx6 b/char
11 Rx 8 b/char
WR3
00
01
10
11
WR4
WR5
OTR
05
04
03
02
AUTO
ENABLE
0
0
0
0
0
0
EVEN/
X1 Clock
X16 Clock
X32 Clock
X64Clock
00
01
10
11
.01
Tx S; 5 b/ char
Tx 7 b/char
Tx 6 b/char
Tx8 b/char
01 1 STOP BIT
10 11jzSTOPBITS
11 2 STOP BITS
SEND
BREAK
SYNCHRONOUS OPERATIONMONOSYNC, BISYNC
Tx
ENABLE
0
ODD
PARITY
RTS
00
Rx
ENABLE
PARITY
ENABLE
0
Transmit Set-Up-Monosync, Bisync
General
The MPSC must be initialized with the following parameters: odd or even parity (WR4; 01, ~O), X1
clock mode (WR4; 07, 06),8- or 16-bit sync character (WR4; 05, 04), CRC polynomial (WR5; 02),
Transmitter Enable (WR5; 03), interrupt modes
(WR1, WR2), transmit character length (WR5; 06,
05) and receive character length (WR3; 07, 06).
WR4 parameters must be written before WR 1, WR3,
WR5, WR6 and WR7.
The data is transmitted on the falling edge of the
Transmit Clock, (TxC) and is received on the rising
edge of Receive Clock (RxC). The X1 clock is used
for both transmit and receive operations for all three
sync modes: Mono, Bi and External.
Transmit data is held high after channel reset, or if
the transmitter is not enabled. A break may be programmed to generate a spacir;lg .line that begins as
soon as the Send Break (WR5; 04) bit is set. With
the transmitter fully initialized and enabled, the default condition is continuous transmission of the 8- or
16-bit sync character.
Using interrupts for data transfer requires that the
Transmit InterruptlOMA Enable bit (WR1; 01) be
set. An interrupt is generated each time the transmit
buffer becomes empty. The interrupt can be satisfied either by writing another character into the
transmitter or by resetting the Transmitter Interrupti
OMA Pending latch >,yith a Reset Transmitter Inter-
Synchronous Mode Register Setup-Monosync,Bisync
07
WR3
WR4
WR5
06
00 Rx 5 b/char
01 Rx 7 b/char
10 Tx 6 b/char
11 Rx8 b/char
O·
OTR
0
00
01
10
11
05
04
03
02
01
00
AUTO
ENABLE
ENTER
HUNT
MODE
RxCRC
ENABLE
0
SYNC
CHAR
LOAD
INHIBIT
Rx·
ENABLE
0
0
EVEN/
ODD
PARITY
PARITY
ENABLE
Tx
ENABLE
1
(SELECTS
CRC-16)
RTS
TxCRC
ENABLE
00
01
11
8 bit Sync
16 bit Sync
Ext Sync
Tx S; 5 b/ char
Tx 7 b/char
Tx6 b/char
Tx8 b/char
SEND
BREAK
2-119
inter
8274
rupt/OMA Pending Command (WRO; 05, 0.4, 03). If
nothing more is written into the transmitter, there
can be no further Transmit Buffer Empty interrupt,
but this situation does cause a Transmit Underrun
condition (RRO; 06).
Oata Transfers using the ROY signal are for software controlled data transfers such as block moves.
ROY tells the CPU, that the MPSC is not ready to
accept/provide data and that the CPU must extend
the output/input cycle. OMA data transfers use the
TxORQ AlB signals which indicate that the transmit
buffer is empty, and that the MPSC is ready to accept the next data character. If the data character is
not loaded into the MPSC by the time the transmit
shift register is empty, the MPSC enters the Transmit Underrun condition.
The MPSC has two programmable options for solving the transmit underrun condition: it can' insert
sync characters, or it can send the CRC characters
generated so far, followed by sync characters. Following a chip or channel reset, the Transmit Underrun/EOM status bit (RRO; 06) is in a set condition
allowing the insertion of sync characters when there
is no ,data to send. The CRC is not calculated on
these automatically inserted sync characters. When
the CPU detects the end message, a Reset Transmit
Underrun/EOM command can be issued. This allows CRC to be sent when the transmitter has no
data to send.
In the case of sync insertion, an interrupt is generated only after the first automatically inserted sync
character has been loaded in the Transmit Shift
Register. The status register indicates the Transmit
Underrun/EOM bit and the Transmit Buffer Empty
bit are set.
In the case of CRC insertion, the Transmit Underrun/EOM bit is set and the Transmit Buffer Empty bit
is reset while CRC is being sent. When CRC has
been completely sent, the Transmit Buffer Empty
, status bit is set and an interrupt is generated to indicate to the CPU that another message can begin
(this interrupt occurs because CRC has been sent
,and sync has been loaded into the Tx Shift Register). If no more messages are to be sent, the program can terminate transmission by, resetting RTS,
and disabling the transmitter (WR5; 03).
Bisync CRC Generation. Setting the Tra,nsmit CRC
enable bit (WR5; 00) indicates CRC accumulation
when the program sends the first data character to
. the MP$C. Although the MPSC automatically transmits up to two sync characters (16 oit sync), it is
wise to send a few more sync characters ahead of
the message (before enabling Transmit CRC) to ensure synchronization at the receiving end.
,The Transmit CRC Enable bit can be changed on
the fly any time in the message to include or exclude
a particular data character from CRC accumulation.
The Transmit CRC Enable bit should be in the desired state when the data character is loaded into
the transmit shift register. To ensure this bit in the
proper state, the Transmit CRC Enable bit must be
issued before sending the data character to the
MPSC.
Transmit Transparent Mode. Transparent mode
(Bisync protocol) operation is made possible by the
ability to change Transmit CRC Enable on the fly
and by the additional capability of inserting 16 bit
sync characters. Exclusion of OLE characters from
CRC calculation can be achieved by disabling CRC
calculation immediately preceding the OLE character transfer to the MPSC.
In the transmit mode, the transmitter always sends
the programmed number of sync bits (8 or 16) (WR4;
05, 04). When in the Monosync mode, the transmitter sends from WR6 and the receiver compares
against WR7. One or two CRC polynomials, CRC 16
or SOLC, may be used with synchronous modes. In
the transmit initialization process, the CRC generator is initialized by setting the Reset Transmit CRC
Generator command (WRO; 07, 06).
The External/Status interrupt (WR1; ogtgode can
be used to monitor the status of the
input as
well as the Transmit Underrun/EOM latch. Optionally, the Auto Enable (WR3; 05) feature can be used
to enable the transmitter when CTS is active. The
first data transfer to the MPSC can begin when the
External/Status interrupt (CTS (RRO; 05) status bit
set) occurs following the Transmit Enable command
(WR5; 03).
Receive
After a channel reset, the receiver is in the Hunt
phase, during which the MPSC looks for character
synchronization. The Hunt begins only when the receiver is enabled and data transfer begins only when
character synchronization has been achieved. If
character synchronization is lost, the hunt phase can
be re-entered by writing the Enter Hunt Phase (WR3;
04) bit. The assembly of received data continues
until the MPSC is reset or until the receiver is disabled (by command or by CD while in the Auto Enables mode) or until the CPU sets the Enter Hunt
Phase bit. Under' program control, all the leading
sync characters of the message can be inhibited
from loading the receive buffers by setting the Sync
Character Load Inhibit (WR3; 01) bit. After character
synchronization is achieved the assembled characters are transferred to the receive data FIFO. After
2-120
inter
8274
receiving the first data character, the Sync Character Load Inhibit bit should be reset to zero so that all
characters are received, including the sync characters. This is important because the received CRC
may look like a sync character and not get received.
Data may be transferred with or without interrupts.
Transferring data without interrupts is used for a
purely polled operation or for off-line conditions.
There are two interrupt modes available for data
transfer: Interrupt on First Character Only and Interrupt on Every Character.
Interrupt on First Character Only mode is normally
used to start a polling loop, a block transfer sequence using ROY to synchronize the CPU to the
incoming data rate, or a OMA transfer using the
RxORQ signal. The MPSC interrupts on the first
character and thereafter only interrupts after a Special Receive Condition is detected. This mode can
be reinitialized using the Enable Interrupt On Next
Receive Character (WRO; OS, 04, OS) command
which allows the next character received to generate an interrupt. Parity Errors do not cause inter·
rupts, but End of Frame (SOLC operation) and Receive Overrun do cause interrupts in this mode. If
the external status interrupts (WR1; DO) are enabled
an interrupt may be generated any time the CD
changes state.
modes. The Special Receive Condition interrupt is
caused by the Receive Overrun (RR1; 05) error condition. The error status reflects an error in the current word in the receive buffer, in addition to any
Parity or Overrun errors since the last Error Reset
(WRO; OS, 04, OS). The Receive Overrun and Parity
error status bits are latched and can only be reset by
the Error Reset (WRO; OS, 04, 03) command. .
The CRC check result may be obtained by checking
for CRC bit (RR1; OS). This bit gives the valid CRC
result 1S bit times after the second CRC byte has
been read from the MPSC. After reading the second
CRC byte, the user software must read two more
characters (may be sync characters) before checking for CRC result in RR1. Also for proper CRC computation by the receiver, the user software must reset the Receive CRC Checker (WRO; 07, OS) after
receiving the first valid data character. The receive
CRC Enable bit (WR3; 03) may also be enabled at
this time.
SYNCHRONOUS OPERATION-SOLC
General
Interr~pt On Every Character mode generates an interrupt whenever a character enters the receive
buffer. Errors and Special Receive Conditions generate a special vector if the Status Affects Vector
(WR1 B; 02) is selected. Also the Parity Error may be
programmed (WR1; 04, OS) not to generate the special vector while in the Interrupt On Every Character
mode.
Like the other synct!ronous operations the SOLC
mode must be initialized with the following parameters: SOLC mode (WR4; OS, 04), SOLC polynomial
(WR5; 02), Request to Send, Data Termin'al Ready,
transmit character length (WR5; OS, 05), interrupt
modes (WR1; WR2), Transmit Enable (WR5; 03),
Receive Enable (WRS; ~O), Auto Enable (WRS; 05)
and External/Status Interrupt (WR1; DO). WR4.parameters must be written before WR1, WRS, WR5,
WRS and WR7.
The Special Receive Condition interrupt can only occur while in the Receive Interrupt On First Character
Only or the Interrupt On Every Receive Character
The Interrupt modes for SOLC operation are similar
to those discussed previously in the synchronous
operations section.
Synchronous Mode Register Setup-SOLC/HOLC
07
WR3
WR4 .
WR5
D6
00 Rx 5 b/char
01 Rx 7 b/char
1.0 Rx S b/char
11 Rx 8 b/char
0
OTR
0
05
04
03
02
01
00
AUTO
ENABLES
ENTER
HUNT
MODE
Rx
CRC
ENABLE
ADDRESS
SEARCH
MODE
0
Rx
0
0
0
0
Tx
ENABLE
0
(SELECTS
SOLC/HOLC
CRC)
RTS
Tx
CRC
ENABLE
1
0
(SELECTS SOLCI
HOLCMOOE)
00 Tx ~ 5 b/char
01 Tx 7 b/char
10 Tx S b/char
11 Tx 8 b/char
SEND
BREAK
2-121
intJ
8274
Transmit
After a channel reset, the MPSC begins sending
SOLC flags.
Following the flags in an SOLC operation the 8-bit
address field, control field and information field may
be sent to the MPSC by the microprocessor. The
MPSC transmits the Frame Check Sequence using
the Transmit Underrun feature. The MPSC automatically inserts a zero after every sequence of 5 consecutive 1's except when transmitting Flags or
Aborts.
SOLC-like protocols do not have provision for fill
characters within a message. The MPSC therefore
automatically terminates an SOLC frame when the
transmit data buffer and output shift register have no
more bits to send. It does this by sending the two
bytes of CRC and then one or more flags. This allows very high-speed transmissions under OMA or
CPU control without requiring the CPU to respond
quickly to the end-of-message situation.
The MPSC can be programmed to receive all frames
or it can be programmed to. the Address Search
Mode. In the Address Search Mode, only frames
with addresses that match the value in WR6 or the
global address (OFFH) are received by the MPSC.
Extended address recognition must be done by the
microprocessor software.
The control and information fields are received as
data.
SOLC/HOLC CRC calculation does not ha.ve an 8bit delay, since all characters are included in the calculation, unlike Byte Synchronous Protocols.
Reception of an abort sequence (7 or more 1's) will
cause the Break/Abort bit (RRO; 07) to. be set and
will cause an External/Status interrupt, if enabled.
After the Reset External/Status Interrupts Command has been issued, a second interrupt will occur
at the end of the abort sequehce.
MPSC
After a reset, the Transmit Underrun/EOM status bit
is in the set state and prevents the insertion of CRC
characters during the time there is no data to send.
Flag characters are sent. The MPSC begins to send
the frame when data is written into the transmit buffer. Between the time the first data byte is written,
and the end of the message,· the Reset Transmit
Underrun/EOM (WRO; 07, 06) command must be
issued. The Transmit Underrun/EOM status bit
(RRO; 06) is in the reset state at the end of the
message which automatically sends the CRC characters.
Detailed Command/Status Description
GENERAL
The MPSC supports an extremely flexible set of serial and system interface modes.
The system interface to the CPU consists of 8 ports
or buffers:
CS
The MPSC may be programmed to issue a Send
Abort command (WRO; 05, 04, 03). This command
causes at least eight 1's but less than fourteen 1's to
be sent before the line reverts to continuous flags.
0
0
0
0
A1 Ao Read Operation
0
0
1 0
0 1
1 1
1 X X
Ch. A Data Read
Ch. A Status Read
Ch. B Data Read
Ch. B Status Read
High Impedance
Write Operation
Ch. A Data Write
Ch. A Command/Parameter
Ch. B Data Write
Ch. B Command/Parameter
High Impedance
Receive
After initialization, the MPSC enters the Hunt phase,
and remains in the Hunt phase until the first Flag is
received. The MPSC never again enters the Hunt
phase unless the microprocessor writes the Enter
Hunt command. The MPSC will also detect flags
separated by a single zero. For example, the bit pattern 011111101111110 will be detected as two
flags.
Data buffers are addressed by A1 = 0, and Command ports are addressed by A1 = 1.
COMMAND/STATUS DESCRIPTION
The following command and status bytes are used
during initialization and execution phases of operation. All Command/Status operations on the two
channels are identical, and independent, except
where noted.
2-122
inter
8274
Command 2
Reset External/Status Interruptsresets the latched status bits of RRO
and re-enables them, allowing interrupts to occur again.
Command 3
Channel Reset-resets the Latched
Status bits of RRO, the interrupt prioritization logic and all control registers
for the channel. Four extra system
clock cycles should be allowed for
MPSC reset time before any additional commands or controls are written
into the channel.
Command 4
Enable Interrupt on Next Receive
Character-if the Interrupt on First
Receive Character mode is selected,
this command reactivates that mode
after each complete message is received to prepare the MPSC for the
next message.
Command 5
Reset Transmitter InterruptiOMA
Pending-if The Transmit Interrupti
OMA Enable mode is selected, the
MPSC automatically interrupts or requests OMA data transfer when the
transmit buffer becomes empty.
When there are no more characters
to be sent, issuing this command prevents further transmitter interrupts or
OMA requests until the next character has been completely sent.
Command 6
Error Reset-error latches, Parity
and Overrun errors in RR1 are reset.
Command 7
End of Interrupt-resets the interrupt-in-service latch of the highestpriority internal device under service.
07, 06
CRC Reset Code.
NUll-has no effect.
WRO
00
01
02, 01, OO-Command/Status Register Pointer bits
determine which write-register the next byte is to be
written into, or which read-register the next byte is to
be read from. After reset, the first byte written into
either channel goes into WRO. Following a read or
write to any register (except WRO) the pointer will
point to WRO.
10
Reset Transmit CRC Generator-resets the CRC generator to D's. If in
SOLC mode the CRC generator's initialized to all 1's.
11
Reset Tx Underrun/End of Message
Latch.
Detailed Register Description
Write Register 0 (WRO):
COMMAND/STATUS POINTER
REGISTER POINTER
( 0
o1
NULL CODE
SEND ABORT (SDLCI
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT RlI
CHARACTER
RESET TIIINT/DMA PENDING
ERROR RESET
END OF INTERRUPT'
'Chlnnel A only
roo 1
NULL CODE
RESET Rx CRC CHECKER
RESET TIl CRC GENERATOR
RESET TIl UNDERRUN/EOM LATCH
170102-4
05, 04, 03-Command bits determine which of the
basic seven commands are to be performed.
Command 0
NUll-has no effect.
Command 1
Send Abort-causes the generation
of eight to thirteen 1's when in the
SOLC mode.
2-123
Reset Receive CRC Checker-resets the CRC checker to D's. If in
SOLC mode the CRC checker is initialized to all 1's.
inter
8274
04,03
0
Write Register 1 (WR1):
o
o
LSB
MSB
o
\D7\D8\ DS\ D4: D3\ D2\ bl\DO \
l
'-----'"
EXT INTERRUPT
ENABLE
TxINTERRUPTI
DMAENABLE
STATUS AFFECTS
VECTOR(CHBONLY)
(NULL CODE CH A)
05
1 VARIABLE
VECTOR
0" FIXED
VECTOR
~
0
0
RxiNT/DMA DISABLE
0
1
RxlNT ON FIRST CHAR OR SPECIAL
CONDITION
1
0
INT ON ALL Rx CHAR (PARITY AFFECTS
VECTOR)OR SPECIAL CONDITION
1
1
INT ON ALL Rx CHAR (PARITY DOES
NOT AFFECT VECTOR) OR SPECIAL
CONDITION
1 " WAIT ON Rx. 0 - WAIT ON Tx
06
MUST BE ZERO
WAIT ENABLE 1
ENABLE. 0
07
DISABLE
WR2
01, DO
170102-5
WR1
DO
01
02
External/Statuslnterrupt Enable-allows interrupt to occur as the result
of transitions on the CO, CTS or
SYNOET inputs. Also allows interrupts as the result of a Breakl Abort
detection and termination, or at the
beginning of CRC, or sync character
transmission when the Transmit Underrun/EOM latch becomes set.
Transmitter InterruptlOMA Enableallows the MPSC to interrupt or request a OMA transfer when the
transr:nitter buffer becomes empty.
Status Affects vector-(WR1, 02 active in channel B only.) If this bit is
not set, then the fixed vector, programmed in WR2, is returned from
an interrupt acknowledge sequence.
If the bit if set then the vector returned from an interrupt acknowledge is variable as shown in the Interrupt Vector Table.
o
0
o
o
02
o
05, 04, 03
2-124
Receive Interrupt Mode.
Receive Interrupts/OMA Disabled.
Receive Interrupt on First Character
Only or Special Condition.
Interrupt on All Receive Characters
or Special Condition (Parity Error is a
Special Receive Condition).
Interrupt on All Receive Characters
or Special Condition (Parity Error is
not a Special Receive Condition). .
Wait on Receive/Transmit-when
the following conditions are met the
ROY pin is activated, otherwise it is
held in the High-Z state. (Conditions:
Interrupt Enabled Mode, Wait Enabled, CS = 0, AO = 0/1, and A1 =
0). The ROY pin is pulled low when
the transmitter buffer is full or the receiver buffer is empty and it is driven
High when the transmitter buffer is
empty or the receiver buffer is full.
The ROYA and ROYs may be wired
OR connected since only one signal
is active at anyone time while the
other is in the High Z state.
Must be Zero.
Wait Enable-enables the wait function.
Channel A Only
System Configuration-These specify the data transfer from MPSC channels to the CPU, either interrupt or
OMA based.
Channel A and Channel B both use
interrupts.
Channel A uses OMA, Channel B
uses interrupts.
.
Channel A and Channel B both use
OMA.
Illegal Code.
Priority-this bit specifies the relative
priorities of the internal MPSC interruptiOMA sources.
(Highest) RxA, TxA, RxB, TxB, ExTA,
ExTB (Lowest).
(Highest) RxA, RxB, TxA, TxB, ExTA,
ExTB (Lowest).
Interrupt Code-specifies the behav, ior of the MPSC when it receives an
interrupt acknowledge sequence
from the CPU. (See Interrupt Vector
Mode Table.)
inter
o x x
1 0 0
8274
Non-vectored interrupts-intended
for use with external DMA CONTROLLER. The Data Bus remains in
a high impedance state during INTA
sequences.
8085 Vector Mode 1-intended for
use as the primary MPSC in a daisy
chained priority structure. (See System Interface section).
1 0 1
8085 Vector Mode 2-intended for
use as any secondary MPSC in a daisy chained priority structure. (See
System Interface section).
8086/88 Vector Mode-intended for
use as either a primary or secondary
in a daisy chained priority structure.
(See System Interface section).
Must be zero.
zero Pin 10 = RTSB
one Pin 10 = SYNDETB
1 1 0
os
07
Write Register 2 (WR2): Channel A Only
o
o
o
BOTH INTERRUPT
A DMA. B INT
o
BOTHDMA
ILLEGAL
o
0
1
PRIORITY RxA
RxB
TxA
TxB
EXTA'
EXTB'
o
PRIORITY RxA
TxA
RxB
TxB
EXTA'
EXTS-
8085 MODE 1
o
8085 MODE 2
~~
ILLEGAL
1
o
VECTORED INTERRUPT
NO
VECTORED INTERRUPT
MUST BE ZERO
1 PIN 10
o
PIN 10
SYNDET B
RTS B
170102-6
NOTE:·
'External Status Interrupt only if EXT Interrupt Enable (WR1; DO) is set.
2·125
inter
8274
/Th~ following
\, '. D.
D4
'Cf" '-~"0
1
table'(jescribesthe MPSC's response to an interrupt acknowledge sequence:
D3
~
MODE
INTA
Data Bus
"
DO
D7
High Impedance
.' 5(-'"
X
Non-vectored
AnylNTA
85 Mode 1
1
V7
1
V6
0
0
1st INTA
2nd INTA
3rd INTA
0
0
Vs
V4*
1
V3'
1
V2*
V1
1
VO
0
0
0
0
0
0
0
0
1
1
0
High Impedance
High Impedance
0
1
1
0
1
0
1
0
0
1
85 Mode 1
1st INTA
2nd INTA
3rd INTA
1
1
0
0
86 Mode
1st INTA
2nd INTA
High Impedance
V5
V7
V6
V4
V3
V2*
V1*
VO'
1
0
1
0
85 Mode 2
1st INTA
2nd INTA
3rd INTA
High Impedance
V6
V5
V7
V4*
V3"
V2*
V1
VO
0
0
0
0
0
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance
1
0
1
1
85 Mode 2
1st INTA
2nd INTA
3rd INTA
1
1
0
1
86 Mode
1st INTA
2nd INTA
0
0
0
NOTE:
'These bits are variable if the "status affects vector" mode has been programmed, (WRl S, D2).
Interrupt/DMA Mode, Pin Functions, and Priority
Ch.AWR2
Pin Functions
Int/OMA
Mode
PIP/
IPOI
ROYAl
RDYBI
RxORQA TxDRQA RxDRQB TxDRQB
Pin 32
Pin 11
Pin 29
Pin 30 Highest
D2 D1 Do CH.A CH.B
0
0
0
INT
INT
1
0
0
INT
INT
0
0
1
0
1
RDVs
IPI
IPO
Lowest
RxA,TxA,RxB,TxB,EXTA,EXTs
RxA, RxB,TxA,TxB,EXTA, EXTs
RxA, TxA (DMA)
DMA
INT
1
RDVA
Priority
RxDRQA TxDRQA
IPI
iPO
RxA(l), RxB, TxB, EXTA, EXTs (INT)
RxA, TxA (DMA)
DMA
RxA(l), RxB, TxB, EXTA, EXT s (INT)
INT
0
1
0
DMA
DMA
1
1
0
DMA
DMA
RxDRQA TxDRQA
RxDRQs TxDRQs
RxA, TxA, RxB, TxB (DMA)
RxA(l), RxB(1), EXTA, EXTs, (I NT)
RxA, RxB, TxA, TxB, (DMA)
RxA(1), RxB(1), EXTA, EXTs (INT)
NOTE:
1. Special Receive Condition
2-126
8274
Interrupt Vector Mode Table
8085 Modes
8086/88 Mode
V4
V2
V3
V1
V2
Vo
Channel
Condition
0
0
0
0
0
0
1
1
0
1
0
1
B
Tx Buffer Empty
Ext/Status Change
Rx Char. Available
Special Rx Condition
(Note 1)
1
1
1
1
0
0
1
1
0
1
0
1
A
Tx Buffer Empty
Ext/Status Change
Rx Char. Available
Special Rx Condition
(Note 1)
NOTE:
1. Special Receive Condition = Parity Error, Rx Overrun Error, Framing Error, End of Frame (SOLC).
Write Register 2 (WR2): Channel B
MSB
WR2 CHANNEL B
07 -DO
Interrupt vector-This register contains the value of the interrupt vector
placed on the data bus during interrupt acknowledge sequences.
LSB
In:w:w:~:~:~: ~:~I
Vector
170102-7
Write Register 3 (WR3):
Ax ENABLE
SYNC CHAA LOAD INHIBIT
' - - - - - ADDA SACH MODE (SDLC)
L - - - - - - - A x CAC ENABLE
' - - - - - - - - - E N T E A HUNT MODE
L - - - - - - - - - - A U T O ENABLES
Ax 5 BITS/CHAA
Ax 7 BITS/CHAA
o
Ax 6 BITS/CHAA
Ax 8 BITS/CHAA
170102-8
2-127
inter
8274
WR3
DO
01
02
03
04
05
07,OS
o
o
0
o
Write Register 4 (WR4):
Receiver Enable-A one enables the
receiver to begin. This bit should be
set only after the receiver has been
initialized.
Sync Character Load Inhibit-A one
prevents the receiver from loading
sync characters into the receive buffers. In SOLC, this bit must be zero.
Address Search Mode-If the SOLC
mode has been selected, the MPSC
will receive all frames unless this bit
is a 1. If this bit is a 1, the MPSC will
receive only frames with address
(OFFH) or the value loaded into WRS.
This bit must be zero in non-SOLC
modes.
Receive CRC Enable-A one in this
bit enables (or re-enables) CRC calculation. CRC calculation starts with
the last character placed in the Receiver. FIFO. A zero in this bit disables, but does not reset, the Receiver CRC generator.
Enter Hunt Phase-After initialization, the MPSC automatically enters
the Hunt mode. If synchronization is
lost, the Hunt phase can be re-entered by writing a one to this bit.
Auto Enable-A one written to this
bit causes,CO to be automatic enable
signal for the receiver and CTS to be
an automatic enable signal for the
transmitter. A zero written to this bit
limits the effect of CO and CTS signals to setting/resetting their corresponding bits in the status register
(RRO).
Receive Character length
Receive 5 Data bits/character
Receive 7 Data bits/character
Receive S Data bits/character
Receive 8 Data bits/character
WR4
DO
Parity-A one in this bit causes a parity bit to be added to the programmed number of data bits per
character for both the transmitted
and received character. If the MPSC
is programmed to receive 8 bits per
character, the parity bit is not transferred to the microprocessor. With
other receiver character lengths, the
parity bit is transferred to the microprocessor.
LSB
1 = ENABLE PARITY
o = DISABLE PARITY
1 = EVEN PARITY
o~
o
0
DOD PARITY
ENABLE SYNC MODES
o
1
1 STOP BIT
1
0
1.5 STOP BITS
1
1
2 STOP BITS
o
0
BBIT SYNC CHAR
o
1
18BITSYNCCHAR
1
0
SDLCIHDLCMODE(01111110IFLAG
1
1
EXTERNAL SYNC MODE
o
0
XI CLOCK
o
1
X18CLOCK
1
0
X32 CLOCK
1
1
X84CLOCK
170102-9
01
03,02
0
o
o
1
o
l'
05,04
o 0
o
o
1 1
07,OS
2-128
Even/Odd Parity-If parity is enabled, a one in this bit causes the
MPSC to transmit and expect even
parity, and a zero causes it to send
and expect odd parity.
Stop bits/sync mode
Selects synchronous modes
Async mode, 1 stop bit/character
Async mode, 1% stop bits/character
Async mode, 2 stop bits/character
Sync mode select
8-bit sync character
1S-bit sync character
SOLC mode (Flag sync)
External sync mode
Clock Mode-Selects the clock/data
rate multiplier for both the receiver
and the transmitter. 1x mode must be
selected for synchronous modes. If
the 1x mode is selected, bit synchronization must be done externally.
8274
o
o
0
Clock rate = Oata rate x 1
o
Clock rate = Oata rate x 16
Clock rate = Oata rate x 32
Clock rate = Oata rate
x
64
01
Request to Send-A one in this bit
forces the RTS pin active (low) and
zero in this bit forces the RTS pin inactive (high).
02
CRC Select-A one in this bit selects
the CRC -16 polynomial (X 16 + X15
+ X2 + 1) and a zero in this bit selects the CCITT-CRC polynomial (X16
+ X12 + X5 + 1). In SOLC mode,
CCITT-CRC must be selected.
03
Transmitter Enable-A zero in this bit
forces a marking state on the transmitter output. If this bit is set to zero
during data or sync character transmission, the marking state is entered
after the character has been sent. If
this bit is set to zero during transmission of a CRC character, sync or flag
bits are substituted for the remainder
of the CRC bits.
Send 8reak-A one in this bit forces
the transmit data low. A zero in this
bit allows normal transmitter operation.
.
Write Register S (WRS):
MSB
LSB
1 07 1 06
051041031021011001
L
CRCENABLE
_ R Ts
SO LC/CRC·18 (CAC MOOE)
1lc ENABLE
SE NOBRUK
04
0
0
1lc 5 BITS OR LESS/CHAR
0
1
1lc 7 BITS/CHAR
1
0
1lc 8 BITs/CHAR
1
1
1lc 8 BITS/CHAR
06,05
Transmit Character length
o
o
Transmit 1-~ bits/character
Transmit 7 bits/character
Transmit 6 bits/character
o
OT A
170102-10
WRS
00
0
Transmit 8 bits/character
8its to be sent must be right justified least significant
bit first, e.g.:
Transmit CRC Enable-A one in this
bit enables the transmitter CRC generator. The CRC calculation is done
when a character is moved from the
transmit buffer into the shift register.
A zero in this bit disables CRC calculations. If this bit is not set when a
transmitter underrun occurs, the CRC
will not be sent.
07 06 05 04 03 02 01 00
o 0 85 84 83 82 81 80
07 Oata Terminal Ready-When set, this bit forces
the OTR pin active (low). When reset, this bit
forces the OTR pin inactive (high).
Five or less mode allows transmission of one to five bits per character. The
microprocessor must format the data in the following way:
07
06
05
04
03
02
01
00
1
1
1
1
0
0
0
80
Sends one data bit
1
1
0
0
0
81
80
Sends two data bits
1
0
0
0
82
81
80
Sends three data bits
Sends four data bits
1
o
0
0
83
82
81
80
o
0
84
83
82
81
80
Sends five data bits
o
2-129
intJ
8274
Write Register 6 (WR6):
Write Register 7 (WR7):
MSB
LSB
MSB
I
I~:~:~:~:OO:~:~:OOI
LSB
07 : 06 : 05 : 04 : 03 : 02 : 01 : 00
\
I
I. . .,.",.
Least significant
Sync byte '(Address
in SOLC/HOLC Mode)
Sync byte (must
be 01111110 in
SOLC/HOLC Mode)
170102-11
170102-12
WR6
07-00
RRO
Sync! Address.....,This register contains the transmit sync character in
Monosync mode, the low order 8
sync bits in Bisync mode, or the Address byte in SOLC mode.
WR7
07-00
DO
01
Sync!Flag-This register contains
the receive sync character in Monosync mode, the high order 8 sync bits
in Bisync mode, or the Flag character
(01111110) in SOLC mode. WR7 is
not used in External Sync mode.
02
Receive Character Available-This
bit is set when the receive FIFO contains data and is reset when the
FIFO is empty.
Interrupt In-Service*-If an Internal
Interrupt is pending, this bit is set at
the falling edge of the second INTA
pulse of an INTA cycle. In non-vectored mode, this bit is set at the failing edge of RO after pointer 2 is
specified. This bit is reset when an
EOI command is issued and there
are no other interrupts in-service at
that time.
Transmit Buffer Empty-This bit is
set whenever the transmit buffer is
·This bit is only valid when IPI is active low and is
always zero in Channel B.
Read Register 0 (RRO):
MSB
LSB
1~1~1~1~lool~I~lool
I
Rx CHAR AVAILABLE
INT IN-SERVICE (CHA only)
Tx BUFFER EMPTY
CARRIER OETECT
SYNC/HUNT
CTS
EXTERNAL STATUS
INTERRUPT MOOE
Tx UNOERRUN/EOM
BREAK/ABORT
170102-13
2-130
inter
03
04
8274
empty except when CRC characters
are being sent in a synchronous
mode. This bit is reset when the
transmit buffer is loaded. This bit is
set after an MPSC reset.
Carrier Detect-This bit contains the
state of the CD pin at the time of the
last change of any of the External/
Status bits (CD, CTS, Sync/Hunt,
Break/ Abort, or Tx Underrun/EOM).
Any change of state of the CD pin
causes the CD bit to be latched and
causes an External/Status interrupt.
This bit indicates current state of the
CD pin immediately following a Reset
External/Status Interrupt command.
Sync/Hunt-In asynchronous modes,
the operation of this bit is similar to
the CD status bit, except that Sync/
Hunt shows the state of the SYNDET
input. Any High-to-Low transition on
the SYNDET pin sets this bit, and
causes an External/Status interrupt
(if enabled). The Reset External/
Status Interrupt command is issued
to clear the interrupt. A Low-to-High
transition clears this bit and sets the
External/Status interrupt. When the
External/Status interrupt is set by the
change in state of any other input or
condition, this bit shows the inverted
state of the SYNDET pin at time of
the change. This bit must be read immediately following a Reset External/Status Interrupt command to
read the ·current state of the
SYNDET input.
In the External Sync mode, the
Sync/Hunt oit operates in a fashion
similar to the Asynchronous mode,
except the Enter Hunt Mode control
bit enables the external sync detection logic. When the External Sync
Mode and Enter Hunt Mode bits are
set (for example, when the receiver is
enabled following a reset), the
SYNDET input must be held High by
the external logic until external character synchronization is achieved. A
High at the SYNDET input holds the
Sync/Hunt status 'in the reset condition.
When external synchronization is
achieved, SYNDET must be driven
Low on the second rising ~ of
Axe after the rising edge of RxC on
which the last bit of the sync character was received. In other words, af-
2-.131
ter the sync pattern is detected, the
external logic must wait for two full
Receive Clock cycles to activitate the
SYNDET input. Once SYNDET is
forced Low, it is good practice to
keep it Low until the CPU informs the
external sync logic that synchronization has been lost or a new message
is about to start. The High-to-Low
transition of the SYNDET output sets
the SynclHunt bit, which sets the External/Status interrupt. The CPU
must clear the interrupt by issuing the
Reset
External/Status
Interrupt
Command.
When the "'S"'y"'"N"'D""E""T input goes High
again, another External/Status interrupt is generated that must also be
cleared. The Enter Hunt Mode control bit is set whenever character synchronization is lost or the end of
message is detected. In this case,
the MPSC again looks for a High-toLow transition on the SYNDET input
and the operation repeats as explained previously.. This implies the
CPU should also inform the external
logic that character synchronization
has been lost and that the MPSC is
waiting for SYNDET· to become active.
In the Monosync and Bisync Receive
modes, the Sync/Hunt status bit is
initially set to 1 by the Enter Hunt
Mode bit. The Sync/Hunt bit is reset
when the MPSC establishes character synchronization. The High-to-Low
transition of the ~ync/Hunt bit causes an External/Status interrupt that
must be cleared by the CPU issuing
the Reset External/Status Interrupt
command. This enables the MPSC to
detect the next transition of other External/Status bits.
When the CPU detects the end of
message or that character synchronization is lost, it sets the Enter Hunt
Mode control bit, which sets the
Sync/Hvnt bit to 1. The Low-to-High
transition of the Sync/Hunt bit sets
the External/Status Interrupt, which
must also be cleared by the Reset
External/Status Interrupt Command.
Note that the SYNDET pin acts as an
output in this mode, and goes low every time a sync pattern is detected in
the data stream.
intJ
05
06
07
8274
,In the SOLC mode, the Sync/Hunt bit
is initially set by the Enter Hunt mode
bit, or when the receiver is disabled.
In any case, it is reset to 0 when the
opening flag of the first frame is detected by the MPSC. The External/
Status interrupt is also generated,
and should be handled as discussed
previously.
Unlike the" Monosync and Bisync
modes, once the Sync/Hunt bit is reset in the 'SOLC mode, it does not
need to be set when the end of message is detected. The MPSC automatically maintains synchronization.
The only way the Sync/Hunt bit can
be set again is by the Enter Hunt
Mode bit, or by disabling the receiver.
Clear to Send-This bit contains the
inverted state of the CTS pin at the
time of the last change of any of the
External/Status bits (CO, CTS, Sync/
Hunt, Break/Abort, or Tx Underrun/
EOM). Any change of state of the
CTS pin causes the CTS bit to be
latched and causes an External/
Status interrupt. This bit indicates the
inverse of the current state of the
CTS pin immediately following a Reset External/Status Interrupt command.
Transmitter Underrun/End of Messag&-:-This bit is in a set condition
following a reset (internal or external). The only command that can reset this bit is the Reset Transmit Underrun/EOM Latch command (WRO,
06 and 07). When the Transmit Underrun condition occurs, this bit is
set, which causes the External/
Status Interrupt which must be reset
by issuing a Reset External/Status
command (WRO; command 2).
Break/ Abort-In, the Asynchronous
Receive mode, this bit is set when a
Break sequence (null character plus
framing error) is detected in the data
stream. The External/Status interrupt, if enabled, is set when break is
detected. The interrupt service routine must issue the Reset External/
Status Interrupt command (WRO,
Command 2) to the break detection
logic so the Break sequence termination can be recognized.
The Break/Abort bit is reset when
the termination of the Break sequence is detected in the incoming
data stream. The termination of the
00
RR1:
03,02,01
04
05,
06
2-132
Break sequence also causes the External/Status interrupt to be set. The
Reset External/Status Interrupt command must be issued to enable the
break detection logiC to look for the
next Break sequence. A single extraneous null character is present in the
receiver after the ,termination of a
break; it should be read and discarded.
In the SOLC Receive mode, this
status bit is set by the detection of an
Abort sequence (seven or more 1's).
The External/Status interrupt is handled the same way as in the case of
a Break. The Break/Abort bit is not
used in the Synchronous Receive
mode.
All Sent-This bit is set when all
characters have been sent, in asynchronous modes. It is reset when
characters are in the transmitter, in
asynchronous modes. In synchronous modes, this bit is always set.
Residue Codes-Bit synchronous
protocols allow I-fields that are not
an integral number of characters.
Since transfers from the MPSC to the
CPU are character oriented, the residue codes provide the capability of
receiving leftover bits. Residue bits
are right justified in the last data byte
, received or first CRC byte.
Parity Error-If parity is enabled, this
bit is set for received characters
whose parity does not match the programmed sense (Even/Odd). This bit
is latched. Once an error occurs, it
remains set until the Error Reset
command is written.
Receive Overrun Error-This bit indicates that the receive FIFO has been
overloaded by the receiver. The last
character in the FIFO is overwritten
and flagged with this error. Once the
overwritten character is read, this error condition is latched until reset by
the Error Reset command. If the
MPSC is in the statu,s affects vector
mode, the overrun causes a special
Receive Condition Vector.
CRC/Framing
Error-In
async
modes, a one in this bit indicates a
receive framing error. In synchronous
modes, a one in this bit indicates that
the calculated CRC value does not
match the last two bytes received. It
can be reset by issuing an Error Reset command.
inter
8274
SDLC Residue Code Table (I Field Bits In 2 Previous Bytes)
8 bits/char
RR1
D3 D2 D1
1
7 bits/char
5 bits/char
6 bits/char
FlrstCRC Last Data FlrstCRC Last Data FlrstCRC Last Data FlrstCRC Last Data
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
0
0
0
3
0
0
1
0
0
4
1
1
0
0
5
0
0
1
0
6
1
0
1
0
7
2
0
1
0
0
3
0
4
0
2
0
1
0
3
0
2
0
0
5
0
4
0
3
6
0
5
4
0
1
1
0
8
0
1
1
1
1
8
-
-
-
-
-
0
0
0
2
8
1
7
0
6
0
5
Read Register 1 (RR1): (Special Receive Condition Mode)
Msa
LSB
1~1~1~1~loo:~:~lool
...
L
\
J
ALLS ENT
-
.r--------.
FIRST CRC·
BYTE
LAST DATA BYTE
000
2
8
o
0
1
0
6
o
1 0
0
4
o
1
1
0
8
1 0
0
0
3
1 0
1
0
7
1 1 0
0
5
1
1
8
1
1
RESIDUE DATA
8 BITS/CHAR. MODE
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
END OF FRAME (SDLC/HDLC MODE)
170102-14
2-133
inter
07
8274
End of Frame-This bit is valid only
in SOLC mode. A one indicates that a
valid ending flag has been received.
This bit is reset either by an Error Reset command or upon' reception of .
the first character of the next frame.
Read Register 2 (RR2):
MS.
I V7 : va : V5
LSI
: V4- : V3- : V2-: V1-:
vo-I
-¥arlabl. In
..,In,.-IO_"...:UP,-t_ _ _ _ Status Affect.
Vector
Vector Mode (WFl1: D2)
POLLED OPERATION
170102-15
07-00
OMA operation is accomplished via an external OMA
controller. When the MPSC needs a data transfer, it
requests a OMA cycle from the OMA controller. The
OMA controller then takes control of the bus and
simultaneously does a read from the MPSC and a
write to memory or vice-versa.
The following section describes the many configurations of these basic types of system interface techniques for both serial channels.
1.
RR2
an interrupt acknowledge signal. When the internal
or external interrupt controller receives the acknowledge, it vectors the microprocessor to a service routine, in which the transaction occurs.
ChannelB
Interrupt Vector-Contains the interrupt vector programmed into WR2. If
the status affects vector mode is selected (WR1; 02), it contains the
modified vector (See WR2). RR2
contains the modified vector for the
highest priority interrupt pending. If
no interrupts are pending, the variable bits in the vector are set to one.
SYSTEM INTERFACE
General
The MPSC to Microprocessor System interface can
be configured in many flexible ways. The basic interface types are polled, wait, interrupt driven, or direct
memory access driven.
Polled operation is accomplished by repetitively
reading the status of the MPSC, and making decisions based on that status. The MPSC can be polled
at any time.
Wait operation allows slightly faster data throughput
for the MPSC by manipulating the Rea9Y input to the
microprocessor. Block Read or Write Operations to
the MPSC are started at will by the microprocessor
and the MPSC deactivates its ROY signal if it is not
yet ready to transmit the new byte, or if reception of
new byte is not completed.
Interrupt driven operation is accomplished via an internal or external interrupt controller. When the
MPSC requires service, it sends an interrupt request
signal to the microprocessor, which responds with
In the polled mode, the CPU must monitor the desired conditions within the MPSC by reading the appropriate bits in the read registers. All data available,
status, and error conditions are represented by the
appropriate bits in read registers 0 and. 1 for channels A and B.
There are two ways in which the software task of
monitoring the status of the MPSC has been reduced. One is the "ORing" of all conditions into the
Interrupt Pending bit. (RRO; D1 channel A only). This
bit is set when the MPSC requires service, allowing
the CPU to monitor one bit instead of four status
registers. The other is available when the "status-affects-vector" mode is selected. By reading RR2
Channel B, the. CPU can read a vector who's value
will indicate that one or more of group of conditions
has occurred, narrowing the field of possible conditions. See WR2 and RR2 in the Detailed Command
Description section.
WAIT OPERAtiON
Wait Operation is intended to facilitate data transmission or reception using bl.ock move operations. If
a block of data is to be transmitted, for example, the
CPU can execute a String 1/0 instruction to the
MPSC. After writing the first byte, the CPU will attempt to write a second byte immediately as is the
case of block move. The MPSC forces the RDY signal low which inserts wait states in the CPU's write
cycle until the transmit buffer is ready to accept a
new byte. At that time, the RDY Signal is high allowing the CPU to finish the write cycle. The CPU then
attempts the third write and the process is repeated.
Similar operation can programmed for the receiver.
During initialization, wait on transmit ('vYR1; D5 = 0)
2-134
inter
8274
Software Flow, Polled Operation
INTERRUPT DRIVEN OPERATION
The MPSC can be programmed into several interrupt modes: Non-Vectored, 8085 vectored, and
8088/86 vectored. In both vectored modes, multiple
MPSC's can be daisy-chained.
In the vectored mode, the MPSC responds to an
interrupt acknowledge sequence by placing a call instruction (8085 mode) and interrupt vector (8085
and 8088/86 mode) on the data bus.
RECEIVE
The MPSC can be programmed to cause an interrupt due to up to 14 conditions in each channel. The
status of these interrupt conditions is contained in
Read Registers 0 and 1. These 14 conditions are all
directed to cause 3 different types of internal interrupt request for each channel: receive/interrupts,
transmit interrupts and external/status interrupts (if
enabled).
TRANSMIT
170102-16
NOTES:
1. RRO; DO is reset automatically when the data is
read.
2. RRO; D2 is reset automatically when the data is writ-
This results in up to 6 internal interrupt request signals. The priority of those Signals can be programmed to one of two fixed modes:
ten.
Highest Priority Lowest Priority
or wait on receive (WR1; D5 = 1) can be selected.
The wait operation can be enabled/disabled by setting/resetting the Wait Enable Bit (WR1; D7).
RxA RxB TxA TxB ExTA ExTB
RxA TxA RxB TxB ExTA ExTB
NOTE:
CAUTION: ANY CONDITION THAT CAN CAUSE
THE TRANSMITTER TO STOP (E.G., CTS GOES
INACTIVE) OR THE RECEIVER TO STOP (E.G.,
RX DATA STOPS) WILL CAUSE THE MPSC TO
HANG THE CPU UP IN WAIT STATES UNTIL RESET. EXTREME CARE SHOULD BE TAKEN
WHEN USING THIS FEATURE.
The interrupt priority resolution works differently for
vectored and non-vectored modes.
Hardware Configuration, Polled Operation
~ ADDRESS BUS
~
~~
I I
I I
_6
1\ DATA BUS
1m
WR
-----
8205
~ 0
-
'---
DB0-7
iNii
Ao
A,
J"
MPSC
Ci
RD
WR
170102-17
2-135
8274
Interrupt Condition Grouping
CONOITioN
MODE
RECEIVE CHARACTER _ _ _ _ _ _ _ _ _ _~I
PARITY ERROR===-::-_......~Si;eciAL...,
~~~~',~'h°EVRE:~~N ERROR ~
END OF FRAMe (SDLC ONLY)_L.LIluailllll:.u
INTERNAL INTERRUPT
REQUEST
INTERRUPT ON ALL
AECIOIVE CHARACTERS
•
INTERRUPT ON FIRST
CHARACTER&~ill:~~~~===~j~~~~~:J
•
R, CHARACTER
FIRST
CHARACTER (SYNC MODES)
DATA
FIRST NON·SYNC
VALID ~DDRESS BYTE (SDLC ONLY)
TRANSITION~~:~~~~~~~~~~~~~~~~~~~~~~~~~
CTS TRANSITION
SYNC TRANSITION
T. UNDIORRUNIIOOM
BREAK/ABORT
DETECT
CD
TRANSMIT BUFFER EMPTY
170102-18
INTERNAL
INTERRUPT
ACCEPTED
LOWER PRIORITY INTERRUPTS NOT ACCEPTED
INTERRUPT
(EXTERNAL)
i'NTA
(EXTERNAL)
HIGHER
INTA
(INTIORNAL)
_ + - > - - - - - N O~~~~~~~&TS------o\---'-I~~~:mSACCIOPUD
170102-19
PRIORITY RESOLUTION: VECTORED MODE
Any interrupt condition can be accepted internally to
the MPSC at any time, unless the MPSC's internal
INTA signal is active, unless a higher priority interrupt is currently accepted, or if IPI is inactive (high).
The MPSC's internallNTA is set on the leading (fall-
iOg) edge of the first External INTA pulse and reset
on the trailing (rising) edge of the second External
INTA pulse. After an interrupt is accepted internally,
and External INT request is generated and the IPO
goes inactive. IPO and TPf are used for daisy-chaining MPSC's together.
2-136
inter
8274
In-Service Timing
(~~\1~~U:J ~~________________________________--J~
INTA
(EXTERNAL)
INTA
(INTERNAL)
IN·SERVICE
(INTERNAL)
170102-20
The MPSC's internallNTA is set on the leading (failing) edge of the first external INTA pulse, and reset
on the trailing (rising) edge of the second external
INTA pulse. After an interrupt is accepted internally,
and externalll\iT request is generated and iPO goes
inactive (high). iPO and iJ5i are used for daisy-chain.
ing MPSC'stogether.
Each of the six interrupt sources has an associated
In-Service latch. After priority has been resolved, the
highest priority In-Service latch .is set. After the InService latch is set, the. INT pin goes inactive (high).
NOTE:
If the External INT pin is active and the IPI signal is pulled
inactive high, the INT signal will also go inactive. IPI qualifies the External INT Signal.
2-137
inter
8274
EOI Command Timing
SERVICE
ROUTINE
INTEFINALINTERRUPT ACCEPTED
J
(~xW·.".I'.':.'; \
jr-----------------t
~----""'
-J/
....__________
IIID:
(EXTERNAL)
I
INTA
(INTERNAL)
----J
woJ
.....JI '
IN·SE.VICE _ _ _ _ _ _ _ _ _ _ _ _ _
(INTERNAL)
.
EOICOMMAND
(INTERNAL)
170102-21
Lower priority interrupts are not accepted internally
while.the In-Service latch is set. HOlNe,ver, hi~her prior(ty interrupts arE\lapcepte,Q i'lternally and a: new external iNi"'reqiJest is generatlild. If the CPU respond~
witH .a new ,INTA s\ilquence, tl1e MPSC.will respond
as before, suspending the lower priority Interrupt.
After the interrupt is serviced, the End-of-Interrupt
(EOI) command should be written to the MPSC. This
command 'will cause an internal pulse that is used to
reset the In-Service Latch which allows service for
lower priority interrupts in the <;Iaisy-chain to resume,
provided a "ew INTA sequence does not start for a
higher priority interrupt (higher than the highest under service). If there is no interrupt pending internally, the IPO follows IPI.
' ,
2-138
inter
8274
Non-Vectored Interrupt Timing
SERVICE
ROUTtNE
INTERNAL INTERRUPT
ACCEPTED
;':::::::~LO"W;••~P;.I;'O.;"T~YI;NTn."
••;UP~T'''NW~~.~Cc.C.;";.D~-=-=-=-=-=-~
~::::::==\
1NTERRUPT
(EXTERNAL)
AD
(EXTERNAL)
INTERNAL POINTEA
SETTOREQ2
1N-81AYtCE
(INTERNAL)
EOICOMMAND
(INTERNAL)
170102-22
PRIORITY RESOLUTION:
NON-VECTORED MODE
In non-vectored mode, the MPSC does not respond
to interrupt acknowledge sequences. The INTA input
(pin 27) must be pulled high for proper operation.
The MPSC should be programmed to the Status-Affects-Vector mode, and the CPU should read RR2
(Ch. B) in its service routine to determine which interrupt requires service.
nal in the vectored mode. It inhibits acceptance of
any additional internal interrupts and its leading
edge starts the interrupt priority resolution circuit.
The interrupt priority resolution is ended by the leading edge of the read signal used by the CPU to retrieve the modified vector. The leading edge of read
sets the In-Service latch and forces the external INT
output inactive (high). The internal pointer is reset to
zero after the trailing edge of the read pulse.
NOTE:
In this case, the internal pointer being set to RR2
provides the same function as the internallNTA sig-
That if RR2 is specified but not read, no internal interrupts, regardless of priority, are accepted.
2-139
inter
8274
-=~~
INTA
CPU
i1II'I'
~
i1Ii
6
6
m'f
IMTA
ilia
;po
WI
MPSC
HIGHEST PRIORITY
WI'
INTA
MPSC
1111
6
11m
iP6
MP$C
LOWEST PRIORITY
170102-23
DAISY CHAINING MPSC
In the vectored interrupt mode, multiple MPSC's can
be daisy-chained on the same INT, INTA signals.
These signals, in conjunction with the IPI and IPO
allow a daisy-chain-like interrupt resolution scheme.
This scheme can be configured for either 8085 or
8086/88 based system.
In either mode, the same hardware configuration is
called for. The INT request lines are wire-OR'ed together at the input of a TTL inverter which drives the
INT pin of the CPU. The INTA signal from the CPU
drives aI/ of the daisy-chained MPSC's.
The MPSC drives IPO (Interrupt Priority Output) inactive (high) if fPi (Interrupt Priority Input) is inactive
(high), or if the MPSC has an interrupt pending.
If fPi is active (low), the MPSC knows that all higher
priority MPSC's have no interrupts pending. The fPi
pin of the highest priority MPSC is strapped active
(low) to ensure that it always has priority over the
rest.
MPSC's Daisy-chained on an 8088/86 CPU should
be programmed to the 8088/86 Interrupt mode
(WR2; 04, 03 Ch. A). MPSC's Daisy-chained on an
8085 CPU should be programmed to 8085 interrupt
mode 1 if it is the highest priority MPSC. In this
mode, the highest priority MPSC issues the CALL
instruction during the first INTA cycle, and the interrupting MPSC provides the interrupt vector during
the fol/owing INTA cycles. Lower priority MPSC's
should be programmed to 8085 interrupt mode 2.
MPSC's used alone in 8085 systems should be programmed to 8085 mode 1 interrupt operation.
The IPO of the highest priority MPSC is connected
to the fPi of the next highest priority MPSC, and so
on.
.
2-140
8274
DMA Acknowledge Circuit
DACK o - - - - - - - ,
~,---.......,
~2---.-r-r--~
MULTIPLEXER
DACK3--~t-r_r_-~
Ao
~A~,---------Ao
t-::C:;-s--:-------- A,
t - - - - t ....~----
ES
170102-24
DMATlming
DRQn~
Ao,A"CS
RD, WR
----~X,
\'-------
___________......,.-->C
-------~\\._ _ _ _ _ _ _ _...../
170102-25
DMA OPERATION
Each MPSC can be programmed to utilize up to four·
DMA channels: Transmit Channel A. Receive Channel A. Transmit Channel B. Receive Channel B.
Each DMA Channel has an associated DMA Request line. Acknowledgement of a DMA cycle is
done via normal data read or write cycles. This is
accomplished by encoding the DACK signals to generate Ao. A1. and CS. and multiplexing them with the
normal Ao. A1. and CS signals.
PERMUTATIONS
Channels A and B can be used with different system
interface modes. In all cases it is possible to poll the
MPSC. The following table shows the possible per-
mutations of interrupt. wait. and DMA modes for
channels A and B. Bits D1. Do of WR2 Ch. A determine these permutations.
Permutation
WR2Ch.A
D1
Do
Channel A
ChannelB
0
0
Wait
Interrupt
Polled
Wait
Interrupt
Polled
0
1
DMA
Polled
Interrupt
Polled
1
0
DMA
Polled
DMA
Polled
NOTE:
D1, DO
=
1,1 is illegal.
r----o.-
l
?
".2
"16-A19
01
ALE
DO
A16
>
"tt
Y
STB
'---
~
.... K
~(:("
iiQ
8284A
. . READY
ViR
K!:';iO.~
A~ ,... 0,
1-,....,
r--
-
01
A ..-A
DO
II
srB
1282
~
eLR
1
.>
,
t
~ OE DO~DO,
8282 5TS
T
OE
827
v
Ol,-DI,
J
00 0,
ADD-AD7
HLOA
ill-
ADSTB
0,,-0
iiEiIII
IIHIWA
HLDA
D
HRa
L.. AEN
74LS74
elK
!--
r-
RESET
HOLD
~
II
,.--
.--
'---V
elK
H-t-
~
:''''O~
A.
8~:O ~
B~
~
j.
A8 .15
"8-.15
.....
~
1237
A-A
DRQ 2
~,
ORO,
ilA5C,
RESET
T
:OA
ilA5C, ~
I/OW
READY
elK
~
I--
ORO,
lli!li
01»
Q.
ORO o
~,
-,-~
l.b:o. .--
'r>
MULTIPLEXEA
,
:
1
i
.... It-.
I~
1
- '
ES
-t>o-
a.
....
!:::~I
'!:::
LJ'
I~
(FROM 8205)
~
:Oe
' ......
I'"
I
I
~t--~-----_J
170102-26
NOTE:
The circuit was not designed based on a worst-case timing analysis. Specific implementations should include this timing analysis.
inter
8274
PROGRAMMING HINTS
Transmit Under-run/EOM Latch
This section will describe some useful programming
hints which may be useful in program development.
In SOLC/HOLC, bisync and monosync mode, the
transmit under-run/EOM must be reset to enable the
CRC check bytes to be appended to the transmit
frame or transmit message. The transmit under-run/
EOM latch can be reset only after the first character
is loaded into the transmit buffer. When the transmitter under-runs at the end of the frame, CRC check
bytes are appended to the frame/message. The
transmit under-run/EOM latch can be reset at any
time during the transmission after the first character.
However, it should be reset before the transmitter
under-runs otherwise, both bytes of the CRC may
not be appended to the frame/message. In the receive mode in bisync operation, tl:le CPU must read
the CRC bytes and two more SYNC characters before checking for valid CRC result in RR1.
Asynchronous Operation
At the end of transmission, the CPU must issue "Reset Transmit InterruptiOMA Pending" command in
WRO to reset the last transmit empty request which
was not satisfied. Failing to do so will result in the
MPSC locking up in a transmit empty state forever.
Non-Vectored Mode
In non-vectored mode, the Interrupt Acknowledge
pin (INTA) on the MPSC must be tied high through a
pull-up resistor. Failing to do so will result in unpredictable response from the 8274.
HOLC/SOLC Mode
When receiving data in SOLC mode, the CRC bytes
must be read by the CPU (or OMA controller) just
like any other data field. Failing to do so will result in
receiver buffer overflow. The CRC bytes are not to
be used for CRC verification. Residue bits may be
contained in the first CRC byte. Also, the End of
Frame Interrupt indicates that the entire frame has
been received. At this pOint, the CRC result (RR 1:
06) and residue code (RR1; 03, 02, 01) may be
checked.
Sync Character Load Inhibit
In bisync/monosync mode only, ,it is possible to prevent loading sync characters into'the receive buffers
by setting the sync character load inhibit bit (WR3;
01 = 1). Caution must be exercised in using this
option. It may be possible to get a CRC character in
the received message which may match the sync
character and not get transferred to the receive buffer. However, sync character load inhibit should be
enabled during all pre-frame sync characters so th!3
software routine does not have to read them from
the MPSC.
In SOLC/HOLC mode, sync character load inhibit bit
must be reset to zero for proper operation.
Status Register RR2
RR2 contains the vector which gets modified to indicate the source of interrupt (See the section titled
MPSC Modes of Operation). However, the state of
the vector does not change if no new interrupts are
generated. The contents of RR2 are only changed
when a new interrupt is generated. In order to get
the correct information, RR2 must be read only after
an interrrupt is generated, otherwise it will indicate
the previous state.
Initialization Sequence
The MPSC initialization routine must issue a channel
Reset Command at the beginning. WR4 should be
defined before other registers. At the end of the initialization sequence, Reset External/Status and Error Reset commands should be issued to clear any
spurious interrupts which may have been caused at
power up.
EOI Command
EOI command can only be issued through channel A
irrespective of which channel had generated the interrupt.
Priority in OMA Mode
There is no priority in OMA mode between the following four signals: TxORQ(CHA), RxORQ(CHA),
TxORQ(CHB), RxORQ(CHB). The priority between
these four signals must be resolved by the OMA
controller. At any given time, all four OMA channels
from the 8274 are capable of going active.
2-143
inter
8274
• Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device; This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias .............•........ O·C to + 70·C
Storage Temperature
(Ceramic Package) .......... -65·C to + 150·C
(Plastic Package) ............ - 40·C to + 125°C
Voltage on Any Pin with
Respect to Ground ............ - 0.5V to + 7.0V
D.C. CHARACTERISTICS
Symbol
TA
=
O·C to + 70·C; Vee
+ 5V ± 10%
Min
Max
Units
Input Low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
+2.0
Vee +0.5
V
VOL
Output Low Voltage
+0.45
V
VOH
Output High Voltage
III
Input Leakage Current
±10
10Fl
Output Leakage Current
Icc
Vee Supply Current
Vil
Parameter
=
Test Conditions
10l = 2.0mA
=
=
V
10H
/k A
VIN
±10
/k A
VOUT = Vee to 0.45V
200
mA
+2.4
200/kA
Vee to OV
NOTE:
1. For Extended Temperature EXPRESS. use MIL8274 electrical Parameters.
CAPACITANCE
Symbol
TA = 25·C; Vee = GND = OV
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
CliO
Input/Output Capacitance
Min
2-144
Max
Units
10
pF
fc
Test Conditions
15
pF
20
pF
Unmeasured pins
returned to GND
=
1 MHz
intJ
8274
A.C. CHARACTERISTICS
Symbol
T A = O·C to
+ 70·C; Vcc
Parameter
=
+ 5V ± 10%
Min
Max
Units
tCY
ClK Period
250
4000
ns
tCL
ClK low Time
105
2000
ns
tCH
ClK High Time
105
2000
ns
tr
ClK Rise Time
0
30
ns
tj
ClKFaliTime
0
30
ns
J,
tAR
AO, A 1 Setup to RD
tAO
AO, A 1 to Data Output Delay
0
ns
200
ns
tRA
AO, A 1 Hold after RD i
tRO
RD
tRR
RD Pulse Width
tOF
Output Float Delay
tAW
CS, AO, A 1 Setup to WR
J,
0
ns
tWA
CS, AO, A 1 Hold after WR i
0
ns
tww
WR Pulse Width
250
ns
J,
0
to Data Output Delay
200
ns
ns
120
ns
tow
Data Setup to WR
150
ns
two
Data Hold after WR i
0
ns
tpi
IPI Setup to INTA J,
0
ns
tiP
IPI Hold after INTA i
10
ns
til
INTA Pulse Width
250
ns
tplPO
IPI
100
ns
tlO
INTA J, to Data Output Delay
200
ns
tea
RD or WR to DRQ J,
150
ns
J,
to IPO Delay
tRY
Recovery Time Between Controls
tcw
CS, AO, A 1 to RDYA or RDYs Delay
tOCY
Data Clock Cycle
4.5
tcy
tOCL
Data Clock low Time
180
ns
tOCH
Data Clock High Time
180
tTD
TxC to TxD Delay (x1 Mode)
tos
RxD Setup to RxC i
tOH
RxD Hold after F1xC i
tlTO
TxC to INT Delay
ns
300
140
ns
ns
300
0
ns
ns
140
ns
4
6
tcy
7
10
tcy
tiRO
RxC to INT Delay
tpL
CTS, CD, SYNDET low Time
200
ns
tpH
CTS, CD, SYNDET High Time
200
ns
tlPO
ExternallNT from eTS, CD, SYNDET
2-145
CL
= 150 pF
CL
= 150 pF
ns
250
i
Test Conditions
500
ns
8274
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT,
"J
0,45
2,0
>
TEST
0,8
< )C
2,0
~OINTS
DEVICE
UNDER
TEST
0.8
170102-27
A.C, Tesling; Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0",
170102-28
CL=100pF
CL Includes Jig Capacitance
WAVEFORMS
CLOCK CYCLE
elK
170102-29
READ CYCLE
Cs.AO.Al
1+----.:...-t.D------..1
170102-30
2-146
8274
WAVEFORMS (Continued)
WRITE CYCLE
a~~>{,. ~_____
. . ..
,. d<
170102-31
DMA CYCLE
-
OAa
-,.).--
/
eJ. AO. A1
RoORWR
170102-33
READ/WRITE CYCLE (SOFTWARE POLLED MODE)
CS, AO,,,,1
ADOAWR
1+---------1,,-------1
"'------170102-34
2·147
inter
8274
INTA CYCLE
NOTES:
1. INTA Signal as RD Signal.
2. IPI signal acts as CS signal.
2-148
inter
8274
WAVEFORMS
(Continued)
TRANSMIT DATA CYCLE
......
...
----"ITD----~
IIi'I
170102-35
RECEIVE DATA CYCLE
RoD
170102-36
OTHER TIMING
~~.~ ~.>------"IPL>------0----,PH---. . .~"'---
t
ItpO--Q-I"~___
170102-37
2-149
intJ
82530/82530-6
SERIAL COMMUNICATIONS CONTROLLER (SCC)
• Two Independent Full Duplex Serial
Channels
• Available In Express Version
• Asynchronous Modes
- 5-8 bit Character; Odd, Even or No
Parity; 1, 1.5 or 2 Stop Bits
-Independent Transmit and Receive
Clocks. 1X, 16X, 32X or 64X
Programmable Sampling Rate
- Error Detection: Framing, Overrun
and Parity
- Break Detection and Generation
• On Chip Crystal, Oscillator, Baud-Rate
Generator and Digital Phase Locked
Loop for Each Channel
• Programmable for NRZ, NRZI or FM
Data Encoding/Decoding
• Diagnostic Local Loopback and
Automatic Echo for Fault Detection and
Isolation
• Bit Synchronous Modes
- SDLC Loop/Non-Loop Operation
-CRC-16 or CCITT Generation
Detection
- Abort Generation and Detection
-I-field Residue Handling
- CCITT X.25 Compatible
• System Clock Rates:
- 4 MHz for 82530
- 6 M,Hz for 82530-6
• Max Bit Rate (6 MHz)
- Externally Clocked: 1.5 Mbps
Self-Clocked:
375 Kbps FM CODING
187 Kbps NRZI CODING
93 Kbps Asynchronous
• Interfaces with Any INTEL CPU, DMA or
I/O Processor
.
• Available In 40 Pin DIP and 44 Lead
PLCC
• Byte Synchronous Modes
-Internal or External Character
Synchronization (1 or 2 Characters)
- Automatic CRC Generation and
Checking (CRC 16 or CCITT)
-IBM Bisync Compatible
The INTEL 82530 Serial Communications Controller (SCC) is a dual-channel, multi-protocol data communications peripheral. It is designed to interface high speed communications lines using Asynchronous, Byte synchronous and Bit synchronous protocols to INTEL's microprocessors based systems. It can be interfaced with
Intel's MCS51/96,iAPX86/88/186 and 188 in pOlled, interrupt driven or DMA driven modes of operation.
The SCC is a 40-pin device manufactured using INTEL's high-performance HMOS· II technology.
• HMOS is a patented process of Intel Corporation.
2-150
October 1987
Order Number: 230834-003
inter
82530/82530·6
DBO.7C:=~
DATA
BUS
BUFFERS
CHANNEL A
BAUD
RATE
GENERATOR
TRANSMITTERI
RECEIVER
READ
REGISTERS
ClK
CONTROL
lOGIC'
WRITE
REGISTERS
lEO
lEI
OPERATION
CONTROL
,'!liD.
R.D.
liDYAlREQ"
RDYeiREo.
CHANNElB
1I'I!iC.
'i'IiiC.
DfiiAlliEO"
DTReiREOB
SYSTEM INTERFACE
SERIAL COMMUNICATION
INTERFACE
230834-1
Figure 1.82530 Internal Block Diagram
2·151
inter
82530/82530~6
081
080
083
082
085
084
087
086
!lilT
RtI
, lEO
WR
lEI
Alii
INTA
cs
Vee
ole
IiDYAIA!()A
IiDYslREOs
R'fiCA
SYNCs
cs
GNO
ROY/REOb
RTxCa
RxOa
TRxCa
~s
SYNCb
RTxCb
TxDa
RxOs
TIeD"
Ole
Vee
filiiC A
RXOA
Alii
lEI
INTA
ROY/REOa
SYNCa
GNO
f'liiC A
lEO
NC
TRi"es
OTRA/A!OA
TleOs
imI~REOs
RTSA
rnA
RTSs
CD A
CTSa
elK
COs
230834-43
230834-2'
Figure 2. Pin Configurations
The following section describes the pin functions of the SCC. Figure 2 details the pin assignments.
Table 1. Pin Description
PinNo.
Symbol
DIP
I
Type
Name and Function
PLCC
DBo
DB1,
DB2
DB3
DB4
DB5
DBs
DB7
40
1
1
39
2
38
3
37
4
2
44
3
43
,4
42
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DATA BUS: The Data Bus lines are bi·directional three-state lines
which interface with the system's Data Bus. These lines carry data
and commands to and from the SCC.
INT
5
6
0
INTERRUPT REQUEST: The interrupt signal is activated when the
SCC requests an interrupt. It is an open drain output.
lEO
6
7
0
INTERRUPT ENABLE OUT: lEO is High only if lEI is High and the
CPU is not servicing an SCC interrupt or the SCC is not requesting
an interrupt (Interrupt Acknowledge cycle only). lEO is connected
to the next lower priority device's lEI input and thus inhibits
interrupts from lower priority devices.
lEI
7
8
I
INTERRUPT ENABLE IN: lEI is used with lEO to form an interrupt
daisy chain when there is more than one interrupt-driven device. A
High lEI indicates that no other higher priority device has an
interrupt under service or is requesting an interrupt.
2·152
intJ
82530/82530·6
Table 1. Pin Description (Continued)
Symbol
Pin No.
Type
Name and Function
I
INTERRUPT ACKNOWLEDGE: This signal indicates an active Interrupt
Acknowledge ~Ie. During this cycle, the SCC interrupt daisy chain
settles. When RD becomes active, the SCC places an interrupt vector
on the data bus (if lEI is High). INTA is latched by the rising edge of
CLK.
DIP PLCC
INTA
8
9
,.
+5V Power supply.
Vee
9
10
RDYA/FiEOA
'FtiWs/J!ims
10
30
11
34
0
0
READY/REQUEST: (output, open-drain when programmed for a Ready
function, driven High or Low when programmed for a Request function).
These dual-purpose outputs may be programmed as Request lines for a
DMA controller or as Ready lines to synchronize the CPU to the SCC
data rate. The reset state is Ready.
~A
~s
11
29
12
33
I/O
I/O
SYNCHRONIZATION: These pins can act either as inputs, outputs or
part of the crystal oscillator circuit. In the Asynchronous receive mode
~tal oscillator option not selected), these pins are inputs similar to
and rn:>. In this mode, transitions on these lines affect the state of
the Synchronous/Hunt status bits in Read Register 0 (Figure 9) but
have no other function.
In External Synchronization mode with the crystal oscillator not
selected, these lines also act as inputs. In this mode, ~ must be
driven LOW two receive clock cycles after the last bit in the
synchronous character is received. Character assembly begins on the
risinjbedge of the receive clock immediately preceding the activation of
SYN .
'
In the Internal Synchronization mode (Monosync and Bisync) with the
crystal osciilator not selected, these pins act as 'outputs and are active
only during the part of the receive clock cycle in which synchronous
characters are recognized. The synchronous condition is not latched,
so these outputs are active each time a synchronization pattern is
recognized (regardless of characters boundaries). In SDLC mode, these
pins act as outputs and are valid on receipt of a flag.
RTxCA
RTxCs
12
28
13
32
I
I
RECEIVE/TRANSMIT CLOCKS: These pins can be programmed in
several different modes of operation. In each channel, RTxC may
supply the receive clock, the transmit clock, the clock for the baud rate
generator, or the 'clock for the Digital Phase Locked Loop. These pins
can be programmed for use with the respective SYNC pins as a crystal
oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate
in Asynchronous modes.
RxDA
RxDs
13
27
14
31
I
I
'RECEIVE DATA: These lines receive serial data at standard TTL levels.
TRxCA
TRxCs
14
26
15
30
I/O
I/O
TRANSMIT/RECEIVE CLOCKS: These pins can be programmed in
several different modes of operation. TRxC may supply the receive
clock or the transmit clock in the input mode or supply the output of the
Digital Phase Locked Loop, the crystal oscillator, the baud rate
generator, or the transmit clock in the output mode.
TxDA
TxDs
15
25
16
29
0
0
TRANSMIT DATA: These output signals transmit serial data at
standard TTL levels
J:)i'RA/FiEOA
DTRs/REQs
16
24
19
27
0
0
DATA TERMINAL READY/REQUEST: These outputs follow the state
programmed into the DTR bit. They can also be used as general
purpose outputs or as Request lines for a DMA controller.
POWER:
2-153
intJ
82530/82530-6
Table 1. Pin Description (Continued)
Pin No.
Symbol
Type
Name and Function
20
26
0
0
REQUEST TO SEND: When the Request to Send (RTS) bit in
Write Register 5 is set (Figure 10), the RTS signal goes Low. When
the RTS bit is reset in the Asynchronous mode and Auto Enable is
on, the signal goes High after the transmitter is empty. In
Synchronous mode or in Asynchronous mode with Auto Enable
off, the RTS pin strictly follows the state of the RTS bit. Both pins
can be used as general·purpose outputs.
18
22
21
25
I
I
CLEAR TO SEND: If these pins are programmed as Auto Enables,
a Low on the inputs enables the respective transmitters. If not
programmed as Auto Enables, they may be used as general·
purpose inputs. Both inputs are Schmitt·trigger buffered to
accommodate slow rise·time inputs. The SCC detects pulses on
these inputs and can interrupt the CPU on both logic level
.transitions.
CDA
CDB
19
21
22
24
I
I
CARRIER DETECT: These pins function as receiver enables if
they are programmed for Auto Enables; otherwise they may be
used as general·purpose input pins. Both pins are Schmitt·trigger
buffered to accommodate slow rise time signals. The SCC detects
pulses on these pins and can interrupt the CPU on both logic level
transitions.
ClK
20
23
I
CLOCK: This is the system SCC clock used to synchronize internal
signal.s.
DIP
PLCC
RTSA
RTSB
17
23
CTSA
CTSB
GND
31
35
DIC
32
37
I
DAT~/COMMAND SELECT: This signal defines the type of
information transferred to or from the SCC. A High means data is
transferred; a Low indicates a command.
CS
33
38
I
CHIP SELECT: This signal selects the SCC for a read or write
operation.
AlB
34
39
I
CHANNEL A/CHANNEL B SELECT: This signal selects the
channel in which the read or write operation occurs.
WR
35
40
I
WRITE: When the SCC is selected this signal indicates a write
operation. The coincidence of RD and WR is interpreted as a
reset.
RD
36
41
I
READ: This signal indicates a read operation and when the SCC is
selected, enables the sec's bus drivers. During the Interrupt
Acknowledge cycle, this signal gates the interrup, vector onto the
bus if the SCC is the highest priority device requesting an interrupt.
GROUND
2·154
82530/82530-6
GENERAL DESCRIPTION
The Intel 82350 Serial Communications Controller
(SCC) is a dual-channel, multi-protocol data communications peripheral. The SCC functions as a serialto-parallel, parallel-to-serial convertor/controller.
The SCC can be software-configured to satisfy a
wide range of serial communications applications.
The device contains sophisticated internal functions
including on-chip baud rate generators, digital phase
locked loops, various data encoding and decoding
schemes, and crystal oscillators that reduce the
need for external logic.
In addition, diagnostic capabilities-automatic echo
and local loopback-allow the user to detect and
isolate a failure in the network. They greatly improve
the reliability and fault isolation of the system.
The SCC handles Asynchronous formats, Synchronous byte-oriented protocols such as IBM Bisync,
and Synchronous bit-oriented protocols such as
HDLC and IBM SDLC. This versatile device supports
virtually any serial data transfer application (Terminal, Personal Computer, Peripherals, Industrial Controller, Telecommunication sytem, etc.).
The 82530 can generate and check CRC codes in
any Synchronous mode and can be programmed to
check data integrity in various modes. The SCC also
has facilities for modem control in both channels. In
applications where these controls are not needed,
the modem control can be used for general purpose
I/O.
The Intel 82530 is designed to support Intel's
MCS51/96, iAPX 86/88 and iAPX 186/188 families.
ARCHITECTURE
The 82530 internal structure includes two full-duplex
channels, two baud rate generators, internal control
and interrupt logic, and a bus interface to a non-multiplexed CPU bus. Associated with each channel are
a number of read and write registers for mode control and status information, as well as logic necessary to interface modems or other external devices.
The logic for both channels provides formats, synchronization, and validation for data transferred to
and from the channel interface. The modem control
inputs are monitored by the control logic under program control. All of the modem control signals are
general-purpose in nature and can optionally be
used for functions other than modem control.
The register set for each channel includes ten control (write). registers, two synchronous character
(write) registers, and four status (read) registers. In
addition, each baud rate generator has two (read/
write) registers for holding the time constant that determines the baud rate; Finally, associated with the
interrupt logic is a write register for the interrupt vector accessible through either channel, a write.only
Master Interrupt Control register and three read registers; one containing the vector with status information (Channel B only), one containing the vector
without status (A only), and one containing the Interrupt Pending bits (A only).
The registers for each channel are designated as
follows:
WRO-WR15-Write Registers 0 through 15.
RRO-RR3, RR10, RR12, RR13, RR15-Read Registers 0 through 3, 10, 12, 13, 15.
Table 2 lists the functions assigned to each read or
write register. The SCC contains only one WR2 and
WR9, but they can be accessed by either channel.
All other registers are paired (one for each channel).
DATA PATH
The transmit and receive data path illustrated in Figure 3 is identical for both channels. The receiver has
three 8-bit buffer registers in a FIFO arrangement, in
addition to the 8-bit receive shift register. This
scheme creates additional time for the CPU to service an interrupt at the beginning of a block of highspeed data. Incoming data is routed through one of
several paths (data or CRG) depending on the selected mode (the character length in asynchronous
modes also determines the data path).
The transmitter has an 8-bit transmit data buffer register loaded from the internal data bus and a 20-bit
transmit shift register that can be loaded either from
the synC-Character registers or from the transmit
data register. Depending on the operational mode,
outgoing data is routed through one of four main
paths before it is transmitted from the Transmit Data
output (TxD).
2·155
82530/82530-6
Table 2. Read and Write Register Functions
READ REGISTER FUNCTIONS
RRO
Transmit/Receive buffer status and External status
RR1
RR2
RR3
RR8
RR10
RR12
RR13
RR15
Special Receive Condition status
Modified interrupt vector
(Channel Bonly)
Unmodified interrupt
(Channel A only)
Interrupt Pending bits
. (Channel A only)
WRITE RE~ISTER FUNCTIONS
WRO .CRC initialize, initialization commands for
the various modes, shift right/shift left
command
WR1
WR2
WR3
WR4
Receive buffer
Miscellaneous status
Lower byte of baud rate generator time
constant
Upper byte of baud rate generator time
constant
External/Status interrupt information
WR5
WR6
WR7
WR8
WR9
Transmit/Receive interrupt and data
transfer mode definition
Interrupt vector (accessed through either
channel)
Receive parameters and control
Transmit/Receive miscellaneous parameters and modes
Transmit parameters and controls
Sync characters or SDLC address field
Sync character or SDLC flag
Transmit buffer
Master interrupt control and reset (accessed through either channel)
WR10 Miscellaneous transmitter/receiver control
bits
WR11 Clock Mode control
WR12 Lower Byte of baud rate generator time
constant
WR13 Upper Byte of baud rate generator time
constant
WR14 Miscellaneous control bits
WR15 External/Status interrupt control
2-156
(
CPUIJO
8R GENERATOR
"11
INPUT
c»
C'
N
W
Q
.......
C
N
-
Q
...
C
CD
~
01
.....
0'1
Co)
-
c»
DI
DI
0'1
Co)
'tI
•
DI
:::J'
G)
OPLL
---.L..____
.1
SR GENERATOR OUTPUT
DPlL OUTPUT
fAiC
3
RECEIYE CLOCK
CLOCK
MUX
TRANSMIT CLOCK
OPLL CLOCK
AT,C
8R GENERATOR CLOCK
SYNC
(OSCILLATOR)
230834-3
82530/82530·6
FUNCTIONAL DESCRIPTION
The functional capabilities of the SCC can be described from two different points of view: as a data
communications device, it transmits and receives
data in a wide variety of data communications protocols; as a microprocessor peripheral, it interacts with
the CPU and provides vectored interrupts and handshaking signals.
DATA COMMUNICATIONS
CAPABILITIES
The SCC provides two independent full-duplex
channels programmable for use in any common
asynchronous or synchronous data-communications
protocol. Figure 4 and the following description briefly detail these protocols.
Asynchronous Modes
Transmission and reception can be accomplished
independently on each channel with five to eight bits
per character, plus optional even or odd parity. The
transmitter can supply one, one-and-a-half or two
stop bits per character and can provide a break output at any time. The. receiver break-detection logic
interrupts the CPU both at the start and at the end of
. a received break. Reception is protected from
spikes by a transient spike-rejection mechanism that
. checks the signal one-half a bit time after a Low
level is detected on the receive data input (RxDA or
RxDs). If the Low does not persist (as in the case of
a transient), the character assembly process does
not start.
Framing errors and overrun errors are detected and
buffered together with the partial character on which
they occur. Vectored interrupts allow fast servicing
of error conditions using dedicated routines. Furthermore, a built-in checking process avoids the interpretation of a framing error as a new start bit: a framing error results in the addition of one-half a bit time
to the point at which the search for the next start bit
begins.
The SCC does not require symmetric transmit and
receive clock signals-a feature allowing use of the
wide variety of clock sources. The transmitter and
receiver can handle data at a rate of 1, Yt6, %2 or
%4 of the clock rate supplied to the receive and
transmit clock inputs. In the asynchronous modes, a
data rate equal to the clock rate, 1x mode, requires
external synchronization. In asynchronous modes,
the SYNC pin may be programmed as an input used
for functions such as monitoring a ring indicator.
MARKING LINE
MARKING LINE
SYNC
DATA
:;
::
DATA
CRC,
CRC,
DATA
CRC,
CRC.
DATA
CRC,
CRC,
CRC,
CRC,
MONOSVNC
SYNC
DATA
SYNC
,
SIGNAL
FLAG
ADDRESS
I
I
DATA
BISYNC
;;
EXTERNAL SYNC
INFO:~ATlON
FLAG
SDLCIHDLCIX.25
230834-4
Figure 4. see Protocols
2-158
inter
82530/82530-6
sisting of continuous flag characters or a steady
marking condition.
Synchronous Modes
The SCC supports both byte-oriented and bit-oriented synchronous communication. Synchronous-byteoriented protocols can be handled in several modes
allowing character synchronization with a 6-bit or
8-bit synchronous character (Monosync), any 12-bit
or 16-bit synchronous pattern (Bisync), or with an
external synchronous signal. Leading synchronous
characters can be removed without interrupting the
CPU.
If a transmit underrun occurs in the middle of a message, an external status interrupt warns the CPU of
this status change so that an abort may be issued.
The SCC may also be programmed to send an abort
itself in case of an underrun, relieving the CPU of
this task. One to eight bits per character can be sent
allowing reception of a message with no prior information about the character structure in the information field of a frame.
5- or 7-bit synchronous characters are detected with
8- or 16-bit patterns in the SCC by overlapping the
larger pattern across multiple incoming synchronous
characters as shown in Figure 5.
The receiver automatically. acquires synchronization
on the leading flag of a frame in SOLC or HOLC
mode and provides a synchronization Signal on the
SYNC pin (an interrupt can also be programmed).
The receiver can be programmed to search for
frames addressed by a single byte (or four bits within
a byte) of a user-selec.ted address or to a global
broadcast address. In this mode, frames not matching either the user-selected or broadcast address
are ignored. The number of address bytes can be
extended under software control. For receiving data,
an interrupt on the first received character, or an
interrupt on every character, or on special condition
only (end-of-frame) can be selected. The receiver
automatically deletes all Os inserted by the transmitter during character assembly. CAC is also calculated and is automatically checked to validate frame
transmission. At the end of transmission, the status
of a received frame is available in the status registers. In SOLC mode, the SCC must be programmed
to use the SOLC CAC polynomial, but the generator
and checker may be preset to all 1s or all Os. The CAC
is inverted before transmission and the receiver
checks against the .bit pattern 0001110100001111.
CAC checking for Synchronous byte-oriented mode
is delayed by one character time so that the CPU
may disable CAC checking on specific characters.
This permits the implementation of protocols such
as IBM Bisync.
Both CAC-16 (X 16
(X16
+
X12
+
X5
+ X15 + X2 + 1) and CCITT
+ 1) error checking polynomials
are supported. Either polynomial may be selected in
all synchronous modes. Users may preset the CAG
generator and checker to all 1s or all Os. The SCC
also provides a feature that automatically transmits
CAC data when no other data is available for transmission. This allows for high-speed transmissions
under OMA control, with no need for CPU intervention at the end of a message. When there is no data
or CAC to send in synchronous modes, the transmitter inserts 6-, 8-, or 16-bit synchronous characters,
regardless of the programmed character length.
The SCC supports synchronous bit-oriented protocols, such as SOLC and HOLC, by performing automatic flag sending, zero insertion, and CAC generation. A special command can be used to abort a
frame in transmission. At the end of a message, the
SCC automatically transmits the CAC and trailing
flag when the transmitter underruns. The transmitter
may also be programmed to send an idle line con-
NAZ, NAZI or FM coding may be used in any 1X
mode. The parity options available in asynchronous
modes are available in synchronous modes.
The SCC can be conveniently used under OMA control to provide high-speed reception or transmission.
SBITS
SYN~
-----....
SYNC
DATA
DATA
DATA
DATA
....---
---~-16
230834-5
Figure 5. Detecting 5- or 7-Blt Synchronous Characters
2-159
82530/82530-6
In reception, for example, the SCC can interrupt the
CPU when the first character of a message is received. The CPU then enables the OMA to transfer
the message to memory. The SCC then issues an
end-of-frame interrupt and the CPU can check the
status of the received message. Thus, the CPU is
freed for other service while the message is being
received. The CPU may also enable the OMA first
and have the SCC interrupt only on end-of-frame.
This procedure allows all data to be transferred via
OMA.
SOLe LOOP MODE
The SCC supports SOLC Loop mode in addition to
normal SOLC. In a loop topology, there is a primary
controller station that manages the message traffic
flow and any number of secondary stations. In Loop
mode, the SCC performs the functions of a secondary station while an SCC operating in regular SOLC
mode can act as a controller (Figure 6).
insertion during messages, this bit pattern is unique
and easily recognized.
When a secondary station has a message to transmit and recognizes an EOP on the line, it changes
the last binary one of the EOP to a zero before
transmission. This has the effect of turning the EOP
into a flag sequence. The secondary station now
places its message on the loop and terminates the
message with an EOP. Any secondary stations further down the loop with messages to transmit can
then append their messages to the message of the
first secondary station by the same process. Any
secondary stations without messages to send merely echo the incoming messages and are prohibited
from placing messages on the loop (except upon
recognizing an EOP).
SOLC Loop mode is a programmable option in the
SCC. NAZ, NAZI, and FM coding may all be used in
SOLC Loop mode.
BAUD RATE GENERATORS
Each channel in the SCC contains a programmable
Baud rate generator. Each generator consists of two
8-bit time constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop on
the output producing a square wave. On startup, the
flip-flop on the output is set in a High state, the value
in the time constant register is loaded into the counter, and the counter starts counting down. The output of the baud rate generator toggles upon reaching zero, the value in the time constant register is
loaded into the counter, and the process is repeated. The time constant may be changed at any time,
but the new value does not take effect until the next
load of the counter.
The output of the baud rate generator may be used
as either the transmit clock, the receive clock, or
both. It can also drive the digital phase-locked loop
(see next section).
230834-6
Figure 6. An SOLe Loop
A secondary station in an SOLC Loop is always listening to the messages being sent around the loop,
and in fact must pass these messages to the rest of
the loop by retransmitting them with a one-bit-time
delay. The secondary station can place its own message on the loop only at specific times. The controller signals that secondary stations may .transmit
messages by sending a special character, called an
EOP (End of Poll). around the loop. The EOP character is the bit pattern 11111110. Because of zero
If the receive clock or transmit clock is not programmed to come from the TAxC pin, the output of
the baud rate generator may be echoed out via the
TAxC pin.
The following formula relates the time constant to
the baud rate. (The baud rate is in bits/second, the
BA clock frequency is in Hz, and clock mode is 1,
16, 32, or 64.)
time
constant
2-160
.,..--,:-S,;..;R..;,C..;,lo..:,ck,;..;f,;..;re,;..;q,-:u..:.e;.,.nc,-"Y_:- _ 2
2.X baud rate x clock mode
intJ
82530/82530-6
In NRZ encoding, a 1 is represented by a High level
and a 0 is represented by a Low level. In NRZI encoding, as 1 is represented by no change in level
and a 0 is represented by a change in level. In FM1
(more properly, bi-phase mark) a transition occurs at
the beginning of every bit cell. A 1 is represented by
an additional transition at the center of the bit cell
and a 0 is represented by no additional transition at
the center of the bit cell. In FMo (bi-phase space), a
transition occurs at the beginning of every bit cell. A
o is represented by an additional transition at the
center of the bit cell, and a 1 is represented by no
additional transition at the center of the bit cell. In
addition to these four methods, the SCC can be
used to decode Manchester (bi-phase level) data by
using the DPLL in the FM mode and programming
the receiver for NRZ data. Manchester encoding always produces a transition at the center of the bit
cell. If the transition is 0/1 the bit is a O. If the transition is 110 the bit is a 1.
Table 3. Time Constant Values for Standard
Baud Rates at BR Clock = 3 9936 MHz
Rate
Time Constant
Error
(BAUD)
(decimal notation)
19200
9600
7200
4800
3600
2400
2000
1800
1200
600
300
150
134.5
110
75
50
102
206
275
414
553
830
996
1107
1662
3326
6654
13310
14844
18151
26622
39934
0.06%
0.04%
0.12%
0.03%
0.0007%
0.0015%
-
DIGITAL PHASE LOCKED LOOP
AUTO ECHO AND LOCAL LOOPBACK
The SCC contains a digital phase locked·loop
(DPLL) to recover clock information from a datastream with NRZI or FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZI) or 16 (FM)
times the data rate. The DPLL uses this clock, along
with the datastream, to construct a clock for the
data. This clock may then be used as the SCC receive clock, the transmit clock, or both.
For NRZI coding, the DPLL counts the 32X clock to
create nominal bit times. As the 32X clock is counted, the DPLL is searching the incoming datastream
for edges (either 1/0 or 0/1). Whenever an edge is
detected, the DPLL makes a count adjustment (during the next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from 1 to 31,
but with a cycle corresponding to two bit times.
When the DPLL is locked, the clock edges in the
datastream should occur between counts 15 and 16
and between counts 31 and O. The DPLL looks for
edges only during a time centered on the 10/16
counting transition.
.,
The SCC is capable of automatically echoing every. thing it receives. This feature is useful mainly in
asynchronous modes, but works in synchronous and
SDLC modes as well. In Auto Echo mode TxD is
RxD. Auto Echo mode can be used with NRZI or FM
encoding with no additional delay, because the datastream is not decoded before retransmission. In
Auto Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this input
can still cause interrupts if programmed to do so). In
this mode, the transmitter is actually bypassed and
the programmer is responsible for disabling transmitter interrupts and READYIREQUEST on transmit.
The SCC is also capable of local loopback. In this
mode, TxD is RxD just as in Auto Echo mode. However, in Local Loopback mode, the internal transmit
data is tied to the internal receive data and RxD is
!9!lored (except to be echoed out via TxD). CTS and
CD inputs are also ignored as transmit and receive
enables. However, transitions on these inputs can
still cause interrupts. Local Loopback works in asynchronous, synchronous and SDLC modes with NRZ,
NRZI or FM coding of the data stream.
The 32X clock for the DPLL can be programmed to
come from either the RTxC input or the output of the
baud rate generator. The DPLL output may be programmed to be echoed out of the SCC via the TRxC
pin (if this pin is not being used as an input).
DATA ENCODING
The SCC may be programmed to encode and decode the serial data in four different ways (Figure 7).
2-161
SERIAL BIT RATE
To run the 82530 (4 MHz/6 MHz) at 1/1.5 Mbps the
receive and transmit clocks must be externally generated and synchronized to the system clock. If the
serial clocks (RTxC and TRxC) and the system clock
(CLK) are asynchronous, the maximum bit rate is
880 Kbps/1.3 Mbps. For self-clocked operation, i.e
using the on chip DPLL, the maximum bit rate is
125/187 Kbps if NRZI coding is used and 250/375
Kbps if FM coding is used.
inter
82530/82530-6
I
I
I
DATAl
BIT CELL LEVEL:
;---;----;
~_ _....:
HIGH"'
LOW"O
~_ _....;
NO CHANGE" ,
CHANGE" 0
BIT CENTER TRANSITION:
TRANSITION" ,
~--~I NO TRANSITION" 0
FM,
(BIPHASE MARK)
NO TRANSITION" ,
FMo
(BIPHASE SPACE) \ -_ _-1
TRANSITION" 0
HIGH .... LOW= 1
LOW ..... HIGH" 0
230834-7
Figure 7. Data Encoding Methods
Table 4. Maximum Bit Rates
Mode
Serial clocks
generated
externally
Self-clocked
operation
NRZI
FM
ASYNC
System
Clock
System Clockl
Serial Clock
Serial Bit Rate
4MHz
4
1 Mbps
6MHz
4
1.5 Mbps
4MHz
4.5
880 Kbps
6MHz
4.5
1.3 Mbps
4MHz
6MHz
4MHz
6MHz
4MHz
6MHz
32
32
16
16
16
16
125 Kbps
187 Kbps
250 Kbps
375 Kbps
62.5 Kbps
93.75 Kbps
110 INTERFACE CAPABILITIES
The SCC offers the choice of Polling, Interrupt (vectored or nonvectored) and Block Transfer modes to
transfer data, status, and control information to and
from the CPU. The Block Transfer mode can be implemented under CPU or DMA control.
POLLING
All interrupts are disabled. Three status registers in
the SCC are automatically updated whenever any
Conditions
Serial clocks synchronized with system
clock. Refer to parameter # 3 and 10 in
general timings.
Serial clocks synchronized with system
clock. Refer to parameter # 3 and # 10
in general timings.
Serial clocks and system clock
asynchronous.
Serial clocks and system clock
asynchronou,s
function is performed, For example, end-of-frame in
SDLC mode sets a bit in one of these status registers. The idea behind polling is for the CPU to periodically read a status register until the register contents indicate the need for data to be transferred.
Only one register needs to be read; depending on its
contents, the CPU either writes data, reads data, or
continues. Two bits in the register indicate the need
for data transfer. An alternative is a poll of the Interrupt Pending register to determine the source of an
interrupt. The status for both Channels resides in
one register.
2-162
inter
82530/82530-6
INTERRUPTS
When a SCC responds to an Interrupt Acknowledge
signal (INTA) from the CPU, an interrupt vector may
be placed on the data bus. This vector is written in
WR2 and may be read in RR2A or RR2B (Figures 9
and 10).
To speed interrupt response time, the SCC can
modify three bits in this vector to indicate status. If
the vector is read in Channel A, status is never included; if it is read in Channel B, status is always
included.
Each of the six sources of interrupts in the SCC
(Transmit, Receive and External/Status interrupts in
both channels) has three bits associated with the
interrupt source: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Operation of the IE bits is straightforward. If the IE bit is set
for a given interrupt source, then that source can
request interrupts. The exception is when the MIE
(Master Interrupt Enable) bit in WR9 is reset and no
interrupts may be requested. The IE bits are writeonly.
The other two bits are related to the interrupt priority
chain (Figure 8). As a peripheral, the SCC may request an interrupt only when no higher-priority device is requesting one, e.g., when lEI is High. If the
device in question requests an interrupt, it pulls
down INT. The CPU then responds with INTA, and
the interrupting device places the vector on the data
bus.
In the SCC, the IP bit signals a need for interrupt
servicing. When an IP bit is 1 and the lEI input is
High, the INT output is pulled Low, requesting an
interrupt. In the SCC, if the IE bit is not set by enabling interrupts, then the IP for that source can never be set. The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request is being
serviced. If an IUS is set, all interrupt sources of lower priority in the SCC and external to the SCC are
prevented from requesting interrupts. The internal
interrupt sources are inhibited by the state of the
internal daisy chain, while lower priority devices are
inhibited by the lEO output of the SCC being pulled
Low and propagated to subsequent peripherals. An
IUS bit is set during an Interrupt Acknowledge cycle
if there are no higher priority devices requesting interrupts.
There are three types of interrupts: Transmit, Receive and External/Status interrupts. Each interrupt
type is enabled under program control with Channel
A having higher priority than Channel B, and with
Receiver, Transmit and External/Status interrupts
prioritized in that order within each channel. When
the Transmit interrupt is enabled, the CPU is interrupted when the transmit buffer becomes empty.
(This implies that the transmitter must have had a
data character written into it so that it can become
empty.) When enabled, the receiver can interrupt the
CPU in one of three ways:
• Interrupt on First Receive Character or Special
Receive condition.
• Interrupt on all Receive Characters or Special •
Receive. condition.
• Interrupt on Special Receive condition only.
Interrupt-on-First-Character or Special-Condition
and Interrupt-on-Special-Condition-Only are typically
used with the Block Transfer mode. A Special-Receive-Condition is one of the following: receiver
overrun, framing error in Asynchronous mode, Endof-Frame in SOLC mode and, optionally, a parity
error. The Special-Receive-Condition interrupt is different from an ordinary receive character available
interrupt only in the status placed in the vector
sce
scc
HIGHEST PRIORITY
sec
LOWEST PRIORITY
+5V
DBO-DB7
iNf
INTA ~--~~----------4-------------------~
__------------____
~
+5V
230834-8
Figure 8. Daisy Chaining SCC's
2-163
82530/82530-6
06 = 0) or as a request line in the DMA Block
Transfer mode (WR1; 06 = 1). To a DMA controller,
the SCC REQUEST output indicates that the SCC is
ready to transfer data to or from memory. To the
CPU, The READY line indicates that the SCC is not
ready to transfer data, thereby~uesting that the
CPU extend the 1/0 cycle. The DTRIREQUEST line
allows full-duplex operation under DMA control.
during the Interrupt-Acknowledge cycle. In Interrupt
on First Receive Character, an interrupt can occur
from Special Receive conditions any time after the
first receive character interrupt.
The main function of the ExternallStatus interrupt is
to monitor the signal transitions of the CTS, CD, and
SYNC pins; however, an ExternallStatus interrupt is
also caused by a Transmit Underrun condition, or a
zero count in the baud rate generator, or by the detection of a Break (asynchronous mode), Abort
(SDLC mode) or EOP (SDLC Loop mode) sequence
in the data stream. The interrupt caused by the
Abort or EOP has a special feature allowing the SCC
to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the
proper termination of the current message, correct
initialization of the next message, and the accurate
timing of the Abort condition in external logic in
SDLC mode. In SOLC Loop mode this feature allows
secondary stations to recognize the wishes of the
primary station to regain control of the loop during a
poll sequence.
PROGRAMMING
Each channel has fifteen Write registers that are individually programmed from the system bus to configure the functional personality of each channel.
Each channel also has eight Read registers from
which the system can read Status, Baud rate, or Interrupt information.
Only the four data registers (Read, Write for channels A and B) are directly selected by a High on the
DIG input and the appropriate levels on the RD, WR
and AlB pins. All other registers are addressed indirectly by the content of Write Register 0 in conjunction with a Low on the DIG input and the appropriate
levels on the RD, WR and AlB pins. If bit 3 in WWO
is 1 and bits 4 and 5 are 0 then bits 0, 1, 2 address
the higher registers 8 through 15. If bits 3, 4, 5 contain a different code, bits 0, 1, 2 address the lower
registers 0 through 7 as shown on Table 5.
CPU/DMA BLOCK TRANSFER
, The SCC provides a Block Transfer mode to accommodate CPU block transfer functions and DMA controllers. The Block Transfer mode uses the READY I
REQUEST output in conjunction with the FiEADYI
REQUEST bits in WR1. The READYIREQUEST output can be defined under software control as a
READY line in the CPU Block Transfer mode (WR1;
Writing to or reading from any register except RRO,
WRO and the Data Registers thus involves two operations.
Table 5. Register Addressing
O/C "Point High"
Code in WRO
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Either Way
Not True
Not True
Not True
Not True
Not True
Not True
Not Tru!3
Not True
True
True
True
True
True
True
True
True
02
01
DO
Write
Register
Read
Register
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data
0
1
2
3
4
5
6
7
Data
Data
0
1
2
3
(0)
(1)
(2)
(3)
Data
9
-
10
11
12
13
14
15
10
(15)
12
13
(10)
15
InWRO
2-164
inter
82530/82530·6
First write the appropriate code into WRO, then follow this by a write or read operation on the register
thus specified. Bits 0 through 4 in WWO are automatically cleared after this operation, so that WWO then
points to WRO or RRO again.
Channel AlChannel B selection is made by the AlB
input (High = A, Low = B)
The system program first issues a series of commands to initialize the basic mode of operation. This
is followed by other commands to qualify conditions
within the selected mode. For example, the Asynchronous mode, character length, clock rate, number of stop bits, even or odd parity might be set first.
Then the interrupt mode would be set, and finally,
receiver or transmitter enable.
READ REGISTERS
The SCC contains eight read registers (actually nine,
counting the receive buffer (RRB) in each channel).
Four of these may be read to obtain status information (RRO, RR1, RR10, and RR15). Two registers
(RR12 and RR13) may be read to determine the
baud rate generator time constant. RR2 contains either the unmodified interrupt vector (Channel A) or
the vector modified by status information (Channel
B). RR3 contains the Interrupt Pending (IP) bits
(Channel A). Figure 9 shows the formats for each
read register.
The status bits of RRO and RR1 are carefully
grouped to simplify status monitoring: e.g. when the
interrupt vector indicates a Special Receive Condition interrupt, all the appropriate error bits can be
read from a single register (RR 1).
WRITE REGISTERS
The SCC contains 15 write registers (16 counting
WR8, the transmit buffer) in each channel. These
write registers are programmed separately to configure the functional "personality" of the channels. In
addition, there are two registers (WR2 and WR9)
shared by· the two channels that may be accessed
through either of them. WR2 contains the interrupt
vector for both· channels, while WR9 contains the
interrupt control bits. Figure 10 shows the format of
each write register.
RI CHAIIACTER AVAILABLE
~
ZERO COUNT
'--_ _ _ TI BUFFER EMPTY
'--_ _ _ _ _ CD
_ _ _ _ _ _ _ IYNClHUNT
~--------~S
....- - - - - - - - - - TI UNDERRUNIEDM
' - - - - - - - - - - - - - BREAK/ABORT
230834-9
ALL SENT
RESIDUE COOE 2
L -_ _ _ RESIDUE CODE 1
' - - - - - - - RESIDUE CODE 0
' - - - - - - - - - MRITY ERROR
....- - - - - - - - - RI OVERRUN ERROR
' - - - - - - - - - - - - CRClFRAMING ERROR
~------------ END OF FRAME (SDLC)
230834-10
Figure 9. Read Register Bit Functions
2-165
inter
82530/82530-6
Yo
VI
'-----II,
' - - - - - - - Y3
INTEIIIIUPT VECTOII·
~---------~
' - - - - - - - - - - - 'Is
~-----------------'"
~----------------------~
·MOOIFIED IN B CHANNEL
230834-11
CHANNEL B EXT/STAT .,.
CHANNEL B T.IP"
'-----CHANNEL 811• .,·
'-------CHANNEL A EXT/STAT.,·
' - - - - - - - - - C H A N N E L AT• .,·
' - - - - - - - - - - - C H A N N E L A II.IP"
~------------------O
'--------------------------0
·ALWAYS 0 IN 8 CHANNEL
230834-12
o
ON LOOP
~------- 0
~----------- 0
~------------- LOOP BINDING
~----------------O
-_
--_
-_
-_
--_
-_
- TWO
CLOCKSMISSING
MIllING
L..._'_
__
___
ONE CLOCK
230834-13
Figure 9. Read Register Bit FUnctions (Continued)
2-166
inter
82530/82530·6
TCa
TC,
TCz
TC3
TC.
LOWER BYTE OF
TIME CONSTANT
TC,
TC.
TC,
230834-14
TC,
TC9
' - - - - - TC,o
' - - - - - - - TCn
.....- - - - - - - - TC,z
UPPER BYTE OF
TIME CONSTANT
' - - - - - - - - - - - TC'3
' - - - - - - - - - - - - - TC,.
' - - - - - - - - - - - - - - - TC,s
230834-15
ZERO COUNT IE
.....----0
.....- - - - - - C D I E
' - - - - - - - - - SYNC/HUNT IE
.....- - - - - - - - - - C T S I E
' - - - - - - - - - - - - - Tx UNDERRUNlEOM IE
' - - - - - - - - - - - - - - - BREAK/ABORT IE
Figure 9. Read Register Bit Functions (Continued)
2-167
230834-16
82530/82530-6
WRITE REGISTER 0
IDr
De
Ds
I
D31 D2
D_
I
D,
Do
I
REGISTER
I
I
0
0
Oor
,
1
10r
0
0
0
1
1
0
,
30r
0
40r
1
0
1
50r
,
1
0
6 or
0
0
1
0
1
2 or
,
70r
0
0
0
NULL CODE
0
0
1
0
1
0
POINT HIGH REGIST
RESET EXTISTATUS INTERRUPTS
0
1
1
1
0
0
SEND ABORT
ENABLE INT ON NEXT Rx CHARACTER
RESET Tx INT PEND ING
1
0
1
1
1
0
ERROR RESET
t
1
1
RESET HIGHEST IUS·
.
CHANNEL·A ONLY
0
0
NULL CODE
0
1
RESET Rx CRC CHECKER
1
0
RESET T. CRC GENERATOR
1
1
RESET T. UNDERRUNlEOM LATCH
230834-17
WIlITE IIEGISTEII'
EXT. INT ENABLE
T. INT ENABLE
'-----_TY'I$ SPECIAL CONDITION
o
0
II. INT DISABLE
o
,
RalNT ON,.FIRS~ CHARACTEII 011 SPECIAL CONDITION
......+~o"",INT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
'--......._'..IRa INT ON SPECIAL CONDITION ONLY
'------~REJ~Y/DMAREQUESTONIIECEIVEITRANSMIT
....--------READYIDMA ":QUEST FUNCTION
'-----------flIEADY/DMA REQUEST ENABLE
230834-19
Figure 10. Write Register Bit Functions
2·168
inter
82530/82530-6
V,
V2
'-------V3
INTERRUPT VECTOR
' - - - - - - - - - - V.
' - - - - - - - - - - - Vs
~-------------------~
'----------------- ~
230834-21
RIENAILE
SYNC CHARACTER LOAD INHIIIT
' - - - - - - - - ADORElllEARCH MODE (SOLC)
' - - - - - - - - HI CRC ENAILI
....- - - - - - - - - ENTER HUNT MODE
' - - - - -_ _ _ _ _ _ _ _ AUTO ENAILES
o
o
1
0
1
0
RIIIITIiCHAMCTER
RI 7 IIT11CHAMCTER
RI • IITIICHARACTER
~......_'... RI IIITliCHARIoCTER
230834-18
WRm REGISTER 4
IDr
De
lis
04 03 0210,1001
~
0
0
1
1
0
0
0
1
1
0
1
1
PARITY ENABLE
PARITY EVEN/ODD
0
1
SYNC MODE SENABLE
0
1
1'" STOP liTs/CHARACTER
2 STOP BITS!CHARACTER
ISTOPBIT/CHARACTER
0
0
0
1
1
0
• liT SYNC CHARACTER
11 BIT SYNC CHARACTER
SOLC MODE (01111110 FLAG)
1
1
EXTERNAL SYNC MODE
XI CLOCK MODE
XII CLOCK MODE
X32 CLOCK MODE
X84 CLOCK MODE
230834-20
Figure 10. Write Register Bit Functions (Continued)
2-169
825301.82530-6
T. CAe ENAIIU
'RflI '
~-------~~.
T. ENAJILE
...._ ~-----_ _ _ _ _ _ _ SENDIREAK
o
o
0
1
o
T•• IITI (OR LESS)lCHARACTER
T. 7 IITS/CHARACTER
T•• IITS/CHARACTER
~~~-t T•• IITs/CHARACTER
~________________ DTR
, 230834-22
SYNC,
SYNC,
SYNC,
SYNCa
ADR7
ADA,
=:
SYNc.
SYNCz
ADIIe
ADR,
SYNC,
SYNC,
SYNC.
SYNC,
ADR,
ADA,
SYNC.
SYNc.
SYNc.
SYNCo
AD",
AD",
SYNCs
SYNCa
SYNCs
1
ADRs
SYNCz
SYNCs
SYNCs
1
ADRz
SYNC,
SYNC,
SYNC,
1
ADA,
SYNCo
SYNCo
lYNCo
1
ADAo
X
X
X
X
MONOSYNC 8 BITS
MONOIYNC 8 BITS
BISYNC ,. BITS
BISYNC 12 BITS
SOLe
SDLe (ADDRESS RANGE)
230834-23
SYNC?
SYNC.
SYNC,s
SYNCl1
0
SYNC.
SYNC4
SYNC'4
SYNC,o
1
SYNC,
SYNCs
SYNC'3
SYNC,
1
SYNC4
SYNCZ
SYNC,z
SYNC,
1
SYNCs
SYNC,
SYNCl1
SYNC,
1
SYNCs:
SYNCo
SYNC,o
SYNCo
"
SYNC,
X
SYNCt
SYNC,
1
SYNCo
X
SYNC,
SYNC4
0"
MONOSYNC 8 BITS
MONOSYNC. BITS
BISYNC ,. BITS
BISYNC 12 BITS
SDLC
230834-24
Figure 10. Write Register Bit Functions (Col)tinued)
2·170
82530/82530·&
VECTOR INCLUDE ITATUI
NO VECTOR
' __ _ _ _ DlIAllLE I.OW&RCHAlN
.....- - - - - - I I A I T I R INTERRUPT ENAllLE
'--------ITATUIHlaH/lI'I'lTIBmw
' - - - - - - - - - - NON-VECTORmIlODE'
CHANNEL RElET.
CHANNEL RElET A
fORCE HAROWARE RElET
230834-25
'See 82530 Technical User's Manual for details of this mode.
(Document # 230925-002 or -003)
WAITE REGISTEA 10
l 0,
D.
0,
I I 0.1 0, I I I
D.
D.
Do
~
• liTIAlT SYNC
LOOP MODE
AIOATJI'tllI ON UNDERIIUN
IIAIIK/~ IDLE
GO ACTIVE ON POLL
0
0
NAZ
0
1
NAZI
1
0
fMl (TAANSMISSION
1
1
fMO (TAANSMISSION 0)
1)
CRC PRESET I/O
230834-27
TRANSMIT CLOCK • ~ lOIN
_TCLOCK' ~ PIN
TIIAHIMIT CLOCK' IA GENERATOII DIITI'UT
_ I T CLOCK ' D'LL OUTPUT
IIICIlVE CLOCX • III O...RATOR OUTPUT
.....----------------------.. ~xnwNOx~
Figure 10, Write Register Bit Functions (Continued)
2-171
230834-29
82530/82530-6
'---- :~: I
TC2
TC,
LOWER IYTE OF
TC. \ TIME CONSTANT
' - - - - - - - - - - - - TCS
~------------------------~---------------------------
TC,
TCf
230834-26
WRITE REGISTER 13
I~I~I~I~I~I~I~I~I
I
L
TC,
TC,
1
TC,o
TCn
UPPER IYTE OF
TCu \ TIME CONSTANT
TCu
TC,.
TCU
230834-28
WRITt! IIEGISTEIi ,.
I~
Itt
~
I I I I I I
D.
D3
D2
D,
Do
~
III GENERATOII ENAILE
III GENERATOII SOUIICE
15ft REOUEST FUNCTION
AUTO ECHO
LOCAL LOOPIACK
0
0
0
0
0
0
,
,
,
,
, ,
,
,
,
,
0
0
0
0
0
, ,
0
NULL COMMAND
ENTEII SEARCH MODE
IIIIET MISSING CLOCK
DISAILE DPLL
SET SOUIICE ' IR GENE RAT OR
SET SOURCE ' IIf'i(!
SETFMMODE
SET NIIZI MODE
230834-30
Figure 10. Write Register Bit Functions (Continued)
2-172
inter
82530/82530-6
o
ZIRO COUNT II
~---O
~-----CDII
' - - - - - - - - - IYNC/HUNT II
' - - - - - . . . : . - - - - - CTIII
~---------- TaUNDllIlUJNlIOM II
~-------------.III~AlD~11
230834-31
Figure 10. Write Register Bit Functions (Continued)
82530 TIMING
The SCC generates internal control signals from WA
and AD that are related to ClK. Since ClK has no
phase relationship with WA and AD, the circuitry
generating these internal control signals must provide time for metastable conditions to disappear.
This gives rise to a recovery time related to ClK.
The recovery time applies only between bus transactions involving the SCC. The recovery time required for pro~ operation is specified from the rising edge of WA or AD in the first transaction in-
volving the SCC to the fal\ing edge of WA or AD in
the second transaction involving the SCC. This time,
TREC must be at least 6 ClK cycles plus 130 ns, for
the 82530-6.
Read Cycle Timing
Figure_11 iIIustr!tes Aead cycle timi~ddresses
on AlB and D/C and the status on INTA must remain stable throughout the cycle. If CS fal\s after AD
fal\s or if it rises before AD rises, the effective AD is
shortened.
W~~C __________~)(~_________________A_DD_R_E_S_S_~_L_ID________________-J)(~
\----/
\
\'------~/
DBO-DBl
_____
----------------~-----~(~____________'X
DATA VALID
»)-----230834-32
Figure 11. Read Cycle Timing
2-173
82530/82530-6
Write Cycle Timing
Interrupt Acknowledge Cycle Timing
Figure 12 illustrates Write cycle timi~ddresses
on AlB and DIG and the status on INTA must remain stable throughout the ~e. If es falls after
WR falls or if it rises before WR rises, the effective
WR is shortened.
Figure 13 illustrates Inter!:!:!ELAcknowledge cycle
timing. Between the time INTA goes Low and the
falling edge of RD, the internal and externallEI/IEO
daisy chains settle. If there is an interrupt pending in
the sec and rEI is High when AD falls, the Acknowledge cycle is intended .for the sec. In this case, the
may be programmed to respond to AD Low by
placing its interrupt vector on 00-07 and it then sets
the appropriate Interrupt-Under-Service internally.
sec
X
AlB, DIe
iNi'A
X
ADDRESS VALID
I
ll"S
\
/
\
WR
DBD-DB7
\
I
(
DATA VALID
>
230834-33
Figure 12. Write Cycle Timing
/
INTA"\
IS
RD
IS
DBO-OB7
II
/
\
(
X
VECTOR
)
230834-34
Figure 13. Interrupt Acknowledge Cycle Timing
2-174
intJ
82530/82530-6
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Case Temperature
Under Bias ...................... O°C to. + 70°C
Storage Temperature
Ceramic Package ............ - 65°C to + 150°C
Plastic Package ............. -40°C to + 125°C
Voltage on Any Pin with
Respect to Ground ............ - 0.5V to + 7.0V
D.C. CHARACTERISTICS Te
Symbol
= 0°Ct070°C;Vee = +5V±5%
Parameter
Min
Max
Units
Test Conditions
VIL
Input Low Voltage
-0.3
+0.8
V
VIH
Input High Voltage
+2.4
Vee +0.3
V
VOL
Output Low Voltage
+0.45
V
IOL = 2.0 mA
VOH
Output High Voltage
V
IOH = -250/-LA
+2.4
IlL
Input Leakage Current
±10
/-LA
O.4V to 2.4V
IOL
Output Leakage Current
±10
/-LA
O.4V to 2.4V
lee
Vee Supply Current
250
mA
CAPACITANCE Te
Symbol
= 25°C; Vee = GND = OV
Parameter
Min
Max
Units
10
pF
fc
Unmeasured pins
returned to GND
CIN
Input Capacitance
COUT
Output Capacitance
15
pF
CliO·
Input/Output Capacitance
20
pF
2-175
Test Conditions
=
1 MHz
intJ
82530/82530-6
A.C CHARACTERISTICS Tc = O·Cto +70·C;Vcc
=
+5V ±5%
READ AND WRITE TIMING
Number
82530 (4 MHz)
Parameter
Symbol
82530-6 (6 MHz)
Min
Max
Min
Max
Units
1
tCl
ClK low Time
105
2000
70
1000
ns
2
tCH
ClK High Time
105
2000
70
1000
ns
10
ns
tf
ClK Fall Time
4
tr
ClK Rise Time
5
tCY
ClK Cycle Time
3
20
20
250
4000
165
15
ns
2000
ns
80
0
ns
0
0
ns
Address to RD! Setup Time
80
0
ns
Address to RD t Hold Time
0
0
ns
6
tAW
Address to WR ! Setup Time
7
tWA
Address to WR
8
tAR
9
tRA
10
tiC
INTA to ClK t Setup Time
11
tlW
INTA to WR! Setup Time (Note 1)
t
t
Hold Time
5
ns
55
ns
0
0
ns
200
55
ns
12
tWI
INTA to WR
13
tlR
INTA to RD! Setup Time (Note 1)
14
tRI
INTA to RD t Hold Time
0
0
ns
15
tCI
INTA to ClK t Hold Time
100
100
ns
16
tClW
CS low to WR!
17
tWCS
CS to WR
18
tCHW
CS High to WR! Setup Time
19
tClR
CS low to RD! Setup Time (Note 1)
20
tRCS
CS to RD t Hold Time (Note 1)
21
tCHR
CS High to RD! Setup Time (Note 1)
22
tRR
RD low Time (Note 1)
23
Null
Parameter Deleted
24
tRDI
RD t to Data Not Valid Delay
25
tRDV
RD! to Data Valid Delay
250
105
ns
26
tDF
RD t to Output Float Delay (Note 2)
70
45
ns
t
Hold Time
5
200
Setup Time
Hold Time
0
0
ns
0
0
ns
100
5
ns
0
0
ns
0
0
ns
100
5
ns
390
150
ns
0
0
ns
NOTES:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Float delay is defined as the time required for a +O.5V change in the output with a maximum D.C. load and minimum A.C.
load.
2-176
82530/82530-6
:c
A.C. TESTING INPUT, OUTPUT WAVEFORM
24=X >
'2.0
045
08
OPEN DRAIN TEST LOAD
+5V
20
TEST POINTS
<
08
2.2K
230834-35
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".
50pF
r
A.C. TESTING LOAD CIRCUIT
230834-42
DEVICE
UNDER
TEST
lCL"'50PF
-=
230834-41
CL = 150 pF
CL Includes Jig Capacitance
CLK
-~--Y
...........:;
Ali. Die
~~~-.
CD
o
1----0
CD-
~
-(i)-~ -:of®
- ® t~®~
--)l
_(1:)__
- V®
~
f-lI
®~
0,---.
Di-
](
®~
-LJ
0--
-@)-
--0-
-®~ -
~®
21
DBO-DB7
READ
)]
@-
:1
®
®
®
~®
-®.JI.
@)
DBO-DB7
WRITE
READY/REO
READY
)I
@-I- - ®
J(
-
r-+@
0..-..:...
®
READY/REO
REOUEST
iii'iiiiiEQ
~
@
-
J
f--®J
REOUEST
-@-
\.
230834-36
Figure 14. Read and Write Timing
2-177
inter
82530/82530-6
INTERRUPT ACKNOWLEDGE TIMING, RESET TIMING, CYCLE TIMING
Number Symbol
82530 (4 MHz)
Parameter
Min
Max
82530-6 (6 MHz)
Min
Units
Max
27
tAD
Address Required Valid to Read Data
Valid Delay
28
TWW
WR low Time
390
60
29
tDW
Data to WR J, Setup Time
0
0
ns
30
tWD
Data to WR
t
0
0
ns
31
tWRV
WR J, to Ready Valid Delay (Note 4)
240
200
ns
32
tRRV
RD J, to Ready Valid Delay (Note 4)
240
200
ns
33
tWRI
WR J, to READY/REO Not Valid Delay
240
200
ns
34
tRRI
RD J, to READY/REO Not Valid Delay
240
200
ns
35
tDWR
WR
t
to DTR/REO Not Valid Delay
5tCY
+300
5tCY
+250
ns
36
tORD
RD
t
to DTR/REO Not Valid Delay
5tCY
+300
5tCY
+250
ns
37
tliD
INTA to RD J, (Acknowledge) Delay
(Note 5)
250
38
til
RD (Acknowledge) low Time
285
39
tlDV
RD J, (Acknowledge) to Read Data
Valid Delay
40
tEl
lEI to RD J, (Acknowledge) Setup Time
41
tiE
lEI to RD
42
tEIEO
lEI to lEO Delay Time
43
tCEO
ClK
44
tRIl
Ri5T to INT Inactive Delay (Note 4)
t
t
Hold Time
(Acknowledge) Hold Time
590
325
t to WR J, Delay for No Reset
t to RDJ, Delay for No Reset
tRW
RD
46
tWR
WR
47
tRES
WR and RD Coincident low for Reset
48
tREC
Valid Access Recovery Time
(Note 3)
ns
100
100
0
ns
ns
ns
0
120
45
ns
125
120
to lEO Delay
ns
250
190
ns
100
ns
250
250
ns
500
500
ns
30
15
ns
30
30
ns
250
250
ns
6tCY
+200
6tCY
+130
ns
NOTES:
3. Parameter applies only between trlj.nsactions involving the SCC.
4. Open-drain output, measured with open-drain test load.
5. Parameter is system dependent. For any SCC in the daisy chain, tliD must be greater than the sum of tCEQ for the
highest priority device in the daisy chain, tEl for the SCC a'nd tEIEO for each device separating them in the daisy chain.
2-178
inter
82530/82530-6
eLK
INTA _ _ _ _ _ _""\
@---.t
-+_____
DBO-DB7 _ _ _ _ _ _ _ _
-++_~
lEI
lEO
t---®--~--I_
1~·~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~)f~-------230834-37
Figure 15. Interrupt Acknowledge Timing
230834-38
Figure .16. Reset Timing
cs
RDORWR
1~'------~\,-~_____
/
---:-J
~
_---J}t-----\=======_'®~r~1-----..."j\~__
230834-39
Figure 17. Cycle Timing
2-179
inter
82530/82530-6
GENERAL TIMING
Number Symbol
82530 (4 MHz)
Parameter
Min
t
1
tRCC
RxC
2
tRRC
RxD to RxC
(Note 1)
3
tRCR
RxD to RxC
(Note 1)
4
tORC
5
tRCD
t
Max
82530-6 (6 MHz)
Min
Units
Max
100
100
ns
t
Hold Time (X1 Mode)
0
0
ns
t
Hold Time (X1 Mode)
150
150
ns
RxD to RxC.J, Setup Time (X1 Mode)
(Notes 1, 5)
0
0
ns
RxD to RxC.J, Hold Time (X1 Mode)
(Notes 1, 5)
150
150
ns
to ClK
6
tSRC
SYNC to RxC
7
tRCS
_ SYNC toRxC
8
tTCC
Setup Time (Notes 1, 4)
t Setup Time (Note 1)
t Hold Time (Note 1)
TxC.J, to ClK
t
Setup Time (Notes 2, 4)
-200
-200
ns
3tCY
+20d
3 tCY
+200
ns
100
100
ns
9
tTCT
TxC.J, to TxD Delay (X1 Mode) (Note 2)
300
300
ns
10
tTCD
TxC to TxD Delay (X1 Mode)
(Notes 2, 5)
300
300
ns
11
tTDT
TxD to TRxC Delay (Send Clock Echo)
200
200
ns
t
12
tDCH
RTxC High Time
180
150
ns
13
tDCl
RTxC low Time
180
150
ns
14
tDCY
RTxC Cycle Time
4tCY
15
tClCl
Crystal Oscillator Period (Note 3)
250
4tCY
16
tRCH
TRxC High Time
180
150
ns
17
tRCl
TRxC low Time
180
150
ns
18
tRCY
TRxC Cycle Time (Note 6)
4tCY
4tCY
ns
19
tCC
CD or CTS Pulse Widtl:l
200
200
ns
20
tSS
SYNC Pulse Width
200
200
ns
1000
165
ns
1000
ns
21
tWRT
WR to RTS Valid Delay
6tCY
6tCY
ns
22
tWDT
WR to DTR Valid Delay
5tCY
5tCY
ns
NOTES:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
3. Both RTxC and SYNC have 30 pF capacitors to ground connected to them.
4. Parameter applies only if the data rate is one-fourth the system clock (ClK) rate. In ali other cases, no phase relationship
between RXC and ClK or 'iXC and ClK is required.
5. Parameter applies only to FM encoding/decoding.
6. Only applies to transmitter and receiver. For DPll and Baud Rate Generator Timings, the requirements are identical to
system clock, ClK, specifications.
2-180
82530/82530-6
CLK
READY/REO
REOUEST
READY/REO
READY
~,TRiC
RECEIVE
RxD
SYNC
EXTERNAL
TRxC, ii'i'iC
TRANSMIT
TxD
TRiC
OUTPUT
~----~---1L==®~
-->f;,1--®-:....-_---l~-"" . . .______J\,...----
r----------------------------
SYNC
INPUT
230834-40
Figure 18. General Timing
2-181
inter
APPLICATION
NOTE
AP-401
December 1986
Designing With the 82510
Asynchronous Serial Controller
FAISAL IMDAD-HAQUE
APPLICATIONS ENGINEER
Order Number: 231928·001
2·182
inter
AP·401
1.0 INTRODUCTION
The emergence of asynchronous communications as the
most widely used protocol (it commands the largest installed base of nodes, exceeding HDLC/SDLC, the second most popular protocol, by a factor of 10 to 1) for
point to point serial links has led to the need for an
asynchronous communications component with high
integration to reduce component count and decrease
the cost of a serial port. The trend towards higher data
rates and multiple job, multiple user systems has underscored the need for an intelligent serial controller to
improve system throughput and decrease the CPU load
normally associated with asynchronous serial communications.
The 82510 CMOS Asynchronous Serial Controller is
designed to improve asynchronous communications
throughput and reduce system cost by integrating functions and simplifying the system interface. Two independent FIFOs, and Control Character Recognition
(CCR), provide data buffering and increase software
efficiency. Two Baud Rate Generators/Timers, an OnChip Crystal Oscillator and seven Programmable I/O
pins provide a high degree of integration and reduce
system component count. This application note will
demonstrate the use of these features in an Asynchronous Communications Environment.
1.1 Goal
The goal of this application note is to demonstrate the
use of the major 82510 features in an asynchronous
communications environment and to depict basic hardware and software design techniques for the 82510. It
will discuss interfaces using both polling and interrupt
techniques, as well as the impact of FIFOs using either
scheme. An application example covering the application of Error Free File Transfer is also provided.
This is followed by a discussion of the hardware design
and system interface considerations in sections three
and four. The fifth section provides some software techniques for transmitting and receiving data as well as the
use of timers. Section seven briefly discusses the file
transfer application based on the XMODEM protocol
and includes the software listings.
2.0 82510 DESCRIPTION
2.1 Overview
The 82510 can be divided into seven functional blocks
(See Figure 1): Bus Interface Unit (BIU), Timing Unit,
Modem Interface Module, Tx FIFO, Rx FIFO, Tx Machine and Rx Machine. All blocks, except BIU can generate a block interrupt request to the 82510 interrupt
logic. In the case of the Rx Machine, Timing Unit and
Modem Interface Module, multiple sources (errors and
status events) within the block cause the block interrupt
request to become active. All of the blocks have registers associated with them. The registers, allow configuration, provide status information about events/errors,
and may also be used to send commands to each block.
2.2 Bus Interface Unit (BIU)
The Bus Interface Unit (BIU) interfaces the 82510
functional blocks to the system or CPU bus. It provides
read and write access to the 82510 registers and controls the generation of interrupts to the external world.
The interrupt logic resolves contention between block
interrupt requests, on a priority basis. The BIU also has
the Hardware Reset circuitry, which is driven by the
RESET pin. The reset signal clears all internal Flip
Flops, and Registers and puts them in a predefined
state. All activities on the Bus interface, including register accesses by the CPU, are synchronized to an internal (82510) system clock, supplied via the CLK pin.
1.2 Scope
The application note describes the operation of the
82510 ASC in a normal (non 8051 9-bit) asynchronous
communications mode. The majority of the discussion
is .focused towards the systems aspects of the Controller. The use of the 82510 in a multidrop or 8051 9-bit
asynchronous environment is not covered. This application note assumes that the reader is familiar with the
82510 in terms of pin description, register architecture
and interrupt structure. It is also .assumed that the
reader is familiar with the information provided in the
82510 Data Sheet.
The initial sections of the application note provide an
overview of the 82510 and its major functional blocks.
2.3 Receive Machine (RxM)
The Rx Machine (RxM) converts the serial data to parallel and writes it to the Rx FIFO, along with the appropriate flags (available in the Receive Flags Register).
The Rx Machine can be configured for control character recognition, data sampling and DPLL operation.
The software can check for noise, control character,
break, address or parity apd framing errors by reading
the status or character flags. Optionally, the Receive
Status bits (in RSn, when enabled, can generate interrupt requests. The Rx Machine block Interrupt request
is reflected in the General Status Register and is set
when an enabled interrupt request within the Rx Ma-
2-183
inter
AP-401
chine (i.e. RST bits) becomes active. The Rx Machine
has eight registers associated with it:
Receive Data (RXD)--Receive Data Character
Receive Flags (RXF)-Receive Character Flags
Receive Status (RST)-Receive Events and Receive Errors
Receive Int~rrupt Enable (RIE)--Enables Interrupts
on corresponding bits in RST
Receive Mode (RMD)-Receive Machine Configuration
Receive Command (RCM)-Receiver ,Command Register
Line Control (LCR)-16450 Register, Character Attribute Configuration
Line Status (LSR)--16450 Status Register, Tx and Rx
status
erate Interrupts (if enabl~u,,~m transitions, in the" modem input pins (DCD, CTS, RI, and DSR). The modem output pins can be controlled by the CPU, alsQ the
RTS pin can be used to provide flow control, in the
automatic transmission mode. It is the source of the
Modem Interrupt bit in GSR. This bit is set whenever
there is a state change in the DCD, RI, DSR or CTS
inputs (reflected in Mo4em Status Register) and the
corresponding enable bits are set. The function and direction of the multifunction pins can be reprogrammed
and is available as a configuration option. Multifunction pins, when configured as outputs, can be controlled by the CPU through the Modem Control Register: The Modem module has four registers associated
with it:
Modem Status
Register (MSR)-State transitions on modem input
pins, and State of the modem input pins
Modem Control (MCR)-Control state of Modem
Output pins
Modem Interrupt
Enable (MIE)-Enable Interrupt on State transitions in
modem input pins
2.4 Transmit Machine (TxM)
The Tx Machine reads characters from the Tx FIFO
and transmits them serially over the TXD line. The Tx
Machine can also transmit additional character attributes (9th bit of Data, Address Marker, Software Parity) available from the Transmit Flags, if configured in
the appropriate mode. The Tx Machine Idle interrupt
request is reflected in the GSR and LSR registers to
indicate that the Transmitter is either Empty or Disabled. The Tx Machine has six registers associated with
it:
Line Control (LCR)--16450 Register, Character Attribute Configuration
Line Status (LSR)-16450 Status Register, Tx and Rx
status
I/O Pin Mode (PMD)-Functions and Directions of
Multifunction pins
2.6 Timing Unit
The Timing Unit is responsible for the generatipn of the
System Clock, using either its Crystal Oscillator or an
externally generated clock, and generation of the Tx
and Rx clocks from either the On-Chip Baud Rate
Generators or the SCLK pin. It is also responsible for
generating Timer Expired interrupts when the
BRGs/Timers are configured for use as Timers. There
are ten registers associated with the Timing Unit, four
of these are used in the Timer mode only.
Timer Status (TMST)-Timer A and/or Timer B expired
Transmit Mode (TMD)--Tx Machine Configuration
Transmit Command--(TCM)-Transmit Command
Register
Timer Interrupt
Enable (TMIE)-Enables Interrupts upon Expiration
of Timers A or B in TMST
Transmit Flags (TXF)-Transmit Character Flags
Timer Control (TMCR)--Start and Disable Timers
Transmit Data (TXD)--Transmit Data'Character
Clock Configure (CLCF)--Select source and mode for
Tx and Rx clocks
2.5 Modem Interface Module
BRG B Configuration (BBCF)--Mode and Clock
source of BRG B
The Modem Interface module is responsible for the modem interface and general purpose I/O pins. It will gen-
2·184
inter
AP-401
BRG B LSB of Divisor (BBL)-Least Significant Byte
of BRG B Divisor/Count
are totally independent of each other and each FIFO
can generate an interrupt request which indicates that
the configured threshold has been met.
BRG A MSB of Divisor (BBH)-Most Significant Byte
of BRG B Divisor/Count
3.0 HARDWARE DESIGN
BRG A Configuration (BACF)-Mode and Clock
source of BRG A
3.1 System Interface
BRG A LSB of Divisor (BAL)-Least Significant Byte
of BRG A Divisor/Count
The 82510 has a standard I/O peripheral interface, it
has a demultiplexed Bus, which consists of a bidirectional eight bit Data Bus, and three Address lines. Interrupt, Read, Write, Chip Select and Reset pins complete the system interface. The three address lines along
with the Bank register are used to select a particular
register.
BRG A MSB of Divisor (BAH)-Most Significant
Byte of BRG A Divisor/Count
2.7 FIFOs, Rx and Tx
The Dual FIFOs (transmit and receive), serve as buffers for the 82510. They buffer the transmitter and Receiver from the CPU. Each of the FIFOs has a programmable threshold. The threshold is the FIFO level
which will generate an interrupt. The threshold is used
to optimize the CPU throughput and provide increased
interrupt to service latency for higher baud rates. It can
be configured through the FIFO Mode Register. Each
FIFO character has flags associated with it (TxF and
RxF). As each character is read from the Rx FIFO its
flags are put into the RxF register. Before a write to
TXD (if character configuration requires) the character
flags are written to the TXF register. The two FIFOs
3.1.1 REGISTER ACCESS
The 82510 registers are logically divided into four
banks. Only one bank can be accessed at anyone time.
Each register bank occupies eight I/O addresses. To
select a register, the correct Bank must first be selected
by writing to the GIR/Bank register (the GIR/Bank
registeri/O address is two (Ao = 0, Al = I, A2 = 0).
Then one of the eight I/O space addresses is selected by
outputting a value (between zero and seven) to the
82510 address pins Ao-A2'
r-
- r+
Vss - r+
A(2-0) 0(7-0)
SERIAL MODULE
Vee
INT
: r-~
INT
4
R1l
WR
eli
RESET
-
-~
-~
BUS
INTERFACE
UNIT
~
TX
, FIFO
f-
TX
MACHINE
I- ~ -+ TXD
RX
FIFO
~
RX
MACHINE
~ l- I-
T-IRT~l
jM]TS
INT
2
INTERNAL BUS
l
l
rJx TJx
TIMING
BLOCK
(BRGS. SYS CLOCK)
MODEM
INTERFACE
MODULE
IX
RXC
RXD
IX
TXC
::
.
I- CLKjXI
I- Wf2/X2
I- Rl/SCLK
J::
- f::
Ji+- ~ m
fiID!/TA/(!lJ'Tll
1leIj/ICLK/OUfl
DTR/TB
irn
l-
I-
231928-1
Figure 1.82510 Block Diagram
2-185
inter
Ap·401
BANK ZERO 825O-COMPATIBLE BANK
Reglater
5
6
3
0
Addre88 Defaul
2
1
xD
Tx Data
bit 7
Tx Data Tx Data
bitS
bit 5
TxData
bit 4
TxData
bit 3
TxData
bit 2
Tx Data
bit 1
TxData
bit 0
0
.....;
RxD
Rx Data
bit 7
RxData RxData
bitS
bit 5
RxData
bit 4
RxData
bit 3
RxData
bltl!
RxData
bit 1
RxData
bit 0
0
-
7
4 '
BAL
BRGA LSB Divide Count (DLAB = 1)
0
02H
BAH
BRGA MSB Divide Count (DLAB = 1)
1
OOH
GER
0
GIR/BANK
0
LCR
0
TxMachine Modem
Interrupt
Interrupt
' I;nable
Enable
RxMachine
Interrupt
Enable
TxFIFO
Interrupt
Enable
RxFIFO
Interrupt
Enable
1
OOH
Active
Block Int
bit 2
Active
Block Int
bit 1
Active
Block Int
bit 0
Interrupt
Pending
2
01H
Parity
Mode
bit 0
Stop bit
Length
bit 0
Character
Length
bit 1
Character
Length
bit 0
3
OOH
OUT 0
Loopback OUT2
OUT 1
RTS
DTR
Complement Control bit Complement Complement Complement Complement
4
OOH
TxFIFO
Interrupt
BANK BANK
Pointer Pointer
bit 1
bit 0
DLAB
Set
Divisor
Break
Latch
Access bit
MCR
0
0
LSR
0
TxM
Idle
MSR
Timer
Interrupt
Enable
Parity
Mode
bit 2
0
Parity
Mode
bit 1
DCDlnput Rllnput DSR Input
Inverted Inverted Inverted
~CRO
Break
Detected
Framing
Error
CTSlnput State
Change
Inverted
inDCD
Parity
Error
Overrun
Error
RxFIFO
IntReg
5
60H
State(H- L) State
Change
Change
inRI
inDSR
State
Change
inCTS
S
OOH
7
OOH
Address or Control Character Zero
BANK ONE-GENERAL WORK BANK
Reglater
7
6
5
4
3
2
1
0
Addre88 Default
tJ"xD
TxData
bit 7
TxData TxData
bitS
bit 5
Tx Data
bit 4
TxData
bit3
TxData
bit 2
Tx Data
bit 1
TxData
bit 0
0
-
RxD
RxData
bit 7
RxData RxData
bitS
bit 5
RxData
bit 4
Rx Data
bit 3
RxData
bit 2
Rx Data
bit 1
RxData
bit 0
0
-
RxF
-
RxChar RxChar
Noisy
OK
RxChar
Parity
Error
Address or
Control
Character
Break
Flag
RxChar
Framing
Error
Ninth
Data bit
of RxChar
1
-
1
-
IrxF
Address Software Ninth bit
Marker bit Parity bit of Data Char
GIR/BANK
0
IrMST
-
-
~MCR
,0
MCR
0
BANK
Pointer
bit 1
BANK
Pointer
bit 0
0
0
0
Active'
Block Int
bit 2
0
Active
Block Int
bit 1
0
0
Active
Block Int
bit 0
Interrupt
Pending
2
01H
TimerB
Expired
Timer A
Expired
3
30H
Start
TimerB
Start
Timer A
3
-
4
OOH
GateB
State
Gate A
State
-
-
0
Trigger
GateB
Trigger
Gate A
0,
0
0
OUT 0
Loopback OUT2
OUTI
RTS
DTR
Complement Control bit Complement Complement Complement Complement
Figure 2. 82510 Register Map
2-186
inter
Ap·401
BANK ONE-GENERAL WORK BANK (Continued)
Register
7
FLR
-
5
6
3
4
RST
Addressl
Control
Character
Received
Addressl Break
Break
Framing
Control
Terminated Detected Error
Character
Match
RCM
Rx
Enable
Rx
Disable
MSR
DCD
Rllnput
Complement Inverted
TCM
0
0
GSR
-
-
ICM
0
0
Flush
RxFIFO
DSR Input
Inverted
CTSlnput State
Inverted Change
inDCD
0
Parity
Error
Overrun RxFIFO
Interrupt
Error
Requested
Open Rx
FIFO
State
Change
inRI
0
0
State
State
Change Change
inDSR inCTS
Flush Tx
Machine
Flush Tx Tx
Enable
FIFO
TxM
Interrupt
Modem
Interrupt
TxFIFO RxFIFO
RxM
Interrupt Interrupt Interrupt
Software
Reset
Manuallnt
Status
Acknowledge Clear
Command
0
0
Address Default
0
1
Tx FIFO Level
LockRx
FIFO
Flush
RxM
Timer
Interrupt
2
-
Rx FIFO Level
Tx
Disable
0
Power
Down
Mode
4
OOH
5
OOH
5
-
6
OOH
6
-
7
12H
7
-
BANK TWO-GENERAL CONFIGURATION
Register
7
6
FMD
0
0
GIR/BANK
0
BANK
Pointer
bit 1
TMD
IMD
Error
Echo
Disable
5
BANK
Pointer
bit 0
RMD
0
Control
9-bit
Character
Character
Echo Disable Length
0
0
3
2
0
0
1
Stop Bit Length
Software
Parity
Mode
Interrupt
RxFIFO ulah
Acknowledge Depth
Mode
Mode
Select
0
Address Default
0
Tx FIFO Threshold
Interrupt
Active
Active
Block Int Block Int Pending
bit 1
bit 0
Active
Block Int
bit 2
Transmit Mode
0
ACR1
RIE
4
Rx FIFO Threshold
Loopbackor
Echo Mode
of Operation
Addressl
Control
Character
Match
Interrupt
Enable
Break
Terminate
Interrupt
Enable
Break
Detect
Interrupt
Enable
Disable
DPLL
Sampling Start bit
Window Sampling
Mode
Mode
Address/Control
Character Mode
Framing
Error
Interrupt
Enable
OOH
01H
3
OOH
4
OCH
5
OOH
Parity
Error
Interrupt
Enable
Overrun
Error
Interrupt
Enable
0
6
1EH
0
0
0
7
OOH
Address or Control Character 1
Addressl
Control
Character
Recognition
Interrupt
Enable
1
2
BANK THREE-MODEM CONFIGURATION
7
6
5
4
3
2
1
0
Address
Default
CLCF
Register
RxClock
Mode
RxClock
Source
TxClock
Mode
TxClock
Source
0
0
0
0
0
OOH
BACF
0
0
0
0
BRGA
Mode
0
0
1
04H
0
05H
1
OOH
BRGA
Clock
Source
BBL
BRGB LSB Divide Count (DLAB
BBH
BRGB MSB Divide Count (DLAB
= 1)
= 1)
Figure 2_ 82510 Register Map (Continued)
2-187
Ap·401
BANK THREE-MODEM CONFIGURATION (Continued)
Register
7
6
GIR/BANK
0
BANK
Pointer
bit.1
BBCF
PMD
5
BANK
Pointer
bit 0
BRGB Clock Source
0
4
3
Active
Block Int
bit 2
0
0
0
DCDIICLKI DCDIICLKI DSR/TAI DSR/TAI RIISCLK
aUT 1
aUT 1
aUTO
aUTO
Function
Direction
Function
Direction Function
MIE
0
0
0
0
TMIE
0
0
0
0
2
Active
Block Int
bit 1
1
0
Active
Block Int
bitO
Address Default
Interrupt
Pending
01H
BRGB
Mode
0
0
3
84
DTR/TB
Function
0
0
4
FCH
5
OFH
6
OOH
DCDState RI State
DSRState CTSState
Change Int Change Int Change Int Change Int
Enable
Enable
Enable
Enable
0
2
0
TimerB
Interrupt
Enable
Timer A
Interrupt
Enable
Figure 2. 82510 Register Map (Continued)
3.1.2 READ AND WRITE CYCLES
3.1.3 80186 INTERFACE
Like most other I/O based peripherals the Read and
Write pins are used to access data in the 82510. Each
read or write cycle has specified setup and hold times in
order for the data to be transferred correctly to/from
the 82510. The critical timings for the read cycle are:
1. Address Valid to Read Active (Tavrl)
2. Command Access Time to Data Valid (Trldv)
3. Command Active Width (Trlrh)
The exact interface is shown in Figure 3. The schematic
shows the 80186 interface to the 82510 on a local bus.
Although the Data Bus is buffered, it is possible to
directly connect the 82510 to the 80186 data bus; because the Data Float Delay after read inactive is 40 ns
for the 82510, which is well under the 85 ns requirement of the 80186. The timing equations for the interface are given below.
Read Cycle:
The less critical parameters are:
4. Address Hold to Read Inactive (Trhax)
5. Data Out Float Delay after Read Inactive (Trhdz)
Address to Read Low
- Latch DelaYmax
=
Tclel - Tclavmax
+ Tclrlmin
Read Access Time = 2Tclcl - Tclrlmax - Tdvcl Transceiver DelaYmax
The critical timings for the write cycle are:
1. Address Valid to Write Low (Tavwl)
2. Write Active Time (Twlwh)
3. Data Valid to Write Inactive (Tdvwh)
Read Active Time = Trlrh
= 2Tclcl - 46
Write Cycle:
The less critical parameters are:
4. Address and Chip Select Hold Time After Write
Inactive (Twhax)
5. Data Hold Time After Write Inactive (Twhdx)
These timings determine the number of wait states required for the 82510 and the CPU interface. The interfaces for some popular microprocessors are discussed in
the following sections.
Address Valid to Write Active = Tclcl
- Tclavmax - Latch Prop. DeiaYmax
Write Active Time
=
=
+
Tcvctvmin
Twlwh
2Tclcl - 40
Data Valid to Write Inactive = 2 Tclcl - Tcldvmax Transceiver DeiaYmax + Tcvctxmin
2-188
intJ
AP-401
16.0MHz
4
J:!J
~
Xl
r--DATA
'I
X2
~~
RESET ROM
L"
UCS
A16-19
RESE T~"" RES
211.
.
-"
.
ALE
~
LATCH
IA
...J\
I"
Y
AO-16
~ Rii
Al~)
0...-
STB
PROGRAM RAM
~ WR
A
ADO-A016
"
E
-"
rRU~
STB
IA
ADO-AD 15
I"
STB
A
80186
L8
DEN
rrr>
AO-IS
Ir
l
~
",0-,
LOW RAM
XCVR
r-- OE
OT/R
Rii
LCS
00-15
~T
-romAOOR
- '!!B
A
1'1
00-7
~
r-;:- RO
IA
AO-IS
, 08-15
"I.....-..
18.432 MHz
-"
A3-1
1-"
~~
A(2-0)
DO-7
Rii
Rii
WR
INTO
PCSO
WR
l
RESET
I
82510
TXD
~
RXD
~
RTS
RESET
CS
r+
INT
-..I
1
74LSOS
231928-2
Figure 3. 82510 Interface to 80186
2-189
inter
AR.. 401
The user can transfer data to the 82510, using the
DMA capabilities of the 80186, by using the RTS pin,
in automatic modem control mode, as a DMA request
line. The RTS pin, in automatic mode, will go inactive
as soon as the Tx FIFO and the Tx shift register are
empty. It will become active once a data character is
written to the TXD register. In most 80186 DMA transfers the user has to make sure that the DMA request
line goes inactive at least two clock cycles from the end
of the DMA deposit cycle. In this case, the extra DMA
cycle is not a problem, because the Tx FIFO will buffer
the data to prevent an overrun (Since the Tx FIFO can
buffer up to four characters, the RTS pin only needs to
go inactive two clocks before the end of the deposit
phase of the fourth DMA). Typically RTS will go inactive five (82510) system clocks after the rising edge of
write.
3.1.4 80286 INTERFACE
The 80286 interface is shown in Figure 4. The 82510 is
on the local bus, and is using the control signals from
the 82288 Bus Controller. The Data Enable (OE) is
qualified by the 82510 Chip Select, to avoid Data Bus
contention between the 82510 and the CPU. The timing
equations for the Read and Write Cycles are given below.
Read Cycle:
Address Valid to Read Active = Tl (CLK period) +
T29 min (CLK to cmd active) - T16max (ALE active
delay) - Latch Prop. DelaYmax
Read Access to Data Valid = 2Tl (CLK period) T29 max (CLK to cmd active) - T8 (Read Data Setup
Time) - Transceiver DelaYmax
wait states means that the access times for the relevant
parameters will be increased by 250 ns.
NOTE:
The address decoding scheme of the 80286 interface is
different from the IBM PC/PC AT I/O addresses for
the serial ports, therefore the interface shown in Figure 4 cannot be used in PC/PC AT oriented designs.
3.1.5 80386 INTERFACE
The 80386 interface to the 82510 is given in Figure 5.
The example uses the Basic I/O interface given in the
80386 Hardware Reference Manual section 8.3. The
only differences are in the specific address lines used for
chip select generation, and the additional wait states in
the wait state generation logic. The address lines A3,
A4 and A5 are used to select one of the eight register
address spaces in the 82510, therefore, A6 and A7,
rather than A4 and A5, are used in the I/O decoder.
This causes a granularity of four in the 8251O's I/O
address space, i.e., the addresses of two consecutive registers in the 82510 differ by four.
The 82510 requires one additional wait state (as currently specified), the desigu assumes that the PAL
equations are modified for that purpose. The user may
also externally generate the wait states and connect to
the "other ready logic" input ORed with the RDY pin
of PAL 2. The two read timings Read Active width and
Read Access time to Data Valid each require one additional wait state in order to meet the 82510 timing requirements. The timings are given below. (82510 times
are at 9.216 MHz)
Read Cycle:
Read Access to Data Valid
= 253.25 ns
Read Active Time = 2TI (CLK period) - T29 max
(CLK to cmd active) + T30min (CLK to cmd inactive)
82510 Trldv
= 308
Write Cycle:
additional time reqd.
= 308-253.25
Address to Write Low = Tl (CLK period) + T29 min
(CLK to cmd active) - T16max (ALE active delay) Latch De1aYmax
Write Active Time = 2 Tl (CLK period) - T29 max
(CLK to cmd active) + T30min (CLK to cmd inactive)
= 54.75 ns
Read Active Width
= 269.25
82510 Trlrh
= 308
additional time reqd.
= 308-269.25
Data to Write High = 3 Tl - Tl4min (Write Data
Valid Delay) + T30min (CLK to cmd inactive) Xcvr. DelaYmax
= 38.75 ns
Address Valid to Read Active = 132.75 ns
Using an 8 MHz 80286 with the 82510 at 18.432 MHz
(divide by two-9.216 MHz) requires two wait states.
The critical timings are the read cycle timings-Read
Access Time and Read Active Width. Inserting two
82510TAVRL
= 7ns
Since each additional wait state adds 62.5 ns at
16 MHz, the 82510 requires one additional wait state.
2-190
(
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18.432 MHz
231928-4
•
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C)
....
intJ
AP-401
The required recovery time between successive commands is 123 ns for the 82510, this is well within the
331.75 ns provided by the Basic I/O interface.
Write Cycle:
Addven to Write Low = 132.75 ns
82510TAVWL
= 7ns
Write Active Time
= 300.5 ns
82510 TWLWH
= 231 ns
Data to Write High
= 289.5 ns '
82510 TOVWH
= 90ns
with the PC software). Also since in the PC family the
interrupt request pin of the UART is gated by the
OUT2 pin, The OUT2 pin must be available in the
16450 compatibility mode, consequently the user is restricted to an external clock source when using the
82510 in the IBM PC compatible mode. The default pin
out is given in Figure 6 and the configuration is given in
Table 1. The default. register values are given in the
82510 register map shown in Figure 2 in section 3.1.1.
Table 1.82510 Default Configuration
INTERRUPTS
Auto Acknowledge
All Interrupts Disabled
NOTE:
The interface shown in Figure 5 uses a different address decoding scheme than that used for the IBM
PC/PC AT families, for the serial ports. Therefore,
the interface in Figure 5 can not be used in PC/PC
AT compatible designs.
RECEIVE
Stand Ctl. Char. Recogn. disabled
Digital Phase Locked Loop (DPLL) disabled
3/16 Sampling
Majority Vote Start bit
Non IJ-lan (Normal) mode
BkD, FE, OE, PE Int. enabled
3.2 Reset
The 82510 can be reset either through hardware (Reset
pin) or Software (reset command via Internal Command Register-ICM). Either reset would cause the
82510 to return to its default wake up mode. In this
mode the register contents are reset to their default valuesand the device is in the 16450 compatible configuration. The Reset pulse must be held active for at least
eight system clocks, the system clock should be running
during reset active time.
3.2.1 DEFAULT MODES FOR 16450
COMPATIBILITY
Upon reset the 82510 will return to its Default Wake
Up mode. The default register bank is bank zero. The
registers in bank zero llI"e identical to the 16450 register
set, and provide complete software compatibility with
the 16450' in the IBM PC environment. The registers
in the other banks have default values, which configure
the 82510 for 16450 emulation. The recommended system clock (for PC compatibility) is 18.432 !¥1Hz, this,
allows the baud rates generation to be done in a manner
compatible with the PC software. The PC software calculates baud rate$ based on a source frequency of
1.8432 MHz. The 82510 syst~m ,clock (18.432 MHz) is
divided by two before being fed to BRG A and then is
again divided by five (BRG B default). This causes the
frequency to be divided by ten before being fed into
BRG A. 18.432 divided by ten yields 1.8432 MHz, so in
effect the BRG A is generating baud rates from a
source frequency of 1.8432 MHz (which is compatible
"16450 is the PC AT version of the INS 8250A.
2-193
FIFO
Rx FIFO Depth = 1
Tx FIFO Threshold = 0
AUTO ECHO Disabled
LOOP BACK Configured
for Local Loopback
CLOCK OPTIONS
Baud Rate = 57.6K
Rx Clock = 16 x
Rx Clock Source = BRG B
Tx Clock = 16 x
Tx Clock Source = BRG B
. BRG A Mode = BRG
BRG A. Source = Sys. Clock
BRG B Mode = BRG
BRG B Source = BRG A Output
. TRANSMIT
Manual Control of RTS
1 Stop Bit
No Parity
5 Bit Character
inter
AP-401
EXTERNAL CLOCK
04
03
05
02
06
01
07
DO
INT
A2
TXD
AI
VSS
OUT2
AD
Ri
Rli
ViR
OSR
C§
OCO
RESET
RXO
RTS
CTS
OTR
ClK
231928-7
Vee
NOTE:
Crystal Oscillator is always divided by two.
Figure 8. Disable Divide by Two
If the Crystal Oscillator is being used to supply the
system clock, then the clock frequency is always divided by two before being fed into the rest of the 82510
circuitry. If, however an external clock source is being
used to supply the system clock, then the user has two
options:
231928-5
Figure 6. Default Pin Out Configuration
of the 82510
3.3 System Clock Options
The term "System Clock" refers to the clock which
provides timings for most of the 82510 circuitry. The
82510 has two modes of system clock usage. It can
generate its system clock from its On-Chip Crystal Oscillator and an external crystal, or it can use an externally generated clock, input to the device through the
CLK pin. The selection of the system clock option is
done during reset. The default system clock source is an
externally generated clock, which can be reconfigured
by a strapping option on the RTS pin. During Reset,
the RTS pin is an input; it is internally pulled high, if it
is externally driven low, then the 82510 expects to use
the Crystal Oscillator for system clock generation, otherwise it is set up for using an external clock source.
This can be done by using an open collector inverter to
RTS, the input of the ~nverter is the Reset signal. The
82510 has a pull up resistor in the RTS circuitry so no
external pull up is needed. In the crystal oscillator
mode the CLK/Xl pin is automatically configured to
Xl, and the OUT2/X2 pin is configured to X2. In the
External Clock mode, the CLK/Xl is configured to
CLK and the OUT2/X2 is configured to OUT2.
1. Use the System Clock after division by two, e.g. if a
8 MHz clock is being fed into the CLK pin, then the
actual frequency of the 82510 system clock will be 4
MHz (default).
2. Disable Division by two and use the. direct undivided clock, e.g. if an 8 MHz clock is being fed into the
CLK pin, then the actual frequency of the 82510
system clock is also 8 MHz.
The divide by two option is the default mode of operation in the External Clock mode of the 82510. A strapping option can be used to disable the Divide By Two
operation (For Crystal Oscillator Mode Divide By Two
must always be active). During Reset, the DTR pin is
an input; it is internally pulled high, if it is externally
driven low then the Divide By Two operation is disabled. The strapping option is identical to the one used
on RTS for selection of the System Clock source.
The 82510 system clock must be chosen with care since
it influences the wait state performance, Baud Rate
Generation (if being used as source frequency for the
BRGs), the power consumption, and the Timer counting period. The power consumption of the 82510 is dependent upon the system clock frequency. If using the
system· clock as a source for the Baud Rate Generator(s), then the system clock frequency must be a baud
rate multiple in order to minimize frequency deviation.
For standard baud rates a multiple of 1.8432 MHz can
be used, in fact the 18.432 MHz maximum frequency
was chosen· with this particular criteria in mind.
231928-6
1 ms is needed for Oscillator startup
Figure 7. Crystal Oscillator Strapping Option
2-194
inter
AP-401
BACF(6)
SCLK---~
CLK/Xl
DEF
BRGA
CLOCK
MUX
BRGA
FSM
RXM
16X
CLOCK
+ COUNTER
+ LOGIC
BBCF(7-6)
SCLK-1--"
....._..
CLK/Xl-+..........,~
CLCF(6)
BRGB
FSM + COUNTER
+ LOGIC
TXM
l6X
CLOCK
CLCF(4)
TxCM BIT ~---i
OF CLCF -t----,
,..
CLOCK
~-----
Rx CM BIT _ _ _--,
IN CLCF
TXM
~\_-----------------------------+lX
______________
RXM
~lX
CLOCK
23l928~8
Figure 9. Timing Flow of the 82510
2-195
inter
AP·401
3.3.1 POWER DOWN MODE
3.3.1.2 Idle Mode
The 82510 has a "power down" mode to reduce power
consumption when the device is not in use. The 82510
powers down when the power down command is issued
via the Internal Command Register (ICM). There are
two modes of. power down, Power Down Sleep and
Power Down Idle.
The 82510 is said to be in the Idle mode when the
Power Down command is issued and the system clock
is still running (i.e. the system clock is generated externally and not disabled by the user). In this mode the
contents of all registers and memory cells are preserved,
however, the power consumption in this mode is greater than in the Sleep mode. Reading FLR will take the
82510 out of this mode.
3.3.1.1 Sleep Mode
This is the mode when even the system clock of the
82510 is shut down. The system clock source of the
82510 can either be the Crystal Oscillator or an exter·
nal clock source. If the Crystal Oscillator is being used
and the power down command is issued, then the
82510 will automatically enter the Sleep mode. If an
external clock is being used, then the user must disable
the external clock in addition to issuing the Power
Down command, to enter the Sleep mode. The benefit
of this mode is the increased savings in power consumption (typical power consumption in the Sleep
mode is in the range of hundreds of microAmps. However, upon wake up, if using a crystal oscillator, the
user must reprogram the device. The data is preserved
if the external clock is disabled after the power down
command, and enabled prior to exiting the power down
mode. To exit this mode the user can either issue a
Hardware reset, or read the FIFO Level Register (FLR)
and then issue a software reset (if using a Crystal Oscillator). In either case the contents of the 82510 registers
are not preserved and the device must be reprogrammed prior to operation.
NOTE:
If the Crystal Oscillator is being used then the user
must allow about 1 ms for the oscillator to wake up
before issuing the software reset.
NOTE:
The data read from FLR when exiting Power Down is
incorrect and must be ignored.
4.0 INTERRUPT BEHAVIOR
4.1 FIFO Usage
The 82510 has two independent four bytes transmit and
receive FIFOs. Each FIFO can generate an interrupt
request, when the FIFO level meets the Threshold requirements. The FIFOs can have a considerable impact
on the performance of an asynchronous communications system. For systems using high baud rates they
can provide increased interrupt-to-service latency reducing the chances of an overrun occurring. In systems
constrained for CPU time, the FIFOs can increase the
CPU Bandwidth by reducing the number of interrupt
requests generated during asynchronous communications. It can reduce the interrupt load on the CPU by
up to 75%. By choosing the FIFO thresholds which
reflect the system bandwidth or service latency requirements, the user can achieve data rates and system .
throughput, unattainable with traditional UARTs.
Table 2. The Power Down Modes
Mode
Sleep
Idle
Clock Source
Exit Procedure
Crystal Oscill.
Automatically
Disabled
H/W Reset or
Read FLRand
Issue S/W Reset
External Clock
Must be Disabled
by User
Enable External
Clock, Read FLR
and Issue S/W Reset
H/W Reset
External Clock
Running
H/W Reset
Read FLR
Power Consumption
Data Preservation
100-900 p.A
Not Preserved
Must be Reprogrammed
. 100-900 p.A
Not Preserved
Must be Reprogrammed
1-3mA
2-196
All Data Preserved
Does Not Need to be
Reprogrammed
inter
AP-401
4.1.1 INTERRUPT-TO-SERVICE LATENCY
Going back to equation (2):
The interrupt-to-service latency is the time delay from
the generation of an interrupt request, to when the interrupt source in the 82510 is actually serviced. Its
primary application is in the reception of data. In traditional UARTs the CPU must read the current character in the Receive Buffer before it is overrun by the next
incoming character. The Rx FIFO in the 82510 can
buffer up to four characters, allowing an interrupt-toservice latency of up to four character transmission
times. The character transmission time is the time period required to transmit one full character at the given
Baud Rate. It is dependent upon the baud rate and is
given by equation (1):
Int._toJervice latency < Buffer size x JO/baud rate
Int_toJerVice latency = {1 of Channels X ({1 of
int. sources per channel)
X Time required to service interrupt
Int_toJervice latency = 4 X 2 X Time required to
service interrupt
(1) Character Transmission Time =
Num. of Bits per Character Frame
Baud Rate
The Transmit and Receive FIFO thresholds should be
selected with consideration to two factors the Baud
rate, and the (CPU Bandwidth allocated for Asynchronous Channels is dependent upon the number of channels supported since it does not include the overhead of
supporting other peripherals) number of Asynchronous
Serial ports being supported by the CPU. In order to
avoid overrun, the interrupt-to-service delay must be
less than the time it takes to fill the 82510 Rx FIFO.
The relationship is given by equation (2):
(2) Int_toJervice-latency < FIFO Size X
Character Transmission Time
Example
Calculate the maximum baud rate that can be supported by a 6 MHz PC AT to support four Full Duplex
Asynchronous channels using
a) The 82510 with four byte FIFO.
b) The 82510 with one byte FIFO.
Assumptions:
• CPU dedicated to Asynchronous communications.
• UART Interrupts limited to Transmission and Reception only.
• Interrupt Routines are opt~ for fast throughput.
• 10 bits per character frame.
The Time required to service interrupt has been calculated to be 100 p.s for a slightly optimized service routine. RMX86 interrupt service time is given as 250 p.s
and for other operating systems it should be slightly
higher.
Int_toJervice
latency
= 4x2xl00 s
= 800 p.s
82510 max Baud Rate = 4 X 10/800 p.s
(four byte FIFO)
= SOK bits/sec
82510 max Baud Rate = 1 X 10/800 p.s
(one byte FIFO)
= 12.SK bits/sec
4.2 Interrupt Handling
The 82S10 has 16 different sources of interrupt, each of
these sources, when set and enabled, will cause their
respective block interrupt. requests to go active. The
block interrupt request, if enabled, will set the 82S10's
INT pin high, and will be reflected as a pending interrupt in the General Interrupt Register (GIR) if no other
higher priority block is requesting service. If a higher
priority block interrupt is also active at the same time,
then the General Interrupt Register will reflect the higher priority request as the source of the 82S10 interrupt.
The lower priority interrupt will issue a new edge on
the interrupt pin only after the higher priority interrupt
is acknowledged and if no other priority block requests
are present. Both the block interrupts and the individual sources within the blocks are maskable. The block
interrupts are enabled through the General Enable Register (GER) which prevents masked bits in the General
Status Register (GSR) from being decoded into the
General Interrupt Register. This does not prevent the
block request from being set in the General Status Register, it only prevents the masked GSR bits from being
decoded into the General Interrupt Register, and thus
generating any interrupts. The individual sources within the block are masked out via the corresponding interrupt enable register associated with the specific block
(Rx Machine, Timing Unit and the Modem I/O module each have an Interrupt Enable register).
2-197
inter
Ap·401
FIFO BELOW
OR EOUAL
THRESHOLD
GER
TXF
HOLD
LOGIC
FALLING EDGE DETECTORS
SERVICE DETECTED
ACKNOWLEDGE
COMMAND
ICM(3)
AUTOMATIC MODE
IMD(3)
231928-9
Figure 9. 82510'8 Interrupt Scheme
2·198
inter
AP-401
4.2.1 THE INTERRUPT SCHEME
The 82510 interrupt logic consists of the following elements:
4.2.1.1 Interrupt Sources Within Blocks
Three of the 82510 functional blocks (Rx Machine,
Timer, Modem I/O) have more than one possible
source of interrupts, for instance the Rx Machine has
seven different sources of interrupts-standard control
character recognition (Std. CCR), control character
Match (special CCR), Break Detect, Break Terminated, Overrun Error, Parity Error, and Framing Error.
The multiple sources are represented as Status bits in
the Status registers of each of these blocks. When enabled the Status bits cause the block request to set in
the General Status Register. There is no difference in
the behavior of the INT pin or the block status bits in
GSR, for multiple sources within a block becoming active simultaneously. The corresponding block status bit
in GSR is set when one or more interrupt sources within the block become active. When the status register for
the block is read all the active ,interrupt sources within
the block are reset. Each source within the three blocks
can be masked through its respective enable register.
4.2.1.2 General Status Register (GSR)
This register holds the status of the six 82510 blocks
(all except Bus Interface Unit). Each bit when set indicates that the particular block is requesting interrupt
service, and if enabled via the General Enable Register,
will cause an interrupt.
4.2.1.3 General Enable Register (GER)
This register is used to enable/disable the corresponding bits in the' General Status Register. It can be programmed by the CPU at any time.
Table 3. Block Interrupt Priority
Block
Priority
Timers
Tx Machine
RxMachine
RxFIFO
Tx FIFO
Modem 1/0
5 (highest)
4
3
2
1
o (lowest)
GIRCODE
3 2 1 (Bits)
1 0 1
100
o1 1
010
001
000
4.2.1.4 Priority Resolver and General Interrupt
Register
If more than one enabled Interrupt request from GSR
is active, then the priority resolver is used to resolve
contention. The priority resolver finds the highest priority pending and enabled interrupt in GSR and decodes it into the General Interrupt Register (bits 3 to 1).
The General Interrupt Register can be read at any time.
NOTE:
GIR is updated continuously, so while the user may
be serving one interrupt source, a new interrupt with
higher priority may update GIR and replace the older
one.
4.2.2 INTERRUPT ACKNOWLEDGE MODES
The 82510 has two modes of interrupt acknowledgement-Manual acknowledge and Automatic acknowledge. In Manual Acknowledge mode, the user has to
issue an explicit Acknowledge Command via the
Internal Command Register (ICM) in order to cause
the INT pin to go low. In Automatic Acknowledge
mode the INT pin will go low as soon as an active or
pending interrupt request is serviced by the CPU. An
operation is considered to be a service operation if it
causes the source of the interrupt (within the 82510) to
become inactive (the specific status bit is reset). The
service procedures for each source vary. see section
4.2.3.2 for details.
4.2.2.1 Automatic Acknowledgement
In the automatic acknowledge mode, a service operation by the CPU will be considered as an automatic
acknowledgement of the interrupt, This will force the
INT pin low for two clock cycles. after that the INT
pin is updated i.e. if there is an active enabled source
pending then the INT pin is set high again (reflected in
GIR). This mode is useful in an edge triggered Interrupt system. Servicing any enabled and active GSR bit
will cause Auto Acknowledge to occur (independently
of the source currently decoded in the GIR register).
This can be used to rearrange priorities of the 82510
block requests.
2-199
inter
AP-401
GSR 5
TIMER
GSR 3 (MODEM)
GIR
GIR= 1INT
8259A
USER
OPERATIONS '
READ GIR SERVE
(=10) TIMER
ISSUE
EOI
TO
8259A
READ GIR SERVE ISSUE
(= 2) TX FifO
EOI
(WRITE
CHARACTERS)
REAO GIR SERVE
(= 0) MODEM
I
ISSUE
EOI
231928-10
8259A -
Edge Triggered
Non Auto EOI
82510 Automatic Acknowledge
Figure 10. Automatic Acknowledge Mode Operation
~ ---I
GSR
bit
(MODEM)
b?tS:
(TXM)
b?tS~
(TIMER)
GIR
GIR = 1
(82590)
INT
8259A
USER
REAO GIR SERVE MODEM READ GIR
(=0)
INTERRUPT
(=10)
SERVE
TIMER
READ GIR
(=8)
SERVE
TXN
READ GIR ISSUE
(= 1) MANUAL
ACK TO
82510
231928-11
NOTE:
Vector refers to GIR bit (3·0)
82510: Manual Ack. Mode
8259A: Edge Triggered Non AEOI
Figure 11. Manual Acknowledge Mode Operation
2·200
AP-401
4.2.2.2 Manual Mode of Acknowledgement
The Manual Acknowledgement Mode requires that,
unlike the automatic mode where a service operation is
considered as an automatic acknowledge, an explicit
acknowledge command be issued to the 82510 to cause
INT to go inactive. In this mode the CPU has complete
control over the timing of the Interrupts. Before exiting
the service routine, the CPU can check the GIR register
to see if other interrupts are pending and can service
those interrupts in the same invocation, avoiding the
overhead of another interrupt as in the Automatic
mode. Of course the user has the option of issuing the
acknowledge command immediately after the service,
which would be similiar in behavior to -the automatic
mode. If the manual acknowledge command is given
before the active source has been serviced and no higher
priority request is pending, then the same source will
immelliately generate a new interrupt. Therefore, the
software must make sure that the Manual Acknowledge command is issued after the interrupt source has
been serviced by the CPU (see section 4.2.3.2. for more
details on interrupt service procedures for each source).
READ CORRESPONDING
STATUS REGISTER &:
SERVICE ALL APPROPRIATE
ACTIVE BITS
RESTORE ORIGINAL
VALUE OF' GIR/BANK
TO RETURN TO
ORIGINAL BANK
231928-12
Figure 12. Typicallnterropt Handler
2-201
AP·401
4.2.3 GENERAL INTERRUPT HANDLER
In general an interrupt handler for the 82510 must first
identify the interrupt source within the 82510, transfer
control to the appropriate service routine and· then
service the active source. The active source can be identified from two registers-General Interrupt Register,
or General Status Register. The GIR register identifies
the highest priority active block interrupt request. The
GSR register identifies all active (pending or in service)
Block Interrupt Requests. The typical operation of the
82510 interrupt handler is given in Figure 12. The two
major issues of concern are the source identification
and Control Transfer to the appropriate service routine.
Since the 82510 registers are divided into banks, and
the interrupt handler may change register banks during
service, it is best to save the bank being used by the
main program and then do the interrupt processing.
Upon completion of service, the original bank .value is
restored to the GIR/Bank register.
4.2.3.1 Source Identification
The 82510 has 16 interrupt sources, and the CPU must
identify the source before performing any service. AI·
though the procedure varies, the typical method would
be to identify the block requesting service by reading
I
USER PRIORITY
= RX FIFO (Hi)
RX MACHINE
TIMER
[ TX FIFO
TX MACHINE
MODEM (LOW)
231928-13
Figure 13. Bypassing the 82510 Fixed Interrupt Priority
2-202
inter
Ap·401
GIR bits 3-1. If the source is either Tx Machine, Tx
FIFO, or Rx FIFO, no further indentification is needed, the user can transfer control to the service routine
(in most cases, only one Timer will be used, therefore
the Timer Routine can also be directly invoked). All
modem I/O interrupts can be handled via one routine
as all the modem interrupt sources are supplementary
to the modem handshaking function. The Rx Machine,
however, has two different types of interrupt sources,
event indications (CCR/Address recognition CCR/Address Match, Break Detect, Break Terminate, and
Overrun Error), and error indications (parity Error,
Framing Error, these error indications do not refer to
any particular character, they just indicate that the specific error was detected during reception). For most applications, the error indicators can be masked off, and
only the event driven interrupts enabled. The error indicators can be read from the Receive Flags prior to
reading a character from the FIFO. This interrupt
scheme can be used, because the Receive character error indicators are available in the Receive Flags, and
can be checked by the Receive routine before reading
the character from the Rx FIFO.
Since all active status bits (except Rx FIFO interrupt in
LSR and RST) are reset when the corresponding block
status register is read, the interrupt routine must check
for all possible active sources within the block, and
service each active source before eXiting the interrupt
handler.
The 82510 interrupt contention is resolved on a fixed
priority basis. In some applications the fixed priority
may not be suitable for the user. For these cases the
user can bypass the 8251O's priority resolution by using
the General Status Register (rather than GIR) to determine the block interrupt sources requesting service.
Each source is checked in order of user priority and
serviced when identified (There will be no problem with
using this algorithm in auto acknowledge mode because
the INT pin will go low as soon as a pending and en.
abled interrupt request goes low). The user will be trading some service latency time for additional source
identification time, this algorithm's efficiency will improve as the number of block sources to verify is reduced. See Figure 13 for the algorithm.
4.2.3.2 Interrupt Service
A service operation is an operation performed by the
CPU, which causes the source of the 82510 interrupt to
go inactive (it will reset the particular status bit causing
the interrupt). An interrupt request within the 82510
will not reset until the interrupt source has been serviced. Each source can be serviced in two or three different ways; one general way is to disable the particular
status bit causing the interrupt, via the corresponding
block enable register. Setting the appropriate bit of the
enable register to zero will mask off the corresponding
bit in the status register, thus causing the INT pin to go
inactive. The same effect can be achie,-:ed by masking
off the particular block interrupt request in GSR via
the General Enable Register. Another method, which is
applicable to all sources, is to issue the Status Clear
command from the Internal Command Register. The
detailed service requirements for each source are given
below:
Table 4. Service Procedures For Each Interrupt Source
Interrupt
Source
Status Bits
& Registers
Interrupt
Masking
Timers
TMST(1-0)
GSR (5)
TMIE (1-0)
GER(5)
ReadTMST
Issue
Status Clear
(StC)
Tx
Machine
GSR (4)
LSR(6)
GER (4)
Write Character
toTx FIFO
Issue StC
Rx
Machine
LSR (4-1)
RST (7-1)
GSR(2)
RIE (7-1)
GER(2)
Read RST or LSR
Write 0 to bit
in RST/LSR
Issue StC
RxFIFO
RST/LSR (0)
GSR (0)
GER (0)
Write 0 to LSR/RST
Bit zero.
Read Character(s)
Issue StC
TxFIFO
LSR (5)
GSR(1)
GER (1)
Write to FIFO
ReadGIR
Issue StC
Modem
MSR (3-0)
GSR(3)
MIE (3-0)
GER (3)
ReadMSR
write 0 into the
appropriate bits of
of MSR (3-0)
Issue StC
Specific
Service
General
Service
NOTE:
The procedures listed in Table 4 will cause the INT pin to go low only if the 82510 is in the automatic acknowledge mode.
Otherwise, only the internal source(s) are decoded, the INT pin will go low only when the Manual Acknowlege command is
issued.
2-203
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AP-401
4.3 Polling
The 82510 can be used in a polling mode by using the
General Status Register to determine the status of the
various 82510 blocks, this is useful when the software
must manage all the blocks at once. If the software is
dedicated to performing one function at a time, then
the specific status registers for the block can be used,
e.g. if the software is only going to be Transmitting, it
can monitor the Tx FIFO level by polling the FIFO
Level Register, and write data whenever the Tx FIFO
level decreases. Reception of data can be done in the
same manner.
5.0 SOFTWARE CONSIDERATIONS
5.1 Configuration
The 82510 must be configured for the appropriate
modes before it can be used to transmit or receive data.
Configuration is done via read and write registers, each
functional block (except for BIU) has a cQnfiguration
register. Typically the configuration is done once after
start up, however, the FIFO thresholds and the interrupt masks can be reconfigured dynamically. If the
82510 configuration is not known at start up it is bestto
bring the device to a known state by issuing a software
reset command (ICM register, bank one). At this point
all block interrupts are masked out in GER and all
configuration and status registers have default values.
The bank register is pointing to bank zero. The 82510
can now be configured as follows:
1. If BRG A is being issued as a baud rate generator
then load the baud rate count into BAL and BAH
registers.
2. Configure the character attributes in LCR register
(Parity, Stop Bit Length, and Character Length).
(Note if interrupts are being used, steps 1 and 2 can
also be done at the end, since the user will have to
return to bank zero to set the interrupt masks in GER)
3. Load ACRO register with the appropriate Control
or Address character (if using the Control Character Match or Address Match capability of the
82510).
4. Switch to Bank two.
(In this. Bank the configuration can be done in any
order)
5. Configure the Receive and Transmit FIFO thresholds if using different thresholds than the default).
6. Configure the Transmit Mode Register for the
Stop Bit length, modem control, and if using echo
or 9 bit length or software parity,configure the
appropriate bits of the register. The default mode
of the modem control is Manual, if using the FIFO
then the automatic mode would be most useful).
7. Configure the Rx FIFO depth, interrupt acknowledge mode, /-tlan or normal mode and echo modes
in IMD register.
8. Load ACRI if necessary
9. Enable Rx Machine Interrupts as necessary via
RIE.
10. Configure RMD forCCR, DPLL operation, Sampling Window, and start bit.
11. Switch to Bank 3.
12. Configure CLCF register for Tx and Rx clocks and
or Sources
13. Configure BACF register for BRG A mode and
source.
14. Load BBL and BBH if BRGB is being used (as
either a BRG or a Timer).
15. Configure BBCF register if necessary.
16. If reconfiguration of the modem pin is necessary
then program the PMD register.
17. Enable any modem interrupt sources, if required,
via MIE register.
18. Enable Timer interrupts, if necessary, via TMIE.
19. If using interrupts
then
i) Switch to Bank zero.
Disable Interrupts at CPU (either by masking
the request at the interrupt controller or executing the CLI instruction).
ii) Enable the appropriate 82510 Block interrupts
by setting bits in the GER register. (CPU interrupts can now be reenabled, but it is recommended to switch banks before enabling the
CPU interrupts).
NOTE:
At this stage it is best to leave the TxM and Tx FIFO
interrupt disabled. See section 6.3 Transmit Operation
for details)
.
20. Switch to Bank One. Load Transmit Flags if using
9-bit characters, or 8051 9-bit mode or software
parity. If using interrupts CPU interrupts can now
be enabled.
Bank One is used for general operation, the 82510 can
now be used to transmit or receive characters.
2-204
AP-401
GENERAL
CONFIGURATION
CONFIGURE:
1. STOP BIT LENGTH
2. MODE OF RTS CONTROL
3. 9-BIT CHAR. LENGTH}
N
4. S/W PARITY
OPTIO AL
5. AUTO ECHE MODE IN
TRANSMIT MODE REGISTER
SET RX FIFO DEPTH.
INTERRUPT
ACKNOWLEDGE MODE,
J.LLAN OR NORMAL AND
AUTO ECHO IN INTERNAL
MODE REGISTER
ENABLE INTERRUPTS" FOR
RX STATUS BITS VIA
RX INTERRUPT
ENABLE REGISTER
231928-14
SET MODES OF CONTROL
CHARACTER RECOGNITION,
DATA SAMPLING, AND
DPLL USE,
IN RX MODE REGISTER
TO C
231928-15
Figure 14. Configuration Flow Chart
2-205
intJ
AP·401
MOOEW AND
'rIMING UNI1
CONriGURATION
C
IN CLOCKS CONFIGURE
REGISTER: SELECT SOURCES
OF TX .It RX CLOCKS
SELECT MODES OF
TX .It RX CLOCKS
CONFIGURE BRG A CLOCK
SOURCE AND MODE OF
OPERATION VIA BRG A
CONFIGURATION REGISTER
o
ENABLE THE 82510
BLOCK INTERRUPT
SOURCES VIA GENERAL
ENABLE REGISTER
CONFIGURE BRG B FOR
SOURCE AND MODE VIA BRG B
CONFIGURATION REGISTER
(IF BEING USED AS A BRG)
ENABLE INTERRUPTS
(IF NECESSARY) ON
MODEW INPUT PINS VIA
MODEM INTERRUPT
ENABLE REGISTER
231928-17
ENABLE TIMER INTERRUPTS
AS NECESSARY, VIA
TIMER INTERRUPT
ENABLE REGISTER
TO 0
231928-16
Figure 14. Configuration Flow Chart (Continued)
2·206
inter
AP-401
The transmitter has two status flags. Tx Machine Idle
and Tx FIFO interrupt request, each of these conditions may cause an interrupt, if enabled. The Transmit
Idle condition indicates that the Tx Machine is either
empty or disabled. The Tx FIFO interrupt bit is set
only when the level of the Tx FIFO is less than or equal
to the threshold. These interrupts should remain disabled until data is available for transmission. Because
outside of disabling the corresponding GSR status bits,
the only way to service Tx Idle is by writing data to the
Transmitter. Otherwise, the Tx Machine interrupt may
occur when no data is available for transmission, and as
a result will keep the INT pin active, preventing the
82510 from generating any further interrupts (unless
the Transmit Interrupt routine automatically disables
the Tx Machine Idle and Tx FIFO interrupt requests in
GSR). The threshold of the Tx FIFO is programmable
from three to zero, at a threshold of three the Tx FIFO
will generate an interrupt after a character has been
transmitted. While at a threshold of zero the interrupt
will be generated only when the Tx FIFO is empty. For
most applications a threshold of zero can be used. If the
threshold is dynamically configured, i.e. it is being
modified during operation, then the Tx FIFO level
must be checked before writing data to the transmitter.
T
X
F
I
F
4
o
L
E
V
3
E
L
-2
THRESHOLD
INACTIVE
INTERRUPTS
ACTIVE
231928-18
- - Tx Machine and 82510
---- User write operation
Figure 15. Tx FIFO Interrupt Hysteresis
5.2 Transmit Operation
5.2.1.1 Transmit Interrupt Handler
5.2.1 GENERAL OPERATION
To transmit a character the CPU must write it to the
TXD register, this character along with the flags from
the Tx Flags register is loaded to the top of the TX
FIFO. If the Tx Machine is empty, then the character
is loaded into the shift register, where it is serially
transmitted out via the TXD pin (the flags are not
transmitted unless the 8251O's configuration requires
their transmission e.g. if software parity is selected then
the S/W parity bit is transmitted as the parity bit of the
character). The CPU may write more than one character into the FIFO, it can write four characters in a burst
(five if the Tx Machine is empty) or it can check the
FIFO level before each write, to avoid an overrun condition to the transmitter. In the case of the latter, the
software overhead of checking the FIFO level must be
less than the time required to transmit a character, otherwise the transmit routine may not exit until another
exit condition has been met.
e.g. at 288,000 bps for an 8-bit char no parity
It takes 34.7 p.s to transmit one character.
If the time, from the write to TXD to the reading of the
Transmit FIFO level, is greater than 34.7 p.s then the
Tx FIFO level will never reach higher than zero, and
the FIFO will always appear to be empty. Therefore, if
the transmit routine is checking for a higher level in the
FIFO it may not be able to return until some other exit
condition-such as no more data available-is met.
This can be a problem in the interrupt handler, where
the service routine is required to be efficient and fast.
The Transmit Interrupt Handler will be invoked when
either the Tx FIFO threshold has been met or if the
Transmitter is empty. Since the Tx Machine interrupt
is high priority (second highest priority, with Timer
being the highest), the interrupt line will not be released
to other lower priority, pending 82510 sources until the
Tx Machine interrupt has been serviced. If no data is
available for transmission, then the only way to acknowledge the interrupt is by disabling it in the General
Enable Register. Thus the Tx Machine interrupt should
not be enabled until there is data available for transmission. The Tx Machine interrupt should be disabled after transmission is completed.
5.2.1.2 Transmission By Polling
Transmission on a polling basis can be done by using
the General Status Register and/or the FIFO Level Register. The software can wait until the Tx FIFO and/or
the Tx Machine Idle bits are set in the General Status
Register, and then do a set number of writes to the TXD
register. This method is useful when the software is trying to manage other functions such as modem control,
timer management and data reception, simultaneously
with transmission.
If management of other functions is not needed while
transmitting, then continuous transmission can be done
by monitoring the Tx FIFO level. A new character is
written to TXD as soon as the FIFO level drops by one
level.
2-207
inter
AP-401
DISABLE TX t.lACHINE
IDLE, AND TX FIFO
INT. REQ. IN GER
Tx FIFO Threshold = 0
231928-19
NOTE:
TxM Idle and Tx FIFO Empty interrupts are enabled by the Main Program, when data transmission is required.
Figure 16. 16 Tx Interrupt Handler Flow Chart
2-208
inter
AP-401
231928-20
Figure 17. Using GSR for Polling
2-209
intJ
AP·401
231928-21
Figure 18. Data Transmission by Monitoring FIFO Level
2·210
AP-401
231928-22
Figure 19. Break Transmission Using Tx FIFO to Measure Break Length
2-211
intJ
AP-401
5.2.1.3 Break Transmission
The 82510 will transmit a break when bit six of the
Line Control Register is set high. This will cause the
TXD pin to be held at Mark for one or more character
time. The Tx FIFO can be used to program a variable
length break, see Figure 19 for details. If the break
command is issued in the midst of character transmission the TXD pin will go low, but the transmitter will
not be disabled. The characters from the Tx FIFO will
be shifted out on to the Tx Machine and lost. To prevent the erroneous transmission of data, The CPU must
make sure the Transmitter is empty or disabled before
issuing the Send Break command.
R
X
OVERRUN
F
I
F
4
o
".,.,
L
E
V
3
E
... --------- ---
5.3.1 RECEIVE INTERRUPT HANDLER
The Receiver will generate two types of interrupts, Rx
FIFO interrupt and Rx Machine Interrupt. The Rx
FIFO interrupt requires that the CPU read data characters from the Rx FIFO. If the Rx Machine interrupts
are disabled then the CPU should also check for errors
in the character before moving it to a valid buffer. The
interrupts generated by the Rx Machine can be divided
into two categories--occurrence of errors during reception of data (parity error, framing error, overrun error),
or the occurrence of certain events (Control/Address
character received, Break detected, Break Terminated).
For typical applications, the error status of each received character can be checked via the Receive Flags,
and the events can be handled via interrupts.
,,
L
~
,-2
THRESHOLD
,,
,
..,,
,,
o~--~--------------------~---+
INACTIVE
INTERRUPTS
read characters from the 82510. Each character on the
Rx FIFO has flags associated with it, all of these flags
are generated by the Rx Machine during reception of
the character. These flags provide information on the
integrity of the character, e.g. whether the character
was received OK, or if there were any errors. The receiver status is provided via the Receive Status Register
(RST), which provides information on events occurring
within the Rx Machine, since the last time RST was
read. The information mayor may not apply to the
current character being read from the RXD register.
The CPU may read one or more characters from the
Rx FIFO. After each read, if the FIFO contains more
than a single character, a new character is loaded into
the RXD register and the flags for that character are
placed into the RXF register. The software can check
for the Rx character OK bit in the flags to make sure
that the character was received without any problems.
ACTIVE
231928-23
- - - - User Read Operations
82510 Character Reception
-
5.3.2 RECEIVING DATA BY POLLING
Figure 20. Rx FIFO Hysteresis
5_3 Data Reception
The receiver provides the 82510 with three types of
'
information:
a) Data characters received
b) Rx Flags for each data character
c) Status information on events within the Rx Ma- .
chine.
The Rx FIFO interrupt request goes active when the
Rx FIFO level is greater than the threshold, if the interrupt for this bit is enabled then it will generate an
interrupt to the CPU. This is a request for the CPU to
To receive data through polling, the 82510 can use the
General Status or the Receive Status Registers to check
for the Rx FIFO request. If the Receive routine does
not generate time outs or modem pin transitions, then
the data can also be received by monitoring the Rx
'FIFO level in the FIFO Level Register. The implementation using GSR would be useful in applications where
the software routine must monitor the timer for time
outs or the modem pins for change in status. The example polling routine illustrates the use of the FIFO Level
Register in receiving data. It waits for the Rx FIFO
request before beginning data reception. The procedure
Rx_Data_Poll will receive the number of characters
requested in Char_count and place them in the Receive buffer.
2-212
intJ
AP-401
231928-24
Figure 20. Rx FIFO Interrupt Handler
2-213
inter
AP-401
#define base Ox3F8;
'* base address of 82510 *'
#define buff __ size 128;
Rx __ Data __ Poll (Char __ count, Rxbuffer)
int Char __ count;
'* Total # of bytes to be received *'
char *Rxbuffer [buff size];
{
=
int count
0;
int status, lvI, Rok;
=
==
While «(status
(Inp(base+7) & Ox05»
OxOl) '* If Rx FIFO Req in GSR set
{
'* Assume in bank one *'
'* If Rx FIFO is not empty *' .
«Inp (base+4) & Ox70),OxlO)0&&(count < (Char __ count»
While «IvI
*1
=
{
'* If Character Received OK *'
if «(Rok
(Inp (base+l) & Oxeo»
{
=
Rxbuffer [count]
++count;
= Inp
==
Ox40)
(base);
Figure 21. Example Polling Routine
5.4.3 CONTROL CHARACTER HANDLING
The 82510 has two modes of control character recognition. It can recognize either standard ASCII or standard EBCDIC control characters, or it can recognize a
match with two user programmed control (or Address
Characters in MCS-51 9-bit mode, for Automatic Wake
up) characters. Each mode generates an interrupt
through the Receive Status Register. The Receive Flags
also indicate whether the character being read is a control character. The usage of CCR depends on the maximum number of possible control characters that can be
received at anyone time. Applications such as Terminal Drivers, which have no more than two control
characters outstanding, such as XON and Cd-C, or
XOFF and Cd-C, can use just the Control ~haracter
Match mode by programming the registers ACRO and
ACRI. If the CPU needs to process text on a line by
line basis the standard Control Character recognition
capabilit; can be used to determine when an end of line
has occurred e.g. a whole line has been received when a
Carriage Return (CR) or Line Feed (LF) is received by
theUART.
Implementation of a character oriented asynchronous
file transfer protocol can be done using both standard
and specific Control Character Recognition. In such
protocols most control characters such as Start of
Header (SOH), can only be received during certain
states, these characters can be received via Standard
Control Character Recognition. A few Control Charac-
ters (e.g. abort) can be received at any stage of communication, these can be received by using the Control
Character Matching capabilities of the 82510.
5.3.3 BREAK RECEPTION
The 82510 has two status indications of break reception, Break Detect indicates that a break has been detected on the RXD pin. Break Terminated indicates
that the Break previously detected on the RXD line has
terminated and normal Data reception can resume.
Each of these status bits can generate an interrupt request through the Rx Machine Interrupt request. Normal consequence of break is to abort the data reception
or to introduce a line idle delay in the middle of data
reception. In the case of the former, the Break Detect
interrupt can be used to reset the 82510 Receive Machine and the Rx routine flags; in the case of the latter,
the break terminated interrupt can be used to filter out
the break characters and resume normal reception.
Each break character is identified by a break flag in the
Rx Flags Register (the CCR flag, Framing error, and
CCR Match flag also may become active when a break
character is received) and is loaded onto the Rx FIFO
as a NULL character. If break continues even after the
Rx FIFO is full, then an overrun error will occur but
no further break characters will be loaded on to the Rx
FIFO. The user can also measure the length of the
break character stream by using the Timer.
2-214
intJ
Ap·401
RXM INTERRUPT--+
READ DATA CHAR
READ CONTROL CHAR
231928-25
Figure 22. Handling Control Character Interrupts
2-215
inter
Ap·401
SPECIAL ClL-CHARACTER
= XOF'F'
XON
CTL-C
NO
231928-26
Figure 23. Using Control Character Match In Terminal Ports
2-216
inter
Ap·401
5.3.4 DATA INTEGRITY
To improve the reliability of the incoming data the
82510 provides a digital filter, a Digital Phase Locked
Loop, and multiple sampling windows (which provide a
noise indication bit).
5.3.4.1 Digital Filter
The Digital Filter is used to filter spikes in the input
data. The Rx Machine uses a 2 of 3 filter. The output is
determined by the majority of samples. If at least two of
the three samples are "1" then the output will be a "1".
Spikes of one sample duration will be filtered but spikes
of two or more samples duration will not be filtered.
5.3.4.2 Digital Phase Locked Loop
The Digital Phase Locked Loop (DPLL) is used by the
Rx Machine to synchronize to the incoming data, and
adjust for any jitter in the incoming data.
The 82510 DPLL operates on the assumption that a
transition in the incoming data indicates the beginning
of a new bit cell. A valid asynchronous character frame
will contain one or more transitions depending upon
the data. If upon occurrence of the transition, the
DPLL phase expectation is different from the sampled
phase, then there is jitter in the incoming data. The
DPLL will compensate for the phase shift by adjusting
its phase expectations, until the expected phase and the
sampled phase are locked in. The user can enable or
disable the DPLL through the Receive Mode Register
(RMD).
5.3.4.3 Sampling Windows
The sampling windows are used to generate the data
bit, by repeated sampling of the RXD line. The bit polarity decision is based upon a majority vote of the samples. If a majority of the samples are "1" then the bit is
a "1". If all samples are not in agreement then the
Noisy Character bit in the RXF register is set. The sampling windows are programmable for either 3 of 16 or 7
of 16. The 3/16 mode improves the jitter tolerance of
the medium. While the 7/16 window improves the impulse noise tolerance of the channel.
The sampling windows also provide a Noisy character
bit in the RXF register. This bit indicates that the current character being read had some noise in one or
more of its bits (all the samples were not in agreement).
This bit can be used along with the Parity and Framing
error bits to provide an indication of noise on the channel. For example, if the Noisy Character bit and the
Parity or the Framing errors occur simultaneously,
then the noise is probably sufficient to merit a complete
check of the communications channel. The noisy bit
can also be used to determine when the cable is too long
or the baud rate is too high. The user would keep a tally
of the noisy characters, and if more than a certain number of characters were received with noise indications;
then either the baud rate should be lowered or the distance between the two nodes should be reduced.
5.4 Timer Usage
The 82510 has two baud rate generators, each of these
can be configured to operate as Timers. Typical applications use BRG A as a BRG and BRG B as a Timer.
Since both the Transmitter and the Receiver may need
to generate time outs, it is best to use the Timer as a
Time Base to decrement ticks (upon a Timer Expired
Interrupt) from (software implemented) Tx and/or Rx
counters. The Timer can also be used to time out the
Rx FIFO and read characters that otherwise may not
have been able to eXgeed the Rx FIFO threshold.
5.4.1 USE AS A TIME BASE
The transmitter and the receiver routines use a software
variable which acts as a counter. The variable is loaded
with the required number of ticks that are needed for
the Time Out period. Once started the Timer generates
an interrupt each time it expires, the interrupt handler
then decrements the counters. Once loaded the software monitors the counters until their value reaches
zero, this would indicate to the software that the required time period has elapsed. The Time Base value
should be selected with regards to the CPU interrUpt
load. The CPU load will increase substantially when
the Timer is used as a Time Base, therefore using the
Timer in this mode at very high baud rates may cause
character overruns. A time base of 5 or 1 ms is probably the most useful. An additional benefit of the Time
Base is that it can support more than two counters if
required.
2-217
inter
Ap·401
5.4.2 USE FOR RX FIFO TIME OUT
BRG·B is used as Timer.
BRG·A is used as BRG. '
-TB Ex bit in TMST Enabled.
T><-Timer_Count contains count.for Transmitter.
R><-Timer_Count contai~s count for Receiver.
In the 82510, Rx FIFO interrupts will occur only after
the FIFO level has exceeded the threshold. Due to this
mechanism and the nonuniform arrival rate of characters in asynchronous communications, there is a chance
that characters will be "trapped" in the Rx FIFO for
an extended period of time.
For example, assume the 82510 is a serial port on a
system and is connected to a terminal. The user is entering a command line. The Rx FIFO Threshold = 3,
and at the end only two bytes are received. Since the
FIFO threshold has not been exceeded, the Rx FlFO
interrupt is not generated. No other characters are received for 30 minutes, if the characters (in the Rx
FIFO) are a line feed and carriage return, respectively,
the CPU may be waiting for the CR to process the
characters it has received. Consequently the characters
will not be processed for 30 minutes.
In order to avoid such situations, a Rx FIFO Time Out
mechanism can be implemented by using the 82510
Timer. The time out indicates that a certain amount of
time has elapsed since the last read operation was performed. It causes the CPU to check the Rx FIFO and
read any characters that are present.
231928-27
Figure 24. Timer use as Time Base for Transmit
and Receive
In applications where the character reception occurs in
a spurious manner (the exact number of characters cannot be guaranteed), the Rx FIFO Time Out is the only
way to prevent characters from being trapped. The time
out period is measured from the last read operation,
every read operation resets the Rx FIFO Timer. To
synchronize with the begil;ming of the data reception,
initially the Rx FIFO threshold is set to zero. After the
first character has been received, the threshold is adjusted to the desired value. When a Rx FIFO time out
occurs and no data is available, the threshold is reset to
zero. In error free data transmission, the beginning of
data transmission is signaled by the reception of a control character, such as SOH or STX, the Rx FIFO time
out mechanism .should be triggered to the reception of
these control characters.
2-218
inter
AP-401
(
MAIN RX ROUTINE)
RX FIFO INTERRUPT ROUTINE
231928-28
231928-29
Figure 25. Rx FIFO Time Out Flow Chart
inter
AP·401
8 BIT
ONE'S
COMPLEMENT
OF PACKET
NUMBER
128 BYTES
OF DATA
8 BIT
128 BYTES
CONTROL
CHARACTER
231928-30
Figure 26. Packet Structure of XMODEM
6.0 82510 IMPLEMENTATION OF
XMODEM
6.2 Software
The 82510 XMODEM implementation is a file transfer
program for the 82510 based on the XMODEM protocol. The software runs on the PC AT on a especially
designed adapter board (the adapter' board design is
shown in Figure 33). The software uses most of the
82510 features including the baud rate generator, Timer, Control Character Recogiiition and FIFOs. The
software uses an interrupt driven implementation, written in both assembly and C languages.
6.1 XMODEM Protocol
XMODEM is a popular error free data transfer protocol for asynchronous communications. Data is transferred in fixed length 128 byte packets, each packet has
a checksum for error checking. The packets are delineated by control characters, which act as flags between
the Receiver and the Transmitter. There are four control characters, SOH, EOT, ACK, and NAK. SOH indicates the Start of a Packet, EOT indicates the End Of
Transmission; ACK and NAK are positive or negative
acknowledgements of the packet respectively. The
packet structure and protocol flow of XMODEM is
provided in the figures given below.
Interrupts are used to transmit and receive data. The
software is implemented as two independent finite state
machines-Transmit State Machine and Receive State
Machine. Each state machine is triggered by external
events such as user commands and data or Control
Character reception. The state machines communicate
with the 82510 interrupt service routines through software flags. The overall structure of the main routine is
given in Figure 31. The major modules of the software
are given in the hierarchy Chart, Figure 34, which lists
the different modules in order.
The interface between the main program and the interrupt service routine is done through global flags. The
interrupt handler services four sources-Transmit,
Timer, Receive, and Control Characters. Each of the
interrupt sources communicates with each of the state
machines through the global flags. The state machines
keep track of their individual states through state variables. The interface between the individual states within
a state machine is done through state flags. The state
machine diagrams are given in Figure 29 and Figure
30.
2-220
intJ
Ap·401
(
TRANSMIT)
NO
ASSEMBLE
NEXT PACKET
231928-31
Fi$lure 27. Protocol Flow for Transmit Side of XMODEM
2·221
Ap·401
SEND NAK
SEND ACK
RX PACKET #
AND PACKET COMP
231928-32
Figure 28. Protocol Flow for Receive Side of XMODEM
2-222
inter
Ap·401
NAK
RXD
231928-33
Figure 29. Transmit State Machine
2-223
Ap·401
4 SEC TIME OUT
AND <10 TIME OUTS
231928-34
Figure 30. Rx State Machine
2-224
inter
Ap·401
mit interrupt service routine reads characters from the
packet buffer and writes it to the Tx FIFO. Since it
does not require the use of the Transmit Flags. no information is written to the TXF register.
START
Initialization
WHILE (NOT QUIT)
{
UPDATE STATUS ON SCREEN
IF (KEYBOARD HIT)
THEN PROCESS COMMAND
PROCESS TRANSMIT STATE MACHINE
PROCESS RECEIVE STATE MACHINE
6.2.2 RECEPTION OF DATA
I
END
Figure 31. Software Structure
6.2.1 TRANSMISSION OF DATA
The Transmit interrupts are disabled until data transmission is required. this prevents unnecessary Transmit
interrupts. The Transmit. interrupt is enabled when a
packet has been assembled or if a Control Character is
required to be transmitted. Upon invocation the Trans-
Data reception begins only after a Start of Header
(SOH) control character is received. This control character puts the receiver in a data reception mode. After
receiving the SOH. the CCR interrupt is disabled (since
.all data being received now is transparent and can not
be interpreted as a control character). After 132 characters are received. the CCR interrupt is reenabled and
the corresponding ACK or NAK sent to the Transmitting system. The receiver has a time out feature. which
causes it to check the Rx FIFO for any remaining characters. End of Transmission is indicated by an EOT
control character, which causes the file to be closed and
the Receiver to go into the Idle state.
...------...;....- SEND_CCR_RQ(rROM RECEIVE STATE MACHINE)
TX
STATE
MACHINE
CCR_TO_GET
GET_CCR_RQ
~-~
RX
STATE
MACHINE
BYTES RXD
RECEIVE
G
Figure 32. Using Flags for Communications with Interrupt Routine
2-225
231928-35
l
74LS04
A8_~A8
OPSW
~
15
+5V
1
AEN
R2
2
2K
2
+12V
L.!!..!........
2
~A
r---"3
4' ~O
1
R1
2K
2
1Y 7
-1~~
5
US
""c:
is
CiI
I\)
i\,
~
CONNECTOR
~
TX01
!i
RX01
....
1
~
"U
()
'P
o
~
III
1...
75154
U10
+5V
6 3A
3 1T
U3
RI
Ci'S
OSR
74LS05
~2
L-
CO
U4
231928-36
l
"TI
ra"
e
ii1
Co)
f'>
I\)
:l:
r\:,
CD
I\)
-...j
ri
CONVIG_510
»
l
...
INILINLHANDLER
ii1
o
:T
'<
o
:T
DI
:::.
231928-37
inter
6.3 Software Listings
MAIN FROGRAM
PAGE
ftp 0
82510 XHODEH
hnclude "t \ftp\ftp def"
'Include "C Ilc\fcntl hI!
hnc:lude "e \IC\5tdl1b h"
.Include "C \le\stdio hIt
1.**.*IiI* ••• _•• *".**.* •• I,,*** •• *~ ••••••••••• *•••••• '
*•••• /
/*.*
..... ,
•••• - J
SEPTE"BER 1986
10
11.
tz
13
.*.*t/
B2S10 tHODEH IMPLEMENTATION
, •••• ** •• ** ••••••••••••••••• '11 • • • 111 • • _ • • • • • • • • • • • • • /
Int
tof .dllse,
f. end of fll_ flag
*'
lQt
npk =0.
hrfl9.
nrfig,
es:p_pkt_null.
pkst,
25
20
lnt
lnt
lnt
lnt
lOt
lnt
lnt
lnt
lnt
lnt
lnt
lnt
lnt
lnt
"
/* FlI. to be Transmitted
14
15
16
l'
IB
19
20
21
22
23
24
Z8
Z9
30
31
32.
/ ' nelt
1,
qUI t
.
=(J,
1st.
0,
key
sohent =0,
n(c:.nl .0,
cercnt =0,
tl:_5 tate .ll_ldll,
fl_statl = 1'1:_ldle.
Inactive,
tB olld
lnactue;
el_cad
-
char
packet number upeeted by reeelTlr '/
/' Tla. Out c.ounter fo, rtC.I"r ' /
rwtocnt,
..
h_fl1,_nalle[40l.
/ ' I of SOli char at t er I rtC:tl'l.d ' /
/' I of h FIFO Interrupts ' /
/. I of ttl-Char . Interrupts '/
/ ' Tr In511l t t tr Shot. Vuuble ' /
/ ' Receiver Sta.h Vat uble ' /
/' IndaatlS
/' IndlCatu
*'
• Valid
• valid
Tl COllsand was guen ' /
R. Co •• and
.WII
usued '/
1* FII, to be Recilved *1
t.:hat
fI f11e_na.,[40] =
33
34
lnt
send_cce_req = Inactlv •.
3'5
3&
31
Int
Int
char
char
char
char
lntVtC =0,
I.
hdata [1321.
38
39
40
1* Flag - RlqulSt to T. Ct I-Char
1* I:Ontl.1n5 the CIa VIctor
'*,
,*1*
flbuf [128].
rxdata [1311,
fI_f_buf (32000)'
*'
'*'
T. Bufhr
R. Bufhr *1
1* R. File Stored in thll buffer
*'
41
42
43
44
45
I
*************.******.******* I
'***
t. state varllbles **11**/
1*'11:'11:'11:'11:'11:**'11:**'11:*'11:****'11:**'11:*'11:*'11:** I
Int
tI:_lnd •.
strutt
pac.ket
char
char
ehat
'*
46
POinter to the neat thuaeter In the
buf fer * I
4'
48
49
50
51
52
53
char
head.
pack_hulD.
pack_cap I ,
buff er [12B] ,
char
Chks~.
54
55
56
57
5t ruct pac.ket rapaek. tlpacl: ,
231928-38
82510 XMODEM Implementation
2-228
intJ
AP·401
HAIN PROGRAK
PAGE
lip.
82510 IHODEH
58
59
/ •• '11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 •••••••••••••••••••• I
60
/**..
t. State aachlne and tnhr[upt
handler
....... /
...... ,
fllVI
&1
/.....
61
63
, ••••••••••••••••••••••••••••••••••••••••••••••••••••• I
&4
, .. hm ud h
fifo
**1
1* Flag - Indicates. request for tran.ausion to
11510 Inhrrupt Handlu 'II/
CCt_to_tI ... 0,
Actual Ctl-char to Trans.it *1
h_byte_cnt .0,
Total' of ayt .. Tran •• itted */
pU'_'lnt .0,
/*. of Paeket. lint'll/
65 lnt
66
"Jnt
68
Int
69 lnt
tI_teq .0,
,'II
,'II
70
71
71
1** Tuut
**1
ta_tuDe_cnt =0,
lnt
,'II
Tranlmitter Tllatr Counter'll/
73
74
15
16
77
78
79
80
81
82
, . . CCR **1
get_ccr_rq ... 0,
I. Flag - aequelt to Rlcelve etl-character
etr_to_vet .0, f. Reclued Ctl-char value'll/
tnt
lRt
'II/
, ••••••••••••••••••••••••••••••• _ ••••••••••••••••••••• ••••• ,
/.u.
'uu
1****
83
IUU
84
I •••• *
U*.*/
* •• ** I
RX STATE VAR IABLES
•••• *I
**.** 1
* *•••• lit • • • *•• ** .:t* •••••••• '/1 * lit • • • ** •••• * •• * •• * •••• * ••• I
85
U
81
88
89
90
?t
H
93
94
char
Int
Int
95
1**
96
Int
'**
98
99
101
102
103
104
105
bad_pkt_cnt,
1* Calcuhted ChksulD *1
1* • of EOTs ReCeived
I
I • • of Bad Pachts Recuved *1
*
I •• ** * ••• * * ••••••• * ••••••• * ••••••••••••••••••••••••• ,
,UU
ra It&t. 'Iuthlnl!! &nd Interrupt
•• ".1
1****
h&ndler fIaq5
*U**,
I •••••••••••••••••••••••••••••••••••• • **.**.* •••• 11:.* I
97
100
eot_cnt .0.
fifo ** I
r a_by t I!!_cn t .0,
I•
•
of Bytes Rec'lVed .,
eeR ttl
th&t a ttl-Char
reeuvd·1
I. AetUJ,l Ctl-ehu recuvtd ./
I. Flaq-indlcatlnq
lnt
Int
has been
/.* Timer
Int
•• ,
[I_tlae_cnt =0,
I. ReceIVe Timer Count
.,
231928-39
82510 XMODEM Implementation (Continued)
2-229
inter
Ap·401
MAIN PROCRAM
PAGE
106
107
108
109
110
111
112
113
Itp c
1*** •••••••••••• ** •••••••• " ••• ** •••••• " •• ,
,.*
t_1 fl. 11*. I I .t"
.t.t .. *IU* ....
111*"
MAIN ROUTINE
, ...
JI
I
ttt ..... "11 t
Int
.nt
.nt
115
116 • nt
117. .nt
q.tlfl,[lfI,
rval,v .0,
0,
cmd
wn_,t,&tul .0 •
118
.. fp.
-flfp,
.
.cod.'
rx Lt
119. FILE
120 • nt
121
lnt
122. .nt
123 .nt
124 int
125 .nt
:I::
0,
twst •
west,
rttl_cnt =0,
tocnt .0,
.
count */
Till' Out Count */
1,1,
Ipcnt
0,
127
CLR 0,
128
1Z9
130
"V_CURS (&0_[, 10_C) ,
printf 111);
inl t (),
MENU 0,
tnblnt4 (),
outp (lpOQ,eoi),
outp «bp&+3),OI2Z),
1 pent =0,
131
13Z
133
134
/ •••
'*'* R.tranllut
ta_secs, ,._'ICS,
116
138
139
140
141
... ,
*t
mlln ()
114
135
136.
137
82510 IMODEII
** *t ..... *'/1""
"
"
"
"/*
Clear Scr •• n
*'
SI"n On M,,,ag,
"
Inltul11t 82510 ond VuiaUu
Pr Int Mlnu *'
Enab I, Interrupts in USIA ' /
"
15IUf EOI
*/
/' stut tlaer B '/
of Loops ,/
/* Keeps Track 01
/'
•
ft • • • • • • _ • • • • _ • • • • _
. t t ..... t __ • • • __ • • • ,
/*..
D.l1n while loop
•• tt/
, ••••••••••••••••••• *t t t t t t t t t tt t t t t t t t t t t t t . t t t t t . ,
while (quih=f.lse)
(
142
143
144
14:5
146.
147.
148
149
1'50
151
1$2.
153
154
155
156
1'57
158.
159
HO
161
lU
163.
164
.65.
I t t t t t t t ._._t tt t t . t t t t_t.t t t t t 11 t t . tt t t ,
'ilt
dISplay protocol parl.,tirs
, t ••••••• t . t •• t ttfl.t 11 t t t t . t . '/I t t t
ttl
*t . t t . I
++ Ipent;
.v_curs
(~,30),
prlntf (1lloop • '"' 'll.u",lpent),
.. ,,_euts (4,50),
ponti
.,,_cuts
ponti
.. ,,_curs
prlntf
("rl lnt cnt
'ttu",rlfenU,
(5,501,
("cer lDt cnt .. 'rtu",eerent);
(4,1),
("interrupt "eetor I;: "u \nll,
q .. tnp (bpa+4),
hfl .. q & 0107,
1D.,_eurs (5,ll,
prlntf ("TX FIFO
",hfl),
q .. Inp (bPI+4),
t l f l = q & 0170;
.,_curs (6,1),
prlntf ("RX FIFO
\n",ufl/16),
.,,_curs (6,50),
prlntf ("SOH count = "3u",sohcnt),
int,.e),
"U
"u
231928-40
82510 XMODEM Implementation (Continued)
2-230
AP-401
PACE
MAIN PROCRAM
ftp c
81110 XMODEM
166
167
.. ,,_curs (1,1),
prlntf ("bytes uc:dud 'Uu",tI_bytl_c.nt),
U8
169
170
171
172
173.
.'_C.UrI
174
.,_curl (6.30),
printf ("pUs .ent • "h", pU._untl,
ta_I'u. tl_tia,_cnt/2.00.
175
116
(7,30),
printf ("a,tll Sent. IUu",tl_byll_c.nU,
a,,_curs (1, SO) ,
pr tntf ("EOT count .. au" I lot_cntl.
."_CUrI (S,30),
punt(
("pkta rid . . . 3u",(tlp_ptt_ftU1D-1l),
177
178
rJ_ItCI • lI_t ia,_ent 1200.
open_wind (3,l,"TI Ti.erOl)j
119.
1.0
181
111
printf ( I I . 'ltlu I.C.",tI_IIU),
open_wind (3,SO,"R. Tlll.r"),
183
184
115
printf
• t.lu •• el",[I_IIe.II,
(8,1),
pr lftt f ("Bad Packets Rad • "3u". hd_pkt_cnt) ,
."_CUri (1,30),
printf (II' of RtT, pac.kets • "3u",r.tl_c.nt);
(01
.'_CUII
116
117. 1* If Co •• and Illuad then proce .. the Co •• and ./
188
If «kl, .tbhltO) ) 0)
189
qUl t .. procell_cad (),
190
191
el.e
192
(
193
194
,***************************************.**.* •• ****.** ·**1
191
IU."
Proce .. TI STATE MACHINE
*****1
196
/. ** ••
reVI'10n 0
*****1
197
1**· ••
*****1
198.
I· *.* *.* ** *** .* •• **.* *.*.* .*** ••••• *.*.** *•••••• ** ••••• *.1
199
.wltch (lx_state) (
200
201
CUt h_141e:
202
203
/ ••••••• *•• *•• *. *. ***.* ••• ** *.*. **•••••• *.*. *.*.* ••• *••• *,
204
•• **./
,.... TRANSMITTER IDLE STATE
201
***.*,
/.* ••
206
*•••• ,
J ••••
207
Checks
for
a
Send
Ct
I-Char
*****1
I· _ ••
208
ChICh for the Trans.it CO.lland *****1
fI fl • • _ J
209
f· *.*
210
/. -*.
fI* *_* I
211
1* *.fI ** * _* _* **fIfI * _*fI fI *•• *.*.** fI.* *.fI* fI*_* ••• *••• _*
1
212
213
214
,. If Control Character to bt Tran •• ithd Then Tran'.lt the
211
Control Character by .ett1ng the TI_req Flag and tnablug
216
tht TIM and TI FIFO Interrupti .,
*-•••••
217
218
219
no
211
222
223
224
tl_req .ctl_chr,
t 1_I_tnb (),
wh.le ( tJ_uq)O),
tl_l_di. ()i
.end_cef_req. inlet he I
III
231928-41
82510 XMODEM Implementation (Continued)
2·231
Ap·401
PACE
5
116
It
If
227.
228
229
It the Trahllut Coamand 11 i'lued then 'Jut for I NAK .,
(ta_cad •• ICti . . )
tl_cad • Inactive;
gtt_cu_rq .acti,.,
tI_tl.,_cnt .200 • .0, 1* 60
231
232 .
233.
brlak;
235
236 .
CUI wlit_MAX
237
zn.
243
244
Ti •• Out *1
IIC.
tI_It&h .. wIlt_NAX;
234
240
241
IZ 51 0 IIIOD£II
(
230
238
239
ftP c
MA IN PROGRAM
/*
1* Wilting for .. NAK charachr to begin TI
*.
*'/I lit lit. lit lit ***....... lit lit lit .,U lit 11: *. lit""" lit III: t *. **
,....
, ....
,....
,**..
Chick. For Tt •• Out
lit
It
lit ... lit
or
* ••
245
246
wn_,tatu.
247
tWItch (wn_stltus)
*.
..... ,
.... */
.. •• *'
."**1
lit *.... lit •• lit. *. **. *lit J
"A.X Rlcehld
ChiCk_wilt
&;
*'
**lit III lit 11: t *lit. lit,. **I
TRANSMITTER \lUTINC FOR A NAK TO BEGIN
TRANSMISSION
'****
I lit lit •• *. **. lit *lit lIt.'IIt *
t
lit lit lit
tilt.
11. *lit t t
(),
lit
1* Ti.1 Out or NAK Rcvd'
(
*'
248
249
250
251 .
h_statt _h'_ldle,
252
blip 0,
/* If TilDl Out thin Abort
Tun.mlilion *1
253
pta.g ("Ti •• OUT 1111 recenet not rudy");
254
cll (tI_r, h_c),
open_wI nd (t I_r, t I_C, "NONE II
255
256
257
258
casl
WI!
tin;
259
260
) ,
break,
/t if no Ti.e Out and no NAK
rc:.d thin do nothlnQ t/
bru,k,
261
262
,t
163
164
165
If NAK recehld thin Opln
fill and adunce to
Tunlait Packet Bta te t/
266
fp .. fopen (h_ftll_naae."rb"
II (Ip". NULL)
16?
168
169
270.
blip () j
prm'9 ("ERROR III flll dOli not IIlIt");
171
272
173
ell (t K_f , t K_C) ;
open_wind (tK_r,tl_c, "nonl");
tK_.hle .tK_idle;
274
215
1?6
I
Il.e
277
278
179 .
110.
la_state. tl_rdy.
tul19 II .kpkt;
181
lIZ .
283
284
285.
}j
(
wn_.tatul • 0;
/t Fiut tnk for Ta
11 to Prepare Packet .,
/. Rllet Vait_HAIt Flag
I
*'
break I
I
brukj'- end
wait nat -,
231928-42
82510 XMODEM Implementation (Continued)
2-232
inter
PAGE
AP-401
216.
c....
187
188
119.
/....
290.
291
291
293.
*••••• _•••••••••• t III
t. tll._ •••••
fl • •
.h".
TANSKITTER READY TO TRANSMIT
,....
thrll
/....
t.
lI.t t • • • • • • • • • • t.tI
,....
Int
or rltraft.ait requelt
I
..... I
of trall.ai •• ion
prlpare packet
,....
..... ,
..... ,
.t.
Hlndler Tun •• tttin; U**.,
, • • • • • • • • • • • • • • • • • • fl . . . . . . . . . . . . . . . . . . . . . . t • • • • _ • • • •
""tt,
_t_
I
/* Any Control Character To Tranl.it? */
if «und_CCf_rtq •• leUn) "
(h_rtq •• O»
h_rtq act I_chr,
196 .
297
298.
300
301
12110 XMODEK
tl_rdy
/fI.t.
294
191
I"
/tp c
KAIN PROGRAM
It Which ShOI of tranl.illion ,./
switch (tlrfI9)
(
301
303 .
304
301
306
307
al.bplet (pth_l.nt, fp),
cp,lbuf ();
tI_uq .pkt;
308
txrflCJ .tx.t9;
tl_Indl .0,
t 1_1_lnb () I
309
310
311
31Z
313.
314.
311
316 .
317
318
319 .
310
Iff A"lablt Pactlt ff/
'* RlqUllt
to
Int. Handllr
TI data .n buffer ff,
Iff Start Tun •• tuion *1
/. Enabl. TIM ,
'II _0178
outp «bpI +7),n1),
val .0.00
outp «bpa +3),'1&1),
val.h30.
outp «bp&+l>.VIl),
811
val.0180.
812
outp (bpu6),'Ii,1),
8t3
814
815
816
nt_bant (03),
ul .. 0150.
outp «bpa),va1),
'al =0Id8,
811, Itt_dlab (03),
818 outp (.
824
val c0102,
outp «bp&+6),val),
nt_bank (00).
827 ,al .. blkenb,
818 outp «bpu1)"al),
829, val. 0101.
830 outp «bpu3),'ul),
831
ut_dlab (00),
832 , , 1 . hEO,
833 outp (bpa ,'1.1);
83~
.. 1 .. 0.01,
835, outp «bpa+U,val),
836. r"lt_dlab (00),
8Z~
826
837
1* **. ** **t *t**tt t • • t* * **_ *.** ** .**t.t.*t*t*t * I
1* IHO - Ra: FIFO depth .4, auto aCk,normal tl
1* local loopbad:
1* RHO - ASCII CCR,dllabll dpl1.1/16 .. mpl
1* wlndow,absolute .tart bit sampling
1* THD - manual modi, 1 Itop bitl
1* no '-bit char, no ./w parity
1* FI10 - RI fifo Thruhold .. 3
1* TI fifo thruhold .. 0
1* RIE - Enable
*1
*1
*1
.J
*/
*1
*1
interrupts
"
"
"
"
"
"1* SBL for 5.5 ban
"
"
"/ '
"
/'
"
1* BBH - for 5 ml ban
"
"
"1* BBCr - 1,5 clk source, timer mode
"
"
"1* TMIE - Timtt B Interrupt enabll
"
"
"" BANK 0 FOR GENERAL CONF I G
"
1* GER enable timer, tI, CCR
"
1* block interrupts
"
1* LCR - dll&bl, parity, 8 bit char
"
/'
,",
di,ilOr .0lEOH for 1200
"1*1* **eRGA
.. * ** _tt_ •• *. __ ••• t •• t •••••••••••• * ••••• t"I
rI
""
MODEM CONFIGURATION
"CLeF
161, BRGA
I
231928-52
82510 XMODEM Implementation (Continued)
2-242
AP-401
HAIN PROCRAH
PACE 16
138
83'
ftp <
1l5IG IHODEH
•• t_dlab (banle)
/ •••••••••••••••••••••••••••••• 1. . . . . . . . . . . . . . . . . . . /
840
Itt
841.
..
..
tt'
.. ,,,
842
843.
'tt
'tt
'tt
844.
1 •••••••••••• ••••••• •••• · · · · · · · · _ · · · · · · . · · · · · · · · · · ,
845
IU
847.
141.
849.
150
851
152
853.
1S4
855
856
857
8S1
859 .
160.
'61
Stt DLAI btt to allow .ee ... to
Di,itor RI9hhu
tnt bank.
(
tnt
1ftv.l.
Itt_hnt (00),
in •• l . inp(bpa +3) j
tn •• ! _inul : 0180;
outp (Upl+3),inuU;
Itt_bant (bant);
)
/. lit dlab in Lea t
..................................................
rt.tt_dlab (bank)
/
..
.. ,
..,
Jtt
,
,
/
.. ,
R••• t DtA8 bit of Lea
,.* ••••••••••
, ..
t t ...
t.* ., ............ It t
•••
t._* ....... /
HZ
8U.
164.
865.
.66
8&1.
,'I
tnt bank,
(
tnt
invil j
.et_banll: (00);
in,.l • Inp(bpa +3) i
in,.l. (invil & 0.1f)i
.69 oulp «bpa+3),iftl'll)j
810 ttt_bank (bant);
871. )
'*
dlab. 0 in LeRtl
231928-53
82510 XMODEM Implementation (Continued)
2·243
intJ
AP-401
MAIN PROCRAM
PAGE 11
871
813
814.
815
876
J.
rout
/fltU
82510 Interrupt
/**--
12510 Interrapt tOaHU
TII1
CCR
,*u*
881
882
883
,....
IU..
, ....
885
82510 X1100E11
fI*._ * 11 *'11 • • • • 11 t • • fit_ *. fI_ ._. 11 • • • 11 11 •• 11 11 *11 11 11 *fI ._ •• _ 11 .*11 fl. 11 • • • I
,u..
, .. ..
,* .. .
8?7
878.
819.
880
884
f\p c
/* . . /** . .
*****/
11****,
.t.t.
.. ... ,
1ftt
I
*_._
••••
•• If
TX FIFO
HX FIFO
TIMER B
fl • • • •
I
:
... **/
t,
*._ ..
Idtntlfus and service. the 12510 interrupt
lourc. r.qulsting S'Ulct.
u ..
tU,U/
I
,u ..
, ••• *•••••••••••••••••••••••
*.*.*/
'I"IU.** ••••••••••••••••••••••••• /
88&
881
lif_510
888
(
88.
lnl
Int
lnt
lnl
cmd_b,
st_b,
int
etle,
890
891
8.2.
8.3
8.4
8'5
89&
8.1.
898
899
.00
901
902
903
904
lnl
lnt
lnl
lnt
()
louree
1,
f 19B,
91 f."l.
f 1'11,
II _c.har,
,- Stote. Temp
V,lu. of elK */
[I
guv.1 =Inp (bPI+Z) •
It 51'1' Bank uQ15hr In telDp.
locat 10ft .1
outp «bpa+ll.0J20)
source: getsre (),
Intvle. _sourCI,
sWitch (.ourc.)
,. Cet Vector Fr01l CIR 123 ./
I. Service the Source .1
90S
906
901
cu. t Itler
, •••••••• 1: • • • • • • • • • • • • • , • • • • • • • • • • • • • • • • • • • • • • • • • , . , • • • • • ,
•••• , I
908. 1****
/
909
,*"U
TIMER SERVICE ROUTINE
/
910
1*"**
decrements h counter
d.cre .... nts
counter
911
1****
911
913
914
915
916
911
918
919
920
921
921
923
.....
.....,
.....
..... ,
....
,
I •• •••• _ •• , ••••••••••••••••••• , ••••••••••••••••••••••••• , I
It_b II' Inp (bp&+3),
If
ell (rl_t,U_C),
1161
l1U
1163
1144.
1165
/* Get ra fiIt n •• 1 ./
,
open_wind (r,_r,ta_tl"enabled");
open_wi nd (r 1_[ I rI_c+ 14, r I_I Il,_naa.) j
fl_cad alethe.
/* Actuate flag to ,ililna1
rl stat .... chlnl */
brl":,
1166
lIP
1148
1169
rst5tO (),
/* reslt 8%510 *1
0pln_wind (24,30,"1I1"1cI rl.lt");
break;
1170.
1171
I 172
1173
I 174
I I 7S
I I 76
1177
I I 78
rlt510 (),
Init (),
Inblnt4 ().
pr"IO (" 82510 runitll.l1Itd");
brlak,
1179
c.a.1
1180
1181.
1112
1183
1184
I t8S
I 186
1187
1118
1189
1190
l1fl
1* rllftltlli1l1 U510 *1
hip (),
I.ep .. ',Itl" ("d' \.Ieom");
default
BEEP ();
pralQ ("incorrect co.mand, rlentlr"),
brlak,
If (lIflO ... true)
.1..
1* if lIit comllland 1IlUld,
thin quit program *1
return (tru.),
return (fall'),
'* .nd of eo•• and proe.1I1n; */
231928-59
82510 XMODEM Implementation (Continued)
2-249
inter
AP-401
PACE 23
1192
1193.
1194
IUS,
11".
1197 .
1198.
1199 .
1200
1101.
1202.
1203
1204
1105.
1206.
1207
1208
1209
111 0
1211
f I p.
HA IN PROCRAH
.t.
umbpU (pttl_ . . ntofp)
,.t
It
**tt** * *It
t
fI
It
82510 IHOOE"
'* *'111 It •• t I: **t l~ ..... t t t *t t t •• til: tt.t_ **II: ** I
R.,d! rl1. to b, tran •• ttttd Ind putl
the data inlo tbt proper .1I0d •• picket fora,l
It*
IU
,1111 t t t
t'_.' It tt •• t t t ttt._._ *.".***'u! *t t t t t t t t ••
lnl
ptt'_'lnt,
FILE
• f Pi
t ••• _ •••
tt'
ttl
tt.t. I
/* thil valu. 11 uled to
Olt tb, nllt ptt • • /
(
int
lua oaO;
1, blkcnt,
It, f t,
char
cpU I cplcc.p,
lnt
lnl
bltcnt .(read <&tJplc:t,buffirtOl.12',l, fp);
if (bltcnt (1)
1* reid 128 b,t . . . /
(
if «It-feof(fp»
>0 && I(ft-flrrorerp»)
(
1112
tof • trUt;
1213 .
1114
1215
htp ();
pnllSa ("Ear
1* If .nd of fU, thtn
lional EOr *1
II I I
II
I I
!!
I
") j
1216 .
,llie
1217
1218
if (ft
1%19
lUO
1221
1222
1223.
1224
1 US.
1216
)0)
(
beep ();
pnU9
("READ ERROR
I I I I I I I I I I I ''') I
t __ lhhatJ_idl.;
I
cpU .pttl_'.nt +1,
1227.
tapact.pact_nu1D. cpU;
1228.
cptc.p .,"tlpact pact_null.
1229.
1230.
taPl.ct, plck_cmpt • cptc.p;
1231
1232
1213
for (1-=0, 1 (1U, i++)
IU1I. lua.tlplc.li:.bufferCll;
tlplell: c:htl. a lua " 155;
1* ont'l coaplt •• nt of
padtt numller .,
I. chteklUlII calculated *1
1234
1235.
1136
1237.
1138 . • pya.f ()
1139 ,*t. ** *t *t ** *. *11. * ••• It 11 *1111.* It. J
*
to t. buffer HI
1240
/n copy plctet
1241.
' . . . . . 11 .. ***11 ...... 11 •• *** ...... ,
1242
1143. lnt 1,
1244.
1%45
1246.
1141.
124L
1149
1250
1251.
t.dltl [0] atJplct.hildi
tJdah [11 -tJpack.plct_ftUllj
hdl~a[2l atlpact,pack_cm.pl;
for (hOi i (128i 1+.)
tldata [1+31 • t_plck bufflr [tli
hdlta [1311 atlplck.cht.ai
I
231928-60
82510 XMODEM Implementation (Continued)
2·250
AP·401
MAIN PROGRAM
PAGE 24
lip.
82510 XMODEM
1252
1254
I""
1255.
, . . . . PROCEUDRE CHECK_WAlT
US?
1258
lZ'!19
, .. . .
/ .. ..
, .. ..
tUO
U6t
, .. ..
, .. ..
t f l . t ft • • • t . t t ••
t.t. t t t . t •• '11" t • • • • • t • • • • • • • • • t • • • • _ •• ***/
..... ,
• ...... I
us, , .. ..
c.h.e.ts
Tia, Out - TI T1al[ • 0
fI_ACK
- Act rlc.iud
u_NAI
- Nit ncthed
waiting - h Tiaer not .. pued
12'2. , .. ..
UU
1264
, . . ..
, .. ..
tUS
1266
, .. ..
1267
T. Tlatr. eer_to_Glt and
CJ.t_cu_req and return.'
..._...•• *'t,,
.....
..... ,
•• t.
. t t •• ,
**_**1
*...
*/
/
••••• J
I ••••••••••••••••••••••••••••••••••••• • •• • •• • •• • ........ •• */
(
1268
1269
if «ltI_ti.,_cnU "
'*
Cget_c.c.r_rq •• uthe»
1270
1271
1272
1273
U?4.
if t. Tiatt •• pired
and Itll1 wlitlng
for eontrol char.thtn
Ti •• out .,
ell'
/. Ct I-Char rC'fd thin
1275
12 76
1277.
1278
1279
1280
1281
1281
1283
tlturn statuI *1
twitch (eer_to_get)
(
CUI
ACI
btl.k,
1284
ease NAI
1285
buak
UU
1287
1288 .
1289
default:
/. c.orrupttd c:tl ehar .,
break,
1290
1291.
1292
1293
1294
1295.
)
else
it «tx_ti.l_cnt )0) "
return (WI. it in;),
(g.t_c.cf_rq •• aeth.t)
1296 .
1297
1298.
231928-61
82510 XMODEM Implementation (Continued)
2-251
Ap·401
IIp c
MAIN PRoeRAM
PAGE 15
82510 XHODEM
1300
Itt t . *. *. III III_ . t . t .t_ IIItttt. t_tttt tt _t t_t tt t . __ t t t . t _* __ * t** I
1301
1302
Itttt
1303
1304
,u**
1305
JUtIiI'
130t.
J
•••• */
tranIllUI51on, uintulilt
Trans.! t ter
•••• */
Flag'
/
/ * t t __ t'll'llt'llt _.'" .'IIttt'll t'llt_.ttt.tttttt'll t t t t *111111 tt ttttt'llt tt _ t I
Itttlil'
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1311
1318
1319
1320
1321
1321
1313
1324
1315
1324
1327
1328
1329
1330
1331
1332
eof .fal •• ,
tuflg III IDkpkt.
quit .. fllse,
key .. 0,
h_1 tit • • \1_1 die.
tJ_cad :: inaet nl,
I.nd_c.cr_rtq • lnact uei
tl_lndi
II
OJ
tl_req IIIlnactive,
eer_to_tl •
Q,
tI_byte_cnt .0;
pth_lent .. 0,
tI_t l.,_cnt .0,
gtt_ccf_rq .. 0,
C.Cf_tO_IJlt .0,
nt_bant (00),
outp «bpu1) ,0.27).
set_bant (001),
outp( (bpI.') • hOD),
h_state =tl_Jdlt.
pta.go ("trlnSlDltttr re.et"),
1334
Itt"tt"
1335
1336
/t***
133?,
1338
1339
..... ,
.....
• • • t It
Abort
1****
t'"
t
till "111'11
III
fttftt
"'IIIt 'III'III'II'II'II*lIIt *'11 _. _t __ 'II *t t t t _ IiItt
iii iii
t_ 'II _.* I
It***
*****1
,tt"
*tt*'" I
t_t_*,
cheeks n
tl8er. and returns the
folloW189 'Illue
SOH - SOH recth.d
EDT - EOT rece lVed
,u ..
Itt**
tt t_*1
**t
__ ,
*tt*tl
ttt_ t I
1340
/t**t
1341
Itt"
1342
1343
tt*tt I
I .. t t
wilting - WaltIng for n'tnt
**ttt/
/ tt . .
I 'II_tt t t t . t t tt t . t tttt._
*tt ***t** *t IIIt***t *** ••• t.*.t t t t t I
1344
1345
1346
1347
1348.
1349
1350
1351
1352.
1353
1354
1355
135'
1357.
time out - n
tUlU I.pu.d
*__
If «etl_rld_flg =:. active) "
(rl_tIIDe_cnt IsO»
(
etl_rld_flg "'lnaetue.
return ( rI_ct I_chr);
else
If ( rI_tl1u_cnt
111=
0)
el ••
return (waiting).
231928-62
82510 XMODEM Implementation (Continued)
2-252
AP-401
PACE 26
1358
1359
1360
1361
1362
1363
1364
1365
ftp e
HAIN PROCRAM
U510 IHODEM
chkpkt ;
pfintt ("fl'd plet •
"3u", radltatO]),
In_cars (13,40);
prntt ("tlpel ptt capl =
C"UdlhtO]»,
"T_carl (14,40),
printt ("ud ptt coapl •• ent • "'X", ndltltll);
."_curs <15,1);
pflntt ("rid chtsulD = "II". udat.at130]) ,
mY_CUfl (15,40),
printf (" •• pd chhua = "'X",pt_chhm),
.tnd_ccf_feq .actiVi.
ccr_to_h = NAKj
)
=
"'X*'.
231928-64
82510 XMODEM Implementation (Continued)
2·254
AP·401
PAGE II
"AiN .ROGUR
It P . c
nil 0
IRODER
IU' , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 . . . . . '
.. ,
1467. , .. PROCEDURE BUF_CrY
cophl pad:.t to II. bafhr
lUI.
Itu.
1t70
1471
1472
1t71
14,. .
Itn.
"".
"".
.....................................tI,,
,tt
,
bal_cn Ipukl_ldl
int '1ltt_Us
I
Inl
lftt
I.
lndl .0.
indl • CpleU_if .. !) 'Uli
1477. If Ilada I 111000 - lun "N. . . . rwrlt, ., ball .. "
1471 I
far ct-Oi 101li 1+ ••
1410.
u_'_lIaf tilldl.1l • riliul ttl i
lUI
1412 .
141 •.
....
In •.
231928-65
82510 XMODEM Implementation (Continued)
2-255
AP"401
PAGE
DEFINITiON FILE
flp def
Idef Ine
"liS I 0 rTP aOOO 6/30' 86."
Idef In. bPi hat 8
Id,fane gU_i.ddr
02
'defln, eSCI 27
ldef ine bel
07
6. Id,f Ine 1Is9_c 17
7
8. .def Ine
Idef Int h_c 35
10. Idef IDe t'_I
10
11. lde'ln. t'_1!
35
12 Id,fine [ 1 _ [
12
13 Ide( In. IO_C. 50
14. I.tt Inl 10_1
24
15 'd,f Ine f,l ..
16 Ulfin. t rUI
17. Id.flnt aet
I
18 Id.f In. inloct i we 0
19 Id'f In. etl_Cohr 2
20 Idef ine pH I
21
I h f 1ne .ot 55\5
Zl Id,f i fte • chk.s 5500
23 Ihf In. epkc.ap 5101
l4
'd,f lne told
5102
25 ldef In • • ptnua 5503
16
17
** •• ** •••••••••••••• /
28
/* . . h state defintlOu u */
"
2
3
4
5.
8Z510 XHODEH
11gn on .1.lige
BUI addre •• ' (
'(
('
ncapt chat
HOI
('
c::oordinlt . . of tho
• • • I&V e lin'
f
('
('
In
,/
*
·'9_[
('
c.oordinatu
*(
i,.
control char tran •• it '/
'tnd packet ' /
/' packet reclh,d ok ' (
/'
('
'* chechua .error */
/' packet e.o.pi incotflet ' (
/' old pad Dua tlclnld ' (
/, lnulid pacttt • re, •. ' /
,.** •••
2'. / •••••••••••••••••••••• ** •• ,
30
31
32
33
34.
35
36
37
31
fdlt Int tl_Ielle
'def IDe Wit t_NAK
ldef Ine TO_,t r_60
td,f int tI_t ely
Idefln, tJ_pack't
'dlfin. Wl1t_Cc
.dlf Ine t a_pit_colli))
Idef 1 ne to_err
000
001
OO!
003
004
005
006
007
0.02
111
112
113
II.
39 td.f Int tlen
40 Idef lnt atpkt
41. tdef Ine tlat;
n 14,f1n. uta
43 IdefIne w<in;
4'
4'S /"":.,,, •• t • • ** •••• *** •• **.*.*,
U
/-- n stlte definition " I
47, , •••••• 91 • • • • • • • • • • • • • • • • • • • ,
48
U. Idef In. fI_idl.
000
50. td,f In. U_fdr
001
51
Idef Inl rI_ptt
002
H
53
54
, •••••••••••••••••••••••••• I
55.
t i.,_out
90
"
td,f ine
51
td.f ine
fI_NAK
9!
58. td,f Inl
tl_left
91
S' tdef In.
r I_Vln
93
60.
/* Tranlmit paeht st>l .,
It u
state .ignal "lUll .,
231928-66
82510 XMODEM Implementation (Continued)
2-256
inter
PAGE
AP-401
DEFINITION FILE
Itp dol
81510 X"ODE"
61
61
, ••••• _ ••••••••••••••••••••••••• ,
'3,tt
'4.
65
,tt
Protocol Control
charictul
.... ,
u" I
/ ••••••••••••••••••••••••••••••• ,
"
61
!8
'd,f In. NAK
Id,l ta, ACK
'defin. SOH
71. Id., tn_ EDT
72 adel inl CAN
Id,t in. NUL
73
".
70
0a14
.""
0.04
0.01
"
"
0.04
0111
0.00
74.
....
I'
N'QltUI Act
Pulthl Act -/
Stlrt of Kllder
End of Tilt
"
"
' • • • • • fII • • • • • • • • • • • • • • • • • • • • • • • • • /
'**
lnturapt lourel
Idefln.
Idt! i1'll
Id,' in.
Ide! In'
'del i nl
,del inl
.del in,
.del ine
Idar i nt
tiaer
In
ee<
/
J ••••••••••••••••••••••••••••••• ,
fll
III
hien
tlldb
eeien
eetdb
tdlth. III ttnb
05
04
03
01
01
0112
0120
0.04
0.33
0.25
94
95 Iddine loi
96. 'dlfhe .pOO
91 Ideflnt ipOl
0.10
0.20
0121
1* end of
antarrupt fill
1* USfl port 0 *1
1* US9A port 1 *1
231928-67
82510 XMODEM Implementation (Continued)
2-257
inter
CRT 1/0 ROUTINES
PACE
e.
ell)
82510 IHODEH
haelud. "ftp deC"
CLR( )
/....
• ,....
1** **. *
Itt
*. *••• *. *•••
.t
t t •• t t
*t.
*. *. *.. t." ••• *••••
t ••••
, •• t.
/*.t.
C.lelrl
10
/
I
·*"*1
*t.t */
Icreen
*'***/
/* •• t
II
12
.....
.....
*•• ift *. **'
tt t
PROCEDURE eLR
*
/*.t
/ •••••••••••••••••••••••••••••••• ,1 • • • • • • • • • • • • • •
/
•• Ut,
**.* •••• ,'
13
14.
15 lnt eJcchr =- tSe.I,
16
17
18
19
patch (.sechr),
prlntf ("[2JOI),
20
Zl
22.
!3
14
15
Z6
17
18
Z9
30
31.
VOFF ()
, •••• ** •••• tt •• *._tt •• _•• t ••••• t . t tt ••••• _t.t.t t • • • • tt ••• ,
....
'* .t.
•• / ••• t
••••• /
/
/* t t t
*****/
Turns ReYlnt Video orr
/*
.....*',
**ttt,
I t . "'.
/*.* *
U. /*. t
.....
..... ,,
•• ***'
PROCEDURE VOFF
••• t.t
It tttt._ ••••• t ••• tttt._
*.*.
t . t . t ••••••••• t ••• t
33
34.
3S. lnt •• cchr • • Iei i
36.
31
38
H
patch (.techr),
print! ("[Om");
40
41.
H
43. RVON ()
44
/ ••••••• t
45
,....
46.
47
48
4•
50
51
51
53
54
55
56.
57.
58
59
, t •••
,. *. *
....
••••••••••
*** *t **t *. *••• *.*t **••••• *•••••••••••• I
• .... ,
..**.,
*
PROCEDURE RVON
,,./ ••**.t.
..........,
lit • • • ,
Reurs. Vid.o ON
I·'·
•
/ ••
..... ,
iIt • • • • /
/
1111 • • • • • • • • • • • • • • • • • 1111.11 • • • • • • • • • • • • • 11.11 • • • •
*••••• t •••• I
lnt .seehr • Uti,
patch (.seehr);
prlntf (IIt1."l,
AD
231928-68
82510 XMODEM Implementation (Continued)
2-258
intJ
AP-401
CRT 1/0 ROUTINES
PAGE
ColO
c
82510 IMODE)1
'1. OPEN_WIND (row, col, It g)
U. int
row.
n lnt
eol,
64. char
.t;C];
65 /1.. '111 • • • • • • • • • • • • • • • • • • • • • ** ••••• *•••••••••••••••••••••••• /
.. /....
" ....
,n.
,....
U
,....
70.
71
71
73.
74
..
PROCEDURE OPEN_WIND
""
..... ,
.. ... ,
/* •••
/
prints I string in rever •• "ideo
It the ginn location
•• U*/
'III . . . . ,
/ • • • '/II
• •••• I
,'/II '/II • •
•••• - J
,'III •• '/II '/II • • • • • • '/II,. *t.t •••••••• '/II _'III' fI • • • • • • t
• • • '111 • • • • • • • • • • • 'III • • '
7S.
76.
"V_CURS (row, co I) i
RVON (),
pnntf ("I"",lt9);
VOFF(),
17
71.
79
80
II.
IZ. )
83
14
85
"
87
BEEP ()
,.*.**
••••••••••••••••••••••• *•••••••••••••••••••••••••• *'
/*...
ttUt,
,....
/t...
PROCEDURE BEEP
18
89
90.
91.
,....
, . . "'*
,....
92
/ ••••••••••••
""'III/
".UI
produce.
I
bl.p
..... ,
** ... ,
/fI"'III
..... ,
.. ... ,
*•• '/1 • • • ,'* ••••••••••••••••••••••••••••••••••• ,
93
94.
95,
!6.
97
98
Int btlchr • bel,
pute.h (belchr),
99.
100.
101.
102.
103.
104
105.
106.
101
108
109
110
III
lIZ
CLL(row,col)
int row.
1nt e.ol.
, ...................................................... 'I •• ,
, ....
• *•• t /
/....
PROCEDURE CLL
..**./
tt ... ,
/tt . .
/U..
char lint at
JUti
....
J • •••
/
QUln
coordinate
•• *11"
••• **'
.. t " l
**.ttli
/ •••••••••••••••••••••••• *••••••••••••••••••••• *. **.* •••• I
113
114
tnt IIcchr • elCI,
MV_CURS (row, co!),
117
putch (Ise.chr)i
118.
prlnlf ("CK"),
119
1%0
115
116
231928-69
82510 XMODEM Implementation (Continued)
2-259
inter
AP-401
PAGE
CRT I/O ROUTINES
CI0
c:
82510 XHODEI'l
HI
122
123. CLMS()
1%4 1* *t ••• t t t t t t fltttt._
125
126
127
*
,....
,* •••
ft ••
..*....... ,,
*t I t t . t . t t . t •••••••••••••• ft • • • • • _. I
PROCEDURE CLMS
Itt __
.*'
.....
t. ,
•• t
118
JUU
129
13D
litU
Utu/
clear .'lllog. lID'
*•• I
**** •••••••••••••••••••••••••••••••••••••••• ** •••••• * I
1****
1****
131
132
, ••
.*.-*.,
133
134
136
137
138. pras9 ( •• 9)
139
140
141
c.har
asg [l,
/ •••••••••• *••••••••••••••• 111' • •
142.
/....
/t . . _
143
144
145
146
141
148
149
** •••••••••••••••••• *•••••• ,
lUlu
..... ,
•••• */
PRINTS MESSAGE AT IIESSAGE LINE
......* ••*',,
*1,*'"
.t ••
1****
/tt . .
, ....
1****
, ••••
*
*. *'
fl. ,
*••••• ft • • • • • • • • • • • • • • • • • • • ** •••••••••••••• *•••••••••
150
elms ();
prlntf (It
151
152.
".",
_5g),
153
154
ISS
CLLC ()
156
157
158
159
160
161
lnt escchr
162
MV_CURS (a,y)
163
1&4
165
166
161
168
;0
tlci,
puteh (neehr),
prlntf ("[K"),
/************ •• *** *t. t t . . . . . t.t._tt_ t t t tt. ***. tt. tilt
, ....
1**"
It .. .
, .. ..
/uu
/** ..
J
lDoves curior to specified
location
*****'f
••• tt
*t • • • • *t *t *t t t t *t _ ••• t *ttt._ ... *t __ tt t t t i t *t '*111 t t t t t t****.,
t **.. I
169
170
J
171.
172
173
int a,
Int ;
174
(
175
Int .seehr
176
177
178
179 .
._.t.t
*
_.*._/
••••• J
t •••• I
PROCEDURE MV_CURS
,
.
•• e I,
putch (licchr),
cprlntf ("Clllu.llluH",I,y);
231928-70
82510 XMODEM Implementation (Continued)
2-260
inter
Ap·401
PAGE
ASM 86 INTERRUPT INIT
Ihl .... 82SIO XMODEl'I
3
DCROUP GROUP
DATA
DATA
SEGMENT WORD PUBLIC 'DATA'
ASSUME OS DGROUP
DATA
ENDS
10
II
II
13
14
_PROG
SEGMENT BYTE PUBL I C 'PROG'
ASSUME CS _PROG
EITRN
PUBLIC
PUBLIC
IS
U
17
18
19
20
21
2Z
23
24
2S
26
27
2B
19
30
31
lnlt_lh
pUlh
pUlh
pUlh
push
aoo
pUlh
pop
aoo
aoo
INT
pop
pop
pop
pop
PROC
BP
AI
os
ox,
OFFSET IhSIO
CS
DS
,DOS yector IItup call
AH,2SH
H,OCH
,COK1 ,ector
,DOS _,sha call
IIH
OS
AX
01
BP
rlt
n
Iftlt_lh
ENDP
33
34
IhS 10
PROC
BP
AX
35
pUlh
36
palb
37
38
39
40
41
pUlh
pUlh
push
push
pUlh
pUlh
push
n
43
44
45
pop
48
49
SO
pop
pop
54
5S
56
57
58
Sf
60
call
pop
pop
pop
pop
pop
pop
net
IMIO
_PROG
end
for
ax
CI
DX
51
01
OS
ES
AX, DGROUP
OS, U
ur_SlO
IS
OS
01
51
01
CX
II
AI
BP
so,
110'
46
47
51
52
53
far
ox
ENDP
ENDS
231928-71
82510 XMODEM Implementation (Continued)
2-261
inter
APPLICATION
NOTE
AP-310
June 1987
High Performance
Driver for 82510
DAN GAVISH and TSVIKA KURTS
SYSTEM VALIDATION
Order Number: 292038·001
2·262
intJ
AP-310
1.0 OVERVIEW
The 82510 Asynchronous Serial Controller is a
CHMOS UART which provides high integration features to offioad the host CPU and to reduce the system
cost.
This Ap-Note presents a mechanism for reduction and
optimization of interrupt handling during asynchronous communication using the 82510. The mechanism
is valuable in applications where handling of interrupts
degrades system performance i.e., when high baud rate
is used, when mUltiple channels are handled or whenever real-time constraints exist: This implementation of
the mechanism is a software driver that transmits or
receives characters at 288000 bits per second.
The driver is based on the burst algorithm which uses
the 82510 features (FIFOs, Timers, Control Character
Recognition etc.) to reduce CPU overhead. CPU is significantly off-loaded for other tasks - about 75% of
the usual load is saved.
The driver can be easily modified to run in conjunction
with other 82510 features such as the MCS-51 9-bit
Protocol.
This document provides a full description of the driver.
The burst algorithm is presented in Section 3, the software module flow-charts and their descriptions are presented in Section 6, and the PL/M software listing is
given in Appendix A.
2.0 INTRODUCTION
2.1 CPU Load Consideration
The trend' towards multi-tasking systems, combined
with higher baud rates and increasing the number of
channels per CPU, has led to the need for decreasing
the CPU bandwidth consumed by the async communications for each byte transfer. Whenever the CPU is
interrupted, a certain amount of CPU time is lost in
implementing the context switch. This overhead can be
as high as hundreds of microseconds per interrupt, depending on the specific operating system parameters.
Thus, in high baud-rate or multi-channel environments,
where the interrupt frequency is very high, a substantial
portion of the CPU time is taken up by this interrupt
overhead. Therefore, systems usually require minimization of the number of interrupt events. In the case of an
asynchronous communication channel, reduction of the
number of interrupts can be achieved by servicing (i.e.,
transferring to/from the buffer) as many characters as
possible whenever the interrupt routine is activated.
This can be done by utilizing FIFOs to hold received or
transmitted characters, so that the CPU is interrupted
only after a certain number of characters have been
received or transmitted. Using a receive FIFO may
cause a potential problem: Due to the random rate of
character arrival in asynchronous communications,
there is a chance that characters will be "trapped" in
the Rx FIFO for extended periods of time. In order to
avoid such situations, a Rx FIFO time-out mechanism
can be implemented using the 82510 timer. The timeout indicates that a certain amount of time has elapsed
since the last read operation was performed. It causes
the CPU to check the Rx FIFO and read any characters that are present. This process, however, introduces
the additional overhead of the timer interrupt. This ApNote describes the use of the burst algorithm to avoid
the timer interrupt overhead while maintaining the use
of the Rx FIFO.
2.2 82510 Feat!Jres Vsed In This
Implemehtatlon
The following new 82510 features were used in this im'
plementation:
2.2_1 FIFOs
The 82510 is equipped with 2 four-byte FIFOs, one for
reception and one for transmission. While characters
are being received, a Rx FIFO interrupt is generated,
when the Rx FIFO occupancy increases above a programmable threshold. While characters are being transmitted, a Tx FIFO interrupt is generated, when the Tx
FIFO occupancy drops below a programmable threshold. The two thresholds are software programmable,
for maximum optimization to the system requirements.
2_2_2 TIMER
The 82510 is equipped with two on chip timers. Each
timer can be used as a baud rate generator or as a general purpose timer. When two independent baud rates
are required for transmit and receive, the two timers
can be used to generate both baud rates internally. Otherwise, one timer can be used for external purposes.
The timer is loaded with its initial value by a software
command and it counts down using system clock pulses. When it expires, a maskable interrupt is generated.
2-263
inter
Ap·310
3.0 THE BURST ALGORITHM
2.2.3 CONTROL CHARACTER RECOGNITION
Depending on the application, the software usually
checks the received characters to determine whether
certain control characters have been received, in which
case special ptocessing is performed. This loads the
CPU, as every received character should be compared
to a list of control characters. With the 82510, the CPU
is offioaded from this overhead. Every received character is checked by the 82510, and compared to either a
standard set of control characters (ASCII or EBCDIC)
or to special user defined control characters. The software does not need to check the received characters,
and a special interrupt is provided when a received control character is detected by the 82510. The specific
operation mode (standard set, user defined, etc.) is programmable.
2.2.4 INTERRUPT cONTROLLING MECHANISM
The twenty possible interrupt sources of the 82510 are
grouped into six blocks: Timer, Tx machine, Rx machine, Rx FIFO, Tx FIFO, or Modem. Interrupt
source blocks are prioritized. The interrupt management is performed by the 82510 hardware. The CPU is
interrupted by a single 82510 interrupt signal. The interrupt' handler is reported on the highest priority pending interrupt block (GIR) and on all the pending interrupt blocks (GSR), as well as on the specific interrupt
source. Interrupts are maskable at the block level and
source level. Interrupts can be automatically acknowledged (become not pending) when serviced by the software, or manually acknowledged by an explicit command.
3.1 Background
The 82510 FIFOs are used to reduce the CPU interrupt
load. When a burst of characters is transmitted or
received, the CPU is interrupted only once per transmission or receptioll of up to four characters. FIFO
thresholds are programmllblej. thus, when high system
interrupt latency is expected, an optin:mJ. threshold may
be selected for the desired trade-off between the CPU
load, lind the acceptable system interrupt latellcy. The
required Rx FIfO threshold is lllso a function of the
receive character rate. When the rate is high, a deep
FIFO is required. When the rate is very low (e.g., hundreds of milliseconds between characters), a low threshold is needed, to reduce the maximum character service
latency (a character is available to the application program only after it is stored in the receive buffer).
The software mechanism described here tunes the Rx
FIFO threshold dynamically when the incoming character rate is variable. The algorithm uses one of the
82510 on-chip timers for time mellsurement, in order to
automatically adapt the threshold to the character reception rate. This is done without loading the CPU
with the overhead of serving excessive interrupts generated by the timer mechanism itself.
3.2 Burst Algorithm Description
The 82510 timer is initialized to the time-out value with
every Rx FIFO interrupt. The time-out value. is ~e
maximum acceptable time between a character's reception and its storage in the receive buffer, but not less
than five character-times. Upon reception of the next
character, the timer status is examined to determine
whether the character rate is high (the timer has not yet
expired) or low (the timer has expired).
2-264
inter
AP-310
2nd character received. at LOW rate
2nd character received. at HIGH rate
receive characters at HIGH rate
292038-1
Figure 1. Burst Algorithm State Diagram
The algorithm is best describjld as a finite state machine
that can be in one of three modes: HUNTING mode,
SINGLE mode, or BURST mode. In HUNTING
mode, after the first character received interrupts the
CPU, the mode switches to SINGLE. On receiving a
character in SINGLE mode (that is the second character) the timer is examined; if the character rate is very
low, the mode is switched back to HUNTING. Otherwise, the rate is high enough to switch to BURST
mode. In BURST mode, the Rx FIFO threshold is
maximal. The machine' remains in BURST mode as
long as a burst of characters is being received. When
the rate of character reception becomes low, the timer
eventually expires generating a timer interrupt which
switches the mode back to HUNTING.
4.0 SOFTWARE' MODULE MAP
The driver contains the following software modules:
• MAIN
• BURST ALGORITHM
- Burst Algorithm Initialization (*)
- Rx FIFO Step (*)
- HUNTING mode
- SINGLE mode
- BURST mode
- Timer Step (0)
• INITIALIZATIONS
- Wait for Modem Status
• INTERRUPT HANDLER
- Rx FIFO Interrupt Service Routine
- Tx FIFO Interrupt Service Routine
- Status Interrupt Service Routine
- Timer Interrupt Service Routine
- Modem Interrupt Service Routine
Note that while a burst of characters is being received,
the CPU is interrupted only once per four received
characters. If the characters are received at a very low
rate, an interrupt occurs for eaph received character.
The CPl) is interrupted by the timer only once, when
the bllrst ,terminates. See Figure 1 for a state diagram.
For more details about the burst algorithm see paragraph 6.2.
(*) The burst algorithm modules are called by the ini-
tialization module and by the interrupt handler modules.
2-265
inter
Ap·310
IN1TIALIZATIONS
292038-2
Figure 2. Modules Block Diagram
5.0 HARDWARE VEHICLE
DESCRIPTION
6.0 SOFTWARE MODULE
DESCRIPTI,ONS
The driver was tested at 288000 baud, on an 80186
based system, with an 8 MHz local bus running with 2
wait-states, and an 18.432 MHz 82510 clock. Two stations were involved: one transmitter station and one
receiver station. Each station consisted of an
iSBC186/51 with a 82510 based SBX board connected
to it. See Appendix B for description- of the SBX board.
This driver is, nonetheless, suitable for running in a
large number of system environments.
6.1 MAIN
The MAIN module is a simple example of an application program that uses the driver.
The communication is done between two station's: One'
station is the transmitter and the other one is the reo
ceiver. After interrupts are enabled, the program waits
for the Finish_Tx flag or the FinisLRx flag-(for the
transmitter or receiver station, respectively) to be set.
In the tran~mitter station, the driver is preloaded with
the transmit data. In the receiver station, the received
data is displayed after data reception is complete.
2-266
inter
Ap·310
292038-3
Figure 3. MAIN
6.2 The Burst Algorithm Modules
6.2.1 INITIALIZE THE BURST ALGORITHM
This module is called by the initialization module.
The global variable Burst_algo is used to indicate the
current burst algorithm mode.
The burst algorithm is most useful at a baud rate of
9600 or higher. At lower baud rates, where the Rx in·
terrupt rate is very low, the burst algorithm is degenerated (Low_baud is assigned to Burst_algo). At a
baud rate of 9600 or more, the burst algorithm mechanism is initialized and starts by disabling the timer interrupt.
The initial state of the burst algorithm is HUNTING
mode. In this mode, it is looking for (hunting) the first
character. The Rx FIFO threshold is zero, thus the first
character received interrupts CPU. This interrupt starts
the burst algorithm mechanism.
2-267
BURST_algo = Low Baud
292038-4
Figure 4. Initialize The Burst Algorithm
inter
AP-310
6.2.2 BURST ALGORITHM MECHANISM
6.2.2.2 SINGLE Mode
Modules HUNTING, SINGLE, BURST are called by
Rx FIFO interrupt service routine. Module
BURST&TIMER is called by timer interrupt service
routine.
When the second character is received, the burst algorithm is in SINGLE mode. Timer status is read
(TMST). If the status indicates that the timer has expired, the receive character rate is low and there is no
need to increase the Rx FIFO threshold. The burst algorithm returns to its first state, i.e., HUNTING mode.
However, if the timer has not expired, the receive character rate is high, and the Rx FIFO threshold is set to
the maximal allowable value. The timer is restarted and
the timer interrupt is enabled so that, if it expires before
the Rx FIFO exceeds the threshold, a timer interrupt
will occur.
6.2.2.1 HUNTING Mode
Hunting for the first character received is the first step
in the burst algorithm. After the first character is de·
tected, received and handled, it must be determined if
reception will be at high or low rate. This is done by
starting the timer. HUNTING mode ends by assigning
the second step, i.e., SINGLE mode, to Burst_algo.
SINGLE mode is ended by assigning the third step,
BURST mode, to BURST__algo.
SINGLE mode
BURSLolgo
BURST mode
=HUNTING
292038-5
Figure 5. The Burst Algorithm
2-268
inter
AP-310
6.2.2.3 BURST Mode
The algorithm enters BURST mode as soon as the receive character rate is evaluated as high, i.e., when two
successive characters are received without a timer expiration. The FIFO is now working at full threshold and
the timer is used as a timeout watch dog. BURST mode
is the most time-critical path of the algorithm. Therefore, it consumes a minimum amount of real time.
The timer is restarted, in order to restart a new timeout
measurement. The timer status is read to trigger automatic reset of the previous status; this is done to avoid
the timer interrupt if the timer has expired during the
Rx FIFO interrupt service routine execution.
If the character reception rate becomes low, then the
time between two successive Rx FIFO interrupts increases. Hence, a reduction in the reception rate causes
the timeout to expire, and a timer interrupt occurs.
This drives the algorithm back to HUNTING mode.
The timer interrupt is disabled and the Rx FIFO
threshold is configured to zero, to issue an Rx interrupt
on the first hunted character.
Figure 6. Timer Interrupt and BURST Algorithm
Table 1. BURST Algorithm Modes
Timer
Timer-Interrupt
Hunting
0
Idle
Disabled
Single
0
Started
Disabled
Burst
Max.
Restarted
Enabled
SINGLE mode has a slightly longer path. However,
under a high reception rate, the algorithm passes SINGLE mode once only and then stays in BURST mode
until the end of the burst. Under a low reception rate
the algorithm passes SINGLE mode many times, but,
since the period between two successive Rx interrupts is
long, this hardly affects system performance.
This module initializes the driver. It is called at program start-up.
The 82510 is configured for the specific operation mode
by the CONFIG_82510 submodule: A Software Reset
command is issued, and then the character configuration is selected. In the receiver station ACRO and
ACRI Registers are loaded with the End-Of-File
ASCII character, so that the Control Character Recognition feature of the 82510 can be used to detect the
specific file terminator. In the transmitter station, the
ASCII characters XOFF and XON are loaded to
ACRO and ACR1, respectively, to detect transmit-off!
on requests automatically. The use of the control character recognition feature of the 82510 reduces system
overhead, as the software does not need to check every
received character. A special interrupt is received when
the 82510 hardware detects a received control character.
Interrupt sources are enabled (note that a Tx interrupt
will occur immediately). BRGA is loaded to generate
the required baud rate (288000 baud in this specific
implementation). Rx FIFO depth is set to 4. The Tx
and Rx FIFO thresholds are initialized to O. BRGB is
selected to function as a timer, and is loaded with the
timeout value (7 ms at 18.432 MHz, in this implementation). The RxC and TxC sources are selected to be
BRGA.
292038-6
FIFO
Threshold
BURST mode is assigned the fastest path because it is
the most real time sensitive mode.
6.3 Initializations
6.2.2.4 Timer Interrupt and Bust Algorithm
Mode
avoid an overrun error). The module was designed to
minimize the CPU overhead inherent in the burst algorithm itself.
The burst algorithm parameters are initialized by
INIT_BURST. WAIT_FOR_MODEM_STATUS
is called and implements a wait until the modem handshake DSR signal is set. If WAIT_FOR_MODEM_
STATUS returns with a timeout error, the modem error is processed. If no error has occurred, the following
parameters are initialized: FinisLRx and Finish_Tx
flags, receive and transmit buffer pointers, and the receiver flag. All status registers are cleared by issuing a
STATUS CLEAR command to the ICM register.
6.2.3 FLOWCHART DESCRIPTION
The Rx FIFO interrupt handler executes the burst algorithm immediately after the Rx FIFO is emptied (to
2-269
inter
AP·310
292038-7
Figure 7.lnitlaUzations
2-270
AP-310
GER = Enbl Intr
Rx, Stat, Wodem
=
, GER Enbl IntI"
Rx, Stat, Wodem
292038-8
Figure 8, 82510 Configurations
2-271
inter
AP-310
This module waits, with a timeout, for the DSR modem .
handshake signal to be set. DSR should be active before'
_any communication starts (it indicates that the modem
is. active). The returned Mod~Handshake flag indio
cates normal return (true) or timeout error return
(false).
292038-9
Figure 9. WalLFor_Modem_Status
2·272
AP·310
6.4 Interrupt Handler.
6.4.1 INTERRUPT HANDLER STRUCTURE
The interrupt handler services the ,82510 interrupt
sources. Since this is a titne-critical path, the code is
optimized to minimize real time consumption.
The interrupt handler identifies the highest priority
pending 82510 interrupt, by reading GIR. The interrupt handler was designed so that shorter paths are
assigned to more real time sensitive interrupt sources.
Rx FIFO interrupt is the most sensitive, Tx FIFO is
the second most sensitive, and so on.
The interrupt handler services only one interrupt
source at a time. This prevents CPU resource starvation from other interrupt driven devices. Interrupts are
enabled at the beginning of the interrupt handler, so
that higher priority interrupt sources are not disabled
by the 82510 interrupt handler.
The programmable interrupt controller (8259A) is assumed to be configured to "edge triggering mode" and
':non-automatic end of the interrupt" mode.
292038-10
Figure 10. Interrupt Handler
2-273
intJ
6.4.2 RxFIFO INTERRUPT SERVICE 'ROUTINE
The Rx FIFO interrupt service routine (IISt.empties the
Rx FIFO. The receive data register (RXD) is reild, as
many times as indicated by the, FIFO occupancy register (FLR),.and the characters are stored in RxJuf.
graph 6.2.2). Before leavjng the Rx FIFO interrupt
service routine, the FIFO occupancy re8ister is rechecked, to empty the Rx·FIFO pf Qharac~ that may
have been received,durlng the Rx FIFO interrupt service routine itself. This can happen if the Rx FIFO interrupt service routine has been interrupted by a higher
priority interrupt.
After emptying the Rx FIFO, the Rx FIFO interrupt
service routine executes the burst algorithm (see para-
292038-11
Figure 11. Rx FIFO Interrupt.Servlce Routine
2·274
inter
Ap·310
6.4.3 Tx FIFO INTERRUPT SERVICE ROUTINE
6.4.4 STATUS INTERRUPT SERVICE ROUTINE
The Tx FIFO interrupt service routine fills the Tx
FIFO with transmit characters while checking for the
End-Of-File terminator. According to the FIFO occupancy register (FLR), the Tx FIFO is loaded (by writing to TXD) until it is full or until the End-Of-File
character is detected. The transmitted characters are
taken from Tx_Buf. If an End-Of-File character is
identified, then the transmission is immediately ended
by disabling all 82510 interrupts and setting the Finish_Tx flag.
The status interrupt service routine has four objectives:
- To empty the Rx FIFO.
- To stop reception if an End-Of-File character is
identified by the control character recognition
mechanism (in the receiver station).
- To disable or enable the Tx interrupt ifaXOFF or
XON character, respectively, is identified by the
control character recognition mechanism (in the
transmitter station).
- To handle parity, framing, or overrun errors (in the
receiver station).
(Txflfo Full)
No
t=t+ 1
292038-12
Figure 12. Tx FIFO Intr Service Routine
2-275
inter
AP·310
First the Rx FIFO is emptied. In the receiver station,
the RST register is checked to determine whether an
End-Of-File terminator has been identified by the
82510, in which case reception is stopped immediately
by disabling all interrupt sources and setting the
Finish_Rx flag. In the transmitter station, the received
characters are checked to identify the received control
character. If XOFF is identified, Tx interrupt is disabled. If XON is identified, Tx interrupt is enabled.
Note that the software does not need to check for any
control character during normal reception; the control
characters are identified by the 82510 device.
RST is checked for parity, framing or overrUn errors. If
one of these errors has occurred, then the error handling routine is executed.
If status interrupt occurs while Burst_algo is assigned
to BURST mode, the timer is restarted.
Note that status interrupt is enabled at both stations.
Transmit
station
292038-13
Figure 13. Status Intr. Service Routine
2-276
inIJ
AP·310
6.4.5 TIMER INTERRUPT SERVICE ROUTINE
6.4.6 MODEM INTERRUPT SERVICE ROUTINE
A timer interrupt occurs when the receive character
rate becomes low. The timer interrupt service routine
first empties the Rx FIFO and then switches the burst
algorithm to HUNTING mode.
Modem interrupt occurs if one of the modem lines has
dropped during transmission or reception. The modem
mterrupt service routine reads the MSR register to ac·
knowledge the modem interrupt. The modem error
routine is then executed.
292038-14
292038-15
Figure 14. TIMER Intr Service Routine
Figure 15. MODEM Intr Service Routine
2·277
inter
AP-310
APPENDIX A
PL/M SOURCE FILE
I·····················································
....................•
•
.82 S 1 0 - H I G H PERFORMANCE
Driver
*
•• This driver is optimized for Real Time Systems. It supports
*
•
• high syst_ performance. It is based on the "BURST algorithm"
•
**** •• ** •• *** •• *•••• **** ••• *.***** •• ******.* •••• *•••••••••• ***.* •••••• *•• /
HIGHPERFORMANCE: DO
i
1·****·**·*·***··*·*·**··*·*·***·*·***·*··**·*··*··*** •••• *** •••• *••••••••
•
LITERALS
•
•• ***.**.**.***.**.*** •••• *.** •• **** •• *•• ***.*.* ••• *** ••• *•••• *.* ••••• *.*/
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
'DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
-DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
LIT
TRUE
FALSE
BAUD 9600
BAUD-19200
BAUD-288000
DLAB-O
DLAB-1
CR LF
X Off
X-On
End Of File
BASE sIo
NASOWORK1
GEN2
MODM3
TXD
RXD
BAL
BAH
GER
GIR
BANK
LCR
MCR
LSR
MSR
ACRO
RXF
TXF
TMST
THCR
FLR
RST
RCM
TCM
GSR
ICM
FMD
THO
LITERALLY 'LITERALLY'i
LIT 'OFFH'
LIT 'OOH'
LIT '003CH'
il.
LIT 'OOlEH'
LIT '0002H'
i
LIT 'Ollll.l.l.l.B'
il·
LIT 'l.OOOOOOOB'
il·
LIT 'ODH'
il·
LIT 'OAH'
LIT 'l.3H'
LIT 'l.l.H'
LIT 'J.AH'
i
LIT '080H'
i/*
LIT 'OOOOOOOOB'
LIT 'OOl.OOOOOB'
LIT '01000000B'
LIT '01100000B'
LIT 'BASE S10 + 0' il.
LIT 'BASE-Sl.O + 0'
LIT 'BASE-Sl.O + 0'
LIT 'BASE-Sl.O + 2'
LIT 'BASE-Sl.O + 2'
LIT 'BASE-Sl.O + 4'
LIT 'BASE-Sl.O + 4'
LIT 'BASE-S10 + 6'
LIT 'BASE-Sl.O + 8'
LIT 'BASE-Sl.O +l.O'
LIT 'BASE-S10 +12'
LIT 'BASE-S10 +l.4'
LIT 'BASE-S10 + 2' il.
LIT 'BASE-S10 + 2'
LIT 'BASE-S10 + 6'
LIT 'BASE-S10 + 6'
LIT 'BASE-Sl.O + 8'
LIT 'BASE-S10 +l.O'
LIT 'BASE-Sl.O +10'
LIT 'BASE-Sl.O +l.2'
LIT 'BASE-S10 +14'
LIT 'BASE-Sl.O +l.4'
LIT 'BASE-Sl.O + 2' il.
LIT 'BASE=Sl.O + 6'
2-278
Character configurations
*/
Reset DLAB
Set
DLAB
Control characters
*/
*/
*/
8 2 S l. 0
registers
*/
BANK 0 - NAS
*/
BANK l. - WORK
*/
BANK 2 - GENERAL CONFIGURE */
292038-16
intJ
Ap·310
DECLARE IMD
LIT 'BASE S10 + 8'
DECLARE ACRl
LIT 'BASE-Sl0 +10'
DECLARE RIE
LIT 'BASE-Sl0 +12'
DECLARE RMD
LIT 'BASE-Sl0 +14' ,
DECLARE CLCF
LIT 'BASE-Sl0 + 0' 1/* BANK 3 - MODEM
DECLARE BBL
LIT 'BASE-Sl0 + 0' 1/* DLAB=l
DECLARE BACF
LIT 'BASE-Sl0 + 2'
DECLARE BBH
LIT' 'BASE-Sl0 + 2'
DECLARE BBCF
LIT 'BASE-Sl0 + 6'
DECLARE PMD
LIT 'BASE-Sl0 + S'
DECLARE MIE
LIT 'BASE-Sl0 +10'
DECLARE TMIE
LIT 'BASE-Sl0 +12' ,
DECLARE OUT2 MCR
LIT '00001000B'
1/* Specific register bits
DECLARE DTR MCR
LIT 'OOOOOOOlB'
DECLARE DSR-MSR
LIT '00100000B'
DECLARE CLRSTAT ICM
LIT '00000100B'
DECLARE INTR S10
LIT '21H'
DECLARE PORT-S0130M
LIT 'OE2H'
DECLARE EN 80130
LIT 'OFDH'
,
DECLARE PORT EOI
LIT 'OEOH'
DECLARE COMM-EOI
LIT '61H'
;1* End Of Interrupt command
DECLARE ENRTX GER
LIT 'OOOOllllB'
;1* Enable Interrupt bits
DECLARE ENTX GER
LIT '00000010B'
DECLARE ENTXSTAT GER LIT 'OOOOll10B'
DECLARE ENRX GERLIT 'OOOOl101B'
DECLARE ENTIMRx GER
LIT '00101101B'
DECLARE DISTX GER
LIT '00001101B'
;
DECLARE DISRX-GER
LIT '00000010B'
1/* Disable Interrupt bits
,
DECLARE DISRTX GER
LIT 'OOOOOOOOB'
DECLARE TXTHRESHO FMD LIT 'OOOOOOOOB'
1/* FIFO threshold
DECLARE RXTHRESHO-FMD LIT 'OOOOOOOOB'
DECLARE RXTHRESH3-FMD LIT 'OOl10000B'
,
DECLARE MASK RXOCC
LIT 'Oll10000B'
;1* Mask on occupancy bits
DECLARE MASK-TXOCC
LIT 'OOOOOlllB'
,
DECLARE MASK-ACRSTAT LIT '01000000B'
;1* Mask on ACR status bits
DECLARE CHRLEN S L I T '00000011B'
11* Async parameters
DECLARE STPBIT-l
LIT 'OOOOOOOOB'
DECLARE PARITY-NON
LIT 'OOOOOOOOB'
DECLARE SWRES CMND
LIT '00010000B'
DECLARE ERRCHR" RST'
LIT 'OOOOll10B'
DEOLARE ACRSTAT RIE
LIT .'01000000B'
,
DECLARE ACRSTAT~RST
LIT '01000000B'
DECLARE NONI GIR
LIT '00100001B'
1/* Interrupt vector
DECLARE MODMI GIR
LIT '00100000B'
DECLARE
TXI-GIR
LIT '00100010B'
DECLARE
RXI-GIR,
LIT' 00100100B'
DECLARE STATI-GIR
LIT '00100110B'
DECLARE TIMI-GIR
LIT '00101010B'
DECLARE AUTOACK IMD
LIT '00001000B'
I
DECLARE TIMOD' BeCF
LIT 'OOOOOOOOB'
1/* Timer
DECLARE TIMBI-TMIE
LIT 'OOOOOOlOB'
;
DECLARE FIFO IMD
LIT 'OOOOOOOOB'
DECLARE STARTIMB TMCR LIT '00100010B'
DECLARE STARTIMB-TMST LIT 'OOOOOOlOB'
DECLARE RTXCLK BRGA CLeF LIT '01010000B' ,
DECLARE LOW BAUD
- LIT 'OOH'
1/* BURST algorithm
DECLARE HUNTING MODE LIT 'OlH'
DECLARE SINGLE-MODE LIT '02H'
,
DECLARE
BURST-MODE LIT '03H'
DECLARE TIME EXP
LIT 'OFFFFH'
1/* timeout=7mS (at 18.4 Mhz)
DECLARE WAIT=TIME
LIT 'OOFFFH'
1/* WAIT_FOR_MODEM_STATUS
*1
*1
*1
*1
*1
*1
*1
*/
*/
*1
*/
*/
*1
*1
*1
*1
292038-17
2-279
inter
AP·310
1***************************************************** ****************~***
*
*
VARIABLES
****************************************************** *****************~*/
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
TX_PTR PQINTER PUBLIC
TX BUF BASED TX PTR (3000) BYTE ;
IX-TX
WORD PUBLIC ;
RX-BUF(3000) BYTE PUBLIC;
IX-RX
WORD PUBLIC
INTR VEC
BYTE PUBLIC
FIN TX
BYTE 'PUBLIC
FIN-RX
BYTE PUBLIC
RX CRR
BYTE PUBLIC
TX-CHR
BYTE PUBLIC
TX-OCC
BYTE PUBLIC
RX-OCC
BYTE PUBLIC
STAT
BYTE PUBLIC
BAUD
WORD PUBLIC
TEMP
BYTE PUBLIC
FIN
BYTE PUBLIC
~~g~ ~~i~~N
~~~~ ~g:tig
DECLARE BURST ALGO BYTE PUBLIC ;
DECLARE MODEM-HANDSHAKE BYTE PUBLIC
V~CLARE COUNTER
WORD PUBLIC
DECLARE RX_ERROR
BYTE PUBLIC ;
1* Transmit buffer
*1
1* Receive buffer
*1
1* Finish Transmission flag
1* Finish Reception
flag
*1
*1
1* Receive station
1* BURST algorithm
*1
*1
1* Error occurred during
1* reception
*1
*1
1*------------------------------------------------------_-------_________ *1
1* 1/0 console utilities
*1
$INCLUDE (: F.1: TIOHP. PEX)
1* Setup and H/W configurations
*1
$INCLUDE (:F1:HPUTIL.PEX)
DECLARE MAIN LABEL PUBLIC ;
/****************************.**********************~********************~
* Procedure INITIALIZATIONS
*
*************************************************************************
* input:
none
*
* output:
none
*
* function:
driver initialization: parameters, 82510
*
*
configuration, modem status .check.
*
* called by: Main
*
* calling:
CONFIG_82510, INITIALIZE_BURST, WAIT_FOR_MODEM
*
**
*
*
*
**
Init the Interrupt mechanism by enable Interrupt in GER register
At the Receive station: Enable Rx FIFO, Status and Modem Interrupts
Disable Timer Interrupt
At the Transmit station: Enable Tx FIFO, Status and Modem Interrupts
flowchart:
figure 7
description:
paragraph 6.3
**
*
*
*
**
****************************************************** *******************1
INITIALIZATIONS: PROCEDURE PUBLIC
DISABLE; ,
CALL SET$INTERRUPT(INTR S10,INTR HANDLER)
.'
1* Install THE INTR HANDLER
TX CHR=OO
RX:::-CRR=OO
*1
*1
292038-18
2·280
inter
Ap·310
1*
1*
1*
1*
CALL TEXT ;
IX TX- OFFFFH
IX-RX- OFFFFH
FlitTX-FALSE ;
FIN RX-l"ALSE ;
RX_BUF(O)-O ;
RX_ERROR"'l"ALSE
1*
1*
1*
1*
1*
1*
BAUD-BAUD_288 000
CALL CONFIG_82510
TX PTR is a pointer to the transmitted*/
data
*/
The index buffer are assiqned to -1
*/
Init Finish Transmit and receive flaqs*1
Reset the flaq
*/
The Async communication Baud rate is
the 82510-full scale 288000
*/
*/
Confiqured the 82510:
*/
S/W reset, character lenqth, parity, */
stop bit, baud rate and fifo threshol */
1***************************************************** ********************
*
INITIALIZE BURST
*
***********-*************************************************************
* input:
none
*
* output:
Burst Alqo
*
start-Burst alqorithm in Huntinq mode
*
* function:
* called by: INITIALIZATIONS
*
none
*
* callinq:
*
*
* flowchart: fiqure 4
description: paragraph 6.2.1
*
*************************************************************************/
ELSE
THEN BURST ALGO-HUNTING MODE ;
1* HUNTING mode: 1* Rx FIFO threshold is 0
1* Timer interrupt is disable
BURST_ALGO-LOW_BAUD
*/
*/
*/
CALL WAIT FOR MODEM STATUS ;
-
TEMP
TEMP
TEMP
TEMP
-
-
INPUT (RXD)
INPUT (RXD)
INPUT (RXD)
INPUT (RST)
1*
1*
Wait for Modem handshake line "DSR"
if ACTIVE set
MODEM_HANDSHAKE
*/
*/
END INITIALIZATIONS ;
1***************************************************** ********************
* Procedure
CONFIG 82510
*
*************************************************************************
* input:
none
*
none
*
* output:
function:
confiqure
the
82510
to
a
specific
operation
*
*
*
mode
*
*
* called by: INITIALIZATIONS
none
*
* calling:
*
*
* flowchart: fiqure 8
description: paragraph 6.3
*
*************************************************************************/
CONFIG_82510: PROCEDURE PUBLIC
1*
Perform Software reset
OUTPUT (BANK) .. WORK1;
OUTPUT (ICM) = SWRES_CMND,;
1* Move to work bank
1* S/W reset command
*/
*/
*/
292038-19
2·281
inter
/* BANK
Ap·310
ZERO -,
NAS
(The default BANK)
*/
/* configured the character by writing to LCR:
*/
/* 1 stop bit, 8 bit lengh, non parity
*/
OUTPUT (LCR)-(STPBIT_1 + CHRLEN_8 + PARITY_NON)
OUTPUT(MCR)"(DTR_MCR OR OOT2_MCR) ;
/* Required only in IBM PC environment: */
/* set OUT2 signal to control an external*/
/* 3-state buffer that drives the 82510 */
/* interrupt signal
*/
IF RECEIVER THEN OUTPUT(ACRO)=End Of File ;
/* At the Receive station EOF is
/* recognized to terminate reception
ELSE OUTPUT(ACRO)- X_OFF
/* At the Transmit station "X Off" is
/* recognized to stop transmission
/* t8lllporary
*/
*/
*/
*/
*/
/* Enable 82510 Interrupt by set GER,
/* done at the end of INITIALIZATIONS
*/
*/
/* Init the 82510 Interrupt mechanism
DISABLE ;
IF RECEIVER THEN OUTPUT(GER)=ENRX GER ;
/* a~ the Receive station
ELSE OOTPUT(GER)=ENTXSTAT_GER
/* and the Transmit station
*/
*/
*/
/* Configured baud rate to 288000
/* by writing to BRG A (BAL and BAH)
OUTPUT(LCR)=INPUT(LCR) OR DLAB 1; /*set' DLAB to allow access to BRG
OUTPUT(BAL)-LOW (BAOD 288000) I
'
OUTPUT (BAH)-HIGH (BAOD-288000) ;
OOTPUT(LCR)-INPUT(LCR) AND DLAB_O; /* reset DLAB
*/
*/
*/
/* BANK TWO - General configuration
OUTPUT (BANK) =GEN2 ';
*/
*/
OOTPUT(IMD)=(AOTOACK IMD OR FIFO IMD) ;
7* Automatic interrupt acknowledge,
/* Rxfifo depth is four bytes
*/
*/
OUTPUT(FMD)=(TXTHRESHO FMD OR RXTHRESHO FMD) ;
/* Rxfifo threshold is temporally zero
/* for HUNTING mode (BURST algorithm)
/* Txfifo threshold is zero for max
/* interrupt latency ,
*/
*/
*/
*/
IF RECEIVER THEN
OnTPUT(ACR1)=~nd_Of_File
ELSE OUTPUT(ACR1)=X_ON ;
OUTPUT (RIE)
=
;
At the Receive station EOF is
recognized, the same as ACRO
At the Transmit statibn "X On'" is
recognized to continue transmission
/*
/*
/*
/*
*/
*/
*/
*/
(ACRSTAT_RIE OR INPUT(RIE»
;
/* Enable interrupt on programmed control*/
/* character received (ACRO/ACR1)
*/
/* BANK THREE - MODEM configuration
OUTPUT(BANK)'"MODM3 ;
OOTPUT(BBCF)-(TIMOD_BBCF)
/*
OOTPUT(BANK) '" NASO;
/*
OOTPUT(LCR)=INPUT(LCR) OR DLAB_1 ;
OUTPUT (BANK) .. MODM3;
/*
OOTPUT(BBL) = LOW (TIME_EXP);
/*
*/ ,
BRG B configured to TlMER,mode
*/
Move t'o nas bank to set" DLAB
*/
/* Set DLAB to allow access to BRG
*/
MODEM bank
*/
Set max timeout (7ms if 18Khz crystal)*/
292038-20
2-282
inter
AP-310
OUTPUT (BBH) - HIGH(TlME EXP);
/*
OUTPUT (BANK) ~ NASO;
/*
OUTPUT(LCR) -INPUT(LCR) AND DLAB 0
OUTPUT (BANK) - MODMJ;
7*
OUTPUT(CLCF)-RTXCLK BRGA CLCF
/*
/*
OUTPUT(TMIE)=TIMBI_TMIE
/* Enable Timer block interrupt
/* (stil disabled in Timer bit in GER)
/* BANK ONE - general WORK
OUTPUT(BANK)-WORK1 ;
OUTPUT(ICM)-CLRSTAT_ICM
/* Remain in
to issue interrupt when time has
expired. Move to NAS bank again
; /* Reset DLAB
switch to BANK THREE - MODEM
The reoeive and transmit olook source
is BRG A
- The RUNTIME
b~nk
/* Issues a oommand to olear all
/* status registers
W 0 R K - THE runtime
bank
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
END CONFIG_82510 ;
/ ••• *********.*** •• **.**.*** ••••••• ***.*** •••• ** •• ************************
* Prooedure WAIT FOR MODEM STATUS
*
.*.**********************************************************************
* input:
none
*
* output:
Modem Handshake
*
*
* funotion: waits-with a timeout for DSR aotive,
returns status flag
*
*
* called by: INITIALIZATIONS
*
* oalling:
none
*
*
**
* flowohart: figure 9
desoription: paragraph 6.3.1
******.**************.****** ••• ******.***********************************/
WAIT_FOR_MODEM_STATUS: PROCEDURE PUBLIC ;
MODEM HANDSHAKE - FALSE ;
COUNTER - WAIT_TIME ;
00 WHILE (NOT MODEM HANDSHAKE) AND «COUNTER:=COUNTER-1) > 0 ) ;
IF (INPUT (MSR) AND DSR MSR) <> 0
THEN MODEM_HANDSHAKE
TRUE
END
-
/*************************************************************************
* Procedure INTERRUPT HANDLER
*
****************** •• *****************************************************
* input:
Tx Buffer
*
Rx Buffer, Finish_Tx, Finish_Rx
*
* output:
* function:
service all 82510 interrupt souroes:
*
*
Rx Fifo, Tx Fifo, Status, Timer, Modem
*
* called by: 82510 hardware i n t e r r u p t '
*
* calling:
Rx_Fifo_Intr, Tx_Fifo_Intr, Status_Intr,
*
*
Timer_Intr, Modem_Intr
*
*
**
* flowchart: figure 10 desoription: paragraph 6.4, 6.4.1
*************************************************************************/
INTR_HANDLER: PROCEDURE INTERRUPT INTR_510 REENTRANT PUBLIC
ENABLE
/* Enable Interrupts of
/* HIGHIER priority devices
*/
*/
INTR_VEC=INPUT(GIR) ;
/* Get the 82510-highest priority
/* pending interrupt
*/
*/
292038-21
2·283
intJ
AP-310
/**.***********************************************************************
*
Rx FIFO INTR
*
*************************************************************************
* input:
none
*
* output:
Rx Buffer, Burst Algo
*
* function: service Rx Fifo Interrupt
*
*
receive characters; store in receive buffer
*
* called by: INTERRUPT HANDLER
*
* calling:
BURST_ALGO
*
** flowchart: figure 11
description: paragra~h 6.4.2
**
*********** ••• ***********************************************************/
IF INTR_VECzRXI_GIR THEN 00 ;
1*
1*
1*
1*
1*
1*
RX_OCC=INPUT(FLR) ;
Rx fifo level occupancy
Shift the Rx occupancy bit
RX_OCC=SHRCRX_OCC,4)
to get it's real value
- OPTIMIZE code Empty the Rx FIFO and store the
received character in RX BUF
RX_BUF (IX_RX: =IX_RX+1) =INPUT CRXD) ;
1* Read the first character immediatly
1* to save Real Time
00 WHILE (RX_OCC:=RX_OCC-1) > 0 ;
RX_BUF(IX_RX:=IX_RX+1)=INPUT(RXD)
END ;
*1
*1
*1
*1
*1
*1
*1
*1
1***************************************************** ********************
BURST ALGORITHM
*
*************************************************************************
* input:
Burst_Algo
*
Burst Algo
*
* output:
* function: execute a step in the burst algorithm
*
*
after characters are received
*
*
* called by: Rx_FIFO_INTR
* calling:
none
*
*
** flowchart: figure
5
description: par. 6.2.2.1 to 6.2.2.3
**
****************************************************** *******************1
1*---------------------------------------------------- -------------*
* BUR 5 T
MOD E - step 3 (full fifo threshold)
*
*
*
*
Reset the Timer status
* Restart the Timer
*-----------------------------------------------------------------*1
IF BURST ALGO = BURST MODE THEN 00 ;
TEMP ~ INPUT(TMST):
OUTPUT (TMCR) =STARTIMB TMCR;
END;
-
1*------------------------------------------_·_---------------------*
*
*
*
HUN TIN G MOO E - step
Operate the TIMER
Change to step 2 SINGLE mode
1
*
*
*
*-----------------------------------------------------------------*1
ELSE IF BURST ALGO = HUNTING MODE THEN 00 ;
OUTPUT(TMCR)=STARTIMB TMCR
BURST ALGO=SINGLE MODE
END;
-
292038-22
2·284
inter
AP-310
/*-----------------------------------------------------------------*
* SIN G L E
MOD E - step 2
*
* If TIME has expired, means the receive
* rate is LOW, return to HUNTING mode
* If TIME did NOT expire, means the
* Receive rate is HIGH, set Rx FIFO threshold, Restart the
* Timer and switch to BURST mode
*
*
*
*
*
*-----------------------------------------------------------------*/
ELSE IF BURST_ALGO = SINGLE_MODE THEN DO ;
IF «INPUT(TMST) AND STARTIMB TMST) <>0) THEN
BURST_ALGO= HUNTING_MODE ;
ELSE DO;
OUTPUT (BANK) .. GEN2;/* Switch to BANK TWO - General Config
OUTPUT(FMD)"'TXTHRESHO FMD OR RXTHRESH3 FMD;
OUTPUT (BANK) cNASO; /* Switch to BANK ZERO - NAS
OUTPUT (GER) = ENTIMRX GER;
/* Enable TIMER,RX and MODEM interrupts
OUTPUT (BANK)-WORK1; /* switch to BANK ONE - WORK
BURST ALGO = BURST MODE;
TEMP; INPUT(TMST); /* Reset timer status
OUTPUT (TMCR) '" STARTIMB TMCR;
END;
END;
/* End of SINGLE mode
*/
*/
*/
*/
*/
*/
/* .... End of BURST algorithm •••••••••.•.•••••.•••••.•.•••.••..•...... */
/*
/*
Another try to empty the Rx fifo
before leaving the interrupt handler
*/
*/
DO WHILE (INPUT (FLR) <>0)
/* Empty the Rx FIFO and store the
/* received character in RX_BUF
RX BUF(IX RX:=IX RX+1)=INPUT(RXD) ;
END ;END ;
/* End of Rx fifo interrupt
*/
*/
*/
/*************************************************************************
*
TxFIFO INTR
*
*************************************************************************
* input:
Tx Buffer
*
* output:
Finish tx
*
* function:
service Tx Fifo interrupt
*
*
transmit characters from transmit buffer (OPTIMIZE code) *
* called by: INTERRUPT HANDLER
*
* calling:
none
*
*
*
* flowchart: figure 12
description: paragraph 6.4.3
*
*************************************************************************/
ELSE IF INTR VEC=TXI GIR THEN DO ;
TX OCC=INPUT(FLR)-AND MASK TXOCC ;
- /* Tx fifo level occupancy
*/
/* Fill Tx FIFO, the transmitted characters are taken from TX.buf
*/
DO WHILE (TX OCC:=TX OCC+1)<5 ;
OUTPUT(TXD)=TX BUF(IX TX:=IX TX+1);
IF TX BUF(IX TX)=End Of File·THEN DO ;
OUTPUT(BANK)=NASO·; ~~ /* Disable Tx interrupt, as the transmit */
OUTPUT(GER)=DISTX GER; /* delimiter character was identified
*/
OUTPUT (BANK) =wORKI
/* Switch to BANK ONE - WORK
*/
TX_OCC = 5 ;
/* load TX.OCC to terminate external loop*/
FIN.TX = TRUE ;
/* Set Finish transmit flag
*/
END
END
END ;
/* End of TXFIFO_INTR
*/
292038-23
2-285
inter
AP-310
1***************************************************** ********************
STATUS INTR
*
*
*************************************************************************
none
*
* input:
Finish Rx
*
* output:
service Status interrupt
*
* function:
*
Receive station: EOF terminate the reception
*
*
Transmit station: X Off Disable the transmission
*
*
x:::on Enable the transmission
*
* called by: INTERRUPT HANDLER
*
* callinq:
none
*
** flowchart: fiqure 13
description: paraqraph 6.4.4
**
****************************************************** *******************1
STAT-INPUT (RST) 1
1* Get the current RST status
*1
RX_OCC=INPUT(FLR)
RX_OCC=SHR(RX_OCC,4)
1* Rx fifo level occupancy
*1
DO WHILE (RX OCC>O AND (NOT FIN RX»1
RX OCC=RX-OCC-l 1
1* First, empty Rx FIFO
RX:::CHR=tNPUT(RXD)
IF
RECEI~R
*1
THEN
ELSE DO 1
IF RX CHR = X OFF THEN DO 1
OUTPUT(BANK)=NASO:I* Switch to BANK ZERO - NAS
OUTPUT (GER) = INPUT(GER) AND DISTX GER 1
1* Disable TransmIt interrupt
OUTPUT(BANK)=WORK1;1* Switch to BANK ONE - WORK
END;
,
ELSE IF RX CHR = X ON THEN DO ;
OUTPUT (BANK) = NASO ;
OUTPUT (GER) = INPUT(GER) OR ENTX GER ;
1* Enable Transmit interrupt again
OUTPUT(BANK)= WORKl
END
END
END ;
IF RECEIVER THEN DO ;
IF «STAT AND ACRSTAT RST) <> 0) THEN DO 1
OUTPUT(BANK)- NASO-;
1* If End_Of_Line was recognized,
OUTPUT (GER) = DISRTX GER ;
OUTPUT(BANK)= WORK1; 1* Disable 82510-interrupts and the
FIN_RX
.. TRUE;
1* Reception
END ;
ELSE IF «STAT AND ERRCHR RST) <> 0) THEN DO ;
CALL WRITE(@('** ERROR-in character Status ',D»
CALL ERROR_CHAR_HANDLER ;
IF BURST ALGO=BURST MODE THEN DO ;
1* In BURST mode do:
TEMP = INPUT(TMST); 1* Reset timer status
OUTPUT (TMCR)
STARTIMB TMCR;
END;
1* Restart TIMER
END
*1
*1
*1
*1
*1
*1
*1
*1
*1
*/
END
END ;
1* End of STATUS interrupt
*/
292038-24
2-286
AP-310
1*************************************************************************
*
*
TIMER INTR
*******************~.******.**************.*********** *******************
*
*
*
*
*
*
input:
output:
function:
called by:
calling:
none
Burst_Algo
service Timer interrupt; receive characters
and switch Burst Algo to HUNTING mode
INTERRUPT HANDLER
BURST 'TIMER
*
*
*
*
*
*
** flowchart: figure 14
description: paragraph 6.4.5
**
*************************************************************************1
ELSE IF INTR_VEC=TIMI_GIR THEN DO ;
IF ((RX_OCC:cINPUT(FLR»<>O) THEN DO
RX_OCC-SHR(RX_OCC,4) ; 1* Rx fifo level occupancy, shift right *1
1* - OPTIMIZE code *1
1* Empty the Rx FIFO and store the
*/
1* received character in RX_BUF
*/
RX_BUF(IX_RX:=IX_RX+l)=INPUT(RXD) ;
DO WHILE (RX OCC:-RX OCC-l) > 0 ;
RX BUF(IX-RX:=IX RX+l)=INPUT(RXD)
END1* store the received character in RX_buf*/
END ;
1*************************************************************************
*
*
*
*
**
* calling:
called by:
Burst Algo
Burst-Algo
execute a step in the burst algorithm
after timer interrupt; switch to HUNTING
TIMER_INTR
none
**
flowchart:
figure
BURST , TIMER
*
*************************************************************************
input:
output:
function:
6
description:
paragraph 6.2.2.4
*
*
*
*
*
*
**
*************************************************************************/
OUTPUT (BANK) = GEN2;
1* Switch to BANK TWO - General Config */
OUTPUT (FMD) = TXTHRESHO_FMD OR RXTHRESHO FMD;
1* Rxfifo threshold=O, Txfifo threshold=O*/
OUTPUT (BANK) = NASO;
OUTPUT (GER) = ENRX GER;
OUTPUT (BANK) = WORKl;
TEMP - INPUT(TMST);
BURST_ALGO = HUNTING_MODE
END ;
1*
1*
1*
1*
1*
1*
Switch to BANK ZERO - NAS
Disable Timer interrupt and
Enable RX,STAT,MODEM interrupts
Acknowledge TIMER interrupt
Back to HUNTING mode
End of TIMER interrupt
*/
*/
*/
*/
*/
*/
292038-25
2-287
inter
AP·310
1*****'*************'**************************************:*****************
*
MODEM I N T R ' "
" ,',
*
•• * ••••••'••••••••• **.* ••••••••••
* •••• *••••••• * •• * ••'''*-•••• *.*.*'.' •• *** ••
*
*
*
*
*••
input:
output:
function:
*
* called by:
*
**
callinq:
flo~chart:
none
none
service Modem interrupt and handle modem errors.
Modem interrupt is occurred if No Modem was setup, or
if DSR was dropped in the middle of the communication
INTERRUPT HANDLER
none
*
figure 15
**
description:
paraqraph 6.4.6
..
*
*
*
*
*
*************************************************************************1
STAT=INPUT(MSR) ;
1* Get MODEM status
*/
1* Handel Modem Errors handshake
*/
END ;
1* End of MODEM interrupt
*/
OUTPUT(PORT_EOI)=COMM_EOI
1* Write End Of Interrupt command to the */
1* PIC (8259A) */
END INTR_HANDLER
/* ••••••••••••••••••••••••• * ••••••••••••••••••••••••••• it* •• * •••• **.* ••• ***
* Procedure
ERROR MODEM HANDLER
.**.it •••••• * ••• * •••
** ••••*••••••••••••••••••• * ••••••••
itit* • •
'*
*.* ••• * •••• * •• /
ERROR_MODEM_HANDLER: PROCEDURE PUBLIC ;
MOPEM_HANDSHAKE
= FALSE ;
1* Flaq indicates that an Error occurred */
1* in Modem
*/
1*************************************************************************
* Procedure ERROR CHAR HANDLER
' *
**********************************************,**,*************************/
ERROR_CHAR_HANDLER: PROCEDURE PUBLIC ;
= TRUE
OUTPUT (BANK)
OUTPUT (GER)
OUTPUT (BANK)
NASO ;
DISRTX GER ;,
WORKl -;
1* Flaq indicates that an Error occurred */
/* durinq Reception
*/
1* switch to BANK ZERO - NAS
1* Disable all the 82510 Interrupts
1* Switch to BANK ONE - WORK
*/
*/
*/
292038-26
2-288
inter
AP-310
/*************************************************************************
* Procedure
LOOP
*
*
* LOOP procedure is executed until Transmission/Reception Finishes
* or until the loop ends.
*
*
*
*****************************~*******************************************/
LOOP: PROCEDURE PUBLIC f
DECLARE N WORD :
DECLARE NUM WORD :.
DECLARE MAXLOOP BYTE
MAXLOOP- 20 ;
NUM-O :
DO WHILE ( (NOT FIN TX) AND (NOT FIN RX) AND (NUM' ,
CR-;-LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyZ0123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',
CR"LF,
iABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',
CR,LF,End_Of_File,O)
/* End_Of_File-terminate the Transmission*/
END TEXT ;
292038-27
2-289
inter
/************************************************"****'****************,*lrr***
*
External
*
*
*
*
*
*
WRITELN:
MENU:
*
procedures
*************************************************************************
I/O cons!)le utility
dispaly a string" end with CR
I/O console utility - display a menu, enter the user
selection
DISPTEXT: I/O console utility - display the contents of the
Receive buffer (Rx buf)
INIT_HARDWARE_SETUP: setup and Hardware configuratIons of the
*
specific station
*
*
*
*
*
*
*
*************************************************************************/
/*************************************************************************
*
* Procedure
MAIN
*
*
*
get station type (Rx or Tx) from the operator;
wait till communication is completed; display;
RECEIVER STATION SHOULD BE ACTIVATED FIRST
Application
INITIALIZATIONS, LOOP
*************************************************************************
* input:
Finish Rx, Finish Tx
*
* output:
Receiver flag
*
~
*
function:
called by:
calling:
** flowchart:
figure
3
description:
paragraph 6.1
*
*
*
*
*
**
*************************,********************************'**************** /
MAIN:
/* External, setup and H/W configurations./
FIN=FALSE ;
DO WHILE NOT (FIN)
SELECTION=O ;
CALL WRITELN(@('-------------------~---------------------~------ ',0));
SELECTION=MENU(SELECTION,@('station: (Quit/Transmitter/Receiver) ',0)) ;
/* Get operator selection.
' */
/* Receiver station should be activated */
/* prior to the transmitter' station
*/
DO CASE SELECTION ;
FIN-TRUE
/* 0 - Quit of HIGH PERFORMANCE Driver
*/
DO;
/* 1 - Transmit station
*/
RECElVER=FALSE ;
CALL INITIALIZATIONS;
CALli" LOOP, ;
END ;
DO;
/* 2 - Receive station
*/
RECEIVER-TRUE
CALL INITIALIZATIONS
CALL LOOP;
END
END
END
CALL EXIT
END HIGHPERFORMANCE ;
/***********************************************************************.*/
2,92038-28
2-290
AP-310
APPENDIX B
82510 BASED sex SERIAL CHANNEL
This document describes the implementation of an
82510 based SBX board that provides a RS-232 interface to any iSBC board which has an SBX connector.
The SBX can be useful for customers that need a fast
software development vehicle while the 82510 system
hardware is still in the design stage. The customer can
also use the SBX for evaluation of the 82510 in a system environment.
In order to minimize the customer's software development costs, the RMX86/286 Terminal Device Driver
for the 82510 has also been developed and can be run
by the RMX user on his iSBC with the SBX-8251O
board described herewith. The RMX86/286 drivers are
available from INSITE, along with the source code and
the documentation.
2-291
BOARD DESCRIPTION
(See Figure B-1)
The following 82510 signals are connected directly to
the SBX connector (installed on the pin side): DATA,
ADDRESS, INTERRUPT, RESET, READ#,
WRITE# and CS#. Wait states are generated by a
shift register logic (U5, U7), clocked by the MCLK
signal of the SBX interface. The number of wait states
is selected by installing one of the eight jumpers to select one parallel output of the shift register. The 82510
is clocked by an 18.432 MHz Crystal (using its on-chip
oscillator). A discrete transistor is used to pull down
the RTS# signal during RESET to set the crystal mode
(note that in a larger board, an unused open collector
inverter or three-state gate can be used for this purpose). The 82510 is connected to the communication
channel through RS-232 line drivers and receivers. Either a 25 pin D-Type connector (P) or a 26 pin Flat-Cable connector (F) is used to connect the board to the
RS-232 channel.
l
, ,..
5
P/4 F/20. RTS
INT
22 AO
~~
~
,1
24
,~~
25 00
.
M
A2
DTR#
26 DI
, ,~
27
, u
28 03
,
_.
,
,
iil
I\)
,
I~
, '"
,'L.L.
II)
I\)
D.
tloR
r
I
9
4
P/20 F/13~ DTR
U2 .
~/" F/24
ru;)oo!6:....-...:..!.~:.r.:.;;:..
~
5 U2
~
TXDATA
D4
CTS#~1~4~__________~~
II
D6
4 D7
20
RD#
19
CS#
13
OSR#I"I'-'O---~
RI#
12
~
XI
U3
~IO
U4
co ...
18.432
101Hz
W
P/5 F/18
-'---'--+ CTS
P/6 F/16 ~ DSR
13
DCDN
RXD 13
18 WR#
......
0CD
I\)
TXD
,'5
._
c:
U1
82510
2 D5
, ,I
."
~i
02
1
L~
115
P/22 F/9~ RI
P/8 F/12
-'---'--+DCO
P/3 F/22
P/7.1
F
F 26
:J:-
GND
....
0
~
II
GND
i
3
292038-29-
!!I.
J/3.17.35
. I a JLF
('j'
"NU •
1/1
Vcc.J/4.18.36
J/2
- 12
:l: ::1i ::1i ::1i ::l!.
TTTTT
71
+ 12 4
.1.
·:;:;0.1)J.t
~~
#
WAIT State Generator
# of WAIT
States
1
2
3
4
Jumper # of WAIT Jumper
to CLOSE States to CLOSE
51
52
53
54
5
6
7
8
55
56
57
58
Only One Jumper 5hould Be Closed at a Time
Type
Vee
GND -12 +12
#
Type
Vee
GND
14
7
-12
U1 82510
21
7
U2 1488
5,9
7
U3 1489
14
7
J
5BX Male Connector for 8 Bit Bus
U4 1489
14
7
P
25 Pin D-Type Connector (Male)
F
26 Pin Flat-cable Connector (Male)
U5 74L5164 1,2,14
7
U6 Jumper
1
14
U7 74L500
Either P or F should be installed.
.
• RXDATA
F/14
+12
Co)
APPLICATION
NOTE
AP-36
November 1986
Using the 8273 SOLC/HOLC
Protocol Controller
JOHN BEASTON
MICROCOMPUTER APPLICATIONS
Order Number: 611001-001
2-293
inter
. AP-36
INTRODUCTION
SDLC/HDLC OVERVIEW
The Intel 8273 is a Data Communications Protocol
~ontroller designed for use in systems utilizing either
SDLC or HDLC (Synchronous or High-Level Data
Link Control) protocols. In addition to the usual features such as full duplex operation, automatic Frame
Check Sequence generation and checking, automatic
zero bit insertion and deletion, and TIL compatibility
found on other single component SDLC controllers, the
8273 features a frame level command structure, a digital phase locked loop, SDLC loop operation, and diagnostics.
SDLC is a protocol for managing the flow of information on a data communications link. In other words,
SDLC can be thOUght of as an envelope-addressed,
stamped, and containing an s.a.s.e.-in which information is transferred from location to location on a data
communications link. (Please note that while SDLC is
discussed specifically, all comments also apply to
HDLC except where noted.) The link may be either
point-to-point or multi-point, with the point-to-point
configuration being either switched or nonswitched.
The information flow may use either full or half duplex
exchanges. With this many configurations supported, it
is difficult to fmd a synchronous data communications
application where SDLC would not be appropriate.
The frame level command structure is made possible by
the 8273's unique internal dual processor architecture.
A high-speed bit processor handles the serial data manipulations and character recognition. A byte processor
implements the frame level commands. These dual
processors allow the 8273 to control the necessary byteby-byte operation of the data channel with a minimum
of CPU (Central Processing Unit) intervention. For the
user this means the CPU has time to take on additional
tasks. The digital phase locked loop (DPLL) provides a
means of clock recovery from the received data stream
on-chip. This feature, along with the frame level commands, makes SDLC loop operation extremely simple
and flexible. Diagnostics in the form of both data and
clock loopback are available to simplify board debug
and link testing. The 8273 is a dedicated function peripheral in the MCS-80/85 Microcomputer family and
as such, it interfaces to the 8080/808S system with a
minimum of external hardware.
This application note explains the 8273 as a component
and shows its use in a generalized loop configuration
and a typical 8085 system. The 8085 system was used to
verify the SDLC operation of the 8273 on an actual
IBM SDLC data communications link.
The first section of this application note presents an
overview of the SDLC/HDLC protocols. It is fairly
tutorial in nature and may be skipped by the more
knowledgeable reader. The second section describes the
8273 from a functional standpoint with explanation of
the block diagram. The software aspects of the 8273,
including command examples, are discussed in the
third section. The fourth and fifth sections discuss a
loop SDLC configuration and the 8085 system respectively.
Opening
Flag
Address
Field (Aj
Control
Field (C)
01111110
8 Bits
8 Bits
Aside from supporting a large number of configurations, SDLC offers the potential of a 2 X increase in
throughput over the presently most prevalent protocol:
Bi-Sync. This performance increase is primarily due to
two characteristics of SDLC: full duplex operation and
the implied acknowledgement of transferred information. The performance increase due to full duplex operation is fairly obvious since, in SDLC, both stations can
communicate simultaneously. Bi-Sync supports only
half-duplex (two-way alternate) communication. The
increase from implied acknowledgement arises from the
fact that a station using SDLC may acknowledge previously received information while transmitting different
information. Up to 7 messages may be outstanding before an acknowledgement is required. These messages
may be acknowledged as a block rather than singly. In
Bi-Sync, acknowledgements are unique messages that
may not be included with messages containing information and each infoI'I\lation message requires a separate
acknowledgement. Thus the line efficiency of SDLC is
superior to Bi-Sync. On a higher level, the potential of a
2 X increase in performance means lower cost per unit
of information transferred. Notice that the increase is
not due to higher data link speeds (SDLC is actually
speed independent), but simply through better line utilization.
Getting down to the more salient characteristics of
SDLC; the basic unit of information on an SDLC link
is that of the frame. The frame format is shown in Figure 1. Five fields comprise each frame: flag, address,
control, information, and frame check sequence. The
flag fields (F) form the boundary of the frame and all
Information
Field (I)
Any Length
Oto N Bits
Figure 1. SOLC Frame Format
2·294
Frame
Check
Sequence
(FCS)
Closing
Flag
16 Bits
01111110
AP-36
other fields are positionally related to one of the two
flags. All frames start with an opening flag and end
with a closing flag. Flags are used for frame synchronization. They also may serve as time-fill characters between frames. (There are no intraframe time-fill characters in SDLC as there are in Bi-Sync.) The opening flag
serves as a reference point for the address (A) and control (C) fields. The frame check sequence (FCS) is referenced from the closing flag. All flags have the binary
configuration 01111110 (7EH).
SDLC is a bit-oriented protocol, that is, the receiving
station must be able to recognize a flag (or any other
special character) at any time, not just on an 8-bit
boundary. This, of course, implies that a frame may be
N-bits in length. (The vast majority of applications tend
to use frames which are multiples of 8 bits long, however.)
The fact that the flag has a unique binary pattern would
seem to limit the contents of the frame since a flag
pattern might inadvertently occur within the frame.
This wOldd cause the receiver to think the closing flag
was received, invalidating the frame. SDLC haltdles
this situation through a technique called zero bit insertion. This techniques specifies that within a frame a
binary 0 be inserted by the transmitter after any succession of five contiguous binary Is. Thus, no pattern of
01111110 is ever transmitted by chance. On the receiving end, after the opening flag is detected, the receiver
removes any 0 following 5 consecutive Is. The inserted
and deleted Os are not counted for error determination.
Before discussing the address field, an explanation of
the roles of an SDLC station is in order. SDLC specifies two types of stations: primary and secondary. The
primary is the control station for the data link and thus
has responsibility of the overall network. There is only
one predetermined primary station, all other stations
on the link assume the secondary station role. In general, a secondary station speaks only when spoken to. In
other words, the primary polls the secondaries for responses. In order to specify a specific secondary, each
secondary is assigned a unique 8-bit address. It is this
address that is used in the frame's address field.
When the primary transmits a frame to a specific secondary, the address field contains the secondary's address. When responding, the secondary uses its own
address in the address field. The primary is never identified. This ensures that the primary knows which of
many secondaries is responding since the primary may
have many messages outstanding at various secondary
stations. In addition to the specific secondary address,
an address common to all secondaries may be used for
various purposes. (An all Is address field is usually
used for this "All Parties" address.) Even though the
primary may use this common address, the secondaries
are expected to respond with their unique address. The
address field is always the first 8 bits following the
opening flag.
The 8 bits following the address field form the control
field .. The control field embodies the link-level control
of SDLC. A detailed explanation of the commands and
responses contained in this field is beyond the scope of
this application note. Suffice it to say that it is in the
control field that the implied acknowledgement is carried out through the use of frame sequence numbers.
None of the currently available SDLC single chip controllers utilize the control field. They simply pass it to
the processor for analysis. Readers wishing a more detailed explanation of the control field, or of SDLC in
general, should consult the IBM documents referenced
on the front page overleaf.
In some types of frames, an information field follows
the control field. Frames used strictly for link management mayor may not contain one. When an information field is used, it is unrestricted in both content and
length. This code transparency is made possible because
of the zero bit insertion mentioned earlier and the 'bitoriented nature of SDLC. Even main memory core
dumps may be transmitted because of this capability.
This feature is unique to bit-oriented protocols. Like
the control field, the information field is not interpreted
by the SDLC device; it is. merely transferred to and
from memory to be operated on and interpreted by the
processor.
The final field is the frame check sequence (FCS). The
FCS is the 16 bits immediately preceding the closing
flag. ,This 16-bit field is used for error detection through
a Cyclic Redundancy Checkword (CRC). The 16-bit
transmitted CRe is the complement of the remainder
obtained when the A, C, and I fields are "divided" by a
generating polynomial. The receiver accumulates the
A, C, and I fields and also the FCS into its internal
CRe register. At the closing flag, this register contains
one particular number for an error-free reception. If
this number is not obtained, the frame was received in
error and should be discarded. Discarding the frame
causes the station to not update its frame sequence
numbering. This results in a retransmission after the
station sends an acknowledgement from previous
frames. [Unlike all other fields, the FCS is transmitted
MSB (Most Significant Bit) first. The A, C, and I fields
are transmitted LSB (Least Significant Bit) first.] The
details of how the FCS is generated and check~ is
beyond the scope of this application note and since all
single component SDLC controllers handle this function automatically, it is usually sufficient to know only
that an error has or has not occurred. The IBM documents contain more detailed information for those
readers desiring it.
The closing flag terminates the frame. When the closing
flag is received, the receiver knows that the preceding
16 bits constitute the FCS and that any bits between the
control field and the FCS constitute the information
field.
2-295
intJ
Ap·36
SOLC does not support aninterframe time-fill character such as the SYN character in Bi-Sync. If an unusual
condition occurs while transmitting, such as data is not
available in time from memory or CTS (Clear-ta-Send)
is lost from the modem, the, transmitter aborts the
frame by sending an Abort character to notify the receiver to invalidate the frame. The Abort character
consists of eight contiguous 1s sent without zero bit
insertion. Intraframe time-fill consists of either flags,
Abort characters, or any combination of the two. .
While the Abort character protects the receiver, from
transmitted errors, errors introduced by the transmission medium are discovered at the receiver through the
FCS check and a check for invalid frames. Invalid
frames are those which are not bounded by flags or are
too short, that is, less than 32 bits between flags. All
invalid frames are ignored by the receiver.
Although SOLC is a synchronous protocol, it provides
an optional feature that allows its use on basicallyasynchronous data links-NRZI (Non-Retum-to-Zero-Inverted) coding: NRZI coding specifies that the signal
condition does not change for transmitting a binary I,
while a binary 0 causes a change of state. Figure 2 illustrates NRZI coding compared to the normal NRZ.
NRZI coding guarantees that an active line will have a
transition at least every 5-bit times; long strings of zeroes cause a transition every bit time, while long strings
of. Is are broken up by zero bit insertion. Since asynchronous operation requires that the receiver sampling
clock be derived from the received data, NRZI encoding plus zero bit insertion make the design of clock
.
recovery circuitry easier.
DATA
BIT SAMPLE
1
o
,0
1
0
1
0
Ill!!!!!!!
NRZ
NRZI
611001-1
, Figure 2. NRZI vs NFiZ Ellcoding
All of thtl previous discussion has applied to SOLC on
either pomt-to-point or ,multi-point, data networks.
SOLC (but not HOLC) also includes specification for a
loop configuration. Figure 3 compares these three configurations. IBM uses this lopp configuration in its
3650 RE1tail Store System. It consists of a single loop
controller station with one or more down-loop secondary stations. Communications on a loop 'rely on the
secondary stations repeating a received message down
loop with a delay of one bit time. The reason for the
one bit delay will be evident shortly.
Loop operation defines a new special character: the
BOP (End-of-Poll) character which consists of a 0 followed by 7 contiguous, non-zero bit inserted, ones. After the loop controller transmits a message, it idles the
line (send~ all Is). The fin8l zero of the closing flag plus
the first 7 Is of the idle form an BOP character. While
POINT·TO·POINT
LOOP
611001-3
MULTJ.POINT
611001-2
Figure 3. Network Configurations
2-296
inter
AP-36
repeating, the secondaries monitor their incoming line
for an EOP character. When an EOP is detected, the
secondary checks to see if it has a message to transmit.
If it does, it changes the seventh 1 to a 0 (the one bit
delay allows time for this) and repeats the modified
EOP (now alias flag). After this flag is transmitted, the
secondary terminates its repeater function and inserts
its message (with mUltiple preceding flags if necessary).
After the closing flag, the secondary resumes its one bit
delay repeater function. Notice that the final zero of the
secondary's closing flag plus the repeated Is from the
controller form an EOP for the next down-loop secondary, allowing it to insert a message if it desires.
lowed by 7 Is) and the HOLC Abort (7 Is). This possible incompatibility is neatly handled by the HOLe protocol not specifying a loop configuration.
This completes our brief discussion of the SOLCI
HOLC protocols. Now let us turn to the 8273 in particular and discuss its hardware aspects through an explanation of the block diagram and generalized system
schematics.
One might wonder if the secondary missed any messages from the controller while it was inserting its own
message. It does not. Loop operation is basically halfduplex. The controller waits until it receives an EOP
before it transmits its next message. The controller's
reception of the EOP signifies that the original message
has propagated around the loop followed by any messages inserted by the secondaries. Notice that secondaries cannot communicate with one another directly, all
secondary-to-secondary communication takes place by
way of the controller.
Loop protocol does not utilize the normal Abort character. Instead, an abort is accomplished by simply
transmitting a flag character. Oown loop, the receiver
sees the abort as a frame which is either too short (if the
abort occurred early in the frame) or one with an FCS
error. Either results in a discarded frame. For more
.details on loop operation, please refer to the IBM documents referenced earlier.
Another protocol very similar to SOLC which the 8273
supports is HOLC (High-Level Oata Link Control).
There are only three basic differences between the two:
HOLC offers extended address and control fields, and
the HOLC Abort character is 7 contiguous Is as opposed to SOLC's 8 contiguous Is.
Extended addressing, beyond the 256 unique addresses
possible with SOLC, is provided by using the address
field's least significant bit as the extended address modifier. The receiver examines this bit to determine if the
octet should be interpreted as the final address octet.
As long as the bit is 0, the octet that contains it is
considered an extended address. The first time the bit is
aI, the receiver interprets that octet as the final address
octet. Thus the address field may be extended to any
number of octets. Extended addressing is illustrated in
Figure 4a.
A similar technique is used to extend the control field
although the extension is limited to only one extra control octet. Figure 4b illustrates control field extension.
Those readers not yet asleep may have noticed the similarity between the SOLC loop EOP character (a 0 fol-
FIRST BIT TAANSMI"ED (LSB FIRST)
611001-4
A. HDLC ADDRESS FIELD EXTENSION
C
FLAG
A
EXTENSION BIT (1 MAX)
ltc, I I " I I
e2
1'2
Fes,
Fes2'
FtAG
611001-5
B. HDLC CONTROL FIELD EXTENSION
Figure 4
BASIC 8273 OPERATION
It will be helpful for the following discussions to have
some idea of the basic operation of the 8273. Each operation, whether it is a frame transmission, reception or
port read, etc., is comprised of three phases: the Command, Execution, and Result phases. Figure 5 shows
the sequence o(these phases. As an illustration of this
sequence, let us look at the transmit operation.
611001-6
Figure 5. 8273 Operational Phases
When the CPU decides it is time to transmit a frame,
the Command phase is entered by the CPU issuing a
Transmit Frame command to the 8273. It is not sufficient to just instruct the 8273 to transmit. The frame
level command structure sometimes requires more information such as frame length and address and control
field content. Once this additional information is sup-
2-297
inter
Ap·36
plied. the Comm.and phase is complete and the Execution phase is entered. It is during the Execution phase
that the actual operation, in this case a frame transmission, takes place. The 8273 transmits the opening flag,
A and C fields, the specified number of I field bytes,
inserts the FCS, and closes with the closing flag. Once
the closing flag is transmitted, the 8273 leaves the EXecution phase and begins the Result phase. During the
Result phase the 8273 notifies the CPU of the outcome
of the command by supplying interrupt results. In this
,case, the results would be either that the frame is complete or that some error condition causes the transmission to be aborted. Once the CPU reads all of the results (there is only' one for the Transmit Frame
command), the Result phase and consequently the
operation, is complete. Now that we have a general
feeling for the operation of the 8273, let us discuss the
8273 in detail.
HARDWARE ASPECTS OF THE 8273
The 8273 block diagram is shown in Figure 6. It consists of two major interfaces: the CPU module interface
and the modem interface. Let's discuss each interface
separately.
CPU Interface
The CPU interface consists of four major blocks: Control/Read/Write logic (C/R/W), internal registers,
data transfer logic, and data bus buffers.
The CPU module utilizes the CIR/W logic to issue
commands to the 8273. Once the 8273 receives'a command and executes it, it returns the results (goodlbad
completion) of the comm.and byway of the C/R/W
logic. The C/R/W logic is supported ~seven ~sters
which are addressed via the Ao, AI, RD, and WR signals, in addition to CS. The Ao and A 1 signals are generally derived from the two low order bits of the CPU
module address bus while RD and WR are the normal
I/O Read and Write signals found on the system control bus. Figure 7 shows the address of each register
using the C/R/W logic. The function of each register is
defined as follows:
Control Inputs
Address Inputs
A1
Ao
CS-RD
CS-WR
0
0
1
1
0
1
0
1
Status
Result
Txl/R
Command
Parameter
Test Mode
RxllR
-
Figure 7. 8273 Register Selection
,-----~---
FLAG DETECT
,---------co
REGISTERS
TxllR
RxllR
TEST MODE
,----------- CfS
COMMAND
, - - - - - - - - - RTS
PARAMETER
STATUS
RESULT
DBo-7
po------- TiC
TxDRQ + ; - - - - - j
TxDACK
DATA'
TIMING
LOGIC
----01
RxDRQ----i
t----TxD
P----RxC
1_______ RxD
' - - - - - - - - DPLL
~-------~
AO---·'
Al---·'
RESET - - - - - - - - - '
OCLK----~
TdNT _ -_____- - '
RxlNT _ _ _ _ _ _--'
CPU MODULE INTERFACE
MODEM INTERFACE
611001-7
Figure 6. 8273 Block Diagram
2-298
intJ
AP-36
Command-8273 operations are initiated by writing
the appropriate command byte into this register.
Parameter-Many commands require more information than found in the command itself. This additional
information is provided by way of the parameter register.
Immediate Result (Result}-The completion information (results) for commands which execute immediately
are provided in this register.
Transmit Interrupt Result (TxIIR}-Results of transmit operations are passed to the CPU in this register.
Receiver Interrupt Result (RxIIR}-Receive operation
results are passed to the CPU via this register.
Status-The general status of the 8273 is provided in
this register. The Status register supplies the handshaking necessary during various phases of the 8273 operation.
Test Mode-This register provides a software reset
function for the 8273.
The commands, parameters, and bit definition of these
registers are discussed in the following software section.
Notice that there are not specific transmit or receive
data registers. This feature is explained in the data
transfer logic discussion.
The final elements of the C/R/W logic are the interrupt lines (RxINT and TxINT). These lines notify the
CPU module that either the transmitter or the receiver
requires service; i.e., results should be read from the
appropriate interrupt result register or a data transfer is
required. The interrupt request remains active until all
the associated interrupt results have been read or the
data transfer is performed. Though using the interrupt
lines relieves the CPU module ofthe task of polling the
8273 to check if service is needed, the state of each
interrupt line is reflected by a bit in the Status register
and non-interrupt driven operation is possible by examining the contents of these bits periodically.
The 8273 supports two independent data interfaces
through the data transfer logic; receive data and transmit data. These interfaces are programmable for either
DMA or non-DMA data transfers. While the choice of
the configuration is up to the system designer, it is
based on the intended maximum data rate of the com-
munications channel. Figure 8 illustrates the transfer
rate of data bytes that are acquired by the 8273 based
on link data rate. Full-duplex data rates above 9600
baud usually require DMA. Slower speeds mayor may
not require DMA depending on the task load and interrupt response time of the processor.
Figure 9 shows the 8273 in a typical DMA environment. Notice that a separate DMA controller, in this
case the Intel 8257, is required. The DMA controller
supplies the timing and addresses for the data transfers
while the 8273 manages the requesting of transfers and
the actual counting of the data block lengths. In this
case, elements of the data transfer interface are:
TxDRQ: Transmit DMA Request-Asserted by the
8273, this line requests a DMA transfer from memory
to the 8273 for transmit.
TxDACK' Transmit DMA Acknowledge-Returned by
the 8257 in response to TxDRQ, this line notifies the
8273 that a request has been granted, and provides access to the transmitter data register.
RxDRQ: Receive DMA Request-Asserted by the 8273,
it requests a DMA transfer from the 8273 to memory
for a receive operation.
RxDACK: Receive DMA Acknowledge-Returned by
the 8257, it notifies the 8273 that a receive DMA cycle
has been granted, and provides access to the receiver
data register.
RD: Read-Supplied by the 8257 to indicate data is to
be read from the 8273 and placed in memory.
WR: Write-Supplied by the 8257 to indicate data is to
be written to the 8273 from memory.
To request a DMA transfer the 8273 raises the appropriate DMA request line; let us assume it is a transmitter request (TxDRQ). Once the 8257 obtains control of
the system bus by way of its HOLD and HLDA (hold
acknowledge) lines, it notifies the 8273 that TxDRQ
has been grant~ returning TxDACK and WR. The
TxDACK and WR signals transfer data to the 8273 for
a transmit, independent of the 8273 chip select pin
(CS). A similar sequence of events occurs for receiver
requests. This "hard select" of data into the transmitter
or out of the receiver alleviates the need for the normal
transmit and receive data registers addressed by a combination of address lines, CS, and WR or RD. Competi-
2-299
inter
AP·36
tive devices that qo not have this "hard select" feature
require the use of an external multiplexer to supply the
correct inputs for register selection during DMA. (Do
not forget.that the SDLC controller sees both the addresses and control signals supplied by the DMA controller during DMA cycles.) Let us look at typical
frame transmit and frame receive sequences to better
see how the 8273 truly manages the DMA data transfer.
At this point the requests stop, the FCS and closing flag
are transmitted, and the TxINT line is raised, signaling
the CPU that the frame transmission is complete. Notice that after the initial command and parameter loading, absolutely no CPU intervention was required (since
DMA is used for data transfers) until the entire frame
was transmitted. Now let's look at a frame reception.
80 ms
Before a frame can be transmitted, the DMA controller
is supplied, by the CPU, the starting address for the
desired information field. The 8273 is then commanded
to transmit a frame. (Just how this is done is covered
later during our software discussion.) After the command, but before transmission begins, the 8273 needs a
little mor.e information (parameters). Four parameters
are required for the transmit frame command: the address field byte, the control field byte, and two bytes
which are the least significant and most significant
bytes of the information field byte length. Once all four
parameters are.1oaded, the 8273 makes RTS (Requestto-Send) active and waits for CTS (Clear-to-Send) to go
active. Once CTS is active, the 8273 starts the frame
transmission. While the 8273 is transmitting the opening flag, address field, and control field; it starts making
transmitter DMA requests. These requests continue at
character (byte) boundaries until the pre-loaded number of bytes of information field have been transmitted.
8 ms
sec/byte
800
eS
80
eS
100
DACK1
DROO
100K
611001-8
Figure 8. Byte Transfer Rate vs Baud Rate
RD
TxDACK
RxDRO
10K
BAUD RATE (bps)
DR01
8257
DMA
CONTROLLER
1K
8273
RxDACK
CS AO
lOR
lOW
WR
A1
roo''"o'
BUS
07-00
~ ~."..
ADDRESS
BUS
"
611001-9
Figure 9. DMA, Interrupt-Driven System
2-300
Ap·36
The receiver operation is very similar. Like the initial
transmit sequence, the DMA controller is loaded with a
starting address for a receiver data buffer and the 8273
is commanded to receive. Unlike the transmitter, there
are two different receive commands: General Receive,
where all received frames are transferred to memory,
and Selective Receive, where only frames having an address field matching one of two preprogrammed 8273
address fields are transferred to memory. Let's assume
for now that we want to general receive. After the receive command, two parameters are required before the
receiver becomes active: the least significant and most
significant bytes of the receiver buffer length. Once
these bytes are loaded, the receiver is active and the
CPU may return to other tasks. The next frame appearing at the receiver input is transferred to memory using
receiver DMA requests. When the closing flag is received, the 8273 checks the FCS and raises its RxINT
line. The CPU can then read the results which indicate
if the frame was error-free or not. (If the received frame
had been longer than the pre-loaded buffer length, the
CPU would have been notified of that occurrence earlier with a receiver error interrupt. The command description section contains a complete list of error conditions.) Like the transmit example, after the initial command, the CPU is free for other tasks until a frame is
completely received. These examples have illustrated
the 8273's management of both the receiver and transmitter DMA channels.
It is possible to use the DMA data transfer interface in
a non-DMA interrupt-driven environment. In this case,
4 interrupt levels are used: one each for TxINT and
RxINT, and one each for TxDRQ and RxDRQ. This
configuration is shown in Figure 10. This configuration
offers the advantages that no DMA controller is re-
quired and data requests are still separated from result
(completion) requests. The disadvantages of the configuration are that 4 interrupt levels are required and that
the CPU must actually supply the data transfers. This,
of course, reduces the maximum data rate compared to
the configuration based strictly on DMA. This system
could use an Intel 8259 8-level Priority Interrupt Controller to supply a vectored CALL (subroutine) address
based on requests on its inputs. The 8273 transmitter
and receiver make data requests by raising the respective DRQ line. The CPU is interrupted by the 8259 and
vectored to a data transfer routine. This routine either
writes (for' transmit) or reads (for receive) the 8273 using the respective TxDACK or RxDACK line. The
DACK lines serve as "hard" chip selects into and out
of the 8273. TxDACK + WR writes data into the 8273
for transmit. RxDACK + RD reads data from the
8273 for receive.) The CPU is notified of operation
completion and results by way of TxINT and RxINT
lines. Using the 8273, and the 8259, in this way, provides a very effective, yet simple, interrupt-driven interface.
Figure II illustrates a system very similar to that described above. This system utilizes the 8273 in a ndnDMA data transfer mode as opposed to the two DMA
approaches shown in Figures 9 and 10. In the nonDMA case, data transfer requests are made on the
TxINT and RxINT lines. The DRQ lines are not used.
Data transfer requests are separated from result requests by a bit in the Status register. Thus, in response
to an interrupt, the CPU reads the Status register and
branches to either a result or a data transfer routine
based on the status of one bit. As before, data transfers
are made via using the DACK lines as chip selects to
the transmitter and receiver data registers.
D7-DO
611001-10
Figure 10_ Interrupt-Based DMA System
2-301
intJ
Ap·36
"CONTROL
BUS
611001-11
Figure 11. Non-DMA Interrupt-Driven System
NC
NC
NC
NC
T,INT RxlNT T,ORO R,ORO
-CONTROL
lOR
BUS
8213
01-00
611001-12
Figure 12. Polled System
Figure 12 illustrates the simplest system of all. This
system utilizes polling for all data transfers and results.
Since the interrupt pins are reflected in bits in the
Status register, the software can read the Status register
periodically looking for one of these to be set. If it finds
an INT bit set, the appropriate Result Available bit is
examined to determine if the "interrupt" is a data
transfer or completion result. If a data transfer is called
for, the DACK line is used to enter or read the data
from the 8273. If the interrupt is a completion result,
the appropriate result register is read to determine the
goodlbad completion of the operation.
The final block of the CPU module interface is the
Data Bus Buffer. This block supplies the tri-state, bidirectional data bus interface to allow communication to
and from the 8273.
The actual selection of either DMA or non-DMA
modes is controlled by a command issued during initialization. This command is covered in detail during
the software discussion.
The modem control block provides both dedicated and
user-defined modem control functions. All signals supported by this interface are active low so that EIA in-
Modem Interface
As the name implies, the modem interface is the modem side of the 8273. It consists of two major blocks:
the modem control block and the serial data timing
block.
2-302
inter
AP-36
verting drivers (MCI488) and inverting receivers
(MCI489) may be used to interface to standard modems.
This function is handled automatically by the 8273. If
RTS is inactive (pin is high) when the 8273 is commanded to transmit, the 8273 makes it active and then
waits for CTS before transmitting the frame. O~
time after the end of the frame, the 8273 returns RTS to
its inactive state. However, if RTS was active when a
transmit command is issued, the 8273 leaves it active
when the frame is complete.
Port A is a modem control input port. Its representation on the data bus is shown in Figure 13. Bits DO and
D1 have dedicated functions. Do reflects the logical
state of the CTS (Clear-to-Send) pin. [If CTS is active
(low), Do is a 1.1 This signal is used to condition the
start of a transmission. The 8273 waits until CTS is
active before it starts transmitting a frame. While trans.
mitting, if CTS goes inactive, the frame is aborted and
the CPU is interrupted. When the CPU reads the interrupt result, a CTS failure is indicated.
Bit Ds reflects the state of the Flag Detect pin. This pin
is activated whenever an active receiver sees a flag character. This function is useful to activate a timer for line
activity timeout purposes.
D1 reflects the logical state of the CD (Carrier Detect)
pin. CD is used to condition the start of a frame reception. CD must be active in time for a frame's address
field. If CD is lost (goes inactive) while receiving a
frame, an interrupt is generated with a CD failure result. CD may go inactive between frames.
Bits D1 thru D4 provide four user-defined outputs. Pins
PB 1 thru PB4 reflect the logical state of these bits. The
8273 does not interrogate or manipulate these bits. D6
and D7 are not used. In addition to being able to output
to Port B, Port B may be read using a Read Port B
command. All Modem control output pins are forced
high on reset. (All commands mentioned in this section
are cov~ed in detail Iater.)
Bits D2 thru D4 reflect the logical state of the PA2 thru
P~ pins respectively. These inputs are user defmed.
The 8273 does not interrogate or manipulate these bits.
Bits Ds, D6, and D7 are not used and each is read as a I
for a Read Port A command.
The final block to be covered is the serial data timing
block. This block contains two sections: the serial data
logic and the digital phase locked loop (DPLL).
Elements of the serial data logic section are the ,data
pins, TxD (transmit data output) and RxD.J!..eceive
data input), and the respective data clocks, ,TxC and
RxC. The transmit and receive data is synchronized by
the TxC and RxC clocks. Figure 15 shows the timing
for these signals. The leading edge (negative transition)
Port B is a modem control output port. Its data bus
representation is shown in Figure 14. As in Port A, the
bit values represent the logical condition of the pins. Do
and ~are dedicated function o~ts. Do represents
the RTS (Request-to-Send) pin. RTS is normally used
to notify the modem that the 8273 wishes to transmit.
D7
D6
11
1
Ds
D4
D3
D2
Dl
Do
I I I I
L
1
CTS - CLEAR TO SEND
CD - CARRIER DETECT
I
I
I
PA21
PA3
USER·DEFINED INPUTS
PA4
611001-13
Figure 13. Port A (Input) Bit Definition
D7
D6
L1 J
1
DS
I
D4
D3
D2
Do
Dl
I I I I I
I
I
I
L
RTS -
I
REQUEST TO SEND
P81
P82
USER·DEFINED OUTPUTS
P83
P84
FLAG DETECT
611001-14
Figure 14. Port B (Output) Bit Definition
2-303
Ap·36
nal circuitry. Clock loopback over~mes this problem
by allowing the internal routing of TxC and RxC. Thus
the same clock used to transmit the data is used to
receive it. Examination of Figure 15 shows that this
method ensures bit synchronism. The fmal element of
the serial data logic is the Digital Phase Locked Loop.
of TxC genetates new transmit data and the trailing
edge (positive transition) of RxC is used to capture the
receive data.
The DPLL provides a means of clock recovery from
the received data stream. This feature allows the 8273
to interface without external synchronizing logic to low
cost asynchronous modems (modems which do not
supply clocks). It also makes the problem of clock timing in loop configurations trivial.
To use the DPLL, a clock at 32 times the required baud
rate must be supplied to the 32 X CLK pin. This clock
provides the interval that the DPLL samples the received data. The DPLL uses the 32 X clock and the
received data to generate a pulse at the DPLL output
pin. This DPLL pulse is positioned at the nominal center of the received data bit cell. Thus the DPLL output
may be wired to RxC andlor TxC to supply the data
timing. The exact position of the pulse is varied depending on the line noise and bit distortion of the received
data. The adjustment of the DPLL position is determined according to the rules outlined in Figure 16.
611001-15
Figure 15. Transmit/Receive Timing
It is possible to reconfigure this section under program
control to perfonn diagnostic functions; both data and
clock loopback are available. In data loopback mode,
the TxD pin is internally routed to the RxD pin. This
allows 'simple board checkout since the CPU can send
an SDLC message to itself. (Note that transmitted data
will still appear on the TxD pin.)
Adjustments to the sample phase of DPLL with respect
to the received data is made in discrete increments. Referring to Figure 16, following the occurrence of DPLL
When data loopback is utilized, the receiver may be
presented incorrect sample timing (RxC) by the exter.
11-_ _ _....:1:..:1::.:.IT,:.:TI::ME:..-_ _ _-I
x
RxD
NO TRANSITION
iiXcLK
:x:
lWW···
2 4 8 • 10 12 14 18 18 20 22 24 28 28 30 32
1-----32CLOCKS-----I
A
1 - - 4 - - 3 0 CLOCKS ---''''Io.:,----.j
I
B
:
I
I
I
I
I
~:--+I--33CLOCKS.,..-+---~
I
I
I
I
I
I
~LOCKS
---t----,
:
i
I
32 I
I
I
I
I
:
QUADRANT I
ADJUSTMENT I
I
I
I
I
I
I
I
Al
-2
81
-1
r:;;::AL
u~nY~.n.
82
Az
+1
+2
I
I
611001-16
Figure 16. DPLL Phase Adjustments
2-304
intJ
Ap·36
pulse A, the DPLL counts 32 X CLK pulses and examines the received data for a data edge. Should no edge
be detected in 32 pulses, the DPLL positions the next
DPLL pulse (B) at 32 clock pulses from pulse A. Since
no new phase information is contained in the data
stream, the sample phase is assumed to be at nominal
1 X baud rate. Now assume a data edge occurs after
DPLL pulse B. The distance from B to the next pulse C
is influenced according to which quadrant (AI, BI, B2,
or AU the data edge falls in. (Each quadrant represents
8 32x CLK times.) For example, if the edge is detected
in quadrant Alo it is apparent that pulse B was too close
to the data edge and the time to the next pulse must be
shortened. The adjustment for quadrant Al is specified
as - 2. Thus, the next DPiI pulse, pulse C, is positioned 32 - 2 or 30 32 X CLK pulses following DPLL
pulse B. This adjustment moves pulse C closer to the
nominal bit center of the next received data cell. A data
edge occurring in quadrant B2 would have caused the
adjustment to be small, namely 32 + I or 33 32 X
CLK pulses. Using this technique, the DPLL pulse
converges to the nominal bit center within 12 data transitions, worse case-4-bit times adjusting through
quadrant Al or A2 and 8-bit times adjusting through
BI or B2·
This completes our discussion of the hardware aspects
of the 8273. Its software aspects are now discussed.
SYNC
MODEM
611001-17
Synchronous Modem Interface
611001-18
Asynchronous Modem Interface
When the receive data stream goes idle after 15 ones,
DPLL pulses are generated at 32 pulse intervals of the
32 X CLK. This feature allows the DPLL pulses to be
used as both transmitter and receiver clocks.
Figure 17. Serial Data Timing Configuration
SOFTWARE ASPECTS OF THE 8273
In order to guarantee sufficient transitions of the received data to enable the DPLL to lock, NRZI encoding of the data is recommended. This ensures that,
within a frame, data transitions occur at least every five
bit times-the longest sequence of Is which may be
transmitted with zero bit insertion. It is also recommended that frames following a line idle be transmitted
with preframe sync characters which provide a minimum of 12 transitions. This ensures that the DPLL is
generating DPLL pulses at the nominal bit centers in
time for the opening flag. (Two DOH characters meet
this requirement by supplying 16 transitions with
NRZI encoding. The 8273 contains a mode which supplies such ,a preframe sync.)
The software aspects of the 8273 involve the communication of both commands from the CPU to the 8273
and the return of results of those commands from the
8273 to the CPU. Due to the internal processor architecture of the 8273, this CPU-8273 communication is
basically a form ofinterprocessor communication. Such
communication usually requires a form of protocol of
its own. This protocol is implemented through use of
handshaking supplied in the 8273 Status register. The
bit definition of this register is shown in FigUre 18.
Figure 17 illqstrates 8273 clock configurations using
either synchronous or asynchronous modems. Notice
how the DPLL output is used for both TxC and RxC in
the asynchron!lus case. This feature eliminates the need
for eX,ternal clock generation logic' where low cost asynchronous modems are used and also allows direct connection of 8273s for the ultimate in low cost data links.
The c011:figuration for loop applicatiQns is discussed in a
fo~.owing section.
"
,,' I
2-305
TaiRA _ TaiNT RESUL' AVAILABLE
fblRA - AIINT RESULT AYAILABLE
LJ~~=== CRIF -
TxlNT
RalNT -- '_INTERRUPT
fb: INTERRUPT
COMMAND RESULT
- IUFFER FULL
' - - - - - - - - - CpaF - COMMAND PARAMETEA
IUFFER FULL
' - - - - - - - - - - C l ' - COMMAND IUFFER FULL
' - - - - - - - - - - - easy -
COMMAND
ausv
611001-19
Figure 18. Status Register Format
AP-36
CBSY: Command Busy--,-CBSY indicates when the
8273 is in the command phase.. CBSY is set when the
CP~ writes a command into th~ Command register,
startmg the Command phase. It IS reset when the last
parameter is deposited in the Parameter register and
accepted by the 8273, completing the Command phase.
CBF: Command Buffer Full-When set, this bit indicates that a byte is present in the Command register.
This bit is normally not used.
CPBF: Command Parameter Buffer Full-This bit indicates that the Parameter register contains a parameter. It is set when the CPU deposits a parameter in the
Parameter register. It is reset when the 8273 accepts the
parameter.
CRBF: Command Result Buffer Full-This bit is set
when the 8273 places a result from an immediate type
command in the Result register. It is reset when the
CPU reads the result from the Result register.
RxINT: Receiver Interrupt-The state of the RxINT
pin is reflected by this bit. RxINT is set by the 8273
whenever the receiver needs servicing. RxINT is reset
when the CPU reads the results or performs the data
transfer.
TxINT: Transmitter Interrupt-This bit is identical to
RxINT except action is initiated based on transmitter
interrupt sources.
RxIRA: Receiver Interrupt Result Available-RxIRA is
set when the 8273 places an interrupt result byte into
the RxI/R register. RxIRA is reset when the CPU
reads the RxI/R register.
TxIRA: Transmitter Interrupt Result AvailableTxlRA is the corresponding Result Available bit for
the transmitter. It is set when the 8273 places an interrupt result byte in the TxI/R register and reset when
the CPU reads the register.
The significance of each of these bits will be evident
shortly. Since the software requirements of each 8273
phase are essentially independent, each phase is covered
separately.
Command Phase Software
Recalling the Command phase description in an earlier
section, the CPU starts the Command phase by writing
a command byte into the 8273 Command register. If
further information about the command ·is required by
the 8273, the CPU writes this inf0rmation into the Parameter register. Figure 19 is a flowchart of the Command phase. Notice that the CBSY and CPBF bits of
the Status register are used to handshake the command
and parameter bytes. Also note that the chart shows
611001-20
Figure 19. Command Phase Flowchart
that a command may not be issued if the Status register
indicates the 8273 is busy (CBSY = 1). If a command
is issued while CBSY = 1, the original command is
overwritten and lost. (Remember that CBSY signifies
the command phase is in progress and not the actual
execution of the command.) The flowchart also includes a Parameter buffer full check. The CPU must
wait until CPBF = 0 before writing Ii parameter to the
Parameter register. If a parameter is issued while CPBF
= 1, the previous parameter is overwritten and lost
An example of command ~utput assembly languag~
software is provided in Figure 20a. This software as-'
sumes that a .~ommand buffer exists in memory. The
buffer is pointed at by the HL register. Figure 20b
shows the command buffer structure.
The 8273 is a full duplex device, i.e., both the transmit~er and receiver niaybe executing commands or passing
mterrupt results at any given time. (Separate Rx and Tx
interrupt pins and result registers are provided for this
reason.) However, there is only one Command register.
Thus, the Command register must be used for only one
command sequence at a time and the transmitter and
receiver may never be simultaneously in a command
phase. A detailed description of the commands and
their parameters is presented in a following section.
2-306
inter
AP-36
;FUNCTION: COMMAND DISPATCHER
;INPUTS: HL - COMMAND BUFFER ADDRESS
;OUTPUTS: NONE
;CALLS: NONE
;DESTROYS: A,B,H,L,F/F'S
;DESCRIPTION: CMDOUT ISSUES THE COMMAND + PARAMETERS
;IN THE COMMAND BUFFER POINTED AT BY HL
CMDOUT: LXI
MOV
INX
CMD1:
IN
RLC
JC
MOV
OUT
CMD2:
MOV
ANA
RZ
INX
DCR
CMD3:
IN
ANI
JNZ
MOV
OUT
JMP
H,CMDBUF ;POINT HL AT BUFFER
B,M
;lST ENTRY IS PAR~ COUNT
H
;POINT AT COMMAND BYTE
STAT73
;READ 8273 STATUS
;ROTATE CBSY INTO CARRY
CMDl
;WAIT UNTIL CBSY=O
A,M
;MOVE COMMAND BYTE TO A
;PUT COMMAND IN COMMAND REG
COMM73
A,B
;GET PARAMETER COUNT
A
;TEST IF ZERO
;IF 0 THEN DONE
H
;NOT DONE, SO POINT AT NEXT PAR
B
;DEC PARAMETER COUNT
STAT73
;READ 8273 STATUS
CPBF
;TEST CPBF BIT
;WAIT UNTIL CPBF IS 0
CMD3
A,M
;GET PARAMETER FROM BUFFER
PARM73
;OUTPUT PAR TO PARAMETER REG
CMD2
;CHECK IF MORE PARAMETERS
Figure 20A. Command Phase Software
PARAMETER
+3
PARAMETER 2
+2
PARAMETER 1
+1
CMDBUF:
Execution Phase SOftware
3
+4
COMMAND
PARAMETER COUNT
+-HL
Figure 20B. Command Buffer Format
During the Execution phase, the operation specified by
the Command phase is performed. If the system utilizes
DMA for data transfers, there is no CPU involvement
during this phase, so no software is required. If nonDMA data transfers are used, either interrupts or polling is used to signal a data transfer request.
For interrupt-driven transfers the 8273 raises the appropriate INT pin. When responding to the interrupt,
2-307
inter
AP-36
the CPU must determine whether it is a data transfer
request or an interrupt signaling that an operation is
complete and results are available. The CPU determines the cause by reading the Status register and interrogating the associated IRA (Interrupt Result
Available) bit (TxlRA for TxlNT and RxlRA for
RxINT). If the IRA = 0, the interrupt is a data
transfer request. If the IRA = 1, an operation is
complete and the associated Interrupt Result register
must be read to determine the completion status (good/
bad/etc.). A software interrupt handler implementing
the above sequence is presented as part of the Result
phase software.
When polling is used to determine when data transfers
are required, the polling routine reads the Status register looking for one of the INT bits to be set. When a set
INT bit is found, the corresponding IRA bit is examined. Like in the interrupt-driven case, if the IRA = 0,
a data transfer is required. If IRA = 1, an operation is
complete and the Interrupt Result register needs to be
read. Again, example polling software is presented in
the next section.
Result Phase Software
During the Result phase the 8273 notifies the CPU of
the outcome of a command. The Result phase is initiated by either a successful completion of an operation or
an error detected during execution. Some commands
such as reading or writing the I/O ports provide immediate results, that is, there is essentially no delay from
the issuing of the command and when the result is
available. Other commands such as frame transmit,
take time to complete so their result is not available
immediately. Separate result registers are provided to
distinguish these two types of commands and to avoid
interrupt handling fo,r simple results.
Immediate results are provided in the Result register.
Validity of information in this register is indicated to
the CPU by way of the CRBF bit in the Status register.
When the CPU completes the Command phase of an
immediate command, it polls the Status register waiting
until CRBF = 1. When this occurs, the CPU may read
the Result register to obtain the immediate result. The
Result register provides only the results from immediate commands.
Example software for handling immediate results is
shown in Figure 21. The routine returns with the result
in the accumulator. The CPU then uses the result as is
appropriate.
All non-immediate commands deal with either the
transmitter or receiver. Results from these commands
are provided in the TxI/R (Transmit Interrupt Result)
and Rxl/R (Receive Interrupt Result) registers respectively. Results in these registers are conveyed to the
CPU by the TxIRA and RxIRA bits of the status register. Results of non-immediate commands consist of one
byte result interrupt code indicating the condition for
the interrupt and, ifrequired, one or more bytes supplying additional information. The interrupt codes and the
meaning of the additional results are covered following
the detailed command description.
Non-immediate results are passed to the CPU in response to either interrupts or polling of the Status register. Figure 22 illustrates an interrupt-driven result handler. (Please note that all of the software presented in
this application note is not optimized for either speed or
code efficiency. They are provided as a guide and to
illustrate concepts.) This handler provides for interrupt-driven data transfers as was promised in the last
section. Users employing DMA-based transfers do not
;FUNCTION: IMDRLT
;INPUTS: NONE
;OUTPUTS: RESULT REGISTER IN A
;CALLS: NONE
;DESTROYS: A, F/F'S
;DESCRIPTION: IMDRLT IS CALLED AFTER A CMDOUT FOR AN
;IMMEDIATE COMMAND TO READ THE RESULT REGISTER
IMDRLT: IN
ANI
JZ
IN
RET
STAT 73
CRBF
IMDRLT
RESL73
;RETURN
;READ
;TEST
;WAIT
;READ
8273 STATUS
IF RESULT REG READY
IF CRBF=O
RESULT REGISTER
Figure 21. Immediate Result Handler
2-308
inter
AP-36
place the results in a result buffer pointed at by
RCRBUF and TxRBUF.
,FUNCTION: RXI - INTERRUPT DRIVEN RESULT/DATA KANDLER
; INPUTS : ReRaUF, RCV'N,.
1CALLS: NONt;
,OUTPUTS: RCRSUF, ReV'NT
; DESTROYS: NOTHING
;DESCRIPTIOti'; RXI IS ENTERED AT A RECEIVER INTt.RRUPT.
.THE INTERRUPT IS TESTED rOR DATA TRANSFER (IRA-,)
JaR RESU1.T (IRA-1).
FOa DATA TRANSFER, THE DATA IS
, PLACED IN A aurFER AT RCVPNT. RESULTS ARE PLACED UI
;A Bur'ER AT RCRBUF.
;A FLAG(RXFLAG) IS SET IF THE INTERRUPT WAS A RESULT.
; (DATA TRANSFER INSTRUCTIONS ARE DENOTED BY C*) AND
,MAYBE ELIMINATED BY USt.RS USING DHA.
,
RXI:
•PSW
PUSb
PUSH
PUSH
•
I.
STAT71
RXIRA
•• 1
aXIl;
JZ
LHLO
RCRsur
.01
STAT11
RUNT
JZ
RxU
10
STAT71
I.
.NI
RXIRA
JZ
RUl
RUR71
IN
MOV
IN.
SHLe
J.P
RXI2:
SHLO
IN
HOV
IN'
JHP
RxI4:
I
AOI
JZ
IN
LhL&
NOV
IN'
SHLe
"VI
ST.
'Ixll:
pop
pop
£!
RET
TU2:
LhLC
NOV
OUT
10'
SULt
JlIP
"PSO
STAT71
TX!RA
TXI2
TXIa71
TxaBUF
M ••
•
TXRBUF
A,81ft
TXFLAG
PSW
•
;
kXIC:
CALI.
LOA
CPI
INR
JMP
RXI
RXFLAG
UH
PEXIT
C
POI.OP1
POP
Rt1'
PSW
; RtS1'OR~ PSW
;RJ:.TURh UTH COMPo STATUS IN C
JNZ
PUIT:
,SAVE HL
;SAVE PSW
; (*) R£AD 8271 STATUS
; (*) TEST TXlRA BIT
; (*) IF a, DATA TRANSFER
; 1, THEN REAt TXIR
;GET RESULT SUP FER POINTER
;STORE RESULT IN BUFFER
iBUMP RESULT POINTER
;RESTORE RE.SULT POINTER
;SET TXFLAG TO SHOlrI COMPLETION
iSET FLAG
; RESTORE PSW
;GO SERVIC~ RX
; GET RX FLAG
,hAS IT A COMPLE1'ION? (81)
;NO. ~o JUST EXIT
~YES, UPDATE C
;TRY AGAIN
611001-62
Figure 23. Polling Result Handler
8273 COMMAND DESCRIPTION
In this section, each command is discussed in detail. In
order to shorten the notation, please refer to the command key in Table l. The 8273 utilizes five different
command types: InitializatiOn/Configuration, Receive,
Transmit, Reset, and Modem Control.
;RESTORE HI.
JEhABL£ IhTERRU,TS
: DONE
TXPhT
(*) GET DATA POlhTER
•• H
(*) GET DATA FROM BUFFER
TXDATA
; (*) OUTPUT TO 8271 VIA TXDACK
(*) BUMP; DATA POINT£R
TXPHT
(*) RESTORE POUlTER
TXU
(*) RETURN AFTER RESTORE
•
Table 1. Command Summary Key
611001-61
Figure 22. Interrupt-Driven Result
Handlers with Non-DMA Data Transfers
Bo,B1
need the lines where the IRA bit is tested for zero.
(These lines are denoted by an asterisk in the comments
column.) Note that the INT bit is used to determine
when all results have been read. All results must be
read. Otherwise, ,the INT bit (and pin) will remain high
and further interrupts may be missed. These routines
A1,A2
Ro. R1
La. L1
2-309
RIC
TIC
A
C
-LSB and MSB of Receive Buffer Length
-LSB and MSB of Received Frame Length
-LSB and MSB of Transmit Frame Length
-Match Addresses for Selective Receive
-Receiver Interrupt Result Code
-Transmitter Interrupt Result Code
-Address Field of Received Frame
-Control Field of Received Frame
inter
AP-36
Initialization/Configuration Commands
The Initialization/Configuration commands manipulate registers internal to the 8273 that define the various
operating modes. These commands either set or' reset
specified bits in the registers depending on the type of
command. One parameter is required. Set commands
perform a logical OR operation of the parameter
(mask) and the internal register. This mask contains Is
where register bits are to be set. A "0" in the mask
causes no change in the corresponding register bit. Reset commands perform a logical AND operation of the
parameter (mask) and the internal register, i.e., the
mask is "0" to reset a register bit and a "1" to cause no
change. Before presenting the commands" the register
bit definitions are discussed.
01:
00:
Operating Mode Register (Figure 24)
07-06: Not Used-These bits must not be manipulated by any command; i.e., 07-06 must be 0
for the Set command and 1 for the Reset command.
OS:
HDLC Abort-When this bit is set, the 8273
will interrupt when 7 Is (HOLC Abort) are
received by an active receiver. When reset, an
SOLC Abort (8 Is) will cause an interrupt.
EOP Interrupt-Reception of an EOP character (0 followed by 7 Is) will cause the 8273 to
interrupt the CPU when this bit is set. Loop
controller stations use this mode as a signal
that a polling frame has completed the loop.
No BOP interrupt is generated when this bit is
reset.
Early Tx Interrupt-This bit specifies when
the transmitter should generate an end of
frame interrupt. If this bit is set, an interrupt is
generated when the last data character has
been' passed to the 8273. If the user software
issues another transmit command within two
byte times, the final flag interrupt, does not 32 bits). The 8273 handles this N-bit
reception through the high order bits (D7-D5) of the
result code. These bits code the number of valid received bits in the last received information field byte.
This coding is shown in Figure 30. The high order bits
of the received partial byte are indeterminate. [The address, control, and information fields are transmitted
least significant bit (Aa) first. The FCS is complemented and transmitted most significant bit first.l
Transmit Commands
The 8273 transmitter is supported by three Transmit
commands and three corresponding Abort commands.
returns to either Idle or Flag Stream, depending on the
Flag Stream bit of the Operating Mode register. IfRTS
was active before the transmit command, the 8273 does
not change it. If it was inactive, the 8273 will deactivate
it within one character time.,
Loop Transmit
Loop Transmit is similar to Frame Transmit (the parameter definition is the same). But since it deals with
loop configurations, One Bit Delay mode must be selected.
If the transmitter is not in Flag Stream mode when this
command is issued, the transmitter waits until after a
received EOP character has been converted to a flag
(this is done automatically) before transmitting. (The
one bit delay is, of course, suspended during transmit.)
If the transmitter is already in Flag Stream mode as a
result of a selectively received frame during a Selective
Loop Receive command, transmission will begin at the
next flag boundary for Buffered mode or at the third
flag boundary for non-Buffered mode. This discrepancy
is to allow time for enough data transfers to occur to fill
up the internal transmit buffer. At the end of a Loop
Transmit, the One Bit Delay mode is re-entered and the
flag stream mode is reset. More detailed loop operation
is covered later.
Transmit Frame
The Transmit Frame command simply transmits a
frame. Four parameters are required when Buffered
mode is selected and two when it is not. In either case,
the first two parameters are the least and the most significant bytes of the desired frame length (La, LJ). In
Buffered mode, La and LJ equal the length in bytes of
the desired information field, while in the non-Buffere4
mode, La and L) must be specified at the information
field length plus two .. (La and L) specify the number of
data. transfers to be performed.) In Buffered mode, the
address and control fields are presented to the transmitter as the third and fourth parameters respectively. In
non-Buffered mode, the A and C fields must be passed
as the first two data transfers.
Transmit Transparent
The Transmit Transparent command enables the 8273
to transmit a block of raw data. This data is without
SDLC protocol, i.e., no zero bit insertion, flags, or
FCS. Thus it is possible to construct and transmit a BiSync message for front-end processor switching or to
construct and transmit an SDLC message with incorrect FCS for diagnostic purposes. Only the La and L)
parameters are used since there are not fields in this
mode. (The 8273 does not support a Receive Transparent command.)
Abort Commands
When the Transmit Frame command is issued, .the
8273 makes RTS (Request-to-Send) act~pin low) if
it was not already. It then waits until CTS (Clear-toSend) goes active (pin low) before starting the frame. If
the Preframe Sync bit in the Operating Mode register is
set, the transmitter prefaces two characters (16 transitions) before the ppening flag. If the Flag Stream bit is
set in the Operating Mode register, the frame (including
Preframe Sync if selected) is started on a flag boundary.
Otherwise the frame starts on a character boundary.
At the end of the franle, the transmitter interrupts tile
CPU (the interrupt results are discussed shortly) and
Each of the above transmit commands has an associated Abort command. The Abort Frame Transmit command causes the transmitter to send eight contiguous
ones (no zero bit insertion) immediately and then revert
to either idle or flag streaming based on the Flag
Stream bit. (The 8 Is as an Abort character i~ compatible with both SDLC and HDLC.)
For Loop Transmit, the Abort Loop Transniit command causes the transmitter to send one flag and then
revert to one bit delay. Loop Ilrotocol depends upon
FCS errors to detect aborted frames.
2-314
inter
Ap·36
The Abort Transmit Transparent simply causes the
transmitter to revert to either idles or flags as a function of the Flag Stream mode specified.
The Abort commands require no parameters, however,
they do generate an interrupt and return a result when
complete.
A summary of the Transmit commands is shown in
Figure 31. Figure 32 shows the various transmit interrupt result codes. As in the receiver operation, the
transmitter generates interrupts based on either good
completion of an operation or an error condition to
start the Result phase.
The Early Transmit Interrupt result occurs after the
last data transfer to the 8273 if the Early Transmit Interrupt bit is set in the Operating Mode register. If the
8273 is commanded to transmit again within two character times, a single flag will separate the frames. (Buffered mode must be used for a single flag to separate the
frames. If non-Buffered mode is selected, three flags
will separate the frames.) If this time constraint is not
met, another interrupt is generated and multiple flags
or idles will separate the frames. The second interrupt
is the normal Frame Transmit Complete interrupt. The
Frame Transmit Complete result occurs at the closing
flag to signify a good completion.
The DMA Underrun result is analogous to the DMA
Overrun result in the receiver. Since SDLC does not
support intraframe time fill, if the DMA controller or
CPU does not supply the data in time, the frame must
be aborted. The action taken by the transmitter on this
error is automatic. It aborts the frame just as if an
Abort command had been issued.
Clear-to-Send Error result is generated if CTS goes inactive during a frame transmission. The frame is aborted as above.
The Abort Complete result is self-explanatory. Please
note however that no Abort Complete interrupt is generated when an automatic abort occurs. The next command type consists of only one command.
Reset Command
The Reset command provides a software reset function
for the 8273. It is a special case and does not utilize the
normal command interface. The reset facility is provided in the Test Mode register. The 8273 is reset by simply outputting a OlH followed by a OOH to the Test
Mode register. Writing the 01 followed by the 00 mimicks the action required by the hardware reset. Since
the 8273 requires time to process the reset internally, at
least 10 cycles of the CLK clock must occur between
the writing ofthe 01 and the 00. The action taken is the
same as if a hardware reset is performed, namely:
1) The modem control outputs are forced high inactive.
Hex
Code
Parameters'
Results
TxllR
Transmit Frame
Abort
C8
CC
Lo, L1, A, C
None
TIC
TIC
Loop Transmit
Abort
CA
CE
Lo, L1. A, C
None
TIC
TIC
Transmit Transparent
Abort
CO
CD
Lo. L1
None
TIC
TIC
Command
·NOTE:
A and C are passed as parameters in buffered mode only.
Figure 31. Transmitter Command Summary
Transmitter Interrupt
Result Code
RIC
D7-DO
00001100
00001101
00001110
00001111
00010000
Early Tx Interrupt
Frame Tx Complete
DMA Underrun
Clear to Send Error
Abort Complete
TxStatus
after INT
Active
Idle or Flags
Abort
Abort
Idle or Flags
Figure 32. Transmitter Interrupt Result Codes
2-315
intJ
If non-Buffered mode is used, the A, C, and I fields are
in memory. The software must examine the initial characters to find the extent of the address field. If Buffered
mode is used, the characters corresponding to the
SOLe A and C fields are transferred to the CPU as
interrupt results. Buffered mode assumes the two characters following the opening flag are to be transferred
as interrupt results regardless of content or meaning.
(The 8273 does not know whether it is being uSed in an
SOLe or an HOLC environment.) In SOLC, these
characters are necessarily the A and C field bytes, however in HOLC, their meaning may change depending
on the amount of extension used. The software must
recognize this and examine the transferred' results as
possible address field extensions.
2) The 8273 Status register is cleared.
3) Any commands in progress cease:
4) The 8273 ~nters an idle state until the next command
is issued.
Modem Control Commands
The modem control ports were discussed earlier in the
Hardware section. The commands used to manipulate
these ports are shown in Figure 33. The Read Port A
and Read Port B commands are immediate. The bit
definition for the returned byte is shown in Figures 13
and 14. 00 not forget that the returned value represents
the logical condition of the pin, i.e., pin active (low) =
bit set.
Frames may still be selectively received as is needed for
secondary stations. The Selective Receive command is
still used. This command qualifies a frame reception on
the first byte following the opening flag matching either
of the Al or A2 match byte parameters. While this does
not allow qualification over the complete range of
HOLC addresses, it does perform a qualification on the
first address byte. The remaining address field bytes, if
any, are then examined via software to completely qualify the frame.
The Set and Reset Port B commands are similar to the
Initialization commands in that they use a mask parameter which defines the bits to be changed. Set Port
B utilizes a logical OR mask and Reset Port B uses a
logical ANO mask. Setting a bit makes the pin active
(low). Resetting the bit deactivates the pin (high).
To help clarify the numerous timing relationships that
occur and their consequences, Figures 34 and 35 are
provided as an illustration of several typical se~uences.
It is suggested that the reader go over these diagrams
and re-read the appropriate part of the previous sections if necessary.
Once the extent of the address field is found, the following bytes form the control field. The same LSB test
used for the address field is applied to these bytes to
determine the control field extension, up to two bytes
maximum. The remaining frame bytes in memory represent the information field.
HOLC CONSIDERATIONS
The 8273 supports HOLe as well as SOLC. Let's discuss how the 8273 handles the three basic HOLC/
SOLC differences: extended addressing, extended control, and the 7 1s Abort character.
Recalling Figure 4a, HOLC supports an address fi~ld
of indefinite length. The actual amount of extenSIOn
used is determined by the least significant bit of the
characters immediately following the opening flag. If
the LSB is 0, more address field bytes follow. If the
LSB is 1, this byte is the final address field byte. Software must be used to determine this extension.
Port
A Input
B Output
The Abort character difference is handled in the Operating Mode register. If the HOLC Abort Enable bit is
set" the reception of seven contiguous ones by an active
receiver will generate an Abort Oetect interrupt rather
than eight ones. (Note that both the HOLC Abort Enable bit and the EOP Interrupt bit must not be set
simultaneously.)
Now let's move on to the SOLe loop configuration
discussion.
Command
Hex
Code
Parameter
Reg
Result
Read
22
None
Port Value
Read
23
None
Port Value
Set
A3
Set Mask
None
Reset
63
Reset Mask
None
Figure 33. Modem Control Command Summary
2-316
inter
AP·36
CARRIER DETECT
~
\'---
RxD
Rx COMMAND
t
OR~~~:~~~~~~=~: __________________________________~_A
____~t_c____t_l_l_____________________
NON·BUFFERED
t
FRAME
tPOSSIBLE
IN~~::~~~~ ___________________________________M_O_D_E____________~C~O~M~P=LE~T~E____~ID~L~E~INT
611001-25
A. Error·Free Frame Reception
CARRIER DETECT
~
\\\\\\\\\\\\
RxD
RxCOMMAND
t
CD
CD
IN~~::~~~~ ________________~~F~A~IL~U~R~E~I__~~____~~__~~____~~F~A~IL~U~R~E_____
611001-26
B. Carrier Detect Failure Dunng Frame Reception
Figure 34. Sample Receiver Timing Diagrams
LOOP CONFIGURATION
Aside from use in the normal data link applications, the
8273 is extremely attractive in loop configuration due
to the special frame-level loop commands and the Digital Phase Locked Loop. Toward this end, this section
details the hardware and software considerations when
using the 8273 in a loop application.
The loop configuration offers a simple, low-cost solution for systems with multiple stations within a small
physical location, i.e., retail stores and banks. There are
two primary reasons to consider a loop configuration.
The interconnect cost is lower for a loop over a multipoint configuration since only one twisted pair or fiber
optic cable is used. (The loop configuration does not
support the passing of distinct clock signals from station to station.) In addition, loop stations do not need
the intelligence of a multi-point station since the loop
protocol is simpler. The most difficult aspects of loop
station design are clock recovery and implementation
of one bit delay (both are handled neatly by the 8273).
Figure 36 illustrates a typical loop configuration with
one controller and two down-loop secondaries. Each
station must derive its own data timing from the received data stream. Recalling our earlier discussion of
the DPLL, notice that TxC and RxC clocks are provided by the DPLL output. The only clock required in the
secondaries is a simple, non-synchronized clock at 32
times the desired baud rate. The controller requires
both 32 X and I X clocks. (The 1X is usually implemented by dividing the 32X clock with a 5-bit divider.
However, there is no synchronism requirement between
these clocks so any convenient implementation may be
used.)
2-317.
inter
Ap·36
T.COMMAND
I
RTS~
L
L
c T S - - - -......
OR1~~:~N~:~~~:~:-------I~,A-I--!-c--I-'-l--I-'2--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
NON·BUFFERED
MODE
I
IN~~=:~~~----------------------------------~F-R-AM--E-CO-M-P-L_E_TE
611001-27
A. Error·Free Frame Transmission
2ND FRAME
I I I I I
1ST FRAME
T.COMMAND
I
"H I
RTS~
CTS~
tEARLY T.
IN~~=~~~--------------------------~--------------------------------------611001-28
B. Diagram Showing Tx Command Queing and Early Tx Interrupt
(Single flag between frames) Buffered Mode is Assumed
T. COMMAND
I.
L
1-
C T S - - - -......
T. DMA
REQUE~T8
IA
IC
1'1
t12
t13
ORDATAINTERRUPTS----------~----~--~~--~----~---------------------~---
I CTS
IN~~=~~~---------------------------------------:::O=R-:A::~~::R;.;;O"'R'--------------ERROR
INTERRUPT
c. CTS Failure (or other error) During Transmission
Figure 35. Sample Transmitter Timing Diagrams
2·318
811001-29
inter
Ap·36
If the controller wants to poll the secondaries, it transmits a polling frame followed by all Is (no zero bit
insertion). The final zero of the closing frame plus the
first seven Is form an EOP. While repeating, the secondaries monitor their incoming line for an EOP. When
an EOP is received, the secondary checks if it has any
response for the controller. If not, it simply continues
repeating. If the secondary has a response, it changes
the seventh EOP one into a zero (the one bit time of
delay allows time for this) and repeats it, forming a flag
for the down-loop stations. After this flag is transmitted, the secondary terminates its repeater function and
~nserts its response frame (with multiple preceding flags
If necessary). After the closing flag of the response, the
secondary re-enters its repeater function, repeating the
up-loop controller Is. Notice that the final zero of the
response's closing flag plus the repeated Is from the
controller form a new EOP for the next down-loop sec?ndary. This new EOP allows the next secondary t'o
Insert a response if it desires. This gives each secondary
a chance to respond.
1. LOOP
OSCILLATOR
OR
DIVIDER
RxD
RxC
TxC
8273
TxD
8273
LOOP
TxD I--+--I--.! RxD
LOOP
TERMINAL
TERMINAL
TxC
RxC
DPLL
611001-30
Figure 36. SOLe Loop Application
A quick review of loop protocol is appropriate. All
communication on the loop is controlled by the loop
controller. When the controller wishes to allow the secondaries to transmit, it sends a polling frame (the control field contains a poll code) followed by an EOP
(End-of-Poll) character. The secondaries use the EOP
character to capture the loop and insert a response
frame as will be discussed shortly.
The secondaries normally operate in the repeater mode,
retransmitting received data with one bit time of delay.
All. received frames are repeated. The secondary uses
the orie bit time of delay to capture the loop.
When the loop is idle (no frames), the controller transmits continuous flag characters. This keeps transitions
on the loop for the sake of down-loop phase locked
loops. When the controller has a non-polling frame to
transmit, it simply transmits the frame and continues to
send flags. The non-polling frame is then repeated
around the loop and the controller receives it to signify
a complete traversal of the loop. At the particular secondary addressed by the frame, the data is transferred
to memory while being repeated. Other secondaries
simply repeat it.
Back at the controller, after the polling frame has been
transmitted and the continuous Is started, the controller waits until it receives an EOP. Receiving an EOP
signifies to the controller that the original frame has
propagated around the loop followed by any responses
Inserted by the secondaries. At this point, the controller
may either send flags to idle the loop or transmit the
next frame. Let's assume that the loop is implemented
completely with the 8273s and describe the command
flows for a typical controller and secondary.
The loop controller is initialized with commands which
specify that the NRZI, Preframe Sync, Flag Stream,
and EOP Interrupt modes are set. Thus, the controller
encodes and decodes all data using NRZI format. Preframe Sync mode specifies that all transmitted frames
be prefaced with 16 line transitions. This ensures that
the minimum of 12 transitions needed by the DPLL to
lock after an all Is line has occurred by the time the
secondary sees a frame's opening flag. Setting the Flag
~tream mode starts the transmitter sending flags which
Idles the loop. And the EOP Interrupt mode specifies
that the controller processor will be interrupted whenever the active receiver sees an EOP, indicating the
completion of a poll cycle.
When the controller wishes to transmit a non-polling
frame, it simply executes a Frame Transmit command.
Since the Flag Stream mode is set, no EOP is formed
after the closing flag. When a polling frame is to be
transmitted, a General Receive command is executed
first. This enables the receiver and allows reception of
all incoming frames; namely, the original polling frame
plus any response frames inserted by the secondaries.
After the General Receive command, the frame is
transmitted with a Frame Transmit command. When
the frame is complete, a transmitter interrupt is gener-
2-319
Ap·36
ated. The loop controller processor uses this interrupt
to reset Flag Stream .mode. This causes the transmitter
to start sending all Is. An EOP is formed by the last
. flag and the first 7 1s. This completes the loop controller transmit sequence.
At any time following the start of the polling frame
transmission the loop controller receiver will start receiving frames. (The exact time difference depends, of
course, on the number of down-loop secondaries due to
each inserting one bit time of delay.) The first receiv,ed
frame is simply the original polling frame. However,
any additional frames are those inserted by the secondaries. The loop controller processor knows all frames
have been received when it sees an EOP Interrupt. This
interrupt is generated by the 8273 since the EOP Interrupt mode was set during initialization. At this point,
the transmitter may be commanded either to enter Flag
Stream mode, idling the loop, or to transmit the next
frame. A flowchart of this sequence is shown in Figure
37.
o
The secondaries are initialized with the NRZI and One
Bit Delay modes set. This puts the 8273 into the repeat.
er mode with the transmitter repeating the received
data with one bit time of delay. Since a loop station
cannot transmit until it sees an EOP character, any
transmit command is queued until an EOP.is received.
Thus whenever the secondary wishes to transmit a response, a Loop Transmit command is issued. The 8273
then waits until it receives an EOP. At this point, the
receiver changes the EOP into a flag, repeats it, resets
One Bit Delay mode stopping the repeater function,
and sets the transmitter into Flag Stream mode. This
captures the loop. The transmitter now inserts its mes~
sage. At the closing flag, Flag Stream mode is reset, and
One Bit Delay mode is set, returning the 8273 to re.peater function and forming an EOP for the next downloop station. These actions happen automatically after a
Loop Transmit command is issued.
When the secondary wants its receiver enabled, a Selective Loop Receive command is issued. The receiver
then looks for a frame having a match in the Address
.field. Once such a frame is received, repeated, and
transferred to memory, the secondary's processor is interrupted with the appropriate Match interrupt result
and the 8273 continues with the repeater funqtion until
an EOP is received, at which point the loop is captured
as above. The processor should use the interrupt to determine if it has a message for the controller. If it does,
it simply issues a Loop Transmit command and things
progress as above. If the processor has no message, the
software must reset the Flag Stream mode bit in the
Operating Mode register. This will inhibit the 8273
from capturing the loop at the EOP; (The match frame
and the EOP may be separated in tfme by ·several
frames depending on how many \Ip-loop·stationsinserted messages of their own.) If the timing is such that the
receiver has already captured the loop when the Flag
Stream mode bit is reset, the mode is exited on a flag
boundary and the frame just appears to have extra closing flags before the EOP. Notice that the 8273 hand~es
the queuing of the transmit commands and the setting
and resetting of the mode bits automatically. Figure 38
illustrates the major p6ints of the secondary command
sequence.
DENOTES COMMAND
c::) DENOTES INTERRUPT CO.DE
611001-31
Figure 37. Loop Controller Flowchart
2-320
AP-36
It is hopefully evident from the above discussion that
the 8273 offers a very simple and easy to implement
solution for designing loop stations whether they are
controllers or down-loop secondaries.
INITIALIZE SET NAZI. ONE
81T DELAY MODES
Ra0l------~-----_UP·LOOP
DATA
8273
TaO
PORT
1---+'----1",
DOWN·LOOP DATA
1----4--r._~
611001-33
Figure 39. Loop Interface
APPLICATION EXAMPLE
o
DENOTES COMMANDS
C ) DENOTES INTERRUPT CODES
611001-32
Figure 38. Loop Secondary Flowchart
When an off-line secondary wishes to come on-line, it
must do so in a manner which does not disturb data on
the loop. Figure 39 shows a typical hardware interface.
The line labeled Port could be one of the 8273 Port B
outputs and is assumed to be high (I) initially. Thus uploop data is simply passed down-loop with no delay;
however, the receiver may still monitor data on the
loop. To come on-line, the secondary is initialized with
only the EOP Interrupt mode set. The up-loop data is
then monitored until an EOP occurs. At this point, the
secondary's CPU is interrupted with an EOP interrupt.
This signals the CPU to set One Bit Delay mode in the
8273 and then to set Port low (active). These actions
switch the secondary's one bit delay into the loop. Since
after the EOP only Is are traversing the loop, no loop
disturbance occurs. The secondary now waits for the
next EOP, captures the loop, and inserts a "new online" message. This signals the controller that a new
secondary exists and must be acknowledged. After the
secondary receives its acknowledgement, the normal
command flow is used.
2-321
This section describes the hardware and software of the
8273/8085 system used to venfy th~ 8273 implementation of SDLC on an actual IBM SDLC Link. This IBM
link was gratefully volunteered by Raytheon Data Systems in Norwood, Mass. and I wish to thank them for
their generous cooperation. The IBM system consisted.
of a 370 Mainframe, a 3705 Communications Processor, and a 3271 Terminal Controller. A Comlink II
Modem supplied the modem interface and all communications took place at 4800 baud. In addition to observing correct responses, a Spectron D60lB Datascope
was used to verify the data exchanges. A block diagram
of the system is shown in Figure 40. The actual verification was accomplished by the 8273 system receiving
and responding to polls from the 3705. This method
was used on both point-to-point and multi-point configurations. No attempt was made to implement any higher protocol software over that of the poll and poll
responses since such software would not affect the verification of the 8273 implementation. As testimony to
the ease of use of the 8273, the system worked on the
first try.
370
MAINFRAME
3705
COMM
PROCESSOR
611001-34
Figure 40. Raytheon Block Diagram
An SDK-85 (System Design Kit) was used as the core
8085 system. This system provides up to 4K bytes of
ROM/EPROM, 512 bytes of RAM, 76 1/0 pins, plus
Ap·36
two timers as provided in two 8755 Combination
EPROM/I/O devices and two 8155 Combination
RAM/I/O/Timer devices. In addition, 5. interrupt inputs are supplied on the 8085. The address, data,and
control buses are buffered by the 8212 and 8216 latches
and bidirectional bus drivers. Although it was not used
in this application, an 8279 Display Driver/Keyboard
Encoder is iIicluded to interface the on-board display
and keyboard. A block diagram of the SDK-85 is
shown in Figure 41. The 8273 and associated circuitry
was constructed on the ample wire-wrap area provided
for the user.
The example 8237/8085 system is interrupt-driven and
uses DMA for all data transfers supervised by an 8257
DMA Controller. A 2400 baud asynchronous line, implemented with an 8251A USART, provides communication between the software and the user. 8253 Programmable Interval Timer is used to supply the baud
rate clocks for the 8251A and 8273. (The 8273 baud
rate clocks were used only during initial system debug.
In actual operation, the modem supplied these clocks
via the RS-232 interface.) Two 2142 lK x 4 RAMs
provided 512 bytes of transmitter and 512 bytes of receiver buffer memory. (Command and result buffers,
plus miscellaneous variables are stored in the 8155s.)
The RS-232 interface utilized MC1488 and MC1489
RS-232 drivers and receivers. The schematic of the system is shown in Figure 42:'
One detail to note is the DMA. and interrupt structure
of the transmit and receive channels. In both cases, the
receiver is always given the higher priority (8257 DMA
channel 0 has priority over the remaining channels and
the 8085 RST 7.5 interrupt input has priority over the
RST 6.5 input.) Although the choice is arbitrary, this
technique minimizes the chance that received data
could be lost due to other processor or DMA commitments.
Also note that only one 8205 Decoder is used for both
peripheral and memory Chip Select. This was done to
eliminate separate memory and I/O decoders since it
was known beforehand that neither address space
would be completely filled.
The 4 MHz crystal and 8224 Clock Generator were
used only to verify that the 8273 operates correctly at
that maximum spec speed. In a normal system, the
3.072 MHz clock from the 8085 would be sufficient.
(This fact was verified during initial checkout.)
2-322
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611001-46
2·330
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; 8251A EUTES
;
CNTLSl EQU
99H
.: CONTROL WORD REGISTER
STAT51 EQU
8911
; STATUS REGISTER
11(1)51 ElIU
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; TX DATA REGISTER
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611001-48
2-332
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611001-49
2-333
inter
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611001-50
2-334
AP-36
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8EC5
8975 COE58A
8978 C357118
89n
8978
8970
897F
8982
8681
8E64
COE58A
C35788
9985 11681
89878EA4
8989 CDE58A
898C C35788
898f
8991
8993
8996
8684
8EC2
CDE58A
C35788
373 ,TRfINSI11 T ANSWER TO POLL SETIJ'
374382 TXI'll. "YI
A,aeH
,CLEAR I'll.L 1~ICATtR
384
STA
POLIN
, lHOlCATtR fI)R
385
LXI
H, LOOPlT
; SETUP STACI( FtR OJIIHI MPUT
386
PUSH
H
; PUT RETlRH TO Cll)R£C IJI STACK
B,84H
387
~l
,G£T • OF PfIRfI£TERS Rm>Y
H, CIIl8F1
388
LXI
; POINT TO SPECIAL BlFFER
C(ftf2
389
JItP
,JltIP TO C~ IXJTPUTER
398 ,
391 ,
392 ;
393 ,COItItfINI) IIlPLEllEHTlNG RIXJTlHES
394 ;
395 ,
396 ; RO - RESET OPERATING PIOO€
397 ,
,. OF PARAl£TERS
398 ROCI1D ~l
B,8tH
C,5tH
399
~l
•CCfIIIIH)
488
CALL
COllI
•G£T PARAl£TERS RHO ISSl( CCfIIIIH)
,G£T
NEXT CCfIIIIH)
481
JItP
CItlREC
482 ;
483 ,RS - RESET SERIAL 1/0 I«lD£ CI»IIfii)
4&4 ;
B,8tH
,I OF PARftl£TERS
485 R500 ~l
;CatIfN)
486,
C,68H
~l
C(JIII
,G£T PARfI£TERS RHO ISSl( catIfN)
487
CALL
488
J~
CIIlREC
· GET NEXT OJIIHI
489 ,
418 ,RO - RECElYER DISABLE COIIPIfH)
4U,
,. OF PARfI£TERS
B,88H
412 ROOO ~l
, COIIIRI)
C,8C5H
413
~I
C(JIII
.1551..( C!»IIIAHO
414
CALL
415
CIIlREC
,G£T NEXT OJIIHI
JItP
416 ,
417 ,RB - RESET IJIE BIT DELAY catIfN)
418 ,
,. OF PfIRfI£TERS
a,91H
419 RBC!1D' ~l
, COIIIAHO
C,64H
428
"YI
421
,G£T PARfl£TER·RHO ISSl( CCfIIIIH)
CALL
COllI
422
; G£T NEXT catIfN)
JItP
OOREC
423 ,
424 ; 58 - SET ONE BIT DELAY COItIAN>
425,
,. OF PARfI£TERS
B,81H
426 5BOO ~l
C,8A4H
427
; COIIIAHO
~l
,G£T PARfI£TER RHO 1551..( catIfN)
428
CALL
COllI
,G£T NEXT COIIIAHO
429
JHP
OOREC
438 ,
431 ,SL - SELECTIYE LOOP RECEIYE COII!ANO
432 ;
,. OF PARfIIETERES
a,84H
433 SLOO ~l
C,8C2H
; COIIIAHO
434
~l
; GET PfIRfI£TER5 RHO ISSl( OJIIHI
435
CALL
COllI
,G£T NEXT COIIIAHO
436
J~
OOREC
437 ,
438 ; TL - TRAHSIIIT LOOP C!J1IIlHI)
2-335
611001-51
inter
AP-36
439 '
8999
899C
999£
89R8
89A3
218829
8682
36CR
219228
C3F6i!9
i!9A6
89A8
09AA
89AO
8681
8E91
CDE58A
C35788
8988
i!992
0984
8987
8681
8EA8
CDE58A
C35788
89BR
I!9BC
89BE
09C1
8684
8EC1
CDE58A
C35788
H, CItlIlLF
,SET COItIfN) BlFFER POINTER
TL~' LXI
g, Il2H
,LOllI) PfIRfIItETER CruNTER
441
KYI
,LOllI) CMRf) INTO BlFFER
~YI
442
",1iC/IH
H, CIIlBtIF+2
,POINT AT FI)II AN> CNTl POSITI(16
443
LXI
,FINISI! (FF ctWIfN) IN TF ROOTitE
444
JIfP
TFC~
445,
446 ; SO - SET OPERATING I'IOOE COIIIBI)
447 ;
B,8lH
+18 SOCIll.l' IIYI
•• OF PARAI£fERS
;CMIH)
C,9lH
449
IIYI
; IE PfRI1ETER AN> 1SSl( mtIIfI)
CALL
458
C~
,IE NEXT COItRf)
451
JIfP
C~C
452 ,
453 ; 55 - SET SERiAl 1/0 COllIN)
454 ;
;. OF PARAlETERS
B,81H
455 SS~ IIYI
C, IlA8H
456
IIYI
• COItIfN)
, IE PfRI1ETER AN> 1551£ COllIN)
457
CAll
C~
,IE tEXT COllIN)
458
JIfP
~C
459 ;
468 ,~ - SELECTIYE RECEIVE COllIN)
461 ;
,. OF PARAIETERS
B,84H
462 ~I'ID "YI
.C(JMI)
C,0ClH
IIYI
463
, IE PfM£TERS AN> ISSl( COllIN)
464
CAll
COIIM
,GET NEXT CQfM)
465
JIfP
CItlREC
+18
466 ;
i!9C4
89C6
89C0
i!9C8
8682
8ECB
CDE58A
C35788
i!9CE
I!9D9
8902
9!lO5
8680
8ECC
CDE58A
C35788
9!lOB
i!9OA
9!lOC
890F
8681
8E63
CDE58A
C35798
09E2
89E4
09E6
09E9
8681
8EA3
CDE5BR
C3578B
467 ; IJ! - GENERAl. RECEIVE COllIN)
468 ;
8,Q2H
469 1JIC1II.l: IIYI
C,0C8H
478
IIYI
471
CAll
C~
472
JIfP
~C
473 ,
474 ,AF - R80RT FRfII£ CIJIMI)
475 ,
B,1l8II
476 AF~. IIYI
C,8CCH
477
IIYI
478
COM
CAlI.
479
JIfP
CI10REC
488 ,
481 ,RP - RESET PORT COI1IflNI)
482 ,
483 RPCI1I) IIYI
B.8lH
C,63H
4B4
"VI
4B5
COIIM
CALL
4B6
JIfP
CIIllREC
487.
488 ,5P - SET PORT COIIM)
; NO PARAI£fERS
, COItRf)
, ISSUE CMIH)
• GET NEXT COllIN)
; NO PfM£TERS
; COItIfN)
,I5SUE COllIN)
,GET NEXT CMRf)
;. OF PfIRAIETEAS
;~
,IE PfIRfIItETER AN> ISSUE
; IE NEXT COItRf)
COllIN)
4i!9 ;
498
491
492
493
494
495
496
SPCt1D
IIYI
IIYI
CALL
JIfP
·B,.8lH
C,BASH
COM
OOREC
,
, TF - TRfIISIIIT FRfII£
,
,. OF PARAIETERS
; COItIfN)
; IE PfIRfIItETER AN> ISSUE
•IE HEX COllIN)
mtIIfI)
COItRf)
611001-52
2-336
inter
AP-36
89EC
89EF
89F1
89Fl
89F6
89F7
89F8
89FB
89FE
IIA81
218920
8682
l6C8
218228
78
A7
CAe78A
CDA08A
DAA788
21
8A82 85
8118l 77
8A84 ClF~
81187 218888
8A8A 810888
8A8O C5
8A8E CDA08A
8A11 DA1B8A
8A14 77
8A15 2l
8A16 C1
8A178l
8A18 CleoeA
8A1B FE80
8A1D CA248A
8A28 C1
8A21 ClA788
iIA24 C1
8A25 219129
8A28 71
8A29 21
8A2A 78
8A28 8684
8A2D 21368A
8fll8 C5
8fll1 El
BAl2 C5
BAll ClF88A
BAl6 C35788
BA39 1685
8A38 2A1128
8fllE E5
8AlF 7E
8A48
8A42
8A44
8A47
8A4A
8A4I)
E61F
FEBe
DA628A
21C38C
CD928C
E1
8A4E 7E
8A4F COC786
497 TFoo. LXI
H,OOIIU'
,SET ctWfN) BlFFER POINTER
498
!WI
8,eat
,L(8) PARAIETER COONTER
499
!WI
; LOfI) COIIINI) INTO BlFFER
",8C8H
5Il8
LXI
IHII)IIUf+2
,POINT AT ~ fill) CNTl POSITIONS
581 TFOO1' I10Y
A,8
. TEST PARAIETER COOO
582
AIfI
A
·15 IT 8'
58l
•YES, L(8) TX DATA BlFFER
12
TBlR.
5e4
CALL
PARIN
;GETPARII£TER
585
JC
ILLEG
,ILLEGfl. ~ RETIR£D
586
INX
H
, IN: COIMI) BlFFER POINTER
587
OCR
,DEC PARII£TER CIOTER
8
588
ftIlII
; L(8) PARAl£TER INTO CMfIN) BlfFER
",A
5e9
./If'
TFoo1
,GET NEXT PARAl£TER
518
H, TlIBIJF
511 TBlR.' LXI
; LOfI) TX DATA BlfFER POINTER
512
LXI
8,888!IH
,CLEAR Be - BYTE cruITER
513 TBlR.1 PUSH
,SAYE
8YTE COONTER
8
514
CALL
PARIN
,GET DATA. fl.IAS PARII£TER
00CIf(
515
JC
; IIMIE 00 IF ILLEGfl.
516
; L(8) DATA BYTE INTO 8IJ'FER
ftIlII
",A
517
INX
H
,INC 8lFFER POINTER
518
POP
8
; RESTORE BYTE CIOTER
519
INX
8
, IN: BYTE cruITER
,GET
P£XT DATA
528
!lIP
TBlJFLl
521 00CfI(' CPI
CR
; RETm£1) ILLEGfl. ~ CR'
522
J2
,YES, THEN TX BlFFER Fill
T8UFFl
523
POP
8
,RESTORE 8 TO SAVE STfO:
524
ILLEG
; ILLEGfl. C~ .
./If'
525 T8UFFl POP
8
,RESTORE 8YTE COOOER
H, CIll8UF+1
,POINT INTO COIMI) BlfFER
526
LXI
527
ftO~
; STORE BYTE COOO LSS
", C
528
INX
,INC POINTER
H
529
I10Y
; STORE BYTE COOO ftSS
",8
8,84H
518
!WI
,L(8) PARfII£TER ClOT INTO 8
H, TFRET
531
LXI
; GET RETlI1N ~ FOR THIS ROUTII£
,PUSH OI£E
512
PUSH
B
513
XTIIL
; PUT RETLRH ON STACK
534
PUSH
8
,PUSH IT SO OOOOT CAN USE IT
, 15S1£ CIJIIIfH)
515
./If'
OOOUT
,GET P£XT CMfIN)
516 TFRET. JftP
CItOREC
537 '
538 ,
539 ,ROOTlP£ TO DISI'LAV RESULT IN RESUlT 8lFFER III£N L(8) fill) CtJISOLE
548 ,POINTERS ARE DIFFERENT
541 ,
542;
543 DISPY "~I
D,85H
,D IS RESULT CIUTER
544
LlLD
,GET CtJISOLE POINTER
CNADR
,SAYE IT
545
PUSH
H
A,ft
546
ftO~
,GET RESUlT Ie
547
ANI
,L1ftlT TO RESUl.T COOE .
1FH
548
CPI
, TEST IF RX OR TX SOlI!CE
8CH
,CARRY, TI£N AX SOlI!CE.
549
Ie
RXSORC
H, TXIftSG
558 TXSORC LXI
,TX INT I£SSAGE
551
Cfl.L
,DISPLAY IT
T'IIISG
,RESTORE ClJIS(l.£ POINTER
552 DISPY2 POP
H
A,ft
553 DISPY1 I10Y
,GET RESUl.T
,mNERT fill) DISI'LAV
554
Cfl.L
rfIOlIT
611001-53
2-337
inter
AP-36
559
JNZ
C} I I
ECIIO
L
D
DISPY1
IlASC 221129
569
SHlI)
CfR)R
9A5F C35798
561
JIf>
OOREC
562,
563,
564 ,RECEIYER SOORCE - DISPlAY RESIA. TS
8A52
0fI54
1lAS7
1lAS8
9fI59
eE29
CDF91i5
2C
15
C24E9A
555
5S6
557
/WI
Cfl.L
558
OCR
I~
;SP~
; DISPlAY IT
, II«: BtFFEl! POINTER
,DEC RESIA.T COOflER
,f«)T DOlE
,UPDATE ctJt5OI.E"" POINTER
,REMN TO LIU'
All)
RECEVIE BtFFEl! mfTENTS
565 ,
566;
81162 21889C
8A65 come
8A68 E1
81169 7E
8A6A COC786
8A6O 9E29
9A6F
9A72
9A73
9A74
9A7S
9A77
9A7A
COF885
2C
15
7ft
FE94
CAA29A
FE93
567 RXSORC: LXI
H,RXI~
569
569
TYIISG
H
A,"
IfWT
578 RXS1:
571
572
POP
IKlY
CALl
IIYI
573
CALl
574
575
576
I~
577
578
579
9A7C CAA79A
see
9A7F A7
S81 RXS2"
IlA8Il C2699A
9A83221329
S82
9A86 CDE89S
9A89 219982
9R8C C1
9fI8() 7B
9A8E 81
CALl
S83
S84
S8S
S86
S97 RXS3"
DCA
/lOY
Cl'1
JZ
Cl'1
JZ
fIfI
JNZ
SIlO
CALl
LXI
see
POP
/lOY
ORA
9A8F CR5798
S89
JZ
9A92
9A93
9A94
9A97
9A99
9A9C
S99
591
592
593
594
/lOY
PUSH
Cfl.L
IIY!
CALL
POP
7E
C5
CDC786
eE2Il
COF885
C1
9A9D 98
9A9E 23
9A9F C3809A
9AR2 4E
9AA3 C5
9AA4 C37F9A
9AA7 C1
9AAB 46
9AA9 C5
9AAR C37F9A
59S
596
597
S99
599
698 R9PT
691
692
683
684 RifT:
695
ocx
INX
JIfI
~y
PUSH
JIfI
POP
lIlY
686
PUSH
687
698
689
619
JIfI
e,'
I
'
ECIIO
L
D
A,D
94H
R9PT
9lH
RifT
R
RXS1
CfR)R
CRLF
H,RXIllf
8
"A,S
C
CIIlREC
A,"
8
IfWT
,RX INT I£SSRGE fI)R
; OISl'lAY I£SSRGE
; RES11JiE ctJt5OI.E POINTER
; RETRIE'IE RESIA.T FR(JI BtFFEl!
; caNERT All) DISPlAY IT
; ASCII 51'
;DISl'LAY IT
,II«: CONSOLE POINTER
; DEC RESIA.T C5
8AD6
8AD7
8AD8
8AD9
8ADC
8AOO
8ADE
8ADF
8AEe
8AE1
8AE2
8AE3
C5
1681
CD1FI!6
CDFBB5
79
FE28
C2E88A
CD1F1!6
CDF885
CD5E87
D2E88A
CDBB85
4F
7A
A7
CAOC8A
15
AF
79
17
17
17
17
SF
C38C8A
79
B3
C1
C9
79
37
C1
C9
613 ;
614 PIlRIN'
615
616
617
619
619
628
621 PIlRIN3.
622
623
624
625
626
627
628
629
638
631
632
633
PUSH
"VI
CA..L
CAlL
/tOY
CPI
B
D,91H
GETCH
ECI«)
A,C
JHZ
PIlRlNi
GETCH
EOO
I/fl.OO
PIlRlNi
CAll
CAlL
CA..L
.oc
CAll
/tOY
/tOY
ANA
J2
OCR
~
/tOY
RAl.
CHYIIN
C,A
A,D
A
PARIN2
D
A
A.C
634
RAl
635
RAt.
636
RAl
637
/tOY
E.R
638
~
PIlRIN3
fl,C
639 PARIN2. IIOY
648
ORA
E
641
POP
B
642
RET
A,C
643 PARIN1: /tOY
644
5TC
POP
645
646
RET
647,
648 '
649 ,JlJI' HERE IF BUFFER FlJl.L
,5A'IE BC
'SET Cft! ro.JlTER
,GET Cft!
,EOO IT
,PUT CfR IN A
;SP"
; 1«), lUEGfl., TRY AGAIN
,GET CfR OF PARMTER
,ECt«l IT
,15 IT A I/fl.ID CIF'
.' 1«), TRY AGRIN
,C3NERT IT TO HEX
; 5A'IE IT IN C
,GET Cft! ro.JlTER
015 IT Ir'
; YEs, OM WIlli 11115 PIlRRI£TER
,DEC CfR COOOER
; CLEAR CII1RY
; RECIMR 1ST CfR
,I1OTATE lEFT 4 PlACES
,SAVE IT IN E
,GET NEXT eft!
,2I«lCfRINA
,COIIBlNE BOlli CfR5
;RESTORE BC
,RETURN TO CA..LING ~
,PUT ILLEGAl. CfR IN A
,SET CII1RY AS lUEGfl. STATUS
,RESTORE BC
,RETURN TO CAlliNG PROGRfII
6S8 ,
8AE4 CF
8AE5
8AEB
8AE9
8AEA
218829
C5
71
78
8AEB A7
8AEC CAFB8A
IIAEF
COfI)8A
8AF2 DAA78Il
8AF5 23
1lAF6115
1lAF7 77
1lAF8 C3EIIIlA
IlAFB 218829
8AFE C1
651BUFFUL DB
ecFH
652 ,
653 ,
654 ,CIlIIftI) DISPATCHER
655 ,
656 ,
H, CIIDBUF
657 CMI
LXI
6S8
B
PUSH
659
/tOY
ItC
A,S
66B COIIU. /tOY
661
ANA
A
J2
662
CItlOOT
PIlRIN
663
CAll
664
JC
IllEG
H
INX
665
666
OCR
B
667
/tOY
itA
J~
668
COIIU.
H, CIIDBUF
669 CItlOOT: LXI
678
POP
B
,EXIT TO
~IT(J!
; SET POINTER
,SAVE BC
,LOAD ClIttH) INTO BlFFER
; CNECI< PIlRRI£TER cruITER
,IS IT 8?
.' YES, GO ISSlE COIfH)
;GET ~TER
,IllEGAl CfR REMI£D
, INC BlFFER POINTER
,DEC PIlRfIIETER ro.JlTER
,PARfI£TER TO BU'FER
,GET NEXT PIlRfIIETER
; REI'OINT POINTER
; RESTORE PIlRII£1ER ClUff
2-339
611001-55
inter
AP-36
9fIFf D898
Il881 87
8882 Dfl'FeR
eB85
l1li86
91188
8889
8II8R
eses
9II8C
Il8IlO
I!88f
8811
8814
8815
1!817
7E
D398
18
A7
C8
23
85
D898
E6Z8
C28D8B
7E
D391
C38SIl8
881R 3E62
881C D3R8
I!81E 818882
81121 79
8822 D3R8
8824 18
8825 D3R8
882781FF41
882R 79
882B D3A1
882D 18
882E D3R1
8838 3E63
8832 D3A8
8834 C9
8835 3E61
8837 D3A8
8839 818888
883C 79
883D D3R2
883F 18
8848 D3R2
884281FF81
11845 79
1!846 D3R3
8848 18
8849 D3R3
884B 3E63
884D D3R8
884F C9
,1l£RI) 8273 STATUS
STAm
671 CCJ1112 IN
,ROTATE CBS\' INTO CARRY
672
RlC
,WRlT F~ 01(
67l
JC
COIIl2
,01(, IIO'fE COllIN) INTO A
674
IIOY
It"
,OOTI'UT CIJIRI)
675
OUT
COIIIm
A,B
,GET PfIlRI£TER CMT
676 P1Il1' !lOY
;IS lT 8?
AHA
677
A
,YES, J)(J£, RETURN
618
RZ
, INC CIJIRI) BlIFFER POINTER
679
INX
H
,DEC PfIlRI£TER CMT
DC~
68e
B
,REAl) STATUS
681 PRR2' IN
STRm
,IS CPSF BIT SET?
ANI
CPSF
682
,WRlT TIL ITS 8
683
1HZ
PRR2
,01(, GET PfIlfII£TER ~ BlfFER
!lOY
684
A,"
,OOTI'UT PfIlAI£TER
685
ruT
~3
,GET
t£lIT PfIlfIETER
JIf'
PIIll
686
687,
68e ,
689 ,I NITI AL IZE AND ENRIII.E RX DIfI CHAIf£\.
698 ,
691,
A,DRDM
,DISRBLE RX DIll CIRf£L
692 RXDIIA. ~I
OUT
: 8257 !lODE ~T
693
IIODE57
B, RlQ3IS
,RX BlfFER STIllT fIlDRESS
694
LXI
!lOy
A,C
,RX BlfFER LS8
695
CH8A)R
.CH8 fI)R ~T
696
OUT
,RX BlIFFER IIS8
697
!lOY
ItS
.CH8 fI)R ~T
698
OUT
CH9RDR
B, RXTC
,RX CH TEERIUIfIL CMT
699
LXI
A,C
,RX ~INRL COOHT LSB
788
!lOY
,CH8 TC ~
7e1
OUT
CH8TC
,RX ~1IR. CMT IIS8
782
!lOY
!l.B
,CH8 TC ~T
183
OUT
CHeTC
,ENRIII.E DIll IOID
!l.EIIlIIA
784
~I
,8257 !lODE ~T
7e5
OUT
IIODE57
,RETURN
786
RET
7e7 ,
788 :
7e9 ,INITIALIZE AND ENABlE TX DIIR CIRf£L
718,
711 ,
A,DTllIft
,DISABLE TX DIll CIRf£l.
712 TXDIfR: ~I
,8257 !lODE PtI!T
713
OUT
IIODE57
,TX BlfFER STIllT fIlDRESS
B, TXBlF
714
LXI
,TX BlIFFER LS8
715
ItC
!lOY
,CNl
fI)R ~T
716
OUT
CH1IIlR
A,B
717
!lOY
TX BlIFFER IIS8
CH1fI)R
CHi fI)R ~T
718
OUT
B, mc
719 TXOIIIlI.: LXI
TX CH ~IIft. CMT
TX ~11ft. CMT LS8
728
!lOY
A.C
CHi TC ~T
ruT
CHiTC
721
722'
TX ~tlft. CMT IIS8
!lOY
ItB
CHiTC
CHi TC PORT
723
ruT
724
~I
Fl.EHIlIIl
EIftll.£ DIll 1m>
725
OUT
IIODE57
8257 !lODE ~T
RET
RETURN
726
727,
728 ,
611001-56
2·340
intJ
AP-36
IICa8
ecae ES
I!C91 FS
9(92 C5
1lCIl3 D5
Ia4 lE62
9C86 D3A8
IlCIl8 lEiS
BCeA 39
IlCIl8 1604
BCIIO 2A1829
BC19 ES
8C11 ES
9C12 45
BC13 2R1328
BC16 94
BC17 78
BCIS BD
BC19 CAE48A
BCIC 15
BC1D C2169C
IlC29 1685
9C22 E1
9C23 DB99
9C25 E698
BC27 CA399C
8C2A DB99
BC2C E692
BC2E CA239C
9C31 0893
BC33 77
BC342C
BC3S 15
BC36 C3239C
BC397A
BC3A A7
BC39 CA4S9C
BClE 3688
9(49 2C
BC4ll5
BC42 C3399C
BC45221828
9C49 3A1528
BC49 FE2D
9C4D CA85IIC
729 'INERRUPT PROCESSING SECTION
i'38 ;
nt
ORG
1lCIl9H
m·
733,
734 ,RECEIVER INTERRIJ'T - RST 7 5
735 ;
i'36 RXI'
PUSH
H
PUSH
PSII
m
PUSH
B
i'38
m
PUSH
D
749
R. DRI>III
"VI
10)£57
741
OUT
742
~I
R.19H
743
51"
D,84H
744
~I
LDfI)R
745
LHLD
746
PUSH
H
747
PUSH
H
B,L
749
lIllY
749
LHLD
CIR>R
759 RXI1
IItt
B
751
lIllY
R.B
CPI'
752
L
12
BUFF\I.
753
7S4
D
OCR
7SS
JNZ
RXI1
D, Il5H
~I
756
757
POP
H
758 RXI2
IN
STAm
759
ANI
RXINT
RXI3
769
12
761
IN
STAm
762
ANI
RXIRA
763
JZ
RXI2
764
IN
RXIR73
II. A
765
lIllY
766
IItt
L
767
OCR
D
769
JPI'
RXI2
R.D
769 RXI3
PlOY
778
ANA
A
771
12
RXI4
m
m
~I
1I.89H
IItt
OCR
L
D
RXI3
LDADR
",",T
774
775
776 RXI4.
SHLD
m
LDA
CPI
JZ
m
m
]PI'
'-'
RXI6
(LOC 3tH)
,SIIYE HL
,SIIYE PSII
,SAYE Be
,SAYE DE
; DISIIlLE RX DIll
; B2S7 10)£ PIJ!T
,RESET RST7 5 FIf
;D IS RESllT C(U(TER
; GET LOll) POINTER
,SIIYE IT
; SIIYE IT ~IN
,SIIYE LSB
,GET CONSIlE POINTER
; BlIf' LOll) POINTER LSB
. GET SET TO TEST
; LlR)=ctJISOI.E?
; YES, BlfFER Fill
;DEC crunER
; NOT DONE, TRY ~IN
,RESET COUNTER
,RESTIJ!E LOll) POINTER
,REfI) STftTUS
, TEST RX INT BIT
,DONE, GO FINISH IJ'
; REfI) STATUS ~IN
; IS RESllT REfI)Y?
; NO, TEST ~IN
; YES, REfI) RESllT
,STORE IN BlfFER
, INC BlfFER POINTER
.' DEC cronER
,GET ~ RESllTS
,GET SET TO TEST
,ALL RESllTS?
,YES, SO FINISH IJ'
,Nfl, LOll) 8 TIL DONE
,BUPI' POINTER
,DEC COUNTER
;GO ~IN
; LFDATE LOll) POINTER
. GET 10)£ INDICATIJ!
,IDIR. IO)£?
,YES, CLEAN IJ' BEFORE RETlI!N
788 ,
781 ,
782 ,
783 ;
POLL 10)£ SO CHEI)(. COHTRI1 8YTE
IF COHTRIl. IS A POLL.. SET IJ' SPECIAL TX
AND RETURN WITH POLL INDICATIJ! NOT 8
rotRI)
IIIFFER
784 ;
BC58 E1
9C51 7E
785
786
POP
PlOY
H
A,"
; GET PREYIru5 LOll) ADR POINTER
,GET Ie BYTE FR~ BlFFER
2-341
611001-57
inter
AP-36
BCS2 E61E
8CS4 C2898C
~7 2C
8C58 2C
8CS92C
IIC5A 56
8CSIl 2C
8CSC 7E
8CSD FE91
BCSF CA6C8C
8C62 FEU
8C64 C2S98C
8C67 1£11
8C69 Cl6EBC
8C6C 1E73
8C6E 212828
8C71 l6C8
BC73 21
BC74 l688
BC7623
BC77 l688
BC79 21
BC7A 72
BC78 21
BC7C n
BC70 lE81
BC7F l2162S
8C82 Cl898C
8C8S E1
8C86 Cl898C
8C89 C01A8B
ecac D1
8C8O
8C8E
8C8F
8C98
BC91
8C92
Cl
Fl
E1
FB
C9
cs
BC93 7E
BC9421
BC9S FEFF
BC97 CAA1BC
BC9fI 4F
BC9B CIlF&85
BC9E C3938C
8CR1 Cl
8CA2 C9
787
78B
789
798
791
ANI
JN2
INl
INl
INR
m
IIOY
793
794
79S
796
797
7ge
INl
IIOY
CPI
J2
CPI
JN2
ttYI
m
888
B81 T1.
882 TXRET·
886
888
889
818
811
JIf'
812
ttYl
LXI
ttYl
INX
PlYI
INX
PI'II
INX
BU
IIOY
814
815
816
817
818
819
828 RXI6·
821
822
II2l RXIS·
824
825
826
827
82S
829
818
831
812
833
834
8lS
836
837
818
POP
mP
CfLl
POP
POP
POP
POP
EI
RET
;
;
; I£SSIlGE TYPER
;
;
TYI!SG: PUSH
rntSG2. lIllY
INX
CPI
839
848
841
842
843 TYI!SG1.
844
INX
NOY
PlYI
STA
mP
12
IIOY
CAll
mP
POP
RET
1EH
RXIS
L
L
L
D,"
L
; LOO8Fl
1t8CSH
H
".88M
H
".88M
H
".0
H
".E
fl.81H
POliN
RXI5
H
RXI5
~
0
B
PSW
H
; GET RDR BYTE
fIIf)
SAYE IT IN 0
•RETURN
• CLEAN IF STRCI( IF IQIR. !OlE
; RETIJRN
; RESET ~ CIIN£I.
• RESTORE REGISTERS
; EIftI.£ INTERRtfTS
;RET\Rl
- ASSIJIES I£SSIIGE STlIHS AT Hl
B
A."
H
IiFFH
TYI!SG1
C,A
EOO
rntSG2
B
SAYE Be
GET ASCII CHR
INC POINTER
STOP?
YES, GET SET FOR EXIT
SET IF FOR DISPI.AY
01SPI.AY CHR
GET NEXT CHR
RESTORE Be
~
845
846
847 SIGHON I£SSIIGE
848
611001-58
2-342
inter
AP-36
OCR3 eo
IICR4 38323733
OCR8 284D4F4E
8CfIC 49544F52
ecse 28285631
0C84 2E31
8CB6 eo
1IC87 FF
IIC88 91>
IIC89 52582849
8C8O 4E54282D
849 SIGH\)j 011
CR, '8273
Pl(JjIT~
Yl 1', CR, IIfFH
85Il
851
852
853
854
855
856
;
.
,
,RECEIYER IHTERRtI'T I£SSfWlES
,
;
R~ltISG 011
CR,'~ INT - ',1IfFH
857
85Il
859
868
,
; TRANSIIITTER IHTERRtI'T I£SSfWlES
8CC1 28
8CC2 FF
OCC3
8CC4
8CC8
8CCC
OCCD
eo
54582849
4E542821)
28
FF
OCCE E5
8CCF F5
0CD8 C5
0CD1D5
9CD23E61
9CD4 D3R8
IICD6 1684
0CD8 2R1828
8CD8 E5
9CDC 45
ecoo 2R132t
aCE884
aCE1 78
8CE2 eo
8CE3 ClE48A
aCE615
8CE7 C2Eeoc
8CEA E1
8CE8 DII92
laD 77
8CEE 2C
8CEF 3688
9CF1 2C
9CF2 3688
9CF42C
9CF53688
9CF7 2C
861
862
863
864
865
866
867
868
869
878
;
mtISG· 011
CR.'~
INT - ',1IfFH
;
,
; TRRNSIIITTER IHTERRtI'T R(lJT11£
;
TXI.
PUSH
H
PUSH
PSN
B
PUSH
PUSH
D
IIYI
fl.DTDIIR
fQ)E57
OOT
D,84H
871
ttYl
LIIJ)
l.DfI)R
872
873
PUSH H
S,L
874
!tOY
LIIJ)
CIR)R
87'S
876 ~11. INR
B
A,S
877
lIlY
878
CII'
L
879
JZ
BlfFI1.
D
888
Del!
881
JN2
~11
H
882
POP
IN
883
mR73
884
lIlY
",A
885
INR
L
IIYI
11.8811
886
887
INR
L
888
IIYI
",8811
889
INR
L
898
ttYl
11.8811
891
INR
L
5RYE II.
SRYE PSN
SRYE 9C
SRYE DE
DISRIllE ~ DIll
8257 IDlE P~T
SET cruITER
GET
UA)
PDINTER
5RYE IT
SRYE lS8 IN S
GET CtWSa.E POINTER
IN: POINTER
GET SET TO TEST
L~?
YES, BlfFER Fl.lL
I«l, TEST I£XT LOCIITlDN
TRY IUIIN
REST~ LDAD POINTER
~ RESllT
STORE 1M BlfFER
lit! POINTER
EXTRA lIESIl.T SPOTS 8
2·343
611001-59
inter
AP-36
eCF6
:;6~e
MVI
INI1
SHLD
892
0CFA 2C
OCFB 221029
0CFE CD?S9B
9Nl1 D1
9002 C1
0093 F1
0094 E1
00B5 Fe
ilOe6 (9
89~
894
899
990
C~LL
POP
POP
POI'
POI'
EI
RET
901
992
ge1
904
995
",09H
L
L(>A[l~
,lfDRTE LOAD POINTER
,~SET DMA CHANNEl.
,PESTOPE DE
,~STOPE Be
,RESTORE PSW
,RESTORE Ii.
,ENABLE INTERRUPTS
, ~ET!JI1N
TXDIIIl
D
B
PSIj
H
ge6 '
997 '
9S2 '
953 '
954
END
PUBLIC SYMBOLS
EXTERNAL SYI'IBOLS
IJSER SYMBOLS
ADWN A 092;:
CMD51 A 892i'
CNT953 A 0e9C
COI1!t A eAE5
A gee0
DE"
ECIfO A 9SFS
ILLEG A 9SAI
P[lCNT2 A 99B6
PAP1 uses
POLIN A 2916
i1f.y
A 9iltI2
RS(MD A 9967
RXI1 A 0C16
RXINT A 0008
RXTC ~ 41FF
SPCMD ~ e9E2
STKSRT A 2OCO
mT73 A 9992
TXBIJF A 8999
TXlNT R 9994
TYMSG A OC9~
AFCI'ID
CHDBFl
CNT15J
eMIl
DEItilDE
ENOCH!(
LDADR
HOESl
PAR2
PRPII'T
RESBUF
~5T65
RXI2
RXIR73
SSCMD
SRCMD
SIj
TFCMD
T~D51
,XIRn
T'r'MSG1
ASSEMBLY (Oi'IPLETE,
A 09CE
A 2020
A 909D
A iIlEA
A 2027
A eA1S
A 2819
A 99CE
A 9B9D
A 2815
A 2099
A 20CE
A OC2J
A 9993
A 9985
A 09IlA
A 994?
A 99EC
A 0088
A 9992
A OCRl
BllFFUL
OOBllF
CNT2S:;
C0IIII2
OISPY
ENDMA
LF
MODESJ
PARIN
RaPT
RE$l7l
RSTi''i
RXB
RXIRA
SDIIN
SSCI'ID
T1
TFCMD1
TXDIfIl
TXIRA
TI'I1SG2
A W4
A 2900
A 0e9E
A 9AFF
A 01[;9
A 806:l
A 990A
A ge9B
A 8fIAI)
A 9AA2
A ge91
R 2004
A9m
A 9992
A 8807
A 0989
A OC6C
A 89F6
A 9935
R 99!l1
A OC93
CHeADR
("DOOT
CNTLSl
Cll'tli'3
DISPYl
IlDWN
LKBFl
i'IODES7
PARIN1
R1PT
ROCPI)
RXBllF
11'~14
RhSl
SIGNON
START
TBUFFL
TFRET
TXDMA1
TXPOL
A 90A0
A 0AFB
A 8989
A ge9\l
A 9A4E
A 9SFF
A 2817
A 00A8
A we
A eAA7
A 895['
A 8288
A 0(45
A 8A69
A I¥..A?
A 9899
A 9A24
A eA3,;
A 9942
A 094C
CHeTe
CllDREC
CNTLC
CPSf
D1SPY2
GETCH
I.KBR2
MONTOR
PftRIN2
RBCI1Ii
RPCI«)
RXD51
R:m
RXS2
$lCI«)
STAT51
TBUFL
TLCHI)
. TXI
TXRET
A 89A1
A 8857
A 8983
A 0029
A !lA4O
A 961F
A 2918
A 9008
A 9ADC
A 897B
A e9D8
A eses
A OCS9
A 8Ai'F
A e9SF
A 9989
A eA07
A 8999
A OCCE
A OC6E
A~
A 8931
A 85118
A 9900
A 8862
A iltI7D
A 9861
A 1l6C7
A 8AIIC
A 8971
A 9911
A 881A
A etas
A 0A6()
S/l(J\f' A 9993
STAT57 A 01!A8
TBUFLl A 9A9D
TRUE A B899
TXll A 0CE0
n.
0
t;
I
I
CHARACTER
*1
t:
ID
Ia:
C
Ii;
I
I-t:
iiilD
1>.1<
~~
II
~
..e
I>.
-I
CHARACTER CHARACTER
*2
*3
t:
ID
l-
a:
~
t:
ID
I>.
0
t;
I
CHARACTER
U
I
t:
III
....
II:
C
l-
Ul
ID
l-
f/)
I
I
CHARACTER
*5
Figure 2. Multiple Character Transmission
2-347
t:
...0
210311-1
inter
AP-134
Framing
Character framing is accomplished by the START and
STOP bits described previously. When the START bit
transition (mark-to-space) is detected, the receiving system assumes that a character of data will follow. In
order to test this assumption (and isolate noise pulses
on the data link), the receiving system waits one-half bit
time and samples the data link again. If the link has
returned to the marking state, noise is assumed, and the
receiver waits for another START bit transition.
bits per second to 38,400 bits per second. Table 1 illustrates typical asynchronous data rates and the associated 'clock frequencies required for the transmitter and
receiver circuits.
Table 1. Communication Data Rates and
Associated Transmitter/Receiver Clock Rates
Data Rate
(Bits/Second)
75
150
300
600
1200
2400
4800
9600
19200
38400
When a valid START bit is detected, the receiver samples the data link for each bit of the following character. Character data bits and the parity bit (if required)
are sampled at their nominal centers until all required
characters are received. Immediately following the data
bits, the receiver samples the data link for the STOP
bit, indicating the end of the character. Most systems
permit specification of I, 1Y., or 2 stop bits.
Clock Rate (kHz)
X16
X32
X64
1.2
2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4
2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.2
-
-
Timing
The trlillsmitter and receiver in 'an asynchronous data
link arrangement are clocked independently. Normally, .
each clock is generated locally and the clocks are' not
synchronized. In fact, each clock may be a slightly different frequency. (In practice, the frequency difference
should not exceed a few percent. If the transmitter and
receiver clock rates vary substantially, errors will occur
because data bits may be incorrectly identified as
START or STOP framing bits.) These clocks are designed to operate at 16,32, or 64 times the communications data rate. These clock speeds allow the receiving
device to correctly sample the incoming bit stream.
Serial-interface data rates are measured in bits/second.
The term "baud" is used to specify the number oftimes
per second that the transmitted signal level can change
states. In general, the baud is not equal to the bit rate.
Only when the transmitted signal has two states (e1ectricallevels) is the baud rate equal to the bit rate. Most
point-to-point serial data links use RS-232-C, RS-422,
or RS-423 electrical interfaces. These specifications call
for two electrical signal levels (the baud is equal to the
bit rate). Modem interfaces, however, may often have
differing bit and baud rates.
While there are generally no limitations on the \:lata
transmission rates used in an aysnchronous data link, a
limited set of rates has been standardized to promote
equipment interconnection. These rates vary from 75
Parity
In order to detect transmission errors, a parity bit may
be added to the character, data as it is transferred over
the data link. The parity bit is set or cleared to make
the total number of "one" bits in the character even
(even parity) or odd (odd parity). For example, the letter "A" is represented by the seven-bit ASCII code
1000001 (4IH). The transmitted data code (with parity)
for this character contains eight bits; 01000001 (4lH)
for even parity and 11000001 (OCIH) for odd parity.
Note that a single bit error changes the parity of the
received character and is therefore easily detected. The
8274 supports both odd and even parity checking as
well as a parity disable mode to support binary data
transfers.
Communication Modes
Serial data transmission between two devices can occur
in one of three modes. In the simplex transmission
mode, a data link cap. transmit data in one direction
only. In the half-duplex ,mode, the data link can transmit data in both directions, but not simultaneously. In
the full-duplex mode (the most common), the data link
can transmit data in both directions simultaneously.
The 8274 directly supports the full-duplex mode and
will interface to simplex and half-duplex communication data links with appropriate software controls.
2-348
inter
AP-134
BREAK Condition
The 8274-processor hardware interface can be configured in a flexible manner, depending on the operating
mode selected-polled, interrupt-driven, DMA, or
WAIT. Figure 3 illustrates typical MPSC configurations for use with an 8088 microprocessor in the polled
and interrupt-driven modes.
Asynchronous data links often include a special sequence known as a break condition. A break condition
is initiated when the transmitting device forces the data
link to a spacing state (binary 0) for an extended length
of time (typically 150 milliseconds). Many terminals
contain keys to initiate a break sequence. Under software control, the 8274 can initiate a break sequence
when transmitting data and detect a break sequence
when receiving data.
All serial-to-parallel conversion, parallel-to-serial conversion, and parity checking required during asynchronous serial I/O operation is automatically performed
by the MPSC.
MPSC SYSTEM INTERFACE
Operational Interface
Hardware Environment
The 8274 MPSC interfaces to the system processor over
an 8-bit data bus. Each serial I/O channel responds to
two I/O or memory addresses as shown in Table 2. In
addition, the MPSC supports non-vectored and vectored interrupts.
The 8274 may be configured for memory-mapped or
I/O-mapped operation.
Command, parameter, and status information is stored
in 21 registers within the MPSC (8 writable registers
and 2 readable registers for each channel, plus the interrupt vector register). These registers are all accessed
by means of the command/status ports for each channel. An internal pointer register selects which of the
command or status registers will be written or read during a command/status access of an MPSC channel.
Figure 4 diagrams the command/status register architecture for each serial channel. In the following discussion, the writable registers will be referred to as WRO
through WR7 and the readable registers will be referred to as RRO through RR2.
Table 2. 8274 Addressing
CS
A1
Ao
. Read Operation
Write Operation
0
0
0
0
0
1
0
1
0
0
1
1
1
X
X
Ch. A Data Read
Ch. A Status Read
Ch. B Data Read
Ch. B Status Read
High Impedance
Ch. A Data Write
Ch. A Command/Parameter
Ch. B Data Write
Ch. B Command/Parameter
High Impedance
2-349
AP-134
l
.,.
ADDRESS BUS
...
6
6 DATA BUS
~
lf6
WII
JYee
8205
~
'---
~
P
-
-
DB0-7
Ao
A,
INTA
MPSC
CS
RD
WR
210311-3
a) Polled Configuration
INT
J
cr--o<}
.
INTA
b
CPU
INT
~
IPI
b
INT
INTA
IPO
IPI
IPO
MPSC
MPSC
HIGHEST PRIORITY
INT
INTA
IPI
b
INTA
IPO
MPSC
LOWEST PRIORITY
210311-4
b) Daisy-Chained Interrupt Configuration
Figure 3. 8274 Hardware Interface for Polled and Interrupt-Driven Environments
The least-significant three bits of WRO are automatically loaded into the pointer register every time WRO is
written. After reset, WRO is set to zero so that the first
write to a command register causes the data to be loaded into WRO (thereby setting the pointer register). After WRO is written, the following read or write accesses
the register selected by the pointer. The pointer is reset
after the read or write operation is completed. In this
manner, reading or writing an arbitrary MPSC channel
register requires two I/O accesse~. The first access is
always a write command. This write command is used
to set the pointer register. The second access is either a
read or a write command; the pointer register (previously set) will ensure that the correct internal register is
read or written. After this second access, the pointer
register is automatically reset. Note that writing WRO
and reading RRO does not require presetting of the
pointer register.
During initialization and normal MPSC operation, various registers are read and/or written by the system
processor. These actions are discussed in detail in the
following paragraphs. Note that WR6 and WR7 are
not used in the asynchronous communication modes.
RESET
When the 8274 RESET line is activated, both MPSC
channels enter the idle state. The serial output lines are
forced to the marking state (high) and the modem interface signals (RTS, DTR) are forced high. In addition, the pointer register is set to zero.
2-350
AP-134
COMMAND/STATUS
POINTER
D2
Dl
0
DO
0
_I
W:
-I w
0
0
0
-I
-I
-I
-I
w
R
:
0
"\
::I
I1
II
R
II
R
R
R
R
R
R
R
I
2'
LSB
MSB
Read Registers
W
R
w
R
·Ch. B only
W
R
-I w
R
6
-I
R
7
w
I
MSB
LSB
Write Registers
210311-5
Figure 4. Command/Status Register Architecture (Each Serial Channel)
External/Status Latches
The MPSC continuously monitors the state of four external/status conditions:
1. CTS--clear-to-send input pin.
2. CD--carrier-detect input pin.
3. SYNDET-sync-detect input pin. This pin may be
used as a general-purpose input in the asynchronous
communication mode.
4. BREAK-a break condition (series of space bits on
the receiver input pin).
2-351
A change of state in any of these monitored conditions
will cause the associated status bit in RRO (Appendix
A) to be latched (and optionally cause an interrupt).
Error Reporting
Three error conditions may be encountered during data
reception in the asynchronous mode:
1. Parity. If parity bits are computed and transmitted
with each character and the MPSC is set to check
parity (bit 0 in WR4 is set). a parity error will occur
whenever the number of "1" bits within the character (including the parity bit) does not match the odd/
even setting of the parity check flag (bit 1 in WR4).
inter
AP-134
2. Framing. A framing error will occur if a stop bit is
not detected immediately following the parity bit (if
parity checking is enabled) or immediately following
the most-significant data bit (if parity checking is not
enabled).
3. Overrun. If an input character has been assembled
but the receiver buffers are full (because the previously received characters have not been read by the
system processor), an overrun error will occur.
When an overrun error occurs, the input character
that has just been received will overwrite the immediately preceding character.
Number of
Bits Transmitted
07 06 05 04 03 02 01 DO (Character Length)
1111000c
1
111000cc
2
11000ccc
3
1000cccc
4
OOOccccc
5
7. Transmitter Enable. The serial channel transmitter
operation may be enabled or disabled by setting or
clearing bit 3 of WR5. (See Appendix A for WR5
details.)
Transmitter/Receiver Initialization
For data transmissions via a modem or RS-232-C interface, the following information must also be specified:
1. Request-to-Send/Data-Terminal-Ready. Must be set
to indicate status of data terminal equipment. Request-to-send is controlled by bit 1 of WR5 and data
terminal ready is controlled by bit 7. (See Appendix
A for WR5 details.)
2. Auto Enable. May be set to allow the MPSC to automatically enable the channel transmitter when the
clear-to-send signal is active and to automatically enable the receiver when the carrier-detect signal is active. Auto Enable is controleld by bit 5 of WR3. (See
Appendix A for WR3 details.)
In order to operate in the asynchronous mode, each
MPSC channel must be initialized with the following
information:
1. Clock Rate. This parameter is specified by bits 6 and
7 of WR4. The clock rate may be set to 16, 32, or 64
times the data-link bit rate. (See Appendix A for
WR4 details.)
2. Number of Stop Bits. This parameter is specified by
bits 2 and 3 of WR4. The number of stop bits may be
set to I, I Y., or 2. (See Appendix A for WR4
details.)
3. Parity Selection. Parity may be set for odd, even, or
no parity by bits 0 and I of WR4. (See Appendix A
for WR4 details.)
4. Receiver Character Length. This parameter sets the
length of received characters to 5, 6, 7, or 8 bits. This
parameter is specified by bits 6 and 7 of WR3. (See
Appendix A for WR3 details.)
5. Receiver Enable. The serial-channel receiver operation may be enabled or disabled by setting or clearing
bit 0 of WR3. (See Appendix A for WR3 details.)
6. Transmitter Character Length. This parameter sets
the length of transmitted characters to 5, 6, 7, or 8
bits. This parameter is specified by bits 5 and 6 of
WR5. (See Appendix A for WR5 details.) Characters
of less than 5 bits in length may be transmitted by
setting the transmitted length to five bits (set bits 5
and 6 of WR5 to I).
The MPSC then determines the actual number of
bits to be transmitted from the character data byte.
The bits to be transmitted must be right justified in
the data byte, the next three bits must be set to 0 and
all remaining bits must be set to 1. The following
table illustrates the data formats for transmission of
I to 5 bits of data:
During initialization, it is desirable to guarantee that
the external!status latches reflect the latest interface
information. Since up to two state changes are internally stored by the MPSC, at least two Reset External!
Status Interrupt commands must be issued. This procedure is .most easily accomplished by simply issuing this
reset command whenever the pointer register is set during initialization.
An MPSC initialization procedure (MPSC$RX$INIT)
for asynchronous communication is listed in Appendix
B. Figure 5 illustrates typical MPSC initialization parameters for use with this procedure.
call MPSC$RX$INIT(41,
1,1,0,1, 3,1,1,
3,1,1,0,1);
initializes the 8274 at address 41 as follows:
X16 clock rate
1 stop bit
Odd parity
8-bit characters
(Txand Rx)
Enable transmitter
and receiver
Auto enable. set
DTR and RTS set
Break transmission disabled
Figure 5. Sample 8274 Initialization Procedure
for Polled Operation
inter
AP-134
Polled Operation
In the pelled mede, the precesser must meniter the
MPSC status by testing the apprepriate bits in the read
register. Data available, status, and errer cenditiens are
represented in RRO and RRI fer channels A and B. An
example ef MPSC-pelled transmitter/receiver routines
are given in Appendix B. The fellewing reutines are,
detailed:
1. MPSC$POLL$RCV$CHARACTER-This precedure receives a character frem the serial data link.
The routine waits until the character-available flag in
RRO has been set. When this flag indicates that a
character is available, RR 1 is checked fer errors
(everrun, parity, er framing). If an error is detected, the character in the MPSC receive 'buffer
must be read and discarded and the error routine
(RECElVE$ERROR) is called. If no. receive errers
have been detected, the character is input frem the
8274 data pert and returned to. the calling program.
MPSC$POLL$RCV$CHARACTER requires three
parameters-the address ef the 8274 channel data
port (data$port), the addres~ of the 8274 channel
cemmand port (cmd$pert), and the address ef a byte
variable in which to. store the received character
(character$ptr).
2. MPSC$POLL$TRAN$CHARACTER-This procedure transmits a character to. the serial data link.
The reutine waits until the transmitter-buffer-empty
flag has been set in RRO befere writing the character
to the 8274.
,MPSC$POLL$TRAN$CHARACTER
requires
three parameters-the address of the 8274,channel
data pert (data$pert), the address of the 8274 channel cemmand pert (cmd$pert), and the character ef
data that is to be transmitted (character).
3. RECEIVE$ERROR-This procedure precesses receiver errors. First, an Errer Reset cemmand is written to. the affected channel. All additional error processing is dependent on the specific applicatien. Fer
example, the receiving device may immediately request retransmissien ef the character er wait until a
message has been completed.
RECEIVE$ERROR requires two parameters-the
address ef the affected 8274 command pert
(cmd$pert) and the errer status (status) from 8274
register RR 1.
Interrupt-Driven Operation
In an interrupt-driven envirenment, all receiver operatiens are reperted to the system processer by means ef
interrupts. Once a character has been received and assembled, the MPSC interrupts the system processer.
The system precesser must then read the character
from the MPSC data buffer and clear the current interrupt. During transmissien, the system precesser starts
serial I/O by writing the first character ef a message to.
the MPSC. The MPSC interrupts the system precessor
whenever the next character is required (i.e., when the
transmitter buffer is empty) and the precessor responds
by writing the next character ef the message to the
MPSC data pert for the appropriate channel.
By using interrupt-driven I/O, the MPSC proceeds independently ef the system processer, signalling the
precesser enly when characters are required fer transmission, when characters are received from the data
link, er when errors occur. In this manner, the system
precesser may centinue executien of ether tasks while
serial I/O is performed cencurrently.
Interrupt Configurations
The 8274 is designed to interface to. 8085- and 8086type processers in much the same manner as the 8259A
is designed. When operating in the 8085 mede, the 8274
causes a "call" to a prespecified, interrupt-service routine lecatien. In the 8086 mede, the 8274 presents the
precessor with a one-byte interrupt-type number. This
interrupt-type number is used to. "vecter" through the
8086 interrupt service table. In either case, the interrupt service address or interrupt-type number is specified during MPSC initialization.
To. sherten interrupt latency, the 8274 can be pregrammed to. modify the prespecifled interrupt vector so.
that no seftware overhead is required to. determine the
cause of an interrupt. When this "status affects vecter"
mede is enabled, the follewing eight interrupts are differentiated autematically by the 8274 hardware:
1. Channel B Transmitter Buffer Empty.
2. Channel B External/Status Transition.
3. Channel B Character Available.
4. Channel B Receive Error.
5. Channel A Transmitter Buffer Empty.
6. Channel A External/Status Transition.
7. Channel A Character Available.
8. Channel A Receive Error.
Interrupt Sources/Priorities
The 8274 has three interrupt sources fer each channel:
1. Receiver (RxA, RxB). An interrupt is initiated when
'a character is available in the receiver buffer er when
a receiver errer (parity, framing, er everrun) is detected.
2. Transmitter (TxA, TxB). An interrupt is initiated
when the transmitter buffer is empty and the 8274 is
ready to. accept another character fer transmission.
2-353
AP-134
3. External/Status (ExTA, ExTB). An interrupt is initiated when one of the external/status conditions
(CDE, CTS, SYNDET, BREAK) changes state.
The 8274 supports two interrupt priority orderings (selectable during MPSC initialization) as detailed in Appendix A, WR2, CH-A.
Interrupt Initialization
In addition to the initialization parameters required for
polled operation, the following parameters must be supplied to the 8274 to specify interrupt operation:
I. Transmit Interrupt Enable. Transmitter-buffer-empty interrupts are separately enabled by bit 1 ofWRl.
(See Appendix A for WRI details.)
2. Receive Interrupt Enable. Receiver interrupts are
separately enabled in one of three modes: a) interrupt
on first received character only and on receive errors
(used for message-oriented transmission systems), b)
interrupt on all received characters and on receive
errors, but do not interrupt on parity errors, and c)
interrupt on all received characters and on receive
errors (including parity errors). The ability to separately disable parity interrupts can be extremely useful when transmitting messages. Since the parity error bit in RRI is latched, it will not be reset until an
error reset operation is performed. Therefore, the
parity error bit will be set if any parity errors were
detected in a multi-character message. If this mode is
used, the serial I/O software must poll the parity
error bit at the completion of a message and issue an
error reset if appropriate. The receiver interrupt
mode is controlled by bits 3 and 4 of WRI. (See
Appendix A for WRI details.)
3. External/Status Interrupts. External/Status interrupts can be separately enabled by bit 0 ofWRl. (See
Appendix A for WRI details.)
4. Interrupt Vector. An eight-bit interrupt-service routine location (8085) or interrupt type (8086) is specified through WR2 of channel B. (See Appendix A
for WR2 details.) Table 3 lists interrupt vector' addresses generated by the 8274 in the "status affects
vector" mode.
5. "Status Affects Vector" Mode. The 8274 will automatically modify the'interrupt vector if bit 3 of WR 1
is set. (See Appendix A for WRI details.)
6. System Configuration. Specifies the 8274 data transfer mode. Three configuration modes are available:
a) interrupt-driven operation for both channels, b)
DMA operation for both channels, and c) DMA operation for channel A, interrupt-driven operation for
channel B. The system configuration is specified by
means of bits 0 and 1 of WR2 (channel A). (See
Appendix A for WRZ details.)
7. Interrupt Priorities. The 8274 permits software specification of receive/transmit priorities by means of
bit 2 of WR2 (channel A). (See Appendix A for
WR2 details.)
8. Interrupt Mode. Specifies whether the MPSC is to
operate in a non-vectored mode (for use with an external interrupt controller), in an 8086-vectored
mode, or in an 8085-vectored mode. This parameter
is specified through bits 3 and 4 of WR2 (channel
A). (See Appendix A for WR2 details.)
An MPSC interrupt initialization procedure
(MPSC$INT$INIT) is listed in Appendix C.
2-354
inter
AP-134
Table 3. MPSC-Generated Interrupt Vectors In "Status Affects Vector" Mode
V7
V6
V5
V4
V3
V2
V1
VO
V7
V6
8086
Interrupt Type
V5
V4
V3
V2
V1
VO
Original Vector
(Specified during
Initialization)
Interrupt
Condition
8085
Interrupt Location
V7
V6
V5
V4
V3
0
0
0
V7
V6
V5
0
0
0
V1
VO
Channel B Transmitter
Buffer Empty
V7
V6
V5
V4
V3
0
0
1
V7
V6
V5
0
0
1
V1
VO
Channel B External/Status
Change
V7
V6
V5
V4
V3
0
1
0
V7
V6
V5
0
1
0
V1
VO
Channel B Receiver
Character Available
V7
V6
V5
V4
V3
0
1
1
V7
V6
V5
0
1
1
V1
VO
Channel B Receive Error
V7
V6
V5
V4
~3
1
0
0
V7
V6
V5
1
0
0
V1
VO
Channel A Transmitter
Buffer Empty
V7
V6
V5
V4
V3
1
0
1
V7
V6
V5
1
0
1
V1
VO
Channel A External/Status
Change
V7
V6
V5
V4
V3
1
1
0
V7
V6
V5
1
1
0
V1
VO
Channel A Receiver
Character Available
V7
V6
V5
V4
V3
1
1
1
V7
V6
V5
1
1
1
V1
VO
Channel A Receive Error
Interrupt Service Routines
,
Appendix C lists four interrupt service procedures, a
buffer transmission procedure, and a buffer reception
procedure that illustrate the use of the 8274 in interrupt-driven environments. Use of these procedures assumes that the 8086/8088 interrupt vector is set to 20H
and that channel B is used with the "status affects vector" mode enabled.
I. TRANSMIT$BUFFER-This procedure begins serial transmission of a data buffer. Two parameters
are required-a pointer to the buffer (buf$ptr) and
the length of the buffer (buf$length). The procedure
first sets the global buffer pointer, buffer length, and
initial index for the transmitter-interrupt service routine and initiates transmission by writing the first
character of the buffer to the 8274. The procedure
then enters a wait loop until the I/O completion
status is set by the transmit-interrupt service routine
(MPSC$TRANSMIT$CHARACTER$INT).
2. RECEIVE$BUFFER-This procedure inputs a line
(terminated by a line feed) from a serial VO port.
Two parameters are required-a pointer to the input
buffer (buf$ptr) and a pointer to the buffer length
variable (buf$length$ptr). The buffer length will be
set by this procedure when the complete line has
been input. The procedure first sets the global buffer
pointer and initial index for the receiver interrupt
service routine. RECEIVE$BUFFER then enters a
wait loop until the I/O completion status is set by
the receive interrupt routine (MPSC$RECEIVE$CHARACTER$INT).
3. MPSC$TRANSMIT$CHARACTER$INT-This
procedure is executed when the MPSC Tx-bufferempty interrupt is acknowledged. If the current
transmit buffer index is less than the buffer length,
the next character in the buffer is written to the
MPSC data port and the buffer pointer is updated.
Otherwise, the transmission complete status is posted.
4. MPSC$RECEIVE$CHARACTER$INT-This procedure is executed when a character has been assembled by the MPSC and the MPSC has issued a character-available interrupt. If no input buffer has been
set up by RECEIVE$BUFFER, the character is ignored. If a buffer has been set up, but it is full, a
receive overrun error is posted. Otherwise, the received character is read from the MPSC data port
and the buffer index is updated. Finally, if the received character is a line feed, the reception complete
status is posted.
5. RECEIVE$ERROR$INT-This procedure is executed when a receive error is detected. First, the error conditions are read from RR 1 and the character
currently in the MPSC receive buffer is read and discarded. Next, an Error Reset command is written to
the affected channeL All additional error proc!lssing
is application dependent.
6. EXTERNAUSTATUS$CHANGE$INT-This
procedure is executed when an external status condition change is deteCted. The status conditions are
read from RRO and a Reset External/Status Interrupt command is issued. Further error processing is
application dependent.
2-355
intJ
AP-134
DATA LINK INTERFApE·
Serial.Data Interface
Each serial 1/0 cb,annel within the 8274 MPSC ~ter
faces to two datil link lines-one line for ,transmitting
data and one for receiving data. During transmission,
characters are converted from parallel data format (as
supplied by the system proeessor or DMA device) into
a serial bit stream (with START and STOP bits) and
clocked out on the TxD pin. During reception, a serial
bit stream is input on theRxD pin, framing bits are
stripped out of the· data stream, and the resulting character is converted to parallel data format and passed to
the system processor or DMA device.
Data Clocking
As discussed previously, the frequency of data transmission/reception on the data link is controlled by the
MPSC clock in conjunction with the programmed
clock divider (in register WR4). The 8274 is designed to
permit all four serial interface lines (Till and RxD for
each channel) to operate at different data rates. Four
clock input pins (TxC and RxC for each channel) are
available for this function. Note that the clock rate divider speified in WR4 is used for both RIlC and TxC on
the appropriate channel; clock rate dividers for each
chanllel are independent.
Modem Control
The following four modem interface signals may be
connected to the 8274:
1. Data Terminal Ready (DTR). This interface signal
(output by the 8274) is software controlled through
bit 7 of WRS. When active, DTR indicates that the
data terminal/computer equipment is active and
ready .to' interact with the data· communications
channel. In addition, this signal prepares the modem
for connection to the communication channel and
maintains connections previously established (e.g.,
,
manual call origination). ' '
2. Request To Send (RTS). This interface signal (output by the 8274) is software controlled through bit 1
'of WRS. When active, RTS indicates that the data
terminal/computer equipment is ready to transmit
data. When the RTS bit is reset in asynchronous
mode, the signal does not go high until the transmitter is empty.
3. Clear To Send (CTS). This interface signal (input to
the 8274) is supplied by the modem in response to an
active RTS signal. CTS indicates that the data terminal/computer equipment is permitted to transmit
data. The state of CTS is available to the programmer as bit S of RRO. In addition, if the auto enable
control is set (bit S ofWR3), the 8274 will not transmit data bytes until CTS has been activated. If CTS
becomes inactive during transmission of a character,
the current character transmission is completed before the transmitter is disabled.
4. Carrier Detect (CD). This interface signal (input to
the 8274) is supplied by the modem to indicate that a
data carrier signal has been detected and that a valid
data signal is present on the RxD line. The state of
CD is available to the programmer as bit 3. of RRO.
In addition, if the auto enable control is set (bit S of
WR3), the 8274 will not enable the serial receiver
until CD !)as been activated. If the CD. signal becomes inactive during reception of a character, the
receiver is disabled,.and the partially received character is lost.
In addition to the above modem interface signals, the
8274 SYNDET input pin for channel A may be used as
a general-purpose input in the asynchronous communication mode. The status of this signal is available to the
programmer as bit 4 of status register RRO.
2~356
inter
AP-134
APPENDIX A
COMMAND/STATUS DETAILS FOR ASYNCHRONOUS
COMMUNICATION
logic and all control registers for the channel. Four extra system clock cycles should
be allowed for MPSC reset time before
any additional commands or controls are
written into the channel.
Command 4 Enable Interrupt on Next Receive Character-if the Interrupt-on-First-Receive
Character mode is selected, this command
reactivates that mode after each complete
message is received to prepare the MPSC
for the next message.
Command 5 Reset Transmitter Interrupt Pending-if
the Transmit Interrupt mode is selected,
the MPSC automatically interrupts data
when the transmit buffer becomes empty.
When there are no more characters to be
sent, issuing this command prevents further transmitter interrupts until the next
character has been completely sent.
Command 6 Error Reset-error latches, Parity and
Overrun errors in RR I are reset.
Command 7 End of Interrupt-resets the interrupt-inservice latch of the highest-priority internal device under service.
Write Register 0 (WRO):
COMMAND/STATUS POINTER
REGISTER POINTER
r
0
o1
NULL CODE
NOT USED IN ASYNCHRONOUS MODES
REseT EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT Ax
CHARACTER
RESET TxlNT PENDING
ERROR RESET
END OF INTERRUPT (Q. Aonlyl .
NOT USED IN ASYNCHRONOUS MODES
210311-6
Write Register 1 (WR1):
D2,DI,DO Command/Status Register Pointer bits
determine which write-register the next
byte is to be written into, or which readregister the next byte is to be read from.
After reset, the first byte written into either channel goes into WRO. Following a
read or write to any register (except WRO)
the pointer will point to WRO.
D5,D4,D3 Command bits determine which of the basic seven commands are to be performed.
Command 0 Null-has rio effect.
Command I Note used in asynchronous modes.
Command 2 Reset External/Status Interrupts-resets
the latched status bits of RRO and reenables them, allowing interrupts to occur
again.
Command 3 Channel Reset-resets the Latched Status
bits of RRO, the interrupt prioritization
DO
DI
D2
2-357
External/Status Interrupt Enable-allows
interrupt to occur as the result of transitions on the CD, CTS or SYNDET inputs. Also allows interrupts as the result
of a Break/Abort detection and termination, or at the beginning of CRC, or sync
character transmission when the Transmit
Underrun/EOM latch becomes set.
Transmitter Interrupt/DMA Enable-allows the MPSC to interrupt or request a
DMA transfer when the transmitter buffer
becomes empty.
Status Affects Vector-(WRI, D2 active
in channel B only.) If this bit is not set,
then the fixed vector, programmed in
WR2, is returned from an interrupt acknowledge sequence. If the bit is set, then
the vector returned from an interrupt acknowledge is variable as shown in the Interrupt Vector Table.
inter
Ap:.134
Write Register 1 (WR1):
Write Register 2 (WR2): Channel A
MBB
MSB
LSB
107 1 0 1 05 1 04 : 03 102 1 D11
Dol
'---..,--I
I
1 07 : 0105104:03102101:001
'---..,--I
0
0
1
1
EXT INTERRUPT
ENABLE
r.INTERRUPTI
DMAENABLE
STATUS AFFECTS
VECTORICHBONLY)
(NULLCODECH A)
'---..,--I
1 VARIABLE
VECTOR
0 VECTOR
FIXED
0
1
0
1
>
0 0
1
0
1 0
1 1
A.tNT/OMA DISABLE
RalNT ON FIRST CHAR OR SPECIAL
CONDITION
tNT ON ALL Ax CHAR (PARITY AFFECTS
VECTOR) OR SPECIAL CONDITION
tNT ON ALL Ax CHAR (PARITY DOES
NOT AFFECT VECTOR) OR SPECIAL
1
CONDITION
o-
1
8085 MODE 2
8086/88 MODE
ILLEGAL
= VECTORED INTERRUPT
NON VECTORED INTERRUPT
MUST BE ZERO
1 PIN 10 = SYNDET B
MUST BE ZERO
o
1 - ENABLE. 0
DISABLE
1 0
1 1
D5
D6
D7
PIN10=RTS s
NOTE:
210311-8
• External Status Interrupt-only if EXT Interrupt Enable
(WR1; DO) is set.
210311-7
D4,D3
00
o1
TlIa >£XTA* >E·)(T8'
8085 MODE 1
WAIT ON Rx,O " WAIT ON TIC
WAIT ENABLE
BOTHOMA
ILLEGAL
1 = PRIORITY AKA >Ax8>TxA>
TI.8 >EXTA' EXlS'
~
0
1
0
1
A OMA, 8 INT
a ::: PRIORITY RxA >txA >Rxa >
~
0
0
1
1
80TH INTERRUPT
Receive Interrupt Mode.
Receive Interrupts/DMA Disabled.
Receive Interrupt on First Character Only
or Special Condition.
Interrupt on All Receive Characters of
Special Condition (Parity Error is a Special Receive Condition).
Interrupt on All Receive Characters or
Special Condition (Parity Error is not a
Special Receive Condition).
Wait on ReceivelTransmit-when the following conditions are met, the RDY pin is
activated, otherwise it is held in the HighZ state. (Conditions: Interrupt Enabled
Mode, Wait Enabled, CS = 0, AO = 0/1,
and Al = 0). The RDY pin is pulled low
when the transmitter buffer is full or the
receiver buffer is empty and it is driven
High when the transmitter buffer is empty
or the receiver buffer is full. The RDY A
and RDYB may be wired or connected
since only one signal is active at anyone
time while the other is in the High Z state.
Must be Zero.
Wait Enable-enables the wait function.
D1,DO
00
o1
1 0
1 1
D2
o
2-358
System Configuration-These specify the
data transfer from MPSC channels to the
CPU, either interrupt or DMA based.
Channel A and Channel B both use interrupts.
Channel A uses DMA, Channel B uses interrupt.
Channel A and Channel B both use
DMA.
Illegal Code.
Priority-this bit specifies the relative priorities of the internal MPSC interrupt!
DMA sources.
(Highest) RxA, TxA, RxA, RxB"
TxBExTA, ExTB (Lowest).
(Highest) RxA, RxB, TxA, TxB, ExTA,
ExTB (Lowest).
inter
05,04,03
oX
X
100
101
1 10
06
D7
AP-134
Interrupt Code:-specifies the behavior of
the MPSC when it receives an interrupt
acknowledge sequence from the CPU. (See
Interrupt Vector Mode Table.)
Non-vectored interrupts-intended for
use with an external interrupt controller
such as the 8259A.
8085 Vector Mode I-intended for use as
the primary MPSC in a daisy-chained priority structure.
8085 Vector Mode 2-intended for use as
any secondary MPSC in a daisy-chained
priority structure.
8086/88 Vector Mode-intended for use
as either a primary or secondary in a daisy-chained priority structure.
Must be Zero.
Write Register 3 (WR3):
MSB
LSB
R. ENABLE
L-_ _ _ _ NOT USED tN
ASYNCHRONOUS
MODES
' - - - - - - - - - - A U T O ENABLES
R. 5 BITS/CHAR
o
Pin 10 = mB.
Pin 10 = SYNOETB.'
o
R. 7 BITs/CHAR
R. 8 BITs/CHAR
R. 8 BITs/CHAR
Write Register 2 (WR2): Channel B
MSB
210311-10
DO
LSB
05
\.
L". "
Vector
07-00
210311-9
Interrupt vector-this register contains
the value of the interrupt vector placed on
the data bus during acknowledge sequences.
07,06
00
oI
I 0
I I
2-359
Receiver Enable-a one enables the receiver to begin. This bit should be set only
after the receiver has been initialized.
Auto Enables-a one written to this bit
causes CO to be an automatic enable signal for the receiver and CTS to be an automatic enable signal for the transmitter. A
zero written to this bit limits the effect of
CO and CTS signals to setting/resetting
their corresponding bits in the status register (RRO).
Receiver Character length.
Receive 5 Oata bits/character.
Receive 7 Oata bits/character.
Receive 6 Oata bits/character.
Receive 8 Oata bits/character.
AP-134
Write Register 4 (WR4):
Write Register 5 (WR5):
MSB
LSB
1071061 D51 041031 021 011 Dol
La
ENABLE PARITY
T USED IN
ASYNCHRONOUS MODES
_ R TS
1
EVEN PARITY
o
ODD PARITY
NOT USED IN
AS YNCHRONOUS MODES
'lXE NABLE
o
0
ENABLE SYNC MODES
o
1
1 STOP BIT
1
0
1.5 STOP BITS
1
1
2 STOP BITS
SENO BREAK
0
NOT USED IN ASYNCHRONOUS MODES
o
0
0
'IX 5 BITS OR LESS/CHAR
0
1
'IX 7 BITS/CHAR
1
0
'IX 6 BITS/CHAR
1
1
'IX 8 BITS/CHAR
DTR
Xl CLOCK
210311-12
X16CLOCK
o
DI
X32 CLOCK
X64 CLOCK
210311-11
DO
DI
D3,D2
o0
o1
I 0
I 1
D7,D6
00
o1
I 0
1 1
Parity-a one in this bit causes a parity bit
to be added to the programmed number of
data bits per character for both the transmitted and received character. If the
MPSC is programmed to receive 8 bits per
character, the parity bit is not transferred
to the microprocessor. With other receiver
character lengths, the parity bit is transferred to the microprocessor.
Even/Odd Parity-if parity is enabled, a
one in this bit causes the MPSC to transmit and expect even parity, and zero causes it to send and expect odd parity.
Stop Bits.
Selects synchronous modes.
Async mode, I stop bit/character.
Async mode, 1'/. stop bits/character.
Async mode, 2 stop bits/character.
Clock mode--selects the clock/data rate
multiplier for both the receiver and the
transmitter. If the Ix mode is selected, bit
synchronization must be done externally.
Clock rate = Data rate X 1.
Clock rate = Data rate X 16.
Clock rate = Data rate X 32.
Clock rate = Data rate X 64.
D3
D4
D6,D5
00
oI
I 0
I 1
Request to Send-a one in this bit forces
the RTS pin active (low) and zero in this
bit forces the RTS pin inactive (high).
When the R TS bit is reset in asynchronous
mode, the signal does not go inactive until
the transmitter is empty.
Transmitter Enable-a zero in this bit
forces a marking state on the transmitter
output. If this bit is set to zero during data
or sync character transmission, the marking state is entered after the character has
been sent. If this bit is set to zero during
transmission of a CRC character, sync or
flag bits are substituted for the remainder
of the CRC bits.
Send Break-a one in this bit forces the
transmit data low. A zero in this bit allows
normal transmitter operation.
Transmit Character length.
Transmit 5 or less bits!character.
Transmit 7 bits/character.
Transmit 6 bits/character.
Transmit 8 bits/character.
Bits to be sent must be right justified, least-significant
bit first, e.g.:
D7 D6 D5 D4 D3 D2 DI DO
o
2-360
0
B5 B4 B3 B2 BI BO
intJ
AP-134
Read Register 0 (RRO):
Msa
In\ PENDING (CHA ONLY)
' - - - - - TlI BUFFER EMPTY
'--_ _ _ _ _ CARRIER DETECT
~
_ _ _ _ _ _ _ SYNDET
'--_ _ _ _ _ _ _ _ _ CTS
EXTERNAL STATUS
INTERRUPT MODE
'--_ _ _ _ _ _ _ _ _ _ NOT USED IN
~
ASYNCHRONOUS MODES
_ _ _ _ _ _ _ _ _ _ _ _ BREAK
210311-13
DO
Dl
D2
D3
D4
Receive Character Availabltr-this bit is
set when the receive FIFO contains data
and is reset when the FIFO is empty.
Interrupt Pending-This Interrupt-Pending bit is reset When an EO! command is
issued and there is no other interrupt request pending at that time. In vector
mode, this bit is set at the falling edge of
the second INTA in an INT A cycle for an
internal interrupt request. In non-vector
mode, this bit is set at the falling edge of
RD input after pointer 2 is specified. This
bit is always zero in Channel B.
Transmit Buffer Empty-This bit is set
whenever the transmit buffer is empty except when CRC characters are being sent
in a synchronous mode. This bit is reset
when the transmit buffer is loaded. This
bit is set after an MPSC reset.
Carrier Detect-This bit contains the state
of the CD pin at the time of the last
change of any of the ExternaVStatus bits
(CD, CTS, Sync/Hunt, Break!AbOrt, or
Tx Underrun/EOM). Any change of state
of the CD pin causes the CD bit to be
latched and causes an ExternaVStatus inter~ This bit indicates current state of
the CD pin immediately following a Reset
ExternaVStatus Interrupt command.
SYNDET-In asynchronous modes, the
operation of this bit is similar to the CD
status bit, except that it shows the state of
the SYNDET input. Any High-to-Low
transition on the SYNDET pin sets this
bit, and causes an ExternaVStatus interrupt (if enabled). The Reset ExternaV
2-361
D5
D7
Status Interrupt command is issued to
clear the interrupt. A Low-to-High transition clears this bit and sets the ExternaV
Status interrupt. When the ExternaV
Status interrupt is set by the change in
state of any other input or condition, this
bit shows the inverted state of the
SYNDET pin at time of the change. This
bit must be read immediately following a
Reset ExternaVStatus Interrupt command
to read the current state of the SYNDET
input.
Clear to Send-this bit contains the inverted state of the CTS pin at the time of
the last change of any of the ExternaV
Status bits (CD, CTS, Sync/Hunt, Break/
Abort, or Tx Underrun/EOM). Any
change of state of the CTS pin causes the
CTS bit to be latched and causes an ExternaVStatus interrupt. This bit indicates the
inverse of the current state of the CTS pin
immediately following a Reset ExternaV
Status Interrupt command.
Break-in the Asynchronous Receive
mode, this bit is set when a Break sequence (null character plus framing error)
is detected in the data stream. The ExternaVStatus interrupt, if enabled, is set
when break is detected. The interrupt
service routine must issue the Reset External/Status Interrupt command (WRO,
Command 2) to the break detection logic
so the Break sequence termination can be
recognized.
AP·134
Read Register 1 (RR1):
Mse
lse
lool~I~I~loo:~:~I~1
.. ' ,
'L All SENT
\
,L
NOT USED IN ASYNCHRONOUS MODES
PARITY ERROR
Rx OVERRUN ERROR
CRC/FRAMING ERROR
NOT USED IN ASYNCHRONOUS MODES
210311-14
The Break bit is reset when the termination of the
Break sequence is detected in the incoming data stream.
The termination of the Break sequence also causes the
ExtemaVStatus interrupt to be set. The Reset External/Status Interrupt command must be is~ued to enable
the break detection logic to look for the next Break
sequence. A single, extraneous null character is present
in the receiver after the termination of a break; it
should be read and discarded.
DO
All sent-this bit is set when all characters
have been sent. It is reset when characters
are in the transmitter. In synchronous
modes, this bit is always set.
04
Parity Error-if parity is enabled, this bit
is set for received characters whose parity
does not match the programmed sense
(Even/Odd). This bit is latched. Once an
error occurs, it remains set until the Error
Reset command is written.
Receive Overrun Error-this bit indicates
that the receive FIFO has been overloaded
by the receiver. The last character in the
FIFO is overwrittenand flagged with this
error. Once the overwritten character is
read, this error condition is latched until
05
Read Register 2 (RR2):
Mse
I va: vs :
V7 :
lse
V4' : V3' : V2': V1':
vo'l
'VarIable In
L'~nt..;,e_rr~uP..;,t_____ StatuI Affectl
Vector
Vector Mode (WR1 ; D2)
210311-15
06
RR2
reset by the Error Reset command. If the
MfSC is in the "status' affects vector"
mc;>de, the overrun causes a Special Receive Error Vector.
Framing Error-in async modes, a one in
this bit indicates a receive framing error.
It can be reset by issuing an Error Reset
command.
Channel B
07-00
2-362
Interrupt vector~ontains the interrupt
vector programmed into WR2. If the
"status affects vector" mode is selected, it
contains the modified vector. (See WR2.)
RR2 contains the modified vector for the
highest priority interrupt pending. If no
interrupts are pending, the variable bits in
the vector are set to one. May be read
from Channel B only.
inter
AP-134
APPENDIX B
MPSC-POLLED TRANSMIT/RECEIVE CHARACTER
ROUTINES
MPSC$RX$INIT: procedure (cmd$port,
clock$rate,stop$bits,parity$type,parity$enable,
rx$char$length,rx$enable,auto$enable,
tx$char$length, tx$enable, dtr, brk, rts) :
declare cmd$port
clock$rate
stop$bits
parity$type
parity$enable
rx$char$length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts
output(cmd$port)=30H:
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte:
f* channel reset *f
f* point to WR4 *f
output(cmd$port)=14H:
f* set clock rate, stop bits, and parity information */
output(cmd$port)=shl(clock$rate,6) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enable:
output(cmd$port)-13H:
f* point to WR3 *f
/* set up receiver parameters *f
output(cmd$port)=shl(rx$char$length,6) or rx$enable or shl(auto$enable,5):
output(cmd$port)=15H:
f* point to WR5 */
f* set up transmitter parameters *f
output (cmd$port) =shl (tx$char$length,5) or shl(tx$enable,3) or shl(dtr,7)
or shl(brk,4) or shl(rts,l),
end MPSC$RX$INIT,
210311-16
2·363
inter
;,,'
AP-134
'IPSC$POLL$RCV$CIIARACTER: procedure (da ta$por t, cmd$porl, ChM ~cter Sptr)
declare
d~t~Sport
cmdSport
character$ptr
character
status
declare char$avail
rcv$error
I)!t~,
byte,
byte,
poin~er,
based character $ptr byte,
byte,
literally '1',
literally '70H',
/* wait for input character ready */
while (input(cmd$port) and char$avail) <> 0 do, end,
/* check for errors in received character
output(cmd$port)=l,
if (status:=input(cmd$port) and rcv$error)
then do,
character=input(data$port) ,
call RECElVE$ERROR(cmd$port,status) ,
return 0;
*/
/* point to RRl */
/* read character to clear MPSC */
1* clear receiver errors
*/
/* error return - no character avail */
end,
else do:
character=input(data$port) ,
return OFFH,
end;
/* good return - character avall */
end MPSC$POLL$RCVSCHARACTER,
MPSC$POLL$TRAN$CHARACTER: procedure(data$port,cmd$port,character),
declare data$port
cmd$port
character
byte,
byte,
byte,
declare tx$buffer$empty literally '4',
/* wait for transmitter buffer empty */
while not (input(cmd$port) and tx$buffer$empty) do: end,
/* output character */
output(data$port)=character,
end MPSC$POLL$TRAN$CHARACTER,
RECElVE$ERROR: procedure(cmd$port,status) ,
declare cmd$port
status
output(cmd$port)=JOH,
byte,
byte:
1* error reset */
/* *** other application dependent
error processing should be placed here
*/
end RECElVE$ERROR,
210311-17
2-364
inter
AP·134
TRANSMIT$BUFFER: procedure(buf$ptr,buf$length)
declare
buf$ptr
bu f.$leng th
pointer,
byte;
j" set up transmit buffer pointer and buffer length in global variables for
interrupt service *1
tx$buffer$ptr=buf$ptr;
transmit$length=buf$length;
transmit$status=not$complete;
output(data$port)=transmit$buffer(O) ;
transmit$index=lj
/* setup status for not complete
j" transmit f,rst character "j
j" first character transmitted
~/
OJ
/* wait until transmission complete or error detected */
while transmit$status = not$complete do; end;
if transmit$status <> complete
then return false:
else return true;
end TRANSMIT$BUFFER;
RECEIVE$BUFFER: procedure (buf$ptr,buf$length$ptr);
declare
buf$ptr
pointer,
buf$length$ptr pointer,
buf$length
based buf$length$ptr byte;
j" set up receive buffer pointer in global variable for interrupt service "j
rx$buffer$ptr=buf$ptr;
receive$index=O;
receive$status=not$complete;
j" set status to not complete "j
j* wait until buffer received "j
while receive$status = not$complete do; end;
buf$length=receive$length;
if receive$status = complete
then return true;
else return false;
end RECEIVE$BUFFER;
210311-18
2-365
inter
Ap·134
APPENDIX C
INTERRUPT-DRIVEN TRANSMITIRECEIVE SOFTWARE
declare
j* global variables for buffer manipulation *j
rx$buffer$ptr
pointer,
j* pointer to receive buffer *j
receive$buffer based rx$buffer$ptr(12S) byte,
receive$status
byte initial(O),
j* indicates receive buffer status *j
receive$index
byte,
1* current index into receive buffer */
byte,
r ece i ve$leng th
j* length of final receive buffer *j
tx$buffer$ptr
pointer,
j* pointer to transmit buffer *j
transmit$buffer based tx$buffer$ptr(128) byte,
byte initial (0) ,
transmit$status
j* indicates transmit buffer status *j
byte,
transmit$index
j* current index into transmit buffer *j
transmit$length
byte,
/* length of buffer to be transmitted */
cmd$port
data$port
a$cmd$port
b$cmd$port
line$feed
not$complete
complete
overrun
channel$reset
er ror $reset
reset$ext$status
1 terally
1 terally
1 terally
1 terally
1 terally
1 terally
1 terally
1 terally
'43H' ,
'41H' ,
'42H' ,
'43H',
'OAH',
"0",
'OFFH',
"1",
1 terally 'lSH',
1 terally '30H' ,
1 terally 'lOH';
210311-20
2-366
inter
AP-134
MPSC$INT$INIT: procedure (clock$rate,stop$bits,parity$type,parity$enable,
rx$char$length,rx$enable,auto$enable,
tx$char$length,tx$enable,dtr,brk,rts,
ext$en,tx$en,rx$en,stat$affects$vector,
config,priority,vector$int$mode,int$vector) ;
declare
clock$rate
stop$bits
parity$type
parity$enable
rx$char$length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts
ext$en
tx$en
rx$en
stat$aff$vector
conf ig
prior ity
vector$int$mode
int$vector
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte;
output(b$cmd$port)=channel$reset;
/"
/"
/"
/"
/"
/"
/"
/"
/"
/"
/*
/"
/"
/"
/"
/"
/"
/"
/"
/"
2-bit
2-bit
I-bit
I-bit
2-bit
I-bit
I-bit
2-bit
I-bit
I-bit
I-bit
I-bit
I-bit
I-bit
2-bit
I-bit
2-bit
I-bit
3-bit
S-bit
code for clock rate divisor "/
code for number of stop bits "/
parity type "/
parity enable */
receive character length */
receiver enable */
auto enable flag */
transmit character length "/
transmitter enable "/
status of DTR pin "/
data link break enable "/
status of RTS pin "/
external/status enable */
Tx interrupt enable "/
Rx interrupt enable/mode "/
status affects vector flag "/
system config - int/DMA "/
priority flag "/
interrupt mode code "/
interrupt type code "/
/" channel reset "/
output(b$cmd$port)=l4H;
/" point to WR4 "/
/" set clock rate, stop bits, and parity information "/
output(b$cmd$port)=shl(clock$rate,6) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enable;
output(b$cmd$port)=13H;
/" point to I'iR3 "/
/" set up receiver parameters "/
output(b$cmd$port)=shl(rx$char$length,6) or rx$enable or shl(auto$enable,5);
output(b$cmd$port)=15H;
/" point to WR5 "/
/" set up transmitter parameters "/
output(b$cmd$port)=shl(tx$char$length,5) or shl(tx$enable,1) or shl(dtr,7)
or shl(brk,4) or shl(rts,l);
output(b$cmd$port)=l2H;
/" set up interrupt vector "/
output(b$cmd$port)=int$vector;
/" point to WR2 "/
output(a$cmd$port)=l2H;
/" point to WR2, channel A "/
/" set up interrupt modes "/
output(a$cmd$port)=shl(vector$int$mode,3) or shl(priority,2) or config;
output(b$cmd$port)=IIH;
/" point to WRI "/
/" set up interrupt enables "/
output(b$cmd$port)=shl(rx$en,3) or shl(stat$aff$vector,2) or shl(tx$en,l)
or ext$en;
end MPSC$INT$INIT;
210311-21
2-367
AP-134
MPSC$RECEIVESCIIARACTER$INT: procedure in tee rupt 2 2H:
/* ignore input if no open buffer */
If receive$status <> not$complete then return;
1* check for receive buffer overrun *1
if receive$index = 128
then receive$status=overrun:
else do:
1* read character from MPSC and place in buffer - note that the
parity of the character must be masked off during this step if
the character is less than 8 bits (e.g., ASCII) *1
receive$buffer(receiv~$index) ,character=input(data$port) and 7FH:
receive$index=receive$index+l:
/* update receive buffer lndex *1
1* check for line feed to end line *1
if character = line$feed
then do; receive$len9th=receive$index; receive$status=complete: end;
end:
end MPSC$RECElVE$CHARACTER$INT:
MPSC$TRANSMIT$CHARACTER$INT: procedure interrupt 20H:
1* check for more characters to transfer *1
if transmit$index < transmit$length
then do:
/* write next character from buffer to MPSC *1
outpUt(data$port)=transmit$buffer(transmit$index) :
transmit$index=transmit$index+l:
1* update transmit buffer index */
end:
else transmit$status=complete:
end MPSC$TRANSMIT$CHARACTER$INT,
RECEIVE$ERROR$INT: procedure interrupt 23H,
declare
temp
byte,
output(cmd$port)=l,
receive$status=input(cmd$port) ,
temp=input (data$port) ,
output(cmdSport)=error$reset,
1* temporary character storage *1
1* point to RRl
*/
1* discard character */
1* send error reset *1
1* *** other application dependent
error processing should be placed here
11
** * /
end RECElVE$ERROR$INT,
EXTERNALSSTATUS$CHANGE$INT: procedure interrupt 21H:
transmitSstatus=input(cmd$port)
output(cmd$port)=reset$ext$status:
1* input status change information
1* *** other application dependent
error processing should be placed here
***
*/
*/
end EXTERNALSSTATUSSCHANGESINT,
210311-19
2-368
inter
Ap·134
APPENDIX D
APPLICATION EXAMPLE USING SDK-86
This application example shows the 8274 in a simple
iAPX-86/88 system. The 8274 controls two separate
asynchronous channels using its internal interrupt controller to request all data transfers. The 8274 driver
software is described which transmits and receives data
buffers provided by the CPU. Also, status registers are
maintained in system memory to allow the CPU to
tnonitor progress of the buffers and error conditions.
THE HARDWARE INTERFACE
Nothing could be easier than the hardware design of-an
interrupt-driven 8274 system. Simply connect the data
bus lines, a few bus control lines, supply a timing clock
for baud rate and, voila, it's done! For this exatnple, the
ubiquitous SDK-86 is used as the host CPU system.
The 8274 interface is constructed on the wire-wrap area
provided. While discussing the hardware interface,
please refer to Diagram 1.
Placing the 8274 on the lower 8 bits of the 8086 data
bus allows byte-wide data transfers at even I/O addresses. For simplicity, the 8274's CS input is generated
by combining the M/IO select line with address line A 7
via a 7432. This places the 8274 address range in multiple spots within the 8086 I/O address space. (While
fine for this example, a more complete address decoding is recommended for actual prototype systems.) The
8086's Al and A2 address lines are connected to the AO
and Al 8274 register select inputs respectively. Although other port assignments are possible because of
the overlapping address spaces, the following I/O port
assignments are used in this example:
Port Function
Data channel A
Command/status A
Data channel B
Command/status B
1/0 Address
OOOOH
0002H
0004H
0006H
To connect the 8274's interrupt controller into the system an inverter and pull-up resistor are needed to convert the 8274's active-low, interrupt-request output,
INT, into the correct polarity for the 8086's INTR interrupt input. The 8274 recognizes interrupt-acknowledge bus cycles by connecting the INTA (INTerrupt
Acknowledge) lines of the 8274 and 8086 together.
The 8274 ReaD and WRite lines directly connect to the
respective 8086 lines. The RESET line requires an inverter. The system clock for the 8274 is provided by the
PCLK (peripheral clock) output of the 8284A clock
generator.
On the 8274's serial side, traditional 1488 and 1489 RS-
232 drivers and receivers are used for the serial interface. The onboard baud rate generator supplies the
channel baud rate timing. In this example, both sides of
both channels operate at the same baud rate although
this certainly is not a requirement. (On the SDK-86,
the baud rate selection is hard-wired thru jumpers. A
more flexible approach would be to incorporate an
8253 Programmable Interval Timer to allow softwareconfigurable baud rate selection.)
That's all there is to it. This hardware interface is completely general-purpose and supports all of the 8274
features except the DMA data transfer mode which requires an external DMA controller. Now let's look at
the software interface.
SOFTWARE INTERFACE
In this example, it is assumed that the 8086 has better
things to do rather than continuously run a serial channel. Presenting the software as a group of callable procedures lets the designer include them in the main body
of another program. The interrupt-driven data transfers
give the effect that the serial channels are handled in
the background while the main program is executing in
the foreground. There are five basic procedures: a serial
channel initialization routine and buffer handling routines for the transmit and receive data buffers of each
channel. Appendix D-1 shows the entire software listing. Listing line numbers are referenced as each major
_routing is discussed.
The channel initialization routine (INITIAL 8274),
starting with line #203, simply sets each channel into a
particular operating mode by loading the command
registers of the 8274. In normal operation, once these
registers are loaded, they are rarely changed. (Although
this example assumes a simple asynchronous operating
mode, the concept is easily extended for the byte- and
bit-synchronous modes.)
l
CONTROL
LINES
CONNECTOR
~ ADDRESS
BUS EXPANSION
CONNECTOR
):0
I\)
'P
lJ
-..j
004
o
c.:i
•
EXPANSION EXPANSION
SOCKET
SOCKET
LED DISPLAY
210311-22
(For detailed description on SDK-86, refer to SDK-86 MCS-86 System Design Kit Assembly Manual.) ~
inter
AP-134
SDK·88
EXPANSION
BUS
5V
751488
40
VCC
INTR
AD
WR
ilm
PCiJ(
38
28
41
22
48
21
50
27
38
2
12
D7
D5
D4
14
13
12
14
15
10
16
D3
17
D2
18
Dl
DO
RTSA
WR
RxDA
19
2
23
MilO
A2
A
ffiA
CDA
RESET
DB7 '
DTRA
DBI
DB5
751489
8274
TxDB
DB4
RTSB
DB3
DB2
RxDB
DBl
CTSB
CHANNEL
B
DBO
CDB
cs
DTRB
A7
Al
CHANNEL
INTA
ClK
RST
D8
TxDA
iNT
AD
6
25
8
24
AO
~
Al
RxCA
TxCiI
PI~:
__________________________-J
210311-23
Figure D-1. 8274/SDK-86 Hardware Interface
The channel operating modes are contained in two tables starting with line # 163. As the 8274 has only one
command register per channel, the remaining seven
registers are loaded indirectly through the WRO (Write
Register 0) register. The first byte of each table entry is
the register pointer value which is loaded into WRO
and the second byte is the value for that particular register.
The indicated modes set the 8274 for asynchronous operation with data characters 8 bits long, no parity, and
2 stop bits. An X16 baud rate clock is assumed. Also
selected is the "interrupt on all RX character" mode
with a variable interrupt vector compatible with the
8086/8088. The transmitters are enabled and all model
control lines are put i": their active state.
2-371
In addition to initializing the 8274, this routine also sets
up the appropriate interrupt vectors. The 8086 assumes
the first I K bytes of memory contain up to 256 separate
interrupt vectors. On the SDK-86 the initial 2K bytes
of memory is RAM and therefore must be initialized
with the appropriate vectors. (In a prototype system,
this initial memory is probably ROM, thus the vector
set-up is not needed.) The 8274 supplies up to eight
different interrupt vectors. These vectors are developed
from internal conditions such as data requests, status
changes, or error conditions for each channel. The initialization routine arbitrarily assumes that the initial
8274 vector corresponds to 8086 vector location 80H
(memory location 200H). This choice is arbitrary since
the 8274 initial vector location is programmable.
AP-134
Finally, the initialization routine sets up the status and
flag in RAM. The meaning and use of these locations
are discussed later.
Following the initialization routine are those for the
transmit commands (starting With line # 268). These
commands assume that the host CPU has initialized the
publicly declared variables for the transmit buffer
pointer, TX_POINTELCHx, and the buffer length,
T~LENGTH_CHx. The transmit command routines simply clear the transmitter empty flag, TX EMPTY CHx, and load the first character of the buffer into
the transmitter. It is necessary to load the first character in this manner since transmitter interrupts are generated only when the 8274's transmit data buffer becomes empty. It is the act of becoriting empty which
generates the interrupt not simply the buffer being empty, thus the transmitter needs one character to start.
The host CPU can monitor the transmitter empty flag,
T~EMPTY_CHx, in order to determine when
transmission of the buffer is complete. Obviously, the
CPU should only call the command routine after first
checking that the empty flag is set.
After returning to the main program, all transmitter
data transfers are handled via the transmitter-interrupt
service routines starting at lines # 360 and # 443. These
routines start by issuing an End-Of-Interrupt command
to the 8274. (This command resets the internal-interrupt controller logic of the 8274 for this particular vector and opens the logic for other internal interrupt requests. The routines next check the length count. If the
buffer is completely transmitted, the transmitter empty
flag, T~EMPTY _CHx, is set and a command is
issued to the 8274 to reset its interrupt line. Assuming
that the buffer is not completely transmitted, the next
character is output to the transmitter. In either case, an
interrupt return is executed to return to the main CPU
program.
The receiver commands start at'line # 314. Like the
transmit commands, it is assumed that the CPU has
initialized the' receive-buffer-pointer public variable,
RX-POINTELCHx. This variable points to the
first location in an empty receive buffer. The command
routines clear the receiver ready flag, R~READY_
CHx, and then set the receiver enable bit in the 8274
WR3 register. With the receiver' now enabled, any received characters are placed in the receive buffer using
interrupt-driven data transfers.
The received data service routines, starting at lines
#402 and #485, simply place the received character in
the buffer after first issuing the EOI command. The
character is then compared to an ASCII CR. An ASCII CR causes the routine to set the receiver ready flag,
RX~EADY _CHx, and to disable the receiver. The
CPU can interrogate this flag to determine when the
buffer contains a new line of data. The receive buffer
pointer, RX_POINTELCHx, points to the last received character and the receive counter, R~COUN
TELCHx, contains the length.
That completes our discussion of the command routines and their associated interrupt service routines. Although not used by the commands, two additional service routines are included for completeness. These routines handle the error and status-change interrupt vectors.
The error service routines, starting at lines # 427 and
# 510, are vectored to if a special receive condition is
detected by the 8274. These special receive conditions
include parity, receiver overrun, and framing errors.
When this vector is generated, the error condition is
indicated in RRI (Read Register 1). The error service
routine issues an EOI command, reads RRI and places
it in the ERROLMSG_CHx variable, and then issues a reset error command to the 8274. The CPU can
monitor the error message location to detect error conditions. The designer, of course, can supply his own
error service routine.
Similarly, the status-change routines (starting lines
#386 and #469) are initiated by a change in the modem-control status lines CTS/, CD/, or SYNDET/.
(Note that WR2 bit controls whether the 8274 generates interrupts based upon changes in these lines. Our
WR2 parameter is such that the 8274 is programmed to
ignore changes for these inputs.) The service routines,
simply read RRO, place its contents in the STATUS_
MSG_CHx variable and then issue a reset external
status command. Read Register contains the state of
the modem inputs at the point of the last change.
°
°
Well, that's it. This application example has presented
useful, albeit very simple, routines showing how the
8274 might be used to transmit and receive buffers using an asynchronous serial format. Extensions for byteor bit-synchronous formats would require no hardware
changes due to the highly programmable nature of the
8274's serial formats.
2-372
inter
AP-134
8274 APPLICATION BRIEF PROGRAM
ISIS-II /1:5-86 twI;R() AS5EItlLEF Y2 1 AS5EItlLY
OBJECT PIOOllE PLAC£O IN F1 AS\I(B OBJ
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,
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6
7
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14
15
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17
18
19
29
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23
24
8274 II'PllCATI(Ij BRIEF _
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,
" TIE 8274 IS INITIR.IZED F~ SIIflE AS'ItDm«lIS SETlIR.
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" TIE INITIALIZATION ROOTINE ALSO LOfI)S THE B8B6'S INTERRIJ>T
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" SIlI(-86 THE IRANSIUTTER AJ() RECEJIn ARE LEFT ENfB.ED
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•
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.
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2-373
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210311-24
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AP-134
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210311-26
2-375
inter
II( 5-86
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AP-134
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210311-27
2-376
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Ap·134
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FRCI1 PROM TO f'AM
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• INITIAl.IZE STATUS BYTES All, FLAGS
m
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210311-28
2-377
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MO'I
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327
32'3
329
330
m
332
m
334
ns
8SEf
SSEF 58
8SF8 52
85F1 C6863S82t18
85F6 (786328_
8SFCBftIl2e8
8SFF B003
8681 EE
Il682 secl
8604 EE
0685 SA
868658
8687 C3
336
337
330
339
,""****.***".******•••****."'***"'***.*.*" •• '1<**** ..,. ~
+0 . . . . . . . . -t: ..........
~
"
,,
"
,•
RX COIttfI/(l FOR ClRf£L A - THE CALLINii fl)JTlNE MUST
INlTlALIZE RXJ>OINTEUHA TO POINT AT THE RECEIVE
BUFFER BEFORE CfLUNG THIS ROllTlNE
"
RX_C _ _ CIfI
PUSH
PUSH
Ill\'
348
MOV
341
342
tll'I
I1IJII
343
OOT
110'1
OOT
144
345
346
f'(l'
f'(l'
347
~~
,SAVE I1EGISTEPS
OX
RX-READUHA, 8 ,CLEfifl fIX REIH FLAG
RX_CCWUIfI, 8 ,(LEAl> RX WJNTER
Ox, CIl1f1fH)_POPLCHA
,POINT AT I.CltlANI) f'IlPT
fL, 3
,SET UP FOR WIC
OX, fL
fL, OC1H
dIP? - 8 BITS,tlfl, E'fIBLE R:'
[)X, fL
DX
A;;
348
RET
349
359 +1 fEJECT
,I1ET~
351
352
353
354
355
356
357
"
35e
,CIIIHfiL 8 TRfIHSItlT DATA SEl/lliCE roJTlI£
START Of INTERRlfT SEI/IIICE ROUTINES
"
359
868852
868957
868A 58
_E862lI1
_ FF06281!2
8612 FF8Em2
0616 748£
0618_
0618
061F 8B3E2002
_
0621 EE
362
XMTIIf! PUSH
PUSII
PUSH
363
CfLL
364
INC
369
361
365
DEC
366
367
JE
110'1
368
369
3711
110'1
OOT
/IOV
DX
,SAVE
REGISTE~
01
AX
EOI
' SENO EOI COItIff«) TO 82,4
TX_POINTER_CHI! ,POINT TO NEXT CNARAl:TER
TILLENGTH_CHI! ,DEC LENIlTH [(OJNTER
XIS
,TEST IF DOlE
DX, DATA_POPUH8
,NOT [>(IN( - GET NE,T CHfIPfl( TEP
01, TX]OINTEP_CHIl
fL, [vll
,PIJT CIlARAl:TEP IN AL
DX, AL
,OIJTPliT IT TO 8274
210311-30
2-379
inter
AP-134
ItCS'86 ItACR() AS5EI1BLER
AS'INCB
LOC ooJ
LIlt:
8622 58
371
8623
8624
B625
862.
8629
8628
B62C
8631
8632
8633
8634
374
375
376
377
378
379
389
381
382
51'
5A
CF
BAe68e
802S
EE
C6B62802S1
58
51'
5A
CF
m
373
383
384
8635 52
8636 57
8637 58
8638 EIJI)';88
8638_
863E EC
863F A22A92
0642 Be10
0644 EE
064~ 58
8646 Sf
,0647 5A
064S CF
0649 52
1164A 57
864858
864( EOC1Be
064f 88:>£2492
385
386
387
388
389
398
m
m
;91
XIS
f'(J>
f'(J>
f'(J>
AX
DI
OX
lRET
/flV
ItO\I
•RETlIIN TO FOREGRIJIJND
OX, m1lfHHORLCHB
,fU CHffIACTERS HAVE SEEN SEND
fl. 2SH
. RESfT TRff6IIlTm INTERru'T PEIf·ING
DX. AI.
TX.EIf'TY.CHIl, 1 . DOOE • 50 SET TX EIf'TY FLM (He
AX
•RESTOI1E REGISTEI1S
01
DX
· RETURN TO FOREGRC'JND
IXJT
ItO\I
f'(J>
PIJ>
f'(J>
lRET
,CIftf£L B STATUS CIflNlE SET1I'IU ROOTlI£
STAINB PUSH
PUSH
PUSH
CALL
ItO\I
IN
/flY
I10V
OUT
POP
394
395
3%
POP
39i'
POP
]!IS
399
400
oIe1
402
DX
,SAVE REGISTERS
01
AX
EOI
,S£NI) EOI COI1/IAHlI TO 9274
OX, ~J'(~UHll
fl. DX
'REff> RRO
5TATlIS."S(LCHB. fl
. PlJT RRe IN STATUS I1ESSAGE
Al. 1!IH
. SE'" RESET STATUS INT COI'II'IAN{l TO 8274
Ox, AI.
AX
. RESTORE REGISTEI1S
DI
OX
lRET
. rHANlt:L B REUlVED MTA
PCYINB PUSH
OX
404
PUSH
PUSH
fI);
405
406
CAlL
HOV
0653 BA04ee
4e~
PIOV
8656 EC
865~ 8805
0659 FF862402
e65!' FF062602
8661 ~(OO
866, ~5eE
0665 C~ge201
498
499
HOV
e60A BA0608
B0ll,
866f EE
0670 BOC0
%,~' EE
066(.
06i'} 58
0674 51'
06;5 SA
%76 CF
483
IN
11K
IN(
410
411
412
41:
414
415
41<
('Mf'
JNE
MY
MOV
I1QY
41i'
WT
418
419
I1QY
4~0
4cl
422
42,
424
4.25
•RESTORE REGISTEI1S
('.IT
RIo
SE~'YI(E
ROUTlI£
· SRI!
~fGISTEPS
Vi
E,JI
,SfN{l £OJ (otf1AH[! TO 827'4
DI. RX.POINTER.CHB
. (£1 R:-: (HS ['HEP POINTEP
I'X. MTA.POPLOIB
ft.. [):~
· REAl' CHAm: TEP
[DI J. AI.
· STOff IN BlIFFEP
~>:.POINTEP .CHB · SIJPiP THE SUFFEP fOlllTEP
· BI.~IP THE WJNTU
P'.COIJNUHB
AI.. [P.(1f'
· TEST '[F LAST (HAP"CTEF' TO [:E 'fen··iE['
RIB
P'•.PEflUUHE.. 1 .'IE5. SET PEAl·Y FLAG
D:j. (OII'IffI['.P[~UHB
,htHH AT (l)M/o1f11(1 F'fIPT
Al.
.POIlIT AT NO,
['X. Ai.
At. 0C!IH
· ['ISABLE p,-:
[·x. Ai.
FOf'
Hi.
POP
POF'
[,[
EITHEF Wfi'T' '!O'E3TOPE
F·£IjI':TEF'~
v.'
I~1
· PETUPN TO F(IFFjPOIJNf
. ':HAlfNEL E. EPROI' 3EPVICE Rl'JTlHE
4;:t:
52
96;'8 59
.:w.;(~
,"
428
PUSH
11(;
0';;'~
ES94ee
42~
(AlL.
H I , SEN[- Em COt'1"1Atlf, TO
06~(
Bfl(1)5OO
4~0
~lOV
[,>;. ((If'1I'fAI.,_POH JHP
':,2~,r
.
210311-31
2·380
inter
AP-134
II:S-86 Ift:I!O ASSEII!I.ER
ASYNCB
LOC
(8J
LIfE
86/F
8681
8682
8683
BIl81
EE
EC
fI22II82
_BBJ8
86BBEE
_58
86BR SA
86BB CF
soo.m
4J1
432
433
434
435
436
437
438
439
1
,.".
~,
OOT
IN
I)l(,~
,.".
,.".
ERR\IUtSI:LCIII,
~, 38H
DI(, ~
fIX
OOT
POP
POP
~,I»(
,POINT RT RfU
.REfI) RRI
.5IWE IT IN EIIROi FUll
•SENII RESET ERRt* C(»IIfM\ TO 8274
~
•RESTORE REGISTERS
I»(
IRET
,R£MN TO F!W!EGIIOIN)
+48
868C 52
86BD 57
_58
86BF E87E88
8692 FFIl62C82
8696 FF8E2E82
86!IR 748E
869C IIfI888II
869F 883£2t82
86R3 8fI85
86115 EE
_58
86R7 SF
_SR
86R9CF
I!6Itl 1118288
86fI) B928
il6IF EE
86B8 C686:i48281
86B5 58
_51'
8687 SA
86B8 CF
e6B~
52
_5~
86B8 58
868C
E85188
_ BR8288
86C2 EC
06C: A2>682
II6C6 8818
e.;cs EE
86(~ 58
IlOCR SF
86CB SA
(liCe
CF
et.CD 52
86CE 57
86CF 58
90108 E8:D88
901·;
ee,E882
86£0<_
441
442
443
444
445
446
447
+48
449
458
451
452
453
454
455 •
456
457
458
459
468
401
46.l
46;
464
465
466
467
468
469
478
471
4;2
4iJ
474
475
4,6
4(7
478
4/9
488
481
482
483
484
485
486
-IS7
,CIfH£L R TRfINSIfIT DATR SERVICE RWTJfE
lIIITlNA PUSH
PUSH
PUSH
CfLL
1M:
DEC
JE
HOV
,.".
HOY
ruT
POP
POP
POP
XIR
I»(
,SllYE REGISTERS
DI
fIX
EOI
TXJ'OINTElU)fI
TILLENGTlLCifl
XIR
,SEIC> EOI COIftI) TO 8274
,POINT TO I£XT ClflRK.TE11
· DEC LE/liTH C(MTE11
·TEST IF OM
1»(. DATR~T..CHR
.I(IT OM - GET NEXT CIflRflCTER
01, TXJ'OINTEILtHR
~, [DJJ
· PUT CIfIlOCTER IN ~
1»(. ~
· OOTPUT IT TO 8274
fIX
· RESTORE i1£GISTERS
01
I»(
IRET
HOY
OX.
COIftI)~Ulfl
,.".
~.
28H
ooT
fh(.
~
ItO'!
POP
POP
TX_EII'TV_CIfI. 1 ,DONE - so SET TX EItPTV FLfIl CHB
AX
· RESTI)I1E REGISTERS
01
POP
I»(
· RETlI1N TO F!W!EilRtUI'
IRET
,~ ~TE11S HR\IE BEEN SEN[>
.RESET _mER INTE11!1lI'T P£J{'11fj
,11E1U1H TO FOf1EGRCU{·
•CHRN£L R STRTUS CIM'£ SEWICE 1l(l.ITI1£
STAINR Pl.lSI!
PUSH
[.j
PUSH
AX
CfLL
EOI
.SEH[· EOI COI'I1A/{· TO 8~~4
OX. rntItRI{·_POPLCHR
~. OX
.REII' PI10
STATUS_~S(UHR. II.
. PUT P/10 IN 5TATUS ~SSfllE
11.. Illi
· SEN[· I1ESEI STAIUS INT (CltIA!{! TO S2~'
~X. II.
AX
· RESTOI1E REGISTEPS
01
HOV
IN
HOY
HOY
OUT
POP
POP
POP
~x
.5IWE PEGISTERS
&lI
IRET
CHfIff£L A RECElVE[' ['AIA SEPVICf; ROUTINE
Pel/[NA PUSH
~x
PUSH
~I
PUSI!
· SR\lE PEGISTERS
498
(II.L
AX
EOI
4~
ItO\
[.j.
4"8
ItO\I
t·;,. DRTAJ'OI'UHR
SEN[· EOI COftlAN[· TO ~2~4
I>.'-POINT'UHR
. GET P;: (itA B1JfFEP P.lINTE'
210311-32
2-381
inter
AP-134
H($-t«:> f1H(1'\J H>,ElRfR
ASI'NCB
LOC OBJ
LINE
iI60ft EC
491
I!6DB
492
493
8ge5
I!6I)(l FFIl63882
86£1 FFIl632B2
1l6E53C81)
Il6E775IIE
1l6E9 1:61l6358291
Il6EE BAe200
Il6Fl1l883
B6F:; EE
1l6F4~
86F6 EE
1l6F,58
1l6F85F
B6F9 SA
B6FA CF
IN
I10V
11£
11£
494
495
4%
C!1P
JIE
IfJ'I
I'IIY
m
498
499
5eB
5e1
502
583
HOY
RIA
584
58';
51!6
OOT
I10V
OUT
POP
POP
POP
IPET
AL, DX
. REfIC- CHAFf!( TEP
CD J1. II.
•STWO IN BUFFE~
RX_POINTER..ofl. BIN Ttf BUFFER POINTE~
~U\wT _CNA
. BIN TI£ c\wTE~
Ill, CIUHk
. TEST IF LAST C~TER TO BE RECElVEI"
RIA
~x..REfK)~ _CNA. I ,YES, SET IlEfI(,~ FLAG
OX, C_'_P~LCHR
. POINT AT (0_ POPT
Fl, 3
,POINT AT 1iR3
DX, II.
11., OCeH
,OI5fI8lE RX
DX. AI.
AX
. EITI£~ 1IfI(, 'IIESTOfIE FEGI5TEI1S
01
DX
. RETl.fN TO F~GROI.I«o
587
588
,CHfltt:L A ~ SERVICE 11«.lTJIE
5e9
Il6FB S2
ll6Fe 511
Il6FD ESlBee
9788_
8783 11881
8705 EE
87116
8787
878A
B70C
EC
A2:;m
8838
EE
8i'8ll 58
8i'9E SA
871!F CF
518
ERRINA PUSH
PUSH
511
512
513
514
515
516
517
518
CALL
HOI'
IIOY
OUT
IN
I10V
IIOY
OUT
519
528
521
522
523
524
525
526
8719 58
527
8711 52
8712_
0715 8838
8717 EE
8718 SA
0719 58
07/A C3
528
529
5>11
POP
POP
lRET
,SAVE REGISTERS
AX
; SEt«> EOI COIIIfMl TO 8274
COltlflND_PORLCNA
I
,POINT AT RRI
II.
OX
,READ RRI
~-'IS('_CNA. II.
•SAVE IT IN ERROR FLAG
11., 3BH
• SEt«> RESET ERROIl COllltAh\) TO 8274
Ox. II.
AX
,RESTOIIE REGISTERS
OX
. RETl.fN TO FOREGI1Ol..,
,EIf>-OF-INTERRIPT ROUTINE - SEM>S EOI C _ TO 8274
, THIS CIlWft) /lUST II.WAYS TO ISst£O ON CHANHfL A
EOI
PUSH
PUSH
lIlY
lIlY
531
OUT
532
POP
POP
533
534
ox
EOI
DX,
11.,
OX,
11.,
AX
. SAVE REGISTEI1S
DX
OX. CIlItlANILPORUHA
,ALWAYS F!J1 CHANHfL A '"
fl, 3BH
OX, AI.
OX
AX
RET
535
536
537
538
•EM> OF CODE ROUTlIE
5;9
EJ{>
fI8C
ENIoS
ASSEI18LY CMlETE, NO ERROIlS FrwD
210311-33
REFERENCES
1. 8274 Multiprotocol Serial Controller (MPSC) Data
Sheet, Intel Corporation, California, 1980.
2. Basics of Data Communication, Electronics Book
Series, McGraw-Hill, New York, 1976.
3. Telecommunications and the Computer, J. Martin,
Prentice-Hall, New Jersey, 1976.
4. Technical Aspects of Data Communications, J. McNamara, DEC Press, Massachusetts, 1977.
5. Miscellaneous Data Communications StandardsEIA RS-232-C, EIA RS-422, EIA RS-423, EIA
Standard Sales, Washington, D.C.
2-382
inter
APPLICATION
NOTE
AP-145
November 1986
Synchronous Communication with
the 8274 Multiple Protocol
Serial Controller
SIKANDAR NAQVI
APPLICATION ENGINEER
Order Number: 210403-001
2-383
Ap·145
INTRODUCTION
The INTEL 8274 is a Multi-Protocol Serial Controller,
capable of handling both asynchronous and synchronous communication protocols. Its programmable features allow it to be configured in various operating
modes, providing opimization to given data communication application.
This application note describes the features of the
MPSC in Synchronous Communication applications
only. It is strongly recommended that the reader read
the 8274 Data Sheet and Application Note AP134
"Asynchronous Communication with the 8274 MultiProtocol Serial Controller" before reading this Application Note. This Application note assumes that the reader is familiar with the basic structure of the MPSC, in
terms of pin description, ReadIWrite registers and
asynchronous communication with the 8274. Appendix
A contains the software listings of the Application Example and Appendix B shows the MPSC ReadIWrite
Registers for quick reference.
The first section of this application note presents an
overview of the various synchronous protocols. The
second section discusses the block diagram description
of the MPSC. This is followed by the description of
MPSC interrupt structure and mode of operation in the
third and fourth sections. The fifth section describes a
hardware/software example, using the INTEL single
board computer iSBC88/45 as the hardware vehicle.
The sixth section consists of some specialized applications of the MPSC. Finally, in section seven, some useful programming hints are summarized.
SYNCHRONOUS PROTOCOL
OVERVIEW
This section presents an overview of various synchronous protocols. The contents of this section are fairly
tutorial and may be skipped by the more knowledgeable
reader.
Bit Oriented Protocols Overview
Bit oriented protocols have been defined to manage the
flow of information on data communication links. One
of the most widely known protocols is the one defined
by the International Standards Organization: HDLC
Opening
Flag
Byte
Address·
Field (A)
(High Level Data Link Control). The American Standards Association's protocol, ADCCP is similar to
HDLC. CCITT Recommendation X.25 layer 2 is also
an acceptable version of HDLC. Finally, IBM's SDLC
(Synchronous Data Link Control) is also a subset of the
HDLC.
In this section, we will concentrate most of our discussion on HDLC. Figure I shows a basic HDLC frame
format.
A frame consists of five basic fields: Flag, Address,
Control, Data and Error Detection. A frame is bounded by flags-opening and closing flags. An address field
is 8 bits wide, extendable to 2 or more bytes. The control field is also 8 bits wide, extendable to two bytes.
The data field or information field may be any number
of bits. The data field mayor may not be on an 8-bit
boundary. A powerful error detection code called
Frame Check Sequence contains the calculated CRC
(Cycle Redundancy Code) for all the bits between the
flags.
ZERO BIT INSERTION
The flag has a unique binary bit pattern: 7E HEX. To
eliminate the possibility of the data field containing a
7E HEX pattern, a bit stuffing technique called Zero
Bit Insertion is used. This technique specifies that during transmission, a binary 0 be inserted by the transmitter after any succ;:ession of five contiguous binary I's.
This will ensure that no pattern of 0 I I 1 1 1 lOis ever
transmitted between flags. On the receiving side, after
receiving the flag, the receiver hardware automatically
deletes any 0 following five consecutive I's. The 8274
performs zero bit insertion and deletion automatically
in the SDLC/HDLC mode. The zero-bit stuffing ensures periodic transitions in the data stream. These
transitions are necessary for a phase lock circuit, which
may be used at the receiver end to generate a receive
clock which is in phase to the received data. The inserted and deleted O's are not included in the CRC checking. The address field is used to address a given secondary station. The control field contains the link-level control information which includes implied acknowledgement, supervisory commands and responses, etc. A
more detailed discussion of higher level protocol functions is beyond the scope of this application note. Interested readers may refer to the references at the end of
this application note.
Control'·
Field (C)
Data
Field
Figure 1. HDLC/SDLC Frame Format
"Extendable to 2 or More Bytes.
"" Extendable to 2 Bytes.
2-384
Frame
Check
Sequence
Closing
Flag
Byte
inter
AP-145
The data field may be of any length and content in
HDLC. Note that SDLC specifies that data field be a
multiple of bytes only. In data communications, it is
generally desirable to transmit data which may be of
any content. This requires that data field should not
contain characters which are defined to assist the transmission protocol (like opening flag 7EH in HDLC/
SDLC communications). This property is referred to as
"data transparency". In HDLC/SDLC, this code
transparency is made possible by Zero Bit Insertion discussed earlier and the bit oriented nature of the protocol.
The last field is the FCS (Frame· Check Sequence). The
FCS uses the error detecting techniques called Cyclic
Redundancy Check. In SDLC/HDLC, the CCITICRC must be used.
NON-RETURN TO ZERO INVERTED (NRZI)
NRZI is a method of clock and data encoding that is
well suited to the HDLC protocol. It allows HDLC
protocols to be used with low cost asynchronous modems. NRZI coding is done at the transmitter to enable
clock recovery from the data at the receiver terminal by
using standard digital phase locked loop techniques.
NRZI coding specifies that the signal condition does
not change for transmitting a 1, while a causes a
change of state. NRZI coding ensures that an active
data line will have transition at least every 5-bit times
(recall Zero Bit Insertion), while contiguous O's will
cause a change of state. Thus, ZBI and NRZI encoding
makes it possible for a phase lock circuit at the receiver
end to derive a receive clock (from received data) which
is synchronized to the received data and at the same
time ensure data transparency.
°
Byte Synchronous Communication
As the name implies, Byte Synchronous Communication is a synchronous communication protocol which
means that the transmitting station is synchronized to
the receiving station through the recognition of a special sync character or characters. Two examples of Byte
Synchronous protocol are the IBM Bisync and MonoSYNC
SYNC
SOH
HEADER
sync. Bisync has two starting sync characters per message while monosync has only one sync character. For
the sake of brevity, we will only discuss Bisync here.
All the discussion is valid for Monosync also. Any exceptions will be noted. Figure 2 shows a typical Bisync
message format.
The Bisync protocol is defined for half duplex communication between two or more stations over point to
point or multipoint communication lines. Special characters control link access, transmission of data and termination of transmission operations for the system. A
detailed discussion of these special control characters
(SYN, ENQ, STX, ITB, ETB, ETX, DLE, SOH,
ACKO, ACK1, WACK, NAK and EOT,'~tc) is beyond
the scope of this Application Note. Readers interested
in more detailed discussion are directed to the references listed at the end of this Application Note.
As shown in Figure 2, each message is preceded by two
sync characters. Since the sync characters are defined
at the beginning of the message only, the transmitter
must insert fill characters (sync) in order to maintain
synchronization with the receiver when no data is being
transmitted.
TRANSPARENT TRANSMISSION
Bisync protocol requires special control characters to
maintain the communication link over the line. If the
data is EBCDIC encoded, then transparency is ensured
by the fact that the field will not contain any of the
bisync control characters. However, if data does not
conform to standard character encoding techniques,
transparency in bisync is achieved by inserting a special
character DLE (Data Link Escape) before and after a
string of characters which are to be transmitted transparently. This ensures that any data characters which
match any of the special characters are not confused for
special characters. An example of a transparent block is
shown in Figure 3.
In a transparent mode, it is required that the CRC
(BCC) is not performed on special characters. Later on,
we will show how the 8274 can be used to achieve
transparent transmission in Bisync mode.
STXTEXT
ETXOR ETB
CRC1
CRC2
ETX
BCC
Figure 2. Bisync Message Format
DLE
STX
Enter transparent mode
TRANSPARENT TRANSMISSION
DLE
return to normal mode
Figure 3. Bisync Transparent Format
2-385
inter
AP-145
each
BLOCK DIAGRAM
channel:
TxDRQA, TxDRQB, RxDRQA,
that TxDRQB and RxDRQa,2,ecome
IPO and IPI respectively in non-DMA mode. IPI is the
Interrupt Priority Input and IPO is the Interrupt Priority Output. These two pins can be used for connecting
multiple MPSCs in a daisy chain. If the Wait Mode is
programmed, then TxRDQA and RxDRQA pins become RDYB and RDYA pins. These pins can be wireOR'ed and are usually hooked up to the CPU RDY
line to synchronize the CPU for block transfers. The
INT pin is activated whenever the MPSC requires CPU
attention. The INTA may be used to utilize the powerful vectored mode feature of the 8274. Detailed discussion on these subjects will be done later in this Application Note. The RESET pin may be used for hardware
reset while the clock is required to click the internal
logic on the MPSC.
RxDRQ~ote
This section discusses the block diagram view of the
8274. The CPU interface and serial interface is discussed separately. This will be followed by a hardware
example in the fifth section, which will show how to
interface the 8274 with the Intel CPU 8088. The 8274
block diagram is shown in Figure 4.
CPU Interface
The CPU interface to the system interface logic block
utilizes the AO, AI, CS, RD and WR inputs to communicate with die internal registers of the 8274. Figure 5
shows the address of the internal registers. The DMA
interface is achieved by utilizing DMA request lines for
r----------,
CHANNEL A
TxDA
CHANNEL A
TRANSMITTER
DaO·7
TxCA
CHANNEL A
WRITE
REGISTERS
DCO'A
CLK
RESET
RDYalTxDRoA
I
!
"':::::;::::::::::::::)1
f'\
CTSA
CHANNEL
CONTROLA
LOGIC
RTSA
SYNDETA
ROY AIRxDRoA
~
IPOITxDRoa
IP11RxDRoa
INT
DTRA
1/\--'---' CHANNEL A
READ
C
REGISTERS
SYSTEM
INTERFACE
CONTROL
LOGIC
a
~ ~~::::::::::::~
RxDA
CHANNEL A
RECEIVER
RxCA
m
INTA
Ao
A1
TxDa
+f
TxCa
DCDa
CHANNEL a
CTSa
{
SYSTEM INTERFACE
SYNDETa
RTSa
!mra
RxCa
RxDa
NETWORK INTERFACE
210403-1
Figure 4. 8274 Block Diagram
2-386
inter
Ap·145
CS
0
0
A1
0
0
0
0
1
Write Operation
AO
0
0
CHA
CHA
DATA READ
STATUS REGISTER
(RRO,RR1)
CHA DATA WRITE
CHA COMMAND/PARAMETER
(WRO-WR7)
1
1
1
CHB
CHB
DATA READ
STATUS REGISTER
(RRO,RR1,RR2)
CHB DATA WRITE
CHB COMMAND/PARAMETER
(WRO-WR7)
X
X
HIGHZ
1
Read Operation
HIGHZ
Figure 5. Bus Interface
Serial Interface
Transmit and Receive Data Path
On the serial side, there are two completely independent channels: Channel A and Channel B. Each chan-
Figure 6 shows a block diagram for transmit and receive data path. Without describing each block on the
diagram, a brief discussion of the block diagram will be
presented here.
nel consists of a transmitter block, receiver block and a
set of read/write registers which are used to initialize
the device. In addition, a control logic block provides
the modem interface pins. Channel B serial interface
logic is a mirror image of Channel A serial interface
logic, except for one exception: there is only one pin for
RTSB and SYNDETB.
A a given time, this pin is either RTSB or SYNDETB.
This mode is programmable through one of the internal
registers on the MPSC.
TRANSMIT DATA PATH
The transmit data is transferred to .the twenty-bit serial
shift register. The twenty bits are needed to store two
bytes of sync characters in bisync mode. The last three
bits of the shift register are used to indicate to the internal control logic that the current data byte has been
shifted out of the shift register. The transmit data in the
CPU I 0
TxOA
TxCA
210403-2
Figure 6. Transmit and Receive Data Path
2-387
inter
AP-'f45
transmit shift register is shifted out through a two bit
delay onto the TxData line. This two bit delay is used
to synchronize the internal shift clock with the external
transmit clock. The data in the shift register is also
presented to zero bit insertion logic which inserts a zero
after sensing five contiguous ones in the data stream. In
parallel to all this activity, the eRe-generator is computing eRe on the transmitted data and appends the
frame with eRe bytes at the end of the data transmission.
RECEIVE DATA PATH
The received· data is passed through a one bit delay
before it is presented for flag/sync comparison. In bisync mode, after the synchronization is achieved, the
incoming data bypasses the sync register and enters directly into the three bit buffer on its way to receive shift
register. In SDLe mode, the incoming data always
passes through the sync register where the data pattern
is continuously monitored for contiguous ones for the
FIRST DATA CHARACTER
FIRST NON-SYNC
CHARACTER (SYNC MODES)
INTERRUPT
ON FIRST RECEIVE
CHARACTER
VALID ADDRESS
BYTE (SDLC)
INTERRUPT ON
ALL RECEIVE
CHARACTERS
PARITY ERROR
RX. OVER-RUN ER~OR
FRAMING ERROR
SPECIAL
RECEIVE
CONDITION
INTERRUPT
END OF FRAME
(SDLCONLY)
DCD TRANSITION
MPSC
INTERRUPTS
CTS TRANSITION
SYNC TRANSITION
TX UNDER-RUN/EOM
BREAK/ABORT DETECT
TRANSMIT
INTERRUPT
TX BUFFER EMPTY
210403-3
Figure 7. MPSC Interrupt Structure
2-388
inter
AP-145
zero deletion logic. The data then enters the three bit
buffer and the receive shift register. From the receive
shift register, the data is transferred to the three byte
deep FIFO. The data is transferred to the top of the
FIFO at the chip clock rate (not the receiver clock). It
takes three chip clock/periods to transfer data from the
serial shift register to the top of the FIFO. The three bit
deep Receive Error FIFO shifts any error condition
which may have occurred during a frame reception.
While all this is happening, the CRC checker is checking the CRC on the incoming data. The computed
CRC is checked with the CRC bytes attached to the
incoming frame and an error generated under a nocheck condition. Note that the bisync data is presented
to the CRC checker with an 8-bit delay. This is necessary to achieve transparency in bisync mode as will be
shown later in this Application Note.
MULTI-PROTOCOL SERIAL
CONTROLLER (MPSC) INTERRUPT
STRUCTURE
The MPSC offers a very powerful interrupt structure,
which helps in responding to an interrupt condition
very quickly. There are mUltiple sources of interrupts
within the MPSC. However, the MPSC resolves the
priority between various interrupting sources and interrupts the CPU for service through the interrupt line.
This section presents a comprehensive .discussion of all
the 8247 interrupts and the priority resolution between
these interrupts.
All the sources of interrupts on the 8274 can be
grouped into three distinct categories. (See Figure 7.)
1. Receive Interrupts
2. Transmit Interrupts
3. ExtemallStatus Interrupts.
An internal interrupt priority structure sets the priority
between the. interrupts. There are two programmable
options available on the MPSC. The priority is set by
WR2A, D2 (Figure 8).
PRIORITY
WR2A:D2
Highest
0
RxA
RxA
1
Lowest
TxA RxB TxB EXTA EXTB
AxB TxA TxB EXTA EXTB
Figure 8. Interrupt Priority
Receive Interrupt
All receive interrupts may be categorized into two distinct groups: Receive Interrupt on Receive Character
and Special Receive Condition Interrupts.
RECEIVE INTERRUPT ON RECEIVE
CHARACTER
A receive interrupt is generated when a character is
received by the MPSC. However, as will be discussed
later, this is a programmable feature on the MPSC. A
Rx character available interrupt is generated by the
MPSC after the receive character has been assembled
by the MPSC. It may be noted that in DMA transfer
mode too, a receive interrupt on the first receive character should be programmed. In SDLC mode, if address search mode has been programmed, this interrupt
will be generated only after a valid address match has
occurred. In bisync mode; this interrupt is generated on
receipt of a character after at least two valid sync characters. In monosync mode, a character followed after at
least a single valid sync character will generate this interrupt. An interrupt on first receive character signifies
the beginning of a valid frame. An end of the frame is
characterized by an "End of Frame" Interrupt (RR1:
D7).' This bit (RR1:D7) is set in SDLC/HDLC mode
only and signifies that a valid ending flag (7EH) has
been received. This bit gets reset either by an "Error
Reset" command (WRO: D5D4D3 = 110) or upon reception of the first character of the next frame. In multiframe reception, on receiving the interrupt at .the
"End of Frame" the CPU may issue an Error Reset
command which will reset the interrupt. In DMA
mode, the interrupt on first receive character is accompanied by a RxDRQ (Receiver DMA request) on the
appropriate channel. At the end of the frame, an End of
Frame interrupt is generated. The CPU may use this
interrupt to jump into a routine which may redefine the
receive buffer for the next incoming frame.
'NOTE:
RR1:D7 is bit D7 in Read Register 1.
SPECIAL RECEIVE CONDITION. INTERRUPTS
So far, we have assumed that the reception is error free.
But this is not 'typical' in most real life applications.
Any error condition during a frame reception generates
yet another interrupt-special receive condition interrupt. There are four different error conditions which
can generate this interrupt.
(i) Parity error
(ii) Receive Overrun error
(iii) Framing error
(iv) End of Frame
(i) Parity error: Parity error is encountered in asynchronous (start-stop bits) and in bisync/monosync protocols. Both odd or even parity can be programmed. A
parity error in a received byte will generate a special
receive condition interrupt and sets bit 4 in RR 1.
2-389
inter
AP-145
(ii) Receive Overrun error: If the CPU or the DMA
controller (in DMA mode) fails to read a received character within three byte times after the received character interrupt (or DMA request) was generated, the receiver buffer will overflow and this will generate a special receive condition interrupt and sets bit 5 in RR 1. '
(iii) Framing error: In asynchronous mode, a framing
error will generate a spt;<;iaJ receive interrupt and set bit
D6 in RR1. This bit is not latched and is updated on
the next received character.
(iv) End of frame: This interrupt is encountered in
SDLC/HDLC mode only. When the MPSC receives
the closing flag, it generates the special receive condition interrupt and sets bit D7 in'RRI.
All the special receive condition interrupts may be reset
by issuing an Error Reset Command.
CRC Error: In SDLC/HDLC and synchronous modes,
a CRC error is indicated by bit D6 in RR1. When used
to check CRC error, this bit is normally set until a
correct CRC match is obtained which resets this bit.
After receiving a frame, the CPU must read this bit
(RRI:D6) to determine if a valid CRC check had occurred. It may be noted that a CRC error does not
generate" an interrupt.
It may also be pointed out that in SDLC/HDLC mode,
receive DMA requests are disabled by a special receive
condition and can only be re-enabled by issuing an Error Reset Command.
Transmit Interrupt
A transmit buffer empty generates a transmit interrupt.
This has been discussed earlier under "Transmit in Interrupt Mode'~ and it would be sufficient to note here
that a transmit buffer empty interrupt is generated only
when the transmit buffer gets empty-assuming it had
a data character loaded into it earlier. This is why on
starting a frame transmission, the first data character is
loaded by the CPU without a transmit empty interrupt
(or DMA request in DMA mode). After this character
is loaded into the serial shift register, the buffer becomes empty, and an interrupt (or DMA request) is
generated. This interrupt is reset by a "Reset Tx Interrupt/DMA Pending" command (WRO: D5 D4 D3 =
101).
External/Status Interrupt
Continuing our discussion on transmit interrupt, if the
transmit buffer is empty and the transmit serial shift
register also becomeS empty (due to the data character
shifted out of the MPSC), a transmit under-run interrupt will be generated. This interrupt may be reset by
"Reset ExternaVStatus Interrupt" command (WRO:
D5 D4 D3 = 101).
The External Status Interrupt can be caused by five
different conditions:
(i) CD Transition
(ii) CTS Transition
(iii) Sync/Hunt Transition
(iv) Tx under-run/EOM condition
(v) Break/Abort Detection.
CD, CTS TRANSITION
Any, transition on these inputs on the serial interface
will generate all External/Status interrupt and set the
corresponding bits in status register RRO. This interrupt will also be generated in DMA as wel~n Wait
Mode. In order to find out the state of the ers or CD
pins before the transition had occurred, RRO must be
read before issuing a Reset ExternaVStatus Command
through WRO. A read of RRO after the Reset ExternaV
Status Command will give the condition of ers or CD
pins after the transition had occurred. Note that bit DS
in RRO gives the complement of the state of CTS pin
while D3 in RRO reflects the actual state of the CD pin.
SYNC HUNT TRANSITION
Any transition ,of the SYNDET input generates an interrupt. However, sync input has different functions in
different modes and we shall discuss them individually.
SDLC Mode
In SDLC mode, the SYNDET pin is an outl'ut. Status
register RRI, D4 contains the state of the SYNDET
pin. The Enter Hunt Mode initially sets this bit in RO.
An opening flag in a received SDLC frame resets this
bit and generates an external status interrupt. Every
time the receiver is enabled or the Enter Hunt Code
Command is issued, an external status interrupt will be
generated on receiving a valid flag followed by a valid
address/data character. This interrupt may be reset by
the "Reset ExternaVStatus Interrupt" command.
External SYNC Mode
The MPSC can be programmed into External Sync
Mode by Setting WR4, D5 D4 = II. The SYNDET
pin is an input in this case and must be held hig~ until
an external character synchronization is established.
However, the External Sync mode is enabled by the
Enter Hunt Mode control bit (WR3: D4). A high at the
SYNDET pin holds the Sync/Hunt bit (RRO,D4) in
the reset state. When external synchronization is established. SYNDET must be, driven low on second rising
2-390
inter
AP-145
edge of RxC after the rising edge of RxC on which the
last bit of sync character was received. This high to low
transition sets the Sync/Hunt bit and generates an external/status interrupt, which must be reset by the Reset External/Status command. If the SYNOET input
goes high again, another External Status Interrupt is
generated, which may be cleared by Reset ExternaV
Status command.
In SOLC Receive Mode, an Abort sequence (seven or
more I's) detection on the receive data line will generate an External/Status interrupt and set RRO,07. A
Reset ExternaVStatus command will clear this interrupt. However, a termination of the Abort sequence
will generate another interrupt and set RRO,07 again.
Once again, it may be cleared by issuing Reset External/Status Command.
Mono-Sync/Bisync Mode
This concludes our discussion on External Status Interrupts.
SYNOET pin acts as an output in this case. The Enter
Hunt Mode sets the Sync/Hunt bit in RO. Sync/Hunt
bit is reset when the MPSC achieves character synchronization. This high to low transition will generate an
external status interrupt. The SYNDET pin goes active
every time a sync pattern is detected in the data stream.
Once again, the external status interrupt may be reset
by the Reset External/Status command.
Interrupt Priority Resolution
The internal interrupt priority between various interrupt sources is resolved by an internal priority logic
circuit, according to the priority set in WR2A. We will
now discuss the interrupt timings during the priority
resolution. Figures 9 and 10 show the timing diagrams
for vectored and non-vectored modes.
Tx UNDER-RUN/END OF MESSAGE (EOM)
The transmitter logic includes a transmit butTer and a
transmit serial shift register. The CPU loads the charaeter into the transmit butTer which is transferred into
the transmit shift register to be shifted out of the
MPSC. If the transmit butTer gets empty, a transmit
butTer empty interrupt is generated (as discussed earlier). However, if the transmit butTer gets empty and the
serial shift register gets empty, a transmit under-run
condition will be created. This generates an External
Status Interrupt and the interrupt can be cleared by the
Reset External Status command. The status register
RRO, 06 bit is set when the transmitter under-runs.
This bit plays an important role in controlling a transmit operation, as will be discussed later in this application note.
BREAK/ABORT DETECTION
In asynchronous mode, bit 07 in RRO is set when a
break condition is detected on the receive data line.
This also generates an ExternaVStatus interrupt which
may be reset by issuing a Reset External/Status Interrupt command to the MPSC. Bit 07 in RRO is reset
when the break condition is terminated on the receive
data line and this causes another Externa1/Status interrupt to ge generated. Again, a Reset ExternaVStatus
Interrupt command will reset this interrupt and will
enable the break detection logic to look for the next
break sequence.
VECTORED MODE
We shall assume that the MPSC accepted an internal
request for an interrupt by activating the internal INT
signal., This leads to generating an external interrupt
signal on the INT pin. The CPU responds with an interrupt acknowledge (INTA) sequence. The leading
edge of the first INTA pulse sets an internal interrupt
acknowledge signal (we will call it Internal INTA). Internal INTA is reset by the high going edge of the third
IN"fA pulse. The MPSC will not accept any internal
requests for an interrupt during the period when Internal INTA is active (high). The MPSC resolves the priority during various existing internal interrupt requests
during the Interrupt Request Priority Resolve Time,
which is defined as the time between the leading edge of
the first INTA and the leading edge of the second
INTA from the CPU. Once the internal priorities have
been resolved, an internal Interrupt-in-service Latch is
set. The external INT is also deactivated when the Interrupt-in-Service Latch is set.
2-391
The lower priority interrupt requests are not accepted
internally until an EOI (WRO: OS D4 03 = III Ch. A
only) command is issued by the CPU. The EOI command enables the lower priority interrupts. However, a
higher priority interrupt request will still be accepted
(except during the period when internal INTA is active) even though the Internal-in-Service Latch is set.
intJ
AP-145
INTERNAL INT
ACCEPTED
U-TERNAL
INT
.... _ _ _ _ _ _---J~
\
\
l ....--------------~\~------------~r------_r
INTA
INTERNAL
INTA
------1.----
I
.~=---------N-O-I-NTE-\....jRN~r.L{INTERRUPTS ACCEPTED
Y
INT-IN.SER~~E
(INTERNAL LATCH)
EOICOMMA.~ND~
___________________________
~
210403-4
Figure 9. 8274 In 8085 Vectored Mode Priority Resolution Time
INTERNAL INT
ACCEPTED
EXTERNAL INT - - - . . . . ,
\
IPI
\
\
POINTER 2
SPECIFIED
~NOINTERNALINTERRUPTS-==\
------~~
I
ACCEPTED
j4-PRIORITY
RESOLVE
TIME
I
....- - - I ~---f:---"t------
J
I
INT.IN.SERVICE_ _ _ _ _ _ _ _ _ _ _ _...J
(INTERNAL LATCH)
EOICOMMAND----------------------~~---J
210403-5
Figure 10. 8274 Non Vectored Mode Priority Resolve Time
2·392
inter
AP-145
This~her priority request will generate another external INT and will have to be handled by the CPU according to how the CPU is set up. If the CPU is set up
to respond to this interrupt, a new INTA cycle will be
repeated as discussed earlier. It may also be noted that
a transmitter buffer empty and receive character available interrupts are cleared by loading a character into
the MPSC and by reading the character received by the
MPSC respectively.
NON·VECTORED MODE
Figure 10 shows the timing of interrupt sequence in
non-vectored mode. The explanation of non-vectored is
similar to the vector mode, except for the following
exceptions.
- No internal priority requests are accepted duri.ng
the time when pointer 2 for Channel B is specified.
- The interrupt request priority resolution time is the
time between the leading edge of pointer 2 and leading edge of RD active. It may be pointed out that in
non-vectored mode, it is assumed that the status
affects vector mode is used to expedite interrupt response.
On getting an interrupt in non-vectored mode, the CPU
must read status register RR2 to find out the cause of
the interrupt. In order to do so, first a pointer to status
register RR2 is specified and then the status read from
RR2. It may be noted here that after specifying the
pointer, the CPU must read status register RR2 otherwise, no new interrupt requests will be accepted internally.
Just like the vectored mode, no lower internal priority
requests are accepted until an EOI command is issued
by the CPU. A higher priority request can still interrupt the CPU (except during the priority request inhibit
time). It is important to note here that if the CPU does
not perform a read operation after specifying the pointer 2 for Channel B, the interrupt request accepted before the pointer 2 was activated will remain valid and
no other request (high or low priority) will be accepted
internally. In order to complete a correct priority resolution, it is advised that a read operation be done after
specifying the pointer 2B.
EOI Command
The EOI command as explained earlier, enables the
lower priority interrupts by resetting the internal InService-Latch, which consequently resets the IPO output to a low state. See Figures 9 and 10 for details. Note
that before issuing any EOI command, the internal interrupting source must be satisfied otherwise, same
source will interrupt again. The Internal Interrupt is
the signal which gets reset when the internal interrupting source is satisfied (see Figure 9).
This concludes our discussion on the MPSC Interrupt
Structure.
MULTI·PROTOCOL SERIAL
CONTROLLER (MPSC) MODES OF
OPERATION
The MPSC provides two fully independent channels
that may be configured in various modes of operations.
Each channel can be configured into full duplex mode
and may operate in a mode or protocol different from
the other channel. This feature will' be very efficient in
an application which requires two data link channels
operating in different protocols and possibly at different
data rates. This section presents a detailed discussion
on all the 8274 modes and shows how to configure it
into these modes.
Interrupt Driven Mode
In the interrupt mode, all the transmitter and receiver
operations are reported to the processor through interrupts. Interrupts are generated by the MPSC whenever
it requires service. In the following discussion, we will
discuss how to transmit and receive in interrupt driven
mode.
TRANSMIT IN INTERRUPT MODE
The MPSC can be configured into interrupt mode by
appropriately setting the bits in WR2 A (Write Register
2, Channel A). Figure 11 shows the modes of operation.
IPI and IPO
So far, we have ignored the IPI and IPO signals shown
in Figures. 9 and 10. We may recall that IPI is the
Interrupt-Priority-Input to the MPSC. In conjunction
with the IPO (Interrupt Priority Output), it is used to
daisy chain multiple MPSCs. MPSC daisy chaining will
be discussed in detail later in this application note.
2-393
WR2A
DC)
D1
0
0
0
1
1
1
Mode
CH A and CH B in Interrupt Mode
CH A in DMA and CH B in Interrupt
Mode
CH A and CH B in DMA Mode
0
1
Illegal
Figure 11. MPSC Mode Selection for
Channel A and Channel B
inter
Ap·146
We will limit our discussion to SOLC transmit and.receive only. However, exceptions for otlier synchronous
protocols wilt be pointed'out. To-initiate a·frame transmission, the first .data character must· be loaded from
the CPU, in all cases. (OMA Mode too, as you will
notiCe later in this application note): Note, that in
SOLC mode, this first, data· cbaracter may be, the address of the station addressed by the MPSC. The transmit buffer consists of a transmit buffer and a serial shift
register.. W,hen the character is transferred from the
buffer into the serial shift regiser, an .interrupt.due to
transmit buffer empty is generated. The CPU has one
byte time to .service this interrupt andJoad,another
character into the transmitter buffer. The MPSC w.ill
generate an interrupt due to transmit buffer underrun
condition if the CPU does not service the Transmit
Buffer Empty Interrupt within one byte time.
This process will continue until the CPU. is out of any
more data characters to be sent. At this point, the CPU
does not respond to the interrupt with a pharacterbut
simply issues a Reset Tx INT/OMA pending c<;>mmand (WRO: 05 04 03 = ~OI). The,MPSC will ultimately underrun, which simply means. that both the
transmit buffer and transmit shift registers are empty.
At this point, flag character (7EH) or CRC.byte is
loaded into the transmit. shift register. This sets the
transmit underrunbit in RRO and generlltes "Transmit
Underrun/EOM" interrupt (RRO: 06 = 1).
You will recall that an SOLC frame has two CRC bytes
after the data field. 8274 generates the CRC on all the
data that is loaded from the CPU. ,Ourilfg initialization,
there is a choice of selecting a CRC-16 or CCITT-CRC
(WR5: 02). In SOLC/HOLC operation, CCITT-CRC
must be selected. We will now see how the CRC gets
inserted at the end of the data field. Here ·we have ·a
choice of having the CRe attached to the data field·or
sending the frame without the· CRO bytes .. Ollring
transmission, a "Reset Tx Underrun/EOM Latch"
command (WRO: 07 06 = 11) will ensure that at the
end of the frame when the transmitter underruns, CRC
bytes will be automatically insetted at the ~d of the
data field. If the "Reset Tx Underrun/EOM Latch"
command was not issued during the transmission of
data charaCters, ho CRC would be inserted and the
MPSC will transmit flags' (7EH) instead.
However, in case of CRC transmission, the CRC transmission sets the Tx Underrun/EOM bit and generates a
Transmittt;f UnderruniEQM Interrupt as discussed
earlier. This will have to be reset in the next frame to
ensure CRC insertion "in the next frame. It is recommended that Tx Underrun/EOM latch be reset very
early in the transmission mode, preferably after loading
the first character. It may be noted here that Tx Underrun EOM latch cannot be reset ifthere is no data in the
transmit buffer. This means that at least one character
has to be loaded into the MPSC before a "Reset Transmit Underrun/EOM Latch" command will be accepted
by the MPSC.
When the transmitter is underrun, an interrupt is generated. This .interrupt is generated at the beginning of
the CRC transmission, thus giving the user enougb
time (minimum 22 transmit clock cycles) to issue an
Abort command (WRO: 05 0403 = 00 1) in case if
the transmitted data had an error. The Abort Commandwill ensure that the MPSC transmits at least
eight l's but less than fourteen. l's before the line reverts to continuous flags. The receiver will scratch this
frame because of bad CRC.
However, assuming the transmission was good (no
Abort Command issued), after the CRC bytes have
been transmitted, closing flag (7EH) is loaded into the
transmit buffer. When the flag (7EH) byte is transferred to the serial shift register, a transmit buffer empty interrupt is generated. If another frame has to be
transmitted, a new data character has to be loaded into
the transmit buffer and the complete transmit sequence
repeated. If no more frames are to bl! transmitted, a
"Reset Transmit INT/OMA Pending" command
(WRO: D5 04 D3 = 101) will reset the transmit buffer
empty interrupt.
For character oriented protocols (Bisync, Monosync),
the same discussion is valid, except that during transmit underrun condition and transmit underrun/EOM
bit in set state, instead of flags, filler sync characters are
transmitted.
CRC Generation
The translllit CRC enable bit (WR5: 00) must be set
before loading any data into the MPSC. The CRC generator must be reset to all 1's at the beginning of each
frame before CRC computation has begun. The CRC
computation starts on the first data character loaded
from the CPU and continues until the last data character. The CRC generated is inverted before it is sent on
the Tx Oata line.
Transmit Termination
A successful transmission can be terminated by issuing
a "Reset Transmit Interrupt/OMA Pending" command, as discussed earlier. However, the transmitter
may be disabled any time during the transmission and
the results will be as shown in Figure 12.
RECEIVE IN INTERRUPT MODE
The receiver has to be initialized into the appropriate
receive mode (see sample program later in this application note). The receiver must be programmed into Hunt
Mode (WR3: D4) before it is enabled (WR3: 00). The
receiver will remain in the Hunt Mode until a flag (or
sync character) is received. While in the SOLC/Bisync/Monosync mode, the receiver does not enter the
Hunt Mode unless the Hunt bit (WR3, 04) is set again
or the receiver is enabled again.
2-$94
inter
AP-145
SOLe Address byte is stored in WR6. A global address
(FFH) has been hardwired on the MPse. In address
search mode (WR3: 02 = 1), any frame with address
matching with the address in WR6 will be received by
the MPSe. Frames with global address (FFH) will also
be received, irrespective of the condition of address
search mode bit (WR3: 02). In general receive mode
(WR3: 02 = 0), all frames will be received.
Transmitter
Result
Disabled during
1. Data Transmission Tx Data will send idle
characters· which will be
zero inserted.
2. CRC Transmission 16 bit transmission,
corresponding to 16 bits of
CRe will be completed.
However, flag bits will be
substituted in the CRC field.
3. Immediately after
issuing ABORT
command.
Abort will still be
transmitted-output will be
in the mark state.
Receive Character Length
Since the MPSe only recognizes single byte address
field, extended address recognition will have to be done
by the CPU on the data passed on by the MPSC. If the
first address byte is checked by the MPSC, and the
CPU determines that the second address byte does not
have the correct address field, it must set the Hunt
Mode (WR3: 02 = 1) and the MPSC will start searching for a new address byte preceded by a flag.
Programmable Interrupts
The receiver may be programmed into anyone of the
four modes. See Figure 13 for details.
1
0
1
0
1
1
Any change in CO input or Abort detection in the received data, will generate an interrupt if External Status
Interrupt was enabled (WRl: DO).
The receiver buffer is quadruply buffered. If the CPU
fails to respond to "receive character" available interrupt within a period of three byte times (received
bytes), the receiver buffer will overflow and generate an
interrupt. Finally, at the end of the received frame, an
interrupt will be generated when a valid ending flag has
been detected.
"NOTE:
Idle characters are defined as a string of 15 or more
contiguous ones.
0
0
External Status Interrupts
Special Receive Conditions
Figure 12. Transmitter Disabled
During Transmission
WR1,CHA
04
03
used to start a OMA transfer or a block transfer sequence using WAIT to synchronize the data transfer to
received or transmitted data.
The receive character length (6, 7 or 8 bits/character)
may ~ changed during reception. However, 'to ensure
that the change is effective on the next received character, this must be done fast enough such that the bits
specified for the next character have not been assembled.
CRC Checking
The opening flag in the frame resets the receive CRC
generator and any field between the opening and closing flag is checked for the CRC. In case of a CRC
error, the CRC/Framing Error bit in status register 1 is
set (RR 1: 06 = 1). Receiver CRC may be disabled/enabled by WR3,03. The CRC bytes on the received
frame are passed on to the CPl,J just like data, and may
be discarded by the CPU.
Receive Terminator
An end of frame is indicated by End of Frame interrupt. The CPU may issue an "Error Reset" command
to reset this interrupt.
Rx Interrupt Mode
Rx INTIDMA disable
Rx INT on first character
DMA (Direct Memory Access) Mode
INT on all Rx characters
(Parity affects vector)
INT on all Rx characters
(Parity does not affect vector)
The 8274 can be interfaced directly to the Intel OMA
Controllers 8237 A, 8257A and Intel I/O Processor
8089. The 8274 can be programmed into OMA mode
by setting appropriate bits in WR2A. See Figure 11 for
details.
Figure 13. Receiver Interrupt Modes
All receiver interrupts can be disabled by WRl: 04 03
= 00. Receiver interrupt on first character is normally
2-395
inter
Ap·145
TRANSMIT IN DMA MODE
After initializing the 8274 into the OMA mode, the
first character must be loaded from the CPU to start
the OMA cycle. When the first data character (may be
the address byte in SOLC) is transferred from the
transmit buffer to the transmit serial shift register, the
transmit buffet gets empty and a transmit OMA request (TxORQ) is generated for the channel. Just like
the interrupt mode, to ensure that the CRC bytes are
included in the frame, the transmit under-runlEOM
latch must be reset. This should preferably be done after loading the first character from the CPU. The
OMA will progress without any CPU intervention.
When the OMA controller reaches the terminal count,
it will not respond to the OMA request, thus letting the
MPSC under-run. This will ensure CRC transmission.
However, the under-run condition will generate an interrupt due to the Tx under-run/EOM bit getting set
(RRO: 06). The CPU should issue a "Reset TxInt/
ORQ pending" command to reset TxORQ and issue a
"Reset External Status" command to reset Tx Underrun/EOM interrupt. Following the CRC transmission,
flag (7EH) will be loaded into the transmit buffer. This
will also generate the TxORQ since the transmit buffer
is empty following the transmission of the C,RC byt~s.
The CPU may issue a "Reset TxINT/ORQ pending"
command to reset the TxORQ. "Reset TxINT/DRQ
pending" command must be issued before setting up
the transmit OMA channel on the OMA Controller,
otherwise the MPSC will start the OMA transfer immediately after the OMA channel is set up.
RECEIVE IN DMA ,MODE
The receiver must be programmed in RxINT on first
receive character mode (WRI: 04 03 = 0 1). Upon
receiving the first character, which may be the address
byte in SOLC, the MPSC generates an interrupt, and
also generates a Rx OMA Request (Rx ORQ) for the
appropriate channel. The CPU has three byte times to
service this interrupt (enable the OMA controller, etc.)
before the receiver buffer will overflow. It is advisable
to initialize the OMA controller before receiving the
first character. In case of high bit rates, the CPU will
have to service the interrupt very fast in order to avoid
receiver over-run.
Once the OMA is enabled, the received data is transferred to the memory' under OMA control. Any re~
ceived error conditions or external status change condition will genetate an interrupt as in the interrupt driven
mode. The End of Frame is indicated by the End of
Frame interrupt which is generated on reception of the
closing flag of the SDLC frame. This End of Frame
condition also disables the Receive OMA request. The
End of Frame interrupt may be reset by issuing an "Error Reset" command to the MPSC. The "Error Reset"
command also re-enables, the Receive OMA request. It
may be, noted that the End of Frame condition sets bit
07 in RRI. This bit gets reset by "Error Reset" command. However, End of Frame bit (RRI: 07) can also
be reset by the flag of the next incoming frame. For
proper operation, Error Reset Command should be issued "after" the End of Frame Bit (RR I: 07) is set. In
a more general case, "Error Reset" command should be
issued after End of Frame, Receive over-run or Receive
parity bit are set in RR 1.
Wait Mode
The wait mode is normally used for block transfer by
synchronizing the data transfer through the Ready output from the MPSC, which may be connected to the
Ready input of the CPU. The mode can be programmed by WR I, 07 05 and may be programmed
separately and independently on CH A and CH B. The
Wait Mode will be operative if the following conditions
are satisfied.
(i) Interrupts are enabled.
(ii) Wait Mode is enabled (WRI: 07)
(iii) CS
= 0, Al = 0
The ROY output becomes active when the transmitter
buffer is full or receiver buffer is empty. This way the
ROY output from the MPSC can be used to extend the
CPU read and write cycle by inserting WAIT, states.
ROY A or ROYB are in high impedance state when the
corresponding channel is not selected. This makes it
possible to connect ROY A and ROYB outputs in wired
OR configuration. Caution must be exercised here in
using the ROY outputs of the MPSC or else the CPU
may hang up for indefinite period. For example, let us
assume that transmitter buffer is full and R02::AJs active, forcing the CPU into a wait state. If the CTS goes
inactive during this period, the ROYA will remain active for indefinite period and CPU will continue to insert wait states.
Vectored/Non,:,Veqtored Mode
The MPSC is capable of providing an interrupt vector
in response to the interrupt acknowledge sequence from
the CPU. WR2, CH B contains this vector and the
vector can be read in status register RR2.WR2, CH A
(bit 05) can program the MPSC in vectored or nonvectored mode. See Figure 14 for details.
2-396
inter
AP-145
In both cases, WR2 may still have the vector stored in
it. However, in vectored mode, the MPSC will put the
vector on the data bus in response to the INTA (Interrupt Acknowledge) sequence as shown in Figure 15. In
non-vectored mode, the MPSC will not respond to the
INTA sequence. However, the CPU can read the vector by polling Status Register RR2. WR2A, 04 and 03
can be programmed to respond to 8085 or 8086 INTA
sequence. It may be noted here that IPI (Interrupt Priority In) pin on the MPSC must be active for the vector
to appear on the data bus.
WR2A,05
0
1
STATUS AFFECT VECTOR
The Vector stored in WR2B can be modified by the
source of the interrupt. This can be done by setting the
Status Affect Vector bit (WRI: 02). This powerful feature of the MPSC provides fast interrupt response time,
by eliminating the need of writing a routine to read the
status of the MPSC. Three bits of the vector are modified in eight different ways as shown on Figure 16. Bits
V4, V3, V2 are modified in 8085 based system and bits
V2, VI, VO are modified in 8086/88 based system.
In non-vectored mode, the status affect vector mode
can still be used and the vector read by the CPU. Status
register RR2B (Read Register 2 in Channel B) will contain this modified vector.
Interrupt Mode
Non-vectored Interrupt
Vectored Interrupt
Figure 14. Vectored Interrupt
05
WR2A
04
03
0
1
1
1
1
1
1
X
0
0
0
0
1
1
X
0
0
1
1
0
0
IPI
Mode
1st INTA
2ndiNTA
3rd INTA
X
0
1
0
1
0
1
Non-Vectored
8085-1
8085-1
8085-2
8085-2
8086
8086
HI-Z
11001101
11001101
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
V7 V6 V5 V4 V3 V2V1 VO
HI-Z
V7V6V5V4V3V2V1 VO
HI-Z
V7V6V5V4V3V2V1 VO
HI-Z
HI-Z
00000000
HI-Z
00000000
HI-Z
-
Figure 15. MPSC Vectored Interrupts
(8085
(8086)
V4
V2
V3
V1
V2
VO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Channel
B
A
Interrupt Source
Tx Buffer Empty
EXT 1STAT Change
RX CHAR Available
Special Rx Condition
Tx Buffer Empty
EXT I STAT Change
RX CHAR Available
. Special Rx Condition
Rx Special Condition: Parity Error, Framing Error, Rx Over-run Error, EOF (SDLC).
EXT/STAT Change: Change in Modem Control Pin Status: CTS. DCD. SYNC. EOM. Break/Abort Detection.
Figure 16. Status Affect Vector Mode
2-397
inter
AP.-145
DUAL PORT ACCESS
CONTROL
8273,8274
SERIAL
I/O
8255A
PARALLEL
I/O
LED'S
8254·2
PIT
COUNTERS
8259A
INTERRUPT
CONTROL
MULTiBUS
ADDRESS BITS
ADR141-17/
CHANNEL C
210403-6
Figure 17. Functional Block Diagram-iSBC® 88/45
APPLICATION EXAMPLE
This section describes the hardware and software of an
8274/8088 system. The hardware vehicle used is the
INTEL Single Board Computer iSBC 88/45-Advanced Communication Controller. The software
which exercises the 8274 is written in PLM 86. This
example will demonstrate how 8274 can be configured
into the SDLC mode and transfer data through DMA
control. The hardware example will help the reader
configure his hardware and the software examples will
help in developing an application software. Most software examples closely approximate real data link controller software in the SDLC communication and may
be used with very little modification.
board and the schematics, refer to Hardware Manual
for the iSBC 88/45, Advanced Communication Controller. iSBC 88/45 is an intelligent slave/multimaster
communication board based on the 8088 processor, the
8274 and the 8273 SDLC/HDLC controller. Figure 17
shows the functional block diagram of the board. The
iSBC 88/45 has the following features.
iSBC® 88/45
A brief description of the iSBC 88/45 board will be
presented here. For more detailed information on the
2-398
•
•
•
•
•
•
•
•
•
•
8 MHz processor
16K bytes of static RAM (12K dual port)
Multimaster/Intelligent Slave Multibus Interface
Nine Interrupt Levels 8259A
Two serial channels through 8274
One Serial channel through 8273
S/W programmable baud rate generator
Interfaces: RS232, RS422/449, CCITT V.24
8237A DMA controller
Baud Rate to 800K Baud
inter
AP-145
INITIALIZE_B~74.PROCEDURE
PUBLIC.
1*********************************************.*.***********************.1
1*
*1
1*
INITIALIZE THE 8274 FOR SDLC MODE
*1
1*
*1
I RESET CHANNEL
1*
*1
2. EXTERNAL INTERRUPTS ENABLED
1*
*1
1*
3 NO WAIT
*1
4 PIN 10 - RTS
1*
*1
5 NON-VECTORED INTERRUPT-BOBb MODE
*1
1*
CHANNEL A DMA. CH B INT
1*
*'
10
7. TX AND RX • 8 BITS/CHAR
ADDRESS SEARCH MODE
9
1*
10 CD AND CTS AUTO ENABLE
1*
II XI CLOCK
*1
1*
12. NO PARITY
1*
*1
13 SDLC/HDLC MODE
1*
*1
10
14. RTS AND DTR
*1
I.
15. CCITT - CRC
*1
I.
16 TRANSM ITTER AND RECEIVER ENABLED
*1
I.
17 7EH == FL.AG
*1
I.
*1
"
*'*'
*'
1******************************************************************.*****1
DECLARE C BYTE.
I. TABLE TO INITIALIZE THE 8274 CHANNEL A AND
10 FORMAT IS· WRITE REGISTER. REGISTER DATA
1* INITIALIZE CHANNEL A ONLY
*1
*1
*1
DECLARE TABLEJ4_A<*) BYTE DATA
<00H,18H.
1* CHANNEL RESET *1
00H.80H,
1* RESET TX CRC *1
02H. IIH.
1* PIN IO-RTSB, A DMA, B INT *1
04H.20H.
1* SDLC/HDLC MODE, NO PARITY *1
07H.07EH,
1* SDLC FLAG *1
OIH.OBH.
1* RX DMA ENABLE *1
1* DTR, RTS, B TX BITS, TX ENABLE,*I
OSH,OEBH.
1* SDLC CRC, TX CRC ENABLE *1
06H,55H,
10 DEFAULT ADDRESS *1
03H,OD'1H,
1* B RX BITS, AUTO ENABLES, HUNT MODE, *1
1* RX CRC ENABLE 01
OFFH).
1* END OF INITIALIZATION TABLE *1
DECLARE TABLE_74_B <*) BYTE DATA
<02H,OOH,
1* INTERRUPT VECTOR *1
I. STATUS AFFECTS VECTOR *1
0IH.1CH.
I. END *1
OFFH).
I. INITIALIZE THE 8274 *1
C=O.
DO ~~HILE TABLEJ4_B OFFH,
OUTPUT OFFH.
OUTPUT(COMMAND_A_74)
TABLE_74_A(C),
C=C+I.
OUTPUT= 010*1
IGNORE_INT,
CALL.
1* V2VIVO ,. 011*1
IQNORE_INT.
CALL.
1* V2VIVO - 100*1
CALL
CHA_EXTERNAL.3HANGE'
1* VOlVIVO • 10101
CALL.
CHA_RX_CHARI
1* V2VIVO - liD*,
CALL.
CHA_RX_SPEC IALI
1* V2V1\10 - 111*1
END.
OUTPUTCCOMMAND_AJ4) -38H.
1* END OF INTERRUPT FOR 8274 *1
RETURN;
END INTERRUPT_8274;
210403-9
Figure 20. Typical Main Interrupt Routine
1********************************.*********************1
1* CHANNEL. A EXTERNAL./STATUS CHANGE INTERRUPT HANDL.ER *1
1******************************************************1
CHA_EXTERNAL._CHANQE'
PROCEDURE,
TEMP· INPUT(STATUS_AJ4).
1* STATUS REG 1*1
IF (TEMP AND END_OF_TX_MESSAGE) • END_OF_TX_MESSAGE THEN
TXOONE_S-OONE;
EL.SE DO.
TXDONE_S-OONE;
RESUL. TS_S-FAILI
END.
OUTPUT(COMMAND A 74) • IOH,
1* RESET EXT/STATUS INTERRUPTS *1
RETURN.
- END CHA_EXTERNAL_CHANGE;
1**********************************************************1
1* CHANNEL A SPECIAL. RECEIVE CONDITIONS INTERRUPT HANDL.ER *1
1**********************************************************1
CHA_RX_SPEC IAL.:
PROCEDURE;
OUTPUT (COMMAND_A_74) - I,
TEMP = INPUTCSTATUS_A_74),
IF OFFH,
OUTPUT (COMMAND_B_74) • T'IBLE]4.J3(C)'
C-C+l.
OUTPUT(COMMANO_B_74)
C=-C+li
3
31
3
32
3
as
TABLE_74_B(C),
END,
210403-17
2-408
inter
33
34
35
36
37
38
39
40
41
42
43
AP-145
2
c-o.
2
DO WHILE TABLEJ4_A(C'
3
3
3
3
3
C-C+1.
OUTPUT (CoMMAND_A_74 •
C=C+11
OFFH.
= TABLE _74_A(C),
= TABLE_74_A(C'.
END.
2
2
:/
<>
OUTPUT (COMMAND_A_74)
CALL
DELAY_S.
RETURN.
END INIT _8274_SDLC_S.
END INIT _8274_9.
PL/M-86 COMP ILER
lSBe 8B/4!o B274 CHANNEL A SOLe TEST
MOOULE INFORMAT ION
CODE AREA SIZE
=
CONSTANT AREA SIZE VARIABLE AREA SIZE·
MAXIMUM STACK SIZE·
213 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS
00A8H
OOOOH
0003H
0006H
1680
OD
3D
60
END OF PL/M-86 COMP ILATION
PLlM-86 COMPILER
1SBe 88/45 B274 CHANNEL A SDI..C TEST
SERIES-III PL/M-B6 VIZ 0 COMPILATION OF MODULE INIT_B237_CHA
OB.!ECT MODULE PLACED IN . FI SINI37 DB.!
COMPILER INVOKED BY.
PLM86.86. FI SINI37 PLM TITLE( ISDC 88/45 8274 CHANNEL A 90LC
TEST> COMPACT NOINTVECTOR ROM
1*****····***····**·.·******.· •• ** ••• ******.**.** ••••• ****************.**1
1*
1*
1*
*1
8237
INITIALIZATION ROUTINE
FOR DMA TRANSFER
*1
*1
/ ************.****************************.*** ••••••••• ****************** I
INIT _8237 _CHA.
00,
.NOLIST
INIT _8237 _9
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PROCEDURE PUBLIC.
OUTPUT (MASTER_CLEAR_37) -0.
OUTPUT(COMMAND_37) ;10 20H.
1* EXTENDED WRITE
OUTPUT(ALL_HASK_37) .. OFH;
/* MASK ALL REOUESTS *1
OUTPUT • (SINGLE_MODE OR WRITE_XFER OR CHO_SEL>.
OUTPUT.
OUTPUT(CLR_BVTE_PTR_37) - 0.
OUTPUT(CHO_ADDR) = OQ.
RECEIVE BUFF AT 900H *1
OUTPUT< CHO_ADDR)
09H.
OUTPUT(CHO_CoUNT> - OHi
OUTPUT (CHO_COUNT) = 01.
OUTPUT (CH1_ADDR) .. OQ,
1* TRANSMIT BUFF AT BOOH *1
OUTPUT(CHl_ADDR) • OSHI
OUTPUT - OIOH.
OUTPUT
OOH.
*'
=
'*
=
210403-18
2-409
intJ
AP-145
27
i!B
i!
2
2'1
2
1* ENABLE TRANSFER *1
OUTPUTCSINQLE_MASK) • CHI_SEL.
RETURNJ
1 * ENABLE TX DMA *1
1* TURN OFF THE 8237 CHANNELS 0 AND I *1
30
31
32
33
I
2
2
2
34
2
3'
BToP_B237_S' PROCEDURE PUBLIC.
oUTPUTCSINQLE_MASIO • CHI_BEL DR SET.-MASK;
oUTPUTCSINGLE_MASK) - CHO_SEL OR SET.-MASK.
RETURNI
END STOP _B237 _BI
END INIT _8:237 _CHAi
MODULE INFORMATION:
CODE AREA 81 ZE
004CH
7bD
CONSTANT AREA SIZE. OOOOH
VARIABLE AREA SIZE = OOOOH
00
00
PL.lM-S6 COMP 1 LER
•
i SBe 8S/45 8274 CHANNEL. A SDL.e TEST
MAX IHUM STACIo!. SIZE -
0002H
20
163 LINES READ
PROGRAM WARNINGS
PROGRAM ERR ORB
o
o
END OF PL/M-B6 COMPILATION
Pl,rl
Sr~
COt1PILER
1
':mc
88/45 82"14 CHANNEL A SOLe. TEST
8I;fi1E::-·111 PL/M-86 V2 0 COMPILATION OF MODULE INTR __8274._S
OHJEC f rmOULE PLACED 1111 Fl SINTR (JLhJ
COf1PILEH INVOKED DY
PLM86 A6
Fl SINTR Pl.M TIlLE
COMPACT NOINTVECTOR ROM
1***·*****************************····*·**************.*.***********.*
•• *1
*1
1*
1*
1*
.SBC '4' PORT A (B274) SOLC TEST
*1
*1
,*******•••• *******************••• *.*****************.***··** •• • •• **** ••*1
STEST
2
I
3
:1
I
:1
DOl
DELAY _S PROCEDURE EXTERNAL.
END DELAY _5.
ENABLE_INTERRUPTS_S PROCEDURE EXTERNAL.
END ENABLE_INTERRUPTS_S.
b
I
7
2
DISADLE_INTERRUPTS_S PROCEDURE EXTERNAL,
END DISABLE_INTERRUPTS_S.
B
9
I
2
INIT _8274_SDLC_5 PROCEDURE EXTERNAL.
END INIT _B274_SDLC_S,
10
II
I
2
INIT _B237 _5' PROCEDURE EXTERNAL,
END INIT _8237 _So
12
13
I
2
STOP _8237 _5. PROCEDURE EXTERNAL,
END STOP _8237 _s.
14
I
I'
2
VERIFY _TRANSFER_S PROCEDURE EXTERNALJ
END VERIFY_TRANSFER_S.
Ib
I
17
2
INT _8274_5 PROCEDURE INTERRUPT 3:5 EXTERNAL,
END INT_8274_S,
.NDLIST
.E.!ECT
PL/M-8b COMPILER
28
29
lSSC
9a/-4~
8274'CHANNEL A SDLC TEST
OECLARE (RESULTS_S. TXDONE_S, RXDONE_S) BYTE PUBLIC.
DECLARE DONE
LIT
'OFFH'.
NOT _DONE
LIT
'OOH'.
PASS
LIT
·OFFH·.
FAIL
LIT
·OOW,
210403-22
2-413
inter
Ap-145
.E.JEeT
PL/I'I-86 COI'IPILER
30
ISIC SS/45 S274 CH_L A SDLC TEST
CHA_BDLC_TEST:
PROCEDURE BYTE PUBLIC,
31
32
33
34
35
36
37
2
2
2
CALL
ENABLE_INTERRUPTS_S,
CALL
INIT_S274_SDLC_S'
ENABLE,
OUTPUT CCOI'II'IAND_A_74) • 2SH,
1* REBET TX INT/DI'IA
*1
OUTPUTCCO",,",ANDJI]4) • 28H,
1* BEFORE INITIALIZINO S237*1
CALL
INIT _S237 _S,
DUTPUTCDATA_A_74) • SSH, . 1* LOAO FIRST CHARACTER FROI'I CPU*I
38
39
40
2
2
2
1* TO ENSURE CRC TRANSMISSION RESET TX UNDERRUN LATCH*I
OUTPUT (COMMAND-"_74) • OCOH,
RXDONE_S. TXDONE_S-NOT _DONE,
CLEAR ALL FLAilS
RESULTS_S-PASS,
1* FL.AII SET FOR MONITOR*I
41
42
2
3
DO WHIL.E TXDONE_S-NOT ..DONE,
43
:I
44
45
46
3
2
3
DO WHIL.ECiNPUTCSTATUB_A_74) AND 04H) <> 04H,
1* WAIT FOR CRC TO gET TRANSMITTED *1
1* TEST FOil TX BUFFFER EMPTY TO VERIFY THIS*I.
END,
DO WHIL.E RXDONE_S-NOT _DONE,
1* DO UNTIL. TERMINAL' COUNT*I
END,
47
2
CAL.L
STOP _8237 _S,
48
2
CALL
DISABL.E_INTERRUPTS_S,
49
2
CAL.L
VERIFY_TRANBFER_S'
50
2
RETURN RESUL. TS_S,
51
52
2
1
2
2
2
II
END,
'*
'* DO
*'
UNTIL. TERMINAL. COUNhl
END CHA_SDL.C_TEST,
END STEST,
'MODUL.E INFORI'IATION:
CODE AREA SIZE
•
CONSTANT AREA SIZE·
VARIABL.E AREA SIZE MAX IMUM STACK SI ZE 198 L.INES READ
o PROgRAM WARNINgS
o PROgRAI'I ERRORS
0063H
99D
OOOOH
OD
0003H
3D
0004H4D
END OF PL.IM-S6 COMPILATION
PL/I'I-S6 COI'IPIL.ER
ISBC SS/45 S274 CHANNEL. A SDL.C TEST
SERIES-II I PL./I'I-S6 V2.0 CDI'IPIL.ATION OF MODUL.E VECTORJ1QDE
OB.JECT I'IODUL.E PL.ACED IN : Fl. VECTOR DB.J
CDI'IPIL.ER INVOKED BY:
PL.MSII. S6 Fl: VECTOR. PLM T1TL.EClSBC S8/45 S214 CHANNEL. II SDL.C TEST)
1*******.*****************•• *************.***********.**************1
1*
1*
I.
I.
1*
8274 INTERRUPT HANDL.INg ROUTINE FOR
8274 VECTOR 1'100£
STATUS AFFECTS VECTOR
*1
*1
*1
.,*'
1****************.***********************************.*********.****1
210403-23
AP-145
1*
1*
1*
1*
1*
1*
THIS IS ...N EX"'I'IPI.E OF HOW 11274 CAN BE USED IN VECTORED 1'!0DE.
THE ISBCBB/4e BO...RD W... S REWIRED TO DIS...BI.E THE PIT BOIe9A "'ND
EN...BI.E THE 80174 TO PI. ...CE ITS VECTOR ON THE DIIT...BUS IN RESPONSE
TO THE INT... SEClUENCE FRol'! THE BOBS OTHER 1'!0DIFIC"'TloNS INCI.UDED
CH...NIIES TO 80174 INITI ...I.IZ"'TION PROIIR",I'! (BINI74) TO PRoOR ...M B0I74
INTO VECTDIIED I'IODE (WRITE REOISTEII 2'" De-I)
VECToIIJ1oDE
.NDl.IST
101
13
14
*I
*1
*I
*1
*1
*I
DOl
DECI."'RE TEMP 8YTEI
DECI.ME (RESUI.TS_S. TXOONE. RXDONE) BYTE EXTERNAI.I
DECI."'RE DONE I.ITER"'I.I.Y ·OFFH'.
NOT JlONE I.ITER""-1. Y • ODH ••
P...SS
I.ITER ...I.I.Y ·OFFH·.
F"'II.
I.ITER"'I.I.Y 'OOH'I
, ••• *****.*******************.********* •• ******** •• *** ···********.******1
1*
1*
TR ...NSMIT INTERRUPT CH"'NNEI. '" INTERRUPT WII.I. NOT BE SEEN IN THE *1
DI'I'" oPER ... TlON
*1
1******••• ** ••••••• ****.***** ••••••• ** ••••• * •••• **.*** ••• ************.*.1
Ie
I/>
17
Ie
I
01
TX_INTERRUPT _CH... PROCEDURE INTERRUPT B41
oUTPUT(CoMI'!...ND_... _74J - 001010008.
oUTPUTlCDI'I"",ND_..._74J - 0011100081
END TX_INTERRUPT _CH"'I
2
2
I*RESET TXINT PENDINO*I
I*EoI*1
,****•••EXTERNAI./ST
***** •• **************.****
•• *.************.**-·*·**·************1
...TUS INTERRUPT PROCEDURE: CHECKS FOR END OF MESS...OE *1
1*
1*
1*
1*
1*
ONLY.
IF THIS IS NOT TRUE THEN THE FAIL FLAG IS SET
HOWEYER,
... USER PRoOR ...M SHOUI.D CHECK FDR OTHER EXT/ST ...TUS CONDITIONS
...I.SO IN RRI AND THEN T...KE ...PPROPRI ...TE ACTION B...SED ON THE
... PPI. I c...T1 ON
*1
*1
*1
*1
1********.************.************.**.***************************'•• ****1
19
010
011
0101
013
014
I
01
2
01
2
3
EXT _ST...T _CH"'NIIE_CH... · PROCEDURE INTERRUPT BlIl
TEI'IP - INPUTlST...TUS-",,_74J.
IF (TEMP AND END_OF _TX_I'!ESSIIOEJ • END_DF _TX_MESS"'OE THEN
TXDoNE • DONE.
EI.SE 001
TXDoNE • DONE.
PI./I'!-8. COI'!P II.ER
Ole
3
2.
3
017
OIB
019
30
01
01
2
01
IS8C 8B/4l1 B274 CH...NNEI. ... SDI.C TEST
RESULTS_S • FAIL.I
END.
oUTPUTlCoI'II'IAND_... _74) • 0001000081
oUTPUTlCoMM...ND-",,-,4J • 001110008.
RETURN.
END EXT _ST ... T _CH...NGE_CH....
,.RESET EXT STAT INT_'
I*EOI*I
1****************************************.**.*********.*.***
•••****.****1
1*
RECEII/ER CH"'RACTER ...VAII. .... I.E INTERRUPT WII.I. ",PPEAR oNI.Y ON FIRSHI
1*
1*
RECEIVE CH...R... CTER. SINCE DM ... CoNTRol.l.ER H...S BEEN ENA81.ED BEFORE *1
THE FIRST CH ...R...CTER IS RECEIVED. THE RECEIVER REClUEST IS
*1
I.
SERVICED BY THE DMA CONTROLLER
*1
1•••• * ••••• **** ••••• * •••••• *** ••••• *.**.*** •••• * •• *****.** •• ************1
31
32
33
34
I
01
2
2
RX_CH...R-"'VAII....8I.E_CH... PROCEDURE INTERRUPT S••
oUTPUT(Col'II'I...ND-",-,4) • 00111000..
I*EoI*1
RETURN.
END RX_CH...R-""V... II....8I.E_CH....
• EJECT
210403-24
2-415
inter
.". ',.
AP-145
PL/I"I-86 COMP ILER
~.
• SBC 8S/45 6274 CHANNEL A SDLC TESr
I******.*.***
.• **.*.*.~**.******.****,:* •••** ••**.*******.* •••~••**.* •••••.*I
1*
SPECIAL RECEIVE CONDITION INTERRUPT SERVICE,ROUTINE CHECKS FOR *1
1*
1*
END OF F"RAME BIT ONLY SEE SPECIAL SERVICE ROUTINE FOR NONVECTORED MODE FOR CRC CHECK AND OVERRUN ERROR CHECK
*'
*'
1*******.* ••**-********.*.*** •• ********.*.*.**.******* ••••• ** •• * ••••• ***1
35
36
37
3B
39
40
41
42
43
44
45
46
47
2
2
4B
49
50
51
52
53
54
55
I
2
56
OUTPUT(COMMANO-,,_74) •
2
2
3
3
3
2
2
2
2
2
2
;2
2
2
2
1.
I*POINTER 1*,
TEMP· INPUT 0
then output(ch_a_command) • reg_no and Of hi
return input(ch_a_command);
end rra,
rrb: procedure (reg_no) bvtel
declare reD_no bvtel
if (reg_no and Of h) <> 0
then output (ch_b_command) • reg_no and Of hi
return input(ch_b_command)1
end rrb;
1*
write .elected .ec register
*1
wra: procedure (reg_no. value)i
declare reg_no bvtel
declare value bvtel
1f (reg_no and Of h) <> 0
then output (ch_a_command) • reg_no end Ofh;
output (ch_a_command) • value,
end wra;
wrb: procedure (reD_no. value);
declare reD_no bVte,
declare value bvte,
if (reg_no and Of h) <> 0
then output (ch_b_command).- reg_no and Ofh;
output (ch_b_command) • value;
end wrb,
1*----------------------------------------------------~---------------------*I
231262-2
Figure 2. Accessing the see Registers
2·423
intJ
AP-222
3. Initialization for ASYNC Operation
In the following example, channel B of the SCC is used
to perform ASYNC communication. Figure 3 shows
how the channel B is initialized and configured for
ASYNC operation. This is done by writing the various
channel B registers with the proper parameters as
shown. The comments in the program show what is
achieved by each statement. After a software reset of
the channel, register #4 should be written before writing to the other registers. The on-chip Baud Rate Generator is used to generate a 1200 bits/sec clock for both
the transmitter and the receiver. The interrupts for
transmitter and/or receiver are enabled only for the
interrupt mode of operation; for polling, interrupts
must be kept disabled.
4. ASYNC Communication in Polling
Mode
Figure 4 ~hows the procedures for re~ding in a received
character from the 82530 (scc_in) and for writing out
a character to the 82530 (scc_out) in the polling mode.
The scc_in procedure returns a byte value which is the
character read in. The'receiver is polled to find if a
character has been received by the SCC. Only when a
character has -been received, the character is read infrom the data port of the SCC channel B.
The scc_out procedure requires a byte parameter
which is the character being written out. The transmit-
/ *---.----------.. - -.- -.---.-------- -- ------------------------------ -------.-----------* I
1*
*1
1* channel B reset *1
1* 2 stop. no paritll'
1* vector = 20h *1
1* rx 8 bits/char, no
sec ch B registllr initialization 'or ASYNC mode
call
call
call
call
call
call
call
Col 11
call
call
call
call
call
tall
wrb(09,
wrb(04,
wrb(02,
wrb(O:),
wrb(05,
wrb(06,
wrb(07.
WT-b i 09,
wrb(10.
wrbOl.
wrb(l2.
wrb(13.
wrb(14.
wrb(15.
/* IInables
brf' '" -b4x
auto-llnabill
/* tx 8 bits/char .1
1*
*1
*1
*1
= BRG
vllctor includes status
1* rxc .. txc = BRG , trxc
out *1
to gllnllratll 1200 baud. x64 @ 4 mhz *1
1*
1* BRG source = SYS eLK. enable BRG *1
1* all ext status interrupts
*1
0"
*1
call wrb (0:3.
call wrb (OS,
I~
OlOOOOOOb);
11001110b);
00100000b);
11000000b);
01100000b);
OOOOOOOOb);
OOOOOOOOb);
00000001 b);
OOOOOOOOb)1
OlOlOll0b);
0001l000b);
OOOOOOOOb);
00000011b);
OOOOOOOOb);
1100000ib);
11101010b);
enab]. interrupts -
o~lV
call wrb(09, 00001001b)i
call wrb (01, 00010011b)i
/* scc-b receive enable
*1
1* scc-b transmit IInablll,
'01'
dtr on, rts on */
interrupt driven ASYNC I/O */
1* mastllr IE. vllctor includes status *1
tx .rx. IIXt intllrrupts IInablll *1
1*
1*-----------------------_·_---------------------------------------------------*1
231262-3
Figure 3. Initialization for ASYNC Communication
2-424
inter
AP·222
1*--------------------------------·--------------------------------------~---*I
I~
sec data
scc_in:
cha~acte~
p~ocedu~e
input
'~om
channel B
*1
bllte;
declare char bute;
do while (input(ch_b_command) and lh) • 0; endl
cha~ • input(ch_b_data)j
i' rx data cha~acte~ il available
retu~n cha~;
then input it to bu"e~
1*
1*
1*
sec data
cha~acte~
scc_out: procedure
*1
output to channel B
*1
*1
(cha~).
do while (input(ch_b_commandl and 4h) • O. end;
output(ch_b_data) = cha~;
i' tx bu'f emptll then t~an,'e~ the
1* data cha~acte~ to tx bu" *1
1*
*1
1*------------------------------------------------------·-----·---------------*1
231262-4
Figure 4. ASVNC Communication In Polling Mode
ter is polled for being ready to transmit the next character before writing the character out to the data port of
see channel B.
Includes Status' (VIS) mode is set - WR9 =
XXXOXXOl. Vectors and the associated events are:
Vector Procedure
Typical calls to these procedures are:
abc_variable = scc.-i,n;
call scc_out (xyz-variable);
Event Causing Interrupt
20h
txintrj
22h
esLb
chj - extemal/status change
24h
rxiotrj
.ch...,.b - receive character available
chj - transmit buffer empty
26h
src b
chj - special receive condition
5. ASYNC Communication in Interrupt
Mode
28h
txlntr-B
ch-B - transmit buffer empty
2ah
esLs
ch-B - external/status change
In contrast to polling for the receiver and/or the transmitter to be ready with/for the next character, the
82530 can be made to interrupt when it is ready to do
receive or transmit.
2ch
rxintr-B
ch-B - receive character available
2eh
src a
ch-B - special receive condition
The on-chip interrupt controller of the see can be
made to operate in the vectored mode. In this mode, it .
generates interrupt vectors that are characteristic of the
event causing the interrupt. For the example here, the
vector base is programmed at 20h and 'Vector
NOTE:
Odd vector numbers do not exist.
Figure 5 shows the interrupt procedures for the chsnnel
B operating in ASYNe mode. The transmitter butTer
empty interrupt occurs when the transmitter can accept
one more character to output. In the interrupt procedure for transmit, the byte char_out_530 is output.
Following this, is an epUoge that is common to all the
2-425
AP;;222
I
-
,
~
..
interrupt procedures; the first statement is an end of
interrupt conu;nand to the 8253Q - not, that it is issued
to channel A - and the second is an End of Interrupt
(EOI) command to the 80186 interrupt controller
)vhich is, in fact, receiving the interrupt from the 82530.
The receive buffer full interrupt occurs when the receiver has at least one character in its buffer, waiting to be
read in by the CPU.
The esLb is not enabled to occur and src_b cannot
occur in the ASYNC mode unless the receiver is overrun or a parity error occ,W:S'
I*--------~~---~~------~~--~--------~-------~--------- ----------------------*/
1* channel B interrupt procedure. *1
procedu"e
call w"a(OO,3Bhl.
output (eoir_1Bbl
"etu"nl
end txint"_bl
p"ocedu"e
inh""uP~ 2~hl
.8000h.
ilitnrupt 22h.
call w"b(OO. 10hli
call w"a(00,38hll
output (eoi,,_186l
"etu"nl
end eli_bl
1* "eset highest IUS *1
1* non specific EOI *1
.8000hl
1* "eset E,SI *1
1* "eset highest rus *1
1* non specific EOI *1
inte""upt 24hl
',',
call w"a(OO,aah).
output (eoi,,_186)
"eturnl
.
end "xint"_bl
• 8000h;-,
.1* "eset highest IUS *1
1* non speCific Ear .*1
int.e""upt 26h.
call
w,,~.(OO.30h)1
call w"a,(OO. 3Bh) 1
output (eoir_186)
"e'urn.
.,
end S"C_bl , .
8000h.
1* error "eset *1
1* "eset highest IUS *1
1*' non specific Ear *1
,I
1*--------------_·_----------------------------------------------------------*1
2~1262-5
Figure 5. ASYNC Communlcatlcm In Interrupt Mod.
2·426
intJ
AP·222
ed on the RxOA pin, it goes from the Hunt to the Sync
mode. It receives the frame and the end of frame interrupt (src_b, vector = 2eh) occurs.
6. Initialization for SOLC
Communication
Channel A of the SCC is programmed for being used
for SOLC operation. It uses the OMA channels on the
80186. Figure 6 shows the initialization procedure for
channel A. The comments in the software show the
effect of each statement. The on-chip Baud Rate Generator is used to generate a clock of 125 kHz both for
reception and transmission. This procedure is just to
prepare the channel A for SOLC operation. The actual
transmission and reception of frames is done using the
procedures described further.
7. SOLC Frame Reception
Figure 7 shows the entire set-up necessary to receive a
SOLC frame. First the OMA controller is programmed
with the receive buffer address (@rx_butl), byte count,
mode etc and is also enabled. Then a flag indicating
reception of the frame is reset. An Error Reset command is issued to clear up any pending error conditions. The receive interrupt is enabled to occur at the
end of frame reception (Special Receive Condition);
lastly, the receiver is enabled and put in the Hunt mode
(to detect the SOLC flag). When the first flag is detect-
8. SOLC Frame Transmission
Figure 8 shows the procedure for transmitting a SOLC
frame once channel A is initialized. The OMA controller is initialized with the transmit buffer address
(@t~buff (1» - note, it is the second byte ofthe transmit buffer - and the byte count - again one less than the
total buffer length. This is done because the first byte in
the buffer is output directly using an I/O instruction
and not by OMA. Then the flag indicating frame transmitted is reset. The events following are very critical in
sequence:
a. Reset external status interrupts
b. Enable the transmitter
c. Reset transmit CRC
d. Enable transmitter underrun interrupt
e. Enable the DMA controller
f. Output first byte of the transmit block to data port
g. Reset Transmit Underrun Latch
1*---------------------------------------------------·-----------------------*1
scc_init_a:
1*
procedurel
ICC ch A register initialization for SOLe mode
call
call
call
call
call
call
call
call
call
call
call
call
call
1*
wra(09.
wra(04.
wra(Ol.
wra (03.
wra (05.
wra(06.
wralO7.
wral10.
wra( 11.
wra (12.
wra (13.
wra (14.
wra (15.
10000000b ) ;
00100000b) ;
o1100000b );
11000000b) I
011 OOOOOb ) ;
01010101b) ;
01111110b ) ;
10000000b ) I
01010110b) i
00001110b) I
OOOOOOOOb ) i
00000110b) ;
OOOOOOOOb ) I
*1
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
channel A-reset *1
SOLe mode *1
OMA for Rx *1
8 bit Rx char. Rx disable *1
8 bit Tx char. Tx disable *1
node address *1
SOLe flag *1
prelet eRe. NRZ. encoding. *1
trxc .. DRG aut *1
rIc" txc .. DRG
to generate 125 Kbaud. xl lih (20. IJ-A + 20 /J-A)
PCSS: ThePCSS signal' qr?-ves U2 and U4.
• 101 (2.0 rnA)
loh (- 400 /J-A)
> iii (':'0.5 mA + -0.5 mAl,
> lih (20 /J-A + 20 /J-A)
101 (2.0 mAl > iii (-0.4 mA
loh (-400 /J-A)
>
lih (20 /J-A
+
Certain symbolic conventions are adhered to throughout the analysis below and are introduced for clarity..
1. All timing variables with a lower case first letter are
82530 timing requirements or responses (i.e., tRR).
2.. All timing variables with Upper case first letters are
80186 timing responses or requirements Unless preceded by' another device's alpha-numeric code (Le.,
Tclcl or '373 Tpd) .
3. In the writ!...£}'cle analysis, the timing variable
TpdW~186-WRS30 represents th~ propagation delay between tne leading or trailin~~e of the WR
signalleav!!!Lthe 80186 and the WR edge arrival at
the 82530 WR input.
Read Cycle
INTA: The INTA signal drives 2(Ul) and US.
•
ANALYSIS
+
-0.8 mA + -0.4 mAl
40/J-A + 20/J-A)
All the' 62530 1;0 pins are TTL volta~ l~el co~patible.
'.
,
1. tAR: Address valid to RD active set up time for the
82530. Since the propaption delay is the ~orst case
path in the assunied typical syst~" 'the war~ is ,calculated only for a propagation delay constrained imd not
an AL~ limited pa~h. The spec value is 0 ns miIilinum:
• 1 Telcl - Teiav(miVc) - '245 Tpd(max)
2(U2) ipd(min) - tAR (min)
= 125
2·438
- 55 - 20.8
+
10
+ 2(2)
- 0
+ Telr1(mln) +
.
= 63.2 ns margin
inter
AP-222
2. tRA: Address to RD inactive hold time. The ALE
delay is the worst case path and the 82530 requires 0 ns
minimum.
• 1 Telel - Telrh (max) + Tehlh(min) + '373 LE
Tpd(min) - 2(U2) Tpd(max)
• 3 Telel + 1(TciCiwalt state) - TelaY(max) - '373
Tpd(max) - '245 Tpd - Tdvcl(min) ~ tAD
= 375 + 125 - 55 - 20.8 -14.2 - 20 -325 = 65'ns
margin
= 55 - 55 + 5 + 8 - 2(5.5) = 2 ns margin
Write Cycle
3. tCLR: CS active low to RD active low set up time.
The 82530 spec value is 0 ns minimum.
1. tAW: Address required valid to WR active low set
up time. The 82530 spec is 0 ns minimum.
• 1 Telcl - Tclcsv(max) - Tclrl(min) - U2
skew(RD - CS) + U2 Tpd(min)
• Tclel - TclaY(max) - TcvctV(mi!'l) '-'. '373 Tpd(max)
+ TpdWR186 - WR530(LOW) [Tclcl - TCiictv(min) +
U3 Tpd(min) + U4 Tpd(min)1 - tAW
= 125 - 66 -10 -1 + 2 =.50 ns margin
4. tRCS: RD inactive to CS inactive hold time: The
82530 spec calls for 0 ns minimum.
•
Tescsx(mln) - U2 skew(RD - C8) - U2 Tpd(max)
= 35 - 1 - 5.5 = 28.5 ns margin
5. tCHR: CS inactive tQ RD active set up time. 'The
82530 requires 5 ns minimum.
• 1 Telcl + 1 Tchcl - Tchesx(max) + Tclrl(rnin) - U2
skew (RD - C8) + U2 Tpd(min) - tCHR
= 125 + 55 - 35 - 10 - 1 + 2 - 5 = 131
2. tWA: WR inactive to address in"alid hold time. The
82530 spec is 0 ns.
• Teleh(mfn)"': Tcvetx(max) + Tchll1(min) + '373 LE
Tpd(min) - TpdWR186=WFi530(HIGH) [U2 Tpd(max) +
U3 Tpd(max) + U4 Tpd(max))
= 55 - 55 + 5 + 8 - [5.5 + 3 + 7.11 = -2.6 ns·
margin
3. tCLW: Chip select active low to WR active low hold
time. The 82530 spec is 0 ns.
"S m\ll'gin
6. tRR: RD pulse active low time. On~ ~186 wait state
is included to meet the 150 ns minimum timing requirements of the 82530.
•
= 125 - 55 - 5 - 20.8 + [125 - 5 + 1 + 4.41 :... 0 .
= 170.6 ns margin
• 1 Telel - TelcsY(max) +. Tcvctv(min~ ~. U2 Tpd(max)
+ TpdWRl86=WR530(LOW) [Telcl'- Tcvetv(min) + U3
Tpd(min) + U4 Tpd(min)1
,
,
'
= 125 -; 66 + 5 - 5.5,+ [125 - 5 + 1
183.9 ns margin
Trlrh(min) + 1(TciCiwait state) - 2(U2 skew) - tRR
= (25Q-50) + 1(125) - 2(1) - 150 = 173 ns margin
+
4.41 =;'
4. tWCS: WR invaljd to Chip Select invalid hold time.
82530 spec is 0 ns.
7. tRDV: RD active low to data valid maximum delay
for 80186 read data set up time (Tdvcl = 20 ns). The
margin is calculated on the Propagation delay path
(worst case).
.
• Texesx(min) - U2 Tpd(max) TpdWR186=WR530(HIGH) [U2 Tpd(max) + U3
Tpd(max) + U4 Tpd(max)1
= 35 + 1.5 ~ [5.5 + 3 + 7.11 = 20.~9 ns margin
• 2 Tclcl + 1(Telclwait state) - Tclrl(max) - Tdvcl(min)
- '245 Tpd(max) - 82530 tRDV(max) - 2(U2) Tpd(max)
5.
tCHw: Chip Select inactive high tQ'~ active lo~
= 2(125) + 1(125) - 70 - 20 - 14.2 - 105 - 2(5.5)
= 154 ns margin
set
8. tDF: RD inactive to data output f1<>l!.~ delay. The
margin is calculated to DEN active low of n~xt cycle.
• 1 Telel + Tehel(min) + TCvctv(min) - Tehesx(max) U2 Tpd(max) + TpdWR186=~530(LOW) [Telel TcvQtv(l'nin) + U3 Tpd(min) + U4 TPd(mln)1 - tCHW
2 Tclcl -l; Teleh(min) - Telrh(max) + Tehetv(min) .
'" 12S 4- 55 +'5 - 35' i- 5.S' + [~25', -5 + 1 + 4.4)'5 ,'"' 264 ns margin,
"
•
2(U~) Tpd(max) - 82530 tDF(mali)
= 250 + 55 -55
+ 10 -
11 - 70 = 179 ns margin
9. tAD: Address required valid to read data valid maximum delay. The 82530 spec value is 325 ns maximum.
up time. The 82;30 spec 'is 5 n s . · '
.
6. tWW: WR active low,pulse. 82530 requires: a minimum of 60 ns from the falling to the rising edge of WR.
This includes one wait state.
2-439
AP-222
'I·v>
.'
•. '
• TwlWh [2Tclcl - 40] + 1 (iCjCiwalt state) - Tpd'iiWi1
186-WFi530(lOW) [Tcl!!!...::" Tcvctv~n) + U3 Tpd(max)
+ U4 Tpd(max)) + TpdWR/186=WR/530(HIGH) [U2
Tpd(min) U3 T,pd(min) + U4 Tpd(min)1 - tWW
should never exist. 82530 drivers should insure that at
least one CPU cycle separates INTA and WR or RD
cycles.
= 210 + 1(125) - [125,- 5 + 4.5
3.21 - 60 = 135.6 ns margin
4. tWI: WR inactive high to INTA, active low minimum hold time. The spec is 0 ns and the margin assumes CLK coincident with INTA.
+
+
9.21 - [1.5
+
1
7. tDW: Data valid to WR active low setup time. The
82530 spec requires 0 ns.
• Tcvctv(mi~ Tcldv(max) - '245 Tpd(max) +
TpdWR186-WR530(lOW) [Tclcl - Tcvctv(min) + U3
Tpd(min) + U4 Tpd(min)l
= 5 - 44 - 14.2
margin
+
125 - 5
+
+
1.0
• Tclcl - Tcvctx(max) - TpdWR186 - WR530(HIGH)
[U3 Tpd(max) + U4 Tpd(max») + Tcvctv(min) + Ul
Tpd(min)
= 125 - 55 - [5.5
margin
4.4 = 72:2 ns
+
3
+
7.1)
+
5
+
10 = 69.4 ns
8. tWD: Data valid to WR inactive high hold time. The
82530 requires a hold time of 0 ns.
5. tIR: INTA inactive high to RD active low minimum
setup time. This spec pertains only to 82530 RD cycles
and has a value of 55 ns. The margin is calculated in
the same manner as tIW.
• Tclch - skew (Tcvctx(max) + Tcvctx(min)1 + '245
OE Tpd(min) - TpdWFi186-WFi530(HIGH) [U2 Tpd(max)
+ U3 Tpd(max) + U4 Tpd(maX»)
6. tRI: RD inactive high to' INTA active low minimum
hold time. The spec is 0 ns and the margin assumes
CLK coincident with INTA.
.
= 55 - 5
margin
+
11.25 - [5.5
+
3.0
+
7.1) = -50.6 ns
•
+
Tcici - Tclrh(max) - 2 U2 Tpd(max)
Ul Tpd(min)
= 125
INTACycle: .
1. tIC: This 82530 spec implies that the INTA signal is
latched internally on the rising edge .of CLK (82530).
Therefore the maximum delay between the 80186 asserting INTA active low or inactive high and the 82530
internally recognizing the new state of INTA is the
propagation delay through Ul plus the 82530 CLK period.
•
Ul Tpd(max)
= 45
+
+
82530 ClK period
3. tIW: INTA inactive high to WR active low minimum setup time. The spec pertains only to 82530 WR
cycle and has a value of 55 ns. The margin is calculated
assuming an 82530 WR cycle occurs immediately after
an INTA cycle. Since the CPU cycles following an
82530 INTA cycle are devoted to locating and exil'cut-'
ing'the proper interrupt service routine, this condition
5& - 2(5.5)
+
5
+
10 = 74 ns margin
7. tIID: INTA active low to RD active low minimum
setup time. This parameter is system dependent. For
any SCC in the daisy chain, tIID must be greater than
the sum of tCEQ fur the highest priority device in the
daisy chain, tEl for this particular SCC, and tEIEO for
each device separating them in the daisy chain. The
typical system with only I SCC requires t1ID tQ be
greater than tCEQ. Since tEl occurs coincidently with
tCEQ and it is smaller it can be neglected. Additionally, tEIEO does not have any relevance to a ~ystem with
only one SCC. Therefore tIID > tCEQ = 250 ns.
250 = 295ns
2. tCI: rising edge of CLK to iN'i'A hold time. This
spec requires that the state of INTA remains constant
for 100 ns. after the rising edge of CLK. If ~ spec is
violated any change in the state of INTA may not be
internally latched in the 82530. tCI becomes criti,cal at
the end of an iNTA cycle when p;n'A goes iJ,lactive.
When calculating margins with tCI, an extra 82530
CLK
. .period must be add~ to the," INTA ~tive delay.
'7
+ .Tcvctv(min)
+
• 4 Tclcl
2 Tidle states - Tcvctv(max) - tiC [Ul .
Tpd(max) + 82530 ClK period) + Tcvctv(min) + U5
Tpd(min) + U2 Tpd(min) - tllO
= 500 + 250 - 70 - [45
= 148 ns margin
+
250) +' 5
+ ,6 +
2 - 250
:
8. tIDV: RD active low to interrupt vector valid delay.
The 80186 expects the interrupt vector to be valid on
the data bus a minimum of 20 ns before T40f the second acknowledge cycle (Tdvcl). tIDV spec is 1'00 ns
manmum.
.
• 3 Tclcl - Tcvctv(max) - U5 Tpd{max) - U2
Tpd(max) - tIOV(max) - '245 Tpd(max) - Tdvcl(min)' .
= 375 - 70 - 25 - 5.5 - 100 - 14.2 - 20 = 140.3
ns margin
2-440
inter
Ap·222
9. tIl: RD pulse low time. The 82530 requires a minimum of 125 ns.
• 3 Tclcl - Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) + Tcvctx(min) + U5 Tpd(min) + U2 Tpd(min)
- tll(min)
= 375 - 70 - 25 - 5.5
162 ns margin
+
5
+
6
+
1.5 - 125 =
• Tclcl + 2(Tclclwail state) - Tcvctv(min) TpdWR186-WI'I530(LOW) [Tclcl - Tcvctv(min)
Tpd(max) + U4 Tpd(max)] - Tdrqcl - tWRI
DMACycle
Fortunately, the 80186 DMA controller emulates CPU
read and write cycle operation during DMA transfers.
The DMA transfer timings are satisfied using the above
analysis. Because of the 80186 DMA request input requirements, two wait states are necess~o prevent
inadvertent DMA cycles. There are also CPUDMA intracycle timing considerations that need to be addressed.
1. tDRD: RD inactive high to DTRREQ (REQUEST)
inactive high delay. Unlike the READYREQ signal,
DTRREQ does not immediately go inactive after the
requested DMA transfer begins. Instead, the DTRREQ
remains active for a maximum of 5 tCY + 300 ns. This
delayed request pulse could trigger a second DMA
transfer. To avoid this undesirable condition, a D Flip
Flop is implemented to reset the DTRREQ signal inactive low following the initiation of the requested DMA
transfer. To determine if back to back DMA transfers
are required in a source synchronized configuration,
the 80186 DMA controller samples the service request
line 25 ns before Tl of the deposit cycle, the second
cycle of the transfer.
•
4 Tclcl - Tclcsv(max) - U4Tpd(max) - Tdrqcl(min)
= 500 - 66 - 10.5 - 25 = 398.5 ns margin
2. tRRI: 82530 RD active low to REQ inactive high
delay. Assuming source synchronized DMA transfer,
the 80186 requires only one wait state to meet the tRRI
spec of 200 ns. Two are included for consistency with
tWRI.
• 2 Tclcl + 2(Tclclwail slate) - Tclrl(max) - 2(U2)
Tpd(max) - Tdrqcl - tRRI
=2(125)
margin
+ 2(125)
3. tWRI: 82530 WR active low to REQ inactive high
delay. Assuming destination synchronized DMA transfers, the 80186 needs two wait states to meet the tWRI
spec. This is because the 80186 DMA controller samples requests two clocks before the end of the deposit
~e. This leaves only I Tclcl + n(wait states) minus
WR active delay for the 82530 to inactivate its REQ
signal.
- 70 - 2(5.5) - 200 = 219 ns
2-441
=375 - 5 - [125 - 5
11.3 ns margin
+
4.5
+
+
U3
9.21 - 25 - 200 =
NOTE:
If one wait state DMA interface is required, external
logic, like that used on the DTRREQ signal, can be
used to force the 82530 REQ signal inactive.
4. tREC: CLK recovery time. Due to the internal data
path, a recovery period is required between SCC bus
transactions to resolve metastable conditions internal to
the SCC. The DMA request lines are masked from requesting service until after the tREC has elapsed. In
addition, the CPU should not be allowed to violate this
recovery period when interleaving DMA transfers and
CPU bus cycles. Software drivers or external logic
should orchestrate the CPU and DMA controller operation to prevent tREC violation. In this example circuit, tREC could be imprOVed by clocking the '530 with
a 6 MHz clock.
Reset Operation
During hardware reset, the system RESET signal is asserted high for a minimum of four 80186 clock cycles
(1000 ns). The 82530 requires WR and RD to be simultaneously asserted low for a minimum of 250 ns.
• 4 Tclcl - U3 Tpd(max) - 2(U2) Tpd(max)
Tpd(min) - tREe
= 1000 - 17.5 - 2(5.5)
margin
+
+
U4
3.5 - 250 ns = 725 ns
Other Components
3
inter
8291A
GPIB TALKER/LISTENER
Designed to Interface Microprocessors
MHz Clock Range
• 1-8
• (e.g.,
8048/49, 8051, 8080/85, 8086/88)
16 Registers (8 Read, 8 Write), 2 for
•
to an IEEE Standard 488 Digital
Data Transfer, the Rest for Interface
Interface Bus
Function Control, Status, etc.
Programmable Data Transfer Rate
Directly Interfaces to External Non• Complete
•
Inverting Trancelvers for Connection to
Source and Acceptor
• Handshake
the GPIB
Provides Three Addressing Modes,
Complete Talker and Listener
• Allowing
• Functions
the Chip to be Addressed
with Extended Addressing
Either
as
a Major or a Minor Talker/
Service Request, Parallel Poll, Device
• Clear,
Listener with Primary or Secondary
Device Trigger, Remote/Local
Addressing
Functions
Handshake Provision Allows for
Selectable Interrupts
• DMA
• On-Chip
Bus Transfers without CPU Intervention
and Secondary
• Address Primary
OutP,ut Pin
Recognition
• Trigger
On-Chip
EOS (End of Sequence)
AutomatiC Handling of Addressing and
•
• Handshake
Message
Recognition Facilitates
Protocol
•
Handling of Multi-Byte Transfers
Provision for Software Implementation
of Additional Features
The 8291A is an enhanced version of the 8291 GPIB Talker/Listener designed to interface microprocessors to
an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard's interface functions
except for the controller. The controller function can be added with the 8292 GPIB Controller, and the 8293
GPIB Transceiver performs the electrical interface for Talker/Listener and Talker/Listener/Controller configurations.
Vee
EOI
8291A
I
37
iiiR"F5
DAV
iiiOs
i5i07
TO NON INVERTING
BUS TRANSCEIVERS
lrn56
i5iOs
i5i04
I
i5iOJ
i5'i02
i5iOi
T/R CONTROL
SAO
ATN
iffiii
iTc
RS2
205248:-1
Figure 1. Block Diagram
205248-2
Figure 2. Pin Configuration
3-1
November 1986
Order Number: 205248-002
inter
8291A
to a, listener role or vice-versa during a holdoff,
the "Holdoff on Source Handshake" has been
eliminated. Only "Holdoff on Acceptor Handshake" is available.
8291A FEATURES AND
IMPROVEMENTS
The 8291A is an improved design of the 8291 GPIB
Talker/Listener. Most of the functions are identical
to the 8291, and the pin configuration is unchanged.
8. The rsv local message is cleared automatically
upon exit from SPAS if (APRS:STRS:SPAS) occurred. The automatic resetting of the bit after the
serial poll is complete simplifies the service re'
quest software.
The 8291A offers the follOwing improvements to the
8291:
9. The SPASC interrupt on the 8291' has been replaced by the SPC (Serial Poll Complete) interrupt
on the 8291A. SPC interrupt is set on exit from
SPAS if APRS:STRS:SPAS occurred, indicating
that the controller has read the bus status byte
after· the 8291A requested service. The SPASC
interrupt was ambiguous because a controller
could enter SPAS and exit SPAS generating two
SPASC interrupts without reading the serial poll
status byte. The SPC interrupt also simplifies the
CPU's software by eliminating the interrupt when
'
the serial poll is half way done,
1. EOi is active with the data as a ninth data bit rather than as a control bit. This is to comply with
some additions to the 1975 IEEE-488 Standard
incorporated in the 1978 Standard.
2. The BO interrupt is not asserted until RFD is true.
If the Controller asserts ATN synchronously, the
data is guaranteed to be transmitted. If the Controller asserts ATN asynchronousiy, the SH
(Source Handshake) will return to 5105 '(Source
Idle State), and the output data will be cleared.
Then, if ATN is released while the 8291A is addressed to talk, a new BO interrupt will be generated. This change fixes 8291 problems which
caused data to be lost or repeated and a problem
with the RQS bit (sometimes cannot be asserted
while talking).
10. The rtl Auxiliary Command in the 8291 has been
replaced by Set and Clear rtl Commands in the
8291 A. Using the new commands, the CPU has
the flexibility to extend the length of local mode
or leave it as a short pulse as in the 8291.
3. llOC and REMC interrupts are setting flipflops
rather than toggling flipflops in the interrupt backup register. This ensures that the CPU knows that
these state changes have occurred. The actual
state can be determined by checking the llO and
REM status bits in the upper nibble of the Interrupt Status 2 Register.
11. A holdoff RFD on GET, SOC, and DCl feature
has been added to prevent additional bus activity while the CPU is responding to any of these
commands. The feature is enabled by a new bit
(B4) in the Auxiliary Register B.
'
12. On the 8291, BO could cease to occur upon IFC
going false if IFC occurred asynchrono~. On
the 8291A, BO continues to occur after IFC has
gone false even if it arrived asynchronously.
4. DREQ is cleared by DACK (RD + WR). DREQ on
the 8291 was cleared only by DACK which is not
compatible with the 8089 I/O Processor.
13. User's software can distinguish between the
8291 and the 8291A as follows:
5. The INT bit in Interrupt Status 2 Register is duplicated in bit 7 of the Address 0 Register. If software polling is used to check for an interrupt, INT
in the Address 0 Register should be polled rather
than the Interrupt Status 2 Register. This ensures
that no interrupts are lost due to asynchronous
status reads and interrupts.
a) pon (OOH to register 5)
b) RESET (02H to register 5)
c) Read Interrupt Status 1 Register. If BO interrupt is set, the device is the 8291. If BO is
clear, it is the a291A.
6. The 8291A's Send EOI Auxiliary Command works
on any byte including the first byte of a message.
The 8291 did not assert EOI after this command
for a one byte message nor on two consecutive
bytes.
This can be used to set a flag in the user's software which will permit special routines to be executed for each device. It could be included as
part of a normal initialization procedure as the
first step after a chip reset.
7. To avoid confusion between holdoff on DAV versus RFD if a device is readdressed from a talker
3-2
8291A
Table 1. Pin Description
Pin
No.
Type
00- 0 7
12-19
I/O
DATA BUS PORT: To be connected to microprocessor data
bus.
RSO-RS2
21-23
I
REGISTER SELECT: Inputs, to be connected to three
non multiplexed microprocessor address bus lines. Select
which of the 8 internal read (write) ~isters will be read from
(written into) with the execution of RO (WR).
CS
8
I
CHIP SELECT: When low, enables reading from or writing into
the register selected by RSO-RS2.
RO
9
I
READ STROBE: When low with CS or OACK low, selected
register contents are read.
WR
10
I
WRITE STROBE: When low with CS or OACK low, data is
written into the selected register.
INT(INT)
11
0
INTERRUPT REQUEST: To the microprocessor, set high for
request and cleared when the appropriate register is
accessed by the CPU. May be software configured to be
active low.
OREQ
6
0
DMA REQUEST: Normally low, set high to indicate byte
output or byte input in OMA mode; reset by OACK.
OACK
7
I
DMA ACKNOWLEDGE: When low, resets OREQ and selects
data in/data out register for OMA data transfer (actual transfer
done by RO/WR pulse).
Must be high if OMA is not used.
TRIG
5
0
CLOCK
3
I
EXTERNAL CLOCK: Input, used only for T, delay generator.
May be any speed in 1-8 MHz range.
RESET
4
I
RESET INPUT: When high, forces the device into an "idle"
(initialization) mode. The device will remain at "idle" until
released by the microprocessor, with the "Immediate Execute
'pon" local message.
28-35
I/O
a-BIT GPIB OATA PORT: Used for bidirectional data byte
transfer between 8291A and GPIB via non-inverting external
line transceivers.
OAV
36
I/O
DATA VALID: GPIB handshake control line. Indicates the
availability and validity of information on the 0101-0108 and
EOllines.
NRFO
37
I/O
NOT READY FOR DATA: GPIB handshake control line.
Indicates the condition of readiness of device(s) connected to
the bus to accept data.
NOAC
38
I/O
NOT DATA ACCEPTED: GPIB handshake control line.
Indicates the condition of acceptance of data by the device(s)
connected to the bus.
ATN
26
I
ATTENTION: GPIB command line. Specifies how data on 010
lines are to be interpreted.
Symbol
0101-0108
Name and Function
TRIGGER OUTPUT: Normally low; generates a triggering
pulse with 1 p.sec min. width in response to the GET bus
command or Trigger auxiliary command.
3-3
intJ
8291A
Table 1. Pin Description (Continued)
Symbol
Pin
No.
Type
IFC
24
I
INTERFACE CLEAR: GPIB command line. Places the
interface functions in a known quiescent state.
SRQ
27
0
SERVICE REQUEST: GPIB command line. Indicates the need
for attention and requests an interruption of the current
sequence of events on the GPIB.
REN
25
I
REMOTE ENABLE: GPIB command line. Selects (in
conjunction with other messages) remote or local control of
the device.
EOI
39
I/O
END OR IDENTITY: GPIB command line. Indicates the end of
a multiple byte transfer sequence or, in conjunction with ATN,
addresses the device during a polling sequence.
T/R1
1
0
EXTERNAL TRANSCEIVERS CONTROL LINE: Set high to
indicate output data/signals on the 0101-0108 and OAV lines
and input signals on the NRFO and NOAC lines (active source
handshake). Set low to indicate input data/signals on the
0101-0108 and OAV lines and output signals on the NRFO
and NOAC lines (active acceptor handshake).
T/R2
2
0
EXTERNAL TRANSCEIVERS CONTROL LINE: Set to
indicate output signals on the EOI line. Set low to indicate
expected input signal on the EOI line during parallel poll.
Vee
40
P.S.
POSITIVE POWER SUPPLY: (5V
GNO
20
P.S.
CIRCUIT GROUND POTENTIAL.
Name and Function
± 10%).
NOTE:
All signals on the 8291A pins are specified with positive 10~However, IEEE 488 specifies negative logic on its 16 signal
lines. Thus, the data is inverted once from 00-07 to 000-0108 and non-inverting bus transceivers should be used.
,. -
I
I
-
-
DMA
CONTROLLER
(OPTIONAL)
- _....."---"""'1 Tli'il
8291A
~-----,
GPIB
TIRl
t -_ _D_-A_C_K_--~i'; . " >:
Ooril.ldIe,$tata ;" , ; .\1.
0108'
'COntltlf:ler ParaM Pou$iat.f'.' ',I "
CPPS
OPWS
,CSBS
SIDS
SIIS
OontrOlIer ParalteJ·PoltWait State ' "
Oont!'Qlter StandbY itate "
.
state
CSNS
Controtter~rvi6e Not,Rlflquested
CSRS, , ControJter seOti9fJ~~~~ S~~~" ,
CSWS
CTRS.
bCAS
DCIS
DTAS
OTIS
LACS
LADS
LIDS
LOCS
LPAS
LPIS
LWLS
NPRS
PACS
PPAS
PPIS
Parallel Poll Standby State
Parallel Poll Unaddressed to Configure
State
Remote State
Remote With Lockout State
System Control Active State
Source Delay State
Source Generate State
System Control Interface Clear Active
State
Source Idle State
System Control Interface Clear Idle
State
System Control Interface Clear Not
Active State
Source Idle Wait State
System Control Not Active State
Serial Poll Active State
Serial Poll Idle State
Serial Poll Mode State
System Control Remote Enable Active
State
System Control Remote Enable Idle
State
System Control Remote Enable Not
Active State
Service Request State
Source Transfer State
Source Wait for New Cycle State
Talker Active State
Talker Addressed State
Talker Idle State
Talker Primary Idle State
SINS
'·Contro.er Synol)ronou$ Wajtsta~·
ControUer Tran,sferstate ., .
SIWS
SNAS
SPAS
SPIS
SPMS
SRAS
Device Clear Active State
Device Clear Idle State
Device Trigger Active State
Device Trigger Idle State
Listener Active State
Listener Addressed State
Listener Idle State
Local State
Listener Primary Addressed State
Listener Primary Idle State
Local With Lockout State
Negative Poll Response State
Parallel Poll Addressed to Configure
State
Parallel Poll Active State
Parallel Poll Idle State
SRIS
SRNS
SRQS
STRS
SWNS
TACS
TAOS
TIDS
TPIS
The Controlier function is implemented on the Intel® 8292,
Table 3. IEEE 488 Interface Message Reference List
Mnemonic
Interface Function(s)
Message
LOCAL MESSAGES RECEIVED (By Interface Functions)
gts(1)
go to standby
ist
individual status
Ion
listen only
Ipe
local poll enable
nba
new byte available
power on
pon
ready
rdy
rpp(1)
request parallel poll
rsc(1)
request system control
rsv
request service
return to local
rtl
sic(1)
send interface clear
sre(1)
send remote enable
tca(1)
take control asynchronously
3-6
C
PP
L,LE
PP
SH
SH, AH, T, TE, L, LE, SR, RL, PP, C
AH
C
C
SR
RL
C
C
C
inter
8291A
Table 3. IEEE 488 Interface Message Reference List (Continued)
Mnemonic
Message
Interface Functlon(s)
tcs(1)
take control synchronously
ton
talk only
REMOTE MESSAGES RECEIVED
ATN
Attention
DAB
Data Byte
DAC
Data Accepted
DAV
Data Valid
DCL
Device Clear
END
End
GET
Group Execute Trigger
GTL
Go to Local
lOY
Identify
IFC
Interface Clear
LLO
Local Lockout
MLA
My Listen Address
MSA
My Secondary Address
MTA
My Talk Address
OSA
Other Secondary Address
OTA
Other Talk Address
PCG
Primary Command Group
PPC(2)
Parallel Poll Configure
[PPD] (2)
Parallel Poll Disable
[PPE] (2)
Parallel Poll Enable
PPRN(1)
Parallel Poll Response N
PPU(2)
Parallel Poll Unconfigure
REN
Remote Enable
Ready for Data
RFD
Request Service
RQS
[SOC]
Select Device Clear
SPD
Serial Poll Disable
SPE
Serial Poll Enable
SQR(1)
Service Request
STB
Status Byte
TCT or [TCT](1)
Take Control
UNL
Unlisten
REMOTE MESSAGES SENT
ATN
Attentions
DAB
Data Byte
DAC
Data Accepted
DAV
Data Valid
Device Clear
DCL
END
End
GET
Group Execute Trigger
GTL
Go to Local
lOY
Identify
IFC
Interface Clear
Local Lockout
LLO
MLAor [MLA]
My Listen Address
MSAor[MSA]
My Secondary Address
MTAor [MTA]
My Talk Address
'Other Secondary Address
OSA
3-7
AH,C
T, TE
SH,AH,T,TE,L,LE,PP,C
(Via L, LE)
SH
AH
DC
(via L, LE)
DT
RL
L, LE, PP
T, TE, L, LE, C
RL
L, LE, RL, T, TE
TE, LE, RL
T, TE, L, LE
TE
T, TE
TE, LE, PP
PP
PP
PP
(viaC)
PP
RL
SH
(via L, LE)
DC
T, TE
T, TE
(via C)
(via L, LE)
C
L,LE
C
(ViaT,TE)
AH
SH
(viaC)
(viaT)
(viaC)
(via C)
C
C
(viaC)
(viaC)
(viaC)
(viaC)
(via C)
8291A
Table 3. IEEE 488 Interface Message Reference List (Continued)
Mnemonic
Message
Interface Function(s)(3)
OTA
PCG
PPC
[PPO)
[PPE)
PPRN
PPU
REN
RFO
ROS
[SOC]
SPO
SPE
SRO
STB
TCT
UNL
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Oisable
Parallel Poll Enable
Parallel Poll Response N
Parallel Poll Unconfigure
Remote Enable
Ready for Oata
Request Service
Selected Oevice Clear
Serial Poll Oisable
Serial Poll Enable
Service Request
Status Byte
Take Control
Unlisten
(viaC)
(viaC)
(viaC)
(viaC)
(viaC)
PP
(viaC)
C
AH
T, TE
(viaC)
(viaC)
(viaC)
SR
(viaT,TE)
(viaC)
(viaC)
NOTES:
1. These messages are handled only by Intel's 8292.
2. Undefined commands which may be passed to the microprocessor.
3. All Controller messages must be sent via Intel's 8292.
telling the 8291,6. to release the holdoff. In this way,
the same byte may be read several times, or an over
anxious talker may be held off until all available data
has been processed.
8291A Registers
A bit-by-bit map of the 16 registers on the 8291 A is
presented in Figure 5. A more detailed explanation
of each of these registers and their functions follows. The access of these registers by the microE!:2..cessor is accomplished by using the CS, RO,
WR, and RSO-RS2 pins.
Register
All Read Registers
All Write Registers
High Impedance
CS
RD
WR
RSO-RS2
0
0
1
0
1
d
1
0
d
CCC
CCC
ddd
When the 8291 A is addressed to talk, it uses the
data-out register to move data onto the GPIB. After
the BO interrupt is received and a byte is written to
this register, the 8291A initiates and completes the
handshake while sending the byte out over the bus.
In the BO interrupt disable mode, the user should
wait until BO is active before writing to the register.
(In the OMA mode, this will happen automatically.) A
read of the Oata-In Register does not destroy the
information in the Oata-Out Register.
Data Registers
I 017 I 016 I 015 I 014 I 013 I 012 I 011 I 010
Interrupt Registers
I
ICPTI APT IGETIENOloECI ERR I BO
OATA-IN REGISTER (OR)
BI
I
INTERRUPT STATUS 1 (1 R)
100710061005100410031002100110001
liNT I SPAS I LLO I REM I SPC I LLOC I REMC I Aosci
OATA-OUT REGISTER (OW)
INTERRUPT STATUS 2 (2R)
The Oata-In Register is used to move data from the
GPIB to the microprocessor or to memory when the
8291 A is addressed to listen. Incoming information
is separately latched by this register, and its contents are not destroyed by a write to the data-out
register. The RFO (Ready for Oata) message is held
false until the byte is removed from the data in register, either by the microprocessor or by OMA. The
8291A then completes the handshake automatically.
In RFO holdoff mode (see Auxiliary Register A),· the
handshake is 'not finished until a command is sent
ICPTI APT IGETIENOloECI ERR I BO I
BI
I
INTERRUPT ENABLE 1 (1W)
I 0 I 0 IOMAOI OMAII SPC I LLOclREMCIAOscl
INTERRUPT ENABLE 2 (2W)
IINTloTOI OLoIA05-0IA04-0IA03-0IA02-0IA01-01
AOORESS 0 REGISTER
3-8
inter
8291A
Figure 5. 8291A Registers
READ REGISTERS
REGISTER SELECT
WRITE REGISTERS
CODE
RS2 RS1 RSO
r-I0-17---'-10-16---'-10-1-S'-10-1-4"'10-1-3'-10-1-2-'1-01-1-'1-01---'0I 0
0
0 r-I0-0-7'-10-0-6'-1o-o-s'-I0-0-4T'""10-0-3T'""10-0-2-'10-O-1"T1-00---'0I
DATA OUT
DATA IN
I CPT I APT I GET I END I DEC I ERR I BO I BI
o
o
I CPT I APT I GET I END I DEC I ERR I BO I BI I
INTERRUPT STATUS 1
liNT ISPASI LLO I REM I
INTERRUPT ENABLE 1
S~C ILLOCIREMCIAOScl
o
0
o
INTERRUPT STATUS 2
S8 ISEasl S6 I S5 I S4 I S3 I S2
INTERRUPT ENABLE 2
S1
o
SERIAL POLL STATUS
I ton I Ion I EOI I LPASITPASI LA I TA IMJMNI
SERIAL POLL MODE
o
o
I TO
I LO
ICPT7ICPT6ICPT5ICPT4ICPT3ICPT2ICPT1ICPTOI
I
0
!
0
! 0
IAOM1!AOMOI
ICNT2ICNT1!CNTOICOM4ICOM3!COM2!COM1ICOMOI
o
COMMAND PASS THROUGH
AUXMOOE
o
liNT I OTO I OLO IAOS.0IA04.0IA03.0IA02.0IA01.01
IARS I
OT I OL ! ADS! A04! A031 A021 A01 I
ADDRESS 0/1
ADDRESS 0
x
0
ADDRESS MODE
ADDRESS STATUS
IOT1 I 0L1 IAOS.1IA04.1IA03.1IA02.1IA01.11
1
ADDRESS 1
I EC7 ! EC6! ECS! EC41 EC31 EC21 EC1 I ECO !
EOS
The 8291A can be configured to generate an interrupt to the microprocessor upon the occurrence of
any of 12 conditions or events on the GPIB. Upon
receipt of an interrupt, the microprocessor must read
the Interrupt Status Registers to determine which
event has occurred, and then execute the appropriate service routine (if necessary). Each of the 12
interrupt status bits has a matching enable bit in the
interrupt enable registers. These enable bits are
used to select the events that will cause.the INT pin
to be asserted. Writing a logic "1" into any of these
bits enables the corresponding interrupt status bits
to generate an interrupt. Bits in the Interrupt Status
Registers are set regardless of the states of the enable bits. The Interrupt Status Registers are then
cleared upon being read or when a local pon (poweron) message is executed. If an event occurs while
one of the Interrupt ,Status Registers .is being read,
the event is held until after its register is cleared and
then placed in the register.
The mnemonics for each of the bits in these registers and a brief description of their respective functions appears in Table 4. This table also indicates
how each of the interrupt bits is set.
NOTE:
The INT bit in the Address 0 Register is a duplicate
of the INT bit in the Interrupt Status 2 Register. It is
only a status bit. It does not generate interrupts and
thus does not have a corresponding enable bit.
The BO and BI interrupts enable the user to perform
data transfer cycles. BO indicates that a data byte
should be written to the Data Out Register. It is set
by TACS. (SWNS + SGNS) • RFD. It is reset when
the data byte is written, ATN is asserted, or the
8291A exits TACS. Data should never be written to
the Data Out Register before BO is set. Similarly, BI
is set when an input byte is accepted into the 8291 A
and reset when the microprocessor reads the Data
In Register. BO and BI are also reset by pon (poweron local message) and by a read of the Interrupt
Status 1 Register. However, if it is so desired, data
transfer cycles may be performed without reading
the Interrupt Status 1 Register if all interrupts except
for BO or BI are disabled; B0 and .BI will automatically reset after each byte is transferred.
NOTE:
Reading the interrupt status registers clears the bits
which were set. The software must examine all
relevant bits in the interrupt status registers before
disregarding the value or an important interrupt may
be missed.
3-9
8291A
",Table 4. Interrupt Bits
Indicates Undefined Commands
CPT
An undefmed command has been received.
Sel by (TPAS + LPAS)oSCGoACDSoMODE 3
APT
A secondary address must be passed through'
to the microprocessor for recog,nition.
Set by DTAS
GET
A group execute trigger has occurred
Set by (EOS + EOI)oLACS
END
An EOS or EOI message has been received.
Set by DCAS
DEC
Device Clear Active State has occurred
Set by TACS.nba.DAC.RFD
ERR
Interface error has occurred; no listeners
are active.
TACSo(SWNS + SGNS)
BO
A byte should be output.
Set by LACS.ACDS
BI
A byte has been Input
Shows status of the INT pin
INT
The device has been enabled for a serial poll
SPAS
The device IS in local lock out state.
.I LWLS+RWLS,
LLO
The device IS in a remote state.
I REMS+RWLS,
REM
SPAS --+~ if APRS:STRS:SPAS was true
LLOO LLO
SPC
LLOC
These are status only. They will not generate
interrupts, nor do they have corresponding
mask bits.
Serial Poll Complete interrupt.
Local lock out change interrupt.
'Remoti::Jocal
REMC
Remote/Local change interrupt.
'Addresseunaddressed
ADSC
Address status change interrupt.'
205248-24
NOTE:
1. In ton (talk-only) and Ion (listen-only) mOdes, no ADSC interrupt is generated.
If the 8291A is used in the interrupt mode, the INT
and DREQ pins can be dedicated to data input and
output interrupts, respectively by enabling BI and
DMAO, provided that no other interrupts are enabled. This eliminates the need to read the interrupt
status registers if a byte is received ,or transmitted.
completed. The bit will be set when the 8291A is an
active listener (LACS) and either EOS (provided the
End on EOS Received feature is enabled in the Auxiliary Register A) or EOI is received. EOS will generate an interrupt when the byte in the Data In Register matches the byte in the EOS register. Otherwise
the interrupt will be generated when a true input is
detected on EOI.
The ERR bit is set to indicate the bus error condition
when the 8291 A is an active talker and tries to send,
a byte to the GPIB, but there are no active listeners
(e.g.; all devices on the GPIB are in AIDS). The lOgical equivalent of (nba. TACS. DAC. RFD) will set
this bit.
The GET interrupt bit is used by the'microprocessor
to detect that DTAS has occurred. It is set by the
8291A when the GET message is received while it is
addressed to listen. The TRIG output pin of the
8291A fires when the GET message is received.
Thus, the basic operation of device trigger may be
started without microprocessor software intervention.
The DEC bit is set whenever DCAS has occurred.
The user must define a known stafe to which all de.
vice functions will retumin DCAS. Typically this
state will be a power-on state. However, the state of
the device functions at DCAS is at the designer's
discretion. It should be noted .that .DCAS has no effect on the interface functions which are retumed to
known state by the IFC (interface clear) message
or the pon local message. '
The APT interrupt bit indicates to the processor that
a secondary address is available in the CPT register
for validation. This interrupt will only occur if Mode 3
addressing is in effect. (Refer to the section on addressing.) In Mode 2, secondary addresses will be
recognized automatically on the 8291A. They will be
ignored in Mode 1.
a,
The END interrupt bit may be used by the microprocessor to detect that a multi-byte transfer has been
3-10
8291A
between memory and the GPIB; DMAI (DMA in) enables the DREO (DMA request) pin of the 8291A to
be asserted upon the occurrence of BI. Similarly,
DMAO (DMA out) enables the DREO pin to be asserted upon the occurrence of BO. One might note
that the DREO pin may be used as a second interrupt output pin, monitoring BI and/or BO and enabled by DMAI and DMAO. One should note that the
DREO pin is not affected by a read of the Interrupt
Status 1 Register. It is reset whenever a byte is written to the Data Out Register or read from the Data In
Register.
The CPT interrupt bit flags the occurrence of an undefined command and of all secondary commands
following an undefined command. The Command
Pass Through feature is enabled by the BO bit of
Auxiliary Register B. Any message not decoded by
the 8291A (not included in the state diagrams in Appendix B) becomes an undefined command. Note
that any addressed command is automatically ignored when the 8291A is not addressed.
Undefined commands are read by the CPU from the
Command Pass Through register of the 8291 A. This
register reflects the logic levels present on the data
lines at the time it is read. If the CPT feature is enabled, the 8291A will hold off the handshake until
this register is read.
To ensure that an interrupt status bit will not be
cleared without being read, and will not remain uncleared after being read, the 8291 A implements a
special interrupt handling procedure. When an enabled interrupt bit is set in either of the Interrupt
Status Registers, the input of the registers are
blocked until the set bit is read and reset by the
microprocessor. Thus, potential problems arise
when interrupt status changes while the register is
being blocked. However, the 8291 A stores all new
interrupts in a temporary register and transfers them
to the appropriate Interrupt Status Register after the
interrupt has been reset. This transfer takes place
only if the corresponding bits were read as zeroes.
An especially useful feature of the 8291A is its ability
to generate interrupts from state transitions in the
interface functions. In particular, the lower 3 bits of
the Interrupt Status 2 Register, if enabled by the corresponding enable bits, will cause an interrupt upon
changes in the following states as defined in the
IEEE 488 Standard.
Bit 0
Bit 1
Bit 2
ADSC
REMC
LLOC
change in LIDS or TIDS or MJMN
change in LOCS or REMS
change in LWLS or RWLS
Serial Poll Registers
The upper 4 bits of the Interrupt Status 2 Register
are available to the processor as status bits. Thus, if
one of the bits 0-2 generates an interrupt indicating
a state change has taken place, the corresponding
status bit (bits 3-5) may be read to determine what
the new state is. To determine the nature of a
change in addressed status (bit 0) the Address
Status Register is available to be read. The SPC interrupt (bit 3 in Interrupt Status 2) is set upon exit
from SPAS if APRS:STRS:SPAS occurred which indicates that the GPIB controller has read the bus
serial poll status byte after the 8291A requested
service (asserted SRO). The SPC interrupt occurs
once after the controller reads the status byte if
service was requested. The controller may read the
status byte later, and the byte will contain the last
status the 8291A's CPU wrote to the Serial Poll
Mode Register, but the SROS bit will not be set and
no interrupt will be generated. Finally, bit? monitors
the state of the 8291A INT pin. Logically, it is an OR
of all enabled interrupt status bits. One should note
that bits 3-6 of the Interrupt Status 2 Register do
not generate interrupts, but are available only to be
read as status bits by the processor. Bit? in Interrupt
Status 2 is duplicated in Address 0 Register, and the
latter should be used when polling for interrupts to
avoid losing one of the interrupts in Interrupt Status
2 Register.
S8
I SROS I S6 I S5 I S4
S3
S2
S1
I S6 I S5 I S4 I S3 I S2
S1
SERIAL POLL STATUS (3R)
S8
rsv
SERIAL POLL MODE (3W)
The Serial Poll Mode Register determines the status
byte that the 8291A sends out on the GPIB data
lines when it receives the SPE (Serial Poll Enable)
message. Bit 6 of this register is reserved for the rsv
(request service) local message. Setting this bit to 1
causes the 8291A to' assert its SRO line, indicating
its need for attention from the controller-in-charge of
the GPIB. The other bits of this register are available
for sending status information over the GPIB. Sometime after the microprocessor initiates a request for
service by setting bit 6, the controller of the GPIB
sends the SPE message and then addresses the
8291 A to talk. At this point, one byte of status is
returned by the 8291A via the Serial Poll Mode Register. After the status byte is read by the controller,
rsv is automatically cleared by the 8291A and an
SPC interrupt is generated. The CPU may request
service again by writing another byte to the Serial
Poll Mode Register with the rsv bit set. If the control-
Bits 4 and 5 (DMAI, DMAO) of the Interrupt Mask 2
Register are available to enable direct data transfers
3-11
8291A
ler performs a serial poll when the rsv bit is'clear, the
last status byte written will be read, but the SRO line
will not be driven by the 8291A and the SROS bit will
be clear in the status byte.
The Serial Poll Status Register is available for reading the status byte in the Serial Poll Mode Register. '
The processor may check the 'status of a request for
service by polling bit 6 of this register, which corresponds to SROS (Service Request State). When a
Serial Poll is 'conducted and the controller-in-charge
reads the status byte, the SROS bit is cleared. The
SRO line and the rsv bit are tied together.
Address Registers
TA IMJMNI
I ton lion I EOII LPAS I TPAS I LA
ADDRESS STATUS (4R)
liNT I DTO I DLO I ADS-O I AD4-0 I AD3-0 I AD2-0 I AD1·0 I
ADDRESS 0 (6R)
IX
To use Mode 2 addressing,the primary address must
be loaded into the Address 0 Register, and the Secondary Address is placed in the Address 1 Register.
With both primary and secondary addresses residing
on chip, the 8291A can handle all addressing sequences without processor intervention.
-In Mode 3, the 8291A handles addressing just as
it does in Mode 1, except that each Major or Minor
primary address must be followed by a secondary
address. All secondary addresses must be verified
by the microprocessor when Mode 3 is used. When
the 829,1A is in TPAS or LPAS (talker/listener primary addressed state), and it does not recognize the
byte on the 010 lines, an APT interrupt is generated
(see section on Interrupt Registers) and the byte is
available in the CPT (Command Pass-Through) Register. As part of its interrupt service routine, the microprocessor must read the CPT Register and write
one of the following responses to the Auxiliary Mode
Register:
1. 07H implies a non-valid secondary address
2. OFH implies a valid secondary address
IDT1IDL1IADS-1IAD4-1IAD3-1IAD2-1IAD1-11
ADDRESS 1 (7R)
I TO I LO I
0 I
0
0
I
0
,
IADM11ADMoi
Setting the TO bit generates the local ton (talk-only)
message and sets the 8291 A to a talk-only mode.
This mode allo\ys the device to operate as a talker in
an interface system without a controller.
ADDRESS MODE (4W)
Setting the LO bit generates the local 100 (listenonly) message and sets lhe 829M to a listen-only
mode. This mode allows the device to operate as a
listener in an interface system without a controller.
The above bits may also be used by a controller-incharge to set itself up for remote command or data
communication.
IARSI DT I DL I ADS I AD4 I AD3 I AD2 I AD1 I
ADDRESS 0/1 (6W)
The Address Mode Register is used to select one of
the five modes of addressing available on the
8291A. It determines the way in which the 8291A
uses the information in the Address 0 and Address 1
Registers.
The mode of addressing implemented by the 8291 A
may be selected by writing one of the following
bytes to .the Address Mode Register. '
-In Mode 1, the contents of the Address 0 Register
constitute the "Major" talker/listener address while
the Address 1 Register represents the "Minor" talker/listener address. In applications where only one
address is needed, the major talker/listener is used,
and the minor talk~r/listener ,should be disabled.
Loading an address via the Address 0/1 Register
into Address Registers 0 and 1 enable~ the major
and minor talker/listener functions respectively.
Register
Contents
10000000
01000000
11000000
00000P01
00000010
0000,0011
-In Mode 2 the 8291A recognizes two sequential
address bytes: a primary followed by, a secondary.
Both address bytes must be received in order to enable the device to talk, or listen. In this manner,
Mode 2 addressing implements the extended talker
and listener functions as defined in IEEE-488.
Mode
Enable talk only' mode (ton)
Em~ble listen only 1J10de (Ion)
The 8291 may talk to itself, ,
Mode 1, (Primary-Primary) "
Mode 2 (Primary-Secondary)
Mode, 3 (Primary/APT-Primary/ APT)
The Address Status Register contains information
used by tl1emicroprocessor t9 handle its own addressing. This information includes status bits that
monitor the address state of each talker/listener,
",ton" and, "Ion" .flags which indicate the talk and
listen only states, and an EOI bit which, when set,
signifies that the END message came with the last
data byte. LPAS anc! TRAS in,dicate that the listener
3-12
inter
8291A
or talker primary address has been received. The
microprocessor can use these bits when the secondary address is passed through to determine
whether the 8291 A is addressed to talk or listen.
The LA (listener addressed) bit will be set when the
8219A is in LACS (Listener Active State) or in LADS
(Listener Addressed State). Similarly, the TA (Talker
Addressed bit) will be set to indicate TACS or TAOS,
but also to indicate SPAS (Serial Poll Active State).
The MJMN bit is used to determine whether the information in the other bits applies to the Major or
Minor talker/listener. It is set to "1" when the Minor
talker/listener is addressed. It should be noted that
only one talker/listener may be active at anyone
time. Thus, the MJMN bit will indicate which, if either, of the talker/listeners is addressed or active.
Mode 3, where secondary addresses are passed
through, must the processor intervene in the addressing sequence.
The Address 0 Register contains a copy of bit 7 of
the Interrupt Status 2 Register (INT). This is to be
used when polling for interrupts. Software should
poll register 6 checking for INT (bit 7) to be set.
When INT is set, the Interrupt Status Register should
be read to determine which interrupt was received.
Command Pass Through Register
ICPT71 CPT61 CPTsl CPT41 CPT31 CPT21 CPT11 CPTol
COMMAND PASS THROUGH (SR)
The Address 0/1 Register is used for specifying the
device's addresses according to the format selected
in the Address Mode Register. Five bit addresses
may be loaded into the Address 0 and Address 1
Registers by writing into the Address 0/1 Register.
The ARS bit is used to select which of these registers the other seven bits will be loaded into. The DT
and DL bits may be used to disable the talker or
listener function at the address signified by the other
five bits. When Mode 1 addressing is used and only
one primary address is desired, both the talker and
the listener should be disabled at the Minor address.
The Command Pass Through Register is used to
transfer undefined 8-bit remote message codes from
the GPIB to the microprocessor. When the CPT feature is enabled (bit BO in Auxiliary Register B), any
message not decoded by the 8291A becomes an
undefined command. When Mode 3 addressing is
used secondary addresses are also passed through
the CPT Register. In either case, the 8291 A will
hold-off the handshake until the microprocessor
reads this register and issues the VSCMD auxiliary
command.
As an example of how the Address 0/1 Register
might be used, consider an example where two primary addresses are needed in the device. The Major
primary address will be selectable only as a talker
and the Minor primary address will be selectable
only as a listener~ This configuration of the 8291 A is
formed by the following sequence of writes by the
microprocessor.
CS RD WR
Date
RS2-RSo
0
1
0
00000001
100
2. Load major address
into Address 0 Register
with listener function
disabled.
0
1
0
001AAAAA
110
3. Load"minor address
into Address 1 Register
with talker functiofl
disabled.
0
t
0
110BBBBB
110
Operation
1. Select addressing
Mode 1
The CPT and APT interrupts flag the availability of
undefined commands and secondary addresses in
the CPT Register. The details of these interrupts are
explained in the section on Interrupt Registers.
An added feature of the 8291A is its ability to handle
undefined secondary' cOlT)mands following undefined primaries. Thus, the number of available commands for future IEEE-488 definition is increased;
one undefined primary command followed by a sequence of as many as 32 secondary commands can
be processed. The IEEE-488 Standard does not permit users to define their own commands, but upgrades, of the stand,ard are thus provided for.
The recommended use of the 8291 A's undefined
command capabilities is for a controller-configured
Parallel Poll. The PPC message is an undefined primary command typically followed by PPE, and undefined secondary command. For details on this procedure, refer to the section on Parallel Poll Protocol.
At this point, the addresses 'AAAAA and BBBBB are
stored in the Address 0 and Address 1 Registers
respectively, and are available to be read by tHe microprocessor. Thus, it is not necessary to store any
address information elsewhere. Also, with the information stored in the Address 0 and Address 1 Registers, processor intervention is not required to
recognize addressing by the controller. Only in
Auxiliary Mode Register
§NT2IcNT1IcNTOlcOM4IcoM3IcoM~COM1IcOMq
AUX MODE (SW)
CNTO-2:CONTROL BITS
COMO-4:COMMAND BITS
3-13
inter
8291A
The 8291A is designed to power up in certain states
as specified in the IEEE-488 state diagrams. Thus,
the following states' are in effect in the power up
state: SIDS, AIDS, TIDS,LlDS, NPRS, LOCS, and
PPIS.
The. Auxiliary Mode Register contains. 'a three-bit
contrcl field and a .five-bit command field. It is used
for several purposes on the 8291A:
1. To load "hidden" auxiliary registers on the 8291 A.
2. To issue .commands from the microprocessor to
the 8291A.
The "0000" pon is an immediate execute command
(a pon pulse). It is also used to release the "initialize" state generated by either an external reset
pulse or the "0010" Chip Reset command.
3. To preset an internal counter used to generate
T1, delay in the Source Handshake function, as
defined in IEEE-488.
Table 5 summarizes how these tasks are performed
with the Auxiliary Mode Register. Note that the three
control bits determine how the five command bits
are interpreted.
TableS
0010-Chip Reset (Initialize): This command has the
same effect as a pulse applied to the Reset pin. (Refer to the section on Reset Procedure.)
0011-Finish Handshake: This command finishes a
handshake that was stopped because of a holdoff
on RFD. (Refer to Auxiliary Register A.)
Code
pontrol Command
Bits
Bits
000
001
Command
ccce
OCCCC Execute auxiliary command
ODDDD Preset internal counter to'
match external clock
frequency of DDDD MHz
(DDDD binary representation
. of 1to 8 MHz)
100
DDDDD Write DDDDD into
auxiliary register A
101
DDDDD Write DDDDD into
auxiliary register B
011
0100-Trigger: A "Group Execute Trigger" is forced
by this command. It has the same effect as a GET
command issued by the controller-in-charge of the
GPIB, but does not cause a GET interrupt.
0101, 1101-Clear/Set rtl: These commands correspond to the local rtl message as defined by the
IEEE-488. The 8291A will go into local mode when a
Set rtl Auxiliary Command is received if local lockout
is not in effect. The 8291A will exit local mode after
receiving a Clear rtl Auxiliary Command if the 8291A
is addressed to listen.
0110-5end EOI: The EOIline of the 8291A may be
asserted with this command. The command causes
EOI togo true with the next byte transmitted. The
EOI line is then cleared upon completion of the
handshake, for that byte.
USP3P2P1 Enable/disable parallel
poll either in response to remote
messages (PPC followed by
PPE or PPD) or as a local
Ipe message ..(Enable if U = 0,
disable if U = .1.)
0111, 1111-Non ValidlValid Secondary Address or
Command (VSCMD): This command informs the
8291A that the secondary address received by the
microprocessor was valid or invalid (0111 = invalid,
1111 = valid). If Mode 3 addressing is used, the
processor must field each extended address and respond to it, or the GPIB will hang up. Note that the
COM3 bit is the invalid/valid flag.
AUXILIARY COMMAND$
Auxiliary commands are executed by the 8291 A
whenever OOOOCCCC is written, into the Auxiliary
Mode Registe.f, where CCCC is the 4-bit command
. ,
.
code.
The valid (1111) command is also used to tell the
8291 A to continue from the command-pass-throughstate, or from RFD holdoff on GET, SDC or DCL.
OOOo..-:-lmmediate Exe,cute pon: This cOmmand resets the 8291A to a power upstate (local pon mes.
sage as defined in IEEE-488).
1000-pon: This command puts the 8291A into the
pon (power on) state and holds it there. It is similar
to a Chip Reset except none of the Auxiliary Mode
Registers are cleared. In this state, the 8291A does
not partioipate in any bus activity. An Immediate Execute pon releases the 8291 A from the pon state
and permits the device to participate in the bus activity again.
The following conditions, constitute the power up
state:
1. All talkers and listeners are disabled.
2. No illterrupt stat!Js bits are set.
3-14
inter
8291A
Thus, the shortest T1 is aChieved by setting NF = 1
using an 8 MHz clock with a 50% duty cycle clock
(tSYNC<63 ns):
0001, 1001-Parallel Poll Flag (local "ist" message):
This command sets (1001) or clears (0001) the parallel poll flag. A "1" is sent over the assigned data
line (PRR = Parallel Poll Response true) only if the
parallel poll flag matches the sense bit from the Ipe
local message (or indirectly from the PPE message).
For a more complete description of the Parallel Poll
features and procedures refer to the section on Parallel Poll Protocol.
1
T1(HS) =
=
125 ns max.
AUXILIARY REGISTER A
Auxiliary Register A is a "hidden" 5-bit register
which is used to enable some of the 8291 A features.
Whenever a1 00 A4A3A2A1AO byte is written into the
Auxiliary Register, it is loaded with the data
A4A3A2A1AO' Setting the respective bits to "1" enables the following features.
INTERNAL COUNTER
The internal counter determines the delay time allowed for the setting of data on the DIO lines. This
delay time is defined as T1 in IEEE-488 and appears
in the Source Handshake state diagram between the
SDYS and STRS. As such, DAV is asserted T 1 after
the DIO lines are driven. Consequently , T 1 is a major factor in determining the data transfer rate of the
8291A over the GPIB (T1 = TWRDV2-TWRD15).
Ao-RFD Holdoff on all Data: If the 8291 A is listening, RFD will not be sent true until the "finish handshake" auxiliary command is issued by the microprocessor. The holdoff will be in effect for each data
byte.
When open-collector transceivers are used for connection to the GPIB, T1 is defined by IEEE-488 to be
2 !ks. By writing 0010DDDD into the Auxiliary Mode
Register, the counter is preset to match a fc MHz
clock input, where DDDD is the binary representation of NF [1 ~NF~8, NF = (DDDD)21. When NF =
fc, a 2 !ks T 1 delay will be generated before each
DAV asserted.
A1-RFD Holdoff on End: This feature enables the
holdoffon EOI or EOS (if enabled). However, no
hold-off will be in effect on any other data bytes.
Az-End on EOS Received: Whenever the byte in
the Data In Register matches the byte in the EOS
Register, the END interrupt bit will be set in the Interrupt Status 1 Register.
Aa-Output 'EOI on EOS Sent: Any occurrence of
data in the Data Out Register matching the EOS
Register causes the EOI line to be sent true along
with the data.
tSYNC is a synchronization error, greater than zero
and smaller than the larger of T clock high and T
clock low. (For a 50% duty cycle clock, tSYNC is less
than half the clock cycle).
A4-EOS Binary Compare: Setting this bit causes
the EOS Register to function as a full 8-bit word.
When it is not set, the EOS Register is a 7 -bit word
(for ASCII characters).
If it is necessary that T 1 be different from 2 !ks, NF
may be set to a value other than fc. In this manner,
data transfer rates may be programmed for a given
system. In small systems, for example, where transfer rates exceeding GPIB specifications are required, one may set NF
045
TEST POINTS
::x=
i
DEVICE
UNDER
<
TEST
Cl
= 1S0pF
205248-10
A.G. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". ,Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".
205248-11
GPIB TIMINGS(1)
Symbol
TEOT13(2)
TEOD16
Parameter
Test Conditions
Max
Units
EOI,J.. toTR1 t
135
ns
PPSS, ATN
= 0.45V
= 0.45V
= 0.45V
EOI ,J.. to DIO Valid
155
ns
PPSS, ATN
TEOT12
EOI t toTR1,J..
155
ns
PPSS, ATN
TATND4
ATN,J.. to NDAC,J..
155
ns
TACS, AIDS
TATI14
ATN,J.. toTR1,J..
155
ns
TACS, AIDS
TATI24
ATN,J.. to TR2,J..
155
ns
TACS, AIDS
TDVND3-C
DAV,J.. to NDAC t
650
ns
AH,CACS
TNDDV1
NDAC t to DAV t
350
ns
SH,STRS
TNRDR1
NRFD t to DREQ t
400
ns
SH
= 2.4V
TDVDR3
DAV,J.. to DREQ t
600
ns
AH, LACS, ATN
TDVND2-C
DAV t to NDAC,J..
350
ns
AH, LACS
TDVNR1-C
DAV t to NRFD t
350
ns
AH, LACS, rdy
TRDNR3
RD,J.. toNRFDt
500
ns
AH, LACS
TWRD15
WR t to DIO Valid
280
ns
SH, TACS, RS
TWRE05
WR t to EOI Valid
350
ns
SH, TACS
TWRDV2
WR t toDAV,J..
+
ns
High Speed Transfers Enabled,
NF = fC, tSYNC = %-fc
830
tSYNC
= True
= O.4V
NOTES:
1. All GPIB timings are at the pins of the 8291A
2. The last number in the symbol for any GPIB timing parameter is chosen according to the transition directions of the
reference signals. The following table describes the numbering scheme.
ito
i
1
ito
-l.
2
-l.
-l.
to
t
3
to
-l.
4
i to VALID
5
-l. to VALID
6
3-25
inter
8291A
APPENDIX A
MODIFIED STATE DIAGRAMS
Figure A-1 presents the interface function state diagrams. It is derived from IEEE Std. state diagrams,
with the following changes:
A. The 8291 A supports the complete set of IEEE488 interface functions except for the controller.
These include: SH1, AH1, T5, TE5, L3, LE3, SR1,
RL1, PP1, DC1, DT1, and co.
Consider the condition when the Not-Ready-ForData signal (pin 37) is active. Intel indicates this active low signal with the symbol NRFD (VOUT S VOL
for AH; VIN s VIL for SH). The IEEE-488-1978 Standard, in its state diagrams, indicates the active state
of this Signal (True condition) with NRFD.
D. All remote multiline messages decoded are conditioned by ACDS. The multiplication by ACDS is
not drawn to simplify the diagrams.
B. Addressing modes included in T, L state diagrams.
E. The symbol
x-G)
Note that in Mode 3, MSA, eSA are generated only
after secondary address validity check by the microprocessor (APT interrupt).
205248-12
C. In these modified state diagrams, the IEEE-4881978 convention of negative (lOW true) logic is
followed. This should not be confused with the
Intel pin- and signal-naming convention based on
positive logic. Thus, while the state diagrams below carry low true logic,' the signals described
elsewhere in this data sheet are consistent with
Intel notation and are based on positive logic.
indicates:
1. When event X occurs, the function returns to
state S.
2. X overrides any other transition condition in the
function.
Statement 2 simplifies the diagram, avoiding the explicit use of X to condition all transitions from S to
other states.
Convention
Level
Logic
IEEE-488
Intel
0
T
F
T
F
T
F
DAV
DAV
NDAC
NDAC
NRFD
NRFD
DAV
DAV
NDAC
NDAC
NRFD
NRFD
1
0
1
0
1
r---'-l
I
I
IL
SH
I
I
I
_ _ _ _ -l
Fl
pon
ATN + F1
(WITHIN t2i
F1 =TACS
+
DAV
SPAS
, 205248-13
Figure A·1. 8291A State Diagrams
3-26
inter
8291A
NDAC
NRFD
I
L _ ~
F2
p o n - - -__'"I
__
J
'THIS TRANSITION WILL NEVER
OCCUR UNDER NORMAL OPERATION
tTOELAV IS ABOUT 300 NS
F2 (WITHIN t2)
FOR DEBOUNCING DAV
F3 + T3'·
ATN
DAV
BI
END IF (EO I + EOSI RECEIVED
NRFD
F2 ~ ATN + LACS + LADS
F3 ~ ATN + rdy
T3' ~ T3 • CPT. APT
205248-"14
r - - - -...,
I
I
I
TEl
I
I
L ____
oon---__""
J
STB AND Ras AVAILABLE
TO SH
IFC
(WITHIN 141
EOI IF DAB
F4 ~ OTA + (OSA. TPAS
MODE 1 + MLA. MODE 1
+
= EOS
MSA. LPAS) •
205248-15
Figure A-1, 8291A State Diagrams (Continued)
3-27
8291A
MTA
pon---"
PCG'MTA
SPE
pon - - - _ - I
SPD
IFC
(WITHIN 14)
205248-16
r----- 1
RQs IN STB
I
I
SR 0
I
L ____
I
I
I
J
pon---_-I
ROS IN STB
205248-17
Figure A-1. 8291A State Diagrams (Continued)
3-28
intJ
8291A
r
-----1
I
I
I
LEI
I
L ____
I
J
pon---_-f
pon---_..
205248-18
r-----'
I
I
F5· rti
I
I
IL _ _ _ _ JI
RL
pon---_..
F5 = (MLA • MODE 1
+
205248-19
LPAS. MSA • MODE 1)
Figure A·1. 8291A State Diagrams (Continued)
3-29
inter
8291A
r-----,
I
I
,I
PP2
I
I
I
L ____ J
pon---"
lOY·
ii5Y
(WITHIN IS}
(WITHIN IS}
PPRN
=RESPONSE ~--f
205248-20
'lOY = ATN • EOI
r----'
I
I
I DC
I
IL ____ JI
Fe = OCL
205248-21
+ SOC. LADS
r----'
I
I
I OT
I
I ____ .JI
L
205248-22
Figure A-1. 8291A State Diagrams (Continued)
3·30
intJ
8291A
APPENDIX B
Table B·1. IEEE 488 Time Values
Time Value
Identlfler(1)
Function (Applies to)
Description
T6
T7
SH
LC, re, SH, AH, T, L
AH
T, TE, L, LE, C, CE
PP
C
C
T8
Te
C
C
Settling Time for Multiline Messages
Response to ATN
Interface Message Accept Time(3)
Response to IFC or REN False
Response to ATN + EOI
Parallel Poll Execution Time
Controller Delay to Allow Current Talker
to see ATN Message
Length of IFC or REN False
Delay for EOI(5)
T1
t2
T3
4
ts
Value
:?: 2 JA-s(2)
~
200 ns
> 0(4)
< 100 JA-s
~
200 ns
:?: 2 JA-s
~
500 ns
> 100 JA-s
~
1.5 JA-s(6)
NOTES:
1. Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values
specified by an upper case T indicate the minimum time that a function must remain in a state before exiting.
2. If three-state drivers are used on the 00, DAV, and
lines, T1 may be:
1. ~ 1100 ns.
2. Or ~ 700 ns if it is known that within the controller ATN is driven by a three-state driver.
3. Or ~ 500 ns for a" subsequent bytes following the first sent after each false transition of ATN (the first byte must be sent
in accordance with (1) or (2).
4. Or ~ 350 ns ·for a" subsequent bytes following the first sent after each false transition of ATN under conditions specified
In Section 5.2.3 and warning note. See IEEE Standard 488.
3. Time required for interface functions to accept, not necessarily respond to interface messages.
4. Implementation de~dent.
5. Delay required for
NDAC, and iiiRFD Signal lines to indicate valid states.
6. ~ 600 ns for three-state drivers.
ro
ro,
3-31
8291A
APPENDIX .C
THE THREE-WIRE HANDSHAKE
TWRDIS
I
I
VALID
~T1.
NOTVALID
VALID
I+-T1.
~TWRDV~
!--TNDDV1_I4--TDVNR1--oo
-t\.
t:=:L
I
""L
-~
~f-TADNR3_
IIRFD
~~
~
!-TDVND3_
~r
,
1\
F9
X
DREQ(SH)
!4-TDVDR3
DREQ(AH)
-:lL
liD
- ....
205248-23
Figure C-1. 3-Wlre Handshake Timing at 8291A
3-32
intJ
8292
GPIB CONTROLLER
• Complete IEEE Standard 488 Controller
Function
• Complete Implementation of Transfer
Control Protocol
•
• Synchronous Control Seizure Prevents
the Destruction of Any Data
Transmission in Progress
Interface Clear (IFC) Sending Capability
Allows Seizure of Bus Control and/or
Initialization of the Bus
• Responds to Service Requests (SRQ)
• Sends Remote Enable (REN), Allowing
Instruments to Switch to Remote
Control
• Connects with the 8291 to Form a
Complete IEEE Standard 488 Interface
Talker/Listener/Controller
The 8292 GPIB Controller is a microprocessor-controlled chip designed to function with the 8291 GPIB Talker/Listener to implement the full IEEE Standard 488 controller function, including transfer control protocol.
The 8292 is a preprogrammed Intel® 8041 A.
MICROPROCESSOR SYSTEM BUS
IFCL
Xl
r--- --... OACK
r-:=:'+I
II
OMA
OREO
I
I
CONTROLLER
(OPTIONAL)
8291
GPIB
TALKERI
LISTENER
I
I
L ______ I
8292
GPIB
CONTROLLER
X2
REN
RESET
OAV
Vee
IBFI
CS
TIR 2
TiAl
VCC
COUNT
OBFI
GND
EOI
IIli
Ao
SPI
WR
CIC
SYNe
NC
TCI
Do
ATNO
01
NC
02
CLTH
03
Vee
8293
04
NC
BUS
TRANSCEIVERS
05
SYC
De
IFC
07
ATNI
VSS
SRO
205250-2
GENERAL PURPOSE INTERFACE BUS
Figure 2. Pin Configuration
205250-1
Figure 1.8291,8292 Block Diagram
3-33
November 1986
Order Number: 20525(}O002
inter
8292
Table 1. Pin Description
Pin
Number
Type
IFCL
1
I
IFC RECEIVED (LATCHED): The 8292 monitors the IFC Line (when not
system controller) through this pin.
X1, X2
2,3
I
CRYSTAL INPUTS: Inputs for a crystal, LC or an external timing Signal to
determine the internal oscillator frequency.
.
Symbol
Name and Function
RESET
4
I
RESET: Used to initialize the chip to a known state during power on.
es
6
I
CHIP SELECT INPUT: Used to select the 8292 from other devices on the
common data bus.
Rt5
8
I
READ ENABLE: Allows the master CPU to read from the 8292.
Ao
9
I
ADDRESS LINE: Used to select between the data bus and the status
register during read operations and to distinguish between data and
commands written into the 8292 during write operations.
WFi
10
I
WRITE ENABLE: Allows the master CPU to write to the 8292.
SYNC
11
0
SYNC: 8041 A instruction cycle synchronization signal; it is an output
clock with a frequency of XTAL + 15.
00- 0 7
12-19
liD
DATA: 8 bidirectional lines used for communication between the central
processor and the 8292's data bus buffers and status register.
Vss
7,20
P.S.
GROUND: Circuit ground potential.
SRQ
21
I
SERVICE ~EQUEST: One of the IEEE control lines. Sampled by the
- 8292 when it is controller in charge. If true, SPI interrupt to the master will
be generated.
ATNI
22
I
ATTENTION IN: Used by the 8292 to monitor the GPIBATN control line.
If is used during the transfer control procedure.
iFC
23
liD
INTERFACE CLEAR: One of the GPIB management lines, as defined by
IEEE Std. 488-1978, places all devices in a known quiescent state.
SYC
24
I
SYSTEM CONTROLLER: Monitors the system controller switch.
CLEAR LATCH: Used to clear the iFCR latch after being recognized by
the 8292. Usually low (except after hardware Reset), it will be pulsed high
when IFCR is recognized by the 8292.
CLTH
27
0
ATNO
29
0
5,26,40
P.S.
COUNT
39
I
EVENT COUNT: When enabled by the proper command the internal
counter will count external events through this pin. High to low transition
will increment the internal counter by one. The pin is sampled once per
three internal instruction cycles (7.5 ,...sec sample period when using 5
MHz XTAL). It can be used for byte counting when connected to NOAC,
or for block counting when connected to the EOL
REN
38
0
REMOTE ENABLE: The Remote Enable bus signal selects remote or
local control of the device on the bus. A GPIB bus signal selects remote
or local control of the device on the bus. A GPIB bus management line,
as defined by IEEE Std. 488-1978.
Vee
ATTENTION OUT: Controls the ATN control line of the bus through
. external logic for tcs and tca procedures. (ATN is a GPIB control line, as
defined by IEEE Std. 488-1978.)
VOLTAGE: +5Vsupplyinput ±10%.
3-34
8292
Table 1. Pin Description (Continued)
Symbol
Pin
No.
Type
DAV
37
I/O
DATA VALID: Used during parallel poll to force the 8291 to accept the
parallel poll status bit. It is also used during the tcs procedure.
IBFI
36
0
INPUT BUFFER NOT FULL: Used to interrupt the central processor
while the input buffer of the 8292 is empty. This feature is enabled and
disabled by the interrupt mask register.
OBFI
36
0
OUTPUT BUFFER FULL: Used as an interrupt to the central processor
while the output buffer of the 8292 is full. The feature can be enabled and
disabled by the interrupt mask register.
E012
34
I/O
END OR IDENTIFY: One of the GPIB management lines, as defined by
IEEE Std. 488·1978. Used with ATN as Identify Message during parallel
poll.
SPI
33
0
SPECIAL INTERRUPT: Used as an interrupt on events not initiated by
the central processor.
TCI
32
0
TASK COMPLETE INTERRUPT: Interrupt to the control processor used
to indicate that the task requested was completed by the 8292 and the
information requested is ready in the data bus buffer.
CIC
31
0
CONTROLLER IN CHARGE: Controls the SIR input of the SRQ bus
transceiver. It can also be used to indicate that the 8292 is in charge of
the GPIB bus.
Name and Function
FUNCTIONAL DESCRIPTION
GPIB
The 8292 is an Intel 8041A which has been programmed as a GPIB Controller Interface element. It
is used with the 8291 GPIB Talker/Listener and two
8293 GPIB Transceivers to form a complete IEEE488 Bus Interface for a microprocessor. The electrical interface is performed by the transceivers, data
transfer is done by the talker/listener, and control of
the bus is done by the 8292. Figure 3 is a typical
controller interface using Intel's GPIB peripherals.
TO
PROCESSOR
BUS
TO
PROCESSOR
BUS
GPIB
205250-3
Figure 3. Talker/Listener/Controller
Configuration
3-35
intJ
8292
The internal RAM in the 8041 A is used as a special
purpose register bank for the 8292. Most of these
registers (except for the interrupt flag) can be accessed through commands to the 8292. Table 2
identifies the registers used by the 8292 and how
they are accessed.
Event Counter Interrupt. The requested number of blocks of data byte has been transferred. The EV interrupt flag is cleared by the
lACK command.
SRQ Service Request. Notified the 8292 that a
service request (SRO) message has been received. It is cleared by the lACK command.
Interrupt Status Register
ERR Error occurred. The type of error can be determined by reading the error status register.
This interrupt flag is cleared by the lACK command.
SYC System Controller Switch Change. Notifies
the processor that the state of the system
controller switch has changed. The actual
state is contained in the GPIB Status Register. This flag is cleared by the lACK command.
EV
I SYC I ERR I SRO I EV I X IIFCR IISF I OSF I
Do
The 8292 can be configured to interrupt the microprocessor on one of several conditions. Upon receipt of the interrupt the microprocessor must read
the 8292 interrupt status register to determine which
event caused the interrupt, and then the appropriate
subroutine can be performed. The interrupt status
register is read with Ao high. With the exception of
OBF and ISF, these interrupts are enabled or disabled by the SPI interrupt mask. OSF and IBF have
their own bits in the interrupt mask (OBFI and IBFI).
OBF Output Buffer Full. A byte is waiting to be read
by the microprocessor. This flag is cleared
when the output data bus buffer is read.
IBF Input Buffer FUll. The byte previously written
by the microprocessor has not been read yet
by the 8292. If another byte is written to the
8292 before this flag clears, data will be lost.
IBF is cleared when the 8292 reads the data
byte.
Interrupt Mask Register
j
1 I SPI I TCI I SYC I OBFI I IBFI I 0
I SRO I
Do
The Interrupt Mask Register is used to enable features and to mask the SPI and TCI interrupts. The
flags in the Interrupt Status Register will be active
even when masked out. The Interrupt Mask Register
is written when Ao is low and reset by the RINM
command. When the register is read, 01 and 07 are
undefined. An interrupt is enabled by setting the corresponding register bit.
SRQ Enable interrupts on SRO received.
IBFI Enable interrupts on input buffer empty.
OBFI Enable interrupts on output buffer full.
IFCR Interface Clear Received. The GPIB system
controller has set IFC. The 8292 has become
idle and is no longer is charge of the bus. The
flag is cleared when the lACK command is
issued.
Table 2. 8292 Registers
READ FROM 8292
WRITE TO 8292
INTERRUPT STATUS
I SYC I ERR I SRO I
07
I
x
EV
I
X
IIFCR I IBF I OBF 11
ERROR FLAG
I
x
I USER I
x
I
x
Ao
INTERRUPT MASK
I
1
DO
I SPI I TCI I SYC I OBFI I
07
ITOUT3ITOUT2ITOUT1Io.
x
I
x
I
0
I USER I
X
0
I SRO I 0
1
I
1
I
0
I
0
Do
I TOUT3I TOUT2ITOUT1I 0
COMMAND FIELD
I SYCS I IFC I REN I SRO 10'
1
GPIB (BUS) STATUS
I REN I OAV I EOI I
I
ERROR MASK
o
CONTROLLER STATUS
I CSBS I CA
Ao
iBR
lop
I
C
I
C
I
C
I
C
Jl
EVENT COUNTER
I SYC I IFC I ANTI I SRO 10'
o
I
0
I
0
EVENT COUNTER STATUS
I
0
I
0
I
0
0
0
10'
0
0
o
10'
TIME OUT
J....I_0--,-1_0--<.1_0-l1_0.....J-1_0--1..1_0---0.1_0_11---0--'10. I
0
I
0
I
0
0
I
0
TIME OUT STATUS
I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 10'
'---"'---'-----'---'---'---'----'----'
NOTE: These registers are accessed by a special utility
command, see page 7.
3-36
inter
SYC
8292
Enable interrupts on a change in the system
controller switch.
TCI
Enable interrupts on the task completed.
SPI
Enable interrupts on special events.
on pin 39 of the 8292 (COUNT). It can be connected
to EOI or NDAC to count blocks or bytes respectively during standby state. A count of zero equals 256.
This register cannot be read, and is written using the
WEVC command.
NOTE:
The event counter is enabled by the GSEC command, the error interrupt is enabled by the error
mask register, and IFC cannot be masked (it will always cause an interrupt).
Controller Status Register
ICSBSI CA I X
I X
Isycsi IFC I REN I SRO
Event Counter Status Register
I
Do
The Controller Status Register is used to determine
the status of the controller function. This register is
accessed by the RCST command.
SRQ Service Request line active (CSRS).
REN Sending Remote Enable.
IFC
Time Out Register
The Time Out Register is used to store the time
used for the time out error function. See the individual timeouts (TOUT1, 2, 3) to determine the units of
this counter. This Time Out Register cannot be read,
and it is written with the WTOUT command.
Sending or receiving interface clear.
SYCS System Controller Switch Status (SACS).
Controller Active (CACS + CAWS
CSWS).
CSBS Controller Stand-by State (CSBS, CA)
(O,O)-Controller Idle.
CA
This register contains the current value in the event
counter. The event counter counts back from the
initial value stored in the Event Counter Register to
zero and then generates an Event Counter Interrupt.
This register cannot be written and can be read using a REVC command.
+
Time Out Status Register
Do
GPIB Bus Status Register
I REN I DAV I EOI I X I SYC IIFC I ATNI I SRO
I
Do
This register contains GPIB bus status information. It
can be used by the microprocessor to monitor and
manage the bus. The GPIB Bus Register can be
read using the RBST command.
Each of these status bits reflect the current status of
the corresponding pin on the 8292.
This register contains the current value in the time
out counter. The time out counter decrements from
the original value stored in the Time Out Register.
When zero is reached, the appropriate error interrupt
is generated. If the register is read while none of the
time out functions are active, the register will contain
the last value reached the last time a function was
active. The Time Out Status Register cannot be written, and it is read with RTOUT command.
Error Flag Register
SRQ Service Request
ATNI Attention In
IFC
Interface Clear
SYC
System Controller Switch
EOI
End or Identify
Four errors are flagged by the 8292 with a bit in the
Error Flag Register. Each of these errors can be
masked by the Error Mask Register. The Error Flag
Register cannot be written, and it is read by the
lACK command when the error flag in the Interrupt
Status Register is set.
TOUT1 Time Out Error 1 occurs when the current
controller has not stopped sending ATN after receiving the TCT message for the time
period specified by the Time Out Register.
Each count in the Time Out Register is at
least 1800 tCY. After flagging the error, the
8292 will remain in a loop trying to take control until the current controller stops send-
DAV Data Valid
REN Remote Enable
Event Counter Register
The Event Counter Register contains the initial value
for the event counter. The counter can count pulses
3-37
intJ
8292
ing ATN or a new command is written by
the microprocessor. If a new command is
_written, the 8292 will return to the loop after
executing it.
TOUT2 Time Out Error 2 occurs when the transmission between the addressed talker and listener has not started for the time period
specified by the Time Out Register. Each
count in the Time Out Register is at least 45
tCY. This feature is only enabled when the
controller is in the CSBS state.
TOUT3 Time Out Error 3 occurs when the handshake signals are stuck and the 8292 is not
succeeding in taking control synchronously
for the time period specified by the Time
Out Register. Each count in the Time Out
Register is at least 1800 tCY. The 8292 will
continue checking ATNI until it becomes
true or a new commnand is received. After
performing the new command, the 8292 will
return to the ATNI checking loop.
USER User error occurs when request to assert
IFC or REN was received and the 8292 was
not the system controller.
Fo-SPCNI-Stop Counter Interrupts
This command disables the internal counter interrupt so that the 8292 will stop interrupting the master
on event counter underflows. However, the counter
will continue counting and its contents can still be
used.
F1-GIDL-Go To Idle
This command is used during the transfer of control
procedure while transferring control to another controller. The 8292 will respond to this command ~
if it is in the active state. ATNO will go high, and CIG
will be high so that this 8292 will no longer be driving
the ATN line on the GPIB interface bus. TCI will be
set upon completion.
F2-RST-Reset
This command has the same effect as asserting the
external reset on the 8292. For details, refer to the
reset procedure described later.
F3-RSTI-Reset Interrupts
This command resets any pending interrupts arid
clears the error flags. The 8292 will not return to any
loop it was in (such as from the time out interrupts).
Error Mask Register
F4-GSEC-Go To Standby, Enable Counting
The Error Mask Register is used to mask the interrupt from a particular type of error. Each type of error
interrupt is enabled by setting the corresponding bit
in the Error Mask Register. This register can be read
with the RERM command and written with Ao low.
The function causes ATNO to go high and the counter will be enabled. If the 8292 was not the active
controller, this command will exit immediately. If the
8292 is the active controller, the counter will be
loaded with the value stored in the Event Counter
Register, and the internal interrupt will be enabled so
that when the counter reaches zero, the SPI interrupt will be generated. SPI will be generated every
256 counts thereafter until the controller exits the
standby state or the SPCNI command is written. An
initial count of 256 (zero in the Event Counter Register) will be used if the WEVC command is not executed. If the data transmission does not start, a
TOUT2 error will be generated.
Command Register
I
1
I
1
I
1
I OP
C
C
C
C
Do
Commands are performed by the 8292 whenever a
byte is written with Ao high. There are two categories
of commands distinguished by the OP bit (bit 4). The
first category is the operation command (OP = 1).
These commands initiate some' action on the interface bus. The second category is the utility command (OP = 0). These commands are used to aid
the communication between the processor and the
8292.
F5-EXPP-Execute Parallel Poll
This command initiates a parallel poll by asserting'
EOI wh~n ATN is already active. TCI will be set at
the end of the command. The 8291 should be previously configured as a listener. Upon detection of
DAV true, the 8291 enters ACDS and latches the
parallel poll response (PPR) byte into its data in register. The master will be interrupted by the 8291 BI
interrupt when the PPA byte is available. No interrupts except the IBFI will be generated by the 8292.
The 8292 will respond to this command only when it
is the active controller.
OPERATION COMMANDS
Operation commands initiate some action on the
GPIB interface bus. It is using these commands that
the control functions such as polling, taking and
passing control, and system controller functions are
performed.
3-38
intJ
8292
ing the controller function for being in the CSBS
(else it will exit immediately), ATFR5 will go low, and
a TCI interrupt will be generated.
F6-GTSB-Go To Standby
If the 8292 is the active controller, ~ will go high
then TCI will be generated. If the data transmission
does not start, a TOUT2 error will be generated.
FD-TCSY-Take Control Synchronously
There are two different procedures used to transfer
the 8292 from CSBS to CACS depending on the
state of the 8291 in the system. If the 8291 is in
"continuous AH cycling" mode (Aux. Reg. AO = A 1
= 1), then the following procedures should be fol·
lowed:
1) The master microprocessor stops the continuous
AH cycling mode in the 8291;
2) The master reads the 8291 Interrupt Status 1
Register;
3) If the END bit is set, the master sends the TCSY
command to the 8292;
4) If the END bit was not set, the master reads the
8291 Data In Register and then waits for another
BI interrupt from the 8291. When it occurs, the
master sends the 8292 the TCSY command.
F7-SLOC-Set Local Mode
If the 8292 is the system controller, then REN will be
asserted false and TCI will be set true. If it is not the
system controller, the User Error bit will be set in the
Error Flag Register.
F8-SREM-8et Interface To Remote Control
This command will set REN true and TCI true if this
8292 is the system controller. If not, the User Error
bit will be set in the Error Flag Register.
F9-ABORT-Abort All Operation, Clear
Interface
This command will cause IFC to be asserted true for
at least 100 ,...sec if this 8292 is the syStem control·
ler. If it is in CIDS, it will take control over the bus
(see the TCNTR command).
If the 8291 is not in AH cycling mode, then the mas·
ter just waits for a BI interrupt and then sends the
TCSY cOmmand. After the TCSY command has
been issued, the 8292 checks for ~. If ~,
then it exits the routine. Otherwise, it then checks
the DAV bit in the GPIB status. When DAV becomes
false, the 8292 will wait for at least 1.5 ,...sec. (T10)
and then ATNQ will go low. If DAV does not go low,
a TOUT3 error will be generated. If the 8292 suc·
cessfully takes control, it sets TCI true.
FA-TCNTH-Take Control
The transfer of control procedure is coordinated by
the master with the 8291 and 8292. When the master receives a TCT message from the 8291, it should
issue the TCNTR command to the 8292. The follow·
ing events occur to take control:
1) The 8292 checks to see if it is in CIDS, and if not,
it exits.
2) Then ATNl is checked until it becomes high. If the
current controller does not release ATN for the
time specified by the Time Out Register, then a
TOUT1 error is generated. The 8292 will return to
this loop after an error or any command except
the RST and RSTI commands.
3) After the current controller releases ATN, the
8292 will assert ATNO and CiC low.
4) Finally, the TCI interrupt is generated to inform
the maste,r that it is in control of the bus.
This command enables the internal counter inter·
rupt. The counter is enabled by the GSEC com·
mand.
Fe-TCASY-Take Control Asynchronously
E1-WTOUT-Wrlte To Time Out Register
TCAS transfers the 8292 from CSBS to CACS inde·
pendent of the handshake lines. If a bus hangup is
detected (by an error flag), this command will force
the 8292 to take control (asserting ATN) 'even if the
AH function is not in ANRS (Acceptor Not Ready
State). This command should be used very carefully
since it may cause the loss of a data byte. Normally,
control should be taken synchronously. After check·
The byte written to the data bus buffer (with Ao = 0)
following this command will determine the time used
for the time out function. Since this function is implemented in software, this will not be an accurate time
measurement. This feature is enable or disable by
the Error Mask Register. No interrupts except for the
iBA will be generated upon completion.
FE-STCNI-start Counter Interrupts
UTILITY COMMANDS
All these commands are either Read or Write to reg·
isters in the 8292. Note that writing to the Error Mask
Register and the Interrupt Mask Register are done
directly.
3·39
inter
8292
E2-WEVC-Wrlte To Event Counter
The byte written to the data bus buffer (with Ao = 0)
following this command will be loaded into the Event
Counter Register and the Event Counter Status for
byte counting of EOI counting. Only IBFI will indicate
completion of this command.
Interrupt Acknowledge
I SYC I ERR I SRQ I EV
IFCR
Do
Each named bit in an Interrupt Acknowledge (lACK)
corresponds to a flag in the Interrupt Status Register. When the 8292 receives' this command,it will
clear the SPI and the corresponding bits in the Interrupt Status Register. If not all the bits were cleared,
then the SPI will be set true again. If the error'flag·is
not acknowledged by the lACK command, then the
Error Flag Register will be transferred to the data
bus buffer, and a TCI will be generated.
E3-REVC-Read Event Counter Status
This command transfers the contents of the Event
Counter into the data bus buffer. A TCI is generated
when the data is available in the data bus buffer.
E4-RERF-Read Error Flag Register
NOTE:
XXXX1 X11 is an undefined operation or utility command, so no conflict exists between the lACK operation and utility commands.
This command transfers the contents of the Error
Flag Register into the data bus buffer. A TCI is generated when the data is available.
SYSTEM OPERATION
E5-RINM-Read Interrupt Mask Register
This command transfers the contents of the Interrupt Mask Register into the data bus buffer. This register is available to the processor so that it does not
need to store this information elsewhere. A TCI is
generated when the data is available in the data bus
buffer.
Communication between the 8292 and the Master
Processor can be either interrupt based communication or based upon polling the interrupt status register in predetermined intervals.
E6-RCST-Read Controller Status Register
Interrupt Based Communication
This command transfers the contents of the Controller Status Register into the data bus buffer and a TCI
interrupt is generated.
Four different interrupts are available from the 8292:
OBFI Output Buffer Full Interrupt
IBFI Input Buffer Not Full Interrupt
TCI Task Completed Interrupt
SPI Special Interrupt
8292 To Master Processor Interface
E7-RBST-Read GPIB Bus Status Register
This command transfers the contents of the GPIB
Bus Status Register into the data bus buffer, and a
TCI interrupt is generated when the data is available.
Each of the interrupts is enabled or disabled by a bit
in the interrupt mask register. Since OBFI and IBFI
are directly connected to the OBF and IBF flags, the
master can write a new command to the Input data
bus buffer as soon as the previous command has
been read.
E9-RTOUT-Read Time Out Status Register
This command transfers the contents of the Time
Out Status Register into the data bus buffer, and a
TCI interrupt is generated when the data is available.
The TCI interrupt is useful when the master is sending commands to the 8292. The pending TCI will be
cleared with each new command written to the
8292. Commands sent to the 8292 can be divided
into two major groups:
EA-RER!III-Read Error Mask Register
This command transfers the contents of the Error
Mask Register to the data bus buffer so that the
processor does not need to store this information
elsewhere. A tCI interrupt is generated when the
data is available.
1) Commands that require response back from the
8292 to the master, e.g., reading register.
2) Commands that initiate some action or enable
features but do not require response back from
the 8292, e.g., enable data bus buffer interrupts.
3-40
inter
8292
With the first group, the TCI interrupt will be used to
indicate that the required response is ready in the
data bus buffer and the master may continue and
read it. With the second group, the interrupt will be
used to indicate completion of the required task, so
that the master may send new commands.
The SPI should be used when immediate information or special events is required (see the Interrupt
Status Register).
"Polling Status" Based Communication
When interrupt based communication is not desired,
all interrupts can be masked by the interrupt mask
register. The .communication with the 8292 is based
upon sequential poll of the interrupt status register.
By testing the OBF and IBF flags, the data bus buffer status is determined while special events are determined by testing the other bits.
Receiving IFC
The IFC pulse defined by the IEEE-488 standard is
at least 100 fA-sec. In this time, all operation on the
bus should be aborted. Most important, the current
controller (the one that is in charge at that time)
should stop sending ATN or EOL Thus, IFC must
externally gate GIC (controller in charge) and ATNO
to ensure that this occurs.
Reset and Power Up Procedure
After the 8292 has been reset either by the external
reset pin, the device being powered on, or a RST
command, the following sequential events will take
place:
1) All outputs t~e GPIB interface will~ high
(SRO, ATNI, IFC, SYC, CLTH, ATNO, CIC, TCI,
SPI, EOi, OBFI, IBFI, DAV, REV).
,
2) The four interrupt outputs (TCI, SPI, OBFI, IBFI)
and CLTH output will go low.
3) The following registers will be cleared:
Interrrupt Status
Interrupt Mask
Error Flag
Erorr Mask
Time Out
Event Counter (= 256), counter is disabled.
4) If the 8292 is the system controller, and ABORT
command will be executed, the 8292 will become
the controller in charge, and it will enter the CACS
state.
If it is not the system controller, it will remain in
CIDS.
System Configuration
The 8291 and 8292 must be interfaced to an IEEE488 bus meeting a variety of specifications including
drive capability and loading characteristics. To interface the 8291 and the 8292 without the 8293's, several external gates are required, using a configuration similar to that used in Figure 5.
3-41
8292
OPI'
T_1IIt
r--l.!iOi2!I___--.!N~o;TE~I~'_ _ _ _ _,-_.:.:''.:...._ _-{
I
I4-'R;;::IN::-_ _...,
PROCUIOR
INTERRUPT
WIi liD
lUI
I
I
RaT CLK ADD DATA DMA
101
311
ATN
Ie
NDAC
..
ATN
UK
I
iiii
Ie
~----\I
.J..m:K
DATA
rrr'-- rI - - rt-t----t r+-J-I--i rL-+-+-+---I r-
I - -....!·I ....,
1 ...
t - -..I ....
l~ I
1--""'1 CLOCK
I--~RUET
1---1 iii
WR
I---IINT
Ci
I-
..
...-CLTH
--
t.===..}..~DATA
0 1 - - - -..1...
lot-----ICi
.,..
~'
iiii
BPI
Id
Eot
I.
IFC
....
....----1 x,
cis
T
IYC
±
~
RIN
r - - - t EA
-+L
I.
ii
T,
COUNT
T.
iFCL
14.7K
SYSTEM
CONTROLLER
SWITCH
ONlo.-
...
'---_
IRQ
.,..
205250-4
NOTES:
1. Connect to NDAC for byte count or to EOI for block count.
2. Gate ensures open collector operation during parallel poll.
Figure 4. 8291 and 8292 System Configuration
3·42
intJ
8292
-
TO MICROPROCESSOR
r.!.!
r-.!!
~
...!!.
DO
0101
01
0102
02
0103
03
"
19
21
22
23
9
10
•
TO
MICROPROCESSOR
8291
11
5
30
8
35
5
1
1
T/A1
WR
EOI
ATN
SRO
IFC
Cs
NDAC
CLOCK
NRFD
INT
REN
TRIG
38
2.
39
3
28
•
0101' ~
0101
f-1!...
f-1!...
0102
0102'
0103
0103'
0104
0100'
0105
0105' ~
010&
0108'
8293
TO
IEEE·..8
SUS
i1!-
0108'
f1L
!E-
DAY'
~
D107·
0107
0108
~
Tlih
DAY
EOI
ATN
27
2.
36
37
.........!.!.
2
OPTA
ATNO
~ iFCI
3!.
OPTS
flLy cc
fl!,.y cc
MODE 3
17
18
19
9
8
10
•
.....
......
&
32
33
35
f-.!.
i l l .!!.
~ DO
---.!!.
c...-....!i
~
18
I
iii07
DiOi
TlR2
OPI S
TRIGGE R
OUTPUT
TO
MICROPROCESSOR
7
DAY
DREO
7 DACK
8
3
33
liD
RESET
10
8
RS2
&
30
31
010&
07
RSO
RSI
23
32
DiGs
D6
25
21
9
0104
18
DO
17
05
28
02
10
03
DO
9
2
05
07
AD
liD
WR
RESET"
Cs
TCI
21
8
jffij 38
&
SRO
D6
8292
IFC
AfliRi
COUNT
T/RI
•m
01
23
5
29
23
39
3
EOl2
3'
7
iiNi
22
11
NOAC
NOAC
II'FI!II
NRFO
T/R2
SRO
. SRO'
REN
REN'
IFC
8213
IFC'
ATN'
ATNO
EOI'
EOI
~I
,.!!...
~I'
TO
EEE·488
SUS
,!!..
.!!..
.!!..
EOl2
iiNi
SPI
OSFI
38
ISFI
11
OSCILLATOR
OUTPUT
SYNC
r
YCC-2.. SS
tr
£i:!.1
15-25 pF
IFCL
X11
CiC
X,I
CLTH
EA
SYC
1
25
31
2'
27
21
2.
22
U
IFCL
CIC
OPTA 1!..YS
CLTH
OPTS
SYC
.l!. Yc
MODE 2
cON
-t
0FF
SYSTEM
CONTROLLER
SWITCH
205250-5
NOTES:
• = GPIB bus transceiver
t = See 8041 data sheet for alternate crystal configurations
tt = Can connect to system reset switch. see 8041A data sheet
Figure 5, 8291, 8292, and 8293 System Configuration
3-43
inter
8292
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... O·C to 70·C
Storage Temperature .......... - 65·C to + 150·C
Voltage to Any Pin with Respect
to Ground .............. " ........ 0.5V to + 7V
Power Dissipation ......... , ............. 1.5 Watt
D.C. CHARACTERISTICS
Symbol
TA = O·C to 70·C, Vss = OV: 8292, Vee
Parameter
0=
± 5V
± 10%
Min Max Unit
Test Conditions
I
VIL1
Input Low Voltage (All Except X1, X2, RESET)
-0.5 0.8
V
VIL2
Input Low Voltage (X1' X2, RESET)
-0.5
06
V
VIH1
Input High Voltage (All Except X1, X2, RESET)
2.2
Vee
V
VIH2
Input High Voltage (X1, X2,RESET)
3.8
Vee
V
VOL1
Output Low Voltage (00-07)
0.45
V
IOL = 2.0mA
VOL2
Output Low Voltage (All Other Outputs)
0.45
V
IOL
VOH1
Output High Voltage (00-07)
2.4
V
VOH2
Output High Voltage (All Other Outputs)
2.4 .
V
WR, CS, Ao
= 1.6 mA
IOH = - 400 /LA
IOH = -50/LA
±10 /LA Vss :;;: VIN :;;: Vee
IlL
Input Leakage Current (COUNT, IFCL, RD,
loz
Output Leakage Current (00-07, High Z State)
±10 /LA Vss +0.45 :>: VIN :>: Vee
=
=
ILl1
Low Input Load Current (Pins 21-24, 27 -38)
0.5
mA VIL
ILl2
Low Input Load Current (RESET)
0.2
mA VIL
lec
Total Supply Current
125
mA Typical = 65 mA
IIH
Input High Leakage Current (Pins 21-24, 27 -38)
100
/LA VIN = Vee
CIN
Input Capacitance
10
pF
CliO
1/0 Capacitance
20
pF
A.C. CHARACTERISTICS
0.8V
0.8V
TA = O·Cto 70·C, Vss = OV: 8292, Vee = ±5V ±10%
DBB READ
Symbol
Parameter
Min
J,
Max
Unit
Test Conditions
tAR
CS; Ao Setup to RD
tRA
CS, Ao Hold to RD t
tRR
RD Pulse Width
tAD
CS, Ao to Data Out Delay
225
ns
. CL = 150 pF
tRD
RD J, to Data Out Delay
225
ns
CL = 150pF
100
ns
15
/Ls
tDF
RD t to Data Float Delay
lev
Cycle Time
0
ns
0
ns
250
ns
2.5
3-44
inter
8292
DBB WRITE
Symbol
Parameter
Min
Max
Unit
tWA
Ao Setup to WA .J..
CS, Ao Hold after WA t
tww
WA Pulse Width
250
ns
tow
Data Setup to WA t
150
ns
two
Data Hold after WR .J..
0
ns
tAW
CS,
0
ns
0
ns
Test Conditions
COMMAND TIMINGS(1,3)
Code Name
Execution
IBFIT TCU2) SPI ATNO CIC
Time
E1
WTOUT
63
E2
WEVC
63
24
E3
REVC
71
24
51
E4
RERF
67
24
47
49
IFC
REN
Em
DAV
Comments
24
E5
RINM
69
24
E6
RCST
97
24
77
E7
RBST
92
24
72
E8
E9
RTOUT
69
24
49
EA
RERM
69
24
49
FO
SPCNI
53
24
F1
GIOL
88
24
F2
RST
94
24
F2
RST
214
24
Count Stops after 39
70
192
t61
.J..52
Not System Controller
.J..52 .J..179 .J..174 .J..101
System Controller
F3
RSTi
61
24
F4
GSEC
125
24
F5
EXPP
75
24
F6
GTSB
118
24
100
F7
73
24
F8
SLOC
SREM
91
24
55
73
F9
ABORT
155
24
133
FA
TCNTR
108
24
86
.J.. 71
FC
TCAS
24
67
.J..55
FD
TCSY
92
115
24
91
.J..80
FE
STCNI
59
24
PIN
RESET
29
-
X
lACK
116
t61
107
t98
.J..53 .J..55
t59 t57
t91
t46
.J..64
.J..120 .J..115 .J..42
.J..68
Starts Count after 43
.J..7
.J..7
Not System Controller
.J..73
t98
If Interrupt Pending
NOTES:
1. All times are multiples of tCY from the 8041 A command interrupt.
2. Tel clears after 7 tCY on all commands.
3. t indicates a level transition from low to high, .j. indicates a high to low transition.
3-45
8292
. ......
> < x=
A.C. TESTING INPUT, OUTPUT WAVEFORM
~
TEST POINTS
08
0 .•5
A.C. TESTING LOAD CIRCUIT
~
DEVICE
UNDER
TEST
0.8
ICL
205250-6
A.C. Testing: Inputs are driven at2.4V lor a Logic "1" and 0.45V
lor a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and O.BV lor a Logic "0".
':'
205250-7
Cl Include Jig Capacitance.
CLOCK DRIVER CIRCUITS
CRYSTAL OSCILLATOR MODE
DRIVING FROM EXTERNAL SOURCE
+5V
. r----< 15 pF
(INCLUDES XTAl.
SOCKET. STRAY)
,:
:J...
T
2
XTAll
,11-6 mHl
4701/
,ck
r=
J>--+----.....,XTAll
I
+5V
L_____
15-25pF
(INCLUDES SOCKET.
STRAYI
3
XTAL2
47011
1-::'----4--'-1 XTAl2
205250-B
NOTE:
205250-9
Both XTAL1 and XTAL2 should be driven. Resistors to
Vee are needed to ensure VIH = 2.8V if TIL circuitry
is used.
NOTE:
Crystal series .resistance should be <750 at 6 MHz;
<1800'at 3.6 MHz. ' ,
LC OSCILLATOR MODE
2
L
45"H
120"H
C
20pF
20pF
NOMINALf
5.2 MHz
3.2 MHz
r-I' ~,
-=
T
C
NOTES:
XTALI
1
1= 2wJ[C'
3
XTAL~
205250-10
1. Cpp ~ 5-10 pF pin-to-pin capacitance
2. Each C should be approximately 20 pF. including stray capacitance.
3-46,
C·=C+3Cpp
2
8292
WAVEFORMS
READ OPERATION-DATA BUS BUFFER REGISTER
CSORAo
(SYSTEM'S
ADDRESS IUS)
~
K
.
-tAR--"
iii)
(READ CONTROL)
"
4--
~tAD
.
--tRA"
IRR
IRV'
"\
I
..
1r--~---D-AT-A-V-A-Ll-D------~!~-----4
~
tAD ......
+--IDF-
DATAIUS _____________________
(OUTPUT)
"
____________
205250-11
WRITE OPERATION-DATA BUS BUFFER REGISTER
CiO
R A o = 1______________________________--"1
(SYSTEM'S
ADDRESS
IUS)
______________________
-~W-II-'- - - I w w
(WRITE
CONTR:~
~,..--------------~tDW-
IWD
...-
IV
DATA IUS
DATA
'v
DATA
«INPUT) ______
M_AY_C_H_A_N_G_E_____J/'!.,..___D_A_T_A_VA_L_ID____~Il\~-------M-A_Y_CH_A_N_G_E_________
205250-12
3-47
inter
8292
APPENDIX A
The following tables and state diagrams were taken from the IEEE Standard Digital Interface for Programmable Instrumentation, IEEE Std. 488-1978. This document is the official standard for the GPIB bus and can be
purchased from IEEE, 345 East 47th St., New York, NY 10017.
C MNEMONICS
Messages
pon
rsc
rpp
gts
tca
tcs
sic
sre
=power on
=request system control
=request parallel poll
:; go to standby
:; take control asynchronously
:; take control synchronously
=send interface clear
= send remote enable
IFC = interface clear
ATN =attention
TCT = take control
Interface States
CIOS
CADS
CTAS
CACS
CPWS
CPPS
=controller idle state
:; controller addressed state
=controller transfer state
:; controller active state
=controller parallel poll wait state
CSBS
CSHS
CAWS
CSWS
CSAS
CSNS
SNAS
SACS
SAIS
SANS
SAAS
SIIS
SINS
SIAS
=controller standby state
= controller standby hold state
=controller active wait state
:; controller parallel poll state
= controller synchronous wait state
= controller service requested state
=controller service not requested state
=system control active state
= system control not active stale
= system control remote enable idle state
:; system control remote enable not active state
=system control remote enable active state
=system control interface clear idle state
:; system control interface clear not active state
=system control interface clear active state
~
=accept data state (AH function)
=acceptor not ready state (AH function)
=source delay state (SH function)
1.5 ,...sec
t The microprocessor must wait for the 80 interrupt before writing the GTSB or GSEC
commands to ensure that (STRS 1\ SDYS) is true.
205250-13
rg
N
inter
8292
REMOTE MESSAGE CODING
Bus Signal Line(s) and Coding That
Asserts the True Value of the Message
C
Mnemonic
Message Name
T L D
D
Y A I
I
P S 00
E S 87654321
ACG
ATN
DAB
MSA
MAC Y 0 0 0 X X X X
Addressed Command Group
U UC X X X X X X XX
Attention
(Notes 1, 9) M DD D DOD D D D D
Data Byte
8 765 4 3 2 1
U HS X X X X X X X X
Data Accepted
Data Valid
U HS X X X X X X X X
Device Clear
M UC Y 0 0 1 0 1 0 0
U ST X X X X X X X X
End
(Notes 2, 9) M DD E E E E E E E E
End of String
876 543 2 1
Group Execute Trigger
M AC Y 0 0 0 1 0 0 0
M AC Y 0 0 0 0 0 0 1
Go to Local
U UC X X X X X X X X
Identify
U UC X X X X X X X X
Interface Clear
M AD Y 0 1 X X X X X
Listen Address Group
Local Lock Out
M UC Y 0 0 1 0 0 0 1
(Note 3) M AD Y 0 1 L L L L L
My Listen Address
54321
(Note 4) M AD Y
0 T T T T T
My Talk Address
432 1
(Note 5) M SE Y
1 S S S S S
My Secondary Address
NUL
OSA
OTA
PCG
PPC
PPE
Null Byte
Other Secondary Address
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Enable
PPD
Parallel Poll Disable
DAC
DAV
DCL
END
EOS
GET
GTL
IDY
IFC
LAG
LLO
MLA
MTA
NN
DRD
AFA
VDC
AESIR
TORFE
NIQCN
X X X
X X X
XXX
1 X X X X
1 X X X X
oX X X X
X X 0
1 X X
XXX
XXX
XXX
XXXXX
XXXXX
1 X X X X
1 X X X
X X X
XXX
X X X
X X X
X X X
XXX
X X X
1
1
X
X
o
oXXXX
X X X X
X X X X
1 X X X
X X 1 X
XXXX
XXXX
XXXX
X X X
X X X X
X X X
XXXX
5
5 4 3 2 1
PPR1
PPR2
PPR3
PPR4
PPR5
PPR6
PPR7
PPR8
PPU
REN
RFD
RQS
SCG
SDC
SPD
Parallel Poll Response 1
Parallel Poll Response 2
Parallel Poll Response 3
Parallel Poll Response 4
Parallel Poll Response 5
Parallel Poll Response 6
Parallel Poll Response 7
Parallel Poll Response 8
Parallel Poll Unconfigure
Remote Enable
. Ready for Data
Request Service
Secondary Command Group
Selected Device Clear
Serial Poll Disable
M
M
M
M
M
(Note 6) M
DD 0 0 0 0 0 0 0 0
X X X
X X X X X
SE
(OSA = SCG 1\ MSA)
AD
(OTA = TAG 1\ MTA)
(PCG = ACG V UCG V LAG V TAG)
AC Y 0 0 0 0 1 0 1
X X X
1 X X X X
SE Y 1 1 0 S P P P
X X X
1 X X X X
321
(Note 7) M SE Y 1
1 D D D D
X X X
XXXX
432 1
XXX
XXX
U ST X X X X X X X 1
X X X
U ST X X X X X X 1 X
XXX
XXX
XXX
U ST X X X X X 1 X X
USTXXXX1XXX
X X X
XXX
(Note 10) U ST X X X 1 X X X X
XXX
XXX
XXX
U ST X X 1 X X X X X
XXX
USTX1XXXXXX
XXX
XXX
U ST 1 X X X X X X X
1 X X X
XXX
M UC Y 0 0 1 0 1 0 1
1 X X X X
XXX
XXX
U UC X X X X X X X X
X X X X 1
X 0 X
U HS X X X X X X X X
XXXXX
XXX
oX X XX
(Note 9) U ST X 1 X X X X X X
XXXX
M SE Y 1 1 X X X X X
XXX
XXX
XXXX
M AC Y 0 0 0 0 1 0 0
MUCY001100
XXXX
XXX
3-50
inter
8292
REMOTE MESSAGE CODING (Continued)
Bus Signal Llne(s) and Coding That
Asserts the True Value of the Message
Mnemonic
SPE
SRQ
STB
Message Name
C
L D
Y A I
p S 0
E S 8 7 6 5 4 3 2
T
Serial Poll Enable
Service Request
Status Byte
D
I
0
1
MUCYOO11OOO
USTXXXXXXXX
(Notes 8, 9) M ST S X S S S S S S
8
6 5 432 1
Take Control
M AC Y 0 0 0 1 0 0 1
Talk Address Group
M AD Y 1 0 X X X X X
Universal Command Group
M UC Y 0 0 1 X X X X
Unlisten
M1DY0111111
Untalk
(Note 11) M 1D Y 1 0 1 1 1 1 1
TCT
TAG
UCG
UNL
UNT
N N
DR D
AFA
VDC
A E SIR
TOR F E
NIQCN
X X X
X X X
X X X
1 X X X X
X X 1 X X
oX XXX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The 1/0 coding on ATN when sent concurrent with multiline messages has been added to this revision for interpretive
convenience.
NOTES:
1.
2.
3.
4.
5.
6.
D1-DS specify the device dependent data bits.
E1-ES specify the device dependent code used to indicate the E08 message.
L1-L5 specify the device dependent bits of the device's listen address.
T1-T5 specify the device dependent bits of the device's talk address.
81-85 specify the device dependent bits of the device's secondary address.
8 specifies the sense of the PPR.
Response = 8eist
P1-P3 specify the PPR message to be sent when a parallel poll is executed.
P3
P2
P1
PPR Message
o
o
o
PPR1
1
1
1
PPRS
7. D1-D4 specify don't-care bits that shall not be decoded by the receiving device. It is recommended that all zeroes be
sent.
S. 81-86, 8S specify the device dependent status (DI07 is used for the RQ8 message.)
9. The source of the message on the ATN line is always the C function, whereas the messages on the DIO and EOI lines
are enabled by the T function.
10. The source of the messages on the ATN and EOI lines is always the C function, whereas the source of the messages on
the DIO lines is always the PP function.
11. This code is provided for system use.
3-51
intJ
8294A
DATA ENCRYPTION/DECRYPTION UNIT
Certified by National Bureau of
• Standards
400 Byte/Sec Data Conversion Rate
• 64-Bit
Data Encryption Using 56-Bit Key
• DMA Interface
• 3 Interrupt Outputs to Aid in Loading
• and Unloading Data
• 7-Bit User Output Port
5V ± 10% Power Supply
• Single
Compatible with iAPX-86, 88,
• Fully
MCS-85™, MCS-80™, MCS-51™, and
•
•
MCS-48TM Processors
Implements Federal Information
Processing Data Encryption Standard
Encrypt and Decrypt Modes Available
The Intel® 8294A Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and
decrypt 64-bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard. The DEU operates on 64-bit text words using a 56-bit user-specified key to produce 64-bit
cipher words. The operation is reversible: if the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the 8294A; however, the 56-bit key is user-defined and
may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the 8294A in 8-bit bytes by way of the
system data bus. A DMA interface and three interrupt outputs are available to minimize software overhead
associated with data transfer. Also, by using the DMA interface two or more DEUs may be operated in parallel
to achieve effective system conversion rates which are virtually any multiple of 400 bytes/second. The 8294A
also has a 7-bit TTL compatible output port for user-specified functions.
Because the 8294A implements the NBS encryption algorithm it can be used in a variety of Electronic Funds
Transfer applications as well as other electronic banking and data handling applications where data must be
encrypted.
DATA
BUS
NC
Xl
x2
RESET
f--i \r- '-~
Vec
CS
GNO
RO
AO
OAV-----j
CCMP-------j
iNA
.Y
___ ~ PO·P6
RESET--
SYNC~-~
--~
OACK
:;=-=---=l::j
+ 5V- POWER
-~
GND--~----
INTERNAL
BUS
SYNC
DO
01
02
03
04
05
06
07
210465-1
Figure 1. Block Diagram
GNO
VCC
NC
DACK
ORO
SRO
DAV
NC
P6
P5
P4
P3
P2
Pl
PO
VOO
VCC
CCMP
NC
NC
NC
210465-2
Figure 2. Pin Configuration
3-52
November 1986
Order Number: 210465-004
inter
8294A
Table 1. Pin Description
Symbol
Pin
No.
Type
Name and Function
NC
1
NO CONNECTION.
X1
X2
2
3
CRYSTAL: Inputs for crystal, L-C or external timing signal to determine
internal oscillator frequency.
~
4
Vee
5
CS
6
GNO
7
AD
8
I
READ: An active low read strobe at this pin enables the CPU to read
data and status from the internal OEU registers.
Ao
9
I
ADDRESS: Address input used by the CPU to select OEU registers
during read and write operations.
WA
10
I
WRITE: An active low write strobe at this pin enables the CPU to send
data and commands to the OEU.
SYNC
11
0
SYNC: High frequency (Clock + 15) output. Can be used as a strobe
for externa:l circuitry.
DO
12
13
14
15
16
17
18
19
I/O
01
02
03
04
05
06
07
DATA BUS: Three-state, bi-directional data bus lines used to transfer
data between the CPU and the 8294A.
GNO
20
GROUND: This pin must be tied to ground.
Vee
40
POWER:
NC
39
NO CONNECTION.
OACK
38
I
DMA ACKNOWLEDGE: Input signal from the 8257 OMA Controller
acknowledging that the requested OMA cycle has been granted.
OAO
37
0
DMA REQUEST: Output signal to the 8257 OMA Controller requesting
a OMA cycle.
SAO
36
0
SERVICE REQUEST: Interrupt to the CPU indicating that the 8294A is
awaiting data or commands at the input buffer. SAO = 1 implies ISF
= O.
OAV
35
0
OUTPUT AVAILABLE: Interrupt to the CPU indicating that the 8294A
has data or status available in its output buffer, OAV = 1 implies OSF
= 1.
NC
34
I
RESET: A low signal to this pin resets the 8294A.
POWER: Tied high.
I
CHIP SELECT: A low signal to this pin enables reading and writing to
the 8294A.
GROUND: This pin must be tied to ground.
+ 5V power input: + 5V ± 10%.
NO CONNECTION.
3-53
inter
8294A
Table 1. Pin Description (Continued)
Symbol
Pin
No.
P6
P5
P4
P3
P2
P1
PO
33
'32
31
30
29
28
27
Voo
Type
0
Name and Function
OUTPUT PORT: User output port lines. Output lines available to the
user via a CPU command which can asset selected port lines. These
li'nes have nothing to do with the encryption function. At power-on,
each line is in a 1 state.
POWER: +5V power input. (+5V ± 10%) Low power standby pin.
26
Vee
25
CCMP
24
POWER: Tied high.
NC
23
NO CONNECTION.
NC
22
NO CONNECTION.
NC
21
NO CONNECTION.
0
CONVERSION COMPLETE: Interrupt to the CPU indicating that the
encryption/decryption of an 8-byte block is complete.
FUNCTIONAL DESCRIPTION
OPERATION
The data conversion sequence is as follows:
1) A Set Mode command is given, enabling the desired interrupt outputs.
2) An Enter New Key command is issued, followed
by 8 data inputs which are retained by the DEU
for encryption/decryption. Each byte must have
odd parity.
RD
WR
CS
Ao
Register
1
0
1
0
0
1
0
1
0
0
1
1
X
X
0
0
0
0
1
Data Input Buffer
Data Output Buffer
Command Input Buffer
Status Output Buffer
Don't Care
X
The functions of each of these registers are described below.
Data Input Buffer-Data written to this register is
interpreted in one of three ways, depending on the
preceding command sequence.
3) An Encrypt Data or Decrypt Data command sets
the DEU in the desired mode.
1) Part of a key.
2) Data to be encrypted or decrypted.
After this, data conversions are made by writing 8
data bytes and then reading back 8 converted data
bytes. Any of the above commands may be issued
between data conversions to change the basic operation of the DEU; e.g., a Decrypt Data command
could be issued to change the DEU from encrypt
'mode to decrypt mode".without changing either the
key or the interrupt outputs enabled.
3) A DMA block count.
Data Output Buffer-Data read from this register is
the output of the encryption/decryption operation.
INTERNAL 'DEU REGISTERS
Command Input Buffer-Commands to the DEU
are writt,en into this register. (See command summary below.)
Four internal registers are addressable by the master processor: 2 for input, and 2 for output. The following table describes how these registers are accessed.
Status Output Buffer-DEU status is available in
this register at all times. It is used by the processor
for poll-driven command and data transfer operations.
3-54
STATUS BIT:
7 6 5
FUNCTION:
X X X KPE CF DEC IBF OBF
4
3
2
1
0
inter
8294A
OBF Output Buffer Full; OBF = 1 indicates that
This command puts the 8294A into the decrypt
mode.
output from the encryption/decryption function is available in the Data Output Buffer. It is
reset when the data is read.
IBF
4 -Set Mode
Input Buffer Full; A write to the Data Input
Buffer or to the Command Input Buffer sets
IBF = 1. The DEU resets this flag when it has
accepted the input byte. Nothing should be
written when IBF = 1.
OPCODE:
MSB
where:
DEC Deorypt; indicates whether the DEU is in an
encrypt or a dElcrypt mode. DEC = 1 implies
the decrypt mode. DEC = 0 implies the encrypt mode.
A is the OAV (Output Available) interrupt enable
B is the SRO (Service Request) interrupt enable
C is the DMA (Direct Memory Access) transfer enable
is the CCMP (Conversion Complete) interrupt
enable
o
After 8294A has accepted a 'Decrypt Data' or
'Encrypt Data' command, 11 cycles are required to update the DEC bit.
CF
This command determines which interrupt outputs
will be enabled. A "'" in bits A, B, or 0 will enable
the OAV, SRO, or CCMP interrupts respectively. A
"1" in bit C will allow DMA transfers. When bit C is
set the OAVand SRO interrupts should also be
enabled· (bits A, B = 1). Following the command
in which bit C, the DMA bit, is set, the 8294 will
expect one data byte to specify the number of
8-byte blocks to be converted using DMA.
Completion Flag; This flag may be used to indicate any or all of three events in the data
transfer protocol.
1) It may be used in lieu of a counter in the
processor routine to flag the end of an
8-byte transfer.
2) It must be used to indicate the validity of
the KPE flag.
3) It may be used in'lieu of the CCMP interrupt
to indicate the completion of a DMA operation.
KPE Key Parity Error; After a new key has been
entered, the DEU uses this flag in conjunction
with the CF flag to indicate correct or incorrect parity.
5 - Write to Output Port
OP CODE:
1'-0-'1-1""'1-0-'-1-0-'-1-0-'-1-0'-10----'-10---'1
MSB
PROCESSOR/DEUINTERFACE
PROTOCOL
LSB
This command is followed by 8 data byte inputs
which are retained in the key buffer (RAM) to be
used in encrypting and decrypting data. These data
bytes must have odd parity represented by the LSB.
ENTERING A NEW KEY
2 - Encrypt Data
OP CODE:
LSB
This command causes the 7 least significant bits
of the command byte to be latched as output data
on the 8294 output port. The initial output is
1111111. Use of this port is independent of the
encryption/decryption function.
Enter New Key
OP CODE:
r-11"'T"I-ps""T"I-Ps-rI-P4-rI-ps-rI-P2--'1-P--'1Ir-p-'o1
MSB
COMMAND SUMMARY
1-
LSB
l'--o--"l-o--r"I--r-1-1,'--10-'1-0-'-1-0-'--1---'01
MSB
After the Enter New Key command is issued, 8
data bytes representing the new key are written to
the data input buffer (most significant byte first).
After the eighth byte is entered into the DEU, CF
goes true (CF = 1). The CF bit goes false again
when KPE is valid. The CPU can then check the
KPE flag. If KPE = 1, a parity error has been detected and the DEU has not accepted the key.
Each byte is checked for odd parity, where the
parity bit is the LSB of each byte.
LSB
This command puts the 8294A into the encrypt
mode.
3 - Decrypt Data
OPCODE:
MSB
The timing sequence for entering a new key is
shown in Figure 3. A flowchart showing the CPU
software to accommodate this sequence is given
in Figure 4.
LSB
3-55
inter
8294A
ENCRYPTING OR DECRYPTING DATA
Figure 5 shows the timing sequence for encrypting
or decrypting data. The CPU writes a data bytes to
th~ DEU's data input buffer for encryption/decryp·
tion. CF then goes true (CF = 1) to indicate that the
DEU has accepted the a-byte block. Thus, the CPU
may test for IBF = 0 and CF = 1 to terminate the
input mode, or it may use a software counter. When
the encryption/decryption is complete, the CCMP
and OAV interrupts are asserted and the OBF fiag is
set true (OBF = 1). OAV and OBF are set false
again after each of the converted data bytes is read
back by the CPU. The CCMP interrupt is set false,
and remains false, after the first read. After a bytes
have been read back by the CPU, CF goes false (CF
= 0). Thus, the CPU may test for CF = 0 to terminate the read mode. Also, the CCMP interrupt may
be used to initiate a service routine which performs
the next series of a data reads and a data writes.
L
.PE _ _ _ _ _ _
INV_A_LlD_ _ _ _ _
~
A,.IL -\..j - L.J - - -l.S - - - - - _..IL
CHECKU-
ViR -,
r I r;;;-l
U
NEW
KEV
1J
r;EY
UDAl" U ;;~TA
'PE
KEY
DATA
COMMAND
210465-3
Figure 3. Entering a New Key
Since CF = 1 only for a short period of time after
the last byte is accepted, the CPU which polls the
CF flag might miss detecting CF = 1 momentarily.
Thus, a counter should be used, as in Figure 4, to
flag the end of the new key entry. Then CF is used to
indicate a valid KPE flag.
Figure 6 offers two flowcharts outlining the alternative means of implementing the data conversion protocol. Either the CF flag or a software counter may
be used to end the read and write modes.
SAO = 1 implies IBF = O,OAV = 1 implies OBF =
1. This,allows interrupt routines to do data transfers
without checking status first. However, the OAV
service routine must detect and flag the end of a
data conversion.
CCMPI
(IF ENABLED)
.----.
IL_ _ _ _ _ _---11
.001L..Jn L_
lIF ENABLED)
DATA REGISTER
IlJ1 - rr
IlJ1 rr
1 BYTE OF KEY
aAV
(IF ENABLED)
1-1+1
IL_ _ __
Jl'--_ _ _ _ _ _ __
-----
01'
wolJLJ-LJ
• DATA WRITES
e
20
m. -
MAXIMUM
a DATA READS
210465-5
Figure 5. Encrypting/Decrypting Data
210465-4
Figure 4. Flowchart for Enter!ng a New Key
3-56
inter
8294A
USING DMA
USING SOFTWARE COUNTER
The timing sequence for data conversions using
DMA is shown in Figure 7. This sequence can be
better understood when considered in conjunction
with the hardware DMA interface in Figure 8. Note
(lnN;;l~~
CF
SRO
jlFENAaLEDI
I_-'________________....Jr
::=r-1L---_ _ _ _--',
Lf1JLf --l
L _ _ _ _ _ _ __
I
1 IL_-'I IL-
QAV
4IF ENA8LEDI _ _ _ _ _ _ _ _ _ _
DAD~-Lrl
=
__ ~
--U--lJU--ULf--[j
SET
OMA
MODE
OMA
8 DMA READS
8 DMA WAITES
BLOCK
COUNT/n) _ _ _ _ _ _ _ _ _ __
210465-6
210465-8
USING CF FLAG
Figure 7. DMA Sequence
AO-A15
00-01
8257
YES
~8
'---rNo'"
NO
210465-7
Figure 6. Data Conversion Flowcharts
iNr----~Ej
8088'lWR -----
~~:ER80:~O~O::sg=
AD _ . -.,~
8294
OE:
cs--Ao - - - - - -
00-----<><3:
RD ______
WR--------q
210465-13
~
Figure 12. Polling Interface
210465-16
OMARO is for memory to OEU Data Transfer
OMAR1 is for OEU to memory Data Transfer
Use of CCMP is optional
1M
Figure 15. DMA Interface
MASTERiD~ ~~
PROCESSOR
INTERFACE
01
~
~----,/
OSCILLATING AND TIMING CIRCUITS
_ __
WII--~
f!---
A.---
8294A
DEU
The 8294A's internal timing generation is controlled
by a self·contained oscillator and timing circuit. A
choice of crystal, L·C or external clock can be used
to derive the basic. oscillator frequency.
ceMP
210465-14
The resident timing circuit consists of an oscillator, a
state counter and a cycle counter as illustrated in
Figure 16.
Figure 13. Single Interrupt Interface
3·59
inter
8294A
SYNC
I-T-r-OUTPUT
(1 25-15 "sec)
"---v-----'
INTERNAL TIMING
210465-17
Figure 16. Oscillator Configuration
OSCILLATOR MODE
LC OSCILLATOR MODE
1
1 = 2.".,f[C'
C1
'
r _ .....
,--r--_-...:·=-IXTAL1
I
I
-.1.-
CO'T'
r
ld
"::"
~.U.1.
C'
T
MHz
=
Cpp
"t---ll--....--:i XTA12
C +3 Cpp
2
5-10 pF
Pin-to-Pin
Capacitance
=
210465-19
__
L__
__C_
Nominal
9 /-,H
20 pF
11.5 MHz
45 /-,H
20 pF
5.2 MHz
120/-,M
20 pF
3.2 MHz
Each C should be approximately 20 pF
including stray capacitance.
210465-18
Cl = 5pF
C2 = Crystal + Stray < 15 pF
C3 = 20-30 pF
Crystal series resistance should be less than 750 at 6 MHz; less
than 1800 at 3.6 MHz; less than 300 at 12 MHz.
Figure 17. Recommended Crystal
DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS
+5.
XTAL1
r----~XTAL 1
+5.
»--~'--~ XTAL 2
210465-20
For the 8294A XTAL2 must be high 35-65% of the period.
Rise and fall times must not exceed IOns.
Resistor to Vee is needed to ensure VIH = 3.0V if TIL Circuitry is used.
Figure 18. Recommended Connection for External Clock Signal
3·60
intJ
8294A
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O·C to + 70·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on Any Pin With
Respect to Ground .............. - 0.5V to + 7V
Power Dissipation ....................... 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
= O·C to +70·C, Vee = +5V ±10%, vss = ov
TA
Symbol
Limits
Parameter
Typ
Min
Unit
Test Conditions
Max
VIL
Input Low Voltage (All
Except Xl, X2, RESET)
-0.5
0.8
V
VILl
Input Low Voltage (Xl, X2,
RESET
-0.5
0.6
V
VIH
Input High Voltage (All
Except Xl, RESET)
2.0
Vee
V
VIHl
Input High Voltage (Xl,
RESET
3.5
Vee
V
VIH2
Input High Voltage (X2)
2.2
Vee
V
VOL
Output Low Voltage (00-07)
0.45
V
IOL
VOL1
Output Low Voltage (All
Other Outputs)
0.45
V
IOL
=
=
2.0mA
1.6 mA
VOH
Output High Voltage (00-07)
2.4
V
IOH = -400,.,.,A
VOHl
Output High Voltage (All
Other Outputs)
2.4
V
IOH
IlL
Input Leakage Current
(RO, WR, CS, Ao)
±10
,.,.,A
Vss ::;: VIN ::;: Vee
IOFL
Output Leakage Current
(00-07, High Z State)
±10
,.,.,A
Vss + 0.45 ::;: VOUT ::;: Vee
100
Voo Supply Current
5
20
mA
100 + lee
Total Supply Current
60
135
mA
III
Low Input Load Current
(Pins 24, 27 -38)
0.3
mA
VIL
=
0.8V
ILl1
Low Input Load Current
(RESET)
0.2
mA
VIL
=
0.8V
IIH
Input High Leakage Current
(Pins 24, 27 -38)
100
,.,.,A
VIN
=
Vee
CIN
Input Capacitance
10
pF
CliO
I/O Capacitance
20
pF
3-61
=
-50,.,.,A
intJ
8294A
A.C. CHARACTERISTICS TA = O·Cto +70·C, vcc = VDD = +5V ±10%, vss
= OV
DBB READ
Symbol
Parameter
Min
tAR
CS, Ao Setup to AD ..J.,
Max
t
Unit
Test Conditions
ns
0
tRA
CS, Ao Hold After AD
tRR
AD Pulse Width
tAD
CS, Ao to Data Out Delay
130
ns
CL = 100 pF
tRD
AD ..J., to Data Out Delay
130
ns
CL = 100 pF
t
tDF
RD
tCY
Cycle Time
0
ns
160
ns
to Data Float Delay
85
ns
15
/Ls
1-12 MHz Crystal
Max
Unit
Test Conditions
1.25
DBB WRITE
Symbol
Parameter
Min
tAW
CS, Ao Setup to WR ..J.,
tWA
CS, Ao Hold After WR
tww
WR Pulse Width
tDW
Data Setup to WR
tWD
Data Hold to WR
t
t
t
0
ns
0
ns
160
ns
130
ns
0
ns
DMA AND INTERRUPT TIMING
Symbol
Parameter
Min
Max
Unit
tACC
DACK Setup to Control
0
ns
tCAC
DACK Hold After Control
0
ns
tACD
DACK to Data Valid
130
ns
tCRO
Control L.E. to ORO T.E.
110
ns
tCI
Control T.E. to Interrupt T.E.
400
ns
Test Conditions
CL = 100 pF
CLOCK
Symbol
Min
Max
Units
tCY
Cycle Time
Parameter
1.25
9.20
/Ls(l)
tCYC
Clock Period
83.3
613
ns
tPWH
Clock High Time
38
tpwL
Clock Low Time
38
tR
Clock Rise Time
10
ns
tF
Clock Fall Time
10
ns
NOTE:
1. ICY = 15/f(XTAL)
3·62
ns
ns
intJ
8294A
A.C. TESTING INPUT, OUTPUT WAVEFORM
, 4
'.0
::>
TEST POINTS
<
0.8
0.45
'.0
08
210465-21
WAVEFORMS
READ OPERATION-oUTPUT BUFFER REGISTER
CSOR Ao
]
K
_I'._j
I ••
"\
~~
(OUTPUT)
(SVSTEM'S
ADDRESS BUS)
I
(I
J_I.'~
-tAD-
(R EAD CONTROL)
-tDF-
l
----IAD---
-----------<
~
---DATAVALID--t>-------------
210465-22
WRITE OPERATION-INPUT BUFFER REGISTER
.:sOR..,
------','xrf'
r
1st
f''---------------
(SYSTEM'S
ADDRESS BUS)
-_',AW--4-'--'----- 'WW--l W
'-
(WRITE CONTROL)
_.Dw-_fl_"WD
DATA BUS
DATA
(INPUT) _ _ _ _.::M:::.AY:...;C"'~:.:;:A:.:;NG::.:E:........_ __ '
-~DATA
1'-------'-____
VAlID---
DATA
-.:::M;:.AY:...;C:::.H:.:;A:.:;NG::.:E:........_ _ _ __
210465-23
3·63
intJ
8294A
DMA AND INTERRUPT TIMING
'"
RoorWR
...
-I
-I
lAce
I'\.
/
ICAe
~
V
I
ORQ
I
-
~--
ICRQ
-
tACO--"--- -.-~-
DATA BUS
\V
/\.
VALID
OAVorSAQ
~
_.- Tel
--
I
210465-24
CLOCK TIMING
2.'V XTAL2
-
-
-
-
-
-
-
1.6V _ _ _ _ _ _ _
-!...)"::~=-=::-:I.-l.
_
.45V-
'.
210465-25
3-64
inter
AP-166
APPLICATION
NOTE
November 1986
Using the 8291AGPIB
. Talker/Listener
Order Number: 230832-001
3-65
AP·166
INTRODUCTION
The first section of this note presents an overview of
IEEE 488 (GPIB). The second section introduces the
Intel GPIB component family. A detailed explanation
of the 8291A follows. Finally, some application examples using the component family are presented.
This application note explains the Intel 8291A GPIB
(General Purpose Interface Bus) Talker/Listener as a
component, and shows its use in GPIB interface design
tasks.
DEVICE A
ABLE TO
TALK. LISTEN.
AND
CONTROL
D
~
DATA BUS
(I-
(e.g. calculator)
DEVICEB
ABLE TO
TALK AND
LISTEN
f-'----'
(e.g. digital
multlmeler)
(IDEVICEC
ONLY ABLE
TO LISTEN
DATA BYTE
TRANSFER
CONTROL
-.
f-'--
(e.g. algnal
generator)
(......
DEVICED
ONLY ABLE
TO TALK
GENERAL
INTERFACE
MANAGEMENT
.......
1.1
I----
(e.g. counter)
}DI01 ... 8
Data Input/Output
DAV
Data Available
NRFD
NDAC
Not Ready lor Data
Not Data Accepled
IFC
ATN
SRQ
Inlerlace Clear
AllenDon
REN
EOI
Servlce Reque,t
Remole Enable
End or IdanDIy
230832-1
Figure 1. Interface Capabilities and Bus Structure
3-66
inter
Ap·166
OVERVIEW OF IEEE 488/GPIB
Electrical Signal Lines
The GPIB is a parallel interface bus with an asynchronous interlocking data exchange handshake mechanism. It is designed to provide a common communication interface among devices over a maximum distance
of 20 meters at a maximum speed of 1 Mbps. Up to 15
devices may be connected together. The asynchronous
interlocking handshake dispenses with a common synchronization clock, and allows intercommunication
among devices capable of running at different speeds.
During any transaction, the data transfer occurs at the
speed of the slowest device involved.
As shown in Figure 1, the GPIB is composed of eight
data lines (D08-DOI), five interface management lines
(IFC, ATN, SRQ, REN, EOI), and three transfer controllines (DAV, NRFD, NDAC).
The eight data lines are used to transfer data and commands from one device to another with the help of the
management and control lines. Each of the five interface management lines has a specific function.
ATN (attention) is used by the Controller to indicate
that it (the controller) has access to the GPIB and that
its output on the data lines is to be interpreted as a
command. ATN is also used by the controller along
with EO! to indicate a parallel poll.
The GPIB finds use in a diversity of applications requiring communication among digital devices over
short distances. Common examples are: programmable
instrumentation systems, computer to peripherals, etc.
SRQ (service request) is used by a device to request
service from the controller.
The interface is completely defined in the IEEE
STD.-488-1978.
REN (remote enable) is used by the controller to specify the command source of a device. A device can be
issued commands either locally through its front panel
or by the controller.
A typical implementation consists of logical devices
which talk (talker), listen (listeners), and control GPIB
activity (controllers).
EOI (end or identify) may be used by the controller as
well as talker. A controller uses EO! along with ATN
to demand a parallel poll. Used by a talker, EOI indicates the last byte of a data block.
Interface Functions
The interface between any device and the bus may have
a combination of several different capabilities (called
'functions'). Among a total of ten functions defined, the
Talker, Listener, Source Handshake, Acceptor Handshake and Controller are the more common examples.
The Talker function allows a device to transmit data.
The Listener function allows reception. The Source and
Acceptor Handshakes, synchronized with the Talker
and Listener functions respectively, exchange the handshake signals that coordinate data transfer. The Controller function allows a device to activate the interface
functions of the various devices through commands.
Other interface functions are: Service request, Remote
local, Parallel poll, Device clear and Device trigger.
Each interface may not contain all these functions. Further, most of these functions may be implemented to
various levels (called 'subsets') of capability. Thus, the
overall capability of an interface may be tailored to the
needs of the communicating device.
IFC (interface clear) forces a complete GPIB interface
to the idle state. This could be considered the GPIB's
"interface reset." GPIB architecture allows for more
than one controller to be connected to the bus simultaneously. Only one of these controllers may be in command at any given time. This device is known as the
controller-in-charge. Control can be passed from one
controller to another. Only one among all the controllers present on a bus can be the system controller. The
system controller is the only device allowed to drive
IFC.
3-67
AP-166
SOURCE
NRFD SIGNAL LINES GOES HIGH
YES
,...._ _.1...._ _., ONLY WHEN ALL ACCEPTORS ARE READY
DATA IS VALID AND MAY
NOW BE ACCEPTED
DATA IS NOT TO BE CONSIDERED
VALID AFTER THIS TIME
230832-2
NOTE:
Flow diagram outlines sequence of events during transfer of data byte. More than one Ilstener at a time can accept data
because of logical connection of NRFD and NDAC lines.
Figure 2. Handshake Flowchart
3-68
inter
AP-166
Tonllon is a method where the ability of the GPIB
interface to talk or listen is determined by the device
and not by the GPIB controller. With this method,
fixed poles can be easily designated in simple systems
where reassignment is not necessary. This is appropriate and convenient for certain applications. For example, a logic analyzer might by interfaced via the GPIB
to a line printer in order to document some type of
failure. In this case, the line printer simply listens to the
logic analyzer, which is a talker.
Transfer Control Lines
The transfer control lines conduct the asynchronous interlocking three-wire handshake.
DAV (data valid) is driven by a talker and indicates
that valid data is on the bus.
NRFD (note ready for data) is driven by the listeners
and indicates that not all listeners are ready for more
data.
The controller addresses devices thrqugh three commands, MTA (my talk address), MLA (my listen address), and MSA (my secondary address). The device
address is imbedded in the command bit pattern. The
device whose address matches the imbedded pattern is
enabled. Some devices may have the same logical talk
and listen addresses. This is allowable since the talker
and listener are separate functions. However, two of the
same functions cannot have the same address.
NDAC (not data accepted) is used by the listeners to
indicate that not all listeners have read the GPIB data
lines yet.
The asynchronous 3-wire handshake flowchart is
shown in Figure 2. This is a concept fundamental to the
asynchronous nature of the GPIB and is reviewed in
the following paragraphs.
In primary addressing, a device is enabled to talk (listen) by receiving the MTA (MLA) message.
Assume that a talker is ready to start a data transfer.
At the beginning of the handshake, NRFD is false indicating that the listener(s) is ready for data. NDAC is
true indicating that the listener(s) has not accepted the
data, since no data has been sent yet. The talker places
data on the data lines, waits for the required settling
time, and then indicates valid data by driving DAV
true. All active listeners drive NRFD true indicating
that they are not ready for more data. They then read
the data and drive NDAC false to indicate acceptance.
The talker responds by deasserting DAV and readies
itself to transfer the next byte. The listeners respond to
DAV false by driving NDAC true. The talker can now
drive the data lines with a new data byte and wait for
NRFD to be false to start the next handshake cycle.
Secondary addressing extends the, address field from 5
to 10 bits by allowing an additional byte. This additional byte is passed via the MSA message. Secondary addressing can also be used to logically divide devices into
various subgroups. The MSA message applies only to
the device(s) whose primary address immediately precede it.
INTEL'S® GPIB COMPONENTS
The logic designer implementing a GPIB interface has,
in the past, been faced with a difficult and complex
discrete logic design. Advances in LSI technology have
produced sophisticated microprocessor and peripheral
devices which combine to reduce this once complex interface task to a system consisting of a small' set of
integrated circuits and some software drivers. A microprocessor hardware/software solution and a high-level
language source code provide an additional benefit in
end-product maintenance. Product changes are a simple matter of revising the product software. Field
changes are as easy as exchanging EPROMS.
Bus Commands
When ATN and DAV are true data patterns which
have been placed by the controller on the GPIB, they
are interpreted as commands by the other devices on
the interface. The GPIB standard contains a repertory
of commands such as MTA (My Talk Address), MSA
(My Secondary Address), SPE (Serial Poll Enable), etc.
All other patterns in conjunction with ATN and DAV
are classified as undefined commands and their meaning is user-dependent.
Intel has provided an LSI solution to GPIB interfacing
with a talkerllistener device (8291A), a controller device (8292), and a transceiver (8293). An interface with
all capabilities except for the controller function can be
built with an 8291A and a pair of 8293's. The addition
of the 8292 produces a complex interface. Since most
devices in a GPIB system will not have the controller
function capability, this modular approach provides the
least cost to the majority of interface designs.
Addressing Techniques
To allow the controller to issue commands selectively
to specific devices, three types of addressing exist on the
GPIB: talk only/listen only (tonllon), primary, and
secondary.
3-69
inter
AP-166
Current states of the 8291A can be determined by examining the device's status read registers. In addition,
the 8291A contains 8 write registers. These registers are
shown in Figure 3. The three register select pins RS3RSO are used to select the desired register.
Overview ofthe 8291A
GPIB Talker/Listener
The Intel 8291A GPIB Talker/Listener operates over a
clock range of 1 to 8 MHz and is compatible with the
MCS-85, iAPX-86, and 8051 families of microprocessors.
The data-in register moves data from the GPIB to the'
microprocessor or to memory when the 8291A is addressed to listen. When the 8291A is addressed to talk,
it uses the data-out register to move data onto the
GPIB. The serial poll mode and status registers are
used to request service and program the serial poll
status byte.
A detailed description of the 8291A is given in the data
sheet.
The 8291A implements the following functions: Source
Handshake (SH), Acceptor Handshake (AH), Talker
Extended (TE), Service Request (SRQ), Listener Extended (LE), Remote/Local (RL), Parallel Poll (PP2),
Device Clear (DC), and Device Trigger (DT).
Read Registers
A detailed description of each of the registers, along
with state diagrams can be found in the 8291A data
sheet.
Register Select
Code
Write Registers
r-~__~__- r__- r__- r__~__~__~RS2 RS1 RSO~~~~__~~__~__~__~__~~
I DI7 I DI6 I DI5 I 014 1 013 I DI2 I DI1
010 I 0
0
0 I 0071 0061 D05 I D04 I 003 1 D02 I D01 I DOO 1
DATA IN
DATA OUT
I CPT 1 APT 1 GET 1 END 1 DEC 1 ERR 1 BO
BI
I 0
0
I CPT I APT 1 GET 1 END I DEC 1 ERR I BO I
INTERRUPT STATUS 1
o I
liNT 1SPAS 1 LLO I REM 1 SPC 1LLOC 1REMC 1ADSC I 0
0
1 0
INTERRUPT STATUS 2
I 58 ISRosl 56 1 SS 1 54 1 53
1DMAOI DMAI 1 SPC I LLOC I REMCI ADSC
I
I
INTERRUPT ENABLE 2
52
51
1 I 58 I RSV I 56
I 0
SERIAL POLL STATUS 2
I ton 1 Lon I EOIILPASITPASI
BI
INTERRUPT ENABLE 1
I SS I 54 I 53
52
51
SERIAL POLL MODE
LA 1 TA IMJMNI
o
I
0
I
0
1 0
I ADM1 1ADMO 1
ADDRESS MODE
ADDRESS STATUS
I CPT71 CPT61 CPTsl CPT41 CPT31 CPT21 CPT1 I CPTO I 1
0
1 I CNT21 CNT1 1 CNTO 1COM41 COM31 COM21 COM1 1COMO I
COMMAND PASS THROUGH
AUXMODE
liNT 1 DTO 1 DLO I,ADS.0IAD4-0IAD3-oIAD2-0IAD1-01 1
o lARS 1 DT 1 DL
I ADS I AD4 I AD3 I AD2 1 AD1
I
ADDRESS 0/1
ADDRESS 0
I X IDT1 1 DL1 IAD5-1IAD4-1IAD3-1IAD2-1 IAD1-1 I 1
1 I EC7 1 EC6 1 ECS 1 EC4 1 EC3 1 EC21 EC1 I ECO I
ADDRESS 1
EOS
Figure 3_ 8291A Registers
3-70
inter
AP-166
address 1 registers allow reading of these programmed
addresses plus trading of the interrupt bit. The EOS
register is used to program the end of sequence character.
Address Mode
The address mode and status registers are used to program the addressing modes and track addressing states.
The auxiliary mode register is used to select a variety of
functions. The command pass through register is used
for .undefined commands and extended addresses. The
address 0/1 register is used to program the addresses to
which the 8291A will respond. The address 0 and
Detailed descriptions of the addressing modes available
with the 8291A are described in the 8291A data sheet.
Examples of how to program these modes are shown
below.
1. MODE: Talker has single address of 01 H
Listener has single address of 02H
CPU Writes to:
Pattern
Comment
Address Mode Register
Address 0/1 Register
Address 0/1 Register
0000 0001
0010 0001
1100 0010
Select Mode 1 Addressing
Major is Talking. Address = 01 H
Minor is Listener. Address = 02H
2. MODE: Talker has single address of 01 H
Listener has single address of 02H
CPU Writes to:
Pattern
Comment
Address Mode Register
Addr~ss 0/1 Register
Address 0/1 Register
0000 0001
0100 0010
1010 0001
Select Mode 1 Addressing
Major is Listener. Address = 02H
Minor is Talking. Address = 01 H
Note that in both of the above examples, the listener will respond to a MLA message with five least significant bits
equal to 02H and the talker to a 01H.
3. MODE: Talker and listener both share a single address of 03H
CPU Writes to:
Pattern
Comment
Address Mode Register
Address 0/1 Register
Address 0/1 Register
0000 0001
0000 0011
1110 0000
Select Mode 1 Addressing
Talker and Listener Address = 03
Minor Address is disabled
4. MODE: Talker and listener have a primary address of 04H and a secondary address of 05H
CPU Writes to:
Pattern
Comment
Address Mode Register
Address 0/1 Register
Address 0/1 Register
0000 0010
0000 0100
1000 0101
Select Mode 2 Addressing
Primary Address = 04H
Minor Address is disabled
5. MODE: Talker has a primary address of 06H. Listener has a primary address of 07H
CPU Writes to:
Pattern
Comment
Address Mode Register
Address 0/1 Register
Address 0/1 Register
0000 0011
0010 0110
1100 0111
Select Mode 3
Talker Address = 06
Listener Primary = 07
The CPU will verify the secondary addresses which could be the same or different.
3-71
AP-166
APPLICATION OF'THE 8291A
LISTENER FUNCTIONS
This phase of the application note will examine programming of the 8291A, corresponding bus commands
and responses, CPU interruption, etc. for a variety of
GPIB activities. This should provide'the reader with a
clear understanding of the role of the ,8291A performs
in a GPIB system. The talker function, listener function, remote message handling, and remote/local operations including local lockout, are discussed.
LISTEN·ONLY (Ion). In listen-only mode the 8291
will not respond to the My Listen Address (MLA) message from the controller. The sequence of events is as
follows:
Talker Functions
TALK-QNLY (ton). In talk only mode the 8291A will
not respond to tQe MTA message from a controller.
Generally, ton is used in an environment which does
not have a controller. Ton is also employed in an interface that includes the controller function.
When the 8291A is used with the 8292, the sequence of
events for initialization are as follows:
1)
2)
3)
4)
5)
6)
The Interrupt/Enable registers are programrned.
Ton is selected.
Settling time is selected.
EQS character is loaded.
"Pon" local message is sent.
,
CPU waits for Byte .out (BQ) and sends a byte to
the data out register.
Addressed Talker (via MTA Message)
The GPIB controller will direct the 8291A to talk by
sending a My Talk Address (MTA) message containing
the 8291A's talk address, The sequence of events is as
follows:
1) The interrupt enable and serial poll mode registers
are programmed.
2) Mode 1 is selected.
~) Settling time is selected.
4) Talker and listener addresses are programmed.
5) Power on (pon) local message is sent.
6) CPU waits for an interrupt. When the controller
has sent the MTA message for the 8291A an interrupt will be generated if enabled and the ADSC bit
will be set.
',
7) CPU reads the Address Status register to determine
if the 8291A has been addressed to talk (TA = l)~
8) CPU waits for an interrupt from either BQ or
ADSC
9) When BQ is set, the CPU writes the data byte to
the data out register.
10) CPU continues to poll the status registers.
11) When unaddressed ADSC, will be set and TA reset.
1) The Interrupt Enable registers are progriimmed.
2) Lon is selected.
3) BOS character is programmed,
4) "Pon" local message is sent.
5) CPU waits for BI and reads the byte from the datain register.
Note that enabling both ton and Ion can create an internal loopback as long as another listener exists.
Address.d Listening
(via the MLA Message)
The; GPIB controller will direct the. 8291A to listen by
sending a MLA message containing the 8291A's listen
address. The sequence of events is as folloWs:
I) The Interrupt Enable registers are programmed.
The serial poll mO,de register is loaded' as desired.
Talker and listener addresses are loaded.
"Pon" local message is sent.
The CPU waits for an interrupt. When the controller has sent the MLA message for the 8291A, the
ADSC bit will be set.
6) The CPU reads the Address Status Register to determine if the 8291A has been addressed to listen
(LA = I).
7) CPU waits for an interrupt for BI or ADSC,
8) When BI is set, the CPU reads the data byte from
the data-in register"
9) The CPU continues to poll the status registers,
10) When unaddressed, ADSC will be set and LA reset.
2)
3)
4)
5)
Remote/Local and Lockout .
Remote and local refer to the source of control of a
device counected to the GPIB. Remote refers to control
from the GPIB controller-in-charge. Local refers to
control from the device's own system. Reference should
be made to the RL state diagram in the 2891A data
sheet.
Upon "pon" the 8291A is in the local state. In this state
the REM bit in Interrupt Status 1 Register is reset.
When the GPIB controller takes control of the bus it
will drive the REN (remote enable) line true. This will
cause the REM bit and REMC (remote/local change)
bit to be set. The distinction between remote and local
modes is necessary in that some types of devices will
have local controls which have functions which are also
controlled by remote messages.
inter
AP-166
These two methods are called Serial and Parallel Poll.
The controller performs one of these two polling methods after a slave device requests service. As implied in
the name, a Serial Poll is when the controller sequentially asks each device if it requested service. In a Parallel Poll the controller asks all of the devices on the
GPIB if they requested service, and they reply in parallel.
In the local state the device is allowed to store, but not
respond to, remote messages which control functions
which are also controlled by local messages. A device
which has been addressed to listen will exit the local
state and go to the remote state if the REN message is
true and the local rtl (return to local) message is false.
The state of the "rtl" local message is ignored and the
device is "locked" into the local state if the LLO remote message is true. In the Remote state the device is
not allowed to respond to local messages which control
function that are also controlled by remote messages. A
device will exit the remote state and enter the local
state When REN goes false. It will also enter the local
state if the GTL (go to local) remote message is true
and the device has been addressed to listen. It will also
enter the local state if the rtl message is true and the
LLO message is false or ACDS is inactive.
Serial Poll
When the controller performs a Serial Poll, each slave
device sends back to the controller .a Serial Poll Status
Byte. One of the bits in the Serial Poll Status Byte indicates whether this device requested service or not. The
remaining 7 bits are used defined, and they are used to
indicate what type of service is required. The IEEE-488
spec only defines the service request bit, however HP
has defined a few more bits in the Serial Poll Status
Byte. This can be seen in Figure 4.
A device will exit the remote state and enter R WLS
(remote with lockout state) if the LLO (local lockout)
message is true and ACDS is active. In this mode, those
local messages which control functions which are also
controlled by remote messages are ignored. In other
words, the "rtl" message is ignored. A device will exit
R WLS and go to the local state if REN goes false. The
device will exit RWLS and go to LWLS if the GTL
message is true and the device is addressed to listen.
When a slave device needs service it drives the SRQ line
on the GPIB bus true (low). For the 8291A this is done
by setting bit 7 in the Serial Poll Status Byte. The CPU
in the controller may be interrupted by SRQ or it may
poll a register to determine the state of SRQ. Using the
8292 one could either poll the interrupt status register
for the SRQ interrupt status bit, or enables SRQ to
interrupt the CPU. After the controller recognizes a
service request, it goes into the serial poll routine.
Polling
The IEEE-488 standard specifies two methods for a
slave device to let the controller know that it needs
service.
rf
I
The first thing the controller does in the serial poll routine is assert ATN. When ATN is asserted true the
controller takes control of the GPIB, and all slave de-
SERVICE REQUESTED
0: SERVICE NOT REQUESTED
8
7
LTYPICAL HP
8
NOT USED
6
•
•
•
•
1
I
DEVICE DEPENDENT STATUS BITS-.-J
,--l
U~ 1: SERVICE REQUESTED
7
0: SERVICE NOT REQUESTED
6
•
W
•
•
DEVICE DEFINED
1: OPERATI.ON COMPLETE
0: BUSY
11:
L-------...1
ERROR
0: NORMAL
Figure 4. The Serial PQII Status Byte
3-73
230832-3
inter
'f·
AP-166
vices on the bus must listen. All bytes sent over the bus
while ATN is true are commands. After the controller
tai
TXRDY;
SETUP IlUFFERS *1
DECL .. RE IlUFF2 (100)
IlYTE;
1* RAM STORAGE AREA
DECLARE IlUFFI (100) IlYTE DATA
(1,2,3,4,5,6,',8,9,10H,
I"H, 13H, 14H, 15H,
l1H,
21H,
31H,
41H.
:;IH,
61H,
-TiH.
81H,
23H,
32H, 33H.
42H. 43H.
52H. 53H.
62H, 63H.
72H, 73H,
82H, 93H,
22H,
2411,
3411.
44H.
54H.
64H,
74H.
94H.
25H,
35H,
45H.
55H,
65H.
75H,
85H,
16H, 17H, 18H,
26H, 27H. 28H.
3611. 37H. 3BH.
46H. 47H. 4BH.
56H. 57H. 5BH.
66H. 67H. 6BH.
76H, 77H. 79H.
86H, 87H, 88H.
*_
19H, 20H.
29H. 30H.
39H. 40H.
49H. 50H.
59H. 60H.
69H. 70H,
79H. BOH.
89H. 90H.
230832-5
3-79
inter
PL/M-86
10
AP-166
C0I1P ILE"R
BOARDI
91H. 92H. 93H. ,94t;. 95H., 9bH. 97H. 98H.
DECLARE BUFF3 ( t7)
BYTE DATA
(ODH. 0AH, 'CDt1PARE ERROR'. 0!!H, C.~H),
1* 8
=NORM$TIME,
OUTPUT
(SET$MODE)
=WR$TRANSFER,
OUTPUT
(SET$MASK)
=CLEAR,
O'JTPUT
(51 ART$O$l.O;
~DMA$WRD$l.STN ('0),
DMA$WRD$LSTN (0)
=SHR (DMA$WRD~LSTN (0), 8),
2
59
60
64
65
66
':,lATUS$2>
00 WH I l.E
1*
52
53
54
55
56
57
58
~O;
I~HILE
i INPUT
(STATUS'SI) AND ERR) = ERR;
DO WHILE
(INPUT
(STATUS$I), AND BO) = 0;
END.
1* WAIT FOR BO INTR *1
OUTPUT
(PORT$OUT)
~OAAH.
END,
48
50
*1
(START $O$HIl
=DMA$WRD$LSTN (0),
OUTPUT
(O*COUtH$l.O)
"'Te$LOl,
, OUTPUT
(OSCOlINT$HI )
:Te$HII.
1* INIT
e~91A
OUTPUT
OUTPUT
OUTPUT
(COMMAND$MOD)
(AODR$STATUS)
( COMMAND$ti0D)
FOR LISTENER FUNCTIONS
*1
~RESET,
=MODI$LO;
=PON,
1*
DO WHILE (INPUT
(SJATUS$l)
ANDSI)
END,
1* WAIT FOR BI INTR . f
XYZ
., INPUT (PORT$IN),
LISTEN ONLY
=0.
67
OUTPUT
68
DO WHILE
(INPUT
(STATUSs!)
AND ONE) .:)
1* WAIT FOR EOJ RECEIVED -oj
(STATUS$2)
=DMA$REQ'L.
1*
*1
ENABLE DMA REGS
*1
ONE;
230832-8
3-82
AP·166
PL.-/M-B6 CDMPILEP
("JARf\
CMPHLW:
70
' .. rC"IPARE THE nlD BUFFERS CONTENTS *1
11AlCH=CMPB
71
IF t1ATCH
'"
73
74
75
(@BUFFL
100);
OKAY THEN GOTO START91.
'3E'ID ERROR MESSI>GE IN BUFFER 3
DO 1=0 TO 16,
CALL CO
(BUFF 3
!
2
2
@BUFF2,
(I)
*1
),
END,
70
(;OTO START91,
77
MODULE INFORMATION'
CCiDE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
243 LINES READ
o PROGRAM ERROR (5)
END OF PL/t1-86
=OlDBH
4750
1170
1120
=0075H
=0070H
=0006H
bD
CaMP ILATJON
230832-9
3-83
inter
PLlM-8t. C0I1PILER
1l0ARD2
ISIS-II PL/M-8t. VI 1 C0I1PILATION OF MODULE 1l0ARD2
OBJECT r10DULE PLACED IN
FI
BRD;!, OBJ
COMPILER INVOKED BY
PLM8t.
FI
BRD2, $RC
/. BOARD 2 TPT PROGRAM
1*
*1
*1
(1)
*1
AND Dt1A'S DATA INTO A BUFFER, t.HILE WAITING *1
FOR THE END IN1ERRUPT S IT TO BECOt1E ACTIVE *1
llPON END ACTIVE, THE DATA IN THE BUFFER IS *1
SEtH [j';C'" iO THE FIIIST BOARD VIA THE GPID
*1
t.HEN THE BLOCK IS FINISHED THE 80191A IS *1
1* PROGRAr1MED BACK INTO THE LISTENER MODE
*1
/* THIS BOARD LISTENS TO THE OTHER BOARD
1*
1*
1*
1*
1*
BOARD2
DO,
1* 8237 PORT ADDRESSES *1
2
DECLARE
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
CLEAII$FF
START$O$Lo
START$O$HI
O$COUNT$LO
O$COUNT$HI
SET.MODE
CMD$37
5ET$MASK
1* 8237 CUMMAND
3
- DATA BYTES
'OFFDDH' ,
'OFFDOH',
'OFFDOH',
'OFFDIH' ,
'OFFDIH', '
'OFFDBH' ,
OFFD8H',
'OFFDFH' ,
I*MASTER CLEAR *1
*1
DECLARE
'48H ,
RDHRANSFER
LITERALLY
WRHRANSFER
'44H',
LITERALLY
ADDR$!A
'OOH',
l.ITERALLY
J01H' ,
ADDR$!S
LITERALLY
NORt1$TIME
'20H',
LITERALLY
iC$LOI
l.ITERALLY
'OFFH',
iC.HIl
'OOH',
LITERALLY
'990',
LITERALLY
TC$L02
'OOH',
LITERALLY
TC$HI2
'OIH' ,
TC
l.ITERALLY
1* 8291A
4
PORT ADDRESSES *1
DECLARE
PORTSOUT
PORT$IN
STATUS$!
STATUS$2
ADOR$STATUS
C0I1r1AND$r100
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
'OFFCOH',
'OFFCOH',I* DATA IN *1
'OFFCIH' , 1* INTR STAT 1 *1
'OFFC2H', 1* INTR STAT 2 *1
'OFFC4H', 1* ADOR STAT
*1
'OFFC5H', 1* CMD PASS THRU *1
230832-10
3·84
inter
AP-166
PL/M-86 COMP IlER
RON'D2
ADDRSO
EOSSREG
5
LITERALLV
LITERALLV
'OFFC6H',
'OFFC7H',
1*
EOS REGISTER
*1
DECLARE.
ENDS EO!
LI TERALL V
DNE
LITERALLY
por~
LITERALLY
RESEl
L.l TERALLY
CLEAR
l.ITERALLV
Dt~ASREG$L L ITER ALL V
DMA$REGST LITERALLV
MODI$TO
LITERALLY
MOD 1 $LO
LI TERALL V
E05
LI1ERALLY
PRESCALER LITERALLY
HIGH$SPEED LITERALLY
XY!
BYTE,
130
L ITER ALL Y
131
LITERALLV
ERR
I I TERALL Y
'8SH',
10H',
'OOH "
'O.2H',
'OOH',
'10H',
I
'20H',
'SOH "
'40' ,
'ODH',
'23H',
'A4H',
'02H',
'OUi' ,
'04H',
START91,
OUTPUT
(STATUS$2)
=CLEAR'
1*
END INITILIZATION STATE
i* WIT 8'237 FOR LISTENER FUNCTION
7
INIT37L,
OUTPUT
(CLEAR$FF)
=CLEAR, 1*
TOGGLE MASTER RESET *1
OUTPUT
(CI1DS37)
=NORM$TH1E,
OUTPUT
(SET$t10DE)
=WR$TRAI~SFER,
1* BLOCK XFER MODE
OUTPUT
lSETSMASK)
=CLEAR,
OUTPUT
(START$O$LO)
=ADDR$lA,
OUTPUT
(START$O$HI)
=ADDR$lB,
OUTPUT
(OSCOUNTSLO)
=TC$L01.
OUTPLUT lO$COUNT$HI)
=TC$HI I,
S
9
10
11
12
13
14
l"
15
16
17
18
19
20
21
2
INIT 82qlA
I~AIT UNTIL EOI
DO (mILE
=0,
ReVD AND END INTR-i3IT SET
(INPUT
(STATUS$l)
*1
*1
FOR LISTENER FUNCTIONS
OUTPUT
(eOMI1AND$MOD)
=RESET,
OUTPUT
(ADDR$STATUS)
~MOD1$LO,
OUTPUT
(COMMANDSMOD)
=PON.
00 I~HILE (INPUT
(STATUS$I)
AND 131)
END.
1* WAIT FOR 131 INTR *1
XVZ= INPUT
(PORT$IN).
OUTPUT
(STATUS$2)
=DI1A$REG$L;
1*
22
*1
>1
AND DNE ) ()
*1
DNE,
230832-11
3-85
AP-166
PliM··8b
COMP ILER
23
1l0ARD2
END,
24
INIT37T.
1* INIT 8237 FOR TAI.KER FUNCTION
29
30
31
32
OUTPUT
OUTPUT
OUTPUT
DUTPu·r
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
33
34
35
36
:l7
38
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
25
26
27
28
1*
39
40
41
42
43
44
45
46
1
1
2
3
FOR TAl.KER FUNCTlON
(EOSSREG)
=EOS,
( COMMANOSMOD )
(AOORSSTATUS)
(COMMAt~D$MOO )
(,;OMt1AND$t100)
(COMMAND$MOD)
*1
=ENO$EOI,/* EOI ON EOS SENT
=110D1$TO,I* TALK ONLY *1
=PRESCALER,
=H I GH$SPEED,
"PON,
*1
-0,
DO (/HILE
(INPUT
(STATUS$I)
AND ERR)
=ERR,
DO (~HIlE
(INPUT
(STATUS$!)
AND BO)
END,
1* (~AIT FOR 110 INTR *1
OUTPUT
(PORT$OUTI
=OAAH,
END,
=0,
2
2
(STATUS$2)
=DMA$REG$T.
CIUTPUl
i* (~AIT FOR TC=O *1
1
DO (mILE
END,
2
50
51
8,,'~IA
INIT
DO (~HILE
(INPUT
(STATUS$I)
AND BO)
END,
1 * (~AIT FOR BO INTR
*/
OUTPUT
(PORT$OUT)
=OAAH,
2
47
48
49
*i
(STATUS$2)
"CLEAR,
1* CLEAR 8291A ORQ *1
(CLEAR$FF)
=CLEAR,
(CMO$37)
=NORM$TIME,
(SET$MOD!')
=RD$TRANSFER,
1* IlLOCK XFER MODE *1
(SET$MASK)
=CLEAR,
(START$O$LO)
=ADDR$lA,
(START$O$HI)
=ADDR$lB,
(O$COUNT$LO)
=TC$L02.
(O$COUiH$HI)
=TC$HI2.
( INPUT
(CMO$37)
AND TC)
<>
TC,
GOTO STAR T91,
END,
MODULE INIO ORMATION
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUt1 STACK SIZE
152 LINE.S READ
o PROGRAM ERROR (S)
=0122H
-OOOOH
-OOO!H
=OOOOH
2900
00
10
00
230832-12
3-86
inter
AP-166
APPENDIXC
SOFTWARE FOR HP 9835A
10
REM S.iHt IN
TERFACE CLEAR
20
ABORTIO 7
30
REM FORCE E
RRORS UNTIL UST
ENERS ACTIYE
49 Frc..rr:
St(lt4
1';'0 SrCl=E:IHAND(
Stul,
3213 STATUS ;-04~
Stat
330 PRINT CHR. I
2113
PlnNT "SEND
I NG PARAllEL POL
L RESPONSE MESSA
GE"
220 REM EXECUT I
NG PARALLEL POLL
230 Ppo 11 byt .. =p
POLl( 7)
240 PRINT "PARA
LLEL POLL BYTE
D (S~ .;; t
OUT
PUT 704 USING ".
,KM; "8"
~e Chkst~t:
S1
AlliS 715to.\l,5to.
t2,$t(lt3,Sto.t4
6€1
Err"Stot2 A
ND I
713
IF Err=1 TH
EN GOlD Freerr
80
PR I NT CHRtf
12), "USTENERS A
RE ON LINE"
90
REM CONFIGU
RE PPOLL
le0 FPOLL CONF:
CURE 7134; h0000~ 1
0121"
SING
KEYBOARD I NTERRU
PRINT "COMM
0
IHIT
=
'H' FOR LIST)"
150 Veyenl
ON k
BD GOSUB 610
160 STATUS 71S<
a.t 1, $to.t2, St o.t 3,
720 RETURN
730 Dec.:
RESET
784
748 PRINT CHRtl
12). "SELECTIVE D
EV JC E CLEAR SENT
1'
rIder
13
750
760
AHD
PRINT·,'
PRINT "COMM
(HIT
'H' FOP UST'"
778 RETUPi1
780 RefVI:
LOCAL
704
798 PRINT CHR. (
12). "REMOT. MESS
AGE SEHT"
S80 PRINT-"
810 PRINT "COMN
RHD
?
IHIT
'H' FOR usn"
S2B RETURN
S3e H.l.: ' PRINT
CHRft 12)
840 PRINT" e@@
• OPERATOR ALLO~
ABLE COMMANDS @@
"",T~;G$
560 PRINT CHRft
12) ,G$
570 PRINT "COMM
AND z ?
(HIT
'H' FOR usn"
5ge GOTO Keven
598 REM IHTERRU
PT SERYI CE ROUTI
NES
600 "REM GET KEY
BOARD DATA
e=B
270
IF Ppol1b,t
e=0 THEN GOTO ,,'
291
280 PRINT "oR
NOT FROM 8291"
281
PRINT "COIiM
RND = ?
(HIT
'H' FOR UST)"
290 COTO Keyen
300 PS291:
PRIN
T "SRO IS FROM N
CC 8291
THE
ENTERPR I SE"
3IB PRINT "PERF
bit· 4
•
IF
610 Whatke-:..:
'II'?
=
Dl
M K$ [S01
620 K$=KBDf
630 IF 5($="G"
HEN GOTO Ge~
640
IF K""D" T
HEN GOTO Dec
650
rF K$-"R" T
HEN GOTO Re"
660
IF K$="H"
HEN GOTO Hel,..
670
IF K.... X· T
HEN. GOTO X.i <
68:0' Get = TRIGSE
230832-13
PRINT "COMM
?
(H·IT
=
'H' FOR usn"
THEN Goro Pc fJr
530
COTO t:.e1"fon
REM R
EADY TO ReV CHAR
S FROM GP IB
540 DIM GHB01
550 EHTER 784 U
PRINT " ___ _
2ii--p~ol t by~
~~e!R~m~ ~E~T'
718
AHD
S31 Rc.vr-I
8)
or,
120 PRINT CHF"
12), "PARALLEL PO
LL CONFIGURED"
130 REM ENABlE
PT
140
AiiD
520
INANDIPpoI1b)te,
I "'.SPOIU.•
R 704
690 PRINT CHRtl
12). "GROUP E):ECU
12), "Sta.tUIJ • -;
St 01
.
340
:r t.;., =BIHAN
=
";Pp~fl1b)tE-
25(1
110
OPtllNG SERIAL PO
LL TO GET STATUS
"tel
18(1
IF Srct=O TH
EN GOTO t e- -=-I"t
19t'.
(IF;: i E'II
zeta PRItH CHRS (
12)· "SRQ PHEIVE
D" '
U"
850 PRINT" hH
koy
re5ul t
860 PRINT"
S.nd GET "
H
11.50.'91."
870
~RINT"
Sene! D£C 1"1
@ossa,,,"
230832-14
e~e
ac
PRINT
Send REM
940 Xl"lltl
DIM A
$1801
950
PRINT CHIUf
1"l"1-!-0.9."
690
PRINT
oar-d
1 nput
91"
900
PRINT
12),"Enter- dato.
to s.nd and hlt
Xl"llts ke,t·
'0
~,2
CONTINUE"
960
INPUT At
978 OUTPUT 704;
At
971
EOI 718
980 PRINT "COMM
AND = ?
IHIT
'H' FORUST'"
990 REtURN
1000 END
H
Prlnts th,
•919tabh"
PRINT
928
PRINT "
TRY IT
930
RETURN
'0,,, ahead,
3-87
230832-15
inter
AP-166
APPENDIX D
SOFTWARE FOR HP 8088/HP 9835A VIA GPIB
PL/M-86 COMPILER
HPIB
ISIS-II PL/M-86 V1. 1 COMPILATION OF MODULE HPIB
PLACED IN :F1:HPIB.OB~
COMPILER INVO~ED BY: PLM86 :F1:HPI~.SRC LARGE
OB~ECTMODULE
HPIB:
1*
PARAMETER DECLARATIONS
*1
DO,
DECLARE
•
ADDRSHI
LITERALLY
'01H',
ADDRSLO
LITERALLY
'OOH',
ADSC
LITERALLY
'01H',
BI
LITERALLY
'01H',
BO
LITERALLY
'Q2H',
CHARSCOUNT BYTE,
CHAR
BYTE,
CHARS(80)
BYTE,
CLEAR
LITERALLY
'OOH',
CPT
LITERALLY
'BOH' ,
CRLF
L I TERALL Y
, OAH' ,
DEC
L ITER ALLY
, 08H ' ,
DMASADRSLSTN
POINTER,
DMASADRSTALK
POINTER,
DMASWRDSLSTN(2) WORD AT
<.DMASADRSLSTN),
DMASWRDSTALK(2) WORD AT
<.DMASADRSTALK),
OMASREOSL
LITERALLY
'IOH',
OMASREOST
LITERALLY
'20H',
ONE
LITERALLY
'IOH',
ENOSEOI
LITERALLY
'B8H' ,
EOS
LITERALLY
'OOH',
ERR
LITERALLY
'04H',
GET
L ITER ALL Y
, 20H' ,
I
BYTE,
LISTEN
LITERALLY
'04H',
MLA
LITERALLV
'04H',
MODES 1
LITERALLY
'OIH',
NOSDMA
LITERALLY
'OOH',
NOSRSV
LITERALLY
'OOH',
NORMSTIME
LITERALLY
'20H',
PON
LITERALLY
'OOH',
PPC
LITERALLY
'O:lH',
PPESMASK
LITERALLY
'60H',
PPOLLSCNFGSFLAG LITERALLY
'OIH',
PPOLLSENSBYTE
BYTE,
PRISBUF(80) BYTE AT
<.CHARS),
ROSXFER
LITERALLY
'48H',
RESET
LITERALLY
'02H',
REMC
LITERALLY
'02H',
RSV
LITERALLY
'40H',
RXRDY
LITERALLY
'02H' ,
3-88
230832-16
inter
AP-166
HPIB
SRGS
L I TERALL V
'40H' ,
BVTE,
STATt
STAT2
BVTE,
TALK
LITERALLV
'02H',
TASORSLA
BVTE,
TRG
LITERALLV
'4tH',
TC
LITERALLV
'OtH',
TCSHI
LITERALLV
'OOH',
TCSLO
LITERALLV
'OFFH',
TXRDY
LITERALLV
'OIH',
UDC
BVTE,
WRSXFER
LITERALLV
'44H',
XVZ
BVTE,
1*
PORT DECLARATIONS
*1
3
DECLARE
ADDRSO
ADDRSSTATUS
CLEARSFF
CMDs37
COMMANDsMOD
COUNTSHI
COUNTSLO
CPTSREG
EOSSREG
PORTSIN
PORTSOUT
SERSDATA
SERSSTAT
SETSMASK
SETSMODE
SPOLLSSTAT
STARTSHI
STAR TSLO
STATUSSI
STATUSS2
,
4
6
7
B
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLY
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
LITERALLV
'OFFC6H',
'OFFC4H',
'OFFDDH',
'OFFDBH',
'OFFC'H',
'OFFDIH',
'OFFDIH" ,
'OFFC5H',
'OFFC7H',
'OFFCOH',
'OFFCOH',
'OFFFOH',
'OFFF2H',
'OFFDFH',
'OFFDBH',
'OFFC3H',
'OFFDOH',
'OFFDOH',
'OFFCIH·.
'OFFC2H',
1* crt
m•••• g •• li.t *1
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
GETSMSG(II) BVTE DATA (ODH,OAH, 'TRIGGER',OAH.ODH),
DECSMSG(16) BVTE DATA (ODH.OAH, 'DEYICE CLEAR',OAH.ODH),
REMCSMSG(10) BYTE DATA (ODH.OAH. 'REMOTE'.ODH.OAH),
CPTSMSG(22) BVTE DATA (ODH.OAM. 'UNDEF CMD RECEIYED'.OAH.ODHI,
HUHSMSG(II) BYTE DATA (ODH.OAM. 'HUH ???'.ODH.OAHI,
1* called procedure. *1
9
REOSER:
PROCEDURE,
230832-17
3-89
inter
AP·166
PL/M-S6 COMPILER
10
2
11
2
3
12
13
2
14
2
15
16
1
2
HPIB
DO WHILE (INPUT (SPOLL.STATI AND SRGSI-SRGS,
END,
END REGSER,
co: PROCEDURE(XXXI,
DECLARE
XXX
BVTE,
17 . 2
1S
3
19
2
20
2
21
1
22
2
23
3
24
3
25
2
DO WHILE (INPUT (SER.STATI AND TXRDVI<>TXRDV,
END,
OUTPUT (SER.DATAI-XXX,
END CD,
HUH:
PROCEDURE,
DO 1-0 TO 10,
CALL CO (HUH.MSQ(III,
END,
END HUH,
26
CI:
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
2
2
3
3
3
3
3
3
3
3
3
4
:5
4
4
3
3
2
4:5
46
PROCEDURE,
IF (INPUT (SER.STATI AND RXRDVI.RXRDV THEN
DO,
1-0,
CHAR.COUNT-O,
STORE.CHAR:
CHAR-(INPUT (SER.DATAI AND 7FHI,
CHAR.COUNT-CHAR.COUNT+l,
CALL CO (CHAR"
CHARS ( I I-CHAR,
1-1+11
IF CHAR <> CRLF THEN
DO,
DO WHILE (INPUT (SER.STATI AND RXRDVI <>RXRDV,
END,
QOTO STORE.CHAR,
END,
CALL REGSER,
END.
END CI,
TALK.EXEC:
PROCEDURE,
2
1*
manipulate ad dr ••• bit. 'or DMA controller
*1
47
4S
49
DMA.ADR.TALK-(eCHARSI,
DMA.WRD.TALK(l ,-SHL(DMA.WRD.TALK(l,. 41,
DMA.WRD.TALK(OI-DMA.WRD.TALK(OI+DMA.WRD.TALK(l"
50
OUTPUT (CLEAR.FFI-CLEAR,
230832-18
3-90
inter
AP-166
PL/M-86 COMPILER
51
52
53
54
HPIB
01
2
2
56
57
58
2
2
2
OUTPUT (CMD371-NORMSTIME,
OUTPUT (SETSMODEI-RDSXFER,
OUTPUT (SETSMASKI-CLEAR,
OUTPUT (STARTSLOI-DMASWRDSTALK(OI,
DMASWRDSTALK(01-SHR(DMASWRDSTALK(0).8),
OUTPUT (STARTSHI)-DMASWRDSTALK(OI,
OUTPUT (COUNTSLO)-CHARSCOUNT,
OUTPUT (COUNTSHII-O,
59
60
2
2
OUTPUT (EOSSREQ)-EOS,
OUTPUT (COMMANDSMOD)-ENDSEOI,
61
601
63
2
3
2
DO WHILE (INPUT (STATUSS1) AND BO)-O,
END,
OUTPUT (PORTSOUT)-OAAH,
64
65
66
67
68
69
01
3
4
3
3
01
DO WHILE (INPUT (STATUSS1) AND ERR I-ERR,
DO WHILE (INPUT (STATUSS1) AND BO)-O,
END,
OUTPUT (PORTSOUT)-OAAH,
END,
OUTPUT (STATUSS21-DMASREOST,
70
2
55
2
2
71
72
73
74
75
76
PROCEDURE,
2
2
77
78
79
80
81
82
83
84
85
2
2
2
2
2
2
2
2
2
OUTPUT (STATUSS21-CLEAR,
OUTPUT (CLEARSFF)-CLEAR,
OUTPUT (CMDS37)-NORMSTIME,
OUTPUT (SETSMODE)-WRSXFER,
OUTPUT (SETSMASKI-CLEAR,
DMASADRSLSTN-(eCHARS),
DMASWRDSLSTN(I).SHL(DMASWRDSLSTN(II.4),
DMASWRDSLSTN(O l-DMASWRDSLSTN (O)+DMASWRDSLSTNC 1),
OUTPUT (STARTSLO)-DMASWRDSLSTNCO) ,
DMASWRDSLSTN(0)-SHR(DMASWADSLSTN(0).8),
OUTPUT (STARTSHI)-DMASWRDSLSTN(O),
OUTPUT (COUNTSLO)-TCSLO,
OUTPUT (COUNTSHII-TCSHI,
OUTPUT (STATUSS2)-DMASREOSL,
86
2
END LISTENSEXEC,
2
2
2
87
PRINTER:
PROCEDURE,
88
2
8.
.0
91
92
93
2
3
3
3
2
DO WHILE PRlSaUF(I) <>CRLF,
CALL CO (PRlSBUFCl»,
1-1+1,
END,
CALL CO CPRlSaUF(I»,
94
2
END PRINTER,
230832-19
3·91
intJ
AP-166
PL/M-86 COMPILER
HPIS
ADSCtEXEC:
9'
PROCEDURE,
96
2
TAtORtLA-INPUT (ADDRtSTATUS),
97
9B
99
100
2
2
2
2
IF (TAtORtLA AND TALK)-TALK THEN
CALL TALKtEXEC,
IF (TAtORtLA AND LISTEN)-LISTEN THEN
CALL LISTENtEXEC,
101
2
102
103
104
10'
106
1
2
3
3
2
QETtEXEC:
107
lOB
109
110
111
1
2
3
3
2
DECtEXEC:
112
113
114
11'
116
1
2
3
3
2
REMCtEXEC:
117
END ADSCtEXEC,
PROCEDURE,
DO 1"0 TO 10,
CALL CO (QETtMSQ(II),
END,
END QETtEXEC,
PROCEDURE,
DO 1-0 TO 1',
CALL CO (DECtMSQ(II),
END,
END DECtEXEC,
PROCEDURE,
DO 1-0 TO 9,
CALL CO (REMCtMSg(II),
END,
END REMCtEXEC,
PPOLLtCON:
PROCEDURE,
llB
2
OUTPUT (COMMANDtMOD)-PPOLLtCNFQtFLAQ,
119
2
END PPOLLtCON,
120
PPOLLtEN:
PROCEDURE,
121
122
2
2
PPOLLtENtSYTE-(UDC AND 6FH),
OUTPUT (COMMANDtMODI-PPOLLtENtSYTE,
123
2
END PPOLLtEN,
124
12'
126
127
1
2
3
3
128
129
130
131
2
2
2
2
UDC-INPUT (CPTtREQ),
UDC-(UDC AND 7FH),
IF (UDC AND PPC)=PPC THEN
CALL PPOLLtCON,
132
133
2
2
IF (UDC AND PPEtMASK)-PPEtMASK THEN
CALL PPOLLtEN,
CPTtEXEC:
PROCEDURE,
DO 1-0 TO 21,
CALL CO (CPTtMSQ(I»,
END,
3-92
230832-20
inter
AP-166
HPIB
P~/M-86 COMPI~ER
END CPTSEXEC.
134
1*
BEQIN CODE
*1
INIT:
1311
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
136
137
138
139
140
141
14;!
(C~EARSFF)
-C~EAR,
(COMMANDSMOD)
-RESET.
(ADDRSSTATUS)
-MODESI.
(ADDRSO)
-MLA,
(STATUSS;!) -NOSDMA.
(COMMANDSMOD)
..pON,
~ISTENERS:
DO WHI~E (INPUT (STATUSSl) AND,BI)-O,
END,
;!
XVI-INPUT (PORTSIN).
XVZ-INPUT (STATUSS;!),
143
144
1411
CMD:
RDSTAT:
1* read status registers and interpret command *1
STATl=INPUT (STATUSSl).
STAT;!-INPUT (STATUSS;!),
146
147
148
149
150
1
1
1
1
1111
1II;!
1113
1114
1115
156
1117
158
1119
;!
;!
;!
1
1
;!
;!
;!
1110
1
161
16;!
163
;!
;!
;!
1
164
1
165
1
;!
;!
;!
1
166
167
168
169
IF CSTATI AND DNE)-DNE THEN
CA~~ PRINTER,
IF CSTATI AND CPT)-CPT THEN
DO,
CA~~ CPTSEXEC,
STAT;!-CSTAT;! AND OFEH),
END.
IF CSTATI AND OET)aQET THEN
DO.
CA~L OETSEXEC.
STAT;!-CSTAT2 AND OFEH),
ENO,
IF CSTATI AND DEC)-DEC THEN
DO,
CAL~ DECSEXEC,
STAT;!-CSTAT;! AND OFEH),
END,
IF CSTAT;! AND REMC)-REMC THEN
DO.
CA~~ REMCSEXEC,
STAT;!-CSTAT2 AND OFEH),
END.
IF CSTAT;! AND ADSC)-ADSC THEN
3-93
230832-21
AP-166
PL/M-S6 COMPILER
170
171
172
173
HPII
1
2
2
DO.
CALL. ADSC.EXEC,
STAT2-CSTAT2 AND OFEHll
ENDI
2
174
CALL. CII
175
OOTO CMDI
176
END.
MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE
YARIAILE AREA SIZE
MAXIMUM STACK SIZE
34., L.INES READ
o PROORAI'I ERRORCSl
• 0475H
1141D
• OOOOH
OD
.,70
• 0061H
• OOOAH
10D
&ND OF PL/M-16 COMPIL.ATION
230832-22
3-94
inter
APPLICATION
NOTE
AP-66
November 1987
Using the 8292 GPIB Controller
Order Number: 231324-002
3-95
infe{
AP-eS
built a system they had to invent new cables and new
documentation just to specify the cabling and interconnection procedures.
INTRODUCTION
The Intel® 8292 is a preprogrammed UPITM-4IA that
implements the Controller function of the IEEE Std
488-1978 (GPIB, HP-IB, IEC Bus, etc.). In order to
function the 8292 must be used with the 8291 Talker/
Listener and suitable interface and transceiver logic
such as a pair of Intel 8293s. In this configuration the
system has the potential to be a complete GPIB ControUer when driven by the appropriate software. It has
the following capabilities: System Controller, send IFC
and Take Charge, send REN, Respond to SRQ, send
Interface messages, Receive Control, Pass Control, Parallel Poll and Take Control Synchronously.
Based on this experience, Hewlett-Packard began to define a new interconnection scheme. They went further
than that, however, for they wanted to specify the typical communication protocol for systems of instruments.
So in 1972, Hewlett-Packard came out with the first
version of the bus which since has been modified and
standardized by a committee of several manufacturers,
coordinated through the IEEE, to perfect what is now
known as the IEEE 488 Interface Bus (also known as
the HPIB, the GPIB and the IEC bus). While this bus
specification may not be perfect, it is a good compromise of the various desires and goals of instrumentation
and computer peripheral manufacturers to produce a
common interconnection mechanism. It fits most instrumentation systems in use today and also fits very
well the microcomputer I/O bus requirements. The basic design objectives for the GPIB were to:
1) Specify a system that is easy to use, but has all of the
terminology and the definitions related to that system precisely speUed out so that everyone uses the
same language when discussing the GPIB.
2) Define all of the mechanical, electrical, and functional interface requirements of a system, yet not define
any of the device aspects (they are left up to the
instrument designer).
3) Perinit a wide range of capabilities of instruments
and computer peripherals to use a system simultaneously and not degrade each other's performance.
4) Allow different manufacturers' equipment to be connected together and work together on the same bus.,
5) Define a system that is good for limited distance interconnections.
6) Define a system with minimum restrictions on performance of the devices.
7) Define a bus that allows asynchronous communication with a wide range of data rates.
8) Define a low cost system that does not require extensive and elaborate interface logic for the low cost
instruments, yet provides higher capability for the
higher cost instruments if desired.
9) Allow systems to exist that do not need a central
controller; that is, communication directly from one
instrument to another is possible.
This application note will explain the 8292 only in the
system context of an 8292, 8291, two 8293s and the
driver software. If the reader wishes to learn more
about the UPI-41A aspects of the 8292, Intel's Application Note AP-41 describes the hardware features and
programming characteristics of the device. Additional
information on the 8291 may be obtained in the data
sheet. The 2893 is detailed in its data sheet. Both chips
will be covered here in the details that relate to the
GPIB controUer.
The next section of this application note presents an
overview of the GPIB in a tutorial, but comprehensive
nature. The knowledgeable reader may wish to skip this
section; however, certain basic semantic concepts introduced there will be used throughout this note.
Additional sections cover the view of the 8292 from the
CPU's data bus, the interaction of the 3 chip types
(8291, 8292, 8293), the 8292's software protocol and
the system level hardware/software protocol. A brief
description of interrupts and DMA will be followed by
an application example. Appendix A contains the
source code for the system driver software.
GPIB/IEEE 488 OVERVIEW
Design Objectives
WHAT IS THE IEEE 488 (GPIB)?
The experience of designing systems for a variety of
applications in the early 1970's caused Hewlett-Packard to define a standard intercommunication mechanism which would allow them to easily assemble instrumentation systems of varying degrees of complexity. In
a typical situation each instrument designer designed
hislher own interface from scratch. Each one was inconsistent in terms of electrical levels, pin-outs on a
connector, and types of connectors. Every time they
Although the GPIB was originally designed for instru~
mentation systems, it became obvious that most of
these systems would be controlled by a calculator or
computer. With this in mind several modifications were
made to the original proposal before its final adoption
as an international standard. Figure I lists the salient
characteristics of the GPIB as both an instrumentation
bus and as a computer I/O bus.
3-96
AP-66
requires special attention to considerations beyond the
scope of this note. Although not required, data buffering in each device will improve the overall bus performance and allow utilization of more of the bus bandwidth.
Data Rate
1M bytes/s, max
250k bytes/s, typ
Multiple Devices
15 devices, max (electrical limit)
8 devices, typ (interrupt flexibility)
Bus Length
20m, max
2 m/device, typ
Byte Oriented
8-bit commands
8-bit data
Block Multiplexed
Optimum strategy on GPIB due to
setup overhead for commands
Interrupt Driven
Serial poll (slower devices)
Parallel poll (faster devices)
Direct Memory Access
One DMA facility at controller
serves all devices on bus
Asynchronous
One talker
3-wire handshake
Multiple listeners
110 to I/O Transfers
Talker and listeners need not
include microcomputer/controller
Multiple Devices-Many microcomputer systems used
as computers (not as components) service from three to
seven peripherals. With the GPIB, up to 8 devices can
be handled easily by I controller; with some slowdown
in interrupt handling, up to 15 devices can work together. The limit of 8 is imposed by the number of unique
parallel poll responses available; the limit of 15 is set by
the electrical drive characteristics of the bus. Logically,
the IEEE 488 Standard is capable of accommodating
more device addresses (31 primary, each potentially
with 31 secondaries).
Bus Length-Physically, the majority of microcomputer systems fit easily on a desk top or in a standard 19"
(48-cm) rack, eliminating the need for extra long cables. The GPIB is designed typically to have 2m of
length per device; which accommodates most systems.
A line printer might require greater cable lengths, but
this can be handled at the lower speeds involved by
using extra dummy terminations.
Byte Oriented-The 8-bit byte is almost universal in
I/O applications; even 16-bit and 32-bit computers use
byte transfers for most peripherals. The 8-bit byte
matches the ASCII code for characters and is an integral submultiple of most computer word sizes. The
GPIB has an 8-bit wide data path that may be used to
transfer ASCII or binary data, as well as the necessary
status and control bytes.
}
Block Multiplexed-Many peripherals are block oriented or are used in a block mode. Bytes are transferred in
a fixed or variable length group; then there is a wait
before another group is sent to that device, e.g., one
sector of a floppy disc, one line on a printer or type
punch, etc. The GPIB is, by nature, a block multiplexed bus due to the overhead involved in addressing
various devices to talk and listen. This overhead is less
bothersome if it only occurs once for a large number of
data bytes (once per block). This mode of operation
matches the needs of microcomputers and most of their
peripherals. Because of block multiplexing, the bus
works best with buffered memory devices.
Figure 1. Major Characteristics of GPIB as
Microcomputer 1/0 Bus
The bus can be best understood by examining each of
these characteristics from the viewpoint of a general
microcomputer I/O bus.
Data Rate-Most microcomputer systems utilize peripherals of differing operational rates, such as floppy
discs at 31k or 62k bytes/s (single or double density),
tape cassettes at 5k to 10k bytes/s, and cartridge tapes
at 40k to 80k bytes/so In general, the only devices that
need high speed 110 are 0.5" (1.3-cm) magnetic tapes
and hard discs, operational at 30k to 781k bytes/s, respectively. Certainly, the 250k-bytes/s data rate that
can be easily achieved by the IEEE 488 bus is sufficient
for microcomputers and their peripherals, and is more
than needed for typical analog instruments that take
only a few readings per second. The IM-byte/s maximum data rate is not easily achieved on the GPIB and
Interrupt Driven-Many types of interrupt systems exist, ranging from complex, fast, vectored/priority networks to simple polling schemes. The main tradeoff is
usually cost versus speed of response. The GPIB has
two interrupt protocols to help span the range of applications. The first is a single service request (SRQ) line
that may be asserted by all interrupting devices. The
controller then polls all devices to find out which wants
service. The polling mechanism is well defined and can
3-97
inter
AP·66
be easily automated. For higher performance, the parallel poll capability in the IEEE 488 allows up to eight
devices to be polled at once-each device is assigned to
one bit of the data bus. This mechanism provides fast
recognition of an interrupting device. A drawback is
the frequent need for the controller to explicitly conduct a parallel poll, since there is no equivalent of the
SRQ line for this mode.
Asynchronous Transfers-An asynchronous bus is desirable so that each device can transfer at its own rate.
However, there is still a strong motivation to buffer the
data at each device when used in large systems in order
to speed up the aggregate data rate on the bus by allowing each device to transfer at top speed. The GPIB is
asynchronous and uses a special 3-wire handshake that
allows data transfers, from one talker to many listeners.
Direct Memory Access (DMA}-In many applications,
no immediate processing of I/O data on a byte-by-byte
basis is needed or wanted. In fact, programmed transfers slow down the data transfer rate unnecessarily in
these cases, and higher speed can be obtained using
DMA. With t.he GPIB, one DMA facility at the,controller serves all devices. There is no need to incorporate complex logic in each device.
I/O to I/O Trans/ers-In practice, I/O to I/O transfers
are seldom done due to the need for processing data
and changing formats or due to mismatched data rates.
However, the GPIB can support this mode of operation
where the microcomputer is neither the talker nor one
of the listeners.
.
rrrrr
DEVICE A
ABL'E TO
TALK. LISTEN.
AND
CONTROL
r
Ir f
==1-
DATA BUS
(t-
(e.g. computer)
DEVICE B
ABLE TO
TALK AND
LISTEN
==1-
(e.g. digital
mullirnete,)
<1---
DATA BYTE
TRANSFER
CONTROL
DEVICE C
ONLY ABLE
TO LISTEN
I
(e.g. ,Ignal
generator)
A
-
(
GENERAL
INTERFACE
MANAGEMENT
DEVICE 0
ONLY ABLE
TO TALK
I
f-
(e.g. counter)
~}
DIOL(?ATA
NPUT/OUTPUT)
DAV (DATA VALID)
NRFD (NOT READY FOR DATA)
NDAC(NOT DATA ACCEPTED)
IFC (INTER FACE CLEAR)
ATN (ATTENTIDN)
SRQ (SERVI CE REQUEST)
REN (REMO TE ENABLE)
EOI (END-O R-IDENTIFY)
231324-1
Figure 2. Interface Capabilities and Bus Structure
3-98
inter
AP-66
NDAC-Not Data Accepted. This handshake line is asserted by a Listener to indicate it has not yet accepted
the data or control byte on the DIO lines. Note that the
Controller will not see NDAC deasserted (i.e., data accepted) until all devices have deasserted NDAC.
GPIB Signal Lines
DATA BUS
The lines DIOI through DI08 are used to transfer addresses, control information and data. The formats for
addresses and control bytes are defined by the IEEE
488 standard (see Appendix C). Data formats are undefined and may be ASCII (with or without parity) or
binary. DIOI is the Least Significant bit (note that this
will correspond to bit 0 on most computers).
DAV-Data Valid. This handshake line is asserted by
the Talker to indicate that a data or control byte has
been placed on the DIO lines and has had the minimum
specified settling time.
--{
.._ _ _---I~---(
..._ _ _ _......~-
DID
MANAGEMENT BUS
H-
A TN-Attention. This signal is asserted by the Controller to indicate that it is placing an address or control byte on the Data Bus. ATN is de-asserted to allow
the assigned Talker to place status or data on the Data
Bus. The Controller regains control by reasserting
ATN; this is normally done synchronously with the
handshake to avoid confusion between control and data
bytes.
DAY
L-
H-,.,
_---l 1...._____.......n
NRFD L
10_ _ __
n . _____11
NDAC: - _ _ _ _..
231324-2
Figure 3. GPIB Handshake Sequence
EOI-End or Identify. This signal has two uses as its
name implies. A talker may assert EOI simultaneously
with the last byte of data to indicate end of data. The
Controller may assert EOI along with ATN to initiate a
Parallel Poll. Although many devices do not use Parallel Poll, all devices should use EOI t<;> end transfers
(many currently available ones do not).
GPIB Interface Functions
There are ten (10) interface functions specified by the
IEEE 488 standard. Not all devices will have all functions and some may only have partial subsets. The ten
functions are summarized below with the relevant section number from the IEEE document given at the beginning of each paragraph. For further information
please see the IEEE standard.
1) SH-Source Handshake (section 2.3). This function provides a device with the ability to properly
transfer data from a Talker to one or more Listeners using the three handshake lines.
2) AH-Acceptor Handshake (section 2.4). This function provides a device with the ability to properly
receive data from the Talker using the three handshake lines. The AH function may also delay the
beginning (NRFD) or end (NDAC) of any transfer.
3) T-Talker (section 2.5). This function allows a device to send status and data bytes when addressed
to talk. An address consists of one (Primary) or two
(Primary and Secondary) bytes. The latter is called
an extended Talker.
SRQ-Service Request. This line is like an interrupt: it
may be asserted by any device to request the Controller
to take some action. The Controller must determine
which device is asserting SRQ by conducting a Serial
Poll at its earliest convenience. The device deasserts
SRQ when polled.
IFC-Interface Clear. This signal is asserted only by
the System Controller in order to initialize all device
interfaces to a known state. After deasserting IFC, the
System Controller is the active controller of the system.
REN-Remote Enable. This signal is asserted only by
the System Controller. Its assertion does not place devices into Remote Control mode; REN only enables a
device to go remote when addressed to listen. When in
Remote, a device should ignore its front panel controls.
TRANSFER BUS
NRFD-Not Ready For Data. This handshake line is
asserted by a listener to indicate it is not yet ready for
the next data or control byte: Note that the Controller
will not see NRFD deasserted (i.e., ready for data) until
all devices have deasserted NRFD.
3-99
inter
Ap·66
4) L-Listener (section 2.6). This function allows a
device to receive data when addressed to listen.
There can be extended Listeners (analogous to extended Talkers above).
5) SR-Service Request (section 2.7). This function
allows a device to request service (interrupt) the
Controller. The SRQ line may be asserted asynchronously.
6) Rr..:.-Remote Local (section 2.8). This function allows a device to be operated in two modes: Remote
via the GPIB or Local via the manual front panel
controls.
7) PP-Parallel Poll (section 2.9). This function allows a device to present one bit of status to the
Controller-in-charge. The device need not be addressed to talk and no handshake is required.
8) DC-Device Clear (section 2.10). This function allows a device to be cleared (initialized) by the Controller. Note that there is a difference between DC
(device clear) and the IFC line (interface clear).
9) DT-Device Trigger (section 2.11). This function
allows a device to have its basic operation started
either individually or as part of a group. This capability is often used to synchronize several instruments.
10) C-Controller (section 2.12). This function allows
a device to send addresses, as well as universal and
addressed commands to other devices. There may
be more than one controller on a system, but only
one may be the controller-in-charge at anyone
time.
At power-on time the controller that is hardwired to be
the System Controller becomes the active controller-incharge. The System Controller has several unique capabilities including the ability to send Interface Clear
(IFC-clears all device interfaces and returns control
to the System Controller) and to send Remote Enable
(REN-allows devices to respond to bus data once they
are addressed to listen). The System Controller may
optionally Pass Control to another controller, if the system software has the capability to do so.
REN
SHIELD
ATN
SRQ
IFC
NOAC
NRFO
OAV
EOI
0108
0107
0108
0105
0104
0103
0102
0101
t
24 12
GNO
~
231324-3
Figure 4. GPlB Connector
GPIB Signal Levels
The GPIB signals are all TTL compatible, low true
signals. A signal is asserted (true) when its electrical
voltage is less than 0.5 volts and is deasserted (false)
when it is -greater than 2.4 volts. Be careful not to become confused with the two handshake signals, NRFD
and NDAC which are also low true (i.e. > 0.5 volts
implies the device is Not Ready For Data).
The Intel 8293 GPIB transceiver chips ensure that all
relevant bus driver/receiver specifications are met. Detailed bus electrical specifications may be found in Section 3 of the IEEE Std 488-1978. The Standard is the
ultimate reference for all GPIB questions.
GPIB Message Protocols
GPIB Connector
The GPIB connector is a standard 24-pin industrial
connector such as Cinch or Amphenol series 57 MicroRibbon. The IEEE standard specifies this connector, as
well as the signal connections and the mounting hardware.
The cable has 16 signal lines and 8 ground lines. The
maximum length is 20 meters with no more than two
meters per device.
The GPIB is a very flexible communications medium
and as such has many possible variations of protocols.
To bring some order to the situation, this section will
discuss a protocol similar to the one used by Ziatech's
ZT80 GPIB controller for Intel's MULTIBUSTM computers. The ZT80 is a complete high-level interface
processor that. executes a set of high level instructions
that map directly into GPIB actions. The sequences of
commands, addresses and data for these instructions
provide a good example of how to use the GPIB (additional information is available in the ZT80 Instruction
Manual). The 'null' at the end of each instruction is for
cosmetic use to remove previous information from the
DIO lines.
3-100
intJ
AP-66
DATA-Transfer a block of data from device A to de-
2) Go To Local
3) Null
vices B, C ...
1) Device A Primary (Talk) Address
Device A Secondary Address (if any)
2) Universal Unlisten
3) Device B Primary (Listen) Address
Device B Secondary Address (if any)
Device C Primary (Listen) Address
etc.
4) First Data Byte
Second Data Byte
LOCAL-Reset all devices to Local
1) Stop asserting REN
LLKAL-Prevent all devices from returning to Local
1) Local Lock Out
2) Null
SPO,LL-Conducts a serial poll of devices A, B, ...
1) Serial Poll Enable
2) Universal Unlisten
3) ZT 80 Primary (Listen) Address
ZT 80 Secondary Address
4) Device Primary (Talk) Address
Device Secondary Address (if any)
5) Status byte from device
6) Go to Step 4 until all devices on list have been polled
7) Serial Poll Disable
8) Null
Last Data Byte (EO!)
5) Null
TRIGR-Trigger devices A, B ... to take action
1) Universal Unlisten
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Group Execute Trigger
4) Null
PPUAL-Unconfigure and disable Parallel Poll response from all devices
1) Parallel Poll Unconfigure
2) Null
ENAPP-Enable Parallel Poll response in devices A, B,
PSCTL-Pass control to device A
1) Device A Primary (Talk) Address
Device A Secondary Address (if any)
2) Talk Control
3) Null
1) Universal Unlisten
2) Device Primary (Listen) Address
Device Secondary Address (if any)
3) Parallel Poll Configure
4) Parallel Poll Enable
5) Go to Step 2 until all devices on list have been configured.
6) Null
CLEAR-Clear all devices
1) Device Clear
2) Null
DISPP-Disable Parallel Poll response from devices A,
B, ...
REMAL-Remote Enable
1) Assert REN continuously
1) Universal Unlisten
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Disable Parallel Poll
4) Null
GOREM-Put devices A, B, ... , into Remote
1) Assert REN continuously
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Null
This Ap Note will detail how to implement a useful
subset of these controller instructions.
GOLOC-Put devices A, B, ... into Local
1) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3-101
AP-66
from the CPU; the other seven control various features
of the 8291.
HARDWARE ASPECTS OF THE
SYSTEM
8291 GPIB Talker/Listener
The 8291 is a custom designed chip that implements
many of the non-controller GPIB functions. It provides
hooks so the user's software can implement additional
features to complete the set. This chip is discussed in
detail in its data sheet. The major features are summarized here:
- Designed to interface microprocessors to the GPIB
- Complete Source and Acceptor Handshake
- Complete Talker and Listener Functions with extended addressing
- Service Request, Parallel Poll, Device Clear, Device
Trigger, Remote/Local functions
- Programmable data transfer rate
- Maskable interrupts
- On-chip primary and secondary address recognition
- 1-8 MHz clock range
- 16 registers (8 read, 8 write) for CPU interface
- DMA handshake provision
- Trigger output pin
- On-chip EOS (End of Sequence)
The pinouts and block diagram are shown in Figure 5.
One of eight read registers is for data transfer to the
CPU; the other seven allow the microprocessor to monitor the GPIB states and various bus and device conditions. One of the eight write registers is for data transfer
The 8291 interface. functions will be software configured in this application example to the following subsets for use with the 8292 as a controller that does not
pass control. The 8291 is used only to provide the
handshake logic and to send and receive data bytes. It
is not acting as a normal device in this mode, as it never
sees ATN asserted.
SHI Source Handshake
AHI Acceptor Handshake
T3
Basic Talk-Only
Ll
Basic Listen-Only
SRO No Service Requests
RLO No Remote/Local
PPO No Parallel Poll Response
DCO No Device Clear
DTO No Device Trigger
If control is passed to another controller, the 8291 must
be reconfigured to act as a talker/listener with the following subsets:
SH 1 Source Handshake
AH 1 Acceptor Handshake
T5
Basic Talker and Serial Poll
L3
Basic Listener
SRI Service Requests
RLl Remote/Local with Lockout
PP2 Reconfigured Parallel Poll
DCl Device Clear
DTl Device Trigger
CO Not a Controller
Pin Configuration
Block Diagram
GPIB CONTROL
TO NON INVERTING
BUS TRANSCEIVERS
I
r/R CONTROL
231324-5
231324-4
Figure 5. 8291 Pin Configuration and Block Diagram
3-102
intJ
AP-66
Most applications do not pass control and the controller is always the system controller (see 8292 commands
below).
The status register is used to pass Interrupt Status information to the master CPU (AO = 1 on a read).
The DBBOUT register is used to pass one of five other
status words to the master based on the last command
written into DBBIN. DBBOUT is accessed when AO
= 0 on a Read. The five status words are Error Flag,
Controller Status, GPIB Status, Event Counter Status
or Time Out Status.
8292 GPIB Controller
The 8292 is a preprogrammed Intel8051A that provides the additional functions necessary to implement a
GPIB controller when used with an 8291 Talker/Listener. The 8041A is documented in both a user's manual and in AP-41. The following description will serve
only as an outline to guide the later discussion.
DBBIN receives either commands (AO = 1 on a Write)
or command related data (AO = 0 on a write) from the
master. These command related data are Interrupt
Mask, Error Mask, Event Counter or Time Out.
The 8292 acts as an intelligent slave processor to the
main system CPU. It contains a processor, memory,
I/O and is programmed to perform a variety of tasks
associated with GPIB controller operation. The on-chip
RAM is used to store information about the state of the
Controller function, as well as a variety of local variables, the stack and certain user status information.
The timer/counter may be optionally used for several
time-out functions or for counting data bytes transferred. The I/O ports provide the GPIB control signals,
as well as the ancillary" lines necessary to make the
8291, 2, 3 work together.
8293 GPIB Transceivers
The 8293 is a multi-use HMOS chip that implements
the IEEE 488 bus transceivers and contains the' additionallogic required to make the 8291 and 8292 work
together. The two option strapping pins are used to
internally configure the chip to perform the specialized
gating required for use with 8291 as a device or with
8291/92 as a controller.
In this application example the two configurations used
are shown in Figure 7a and 7b. The drivers are set to
open collector or three state mode as required and the
special logic is enabled as required in the two modes.
The 8292 is closely coupled to the main CPU through
three on-chip r~gisters that may be independently accessed by both the master and the 8292 (UPI-41A).
Figure 6 shows this Register Interface. Also refer to
Figure 12.
t.~,A-~
'
•
CPU
~
:!
II:
~
i
."U
-
-
........
CS AO RD WR
0
0
0
0
1
0
1
0
1
0
0
1
1
1
1
0
0
X
X
X
STATUS
1
DBBIN
I UPI-41A
r
0
~~ ~::1'\
-;-
t\1
I-I-- ....
AO
~
RD
WIi
I
1 DBBOUT
231324-48
REGISTER
READ DB BOUT
READ STATUS
WRITE DBBIN (DATA)
WRITE DBBIN (COMMAND)
NO ACTION
Figure 6. UPI-41A Registers
3-103
I
inter
AP-66
a. 8293 Mode 2
b. 8293 Mode~..
+5
MODE 2
OPTA
lTNO
1m
+5
OPT.
NDAC~----~--------~
NDAC*
NoU'Dr---------------~
NRFD*
DAY
TIFtl
Diif;
Tllll
wcr---~----------~
SYC
'FC*
r-......+-----------......- l
tiKJ,
REN*
DIO,
SRO*
Dm4
ATI'IlI---+-_--l----r-i
~~~-4_--l---~~~
ATN*
~~-4--_+---------+~_
EO'*
om;
mo.
mo,
DR!I
Em
nil
231324-7
231324-6
Figure 7
8291/2/3 Chip Set
Figure 8 shows the four chips interconnected with the
special logic explicitly shown.
The 8291 acts only as the mechanism to put commands
and addresses on the bus while the 8292 is asserting
ATN. The 8291 is tricked into believing that the ATN
line is not asserted by the ATN2 output of the ATN
transceiver and is placed in Talk-only mode by the
CPU. The 8291 then acts as though it is sending data,
when in reality it is sending addresses and/or commands. When the 8292 deasserts ATN, the CPU software must place the 8291 in Talk-only, Listen-only or
Idle based on the implicit knowledge of how the controller is going to participate in the data transfer. In
other words, the 8291 does not respond directly to addresses or commands that it sends on the bus on behalf
of the Controller. The user software, through the use of
Listen-only or Talk-only, makes the 8291 behave as
though it were addressed.
Although it is not a common occurrence, the GPIB
specification allows the Controller to set up a data
transfer between two devices and not directly participate in the exchange. The controller must know when
to gQ active again and regain control. The chip set accomplishes this through use of the "Continuous Acceptor Handshake cycling mode" and the ability to detect
EOI or EOS at the end of the transfer. See XFER in the
Software Driver Outline below.
If the 8292 is not the System Controller as determined
by the signal on its SYC pin, then it must be able to
respond to an IFC within 100 I-I-sec. This is accomplished by the cross-coupled NORs in ~e 7a which
deassert the 8293's internal version of CIC (Not Controller-in-Charge). This condition is latched until the
8292's firmware has received the IFCL (interface clear
received latch) signal by testing the IFCL input. The
firmware then sets its signals to reflect the inactive condition and clears the 8293's latch.
3-104
intJ
AP-66
+5
MODE 3
ATNO
~~
~
DAY
row
T/1I1
T/R1
Dm1-lI
DRii
liEN
Imn
~-
rnJ
l>iOO
T/1I2
DT04
iFC
mas
H
H
NRFD
0106
filOAe
j)j()7
V
~
~-
8291
rnJ
A'i'N
A'i'N
SiiQ
f---
OPTA
OPTB
DA Y*
010
010
-
01
-
010
~
~ r~ r~
0108
r-
010 5*
r-
0106*
010
010 8*
MODE 2
OPTA
-Y7
_3
OPTB
NDAC
~
DAY
mmi
$IR
T/R1
8292
j
IFC
IFC
SYC
SYC
liEN
liEN
SiiQ
sm:i
ATm
ATNI
V
~
I
t
T'C
SIR
TIC
~
ferSR
AfN
EOi2
EOi2
i
~r1T
rt->tR=
ATNO
EOi
ATiW
COUNT
SA
T/R2
iFC[
wer
CLTH
CLTH
eiC
CIC
NDAC*
NRFD*
IFC*
REN*
SRO*
ATN*
EOI*
TC
~
231324-8
Figure 8. Talker/Listener/Controller
3-105
inter
AP-66
In order for the 8292 to conduct a Parallel Poll the
8291 must be able to capture the PP response on the
010 lines. The only way to do this is to fool the 8291
by putting it into Listen-only mode and generating a
DAV condition. However, the bus spec does not allow
a DAV during Parallel Poll, so the back-to-back 3-state
buffers (see Figure 7b) in the 8293 isolate the bus and
allow the 8292 to generate a local DAV for this purpose. Note that the 8291 cannot assert a Parallel Poll
response. When the 8292 is not the controller-in-charge
the 8291 may respond to PPs and the 8293 guarantees
that the DIO drivers are in "open collector" mode
through the OR gate (Figure 7b).
Figure 9 shows the card's block diagram. The
ZT7488/18 plugs into the STD bus, a 56 pin 8 bit microprocessor oriented bus. An 8085 CPU card is also
available on the STD bus and will be used to execute
the driver software.
The 8291 uses I/O Ports 60H to 67H and the 8292 uses
I/O Ports 68H and 69H. The five interrupt lines are
connected to a three-state buffer at I/O Port 6FH to
facilitate polling operation. This is required for the
TCI, as it cannot be read internally in the 8292. The
other three 8229 lines (SPI, IBF, OBF) and the 8291's
INT line are also connected to minimize the number of
I/O reads necessary to poll the devices.
ZT7488/18 GPIB Controller
NDAC is connected to COUNT on the 8292 to allow
byte counting on data transfers. The example driver
software will not use this feature, as the software is
simpler and faster if an internal 8085 register is used for
counting in software.
Ziatech's GPIB Controller, the ZT7488/18 will be used
as the controller hardware in this Application Note.
The controller consists of an 8291, 8292, an 8 bit input
port and TTL logic equivalent to that shown in Figure 8.
DATA BUS
DO~D7
=U
8291
BUFFERS
AG-"
~
r---f---"3~STATE
....
~
r--lORa'
CARD
SELECT
DECODER
"-M
-
h
'"""--
10 EX'-
ADDRESS
r--
829.
BUFFERS
WT'
SVB AESET-
DMA
CONNECTOR
---INTERFACE
LOOIC
I-
CLOCKRD'
J.
f--~
"--ADDRESS
r-l-
U
~
-
~
~0---0
PORT
SELECT
DECODER
'---
_
INTERRUPT
PORT
II
r-'
~
f-
TRANS..
CIIVERS
-;:::
Jl
GPI 8
NNECTOR
co
I='--
231324-9
'INDICATES ACTIVE LOW LOGIC
Figure 9. ZT7488/18 GPIB Controller
3-106
inter
AP-66
READ REGISTERS
PORT #
WRITE REGISTERS
I 0171 016 I 0151 014 I 013 I 012 I 011 I 010 1 6cf>H 100710061 0051 0041 003 I 0021 001 I 0001
DATA IN
DATA OUT
ICPT I APT I GET I END I DEC
I ERR
INTERRUPT STATUS 1
I BO
I BI
ICPT I APT I GET I END 1 DEC
1 61 H
I ERR I BO I BI 1
INTERRUPT MASK 1
liNT ISPASI LLO I REM ISPAScl LLOC IREMCI Aosci 62H I 0 I 0 10MAOI OMAllsPAScl LLOclREMCIAOScl
INTERRUPT STATUS 2
INTERRUPT MASK 2
I S8
I S8
ISROsl S6 I S5 I S4 I S3 I S2 I S1 1 63H
SERIAL POLL STATUS
I ton \
I rsv 1 S6 I S5 1 S4 1 S3 I S2 I S1 1
SERIAL POLL MODE
Ion \ EOI \ LPAS \ TPAS \ LA \ TA \MJMNI 64H \ TO \ LO \
ADDRESS STATUS
0
\ 0 \ 0 \ 0
ADDRESS MODE
\AOM1\AOMOI
ICPT7\ CPT61cPT51 CPT41 CPT31 CPT21 CPT11 CPTO 1 65H ICNT21cNT11 CNTO ICOM41 COM31cOM21cOM11cOMOI
COMMAND PASS THROUGH
AUX MODE
X I OTO \ OLO IA05-01 A04-0 IA03-0IA02-0IA01-01 66H lARS 1 OT 1 OL 1 ADS I A04 \ AD3 I A02 I A01 1
ADDRESS 0
ADDRESS 0/1
X I OT1 \ OL1 \A05-11 A04-1IA03-1IA02-1\A01-11 67H I EC7\ EC6\ EC5
ADDRESS 1
I EC4\
EC3 \ EC21 EC1 \ ECO 1
EOS
Figure 10_ 8291 Registers
.1 .,
r-A,
AD
a
ilSIf
::
~ 03
IIIIIW
~
0,
,n .,
WA
imIII
a,
A,
.,~
mw
~---=¥t
r----'
101M
RESE
T
'NT A
V
'NT
D7-D 0_
l
:V'
1ft
.
fA
1ft
---y
l..J.,
:: Il=
I--
ClK
-
07·00
.
I-
Z
fA
ffl
~
~
es
8212
MD
...,
r--
8257-5
HAQ
HLD"
Aoy
ClK
DS1
~~
~
rI
~S~~
~(
825..,
CS AD
ISFI
OBFI
BPI
TC'
•
SAO
AEN
'FC
SAO
AEN
'FC
ATN
~ ~~~2
:~:I
NRFD
NDAC
OAV
r
T/R1
0101
0108
T/R2
ClK
ca
-
'I'r
ATHO
~~~H
I
0 0 0,0,0.
r...
2142
'
I-07·00 'r-
~
::I
~
I,n
F
cs
r
AO
r--
S
[
I
1293
MODE 2
11rplllll
~ ~
2142
!~~an~!gg!~~np~~
MODE 3
!;!
SYC
CS
~~ZZ~~fA1ft1ft • • • n~n"l
8213
...5
c~:;wf;U3
~N
I
I
Ur-
cc ... cc
. - 11
COUNT
EO'
AS'
AS'
ABO
I:
J
'NT
O A O O - DREQ
OACKO >--< DACK
r"
HOLD
HLDA
AaT AD WA
~
AD
(q;g~!
GPl8
~
. .. ;
:c c
A15· AO
231324-10
Figure 11. DMA/lnterrupt GPIB Controller Block Diagram
3-107
inter
AP-66
ister. Note the two letter mnemonics to be used in later
discussions. The CPU must not write into the 8292
while IBF (Input Buffer .Full) is a one, as information
will be lost.
The application example will not use OMA or interrupts; however, the Figure 11 block diagram includes
these features for completeness.
The 8257-5 OMA chip can be used to transfer data
between the RAM and the 8291 Talker/Listener. This
mode allows a faster data rate on the GPIB and typically will depend on the 8291's EOS or EO! detection to
terminate the transfer. The 8259-5 interrupt controller
is used to vector the five possible interrupts for rapid
software handling of the various conqitions.
Direct Commands
Both the Interrupt Mask (1M) and the Error Mask
(EM) register may be directly written with the LSB of
the address bus (AD) a "0". The firmware uses the MSB
of the data written to differentiate between 1M and EM.
8292 COMMAND DESCRIPTION
LOAD INTERRUPT MASK
This section discusses each command in detail and re~
lates them to a particular GPIB activity. Recall that
although the 8041A has only two read registers and one
write register, through the magic of on-chip firmware
the 8292 appears to have six read registers and five
write registers. These are listed in Figure 12. Please see
the 8292 data sheet for detailed definitions of each reg-
PORT #
READ FROM 8292
INTERRUPT STATUS
I SYC IERRI SRO lEVi
This command loads the Interrupt Mask with 07-00.
Note that 07 must be a "I" and that interrupts are
enabled by a corresponding "I" bit in this register. IFC
interrupt cannot be masked off; however, when the
8292 is the System Controller, sending an ABORT
command will not cause an IFC interrupt.
X IIFCR I IBF
D7
OBF
WRITE TO 8292
COMMAND FIELD
69H
11 I
6SH
111SP11 TCI ISYCIOBFII IBFI I
lOp I C I
C
I
C
C
0
I SRO !
Do
INTERRUPT MASK
ERROR FLAG"
X
X IUSERI X I X ITOUTsITOUT2ITOUT1!
D7
Do
ERROR MASK
CONTROLLER STATUS"
ICSBsl CA I
1 0 1 0 IUSERI
I
6SH
101 D
0
1 0 1 0 1 D
TIMEOUT*
1
6SH
10 1 0
0
1 0 I
GPIB (BUS) STATUS·
1 REN 10AVI EOI I X I SYC 1 IFC I ANTI I SRO
EVENT COUNTER STATUS"
D
0
I
D I
D
0
0
I
10 1 0 I D 1
TIME OUT STATUS·
1
0
0
D
I
I
I
0
0
D
0
o 1 0 1TOUT41 TOUTs 1TOUT11
EVENT COUNTER"
6SH
X I X ISYCSI IFC I REN I SRO
6SH
I
0
0
0
0
D
"Note: These registers are accessed by a special
utility command.
Figure 12.8292 Registers
3-108
o
1
inter
AP-66
When the 8292 has completed the command, IBF will
become a "0" and will cause an interrupt if masked on.
LOAD ERROR MASK
This command loads the Error Mask with 07-00.
Note that 07 must be a zero and that interrupts are
enabled by a corresponding "I" bit in this register.
Utility Commands
These. commands are used to read or write the 8292
registers that are not directly accessible. All utility
commands are written with AO = I, 07 = 06 = 05
= 1,04 = 0.03-00 specify the particular command.
For writing into registers the general sequence is:
1) wait for IBF = 0 in Interrupt Status Register
2) write the appropriate command to the 8292,
3) write the desired register value to the 8292 with AO
= 1 with no other writes intervening,
4) wait for indication of completion from 8292 (IBF =
0).
For reading a register the general sequence is:
1) wait for IBF = 0 in Interrupt Status Register
2) write the appropriate command to the 8292
3) wait for a TCI (Task Complete I~terrupt)
4) Read the value of the accessed register from the 8292
with AO = O.
WEVC-Write to Event Counter
(Command = OE2H)
The byte written following this command will be loaded into the event counter register and event counter
status for byte counting. The internal counter is incremented on a high to low transition of the COUNT (TI)
input. In this application example NOAC is connected
to count. The counter is an 8 bit register and therefore
can count up to 256 bytes (writing 0 to the EC implies a
count of 256). If longer blocks are desired, the main
CPU must handle the interrupts every 256 counts and
carefully observe the timing constraints.
Because the counter has a frequency range from 0 to
133 kHz when using a 6 MHz crystal, this feature may
not be usable with all devices on the GPIB. The 8291
can easily transfer data at rates up to 250 kHz and even
faster with some tuning of the system. There is also a
500 ns minimum high time requirement for COUNT
which can potentially be violated by the 8291 in continuous acceptor handshake mode (i.e., TNOOVI +
TOVN02 - C = 350 + 350 = 700 max). When
cable delays are taken into consideration, this problem
will probably never occur.
WTOUT-Write to Time Out Register
(Command = OEIH)
The byte written following this command will be used
to determine the number of increments used for the
time out functions. Because the register is 8 bits, the
maximum time out is 256 time increments. This is
probably enough for most instruments on the GPIB but
is not enough for a manually stepped operation using a
GPIB logic analyzer like Ziatech's ZT488. Also, the
488 Standard does not set a lower limit on how long a
device may take to do each action. Therefore, any use
of a time out must be able to be overridden (this is a
good general design rule for service and debugging considerations).
The time out function is implemented in the 8292's
firmware and will not be an accurate time. The counter
counts backwards to zero from its initial value. The
function may be enabled/disabled by a bit in the Error
mask register. When the command is complete IBF will
be set to a "0" and will cause an interrupt if masked on.
REVC-Read Event Counter Status
(Command = OE3H)
This command transfers the content of the Event
Counter to the OBBOUT register. The firmware then
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value from the 8292 with
AO = O.
RINM-Read Interrupt Mask Register
(Command = OE5H)
This command transfers the content of the Interrupt
Mask register to the OBBOUT register. The firmware
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value.
RERM-Read Error Mask Register
(Command = OEAH)
This command transfers the content of the Error Mask
register to the OBBOUT register. The firmware sets
TCI = 1 and will cause an interrupt if masked on. The
CPU may then read the value.
RCST-Read Controller Status Register
(Command = OE6H)
3-109
Ap·66
This command transfers,the content of the Controller
Status register to the DBBOUT register. The firmware
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value.
Operation Commands. It is not meant to replace the
complete controller state diagram in the IEEE Standard.
RST-Reset (Command = OF2H)
RTOUT-Read Time Out Status Register
(Command = OE9H)
This command transfers the content of the Time Out
Status register to the DBBOUT register. The firmware
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value.
If this register is read while a time-out function is in
process, the value will be the time remaining before
time-out occurs. If it is read after a time-out, it will be
zero. If it is read when no time-out is in process, it will
be the last value reached when the previous timing occurred.
RBST-Read Bus Status Register
(Command = OE7H)
This command causes the firmware to read the GPIB
management lines, DAV and the SYC pin and place a
copy in DBBOUT. TCI is set to "I" and will cause an
interrupt if masked on. The CPU may read the value.
This command has the same effect as an external reset
applied to the chip's pin #4. The 8292's actions are:
1) All outputs go to their electrical high state. This
means that SPI, TCI, OBFI, IBFI, CLTH will be
TRUE and all other GPIB signals will be FALSE.
2) The 8292's firmware will cause the above mentioned
five signals to go FALSE after approximately 17.5
/ks (at 6 MHz).
3) These registers will be cleared: Interrupt Status, Interrupt Mask, Error Mask, Time Out, Event Counter, Error Flag.
4) If the 8292 is the System Controller (SYC is TRUE),
then IFC will be' sent TRUE for approximately
100 /ks and the Controller function will end up in
charge of the bus. If the 8292 is not the System Controller then it will end up in an Idle state.
5) TCI will not be set.
RERF-Read Error Flag Register
(Command = OE4H)
AST
sye
This command transfers the content of the Error Flag
register to the DBBOUT register. The firmware sets
TCI = 1 and will cause an interrupt if masked on. The
CPU may then read the value.
This register is also placed in DBBOUT by an lACK
command if ERR remains set. TCI is set to "I" in this
case also.
,..-:--------------,
I
I
RST+
---..
ABORT· 6ye
I
lACK-Interrupt Acknowledge
(Command = Al A2 A3 A4 I A5 1 1)
I
L ____
This command is used to acknowledge any combinations of the five SPI interrupts (AI-A5): SYC, ERR,
SRQ, EV, and IFCR. Each bitAI-A5 is an individual
acknowledgement to the corresponding bit in the Interrupt Status Register. The command clears SPI but it
will be set again if all of the pending interrupts were not
acknowledged.
If A2 (ERR) is "1", the Error Flag register is placed in
DBBOUT and TCI is set. The CPl) may then read the
Error Flag without issuing an RERF command.
....!Y~'!£O~A~L~
I
I
_____
--.J
231324-11
Figure 13.8292 Command Flowchart
RSTI-Reset Interrupts (Command = OF3)
This command clears all pending interrupts and error
flags. The 8292 will stop waiting for actions to occur
(e.g., waiting for ATN to go FALSE in a TCNTR command or waiting for the proper handshake state in a
TCSY command). TCI will not be set.
ABORT-Abort all operations and Clear Interface
(Command = OF9H)
Operation Commands
The following diagram (Figure 13) is an attempt to
show the interrelationships among the various 8292
If the 8292 is not the System Controller this command
acts like a NOP and flags a USER ERROR in the Error Flag Register. No TCI will occur.
3-110
intJ
AP-66
If the 8292 is the system Controller then IFC is set
TRUE for approximately 100 ,""S and the 8292 becomes
the Controller-in-Charge and asserts ATN. TCI will be
set, only if the 8292 was NOT the CIC.
sets ATN FALSE and TCI TRUE. This command is
used as part of the Send, Receive, Transfer and Serial
Poll System commands (see next section) to allow the
addressed talker to send data/status.
STCNI-Start Counter Interrupts
(Command = OFEH)
Enables the EV Counter Interrupt. TCI will not be set.
Note that the counter must be enabled by a OSEC command.
If the data transfer does not start within the specified
Time-Out, the 8292 sets TOUT2 TRUE in the Error
Flag Register and sets SPI (if enabled). The controller
continues waiting for a new command. The CPU must
decide to wait longer or to regain control and take corrective action.
SPCNI-Stop Counter Interrupts
(Command = OFOH)
GSEC-Go To Standby and Enable Counting
(Command = OF4H)
The 8292 will not generate an EV interrupt when the
counter reaches O. Note that the counter will continue
counting. TCI will not be set.
This command does the same things as GTSB but also
initializes the event counter to the value previously
stored in the Event Counter Register (default value is
256) and enables the counter. One may wire the count
input to NDAC to count bytes. When the counter
reaches zero, it sets EV (and SPI if enabled) in Interrupt Status and will set EV every 256 bytes thereafter.
Note that there is a potential loss of count information
if the CPU does not respond to the EV/SPI before another 256 bytes have been transferred. TCI will be set
at the end of the command.
SREM-Set Interface to Remote Control
(Command = OF8H)
If the 8292 is the System Controller, it will set REN
and TCI TRUE. Otherwise it only sets the User Error
Flag.
SLOC-Set Interface to Local Mode
(Command = OF7H)
TCSY-Take Control Synchronously
(Command = OFDH)
If the 8292 is the System Controller, it will set REN
FALSE and TCI TRUE. Otherwise, it only sets the
User Error Flag.
EXPP-Execute Parallel Poll
(Command = OF5H)
If not Controller-in-Charge, the 8292 will treat this as a
NOP and does not set TCI. If it is the Controller-inCharge then it sets lOY (EO! & ATN) TRUE and
generates a local DAV pulse (that never reaches the
GPIB because of gates in the 8293). If the 8291 is configured as a listener, it will capture the Parallel Poll
Response byte in its data register. TCI is not generated,
the CPU must detect the BI (Byte In) from the 8291.
The 8292 will be ready to accept another command
before the BI occurs; therefore the 8291's BI serves as a
task complete indication.
GTSB-Go To Standby (Command = OF6H)
If the 8292 is not the Controller-in-Charge, it will treat
this command as a NOP and does not set TCI TRUE.
Otherwise, it goes to Controller Standby State (CSBS),
If the 8292 is not in Standby, it treats this command as
a NOP and does not set TCI. Otherwise, it waits for the
proper handshake state and sets ATN TRUE. The 8292
will set· TOUT3 if the handshake never assumes the
correct state and will remain in this command until the
handshake is proper or a RSTI command is issued. If
the 8292 successfully takes control, it sets TCI TRUE.
This is the normal way to regain control at the end of a
Send, Receive, Transfer or Serial Poll System Command. If TCSY is not successful, then the controller
must try TCAS (see warning below).
TCAS-Take Control Asynchronously
(Command = OFCH)
If the 8292 is not in Standby, it treats this command as
a NOP and does not set TCI. Otherwise, it arbitrarily
sets ATN TRUE and ECI TRUE. Note that this action
may cause devices on the bus to lose a data byte or
cause them to interpret a data byte as a command byte.
Both Actions can result in anomalous behavior. TCAS
should be used only in emergencies. If TCAS fails, then
the System Controller will have to issue an ABORT to
clean things up.
3-111
inter
GlDL-Go to Idle (Command
AP-66
=
OFIH)
If the 8292 is not the Controller in Charge and Active,
then it treats this command as a NOP and does not set
TCI. Otherwise, it sets ATN FALSE, becomes Not
Controller in Charge, and sets TCI TRUE. This command is used as part of the Pass Control System Command.
In order to use polling with the 8292 one must enable
Tel but not connect the pin to.the CPU's interrupt pin.
TCI must be readable by some means. In'this application example it is connected to bit 1 port 6FH on the
ZT7488/18. In addition, the other three 8292 interrupt
lines and the 8291 interrupt;lre also on that port (SPIBit 2, IBFI-Bit 4, OBFI-Bit 3, 8291 INT-Bit 0).
These drivers assume that only primary addresses will
be used on the GPIB. To use secondary addresses, one
must modify the test for valid talk/listen addresses
(range macro) to include secondaries.
TCNTR-Take (Receive) Control
(Command = OFAR)
If the 8292 is not Idle, then it treats this command as a
NOP and does not set TCI. Otherwise, it waits for the
current Controller-in-Charge to set ATN FALSE. If
this does not occur within the specified Time Out, the
8292 sets TOUTl in the Error Flag Register and sets
SP! (if enabled). It will not proceed until ATN goes
false or it receives an RSTI command. Note that the
Controller in Charge must previously have sent this
controller (via the 8291's command pass through register) a Pass Control message. When ATN goes FALSE,
the 8292 sets CIC, ATN and TCI TRUE and becomes
Active.
SOFTWARE DRIVER OUTLINE
The set of system commands discussed below is shown
in Figure 14. These commands are implemented in software routines executed by the main CPU.
The following section assumes that the Controller is the
System Controller and will not Pass Control. This is a
valid assumption for 99 + % of all controllers. It also
assumes that no DMA or Interrupts will be used. SYC
(System Control Input) should not be changed after
Power-on in any system-it adds unnecessary complexity to the CPU's software.
3-112
INIT
INITIALIZATION
Talker I Listener
SEND
SEND DATA
RECV
RECEIVE DATA
XFER
TRANSFER DATA
Controller
TRIG
DCLR
SPOL
PPEN
PPDS
PPUN
PPOL
PCTL
RCTL
SRQD
GROUP EXECUTE TRIGGER
DEVICE CLEAR
SERIAL POLL
PARALLEL POLL ENABLE
PARALLEL POLL DISABLE
PARALLEL POLL UNCONFIGURE
PARALLEL POLL
PASS CONTROL
RECEIVE CONTROL
SERVICE REQUESTED
System Controller
REME REMOTE ENABLE
LOCL
LOCAL
IFCL
ABORT IINTERFACE CLEAR
Figure 14. Software Drive Routines
intJ
AP-66
Initialization
8292-Comes up in Controller Active State when SYC
is TRUE. The only initialization needed is to enable the
TCI interrupt mask. This is done by writing OAOH to
Port 68H.
8291-Disable both the major and minor addresses because the 8291 will never see the 8292's commands/addresses (refer to earlier hardware discussion). This is
done by writing 60H and OEOH to Port 66H.
Set internal counter to 3 MHz to match the clock input
coming from the 8085 by writing 23H to Port 65H.
High speed mode for the handshakes will not be used
here even though the hardware uses three-state drivers.
No interrupts will be enabled now. Each routine will
enable the ones it needs for ease of polling operation.
The INT bit may be read through Port 6FH. Clear
both interrupt mask registers.
Release the chip's initialization state by writing 0 to
Port 65H.
Set Address Mode to Talk-only by writing 80H to Port
64H.
INIT;
Enable-8292
Enable TCI
Enable-8291
Disable major address
Disable minor address
ton
Clock frequency
All interrupts off
Immediate execute pon
;Set up In. pins for Port 6FH
;Task complete must be on
;In controller usage, the 8291
;Is set to talk only and/or listen only
;Talk only is our rest state
;3 MHz in this ap note example
;Releases 8291 from init. state
Talker/Listener Routines
SEND DATA
SEND
This system command sends data from the CPU to one
or more devices. The data is usually a string of ASCII
characters, but may be binary or other forms as well.
The data is device-specific.
My Talk Address (MTA) must be output to satisfy the
GPIB requirement of only one talker at a time (any
other talker will stop when MTA goes out). The MTA
is not needed as far as the 8291 is concerned-it will be
put into talk-only mode (ton).
This routine assumes a non-null listener list in that it
always sends Univeral Unlisten. If it is desired to send
data to the listeners previously addressed, one could
add a check for a null list and not send UNL. Count
must be 255 or less due to an 8 bit register. This routine
also always uses an EOS character to terminate the
string output; this could easily be eliminated and rely
on the count. Items in brackets ( ) are optional and will
not be included in the actual code in Appendix A.
3-113
AP-66
SEND:
Output-to-8291 MTA, UNL
Put EOS into 8291
While 20H S; listener S; 3EH
output-to-8291 listener
Increment listen list pointer
Output-to-8292 GTSB
Enable-8291
Output EOI on EOS sent
If count < > 0 then
While not (end or count
0)
(could check tout 2 here)
Output-to-8291 data
Increment data buffer pointer
Decrement count
Output-to-8292 TCSY
(If toutS then take control async)
Enable 8291
No output EOI on EOS sent
Return
;We will talk, nobody ~isten
;End of str.ing compare character
;GPIB listen addresses are
:" space n thru • > n ASCII
:Address all listeners
;8292 stops asserting ATN, go to standby
:Send EOI along with EOS character
;Wait for EOS or end of count
;Optionally check for stuck bus-tout 2
:Output all data, one byte at a time
;8085 CREG will count for us
;8292 asserts ATN, take control sync •.
:If unable to take control sync.
:Restore 8291 to standard condition
231324-12
Figure 15. Flowchart for Receive Ending Conditions
3-114
inter
AP-66
CONTROLLER
8291,8292
LITN
"I"
eTLR
~
E:~;~.:
.,'(
DEVICE
...
y
:'LsfN~J
'.~ "2"
d
TALK
"R"
...
y..................
" " " - - - - -. . . . . .
,.
.:.
,'.
" ..
DEVICE
LITN
"+"
~~~
...
...
10"
: '), ".
....
TALK
"K"
DEVICE
: LSTNj
">" "
TALK
"""
231324-13
Figure 16. SEND to "1", "2", ">"; "ABCD"; EOS = "D"
RECEIVE DATA
RECV
This system command is used to input data from a
device. The data is typically a string of ASCII characters.
This routine is the dual of SEND. It assumes a new
talker will be specified, a count of less than 257, and an
EOS character to terminate the input. EO! received
will also terminate the input. Figure 15 shows the flow
chart for the RECV ending conditions. My Listen Address (MLA) is sent to keep the GPIB transactions
totally regular to facilitate analysis by a GPIB logic
analyzer like the Ziatech ZT488. Otherwise, the bus
would appear to have no listener even though the 8291
will be listening.
Note that although the count may go to zero before the
transmission ends, the talker will probably be left in a
strange state and may have to be cleared by the controller. The count ending of RECV is therefore used as an
error condition in most situations.
3-115
AP-66
RECV:
Put EOS into 8291
If' 40H ~ talker ~ 5EH then
Output-to-8291 talker
Increment talker pointer
Output-to-8291 UNL, MLA
Enable-8291
Holdof'f' on end
End on EOS received
lon, reset ton
Immediate execute pon
Output-to-8292 GTSB
While not (end or count
0
(or tout2»
Input-f'rom-8291 data
Increment data buf'f'er pointer
Decrement count
(If' count = 0 then error)
Output-to-8292 TCSY
(If' Tout3 then take control async.)
Enable-8291
No holdof'f' on end
No end on EOS received
ton, reset lon
Finish handshake
Immediate execute pon
Return error-indicator
;End of' string compare character
;GPIB talk addresses are
;n@" thru n II" ASCII
;Do this f'or consistency's sake
;Everyone except us stop listening
;Stop when EOS character is
;Detected by 8291
;Listen only (no talk)
;8292 stops asserting ATN, go to standby
;wait f'or EOS or EOI or end of' count
;optionally check f'or stuck bus-tout2
;input data, one byte at a time
;Use 8085 C register as counter
;Count should not occur bef'ore end
;8292 asserts ATN take control
;If' unable to take control sync.
;Put 8291 back as needed f'or
;Controller activity and
;Clear holdof'f' due to end
;Complete holdof'f' due to end, if' any
;Needed to reset lon
ea._.
CONTROLLER
CONTROLLER
12t1.12112
Ea
"r
CTLR
TALK
·A·
LaTH
"'"
~
DEVICE
LSTN
"f·
"2"
TALK
"A"
DEVICE
,
,.
TALK
.0"
t:~J
z.
"
~
"R"
TALK
"0"
DEVICE
II.
DEVICE
LSTN
CTI.R
~.
TALK
"II"
DEVICE
,.
DEVICE
LSTN
[:zJ
TALK
'!C"
TALK
"."
"I<"
DEVICE
DEVICE
LlTN
">"
LSTN
"A"
231324-15
TALK
"""
">"
15:1
231324-14
Figure 18. XFER from" II" to "1", "2", "+ ";
EOS = ODH
Figure 17. RECV from "R"; EOS = ODH
3-116
inter
AP-66
This is accomplished through the use of the 8291's continuous acceptor handshake mode while in listen-only.
TRANSFER DATA
XFER
This system command is used to transfer data from a
talker to one or more listeners where the controller
does not participate in the transfer of the ASCII data.
This routine assumes a device list that has the ASCII
talker address as the first byte and the string (one or
more) or ASCII listener addresses following. The EOS
character or an EOI will cause the controller to take
take control synchronously and thereby terminate the
transfer.
XFER:
Output-to-829l: Talker, UNL
While 20H S listen S 3EH
Output-to-829l: Listener
. Increment listen list pointer
Enable-829l
lon, no ton
Continuous AH mode
End on EOS received
Immediate execute PON
Put EOS into 8291
Output-to-8292: GTSB
Upon end (or tout2) then
Take control synchronously
Enable-829l
Finish handshake
Not continuous AH mode
Not END on EOS received
ton
Immediate execute pon
Return
;Send talk address and unlisten
;Send listen address
;Controller is pseudo listener
;Handshake but don't capture data
;Capture EOS as well as EOI
;Initialize the 8291
;Set up EOS character
;Go to standby
;8292 waits for EOS or EOI and then
;Regains control
;Go to Ready for Data
Controller
GROUP EXECUTE TRIGGER
TRIG
This system command causes a group execute trigger
(GET) to be sent to all devices on the listener list. The
intended use is to synchronize a number of instruments.
TRIG:
Output-to-829l UNL
While 20H S listener S 3EH
Output-to-829l Listener
Increment listen list pointer
Output-to-829l GET
Return
;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on any non-valid character
;Issue group execute trigger
3-117
infer
AP-66
CONTROLLER
CONTROLLER
8291.8292
LSTN,
"'"
R
8291.8292
LSTN
",to
TALK
"A"
\
"
DEVICE
~]
"
"0"
OEVICE
LSTN
"2"
DEVICE
ffi
V'
DEVICE
Gf]
TALK
"""
"2" ,
DEVICE
ffi
TALK
"0"
"1"
"TALK
"R"
"-
;>
TALK
"A"
'"
TALK
"1"
R
DEVICE
LSTN
TALK
"K"
TALK
"K"
"+"
DEVICE
DEVICE
LSTN
TALK
LSTN
">"
IIA"
">"
231324-16
TALK
"""
231324-17
Figure 19. TRIG "1", "+"
Figure 20. DCLR "1", "2"
DEVICE CLEAR
DCLR < Listener list>
This system command causes a device clear (SDC) to
be sent to all devices on the listener list. Note that this
is not intended to clear the GPIB interface of the device, but should clear the device-specific logic.
DCLR:
Output-to-829l UNL
While 20H ~ listener ~ 3EH
Output-to-829l Listener
Increment listen list pointer
Output-to-829l SDC
Return
;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on any non-valid character
;Selective device clear
SERIAL POLL
SPOL
This system command sequentially addresses the designated devices and receives one byte of status from each.
The bytes are stored in the buffer in the same order as
the devices appear on the talker list. MLA is output for
completeness.
3-118
AP·66
SPOL:
Output-to-8291 UNL, MLA, SPE
;Unlisten, we listen, serial poll enable
;Only one byte at serial poll
;Status wanted tram each talker
;Check tor valid transter
;Address each device to talk
;One at a time
While 40H S; talker S; 5 EH
Output-to-8291 talker
Increment talker list pointer
Enable-8291
lon, reset ton
Immediate execute pan
Output-to-8292 GTSB
Wait tor data in (BI)
Output-to-8292 TCSY
Input-trom-8291 data
Increment butter pointer
Enable 8291
ton, reset lon
Immediate execute pan
Output-to-8291 SPD
;Listen only to get status
;This resets ton
;Go to standby
;Serial poll status byte into 8291
;Take control synchronously
;Actually get data tram 8291
;Reset lon
;Send serial poll disable atter all
devices polled
Return
-,-
CONTROLLER
~
",..
CTLA
".
CONTROLLER
_,1m
T.wc
-A"
LSTH
"~
El
TALK
"A"
'"
DEVICE
DEVICE
~
LSTH
"1"
,
v
"~"
LSTH
TALK
'~"
"Q"
DEVICE
"v
l" ..... ,.
rT~~~
LSTH
"2"
t
v
"K"
DEVICE
LITH
","
DEVICE
..",.
19
V
TALK
"K"
DEVICE
1\
LSTH
TALK
"A"
"2"
"-
r··"~
TALK
"+"
~
.
DEVICE
LSTH
DEVICE
LSTN
,;::"
..
231324-18
TALK
"An
231324-19
Figure 21. SPOL "Q", "R", "K", " /\"
Figure 22. PPEN "2"; IP3P2P1
= 0111B
PARALLEL POLL ENABLE
PPEN
This system command configures one or more devices to respond to Parallel Poll, assuming they implement subset
PPl. The configuration information is stored in a buffer with one byte per device in the same order as
3-119
Ap·66
devices appear on the listener list. The configuration byte has the format XXXXIP3P2Pl as defined by the IEEE
Std. P3P2Pl indicates the bit # to be used for a response and I indicates the assertion value. See Sec'. 2.9.3.3 of the
Std. for more details.
.
PPEN:
Output-to-829l UNL
While 20H !>: Listener !>: 3EH
Output-to-829l listener
Output-to-829l PPC, (PPE or data)
Increment listener list pointer
Increment buffer pointer
Return
;Universal unlisten
;Check for valid listener
;Stop old listener, address new
;Send parallel poll info
;Point to next listener
;One configuration byte per.listener
PARALLEL POLL DISABLE
PPDS
This system command disables one or more devices from responding to a Parallel Poll by issuing a Parallel Poll
Disable (PPD). It does not deconfigure the devices.
PPDS:
Output-to-829l UNL
While 20H !>: Listener !>: 3EH
Output-to-829l listener
Increment listener list pointer
Output-to-829l PPC, PPD
Return
;Universal Unlisten
;Check for valid listener
;Address listener
;Disable PP on all listeners
CONTROLLER
1291,8212
LSTN
"'"
B
CONTROLLER
8291,8292
TALK
"A"
LSTH
"'"
"
"
"
"v
"v
DEVICE
~
"'"
R
TALK
"A"
"
,/
TALK
DEVICE
LSTH
TALK
"'"
."0"
DEVICE
"0"
DEVICE
0-
)
LSTH
TALK
"2"
"A"
'"
DEVICE
REJ
V
"k"
DEVICE
"v
TALK
">"
TALk
"A"
DEVICE
"TALK
RFl
LaTH
"2"
LSTH
,,+..
TALK
"k"
DEVICE
LSTN
"""
">"
. ,,"
TALK
231324-21
231324-20
Figure 23. PPDS "1", "+", ">"
Figure 24. PPUN
3·120
inter
AP-66
PARALLEL POLL UNCONFIGURE
PPUN
This system command deconfigures the Parallel Poll response of all devices by issuing a Parallel Poll Unconfigure
message.
PPUN:
;Unconfigure all parallel poll
Output-to-8291 PPU
Return
CONDUCT A PARALLEL POLL
PPOL
This system command causes the controller to conduct
a Parallel Poll on the GPIB for approximately 12.5
JLsec (at 6 MHz). Note that a parallel poll does not use
the handshake; therefore, to ensure that the device
knows whether or not its positive response was ob-
served by the controller, the CPU should explicitly acknowledge each device by a device-dependent data
stnng. Otherwise, the response bit will still be set when
the next Parallel Poll occurs. This command returns
one byte of status.
PPOL:
Enable-8291
lon
Immediate execute pon
Output-to-8292 EXPP
Upon BI
Input-from-8291 data
Enable-8291
ton
Immediate execute pon
Return Data (status byte)
;Listen only
;This resets ton
;Execute parallel poll
;When byte is input
;Read it
;Talk only
;This resets lon
PASS CONTROL
PCTL < talker>
This system command allows the controller to relinquish active control of the GPIB to another controller.
Normally some software protocol should already have
informed the controller to expect this, and under what
conditions to return control. The 8291 must be set up
to become a normal device and the CPU must handle
all commands passed through, otherwise control cannot be returned (see Receive Control below). The controller will go idle.
perL:
If 40H ~ talker ~ 5EH then
i f talker < > MTA then
output-to-829l talker, TCT
Enable-8291
not ton, not lon
Immediate execute pon
My device address, mode 1
Undefined command pass through
(Parallel Poll Configuration)
Output-to-8292 GIDL
Return
;Cannot pass control to myself
;Take control message to talker
;Set up 8291 as normal device
;Reset ton and lon
:Put device number in Register 6
;Required to receive control
;Optional use of PP
;Put controller in idle
3-121
Ap·66
CONTROLLER
CONTROLLER
1291,8282
8291.8292
~~_~N_,__~~
~~~
OEVICE
LSTN
TALK
"I"
"0"
V
OEVICE
"
V
TALK
"R"
LSTH
"2"
DEVICE
LSTH
C
TALK
"."
">"
V
TALK
"0"
DEVICE
LSTN
TALK
"2"
"R"
DEVICE
TALK
"K"
LSTN
"
:;
':
DEVICE
LSTN
LSTN
"1"
"
:,':::
1------+1
DEVICE
~
,~,1
TALk
"A"
LSTN
"'"
231324-22
Figure 25. PPOl
eTLR
~
'.TALK
,"C" \
DEVICE
LSTN
TALK
">"
"A"
CONTROLLER
231324-23
RECEIVE CONTROL
Figure 26. PCTl "C"
RCTL
This system command is used to get control back from
the current ~ontroller-in-charge if it has passed control
to this inactive controller. Most GPIB systems do not
use more than one controller and therefore would not
need this routine.
whereby the controller-in"charge sends a data message
to the soon-to-be-active controller. This message should
give the current state of the system, why control is being passed, what to do, and when to pass control back.
Most of these issues are beyond the scope of this Ap
Note.
To make passing and receiving control a manageable
event, the system designer should specify a protocol
3-122
intJ
AP-66
RCTL:
Upon CPT
If (command=TCT) then
If TA then
Enable-8291
Disable major device number
ton
Mask off interrupts
Immediate execute pon
Output-to-8292 TCNTR
Enable-8291
Valid command
Return valid
Else
Enable-8291
Invalid command
Else
Enable-8291
Invalid command
Return invalid
;Wait for command pass through bit in 8291
;If command is take control and
;We are talker addressed
;Controller will use ton and Ion
;Talk only mode
;Take (receive) control
;Release handshake
;Not talker addr. so TCT not for us
;Not TCT, so we don't care
8291,8292
lSTN
"I"
,
SYSTEM
CONTROLLER
8291.8292
CONTROLLER
,.. ~
LSTN
CTLR
"I"
B
.
TALK
"A"
Z
a:
I
DEVICE
~
---,/
DEVICE
LSTN
TALK
LSTN
TALK
"1"
"Q"
"1"
"Q"
LSTN
TALK
"2"
"R"
LSTN
"2"
LSTN
TALK
LSTN
TALK
"."
"K"
" "
"K"
TALK
LSTN
DEVICE
"v
"""'v -
DEVICE
DEVICE
DEVICE
LSTN
"#"
~
TALK
"C"
.
DEVICE
I'..
-V
TALK
"R"
LSTN
","
DEVICE
..,,"
">"
TALK
"1\"
231324-25
Figure 28. REME
CONTROLLER
231324-24
Figure 27. RCTL
3-123
AP-66
SERVICE REQUEST
SRQD
This system command is used to detect the occurrence of a Service Request on the GPIB. One or more devices may
assert SRQ simultaneously, and the CPU would normally conduct a Serial Poll after calling this routine to determine
which devices are SRQing.
SRQD:
If SRQ then
Output-to-8292 IACK.SRQ
Return SRQ
Else return no SRQ
;Test 92 status bit
;Acknowledge it
System Controller
REMOTE ENABLE
REME
This system command asserts the Remote Enable line (REN) on the GPIB. The devices will not go remote until they
are later addressed to listen by some other system command.
RENE:
Output-to-8292 SREM
Return
;8292 asserts remote enable line
LOCAL
LOCL
This system command deasserts the REN line on the GPIB. The devices will go local immediately.
LoeL:
Output-to-8292 SLOC
Return
;8292 stops asserting remote enable
3-124
intJ
AP-66
SYSTEM
CONTROLLER
SYSTEM
CONTROLLER
8291.8292
LSTN
"'"
R
TALK
LITH
"A"
"I"
I~
•
TALK
"."
"!!.
DEVICE
DEVICE
LSTH
"1"
TALK
"0"
LSTN
TALK
"A"
LSTH
TALK
"2"
"A"
TALK
LSTN
UK"
"+"
TALK
LSTN
DEVICE
DEVICE
LSTH
"2"
DEVICE
DEVICE
LSTN
"."
DEVICE
DEVICE
LSTH
">"
TALK
"0"
"'"
",.."
">"
TALK
",.."
231324-27
231324-26
Figure 30. IFCL
Figure 29. LOCL
INTERFACE CLEARI ABORT
IFCL
This system command asserts the GPIB's Interface
Clear (IFC) line for at least 100 microseconds. This
causes all interface logic in all devices to go to a known
state. Note that the device itself mayor may not be
reset, too. Most instruments do totally reset upon IFC.
Soine devices may require a DCLR as well as an IFCL
to be completely reset. Th~ (system) controller becomes
Controller-in-Charge.
IFCL:
Output-to-8292 ABORT
Return
;8292 asserts Interface Clear
;For 100 microseconds
INTERRUPTS AND DMA
CONSIDERATIONS
The previous sections have discussed in detail how to
use the 8291, 8292, 8293 chip set as a GPIB controlle~
with the software operating in a polling mode and using
programmed transfer of the data. This is the simplest
mode of use, but it ties up the microprocessor for the
duration of a GPIB transaction. If system design constraints do not allow this, then either Interrupts and/ot
DMA may be used :to free up processor cycles.
The 8291 and 8292 provide sufficient interrupts that
one may return to do other work while waiting for such
things as 8292 Task Completion, 8291 'Next Byte In,
8291 Last Byte Out, 8292 Service Request In, etc. The
only difficulty lies in integrating these various interrupt
sources and their matching routines into the overall
system's interrupt structure. This is highly situationspecific and is beyond the scope of this Ap Note.
The strategy to follow is to replace each .of the WAIT
routines. (see Appendix A) with a return to· the main
code, and. provide for the corresponding interrupt to
bring the control back to the next section .of GPIB
3-125
Ap·66
MAl!" CODE
INTERRUPT CODE
OPIB SUBROUTINE
USER:
SEND:
~
__~____~~______________~(WAITO)
~INT:
~
________
O~O?
(WAIT 0)
~INT: _ _ _ _- - - - - - - ........ =
___
~
--...
OPIBBO?-
~
OPIBBO?-
===
(WAIT 0)
_--
~INT:==
..
(WAIT T)
~ INT: OPIB B O : " - - - - - - - - = = ..
OPIB TCI?
-
ETC.
231324-28
Figure 31. GPIB Interrupt and ~o·Routlne Flow of Control
code. For example WAITO (Wait for Byte Out of
8~91) would be replaced by having the BO interrupt
enabled and storing the (return) address of the next
instruction in a known place. This co-routine structure
will then be activated by a BO interrupt. Figure 31
shows an example of the flow of control.
DMA is also useful in relieving the processor if the
average length of a data buffer is long enough to over·
come the extra time used to set up a DMA chip. This
decision will also be a function of a data rate of the
instrument. The best strategy i~ to use the DMA to
handle only the data buffer transfers on SEND and
RECV an4 to do all the addressing and control just lIS
shown in the driver descriptions.
be found on the GPIB. The Ziatech ZT488 GPIB analyzer is used to single step the bus to facilitate debugging the system. It also serves as a training/familiarization aid for newcomers to the bus.
This example will set up the function generator to output a specific waveform, frequency and amplitUde. It
will then tell the counter to Illeasure the frequency and
Request Service (SRQ) when cOmplete. The program
will then read in the data. The assembled source code
will be found at the end of Appendix A.
ZT14881'.
CONTROLLER
Another major reason for using a DMA chip is to increase the data rate and therefore increase the overall
transaction rate. In this case the limiting factor becomes the time used to do the addressing and controi'of
the GPIB using software like that in Appendix A. The
data transmission time becomes insignificant at DMA
speeds I,Inles~ extremely long buffers are used.
LSTN
·r
TALK
"A"
CT\.R
HP 532....
COUNTER
"'"
Refc;r tc;! Figure 11 for a typical D~A and interrupt
based design using the 8291, 8292, 8293. A system like
this ~an achieve a 2S0K byte transfer rate while under
DMA control.
'
, '"
HP_
L8TN
"I"
3~126
TALK
"Roo
ZT_
"
This s~tiori will present the code required to 'operate II
tyPical GPIB ittsirument set up as shown in Figure 32.
Thc·HP5328A universal 'count~r and the HP3325 function generator are typical of many GPIB'devices; however, there are a wide variety of software protocols to
'"Q" ,
'
FUNCTION
GENERATOR
"
APPLICATION EXAMPLE
TALK
LSTN
GPII ANAtYZER
"
"
231324-29
Figure 32. GPIB Example Configuration
inter
SEND
LSTN: "2", COUNT:
;SETS UP FUNCTION
;COUNT EQUAL TO #
;EOS CHARACTER IS
AP-66
15, EOS: ODH, DATA: ".FU1FR37KHAM2VO (CR)"
GEN. TO 37 KHZ SINE, 2 VOLTS PP
CHAR IN BUFFER
(CR)
ODH
CARRIAGE
=
=
SEND
LSTN: "1", COUNT: 6, EOS: "T" DATA: "PR4G7T"
;SETS UP COUNTER FOR P:INITIALIZE, F4: FREQ CHAN A
G7:0.1 HZ RESOLUTION, T:TRIGGER AND SRQ
;COUNT IS EQUAL TO # CHAR
WAIT FOR SRQ
SPOL TALK: "Q", DATA: STATUS 1
;CLEARS THE SRO_IN THIS EXAMPLE ONLY FREQ CTR ASSERTS SRQ
RECV TALK: "Q", COUNT: 17, EOS: OAH,
DATA:"+
37000.0E+O" (CR) (LF)
;GETS 17 BYTES OF DATA FROM COUNTER
;COUNT IS EXACT BUFFER LENGTH
;DATA SHOWN IS TPYICAL HP5328A READING THAT WOULD BE RECEIVED
CONCLUSION
This Application Note has shown a structured way to
view the IEEE 488 bus and has given typical code sequences to make the Intel 8291, 8292, and 8293's behave as a controller of the GPIB. There are other ways
to use the chip set, but whatever solution is chosen, it
must be integrated into the overall system software.
The ultimate reference for GPIB questions is the IEEE
Std 488 -1978 which is available from IEEE, 345 East
47th St., New York, NY, 10017. The ultimate reference
for the 8292 is the source listing for it (remember it's a
pre-programmed UPI-41A) which is available from INSITE, Intel Corp., 3065 Bowers Ave., Santa Clara, CA
95051.
3-127
AP-66
, APPENDIX ,A
ISIS-II 8980/8085 MACHO ASSEMBLER, V3.0
G PI R CON'rHOLLER SUBROU'rINES
LOC
OHJ
LINE
SOUI~CE
ST~TEMEN'r
1 $'rI'fLE ('GPIR CONTROLLER SUBRQU'UNES ')
2
3
GPIB CONTROLLER SUBROUTINES
4
5
~
for Intel 8291, 8292 on ZT 748"/18
8ert Forbes, Ziatech Corporation
7
24H~ Broad Street
San Luis Ohispo, CA, USA t))4Al
8
9
1000
19
11
12
13
14
15
H
17
18
19
20
21
22
General Definitions & Equates
8291 Control Values
;
PRT91
;
DIN
OQUT
23 ;
0A61
0061
0092
0001
9910
0980
0962
0064
0080
0049
30C9
0091
9064
9920
0992
0001
24 INTI
25 IN'f'U'
26
27
28
29
30
31
BOM,
81M
ENDMK
CPT
,
,
9023
; ,:or ZT748A/18 w/8085
;8291 Base Port
Reg ,,, Data in & Data out
EOU
PRT91+9 : 91 Data in reg
PRT.91+(~,
EQU
Reg
EQU
EQU'
EOU
EOU
EQU
EQU
;91 Data out ceq
I 1 Interrupt 1 Constants
PRT91+1
PRT91+1
02
01
19H
; JNT Req 1
; IN'r Mask Reg. 1
; 91 80 I~'rRP Mask
; 91 81 INTRP M.sk
;91 END INTRP M.sk
R~H
:91 command pass thru int ,,?it
Req 12 Interrupt 2
32 INT2
33
EQU
34
35 ADRMD
n 'rON
37 LON
38 TLON
39 MODEl
40
41
42 ADHST
43 EOIST
44 TA
45 LA
46
47
48 AUXMD
49 CLKRT
Reg t4 A.ddress "'ode Constants
80U
PRT91+4 ; 91 adr'tress mode reg ister •
EQU
89H
;91 talk only morle & not listen only
EOU
4~H
;91 listen only & not ton
EQU
Be0H
;91 talk & listen only
EQU
PH
;mode 1 addressing for device
,
,
0965
ORG
EQU
Reg 14
EQU
EOU
EQU
EOU
PRT9l+2
(Read)
Adoress Status Reqister
PRT91+4 ; reg '4
20H
2
1
; listener active
Reg IS
(Write) AuxilIary Mode Register
EQU
EOU
PRT91+5 ;91 Rluxillary mode reqister
23H
; 91 3 Mhz clock input
231324-30
3-128
inter
0~03
0~06
0080
0001
0002
0003
0004
0088
000F
0807
001'.0
~001
50 FNHSK
51 SDEOI
52 AXRA
006~
0060
00E0
0068
0068
aBAg
0068
0an
9982
0004
0068
3068
0069
56
57
58
59
60
~1
~4
00~8
0968
0~68
IH,G8
0068
80F0
00F1
00F2
00F3
00F4
90F5
00F6
00F7
00F8
00F9
00FA
00FC
00FD
00FE
Reg IS
EQU
PRT91+S
Reg 16
EOU
EOU
EOU
Address ~/l reg. constants
PRT9l+6
60H
;Disable major talker & listener
0E0H
iD! sable minor talker & listener
Reg t7
EQU
EOS
PRT91+7
8292
CONTROL VALUES
PRT92
EQU
PRT9l+8 ; 8292 Base Port ,
INTMR
EQU
EQU
PRT92+11J ,92 INTRP
ERRM
TOUTI
TOUT2
TOUT3
EVREG
TOREG
EOU
EQU
EQU
EQU
EQU
EQU
PRT92+0 ,92
n
,92
,Q2
02
04
,92
PRT92+ft ,92
PRT92+ft ,92
CM092
EQU
PRT92+l ,92 Command Req i ster
INTST
EVaIT
IBFBT
SRQBT
EQU
EQU
EQU
EQU
PRT92+l ,9~ Interrupt Status Reg
10A
;Event Counter Bit
02
; Input Ruffer Full Bi t
2~H
;Seq bi t
ERF!.G
CLRST
BUSST
EVCST
TOST
PRT92+0
PRT92+0
PRT92+0
PRT92+0
PRT92+8
,92
,92
,92
,92
,
,,,
EQU
EQU
EQU
EQU
EQU
8292
OPERATION COMMANDS
SPCNI
GIDL
RSET
RSTI
GSEC
EXPP
GTSB
SLOC
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
8F0H
8F1.H
ftF2H
0F3H
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FCH
0FDH
EDEOS
EOIS
VSC,~O
NVCMD
AXRB
,,
,,
65
66
67 ADR01
~8 DTDLI
59 DTDL2
70
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
0069
0018
8002
0020
CPTRG
54 HOEND
55 CAHCY
71
0067
0FH
97H
0A0H
01H
53 HOHSK
62
63
0365
CPTEN
EQU
EOU
EQIJ
EQU
EQU
EOU
EQU
EQU
EQU
EOU
EQU
EQU
93
94
95
95
97
98
99
!B0
101
102
103
104
105
106
107
lA8
189
110
111
112
113
114
115
116
117
,
,
,,,
,
EQSR
,
,INTM
,
,
,
SREM
ABORT
TeNTR
118 TCASY
119 TCSY
120 STCNI
121
122
,,
EQU
EQU
EQU
EQU
EQU
EQU
03
0~
8~H
1
?
3
4
8
,91
,91
,91
,91
,91
,91
,91
flninsh handshake command
senli EOI wi th next hyte
aux. req A pattern
hold off h"'nrlshake on all bytes
hoI" off handshake on ent1
continuous AH cycling
end on EOS r ece i ved
; 91 output EnI on EOS sent
,91 val id command pass throuqh
,91 lnval id command pass through
;Aux. r e 9· 8 pattern
;commanrl pass thru enable
(RelJd)
"A8H
BFEH
Character Reqister
r~ask
(CS7)
Reg
;TCI
Er ror Mask Reg
Time Out for Pass Control
'time Out for Standby
Time Out for Take Control Sync
Event Counter Pseudo Req
Time Out Pseudo Reg
Error Flaq Pseucto Reg
Controller Status Pseudo Reg
GPIB (Bus) Status Pseudo Reg
Event Counter Status Pseudo Req
;92 Time Out Status Pseudo Reg
;Stop Counter Interrupts
;Go to idle
;Reset
;Reset Interrupts
;Goto standby, enable countLng
;Execute parallel poll
;Goto standby
;Set ,local mode
;Set interface to remote
;Abort all operation, clear inter face
:Take control (Receive control)
;Take control asyncronously
;Take control syncronousl y
;Start counter interru!)ts
231324-31
3-129
intJ
AP~66
123
124 ,
00E1
0SE2
0BE3
09E4
00E5
08E~
BaE7
00E9
SBEA
\!Bsa
m~OUT
8292
UTILITY COMMA'IDS
BOU
EOU
EOU
EOU
EOU
0ElK
BE2H
BE3H
SE4H
BE5H
127
128
129
130
131
132
133
134
135
136
137
138
139
14S
WEVC
REVC
RERF
RINM
RCST
RSST
RTOUT
RERM
lACK
,
142
143
144
145
146
l47
l48
149
159
151
152
153
PRTF
TCIF
SPIF
08FF
ISFF
80F
EOU
EOU
BOU
EOU
EOU
EOU
,
,
GPIB
MDA
EQU
EOU
EOU
EOU
BOll
EQU
EOU
EOU
EOU
EOU
EQU
EQU
EQU
,
EOU
,Write to timeout req
,Wr 1te to event counter
,Read event counter status
, Read error flag reg
; Read interrupt mask reg
,Read controller status req
0E6H
EOU
EOU
0E7H
;Read OPIB Bus,. status req
EOU
BE9H
BEAH
;Read error mask reg
EOU
0BH
;Interrupt Acknowledqe
;Read timeout status req
PORT F BIT ASSIGNMENTS
141 ,
006F
0002
0094
0008
0010
~081
0901
0841
0921
0e3F
3098
0904
9018
0919
8005
0870
0060
8915
0009
MTA
MLA
1~4 UNL
155 GET
15~
SOC
157
158
159
H9
161
SPE
SPD
PPC
PPD
PPE
PPU
'fCT
1~2
1~3
164
H5 ,
PRT91+9FH
,ZT748A port 6F for interrupts
B2R
;Task complete interrupt
34H
,Special interrupt
08H
,92 Output (to CPU) Buffer full
10H
,92 Input (from CPU) Buffer empty
91H
,91 Int line (BO in this cos.)
~ESSAGES
(COMMANDS)
;My device address is 1
MDA+4RH ;My talk address is 1 ("AM)
1
MDA+20H
3FH
08
04H
18H
19H
95
70H
6BH
ISH
09
;My listen address is 1 (MrH)
;Universal un! isten
,Group Execute Triqqer
;Device Clear
;Serial poll enable
;Serial poll disable
;Parallel poll confiqure
;Parallel poll. disable
;Parallel poll disahle
;Parallel poll unconfiqured
;~rake control (pass control)
MACRO DEFINI'rIONS
1~6
1~7
168 ;
169 SETF
170
171
g~ ~AITO
174
175 WAITL:
176
177
178
179
IB~ ,
181 WAITI
182
183 WAIn:
184
185
18S
187
188 ,
189 WAITX
19B
191 WAITL:
192
193
194
195
MACRO
ORA
;Sets flags on A reqister
A
BND~
MACRO
LOCAL
Iii
ANI
JZ
;Wait for last 91 byte to be done
WAITL
I~Tl
BOM
WAITL
ENDM
MACRO
LOCAL
IN
MOV
ANI
JZ
WAITL
INTI
B,A
BIM
WAITL
ENDM
MACRO
LOCAL
IN
ANI
JNZ
;Get Inti status
;Check for bY,te out
; If not, try again
;until it is
;Wait for 91 byte to be input
;Get INTI status
,Save status in B
;Check for byte in
;If not, just try again
,until it Is
;Wait for 92 1 s Tel to 90 false
WAITL
PRTF
TCIF
WAITL
ENDM
231324-32
3-130
intJ
AP-66
196 WAIT'r
197
198 WAITI.:
199
200
201
~ACRO
[.OCA[.
IN
ANI
JZ
ENOM
WAITL
PRTF
TCIF
WAITL
MACRO
LOWE~,
;Get task complete int,etc.
;filllask it
,Walt for tlilsk to be complf'te
202
203 RANGE
UPPER, LABEL
204
;Checks for value in ranqe
;hranches to lahel if not
;In ranqe. Falls throuqh if
,lower (= ( (H) (I.) ) (= upper.
205
206
207
208
;Get next byte.
209
210
211
212
213
214
215
216 C[.RA
217
,
218
219
220
221
222
223
224
225
22"
227
1002
D3~8
1004 3E"a
1006 0361;
U~B 3EE0
103A 0361;
10~C ]g80
11"08 D3<4
1010 3~23
1~12 03"5
1014 AF
1015 0361
iB17 03"2
1019 031;5
1018 C9
A,M
LOWER
LABEL
UPPER+!
LABEL
~ACRO
XRA.
ENOM
A
;A XOR A .. 9
All of the followin!) routines have these common
assumptions about the state of the 8291 & q292 upon entry
to the routine and will exit the routinf' in an inentical state.
8291 :
BO is or has heen set,
All interrupts are maskeri off
'rON merle, not LA
228
No holdoffs in effect or enabled
229
230
231
232
233
234
235
23"
237
239
239
240
241
242
243
244
No holrtoffs waitinq for finish commC'lnri
8292:
8BBS:
ATN asserted (active cOl1troller)
note: RC'rL is an exception--- it expects
to not be active controller
Any previous task is completp & 92 is
ready to receive next command.
Pointer reqisters (DE,HL) enti one
heyond last leqal entry
•••••••• *********. ** ••• *. ft* ** •• *.*.*. 'II • • * •• 'II • • • • • 'II • • 'II • •
INITIALIZATION IWU'fINE
INPu'rs:
OUTPUTS:
CA['LS:
OES1'ROYS:
24~
1000 )gA0
MOV
CPI
JM
CPI
JP
ENeM
246
247
248
249
250
251
252
253
NIT:
None
None
None
A,l-'
A,DTDLI
o~'r
ADR01
254
.VI
ou'r
WI
A, 'rON
;'falk /)nl y morle
255
OU'f
25<;
.VI
OU'f
ADFlMO
A,CLJ(RT
,3 "HZ for rlelay timer
757
258
259.
A,J)TDL2
:Disahle minor talker/listener
ADR~l
AUX.D
CLI:{A
260
21;1
262
263
A,IN'rM
I""'rMR
, F1nahle Tel
,Output to 92's intr. mask req
;J)lsa~le major talker/listener
MVI
ou'r
.VI
,
X"'
ou'r
ou'r
A
OUT
AUXMJ)
IN'l'l
IN'f2
,A XOR A =0
;Disahle all 91 mi!sk hi ts
;Immertiate execute PO"
RE'r
264
2"5 I •• •••••• * ••• * •••• *.*** ••••• ** **** *** *.*-* ******* ••• ,. fr
26<;
2~7
268
SEND ROU'rINE
2~9
231324-33
3·131
intJ
191C 3E41
10lE 03'0
1020
1922
1924
1927
1029
1028
102C
102B
leU
1031
1034
1.3~
1039
1938
1030
1040
1941
1043
1044
0661
£602
CII20U
3B3F
0360
78
03'7
7F,
FE20
FA4710
,'E3F
F24710
DB~l
E602
CA39lA
7£
D3~0
23
C32EI0
1047 D861
1049 E602
1046 C1I4710
104£
1950
1052
1054
3EF6
D369
3E88
D365
105' DB6F
1058 E602
10511 C25'U
105D DBSF
le5~' E602
1061 CI\SD10
1064 79
1965
106'
1069
105A
18SC
87
CII8S10
V.
D3'.
sA
AP-66
27.
271
272
271
274
275
276
277
278
279
28.
281
2B2 END:
283
284
2R5+?UJ301 :
2B6+
2B7+
28B
289
290
291
292
293 S£~Dl:
294+
295+
29'+
297+
298+
299+
309+
381+
302+
303+
304
305+??0~02 :
306+
307+
308
309
31.
311
312
313 SEND2,
314+??0933:
315+
3H+
317
318
319
320
321
322
323
324+??.04,
325+
326+
327
328+119805:
329+
330.
331
332 ;
333 ;
334
335
336+
337
338 SEND3,
339
340
341
342
INPU'rs,
HL listener l~st pointer
DE data buffer pointer
C
OU'rPUTS:
CALLS,
DESTROYS:
MVI
ou'r
count-- 9 wi 11 cause no tiata to be sent
b F.OS ch"racter-- softwar.e detected
none
none
A, C, DE, HL,
A,MTA
OOUT
; Seni! ""fA to turn off any
;previous talker
INTI
;Get tntl status
;Check fOt" byte out
;If not, try aqain
WAITO
IN
ANI
BO~
JZ
??IHHH
~VI
ou'r
A,U"4L
OOUT
A,S
EOSR
RANGE
20H,3EH,SEND2
OUT
MOV
F
;Sen" universal unl lsten
Ito stop previous listeners
;Get EOS character
;Output it to B2ql
;while 1 istener .....
;Check next listen address
;Checks for value in ranqe
; hrilnches tl) label if not
; in range. Falls throWlh if
flower (= ( (H) (Ll ) <- upper.
;Get next byte.
MOV
CPI
A,M
CPI
28H
SEND2
3EA+l
JP
SEND?
JM
I~AITO
IN
ANI
IN'U
ROM
JZ
na002
MOV
A,M
ou'r
DOU'r
INX
H
SENDl
J~P
WAITO
IN
A~I
JZ
INT!
BOM
??0003
;Wait for previous listener sent
;Get tntI status
;Check for byte out
:If not, try again
:Get this listener
;Output to GPIB
;Increl'tent listener list pointer
:Loop till non-valid listener
:Enable' 91 en"'1n., conditions
;Wait for'lstn addr accepted
;Get IntI status
; Check for byte out
:If not, try aqain
;WAITO required for early versions
;of 8292 to avoid GTC;S before OAC
MVI
OUT
MVI
OUT
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
A,GTSB
CMD92
;Goto stan-ihy
;
A, AXRA+EOIS
,Sfmli Eor wit'"' EOS character
AUX~D
;Wait for Tel to qo false
PRTF
TCIF
??91~~4
PRTF
TClr
110805
delete next
~OV
A,C
SETF
ORII
A
JZ
WIIX
OUT
C~P
;Wait for Tel on GTSa
;Get tasle complete int,etc.
;Mask it
~Wait for task to be complete
instructions to make count of 0=25fi
;Get count
;Set flaqs
SEND~
J)
DOU'r
B
: If count=0, send no data
;Get data byte
;Output to GPIB
;'rest EO~
this is faster
land uses less code than usinq
;91 1 5 END or EOI bits
4
...
231324-34
3-132
inter
l~'D CA7~'19
1070
1972
1974
1977
1978
1079
197C
107F
U80
DB~l
AP·66
343
344 SEND":
Ef;~2
34~+
CA791B
13
eD
347+
348
349
350
HI
352 SF-ND5:
353
354
C2~910
C38SH
13
UD
JZ
IN
'ANI
.JZ
INX
DCR
J'Z
J~P
INX
OCR
;Get IntI statu9
;Cfleck for byte out
;If n...,t, try aqilin
; IncreJ1'lent buf fer pointer
;Decrement count
, If count ( > 0, qo send
; Else qo finish
; fo r consi steney
80.
710U06
D
C
SEND3
SEND6
D
C
10BB 3E~'D
108A D3'9
lA8C 3EB0
108E 0365
359 SENM:
360
361
362
363
3t:;4+??IHHJ8:
ou'r
CMD92
MVI
OUT
WAITX
IN
A,AXRA
3~5+
A~I
TCIF
3'~+
JNZ
',ojAIT'f
IN
ANI
JZ
RET
??0IHJ8
INn
BO",
1?0007
3<;~
3~7
DB6F
E602
CA9710
C9
368+??0I!HJ9:
369+
370+
371
372
373
374
375
376
377
378
379
H9
381
382
383
384
385
"'VI
A,TCSY
AUX'~D
10B0
1082
1084
19B7
10B9
D861
£'02
CAB01B
3E3F
DH0
10BS 0861
10BO E692
10BF CABB10
;'fhis ensureS that the stltnliard entry
;Get Intl status
,Check for byte out
ilf not, try a1ain
;assumptions for the next su~routine are met
;Take control syncronously
:Reset send Ear on EOS
;Wait for Tcr false
PRTF
PRT~'
TCIF
??0AA9
;Wait for Tel
:Get task complete int,etce
:Mask it
,Wait for task to
complete
"e
HL talker pointer
INPU'r:
D~
OU'rpUT:
CALLS:
DESTROYS:
RETURNS:
riata buffer pointer
count (max buffer size) B impli@s 21l1l
EOS character
Fills huffer pointerl at by nE
None
C
B
A, BC, DE,
HL, F
Azil no rmal
term inati oo--E05 -ietE'cted
A=4R Error--- count overrUn
A(4R or A)SEH f.:rror--- ba('l talk adr'lress
"'av
OU'f
R~NGE
A,B
;Get Ens character
EOSR
;Output it to 91
40H,SEH,HECV6
;Checks for value in range
;branches to label if not
lin ranqe. Falls throuqh if
39~+
10AD D360
10AF 23
,
RECEIVE ROUTINE
3Rt]
7£
FE40
FA3911
F£5F
F23911
qo finish
*************************************** •• ************************--*
387
388
389
390 ECV:
391
392
393+
394+
395+
10A2
10A3
10A5
10A8
10M
eos
WAI'ro
355+??0"97 :
IN
356+
ANI
357+
.JZ
1097
1099
109B
109E
,
,If char
INTI
1081 OB61
1983 E602
lABS CAB110
1U90 DBH
1092 £'92
1994 C2931B
=
SeN!)<;
WArrD
345+??""~":
397+
398+
399+
400+
491+
402+
403
,lower (- ( (H) (L) )
;Get next byte.
MOV
CPI
A,M
JM
CPI
JP
RECV6
(=
upper.
49H
5EH+l
RECVC,
;valid if
40H<~
talk 9 go back' wait
;Else set error indicator
;And qo take control
INX
o
OCR
/lVI
C
B,0
:Retreive status
;Cheek for 81
:If 81 then qd input data
;Else wait for last BI
; In loop
:Get data byte
;Store it in buffer
:Incr data pointer
;Deerement count, but i1nore it
,Set normal completion indicators
MVI
OUT
A, TCSY
:Take control synchronously
CM092
ANI
JNZ
IN
JMP
IN
STAX
WAITX
INTI
RECV3
DIN
D
,Wait for TCI=0
IN
PRTF
I'.NI
TCIF
??0U5
JNZ
(7 toy)
471
WAITT
;'..,ait for Tel ... l
472+??00H. IN
PRTF
:Get task complete int,etc.
473+
ANI
TCIF
,Mask it
474+
JZ
??39H)
;Wait for task to be complete
475
475 ; if timeout
is to be checked, the above WAITT should
477 ,be o~itted & the appropriate code to look for Tel or
478 ITOU't3 inse['ted, here.
4H
480
~VI
A, AXR.'
;Pattern to clear 91 E~D conditions
481
ou'r
AUXMD
;
482
MVI
A,TON
:This bit pattern alrea"y in "A"
483
OUT
ADRiI4D
:Output TON
484
MVI
A,FNHSK' :Finish handshake
485
OUT
AUXMO
,
486
487+
CLRA
XRA
488
ou'r
489
490 RECVS.
MOV
RET
A
AUXMO
A,B
:A XOR A =21
; l1'trned iate execute POIIJ-Reset
:Get completion character
LO~
231324-36
3-134
inter
AP-66
491 ,
492 I
* * .. It ...... * It It """.It It It .... *.It .1t ...... It ...................... * *.It" It. * * *••• It • • • • *
493 ,
XFER
494 ,
495 ,
49~ ,INPU'fS:
497
498 ;OU'fPUTS:
499 ,CALLS:
508 ,DESTROYS:
501 ,RETURNS:
502
5~3
,
,
504 ,NOTE:
50S
506
507
113A
1138
1130
1140
1142
1145
1147
7E
FE40
FABB11
FE5F
F28B11
0350
23
1148
114A
114C
114F
1151
0861
£602
CA4B11
)E3F
0360
1153
1154
1156
1159
115B
7E
FE20
FA6Cll
FE3F
F26C11
11SE
1160
1162
1165
1166
1168
1169
0861
E602
CA5Ell
7E
0360
23
C35311
116C
116E
1178
1173
1175
1177
1179
OB61
E602
CA6C11
3E87
0365
3E48
0364
117B
117C
117£
117F
1181
1183
AF
0365
78
0367
3EF6
0369
~OU'rINE
HL nevice 11st pointer
B EOS character
None
None
A, HL, F
A-a
normal, A ( )
{!J
bat1 talker
XFER will not work 1 £ the talker
uses EOI to terminate the transfer.
Intel will be making hardware
modifications to tho 8291 that will
~08
correct this prohlem. Until that time,
509 ,
5U ,
511 XFER,
!H2+
513+
514+
515+
516+
517+
518+
only EO'; may be used without possible
loss of the last data byte transfered.
4AH, SEH, XFER4
,Check for val id talker
,Cheeks for value in ranqe
;branches to label if not
,In ranqe. Falls throu'lh if
:lower (a ( (H) (L) ) ( . upper.
;Get next byte.
RANGE
MOV
A,M
CPI
4RH
JM
XFER4
5EH+l
XFER4
DOUT
~19+
520+
521+
522
523
524
525+710917:
526+
527+
528
529
530 XFER1:
531+
532+
533+
534+
535+
536+
537+
538+
539+
548+
CPI
,TP
OUT
INX
I.vAI'rO
IN
ANI
JZ
~VI
H
;Send it to GPIB
lIner pointer
INTl
BOM
?7M17
A,UNL
;Get IntI status
;Check for byte out
;If not, try again
;Universal unllsten
OUT
RANGE
OOUT
MOV
A,M
2BH, 3EH,XFE~2
;Check for valid listener
;Checks for value in ranqe
; branches to label 1 f not
,In range. Falls through If
;lower
(a
(
CH) (L)
) (- upoer.
;Get next byte.
CPI
20H
JM
XFER2
3EH+l
XFER2
CPI
JP
WAITO
541
542+170018:
IN
ANI
543+
544+
JZ
545
~OV
546
OU'f
547
INX
548
JMP
549 XFER2: WAITO
559+718019:
IN
ANI
551+
552+
JZ
553
"IVI
554
OUT
555
"'VI
556
OUT
557
CLRA
558+
XRA
559
OU'f
560
~OV
INT1
BOM
710018
A,M
DOUT
;Get IntI status
;Check for byte out
IIf not, try again
;Get 1 i stener
XFER1
;Iner pointer
;Loop until non-valId listener
INTI
;Get IntI status
BOM
,Check for byte out
,If not, try again
; tnv! sible han<1shake
;Continuous "H mode
;Listen only
H
?1"019
A., A.XRA+CAHCY+EOEOS
AUX~D
AiLON
ADR~D
A
AUX~O
A,B
EOSR
5~1
ou'r
562
563
MVI
A.,GTSB
OU'f
CMD92
;A XOR A .B
I Immed. XEQ PON
;Get EOS
,Output I t to ql
;Go to standby
231324-37
3·135
inter
AP-66
554
11B~
OB~F
11B7 E~A2
11B9 C28511
11BC
118E
1190
1193
1195
1197
119A
119C
DB6F
E6A2
CA8C11
0861
E~10
CM311
3EFO
03~9
119E OB5F
11M E6n
111'.2 C29El1
111'.5
111'.7
111'.9
111'.C
111'.E
118A
1182
1184
11B6
nB6F
E602
C1'.I'.511
3E80
0365
3E03
0365
3E80
03~4
11B8 AF
11B9 0365
11BB C9
5~5+??A02"':
556+
567+
568
5';9+119321 :
570+
571+
572 XFER3:
573
574
575
57.;
517
578+110"22:
579+
580+
581
582+710023:
583+
584+
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
IN
ANI
.JZ
MVI
otJ'r
PRTF
TCIF
??""2f1
;Wait for TCS
PRTF
TCIF
170021
INTI
ENDMK
XFER3
;Get task cnmplete int,etc.
;Mask it
;Wait for task to be complete
;Get END status ">1 t
A,TCSY
;'rake control syncronously
;Mask it
C~D92
WAI'rx
I~
ANI
JNZ
,WAITT
IN
ANI
JZ
PRTF
TCIF
710322
PRTF
Tcn'
??APl23
;Wait for TCI
;Get task complete int,etc.
;Mask it
;Wait for task to be complete
;Not cont Ali 0 rENO on EOS
5~5
"VI
A,AXRA
586
ou'r
AUXNlD
587
MVI
A, FNHSK ;Finish handshake
588
ou'r
AUX~O
589
~VI
A,TON
;Talk only
590
ou'r
ADRMn
591
CLRA
;Normal return A=A
592+
XRI'.
;A XOR A =9
593
OUT
I Immed iate XEO PON
594 XFr<4:
RET
595 ;
596 ; ***************** *******.*********** ***************
597
598
599
T~ IGGER ROUTINE
600
601 ;
602 ;INPu'rs:
HL listener list pointer
603 ;OUTPU'fS:
None
604 ;CALLS:
None
605 ; DESTROYS:
A, HL, F
~06
11BC 3E3F
llBE 03~0
607 ;
60B TRIG:
609
610 TRIGl:
511+
rH2+
MVI
ou'r
RANGE
~13+
614+
615+
1,lC0
11Cl
11C3
11CG
11C8
7E
FE20
FA0911
FE3F
F20911
l1ca
11CO
11CF
1102
1103
1105
1106
0861
E602
CACS11
7E
0360
23
C3CUI
~H+
617+
618+
619+
620+
621
~22+??0A24:
623+
624+
625
~26
627
628
~29
1109
110B
1100
11E0
11E2
OB61
E002
CA0911
3E08
0360
11E4 OB,l
11E6 E602
TRIG2:
630+1?0A25:
631+
632+
633
634
635
63 6+??0A26:
637+
MOV
CPI
JM
CPI
JP
WI'.ITO
IN
A"I
JZ
~OV
A,UNL
2~H
TRIG2
3EH+l
TRIG2
IN'rl
BOM
110324
A,M
OOUT
ou'r
INX
H
JMP
TRIGI
WAITO
IN
ANI
.JZ
,WI
OUT
;
:Send universal unlisten
20a,3EH,TRIG2
;Check for val in listen
;Checks for value in ranqe
;branches to label if not
: in range. Falls through if
; lower (== ( (H) (l) ) (- upper.
;Get next byte.
A,M
DOUT
IN'fl
ROM
710925
A,GET
DOUT
;wait for U"'IL to finish
;Get Intl status
;Check for byte out
;If not, try a'lain
:Get listener
;Sen~ Listener to GPIB
;Incr. pointer
;Loop until non-valid char
;wait fr')r last listen to finish
;Get tnt I st~tus
;Check for byte out
;If not, try aqain
;Sen,; qroup execute trifJqer
Ito all addresser! li1l>teners
\~AITO
IN
ANI
INTI
80M
;Get IntI status
;Check for byte out
3-136
231324-38
inter
11E8 CAE411
11EB C9
AP-66
638+
639
641 ,
641 ;
~!~
644
645
646
647
648
649
~50
11EC 3E3F
11EE 03~0
11F0 7E
UFl FE20
11F3 FA0912
11F6 FE3F
11F8 F20912
11FB
liFO
11FF
1202
1203
1205
1206
0861
E602
CAFBll
7E
0360
23
C3F011
1209
120B
1200
1210
1212
08~1
E602
CA0912
3E04
0360
1214
1216
1218
121B
D861
E602
CA1412
C9
121C 3E3F
121E 0360
1220
1222
1224
1227
1229
OB61
E602
CA2012
3E21
0360
1228
1220
122F
1232
1234
OB61
E602
CA2B12
3E18
0360
1236 OB61
JZ
;If not,
t~y
again
.-.* ....-..... _.. _._.-.-._. _____ .*._._ .. _.
;OEVICE CLEAR ROU'rINE
,
,
,INPUTS:
,OUTPUT:
,CALLS:
,DESTROYS:
,
DCLR:
MVI
OUT
DCLRl:
RANGE
651
652
653
654
655+
656+
657+
658+
659+
669+
661+
662+
~63+
664+
665
666+110027:
667+
668+
669
670
671
672
178826
RET
HL listener pointer
None
None
A, HL, F
... ,UNL
DQUT
20H, 3EH, OCLR2
,Checks for value In range
,branches to label if not
;In range. '"11s through If
,lower
<= (
(H) IL)
)
<-
upper.
;Get next byte.
MOV
CPI
JM
CPI
JP
WAITO
IN
ANI
JZ
"OV
OUT
INX
A,M
208
OCLR2
3EH+1
DCLR2
INTI
80M
110027
A,M
OOUT
;Get IntI status
;Check for byte out
;If not, try again
;Send listener to GPIS
H
JMP
OCLR1
673 OCLR2, WAITO
674+110028:
IN
INTI
ANI
675+
BOM
676+
JZ
110028
677
MVI
A,SOC
678
OUT
OOUT
679
WAITO
689+110029:
IN
INTI
681+
ANI
BOM
682+
JZ
170029
683
RET
684
685 ;; _._---_.-._.-._.
;Get IntI status
;Check for byte out
,If not, try aqain
;Sen~ device clear
;To all addressed listeners
;Get IntI status
;Check for byte out
;If not, try again
_._-*-.-•• __ .-__________ *_._. _____ _
686
687
SERIAL POLL ROUTINE
688 ,
689 ; INPUTS:
HL talker list pointer
690 ,
DE status buffer pointer
691 ,OUTPUTS:
Fills buffer pointed to by DE
692 ,CALLS:
None
1593 ; DESTROYS:
A., BC, DE, HL, F
694 ,
695 SPOL:
MVI
A,U~L
;Universal unlisten
696
DQUT
OUT
697
WAITO
698+770030:
IN
INT1
;Cet IntI status
699+
ANI
BOM
;Check for byte out
700+
JZ
11H03a ;If not, try again
701
MVI
A,MLA
;My listen address
702
OUT
DOUT
703
WAITO
704+110031:
IN
INT1
JGat IntI status
705+
ANI
80M
;Check for byte out
706+
JZ
110031 ;If not, try again
707
MVI
A,SPE
;Serial poll enable
708
OUT
DOUT
;To be forma} about 1 t
709
WAITO
7la+110032:
INTI
IN
;Get IntI status
<
231324-39
3-137
inter
1238 Ef')M2
123A CA3~12
1230
123E
1240
1243
124~
1248
1249
1248
124C
124E
7F.
FE40
FA9412
FE5F
F29412
7E
0360
23
3E40
D364
1250 0861
1252 E602
1254 CA5012
1257
1258
125.0.
125C
AF
0365
3EF6
0369
125E 086F
1260 E602
1262 C25El2
1265 DB6F
12~7
E~02
12~9
CM512
12SC DBfil
12fiE 47
12~F
Efi~1
1271 CA6C12
1274 3EFO
03S9
127~
1278 OBfiF
127A E602
127C C27812
127F
1281
1283
1286
1288
1289
128A
128C
D8fiF
E6n
CA7F12
OB6A
12
13
3E80
D3~4
128£ AF
128F 0365
1291 C33D12
1294 3U9
1296 0360
1298 0861
129A £602
129C CA9812
129F AF
12A0 D3fi5
12A2 C9
Ap·66
711+
712+
713 SPOLl:
714+
715+
71tH
717+
71R+
719+
720+
721+
722+
723+
724
725
726
727
728
729
730+1?0033:
731+
732+
733
734+
735
736
737
738
739+110034:
740+
741+
742
743+1100]5:
744+
745+
746
747+??a~35:
MI
JZ
RANGE
MOV
CPI
,'1'1
CPI
JP
,~OV
ou'r
INX
",VI
ou'r
WAITO
IN
ANI
JZ
BO~
;Check for byte out
:If not, try aqain
:Check for val id talker
:Checks for value In ran'1e
; hranches to la"el if not
1 in ranqe. Falls through I f
; lower (= ( (H) (L) ) (a upper ..
tGet next "yte.
1700]2
4OJ!-I,SF.H,SPOL2
h,M
40H
SPOL2
5EH+l
SPOL2
A,M
oou'r
;Get talker
; Sen" to GPIB
;Iner tl'tlker list pointer
;Listen only
H
A,LO'J
AORMO
;Wa 1t fo r tal k ar:tdress to complete
;Get IntI status
;Check for byte out
;If not, try again
;Pattern for imme-1iate XEQ PON
IN'rl
80",
710033
CLRA
XRA
ou'r
MVI
ou'r
WAITX
IN
ANI
JNZ
I.AITT
IN
ANI
JZ
A
AUXMO
A,GTSB
CMD92
;A XOR A ."
;Goto standhy
;Wait for TCI false
PRTF
TCIF
110~34
PRTF
TCIF
??0~35
WAIn
IN
MOV
ANI
;Wait for TCI
,Get task complete int,etc.
;Mask it
;Wait for task to he complete
;Wait for status byte input
;Get tNTI st,IJtus
I Save sta tus in B
,Cheek for byte in
,If not, just try aqain
,Take, control sync
INn
748+
B"A
749+
BIM
750+
JZ
17003fi
751
A,TCSY
MVI
752
ou'r
CMD92
753
14AITX
;Wait for Tel false
754+110037: IN
PRTF
755+
ANI
TCIF
756+
JNZ
110037
757
I'IAI1"r
;Wait for TCI
758+110338: IN
PRTF
;Get task complete int,ete.
759+
ANI
TCIF
JMask it
7fi0+
JZ
170038 ;wait for task to be complete
761
IN
DIN
;Get serial poll status hyte
762
STAX
D
;Store it in buffer
763
INX
0
;Incr pointer
764
MVI
~,TON
,Talk only for controller
765
ou'r
ADRMD
7fifi
CLRA
767+
XRA
A
;A XOR A =0
768
ou'r
AUXMO
; Immed i ta te xeQ PON
769
,CLR LA
779
JMP
SPOLI
,00 on to next deviee on'list
771
172 SPOL2: MVI
A,SPO
,Serial poll disable
773
OUT
OOUT
JWe know 80 we s se t (WAITO above)
774
WAnO
775+110039:
IN
INTI
;Get IntI status
776+
ANI
BOM
;Check for byte out
777+
JZ
110A39 ,If not, try a1ain
778
CLRA
779+
XRA
A
;A XOR A =~
780
OUT
AUX,~D
,Immediate XEQ PON to clear LA.
781
RET
782
783 ; ** * * ** ******* *** *. * ** ** *** ** ** ** ** * ***** ****. ** * ****."
784
<
,
231324-40
3-138.
intJ
AP-66
785 ,
PARALLEL POLL ENABLE ROUTINE
~:j ; INPUTS:
12A3 3£3F
12A5 D368
12A7
12A8
12AA
12AO
12AF
7E
FE28
FA0812
PE3F
F20812
12B2
1284
1286
1289
128A
DB61
Efi82
CAB212
7E
128C
12BE
12Cn
12C3
12C5
0861
EfiB2
CABC12
3E05
DH8
03~B
12C7
12C9
12Cd
12CE
12CF
1201
1203
1204
1205
OB61
D3fiO
23
13
C3A712
1208
120A
120C
12DF
OBfi1
E6B2
CA0812
C9
E6~2
CAC712
1A
'fin
788 ,
789 ,OUTPu'rs:
790 ,CALLS:
791 ,DESTROYS:
792 ,
793 ,
794 PPEN:
MVI
795
OUT
796 PPEN1:
RANGE
797+
79B+
799+
80A+
8Bl+
802+
MOV
803+
CPI
834+
J~
8a5+
CPI
886+
JP
837
WAITO
888+??8148 :
IN
809+
A'II
8t1+
JZ
811
MOV
HL listener list pointer
DE confil1uration byte pointer
None
1II0ne
A, D!, HL, F
;Universal unlisten
A,UlIIL
COUT
,Cheek for valid listener
,Checks for value in ranqe
2"H,3!H,PPE~2
,branches to label if not
lin ran~e. Falls throu1h if
,lower (m ( (HI (LI I (- upper.
,Get next byte.
A,M
28H
PP£N2
3EH+1
PPEN2
,Valid wait 91 dau out req
,Get IntI status
;Cheek for byte out
,If not, try aqatn
;Get listener
INT1
BOM
??0B4A
A,M
812
OUT
OOUT
813
'~AITO
814+??8041:
IN
INT1
;Get IntI status
815+
A'II
80M
;Check for byte out
816+
JZ
??B941
,If not, try aqaIn
817
MVI
A,PPC
,parallel poll Clonfiqure
818
ou'r
COUT
819
WAITO
821+??8842 :
IN
INT1
,Get Int! status
821+
80..
MI
,Check for byte out
822+
.JZ
??A942 ,If not, try a~aln
823
LOAX
D
,Get matching confiquration byte
B24
ORI
PPE
,Merge wi th parallel poll enable
825
DOUT
ou'r
826
INX
H
,Incl" pointers
827
INX
o
828
JMP
PPEN1
;Loop until inyali~ listener char
829 PPEN2: WAITO
830+??0A43:
IN
INT1
,Get IntI status
831+
ANI
BO~
;Check for byte out
832+
JZ
??8843 ;If not, try .98in
833
RET
834 ,
835 ,PARALLEL POLL DISABLE ROU'rINE
836
837 ,INPUTS:
HL listener list pointer
838 ,OUTPUTS:
None
839 ,CALLS:
None
,
840 ,DESTROYS:
l2EB 3E3F
12E2 0358
12E4
12E5
12E7
12£11
12EC
7E
FE28
FAF012
F£3F
'2F012
12EF DBfi1
12F1 Efi02
12F3 CAEF12
841
842 PPDS:
843
844 PPOS1:
845+
84H
847+
848+
849+
858+
851+
852+
853+
854+
855
85fi+??8844:
857+
858+
A,
HL,
F
;Universal unllsten
!lVI
A,U~L
ou'r
DOUT
RANG!
2BH,3BH,PPOS2
MOV
,Check for valid listener
,Checks for value in ranqe
;branches to label it not
rln ran,.e. Falls throuqh if
; lower <= ( (H) eLl ) <- upper.
;Get next byte.
JP
A,M
20R
PPDS2
3EH+l
PPOS2
WAITO
IN
ANI
BO'4
JZ
??IA44
CPI
J~
CPI
IN'rl
;Get IntI status
,Check for byte out
,If not, try aqatn
231324-41
3-139
inter
12F6 7E
12F7 D3~9
12F9 23
12PA C3E412
12FD D8~1
12FF F.~B2
1301 CAPD12
1304 3E05
130~
D3~0
1308
130A
130C
130P
1311
CA9813
3B7a
DH9
D861
1313
1315
1317
131A
DB61
£682
CA1313
C9
E~02
131B 3E15
13lD D360
13lF
1321
1323
1326
OB61
£602
CA1F13
C9
AP-66
~59
~OV
8~0
8~1
8~2
OUT
INX
H
lIner pointer
J~P
PPOS1
WAITO
IN
ANI
;Loop until Invalid 1 i stener
INTI
80'1
JZ
??8A4~
'4VI
OU'f
,Get IntI status
,Check for hyte out
;If not, try aqain
;Parallel poll confiqure
DOU'f
863 PPDS2:
8~4+71U45:
8~5,,"
85~+
8~7
8~8
8~9
A,M
DOUT
A,PPC
;Get llstener
WAlTa
IN
870+71804" :
INn
;Get IntI status
871+
A'II
801'1
,Check for byte out
872+
JZ
??"~Ufi
;If not', try aqain
873
"IVI
A,PPD
;Parallel poll disable
874
DOUT
ou'r
875
WAITO
R76+??B047:
INTI
IN
,Get Intl status
877+
80"!
ANI
;Check for byte out
878+
JZ
770047 ;If not, try aq.!n
879
RET
88B
881 ,
PARALLEL POLL UNCONPIG,UR£ ALL ROUTINE
882 ,
883 I
884 ; INPUTS:
None
885 ;OUTPUTS:
None
886 ,CALLS.
None
887 ,DESTROYS:
A, P
888 ;
889 PPUN,
A,PPU'
,Parallel poll unconfiqure
"VI
898
DOU'f
ou'r
891
WAITO
892+178048:
IN
INTI
;Get IntI status
893+
ANI
80M
;Check for byte out
894+
JZ
??U48 ;If not, try a~ain
895
RET
89~ ,
,
897 ; **************************************** *.********
: : : ;CONDUCT A PARALLEL POLL
980
1327 3U0
1329 D364
1328
132C
132£
1338
AF
D365
3EF5
DH9
1332
1334
1335
1337
133A
133C
DBH
47
E6Bl
CA3213
3EBa
D364
133£ AF
133F D3~5
1341 D8~0
1343 C9
981 ,
982 ;INPU'fS:
Nlone
983 ;OUTPUTS:
None
904 ,CALLS:
None
985 ,DESTROYS:
A, B, ..
986 ,RETURNS:
A= parallel poll status byte
987 ;
908 PPOL:
",VI
A,LON
;Listen ?nly
909
OU'f
AOR'ID
918
CLRA
,Immediate XEO PON
911+
XRA
,A XOR A -g
A
912
OUT
AUXMD
,Reset TO,..
913
A,EXPP ,Execute parallel poll
"'VI
914
OUT
CMD92
915
WAITI
;Wait for completlon= Bl on 91
916+??U49: IN
INT1
,Get INTI status
917+
MOV
B,A
;Save status in B
918+
ANI
9I"!
,Check for byte in
919+
JZ
??8349 :If not, iust try aqain
928
>lVI
,Talk only
A, TO'"
921
OUT
ADRMD
922
CLRA
,Iromed iate XEQ POl'
923+
XRA
A
,A XOR A ."
924
OU'f
AUX"ID
,Reset LO'"
925
IN
DIN
;Get PP byte
926
RET
927
928 *************.********************************
929 PASS CONTROL ROU'rINE
938
931 INPUTS:
HL pointer to talker
932 OU'fPUTS:
None
3·140
231324-42
inter
1344
1345
1347
134A
134C
134F
1351
1354
7E
FE40
FIIBA13
FE5F
F28AD
F£41
CA8A13
D3~0
1356 DB61
1358 EGe 1
135A CA5~13
1350 3£09
135F D3~0
1361 DB61
13n3 E602
13~5 CM113
1368 3£01
13nA 0364
13SC AF
1360 0365
3E01
1371 0366
1373 3EAl
1375 DH5
13~F
1377 3EFl
1379 D3fi9
137B
DB~F
1370 £602
137F C27813
1382
1384
138S
1389
138A
138B
1380
138F
1392
1394
D86F
E602
CA8213
23
C9
DB~l
E680
CACF13
OB65
F£09
AP-66
933 ;CALLS:
None
934 ; DESTROVS:
A, HL, f'
935 PCTL:
RANGE
40H,5EH,PCTLl
;Is it a valid talker
936+
;Checks for value in ran~e
937+
; hrltncheS to la':Jel if not
938+
:In ranqe. Falls throuqh if
939+
flower (= ( (H) (L) ) (= upper.
940+
;Get next byte.
941+
MOV
A,M
942+
CPI
40~
943+
PCTLI
J'
944+
CPI
5EH+l
945+
JP
PCTLI
946
CPI
MTA
rIs it my talker ad~ress
947
JZ
PCTLI
:Yes, just return
94R
OUT
DOUT
;Seno on GPI8
949
WAITO
950+??0~59:
IN
IN'r!
,Get IntI sta.tus
951+
A~I
BOM
;Check tor byte out
952+
JZ
??005~
;If not, try aqain
953
~VI
A,TCT
;Take control mess~qe
954
ou'r
DOUT
WAITO
955
95 6+??0051:
I"i·rl
IN
iGet IntI status
957+
ANI
80M
;Check for hyte out
958+
JZ
??0~51
;If not, try aqain
959
'1VI
A,MODEI ;Not talk only or listen 'Only
9n0
OU'f
ADRMO
;Enable ql ~nrlress mo~e I
9H
CLRA
9<;2+
XRA
A
;A XOR A ,.a
9n3
OUT
AUXMD
; Immed iate XEQ PON
904
A,MDA
;My device adnress
""VI
965
ou'r
ADRal
;enabled to talk and listen
96<;
MVI
A,AXR8+CPTE~
;Command pass thru en~ble
9n7
DU'r
AUX~D
968 :·······optional PP configuration goes here ••••••••
9<;9
MVI
A,GIOL
:92 go idle command
970
ou'r
CMD92
971
WAITX
972 .... ?10052: IN
973+
ANI
974+
JNZ
975
WAITT
:Wait for Tel
976+??0053, IN
PRTF
;Get task complete int,etc.
977+
ANI
;Mask it
TCIF
978+
JZ
??g~ 53
;Wait for task to be complete
INX
979
A
990 PCTLl:
RET
981
982 ;
983 ;****************** ••• ********************
:::
986
987
988
989
990
991
992
;R£CEIVE CONTROL ROUTINE
993
;NOTE:
;
J INPUTS:
;Ou'rpUTS:
;CALLS:
;DESTROYS:
;RETURNS:
994
995
996
997
998
999
1000 ;
1001 RCTL,
1002
1003
1004
1005
None
None
None
A, F
0= invalid (not take control to us or cP'r bit not on)
<.) 0 = valid take control-- 92 will now be in control
THIS CODE MUST BE TIGHTLY INTEGRATED IWfO ANY USp,q
SOFTWARE TH ... 'r FUNCTIONS "ITA 'rHE ~291 ... 5 ... DEVICE,
NORMALLY SO'~E AOVA"!CE WARNING OF IMPENDI"IG PASS
CONTROL SHOULD BE GIVE"! 'fO US ~Y rHE CONTROLLER
WITH O'fHER USEFUL INFO, THIS PROTOCOL IS SITUI\TION
SPECIFIC AND WILL NOT BE COVERED HERE.
IN
ANI
JZ
IN
CPI
IN'rl
CPT
RC'fL2
CPfRG
TC'f
;Get INTI retJ (i.e. cP'r etc.)
;Is command 'pass thru on ?
;No, invalid-- go return
;Get command
;Is it take control?
231324-43
3-141
AP-66
139~
C2CAlJ
1399 DB~4
139R E6a2
139D CACAlJ
13A~ 3E60
13A7 DH~
13A4 JE8P
13M DH4
13A8
13A9
13A8
13AO
13AF
1381
lJB3
1385
AF
0361
0352
0365
3EFA
0369
3EBF
D365
13S7 DMF
13B9 E602
13SB C28713
13dE
13ea
13C2
13C5
13C7
13CA
13CC
DB6F
£682
CABElJ
JE09
C3CF13
3ur
036S
13CE AF
lJCF C9
1806
1007
1808
1009
DR69
E628
CAE213
F6~B
0369
0869
E6U
CAOS13
C9
13£3 3EF8
lJE5 0369
13E7 DB6F
13£9 E602
13E8 C2E713
l3EE DB6F
13F0 E602
13F2 CAEE13
I~
A'll I
,JZ
",VI
1019
IP11
1012
ou'r
RCTL1
ADRqT
'rA
RCTl.1
;NO, go return inVAlid
;Get ad"ress status
,IsT"on?
,No -- qo return invalid
A,DTDLI ,DiRanle talker listener
ADRR1
A,TOt4
,Talk only
MVI
~DR~J)
OUT
1B14
CLRA
1B15+
XRA
~
,1\ XOR A =A
UH
OUT
IN"rl
,Mask off I~T hits
1017
OUT
INT2
1018
OUT
AUXMD
1819
MVI
II,TCN'rR :T.. ke (receive) contrni 92 command
ou'r
C",092
1120
1021
MVI
A. VSC,~l> ;val lit COlDmanri 'pl'ttern for 91
1022
OUT
AUX"D
1023 ; ******** optional TOUTl check could be put here ****.***
1024
WAITX
1825+110054 : IN
PRTF
1826+
ANI
TCIF
IB27+
3HZ
110054
1028
WAITT
;Wait for Tel
1829+119355: IN
PRTF
;Get task complete int,ete.
1030+
ANI
TCn
,Mask it
lB31+
JZ
??0366
,Walt for task to he complete
1837
MVI
A,TCT
;Val in return pattern
1833
3~P'
RC'rL2
,Only one return per routine
1834 RCTLI: MVI
A,VSCII1D ;Acknowledqe cP'r
1035
OUT
AUXMD
1836
CLRA
; Error return pattern
1037+
XRA
A
;A XOR A =B
1838 RCTL2:
RET
IB39 ,
1~1l
184M
,*************.*. **.***** ***********************.*
1~43
,
1041
1B42
13UO
1302
1304
1307
1309
lJ08
1300
l30F
13£2
.JNZ
SRO ROUTI'llE
le44 ; INPUTS;
None
1845 ;oU'rpUTS:
None
1046 ,CALLS:
None
lB47 ;RE'fURNS:
A~ A no SRO
lB48
A ( > 0 SRO occureti
1049
USB,
1051 SRQD:
IN
INTST
;Get 92 1 9 I~TRQ status
1852
ANI
;~ask off SRQ
SR9BT
1053
JZ
SRQD2
,Not set--- go return
1054
ORI
lACK
,Set--- must clear it with I"'C~
lB55
ou'r
CMD92
1056 SRQD1.
IN
I~TST
,Get ISF
1057
ANI
19FRT
;Mask 1 t
IM8
JZ
SRQDl
,WIIlt if not set
1059 SROD2: RET
10GB ,
1861 1 ** *** ************ ft"'''''''''''''''' ***** ** *** ********* *
1862 ,
1063 ,REMOTE ENARLE ROUTINE
1864 I
1A65 I INPUTS:
None
1066 ,oU'rpu'rs:
None
1067 ,CALLS:
NONE
1868 ;'DES,TROYS:
A, F
1369 ,
lB70 RE.. E:
MVI
",SREMo
,CMD92
OUT
1871
;92 asserts remote enahle
1072
WAITX
;Wait for Tel = "
1073+??0056: IN
PRTF
ANI
le74+
TCIF
1375+
3NZ
??H05~
1876
WAITT
,Wai t fOT TCI
1077+110057: IN
PRTF
;Get task complete lnt,ete.
lB78+
ANI
TCIF
,Mask i t
1079+
JZ
??A~57
;Wait for task to he complete
3-142
231324-44
AP·S6
13~'5
C9
13F6 3EF7
llFB 0369
13~'A
DB6F
llFC E632
13FE C2FA13
14Bl
1403
1405
140B
OBfiF
E602
CA0114
C9
IBBA
lABl
1082
1983
lA84
lABS
1086
lA87
1988
1989
1090
1091
1092
1993
1A94
,
RF.T
,.*****************************************
I
,LOCAL
ROU"rI~E
,
,INPU'l'S.
,OUTPUTS.
,CALLS.
,DESTROYS.
,
~VI
LOCL.
OUT
"'AITX
lA9~+??0958. IN
1096+
ANI
1097+
JNZ
1098
WAIT'r
1099+110059, IN
1190+
ANI
11Bl+
JZ
1102
RE'r
1193 I
None
None
None
A, F
A, SLOC
CMD92
;92 stops asserting remote enable
;Wait for Tel .. "
PH1'F
TCIF
??a0~R
tWa i t
PRn'
TCIF
?1~A
59
for TCl
;Get task complete int,etc.
,Mask it
,Wait for task to be complete
llA4 ;**********************************************
1195 ,
,
1106 ,I~TEHFACF. CLF. .. R I AROIIT ROU'rINE
11A7
1108
None
1109 ~INPU'rS:
None
l11A ~OU'rpUTS :
None
1111 ,CALLS.
1112 ; DESTROY'S:
A, F
1113
1114 ,
1115 IFCL,
MVI
A,ABORT
1116
OUT
; Send IFC
CMD92
1117
WAITX
,Wait for TCI =91
1118+110060, IN
PRTF
1119+
ANI
TCIF
1120+
JNZ
??AA6~
1121
WAITT
;1."a1 t for Tel
1122+11001;1: IN
PRTF
;Get task enmpletp. int,etc.
1123+
ANI
TCIF
,Mask It
,
1409 ]EF9
140~ DH9
1400 DBfiF
140F E602
1411 C20D14
1414 DBfiF
1415 Efi02
1418 CA1414
1124+
JZ
??~~~l
;Wait for task to be complete
1125 ;Delete both 'NAITX & WAITT if this routine
112~ ,is to be called while the !!292 is
11'7 ;Controller-in-Charqe. If not C.I.C. then
1418 C9
1128 ,'reI is set, else nothinq is set (IFC is sent)
1129 ;anr:t the WAIT'S will hanq forever
1139
RET
1132 ,
3-143
231324-45
inter
AP-66
0032
0931
0051
000D
003A
00~'"
0940
141C
142A
1424
1428
1421\
000F
1428
142F
00AI;
1431
1432
1433
1434
1435
143,
31
FF
32
FF
51
FF
1437
1439
143B
143£
1441
AI;0D
AEAF
111C14
213314
COIC10
46553141;
52333748
48414D32
51;4F
AD
50463447
3754
1444 ~<;54
1446 ~E06
1448 112a14
1448 213114
144E CDIC10
1451 CODa13
1454 CA5114
1457
145A
1450
1460
1461
1462
1464
11003C
213514
COIC12
18
lA
EI;40
CA7714
1467 0631\
1469 0Ell
213514
146E l1913C
1471 C09F10
1474 C27714
146~
1477 00
3C00
3C00
0all
1133
1134
1I35
113(,
1137
1138
1139
1I49
1141
1I42
1I43
; APPLICATION EXA"'IPLF. CODE FOR
8~8~
;
FGD'L
EQU
~'CDNL
EQU
FCDN'f
SRQM
€QU
EQU
EOU
EQU
EQU
~'GDI\1'A:
DB
CR
L~'
LE~D
;Fune qen devicE" num "2" ASCII,lstn
;Freq ctr device num "I" A~CII,lstn
;Freq etc ta 1 k add ress
;ASCII carriaqe return
;ASe II 1 ine feed
;List end fo r Tal kILl sten 1 ists
;Bi t indicatinq device sent SRO
'2 '
'I'
'Q'
"Ott
9A"
9F~'H
4AH
'FUIFR37KHA~2VO',CR
:Dat-l to set up func. qen
1144 LIMI
EQU
1145 FCDATA: DB
15
• PF4G7r I
;Data to 'set up freq etc
1I46 LIM2
1147 LLI :
EQU
DB
FCDNL, LEND
;Buffer length
; Li sten list for fceq etc
1148 LL2:
DB
FGDNL, LEND
; Li sten list for func. qen
1149 TLI :
DB
FCDNT,LgIIJD
;'ralk 1 ist for freq etc
1150
1151
1'152
1I53
1154
1155
1156
1157
1158
1159
11,0
llfil
1162
1163
1164
1165
11H
111;7
1168
1169
1170
1171
1172
1173
1174
1175
117,
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1195
1197
,8uffer lenqth
;
;SETUP
FU~CTION
MVI
MVI
LXI
LXI
CALL
;SETUP FREel
GENE.tA'roR
B,CR
:EOS
C,LIMI ;Count
O,FGf}A.T4
H,LL2
SEND
;Data pointer
; Li sten list pointer
COU~'rER
~VI
B, 'T'
MVI
LXI
LXI
CALL
C, Ltl'o12
;EOS
,Count
0, FCDATA
H,LLl
;Data pointer
; Li sten list pointer
SEND
;WAIT FOR SH.Q FROM FREO CTR
Loop:
CALL
JZ
SRQD
LOOP
;Has SRO occur red
;No, wa it for it
; SER IAL POLL TO CLEAR SRQ
LXI
LXI
CALL
DCX
LDIIX
liN I
JZ
D,SPBYTE
;Suffer pointer
H,TLI
SPOL
;Talk 1 i st po in ter
0
D
SRQM
ERROR
;BackuJ) bufffH pointer to ctr byte
;Get status byte
;Did ctr assert SRQ ?
;Ctr shoulti have said yes
;RECEIVE READING FROM COU'''TER
MVI
MVI
LXI
LXI
CALL
JNZ
B, LF
;EOS
;Count
;'l'alk list pointer
H,TLl
;Dat., In buffer pointer
D. FCDATI
C,LI~3
RECV
ERROR
;
;******* rest of user processing
~RROR:
ORG
NOP
ETC.
3Cn0H
SPBYTE:
OS
LI>l3
EQU
qoe~
here *****
;User depenr:lant error handl inq
1
17
; Location for ser ial poll byte
;Max freq counter input
231324-46
3-144
intJ
Ap·66
3C01
1198 FCDA'l'Io DS
1199
EII/D
I Freq ctr Input buffer
LIM3
PUBLIC SYMBOLS
EXTER'IAL
SYI~I!OLS
USEK SY.'ftWLS
A AlfF9
A801~T
81.
CLNS'f
.1\ AB91
A "B#j~
DCLR
A llEC
EDEOS
ERROR
lo'CONL
A 0004
GS~C
IFeL
IN'fST
LLI
I'ItODEl
PPO
PP~JIl2
H'NGE
REcvl
Rlm.lo'
SOEOI
SE~D6
SPIF
SROOI
reNTK
TOST
UVL
wou'r
AImB~
KOF
C"'092
DCLRI
e. . OIltK
A".,,,,,
A "'HH
A flDl;q
AUF"
"
BA1'1
EVdIT
FCDNr
A "~111
1".F4
GTS~
A 0AF6
1409
A BB~9
A 1431
RA01
A 007.
1208
+ 0905
A leEA
A AeE4
A H0H~
A 10BS
HUT
LA
LL2
_TA
PE-OS
PPOL
A 1477
A 0031
••
•
•
• •• H4
A l30B
•••
HdST
RECV2
RERM
SEND
SE'fF
SPOL
5"002
~"FA
TCsr
S.0f)8
'rOUT I
003F
A 'HH:t
vsc..,o
xr£a
.'SSEI~ilLY COJ~PLETE,
A '''''51
AD~~O
80.
CPT
DCLR2
EOlli
BVCST
I"TI
A 80141
LEND
LOCL
..
A
A
A
12EiiI
1327
e9E7
lIRe;
•
+ 0"":1
•
"3~A
A HUC
121C
A 13 .. 2
A "~f'D
•
PB~l
A CJ""P
A 113A
NO
" 0""2
~vc",n
PPiJC;1
PPU
ReST
RECV3
REVC
SE-IOI
SLOC
SPOll
St{OM
'reT
TOUT2
WAI'rI
XFE~l
AD~s'r
'JUSST
" III"·"
A 1209
CPTE'"
01.
" eftAP
EOYST
A "~~f'
FGDATA " 141C
Hoet.lO
A 0101'12
A 16'09
•A .041
1433
A 111111;4
A
A.
A
A
A
A
A
,
••
•
,•
"""1
flAFF
13FI;
911'017
12£"
Aue;
""EI;
lInl;
AAEl
1M2E
"9F7
A 1210
9840
01UI9
0\ AAA2
+ lHlJA2
•
1153
P.VR£G
PGr)'lL
HOIiSI(
[~T2
LF
L0_
OBFF
PPDS2
PPUN
~CTL
A c."O=;4
A CllfIll1R
•,
•• ~"""
•• "''''!H
•
•
• Ill.
••
•
AQI~l
0:'1'if1
A!H;q
A AAJ,
fI"~2
A tHlillA
III1UA
A
"~1A
12FD
A 131A
13~8
AUX"'D
CAHCY
CPTRG
flOUT
EOS'l
F!xpp
FNH'iK
lACK
I'fTrol
Lt"1
LOOP
PCTL
PPE
PRTCfl
Rt.::1'Ll
I~FCVc;
A
~IH':S
RI""
SE'\I02
1.47
SPSY'rr. A 3COO
C;POL2 A 1'94
SPCNt
SqP.Ni
C;TC''U
T'
RECVIf
'rLl
'rOUT)
'''''tTO
lCFP.tt2
HAFF.
A 14')Cj
" 0A~4
+ IlRCn
" lll;C
q"~T
SE~03
TLt)~
'rRIG
WI\ITT
XFERl
,
•• "~"'1
•,•
••
,
AMr;
"XiV. ,
CLK~'r
0"C;1)
CR
OTOLI
ERFLG
A 91"C;q
"HJ"1
0GtFI)
AA"'l
AQ'JB
IUlA"
A "GIlAl'
lot.:;1
A 13'"
Alit""
t.t""'i'll
A DCA
1117
00F2
A UH;q
A •• FB
A •• F~
A "~"2
,•
,
•
. "cn
• .IIRC
A
,
+
;Hl~4
11·3
FCOATA
G€T
IBFBT
I"lT~1
LPt2
.DA
PCTLI
PPE"
PH'f9'
RCTL2
RECV':'
QSTI
SE"JD4
SPO
SqoaT
rc,sy
'r01l1
TRIGl
I'Ih IT X
l(Fi':IU
,
, "Il'l"
.,
RCUB'
AX!\8
A
llIt~n
A
A
"~S;tlI
CLRA
DCL
OTDL2
,
••
~Pt;A
1.12'"
(H"'~
llU'
A 14:9';1
A 'HH'~
,•
qIJIH
119A
• DO
A "Afiq
•
,
13-:F
A 1119
A eAF3
1M7.
A AA19
A
fI .... FC
A "3q~
,,0'91
•
, llell
+
, 11131'\
A!l93
A9A!17
"""0
+
A "'1-'14
A BAE'
" ",,'Ut
ERR.oII
FCOATI A 3eAI
GIOt
A "AFI
ISFF
A "'JU'
I~T"'R
A
A
A
A
A
A
LlM3
"LA
PPC
PPF.:N1
PRTr
RECV
RP.ME
RTDtJ'r
SE"05
SPE
S~OO
',l'CIto'
TOt{EG
'rRIG2
"'Eve
•
143fi8
~.ll
RAn
0~"tS
12A7
""IiF
lA9P
A 13E3
A 9RE9
lH7F
A •• Ie
,
•,
A
1300
0~A2
AnliS
A 1109
A A'lF;'
~RRORS
231324-47
3-145
AP-66
APPENDIX B
Analyzer was used. This analyzer acted as a talker, listener or another controller as needed to execute the
tests. The, sequence of outputs are shown with each test.
All numbers are hexadecimal.
Test Cases for the Software Drivers
The following test cases were used to exercise the software routines and to pheck their ~ction. To provide
another device!controller on the GPIB a ZT488 GPIB
Send Test Cases
B=
C=
DE=
HL=
3E70:
3E80:
GPIB output:
Ending B=
EndingC=
Ending DE=
Ending HL=
44
30
3E80
3E70
20 30 3E 3F
11 44
41 ATN
3FATN
20ATN
30ATN
3EATN
11
44EOI
44
2
3E80
3E70
44
0
3E80
3E70
41 ATN
3FATN
20ATN
30ATN
3EATN
11
44EOI
41 ATN
3FATN
20ATN
30ATN
3EATN
44
2E
3E82
3E73
44
0
3E82
3E73
44
0
3E80
3E73
Receive Test Cases
B=
C=
DE=
HL=
3E70:
GPIB output:
ZT488 Data
In
EndingA =
Ending B =
EndingC =
Ending DE=
Ending HL=
44
30
3E80
3E70
40
40ATN
3FATN
21 ATN
1
2
3
4
44
0
0
2B
3E8S
3E71
44
30
3E80
3E70
50
50ATN
3FATN
21 ATN
1
2
3
4
5,EOI
0
0
2B
3E85
3E71
44
30
3E80
3E70
5E
5EATN
3FATN
21 ATN
1
2
3
44,EOI
44
30
3E80
3E70
5F
44
4
3E80
3E70
40
40ATN
3FATN
21 ATN
1
2
3
4
44
4
3E80
3E70
40
40ATN
3FATN
21 ATN
11
22
33
44
44
0=256
3E80
3E70
40
40ATN
3FATN
21 ATN
1
2
3
44
0
0
2C
3E84
3E71
SF
44
30
3E80
3E70
40
40
0
3E84
3E71
0
0
0
3E84
3E71
0
0
FC
3E84
3E71
3-146
inter
AP-66
Serial Poll Test Cases
C=
30
C=
DE=
HL=
3E70:
3E80
DE=
3E70
HL=
40
3E70:
50
GPIB output:
5E
SF
GPIB output: 3F ATN
EndingC =
output: 21 ATN
Ending DE=
output: 18 ATN
output: 40 ATN
Ending HL=
input": 00
output: 50 ATN
input": 41
output: SE ATN
input": 7F
output: 19 ATN
"NOTE: leave ZT488 in single step mode even on input
EndingC = 30
Ending DE = 3E83
Ending HL= 3E73
Ending 3E80: 00 41 7F
30
3E80
3E70
SF
3FATN
21 ATN
18ATN
19ATN
30
3E80
3E70
Pass Control Test Cases
HL=
3E70:
GPIB output:
Ending HL=
EndingA =
3E70
40
40 ATN
09ATN
-ATN
3E71
02
3E70
41 (MTA)
3E70
SF
3E70
41 (MTA)
3E70
SF
Receive Control Test Cases
GPIB input
Run Receive Control
GPIB Input
Ending A=
10 ATN
ATN
40ATN
09ATN
41 ATN
09ATN
ATN
o
o
ATN
09
3-147
inter
AP-66
Parallel Poll Enable Test Cases
OE=
HL=
3E70:
3E80:
3E80
3E70
20 30 3E
01 02 03
3FATN
20ATN
05ATN
61 ATN
30ATN
05ATN
62ATN
3EATN
05ATN
63ATN
3E83
3E73
GPIB output:
Ending OE=
Ending HL=
3F
3E80
3E70,
3F
3FATN
3E80
3E70
Parallel Poll Disable Test Cases
HL=
3E70:
3E70
20 30 3E
3FATN
20ATN
30ATN
3EATN
05ATN
70ATN
3E73
GPIB output:
Ending HL=
3F
3E70
3F
3FATN
05ATN
70ATN
3E70
Parallel Poll Unconfigure Test Case
GPIB output:
15 ATN
Parallel Poll Test Cases
Set 010 #
Ending A
1 2 3 4
1 2 4 8
5 6 7
10 20. 40
8
80
None
0
SRQTest
Ending A =
Set SRO momentarily
02
ResetSRO
00
inter
AP-66
Trigger Test
HL=
DE=
BC=
3E70:
GPIB output:
3E70
3E80
4430
20 30 3E 3F
3FATN
20ATN
30ATN
3EATN
08ATN
3E73
3E80'
4430
Ending HL=
DE=
BC=
Device Clear Test
HL=
DE=·
BC=
3E70:
GPIB output:
3E70
3E80
4430
20 30 3E
3FATN
20ATN
30ATN
3EATN
14ATN
3E73
3E80
4430
Ending HL=
DE=
RC=
3F
XFERTest
B=
HL=
3E70:
GPIB output:
44
3E70:
40 20 30 3E 3F
40ATN
3FATN
20ATN
30ATN
3EATN
o
GPIB input:
1
2
3
44
o
Ending A =
B=
HL =
44
3E74
~-149
intJ
Ap·66
Application Example
GPIB Output/Input
41 ATN
3FATN
32ATN
GPIB output:
46
55
31
46
52
33
37
4B
48
41
40
32
56
4F
OOEOI
41 ATN
3FATN
31 ATN
50
46
34
47
37
54EOI
SRO
GPIB input:
GPIB output:
3FATN
21 ATN
18ATN
51 ATN
GPIB input:
GPIB output:
40SRO
19ATN
51 ATN
3FATN
21 ATN
3·150
inter
AP-66
GPI8 input:
20
28
20
20
20
33
37
30
30
30
2E
30
45
28
30
00
OA
GPI8 output:
XXATN
Ap·66
APPENDIX C
REMOTE MESSAGE CODING
Bus Signal LlneCs) and
Coding That Asserts the
True Value of the Message
C
I D
D NN
I DRD A E S I R
Y a I
o AFA TOR F E
P s 0
Message Name e s 8 7 6 5 4 3 2 1 VDC N I Q C N
T
Mnemonic
ACG
ATN
DAB
0 o 0 XXXXXXX 1 X X
XXXXXXXXXX 1 X X
DDDDDDDXXX 0 X X
7 6 5 4 3 2 1
X X X X X X X XXO X X X
X X X X X X X 1XX X X X
0 0 1 0 1 o 0 XXX 1 X X
X X X X X X X XXX 0 1 X
E E E E E E E XXX 0 X X
7 6 5 4 3 2 1
0 0 0 1 0 0 0 XXX 1 X X
0 0 0 000 1 XXX 1 X X
X X X X X X X XXX X 1 X
X X X X X X X XXX X X X
0 1 X X X X X XXX 1 X X
0 0 1 000 1 XXX 1 X X
0 1 L L L L L XXX 1 X X
5 4 3 2 1
Y 1 0 T T T T T XXX 1 X X
543 2 1
Y 1 1 S S S S S XXX 1 X X
5 4 3 2 1
0 0 0 0 0 0 0 0 XXX X X X
(OSA = SCG II MSA)
(OTA = TAG II MTA)
(PCG = ACG V UCG V LAG V TAG)
Y 0 0 0 0 1 0 1 XXX1XX
Y 1 lOS P P P XXX 1 X X
321
Y 1 1 1 D D D D XXX 1 X X
432 1
X X X X X X X 1 XXX 1 1 X
X X X X X X 1 X XXX 1 1 X
X
X
X
X
X
X
X
X
X
X
GET
GTL
IDY
IFC
LAG
LLO
MLA
addressed command group
M AC Y
attention
U UC X
data byte
(Notes 1, 9) M DD D
8
data accepted
U HS X
data valid
U HS X
device clear
M UC Y
end
U ST X
end of string
(Notes 2, 9) M DD E
8
group execute trigger
M AC Y
go to local
M AC Y
identify
U UC X
interface clear
U UC X
listen address group
M AD Y
local lock out
M UC Y
(Note 3)
my listen address
M AD Y
X
X
X
1
X
X
X
X
X
X
X
X
X
X
MTA
my talk address
(Note 4)
M AD
X X
MSA
my secondary address
(Note 5)
M SE
NUL
OSA
OTA
PCG
PPC
PPE
null byte
other secondary address
other talk address
primary command group
parallel poll configure
parallel poll enable
(Note 6)
M
M
M
M
M
M
PPD
parallel poll disable
(Note 7)
M SE
PPR1
PPR2
parallel poll respons~ 1
parallel poll response 2
(Note 10)
U ST
U ST
DAC
DAV·
DCL
END
EOS
}
3-152
DD
SE
AD
-
AC
SE
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
inter
AP-66
REMOTE MESSAGE CODING (Continued)
Bus Signal Line(s) and
Coding That Asserts the
True Value of the Message
C
I
T
D
Y a I
P s 0
Mnemonic
s
Message Name e
PPR3
PPR4
PPR5
PPR6
PPR7
PPR8
PPU
REN
RFD
ROS
SCG
SDC
SPD
SPE
SRO
STS
parallel poll response 3
parallel poll response 4
(Note 10)
parallel poll response 5
parallel poll response 6
parallel poll response 7
(Note 10)
parallel poll response 8
parallel poll unconfigure
remote enable
ready for data
(Note 9)
request service
secondary command group
selected device clear
serial poll disable
serial poll enable
service request
(Notes 8, 9)
status byte
U
U
U
U
U
U
M
U
U
U
M
M
M
M
U
M
ST
ST
ST
ST
ST
ST
UC
UC
HS
ST
SE
AC
UC
UC
ST
ST
TCT
TAG
UCG
UNL
UNT
take control
talk address group
universal command group
un listen
untalk
M
M
M
M
M
AC
AD
UC
AD
AD
}
}
(Note 11)
8 7 6 5 4 3 2
X
X
X
X
X
XXXX1 X
XXX1 XX
XX 1 XXX
X1 XXXX
1 X X X X X
XXXXXX
D NN
I DRD A E S I R
0 AFA T 0 R F E
1 VDC N I Q C N
X
X
X
X
X
X
1
Y 001 0 1 0 1
XXXXX
XXXXX
X 1 XXX
Y 1 1 X X
XX
XX
XX
XX
X
X
X
X
Y 0 000 1 0 0
Y 0
1 1 0 0 1
Y 0
1 1 0 0 0
o
o
XXXXXXXX
XS S S S S S
S
8
Y
Y
Y
Y
Y
6 5 4
0
0 1
XX
1
0 0 1 X
0 1 1 1
1 0 1 1
o
o
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XOX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
3 2 1
0 0 1
XXX
X X X XXX
X X X XXX
1 1 1 XXX
1 1 1 XXX
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X X
X X
0 X
1 X
1 X
1 X
1 X
X X
0 X
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1 X
XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
The 1/0 coding on ATN when sen1 concurrent With multiline messages has been added to this revision for interpretive convenience.
NOTES:
1. 01-08 specify the device dependent data bits.
2. E1-E8 specify the device dependent code used to indicate the E08 message.
S. L1-L5 specify the device dependent bits of the device's
listen address.
4. T1-T5 specify the device dependent bits of the device's
talk address.
5. 81-85 specify the device dependent bits of the device's
secondary address.
6. 8 specifies the sense of the PPR.
S
Response
o
0
1
1
P1-PS specify the PPR message to be sent when a parallel poll is executed.
P3
P2
P1
o
o
o
PPR1
1
1
1
PPR8
PPRMessage
7.01-04 specify don't-care bits that shall not be decoded
by the receiving device. It is recommended that all zeroes
be sent.
8. 81-86, 88 specify the device dependent status. (0107
is used for the RQ8 message.)
9. The source of the message on the ATN line is always
the C function, whereas the messages on the 010 and EOI
lines are enabled by the T function.
10. The source of the messages on the ATN and EOI lines
is always the C function, whereas the source of the messages on the 010 lines is always the PP function.
11. This code is provided for system use, see 6.S.
3-153
Modem Products
4
inter
•
•
•
•
•
•
•
•
•
•
89024
2400 BPS INTELLIGENT MODEM CHIP SET
Customized Command Set and
• Easily
Features
Chip Intelligent Modem Solution
• Two
with Minimal External Components
No External ,...C Required
• Output
• Range Level Programmable over 16 dB
Dial and Re-dlal Capability
• Full
Set of Control Signals for DAA
• Interface
Local, External, or Slave Timing
• Options
In Synchronous Mode
Adaptive Equalization
• Capable of Detecting Dial, Busy,
• Ringback and Modem Answer Tones of
Most International Networks
• Auxiliary Relay Control Output
For Public Switched Telephone
Network and Unconditioned Leased
Lines Applications
V.22 bls, V.22 A/B, V.21, Bell 212A, and
Bell 103 Compatible
Serial Command Set Compatible with
Hayes Smartmodem 2400
Automatically Adapts to Remote
Modem Type with Recognition of Data
Rates
DTMF and Pulse Dialing, with Automatic
Selection of Dial Signaling
On-Chip Hybrid and B!lIIng Delay Timer
On-Chlp Serial Port and Handshake
Signals for R8-232/V.24 Intertace
Telephone Line Audio Monitor Output
Analog/Digital Loopback Diagnostics
with Mark/Space Pattern Generation
and Error Detection
Simple Serial Interface to External
NVRAM
89026
89027
HAYES COIoiMANDS
FSK IoIODULATOR/
DEIoiODULATOR
DTMF TONE GENERATOR
ANSWER TONE GEN.
TELEPHONE
LINE
INTERFACE
DTE
INTERFACE
(DAA)
QAIoI/PSK TRANSMITTER
SCRAMBLER/ENCODER
QAIoI/PSK RECEIVER
SIGNAL RECOVERY
DESCRAMBLER. DECODER
LINE CONTROL/STATUS
OM INTERFACE
270242-1
Figure 1.89024 System Block Diagram
4·1
October 1988
Order Number: 270242-003
89024
serial NVRAM, and RS-232 driver/receivers, represent the circuitry required for implementing an autodial, auto-answer, 300 to 2400 bps, full duplex
Hayes compatible intelligent modem.
GENERAL DESCRIPTION
The Intel 89024 chip set is a highly integrated, high
performance, intelligent modem, providing a complete system in two chips. The system conforms to
the following CCITT and Bell standards:
A complete set of industry standard AT commands
is provided for modem configuration and user interface. Virtually all PC software written for the Hayes
Smartmodem 2400 can also·be used with this·chip
set. Alternatively, in applications where user proprietary modem control commands and features are desired, the user can replace the 89024 internal command module with custom proprietary software resident in the 89026 microcontroller's on-chip ROM or
an external memory device.
• ccrr.r V.22.bis
2400 bps sync and ·async
1200 bps sync and async (fall-back)
• CCITT V.22 A & B
1200 bps sync and async
600 bps sync and async (fall-back)
• CCITT V.21
o to 300 bps anisochronous
• BELL 212A
1200 bps sync and async
300 bps faU-back mode
The 89024 has a set of default features. Upon power
up, the modem configuration will be in accordance
with these default options, unless a different configuration has been saved in the external NVRAM with
the &W command.
• BELL 103
o to 300 bps anisochronous
The 89024 system consists of a 16 bit application
specific processor (89026) and an analog front end
device (89027). The 89026 processor pertorms all
"Digital Signal Processing" algorithm execution for
processing the modem signals, as well as providing
all modem control functions typically performed by
an external processor. The analog front end provides for 2 wire and 4 wire telephone line interface,
0/ A conversion, and most of the complex filtering
functions required in QAM/DPSK/FSK modems.
Refer to Figure 1 for a simplified block diagram of
the system.
The 89024 modem has built in auto-dialing and autoanswering capabilities. It can be configured to the
proper line signaling mode (Tone. or pulse), and to to
the type (CCITT or Bell) and speed of the calling or
answering modem. It can also detect and identify
call set-up signals of telephone networks, allowing
unattended data call operation. .
A full set of diagnostic loop-test features compatible
with CCITT V.54 is supported. The chip set also provides a line signal for audio monitoring of call progress, a comprehensive set of DAA control lines for a
simple interface to the telephone network, and a full
complement of TTL level RS-232/ V.24 handshake
signals.
In stand-alone modem applications, the 89024 chip
set along with a Data Access Arrang.ement (DAA), a
NOTICE:
Hayes is a registered trademark of Hayes Microcomputer Products, Inc.
Smartmodem 2400 is a trademark of Hayes Microcomputer Products, Inc.
Smartcom!1 is ~ registered trademark of Hayes Microcomputer Products, Inc.
4-2
inter
89024
PACKAGING
Both devices are available in standard DIP packages
as well as PLCC packages for surface mount appli·
cations.
SCLK
SOATA
vcc
STR
TSYNC
ClKOUT
...,
~
u ~
~
~
f!!
"... 8
... Ill>
~
...:>
...u~
TX3
X2
TX2
vss
Xl
TX2
X2
AOl
NC
AVee
VSS
Xl
AOl
AVec
TXl
AGNO
TXl
NC
TXO
RST
TXO
AGNO
HYB
NC
HYB
RST
AMP
ED
AMP
NC
A02
AZ2
I
AZl
Q
VBB
N
0
-
000(
270242-2
0
CD ...
>IX>
N
N
N
000(
000(
Q
""'
270242-3
28 Pin PLCC
28·Pln Plastic DIP
ADO
Q
ADl
AGND
AD2
VREF
AD3
VPO
AD4
B/C
A05
RST
AD6
SOATA
AD7
SCLK
ADS
TClO
AD9
TCLl
A010
s/i.
ADll
RTS
AD12
CTS
AD13
STR
A014
DTR
A015
SH
XTClK
270242-5
68 Pin PLCC
Figure 2. Device Packages
4·3
89024
dem will initiate a disconnect only ~tter a Y1 command. The optional disconnect requests originated
by the remote modem, are of two types, (1) disconnect when receiving long-space, and (2) disconnect
when received carrier is dropped. The modem chipset can also be configured to transmit 'long-space'
just before disconnection, in each of the aforementioned cases.
CALL ESTABLISHMENT,
TERMINATION AND RETRAIN
The 89024 modem system incorporates all protocols and functions required for automatic (or manual) establishment, progress and termination of a
data call.
The modem Chip-set has a built in auto-dialer, both
DTMF and Pulse type, and is capable of automatically adapting to the telephone dial type. The dialing
sequence on the telephone link conforms to the
CCITT V.25 recommendations. An exception to the
V.25 is that the interrupted calling tone will not be
transmitted by the calling modem, as is suggested in
V.22 bis.
Because the CCITT and Bell modem connection
protocols are quite different from each other and do
not provide recognition of remote modem type (Le.
V.22 bis to 212A), the Intel Chip-set provides the additional capability of identifying the remote modem
type. This feature is beneficial during the migration
phase of the technology from the 1200 bps to 2400
bps. In North America, where the installed base of
1200 bps modems is mostly made-up of 212A type,
this feature allows a "Data Base Service Provider"
to easily upgrade the existing 212A modems to 2400
bps V.22 bis standard, transparently, to 212A users.
Similarly, a user with a 89024 based modem system
can automatically call data bases with either 212A or
V.22 bis modems, without concern over the difference. This feature's benefits are realized .in smooth
upgrading of data links, with minimum cost and reduced disruption in services. Refer to Table 1 for a
detailed description of remote modem Cbnlpatibility.
The modem can detect the dial, busy and ringback
signals at remote end, and will provide call progress
messages to the user'. The modem is capable of redialing the last number dialed, by one command.
The modem when configured for auto-answer, will
answer an incoming call, remain silent for the two
second billing delay interval, before transmitting the
answer tones. Afterwards modem to modem identification and handshaking will proceed at a speed and
operating mode acceptable to both ends of the link.
The data call can also be setup by manual dialing
with the modems set to data mode, or by voice to
data transfer by means of mechanical switch (exclusion key), using the SH pin. Once set to data mode,
the modem handshaking will proceed before the
modems will be ready to accept and exchange data.
SOFTWARE CONFIGURATION
COMMANDS
This section lists the 89024 commands and registers
that may be used while configuring the modem.
Commands instruct the modem to perform an action, the value in the associated registers determine
how the commands are performed, and the result
codes retl,lrned by the modem tell the user about the
execution of the commands.
During data transmission, if one of the modems finds
that the received data is likely to have a high bit error
rate (indicated by a large mean square error in the
adaptive equalizer), it initiates a retrain sequence.
This automatic retrain feature is only available at
2400 bps, and conforms to CCITT V.22 bis recommendations.
The commands may be entered in a string, with or
without spaces in between. Any spaces within or between commands will be ignored by the modem.
During the entry of any command, the 'backspace'
key (CNTRl H) can be used to correct any error.
Upper case or lower case characters can be used in
the commands. Commands described in the following paragraphs refer to asynchronous terminals using ASCII codes.
Disconnection of the data call can be initiated by the
DTE at the local end, or by the remote DTE, (if the
modem is configured to accept it). Whether DTR will
initiate a disconnect, depends on the last &0 Command. Receiving a long space from a remote mo-
4-4
inter
89024
Table 1. Remote Modem Compatibility
Originating
Answer Modem
CCITT
CCITT
89024
Bell
Bell
CCITT
CCITT
Modem
300
1200
300
600
1200
2400
300
1200'
300
1200
-
-
300'
1200
300'
1200
-
-
Bell
CCITT
300
1200
300
600
1200
2400
-
-
300
-
-
600
-
1200'
1200'
1200
1200
89024
Bell
Bell
Modem
300
1200
300
300
300
1200
1200
-
-
-
600
Answering
Bell
CCITT
300
1200
300
600
1200
2400
-
-
300'
300'
1200
1200
-
Originating Modem
CCITT
CCITT
-
300
-
-
-
-
-
1200
1200
1200
2400
CCITT
CCITT
600
1200
2400
-
1200
1200
1200
1200
-
-
-
1200
1200
-
-
1200
2400
• These connection data rates are obtained when connecting 89024 based modems end to end. The same results may not
be obtained when a 89024 based modem is connected to other modems.
& Command Set (Continued)
Command Set
AT
A
AI
Bn
Os
En
Hn
In
Ln
Mn
0
an
Sn=x
Sn
Vn
Xn
Yn
Z
+++
Attention code.
Go off-hook in answer mode
Repeat previous command string
BELLICCITT Protocol Compatibility at
1200 bps
The dialing commands
(0-9 ABC 0 • # P R T S W ,; @)
Echo command (En)
Switch-Hook Control
If &J1 option is selected, H1 will also
switch the auxiliary relay
Request Product Code and Checksum
Speaker Volume
Monitor On/Off
On-Line
Result Codes
Write S Register
Read S Register
Enable Short-Form Result Codes
Enable Extended Result Code
Enable Long Space Disconnect
Fetch Configuration Profile
The Default Escape Code
&C
&0
&F
&G
&J
&L
&M
&P
&R
&S
&T
&W
&X
&2
4-5
DCDOptions
DTR Options
Fetch Factory Configuration Profile
Guard Tone
Telephone Jack Selection
Leased/Dial-up Line Selection
Async/Sync Mode Selection
Make/Break Pulse Ratio
RTS/CTS Options
DSR Options
Test Commands
Write Configuration to Non Volatile Memory
Sync Clock Source
Store Telephone Number
89024
Dial Modifiers
CONFIGURATION REGISTERS
P
R
T
S
W
·The modem stores all the configuration information
in a set of registers. Some registers are dedicated to
special command and function, and others are bitmapped, with different commands sharing the register space to store the command status.
S•
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14'
S15
S16
S17
518'
S19
S20
S21'
S22'
S23'
S24
S25'
S26'
S27'
Ring to Answer
Ring Count. (Read Only)
Escape Code Character
Carriage Return Character
Line Feed Character
Back Space Character
Wait for Dial Tone
Wait for Data Carrier
Pause Time for the Comma Dial Modifier
Carrier Detect Response Time
Lost Carrier to Hang Up Delay
Not Used
Escape Code Guard Time
Not Used
Bit Mapped Option Register
Not Used
Modem Test Options
Not Used
TestTimer
Not Used
Not Used
Bit Mapped Options Register
Bit Mapped Options Register
Bit Mapped Options Register
Not Used
Delay to DTR (Sync Only)
RTS to CTS Delay (Half Dup.)
Bit Mapped Options Register
@
Pulse Dial
Originate call in Answer Mode
Tone Dial
Dial a stored number
Wait for dial tone
Delay a dial sequence
Return to command state
Initiate a flash
Wait for quit
If neither P or T is specified in the command
string, the modem automatically selects the
proper dial mode.
.
Example:
Terminal: AT &Z T 1 (602) 555-1212
Modem: OK
Result:
Modem stores T16025551212 in the external NVRAM.
The number can be dialed from asynchronous mode
by issuing the following command:
Terminal: AT OS
Modem: T16025551212
or by turning on DTR when in Synchronous Mode 2.
Up to 33 symbols (dial digits and dial modifiers) may
be stored. Spaces and other delimiters are ignored
and do not need to be included in the count. If more
than 33 symbols are supplied, the dial string will be
truncated to 33.
APPLICATIONS OVERVIEW
The block diagram of a stand-alone 300 to 2400 bps
Hayes compatible modE;lm is depicted in Figure 3.
The DAA section shown in this diagram may be obtained with FCC registration, or implemented using
the suggested diagram in Figure 4.
NOTE:
• These S registers can be stored in the NVRAM.
4-6
inter
89024
POWER SUPPLY
DGND
RST
AGND
+5 VOLTS
AUDIO
-5 VOLTS
~ONITOR
0.01 }o'F
TELEPHONE LINE
INTERFACE
I~
!'
X1
X2
ClKIN
ED
STR
I
SERIAL
Q
DIGITAL
Vee
DAA
AND
HYB
4Wj2W
89027
VREF
89026
m
z >g >
«
Q
"«
AZ1
ClKOUT
AZ2
ED
-=
z"'
0
r
"TIP
RING
0.02}o'F
I
Q
INTERFACE
TSYNC
TSYNC
V.24j
SDATA
SOATA
RS232C
SClK
A01
TRXCAR
A02
TXO
RCVCAR
TX1
TX2
SCLK
TX3
~
VI
~
~
A~P
STR
VI
VI
t~""
lEVEL
SELECT
OTE
«
Q
z
;!
VI
w
~I
TIP
z
:J
w
z
RING ~
OH
Ali
5H
~IC
i!J
~
270242-6
NOTE:
Pin #22 and pin #19 are NO CONNECT for the 89024 modem application.
Figure 3. Typical Modem Configuration
~I
r------t-~TIP
AIi~---------------------------------r-~
.---1-----+-+ RING
OH~----------------------------~
~IC
AUXILIARY
BUSINESS
PHONE
10K
+SV
"b-_--++. RING
~
g A02~-1~---'--~
~
TELEPHONE
LINE OR
DATA PHONE
'"~
0>
'" A01
~~
b-+.....-++. TIP
________________
-;r~R~I~NG~~::::::::::::::::::~
DETECTOR
5H~_________________-f~E~X~C:L~U;SI~O:N~K~E~Y~-----------~
STATE DETECTOR
270242-7
Figure 4. Typical Telephone Line Interface with Built In Hybrid
4-7
inter
89024
SYSTEM COMPATIBILITY SPECIFICATIONS
Parameter
Synchronous
Asynchronous
Specification
2400 bps ± 0.01 %
1200 bps ± 0.01 %
600 bps ±0.01 %
V.22 bis
V.22 and BELL 212A
V.22A,B
2400,1200,600 bps, character asynchronous.
o-300 bps anisochronous.
Asynchronous Speed Range
+ 1 % - 2.5% default. Extended + 2.3% - 2.5% range of CCITT
standards optional via software customization.
Asynchronous Format
8,9,10,11 bits, including start, stop, parity. Bits 8, 9, 11 optional
via S/W customization.
Synchronous Timing Source
Internal, derived from the local oscillator.
External, provided by DTE through XTCLK.
Slave, derived from the received clock.
Telephone Line Interface
Two wire full duplex over public switched network or 4 wire
leased lines.
On-chip hybrid and billing delay timers.
Output level -1 to -16 dBm
Modulation
V.22 bis, 16 point QAM at 600 baud.
V.22 and 212A, 4 pOint DPSK at 600 baud.
V.21 and 103, binary phase coherent FSK
Output Spectral Shaping
Square root of 75% raised cosine, QAM/PSK.
Transmit Carrier Frequencies
V.22 bis, V.22, 212A
V.21
Bell 103 mode
Receive Carrier Frequency Limits
V.22 bis, V.22, 212A
V.21
Bell 103
Originate
Answer
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
1200 Hz
2400 Hz
1180 Hz
980 Hz
1850 Hz
1650 Hz
1070 Hz
1270 Hz
2020 Hz
2225 Hz
2400 Hz
Originate
Answer
1200 Hz
Originate 'space' 1850 Hz
Originate 'mark'
1650 Hz
1180 Hz
Answer 'space'
Answer 'mark'
980 Hz
Originate 'space' ..,/ 2020 Hz
Originate 'mark',.r 2225 Hz
Answer 'space' t/1070 Hz
Answer 'mark' 11'1270 Hz
.01 %
.01 %
.01 %
.01 %
.01 %
.01 %
.01 %
.01 %
± .01 %
± .01 %
±
±
±
±
±
±
±
±
± 7 Hz
± 7 Hz
± 12 Hz
± 12 Hz
± 12 Hz
± 12 Hz
± 12 Hz
± 12 Hz
± 12 Hz
± 12 Hz
Energy Detect Sensitivity
Greater than -43 dBm ED is ON. Less thah -48 dBm ED is
OFF. Signal in dBm measured at A02.
Line Equalization
Fixed compromise equali,zation, transmit.
Adaptive equalizer for DPSK/QAM, receive.
Diagnostics Available
Local analog loopback.
Local digitalloopback.
Remote digitalloopback.
Local interface loopback.
Self Test Pattern Generator
Alternate 'ones' and 'zeros' and error detector, to be used along
with most loopbacks.
A number indicating the bit errors detected is sent to DTE.
4-8
inter
89024
RECEIVER PERFORMANCE SPECIFICATIONS
Parameter
Specification
Test condition: Unconditioned 3002 line, across the full dynamic range.
The noise bandwidth is 3 KHz flat.
Random Noise
Typical Bit Error rate of 1 in 100000 or better at 12 dB SNR at 300 bps, 5 dB
SNR at 600 bps, 8 dB SNR at 1200 bps and 16 dB SNR at 2400 bps.
Frequency Offsets(1)
± 7Hz.
Phase Jitter(1)
2400 bps - 15° peak to peak, at up to 300 Hz.
600, 1200 bps - 45° peak to peak, at up to 300 Hz.
NOTE:
1. There are no observable data errors for the received signals, for the above limits of line impairments.
These impairments are applied one at a time in absence of noise.
PERFORMANCE SPECIFICATIONS
Parameter
Min
DTMFLevel
Typ
Max
1.0
dBm
-35
DTMF Second Harmonic
DTMF Twist (Balance)
3
dB
100
ms
Pulse Dialing Rate
10
pps
39/61
33/67
%
%
Pulse Interdigit Interval
785
2.1
Hz
dB
1800
-6
Hz
dB
Dial Tone Detect Duration
3.0
sec
Ringback Tone Detect
Duration
Cadence
0.75
1.5
sec
Busy Tone Detect
Duration
Cadence
Software Controlled
US
UK, Hong Kong
sec
540
-3
Frequency
Amplitude
HYB enabled into 600n
ms
Billing Delay Interval
Guard Tone Frequency
Amplitude
atA01
dB
DTMF Duration
Pulse Dialing Make/Break
Comments
Units
referenced to High
channel transmit.
QAM/DPSK Modes Only
,
Off/On Ratio
0.2
sec
0.67
1.5
4-9
Off/On Ratio
inter
89024
In the transmit operation, the 89026 synthesizes
DTMF tones and the 300 bps FSK modem signal
prior to transmitting them to the 89027 as digitized
amplitude samples. During 1200 and 2400 bps operation, DPSK and QAM is used to send 2 or 4 bits of
information respectively at 600 baud to 89027. Since
the QAM coding technique is an inherently synchronous transmission mechanism, during asynchronous
QAM transmission, the asynchronous data is synchronized by adding or deleting stop bits. Following
the synchronization process, the 89026 transmits
digitized phase and amplitude samples to 89027
over a high speed serial link.
89026 OVERVIEW
The 89026 processor performs data manipulation,
signal processing and user interface functions. It
supports an external ROM, for user designed software. This option allows customer designed code to
control the signal processing algorithms resident in
the 89026. For example proprietary modem control
and call progress management applications can be
implemented using EPROMs or alternatively by having it burnt in the processor ROM (done so by Intel
factory contracting). On-Chip ROM is 8 Kbytes. A
block diagram of 89026 is in Figure 5.
In the receive operation, the information is received
by 89026 from 89027 as two Signals which are 90
degrees phase shifted from each other. These analog signals are then digitized by the 89026's onboard AID converter, and using DSP software algorithms the Signals are gain adjusted, adaptively
equalized for telephone line delay and amplitude distortion, and demodulated. Following the demodulation process by the 89026, the data is unscrambled,
and if necessary, returned to asynchronous format.
89026 contains a TTL compatible serial link to DTE/
DCE equipment, along with a full complement of
V.24/RS-232-C control signals. Alternatively, UART
or USART may be used to directly transfer data to
and from a microcomputer bus. The industry standard AT command set is supported by the 89026,
faCilitating communications compatibility between
89024 and most PC software written for the AT com.
mand set.
!.-____
...---------:!-o
---L_ I
COMMAND INTERPRETER
AUTO BAUD-RATE/
DATA FORMAT
DETECTOR
TSYNC
SCLK
SDATA
270242-8
Figure 5. 89026 Block Diagram
4·10
inter
89024
89026 PINOUT
Symbol
Function (89026)
Direction
Pin No.
68 pin
CLKIN
RST
12.96 MHz master clock from 89027
Chip reset (active low)
In
In
67
16
I
Q
STR
ED
In-phase received signal
Quadrature-phase received signal
Symbol Timing from 89027
Energy Detect input
In
In
In
In
11
10
24
9
TSYNC
SDATA
SCLK
Transmitter sync pulse to 89027
Serial Data to 89027
Serial Clock to 89027
Out
Out
Out
35
17
18
OH
SH
RI
AR
Off-Hook control to DAA
Switch-Hook from dataphone
Ring Indicator from DAA
Aux Relay control to DAA
Out
In
In
Out
33
44
42
38
TCL1
TCLO
CONFIG
NVRAM Data 1/0
NVRAM CLK
103/v.21 default option
NVRAMCE
Dumb/Smart mode select
Custom Firmware Disable
1/0
Out
In
Out
In
In
20
19
15
21
6
8
TM
Test Mode Indicator
Out
39
TXD
RXD
RTS
CTS
DSR
DCD
DTR
RCLK
TCLK
XTCLK
SS
REMLB
LCLLB
Transmitted data from DTE
Received data to DTE
Request to send from DTE
Clear to Send to DTE
Data Set Ready to DTE
Data Carrier Detect to DTE
Data Termina'i Ready from DTE
Received clock to DTE
Transmit clock to DTE
External timing clock from DTE
Speed Indicator to DTE
Speed select from DTE(4)
Remote Loopback Command from DTE
Local Loopback Command from DTE
In
Out
In
Out
Out
Out
In
Out
Out
In
Out
In
In
In
27
29
22
23
30
31
25
34
28
26
32
5
7
4
Vee
VPD
VREF
VSS1
VSS2
AGND
VSSS
Positive power Supply ( + SV)
Ram back-up power
AID converter reference
Digital ground
Digital ground
Analog ground
Back-bias generator output
+5V
+SV
+5V
GND
GND
AGND
Out
1
14
13
36
68
12
37
EA
ADO-AD15
AA
JS
External Memory enable
External memory access address/data(5)
Auto Answer
Jack Select
In
1/0
Out
Out
BIC
SIft.
DIS
ST
4-11
2
60-45
60
59
inter
89024
89026 PINOUT (Continued)
Symbol
Function (89026)
Direction
NMI
X2
CLKOUT
TEST
INST
ALE
RO
READY
BHE
WR
No-maskable Interrupt(Vss)(1)
Crystal output(NC)(2)
Clk output (NC)(2)
Factory test(Vcc)(3)
External memory instruction fetch
Address latch enable
External memory read
Ex1ernal memory ready(Vcc)(3)
Ex1ernal memory bus high enable
Ex1ernal memory write
Pin No.
68 pin
In
Out
Out
In
Out
Out
Out
In
Out
Out
3
66
65
64
63
62
61
43
41
40
NOTES:
1. Pins marked with (VSS) must be connected to VSS.
2. Pins marked with (NC) are to be left unconnected.
3. Pins marked with (Vecl must be connected to Vee.
4. SS pin reserved for future use.
5. With internal ROM enabled, ADO-AD1 are used as AA and JS.
DCD
In async operation, OCO remains Low regardless of
data carrier (default), or it can be programmed to
indicate received carrier signal is within the required
timing and amplitude limits. In sync operation Low
indicates the received carrier signal is within the required timing and amplitude limits.
89026 PIN DESCRIPTION
XTCLK
Transmitter timing from OTE, when external clock
option is selected.
TXD
The serial data from OTE to be transmitted on the
line. A logic 'high' is mark. In synchronous mode,
89026 samples this data on the rising edges of
TCLK.
DSR
Low indicates modem is off-hook, and it is in data
transmission mode, and the answer tone' is being
exchanged. CTS Low indicates modem is prepared
to accept data.
TCLK
Clock output from 89026 as timing source for data
exchange from OTE to modem. Serial data is read
on the rising edges of the TCLK. This output is High
in asynchronous mode.
RTS
In async mode RTS i~nored. Under command
control, in sync mode RTS can be ignored, or the
modem can respond with a Low on CTS.
RXD
DTR
The serial data to OTE. 'Mark' is a logic High. In
synchronous mode, the rising edge of RCLK occurs
in the middle of RXO.
&00 command will cause the modem to ignore OTR.
For &01 the modem assumes the asynchronous
command state on a Low to High transition of the
OTR circuit. The &02 command does the same as
&01 except the state of OTR will enable/disable
auto answer. A Low to High transition of OTR after
the &03 command will cause the modem to assume
.
the initialization state.
RCLK
Synchronous clock output. Rising edge of RCLK occurs in the middle of each RXO bit. This pin remains
High in asynchronous mode.
VBBS
Blc
This pin to be connected to AGNO through a
0.01 IJ-F capacitor.
Low configures the modem to CCITT V.21. High will
configure the modem to Bell 103, when at 300 bps
speed. This pin only affects the modem in 300 bps
operation.
TM
A Low indicates maintenance condition in the modem.
4-12
inter
89024
TCl1, TClO
REMlB
A logic Low on thi!l pin initiates a remote loopback
condition.
These pins are used as the serial clock and data for
interface to an NVRAM. Refer to Figure 3. TClO is
used to output a clock and serial data is read in on
TCL1.
SI
Selects one of the two data rates or ranges of rates
in the DTE to correspond to the rate in modem. Low
selects the higher rate (2400 CCITT/1200 BELL) or
range of rates. High selects the Low rate or range of
rates.
AR
This Auxiliary r.elay control is for switching a relay for
voice or data calls. High is voice, Low is data.
RI
DIS
A Low Signal from DAA indicates line ringing. This
input is ignored when the modem is configured for
leased line. This signal should follow the ring cadence.
A Low on this pin will indicate the smart mode which
will respond to all commands. A High will ignore all
commands.
OH
VREF
Voltage reference for the analog to digital converter
should be connected to the 89027 AVcc.
Low controls off hook. High indicates on hook.
When dialing, this control is used to pulse dial the
line.
VPD
SH
The internal RAM power down supply voltage to be
connected to 5 Volts during normal operation.
Used as a telephone voice to data switch or vice
versa. Any logic level transition will toggle the modem state. This input is ignored, if a software command attempts to switch the modem between voice
and data.
sf!..
The function of this pin is re-defined as external
NVRAM CEo
AA
Used as an indicator for Auto Answer status and
Ring indicator. Active low.
CON FIG
Low indicates availability of custom software modules in off-chip memory.
lCllB
A Low will set the modem in the local analog loopback test mode. Logic Low levels applied simultaneously to REMLB and LCLLB pins, sets the modem
to the local digital loopback.
EA
When High, memory access from address 2000H to
4000H are directed to on-chip ROM. When Low, all
memory access is directed to off-chip memory.
JS
Low is used to pulse A and A1 leads to control a 1A2
Key System jack.
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent dam-.
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this sPecification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
89026 ABSOLUTE MAXIMUM
RATINGS"
TemperatureUnderBias .......... -10to +80·C
Storage Temperature ............ - 40 to + 125· C
Voltage from Any Pin to
Vss or AGND ................. -0.3V to + 7.0V
Average Output Current from Any Pin ....... 10 mA
NOTICE' Specifications contained within the
following tables are subject to change.
Power Dissipation ....................... 1.5 Watts
4-13
89024
OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Units
TA
Ambient Temperature Under Bias
0
+70
C
VCC
Digital Supply Voltage
4.75
5.25
V
VREF
Analog Supply Voltage
4.75
Vcc-·3
5.25
Vcc+· 3
V
V
FREQ
ClKIN Frequency 12.96 Mhz
-0.01%
+0.01%
VPD
Power-Down Supply Voltage
4.75
5.25
V
NOTE:
Vees should be C9nnected to AGND through a 0,01 /-LF capacitor. AGND, Vss and the 89027 Vss, AGND must be nominally
at the same potential.
DC CHARACTERISTICS
Symbol
Min
Max
Units
Vil
Input low Voltage
Parameter
-0.3
+0.8
V
VIl1
Input Low Voltage,RST
-0.3
+0.7
V
VIH
Input High Voltage
2.0
Vee +·5
V
VIH1
Input High Voltage, RST Rising
2.4
Vee +·5
V
VIH2
Input High Voltage, RST Falling
2.1
Vee +·5
V
VIH3
Input High Voltage, NMI, ClKIN
2.4
Vcc +·5
V
VOL
Output low Voltage
0.45
V
See Note 1.
VOH
Output High Voltage
V
See Note 2.
Icc
Vee Supply Current
200
mA
All outputs disconnected
IpD
VPD Supply Current
1
mA
Normal operation and Power-Down
15
mA
±10
p.A
Vin=O to Vee See Note 3
IREF
VREF Supply Current
III
Input leakage Current
IIH
Input High Current to EA
IlL
Input low Current
2.4
Comments
ExceptRST
Except'R'S'f,
NMI,ClKIN
100
p.A
VIH=2.4V
-100
p.A
Vil = 0.45V See Note 4
IIL1
Input low Current to 'R'S'f
-2
mA
Vil =0.45V
11L2
Input low Curr~nt SI A; SR, RI, READY
-50
p.A
Vil =0.45V
Cs
Pin Capacitance (Any Pin to Vss>
10
pF
1 MHz
NOTES:
,
1. IOL = 0.36 mA for pins TClO, TCl1, B/C, RTS, C'fS, DSR, OCD, Si, AR, and OR. Alec if ADO - AD15 are configured as 1/
o ports.
,
IOL = 2.0 mA for TM, ClKOUT, ALE, BRE, RD, WR, RXD, 'i'C[j(, and ADO - AD15 when used as external memory bus.
2.loH = -20 /-LA forJllns TClO, TCL1, B/C, RiS, C'fS, DSR, OCD, Si, AR, and OR.
IOH = -200 /-LA for TM, ClKOUT, ALE, BHE, RD, WR, RXD, TClK, and ADO - AD15 when used as external memory bus.
ADO - AD15 when used as 110 ports, haveEopen-drain outputs. '
3. For pins l5'fR, XTrnJ<, TXD, DI'S, 'S'S, R MlB, lCllB, CONFIG, ADO-AD15.
4. TClO, TCl1, Bic, RTS. 5. Power must be applied to the device in the following sequence: Vss first, then Vco.
4-14
89024
AC CHARACTERISTICS (VCC. VPD
= 4.75 to 5.25 Volts; TA = O·Cto 70·C; ClKIN = 12.96 MHz)
Test Conditions: Load capacitance on output pins = 80 pF
Frequency = 12.96 MHz
Timing Requirements
Symbol
Parameter
TAVDV
TRLDV
Min
Max
Units
Address Valid to Input Data Valid
5Tosc-90
ns
RD Active to Input Data Valid
3Tosc-60
ns
Tosc-20
ns
TRXDX
Data Hold after RD Inactive (1)
TRXDZ
RD Inactive to Input Data Float (1)
0
ns
Timing Responses
Symbol
FXTAL
Parameter
CLKIN Frequency
Min
Max
-0.01%
+0.01%
Units
Tosc
CLKIN Period
TCHCH
ClKOUT Period (1)
3Tosc (2)
3Tosc (2)
ns
TCHCL
CLKOUT High Time
Tosc-20
Tosc+20
ns
ns
77
TCLLH
CLKOUT Low to ALE High
-5
20
ns
TLlCH
ALE Low to CLKOUT High
Tosc-20
Tosc+40
ns
TLHll
ALE Pulse Width
Tosc-25
Tosc+15
ns
TAVLl
Address Setup to End of ALE
Tosc-50
ns
TLLRL
End of ALE to RD or WR active
Tosc-20
ns
TlLAX
Address Hold after End of ALE
Tosc-20
ns
TWLWH
WR Pulse Width
2Tosc-35
ns
TQVWX
Output Data Setup to End of WR
2Tosc-60
ns
TWXQX
Output Data Hold after End of WR
Tosc-25
ns
TWXLH
End of WR to next ALE
2Tosc-30
ns
TRLRH
RD Pulse Width
3Tosc-30
ns
TRHLH
End of RD to next ALE
Tosc-25
ns
NOTES:
(1) This specification is not tested. but is verified by design analysis and/or derived from other tested parameters.
(2) CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc ± 10 nsec if Tosc is constant
and the rise and fall times on XTAL are less than 10 nsec.
4-15
inter
89024
WAVEFORM
ClKIN
I
!-TC'HCH
ClK OUT
--J
-
I
I
~\
I
J
TCHCl
TCllH
TllCH
TLHLL
'.
ALE
"
j
J
TLlRL
,
TRLRH
~
TRHlH
TRXDZ
TAVLL
f-
TLLAX
f-..+
TRXDX
!-TRLDV_
ADDR OUT
AD
\
DATA IN
~
TAVDV
TLLRl
,
TWXLH---.,
!-TWLWH
TAVLL
~
TLLAX
IADDR OUT
AD
SHE. INST
TWXOX
!-TOVWX
"
VALID
DATA OUT
/
270242-9
Figure 6. Bus Signal Timings
4·16
inter
89024
ters, combined with the necessary guard tone,
smoothed by a low pass filter, and transmitted to the
line. Prior to transmitting either FSK or QAM signals
to the telephone line, the 89027 adjusts the signal
gain through an on-board programmable gain amplifier.
89027 OVERVIEW
The 89027 is a 28 pin CMOS analog front end device, which performs most of the complex filtering
functions required in modem transmitters and receivers. A general block diagram of this chip is provided in Figure 7. Most of the analog signal processing functions in this chip are implemented with
CMOS switched capacitor technology. The 89027
functions are controlled by 89026, through a high
speed serial data link.
During the receive operation, the received FSK and
QAM signals are passed through anti-alias filters,
bandsplit filters, automatic gain control and carrier
detect circuits, a Hilbert transform filter, and the output sent to the 89026 processor as analog signals.
During FSK transmit operation, the 89027 receives
digitally synthesized mark and space sinusoid amplitude information from the 89026. The 89027 converts the signal to its analog equivalent, filters it, and
transmits it to the telephone line. For QAM transmission, the signal constellation points are transferred
to the 89027. This information is modulated into an
analog signal, passed through spectral shaping fil-
Other functions provided by the 89027 are: an onboard two wire to four wire circuit with disable capability, an audio monitor output with software configurable gain, and a programmable gain transmit signal.
The 89027 is available in 28 pin plastic DIP and
PLCC packages.
.----------------------------------------------------------------I
r--------___
~--;.AMP
A02
Hya
ED
~------~~------------~
STR +0-----__0---41---1
...--...... '---i+ AO!
"-r--l----r---l---'----r-------Vee Vaa
AGND
Vss
RST
AVee
AZ2
AZ!
OUTPUT LEVEL
TX3-TXO
270242-10
Figure 7_ 89027 Block Diagram
4-17
inter
89024
89027 PINOUT
Direction
Pin No.
+5V
-5V
DGND
AGND
+5
28
15
24
21
7
Xtal Oscillator
Xtal Oscillator
12.96 MHz Clock Output to Microcontrolier
In
Out
Out
23
25
26
RST
HYB
AZ1
AZ2
Chip reset (active low)
Enable on-chip hybrid(1)
Auto-zero capacitor
Auto-zero capacitor
In
In
Out
In
20
10
16
17
SDATA
SCLK
TSYNC
Serial data from 89026
Serial clock from 89026
Transmitter sync from 89026
In
In
In
2
1
3
STR
ED
I
Q
Symbol timing to 89026
Receiver energy detect to 89026
In phase received signal to 89026
Quadrature-phase received signal to 89026
Out
Out
Out
Out
27
18
13
14
A01
A02
AMP
Transmitter output
Receiver input
Output to monitor speaker
Out
In
Out
6
12
11
TXO
TX1
TX2
TX3
Transmitter level control (LSB)(1)
Transmitter level control(1)
Transmitter level control(1)
Transmitter level control (MSB)(1)
In
In
In
In
9
8
5
4
Symbol
Function (89027)
Vee
Vss
Vss
AGND
AVee
Positive Power Supply (Digital)
Negative Power Supply
Digital Ground
Analog Ground
Positive Power Supply (Analog)
X1
X2
CLKOUT
NOTES:
1. When held high, these pins should be connected through 10K resistors to AVec.
2. Pins # 19 and # 22 are No Connect.
A01
89027 Pinout Description
Transmitter output. .
TXO-3
These four pins control the transmitted signal level.
A02
HYB
Receiver input.
This pin enables the on-chip hybrid. A line impedance matching network must be connected between
A01 and A02 when HYB is enabled. If HYB is disabled and an external 4W12W hybrid is used, the
hybrid receive path must be amplified by 6 dB.
This output can be used to monitor the cali progress
tones and operation of the line.
AMP
4-18
inter
89024
ABSOLUTE MAXIMUM RATINGS
Power Dissipation ........................ 1.35W
Temperature Under Bias .......... -10 to + 80° C
Voltage with Respect
to VSS(1) ....................... -0.3V to 6.5V
Storage Temperature ............ - 40 to + 125° C
All Input and Output Voltages
with Respect to Vss .......... - 0.3V to + 13.0V
NOTE:
1. Applies to pins SCLK, SDATA, TSYNC, RST,
All Input and Output Voltages
with Respect to Vee & AVee ..... -13.0V to 0.3V
HYB, TXO-TX3 only.
POWER DISSIPATION Ambient Temp = O°C to 70°C, Vee = AVee = 5V ±5%, Vss = AGND = OV.
Symbol
Parameter
Min
Typ
Max
Units
AlcC1
AVee Operating Current
19
25
mA
ICC1
Vee Operating Current
7
10
mA
Ibb1
Vss Operating Current
-19
-25
mA
Alccs
Vee Standby Current
0.2
1
mA
Iccs
Vee Standby Current
7
10
mA
Ibbs
Vss Standby
-0.6
-2
mA
Pdo
Operating Power Dissipation
225
300
mW
Pds
Standby Power Dissipation
40
70
mW
DC CHARACTERISTICS (Ta = 0°Cto70°C, AVee = Vee = 5V ±5%, Vss = 5V ±5%, AGND =
Vss = OV), supply voltage must be at the same potential as the 89026 power supply. Typical Values are for
Ta = 25°C and nominal power supply values. Power must be applied in the following sequence: Vss, AGND,
Vss, Vee, and AVee. Vee, AVee and 89026 VREF must be nominally at the same potential.
Inputs: TXO, TX1, TX2, TX3, HYB, RST
Outputs: CLKOUT
Symbol
Parameter
Min
Max
Units
Test Condition
Vss :S: Vin :S: Vee
iii
Input Leakage Current
-10
+10
/LA
Vii
Input Low Voltage
Vss
0.8
V
Vih
Input High Voltage
3.0
Vee
V
Vol
Output Low Voltage
0.4
V
Voh
Output High Voltage
V
Ich :S: 50/La, 1 TTL load
Vco1
CLKOUT Low Voltage
0.4
V
C1 = 60 pF
Vcoh
CLKOUT High Voltage
V
C1 = 60 pF
2.4
2.4
4-19
101
~
-1.6mA,1 TTL load
inter
89024
AC CHARACTERISTICS (Ta = 25°C, Vcc = AVcc = 5 V, Vss = AGND = 0, VBB '" -5 V)
ANALOGINPUTS:A02
Parameter
Typ
Min
Max
Units
-9
dBm
A02 Input Voltage Range
A02 Input Resistance
-3.5V
:::>
0
U
V»
'"
0-
V>
'"
...J
(.)
TX2
X2
AOl
vss
Xl
AVee
AGND
TXl
CLKSEL
TXO
RST
TXO
AGND
HYB
CLKOUT2
HYB
RST
A~P
ED
AMP
CLKOUT2
A02
AZ2
I
AZl
Q
vee
-0
N
0
I:D_NC
m NNW
> « «
«
290181-3
290181-2
28 Pin PLCC
28 Pin Plastic DIP
8
~~
~>
o
U
....
N
x
~ IYl~
0
tn~
~~ 10~
Q
ADO
I
ADl
AGNO
AD2
VREF
AD3
V pD
AD4
BIC
ADS
RST
AD6
SDATA
AD7
SClK
AD8
TelO
AD9
TCll
AD10
sli.
ADll
RTS
A012
CTS
A013
STR
A014
OTR
AD1S
XTClK
elKIN2
290181-4
68 Pin PLCC
Figure 2. Device Packages
4-24
inter
89C024XE
dem will initiate a disconnect only after a Y1 command. The optional disconnect requests originated
by the remote modem, are of two types, (1) disconnect when receiving long-space, and (2) disconnect
when received carrier is dropped. The modem chipset can also be configured to transmit 'long-space'
just before disconnection, in each of the aforementioned cases.
CALL ESTABLISHMENT,
TERMINATION AND RETRAIN
The 89C024XE modem system incorporates all protocols and functions required for automatic (or manual) establishment, progress and termination of a
data call.
The modem chip-set has a built in auto-dialer, both
DTMF and Pulse type, and is capable of automatically adapting to the telephone dial type. The dialing
sequence on the telephone link conforms to the
CCITT V.25 recommendations. An exception to the
V.25 is that the interrupted calling tone will not be
transmitted by the calling modem, as is suggested in
V.22 bis.
Because the CCITT and Bell modem connection
protocols are quite different from each other and do
not provide recognition of remote modem type (Le.
V.22 bis to 212A), the Intel chip-set provides the additional capability of identifying the remote modem
type. This feature is beneficial during the migration
phase of the technology from the 1200 bps to 2400
bps. In North America, where the installed base of
1200 bps modems is mostly made-up of 212A type,
this feature allows a "Data Base Service Provider"
to easily upgrade the existing 212A modems to 2400
bps V.22 bis standard, transparently, to 212A users.
Similarly, a user with a 89C024XE based modem
system can automatically call data bases with either
212A or V.22 bis modems, without concern over the
difference. This feature's benefits are realized in
smooth upgrading of data links, with minimum cost
and reduced disruption in services. Refer to Table 1
for a detailed description of remote modem compatibility.
The modem can detect the dial, busy and ringback
signals at remote end, and will provide call progress
messages to the user. The modem is capable of redialing the last number dialed, by one command.
The modem when configured for auto-answer, will
answer an incoming call, remain silent for the two
second billing delay interval, before transmitting the
answer tones. Afterwards modem to modem identification and handshaking will proceed at a speed and
operating mode acceptable to both ends of the link.
The data call can also be setup by manual dialing
with the modems set to data mode, or by voice to
data transfer by means of mechanical switch (exclusion key), using the SH pin. Once set to data mode,
the modem handshaking will proceed before the
modems will be ready to accept and exchange data.
SOFTWARE CONFIGURATION
COMMANDS
This section lists the 89C024XE commands and registers that may be used while configuring the modem. Commands instruct the modem to perform an
action, the value in the associated registers determine how the commands are performed, and the result codes returned by the modem tell the user
about the execution of the commands.
During data transmission, if one of the modems finds
that the received data is likely to have a high bit error
rate (indicated by a large mean square error in the
adaptive equalizer), it initiates a retrain sequence.
This automatic retrain feature is only available at
2400 bps, and conforms to CCITT V.22 bis recommendations.
The commands may be entered in a string, with or
without spaces in between. Any spaces within or between commands will be ignored by the modem.
During the entry of any command, the 'backspace'
key (CNTRl H) can be used to correct any error.
Upper case or lower case characters can be used in
the commands. Commands described in the following paragraphs refer to asynchronous terminals using ASCII codes.
Disconnection of the data call can be initiated by the
DTE at the local end, or by the remote DTE, (if the
modem is configured to accept it). Whether DTR will
initiate a disconnect, depends on the last &D command. Receiving a long space from a remote mo-
4-25
89C024XE
Table 1: Remote Modem Compatibility
Originating
89C024XE
Modem
Bell
CCITT
300
1200
300
600
1200
2400
Answering
89C024XE
Modem
Bell
CCITT
300
1200
300
600
1200
2400
Bell
300
Bell
1200
300
1200'
300
1200
-
Answer Modem
CCITT
CCITT
300
600
-
-
300
-
1200'
1200'
1200
1200
Bell
300
Bell
1200
300
300
1200
1200
300'
300'
600
-
Originating Modem
CCITT
CCITT
300
600
-
-
300
-
1200
1200
600
-
CCITT
1200
CCITT
2400
300'
1200
300'
1200
-
-
1200
1200
1200
2400
CCITT
1200
CCITT
2400
1200
1200
1200
1200
-
-
1200
1200
1200
2400
• These connection data rates are obtained when connecting 89C024XE based modems end to end. The same results may
not be obtained when a 89C024XE based modem is connected to other modems.
& Command Set (Continued)
Command Set
AT
A
AI
Bn
Ds
En
Hn
In
Ln
Mn
0
On
Sn=x
Sn
Vn
Xn
Yn
2
+++
Attention code.
Go off-hook in answer mode
Repeat previous command string
BELL/CCITT Protocol Compatibility at
1200 bps
The dialing commands
(0-9 ABC D • # P R T S W,; @)
Echo command (En)
Switch-Hook Control
If &J1 option is selected, H1 will also
switch, the auxiliary relay
Request Product Code and Checksum
Speaker Volume
Monitor On/Off
On-Line
Result Codes
Write S Register
Read S Register
Enable Short-Form Result Codes
Enable Extended Result Code
Enable Long Space Disconnect
Fetch Configuration Profile
The Default Escape Code
&C
&D
&F
&G
&J
&L
&M
&P
&R
&S
&T
&W
&X
&2
4-26
DCDOptions
DTR Options
Fetch Factory Configuration Profile
Guard Tone
Telephone Jack Selection'
Leased/Dial-up Line Selection
Async/Sync Mode Selection
Make/Break Pulse Ratio
RTS/CTS Options
DSR Options
Test Commands
Write Configuration to Non Volatile Memory
Sync Clock Source
Store Telephone Number
inter
89C024XE
Dial Modifiers
CONFIGURATION REGISTERS
P
R
T
S
W
The modem stores all the configuration information
in a set of registers. Some registers are dedicated to
special command and function, and others are bitmapped, with different commands sharing the register space to store the command status.
S'
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
•
•
•
•
•
•
•
•
Ring to Answer
Ring Count. (Read Only)
Escape Code Character
Carriage Return Character
Line Feed Character
Back Space Character
Wait for Dial Tone
Wait for Data Carrier
Pause Time for the Comma Dial Modifier
Carrier Detect Response Time
Lost Carrier to Hang Up Delay
Not Used
Escape Code Guard Time
Not Used
Bit Mapped Option Register
Not Used
Modem Test Options
Not Used
Test Timer
Not Used
Not Used
Bit Mapped Options Register
Bit Mapped Options Register
Bit Mapped Options Register
Not Used
Delay to DTR (Sync Only)
RTS to CTS Delay (Half Dup.)
Bit Mapped Options Register
@
Pulse Dial
Originate call in Answer Mode
Tone Dial
Dial a stored number
Wait for dial tone
Delay a dial sequence
Return to command state
Initiate a flash
Wait for quit
If neither P or T is specified in the command
string, the modem automatically selects the
proper dial mode.
Example:
Terminal: AT &Z T 1 (602) 555-1212
Modem: OK
Result:
Modem stores T16025551212 in the external NVRAM.
The number can be dialed from asynchronous mode
by issuing the following command:
Terminal: AT OS
Modem: T16025551212
or by turning on DTR when in Synchronous Mode 2.
Up to 33 symbols (dial digits and dial modifiers) may
be stored. Spaces and other delimiters are ignored
and do not need to be included in the count. If more
than 33 symbols are supplied, the dial string will be
truncated to 33.
APPLICATIONS OVERVIEW
The block diagram of a stand-alone 300 to 2400 bps
Hayes compatible modem is depicted in Figure 3.
The DAA section shown in this diagram may be obtained with FCC registration, or implemented using
the suggested diagram in Figure 4.
NOTE:
• These S registers can be stored in the NVRAM.
4-27
inter
89C024XE
POWER SUPPLY'
DGND
RST
AUDIO
MONITOR
-5 VOLTS
AGND
+5 VOLTS
TELEPHONE LINE
INTERrACE
llii"'''~
XI
u
0
%
..
U
..
" "Vee
~ «
X2
VREF
CLKIN
N89C026XE
ED
STR
I
Q
TSYNC
89027
..'"
%
0
TIP
AZI
CLKOUT
ED
AZ2
STR
AMP
AO.
I
Q
SDATA
TXI
SCLK
SCLK
TX2
CLKOUT2
TX3
en
~
z
iii
~
TRXCAR
.1l
RCVCAR
;!
RING
O.02)"r
A02
TXO
TSYNC
SDATA
CLKIN2
...
DAA
AND
~W/2W
Hya
0
l~~·'
LEVEL
SELECT
%
en
...
...
%
MI
::;
TIP
%
OH
RING ~
t=
AR
MIC
j
SH
Ri
u
u
l;l
~
290181-5
Figure 3. Typical Modem Configuration
MI
.------+-+ TIP
AR~-------------------------------;--~
OH~-------------~
.--+----+--+ RING
AUXILIARY
BUSINESS
PHONE
MIC
10K
.....--++. RING
I:;
~
o
'"
~
TELEPHONE
LINE OR
DATA PHONE
N
o
'"
00
A01
....---lH'" TIP
~+
~--~----------~o
Ri~---------i~D:a~~~~~~O:R~::::::::::::::::~~
--~
SH..
__________________
~~EX~C~L~U~SI~O~N~K~E~Y~:::::::::::::::::::J~
STATE DETECTOR
290181-6
Figure 4. Typical Telephone Line Interface with Built In Hybrid
4-28
89C024XE
SYSTEM COMPATIBILITY SPECIFICATIONS
Parameter
Synchronous
Asynchronous
Specification
2400 bps ± 0.01 %
1200 bps ±0.01 %
600 bps ±0.01%
V.22 bis
V.22 and BELL 212A
V.22A,B
2400, 1200, 600 bps, character asynchronous.
o- 300 bps anisochronous.
Asynchronous Speed Range
+ 1 % - 2.5% default. Extended + 2.3% - 2.5% range of CCITT
standards optional via software customization.
Asynchronous Format
8,9,10,11 bits, including start, stop, parity. Bits 8, 9, 11 optional
via S/W customization.
Synchronous Timing Source
Internal, derived from the local oscillator.
External, provided by DTE through XTCLK.
Slave, derived from the received clock.
Telephone Line Interface
Two wire full duplex over public switched network or 4 wire
leased lines.
On-chip hybrid and billing delay timers.
Output level -1 to -16 dBm
Modulation
V.22 bis, 16 point QAM at 600 baud.
V.22 and 212A, 4 point DPSK at 600 baud.
V.21 and 103, binary phase coherent FSK
Output Spectral Shaping
Square root of 75% raised cosine, QAM/PSK.
Transmit Carrier Frequencies
V.22 bis, V.22, 212A
V.21
Bell 103 mode
Receive Carrier Frequency Limits
V.22 bis, V.22, 212A
V.21
Bell 103
Originate
Answer
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
1200 Hz
2400 Hz
1180 Hz
980 Hz
1850 Hz
1650 Hz
1070 Hz
1270 Hz
2020 Hz
2225 Hz
±
±
±
±
±
±
±
.01 %
.01 %
.01%
.01%
.01 %
.01 %
.01 %
± .01 %
± .01 %
± .01 %
Originate
Answer
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
2400 Hz
1200Hz
1850 Hz
1650 Hz
1180 Hz
980 Hz
2020 Hz
2225 Hz
1070 Hz
1270 Hz
±
±
±
±
±
±
±
±
±
±
7 Hz
7Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz
Energy Detect Sensitivity
Greater than -43 dBm ED is ON. Less than -48 dBm ED is
OFF. Signal in dBm measured at A02.
Line Equalization
Fixed compromise equalization, transmit.
Adaptive equalizer for DPSK/QAM, receive.
Diagnostics Available
Local analog loopback.
Local digital loopback.
Remote digitalloopback.
Local interface loopback.
Self Test Pattern Generator
Alternate 'ones' and 'zeros' and error detector, to be used along
With most loop backs.
A number indicating the bit errors detected is sent to OTE.
4-29
inter
8QC024XE
RECEIVER PERFORMANCE SPECIFICATIONS
Parameter
Specification
Test condition: Unconditioned 3002 line, across the full dynamic range.
The noise bandwidth is 3 KHz flat.
Random Noise
Typical Bit Error rate of 1 in 100000 or better at 12 dB SNR at 300 bps, 5 dB
SNR at 600 bps, 8 dB SNR at 1200 bps and 1'6 dB SNR at 2400 bps.
Frequency Offsets(1)
± 7 Hz.
Phase Jitter(1)
2400 bps - 15° peak to peak, at up to 300 Hz.
600, 1200 bps - 45° peak to peak, at up to 300 Hz.
NOTE:
1. There are no observable data errors for the received signals, for the above limits of line impairments.
These impairments are applied one at a time in absence of noise.
PERFORMANCE SPECIFICATIONS
Parameter
Min
Typ
DTMF Level
Max
Units
dBm
5.0
DTMF Second Harmonic
-35
dB
DTMF Twist (Balance)
3
dB
Default DTMF Duration
100
ms
10
pps
39/61
33/67
%
%
Pulse Dialing Rate
Pulse Dialing Make/Break
Pulse Interdigit Interval
785
2.1
Hz
dB
1800
-6
Hz
dB
Dial Tone Detect Duration
3.0
sec
Ringback Tone Detect
Duration
Cadence'
0.75
1.5
sec
Busy Tone Detect
Duration
Cadence
"
Software Controlled
US
UK, Hong Kong
sec
540
-3
Frequency
Amplitude
HYB enabled into 600n
ms
Billing Delay Interval
Guard Tone Frequency
Amplitude
Comments
atA01
referenced to High
channel transmit.
QAM/DPSK
Modes Only
,
Off/On Ratio
0.2
sec
0.67
1.5
4-30
OffiOn Ratio
inter
89C024XE
signal and transmits them to the 89027 as digitized
amplitude samples. During 1200 and 2400 BPS operation, DPSK and QAM is used to send 2 to 4 bits
of information respectively at 600 baud to the AFE.
Because the QAM coding technique is an inherently
synchronous transmission mechanism, in the case
of asynchronous QAM transmission, the asynchronous data is synchronized by adding or deleting stop
bits. Following the synchronization process, the
89C026XE transmits digitized phase and amplitude
samples to 89027 over the high speed serial link.
89C026XE OVERVIEW
The 89C026XE processor performs data manipulation, signal processing and user interface functions.
It supports external ROM and RAM to perform asynchronous, synchronous, and lor custom code with or
without high level protocol functions. These options
will allow proprietary modem control, functions, call
progress management applications to be implemented. A block diagram of the 89C026XE is provided in Figure 5.
In the receive operation, the information is received
by the 89C026XE from the 89027 as two signals
which are 90 degrees phase shifted from each other. These analog signals are then digitized by the
AID converter resident on the 89C026XE. By using
DSP algorithms, the received signals are processed
using adaptive equalization for telephone line delay,
amplitude distortion and gain adjustment is executed
and the signal demodulated. Following demodulation, the data is unscrambled, and if necessary, returned to asynchronous format.
89C026XE contains a TTL compatible serial link to
DTE equipment, along with a full complement of
V.24/RS-232-C control signals. Alternatively, a
UART or USART may be used directly to transfer
data to and from a microcomputer bus. The industry
standard AT command set is supported by the
89C026XE, facilitating compatability between
89C024XE and most PC software written for the AT
command set.
During transmit operation, the 89C026XE synthesizes DTMF tones and the 300 BPS FSK modem
e.
r------------------L--I
r-------i-Q
p __________________________________________________ . _ . __
I
I
I
I
I
I
COMMAND INTERPRETER
I
I
AUTO BAUD-RATE/
DATA FORMAT
DETECTOR
RXD(103)
TDX(104) ~
TCLK(114)
RCLK(115)
XTCLK( 113) ----1...-.-.+
RTS~ ~el
CTS
DTR
DSR
REMLB(140)
LCLLB(141)
... >-
--'---+ <5 ~
I
'" '"
---r--+ !z ~
8~
SS(lll1~ ~~
51
... en
fM
.... z
~s
oeD
TCLO~ ~~
:;i i3
TCLl
--'---+
S~-+-+
CON FIG
BIS. ---r--+
G~
08
TSYNC
SCLK
SDATA
OH
AR
I
SR~
Ri -..---.
D/S
---:---+
-F;K- ~
MUX
iiMTf ;-ANSWER
FSK
MOD : TONE:
I-:D~A~TA;'-'------------+I
. , GEN.'
TONE
GEN.
:
I
.!-- ED
I
~~~----__- - - -__~::::::::::::::~~~~~~~~:J~STR
~--I---r-l--l---r--l----r---l----------------------------!
RST
EA
VpD
Vee VSS1
VSS2
AGND
Vees
290181-7
Figure 5. 89C026XE Block Diagram
4-31
inter
89C024XE
89C026XE PINOUT
Symbol
Function (89026)
Direction
Pin No.
CLKIN
CLKIN2
RST
12.96 MHz master clock from 89027
270 KHz from 89027
Chip reset (active low)
In
In
In
67
44
16
I
Q
STR
ED
In-phase received Signal
Quadrature-phase received signal
Symbol Timing from 89027
Energy Detect input
In
In
In
In
11
10
24
9
TSYNC
SDATA
SCLK
Transmitter sync pulse to 89027
Serial Data to 89027
Serial Clock to 89027
Out
Out
Out
35
17
18
OH
SH
RI
AR
Off-Hook control to DAA
Switch-Hook from dataphone
Ring Indicator from DAA
Aux Relay control to DAA
Out
In
In
Out
33
5
42
38
TCL1
TCLO
BIC
S/A
D/S
CONFIG
NVRAM Data I/O
NVRAMCLK
103/V.21 default option
NVRAMCE
Dumb/Smart mode select
Custom Firmware Disable
I/O
Out
In
Out
In
In
20
19
15
21
6
8
TM
Test Mode Indicator
Out
39
TXD
RXD
RTS
CTS
DSR
DCD
DTR
RCLK
TCLK
XTCLK
REMLB
LCLLB
Transmitted data from DTE
Received data to DTE
Request to send from DTE
Clear to Send to DTE
Data Set Ready to DTE
Data Carrier Detect to DTE
Data Terminal Ready from DTE
Received clock to DTE
Transmit clock to DTE
External timing clock from DTE
Speed Indicator to DTE
Remote Loopback Command from DTE
Local Loopback Command from DTE
In
Out
In
Out
Out
Out
In
Out
Out
In
Out
In
In
27
29
22
23
30
31
25
34
28
26
32
7
4
Vee
VPD
VREF
VSS1
VSS2
AGND
VeBs
Positive power supply ( + 5V)
Ram back-up power
A/D converter reference
Digital ground
Digital ground
Analog ground
Back-bias generator output
+5V
+5V
+5V
GND
GND
AGND
Out
1
14
13
36
68
12
37
EA
ADO-AD15
AA
JS
External Memory enable
External memory access address/data(5)
Auto Answer
Jack Select
In
1/0
Out
Out
Si
4-32
2
60-45
60
59
intJ
89C024XE
89C026XE PINOUT (Continued)
Symbol
Function (89026)
NMI
X2
CLKOUT
TEST
INST
ALE
RD
READY
BHE
WR
No·maskable Interrupt(Vss)(1)
Crystal output(NC)(2)
Clk output
Factory test(Vcc)(3)
External memory instruction fetch
Address latch enable
External memory read
External memory ready(Vcc)(3)
External memory bus high enable
External memory write
Direction
In
Out
Out
In
Out
Out
Out
In
Out
Out
Pin No.
3
66
65
64
63
62
61
43
41
40
NOTES:
1. Pins marked with (Vss) must be connected to Vss.
2. Pins marked with (NG) are to be left unconnected.
3. Pins marked with (Ved must be connected to Vee.
4. With internal ROM enabled, ADO·AD1 are used as AA and JS.
DCD
89C026XE PIN DESCRIPTION
In async operation, DCD remains Low regardless of
data carrier (default), or it can be programmed to
indicate received carrier signal is within the required
timing and amplitude limits. In sync operation Low
indicates the received carrier signal is within the required timing and amplitude limits.
XTCLK
Transmitter timing from DTE, when external clock
option is selected.
TXD
The serial data from DTE to be transmitted on the
line. A logic 'high' is mark. In synchronous mode,
89026 samples this .data on the rising edges of
TCLK.
DSR
Low indicates modem is off-hook, and it is in data
transmission mode, and the answer tone is being
exchanged. CTS Low indicates modem is prepared
to accept data.
TCLK
Clock output from 89026 as timing source for data
exchange from DTE to modem. Serial data is read
on the rising edges of the TCLK. This output is High
in asynchronous mode.
RTS
In async mode RTS i~nored. Under command
control, in sync mode RTS can be ignored, or the
modem can respond with a Low on GTS.
RXD
DTR
The serial data to DTE. 'Mark' is a logic High. In
synchronous mode, the rising edge of RCLK occurs
in the middle of RXD.
&DO command will cause the modem to ignore DTR.
For &D1 the modem assumes the asynchronous
command state on a Low to High transition of the
DTR circuit. The &D2 command does the same as
&D1 except the state of DTR will enable/disable
auto answer. A Low to High transition of DTR after
the &D3 command will cause the modem to assume
the initialization state.
RCLK
Synchronous clock output. Rising edge of RCLK occurs in the middle of each RXD bit. This pin remains
High in asynchronous mode.
Vees
s/c
This pin to be connected to AGND through a
0.01 fJ-F capacitor.
Low configures the modem to CCITT V.21. High will
configure the modem to Bell 103, when at 300 bps
speed. This pin only affects the modem in 300 bps
operation.
TM
A Low indicates maintenance condition in the modem.
4-33
89C024XE
TCl1, TClO
Sf
These pins are used as the serial clock and data for
interface to an NVRAM. Refer to Figure 3. TCLOis
used to output a clock and serial data is read in on
TCL1.
Selects one of the two data rates or ranges of rates
in the DTE to correspond to the rate in modem. Low
selects the higher rate (2400 CCITT/1200 BELL) or
range of rates. High selects the Low rate or range of
rates.
AR
DIS
This Auxiliary relay control is for switching a relay for
voice or data calls. High is voice, Low is data.
RI
A Low on this pin will indicate the smart mode which
will respond to all commands. A High will ignore all
commands.
A Low signal from DAA indicates line ringing. This
input is ignored when the modem is configured for
leased line. This signal should follow the ring cadence.
Voltage reference for the analog to digital converter
should be connected to the 89027 AVcc.
VREF
OH
VPD
Low controls off hook. High indicates on hook.
When dialing, this control is used to pulse dial the
line.
The internal RAM power down supply voltage to be
connected to 5 Volts during normal operation.
SH
Used as a telephone voice to data switch or vice
versa. Any logic level transition will toggle the modem state. This input is ignored, if a software command attempts to switch the modem between voice
and data.
The function of this pin is re-defined as external
NVRAM CEo
S/A
CON FIG
Low indicates availability of custom software modules in off-chip memory.
AA
EA
Used as an indicator for Auto Answer status and
Ring indicator. Active low.
When high, memory access from address 2000H to
4000H are directed to on-chip ROM. When low, all
Memory access is directed to off-chip memory.
lCllB
A Low will set the modem in the local analog loopback test mode. Logic Low levels applied simultaneously to REMLB and LCLLB pins, sets the modem
to the local digital loopback.
JS
Low is used to pulse A and A 1 leads to control a 1A2
Key System jack.
REMlB
A logic Low on this pin initiates a remote loopback
condition.
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at thfJsfJ or any
othfJr conditions abovfJ thosfJ indicatfJd in thfJ operational sfJctions of this spfJcification is not implifJd. Exposure to absolutfJ maximum rating conditions for
fJxtfJndfJd pfJriods may afffJct dfJvicfJ rfJliability.
89C026XE ABSOLUTE MAXIMUM
RATINGS*
Temperature Under Bias .......... -10 to +800 C
Storage Temperature ............ - 40 to + 1250 C
Voltage from Any Pin to
Vss or AGND ................. -0.3V to + 7.0V
Average Output Current from Any Pin ....... 10 rnA
Power Dissipation ...................... 1.5 Watts
NOTICE: Specifications contained within the
following tables are subject to change.
4-34
inter
89C024XE
OPERATING CONDITIONS
Symbol
TA
Parameter
Min
Max
Units
Ambient Temperature Under Bias
0
+70
C
V
Vcc
Digital Supply Voltage
4.75
5.25
FREQ
CLKIN Frequency 12.96 Mhz
-0.01%
+0.01%
CLKIN2
Frequency 270 KHz
-0.01%
+0.01%
VPD
Power-Down Supply Voltage
4.75
5.25
V
NOTE:
VBBS should be connected to AGND through a 0.01 /LF capacitor. AGND, Vss and the 89027 Vss , AGND must be nominally
at the same pote"tial.
DC CHARACTERISTICS
Symbol
Parameter
Min
Max
Comments
Units
Vil
Input Low Voltage
-0.3
+0.8
V
VIL1
Input Low Voltage,RST
-0.3
+0.7
V
VIH
Input High Voltage
2.0
Vcc +·5
V
VIH1
Input High Voltage, RST Rising
2.4
Vcc +·5
V
VIH2
Input High Voltage, RST Falling
2.1
Vcc +·5
V
VIH3
Input High Voltage, NMI, CLKIN
2.4
V cc +·5
V
VOL
Output Low Voltage
VOH
Output High Voltage
Icc
V cc Supply Current
55
mA
All outputs disconnected
IpD
VPD Supply Current
1
mA
Normal operation and Power-Down
IREF
VREF Supply Current
III
Input Leakage Current
IIH
Input High Current to EA
III
Input Low Current
0.45
2.4
ExceptRST
Except RST,
NMI,CLKIN
V
See Note 1.
V
See Note 2.
15
mA
±10
/J- A
Vin=O to Vcc See Note 3
100
/J- A
VIH=2.4V
-100
/J-A
Vil = 0.45V See Note 4
IIl1
Input Low Current to RST
-2
rnA
Vil =0.45V
IIl2
Input Low Current SI A, SH, RI, READY
-50
/J- A
Vil =0.45V
Cs
Pin Capacitance (Any Pin to V ss)
10
pF
1 MHz
NOTES:
1. IOL = 0.36 mA for pins TClO, TCl1, B/C, RTS, CTS, DSR, DCD, Sf, AR, and 00. Also if ADO - AD15 are configured as 1/
o ports.
IOL = 2.0 mA for TM, ClKOUT, ALE, BHE, RD, WR, RXD, TClK, and ADO - AD15 when used as external memory bus.
2. IOH = - 20 /LA fo~s TClO, TCl1, B/C, RTS, CfS, DSR, DCD, Sf, AR, and OH.
IOH = -200 /LA for TM, ClKOUT, ALE, BHE, RD, WR, RXD, TClK, and ADO - AD15 when used as external memory bus.
ADO - AD15 when used as I/O ports, have open-drain outputs.
.
3. For pins DTR, XTClK, TXD, D/S, REMlB, lCllB, CONFIG, ADO-AD15.
4. TelO, TCl1, B/C, RTS.
5. Power must be applied to the device in the following sequence: Vss first, then Vee.
4-35
89C024XE
A.C. CHARACTERISTICS vee. VPD =
4.75V to 5.25V; TA = O·C to 70·C; CLKIN = 12.96 MHz
Test Conditions: Load capacitance on output pins
Tose = 1/12.96 MHz
=
80 pF
The memory system must meet these specifications to work with 89C026XE
Symbol
Parameter
TAVYV
Address Valid to READY Setup
TLLYV
ALE Low to READY Setup
TYLYH
Non READY Time
TeLYX
READY Hold after CLKOUT Low
hLYX
READY Hold after ALE Low
Min
Max
Units
2Tose-75
ns
Tose- 72
No upper limit
Notes
ns
ns
0
Tose- 3O
ns
(Note 1)
Tose- 15
2Tose-4O
ns
(Note 1)
TAVGV
Address Valid to Buswidth Setup
2Tose-7O
ns
hLGV
ALE Low to Buswidth Setup
Tosc- 7O
ns
ns
TeLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
0
3Tose-6O
TRLDV
RS Active to Input Data Valid
Tose- 23
ns
TeLDv
CLKOUT Low to Input Data Valid
Tose- 5O
ns
TRHDZ
End of RD to Input Data Float
Tose- 2O
ns
TRXDX
Data Hold after RD Inactive
0
NOTES:
1. If max is exceeded, additional wait states will occur.
4-36
ns
ns
intJ
89C024XE
The 89C026XE will meet these specifications:
Symbol
Min
Max
Units
Notes
CLKIN Frequency
12.95870
12.96129
MHz
12.96 ± 0.01 %
FCLKIN2
CLKIN2 Frequency
269.973
270.027
KHz
270 ±0.01%
TXHCH
XTAL 1 High to CLKOUT High or Low
40
110
ns
(Note 1)
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
Tosc+10
ns
FCLKIN
Parameter
ns
2Tosc
Tosc-10
TCLLH
CLKOUT Falling Edge to ALE Rising
-5
15
ns
TLLCH
ALE Falling Edge to CLKOUT Rising
-15
15
ns
TLHLH
ALE Cycle Time
TLHLL
ALE High Period
Tosc-10
TAVLL
Address Setup to ALE Falling Edge
Tosc-15
ns
TLLAX
Address Hold after ALE Falling Edge
Tosc-35
ns
TLLRL
ALE Falling Edge to RD Falling Edge
Tosc-40
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAX
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling Edge
TCLWL
CLKOUT Low to WR Rising Edge
ns
4Tosc
10
Tosc+ 10
ns
30
Tosc+25
ns
ns
25
ns
TQVWH
Data Stable to WR Rising Edge
TCHWH
CLKOUT High to WR Rising Edge
TWLWH
WR Low Period
Tosc-30
ns
TWHQX
Data Hold after WR Rising Edge
Tosc-10
ns
TWHLH
WR Rising Edge to ALE Rising Edge
Tosc-10
TWHBX
SHE, INST HOLD after WR Rising Edge
Tosc-10
ns
Tosc-20
-10
(Note 2)
ns
10
Tosc-10
0
ns
ns
Tosc-5
Tosc
ns
10
Tosc+ 15
ns
ns
(Note 2)
ns
NOTES:
1. This specification is not tested, but is verified by design analysis and/or derived from other tested parameters.
2. Assuming back-to-back bus cycles.
4-37
inter
89C'024XE
WAVEFORM
CLKIN
CLKOUT
ALE
-1--- tLLRL -+1--
rBUS
tAVLL - I o f - ADDRESS OUT
;< tAVDVtLLWL
290181-8
Figure 6. Bus Signal Timings
4·38
89C024XE
shaping filters, combined with the necessary guard
tone, smoothed by a low pass filter, and transmitted
to the line. Prior to transmitting either FSK or QAM
signals to the telephone line, the 89027 adjusts the
signal gain through an on-board programmable gain
amplifier.
89027 OVERVIEW
The 89027 is a 28 pin CMOS analog front end device, which performs most of the complex filtering
functions required in modem transmitters and receivers. A general block diagram of this chip is provided in Figure 7. Most of the analog signal processing functions in this chip are implemented with
CMOS switched capacitor technology. The 89027
functions are controlled by 89C026XE, through a
high speed serial data link.
During the receive operation, the received FSK and
QAM signals are passed through anti-alias filters,
bandsplit filters, automatic gain control and carrier
detect circuits, a Hilbert transform filter, and the output sent to the 89C026XE processor as analog signals.
During FSK transmit operation, the 89027 receives
digitally synthesized mark and space sinusoid amplitude information from the 89C026XE. The 89027
converts the signal to its analog equivalent, filters it,
and transmits it to the telephone line. For QAM
transmission, the signal constellation pOints are
transferred to the 89027. This information is modulated into an analog signal, passed through spectral
Other functions provided by the 89027 are: an onboard two wire to four wire circuit with disable capability, an audio monitor output with software configurable gain, and a programmable gain transmit signal.
The 89027 is available in 28 pin plastic DIP and
PLCC packages.
.-------------------------------------------------------------.--I
....-----+--i+ AMP
A02
HYB
t - -...... AOl
.-r--l- --T---T- -'---T--- --- -Vee
vee
AGND
vss
RST
AVee
AZ2
AZl
OUTPUT LEVEL
TX3-TXO
290181-9
Figure 7. 89027 Block Diagram
4-39
89C024XE
89027 PINOUT
Symbol
Vee
Function (89027)
Direction
Pin No.
+5V
-5V
DGND
AGND
+5
28
15
24
21
7
AVee
Positive Power Supply (Digital) .
Negative Power Supply
Digital Ground
Analog Ground
Positive Power Supply (Analog)
X1
X2
CLKOUT
CLKOUT2
Xtal Oscillator
Xtal Oscillator
12.96 M Hz Clock Output to 89C026XE
270 KHz Clock Output to 89C026XE
In
Out
Out
Out
23
25
26
19
RST
HYB
AZ1
AZ2
Chip reset (active low)
Enable on-chip hybrid (1)
Auto-zero capacitor
Auto-zero capacitor
In
In
Out
In
20
10
16
17
SDATA
SCLK
TSYNC
Serial data from 89C026XE
Serial clock from 89C026XE
Transmitter sync from 89C026XE
In
In
In
2
1
3
STR
ED
I
Q
Symbol timing to 89C026XE
Receiver energy detect to 89C026XE
In phase received signal to 89C026XE
Quadrature-phase received signal to 89C026XE
Out
Out
Out
Out
27
. 18
A01
A02
AMP
Transmitter output
Receiver input
Output to monitor speaker
Out
In
Out
6
12
11
TXO
TX1
TX2
TX3
Transmitter level
Transmitter level
Transmitter level
Transmitter level
In
In
In
In
9
8
5
4
VBB
Vss
AGND
control (LSB) (1)
control(1)
control (1)
control (MSB)(1)
13
14
NOTE:
1. When held high, these pins should be connected through 10K resistors to AVGL
A01
89027 Pinout Description
Transmitter output.
TXO-3
A02
These four pins control the transmitted signal level.
The output level can be adjusted from -1 dBm to
-16 dBm in 1 dB steps.
Receiver input.
HYB
AMP
This pin enables the on-chip hybrid. A line impedance matching network must be connected between
A01 and A02 when HYB is enabled. If HYB is disabled and an external 4W/2W hybrid is used, the
hybrid receive path must be amplified by 6 dB.
This output can be used to monitor the call progress
tones and operation of the line.
4-40
inter
89C024XE
ABSOLUTE MAXIMUM RATINGS
Power Dissipation ........................ 1.35W
Temperature Under Bias .......... -10 to + 80° C
Storage Temperature ............ -40 to + 125° C
Voltage with Respect
to VSS(l) ....................... -0.3V to 6.5V
All Input and Output Voltages
with Respect to Vss .......... - 0.3V to + 13.0V
All Input and Output Voltages
with Respect to Vee & AVee ..... -13.0V to 0.3V
NOTE:
1. Applies to pins SCLK, SDATA, TSYNC, RST,
HYB, TXO-TX3 only.
POWER DISSIPATION Ambient Temp = 00t070°C,Vee= AVee= 5 ± 5%,Vss= AGND= O.
Symbol
Parameter
Min
Typ
Max
Units
19
25
mA
AlcCl
AVee Operating Current
ICCl
Vee Operating Current
7
10
mA
Ibbl
Vss Operating Current
-19
-25
mA
Alccs
AVee Standby Current
0.2
1
mA
Iccs
Vee Standby Current
7
10
mA
Ibbs
Vss Standby Current
-0.6
-2
mA
Pdo
Operating Power Dissipation
225
300
mW
Pds
Standby Power Dissipation
40
70
mW
DC CHARACTERISTICS (Ta=O°C to 70°C, AVee = Vee = 5V ±5%, Vss = 5V ±5%, AGND =
Vss = OV), supply voltage must be at the same potential as the 89C026XE power supply. Typical Values are
for Ta = 25°C and nominal power supply values. Power must be applied in the following sequence: Vss,
AGND, Vss, Vee, and AVee. Vee, AVee and 89C026XE VREF must be nominally at the same potential.
Inputs: TXO, TX1, TX2, TX3, HYB, RST
Outputs: CLKOUT
Symbol
Parameter
Min
Max
Units
Test Condition
Iii
Input Leakage Current
-10
+10
!LA
Vss s Vin s Vee
Vii
Input Low Voltage
Vss
0.8
V
Vih
Input High Voltage
2.0
Vee
V
Vol
Output Low Voltage
0.4
V
Voh
Output High Voltage
Veol
CLKOUT Low Voltage
Vcoh
CLKOUT High Voltage
2.4
0.4
2.4
4·41
101
~
-1.6mA,1 TTL load
V
Ich s 50 !La, 1 TTL load
V
Cl
V
Cl = 60 pF
=
60 pF
89C024XE
AC CHARACTERISTICS (Ta = 25·C, Vcc = AVcc = 5 V, Vss = AGND = 0, VBB = -5 V)
ANALOGINPUTS:A02
Parameter
Typ
Min
Max
Units
-9
dBm
A02 Input Voltage Range
A02 Input Resistance
-3.5V-I
II
I
~1_TD0N2
270073-3
Figure 3. General SLD Timing
5-3
intJ
SLD INTERFACE SPECIFICATION
General SLD Timing
Symbol
Parameter
Min
Typ
Max
Unit
150
ns
0
ns
200
ns
TOSM
Data Setup Time, Master(1)
TOHM
Data Hold Time, Mastedl)
Toss
Data Setup Time, Slave
150
TOHS
Data Hold Time, Slave
TOOFFI
SDIR to Slave Data High Z
TOONl
SDIR to Master Data On
70
ns
TOOFF2
Master Data High Z to SDIR
20
ns
TOON2
SDIR to Slave Data On
0
ns
TOIRR
Sel to SOIR Rising Edge(2)
-150
TOIRFR
Sel Rising Edge to SDIR Falling Edge(2)
-150
SOIR Falling Edge to Sel Falling Edge(2)
200
Sel Outy Cycle(3)
30
TOIRFF
ns
50
Sel Frequency(4)
100
ns
ns
ns
50
70
%
512
514.7
KHz
50
ns
Rise and Fall Times, All Signals
125
SOIR Period
ns
fJ-s
NOTES:
1. SLO master can receive on falling or rising edges.
2. It is the responsibility of the master to control SOIR properly to allow reception of data at SLO turn-around pOints. The
TOI R times above do not guarantee data reception on both rising and falling edges.
3. Not all slave devices will accept this duty cycle range. Refer to the timing for the specific slave devices the master will
interface with.
4. SCl may be 514.7 KHz (instantaneous) for 1.544 MHz system clocks. However. not all slave devices will accept this.
Refer to the timing for the specific slave devices the master will interface with. SCl must have 64 pulses per SOIR cycle in
any case.
5-4
inter
iATC 29C48
FEATURE CONTROL COMBO
External and User Programmable
• Transmit
and Receive Gain
Programmable External Hybrid Balance
• Network
Select
Programmable Analog, Digital, and
• Subscriber
Loopback
Programmable p.1 A-Law Select
• Secondary
Input Channel
• Low PowerAnalog
• External ToneConsumption
to Receive Path
• SLD AlB ChannelInjection
• Channel Line Cards)Select (for 16
The Intel iATC 29C48 Feature Control Combo is a low cost, user-programmable, fully integrated PCM Codec
with transmit/receive filters fabricated in a CMOS technology. This te'chnology is built on CHMOS and will
allow the 29C48 to realize the same excellent transmission performance as in the Intel 2913/2914 combo
while achieving the low power consumption typical of CMOS circuits.
The 29C48 supports the analog subscriber with a variety of added per-line features to the normal BORSCHT
functions associated with the analog line circuit. Some of these features include-secondary analog input
channel, programmable transmit and receive gain, custom hybrid balancing network selection, and programmable ,.., or A-law conversions. Additionally, the 29C48 can operate on either the A or B channel of the SLD
interface, allowing two combos to be connected to one SLD link. In order to facilitate the SLiC interface in this
configuration, the 29C48 generates SLiC' chip select signals for the proper routing of signaling information.
A unique feature of the 29C48 is programmable tone injection. This feature and its SLD interface makes it
particularly easy to use in conjunction with Intel's advanced tranceivers, such as the iATC 29C53AA, in
subscriber equipment environments. The 29C53AA handles transfer of voice and feature control information
to the 29C48.
Plastic Leaded Chip Carrier
&
I9S=~;
18-Lead Plastic Dual-In-Llne Package
VBB
VFR
EBN3IT1
EBN2
EBNl
EBN
ses
B/A
ONDD
NC'
NC
E8N2
NC
NC
NC
E8Nl
E8N
NC
vee
VFX
TOI
T02
ONDA
SAl
SLD
SDIR
seL
270153-1
TGI
TG2
NC
NC
NC
GNDA
SAl
NC
SLD
I~
'Not connected
I;
CI
...
a:
§l ~ ~
III
270153-26
Figure 1. Pin Configurations
October 1988
5-5
Order Number: 270153-004
iATC29C48
TRANSMIT GAIN ADJUST
~
~--+-.(lSAI
PROGRAMMABLE
BALANCE NETWORK
GAIN (1 or 2)
v,..
BALANCE
NETWORK
ENABLE
EIN
piA LAW
Bli
EBN1
FEATURE
CONTROL
REGISTERS
AND LOGIC
:k
ElM2
Tl/EBN3
SCL
SOIR
SLO
BALANCE
NETWORKS
SELECTION
UNIT
SCi
VFR
0-+-"'---<
RECEIVE PROGRAMMABLE GAIN
vee
VBB
GNDA
GNOD
270153-2
Figure 2. Block Diagram
5-6
inter
iATC29C48
Table 1. Pin Names
VFX
VFA
GNDD
GNDA
VCC
Analog Input
Analog Output
Digital Ground
Analog Ground
Power (+5V)
SCL
SLD
SDIA
TG1, TG2
EBN1f2
VBB
Power (-5V)
EBN3fTI
BfA
Channel Selection
SLiC Chip Select
EBN
SAl
SCS
Subscriber Clock
Subscriber Data Link
Subscriber Direction
Transmit Gain Adjust
External Balance Network
Selection Inputs
External Balance Network
Selection Input Or Tone
Injection
External Balance Input
Secondary Analog Input
Table 2. Pin Description
Symbol
Function
VCC
Most positive supply; input voltage is + 5V ± 5 %.
VBB
Most negative supply; input voltage is - 5V
GNDA
Analog ground return line. Not internally connected to GNDD.
GNDD
Digital ground return line. Not internally connected to GNDA.
± 5 %.
VFX
Analog voice input to transmit channel. Input impedance is typically larger than 100 K.n.
TG1
Inverting input to transmit gain adjusting op-amp. Feedback point for external gain adjusting
resistor network or frequency compensation network. Input impedance is typically larger than
10 M.n.
TG2
Output of the transmit gain adjusting op-amp. Will drive external gain adjusting resistor network as
well as frequency compensation network with an impedance of at least 10 K.n.
VFA
Aeceive voice output. Capable of directly driving transformer hybrids or impedance loads of 600 .n.
EBN
Input to the hybrid balancing circuit. Input impedance is typically larger than 10 MO.
EBN1
Input connected to a grounded switch. The switch's on resistance is not greater than 600 .n.
EBN2
Input connected to a grounded switch. The switch's on resistance is not greater than 600 .n.
EBN3fT1 This pin is multiplexed according to the feature control registers. When programmed to be EBN3, it
is an input connected to a grounded switch. The switch's on resistance is not greater than 600 .n. If
this pin is programmed to be TI, an analog signal applied on this pin will be added to the received
voice signal before the receive power amplifier.
SCL
Subscriber clock. This is an input which should be 512 KHz with a duty cycle ranging from 25 % to
75%. Input wi" accept TTL levels.
SDIA
Subscriber direction signal and frame sync input. When high, SLD becomes an input and data is
received by the 29C48. When low, the output buffer on the 29C48 SLD pin is enabled and data is
transmitted by the 29C48. Input will accept TTL levels.
SLD
Subscriber Line Datalink. A 512 Kbps bi-directional serial data port, which is clocked by SCL. SLD
becomes a TTL compatible input when SDIA is high and an output capable of driving one TTL load
when SDIA is low, during the appropriate SLD fields for the assigned channel.
BfA
Pin strapped to assign the 29C48 to process either A or B channel information from the SLD bus. A
low level (GNDD) on this pin selects channel A, a high level (VCC) channel B.
SCS
This pin is a TTL compatible output capable of driving one TTL load: when low, it informs a SLiC
device connected to the same SLD bus as the 29C48 that it can process the receive and transmit
signaling data of the present SLD frame.
SAl
Secondary analog input.
5-7
inter
iATC29C48
(See Figure 3 for a typical ISDN subscriber equipment application.)
FUNCTIONAL DESCRIPTION
The 29C48 is a combined channel filter and PCM
codec for use in ISDN subscriber equipment or analog line interface circuit boards in digital switching
systems.
For analog line interface circuit boards this device
resides between the circuitry which provides the
"BORSHT" functions for a given line, and the
shared line board controller. It provides the transmit
and receive voice-path filtering and companded analog-to-digital and digital-to-analog conversions necessary to interface a full duplex voice telephone circuit with the PCM highways of a time division multiplexed (TOM) system. (See Figures 4a and 4b for
typical line card applications.)
The 29C48 incorporates features which make it particularly suited to subsc:riber applications. Tone .injection allows easy implementation of DTMF feedback and side tone injection, and secondary analog
signal input allows remote control and monitoring.
SUBSCRIBER EQUIPMENT I
"s" INTERFACE
I
L
C
SCL
VFX
SDIR
29C41
29C53AA
SLD
VFR
270153-5
Figure 3. Subs~rlber Equipment
_.
~L
SLiC (.,6)
COMBD(.'6)
VFX
VFAU:S
SUCIA
Ci
SLD BUS (xl)
SELECT
~L
SCL
SOIR
L
.
SLDO
.
VFX· 29C46
OB
VFR
••
I - - 10M HWYS
LINE
CARD.
CONTROLLER
I-BlA SELECT
SIGNALING
"I)I
VI
f - - SIG HWY
I - - SYNC
SLD7-:-
scs
Ci
SUCOB
BACKPLANE
___ BlA
SCi
f~
,....
LCC(.')
~~
p.P
270153-3
Figure 4a. Analog Line Card with Discrete or Electronic Parallel Control SLiCs
5-8
intJ
IATC29C48
SUC(Xlll
:IT
COIlllO (xlII
VFX
SUCOA
CS
VFR
SCS
a.:::
LCC(xll
SLD BUS (xiI
I--SE~CT
SCL
SDIR
SLDO
~ TOIl
.•
:ft
Ci
sucoa
SCS_
VFX 08
VFR
BACKPUNE
SLD7~
i--BlA SELECT
UNECARD
CONTROLLER
HWYS
~ SIG HWY
I-- SYNC
~,..
"
.
r--"---,
IL _ _
lAP_ _ ...JI
270153-4
Figure 4b. Analog Line Card with SLD Compatible SLiCs
TRANSMIT AND RECEIVE
OPERATION
Decoding
The PCM word received on the SLO lead (first or
second byte of the receive half-frame, depending
upon the channel assignment of the device) is sent
to the decoder after a serial to parallel conversion.
The decoded value is held on an internal sample
and hold capacitor.
Transmit Filter
A low pass anti-aliasing section is included on chip.
This section typically provides 35 dB attenuation at
the sampling frequency. No external components
are required to provide the necessary anti-aliasing
function for the switched capacitor section of the
transmit filter.
Receive Filter
The receive seotion of the filter provides a passband
flatness and stopband rejection which fulfills the
AT&T 03/04 specification and the CCITT G.714
recommendation. It also provides additional loss at
12 KHz and 16 KHz. The receive filter transfer characteristics and specifications will be within the limits
shown in Figure 13.
The passband section provides flatness and stopband attenuation which fulfills the AT&T 03/04
specification and the CCITT G.714 recommendation. The 29C48 specifications meet the digital class
5 central office switching systems requirements. The
transmit filter transfer characteristics and specifications will be within the limits shown in Figure 12.
A high pass section configuration rejects low fre- '
quency noise from 50 and 60 Hz power lines, 17 Hz
European electric railroads, ringing frequencies and
their harmonics, and other low frequency noise. The
transmit filter also provides additional loss at 12 KHz
and 16 KHz to support metering pulses.
Encoding
The output of the transmit filter or the secondary
analog input is internally sampled by the encoder
and held on an internal sample and hold capacitor.
OC offset is corrected by an on-chip auto zero circuit. The signal is then encoded and presented as
PCM data on the SLO lead. (First or second byte of
the transmit half-frames depending upon the channel assignment of the device.)
GENERAL OPERATION
External Gain Setting
Both transmit and receive gain levels can be modified by external resistors during line card assembly.
The value of transmit gain is adjusted by connecting
resistors RT1 and RT2 (see Figure 5) at the two external gain setting control pins, TG1 and TG2. These
two pins are the input and output of ~n on-board
gain amplifier stage, and the resistors provide the
necessary input and feedback for gain control. External gain of up to 20 dB can be set, without degrading the performance of the amplifier. The value of
external gain is given by:
A = 1
+
RT1/RT2
For unity gain, pins TG1 and TG2 are tied together.
5-9
inter
iATC29C48
For the receive section, the external gain can be set
by the external resistors, RR1 and RR2. There are
two possible ways of implementing the gain control.
The first is illustrated in Figure 6a, where the value of
the receive gain is given by:
A = RR2/(RR1
+
filtered input channel. Narrow band analog signals
can be supplied through this channel for remote
loop testing and various control uses.
The secondary analog input channel is accessed under software control through the SAl input. When the
SAlE bit in the feature control register #3 is set to a
RR2)
The value of RR1 + RR2 should not be less than
6000 to avoid degrading the output power stage's
performance. The second way of implementing the
receive gain is shown in Figure 6b, where pin EBN3/
T1 is used. The value of the receive gain in this configuration is given by:
A = 1
+
An
-=
ATl
TG2
TGl
VFX o-J----,~--l
RR1/RR2
Hybrid Balancing Network
270153-6
Three external balancing networks can be applied to
the 29C48 by the user to accommodate varying subscriber loop characteristics (see Figure 7 for external
connections). Feature control allows the grounding
of any combination of these networks in order to
best suit a particular application. Feature control
also allows the user to select a gain of 0.0 or + 6.0
dB in the balance Signal path to suit the type of SLIC
used.
Figure 5. Transmit Gain Setting
29C48
VFR
RR1
FREQUENCY COMPENSATION
RR2
The user may, if desired, compensate for the frequency response characteristics of the SLIC by adjusting the frequency response of the transmission
chain. This can be accomplished in the same way as
the external gain setting is done in the transmit and
receive directions. But, instead of using purely resistive impedances, resistor and capacitor networks
have to be used to achieve complex impedances.
The two compensation schemes are shown in Figures 8a and 8b. The gains in the transmit and re- .
ceive directions are respectively:
-=
270153-7
Figure 6a. Receive Gain Setting
29C48
VFR
RR1
for Figure 8a
A
= 1 + ZX1/ZX2
for Figure 8b
A
= 1 + ZR1/ZR2
EBN3m
RR2
-=
SECONDARY ANALOG INPUT
270153-8
Figure 6b, Receive Gain Setting
Although the main application of the 29C48 will be
for voice transmission, it also offers a secondary un-
5-10
inter
IATC29C48
logical one, the 29C48 will encode and transmit the
Signal present at the SAl input. The 29048 will
switch back to transmission of the voice Signal as
soon as the SAlE bit is set back to a logical zero.
TONE INJECTION
When specified by the feature control memory, an
audio frequency signal applied to the EBN3/T1 pin
will be added to the receive voice signal at the power amplifier. This feature allows easy implementation
of DTMF feedback and side tone injection in ISDN
telephone applications, as well as injection of call
waiting or metering tones in line card applications. A
typical application is shown in Figure 9. Here VFR is
the combination of the receive voice signal (VO) and
two tones (V1 and V2).
VFR = 2VO - (V1
270153-9
+ V2)/2
Figure 7. Balance Networks
CHANNEL ASSIGNMENT
Two 29048s can be attached to the same SLD line
to exchange information with the SLD master during
each SLD frame.
The BIA pin of the 29048 is used to assign a voice
channel of the SLD frame to the device. When the
BIA pin is tied low, the 29C48 operates as an Achannel combo, receiving and tranSmitting voice
during the first and fifth bytes of the SLD frame.
When this pin is tied high, the 29C48 operates as a
B-channel combo, receiving and transmitting voice
during the second and sixth bytes of the SLD frame.
270153~10
Figure Sa. Transmit Frequency Compensation
VFR
110
EIN3ITI
2110
270153-11
V1--JVVY-_
2110
Figure ab. Receive Frequency Compensation .
270153-12
Figure 9. External Tone Injection
5-11
inter
iATC29C48
can be disabled through the feature control memory.
Operation of this signal in the transmit direction remains unaffected to allow continued monitorin.9...2!
subscriber status by a line card controller. The SCS
signal remains active in the power down mode.
The feature control receive and transmit channels of
the SLD frame are shared by the two 29C48s. A
29C48 will accept or return feature control information only if it has been instructed to do so during the
first byte of a feature control frame. This is accomplished by setting the logic level of the channel selection bit (LSB) in feature control byte #1 to 'match
the logic level of the BIA pin of the appropriate
29C48. The selected 29C48 will keep exchanging
feature control information until a new framing byte
makes a new selection. The status of the channel
selection bit is sent back during the seventh byte of
the SLD frame in which a 00 was received in the
F/WE bits of the 3rd byte of the same SLD frame.
The eight possible sequences for SCS are shown in
Figure 10.
Precision Voltage References
Voltage references are generated on-chip .and are
trimmed during the manufacturing process. Separate
references are supplied for both the transmit and
receive sections of the chip, each trimmed independently. These references determine the gain and dynamic range of the device and provide the user a
significant margin for error in other board components.
The 29C48 does not process data received in the
signaling channel. However, it generates chip select
signals during the appropriate time slots in order to
facilitate the SLiC interface. (See section on SLiC
Chip Select.) The 29C48 enters into a high impedance state during the signaling transmit channel, the
eighth byte of the SLD frame.
SLD Interface
The 29C48 is intended for use with the 29C53AA
ISDN transceiver or a SLD compatible line card controller. They manage the transfer of all voice and
feature control data to and from the Feature Control
Combo. The interface between the two consists of
just three leads, two of which are clock signals and
the third a serial bus for communication.
SLIC Chip Select
In order to facilitate interfacing to an SLD compatible
SLlC, especially when two SLiCs share the same
SLD line, the 29C48 includes a programmable chip
select signal.
During the receive cycle of the SLD frame, the SCS
pin of the 29C48 whose channel selection pin (B/A)
has the same logic state as the channel selection bit
(see previous section on Channel Assignment) is
pulled low during the receive signaling byte.
The subscriber direction (SDIR) lead provides an 8
KHz signal which divides each frame into transmit
and receive halves. During the first half when SDIR
is high (RCV half-cycle), the 29C48 receives data
and in the second (XMIT half-cycle) the 29C48
transmits data. Frame synchronization and all internal timing for the digital circuitry is derived from the
rising edge of the SDIR signal.
During the transmit cycle of the SLD frame, the SCS
signal can operate in two modes. In the first mode,
called 'byte mode,' the SCS pin of the selected
29C48 is pulled low during the transmit signaling
byte, as described above for the receive direction.
The subscriber clock (SCL) input generated by the
29C53AA is a fixed 512 KHz clock signal allowing 64
bits (8 bytes) of data to be transferred on the SLD
lead during each 125 fJ-s frame. The SCL duty cycle
can range from 25% to 75%.
A second mode, called the 'half-byte mode,' is provided. In this mode, during the transmit cycle of the
SLD frame, the SCS pin of the channel A combo is
pulled low during the least significant four bits (last
four bits) of the transmit signaling byte. During the
same frame, the SCS pin of the channel B combo is
pulled low during the most significant four bits (first
four bits) of the transmit signaling byte. This allows
Signaling data from both A and B channel SLD compatible SLiCs to be processed by a line card controller during the same frame.
The Subscriber Line Datalink (SLD) is a bi-directional serial bus that transfers four bytes of serial data to
and from the 29C48 each frame. During the first half
of each frame, RCV channel information is expected
by the 29C48 as one byte consisting of voice and
one byte of feature control information, while the
other two bytes of the RCV half-frame are simply
ignored. Similarly, during the second half-frame, one
To minimize power consumption, operation of the
SCS signal during the receive half of the SLD frame
5-12
IATC29C48
During this time, the 29C48 resets and enters the
power down mode, The SCS output remains high
until the 29C48 has been configured as an A or B
channel device by the first write to feature control
byte #1.
byte of voice and, if so instructed, one byte of feature control information is sent by the 29C48. The
29C48 places its SLD lead in a high impedance state
while the other device connected to the SLD line
transmits its own information, and also while the one
byte of signaling information is transmitted by an
SLD compatible SLiC. The most significant bit (bit 7)
of each byte is sent first on the SLD line. The data
format of an SLD frame is shown in Figure 11.
PROGRAMMABLE FEATURES
The 29C48 is configured by a set of five feature control bytes (FCB).
Upon power supply application, feature control read
or write of the 29C48 is disabled for 9 SLD frames.
Receive SCS Disabled (See Section on SLiC Chip Select)
1) A-Channel Selected (See Section on Channel Assignment)/Byte Mode
1-01.0-----
1-01-0----
RECEIVE HALF FRAME - - - - _ .
TRANSMIT HALF·FRAME
----..j.1
I
I
A CHANNEL
sa
a·CHANNEl
sa
270153-13
2) B-Channel Selected/Byte Mode
RECEIVE HALF·FRAME
TRANSMIT HALF-FRAME
...-CHANNEL iCS
B-cttANNEL SCi
270153-27
3) A-Channel Selected/Half-Byte Mode
!\-o.-----RECEIVEHALF.FRAME
I
A-cHANNEL
•.
- 11
I
I
-----.~I
- - - - T R A N S M , T HAlF·FRAME - - - -.....
SCi
B-CHANNEL SCi
270153-28
4) B-Channel Selected/Half·Byte Mode
RECEIVE HALF-FRAME
TRANSMIT HALF-FRAME
270153-29
Figure 10. SCS Timing Diagram
5-13
IATC 29C48
bits, feature control byte # 1 also includes a channel
selection bit (bit 0, LSB). This bit is used to designate one of the two 29C48s sharing an SLD link for
feature control information exchange. (See previous
section on channel Assignment.)
These bytes of information are stored in internal registers which are serially multiplexed to and from the
SLD interface in the third and .seventh bytelocations. The first two bits of each· byte consist of a
multiframe synchronization and write enable code.
The framing bit (bit 7, MSB) establishes the beginning of a feature control frame when set to a logical
zero, and increments the feature control counter
when set to one. The second (bit 6) enables the
writing to the 29C48 when it is the logical complement of the framing bit. In addition to the two header
When writing new feature control information to the
29C48, the first byte should contain a framing (F)
and write enable (WE) header of 01 (F = 0 and
WE = 1), and an appropriate channel selection bit.
This designates a new frame of information to trans-
Receive SCS Enabled
5) A-Channel Selected (See Section on Channel Assignment)/Byte Mode
1-01------
0+1•.-----
RECEIVE HALF FRAME - - - -......
TRANSMIT HALF FRAME
------I_I
I
I
A CHANNEL
SCs
B CHANNEL
SCs
270153-14
6) B-Channel Selected/Byte Mode
I-01.o------RECEIVE H A L F · F R A M E - - - - -...+1....- - - - TRANSM'THALF.FRAME _ _ _ _ _
.I
I
I
I
A-CHANNEL ia:
a-CHANNEL
sa:
270153-30
7) A-Channel Selected/Half·Byte Mode
l i - o . - - - - - R E C E I V E HALF·FRAME
I
A-CHANNEl
----__00.+\. .
-1\
- - - - - T R A N S M I T HALF·FRAME - - - -....
I
I
iCS
a-CHANNEL SCi
270153-31
8) B-Channel Selected/Half.Byte Mode
RECEIVE HALF·FRAME
A-CHANNEL
TRANSMIT HALF-FRAME
sa:
B-cttANNELSCS
270153-32
Figure 10. SCS Timing Diagram (Continued)
5-14
iATC29C48
I
:
I
RECEIVE HALf'oCYCLE
I
TRANSMIT HALf'oCYCLE
I
:
!---_~I
smR.-J
~I--~~--~--~----r---~---'----T---~I
8~----~~~~T-~~~~T-~1~T-~~~~T-~~~1~--IVOICEA
I
CONTROL
:
I
VOICE B
I
CONTROL
SIGNALING:
I
SIGNALING :
1 FRAIIE
14--------- (125 pi)
512 KBPS
:
-I
I
270153-15
Voice A, Voice B: A and B channel voice bytes respectively.
Control: Feature control information. This information is exchanged with the 29C48 whose channel selection pin matches the channel selection bit
of the latest framing feature control byte.
Signaling: Signaling information which controls the subscriber line. The 29C48 enters into a high Impedance state during the transmit signaling time
slot, and generates a chip select signal (see section on SLiC chip select).
Figure 11. 29C48 SLD Interface
fer. The subsequent bytes should each have F = 1
to advance the counter, and WE = 0 to enable the
write operation.
placed in a high impedance state, inhibiting voice
signals. A code of all ones will be output in the voice
byte on the SLD. Signaling and feature control information will continue to be processed to allow the
29C48 to be read or reprogrammed.
The SLD master can also request to verify the fea·
ture control register contents by sending a 00 or 11
at the beginning of the byte to be read. To read the
first byte, a 00 FIWE code and an appropriate chan·
nel selection bit should be sent while each subsea
quent byte should have a 11 header. An internal six·
stage counter is set on the first byte verified then
incremented once each 125 ILs frame. It is reset
only upon detection of a 01 or 00 F/WE. Once the
counter is greater than five, neither read nor write
modes may be selected by sending the 29C48 a 11
or 10 framing and write enable code. While in this
state, the 29C48 will then echo in byte 7 the data it
received in byte 3. Another feature control informa·
tion exchange cycle can only be initiated by establishing a new feature control frame (sending F = 0).
The state of the feature control combo can be
changed from standby to active by the first feature
control byte only. All other register contents will be
preserved during power down provided the power
supplies remain connected.
LOOP BACK MODE SELECT
Three modes of remote testing are incorporated in
the 29C48 and can be selected by appropriate coding in this register. The loop back features allow a
number of tests to be performed to determine line
quality and balancing. These include digital loop
back, analog loop back, and subscriber loop back.
In the digital loopback mode, the combo retransmits
the PCM word it receives in the voice A or B byte of
the SLD back to the SLD master in the same frame.
This feature allows path verification and testing of
the circuit up to the combo.
FCB # 1--Power Up/Down, Loop Back
Mode, ,....A/-Law, Channel Select
Register
POWER UP AND DOWN
When the analog loopback mode is selected, the
analog output VFR is internally connected to the analog input VFX. This feature allows functional testing
of the combo as well as gain adjustment.
The 29C48 can be instructed to go into the power
down or standby mode for reduced power consumption. In this mode, all analog inputs and outputs are
5-15
iATC29C48
MSB
Bit Number ___
B'tNlme
#71
no change
write lneb"
1
00
F
01
we
_down
_up
-17J'l'l 41 3
tive programming of this register. A range from 0 to
-15.5 in 0.5 dB increments can be set for the receive channel.
LSB
~1~
)1
PUP
-
DLB
-
MSB
BltNomel
#78
normal operation
dlgltolloop bock
noehangB
write
.Nlbte
11
10
normal operation
analog loop back
ALB
Galn(dB)
normal operation
lubecrlber loop bad!;
SLB
0
-0.5
-1.0
-1.5
00000
00001
00010
00011
-15.0
-15.5
11110
11111
A-Law
pA
,..Law
channel A
#12345
0
AB
channel B
w=}
-'}
RON2
RON3
RGN4
RON5
270153-17
270153-16
In the third test mode, subscriber loopback, the digital output of the AID converter is internally connected to the input of the 01 A converter. The analog
signal input to VFX is sent through the transmit filter,
encoded, then decoded, filtered ~md output to VFR.
This mode is used primarily for simplifying analog to
analog testing from the subscriber side of the line
card. Simultaneous selection of more than one loopback mode is prohibited.
FCB # 3-Secondary Analog Channel,
Chip Select, and Tone Injection
Register
SECONDARY ANALOG INPUT
The 29C48 can be instructed to switch the input of
its encoder to the secondary analog input by setting
the SAlE bit to a logical one. Transmission of the
voice signal will resume as soon as SAlE is set back
to a logical zero.
CONVERSION LAWS
The 29C48 can be selected for either p.-Iaw or A-law
operation. A user can select either conversion law
by assigning the corresponding bit. A logical 1 in bit
1 would select p.-Iaw while a logical 0 would select
A-law conversions. Both conversiQns follow CCITT
recommendation G.711.
PROGRAMMABLE SLIC CHIP SELECT
Although the 29C48 does not process signaling information, it generates chip select signals in order to
help in interfacing to SLD compatible SLiCs.
During the transmit half-frame, the chip select works
in two possible modes determined by the CSM bit. In
the byte mode, the. SCS pin of the 29C48 selected
by the channel selection. bit in feature control byte
# 1 will be pulled low during the transmit signaling
byte. In the half-byte mode, the SCS pin of the Achannel 29C48. will be pulled low during the four
least significant bits of the transmit signaling byte,
and the SCS pin of the B-channel 29C48 will be
pulled low during the four most significant bits .of the
transmit signaling byte.
FEATURE CONTROL EXCHANGE
CHANNEL SELECT
The LSB of feature control byte # 1 is the channel
selection bit. It is used to select one of the two
29C48s sharing an SLD line for feature control information exchange. A logical zero will select the channel A combo, and a logical one will select the channel B combo.
FCB # 2-Receive Programmable Gain
Register
Generation of chip select Signals during the receive
half frame can be disabled by setting the CSD bit to
a logical zero.
The receive gain levels can be adjusted by applying
external resistors as mentioned earlier, or by selec5-16
inter
iATC29C48
FCB # 5-Balance Network Select and
Gain Register
TONE INJECTION
When the TIE bit is set to a logical one, audio signal
applied at the EBN3/T1 pin will be added to the output of the receive programmable gain module. This
feature can be used for easy implementation of side
tone injection and DTMF feedback, as well as injection at the line card of call waiting tones, ringing or
metering pulses.
MSB
BALANCE NETWORKS
Three external balance networks can be used with
the 29C48. Feature control allows the selection of
network EBN1, EBN2, and EBN3 individually or in
combination in order to best suit a particular application.
L.SB
EBN3 selection is not effective when TIE is set to a
logical one.
BIT NUMBER -1716151413121 ' 1 0.1
M-l
11
#76
NO CHANGE
WRITE ENABLE
~
F}
,OWE
GAIN SETTING
An additional 6 dB gain in the balance signal path
can be realized by setting the BNG bit to a logical
one. A logical zero provides unity gain.
SECONDARY ANALOG INPUT
ENABLED
,
BYTE
0
DISABLED
0
SAlE
SCS MODE
HALF-BYTE
SCS DISABLE RECEIVE
SCS ENABLE RECEIVE
EBN3 PIN ENABLED
TI PIN ENABLED
,
,
,
MSB
CSM
#76
J
11
10
F}
WE-
LSB
Bll Number __ 171&151 4131 211101
BIIN·~l
0
CSD
0
no change
wrlte.n.t)le
TIE
RESERVED
III10nco Notworlc
dl .._
DON"T CARE
onobled
270153-1B
0_
,
0
BNE-
432
8BN3
no aetectlon
EBNII3 001_
EBN3
FCB # 4-Transmit Programmable
Gain Register
o
The gain setting of the transmit section of the chip
operates in the same manner as the receive gain
register. A 12 dB range from 0.0 dB to + 12.0 dB in
0.5 dB increments is available.
000
001
010
EBNl
IOlocted 011
EBN2
••Iocted 100
EBNII2J3 0.1_ 101
EBN213 .._
110
EBNII2 ••1 _ 111
8BN2
8BNl
Ballance Network Gain
OdBgaln
&dB gain
0
1
BNG
don't care
270153-20
+0.0
+0.0
11000
I1XXX
270153-19
5-17
inter
iATC29C48
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
. other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ......... -10·C to +85·C
Storage Temperature .......... - 65·C to + 150·C
All Input and Output Voltages
with Respect to Vss .............. - 0.3V to 13V
All Input and Output Voltages
with Respect to Vcc .............. -13V to 0.3V
Power Dissipation .•...................... 1.35W
~
NOTICE' Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS
TA = O·C to +70·C, Vcc = +5V ±5%, Vss = ~5V ±5%; SCL (50% duty), SOIR, SLO applied GNDD
OV, GNOA = OV. Typical values are for T A = 25·C and nominal power supply values
=
DIGITAL INTERFACE
Symbol
Parameter
Typ
Min
IlL
Input Leakage Current
VIL
Input Low Voltage
-0.3
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Max
±10
Units
p,A
0.8
V
Test Conditions
Os Vin s Vee
V
0.4
2.4
V
10L;;:: -1.6 mA, 1 TIL Load
V
10H s 50 IJ-A, 1 TIL Load
POWER DISSIPATION
Typ
Max
Units
ICC1
Vee Operating Current
7.5
10
mA
Idle Channel
ISS1
Vss Operating Current
7.0
10
mA
Idle Channel
Icco
Vee Standby Current
0.6
1.0
mA
Isso
Vss Standby Current
0.3
0.6
mA
Symbol
Parameter
Min
A.C. CHARACTERISTICS-TRANSMISSION PARAMETERS
(TG1 = TG2, Transmit Programmable Gain = 6 dB. Receive Programmable Gain =
Test Conditions
0 dB)
GAIN AND DYNAMIC RANGE
Max
Units
EmW
Symbol
Encoder Milliwatt Response
Tolerance
Parameter
Min
Typ
±0.25
dB
Signal Input of 0 dBmO
f = 1.02 KHz
DmW
Digital Milliwatt Response
Tolerance
±0.25
dB
f
DmWf.v
Digital Milliwatt Response VFR,
IJ--Iaw
6.11
1.564
dBm
Vrms
RL = 600n
f = 1.02 KHz
DmWAV
Digital Milliwatt Response VFR,
A-law
6.17
1.576
dBm
Vrms
RL = 600n
f = 1.02 KHz
OTLP,..,x
Zero Transmission Level Point
Transmit Channel (0 dBmO)
0.09
0.783
dBm
Vrms
IJ--Iaw, Referenced to 600n
OTLPAX
Zero Transmission Level Point
Transmit Channel (0 dBmO)
0.15
0.788
dBm
Vrms
A-law, Referenced to 600n
~Gp
Programmable Gain Accuracy
±0.20
5-18
dB
Test Conditions
f
= 1.02 KHz
= 1.02 KHz for All Steps
inter
iATC29C48
GAIN TRACKING
Reference level = 0 dBmO at 1.02 KHz, TG1 = TG2, Transmit Programmable Gain = 6 dB,
Receive Programmable Gain = 0 dB, AT&T PUB 43801 and CCITT G.714-Method 2
Symbol
Max
Units
Test Conditions
GTT
Transmit Gain Tracking Error
Sinusoidal Input; ,... or A-law
Parameter
±0.25
±0.50
± 1.2
dB
dB
dB
+3to -40dBmO
-40 to -50 dBmO
-50 to -55 dBmO
GTA
Receive Gain Tracking Error
Sinusoidal Input; ,... or A-law
±0.25
±0.50
± 1.2
dB
dB
dB
+3to -40dBmO
-40 to -50 dBmO
-50 to -55 dBmO
Min
Typ
ANALOG INTERFACE, RECEIVE CHANNEL
ROA
Output Resistance, VFR
VOSA1
Output Offset, VFR
CLA
Load Capacitance, VFR
VOA1
Max Output Voltage Swing
Across RL, VFR
1
n
50
mV
100
±3.2
Relative to GNDA
pF
Vp
RL Z 6000(1)
ANALOG INTERFACE, TRANSMIT PRIMARY AND SECONDARY CHANNELS
IBX
Input Leakage Current, EBN,
TG1, TI
100
nA
RIX1
Input Resistance, VFX
100
KO
RIX2
Input Resistance, EBN, TG1, TI
10
MO
TGmax
Max Transmit Gain Adjust
VOTG
Max Output Voltage Swing TG2
CLX
Load Capacitance, TG2
RLX
Load Resistance, TG2
RGND
On Resistance to GNDA, EBN1,
EBN2, EBN3
20
dB
±1.6
V
20
10
Operating
Range(2)
RL Z 10K 0(3)
pF
KO
150
600
0
NOTES:
1. The 29C48 power amplifier is designed to drive signals in excess of the maximum encoding level, which is 3.14 dBmO for
A-Law and 3.17 dBmO for ",-Law.
2. -3.2V < VFX, EBN, TI < +3.2V; -1.6V < TG1 < +1.6V.
3. Transmit programmable gain must be set to 0 dB to encode this level without clipping in later stages.
5-19
intJ
iATC29C48
DISTORTION (Primary Channel)
Symbol
Parameter
Min
SDx
SDR
Signal to Distortion, fJ- or A-law
Sinusoidal Input; CCITT G.714Method 2 Half Channel
35
29
25
DPx
DPR
Single Frequency Distortion
Products in Band (2nd or 3rd
Harmonic Half Channel)
IMD1
Typ
Max
dB
dB
dB
-60
Test Conditions
Units
Oto -30dBmO
-30 to -40 dBmO
-40 to -45 dBmO
-47
dBmO
Intermodulation Distortion, End to
End Measurement
-35
dB
CCITT G.712(7.1)
IMD2
Intermodulation Distortion, End to
End Measurement
-49
dBmO
CCITT G.712(7.2)
SOS
Spurious Out of Band Signals,
End to End Measurement
-25
dBmO
CCITT G. 712(6.1)
SIS
Spurious in Band Signals, End to
End Measurement
-40
dBmO
CCITT G.712(9)
DAX
Transmit Absolute Group Delay
fJ-s
odBmO, 1.4 KHz
220
Input = 1.02 KHz 0 dBmO
AT&T Advisory #64 (3.8)
Includes Delay Through AID
Dox
Transmit Differential
Delay; Relative to DAX
170
95
45
75
fJ-s
fJ-s
fJ-s
fJ-s
f
f
f
f
= 500-600 Hz
= 600-1000 Hz
= 1000-2600 Hz
= 2600-2800 Hz
DAR
Receive Absolute Group Delay
140
fJ-s
odBmO, 0.3 KHz
Includes Delay Through Df A
DOR
Receive Differential Envelope
Delay; Relative to DAR
35
35
110
135
fJ-s
fJ-s
fJ-s
fJ-s
f= 500-600 Hz
f= 600-1000 Hz
f = 1000-2600 Hz
f "7 2600-2800 Hz
NOISE (Primary Channel)
Symbol
Parameter
Min
Typ
T.est Conditions
Max
Units
15
dBrnCO
TG1 = TG2; Transmit
Programmable Gain =
-75
dBmOp
TG1 = TG2; Transmit
Programmable Gain = 6 dB
11
dBrnCO
Unity Gain; Idle Code;
Receive Programmable
Gain = OdB
Unity Gain; Idle Code;
Receive Programmable
Gain = OdB
NXC1
Transmit Noise, C-Message
Weighted
NXP1
Transmit Noise, Psophometrically
Weighted
NRC1
Receive Noise, C-Message
Weighted
NRP1
Receive Noise, Psophometrically
Weighted
-79
dBmOp
PSRR1
VCCorVBB
Power Supply Rejection
Transmit Channel
-30
dB
Idle Channel; 200 mV P-P
Signal on Supply,
DC to 50 KHz (1)
PSRR2
VCCorVBB
Power Supply Rejection
Receive Channel
-30
dB
Idle Channel; 200 mV P-P
Signal on Supply,
DC to 50 KHz (1)
6 dB
NOTE:
1. Measured at SLO Voice bytes for transmit channel. Measured at VFR for receive channel. Idle code on feature control
byte.
5-20
IATC29C48
CROSSTALK
Symbol
Parameter
Crosstalk, Transmit Voice to
CTTA
Receive Voice
CTAT
Min
Crosstalk, Receive Voice to
Transmit Voice
Typ
-90
Max
-75
Units
dB
-80
-72
dB
Test Conditions
Input = 0 dBmO, Unity Gain
1.02 kHz; Idle Code on SLD
Voice Byte
o dBmO, 1.02 KHz Signal at
SLD Receive Voice Byte;
VFX = GNDA
TRANSMIT VOICE FREQUENCY CHARACTERISTICS
TG1 = TG2, Transmit Programmable Gain = 6 dB
Symbol
GAX
Parameter
Gain Relative to Gain at 1.02 KHz
16.67 Hz
50Hz
60 Hz
200Hz
300 to 3000 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz and Above
.,.. j
EXPANDED
SCALE
Typ
Min
Max
Units
Test Conditions
o dBmO Signal Input at VFX
-1.8
-0.125
-0.35
-0.70
-30
-25
-23
-0.125
+0.125
+0.03
-0.10
-14
-32
+~~;~:B
-O.125dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
+0.125 dB
+0.03 dB
3000Hz·
../"'3300Hz
20~~"""""""""~-0.'Od'
3400Hz
Od8
-0.35 dB
3300Hz
-10dB
/r-
Od8
-10dS
-14dB
4000Hz
"'20dS
TYPICAL
-JOdS
-4-0 de
-SOdS
-60dS
10Hz
100Hz
1 KHz
10KHz
270153-21
Figure 12. Transmit Voice Frequency Characteristics
5-21
infef
iATC29C48
RECEIVE VOICE FREQUENCY CHARACTERISTICS
Receive Programmable Gain = 0 dB, Feature Control Bit TIE = 0
Symbol
GRR'
Parameter
Min
Typ
Max
Units
Test Conditions
o dBmO Input on SLD
Gain Relative to Gain at 1.02 KHz
Below 200 Hz
200 Hz
+0.125
dB
-0.5
+0.125
dB
300 to 3000 Hz
-0.125
+0.125
dB
3300 Hz
-0.35
+0.03
dB
3400 Hz
-0.70
-0.1
dB
4000 Hz
-14
dB
4600 Hz & Above
-30
dB
+1.0dB
+O.125d8 +O.12Sd8
EXPANDED
SCALE
+O.125d8
+O.03dB
(/ // // // // (/ ~~O/H:. //:~O/H: /////(/ /////////t~?~~:~,:zdB
DdB
/
3400Hz
-O.SOdB
200 Hz
-0.12SdB
3000 Hz
TYPICAL
-0.35 dB
3300 Hz
-0.70 dB
3400Hz
-1.DdB
'////
OdB
~
-10dS
~
-UdB
TYPICAL
4000 Hz
-20dB
-30dB
-30dB
4600 Hz
-40dB
-SDdB
-
-SOdB
I
10Hz
I
I
100Hz
1 KHz
I
10KHz
270153-22
NOTES:
1. Typical transfer function of the receive filter as a separate component.
2. Typical transfer function of the receive filter driven by the sample and hold output of the Intel 2910A and 2911 A
codecs. The combined filter I codec response meets the stated specifications.
Figure 13. Receive Voice Frequency Characteristics
5-22
inter
iATC29C48
A.C. CHARACTERISTICS-TIMING PARAMETERS
Symbol
Max
Units
TSCL
SCl Pulse Width
Parameter
486
1465
ns
TDC
SCl Duty Cycle
25
75
%
TRC
TFC
Rise, Fall Times, SCl
50
ns
TRD
TFD
Rise, Fall Times, SlD
50
ns
TRS
TFS
Rise, Fall Times, SCS
50
ns
TDIRR
SCl to SDIR Delay
-500
500
ns
Receive Cycle
TDIRF
SCLto SDIRDelay
-500
500
ns
Transmit Cycle
TDD
SCl to SlD Delay
0
200
ns
29C48 Transmitting
TSD
Set-up Time, SlD to SCl
100
ns
29C48 Receiving
THD
Hold Time, SCl to SlD
100
ns
29C48 Receiving
THZ1
SDIR to SlD Active
0
100
ns
Byte 1, Bit 1 29C48
Transmitting, Channel A
THZ2
SCl to SlD High Impedance
0
100
ns
Channel A, B, or Feature
Control as Appropriate
(Channel AlB Operation)
THZ3
SCl to SlD Active
0
100
ns
Channel A, B, or Feature
Control, as Appropriate
(Channel AlB Operation)
TSCSF
SCl to SCS low
TFS
250
ns
50 pF load
THZSCSF
SlD High Impedance
toSCS low
ns
Transmit Feature Control
TSCSR
SCl to SCS High
ns
50 pF load
'In cases where T DIRF
IS
positive, T DD
IS
Min
Typ
0
TRS
200
Test Conditions
50 pF load
to be measured from the SOIR edge.
RECEIVE CYCLE
SDIR
SLD
--<'----...JI ~___
SCS(AOR B)
270153-23
5-23
inter
iATC29C48
TRANSMIT CYCLE
SOIR
SLOCA)
SLOCB)
tSCSR
SCs CA OR B)
IRS
270153-24
A.C. TESTING INPUT, OUTPUT WAVEFORM
270153-25
A.C. Testing inputs are driven at 2.4 for a logic "1" and 0.45 for a
logic "0". Timing measurements are made at 2.0V for a logic "1"
and O.BV for a logic "0".
5-24
inter
•
•
•
•
•
•
iATC 29C53AA
DIGITAL LOOP CONTROLLER
•
•
•
•
•
•
4-Wire Full Duplex Digital Transceiver
CCITT 1.430 "S" Interface Compatible
ISDN Basic Rate 144K Bit Per Second
O-Channel Processing Support
Point-To-Point or Point-To-Multipoint
Bus Configuration
Same Device Used at Both Ends of
Loop
Exceeds 1K Meter Range
IATC Standard SLD Interface
MCS® Standard Microprocessor
Interface
Peripheral Interface/Status Port
Low Power, High Density CHMOS
Single
+ 5 Volt Supply
The Intel Advanced Telecommunication Component (iATC) 29C53AA Digital Loop Controller (DLC) is a 4-wire
transceiver/controller that is CCITT 1.430 compatible and can function at either loop end. This part has
integrated those features which are pertinent to the transceiver function and offers efficient interfacing to other
system components such as CODEC/Filters and microcontrollers through the SLD and microprocessor interface ports. It is primarily intended for use in Integrated Services Digital Networks (ISDN) as a basic rate digital
data transceiver which transfers data at 144 Kbps as three separate channels-two 64 Kbps digitized-voice/
data channels (8 channels), and a 16 Kbps signaling/data channel (D channel). The 8- and D-channel routing
along with D-channel processing (packet framing) is programmable through either the microprocessor or SLD
interface ports. The 29C53AA's loop interface uses a 100% pulse-width pseudo-ternary line code which meets
CCITT's "s" interface recommendations. It is capable of interfacing with up to eight 29C53AAs in a passive or
extended bus configuration as well as point-to-point.
Plastic Chip Carrier
350 x 550 MILS
28-Lead Dual-In-Llne Package
cs SLDINlDOAD1
SCL
AD2
SDIR
AD3
ALE
AD4
RES
CLK
vce
VSS
WR
ADS
RD
AD6
P4
AD7
P3
P1
INT
ADO
SLD
AD1
Cs
AD2
SCL
AD3
SOIR
AD4
ALE
CLK
RES
VSS
VCC
ADS
WR
AD6
RD
AD7
P4
P1
P3
LX+
LRP2
LXLR+
P2
LX+
LR+
LX-
LR-
270097-1
270097-2
Figure 1. 29C53AA Pin Configurations
5-25
October 1988
Order Number: 270097-004
intJ
Symbol
iATC 29C53AA
Pin No.
Function
+ 5V
Vee
8
POSITIVE SUPPLY: Input voltage is
Vss
CLK
22
GROUND:OV
23
MASTER CLOCK: The 3.84 MHz system clock input is the reference .for the
loop and the SLD interface.
Aes
7
LX+, LX-
13,14
LA-, LA+
±5%.
RESET: (Active high input). A high level on this pin initializes control registers
and places interface outputs in a high impedance state. Operation begins after
the high level is removed.
POLARIZED TRANSMIT LOOP INTERFACE PINS: These pins will directly
drive the twisted pair line through a pulse transformer. The transmitted line
code is 100% pulse width pseudo-ternary.
15,16
RECEIVE LOOP INTERFACE PINS: The receiver is not sensitive to polarity.
SLD
2
SUBSCRIBER LINE DATALlNK: This pin transfers serial data between the
29C53AA and other SLD based components (e.g., 29C48).
SCL
4
SUBSCRIBER CLOCK: 512 KHz signal may be either generated or received by
the 29C53AA. This signal clocks the data on the SLD pin.
SOIA
5
SUBSCRIBER DIRECTION: An 8 KHz signal may be either generated or
received by the 29C53AA to indicate SLD data direction and framing. A high
level indicates master to slave transfer; a low level indicates slave to master
transfers.
CS
3
CHIP SELECT: (Active low input). A low level on this pin enables the 29C53AA
bus interface for the next bus cycle. The value is latched by the falling edge of
ALE.
AD
10
READ STROBE: (Active low input). When low, data is transferred from the
selected register to the data pins AD (0-7). When no local microprocessor is
connected, this pin should be tied to Vss.
WR
9
WRITE STROBE: (Active low input). When WR changes from low to high, data
on pins AD (0-7) is latched into the 29C53AA. When no local microprocessor
is connected, this pin should be tied to Vss.
19-21,
24-28
ADDRESS/DATA PINS: This is a standard MCS microprocessor bus used to
transfer address and data between the local microprocessor and the internal
registers of the 29C53AA. When a local microprocessor is not used, these pins
should be tied to Vss.
ALE
6
ADDRESS LATCH ENABLE: Address is latched from AD(1-5) on falling edge
of this signal. State of CS is also latched at this time.
INT
1
INTERRUPT REQUEST: This is an open drain active low output. (See text for
the interrupt conditions.)
18,17
PERIPHERAL INTERFACE INPUTS: These are standard CHMOS high
impedance inputs that are sampled at a 4 KHz rate (once per "s" frame). The
sampled data is stored in the LPS register (bits 5 and 6). If any peripheral input
bits have changed value since the previous frame, an interrupt condition is
indicated; only present status is available.
P3
12
PERIPHERAL INTERFACE INPUT/OUTPUT PIN: When configured as an
input, this pin has the same characteristics as P1 and P2. The sampled data is
stored in the LPS register (bit 7). When programmed as an output, this pin
outputs the data stored in the PEC register (bit 1). The pin is configured by bit 2
of the PEC register. An alternate function of this pin and P4 is to indicate the
status of the SLD interface. See the section on the SLD interface.
P4
11
PERIPHERAL INTERFACE OUTPUT PIN: This pin outputs data stored in the
PEC register (bit 0) or SLD status.
AD (0-7)
P1, P2
5-26
(
r--------------------------~
LX+
OUTPUT
DRIVER
LX-
~
c
;
I,
~
XMIT FORMATTER
AND TIMING
0- CHANNEL PROCESSOR
SBUS
ANALOG
REF.
~
~
01
Cf' ~
~
~
ID
0'
()
~
LR+
CD
~I
FILTER
1
AND
LR- ~ DETECTORS
3
2
tZ
ill
3
Co)
SLD
INTERFACE
~
oen
~
LINE
INTERFACE
UNIT
SLD STATUS
AND
PERIPHERAL
INTERFACE
RBUS
XFER
TIMING
CONTROL
SLD
INTERFACE
UNIT
._--------------------------
"@
aID
270097-3
IiiiiI
IF'
~
0=
~
~
~
iATC 29C53AA
1.0 INTRODUCTION
The 29C53AA Digital loop Controller is an advanced, programmable digital transceiver providing
the layer one interface at the S or T reference point
in Integrated Services Digital Network (ISDN) basic
access applications. It provides access to the two B
channels and the 0 channel in accordance with
CCITT recommendation 1.430, and supports both
point-to-point and multipoint topologies. It can be
used in linecard (NT) applications, or with the 29C48
programmable CODEC/Filter and appropriate data
communications devices in voice/data subscriber
(TE) applications.
The 29C53AA may be incorporated at either end of
a subscriber loop interface (at the line card or digital
telephone/terminal). As shown in Figure 2, the
29C53AA has four separate interfaces: a serialSlD
system interface; a parallel peripheral interface; a
parallel microprocessor interface and a 4-wire
CCITT compatible S-interface (subscriber loop inter.
face).
or requests for service may be generated for conditions such as FIFO fullness level, loss of sync, frame
check error, overflows and aborts.
The line interface unit contains the line drivers and
receivers for the S interface. Connection is made to
the transmission lines through a pulse transformer.
Formatting, timing and synchronization are also
provided here. The receiver includes filters, AGC circuitry, threshold detectors and a loop delay shift register. The loop delay shift register maintains the
proper internal frame relationship regardless of loop
length (it allows extra propagation delay time for
long loops or line repeaters). The received D-channel bits are logically looped back to create the
E-channel bits in an NT application through the
E-channel circuitry.
The microprocessor interface circuitry allows the
29C53AA to function as a peripheral to a microcontroller or microprocessor. All internal registers are
directly accessible.
The spare bits processing block provides access to
the FA, N, and A bits. It also provides access to the
Sand M bits, and supports the Sand Q channels.
THE BLOCK DIAGRAM
Figure 2 represents a block diagram of the
29C53AA. Its three major blocks, the line interface
unit, the D-channel processor and the SlD interface
unit are interconnected by two buses. The parallel
bus (PBUS) is used to transfer processed D-channel
data and general status and control information,
while the serial bus (SBUS) is used to transfer
B-channel data and unprocessed D-channel data
between the line interface unit and the SlD interface
unit.
The peripheral interface circuitry provides an auxiliary port for controlling auxiliary peripherals such as
power controllers, etc. It can be programmed to provide SlD status as well.
The SlD interface unit consists of shift registers and
serial to parallel converters. Data from both the
SBUS and the SlD interface is stored here in appropriate parallel registers before it is loaded into shift
registers and passed on. All of the timing circuitry for
the SlD interface is located here. This block also
contains a command processor which is responsible
for executing commands received in the SlD C byte.
As shown in Figure 3, the SlD interface consists of
three lines: the SlD bidirectional data line; the
512 KHz SCl clock line; and the 8 KHz SDIR data
direction line. SlD data is updated on the rising edge
of SCl and is latched on its falling edge. The 125 ,""S
SlD frame period consists of 32 bits transferred in
master to slave direction followed by 32 bits in the
slave to master direction. The 32 bits compose four
8-bit bytes in the following order: B1 and B2 (voice
or data bytes); C (control byte); and S (signaling or
status byte). Unprocessed D-channel data may be
transported over the S-byte in bits and 1, or over
the B2 byte.
SLD INTERFACE
The SlD interface provides communication with other devices incorporating SlD interfaces.
The D-channel processor has three major sections.
An HDlC section performs some of the basic LAPD
protocol functions such as zero insertion or deletion,
flag recognition or insertion for frame delineation,
abort flag recognition, idle state transmission, and
end of packet frame check sequence for both data
directions. The FIFO section consists of two 32-byte
buffers, one for transmit and one for receive. The
control and status section monitors the FIFO data
levels and the HDlC section for progress. Interrupts
°
The 29C53AA can be operated as an SlD master or
slave. As an SlD master, it generates the SCl and
SDIR signals. When SDIR is high, the SlD pin outputs data. As a slave, it receives SCl and SDIR sig-
5-28
iATC 29C53AA
nals and SDIR enables the SLD output driver when it
is low. The SLD bus is always active; no powereddown or inactive mode is defined.
resistance (see Figure 12). The series resistance,
when used with protection diodes, provides additional protection against surges. It also increases the
output impedance.
In a network termination (NT) application (line card),
whether a microprocessor is connected to the
29C53AA or not, the SLD control and signaling
bytes may be used for 29C53AA configuration and
D-channel transfers. The command bytes are interpreted and executed by the 29C53AA's command
processor circuit. The command processor generates internal P8US cycles to carry out those commands. Internal prioritization resolves P8US collisions between microprocessor-interface generated
and command-processor generated cycles. In case
of collisions, the microprocessor interface has higher priority to minimize access time but both cycles
will be completed.
The nominal bit rate is 192 Kbps. Figure 4 shows the
frame structure. The 250 ,...S frame transfers two octets of 81, 82 and four bits of D data. The E bits in
the master to slave direction echo received D-channel data. The "S" interface slave compares the receive E-channel data to its transmitted D-channel
data for D-channel contention as defined in CCITI
recommendation 1.430. If these bits do not agree,
then the slave will abort its transmission effort. The
S, M, fA, A, and N bits are all accessible and programmable. The 29C53AA supports the layer 1
maintenance multiframing for the Q and S channels.
The activation protocol described in 1.430 is supported by the 29C53AA. An inactive receiver can
achieve bit synchronization to an incoming signal
with approximately 15 mark-mark transitions. Info 2
or 3 frame alignment is not officially recognized until
reception of 16 frames, to allow settling of the
29C53AA's adaptive receive data thresholds. The
full activation sequence will complete in approximately 10 ms.
"S" TRANSCEIVER
The 4-wire "S" transceiver circuit in the 29C53AA
conforms to CCITI recommendation. 1.430. This
transceiver provides the internal drivers for transformer coupling to standard telephone type twisted
pair cables.
The "S" transceiver line code is 100% pulse width
pseudo-ternary code, with binary ones represented
by no line signal, and binary zeros by a positive or
negative pulse. Pulses alternate polarity except
when a code violation is created for establishing the
frame reference timing. The nominal pulse amplitude
is 750 mV when a suitable pulse transformer is used.
The 29C53AA is not sensitive to the polarity of the
wire pair connected to LR + and LR -. Pulses are
always interpreted as zeros and framing relies on
violations; not on absolute polarity. System configurations-may dictate that care be taken in connecting
the LX outputs. In a multi-drop bus configuration all
TE transmitters must be connected with the same
polarity so that positive pulse to negative pulse contention does not take place in the framing and Dchannel bits.
The 29C53AA transmitter is typically connected to
the line through a pulse transformer and series
91
SLD
SDIR
J
92
91
S
C
I.
92
SLAVE MASTER -
C
S
MASTER
SLAVE
SCL
I.
125,uS
.1
270097-4
B1 - 64KBPS DATA
- 8 BIT BYTE
B2 - 64KBPS DATA
- 8 BIT BYTE
C· CONTROL/DATA ·8 BIT BYTE
S - SIGNALING/DATA· 8 BIT BYTE
ALL BYTES ARE MSB FIRST
Figure 3. SLD Interface
5-29
intJ
iATC 29C53AA
• MASTER TO SLAVE (NT TO TEl
F
L~-BI-8BITS-!E
'YLrE ~
D A FA N!-82-8BITS-!E
11111111
D MI-BI-881TS--!E
D SI-B2-8BITS-!E
D L
f ~ 111111 f~ 111111 { 8HP
• MASTER TO SLAVE (TE TO NT)
1--------1
2 BIT OFFSET
:rwr ffitfU1H ffibqJ} ffibqJ} ffitP1
F
L
~-BI-8
BITS
r
-I
L D L FA L
1- B2-8 BITS-! L
48 81T WIDE FRAME -
D L I- BI-8 BITS--! L
D L I-B2-8 81TS-! L
D L
250 MICRO SECONDS
270097-5
A· BIT USED FOR ACTIVATION
B1. 2·64 K BPS DATA
D· DCHANNEL BIT (16K BPS DATA)
E • D CHANNEL ECHO BIT
F· FRAME BIT
FA' AUX. FRAME BIT
L • DC BALANCING BIT
N • BIT = FA (NT to TE)
M • MULTIFRAMING BIT
S • S CHANNEL BIT
Figure 4. The S-Interface Frame Structure
The 29C53AA, functioning as an "S" interface master in a multi-drop application, can interface with up
to eight slave systems. In this multiplexing operation
a slave initiates a data transfer to the master, by
requesting access and transferring the data in accordance with the D-channel line access protocol
(1.440). Figure 5 shows typical applications of the
29C53AA.
internal registers are accessible and are available by
a single microprocessor cycle access. The
29C53AA latches address information from
POINT-TO-POINT
1-1-----1km-----....11
~~-------------------~
The frame alignment timing diagram Figure 6(b)
shows the relationship of the "S" interface data to
the SLD data. Figure 6(a) shows the block diagram
used for the timing diagram. The top timing diagram
of Figure 6(b) shows the transmitted "S" data
stream from the network terminator (master). The
dotted lines depict up to 20 f.Ls propagation delay to
the "S" receiver at the terminal equipment (slave)
end. The terminal equipment's transmitted "S" interface frame is designed to have a fixed 2-bit frame
alignment del""y from that pf its received, frame. The
adjustment for loop propagation delay is accounted
for in the network terminato(s r~cE:live circuitry (loop
delay section. of block diagram). The loop delay circuitry will compensate for up to 10 bit periods of
round trip propagation delay which allows line repeaters to be placed in a loop that is several thousand meters long.
PASSIVE BUS
,------100 M- 200 M
----·1
•••
EXTENDED PASSIVE BUS
r25-50M _'1~_--500 M - - _ . jI
0·· ·8
MICROPROCESSOR INTERFACE
This interface is designed to operate with stand,ard
Intel microprocessors such as the MCS®-48, MCS51, MCS-85 and 8086 families. All of the 29C53AA's
~
270097-6
Figure 5. 29C53AA Bus Configurations
5-30
inter
iATC 29C53AA
NT
TE
RECEIVE
DATA PATH
(B)
TRANSMIT
DATA PATH
(A)
4 WIRE"S"
TRANSMIT
DATA PATH
RECEIVE
DATA PATH
(D)
(E)
270097-7
Figure 6(a). Frame Alignment (Block Diagram)
AD1-AD5, and does not use ADO for addressing.
This provides compatibility with 16-bit microprocessors.
PERIPHERAL INTERFACE
The maskable interrupt pin is activated by the following interrupt status features: D-channel errors; loss
of sync on "S" loop; change in spare bits or peripheral interface data; FIFO data transfer requests.
The peripheral interface uses four pins to provide
control to, and to accept status from, external devices. Two pins are inputs, one is an output and one is
configurable either as an input or an output. The
configurable pin defaults to the input mode on power
up.
Alternatively, the 29C53AA can operate in the standalone mode in line card and NT applications. This
mode is determined after a reset, provided all the
microprocessor interface pins have been tied to
VSS, except for the interrupt pin. The 29C53AA is
then controlled using the C byte of the SLD interface.
The peripheral interface can also be used to indicate
SLD status. Figure 7 shows the timing diagram of P3
and P4. 81, 82 and D-channel data on the SLD pin
can be selected or gated by using these signals. As
noted on the P3 timing, the D-channel is imbedded
in the last two bits (0, 1) of the Signaling byte. (This
must be programmed in the DPC register).
r
B1
SLD
SDIR
J
B2
c
MASTER - - - SLAVE
I
S
: I,
2 BITS
B1
B2
c
SLAVE - - - MASTER
S
,
'r
,
,
,
'
rr
P3
,
_____r
270097-9
NOTE:
1. Status indicators are activated by the SST Bit in the PEG Register.
2. P3 changes two bits prior to P4 If raw D-channel data is routed over the SLD S byte.
Figure 7. 29C53AA SLD Status Indicators
5-31
(A)
NT
SX
f
Bl(a)
(B)
SR
...,z
"11
SLDX
...J""
SDIR
lEi
c:
0 ...
...,,,,
C1)
. . I-
~
:Eo
z;;;
"'...J
~VI
~
...
...,I
"11
III
,
B2(b)
l
t
1
"I
I "E"!!2
1
(C)
'"
55i
0.....,
...
Bl(b)
V
-:\, I-LOOP
"
DELAY
I-
B2(a)
T
SLDR
I-
~
3C1)
(D)
~
01
l:J
I\)
i!i
::J
3C1)
3-
(E)
'3
SR
N
SX
~
en
~
3
S'
ID
.
'"~
0
iii'
...
(F)
....
;;;...,
ID
"''-'
"'...,
III
3
SLDX
'--___r-
1-",
~~
~
0;;;
i!9
"'VI
z
SDIR
SLDR
~
.!.
z
2eJ
IiiiiJ
IF'
(A)
SX
~
o
o
co
....I
00
NOTE:
+ Depicts the beginning of the'S' Interface frame
.. (loading edge of F bit) and the beginning of the SLD interface frame.
~
~
~
2eJ
~
inter
IATC 29C53AA
Op Code Table
OpCode
Operation
Argument
-
000
Reserved For Status Poll (Call Verify) By Master
001
Single Byte Transfer To Slave
RegAdr
010
Prepare Single Byte For Transfer To Master
RegAdr
011
Multiple-Byte 0 Data Transfer To Slave
'Bytes
100
Multiple-Byte 0 Data Transfer To Master
Max' Bytes
101
Multiple-Byte Configuration Transfer To Slave
, Bytes
110
Multiple-Byte Status Transfer To Master
, Bytes
111
Reserved For Status Poll (Call Verify) Tail & Idle
are transferred or an EOP (end of packet) is detected. The EOP may occur even when there are additional bytes in the FIFO. The header byte contains
the byte count in the lowest five bits and the packet
status in the upper three bits.
INTERNAL CONTROL AND STATUS
REGISTERS
'
All of the 29C53AA's internal control and status registers may be accessed through the microprocessor
interface or through the SLO interface (when in SI,.O
slave mode). When a microprocessor accesses a
register, the address and CS inputs are latched on
the trailing edge of ALE. The address is latched from
pins A01-A05 of the microprocessor port.
Data transfers over the SLO line cannot be made in
both directions simultaneously. Multiple commands'
and data bytes may follow each other directly from
the line card controller to the 29C53AA if the previous command has been fully executed.
In an SLO access, the 29C53AA receives a control
byte containing an operation code and an argument.
The three most significant bits contain the operation
code and the remaining five bits contain the argument. The operation code defines eight transfer
types.
SLD Control Byte
It is possible to fully configure the 29C53AA over the
SLO interface. Provisions are also made to perform
this transfer at a 2 byte-per frame rate using both the
C and S bytes of the SLO. The first control byte of a
configuration transfer to the 29C53AA specifies the
type of operation to be performed and the number of
data bytes to follow. The system interface command
unit loads the internal registers with the information
as it is received. When the specified number of data
bytes have been transferred, the 29C53AA assumes
the next input is a control byte.
BITS
](
-
Argument
OpCodo
The order of the bytes in a configuration or status
block transfer is determined by the addresses of the
internal registers. A multiple-byte transfer, beginning
with register OOH, transfers the data to or from that
register and increments the address counter.
The 3-bit operation code in the control byte from the
SLO master should normally be 111, indicating the
idle state. The transferring of data to and from the
29C53AA is accomplished by indicating the type and
the number of bytes to transfer in a non-idle control
byte. When a polle,d response is requested, the
29C53AA responds to the poll operation code 000.
This can be used for the transfer of one or several
bytes of information.
The register table below identifies the address of
each 29C53AA register. The status registers are
read-only registers while all control registers are
read/write reg,isters. Because all the register addresses do not fit into the 5-bit address space, a
register test mode has been included which permits
reading the contents of control registers at addresses which normally are status registers. Where no
register is assigned a location in the register test
mode, the normal status register located at this address is read.
The O-channel block transfers from the 29C53AA to
the SLO master preface the data bytes with a byte
header specifying'the number of following bytes
(less than or equal to the maximum specified) and
the status of the packet they belong to. All transferred data bytes belong to the same packet; the
transfers occur until the selected number of bytes
5-33
intJ
IATC 29C53AA
Table 1. 29C53AA Registers
Parallel
Port
Address
00
00
02
02
04
04
06
08
08
OA
OA
Internal
Address(1)
Access
Symbol
-00000
RD
WR (RT)
RD
WR (RT)
EXS
OC
OC
OE
10
12
14
16
18
1A
1C
1C
00000
00001
00001
00010
00010
00011
00100
00100
00101
00101
00110
00110
00111
01000
01001
01010
01011
01100
01101
01110
01110
1E
1E
20
22
24
26
30
32
34
36
38
01111
01111
10000
10001
10010
10011
11000
11001
11010
11011
11100
RD
WR (RT)
3A
3C
3E
11101
11110
11111
RD
WR (RT)
RDWR
RD
WR(RT)
RD
WR(RT)
RD
WR(RT)
RDWR
RD
WR
RDWR
RDWR
ROW
RDWR
RD
WR (RT)
EXM
DPS
DPC
LPS
LCR
PEC
RFN
SCR
XFN
SOC
SBR
SBX
LLB
RFO
XFI
GCR
DPR
RFXF
XFXF
PLENH
DUTH
Function
Interrupt Status
Interrupt Mask
D-Channel Processor Status
D-Channel Processor Control
Loop and Peripheral Interface Status
Loop Interface Control
-Peripheral Interface and E-Channel Control
' Receive FIFO Status - " of Bytes Used
SLD Interface Control
Transmit FIFO Status - " of Free Bytes
SLD Data Transfer Configuration
RDWR
RDWR
RD
RD
RDWR
PLENL
DOTH
SBC
PSR
RSR
XSR
81LS
RDWR
RDWR
RDWR
RDWR
B2LS
CR
SR
B1SL
Spare Bits Receive Status
Spare Bits Transmit
Loop Interface Loopback Control
Receive FIFO Output
Transmit FIFO Input
General Command Register
D-Channel Priority Counter
Receive FIFO Interrupt Level
Transmit FIFO Interrupt Level
Packet Length High Byte
D-Channel Byte Counter Underflow
and Overflow Threshold
Packet Length Low Byte
D-Channel Byte Counter Overflow Threshold
Spare Bit Control
Position Selection
Receive Service Request
Transmit Service Request
B1 Data in Loop to SLD Direction
B2 Data in Loop to SLD Direction
Control Byte from SLD
Signaling Byte from SLD
B1 Data in SLD to Loop Direction
RDWR
RDWR
RDWR
B2SL
CX
SX
B2 Data in SLD to Loop Direction
Control Byte to SLD
Signa,ling Byte'toSLD
NOTE:
1. Address represents AD1-AD5. ADO is not used by the 29C53AA for addressing.
5-34
intJ
IATC 29C53AA
CR Control Byte Receive 11010 R, W
29C53AA Register Definitions
7
In the register descriptions that follow, the acronym,
name, five bit address, and whether the register can
be written or read (or read only in RT mode) are
provided in the heading. For easy reference, the registers are listed in alphabetical order.
6
5
4
3
2
o
CX Control Byte Transmit 11110 R, W
This register provides access to the B1 channel data
flow in the direction from the "S" loop to SLD interface. Data can be read or overwritten by the microprocessor in Intercept mode (see SCR register).
Also, data can be accessed so the MSB is in bit 7
(default mode) or flipped so that the LSB Is in bit 7
by issuing the appropriate GCR command.
7
5
2
4
o
7
4
6
B1 data
7
5
4
3
2
5
6
4
ORT
unused
3
I I
B20
o
2
D-Ch. Routing
DRT D-channel routing through B2 on the SLD if bits
2-0 are 101.
BITS
B2SL B2 Data SLD to "S" Direction 11101 R, W
6
o
2
DPC D-Channel Processor Control 00001 W (RT)
This register provides access to the B1 channel data
flow in the direction from the SLD interface to the
"S" loop. Data can be read or overwritten by the
microprocessor in intercept mode (see SCR register). Also, data can be accessed so the MSB is in bit
7 (default mode) or flipped so that the LSB is in bit 7
by issuing the appropriate GCR command.
7
3
4
5
This overflow threshold (maximum packet length)
may be specified in the range 1-4095. An exception
is generated (see DPS register) if the threshold is
equaled or exceeded. Setting this register to OOH
(default) disables this function. The most significant
four bits of the overflow threshold are set in the
DUTH register.
o
3
o
2
Overflow Threshold Bits 0-7
B1SL B1 Data SLD to "S" Direction 11100 R, W
5
3
DOTH Overflow Threshold (Low Byte) 01111 W (RT)
This register provides access to the B2 channel data
flow in the direction from the "S" loop to SLD interface. Data can be read or overwritten by the microprocessor in intercept mode (see SCR register).
Also, data can be accessed so the MSB is in bit 7
(default mode) or flipped so that the LSB is in bit 7
by issuing the appropriate GCR command.
6
4
This address provides access to the transmit control
byte register pair in the SLD register bank. In SLD
master mode, data placed in this register is transmitted over the SLD link in the C byte. This is typically
control information sent to an SLD slave device
such as the 29C48. Data is only transmitted in SSM
(SLD master) mode.
B2data
7
5
6
data
B2LS B2 Data "S" to SLD Direction 11001 R, W
6
o
2
This address provides access to the receive control
byte register pair in the SLD register bank. In SLD
master mode, this register contains the received
control (C) byte from the SLD link. This is typically
control information read back from an SLD slave device such as the 29C48. Register contents are only
valid in SSM (SLD master) mode.
B1 data
7
3
4
data
B1 LS B1 Data "S" to SLD Direction 11000 R, W
7
5
6
o
",2 data
This register provides access to the B2 channel data
flow in the direction from the SLD interface to "S"
loop. Data can be read or overwritten by the microprocessor in intercept mode (see SCR register).
Also, data can be accessed so the MSB is in bit 7
(default mode) or flipped so that the LSB is in bit 7
by issuing the appropriate GCR command.
5
4
0
0
route through B2 bits 0, 1
0
1
route through B2 bits 2, 3
1
0
route through B2 bits 4, 5
1
1
route through B2 bits 6, 7
B2D When the rSw 0 channel is routed to the SLD in
the B2 byte (DPC bits 2-0 = 101), this bit sets
the value for the unused bits of the transmit
direction B2 byte (all zeroes or all ones).
5-35
intJ
iATC29C53AA
Transmit status, encodep as follows:
D-channel routing is programmed in bits 2-0 of this
register for both NT and TE operation. D-channel
processing can be bypassed to provide a clear 16K
bits per second channel over the SLD line if desired .
Bit 1/3/5/7 of the B2 channel or bit 1 of the S channel will be the first one transferred over the "S" bus
in this case.
BITS
Bit 4 if set to 1, the packet being transmitted was
aborted due to FIFO Underrun. The FIFO was
emptied, and no EOP tag was found.
Bit 5 if set to 1, the packet being entered to the FIFO
by the microprocessor was aborted due to
FIFO overrun. The FIFO was written to when
full.
Bit 6 if set to 1, the packet being transmitted was
aborted due to loss of priority, or loss of sync.
At a TE, priority is lost if the E-channel bit just
received does not match the last transmitted D
bit.
D-CHANNEL MODE
2
1
0
0
0
0
Processor inactive, disconnect
from SBUS
0
0
1
Loopback test mode (1)
0
1
0
Reserved
0
1
1
Processor active on SBUS,
normal operation
1
0
0
Processor inactive, raw D
through SLD S byte bits 1, 0
1
0
1
Processor inactive, raw D
through SLD B2 byte as set in
DPC4,5
1
1
0
Reserved
1
1
1
Reserved
RB Receiver busy. This bit is set when a packet is
currently being received. This bit does not affect
the RDP bit in EXS, or cause an interrupt.
Receive status. The status of the packet which the
microprocessor has access to (appears at RFO) is
encoded as follows:
BITS
Receive Status
2 1 0
0 0 0 Still receiving, no EOP yet
0 0 1 Good EOP
0 1 0 FCS error
NOTE:
1. Bit PEC.4 (EMO) must also be set to one to use the Dchannel loopback test mode when operating as a loop
slave (TE) if the loop interface is not synchronized.
0 1 1 FIFO underrun (read when empty)
1 0 0 FIFO overrun
received)
6
5
4
3
I ZIS I
unused
2
0
unused
PRI
1 1 0 Packet overflow (packet too long,
threshold set in DOTH)
ZIS When ZIS = 1, the transmitter will not perform
zero insertion on the outgoing D-channel
frame. The data in the FIFO will be transmitted
as is. When ZIS = 0, zero insertion is enabled
which is normal operation. The default for this
bit is o.
1 1 1 Abort or loss of sync
DUTH Underflow and
Threshold 01110 W (RT)
7
PRI When PRI = 0, the higher priority class (8) is
selected for the D-channel priority logic. When
PRI = -1, the lower priority class (10) is selected. This bit defaults to 1, selecting the lower
priority class.
I XB I
6
5
4
transmit status
3
I RD I
2
6
5
underflow threshold
4
Overflow
3
2
(High
Byte)
o
overflow threshold bits 11 -6
The underflow threshold (minimum packet length)
may be specified in the range 1-15. An exception is
generated (see DPS register) if the threshold is not
exceeded. Setting this register to OOH (default) disables this function. The upper four bits of the overflow threshold are also contained here.
DPS D-Channel Processor Status 00001 R
7
full when next byte
1 0 1 Packet underflow (packet too short,
threshold set in DUTH)
DPR D-Channel Priority 01011 R, W
7
(~IFO
0
receive status
XB Transmitter busy. This bit is set to 1 whenever
D-channel processor is transmitting. This bit
does not affect the XDP bit in EXS, or cause an
interrupt. This bit is zero when the transmitter is
inactive or awaiting priority on the D-channel.
5-36
inter
IATC 29C53AA
EXM Exception Mask 00000 W (RT)
76543210
I
0
I XSR I RSR I PC I sx I LS I XDP I RDP I
RSR request for receive FIFO data transfer. A complete D-channel packet has been received, or
the FIFO is full to the programmed level (set in
RFXF).
PC
Setting a bit to 1 in this register enables the associated exception to generate an interrupt, and to appear in the S byte of the SLD line. This register is
initialized to OOH, all interrupt sources masked.
change noted in peripheral interface inputs.
Read LPS bits 5-7 for status.
SX
exception noted in spare bit unit (multiframing
or A bit change). Read SBC for more information.
EXS Exception Status 00000 R
LS
loss or gain of synchronization to the "S" loop.
Read LPS for loop status.
7
I
X
6
5
4
3
2
1
0
I XSR I RSR I PC I sx I LS I XDP I RDP I
RDP D-channel processor exception, receive side.
Read DPS bits 0-2 to determine cause.
This is the main status register. It should be polled
first when investigating the source of an exception.
Some status is expanded in additional registers.
When unmasked, bits set in EXS cause an interrupt,
and affect the SLD Signaling byte status.
X
XDP D-channel processor exception, transmit side.
Read DPS bits 4-6 to determine cause.
GCR General Command Register 01010 R, W
7
6
5
XSR request for transmit FIFO data transfer. The
transmit FIFO is at the programmed level of
emptiness (set in XFXF). Or, if XFXF = 0, the
closing flag of a packet has been transmitted.
CODE
COMMAND
GRST
011XXX11
GDRAB
3
2
Writing one of the listed codes to the GCR register
causes the specified event to execute once. A new
command should not be written to GCR for five cycles of CLK. Where the code contains X's, those bits
have no effect. Reading the GCR register reads the
previous command.
EVENT.
Reset all internal units.
Clear receive FIFO to next EOP (ignore data from loop
until FLAG if none presently in FIFO).
011XXX10
GDRCL
Clear entire receive FIFO.
011XXX01
GDXAB
Abort and clear the transmit packet currently being
constructed by the microprocessor.
011XXXOO
GCXCL
Stop D-channel transmission, clear transmit FIFO, and
indicate idle on transmitted D-channel.
01 OXXX1 0
GDXMK
Mark EOP in transmit FIFO (no effect if FIFO empty).
010XXXT1
GLMX4,
GLMX2
010XXXOO
GSSY
Transmit INFO 4 (T= 0) or INFO 2 (T= 1) regardless of
receive state. GLMX2 must be issued once before
GLMX4 will cause INFO 4 to be transmitted. GTD must
be issued to after GLMX4 return to normal operation.
Synchronize S frame to the next SLD frame (valid only
when the loop is inactive).
001XXXNF
GB1F,
GB2F
N = select B1 (0) or B2 (1).
F == 0, don't flip (bit reverse) B 1IB2 between
PBUS and SBUS (MSB first).
F = 1, flip B1 IB2 between PBUS and SBUS (LSB first).
OOOXXXOA
GTST
Set PBUS address A5 to A (A = 1 for register test
mode).
000XXX1D
GTA,
Set 0 = 1 for loop activation command, set 0 = 0 for
loop deactivation command.
GTD
otherwise
no effect
o
command code
reserved for future use, should be masked.
111XXXXX
4
no action taken.
5-37
inter
iATC 29C53AA
(SLD) interface, the loopback occurs at the. interface
to the internal SBUS. None of the data formating, or
analog Circuitry is included. The loop interface must
be active and synchronized to use these loop back
features.
DL 1 = Loopback D toward loop, 0 = disable loopback
B2L 1 = Loopback B2 toward loop, 0 = disable loopback
B1 L 1 = Loopback B1 toward loop, 0 = disable loopback
DS 1 = Loopback D toward system, 0= disable
loopback
B2S 1 = Loopback B2 toward system, 0= disable
loopback
B1S 1 = Loopback B1 toward system, O=disable
loopback
LCR Loop Interface Control 00010 W (RT)
7
6
unused
5
4
3
2
I B1E I B2E IXMIT I
1
0
MODE
B1 E; B2E B-Channel Transmit Enables (no effect in
LSM modes)
o disable transmitter for Bn subframes
1 enable transmitter for Bn subframes
XMIT Transmitter Enable (no effect in LSM modes)
o power/down/disable transmitter (output is
high impedance)
1 enable transmitter
MODE Loop Interface Mode
bits
210
o0
0
LOFF power down/disable transceiver
o0
1
LOFF power down/disable transceiver
When operating as a loop slave (TE), bit PEC.4
(EMO) must also be set to one to use the D-channel
loopback toward the system interface (set by the DS
bit) if the loop interface is not synchronized.
o
0
reserved
LPS Loop, Peripheral Interface Status 00010 R
o
o
reserved
1 0 0
LSSA Adaptive Receive Timing, Slave (TE)
1 0 1
LSMH Hybrid Receive Timing, Master (NT)
Extended passive bus or point-to-point
P3S state of peripheral interface pin P3 when configured as an input
P2S state of peripheral interface pin P2
LSMA Adaptive Receive Timing, Master
P1 S state of peripheral interface pin P1
o
6
7
5
4
3
2
encoded loop interface status
(NT)
Loop interface status code:
LSMF Fixed Receive Timing, Master (NT)
Short passive bus
BITS
LLB Loop Interface Loopback Control 00111 R, W
7
I
0
6
5
432
I DL I B2L I B1L I
0
1
0
I DS I B2S I B1S I
4
3
reserved for future use, should be zero
mode: master(1)/slave(0)
2
transmitter enable (both LCR.3 AND LCR.2 are
set)
1, 0 11
10
01
11
For data looped back towards the loop, the analog
circuitry and data formating and deformating is included. For data looped back towards the system
5-38
=
=
=
=
active
initialize (init)
initialize
inactive
intJ
IATC 29C53AA
29C53AA LOOP INTERFACE STATES
BITS
Description
43210
1XXXX
Reserved for future use
01111
LSM3 active: sending INF04
01110
LSM2 remote init: receiving INFO 1
01101
LSM1 local inlt: send INFO 2 on local request
01100
LSMO inactive, powered up (receiver active)
01011
-(unused)LMP2 passive resync,
01001
LMP1 passive resync,
01000
-(unused)-
00111
LSS3 active: sending INF03
00110
LSS2 remote init: sync to INFO 21INFO 4
00101
LSS1 local init: send INFO 1 on local request
00100
LSSO inactive, powered up (receiver active)
00011
LSP3 active, receive only, successful passive resync
00010
LSP2 passive resync,
LSP1 passive resync,
00000
LOFF inactive, powered down (receiver inactive)
P30EN P3 output enable (also enabled by SST). 0
= input, 1 = output
R,W
I
6
0
AA
AA
< 16 frames correct
< 3 Pulses per frame
00001
PEC Peripheral Interface, E Channel Control 00011
7
< 16 frames correct
< 3 pulses per frame
01010
5
I EM1
4
3
2
I EMO I SST Ip3DENI P3
0
P3
P3 output value
P4
P4
P4 output value
PLENH D-Channel Packet Length High Byte 01110 R
auto-answer mode enabled (1), or disabled
(0)
7
6
5
4
Master, LSM modes
generate E channel from received D
10
force E channel to logical zero
11
force E channel to logical one
PLENL D-Channel Packet Length Low Byte 01111 R
normal E-channel function, contention resolution mechanism is enabled
01
ignore E channel, always transmit D-channel data without waiting for priority. Loss of
priority exception is suppressed
11
Force loss of priority
SST
present SLD status on P3 and P4 if 1, or if 0,
P3 and P4 are 1/0 pins controlled by PEC
bits 0-2.
o
This' register holds the upper byte of the length of
the current D-channel packet. The count is updated
as the packet is read out of the receive FIFO. Reads
of PLENH should be done a minimum of 3 CLK cycles after reading RFO..
Slave, LSS mode
XO
2
length
EM1, EMO
OX
3
7
6
5
4
3
2
o
length
This register holds the lower byte of the length of the
current D-channel packet. The count is updated as
the packet is read out of the receive FIFO. Reads of
PLENL should be done a minimum of 3 CLK cycles
after reading RFO.
5-39
lATe 29C53AA
RFXF Receive FIFO Excepti!)n pull ness 01100 R, W
PSR Position Selection Register 10001 R, W
7
6
5
4
3
2
.
0
7
any bit set
This register allows the processor to poll up to eight
29C53AA transceivers on the same microprocessor
bus at one time, with each having its own status bit
position in the byte. Using this method the processor
can check status on all 29C53AA devices with a single read.
See also RSR (Receive Service Request) and XSR
(Transmit Service Request).
This register cannot be accessed via SlD command.
RFN Receive FIFO Number 00100 R
7
6
543
EOP IMOREI FULL I
2
0
number of bytes avail.
MORE If MORE = 1, more information is available
in the receive FIFO beyond the first packet,
delineated by an EOP marker. If MORE =
0, no data lies beyond the first packet.
7
3
2
o
RFXF
654
3
2
0
All bits in this register reflect the same status, the
state of the RSR bit in the EXS register. When this
register is read, only those bits indicated by a 1 in
the corresponding bit positions in the PSR register
are enabled onto the microprocessor bus. The remaining bit positions on the microprocessor port
pins remain in a high impedance state during a read.
This allows up to eight 29C53AA transceivers connected to the same microprocessor bus to be polled
for status with one read. This feature is useful, for
example, in linecard applications where multiple
29C53AA devices are controlled by one microprocessor.
See also PSR (Position Selection Register) and XSR
(Transmit Service Request).
SBC Spare Bit Control 10000 R, W
76543210
I MFE I MDX I MS I SIE I MIE I MX I AXE I AX
All exceptions are generated at the beginning of the
ISDN frame following the event which causes the
exception.
MFE Multiframe function enable. When MFE = 1,
the spare bit unit is In the multlframe mode.
When MFE = 0, the 29C53AA will not perform
any of the multiframing procedures.
MDX Multiframe Q/S data change exception indication. When MFE = 1, this bit is set to 1 if a
Q/S bit quartet is received that is different
from the previous one received, and a spare
bit exception (SX in EXS) is generated. This bit
is cleared upon reading SBC.
MS Multiframe sync indication. When MFE = 1,
this bit indicates the multiframe synchronization status (1 = in sync, 0 = out of sync).
When MS changes from 1 to 0, a spare bit
exception is generated (SX in EXS). When
MFE = 0, this bit is always a one.
RFO Receive FIFO Output 01000.R
4
-
2
each bit set to state of RSR
The entire FIFO is filled if 1. The FIFO. is not
full if O.
number If at least one EOP is marked, this value is
the number of bytes to the first EOP.· If no
EOP is marked, this value indicates the
number of valid bytes in the receive FIFO.
5
3
RSR Receive Service Request 10010 R
FUll
6
4
If the number of bytes accumulated in the FIFO is
equal to or exceeds this 5-bit number, or if the receive FIFO contains a byte marked EOP, the receive
FIFO exception RSR is activated. Setting this register to zero disables this function. However, a packet
tagged EOP will still set the RSR exception.
This register indicates the number of bytes in the
receive FIFO as detailed below.
EOP
Minimum of one byte in the receive FIFO is
marked as the end of a packet if EOP = 1.
If EOP = 0, no byte marked as end of packet.
7
5·
unused
A one in any bit of this register enables that bit onto
the microprocessor bus when the XSR and RSR
registers are read. Those bits of PSR in the zero
state disable the corresponding bit positions of the
microprocessor bus of the 29C53AA so that those
bits remain in a high impedance state when RSR or
XSR are read.
I
6
o
data
Read from this register to read from the· receive
FIFO. Do not write to this location, as one byte will
be lost from the packet (read out ·from the FIFO).
Reads from this location should be separated by 4
ClK cycles.
5-40
inter
iATC 29C53AA
SIE Single frame interrupt enable. Setting this bit to
a 1 enables the generation of a spare bit exception (SX in EXS) every ISDN frame. The
single frame exception does not have an indication as such, but the indication should be
inferred if the SX bit in EXS and the SIE bit are
set. If SIE = 0, no single frame exception is
generated.
MIE Multiframe interrupt enable. When MFE = 1,
setting MIE to a 1 enables the generation of a
spare bit exception (SX in EXS) when the MX
bit becomes set. MIE = 0 masks the MX bit
from producing a spare bit exception.
SSX Spare Sit Transmit 00110 W (RT)
(MFE = 1/MFE = 0)
OS1OS4
are only valid when MFE = 1. OS1 is transmitted first.
FAE# FA echo enable. Valid only when MFE = 0
and in LSS (TE) mode. If FAE# is 0, the
29C53AA automatically echoes the received FA bit from the NT in the FA bit position of its transmit frame. If FAE# is 1, the
transmitted FA bit follows the state of bit
SSR.1. The default is FAE# = 0, and the
FA bit is echoed.
S
S bit transmitted. Valid only in LSM (NT)
modes. When MFE = 1, the S bit is located
at SSR.3, and when MFE=O, at SSRA.
When MFE = 1, the S bit is transmitted in
the frames of the multiframe when FA is not
equal to 1.
M
M bit transmitted. Valid only in NT mode
and MFE = o.
N = FA Control for the N bit. Valid only in the "NT
mode. If N = FA is set to 1 the N bit transmitted will equal the FA bit value. The N =
FA bit should be set toO for normal operation so that the N bit will be the complement
of the FA bit. The default is N = FA set to
MX
Multiframe exception indication. When MFE =
1, this bit becomes set to 1 on the first frame of
the 20 frame multiframe, indicating that new 0
or S transmit data can be written to SSX, and
that new 0 or Sreceive data is available in
SSR. MX is cleared upon reading SSC. If MFE
= 0, MX is not set. At the TE the multiframe
exception indication is not dependent on multiframe sync being established.
AXE Activation bit change exception enable. Setting AXE to a 1 enables the generation of a
spare bit exception (SX in EXS) when AX becomes set. For AXE = 0, the A bit exception is
suppressed.
AX Activation bit exception indication. This bit becomes set to 1 after a change in the received
A bit value at the TE, only after the loop interface has acquired synchronization. The state
of the A bit can be read in SSR. This bit is
cleared upon reading SSC.
o.
FA
FA bit transmitted. When MFE = 0 (and
FAE# = 1 for LSS mode) this bit controls
the value of the transmitted FA bit (normally
0). If MFE = 1, this bit controls the value of
the transmitted FA bit during frames not involved in the multiframe procedure.
Control for the A bit. Valid only in the NT
mode. The complement of this bit is sent in
the A bit position of the transmit frame. For
the default value of zero the A bit is transmitted as a one. During activation, the A bit
is set to zero during INFO 2 regardless of
the state of A # .
SSR Spare Sit Receive 00110 R
7
6
5
4
3
las4/xlaS3/xlaS2/xlaslIsi S/M
2
I
N
0
I
FA
A
0 or S bit quartet transmission. These bits
I
A#
(MFE = 1/MFE = 0)
OS1- 0 or S bit quartet received. These bits are
OS4 only valid when MFE = 1. OS1 is received
first.
S
S bit reCeived. Valid only in LSS (TE) mode.
When MFE = 1 the S bit is located at SSR.3,
and when MFE = 0, at SSR.4.
M
M bit received. Valid only in LSS mode. This
bit is not indicated in SSR when MFE = 1.
N
N bit received. Valid only in LSS mode.
FA
FA bit received.
A
A bit received. Valid only in LSS mode.
SCR System Interface Control 00100 W (RT)
7
6
unused
5
4
82M
o
2
3
81M
81M
This register configures the system, or SLD interface. It defaults to OOH upon power up, which is the
NOTE:
The 0 and S bit quartets are updated every 20
frames, while the remaining bits are updated every
frame.
"
5-41
inter
iATC 29C53AA
SLO slave mode. In this mode, the 29C53AA expects to receive its timing reference from the SLO
interface. Therefore, in a terminal or other application where the SLO interface will be a signal source,
the SLO mode master mode should be programmed
immediately after reset.
MCS Multiple Byte Configuration and Status Transfer
o use control byte only (one byte per SLO frame)
use both control and signaling bytes (two bytes
per SLO frame)
MF Multiple Byte FIFO transfers (both directions)
Bits 5, 4 B2 Mode
o
use control byte only (one byte per SLO frame)
o 0 enable normal SlO transfers (default mode).
use both control and signaling bytes (two bytes
per SLO frame)
1 0 microprocessor intercept of B2
o 1 loop back B2 toward system interface
SS
Single Status Byte Transfer (29C53AA to SLO
master)
o
respond to poll command received in SLO control byte
1 1 loop back B2 toward loop interface
Bits 3,2 B1 Mode
o 0 enable normal SlO transfers (default mode).
SC
1 0 microprocessor intercept of B1
o
respond immediately beginning in the next half
of the SLO frame
Single Command/Configuration Byte· Transfer
(SLO master to 29C53AA)
data follows in control byte of next frame
data follows in the same frame's signaling byte
o 1 loop back B 1 toward system interface
SR Signaling Byte Receive 11011 R, W
1 1 loop back B1 toward loop interface
7
6
5
3
4
Bits 1, 0 System Interface Mode
2
o
data
00 SSS SlO slave (default mode). The
29C53AA SIOR and SCL pins are
inputs, and the 29C53AA transmits
data on SLO when SOIR is low
1 0 SSN SLO interface for intelligent NT2. The
29C53AA generates SCL and SOIR,
and transmits data on SLO when SOIR
is low
o 1 SSM SLO master. The 29C53AA generates
SCl and SOIR, and transmits data on
SLO when SOIR is high.
1 1 reserved
This address provides access to the receive signaling byte register pair in the SLO register bank. In
SLO master mode, this register contains the received signaling (S) byte from the SLO link. This is
typically signaling or status information read back
from an SLO slave device. Register contents are
only valid in SSM (SLO Master) mode.
SX Signaling Byte Transmit 11111 R, W
7
6
543
2
0
data
SOC SLO Data Transfer Configuration 00101 W (RT)
7
6
unused
543
2
1
0
I CE I MP I MC5 I MF I 55 I 5C I
This register has no effect in SLO master mode
(SSM).
CE
Command Enable
o
Ignore commands received on the SLO line
(except when RO and WR are both low during
reset)
1
Enable execution of SLO commands
MP
Multiple Transfer to SLO Master
o
respond to poll command received in control
byte
This address provides access to the transmit signaling byte register pair in the SLO register bank. In
SLO master mode, data placed in this register is
transmitted over the SLO link in the S byte. This is
typically signaling or status information sent to an
SLO slave device. Register contents are only transmitted in SSM (SLO Master) mode.
XFI Transmit FIFO Input 01001 W
7
6
5
4
3
2
o
data
This is the input address for the transmit FIFO. This
register should not be read, as it will cause the previous contents of XFI to be entered into the FIFO, and
the FIFO count (XFN) to be incremented. Writes ·to
this register should be separated by 3 ClK cycles.
respond immediately beginning in the next half
of the SLO frame
5-42
IATC 29C53AA
XFN Transmit FIFO Number 00101 R
7
6
4
5
3
2
I I I
0
XSR Transmit Service Request 10011 R
7
6
5
4
3
2
o
each bit set to state of XSA
number of free bytes
0
All bits in this register reflect the same status, the
state of the XSR bit in the EXS register. When this
register is read, only those bits indicated by a 1 in
the corresponding bit positions in the PSR register
are enabled onto the microprocessor bus. The remaining bit positions on the microprocessor port
pins remain in a high impedance state during a read.
This allows up to eight 29C53AA transceivers connected to the same microprocessor bus to be polled
for status with one read. This feature is useful, for
example, in linecard applications where multiple
29C53AA devices are controlled by one microprocessor.
This register indicates the number of empty bytes in
the transmit FIFO. The count requires 5 ClK cycles
to update after a write to XFI.
XFXF Transmit FIFO Exception Fullness 01101 R,
W
7
6
unused
5
4
3
2
o
o
XFXF
If the number of untransmitted bytes in the transmit
FIFO is equal to this 5-bit number, the transmit service request (XSR) bit is set in EXS.
See also PSR (Position Selection Register) and RSR
(Receive Service Request).
5-43
IATC 29C53AA
• Notice: Stresses above those listed under '~bso
lute Maxif11um Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating Conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM' RATINGS
Temperature Under Bias ......... - 10'C to + SO'C
Storage Temperature .......... -65'C to + 150'C
Voltage on any Pin .... Vss -0.5V to Vcc to +0.5V
Maximum Voltage on Vee
with Respect to Vss ..................... + 7V
T()tal Power Dissipation ..... '............. 500 mW
NOTICE: Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS Vee = +5V ±5%;Vss = OV;TA
Typical Values are at TA = 25'C and Nominal Power Supply Values
= 0'Ct070'C;
DIGITAL INTERFACES
Symbol
Parameter
Typ
Min
IILK
IOLK
Input/Output leakage Current
(Excluding lR+, lR-, LX+, LX-)
VIL
Input low Voltage
VIH
Input High Voltage
VOL
Output low Volta~e
VOH1
Output High Voltage
2.4
VOH2
Output High Voltage
0.9 Vee
C
Pin Cap. (ex. lR±, LX±)
Max
Units
±10
p.A
O.S
Test
Conditions
Vss
s: VIN s: Vee
V
2.0
V
0.45
V
IOL = +2.0mA
IOL = 1.2 mA for
P1-P4, SlD
V
IOH
V
=
IOH =
-400 p.A
-40 p.A
pF
10
POWER SUPPLY CURRENT (Averaged over 1 ms)
Symbol
Typ
Max
Units
Test Conditions
ICC(p)
Power Down (Standby)
4
8
mA
SlD and ClK Active
ICC (I)
Idle Operating Current
8
12
mA
Receiver, SlD, ClK
Active
Vee(N)
Normal Operating Current
20
mA
Everything is Active
(Excluding Current
for Output loads)
Parameter
A.C. Characteristics
Vcc
Min
= 5V ± 5%; Vss = OV; TA = 0'C-70'C; ClK = 3.S4 MHz
RECEIVER
Symbol
Parameter
VRD
Minimum Received Differential
Pulse Voltage
llR
lR + , lR - Input Impedance
CIR
lR+, lR- Input Capacitance
Min
30
Typ
Max
Units
300
400
mV
60
10
5-44
20
Test Conditions
KO
Each Pin
pF
Each Pin
inter
IATC 29C53AA
TRANSMITTER
Symbol
Min Typ Max Units
Parameter
Test Conditions
1900 2000 2100 mV Rl = 2500 (Note 1)
VXD
Transmit Differential Pulse Voltage
ZOXI
LX+, LX- Output Impedance
KO
Each Pin, Transmitting Binary One
ZOX2
LX+, LX- Output Impedance
2
5
0
Transmitting Binary Zero, Each Pin
Cox
Output Capacitance
30
40
pF
Each Pin
Cl
Capacitive Load between LX + , LX-
1500
pF
Parallel with 3000 Directly
across LX + and LX - (Note 2)
tMR
Transmit Pulse Rise Time
400
ns
Test Load
IXl
Source, Sink Current Limit
14.4
mA Rl = 75
PHU
Pulse Height Unbalance
tpw
Pulse Width
30
60
10
0.5
3
5.16 5.21 5.26
%
Test Load
,...s
CLK = 3.84 MHz ± 100 ppm (Note 3)
TIMING
Symbol
Min Typ Max Units
Parameter
0
J
Timing Extraction Jitter ("S" Slave Mode)
PO
Total Phase Deviation lX with Respect to lR -7
±5
%
+15
%
Test Conditions
ClK = 3.84 MHz ± 100 ppm
NOTES:
1. This is essentially the open circuit voltage.
2. This is a stability test. Overshoot less than 25%, damping time less than 1.5 !Ls.
3. Free running, measured between zero crossing of adjacent pulses. During DPLl adjustment in lSS (TE) mode, the
framing pulse may be wider or narrower by one cycle of elK (260 ns).
Lx3]
2S0pF
LX-
_
39.0.
160.0.
39.0.
270097-16
270097-15
Differential Output
across LX+, LX- for VXD
across 160n lest circuit
load for IMR, tpw
Transmitter Test Load
5-45
iATC 29C53AA
TKDV
SLDouT-----1-1c::::::::::::::::t~c:::::::::::!
TSDV 1-TKDV
-TKDE
~SJ=ji_
SLD'N ~,.--------------------------------~S r---- TEST POINTS
~~8
0.45
< O~~
2.0:
270097-13
A.C. Testing: Inputs are driven at 2.4V for a Logie "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0". Load capacitance CL =
100 pF.
Figure 11. A.C. Testing Input, Output Waveform
5-48
inter
iATC 29C53AA
3.84 MHz :I: 100 ppm
SLD
SDIR
+5
(5)
INT
CS
R
if""
ALE
ADO-AD7
270097-14
Figure 12. 29C53AA Application Diagram
NOTES:
1. The SLD port will be connected to an SLD master in NT applications, or to SLD slave devices such as the 29C48
programmable CODEC/Filter or appropriate data communication devices in TE applications.
2. Series resistance is used to increase the output impedance during transmission of a binary zero to greater than 200 on
the loop side. It also serves as protection against surges when used in combination with external protection diodes.
3. A lower turns ratio (e.g., 1:1.8) may be used at the cost of a lower ratio of received signal to locally generated noise.
4. Appropriate protection circuitry can be added depending upon the application.
5. Pullup selected for approximately 1 mA IOL.
5-49
intJ
89151
T-LINK COMMUNICATIONS CONTROLLER
•
Complete Implementation of the T -Link
Rate Adaptlon Protocol in a Single
Device
•
•
•
Adapts Synchronous or Asynchronous
Terminals to 64 Kbitts Clear or
Restricted Channels
Rate Adaption of Synchronous or
Asynchronous Data at Rates of 300
Bitts to 64 Kbit/s
Provides Interworking Capability to the
ISDN
•
•
•
•
•
•
•
Supports Exchange of Terminal Status
Indicators
Provides Error Correction for Data Rate
of 9600 Bltls or Less
General Purpose Parallel
Microprocessor Interface
Serial Terminal Interface Including
Handshake Signals
Serial Synchronous Network Interface
SLD Compatible
IDL Compatible
The 89151 T-Link Communications Controller (TCG) is a highly integrated communications controller which
provides a complete implementation of the T-Link rate adaption protocol. The T-Link Communications Controller is used to rate adapt synchronous and asynchronous terminals to the public switched digital network, or an
ISDN, providing transparent, digital end to end communications. The 89151 TCC includes a terminal interface
port supporting synchronous or asynchronous terminals, a synchronous network interface port, and a general
purpose parallel microprocessor port. The 89151 TCC can operate as a peripheral to a wide variety of microprocessors.
89151
T-LiNK COMMUNICATIONS
CONTROLLER
CSB A1 AO D7D6D5D4D3D2D1DO RDBWRB RDYTDR RDR
i
Parallel Microprocessor Interface
290197-1
Figure 1.89151 T·Link Communications Controller
5-50
October 1988
Order Number: 290197-001
inter
89151
The T·Llnk Rate Adaptlon Protocol
T-Llnk Communications Controller Overview
T-Link is a full duplex byte oriented rate adaptation
protocol designed to transfer either asynchronous or
asychronous data over a switched digital circuit at
data rates from 300 bitls to 64 Kbitls. T-Link can
operate over a 64 Kbitls clear channel, or over a
64 Kbitls restricted channel with a 1's density requirement. T-link can also be used on a 64 Kbitls
channel with capacity restricted to 56 Kbitls due to
the use of inband signaling or a 1's density requirement of today's T1 networks. T-link provides:
The 89151 T-Link Communications Controller provides a T·Link building block for implementing a Terminal Adaption Device that may be used for an ISDN
TA or other TAD application. The complete rate
adaption protocol is built into the 89151. The 89151
includes three interfaces which facilitate its use in
DCE applications~ supporting the T-Link rate adaption protocol. There are the serial terminal interface,
the serial network interface and the parallel microprocessor interface. Refer to Figure 1.
The terminal interface supports synchronous and
asynchronous serial terminals. As T-Link carries the
terminal status across the connection, the standard
EIA handshake leads are provided. Clocking can be
sourced by the attached device or by the 89151.
End to End Synchronization
Support of terminals with synchronous data rates
from 1200 bit! s to 64 Kbitl s
Support of terminals with asynchronous data rates
from 300 bitls to 19.2 Kbitls
The network interface is designed to pass serial
data between the 89151 and the network side of the
terminal adaptor. It can operate. in one of two
modes. In one mode, the network interface consists
of a serial input, serial output, a 2.56 MHz bit clock,
and an 8 KHz synchronization clock. This mode is
called IDL. In the second mode, it supports the SLD
interface.
Exchange of EIA or CCITT DTEIDCE lead status
User data (synchronous or asynchronous) transfer
Error correction for user data rates of 9600 bitls or
less
The microprocessor interface is used to pass commands and status between a local microprocessor
and the 89151. Options for T-Link control can be
selected. This interface includes an eight bit parallel
data bus, read (RDS) and write (WRS) Signals, a
ready (ROY) signal and address lines (AO, A 1). This
port supports a wide variety of microprocessors and
microcontrollers.
Networks providing circuit switched 64 Kbitls data
transmission are ideal for providing high speed, wide
area data transfer. T-link provides a rate adaption
protocol which can be used by a Terminal Adaption
Device (TAD) to connect present DTEs to such networks. The T-link protocol can be used on existing
networks as well as on the ISDN (Figure 2).
290197-2
Figure 2. Rate Adaption for the Switched Digital Network
5-51
inter
89151
A specific example of an ISDN terminal adaptor is
shown in Figure 4. Here the 89151 is used along
with the 29C53 Digital Loop Controller, which provides access to the "S" reference point of the ISDN'
basic rate interface. The 89151 T-Link Communications Controller connects directly to the SLD interface of the 29C53, and is used to rate adapt a nonISDN terminal to one of the 64 Kbitls basic rate 8
channels. The TCC can operate over either the 81
or 82 channel, and so it can share the SLD interface
with another SLD slave device, such as the 29C48
programmable CODEC/Filter. Channel data can be
complemented by a TCC package pin. The layer 2
and 3 ISDN signaling functions are performed by the
80188.
Applications
Figure 3 illustrates atypical TAD implemented using
the 89151 T-Link communications Controller. The
serial terminal interface can support a variety of protocols, such as RS232CIV.24, V.35, RS449, etc.
The human interface provides keypad, switches and
display for example. The network interface block
provides the physical connection to the network and
is dependent on the type of network involved. The
microprocessor is in charge of responding to user
inputs, setting up the connection and controlling
T-link options. The entire T-Link rate adaption protocol is performed by the 89151, providing a transparent data link once the connection is setup.
SERIAL
'TERMINAL
INTERFACE
SERIAL
NETWORK
INTERFACE
89151
T-LINK
CONTROLLER
i
HUMAN
INTERFACE
MICROPROCESSOR
290197-3
Figure 3. Terminal Adaption Device (TAD) Based on the 89151
RS232C
80188
290197-4
Figure 4. ISDN Terminal Adaptor Using T-Link
5-52
intJ
ISP188
ISDN SOFTWARE PACKAGE FOR THE 80188
•
•
•
•
•
•
•
•
•
•
Complies with CCITT
Recommendations for Layers 1, 2 and
3 of the ISDN User Network Interface
Device Drivers for Intel's
IATC29C48/C50A, IATC29C53,
and 82530
IntellAPX 80188 Based
Software License and Source Code
Included
Written in Microsoft "C" Language
IBM PC Development Environment
PC Plug-In Development Boards
Available
Debug MonitorlDisplay Supported
Comprehensive Support Services
Available from DGM&S, Inc."
Reference Sold by Intel
The ISDN Software Package for the 80188 (ISP188) is specifically designed for ISDN terminal applications
using Intel's Advanced Telecommunication Components (iATC). The software supports the iATC 29C53 Digital
Loop Controller, the iATC 29C48/29C50A Feature Control CODEC/filter combos (for voice conversion), and
the 82530, Serial Communications Controller.
ISP188 is based on the 8086 architecture and can be used with the 80188/186,80286 and 80386 microprocessors. The software source modules are written in "C" language using the Microsoft compiler. The modules
are well defined to permit integration with customer supplied software.
ISP188 supports the recommendations set forth by CCITT for the datalink and network layers (1.440, 1.441, and
1.450,1.451) of the OSI Reference Model. The iATC 29C53 supports the physical layer (1.430). Combined, the
29C53 and ISP188 implement the standards now in place for the "S" reference point (layers 1, 2, and 3).
ISP188 package includes a software license for incorporation into OEM products and a copy of the source
code is provided on a 5% inch floppy disk.
A PC co-processor board is available that contains the Intel components and other necessary hardware to use
ISP188 to establish a voice call and simultaneous circuit switched data or PC to PC file transfer through ISDN
switched access. In addition, demonstration routines are included to show examples of the same capabilities
in a back to back PC environment (local, no switch involved). Additionally, a debug port is provided on the
board and supported by the software so that diagnostic messages can be enabled and sent to a printer or
terminal over an RS 232·C connection.
The PC card and software combined can be used for ISDN hardware or software development or be included
in an OEM product. Typical applications for ISP188 include digital telephones, feature telephones, integrated
voice/data terminals (IVDT), and terminal adapters.
"Dale, Gesek, McWilliams & Sheridan, Inc.
APPLICATION
PRESENTATION
SESSION
TRANSPORT
NETWORK
DATA LINK
PHYSICAL
81
B2
CHANNELS
LAYERS
290149-1
Figure 1. OSI Reference Model
5-53
November 1987
Order Number: 290149-001
inter
ISP188
D-channel and link control (29C53)
B-channel control (82530, 29C48/C50A)
B-channel data transfer (82530)
Voice analog control (29C48/C50), DTMF generation, alerting tones
PC bus interface via 8K x 8 FIFO (SM1 & SM2)
FUNCTIONAL DESCRIPTION
ISP1 BB is designed to establish, maintain, and teardown vOice and circuit switched data links on the
basic rate 2B + D "S" bus interface. The software
package provides the "out of band" "D" channel
Signalling software for call control. This includes layer 2 LAPD, and layer 3 for basic voice services and
circuit switch data calls on the B channels.
The D-channel and link control driver interfaces the
software to t!1e 29C53 Digital Loop Controller. It supports the activation, deactivation, error detection
and D-channel data transfer functions on the "S"
bus. The device driver supports the following primitives as its interface to layer 2 of the ISDN D-channel:
PH-DATA (Transmit and receive packets from layer
The software was designed and tested with a PC
plug-in card which functions as a communication coprocessor in an IBM PC, XT, or AT host environment. The co-processor board contains the Intel
ISDN components for which the software was designed. All of the software modules run on the
board, while some support software runs under MSDOS. A Shared Memory Interface (SM1 and SM2)
which is contained on the co-processor is used for
communication between the host environment and
the board. Figure 2 outlines the software modules,
where they run and devices for which drivers are
supplied.
2)
PH-ACTIVATE (Activate or sense activation of the S
bus link)
PH-DEACTIVATE (Deactivate or sense the deactivation of the S bus link)
PH-MPH_ERROR (Detect and report link level error
conditions to the management entity)
ISP188 is configured to be compatible with the
AT&T #5ESS Central Office switch and is compatible with the 5E4.1 Generic Basic Rate Interface
specification. A PC/XT / AT host configured with the
coprocessor board and loaded with ISP188 may be
connected to an AT&T #5ESS Basic Rate Interface.
The B-channel control driver is used to control access to the B-channels. Access is through the following procedures:
Enable/Disable voice to B1 or B2 (29C48/C50A)
Enable/Disable 82530 channel A to B1 or B2
Enable/Disable 82530 channel B to B1 or B2
Enable/Disable B2530 channel A to 29C48/C50Athis permits tone generation to speaker or ear piece
Layer 1, ISDN Hardware Device Drivers
The device drivers allow the software to interface
with the hardware components. The following hardware device drivers are provided:
5-54
inter
ISP188
PC SIDE
MS DOS
INSTALLABLE "5 DOS DRIVER
CO-PROCESSOR SIDE
W
A
MULTI-TASKING REALTIME KERNEL
"
A
G
E
M
E
N
T
DEBUG PROCESS
RS232-C
ASYNC
HOOK
SWITCH
PORT
SLD BUS
ALERTING
DEVICE
L...---o-~ ~
SPEAJ--1~--'
L....IIM...-
....- - I LX-
~VV~~~~--ILR+
·~~;·;-310
~
LX+
29C53
V220MA48
---1_--'
o..JOM.....- ....- - I
LR-
270209-4
Figure 4. Protection
may not exceed the power supply by more than 500
mY. The 5V and ground connections to the diodes
should be as close as possible to the 29C53 power supply pins, which in tum should be decoupled by a 0.1 ,...F
capacitor. The capacitor serves a secondary function of
bypassing surge currents. The particular diodes chosen
are dependent on the expected surge current, however,
BAT85 from Philips used in this application can withstand 200 rnA forward current while presenting a maximum of 10 pF capacitance across it. The maximum
current through the diodes can be limited by placing a
resistor in series with the diodes and the transformer.
The value of this resistance can be extracted from the
transformer design discussion. To further limit the current to the 29C53, the series resistance can be split,
with part of it on the 29C53 side of the diodes, and part
of it on the transformer side of the diodes. For the
receive direction it is possible to replace the diode
bridge by placing a resistance in series with the 29C53
receive pins. This series resistance will limit the surge
current that the 29C53 is exposed to. The value of this
resistance is limited by the input impedance presented
by the 29C53 and the loss that can be tolerated in the
received signal. The receive differential input imped-
ance of the 29C53 is 100 KO, hence a 10 KO resistor in
each arm will reduce the received signal by 17%.
In case of a mains cross, the loop can be made to self
recover by using thermal devices such as the positive
temperature coefficient thermister (PTC). Keystone
Carbon Company has a range of PTCs specific to telephone line applications that they refer to as resettable
fuses. Economic considerations may make this unjustifiable in which case a fusible resistor or link may be
used.
Further protection may be deemed necessary, in which
case two varistors can be placed across the line close to
the transformer. The varistor has a volt-current relationship similar to a diode i.e. after a specified voltage
across the varistor is reached, the current through it
will rise dramatically; thus clamping the voltage to the
specified level. A typical varistor that may be used as a
back-up protection is the GE V220MA4B. This device
typically presents a 21 pF capacitance.
The ideas discussed thus far are encompassed in Figure
5 for a minimal component count protection scheme.
5-81
inter
AP-282
270209-5
Figure 5. Protection with Minimal Components
For the core RM6PLOO-3E2A
LINE TRANSFORMER
AL = 6710
A transformer is used at both the terminal and the line
card to provide isolation from the line. A well balanced
1.430 transformer resolves the issue of DC currents
since they induce self-cancelling fluxes. Generally
speaking, a pulse transformer with minimum leakage
inductance and· self capacitance is required. The impedance templates in 1.430 specify the minimum value of
the inductance required at the line side. This value can
be calculated to be 20 mHo A further requirement is to
minimize the winding resistance, so that a minimal
voltage is dropped across it. A 2.5: I ratio transformer
can be used with the 29C53 to produce the proper pulse
amplitude. The transformer design discussed below can
be used with the 29C53 at either the line card or the
terminal. Alternatively it can be used for example purposes to aid designs.
±
25%
Therefore minimum
AL = 5032 '" 5000
The number of turns, Ns, required for 20 mH is given
by:
Ns = 103 ~LlAL
Ns = 70 turns
L - required inductance in mH
- assume 25 mH is required
The 29C53 side winding will require 2.5 times this
number of turns.
Np = 175 turns
The transformer is now ready to be wound, the 32
gauge wire will just fill the RM6PCBI bobbin. The
bobbin is started by bifilar winding the 175 turns. Bifilar winding is accomplished by taking two separate
pieces of wire and winding them simultaneously. The
finish of one winding is then soldered to the start of the
other and often, as is the case in this implementation,
the point of connection of the two wires (center tap) is
brought out to a pin of the transformer. The remaining
ends (start and finish) now comprise the winding. The
transformer is now followed by I Y4 layers of insulating
tape. The insulating tape used was the Permacel P-256
which forms a dielectric capable of withstanding 5 KV,
this serves to protect the line card and the subscribers
The RM series of ferrite cores are chosen to facilitate
easy winding and PCB mounting, additionally the RM
series is available internationally from various vendorsFerroxcube in the U.S. and Mullard in Europe, to name
two. The RM6 core was selected to be the smallest size
that accommodates wiring which does not exceed the
maximum allowable DC resistance. The core material
has to have a high enough permeability to allow the 20
mH inductance with a minimum number of turns
hence, the Ferroxcube core material 3E2A was selected. This material has a very high inductance factor, AL.
This is given by the manufacturer as the inductance (in
mH) per 1000 turns.
5-82
inter
AP-282
from lightning induced surges. The 70 turns are then
bifilar wound; this results in a well balanced transformer. The start of one winding should be connected to the
finish of the other and brought out to a pin, thus creating a center tap on the line winding. The transformer is
then finished with 11/. layer of insulating tape. The
transformer thus designed gave satisfactory results in
the lab and is characterized by the following:
Secondary inductance
Ls=26mH
Secondary leakage inductance
Is = 20l£H
Secondary winding resistance
Rs = 1.50
Primary winding resistance
Rp = 2.70
larger core will make it possible to use a thicker wire.
Both of these factors will contribute to reduce the winding resistance, hence a larger value diode protection resistor may be used. Alternatively, the transformer turns
ratio can be decreased so that the output voltage is increased and hence more of it can be dropped across the
series resistance. This in tum means that the value of
this protection resistor can be increased. However, note
that the 29CS3 is only capable of driving loads greater
than 2000. If a turns ratio of 1.8:1 is used then the
overall series resistance can be 640. This also increases
the output impedance to 200 while transmitting a
pulse. As discussed earlier this resistor can be larger on
the 29C53 receive pins.
The capacitance between the two bifilar windings was
measured to be 100 pF and this may be too high for
certain applications. For this case the bifilar winding
can be replaced by the cross winding technique shown
in Figure 6a. The two windings are now wound in opposite directions, one wire is on top on the top side
while the other is on top on the bottom side. This technique reduced the above mentioned capacitance to less
than SO pF.
Some establishments may require further line isolation
from the transformer in which case a Faraday shield
can be placed in between the primary and the secondary windings. The Faraday shield can be made by
wrapping 1'14 layers of a copper tape (such as the permacel P-389) between the two windings. The copper
tape should be insulated from the windings and should
be brought out to the local ground. As well as isolating,
the Faraday shield also serves to reduce the interwinding capacitance.
The transformer designed was connected up as shown
in Figure 6b to measure its longitudinal balance.
2500HM
50 OHM :t 0.02%
270209-7
Figure 6a. erosswlndlng
The 29CS3 has been designed to drive voltages as specified in the 1.430, since the transformer presents a series
resistance, some of this voltage will be dropped across
it. For the transformer designed above, the overall series resistance is (2.7 + I.S.6.25) = 120 which will
result in a 3.8% error over the allowed peak transmit
signal in 1.430. This is acceptable as 1.430 allows a 10%
error for the peak voltage. If series resistors are required to protect the Schottky diodes, their value may
be calculated by having the maximum allowed peak
voltage error. Note that equal value resistors should be
placed on both arms of the line. If larger values of protection resistors are required, the above procedure may
be repeated with a larger core. This will allow the same
inductance to be achieved with a fewer turns and the
50 OHM :t 0.02%
270209-6
Figure 6b. longitudinal Balance
Lei v = vf/2.S
Then longitudinal balance is given by: 20 Log VIVo
Measurements conducted showed this figure to be better than 70 dB for the frequency range of 10 KHz to 1
MHz.
The center tap on the primary (29C53 side) is coupled
to ground via a 10 nF capacitor. In this manner longitudinal signals on the primary are bypassed to ground.
Measurements produced greater than 70 dB of longitudinal signal rejection.
5-83
inter
Ap·282
When designing the System board, special care should
be paid to the layout. The transformer and the 29C53
should both be placed on a ground plane. The connecting tracks from the 29C53 to the transformer should be
as short as possible. The two devices should be placed
close to the edge where the transmission lines interface,
while the high frequency logic should be placed on the
opposite edge. The analog ground wiring should follow
a star configuration and should have a separate isolated
lead originating from the system ground where it enters
the board.
can be obtained without overshoot is for the critically
damped case and is given by:
Though the analysis of pulse transformers is beyond the
scope of this brief (2), one should be aware of the pertinent parameters affecting the good reproduction of the
pulse. The pulse transformer is generally analyzed by
different equivalent circuits, depicting the varying phases of the pulse.
The fall period is characterized by the second order
circuit of Figure 7c; the primary concern here to prevent severe undershoot or backswing when the 29C53
transmitter is in the high impedance mode. This can
best be achieved by having an overdamped system,
which is the case when:
Ir = 3.35
race
where a = RL / (Rg
+
Ru
For the top period, there will be sonie decay leading to
a fractional droop, this is given by:
0'"
7'
Lp
R
where
7' =
pulse widlh
R = RL and Rg in parallel
Lp> 4CRL2
Figure 7 shows these circuits. The pulse shape is then
optimized by considering the transient response of the
equivalent circuits.
Commercially available pulse transformers exist which
are compatible with the 29C53. Some examples are given in Table 1. Most manufacturers will modify their
design to meet the requirements of a particular application.
The pulse response of the transformer is characterized
by a finite rise time, a decaying top period and finite fall
time as depicted in Figure 7d. The fastest rise time that
RL - Load impedance
c - Shunt capacitance
L - Leakage inductance
lp - Primary inductance
a) RISE PERIOD
b) TOP AND DECAY PERIOD
d) PULSE RESPONSE
c) FALL PERIOD
270209-8
Figure 7. (a) Equivalent Circuits for Rise Period
(b) Top and Decay Period (c) Fall Period (d) The Pulse Response
5-84
inter
AP-282
TABLE 1. Manufacturers of Pulse Transformers
Manufacturer
Location
Winding Ratio
Part No.
AlE Magnetics
St. Petersburg, FL
(813) 347-2181
1.8:1
2.5:1
325-0228
325-0172
Schott Corporation
Nashville, TN
(615) 889-8800
1.8:1
2.5:1
11207
11124
CTM Magnetics
Tempe,AZ
(602) 967-9447
1.8:1
2.5:1
22087
25585
Pulse Engineering
San Diego, CA
(619) 268-2400
1.8:1
2.5:1
64994
64996
POWER EXTRACTION
The same transformer can be used at both the line card
and the terminal, and the same protection scheme can
be used at both ends of the loop. The need now arises to
provide power to the terminal. There are a number of
ways of providing power to the terminal, for instance a
secondary cell can be used as battery back-up in con- .
junction with a main supply. There is also some scope
for trickle charging secondary cells from the line or .
from a small solar cell array, but the drawback with
secondary cells tends to be their short life span. This
disadvantage can be offset by using special purpose primary cells as a back-up supply, these do not need any _
charging circuitry and can be expected to have life expectancy twice that of the secondary cells. Finally, the
power can be fed from the switch, in which case a regulator is required at the terminal to extract the power off
the line. Figure 8 illustrates this approach.
-
TERMINAL
A DC to DC converter is required to convert the line
voltage to 5V for the local circuitry. In order to obtain
the lowest losses in the conversion process, it is necessary to use a high efficiency regulator, specifically, a
switched mode regulator. Basically, there are three
types of switched mode power supplies, the forward,
the push pull and the flyback converter (3). This sec-'
tion is devoted to the flyback implementation of a DC
to DC converter. The flyback is the most suitable converter for this application, as it provides the highest
achievable efficiency and the simplest drive circuitry.
Figure 9 shows a block diagram of a flyback converter.
OUT
SWITCH
270209-10
Figure 9. Flyback Converter
270209-9
Figure 8. Power Extraction
l
::!!
a::a
...?~
UI
c
o_
ex.
0
J>
'P
~
m C
~
o
oo
~
CD
i.,
270209-13
AP·282
In the flyback inductor, energy is inductively stored
during the switch on period, and then passed to the
load during the switch off, or the flyback period. During the switch on period, the output didde does not
conduct so that the energy in the choke (although appearing as a transformer, this element will be referred
to as the choke in accordance with its function) builds
up with rising current. While the switch is off the choke
voltage reverses in polarity causing the output diode to
conduct whereupon the inductive energy is discharged
into the output capacitor to form a DC voltage. Regulation is achieved by modulating the oscillator duty cycle,
which effectively varies the switch on/off periods. In
Figure 9 the diode bridge ensures the correct polarity
for the converter while the opto-isolator completes the
input to output isolation.
current. The current through the regulating diode is
proportional to the voltage difference between the output and the reference. This device is available from
Texas Instruments and Motorola amongst others. Figure 11 illustrates its function.
.......J
Rl0
VREF
I".~
VOUT
• TL431
R9
270209-11
Figure 11. Regulator
Figure 10 shows a discrete circuit implementation of a
DC to DC converter. This circuit was designed to regulate a 5V output for 20-60V input voltage. This implementation provides a maximum power of at least 450
mW. The DC to DC converter consists of an oscillator,
a pulse width modulator incorporating an error amplifier and isolating stage, the start up circuitry and the
flyback converter. When T5 is on, the choke stores energy and reverse biases diodes 08,09 and 010. While
T5 is off, the choke voltage is negative, hence diodes
08, 9 and 10 are all forward biased and thus build a
DC voltage on their respective capacitors. Note that
due to the reverse winding technique, the voltage in the
output windings are opposite in polarity to the switch
winding. The 5V output is regulated by comparing it to
a reference voltage, the error in the comparison is then
used to modify the transistor T5 on time in such a way
so as to keep the 5V output constant.
For the regulator diode, the output voltage is given by:
Vout = (1 + RlO IR9) Vref
where Vref is typically 2.5V.
If Rl0 = Rg
then Vout = 5V
The current through the regulating diode will increase
or decrease with a respective change in the output voltage. This change in current is coupled to the output of
the oscillator through the opto-isolator. The opto-isolator used is a Hewlett Packard 6N139, which has Darlington transistor stage providing high current gain that
results in a lower power dissipation in the opto-isolator.
The current through the isolator differentiates the output of the oscillator through capacitor C3. This differentiated signal is then squared off to define the switching transistor T5 on period. T5 is an IRFDIIO MOSFET and is available from International Rectifier. The
isolator current and hence the output voltage control
the amount of differentiation or the transistor T5 on
period as illustrated in Figure 12. Thus regulation is
achieved, as the on period is reduced with increasing
output voltage and vice versa.
The diode bridge 01-04 ensures a certain polarity of
the DC voltage for the converter, this is necessary in
case the network uses polarity reversal for signaling.
The decoupling capacitor CI serves a secondary function of bypassing any induced surge current. One half
of the Schmitt NAND gate CD4093 is used to form a
25 KHz oscillator.
At the output, the opto-isolator in conjunction with the
regulating diode TL431 is used to generate an error
OSCILLATOR OUTPUT
-fU --- ~ --- JTL..S--o
b
Figure 12. Pulse Width Modulation
5-87
c
TO T5
270209-12
inter
AP-282
The resistor R6 and transistor T4 provide current overload protection. Transistor T4 will conduct when the
voltage across R6 exceed 0.6V or conversely, the current through it is greater than ISO mAo With T4 conducting, the drive to the MOSFET is nulled by the
associated NAND gate.
At full load, the incomplete energy transfer mode exhibits a lower peak switching transistor current, while
the complete mode at lower power assures a smaller
core. The inductance required to achieve this is 6.S mH
for the switch winding. The core used was an
RM6CA400-3B7. The number of turns required to
achieve this inductance is 130 and for a 20-60V line
voltage, 50:turns are required for a + SV output, hence
use SO turns for the- 5V too. The self bias winding uses
70 turns. The transformer was wound with 130 turns of
34AWG, followed by 50 bifilar turns of 32AWG and
finished off with 70 turns of 32AWG. The dot scheme
in Figure 10 should be adhered to. The bobbin is then
immersed in varnish such as the Dolph's BC356 to dispel any moisture and to provide a protective coating.
Alternatively, a commercially available DC to DC converter transformer such as the 326-0S33 can be purchased from AlE Magnetics.
The transformer choke is a three winding transformer
consisting of the switching winding, the output winding, which is split for the + 5V and - SV and the selfbias winding. The transformer is designed for complete
energy transfer under no load conditions and incomplete energy transfer under full load conditions. Figure
13 shows the wave forms of the two modes.
At start up, the converter is powered by the linear regulator DS, Rl and TI, which sets the power supply at
S.3V. After start up the self bias winding forces the
voltage on C4 to be between 7 and IS volts, which will
back bias diode D6, thus turning off the linear regulator. Under this condition the power supply provides a
self bias voltage to keep it running, while little power is
The two transistors T2 and T3 provide a low source
impedance driving stage for the switching transistor.
The fast current sinking and sourcing will ensure fast
switching of transistor TS.
The input capacitance of the MOSFET IRFDIIO is a
maximum of 200 pF. Without the buffer stage the
MOSFET will stay in the linear region longer before
saturating, thus resulting in a slower switching speed.
The slow switching in turn will result in a lower overall
efficiency for the converter.
T5 DRAIN VOLTAGE
Lf1-,
T5 DRAIN-SOURCE
A
_
CURRENT - - - / l...-.-../"
~
(b)
(0)
Figure 13..(a) Current Voltage Waveforms for Complete Energy Transfer
(b) Waveforms for Incomplete Energy Transfer
5-88
270209-14
inter
AP-282
GATE VOLTAGE
DRAIN VOLTAGE
5V SECONDARY
CURRENT
l00MAIDV
270209-15
GATE VOLTAGE
DRAIN VOLTAGE
5VPRlMARY
CURRENT
50 MAIOV
270209-16
Figure 14. Converter Oscillograms
dissipated in the start up regulator. Transistor Tl is selected so that the base-collector can sustain the high
voltage stress when it is off. The - 5V supply will only
be regulated if the load on that winding is the same as
that on the + 5V winding. If this is not possible, it may
be necessary to use a linear post regulator to obtain a
regulated - 5V supply.
placed as close to the gate lead as possible. These precautions will avoid undesired oscillations in the MOSFET. The output stage uses Schottky diode and low
ESR capacitors to reduce power dissipation. In the
event of any undesired EMI radiation the transformer
can be placed in an electromagnetic container and the
converter can be enclosed in a copper container.
Figure 14 shows the volt-current oscillograms for a 30V
line voltage and 400 m W output power. This shows the
flyback converter working in the incomplete energy
transfer mode. The results obtained in the lab gave an
overall efficiency of better than 67% and a power supply ripple of less than 25 mV. The no load power consumption was less than 50 mW. Regulation of the output voltage was better than 150 mY.
lif
/
The design was wire wrapped to illustrate the concept
of power extraction and can of course, be optimized for
better performance. Special care should be paid to the
layout; Figure 15 shows good layout principles. Use
star ground connections to avoid current loops in the
ground.
MAGNETIC FIELDS
DUE TO FORWARD
AND RETURN
CURRENTS CANCEL
All lead lengths goirig to the switching MOSFET
should be minimized and in particular the gate lead.
The resistor in series with the MOSFET should be
270209-17
Figure 15. Good Layout Principles
5-89
inter
Ap·282
POWER FAILURE CONSIDERATIONS
ap-
Without power the line interface pins of the 29(:53
pear as diode drops across the line. This means that the '
transmitter of the Network Terminator and, the powered on terminals in a multidrop configuration will be
terminated by a diode instead of the usual SOO. In the
event of a failure, it therefore becomes necessary to iSolate the offending terminal from the line. This can be
done by providing a switch in the transmit paj:h that is
nonna1ly closed and opens when no power is applied.
LX+
When there is power, the two MOSFETS will be on
appear l1li a small on resistance, which has to be
included in the line transformer design analysis. When
thete,js, ,n6 power, the MOSFETS appear as back to
back diodes, thuntopping any AC flow. The VN0300
MOSFE'}'S 'maillitactured by Siliconix may be used,
when on, they present,a 1.20 resistance each. Note that
in order to ensure that the MOSFETS conduct it is
necessary to h&ve a 10V supply in the system. If this is
not possible the MOSFETS can be replaced by a Reed
relay which presents a lower on resistance and capacitance but ,has th~' disadvantage of consuming more
power. A low power relay could not be located hence a
vendor was requested to customize one. Figure 17
shows the isolatiOn' technique using the Wabash
1992-2-1 25 mW relay which will operate at 3.8V and
release at 0.5V.
and
1------,.
TRANSMIT
29C53
LX+
1------,.
I
I
1-----"
LXLR+ I--'W\r---,.
29053
"3
'
I
II :
LR- I--'W~=~
LX270209-18
C
I
LR+
Figure 16. Isolation of Equipment In '
Case of Power Failwe
c
In the receive path, it is only necessary, to increase the
impedance seen by the line. One way to implement this
principle is to use a MOSFET bilateral switch in the
transmit path and to place series resistors in the receive
path, such that the impedance seen by the line is greater
than 25000.' Figure 16, illustrates this approach. A
noteworthy point is that the series resistors in the receive path not only provide terminal isolation in case of
failure but also protect the terminal from current
surges.
LR-
1-----"
270209-19
Figure 17. Power FaIlure Isolation
5-90
inter
Ap·282
The protection circuits and the transformer, however,
can only be provided in discrete form at the present
time. The concepts presented in the protection section
emphasized low capacitance and maximum protection.
The section took an overkill approach and as such a
subset of the discussed ideas should suffice most applications. The transformer designed pointed out the relevant parameters to consider and can be used as it is or
modified to the particular application. Of course the
ISDN transformer is also commercially available.
CONCLUSION
Specific implementations have been provided for the
general aspects of line interfacing at both the line card
and the terminal end. These solutions can be taken as
they are and placed in the particular application or
used to aid a system design.
The fixed voltage or constant current feed are both simpler and more economical to realize in discrete form;
however the constant current variable voltage scheme
may be more suitable in an integrated form. The power
converter discussed was based on a low cost simple implementation and it is certainly possible to optimize it
to obtain conversion efficiencies in the 75% range. As
an alternative to discrete implementations, a low power
switch mode power supply is commercially available
from Fairchild and Motorola, to name two.
REFERENCES
1. Protecting against surge voltages in short and long
branch circuits. By Shanawaz M. Khan, Communications Systems Equipment Design, December 1984
2. Transformers for electronic circuits. By Nathan R.
Grossner, McGraw Hill
3. Design of solid state power supplies. By Eugene R.
Hnatek, Von Nostrand Reinhold Company
5-91
inter
APPLICATION
BRIEF
AP-4do
October 1988
ISDN Applications with
29C53 and 80188
HERBERT WEBER
TELECOM OPERATIONS
Order Number: 270247-003
5-92
inter
AB-400
TERMINAL ADAPTOR (TA)
A terminal adaptor, or "TA", is the link between existing non-ISDN equipment like terminals, facsimile,
printers and the ISDN network. The (unction of this
application is to effectively replace equipment such as a
modem. Usually provided as a separate box, it processes RS232 or X.21 data and places it on the 4 wire'S'
loop. No change at the terminal is required to make it
ISDN compatible.
• Upper portion of link access procedure (CCITT
1.440) handling:
- Multiple logic channels
- Sequence control
- Error correction (retransmission)
- Flow control
The design is based on a 29C53 transceiver for the
ISDN connection and an 80188 microprocessor in combination with an 82530 communications controller for
the data connection. Benefits of the application are:
• Data rates up to 19.2 Kb!s using an RS232 interface
or up to 48 Kb!s using an X.21 interface.
• Compact design and low cost.
• Virtually error free transmission.
EPLD
• Interface conversion,' serial to!from SLD
• B-channel assignment
29C53
• Physical level interface (CCITT 1.430)
• Lower portion of the link access procedure:
- Zero insertion!deletion
- CRC generation and checking
- Flag appending and detection
• D-channel message buffering
Link Setup
The user sets up a call in the same manner as a Hayes·
modem user does, i.e. a command is transferred to the
adaptor via the RS232 interface. The command takes
the form of an ASCII string in which the first 2 characters are "AT".
The 80188 passes the information for the D-channel
messages via the parallel bus into the FIFO's of the
29C53.
C
The 80188 accepts the command and begins the call
setup procedure by communicating the call's destination to the NT (or CO). This is achieved by passing call
setup messages to a link level protocol, which is passed
to the NT over the physical level (S bus). The partitioning of the tasks is as follows:
The NT grants a B-channel (if available) to the TA and
the channel is now ready for data transfer.
Data Transfer
An indication is given to the user's terminal via the
RS232 or X.21 port that communication may commence. Any subsequent data, from the terminal, is
treated as follows:
82530
Full duplex, dual channel serial communications controller capable of working in asynchronous, bit or byte
synchronous modes. The 82530 receives commands
from the terminal's RS232 or X.21 interface and passes
them on to the 80188.
Data from the terminal passes via the 82530 to RAM
via one of the 80188 DMA channels.
The 80188 fetches the data from RAM, depacketizes
and packetizes it before sending it back to the 82530
where a protective HDLC protocol is added.
80188
After having received the dialing information from the
keyboard, the 80188 sets up the call via the 29C53 Dchannel by sending the appropriate CCITT message up
the link.
• Call setup message generation (CCITT 1.451).
From the 82530 the data reaches the EPLD to be inserted into the B1 or B2 channel on the SLD bus. The
29C53 sends it out over the "S" interface.
• Hayes is a registered trademark of Hayes Microcomputer
Products, Inc.
5-93
inter
AB-400
SLD
P3/4
RS 232 C
300 - 19 200 blt/s
oR
X.21
600 - 48 000 blt/s
ill-
:Jl.l
CH B
~
HDLC
29C53
CS
AID
it
I
.. ~
CHANNEL
SELECT
c::::
c:::
4W 'S' Interface
INn
PCSI
....
INTO
82530
SEL
D/C
...
.
"
~
~
,
4
~
PCS5
...
...
IAPX188
AID
UCS
LCS
. ,.
'II
,
AID
AID
EPROM
RAM
270247-1
Figure 1. Terminal Adaptor
5-94
inter
AB·400
ISDN PHONE WITH BUILT IN TERMINAL ADAPTOR (TA)
Figure 2 shows the concept of an ISDN phone with
hookup to standard sync/async terminals. No change
at the terminal is required to make it ISDN compatible.
The design is based on a 29C53 transceiver for the
ISDN connection, a 29C48 combo for the voice connection and an 80188 microprocessor in combination with
an 82530 communications controller for the data connection. Benefits of the application are:
• Data rates up to 19.2 kb/s using an RS232 interface
o~ up to 48 j<.b/susing an X.21 interface.
• Compact design and low cost.
• Virtually error free transmission.
Link Setup
Applies both for speech and dat~ links. The 80188 accepts the command and begins the call setup procedure
by communicating the call's destination: to the NT (or
CO):This-is achieved by passing call setup messages to
a link level protocol, which is passed to the NT over'the
physical level (S-bus). The partitioning of the tasks is as
follows:
- Error correction (retransmission)
- Flow control
EPLD
• Interface conversion, serial to/from SLD
• B-channel assignment
29C53
• Physical level interface (CCITT 1.430)
• Lower portion of the link access procedure:
- Zero insertionldeletion
- CRC generation and checking
- Flag appending and detection
• D-channel message buffering
The 80188 passes the information for the D-channel
messages via the parallel bus into the FIFO's of the
29C53.
The NT grants a B-channel (if available) to the TA and
,the channel is now ready for data transfer.
8279
The 8279 keyboard and display controller scans the telephone number pad and supports a small telephone display. Calls are initiated either through the terminal
keyboard using an extended Hayes Smart Modem command set or via the telephone number pad.
82530
Full duplex, dual channel serial communications controller capable of working in asynchronous, bit or byte
synchronous modes. The 82530 receives commands
from the terminal's RS232 or X.21 interface and passes
them on to the 80188.
80188
After having received the dialing information from either keyboard, the 80188 sets up the call via the 29C53
D-channel by sending the appropriate message up the
link.
• Call setup message generation (CCITT 1.451)
• Upper portion of link access procedure (CCITT
1.440) handling:
- Multiple logic channels
- Sequence control
Information Transfer
VOICE
The voice transfer is supported by the 29C48 which
transmits the voice on either the BI or B2 channel
(controlled by the EPLD) into the 29C53 and onward
to the S-bus.
DATA
An indication is given to the user's terminal via the
RS232 or X.21 port that communication may commence. Any subsequent data, from the terminal, is
treated as follows:
Data from the terminal passes via the 82530 to RAM
via one of the 80188 DMA channels.
The 80188 fetches the data from RAM, depacketizes
and packetizes it before sending it back to the 82530
where a protective HDLC protocol is added.
From the 82530, the data reaches the EPLD to be inserted into the BI or B2 channel on the SLD bus. The
29C53 sends it out over the "S" interface.
inter
AB-400
,
It'
29C48
.......
~
SLO
SLO
81/82
P3/4
.,Jj
..
4W 'S' Interface
CS
A/O
"
.~
c:::::
Ir:::::
I
29C53
'
EPLO
RS 232 C
300 - 19200, blt/s
OR
X.21
600 - 48 000 blt/s
~
:IJ.L
CHANNEL
SELECT
INn
'PCSl
HOLC
INTO
82530
SEL
O/C
PCSS
....
'"
"I
A ~
..
r
~
A
...r-
.
IAPX188
A/O
UCS
LCS
PCS4
"I
,.
~
"
A/O
A/O
EPROM
RAM
"I
,.
INT3
I
A/O CS INT
OUT
8279
~OISPLAY
RL ~KEY80ARO
270247-2
Figure 2. ISDN Phone With Built In Terminal Adaptor
5-96
inter
AB-400
PERSONAL COMPUTER INTERFACE
Like the terminal adaptor, the ISDN PC adaptor
provides a link to the ISDN network. The ISDN CoProcessor shown in Figure 3 implements the hardware
functions required to support the CCITI I-series "S"
interface.
29C48
Voice conversion and interface to the four wire handset
is performed by this software programmable integrated
Codec/filter combo. Designed for ISDN terminal applications it offers programmable gain in transmit and
receive direction for user loudness control and adaptation to local network requirements as well as sidetone
insertion and tone injection for locally produced feedback signals.
The ISDN Co-Processor is using the 80188 microprocessor in combination with an 82530 serial communications controller for data processing, dual port RAM as
interface and buffer to the host bus, the 29C48 Codecl
filter for voice support and the 29C53 transceiver for
the ISDN connection.
The 29C48 can access either B1 or B2 channel by setting the B Sel pin accordingly.
The ISP188 ISDN Software Package is optimized for
this hardware configuration.
29C53
82530
"s" bus transceiver and D channel controller in a single
chip. The 29C53 provides the physica1level interface to
the "s" bus in accordance to CCITI 1.430 and the
lower portion of the link access protocol. Activation,
deactivation, zero insertiOn/deletion, CRC generation
and checking and flag appending and detection are performed by the 29C53, the higher level portions of
LABD are executed on the 80188 and passed on to the
29C53 via the parallel bus into the FIFO's.
Full duplex, dual channel serial communications controller. One of the two channels is attached to either of
the B channels and operates at 64 kb/s. The second
channel is available to external datacom equipment via
an optional serial port, or for connection to the second
B channel.
B channel access is via the SLD serial port. Voice signals are directly passed on to the 29C48. Data is
extracted and injected by the EPLD (Erasable, Programmable Logic Device) which performs the B channel assignment and the interface conversion to the
82530.
Co-Processor
The PC adaptor is an intelligent communications subsystem designed to function as a slave processor board
in the PC. This relieves the host processor of much of
the communications function.
c::
4W 'S. Injrlace :
RAil
DUAL PORT RAIl
80188
ROil
270247-4
Figure 3. Personal Computer Interface
5-97
AB-400
FULL FEATURE ISDN LINE CARD
:
:
PCMl
PCM2
LINE CARD
CONTROLLER
CS INT
:
:
4W
's'
I
Interface
HOLC
TOM BACKPLANE
+-+ ;~~~RL~~~
SLO
29C53
I
PACKET NETWORK
~~~~;;~~t~~
PCS4
UCS
LCS
INT3
PCSO.1
PSC2.3
270247-3
Figure 4. Full Feature ISDN Line Card
The addition of ISDN line cards to a PABX provides
the user with access to the ISDN network. While the
analog line card provides access for standard telephone
as well as for modems, ISDN terminal adaptors, terminals and phones are connected to the ISDN line card
via a 4 wire'S' loop. The described application provides
all functions to separate voice and switched data (Bchannels) from signaling and packetized data (D-channe1).
4. The 80188 determines whether the data is for signaling (S-packet) or is a message to be sent out over the
packet (P-packet) switched network.
Signaling information can be processed locally or
sent via the linecard controller.
If the data is of "P" type, meant for the packet
switched network, it is DMA'd into the 82530 serial
communications controller which performs the nee.essary HDLC transmission, again without any CPU
involvement.
The 29C53 and 80188 together handle the processing of
D-channel protocols and messages as follows:
5. The 80188 software is responsible for sending out
acknowledgements for received messages from the
29C53's D-channe1 and can thus support large window sizes.
1. The 29C53 executes all bit level HDLC processing,
puts the "raw" messages into its FIFO and raises the
interrupt signal.
2. A special status register in the 29C53s allows the
80188, through a single status read operation, to determine which of the 29C53s is requiring interrupt
servicing, i.e. has D-channel messages(s) in its FIFO.
B-channel information is directly passed from the "S"
loop over the 29C53 and line card controller to the
switch backplane.
3. The 80188 accesses the FIFO concerned and the
data is transferred to RAM.
For transmission in the opposite direction, the procedure is equivalent to the one described above.
5-98
intJ
AB-400
OTHER AVAILABLE TELECOM LITERATURE
Order Number
Title
29C53 Reference Manual
270151-001
29C53 Line Card Evaluation Kit
(LEK) Manual
29C53 Terminal Evaluation Kit
(TEK) Manual
ISP188
ISDN Software Package
for the 80188
IDK29C53
ISDN Development Kit for 29C53
PC53 ISDN Board
5-99
290149-001
PCM Codec fFilter
andCombo
6
I-n+_f
•• ~
2910A
PCM CODEC - p.LA W
8-BIT COMPANDED AID AND 01 A CONVERTER
Per Channel, Single Chip Codec
• CCITT
G711 and G712 Compatible, ATT
• T1 Compatible
with 8th Bit Signaling
Microcomputer Interface with On-Chip
• Timeslot Computation
Direct Mode Interface When
• Simple
Fixed Tlmeslots are Used
• ±S% Power Supplies: + 12V, +SV, -SV
78dB Dynamic Range, with Resolution
• Equivalent
to 12-Blt Linear Conversion
•
•
•
Around Zero
Precision On-Chip Voltage Reference
Low Power Consumption 230 mW Typ.
Standby Power 33mW Typ.
Fabricated with Reliable N-Channel
MOS Process
The Intel 2910A is a fully integrated PCM (Pulse Code Modulation) Codec (Coder-Decoder), fabricated with
N-channel silicon gate technology. The high density of integration allows the sample and hold circuits, the
digital-to-analog converter, the comparator and the successive approximation register to be integrated on the
same chip, along with the logiC necessary to interface a full duplex PCM link and provide in-band signaling.
The primary applications are in telephone systems:
• Transmission
-T1 Carrier
• Switching
• Concentration
-Digital PBX's and Central Office Switching Systems
-Subscriber Carrier IConcentrators
The wide dynamic range of the 2910A (78dB) and the minimal conversion time (80/J-sec minimum) make it an
ideal product for other applications, like:
• Date Acquisition
• Telemetry
• Secure Communications Systems
• Signal Processing Systems
@SIGX_-J_ _ _ _ _ _ _T..;.R;.;AN..:.;SM..;.;.;IT...;S.;;;EC;.;T...;IO;.;N....,A/O
®
o
VFx
r......JL------l-~~_
---ir---t
AUTO
SA':PLE
CD CAP 1x
0 CAP2 x - - - t - - - - t
1--_ _ _-;
HOLD
SUCCESSIVE
TS x
Ox
@
@
AfPROXIMATION
CLKx@
REGISTER
FSx @
006785-1
Figure 2. Pin
Configuration
r-'-if-+-Oc @
I---t-- Cl"c
®
L.....---.Jr-T- PON ®
®
1---t--ClKR ®
I--+__ FSR ®
r-L-t-_I-_OR
@
®
VFR
---f.--cC
Holding Capacitor
VFx
Analog Input
VFR
Analog Output
DR. Dc.SIGx
Dlgrtallnput
SIGR. Ox. TSx
Digital Output
ClKc ClKx. ClKR Clock Input
9GR_-+_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
OPINNLMIER
CAP1X CAP2x
GROA
GROO
®
@
~
006785-2
Figure 1. Block Diagram
FSx FSR
Frame Sync Input
AUTO
Auto Zero Output
VBB
Power (-5V)
Vee
Power (+5V)
Voo
Power (+ 12V)
PDN
Power Down
GRDA
Analog Ground
GRDD
Digital Ground
NC
No Connect
Figure 3. Pin Names
6-1
November 1986
Order Number: 006785-002
2910A
Pin Description
Pin ,No.
Symbol
Function
Hold
Connections for the transmit holding capacitor. Refer to .
Applications section.
Description
1
CAP1x
2
CAP2x
3
VFx
Input
Analog input to be encoded into a PCM word. The signal on this
lead is sampled at the same rate as the transmit frame
synchronization pulse FSx, and the sample value is held in the
external capacitor connected to the CAP1 x and CAP2x leads
until the encoding process is completed.
4
AUTO
Output
Most significant bit of the encoded PCM word ( + 5V for negative,
- 5V for positil(e inputs). Refer to tlJe Codec Applications
section.
5
GRDA
Ground
Analog return common to the transmit and receive analog
circuits. Not connected to GRDD internally.
6
SIGR
Output
Signaling output. SIGR is updated with the 8th bit of the receive
PCM word on signaling frames, and is latched between two
signaling frames. TIL interface.
7
VDD
Power
+ 12V±5%; referenced to GRDA.
8
DR
Input
Receive PCM highway (serial bus) interface. The Codec serially
receives a PCM word (8 bits) through this lead at the proper time
defined by FSR, CLKR, Dc, and CLKe.
9
PDN
Output
Active high when Codec is in the power down state. Open drain
output.
10
VFR
Output
Analog output. The voltage present on VFR is the decoded value
of the PCM word received on lead DR. This value is held
constant between two conversions.
11
NC
Recommended practice is to strap these NC's to GRDA.
12
NC
No
Connects
13
GRDD
Ground
Ground return common to the logic power supply, Vee.
14
Dx
Output
Output of the transmit side onto the send PCM highway (serial
bus). The 8-bit PCM word is serially sent out on this pin at the
proper time defined by FSx, CLKx, Dc, and CLKe. TIL threestate output.
15
TSx
Output
Normally high, this signal goes low while the Codec is
transmitting an 8-bit PCM word on the Dx lead. (Timeslot
information used for diagnostic purposes and also to gate the
data on the Dx lead.) Open drain output.
16
Vee
Power
+5V±5%, referenced to GRDD.
17
CLKR
Input
Master receive clock defining the bit rate on the receive PCM
highway. Typically 1.544 Mbps for a T1 carrier system. Maximum
rate 2.1 Mbps. 50% duty cycle. TIL interface.
18
FSR
Input
Frame synchronization pulse for the receive PCM highway.
Resets the on-chip timeslot counter for the receive side.
Maximum repetition rate 12 KHz. Also used to differentiate
between non-signaling frames and signaling frames on the
receive side. TTL interface.
6-2
inter
2910A
Pin Description (Continued)
Pin No.
Symbol
Function
19
CLKx
Input
Master transmit clock defining the bit rate on the transmit PCM
highway. Typically 1.544 Mbps for a T1 carrier system. Maximum
rate 2.1 Mbps. 50% duty cycle. TIL interface.
20
FSx
Input
Frame synchronization pulse for the transmit PCM highway.
Resets the on-chip timeslot counter for the transmit side.
Maximum repetition rate 12 KHz. Also used to differentiate
between non-signaling frames and signaling frames on the
transmit side. TIL interface.
21
SIGx
Input
Signaling input. This digital input is transmitted as the 8th bit of
the PCM word on the Ox lead, on Signaling frames. TIL
interface.
22
Vss
Power
- 5V ± 5%, referenced to GRDA.
23
De
Input
Data input to program the Codec for the chosen mode of
operation. Becomes an active low chip select when CLKe is tied
to Vee. TTL interface.
24
CLKe
Input
Clock input to clock in the data on the De lead when the timeslot
assignment feature is used; tied to Vee to disable this feature.
TIL interface.
Description
previously described and substitute the signal present on lead SIGx for the least significalJt bit of the
encoded PCM word. Similarly, on a receive signaling
frame, the Codec will decode the 7 most significant
bits according to the CCITI G733 recommendation
and will output the least significant bit value on the
SIGR lead until the next signaling frame. Signaling
frames on the send and receive sides are independent of each other, and are selected by a doublewidth frame sync pulse on the appropriate channel.
FUNCTIONAL DESCRIPTION
The 2910A PCM Codec provides the analog-to-digital and the digital-to-analog conversions necessary
to interface a full duplex (4 wires) voice telephone
circuit with the PCM highways of a time division mUltiplexed (TOM) system.
In a typical telephone system the Codec is used between the PCM highways and the channel filters.
The Codec provides two major functions:
• Encoding and decoding of analog signals (voice
and call progress tones)
r----------------------
• Encoding and decoding of the signaling and supervision information
I
PA&X' C 0 SWITCHING SYSTEM I CHANNel BANK
I
I
I
I .....-.1...--,
I SUPERVISION
I PROTECTION
I
On a non-signaling frame, the Codec encodes the
incoming analog signal at. the frame rate (FSx) into
an 8-bit PCM word which is sent out on the Ox lead
at the proper time. Similarly, the Codec fetches an 8bit PCM word from the receive highway (DR lead)
and decodes an analog value which will remain constant on lead VFR until the next receive frame.
Transmit and receive frames are independent. They
can be asynchronous .(transmission) or synchronous
(switching) with each other.
BATTERY
FEED
RINGING
L _____
~
__ --. _________
~M~I~~YS
006785-4
For channel associated Signaling, the Codec transmit side will encode the incoming analog signal as
Figure 4. Typical Line Termination
6-3
inter
2910A
";'" ,
The 2910A Codec is intended to be used on line and,
trunk terminations. The call progress tones (dial
tone, busy tone, ring-back tone, re-order tone), and
the prerecorded, announcements, can be sent
through the voice-path; digital signaling (off hook
and disconnect supervision, rotary dial pulses, ring
control) is sent through the signaling path.
4
5
6
7
8
Tlmeslot
0
0
0
0
0
0
0
0
0
0
0
1
1
2
•
•
•
•
•
1
1
1
•
1
1
1
64
The Codec will retain the control word (or words)
until a new word is loaded in or until power is lost.
This feature permits dynamic allocation of timeslots
for switching applications.
Codec Control
The operation of the 2910A is defined by serially
loading an a-bit word through the Dc lead (data) and
the CLKc lead (clock). The loading is asynchronous
with the other operations of the Codec, and takes
place whenever transitions occur on the CLKc lead.
The Dc input is loaded in during the trailing edge of
the CLKc input.
I--
3
•
•
COOEC OPERATION
BI14
Standby
Bit
In the power-down mode, most functions of the Codec are directly disabled to reduce power dissipation
to a minimum.
BIT 3
Mode
'X&R
X
R
'0
1
0
1
0
0
1
1
Circuitry is provided within the Codec to internally
define the transmit and receive timeslots. In small
systems this may eliminate the need for any external
timeslot exchange; in large systems it provides one
level of concentration. This feature can be bypassed
and discrete timeslots sent to each Codec within a
system.
I BI~~Ec:T21
BIt2
Bit 1
~~N xB~.
MODE --l------nME SLOT'
BIT 7
BIT
Microcomputer Control Mode
In the microcomputer mode, each Codec performs
its own timeslot computation independently for the
tral:lsmit and receive channels by counting clock
pulses (CLKx and CLKR). All Codecs tied to the
same data bus receive identical framing pulses (FSx
and FSR). The framing pulses reset the on-Chip
timeslot counters every frame; hence the timeslot
counters of all devices are synchronized. Each Codec is programmed via CLKc and Dc for the desired
transmit and receive timeslots according to the description in the Codec Control Section. All Codecs
tied to the same DR bus will, in general, have different receive timeslots, although that is not a device
requirement. There may be separate busses for
transmit and receive or all Codecs may transmit and
receive over the same bus, in which case the transmit and receive channels must be synchronous
(CLKx = CLKR). There are no other restrictions on
timeslot assignments; a device may have the same
transmit and receive timeslot even if a Single bus is
used.
i
"X~
006785-3
The control word contains two fields:
Bit 1 and Bit 2 define whether the subsequent 6 bits
apply to both the transmit and receive side (00), the
transmit side only (01), the receive side only (10), or
whether the Codec should go into the standby, powerdown mode (11). In the last case (11), the following 6 bits are irrelevant.
There are several requirements for using the
CLKc-Dc interface in the microcomputer mode.
1) A complete timeslot assignment, consisting of
eight negative transitions of CLKc must be made
in less than one frame period. The assignment
The last 6 bits of the control word define the timeslot
assignment, from 000000 (timeslot 1) to 111111
(timeslot 64). Bit 3 is the most significant bit and bit a
the least significant bit and last into the Codec.
6-4
2910A
can overlap a framing pulse so long as all 8 control bits are clocked in within a total span of
125 /Ls (for an 8 KHz frame rate). GLKe must be
left at a TIL low level when not assigning a timeslot.
2) A dead period of two frames must always be observed between successive timeslot assignments. The two frame delay is measured from the
rising edge of the first GLKe transition of the previous times lot assigned.
3) When the device is in the power-down state
(Standby), the following three-step sequence
must be followed to power-up the codec to avoid
contention on the transmit PGM highway.
a) Assign a dummy transmit timeslot. The dummy
should be at least two timeslots greater than
the maximum valid system timeslot (usually 24
or 32). For example, in a 24 timeslot system,
the dummy could be any timeslot between 26
and 64. This will power-up the transmit side,
but prevent any spurious Ox or TSx outputs.
b) Two frames later, assign the desired transmit
timeslot.
c) Two frames later assign the desired receive
timeslot.
4) Initialization sequence: The device contains an
on-chip power-on clear function which guarantees that with proper sequencing of the supplies
(Vee or VOO on last), the device will initialize with
no timeslot assigned to either the transmit or receive channel. After a supply failure or whenever
the supplies are applied, it is recommended that
either power down assignment be made first, or
the first timeslot assignment be a transmit timeslot or a transmit/receive timeslot. The consequence of making a receive timeslot assignment
first, after supply application, is that the transmit
channel will assume timeslot 1, potentially producing bus contention.
5) Transmit only/receive only operation is permitted
provided that a power down assignment is made
first. Otherwise, special circuits which use only
one channel should be physically disconnected
from the unused bus; this allows a timeslot to be
made to an unused channel without consequence.
6) Both frame synchronizing pulses (FSx FSR) must
be active at all times after power on 'clear (after
power supplies are turned on). This requirement
must be met during powerdown and receive only
or transmit only operation, as well as during normal transmit and receive operation.
Example of Microcomputer Control Mode:
The two words 01000001 and 10000010 have been
loaded into the Godec. The transmit side is now programmed for timeslot 2 and the receive side for
timeslot 3. The Godec will output a PGM word on the
transmit PGM highway (bus) during the timeslot 2 of
the transmit frame, and will fetch a PGM word from
the receive PGM highway during times lot 3.
rSEPARATEO BY AT LEAST TWO FRAMESl
~~
~~c
:
I
~~:
Dc
I
I
I
I
I
I
I
I
I
I
I
I
I
I.
I
01000001
"
'.
10000010
Figure 5. Microcomputer Mode Programming Example
_,
006785-5
inter
2910A
XMT TIME SLar 1
FSx
XMT TIME SLOT 3
IMY TIME SLOT 2
--I
IN
eLK, IN
Rev TIME $LOl' 3
RCV TIME SLOT \
Fs., IN
0"
IN
PCM WORD CLOCKED IN
006785-8
Figure 6. Microcomputer Mode PCM Highway Example
In this example the Codec interface to the PCM
highway then functions as shown above. (FSx and
FSR may be asynchronous.)
fied limits. This assumes that CLKc is tied to Vee
and that all clocks are available at the time the supplies have settled.
Direct Control Mode
General Control Requirements
The direct mode of operation will be selected when
the CLKc pin is strapped to the + 5 volt supply
(Vee). In this mode, the Dc pin is an active low chip
select. In other words, when Dc is low, the device
transmits and receives in the timeslots which follow
the appropriate framing pulses. With Dc high the device is in the power down state. Even though CLKc
characteristics are simpler for the 2910A it will oper·
ate properly when plugged into a 2910 board.
All bit and frame clocks should be applied whenever
the device is active. In particular, an unused channel
cannot be deactivated by removal of its associated
frame or bit clock while the other channel of the
same device remains active.
A single channel cannot be deactivated except by
physical disconnection of the data lead (Dx or DR)
from the system data bus. A device (both transmit
and receive channels) may be deactivated in either
control mode by powering down the device. Both
channels are always powered down together.
Deactivation of a channel by removal of the appro·
priate framing pulse (FSx or FSR) is not permitted.
Specifically, framing pulses must be applied for a
minimum of two frames after a change in state of Dc
in order for the Dc change to be internally sensed. In
particular, when entering standby in the direct mode,
framing pulses must be applied as usual for two
frames after Dc is brought high.
Encoding
The VF signal to be encoded is input on the VFx
lead. An internal switch samples the signal and the
hold function is performed by the external capacitor
connected to the CAP1 X and CAP2x leads. The
sampling and conversion is synchronized with the
The Godec will enter the direct mode within three
frame times (375 ,""s) as measured from the time the
device power supplies settle to within the speci·
""I
, - - - - '. .
XcLK.-------o--l!
....
N.J___~(··_C_~_~_L~S~~M-I~-~--D~-----~==~~~~~L-------_ ____
~~
••••••••••• u u •• u
••
;;~:~:.=3
u
•• m
••••
;.~
006785-7
Figure 7. Transmit Encoding
6-6
intJ
2910A
• A frame synchronization pulse which is a full
clock period in duration (CLKx period for FSx,
CLKR period for FSR) deSignates a non-signaling
frame.
• A frame synchronization pulse which is two full
clock periods in duration (two CLKx periods for
FSx two CLKR periods for FSR) deSignates a signaling frame.
transmit timeslot. The PCM word is then output on
the Ox lead at the proper timeslot occurrence of the
following frame. The AID converter saturates at approximately ± 2.2 volts RMS (± 3.1 volts peak).
Decoding
The PCM word is fetched by the DR lead from the
PCM highway at the proper timeslot occurrence. The
decoded value is held on an internal sample and
hold capacitor. The buffered non-return to zero output signal on the VFR lead has a dynamic range of
approximately ± 2.2 volts RMS (± 3.1 volts peak).
On the encoding side, when the FSx pulse is widened, the 8th bit of the PCM word will be replaced by
the value on the SIGx input at the time when the 8th
bit is output on the Ox lead.
Signaling
On the decoding side, when the FSR pulse is widened, the 8th bit of the PCM word is detected and
transmitted on the SIGR lead. That output is latched
until the next receiving signaling frame.
The duration of the FSx and FSR pulses defines
whether a frame is an information frame or a signaling frame:
.
I-
TS..
The remaining 7 bits are decoded according to the
value given in the CCITT G733 recommendation.
The SIGR lead is reset to a TTL low level whenever
the Codec is in the power-down state.
"liT....
"'
.92 iTS.. I-
I
-,'
"I
ClKx~,~,.rt.rLJn.I·"1..fl..I1.J1..
192 I
_IT SIGNAL PRAM.
In
FSx J
, "~7
___.I-_ _ _ _ _ _
_
.~.
~ ---------,-----------------;~;:ummm-:7~
S/Gx :.:-::::: ::::: : : : : : : ::: :::::
L::: :: ::::: :: ::::: :x::::=:=-=~::t=======:O==-=
006785-8
Figure 8. Transmit 8th Bit Signaling
I"
TSI,
".'
TSn"
"'
d- TS"
..
1'
T....
"I
CLKR~'.f1.Il...ILJ"LJJ1Jl..I1U'l..fU1..fl..JlS
192
REC SIGNAL FRAME
.JI
_ _ _ _ _ _ _ _ __
~
0,.
SIG R
.~,
.
==========:=========.= , ; :
SIGR
:::~::::::::::::::::::::::::::::::::::::!:~::::~::::~::::::::::::::~:::
Figure 9. Receive 8th Bit Signaling
6-7
'~
XV
008785-9
2910A
T1 Framing
Precision Voltage Referer:'lce for the
01A Conyerter
..
The Codec will accept the standard 03/04 framing
format of 193 clock pulses per frame (equivalent to
CLKx, CLKR of 1.544 Mb/s). However, the 193rd bit
may be blanked (equivalent to CLKx, CLKR of
1.536 Mb/s) if desired.
The voltage reference is generated on the chip and
is calibrated during the manufacturing process. The
technique uses the difference in sub-surface charge
density between two suitably implanted MOS devices to derive a temperature stable and bias stable
reference voltage..
.
.
Standby Mode-Power Down
A gain setting op amp, programmed during m~nufac
turing, "trims" the reference voltage source to the
final precision voltage reference value provided to
the 01 A converter. The precision voltage reference
determines the initial gain and dynamic range characteristics described in the A.C. Transmission Specification section.
To minimize power consumption and heat dissipation a standby mode is provided where all Codec
functions are disabled except for De and CLKe
leads. These allow the Codec to be reactivated. In
the microcomputer mode the Codec is placed into
standby by loading a control word (De) with a "1" in
bits 1 and 2 locations. In the direct mode when De is
brought high, the all "1's" control word is internally
transferred to the control register, invoking the
standby condition.
,...·Law Conversion
~-Iaw represents a particular implementation of a
piece-wise linear approximation to a logarithmic
compression curve which is:
While in the standby mode, the Ox output is actively
held in a high impedance state to guarantee that the
PCM bus wi" not be driven. The SIGR output is held
low to provide a known condition and remains this
way upon activation until it is changed by signaling.
F(x) = Sgn(x) In(1 + ~Ixl) 0
In(1 +~)
The power consumption in the standby mode is typica"y·33 m'!".
:s:
Ixl
:s:
1
where x = input signal
Sgn(x) = sign of input signal
Power·On Clear
~
Whether the device is used in the direct or microcomputer mode, an internal reset (power-on clear) is
generated, forcing the device into the power down
state, when power is supplied by any of the following
methods. (1) Device power supplies are turned on in
a system power-up situation where either Vee or
Voo is applied last. (2) A large supply transient causes either of the two positive supplies to drop to less
than approximately 2 volts. (3) A board containing
Codecs is plugged into a "hot" system where Vee or
Voo is the last contact made. It may be necessary to
trim back the edge connector pins or fingers on Vee
or Voo relative to the other supply to guarantee that
the power-on clear will operate properly when a
board is plugged into a "hot" system. Furthermore,
the Codec will inhibit activity on TSx and Ox during
the application of power supplies.
= 255 (defined by AT & T)
The 291 OA ~ = 255 law Codec uses a 15 segment
approximation to the logarithmic law. Each segment
consists of 16 steps. In adjacent segments the step
sizes are in a ratio of two to one. Within each segment the step size is constant except for the first
step of the first segment of the encoder, as indicated
in the attached table. The output levels are midway
between the corresponding decision levels. The out~
put levels Yn are related to the input levels xn by the
expression:
Yn =
xn +xn+1 for 1 :s:
2
n
:s:
127
Yo=xo=Oforn=O
These relationships are implicit in the following table.
The device is also tolerant of transients in the negative supply (Vss) so long as Vss remains more negative than -3.5 volts. Vss transients which exceed
this level should be detected and followed by a system reinitialization.
6-8
inter
2910A
Theoretical WLaw-Positive Input Values (for Negative Input Values, Invert Bit 1)
1
2
3
4
5
Segment
Number
No. of Steps
x Step Size
Value.t
Segment
End
Points
Decision
Value
Numbern
Declalon
Valuexn(1)
8159(5)
(128)
(8159)
127
7903
I
I
I
I
I
I
I
I
6
7
8
PCMWord(3)
Normalized
Value
at Decoder
Output Yn(4)
Decoder
Output
Value
Number
8031
127
MSB Bit Number LSB
1 2 3 4 5 6 7 8
1 a a a a a a a
8
16 x 256
4063
7
16 x 128
2015
6
16 x64
113
4319
112
4063
I
I
I
I
I
I
I
I
I
(see Note 2)
I
I
1 a a a 1 1 1 1
97
2143
96
2015
I
I
I
I
I
I
I
I
1055
I
I
80
991
5
I
I
I
I
16x32
479
4
16x 16
I
I
I
I
65
511
64
479
I
I
I
I
I
I
I
I
49
239
48
223
I
I
I
I
I
I
I
I
3
16 x 8
33
103
32
95
I
I
I
I
I
I
I
I
2
16 x 4
17
35
16
31
15x2
I
I
I
I
I
I
I
I
2
3
1
1
a
a
-
1023
80
-
I
I
I
I
I
I
495
I
I
I
I
I
I
64
-
I
I
I
I
I
I
231
I
I
I
I
I
I
-
99
32
-
I
I
I
I
I
I
33
I
I
I
I
I
I
16
I-
I
I
I
I
I
I
2
I
I
I
I
I
I
1
a
a
I
I
I
(see Note 2)
I
I
I
(see Note 2)
I
I
I
(see Note 2)
I
I
I
(see Note 2)
I
I
1 1 1 1 1 1 1 0
1
-I-
I
I
I
I
I
I
I
I
I
I
I
I
I
1 1 1 a 1 1 1 1
31
112
I
I
I
I
I
I
96
(see Note 2)
1 1 a 1 1 1 1 1
95
4191
I
I
I
I
I
I
I
I
1 1 a a 1 1 1 1
223
I
I
I
I
I
I
2079
I
1 a 1 1 1 1 1 1
I
I
I
I
I
I
-
(see Note 2)
1 a 1 a 1 1 1 1
991
~
I
(see Note 2)
1 a a 1 1 1 1 1
81
-
I
I
I
I
I
I
48
I
I
I
I
I
I
1 1 1 1 1 1 1 1
1 xl
NOTES:
1. 8159 normalized value units correspond to the value of the on-chip voltage reference.
2. The PCM word corresponding to positive input values between two successive decision values numbered nand n + 1
'(see column 4) is (255-n) expressed as a binary number.
3. The PCM word on the highways is the same as the one shown in column 6.
4. The voltage output on the VFR lead is equal to the normalized value given in the table, augmented by an offset. The
offset value is approximately 15 mY.
5. x128 is a virtual decision value.
6-9
inter
2910A
VFR
_
. . . . __ ...... _ _ . . . __ • _ _ _ _ _ _ ............ u
...... _ . . . . . _ . . . . . . . . . ..
VFx
006785-10
Figure 10. Codec Transfer Characteristic
During signaling frames, a 7-bit transfer characteristic is implemented in the decoder. This characteristic
is derived from the decoder values in the attached
table by assuming a value of "1" for the LSB (8th
bit) and shifting the decoder transfer characteristics
one half-step away from the origin. For example, the
maximum decoder output level for signaling frames
has normalized value 7903, whereas it has value
8031 in normal (non-signaling) frames.
APPLICATIONS
VFx
r-------------,
8 KHz
CO DEC
---'\1'11\
5001"1
R,
I
150 Kn :
+CAP1x
CAPx
1.
2000 pF
I
'r
GRDA I
-=-
I
I
I
VF., I
I
I
I
2 mV OFFSET
I
L-!?RDA --~,------ J
006785~11
Figure 11. Circuit Interface-without External Auto Zero
6-10
inter
2910A
For an 8 KHz sampling system the transmit holding
capacitor CAPx should be 2000 pF ± 20%.
The circuit interface with auto zero drawing shows a
possible connection between the VFx and AUTO
leads with the recommended values of C1 = 0.3 ""F,
R1 = 150 Kn., R2 = 330 Kn., and R3 = 470 Kn..
Auto Zero
Filters Interface
The 291 OA contains a transparent on-chip auto zero
plus a device pin for implementing a sign-bit driven
external auto zero feedback loop. The on-chip auto
zero reduces the input offset voltage of the encoder
(VFx) to less than 3 mV. For most telephony applications, this input offset is perfectly acceptable, since it
insures the encoder is biased in the lower 25% of
the first segment.
The filters may be interfaced as shown in the circuit
interface diagrams. Note that the output pulse
stream is of the non-return-to-zero type and hence
requires the (sin x)/x correction provided by the
2912A filter.
Where lower input offset is required the external
auto zero loop may be used to bias the encoder exactly at the zero crossing point. The consequence of
the external auto zero loop, aside from extra components, is the addition of the dithering auto-zero signal to the input signal, resulting in slightly higher idle
channel noise (approximately 2dB) than when the,
external loop is not used. Consequently, where the
application permits, it is recommended that the external auto zero loop not be used. When not used,
the AUTO pin should float.
For higher drive capability or increased system reliability it may be desirable that the Ox output of a
group of Codecs be buffered from the system PCM
bus with an external three-state or open collector
buffers. A buffer can be enabled with the I!EPropriate
Codec generated TSx signal or signals. TSx Signal
may also beused to activate external zero code suppression logiC, since the occurrence of an active
state of any TSx implies the existence of PCM voice
bits (as opposed to transparent data bits) on the
bus.
Holding Capacitor
Ox Buffering
r-------,
I
I
I
r---
I
VFx
I
t---"""""'----1
AUTO
IIa
R.
470KO
33011
":"" GRDA
I __ _
L
006785-12
Figure 12. Circuit Interlace-with External Auto Zero
6-11
2910A
• Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ......... -10·C to + 80·C
Storage Temperature .......... - 65·C to + 150·C
All Input or Output Voltages with
Respect to Vss .... " .... , ..... -O.3V to + 20V
Vcc Voo GRDD, and GRDA with
Respect to Vss ................ - O.3V to + 20V
Power Dissipation ........................ 1.35W
D.C. CHARACTERISTICS
TA=O·C to +70·C, Voo= +12V ±5%, Vcc= +5V ±5%, Vss= -5V ±5%, GRDA=OV, GRDD=OV,
unless otherwise specified
DIGITAL INTERFACE
Symbol
Limits
Parameter
Min
Typ(l)
Units
I,l
Low Level Input Current
10
p.A
10
p.A
I'H
High Level Input Current
V,l
Input Low Voltage
V,H
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Test Conditions
Max
0.6
Y,N < V,l
Y,N >V,H
V
2.0
V
0.4
2.4
V
Ox. 10l = 4.0 mA
SIGR. 10l = 0.5 mA
'fSx. 10l = 3.2 mAo Open Drain
PDN, 10l = 1.6 mAo Open Drain
V
Dx.IOH = 15 mA
SIGR 10H = 0.08 mA
ANALOG INTERFACE
Symbol
Limits
Parameter
Min
Typ(1)
Max
Units
Test Conditions
ZAI
Input Impedance when
Sampling, VFx
125
300
500
Ii
in Series with CAPx to GRDA.
-3.1V < Y,N < 3.W
ZAO
Small Signal Output
Impedance, VFR
100
180
300
Ii
-3.W
VOR
Output Offset Voltage at VFR
±50
mV
all "1 s.. code sent to DR
V,X
Input Offset Voltage at VFx
±5
mV
VFx Voltage Required to
Produce all "1 s.. Code at Ox
VOL
Output Low Voltage at AUTO
(Vss+2)
V
400 Kli to GRDA
VOH
Output High Voltage at AUTO
V
400 Kli to GRDA
Vss
(Vcc- 2)
Vcc
< VOUT < 3.W
POWER DISSIPATION
Symbol
Limits
Parameter
Min
Typ(l)
Max
Units
Test Conditions
mA
Auto Output = Open Clock
Frequency = 2.048 MHz
IDDO
Standby Current
0.7
1.1
Icco
Standby Current
4
7.0
mA
Isso
Standby Current
1
2.5
mA
IDDI
Operating Current
11
16
mA
Icci
Operating Current
13
21
mA
Issl
Operating Current
4
6.0
mA
NOTE:
1. Typical values are for T A = 25°C and nominal power supply values.
6-12
intJ
2910A
A.C. CHARACTERISTICS
TA=O°c to + 70°C, VDD= +12V ±5%, VCC= +5V ±5%, VBB= -5V ±5%, GRDA=OV, GRDD=OV,
unless otherwise specified
TRANSMISSION
Symbol
Limits
Parameter
Typ(1)
Min
SID
Signal/Tone Distortion Ratio,
C-Message Weighted
Half Channel
(See Figure 1)
Unit
Test Conditions
dB
dB
dB
VFx = 1.02 KHz, Sinusoid
-30 dBmO ,;; VFx ,;; 0 dBmO
-40 dBmO ,;; VFx < -30 dBmO
-45 dBmO ,;; VFx < -40 dBmO
Max
36
30
27
±0.25
±0.60
±1.5
±0.30
±0.70
±1.8
dB
dB
dB
VFx = 1.02 KHz, Sinusoid
-37 dBmO ,;; VFx';; +3 dBmO
-50 dBmO';; VFx < -37 dBmO
-55 dBmO ,;; VFx < -50 dBmO
AG
Gain Tracking Deviation
Half Channel(2)
Reference Level 0 dBmO
AGv
AG Variation with Supplies
Half Channel
±0.0002
±0.0004
±0.0004
±0.0008
dB/mY
dB/mY
-37 dBmO';; VFx ,;; +3 dBmO
-50 dBmO ,;; VFx < -37 dBmO
AGT
AG Variation with Temperature
Half Channel
±0.001
±0.002
±0.002
±0.005
dBI"C
dBI"C
-37 dBmO';; VFx ,;; +3 dBmO
-50 dBmO ,;; VFx < -37 dBmO
NIC1
Idle Channel Noise, C-Message
Weighted
2
7
dBrncO
No Signaling(3)
NIC2
Idle Channel Noise, C-Message
Weighted
10
13
dBrncO
with 6th and 12th Frame
Signaling(3)
NIC3
Idle Channel Noise, C-Message
Weighted
14
18
dBrncO
with 1 KHz Sign Bit Toggle
HD
Harmonic Distortion (2nd or 3rd)
-48
-44
dB
IMD
Intermodulation Distortion
2nd Order
3rd Order
-45
-55
dB
dB
VFx = 1.02 KHz, 0 dBmO;
Measured at Decoder Output VFR
4-Tone Stimulus in Accordance
with BSTR PUB 41009
NOTES:
1. Typical values are for TA = 25°C and nominal supply values.
2. Measured in one direction, either decoder or encoder and an ideal device, at 23°C, nominal supplies.
3. If the external auto-zero is used NIC1 has a typical value of 8 dBrncO and NIC2 has a typical value of 13 dBrncO.
4. DR of Device Under Test (D.U.T.) driven with repetitive digital word sequence specified in CCITT recommendation G.711.
Measurement made at VFR output.
5. With the D.C. method the positive and negative clipping levels are measured and AIR is calculated. With the A.C. method
a sinusoidal input signal to VFx is used where AIR is measured directly.
..
~~
-----------------
30 / /
/
/
..
AT&T 03 CHANNEL
BANI( COMPA flalllTV
SPECIFICATION
33
/
(ISSUE 3 10 77}
ATIT
D3 CHANNEL lANK
I1---:i;-~:;--:;;:====::j3
-55
-50
-37
•
COMPAna'LllY
SPECIFtCATtOH
CiSlUE 110.77)
END-Y()'END
INPUT
LEVEL
cl8mO
-2
-20
-\0
INPUT lEVEL !dBmO}
006785-13
006785-14
Figure 13. Signal/Total Distortion Ratio
(Half-Channel)
Figure 14. Gain Tracking Deviation
(Half·Channel)
6-13
(~G)
inter
2910A
A.C. CHARACTERISTICS
+5V ±5%, Vss= -5V ±5%, GRDA=OV, GRDD=OV,
TA=O·Cto +70·C, VDD=+12V ±5%, Vcc
unless otherwise specified (Continued)
GAIN AND DYNAMIC RANGE
Symbol
Limits
Parameter
Min
DmW
Digital Milliwatt Response
Unit
Typ(1)
5.53
Test Conditions
Max
23°C, Nominal Supplies(4)
5.63
5.73
dBm
-0.001
-0.002
dBI"C
Relative to 23·C(4)
±0.07
dB
Supplies ±5%(4)
2.23
VRMS
DmWT
DmWo Variation with
Temperature
DmWs
DmWo Variation with
Supplies
AIR
Input Dynamic Range
AIRT
Input Dynamic Range with
Temperature
-0.5
AIRS
Input Dynamic Range with
Supplies
±18
mVRMS
AOR
Output Dynamic Range, VFR 2.13
2.19
VRMS
AoRT
AoR Variation with
Temperature
-0.5
AORS
AOR Variation with Supplies
±18
2.17
2.20
2.16
Using D.C. and A. C. Tests(5)
23°C, Nominal Supplies
mVRMSI"C Relative to 23·C
Supplies ±5%
23·C, Nominal Supplies
mVRMSI"C Relative to 23·C
mVRMS
Supplies ±5%
SUPPLY REJECTION AND CROSSTALK
Symbol
Limits
Parameter
Min
Typ(1)
Unit
Test Conditions
dB
Decoder Alone(2)
Max
PSRRl
VDD Power Supply Rejection Ratio
45
PSRR2
Vss Power Supply Rejection Ratio
35
dB
Decoder Alone(2)
Decoder Alone(2)
PSRR3
Vcc Power Supply Rejection Ratio
50
. dB
PSRR4
VDD Power Supply Rejection Ratio
50
dB
Encoder Alone(3)
PSRR5
Vss Power Supply Rejection Ratio
45
dB
Encoder Alone(3)
PSRRs
Vcc Power Supply Rejection Ratio
50
dB
Encoder Alone(3)
CTR
Crosstalk Isolation, Receive Side
75
dB
(Note 4)
CTT
Crosstalk Isolation, Transmit Side
75
80
dB
(Note 5)
CAPX
Input Sample and Hold Capacitor
1600
200
80
2400
pF
NOTES:
1. Typical values are for T A = 25'C and nominal power supply values.
2. D.U.T. decoder; impose 200 mVp.p, 1.02 KHz on appropriate supply; measurement made at decoder output;
idle channel conditions.
3. D.U.T. encoder; impose 200 mVp.p, 1.02 KHz on appropriate supply; measurement made at encoder output;
idle channel conditions.
4. VFx of D.U.T. encoder = 1.02 KHz, 0 dSmO. Decoder under quiet channel conditions; measurement·made
output.
5. VFx = 0 Vrms. Decoder = 1.02 KHz, 0 dSmO. Encoder under quiet channel conditions; measurement made
output.
6-14
decoder in
encoder in
at decoder
at encoder
inter
2910A
A.C. CHARACTERISTIC-TIMING SPECIFICATION(1)
TA=O·Cto +70·C, voo= + 12V ±5%, vcc= +5V ±5%, vss= -5V ±5%, GRDA=OV, GRDD=OV,
unless otherwise specified
CLOCK SECTION
Symbol
Limits
Parameter
Min
tcy
Clock Period .
tr• tf
Clock Rise and Fall Time
tclK
Clock Pulse Width
215
Clock Duty Cycle (tClK + tCY)
45
tcoc
Units
Comments
ns
CLKx. CLKR (2.048 MHz Systems), CLKc
ns
CLKx. CLKR. CLKc
ns
CLKx. CLKR. CLKc
Max
485
0
30
55
.%
CLKx. CLKR
TRANSMIT SECTION
Symbol
Limits
Parameter
Min
Units
Comments
Timeslot
from Leading Edge of Transmit Timeslot (2)
Max
tVFX
Analog Input Conversion
tozx
Data Enabled on TS Entry
50
180
ns
0< ClOAO < 100 pF
tOHX
Data Hold Time
80
230
ns
o < ClOAO < 100 pF
tHZX
Data Float on TS Exit
75
245
ns
ClOAO = 0
tSON
Timeslot X to Enable
30
220
ns
o < CLOAO < 100pF
tSOFF
Timeslot X to Disable
70
225
ns
ClOAO = 0
tss
Signal Setup Time
0
ns
Relative to Bit 7 Falling Edge
tSH
Signal Hold Time
100
ns
Relative to Bit 8 Falling Edge
tFSO
Frame Sync Delay
15
20
150
ns
RECEIVE AND CONTROL SECTIONS
Symbol
Parameter
Limits
Min
Max
9 "Ae
9 "A6
Units
Comments
Timeslot
from Leading Edge of the Channel Timeslot
tVFR
Analog Output Update
tOSR
Receive Data Setup
20
ns
tOHR
Receive Data Hold
60
ns
tSIGR
SIGR Update
tFso
Frame Sync Delay
15
tosc
Control Data Setup
115
ns
Microcomputer Mode Only
tOHC
Control Data Hold
115
ns
Microcomputer Mode Only
1
/Ls
150
ns
from Trailing Edge of the Channel Timeslot
NOTES:
1. All timing Pl!rameters referenced to 1.5V. except tHZX and tSOFF which reference to high impedance state.
2. The 20 timeslot minimum insures that the complete AID conversion will take place under any combination of receive
interrupt or asynchronous operation of the Codec.. If the transmit channel only is operated. the AID conversion can be
completed in a minimum of 11 timeslots. Refer to the Codec Control General Requirement section for instructions on setting
a channel in an idle condition.
6-15
-f
:D
~
3:
G')
rn
:::j
ClK)(
~
2
3
tr -
-
4
tf
5
---
6
1
8
_
~
i
Z
~
i
z
A1
I
+CAP1x
CAP,
2000 pF
I
I
I
l
I
I
150 KO
I
I
DECODER
FILTER
c,
R,
.3,F
'&OKO
I
I
AUTO
...
3300
I
.". QRDA
I _I;-______
....:Y~F.~If__.l
YF., I I
I
..
I
L!"~~~
r---
r -____~YF~xl~_ _
I
r-------------,
I+-":":"='-+.--.J
YFxo
,
For an 8 KHz sampling system the transmit holding
capacitor CAPx should be 2000 pF ± 20%.
IIII
1~__I"I__
:
ENCODER
FILTER
L __ _
__ -.J
270158-10
Figure 12. Circuit Interface-With
External Auto Zero
1
2 mY OFFSET
I
Auto Zero
L-1;D;---------J
The 2911 A contains a transparent on-chip auto zero
plus a device pin for implementing a sign-bit driven
external auto zero feedback loop. The on-chip auto
zero reduces the input offset voltage of the encoder
(VFx) to less than 3 mY. For most telephony applications, this input offset is perfectly acceptable, since it
insures the encoder is biased in the lower 25% of
the first segment.
270158-9
Figure 11. Circuit Inter1ace-Wlthout
External Auto Zero
Filters Interface
The filters may be interfaced as shown in the circuit
interface diagrams. Note that the output pulse
stream is of the non-return-to-zero type and hence
requires the (sin x)/x correction provided by the
2912A filter.
Where lower input offset is required the external
auto zero loop may be used to bias the encoder exactly at the zero crossing point. The consequence of
the external auto zero loop, aside from extra components, is the addition of the dithering auto-zero signal to the input Signal, resulting in slightly higher idle
channel noise (approximately 2 dB) than when the
external loop is not used. Consequently, where the
application permits, it is recommended that the external auto zero loop not be used. When not used,
the AUTO pin should float.
Ox Buffering
For higher drive capability or increased system reliability it may be desirable that the Ox output of a
group of Codecs be buffered from the system PCM
bus with an external three-state or open collector
buffers. A buffer can be enabled with the ~ropriate
Codec generated ~x signal or signals. TSx signal
may also be used to activate external zero code suppression lo~ since the occurrence of an active
state of any TSx implies the existence of PCM voice
bits (as opposed to transparent data bits) on the
bus.
The circuit interface with external auto zero drawing
shows a possible connection between VFx and
AUTO leads with the recommended values of
C1 =0.3 ,...F, R1 = 150 Kn, R2=330n, and
R3=470 Kn.
6-27
intJ
2911A-1
• Notice: Stresses above those listed under ''llbsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ......... -10°C to + 80°C
Storage Temperature .......... -65°C to + 150°C
All Input or Output Voltages with
Respect to Vss ................ -0.3V to + 20V
Vee, Voo, GRDA, and GRDA with Respect
to Vss ....................... - 0.3V to + 20V
Power Dissipation ........................ 1.35W
D.C. CHARACTERISTICS
TA = O°C to + 70°C, Voo = + 12V ±5%, Vee
unless otherwise specified.
=
+5V ±5%, Vss
=
-5V ±5%, GRDA
= OV, GRDD =
OV,
DIGITAL INTERFACE
Symbol
limits
Parameter
Min
Typ(1)
Test Conditions
Unit
Max
IlL
Low Level Input Current
10
/LA
VIN
IIH
High Level Input Current
10
/LA
VIN
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
0.6
< VIL
> VIH
V
2.2
V
0.4
2.4
V
Dx, IOL = 4.0 mA
TSx, IOL = 3.2 mA, open drain
PDN, IOL = 1.6 mA, open drain
V
Dx, IOH
=
15 mA
ANALOG INTERFACE
Symbol
Limits
Parameter
Min
Typ(1)
Max
Unit
Test Conditions
ZAI
Input Impedance when
Sampling, VFx
125
300
500
!l
In series with CAPx to GRDA,
-3.1V < VIN < 3.1V .
ZAO
Small Signal Output
Impedance, VFR
100
180
300
!l
-3.1V
VOR
Output Offset Voltage at VFR
-50
50
mV
Minimum code to DR
VIX
Input Offset Voltage at VFx
-5
5
mV
Minimum positive code
produced at Dx
VOL
Output Low Voltage at AUTO
Vss
(Vss +2)
V
400 K!l to GRDA
VOH
Output High Voltage at AUTO (Vee -2)
Vee
V
400 K!l to GRDA
6-28
< VOUT < 3.1V
inter
2911A-1
D.C. CHARACTERISTICS
TA = O·Cto +70·C, voo = + 12V ±5%, vcc
unless otherwise specified. (Continued)
= +5V ±5%, vss = -5V ±5%, GRDA = av, GRDD = av,
POWER DISSIPATION
Limits
Parameter
Symbol
Typ(1)
Min
Unit
Test Conditions
Max
1000
Standby Current
0.7
1.1
mA
IccO
Standby Current
4.0
7.0
mA
Isso
Standby Current
1.0
2.5
mA
11
16
mA
1001
Operating Current
Icci
Operating Current
13
21
mA
Issl
Operating Current
4.0
6.0
mA
Auto Output = Open
Clock Frequency = 2.048 MHZ
NOTE:
1. Typical values are for T A
= 25°C and nominal power supply values.
A.C. CHARACTERISTICS
TA = O·Cto +70·C, Voo = + 12V ±5%, Vcc
unless otherwise specified.
= +5V ±5%, Vss = -5V ±5%, GRDA = OV, GRDD = OV,
TRANSMISSION
Symbol
Limits
Parameter
Min
SID
aG
aGv
aGT
Typ(1)
Unit
Signal to Total Distortion Ratio. 37
CCITT G.712 Method 2
dB
Signal level 0 dBmO to
-30 dBmO
(Half Channel)
31
dB
Signal level to - 40 dBmO
26
dB
Signal level to -45 dBmO
dB
dB
dB
VFx = 1.02 KHz, sinusoid
-40 dBmO ~ VFx ~ + 3 dBmO
- 50 dBmO ~ VFx < - 40 dBmO
- 55 dBmO ~ VFx < - 50 dBmO
2911A
Gain Tracking Deviation
Half Channel(3)
Reference Level -10 dBmO
aG Variation with Supplies
Half Channel
~G Variation with
Temperature Half Channel
±0.25
±0.60
±1.5
±0.30
±0.70
±1.8
±0.0002 ±0.0004 dB/mY -40 dBmO
±0.0004 ±0.0008 dB/mY - 50 dBmO
±0.001
±0.002
±O.002
±0.005
NIC
Idle Channel Noise
-85
-78
HD
Harmonic Distortion
(2nd or 3rd)
-48
-44
IMD1
IMD2
Test Conditions
Max
Intermodulation Distortion
G.712(7.1)
G.712(7.2)
-45
-50
6-29
dBrC -40 dBmO
dBrC - 50 dBmO
~
~
~
~
VFx
VFx
VFx
VFx
~
+3 dBmO
< - 40 dBmO
~
+3 dBmO
< - 40 dBmO
dBmOp Quiet Code. (Note 2)
dB
VFx = 1.02 KHz, 0 dBmO;
measured at decoder output VFR
dB
CCITTG.712
dBmO Two Tone Method
intJ
2911A-1
A.C. CHARACTERISTICS
TA = O°Cto + 70°C, VDD = +12V ±5%, VCC
unless otherwise specified. (Continued)
=
+5V ±5%, VSS
=
-5V ±5%,GRDA
=
OV,GRDD
=
OV,
GAIN AND DYNAMIC RANGE
Symbol
Parameter
Min
DmW
Digital Milliwatt Response
DmWT
DmWo Variation with
Temperature
DmWs
DmWo Variation
with Supplies
AIR
Input Dynamic Range
AIRT
5.58
Limits
Typ(1)
Unit
5.66
5.78
dBm
-0.001
-0.002
dBrC
±0.07
dB
2.243
VRMS
Input Dynamic Range
vs Temperature
-0.5
mVRMSrC
AIRS
Input Dynamic Range
vsSupplies
±18
mVRMS
AOR
Output Dynamic Range,
VFR
2.20
VRMS
AORT
AOR Variation with
Temperature
-0.5
mVRMSrC
AORS
AOR Variation with Supplies
±18
mVRMS
2.183
2.14
2.213
2.17
Test Conditions
Max
23°C, nominal supplies(4)
Relative to 23°C(4)
Supplies ± 5%(4)
Using D.C. and A.C. tests(5)
23°C, nominal supplies
Relative to 23°C
Supplies ±5%
23°C, Nominal Supplies
Relative to 23°C
Supplies ±5%
SUPPLY REJECTION AND CROSSTALK
Symbol
Parameter
Min
Limits
Typ(1)
Unit
Test Conditions
Max
PSRR1
VDD Power Supply Rejection Ratio
45
dB
decoder alone(6)
PSRR2
Vss Power Supply Rejection Ratio
35
dB
decoder alone(6)
PSRR3
Vcc Power Supply Rejection Ratio
50
dB
decoder alone(6)
PSRR4
VDD Power Supply Rejection Ratio
50
dB
encoder alone(7)
PSRR5
. Vss Power Supply Rejection Ratio
45
dB
encoder alone(7)
PSRR6
Vcc Power Supply Rejection Ratio
50
dB
encoder alone(7)
CTR
Crosstalk Isolation, Receive Side
75
80
dB
(Note 8)
CTT
Crosstalk Isolation, Transmit Side
75
80
dB
(Note 9)
CAPX
Input Sample and Hold Capacitor
1600
2000
2400
pF
NOTES:
1. TYPical values are for TA = 25°C and nominal power supply values.
2. If the external auto zero is used NIC has a typical value of - 76 dSmO.
3. Tested and guaranteed at 23'C, nominal supplies.
4. DR of Device Under Test (D.U.T.) driven with repetitive digital word sequence specified in CCITT recommendation G.711.
Measurement made at VFR output.
5. With the D.C. method the positive and negative clipping levels are measured and AIR is calculated. With the A.C. method
a sinusoidal input signal to VFx is used where AIR is measured directly.
6. D.U.T. decoder; impose 200 mVpp, 1.02 KHz on appropriate supply; measurement made at decoder output; decoder in
idle channel conditions.
7. D.U.T. encoder, impose 200 mVpp, 1.02 KHz on appropriate supply; meaurement made at encoder output; encoder in idle
channel conditions.
8. VFx of D.U.T encoder = 1.02 KHz, 0 dSmO. Decoder under quiet channel conditions; measurements made at decoder
output.
9. VFx = 0 Vrms. Decoder = 1.02 KHz, 0 dSmO. Encoder under quiet channel conditions; measurement made at encoder
output.
6-30
2911A·1
4,G
41111 •
•3
••7
INPUT
~~~~----~~------------------~~~~::L
-.7
-I
-1.8
-3
270158-11
Figure 13. Tracking Deviation (~G) (Half Channel)
-.Jl
;u~_______a~"~~~1"~C~______
Cd_
270158-12
Figure 14. Signal,to Total Distortion Ratio (Half Channel)
6-31
intJ
2911A-1
A.C. CHARACTERISTICS-TIMING SPECIFICATION(1)
= +5V ±5%, vaa = -5V
TA = O'Cto +70·C, voo = +12V ±5%, vcc
unless otherwise specified.
±5%, GRDA
=
OV, GRDD
=
OV,
CLOCK SECTION
Symbol
LImits
Parameter
Min
tCY
Clock Period
t r, tf
Clock Rise and Fall Time
tCLK
Clock Pulse Width
215
tcDC
Clock Duty Cycle (loLK + loy)
45
Max
Unit
Comments
ns
CLKx, CLKR (2.048 MHz systems), CLKc
ns
CLKx, CLKR, CLKc
ns
CLKx, CLKR, CLKc
%
CLKx, CLKR
485
0
30
55
TRANSMIT SECTION
Symbol
LImits
Parameter
Min
tVFx
Analog Input Conversion
20
tozx
Data Enabled on TS Entry
50
tOHX
Data Hold Time
80
tHZX
Data Float on TS Exit
75
tSON
Timeslot X to Enable
30
tsOFF
Timeslot X to Disable
tFso
Frame Sync Delay
Max
Unit
Timeslot
180
Comments
From Leading Edge of Transmit Timeslot(2)
ns
0< CLOAO < 100 pF
230
ns
0< CLOAO < 100 pF
245
ns
CLOAO
185
ns
0< CLOAO < 100 pF
70
225
ns
CLOAO
15
150
ns
=0
=0
RECEIVE AND CONTROL SECTIONS
Symbol
Parameter
LImits
Min
Max
e1j,e
e1j,e
Unit
Comments
Timeslot
From Leading Edge of the Channel Timeslot
tvFR
Analog Output Update
tOSR
Receive Data Setup
20
ns
tOHR
Receive Data Hold
60
ns
tFSO
Frame Sync Delay
15
tosc
Control Data Setup
115
ns
Microcomputer Mode Only
tDHC
Control Data Hold
115
ns
Microcomputer Mode Only
150
ns
NOTES:
1. All timing parameters referenced to 1.5V. except tHzx and tsOFF. which reference a high impedance state.
2. The 20 timeslot minimum insures that the complete AID conversion will take place under any combination of receive
interrupt or asynchronous operation of the Codec. Consult an Intel applications specialist or Intel Corporation for applications information which would allow operation with less than 20 timeslots.
6-32
2911A-1
TIMING WAVEFORMS(1)
TRANSMIT TIMING
270158-13
RECEIVE TIMING
270158-14
CONTROL TIMING
270158-15
NOTE:
1. All timing parameters referenced to 1.5V, except tHzx and tSOFF which reference a high impedance state.
6-33
intJ
2912A
PCM TRANSMITIRECEIVE FILTER
Consumption:
• 60LowmWPower
Typical without Power
•
•
•
Gain in Both Directions
• Adjustable
Fully Compatible with the Industry
• Standard
Intel 2912
Amplifiers
80 mW Typical with Power Amplifiers
0.5 mW Typical Standby
Low Idle Channel Noise:
2 dBrncO Typical, Receive
6 dBrncO Typical, Transmit
Excellent Power Supply Rejection:
40 dB Typical on VCC @ 50 KHz
30 dB Typical on VBB @ 50 KHz
Transmit Filter Rejects Low
Frequency Noise:
23 dB @ 60 Hz
25 dB @ 50 Hz
50 dB @ 16-2/3 Hz
•
•
•
•
•
D3/D4 and CCITT G712 Compatible
Common Mode Op Amp Input Rejection
75 dB Typical
Direct Interface to the Intel
2910Al2911A PCM Codecs Including
Stand-By Power Down Mode
Direct Interface with Transformer or
Electronic Hybrids
Fabricated with Reliable N-Channel
MOS Process
The Intel 2912A 2nd generation PCM line filter is a fully integrated monolithic device containing the two filters
of a PCM line or trunk termination. It has improved key parameters of power consumption, idle channel noise,
and power supply rejection. A single part exceeds both AT&T" 03/04 and CCITT transmission specs, exceeds digital Class 5 central office switching system stringent specifications, and is fully compatible with the
2912. The primary application for the 2912A is in telephone systems for transmission, switching, or remote
concentration.
An advanced version of the switched capacitor technique used for the 2912 is used to implement the transmit
and receive passband filter sections of the 2912A. The device is fabricated using Intel's reliable two layer
polysilicon gate NMOS technology. (See Intel Reliability Report RR-24 on the 2910A, 2911 A, and 2912.) The
combination of advances in the switched capacitor techniques first used on the 2912 and the NMOS technology results in a monolithic 2912A filter which is packaged in a standard 16-pin DIP.
o
0
Pin Names
~h
0\1FJCI+
YFkl~
os.
YFxo@
I
VFxl~
~G
(!) PWRO'
0PWRo-
VFAO
VFAI@
I
'DN
eLf(
PWRI
VfAI
@
@
Vee
270159-2
ClKO@
PWIU Vf"o
OPINNUMBER
Yea
Vee GROO GADA
00 00
@ @
VFXI+. VFxl
GSx
-VFxO
VFRI
VFRO
PWRI
PWRO+,PWRO
CLK
CLKO
PDN
Vee
Vaa
GRDD
GRDA
Analog Inputs
Gain Control
Analog Output
Analog Input
Analog Output
Driver Input
Driver Output
Clock Input
Clock Selection
Power Down
Power (+5V)
Power (-5V)
Digital Ground
Analog Ground
Figure 2. Pin Configuration
270159-1
Figure 1. Block Diagram
'AT&T is a registered trademark of American Telephone and Telegraph Corporation.
6-34
September 1988
Order Number: 270159·002
intJ
2912A
Table 1. Pin Description
Symbol
VFxl +
Pin No.
1
Function
Input
VFxl -
2
Input
GSx
3
Output
VFRO
4
Output
PWRI
5
Input
PWRO+
6
Output
PWRO-
7
Output
VBB
Vcc
VFRI
8
9
10
Power
Power
Input
GRDD
CLK(1)
11
12
Ground
Input
PDN
13
Input
CLKO(1)
14
Input
GRDA
15
Ground
VFxO
16
Output
Description
Analog input of the transmit filter. The VFxl + signal comes
from the 2 to 4 wire hybrid in the case of a 2 wire line and goes
through the frequency rejection and the antialiasing filters
before being sent to the Codec for encoding.
Inverting input of the gain adjustment operational amplifier on
the transmit filter.
Output of the ~in adjustment operational amplifier on the
transmit filter. sed for gain setting of the transmit filter.
Anal
RECEIVE FILTER TRANSFER CHARACTERISTICS (See Receive Filter Transfer Characteristics, Figure 8)
~ymbol
~RR
Parameter
Min
Typ(1) Max
Unit
o dBmO Input Signal
Gain Relative to Gain at 1 KHz with
Sinx/x Correction of 2910A or 2911A
Below 200 Hz
200Hz
Test Conditions
0.125
dB
-0.5
0.125
dB
300 Hz to 3000 Hz
-0.125
0.125
dB
3300 Hz
-0.35
0.03
dB
3400 Hz
-0.7
-0.1
dB
-14
dB
-30
dB
+0.1
dB
4000 Hz
4600 Hz and Above
odBmO Sign.al ==
1.6 VRMS X
. ( 7Tf )
Sin 8000
Input at VFRI
(8;~0)
~AR
~ART
Absolute Passband Gain at 1 KHz, VFRO -0.1
~ARS
Gain Variation with Supplies at 1 KHz
0.01
PTTR
Cross Talk, Transmit to Receive,
Measured at VFRO;
20 log (VFRO/VFXO)
NCR
Total C Message Noise at Output, VFRO
DOR
Differential Envelope Delay, VFRO,
1 KHz to 2.6 KHz
DAR
Absolute Delay at 1 KHz, VFRO
110
JLs
DPR1
Single Frequency Distortion Products
-48
dB
o dBmO Input Signal at 1 KHz
PPR2
Single Frequency Distortion Products at
Maximum Signal Level of + 3 dBmO at
VFRO
-45
dB
+ 3 dBmO Signal Level of
2.26 VRMS, 1 KHz Input at
VFRI
Gain Variation with Temperature at
1 KHz
0
RL = 00(3,4)
0.0002 0.002 dBI"C
o dBmO Signal Level
0.07
dBN
o dBmO Signal Level,
-70
-60
dB
2
6
Supplies ±5%
100
VFxl = 1.1 VRMS, 1 KHz
Output, VFRI Connected to
GRDA
dBrncO VFRO Output or PWRO + and
(Note 2) PWRO - Connected with
Unity Gain
JLs
NOTES:
1. Typical Values are for TA = 25°e and nominal power supply values.
2. A noise measurement of 12 dSrnc into a 6000 load at the 2912A device is equivalent to 6 dSrncO.
3. For gain under load refer to output resistance specs and perform gain calculation.
4. Output is non-inverting.
6-42
2912A
TRANSFER CHARACTERISTICS
+~~;~:B
+1.0dB
+0.125 dB
3000Hz
-0.125dB
20~~ «
EXPANDED
SCALE
«( «
«"
("""
'::::~3~~g~:
-0.125 dB
3000 Hz
OdB
TYPICAL
+0.03 dB
/'3300Hz
-0.70dB
3400Hz
-O.35dB
3300 Hz
-1.0dB
:/r
OdB
-10dB
-14dB
4000 Hz
-20dB
TYPICAL
-30 dB
-4-0 dB
-50 dB -+'""""~"
-SO dB
10Hz
1 KHz
100Hz
10KHz
270159-7
Figure 7. Transmit Filter
6-43
inter
2912A
~
,,/~.
,/
Typical Filter (1)
Transfer Function
+1.0 dB
«?et ««c/cecc,. «
",/'
\
+0.12SdB +0.12SdB
200 Hz
300 Hz
EXPANDEO
SCALE
...
,/~-"\
,
,,
+2.0dB
,< «, ,. . t<.
:::
-O.SOdB
200Hz
I
I
, ... '"
",-'
«
«
«
I
+0.12SdB
+0.03 dB
3000 Hz ~300 Hz
"
< «
OdB
,
«
«
0/
~
/
«!!
_~
-0.12SdB
3000Hz
Typical
-0.10dB
3400Hz
-0.3SdS
3300Hz
-0.70dS
3400Hz
-1.0 dB
OdS
-10dS
Typlcal---------~
-14dB
4000Hz
Fllt,r Transfer Function (2)
When multiplied by
-20dB
r. .In ~~o)J
J
L
-30dS
(8000)
which Is the SI~X output
-30dS
4600 Hz
response of the INTEL
2910A and 2911 A COaECS.
Where X ==
-40dS
8~O •
-SOdB
-60dB
10Hz
1 KHz
100Hz
10KHz
270159-8
Figure 8. Receive Filter
NOTES:
1. Typical Transfer Function of the Receive Filter as a Separate Component.
2. Typical Transfer Function of the Receive Filter Driven by the Sample and Hold Output of the Intel 2910A and 2911A
CODECS. The Combined Filter/CODEC Response Meets the Stated Specifications.
6·44
intJ
2912A
POWER SUPPLY REJECTION TYPICAL VALUES OVER 3 RANGES
..
.. -,
All VFXO wilh VFxl Connected to GRDA;
Input Op Amp at Unity Gain
vee
vee
vee
OIl
3D
I-
v••
VII.
~
2D ~
..§
I
10
270159-9
Figure 9. Transmit Filter
..
.
All VFRO with VFRI Connected to GRDA
vee
vee
OIl
-
~
VIla
3D
-
2D
r
v••
~
.g
.i
:I
10
270159-10
Figure 10. Receive Filter
6-45
2913 AND 2914
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
•
2913 Synchronous Clocks Only, 300 Mil
Package
•
2914 Asynchronous Clocks, 8th Bit
Signaling, Loop Back Test Capability
•
•
•
AT&T 03/04 and CCITT Compatible for
Synchronous Operation
Pin Selectable ,..,·Law or A·Law
Operation
•
•
•
•
•
•
Two Timing Modes:
- Fixed Data Rate Mode
1.536, 1.544, or 2.048 MHz
- Variable Data Rate Mode
64 KHz 2.048 MHz
Exceptional Analog Performance
28·Pln Plastic Leaded Chip Carrier
(PLCC) for Higher Integration
Low Power HM08-E Technology:
- 5 mW Typical Power Down
-140 mW Typical Operating
Fully Differential Architecture Enhances
Noise Immunity
On·Chip Auto Zero, Sample and Hold,
and Precision Voltage References
Direct Interface with Transformer or
Electronic Hybrids
The Intel 2913 and 2914 are fully integrated PCM codecs with transmit/receive filters fabricated in a highly
reliable and proven N-channel HMOS silicon gate technology (HMOS-E). These devices provide the functions
that were formerly provided by two complex chips (2910A or 2911A and 2912A). Besides the higher level of
integration, the performance of the 2913 and 2914 is superior to that of the separate devices.
The primary applications for the 2913 and 2914 are in telephone systems:
• Switching-Digital PBX's and Central Office Switching Systems
• Transmission-D3/D4 Type Channel Banks and Subscriber Carrier Systems
• Subscriber Instruments-Digital Handsets and Office Workstations
The wide dynamic range of the 2913 and 2914 (78 dB) and the minimal conversion time make them ideal
products for other applications such as:
• Secure Communications Systems
• Voice Store and Forward
• Satellite Earth Stations
• Digital Echo Cancellers
~
v••
Vee
Yeo
PWFlO+
OS,
PWRO+
Gs,
PWRO-
YFI(I-
PWAO-
Y'.I -
GS.
YF.I+
VFxl +
PON
GADA
V..
os.
PiiN
GRDA
CLKSEL
ASEL
LOOP
SIG.IABEL
SIc,a..
TixlDCLKx
O.
FSo
GADO
TSIC/DCLK.
D,
FS,
CLKx
I
I
< <
+ •
8
Jl
Ne
YFxl-
os.
YFxl+
Ne
CLKSEL
DCLK..
0
Ne
0,
DClK..
FS,
O.
Fl.
elK.
GRDD
elK"
PON
NC
-.
SlGx/ASEL
CLKSEL
TSxIOCLKx
LOOP
Ne
OCLKo
0,
DR
NC
210629-1
210629-2
rlff~
210629-3
Figure 1. Pin Configurations
6-46
October 1987
Order Number: 210629-003
TRANSMIT
SECTION
~..
VFx l
I
:1 ~ lii~
GSx ..
I
REFERENCE
AUTO
ZERO
1--1 COMPARATOR I-
I
L...--
iil
.....
!!!
0
::::=;::<:=:=:::-:::::-::::::::-::::.=::;=:::::-:"::.-;: ::::.:::
RECEIVE
n
~
SECTION
C
iii'
cc
DI
3
ANALOG
TO
DIGITAL
CONTROL
lOGIC
PWRO-~-1r----
I..
OUTPUT
IIEGISTER
'I..
I_
I ..
SlGxlASEl
CLKX
...
CD
0"·'·,·,·,·,·;"~,,,,·,···,·,·,·,·,,··,·,·,·,·,·,.'.:"""""'''''''''':''''''''=''''''''
(0)
II)
~
CONTROL
SECTION
hR
_____.....K
FSx
N
:::::-:::::-:-:::::::.;:::::::::-::::::;:::.::::::::::::::::~:::::::::::::::.;;::.;:::::.:::
Q.
CONTROL
lOGlIC
~
GSA
PWRO+4--1t-lr
~
III _ .TSx/OCLKx
f
,
C'::7:-:::
SUCCESSIVE
APPROXIMAnoN
REGISTER
• ..
c
C7l
.".
....
------......,
-Ox
SAMPLE
AND HOLD
ANOOAC
:!!
cc
~
l
I
BUFFER
~lOOP
...
~
]II:::oJ
~
SAMPLE
AND HOLD
AND DAC
REFERENCE
t::::t:==SEl
N
CD
I
I-
DIGITAL
TO
ANALOG
CONTROL
lOGIC
•
I+-
t
INPUT
REGISTER
...
DR
I"
DClKR
L-------1r--.-SlGR
"@
aID
IiiiiI
t t t t
Vee
Va.
GROO
GROA
If'"
c:::o
FlIR
~
cue,.
c:::o
210629-4
~
~
~
~
inter
2913 and 2914
Table 1. Pin Names
Name
Description
Power (-SV)
Name
Description
Power Amplifier Outputs
GSx
VFxl-, VFxl +
Transmit Gain Control
GSR
PDN
Receive Gain Control
GRDA
Analog Ground
Power Down Select
NC
No Connect
CLKSEL
Master Clock Frequency
Select
SIGx
Tral1smit Signaling Input
VBB
PWRO +, PWRO-
Analog Inputs
LOOP
Analog Loop Back
ASEL
/L- or A-Law Select
SIGR
Receive Signaling Output
TSx
Timeslot Strobe/Buffer Enable
DCLKR
Receive Variable Data Clock
DCLKx
Transmit Variable Data Clock
DR
FSR
Receive PCM Input
Dx
Transmit PCM Output
Receive Frame
Synchronization Clock
FSx
Transmit Frame
Synchronization Clock
GRDD
Digital Ground
CLKx
Transmit Master Clock
Vee
Power (+SV)
CLKR
Receive Master Clock (2914
Only, Internally Connected
toCLKx on 2913)
Table 2 Pin Description
Symbol
Function
VBB
Most negative supply; input voltage is - 5V ± 5 %.
PWRO+
Non-inverting output of power amplifier. Can drive transformer hybrids or high impedance
loads directly in either a differential or Single ended configuration.
PWRO-
Inverting output of power amplifier. Functionally identical and complementary to PWRO + .
GSR
Input to the gain setting network on the output power amplifier. Transmission level can be
adjusted over a 12 dB range depending on the voltage at GSR.
PDN
Power down select. When PDN is TTL high, the device is actiVe. When low, the device is
powered down.
CLKSEL
Input which
CLKSEL =
CLKSEL =
CLKSEL =
LOOP
Analog loopback. When this pin is TTL high, the analog output (PWRO + ) is internally
connected to the analog input (VFxl + ), GSR is internally connected to PWRO -, and
VFxl- is internally connected to GSx. A 0 dBmO digital Signal input at DR is returned as a
+ 3 dBmO digital signal output at Dx.
SIGR
Signaling bit output, receive .channel. In fixed data rate mode, SIGR outputs the logical
state of the eighth bit of the PCM word in the most recent signaling frame.
DCLKR
Selects the fixed or variable data rate mode. When DCLKR is connected to VBB, the fixed
data rate mode is selected. When DCLKR is not connected to VBB, the device operates in
the variable data rate mode. In this mode DCLKR becomes the receive data clock which
operates at TTL levels from 64 Kb to 2.048 Mb data rates.
L
must be pinstrapped to reflect the master clock frequency at CLKx, CLKR.
VBB ....................... 2.048 MHz
GRDD .................... 1.544 MHz
Vee ....................... 1.536 MHz
6-48
2913 and 2914
Table 2. Pin Description (Continued)
Symbol
Function
DR
Receive PCM input. PCM d,ata is clocked in on this lead on eight consecutive negative
transitions of the receive data clock; CLKR in- the fixed data rate mode and DCLKR in
variable data rate mode.
'
FSR
8 KHz frame synchronization clock inputltimeslot enable;receive channel. A multi-function
input which in fixed data rate mode distinguishes between signaling arid non-signaling
frames by means of a double or single wide pulse respectively. In variable data rate mode
this signal must remain high for the entire length of the timeslot. The receive channel
enters the standby state whenever FSR is TTL low for 300 milliseconds.
GRDD
Digital ground for all internal logic circuits. Not internally tied to GRDA.
CLKR
Receive master and data clock for the fixed data rate mode; receive master clock only in
variable data rate mode.
CLKx
........
FSx
Transmit master and data clock for the fixed data rate mode; transmit master clock only in
variable data rate mode.
•
8 KHz frame synchronization clock inputltimeslot enable, transmit channel. Operates
'.
'
independently but in an analogous manner to FSR.
The transmit channel enters the standby state whenever FSx is TTL low for 300
milliseconds.
Dx
Transmit PCM output. PCM data is clocked out on this lead on eight consecutive positive
transitions of the transmit data clock: CLKx. in fixed data rate mode and DCLKx in variable
data rate mode.
TSx/DCLKx
Transmit channel timeslot strobe (output) or data clock (input) for the transmit channel. In
fixed data rate mode, this pin is an open drain output designed to be used as an enable
signal for a three-state buffer. In variable data rate mode, this pin becomes the transmit
data clock which operates at TTL levels from 64 Kb to 2.048 Mb data rates.
SIGx/ASEL
A dual purpose pin. When connected to VBB. A-law operation is selected. When it is not
connected to VBB this pin is a TTL level input for signaling operation. This input is
transmitted as the eighth bit of the PCM word during signaling frames on the Dx lead. If not
used as an input pin, ASEL should be strapped to either Vee or GRDD.
NC
No connect.
GRDA
Analog ground return for all internal voice circuits. Not internally connected to GRDD.
VFxl +
Non-inverting analog input to uncommitted transmit operational amplifier.
VFxl -
Inverting analog input to uncommitted transmit operational amplifier.
GSx
Output terminal of transmit channel input op amp. Internally, this ill the voice signal input to
the transmit filter.
Vee
Most positive supply; input voltage is + 5V ± 5%.
6-49
inter
2913 and 2914
'Fhe following major functions are provided:
FUNCTIONAL DESCRIPTION
• Bandpass filtering of the analog signals prior to
.
encoding and after decoding
The 2913 and 2914 provide the analog-to-digital and
the digital-to-analog conversions and the' transmit
and receive filtering necessary to interface a full duplex (4 wires) voice telephone circuit with the PCM
highways of a time division multiplexed (TOM) system. They are intended to be used at the analog
termination of ~ PCM line or trunk.
• EncOding and decoding of voice and call progress informatlTESTPOINTS<
0.8
0.8
x=
210629-17
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for Logic "0". Timing measurements are made at 2.0V for a Logic
"1" and 0.8V for a Logic "0".
6·66
inter
2916/2917
HMOS COMBINED SINGLE CHIP PCM CODEC AND FILTER
,u.-Law, 2.048 MHz Master Clock
• 2916
2917 A-Law, 2.048 MHz Master Clock
• New 16-Pln Package for Higher
• Llnecard Density
03/04 and CCITT Compatible
• AT&T
Variable Timing Mode for Flexible
• Digital Interface: Supports Data Rates
from 64 KB to 2.048 MB
Differential Internal Architecture
• Fully
Enhances Noise Immunity
Timing Mode for Standard
• Fixed
32-Channel Systems: 2.048 MHz
•
Master Clock
Low Power HMOS-E Technology
- 5 mW Typical Power Down
-140 mW Typical Operating
On Chip Auto Zero, Sample and Hold,
and Precision Voltage References
•
with Direct Mode Intel
• Compatible
2910A, 2911A, and 2912A Designs
The Intel 2916 and 2917 are limited feature versions of Intel's 2913 and 2914 combination codec/filter chips.
They are fully integrated PCM codecs with transmit/receive filters fabricated in a highly reliable and proven
N-channel HMOS silicon gate technology (HMOS-E). These devices provide the functions that were formerly
provided by two complex chips (2910A or 2911 A and 2912A). Besides the higher level of integration, the
performance of the 2916 and 2917 is superior to that of the separate devices.
The primary applications for the 2916 and 2917 are in telephone systems:
• Switching-Digital PBX's and Central Office Switching Systems
• Subscriber Instruments-Digital Handsets and Office Workstations
Other possible applications can be found where the wide dynamic range (78 dB) and minimum conversion time
(125 p.s) are required for analog to digital interface functions:
• High Speed Modems
• Secure Communications
• Voice Store and Forward
• Digital Echo Cancellation
vcc
Vaa
PWRO+
GSx
PWRO-
VFXI -
PDN
GRDA
DClKR
TSX/DClKx
DR
Ox
FSR
FSx
GRDD
ClK
270156-1
Figure 1. Pin Configuration
6-67
October 1987
Order Number: 270156-002
2916/2917
XMIT
SECTION
GS,
AUTO
ZERO
---ll---..--.
.ftxlDCLK,
D,
YF.I-
SAMPLE
AND HOLD
SUCCESSIVE
COMPARATOR
~PPROXIMATION
AND DAC
REGISTER
ANALOG
TO
DIGITAL
CONTROL
OUTPUT
REGISTE"
I---------...---f--'.I,
.~~~~~~====~~~~==~~==~:::LOG~,c~~~~~~~~~~;::::::r~CLK
"ev
SECTION
IUFFER
SAMPLE
AND HOLD
AND DAC
_WAO -
_-+....____-..J
Fe.
270156-2
Figure 2; Block Diagram
Table 1. Pin Names
Name
Description
VBB
PWRO+, PWRO-
Name
Description
Power (-5V)
GSx
Transmit Gain Control
Power Amplifier Outputs
VFxl -
Analog Input
PDN
Power Down Select
GRDA
Analog Ground
DClKR
Receive Variable Data Clock
iSx
Timeslot Strobe/Buffer Enable
DR
Receive PCM Input
DClKx
Transmit Variable Data Clock
FSR
Receive Frame
Synchronization Clock
Dx
Transmit PCM Output
FSx
GRDD
Digital Ground
Transmit Frame
Synchronization Clock
Vee
Power (+5V)
ClK
Master Clock
inter
2916/2917
Table 2. Pin Description
Symbol
Function
Vss
Most negative supply, input voltage is - 5 volts ± 5%.
PWRO+
Non-inverting output of power amplifier. Can drive transformer hybrids or high impedance loads
directly in either a differential or single ended configuration.
PWRO-
Inverting output of power amplifier. Functionally identical and complementary to PWRO + .
PDN
Power down select. When PDN is TIL high, the device is active. When low, the device is
powered down.
DCLKR
Selects the fixed or variaolE\ data rate mode. When DCLKR is connected to Vss, the fixed data
rate mode is selected. Wtlen DCLKR is not connected to Vss, the device operates in the
variable data rate mode. In .this mode DCLKR becomes the receive data clock which operates
at TIL levels from 64 Kb to 2.048 Mb data rates.
DR
Receive PCM input. PCM data is clocked in on this lead on eight consecutive negative
transitions of the receive data clock; CLK in the fixed data rate mode and DCLKR in variable
data rate mode.
FSR
8 KHz frame synchronization clock input/timeslot enable, receive channel..Jn variable data rate
mode this signal must remain high for the entire length of the timeslot. Tile receive channel
enters the standby state whenever FSR is TIL low for 300 milliseconds.
GRDD
Digital ground for all internal logic circuits. Not internally tied to GRDA.
CLK
Master and data clock for the fixed data rate mode; master clock only in variable data rate
mode.
FSx
8 KHz frame synchronization clock input/timeslot enable, transmit channeL Operates
independently but in an analogous manner to FSR~ The transmit channel enters the standby
state whenever FSx is TIL low for 300 milliseconds.
Ox
Transmit PCM output.·PCM data is clocked out on this lead on eight consecutive positive
transitions of the transmit data clock; CLK in fixed data rate mode and DCLKx in variable data
rate mode.
TSx/DCLKx Transmit channel timeslot strobe (output) or data clock (input) for the transmit channel. In fixed
data rate mode, this pin is an open drain output designed to be used as an enable signal for a
three-state buffer. In varia!>le data rate mode, this pin becomes the transmit data clock which
operates at TIL levels from 64Kb to 2.048 Mb data rates.
GRDA
Analog ground return for all internal voice circuits. Not internally connected to GRDD.
VFx l -
Inverting analog input to uncommitted transmit operational amplifier.
GSx
Output terminal of on-chip transmit channel input op amp. Internally, this is the voice signal
input to the transmit filter.
Vee
Most positive supply; input voltage is + 5 volts ± 5%.
6-69
inter
2916/2917
To enhance system reliability, TSx and Ox will be
placed in a high impedance state approximately
30 Iks after an interruption of CLK.
FUNCTIONAL DESCRIPTION
The 2916 and 2917 provide the analog-to-digital and
the digital-to-analog conversions and the transmit
and receive filtering necessary to interface a full duplex (4 wires) voice telephone cirCUit with the PCM
highways of a time division multiplexed (TOM) system. They are .intended to be used at the analog
termination of a PCM line.
Power Down and Standby Modes
To minimize power consumption, two power down
modes are provided in which most 2916/2917 functions are disabled. Only the power down, clock, and
frame sync buffers, which are required to power up
the device, are enabled in these modes. As shown in
Table 3, the digital outputs on the appropriate channels are placed in a high impedance state until the
device returns to the active mode.
The following major functions are provided:
• Bandpass filtering of the analog signals prior to
encoding and after decoding
• Encoding and decoding of voice and call progress information
The Power Down mode utilizes an external control
Signal to the PDN pin. In this mode, power consumption is reduced to an average of5 mW. The device is
active when the signal is high and inactive when it is
low. In the absence of any signal, the PDN pin floats
to TTl:. high allowing the device to remain active continuously.
• Encoding and decoding of the signaling and supervision information
GENERAL OPERATION
System Reliability Features
The Standby mode leaves the user an option of
powering either channel down ·separately or powering the entire device down by selectively removing
FSx and/or FSR. With both channels in the standby
state, power consumption isreduqed.to an average
of 12 mW. If transmit qnly operation is desired, FSx
should be applied to the device while FSR is held
low. Similarly, if receive only operation is desired;
FSR should be applied while FSx is held low.
The combochip can be powered up by pulsing FSx
and/ or FSR while a TTL high voltage is applied to
PDN, provided that all clocks and supplies are connected. The 2916 and 2917 have internal resets on
power up (or when Vss or Vee are re-applied) in
order to ensure validity of the digital outputs and
thereby maintain integrity of the PCM highway.
On the transmit channel, digital outputs Dx and TSx
are held in a high impedance state for approximately
four frames .(500 Iks) after power up or ae.e!ication of
Vss or Vee. After this delay, .ox and TSx will be
functional and will occur in the proper timeslot. The
analog circuits on the transmit side require approximately 60 milliseconds to reach their equilibrium value due to the autozero circuit settling time.
Fixed Data Rate Mode
Fixed data rate timing, which is 2910A and 2911 A
compatible, is selected by connecting OCLKR to
Vss. It employs master clock CLK, frame synchronization clocks FSx and FSR, and output TSx.
Table 3. Power-Down Methods
Device Status
Power-Down
Method
Typical
Power
Consumption
Digital Output Status
Power Down Mode PDN = TTL Low
5mW
TSx and Dx are placed in a high impedance
state within 10 Iks.
Standby Mode
FSx and FSR are TTL Low
12mW
TSx and Dx are placed in a high impedance
state within 300 milliseconds.
Only Transmit is
on Standby
FSx is TTL Low
70mW
TSx and Dx are placed in a high impedance
state within 300 millisecond.s.
Only Receive is
on Standby
FSR is TTL Low
110mW
6-70
2916/2917
ClK serves as the master clock to operate the codec and filter sections and as the bit clock to clock
the data in and out from the PCM highway. FSx and
FSR are 8 KHz inputs which set the sampling frequency. 'i'Sx is a timeslot strobe/buffer enable output which gates the PCM word onto the PCM highway when an external buffer is used to drive the line.
Separate references are supplied to the transmit
and receive sections and each is trimmed independently during the manufacturing process. The reference value is then further trimmed in the gain setting
op-amps to a final precision value. With this method
the ,combochip can achieve the extremely accurate
Digital Milliwatt Responses specified in the transmission parameters, providing the user a significant
margin for error in other board components.
Data is transmitted on the highway at Ox on the first
eight positive transitions of ClK following the rising
edge of FSx. Similarly, on the receive side, data is
received on the first eight falling edges of ClK. The
frequency of ClK must be 2.048 MHz. No other frequency of operation is allowed in the fixed data rate
mode.
TRANSMIT OPERATION
Transmit Filter
The input section provides gain adjustment in the
passband by means of an on-Chip operational amplifier. This operational amplifier has a commoon mode
range of ± 2.17 volts, a maximum DC offset of
25 mV, a minimum open loop voltage gain of 5000,
and a unity gain bandwidth of typically 1 MHz. Gain
of up to 20 dB can be set without degrading the
performance of the filter. .The load impedance to
ground (GRDA) at the amplifier ,output (GSx) must
be greater than 10 kilohms in parallel with less than
50 pF. The input signal on lead VFxJ - can be either
AC or DC coupled. The input op amp can only be
used in the inverting mode as shown in Figure 3.
Variable Data Rate Mode
Variable data rate timing is selected by connecting
DClKR to the bit clock for the receive PCM highway
rather than to Vee. It employs master clock ClK, bit
clocks DClKR and DClKx, and frame synchronization clocks FSR and FSx.
Variable data rate timing allows for a flexible data
frequency. It provides the ability to vary the frequency of the bit clocks, from 64 KHz to 2.048 MHz. The
master clock is still restricted ,to 2.048 MHz.
A low pass anti-aliasing seption is included on-Chip.
This section typically provides 35 dB attenuation at
the sampling frequency. No external components
are required to provide the necessary anti-aliasing
function for the switched capacitor section of the
transmit filter.
In this mode, DClKR and DClKx become the data
clocks for the receive and transmit PCM highways.
While FSx is high, PCM data from Dx is transmitted
onto the highway on the next eight consecutive positive transitions of DClKx. Similarly, while FSR is
high, each PCM bit from the highway is received by
DR on the next eight consecutive negative transitions of DClKR.
On the transmit side, the PCM word will be repeated
in all remaining timeslots in the 125 jJ.s frame as long
as DClKx is pulsed and FSx is held high. This feature allows the PCM word to be transmitted to the
PCM highway more than once per frame, if desired,
and is only available in the variable data rate mode.
AZ
r--v
GS.
VF.I-
~
PreCision Voltage References
No external components are required with the combochip to provide the voltage reference function.
Voltage references are generated on-Chip and are
calibrated during the manufacturing process. The
technique uses a difference in sub-surface charge
density between two suitably implanted MOS devices to derive a temperature and bias stable reference
voltage. These references determine the gain and
dynamic range characteristics of the device.
Al
.
f>
Galn=_~
Al
6
Input
270156-3
Figure 3. Transmit Filter Gain Adjustment
6-71
inter
2916/2917
The passband section provides flatness and stopband attenuation which fulfills the AT&T 03/04
channel bank transmission specification and CCITT
recommendation G.714. The 2916 and 2917 specifications meet or exceed digital class 5 central office
switching systems requirements. The transmit fUter
transfer characteristics and specifications will be
within the limits shown in Figure 4.
RECEIVE QPERATION
Decoding
The PCM word at the DR lead is serially fetched on
the first eight data clock .bits of the frame. A DIA
conversion is performed on the digital word and the
corresponding analog sample is held on an internal
sample and hold capacitor. This sample is then
transferred to the receive filter.
A high pass section configuration was chosen to reject low frequency noise from 50 and 60 Hz power
lines, 17 Hz European electric, railroads, ringing frequencies and their harmonics, and other low frequency noise. Even though there is high rejection at
these frequencies, the sharpness of the band edge
gives low attenuation at 200 Hz. This feature allows
the use of low-cost transformer hybrids without external components. ,
Receive Filter
The receive filter provides passband flatness and
stopband rejection which fulfills both the AT&T 031
04 specification am;! CCITT recommendation G.714.
The filter contains the required compensation for the
(sin x)/x response of such, decoders. The receive
filter characteristics and· specifications will be within
the limits shown in Figure 5.
Encoding
The encoder internally samples the output of the
transmit filter and holds each sample on an interrial
sample and hold capacitor. The encoder then performs an analog to digital conversion on a switched
capacitor array. Digital data representing the sample
is transmitted on the first eight data clock bits of the
next frame:
Receive Output Power Amplifiers
A balanced output amplifier is provided in order to
allow maximum flexibility in output configuration. Either of the two outputs can be used single ended
(referenced to GRDA) to drive single ended loads.
Alternatively, the differential output will drive a
bridged load directly. The output stage is capable of
driving loads as low as 300 ohms single ended or
600 ohms differentially.
An on-chip autozero circuit corrects for DC-offset on
the input signal to the encoder. This autozero circuit
uses the sign bit averaging technique; the sign bit
from the encoder output is long term averaged and
subtracted from the input to the encoder. In this way,
all DC offset is removed from the encoder input
waveform.
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions, that is, when the digital input at DR is the eightcode sequence specified in CCITT recommendation
G.711.
Table 4. Zero Transmission Level Points
Symbol
Parameter
Value
Units
Test Conditions
OTLP1x
Zero Transmission Level Point
Transmit Channel (OdBmO) p.-Iaw
+2.76
+1.00
dBm
dBm
Referenced to 600n
Referenced to 900n
OTLP2x
Zero Transmission Level Point
Transmit Channel (OdBmO) A-law
+2.79
+1.03
dBm
dBm
Referenced to 600n '
Referenced to.900n
OTLP1R
Zero Transmission Level Point
Receive Channel (OdBmO) p.-Iaw
+5.76
+4.00
dBm
dBm
Referenced to 600n
Referenced to 900n
OTLP2R
Zero Transmission Level Point
Receive Channel (OdBmO) A-law
+5.79
+4.03
dBm
dBm
Referenced to 600n
Referenced to 900n
"'
6-72
inter
2916/2917
• Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ......... -1 O·C to + 80·C
Storage Temperature .......... - 6S·C to + 150·C
Vcc and GRDD with Respect
toVss ....................... -0.3Vto +15V
All Input and Output Voltages
with Respectto Vss ........... - 0.3V to + 1SV
Power Dissipation ........................ 1.35W
NOTICE: Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS
(TA = O·C to 70·C. Vcc = +SV ±S%. Vss = -SV ±S%. GRDA = OV. GRDD = OV. unless otherwise
specified)
Typical values are for TA = 25·C and nominal power supply values.
DIGITAL INTERFACE
Symbol
IlL
Parameter
Min
Typ
Low Level Input Current
Max
Unit
Test Conditions
10
/A-A
GRDD :s;; VIN :s;; VIL (Note 1)
VIH :s;; VIN :s;; Vcc
IIH
High Level Input Current
10
/A-A
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
2.0
V
0.4
2.4
V
IOL = 3.2 mA at Ox. TSx
,
V
IOH = 9.6 mA at Ox
pF
VOH
Output High Voltage
Cox
Digital Output Capacitance(2)
5
CIN
Digital Input Capacitance
5
10
pF
POWER DISSIPATION
All measurements made at fOCLK = 2.048 MHz. outputs unloaded.
Symbol
Parameter
ICC1
Vcc Operating Current(4)
Min
Typ
Max
Unit
14
19
mA
Test Conditions
ISS1
Vss Operating Current
-18
-24
mA
Iceo
VCC Power Down Current
0.5
1.0
mA
PDN :s;; VIL; after 10 /A-s
Isso
Vss Power Down Current
-O.S
-1.0
mA
PDN :s;; VIL; after 10 /A-s
Ices
VCC Standby Current
1.2
2.4
mA
FSx. FSR :s;; VIL; after 300 ms
FSx. FSR :s;; VIL; after 300 ms
Isss
Vss Standby Current
-1.2 ' -2.4
mA
P01
Operating Power Dissipation(3)
140
200
mW
Poo
Power Down Dissipation(3)
S
10
mW
PDN :s;; VIL; after 10 /A-s
PST
Standby Power Dissipation(3)
12
25
mW
FSx. FSR :s;; VIL
NOTES:
1. "'IN is the voltage on any digital pin.
2. Timing parameters are guaranteed based on a 100 pF load capaCitance. Up to eight digital outputs may be connected to
a common PCM highway without buffering. assuming a board capaCitance of 60 pF.
3. With nominal power supply values.
4. Vee applied last or simultaneously with Vee.
6-73
2916/2917
ANALOG INTERFACE, TRANSMIT CHANNEL INPUT STAGE
Symbol
Parameter
Typ
Min
lex1
Input Leakage Current, VFxl- .
RIXI
Input.Resistance, VFxl-
VOSXI
Input Offset Voltage, VFxl-
~ax
Unit
100
nA
10
AVOL
DC Open Loop Voltage Gain, GSx
Open Loop Unity Gain Bandwidth, GSx
CLXI
Load Capacitance; GSx
RLXI
Minimum Load Resistance, GSx
S;
VIN
S;
2.17V
MG
mV
2S
fe
Test Conditions
-2.17V
SOOO
1
MHz
SO
pF
10
KG
ANALOG INTERFACE, RECEIVE CHANNEL DRIVER AMPLIFIER STATE
Symbol
Parameter
Min
Typ
'Max
Unit
RORA
Output Resistance, PWRO +, PWRO-
1
G
VOSRA
Single-Ended Output DC Offset, PWRO + ,
PWRO-
7S
mV
CLRA
Load Capacitance, PWRO +, PWRO-
,100
Test Conditions
Relative to GRDA
pF
A.C. CHARACTERISTICS-TRANSMisSION PARAMETERS
Unless otherwise noted, the analog input is a 0 dBmO, 1020 Hz sine wave.( 1) Input amplifier is set for unity
gain, inverting. The digital input is a PCM bit stream generated by passing, a 0, dBmO, 1020 Hz sine wave
through an ideal encoder. Receive output is measured single ended. All output levels are (sin x)/x corrected.
Typical values are for TA = 2S'C and nominal power supply values. (TA = O"C to + 70'C; Vee = + sv ± S%;
Vee = -SV ±S%; GRDA = OV; GRDD = OV; unless otherwise specified).
GAIN AND DYNAMIC RANGE
Symbol
EmW
Parameter
Min
Typ
Max
Units
Test Conditions
Encoder Milliwatt Response -0.18 ±0.04 +0.18 dBmO Signal Input of 1.064 Vrms ",,-law
(Transmit Gain Tolerance)
Signal Input of 1.068 Vrms A-law
TA = 2SoC, Vee = -SV,
Vee = +SV
EmWTS EmW Variation with
Temperature and Supplies
-0.07 ±0.02 +0.07
DmW
-0.18
Digital Milliwatt Response
(Receive Gain Tolerance)
DmWTS DmW Variation with
Temperature and Supplies
dB
± S,% Supplies, 0 to 70"C
Relative to Nominal Conditions
±0.04 +0.18 dBmO Measu're Relative to OTLPR. Signal
Input per CCITT Recommendation
G.711. Output Signal of 1000 Hz.
RL =: 00
TA = 25'C;VBB = -SV,
Vee = +SV.
-0.07 ±O'.02 +0.07
dB
±S% Supplies, 0 to 70"C
NOTE:
1. 0 dBmO is defined as the zero reference point of the channel under test (OTLP). This corresponds to an analog Signal
input of 1.064 volts rms or an output of 1.503 volts rms (for ,...Iaw).
'
6-74
inter
2916/2917
GAIN TRACKING
Reference Level = -10 dBmO
Symbol
2916
Parameter
Min
GT1x
Transmit Gain Tracking Error
Sinusoidal Input; ,...Iaw
GT2x
Transmit Gain Tracking Error
Sinusoidal Input; A-law
GTIR
Receive Gain Tracking Error
Sinusoidallnput;/L-Iaw
.
GT2R
2917
Max
Min
Unit
±0.25
±0.5
±1.2
±0.25
±0.5
±1.2
±0.25
±O.5
±1.2
,
Receive Gain Tracking Error
Sinusoidal Input; A-law
Test Conditions
Max
±0.25
±0.5
±1.2
dB
dB
dB
+3to -40.dBmO
-40 to -50dBmO
-50 to -55 dBmO
dB
dB
dB
+3to -40dBmO
-40 to -50 dBmO
-50 to -55 dBmO
dB
dB
dB
+3to -40dBmO
-40 to -50 dBmO
-50 to -55 dBmO
Measured at PWRO+,
Rl = 3000
dB
dB
dB
+3to -40dBmO
-40 to -50 dBmO
-50to -55dBmO
Measured at PWRO + ,
Rl = 3000
NOISE (All receive channel measurements are single ended)
Symbol
2916
. : Parameter
Min
Typ
2917
Max
Min
Typ
Test Conditions
Unit
Max
NXC1
Transmit NOise, C-Message
Weighted
15
Nxp
Transmit NOise,Psophometrically
Weighted
NRC1
Receive Noise, C-Message
Weighted: Quiet Code
11
dBrncO DR
NRC2
Receive Noise, C-Message
Weighted: Sign Bit Toggle
12
dBrncO
Input to DR is Zero Code
with Sign Bit Toggle at 1 KHz
Rate
NRP
Receive Noise, Psophorrietrically
Weighted
.,
-79
dBmOp
DR = Lowest Positive
Decode Level
NSF
Single Frequency Noise
End to End Measurement
-50
dBmO
PSRR1
VCC Power Supply Rejection,
Transmit Channel
-30
-30
dE!
Idle Channel; 200 mV pop
Signal on Supply; 0 to 50
KHz, Measure at Ox
PSRR2
VBB Power Supply Rejection,
Transmit Channel
-30
-30
dB
Idle Channel; 200 mV pop
Signal on Supply; 0 to 50
KHz, Measure at Ox
PSRR3
Vee Power Supply Rejection,
Receive Channel
-25
-25
dB
Idle Channel; 200 mV pop
Signal on Supply; Measure
Narrow Band at PWRO + ,
Oto 50 KHz
PSRR4
VBB Power Supply Rejection,
Receive Channel.
-25
-25
dB
Idle Channel; 200 mV pop
Signal on Supply; Measure
Narrow Band at PWRO + ,
Oto 50 KHz
CTTR
Crosstalk, Transmit to Receive
-71
-71
dB
Input = 0 dBmO, Unity
Gain, 1.02 KHz, DR =
Lowest Positive Decode
Level, Measure at PWRO+
CTRT
Crosstalk, Receive to Transmit
-71
-71
dB
DR = 0 dBmO, 1.02 KHz,
Measure at Ox
-75
dBrncO
Unity Gain
dB mOp
Unity Gain
,
-50
6-75
=
11111111
CCITT G.712.4.2
Measure at PWRO +
inter .
2916/2917
DISTORTION
Symbol
Parameter
Min Typ Max
Test Conditions'
Unit
odBmO to -
Transmit Signal to Distortion, ~-law
Sinusoidal Input;
cCln G.714-Method 2 (2916)
36
30
25
dB
dB
dB
Transmit Signal to Distortion, A-law
, Sinusoidal Input;
cCln G.714-Method 2 (2917)
36
30
25
dBmO to -30 dBmO
dB
dB· -30 dBmO to-40 dBmO
-40 dBmO to -45 dBmO
dB
Receive Signal to Distortion, ~-law
Sinusoidal Input; cCln G.714-Method
2 (2916)
36
30
25
dB
dB
dB
dBmO to - 3Q dBmO
- 30 demO to -40 dBmO
- 40 dBmO to - 45 dBmO
SD2R
Receive Signal to Distortion, A-law
Sinusoidal Input; cCln G.714-Method
2 (2917)
36
30
25
dB
dB
dB
o dBmO to - 30 dBmO
-30 dBmO,to ;-.40 dBmO
-40 dBmO to -45 dBmO
DPx
Transmit Single Frequency Distortion
Products (2916)
-46 dBmO AT&T Advisory #64 (3.8)
o dBmO Input Signal
DPR
Receive Single Frequency Distortion
Products (2916)
-46 dBmO AT&T Advisory #64
o dBniO Input Signal
IMD1
Intermodulation Distortion,
End to End Measurement
-35
IMD2
Intermodulation Distortion,
End to End Measurement .
-49 dBmO cCln G.712 (7.2)
SOS
Spurious Out of Band Signals,
End to End Measurement
-25 dBmO CClnG.712 (6.1)'
SIS
Spurious In Band Signals,
End to End Measurement
-40 dBmO cCln G.712 (9)
DAX
Transmit Absolute Delay
245
~s
Fixed Data Rate. ClKx = 2.048
MHz; OdBmO, 1.02 KHz Input
Signal, Unity Gain. Measure
atDx·
Dox
Transmit Differential Envelope Delay
Relative to DAX
170
95
45
105
~s
f = 500 Hz to 600 Hz
f = 600 Hz to 1000 Hz
f = 1000 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
SD1x '
SD2x
SD1R
.,
30 dBmO
-30dBmOto -40dBmO
-40 dBmO to -45 dBmO
o
dB
~s
~s
~s
DAR
Receive Absolute Delay
190
~s
DOR
Receive Differential Envelope Delay
Relative to DAR
45
35
85
110
~s
6-76
~s
~s
~s
o
(3.~)
CCITTG.712 (7.1)
Fixed Data Rate; ClK = 2.048
MHz; Digital Input is DMW
Codes. Measure at PWRO +
f = 500 Hz to 600 Hz
f = 600 Hz to 1000 Hz
f = 1000 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
2916/2917
TRANSMIT CHANNEL TRANSFER CHARACTERISTICS
Input amplifier is set for unity gain, inverting.
Symbol
Parameter
GRX
Gain Relative to Gain at 1.02 KHz
Typ
Min
Max
Unit
16.67 Hz
-30
dB
50Hz
-25
dB
60Hz
-23
dB
-1.8
-0.125
dB
200Hz
Test Conditions
odBmO Signal Input at VFxl-
300 to 3000 Hz
-0.125
+0.125
dB
3300 Hz
-0.35
+0.03
dB
3400 Hz
-0.7
-0.10
dB
4000Hz
-14
dB
4600 Hz and Above
-32
dB
6·77
2916/2917
+1.0 dB
EXPAND£O
SCALE
OdB
-1.0dB
OdB
-10dS
-20dB
TYPICAL
-30dS
-40 dB
-50dS
-SOdB
10Hz
100Hz
1 KHz
10KHz
270156-4
Figure 4. Transmit Channel
6-78
inter
2916/2917
RECEIVE CHANNEL TRANSFER CHARACTERISTICS
Symbol
Parameter
GRR
Gain Relative to Gain at 1.02 KHz
Min
Max
Unit
+0,125
dB
-0.5
+0.125
dB
+0.125
+0.125
dB
3300 Hz
-0.35
+0.03
dB
3400 Hz
-0.7
-0.1
dB
4000 Hz
-14
dB
4600 Hz and Above
-30
dB
300 to 3000 Hz
Test Conditions
o dBmO Signal Input at DR
Below 200 Hz
200Hz
Typ
6-79
inter
2916/2917
+1.0dB
+0.125dB +0.125dB.
200 Hz
300 Hz
EXPANDED
SCALE
+0.125dB
-0.03dB
3000 Hi ~300 Hz
««««««({«.«'«««««««««««~
--...::
OdB
-0.50 dB
/.
200 Hz
-0.125dB
3000 Hz
-0.10dB
3400Hz
-0.35 dB
3300Hz
-0.70 dB
3400Hz
-1.0dB
OdB
-10dB
TYPICAL - - - - - - - - - : ; , ; .
-20dB
-30 dB
-40dB
-50 dB -
-SO dB
10Hz
100Hz
1 KHz
10KHz
270156-5
Figure 5. Receive Channel
6·80
inter
2916/2917
A.C. CHARACTERISTICS-TIMING PARAMETERS
CLOCK SECTION
Symbol
Typ
Parameter
Min
tCY
Clock Period, ClK
488
ns
tCLK
Clock Pulse Width, ClK
220
ns
tOCLK
Data Clock Pulse Width
220
ns
tcoc
Clock Duty Cycle, ClK
45
t r, tf
Clock Rise and Fall Time
Max
50
5
Unit
55
%
30
ns
Test Conditions
fCLK = 2.048 MHz
64 KHz ~ fOCLK ~ 2.048 MHz
TRANSMIT SECTION, FIXED DATA RATE MODE(1)
.Parameter
Min
Max
Unit
tozx
Data Enabled on TS Entry
0
145
ns
o<
toox
Data Delay from ClK
0
145
ns
0< CLOAO < 100 pF
tHZX
Data Float on TS Exit
60
215
ns
CLOAO = 0
tSON
Timeslot X to Enable
0
145
ns
0< CLOAO < 100 pF
tSOFF
Timeslot X to Disable
60
215
ns
CLOAO = 0
tFSO
Frame Sync Delay
100
tcLK
ns
Symbol
Typ
Test Conditions
CLOAD < 100 pF
RECEIVE SECTION, FIXED DATA RATE MODE
Symbol
Parameter
Min
tOSR
Receive Data Setup
10
tOHR
Receive Data Hold
60
tFSD
Frame Sync Delay
100
Typ
Max
Unit
ns
ns
tCLK
NOTE:
1. Timing parameters TDZX, THZX, and TSOFF are referenced to a high impedance state.
6·81
ns
Test Conditions
2916}2917
WAVEFORMS
Fixed Data Rate Timing
TRANSMIT TIMING
~
i ~~
~
ICLK
Fl.
'
I
CLK
2
3
4
~j
5
•
7
•
I,
.
270156-6
CLK
D.
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-_I-I~'~"
270156-7
NOTE:
1. All timing parameters referenced to VIH and VIL except tozx. tsoFF and tHZX which reference a high Impedan~e state.
RECEIVE TIMING
CYTtMEILOT
!eLK'
CLK
FIR
~
'-1' ,..
j
2,
:,
4
to
I
"
7
•
.
~------------------------------------------270156-8
STAILE
270156-9
NOTE:
1. All timing parameters referenced to VIH and VIL.
6·82
2916/2917
TRANSMIT SECTION, VARIABLE DATA RATE MODE(1)
Symbol
Parameter
tTSOX
Timeslot Delay from DCLKx(2)
tFSO
Frame Sync Delay
Max
Unit
140
tox-140
ns
100
tCy-100
ns
Min
Typ
toox
Data Delay from DCLKx
0
100
ns
tOON
Timeslot to Ox Active
0
50
ns
tOOFF
Timeslot to Ox Inactive
tox
Data Clock Period
tOFSX
Data Delay from FSx
0
80
ns
488
15620
ns
0
140
ns
Test Conditions
o < CLOAO < 100 pF
o < CLOAO < 100 pF
o < CLOAO < 100 pF
RECEIVE SECTION, VARIABLE DATA RATE MODE
Symbol
Parameter
Min
Max
Unit
tTSOR
Timeslot Delay from DCLKR(3)
140
Typ
tOR-140
ns
tFSO
Frame Sync Delay
100
tCy-100
ns
tOSR
Data Setup Time
10
tOHR
Data Hold Time
60
tOR
Data Clock Period
488
tSER
Timeslot End Receive Time
60
Test Conditions
ns
ns
15620
ns
ns
64 KB OPERATION, VARIABLE DATA RATE MODE
Unit
Test Conditions
488
ns
FSx is TIL High for Remainder of
Frame
1952
ns
FSR is TIL High for Remainder of
Frame
Symbol
Parameter
Min
tFSLX
Transmit Frame Sync Minimum
Downtime
tFSLR
Receive Frame Sync Minimum
Downtime
tOCLK
Data Clock Pulse Width
Typ
Max
10
J.Ls
NOTES;
1. Timing parameters tOON and tOOFF are referenced to a high impedance state.
2. tFSLX minimum requirements overrides tTSOX maximum spec for 64 KHz operation.
3. tFSLR minimum requirements overrides tTSOR maximum spec for 64 KHz operation.
6·83
2916/2917
VARIABLE DATA RATE TIMING
TRANSMIT TIMING
270156-10
RECEIVE TIMING
270156-11
NOTE:
.
1. All timing parameters referenced to VIH and VIL except tDON and tOFF which reference a high impedance state.
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUTIOUTPUT
2.4=>(
0.45
2.0
2.0
>TEST POINTS<
0.8
)C
0.8
270156-12
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V for a Logic "0". Timing measurements are made at 2.0V for a Logic "1" and
O.BV for a Logic "0".
6-84
inter
APPLICATIONS INFORMATION
2910A/2911A/2912A
CODECINTERFACE
CLOCK INTERFACE
The 2912A PCM Filter is designed to directly interface to the 2910A and 2911A Codecs as shown below. The transmit path is completed by connecting
the VFxO output of the 2912A to the coupling capacitor associated with the VFx input of the 2910A
and 2911 A codecs. The receive path is completed
by directly connecting the codec output VFR to receive input of the 2912A VFRI. The PDN input of the
2912A should be connected to the PDN output of
the codec to allow the filter to be put in the powerdown standby mode under control of the codec.
To assure proper operation, the ClK input of the
2912A should be connected to the same clock provided to receive bit clock, ClKR of 2910A or 2911A
Codec as shown below. The ClKO input of the
2912A should be set to the proper voltage depending on the standard clock frequency chosen for the
codec and filter.
DIGITAL
2110A
~
SIGx ••- - - ' - - - - - - - - - - - - - - - - - - - - - - - ,
SIG".'- - - - - - - - - - - - - - - - - - - ,
r------t-VDD
POWER SUPPLY
INPU~S
CONTROL
} FROM SYSTEM
LINE
~
2112A
OUTPUT TO
ELECTRONIC HYBRIDS
PCM FRAME SYNCH
AND 81T CLOCKS
POWER AMPLIFIER INPUT
r-:-±---' r--:::-:;-i:-,--+-INPUT FROM PCM HIGHWAY
POWER AMPLIFIER OUTPUT
{
TO TRANSFORMER HYBRIDS
GRDA
~
GRDO
*
=-~:~D };:'~~ES
~------------------------------------~---vu
111 OECOUPLING CAPACITORS
~GRDA
270219-1
Figure 1. A Typical 2910A Codec and 2912A Filter Configuration
6-85
October 1986
Order Number: 270219-001
intJ
2910A/2911A/2912A
10) The optimum grounding configuration is to maintain separate digital and analog grounds on the
circuit boards, and to carry these grounds back
to the power supply with a low il'11pedance connection. This keeps the grounds'separate over
the entire system except at the power supply.
11) The voltage difference between ground 'leads
GRDA and GRDD (analog and digital ground)
should not exceed two volts. One method of
preventing any substantial voltage difference between leads GRDA and GRDD is to connect two
diodes back to back in opposite directions
across these two ground leads ori each board.
12) C()dec~filter pairs should be aligned so that pins
9 through 16 of the filter face pins 1 through 12
of the codec. This minimizes the distance for analog connections between devices and with no
crossing analog lines.
13) No digital or high voltage level (such as ringing
supply) lines should run under or in parallel with
these analog VF connections. If the analog lines
are on the top (component side) of the PC
board, then GRDD, GRDA, or power supply
leads should be directly under them, on the bottom to prevent analog/digital coupling.
14) Both the codec and filter devices should be
shielded from traces on the bottom of the PCB
by using ground or power supply leads on the
top side directly under ,the device (like a ground
plane).
GROUNDING, DECOUPLING, AND
LAYOUT RECOMMENDATIONS' '
The most important steps in designing a low noise
line card are to insure that the layout of the circuit
components and traces'results in a minimum of
cross coupling between analog and digital signals,
and to provide well bypassed and clean power sup·
plies, solid ground planes, and miriimallead lengths
between components.
1) All power source leads should be bypassed to
ground on each printed circuit board (PCB),on
which codecs are provided. At least one electrolytic bypass capacitor (at least 50 J-LF) per board
is recommended at the point where all power
traces from the codecs and filters join prior to
interfacing with the edge connector pins assigned to the power leads,
2) When using two-sided PCBs, use both corresponding pins on opposite sides of the board for
the same power lead. Strap them together both
on the PCB and on the back of the edge connector.
3) Layout the traces on cod~c- and filter-equipped
boards such that analog signal and capacitor
leads are separated as widely as possible from
the digital clock and data 'leads.
4) Connect the codec sample and hold capacitor
with the shortest leads possible. Mount it as
close to the codec CAP1 X, CAP2X pins as possible. Shield the capacitor traces with analog
ground.'
,
15) Two +5V power supply leads (Vee> should be
used on each PCB, one to the filters, the other
to the codecs. These leads should be separately
decoupled at the PCB where they then join to a
single 5V supply at the backplane connector.
Decoupling can be accomplished with either a
series resistor/parallel capacitor (RC lowpass)
or a series RF choke and parallel capacitor of
each 5V lead. The capacitor should be at least
10 J-LF in parallel with a 0.1 J-LF ceramic. This
filters both high and low frequencies and accommodates large current spikes due to switching.
16) Both grounds and power supply leads must have
low resistance and inductance. This should be
accomplished by using a ground plane whenever possible. When narrower traces must be
used, a minimum width of 4 millimeters should
be maintained. Either multiple or extra large plated through holes should be used when passing
.the ground connections through the PCB.
5) Do not layout any board traces (especially digital) that pass between or near the leads of the
sample and hold capacitor(s) since they are in
high impedance circuits which are sensitive to
noise coupling.
6) Keep analog voice circuit leads paired on their
layouts so that no intervening circuit leads are
permitted to run parallel to. them and/or between them.
7) Arrange the layout for each duplicated line, trunk
or channel circuit in identical form.
8) Line circuits mounted extremely close to adjacent line circuits inorease the possibility of interchannel crosstalk.
9) Avoid assignment of edge connector pins to any
analog Signal adjacent to any lead carrying digital (periodic) signals or power,'
6-86
inter
2910A/2911A/2912A
17) The 2912A PCM filter should have all power
supplies bypassed to analog ground (GRDA).
The 2910Al2911A Codec +5V power supplies
should be bypassed to the digital ground
(GRDD). This is appropriate when separate
+ 5V power supply leads are used as suggested
in item 15. The - 5V and + 12V supplies should
be bypassed to analog ground (GRDA). Bypass
capacitors at each device should be high frequency capacitors of approximately 0.1 to 1.0
J.tF value. Their lead lengths should be minimized by routing the capacitor leads to the appropriate ground plane under the device (either
GRDA or GRDD).
18) Relay operation, ring voltage application, interruptions, and loop current surges can produce
enormous transients. Leads carrying such signals must be routed well away from both analog
and digital circuits on the line card and in backplanes. Lead pairs carrying current surges
should be routed closely together to minimize
possible inductive coupling. The microcomputer
clock lead is particularly vulnerable, and should
be buffered. Care should also be used in the
backplane layout to prevent pickup surges. Any
other latching components (relay buffers, etc.)
should also be protected from surges.
19) When not used, the AUTO pin should float with
minimum PC board track area.
ZERO TRANSMISSION LEVEL POINTS
2910A/2912A 0 dBmO
TRANSMIT
FILTER
2.85 dBm
DECOOER
DIGITAL
MILLIWATT
CODES
(OR EQUIV.1
5.85 dim
1.52 Vrm.
1.08 Vrml
RECEIVE
ENCODER
POWER
AMPLIFIERS
FILTER
5.85 dBm
S.Udlm
1.... Vrm.
1.52 Vrml
, SINGLE ENDED,IOO0
us dam
1.12 Vrmt
BALANCED. ICIO
11 .• dim
n
UMVrm,
270219-2
2911A/2912A 0 dBmO
TRANSMIT
ALTER
2.88d8m
1.08 Vrml
ENCODER
5.81 dBm
1.52 Vrml
DECODER
DIGITAL
MILLIWAn
CODES
(OR EQUIV.1
5.88 dBm
1.49 Vrm.
RECEIYE
POWER
FILTER
AMPLIFIERS
5.88 dIm
i.S2Yrms
SINGLE ENDED. 800n
U8dam
1.52 Vrmt
BALANCED, 800 n
11.edBm
3.05 Vrms
270219-3
6-87
inter
APPLICATION
NOTE
AP-142
November 1986
Designing Second-Generation
Digital Telephony Systems
Using the Intel 2913/14
Codec/Filter Combochip
ROBERT E. HOLM
TELECOM TECHNICAL SUPPORT
JOHN HUGGINS
TELECOM DESIGN ENGINEERING
Order Number: 210314-002
6-88
intJ
AP-142
Note: See data sheet for latest specifications. Values given In this application
note are for reference only, and were considered correct at the time of publication (Feb. 1982).
each feature and specifications for timing and performance levels. This application note, in conjunction with
the data sheet, describes in more detail how the new
and improved features help in the design of second-generation linecards first by comparing the two generations
of components to see where the improvements have
been made, and then by discussing specific design considerations.
1.0 INTRODUCTION
This application note describes the features and capabilities of the' 2913 and 2914 codec/filter combochips,
and relates these capabilities to the design and manufacturing of transmission and switching li~ecards.
1.1 Background
1.2 Comparison of Flrst- and SecondGeneration Component
Capabilities
The first generation of per line codecs (Intel
2910A/IIA) and'filters (Intel 2912A) economically integrated the analog-digital conversion circuits and
PCM formatting circuits into one chip and the filtering
and gain setting circuits into another chip. These two
chips helped to make possible the rapid conversion to
digital switching systems that has taken place in the last
few years.
The combochip represents a higher level of component
integration than the devices it replaces and, because of
the economics of LSI (replacing two chips with one),
ultimately will cost significantly less at the component
level. But comparison of the combochip block diagram
with first-generation single-chip codec and filter reveals
few major functional differences. Figure I compares the
first-generation codec and filter chips to the combochip. Both provide rigidly specified PCM capabilities of
voice signal bandlimiting and nonlinear companded
AID and D/A convet'l!ion. The first on-chip reference
voltage was introduced in the 2910/2911 single-chip
codecs and is included in the combochip. The provision
of uncommitted buffer amplifiers for flexible transmission level adjustment and enhanced analog output drive
was a feature ofthe now standard 2912 switched-capacitor PCM filter is available on the combochip. Like-
The second generation of Intel LSI PCM telephony
components, the 2913/14 Combochip, extends the level
of integration of the linecard by combining the codec
and filter functions for each line on a single LSI chip.
In the process of combining both functions, circuit design improvements have also improved performance,
reduced external component count, lowered power dissipation, increased reliability, added new features, and
maintained architectural transparency.
The 2913 and 2914 data sheet contains a complete description of both parts, including detailed discussions of
I
I
It ..
°lli
!I....
I
I
I
I
I
I
TRANSFORMER TRANSMISSION
DRIVER
LEVEL CONTROL
PCM
LOWPASS
I
SINGLE-CHIP PCM CODI!C
: .' 8INGLE'-C;:HIP PCM FILTER
I
I
COMBOCHIP
210314-1
Figure 1. LSI Partitioning of Codec/Filter Functions
6-89
inter
Ap-142
4iagnostia software, the bulk of the production, costs
are in the high-volume linecards. The combochip addresses these cost pressures and defers the appetite for
new integrated functions to a'future generation ofPCM
components.
wise, independent transmit (AID) and receive (0/A)
analog voice channels which pemit the two channels t.o'
be timed from independent (asynchronous) clocksources is common to the first- and second-generation devices. Finally, the ability to multiplex signalling bits on a
bit-stealing basis from the digital side of the device has
been duplicated on the combochip.
Figure 2 contains the block diagram of the 2913/14
combochip which illustrates not only the basic companding and filtering functions but also some of the
changes and new features contained in the second-generation devices, such as internal auto zero, separate
ADC and DAC for transmit and receive sections, respectively, precision gain setting (RCV section), and in"
put!output registers for both fixed and variable data
rates. Table 1 lists many of the features that are important to linecard design and performance. A direct comparison between first-and second-generation products
Data traffic-conscious systems manufacturers now provide dedicated codec, filter, and subscriber interface
functions on a per-subscriber basis, which in tum puts
intense cost pressures on these functions. The functional duplication of first-generation components addresses
the needs of the system manufacturer who wants to
cost reduce existing fixed-architecture system designs.
Whereas the bulk of the system development costs (and
time) are in the switching machine call processing and
Table 1. Comparison between 2913/14 Combochlp and the
2910A/11A/12A Single-Chip Codecs and Filters
Features
Power
Operating
Standby
2910A/11A plus 2912A'
2913/14
280-310mW
140mW
33mW
5mW
38-40
20-24
Pins
Board Area Including Interconnects
Data Rates
-Fixed
Normalized = 1.0
0.33
1.536, 1.544, 2.048 Mbps
Same
-Variable
Companding Law
None
-,u.-Law
2910
-A-Law
2911
+ 2912
+ 2912
64 Kbps -
2.048 Mbps
Strap Selectable
30dB
>35dB
NotSpec'd
> 35dB
Trim Using Pot Necessary
Precision Resistors
Eliminate Trim Req.
Direct
Yes
Yes
Timeslot ASSign
Yes
No
Yes
Yes
15 dBrncO Transmit
11 dBrncO Receive
15 dBrncO Transmit
11 dBrncO Receive
SID - Half Channel Improvement
See Data Sheet
See Section 2.0
GT -
See Data Sheet
See Section 2.0
PDN Pin
Frame Sync Removal or PDN Pin
Signalling
2910-8th Bit
2914-8th Bit
Auto Zero
External
Internal
S&HCaps
External Transmit
Internal Receive
Internal
Test Modes
None
Design Tests
Manufacturing Test
On-Line Operational Tests
Resistive Ladder
Capacitive Charge Redistribution
Ladder
Fuse Blowing ± 0.2 dB
Fuse Blowing ± 0.04 dB
PSRR
1 KHz
> 10 KHz
Gain Setting
Operating Modes
On-Chip VREF
ICN - Half Channel Improvement
Half Channel Improvement
Power Down (Standby)
Encoder Implementation
Filter/Gain Trim
6-90
inter
AP-142
XMIT
SECTION
AUTO
ZEAO
D.
VFXI+
SAMPLE
AND HOLD
AND DAC
VFXI-
8UCCEII'VE
APPROXIMATION
COMPARATOR
REOIITER
OUTPUT
Tlx/DCLKX
REGISTER
SIOx/ASEl
GI,
-1--;::=~.,
ANALOG
TO
OIGITAl
CONTROL
t-------------1r-- FS,
L~LO;G:'C_J-----------l--CLKX
ACV
SECTION
CLKSEL
PDIi
GS,
LOOP
PWAO+
--t--...--..,
PWAO-
_-+'-+__...J
D.
DCLKA
Yee
V..
GRDD
GRDA
Fa.-
elK"
210314-2
(a) Combochlp Block Diagram
Vee
PWRO +. PWROGSR
PDN
CLKSEL
LOOP
SIGR
DCLKR
DR
FSR
GRDD
Vee
Power (-5V)
Power Amplifier Outputs
Receive Gain Control
Power Down Select
Master Clock Frequency
Select
Analog Loop Back
Receive Signaling Bit Output
Receive Variable Data Clock
Receive PCM Input
Receive Frame
Synchronization Clock
Digital Ground
Power (+5V)
GSx
VFxl-. VFxl +
GRDA
NC
SIGx
Transmit Gain Control
Analog Inputs
Analog Ground
No Connect
Transmit Signaling Input
ASEL
TSx
DCLKx
Dx
FSx
p.- or A-law Select
Timeslot Strobe/Buffer Enable
Transmit Variable Data Clock
Transmit PCM Output
Transmit Frame
Synchronization Clock
Transmit Master Clock
Receive Master Clock
CLKx
CLKR
(b) Combochlp Pin Names
Figure 2. Block Diagram of 2913/14 Combochip
6-91
AP-142
shows the significant improvement in the combochip
both in performance levels and system flexibility.
Table 3. 2914 Factors which Increase Linecard
Manufacturing Yields and Efficiency
• Higher Reliability
-Fewer connections and components
-More integrated packaging
-More margin to specs
-Lower power
-NMOS proven process
-Less sensitive to parameter variations
2.0 DESIGN CONSIDERATIONS
The key point with the 2913/14 is that it will result in a
linecard that performs better and costs less than any
two-chip codec/filter solution. The lower cost results
from many factors, as seim in Table 2. Both direct replacement costs and less tangible design and manufacturing time savings combine to yield lower recurring
and nonrecurring costs. As an example, the wider margins to transmission specs and the higher power supply
rejection ratios of the 2913/14 will both shorten the
design time needed to build and test the linecard prototype and reduce the reject rate on the manufacturing
line.
• Fewer Manufacturing Steps
-No gain trimming
-On chip VREF
-Wide power supply tolerance
-On chip test modes
-Wide margins to spec
Table 2. 2913/14 Factors which Lower the Cost
of Llnecard Design and Manufacturing
• Lower LSI Cost (2914 vs. 2910/11
2912)
• Fewer External Components
• Less Board Area
• Shorter Design/Prototype Cycle
• Better Yields/Higher Reliability
• Lower Power/Higher Density
+
Table 4. Design Factors for 2914 which Reduce
Llnecard PCB Area
• Integrated Packaging
-2914 vs. 2910/11 + 2912
= 1/3 board area
-2913 takes even less space
• Fewer Interconnects/Components
-Codec/filter combined
-On-chip reference voltage
-On-chip auto zero
-On-chip capacitors
-No gain trim components
-No voltage regulators
Part of the recurring cost of linecard production is the
efficiency of the manufacturing line in turning out each
board. This is measured in both parts cost and time.
Average manufacturing time is strongly effected by the
line yield, i.e., the reject rate reliability. A linecard using the 2913/14 has many labor-saving features, which
also increases the reliability of the manufacturing process. Some of these features are detailed in Table 3.
The combination of fewer parameters to trim (gain, reference voltage, etc.), tolerance to wider power supply
variations, and on-chip test modes make the linecard
very manufacturable compared to first-generation designs.
• Efficient Layout (Facilitates Auto Insertion)
-Analog/digital sections separated on
chip
-Digital traces can cross under chip
-Two power supplies only
-Low powerlhigh density
Probably the most obvious improvement in linecard design based around the 2913/14 is the reduction in linecard PCB area needed compared to two-chip designs.
The combination of the codec and filter into a single
package alone reduced the LSI area by one-third. Table
4 shows many of the other ways in which board area is
conserved. In general, it reduces to fewer components,
more on-chip features, and layout of the chip resulting
in an efficient board layout which neatly separates the
analog and digital signals both inside the chip and on
the board.
6-92
intJ
AP-142
Table 5. 2913/14 Operating Mode Options Add Flexibility to Llnecard Design
Option
Results of Mode Selection
Mode Control Pins
2914 (24 Pin)
+ Signalling
I ' 2913 (20 Pin)
I A-Law/,...-Law. no Signalling
Companding Law
SIGX/ASEL
A-Law or ,...-Law
PowerOown
PDN
Transmit & Receive Side Go To Standby Power (5 mW)
Data Rate
Test Modes
FSx & FSR Removed
Ssme (12 mW)
FSxRemoved
Transmit Side Goes to Standby (110 mW)
FSRRemoved
Receive Side Goes to Standby (70 mW)
- Vcc/GRDOlVee
DCLKR = Vee
1.536/1.544/2.048 Mbps in Fixed Data Rate Mode
- Vee1GRDDIVee
DCLKe = Clock
Variable Data Rate Mode from 64 Kbps to 2.048 Mbps,
No Signalling
= Vee
Pl5N = Vee
Implements Analog Loopback
LOOP
DR - Vee
I No Loopback Capability
Provides Access to Transmit Codec Through ASEL and TSX
Pins
Provides Access to RCV Filter Input at DCLKR and Transmit
Filter Outputs at ASEL and 'fSX Pins
Many of the factors discussed-which result in efficient, cost-effective linecard designs-are discussed in
more detail both in the 2913/14 data sheet and in the
following sections of this note.
without significant system timing, control, or software
modifications. To this end, two distinct user-selectable
timing modes are possible with the combochip. For
purposes of discussion, these are designated (a) fixed
data rate timing (FORT) and (b) variable data rate tim"
ing (VDRT).
'
2.1 Operating and Test Mode
Selection
A key to designing with the 2913/14 combo is the wide
range of options available in configuring, either with
strap options or in real time, the different mOdes of
operation. The 2913 combochip (20 pins) is specifically
aimed at synchronous switching systems (remote concentrators, PABXs, central offices) where small package size is especially desirable. The 2914 combochip (24
pins) has additional features which are most suitable for
applications requiring 8th-bit signalling, asynchronous
operation" and remote testing of transmission paths
(e.g., channel banks). Once the specific device is selected, there is a wide range of operating modes to use in
the card design, as seen in Table 5. This table lists the
optional parameters and the pins which control the operating mode. The result of selecting a mode is listed for
both the 2913 and 2914.
The purpose of offering these options is to ensure that
the 2913/14 combo will accommodate any existing
linecard design with architectural transparency. At the
same time, features were designed in to facilitate design
'and manufacturing testing to reduce overall cost of development and production.
,2.2 Data Rate Modes
Any rapid conversion scerulrio presumes that the combochip will fit existing system architeCtures (retrofit)
FORT is identical to the 2910/2911 cOdec timing in
which a single high-speed clock serves both as master
clock for the codec/fIlter internal conversion/filtering
functions and as PCM bit clock for the high-speed serial PCM data bus over which the combochip transmits
and receives its digitized voice code words. In this
mode, PCM bit rates are necessarily confined to one of
three distinct frequencies (1.536 MHz, 1.544 MHz, or
2.048 MHz). Many recently designed systems employ
this type of timing which is sometimes referred to as
burst-mode timing because of the low duty cycle of
each timeslot (i.e., channel) on the time division multiplexed PCM bus. It is possible for up to 32 active combochips to share the same seria1 PCM bus with FORT.
VORT (sometimes referred to as shift register timing),
by comparison, utilizes one high-speed master clock for
the combochip internal conversion/filtering functions
and a separate, variable frequency, clock as the PCM
bit clock for the serial PCM data bus. Because the serial
PCM data rate is independent of internal conversion
timing, there is considerable flexibility in the choice of
PCM data rate. In this mode the master clock is permitted to be 1.536 MHz, 1.544 MHz, or 2.048 MHz,
while the bit clock can be any rate between 64 KHz and
2.048 MHz. In this mode it is possible to have a dedicated serial bus for each combochip or to share a single
serial PCM bus among as many as 32 active combo'chips.
6-93
inter
AP-142
Thus, the two predominant timing configurations of
present system architectures are served by the same device, allowing, in many cases, linecard redesign without
modification of any common system hardware or software. Additional details relating to the design of systems using either mode are found in section 3.0.
have its effect on line circuit costs even though the system transmission specifications may not reflect the improved performance margin. ,
2.3 Margin to Performance
Specifications
Gain Tracking-Figure 3 shows the gain tracking data
for both the transmit, and receive sides of the combo
using both sine wave testing (CCITT 0712.11 Method
2) and white noise testing (CCITT 0712.11 Method 1).
The data shows a performance very nearly equal to, the
theoretically best achievable using both test techniques.
End to end measurements, although not spec'd, also
show a corresponding· good performance with errors
less than or equal to the sum of the half channel values.
Half channel measurements have been made of the
transmission parameters-gain tracklng (QT), signal to
distortion ratio (SID), and idle channel noise (ICN).
The combochip benefits from design, manufacturing,
and test experience with first-generation PCM products
on the part of the system manufacturer, component
suppliers, and test equipment suppliers. The sub-millivolt PCM measurement levels and tens of microvolts
accuracy requirements on the lowest signal measurements often result in tester correlation problems, yield
losses, and excess costs for system and PCM component manufacturers alike. Thus additional performance
margin built into the PCM components themselves will
Signal to Distortion Ratio-This is a measure of the
system linearity and the accuracy in implementing the
companding codes. Figure 4 shows the excellent perfor-
Gain Tracking Error Versus Signal Level
2914 Combo AID
Sinusoidal Test (CCITT G712.11 Method 2)
Gain Tracking Error Versus Signal Level
2914 Combo DIA
Sinusoidal Test (CCITT G712.11 Method 2)
2 "
!
iii'
~
II:
o
II:
1
f5
.5
!
0
~
-1
~
II:
f5
.5
o
!
~
0
o
...
~ -1
o
I
~--I
1
~---------_I
~
=
... -.5
: -.5
1
1
I
1
INPUT
W.
1
I
1 1LEVEL
-55 -50 -40- - - - - - - - - - '0+3
1--":
dBmO
1
1
i
I
0"
1
1
1
I
-2
-2
210314-4
210314-3
Gain Tracking Error Versus Signal Level
2914 Combo AID
White Noise Test (CCITT G712.11 Method 1)
,Gain Tracking Error Versus Signal Level
2914 Combo DIA
White Noise Test (CCITT G712.11 Method 1)
1
1
1
1
1
1
1
iii'
~
~
i"'
!
~-I
II:
~
1':- _ _ _ _ _ _ _ _ _ _ _ _ J1
0
-2
r-+-+-..
1
-55 -50-:40
, I
L..l
1- - - - - - - - _ _ _ _ _ _ 11
~ .5
.5
gc -.5
::z -1
3
1
"'~
INPUT
1 1 LEVEL
0 +3
0
gc -.5
r------------ldB"!O
1
I
::z
I-~
~
1
I
I
i"i"--~
-55 ~50
't
-40
I
-1
I Il~~r
0 +3
r - - - - - - - - - - ---ldBmO
1
1--'
1
1
-2
1
210314-6
210314-9
Figure ,3. 2914 Half Chl!nnel Gain Tracking Performance Measurements
for Both Sine and Noise Testing
6·94
intJ
AP-142
--
i
0'40
.
~
~
~30
~
i
0'40
!i
.
~30
AID SINEWAYE TEST
~
!e2O
Q
5~
~
~
~
10
S!
D/A SINEWAYE TEST
0
1;;20
is
..
~
-
10
Z
~
0
-45 -40 -35 -30 -25
-15
-5
0
0
-45 -40 -35 -30 -25
5
INPUT LEVEL (dBmOl
-15
210314-7
2
.
Ii
Z30
0
is
~
I)
i
0
5
210314-8
ii
i40
~
1;;20
-5
INPUT LEYEL (dirnDl
/
!.4O
/--ft'''H~
0
\
1 Vfi-'."~
'-.
.
~
30
1;;20
is
FULL CHANNEL SPEC-
FULL CHANNEL SPEC
....
g
10
~
Z
0
50 -45 -40 -35 -30 -25
-15
-5
0
"in
5
INPUT LEYEL (dirnDl
10
0
50 -45 -40 -35 -30 -25
-15
-5
0
5
INPUT LEYEL (dirnDl
210314-9
210314-10
Figure 4. 2914 Half Channel Signal to Distortion Ratio (SID) Performance Measurements
for Both Sine and Noise Testing
mance of the 2914 for both the transmit (AID) and
receive (DI A) channels using sine wave and noise testing. The margin is greater than 3 dB above the half
channel spec which means that a larger error budget is
available to the rest of the channel.
Power Supply Rejection-Circuit innovation in the internal combochip design has resulted in significant improvements in power supply rejection in the 5 to 50
KHz range (Figure 7), and it is this frequency band
which usually contains the bulk of the switching regulator noise. These higher frequencies, outside the audio
range as they are, are not objectionable or even detectable in the transmit direction except to the extent that
they alias into the audio range as a result of internal
sampling processes in the transmit filter and AID converter. Sampling techniques in the combochip minimize
this aliasing. In the receive direction, excess high frequency noise which propagates onto the subscriber loop
can interfere with signals in adjacent wires and is thus
objectionable even without aliasing. The symmetrical
true differential analog outputs of the combochip are an
improvement from earlier designs which failed to maintain true power supply symmetry through the output
amplifiers. Not only does the differential design improve transmission performance, but it also reduces the
need for power supply bypass capacitors, thereby saving component cost on the linecard.
Statistical Analysis-A statistical analysis of G.T. and
SID measurements over many devices shows a very
tight distribution, as seen in Figure 5. There are several
consequences resulting from this highly desirable distribution: (1) the device performance is controllable, resulting in high yields, (2) the device circuit design is
tolerant of normal process variations, thereby ensuring
predictable production yields and high reliability, and
(3) understanding of the circuit design and process fundamentals is clearly demonstrated-largely as a result
of previous telephony experience with the Intel NMOS
process.
Idle Channel Noise-The third transmission parameter
is idle channel noise (ICN). Figure 6 gives half channel
ICN measurements which show a substantial margin to
specification.
6-95
inter
AP-142
2
ii
i
!a:
I
I~ENYELOPE
1
l _
1
15
.5
i
0
g-.5
... -1
~
MINIMAX
~40
1
1
1
1 INPUT
LEYEL
i
L ________ J
I
::J-50
I -55
-41/
~30
~
0
I
1
11 I+
________
0 3
1--1
1
1
Ii0
idBmO
~
(MIWMAX
ATaT SPEC. To\. 14
2114 COMaoCHIP
DIA IINIWAVE TEST
20
~
1
1
I
~
10
z
-2
S
210314-11
0
-45 -40 -25 -20 -2&
-15
INPUT LEYEL C-I
-I
0
5
210314-12
Figure 5. Statistical Analysis of Transmission Performance Showing
Tight Distribution Over Many Devices
I
I
AID
DIA
Weighting
ICN
C Message
15 dBrnCO
CMessage
11 dBrnCO
Figure 6. 2914 Idle Channel Noise (ICN)
Measurements
Autozero-The autozero circuit is contained completely on-chip. It automatically centers the signal/noise distribution at the encoder input., This ensures minimal '
ICN due to bit toggling and also maintains maximum
sensitivity to the AC signals of interest.
2.4 Power Conservation
Figure 8 illu*at~ typical power consumption and office equipment dissipation for a resistive line biasing
arrangement (with no loop current limiting) and for the
per-line PCM components. It can be seen that overall
line circuit power consumption and dissipation are
strong functions of subscriber loop resis~ce, and are
dominated by line biasing current regardless of loop
length. It can also be seen that the combochlp achieves
significant reductions in PCM component contributions relative to both the 291OA/2912A and
2910/2912. Present residential traffic characteristics
are such that the PCM components are active less than
10% of the time, and in its low-power standby state,
the combochip power dissipation drops t() typically
5 mW as the line Icurrent (and dissipation) goes to its
background on-hook leakage level of typically a few
milliwatts (but for very leaky lines, as much as 50 mW 500mW).
The concern for linecard power consumption and dissipation is related both to the cost of providing power
and to the system density problem involving convection
heat removal from the linecards. Consequently, much
recent line circuit development activity centers on elimination of the inefficient resistive line current feed both
by current limiting in short loops and by more exotic
and expensive per-line dc-dc converters. For both pres:
ent-generation designs and cost-reduction redesigns,
the typical combochip dissipation of 140 mW
active/5 mW standby will allow system board packing
density improvements and, power supply cost reductions.
A closer look at the effect ofloading (duty cycle) on the
average power dissipation of a combochip is given in
Table 6. Typical loading percents run as low as 5% for
very large switching systems (thousands of lines) up to
100% in nonswitching applications such as channel
banks. Clearly, the average power dissipation in a typical switching system is below 35 mW which facilitates
board packing density and cost of power considerations.
Table 6. Typical Power Dissipation Per Line
Using 2914 Combochip
6-96
Duty
Cycle
Power
Dissipation
Central
Office
5%
12mW
PABX
15%
25mW
Peak Hour
C.O.
50%
73mW
Channel
Bank
100%
140mW
inter
AP-142
POWER LINE
HARMONICS
VOICEBAND
100
SWITCHING REGULATOR
l0000HZ
1000HZ
-ZODB
-3ODB
-40DB
-50DB
210314-13
Figure 7. Wldeband 2914 Power Supply Rejection Ratio (PSRR)
72 VOLT BATTERY
900 OHM FEED RESISTOR
NO CURRENT LIMITING
200
400
800
800
1000
1200 1400
SUBSCRIBER LOOP RESISTANCE (OHMS)
1800
1800
2000
210314-14
Figure 8. Line Circuit Power Consumption and Dissipation Curves
6-97
inter
AP-142
has previously been in the nominal insertion loss of the
PCM filter and in the uncertainty of the reference voltage of the codec. With this cumulative 0.15 dB uncertainty in the PCM components themselves, the system
manufacturer had no choice but to resort to the cost
and manufacturing complexity of the active trim. The
combochip, however, can be trimmed during its manufacture to a nominal tolerance of ±0.04 dB which includes uncertainties in both the filter and codec voltage
reference functions. This leaves 0.21 dB uncertainty to
variations in the other line circuit elements and to temperature and supply variations.
2.5 Elimination of Gain Trim in the Line
Circuit
Four resistors-Rl- R4 of Figure 9-on the transformer side of the PCM components are used to establish
appropriate transmission levels at the PCM components and are, at first glance, equivalent in the two cases. However, a significant reduction in linecard manufacturing costs associated with individual line trim (or
mop-up) is possible with the combochip. The need for
this trim is dictated by system gain contrast specifications which typically require that the line-to-line gain
variation shall not exceed 0.5 dB, which translates to
0.25 dB for each (transmit and receive) channel. Table
7 shows that the major portion of this gain variation
The variation in combochip gain with supply and temperature has also been imprOVed to allow as low as
2910111
PCMCODEC
RING
TRANSFORM".:E~A~~=:::;-,,...:;;:::::.~
.----;
-------n1
I
~I
1:1
l____________~::~~~~~~~~~~~~~~~~~~~VCC
GRDD
Vss
GRDA
210314-15
(a) Line Circuit Utilizing Single-Chip PCM Codec and Filter
TRANSFORMER~::~--~~::;;;:~~-r~
r-41
~---t"--"I-ri.j.---..:t
1~ :f
TIP
1
1
1
r-+--..J
~--~
1
.......1_ _ _ _-+.......
'- _ _ _ _ _ ..J
210314-16
(b) Line Circuit Using Combochip
Figure 9. Schematics of the Codec/Filter Function and the 2/4 Wire Hybrid Transformers
6-98
inter
AP-142
Table 7. Gain Trim Budget for Codec/Fllter Functions
Device
2910
2912
2914
aT
Manufacturing Uncertainty
(Initial)
.aSupplles
Total
Variation· Budget
for Other. Components
±0.1
±0.05
±0.15
±0.1
±0.05
±0.15
±0.3dB
OdB
±0.04
±0.08
±0.12 dB
±0.13dB
,
• Assumes 0.5 dB end to end gain contrast specifications.
0.08 dB variation over supplies and temperature so that
more than half the system specification could be reserved for transformer, wiring, and resistor uncertainties. This possibility of using fixed precision gain trim
components and abandoning the active trim holds the
potential for simplification and cost reduction of the
line board manufacturing process.
version, Switching, and Transmission using the Intel
2910A/2911A codec and 2912 PCM filter) also describes the basics of using the fixed data rate mode for
first-generation codecs and filters which is essentially
the same as for the 2913/14 second-generation combo'.
chip.
'
3.2 Variable Data Rate Mode
2.6 Power Up/Down Considerations
The VDRT mode is described in some detail both in
section 2.2 and in the 2913/14 data sheet. This section
focuses on two design asPects: (I) the Iwvantage of
clocmg data on the rising edges of the clock for transmit and receive data, respectively, and (2) making the
2913/14 transparent in previously designed systems (a
retrofit" cost reduction redesign).
Power Supply Sequene&-There are no requirements
for a particular sequence of powering up the combochip. All discussions of power up or power down timing assume that both Vee and VBB are present.
Power Up Delay-Upon application of power supplies,
or coming out of the standby power down mode, three
circuit time constants must be observed: (1) digital signal timing, (2) autozero timing, and (3) filter settling.
An internal timing circuit activates SIFr , Dx. and TSx
approximately two or three frames after power up. Until this time, SIGr is held low and the other two signals
are in a tIj-state mode. During tlJis time, SIGx will have
no effect on the PCM output.
.
qock Timing-.-The 2913/14 is ideally set up to transmit and receive data, using the same clock, with no race
conditions or other marginal timing requirements. This
is accomplished by transmitting data on the rising edge
of the first clock pulse following the data enable pulse
FSx and receiving data on the falling edge of the clock,
which is directly in the mid91e of the Dx data, pulse.
Several manufacturers use leading edge timing for both
transmit and receive requiring an inversion of the receive clock.
Power 'Down Modes-These modes are described in detail in Table 3 of the +91~/14 data sheet except for a
fail-safe mode in ~e CLKx is inte~rupted. If this
should happen, both Dx and TSx go into the tri-state
mode until the clock is restored. This ensures the safety
of the PCM highway should the interrupted clock be a
loCal problem,
Figure 10 shows the transmit and receive clock and
data timing for an entire time slot of data. A closer look
at the timing functions is given in Figure 11 which
looks specifically at the first clock cycle after the transmit data enable FSx.
According to the 29i3/14 data sheet, the fram~ sync/
data enable fSx must. precede the clock (DCLKx) by
at ICllllt T tsdx or nominally 1~ ns for that clock pulse to
be recognized as the first clock pulse in the time slot. In
actuality, the 2914 will allow FSx to lag up to 80 ns the
DCLKx rising ~ge and recognize it as the first clock
pulse in a 2.048 MHz system.
3.0 OPERATING MODES
There are three basic operating modes'that are supported by the 291~/14: fixed data rate timing (FDRT), variable data rate timing (VDRT), and on-line testing.
3.1 Fixed Data R',t~ Mode
On'1c FSx has reached VIH of about 2V, the Dx output
The FORT mode is described in some detail in both
section 2.2 of this note and in the 2913/14 data sheet.
In addition, Intel Application Note AP-64 (Data Con-
will remain in the tii-state high-impedance mode for
6-99
AP·142
'Transmit Timing
210314-17
'Receive Timing
210314-18
NOTE:
All timing parameters referenced to VIH and VIL except tOON and klFF whiph reference a high impedance state.
Figure 10. Variable Data Rate Timing for an Entire Time Slot
Tdon or about 34 ns longer. It then comes out of tristate
and will represent some data which is invalid until the
valid data is available TDDX or about 75 ns (100 ns
worst case) after the clock rising edge. This means there
is about 90 ns of invalid data after the tri-state mode.
At this point there is valid data on the Dx highway
that lasts for approximately one full clock cycle.
Since the Dx highway is tied directly to the Dr highway in digital loopback, the valid data above is now
available to the receive channel with some propagatibn
delay. The receiver is only interested in the data for
about a 50 ns (110 ns worst case) window centered
about the falling edge of the DCLKr clock which occurs about half a clock cycle from the FSr rising edge.
The window width is equal to the data set-up time.
Tdsr, plus the clock fall time, Te, plus the data hold
time, T dhr. Information at any other time, on the Dr
highway falls into the DON'T CARE category.
Retrofitting the 2913/14-Severa1 switching/transmission systems have been designed using first-generation
codecs which operate at data rates from 64 Kbps to
2.048 MBps. In addition, they may 'have been designed
using the rising clock edges for both transmit and receive data.
Other aspects of these older designs could be relative
skewing between the sync pulses (Data Enable) and the
clock pulses in such a way that the. sync pulse occurs
after (Lags) the first clock pulse rising edge. All of these
conditions can be easily handled using the variable data
rate timing mode of the 2913/14 plus some simple externallogic. By the addition of this logic, the 2913/14
becomes transparent to the older deSign thereby allowing an upgrade in performance while having no impact
on backplane wiring or on system control hardware/
software. In addition, many of the features of the
2913/14 may be incorporated, such as the test modes,
which provide additional capabilities beyond those
available in the' original design and at a lower cost.
The circuit diagram in Figure 12 shows the maximum
amount of additional random logic that could be necessary to make the 2913 or 2914 completely transparent
at the linecard level (no im:pact on backplane wiring or
timing). The inverter on DCtKR inverts all the receive
clocks for each linecard. This inverter is only needed if
(1) the transmit and receive clocks are inverted at the
system/backplane level (as opposed to the linecard level) and (2) $e previous design used only rising (or falling) edgeS to clock the transmit/receive data.
6-100
inter
AP-142
DIGITAL LOOP BACK
VARIABLE DATA RATI! MODI!
Fix,.....
2::Iv - -
-;f('"
~JI
Ttadll=15 nHe
-IlI 1,,-----I
DCLK..,
I I
1,,-,/TdeI.=100 nHe I
~ ,.?~
I
~~~I~lnlr-------~I-+------------~
1
I
D.
TRI·STATE
MODE
7
I
I
I
I
1
!.-
TRANSMIT DATA VALID
I
I
I
I
Tdon2:35 nHe I
I
DON'T
CARE
Dr
I'
I
I RECEIVE DATA
1
Dr
Trdo-50nHe
(SETUP TIME)
210314-19
Figure 11. Waveform Timing Diagrams for the 2913/14
3.3 On-Line Test Modes
4.1 DeSign/Prototype Testing
Two modes are available which permit maintenance
checking of the linecard up to the SLIC/combochip
interface, including the PCM highways and time slot
interchanges. Tests include time slot-dependent error
checking. The two test modes are called "redundancy
testing" and "analog loopback." These test modes are
described in detail in Section 4.3.
In the design of a linecard prototype or in the qualification of a device, it is often helpful to have direct access
to the internal nodes at key points in the LSI system.
Some manufacturers even dedicate pins specifically for
this function. The Intel 2913/14 approach was to reduce cost by using multifunction pins and smaller packages to achieve this goal. Measurements through these
multipurpose pins will typically yield full device capability against performance specifications, however these
measurements are not included in the device specifications. This is done for two reasons: first, to save manufacturing cost by eliminating unnecessary tests and
specifications, and, second, more cost effective manufacturing test techniques are available, as discussed in
section 4.2.
4.0 MULTIMODE TEST CAPABILITIES
The 2913/14 was designed with every phase of design,
manufacturing, and operation taken into consideration.
In particular, several test modes have been implement·
ed within the device with essentially no increase in the
package size or pin count. These test modes fall into
three categories: design/prototype tests, manufacturing
tests, and on-line operation tests; see Table 8.
6-101
inter
AP-142
2913 HOOKUP
2914 HOOKUP
VBB
VBB
PWRO+
PWRO-
GSR
4
PDN
CLKSEL• L
,..-DClKR-{
DRC
FSR-(
GRDD [
7
8
9
10
-
VCC
GSx
VFXIVFXI+
GRDA
1-'.ASEl
14 !=J-i'SX/DClKX13pDX
12 P.FSX 11 ClKx
1
PWRO-
21
GSR
2914
SIGR L. 8
,DelKR-£:
DR C
r--FSR-£:
GRDDC
P
9
10
11
12
VCC
GSx
VFXIVFXI+
GRDA
NC
SIGX/ASEl
17 f-/"'i'S XIDClK X18pDX
ISP.FSX U pClKX
13
ClKR
P
I
I
I
DClKR
I
I
.'1.
, ...
I
~
TSXI
I
TSRI
210314-20
NOTE:
(1) One inverter per linecard.
Figure 12. Circuit Diagram Showing Connections Needed to Retrofit the 2913/14
into Existing Variable Data Rate Systems
Transmit Coded (Encoder)-The transmit filter can be
bypassed by directly accessing the differential input of
the transmit encoder with an analog differential drive
signal. Table 9 shows the control pin voltages and the
input pins for this test. This test mode permits DC testing of the encoder which is otherwise blocked by the
AC coupling (low frequency reject filter) of the transmit filter.
Table 8. Multimode Testing for Each Level from
Design to On-Line Operation
• Design/Prototype Testing
- Direct access to transmit codec inputs
- Direct access to the receive filter input
and the transmit filter differential outputs
Transmit and Receiver Filter-Table 9 shows the control values that permit access to the differential' outputs
of the transmit filter and the single-ended input to the
receive filter. The voltage difference between the transmit filter outputs represents the filtered output that will
be encoded. By driving VFxI (single ended or differentially), the transmit filter response is obtained as a differential output. The final stage is the 60 Hz reject filter
which is a switched capacitor filter sampled at an
8 KHz rate. When measured digitally (after the encoder), the filter characteristic is obtained directly: however, when measured in analog, a sin (CJ)T/2)/CJ)T/2 correction factor must be included.
• Manufacturing Tests
- Standard half channel tests for combined codec/filters
- Filter response half channel measurements,
• Operation On-Line Tests
- Analog loopback for testing PCM and
codec analog highways
- Redundancy checks with repeatable
DX outputs
Table 9 gives the input control pin values and the corresponding functions assigned to the key test pins on the
2914 for the design test modes.
6-102
Ap-142
Table 9. 2914 Te.t Function. and Control Input. for the Design Test Mod••
Input
Pin Function (24-Pln)
Teat
Function
PDN
DR
Pin 9
DCLKR
Pin 17
TSx/DCLKx
Pin 18
SIGx/ASEL
O-Vee
O-Vee
DCLKR
TSx/DCLKx
SIGx/ASEL
Normal Operation
Vee
O-Vee
-
+VFX
-VFX
Encoder
O-Vee
Vee
VFRI
+VFXO
-VFXO
RCV, XMIT Filter
NOTES:
The terms used above are deflnad as:
±VFX ,. Encoder Input
± VFXO = XMIT Filter Output
VFRI = RCV Filter Input
The input to the receive filter nrst passes through a
sample and hold. This is necessary to simulate the
sin (ClIT/2)/ClIT/2 characteristic that results from the
decoder D/A output. The net result is a filter characteristic that can be compared directly to the specincations.
Start-up Procedure for Test Modes-To place the
2913/14 in the test mode it is first necessary to operate
the deviCe for a few ms in normal operation. Then vim
can be applied to the control pins to select the desired
test access.
4.2 Production Testing
While it may be convenient for the designer to have
access to both the niter and the codec inputs and outputs during the design or evaluation phase the nnaI
product will always use the filter and codec circuits
together with all signals passing through both on the
way to or from the PCM highways. It therefore makes
sense to perform all manufacturing measurements with
the device configured in its normal operating mode, i.e.,
all measurements should be complete nlter/codec half
channel measurements. This approach not only tests
the combo as it will actually be used, but also saves
time and money by eliminating separate measurements
and correlation exercises to determine the full half
channel performance.
Since the transmission specincations of SID, gain
tracking, and ICN all require measurements which are
"in-band" or "filter independent," the codec functions
can be easily tested using conventional half channel
measurement equipment. The apparent difficulty arises
in trying to fully measure the filter characteristics beyond the half sampling frequency of 4 KHz. In fact,
this- is not really a problem with today's computerbased testing plus an understanding of the sampled data
process which is discussed under "FUter Testing".
ENCODER/DECODER TESTING
Transmission specifications are AC-coupled in-band
measurements when using either CCITT G.712.11
methods 1 & 2 (white noise testing and sinusoidal testing, respectively) or AT&T Pub 43801 (Sinusoidal
Testirig). The noise testing uses a narrowband of flat
noise from 300 to 500 Hz to drive the filter/codec (either in aruilog or the equivalent digital sequence for the
transmit/receive channels, respectively). The resulting
harmonic products are used to determine SID. Likewise, gain tracking is also determined from this signal
input. Sinusoidal testing uses a tone at 1.020 KHz for
SID measurements and gain tJ:acking measurements.
Idle channel noise measurements require the combined
filter/codec since it has long been shown that separate
measurements of filters and codecs are difficult to relate
to the combined measurement (usually there is no specinc relationship because of the non-linear properties of
the encoder/deCoder operations). Typically the frequency response of ICN measurements is primarily determined by the weighting filter (either C message or
psophometric, which are both AC-coupled, bandpass
type filters).
The conclusion is that combined filter/codec testing in
no way limits the measurement of half channel transmission parameters of SID, G.T., or ICN.
FILTER TESTING
Testing the filter response, of the transmit and receive
channels presents two separate test situations which, in
some ways, are mirror images of one another. With the
transmit side, signals may be introduced at any frequency to test the filter response. At the output of the
filter, the resulting signals are sampled at 8 KHz and
digitized resulting in a sequence of PCM words representing the samples of filtered input signal. On, the receive Side, a digital PCM sequence of samples representing the driving signal is converted to an analog signal by the decoder and can be measured at the filter
output in analog form.
.
6-103
AP-142
Sampling Process-In both cases, of testing the filter,
the signal eventually is in a sampled form. Since the
sampling rate is fixed at S KHz, all signals must be
represented below 4 KHz (half the sampling frequency). This means that the PCM bit stream can only represent signals at frequencies below 4 KHz. If a signal
above 4 KHz is 'sampled, those samples appear exactly
as if the signal was at a frequency ,mirror imaged about
4 KHz. Two examples include signals at 5 KHz and
7 KHz which will result in samples that look like signals of 5-S KHz = 3 KHz and 7-S KHz = 1 KHz,
respectively.
Conversely, the sampling process produces replicas (aliasing) of the sampled signal around multiples of the
sampling frequency. Therefore, if two signals are introduced digitally representing 1 KHz and 2 KHz, there
will also be frequency components located at S KHz =
± I KHz and S KHz = ± 2 KHz, and so on for all
multiples of S KHz. Thus it is possible to generate frequencies at arbitrary values after sampling by controlling the frequency of each signal within the 4 KHz input band regardless of whether it is in analog or PCM.
When an analog signal is sampled, the frequency components generated are all of the same amplitude as the
corresponding input spectral components. Therefore,
on the transmit side, measurements made from the
PCM data will' have a throughput gain of unity except
where components are superimposed (e.g., a 4 KHz input signal will have -an alias component at 4 KHz
which may double the amplitude at 4 KHz when the
two components are combined).
are generated to determine spectral frequencies and amplitudes at the codec output, or (2) use an "ideal" D/A
converter on the PCM samples to convert the digital
data back to analog so that the spectral amplitudes and
frequencies can be determied using analog circUits such
as spectrum analyzers or filter banks. In either case, the
effects of sampling will be the same. Figure 13 shows
two spectral diagrams of amplitude versus frequency.
The top diagram represents the locations of nine test
frequencies corresponding to the seven specified frequencies in the 2913/14 data sheet plus a component at
7 KHz and one at 10 KHz. The bottom figure shows
the "equivalent" spectral component locations when
carried in the PCM bit stream. As an example, frequency "S is located at 7 KHz. The corresponding PCM
frequency is seen in the lower figure at 1 KHz. Note
also that the analog component at 9 KHz (see "S·)
would also generate the I KHz component in the PCM
data.
To test the filter, the desired test frequencies are introduced in analog to the filter input in such a way that
there is no confusion as to where the resulting component will be after sampling (Le., don't simultaneously
put in 1 KHz and 7 KHz since both of the,se il1puts
result in a 1 KHz component in the PCM data). Then,
using either technique (FFT or analog) mentioned
above, measure the amplitude of the corresponding
When an analog signal is reconstructed from digital
samples, it goes through a sample and hold stage which
has the effect of imposing'll weighting function on the
resulting spectral components that ,is represented by
smo
o
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210314-21
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sI'CLlNK2. GNr:'I'XGVR, XCVRCBL·5
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PO.DOSRBIRO
RI~llll'st Block l)evelopcr's Software
with iNA 961 for PCLlNK2
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IBM PC LAN
sPCLlNK2TWKIT
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FLEXIBLE AND HIGH")'
CONFIGIlIlABLE
1\-\ 960 IS a mature, ne\ible .. and read~'lo·ust' software
bUilding block for Og~1 suppliers of networ~ed systems for
both manufacturing and office applications (e.g .. ~I:\P
rfacffi. RS232C and
RS-l22·VRS449 ('()mp..1tlhll'
•
6 MHz 8()IR6 mll'rupnJ('l'lAAII'
•
128" Ii~tl'~ uf duul'purt K,\M c'xllltndableo
un·board tu 2561\ b~ll's
• Slx'kc'ls lilr up to 1921-: b)tffi of JRDEC
28·pin mandant mc'mnr~ drvlrt'S
• PntdlK't (''(Kt(~ SS1lC186:' I
1SII~ISXIfl'·
lJlJllti IfIIJ£rIBIJS I
IEEE 8,,11. :lIEr.EIINEr NEr,"",,, INI'EB.,.tI~E tlIMPI'EB.
CPU .. .. .. ... .... .. .......................80186 (8 MHz)
LAN Coprocessor. . .
. ..............82586
RAM (Bytes) . . . . . . . . . . . . . . . . . .
. ...............256K
EPROM (Bytes) . . . . . . . . .
. . .. 128K (27512), 16K (2764)
MULTI BUS'" Address . . . . . . . . . . . . . . . . . .. Any 64 KB boundary.
with a 16 MB address space
Software Support .. .. .. .. .. .. .. ... ... .... ... .iNA 9601961
Power ReqUirements + 5V . . . ... . .. .. .. .............6,2 A
+12V ............................O.SA
• HIgh f'torforman('t' IEE~: 8112.:lIl·;ttwrJll't
compatiblt' nf't\lnrk fnmt-end pnl('('ssClr
• Residl'm n('l\lork soft\lal'l' ran bc' dnwn·
loadl'd Cl\l'I' IhI' bus ur thl' LAN
• On·hoard diagnClstir and txXlt flrmW81'l'
• ISXM'" 552·\ versccm is a prrcnnflgurl'cl
controller [or executing iNA 961 (ISO 8073
Transport and ISO 8473 'IIet\\urk
soft\lare) In System 310 and 320 family
pntducts
• Product Qxje: pSBC552A. pSXM552A
7-11
1F>1Rl~ILD~D~~~IPl'jf
MIJLTIBIJS@I1 ,Ope.NETTli ~,ETWORK~NG "ARDWARE
I
ISBt;e IB61lJ30 ItIIff,TIBlfse"
IEEE BO:l. 31ETIIEIlNEI' NETWOIll( INTEIlP,4(JE ,4B4,.."EIl
• PrOl ides Ethrrl1t't(!) (lg~:~: 1102.3)
compatlhll' net\\orkmg capahihty lill' all
\lL'I:rnWS"'1I systems
•
CPU ....... , ..... , .. , , , ,. ....., ......••••..80186 (8 MHz)
DRAM ............................ , ........ 512 KB on-board '
EPROM .... , ......... 4 28-pln JEDEC s~es,up to 256 KB (max.)
using 27512 devices. up to 512 KB (tolal) using'iSBce 341 module'
Ethernet 110 .........................1 channel 15-pin q:>nnector
Controller.. .. . .. . . . .. " ....... 82586 LAN Coprocessor
Serial 1/0 . . . . . . . . . .
. . . .. 1 channel RS232C, 15-pin connector
Controller.... , ............... " ...................•8031
Leads Supported.
. ... '. . .............. TO, RD
Timers ....................... " ....................... '.3
Interrupts. .........
5 levels with 5 on-board sources
and 255 sources from iPSB Bus
Power Requirements + 5V . . . . .
.8 8 A (excludes power for
user-installed memory devices)
+12V
, ...•....... SOmA
-12V ... .
.. .............SOmA
\ll'LTlBlIS"'1I IPSB (parallel SysU'm Bus)
Interlac/' wlt,h full M('SS8/.W Passing
rapahlht~
• Kl'SIUl'JIt Ilrmwa!'/' to support, RUilt -m-Sell·
Test (BlST) pO\\l'r-up dlagnosl.I{·s. ann hll$t·
to-controller softwarr download
• ~hur 28-1.1111 JEDf:C SIIffi. expanuahle to 8
Sites \\Ith ISBC'" 341 MlIl:rIMODlIL~:iII) for
a 1lI!l\lmum of r, 121\ hylffi of EPROM
• Provldl'S onl' KS232C serra I port fol' ust' III
drhug and Iffitmg
• Product CAlde: pSBCI1l6530
PC HilS OpenNETTli NETWORKING "ARD,WARE
PtJ £INI(:I NETWOIlK INTEIlP,4(JE ,4B4,.."EIl (PtJ UNI(:I NI,4)
CPU. .. .. .. .. .. . .. . . ' " .................80186 (8 MHz)
LAN Communications Controlier .. . . . . . . . • . . .. . ... .' ... ,82586
Ethernet Interface. .. . .....15-pln connector. 82501 serial interface
DRAM 256 KB (dual-port), 0 wait-state memory access by the CPU
EPROM ................... , ........................16 KB
Size ...................... "., ......... 4.15 In H x13.3 in W
Power Requirements + 5V
.. . ........... ,... . .. 2.0, A
+12V .', .........................0.5 A
• Intelligent high performanCt' hardw81't' with
on-hoard nllcroproct'Ssor, 16K bytes
EPROM and 256K b~tes RAM.
• Full slot PC AT. PC XT (or compatihle
computer system) board
• 80186 microprocessor, 82586 LA~
coprocessor. 8 MHz zero-walt-state
memory access.
• ~A \I ~hlll't~1 h) tht' PC host and PC I.II1k2 hOllrd \ ra an 8/1: memory
windo\\.
• ,Iumlx'r st'I(~'lInn for ~:lIll'rm1
•
~;rf('('tl\l'
st'lf drallnOslI(·s.
• Pl'tllJU('t nKIl': sI'CI.I\I..2NI·\
7·12
()f'
II':~:~:
B()2.:l
,---_ _ _ _ _ _ _~=_=:_:_::_:_:_-------..,~a=ilIEU~UINl~IRlW
OpeaNET™ NETWORKING ACCESSORIES I
ISBX'" (JBB IM'I'II UN" ENGINE /fIll£'I'IItIODll£E~ BOIIIlD
LAN Coprocessor
....... - . , , .. - .. , ..... , .. ,82586 (8 MHz)
RAM (Bytes) .
. .. .................. . ...16K (dual-port)
Software Support
........................ .iNA 960/961
Power Requirements +5V.
.2.0 A
+12V...........
.. ...lOA
•
•
Pr()\ Ides an IEEE 802 3/Eth('rnt't
compatible connertioll for 8086 and
801H6-based host boards OWl' a 16-IIiL
iSBX" mtcrfarp
• 011111':1111111' 111111 1\ \ Il!iOl!)(il ISO H07:l Tl'1Inspurl und ISO 8473
NI'\llol'k sollllat'l'
Singlt'-lIld(' ISBX'" MliLTIMOf)l'I.W·
•
I'I'OIl(it'S all 11,:10:10: 1102 :llo 1~:Io:I': H02. t ~outt'r ('a)labllit\ II ht'n UM\'d
willi 11I"ISBe'" ~~ 111o:1·:E H02.1 L \\ (111111'H1I('1'
-
•
1'1'011111'1 Clld." sSB\'iBti
ID(]/fl fJlI-IIN'I'EUlNIr" I'tlN-fJll'l' llN.'I'
Size ..... , , . . . . . . . . . . . . . . .. .. 14 in W x 7 8 in H x 5.5 in D
Power Requirements ........... .100n20/220/240 VAC, 47-64 Hz
• Connecls up to nmp Rtht'rnt't mmpatihlt'
lIorkstatlons without !.II(' "t\'dlo!'
tranSl't'lIers or maxial cablc
•
•
Casl':!d"III.' 10 ~III'IHIII II-HI IlIlIblolltllll'
•
I'I"HIIII'I (Jill!- I'IlC\1!1\ II
Connt\'ts dll'l.'('ll~ to thl' ~:tht'l'n('t ('mlxrul
('able through a stanclard tranSt\'lwr ('ubll'
E'I'HEIlNE'I'/'EEE BOZ.3 .,"'N-W'IlI: 'I'lltiNSCI:• .,,:1l
Size
..
Power Requirements + 12V
(from transceIver cable)
•
DiN'asl metal cast' for protection. I'('du('('d
E\11. and efftclent heat dissipation
•
IAlII mrush current at pOIlt'r-up. auto
shutd()\1 n II hen IOII-mput lultage OCCUl'S.
and surge protection
•
IE~:g 1l()2.3-compllant. Ethernet V1.0/\,20
2 81n x3.6 in. x3.8 in
.375mA
•
Th"~'I.~:lls 1Ill1llilol' pmll'l' ~lalll~ p:lckl'l mllisions and sl~nal qllullt~
•
Rt'mOlallll' B\C I~IK' (ahlt, IiiI'
•
llsl'r-mnl'lglll'alllt' lill'us(' 11111101' 1IIIII0UIIlI'ilI'Ihl'at
•
Pl'tJdllct eml(' C\I-:'I'\C\ ~
compatible
7-13
OJteaNETTII NETWORKING ORDERING IN'ORItlATION
R.IINET
RIIllUNIT
IRMX-NET for IRMX 86 operating system
IRMX-'lET for iRMX II operating system
ePClUNKIMA
ePClUNKl
ePClUNKIlBD
I'C Llnk2 Network lnl.erfHCt' i\dllllLl,' lIurdwul'l' Olily
Seven-layer Solution with sPCLINI\2NIi\, iNi\96I, NI'tBlOS intl'r£8C(', M8-NET
five-layer Solutkm with sPCLIJl.II.2J1.Ii\, iNA!J6I, Nt'tBIOS intl'r.l'at\'
Seven· layer Thln-wlI~ Solutkm with sPCLlN"2, CN~m\(''VR, )lCVRCBL·[j
NetBIOS Dt'VClopcr's Kit wiUI 2-sPCLlN"2CN~:'I'''I'I'l1, NI'tBI(X:; programml'r kit
R(~IUl:Mt BIIX:k Dt~:IOIK:r'll SOnWII1\' with INA 061 fur PCI,I'II"2
RlI)alty fee for I'CI.DOSDRBIRO
INA!J61 WI to R2 migration I!lJftWUI'l: for 1'(; I,Ilk Hlld RI to W3 COl' 1'<: 1,lIIk2
Royalty fee for PCLNKSWlJl'RO
.raJNKZnIUT
III'CI.INUDEWKIT
I'CLDOSII_.
rc:tD08IlBIRF
I'CmUWIlP.
PCUlUWIlPRF
t'.4X/t'BS o,.eaNI:'I' PllflDIIfl'l'S
Jl.l'tworking SoI'twal'l" for VAX family
WIlMET
\(bJUVMS Networking Software for MlcnJVAX II
IIIWIIIMIT
"NIX SI'S'IDI t' OJINNE'I' .....IIflFS
U:-lIX SV.()penNET with iSBC 552A on MULTIBUS I
SWNITSSZA
UNIX SV-openNET with iSBC 186/530 on MlILTIBUS II
SWNIT1I30
III,,"ITZ 1
IIIAPNITZ 1RF
IIIAPZ 1SliM.
IIIAPZISIM.,
SllCSII41
SKSS43
Umfigurable ISOIOSI Layen; 5 throul!h 7 of tilt, Mi\1'2.1
Royalty fet:' for MAPNET21
Pl'Ct:'Onfigured ISOIOSI Layt'l'S 3 thl'llUllh 7 of tlx' Mi\P2.I, in!'lUlk'S license
Ro~alty fet:' for MAP21SXM
iSBC554-1 MULTIBUS I MAP Communiration~ ~:ngil1l'. Xmit: CII 3', 4' Rev: CII P. 0
ISHC554·3 Ml!I,TIBlJS I MAP Commumratf(m~ ~:Illllnl', )lmit: C1I6', ~'M I' Rev: CH T. U
1N.4 __ O".,aNE'I' 1S010SI .....1Jflrs
INA......
INA..HIII'
1801001 Transport and Network layen;. Inclum's iNA!l61
Royalty fee for INA960
B"U'1IIflS • .4NIJ B"£I'II111S " IEEE 802. 3/E'1'11E1lNE'I' PIlOIIiJIJFS
88IM:la.llt
J8BCSSZ.t
,sllIllSSZ.t
,sIlCI . . 53.
ISBC 186/51 MULTIBUS IIE~:~: 802.31Ethernet \AJIIlmuniration ('Almputrr
iSBC 552i\ MULTI BUS I IEEE B02.3lEtIlernet Network Intrr\'8C(' A~apter
ISBC 552A preconfigured for Intel System 310 and 320, inrludt'll iNA 961 royalty
iSBC 186/530 MULTIBUS II IEEE B02.31Ethernt't Nt'twork 1ntt'r£aCt' Adapter
ISBX 586 MUI:r1MODUI,Fo IFoFoFo 802.3iELhcrnct Data I,lnk board
IDCM 911·1 Intellink Pan-olt Unit
Thin-wire transrelver. Requires transreiver cablt' (XCVRCHI..5)
five-foot transceiver cable
7·14
I
OpenNETTM NETWORKING LITERi\TlJRE
--------~------------
Ik'lKrlpU.D
IRMX-NE'l' OpeRNE'l' PRODIlC'l'S
IRMX·I\ET Software Rfleosc 3.0 Installation and Configuration CUIlecute the application and networking software written in higher-level
languages.
'
Self Clocking Polnt-to-Polnt Interface
The iSBC 88/45 ADCP board is used in an asynchronous mode interface when configured as shown
in Figure' 4. The point-to-point RS232C example
uses the self-clocking mode interface for NRZI encoding/decoding of data. The digital phase-lock'
loop allows operation of the interface in either halfduplex or full/duplex implementation with or without
modems.
CONNECTOR
J1 J2 OR J3
ToC
ToO
RTS
,SBC' Hl4S CTS
BOARD RoC
RoD
DTR
DSR
BOARD
This architectural support includes four 16-bit byte
addressable data registers, two 16-bit memory base
pointer registers and two 16-bit index registers.
These registers are addressable through 24 different
operand addressing modes for comprehensive
memory addressing and for high-level language data
structure manipulation.
The stack-oriented architecture readily supports
Intel's iRMX executives and iMMX multiprocessing
software. Both software packages are designed for
modular application programming. Facilitating the
fast inter-module communications, the 4-byte instruction queue supports program constructs needed for real-time systems.
CONNECTOR
J1 J2 OR J3
RoC
RoD
RTS
CTS ,sac "'4$
hC BOARD
Since programs are segmented between pure procedure and data, four segment registers (code,
stack, data, extra) are available for addressing 1
megabyte of memory space. These registers contain
the offset values used to address a 64K byte segment. The registers are controlled explicitly through
program control or implicitly by high-level language
functions and instructions.
210372-5
Figure 4. SelfooClocklng or Asynchronous Pointto-Point Modem Interface Configuration
Example-RS232C
Synchronous Polnt-to-Polnt Interface
The real-time system software can also utilize the
programmable timers as shown in Table 2 and various interrupt control modes available on the ADCP
board to have responsive and effective application
solutions.
Figure 5 shows a synchronous pOint-to-point mode
of operation for the ISBC 88/45 ADCP board. This
RS232C example uses a modem to generate the
receive clock for coordination of the data transfer.
The iSBC 88/45 ADCP board generates the transmit
synchronizing clock for synchronous trans"!ission.
Table 2. Programmable Timer Functions
Function
CONNECTOR
J1, J2 OR J3
RTS
eTS
ISBC' 1110 ToO
BOARD RoD
DTR
DSR
CONNECTOR
, J1, J2 OR J3
Operation
CTS
RoD ,SBC' 11'45
ToO BOARD
Interrupt on Terminal An interrupt is generated on
Count
terminal count being reached.
This function Is useful for
generation of real-time
clocks.
DSR
DTR
Rate Generator
Divide by N counter. Based
on the input clock period, the
output pulse remains low until
the count is expired.
Square Wave
Generator
Output remains high for onehalf the count, goes low for
the remainder of the count.
Software Triggered
Strobe
Output remains high until
count expires, then goes low
for one clock period.
210372-6
Figure 5. Synchronous Polnt-to-Polnt Modem
Interface Configuration Example-RS232C
Central Processing Unit
The central processor for the iSBC 88/45 Advanced
Data Communications Processor board Is Intel's
iAPX 8088 microprocessor operating at 8 MHz. The
microprocessor interface to other functions is illustrated In Figure 6. The microprocessor arc,hitec-
8-4
inter
ISBCGI> 88/45 BOARD
Numeric Data Processor Extension
Interrupt Capability
The 8088 instruction set includes 8-bit and 16-bit
signed and unsigned arithmetic operators for binary,
BCD, and unpacked ASCII data. For enhanced numerics processing capability, the iSBC 337 MULTIMODULE Numeric Data Processor extends the
8088 architecture and data set.
The iSBC 88/45 ADCP board provides nine vectored interrupt levels. The highest level is the NMI
(Non-Maskable Interrupt) line. The additional eight
interrupt levels are vectored via the Intel 8259A Programmable Interrupt Controller (PIC). As shown in
Table 3, four priority processing modes are available
to match interrupt servicing requirements. These
modes and priority assignments are dynamically
configurable by the system software.
The extended numerics capability includes over 60
numeiic instructions offering arithmetic, trigonometric, transcendental, logarithmic, and exponential instructions. Many math-oriented applications utilize
the 16-, 32-, and 64-bit integer, 32- and 64-bit floating point, 18-digit packed BCD, and 80-bit temporary
data types.
Table 3. Programmable Interrupt Modes
Operation
Mode
16K Bytes Static Ram
The iSBC 88/45 ADCP board contains 16K bytes of
high-speed static RAM, with 12K bytes dual-ported
which is addressable from other MULTIBUS devices. When coupled with the high-speed DMA capability of the iSBC 88/45 ADCP board, the dual-ported
memory provides effective data communication buffers. The dual-ported memory is useful for interprocessor message transfers.
Nested
Interrupt request line priorities
fixed; interrupt 0 is the highest
and 7 is the lowest.
Auto-Rotating
The interrupt priority rotates;
once an interrupt is serviced it
becomes the lowest priority.
Specific Priority
System software assigns
lowest level priority. The other
levels are sequenced based on
the level assigned.
Polled
System software examines
priority interrupt via interrupt
status register.
EPROM
14K InES
IOUL_
ADDIIIIUIITI
ADflt.'·ADIIJt1
CHANNEL C
ICONNECTOR J1l
210372-7
Figure 8. Block Diagram of the ISBCIt 88/45 ADCP Board
8-5
ISBC@ 88/45 BOARD
In addition to specialized or custqm, designed iSBX
boards, the customer has a broad range of Intel
iSBC MULTIMOOULEs available, including parallel
I/O, analog I/O, iEEE 488 GPIB, floppy disk, magnetic bubbles, video, and serial I/O boards.
Interrupt Request Generation
Listed in Table 4 are the devices and functions supported by interrupts on the iSBC 88/45 AOCP board.
All interrupt signals are brought to the interFupt jumper matrix. Any of the 23 interrupt sources are
strapped to the appropriate 8259A PIC request level.
The PIC resolves requests according to the software
selected mode and, if the interrupt is unmasked, issues an interrupt to the CPU.
The serial I/O MULTIMOOULE board~' include the
iSBX 351 (one ASYNC/SYNC serial channel) the
iSBX 352 (one HOLC/SOLC serial channel) and the
iSBX 354 (two SYNC/ ASYNC, HOLC/SOLC serial
channels) boards. Adding two iSBX 352 MULTIMODULE boards to the iSBC 88/45 AOCP provides
a total of five HOLC/SOLC channels.
EPROM/RAM Expansion
In addition to the 9n-board RAM, the iSBC 88/45
AOCP board provides four 28-pin JEOEC sockets for
EPROM expansion. By using 2764 EPROMs, the
board has 32K bytes of program storage. Three of
the JEOEC standard sockets also support byte-wide
static RAMs or iRAMs; using 8K x 8 static RAMs
provides an additional 24K bytes of RAM.
MULTIBUS® Multimaster Capabilities
OVERVIEW
The MULTIBUS system is Intel's industry standard
microcomputer bus structure. Both' 8- and 16-bit single board computers are supported on the MULTIBUS structure' with 24 address and 1G data lines. In
addition to expanding functions contained on a single board computer (e.g., memory and digital I/O),
the MULTIBUS structure allows very powerful distributed processing configurations with multiple
processors, intelligent slaves, and peripheral
boards.
Inserting the optional iSBC341 MULTIMOOULE
EPROM expansion board onto the iSBC 88/45
AOCP board provides four additional 28-pin JEOEC
sites. This expansion doubles the available program
storage or extends the RAM capability by 32K bytes.
ISBXTM MULTIMODU,LETM Expansion
Two 8-bit iSBX MULTIMOOULE connectors are provided on the iSBC 88/45 microcomputer. Through
these connectors, additional iSBX functions extend
the I/O capability of the microcomputer. The iSBX
connectors provide the necessary signals to inter"
face to the local bus.
Multimaster Capability
The iSBC 88/45 AOCP board provides full MULTIBUS arbitration control logic. This con,trol
Table 4. Interrupt Request Sources
Device
Function
No. of
Interrupts
MULTIBUS Interface
Select 1 interrupt from MULTIBUS resident peripherals
or other CPU boards.
8
8273 HOLC/SOLC
Controller
Transmit buffer empty and receive buffer full
2
8274 HOLC/SOLC
SYNC/ ASYNC Controller
Software examines register for status of communication
operation
1
8254-Timer
Counter 2 of both PIT devices
2
iSBX Connectors
Function determined by iSBX MULTIMOOULE Board
(2 interrupts per socket)
4
Bus Fail Safe Timer
Indicates MULTIBUS addressed device has not
responded to command within 4 msec
1
Power Une Clock
Source of 60 MHz signal from power supply
1
Bus Flag Interrupt
Flag interrupt in byte location 1000H signals board reset
or data handling request
2
iSBC 337A Board
Numeric Data Processor generated status information
1
8237A-5
Signals end of 8237 OMA operation
1
-
8-6
iSBC® 88/45 BOARD
logic allows up to three iSBC 88/45 ADCP boards or
other bus masters, including iSBC 286, iSBC 86 and
iSBC 86 family boards to share the system bus using
a serial (daisy chain) priority scheme. By using an
external parallel priority decoder, the MULTIBUS
system bus could be shared among sixteen masters.
to support assembler, PLlM, PASCAL, and FORTRAN software development environments. The
modular building block software lends itself well to
customized application solutions.
SPECIFICATIONS
The Intel standard MULTIBUS Interprocessor Protocol (MIP) software, implemented as the Intel iMMX
800 package for iRMX 86 and iRMX 88 Real-Time
Executives, fully supports multiple 8- and 16-bit distributed processor functions. The software manages
the message passing protocol between microprocessors.
Word Size
Instruction: 8, 16, 24, or 32 bits
Data: 8 or 16 bits
System Clock
8 MHz: ±0.1%
System Development Capabilities
NOTE:
The application development cycle for an iSBC
88/45 ADCP board is reduced and simplified
through the usage of several Intel tools. The tools
include the Intellec Series Microcomputer Development System, the ICE-88 In-Circuit Emulator, the
iSDM 86 debug monitor software, and the iRMX 86
and iRMX 88 run-time support packages.
Jumper selectable for 4 MHz operation with iSBC
337 Numeric Data Processor module or ICE-88
product.
Cycle Time
Basic Instruction Cycle at 8.00 MHz: 1.25 JLS, 250 ns
(assumes instruction in the queue)
The Intellec Series Microcomputer Development
System offers a complete development environment
for the iSBC 88/45 software. In addition to the operating system, assembler, utilities and application debugger features provided with the system, the user
optionally can utilize higher-level languages like
PL/M, PASCAL, and FORTRAN.
NOTE:
Basic instruction cycle is defined as the fastest instruction time (i.e., two clock cycles).
Memory Cycle Time
The ICE-88 In-Circuit Emulator provides a link between the Intellec system and the target iSBC
88/45-based system for code loading and execution. The ICE-88 package assists the developer with
the debugging and system integrating processes.
RAM: 500 ns (no wait states)
EPROM: jumper selectable from 500 ns to 625 ns.
On-Board RAM·
KBytes
Run-Time Building Blocks
16 (total)
12 (dual-ported)
Intel offers run-time foundation software to support
applications which range from general purpose to
high-performance solutions. The iRMX 88 Real-time
Multitasking Executive provides a multitasking structure which includes task scheduling, task management, intertask communications, and interrupt servicing for high-performance applications. The highly
configurable modules make the system tailoring job
easier whether one uses the compact executive or
the complete executive with its variety of peripheral
devices supported.
Hex Address
Range
00OO-3FFF
1000-3FFF
"Four ISSC 88/45 EPROM sockets support JEDEC 24/28·
pin standard EPROMs and RAMs (3 sockets); iSBC 341 (4
sockets)
Environmental Characteristics
Temperature: O·C to + 55·C, free moving air across
the base board and MULTIMODULE board
Humidity: 90%, non-condensing
The iRMX 86 Operating System provides a very rich
set of features and options to support sophisticated
applications solutions. In addition to supporting realtime requirements, the iRMX 86 Operating System
has a powerful, but easy-to-use human interface.
When add.ed to the sophisticated I/O system, the
iRMX 86 Operating System is readily extended
Physical Characteristics
Width: 30.48 cm (12.00 in)
Length: 17.15 cm (6.75 in)
Height: 1.50 cm (0.59 in)
Weight: 6.20 gm (22 oz)
8-7
inter
ISBC e 88/45 BOA'AD
Memory ~apacltyI Addressing
Electrical Characteristics
On-Board EPROM'
DC Power Dissipation-28.3 Watts
Device
Total
KByte8
Hex Addres8
Range
2716
2732A
2764
27128
8
16
32
64
FEOOO-FFFFF
FCOOO.-FFFFF
F8000-FFFFF
FOOOO-FFFFF
DC Power Requirements
Without EPROM(l)
With optional
ISBCGl> 341 MULTIMODULETN EPROM
Device
Total
KByte8
Hex Addre88
Range
2716
2732A
2764
27128
16
32
64
128
FCOOO-FFFFF
F8000-FFFFF
FOOOO-FFFFF
EOOOO-FFFFF
+0.14A
With 16K EPROM
(Using 2732A)
+0.20A
With 32K EPROM
(Using 2764)
+0.24A
20mA
20mA
-
-
-
-
Serial Communication Characteristics
± 0.1 %
Channel Device
A
Interfaces
iSBXTM Bus-All signals TIL compatible
B
Serial RS232C SignalsCTS
CLEAR TO SEND
OSR
DATA SET READY
OTE TXC TRANSMIT CLOCK
OTR
DATA TERMINAL READY
FG
FRAME GROUND
RTS
REQUEST TO SEND
RXC
. RECEIVE CLOCK
RXD
RECEIVE DATA
SG
SIGNAL GROUND
TXO
TRANSMIT DATA
C
. Supported
Interface
Max. Baud
Rate
8274(1) RS442A/449 800K SOLC/HOLC
RS232C
125K Synchronous
CCITIV.24 50K Asynchronous
125K Synchronous(2)
8274 RS232C
CCITIV.24 50K Asynchronous
8273(3) RS442A1449 64K SOLC/HOLC(3)
RS232C
9.6K SELF CLOCKING
CCITIV.24
NOTES:
1. 8274 supports HOLC/SOLC/SYNC/ASYNC multiprotocol
2. Exceed RS232C/CCITT V.24 rating of 20K baud
3. 8273 supports HOLC/SOLC
BAUD RATE EXAMPLES (Hz)
Asynchronous
+16 +32 +64
KBaud
8254
Synchronous
Timer Divide
KBaud
C.ountN
Serial RS422A/449 SignalsCS
OM
RC
RD
RS
RT
SC
SO
SG
TR
TI
5.1A
With 8K EPROM
(Using 2716)
With 64K EPROM
+0.24A
(Using 27128)
NOTE:
1. AS SHIPPED-no EPROMs in sockets, no iSBC 341
module. Configuration includes terminators for two
RS422A1449 and one RS232C channels.
"Four ISBC 88/45 EPROM sockets support JEOEC 24/28pin standard EPROMs and RAMs (static and iRAM, 3 sockets); iSBC 341 sockets also support EPROMs and RAMs.
Timer Input Frequency-8.00 MHz
Current Requirements
(All Voltage8 ±,%)
-12V
+12V
+5V
Configuration
CLEAR TO SEND
DATA MODE
.
RECEIVE COMMON
.RECEIVE DATA
REQUEST TO SEND
RECEIVE TIMING
SEND COMMON
SEND DATA
SIGNAL GROUND
TERMINAL READY
TERMINAL TIMING
10
26
31
52
104
1·25
143
Hj7
417
833
EQUATION
8-8
800
300
256
154
76.8
64
56
48
19.2
9.6
8,000,000
N
50.0
19.2
16.1
9.6
4.8
4.0
3.5
3.0
25.0
9.6
8.06
4.8
2.4
2.0
1.7
1.5
- -- --
.
500K 250K
N
N
12.5
4.8
4.03
2.4
1.2
1.0
0.87
0.75
125K'
N
inter
ISBe@ 88/45 BOARD
SERIAL INTERFACE CONNECTORS
Interface
RS232C
RS232C
RS449
RS449
Mode(1)
MULTIMODULETM
Edge Connector
Cable
Connector
DTE
DCE
DTE
DCE
26-pin(4), 3M-3462-0001
26-pin(4), 3M-3462-0001
40-pin(5), 3M-3464-0001
40-pin(5), 3M-3464-0001
3M(2)-3349/25
3M(2)-3349/25
3M(3)-3349/37
3M(3)-3349/37
25-pin(6),3M-3482-1000
25-pin(6),3M-3483-1000
37-pin(7),3M-3502-1000
37-pin(7),3M-3503-1000
NOTES:
1. DTE-Data Terminal Equipment Mode (male connector); DCE-Data Circuit Equipment mode (female connector) requires
line swaps.
2. Cable is tapered at one end to fit the 3M-3462 connector.
3. Cable is tapered to fit 3M-3464 connector.
4. Pin 26 of the edge connector is not connected to the flat cable.
5. Pins 38, 39, and 40 of the edge connector are not connected to the flat cable.
6. May be used with the cable housing 3M-3485-1000.
7. Cable housing 3M-3485-4000 may be used wih the connector.
Line Drivers (Supplied)
Reference Manual
Device
Characteristic
Qty
Installed
1488
1489
3486
3487
RS232C
RS232C
RS422A
RS422A
3
3
2
2
1
1
2
2
143824-iSBC 88/45 Advanced Data Communications Processor Board Hardware Reference Manual
(not supplied).
Reference manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.
ORDERING INFORMATION
Part Number Description
SBC 88/45
8-bit 8088-based Single Board Computer with 3 HDLC/SDLC serial
channels
8-9
inter
iSBC® 188/56
ADVANCED COMMUNICATING COMPUTER
•
•
•
•
•
7 On-Board DMA Channels for Serial
• 110,280188
DMA Channels for the
iSBC® Single Board Computer or
Intelligent Slave Communication Board
iSBXTM MULTIMODULETM Board
8 Serial Communications Channels,
Expandat)le to 12 Channels on a Single
MULTIBUS® Board
•
8 MHz 80188 Microprocessor
•
•
•
Supports RS232C Interface on6
Channels, RS422A/449 or RS232C
Interface Configurable on 2 Channels
Supports Async, Bisync HDLC/SDLC,
On-Chip Baud Rate Generation, Half/
Full-Duplex, NRZ, NRZI or FM
Encoding/Decoding
•
MULTIBUS Interface for System
Expansion and Multimaster
Configuration
Two iSBX Connectors for Low Cost I/O
Expansion
256K Bytes Dual-Ported RAM On-Board
Two 28-pin JEDEC PROM Sites
Expandable to 6 Sites with the iSBC
341 MULTIMODULE Board for a
Maximum of 192K Bytes EPROM
Resident Firmware to Handle up to 12
. RS232C Async Lines
The iSBC 188/56 Advanced Communicating Computer (COMMputerTM) is an intelligent 8-channel single
board computer. This iSBC board adds the 8 MHz 80188 microprocessor-based communications flexibility to
the Intel line of OEM microcomputer systems. Acting as a stand-alone CPU or intelligent slave for communication expansion, this board provides a high performance, low-cost solution for multi-user systems. The features
of the iSBC 188/56 board are uniquely suited to manage higher-layer protocol requirements needed in today's
data communications applications. This single board computer takes full advantage of Intel's VLSI technology
to provide state-of-the-art, economic, computer based solutions for OEM communications-oriented applications.
280715-1
'IBM is a registered trademark of International Business Machines
'UNIX is a trademark of Bell Laboratories
'XENIX is a trademark of Microsoft Corporation
8-10
November 1986
Order Number: 280715-002
inter
ISBC® 188/56 ADVANCED COMM COMPUTER
incoming and outgoing messages at data rates up to
19.2K baud. Two channels are supported for continuous data rates greater than 19.2K baud. Each serial
channel can be individually programmed for different
baud rates to allow system configurations with differing terminal types. The firmware supplied on the
iSBC 188/56 board supports up to 12 asynchronous
RS232C serial channels, provides modem control
and performs power-up diagnostics. The high performance of the on-board. CPU provides intelligence
to handle protocols and character handling typically
assigned to the system CPU. The distribution of intelligence results in optimizing system performance
by releasing the system CPU of routine tasks.
OPERATING ENVIRONMENT
The iSBC 188/56 COMMputer™ features have
been designed to meet the needs of numerous communications applications. Typical applications include:
1. Terminal/cluster controller
2. Front-end processor
3. Stand-alone communicating computer
Terminal/Cluster Controller
A terminal/cluster controller concentrates communications in a central area of a system. Efficient
handling of messages coming in or going out of the
system requires sufficient buffer space to store
messages and high speed I/O channels to transmit
messages. More sophisticated applications, such as
cluster controllers, also require character and format
conversion capabilities to allow different types of terminals to be attached.
Front-End Processor
A front-end processor off-loads a system's central
processor of tasks such as data manipulation and
text editing of characters collected from the attached terminals. A variety of terminals require flexible terminal interfaces. Program code is often dynamically downloaded to the front-end processor
from the system CPU. Downloading code requires
sufficient memory space for protocol handling and
program code. Flow control and efficient handling of
interrupts require an efficient operating system to
manage the hardware and software resources.
The iSBC 188/56 Advanced Communicating Computer is well suited for multi-terminal systems (see
Figure 1). Up to 12 serial channels can be serviced
in mUlti-user or cluster applications by adding two
iSBX 354 MULTIMODULE boards. The dual-port
RAM provides a large on-board buffer to handle
ISac~
ISBX'" 354
BOARD
ISBX'" 354
BOARD
c:::=::::J
c:::::::::::J
ISac'" 188/56
BOARD
86/30 BOARD
,...---r.--~
FIRMWARE
1/
SYSTEM
PROCESSOR
MULTIBUS" ,SYSTEM BUS
280715-2
Figure 1_ Terminal/Cluster Controller Application
8-11
inter
ISBC® 188/56 ADVANCED COMM COMPUTER
The iSaC 188/56 board features are designed to
provide a high performance solution for front-end
processor applications (see Figure 2). A large
amount of random access memory is provided for
dynamic storage of program code. In addition, local
memory sites are available for storing routine programs such as X.25, SNA or bisync protocol software. The serial channels can be configured for links
to mainframe systems, point-to-point terminals, modems or multidrop configurations.
The MULTISUS interface can be used to access additional system functions. Floppy disk control and
graphics capability can be added to the iSSC standalone computer through the is ax connectors.
ARCHITECTURE
'The four major functional areas are Serial I/O, CPU,
Memory and OMA. These areas are illustrated in Figure 4.
Stand-Alone COMMputer™
Application
Serial 110
A stand-alone communication computer is a complete computer system. The CPU is capable of managing the resources required to meet the needs of
multi-terminal, multi-protocol applications. These applications typically require multi-terminal support,
floppy disk control, local memory allocation, and
program execution and storage.
Eight HOLC/SOLC serial interfaces are provided on
the iSaC 188/56 board. The serial interface can be
expanded to 12 channels by adding 2 iSaX 354
MULTIMOOULE boards. The HOLC/SOLC interface
is compatible with laM' system and terminal equipment and with CCITI's X.25 packet switching interface.
To support stand-alone applications, the iSaC
188/56 COMMputer board uses the computational
capabilities of an on-board CPU to provide a highspeed system solution controlling 8 to 12 channels
of serial I/O (see Figure 3). The local memory available is large enough to handle special purpose
code, execution code and routine protocol software.
Four 82530 Serial Communications Controllers
(SCC) provide eight channels of half/full duplex serial I/O. Six channels support RS232C interfaces. Two channels are RS232C/ 422/ 449 configurable and can be tri-stated to allow multidrop networks.
The 82530 component is designed to satisfy several
serial communications requirements; asynchronous,
o
•
ISBX'" 354
ISBX'" 354
BOARD
BOARD
C==::J c::=::::J
ISBC~ 188/56
r----,,---,
BOARD
MULTIBUS@ SYSTEM BUS
280715-3
Figure 2. Front-End Processor Application
8-12
Isec® 188/56 ADVANCED COMM COMPUTER
byte-oriented synchronous (HOLC/SOLC) modes.
The increased capability at the serial controller point
resl,llts inoff,loading the CPU of tasks formerly assigned to the CPU or its associated hardware. Configurability of the 82530 allows the user to configure
it to handle all asynchronous data formats regardless of data size, number of start or stop bits, or
parity requirements. An on-chip baud rate generator
allows independent baud rates on each channel.
Central CPU
The 80188 central processor component provides
high performance, flexibility and powerful processing. The 80188 component is a highly integrated microprocessor with an 8-bit data bus interface and a
16-bit internal architecture to give high performance.
The 80188 is upward compatible with 86 and 186
software;
The clock can be generated either internally with the
SCC chip, with an external clock or via the NRZ1
clock encoding mechanism.
The 80188/82530 combination with on-board
PROM/EPROM sites, and dual-port RAM provide
the intelligence and speed to manage multi-user,
multi-protocol communication operations.
All eight channels can be oonfigured as Data Terminal Equipment (OTE) or Data Communications
Equipment (OCE). Table 1 lists the interfaces supported.
Table 1.ISBC® 188/56 Interface Sl,Ipport
Connection
Synchronous
Memory
There are two areas of memory on-board: dual-port
RAM and universal site memory. The iSBC 188/56
board contains 256K bytes of dual· port RAM that is
addressable by the 80188 on-board. The dual-port
memory is configurable anywhere in a 16M byte address space on 64K byte boundaries as addressed
from the MULTIBUS port. Not all of the 256K bytes
are visible from the MULTIBUS bus side. The
amount of dual-port memory visible to the
Asynchronous
Modem to Direct Modem to Direct
Point-to-Point
Multidrop
Loop
X"
X
Channels
o and 1
Channels
o and 1
X
N/A
•• All 8 channels are denoted by X.
rFlWll
ROUTINE
PROGRAMS
80188
D
L...JL.......I
EXECUTION
CODE
STAND-ALONE
PROCESSOR
MULTIBUSs SYSTEM BUS
280715-4
Figure 3. Stand-Alone COMMputer™ Application
8-13
ISBCiID 188/56 ADVANCEDCOMM COMPUTER
MULTIBUS side can be set (with jumpers) to none,
16K bytes, or 48K bytes. In a multiprocessor system
these features provide local memory for each ·processor and shared system memory configurations
whereihe total system memory size can exceed one
megabyte without addressing conflicts.
On-Board DMA
Seven, channels of Direct Memory Access (DMA)
are provided between serial 110 and on-board dual
port RAM by two 8237-5 components. Each of channels 0, 1, 2, 3, 5, 6, and 7 is supported by their own
DMA line. Serial channels 0 and 1 are configurable
for full duplex DMA. Configuring the full duplex DMA
option for Channels 0 and 1 would require Channels
2 and 3 to be interrupt driven or polled. Channel 4 is
interrupt driven or polled only.
The second area of memory is universal site memory providing flexible memory expansion. Two 28-pin
JEDEC sockets are provided. One of these sockets
is used for the. resident firmware as described in the
FIRMWARE section.
Two DMA channels are' integrated in the 80188
processor. These additional channels can be connected to the iSBX interfaces to provide DMA capability to iSBX MULTIMODULE boards such as the
iSBX 21M Floppy Disk Controller MULTIMODULE
board.
The default 'configuration of the boards supports
16K byte EPROM devices such as the Intel 27128
component. However, these sockets can contain
ROM, EPROM, Static RAM, or EEPROM. Both soqkets must contain the same type of component (i.e.
as the first socket contains an EPROM for the resident firmware, the second must also contain an
EPROM with the same pinout). Up to 32K bytes can
be addressed per socket giving a maximum universal site memory size of 64K bytes. By using the iSBC
341 MULTI MODULE board, a maximum of 192K
bytes of universal site memory is available. This provides sufficient memory space for on-board network
or resource management software.
OPERATING SYSTEM SUPPORT
Intel offers run-time foundation software to support
applications that range from general purpose to
high-performance solutions.
CHANNELS
CHANNEL
7·2
1-11
RS232C1
4221441
RS232C
258KFIAM
MULTlBUS· SYSTEM BUS
280715-5
Figure 4. Block Diagram of ISBCe 188/56 Board
8-14
inter
iSBC® 188/56 ADVANCED COMM COMPUTER
Release 6 of the iRMX 86 Operating System provides a rich set of features and options to support
sophisticated stand-alone communications applications on the iSBC 188/56 Advanced Communicating
Computer. In addition to supporting real-time requirements, the iRMX 86 Operating System Release
6 has a powerful, yet easy to use human interface.
Services provided by the iRMX 86 Operating System
include facilities for executing programs concurrently, sharing resources and information, servicing
asynchronous events and interactively controlling
system resources and utilities. The iRMX 86 Operating System is readily extended to support assembler, PL/M, PASCAL, and FORTRAN software development environments. The modular building
block software lends itself well to customized application solutions. If the iSBC 188/56 board is acting
as an intelligent slave in a system environment, an
iRMX 86 driver resident in the host CPU can be written by following the examples in the manual "Guide
to Writing Device Driven for iRMX 86 and iRMX 88
1/0 Systems".
vanced Communicating COMMputer board. The
monitor contains the necessary hardware, software
and documentation required to interface the iSBC
188/56 target system to an Intel microcomputer development system for debugging application software.
The XENIX' 286 Operating System, Release 3, is a
fully licensed adaptation of the Bell Laboratories
System III UNIX' Operating System. The XENIX system is an interactive, protected, multi-user, multi~
tasking operating system with a powerful, flexible
human interface. Release 3 of XENIX 286 includes a
software driver for the iSBC 188/56 board (and up to
two iSBX 354 MULTIMODULE Boards) acting as an
intelligent slave for mUlti-user applications requiring
multiple persons running independent, terminal-oriented jobs. Example applications include distributed
data processing, business data processing, software
development and engineering or scientific data analysis. XENIX 286 Release 3 Operating System services include device independent 1/0, tree-structured
file directory and task hierarchies, re-entrant/shared
code and system accounting and security access
protection.
The iSDMTM 86 System Debug Monitor supports target system debugging for the iSBC 188/56 Ad-
Table 2. Features of the ISBC@ 188/56 Firmware
Feature
Description
Asynchronous Serial
Channel Support
Supports the serial channels in asynchronous ASCII mode.
Parameters such as baud rate, parity generation, parity
checking and character length can be programmed
independently for each channel.
Block Data Transfer
(On Output)
Relieves the host CPU of character-at-a-time interrupt
processing. The iSBC 188/56 board accepts blocks of data for
transmission and interrupts the processor only when the entire
block is transmitted.
Limited Modem Control
Provides software control of the Data Terminal Ready (DTR)
line on all channels. Transitions on the Carrier Detect (CD) line
are sensed and reported to the host CPU.
Tandem Modem Support
Transmits an XOFF character when the number of characters
in its receive buffer exceeds a threshold value and transmits an
XON character when the buffer drains below some other
threshold.
Download and
Execute Capability
Provides a capability for the host CPU to load code anywhere in
the address space of the iSBC 188/56 board and to start
executing at any address in its address space.
Power Up
Confidence Tests
On board reset, the firmware executes a series of simple tests
to establish that crucial components on the board are
functional.
8-15
intJ
iSBC® 188/56 ADVANCED COMM COMPUTER
80188 processor and the other in the 80130 component. The two controllers are configured with the
80130 controller as· the master and the 80188 controller as the slave. Two of the 80130 interrupt inputs
are connected to the 82530 serial controller components to provide vector interrupt capabilities by the
serial controllers. The iSBC 188/56 board provides
22 interrupt levels. The highest ,level is the NMI
(Non-Maskable Interrupt) line which is directly tied to
the 80188 CPU. This interrupt is typically used for
signaling catastrophic events (e.g. power failure).
There are 5 levels of interrupts internal to the 80188
processor. Another 8 levels of interrupts are available from the 80130 component. Of these 8, one is
tied to the programmable interrupt controller (PIC) of
the 80188 CPU. An additional 8 levels of interrupts
are available at the MULTIBUS interface. The iSBC
188/56 board does not support bus vectored interrupts. Table 3 lists the possible interrupt sources.
FIRMWARE
The iSBC 188/56 Communicating COMMputer
board is supplied with resident firmware that supports up to 12 RS232C asynchronous serial channels. In addition, the firmware provides a facility for a
host CPU to download and execute code on the
iSBC 188/56 board. Simple power-up confidence
tests are also included to provide a quick diagnostic
service. The firmware converts the iSBC 188/56
COMMputer board to a slave communications controller. As a slave communications controller, it requires a separate MULTIBUS host CPU board and
requires the use of MULTIBUS interrupt line to signal
the host processor. Table 2 summarizes the features of the firmware.
INTERRUPT CAPABILITY
The iSBC 188/56 board has two programmable interrupt controllers (PICs). One is integrated into the
Table 3 Interrupt Request Sources
Function
Number of
Interrupts
MULTIBUS Interface
INTO-INT7
Requests from MULTIBUS resident peripherals or other
CPU boards.
8
82530 Serial Controllers
Transmit buffer empty, receive buffer full and channel
errors 1 and external status.
Internal 80188
Timer and DMA
Timer 0, 1, 2 outputs and 2 DMA channel interrupts.
80130 Timer Outputs
Timer 0, 1, 2 outputs of 80130.
3
Interrupt from Flag
Byte Logic
Flag byte interrupt set by MULTIBUS master (through
MULTIBUS® 1/0 Write).
1
Bus Flag Interrupt
Interrupt to MULTIBUS® (Selectable for INTO to INT?)
generated from on-board 80188 1/0 Write.
1
iSBX Connectors
Function determined by iSBX MULTIMODULE board.
Device
8 per 82530
Total = 32
5
4 (Two per
Connector)
2
iSBXDMA
DMA interrupt from iSBX(TDMA).
Bus Fail-Safe Timeout
Interrupt.
Indicates iSBC 188/48 board timed out either waiting for
MULTIBUS access or timed out from no acknowledge
while on MULTIBUS System Bus.
1
Latched Interrupt
Converts pulsed event to a level interrupt. Example:
823?A-5 EOP.
1
OR-Gate Matrix
Concentrates up to 4 interrupts to 1 interrupt (selectable
by stake pins).
1
Ring Indicator
Interrupt
Latches a ring indicator event from serial channels 4, 5,
6, or?
1
NOR-Gate
Matrix
Inverts up to 2 interrupts into 1 (selectable by stake
pins).
1
8-16
inter
ISBC~
188/56 ADVANCED COMM COMPUTER
The Multimaster capabilities of the iSBC 188/56
board offers easy expansion of processing capacity
and the benefits of multiprocessing. Memory and
I/O capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards.
SUPPORT FOR THE 80130
COMPONENT
Intel does not support the direct processor execution of the iRMX nucleus primitives from the 80130
component. The 80130 component provides timers
and interrupt controllers.
SPECIFICATIONS
EXPANSION
Word Size
EPROM Expansion
Instruction-8, 16, 24 or 32 bits
Data Path-8 bits
Processor Clock
82530 Clock
8 MHz
4.9152 MHz
Memory may be expanded by adding Intel compatible memory expansion boards. The universal site
memory can be expanded to six sockets by adding
the iSBC 341 MULTIMODULE board for a maximum
total of 192K bytes of universal site memory.
DMAClock
4MHz
Dual Port RAM
iSBC 188/56 Board-256 bytes
iSBXTM MULTIMODULETM Expansion
Module
As viewed from the 80188-64K bytes
Two 8-bit iSBX MULTIMODULE connectors are provided on the iSBC 188/56 board. Using iSBX modules additional functions can be added to extend the
I/O capability of the board. In addition to specialized
or custom designed iSBX boards, there is a broad
range of iSBX MULTIMODULE boards from the Intel
including parallel I/O, analog I/O, IEEE 488 GPIB,
floppy disk, magnetic bubbles, video and serial I/O
boards.
As viewed from the MULTIBUS System BusChoice: 0, 16K or 48K
EPROM
iSBC® 188/56
On Board
Size
Address Range
Board Using:
Capacity
2732
2764
27128
27256
27512
The serial I/O MULTIMODULE boards available include the iSBX 354 Dual Channel Expansion MULTIMODULE board. Each iSBX 354 MULTIMODULE
board adds two channels of serial I/O to the iSBC
188/56 board for a maximum of twelve serial channels. The 82530 serial communications controller on
the MULTIMODULE board handles a large variety of
serial communications protocols. This is the same
serial controller as is used on the iSBC 188/56
board to offer directly compatible expansion capability for the iSBC 188/56 COMMputer board.
4K
8K bytes FEOOO-FFFFFH
8K 16K bytes FCOOO-FFFFFH
16K 32K bytes F8000-FFFFFH
32K 64K bytes FOOOO-FFFFFH
64K 128K bytes EOOOO-FFFFFH
Memory Expansion
MULTIBUS® INTERFACE
The iSBC 188/56 Advanced COMMputer board can
be a MULTIBUSmaster or intelligent slave in a multimaster system. The iSBC 188/56 board incorporates a flag byte signalling mechanism for use in
multiprocessor environments where the iSBC
188/56 board is acting as an intelligent slave. The
mechanism provides an interrupt handshake from
the MULTIBUS System Bus to the on-board-processor and vice-versa.
EPROM with
ISBC® 341
Board Using:
Capacity
Address Range
2732
2764
27128
27256
24K bytes
48K bytes
96K bytes
192Kbytes
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO- FFFFFH
I/O Capacity
Serial-8 programmable lines using four 82530 components
iSBX MULTIMODULE-2 iSBX single-wide boards
8-17
inter
iSBC® 188/56 ADVANCED COMM COMPUTER
Serial Communications Characteristics
SERIAL RS232C SIGNALS
Synchronou&-Internal or external character synchronization on one or two synchronous characters
CD
CTS
DSR
DTE TXC
DTR
RTS
RXC
RXD
SG
TXD
RI
Asynchronous-5-8 bits and 1, 1%, or 2 stop bits
per character; programmable clock factor; break detection and generation; parity, overrun, and framing
error detection.
Baud Rates
Synchronous
X1 Clock
Carrier
Clear to Send
Data Set Ready
Transmit Clock
Data Terminal Ready
Request to Send
Receive Clock
Receive Data
Signal Ground
Transmit Data
Ring Indicator
RS422A/449 SIGNALS
Baud Rate
82530 Count Value
(Decimal)
64000
48000
19200
9600
4800
2400
1800
1200
300
36
49
126
254
510
1022
1363
2046
8190
Receive Common
Receive Data
Receive Timing
Send Data
Terminal Timing
RC
RD
RT
SD
n
Environmental Characteristics
Temperature: 0 to 55·C at 200 Linear Feet/Min.
(LFM) Air Velocity
Humidity:
Asynchronous
X16Clock
to 90%, non-condensing (25°C to
70°C)
Physical Characteristics
Baud Rate
82530 Count Value
(Decimal)
19200
9600
4800
2400
1800
1200
300
110
6
14
30
62
83
126
510
1394
Width:
Length:
Height:
Weight:
30.48 cm (12.00 in)
17.15 cm (6.75 in)
1.04 cm (0.41 in)
595 gm (21 oz)
Electrical Characteristics
The power required per voltage for the iSSC 188/56
board is shown below. These numbers do not include the current required by universal memory sites
.
or expansion modules.
Interfaces
iSBXTM BUS
The iSSC 188/56 board meets iSSX compliance level D8/8 DMA"
Voltage
(Volts)
Current
(Amps)typ.
Power
(Watts) typo
+5
+12
-12
4.56A
0.12A
" 0.11A
22.8W
1.5W
1.3W
Reference Manual
iSSC 188/56 Advanced Data Communications Computer Reference Manual Order Number 148209-001.
MULTIBUS® SYSTEM BUS
The iSSC 188/56 board meets MULTISUS compliance level Master/Slave D8 M24 116 VO EL.
ORDERING INFORMATION
Part Number
iSSC 188/56
8-18
Description
8-Serial Channel Advanced Communicating Computer
inter
iSBC® 534
FOUR CHANNEL COMMUNICATION EXPANSION BOARD
•
•
•
•
Serial I/O Expansion Through Four
Programmable Synchronous and
Asynchronous Communications
Channels
•
•
Individual Software Programmable
Baud Rate Generation for Each Serial
I/O Channel
•
Two Independent Progammable 16·Bit
Interval Timers
•
•
Sixteen Maskable Interrupt Request
Lines with Priority Encoded and
Programmable Interrupt Algorithms
Jumper Selectable Interface Register
Addresses
16·Blt Parallel I/O Interface Compatible
with Bell 801 Automatic Calling Unit
RS232C/CCITT V.24 Interfaces Plus 20
mA Optically Isolated Current Loop
Interfaces (S~ckets)
Programmable Digital Loopback for
Diagnostics
Interface Control for Auto Answer and
Auto Originate Modems
The iSBC 534 Four Channel Communication Expansion Board is a member of Intel's complete line of memory
and I/O expansion boards. The iSBC 534 interfaces directly to any Single board computer via the MULTIBUS
to provide expansion of system serial communications capability. Four fully programmable synchronous and
asynchronous serial channels with RS232C buffering and provision for 20 mA optically isolated current loop
buffering are provided. Baud rates, data formats, and interrupt priorities for each channel are individually
software selectable. In addition to the extensive complement of EIA Standard RS232C signals provided, the
iSBC 534 provides 16 lines of RS232C buffered programmable parallel I/O. This interface is configured to be
directly compatible with the Bell Model 801 automatic calling unit. These capabilities provide a flexible and
easy means for interfacing Intel iSBC based systems to RS232C and optically isolated current loop compatible
terminals, cassettes, asynchronous and synchronous modems, and distributed processing networks.
280238-1
8-19
November 1986
Order Number: 280238-001
inter
ISBC® 534 COMMUNICATION BOARD
FUNCTIONAL DESCRIPTION
Table 1. Programmable Timer Functions
Communications Interface
Four programmable communications interfaces. using Intel's 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) are contained
on the board.· Each USART can be programmed by
the system software to individually select the desired
asynchronous or synchronous serial data transmission technique (including IBM Bisync). The mode of
operation (i.e., synchronous or asynchronous), data
format, control character format, parity, and baud
rate are all under program control. Each 8251A provides full duplex, double buffered transmit and receive capability. Parity, overrun, and framing error
detection are all incorporated in each USART. Each
set of RS232C command lines, serial data lines, and
signal ground lines are brought out to 26-pin edge
connectors that mate with RS232C flat or round cables.
Function
Operation
Interrupt on
terminal count
When terminal count is
reached an interrupt request is
generated. This function is
used for the generation of realtime clocks.
Rate generator
Divide by N counter. The output
will go low for one input clock
cycle and high for N-1 input
clock periods.
Square wave
rate generator
Output will remain high for onehalf the count and low for the
other half of the count.
Interrupt Request Lines
Two independent Intel 8259A programmable interrupt controllers (PIC's) provide vectoring for 16 interrupt levels.· As shown in Table 2, a selection of
three priority processing algorithms is available to
the system deSigner. The manner in which requests
are serviced may thus be configured to match system requirements. Priority assignments may be reconfigured dynamically via software at any time during system operation. Any combination of interrupt
levels may be masked through storage, via software,
of a single byte to the interrupt mask register of each
PIC. Each PIC's interrupt request output line may be
jumper selected to drive any of the nine interrupt
lines on the MlJLTIBUS.
16·Blt Interval Timers
The iSBC 534 provides six fully programmable and
independent BCD and binary 16-bit interval timers
utilizing two Intel 8253 programmable interval
timers.· Four timers are available to the systems designer to generate baud rates for the USARTs under
software control. Routing for the outputs from the
other two counters is jumper selectable. Each may
be independently routed to the programmable interrupt controller to provide real time clocking or to the
USARTs (for applications requiring different transmit
and receive baud rates). In utilizing the iSBC 534,
the systems designer simply configures, via software, each timer independently to meet system requirements. Whenever a given baud rate or time delay is needed, software commands to the programmable timers select the desired function. Three
functions of these Jimers are supported on the iSBC
534, as shown in Table 1. The contents of each
counter may be. read at any time during system operation.
Table 2. Interr!Jpt Priority Options
Algorithm
Fully
nested
8-20
Operation
. Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.
Autorotating
Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.
Specific
priority
System software assigns
lowest priority level. Priority of
all other levels based in
sequence numerically on this
assignment.
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280238-2
ISBC@ 534 COMMUNICATION BOARD
Interrupt Request Generation-As shown in Table,
3, interrupt requests may originate from 16 sources.
Two jumper selectable interrupt requests (8 total)
can be automatically generated by each USART
when a character is ready to be transferred to the
MULTIBUS system bus (i.e., receive buffer is full). or
a character has been transmitted (transmit buffer is
empty). Jumper selectable requests can be generat.
ed by two of the programmable timers (PITs), and ,six
lines are routed directly from peripherals to accept
carrier detect (4 lines), ring indicator, and the Bell
801 present next digit request lines.
Asynchronous- 5-8 bit characters; break character
generation; 1, 1Y2, or 2 stop bits;
false start bit detection.
Sample' Baud Rates(1)
I
Frequency(2) ,
Baud Rate (Hz)
(kHz, Software
Selectable)
Synchronous Asynchronous
-
153.6
76.8
38.4
19.2
9.6
4.8
6.98
Systems Compatibility
The iSBC 534 provides 16 RS232C buffered parallel
I/O lines implemented utilizing an Intel 8255A pro·
grammable peripheral interface (PPI) configured to
operate in mode 0. 0 These lines are configured to
be directly compatible with the Bell 801 automatic
calling unit (ACU). This capability allows the
iSBC 534 to interface to Bell 801 type ACUs and up
to four modems or other serial communications de·
vices. For systems not requiring interface to an ACU,
the parallel I/O lines may also be used as general
purpose RS232C compatible control lines in system
implementation.
38400
19200
9600
4800
6980
0
1
2
3
4
5
6
7
PORTO RxRDY
PORTOTx RDY
PORT 1 RxRDY
PORT 1 TxRDY
PORT 2 RxRDY
PORT2Tx RDY
PORT 3 RxRDY
PORT 3 Tx RDY
PIT 1 counter 1
PIT 2 counter 2
Ring Indicator (all ports)
Present next digit
Carri~r detect port 0
Carrier detect port 1
Carrier detect port 2
Carrier detect port 3
-
Input Frequency (On· Board Crystal Oscillator)1.2288 MHz ± 0.1 % (0.813 ,...S period, nominal)
Function
PIC 1
2400
1200
600
300
150
75
110
Interval Timer and Baud Rate
Generator Frequencies
Table 3. Interrupt ASSignments
PICO
+ 64
9600
4800
2400
1200
600
300
NOTES:
1. Baud rates shown here are only a sample subset of possible software programmable rates available. Any frequen·
cy from 18.75 Hz to 614.4 kHz may be generated utilizing
on·board crystal oscillator and 16-bit programmable inter·
val. timer (used here as frequency divider).
2. Frequency selected by 1/0 writes of appropriate 16-bit
frequency factor to Baud Rate Register.
o NOTE:
Complete operational details on the Intel 8251A
USART, the Intel 8253 Programmable Interval Tim·
er, the Intel 8255A Programmable Peripheral Inter·
face, and the Intel 8259A Programmable Interrupt
Controller are contained in the Intel Component
Data Catalog.
Interrupt
Request
Line
+ 16
Real·Time
Interrupt
Interval
Sln!!le Timer
DuallTlmer
Counter
(Two Timers
cascaded)
Min
Max
Min
Max
1.63/,s
53.3ms
3.26/,s
58.25
minutes
Rate
Generator
18.75 Hz 614.4 kHz 0.0029 Hz 307.2 kHz
(Frequency)
SPECIFICATIONS
Serial Communications Characteristics
Synchronous- 5-8 bit characters; internal or exter·
nal character synchronization; auto·
matic sync insertion.
8-22
inter
ISBC® 534 COMMUNICATION BOARD
Interfaces-RS232C Interfaces
Physical Characteristics
EIA Standard RS232C Signals provided and supported:
Carrier detect
Receive data
Clear to send
Ring indicator
Data set ready
Secondary receive data
Data terminal ready Secondary transmit data
Request to send
Transmit clock
Receive clock
Transmit data
Width:
12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Weight: 14 oz. (398 gm)
Parallel I/o-a input lines, 8 output lines, all Signals
RS232C compatible
Average DC Current
Electrical Characteristics
Without
With
Opto-Isolators Opto-lsolators(1)
1.9 A, max
1.9A, max
Vee = +5V
420mA, max
Voo=+12V 275mA, max
VAA = -12V 250·mA, max
400mA, max
Voltage
Bus-All signals MULTIBUS system bus compatible
1/0 Addressing
NOTE:
The USART, interval timer, interrupt controller, and
parallel interface registers of the iSBC 534 are configured as a block of 16 1/0 address locations. The
location of this block is jumper selectable to begin at
any 16-byte 1/0 address boundary (Le., OOH, 10H,
20H, etc.).
1. With four 4N33 and four 4N37 opto·isolator packages
installed in sockets provided to implement four 20 mA current loop inteliaces.
Environmental Characteristics
Operating Temperature: O°C to + 55°C
110 Access Time
400
400
400
400
ns
ns
ns
ns
USART registers
Parallel 1/0 registers
Interval timer registers
Interrupt controller registers
Reference Manual
502140-002-iSBC 534 Hardware
al (NOT SUPPLIED)
Pins Centers
Mating Connectors
(qty.) (In.)
Bus
0.156
Viking 2KH43/9 AMK12
86
Serial and
3m 3462-0001 or
26
0.1
parallel 1/0
TI H312113
Interface
ORDERING INFORMATION
Part Number Description
SBe 534
Four Channel Communication Expansion Board
I e 0'P t 0- IsoIat ors
Compafbi
Receiver
Supplier
Fairchild
General EI,ectric
Monsanto
Fairchild
General Electric
Monsanto
Manu-
Reference manuals are shipped with each product
only if designated SUPPLIED (see above). Manuals
may be ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, California 95051.
Compatt'ble Connectors
Function
Driver
Referenc~
Part Number
4N33
4N37
8-23
iSBC® 544
INTELLIGENT COMMUNICATIONS CONTROLLER
• iSBC®
Communications Controller
Acting as a Single Board
Communications Computer or an
Intelligent Slave for Communications
Expansion
•
On-Board Dedicated 808SA
Microprocessor Providing
Communications Control and Buffer
Management for Four Programmable
Synchronous/ Asynchronous Channels
•
•
Sockets for Up To 8K Bytes of EPROM
•
16K Bytes of Dual Port Dynamic Read/
Write Memory with On-Board Refresh
•
Ten Programmable Parallel I/O Lines
Compatible with Bell 801 Automatic
Calling Unit
•
•
•
•
Twelve Levels of Programmable
Interrupt Control
Individual Software Programmable
Baud Rate Generation for Each Serial
I/O Channel
Three Independent Programmable
Interval Timer/Counters
Interface Control for Auto Answer and
Auto Originate Modem
Extended MULTIBUS® Addressing
Permits ISBC 544 Board Partitioning
Into 16K-Byte Segments In a
1-Megabyte Address Space
The iSSC 544 Intelligent Communications Controller is a member of Intel's family of single-board computers,
memory, I/O, and peripheral controller boards. The iSSC 544 board is a complete communications controller
on a single 6.75 x 12.00 inch printed circuit card. The on-board 8085A CPU may perform local communications
processing by directly interfacing with on-board read/write memory, nonvolatile read only memory, four synchronous/asynchronous serial I/O ports, RS232/RS366 compatible parallel I/O, programmable timers, and
programmable interrupts.
280239-1
8-24
November 1986
Order Number: 280239-001
inter
ISBC® 544 COMMUNICATIONS CONTROLLER
8085A CPU to coordinate up to four serial channels.
Using the iSBC 544 as an intelligent slave, multichannel serial transfers can be managed entirely onboard, freeing the bus master to perform other system functions.
FUNCTIONAL DESCRIPTION
Intelligent Communications Controller
Two Mode Operation - The iSBC 544 board is
capable of operating in one of two modes: 1) as a
single board communications computer with all computer and communications interface hardware on a
single board; 2) as an "intelligent bus slave" that
can perform communications related tasks as a peripheral processor to one or more bus masters. The
iSBC 544 may be configured to operate as a standalone single board communications computer with
all MPU, memory and I/O elements on a single
board. In this mode of operation, the iSBC 544 may
also interface with expansion memory and I/O
boards (but no additional bus masters). The iSBC
544 performs as an intelligent slave to the bus master by performing all communications related tasks.
Complete synchronous and asynchronous I/O and
data management are controlled by the on-board
Architecture - The iSBC 544 board is functionally
partitioned into three major sections: I/O, central
computer, and shared dual port RAM memory (Figure 1). The I/O hardware is centered around the four
Intel 8251A USART devices providing fully programmable serial interfacing. Included here as well is a
10-bit parallel interface compatible with the Bell 801
automatic calling unit, or equivalent. The I/O is under full control of the on-board CPU and is protected
from access by system bus masters. The second
major segment of the intelligent communications
controller is a central computer, with an 8085A CPU
providing powerful processing capability. The 8085A
together with on-board EPROM/ROM, static RAM,
programmable timers/counters, and programmable
SERiAL iiO - -
-
-
-
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-
-
-
;ARAUELii'o -
-,
I
I
I
INPUT
I
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I
PROGRAMMABLE 110
:
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I
I
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DYNAMIC
RAM
I
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___ y~L..!ORT~A~ M!M~~Y
MULTIIUS
280239-2
Figure 1. iSBC® 544 Intelligent Communications Controller Block Diagram
8-25
inter
iSBC® 544 COMMUNICATIONS CONTROLLER
interrupt control provide the intelligence to manage
sophisticated communications operations on-board
the iSBC 544 board. The timer/counters and interrupt control are also common to the I/O area providing programmable baud rates to the USARTs and
prioritizing interrupts generated from the USARTs.
The central computer functions are protected for access only by the on-board 8085A. Likewise, the onboard 8085A may not gain access to the system bus
when being used as an intelligent slave. When the
iSBC 544 is used as a bus master, the on-board
8085A CPU controls complete system operation accessing on-board functions as well as memory and
I/O expansion. The third major segment, dual port
RAM memory, is the key link between the iSBC 544
intelligent slave and bus masters managing the system functions. The dual port concept allows a common block of dynamic memory to be accessed by
the on-board 8085A CPU and off-board bus masters. The system program can, therefore, utilize the
shared dual port RAM to pass command and status
information between the bus masters and on-board
CPU. In addition, the dual port concept permits
blocks of data transmitted or received to accumulate
iii the on-board shared RAM, minimizing the need
for a dedicated memory board.
Bell Model 801, or eqlJivalent, and can also be used
for auxiliary functions. All signals are RS232C compatible, and the interface cable signed assignments
meet RS366 specifications. For systems not requiring an ACU interface, the parallel I/O port can be
used for any general purpose interface requiring
RS232C compatibility.
Central Processing Unit
Intel's powerful 8-bit n-channel 808SA CPU, fabricated on a single LSI chip, is the central processor for
the iSBC 544. The 8085A CPU is directly software
compatible with the Intel 8080A CPU. The 808SA
contains six 8-bit general purpose registers and an
accumulator. The six general purpose registers may
be addressed individually or in pairs, providing both
single and double precision operators. The minimum
instruction execution time is 1.45 microseconds. The
808SA CPU has a 16-bit program counter. An external stack, located within any portion of iSBC 544
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this external stack. This stack provides subroutine nesting bounded only by memory
size.
Serial I/O
Four programmable communications interfaces using 'Intel's 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) are contained
on the board and controlled by the on-board CPU in
combination with the on-board interval timer/counter to provide all common communication frequencies. Each USART can be programmed by the system software to individually select the desired asynchronous or synchronous serial data transmission
technique (including IBM Bisync). The mode of operation (i.e., synchronous or asynchronous), data format, control character format, parity, and baud rate
are all under program control. Each 8251A provides
full duplex, double-buffered, transmit and receive capability. Parity, overrun, and framing error detection
are all incorporated in each USART. Each channel is
fully buffered to provide a direct interface to RS232C
compatible terminals, peripherals, or synchronous/
asynchronous modems. Each channel of RS232C
command lines, serial data lines, and signal ground
lines are brought out to 26-pin edge connectors that
mate with RS232C flat or round cable.
EPROM/ROM Capacity
Sockets for up to 8K bytes of nonvolatile read only
memory are provided on the iSBC 544 board. Read
only memory may be added in 2K byte increments
up to a maximum of 4K bytes using Intel 2716
EPROMs or masked ROMs; or in 4K byte increments up to 8K bytes maximum using Intel 2732
EPROMs. All on-board EPROM/ROM operations
are performed at maximum processor speed.
RAM Capacity
The iSBC 544 contains 16K bytes of dynamiC read/
write memory using Intel 2117 RAMs. Power for the
on-board RAM may be provided on an auxiliary power bus, and memory protect logic is included for
RAM battery backup requirements. The iSBC 544
contains a dual port controller, which provides dual
port capability for the on-board RAM memory. RAM
accesses may occur from either the on-board 8085A
CPU or from another bus master, when used as an
intelligent slave. Since on-board RAM accesses do
not require the MULTIBUS, the bus is available for
concurrent bus master use. Dynamic RAM refresh is
accomplished automatically by the iSBC 544 for accesses originating from either the CPU or from the
MULTIBUS.
Parallel I/O Port
The iSBC 544 provides a 10-bit parallel I/O interface
controlled by an Intel 8155 Programmable Interface
(PPI) chip. The parallel I/O port is directly compatible with an Automatic Calling Unit (ACU) such as the
8-26
inter
iSBC® 544 COMMUNICATIONS CONTROLLER
vals. The sixth PIT timer/counter (TINT1) can be
used to generate interrupt intervals to the on-board
8085A. In addition to the timer/counters on the 8253
PITs, the iSBC 544 has a 14-bit timer available on
the 8155 PPI providing a third general use timer /
counter (TINTO). This timer output is jumper selectable to the interrupt structure of the on-board 8085A
CPU to provide additional timer/counter capability.
Addressing - On board RAM, as seen by the onboard 8085A CPU, resides at address 8000HBFFFH. On-board RAM, as seen by an off-board
CPU, may be placed on any 4K byte address boundary. The iSBC 544 provides extended addressing
jumpers to allow the on-board RAM to reside within
a one megabyte address space when accessed via
the MULTIBUS. In addition, jumper options are provided which allow the user to protect 8K or 12K
bytes on-board RAM for use by the on-board 8085
CPU only. This reserved RAM space is not accessible via the MULTIBUS and does not occupy any system address space.
Timer Functions - In utilizing the iSBC 544 board,
the systems designer simply configures, via software, each timer independently to meet systems requirements. Whenever a given baud rate or interrupt
interval is needed, software commands to the programmable timers select the desired function. The
on-board PITs together with the 8155 provide a total
of seven timer/counters and six operating modes.
Mode 3 of the 8253 is the primary operating mode of
the four dedicated USART baud rate generators.
The timer/counters and useful modes of operation
for the general use timer/counters are shown in Table 1.
Static RAM - The iSBC 544 board also has 256
bytes of static RAM located on the Intel 8155 PPI.
This memory is only accessible to the on-board
8085A CPU and is located at address 7FOOH7FFFH·
Programmable Timers
The iSBC 544 board provides seven fully programmable and independent interval timer/counters utilizing two Intel 8253 Programmable Interval Timers
(PIT), and the Intel 8155. The two Intel 8253 PITs
provide six independent BCD or binary 16-bit interval
timer/counters and the 8155 provides one 14-bit binary timer/counter. Four of the PIT timers (BDGO-3)
are dedicated to the USARTs providing fully independent programmable baud rates.
Interrupt Capability
The iSBC 544 board provides interrupt service for up
to 21 interrupt sources. Any of the 21 sources may
interrupt the intelligent controller, and all are brought
through the interrupt logic to 12 interrupt levels. Four
interrupt levels are handled directly by the interrupt
processing capability of the 8085A CPU and eight
levels are serviced from an Intel 8259A Programmable Interrupt Controller (PIC) routing an interrupt request output to the INTR input of the 8085A (see
Table 2).
Three General Use Timers - The fifth timer
(BDG4) may be used as an auxiliary baud rate to any
of the four USARTs or may alternatively be cascaded with timer six to provide extended interrupt inter-
Table 1. Programmable Timer Functions
Function
Operation
Interrupt on Terminal
Count (Mode 0)
When terminal count is reached, an interrupt request is
generated. This function is useful for generation of realtime clocks.
Rate Generator
(Mode 2)
Divide by N counter. The output will go low for one input
clock cycle and high for N - 1 input clock periods.
Square-Wave Rate
Generator (Mode 3)
Output will remain high until one-half the TC has been
completed, and go low for the other half of the count.
This is the primary operating mode used for generating a
Baud rate clocked to the USARTs.
Software Triggered
Strobe (Mode 4)
When the TC is loaded, the counter will begin. On TC
the output will go low for one input clock period.
Single Pulse
Single pulse when TC reached.
Counter
8253
TINT1
8253
BDG4*
8253
BDGO-4
TINT1
8253
BDG4*
TINT1
8155
TINTO
Repetitive Single Pulse
Repetitive single pulse each time TC is reached until a
new command is loaded.
8155
TINTO
• BDG4 is jumper selectable as an auxiliary baud rate generator to the USARTs or as a cascaded output to TINT1. BDG4
may be used in modes 2 and 4 only when configured as a cascaded output.
8-27
inter
iSBC® 544 COMMUNICATIONS CONTROLLER
to the 808SA interrupt inputs, TRAP, RST 7.5, RST
6.5 and RST 5.5 have a unique vector memory address. An 8085A jump instruction at each of these
addresses then provides ·software linkage to interrupt service routines located independently anywhere in the Memory. All interrupt inputs with the
exception of the TRAP may be masked via software.
Table 2 Interrupt Vector Memory Locations
Interrupt
Source
Vector
Location
. Interrupt
Level
Power Fail
TRAP
24H
8253TINT1
RST7.5
3CH
8155 TINTO.
Ring Indicator(1) RST 6;5
34H
Carrier Detect
Flag Interrupt
RST5.5
2CH
INTO/-INT7/(10f8)
RXRDYO
INTR
Programmable
TXRDYO
RXRDY1
TXRDY1
RXRDY2
TXADY2
RXRDY3
TXRDY3
1
2
3
8259A Interrupts - Eight interrupt sources signal.
ing transmitter and receiver ready from the four
USARTs are channeled directly to the Intel 8259A
PIC. The PIC then provides vectoring for the next
eight interrupt levels. Operating mode and priority
assignments may be reconfigured dynamically via
software at any time during system operation. The
PIC accepts transmitter and receiver interrupts from
the four USARTs. It then determines which of the
incoming requests is of highest priority, determines
whether this request is of higher priority than the level currently being serviced, and , if appropriate, issues an interrupt to the CPU. The output of the PIC
is applied directly to the INTR input of the 808SA.
Any combination of interrupt levels may be masked,
via software, by storing a single byte in the interrupt
mask register of the PIC. When the !3085A responds
to a PIC interrupt, the PIC will generate a CALL instruction for each interrupt level. These addresses
are equally spaced at intervals of 4 or 8 (software
selectable) bytes. Interrupt response to the PIC is
software programmable to a 32- or 64-byte block of
memory. Interrupt sequences may be expanded
from this block with a single 8085A jump instruction
at each of these addresses.
4
5-12
NOTE:
1. Four ring indicator interrupts and four carrier detect interrupts are summed to the RST 6.5 input. The 8155 may be
interrogated to inspect anyone of the eight signals.
Interrupt Sources - The 22 interrupt sources originate from both on-board communications functions
and the MULTIBUS. Two interrupts are routed from
each of the four USARTs (8 interrupts total) to indicate that the transmitter and receiver are ready to
move a data byte to or from the on-board CPU. The
PIC is dedicated to accepting these 8 interrupts to
optimize USART service request. One of eight interrupt request lines are jumper selectable for direct
interface from a bus master via the system bus. Two
auxiliary timers (TINTO from 8155 and TINT1 from
8253) are jumper selectable to provide general purpose counter/timer interrupts. A jumper selectable
Flag Interrupt is generated to allow any bus master
to interrupt the iSBC 544 by writing into the base
address of the shared dual port memory accessable
to the system. The Flag Interrupt is then cleared by
the iSBC 544 when the on-board processor reads
the base address. This interrupt provi(jes an interrupt link between a bus master and intelligent slave
(see System Programming). Eight inputs from the
serial ports are monitored to detect a ring indicator
and carrier detect from each of the four channels.
These eight interrupt sources are summed to a single interrupt level of the 808SA CPU. If one of these
eight interrupts occur, the 8155 PPI can then be interrogated to determine which port caused the interrupt. Finally, a jumper selectable Power Fail Interrupt
is available from the MULTIBUS to detect a power
down condition.
Interrupt Output - In addition, the iSBC 544 board
may be jumper selected to generate an interrupt
from the on-board serial output data (SOD) of the
8085A. The SOD signal may be jumpered to anyone
of the 8 MULTIBUS interrupt lines (INTOI-INT7/) to
provide an interrupt signal directly to a bus master.
Power-Fail Control
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow Signal from
the iSBC 635 Power Supply or equivalent.
Expansion Capabilities
When the iSBC 544 board is used as a single board
communications controller, memory and I/O capacity may be expanded and additional functions added
using Intel MULTIBUSTM compatible expansion
boards. In this mode, no other bus masters may be
configured in the system. Memory may be expanded
to a 65K byte capacity by adding user specified combinations of RAM boards, EPROM boards, or combination boards. Input/output capacity may be increased by adding digital 1/0 and analog I/O expan-
8085 Interrupt - Thirteen of the twenty-two interrupt sources'· are available directly to four interrupt
inputs of the on-board 8085A CPU. Requests routed
8-28
iSBC® 544 COMMUNICATIONS CONTROLLER
vides a linker, object code locater, and library manager. A unique in-circuit emulator (ICE-85) option
provides the capability of developing and debugging
software directly on the iSBC 544 board.
sion boards. Furthermore, multiple iSBC 544 boards
may be included in an expanded system using one
iSBC 544 board as a single board communications
computer and additional controllers as intelligent
slaves.
SPECIFICATIONS
System Programming
Serial Communications Characteristics
In the system programming environment. the
iSBC 544 board appears as an additional RAM
memory module when used as an intelligent slave.
The master CPU communicates with the iSBC 544
board as if it were just an extension of system memory. Because the iSBC 544 board is treated as memory by the system, the user is able to program into it
a command structure which will allow the iSBC 544
board to control its own I/O and memory operation.
To enhance the programming of the iSBC 544
board, the user has been given some specific tools.
The tools are: 1) the flag interrupt, 2) an on-board
RAM memory area that is accessible to both an offboard CPU and the on-board 808SA through which a
communications path can exist, and 3) access to the
bus interrupt line.
Synchronous -
5-8 bit characters; automatic
sync insertion; parity.
Asynchronous -
5-8 bit characters; break character generation; 1, 1%, or 2
stop bits; false start bit detection; break character detection.
Baud Rates
Frequency (KHz)(1)
Baud Rate (Hz)(2)
(Software
Selectable)
Synchronous Asynchronous
Flag Interrupt - The Flag Interrupt is generated
anytime a write command is performed by an offboard CPU to the base address of the iSBC 544
board's RAM. This interrupt provides a means for
the master CPU to notify the iSBC 544 board that it
wishes to establish a communications sequence. In
systems with more than one intelligent slave, the
flag interrupt provides a unique interrupt to each
slave outside the normal eight MULTIBUS interrupt
lines (INTO/ -INT7 I).
153.6
76.8
38.4
19.2
9.6
4.8
6.98
38400
19200
9600
4800
6980
+16
+64
9600
4800
2400
1200
600
300
2400
1200
600
300
150
75
110
-
NOTES:
1. Frequency selected by I/O writes of appropriate 16-bit
frequency factor to Baud Rate Register.
2. Baud rates shown here are only a sample subset of possible software programmable rates available. Any frequency from 18.75 Hz to 614.4 KHz may be generated utilizing
on-board crystal oscillator and 16-bit Programmable Interval Timer (used here as a frequency divider).
On-Board RAM - The on-board 16K byte RAM
area that is accessible to both an off-board CPU and
the on-board 8085A can be located on any 4K
boundary in the system. The selected base address
of the iSBC 544 RAM will cause an interrupt when
written into by an off-board CPU.
Bus Access - The third tool to improve system
operation as an intelligent slave is access to the
MULTIBUS interrupt lines. The iSBC 544 board can
both respond to interrupt signals from an off-board
CPU, and generate an interrupt to the off-board CPU
via the MULTIBUS.
8085A CPU
Word Size -
8, 16 or 24 bits/instruction; 8 bits of
data
Cycle Time - 1.45/I-I-S ±0.01 % for fastest executable instruction; i.e., four clock cycles.
Clock Rate- 2.76 ~Hz ± 0.1%
System Development Capability
The development cycle of iSBC 544 board based
products may be significantly reduced using the Intellec series microcomputer development systems.
The Intellec resident macroassembler, text editor,
and system monitor greatly simplify the design, development and debug of iSBC 544 system software.
An optional ISIS-II diskette operating system pro-
System Access Time
Dual port memory -
740 ns
NOTE:
Assumes no refresh contention.
8-29
inter
iSBC®544 COMMUNICATIONS CONTROLLER
Memory Capacity
Interrupts
On-Board ROM/PROM installed ROM or EPROM
On-Board Static RAM -
4K, or 8K bytes of user
Address for 8259A Registers (Hex notation, I/O
address space)
256 bytes on 8155
E6
E6
E7
E6
E7
E6
On-Board Dynamic RAM (on-board access) 16K bytes. Integrity maintained during power failure
with user-furnished batteries (<>ptional)
On-Board Dynamic RAM (MULTIBUS access) 4K, 8K, or 16K bytes available to bus by swtich selection
Memory Addressing
NOTE:
Several registers have the same physical address:
Sequence of access and one data bit of the control
word determine,s which register will respond.
Interrupt levels routed to the 8085 CPU automatically vector the processor to unique memory locations:
On-Board ROM/PROM - O-OFFF (using 2716
EPROMs or masked ROMs); 0-1 FFF (using 2732A
EPROMs)
On-Board Static RAM -
Interrupt request register
In-service register
Mask register
Command register
Block address register
Status (polling register)
24 TRAP
3C RST 7.5
34 RST 6.5
2C RST 5.5
256 bytes: 7FOO-7FFF
On-Board Dynamic RAM (on-board access) 16K bytes: 8000-BFFF.
On-Board Dynamic RAM (MULTIBUS® access) any 4K increment OOOOO-FFOOO which is switch and
jumper selectable. 4K, 8K or 16K bytes can be made
available to the bus by switch selection.
Timers
Addresses for 8253 Registers (Hex notation, 1/0
address space)
Programmable Interrupt Timer One
08
Timer 0
BOGO
09
Timer 1
BDG1
DA
Timer 2
BDG2
DB
Control register
1/0 Capacity
Serial - 4 programmable channels using four
8251A USARTs
Programmable Interrupt Timer Two
DC
Timer 0
DO
Timer 1
,DE
Timer 2
OF
Control register
Parallel - 10 programmable lines available for Bell
801 ACU, or equivalent use. Two auxiliary jumper
selectable signals
BDG3
BDG4
TINT1
Address for 8155 Programmable Timer
E8
Control
Timer (LSB)
TINTO
Timer (MSB)
TINTO
ED
1/0 Addressing
On-Board Programmable I/O
Port
Data
Control
USARTO
USART 1
USART2
USART3
8155 PPI
DO
02
04
06
E9 (PortA)
EA (Port B)
EB (PortC)
01
03
05
07
E8
Inpot Frequencies - Jumper selectable reference
1.2288 MHz ± 0.1% (0.814 /A-s period nominal) or
1.843 MHz ± 0.1 % crystal (0.542 /A-s period, nominal)
8-30
inter
ISBC~
544 COMMUNICATIONS CONTROLLER
Output Frequencies (at 1.2288 MHz)
Function
Single
Timer/Counter
Min
Dual Timer/Counter
(two timers cascaded)
Max
Min
Max
Real-Time Interrupt Interval
1.63,...s
53.3,...s
3.26,...s
58.25 min
Rate Generator (frequency)
18.75 Hz
614.4 KHz
0.00029 Hz
307.2 KHz
Interfaces
Connectors
Serial I/O - EIA Standard RS232C signals provided and supported:
Carrier Detect
Clear to Send
Data Set Ready
Data Terminal Ready
Request to Send
Receive Clock
Receiver Data
Ring Indicator
Secondary Receive Data"
Secondary Transmit Data "
Transmit Clock
Transmit Data
DTE Transmit clock
• Optional if parallel 1/0 port is not used as Automatic Calling Unit.
Centers
(In.)
Mating
Connectors
Bus
86
0.156
Viking
2KH43/9AMK12
Parallel I/O
50
0.1
3M 3415-000 or
AMP 88083-1
Serial I/O
26
0.1
3M 3462-000 or
AMP 88373-5
Memory Protect
Parallel I/O - Four inputs and eight outputs (includes two jumper selectable auxiliary outputs). All
Signals compatible with EIA Standard RS232C. Directly compatible with Bell Model 801 Automatic
Calling Unit, or equivalent.
MULTIBUS -
Pins
(qty)
Interface
An active-low TTL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during the system power-down sequences.
Compatible with iSBC MULTIBUS.
On-Board Addressing
Bus Drivers
All communications to the parallel and serial I/O
ports, to the timers, and to the interrupt 'controller,
are via read and write commands from the on-board
8085A CPU.
Auxiliary Power
Function
Characteristic
Sink
Current (mA)
Data
Address
Commands
Tri-state
Tri-state
Tri-state
50
15
32
NOTE:
Used as a master in the single board communications
computer mode.
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.
Physical Characteristics
Width:
Depth:
8-31
30.48 cm (12.00 inches)
Thickness:
17.15 cm (6.75 inches)
1.27 cm (0.50 inch)
Weight:
3.97 gm (14 ounces)
ISBC@,544 COMMUNICATIONS CONTROLLER
,
,
'"
Electrical Characteristics
.
DC Power Requlr.ments
.,1,
Current Requirements
Vee = +5V ±5%
(max),
VDD = ± 12V ±5%
(max)
Vaa = - 5V(3) ± 5%
(max)
VAA= -12V ±5%
(max)
With 4K EPROM
(using 2716)
Icc = 3.4A max
100 = 350 mA max
lee = 5mAmax
IAA =' 200 mA max
Without EPROM
Configuration
3.3Amax
350mAmax
5mAmax
200 mA max
RAMonly(1)
390mAmax
176 mA max
5mAmax
-
RAM(2) refresh
only
390mAmax
20mAmax
5mAmax
NOTES:
1. For operational RAM only, for AUX power supply rating.
2. For RAM refresh only. Used for battery backup requirements. No RAM accessed.
3. Vee is normally derived on-board from VAA, eliminating the need for a Vee supply. If it is desired to supply Vee from the
bus, the current requirement is as shown.
Reference manuals are shipped with each product
only if designated SUPPLIED (see above). Manuals
may be ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, California 95051.
Environmental Characteristics
Operating Temperature: O°C to 55°C (32"F to 131°F)
Relative Humidity: To 90% without condensation
Reference Manual
ORDERING INFORMATION
502160 - iSBC 544 Intelligent Communications
Controller Board Hardware Reference Manual (NOT
SUPPLIED)
8-32
Part Number
Description
iSBC 544
Intelligent Communications Controller
ISBt® 548/549 TERMINA ... tONTRO ...... ERS
HIGH PERI'fJRMA.Nt:E 'I'ERMINA.£ t:ONTIlfIUER BOA.RDS 1'011
MIJ£'I'IBIJS@I
The iSBC 548 and iSBC 549 are intelligent terminal controllers for MULTIBUS I applications. The
iSBC 548 provIdes baSic multiuser support with 8 channels of RS 232 Asynchronous interface. The
iSBC 549 combines 4 srrial channels with a real-time clock and a line printer interface. Acting as
intelligent slaves for communication expansion, these boards provide high performance, low cost
solutions for multi-user systems.
I'EA.TIJRES
ISBC 548 FEATURES
• Supports eight channels asynchronous
RS232 interface
ISBC 549 FEATURES
• Supports four channels asynchronous RS232
interface
• Line printer interface
• Real-time clock/calendar with battery backup
STANDARD ISBC 548/549 FEATURES
• 8 MHz 80186 Microprocessor
• Supports transfer rates up to 19.2K Baud
• 128K Bytes Zero \Vail State DRAM (32K Dual
Port)
• Supports t'ull Duplex Asynchronous
Transmissions
• Jumprr sriectahir memory mappmg, 1/0
mapping and MULTIBUS Interrupts
intel'---------In(('1 Corporation assuml'~ nu I'('SptmSllllllt~ fnr tht' O:oi/' uf 3n\ rtr('Ullr) nlill'r lhan ('11'('tlltr~ ('mhrwlwtlln dO Intel prorjll('l NtllIt.ht'I'l'il'fUil pau.'nt 1i(\'MI'<{ Ill'('
Implied Irlfurmatlon ronl311lrd m'rt'ln sUp!.'fSt'dt'!\ prt·\ IlluSI~ pUhl~'1ht'tl ~JX'rlflnlllum; 1m IIlt'St' dfVII't'S fmm InLl'! and IS subll'rt 10 I'hang.:: wlIhmn nutu~·
Scptcmhl'r. 198B
@ Intel CorporatIOn 1988
Order Numht'f 2H0674 001
8-33
FEATURES
IISI'NCHRONOllS RS232 INTERFIIQ:·
..
SllPPORT
. .. .
The ISBC 5481549 .\s~ nchronous RS232 Internal suppurt is
presented in DTE Configuration. 825~Q Sl'riHI
Communications Controllers (SCCS) pro\Ide channel~ of halfl
full duple\ senalllO. Conflgurabj)it~ of the 82530 alli)l\s
handling all as~ nchronous data formats regardless of data
,iU'. rlumhrJ' of start or stop bits. or parit~ reqUlrcments.
The s~ nchronous transmission features of the 82530 are
not supported ..\n on-chip baud rate generator allows
independent baud rate~ on each channel. The serlallil1t's
can be brought to the bac~-panel Iia -W-Pln connectors and
nbbon c a b l e . ·
.
LINE PRINTER INTERFIICE
The iSBC 549 mcorporates astandarcl line printer intel'farl'
rumpatible Ilith IB'" or Centronics" line printers.
Intelligent buffering on the iSBC 3·19 allolls the CPl' to
offload pnntmg tas~s and return to higher priorit~ lobs.
REIIL-TIME CLOCIVCIILENDIIR
MEMOR},
TheiSBG ;'481549 have three areas o(memory rm-board:
dual-port RAM, private RAM, and EPROM. J<:ach board
contains 128K bytes of on-bo3f'
.....
co
co
......
7
,......
SERIAL
COMMUNtCATIONS
0
aJ
00
0.
CO
CONTROLLER
(82530)
..
0
I»
C.
."
:::s
!l
0"
'"<
aJ
c
iii"
COMMUNICATIONS
CONTROLLER
(82530)
Ui
INTERRUPT
iSBX·
isaX"
CONTROl.
(2-8259As)
IIULTlIIODULE"
-MULTIMOOULE'·
CONNECTOR
CONNECTOR
1~~PL7
OPTION
82258ADMA
DMACONTRDL
(OPTION)
{
80186
CPU
8 MHZ
10
iil
11
3
....,.
......
...
1 I
512KBYTES
DRAM
~
....00®
0)
I'
{
FOUR 2a.P1N SITES
JEDEC
MEMORY
I
(OPTION)
FOUR 28-PIN SITES
L
~iJ'
o
)
ON·BOARO flO LOCAL BUS
:::s
!!!.
~
1
SERIAL
}
..0:
~
C
0"
()
SERIAL
COMMUNICATIONS
CONTROUER
(82530)
I
I
..J
~
rv
IIULTIBUS' II
iPSB
INTERFACE
~
f'rV
8751
,.coNTROLLER
(INTERCONNECTI
BlST)
;..
ON"BOARD MEMORY LOCAL BUS
A
MULTIBUS" II PARALLEL SYSTEM BUS
1.1
280268-4
intJ
ISBC® 186/410
DIRECT MEMORY ACCESS (DMA) FUNCTION
SERIAL I/O SUBSYSTEM
The iSBC 186/410 board provides 13 channels of
DMA to support serial I/O, iPSB interlace, and/or
iSBX bus transfer operations. The 80186 microprocessor provides two DMA channels, the 82258 Advanced (ADMA) controller supports three "direct"
channels of DMA, and the ADMA multiplexer circuit
uses the fotJrth 82258 ADMA channel providing
eight additional multiplexed DMA channels. The allocation of the board's DMA channels to on-board resources is listed in Table 1.
Six serial interlaces are provided on the iSBC
186/410 board: two interlaces support full asynchronous, byte-synchronous, and bit-synchronous
(HDLC/SDLC) communication and four interlaces
support asynchronous-only communication. The two
RS422A configurable ports can also be tri-stated to
allow multi-drop networks. The board's serial capability can be expanded to 10 channels by adding two
iSBX 354 Dual Channel Serial I/O MULTIMODULE
boards. Each added iSBX 354 board uses an
Table 1.ISBC@ 186/410 Board DMA Channel Allocation
Channel
Count
DMA Configuration
Local Bus Resource
Channel
Number
80186
1
DMAChannel
0
Half-Duplex High Speed Serial Interlace (SCC1 Channel A)
(-High Density 15·Pin Connector)
2
DMAChannel
1
Full-Duplex Serial Interlace (SCC1 Channel A) or SBX1 DMA Request
0
Input DMA from MPC (Message Passing Coprocessor)
82258ADMA
3
DMAChannel
4
DMAChannel
1
Output DMA to MPC
5
DMAChannel
2
Half-Duplex High Speed Serial Interlace (SCC1 Channel B)
(-High Density 15-Pin Connector) or SBX1 DMA REQ
DMAChannel
3
Full-Duplex High Speed Serial Interlace (SCC1 Channel B) or
INT2 DMA REQ from DMA Multiplexer
DMA Multiplexer"
6
DMAChannel
0
Half-Duplex Serial Interlace (SCC2 Chan. A, 9-pin conn.)
7
DMAChannel
1
Full-Duplex Serial Interlace (SCC2 Chan. A)
8
DMAChannel
2
Half-Duplex Serial Interlace (SCC2 Chan. B, 9-pin conn.)
9
DMAChannel
3
Full-Duplex Serial Interlace (SCC2 Chan. B) or SBX1 DMA Request
or Half-Duplex SCC1 Channel B.
10
DMAChannel
4
Half-Duplex Serial Interlace (SCC3 Chan. A, 9-pin conn.)
Full-Duplex Serial Interlace (SCC3 Chan. A) or SBX2 DMA Request
11
DMAChannel
5
12
DMAChannel
6
Half-Duplex Serial Interlace (SCC3 Chan. B, 9-pin conn.)
13
DMAChannel
7
Full-Duplex Serial Interlace (SCC3 Chan. B) or INT1 SBX1 for
SBX344
NOTE:
• ADMA Channel 3 is used to add the DMA Multiplexer.
8-57
inter
iSBC® 186/410
SOLe) modes. The increased capability at the serial
controller pOint results in off-loading a CPU of tasks
normally assigned to the CPU or its associated hardware. Configurability of the 82530 allows the user to
configure it to handle all asynchronous data formats
regardless of data size, number of start or stop bits,
or parity requirements. An on-chip baud rate generator allows independent baud rates on each channel.
82530 SCC component to provide two independent
full duplex serial channels configurable as either
RS232C or RS422A interfaces. It also supports both
asynchronous or programmable byte and bit synchronous (HOLC/SOLe) protocols. The HOLel
SOLC interface is compatible with IBM system and
terminal equipment and with CCITT's X.25 packet
switching interface.
Three 82530 Serial Communications Controllers
(SCCs) provide six channels of half/full serial 1/0.
Two channels are configurable as either RS232C or
RS422 on two high density 15-pin female O-shell
connectors. Four more channels are RS232C-only
using IBM standard 9-pin male O-shell connectors.
All six channels directly support the Data Terminal
Equipment (OTE) configuration, with the Data Communication Equipment (OCE) pin-out supported by
changes in the cable wiring.
Memory Subsystem
The iSBC 186/410 board's on-board memory subsystem consists of a large DRAM array and a set of
universal memory sites. Access to the on-board
memory subsystem resources, as well as off-board
iPSB bus access, is accomplished by observing the
iSBC 186/410 board memory map (see Figure 4).
The mapping occurs within the 1 megabyte memory
space of the 80186 microprocessor, and is split into
three main areas: DRAM reserved, iPSB window,
and EPROM reserved. The first 0 to 512K bytes is
always reserved for local DRAM, the next 128K or
The 82530 component is designed to satisfy several
serial communications requirements; asynchronous,
pyte-synchronous, and bit-synchronous (HOLCI
IPSB
MEMORY
MAP
D'''-MBII
MEMORY
186/410
MEMORY
MAP
1024K
ONBOARD
EPROM
768K
WINDOW MAY BE
128K OR 256K
640K
-
IPSB
WiNDOW-
MBII
WINDOW
BASE ADDRESS IS ANY MULTIPLE OF 128K
_ - "+-;':';;';:'::";;'':'':'''''1-- OR 256K (SIZE OF MULTIPLE =WINDOW SIZE)
512K
ON·
BOARD
DRAM
o
....._ _....1 0
280268-5
Figure 4. iSBC® 186/410 Board Memory Map Diagram
8-58
inter
ISBC® 186/410
256K bytes (or up to 768K) is the iSPB window, and
the remaining 384K or 256K byte area is reserved
for local EPROM. The iPSB window maps a 128K or
256K byte local memory area into the 4 gigabyte
global physical address range of the MULTIBUS II
iPSB bus. This window is programmable and allows
the 80186 processor to access the complete 4 gigabyte memory space of the iPSB bus.
tervals under software control. The outputs may be
independently routed to a PIC to count external
events. The system software configures each timer
independently and can read the contents of each
counter at any time during system operation.
In a MULTIBUS II system, external interrupts (interrupts originating from off-board) are interrupt type
messages over the iPSB bus rather than signals on
individual lines. Interrupt type messages are handled
by the bus interface logic, the MPC Message Passing Coprocessor chip. The MPC component interrupts the 80186 processor via an 8259A Programmable Interrupt Controller (PIC) indicating a message has been received. This means that 1 Interrupt
line can handle interrupts from up to 255 sources.
The board's memory map also supports a 64K byte
access window for 1/0 space between local arid
iPSB bus access. The 64K bytes of local 1/0 space
is mapped 1-to-1 to the iPSB bus' 64K byte 1/0
space and is not programmable. The upper 32K
bytes access the iPSB bus 1/0 space, and the lower
32K bytes are reserved for local on-board 1/0.
Two on-board 8259A PICs are used in a masterslave configuration for processing on-board interrupts. One of the interrupt lines handles the interrupt
messages received from the iPSB bus. Table 2 includes a list of devices and functions supported.
DRAM CAPABILITIES
The iSBC 186/410 board comes standard with a
512K byte DRAM memory array on-board.
EPROM MEMORY
ISBXTM BUS 110 EXPANSION
A total of four 28-pin JEDEC universal sites reside
on the iSBC 186/410 board. These sockets support
addition of byte-wide ROM and EPROM devices in
densities from 8K bytes (2764) to 64K bytes (27512)
per device. Two of the four sockets contain a pair of
27812 EPROM devices installed at the factory(1).
These devices contain 128K bytes of firmware providing both the Host-to-controller download routine
and the Built-In-Self-Test (BIST) power-up diagnostics routine. The remaining two sockets allow the
user to add either two additional devices or an iSBC
341 EPROM MULTIMODULE for a maximum of
512K bytes.
NOTE:
(1) These devices may be removed by the user for
access to the two 28-pin sites.
Two 8/16-bit iSBX bus (IEEE P959) connectors are
provided for modular, low-cost 1/0 expansion. The
iSBC 186/410 board supports both 8-bit and 16-bit
iSBX MULTIMODULEs through these mating, gastight pins and socket connectors. DMA is also supported to the iSBX connectors and can be configured by programming the DMA multiplexor attached
to the 82258 ADMA component. The iSBX connectors on the iSBC 186/410 board support a wide variety of standard iSBX compatible boards from Intel
and other independent vendors providing add-on
functions such as, floppy control, %" tape control,
bubble memory, parallellserialllO, BITBUSTM interface, math, graphics, IEEE 488, and analog 110.
Custom iSBX module designs are also supported as
per the IEEE P959 iSBX bus specification.
General 1/0 Subsystem
IPSB Bus Interface Subsystem
The 1/0 subsystem provides timers, interrupt control
and two IEEE P959 iSBX connectors for 1/0 expansion or customization.
This subsystem's main component is the Message
Passing Coprocessor chip. Subsystem services provided by the MPC bus interface component include
full message passing support and memory, 1/0, and
interconnect access to the iPSB bus by the 80186
processor. The single-chip Message Passing Coprocessor is a highly integrated CHMOS. device implementing the full message passing protocol and
performing all the arbitration, transfer, and exception
cycle protocols specified in the MULTIBUS II Architecture Specification Rev. C., Order Number
1'46077.,
PROGRAMMABLE TIMERS AND INTERRUPT
CONTROL
The 80186 microprocessor on the iSBC 186/410
board provides three independent, ,fully programmable 16-bit interval timerslevent counters for use by
tile systems designer to generate accurate time in-
8-59
inter
iSBC® 186/410
Table 2.ISBC® 186/410 Board Interrupt Devices and Functions
Device
Function
Number of
Interrl,lpts
iPSB Bus Interface (MPC)
Message-Based Interrupt Requests from the iPSB
bus via MPC Messag~ Passing Coprocessor
1 interruptfor
up to 255
sources
8751 Interconnect Controller
Interconnect Space
1
80186 Timers & Interrupt
Timers 0 and 1 and Interrupt Acknowledge 1
3
82530 SCCs (3 devices)
SCC # 1 and SCC # 2 or SCC #3 for Transmit
Buffer Empty, Receive Buffer Full, and Channel
Errors
2
iPSB Bus Interface (MPC)
Indicates Transmission Error on iPSB Bus
1
82258ADMA
DMA Transfer Complete
1
iEEE P959 iSBX Bus Connectors (2)
Functions Determined by iSBX Bus
MULTIMODULE Boards
IEEE P959 iSBX Bus Connectors (2)
4
(2/ connector)
DMA Interrupt from iSBX (TDMA)
2
for the exclusive use of the download program. Host
CPUs must not overwrite this area with download
commands.
Interconnect Subsystem
MULTIBUS II interconnect space is a standardized
set of software configurable registers designed to
hold and control board configuration information as
well as system and board level diagnostics and test·
ing information. Interconnect space is implemented
with the 8751 microcontroller and the MPC silicon
resident on the iSBC 186/410 board.
Software on the host is responsible for accessing
the iSBC 186/410 board's firmware on disk or from
ROM visible to the host and translating it into linear
sequences of bytes suitable for downloading (see
Figure 5). After downloading the firmware, the host
issues a command for the loader routine on the controller to begin execution of the downloaded software.
The read-only registers store information such as
board type, vendor 1.0., firmware rev. level, etc. The
software configurable registers are used for autosoftware configurability and remote/local diagnostics and testing.
BUILT·IN SELF·TEST DIAGNOSTICS
On-board built-in self-test (BISn diagnostics provide
a customer confidence test of the various functional
areas on the iSBC 186/410 board. The initialization
checks are performed by the 8751 microcontroller,
while the BIST package is executed by the 80186
microprocessor. On-board tests includ~d in the BIST
package are: DRAM, EPROM, 80186, 82530 SCCs,
and the MPC.
Firmware Capability
HOST/CONTROLLER SOFTWARE DOWNLOAD
ROUTINE
Resident in ROM on this controller is a host-to-controller software download routine to support the
downloading of communication firmware into the
iSBC 186/410 Serial Communication Computer.
This loader adheres to the MULTIBUS II Download
Protocol and responds to commands issued by software running on a host CPU board. The host CPU
passes these commands to the loader via registers
defined in the board's interconnect space. A download function, a commence execution function, and
an examine local memory function are all provided in
the routine. Data transfers are supported by both
shared memory systems and message based systems. The top 1K of DRAM on the board is reserved
Additional activities performed include initialization
at power-up using the Initialization and Diagnostics
Executive and a program table check, a feature allowing users to add custom code in EPROM while
still maintaining full use of factory supplied BISTs.
Immediately after power-up and initialization of the
8751 microcontroller, the 80186 microprocessor begins its own initi~lizatiqn and on-board diagnostics.
Upon successful completion of these ac;tivities, the
Initialization and Diagnostics Executive invokes the
user-defined program table. A check is made of the
program table which then executes user-defined
custom programs.
8-60
inter
iSBC® 186/410
FIRMWARE
r--+......H_O_S_T.,
os
CONTROLLER
ROM BASED
DOWNLOAD
ROUTINE
IPSB BUS
280268-6
Figure 5. Download Routine
The BIST package provides a valuable testing, error
reporting and recovery capability on MULTIBUS II
boards enabling the OEM to reduce manufacturing
and maintenance costs. An LED on the board's front
panel indicates the status of power-up diagnostics. It
is on when BIST diagnostics start running and is
turned off upon successful completion of the BISTs.
NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le., 4 clock cycles).
Memory Capacity
Local Memory
SPECIFICATIONS
DRAM-512K bytes on-board (64K x 4-bit devices);
8 sockets provided to support additional 256K bytes
Word Size
EPROM-Number of sockets-four 28-pin JEDEC
sites
Instruction: 8-, 16-, 24-, 32-, 40-, or 48-bits
Data: 8- or 16-bits
EPROM
Device Size
(Bytes)
Max. Memory
Capacity
System Clock
2764
27128
27256
27512
8K
16K
32K
64K
32K bytes
64K bytes
128K bytes
256K bytes
CPU: 8.0 MHz
NOTE:
**EPROM Expansion to up to a maximum of 512K bytes is
achieved via attachment of the iSBC 341 EPROM (256K
byte) MULTIMODULE board.
Cycle Time
Basic Instruction: 8.0 MHz-500 ns
I/O Capability
Serial-Six programmable serial channels using
three 82530 Serial Communications Controller components.
8-61
inter
iSBC® 186/410
I/O Expansion-Two 8/16-bit IEEE P959 iSBX connectors (DMA supported). (The board supports either two single wide or one double-wide form factor
iSBX module(s).)
Baud Rates
Synchronous X1 Clock
(Channels 0,1)
Timers-Three programmable timers on the 80186
microprocessor.
Baud Rate
82530 Count Value
(Decimal)
64000
48000
19200
9600
4800
2400
1800
1200
300
36
49
126
254
510
1022
1363
2046
8190
Input Frequencies-Frequencies supplied by the internal 80186 16 MHz crystal; 82530 SCCs: crystal
driven at 9.8304 MHz div. by two; iSBX Connector:
crystal driven at 9.8304 MHz.
Serial Communications Characteristics
Synchronous-Internal or external character synchronization on one or two synchronous characters.
Asynchronous X16 Clock
(Channels 0-5)
Asynchronous-5-8 data bits and 1, 1% or 2 stop
bits per character; programmable clock factor; break
detection and generation; parity, overrun, and framing error detection.
Baud Rate
82530 Count Value
(Decimal)
19200
9600
4800
2400
1800
1200
300
110
6
14
30
62
83
126
510
1394
Serial Signals/Pin-Outs
RS232C Interface Pin Assignment for High Density 15-Pin Connectors
J2
Pin
1
2
3
4
5
6
RS-232C Pin
Number
1
2
3
4
5
6
7
7
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
RS-232C Signal
Name
RS-232C Signal Function
TXD
RTS
RXD
CTS
RXC
DSS
DTR
DSR
bCD
STXC
SGD
LCLPBK
RMLPBK
TSTMD
RNG
Transmit Data
- Request To Send
Receive Data
Clear To Send
Receive Clock
Data Signal Select
Data Terminal Ready
Data Set Ready
Carrier Detect
Transmit Clock
Signal Ground
Local Loopback
Remote Loopback
Test Mode Indicator
Not Supported
8-62
ISBC@ 186/410
RS422A Interface Pin Assignment for High Density 1S-Pln Connectors
J1
Pin
Signal Name
1
2
3
4
5
6
RS42211
On Board
RS-422A Signal
Name
TR(a)
(a)
RD(a)
(a)
(a)
TR (b)
(b)
RD(b)
(b)
(b)
RS4229
RS42212
7
8
9
10
11
12
13
14
15
RS-422A Signal Function
RS42290
Transmit Data
Control
Receive Data
Indication
Signal Timing
Transmit Data
Control
Receive Data
Indication
Signal Timing
Signal Ground
Not Used
Not Used
Not Used
Chassis Ground
NOTE:
The iSBC® 186/40 board does not support the unused signals.
RS232C Interface Pin Assignment for IBM® Compatible g-Pln Connectors
Pin Number
Signal Name
Function
In/Out
1
2
3
4
5
6
7
8
9
CD
RXD
TXD
DTR
SG
DSR
RTS
CTS
RI
Carrier Detect
Received Data
Transmit Data
Data Terminal Ready
Signal Ground
Data Set Ready
Request To Send
Clear To Send
Ring Indicator
. In
In
Out
Out
Interrupt Capability
In
Out
In
Not Supported
Connectors
Interface
Potential Interrupt Sources from iPSB Bus-255 individual and 1 Broadcast
iPSB
bus (P1)
Interrupt Levels-12 vectored requests using two
8259As and 1 input to the master PIC from the slave
PIC
Connector
96-pin DIN, right
angle female
Part #
603-2-IEC-C096-F
RS232CI 15-pin high density,
F1S422A
Interrupt Requests-All levels TTL compatible
RS232Conly
Interfaces
iPSB Bus-Compliance Level RQAlRPA D16M32
iSBX Bus-Compliance Level 08/16 DMA
o type, right
angle female
(see note)
9-pin IBM compatible, 0 type, right
angle male (see
note)
NOTE:
The manufacturers below provide connectors which
will mate with the connectors supplied on the iSBC
186/410 board front-panel.
Serial 1/0-2 ch. RS232C or RS422A compatible,
configured DTE only; 4 ch. RS232C IBM compatible
only, configured DTE only.
8-63
inter
ISBC~
186/410
Mating Connectors, Shells and Cables
Connectors and Shells
Manufacturer
High Density D·type Plug (male)
High Density D-type Plug (male)
D-type Receptacle (female)
D-type Receptacle (female)
Connector Shells
AMP
Positronic
AMP
ITT-Cannon
AMP
ITT-Cannon
3M,
Cable Description
15 Conductor-Shielp,
15 Conductor-Shield,
10 Conductor-Shield,
9 Conductor-Shield,
Pins
Part No.
15
15
9
9
(For 15 or
9-pin connect.
above).
204501-1
DD-15M
205203-3
DE-9S
745171-X
DE-51218
358-2100
Manufacturer
Part No.
5120/15
Alpha
Beldon
Alpha
Beldon
Round
Round
Round
Round
9541
5120/10
9539
NOTE:
All cable referenced is available in 100 ft. minimum lengths.
PHYSICAL DIMENSIONS
ELECTRICAL CHARACTERISTICS
The iSBC 186/410 board meets all MULTIBUS II
mechanical specifications as presented in the
MULTIBUS II Architecture Specification Handbook
(#146077, Rev. C)
The maximum power required per voltage is shown
below.
Eurocard Form Factor
Depth: 220 mm (8.7 inches)
Voltage
(volts)
Max. Current
(amps)
Max. Power
(watts)
+5V
+12V
-12V
8.22A
150mA
150mA
43.16W
1.89W
1.89W
Height: 233 mm (9.2 inches)
Front Panel Width: 20 mm (0.76 inches)
Weight: 822 gm (29 ounces)
REFERENCE MANUALS
iSBC 186/410 Serial Communications Computer User's Guide (#148941-001)
ENVIRONMENTAL
CHARACTERISTICS
Intel MULTIBUS II Architecture Specification Handbook (# 146077)
Manuals may be ordered from any Intel Sales. Representative, Distribution Office, or from the Intel literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.
Temperature
Inlet air at 200 LFM airflow over all boards
Non-operating: - 40·C to + 75·C
Operating: O· to + 55·C
ORDERING INFORMATION
Humidity
Part Number
Non-operating-95% Relative Humidity
non-condensing
Operating-90% Relative Humidity
condensing
@
@
+ 55·C,
Description
iSBC 186/410 MULTIBUS II Serial Communications Computer
+ 55·C, non-
8-64
inter
~aJ:.. #2
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