1989_Analog_Devices_Data_Conversion_Products_Databook 1989 Analog Devices Data Conversion Products Databook
User Manual: 1989_Analog_Devices_Data_Conversion_Products_Databook
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How to Find Product Data in This Databook
THIS VOLUME
Contains Data Sheets, Selection Guides and a wealth of background information on signal conversion and a wide variety of
components for analog signal processing.
It is one member of a three-volume, 2,800-page set of Databooks describing and specifying Linear, Conversion and DSP
products from Analog Devices, Inc., in IC, hybrid and assembled form for measurement, control and real-world signal
processing.
IF YOU KNOW THE MODEL NUMBER
Turn to the product index at the back of the book and look up the model number. You will find the Volume-Section-Page
location of data sheets bound into this volume.
If you're looking for a form-and-function-compatible version of a product originally brought to market by some other manufacturer
(second source), add our "AD" prefix and look it up in the index.
IF YOU DON'T KNOW THE MODEL NUMBER
Find your function in the list on the opposite page or in the Table of Contents on pages 1-5 through 1-10. Turn directly to
the appropriate Section. You will find a functional Selection Guide at the beginning of the Section. The Selection Guides (and
the "Orientation" that usually accompanies them) will help you fmd the products that are the closest to satisfying your need.
Use them to compare all products in the category by salient criteria.
IF YOU CAN'T FIND IT HERE . .. ASK!
If it's not a signal conversion product, it's probably in one of the two sister volumes, the Linear Products Databook or the
DSP Products Databook. If you don't already own these volumes, you can have them FREE by getting in touch with Analog
Devices or the nearest sales office, or phoning (617)-329-4700, Extension 3392.
See Worldwide Service Directory on pages 15-9 and 15-10 at the back of this volume for our sales office phone numbers.
Contents of Other Databooks
LINEARPRODUCTSDATABOOK
Operational Amplifiers
Comparators
Instrumentation Amplifiers
Isolation Amplifiers
Analog MuitiplierslDividers
Log/Antilog Amplifiers
RMS-to-DC Converters
Special Function Components
Temperature Transducers
Signal Conditioning Components & Subsystems
Digital Panel Instruments
Application Specific ICs
Power Supplies
Component Test Systems
DSPPRODUCTSDATABOOK
DSP Processors
Microcoded Support Components
Floating-Point Components
Fixed-Point Components
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor
for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Analog Devices.
Specifications shown in this Databook are subject to change without notice.
1989/90
DATA CONVERSION
PRODUCTS
DATABOOK
General Information
01A Converters
AID Converters
VIF & FIV Converters
Synchro & Resolver Converters
Sample/Track-Hold Amplifiers
©Analog Devices, Inc., 1989
All Rights· Reserved
IlANALOG
DEVICES
CMOS Switches & Multiplexers
Voltage References
••
•a
II
••
Data Acquisition Subsystems
II
II
Microcomputer liD Boards
II
Application Specific ICs
Power Supplies
III
II
Component Test Systems
III
Package Information
Appendix
Product Index
a
I
I
,.ANALOG
.... DEVICES
DATA CONVERSION PRODUCTS DATABOOK
July 1989
© Analog Devices. Inc•• 1989
All Rights Reserved
Information furnished by Analog Devices is believed to be accurate and reliable. However. no responsibility
is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Products in this book may be covered by one or more ofthe following patents. Additional patents are pending.
U.S.:
RE29.619. RE29.992. RE30.586, RE31,850, DES. 233.909, 3,007.114. 3.278.736, 3,355.670, 3,441,913, 3,467,908.
3,500.218. 3,530,390, 3,533.002. 3,685.045. 3.729.660, 3.793.563, 3,803.590. 3,842,412,3,868,583,3,890.611,
3,906,486. 3.909.908. 3.932,863, 3,940.760, 3,942.173, 3,946.324. 3,950.603, 3.961,326, 3.978,473, 3.979,688,
4,016,559.4,020,486,4.029,974,4,034.366. 4.054.829. 4.092.698, 4.123.698, 4.136,349. 4,141,004, 4,213.806.
4,250.445. 4.268,759. 4.270,118, 4,286,225. 4,309,693, 4,313,083, 4,323,795, 4,338,591, 4,349.811, 4,363.024,
4,374,314, 4,383,222,4,395,647,4,399.345,4,400.689, 4,400.690, 4,427,973, 4,439,724, 4,460,891. 4,475,103,
4,475.169,4,476,538.4,481,708,4,484,149,4,485.372, 4,491,825, 4,511,413, 4,521,764, 4,543,560, 4,543.561,
4,547,766,4,547,961.4,556,870,4,558,242, 4,562,400, 4,565,000, 4,586,019, 4,586,155, 4,590,456. 4,596,976,
4,601,760, 4,604,532, 4,608,541, 4.622.512, 4.626.769, 4,639,683, 4,644,253, 4,646,056, 4,646,238, 4,678.936,
4,684.922,4,685,200,4,694,276,4,697,151, 4,703.283, 4,707.682, 4,709,167, 4,717,883, 4.722,910, 4,742,331,
4,751,455,4,752,9004,761,636,4,769,564. 4,771,011, 4,774,685, 4,791,551, 4,800,524, 4,808,908, 4,811,296,
4,814.767
France:
111.833,70.10561,75.27557,7608238,77 20799,7810462,7924041,8000960,8011312,8102661,81 14845,
8209758,8303140
Japan:
1,092,928,1,242,936,1,242,965,1,306,235,1,337,318,1,401,661,1,412,991
West Germany:
2,014034,2540451.7,2611858.1
U.K.:
1,310,591,1,310,592,1,537,542,1,590.136. 1,590,137, 1,599,538,2,008,876,2,032,659,2.040,087,2,050,740,
2,054,992,2,075,295,2,081,040,2,100,081, 2,103,884, 2,104.288. 2,107,951, 2,115.932, 2.118,386, 2,119,139,
2,119,547,2,126,445,2,126,814,2,135,545,2,137,787
Canada:
984,015, 1,006,236, 1,025,558, 1,035,464. 1,054,248, 1,141,034, 1,141,820, 1,142,445, 1,143,306, 1,150,414,
1,153.607,1,157,571,1,159,956.1,177,127, 1,177,966, 1,184,662, 1,184,663, 1,191,715, 1.192,310, 1,192.311,
1,192,312,1,203,628,1,205,920,1,212,730,1,214,282,1,219,679,1,219,966,1,223,086
Sweden:
7603320-8
General Information
Contents
Page
General Introduction
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
I- 3
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . ..
I- 5
GENERAL INFORMATION 1-1
II
1-2 GENERAL INFORMA TlON
General Introduction
Analog Devices designs, manufactures and sells worldwide
sophisticated electronic components and subsystems for use in
real-world signal processing. More than six hundred standard
products are produced in manufacturing facilities located
throughout the world. These facilities encompass all relevant
technologies, including several embodiments of CMOS, BiMOS,
bipolar and hybrid integmted circuits, each optimized for specific attributes - and assembled products in the form of potted
modules, printed-circuit boards and instrument packages.
State-of-the-art technologies have been utilized (and in many
cases invented) to provide timely, reliable, easy-to-use advanced
designs at realistic prices. Our popular IC products are available
in both conventional and surface-mount packages (SO, LCC,
PLCC), and many of our assembled products employ surfacemount technology to reduce manufacturing costs and overall
size. More than twenty years of successful applications experience and continuing vertical integration insure that these products are oriented to user needs. The ongoing application of
today's state-of-the-art and the invention of tomorrow's stateof-the-art processes strengthen the leadership position of Analog
Devices in standard data-acquisition and signal-processing products and make us a strong contender in high-performance
mixed-signal ASICs.
MAJOR PROGRESS
Since publication of our 1988 Data Conversion Products Databook, more than 40 significant new data conversion products
have been introduced; they run the gamut from bmnd new
product categories and technologies to new standard products
(with improvements in price, performance or design) to augmented second-source products. They are all classified and summarized in this Volume, along with existing products that are
desirable for use in new designs.
Major new data conversion products include hybrid and monolithic products with high levels of performance and integration,
complete and fully guaranteed specifications, and attractive
price. For high-speed AID conversion, these include: the
AD900S (12 bit, 10 MSPS), AD9006 and AD9016 (6 bit,
SOO MSPS) with direct and demultiplexed 1:2 output, AD9011
(8 bit, 100 MSPS), AD9028 (8 bit, 300 MSPS) also with direct
and demultiplexed 1:2 output, and the AD9048 (8 bit,
20 MSPS). High-speed D/A conversion is available with the
AD9712 and AD9713 DACs, providing 100 MSPS and
80 MSPS update mtes, respectively.
A variety of speed, functionality, and resolution combinations
are available from the AD7769 dual 8-bit ADC and DAC 1/0
port, the AD7237 and AD7247 dual 12-bit DAC (8+4- or 12-bit
parallel data loading), AD662 12-bit single-supply DAC, the
AD7840 14-bit DAC (serial or parallel data loading), the
AD7772 12-bit, 10 ILS serial output ADC, and the AD7871 and
AD7872 14-bit ADCs (serial only or serial/parallel data interface). Higher performance is achieved with the AD1679 and
ADl779 14-bit, 100 KSPS ADCs with byte-wide and fully parallel interface, the ADJ377 16-bit, 10 ILS ADC, the ADJ362 16channel, 10 ILS ADC, the ADJ334 ADC with 4 channels of
simultaneous or independent sampling (well-suited for DSP
applications), and the ADJ330 which provides AID conversions
at 100 KSPS with 18-bit dynamic range and 12 bits of resolution
in a floating-point output format.
Digital audio needs are met with the optimized ADI8S6 (16 bit)
and ADI860 (18 bit) DACs, both of which minimize the need
for external components; video applications are served by the
ADV453, ADV471, ADV476, and ADV478 video DACs plus
internal RAM which provide a variety of color resolution, pixel
density, and color palette choices. Conversion support circuitry
includes the monolithic AD684 quadruple samplelhold amplifier
for simultaneous sampling, and the ADll54 and AD386 16-bit
sample or tracklhold devices. Switching and routing of wideband signals is facilitated by the AD9300 4-channel video
multiplexer.
THE 1989190 DATA CONVERSION PRODUCTS
DATABOOK
This Volume provides complete technical data on Analog
Devices "data conversion" products - designed to process, condition and otherwise operate between analog signals and digital
signals. One of a set of three volumes, it is accompanied by
the DSP Products Databook, dedicated to products for highperformance digital signal-processing (i.e., digital-to-digital), and
the Linear Products Databook, which covers products involved in
spanning the interface between analog signals and analog results.
The product data in this book is intended primarily for the
majority of users who are concerned with new designs. For this
reason, those existing and available products that offer little if
any unique advantage over newer products in future designs are
included in the Index and their data sheets are available from us
separately - but they aren't published in this book.
This book includes:
• Comprehensive data sheets on more than 193 significant
product families:
• Orientation material and selection guides for rapid product
finding;
• A representative list of available Analog Devices technical
publications on real-world analog and digital signalprocessing;
• Worldwide Service Directory; and
• Product Index to all three volumes.
TECHNICAL SUPPORT
Our extensive technical literature discusses the technology and
applications of products for precision measurement and control.
Besides tutorial material and comprehensive data sheets, including a large amount in our Databooks, we offer Application
Notes, Application Guides, Technical Handbooks (at reasonable
prices), and seveml free serial publications; for example, Analog
Productlog provides brief information on new products being
introduced, and Analog Dialogue, our technical magazine, provides in-depth discussions of new developments in analog and
digital circuit technology as applied to data acquisition, signal
processing, control, and test. DSPatch is a quarterly newsletter
that brings its reader up-to-date applications information on our
DSP products and the general field of digital signal processing.
We maintain a mailing list of engineers, scientists, and technicians with a serious interest in our products. In addition to
Databook catalogs - and general short-form selection guides, we also publish several short-form catalogs on specific product
families. You will find typical publications described on pages
IS-6 to IS-8 at the back of the book.
GENERAL INFORMA TlON 1-3
SALES OFFICES
Backing up our design and manufacturing capabilities and our
extensive array of publications is a network of sales offices and
representatives throughout the United States and most of the
world. They are staffed by experienced sales and applications
engineers, and many of them maintain a local stock of Analog
Devices products. Our Worldwide Service Directory, as of the
publication date, appears on pages 15-9 and 15-10 at the back of
the book.
PRODUCTS NOT FOUND IN THE SELECTION
GUIDES
For maximum usefulness to designers of new equipment, we
have limited the contents of selection guides to products most
likely to be used for the design of new circuits and systems. If
the model number of a product you are interested in is not in
the Index, tum to page 15-4 at the back of this volume where
you will fmd a list of older products for which data sheets are
available upon request. On page 15-5 you will find a guide to
substitutions (where possible) for products no longer available.
RELIABILITY
The manufacture of reliable products is a key objective at Analog Devices. The primary focus is the Companywide Quality
Improvement Process (QIP). In addition, we maintain facilities
that have been qualified under such standards as MIL-M-38slO
for ICs in the U.S. and Ireland and MIL-STD-1772 for hybrids.
More than 25 of our products - both proprietary and secondsource - have qualified for JAN part numbers; others are in the
process. A larger number of products - including many of the
newer ones just starting the JAN qualification process - are specifically characterized on Standard Military Drawings (SMDs).
Most of our ICs are available in versions that comply with MILSTD-883C Class B. We publish a Military Products Databook for
designers who specify ICs and hybrids for military contracts (the
1987 issue contains data on nearly 150 available product famiIities). A newsletter, Analog Briefings, provides current information about the status of reliability at AD!.
Our PLUS program makes available standard devices (commercial and industrial grades, plastic or ceramic packaging) for any
user with demanding application environments, at a small premium. Subjected to stringent screening, similar to MIL-STD883 test methods, they are often suffixed "/+" and are available
from stock.
1-4 GENERAL INFORMA TION
PRICES
Accurate, up-to-date prices are an important consideration in
making a choice among the many available product familities.
Since prices are subject to change, current price lists and/or
quotations are available upon request from our sales offices.
Table of Contents
Page
DIA Converters - Section 2
2 -1
Selection Guide . . . . . . . . . . . . . . .
2-4
Orientation . . . . . . . . . . . . . . . . .
2-8
AD390 - Quad 12-Bit Microprocessor-Compatible D/A Converter
2 - 13
2 - 21
AD392 - Complete Quad 12-Bit D/A Converter with Readback .
AD394/395 - ....P-COmpatible MUltiplying Quad 12-Bit D/A Converters
AD3% - ....P-COmpatible Multiplying Quad 14-Bit D/A Converter ..
2 - 27
AD557 - DACPORT Low Cost Complete ....P-Compatible 8-Bit DAC
2 - 35
2 -43
AD558 - DACPORT Low Cost Complete ....P-Compatible 8-Bit DAC
2 - 47
AD561 - Low Cost 10-Bit Monolithic D/A Converter . . . . .
AD562/563 - IC 12-Bit D/A Converters . . . . . . . . . . . . .
2 - 55
2 - 59
AD565A/566A - High Speed 12-Bit Monolithic D/A Converters
2 - 63
AD568 - 12-Bit Ultrahigh Speed Monolithic D/A Converter
2 - 71
AD569 - 16-Bit Monotonic Voltage Output D/A Converter
2 - 83
AD662- Single Supply 12-Bit DACPORT . . . . . . . . .
AD664 - Monolithic 12-Bit Quad DAC . . . . . . . . . . .
2 - 95
2 -103
AD667 - Microprocessor-Compatible 12-Bit D/A Converter
2 - 123
AD668 - 12-Bit Ultrahigh Speed MUltiplying D/A Converter.
AD767 - Microprocessor-Compatible 12-Bit D/A Converter
2 - 131
.
2 - 135
AD1l45 - Low Cost 16-Bit Digital-to-Analog Converter . . .
2 - 143
2 -149
AD1l47/1148 - Microprocessor-Compatible 16-Bit D/A Converters
2 - 155
ADI139 - High Accuracy 18-Bit Digital-to-Analog Converter
ADl856 - 16-Bit PCM Audio DAC . . . . . . . . . . . .
2 - 161
ADl860 - 18-Bit PCM Audio DAC . • . . . . . . . . . .
2 -171
AD7l11- LOGDAC CMOS Logarithmic D/A Converter
2 - 183
2 -189
AD7224 - LC2 MOS 8-Bit DAC with Output Amplifier
.
AD7225 - LC2 MOS Quad 8-Bit DAC with Separate Reference Inputs
AD7226 - LC2MOS Quad 8-Bit D/A Converter
AD7228 - LC2 MOS Octal 8-Bit DAC
..
...... .
2 - 193
2 -199
AD7237/7247 - LC 2MOS Dual 12-Bit DACPORTs
AD724517248 - LC2 MOS 12-Bit DACPORTs . . .
2 - 205
2-213
2 -221
AD7524 - CMOS 8-Bit Buffered Multiplying DAC .
2 - 235
AD7528 - CMOS Dual 8-Bit Buffered Multiplying DAC .
2 - 241
AD7533 - CMOS Low Cost 10-Bit MUltiplying DAC
2 - 245
AD7534 - LC2 MOS ....P-Compatible 14-Bit DAC
AD7535 - LC2MOS ....P-COmpatible 14-Bit DAC . . .
2 - 251
2 - 255
AD7536 - LC2MOS 14-Bit ....P-Compatible DAC . . .
2- 259
AD7537 - LC2MOS (8+4) Loading Dual12-Bit DAC
2-263
AD7538 - LC2MOS ....P-COmpatible 14-Bit DAC . . .
2 - 267
AD7541A - CMOS 12-Bit Monolithic MUltiplying DAC
2 -275
AD7542 - CMOS ....P-COmpatible 12-Bit DAC . . .
2 - 281
AD7543 - CMOS Serial Input 12-Bit DAC . . . . . .
2 - 289
AD7545 - CMOS 12-Bit Buffered Multiplying DAC .
2 - 293
2-297
AD7545A - CMOS 12-Bit Buffered Multiplying DAC
AD7547 - LC2 MOS Parallel Loading Dual 12-Bit DAC
2 - 301
GENERAL INFORMA TION 1-5
II
Page
AD7548 - LC2 MOS 8-Bit jLP-Compatible 12-Bit DAC ..
2 - 305
AD7549 - LC2 MOS Dual 12-Bit jLP-Compatible DAC . .
2 - 317
AD7628 - CMOS Dual 8-Bit Buffered Multiplying DAC .
2 - 325
2- 329
AD7840 - LC2MOS Complete 14-Bit DAC . . . . . . .
AD7845 - LC2 MOS Complete 12-Bit Multiplying DAC .
AD7846 - LC2 MOS 16-Bit Voltage Output DAC . . . . .
AD7848 - LC2 MOS Complete 12-Bit DAC with DSP Interface
AD9700 - Monolithic Video D/A Converter
..... .
AD9701 - 250 MHz Video Digital-to-Analog Converter
AD9702 - Triple 4-Bit D/A Converter . . . . . .
AD9703 - Monolithic Video D/A Converter
.. .
2 - 345
2 - 357
2 - 371
2 - 379
2 - 385
2 - 391
2 - 395
AD9712/9713 - 12-Bit 100 MSPS D/A Converters
2 - 399
AD9768 - Ultrahigh Speed IC D/A Converter
2 - 403
..
AD DAC71IDAC72 - High Resolution 16-Bit D/A Converters
2 - 407
AD DAC80/DAC85/DAC87 - Complete Low Cost 12-Bit Monolithic D/A Converters
2-411
ADV453 - CMOS 66 MHz Monolithic 256 x 24 Color Palette RAM-DAC . . . . .
2 -421
ADV476 - CMOS Monolithic 256 x 18 Color Palette RAM-DAC . . . . . . . . . .
2 - 431
ADV478/471 - CMOS 80 MHz Monolithic 256 x 24 (18) Color Palette RAM-DAC
2 -441
DACl136/1138 - High Resolution 16- and 18-Bit Digital-to-Analog Converters
2 -453
HDD-1206 - 12-Bit Deglitched Voltage Out D/A Converter
2 - 459
HDG Series - Hybrid Video Digital-to-Analog Converters
HDG-0807 - Hybrid Video Digital-to-Analog Converter .
2 - 463
HDM-1210 - Ultrahigh Speed Multiplying D/A Converter
2 - 467
2-471
HDS-1250 - Ultrahigh Speed 12-Bit D/A Converter
2-477
AID Converters - Section 3
3-1
Selection Guide . . . . . . . . . . . . . .
3-3
3-9
Orientation . . . . . . . . . . . . . . . .
AD570/571 - 8- and lO-Bit Analog-to-Digital Converters
AD572 - 12-Bit Successive Approlcirnation Integrated Circuit AID Converter
AD573 - lO-Bit AID Converter . . . . . . . . . . . . . . . .
AD574A - Complete 12-Bit AID Converter . . . . . . . . . .
AD575 - Complete lO-Bit AID Converter with Serial Output
AD578 - Very Fast Complete 12-Bit AID Converter
AD579 - Very Fast Complete 10-Bit AID Converter
AD670 - Low Cost Signal Conditioning 8-Bit ADC
AD673 - 8-Bit AID Converter . . . . . . . . . . .
AD674A - Complete 12-Bit AID Converter . . . . ..
AD678 - 12-Bit 200 KSPS Complete Sampling ADC .
AD679 - 14-Bit 100 KSPS Complete Sampling ADC .
AD770 - 200 MSPS Wideband 8-Bit AID Converter .
AD779 - 14-Bit 100 KSPS Complete Sampling ADC .
AD1170 - High Resolution Programmable Integrating AID Converter
AD1175K - High Accuracy 22-Bit Integrating AID Converter
AD1376 - Complete High Speed 16-Bit AID Converter
AD1377 - Complete High Speed 16-Bit AID Converter
1-6 GENERAL INFORMA TlON
3 - 15
3 - 21
3 - 29
3 - 37
3-49
3 - 57
3 - 63
3 - 69
3 - 81
3 - 89
3 - 99
3 - 111
3 - 123
3 - 13S
3.,.. 147
3 - 159
3 - 167
3 -175
Page
AD1380 - Low Cost 16-Bit Sampling ADC . . . . . .
AD1678 - l2-Bit 200 KSPS Complete Sampling ADC
3 - 183
3 - 191
AD1679 - l4-Bit 100 KSPS Complete Sampling ADC
3 - 203
ADl779 - 14-Bit 100 KSPS Complete Sampling ADC
3 - 215
AD5200/5210 Series - 12-Bit Successive Approximation High Accuracy AID Converters.
AD756917669 - LC2MOS Complete 8-Bit Analog 1/0 Systems
3 - 227
3 - 233
AD7572 - LC2MOS Complete High Speed l2-Bit ADC
3 - 253
AD7575 - LC2MOS 5 fLS 8-Bit ADC with TracklHold ..
3 - 265
AD7576 - LC2MOS 10 fLS fLP-Compatible 8-Bit ADC ..
3 - 269
AD7578 - CMOS l2-Bit Successive Approximation ADC
AD7579/7580 - LC 2 MOS IO-Bit Sampling AID Converters .
3 - 273
AD7581 - CMOS fLP-Compatible 8-Bit 8-Channel DAS
.
AD7582 - CMOS l2-Bit Successive Approximation ADC
AD7672 - LC2MOS High Speed 12-Bit ADC . .
AD7769 - LC2MOS Analog 1/0 Port . . . . . . . . . . .
3 - 279
3 - 295
3 - 303
3 - 309
AD7772 - LC2MOS Serial Output 12-Bit ADC . . . . . .
3 - 325
3 - 341
AD7820 - LC2MOS High Speed fLP-Compatible 8-Bit ADC with TracklHold Function
AD7821- LC2MOS High Speed fLP-Compatible 8-Bit ADC with Track/Hold Function
3 - 357
3 - 367
AD782417828 - LC2 MOS High Speed 4- & 8-Channel 8-Bit ADCs .
3 - 379
AD7870 - LC2MOS Complete l2-Bit 100 kHz Sampling ADC . . . . . . . . . . .
AD787117872 - LC2MOS Complete 14-Jlit Sampling ADCs . . . . . . . . . . . .
3 - 391
3 -407
AD7878 - LC2 MOS Complete l2-Bit 100 kHz Sampling ADC with DSP Interface
AD9000 - High Speed 6-Bit AID Converter . . . . . .
3 - 419
3 - 435
AD9002 - High Speed 8-Bit Monolithic AID Converter
3 -443
AD9003 - 12-Bit 1 MHz AID Converter . . . . .
3 - 451
AD9005 - 12-Bit 10 MSPS AID Converter . . . .
3 - 459
AD9006/9016 - High Speed 6-Bit AID Converters
3 - 467
AD9011 - 8-Bit 100 MSPS AID Converter . . . .
3 - 483
AD9012 - High Speed 8-Bit TTL AID Converter
3 -489
AD9028/9038 - High Speed 8-Bit AID Converters
3 - 497
AD9048 - Monolithic 8-Bit Video AID Converter
3 - 509
3 - 517
AD9502 - Hybrid RS-170 Video Digitizer . . . .
AD9688 - High Speed 4-Bit Monolithic ADC ..
AD ADC71172 - Complete High Resolution 16-Bit AID Converters
3 - 525
3 - 531
AD ADC80 - 12-Bit Successive Approximation Integrated Circuit AID Converter
AD ADC84/85/AD5240 - Fast Complete 12-Bit AID Converters .
ADC1130/1131 - 14-Bit High Speed Analog-to-Digital Converters
ADC1l40 - Low Cost 16-Bit Analog-to-Digital Converter . . . .
3333-
CAV-104O - 10-Bit Video Analog-to-Digital Converter . . . . . .
3 - 563
CAV-l205 - 12-Bit
CAV-l220 - 12-Bit
HAS-1201 - 12-Bit
HAS-1202/l202A -
3 - 567
3 - 569
5 MHz Eurocard Analog-to-Digital Converter
Video Analog-to-Digital Converter . . . . . .
1 MHz Analog-to-Digital Converter . . . . .
Ultrafast Hybrid Analog-to-Digital Converters
HAS-1204 - Ultrahigh Speed 12-Bit AID Converter
539
547
555
559
3 - 573
3 - 579
...
3 - 583
HAS-l409 - 14-Bit 125 kHz Analog-to-Digital Converter.
3 - 587
MOD-1205 - 12-Bit Video Analog-to-Digital Converter
3 - 593
GENERAL INFORMA TION 1-7
a
Page
V/F & FN Converters - Section 4
4-1
Selection Guide . . . . . . . . . . . . . . . . . . .
4-2
Orientation . . . . . . . . . . . . . . . . . . . . .
4-3
AD537 - Integmted Circuit Voltage-to-Frequency Converter
4-5
AD650 - Voltage-to-Frequency and Frequency-to-Voltage Converter.
AD654 - Low Cost Monolithic Voltage-to-Frequency Converter . . .
4-l3
4- 25
4- 41
ADVFC32 - Voltage-to-Frequency and Frequency-to-Voltage Converter
4-49
AD652 - Monolithic Synchronous Voltage-to-Frequency Converter
.
Synchro & Resolver Converters - Section 5
5-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5
DRC1745/1746 - High Power Output, Hybrid Digital-to-SynchrolResolver Converters
5-7
IPA1764 - Hybrid Inductosyn Preamplifier . . . . . . . . . . . . . . . . . . . . . . .
5 - 15
OSC1758 - Hybrid Power Oscillator
SDClRDC1740/174111742 - 12- and 14-Bit Hybrid Synchro/Resolver-to-Digital Converters
5 -17
5 -19
ISI4/24/44/64 - Tachogenerator Output Hybrid Resolver-to-Digital Converters
5 - 27
......................... .
..... .
IS20/40/60/61 - Hybrid Tracking Resolver-to-Digital Converters . . . . . . . . . . . . . ;
5 - 35
IS74 - Tachogenerator Output Variable Resolution, Hybrid Resolver-to-Digital Converter
2S50 - LVDT-to-Digital Converter . . . . . . . . . . . . . . . . . .
5 -43
5 - 51
2S54/56/58 - High Resolution LVDT-to-Digital Converters
.... .
5 - 53
2S80 - Variable Resolution, Monolithic Resolver-to-Digital Converter
5 - 65
2S81 - Low Cost Monolithic 12-Bit Resolver-to-Digital Converter ..
5 -77
5 - 89
2S82 - Variable Resolution, Monolithic Resolver-to-Digital Converter
5S70/72 - Synchro and Resolver Isolation Transformers
5 - 101
6S04 - Digital Director . . . . . . . . . . . . . . . . . . . . . . . .
5 - 103
Sample/Track-Hold Amplifiers - Section 6
6-1
Selection Guide . . . . . . . . . . . . . . . . . .
6-2
Orientation . . . . . . . . . . . . . . . . . . . .
6-3
AD346 - High Speed Sample-and-Hold Amplifier
6-5
AD386 - True 16-Bit Track-and-Hold Amplifier .
6-11
6- 25
AD389 - High Resolution Track-and-Hold Amplifier
AD582 - Low Cost Sample-and-Hold Amplifier
...
6 - 31
AD583 - Sample-and-Hold Amplifier . . . . . . . ..
6- 35
6- 37
AD585 - High Speed Precision Sample-and-Hold Amplifier
AD684 - Four Channel Sample-and-Hold Amplifier .. . .
6 - 43
AD1l54 - Low Cost 16-Bit Accurate Sample-and-Hold Amplifier
6 - 51
HTC-0300A - Ultrahigh Speed Hybrid Track-and-Hold Amplifier
6 - 57
HTS-00I0 - Ultrahigh Speed Hybrid Track-and-Hold Amplifier
6 - 61
HTS-0025 - Ultrahigh Speed Hybrid Track-and-Hold Amplifier .
6- 67
1-8 GENERAL INFORMA TION
Page
CMOS Switches & Multiplexers - Section 7
.7- I
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . .
.7-2
Orientation
.............................. .
.7-4
AD75011750217503 - CMOS 4/8 Channel Analog Multiplexers . . . . .
.7-7
a
AD75 IODI/75 llDI175 12DI - Dielectrically Isolated CMOS Protected Analog Switches
.7-9
AD7590DII7591DII7592DI - Dielectrically Isolated CMOS Analog Switches with Data Latches.
· 7 - 13
.7- 17
AD9300 - 4 x I Wideband Video Multiplexer . . . . . .
ADG20lAI202A - CMOS Quad SPST Switches
....
· 7 - 25
.7 - 29
ADG20lHS - LC 2 MOS High Speed Quad SPST Switch
ADG211A/212A - LC2 MOS Quad SPST Switches . . .
.7- 37
ADG22 11222 - CMOS Quad SPST Switches . . . . . .
.7-41
ADG506A/507A - CMOS 8116 Channel Analog Multiplexers
.7-45
ADG508A/509A - CMOS 4/8 Channel Analog Multiplexers
· 7 - 53
ADG526A/527A - CMOS Latched 8/16 Channel Analog Multiplexers
· 7 - 57
ADG528A/529A - CMOS Latched 4/8 Channel Analog Multiplexers .
· 7 - 65
Voltage References - Section 8
.8-1
Selection Guide . . . . . . . . . . . . . . . . .
.8-2
... . . . . . . . . . . . . . . . .
.8-3
AD580 - High Precision 2.5 Volt IC Reference.
.8-5
AD581 - High Precision 10 Volt IC Reference .
.8-9
AD584 - Pin Programmable Precision Voltage Reference.
· 8 - IS
AD586 - High Precision 5 V Reference . . .
· 8 - 23
AD587 - High Precision 10 V Reference ..
AD588 - High Precision Voltage Reference.
· 8 - 31
.8- 39
AD589 - Two-Terminal IC 1.2 V Reference
· 8 - 51
Orientation
AD689 - High Precision 8.192 V Reference
· 8 - 55
ADI403/1403A - Low Cost Precision 2.5 V IC References
.8 - 63
AD2700/270112702 - ± 10 Volt Precision Reference Series
.8 - 67
AD2710/2712 - ± 10.000 Volt Ultrahigh Precision Reference Series
· 8 - 71
.8-75
ADREFOll02 - 5 V
+ 10 V References . . . . . . . . . . . . . .
Data Acquisition Subsystems - Section 9 .
.9-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . .
.9-2
............................ .
.9-3
Orientation
AD363/364 - Complete 16 Channel I2-Bit Data Acquisition Systems .
.9-5
AD367 - High Resolution Programmable Gain DAS . . . . . . . . .
.9-13
AD368/369 - Complete 12-Bit D/A Converters with Programmable Gain.
.9- 19
AD1330 - 18-Bit Floating Point Data Acquisition System
.9- 29
....... .
AD1332 - Complete 12-Bit Sampling AID Converter for Digital Signal Processing.
AD1334 - Four Channel 12-Bit Sampling AID Converter for Digital Signal Processing
· 9 - 31
.9-49
AD1362 - 16 Channell2-Bit Data Acquisition System . . . . . . . . . . . . . . . .
.9 - 65
DAS1l5211153 - I4-Bit & IS-Bit Sampling Analog-to-Digital Converters . . . . . . .
.9-73
DAS1l57/11581ll59 - Low Power I4-Bit, IS-Bit & I6-Bit Sampling AID Converters
.9-77
GENERAL INFORMA TION
1-9
Page
Microcomputer 110 Boards - Section 10 . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10 - 1
Application Specific Integrated Circuits - Section 11 .................
11 - 1
Power Supplies - Section 12 .....................................
12 - 1
Component Test Systems - Section 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
13 - 1
Package Information - Section 14
14 - 1
Appendix - Section 15 ..........................................
15 - 1
Ordering Guide . . . . '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
15 - 2
Product Families Still Available. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
15 - 4
Substitution Guide for Product Families No Longer Available . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
15 - 5
....•............................................
15 - 6
Worldwide Service Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
15 - 9
Product Index - Section 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
16 - 1
Technical Publications
1-10 GENERAL INFORMATION
OfA Converters
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . .
Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD390 - Quad 12-Bit Microprocessor-Compatible D/A Converter
AD392 - Complete Quad 12-Bit D/A Converter with Readback .
2-4
2-8
2 -13
2 - 21
AD394/395 - floP-Compatible Multiplying Quad 12-Bit D/A Converters
AD396 - floP-Compatible Multiplying Quad 14-Bit D/A Converter ..
2 - 27
2 - 35
AD557 - DACPORT Low Cost Complete floP-Compatible 8-Bit DAC
2 -43
AD558 - DACPORT Low Cost Complete floP-Compatible 8-Bit DAC
2-47
AD561 - Low Cost lO-Bit Monolithic D/A Converter
.... .
2 - 55
AD562/563 - IC 12-Bit D/A Converters . . . . . . . . . . . . .
2 - 59
2 - 63
2 -71
AD565A/566A - High Speed 12-Bit Monolithic D/A Converters
AD568 - 12-Bit Ultrahigh Speed Monolithic D/A Converter
AD569 - 16-Bit Monotonic Voltage Output D/A Converter
AD662- Single Supply 12-Bit DACPORT
2 - 83
........ .
2 - 95
2 - 103
2 - 123
AD664 - Monolithic 12-Bit Quad DAC . . . . . . . . . . .
AD667 - Microprocessor-Compatible 12-Bit D/A Converter
AD668 - 12-Bit Ultrahigh Speed Multiplying D/A Converter.
2 - 131
AD767 - Microprocessor-Compatible 12-Bit D/A Converter
2 - 135
2 -143
.
ADl139 - High Accuracy l8-Bit Digital-to-Analog Converter
AD1l45 - Low Cost l6-Bit Digital-to-Analog Converter . . .
AD1l47/1148 - Microprocessor-Compatible 16-Bit D/A Converters
ADl856 - l6-Bit PCM Audio DAC . . . . . . . . . . . .
ADl860 - 18-Bit PCM Audio DAC . . . . . . . . . . . .
2 - 161
..
2 - 171
2 - 183
2 - 189
2 - 193
2 -199
...... .
2- 205
AD7111- LOGDAC CMOS Logarithmic D/A Converter
AD7224 - LC 2MOS 8-Bit DAC with Output Amplifier
AD7225 - LC2 MOS Quad 8-Bit DAC with Separate Reference Inputs
AD7226 - LC2MOS Quad 8-Bit D/A Converter
AD7228 - LC2 MOS Octal 8-Bit DAC
2 - 149
2 - 155
AD7237/7247 - LC 2MOS Dual l2-Bit DACPORTs
2-213
AD7245/7248 - LC2MOS 12-Bit DACPORTs
2 - 221
AD7528 - CMOS Dual 8-Bit Buffered Multiplying DAC .
2 - 235
2 - 241
AD7533 - CMOS Low Cost 10-Bit Multiplying DAC
2 - 245
AD7534 AD7535 AD7536 AD7537 -
2 - 251
...
AD7524 - CMOS 8-Bit Buffered Multiplying DAC .
LC2 MOS
LC2MOS
LC2 MOS
LC2 MOS
floP-Compatible 14-Bit DAC
floP-Compatible 14-Bit DAC . . .
14-Bit floP-Compatible DAC . . .
(8+4) Loading Dual 12-Bit DAC
2 - 255
2 - 259
AD7538 - LC2 MOS floP-Compatible 14-Bit DAC . . .
2 - 263
2 - 267
AD754lA - CMOS 12-Bit Monolithic Multiplying DAC
2 - 275
AD7542 - CMOS floP-Compatible 12-Bit DAC . . .
AD7543 - CMOS Serial Input 12-Bit DAC . . . . . .
AD7545 - CMOS 12-Bit Buffered MUltiplying DAC .
2 - 281
2 - 289
AD7545A - CMOS 12-Bit Buffered Multiplying DAC
AD7547 - LC2 MOS Parallel Loading Dual 12-Bit DAC
2 - 297
2 - 301
AD7548 - LC2 MOS 8-Bit floP-Compatible 12-Bit DAC .
2 - 305
2 - 293
DIGITAL-TO-ANALOG CONVERTERS 2-1
II
Page
AD7549 - LC2 MOS Dual 12-Bit JJ..P-Compatible DAC . . .
AD7628 - CMOS Dual 8-Bit Buffered Multiplying DAC .
AD7840 - LC2MOS Complete 14-Bit DAC . . . . . . .
AD7845 - LC2 MOS Complete 12-Bit Multiplying DAC ..
AD7846 - LC2MOS 16-Bit Voltage Output DAC . . . . . .
AD7848 - LC2MOS Complete 12-Bit DAC with DSP Interface
AD9700 - Monolithic Video D/A Converter . . . . . .
AD9701 - 250 MHz Video Digital-to-Analog Converter
AD9702 - Triple 4-Bit D/A Converter . . . . . .
AD9703 - Monolithic Video DIA Converter .. .
AD9712/9713 - 12-Bit 100 MSPS D/A Converters
AD9768 - Ultrahigh Speed IC D/A Converter ..
AD DAC71/DACn - High Resolution 16-Bit D/A Converters
AD DAC80/DAC85/DAC87 - Complete Low Cost 12-Bit Monolithic D/A Converters
ADV453 - CMOS 66 MHz Monolithic 256 x 24 Color Palette RAM-DAC . . . . .
ADV476 - CMOS Monolithic 256 x 18 Color Palette RAM-DAC . . . . . . . . . .
ADV478/471 - CMOS 80 MHz Monolithic 256 x 24 (18) Color Palette RAM-DAC
DAC1136/1138 - High Resolution 16- and 18-Bit Digital-to-Analog Converters
HDD-1206 - l2-Bit Deglitched Voltage Out D/A Converter
HDG Series - Hybrid Video Digital-to-Analog Converters
HDG-0807 - Hybrid Video Digital-to-Analog Converter .
HDM-121O - Ultrahigh Speed Multiplying D/A Converter
HDS-1250 - Ultrahigh Speed 12-Bit D/A Converter . . .
2-2 DIGITAL-TO-ANALOG CONVERTERS
2 - 317
2- 325
2 - 329
2 - 345
2 - 357
2-371
2 - 379
2 - 385
2 - 391
2 - 395
2 - 399
2 - 403
2 - 407
2-411
2 - 421
2 - 431
2 -441
2 - 453
2 - 459
2 -463
2-467
2 - 471
2-477
DIGITAL-TO-ANALOG CONVERTERS 2-3
'r'
"'"
S2
~
i;!
Selection Guide
Digital-to-Analog Converters
I"-
~
VOLTAGE OUTPUT DACs
:b.
Settling
Time
",s
typ
Bus
Interface
Bits'
Reference
Voltage
IntlExt (M?
Package
Options'
Temp
Range4
Page
Comments
8
0.8
8, ",p
Int
N, P
C
2-43
8
8
8
12
12
12
12
12
12
12
12
1
3
7
2
3
3
3
3
3
3
4
8, ",p
8, ",p
8, ",p
12
12, ",p
12
12
12
4/8/12, ",p
12, fJ.P
12, ",p
Int
Int
2-12.5 V, Ext
Int
2.56 V,Int
6.3 V, Int
6.3 V, Int
6.3 V, Int
10 V, Int
10 V, Int
3 V, Int
E, N, P, Q
D,E, N, P
E, N, P, Q
M,W
N,Q
D
D
D
D,E, N,P
D,N
E, N, P, Q
C, I, M
C, M
C, I, M
C, M
C, I, M
C
I,M
I,M
C, I, M
C, I, M
C, I, M
3-237
2-47
2-189
2-459
2-95
2-411
2-411
2-411
2-123
2-135
2-371
AD7845
12
5
12, ",p
Ext (M)
E, N, P, Q
C, I, M
2-345
AD7245
AD7248
*AD7840
12
12
14
10
10
4
12, ",p
8, ",p
14/Serial, ",p
5 V, Int
5 V, Int
3 V, Int
E, N, P, Q
E, N, P, Q
E, N, P, Q
C, I, M
C, I, M
C, I, M
2-221
2-221
2-329
*AD1856
AD569
AD DAC7l-V
AD DAC72-V
*AD7846
16
16
16
16
16
1.5
3
5
5
6
Serial, ",p
8/16, ",p
16
16
16, ",p
Int
±5 V, Ext (M)
6.3 V, Int
6.3 V, Int
Ext (M)
N
D,N
D,H
D,H
D,E, N, P
C
I,M
C
C, I
C, I, M
2-161
2-83
2-407
2-407
2-357
Lowest Cost 8-Bit DACPORT™. Single
+5 V Supply
CMOS, Complete 8-Bit DAC/ADC/SHAlReference
10 V Out DACPORT. Single or Dual Supply
CMOS, Low Cost 8-Bit DAC
Deglitched Voltage Output
Complete 12-Bit DACPORT'M. Single +5 V Supply
Improved Industry Standard
Improved Industry Standard
Improved Industry Standard
Highest Accuracy Complete 12-Bit DAC
Fastest Interface Complete 12-Bit DAC
CMOS, Complete 12-Bit DAC with
DSP Interface
CMOS, 12-Bit Multiplying DAC with
Output Amplifier
CMOS, 12-Bit Complete DAC, Parallel Load
CMOS, 12-Bit Complete DAC, Byte Load
CMOS, 14-Bit Complete DAC, Parallel
or Serial Load
16-Bit PCM Audio DAC
Monolithic, 16-Bit Monotonic DAC
High Resolution l6-Bit DAC
High Resolution l6-Bit DAC
CMOS, 16-Bit MUltiplying DAC with
Readback Capability
AD1l45
DAC1136
AD1147
16
16
16
6
8
20
8/16/Serial, ",p
16
16, ",p
3-6 V, Ext
6 V, Int
10 V, Int
G, PLLCC4
Module
D
C
I
2-149
2-453
2-155
AD1148
16
20
16, ",p
10 V, Int
D
*AD1860
DACI138
AD1139
18
18
18
1.5
Serial, ",p
18
8, ",p
Int
6 V, Int
-10 V, Int
N
Module
D
~
l"-
0
C'l
C')
0
<:
M'i
:J:J
;;j
:J:J
til
Model
AD557
AD7569
AD558
AD7224
HDD-1206
*AD662
AD DAC80-V
AD DACSS-V
AD DACS7-V
AD667
AD767
*AD7848
Res
Bits
10
40
DACPORT is a trademark of Analog Devices, Inc.
2-155
C
C
C
2-171
2-453
2-143
High Resolution and Accuracy
8-Bit Latched Input DAC
for Offset and Gain Adjust
Separate 8-Bit Bus for Offset
and Gain Adjust DACs
18-Bit PCM Audio DAC
High Resolution and Accuracy
True 18-Bit Accuracy
CURRENT OUTPUT DACs
Res
Bits
Settling
Time
p.s
typ
Bus
Interface
Bits l
Reference
Volt
IntlExt (Mi
Package
Options3
Temp
Range4
Page
Comments
AD9768
AD7524
AD561
AD7533
AD568
HDS-1250
AD668
8OM-1210
AD565A
8
8
10
10
12
12
12
12
12
0.005
0.1
0.25
0.6
0.035
0.035
0.05
0.085
0.25
8, p.P
8, p.P
10
10
12
12
12
12
12
-1.26 V, Int
Ext (M)
Int
Ext (M)
Int
Int
Ext (M)
Int
10 V, Int
D,E
E, N, P, Q
D,N
E, N, P, Q
Q
D,M
Q
D
D
C, M
C, I, M
C, M
C, I, M
C, M
C, M
C, M
I,M
C, I, M
2-403
2-235
2-55
2-245
2-71
2-477
2-131
2-471
2-{)3
AD DACSO-I
AD DACS5-1
AD DACS7-1
AD566A
AD7541A
AD7548
12
12
12
12
12
12
0.3
0.3
0.3
0.35
0.6
1
12
12
12
12
8, p.P
6.3 V, Int
6.3 V, Int
6.3 V, Int
10 V, Ext
Ext (M)
Ext (M)
D
D
D
D
E, N, P, Q
E, N, P, Q
C
I,M
I,M
C,M
C, I, M
C, I, M
2-411
2-411
2-411
2-{)3
2-275
2-305
AD562
AD563
AD7542
AD7543
AD7545
AD7545A
AD7534
AD7535
AD7536
AD7538
*AD1856
AD DAC71-1
AD DAC72-1
*ADI860
12
12
12
12
12
12
14
14
14
14
16
16
16
18
1.5
1.5
2.0
2.0
2.0
1.0
1.5
1.5
1.5
1.5
0.35
1
1
0.35
12
12
4, p.P
Serial, p.P
12, fLP
12, fLP
8, p.P
8/14, p.P
8114, p.P
14, p.P
Serial, p.P
16
16
Serial, p.P
Ext
2.5 V, Int
Ext (M)
Ext (M)
Ext (M)
Ext (M)
Ext (M)
Ext (M)
Ext (M)
Ext (M)
Int
6.3 V, Int
6.3 V, Int
Int
D
D
D, E, N,
D, E, N,
E, N, P,
E, N, P,
D,N,P
D, E, N,
D, E, N,
N,Q
N
D,H
D,H
N
C,
C,
C,
C,
C,
C,
C,
C,
C,
C,
C
C
C,
C
2-59
2-59
2-281
2-289
2-293
2-297
2-251
2-255
2-259
2-267
2-161
2-407
2-407
2-171
Ultrahigh Speed, ECL Compatible, 20 mA Output Current
CMOS, Low Cost, 8-Bit Multiplying DAC with Latch
Industry Standard 10-Bit DAC, JAN Part Available
CMOS, Low Cost 10-Bit Multiplying DAC
Highest Accuracy 12-Bit Ultrahigh Speed DAC
Ultrahigh Speed 12-Bit DAC
Multiplying 12·Bit Ultrahigh Speed DAC
Ultrahigh Speed 12-Bit Multiplying DAC
Industry Workhorse High Speed DAC.
JAN Part Available
Industry Standard, High Speed DAC
Improved Industry Standard
Improved Industry Standard
High Speed DAC
CMOS, 12-Bit Multiplying DftC
CMOS, Byte Load 12-Bit DAC, Specified with
Single and Dual Supplies
Industry Standard, JAN Part Available
Industry Standard
CMOS, Nibble Load 12-Bit Multiplying DAC
CMOS, Serial Load 12-Bit Multiplying DAC
CMOS, Parallel Load 12-Bit MUltiplying DAC
CMOS, Improved AD7545
CMOS, Byte Load
CMOS, Parallel or Byte Load
CMOS, Parallel or Byte Load, Bipolar Output
CMOS, Parallel Load
16-Bit PCM Audio DAC
High Resolution 16-Bit DAC
High Resolution 16-Bit DAC
I8-Bit PCM Audio DAC
Model
CJ
§
);!
r;-
d
:h
....~
Cl
G')
C')
Cl
<:
~
::1)
~
~
~
U1
12
P
P,Q
Q
Q
P
P
I, M
M
I, M
I, M
I, M
I, M
I, M
I, M
I, M
I, M
I
'This column lists the data format for the bus with "!,-P" indicating microprocessor capability-i.e., for a l2-bit converter 8112, !,-P indicates that the data can be formatted for an 8-bit bus or can be in parallel (12
bits) and is microprocessor compatible .
'Ext indicates external reference with the range of voltages listed where applicable. Ext (M) indicates external reference with multiplying capability. Int indicates reference is internal. A voltage value is given if the
reference is pinned out.
'Package Options: D-Side-Brazed Dual-In-Line Ceramic; E-Leadless Chip Carrier; H-Round Hermetic Metal Can (Header); M-Metal Hermetic Dual-In-Line; N-Plastic Molded Dual-In-Line; P-Plastic Leaded
Chip Carrier (PLCC); Q-(:erdip; W-CeramiclGiass Dual-In-Line, Non-Hermetic; Z-Ceramic Leaded Chip Carrier.
'Temperature Ranges: C-Commercial, 0 to +70OC; I-Industrial, -40°C to +8S oC (Some older products -25°C to +8S°C); M-Militaty, -55°C to +12S oC.
'PLLCC = Plastic Leadles, Chip Carrier.
Boldface Type: Product recommended for new design.
*New product since the publication of the 198711988 Databooks.
•
"l-'
0)
S2
e
~
Selection Guide
Digital-to-Analog Converters
I"-
~
:l.
Update
Rate
~
l"-
Q
c;)
C)
Q
<:
~
~
~
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VIDEODACs
Settling
Time
ns
max
Reference
Voltage
IntlExr
Package
Options2
Temp
Range3
Page
Comments
Int
D,W
N
P
D,W
I
C
C
I,M
2-391
2-431
2-441
2-395
8
Int
E,Q
I,M
2-385
9
12
Int
Ext
14
25
25
Int
-1.2 V, Int
-1.2 V, Int
D,W
D,W
P
N,P
D,W
N,P
N,P
I,M
I,M
C
C
I
C
C
2-463
2-379
2-441
2-421
2-467
2-399
2-399
RGB Output, TIL or ECL Interface
CMOS, Triple 6·Bit Color Palette RAM·DAC
CMOS, Triple 6·Bit Color Palette RAM·DAC
Synchronous Composite Functions, Designed for
High Resolution Screens, 300 MHz Update Rate
Low Power, Low Glitch Impulse, Synchronous
Composite Functions, 250 MHz Update Rate
-5.2 V Power Supply
Single -5.2 V Power Supply, On·Chip Reference
CMOS, Triple 8·Bit Color Palette RAM·DAC
CMOS, Triple 8·Bit Color Palette RAM·DAC
TIL·Compatible Inputs
TTL Compatible Inputs, Low Glitch Energy
ECL Compatible Inputs, Low Glitch Energy
Model
Res
Bits
MHz
min
AD9702
*ADV476
*ADV471
AD9703
4
6
6
8
125
66,50,35
80,50,35
300
5
Ext
6
AD9701
8
225
8
8
8
8
8
12
12
150
100
SO, 50, 35
HDG·0805
AD9700
*ADV478
*ADV453
HDG·0807
*AD9713
*AD9712
66,40
50
SO
100
LOGDACs™
Model
Res
dB
Full Scale
Range
dB
AD7111
0.375
88.5
Accuracy
dB
Package
Options2
Temp
Range3
Page
Comments
0.17
E,N,Q
C,I,M
C2-183
Low Distortion
LOGDAC is a trademark of Analog Devices, Inc.
MULTIPLE DACs
§
i;!
r-
~
:l:.
~
r-
0
G)
(")
0
~
Settling
Time
Jl.s
typ
Bus
Interface
Bits4
Reference
Volt
IntlExt'
#
DACs
Package
Options'
Temp
Range'
Page
Comments
V
1
8, Jl.P
Int
2
N,P
C, I, M
3-237
8
V
2.5
8, Jl.P
Ext
2
N,P
C, I
3-329
AD7225
8
V
5
8, Jl.P
2-12.5 V, Ext
4
E, N, P, Q
C, I, M
2-193
AD7228
8
V
5
8, Jl.P
2-10 V, Ext
8
E, N, P, Q
C, I, M
2-205
AD7226
8
V
7
8, Jl.P
2-12.5 V, Ext
4
E, N, P, Q, R
C, I, M
2-199
AD392
12
V
4
12, Jl.P
Int
4
M
C
2-21
AD390
*AD7237
*AD7247
AD664
AD394
12
12
12
12
12
V
V
V
V
V
8
10
10
15
12, Jl.P
8, Jl.P
12, Jl.P
12, Jl.P
12, Jl.P
+10 V, Int
+5 V, Int
+5 V, Int
±14.5 V, Ext (M)
±ll V, Ext (M)
4
2
2
4
4
D
N,P,Q
N,P,Q
D, E, N, P
D
C,
C,
C,
C,
C,
AD395
12
V
15
12, Jl.P
±ll V, Ext (M)
4
D
C,M
2-27
AD396
14
V
15
8, Jl.P
±1l V, Ext (M)
4
D
C,M
2-35
AD7528
8
0.2
8,JJ.P
Ext (M)
2
E, N, P, Q,R
C, I, M
2-241
AD7628
8
0.35
8,I1P
Ext eM)
2
E, N, P, Q
C, I, M
2-325
AD7537
AD7547
AD7549
12
12
12
1.5
1.5
1.5
8,I1P
12, I1P
4,I1P
Ext eM)
Ext eM)
Ext eM)
2
2
E,N,P,Q
E, N, P, Q
D, E, N, P
C, I, M
C, I, M
C, I, M
2-263
2-301
CMOS, Complete 8·Bit Dual
DAC/ADClSHAJReference
CMOS, Complete 8·Bit Dual DACI
2·Channel ADC
CMOS, Separate Reference for
Each DAC
CMOS, Specified with Single and
Dual Supplies, Skinny 20·Pin Package
CMOS, No User Trims, Specified
with Single and Dual Supplies
Fast Bus Access Time «40ns),
Data Readback Capability
Factory Trimmed Gain and Offset
CMOS, Complete 12·Bit Dual, Byte Load
CMOS, Complete 12·Bit Dual, Paranel Load
Readback, Reset, Low Power Quad DAC
Four Independent Reference Inputs,
Precision Amps for Bipolar Output
Four Independent Reference Inputs,
Precision Amps for Unipolar Output
Four Independent Reference Inputs,
Bipolar Output, Simultaneous Update
CMOS, +5 V to +15 V Operation, TTL
Compatible at VDD 5 V
CMOS, + 12 V to + IS V Operation, TTL
Compatible at VDD = 12 V to 15 V
CMOS, Byte Load, Double Buffered
CMOS, Parallel Load
CMOS, Nibble Load, Double Buffered
Model
Res
Bits
Out
Mode
VII
*AD7669
8
*AD7769
10
2
M
I, M
I,M
I, M
M
2-13
2-213
2-213
2-103
2-27
2-317
=
'Ext indicates external reference with the range of voltages listed where applicable. Ext (M) indicates external reference with multiplying capability. Int indicates reference is internal. A voltage value is given if the
reference is pinned out.
'Package Options: D-Side·Brazed Dual-In-Line Ceramic; E-Leadless Chip Carrier; M-Metal Hermetic Dual-In-Line; N-Plastic Molded Dual-In-Line; P-Plastic Leaded Chip Carrier (PLCC); Q-<:erdip; R-Small
Outline Plastic (SOIC); W...(;eramidGlass Dual-in-Line, Non-Hermetic.
'Temperature Ranges: C...(;ommercial, 0 to +7O"C; I-industrial, -4O"C to +85 oC (Some older products -25°C to +850 C); M-Military, -55°C to + 125°C.
"'This column lists the data format for the bus with "".P" indicating microprocessor capability-i.e., for a 12-bit converter 8/12, ".p indicates that the data can be formatted for an 8-bit bus or can be in patallel (12 bits)
and is microprocessor compatible.
Boldface Type: Product recommended for new design.
*New product since the publication of the 1987/1988 Databooks.
M'i
::Q
~
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C/)
'1"
"
II
Orientation
Digital-to-Analog Converters
FACTORS IN CHOOSING A D/A CONVERTER
In this catalog there are listeq some 57 different families of
digital-to-analog converters (DACs). If one were to consider all
the variations, there would Ix! several times that number to
choose among. The reason for so many different types is the
number of degrees of freedom in selection - technological, functional, performance and package. Complete information on
converters may be found in the 700-page book, Analog-Digital
Conversion Handbook, published by Prentice-Hall, Inc.
FUNCTIONAL CHARACTERISTICS
The basic structure of all conventional DIA converters involves
a network of precision resistors, a set of switches and some form
of level-shifting to adapt the switch drives to the specified logic
levels. In addition, the device may contain output-conditioning
circuitry, an output amplifier, a reference amplifier, an on-board
reference, on-board buffer registers (single- or dual-rank), configuration conditioning and even high-voltage isolation.
Basic DAC
This form which supplies a current, and consequently a small
voltage across its internal impedance or an external low-impedance
load, is used principally for high speed, for example, the IOns
HDM-121O. Basic current-output DACs, such as the AD565A,
are inherently fast, but additional elements (such as an output
op amp), furnished by the user to meet overall system specs,
slow down the conversion. Some popular CMOS IC devices,
such as the AD7543 and the AD7524, are quite simple (and
correspondingly low in cost), but they usually require a buffering
op amp.
While the basic DAC function is almost always linear, there are
exceptions. For example, the AD7111 LOGDAC, which has
linear two-quadrant analog response, has a digitally controlled
exponential gain function, i.e., 0.375dB per bit; thus its gain at
the input code 1000 0000 (binary 128) is -48dB (48 x 0.375),
and the analog output swing for lOY p-p input is 0.04 p-pVIN
0.375N)
toexp- ( -W.
Output Conditioning
The analog quantity that is the "output" of a DAC, representing
the input digital data may be a "gain" (multiplying DAC), a
current and/or a voltage. In order to obtain a substantial voltage
output at low impedance, an op amp is required. It is often
provided by the DAC itself (whether monolithic, modular or
hybrid), but many permit the user to choose an external op amp
that will meet the particular needs of the application in stability,
speed and cost.
Almost all types of DACs provide one or more feedback resistors;
they are matched to, and thermally track, resistances in the
network so that an external op amp, if used, will not require an
external feedback resistor that might introduce tracking errors.
If more than one feedback resistor is provided, a choice of analog
output voltage ranges becomes available, e.g.,
5V full-scale
or
10V full-scale. If bipolar output-voltage ranges are specified,
a bipolar-offset resistor is provided to subtract a half-scale value
from the current flowing through the cOp amp summing point; it
is usually derived from the DAC's reference (or analog) input to
°-
2-8 DIGITAL-TO-ANALOG CONVERTERS
°-
avoid. additional tracking error. Multiplying DACs use an internal
or external op amp for bipolar offset.
In order to avoid difficulties, the user must pay special attention
to the specified output polarity, its relationship to the reference
(if external) and to the input digital code. This can be especially
tricky if the output is bipolar and the input requires a complementary (negative-true) digital coding. Another such case is
where a current-output DAC, specified for a particular outputvoltage polarity when used with an inverting op amp, is used in
a mode that develops an output voltage passively (without the
op amp) across lip external resistive load. In addition to polarity,
in this case, the user should be aware of the output-compliance
constraint and the specified resistive component of output
impedance.
Reference Input
The reference may be specified as external or internal, fixed or
variable, single polarity or bipolar. If internal, it may be permanently connected (as in the AD561) or optionally connectible (as
in the AD565A). If the DAC is a 4-quadrant mUltiplying type,
the reference (or "analog input") is external, variable and bipolar
(e.g., AD7533, AD7541, AD7541A, etc.). The user should
check a converter's specifications to determine whether the fullscale accuracy specifications are overall or subdivided into a
converter-gain spec and a reference spec.
Digital Data
There a number of ways in which converters differ in regard to
the input data: first, the coding must be appropriate (binary,
offset-binary, twos complement, BCD, arbitrary, etc.), and its
sense should be understood (positive-true, negative-true). The
resolution (number of bits) must be sufficient; in addition, the
specifications must be checked to ascertain that the 2° distinct
binary input codes will not only be accepted, but that also they
will (if necessary) correspond to 2D output values in a monotonic
progression at any temperature in the operating range with
sufficient accuracy. Analog Devices offers DACs with resolutions
of 8, 10, 12, 14, 16 and 18 bits. The data levels accepted by the
converter must be checked (TTL, ECL, low-voltage CMOS,
high-voltage CMOS), as must.the input loading imposed by the
converter and the supply conditions under which the converter
will respond to the data. Check the data notation (is the MSB
Bit I or Bit (n-I)?) - misinterpretation can lead to connecting
the data bits in backward order.
If buffer registers are desired, the converter should have an appropriate buffer configuration (for example, the AD558 and
AD7226 have a set of TTL buffers; the AD667 and AD7224
have two ranks of buffering).
Controls
If the DAC has external digital controls - for example, register
strobes - their drive levels, digital sense (true or false), loading
and timing must be considered. The function and use of configuration controls (where present), such as serial/parallel, short-cycle
or chip-select decoding, should be understood, and the appropriate
ways of disabling them when not needeq shoulq be employed.
Many DACs are specifically designed to interface directly to the
bus of the computer or microprocessor. These DACs provide
the necessary control and handshake lines, as well as the data
bit buffers, to minimize and often eliminate the interface circuitry
required. The bus timing should be studied with respect to the
timing provided by the DAC interface, especially as the processor
performs a data-write cycle to the DAC. Systems with higher
speed clocks require either shorter DAC strobe times (such as
the AD767) or the use of processor-wait states when the DAC is
addressed. DACs for video applications, such as the AD9701,
provide special control lines unique to CRT applications (e.g.
blanking, sync and reference level display).
STATIC AND DYNAMIC PERFORMANCE
SPECIFICATIONS
All DACs are specified using terms such as accuracy, linearity,
offset, defined and explained below. These static, or "dc,"
parameters are necessary and sufficient for many applications;
they may not be sufficient for others, such as those in digital
signal processing, adaptive filtering, or waveform generation.
Dynamic, ac specifications define how the DAC performs using
parameters such as signal-to-noise ratio (SNR), intermodulation
distortion (IMD) and total harmonic distortion (THD). These
specifications characterize the performance of the DAC output
in applications where the envelope of output changes and output
timing errors are critical.
POWER SUPPLIES
Appropriate power supplies should be made available considering
the logic levels and analog output signals to be employed into
the system. The appropriate degree of power-supply stability to
meet the accuracy specs should be employed. In many cases
separate analog and digital grounds are required; ground wiring
should follow best practice to minimize digital interference with
high-accuracy analog signals while ensuring that a connection
between the grounds can always exist at one point, even if the
"mecca" point is inadvertently unplugged from the system.
SPECIFICATIONS AND TERMS
Definitions of the performance specifications and related information are provided on the next few pages in alphabetical order.
Accuracy, Absolute
Error of a DIA converter is the difference between the actual
analog output and the output that is expected when a given
digital code is applied to the converter. Sources of error include
gain (calibration) error, zero error, linearity errors and noise.
Error is usually commensurate with resolution, i.e., less than
2-(·+1), or "1I2LSB" of full scale. However, accuracy may be
much better than resolution in some applications; for example, a
4-bit reference supply having only 16 discrete digitally chosen
levels would have a resolution of 1116, but it might have an
accuracy to within 0.01% of each ideal value.
Absolute accuracy measurements should be made under a set of
standard conditions with sources and meters traceable to an
internationally accepted standard.
Accuracy, Relative
Relative accuracy error, expressed in %, ppm or fractions of
I LSB is the deviation of the analog value at any code (relative
to the full analog range of the device transfer characteristics)
from its theoretical value (relative to the same range) after the
full-scale range (FSR) has been calibrated. Since the discrete
analog output values corresponding to the digital input values
ideally lie on a straight line, the relative accuracy error of a
linear DAC can be interpreted as a measure of nonlinearity (see
Linearity) .
Compliance-Voltage Range
For a current-output DAC, the maximum range of (output)
terminal voltage for which the device will provide the specified
current-output characteristics.
Common-Mode Rejection (CMR)
The ability of an amplifier to reject the effect of voltage applied
to both input terminals simultaneously. Usually a logarithmic
expression representing a "common-mode rejection ratio" e.g.,
1,000,000:1 (CMRR) or 120dB (CMR). A CMRR of 106 :1 means
that a IV common-mode voltage passes through the device as
though it were a differential input signal of I microvolt.
Common-Mode Voltage
An undesirable signal picked up in a circuit by both wires making
up the circuit, with reference to an arbitrary "ground." Amplifiers
differ in their ability to amplify a desired signal accurately in
the presence of a common-mode voltage.
Deglitcher
As the input code to a DAC is increased or decreased by small
changes, it passes through what is known as major and minor
transitions. The most major transition is at half-scale when the
DAC switches around the MSB and all switches change state,
Le.,Olll 1111 to 1000 0000. If, at major transitions, the switches
are faster (or slower) to switch off than on, this means that for a
short time the D/A will give a zero (or full-scale) output and
then return to the required ILSB above the previous reading.
Such large transient spikes which differ widely in amplitude and
are extremely difficult to filter out are commonly known as
"glitches," hence, a deglitcher is a device which removes these
glitches or reduces them to a set of small, uniform pulses. It
normally consists of a fast sample-hold circuit which holds the
output constant until the switches reach equilibrium. Glitch
energy is smallest in fast-switching DACs driven by fast logic
gates that have little time skew between 0-1 and 1-0 transitions.
100~0000
01111111
_=-=~
-- ==-=-~- -
WITH IDEAL DEGLITCHER
GLITCH
Feedthrough
Undesirable signal coupling around switches or other devices
that are supposed to be turned off or provide isolation, e.g.,
feedlhrough error in a mUltiplying DAC. It is variously specified
in %, ppm, fractions of ILSB or fractions of I volt with a given
set of inputs at a specified frequency.
Four-Quadrant
In a multiplying DAC, "four quadrant" refers to the fact that
both the reference signal and the number represented by the
digital input may be of either positive or negative polarity. A
four-quadrant multiplier is expected to obey the rules of multiplication for algebraic sign.
DIGITAL-TO-ANALOG CONVERTERS 2-9
•
Gain
The "gain" of a converter is that analog scale-factor setting that
provides the nominal conversion relationship, e.g., IOV span for
a full-scale code change in a fixed-reference converter.. For
fixed-reference converters where the use of the internal reference
is optional, the converter gain and the reference may be specified
separately. Gain- and zero-adjustment are discussed under Zero.
Harmonic. Distortion (and Total Harmonic Distortion)
The DAC is driven by the digitized representation of a sine
wave. The ratio of the rms sum of the harmonics of the DAC
output to the fundamental value is the THD. Usually only the
lower order harmonics are included such as second through
fifth:
(V 2 + V 2 + V 2 + V 2)1/2
THD=20 log 2
3
4
5
VI
where VI is the rms amplitude of the fundamental and V2, V3,
V4 and V5 are the rms amplitudes of the individual harmonics.
Intennodulation Distortion
The DAC is driven by the digitized representation of two combined
sine waves of frequencies fa and fb. As with any imperfectly
linear device, distortion products (of order m + n) are produced
at sum and difference frequencies of rnfa ± nfb where m, n = 0,
1,2,3, .... Intermodulation terms are those for which m or n
is not equal to zero. The second order terms include (fa + fb)
and (fa - fb) and the third order terms are (2fa + f b), (2fa - fb),
(f. + 2fb) and (fa - 2fb). IMD is defined as:
IMD = 20 10 (rms sum of the sum and difference distortion products)
g
rms amplitude of the fundamental
Least-Significant Bit (LSB)
In a system in which a numerical magnitude is represented by a
series of binary (i.e., two-valued) digits, the LSB is that bit that
carries the smallest value or weight. For example, in the natural
binary number 1101 (decimal 13, or 23 + 22 + 0 + 2~, the
rightmost digit is the LSB. Its analog weight, relative to full
scale is Z- where n is the number of binary digits. It represerits
the smallest analog change that can be resolved by an n-bit
converter.
Linearity
Linearity error of a converter (also integral nonlinearity, see
Linearity, Differential), expressed in %, ppm of full-scale range
or (sub)multiples of lLSB, is a deviation of the analog values in
a plot of the measured conversion relationship from a straight
line. The straight line can be either a "best straight line" determined empirically by manipulation of the gain and/or offset to
equalize maximum positive and negative deviations of the actual
transfer characteristics from this straight line; or it can be a
straight line passing through the end points of the transfer characteristic after they have been calibrated (sometimes referred to
as "end-point" linearity). End-point linearity error is similar to
relative accuracy error.
For multiplying D/A converters, the analog linearity error, at a
specified digital code, is defmed in the same way as for multipliers,
i.e., by deviation from a "best straight line" through the plot of
the analog output-input response.
2-10 DIGITAL-TO-ANALOG CONVERTERS
"F.S.;:-"------,;;""--:>">1
"BEST"
7/8
6'.
LINEAR ENVElOPE
STRAIGHT LINE
'"~.,...---....
SIB.
."I
----::"-.1
NONUJEARITY
LESS THAN
LS.
J
OFFSET
000 001 OlD 011 100 101 110 111
a. Y.LSB Nonlinearity Achieved
By Arbitrary Location of "Best
Straight Line".
000 Oat 010 011 100 101 "0 111
b. Nonlinearity Reference is
Straight Line Through End
Points. Nonlinearity >%LSB
for Curve of a.
Comparison of Linearity Criteria for 3-Bit D/A Converter.
Straight Line Through End Points is Easier to Measure, Gives
More Conservative Specification.
Linearity, Differential
Any two adjacent digital codes should result in measured output
values that are exactly ILSB apart (2-n of full scale for an n-bit
converter). Any deviation of the measured "step" from the ideal
difference is called differential nonlinearity expressed in (sub)multiples oflLSB. It is an important specification because a differential
linearity error greater than lLSB can lead to nonmonotonic
response in a DIA converter and missed codes in an AID converter
(see Differential Linearity in the AID converter section for an
illustration).
Monotonic
A DAC is said to be monotonic if the output either increases or
remains constant as the digital input increases with the result
that the output will always be a single-valued function of the
input. The specification "monotonic" (over a given temperature
range) is sometimes substituted for a differential nonlinearity
specification since differential nonlinearity less than ILSB is a
sufficient condition for monotonic behavior.
Most-Significant Bit (MSB)
In a system in which a numerical magnitude is represented by a
series of binary (i.e., two-valued) digits, the MSB is that digit
(or bit) that carries the largest value of weight. For example, in
the natural binary number 1101 (decimal 13, or 23 + 22 + 0 +
2~, the leftmost "I" is the MSB with a weight of 20-1, or 8LSBs.
Its analog weight, relative to a DAC's full-scale span, is 112. In
bipolar DACs, the MSB indicates the polarity of the number
represented by the rest of the bits.
Multiplying DAC
A multiplying DAC differs from a fixed-reference DAC in being
designed to operate with varying (or ac) reference signals. The
output signal of such a DAC is proportional to the product of
the "reference" (i.e., analog input) voltage and the fractional
equivalent of the digital input number (see also four-quadrant).
Noise, Peak and rms
Internally generated random noise is not a major factor in D/A
converters, except at extreme resolutions (e.g., DACI138) and
dynamic ranges (AD7111). Random noise is characterized by
rms specifications for a given bandwidth or as a spectral density
(current or voltage per root hertz); if the distribution is Gaussian,
the probability of peak-to-peak values exceeding 7x the rms
value is less than 0.1 %.
Of much greater importance in DACs is interference in the
form of high-amplitude low-energy (hence low-rms) spikes appearing at the DAC's output caused by coupling of digital signals
in a surprising variety of ways; they include coupling via stray
capacitance, via power supplies, via inadequate ground systems,
via feedthrough and by glitch generation. Their presence underscores the necessity for maximum application of the designer's
art, including layout, shielding, guarding, grounding, bypassing
and deglitching.
Offset
For almost all bipolar converters (e.g., :±: 10-volt output), instead
of actually generating negative currents to correspond to negative
numbers, a unipolar DAC is used and the output is offset by
half full scale (IMSB). For best results, this offset voltage or
current is derived from the same reference supply that determines
the gain of the converter.
This makes the zero point of the converter independent of thermal
drift of the reference because the 112 scale offset cancels the
weight of the MSB at zero, independently of the amplitude of
both.
Power-Supply Sensitivity
The sensitivity of a converter to changes in the power-supply
voltages is normally expressed in terms of percent-of-full-scale
change in analog output value (of fractions of I LSB) for a 1%
dc change in the power supply, e.g., 0.05%/l°/o,lVs). Power
supply sensitivity may also be expressed in relation to a specified
dc shift of supply voltage. A converter may be considered "good"
if the change in reading at full scale does not exceed :±: 1I2LSB
for a 3% change in power supply. Even better specs are necessary
for converters designed for battery operation.
Quantizing Uncertainty (or "Error")
The analog continuum is partitioned into 2n discrete ranges for
n-bit processing. All analog values within a given range of output
(of a DAC) are represented by the same digital code usually
assigned to the nominal midrange value. For applications in
which an analog continuum is lo be restored, there is an inherent
quantization uncertainty of :±: 1I2LSB due to limited resolution,
in addition to the actual conversion errors. For applications in
which discrete output levels are desired (e.g., digitally controlled
power supplies or digitally controlled gains), this consideration
is not relevant.
Resolution
An n-bit binary converter should be able to provide 2n distinct
and different analog output values corresponding to the set of nbit binary words. A converter that satisfies this criterion is said
to have a resolution of n bits. The smallest output change that
can be resolved by a linear DAC is 2-n of the full-scale span.
However, a nonlinear device, such as the AD7111 LOGDAC,
has a logarithmic gain resolution of 0.375/88.5dB = 1:256dB
which corresponds to a gain increment of 4.25%/step or
26,600:1.
Settling Time
The time required, following a prescribed data change, for the
output of a DAC to reach and remain within a given fraction
(usually ± 1I2LSB) of the final value. Typical prescribed changes
are full scale, IMSB and lLSB at a major carry. Settling time of
current-output DACs is quite fast. The major share of settling
time of a voltage-output DAC is usually contributed by the
settling time of the output op amp circuit.
Signal-to-Noise Ratio
Signal-to-Noise Ratio (SNR) is the measured signal to noise at
the output of the converter. The signal is the rms magnitude of
the fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency. SNR is dependent on
the number of quantization levels used in the digitization process;
the more levels, the smaller the quantization noise. The theoretical
SNR for a sine wave is given by:
SNR = (6.02N + 1.76) dB
where N is the number of bits. Thus for an ideal 8-bit converter,
SNR = 50dB.
Slew Rate (or Slewing Rate)
Slew rate of a device or circuit is a limitation in the rate of
change of output voltage, usually imposed by some basic circuit
consideration such as limited current to charge a capacitor.
Amplifiers with slew rate of a few V/fJ-s are common and moderate
in cost. Slew rates greater than about 75 volts/fJ-s are usually
seen only in more sophisticated (and expensive) devices. The
output slewing speed of a voltage-output DIA converter is usually
limited by the slew rate of the amplifier used at its output (if
one is used).
Stability
Stability of a converter usually applies to the insensitivity of its
characteristics to time, temperature, etc. All measurements of
stability are difficult and time consuming, but stability vs. temperature is sufficiently critical in most applications to warrant
universal inclusion of temperature coefficients in tables of specifications (see "Temperature Coefficient").
Staircase
A voltage or current increasing in equal incrementYas a function
of time and having the appearance of a staircase (in a time plot)
generated by applying a pulse train to a countJ' and the output
of the counter to the input of a DAC.
A very simple AID converter can be built by comparing a staircase
from a DAC with the unknown analog input. When the DAC
output exceeds the analog input by a fraction of lLSB, the
count is stopped and the code corresponding to the count is the
digital output.
Switching Time
In a DAC, the switching time is the time it takes for the switch
to change:- from one state to the other ("delay time" plus "rise
time" from 10% - 90%) but does not include settling time, e.g.,
to <1I2LSB.
DIGITAL- TO-ANALOG CONVERTERS 2-11
2
Temperature Coefficients
In general, temperature instabilities are expressed as %I"C, ppm/
°C, as fractions of 1LSB/oC or as a change in a parameter over a
specified temperature range. Measurements are usually made at
room temperature and at the extremes of the specified range,
and the temperature coefficie!lt (tempco, T.C.) is defined as the
change in the parameter divided by the correspoJ;lding temperature
change. Parameters of interest include gain, linearity, offset (bipolar)
and zero.
Gain Tempco: Two factors principally affect converter gain
stability with temperature.
a) In fixed-reference converters, the reference source will
vary with temperature. For example, the tempco of
an ADS81L is generally less than Sppm/°C.
b) The reference circuitry and switches may add another
3ppm/oC in good 12-bit converters (e.g. ADS66K1T).
High resolution converters require much better tempcos
for accuracy commensurate with the resolution.
Linearity Tempco: Sensitivity of linearity ("integral" and/or
·differentiallinearity) to temperature (in % FSRloC or ppm FSruoC)
over the specified range. Monotonic behavior is achieved if the
differential nonlinearity is less than lLSB at any temperature in
the range of interest. The differential nonlinearity temperature
coefficient may be expressed as a ratio, as a maximum change
over a temperature range and/or implied by a statement that the
device is monotonic over the specified temperature range.
2-12 DIGITAL-TO-ANALOG CONVERTERS
Offset Tempco: The temperature coefficient of the all-DACswitches-off (minus full scale) point of a bipolar converter (in %
FSRloC or ppm FSRl°C) depends on three major factors:
a) The tempco of the reference source
b) The voltage zero-stability of the output amplifier
c) The tracking capability of the bipolar-offset
resistors and the gain resistors
Unipolar Zero Tempco (in % FSRI"C or ppm FSRI"C): The
temperature stability of a unipolar fixed-reference DAC is principally affected by current leakage (current-output DAC) and
offset voltage and bias current of the output op amp (voltage-output
DAC).
Total Unadjusted Error
Total unadjusted error is a comprehensive specification which
includes internal voltage reference error, relative accuracy, gain
and offset errors.
Zero- and Gain-Adjustment Principles
The output of a unipolar DAC is set to zero volts in the all-bits-off
condition. The gain is set for F.S.(l - 2-D ) with all bits on.
The "zero" of an offset-binary bipolar DAC is set to -F.S.
with all bits off, and the gain is set for + F.S.(l - 2-(0-1)) with
all bits on. The data sheet instructions should be followed.
r.ANALOG
WDEVICES
FEATURES
Four Complete 12-Bit DACs in One IC Package
Linearity Error :t: 1/2LSB T min - T max (AD390K, T)
Factory-Trimmed Gain and Offset
Buffered Voltage Output
Monotonicity Guaranteed Over Full Temperature Range
Double-Buffered Data Latches
Includes Reference and Buffer
Fast Settling: 8jJ.s max to :t: 1/2LSB
Quad 12-Bit MicroprocessorCompatible OfAConverter
A0390* I
AD390 FUNCTIONAL BLOCK DIAGRAM
-v,
DGND
AGND
PRODUCT DESCRIPTION
The AD390 contains four 12-bit high speed voltage-output
digital-to-analog converters in a compact 28-pin hybrid package.
The design is based on a proprietary latched 12-bit DAC chip
which reduces chip count and provides high reliability. The
AD390 is ideal for systems requiring digital control of many
analog voltages where board space is at a premium. Such applications include automatic test equipment, process controllers,
and vector-scan displays.
The AD390 is laser-trimmed to ± 1I2LSB max nonlinearity
(AD390KD, TD) and absolute accuracy of ±O.OS percent of
full scale. The high initial accuracy is made possible by the use
of thin-film scaling resistors on the monolithic DAC chips. The
internal buried zener voltage reference provides excellent temperature drift characteristics (20ppml"C) and an initial tolerance
of ± 0.03% maximum. The internal reference buffer allows a
single common reference to be used for multiple AD390 devices
in large systems.
The individual DACs are accessed by the CSI through CS4
control inputs and the AO and Al lines. These control signals
permit the registers of the four DACs to be loaded sequentially
and the outputs to be simultaneously updated.
The AD390 outputs are calibrated for a ± IOV output range
with positive-true offset binary input coding. A 0 to + 10V
version is available on special order.
The AD390 is packaged in a 28-lead ceramic package and is
specified for operation over the 0 to + 70°C and - SSoC to + 12SoC
temperature range.
'Covered by patent numbers 3,803,590; 3,890,611; 3,932,863;
3,978,473; 4,020,486 and olber patents pending.
PINS 1-12
D8O{LSBI - DB11jMSB)
PRODUCT HIGHLIGHTS
1. The AD390 offers a dramatic reduction in printed circuit
board space requirements in systems using mUltiple DACs.
2. Each DAC is independently addressable, providing a versatile
control architecture for simple interface to microprocessors.
All latch enable signals are level-triggered.
3. The output voltage is trimmed to a full scale accuracy of
± 0.05%. Settling time to ± 1I2LSB is 8 microseconds
maximum.
4. An interna110 volt reference is available or an external reference
can be used. With an external reference, the AD390 gain TC
is ± Sppm/°C maximum.
S. The proprietary monolithic DAC chips provide excellent
linearity and guaranteed monotonicity over the full operating
temperature range.
6. The 28-pin double-width hybrid package provides extremely
high functional density. No external components or adjustments
are required to provide the complete function.
7. The AD390SD and AD390TD feature guaranteed accuracy
and linearity over the - 55°C to + 12SoC temperature range.
DIGITAL-TO-ANALOG CONVERTERS 2-13
•
SPECIFICATIONS
(TA
= +25"&, Vs = ±15V unless oIhlllWise specified)
Model
Min
DATA INPUTS (Pins 1-12 and 23-28)1
Except Pin 24 TTL or 5 Volt CMOS
Input Voltage
Bit ON (Logic "1")
Bit OFF (Logic "0")
Input Current (Pin 24 is 3 x Larger)
Bit ON (Logic "1")
Bit OFF (Logic "0")
AD390JD/SD
Typ
+2.0
+5.5
+0.8
+2.0
AD390KD/TD
Typ
Max
1200
400
!LA
12
12
Bits
4
± 10
5
8
V
rnA
4
± 10
5
8
±0.05
±0.025
± 114
± 112
±0.1
±0.05
±3/4
±3/4
±0.025
±0.012
± 118
±1I4
±0.05
±0.025
± 112
± 112
1200
500
150
400
±40
±20
±5
±1O
±10
±5
± 112
±3/4
±1I4
± 112
MONOTONICITY GUARANTEED OVER FULL TEMPERATURE RANGE
CROSS TALKs
0.1
REFERENCE OUTPUT
Voltage (without load)
Current (available for external use)
9.997
2.5
REFERENCE INPUT
Input Resistance
Voltage Range
5
POWER REQUIREMENTS
Voltage6
Current
+Vs
-Vs
POWER SUPPLY GAIN SENSITIVITY
+Vs
-Vs
TEMPERATURE RANGE
Operating (Full Specifications)J, K
S,T
Storage
10.000
3.5
0.1
10.003
9.997
2.5
11
5
± 15
± 16.5
± 13.5
12
-75
0.002
0.0025
0
-55
-65
10.000
3.5
%ofFSR4
%ofFSR
LSB
LSB
ppml"C
ppml"C
ppml°C
LSB
V
rnA
11
V
± 15
± 16.5
V
20
-90
12
-75
20
-90
rnA
rnA
0.006
0.006
0.002
0.0025
0.006
0.006
%FS/%
%FS/%
+70
+ 125
+ 150
°C
°C
°C
n
1010
+70
+ 125
+ 150
0
-55
-65
'Timing specifications appear in Table II.
'The AD390 outputs are guaranteed stable for load capacitances up to 300pF.
':!: 10V range is standard. A 0 to lOY version is also available. To order, use the following part numbers:
ADS0207-I
J Grade
ADS0207-2
K Grade
ADS0207-3
SGrade
ADS0207 -4
T Grade
ADS0207 -7
S/8838 Grade
ADS0207-8
T/8838 Grade
4FSR means Full Scale Range and is equal to 20V for a :!: I OV range.
'Crosstalk is defined as the change in anyone output as a result of any other output being driven from - lOY to
"The AD390 can be used with supply voltage as low as :!: 11.4V, Figure 10.
2-14 DIGITAL-TO-ANALOG CONVERTERS
~
LSB
NOTES
Specifications subject to change without notice.
,..A
10.003
10 10
± 13.5
Units
V
V
RESOLUTION
TEMPERATURE DRIFT
Gain (internal reference)
(external reference)
Zero
Linearity Error T min - T max
Differential Linearity
Min
+ 5.5
+0.8
500
150
OUTPUT2
Voltage Range 3
Current
Settling Time (to ± V2LSB)
ACCURACY
Gain Error (w/ext. 1O.000V reference)
Offset
Linearity Error
Differential Linearity Error
Max
+ lOY into a 2krl load.
AD390
PIN CONFIGURATION
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
+Vs to DGND . . . . . . . . . . . .
· .0 to +18V
-Vs toDGND . . . . . . . . . . . .
· .0 to -18V
Digital Inputs (Pins 1-12, 23-28) to DGND .
-10 to +7V
Ref In to DGND . . . . . . .
. ±Vs
AGND to DGND . . . . . . . . . . . . . .
· . . . ±0.6V
Analog Outputs (Pins 16, 18-21)
. . . . . . . . . . . . . . Indefmite Shon to AGND or DGND
Momentary Shortto ± Vs
ORDERING GUIDE
Model
Temperature
Range
Gain Error
25°C
Tmin-Tmax
Package
Option*
AD390JD
AD390KD
AD390SD
AD390TD
Oto + 70°C
Oto + 70°C
-55°Cto + 125°C
- 55°C to + lZSoC
±4LSB
±2LSB
±4LSB
±ZLSB
±3/4LSB
± 1I2LSB
±3/4LSB
± lIZLSB
DH-28
DH-28
DH-28
DH-18
Linearity Error
*See Section 14 for package outline information.
DIGITAL-TO-ANALOG CONVERTERS 2-15
Digital Circuit Details
DATA AND CONTROL SIGNAL FORMAT
The AD390 accepts 12-bit parallel data in response to control
signals CSI-CS4, AO and Al The input registers are double-buffered, allowing any register to be updated independently of the
others. As detailed in Table I, the four chip select lines are used
to address the DAC register of interest. It is permissible to have
more than one chip select active at any time. The fU"st rank
register of a given DAC is loaded by bringing the appropriate
chip select and AO both low. The second rank register of any
DAC can then be loaded by bringing the appropriate chip select
Al both low. If CSI-CS4 are all brought low coincident with Al
low, all four DAC outputs will be updated to the value in the
corresponding first rank register. All control inputs are levcltriggered and may be hard-wired low to render any register (or
group of registers) transparent.
+y.
DGND
TIMING
The AD390 control signa1 timing is fairly straightforward. AO,
Al and CSI-CS4 must be concurrently valid for at least lOOns
fora desired operntion to occur. When loading data from a bus
into the first rank register, the data inputs must be stable for at
least SOns before any control signal returns high. Data can change
immediately after the control signals are inactive. When loading
the second mnk registers from the first mnk, it is possible to
exercise the chip select inputs at the same time as AI. DAC
settling time is measured from the falling edge of whichever
control signal last becomes valid.
WRITE CYCLE #1
(Load First Rank from Data Bus; Al = 1)
CiioCS4-----.t-==~wi
AGND
D811
o
c=
I;:::'DW-I
DB·----X
I y--
\\\
A.
1'~
~
I- ...,=!
WRITE CYCLE #2
(Load Second Rank from First Rank; AO = 1)
Figure 2. Timing Diagrams
Symbol Parameter
tAW
twp
tDW
tDH
tAS
tSETT
Min Typ Max Units
CS 1·4 Valid before AO Rising Edge
100
AO,AlLowTime
100
DBII·DBOvalid beforeAORising Edge SO
DBll·DBOvaiidafter AORising Edge
10
CSI-4valid before AI Low
0
Output Voltage Settling Time
ns
ns
ns
ns
ns
4
fLS
Table II. AD390 Timing Specifications
INTERFACING THE AD390 TO MICROPROCESSORS
The AD390 control logic provides simple interface to microprocessors. The latches are fast enough to operate with even the
fastest processors.
PINS 1-12
DBO(LSBI _ DB11IMSB}
Figure 1. AD390 FunctionslBlock Diagram
m
ffi
I
X
I
X
I
X
I
X
0
1
0
I
I
I
I
0
I
I
I
I
0
0
I
I
I
I
0
I
I
I
I
0
I
I
I
I
0
0
0
I
I
I
mm
Al AD Operation
X X NoOperation
I
I NoOperation
0
0
0
0
Enable 1st rank ofDAC I
Enable lst rank ofDAC 2
Enable lst rank ofDAC 3
Enable lst rank ofDAC 4
0
0
0
0
0
I
I
I
I
Load DAC I second rank from first rank
Load DAC 2 second rank from first rank
Load DAC 3 second rank from first rank
Load DAC 4 second rank from first rank
0
0
0 All latches transparent
Table I. AD390 Truth Table
2-16 DIGITAL-TO-ANALOG CONVERTERS
16-Bit Processors
The AD390 is a 12-bit resolution DAC system and is easily
interfaced to 16-bit wide data buses. Severnl possible addressing
configurntions exist.
In the circuit of Figure 3, the AD390 second mnk registers are
made transparent by hard-wiring Allow. A system WR signal
is used to drive the AO control input and a 74LS138 decoder
driven from the least significant address bits provides the active-low
CSI through CS4 signals. In this circuit, only one DAC at a
time may be updated. If simultaneous update of all four DACs
is required, a slightly different addressing scheme is used. The
circuit shown in Figure 4 allows selection of either register of
any DAC at the expense of larger memory space requirements.
In this circuit, address lines AO through A3 each select a single
DAC of the four contained in the AD390. The use of a sepamte
address line for each DAC allows seveml DACs to be accessed
AD390
simultaneously. The address lines are gated by the simultaneous
occurrence of a system WR and the appropriately decoded base
address. Selection of first rank or second rank register for any
DAC is done by using two additional address bits. The AD390
thus occupies a block of 64 memory word locations but offers
considerable flexibility in DAC updating.
In this addressing scheme, the AS and A4lines divide the 64
locations into 4 blocks. When both AS and A4 are high, no
operation occurs. When AS and A4 are both low, data written
into anyone of the DACs (selected by A3-AO) will immediately
update that analog output. In the address block where A4 is
low and AS is high, data is written into the first rank register
of the selected DAC (or DACs). When AS is low and A4 is
high, data previously written into the first rank register of
the selected DAC is transferred to the second rank register,
which updates the analog output. It is particularly useful to
perform a WR opemtion with AS low, A4 high, and A3
through AO all low (base address plus 32) since this action
will cause all four DAC outputs to be simultaneously updated
to the values previously written into the first rank registers.
In both addressing schemes shown, AO represents the least
significant word address bit. In most I6-bit systems this will
be the Al address line. Data may reside in either the I2MSBs
(left-justified) or the lower 12 bits (right-justified). Left jus-
,...,.
tification is useful when the data word represents a binary
fraction of full scale, while right-justified data usually represents
an integer value between 0 and 4095.
8-Bit Processors
Since the AD390 is designed to accept data in I2-bit words,
an external latch is required in order to interface with 8-bit
buses. Thus each DAC in the AD390 occupies 2 memory
locations. The choice of data format is similar to the choice
in the l6-bit bus interface. The data can either be right-justified
(one byte contains the 8LSBs and another the 4MSBs in the
bottom half of the byte) or left-justified (where one byte
contains the 8MSBs and another the 4LSBs in the top half of
the byte). The addressing scheme illustrated in Figure 6
allows 12-bit data to be sent to the first rank register of any
DAC in a right-justified format. The first rank register of
DAC occupies two memory locations-a write to the even (AO
low) address stores the 4MSBs of the DAC data in a 74LS173
quad latch. When the 8LSBs are written to the odd address
(AO = 1), the eight bits present on the data bus and the four
bits held in the 74LS173 are strobed into the first rank register
of the selected DAC. Address bits Al through A4 select the
DAC to be addressed, while A6 and AS enable either the
first or second rank register (or both) as in the I6-bit interface
of Figure 4.
~------''f
DATA
a. Right-Justified Data (0 =5 D =5 4095);
VOUT = -10V + (4.883mV x D)
BUS
ANAlOG
OUTPUTS
AD390
..
"'
I,
745139
b. Left-Justified Data, 0
VOUT = - 10V
~--------------~
+
=5
D
65520\.
=5 655361
(20V x D)
Figure 5. 12-Bit Data Formats for 16-Bit Bus
Figure 3. AD390-16-Bit Bus Interface
AD390
'I·BIT , - - - - - - - - - - - - - - - - - '
DATA
aus L _ _ _ _ _ _--,
8-8IT ~-------t
DATA
o
BUS
f---L-......
L ______...L__- ,__--,
0:.0 AD390
HIGHORDEft
ADDRESS BITS
SYSWii
A3 A2 A1
X
X
X
X
X
X
0
X
0
0
X
o
o
x
0
AO OPERATION
0 SELECTDAC1
X SELECTDAC2
X SELECTDAC3
X SELECTDAC4
0 SELECTAU.DACS
A4 A3 A2 At
AO
OPERATION
o
SELECTDAC1LOWBYTE
o
1
o
1
o
SELECTDACZLOWBYTE
SELECTDAC2H1GHBYTE
t SElECTDAC1H1GHBYTE
M.A5:SEETEXT
SElECTDAC3LOWSYTE
SELECTDAC3H1GHBYT£
SB.ECTDAC4LDWBYTl
1 SB.ECTDAC4H1GHBYTE
ALL GATES: 114 74lS3Z
Figure 4. Alternate 16-Bit Bus Interface
A6.A5:SEETEXT
Figure 6. AD390-8-Bit Bus Interface Connections
DIGITAL-TO-ANALOG CONVERTERS 2-17
•
Analog Circuit Details
REFERENCE CONNECTIONS
The AD390 is equipped with a precision internal reference
voltage of 10.00 volts, trimmed to within ± 3 millivolts. This
reference is available for external use and can typically supply
up to 3.5 milliamps of output current. In normal operation, this
reference is connected to pin 17 (REF IN), which establishes
the ± 10 volt output scale. The internal reference is sufficiently
accurate for most applications, however, if a master system
reference is available, or if a range other than ± 10V (± 10.24V,
for example) is desired, an external reference may be used. It is
recommended that the reference used with the AD390 be at
least 5 volts and at most 11 volts to preserve specified linearity.
Digital Input Code
0000 0000
0100 0000
1000 0000
10000000
1100 0000
1111 1111
0000
0000
0000
0001
0000
1111
Analog Output Voltage
-IO.OOOV
-5.000V
O.OOOV
+ 4. 88mV
+5.000V
+9.9951V
- Full Scale
-1I2Scale
Zero
+ILSB
+ 112 Scale
+ Full Scale - ILSB
power ground return impedances, and offsets due to multiple
load currents sharing the same signal ground returns. While the
AD.390 outputs are accurately developed between the output pin
and pin 15 (AGND), delivering these signals to remote IQads
can be a problem. These problems are compounded if a current
booster stage is used, or if multiple AD390 packages are used.
Figure 8 illustrates the parasitic impedances which influence
output accuracy.
A....
"A"
....
Ru
Ru
I.
rr=
z..
1&
A....
"B"
Zoo
TO POWER
GROUND
A1-A3: OPTIONAL CURRENT aooSTIRS
fIw,-Rvn: WlFUNG RESISTANCES
Zu.. loa: SIGNAL GROUND RETURN IMPEDANCE
lpg: POWER GROUND RETURN NPEDANCES
Table III. AD390 Analog Output vs. Digital Input (± V
Scale)
Figure 8. Grounding Errors in Mu/tip/e-AD390 Systems
GROUNDING RULES
The AD390 includes two ground connections in order to minimize
system accuracy degradation arising from grounding errors. The
two ground pins are designated DGND (pin 13) and AGND
(pin 15). The DGND pin is the return for the supply currents
of the AD390, and serves as the reference point for the digital
input thresholds. Thus DGND should be connected to the same
ground as the digital circuitry which drives the AD390.
An output buffer configured as a subttactor as shown in Figure
9 can greatly reduce these errors. First, the effects of voltage
drops in wiring resistances is eliminated by sensing the voltage
directly at the load with R4. The voltage drops caused by currents
flowing through ZGA are eliminated by sensing the remote ground
directly with R3. Resistors Rl through R4 should be well matched
in order to achieve maximum rejection of the voltage appearing
across ZGA' Resistors matched to within one percent (including
the effects of RW2 and Rw3) will reduce ground interaction
errors by a factor of 100.
Pin IS, AGND, is the high quality analog ground connection.
This pin should serve as the reference point for all analog circuitry
which follows the AD390. It is recommended that any analog
signal path carrying significant currents have its own return
connection to pin IS as shown in Figure 7.
V~I----
_ _---..,
TO POWER
GROUND
,I@I'=::o.._ _ TOOg,:U~
L...-----::;;r.-....J
TOPOWERGROUND
Figure 7. Recommended Ground Connection~
Several complications arise in practical systems, particularly if
the load is referred to a remote ground. These complications
include dc gain errors due to wiring resistance between DAC
and load, noise due to currents from other circuits flowing in
2-18 DIG/TAL-TO-ANALOG CONVERTERS
R1-R4 MATCH TO 1% OR BEnER
Figure 9. Use of Subtractor Amplifier to Preserve Accuracy
POWER SUPPLY DECOUPLING
The power supplies used with the AD390 should be well filtered
and regulated. Local supply decoupling consisting of a lOjl.F
tantalum capacitor in parallel with O.ljl.F ceramic is suggested.
The decoupling capacitors should be connected between the
AD390 supply pins and the load ground (ideally the AGND
pin). If an output booster is used, its supplies should also be
decoupled to the load ground.
AD390
OPERATION FROM :t12 VOLT SUPPLIES
OUTPUT CURRENT BOOSTING
The AD390 may be used with ± 12 volt ± 5% power supplies if
certain conditions are met. The most important limitation is the
output swing available from the output op amps. These amplifiers
are capable of swinging only as far as 3 volts from either supply.
Thus, the normal ± 10 volt output range cannot be used. Changing
the output scale is accomplished by changing the reference
voltage. With a supply of ± 11.4 volts (5% less than ± 12V), the
output range is restricted to a maximum ± 8.4V swing. It may
be useful to scale the output at ±8.192 volts (yielding a scale
factor of 4 millivolts per LSB). The required 8.192V reference
can be derived from a precision, low TC divider from the
internal + 10.OOOV reference. The only restriction is that the
total load resistance presented to the + 10.OOOV reference
output must be at least 10kO for - 55°C to + 125°C temperature
range 12 volt applications. Figure 10 shows a suggested circuit
to set up a ±8.192V output range. Multiple AD390 units
can share the same resistive divider-generated reference since
the REF IN terminal is very high impedance.
The output amplifiers used in the AD390 are capable of
supplying a ± 10 volt swing into a resistive load of 2kO or
greater. Stability is guaranteed for load capacitance up to
300pF. Larger load capacitance may cause severe overshoot
and possible oscillation. The settling characteristic of the
AD390 output amplifier is shown in Figure 12.
II
a. All Bits OFF-to-ON
16 REFOUT
AI
1.l52k
AD'"
ANALOG
OUTPUTS
Fl1, R3: 1% METAL FILM OR BETTER
R2: LOW TC MULn·TURN TRIMPOT
TOPOWEA
GROUND
Figure 10. Connections for ±B.192V Full Scale
(Recommended for ± 12V Power Supplies)
b. All Bits ON-to-OFF
IMPROVING FULL-SCALE STABILITY
In large systems using multiple AD390s, it may be desirable
for all devices to share a common reference. While it is possible
to use the reference output for one device to provide a reference
for all devices, use of an external precision reference can
greatly improve system accuracy and temperature stability.
The external reference should be at least + SV and at most
+ llV to preserve DAC linearity.
The AD2710 is a suitable reference source for such systems.
It features a guaranteed maximum temperature coefficient of
± IppmI"C, compared with the 10 to 20ppmfC drift of the
AD390 internal reference. The combination of the AD2710LN
and AD390KD shown in Figure II will yield a multiple-DAC
system with maximum full-scale drift of ± 6ppmfC and
excellent tracking .
• ,SV
+15V
Figure 12. AD390 Settling Characteristic
In many applications, including automatic test equipment,
the load presented to the AD390 may be less than 2k!l or
include large capacitance. In such cases, it is advisable to use
a buffer amplifier capable of delivering rated output to the
most severe load anticipated. The AD382, for example, can
supply ± 10V into a 2000 load and the AD3554 is suitable
for load resistances down to 1000· In applications where
errors due to output boosting must be minimized, the composite
amplifier shown in Figure 13 provides excellent de stability
as well as lOOmA output drive capability.
-15V
A,
c,
OUTPUTS
TOPOWfR
GROUND
Figure 11. Low Drift AD390 Configuration
TOPOW£R
GROUND
Figure 13. Composite Amplifier for Increased Output Drive
DIGITAL-TO-ANALOG CONVERTERS 2-19
APPLICATIONS
The functional density of the AD390 permits complex analog
functions to be produced under digital control, where board
space requirements would otherwise be prohibitive. Multiple-output plotters, multi-channel displays and complex waveform
generation and multiple programmable voltage sources can all
be implemented with the AD390 in a fraction of the space which
would be needed if separate DACs were used.
PROGRAMMABLE WINDOW COMPARATOR
The AD390 can be used to perform limit testing of responses to
digitally-controlled input signals. For example, two DACs may
be used to generate software-controlled t~t conditions for a
component or circuit. The response to these input conditions
can either be completely converted from analog to digital or
simply tested against high and low limits generated by the two
remaining DACs in the AD390.
In the circuit of Figure 14 two AD311 voltage comparators are
used with an AD390 to test the output of a S volt power supply
regulator. The AD390 V OUT1 output (through an appropriate
current booster) drives the input to the regulator to simulate
variations in input voltage. The output of the regulator is applied
to comparators 1 and 2, with their outputs wire-ORed with
LED indicators as shown. The teSt limits for each comparator
are programmed by the AD390 V OUT2 and VOUT3 outputs.
When the output of the device under test is within the limits,
both comparators are off and D 1 lights. If the output is above
or below the limits, either D4 or DS lights.
.
+1SV
USING THE AD390 FOR ANALOG-TO-DIGITAL CONVERSION
Many ·systems require both analog output and analog input
capability. While complete integrated circuit analog-to-digital
converters (such as the AD574A) are readily available, the AD390
can be used as the precision analog section of an ADC if some
extemallogic is available. Several types of analog-to-digital
converters can be built with a DAC, comparator, and control
logic, including staircase, tracking, and successive-approximation
types. In systems which include a microprocessor, only a comparator must be added to the AD390 to accomplish the APC
function since the processor can perform the required digital
operations under software control. A suitable circuit is shown in
Figure IS. The AD311 comparator compares the unknown
input voltage to one of the AD390 outputs for the analog-to-digital
conversion, while the other three outputs are used as normal
DACs. The diode clamp shown limits the voltage swing at the
comparator input and improves conversion speed. With careful
layout, a new comparison can be performed in less than 10
microseconds, resulting in 12-bit successive approximation conversion in under 120 microseconds. The benefit of the AD390
in this application is that one ADC and three DACs can be
implemented with only two IC packages (the AD390 and the comparator).
ANALOG
INPUT
-1DVTO +1OV
+15V
-1&V
+5V
-1SV
CONTROL
"'" = AIN > VQUTI
"0" = AIN < Voun
lOGIC
Oft
.p
Figure 15. Using One AD390 Output for AID Conversion
A1: DAC OUTPUT BOOSTER
A2, All AD311 COMPARATOR lOR EQUNALENTI
Figure 14. Programmable WindowComparatorUsedln
Power Supply Testing
2-20 DIGITAL-TO-ANALOG CONVERTERS
11IIIIIIII ANALOG
WDEVICES
FEATURES
Data Readback Capability
Four Complete, Voltage Output, 12-Bit DACs in One
32-Pin Hermetic Package
Fast Bus Access: 40ns max, Tmin-Trnax
Asynchronous Reset to Zero Volts
Minimum of Two TTL Load Drive (Readback Mode)
Double-Buffered Data Latches
Monotonicity Guaranteed T min-T max
Linearity Error ± 1/2LSB
Low Digital-to-Analog Feedthrough, 2nV·sec typ
Factory Trimmed Gain and Offset
Low Cost
PRODUCT DESCRIPTION
The AD392 is a quad 12-bit, high speed, voltage output digital-toanalog converter with readback in a 32-pin hermetically sealed
package. The design is based on a custom IC interface to complete
12-bit DAC chips which reduces chip count and provides high
reliability. The AD392 is ideal for systems requiring digital
control of many analog voltages and for the monitoring of these
analog voltages especially where board space is a premium. Such
applications include ATE, robotics, process controllers and
precision filters.
Featuring maximum access time of 40ns, the AD392 is capable
of interfacing to the fastest of microprocessors. The read back
capability provides a diagnostic check between the data sent
from the microprocessor and the actual data received and transferred to the DAC. When RESET is low, all four DACs are
simultaneously set to (bipolar) zero providing a known starting
point.
Complete Quad 12-Bit
OfAConverter with Readback
AD392 I
AD392 FUNCTIONAL BLOCK DIAGRAM
E
WR iffi
2ND UP
+5V
DGND
PRODUCT HIGHLIGHTS
1. The AD392 is packaged in a 32-pin DIP and is a complete
solution to space constraint multiple DAC applications.
2. Readback capability provides system monitor of DAC output
useful in ATE, robotics or any closed-loop system.
3. Fast bus access time of 40ns maximum allows for fast system
updating compatible with high speed microprocessing.
4. Simultaneous reset to zero volts output is extremely useful
for system calibration or simply when all DAC outputs must
initially start at zero volts.
5. Readback drive capability of two TTL loads virtually eliminates
the need to buffer.
The AD392 is laser-trimmed to ± 1I2LSB integral linearity and
± lLSB max differential linearity at + 25°C. Monotonicity is
guaranteed over the full operating temperature range. The high
initial accuracy and stability over temperature are made possible
by the use of precision thin-film resistors.
6. Each DAC is independently addressable, providing a versatile
control architecture for simple interface to microprocessors.
The individual DAC registers are accessed by the address lines
AO and Al and control lines CS and 2ND UP. These control
signals permit the registers of the four DACs to be loaded
sequentially and the outputs to be simultaneously updated.
8. Low digital-to-analog feedthrough (2nY·sec typ) is maintained
to assure DAC accuracy.
7. Monolithic DAC chips provide excellent linearity and guaranteed monotonicity over the full operating temperature range.
The AD392 outputs are calibrated for a ± lOY output range
with positive true offset binary input coding.
The AD392 is packaged in a 32-lead metal platform DIP and is
hermetically sealed. The AD392 is specified for operation over
the 0 to + 70°C temperature range.
DIGITAL-TO-ANALOG CONVERTERS 2-21
SPECIFICATIONS
(Vee
= +15Y, Va = -15V,VIII = +5Y, TA +25"&, unless othaIwise spacified)
ADm
Parameter
Min
DATA INPUTS (Pills 1-13, 16-18, 30-32)
TTL Compatible
Input Voltage
Bit ON (Logic "I ")
Bit OFF (Logic "0")
Input Current
+2S"C
TmlntoT..-
Mas
UDits
Comments
+2.0
DGND
+VDD
+0.8
V
V
VDD = S.2SV
VDD = 4.7SV
-2
-20
+2
+20
!LA
!LA
VIN = VDDorGND
VIN = VDDorGND
12
Bits
+0.4
VDD
V
V
Typ
RESOLUTION
OUTPUT
Bidirectional Outputs (Pills 2-13)
VoltsgeOutput Low (!oL = +4.0rnA)
VoltageOutputHigh(loH = -4.0mA)
Tristate Output Leakage
TmlntoT."..
DACOutputVoltageRange
Current Range
Short Circuit Current
STATIC ACCURACY
Gain Error
Offset
Bipolar Zero
Integral Linesrity Error
Differential Linesrity Error
0
+2.4
-20
-S
-0.1
-0.05
TEMPERATURE PERFORMANCE
Gain Drift
Offset Drift
Integral Linesrity Error
Tmin to T""",
Differential Linearity Error
+S
+40
+0.1
+O.OS
-O.S
-I
+0.5
+1
%ofFSR
%ofFSR
%ofFSR
LSB
LSB
-25
-25
±20
±20
+25
+25
ppm FSRrC
ppmFSRrC
See Note I
-1
LSB
+1
-Monotonicity Guaranteed Over Full Temperature Range-
I
10
2
0.1
±13.5
+4.5
26
62
7.2
1356
Ioc
lEE
IDD
Power Dissipation
POWER SUPPLY GAIN SENSITIVITY
+Voc, VDD, -VEE
TEMPERATURE RANGE
Operating (Full Specifications)
Storage
!LA
V
rnA
rnA
±O.OS
±0.025
±0.02S
±0.25
±0.5
ACANALOGPERFORMANCE
SettlingTime(to ± 1/2LSB)
Change All Register Inputs
From + 5V toOV/OV to +5V
For LSB Change
Slew
Digital-ta-Analog Glitch Impulse
Crosstalk
POWER REQUIREMENTS
+Voc, -VEE
+VDD
Current (All Digital Inputs DGND or
+VDDONLY, No Load)
+20
±IO
0
-65
4
2
II.S
See Note 2
I>S
V/j>S
nV·sec
LSB
See Note 3
See Note 4
±16.5
+5.5
V
V
44
82
13
1955
rnA
rnA
rnA
mW
See Note 5
0.002
O/OFSI%Vs
See Note 6
+70
+150
"C
"C
NOTES
IVOUT =
Voo or DGND.
_
Referenced to trailing rising edge of WR.
3Digital·to-Analog Glitch Impulse: This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the
inputs change state. Specified as the area of the glitch in nV-sees.
"Crosstalk is defmed as the change in anyone output as a result of any other output being driven from -lOV to + lOV into a 21d1load.
'ale approximately 100CIW.
6+VCCJ +VODJ -VEE are ±100/0.
2
SpecifIcations subject to change without notice.
2-22 DIGITAL-TO-ANALOG CONVERTERS
AD392
ABSOLUTE MAXIMUM RATINGS·
+ Vee to AGND (Any DAC)
-VEIl to AGND (Any DAC)
+ Vnn to DGND . . . . .
Digital Inputs to DGND
(Pins 1-13, 16-18, 30-32)
Analog Outputs (Pins 20, 22, 26, 28)
Short Circuit Duration
(+Vc.c, -VEllorAGND)
Storage Temperature
PIN CONFIGURATION
. . . 0 to + 18V
. . . 0 to -18V
-O.3V to +7V
A1
cs
RESET
-0.3V to +7V
AGN04
Indefinite
VOUT4
-65°C to + 150°C
Voun
•
AGND3
-VEE
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a sress rating only and functional
operation at or above this specification is not implied. Exposure to above
maximum rating conditions for extended periods may affect device reliability.
+Vcc
Dsa
AGND2
DB.
Voun
AGND1
OB10
MSB DB11
Voun
+Voo
eAOE
2ND UP
DGND
Wti
AD
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
ORDERING GUIDE
Model
Temperature
Range
Gain Error
Linearity Error
Tmin-Tmax
Package
Option·
AD392JV
Oto + 70°C
±4LSB
±ILSB
DH-32A
*See Section 14 for package outline information.
DIGITAL-TO-ANALOG CONVERTERS 2-23
Theoll. of Operation
The AD392 is a quad I2-bit digital-to-analog converter with
readback capability. The analog portion of the AD392 includes
four bipolar process digital-to-analog converters. Each DAC
contains current steering switches and a resistor ladder network
which is laser-wafer trimmed for I2-bit accuracy. A precision
output amplifier for voltage out operation and an internal highly
stable voltage reference are all integrated on a single chip. The
DAC is fixed to run in bipolar, 20V span analog output mode as
shown in Table I.
AaaIogOu_
DataIDpat
AaaIogOulpUtVoltap
{:n
+9.99SIV
+ Full Scale -ILSB
+I·(VREPIN)
g:}
+S.ooov
+ 112 Scale
0001
+I'(VREFIN)
{~}
+4.88mV
+ILSB
0000
0000
+I·(VREPIN
){~}
+o.ooov
Zero
1II1
1111
-I·(VREPIN)
{~}
-4.88mV
-ILSB
1111
1111
1II1
+I·(VREPIN)
1100
0000
0000
1000
0000
1000
0111
0100
0000
0000
-I'(VREFIN)
g:}
-s.ooov
-II2Scale
0000
0000
0000
-1'(VREfIN)
{~}
-IO.OOOV
-FullScale
Table I. A0392 BipolarCode Table.
The digital portion of the AD392 includes the readback function,
control logic and registers all integrated on a custom IC. Data
can be latched into anyone of the first rank registers by selecting
the correct combination of address lines (AO and AI) and CS.
The second rank registers are controlled by the 2ND UP control
line. Use of the 2ND UP line enables the DACs to be updated
simultaneously. The digital word can be readback from the
second rank registers by asserting the cOrrect address lines,
2ND UP and RD command. The RD and WR commands
control the bidirectional 110 port. The AD392 features a RESET
command for simultaneous update of all DACs to 0 volts out.
This is useful for easy system calibration.
+15V
-15V
CASE
DATA AND CONTROL SIGNAL FORMAT
The double buffered registers of the AD392 are addressed by
the CS, Al and AO lines. Each rank of registers is 12 bits wide
and is presented in a straight offset binary notation. The first
rank of registers are loaded sequentially, with valid CS, AI, AO
on the trailing rising edge of WR. The second rank of registers,
on.the other hand, are loaded simultaneously with the data
wbich is in their corresponding first rank registers, with a valid
CS and positive pulse of the 2ND UP command. (Note: All
second rank registers can be made transpare!lt by tieing the
2ND UP line to a Logic "1".) The data loaded into the second
rank registers represents the actual digital code which is on the
input of the individual DACs. This data can be read back through
the data port, with valid CS, Al and AO, by taking the RD line
to a Logic "0". The AD392 also features an asyncronous reset
to zero volts for all four DACs by applying a negative pulse to
the RESET line. Executing a reset replaces the contents of both
ranks of registers with the bipolar zero code (MSB equals Logic
"1", all other bits equal Logic "0".)
cs
AI
All
WJl
iii iiSET
1
X
X
X
X
I
X
Chip ReadlWrite Disable
X
X
X
X
X
0
X
MSB. Go to I, All
Other. Go to 0
0
X
X
X
X
I
I
All 2ND Rank
Latches Transpsrent
0
X
X
X
X
I
0
All 2ND Rank
Latches Latched
0
0
0
I
0
I
X
Read Back DACI
2ND Rank
0
0
0
U
I
I
X
Write to 1ST Rank
DACI
I
I
0
I
X
Read Back DAC2
2ND Rank
I
X
Write to 1ST Rank
DAC2
0
0
lNDUp Output
0
0
I
U
I
0
I
0
I
0
I
X
Read Back DAC3
2ND Rank
0
I
0
U
I
I
X
Write to 1ST Rank
IDAC3
0
I
I
I
0
I
X
0
I
I
ru
Read BackDAC4
2ND Rank
I
I
X
Write to 1ST Rank
InAC'A
Symbols: X = Don'tCsre
I =
J..osic Rich
o = J..osic Low
U
= Positi.., TroiliDs Edae TriaFed
Table II. AD392 Truth Table
Wii iiD
2ND UP
+5V
DGND
Figure 1. AD392 Block Diagram
2-24
DIGITAL~TO-ANALOG
CONVERTERS
AD392
TIMING
The timing diagrams (Figures 2 and 3) illustrate the precise
relationship between control signals, address signals and the
data. The address lines (CS, AI, AO) as well as the data (OO-DB)
must be valid a minimum of ISns before a WR is executed, and
the data must remain valid a minimum of ISns after the WR
has been executed. Minimum pulse width for the WR, 2ND UP
and RESET commands is ISns. Similarly, the address lines (CS,
AI, AO) must be valid a minimum of ISns before a RD is executed.
Data will be valid a maximum of 40ns after RD goes low. (Note:
This is a MAXIMUM and, therefore, data should be off the bus
just before RD goes low to avoid bus contention problems, i.e.,
damage to the device, data bus oscillations which may result in
latching erroneous data in the registers.) Data will be off the
bus a maximum of 30ns after RD goes high. (Note: This is a
MAXIMUM and, therefore, the data read should be completed
just before RD goes high to avoid reading erroneous data.)
DAC settling time is measured from the trailing rising edge of
the WR signal.
Symbol
Parameter
tos
tw
tsu
tHD
tRS
tVR
tDOS
Device Select
WritelUpdatelReset Pulse Width
Data Setup Time
Dsta Hold Time
Reset Valid for Read
Read Valid After Write
Device De-Se1ect (from Read Dsta to Tristate
Bus Access On Time
Bus Access Off Time
Minimum Latch Delay after Write!
Minimum Latch Delay after Next Write!
2ND Rank Transparent for Valid Read
2ND Rank Transparent to DAC Port Outputs
DataRiae, Fall Times
[BAOn
tBAOff
t2L1
t2l'>
t2TR
t2TD
tR"tp
Min M"" Vail
IS
os
IS
os
IS
os
IS
30
ns
ns
ns
ns
ns
ns
40
5
os
ns
ns
ns
ns
3S
30
40
40
10
S
2S
0
NOTES
Timing between pulses measured at SO% points.
Bus access on time measured from SO% point of read. going low to active bigb (2.4)
or active low (0.4)(... Figura 4 and 5).
Bus access off time measured from 50% point of read going higb to point at whicb voltage
trails away from. active bigh or low under sWldard tristate load conditions (see Figure 6).
Table III. AC Charactertics: VDD = 5.0V ± 10%;
OsTAs+70'C; V1N=VDDorDGND
on
~
r-r-r--
,IT
ACTIVE
+l;R
IrrFj--
V
I.
3.
•
RESET--------------___________________________________
-DATA IS IN BOTH
-j-"-
DATA
OUT
T
2.
50
40
AND 2P4D RANKS
··DATA 8 IS IN 2N1> RANK, DATA C IS IN 1ST RANK
Figure 4. Typical Bus Access Off Time (tSA Off)
Figure 2. AD392 WritelRead Cycle Timing Diagram
-
I
f
1
-I
TRISTATE
".ON
~
0
I
>
I
t-
I-"~-l
AESETCODE
=='-___________
FORCED
I
~c--
TRISTATE
TRISTATE -
DATAIN
lliO
BUSI --------==~----------....:.----_==:::_----------________.;.T.::::'ST:.:.A:.:T.:.'______....,____-:-____
~~
-f.:1-
OUT
II
f
-1 ... 0 "1-'::
DATA
1 I
tSA10N
I.
-I
2.
3.
ACTIve
HIGH
40
I
50
Figure 5. Typical Bus Access On Tim" (tSA On)
+5V
Figure 3. AD392 Read Cycle Timing Diagram
(HP6216A
VOLTAGE SUPPLY)
Rl
TRISTATE
O~PUTo-~~~--~--~__t
TO SCOPE INPUT
TEKTRONIX
1A26 PLUG-IN
02
P6106A PROBES
Rl = 1.35kH :t1%, 1/4W
R2 = 1.2SkH ±1%,1/4W
C1 '" 100pF, FOR tBA ON
'" 15pF, FOR t8A OFF
ALL DIODES 1N916
OR EQUIVALENT
1704A MAINFRAME
7892 TIME BASE
OR EQUIVALENT
[)tGITAl
GROUND
Figure 6. Standard Tristate Load Circuit
DIGITAL-TO-ANALOG CONVERTERS 2-25
I
SEITLING TIME
The output amplifiers used in the AD392 are capable of supplying
a ± 10 volt swing into a resistive load of 2Jdl or greater. The
settling characteristics of the output amplifier is shown in
Figure 7. The test setup used to determine settling time is shown
in Figure 8.
the DAC bit input currents are sourced from the + VDD supply
and should return by the shortest possible path and not down
the analog return (see Figure 9 for details.).
ADDRESS BUS
POWER SUPPLY DECOUPLING
The power supplies used with the AD392 should be well filtered
and regulated. Internally the + Va:; and - VEE supplies are
independently decoupled about each DAC with O.039 ....F chip
capacitors to their corresponding AGND. Therefore, if the
grounding scheme of Figure 9 is used, it should be sufficient to
place a 4.7....F tantalum electrolytic capacitor across the + Va:;
and - VEE supplies. Decoupling the + VDD supply to DGND
should be done in the same manner, however, using a parallel
combination ofO.047 ....F ceramic and a 4. 7....F tantalum electrolytic
capacitor.
Ii'ilf--+-----
2ND UP
Figure 9. AD392 Recommended Circuit Schematic
CIRCUIT DETAILS
The following two suggestions are intended to aid the user in
the normal operation of the AD392:
1. Bus Termination: The bidirectional tristateable port of the
Figurel. AD392 VoSettling20VStep
PULSEGEN
HP8D128 •. _ _ _ _- - - ,
ADDRESS
-VSETTUNG
DECODE
......,.
PULSE GEN.
}-1-~~~~~~~~~
+!:IV
SUPPLYI
~D UP
TO: TEKTRONIX
WR
7A13PWO-IN
P610&APROBE
710A MAINFRAME
7892 TIME BASE
0.01% FSR = 'mV (0 ARTIFICIAL SUMMING NODE
FigureB. AD392VoSettlingTimeCircuit
GROUNDING RULES
The AD392 has been designed with four independent DAC
analog grounds and a separate digital ground return pin. The
analog ground pins are not only the reference points for the
individual voltage outputs, they also serve as the return path for
the switched DAC bit input currents. These rapidly switching
currents may be as large as several milliamps for each DAC
and, therefore, should be returned to a low impedance node to
avoid code dependent linearity errors, digital-to-analog feedthrough and crosstalk between DAC outputs. It is recommended
that all four DAC analog grounds and the digital ground be tied
together at the package for optimal performance. + Va:; and
- VBE grounds can be tied together back at the system supply
and brought up to the AD392 together, whereas the + VDD
ground is tied to the other grounds at the package and not back
at the system supply. This conf1gll1"lltion is recommended because
2-26 DIGITAL- TO-ANALOG CONVERTERS
AD392 (as well as the digital inputs) should not be allowed
to "float". These functions are provided by a custom CMOS
integrated circuit having an input control circuit which is
essentially the common gate contact of a pair of P and N
channel MOS devices connected in series between the + VDD
and DGND supply lines. An unterminated bus allows the
gate potential to float to a point where both channels are
partially "on" creating an ohmic path across the supply.
Therefore, to avoid excessive supply current drain and possible
reflections of the digital signal the bus should be terminated
in its characteristic impedance to DGND.
2. Digital Signal Integrity and the RESET lille: The AD392
has been designed to respond to extremely fast data rates and
as a result must operate with a "clean" bus to ensure that
valid data is being transmitted (i.e., transients on the bus
that cross thresholds with sufficient duration, Sns-IOns, may
cause data to become invalid just before a WR command). If
the RESET line is not connected to this "clean" bus (i.e.,
connected to some sort of power on reset circuitry), then it is
recommended that this line be decoupled with a minimum of
IOOOpf capacitor to avoid an unwanted asynchronous zero
volt reset on all four DACs. If this signal is not used, it
should be tied to + VDD at the package.
p.P-Compatible Multiplying
Quad 12-Bit D/A Converters
AD3941AD395 I
rIIIANALOG
WDEVICES
FEATURES
Four Complete 12-Bit CMOS DACs with Buffer
Registers
Linearity Error ±1/2LSB Tmin-Tmax (AD394, AD395K,T)
Factory-Trimmed Gain and Offset
Precision Output Amplifiers for V OUT
Full Four Quadrant Multiplication per DAC
Monotonicity Guaranteed Over Full Temperature
Range
Fast Settling: 15",s Max to ± 1/2LSB
Available to MIL-STD-883 (See ADI Military Catalog)
AD394/AD395 FUNCTIONAL BLOCK DIAGRAMS
AD394
2.
v.,"., •
VOUT2
AGND
MSB
81
1
PRODUCT DESCRIPTION
The AD394 and AD395 contain four 12-bit, high-speed, low
power, voltage output multiplying digital-to-analog converters in
a compact 28-pin hybrid package. The design is based on a
proprietary latched 12-bit CMOS DAC chip which reduces chip
count and provides high reliability. The AD394 and AD395
both are ideal for systems requiring digital control of many
analog voltages where board space is at a premium and low
power consumption a necessity. Such applications include automatic test equipment, process controllers, and vector stroke
displays.
Both the AD394 and the AD395 are laser-trimmed to ± 1I2LSB
max differential and integral linearity (AD394, AD395K,T) and
full scale accuracy of ± 0.05 percent at 25°C. The high initial
accuracy is made possible by the use of precision laser trimmed
thin-film scaling resistors.
The individual DAC registers are accessed by the CSI through
CS4 control pins. These control signals allow any combination
of the DAC select matrix to occur (see Table III). Once selected,
the DAC is loaded with a single 12-bit wide word. The 12-bit
parallel digital input interfaces to most 12- and 16-bit bus
systems.
The AD394 outputs (V REFIN = + lOY) provide a ± lOY bipolar
output range with positive-true offset binary input coding. The
AD395 outputs (V REFIN = -lOY) provide a OV to + lOY unipolar
output range with straight binary input coding.
Both the AD394 and the AD395 are packaged in a 28-lead
ceramic package and are available for operation over the 0 to
+ 70°C and - 55°C to + 125°C temperature range.
PRODUCT HIGHLIGHTS
1. The AD394, AD39S offer a dramatic reduction in printed
circuit board space in systems using multiple DACs.
2. The use of CMOS DACs provides low power consumption.
3. Each DAC is independently addressable, providing a versatile
control architecture for simple interface to microprocessors.
All latch enable signals are level-triggered.
4. The output voltage is trimmed to a full scale accuracy of
±O.OS%. Settling time to ± 1I2LSB is 15 microseconds
maximum.
5. Maximum gain TC of Sppm/°C is achievable by both the
AD394 and the AD39S.
6. The monolithic CMOS DAC chips provide excellent linearity
and guaranteed monotonicity over the full operating temperature range.
7. The 28-pin double-width hybrid package provides extremely
high functional density.
8. Two or four quadrant multiplication can be achieved simply
by applying the appropriate input voltage signal to the selected
DAC's reference (VREFIN).
9. Both the AD394S,TD and AD39SS,TD feature guaranteed
accuracy and linearity over the - 55°C to + 125°C temperature
range.
DIGITAL- TO-ANALOG CONVERTERS 2-27
SPECIFICATIONS
tTA =
+ m , VREFIN
Model
MIN
DATA INPUTS (Pins 1_16)2
TTL or 5 Volt CMOS Compatible
Input Voltase
Bit ON (Logic "I")
Bit OFF (Logic "0")
Input Current
TYP
MAX
±4
+5.5
+0.8
±40
+2.4
0
REFERENCE INPUTS
Input Resistance
Voltage Range
MAX
UNITS
+5.5
+0.8
±40
V
V
12
Bits
5
±0.05
±0.025
±0.025
± 114
± 112
±O.I
±0.05
±0.025
±0.012
±0.012
± 118
±1/4
±3/4
±3/4
±10
±10
±1I2
± 112
%ofFSR4
%ofFSR
%ofFSR
LSB
LSB
±5
±5
ppmFSRf'C
ppmFSRf'C
±0.05
±0.025
±3/4
± 114
± 112
± li2
MONOTONICITY GUARANTEED OVER FULL TEMPERATURE RANGE
25
+11
5
-11
LSB
25
+11
k!l
V
JJ'l
10
15
10
15
10
15
10
15
..s
5
See Figure I
250
5
See Figure I
250
mVp-p
0.1
2.0
0.1
2.0
LSB
mVp-p
± 16.5
± 13.5
0
-55
-65
5
-11
,.A
V
V
mA
±VREFIN
OVto -(VREFIN )
5
POWER SUPPLY GAIN SENSITIVITY
+Vs
-Vs
TEMPERATURE RANGE
Operating (Full Specifications)J, K
S,T
Storage
±4
±VREFIN
DYNAMIC PERFORMANCE
Settling Time (to ± 112LSB)
V REFIN = + IOV, Change All Digital
Inputsfrom + 5.0VtoOV
V REFIN = Ot05VStep,
All Digital Inputs = OV
Reference Feedtbrough Error"
AD395
AD394
Digital-to-Analog Glitch Impulse'
Crosstalk
Digital Input (Static)8
Reference9
POWERREQUIREMENTS
Supply Voltage Io
Current (All Digital Inputs OV or + 5V)
+Vs
-Vs
Power Dissipation
+2.4
0
OVto -(VREFIN)
STATIC ACCURACY
Gain Error
Offset
Bipolar Zero (AD394)
Integral Linearity Error'
Differential Linearity Error
TEMPERATURE PERFORMANCE
Gain Drift
Offset Drift
Integral Linearity Error'
Tmin to Tmax
Differential Linearity Error
AD394KDrrD1
AD39SKDrrD
MIN
TYP
12
RESOLUTION
OUTPUT
Voltage Range'
AD394
AD395
Current
--
= lOY, Vs - + 15V unless othlllWise specified)
AD394JDISD 1
AD39SJDISD
± 13.5
nV-sec
±16.5
V
20
18
570
22
28
750
20
18
570
22
28
750.
mA
mA
mW
0.002
0.0025
0.006
0.006
0.002
0.0025
0.006
0.006
%FSI%
%FSI%
+70
+125
+150
"C
+70
+125
+150
0
-55
-65
NOTES
'AD394and AD395 S and T grades are available to MIL-STD-883, Method 5008, Cia.. B. See Analog Devices MiIi_Catalog (1987) for
proper part number and detail speciflCltion.
2Timing specifications appear in Table IV and Figure S.
lCode tables and graphs appearon Theory ofOpcration page.
4FSRmeans FuU Scale Range and is equal to 20V for a ± lOV bipolar range andlOV for 010 lOV unipolar range.
5Integral nonlinearity isa measure of the maximum deviation from a straight line passing thougb the endpoints of the DAC transfer function.
6ForAD39S(unipoJar), DAC rqilter loaded. wirh 0000 0000 0000, VRBPIN = 20VP"'P, IOkHzsinewave. ForAD394 (bipolar), VRBFlN = 20Vp-p, 60 and 400Hz.
7This is a measure of the amount ofcharge injected from the diJj.tal inputs to the analog outputs when the inputs change state. It is usuallyspecifled
as the area oftbeglitchionVsandis measured witbVRBPIN = AGND.
'Digital crosstalk is defmed as the change inanyoneoutput's steady state value as a result of any other output beiogdriven from. VOUTMIN to VO UTMAX
into a 2Idlloadby means ofvaryiog the digital input code.
\
9Referencecrosstalkis defmed as the change in any one output as a result of any other output being driven from VOUTMIN to VouTMAx@IOkHz
into a2kU load bymeansofvaryins the amplitude .fthe reference sipaI.
U'TbeAD394and theAD395 can beuaed with supplyvoltqeaaalow .. ± 11.4V, Figure 10.
Specifications subject tochaoge without notice.
2-28 OIGITAL-TO-ANALOG CONVERTERS
'C
"C
AD394/AD395
ABSOLUTE MAXIMUM RATINGS·
+Vsto DGND . . . . . . • . . . .
-VstoDGND • . . . • . . . . . .
Digital Inputs (Pins 1-16) to DGND
VIUlF1N to DGND
AGND to DGNO . . . . . . . • . .
-O.3V to + 17V
+O.3V to -17V
-O.3V to +7V
±2SV
. • . . . ±O.6V
Analog Outputs (pins 18,21, 24, 27)
. . . . . • . . . . . . . . Indefinite Short to AGND or DGND
Momentary Short to ± Vs
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
g
~~DEVICE
MIL-STD-883
The rigors of the military/aerospace environment, temperature
extremes, humidity, mechanical stress, etc., demand the utmost
in electronic circuits. The AD394, AD395, with the inherent
reliability of integrated circuit construction, were designed with
these applications in mind. The hermetically-sealed, low profile
DIP package takes up a fraction of the space required by equivalent
modular designs and protect the chips from hazardous environments. To further insure reliability, the AD394, AD395 are
both fully compliant to MIL-STD-883 Class B, Method 5008.
Consult Analog Devices Military Catalog for proper ordering
part number and detail specification.
PIN CONFIGURATION
Figure 1. AD394 Feedthrough VREFIN = 60Hz (top photo) and
400Hz (bottom photo) Sinewave. Digital code is set at 1000
0000000.
SCALE: Reference Input 5VIDIV (Thin Trace)
Feedthrough Output 5m V'DIV
TIME: TopPhoto5ms:DIV
Bottom Photo 500f1,s/DIV
ORDERING GUIDE
Model
Temperature
Range
Gain Error
AD394JD
AD395JD
AD394KD
AD395KD
AD394SD
AD39SSD
AD394TD
AD39STD
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
- 55°C to + 125°C
- 55°C to + 125°C
- 55°C to + 125°C
- 55°C to + 125°C
±4LSB
±4LSB
±2LSB
±2LSB
±4LSB
±4LSB
±2LSB
±2LSB
Linearity Error
Tmn.-Tmax
±3/4LSB
±3/4LSB
± 1I2LSB
± 1I2LSB
±3/4LSB
±3/4LSB
± 1I2LSB
± 1I2LSB
Package
Option·
DH-28A
DH-28A
DH-28A
DH-28A
DH-28A
DH-28A
DH-28A
DH-28A
·See Section 14 for package outline information.
DIGITAL-TO-ANALOG CONVERTERS 2-29
•
Theory of Operation
The AD394 quad DAC provides four-quadrant multiplication.
It is a hybrid IC comprised of four monolithic 12-bit CMOS
multiplying DACs and eight precision output amplifiers. Each
of the four independent-buffered channels has an independent
reference input capable of accepting a separate de or an ac signal
for multiplying or for function generation applications. The
CMOS DACs act as digitally programmable attenuators when
uaed with a varying input signal or, if used with a fixed dc
reference, the DAC would act as a standard bipolar output
DAC. In addition, each DAC has a 12-bit wide data latch to
buffer the converter when connected to a microprocessor data
bus.
TheAD395 quad DAC provides two-quadrant multiplication
and is comprised of four 12-bit CMOS multiplying DACs and
four precision output amplifiers. The two-quadrant-multiplication
function arises from a straight-binary digital input multiplied by
OFFSET
BINARY
§
~ I
§ § § ~ §
§ Ii ,;8
~
--
a bipolar analog input which resUlts in two-quadrant multiplication. The AD395 can also operate as a standard unipolar DAC
when a fixed de reference is applied to VRBPIN •
MULTIPLYING MODE
The figures below show the transfer function for each model.
The diagrams indicate an area over which many different combinations of the reference input and digital input can result in a
particular analog output voltage. The highlighted transfer line in
each diagram indicates the transfer function if a fIXed reference
is at the input. The digital codes above each dIagram indicate
the mid and endpoints of each function. The relationship between
the reference input (VREFIN) the digital input code and the
analog outpUt is giVeD in Tables I and II below. Note that the
reference input signal sets the slope of the transfer function (and
determines the full scale output at code III . . Ill) while the
digital input selects the horizontal position in each diagram.
§ ~
~
~ §
~
§ ~
§
§
§
lLSB
g
•
,;
~
~
+ FULL SCALE
-
iii
DtGITAL
INPUT
CODES
----- -- -- ------ -H
-FULL SCALE
Vou'=IV~!F",J'(~-11
Figure 2. AD394 as a Four-Quadrant Multiplier of Reference
Input and Digital Input
ANALOG OUTPUT
DATAINPlIT
{=l
U:}
ANALOGOUTPUTVOLTAGEVIW1N '" +IOVOLTS
+9.99SIV
+FULLSCALE-ILSB
+s.ooov
+ 112 SCALE
{2~8}
+4.SlmV
+ILSB
0000
+IO(VREFlN){~}
+o.OOOV
ZEllO
Illl
-lo(VRJ!FlN)
{2~B}
-4.BlmV
-ILSB
1111
1111
1111
+lo(VREFlN)
1100
0000
0000
+loCVRBFIN)
1000
0000
0001
+lo(VRSFIN)
1000
0000
Olll
1Il1
Figure 3. AD395 as a Two-Quadrant Multiplier of Reference
Input and Digital Input
ANALOGOUTPUT
DATA INPUT
0100
0000
0000
-loCVkEFlN)
g:}
-5.000V
-1J2SCALE
0000
0000
0000
-lo(VREFlN)
{'z::}
-IO.OOOV
-FULL SCALE
Table I. AD394 Bipolar Code Table
2-30 DIGITAL- TO-ANALOG CONVERTERS
{=}
ANALOGOUTPUTVOLTAGEVUPIN""
+ lOVOLTS
-9.9976V
- FULL SCALE -ILS8
-S.OOOV
-IJ2SCALB
I III
1II1
1111
-I°(VREF[N)
1000
0000
0000
-loCVREFlN) { : }
0000
0000
0001
-lo(VRBJIIN)
{~}
-2.44mV
-ILS8
0000
0000
0000
-lo(VREFlN)
{~}
o.OOOV
ZERO
Table II. AD395 Unipolar Code Table
Digital Circuit Details - AD3941AD395
DATA AND CONTROL SIGNAL FORMAT
The AD394 and AD395 accept 12-bit parallel data in response
to control signals CSI-CS4. As detailed in Table III, the four
chip select lines are used to address the DAC register of interest.
It is permissible to have more than one chip select active at any
time. If CSI-CS4 are all brought low coincident, all four DAC
outputs will be updated to the value located on the data bus. All
control inputs are level-triggered and may be hard-wired low to
render any register (or group of registers) transparent.
CSl
CS2
CS3
I
1
0
I
I
I
I
0
1
1
1
0
0
0
I
I
I
0
CS4
Symbol
Parameter
T..unto Tmax
Units
les
tDA
tDS
tDH
Chip Select Pulse Width
Data Access Time
DataSet·UpTime
Data Hold Time
380
nsmin
nsmin
nsmin
nsmin
0
210
10
Table IV. AD394, AD395 Timing Specifications
Operation
All DACs Latched
I
I
0
0
Load DAC I From Data Bus
Load DAC 2 From Data Bus
Load DAC 3 From Data Bus
Load DAC 4 From Data Bus
All DACs Simultaneously Loaded
Table III. DAC Select Matrix
NOTES
11'1 = TF = 20ns. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% to 90% of Voo (+6V TVPI
TIMING MEASUREMENT REFERENCE LEVEL IS (V ,H + V,d12
AD394
MODE SELECTION
WRITE MODE
CS LOW, OAe RESPONDS TO
DATA BUS (dbO-dbl11INPUTS
HOLOMOOE
CsHIGH, DATA BUS(dbO-dbl1!.5
LOCKED aUT; DA..0l0LDSLASTDATA
PRESENTWHENCSASSUMED
HIGH STATE.
Figure 5. Timing Diagram
CSi13
AD395
ffi 13
MSB a1
1
I
I
I
I
I 1
B12 12
CS3
15
ffi 14
MSB B1 1
I
I
I
a12 12
CS3
I
I
I
~
15
Figure 4. AD394 (Bipolar) Functional Block Diagram
TIMING
The AD394, AD395 control signal timing is very straightforward.
CSI-CS4 must maintain a minimum pulsewidth of at least 380ns
for a desired operation to occur. When loading data from a bus
into a 12·bit wide data latch, the data must be stable for at least
210ns before returning CS to a high state. When the CS is low,
the data latch is transparent allowing the data at the input to
propagate through to the DAC. Data can change immediately
after the chip select returns high. DAC settling time is measured
from the falling edge of the active chip select.
Figure 6. AD395 (Unipolar) Functional Block Diagram
DIGITAL-TO-ANALOG CONVERTERS 2-31
•
Analog Circuit Details
GROUNDING RULES
The AD394 and AD395 include two ground connection$ in
order to minimize system accuracy degradation arising from
grounding errors. The two ground pins are designated DGND
(pin 17) and AGND (pin 23). The DGND pin is the return for
the supply currents of the AD394, AD395 and serves as the
reference point for the digital input thremolds. Thus DGND
should be connected to the same ground as the circuitry which
drives the digital inputs.
Pin 23, AGND, is the high-quality analog ground connection.
This pin should serve as the reference point for all analog circuitry
aswciated with the AD394, AD395. It is recommended that any
analog signal path carrying significant current!! have its own
return connection to pin 23 as shown in Figure 7.
AD394
AD39S
can be a problem. These problems are compounded if a current
booster stage is used, or if multiple AD394, AD395 packages
are used. Figure 8 illustrates the parasitic impedances which
influence output accuracy.
An output buffer configured lis a subtractor as shown in Figure
9 can greatly reduce these errors. First, the effects of voltage
drops in wiring resistances is eliminated by sensing the voltage
directly at the load with R4. The voltage drops caused by current!!
flowing through ~A are eliminated by sensing the remote ground
directly with R3. Resistors RI through R4 should be well matched
in order to achieve maximum rejection of the voltage appearing
across ~A. Resistors matched to within one percent (including
the effects of RWl and R Wl) will reduce ground interaction
errors by a factor of 100.
Voun 1 - - - - - - ,
VOUT2 I - - - - - ,
VOUT3
TO POWER
GROUND
R1-R4 MATCH TO
,% OR BETTER
Figure 9. Use of Subtractor Amplifier to Preserve
Accuracy
SHOWN WITH ALL
:,~~~~~~~~
I
lOOTHER
II
ANALOG CIRCUITS
OPERATION FROM :t12 VOLT SUPPLIES
MODE
L ______
..J
Figure 7. Recommended Ground Connections
Several complications arise in practical ~ems, particularly if
the load is referred to a remo~ groUnd. These complications
include dc gain errors due to wiring resistance between DAC
and load, noise due to currents from other circuits flowing in
power ground return impedances, and offset!! due to multiple
load currents sharing the same signal ground returns. While the
DAC outputs are accurately developed between the output pin
and pin 23 (AGND), delivering these signals to remote loads
+15V
R"
2'
z...
A3
AD394
AD39S
Figure 10 shows a suggested circuit to set up a :!::8.192V output
range. To help prevent poor gain drift due to possible mismatch
between RIN and RnmvBNIN of divider network it is recommended
to buffer the potentiometer wiper voltage with an OP-07.
",-,
.....
z'"
The AD394, AD395 may be used with :!:: 12 volt :!:: 5% power
supplies if certain conditions are met. The most important limitation is the output swing available from the output op amps.
These amplifiers are capable of swinging only as far as 3 volts
from either supply. Thus, the normal ± 10 volt output range
cannot be used. Changing the output scale is accomplished by
changing the reference voltage. With a supply of ± 11.4 volts
(5% less than ± 12V), the output range is restricted to a maximum
±8.4V swing. It may be useful to scale the output at ±8.192
volts (yielding a scale factor of 4 millivolts per LSB).
REMorE GROUND
""
Rw.
R2
soon
ANALOG
OUTPUTS
R.
B.25k
z..
ro.-
t
TO POWER
GROUND
laB
A1-A3: OPTIONAL CURRENT BOOSTERS
RW1-~: WIRING RESISTANCES
R1. A3: 1% METAL FILM OR BETTER
R2: LOW TC MULTI-TURN TRIMPOT
2oA. loa: SIGNAL GROUND RETURN IMPEDANCE
ZPG: POWER GROUND RETURN IMPEDANCES
TO POWER
GROUND
Figure 8. Grounding Errors in Multiple-AD394, AD395
Systems
2-32 DIGITAL-TO-ANALOG CONVERTERS
Figure 10. Connections for ±8.192V Full Scale
(Recommended for ± 12V Power Supplies)
AD394/AD395
POWER SUPPLY DECOUPLING
The power supplies used with the AD394, AD395 should be
well filtered and regulated. Local supply decoupling consisting
of a lOI.l.F tantalum capacitor in parallel with O.l~ ceramic is
sugested. The decoupling capacitors should be connected between
the AD394 supply pins and the AGND pin. If an output booster
is used, its supplies should also be decoupled to the load
ground.
16.81T
DATA
BUS
+15V
-15V
+10.DOOV
AD2710LN
OUTPUTS
TO POWER
GROUND
Figure 11. Low Drift AD394, AD395 Configuration
Applications
INTERFACING THE AD394, AD395 TO
MICROPROCESSORS
The AD394, AD395 control logic provides simple interface to
microprocessors. The individual latches allow for multi-DAC
interfacing to a single data bus.
112
74lS139
AO
i/iR-------'
ALL GATES: 1/474LS32
Figure 12. AD394, AD395 16-Bit Bus Interface
8-BIT PROCESSORS
The circuit of Figure 13 shows the general principles for
connecting the AD394 or the AD395 to an 8-bit data bus.
The 74LS244 buffers the data bus; its outputs are enabled
when the DAC address appears on the address bus. The first
byte sent to the DAC is loaded to the 74LS373 octa1latch
and, when the second byte is sent to the DAC, it is combined
with the first byte to create a 12-bit word. The connections
shown are for right-hand justified data. CS and WR inputs
to the DAC are also gated, and when active, the DAC is
loaded. Pull-up resistors at the output of the 74LS244 buffer
ensure that the inputs to the DAC do not float at an ill-defined
levd when the DAC is not being addressed. This method of
connecting 12-bit DACs to an 8-bit data bus is most cost
effective when multiple DACs are utilized for 8-bit data bus
applications.
••,,{ co•
In the addressing scheme shown, AO represents the least significant
word address bit. Data may reside in either the 12MSBs (left-justified) or the 12LSBs (right-justified). Left justification is useful
when the data word represents a binary fraction of full scale,
while right-justified data usually represents an integer value
between 0 and 4095.
."
{
.
"",,,
'"'
".
..J
t.>- f+4-tJ-+++H
H++..-+++H
~~:
16-BIT PROCESSORS
The AD394, AD395 are 12-bit resolution DAC systems and are
easily interfaced to 16-bit wide data buses. Several possible
addressing configurations exist.
In the circuit of Figure 12, a system write signal is used to
control the decoded address lines and a 74LS139 decoder driven
from the least significant address bits provides the active-low
CS 1 through CS4 signals. In the circuit of Figure 12, address
lines AO and Al each select a single DAC of the four contained
in the AD394 or AD395. The use of a separate address line for
each DAC allows several DACs to be accessed simultaneously.
The address lines are gated by the simultaneous occurrence of a
system WR and the appropriately decoded base address.
ANALOG
OUTPUTS
A1
The AD2710 is a suitable reference source for such systems.
It features a guaranteed maximum temperature coefficient of
± IppmI"C. The combination of the AD2710LN and AD394,
AD395 shown in Figure 11 will yidd a multiple-DAC system
with maximum full-scale drift of ± 6ppmI"C and excellent
+15V
D11
12 BITS
'-------------,A DO
AD394
AD395
IMPROVING FULL-SCALE STABILITY
In large systems using multiple DACs, it may be desirable
for all devices to share a common reference. A precision
reference can greatly improve system accuracy and temperature
stability.
tracking.
r---------~
~tw
1.LS
DECODER
1>---4I----*~
NOTE:
UNUSED HEX INVERTER INPUTS SHOULD BE nED LOW. ALL OTHER
GATE INPUTS SHOWN SHOULD BE TIED HIGH TO +5V
THROUGH A 10kU RESISTOR.
Figure 13. AD394, AD395 8-Bit Data Bus Interface
DIGITAL-TO-ANALOG CONVERTERS 2-33
•
+15V
Applications
-15V
+5V
The functional density of the AD394 and AD395 permits complex
analog functions to be produced under digital control, where
board space requirements would otherwise be prohibitive. Multiple-output plotters, multi-channel displays and complex
waveform generation and multiple programmable voltage soUtCeS
can all be implemented with the AD394 or AD395 in a fraction
of the space which would be needed if separate DACs were
used.
3301l
D4"HIGH"
/'
DS"LOW"
USING THE AD394 FOR ANALOG-TO-DIGITAL
CONVERSION
Many systems require both analog output and analog input
capability. While complete integrated circuit analog-to-digital
converters (such as the AD574A) ate readily available, the AD394
can be used as the precision analog section of an ADC if some
external logic is available. Several types of analog-to-digital
converters can be built with a DAC, compatator, and control
logic, including staircase, tracking, and successive-approximation
types. In systems which include a microprocessor, only a compatator must be added to the AD394 to accomplish the ADC
function since the processor can perform the required digital
operations under softwate control. A suitable circuit is shown in
Figure 14. The AD311 compatator compates the unknown
input voltage to one of the AD394 outputs for the analog-to-digital
conversion, while the other three outputs are used as normal
DACs. The diode clamp shown limits the voltage swing at the
ANALOG
'NPUT
-1OVTO +1DV
..". = AIN > YOUT1
"(t" = AlN < YOU"
D3
A 1: DAC OUTPUT BOOSTER
A2. A3: AD311 COMPARATOR (OR EQUIVALENT)
Figure 15. Programmable Window Comparator Used in
Power-Supply Testing
In the circuit of Figure 15, two AD311 voltage compatators are
used within AD395 to test the output of a 5 volt power-supply
regulator. The AD395 VOurl output (through an appropriate
current booster) drives the input to the regulator to simulate
vatiations in input voltage. The output of the regulator is applied
to compatators 1 and 2, with their outputs wire-ORed with
LED indicators as shown. The test limits for each compatator
are programmed by the AD395 VOUTI and VOUT3 outputs.
When the output of the device under test is within the limits,
both compatators are off and Dllights. If the output is above
or below the limits, either D4 or D5 lights.
AD395 AS A MULTIPLIER AND ATTENUATOR
So far, it has been assumed that the reference voltage V RBFIN is
fixed. In fact, V RBFIN can be any voltage within the range (-l1V
< V RBFIN < + llV). It can be negative, positive, sinusoidal or
whatever the user prefers. This leads to the name "Multiplying
D/A Converters" because the output voltage, Your, is proportional
to the product of the digital input word and the voltage at the
V REFIN terminal.
VOUT = -1, (VREFIN) • (~)
Figure 14. Using One AD394 Output for AID Conversion
compatator input and improves conversion speed. With careful
layout, a new compatison can be performed in less than 15
microseconds, resulting in 12-bit successive approximation conversion in under 180 microseconds. The benefit of the AD394
in this application is that one ADC and three DACs can be
implemented with only two IC packages (the AD394 and the
compatator).
PROGRAMMABLE WINDOW COMPARATOR
The AD395 can be used to perform limit testing of responses to
digitally-controlled input signals. For example, two DACs may
be used to generate software-controlled test conditions for a
component or circuit. The response to these input conditions
can either be completely converted from analog to digital or
simply tested against high and low limits generated by the two
remaining DACs in the AD395.
(0
0
21
-28
_11
14
-FULL SCALE
VOUT
= (VREAN)·(81~2 -
1)
Figure 1. AD396 as a Four-Quadrant Multiplier of Reference
Input and Digital Input
ANALOG OUTPUT VOLTAGE VREFIN
= +10VOLTS
1111
1111
1111 11
8192 }
+ I·(VREFIN) {8191
+9.9988V
+ FULL SCALE - ILSB
1100
0000
0000 00
8192 }
+ I·(VREFIN) {4096
+S.OOOV
+ 112 SCALE
1000
0000
0000 01
+ I·(VREFIN) {8:92}
+ 1.22mV
+ILSB
1000
0000
0000 00
+ I·(VREFIN )
+O.OOOV
ZERO
0111
11 II
IIII II
- I· (VREF1N) {81192}
-1.22mV
-ILSB
0100
0000
0000 00
-I·(VREFIN) {4096
8192 }
-S.OOOV
-1I2SCALE
0000
0000
0000 00
-I·(VREFIN) {8192
~192 }
-IO.OOOV
-FULL SCALE
{8~92}
Table I. AD396 Bipolar Code Table
2-38 DIGITAL-TO-ANALOG CONVERTERS
ILSB
+~
<0
MULTIPLYING MODE
Figure I shows the transfer function for the AD396. The diagram
indicates an area over which many different combinations of the
reference input and digital input can result in a particular analog
output voltage. The highlighted transfer line in the diagram
indicates the transfer function for a fixed reference at the input.
The digital codes above the diagram indicates the mid and endpoints of the function. The relationship between the reference
input (VREFIN)' the digital input code, and the analog output is
given in Table I below. Note that the reference input signal sets
the slope of the transfer function (and determines the full-scale
output at code 111..111) while the digital input selects the horizontal position in each diagram.
..§ .g § .. .§ ..... ..8
..
.. ..
.... § .... §.~ .. 8~ E..
=
Digital Circuit Details -'- AD396
DATA AND CONTROL SIGNAL FORMAT
The AD396 accepts I4-bit data by loading two separate input
registers off an 8-bit data bus, and then loading the internal
DAC register. The LS (least significant) register is loaded with
the bottom 8-bits of the I4-bit word by selecting the appropriate
address lines (see Table II). The MS (most significant) register
is loaded with the top 6-bits in a similar manner. The CS and
WR line must also be asserted to load the registers. The internal
DAC register can then be loaded with the l4-bit data word. The
appropriate DAC or DACs are selected by asserting CSI-CS4
(see Table III). If CSI-CS4 are all brought low coincidentally,
all four DAC outputs will be updated to the value located in the
DAC register. When Al =0 and Ao=O all DAC registers are
transparent so by placing all Os or Is on the data inputs the user
can load the DACs to zero or full scale in one write operation.
This provides simple system calibration.
WI[ ~
Al
AO
X
I
X
X
Device not selected
I
X
X
X
No data transfer
0
0
0
0
DAC loaded directly from Data Bus
0
0
0
I
MS Input Register loaded from Data Bus
0
0
I
0
LS Input Register loaded from Data Bus
0
0
I
I
DAC Register loaded from Input Registers.
r-____--f=::;------r----~2a v"".,,..
AD396
B7
,
,, ,,
,,, ,,,
:'
I,
...
Function
Table II. Truth Table
CSI
CS2
CS3
CS4
I
0
I
I
I
0
I
I
0
I
I
0
I
I
I
0
I
0
I
I
I
I
0
0
Operation
AUDACsLatched
Load DAC I From Data Register
Load DAC 2 From Data Register
Load DAC 3 From Data Register
Load DAC 4 From Data Register
AU DACs Simultaneously Loaded
Figure 2. AD396 Block Diagram
Table III. DAC Select Matrix
TIMING
The AD396 timing is shown in Figure 3, and has a few restrictions
as stated in Table IV. WR must maintain a minimum pulse
width of 240ns for desired operation to occur. When loading
data in from the data bus, data must be stable for at least I80ns
before returning WR to a high state. The Data must be held
constant for at least 30ns after WR goes high to assure latching
of valid data. DAC settling time is measured from the falling
edge of the WR command.
(Vcc=
Parameter
Limit at
TA=2S"C
I,
0
I,
0
I,
140
20
0
0
170
I.
I,
I.
I,
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED ""OM 10% TO!IO"Ie Of +5V. t,=t,=20ml.
2. TIMING MEASUREMENT REFERfNCE LEVEL IS VII
~ VIL
Figure 3. AD396 Timing Diagram
+ ISV, VEE = -ISV, VREF = + lOY)
Limit at
TA=Oto +70"C
T A= -2S"C.o +8S"C
Limit at
T A= -SS"C.o +12S"C
Units
Test ConditionsiColftlDents
0
0
70
20
0
0
200
0
0
180
30
0
0
240
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
Address Valid to Write Se[Up Time
Address Valid to Write Hold Time
Data Setup Time
Data Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
Table IV. Timing Characteristics
DIGITAL-TO-ANALOG CONVERTERS 2-39
Analog Circuit Details
GROUNDING RULES
The AD396 includes two ground connections in order to minimize
system accuracy degradation arising from grounding errors. The
two ground pins are designated DGND (Pin 17) and AGND
(Pin 23). The DGND pin is the return for the supply currents
of the AD396 and serves as the reference point for the digital
input thresholds. Thus DGND should be connected to the same
ground as the circuitry which drives the digital inputs.
Pin 23, AGND, is the high-quality analog ground connection.
This pin should serve as the reference point for all analog circuitry
associated with the AD396. It is recommended that any analog
signal path carrying significant currents have its own return
connection to Pin 23 as shown in Figure 4.
Ali ouput buffer configured as a subtractor as shown in Figure
6 can greatly reduce these errors. First, the effects of voltage
drops in wiring resistances is eliminated by sensing the voltage
directly at the load with R4. The voltage drops caused by currents
flowing.through ZoA are eliminated by sensing the remote gound
directly with R3. Resistors RI through R4 should be well matched
in order to achieve maximum rejection of the voltage appearing
across ~A' Resistors matched to within one percent (including
the effects of RW2 and R W3) will reduce ground interaction
errors by a factor of 100.
AD396
R2
'Ok
TO POWER
GROUND
R1-R4 MATCH TO 1% OR BETI'ER
Figure 6. Use of Subtractor Amplifierto Preserve Accuracy
lOOTHER
ANALOG CIRCUITS
Figure 4. Recommended Ground Connections
Several complications arise in practical systems, particularly if
the load is referred to a remote ground. These complications
include dc gain errors due to wiring resistance between DAC
and load, noise due to currents from other circuits flowing in
power ground return impedances, and offsets due to multiple
load currents sharing the same signal ground returns. While the
DAC outputs are accurately developed between the output pin
and Pin 23 (AGND), delivering these signals to remote loads
can be a problem. These problems are compounded if a current
booster stage is used, or if multiple AD396 packages are used.
Figure 5 illustrates the parasitic impedances which influence
output accuracy.
OPERATION FROM :!:12V SUPPLIES
The AD396 may be used with :!: 12 volt :!: 5% power supplies if
certain conditions are met. The most important limitation is the
output swing available from the output op amps. These amplifiers
are capable of swinging only as far as 3 volts from either supply.
Thus, the normal ± 10 volt output range cannot be used. Changing
the output scale is accomplished by changing the reference
voltage. With a supply of ± 11.4 volts (5% less than :!: 12V), the
output range is restricted to a maximum ± 8.4 swing. It may be
useful to scale the output at ± 8.192 volts (yielding a scale factor
of I millivolt per LSB).
Figure 7 shows a suggested circuit to set up a ±8.192V output
range. To help prevent poor gain drift due to possible mismatch
between RIN and RTHEVENIN of the divider network it is recommended to buffer the potentiometer wiper voltage with an
OP-07.
+15V
Ow,
....
AD396
I.
rr=
z..
....
23
....
A3
AD396
R"
REMOTE GROUND.
R2
ooon
ANALOG
Ru
....
OUTPUTS
R3
8.25k
R1. R3: 1% METAL FILM OR BEnER
R2: lOW TC MULTI·TURN TRIMPOT
z..
~
Zo.
t
At-A3: OPTIONAL CURRENT BOOSTERS
Rw,-Rws: WIRING RESISTANCES
TO POWER
GROUND
Zc.... laa: SIGNAL GROUND RETURN IMPEDANCE
Zpc: POWER GROUND RETURN IMPEDANCES
Figure 5. Grounding Errors in Multiple-AD396 Systems
2-40 DIGITAL-TO-ANALOG CONVERTERS
TO POWER
GROUND
Figure 7. Connections for ± B.192V Full Scale
(Recommended for ± 12VPowerSupplies)
Applications - AD396
POWER SUPPLY DECOUPUNG
The power supplies used with the AD396 should be well fIltered
and regulated. Local supply decoupJing consisting of a lO",F
tantalum capacitor in parallel with O.I",F ceramic is suggested.
The decoupJing capacitors should be connected between the
AD396 supply pins and the AGND pin. If an output booster is
used, its supplies should also be decoupled to the load ground.
The circuit in Figure 9 demonstrates how the AD396 is used to
set up four different voltage thresholds (l threshold per DAC).
IMPROVING FULL-SCALE STABILITY
In large systems using multiple DACs, it may be desirable for
all devices to share a common reference. A precision reference
can greatly improve system accuracy and temperature stability.
II
The AD2710 is a suitable reference source for such systems. It
features a guaranteed maximum temperature coefficient of
± IppmJ"C. The combination of the AD2710LN and AD396
shown in Figure 8 will yield a multiple-DAC system with maximum
full-scale drift of ± 6ppmf'C and excellent tracking.
+15V
+15V
OUTPUT
Figure 9. A0396 in ATE Systems
-15V
OUTPUTS
TO POWER
GROUND
Figure 8. Low Drift A 0396 Configuration
Applications
USING THE AD396 IN AUTOMATIC TEST
EQUIPMENT
Most Automatic Test Equipment requires multiple accurate
analog voltage thresholds which must be under microprocessor
control. The AD396 is useful in such an application where
space is at a premium and accuracy is essential.
A fixed reference is used for the VREFIN input of each of the
multiplying DACs. The digital code corresponding to the desired
voltage output is put on the bus, and the CHIP SELECT for
the proper DAC is asserted. Two of the four DACs are used to
set logic thresholds on the AD345 pindriver. The AD345 pindriver
will then accurately test the logic thresholds on an I/O pin of
the DUT (Device Under Test). The pindriver tests the pin by
driving the pin to the proper logic thresholds set by the DACs.
The response from the I/O pin will then enter the AD9687 dual
comparator. The other two DACs are used to set the voltage
threshold for either a Logic HI (2.2V-5.0V) or a Logic LO (OVO.8V). This is done by placing the upper voltage limit on the
positive terminal of the higher comparator, and the lower voltage
limit on the negative terminal of the lower comparator. The
response can then be accurately tested if it is either a Logic HI
or LO by looking if the output value of the pin falls within the
designated window.
OIGITAL-TO-ANALOG CONVERTERS 2-41
THE AD396 IN SYNCHRO-TO-D1GITAL CONVERTERS
The AD396 is useful in navigation systems where a Synchro-toDigital Converter is needed. The Synchro-to-Digital Converter
is used to measure angular position and is needed to measure
pitch in the x-y-z axes and roll in the x-y-z axes. An SoD converter
has three inputs and two converters are needed for this application.
Each SoD converter uses two multiplying DACs and the accuracy
of the S-D converter depends on the accuracy of the multiplying
DAC.
The outputs of the transformer are Vsinwt(sinO) and Vsinwt(cosO).
These two outputs are applied to the VREF inputs of the DACs
whose digital input words are proportional to the sine and cosine
of angle 0 as shown in Figure 10. The output of the cosine
multiplier is given by Vsinwt(sinO)(cosq,), and the output of the
REF
the sine multiplier is given by Vsinwt(cosO)(sinq,).
These signals are subtracted by the error amplifier to give the
error signal which is:
Vsinwt( sinOcosq,-cosOsinq,) = Vsinwt( sinO-q,)
This error signal is demodulated by the phase sensitive detector
which utilizes the system reference voltage and a dc error signal
proportional to sin(O-q,) is produced. The dc error signal is fed
back via an integrator and V.C.O. to drive the up-down counter
until the error signal is nulled. The contents of the up-down
counter give a binary representation of the angular position. For
more information on synchro-to-digital conversion the reader is
referred to Analog Devices Synchro & Resolver Conversion
Handbook.
.::R",o.o-l-..!......J
51
53
52
BUSY
INHIBIT
VELOCITY
OUTPUT
Figure 10. A Tracking Synchro-to-Digital Converter
2-42 DIGITAL-TO-ANALOG CONVERTERS
r.ANALOG
WDEVICES
OACPORT Low-Cost Complete
fJ.P-Compatible 8-Bit OAC
AD557 I
FEATURES
Complete 8-Bit DAC
Voltage Output - 0 to 2.56V
Internal Precision Band-Gap Reference
Single-Supply Operation: +5V (±10%)
Full Microprocessor Interface
Fast: 1ILs Voltage Settling to ± 1/2LSB
Low Power: 75mW
No User Trims Required
Guaranteed Monotonic Over Temperature
All Errors Specified T min to T max
Small 16-Pin DIP or 20-Pin PLCC Package
Low Cost
AD557 FUNCTIONAL BLOCK DIAGRAM
.
DIGITAL INPUT DATA
CONTROL
INPUTS
,..--A---,
cs
fE
BIT 1
IMSBI •
BIT 8
•
•
•
•
• ILSBI
+Vcc
t
GNO
GND
~ ~
Your
VOUT SENSE A
'-~--~ VOUT SENSE B
PRODUCT DESCRIPTION
The AD557 DACPORT™ is a complete voltage-output 8-bit
digital-to-analog converter, including output amplifier, full
microprocessor interface and precision voltage reference on a
single monolithic chip. No external components or trims are
required to interface, with full accuracy, an 8-bit data bus to an
analog system.
The low cost and versatility of the AD557 DACPORT are
the result of continued development in monolithic bipolar
technologies.
The complete microprocessor interface and control logic is implemented with integrated injection logic (I 2L), an extremely
dense and low-power logic structure that is process-compatible
with linear bipolar fabrication. The internal precision voltage
reference is the patented low-voltage band-gap circuit which
permits full-accuracy performance on a single + 5V power supply.
Thin-mm silicon-chromium resistors provide the stability required
for guaranteed monotonic operation over the entire operating
temperature range, while laser-wafer trimming of these thin-film
resistors permits absolute calibration at the factory to within
±2.5LSB; thus, no user-trims for gain or offset are required. A
new circuit design provides voltage settling to ± 1I2LSB for a
full-scale step in 800ns.
PRODUCT HIGHLIGHTS
1. The 8-bit I2L input register and fully microprocessorcompatible control logic allow the AD557 to be directly
connected to 8- or 16-bit data buses and operated with standard
control signals. The latch may be disabled for direct DAC
interfacing.
2. The laser-trimmed on-chip SiCr thin-mm resistors are calibrated for absolute accuracy and linearity at the factory.
Therefore, no user trims are necessary for full rated accuracy
over the operating temperature range.
3. The inclusion of a precision low-voltage band-gap reference
eliminates the need to specify and apply a separate reference
source.
4. The AD557 is designed and specified to operate from a single
+4.5V to +S.5V power supply.
5. Low digital input currents, lOO ....A max, minimize bus loading.
Input thresholds are TTL/low voltage CMOS compatible.
6. The single-chip, low power I2L design of the AD557 is inherently more reliable than hybrid multichip or conventional
single-chip bipolar designs.
The AD557 is available in two package configurations. The
AD557JN is packaged in a 16-pin plastic, O.3"-wide DIP. For
surface mount applications, the AD557JP is packaged in a 20-pin
JEDEC standard PLCC. Both versions are specified over the
operating temperature range of 0 to + 70°C.
DACPORT is a trademark of Allalol Devices, Inc.
Covered by U.S. PateDt Nos. 3,117,863; 3,685,045; 4,323,795; other
pateDts pendiJII.
DIGITAL-TO-ANALOG CONVERTERS 2-43
SPECIFICATIONS
(@ TA
= +25'1:, Vee = + 5V unless otherwise specified)
Min
Model
AD557J
Typ
RESOLUTION
RELATIVE ACCURACY'
Oto +70"C
OUTPUT
Ranges
Current Source
Sink
±1I2
Max
Units
8
Bits
I
PIN CONFIGURATIONS
DIP
LSB
~
~
~
~
BIT 8 {LSBI
Oto +2.56
BIT 7
V
mA
+5
BIT6
Internal Passive
Pull-Down to Ground2
OUTPUT SETTLING TIME3
0.8
FULL SCALE ACCURACY'
@25°C
T_toT""",
±1.5
±2.5
ZERO ERROR
@25°C
T_toT....
1.5
BIT 5
±2.5
±4.0
LSB
LSB
±I
±3
LSB
LSB
±100
fJ.A
•
AD557
TOPVIEW
~
~
BIT 4
BIT3
~
B,T2
[Z
(MSB) BIT 1
[:!:
fJ.s
~
INottoScale}
~
~
~
r;;,
~
VOUT
V OUT SENSE A
VouTSENSEB
GND
~
GND
~
+Vcc
~
~
CS
CE
PLCC
MONOTONICITy5
Guaranteed
T min to Tmax
DIGITAL INPUTS
Tminto Tmax
Input Current
Data Inputs, Voltage
Bit On-Logic "I"
Bit On- Logic "0"
Controllnputs, Voltage
On-Logic"l"
On- Logic "0"
2.0
0
0.8
2.0
0
0.8
Input Capacitance
TIMING"
tw Strobe Pulse Width
T.,.;n toT....
tOH Data Hold Time
T min to Tmu:
tos Data Setup Time
T min to T mas:
POWER SUPPLY
Operating Voltage Range (VcCJ
2.56 Volt Range
Current (Icd
Rejection Ratio
V
V
r:~
BIT5
~
0
~V
A0557
NC~
V
BIT4
~
V
BIT 3
8
TOPVIEW
(Notto Scale)
i
OUT
~GND
s
SENSE B
NC
15 GNO
14 +Vcc
pF
4
225
300
10
10
225
ns
ns
ns
ns
300
ns
Ne
= NO CONNECT
fiS
ns
AD557 ORDERING GUIDE
+4.5
IS
POWER DISSIPATION, Va:=5V
OPERATING TEMPERATURE RANGE
/
BlTa
75
0
+5.5
25
0.03
mA
Model
Package
Options*
Temperature
%/%
AD557JN
AD557JP
Plastic (N-16)
PLCC (P-20A)
Oto + 70°C
Oto + 70°C
V
125
mW
+70
°C
NOTES
'Relative Accuracy is dermed as the deviation of the code transition points from the ideal transfer point on a
straight line from the offset to the full scale of the device. See "Measuring Offset Error" on AD558 data sheet.
'Passive pull-down resistance is 2kn.
'Settling time is specified for a positive-going full-scale step to ± 1I2LSB. Negative-going steps to zero
are slower, but can he improved with an external pull-down.
'The full-scale output voltage is 2.55V and is guaranteed with a + 5V supply.
SA monotonic converter has a maximum differential linearity error of ± ILSB.
·See Figore 7.
*
ee Section 14 for package outline infonnatlon.
Specifications shown in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
vcc to Ground
Digital Inputs (Pins 1-10)
VOUT
••••••
Power Dissipation . . . . . .
Storage Temperature Range
N IP (Plastic) Packages ..
Lead Temperature (soldering, 10 sec)
. . . . . OV to +18V
. . . . . 0 to +7.0V
Indefinite Short to Ground
Momentary Short to Vee
. . . . . 450mW
- 25°C to + 100°C
. . . . 300°C
2-44 DIGITAL-TO-ANALOG CONVERTERS
Thermal Resistance
Junction to Ambient/Junction to Case
NIP (Plastic) Packages . . . . . . . . . . .. 140/55°C/W
*Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
AD557
CIRCUIT DESCRIPTION
The ADSS7 consists of four major functional blocks fabricated
on a single monolithic chip (see Figure I). The main D/A converter
section uses eight equally weighted laser-trimmed current sources
switched into a silicon-chromium thin-film Rl2R resistor ladder
network to give a direct but unbuffered OmV to 400mV output
range. The transistors that form the DAC switches are PNPs;
this allows direct positive-voltage logic interface and a zero-based
output range.
.
DIGITAL INPUT DATA
CONTROL
INPUTS
BIT 1
IMSBI •
....---"----,
cs
•
•
•
•
BIT 8
• (LSBI
CE
+Vcc
t
GND
GNO
¢ ¢
VOUT
Vour SENSE A
'--+JWK:
VOUT SENSE B
CONNECTING THE AD557
The ADSS7 has been configured for low cost and ease of application. All reference, output amplifier and logic connections are
made·internally. In addition, all calibration trims are performed
at the factory assuring specified accuracy without user trims.
The only connection decision to be made by the user is whether
the output range desired is unipolar or bipolar. Clean circuit
board layout is facilitated by isolating all digital bit inputs on
one side of the package; analog outputs are on the opposite side.
UNIPOLAR 0 TO + 2.S6V OUTPUT RANGE
Figure 2 shows the configuration for the 0 to + 2.S6V full-scale
output range. Because of its precise factory calibration, the
ADSS7 is intended to be operated without user trims for gain
and offset; therefore, no provisions have been made for such
user trims. If a small increase in scale is required, however, it
may be accomplished by slightly altering the effective gain of
the output buffer. A resistor in series with VOUT SENSE will
increase the output range. Note that decreasing the scale by
putting a resistor in series with GND will not work properly
due to the code-dependent currents in GND. Adjusting offset
by injecting dc at GND is not recommended for the same
reason.
Figure 1. Functional Block Diagram
The high-speed output buffer amplifier is operated in the noninverting mode with gain determined by the user-connections at
the output range select pin. The gain-setting application resistors,
are thin film laser trimmed to match and track the DAC resistors
and to assure precise initial calibration of the output range, OV
to 2.56V. The amplifier output stage is an NPN transistor with
passive pull-down for zero-based output capability with a single
power supply.
The internal precision voltage reference is of the patented band-gap
type. This design produces a reference voltage of 1.2V and
thus, unlike 6.3V temperature-compensated zeners, may be
operated from a single, low-voltage logic power supply. The
microprocessor interface logic consists of an 8-bit data latch and
control circuitry. Low power, small geometry and high speed
are advantages of the I2L design as applied to this sect:on. I2L
is bipolar process compatible so that the performance of the
analog sections need not be compromised to provide on-chip
logic capabilities. The control logic allows the latches to be
operated from a decoded microprocessor address and write
signal. If the application does not involve a ",p or data bus,
wiring CS and CE to ground renders the latches "transparent"
for direct DAC access.
Digital Input Code
Binary
0000 0000
0000 0001
0000 0010
0000 1111
0001 0000
Olll 1111
10000000
llOO 0000
llll llll
Hexadecimal
00
01
02
OF
10
7F
80
CO
FF
Figure 2. 0 to 2.56V Output Range
BIPOLAR -1.28V TO + l.28V OUTPUT RANGE
The ADSS7 was designed for operation from a single power
supply and is thus capable of providing only a unipolar 0 to
+ 2. S6V output range. If a negative supply is available, bipolar
output ranges may be achieved by suitable output offsetting and
scaling. Figure 3 shows how a ± 1.28V output range may be
achieved when a - SV power supply is available. The offset is
provided by the ADS89 precision 1.2V reference which will
operate from a +SV supply. The AD711 output amplifier can
provide the necessary ± 1.28V output swing from ±SV supplies.
Coding is complementary offset binary.
Skll
Output
Decimal Voltage
0
I
2
IS
16
127
128
192
255
0
O.OIOV
0.020V
O.ISOV
0.160V
l.270V
1.280V
1.920V
2.SSV
-5V
INPUT CODE
Your
00000000
10000000
11111111
+1.28V
OV
-l.21V
Figure 3. Bipolar Operation of AD557 from ± 5V Supplies
DIGITAL-TO-ANALOG CONVERTERS 2-45
TIMING AND CONTROL
Applications
GROUNDING AND BYPASSING
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the ADS 57 is intended for application in microcomputer
systems where digital noise is prevalent, special care must be
taken to assure that its inherent precision is realized.
The ADSS7 has two ground (common) pins; this minimizes
ground drops and noise in the analog signal path. Figure 4
shows how the ground connections should be made.
The ADSS7 has data input latches that simplify interface to 8and 16-bit data buses. These latches are controlled by Chip
Enable (CE) and Chip Select (CS) inputs. CE and CS are internally
"NORed" so that the latches transmit input data to the DAC
section when both CE and CS are at Logic "0". If the application
does not involve a data bus, a "00" condition allows for direct
operation of the DAC. When either CE or CS go to Logic "1,"
the input data is latched into the registers and held until both
CE and CS return to "0." (Unused CE or CS inputs should be
tied to ground.) The truth table is given in Table I. The logic
function is also shown in Figure 6.
'_IDa..
ell e! DACDa"
0
0
0
1
0
1
0
1
X
X
)it--+--- TO SYSTEM GND
J
0
0
"transparent"
0
0
0
1
0
1
0
1
"transparent"
J
J
0
0
1
X
X
1
latching
latching
latching
previous data
previous data
latching
latched
latched
Notes: X "" Does not matter
J ""
---~ TOSYSTEMGND
O.1I1F
J
LatclI
Coadilioa
Logic Threshold at Positive-Goiag Transition
(SEE TEXT)
lllJl-""----t~
Table I. AD557 Control Logic Truth Table
TO SYSTEM Vee
Figure 4. Recommended Grounding and Bypassing
It is often advisable to maintain separate analog and digital
grounds throughout a complete system, tying them common in
one place ouly. If the common tie-point is remote and accidental
disconnection of that one common tie-point occurs due to card
removal with power on, a large differential voltage between the
two commons could develop. To protect devices that interface
to both digital and analog parts of the system, such as the ADSS7,
it is recommended that common ground tie-points should be
provided at each such device. If only one system ground can be
connected directly to the ADSS7, it is recommended that analog
common be selected.
USING A "FALSE" GROUND
Many applications, such as disk drives, require servo control
voltages that swing on either side of a "false" ground. This
ground is usually created by dividing the + l2V supply equally
and calling the midpoint voltage "ground."
Figure 5 shows an easy and inexpensive way to implement this.
The ADS86 is used to provide a stable SV reference from the
system's + 12V supply. The op amp shown likewise operates
from a single ( + 12V) supply available in the system. The resulting
output at the VOUT node is ±2.SV around the "false" ground
point of SV. ADSS7 input code vs. VOUT is shown in Figure 6.
7.5
5.0
2.5
AD567 INPUT CODE
Figure 6. AD557 Input Code vs. Level Shifted Output in
"False" Ground Configuration
In a level-triggered latch such as that used in the ADSS7, there
is an interaction between the data setup and hold times and the
width of the enable pulse. In an effort to reduce the time required
to test all possible combinations in production, the ADSS7 is
tested with TDs=Tw=22Sns at 25°C and 300ns at Tmin and
T max, with T DH = IOns at all temperatures. Failure to comply
with these specifications may result in data not being latched
properly.
Figure 7 shows the timing for the data and control signals,
and CS are identical in timing as well as in function.
DATA
INPUTS
CiORCf
~
O.8V-
~x=.
to. - . . j __
uv~I
r==m
"
-~ ... ==:j
>-+---.....()Vo~
+12V
100k
c
DAC
v OUTPUT
- -------~---
r~·
lOOk
tw - STROBE PULSE WIDTH = 2:2In. min
= DATA HOLD llME • 'Ons min
to. = DATA SETUP nME = 2Z&n. min
to..
tunuNa - DAC OUTPUT SEn'UNG TIME TO ::t112 LS8
Figure 5. Level Shifting the AD557 Output Around a "False"
Ground
2-46
DIGITAL-TO~ANALOG
CONVERTERS
Figure 7. AD557 Timing
CE
r'III ANALOG
WDEVICES
FEATURES
Complete 8-Bit DAC
Voltage Output - 2 Calibrated Ranges
Internal Precision Band-Gap Reference
Single-Supply Operation: +5V to +15V
Full Microprocessor Interface
Fast: 1ps Voltage Settling to ±1/2LSB
Low Power: 75mW
No User Trims
Guaranteed Monotonic Over Temperature
All Errors Specified Tmin to Tmax
Small 16-Pin DIP, 20-Pin PLCC and LCC Packages
Single Laser-Water-Trimmed Chip for Hybrids
Low Cost
PRODUCT DESCRIPTION
The ADSS8 DACPORTTM is a complete voltage-output 8-bit
digital-to-analog converter, including output amplifier, full
microprocessor interface and precision voltage reference on a
single monolithic chip. No external components or trims are
required to interface, with full accuracy, an 8-bit data bus to
an analog system.
The performance and versatility of the DACPORT is a result of
several recently-developed monolithic bipolar technologies.
The complete microprocessor interface and control logic is
implemented with integrated injection logic (12 L), an extremely dense and low-power logic structure that is process-compatible with linear bipolar fabrication. The internal precision
voltage reference is the patented low-voltage band-gap circuit
which permits full-accuracy performance on a single +SV to
+lSV power supply. Thin-film silicon-chromium resistors
provide the stability required for guaranteed monotonic operation over the entire operating temperature range (all grades),
while recent advances in laser-wafer-trimming of these thinfilm resistors permit absolute calibration at the factory to
within ±lLSB; thus no user-trims for gain or offset are required. A new circuit design provides voltage settling to
±1I2LSB for a full-scale step in 800ns.
The AD558 is available in four performance grades. The
ADS 58} and K are specified for use over the 0 to + 70° C temperature ran
while the AD558S and T grades are specified for -55 C to +l25°C operation. The "}" and "K" grades
are available either in 16-pin plastic (N) or hermetic ceramic
(D) DIPS. They are also available in 20-pin }EDEC standard
PLCC packages. The "S" and "T" grades are available in
l6-pin hermetic ceramic DIP packages and 20-pin LCC
packages.
Ie,
·Covered by u.s. Patent No •. 3,887,8631 3,68S,04SI4,3Z37951
Patents Pending.
DACPORT is a trademark of Analog Devices, Inc.
OACPORT Low-Cost Complete
fJ.P-Compatible 8-Bit OAC
A0558* I
AD558 PIN CONFIGURATION (DIP)
AD558 PIN CONFIGURATION (PLCC AND LCC)
i§
Ne = NO CONNECT
!
~
Ir: I~
I
PRODUCT HIGHLIGHTS
1. The 8-bit \2 L input register and fully microprocessorcompatible control logic allow the AD558 to be directly
connected to 8- or l6-bit data buses and operated with
standard control signals. The latch may be disabled for
direct DAC interfacing.
2. The laser-trimmed on-chip SiCr thin-film resistors are calibrated for absolute accuracy and linearity at the factory.
Therefore, no user trims are necessary for full rated accuracy over the operating temperature range.
3. The inclusion of a precision low-voltage band-gap reference
eliminates the need to specify and apply a separate reference sou rce.
4. The voltage-switching structure of the AD558 DAC section
along with a high-speed output amplifier and laser-trimmed
resistors give the user a choice of OV to +2.56 V or OV to
+ lOV output ranges, selectable by pin-strapping. Circuitry
is internally compensated for minimum settling time on
both ranges; typically settling to ±1I2LSB for a full-scale
2.55 volt step in 800ns.
5. The AD558 is designed and specified to operate from a
single +4.5V to +l6.SV power supply.
6. Low digital input currents, lOOILA max, minimize bus
loading. Input thresholds are TTL/low voltage CMOS
compatible over the entire operating Vec range.
(continued further)
DIGITAL-TO-ANALOG CONVERTERS 2-47
SPECIFICATIONS
(@ TA
= + 25"1:. Vee ;:: + 5V to + 15V unless otherwise specified)
Model
AD558J
Typ
AD558K
Typ
AD558S'
Typ
AD558T'
Typ
Mu
Units
RESOLUTION
8
8
8
8
Bits
RELATIV!!ACCURACY'
Oto + 7O"C
- 55"C to + 125"C
,01/2
,0114
,01/2
,03/4
,01/4
±3/8
LSB
LSB
MiD
OUTPUT
Ranges'
Current Source
Sink
Mu
MiD
Oto +2.56
Oto +10
Oto
0.8
2.0
FULLSCAL!!ACCURACY'
@25"C
TmintoTmu.
ZERO ERROR
@25"C
Tmm to Tmu
1.5
3.0
0.8
2.0
MiD
Oto +2.56
010 + 10
V
V
mA
+5
+5
Internal Passive
Internal Passive
Pull-Down to Ground
Pull·Down to Ground4
MONOTONICITY'
TmirltoTmu.
+ 10
+5
Internal Passive
Mu
Oto +2.56
Oto +10
Oto +2.56
+5
OUTPUT Sl!TTUNG TIM!!'
Ot02.56 Volt Range
Oto lOVoltRange4
MiD
Max
Internal Passive
Pull-Down to Ground
Pull-Down tD Ground
1.5
3.0
0.8
2.0
0.8
2.0
1.5
3.0
...
1.5
3.0
~.
,01.5
,02.5
,00.5
,01
,01.5
,02.5
,00.5
,01
LSB
LSB
,01
,02
,01/2
,01
,01
,02
,0112
,01
LSB
LSB
Guaranteed
Guaranteed
Guaraateed
Guaranteed
DIGITAL INPUTS
TmintoTIJIIlII
Input Current
Data Inputs, Voltage
BitOn-Logic"}"
Bit On- Logic ''0''
Control Inputs, Voltage
Do-Logic "I"
On- Logic "0"
Input Capacitance
TIMING'
tw Strobe Pulse Width
T.runtoTmu
tDH Data Hold Time
TmintoTDUIII
lOS Data Set-UpTime
TmintoTmu.
POWER SUPPLY
Operating Voltage Rsnge (Vee)
2.56 Volt Rsnge
10 Volt Rsnge
Current (Icc)
,0100
2.0
0
2.0
0
0.8
0.8
2.0
0
4
,0100
2.0
0
2.0
0
0.8
10
15
75
225
0
+16.5
+16.5
25
0.03
125
375
+70
+4.5
+11.4
15
75
225
0
+16.5
+16.5
25
0.03
~OperationoftbeOto lOvoitoutpUtraDgerequiresaminimwnsupplyvolrageof + 11.4volts.
4PassivepuD-downresistance is2kO for 2.S6volt range, 10k0for 10 voItrange.
SScttling time is specified for a positive-going full-scale step to ± 1/2LSB. Negative-going steps to zero
areslower, butcao beimproved withanextemalpuD--down.
'ThefullraugeoutputvoJragefortbe 2.S6 rangeis2.SSV aodis guaranteed. with a + SV supply,
fortbe 10Vrange,itis9.960V guaraoteedwitha + ISVsuppJy.
7A monotonic converter has amuimumdifferentiallinearityerrorof ± lLSB.
'See FiJure 7.
Specifications shown in boIdfaceare tested on all production units at fina1
e1ectricaltest.
Specifications subject to clwlge without notice.
V
V
0.8
pF
os
ns
ns
270
10
10
200
270
15
75
225
-55
+16.5
+16.5
25
0.03
125
375
+125
D3
ns
os
+4.5
+11.4
15
75
225
-55
+16.5
+16.5
25
0.03
V
V
mA
%/%
125
375
+125
mW
mW
"C
AD558 METALIZATION PHOTOGRAPH
NOTES
'The AD558 S & T grades are available processed sod.."...,..j to MlL-STD-883C1assB.
Consult Analog Devices' Military Databook for details.
2Re1ative Accuraq- is defined as the deviation ofthe code transition points from the ideal
transfer point on a suaigbt line from. the offset to the fullscal.e of the device. See "Measuring
Offset Error".
2.0
0
200
+4.5
+11.4
125
375
+70
V
V
4
200
270
10
10
200
270
10
200
270
+4.5
+11.4
0.8
4
200
270
~
100
2.0
0
4
200
270
10
10
200
270
Rejection Ratio
POWER DISSIPATION, Vcc=5V
Vee = 15V
OPERATING TEMPERATURE RANGE
,0100
2.0
0
Dimensions shown in inches and (mm).
r-
,.
D."
12.21
10
,.
iii.
"
12
13
ii:
14 ~
~I--------- 0.11212.8) ---------.~I
2-48 DIGITAL-TO-ANALOG CONVERTERS
AD558
ABSOLUTE MAXIMUM RATINGS
.....
. . . . . . OV to + 18V
Digital Inputs (Pins 1-10)
. . . . . . . . 0 to +7.0V
Indefinite Short to Ground
VOUT • • • • • •
Momentary Short to Vee
Power Dissipation
. . . . . 450mW
Storage Temperature Range
NIP (Plastic) Packages .
- 25°C to + 100°C
DIE (Ceramic) Package.
- 55°C to + 150°C
Lead Temperature (soldering, 10 sec) .
. . . . . . 300°C
Thermal Resistance
Junction to Ambient/Junction to Case
DIE (Ceramic) Package .
100/30°CIW
NIP (Plastic) Packages . . . . . . .
140/S5°C/W
vcc to Ground
Figure 1a. AD558 Pin Configuration (DIP)
ii
NC
eo
NO CONNECT
~ ~ I~ I~
~
!
Figure 1b. AD558 Pin Configuration (PLCC and LCC)
AD558 ORDERING GUIDE
Model
Package
Options·
AD558JN
AD558JP
AD558JD
AD558KN
AD558KP
AD558KD
AD558SD
AD558SE
AD558TD
AD558TE
Plastic (N-16)
PLCC(P-20A)
TO-116(D-16)
Plastic (N -16)
PLCC (P-20A)
TO-116 (D-16)
TO-116(D-16)
LCC(E-20)
TO-l 16(D-16)
LCC(E-20)
Relative Accuracy
Error Max
Full-Scale
Error, Max
Temperature
TmintoTmax
Tmin10 Tmax
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
- 55°e to + 125°e
- 55°C to + 125°C
- 55°C to + 125°e
- 55°C to + 125°C
:!: 1I2LSB
:!: 1I2LSB
:!: 1I2LSB
:!: 1I4LSB
:!: 1I4LSB
:!: 1I4LSB
±3/4LSB
±3/4LSB
±3/8LSB
±3/8LSB
:!:2.5LSB
:!:2.5LSB
:!:2.5LSB
:!: 1LSB
:!:ILSB
:!:ILSB
±2.5LSB
±2.5LSB
±ILSB
±ILSB
·See Section 14 for package outline information.
DIGITAL-TO-ANALOG CONVERTERS 2-49
•
The high-speed output buffer amplifier is operated in the noninverting mode with gain determined by the user-connections
at the output range select pin. The gain-setting application
resistors are thin-film laser-trimmed to match and track the
DAC resistors and to assure precise initial calibration of the'
two output ranges, OV to 2.S6V and OV to 10V. The amplifier
output stage is an NPN transistor with passive pull-down for
zero-based output capabiliry with a single power supply.
(continued from features page)
7. The single-chip, low power 12L design of the ADSS8 is
inherently more reliable than hybrid multi-chip or conventional single-chip bipolar designs. The ADSS8S and T
grades which are specified over the -55°C to +12S oC
temperature range, are available processed to MIL-STD883, Class B.
8. All ADSS8 grades are available in chip form with guaranteed specifications from +2SoC to Tmax. MIL-STD-883,
Class B visual inspection is standard on Analog Devices
bipolar chips. Contact the factory for additional chip
information.
CIRCUIT DESCRIPTION
The ADSS8 consists of four major functional blocks, fabricated on a single monolithic chip (see Figure 2). The main
D to A converter section uses eight equally-weighted laser-trimmed current sources switched into a silicon-chromium thinfilm R/2R resistor ladder network to give a direct but unbuffered OmV to 400mV output range. The transistors that form
the DAC switches are PNPs; this allows direct positive-voltage
logic interface and a zero-based output range.
CONTROL
INPUTS
~
cs
MIL-STD-883
The rigors of the military/aerospace environment, temperature
extremes, humidity, mechanical stress, etc., demand the utmost
in electronic circuits. The ADSS8, with the inherent reliability
of integrated circuit construction, was designed with these
applications in mind. The hermetically-sealed, low profile
DIP package takes up a fraction of the space required by
equivalent modular designs and protects the chip from hazardous environments. To further ensure reliability, militarytemperature range ADS 58 grades S and T are available screened
to MIL-STD-883. For more complete data sheet information
consult the Analog Devices' Military Databook.
DIGITAL INPUT DATA
r-------~.------~.
LSB
MSB
CE
+Vcc
GND
GND
)' ~ ~
VOUT
VoUT SENSE
'--+'Nr-(
The internal precision voltage reference is of the patented
band1!ap type. This design produces a reference voltage of 1.2
volts and thus, unlike 6.3 volt temperature-compensated zeners,
may be operated from a single, low-voltage logic power supply.
The microprocessor interface logic consists of an 8-bit data
latch and control circuitry. Low-power, small geometry and
high-speed are advantages of the 12L design as applied to this
section. 12 L is bipolar process compatible so that the performance of the analog sections need not be compromised to provide on-chip logic capabilities. The control logic allows the
latches to be operated from a decoded microprocessor address and write signal . .!!j:he a~cation does not involve a
p.P or data bus, wiring CS and CE to ground renders the latches
"transparent" for direct DAC access.
'louT seLECT
Figure 2. AD558 Functional Block Diagram
CHIP AVAILABILITY
The ADSS8 is available in laser-trimmed, passivated chip form.
ADSS8J and ADSS8T chips are available. Consult the factory
for details.
Output Voltage
Digital Input Code
Binary
Hexadecimal
00000000
00000001
00000010
00001111
00010000
01111111
10000000
11000000
11111111
00
01
02
OF
10
7F
80
CO
FF
Decimal
0
1
2
15
16
127
128
192
25S
Input Logic Coding
2-50 DIGITAL-TO-ANALOG CONVERTERS
2.S6V Range
10.OOV Range
0
0.010V
0.020V
0.lS0V
0.160V
1.270V
1.280V
1.920V
2.S5V
0
0.039V
0.078V
0.S86V
0.625V
4.961V
5.000V
7.500V
9.961V
Applications AD558
CONNECTING THE ADSS8
The ADS58 has been configured for ease of application. All
reference, output amplifier and logic connections are made
internally. In addition, all calibration trims are performed at
the factory assuring specified accuracy without user trims. The
only connection decision that must be made by the user is a
single jumper to select output voltage range. Clean circuit·
board layout is facilitated by isolating all digital bit inputs on
one side of the package; analog outputs are on the opposite side.
Figure 3 shows the two alternative output range connections.
The OV to 2.56V range may be selected for use with any
power supply between +4.5V and +16.5V. The OV to 10V
range requires a power supply of +l1.4V to +16.SV.
Because of its precise factory calibration, the ADS 58 is intended to be operated withou t user trims for gain and offset;
therefore no provisions have been made for such user-trims.
If a small increase in scale is required, however, it may be accomplished by slightly altering the effective gain of the output
buffer. A resistor in series with VOUT SENSE will increase the
output range.
GROUNDING AND BYPASSING"
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the AD558 is intended for application in microcomputer systems where digital noise is prevalent, special care must
be taken to assure that its inherent precision is ~ealized.
The ADSS8 has two ground (common) pins; this minimizes
ground drops and noise in the analog signal path. Figure S
shows how the ground connections should be made.
It is often advisable to maintain separate analog and digital
grounds throughout a complete system, tying them common
in one place only. If the common tie-point is remote and accidental disconnection of that one common tie-point occurs
due to card removal with power on, a large differential voltage between the two commons could develop. To protect devices that interface to both digital and analog parts of the
system, such as the AD558, it is recommended that common
ground tie-points should be provided at each such device. If
only one system ground can be connected directly to the
AD558, it is recommended that analog common be selected.
~
'5 Vour SENSE
I
VOUT SELECT...
14
I
t8EE NEXT
PAGE)
,
RI..
13 GND
k--t-----~
a. OV to 2.56V Output Range
b. OV to 10V Output Range
O.1pF
TO SYSTEM GND
TO SYSTEM GND
(SEE TEXT)
...:::==---__
TO SYSTEM Vee
+Vcc
11'11'
Figure 3. Connection Oiagrams
For example if a OV to 10.24V output range is desired (4OmV
= 1LSB), a nominal resist•. nce of 8S0n is required. It must be
remembered that, although the internal resistors all ratiomatch and track, the absolute tolerance of these resistors is
typically ±20% and the absolute TC is typically -SOppmtC
(0 to -100ppm/oC). That must be considered when re-scaling
is performed. Figure 4 shows the recommended circuitry for a
full-scale output range of 10.24 volts. Internal resistance values
shown are nominal.
NOTE: Decreasing the scale by putting a resistor in series with
GND will not work properly due to the code-dependent currents in GND. Adjusting offset by injecting dc at GND is not
recommended for the same reason.
>~~--~_VOUT
604n
Figure 4. 10.24V Full-Scale Connection
Figure 5. Recommended Grounding and Bypassing
POWER SUPPLY CONSIDERATIONS
The ADS58 is designed to operate from a single positive power
supply voltage. Specified performance is achieved for any supply voltage between +4.5V and +16.SV. This makes the
AD558 ideal for battery-operated, portable, automotive or
digital main-frame applications.
The only consideration in selecting a supply voltage is that, in
order to be able to use the OV to 10V output range, the power
supply voltage must be between +11.4Vand +16.5V. If, however, the OV to 2.56V range is to be used, power consumption
will be minimized by utilizing the lowest available supply
voltage (above +4.5V).
TIMING AND CONTROL
The ADS 58 has data input latches that simplify interface to
8- and 16-bit data buses. These latches are controlled by Chip
Enable (CE) and Chip Select (CS) inputs. CE and CS are internally "NORed" so that the latches transmit input data to the
DAC section when both CE and CS are at Logic "0". If the
application does not involve a data bus, a "00" condition
allows for direct operation of the DAC. When either CE or
CS go to Logic" 1". the input data is latched into the registers
·For additional insight. "An IC Amplifier Users' Guide to Decoupling.
Grounding and Making Things Go Right For A Change", is available
at no charge from any Analog Devices Sales Office.
DIGITAL-TO-ANALOG CONVERTERS 2-51
•
and held until both CEand CS return to "0". (Unused CE or
CS inputs should be tied to ground.) The truth table is given
in Table I. The logic function is also shown in Figure 6.
Input Data
CE
CS
DACData
o
0
0
0
0
~
~
0
1
X
0
0
~
~
0
0
1
X
X
o
1
o
Notes:
Latch
Condition
"transparent"
I'transparent"
0
latching
1
latching
0
latching
1
latching
previous data latched
previous data latched
X
X = Does Dot matter
.J: =Logic Threshold at Positive-Going Transition
USE OF VOUT SENSE
Separate access to the feedback resistor of the output amplifier allows additional application versatility. Figure 8a shows
how I X R drops in long lines to remote loads may be cancelled
by putting the drops "inside the loop." Figure 8b shows how
the separate sense may be used to provide a higher output
current by feeding back around a simple current booster.
VOUTSENSE
=r
OVTO+1OV
vaUT
RL
a. Compensation for I x R Drops in Output Lines
Vee
Table I. AD558 Control Logic Truth Table
r=:::.:.-==-"*-- ov
VOUT
I
INPUTDATA~
1~
: I
I
~'-----i,----
OACOATA
Figure 6. AD558 Control Logic Function
In a level-triggered latch such as that in the ADSS8 there is
an interaction between data setup and hold times and the
width of the enable pulse. In an effort to reduce the time
required to test all possible combinations in production. the
ADSS8 is tested with tDS = tw = 200ns at 2SoC and 270ns at
Tmin and Tmax. with tDH = 10ns at all temperatures. Failure
to comply with these specifications may result in data not
being latched properly.
TO +2.56V
b. OUtput Current Booster
Figure 8. Use of VOUT Sense
OPTIMIZING SETTLING TIME
In order to provide single-supply operation and zero-based
output voltage ranges. the ADSS8 output stage has a passive
"pull-down" to ground. As a result. setding time for negativegoing output steps may be longer than for positive-going output steps. The relative difference depends on load resistance
and capacitance. If a negative power supply is available. the
negative-going setding time may be improved by adding a pulldown resistor from the output to the negative supply as shown
in Figure 9. The value of the resistor should be such that. at
zero voltage out. current through that resistor is 0.5mA max.
Figure 7 shows the timing for the data and control signals;
CE and CS are identical in timing as well as in function.
AD558
~::fos==~.i
'-2,OV
~~
DATA
,
INPUTS~
----
tw
I
\~ tw
CSo.CE_
..._v__
OAe
V OUTPUT
.:_
I
~
==1'----
-- -------~---
~
r'~um
=
STROBE PULSE WIDTH = 225ns min
tot. ""' DATA HOLD TIME .., 10ns min
los = DATA SETUP nME = 2Z5ns min
tamuNo .., DAC OVTPUT SETIUNO 11;ME TO ± 112 LSB
Figure 7. AD558 Timing
2-52 DIGITAL-TO-ANALOG CONVERTERS
Figure 9. Improved Settling Time
BIPOLAR OUTPUT RANGES
The AD5S8 was designed for operation from a single power
supply and is thus capable of providing only unipolar (OV to
+2.56 and OV to 10V) output ranges. If a negative supply is
available. bipolar output ranges may be achieved by suitable
output offsetting and scaling. Figure 10 shows how a ±1.28
volt output range may be achieved when a -S volt power supply is available. The offset is provided by the AD589 precision
1.2 volt reference which will operate from a +S volt supply.
The ADS44 output amplifier can provide the necessary ±1.28
volt output swing from ±S volt supplies. Coding is complementary offset binary.
Applying the AD558
Skll
-5V
INPUT CODe
VOUT
OOOOOOOD
10000000
11111111
+128V
OV
-1.21V
INTERFACING THE ADSSS TO MICROPROCESSOR DATA
BUSES
The ADSS8 is configured to act like a "write only" location
in memory that may be made to coincide with a read only
memory location or with a RAM location. The latter case
allows data previously written into the DAC to be read back
later via the RAM. Address decoding is partially complete for
either ROM or RAM. Figure 12 shows interfaces for three
popular microprocessor systems.
Figure 10. Bipolar Operation of AD558 from ± 5V
Supplies
MEASURING OFFSET ERROR
One of the most commonly specified end-poillt errors
associated with real-world non ideal DACs is offset error.
In most DAC testing, the offset error is measured by applying
the zero-scale code and measuring the output deviation from
o volts. There are some DACs,like the AD558 where offset
errors may be present but not observable at the zero scale,
because of other circuit limitations (such as zero coinciding
with single-supply ground) so that a nonzero output at zero
code cannot be read as the offset error. Factors like this make
testing the ADS 58 a little more complicated.
By adding a pulldown resistor from the output to a negative
supply as shown in Figure II, we can now read offset errors
at zero code that may not have been observable due to circuit
limitations. The value of the resistor should be such that, at
zero voltage out, current through the resistor is O.5mA max.
R/W~ ~
GATED DECODED ADDRESS
-+
n
a_ 6800/AD558 Interface
SOSOA
DATA BUS
MrnW~~
DECODED ADDRESS SELECT PULSE'" B'
b_ 8080A/AD558Interface
a. OV to 2.56V Output Range
b. OV to 10V Output Range
Figure ". Offset Connection Diagrams
CDP 1802: MWR -+ EE"
DECODED ADORESS SELECT PULSE
a
c. 1802/AD5581nterface
Figure 12. Interfacing the AD558 to Microprocessors
-+
DIGITAL- TO-ANALOG CONVERTERS 2-53
AD558 Performance
LSB
1.75
1.50
1.25
1.00
0.75
0.50
0.25
FULL
SCALE
ERROR
0
-0.25
-0.50
-0.75
-1.00
(typical @ +25"&, Vee ± +5Y to +15Y unless otheIwise notad)
DATA INPUT,
TTL LEVELS
- - ALLAD558
- - - - AD558S. T
....
-1-1
:.... "·11
·-
..
I
-
I
n II
r.4111
VOUT,
, .. ..
1 LSB/DIV
,
•......1-., 1.
. ...
-
.= =
II
~-"
HORIZONTAL: 200ns/DIV
-55
-25
0
+25
+50 +75 +100 +125
·C
1LSB = 0.39% OF FULL-SCALE
Figure 16. .AD558 Settling Characteristic Detail
OV to 2.56V Output Range Full-Scale Step
Figure 13. Full-Scale Accuracy vs. Temperilture
Performance of AD558
DATA INPUT,
TTL LEVELS
LSB
- - - ALL AD558
- - - - AD558S. T
1/2
ZERO
ERROR
1/4
...... ...... ...
-_ .. .. .
~
0
-55 -25
+25
0
VOUT •
1/2LSB/DIV
+75 +100 +125
+50
·C
-1/4
HORIZONTAL: 500nslDlV
-1/2
1LSB = 0.39% OF FULL-SCALE
Figure 17. AD558 Settling Characteristic Detail
OV to 10V Output Range Full-Scale Step
Figure 14. Zero Drift vs. Temperature Performance
ofAD558
cs AND CE
mA
STROBE PULSE
16
DATA IN.
ALL BITS
----------
14
Icc
12
10
VOUT.
OVTO 2.56V
RANGE
HORIZONTAL: 1OOns/DIV
Figure 18. AD558 Logic Timing
4
6
8
10
12
14
16
18 i VOLTS
Vee
Figure 15. Quiescent Current VB. Power Supply
Voltage for AD558
2-54 DIGITAL-TO-ANALOG CONVERTERS
ANALOG
WDEVICES
11IIIIIIII
FEATURES
Complete Current Output Converter
High Stability Buried Zener Reference
Laser Trimmed to High Accuracy (1/4LSB Max Error,
AD561K,T)
Trimmed Output Application ResistorsforOto +10,:t:5
Volt Ranges
Fast Settling - 250ns to 112LSB
Guaranteed Monotonicity Over Full Operating
Temperature Range
TTUDTL and CMOS Compatible (Positive True Logic)
Single Chip Monolithic Construction
Available in Chip Form
PRODUCT DESCRIPTION
The ADS 61 is an integrated circuit 10-bit digital-to-analog
converter combined with a high stability voltage reference
fabricated on a single monolithic chip. Using 10 precision highspeed current-steering switches, a control amplifier, voltage
reference, and laser-trimmed thin-film SiCr resistor network,
the device ptoduces a fast, accurate analog output current.
Laser trimmed output application resistors are also included to
facilitate accurate, stable current-to-voltage conversion; they
are trimmed to 0.1 % accuracy, thus eliminating external trimmers in many situations.
Several important technologies combine to make the ADS61
the most accurate and most stable 10-bit DAC available. The
low temperature coefficient, high stability thin-film network
is trimmed at the wafer level by a fine resolution laser system
to 0.01% typical linearity. This results in an accuracy specification of ±1I4LSB max for the K and T versions, and 1I2LSB
max for the J and S versions.
The ADS61 also incorporates a low noise, high stability subsurface zener diode to ptoduce a reference voltage with excellent
long term stability and temperature cycle characteristics which
challenge the best discrete zener references. A temperature
compensation circuit is laser-trimmed to allow custom correction of the temperature coefficient of each device. This results
in a typical full-scale temperature coefficient of lSppmtC; the
T.C. is tested and guaranteed to 30ppmtC max for the K and
T versions, 60ppm/oC max for the S, and 80ppm/oC for the J.
The ADS6I is available in four performance grades. The
ADS61J and K are specified for use over the 0 to +70oC
Low Cost 10-Bit
Monolithic OfAConverter
AD561* I
ADS61 FUNCTIONAL BLOCK DIAGRAM
TO-116
BIPOLAR
OFFSET
RFB
temperature range and are available in either a 16-pin
hermetically-sealed ceramic DIP or a 16-pin molded plastic
DIP. The ADS61S and T grades are specified for the -SSoC
to +12SoC range and are available in the ceramic package.
PRODUCT HIGHLIGHTS
1. Advanced monolithic processing and laser trimming at the .
wafer level have made the ADS61 the most accurate IO-bit
converter available while keeping costs consistent with large
volume integrated circuit production. The ADS61K and T
have 1I4LSB max relative accuracy and 1I2LSB max differential nonlinearity. The low T.e. R-2R ladder guarantees
that all ADS61 units will be monotonic over the entire
operating temperature range.
2. Digital system interfacing is simplified by the use of a positive true straight binaty code. The digital input voltage
threshold is a function of the positive supply level; connecting VCC to the digital logic supply automatically sets the
threshold to the proper level for the logic family being used.
Logic sink current requirement is only 2SJ.lA.
3. The high speed current steering switches are designed to
settle in less than 2S0ns for the worst case digital code
transition. This allows construction of successive-approximation AID converters in the 3 to SJ.ls range.
4. The ADS61 has an output voltage compliance range from
-2 to + 10 volts, thus allowing direct current-to-voltage
conversion with just an output resistor, omitting the op amp.
The 40Mil open collector output impedance results in negligible errors due to output leakage currents.
• Covered by Patent Nos•• 3,940,760,3,747,088, RE 28,633,
3,803,590; RE 29,6191 3,961,32614,141,004; 4,213,8061
4,136,349.
DIGITAL-TO-ANALOG CONVERTERS 2-55
•
SPEC IFICAli 0NS
(fA
= + 25"1:, Vee = +5V, VEE = -15V, unless otherwise specified)
MIN
MODEL
AD561J
TYP
RESOLUTION
10 Bits
ACCURACY (Error Relative
to Full Scale)
t1l4
(0.02S)
DIFFERENTIAL NONLINEARITY
tl/2
DATA INPUTS
TTL, Vee = +SV
Bit ON Logic "1"
+2.0
Bit OFF Logic "0"
CMOS, 10V 0;;;; Vee 0;;;; 16.SV
Bit ON Logic "1"
70%Vcc
Bit OFF Logic "0"
Logic Current (Each Bit) (Tmio to Tmax)
Bit ON Logic" 1"
Bit OFF Logic "0"
OUTPUT
Current
Unipolar
Bipolar
Resistance (Exclusive of
Application Resistors)
Unipolar Zero (All Bits OFF)
Capacitance
Compliance Voltage
MAX
UNITS
MAX
tllS
(0.012)
t1l4
(0.02S)
LSB
%ofF.S.
t1l4
t1l2
LSB
•
V
V
•
V
V
•
•
•
•
J.LA
•
•
•
•
•
•
•
•
+O.S
•
30% Vee
+100
-2S
to.7S
2.0
t1.0
2.4
t1.2
-2
40M
0.01
2S
-3
SETTLING TIME TO 1I2LSB
All Bits ON-to-oFF or OFF-to-oN
AD561K
TYP
10 Bits
tl12
(O.OS)
+S
-S
1.S
MIN
•
•
O.OS
+10
•
·•
•
•
2S0
nA
rnA
rnA
n
%ofF.S.
pF
V
ns
POWER REQUIREMENTS
Vcc' +4.SV dc to +16.SV dc
VEE' -10.SV dc to -16.SV dc
POWER SUPPLY GAIN SENSITIVITY
Vcc' +4.SV dc to +16.SV dc
VEE' -10.SV dc to -16.SV dc
S
12
10
16
·•
·•
2
4
10
2S
•
•
•
•
ppm of F.S.I%
ppmofF.S.I%
TEMPERATURE RANGE
Operating
Storage ("D" Package)
(UN" Package)
o to +70
-6S to +lS0
-2S to +SS
·•
•
•
•
•
°c
°c
°c
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Full Scale
Differential Nonlinearity
1
2
IS
2.S
1
2
IS
2.S
S
10
30
ppmofF.Sfc
ppmofF.Sfc
ppmofF.Sfc
ppmofF.Sfc
MONOTONICITY
10
20
SO
Guaranteed over full
operating temp. range
rnA
rnA
Guaranteed over full
operating temp. range
PROGRAMMABLE OUTPUT
RANGES
o to +10
-S to +S
•
•
V
V
CALIBRATION ACCURACY
Full Scale Error with Fixed 2Sn
Resistor
Bipolar Zero Error with Fixed IOn
Resistor
to.1
•
% of F.s.
to.1
•
%ofF.s.
to.S
to.5
•
•
%ofF.S.
% of F.s.
CALIBRATION ADJUSTMENT
RANGE
Full Scale (With soO Trimmer)
Bipolar Zero (With son Trimmer)
NOTES
'Specifications same as AD561J specs.
Specifications subject to cbange without notice.
2-56 DIGITAL-TO-ANALOG CONVERTERS
AD561
MIN
MODEL
AD561S
TYP
RESOLUTION
10 Bits
ACCURACY (Error Relative
to Full Scale)
±1/4
(0.025)
DIFFERENTIAL NONLINEARITY
±112
DATA INPUTS
TTL. Vee =+5V
+2.0
Bit ON Logic "I"
Bit OFF Logic "0"
CMOS. 10V";Vee "; 16.5V
Bit ON Logic "I"
70% Vee
Bit OFF Logic "0"
Logic Current (Each Bit) (Tmin to Tmax)
Bit ON Logic "I"
Bit OFF Logic "0"
OUTPUT
Current
Unipolar
Bipolar
Resistance (Exclusive of
Application Resistors)
Unipolar Zero (All Bits OFF)
Capacitance
Compliance Voltage
SETTLING TIME TO 1I2LSB
All Bits ON-to-oFF or OFF-to-oN
POWER REQUIREMENTS
Vee. +4.5V dc to +16.5V dc
VEE' -10.8V dc to -16.SV dc
MAX
+20
-25
+100
-100
1.5
±0.75
2.0
±l.0
2.4
±l.2
-2
40M
0.01
25
-3
0.05
+10
250
POWER SUPPLY GAIN SENSITIVITY
Vee. +4.5V dc to +16.5V dc
VEE' -10.8V dc to -16.5V dc
2
4
10
25
TEMPERATURE RANGE
Operating
Storage
-SS to +125
-6S to +150
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Full Scale
Differential Nonlinearity
1
2
15
2.5
10
20
60
Guaranteed over full
operating temp. range
PROGRAMMABLE OUTPUT
RANGES
o to +10
-5 to +5
CALIBRATION ACCURACY
Full Scale Error with Fixed 25n
Resistor
Bipolar Zero Error with Fixed IOn
Resistor
±0.1
±0.1
±O.S
±0.5
UNITS
±114
(0.025)
LSB
%ofF.S.
±114
±112
LSB
••
V
V
..
30% Vee
6
MAX
±118
(0.012)
••
+0.8
10
16
CALIBRATION ADJUSTMENT
RANGE
Full Scale (With son Trimmer)
Bipolar Zero (With son Trimmer)
AD561T
TYP
10 Bits
±112
(0.05)
11
MONOTONICITY
MIN
..••
..•• ....
....
....
••
..
....
....
..••
1
2
15
2.5
..
..
••
..••
..
..
....
..••
V
V
nA
IJA
mA
mA
n
% ofF.S .
pF
V
ns
mA
mA
ppm of F .S.I%
ppm of F .S.I%
••
••
°c
°c
5
ppm of F.S./C
ppm of F.S./C
ppm of F.S./C
ppm ofF.S./C
10
30
Guaranteed over full
operating temp. range
....
..
..
....
V
V
%ofF.s.
% ofF.S.
% of F.S.
%ofF.S.
NOTES
··Specifications same as ADS61S specs.
SpecificatioDs subject to change without notice.
DIGITAL-TO-ANALOG CONVERTERS 2-57
II
CIRCUIT DESCRIPTION
A simplified schematic with the essential circuit features of the
ADS61 is shown in Figure 1. The voltage reference, CR1, is a
buried zener (or subsurface breakdown diode). This device exhibits far better all-around performance ·than the NPN baseemitter reverse-breakdown diode (surface zener), which is in
nearly universal use in integrated circuits as a voltage reference.
Greatly improved long term stability and lower noise are the
major benefits the buried zener derives from isolating the
breakdown point from surface stress and mobile oxide charge
effects. The nominal 7.5 volt device (including temperature
compensation circuitry) is driven by a current source to the
negative supply so that the positive supply can be allowed to
go as low as 4.5 volts. The temperature coefficient of each
diode is determined individually; this data is then used to laser
trim a compensating circuit to balance the overall T .C. to zero.
The typical resulting T.C. is 0 to ±1Sppm/oC.
The negative reference level is invetted and scaled by A 1 to give
a +2.5 volt reference (which can be driven by the low positive
supply). The ADS61, packaged in the 16-pin DIP, has the +2.S
volt reference (REF OUT) connected directly to the input of
the control amplifier (REF IN). The buffered reference is not
directly available externally except through the 2.SkU bipolar
offset resistor.
The 2.SkU scaling resistor and control amplifier A2 then force
a 1mA reference current to flow through reference transistor
Q1, which has a relative emitter area of 8A. This is accom-
plished by forcing the bottom of the ladder to the proper voltage.
Since Ql and U2 have equal emitter areas and have equal SkU
emitter resistors, U2 also carries 1mA. The ladder voltage drop
constrains Q7 (with area 4A) to carty only O.5mA; Qg carries
0.2SmA, etc.
The first four significant bit cells are scaled exactly in emitter
area to match Ql for optimum VBE and VBE drift match, as
well as for beta match. These effects are insignificant for the
lower order bits, which account for a total of only 1/16 of full
scale. However, the 18mV VBE difference between two
matched transistors carrying emitter currents in a ratio of 2: 1
must be corrected. This is done by forcing 120J.(A through the
1S0U interbase resistors. These resistors and the R-2R ladder
resistors are actively laser-trimmed at the wafer level to bring
total device accuracy to better than 1I4LSB. Sufficient ratio
accuracy in the last two bits is obtained by simple emitter area
ratio such that it is unnecessaty to use additional area for
ladder resistors. The current in Q16 is added to the ladder to
balance it properly but is not switched to the output; thus full
scale is 1023/1024 x 2mA.
The switching cell of U3 ' <4, Us and U6 serves to steer the
cell current either to ground (BIT 1 low) or to the DAC output
(BIT 1 high). The entire switching cell carries the same current
whether the bit is on or off, thus minimizing thermal transients
and ground current errors. The logic threshold, which is generated from the positive supply (see Digital Logic Interface) is
applied to one side of each cell.
Fif1ure. 1. Circuit Diagram Showing Reference, Control Amplifier, Switching Cell, R-2R Ladder, and Bit Arrangement ofAD561
PIN CONFIGURATION
TOP VIEW
ADS61 ORDERING GUIDE
,.v
GROUND
1
SPAN
RESISTOR
BIPOLAR
OFFSET
2
OUTPUT
[~
Vee (+5V)
..
81T9
DIGITAL
LOGIC
INPUTS
MODEL
""J
BIT2
5
BIT3
DIGITAL
LOGIC
INPUTS
BIT4
ADS61]D
ADS61]N
ADS61KD
ADS61KN
ADS61SD
ADS61TD
TEMP RANGE
o to +70oC
o to +70oC
o to +70oC
o to +70oC
-SS to +12Soc
-SS to +12SoC
ACCURACY
@+2S°C
GAINT.C.
(ofF.S./C)
PACKAGE
OPTIONS·
±~LSB
80ppm max
80ppm max
30ppm max
30ppmmax
60ppm max
30ppm max
D-16
N-16
D-16
N-16
D-16
D-16
max
max
±14LSB max
±14LSB max
±~LSB max
±14LSB max
±~LSB
BIT5
• See Section 14 for package outline information.
Figure 2.
2-58 DIGITAL-TO-ANALOG CONVERTERS
Ie 12-Bit
OfAConverters
A0562fA0563* I
11IIIIIIII ANALOG
WDEVICES
FEATURES
True 12-Bit Accuracy
Guaranteed Monotonicity Over Full Temperature Range
Hermetic 24-Pin DIP
TTL/DTL and CMOS Compatibility
Positive True Logic
ADS62, ADS63 PIN CONFIGURATIONS
Vee +5V/+1SV IN
(lSmA)
CMOS/TTl
REF. V LO IN
A unique combination of advanced circuit design, high stability SiCr thin film resistor processing and laser trimming
technology provide the ADS621ADS63 with true 12-bit
accuracy. The maximum error at +2S o C is limited to ±Y..LSB
on all versions and monotonicity is guaranteed over the full
operating temperature range.
The ADS62 and ADS63 are recommended for high accuracy
12-bit D/A converter applications where true 12-bit performance is required, bu t low cost and small size are considerations. Both devices are also ideal for use in constructing AID
conversion systems and as building blocks for higher resolution D/A systems. J and K versions are specified for operation over the 0 to +70o C temperature range, the Sand T for
operation over the extended temperature range, _SSoC to
+12S o C. All are packaged in a 24-pin, hermetically sealed,
ceramic, dual-in-line package.
3. The devices incorporate a newly developed and fully differential, non-saturating precision current switching cell
structure which provides increased immunity to supply
voltage variation and also reduces nonlinearities due to
thermal transients as the various bits are switched; nearly
all critical components operate at constant power dissipation.
BIT 3 IN
BIT4 IN
BIT 5 IN
5
•
BIT6 IN
BIPOLAR OFFSET R IN
7
BIT7 IN
BIPOLAR OFFSET ROUT
8
BIT8 IN
•
BIT9 IN
VEE -15V IN
(20mA)
OAe OUT t-2mA F,S.)
10V SPAN R
BIT 10 IN
20V SPAN R 11
BIT 11 IN
BIT 12 (LSB) IN
GND
Vee +5V/+15V IN
,
BIT 1 (MSB) IN
•
CMOS/TTL
LOGIC THRESHOLD
REFERENCE SUPPLY IN
BIT 2 IN
BIT 3 IN
3
REFERENCE OUT
(+2.5V:t3%1
BIT4 IN
BITS IN
REF GND
5
REFERENCE IN
6
AD563
BITS IN
VeE -15V
7
TOP VIEW
INot to Scalel
BIT 7 IN
BIPOLAR OFFSET IN
8
BITS IN
DAC OUT
9
BIT9 IN
(~2mA
F.S.l
10VSPAN R
BIT 10 IN
20V SPAN R 11
BIT 11 IN
GND
PRODUCT HIGHLIGHTS
1. The ADS62 multiplies in two quadrants when a varying
reference voltage is applied. When multiplication is not
required, the ADS63 is recommended with its internal
low drift voltage reference.
2. True 12-bit resolution is achieved with guaranteed monotonicity over the full operating temperature range. Voltage outputs are easily implemented by using an external
operational amplifier and the ADS621ADS63s internally
provided feedback resistors.
BIT2 IN
3
AMP SUMMING
JUNCTION
REF. V HI IN
PRODUCT DESCRIPTION
The ADS621ADS63 are monolithic 12-bit digital-to-analog
converters consisting of especially designed precision bipolar
switches and control amplifiers and compatible high stability
silicon chromium thin film resistors. The ADS63 also includes
its own internal voltage reference.
1
LOGIC THRESHOLD
BIT 12 (lSB)IN
4. The thin film resistor network contains gain, range, and
bipolar offset resistors so that various output voltage
ranges can be programmed by changing connections to
the device terminal leads. Thin film resistors are laser
trimmed while the device is powered to accurately calibrate all scale factors. The scale factors are dependent
upon the tracking coefficient «±2ppm/°C) of these resistors, rather than upon their absolute temperature
coefficients.
S. TTL or CMOS input can be accommodated for supply
voltages from +SV to +lSV.
6. Positive true logic eliminates the need for additional inverter components.
·Covered by Patent NOI. 3,961,326,4,141,004,3,747,088, RE 28,633,
3,803,590,4,020,486, the AD563 io ..... covered by 4,213,806,
4,136,349.
DIGITAL-TO-ANALOG CONVERTERS 2-59
•
SPECIFICATIONS
(fA
= + 25"1:, unless otherwise specified)
AD562KD/BIN
ADS62KD/BCD
MODEL
DATA INPUTS {positive True, Binary
(BCD) and Offset Binary (BCD»
TTL, Vee = +5V, Pin 2
Open Circuit
Bit ON Logic "I"
Bit OFF Logic uO"
CMOS, 4.75 ';;Vee ';;15.8,
Pin 2 Tied to Pin 1
Bit ON Logic "I"
Bit OFF Logic "0"
Logic Current (Each Bit)
Bit ON Logic "I"
Bit OFF Logic "0"
+2.0V
+0.8V max
70%Vee min
30%Vee max
+ 20nA typ, +1 OOnA max
-SOI'A typ, -IOOI'A max
OUTPUT
Current
Unipolar
Bipolar
Resistance (Exclusive of
Span Resistors)
Unipolar Zero (All Bi~s OFF)
Capacitance
Compliance Voltage
S.3Hl min, 6.6kn typ, 7.9kn max
0.01% of F.S. typ, 0.05% of F.S. max
33pF typ
-1.SV to +IOV typ
RESOLUTION
Binaty
BCD
12 Bits
3 Digits
ACCURACY (Error Relative
to Full Scale)
Binary
BCD
±1/2LSB max
±1I2LSB max
DIFFERENTIAL NONLINEARITY
±1I2LSB max
SETTLING TIME TO 1I2LSB
All Bits ON-ta-OFF or OFF-to'()N
LSI'S typ
POWER REQUIREMENTS
Vee' +4.75 to +IS.8V de
VEE' -ISV de ±S%
15mA typ, 18mA max
20rnA typ, 2SmA max
POWER SUPPLY GAIN SENSITIVITY
Vee @ +SV de
Vee @ +ISV de
VEE @-ISVde
TEMPERATURE RANGE
Operating
Storage
-1.6mA min, -2.OrnA typ, -2.4mA max
±0.8mA min, ±1.0mA typ, ±1.2mA max
2ppm of F .S.I% max
2ppm of F.S.I% max
6ppm of F.s.l% max
o to
+70°C typ
_65°C to +150o C typ
TEMPERATURE COEFFICIENT
Unipolar Zero
Bipolar Zero
Gain
Differential Nonlinearity
MONOTONICITY
EXTERNAL ADJUSTMENTS'
Gain Error with Fixed son Resistor
Bipol,ar Zero Error with Fixed
son Resistor
Gain Adjustment Range
Binary Bipolar Zer~ Adjustments
Range
BCD Bipolar Offset Adjustment
Range
PROGRAMMABLE OUTPUT
RANGES
2ppm of F.S.fC max
4ppm of F.S.fC max
Sppm of F.sfc max
2pptn of F.sfc
Guaranteed Over Full Operating
Temperature Range
±0.2% of F.S. typ
±O.I% ofF.S. typ
±0.2S% of F.S. typ
±0.2S% of F.S. typ
±0.17% of F.S. typ
o to
+SV typ
-2.SV to +2.SV typ
OV to + IOV typ
-SV to +SV typ
-IOV to + 10V typ
REFEKt;N<.;t;IN~UT
Input Impedance
20kn typ
AD562ADIBIN
ADS62ADIBCD
ADS62SDIBIN
AD562SD/BCD
··
··
··
··
··
··
··
··
··
··
··
··
··
···
±!l4LSB max
±!lIOLSB max
·
··
···
·
··
··
·
·
··
·
·
···
··
·
- 2S Q C to +8S o C
• Specifications same as AOS62KO. ··Specifications same as ADS63KO. ···Specifications same asADS63JD.
Specifica.tions subject to change without notice.
2-60 DIGITAL-TO-ANALOG CONVERTERS
··
·
·
··
··
·
·
··
·
·
·
··
·
·
···
··
·
_55°C to +125°C
Ippm of F.S.fC
1
Device calibrated with internal reference.
AD562/AD563
AD563JD/BIN
AD563JD/BCD
AD563KD/BIN
AD563KD/BCD
AD563SD/BIN
AD563SD/BCD
AD563TD/BIN
AD563TDIBCD
··
··
··
··
··
··
··
··
··
··
··
··
··
··
··
··
....
··
··
··
··
··
··
··
·
·
1 SmA typ. 20rnA max
·
lppm of F.S.I% typ. 10ppm of F.S.I% max
lppm of F.S'!% typ. 10ppm of F.S'!% max
14ppm of F.S'!% typ. 2Sppm of F.S'!% max
··
With Internal Reference
lppm of F.sfc typo 2ppm of F.sfc max
IOppm of F.S,!~C max
SOppm of F .S.! C max
··
With Fixed Ion Resistor
±0.2% of F.S. typ
··
·
·
···
·
·
sill typ
···
·
··
±1I4LSB
±1I4LSB
·
·
...
·
......
...
··
......
··
20ppm of F.sfc max
...
··
·
·
··
···
...
···
·
··
....
·
·...
·
...
·
·.....
...
·
...
......
-SS·C
·
......
··
...
··
·
·
··
···
to
+12S·C
30ppm of F.sfc max
...
II
-SS·C to +12S·C
·
......
··
...
··
·
IOppm of F.sfc max
·
··
··
·
...
OIGITAL-TO-ANALOG CONVERTERS 2-61
THE ADS621ADS63 OFFERS TRUE 12-BIT RESOLUTION
OVER FULL TEMPERATURE RANGE
UNIPOLAR DAC's
STEP I •.. OUTPUT RANGE
Determine the output range required. For +IOV F.S., connect the external operational amplifier output to Pin 10 and
leave Pin II unconnected. For +SV F.S., connect the external op amp output to Pin 10 and short Pin II to Pin 9.
Accuracy: Analog Devices defines accuracy as the maximum
deviation of the actual DAC output from the ideal analog
output (a straight line drawn from 0 to F.S. - ILSB) fOT
any bit combination. The AD563, for example, is laser
trimmed to '4LSB (0.006% of F.S.) maximum error at +2S oC
for K, Sand T versions ... YzLSB for the J version.
STEP" ... ZERO ADJUST
Turn all bits OFF and adjust R, until op amp output is 0
volts.
Monotonicity: A DAC is said to be monotonic if the output
either increases or remains constant for increasing digital inputs such that the output will always be a single-valued function of the input. All versions of the ADS621ADS63 are
monotonic over their full operating temperature range.
STEP III ... GAIN ADJUST
Turn all bits ON for binary DAC's (bits 1,4, 5,8, 9 and 12
ON for BCD DAC's). Adjust R2 until op amp output is:
BINARY
4.9988V for +SV Range
9.9976 for +IOV Range
Differential Nonlinearity: Monotonic behavior requires that
the differential nonlinearity error be < lLSB both at 25°C
and over the temperature range of interest. Differential nonlinearity is the measure of the variation in analog value, normalized to full scale, associated with a one LSB change in
digital input code. For example, for a IOV full-scale output,
a change of one LSB in the digital input code should result
in a 2.4mV change in the analog output (lOV x 114096 =
2.4mV). If in actual use, however, a one LSB change in the
input code results in a change of 1.3mV in analog output, the
differential nonlinearity would be 1.lm V, or 0.011% of F .S.
The differential nonlinearity temperature coefficient must also
be considered if the device is to remain monotonic over its full
operating temperature range. A differential nonlinearity temperature coefficient of Ippm/C could, under worst case conditions for a temperature change of +25°C to +12S oC, add
0.01 % (100°C x Ippm/C) of error. The resulting error could
then be as much as 0.006% + 0.01 % = 0.016% of F.S. (! LSB
represents 0.024% of FS.). All versions of the AD563 are
100% tested to be monotonic over the full operating temperature range.
BCD
4.9950 for +SV Range
9.9900 for +IOV Range
BIPOLAR DAC's
STEP I ... OUTPUT RANGE
Determine the output range required. For ±IOV F .S., connect the external op amp output to Pin II and leave Pin 10 unconnected. For ±SV F.S., connect the external op amp output to Pin 10 and leave Pin II unconnected. For ±2.5V F.S.,
connect the external op amp output to Pin 10 and short
Pin 11 to Pin 9.
STEP" ... OFFSET ADJUST
Turn all bits OFF and adjust R3 until op amp output is:
-2.S000V for ±2.SV Range
-S.OOOOV for ±SV Range
-IO.OOOOV for ±IOV Range
STEP III ... GAIN ADJUST (Bipolar Zero)
Turn bit I ON for Binary DAC's (bits 2 and 4 ON for BCD
DAC's). Adjust R2 until op amp output is 0 volts.
ORDERING GUIDE
MODEL
INPUT CODE
ADS62KD/BIN
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
ADS62KD/BCD
ADS62AD/BIN
ADS62AD/BCD
ADS62SD/BIN
AD562SD/BCD
AD563JD/BIN
AD563JD/BCD
ADS63KD/BIN
ADS63KD/BCD
ADS63SD/BIN
AD563SD/BCD
ADS63TD/BIN
ADS63TD/BCD
Coded Decimal
Coded Decimal
Coded Decimal
Coded Decimal
Coded Decimal
Coded Decimal
Coded Decimal
'See Section 14 for package outline information.
2-62 DIGITAL-TO-ANALOG CONVERTERS
TEMP.
RANGE
o to +70°C
o to +70 C
0
-25°C to +8S oC
-25°C to +85°C
-55°C to +12S oC
-55°C to +12S oC
o to +70 0 C
o to +70°C
o to +70°C
o to +70°C
-5SoC to +12SoC
-SSoC to +12SoC
-SSoC to +12SoC
-S 5° C to + 12So C
ACCURACY
@+2S oC
GAIN T.C.
(ofF.S./C)
PACKAGE
OPTION *
±1I2LSB max
±1I2LSB max
±II2LSBrmax
±1I2LSB max
±1/4LSB max
±1I10LSB max
±1I2LSB max
±1/2LSB max
±1/4LSB max
±1I4LSB max
±1/4LSB max
±1I4LSB max
±1I4LSB max
±1I4LSB max
5ppmmax
Sppm max
5ppm max
5ppm max
5ppm max
5ppm max
SOppm max
SOppm max
20ppm max
20ppm max
30ppm max
30ppm max
IOppm max
10ppm max
D-24
D-24
0-24
D-24
D-24
0-24
D-24
0-24
D-24
D-24
D-24
D-24
D-24
0-24
High-Speed 12-Bit
Monolithic OfAConverters
A0565A*fA0566A* I
~ANALOG
WDEVICES
FEATURES
Single Chip Construction
Very High-Speed Settling to 1/2LSB
AD565A: 250ns max
AD566A: 350ns max
Full-Scale Switching Time: 30ns
Guaranteed for Operation with ±12V Supplies: AD565A
with -12V Supply: AD566A
Linearity Guaranteed Over Temperature:
1/2LSB max (K, T Grades)
Monotonicity Guaranteed Over Temperature
Low Power: AD566A = 180mW max;
AD565A = 225mW max
Use with On-Board High-Stability Reference (AD565A)
or with External Reference (AD566A)
Low Cost
ADS65A FUNCTIONAL BLOCK DIAGRAM
REF our
Vee
BIPOLAR OFF
II
10V SPAN
REF
IN
OAC
OUT
- VEE
Pg:~R
MSB _ _ _ _ _ _..
_
LS8
ADS66A FUNCTIONAL BWCK DIAGRAM
BIPOLAR OFF
PRODUCT DESCRIPTION
The AD565A and AD566A are fast 12-bit digital-to-analog
converters which incorporate the latest advances in analog
circuit design to achieve high speeds at low cost_
The AD565A and ADS66A use 12 precision, high-speed
bipolar current-steering switches, control amplifier and a
laser-trimmed thin-film resistor network to produce a very
fast, high accuracy analog output current. The ADS6SA also
includes a buried zener reference that features low-noise,
long-term stability and temperature drift characteristics
comparable to the best discrete reference diodes.
The combination of performance and flexibility in the
ADS65A and AD566A has resulted from major innovations
in circuit design, an important new high-speed bipolar process, and continuing advances in laser-wafer-trimming techniques (LWT). The ADS65A and AD566A have a 10-90%
full-scale transition time less than 35ns and settle to within
±1I2LSB in 250ns max (350ns for AD566A). Both are
laser-trimmed at the wafer level to ±1/8LSB typical linearity
and are specified to ±1I4LSB max error (K and T grades) at
+.25°C. High speed and accuracy make the AD565A and
AD566A the ideal choice for high-speed display drivers as
well as fast analog-to-digital converters.
The laser trimming process which provides the excellent
linearity is also used to trim both the absolute value and the
temper:ture coefficient of the reference of the AD565A resulting in a typical full-scale gain TC of 10 ppmtC. When
tighter TC petformance is required or when a system reference is available, the AD566A may be used with an external
reference.
10V SPAN
REF
IN
OAC
OUT
- VEE
POWER MSB -
GNO
LSD
AD56SA and AD566A are available in four petformance
grades. The J and K are specified for use over the 0 to
+70°C temperature range while the Sand T grades are
specified for the -55°C to +125°C range. All are packaged
in a 24-pin, hermetically sealed, ceramic, dual-in-line package.
PRODUCT HIGHLIGHTS
1. The wide output compliance rang~ of the AD565A and
ADS66A are ideally suited for fast, low noise, accurate
voltage output configurations without an output amplifier.
2. The devices incorporate a newly developed, fully differential, nonsaturating precision current switching cell structure
which combines the dc accuracy and stability first developed
in the AD56213 with very fast switching times and an optimally-damped settling characteristic.
3. The devices also contain SiCr thin film application resistors
which can be used with an external op amp to provide a
precision voltage output or as input resistors for a successive approximation AID converter. The resistors are
matched to the internal ladder network to guarantee a low
gain temperature coefficient and are laser-trimmed for
minimum full-scale and bipolar offset errors.
·Covered by Patent Nos .• 3,803,590; RE 28,633; 4,213,806;
4,136,349; 4,020,486; 3,747,088.
DIGITAL-TO-ANALOG CONVERTERS 2-63
SPECIFICATIONS
MODEL
MIN
DATA INPUTS' (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic "I"
Bit OFF Logic "0"
Logic Current (each bit)
Bit ON Logic" I "
Bit OFF Logic "0"
+2.0
(fA
+25"1:, Vee =+ 15V, VEE =-l5V, unless otherwise specified)
AD565A]
TYP
+120
+35
MAX
MIN
+5.'
+0.8
+2.0
+300
+100
AD56'AK
TYP
+120
+35
12
RESOLUTION
MAX
UNITS
+5.5
+0.8
V
V
+300
+100
p.A
p.A
12
Bits
-2.4
±1.2
rnA
rnA
OUTPUT
Current
Unipolar (all bits on)
Bipolar (all bits on or off)
Resistance (exclusive of span
resistors)
Offset
Unipolar
Bipolar (Figure 3, R2 =
Capacitance
Compliance Voltage
-1.6
±0.8
6k
son fixed)
Tmin to Tmax
-2.0
il.O
-2.4
±1.2
-1.6
±D.8
8k
!Ok
6k
0.01
0.05
25
0.05
0.15
-1.5
ACCURACY (error relative to
full scale) +25°C
+10
±1I4
(0.006)
±1I2
(0.012)
Tmin to Tmax
-2.0
±l.O
8k
!Ok
n
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
+10
V
±1I4
(0.006)
±112
(0.012)
LSB
% of F.S. Range
LSB
-1.5
±1I8
(0.003)
±1I4
(0.006)
±1I2
(0.012)
±3/4
(0.018)
%ofF.s.R~e
DIFFERENTIAL NONLINEARITY
+2S o C
±1/2
±3/4
MONOTONICITY GUARANTEED
Tmin toTmax
±1I4
±1I2
MONOTONICITY GUARANTEED
LSB
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
I
5
IS
2
2
10
SO
I
5
10
2
2
10
20
pprn/oC
pprnt"C
pprnt"C
pprnt"C
SETTLING TIME TO 1I2LSB
All Birs ON-to-OFF or OFF-to-DN
250
400
250
400
ns
FULL SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
IS
30
30
50
IS
30
30
50
ns
n.
+70
+150
°c
°c
TEMPERATURE RANGE
Operating
Storage
0
-65
+70
+150
0
-65
POWER REQUIREMENTS
Vee. +11.4 to +16.5V de
VEE. -11.4 to -16.5V de
3
-12
5
-18
3
-12
S
-18
rnA
rnA
POWER SUPPLY GAIN SENSrflVITY
Vee = +11.4 to +16.5V de
VEE = -11.4 to -16.5V de
3
15
10
2S
3
15
10
25
ppm of F.S.I%
ppm of F.S.I%
PROGRAMMABLE OUTPUT
RANGE (see Figures 2, 3. 4)
o to +5
-2.' to +2.5
Oto+10
-5 to +5
-10 to +10
Oto+5
-2.5 to +2.5
o to +10
-5 to +5
-10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed son
Resistorfor R2 (Figure 2)
Bipolar Zero Error with Fixed
Resistor for RI (Figure 3)
Gain Adjustment Range (Figure 2) ±0.25
Bipolar Zero Adjustment Range
±D.t5
son
REFERENCE INPUT
Input Impedance
REFERENCE OUTPUT
Voltage
Current (ava.i1able for external
loads)"
POWER DISSIPATION
V
V
V
V
V
±O.I
±D.25
±O.I
±0.2S
% of F.S. Range
±0.05
±D.15
±0.05
±O.I
% of F.S. Range
% of F.S. Range
% ofF.s. Range
±D.25
±D.15
15k
20k
25k
15k
20k
25k
n
9.90
10.00
10.10
9.90
10.00
10.10
V
1.5
2.5
345
mW
1.5
2.5
225
345
NOTES
1 The diptal inputs are I'laranteed. but not tested over the operatin. temperature range.
'The power supply gain scnsitMty is tested in reference to a Vcc, VEE ofUSV de.
2-64 DIGITAL-TO-ANALOG CONVERTERS
225
rnA
• For operation at elevated. temperatures the reference cannot supply current for
external loads. It. therefore. should be buffered if additional loads are to be supplied.
Specifications subject to chanse without notice.
AD565A1AD566A
MODEL
MIN
DATA INPUTS' (Pins 13 to 24)
TTL or 5 Volt CMOS
I"Pu t Vol tage
Bit ON Logic .. t"
+2.0
AD565AS
TYP
Bit OF': Logic "0"
MAX
MIN
+5.5
+2.0
AD565AT
TYP
+120
+35
RESOLUTION
OUTPUT
Current
Unipolar (all bits on)
Bipolar (all bits on or off)
Resistance (exclusive of span
resistors)
Offset
Unipolar
Bipolar (Figure 3, Rz
Capacitance
Compliance Voltage
T min to Tmax
ACCURACY (error relative to
full scale) +2SDC
V
V
+300
+100
12
+ 110
+35
+300
+100
12
IlA
Il A
Bits
-1.6
-2.0
-2.4
::to.8
::t1.O
::tl.2
rnA
rnA
8k
10k
6k
8k
10k
n
lUll
0.05
0.15
lUll
0.05
0.1
% of F.S. Range
% of F.S. Range
pI'
-2.0
6k
±l.O
0.05
25
-1.5
+10
±1/4
(0.006)
± 1/2
(()'OI2)
Tmin to Tmax
+5.5
-2.4
±1.2
-1.6
±O.S
= 50n fixed)
UNITS
+0.8
+0.8
Logic Current (each bit)
Bit ON Logic "1"
Bit OFF Logic "0"
MAX
0.05
25
-1.5
±I12
(0.012)
±1/8
(0.003)
+10
V
±I14
(0.006)
LSB
% of F.S. Range
LSB
% of F.S. Range
±3/4
±1/4
±1/2
(O.OIS)
(0.006)
(0.012)
DIFFERENTIAL NONLINEARITY
+2SDC
±l/2
±3/4
MONOTONICITY GUARANTEED
Tmin to Tmax
±1/4
±I12
MONOTONICITY GUARANTEED
LSB
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
I
5
IS
2
2
10
30
250
IS
30
ppm/'C
ppm/'C
I
5
10
2
2
10
400
250
400
ns
30
50
IS
30
30
50
ns
ns
+125
+150
'c
'c
I5
ppm/DC
ppm/'C
SETTLING TIME TO 1/2LSB
All Bits ON-to-OFF or
OFF-to-O"'~
FULL SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
TEMPERATURE RANGE
Operating
Storage
-55
-65
+125
+150
-55
-65
POWER REQUIREMENTS
Vee, +11.4 to +16.5V de
VEE, -11.4 to -16.5V de
3
-12
5
-IS
3
-12
5
-IS
rnA
rnA
POWER SUPPLY GAIN SENSITIVITY'
Vee = +11.4 to +16.5V de
VEE = -11.4 to -16.5V de
3
15
10
25
3
15
10
25
ppm of F.S.I%
ppm of F.S.I%
PROGRAMMABLE OUTPUT
RANGES (see Figures 2, 3,4)
o to +S
-2.5 to +2.5
Oto+IO
-S to +S
-10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed son
Resistor for R2 (Figure 2)
Bipolar Zero Error with Fixed
50n Resistor for RI (Figure 3)
Gain Adjustment Range (Figure 2) to.25
Bipolar Zero Adjustment Range
±a.t5
o to +S
V
-2.5 to +2.5
V
V
V
V
o to +10
-S to +S
-10 to +10
±0.1
±0.25
±a.05
±0.15
±O.I
±0.25
% of F.S. Range
±0.05
±a.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
±0.25
±a.15
REFERENCE INPUT
Input Impedance
REFERENCE OUTPUT
Voltage
Current (available for external
loads)'
POWER DISSIPATION
15k
20k
25k
15k
20k
25k
n
9.90
10.00
10.10
9.90
10.00
10.10
V
1.5
2.5
1.5
2.5
225
345
225
rnA
345
mW
Specifications shown In boldface an: tested on all productIOn UOlts at
(mal electrical test. Results from those tests are used to calculate out·
going quality levels. AU min and max specifications arc guaranteed,
although only those shown in boldface arc tested on all production
units.
DIGITAL-TO-ANALOG CONVERTERS 2-65
SPECIFICATIONS
(fA
= + 25"&, VEE = - 15V, unless othelWise specified)
MODEL
MIN
DATA INPUTS' (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic "I"
Bit OFF Logic "0"
Logic Current (each bit)
Bit ON Logic "1"
Bit OFF Logic "0"
+2.0
0
RESOLUTION
OUTPUT
Current
Unipolar (all bits on)
Bipolar (all bits on or off)
Resistance (exclusive of span
resistors)
Offset
Unipolar (adjustable to
zero per Figure 3)
Bipolar (Figure 4 R, and
R, = son fixed)
Capacitance
Compliance Voltage
Tmin toTmax
+120
+lS
MIN
+5.5
+0.8
+2.0
0
+300
+100
ADS66AK
TYP
+120
+lS
MAX
UNITS
+5.5
+0.8
V
V
+300
+100
p.A
12
Bits
p.A
-1.6
iO.8
-2.0
i1.0
-2.4
i1.2
-1.6
iO.B
-2.0
±1.0
-2.4
i1.2
mA
mA
6k
Bk
10k
6k
8k
10k
n
0.01
0.05
0,01
0.05
%of F.S.R.
0.05
25
0.15
0.05
25
0.1
% of F.S.R.
pF
+10
V
±1/4
(0.006)
LSB
% of F.S.R.
LSB
%of F.S.R.
-1.S
+10
i1/4
(0.006)
±1/2
(0.012)
Tmin toTmax
Tmin toTmax
MAX
12
ACCURACY (error relative to
full scale) +2S o C
DIFFERENTIAL NONLINEARITY
+2S o C
ADS66AJ
TYP
-1.S
i1/2
(0.012)
±3/4
(O.OIB)
±1/2
±3/4
MONOTONICITY GUARANTEED
±1/8
(O.OOl)
±1/4
(0.006)
±i12
(0.012)
±1/2
±1/4
MONOTONICITY GUARANTEED
LSB
TEMPERATURE COEFFICIENTS
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
1
5
7
2
2
10
10
1
5
3
2
2
10
S
SETTLING TIME TO 1/2LSB
All Bits ON-to.()FF or OFF-to.()N (Figure 8)
250
350
250
350
ns
FULL SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
15
30
30
50
15
30
30
50
ns
ns
POWER REQUIREMENTS
VEE. -11.4 to -16.5V de
-12
-18
-12
-18
mA
POWER SUPPLY GAIN SENSITIVITY'
VEE = -11.4 to -16.5V de
15
ZS
15
25
ppm of F.S.I%
PROGRAMMABLE OUTPUT
RANGE (see Figures 3. 4. 5)
o to+5
-2.5 to +2.5
o to +5
-2.5 to +2.5
o to +10
-5 to +S
-10 to +10
o to +10
-S to +S
-10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed SOn
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50n Resistor for R I (Figure 4)
Gain Adjusbnent Range (Figure 3)
Bipolar Zero Adjustment Range
±0.25
±o.IS
REFERENCE INPUT
Input Impedance
15k
POWER DISSIPATION
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Reference Voltage
Accuracy
Reference Feedthrough (unipolar mode.
all bits OFF, and 1 to +10Y [p-pl. sinewave
frequency for 1/2LSB [popl. feedthrough)
Output Slew Rate 10%-90%
90%-10%
Output Settling Time (all bits on and a 0-10V
step change in reference voltage)
CONTROL AMPLIFIER
Full Power Bandwidth
Small-Signal Closed-Loop Bandwidth
±O.I
±0.2S
±o.05
±O.IS
20k
25k
300
V
V
V
±0.1
±O.ZS
% of F.S.R.
±0.05
±O.I
% of F.S.R.
%ofF.SK
% of F.S.R.
20k
25k
n
180
300
mW
Two (2): Bipolar Operation at Digital Input Only
+IV to +10V. Unipolar
10 Bits (±O.OS% of Reduced F.S.) for IV de Reference Voltage
40kHz typ
5mA/p.s
ImA/p.s
i.Sp.s to 0.01% F.S.
300kHz
1.8MHz
NOTES
I The digitlll input levels aR guaranteed but not tested over the temperlltuR ranse.
tThc power supply pin sensitivity is tested in reference to a VEE of -lSV dc.
Specifications subject to change without notice.
2-66 DIGITAL-TO-ANALOG CONVERTERS
15k
ppmtC
ppmtc
V
V
±o.25
±o.IS
180
ppm/C
pprn/C
AD565A1AD566A
MODEL
MIN
DATA INPUTS' (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic "1"
AD566AS
TYP
+2.0
0
Bit OFF Logic "0"
Logic Current (each bit)
Bit ON Logic "I"
Bit OFF Logic "0"
+120
+35
RESOLUTION
MAX
MIN
+5.5
+0.8
+2.0
0
AD566AT
TYP
+300
+100
+120
+35
12
OUTPUT
Current
Unipolar (all bits on)
Bipolar (all bits on or off)
Resistance (exclusive of span
resistors)
Offset
Unipolar (adjustable to
UNITS
.5.5
+0.8
V
V
+300
+100
I'A
I'A
12
Bits
-1.6
fO.S
-Z.O
±l.O
-2.4
±1.2
-1.6
±O.S
-2.0
±1.0
-2.4
±1.2
mA
mA
6k
8k
10k
6k
8k
10k
n
0.0\
0.05
0.01
0.05
% of F.S.R.
0.05
25
0.15
0.05
25
0.1
%of F.S.R
pF
+10
V
(0.006)
±1I4
(0.006)
±1I2
(0.012)
LSB
%ofF.5.R.
LSB
%of F.S.R.
±1/4
±11l
LSB
zero per Figure 3)
Bipolar (Figure 4 R 1 and
R, =
fixed)
Capacitance
Compliance Voltage
son
-1.5
TmintoTmax
MAX
ACCURACY (error relative to
full scale) +2S o C
+10
±1I4
(0.006)
±I/2
(0.012)
Tmin to Tmax
-1.5
±IIl
±I/S
(0.003)
(0.012)
±3/4
(0.018)
±1/4
DIFFERENTIAL NONLINEARITY
t2SOC
±3/4
±I/2
MONOTONICITY GUARANTEED
Tmin toTmax
TEMPERATURE COEFFICIENTS
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
1
5
7
2
SETTLING TIME TO 1I2LSB
All Bits On-to'()FF or OFF-to'()N (Figure 8)
250
FULL SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
MONOTONICITY GUARANTEED
2
ppm/oC
1
5
3
2
2
10
5
350
250
350
ns
15
30
30
50
15
30
30
50
ns
ns
POWER REQUIREMENTS
VEE. -11.4 to -16.5V de
-12
-18
-12
-18
mA
POWER SUPPLY GAIN SENSITIVITY'
VEE = -11.4 to -16.5V de
15
25
15
25
PROGRAMMABLE OUTPUT
RANGE (see Figures 3, 4, S)
o to +5
to
10
o to +S
-2.S to +2.5
o to +10
-S to +5
-10 to +10
-2.5 to +2.5
o to +10
-5 to +S
-10to+l0
EXTERNAL ADJUSTMENTS
Gain Error with Fixed SOn
Resistor R2 (Figure 3)
Bipolar Zero Error with Fixed
son Resistor for Rl (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
to.2S
to.IS
REFERENCE INPUT
Input Impedance
15k
POWER DISSIPATION
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Reference Voltage
Accuracy
Reference Feedthrough (unipolar mode,
all bits OFF, and 1 to +10V [p-p) , sinewave
frequency for 1/2LSB Ip-pJ feedthrough)
Output Slew Rate
10%-90%
90%-10%
Output Settling Time (all bits on and a O-IOV
step change in reference voltage)
CONTROL AMPLIFIER
Full Power Bandwidth
Small-Signal Closed-Loop Bandwidth
Specifications subject to change without notice.
to.l
±O.lS
±0.05
±O.15
25k
180
300
15k
ppmlC
ppmlC
ppm of F.S.I%
V
V
V
V
V
±O.l
±O.2S
% of F.S.R.
±0.05
±O.l
% of F.S.R.
% of F.S.R.
%of F.S.R.
±O.25
±0.15
20k
ppm/C
20k
25k
n
180
300
mW
Two (2): Bipolar Operation at Digital Input Only
+IV to +lOV, Unipolar
10 Bits (±O.OS% of Reduced F.S.) for IV dc Reference Voltage
40kHz typ
5mAil's
ImAil's
1.51" to 0.01% F.S.
300kHz
1.8MHz
Specifications shown in boldface are tested on all production units at
f"mal electrical test. Results from those tests arr used to calculate outgoing quality levels. All min and max specifications are JUaranteed,
although only those shown in boldface are tested on an production
units.
DIGITAL-TO-ANALOG CONVERTERS 2-67
ABSOLUTE MAXIMUM RATINGS
vcc to Power Ground
. . . . . .
• . OV to +18V
VEE to Power Ground (AD565A)
· . OV to -18V
Voltage on DAC Output (Pin 9)
· -3Vto +12V
Digital Inputs (Pins 13 to 24) to
Power Ground . . . . . . . .
- 1.0V to + 7.0V
Ref in to Reference Ground . . .
± 12V
Bipolar Offset to Reference Ground .
± 12V
10V Span R to Reference Ground . .
± 12V
20V Span R to Reference Ground. .
±24V
Ref out (AD565A)
. Indeflnite Short to Power Ground
Momentary Short to Vcc
Power Dissipation
. . . . . . . . . . . . . . 100OmW
PIN DESIGNATIONS
NC
.PIN 1
IDENTIFIER
BIT 1 IN (MSB)
NC
BIT 1 IN (MSB)
NC
BIT2 IN
NC
BIT2 IN
Vee
BIT3 IN
REFERENCE GNO
BIT3 IN
REF OUT (+10V ±1%)
BIT4 IN
AMP SUMMING
JUNCTION
BIT4 IN
REFERENCE GNO
BIT5 IN
REFERENCE V HI IN
BIT5 IN
BITe IN
-VEE -15V IN
(20mA)
BITe IN
BIT7 IN
BIPOLAR OFFSET R IN
BIT7 IN
REFERENCE IN
AD565A
TOP VIEW
(Not to Scale)
BIPOLAR OFFSET IN
BITS IN
NC
BITS IN
OAC OUT (-2mA F.S.)
BIT9 IN
OAC OUT (-2mA F.S.)
BIT9 IN
10V SPAN R
BIT 10 IN
10VSPAN R
BIT 10 IN
20V SPAN R
BITll IN
20V SPAN R
BIT 11 IN
POWER GNO
BIT 12 IN (LSB)
POWER GNO
BIT 12 IN (LSB)
ADS6SA ORDERING GUIDE
Model
Package
Option *
Temp. Range
Linearity
Error Max MaxGainT.C.
@2S·C
(ppmofF.S.I"C)
AD565AJD/BIN
AD565AKDIBIN
AD565ASD/BIN
ADS6SATD/BIN
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
Oto + 70°C
Oto + 70°C
- 55°C to + 125°C
- 55°C to 112SoC
±1I2LSB
±1I4LSB
±1I2LSB
± 1I4LSB
50
20
30
IS
*See Section 14 for package outline information.
ADS66A ORDERING GUIDE
Model
Package
Option*
Temp. Range
Linearity
Error Max Max Gain T .C.
@+2S·C (ppm ofF .S.I"C)
ADS66AJD/BIN
ADS66AKD/BIN
AD566ASDIBIN
ADS66ATD/BIN
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
Oto + 70°C
Oto + 70°C
- 55°C to + 125°C
- 55°C to + 125°C
±1I2LSB
±1I4LSB
±1I2LSB
±1I4LSB
*See Section 14 for package outline information.
2-68 DIGITAL-TO-ANALOG CONVERTERS
10
3
10
3
Applying the AD565A1AD566A
GROUNDING RULES
The AD565A and AD566A bring out separate reference and
power grounds to allow optimum connections for low noise
and high-speed performance. These grounds should be tied
together at one point, usually the device power ground. The
separate ground returns are provided to minimize current
flow in low-level signal paths. In this way, logic return
currents are not summed into the same return path with
analog signals.
CONNECTING THE ADS6SA FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using
an operational amplifier are shown here with the preferred trimming techniques. If a low offset operational amplifier (ADS 10L,
AD517L, AD741L, AD301AL, AD OP-07) is used, excellent
performance can be obtained in many situations without trimming (an op amp with less than O.SmV max offset voltage
should be used to keep offset errors below 1I2LSB). If a son
fixed resistor is substituted for the lOOn trimmer, unipolar
zero will typically be within ±1I2LSB (plus op amp offset),
and full scale accuracy will be within 0.1 % (0.25% max).
Suhstituting a son resistor for the lOOn bipolar offset trimmer will give a bipolar zero error typically within ±2LSB
(0.05%).
The ADS09 is recommended for buffered voltage-output applications which require a settling time to ±1I2LSB of one microsecond. The feedback capacitor is shown with the optimum
value for each application; this capacitoris required to compensate for the 25 picofarad DAC output capacitance.
FIGURE 3. OTHER VOLTAGE RANGES
The AD565A can also be easily configured for a unipolar 0 to
+5 volt range or ±2.5 volt and ±10 volt bipolar ranges by using
the additional 5k application resistor provided at the 20 volt
span R terminal, pin 11. For a 5 volt span (0 to +5 or ±2.S),
the two 5k resistors are used in parallel by shorting pin 11 to
pin 9 and connecting pin 10 to the op amp output and the
bipolar offset either to ground for unipolar or to REF OUT
for the bipolar range. For the ±10 volt range (20 volt span)
use the 5k resistors in series by connecting only pin 11 to the
op amp output and the bipolar offset connected as shown.
The ±10 volt option is shown in Figure 3.
Figure 1. 0 to +10V Unipolar Voltage Output
FIGURE 1. UNIPOLAR CONFIGURATION
This configuration will provide a unipolar 0 to + 10 volt output
range. In this mode, the bipolar terminal, pin 8, should be
grounded if not used for trimming.
Rl
REF OUT
,
Vee
""'"
BIPOLAR OFF
STEP I ... ZERO ADJUST
Turn all bits OFF and adjust zero trimmer Rl, until the output reads 0.000 volts (lLSB = 2.44mV). In most cases this trim
is not needed, but pin 8 should then be connected to pin 12.
STEP II ... GAIN ADJUST
Turn all bits ON and adjust lOOn gain trimmer R2, until the
output is 9.9976 volts. (Full scale is adjusted to 1LSB less than
nominal full scale of 10.000 volts.) If a 1O.2375V full scale is
desired (exactly 2.5mV/bit), insert a 120n resistor in series
with the gain resistor at pin 10 to the op amp output.
FIGURE 2. BIPOLAR CONFIGURATION
This configuration will provide a bipolar output voltage from
-5.000 to +4.9976 volts, with positive full scale occurring with
all bits ON (all l's).
STEP I ... OFFSET ADJUST
Turn OFF all bits. Adjust lOOn trimmer R1 to give -5.000
volts output.
REF
5
GNDH-""1,"",,"'"1
Figure 2. ±5V Bipolar Voltage Output
v'"
Rl
100n
STEP II ... GAIN ADJUST
Turn ON All bits. Adjust lOOn gain trimmer R2 to give a
reading of +4.9976 volts.
Please note that it is not necessary to trim the op amp t6 obtain full accuracy at room temperature. In most bipolar situations, an op amp trim is unnecessary unless the untrimmed offset drift of the op amp is excessive.
Figure 3. ± 10V Voltage Output
DIGITAL-TO-ANALOG CONVERTERS 2-69
•
CONNECTING THE ADS66A FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using
an operational amplifier are shown here with the preferred
trimming techniques. If a low offset operational amplifier
(AD510L, ADS 17L, AD741L, AD301AL, AD OP-07) is used,
excellent performance can be obtained in many situations
without trimming (an op amp with less than 0.5mV max offset voltage should be used to keep offset errors below 1/2LSB).
If a son fixed resistor is substituted for the lOOn trimmer,
unipolar zero will typically be within ±1/2LSB (plus op amp
offset), and full scale accuracy will be within 0.1 % (0.25%
max). Substituting a son resistor for the lOOn bipolar offset trimmer will give a bipolar zero error typically within
±2LSB (0.05%).
The AD509 is recommended for buffered voltage-output applications which require a setrling time to ±1I2LSB of one
microsecond. The feedback capacitor is shown with the optimum value for each application; this capacitor is required to
compensate for the 25 picofarad DAC output capacitance.
for the bipolar range. For the ±10 volt range (20volt span) use
the 5k resistors in series by connecting only pin 11 to the op
amp output and the bipolar offset connected as shown. The
±10 volt option is shown in Figure 6.
ANALOG OUTPUT
DIGITAL INPUT
MSB
LSB
000000000000
011111111111
100000000000
111111111111
Straight Binary
Offset Binary
Two's CompI.*
Zero
Mid Scale -1 LSB
+112 FS
+FS -ILSB
-Full Scale
Zero -lLSB
Zero
+ Full Scale -1 LSB
Zero
+FS -lLSB
-FS
Zero-1LSB
-Invert the MSB of the offset binary code with an external
inverter to obtain two's complement.
Table I. Digital Input Codes
+15V
FIGURE 4. UNIPOLAR CONFIGURATION
This configuration will provide a unipolar 0 to +10 volt output
range. In this mode, the bipolar terminal, pin 7, should be
grounded if not used for trimming.
STEP I ... ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R1, until the output
reads 0.000 volts (ILSB = 2.44mV). In most cases this trim
is not needed, but pin 7 should then be connected to pin 12.
STEP II ... GAIN ADJUST
Turn all bits ON and adjust lOOn gain trimmer, R2, until the
output is 9.9976 volts. (Full scale is adjusted to 1LSB less than
nominal full scale of 10.000 volts.) If a 10.23 75V full scale is
desired (exactly 2.5mV/bit), insert a 120n resistor in series
with the gain resistor at pin 10 to the op amp output.
Figure 4. 0 to +10V Unipolar Voltage Output
FIGURE 5. BIPOLAR CONFIGURATION
This configuration will provide a bipolar output voltage from
-5.000 to +4.9976 volts, with positive full scale occurring with
all bits ON (all 1's).
STEP I ... OFFSET ADJUST
Turn OFF all bits. Adjust lOOn trimmer R1 to give -5.000
output volts.
Figure 5. ±5V Bipolar Voltage Output
STEP II ... GAIN ADJUST
Turn ON all bits. Adjust lOOn gain trimmer R2 to give a
reading of +4.9976 volts.
Please note that it is not necessary to trim the op amp to obtain full accuracy at room temperature. In most bipolar situations, an op amp trim is unnecessary unless the untrimmed offset drift of the op amp is excessive.
FIGURE 6. OTHER VOLTAGE RANGES
The AD566A can also be easily configured for a unipolar 0 to
+5 volt range or ±2.5 volt and ±10 volt bipolar ranges by using
the additional 5k application resistor provided at the 20 volt
span R terminal, pin 11. For a 5 volt span (0 to +5Vor ±2.5V),
the two 5k resistors are used in parallel by shorting pin 11 to
pin 9 and connecting pin 10 to the op amp output and the bipolar offset resistor either to ground for unipolar or to VREF
2-70 DIGITAL-TO-ANALOG CONVERTERS
·THE PARALLEL COMBINATION OF THE BIPOLAR OfFSET RESISTOR
AND R3 ESTABLISH A CURRENT TO BALANCE THE MSB CURRENT.
THE EFFECT OF TEMPERATURE COEFfiCIENT MISMATCH BETWEEN
THE BIPOLAR RESISTOR COMBINATION AND DAC RESISTORS IS
EXPLAINED ON PREVIOUS PAGE.
Figure 6. ± 10V Voltage Output
12-Bit Ultrahigh Speed
Monolithic OfAConverter
A0568 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
Ultrahigh Speed: Current Settling to 1LSB in 35ns
High Stability Buried Zener Reference on Chip
Monotonicity Guaranteed Over Temperature
10.24mA Full-Scele Output Suitable for Video
Applications
Integral and Oifferential Linearity Guaranteed Over
Temperature
0.3" "Skinny DIP" Packaging
Variable Threshold Allows TTL and CMOS
Interface
AD568 FUNCTIONAL BLOCK DIAGRAM
.",
"~:::~;':@"M--"::"'""."\
~::::~~~::ji-LtLtL~_-1~~23
~=':E
~
"
c~~~~,,~-~~~~~~~~~~
'=::~.
2181POLAR
OFFSETCI • ..,I
's ~OE~:'~
.~"'"
COMMON
PRODUCT DESCRIPTION
The AD568 is an ultrahigh-speed, 12-bit digital-ta-analog convener (DAC) settling to 0.025% in 35ns. The monolithic device
is fabricated using Analog Devices' Complementary Bipolar
(CB) Process. This is a proprietary process featuring high-speed
NPN and PNP devices on the same chip without the use of
dielectric isolation or multichip hybrid techniques. The high
speed of the ADS68 is maintained by keeping impedance levels
low enough to minimize the effects of parasitic circuit
capacitances.
The DAC consists of 16 current sources configured to deliver a
10.24mA full-scale current. Multiple matched current sources
and thin-ftlm ladder techniques are combined to produce bit
weighting. The DAC's output is a 1O.24mA full scale (FS) for
current output applications or a 1.024V FS unbuffered voltage
output. Additionally, a 10.24V FS buffered output may be
generated using an onboard lldl span resistor with an external
op amp. Bipolar ranges are accomplished by pin strapping.
PRODUCT HIGHLIGHTS
1. The ultrafast settling time of the AD568 allows leading edge
performance in waveform generation, graphics display and
high-speed AID conversion applications.
2. Pin strapping provides a variety of voltage and current output
ranges for application versatility. Tight control of the absolute
output current reduces trim requirements in externally-scaled
applications.
3. Matched on-chip resistors can be used for precision scaling
in high-speed AID conversion circuits.
4. The digital inputs are compatible with TTL and + 5V CMOS
logic families.
5. Skinny DIP (0.3") packaging minimizes board space requirements and eases layout considerations.
Laser wafer trimming insures full 12-bit linearity. All grades of
the AD568 are guaranteed monotonic over their full operating
temperature range. Furthermore, the output resistance of the
DAC is trimmed to won ± 1.0%. The gain temperature coefficient
of the voltage output is 3OppmI"C max (K).
The AD568 is available in three performance grades. The
ADS68JQ and KQ are available in 24-pin cerdip (0.3") packages
and are specified for operation from 0 to + 7O'C. The AD568SQ
features operation from - 55'C to + 125"C and is also packaged
in the hermetic 0.3" cerdip.
DIGITAL-TO-ANALOG CONVERTERS 2-71
•
SPECIFICATIONS
Model
Min
RESOLUTION
ACCURACY'
Linearity
Tmin toTnwt
Differential Nonlinearity
TmintoTmu:
Monotonicity
Unipolar Offset
Bipolar Offset
Bipolar Zero
Gain Error
TEMPERATURE COEFFICIENTS'
Unipolar Offset
Bipolar Offset
Bipolar Zero
Gain Drift
Gain Drift (loUT)
DATA INPUTS
Logic Levels (T min to T max)
VIR
VII.
Logic Currents (Tmin to T max)
IIR
III.
VTH Pin Voltage
(@TA
= +25"C, Vee, V =±15V unless oIhllWise noted)
ADS68J
Typ
EE
AD568S
AD568K
Typ
Min
Mas
12
Mas
Max
-0.2
-1.0
-0.2
-1.0
-s
*
*
-50
*
+30
*
*
*
ppmofFSRfC
ppmofFSRfC
ppmofFSRfC
ppmofFSRfC
ppmofFSRfC
*
*
*
*
*
*
V
V
*
*
*
*
*
p.A
p.A
V
+3
+20
-50
-150
*
*
2.0
0.0
7.0
0.8
*
*
+10
-100
*
*
0
-60
-30
*
*
*
1.4
%ofFSR
%ofFSR
%ofFSR
%ofFSR
+5
+30
-3
-20
-IS
LSB
LSB
LSB
LSB
-5
-30
+5
+30
+15
+50
+150
-30
Uails
Bits
-114
-112
+112
+112
+1/4
-112
+1/2
-3/4
+3/4
+3/4
-I
-112
+1
+1
+1/2
-1
-1
-1
+1
+1
GUARANTEED OVERRATED SPECIFlCATlONTEMPERATURERANGE
+0.2
*
*
*
*
+1.0
*
*
*
*
+0.2
*
*
*
*
+1.0
*
*
*
*
-1
-1
-10
-0.5
Typ
12
12
-1/2
-3/4
Min
+50
*
-100
-200
*
CODING
BINARY, OFFSET BINARY
CURRENT OUTPUT RANGES
OtolO.24, ±5.12
mA
VOLTAGE OUTPUT RANGES
Oto1.024, ±0.512
V
COMPLIANCE VOLTAGE
-2
OUTPUT RESISTANCE
Exclusive ofRL
Inclusive ofRL
99
160
SETTLING TIME
Current to
±0.025%
±O.I%
Voltage
5011Losd' ,0.512Vp·p,
[00.025%
toO.I%
tol%
75!l Losd', 0.768V p'p,
to 0.025%
toO.I%
to 1%
1001l (Internal RLl', 1.024V p.p,
to 0.025%
toO.I%
[01%
Glitch Impulse4
Peak Amplitude
FULL·SCALE TRANSITION'
10% to 90% Rise Time
90% to 10% FaU Time
POWER REQUIREMENTS
+ 13.5V to + 16.5V
-13.5Vto -16.5V
Power Dissipation
PSRR
TEMPERATURE RANGE
Rated Specification2
Storage
+1.2
*
*
*
*
V
*
*
*
*
!l
!l
35
23
*
*
*
*
nSloO.025%ofFSR
nstoO.I%ofFSR
37
25
18
*
*
*
*
*
*
nstoO.025%ofFSR
nstoO.I%ofFSR
nSlO 1% ofFSR
40
25
20
*
*
*
•
50
38
24
350
15
*
*
*
*
*
*
*
*
*
*
11
11
*
*
*
*
200
100
27
-7
525
0
-65
240
101
70
+150
NOTES
*SameasAD568J.
1Measured in [OUT mode.
lMeasured in Vom mode, unless otherwise specified. See text for further infonnation.
3ofotal Resistance. Refer to Figure 3.
2-72 DIGITAL-TO-ANALOG CONVERTERS
*
*
*
32
-8
625
0.05
nSlo 0.025% ofFSR
nSloO.1%ofFSR
nSlo l%ofFSR
*
*
*
*
*
*
*
*
*
nSlo 0.025% ofFSR
nstoO.1%ofFSR
OSlO l%ofFSR
pV-sec
%ofFSR
ns
ns
*
*
*
*
rnA
rnA
"C
"C
0
70
-55
+125
*
*
*
*
4 At
mW
%ofFSRN
the major carry. driven by HeMOS logic. See text for further explanation.
5Measuredin VoUTmode.
Specifications shown in boldface are tested on all production units at fmal electrical test.
Specifications subjC(;;t to change without notice.
AD568
MSB
LSB
REFERENCE
COMMON
lOUT
LOAD RESISTOR
'....1
THRESHOLD 14
COMMON
BIPOLAR
OFFseT (lapol
C~:~~~ 17}-----<~
TOV SPAN
RESISTOR
~------~~------~
TOV SPAN
AD568
RESISTOR
ANALOG
v"
COMMON
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS*
vcc to REFCOM
. .
VEE to REFCOM ..
REFCOM to LCOM
ACOM to LCOM .
THCOM to LCOM
SPANs to LCOM
IBPO to LCOM
lOUT to LCOM .
Digital Inputs to THCOM
Voltage Across Span Resistor
VTH to THCOM . . . . . .
Logic Threshold Control Input Current .
Power Dissipation . . . . . . . . . . . .
Storage Temperature Range
Q (Cerdip) Package.
Junction Temperature
Thermal Resistance
S;.
ADS68 PIN CONFIGURATION
. . . . OV to + l8V
. . . . OV to -18V
+ l00mV to - lOY
±100mV
±500mV
.. ±12V
. . . ±5V
-5V to VTH
-500mV to +7.0V
. . . . . . . 12V
-0.7V to + I.4V
. . SmA
. . . . . IOOOmW
- 65°C to + 150°C
175°C
+15V IVee!
REFERENCE COMMON IREFCOMI
-15VIVn )
'OUT
LOAD RESISTOR (RLI
ANALOG COMMON (ACOM)
LADDER COMMON ILeDM)
TOV SPAN RESISTOR
TOV SPAN RESISTOR
BIT 10
TtfRESHOLD COMMON ITHCOMI
BIT 121LSBI
THRESHOLD CONTROL (VTHI
S;c . • . . • • . •
*Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational. sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ORDERING GUIDE
Model
Package
Option*
AD568JQ 24-Lead Cerdip (Q-24)
AD568KQ 24-Lead Cerdip (Q-24)
AD568SQ 24-Lead Cerdip (Q-24)
Temperature Linearity
RangeOC
Error Max.
@2SoC
Voltage
GainT.C.
MaxppmfOC
Oto +70
Oto +70
-55to + 125
±50
±30
±50
± 112
± 114
± 112
·See Section 14 for package outline information.
DIGITAL-TO-ANALOG CONVERTERS 2-73
II
Definitions
Connecting the AD568
LINEARITY ERROR (also called INTEGRAL NONLINEARITY OR INL): Analog Devices defmes linearity
error as the maximum deviation of the actual analog output
from the ideal output (a straight line drawn from 0 to
FS -ILSB) for any bit combination expressed in multiples
of lLSB. The AD568 is laser trimmed to 1I4LSB (0.006% of
FS) maximum linearity error at + 25°C for the K version and
1I2LSB for the J and S versions.
UNBUFFERED VOLTAGE OUTPUT
DIFFERENTIAL LINEARITY ERROR (also called
DIFFERENTIAL NONLINEARITY or DNL): DNL is
the measure of the variation in analog value, normalized to
full scale, associated with a lLSB change in digital input
code. Monotonic behavior requires that the differential linearity
error not exceed lLSB in the negative direction.
MONOTONICITY: A DAC is said to be monotonic if the
output either increases or remains constant as the digital
input increases.
Unipolar ConfJgU1"8tion
Figure 3 shows the AD568 configured to provide a unipolar 0 to
+ 1.024V output range. In this mode, the bipolar offset terminal,
Pin 21, should be grounded if not used for offset trimming.
The nominal output impedance of the AD568 with Pin 19 grounded
has been trimmed to lOOn, ± 1%. Other output impedances can
be generated with an external resistor, REXT> between Pins 19
and 20. An REXT equalling 300n will yield a total output resistance
of 7Sn, while an RExT of loon will provide son of output
resistance. Note that since the full-scale output current of the
DAC remains 10.24mA, changing the load impedance changes
the unbuffered output voltage accordingly. Settling time and
full-scale range characteristics for these load impedances are
provided in the specifications table.
+15V
-15V
UNIPOLAR OFFSET ERROR: The deviation of the analog
output from the ideal (OV or OmA) when the inputs are set
to all Os is called unipolar offset error.
BIPOLAR OFFSET ERROR: The deviation of the analog
output from the ideal (negative half-scale) when the inputs
are set to all Os is called bipolar offset error.
BIPOLAR ZERO ERROR: The deviation of the analog
output from the ideal half-scale output of OV (or OmA) for
bipolar mode when only the MSB is on (100 .....00) is called
bipolar zero error.
DIGITAL
INPUTS
~~--~~--------~ ~~w~
GROUND
GAIN ERROR: The difference between the ideal and actual
output span of FS -ILSB, expressed in % of FS, or LSB,
when all bits are on.
DlGrTAL
SUPPlY
GROUND
GLITCH IMPULSE: Asymmetrical switching times in a
DAC give rise to undesired output transients which are quantified by their glitch impulse. It is specified as the net area of
the glitch in nY-sec or pA-sec.
+5V
Figure 3. Unipolar Output Unbuffered 0 to
+ 1.024V
D.B
~
.
g
Bipolar Configuration
Figure 4 shows the connection scheme used to provide a bipolar
output voltage tange of 1.024V. The bipolar offset (-0.512V)
occurs when all bits are OFF (00 ... 00), bipolar zero (OV)
A
D.B
It
!;
5
+15V
-15V
0
~
Q
D..
50
'00
TlME-
n.
'50
... ...
Figure 2. AD568 Glitch Impulse
DIGITAL
INPUTS
ri.-~~--~~---------, ~~
GROUND
COMPLIANCE VOLTAGE: The range of allowable voltage
at the output of a current-output DAC which will not degrade
the accuracy of the output current.
SETTLING TIME: The time required for the output to
reach and remain within a specified error band about its final
value, measured from the digital input transition.
DIGITAL
SUPPLY
GROUND
+5V
Figure 4. Bipolar Output Unbuffered ±O.512V
2-74 DIGITAL-TO-ANALOG CONVERTERS
AD568
occurs when the MSB is ON with all other bits OFF (10 ...
00), and full-scale minus ILSB (0.51175V) is generated when all
bits are ON (II ... II). Figure 5 shows an optional bipolar
mode with a 2.048V range. The scale factor in this mode will
not be as accurate as the configuration shown in Figure 4, because
the laser-trimmed resistor RL is not used.
Figure 4 also demonstrates how the internal span resistor may
be used to bias the VTH pin (Pin 13) from a 5V supply. This
eliminates the requirement for an external RTH in applications
that do not require the precision span resistor.
+ 15V
-1SV
BIPOLAR MODE (Refer to Figure 7)
Step I - Set bits to offset binary "zero" (10 ... 00). Adjust the
zero resistor to produce OV at the DAC output. This removes
the bipolar zero error.
Step 2 - Set all bits to Logic "I" (ON). Adjust gain trim resistor
so the output voltage is equal to the desired full-scale minus
ILSB.
Step 3 - (Optional) If precise trimming of the bipolar offset is
preferred to trimming of bipolar zero: set all bits to Logic "0"
(OFF). Trim the zero resistor to produce the desired negative
full scale at the DAC output.
Note: this may slightly compromise the bipolar zero trim.
V~
~~--------~__~----o+
DIGITAL
INPUTS
f--__"""YI-,S.l1kfl
,...
ZERO
an
~~~*
t-O.512VTO +O.512V1
v..
Figure 7. Bipolar Unbuffered Gain and Zero Adjust
+5V
Figure 5. Bipolar Output Unbuffered ± 1.024V
Optional Gain and Zero Adjustment
The gain and offset are laser trimmed to minimize their effects
on circuit performance. However, in some applications, it may
be desirable to externally reduce these errors further. In those
cases, the following procedures are suggested.
UNIPOLAR MODE: (Refer to Figure 6)
Step I - Set all bits (BIT I-BIT 12) to Logic "0" (OFF) - note
the output voltage. This is the offset error.
Step 2 - Set all bits to Logic "I" (ON). Adjust the gain trim
resistor so that the output voltage is equal to the desired full
scale minus ILSB plus the offset error measured in step 1.
Step 3 - Reset all bits to Logic "0" (OFF). Adjust the offset
trim resistor for OV output.
~----------~~-----o+
DKiITAL
INPUTS
S.l1kU
ANALOG
OUTPUT
loon
OFFSET
IOTO +1.024VI
BUFFERED VOLTAGE OUTPUT
For full-scale outputs of greater than I V, some type of external
buffer amplifier is required. The AD840 fills this requirement
perfectly, settling to 0.025% from a 10V full-scale step in less
than lOOns.
A Ikfl span resistor has been provided on chip for use as a
feedback resistor in buffered applications. Using R SPAN (Pins
15, 16) introduces a lOOmW code-dependent power source onto
the chip which may generate a slight degradation in linearity.
Maximum linearity performance can be realized by using an
external span resistor.
Unipolar Inverting Configuration
Figure 8 shows the connections for producing a - 1O.24V full-scale
swing. This configuration uses the AD568 in the current output
mode into a summing junction at the inverting input terminal of
the external op amp. With the load resistor RL grounded, the
DAC has an output impedance of 1000. This produces a noise
gain of II from the noninverting terminal of the op amp, and
hence, satisfies the stability criterion of the AD840 (stable at a
gain of 10). The addition of a 5pF compensation capacitor across
the IkO feedback resistor produces optimal settling. Lower
noise gain can be achieved by connecting RL to loUT, increasing
the DAC output impedance to approximately 2000, and reducing
the noise gain to 6 (illustrated in Figure 9). While the output in
this configuration will feature improved noise performance, it is
somewhat less stable and may suffer from ringing. The compensation capacitance should be increased to 7pF to maintain stability
at tins reduced gain.
Figure 6. Unbuffered Unipolar Gain and Zero Adjust
DIGITAL-TO-ANALOG CONVERTERS 2-75
E
+15V
H6V
-15V
O.2 .... F
DIGITAL
INPUTS
-1&V
O.2I1-F
DIGITAL
INPUTS
+'V
+'V
Figure 8. Unipolar Output Buffered 0 to - 10.24V
Bipolar Inverting Configuration
Figure 9 illustrates the implementation of a + S.12V to - S.12V
bipolar range, achieved by connecting the bipolar offset current,
I BPO, to the summing junction of the external ampliller. Note
that since the amplifier is providing an inversion, the full-scale
output voltage is - S.12V, while the bipolar offset voltage (all
bits OFF) is + S.12V at the ampliller output.
+16V
-15V
O·2.tIoF
ANALOG
/f~----~---+-o ~
DIGITAL
INPUTS
ANAlOG
SUPPLY
GROUND
+5V
Figure 9. Bipolar Output Buffered ±5.12V
Noninverting Configuration
If a positive full"scale output voltage is required, it can be implemented using the ADS68 in the unbuffered voltage output
mode followed by the AD840 in a noninverting configuration
(Figure 10). The noise gain of this topology is 10, requiring
onIy SpF across the feedback resistor to optimize settling.
2-76 DIGITAL-TO-ANALOG CONVERTERS
Figure 10. Unipolar Output Buffered 0 to
+ 10.24V
Guidelines for Using the AD568
The designer who seeks to combine high speed with high precision
faces a challenging design environment.· Where tens of milliamperes are involved, fractions of an ohm of misplaced impedance
can generate several LSBs of error. Increasing bandwidths make
formerly negligible parasitic capacitances and inductances significant. As system performance reaches and exceeds that of the
measurement equipment, time-honored test methods may no
longer be trustworthy. The DAC's placement on the boundary
between the analog and digital domains introduces additional
concerns. Proper RF techniques must be used in board design,
device selection, supply bypassing, grounding, and measurement
if optimal performance is to be realized. The ADS68 has been
configured to be relatively easy to use, even in some of the more
treacherous applications. The device characteristics shown in
this datasheet are readily achievable if proper attention is paid
to the details. Since a solid understanding of the circuit involved
is one of the designer's best weapons against the difficulties of
RF design, the following sections provide illustrations, explanations, examples, and suggestions to facilitate successful design
with the ADS68.
Current Output vs. Voltage Output
As indicated in FigUres 3 through 10, the ADS68 has been
designed to operate in several different modes depending on the
external circuit configuration. While these modes may be
categorized by many different schemes, one of the most important
distinctions to be made is whether the DAC is to be used to
generate an output voltage or an output current. In the current
output mode, the DAC output (Pin 20) is tied to some type of
summing junction, and the current flowing from the DAC into
this summing junction is sensed (e.g., Figures 8 and 9). In this
mode, the DAC output scale is insensitive to whether the load
resistor, R L , is shorted (Pin 19 connected to Pin 20), or grounded
(Pin 19 connected to Pin 18). However, this does affect the
output impedance of the DAC current and may have a significant
impact on the noise gain of the external circuitry. In the voltage
output mode, the DAC's output clirrent flows through its own
internal impedance (perhaps in parallel with an external impedance) to generate a voltage, as in Figures 3, 4, 5, and 10. In this
AD568
case, the DAC output scale is directly dependent on the load
impedance. The temperature coefficient of the ADS68's internal
reference is trimmed in such a way that the drift of the DAC
output in the voltage output mode is centered on zero. The
current output of the DAC will have an additional drift factor
corresponding to the absolute temperature coefficient of the
internal thin-film resistors. This additional drift may be removed
by judicious placement of the Ikn span resistor in the signal
path. For example, in Figures 8 and 9, the current flowing from
the DAC into the summing junction could suffer from as much
as ISOppm/"C of thermal drift. However, since this current
flows through the internal span resistor (Pins IS and 16) which
has a temperature coefficient that matches the DAC ladder
resistors, this drift factor is compensated and the buffered voltage
at the amplifier output will be within specified limits for the
voltage output mode.
Output Voltage Compliance
The AD568 has a typical output compliance range of + 1.2V to
- 2.0V (with respect to the LCOM Pin). The current-steering
output stages will be unaffected by changes in the output terminal
voltage over that range. However, as shown in Figure 11, there
is an equivalent output impedance of 200n in parallel with
ISpF at the output terminal which produces an equivalent error
current if the voltage deviates from the ladder common. This is
a linear effe.:t which does not change with input code. Operation
beyond the maximum compliance limits may cause either output
stage saturation or breakdown resulting in nonlinear performance.
The positive compliance limit is not affected by the positive
power supply, but is a function of output current and the logic
threshold voltage at VTH , Pin 13.
i;;~ 10.24mA x (1 _ =ALlN)
lour:: 10.24mA x DIG~~iIN
COMPLIANCE TO
VTHAESIfOLD
COMPUANCETO
LOGIC lOW VALUE
'""...--+-.....-.
I~~~J
15pF
15pF
LADDER
COMMON
ANALOG
digital feedthrough noise, the interconnect distances to the DAC
inputs should be kept as short as possible. Termination resistors
may improve performance if the digital lines become too long.
The digital input should be free from large glitches and ringing
and have maximum 10% to 90% rise and fall times of Sns. Figure
12 shows the equivalent digital input circuit of the ADS68.
VTtlIlESHDl.D
I -.........~-t---o
1.4V
BANDGAP
DIODE
TO
TO
THRESHOLD
ANALOG
COMMON
COMMON
TO
lOUT
LADDER THRESHOLD
COMMON
COMMON
BIT , DRIVES 4 OF THESE CELLS IN PARALLEL.
BIT 2 DRIVES 2 CELLS.
BITS 3-12 DRIVE SINGLE CELLS.
Figure 12. Equivalent Digital Input
Due to the high-speed nature of the ADS68, it is recommended
that high-speed logic families such as Schottky TTL, high-speed
CMOS, or the new lines of FAST'" TTL be used exclusively.
Table I shows how DAC performance can vary depending on
the driving logic used. As this table indicates, STTL, HCMOS,
and FAST represent the most viable families for driving the
AD568.
DAC PERFORMANCE VS. DRIVE LOGIC'
Logic
Family
10-90%
DAC
Rise Time'
TIL
LSTIL
STIL
HCMOS
FAST"
IIns
IIns
9.5ns
IIns
12ns
DAC
SETTLING TIME'"
Glitch"
0.1%
0.025% Impulse
1%
18ns
28ns
16ns
24ns
16ns
34ns
46ns
33ns
38ns
36ns
50ns
80ns
50ns
50ns
42ns
2.5nV·s
950pV-s
850pV-s
35OpV-s
1.0nV-s
Maximum
Glitch
Excursion
240mV
l60mV
ISOmV
115mV
250mV
1All values typical, taken in test fIXture diagrammed in Figure 13.
lMeasuremcnts are made for a IV full-scale step into IOOODAC load resistance.
3Settling time is measured from the time the digital input crosses the threshold voltage
(1.4V) to when the outPUt is within the specifIed range of its fmal value.
"The worst case glitch impulse, measured on the major carry. DAC full scale is 1V.
COMMON
Figure 11. Equivalent Output
Digital Input Considerations
The ADS68 uses a standard positive true straight binary code
for unipolar outputs (all Is full-scale output), and an offset
binary code for bipolar output ranges. In the bipolar mode,
with all Os on the inputs, the output will go to negative full
scale; with III ... 11, the output will go to positive full scale
less ILSB; and with 100 .. 00 (only the MSB on), the output
will go to zero.
The threshold of the digital inputs is set at 1.4V and does not
vary with supply voltage. This is provided by a bandgap reference
generator, which requires approximately 3mA of bias
current achieved by tying RTH to any + VL supply where
_ (+VL -1.4V)
RTH 3mA
.
The input lines operate with small input currents to easily achieve
interface with unbuffered CMOS logic. The digital input signals
to the DAC should be isolated from the analog output as much
as possible. To minimize undershoot, ringing, and possible
Table I.
The variations in settling times can be attributed to differences
in the rise time and current driving capabilities of the various
families. Differences in the glitch impulse are predominantly
dependent upon the variation in data skew. Variations in these
specs occur not only between logic families, but also between
different gates and latches within the same family. When selecting
a gate to drive the ADS68 logic input, pay particular attention
to the propagation delay time specs: tPLH and tPHL. Selecting
the smallest delays possible will help to minimize the settling
time, while selection of gates where tpLH and tpHL are closely
matched to one another will minimize the glitch impulse resulting
from data skew. Of the common latches, the 74374 octal flip-flop
provides the best performance in this area for many of the logic
families mentioned above.
"FAST is a registered trademark of Fairchlld Camera and Instnunentation
Corporation.
DIGITAL-TO-ANALOG CONVERTERS 2-77
CLOCK"--I.::::;;;;b....,
Glitch Considerations
In many high-speed DAC applications, glitch performance is a
critical specification. In a conventional DAC architecture such
as the AD568 there are two basic glitch mechanisms: data skew
and. digital feedthrough. A thorough understanding of these
sources can help the user to minimize glitch in any application.
+5V
SELECT
1A
Vee
'8
,vl--I----,
2A
zvl--If---.
28
3A 74158 3V t----1I---,
38
+11iV -liV
4V
V",
REfCOM
V"
4 AD568IBPO
5
V....
lou.
"'
ACOM
.....
,. .....
!.COM
"
'2
THCOM
Vm
1k
+5V
Figure 73. Test Setup for Glitch Impulse and Settling
Time Measurements
Settling Time Considerations
As can be seen from Table I and the specifications page, the
settling time of the AD568 is application dependent. The fastest
settling is achieved in the current-output mode, since the voltageoutput mode requires the output capacitance to be charged to
the appropriate voltage. The DAC's relatively large output current
helps to minimize this effect, but settling-time sensitive applications should avoid any unnecessary parasitic capacitance at the
output node of voltage output configurations. Direct measurement
of the fme scale DAC sei:tling time, even in the voltage output
mode, is extremely tricky: analog scope front ends are generally
incapable of recovering from overdrive quickly enough to give
an accurate settling representation. The plot shown in Figure 14
was obtained using Data Precision's 640 16-bit sampling head,
which features the quick overdrive recovery characteristic of
sampling approaches combined with high accuracy and relatively
sntaI1 thermal tail.
1.028
.~
1.022
20
.
80
80
,GO
TNE-ns
Figure 74. Zero to Full-Scale Settling
2-78 DIGITAL-TO-ANALOG CONVERTERS
'20
DIGITAL FEEDTHROUGH - As with any converter product,
a high-speed digital-to-analog converter is forced to exist on the
frontier between the noisy environment of high-speed· digital
logic and the sensitive analog domain. The problems of this
interfacing are particularly acute when demands of high speed
(greater than 10MHz switching times) and high precision (12
bits or more) are combined. No amount of design effort can
perfectly isolate the analog portions of a DAC from the spectral
components of a digital input signal with a 2ns risetime. Inevitably,
once this digital signal is brought onto the chip, some of its
higher frequency components will find their way to the sensitive
analog nodes, producing a digital feedthrough glitch. To minimize
the exposure to this effect, the AD568 has intentionally omitted
the on-board latches that have been included in many slower
DACs. This not only reduces the overall level of digital activity
on chip, it also avoids bringing a latch clock pulse on board,
whose opposite edge inevitably produces a substantial glitch,
even when the DAC is not supposed to be changing codes.
Another path for digital noise to fmd its way onto a converter
chip is through the reference input pin. The completely internal
reference featured in the AD568 eliminates this noise input,
providing a greater degree of signal integrity in the analog portions
of the chip.
DATA SKEW - The AD568, like many of its slower predecessors,
essentially uses each digital input line to switch a separate,
weighted current to either the output (lOUT) or some other node
(ANALOG COM). If the input bits are not changed simultaneously, or if the different DAC bits switch at different speeds,
then the DAC output current will momentarily take on some
incorrect value. This effect is particularly troublesome at the
"carry points", where the DAC output is to change by only one
LSB, but several of the larger current sources must be switched
to realize this change. Data skew can allow the DAC output to
move a substantial amount towards full scale or zero (depending
upon the direction of the skew) when only a small transition is
desired. Great care was taken in the design and layout of the
ADS68 to ensure that switching times of the DAC switches are
symmetrical and that the length of the input data lines are short
and well matched. The glitch-sensitive user should be equally
diligent about minimizing the data skew at the ADS68's inputs,
particularly for the 4 or 5 most significant bits. This can be
achieved by using the proper logic family and gate to drive the
DAC, and keeping the interconnect lines between the logic
outputs and the DAC inputs as short and as well matched as
possible, particularly for the most significant bits. The top 6
bits should be driven from the same latch chip if latches are
used ..
Glitch Reduction Schemes
BIT-DESKEWING - Even carefully laid-out boards using the
proper driving logic may suffer from some degree of data-skew
induced glitch. One common approach to reducing this effect is
to add some appropriate capacitance (usually several pF) to each
of the 2 or 3 most significant bits. The exact value of each capacitor
for a given application should be determined experimentally, as
it will be dependent on circuit board layout and the type of
driving logic used. Table II presents a few examples of how the
glitch impulse may be reduced through passive deskewing.
AD568
BIT DELAY GLITCH REDUCTION EXAMPLES'
Uncompensated Glitch
Modified
Threshold2
74HCIS8
3S0pV-s
1.7V
ISOpV-s
74S158
850pV-s
l.OV
200pV-s
74FI58
lO00pV-s
I.3V
480pV-s
Uncompensated Glitch
Compensation
Used
Compensated Glitch
Logic
Family
Gate
74157
3S0pV-s
C2=5pF
250pV-s
HCMOS
74158
850pV-s
RI =son,cl =7pF 600pV-s
STTL
FAST
Logic
Familv
Gate
HCMOS
STTL
THRESHOLD SHIFT FOR GLITCH IMPROVEMENT'
NOTE
I Measurements were made using a modified version of the fixture shown in
Figure 13, with resistors and capacitors placed as shown in Figure 15.
Resistance and capacitance values were set to zero except as noted.
Table II.
As Figure 1S indicates, in some cases it may prove useful to
place a few hundred ohms of series resistance in the input line
to enhance the delay effect. This approach also helps to reduce
some of the digital feedthrough glitch, as the higher frequency
spectral components are being filtered out of the most significant
bits' digital inputs.
D~~~:G -#iIr-"""'....~
lOGIC
A0568
Figure 15. R-C Bit Deskewing Scheme
THRESHOLD SHIFT - It is also possible to reduce the data
skew by shifting the level of logic voltage threshold, VTH (Pin
13). This can be readily accomplished by inserting some resistance
between the THRESHOLD COM pin (Pin 14) and ground, as
in Figure 16. To generate threshold voltages below I.4V, Pin 13
may be directly driven with a voltage source, leaving Pin 14 tied
to the ground plane. As Note 2 in Table III indicates, lowering
the threshold voltage may reduce output voltage compliance
below the specified limits, which may be of concern in an unbuffered voltage output topology.
Table III shows the glitch reduction achieved by shifting the
threshold voltage for HCMOS, STTL, and FAST logic.
SELECTING RA AND RB:
RA + RB = 5V/3.6mA
THRESHOLD VOLTAGE = V TH = 1.4V + (3.6mA x RBI
ADS6S
I-_......;;;;.~
Resulting
Glitch
NOTES
I Measurements made on a modifu:d version of the circuit shown in
Figure 13, with a IV full scale.
2Use care in any scheme that lowers the threshold voltage since the
output voltage compliance of the DAC is sensitive to this voltage.
[f the DAC is to be operated in the Voltage output mode, it is strongly
suggested that the threshold voltage be set at least 200mVabove
the OUtput voltage full scale.
Table III.
Deglitching
Some applications may prove so sensitive to glitch impulse that
reduction of glitch impulse by an order of magnitude or more is
required. In order to realize glitch impulses this low, some sort
of sample-and-hold amplifier (SHA)-based deglitching scheme
must be used.
There are high-speed SHAs available with specifications sufficient
to deglitch the ADS68, however most are hybrid in design at
costs which can be prohibitive. A high performance, low cost
alternative shown in Figure 17 is a discrete SHA utilizing a
high-speed monolithic op amp and high-speed DMOS FET
switches.
This SHA circuit uses the inverting integrator architecture. The
AD841 operational amplifier used (300MHz gain bandwidth
product) is fabricated on the same high-speed process as the
AD568. The time constant formed by the 200n resistor and the
100pF capacitor determines the acquisition time and also band
limits the output signal to eliminate slew induced distortion.
A discrete drive circuit is used to achieve the best performance
from the SDSOOO quad DMOS switch. This switch driving cell
is composed of MPSS71 RF npn transistors and an MC10124
TTL to ECL translator. Using this technique provides both
high speed and highly symmetrical drive signals for the SDSOOO
switches. The switches are arranged in a single-throw double-pole
(SPDT) configuration. The 360pF "flyback" capacitor is switched
to the op amp summing junction during the hold mode to keep
switching transients from feeding to the output. This capacitor
is grounded during sample mode to minimize its effect on acquisition time.
Circuit layout for a high speed SHA is almost as critical as the
design itself. Figure 17 shows a recommended layout of the
deglitching cell for a double sided printed circuit board. The
layout is very compact with care taken that all critical signal
paths are short.
C1: 1000pFCHIPCAPACITOR
Figure 16. Positive Threshold Voltage Shift
DIGITAL- TO-ANALOG CONVERTERS 2-79
II
referred to this node and thus it becomes the "high quality"
ground for the ADS68. The REFERENCE COMMON (and
Bipolar offset when not used), should also be connected to this
node.
All of the current that flows into the VTH terminal (Pin 13)
.··rr
from the resistor tied to the SV logic supply (or other convenient
positive supply) flows out the THRESHOLD COMMON (Pin
14). This ground pin should be returned directly to the digital
ground plane on its own individual line.
The + SV logic supply should be decoupled to the THRESHOLD
COMMON .
-,sv
,...
.
~' "
TO PIN 2
""'"
Figure 17. High Performance Deglitcher
Grounding Rules
The ADS68 brings out separate reference, output, and digital
power grounds. This allows for optimum management of signal
ground currents for low noise and high-speed settling performance.
The separate ground returns are provided to minimize changes
in current flow in the analog signal paths. In this way; logic
return currents are not summed into the same return path with
the analog signals.
Because the VTH pin is connected directly to the DAC switches
it should be decoupled to the analog output signal common.
In order to preserve proper operation of the DAC switches, the
digital and analog grounds need to eventually be tied together.
This connection between the ground planes should be made
within 1I2" of the DAC.
The Use of Ground and Power Planes
If used properly, ground planes can perform a myriad of functions
on high-speed circuit boards: bypassing, shielding, current
transpon, etc. In mixed signal design, the analog and digital
ponions of the board should be distinct from one another, with
the analog ground plane covering analog signal traces and the
digital ground plane confined to areas covering digital interconnect.
It is important to understand which supply and signal currents
are flowing in which grounds so that they may be returned to
the proper power supply in the best possible way.
The majority of the current that flows into the Vcc supply
(Pin 24) flows out (depending on the DAC input code) either
the ANALOG COMMON (Pin 18), the LADDER COMMON
(Pin 17), and/or lOUT (Pin: 20).
The current in the LADDER COMMON is configured to be
code independent when the output current is being summed
into a virtual ground. If lOUT is operated into its own output
impedance (or in any unbuffered voltage output mode) the
current in LADDER COMMON will become partially code
dependent.
The current in the ANALOG COMMON (Pin 18) is an approximate complement of the current in lOUT' i.e., zero when the
DAC is at full scale ~d approximately lOrnA at zero input
code.
Component Side
A relatively constant current (not code dependent) flows out the
REFERENCE COMMON (Pin 23).
The current flowing out of the VEE supply (Pin 22) comes from
a combination of reference ground and BIPOLAR OFFSET
(Pin 21). The plus and minus ISV supplies are decoupled to the
REFERENCE COMMON.
The ground side of the load resistor RL> ANALOG COMMON
and LADDER COMMON should be tied together as close to
the package pins as possible. The analog output voltage is then
Foil Side
Figure 18. Printed Circuit Board Layout
2-80 DIGITAL-TO-ANALOG CONVERTERS
AD568
The two ground planes should be connected at or near the
DAC. Care should be taken to insure that the ground plane is
uninterrupted over crucial signal paths. On the digital side, this
includes the digital input lines running to the DAC and any
clock lines. On the analog side, this includes the DAC output
signal as well as the supply feeders. The use of wide runs or
planes in the routing of power lines is also recommended. This
serves the dual function of providing a low series impedance
power supply to the part as well as providing some "free" capacitive
decoupling to the appropriate ground plane. Figure 18 illustrates
the PC board used for the circuit shown in Figure 13. This
design was constructed on a simple two-layer board and illustrates
many of the points discussed above. If more layers of interconnect
are available, even better results are possible.
Using The Right Bypass Capacitors
Probably the most important external components associated
with any high-speed design are the capacitors used to bypass the
power supplies. Both selection and placement of these capacitors
can be critical and, to a large extent, dependent upon the specifics
of the system configurations. The dominant consideration in
selection of bypass capacitors for the ADS68 is minimization of
series resistance and inductance. Many capacitors will begin to
look inductive at 20MHz and above, the very frequencies we are
most interested in bypassing. Ceramic and film-type capacitors
generally feature lower series inductance than tantalum or elec-
trolytic types. A few general rules are of universal use when
approaching the problem of bypassing:
Bypass capacitors should be installed on the printed circuit
board- with the shortest possible leads consistent with reliable
construction. This helps to minimize series inductance in the
leads. Chip capacitors are optimal in this respect.
Some series inductance between the DAC supply pins and the
power supply plane often helps to filter out high-frequency
power supply noise. This inductance can be generated using a
small ferrite bead.
High-Speed Interconnect and Routing
It is essential that care be taken in the signal and power ground
circuits to avoid inducing extraneous voltage drops in the signal
ground paths. It is suggested that all connections be short and
direct, and as physically close to the package as possible, so that
the length of any conduction path shared by external components
will be minimized. When runs exceed an inch or so in length,
some type of tertnination resistor may be required. The necessity
and value of this resistor will be dependent upon the logic family
used.
For maximum ac performance, the DAC should be mounted
directly to the circuit board; sockets should not be used as they
introduce unwanted capacitive coupling between adjacent pins
of the device.
Applications
1,,5, 12-BIT SUCCESSIVE APPROXIMATION AID
CONVERTER
The ADS68's unique combination of high speed and true 12-bit
accuracy can be used to construct a 12-bit SAR-type AID converter
with a sub-!,-s conversion time. Figure 19 shows the configuration
used for this application. A negative analog input voltage is
converted into current and brought into a summing junction
with the DAC current. This summing junction is bidirectionally
clamped with two Shottky diodes to limit its voltage excursion
from ground. This voltage is differentially amplified and passed
to a high-speed comparator. The comparator output is latched
and fed back to the successive approximation register, which is
then clocked to generate the next set of codes for the DAC.
o TO
v,.
- 10.24V
+5V
+5V
PARALLEL DATA
OUT
===:::
L
01, D2 THOMPSON CSFBAR - 10
OR SIMILAR SCHOTTKY DIODE
CONVERSiON COMPLETE
START CONVERT
CHtPENABU
01 -
as RCA CA3127 ARRAY AS PEA
"BUILD YOUR OWN AID CONVERTER
FOR OPTIMUM PERFORMANCE," EON.
CLOCK
MARCH 20, 1986, PAGE 195.
-
Figure 19. AD568 1p.s Successive Approximation AID Application
DIGITAL-TO-ANALOG CONVERTERS 2-81
HIGH-SPEED MULTIPLYING DAC
CirCuit Details
Figure 20 shows an approximate timing budget for the AID
converter. If 12 cycles are to be completed in l,..s, approximately
80ns is allowed for each cycle. Since the Shottky diodes clamp
the voltage of the summing junction, the DAC settling time
approaches the current-settling value of 35ns, and hence uses up
iess than half the timing budget.
A powerful use for the AD568 is found in multiplying applications,
where the DAC controls the amplitude of a high-speed signal.
Specifically, using the AD568 as the control voltage input signal
for the ADS39 60MHz analog multiplier and AD5539 wide-band
op amp, a high-speed multiplying DAC can be built.
In the application shown in Figure 21, the AD568 is used in a
buffered voltage output mode to generate the input to the AD539's
control channel. The speed of the AD568 allows oversampJing
of the control signal waveform voltage, thereby providing increased
spectral purity of the amplitude envelope that modulates the
analog input channels.
To maintain simplicity, a simple clock is used that runs at a
constant rate throughout the conversion, with a duty cycle of
approximately 90%. If absolute speed is wortIit the additional
complexity, the clock frequency can be increased as the conversion
progresses since the DAC must settle from increasingly smaller
steps.
The AD568 is configured in the unbuffered unipolar output
mode. The internal200n load resistor creates the O-IV FS
output signal, which is buffered and amplified to a 0-3V range
suitable for the control channel of the ADS39.
When seeking a cycle time of less than lOOns, the delays generated
by the older generation SAR registers become problematic.
Newer, higher speed SAR logic chips are becoming available in
the classic 2504 pinout that cuts the logic overhead in half. One
example of this is Zyrel's ZR2504.
A soon input impedance exists at Pin I, the input channel. To
provide a buffer for the 0-1 V output signal from the AD568
looking into the impedance and to achieve the full-scale range,
the AD84I, high-speed, fast settling op amp is included. The
gain of 3 is achieved with a 2kn resistor configured in follower
mode with a Ikn pot and soon resistor. A 20kn pot with connections to Pins 3, 4 and 12 is provided for offset trim.
Finding a comparator capable of keeping up with this DAC
arrangement is fairly difficult: it must respond to an overdrive
of 250,...V (ILSB) in less than 2Sns. Since no inexpensive comparator exists with these specs, special arrangements must be
made. The LTIOl6 comparator provides relatively quick response,
but requires at least SmV of overdrive to maintain this speed. A
discrete preamplifier may be used to amplify the summing junction
voltage to sufficiently overdrive the comparator. Care must be
exercised in the layout of the preamp/comparator block to avoid
introducing comparator instability with the preamp's additional
The AD539 can accept two separate input signals, each with a
nominal full-scale voltage range of ± 2V. Each signal can then
be simultaneously controlled by the AD568 signal at the common
input channel, Vx . The current outputs from the two signal
channels, Pins 11 and 14, applied to the ADSS39 in a subtracting
configuration, provide the voltage output signal:
gain.
SAR
DELAY
DAC SETTLING
\10ns \
35ns
D
PREAMP COMPARATOR
DELAY DELAY
15ns
-
VY2
2V
(0 '" D '" 4095)
For applications where only a single channel is involved, channel
2, VY2 , is tied to ground. This provides:
\10ns \10ns \
LJ
VYl
VOUT = 4096 x
CLOCK
PULSE
D
VY1
VOUT = 4096 x 2V
(0", D '" 4095)
I
o
10ns
20ns
30ns
40n5
50n5
&Ons
70ns
i
t
START OF
CLOCK CYCLE
Some AD539 circuit details: The control amplifier compensation
capacitor for Pin 2, Ce, must have a minimum value of 3000pF
to provide circuit stability. For improved bandwidth and feedthrough, the feedthrough capacitor between Pins I and 2 should
be 5-20% of Ce. A Schottky diode at Pin 2 can improve recovery
time from small negative values ofVx . Lead lengths along the
path of the high-speed signal from AD568 should be kept at a
minimum .
80ns
STAtTOFNEXT
CLOCK CYCLE
LATCH COMPARATOR
Figure 20. Typical Clock Cycle for a 1p,s SAR AID Converter
• v,
'¢'
§!!2!!!.~CONNECnONTOGROUNDPl.ANE.
Figure 21. Wideband Digitally Controlled Multiplier
2-82 DIGITAL-TO-ANALOG CONVERTERS
l6-Bit Monotonic
Voltage Output OfA
A0569 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
Guaranteed 16-Bit Monotonicity
Monolithic BiMOS II Construction
±O.01% Typical Nonlinearity
8- and 16-Bit Bus Compatibility
3,..s Settling to 16-Bits
Low Drift
Low Power
Low Noise
AD569 FUNCTIONAL BLOCK DIAGRAM
+VIEF FORCE
R.
+VREF
SENSE
ADS.9
R256
0255
n254
R512
MS.
SEGMENT
SELECTION
APPLICATIONS
Robotics
Closed-Loop Positioning
High-Resolution ADCs
Microprocessor-Based Process Control
R3
R'
R'
-VR1!F SENSE
RA
-VRI;:F
PRODUCT DESCRIPTION
The AD569 is a monolithic l6-bit digital-to-analog converter
(DAC) manufactured in Analog Devices' BiMOS II process.
BiMOS II allows the fabrication of low power CMOS logic
functions on the same chip as high precision bipolar linear circuitry.
The AD569 chip includes two resistor strings, selector switches,
decoding logic, buffer amplifiers, and double-buffered input
latches.
The AD569's voltage-segmented architecture insures l6-bit
monotonicity over time and temperature. Integral nonlinearity is
maintained at ±0.01%, while differential nonlinearity is
± 0.0004%. The on-chip, high-speed buffer amplifiers provide a
voltage output settling time of 3ILs to within ±O.OOl% for a
full-scale step.
The reference input voltage which determines the output range
can be either unipolar or bipolar. Nominal reference range is
± 5V and separate reference force and sense connections are
provided for high accuracy applications. The AD569 can operate
with an ac reference in multiplying applications.
FORCE
LOAC
co
HBE
LiE
PRODUCT HIGHLIGHTS
1. Monotonicity to 16 bits is insured by the AD569's voltagesegmented architecture.
2. The output range is ratiometric to an external reference or ac
signal. Gain error and gain drift of the AD569 are negligible.
3. The AD569's versatile data input structure allows loading
from 8- and l6-bit buses.
4. The on-chip output buffer amplifier can supply ± SV into a
lk!l load, and can drive capacitive loads of up to lOOOpF.
5. Kelvin connections to the reference inputs preserve the gain
and offset accuracy of the transfer function in the presence of
wiring resistances and ground currents.
Data may be loaded into the AD569's input latches from 8- and
l6-bit buses. The double-buffered structure simplifies 8-bit bus
interfacing and allows multiple DACs to be loaded asynchronously
and updated simultaneously. Four TTLILSTTLl5V CMOScompatible signals control the latches: CS, LBE, HBE, and
LDAC.
The AD569 is available in five grades: J and K versions are
specified from 0 to + 70°C and are packaged in a 28-pin plastic
DIP and 28-pin PLCC package; AD and BD versions are specified
from - 25°C to + 85°C and are packaged in a 28-pin ceramic
DIP. The SD version, also in a 28-pin ceramic DIP, is specified
from - 55°C to + 125°C.
DIGITAL-TO-ANALOG CONVERTERS 2-83
11
SPECIFICATIONS
Model
erA
= +25"1:, +Ys = +12Y, -Ys = -12Y, +VIIS' = +5Y, -Y = -5Y, unless otherwise noted)
REF
AD569JN/AD
Parameter
RESOLUTION
LOGIC INPUTS
VIH (Logic "1")
VIL (Logic "0")
IIH (VIH =5.5V)
IlL (VIL =OV)
MiD
Typ
2.0
0
5.5
0.8
10
10
±0.02
±0.02
±1I2
±1I2
TmintoTmax
Bipolar Zero2
T min to Tmax
OUTPUT CHARACTERISTICS
Voltage
Capacitive Load
Resistive Load
Short Circuit Current
POWER SUPPLIES
Voltage
+Vs
-Vs
Current
+Is
-Is
Power Supply Sensitivity'
+ 1O.8V:s + Vs:S + 13.2V
-1O.8V2: - Vs2: - 13.2V
TEMPERATURE RANGE
Specified
]N,KN,]P,KP
AD,BD
SD
Storage
]N,KN,]P,KP
AD,BD,SD
MiD
Typ
16
TRANSFER FUNCTION
CHARACTERISTICS
Integral Nonlinearity
TmintoT""",
Differential Nonlinearity
TmintoT""",
Unipolar Offset'
TmintoT""",
Bipolar Offset'
TmintoTmax
Full Scale Error'
REFERENCE INPUT
+ VREF Range'
- VREF Range'
Resistance
AD569KNIBD
Max
-5
-5
15
20
-5
2.0
0
5.5
0.8
10
10
±0.0l
±0.020
± 114
±1I2
+5
+5
25
-5
-5
15
+5
1000
-5
+13.2
-13.2
+9
-9
+13
-13
±0.5
±1
±2
±3
0
-25
-65
-65
+70
+85
+150
+150
NOTES
'FSR stands for Full·Scale Range,and is IOVfora -5to +5Vspan.
'Refer to Deftoitions section.
'For operation with supplies other than ± 12V, refer to the Power Supply
and Reference Voltage Range Section.
'Measured between + VREP Force and - VREP Force.
'Sensitivity of Full-Scale Error due to changes in + Vs and sensitivity
of Offsetto chall8es in - Vs.
Specifications subject to chRll8< without notice.
2-84 DIGITAL-TO-ANALOG CONVERTERS
Max
Units
16
Bits
5.5
0.8
10
10
Volts
Volts
,.A
,.A
±0.04
±0.04
±1
±1
±SOO
±750
±SOO
±7SO
±350
±450
±0.04
±O.04
%FSR 1
%FSR
LSB
LSB
ILV
ILV
ILV
ILV
ILV
ILV
%FSR
%FSR
+5
+5
25
Volts
Volts
20
+5
1000
Volts
pF
kO
rnA
+12
-12
+13.2
-13.2
Volts
Volts
2.0
0
±112
±1
±350
±450
±350
±450
±350
±450
±0.024
±O.O24
+5
+5
25
-5
-5
15
+5
1000
-5
+10.8
-10.8
0
-25
-65
-65
20
I
10
+ 12
-12
Typ
±0.024
±O.O24
1
10
+10.8
-10.8
Min
16
±0.04
±0.04
±1
±1
±500
±7SO
±500
±7SO
±3SO
±4SO
±0.04
±0.04
1
AD569SD
Max
10
+10.8
-10.8
k04
+12
-12
+13.2
-13.2
+9
+13
-13
+9
-9
-9
+13
-13
rnA
rnA
±0.5
±1
±2
±3
±0.5
±I
±2
±3
pprn/%
pprn/%
-55
+125
'C
'C
'C
-65
+150
'C
'C
+70
+85
+ 150
+150
Specifications shown in boldface are tested on all production units at fmal
electrical test. Results from those tests are used to calculate outgoing quality
levels. All toin and max specif1C8tions are guaranteed, although only those
shown in boldface are tested on all production units.
AD569
AC PERFORMANCE CHARACTERISTICS
1lIese charac:lllrislics are included fur IJesi&n Guidance Only and an not subject III tast.
+Vs = + 12Y; -Vs = -12Y; +VREF = +5V; -VREF = -5Yexceptwherastalad.
Parameter
Limit
Units
Test Conditions/Comments
Output Voltage Settling
(Time to ±O.OOI%FS
ForFSStep)
5
3
No Load Applied
(DAC output measured from falling edge of LDAC.)
VotITLoad = IkO,CLOAD = lOOOpF.
(DAC output measured from falling edge of LDAC.)
Measured with VREF = OV. DAC registers alternatively loaded
with input codes of8000H and OFFFH (worst-case
transition). Load = lkO.
+ VREF = IVrms 10kHz sine wave,
-VREF=OV
Measured between VOtIT and - V REF
Digitsl-to-Analog Glitch
Impulse
500
ILsmax
ILstyp
ILsmax
ILS typ
nV-sectyp
Multiplying Feedthrough
-100
dB max
Output Noise Voltage
Density (lkHz-IMHz)
40
nV/YHZtyp
6
4
TIMING CHARACTERISTlCSc+Vs = +l2Y,-Vs= -l2V,TmintoTmaxl
Parameter
Case A!
twc
tsc
tHC
CaseB2
twa
tSB
tHB
tWD
CaseC 3
tws
tss
tHS
Limit
Units
Test Conditions/Comments
70
60
0
nsmin
nsmin
nsmin
I SOns Pulse on HBE, LBE, and LDAC
CS Pulse Width
CS Data Setup Time
CS Data Hold Time
60
30
20
70
nsmin
nsmin
nsmin
nsmin
lOOns Pulse on CS
HBE, LBE Pulse Width
HBE, LBE Data Setup Time
HBE, LBE Data Hold Time
LDAC Pulse Width
70
30
10
nsmin
nsmin
nsmin
lOOns Pulse on CS
LDAC & HBE, LBE Pulse Width
LDAC & HBE, LBE Data Setup Time
LDAC & HBE, LBE Data Hold Time
NOTES
'Write strobe applied toCS as shown in Figure 20a. Address decoding defines which
register(s) data is strobed into (see Figure I).
'Write strobe applied to HBE and/or LBE as in Figure 19 or applied to LDAC
separately. DAC base address applied toCS (see F~ I).
'Write strobe applied to LDAC and either HBE or LBE for synchronous load of 16-bit DAC
register with one ofthe 8-bit first-rank registers as shown in Figure 20b (see Figure 2).
Figure 1_ AD569 Timing Diagram
Figure 2. Timing for Synchronous Load of DAC Register
DIGITAL-TO-ANALOG CONVERTERS 2-85
ABSOLUTE MAXIMUM RATlNGS*
(TA = + lSOC unless otherwise noted)
. + I8V, -O.3V
+ Vs (Pin 1) to GND (Pin 18)
. -I8V, +O.3V
- Vs (Pin 28) to GND (Pin 18)
+26.4V, -O.3V
+ Vs (Pin 1) to - Vs (Pin 28) .
Digital Inputs
(Pins 4-14, 19-27) to GND (Pin 18)
+ Vs , -O.3V
+ VREF Force (Pin 3) to + VREF Sense (Pin 2)
± 16.SV
- VREF Force (Pin IS) to - VREF Sense (Pin 16)
± 16.5V
VREF Force (Pins 3, IS) to GND (Pin 18) . . • .
. . ±Vs
VREF Sense (Pins 2,16) to GND (Pin 18) . • . .
. . ±Vs
Your (Pin 17) . . . .
. .• indefinite Short to GND
Momentary Short to +Vs, -Vs
Power Dissipation (Any Package) . . . . •
Operating Temperature Range
Commercial Plastic UN, KN Versions) .
Industrial Ceramic (AD, BD Versions)
Extended Ceramic (SD Versions) ..
Storage Temperature •. . . . . . . .
Lead Temperature (Soldering, IOsecs)
. .1000mW
o to +70°C
- 2SOC to + 8SOC
- SSOC to + 125°C
-6SOC to + ISOOC
. . . • . +300"C
*Stresses above those listed under "Absolute Maximum Ratings" may
cause pel"lDl\!lCllt damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affcct device reliability.
ESD SENSITIVITY
The ADS69 features input protection circuitry consisting oflarge "distributed" diodes and polysilicon
series resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy
pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the ADS69 bas been
classified as a Category A device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment
and discharge without detection. Unused devices must be stored in conductive foam or shunts,
and the foam should be discharged to the destination socket before devices are removed. For
further information on ESD precaution&, refer to Analog Devices' ESD Prevention Manual.
WARNING!
0
*~DEVICE
PIN DESIGNATIONS
!I
is
iJ IJ :: :: ~
+ + +
I
I
C
a;
Q
'282728
o
AD569
TOP VIEW
(Not to Scale)
DB13
(MS8) 0815
cs
ORDERING INFORMATION
Integral Nonlinearity
Differential Nonlinearity
Temperature Range and Package Options*
+ 25°C
Tmbl-T """,
+ 25°C
Tmbl-T """,
Plastic (N-28)
Oto +700c
±O.04%
±O.O24%
±O.04%
±O.O24%
±ILSB
±1I2LSB
±ILSB
±ILSB
AD569JN,JP
ADS69KN,KP
*See Section 14 for package outline information.
~-86
D/GITAt.-TO-ANALOG CONVERTERS
Ceramic (D-28)
- 25°C to + 85°
Ceramic (D-28)
- 55°C to + 125°C
ADS69AD
ADS69BD
ADS69SD
-
AD569
FUNCTIONAL DESCRIPTION
The AD569 consists of two resistor strings, each of which is
divided into 256 equal segments (see Figure 3). The 8MSBs of
the digital input word select one of the 256 segments on the
first string. The taps at the top and bottom of the selected segment
are connected to the inputs of the two buffer amplifiers A I and
A2. These amplifiers exhibit extremely high CMRR and low
bias current, and thus accurately preserve the voltages at the top
and bottom of the segment. The buffered voltages from the
segment endpoints are applied across the second resistor string,
where the 8LSBs of the digital input word select one of the 256
taps. Output amplifier A3 buffers this voltage and delivers it to
the output.
Buffer amplifiers Al and A2 leap-frog up the first string to
preserve monotonicity at the segment boundaries. For example,
when increasing the digital code from OOFFH to OIOOH, (the
first segment boundary), Al remains connected to the same tap
on the flI'St resistor, while A2 jumps over it and is connected to
the tap which becomes the top of the next segment. This design
guarantees monotonicity even if the amplifiers have offset voltages.
In fact, amplifier offset only contributes to integral linearity
error.
CAUTION
It is generally considered good engineering practice to avoid
inserting integrated circuits into powered-up sockets. This
guideline is especially important with the AD569. An empty,
powered-up socket configures external buffer amplifiers in an
ANALOG CIRCUIT DETAILS
Definitions
LINEARITY ERROR: Analog Devices defines linearity error
as the maximum deviation of the actual, adjusted DAC output
from the ideal output (a straight line drawn from 0 to FS-ILSB)
for any bit combination. The AD569's linearity is primarily
limited by resistor uniformity in the flI'St divider (upper byte of
16-bit input). The plot in Figure 4 shows the AD569's typical
linearity error across the entire output range to be within ± 0.01%
of full scale. At 25"C the maximum linearity error for the
AD569]N, AD and SD grades is specified to be ±0.04%, and
± 0.024% for the KN and BD versions.
% ERROR
0.036
0.03
0.024
0.018
0.012
0.006
""'II\.
+VREF
FORCE
..
+V"Ef SENSE I>--+-~
AD569
0256
.'55
RS12
.,,.
You,
I
-V"fF SENSE ~-t--;
-VItIF
FORCE
LDAC .......~---..
0815 • • •
DB8
Figure 3. AD569 Block Diagram
open-loop mode, forcing their outputs to be at the positive or
negative rail. This condition may result in a 1arge current surge
betWeen the reference force and sense terminals. This current
surge may permanently damage the AD569.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs. All
versions of the AD569 are monotonic over their full operating
temperature range.
DIFFERENTIAL NONLINEARITY: DNL is the measure of
the change in the analog output, normalized to full scale, associated
with a ILSB change in the digital input code. Monotonic behavior
requires that the differential linearity error be less than ILSB
over the temperature range of interest. For example, for a ± 5V
output range, a change of lLSB in digital input code should
result in a 152,...V change in the analog output (lLSB = lOY!
65,536). If the change is actually 38,...V, however, the differential
linearity error would be - 114,...V, or - 3/4LSB. By leapfrogging
the buffer amplifier taps on the first divider, a typical AD569
keeps DNL within ± 38,...V (± 1I4LSB) around each of the 256
segment boundaries defined by the upper byte of the input
word (see Figure 5). Within the second divider, DNL also
typically remains less than ± 38,...V as shown in Figure 6. Since
the second divider is independent of absolute voltage, DNL is
the same within the rest of the 256 segments.
OFFSET ERROR: The difference between the actual analog
output and the ideal output (- VREF), with the inputs loaded
with all zeros is called the offset error. For the AD569, Unipolar
Offset is specified with OV applied to - VREF and Bipolar Offset
is specified with - 5V applied to - VREF • Either offset is trimmed
by adjusting the voltage applied to the - VREF terminals.
-0.006
-0.012
-0.018
-0.024
-0.03
-0.036
~ ~
i IIi IIIII
CODE (HEXI
Figure 4. Typical Linearity
~
II~ l
BIPOLAR ZERO ERROR: The deviation of the analog output
from the ideal half-scale output of O.OOOOV when the inputs are
loaded with 8000H is called the Bipolar Zero Error. For the
AD569, it is specified with ± 5V applied to the reference
terminals.
DIGITAL-TO-ANALOG CONVERTERS 2-87
DlGITAL-TO-ANALOG GLITCH IMPULSE: The charge
injected into the analog output when a new input is latched into
the DAC register gives rise to the Digital-ta-Analog Glitch Impulse.
Glitches can be due to either time skews between the input bits
or charge injection from the internal switches. Glitch Impulse
for the ADS69 is mainly due to charge injection, and is measured
with the refereoce connections tied to ground. It is specified as
the area of the glitch in n V-sees.
1&-BIT LSB
1_0
0.8
0.&
0.4
0.2
TOTAL ERROR: The worst-case Total Error is the sum of the
fixed full-scale and offset errors and the linearity error.
-0.2
-0.4
-0.6
-0.8
-1.0
o
~
c
200
2!
§
0
I I
0
~
goo
a §
0
2
! ! 8
goo
8
!
~
~
t
CODE (HEX)
Figure 5. Typical DNL at Segment Boundary Transitions
POWER SUPPLY AND REFERENCE VOLTAGE RANGES
The ADS69 is specified for operation with ± 12 volt power
supplies. With ± 10"10 power supply tolerances, the maximum
reference voltage range is ± 5 volts. Reference voltages up to
± 6 volts can be used but linearity will degrade if the supplies
approach their lower limits of ± 10.8 volts (12 volts - 10"10).
If ± 12 volt power supplies are unavailable in the system, several
alternative schemes may be used to obtain the needed supply
voltages. For example, in a system with ± 15V supplies, a single
Zener diode can be used to reduce one of the supplies to 9 volts
with the remaining one left at 15 volts. Figure 7a illustrates this
scheme. A IN753A or equivalent diode is an appropriate choice
for the task. Asymmetrical power supplies can be used since the
AD569's output is referenced to - VREF only and thus floats
relative to logic ground (GND, Pin 18). Assuming a worst-case
± 1.5 volt tolerance on both supplies (10"10 of IS volts), the
maximum reference voltage rauges would be + 6 and - 2 volts
for +Vs = +15Vand -Vs = -9V, and +210 -8 volts for
+Vs = 9Vand -Vs = -15V.
-0.2
-0.4
-0.&
-0.8
-1.0
~ ~ ~
i II
~
I "I i i
~
Ii
~ ~
CODE (HEX)
a. Segment 1
1&-BIT LSB
1.0
0.8
0.&
Alternately, two 3V Zener diodes or voltage regulators can be
used to drop each ± IS volt supply to ± 12 volts, respectively.
In Figure 7b, IN746A diodes are a good choice for this task.
A third method may be used if both ± IS volt and ± 5 volt
supplies are available. Figure 7c shows this approach. A combination of + Vs = + 15V and - Vs = - 5V can support a
refereoce range of 0 to 6 volts, while supplies of + Vs = + 5V
and - Vs = -15V can support a reference range of 0 to - 8
volts. Again, 100/0 power supply tolerances are assumed.
NOTE: Operation with + Vs = + SV alters the input latches'
operating conditions causing minimum write pulse widths to
extend to IlLS or more. Control signals CS, HBE, LBE, and
LDAC should, therefore, be tied low to render the latches
transparent.
0.4
No timing problems exist with operation at + Vs = 9Vand
- Vs = -ISV. However, 10% tolerances on these supplies
generate a worst-case condition at -Vs = -16.5Vand +Vs =
+ 7.5V (assuming + Vs is derived from a + 15V supply). Under
these conditions, write pulse widths can stretch to 200ns with
similar degradation of data setup and hold times. However,
± o. 7SV tolerances (± 5%) yield minimal effects on digital timing
with write pulse widths remaining below lOOns.
-0.4
-0.&
-0.8
-1.0
b. Segment 256
Figure 6. Typical DNL Within Segments
MULTIPLYING FEEDTHROUGH ERROR: This is the error
due to capacitive feedthrough from the refereoce to the output
with the input registers loaded with all ~_
FULL-SCALEEAAOR: The ADS69's voltage dividing architecture gives rise to a fIXed full-scale error which is independent
of the refereoce voltage •. This error is trimmed by adjusting the
voltage applied to the + V RBF terminals.
2-88 DIGITAL-TO-ANALOG CONVERTERS
Finally, Figure 7d illustrates the use of the combination of an
AD588 and ADS69 in a system with ± IS volt supplies. As
shown, the AD588 is connected to provide ± 5V to the reference
inputs of the AD569. It is doing double-duty by simultaneously
regulating the supply voltages for the AD569 through the use of
the level shifting zeners and transistors. This scheme utilizes the
capability of the outputs of the AD588 to source as well as sink
current. Two other benefits are realized by using this approach.
The first is that the AD569 is no longer directly connected to
the system power supplies. Output sensitivity to variations in
those supplies is, therefore, eliminated. The second benefit is
AD569
that, should a zener diode fail (a short circuit would be the most
likely failure), the supply voltage decreases. This differs from
the situation where the diode is used as a series regulator. In
that case, a failure would place the unregulated supply voltage
on the AD569 terminal.
+15V
-15V
a. Zener Regulates Negative Supply
+15V
-15V
b. Diodes Regulate Both Supplies
ANALOG CIRCUIT CONNECTIONS
The AD569 is intended for use in applications where high resolution and stability are critical. Designed as a multiplying DIA
converter, the AD569 may be used with a fixed dc reference or
an ac reference. V REF may be any voltage or combination of
voltages at + V FORCE and - VFORCE that remain within the
bounds set for reference voltages as discussed in the power
supply range section. Since the AD569 is a multiplying D/A
converter, its output voltage, Your, is proportional to the product •
of the digital input word and the voltage at the reference terminal.
The transfer function is Vour = D· V REF where D is the fractional
binary value of the digital word applied to the converter using
offset-binary coding. Therefore, the output will range from
- V REF for a digital input code of all zeros (OOOOW to + V REF
for an input code of all ones (FFFFw.
For applications where absolute accuracy is not critical, the
simple reference connection in Figure 8 can be used. Using only
the reference force inputs, this configuration maintains linearity
and 16-bit monotonicity, but introduces small, fixed offset and
gain errors. These errors are due to the voltage drops across
resistors RA and RB shown in Figure 9. With a 10V reference
voltage, the gain and offset errors will range from 80 to lOOmV.
Resistors RA and RB were included in the first resistor string to
avoid degraded linearity due to uneven current densities at the
string's endpoints. Similarly, linearity would degrade if the
reference voltage were connected across the reference sense
terminals. Note that the resistance between the force and sense
terminals cannot be measured with an ohmmeter; the layout of
the thin-film resistor string adds approximately 4kO of resistance
(Rs) at the sense tap.
+15V(+5Vi
+ 15V
-9V
-15V (-5VI
c. Use of:± 15Vand :±5V Supplies
Figure 8. Simple Reference Connection
d. AD5B8 Produces References and Supply Voltages
Figure 7. Power Supply Options
For those applications in which precision references and high
accuracy are critical, buffer amplifiers are used at + V REF and
- V REF as shown in Figure 10 to force the voltage across resistors
RI to R256. This insures that any errors induced by currents
flowing through the resistances of the package pins, bood wires,
aluminum interconnections, as well as RA and RB are minimized.
Suitable amplifiers are the AD517, AD OP-07, AD OP-27, or
the dual amplifier, the AD712. Errors will arise, however, as
the buffer amplifiers' bias currents flow through Rs (4kn). If
the bias currents produce such errors, resistance can be inserted
at the noninverting terminal (Rud of the buffer amplifiers to
compensate for the errors.
DIGITAL-TO-ANALOG CONVERTERS 2-89
+ VR£F FORCE o---"""'l
Ro
R.
+VAEF SENSE: 0-.....,.--1~--
R254
v
AD569
R3
R.
H.
••
H.
Ro
-VAEF SENSE o----1~--
H.
-VREFFORCE
0---.......
Figure 10. Reference Buffer Amplifier Connections
Figure 9. MSB Resistor Divider
Figures 11, 12, and 13 show reference configurations for various
output ranges. As shown in Figure 11; the pin-programmable
AD588 can be connected to provides uacking ± 5V outputs
with 1-3ppm/"C temperature stability. Buffer amplifiers are
included for direct connection to the AD569. The optional gain
and balance adjust trimmers allow bipolar offset and full-scale
errors to be nulled. In Figure 12, the low-cost ADS86 provides
+ SV reference. A dual op amp, the AD712, buffers the reference
input terminals preserving the absolute accuracy of the ADS69.
The optional noise-reduction capacitor and gain adjust trimmer
allow further elimination of errors. The low-cost ADS84 offers
2.SV, SV, 7.SV, and 10V options and can be connected for
± SV tracking outputs as shown in Figure 13. Again, an AD712
is used to buffer the reference input terminals.
_-!=2~::;========f=T==+··V
-12V
r-........
+5V
17 VOUT
-6VTO
'OOk
20 TURN
Figure 11. Ultra/ow Drift :!:5V Tracking Reference
+Vs
-Vs
17 V OOT
+5V
OTO
Figure 12. Low-Cost :!:5V Reference
2-90 D/G/TAL-TO-ANALOG CONVERTERS
AD569
112 AD712
tVa
-Vs
I
"VOUT
-5VTO
+5V
Figure 13. Low-Cost ±5V Tracking Reference
MULTIPLYING PERFORMANCE
Figure 14 illustrates the gain and phase characteristics of the
AD569 when operated io the multiplying mode. Full-power
bandwidth is shown io Figure 148 and the corresponding phase
shift is shown io Figure 14b. Performance is plotted for both a
full-scale ioput of FFFFH and an ioput of 8080H. An ioput
represents worst-case conditions because it places the buffer taps
at the midpoiots of both dividers. Figure IS illustrates the AD569's
ability to resolve 16-bits (where lLSB is 96dB below full scale)
while keeping the noise floor below - l30dB with an ac reference
of IV rms at 200Hz.
- ill +E:INHT CO~E ••••:~
~VOUT
WITH
LSBON
0.8
--wo..l cJJJLJ::
-10dB
-2OdB
'I'NOTAlIZED GAIN
TO . .81
N[\
~,
t-~
:t::: t~~I j]OV"l
1kHz
---VIN
10kHz
100kHz
1MHz
a. Bandwidth
_lLL SCAl! IllT ~ ••J
.
-
r
45
...
--,waftS, iTi~ CODE ....
..
135
a. Time Domain
N
1'. ~
,
,, 1\
"
.11_111
+V"EF t: SINE WAVE lOV pop
-V"EF"" GND
\
\
,...
1kHz
10kHz
,_Hz
b. Phase Shift
1MHz
b. Frequency Domain
Figure 15. Multiplying Mode Performance (Input Code
0001H )
Figure 14. Full Power Multiplying Performance
DIGITAL-TO-ANALOG CONVERTERS 2-91
Multiplying feedthrough is due to capacitive coupling between
the reference inputs and the output. As shown in Figure 16,
under worst-case conditions (hex input code 0000), feedthrough
remains below -100dB at ac reference frequencies up to
10kHz.
Figure 16. Multiplying Feedthrough
BYPASSING AND GROUNDING RULES
It is generally considered good engineering practice to use bypass
capacitors on the device supply voltage pins and to insert small
valued resistors in the supply lines to provide a measure of
decoupling between various circuits in a system. For the AD569,
bypass capacitors of at least 4.711-F and series resistors of 100
are recommended. The. supply voltage pins should be decoupled
to Pin 18.
NOISE
In high-resolution systems, noise is. often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 15211-V (- %dB).
Therefore, the noise floor· must remain below this level in the
frequency ranges of interest .. The ADS69's noise spectral density
is shown in Figures 17 and 18. The lowband noise spectrum in
Figure 17 shows the Ilf comer frequency at 1.2kHz and Figure
18 shows the wideband noise to be below 4OnVt'\I'HZ.
DIGITAL CIRCUIT CONNECTIONS
The AD569's truth table appears in Table I. The High Byte
Enable (HBE) and Low Byte Enable (LBE) inputs load the
upper and lower bytes of the 16-bit input when Chip Select
(CS) is valid (low). A·similar strobe to Load DAC (LDAC)
loads the 16-bit input into the DAC register and completes the
DAC update. The DAC register can either be loaded with a
separate write cycle or synchronously with either of the 8-bit
registers in the first rank. A simultaneous update of several
AD569s can be achieved by controlling their LDAC inputs with
a single control signal.
~
mm
ID" IE\C
1
X
0
X
1
0
X
1
1
0
1
0
1
0
0
OPERATION
X
1
1
No Operation
No Operation
Enable 8MSBs of First Rank
0
1
Enable 8LSBs of First Rank
1
0
Enable 16-Bit DAC Register
0
0
All Latches Transparent
Tablel. AD569 Truth Table
All four control inputs latches are level-triggered and active low.
When the DAC register is loaded directly from a bus, the da.!!.
at the digital inputs will be reflected in the output any time CS,
LDAC , LBE and HBE are low. Should this not be the desired
case, bring LDAC (or HBE or LBE) high before changing the
data. Alternately, use a second write cycle. to transfer the data to
the DAC register or delay the write strobe pulse until the appropriate data is valid. Be sure to observe the appropriate data
setup and hold times (see Timing Characteristics).
Whenever possible, the write strobe signal should be applied to
HBE and LBE with the AD569's decoded address applied to
CS. A minimum pulse width of 60ns at HBE and LBE allows
the AD569 to interface to the fastest microprocessors. Actually,
data can be latched with narrower pulses, but the data setup
and hold times must be lengthened.
16-Bit Microprocessor Interfaces
Since 16-bit microprocessors supply the AD569's complete 16bit input in one write cycle, the DAC register is often unnecessary.
If so, it should be made transparent by grounding LDAC. The
DAC's decoded address should be applied to CS, with the write
strobe applied to HBE and LBE as shown in the 68000 interface
in Figure 19.
DTACK~-------------,
A23
1-......---1
cs
AD569
AU
LDS--------------~~LBE
Figure 19. AD569/68000 Interface
Figure 18. Wideband Noise Spectrum
2-92 DIGITAL-TO-ANALOG CONVERTERS
AD569
WRITE
STROBE
Lr
least one address line is needed to differentiate between the
upper and lower bytes of the first rank (HBE and LBE). The
simplest method involves applying the two addresses directly to
HBE and LBE and strobing the data using CS as shown in
Figure 20a. However, the minimum pulse width on CS is 70ns
with a minimum data setup time of 60ns. If operation with a
shorter pulse width is required, the base address should be
applied to CS with an address line gated with the strobe signal
to supply the HBE and LBE inputs (see Figure 20b). However,
since the write pulse sees a propagation delay, the data still
must remain valid at least 20ns after tl1e rising edge of the delayed
write pulse.
CS
AD569
ADDRI
AN
ADDR
DECODE
A,
HiE
ADDR2
LBE
LDAC
a. Simple Interface
OUTPUT SETTLING
The ADS69's output buffer amplifier typically settles to within
±0.001% FS of its final value in 3fJ.s for a 10V step. Figure 21
shows settling for negative and positive full-scale steps with no
load applied. Capable of sourcing or sinking SmA, the output
buffer can also drive loads of IkH and 1000pF without loss of
stability. Typical settling to 0.001% under these worst-case
conditions is 4fJ.s, and is guaranteed to be a maximum of 6fJ.s.
The plots of Figure 21 were generated using the settling test
procedure developed specifically for the ADS69.
ADDR
DECODE
AD569
AO-------1~----+_~~}-----~
HBE
Subranging 16-Bit ADC
The subranging ADC shown in Figure 22 completes a conversion
in less than 20",s, including the sample-hold amplifier's sample
time. The sample-hold amplifier is allocated S",s to settle to 16
bits.
b. Fast Interface
Figure 20. 8-Bit Microprocessor Interface
8-Bit Microprocessor Interfaces
Since 8-bit microprocessors require two write cycles to provide
the ADS69's 16-bit input, the DAC register must be utilized. It
is most often loaded as the second byte enters the first rank of
latches. This synchronous load method, shown in Figure 20,
requires LDAC to be tied to either LBE or HBE, depending
upon the byte loading sequence. In either case, the propagation
delay through the first rank gives rise to longer timing requirements
as shown in Figure 2. If the DAC register (LDAC) is controlled
separately using a third write cycle, the minimum write pulse
on LDAC is 70ns, as shown in Figure I.
Two basic methods exist for interfacing the ADS69 to an 8-bit
microprocessor's address and control buses. In either case, at
2.0
1.0
0000 TO FFFF
>
E
E
,
w
...:::>
...>'"
w
...>'"
The ADS69's reference polarity is reversed so that a full-scale
output is - SV and zero scale is OV, thereby subtracting an 8bit approximation from the original sampled signal. The residue
from the analog subtraction is then quantized by the second 8bit flash conversion to recover the 8LSBs. Even though only the
ADS69's upper 8MSBs are used, the ADS69's accuracy defines
the AID converter's overall accuracy. Any errors are directly
reflected in the output.
FFFF TO 0000
>
3
Before the first flash, the analog input signal is routed through
the AD630 at a gain of + I. The lower AD7820 quantizes the
signal to the 8-bit level within 1.4fJ.s, and the 8-bit result is
routed to the ADS69 via a digital latch which holds the 8-bit
word for the ADS69 and the output logic.
1.0
'"
Z
'"
Z
0.001% FS
it
it
:IE
:IE
If
...
0
0
0:
0:
-1.0
0:
0
0
0:
0:
0:
a:
w
w
-1.0
-2.0
4
10
"
12
13
14
15
2
4
TIME - ".
6
8
10
II
12
13
14
15
TIME- ",
a. Turn-On Settling
b. Turn-Off Settling
Figure 21. Full-Scale Output Settling
DIGITAL-TO-ANALOG CONVERTERS 2-93
•
Preceding the second flash, the residue signal must be amplified
by a factor of 256. The OP-37 provides a gain of 25.6 and the
AD630 provides another gain of 10. In this case, the AD630
acts as a gain element as well as a channel control switch. The
second flash conversion yields a 9-bit word. This provides one
extra bit of overlap for digital correction of any errors that occurred
in the first flash. The correction bit is digitally added to the
first flash before the entire 16-bit output is strobed into the
output register.
V REF
-,.-o1H.-+......-v:..::,..'"!
Wii
= +5V
DIG OUT 8
t'Rc::D'--_--,
TIMING & CONTROL
Figure 22. 16-8it Subranging ADC
2-94 DIGITAL-TO-ANALOG CONVERTERS
Single Supply
12-Bit DACPORT
AD662 I
r'IIIIANALOG
WDEVICES
FEATURES
Complete 12-Bit DIA Function
On-Chip Output Amplifier
Internal High Stability Voltage Reference
Single +5 V Operation
Settling Time: 3 ,,"5 to 1/2 LSB
Monotonicity Guaranteed Over Temperature
Fast Digital Interface
Low Power Consumption: 55 mW
TTLI5 V CMOS Compatible Logic Inputs
20-Pin Cerdip and Plastic Packages
PRODUCT DESCRIPTION
The AD662 DACPORT'· is a complete 12-bit voltage output
DAC specified to operate on a single +5 V power supply. The
converter combines 1023 individual current sources and a 2-bit
binary weighted DAC, high stability voltage reference, and an
on-chip output amplifier to achieve 12-bit resolution and monotonicity over temperature.
Microprocessor compatibility is accomplished with
""...._ .••
data latch, allowing a direct interface be
16-bit digital bus. The latch respo
35 ns, for easy use with the fastest
AD662 FUNCTIONAL BLOCK DIAGRAM
+5V
+5V
DVoo
AV DO
AGND
DGND
PRODUCT HIGHLIGHTS
I. The AD662 is a complete voltage output DAC with a voltage
reference, an output amplifier, and digital latches on a single
chip.
timized for single
+5 V supply
to write pulse widths as short as
rect interface with the industry's fastest
Functional completeness of the 12-bit DA
designers of single supply systems with a co
solution that was previously unavailable.
The AD662 is available in two performance grades over co
mercial, industrial, and military temperature ranges. The d
is available in 20-pin plastic and cerdip packages. The AD662J,
A, and S grades provide 4 LSB integral nonlinearity (INL),
while the K, B, and, T grades provide 2 LSB INL, over
temperature.
power consumption of the device, 55 mW, makes it
ideal for applications that are power constrained such as
portable or battery-operated equipment.
DACPORT is a trademark of Analog Devices, Inc.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice .
. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-95
•
SPECIFICATIONS
(@ TA
= Tm;. to Tmax , DVDD = AVDD = 5 V, unless otherwise specified)1
AD662JIAIS
Parameter.
Min
Typ
TEMPERATURE COEFFICIENT
Gain Error
Zero Error
DIGITAL INPUTS
Logic Levels
V Ill
V'L
IIll
I'L
Data Setup Time t DS
Data Hold Time tDH
Write Pulse Width tpw
ANALOG OUTPUT
Range
Output Current
Output Impedance
Source
Sink
Sink from VOUT <50 mV2
Short Circuit Current
toGND
tOV DD
Min
Typ
12
RESOLUTION
TRANSFER CHARACTERSTICS
Accuracy
Integral N oniinearity
Differential Nonlinearity
Monotonicity
Gain Error2
Zero Error2
AD662K1B1f
Max
-4
-1
±1I2
+4
+1
-2
-1
±1/2
Max
Units
12
Bits
+2
+1
LSB
LSB
GUARANTEED OVER RATED SPECIFICATION RANGE
-0.25
-3.2
-60
-10
±2
±30
+2.0
0
-1
+0.25
+3.2
-0.25
-3.2
+0.25
+3.2
% ofFS
mV
+60
+10
-30
-10
+30
+10
ppm of FSrC
fJ-VrC
DVDD
DVDD
+0.8
+1
+1
+0.8
V
V
~
~
ns
ns
ns
±2
±15
V
rnA
-50
0.1
0.2
0
0
0
+50
rnA
-50
rnA
SETTLING TIME
To 0.01%
«112 LSB, RL = I kO, C L = 470 pF)
Full Scale Change (0 to FS)
FS to Code 40 (25 m V)2
FS to Code 12 (7.5 mV)2
FS to Zero2
LSBChange (Midscale)'
LSB Change (Not Midscale)'
3.0
3.0
5.5
8.6
2.0
1.0
3.0
3.0
5.5
8.6
2.0
.1.0
fJ-S
fJ-S
fJ-s
fJ-S
fJ-S
fJ-S
REFIN INPUT IMPEDANCE
50
50
kO
POWER SUPPLY SENSITIVITY
PSRR2
POWER SUPPLY REQUIREMENTS
Operating Voltage Range
Supply Current
Power Consumption
TEMPERATURE RANGE
Specified Range (J, K)
Specified Range (A, B)
Specified Range (S, T)
Storage
-400
100
+400
-400
100
+400
ppmofFSN
4.5
5.0
5.5
13.5
68
4.5
5.0
5.5
13.5
68
V
70
+85
+125
+150
0
-40
-55
-65
70
+85
+125
+150
·C
·C
·C
·C
11
55
0
-40
-55
-65
11
55
rnA
mW
NOTES
I Specified for AVDO tied to DV ~O'
2This parameter is specified for + 25"C operation only.
Specifications subject to change without notice.
Specifications shown in boldface are tested 3t+ 250C on all production units at final electrial test. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
This information applies to a product under-development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-96 DIGITAL-TO-ANALOG CONVERTERS
AD662
ABSOLUTE MAXIMUM RATINGS·
AVDD and DV DD to AGND and DGND ..... -0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . -0.3 V to DVDD +O.3 V
REFIN to AGND . . . . . . . . . . . . . . -0.3 V to AVDD +0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD
REFOUT to AGND . . . . . . . . . . . . . . . . . -0.3 V to AVDD
AVDD to DVDD • • • • • • • • • • • • • • • • • • • • • • • • • • • • ±IV
AGND to DGND . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Storage Temperature Range
N Package (Plastic) . . . . . . . . . . . . . . . . -25°C to + 100°C
Q Package (Cerdip) . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . + 3000C
·Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indio
cated in the operational sections of this specification is not implied. Expo·
sure 10 absolute maximum rating conditions for extended periods may affect
device reliability.
Binary
0000
0000
0000
0000
0000
0000
0001
0001
0010
0011
0100
0111
1000
1100
1111
0000
0000
0000
0000
0001
1111
0000
1111
0000
1111
0000
1111
0000
0000
1111
Hexadecimal
Decimal
Output (V)
000
001
002
ooF
010
OFF
100
IFF
200
3FF
400
7FF
800
COO
FFF
0
1
2
15
16
255
256
511
512
1023
1024
2047
2048
3072
4095
0
0.000625
0.001250
0.009375
0.010000
0.159375
0.160000
0.319375
0.320000
0.639375
0.640000
1.279375
1.280000
1.920000
2.559375
0000
0001
0010
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
0000
1111
~
L
./
~
3m.
-
20
,."
•
L
L
..2
,/
o
2m~
V
./
mA/
A
10
15
H
a
H
•
~
INPUT VOLTAGE TO OUTPUT AMPlIFIER - mV
u
~
Figure 3. External Reference Configuration
Figure 5. Output Voltage for Sink Current of 0 to 5 mA
TIMING AND CONTROL
The AD662 has a 12-bit latch that simplifies interface to a 12-bit
(or wider) data bus. The latch is controlled by the Chip Enable
(CE) input. If the application does not involve a data bus, wiring CE low allows direct operation of the DAC.
The settling time from 0 to full scale is 3 fl.S. However, the settling time of the DAC from full scale towards 0 will increase for
final values
ximately 25 mV (Code 40). For a system
tling for all the code transitions, it is recthe codes below 40 and to refer the outd at 25 mV above AGND. Figure 6 illuse for the AD662 from 0 to full scale and
ck to O. Figures I and 7 are enlargements
times circled in Figure 6.
The data latch is level triggered and acquires data f
bus during the time period when CE is 10
high, the data is latched into
returns low. The minimum .
present on the bus before CE
setup time (tDS ) as seen in Figure 4.
the amount of time that the data has to
CE goes high. The AD662 is specified Co DS - 25
= 0 ns for minimum CE pulse width (tpw) of 35 ns,
direct interface with the fastest microprocessors and co
e_
l:IH IIIIIII !I
•
0
8
Figure 6. Settling Time
.....
.....
' - : CHIP ENABLE PULSE WIDTH = 36 ns MIN
tDH:
DATA HOLD TIME,., 0 ns MIN
tos: DATA SETUP TIME", 25 ns MIN
tunLlNG:
DAC SEnUNG TIME = 3.0 ttl TVP
Figure 4. Timing Diagram
OUTPUT CONSIDERATIONS
The AD662 has an internal output amplifier which provides the
specified low impedance output. The amplifier drives the output
down to the zero offset value from ground when the input code
is OOOH. The output maintains its specified linearity for all the
codes from OOOH to FFFH when the output sources up to 5 mA
of output current. When the output sinks current for input
codes below 048H, however, the output impedance increases up
to 10 n typical. This output impedance determines the lowest
possible output level for a given sink current. The transfer curve
will be nonlinear at this level and stay flat for inputs below it.
This situtuation is illustrated in Figure S. For example, the output stays at about SO mV for input codes between OOOH and
OSOH when the output is sinking 5 mAo
i! .....
~
0.024
\
\
1\
.....
....•
SECOND -
",I
Figure 7. Full Scale to Code 40 Settling Time
When the internal reference is used, it is highly recommended
to filter the internal reference output by adding an external
capacitor of at least 1 fl.F from REFIN (= REFOUT) to
AGND. Otherwise, noise from the reference will dominate the
total output noise and will exceed an LSB level. The total output noise is largest at full scale because the DAC core has the
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-99
•
maximum nInnber of current sources connected to its output.
The measured output white noise is 68 nV/v'HZ. The corner
frequency for IIf noise is approximately 15 kHz. The output
amplifier has its - 3 dB frequency at about I MHz. This data
results in a total output noise of about 79 j.LV rms from 0.1 Hz
at full scale. Figure 8 illustrates the output noise versus frequency with a Ij.LF cap from REFIN and REFOUT to AGND.
The output of the AD662 is protected against short circuits to
ground and the supply. However, short circuits to another 5 V
supply through resistances in the 30 n to 120 n range may
cause device damage and should be avoided.
100·mmnmn
POWER SUPPLY AND DECOUPLING
The AD662 has two power supply pins, digital VDD at Pin 20
and analog VDD at Pin 15. Specified device performance is
achieved for a supply voltage between 4.5 V and 5.5 V at both
pins. The AD662 is designed to operate from a single power
supply, although it has two supply pins. Figure 2 shows this
configuration. The two supply pins should be tied at one point
to the single system supply and should be decoupled to one system ground point. Figure 10 is the measured PSRR of the output at full scale when the analog and digital VDDS are tied
together.
When it is impractical or uneconomical to provide a quiet single
system supply, the user can use two system supplies as shown in
Figure 9. The analog VDD at Pin IS should be the "high quality" supply in this case. Decoupling capacitors should be used
on both supply pins. They should be located as near as possible
to the device. The digital VDD should be bypassed to the digital
ground pin and likewise for analog VDD and ground.
'~OOL...J--,...u.,Lk...J.....J.....I.l.
L..JL....l...u.L..J'-:
,0k
GROUNDING RULES
The AD662 has two ground connections,
(DGND) at Pin 10 and analog ground (AG
at Pin 12.
AGND pin is the "high quality" ground reference point ~
device. Any external loads or external reference should be
referred to this ground. In order to minimize a voltage drop
across Pin 12 and the reference point, care should be taken to
provide a system reference point as close to Pin 12 as possible.
Note that the AD662 typically has 10 mA analog ground current
and a 0.1 n series resistance between AGND, Pin 12, and the
system reference point would result in an additional offset of
1 mV (equivalent to 1.6 LSBs). The digital ground returns current from the digital portion of the device and should be tied to
the analog ground at one point, usually the device power
ground. This should be as close to the device as possible in
order to avoid a differential voltage across these two ground
pins. Differential voltage across two ground pins will degrade
the accuracy of the device. Figures 2 and 9 illustrate connections
for proper operation of the device.
1k
10k
100k
1M
10M
FREQUENCY - Hz
Figure 10. PSRR
VS.
Frequency
BIPOLAR OPERATION
The AD662 was designed for operation from a single +5 V supply and is capable of providing a unipolar output range. When a
negative supply is available in a system, bipolar output ranges
can be achieved by properly offsetting and scaling the output.
Figure 11 shows an example of this application and Figure 12 is
a photo of its settling time characteristics. The precision voltage
reference, AD589, provides the offset and determines the bipolar zero level. The BiFET amplifier, AD711, provides the buff+5V
~--------------------~
DIGITAL ANALOG
SUPPlY
SUPPLY
+6V
+5V
0.1 pF
IIII'OLAR
OUT
SYSTEM GND
Figure 9. Output Configuration Using Two Supplies
-5V
Figure ". Bipolar Buffered Output ±1.2B V
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-100 DIG/TAL-TO-ANALOG CONVERTERS
AD662
ered output. In the case of the circuit shown in Figure 11, the
bipolar signal range is ± 1.28 V. If we adjust the bipolar zero
with the 10 kO potentiometer to be 0 V, the input code, FFFH,
will produce a nominal -1.2794 V and OOOH will give + 1.28 V.
ADSP-2101 or ADSP-2102 - AD662INTERFACE
Figure 14 demonstrates the AD662 interfaced to an ADSP210IlADSP-2102. With a clock frequency of 12.5 MHz, and
instruction execution in one 80 ns cycle, the digital signal processor suppons the AD662 interface with one software wait
state.
2.00 V
AO-A13
711 OUT
OV
662 OUT
OMS
Wii 1 - - - - - - - - '
20V
DBll-D80
ADSP-2100
OR
0.1 V
AD662
ADSP-2101
D12--023
DB11-DBO
DATA BUS
Figure 12. Settling Time Characteristics
Figure 1l1;;~'lnterfacetoADSP-2101IADSP-2102
.,
.~" ~~~
Applications
SP-2102 starts the data memory write operation
memory mapped address on its
assening DMS. The decoded address generer. This allows the converter's 12-bit
o be loaded with the value on the data bus. The
e ~R.eration to the AD662 is extended by a software wait
'A~e ~ompleted within two processor cycles (160 ns).
~onverter's
NUCROPROCESSORINTERFACE
The high speed digital interface of t1u;,
with a wide variety of microp
"The 12-bit single buffered inpu
load data from processors such
series, 80386, and microcontrollers suc
illustrative examples follow.
"C'
;f;:,
ADSP-2100 - AD662 INTERFACE
Figure 13 demonstrates the AD662 interfaced to an AD
2100A. With a clock frequency of 12.5 MHz, and instruction
execution in one 80 ns cycle, the digitial signal processor suppons the AD662 interface with one hardware wait state.
ADSP-2100A stans a data memory write operation by providing
the convener's memory mapped address on the DMA bus. The
decoded address generates CE for the convener. CE, together
with some glue logic and latches, is used to force the ADSP2100A into a one cycle wait state by generating DMACK. The
write operation to the AD662 is thus staned and completed
within two processor cycles (160 ns). At clock speeds of 6 MHz,
no wait states are necessary.
~..""
i\tS920C25 - AD662 INTERFACE
Figure 15 illustrates the AD662 interface to a TMS32OC25 digital signal processor using the I/O pon capability. The IS signal
distinguishes the 110 address space from the local program/data
memory space is used to enable 74F138 decoder. The decoded
pon address is then gated with the RiW and STRB to provide
the AD662 CEo As shown, this interface will support a 40 MHz
processor without wait states.
+.v
l
TMS320C25
74F32
Y7
is --<
G2A
V6p
--<
G2.
v.
A3
A2
Al
-.
-c
AD - A
DMAO-13
RiVii
STRi
OMWII
74F138
Gl
V4
~
V3
V2
~
=L>-
CE
~
AD662*
Vl0
VO 0
]
f-----1f-'
READY
AD662
ADSP-2100A
16.5V
-16,SV<--VEE--+ -H.4V
4.5V<--VLL--+5.5V
:t2
:t2
:t2
2.0
0
rnA
-60
dB
dB
10
fLS
500
fLS
nV-sec
10
MULTIPLYING MODE PERFORMANCE
Reference Feedthrough@ 1kHz
Reference - 3dB Bandwidth
DIGITALINPUTS
VIH
VIL
Data Inputs
IIH@VIN=VLL
IIL@VIN=DGND
CS/DSOIDSIIRSTIRDILS
IIH@VIN=VLL
IIL@VIN=DGND
LSB
LSB
LSB
LSB
LSB
LSB
dB
kHz
±S
±S
±S
ppmflo
ppm/%
ppm/%
0.8
Volts
Volts
vA
-10
-10
:tl
:tl
10
10
fLA
-10
-10
±I
:tl
10
10
fLA
2-104 DIGITAL-TO-ANALOG CONVERTERS
vA
AD664
Model
Min
MSITR"
IIH@V1N=VLL
IIL@VIN=DGND
AD664BDIBE/TDITE
Typ
Max
Units
-10
-150
5
-85
10
0
JLA
-10
-10
70
120
10
/LA
/LA
0.4
Volts
Volts
/LA
QSO/QSI/QS2 11
IIH@V1N=VLL
IIL@V1N=DGND
DIGITAL OUTPUTS
VoL@1.6mASink
VOH@O.5mA Source
DIGITAL TIMING (V1N = 0.8, 2.4V)12
Data Input Mode (Figure 10)
CS Pulse Width lew
Data Setup tos
Data Hold tDH
Address Setup tAS
Address Hold tAH
LS Setup tLS
LSHoldlLH
Data Input Mode (Figure 9)
Data Setup tos
Data Hold tDH
LSWidthtLw
LSSelUptLs
CS Hold tcH
Address Setup tAS
Address Hold tAH
Mode Select (Figure 16)
LS Setup tLS
Address Setup tAS
Data Setup los
LSWidthtLw
CS Hold tCH
OataHoldtoH
MSHoldtMH
Mode Select (Figure 17)
MSSetuptMS
MSHoldtMH
LS Setup tLS
Data Setup tos
CSWidthtw
LSHoldtLH
Data Hold tOH
Readback Mode (Figures 20, 21)
Address Setup tAS
Address Hold tAH
ROSetuptRs
RO Hold tRH
MSSetuptMS
MSHoldtMH
Data Access tov
2.4
80
0
0
30
0
30
ns
ns
ns
ns
ns
ns
ns
0
0
80
0
SO
0
30
ns
ns
ns
ns
ns
ns
ns
20
0
0
80
260
0
0
ns
ns
ns
ns
ns
ns
ns
20
0
0
0
80
85
100
ns
ns
ns
ns
ns
ns
ns
20
30
20
30
20
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
90
ns
100
240
75
Data Release (OF
Address Hold tAH
Asynchronous Reset (Figure 23)
Reset Width tw
±I
TEMPERATURE RANGE
KN/KP
0
BOIBE
TOITE
-40
-55
+70
+85
+125
·C
·C
·C
NOTES
I A minimum power supply of ± 12.0V is required for 0 to + lOY and ± IOV operation.
A minimum power supply of ± 11.4V is required for - 5V to + SV operation.
2Bipoiar zero error is the difference from the ideal output (0 volts) and the actual output voltage witb code 100 000 000 000 applied to the inputs.
3Linearity error is defmed as the maximum deviation of the actual DAC output from the ideal output (a straight line drawn from 0 to F.S. - ILSB)
4FSR means Ful1~Sca1e Range and is 20V for ± lOY range and lOY for ± SV range.
SA minimum power supply of ± 12.0V is required for a IOV reference voltage.
6Analog GroWld Current is input code dependent.
7Gain error matching is the largest difference in gain error between any two DACs in one package.
BOffset error matching is the largest difference in offset error between any two DACs in one package.
9Bipolar zero error matching is the largest difference in bipolar zero error between any two DACs in one package.
IOLinearity error matching is the difference in the worst case linearity error betweeen any two DACs in one package.
"44-pin versions only.
_
'2Timing specifications are relative to CS.
*For Vcc<13V and V EE < - BV. Voltage not to exceed llV maximum.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at fmal electrical test. Results from those tests arc used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
DIGITAL-TO-ANALOG CONVERTERS 2-105
ABSOLUTE MAXIMUM RATINGS·
Vex; to VEE . . . . . . . . . .
Digital Inputs .
Analog Outputs . . . . . . . .
(Specifications apply to all grades except where noted)
. . . . . 0 to +36V
.. -O.3V to +7V
Indeftnite Shorts to
Vex;, V LL, VEE and GND
. 0 to +7V
.0 to +18V
*Stresses above those listed under "Absolute Maximum Ratings" may
-18V to OV
cause permanent damage to the device. This is a stress rating only aod
+ 300°C, lOsee
functional operation of the device at these or aoy other conditions above
. . . . lOOOmW
those indicated in the operational section of this specification is not
. -IV to +lV
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
-IlV to + llV
CAUTION ___________________________________________________
VLL to DGND
Vex; to DGND
VEEtoDGND
Soldering . . .
Power Dissipation .
AGND to DGND .
Reference Input
ESD (electrostatic discharge) sensitive device. Unused devices must be stored in conductive foam or
shunts. The protective foam should be discharged to the destination socket before devices are removed.
WARNING!
~~DEVICE
AD664 ORDERING GUIDE 1
Model
Output
Range
Temperature
Range
Gain
Error
Linearity
Error
Package
Options2
AD664BD-UNI
AD664BD-BIP
AD664TD-UNI/883B3
AD664TD-BIP/883B 3
AD664BE
AD664TEl883B 3
OtoVREF
-VREFtoVREF
OtoVREF
- VREFto VREF
Programmable
Programmable
Ind
Ind
Mil
±5LSB
±5LSB
±5LSB
±5LSB
±5LSB
±5LSB
±O.5LSB
±O.5LSB
±O.5LSB
±O.5LSB
±O.5LSB
±O.5LSB
D-28
D-28
D-28
D-28
E-44A
E-44A
Mil
Ind
Mil
NOTES
1AD664KN aod AD664KP commercial devices to be available soon.
2See Section 14 for package outline information.
'Consult Military Products Databook for complete specifications.
2-106 DIGITAL-TO-ANALOG CONVERTERS
0
AD664
Vee
Va;
+12VI+15V -12V1-1SV
ANALOG
GROUND
DB'
Figure 1a. 44-Pin Block Diagram
FUNCTIONAL DESCRIPTION
The AD664 combines four complete 12-bit voltage output D/A
converters with a fast, flexible digital input/output port on one
monolithic chip. It is available in two forms, a 44-pin version
shown in Figure la and a 28-pin version shown in Figure lb.
44-Pin Versions
Each DAC offers flexibility, accuracy and good dynamic performance. The R-2R structure is fabricated from thin-film resistors
which are laser-trimmed to achieve 112LSB linearity and guaranteed monotonicity. The output amplifier combines the best
features of the bipolar and MOS devices to achieve good dynamic
performance and low offset. Settling time is under lOJ.l.s and
each output can drive a SmA, SOOpF load. Short-circuit protection
allows indefinite shorts to VLL , Vee, VEE and GND. The output
and span resistor pins are available separately. This feature
allows a user to insert current-boosting elements to increase the
drive capability of the system, as well as to overcome parasitics.
Digital circuitry is implemented in CMOS logic. The fast, low
power, digital interface allows the AD664 to be interfaced with
most microprocessors. Through this interface, the wide variety
of features on each chip may be accessed. For example, the
input data for each DAC is programmed by way of 4-, 8-, 12or l6-bit words. The double-buffered input structure of this
latch allows all four DACs to be updated simultaneously. A
readback feature allows the internal registers to be read back
through the same digital port, as either 4-, 8- or 12-bit words.
When disabled, the readback drivers are placed in a high impedance
(tristate) mode. A TRANSPARENT mode allows the input data
to pass straight through both ranks of input registers and appear
at the DAC with a minimum of delay. One D/A may be placed
in the transparent mode at a time, or all four may be made
transparent at once. The MODE SELECT feature allows the
output range and mode of the DACs to be selected via the data
bus inputs. An internal mode select register stores the selections.
This register may also be read back to check its contents. A
RESET-TO-ZERO feature allows all DACs to be reset to 0
volts out by strobing a single pin.
Vee
ANALOG
Va;
+12\11+15V -1ZV/-1SV
GROUND
DB11
0810
DB9
Vou,A
DB7
V~B
DB&
DB5
DB'
DB3
DB'
DB'
DS1 050
+5V
DIGITAL
VLL
GROUND
Figure 1b. 28-Pin Block Diagram
28-Pin Versions
The 28-pin versions are dedicated versions of the 44-pin AD664.
Each offers a reduced set of features from those offered in the
44-pin version. This accommodates the reduced number of package
pins available. Data is written and read with 12-bit words only.
Output range and mode select functions are also not available in
28-pin versions. As an alternative, users specify either the UNI
(unipolar, 0 to VREF) models or the BIP (bipolar, - VREF to
VREF) models depending on the application requirements. Finally,
the transparent mode is not available on the 28-pin versions.
DIGITAL-TO-ANALOG CONVERTERS 2-107
Mode = RIP
Mode=UNI
Gain = I
000000000000 = OV
100000000000 = VREF/2
111111111111 = VREF -ILSB
000000000000 = - VREF/2
100000000000 = OV
111111111111 = VREP/2 -ILSB
Gain = 2
000000000000 = OV
100000000000 = VREF
111111111111 = 2XVREF -ILSB
000000000000 = - VREF
100000000000 = OV
111111111111 = +VREF-ILSB
Table I. Transfer Functions
DEFINITIONS OF SPECIFICATIONS
LINEARITY ERROR: Analog Devices defines linearity error
as the maximum deviation of the actual, adjusted DAC output
from the ideal analog output (a straight line drawn from 0 to
FS - ILSB) for any bit conbination. This is also referred to as
relative accuracy. The AD664 is laser-trimmed to typically maintain linearity errors at less than ± 1I4LSB.
MONOTONICITY: A DAC is said to be monotonic if the
output either increases or remains constant for increasing digital
inputs such that the output will always be a nondecreasing
function of input. All versions of the AD664 are monotonic over
their full operating temperature range.
DIFFERENTIAL LINEARITY: Monotonic behavior requires
that the differential linearity error be less than I LSB both at
25°C as well as over the temperature range of interest. Differential
nonlinearity is the measure of the variation in analog value,
normalized to full scale, associated with a ILSB change in digital
input code. For example, for a 10V full-scale output, a change
of ILSB in digital input code should result in a 2.44mV change
in the analog output CVREF= 10V, Gain = I, ILSB= 10Vx 11
4096=2.44mV). If in actual use, however, a ILSB change in
the input code results in a change of only 0.61mV (1I4LSB) in
analog output, the differential nonlinearity error would be
-1.83mV,or -3/4LSB.
GAIN ERROR: DAC gain error is a measure of the difference
between the output span of an ideal DAC and an actual device.
of a DAC when the input is loaded with all "Os" and the MODE
is unipolar.
BIPOLAR ZERO ERROR: Bipolar zero error is the difference
between the ideal output (OV) and the actual output of a DAC
when the input code is loaded with the MSB = "I" and the
rest of the bits = "0" and the MODE is bipolar.
SETTLING TIME: Settling time is the time required for the
output to reach and remain within a specified error band about
its final value, measured from the digital input transition.
CROSSTALK: Crosstalk is the change in an output caused by
a change in one or more of the other outputs. It is due to capacitive
and thermal coupling between outputs.
REFERENCE FEEDTHROUGH: The portion of an ac reference
signal that appears at an output when all input bits are low.
Feedthrough is due to capacitive coupling between the reference
input and the output. It is specified in decibels at a particular
frequency.
REFERENCE 3dB BANDWIDTH: The frequency of the ac
reference input signal at which the amplitude of the full-scale
output response falls 3dB from the ideal response.
GLITCH IMPULSE: Glitch impulse is an undesired output
voltage transient caused by asymmetrical switching times in the
switches of a DAC. These transients are specified by their net
area (in nY-sec) of the voltage vs. time characteristic.
UNIPOLAR OFFSET ERROR: Unipolar offset error is the
difference between the ideal output (OV) and the actual output
PIN CONFIGURATIONS
44-Pin Package
28-Pin DIP Package
•
~I
~I
yo•
Vo.
1
V.. (-12V/-.5VI
~ Z~
Z
Z
Q
z
~
8
Z
Q
u
0
~
+
~Z
Z
8
~ 0
l!l 151 ~ z >
Z
3
Vcc l+12V/+15V)
AGND
IS
ADe64
iiii
TOP VIEW
(Not to Scale)
AD664
TOP VIEW
INo.toScaIeI
DB10
DB9
DB3
DBa
NO CONNECT 16
D84
DB7
NO CONNECT 17
DB5
DB6
2-108 DIGITAL-TO-ANALOG CONVERTERS
DB.
AD664
ANALOG CIRCUIT CONSIDERATIONS
Grounding Recommendations
The AD664 has two pins, designated ANALOG and DIGITAL
ground. The analog ground pin is the "high quality" ground
reference point for the device. A unique internal design has
resulted in low analog ground current. This greatly simplifies
management of ground current and the associated induced voltage
drops. The analog ground pin should be connected to the analog
ground point in the system. The external reference and any
external loads should also be returned to analog ground.
greater than both the external reference and the inverted external
reference.
Output Considerations
Each DAC output can source or sink SmA of current to an
external load. Short-circuit protection limits load current to a
maximum load current of 4OmA. Load capacitance of up to
SOOpF can be accomodated with no effect on stability. Should
an application require additional output current, a current boosting
element can be inserted into the output loop with no sacrifice in
accuracy. Figure 3 details this method.
The digital ground pin sh01,Ild be connected to the digital ground
point in the circuit. This pin returns current from the logic
portions of the AD664 circuitry to ground.
Analog and digital grounds should be connected at one point in
the system. If there is a possibility that this connection be broken
or otherwise disconnected, then two diodes should be connected
between the analog and digital ground pins of the AD664 to
limit the maximum ground voltage difference.
Power Supplies and Decoupling
The AD664 requires three power supplies for proper operation.
VLL powers the logic portions of the device and requires
+ S volts. Va::. and VEE power the remaining portions of the
circuitry and require + 12V to + ISV and -12V to -ISV,
respectively. Va::. and VEE must also be a minimum of two volts
greater then the maximum reference and output voltages
anticipated.
Decoupling capacitors should be used on all power supply pins.
Good engineering practice dictates that the bypass capacitors be
located as near as possible to the package pins. VLL should be
bypassed to digital ground. Va::. and VEE should be decoupled
to analog ground.
Driving the Reference Input
The reference input of the AD664 can have an impedance as
low as 1.3kO. Therefore, the external reference voltage must be
able to source up to 7.7mA of load current. Suitable choices
include the SV ADS86, the IOV ADS87 and the 8.192V AD689.
The architecture of the AD664 derives an inverted version of
the reference voltage for some portions of the internal circuitry.
This means that the power supplies must be at least 2V
V+
SYSTEM SUPPLIES
-1SV
+t5V
+5V
==:;:5:~=
.-----__........1
EXTERNAL
LOAD
Figure 3. Current-Boosting Scheme
AD664 output voltage settling time is lOlLS maximum. Figure 4
shows the output voltage settling time with a fixed IOV reference,
gain = I and all bits switched from I to o.
LARGE
SCALE
ILSB
ANE
SCALE
OV
-ILSB
INPUT
BITS
liS "
Figure 4. Settling Time; All Bits Switched from On to Off
Alternately, Figure S shows the settling characteristics when the
reference is switched and the input bits remain fixed. In this
case, all bits are "on", the gain is I and the reference is switched
froin - SV to + 5V.
LARGE
SCALE
FINE
SCALE
+5Y
REF
INPUT
RETURN
R~N-----..J
RET~:N
--------1
Figure 2. Recommended Circuit Schematic
Figure 5. Settling Time; Input Bits Fixed, Reference
Switched
DIGITAL-TO-ANALOG CONVERTERS 2-109
•
Multiplying Mode Performance
Figure 6 illustrates the typical open-loop gain and phase performance of the output amplifiers of the AD664.
+20
\
GAIN"
+1 5
~
\
0
PHASE~ ~ ~~
+5
I"-......
"1\
~
Figure 8. Typical Output Noise
\
10k
100k
1M
FREQUENCY
Figure 6. Gain and Phase Performance of AD664 Outputs
Crosstalk
Crosstalk is a spurious signal on one DAC output caused by a
change in the output of one or more of the other DACs. Crosstalk
can be induced by capacitive, thermal or load current induced
feedthrough. Figure 7 shows typical crosstalk. DAC B is set to
output 0 volts. The outputs of DAC A, C and D switch 2kO
loads from IOV to OV. The first disturbance in the output of
DAC B is caused by digital feedthrough from the input data
lows. The second disturbance is caused by analog feedthrough
from the other DAC outputs.
Partial address decoding is perfortned by the DSO, DSI, QSO,
QSI and QS2 address bits.
The RST pin provides a simple method to reset all output
voltages to zero. Its advantages are speed and low software
overhead.
INPUT DATA
In general, two types of data will be input to the registers of the
AD664, input code data and mode select data. Input code data
sets the DAC inputs while the mode select data sets the gain
and range of each DAC.
The versatile 110 port of the AD664 allows many different types
of data input schemes. For example, the input code for just one
of the DACs may be loaded and the output mayor may not be
updated. Or, the input codes for all four DACs may be written,
and the outputs mayor may not be updated.
DACA.C.D
OUT
1LSB
DACB
OUT
As Table II shows, the AD664 makes a wide variety of operating
modes available to the user. These modes are accessed or programmed through the high-speed digital port of the quad DAC.
On-board registers program and store the DAC input codes and
the DAC operating mode data. All registers are double-buffered
to allow for simultaneous updating of all outputs. Register data
may be read back to verify the respective contents. The digital
port also allows transparent operation. Data from the input pins
can be sent directly through both ranks of latches to the DAC.
ov
I
I
I
-l-j-~1
-1LSB
-,-----
The same applies for MODE SELECTION. The mode of just
one or many of the DACs may be rewritten and the user can
choose to immediately update the outputs or wait until a later
time to transfer the mode information to the outputs.
A user may also write both input code and mode information
into their respective first ranks and then update all second ranks
at once.
DIGITAL
CROSSTALK
ANALOG
CROSSTALK
Figure 7. Output Crosstalk
Output NoiSe
Wideband output noise is shown in Figure 8. This measurement
was made with a 7MHz noise bandwidth, gain = I and all
bits on. The total rms noise is approximately one fifth the visual
peak-to-peak noise.
.
Finally, transparent operation allows data to be transferred from
the inputs to the outputs. This feature is useful, for example, in
a situation where one of the DACs is used in an AID converter.
The SAR register could be connected directly to a DAC by
using the transparent mode of operation. Another use for this
feature would be during. system calibration where the endpoints
of the transfer functi\>n of each DAC would be measured. For
example, if the full-scale voltages of each DAC were to be measured, then by making all four DACs transparent and putting all
"Is" on the input port, all four DACs would be at full-scale.
This requires far less software overhead than loading each register
individually.
The following sections detail the timing requirements for various
data loading schemes.
2-110 DIGITAL-TO-ANALOG CONVERTERS
AD664
Function
DSl,DSO
Load 1st Rank (data)
DACA
DACB
DACC
DACD
00
01
10
-LS
-MS -TR
0
0
0
1
1
1
1
0
11
QSO,
1, 21
1
1
1
1
Select Quad
Select Quad
Select Quad
Select Quad
-RST
-RD -CS
1
1
1
1
1--+0
1--+0
1--+0
1--+0
1
1
1
1
1
Load 2nd Rank (data)
XX
1
1
1
XXX
1
1--+0
Readback 2nd Rank (data)
SelectD/A
1
1
Select Quad
0
1--+0
1
Reset
XX
X
X
X
X
XXX
X
X
0
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
000
000
000
000
000
1
1
1
1
1
1--+0
1--+0
1--+0
1--+0
1--+0
1
1
1
1
1
0
1
0
0
1
1
1
1
1--+0
1--+0
1
1
X
0
1
OOX
XXX
OOX
0
1--+0
1
Transparent I
AlIDACs
DACA
DACB
DACC
DACD
Mode Select 1,2
1st Rank
2nd Rank
Readback Model
Notes: X
XX
00
01
10
11
XX
XX
XX
= don't care.
'For~in versions only_
'ForMS, TR,LS = O,aMS 1st write occurs.
Table II. AD664 Digital Truth Table
Load and Update One DAC Output
In this first example, the object is simply to change the output
of one of the four DACs on the AD664 chip. The procedure is
to select the address bits that indicate the DAC to be programmed,
pull LATCH SELECT(LS) low, pull CHIP SELECT(CS) low,
release LS and then release CS. When CS goes low, data enters
the first rank of the input latch. As soon as LS goes high, the
data is transferred into the second rank and produces the new
output voltage. During this transfer, MS, TR, RD and RST
should be held high.
DATA
INPUT/OUTPUT
BITS
Preloacling the First Rank of One DAC
In this case, the object is to load new data into the first rank of
one of the DACs but not the output. As in the previous case,
the address and data inputs are placed on the appropriate pins.
LS is then brought to "0" and then CS is asserted. Note that in
this situation, however, CS goes high before LS goes high. The
input data is prevented from getting to the second rank and
affecting the output voltage.
INPU~!~TPUT
..IX
___
---v
ADIlMSJL
050.051.052 - - - "
050.0:
~
X'-___
DATA VALID
tos
t-I
--I I-- t ...
~t'.1
v--L
-
1
I
ADDRESS VALID
t~ ~
" ~~1 1~{
~
Figure 9. Update Output of a Single DAC
Figure 10. Preload First Rank of a DAC
This allows the user to "preload" the data to a DAC and strobe
it into the output latch at some future time. The user could do
this by reproducing the sequence of signals illustrated in the
next section.
DIGITAL-TO-ANALOG CONVERTERS 2-111
Update Second Rank of a DAC
Assuming that a new input code had previously been placed
into the first rank of the input latches, the user can update the
output of the DAC by simply pulling CS low while keeping LS,
MS, TR, RD and RST high. Address data is not needed in this
case. In reality, all second ranks are being updated by this procedure, but only those which receive data different from that
already there would manifest a change. Updating the second
rank does not change the contents of the first rank.
INPU~~~TPUT
a/offc,:'~%
Q~:f!~ :W///
//Moff1rf7i
tew = 85n5 MIN
:-0Figure 11. Update Second Rank of a DAC
The same options that exist for individual DAC input loading
also exist for multiple DAC input loading. That is, the user can
choose to update the first and second ranks of the registers or
preload the fJrst rsnks and then update them at a future time.
Load and Update Multiple DAC Outputs
The following examples demonstrste two ways to update all
DAC outputs. The first method involves doing all data transfers
during one long CS low period. Note that in this case, shown in
Figure 12, LS returns high before CS goes high. Data hold
time, relative to an address change, is 70ns. This updates the
outputs of all DACs simultaneously.
DATA
INPUT/OUTPUT
BITS
·r--',.--....,--.. . .,..--
-APORESL - , , . - - ..
QSO.QS1.QS2
DSO.DSl
cs
BITS
...APDR~
aso. OS1, QS2
DSO,DS1
ALTF,Bt.IATE
LS
: / / //
/ /
o
LS
DATA
INPUTIOUTPUT
~
\
I
I
Figure 12. Update All DAC Outputs
The second method involves doing a CS assertion (low) and an
LS toggle separstely for each DAC. It is basically a series of
preload operstions (Figure 10). In this case, illustrated iit
Figure 13, two LS signals are shown. One, labelled LS, goes
high before CS returns high. This transfers the "new" input
word to the DAC outputs sequentially. The second LS signal,
labelled Alternate LS, stays low until CS returns high. Using
this sequence loads the fJrst rsnks with each "new" input word
but doesn't update the DACoutputs. To then update all DAC
outputs simultaneously would require the signals illustrated in
Figure II.
Figure 13. Load and Update Multiple DACs
Preload Multiple First Rank Registers
The first ranks of the DAC input registers may be preloaded
with new input data without disturbing the second rank data.
This is done by transferring the data into the fJrst rank by bringing
CS low while LS is low. But CS must return high before LS.
This prevents the data from the first rank from getting into the
second rank, A simple Second rank update cycle as shown in
Figure II would move the "pre1oaded" information to the
DACs.
DATA
INPUTfOUTPUT
BITS
~~,~
_ _- I \ _ _ _-',~ _ _-J.~_ _-',~
...APJl!!IiIiL050, OS1, QS2 ~
ADDRESS
THREE
D80.OS1
X
ADDRESS
______________~r
\
r
\~
Figure 14. Preload First Rank Registers
Selecting Gain Range and Modes (44-Pin Versions)
The AD664's mode select feature allows a user to configure the
gain ranges and output modes of each of the four DACs. On-board
switches take the place of up to eight external relays that would
normally be required to accomplish this task. The switches are
programmed by the mode select word entered via the data I/O
port. The mode select word is eight bits wide and occupies the
topmost eight bits of the input word. The last four bits of the
input word are "don't cares."
Figure 15 shows the format of the MODE SELECT word. The
first four bits determine the gain range of the DAC. When set
to be a gain of I, the output of the-DAC spans a voltage of I
times the reference. When set to a gain of 2, the output of the
DAC spans a voltage of 2 times the reference.
The next four bits detertnine the mode of the DAC. When set
to UNIPOLAR, the output goes from 0 to REF or 0 to 2REF.
When the BIPOLAR mOde is selected, the output goes from
-REF/2 to REF/2 or -REF to REF.
DB4
DB11
GA
GB
GC
GX = "0", GAIN=1
GX="1", GAIN=2
MX="O", UNIPOLAR
MX="1", BIPOLAR
Figure 15. Mode Select Word Format
2-112 DIGITAL-TO-ANALOG CONVERTERS
'(
I.._...;FO.:;.U",R,--_
AD664
Load and Update Mode of One DAC
In this next example, the object is to load new mode information
for one of the DACs into the first rank of latches and then
immediately update the second rank. This is done by putting
the new mode information (8-bit word length) onto the databus.
Then MS and LS are pulled low. Following that, CS is pulled
low. This loads the mode information into the first rank of
latches. LS is then brought high. This action updates the second
rank of latches (and, therefore, the DAC outputs). The load
cycle ends when CS is brought high.
The fully transparent mode is selected by asserting lows on
QSO, QSI, QS2, TR and CS while asserting highs on LS, MS
and RD. Figure 18 illustrates the correct timing relationships
for those signals. Address setup and TR setup times are Ons
minimum.
•
In reality, this load cycle really updates the modes of all the
DACs, but the effect is to only change the modes of those DACs
whose mode select information has actually changed.
INPU~~t'TPUT
BITS
-.I\
'MH
Xr-'::M-=O=D-=E-=SE~L-=EC=Tc..,X
_ _ _ _....I.,.
'DS
~
t--
'MS
DATA WORD
I"
=;j
lI.-
....._ _ _ __
--l f--
'DH
--'\:±'LW-4""';-:',--
I
__
-1--,'LS
~
~
lr_tcH_ _
~
Figure 16. Load and Update Mode of One DAC
Preloading the Mode Select Register
Mode data can be written into the first rank of the mode select
latch without changing the modes currently being used. This
feature is useful when a user wants to preload new mode information in anticipation of strobing that in at a future time. Figure
17 illustrates the correct sequence of control signals to accomplish
this task. (A second rank load requires CS = 320ns.)
DATA
INPUT/OUTPUT
BITS
~
X
r1
- - " MODE SELECT
DATAWORD ....._ __
--A
~
'DS
~I'DH
J r~1'"'
Figure 17. Preload Mode Select Register
Transparent Mode Operation (44-Pin Versions)
Transparent operation allows data from the inputs of the AD664
to be transferred into the DAC registers without the intervening
step of being latched into the first rank of latches. Two modes
of transparent operation exist, the "partially transparent" mode
and a "fully transparent" mode. In the "partially transparent"
mode, one of the DACs is transparent while the remaining three
continue to use the data latched into their respective input registers.
Both modes require a 12-bit wide input word!
Figure 18. Fully Transparent Operation
The partially transparent mode of operation is achieved by
setting QSO, QSI, QS2, LS and TR low while RD and MS are
high. The address of the transparent DAC is asserted on DSO
and DS!. Figure 19 illustrates the correct sequence of those
signals. The required minimum setup times for QSO, QSI,
QS2, DSO, DSI, TR and LS are again Ons.
.....ADDRESL
QSo, OSI, QS2,
DSO,DSI
m,[S
Figure 19, Partially Transparent Operation
OUTPUT DATA
Two types of outputs may be obtained from the internal data
registers of the AD664 chip, mode select apd DAC input code
data, Readback data may be in the same forms in which it can
be entered; 4-, 8-, and 12-bit wide words (12 bits only for 28-pin
versions).
DAC Data Readback
DAC input code readback data is obtained by setting the address
of the DAC (DSO, DSI) and Quads (QSO, QSI, QS2) on the
address pins and bringing the RD and CS pins low. The timing
diagram for a DAC code readback operation appears in
Figure 20.
X
AO~SL~
QSO, 051, 052,
OSO,OSI
_
m
a
I 1~j.J t 1L
DATA
INPUT/OUTPUT
BITS
,L.._ _ __
•
-.1 'A:
'AH_
~~------
HIGH Z
mo~:r~
'"I"~
I
HIGH
I 1-"0"
'DV --I r- :.j I-toF
z-
Figure 20, DAC Input Code Readback
DlGITAL-TO-ANALOG CONVERTERS 2-113
Mode Data Readback
Mode data is read back in a similar fashion. By setting MS,
QSO, QSI, RD and CS low while setting TR and RST high, the
mode select word is presented to the 110 port pins. Figure 21
shows the timing diagram for a readback of the mode select data
register.
At power-up, an AD664 may be activated in either the read or
write modes. While, at the device level, this will not produce
any problems, at the system level it may. Analog Devices
recommends the addition of a simple power-on reset scheme to
any system where the possibility of an unknown start-up state
could be a problem. The simplest version of this scheme is
illustrated in Figure 24.
+5V
AD684
#1
RST
10kO
100nF
Figure 21. Mode Select Readback
Figure 24. Power-On Reset
OUTPUT LOADS
Readback timing is tested with the output loads shown in
Figure 22.
+5V
OUTPUT
PIN
-tI!
3kll
PIN
-= 3kll
HIGHZ_ "0"
--!:
I
OUTPUT - -.....- - - 1 > - - -
100pF
1
1100PF
HIGHZ_"1"
+5V
kll
OUTPUT
PIN
1
OU~UT--~1r.~_ _J[~-
r
10pF
kll
"O"_HIGHZ
J
1
10PF
·1" .... HIGHZ
Figure 22. Output Loads
Asynchronous Reset Operation
The asynchronous reset signal shown in Figure 23 may be asserted
at any time. A minimum pulse width (tRW) of 90ns is required.
The reset feature is designed to return all DAC outputs to
o volts regardless of the mode or range selected. In the 44-pin
versions, the modes are reset to unipolar 10V span (gain of I),
and the input codes are rewritten to be "Os." Previous DAC
code and mode information is erased.
In the 28-pin versions of the AD664, the mode remains unchanged,
the appropriate input code is rewritten to reset the output voltage
to 0 volts. As in the 44-pin versions, the previous input data is
erased.
.
~tRWt
U
Figure 23. Asynchronous Reset OPeration
2-114 DIGITAL-TO-ANALOG CONVERTERS
It is obvious from inspection that the scheme shown in Figure
24 is only appropriate for systems in which the RST pin is
otherwise not used. Should the user wish to use the RST pin,
an additional logic gate may be included to combine the power-on
reset with the reset signal.
Interfacing the AD664 To Microprocessors
The AD664 is easy to interface with a wide variety of popular
microprocessors. Common architectures include processors with
dedicated 8-bit data and address buses, an 8-bit bus over which
data and address are multiplexed, an 8-bit data and 16-bit address
partially muxed, and separate 16-bit data and address buses.
AD664 addressing can be accomplished through either memorymapped or 1/0 techniques. In memory-mapped schemes, the
AD664 appears to the host microprocessor as RAM memory.
Standard memory addressing techniques are used to select the
AD664. In the 110 schemes, the AD664 is treated as an external
1/0 device by the host. Dedicated 110 pins are used to address
the AD664.
MC6801 Interface
In Figures 25a-25d, we illustrate a few of the various methods
that can be used to connect an AD664 to the popular MC6801
microprocessor. In each of these cases, the MC6801 is intended
to be configured in its expanded, nonmultiplexed mode of operation. In this mode, the MC6801 can address 256 bytes of external
memory over 8-bit data (Port 3) and 8-bit address (Port 4) buses.
Eight general-purpose 1/0 lines (Port I) are also available. Onboard RAM and ROM provide program and data storage space.
In Figure 25a, the three least significant address bits (P40, P41
and P42) are employed to select the appropriate on-chip addresses
for the various input registers of the AD664. Three 1/0 lines
(PI7, PI6 and PIS) are used to select various operating features
of the the AD664. lOS and E(nable) are combined to produce
an appropriate CS signal. This addressing scheme leaves the five
most significant address bits and five 110 lines free for other
tasks in the system.
Figure 25b shows another way to interface an AD664 to the
MC6801. Here we've used the six least significant address lines
to select AD664 features and registers. This is a purely memorymapped scheme while the one illustrated in Figure 25a uses
some memory-mapping as well as some dedicated 1/0 pins. In
Figure 25b, two address lines and all eight 1/0 lines remain free
for other system tasks.
AD664
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GND
1~40
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III
II
~Cii&l13;;Glfiill~::
F¥
PI3
17 "4
• .,
T
P37 ~I-D7
P40 29 f- AO
PI.
=!
v
P32~
=} :::
~ P23
DO
P31 36
Vee
~
-
~ RIW~
P30:¥
~
QQQQQQQQQQ!!
DS1
DSO
A0664
aso
aS1
aS2
CS
RD
FREE
(
FOROTHER . _
TASKS
I
[S
J
fii
MS
RST
I
+5V
Figure 25b. Alternate AD664 to MC6801 Interface
DIGITAL-TO-ANALOG CONVERTERS 2-115
GNO
-~ .vas ~ XTALl
*
~
+5V
R=
~:~L2
E~
SC1~
lOS
RIW
:~
'RQ1
P31~
RESET
P32 35
-~ V~
P22
V
D7
AO
:~
P11
P42
-~P12
~
~r-- h
-"'"
P"~!---:
l
-
.... ~r---'
1 P13
P14
....
~ P1.
P46
~ P16
L.!2.
"
P36
[-e,;_
.,..
-I#:
'-w.:
r r - - r T O CS #2
P33~
ffi=~!
_
IV
DO
*:~
:~
~ MC&801 ~
FREE FOR
OTHER
110 TASK
S
"..
1
~TOCS#1
...........,.~
~ r-r---) FOR~\~ER
~
TASKS
P47~
P17
A7-
STAN:'; 21
l
ii!1iillllillliill:S1iiIU!:;!::
CCCCClCCCQC!!
DSI
DSO
AD664 #1
iiSO
L
ii!1iillllillliill:S1ii!!llll:;!::
' - - DSO
L
aSl
' - - - aS2
eB!
CCCCQCQC
DSI
AD664 #2
aso
as;
' - - - QS2
cs
CS#1
AD LS Tii MS RST
cs
+:V
CS#2
II
AD LS 'i'i'i
MS
liST
+Jv
Figure 25c. Interfacing Two AD664s to an MC6801
G ND-~
~
se1
EXTAl2
sa ~-RIW-
~ NMi
~
+5V-~
~
FREE
FOR
OTHER
I/O TAS
!..
XTAL1
P30 37
'RQ1
P31 36
RESET
P22 35
v~
P33 34
P2D
P3. 22
P21
P35 32
10SDO
ffi: P22 Mel101 P38
~
~
ffi: P1'
P4128
P23
P37
P24
P40 29
I-f¥.. P11
P12
P42 27
[-*
1- 15
~
P13
P1.
P15
P1.
P17
f--£>
D7
AO
....'"'1>
"'
P43 "
P44 25
... 2'
P46~_
~
l
P47¥._]
STANci':~
21
'--- DSO
L
UNCOMMITED (
ADg~~S
~_
l
81iiIUlliill:S1ii:S1ll:;!::
CCCQCQCCC!!
DSI
'--- DSO
AD664 #1
aso
as;
' - - - QS2
L
1
LS 'i'i'i MS liST
•••
+:v
'-g~~-+5V
3
A.
~ '. 74138
~~;
0,
CS#3
CS#4
5
E.
01
EI
'-E'"
0..
GND
0.
8
m-.
m--.
CS#2
0, 13
7
GND
14
CS#5
TI-..
o.~CS#6
CS#7
Figure 25d. Interfacing Eight AD664s to an MC6801
2-116 DIGITAL-TO-ANALOG CONVERTERS
iiSO
AD664 #8
as;
' - - - OS2
#1
CS AD
~A'
ii!1iilll'"lIilll:S1iiIU:;!::
QCQ!QQClQQcqg~
DSI
CS
AD LS 'i'i'i MS liST
I
+~v
AD664
Expansion of the scheme employed in Figure 25a results in that
shown in Figure 25c. Here, two AD664s are connected to an
MC6801, providing a total of eight 12-bit, software programmable
DACs. Again, the three least significant bits of address are used
to select the on-chip registers of the AD664. lOS and E, as well
as a fourth address bit, are decoded to provide the appropriate
CS signals. Four address and five 1/0 lines remain uncommitted.
frees up another 1/0 or address bit. The same consideration
applies to mode select. In all of these cases TR is shown tied to
VLClG1C, because the MC6801 cannot provide the 12-bit-wide
input word required for the transparent mode. In situations
where transparent operation isn't required, and mode select is
also not needed, the designer may consider specifying the DIP
version of the device (either the UNI or BIP version).
A slighdy more sophisticated approach to system expansion is
illustrated in Figure 25d. Here, a 74LS138 (l-of-8 decoder) is
used to address one of the eight AD664s connected to the MC6801.
The three least significant address bits are used to select on-chip
register and DAC. The next three address bits are used to select
the appropriate AD664. lOS and E gate the 74LS138 output.
Each of the schemes illustrated in Figure 25 operates with an
MC6801 at clock rates up to and including 1.5MHz. Similar
schemes can be derived for other 8-bit microprocessors and
microcontrollers such as the 805118086/8088/6502, etc. One
such scheme developed for the 8051/AD664 is illustrated in
Figure 26.
The schemes in Figure 25 illustrate some of the trade-offs which
a designer may make when configuring a system. For example,
the designer may use 110 lines instead of address bits or vice
versa. This decision may be influenced by other 110 tasks or
system expansion requirements. He/she can also choose to implement only a subset of the features available. Perhaps the
RST pin isn't really needed. Tying that input pin to V LOGIC
8051 Interface
Figure 26 shows the AD664 combined with an 8051 ,,"controller
chip. Three LSBs of address provide the quad and DAC select
signals. Control signals from Port I select various operating
modes such as readback, mode select and reset as well as providing
the LS signal. Read and write signals from the 8051 are decoded
to provide the CS signal.
+5V
": "! "! ,.:
... ...~
~
A: A: A:
I
u !l
B
CO!
z > If
B
..,
:;j
~ ... ...cl
4
DB4
•••
DB11
DB3
DB6
DS1
P3.1 ,.
AD664
DSO
P3.2
~-+-+-~ OSo, OS1
P3.3
P2.7
P3.4
P2.&
P3.5
P2.5
OS2
Figure 26. AD664 to 8051 Interface
DIGITAL-TO-ANALOG CONVERTERS 2-11'7
IBM .PC* IDterface
Figure 27 illustrates a simple interface between an IBM PC and
an AD664. The three least significant address bits are used to
select the Quad and DAC. The next two address bits are used
for LS and MS. In this scheme, a l2-bit input word requires·
two load cycles, an 8-bit word imd a 4-bit word. Another write
is required to transfer the word or words previously written to
the second rank. A l2-bit-wide word again requires at least two
read cycles; one for the 8MSBs and four for the LSBs. The
page Select signal prodUces a CS strobe for any address from
300H to 31FH.
DO
•••
D7
:i:;&t:aill=ID==~i
QQQQQQQQQQI!lQ
A2
A1
p>--c
AO
+12V
-12V
+5V
Er
A3
A4
.:n-
lOR
lOW
A5
A6
~
-,
~J
~r
AS
A7
A9
~
rr
PAGE
SELECT
OS1
DSO
elSO
QS1
OS2
-
V.EF
CS RD
RESET
DRIVE
""
Figure 27. AD664 to IBM PC Interface
*IBM PC is 8 IradelIWk of IaceraatioJlallluoiaess Machine. Corp.
2-118 DIGITAL-TO-ANALOG CONVERTERS
COMr
D
[S
TIi
MS
iiST AcoM
h
AEN
GND
AD664
Vee
VEE
VLOGIC
r-C>-
AD664
Table III, shown below details the memory locations and addresses
used by this interface.
300
301
302
303
o
o
o
o
o
304
305
306
307
308
311
312
313
314
315
316
o
o
o
o
o
o
o
1
o
1
1
1
o
o
o
0
0
0
0
0
0
0
1
0
Illegal Address
Mode Select, 1st Rank
Illegal Address
Mode Select, 1st Rank
Illegal Address
Mode Select, 1st Rank
Illegal Address
Mode Select, 1st Rank
2nd Rank
Mode
DAC A, 4LSBs, 1st Rank
DAC A, 8MSBs, 1st Rank
DACB,4LSBs, IstRank
DACB,8MSBs, lstRank
DAC C, 4LSBs, 1st Rank
DAC C, 8MSBs, 1st Rank
Note: Shaded registers are readable.
Table III. IBM PC Memory Map
DIGITAL-TO-ANALOG CONVERTERS 2-119
II
The following IBM PC Basic routine produces four output
voltage ramps from one AD664. Line numbers 10 through 70
define the hardware addresses for the first and second ranks of
DAC registers as well as the first and second ranks of the mode
select register. Program variables are initialized in line numbers
110 through 130. Line number 170 writes "Os" out to the first
rank and, then, the second rank of the mode select register.
5
10
20
~!J
40
50
60
70
80
90
100
11 0
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
400
410
420
430
440
450
500
510
520
530
Line numbers 200 through 320 calculate output voltages. Firuilly
line numbers 410 through 450 update the first, then the second
ranks of the DAC input registers. Hardware registers may be
read with the "INP" instruction. For example, the contents of
the DAC A register may be accessed with the following com"
mand: Line# A = INP(DACA).
REM--.-AD664 LISSAJOUS PATIERNS---REM - - -ASSIGN HARDWARE ADDRESSES- -DACA =785
DACB 757
=
DACe = 789
DACD = 791
DAC2ND = 792
MODEl =769 :MODE2 = 776
REM
REM
REM - - -I NITIALIZE VARIA8LES- -X=O: Y1 = 128: Y2 = 64: Y3 = 32
ex = 1: CY 1 = 1: CY2 = -1 : CY3 = 1
FX = 9: FY 1 = 5: FY2 = 13 : FY3 = 15
REM
REM
REM - - -I NITIALIZE MODES AND GAl NS- -OUT MODEl ,0: OUT MODE2,0
REM
REM
REM ---CALCULATE VARIABLES--X = X + FX*ex
Yl =Yl + FYI "CVl
Y2 = '12 + FY2*CY2
Y3 = Y3 + FY3*CY3
If X> 255 THEN X = 255: CX = -1: GOTO 270
I F X < 0 THEN X = 0: ex = 1
If Yl > 255 THEN Yl =255: CVl = -1: GOTO 290
IF Yl < 0 THEN Yl =0: CYI = 1
IF V2 > 255 THEN Y2 =255: CY2=-I: GOTO 310
IF Y2 < 0 THEN Y2 = 0: CV2=-1
IF Y3 > 255 THEN V3 = 255: CV3=-I: GOTO 400
If V3 < 0 THEN Y3=0: CY3= 1
REM
REM
REM ---SEND DAC DATA--OUT DACA,X
OUT DAC8,Yl
OUT DACC ,Y2
OUT DACD,Y3
OUT DAC2ND,0
REM
REM
REM ---lOOP BACK--GOTO 210
2-120 DIGITAL-TO-ANALOG CONVERTERS
AD664
Simple AD664 to MC68000 Interfac:e
Figure 28 shows an AD664 connected to an MC68000. In this
memory-mapped I/O scheme, the "left-justified" data is written
in one 12-bit input word. Four address bits are used to perform
the on-chip D/A selection as well as the various operating features.
The RiW signal controls the RD function and system reset
controls RST.
This scheme can be converted to write "right-justified" data by
connecting the data inputs to DATA bits DO through DB
respectively. Other options include controlling the QSO, QS I
and QS2 pins with UDS and LDS to provide a way to write
8-bit input and read 8-bit output words.
MC68000
MICROPROCESSOR
··
-[
--BUS
A23
A7
V ccl21
AO
GNOl21
elK
OB16
~,.[
BUS
OBO
---
-,-
AS
RtW
FCO
FC1
FC2
_E
.---
UOS
r~
1;~giZl=IDII~::
~
-
LOS
OTACK ~
iiii
VMA
BG
VPA
BGACK
f-f--
I-
'--- OSO
i-
AD664
OSO
~ J
OS1
OS2
;
BERR
IPlO
RESET
iiiL1
f-f--
-< (...
IPL2
f--
200pF
HALT
QQQQQQQQQQI!!I!!
OS1
570pF
cs
RO
I
*10
270
LS TR
I
MS
L 1
I
RST
+5v
Figure 28. AD664 to MC6BOOO Interface
DIGITAL-TO-ANALOG CONVERTERS 2-121
•
COMPARE
C=:::-':===:-:-::'l-~~../
!-"1~j1"""'J.--+-+-""":~
REGISTER
AD664
Figure 29. AD664 in a "Tester-Per-Pin" Architecture
APPLICATIONS OF THE AD664
"Tester-Per-Pin" ATE
Architec:~
Figure 29 Shows the AD664 used in a single chaonel of a digital
test system. In this scheme, the AD664 supplies four individual
output voltages. Two are provided to the VHIGH and V LOW
inputs of the AD345 pin driver I.C. to set the digital output
levels. Two others are routed to the inputs of the AD96687 dual
comparator to supply reference levels of the readback features.
This approach can be replicated to give as many chaonels of
stimuluslreadback as the tester has pins. The AD664 is a particularly appropriate choice for a large-scale system because the
low power requirements (under sOOmW) ease power supply and
cooling requirements. Analog ground currents of 600f,LA or less
make the ground current management task simpler. All DACs
can be driven from the same system reference and will track
over time and temperature. Finally, the sma1l board area required
by the AD664 (and AD345 and AD96687) allows a high functional
density.
Drawing scaling can be achieved by taking advantage of the
AD664's software programmable gain settings. If, for example,
an "A" size drawing is created with gain settings of 1, then a
"c" size drawing can be created by simply resetting all DAC
gains to 2 and redrawing the object. Conversely, a "c" size
drawing created with gains of 2 can be reduced to "A" size
simply by changing the gains to 1 and redrawing. The same
principal applies for conversion from "8" size to "D" size or
"D" size to "8" size. The multiplying capability of the AD664
provides another scaling option. Changing the reference voltage
provides a proportional change in drawing size. Inverting the
reference voltage would invert the drawing.
Swapping digital input data from the X channel to the Y chaonel
would rotate the drawmg 90 degrees.
X-Y Plotters
Figure 30 is a block diagram of the control section of a microprocessor-controlled X-Y pen plotter. In this conceptual exercise,
two of the DACs are used for the X-chaonel drive and two are
used for the Y-channel drive. Each provides either the coarse or
fme movement control for its respective chaonel. This approach
offers increased resolution over some other approaches.
X DRIVE
A designer can take advantage of the reset feature of the AD664
in the following maoner. If the system is designed such that the
"HOME" position of the pen (or galvanometer, beam, head or
similar mechanism) results when the outputs of all of the DACs
are at zero, then no system software is required to home the
pen. A simple reset signal is sufficient.
Similarly, the transparent feature could be used to the same
end. One code can be sent to all DACs at the same time to send
the pen to the home position. Of course, this would require
some software where the previous example would require only a
single reset strobe signall
2-122 DIGITAL-TO-ANALOG CONVERTERS
Y DRIVE
TRANS ADDRESS DATA RESET
Figure 30. X- Y Plotter Block Diagram
1IIIIIIII ANALOG
WDEVICES
Microprocessor-Compatible
12-Bit D/A Converter
AD667*
FEATURES
Complete 1Z-Bit D/A Function
Double-Buffered Latch
On Chip Output Amplifier
High Stability Buried Zener Reference
Single Chip Construction
Monotonicity Guaranteed Over Temperature
Linearity Guaranteed Over Temperature: 1/ZLSB max
Settling TIme: 3...s max to 0.01%
Guaranteed for Operation with % 1ZV or % 15V
Supplies
Low Power: 300mW Including Reference
TTU5V CMOS Compatible Logic Inputs
Low Logic Input Currents
I
AD667 FUNCTIONAL BLOCK DIAGRAM
{LSBI
IMSBI
OB11- __ DB8
+Vcc
POWER
-VEl
GND
PRODUCT DESCRIPTION
The AD667 is a complete voltage output 12·bit digital-to-analog
converter including a high stability buried Zener voltage reference
and double-buffered input latch on a single chip. The converter
uses 12 precision high speed bipolar current steering switches
and a laser trimmed thin film resistor nerwork to provide fast
settling time and high accuracy.
Microprocessor compatibility is achieved by the on-chip doublebuffered latch. The design of the input latch allows direct interface
to 4-, 8-, 12-, or l6-bit buses. The 12 bits of data from the first
rank of latches can then be transferred to the second rank,
avoiding generation of spurious analog output values. The latch
responds to strobe pulses as short as lOOns, allowing use with
the fastest available microprocessors.
The functional completeness and high performance in the AD667
results from a combination of advanced switch design, high
speed bipolar manufacturing process, and the proven laser wafertrimming (LWT) technology. The AD667 is trimmed at the
wafer level and is specified to ± 1I4LSB maximum linearity
error (K, B grades) at 25°C and ± 1I2LSB over the full operating
temperature range.
The subsurface (buried) Zener diode on the chip provides a
low-noise voltage reference which has long-term stability and
tempemture drift characteristics comparable to the best discrete
reference diodes. The laser trimming process which provides the
excellent linearity, is also used to trim the absolute value of the
reference as well as its temperature coefficient. The AD667 is
thus well suited for wide tempemture range performance with
± 1I2LSB maximum linearity error and guaranteed monotonicity
over the full temperature range. Typical full scale gain T.C. is
5pprnl°C.
The AD667 is available in five performance grades. The AD667J
and K are specified for use over the 0 to + 70°C temperature
range and are available in a 28-pin molded plastic DIP (N) or
PLCC (P) package. The AD667S grade is specified for the
- 55°C to + 125°C range and is available in the ceramic DIP
(D) or LCC (E) package. The AD667A and B are specified for
use over the - 25°C to + 85°C temperature range and are available
in either a 28-pin hermetically sealed ceramic DIP (D) or LCC
(E) package.
PRODUCT HIGHLIGHTS
1. The AD667 is a complete voltage output DAC with voltage
reference and digital latches on a single IC chip.
2. The double-buffered latch structure permits direct interface
to 4-, 8-, 12-, or 16-bit data buses. All logic inputs are TTL
or 5 volt CMOS compatible.
3. The internal buried Zener reference is laser-trimmed to 10.00
volts with a ± I % maximum error. The reference voltage is
also available for external application.
4. The gain setting and bipolar offset resistors are matched to
the internal ladder network to guarantee a low gain temperature
coefficient and are laser-trimmed for minimum full scale and
bipolar offset errors.
5. The precision high speed current steering switch and on-board
high speed output amplifier settle within 1I2LSB for a IOV
full scale transition in 2.011s when properly compensated.
*Covered by Patent Numbers 3,803,590; 3,890,611; 3,932,863; 3,978,473;
4,020,486; and others pending.
DIGITAL-TO-ANALOG CONVERTERS 2-123
SPECIFICATIONS
(T,= +25"1:, :t12V. :t15V power supplies IIIIass otharwise notad)
Model
AD667J
Typ
Min
DIGITAL INPUTS
Resolution
Logic Levels(TTLCompatible, T,.;.-T_)1
VIH (Logie "I")
VIL (Logie "0")
1m (Vm = S.sV)
IlL (VIL=0.8V)
TRANSFER CHARACfERISTICS
ACCURACY
Linearity Error@ + 2S"C
TA=TmmtoTmu:
Differential Linearity Error@ + 2S"C
TA=TmintoTmu:
Gain
Unipolar Offset
Bipolar Zero2
Error
Error
+S.s
+2.0
0
REFERENCE OUTPUT
External Current
:!: 114
:!:1/2
:!: 112
±3/4
:!: 112
±3/4
MODotoniclty Guaranteed
:!:O.I
±0.2
:tl
±2
:!:O.OS
±0.1
:!:2
:!:5
±I
±5
TEMPERATURE RANGE
Specification
Storage
AD667K
Typ
+2.0
0
3
I
Unils
12
Bits
+S.s
V
V
+0.8
10
5
±1/4
±112
:!:1/4
±112
MODotonicltyGuaranteed
±Q.2
:!:O.I
:!:I
±2
:!:O.OS
±0.1
:!:2
±5
4
3
3
2
I
10
Mas:
:!: 1/8
:!: 114
±30
±3
±1O
3
2
I
±IS
±3
±1O
4
3
10
±5
0.05
:!:
10.00
1.0
10.10
5
5
10
10
9.90
0.1
12,::!:: 15
V
10.00
1.0
10.10
V
5
5
10
10
pprnofFSI%
ppmofFS/%
±16.5
V
V
±11.4
12
25
0
-65
1'8
1-'5
1'8
rnA
0
rnA
rnA
±I2, ±IS
±16.5
8
20
ppmofFSRI"C
ppm ofFSRI"C
ppmofFSRI"C
ppm ofFSRI"C
40
0.05
40
±11.4
LSB
LSB
LSB
LSB
%ofFSR'
LSB
%ofFSR
+5, + 10
:!:5
9.90
0.1
!LA
!LA
VII'S
±2.5, ±5, ± 10,
::!::2.S, ±S, ± 10,
+5, + 10
POWER SUPPLY SENSITIVITY
Vee = + I 1.4 to + 16.5V de
VEE = -11.4to -16.5V de
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range'
Supply Current
+ 11.4 to + 16.SV de
-11.4to -16.5Vde
+0.8
10
5
3
I
ANALOG OUTPUT
Ranges'
Output Current
Output Impedance (de)
Short Cireuit Current
Min
12
DRIFT
Differential Linearity
Gain (Full Scale) TA = 2S"C to T .... or T....,.
Unipolar Offset T A = 25"C to T .... ot T max
Bipolar Zero T A = 25"C to T .... or T max
CONVERSION SPEED
Settling Time to ±O.OI%ofFSRfor
FSR Change (2kOiiSOOpF load)
with IOkO Feedback
with 5kO Feedback
For LSB Change
Slew Rate
Mas:
8
20
+70
+ 125
0
-65
12
rnA
25
rnA
+70
+125
°C
"C
NOTES
lThe digital input specifications are 100% tested at + 25°C, and guaranteed but not tested over the full temperature range.
2Adjustable to zero.
3FSR means "Full Scale Range" and is 20V for:!: 10V range and lOY for the ± SV range.
4A minimwn power supply of ± 12.SV is required for a ± lOY full scale output and ± 11.4V is required for all other voltage ranges.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final
dectrical test. Results from those tests are used to calculate outgoing quality
ABSOLUTE MAXIMUM RATINGS
levels. All min and max specifications are guaranteed, although only those
Vcc to Power Ground . . . . • .
shown in boldface are tested on all production units.
TIMING SPECIFICATIONS
(All Models, TA = 25°C, Vcc= + 12Vor + 15V,
VEB= -12Vor -15V)
Min
Symbol Parameter
Data Valid to EndofCS
50
tDC
Address Valid to End ofCS
100
tAC
CS Pulse Width
100
fcp
Data Hold Time
0
tDH
Output Voltage Settling Time
tSBTT
Typ Max
2
2-124 DIGITAL-TO-ANALOG CONVERTERS
4
ns
ns
ns
ns
IJoS
. OV to +18V
VEE to Power Ground . . . . . .
• OV to -18V
Digital Inputs (pins 11-15,17-28)
to Power Ground . . • . . . .
- LOV to + 7.0V
Ref In to Reference Ground • . .
± 12V
Bipolar Offset to Reference Ground •
± 12V
10V Span R to Reference Ground . .
± 12V
± 24V
20V Span R to Reference Ground . •
Ref Out, Your (Pins 6, 9) .. Indefinite short to power ground
Momentary Short to Vcc
Power Dissipation . . . . . • . . . . . . . • • • .•. 1000mW
AD667
Model
AD667A
Typ
MiD
DIGITAL INPUTS
RosoIution
l.oiIic Levels (TIL Compatible, T .... _ T ....)1
VIH (Losic "I")
VIL (Losic ''0'')
11H(VIH=S.sV)
In. (VIL=0.8V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error@ + 2S"C
T/t.= TmiD10Tmu
Differential Linearity Error@ + 2S"C
TA=Tmin1OTmu:
Gain Error'
Unipolar Offset Error'
Bipolar z.ro2
Typ
MiD
12
+2.0
0
3
I
+5.5
+0.8
10
5
±1/4
:t:I/2
±1/2
:t:3I4
±I/2
:t:3I4
MonotoDicity Gunateed
±O.I
:t:0.2
±I
:t:2
±0.05
:t:O.l
DRIFT
Differential Linearity
Gain (Full Sc:ale} Tit. = 2S"C to T min or T ....
Unipolar Offset T" = 2S"C to T min or T ....
Bipolar Zero Tit. = 2S"C to T min or T .....
CONVERSION SPEED
Settling Time to ±O.OI%ofFSRfor
FSR cbanse (ZknlISOOpF load)
witb IOkn Feedback
with 5k1l Feedbsck
For LSBCbanse
S1ewRate
AD667B
Mu:
:!:2
±5
±I
:::s
3
2
I
Typ
MiD
12
+2.0
0
3
I
+5.5
+0.8
10
5
+2.0
0
3
I
±2
±S
4
3
3
2
I
Mu:
Units
12
Bits
+5.5
+0.7
10
5
V
V
"'"'""
:!: 118
:t:II2
:!: 112
:t:3/4
:!: 114
:t:3I4
MoootoDicity Guaranteed
:!:O.I
:t:0.2
:!:I
:t:2
:!:0.05
:t:0.1
± 118
:t:I/4
±1I4
:t:II2
±1/4
:t:112
MoootoaicltyG........teed
:t:0.2
±O.I
±I
:t:2
±O.OS
:t:O.l
±3O
:t:3
:t:10
10
AD667S
Mu:
±2
±IS
:!: 15
:t:3
:t:1O
4
3
3
2
1
10
LSB
LSB
LSB
LSB
%ofFSR'
LSB
%ofFSR
ppmofFSRI"C
ppm ofFSRI"C
ppm of FSRI"C
ppmofFSRI"C
:t:3O
:t:3
:t:l0
..... ---
4
3
V/ .._
10
ANALOG OUTPUT
Ranses4
±2.S, :5,:!: 10,
+S, +10
Output Current
Output Impedaru:e(dc)
Shon Circuit Current
±S
:!:2.S, ±5,:!: 10,
+S, +10
±S
POWER SUPPLY SENSITIVITY
Vcc= +11.4to+16.SVdc
VEE = -11.4to-16.SVdc
POWER SUPPLY REQUIREMENTS
Rated Voltqes
Ranse4
:!:
10.00
1.0
10.10
S
5
10
10
Supply Current
+ I 1.4 to + 16.5Vdc
-11.4to -16.5Vdc
8
20
TEMPERATURE RANGE
Specification
Storsse
-25
-65
Po2'/IoJJ-~t-==tAC-j x==
8
20
-25
-65
1-... =1
40
mA
10.00
1.0
lo.IO
V
mA
5
5
10
10
ppmofFSI%
ppmofFSI%
:t:I6.5
V
V
12
25
mA
mA
+ 125
+ 150
"C
"C
:tI2, :tIS
:t:11.4
12
25
8
20
- 55
-65
+85
+150
r-t.c-J
I/
-~r-~=j-
A3 - - ' " " ' \
I~
\\\ j
10
10
:t:I6.5
1-<00-1
--~Xl.-
5
5
9.90
0.1
WRITE CYCLE *2
(Load Second Rank from First Rank; A2, AI, AO= 1)
WRITE CYCLE *1
(Load First Rank from Data Bus; A3 = 1)
DB11-DBD _ _ _ _ _...1
lo.IO
:t:11.4
12
25
+85
+150
TIMING DIAGRAMS
10.00
1.0
±I2, ±IS
:t:I6.5
n
O.OS
40
9.90
0.1
12,:t" 15
:t:11.4
mA
O.OS
40
9.90
0.1
V
+ 5. + 10
±S
O.OS
REFERENCE OUTPUT
Extemal Current
± 2.S, ± 5, ± 10,
cs
to.
OUTPUT
l=="ETT ------.-=<-.I.......rt....
.
7
-----'--
-
"!2LSB
DIGITAL-TO-ANALOG CONVERTERS 2-125
•
28-PIN DIP CONNECTIONS
e"
PLCC, LCC PIN CONNECTIONS
DB11 (MSB)
DB10
PIN 1
IDENTIFIER
DB9
DBB
DB7
DBB
REFGND
DB6
VREF OUT
VIiEFIN
AD667
DBS
+Vcc
TOP VIEW
(Not to Scale)
DB4
DB7
AD667
TOP VIEW
(Not to Scale)
+Vcc
DB3
-VEE
DB2
DB2
CS
DB1
A3
DBa (LSB)
A2
POWER GROUND
A1
AO
"NOTE DIP PACKAGE PIN NUMBERS
AND LCC CONTACT NUMBERS SERVE
THE SAME FUNCTION.
ORDERING INFORMATION
Package Options·
Plastic DIP (N-28)
PLCC (P-28A)
Plastic DIP (N-28)
PLCC (P-28A)
Ceramic DIP (D-28)
LCC(E-28A)
Ceramic DIP (D-28)
LCC(E-28A)
Ceramic DIP (D-28)
LCC(E-28A)
Temperature
Range-OC
Oto +70
Oto +70
Oto +70
Oto +70
-25to +85
-25to +85
-25to +85
-25to +85
-55to +125
-55to + 125
*See Section 14 for package outline information.
2-126 DIG/TAL-TO-ANALOG CONVERTERS
DBS
DB4
DB3
Model
AD667JN
AD667JP
AD667KN
AD667KP
AD667AD
AD667AE
AD667BD
AD667BE
AD667SD
AD667SE
DB6
Linearity
Error Max
@25°C
±1I2LSB
±1I2LSB
±1I4LSB
±1I4LSB
±1I2LSB
±1I2LSB
±1I4LSB
±1I4LSB
±1I2LSB
±1I2LSB
GainT.C.
Maxppm/"C
30
30
15
IS
30
30
IS
IS
30
30
Analog Circuit Details - AD667
THE AD667 OFFERS TRUE 12-BIT PERFORMANCE
OVER THE FULL TEMPEllATURE RANGE
LINEARITY ERROR: Analog Devices defines linearity error
as the maximum deviation of the actual, adjusted DAC output
from the ideal analog output (a straight line drawn from 0 to
F.S. - ILSB) for any bit combination. The AD667 is laser
trimmed to 1/4LSB (0.006% of F.S.) maximum error at +2S"<:
for the K and B versions and 1I2LSB for the J, A and S
versions.
UNIPOLAR CONFIGURATION (Fipre 2)
This configuration will provide a unipolar 0 to + 10 volt output
range. In this mode, the bipolar offset terminal, pin 4, should
be grounded if not used for trimming.
•
MONOTONICITY: A DAC is said to be monotonic if the
output either increases or remains constant for increasing digital
inputs such that the output will always be a nondecreasing
function of input. All versions of the AD667 are monotonic over
their full operating temperature range.
DIFFERENTIAL NONLINEARITY: Monotonic behavior
requires that the differential linearity error be less than ILSB
both at + 25"<: and over the temperature range of interest.
Differential nonlinearity is the measure of the variation in analog
value, normalized to full scale, associated with a ILSB change
in digital input code. For example, for a 10 volt full scale output,
a change of ILSB in digital input code should result in a 2.44mV
change in the analog output (ILSB= 10Vx 1I4096=2.44mV). If
in actual use, however, a ILSB change in the input code results
in a change of only 0.61mV (1I4LSB) in analog output, the
differential linearity error would be -1.83mV, or -3/4LSB.
The AD667K and B grades have a max differential linearity
error of 1I2LSB, which specifies that every step will be at least
1I2LSB and at most I 112 LSB.
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD667 may be connected
to produce bipolar output voltage ranges of ± 10, ± S or ± 2.SV
or unipolar output voltage ranges of 0 to + SV or 0 to + 10V.
Gain and offset drift are minimized in the AD667 because of the
thermal tracking of the scaling resistors with other device components. Connections for various output voltage ranges are
shown in Table I.
Figure 2. 0 to
+ 10V Unipolar
Voltage Output
STEP I ... ZERO ADJUST
Turn all bits OFF and adjust zero trimmer RI, until the output
reads 0.000 volts (lLSB=2.44mV). In most cases this trim is
not needed, and pin 4 should be connected to pin S.
STEP II ... GAIN ADJUST
Turn all bits ON and adjust lOOn gain trimmer R2, until the
output is 9.9976 volts. (Full scale is adjusted to I LSB less than
nominal full scale of 10.000 volts.)
BIPOLAR CONFIGURATION (FJgUre 3)
This configuration will provide a bipolar output voltage from
-S.OOO to +4.9976 volts, with positive full scale occurring with
all bits ON (all l's).
STEP I ... OFFSET ADJUST
Turn OFF all bits. Adjust 1000 trimmer RI to give - 5.000
volts output.
STEP II ... GAIN ADJUST
Turn ON all bits. Adjust 1000 gain trimmer R2 to give a reading
of +4.9976 volts.
r-_ _ _ _~."'
...;;;;";;:.1---_I4 Zl:~~,."
SUMMING
JUNCTION
FROM WEIGHTED
RESISTOR ....-
!iI
AGND
10V SPAN
-".,...-_--'\I\_--l
......
NETWORK
I~,
Figure 1. Output Amplifier Voltage Range Scaling Circuit
Figure 3. ± 5V Bipolar Voltage Output
Range
Digital
Input Codes
Connect
Pin9to
Connect
Pinlto
Connect
Pin'2to
Connect
Pin 4 to
±lOV
±5V
±2.SV
Oto + lOY
Oto +SV
Offset Binary
Offset Binary
Offset Binary
Straight Binary
Straight Binary
1 and 2
2
I and 2
2
9
2 and 9
3
2 and 9
3
NC
1 and 9
9
1 and 9
9
6 (through 500 fixed or lOOOtrim resistor)
6 (through son fixed or lOOOtrim resistor)
6 (through 500 fixed or lOOOtrimresistor)
5 (or optional trim - See Figure 2)
5 (or optional trim- See Figure 2)
Output
Table I. Output Voltage Range Connections
DIGITAL-TO-ANALOG CONVERTERS 2-127
INTERNALlEXTERNAL REFERENCE USE
The AD667 has an intcmallow-noise buried zener diode reference
which is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for usc in a high
speed DAC and will give long-term stability equal or superior to
the best discrete zener reference diodes. The performance of the
AD667 is sPecified with the internal reference driving the DAC
since all trimming and testing (espccially for full scale error and
bipolar offset) is done in this configuration.
The intcmal reference has sufficient buffering to drive external
circuitry in addition to the reference currents required for the
DAC (typically 0.5mA to Ref In and LOrnA to Bipolar Offset).
A minimum of O.lmA is available for driving extcrnalloads.
The AD667 refcrcncc output should be buffered with an external
op amp if it is required to supply more than O.lmA output
current. The reference is typically trimmed to ± 0.2%, then
tested and guaranteed to ± 1.0% max error. The temperature
coefficient is comparable to that of the full scale TC for. a particular
grade.
If an extcmal reference is used (10.000V, for example), additional
trim range must be provided, since the intcrna1 reference has a
tolerance of ± 1%, and the AD667 full-scale and bipolar offset
are both trimmed with the intcrna1 reference. The gain and
offset trim resistors give about ± 0.25% adjustment range,
which is sufficient for the AD667 when used with the intcrna1
reference.
It is also possible to use external references other than 10 volts.
The recommended range of reference voltage is from + 8 to
+ 11 volts, which allows both 8. 192V and 10.24V ranges to be
used. The AD667 is optimized for fIxed-reference applications.
If the reference voltage is expected to vary over a wide range in
a particular application, a CMOS multiplying DAC is a better
choice.
the system. The power ground at pin 16 can be connected to
the most convenient ground point; analog power return is preferred. If power ground contains high frequency noise beyond
200mV, this noise may feed through the converter, thus some
caution will be required in applying these grounds.
It is aiiio important to apply decoup1ing capacitors properly on
the power supplies for the AD667 and the output amplifter.
The correct method for decoupling is to connect a capacitor
from each power supply pin of the AD667 to the analog ground
pin of the AD667. Any load driven by the output amplifter
should also be referred to the analog ground pin.
OPTIMIZING SETTLING TIME
The dynamic performance of the AD667's output amplifter can
be optimized by adding a small (2OpF) capacitor across the
feedhack resistor. Figure 4 shows the improvement in both
large-signal and small-signal settling for the 10V range. In Figure
41, the top trace shows the data inputs (DBII-DBO tied together),
the second trace shows the CS pulse (A3-AO tied low), and the
lower two traces show the analog outputs for C p = 0 and 20pF
respectively.
Figures 4b and 4c show the settling time for the transition from
all bits on to all bits off. Note that the settling time to ± 1I2LSB
for the lOY step is improved from 2.4 microseconds to 1.6
microseconds by the addition of the 20pF capacitor.
Figures 4d and 4e show the settling time for the transition from
all bits off to all bits on. The improvement in settling time
gained by adding Cc = 20pF is similar.
Reduced values of reference voltage will also permit the ± 12
volt ± 5% power supply requirement to be relaxed to ± 12 volts
±1O%.
It is not recommended that the AD667 be used with external
feedhack resistors to modify the scale factor. The internal resistors
are trimmed to ratio-match and temperature-track the other
resistors on the chip, even though their absolute tolerances are
± 200/0, and absolute temperature coefficients are approximately
- 50ppml"C. If external resistors are used, a wide trim range
( ± 20%) will be needed and temperature drift will be increased
to reflect the mismatch between the temperature coefficients of
the internal and external resistors.
Small resistors may be added to the feedback resistors in order
to accomplish small modifIcations in the scaling. For example, if
a 1O.24V full-scale is desired, a 1400 1% low-TC metal-fIlm
resistor can be added in series with the internal (nominal) 5k
feedback resistor, and the gain trim potentiometer (between
pins 6 and 7) should be increased to 2000. In the bipolar mode,
increase the value of the bipolar offset trim potentiometer also
to 2000.
a. Large Scale Settling
V otn.1LSBIDIY
+- -
~
I
---t--t-
I-I -1- ~- soonS
V ouT.5V/01V
b. Fine-Scale Settling, CF=OpF
0811-080
GROUNDING RULES
The AD667 brings out separate analog and power grounds to
allow optimum connections for low noise and high speed performance. These grounds should be tied together at one point,
usually the device power ground. The separate ground returns
are provided to minimize current flow in low-level signal paths.
The analog ground at pin 5 is the ground point for the output
amplifter and is thus the "high quality" ground for the AD667;
it should be connected directly to the analog reference point of
2-128 DIGITAL-TO-ANALOG CONVERTERS
- _L
-i-_'-t 1-1___
_ ~
_...L._
~I
=========_
,
VouT,1LS8JDIV
500nS
Vour.5VIDIV
c. Fine-Scale Settling, CF=20pF
Figure 4. Settling Time Performance
AD667
I >2mY
0811-018
It is permissible to enable more than one of the latches simultaneously. If a flI'St rank latch is enabled coincident with the
second rank latch, the data will reach the second rank correctly
if the "WRITE CYCLE 1" timing specifications are met.
*
VOC,lTo 1LSBlDIV
Vatu.SVIDIV
d. Fine-Scale Settling, CF=OpF
CS
A3 A2 Al AO
Operation
I
X
1
I
No Operation
No Operation
Enable 4 LSBs of First Rank
Enable 4 Middle Bits of First Rank
Enable 4 MSBs of First Rank
Loads Second Rank from First Rank
All Latches Transparent
X
0
0
0
0
0
I
I
0
0
X
I
I
I
0
1
0
X
1
I
0
X
1
0
I
I
I
1
0
1
0
"X"=Don'tCare
Table II. AD667 Truth Table
VQUT.1LSBIOIV
5V
500nS
.
VOUT.5ViOIV
e. Fine-Scale Settling, CF=20pF
Figure 4. Settling Time Performance (Continued)
DIGITAL CIRCUIT DETAILS
The bus interface logic of the AD667 consists offour independently
addressable registers in two ranks. The first rank consists of
three four-bit registers which can be loaded directly from a 4-,
8-, 12-, or 16-bit microprocessor bus. Once the complete 12-bit
data word has been assembled in the flI'St rank, it can be loaded
into the 12-bit register of the second rank. This double-buffered
organization avoids the generation of spurious analog output
values. Figure 5 shows the block diagram of the AD667 logic
section.
IMSal
DB11 - - - D88
087 ___ D84
IUISI
DB3 ___ OBO
INPUT CODING
The AD667 uses positive-true binary input coding. Logic "I" is
represented by an input voltage greater than 2.0V and logic "0"
is defined as an input voltage less than 0.8V.
Unipolar coding is straight binary, where all zeroes (OOOIiJ on
the data inputs yields a zero analog output and all ones (FFFIiJ
yields an analog output 1LSB below full scale.
Bipolar coding is offset binary, where an input code of ()()(lH
yields a minus full-scale output, an input of FFFH yields an
output lLSB below positive full scale, and zero occurs for an
input code with only the MSB on (800H).
The AD667 can be used with two's complement input coding if
an inverter is used on the MSB (DB11).
DIGITAL INPUT CONSIDERATIONS
The threshold of the digital input circuitry is set at 1.4 volts
and does not vary with supply voltage. The input lines can thus
interface with any type of 5 volt logic. The configuration of the
input circuit is shown in Figure 6.
+ Vee
DIGITAL
INPUTS
(PINS 11 - 15
AND 17 - 28)
I
I
I
30kH
.--....- - 0 0
J
GROUND~
POWER
Figure 5. AD667 Block Diagram
The latches are controlled by the address inputs, AO-A3, and
the CS input. All control inputs are active low, consistent with
general practice in microprocessor systems. The four address
lines each enable one of the four latches, as indicated in
Table II.
All latches in the AD667 are level-triggered. This means that
data present during the time when the control signals are valid
TO LOGIC
-O.7V
Figure 6. Equivalent Digital Input Circuit
The AD667 data and control inputs will float to a logic 0 if left
open. It is recommended that any unused inputs be connected
to power ground to improve noise immunity.
Fanout for the AD667 is 100 when used with a standard low
power Schottky gate output device.
will enter the latch. When anyone of the control signals returns
high, the data is latched.
DIGITAL-TO-ANALOG CONVERTERS 2-129
•
8-BIT MICROPROCESSOR INTERFACE
The AD667 interfaces easily to 8-bit microprocessor systems of
all types. The control logic makes possible the use of right- or
left-justified data formats.
Whenever a 12-bit DAC is loaded from an 8-bit bus, two bytes
are required. If the program considers the data to be a 12-bit
binary fraction (between 0 and 4095/4096), the data is left-justified,
with the eight most significant bits in one byte and the remaining
bits in the upper half of another byte. Right-justified data calls
for the eight least significant bits to occupy one byte, with the 4
most significant bits residing in the lower half of another byte,
simplifying integer arithmetic.
I
I
DBll
I
DB3
I
DBlol DB91 DB8
DB2
I
OBl
I
DBD
I
I
DB71 OB61 DB51 DB41
x
I
x
x
x
Right-justified data can be similarly accommodated. The overlapping of data lines is reversed, and the address connections
are slightly different. The AD667 still occupies rwo adjacent
locations in the processor's memoty map. In the circuit of Figure
9, location XOlloads the 8LSBs and location XIO loads the
4MSBs and updates the output.
r-
.--r--
,....
07
06
05
0'
01
DO
A15
I
a. Left Justified
I
I
I
DB'
DB3
DB2
DB1
03
02
WR
DB11 (MSB)
0810
DB.
DBa
DB7
DB6
DB5
DBO (LSB)
;,
ADDRESS,
DECODER
AD667
~ os
A2
A1
I~I~I~I~I~I~I~I~I
AD
L:
AD
A1
L
A2
A3
b. Right Justified
Figure 7. 12-Bit Data Formats for 8-Bit Systems
Figure 8 shows an addressing scheme for use with an AD667 set
up for left-justified data in an 8-bit system. The base address is
decoded from the high-order address bits and the resultant
active-low signal is applied to CS. The two LSBs of the address
hus are connected as shown to the AD667 address inputs. The
latches now reside in two consecutive locations, with location
XOI loading the four LSBs and location XIO loading the eight
MSBs and updating the output.
OB11jMSB)
OB10
DB.
DBa
DB7
DB6
DB5
07
06
05
0'
03
02
01
DO
L-
WR
A15
I
I
I
-
-'---
ADDRESS
DECODER
DB'
DB3
DB2
DB1
Dao (LSB)
AD667
AO
A1
r
L
USING THE AD667 WITH 12- AND 16-BIT BUSES
The AD667 is easily interfaced to 12- and 16-bit data buses. In
this operation, all four address lines (AO through A3) are tied
low, and the latch is enabled by CS going low. The AD667 thus
occupies a single memory location.
This configuration uses the first and second rank registers
simultaneously. The CS input can be driven from an active-low
decoded address. It should be noted that any data bus activity
during the period when CS is low will cause activity at the
AD667 output. If data is not guaranteed stable during this
period, the second rank register can be used to provide double
buffering.
DB11 (MSB)
011
010
oatO
D.
A1
A2
A3
Da
DO
03
02
01
DO
A15
I
,I
AO
Figure 8. Left-Justified 8-Bit Bus Interface
7
DB'
DBa
DB7
DB6
DB5
DB4
DB3
DB2
DB1
07
06
05
~ os
A2
AD
I
Figure 9. Right-Justified 8-Bit Bus Interface
DBO (LSB)
ADDRESS
DECODER
~ os
AD667
=----r
r-
tt-
+V
A3
A2
A1
AD
Figure 10. Connections for 12- and 16-Bit Bus Interface
2-130 DIGITAL-TO-ANALOG CONVERTERS
12-Bit Ultrahigh Speed
Multiplying D/A Converter
r.ANALOG
WDEVICES
AD668 I
AD668 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Ultrahigh Speed: Current Settling to 1 LSB in 50 ns
for a Full Scale Change in Digital Input. Voltage
Settling to 1 LSB in 80 ns for a Full Scale Change
in Analog Input
25 MHz Reference Bandwidth
Monotonicity Guaranteed over Temperature
10.24 mA Current Output or 1.024 V Voltage Output
Integral and Differential Linearity Guaranteed over
Temperature
0.3" "Skinny DIP" Packaging
THRESHOLD
COMMON
PRODUCT DESCRIPTION
The AD668 is an ultrahigh speed, l2-bit, multiplying digitalto-analog converter, providing outstanding accuracy and speed
performance in responding to both analog and digital inputs.
The AD668 provides a level of performance and functionality in
a monolithic device that exceeds that of many contemporary
hybrid devices. The part is fabricated using Analog Devices'
Complementary Bipolar (CB) Process, which features high-weeli
NPN and PNP devices on the same chip without the use of
dielectric isolation. The AD668's design capitalizeS on this proprietary process in combination with $tsndard .Iowcitnpedance.
circuit techniques to provide its unique combinatiQn of speed
.
and accuracy in a monolithic part.
The wideband reference input is buffered by a:high gain, closed
loop reference amplifier. The reference input is essentially a.
1 V, high impedance input, but trimmed resistive dividers are
provided to readily accommodate 5 V and 1.25 V references.
The reference amplifier features an effective small signal bandwidth of 25 MHz, and an effective slew rate of 3% of full
scale/ns.
Multiple matched current sources and thin film ladder
techniques are combined to produce bit weighting. The output
range can nominally be taken as a 10.24 rnA current output or a
1.024 V voltage output. Varying the analog input can provide
modulation of the DAC full scale from 10% to 120% of its nominal value. Bipolar outputs can be realized through pin-strapping
to provide two quadrant operation without additional external
circuitry.
LADOER
COMMON
ANALOG
COMMON
v"
Laser wafer trimming insures full l2-bit linearity and excellent
gain accuracy. All grades of the AD668 are guaranteed monotonic over their full operating temperature range. Furthermore,
the output resistance of the DAC is trimmed to 100 n ± 1.0%.
The AD668 is availa\:lie in three performance grades. The
AQ668JQ and KQ are available in 24-pin cerdip (0.3") packages
andll1'e'specified for operation from 0 to + 70°C. The AD668SQ
.felltures operation from -55°C to + 125°C and is also packaged
in the hermetic 0.3" cerdip.
PRODUCT HIGHLIGHTS
I. The fast settling time of the AD668 provides suitable performance (or waveform generation, graphics display, and highspeed NU'wnversion applications.
".~;
.The high bandwidth reference channel allows high frequency
modulation between analog and digital inputs.
3. The AD668's design is configured to allow wide variation of
the analog input, from 10% to 120% of its nominal value.
4. The AD668's combination of high performance and tremendous flexibility makes it an ideal building block for a variety
of high speed, high accuracy instrumentation applications.
5. The digital inputs are readily compatible with both TTL and
5 V CMOS logic families.
6. Skinny DIP (0.3") packaging minimizes board space requirements and eases layout considerations.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-131
•
SPECIFICATIONS
(@ TA
Model
Min
RESOLUTION
12
LSB WEIGHT (At Nominal FSR)
Current
Voltage (Current into RrJ
= +25°C, Vee = +15 V, VEE = -15 V, unless otherwise noted)
AD668J
Typ
Max
AD668K
Min
Typ
AD668
Max
12
Min
*
*
2.5
250
Typ
Max
12
*
*
iJA
..V
ACCURACY'
Linearity
T_toT"""
Differentisl Linearity
T_toT"""
Monotonicity
Unipolar Offset (Digital)
Bipolar Offset
Bipolar Zero
Analog Offset
Gain Error
-112
-3/4
-1
-1
GUARANTEED
-0.2
-1.0
-0.2
-0.5
-1.0
-112
-1/4
+114
+112
+112
-112
-314
+314
+314
+112
-112
-1
+1
+1
+112
-112
-1
+1
+1
+112
OVER RATED SPEClFlCATlON TEMPERATURE RANGE
+0.2
*
*
*
*
+1.0
*
*
*
*
+0.2
*
*
*
*
+0.5
*
*
*
*
+1.0
*
*
*
*
TEMPERATURE COEFFICIENTS2
Unipolar Offset
Bipolar Offset
Bipolar Zero
Analog Offset
Gain Drift
Gain Drift (lOUT)
-5
-15
-10
-30
-30
-100
+5
+15
+10
+30
+30
+100
REFERENCE INPUT
Input Resistance
5.0V
1.25 V
1.0 V
Reference Rsnge (T_
,
*
*
*
*
5
DATA INPUT
Logic Level (TnUn to T """)
VIH
V,L
Logic Currents (TnUn to T...J
1m
I'L
VTH Pin Voltage
10
1
100
2.0
0.0
-10
0
60
*
*
*
*
*
*
*
*
*
-10
0
7.0
0.8
+10
100
*
*
*
*
*
*
*
5
5
1
100
*
100
1.4
LSB
LSB
LSB
LSB
% ofFSR
% ofFSR
% ofFSR
% ofVNOM
% ofFSR
ppmofFSRrC
ppm of FSRf'C
ppmofFSRrC
ppm OfVNOMf'C
ppmofFSRrC
ppm of FSRf'C
kO
kO
120
Mo.
% ofVNoM
*
*
V
V
+10
200
iJA
-iJA
V
BINARY, OFFSET BINARY
CURRENT OUTPUT RANGES
VOLTAGE OUTPUT RANGES
OUTPUT COMPLIANCE
-2
OUTPUT RESISTANCE
Exclusive of RL
Inclusive of RL
160
99
REFERENCE AMPLIFIER
Input Bias Current
Slew Rate
Large Signal Bandwidth
Small Signal Bandwidth
Undervoltage Recovery Time
VRE"tVNOM to 0%
VRE"tVNOM to 1%
10
10
1.4
5
5
1
100
*
*
*
*
*
*
120
120
CODING
*
*
*
*
*
*
5
to T...J
*
*
Units
Bits
+1.2
200
100
1.5
240
101
oto 10.24, ±5.12
oto 1.024, ±0.512
*
*
*
*
*
*
*
*
*
*
*
mA
V
*
*
*
*
*
V
*
*
0.
0.
iJA
20
25
*
*
*
*
*
*
% ofFSlns
MHz
MHz
500
120
*
*
*
ns
ns
3
*
This information applies to a product under development. Its characteristics and specifications are subject to change without notice
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-132 DIGITAL-TO-ANALOG CONVERTERS
AD668
Min
Model
AD668J
Max
Typ
SETTLING TIME
Analog (10% to 120% Step)
to ±1%
to ±0.1%
to ±0.025%
Digital
Current to
±1%
±0.025%
Voltage (100 n, Internal Rd'
101%
to 0.01%
o to 0.025%
Glitch Impulse'
Peak Amplitude
POWER REQUIREMENTS
+10.S V to +16.5 V
-IO.S V to -16.5 V
Power Dissipation
PSRR'
TEMPERATURE RANGE
Rated Specification'
Storage
AD668K
Typ
Max
AD668
Typ
Min
Max
Units
60
90
120
*
*
*
*
*
*
ns to 1% ofFSR
ns to 0.1% ofFSR
ns to 0.025% of FSR
TBD
50
*
*
*
ns to 1% ofFSR
ns to 0.025% of FSR
25
50
SO
350
20
•
•
•
*
ns to 1% ofFSR
ns to 0.1% of FSR
ns to 0.025% of FSR
pV-sec
% ofFSR
27
7
510
*
*
-65
•
*
•
•
·
32
•
9
615
0.05
*
Al)Ii6S,J(!
*
., #
*
•
•
•
•
'"
•
•
.
+70
+150
0
PACKAGE OPTIoN"
Cerdip (Q-24)
Min
-55
+125
•
•
mA
-mA
mW
%ofFSRN
'C
'C
.,
., AD66SKQ
AD66SSQ
,
NOTES
I Measured in lOUT mode. Specified at nominal full-scale refer_.,
'Measured in VOUT mode, unless otherwise specified.
3Total resistance.
'At the major carry, driven by HCMOS logic.
'Measured at 15 V ±10% and 12 V ±IO%.
'See Section 14 for package outline information.
·Same as AD66SJ.
Specifications shown in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
PIN CONFIGURATION
REFERENCE COMMON IREfCDMI
configurations are provided in the section APPLYING THE
AD668. Subsequent sections contain more detailed information
useful in optimizing DAC performance in high-speed, high resolution applications.
REfERENCE INPUT 1 fRfFINti
21
REFERENCE INPUT 2 IREFIN21
lOUT
DIGITAL
INf'UTS
19
LOAD RESISTOR fALl
18
ANALOG COMMON IACOMI
17
LADDER COMMON (lCOM)
1&
BIPOLAR OFfSET IIBPOI
DAC Transfer Function
The AD668 may be used either in a current-output mode (with
the DAC output connected to a virtual ground) or a voltageoutput mode (DAC output connected to a resistive load.)
In current output mode:
Unipolar Mode
THRESHOLD COMMON (THCOMI
THRESHOLD CONTROL IVntl
VIN
lOUT = VNOM X
DAC code
4096
x 10.24 rnA
Bipolar Mode
FUNCTIONAL DESCRIPTION
The AD668 is designed to combine excellent performance with
maximum flexibility. The functional block diagram and the simple transfer functions provided below will provide the user with
a basic grasp of AD668's operation. Examples of typical circuit
VIN
lOUT = VNOM
x
DAC code
VIN
4096
x 10.24 rnA - V NOM x S.12 rnA
In voltage output mode:
vOUT =
lOUT X
R LOAD
(for both unipolar and bipolar modes)
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-133
Where:
VIN - the analog input voltage.
V NOM - the nominal full scale of the reference voltage: 1 V,
1.25 V, or 5 V, determined by the wiring confIguration of
Pins 21 and 22. (See APPLYING THE AD668.)
the 100 n trimming potentiometer shown in Figure 1. If trimming is not desired, a 50 n resistor may be used in place of the
potentiometer to produce the specified gain accuracy, or, if a
+ 1% nominal gain error is tolerable, the resistor may be omitted
altogether.
+15V
DAG code - the numerical representation of the DAC's digital inputs; a number between 0 and 4095.
TO ANALOG GROUND
PLANE
R LOAD - the resistance of the DAC output node; the maximum this can be is 200 n (the internal DAC ladder resistance). The on-board load resistor (Pin 19) has been trimmed
so that its parallel combination with the DAC ladder resistance is 100 n (±1%).
5VNOMINAL
REFERENCE INPUT
~------~~~-o+
Bipolar mode - produces a bipolar analog output from the
digital input by offsetting the normal output current with a
precision current source. This offset is achieved by connecting Pin 16 to the DAC output. In the unipolar mode, Pin 16
should be grounded.
ANALOG
SUPPLY
GROUND
Operating Limits:
/-t--<~----.o--- -'5V
0.1 <
VIN
<1.2
VNOM
!!I\l~"""------"Mr--. +5V
,.0
o
Max
Min
Tn>
12
+5.5
+0.8
+2.0
0
3
I
+2.0
0
10
5
:t 118
:1:112
:1:1/2
:t1/4
:t 114
:1:1
MODOtonicity Guaranteed
:to.1
:1:0.2
±I
:1:2
:to.05
:1:0.1
3
I
Max
Uaits
12
Bits
+5.5
+0.8
V
V
V
10
5
""'""'
:t112
:1:1
:1:1
:t1/2
:t1l2
:1:1
MODOtoniclty Guaranteed
:to.1
:1:0.2
:1:2
±I
:1:0.1
±0.05
LSB
LSB
LSB
LSB
%ofFSR'
LSB
%ofFSR
:t5
:tl
:t5
:t30
:1:3
:1:10
±5
:tl
±15
:1:3
:1:10
:t5
±I
±5
:t30
:t3
:t10
ppm ofFSRI"C
ppm ofFSRI"C
ppmofFSRrC
3
2
I
4
3
3
2
I
4
3
3
2
I
4
3
ILS
ILS
ILS
V/lLs
10,
V
10
10
10
ANALOG OUTPUT
±2.S, :tS,:!: 10,
Ranses6
Output Current
Output Impedance (de)
Short-Circuit Current
REFERENCE OUTPUT
External Current
POWER SUPPLY REQUIREMENTS
Rated Voltages
10.00
1.0
10.10
5
5
10
10
Supply Current
+ 11.4to + 16.5V de
- 11.4 to - 16.5V de
Total Power Consumption
9
18
400
10.00
1.0
lo.IO
5
5
10
10
9.90
0.1
mA
10.10
V
mA
5
5
10
10
ppmofFs/%
ppmofFS/%
:1:16.5
V
V
13
23
600
mA
mA
mW
:tI2, ±IS
:tI2, :tIS
:1:16.5
40
10.00
1.0
40
9.90
0.1
:tI2, :tIS
:l:ll.4
mA
:1:11.4
13
:1:16.5
9
18
400
23
600
n
0.05
0.05
40
9.90
0.1
:t
+5, +10
±5
0.05
POWER SUPPLY SENSITIVITY
Vee = + 11.4 to + 16.5V de
VEE = -11.4to-16.5Vde
Ranse6
:t5
±5
±2.S, :t5,
::!::2.S, ±S, ::!::lO,
+5, + 10
+5, +10
:1:11.4
9
18
400
13
23
600
TEMPERATURE RANGE
11K
AlB
S
Operating
Storage (All Grades)
0
-25
-55
-55
-65
+70
+85
+125
+ 125
+125
NOTES
0
-25
-55
-55
-65
+70
+85
+125
+125
+125
-25
+85
-65
+125
"s" specifications shown for information only. Consult Analog Devices Military Databook or contact factory for a controlled
specification sheet.
'AD767A Chips specifications are tested at +25'C and, when in boldface, at + 85'C. They are typical al -25'C.
'The digital input specifications are 100% tesled al + 25'C, and guaranleed bUI nol tested over the full temperature range.
'Adjustable to zero.
'FSR IDCIlIIS "Full·Sca1e ~.. and is 20V for :t IOV range and IOV for the :t 5V range.
6A minimum power supply of :t 12.5V is required for a :t 10V full-scale OUtpUI and :t 11.4V is required for all other voltage ranges.
Specifications subject to change withOUI notice:
I AD767
Specifications shown in boldface are tested on all production units al fina1
electrica1 tesl (eacept per Notes I and 2). Results from those tests are used to
ca1cuIste outaoing quality levels. All min and max specifications are guaranleed,
a1thoush only those shown in boldface are tested on all production units.
2-136 DIGITAL-TO-ANALOG CONVERTERS
"C
'C
"C
"C
"C
-
AD767
ABSOLUTE MAXIMUM RATINGS*
Vex:. to Power Ground . . . .
VEE to Power Ground . . . .
Digital Inputs (Pins 11, 13-24)
to Power Ground . . . . .
Ref In to Reference Ground .
Bipolar Offset to Reference Ground .
lOY Span R to Reference Ground .
20V Span R to Reference Ground .
Ref Out, VOlrr (Pins 6, 9) .. Indefinite short to power ground
Momentary Short to Vex:.
Power Dissipation . • . . . . . . . . . • . . • . . . . lOOOmW
. OV to +18V
. OV to -18V
-l.OV to +7.0V
±12V
±12V
±12V
±24V
TIMING SPECIFICATIONS
(All Models, T A = 25°C, Vex:. = + 12Vor + 15V,
VEE = -12Vor -15V)
* Stresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above tbose indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
Symbol Parameter
tos
tOH
les
tSETT
Data Valid to End ofCS
( - 25"C to + 85"C)
( - SS"C to + 125°C)
Data Hold Time
( - 25°C to + 85°C)
( - 55°C to + 125°C)
CS Pulse Width
( - 25°C to + 85°C)
( - 55°C to + 125°C)
Output Voltage Settling Time*
Min
Typ Max
40
-
60
90
10
10
20
40
60
90
-
-
2
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
ILS
-
*tSE'IT is measured referenced to the leading edge of les. If leS>tDS, then
tS£'IT is measured referenced to tbe beginning of Data Valid.
PIN CONFIGURATION
DIP
PLCC
'282721
BIPOFF
5
AD767
TOPVfIW
INotto s......
VOUT
11
AD767 ORDERING GUIDE
Model
AD767JN
AD767JP
AD767KN
AD767KP
AD767AD
AD767BD
AD767SDI
883B
AD767A
Chips
Package
Options*
Plastic DIP (N-24)
PLCC (P-28A)
Plastic DIP (N-24)
PLCC (P-28A)
Ceramic DIP (D-24A)
Ceramic DIP (D-24A)
Temperature
Range°C
Oto +70
Oto +70
Oto +70
Oto +70
-25to +85
-25to +85
Linearity
Error Max GainT.C.
Tmin-Tmax Maxppml"C
±ILSB
30
30
±ILSB
15
±I12LSB
15
±I12LSB
±ILSB
30
15
±I12LSB
Ceramic DIP (D-24A)
-55to + 125
±ILSB
30
N/A
-25to +85
±ILSB
30
'See Section 14 for package outline information.
DIGITAL-TO-ANALOG CONVERTERS 2-137
•
...
Analog Circuit Details
THE AD767 OFFERS TRVE 12·BIT PERFORMANCE
OVER THE FULL TEMPERATURE RANGE
LINEARITY ERROR: Analog Devices defines linearity error
as the maximum deviation of the actual, adjusted DAC output
from the ideal analog output (a straight line drawn from 0 to
F.S. - lLSB) for any bit combination. This is also referred to
as relative aa:uracy. The AD767 is laser trimmed to typically
maintain linearity errors at less than ± 1/8LSB for the K and B
versions and ± 112LSB for the J, A and,S versions. Linearity
over temperature is also held to ± 1/2LSB (KID) or ± lLSB
QlAlS).
MONOTONICITY: A DAC is said to be monotonic if the
output either increases or remains constant for increasing digital
inputs such that the output will always be a nondecreasing
function of input. All versions of the AD767 are monotonic over
their full operating temperature range.
DIFFERENTIAL NONLINEARITY: Monotonic behavior
requires that the differential linearity error be less than 1LSB
both at + 25"<: as well as over the temperature range of interest.
Differential nonlinearity is the measure of the varistion in analog
value, normalized to full scale, associated with a lLSB change
in digital input code. For example, for a 10 volt full·scale output,
a change of lLSB in digital input code should result in a 2.44mV
change in the analog output (ILSB= 10Vx 114096 = 2.44mV).
If in actual use, however, a ILSB change in the input code
results in a change of only 0.61mV (1/4LSB) in analog output,
the differential nonlinearity error would be -1.83mV, or
-3/4LSB.
GAIN ERROR: DAC gain error is a measure of the difference
between an ideal DAC and the actual device's output span. All
grades of the AD767 have a maximum gain error of 0.2% FS.
However, if this is not sufficient, the error can easily be adjusted
to zero (see Figures 2 and 3).
Gain and offset drift are minimized in the AD767 because of the
thermal tracking of the scaling resistors with other device components. Connections for various output voltage ranges are
shown in Table I.
r-_ _ _ _ _9"'1,9/V5k...
fl _ _ _--i
'iI
SUMMING
JUNCTION
FROM WEIGHTED
4
~1::'sL:r
AGND
10V SPAN
--4
~~~~~~-~-"'IN____-~-"'IN____
Figure 1. Output Amplifier Voltage Range Scaling Circuit
UNIPOLAR CONFIGURATION (Figure 2)
This confIguration will provide a unipolar 0 to + 10 volt output
range. In this mode, the bipolar offset terminal, Pin 4, should
be grounded if not used for trimming.
STEP I ... ZERO ADJUST
Tum all bits OFF and adjust zero trimmer RI, until the output
reads 0.000 volts ClLSB=2.44mV). In most cases this trim is
not needed, and Pin 4 should be connected to Pin S.
STEP II ... GAIN ADJUST
Tum all bits ON and adjust lOOn gain trimmer R2 until the
output is 9.9976 volts. (Full scale is adjusted to ILSB less than
nominal full scale of 10.000 volts.)
+Vcc
UNIPOLAR OFFSET ERROR: Unipolar offset error is a com·
bination of the offset errors of the voltage-mode DAC and the
output amplifier and is measured when the AD767 is configured
for unipolar outputs. It is present for all codes and is measured
with all "Os" in the DAC latches. This is easily adjustable to
zero when required.
BIPOLAR ZERO ERROR: Bipolar zero errors result from
errors produced by the DAC and output amplifier when the
AD767 is configured for bipolar output. Again, as with unipolar
offset and gain errors, this is easily adjusted to zero when
required.
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD767 may be connected
to produce bipolar output voltage ranges of ± 10, ± 5 or ± 2.sV
or unipolar output voltage ranges of 0 to + sV or 0 to + 10V.
Figure 2. 0 to
+ 10V Unipolar Voltage Output
Output
Range
Digital
Input Codes
Connect
Pin9to
Connect
Pinlto
Connect
Pin2to
Connect
Pin 4 to
±IOV
±SV
±2.SV
Oto + lOY
Oto +SV
Offset Binary
Offset Binary
Offset Binary
Straight Binary
Straight Binary
I
land2
2
I and 2
2
9
2and9
3
2and9
3
NC
I and 9
9
I and 9
9
6 (through son fIXed or lOOntrim resistor)
6 (through son fIXed or lOOntrim resistor)
6 (throUgh son fIXed or lOOntrim resistor)
S (or optional trim - See Figure 2)
S (or optional trim-See Figure 2)
Table I. Output Voltage Range Connections
2-138 DIGITAL-TO-ANALOG CONVERTERS
AD767
BIPOLAR CONFIGURATION (Figure 3)
This configuration will provide a bipolar output voltage from
- 5.000 to +4.9976 volts, with positive full scale occurring with
all bits ON (all Is).
STEP I ... OFFSET ADJUST
Turn OFF all bits. Adjust lOOn trimmer RI to give - 5.000
volts output.
STEP II ... GAIN ADJUST
Turn ON all bits. Adjust lOOn gain trimmer R2 to give a reading
of + 4.9976 volts.
STEP III ... BIPOLAR ZERO ADJUST (Optional)
In applications where an accurate zero output is required, set
the MSB ON, all other bits OFF, and readjust RI for zero volts
output.
GND
;;t;; 5V
If an external reference is used (lO.OOOV, for example), additional
trim range must be provided, since the internal reference has a
tolerance of ± 1%, and the AD767 full-scale and bipolar offset
..
are both trimmed with the internal reference. The gain and
offset trim resistors give about ± 0.25% adjustment range,
which is sufficient for the AD767 when used with the internal
reference.
iii
It is also possible to use external references other than 10 volts.
The recommended range of reference voltage is from + 8 to
+ 10.5 volts, which allows both 8.192V and 10.24V ranges to be
used. The AD767 is optimized for fixed-reference applications.
If the reference voltage is expected to vary over a wide range in
a particular application, a CMOS multiplying DAC is a better
choice.
Reduced values of reference voltage will also permit the ± 12
volt ± 5% power supply requirement to be relaxed to ± 12 volts
±IO%.
200F
Figure 3.
The AD767 reference output should be buffered with an external
op amp if it is required to supply more than O.lmA output
current. The reference is typically trimmed to ± 0.2%, then
tested and guaranteed to ± 1.0% max error. The temperature
coefficient is comparable to that of the full-scale TC for a particular
grade.
Bipolar Voltage Output
INTERNALlEXTERNAL REFERENCE USE
The AD767 has an internal low-noise buried Zener diode reference
which is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for use in a
high-speed DAC and will give long-term stability equal or superior
to the best discrete Zener reference diodes. The performance of
the AD767 is specified with the internal reference driving the
DAC since all trimming and testing (especially for full-scale
error and bipolar offset) is done in this confIgUration.
The internal reference has sufficient buffering to drive external
circuitry in addition to the reference currents required for the
DAC (typically O.5mA to Ref In and 1.0mA to Bipolar Offset).
A minimum of O.lmA is available for driving external loads.
It is not recommended that the AD767 be used with external
feedback resistors to modify the scale factor. The internal resistors
are trimmed to ratio-match and temperature-track the other
resistors on the chip, even though their absolute tolerances are
± 20%, and absolute temperature coefficients are approximately
- 50ppml°C. If external resistors are used, a wide trim range
(±20%) will be needed and temperature drift will be increased
to reflect the mismatch between the temperature coefficients of
the internal and external resistors.
Small resistors may be added to the feedback resistors in order
to accomplish small modifications in the scaling. For example, if
a 1O.24V full scale is desired, a 140n 1% low-TC metal-film
resistor can be added in series with the internal (nominal) 5k
feedback resistor, and the gain trim potentiometer (between
Pins 6 and 7) should be increased to 200n. In the bipolar mode,
increase the value of the bipolar offset trim potentiometer also
to 200n.
+Vcc
61.9U
OUTPUT
GND
Figure 4. Using the AD767 with the AD588 High Precision,Reference
DIGITAL-TO-ANALOG CONVERTERS 2-139
USING THE AD767 WITH THE ADS88 HIGH PRECISION
Figures Sb and Sc show the settling time for the transition from
VOLTAGE REFERENCE
The AD767 is specified for gain.drift from ISppmI"C to 3OppmI"C
(depending on grade) using its internal 10 volt reference. Since
the internal refeteD.ce contributes the majority of this drift, an
external high-precision voltage reference will greatly improve
performance over temperature. As shown in Figure 4, the 10
volt output from the ADS88 is used as the reference. With a
1.5ppmI"C outpUt voltage drift the ADS88 contributes less than
1/2LSB gain drift when used with the AD767 over the industrial
temperature range. Using this combination may result in apparent
increases in full-scale error due to the differences between the
internal reference by which the device is laser trimmed and the
external reference with which the device is actually applied. The
AD767 internal refeteD.ce is specified to be 10 volts ± 100mV
whereas the ADS88 is specified as 10 volts ± 1mV. This may
result in up to 101mV of apparent full-scale error beyond the
±2SmV specified AD767 gain error. The soon potentiometer
in series with the reference input allows adequate trim range to
null this error.
all bits on to all bits off. Note that the settling time to ± 1I2LSB
for the lOY step is improved from 2.4 microseconds to 1.6
microseconds by the addition of the 20pF capacitor.
D81'-OBO
I +
C=
t i ---1-'-- t-
-t -+
I
j
iiiiiiiiiiiiiiUiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
Figure 5b. Fine-Scale Settling, CF=OpF
GROUNDING RULES
The AD767 brings out separate analog and power grounds to
allow optimum connections for low noise and high-speed per-
08'1-DBO
formance. These grounds should be tied together at one point,
usually the device power ground. The separate ground returns
are provided to minimize current flow in low-level signal paths.
The analog ground at Pin S is the ground point for the output
amplifier and is thus the "high quality" ground for the AD767;
it should be connected directly to the analog reference point of
the system. The power ground at Pin 12 can be connected to
the most convenient ground point; analog power return is preferred. If power ground contains high frequency noise beyond
200mV, this noise may feed through the converter, thUs some
caution will be required in applying these grounds.
It is also important to apply decoupling capacitors properly on
the power supplies for the AD767. The correct method for
decoupling is to connect a capacitor from each power supply pin
of the AD767 to the analog ground pin of the AD767. Any load
driven by the output amplifier should also be referred to the
analog ground pin.
VouT.1LSB/DIV
~---+--
-
, ; , 1 ,I I
!
,I
- 11-'-~--T~+--
,
I
be optimized by adding a small (2OpF) capacitor across the
feedback resistor. Figure S shows the improvement in both
1arge-signal and small-signal sett1ing for the 10V range. In Figure
Sa, the top trace shows the data inputs (DBll-DBO tied together),
the second trace shows the CS pulse, and the lower two traces
show the analog outputs for Cp = 0 and 20pF respectively.
I
_______
iiiii_ _iiioi
150
V
ouT
.5V/DIV
Figure 5c. Fine-Scale Settling, CF=20pF
Figures Sd and Se show the settling time for the transition from
all bits off to all bits on. The improvement in settling time
gained by adding Cc = 20pF is similar.
:01-
1
I
! 1_ -
~
0811-080
~+
IL
I-+- r
t. ~
I
OPl1MlZlNG SETTLING TIME
The dynamic performance of the AD767's output amplifier can
~- ~+-
:
I
±
VOUT• 1LSB/DIV
Ct..
~-I- T I J/_ ___ .
~,.
5V
1
I
~
,I
I
I.l-
,
VoUT,SV/DIV
,-1
I
Figure 5d. Fine-Scale Settling, CF=OpF
>2",~
DB11-DBD
-
I
-
-
I I
I
08,,-080
! I
,~,_L1VOUT. 10V/DIV, CF=20pF
I
~
+
I
I
_
I
VoUT.1LSB/DIV
VOUT, 10V/DIV, CF=DpF
VolJT .5V/DIV
Figure 5a. Large Scale Settling
2-140 DIGITAL- TO-ANALOG CONVERTERS
Figure 5e.
Fine~Scale
Settling, CF=20pF
Applications - AD767
DIGITAL INPUT CONSIDEIlA'DONS
The threshold of the diaital input circuitry is set at 1.4 volts
and does not c:hanae with supply voltage. Thus the AD767
diaital interface may be driven with any of the popular types of
5 volt logic:.
A good eDgineering practice is to COIIDI:Ct unused inputs to
power ground to improve noise immunity. UIlCOllllCCted data
and control inputs will 60at to logic 0 if left open.
The low diaital input current of the AD767 eliminates the need
for bufferldrivers required by many monolithic conveners using
bipolat technology. A single low-power Schottky gate, for example,
will drive several AD767s when connected to a common bus.
INPUT CODING
The AD767 uses positive-true binary input coding. Logic "I" is
represented by an input voltage greater than 2.0V, and logic:
"0" is defined as an input Voltage less than O.SV.
Unipolat coding is straight binary, where all zeroes (OOIIW on
the data inputs yields a zero analog output and all ones (FFFa)
yields an analog output lLSB below full scale.
Bipolat coding is offset binary, where an input code of ~
yields a minus full-scale output, an input of FFFH yields an
output lLSB below positive full scale, and zero occurs for an
input code with only the MSB on (8OOa).
The AD767 can be used with twos complement input coding if
an inverter is used on the MSB (DBll).
MICROPROCESSOR INTERFACE
The AD767, with its 40ns minimum CS pulse width, may be
easily interfaced to any of today's high-speed microprocessors.
The 12-bit single buffered input register will accept 12-bit parallel
data from processors such as the 68000, 8OS6, TMS320 series,
and the Analog Devices ADSP-2100. Several illustrative examples
follow.
68000 - AD767 INTERFACE
Figure 6 illustrates the AD767 interface to a 68000 microprocessor.
An active low decoded address is OR'ed with the processor's
RiW signal to provide CS and latch data into the AD767. Later
in the bus cycle the processor issues the upper (UDS) and lower
(LDS) data strobes which are gated with the decoded address to
provide DTACK and terminate the bus cycle. As shown, this
interface will suppon a 12.SMHz 68000 system.
A1-A23
68000
RiW
ADDRESS BUS
AD767*
I---====--W
LDS L.----S"_.
UDS
CTACK
r---"'L--"
t--~,--J..---.l
00-015
DATA BUS
V i i R I - - - - - - -....-.....
AD767*
8086
ALE
ADO-AD15
t-_ _ _ _ _ _ _ _ _-,A DBO-DBll
-LINEAR CIRcurrRV
OMITTED FOR CLARITY
Figure 7. 8086 - AD767 Interface
TMS32010 - AD767 INTERFACE
The high-speed diaital interface of the AD767 facilitates its use
with the TMS32010 microprocessor at speeds up to 20MHz. In
the three multiplexed LSBs of the address bus, PAl - PAO are
decoded as a pon address and OR'ed with the low write enable
to generate CS for the DAC. A simple OUT xx,y instruction
will output the data word stored in memory location xx to any
one of eight port locations y.
DBD-DB"
080-0811
DATA BUS
-LINEAR CIRCUITRY
OMITTED FOR CLARITY
Figure 6. 68000 - AD767 Interface
TMS32010
A2-AO
PAZ-PAD
AD767'
PORT
ADDRESS
DECODER
=ru-
1/086 - AD767 INTERFACE
Interfacing the AD767 to the S086 16-bit microprocessor requires
a minimal amount of atema1 components. A 10MHz 8086, for
WE
example, generates a 16Sns low write pulae which may be gated
with a decoded address to provide CS for the AD767. As WR
returns high valid data is latched into the DAC. See Figure 7.
Figure 8. TMS32010 - AD767 Interface
174lS1381
es
DIGITAL-TO-ANALOG CONVERTERS 2-141
•
TMS3ZOZO - AD767 INTERFACE
Interfacing the AD767 to the TMS32020 microprocessor is
easily achieved by usiDg the TMS32020 110 port capability. The
IS sigDal distiJJguisbes the 110 address space from the local
programIdata memory space and is used. to CDllblc a 74LS138
decoder. The dccodedport address is then gated with the RiW
and STRB signals to provide the AD767 <:S.
GI
Y7
is
li2A
V6
A3
GoB
The LOW dcc:oded address is also gated with the Q output of a
D flip-flop to hold DMACK (Data Memory Aclmowledgc)
LOW. This forces the processor into a wait state and e:&tcnds
the AD767 CS by 1 clock cycle. The rising edge of CLKOUT
latches Q HIGH bringing DMACK HIGH. The cycle is now
complete.
+5V
TMS32020
At the beginning of the data memory access cycle the proc:cssor
provides a 14-bit address on the DMA bus. The DMS sigDal is
then asserted CDllbling a LOW address decode. Valid data is
now placed on the data bus and DMWR is issued. DMWR is
OR'ed with the LOW address decode to generate the AD767
CS.
Y5
V4
174LS138)
TMS320ClS - AD767 INTERFACE
Figure II illustrates the AD767 interface to a TMS320C2S
digital sigDal processor. Due to the high-speed capability of the
processor (40MHz), a single wait state is required and is easily
generated usiDg MSC. A 20MHz TMS320C2S however, docs
not require wait states and should be interfaced usiDg the circuit
shown in Figure 9.
Y3
C
A2
V2
AI
VI
VO
A
AO
RM
STRB
READY
DBO-DB"
015- 0 D
+5V
·UNEAR CIRCUITRY
OMmED FOR CLARITY
TMS320C25
is
Figure 9. TMS32020 - AD767 Interface
ADSP·2100 - AD767 INTERFACE
The ADSP-2100 single chip DSP processor may be interfaced to
the AD767 as shown in Figure 10. With a clock frequency of
32MHz, and instruction execution in a single 12Sns cycle, the
processor will support the AD767 interface with a single wait
state.
A3
A2
AI
AO
AD767*
MN~----;-~
S'iiiil----LJ
READY
____~
I---...('[~-------'
MSc 1 - - - - - - - - - '
DBO-DBl1
DMAuD
ADDRESS BUS
·LlNEAR CIRCUITRY
OMITTED FOR CLARITY
Figure 11. TMS320C25 - AD767 Interface
DMACK
AD767*
ADSP·2100
CLKOUT
I----i)
DM0 1l;_o
DATA BUS
-LINEAR CIRCUITRY
OMITTED FOR CLARITY
Figure 10. ADSP-2100 - AD767 Interface
2-142 DIGITAL-TO-ANALOG CONVERTERS
~ANALOG
WDEVICES
FEATURES
18-Bit Resolution
Low Nonlinearity
Differential: :!: 1/2LSB max
Integral: :!: 1/2LSB max
High Stability
Differential TC: :!: 1ppml"C max
Integral TC: :!: 1/2ppmI"C max
Gain TC (with Reference): :!:4ppmI"C max
Fast Settling
Full Scale: 4O.,.s to :!:0.00019%
LSB: 6.,.s to :!:0.00019%
Small Hermetic 32-Lead Triple DIP Package
Low Cost
High Accuracy, l8-Bit
Digital-to-Analog Converter
ADl139
I
AD1l39 FUNCTIONAL BLOCK DIAGRAM
APPLICAnONS
Automatic Test Equipment
Scientific Instrumentation
Beam Positioners
Digital Audio
GENERAL DESCRIPTION
The ADI139 is the first DAC offering 18-bit resolution (l part
in 262,144) and true IS-bit accuracy in a component size hybrid
package. A proprietary bit switching technique provides high
accuracy, speed and stability without compromising small size
or low cost.
The ADI139 is a complete DAC with precision internal reference,
latched data inputs and a quality output voltage amplifier. The
analog output voltage ranges are pin programmable to + 5V,
+ IOV, ± 5V and :!: 10V. Current output is also provided for
use with external amplifiers. The internal precision -IOV reference has a low ± 3ppml"C maximum temperature coefficient
and is available for ratiometric applications.
The ADI139K is a tl"Ue 18-bit accurate DAC with:!: 1I2LSB
maximum differential and integral nonlinearity. The differential
and integral nonlinearity temperature stability is guaranteed at
± Ippm/°C maximum and ± 1I2ppm/"C maximum, respectively.
The ADI139 settles to within ± 1I2LSB at 18 bits (±0.00019%)
in 4Of.Ls for a full-scale step (IOV). The glitch energy is a low
400mV x 500ns for a major carry, and wideband output noise is
only 15f.LV.
The ADI139 operates from:!: 15V dc and + 5V dc power supplies.
Digital inputs are 5V CMOS compatible with binary·input
coding for unipolar output ranges and offset binary coding for
bipolar ranges.
PRODUCT HIGHLIGHTS
I. Eighteen-bit resolution with ± 1I2LSB maximum differential
and integral nonlinearity in a hermetic 32-lead triple DIP
package.
2. Complete DAC with internal reference, stable low-noise
output amplifier, latched DAC inputs, reference output and
internal application resistors for programmable output voltage
ranges.
3. Temperature compensated internal precision reference with
±O.I% maximum initial accuracy and ±3ppm/oC maximum
tempco.
4. Four pin programmable output voltage ranges ( + 5V, + 10V,
± 5V, ± lOY) and current output available ( - IrnA,
±0.5rnA).
5. The 18-bit parallel input latch assists in microprocessor
interface.
6. Accurate measurements of the DAC's output are unusually
simple since the ADI139 does not suffer from code dependent
ground current errors.
7. True analog output remote sense capability.
DIGITAL-TO-ANALOG CONVERTERS 2-143
•
SPECIFICATIONS
(IJpicaI @
+2ft and rabid sqJpIies unless o\b8IWise specified)
4011391
RESOLUTION
ACCURACY
Differential Nonlinearity
InresraI Nonlinearity
Monotonicity (18 Bits)
InitialErrors l
Unipolar Gain Error
BipolarGain Error
<>met Error
Bipolar <>met Error
STABIUTY(ppm FSR /"C)
Differential Nonlinearity'
InresraI Nonlinearity'
Gain (Including VREF)
Offset
Unipolar Mode
Bipolar Mode
STABIUTY (Long Term, ppm FSR'/looohour)
Differential Nonlinearity'
Gain (Including V REF)
<>met
BipolarOffset
Reference Ontput Voltage
WARMUP TIME (MINIMUM)
REFERENCE VOLTAGE (V REF)
OutputVoltage(@5mAmax)
Noise(BW = O.I-IOHz)
Noise(BW = 100kHz)
Tempco
DYNAMIC PERFORMANCE
Setding Time to 1/2LSB (@ 18 Bits)'
Voltage
Unipolar(IOV Step)
Bipolar (20V Step)
Unipolar(LSB Step)
Bipolar (LSB Step)
Slew Rate
Current6
Full-Stale Step
LSBStep
Glitch Energy (Major Catty
(ill 20MHz Bandwidth O-to-IOV Range)
OUTLINE DIMENSIONS
401139K
Dimensions shown in iru:hes 8J!d (mm).
18 Bits
±ILSBmax
±1/2LSBmax
(= ± 0.00038% max)
(= ±O.oool9%max)
±ILSBmax
(= ± 0.00038%max)
Guaranteed
±0.01%
±0.02%
±O.O\%
±0.01%
±lmax
±O.Smax
±4max
±II2LSBmax
·
(= ±O.oool9%max)
015013.8111
..... 15...'
fbSEAnNGPI.ANE
j...... •.•t51038'
I
0 03510.891
1
,..--------,
• DOT INDICATES
PIN t POSITION
·
±O.Styp, ±lmax
±lmax
±lmax
±0.5
±lS
±I
±2
+15
ISmiDutes
-IOV(±O.I%max)
20lJ.Vpk-pk
50IJ.Vrms
3ppm/"Cmax
·
10IJ.Vpk-pk
WARNING!
0
~~DFVICE
CAUTION, OBSERVE PROPER PLUG-IN POLARITY TO
PREVENT DAMAGE TO CONVERTER
PIN DESIGNATIONS
400mV (500ns Duratinn)
DIGITAL INPUTS (5V CMOS Compotible)
VII.
V1H
Unipolar Code
Bipolar Code
ANALOG OUTPUT
Current"
Voltage(PinProgrammable)
Noiae (Includes VREF)
BW = O.I-IOHz(IJ.Vpk-pk)
BW = lOOkHz(Unipolar)
BW = 100kHz (Bipolar)
VOLTAGECOMPUANCE
,",0.8V
"3.5V
Binary (BIN)
Offset Binary (OBN)
-lmA, ±O.SmA
+SV,+10V,±5V,±10V
2xFSR
15IJ.Vrms
4SIJ.Vrms
IxFSR
±IOmV
Source Resistance
Unipolar
Bipolar
Source Capacitance
POWER SUPPLY REQUIREMENTS
+5Vdc(±S%)
± ISVdc(±S%)
POWER SUPPLY REJECTION
(:t15Vdc)
Gain
Offset
Reference OntpUt
(+SVdc)
Differential Nonlinearity
TEMPERATURE RANGE
Operatins (Rated Performance)
Storaae
3.3k!1
2.85kn
10pF
lOOIJ.A
+ 2SmA, - 30mA
±2.SppmI%
±0.3ppm/%
:t2.5ppm1%
+O.ISppm/%
PIN DESCRIPTION
PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
SIGNALGND
BIPOLAR OFFSET
lOUT
AMPIN
20VSPAN
10VSPAN
AMP OUT
DB17 (MSB)
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
22
21
20
19
18
17
NOTES
_.AIoo, .......
'ScoF..... 7r..1yPicoI ........... u...;,yocolOlily ...
BURN-1N8OCIioII0IIplp6forcaudoa.......
tid ni.bycbeUlll'.
·F..... '....,.....IyPicoILSB ... fuII«oIo ........ timelD_112LSB
at 12-10 ll-bit resolatioDl.
'Cuneat~Opaodoa._r..iaputlD .............
....... _ _ .
S~_ID
2-144 DIGITAL-TO-ANALOG CONVERTERS
28
27
26
25
24
23
GAIN TRIM
REF OUT
-15V
+15V
+5V
POWERGND
WR
DBO(LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
*SpccifatioalllPlCuADll39).
Ilnitial Enonare adjusIabIe to3Cf'O"ria eucrul poteIdiameten(.ee F'1pI'C 1).
2FSR JDC8DI FuIJ-ScaIc Range.
'T_SIabilltyofliDarityia...-... I%"QL.LowIn ..................
M.IL-STI)..l05.
010 +7O"C
- 4O"C to + 85"<:
31
30
29
_af.
OIIQIIiIier.
AD1139
OFFSET & GAIN CALIBRATION
Initial offset and gain errors can be adjusted to zero by potentiometers as shown in Figure I. The offset adjust range is plus
0.03% to minus 0.02% of full scale range (wiper of potentiometer
to REF OUT equals plus 0.03%). The gain adjust range is plus
0.06% to minus 0.08% of full scale range (wiper to REF OUT
equals plus 0.06%). Measurement instruments used should be
capable of resolving 1j1.V at plus full scale for the chosen output
range and within Ij1.V of zero.
Procedure:
UNIPOLAR MODE
1. Apply a digital input of all "Os."
2. Adjust the offset potentiometer until a O.OOOOOOV output is
obtained.
3. Apply a digital input of all "Is."
4. Adjust the gain potentiometer until plus full-scale output is
obtained (see Table I for exact value).
AD1139 Functional Block Diagram
ANALOG OUTPUT RANGE
The AD 1139 is pin programmable to provide a variety of analog
outputs, either current or voltage. A unipolar output current of
o to - lmA is available at Pin 3 and can be offset by O.SmA
(connect Pin 2 to Pin 3) for a biolar output of ±O.SmA. Output
voltage ranges (+ SV, + lOY, ± SV and ± lOY) are available at
Pin 7 by connecting the current output (Pin 3) to the amplifier
input (Pin 4) and the appropriate internal feedback resistors to
the amplifier output (Pin 7) as shown in Figure I.
BIPOLAR MODE
1. Apply a digital input of 100 ..... 000.
2. Adjust the offset potentiometer until a O.OOOOOOV output is
obtained.
3. Apply a digital input of all "Is."
4. Adjust the gain potentiometer until plus full-scale output is
obtained (see Table I for exact value).
CodeOOO •••. OO
Unipolar + SV
+lOV
O.OOOOOOV
O.OOOOOOV
Bipolar ±SV
±lOV
Code 100 •••• 00
O.OOOOOOV
O.OOOOOOV
+lSV.,....;iV.-..-.I=".;;:;;;:..........- - - - - - - ,
Code Ill ••• 11
+4.999981V
+9.999962V
Code III •••• 11
+4.999962V
+9.999924V
CodeOOO ••••00
- S.OOOOOOV
- IO.OOOOOOV
Table I. Full-Scale and Offset Calibration Voltages
I}-.....- - . :
,~---t-<>
-,!IV
'@----r.-jLo+1SY
~~-+-t-o
••v
Symbol
Parameter
Requirement
tDS
Data Setup Time
Data Hold Time
Write Pulse Width
160nsmin
120nsmin
200nsmin
tDH
tVIR
Table II. Timing Requirements
NOTES
ALL RESISTORS AREMETAlfLM RN55 OR EClUIVALENT.
ALLCAPACITOASAA£POLARtZEOTANTALUM.
I r ,J=::
r-t
.1I . .,
.....
POWER
GROUND
I.
L.. -
AMPIN
:oJ
JOY
TIMING DIAGRAM & LATCH. CONTROL
Timing requirements for the ADI139 are shown in Table II.
The timing diagram is shown in Figure 2. The WRite line controls
an 18-bit wide data input latch. This latch is transparent when
the WRite line is LOW, allowing all bits to be accessed directly.
When the WRite line is activated HIGH, the data present at the
inputs is held in the latch and the appropriate analog voltage is
seen at the output.
VOLTAGE
OUTPUT
DBO-DB17
~
Wii\
0AU.OTHER ... CONNECTIOfISARE THE SAME. AS SHOWN
DATAVAUD
x==
~'''--1 .... 1==
/
~,-::::::::j
FOIIIUNIPOlMOTO + lOYOI'EItAT1ON.
Figure 1. Output Voltage and Trim Configuration
Figure 2. AD1139 Timing Diagram
DIGITAL-TO-ANALOG CONVERTERS 2-145
•
GROUNDING & GUARDING
The current from measurement ground (Pin 1) is small and
independent of the digital input code to the DAC. This gready
simplifies making error free analog measurements. Connect this
high quality ground to the .system's or application's high quality
ground. Connect the DAC's power ground (Pin 27) to the sy~em
return, also connect the system's high quality ground to the
system return. It is most important thot the measurement ground
(Pin 1) and j)IYWer ground (Pin 27) be connected externally for
propeT
circuit operation.
The current output pin (lour, Pin 3) is s.ensitive to external
noise sources, such as digital input lines. This pin and any
components connected to this pin should be surrounded by a
grounded guard as shown in Figure 3.
PIN 1
~IIPlN2
~
BPO
10
PlN4
AMP IN
When used as a reference DAC to test the integral and-differential
linearity of 14- and l6-bit DACs, the AD1139 provides a measurement capability with just IIl6LSB of uncertainty at 14 bits.
Gain and offset errors of the device-under-test (D. U. T.) may be
accounted for in software. Once zeroed, the integral linearity
error can be measured as the difference between the reference
DAC CAD1139) and the D.U.T. as seen at the digital voltmeter.
The differential linearity error is then determined by incrementing
or decrementing the D. U. T. digital input by lLSB, and comparing
the new output at the DVM with the previous output. The
difference between these two measurements should be exacdy
one ideal LSB. The amount of disagreement from one ideal
LSB is the differential linearity error.
~
PlNl
RATIOMETRIC DAC TESTING APPLICATION
The AD1139's highly stable reference output can be conveniendy
used in the testing of other high resolution DACs. Figure 5
describes how the REF OUT (Pin 31) is used as the external
reference input to a device-under-test. The gain of the deviceunder-test will now accurately track the AD 1139's gain and
eliminate reference contribution to gain error.
INTERNALAMPLIAER
UUPot.AA RANGEl
EXTERNAlAMPLIRER
IUNIPOlARFlANQE)
Figure 3. Guarding Recommendations
REMOTE SENSE APPLICATION
The ADl139's remote sense capability allows driving heavy
loads or long cables without the usual, accompanying gain errors.
By sensing at the load, as described in Figure 4, the load current
will pass through the amplifier's output and the power ground,
but not through the sense lines. The potential gain errors that
would be induced by this load current are therefore minimized.
The load should not exceed -± lOrnA or 2 nanofarads to insure
proper operation of the AD1139's internal output amplifier.
Figure 4. Remote Sensing
Figure 5. Ratiometric DAC Testing
mM* PC INTERFACE
Figure 6 illustrates a typical IBM personal computer interface
which uses three 8-bit external latches and two decoder chips.
The three HCT374 latches are connected to the data bus (DO
through D7). The HCT138 decoder chip decodes the address
bus and enables each latch, including the AD1139's internal
DAC latch, to see the appropriate digital word. The HCT688
chip and the HCT138 decoder defme the 110 address space
where the four latches will reside. In the Figure 6 example, they
reside in the address space as shown in Table III.
110 Address
Selected Latch
Data Bits
380H
381H
382H
383H
Low Byte
Mid Byte
High Byte
AD1139 Latch
DBO-DB7
DBS-DB15
DBI6,DBI7
DBO-DB17
Table III. IBM Interface Address Locations
*IBM is a trademark of International Business Machines Corp.
2-146 DIGITAL-TO-ANALOG CONVERTERS
ADl139
1_ CONNECT TO
CONNECTTOTHE
•
PC'S +sVSUPPLy,-1
BUS
PINN
D7
(A21
D6
IA3)
DS
(A4)
D4
lAS)
D3
(A6)
D2
(A7)
Dl
(AB)
DO
IA9)
THEADl139'S
+sVSUPPLY'
LOW
BYTE
4
20
2
5
7
•
8
13
14
17
18
11
+SV
WR
(B13)
AO
(A31)
Al
(A30)
I8
16
I
15
I
14
13
12
I
+SV
(A28)
(A27)
A5
(A26)
A6
(A2s)
A7
(A24)
A8
(A23)
A9
(A22)
Al0
(A21)
AEN
7
13 HCT374
12
14
15
17
16
18
19
11
10
2
4
DBn
DB12
DBll
DB10
DB9
17 DB8
5
16
6
3
HCT6BB
5
13
9
13
HCT374 12
14
15
17
11 DB14
2
4
11
6
18
19
A3
10 DBls
4
I
4
A4
AD1139
17
18
18
10
11
IAll)
NOTE
I
'THE PC'S + 5V de LOGIC SUPPUES SHOULD BE KEPT SEPARATE
FROMTHEADl139 +SVdeSUPPLY. TO KEEP LOGIC
INDUCED NOISETO A MINIMUM.
Figure 6. AD1139 to IBM PC Compatible Interface
LONG-TERM STABILITY VS. TEMPERATURE
Adjusting the linearity of any DAC after it is installed in the
application is often difficult or impossible. It is preferable to
maintain some specified accuracy over the useful working life of
the product (commonly 5 to 10 years). Stable linearitY performance
over time can, therefore, be a very important parameter for the
DAC.
Accelerated testing to determine the expected linearity stability
over time can be accomplished by two different methods. Linearity
is first measured at + 25°C. The DAC is then operated at a
fIXed elevated temperature for an extended period of time. The
DAC is then retested at + 25OC, and the change in linearity
error vs. time is calculated. The ARRHENIUS EQUATION
(used in reliability calculations) can be used to determine what
the acceleration factor is from + 25°C to the elevated test tem-
perature. Knowing the acceleration factor and the linearity error
vs. time at the elevated temperature, one could calculate the
expected long-term stability of linearity at nominal
temperatures.
A second test method determines how long it will take for the
linearity to shift by a specific error band (we chose ± 2ppm for
our example) at any specified temperature. The first step is to
measure the linearity at a moderately elevated temperature (e.g.,
+ 85°C) and then monitor how long it takes at this temperature
to reach the error band limit. The second step is to perform the
same test at a much higher elevated temperature (e.g., + 125OC).
The two resulting time vs. temperature points are then ploned
on semilog paper. A line drawn through the two points allows
extrapolation to the length of time expected to reach the error
band ( ± 2ppm) at other temperatures, including + 25°C.
DIGITAL-TO-ANALOG CONVERTERS 2-147
Figure 7 shows how long it would take for the ADl139's 'linearity
to drift ± 2ppm (1I2LSB) at any operating temperature. The
uppermost plot shows stability under storage conditions (no
power).. and the lower plot shows the ADl139's operating stability
(under power). The operating vs. storage difference is due to the
10"C temperature rise when the ADl139 is powered.
+16V
-1&V
'M
)-""--""-""",,,,,--+---0
300.000
MEASUREMENT
GROUND
134 YEARSI
'OOK
87,600
110 YEARSI
43,800
15 YEARS
'OK
8,760
UVEAR I
"'"
~
Figure 8. External Amplifier for High Speed
~ STORAGEINOPOWERAPPLIEDI
'K
720
Output Voltage Range
It MONTH I
'\
..
""'
, - -
OPERATING
Noise Gain
Oto +5V
Oto +lOV
±5V
±IOV
I'\.
2
3
4
7
0
Table IV. Noise Gain vs. Output Voltage Range
'\ '\
10
20
30
40
50
60
70
80
90
100
"-
110
TEMPERATURE- degrees
EXPECTED TIME REQUIRED TO
"'
120
130
PRODUCE A :!: 2ppm LINEARITY
SHIFTVS. TEST TEMPERATURE
NOTE: MAX OPERATING TEMPERATURE IS +70"<:
SETTLING TIME
The LSB step and full-scale step typical settling times, to within
± 1I2LSB at 18 bits, are shown in the Specification Table.
Figure 9 graphically presents the typical settling times to within
± 1I2LSB at resolutions from 12 to 18 bits.
Figure 7. Nonlinearity vs. TimelTemperature
,
ERROR
12lS8
ERAOR
BAND
BURN-IN
All ADI139s undergo a 168 hour, powered burn-in @12SoC,
prior to laser trimming. This burn-in produces the optimum
stability for the resistor network and eliminates infancy defects.
As shown in Figure 7, exposure to elevated temperatures produces
an acceleration of the normal aging process. Preconditioninglburnin employed by the user will lead to premature linearity shifts
outside of the initial guaranteed specifications. The ADI warranty
will not cover DACs that exhibit this type of forced premature
specification degradation.
EXTERNAL AMPLIFIER FOR HIGH SPEED OR HIGH
OUTPUT CURRENT
The ADI139's internal output amplifier is optimized for very
low noise, dc stable applications with moderate settling time.
Applications requiring higher speed or more output current can
use an external amplifier, such as shown in Figure 8. The AD711
settles to within 16 bits in only 6",s for a unipolar full scale
step. Other amplifiers may be chosen for differing tradeoffs.
The noise gain seen by the output amplifier, depends on the
output voltage range selected (see Table IV). The amplifier
selected must be stable at the noise gain corresponding to the
output range.
2-148 DIGITAL-TO-ANALOG CONVERTERS
LSBSTEPFOR
MAJOR CARRY'
.
i
~
H
.r-
IFUU-SCALE
RANGESTEP-
.
;
+,
+5
;\
I
+±':
~10
,
28
'OOppm
\
\\
" \
,
\ \
",
t
:3~ 'Oppm
\1
\ \
'..
i
~
"c.
\.,\
'l\
I
+10'±1j
,ppm
\
\' 1\
.
'38
,
,
..
58
,
'78
'88
""1
,,...
10,..5
SETTliNG nME-+
NOTE
'LSB senLiNG TIMES SHOWN WIU ONLY BE ACMIEVEDWITH
CLAMPING DIODES FROM THE DAC'SAMPIN (pINt) TO
GROUND PER FIGURE 1.
Figure 9. Settling Time vs. Resolution
100,...
~ANALOG
WDEVICES
FEATURES
16-Bit Resolution
Low Nonlinearity
Differential: ±3/4LSB max
Integral: ± 1LSB max
Relative Accuracv: ± 0.003% max
Fast Full-Scale Settling: 6"s to ± 1/2LSB
High Stabilitv
Monotonic to 16 Bits: +1S"C to +3S"C
Offset TC: ±0.1ppml"C max
Gain TC: ±O.1ppml"C max
Double Buffered Digital Input
Parallel and Serial Data Input
Single + SV SupplV Operation
Low Power Consumption: 2.SmW
Small Size: 44-Pad Plastic LLCC
Low Cost
APPLICATIONS
Automatic Test Equipment
Scientific Instrumentation
Machine Control
Digital Audio
Robotics
GENERAL DESCRIPTION
The AD1145 is a double-buffered, l6-bit resolution DAC with
± 3/4LSB maximum differential and ± lLSB maximum integral
nonlinearity. Size comparable to the smallest monolithic DACs
and high reliability are owed to its proprietary two-chip construction. A custom CMOS integrated circuit and laser-trimmed,
thin-film resistor network provide 16-bit accuracy, excellent
temperature stability and low power consumption.
Low Cost l6-Bit
Digital-to-Analog Converter
ADl145 I
AD1l45 FUNCTIONAL BLOCK DIAGRAM
··A.~
AD1145
DO"
08'- -
IMS81
so
·V..., = PINS " ",H and II.
"AGM) = PINS
28 end 40
8,'"
-
-
D80
,'"",
~
A clear line allows resetting the DAC output to zero volts on
command. Power-up automatically resets the DAC output to
zero volts following a power failure as required in machine
control applications. All outputs may be simultaneously updated
in a multiple DAC system.
Internal application resistors allow a wide variety of pin programmable output voltage ranges (+ 5V, + IOV, - SV, -IOV,
± SV and ± lOY). The ADl145 may be operated off of a single
+ 5V reference/supply, consuming only 2.SmW of power.
A 5 volt full-scale output step settles to within ± 1I2LSB in just
6 microseconds. Wideband noise (100kHz) is only 50 microvolts
peak-to-peak.
The ADl145 offers an unparalleled combination of low cost,
high accuracy, small size and convenient design-in features. The
AD1l4S directly interfaces with 8- and 16-bit microprocessors
or can be used in stand-alone applications. Digital input coding
is binary for unipolar output and offset binary or twos complement
for bipolar output. Data can be written to the DAC in either a
parallel or a serial mode. Serial data readback is available for
error checking.
DIGITAL-TO-ANALOG CONVERTERS 2-149
•
SPECIFICATIONS
(typical @+25OC. rated supplies unless otherwise specified)
Model
AD1145A1AG
RESOLU.T10N
16 Bits
ACCURACY
Differential Nonlinearity, max
Integral Nonlinearity, maxi
AD1145BJBG
Relative AccuraCy, max
±ILSB(- ±O.OOIS%)
±ILSB(- ±0.0015%)
±0.003%
Initial Errors
Offset Error
±1I4LSB
Gain Error
w/o "Int. Application Resistors
w/lnt. Application Resistors
*
re
.L~
~·~1.
±1I4LSB
+0.1%
@ +2S
+ ISto +3S
-4010 +8S
-4Oto + 100
Oto+70
-40 to + 100
±O.lppmI"C
±O.lppmrc
STABILITY LONG TERM
Differential Nonlinearity
Offset
DYNAMIC PERFORMANCE
SV Full-Scale Settling Time (to ± 1/2LSB)
LSB Settling Time
Glitch Energy (Major Carry BW - 20MHz)
Total Harmonic Distortion
«v
ANALOG OUTPUT
Nominal·Voltage Output Range
Voltage Ranges (w/Externai Amplifier)'
T Ei
r.~ ~
~
8
Source Capacitance
Output Impedance
POWER SUPPLY REQUIREMENTS (Voo)
w/CMOSDigitaiInputs(VIN - VDoorGND)
wfI'TL Digital Inputs cYlN - 2.4VorO.SV)
Range for Multiplying'
Total Power (C" + SV (Including Reference)
w/CMOS Digital Inputs
wfI'TL Digital Inputs
POWER SUPPLY SENSITIVITY
Differential Nonlinearity
Offset
Gain
EXTERNAL REFERENCE INPUT
Nominal
Range 3
Input Resistance
VIH
Parallel & Serial (with Serial Readhack)
Unipolar Code
BipolarCodes
TEMPERATURE RANGE
Rated Performance
Storage
PACKAGE
Surface Mount Device(ADlI4SA, B)
PACKAGE
c::
~~
~
....
:::11.211
~
1-;;LI3.2J
..1."x
44·PIN GRID ARRAY*
6".
3fLS
SOOmV x
-98<1B
~1~~
2".
I
I
I
USfU51
d.':,
I
+SV
-SV,-lOV,+SV,+10V,
4STAND·OFFPlNS
S"Vpk-pk
SO"Vpk-pk
18pF
Sill
+ SV dc (u>lO"A
+SVdc(u,3mA
VR,RF
-O.3:!!S;VnD~VREF
+O.6V
*
*
*
2.5mW
17.5mW
j
0.2ppml%
IO"VN
IO"VN
+SV(uSOO"A
+ 3.0V dc to + 6.0V dc
10kfl
PIN
1,11,1Z.
23.34
2
.,
Binary
Offset Binary 1
Twos Complement
5
6.18.
28,40
7.17.
.....
•
,.,."
- 4O'C to + lOO'C
- SS'C to + 12S'C
9,tO
44-Pad Plastic Leadless
,.
"
44-Pin Grid Array
Best Straighr Line linearity by manipulatioD oftbe pin and/or offset co equalize maximum poeitivc: and neptive deviations.
lpor custom voltqC raDICI use external rcsiSlOn as shown in Fipuc 2d and le.
~DD must track VREFwithin +O.6and -0.3 volta. VDDandVRSFcan. bctied toactbcr iflhc referencevoltageis well buffered.
"'SpeciflClrionssameuAD1l4SNAG.
Spcciftcatiolllaubiect IOcbaoae without DOticc.
CAUTION: OBSERVE PROPER PLUG·IN
POLARITY AND DO NOT PLUG INTO
"LIVE" SOCKET - THE CONVERTER MAY
BE DAMAGED.
2-150 DIGITAL-TO-ANALOG CONVERTERS
-oJ j..-•.
1I•.54'
AD1l45 PIN DESIGNATIONS
0.8Vmax «< 10"Amax
2.0V min (C. IOJLA max
£SDS CLASSIFICATION: •
L. . .w,
·PACKAGE NOTES:
A POSI assembly wain" wafh cycle may trap
,waler between tbe surface mounl device
and P.C. board. A drying period sbould
be observed befoa:e operalion (e.g.,
6SOC bake for t hour).
See Table VI for ~m~d sockets.
NOTES
I
,
.C::i::
'OTTOM~EW
fl
ChipCarrier
Leaded Device(ADI14SAG, BG)
.~=E
•." . 1._ _ _ _ _ _ _- - '•.
(0.&11
DIGITAL INPUTS
Vu.
1io:.
~
Fnnnnnnnnnnn~
±5V,±lOV
Noise(BW - O.I-IOHz)
Noise(BW - 100kHz)
-1.
;'1N1
.U--- \I:.~
±O.lppmllOOOhours
± O.lppmlIOOO hours
±O.lppmllOOOhours
Gain
PlN~
~UU U UUIIU UUU U.
Monotonicity, Guaranteed (Range OC)
Offset, max
Gain,max
PLASTICLEADLESS
CHIP CARRIElt*
±3/4LSB(- ±0.001%)
*
STABILITYVS. TEMPERATURE
16 Bits
IS Bits
14 Bits
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
.sJD.a3,. METHOD 3011.. CATEGORY.
WARNING!
~
~~~
20
21
22
..
.,.
...."
"
......
MNEMONIC D~
NC
NoConnection
0811
o.talMt11
DataBlt10
D... Bft:9
OB10
on
DBa
OataBlt8
AGND
AnllogGround
v_
VottageRefenlnc:elnput
10K
20X
20kU Applleatlon Reeilton
COOE
CUi
lDAc
Cu<
DBOISI
0.,
oaa
D83
084
0. .
DBB
087
30
WIIHB
32
WiUi
Ci
iiD
v_
OGNI>
37
vo
081&180
08,.
0813
0812
10kn~on"i.tor
SefectsDlgillllrnp.atCode
Clear, Activeluw,Asynchronous
LoadDACRegJlter,Active
lowAsyttchronoul
Clock. Rbi"g Edge Triggered
Dahl Bit 0 ILSBI. Serifllinput
Oat. BIt t
OataBit2
OataBit3
DataSlt4
DatliBh6
o.taB1t1
D_BII7
Write High Byte. ActiYt Low
Write lowByla,AClIVe Low
ChtpSelect.Activ1tLow
RDdb_Actlve Low
DlglUl PoW« Suppty
DtgItalGround
AppllcationRwiltorCommon
DACVo!Uee'lPtput
Datil Bit '51MSal. S .....IOutput
OatliBlt14
OauBit13
o.taBit1Z
ADl145
OUTPUT AMPUFIER AND REFERENCE
The users choice of output amplifier and .reference to complement
the AD1l4S will have a direct effect on the overall accuracy,
speed and precision of the complete DAC circuit. The ADl14S
can be optimized accordingly for a wide range of applications.
Internal application resistors are provided to obtain output voltage
rangesofOtoSV,OtoIOV,Oto -SV,Oto -lOY, :tSV,and
:t lOY: External resistors can be used for custom output voltage
ranges as shown in Figure 2.
The ADl14S's high impedance (SkO) voltage output must be
buffered to drive a load since resistive loading at the output
introduces a gain error (e.g., SOMO load resistance introduces a
0.01% gain error). Op amp bias current flows through the DAC
output impedance to introduce an offset term (e.g., 100 nanoamps
bias current introduces a 0.01% offset error).
In the noninverting mode the inputs of the operational amplifier
swing between 0 and + 5 volts. Therefore, to maintain 16-bit
linearity the common-mode rejection ratio of the operational
amplifier must be at least 96dB over a 5 volt range. Special
consideration must be given to offset voltage, offset drift,
bias current, bias drift, common-mode rejection, slew rate,
and settling time when selecting an operational amplifier.
High quality BiFET amplifiers, such as the AD711, are
recommended.
UNIPOLAR MODE CALIBRATION
1. Apply a digital input of all "O"s.
2. Adjust the offset potentiometer until a O.OOOOOV output
is obtained.
3. Apply a digital input of all "l"s.
4. Adjust the gain potentiometer until plus full-scale output
is obtained. (see Table I for full-scale value).
BIPOLAR MODE CALIBRATION
I. Apply a digital input of all "O"s (for offset binary coding)
or 8000 Hex (for twos complement coding).
2. Adjust the offset potentiometer until minus full-scale
output is obtained (see Table I for value).
3. Apply a digital input of all "I"s (for offset binary coding)
or 7FFF Hex (for twos complement coding).
4. Adjust the gain potentiometer until plus full-scale output
is obtained (see Table I for full-scale value).
Output
Unipolar:
OVto5V
O.OOOOOV
4.999924V
O.OOOOOV
9.999848V
0000
FFFF
OVtolOV
0000
FFFF
The linearity and settling time for the AD1l4S have a direct
correlation to the output impedance and recovery time of the
voltage reference. Therefore, a reference with a fast recovery
time and low output impedance, such as the ADS86, is recommended. When choosing a voltage reference, gain error and
temperarure drift must also be considered. A typical reference
and output amplifier hookup is shown in Figure 1.
.5.
Input Code (Hex)
Range
Offset
TwosComp
0000
8000
FFFF
7FFF
0000
8000
FFFF
7FFF
Bipolar:
-5Vto +SV
-IOVto + lOY
-S.OOOOOV
+4.999848V
-1O.OOOOOV
+9.99969SV
Table I. Offset and Gain Adjust
ANALOG OUTPUT RANGE
Figure 2 shows the required external amplifier connections for
standard and custom output ranges. See Figure I for 0 to SV.
AD"4&.
a.
a to
+ 10V Output
d. Unipolar Output
a
Figure 1. AD1145 Configured for a to 5V Output with
External Reference and Unity Gain Amplifier.
OFFSET AND GAIN CALIBRATION
The ADl14S has virtually no offset or gain errors of its own.
When connected in a system, such as that shown in Figure 1,
the system errors are nulled with external potentiometers. Offset
error is nulled by adjusting the offset voltage of the output
amplifier. Gain error is nulled by adjusting the output voltage of
the external reference. The voltmeter used to measure the output
must be capable of IILV resolution. Offset adjustment should be
done before gain adjustment.
c.
e. Bipolar Output
-5V. -10V Output
Figure 2. Analog Output Range Configurations
a to
DIGITAL-TO-ANALOG CONVERTERS 2-151
TIMING DIAGRAM
The timing requirements of the AD1145 are shown in Table II.
The timing diagrams for both serial and parallel input modes of
operation as well as serial output operation are shown in
Figure 3. The serial output mode enables the user to read back
data written to the AD1l45.
Symbol
tos
tOH
twa
tcws
tcwH
Parameter
Data Setup Time
Data Hold Time
Write Pulse Width
Chip Select to Write Setup
Chip Select to Write Hold
Requirement
25ns
IOns
25ns
Ons
CLK is the line used to CLocK serial data into or out of the
input registers. Data is moved on each positive transition of
CLK. Note titat CLK must be held high for parallel operation.
RD is the ReaD line. A low on this line enables the serial output
function and also connects the serial output to the serial input.
CLR is the CLeaR line. A low on this line clears the DAC
output to zero volts regardless of input coding. CLR operates
independently of CS.
CODE determines the input coding of the DAC. A low on this
line inverts the MSB for twos complement coding. A high does
not invert the MSB (for binary and OBN codes).
ODS
Table II. Timing Requirements
PARALLEL OPERATION
The AD1l45 is fully compatible with either 8- or 16-bit microprocessor systems. In an 8-bit system, data may be loaded using
either two or three instruction cycles, with either the high byte
or the low byte being loaded first. Typical load sequences are
(1) load high byte, load low byte, load DAC register, or (2) load
high byte, load low byte and DAC register. With a 16-bit system,
data may be loaded using either one, or two, instruction cycles,
or the DAC may be operated with all of its registers transparent.
Table III illustrates the AD 1145's parallel operation as a function
of its control lines. Note titat CLK and RD must be held high
for parallel operation.
CUI.
CS
WltJ,.B
WRHB
LDAC
OPERATION
0
X
X
X
X
1
0
0
0
0
I
0
0
0
1
Reset DAC Output to
Zero Volts.
InputandDAC
Registen are Transparent.
Load High Byte and
Low Byte Input Registen •
Load DAC Register
from High Byte Register
and Transparent Low
Byte Inputs.
Load Low Byte Input
Register.
Load DAC Register
from Low Byte Register
and Transparent High
Byte Inputs.
Load High Byte Input
Register.
Load DAC Register from
Input Registers.
Load DAC Register from
Input Registers.
No Operation.
No Operation.
.
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
1
X
X
0
1
1
1
X
X
1
X
1
1
1
SERIAL INPUT OPERATION
a~~
__________~~______________~r-
1i6~
If
r
ClK~~cuc=12MHZm••
DATA~~
SERIAL READSACIC OPERAllON
Figure 3. Timing Diagrams
The ADl145 has eight control lines. A brief description of each
line follows:
CS is the Chip Select line and allows multiple ADl145s to share
the same input bus. The desired DAC is selected with the CS
line. A low on this line enables WRLB, WRHB, CLK, and RD
of the selected DAC.
WRLB is the WRite line for the Low Byte input register.
A low
on this line makes the register transparent. A high level latches
the input data into the register.
WRHB is the WRite line for the High Byte input register.
Operation is the same as WRLB.
LDAC is the Load line for the DAC register. A low on this line
makes the DAC register transparent. A high level latches the
data from the input registers into the DAC register. LDAC
operates independently of CS.
2-152 DIGITAL-TO-ANALOG CONVERTERS
Table III. Parallel Operation Truth Table
SERIAL OPERATION
In the serial mode, data is written from DBO/SI into the input
register on each positive going transition of the clock. For error
checking, data can also be readback from the input register to
DBI5/S0. The serial output is switched internally to the serial
input in the readback mode so that the data is recirculated as it
is read. In this way the data is restored after 16 clock cycles.
The data in the DAC register and hence the DAC output voltage
is unchanged during readback. Table IV shows the serial operation
of the AD1145 as it relates to the status of the control lines.
INPUT CODING
The AD1145 accepts data in twos complement, offset binary, or
straight binary formats. The code pin either inverts or not inverts
ADl145
CLR CS
0
x
I
0
I
0
I
x
I
x
CLK RD
x
x
I
•
•
t
0
x
x
x
LDAC OPERATION
x
Reset DAC Output to Zero Volts.
I
Clock Serial Data from DBO/SI into
Input Register.
Clock Serial Data from Input
I
Register out to DB 15/S0.
0
Load DAC Register.
No Operation.
I
SINGLE SUPPLY OPERATION
The AD1l45 can operate with Voo connected to VREF• If CMOS
is used to drive the DAC inputs, the static current drawn from
Voo will be less than IO/LA. If TTL is used to drive the DAC
inputs, the static current draw will be increased to about 3mA
depending on the digital input. Therefore, the reference must
be well buffered to avoid code dependent errors when TTL
inputs are used. Figure 4 shows the AD1l45 operating from a
single supply .
+15V
Table IV. Serial Operation Truth Table
the MSB. If code is low, the MSB is inverted for twos complement
coding. If code is high, the MSB is true for straight binary and
offset binary coding. See Table V for further detail.
CLEAR LINE OPERATION
The clear line, in conjunction with the code line, resets the
DAC output to zero volts. For straight binary operation CODE
should be tied to + V00, the MSB will not be inverted, the
DAC register gets reset to OOOOH, and the AD1l45's output is
reset to zero volts. For twos complement operation, CODE is
tied to DGND, the MSB is inverted, the DAC register is reset
to 112 full scale, and the AD 1145's output is reset to zero volts.
For offset binary operation CODE is tied to CLR. In this way
the MSB is not inverted in normal operation but on CLEAR the
MSB gets inverted, the DAC register is reset to 112 full scale,
and the AD 1145's output is reset to zero volts. Table V shows
the clear operation as a function of CODE input.
CLR CODE OPERATION
0
0
0
I
0
I
I
I
BIPOLAR CLEAR (Twos Complement,
Offset Binary)
UNIPOLAR CLEAR (Binary)
MSB INVERTED (Twos Complement)
MSBTRUE (Binary, Offset Binary)
Table V. Clear Operation Truth Table
POWER-UP RESET
In the event of a power failure, the DAC output is automatically
reset to zero volts upon power-up. When CODE is high, the
DAC is reset to zero for a unipolar clear. When CODE is low,
the DAC is reset to 112 full scale for a bipolar clear (zero volt
output).
GROUNDING AND GUARDING
The AD1145 is a precision D/A converter with 76/LV LSB
resolution at a FSR of 5V. Special care must be taken to insure
proper layout, grounding, and guarding. Analog and digital
grounds should be individually star pointed and then tied together
at a single point near the measurement point. High-speed digital
inputs should be kept separate from low level analog outputs.
Power supplies should be locally bypassed around all high-speed
components and at the power supply input to the printed circuit
board. All high impedance nodes such as the DAC output and
amplifier inputs are sensitive to interference from the digital
input lines. They should be surrounded by low impedance
guard tracks at all times. Figure 2 shows the proper guarding of
the AD1145 depending on output configuration.
Figure 4. Single Supply Configuration
MULTIPLYING DAC OPERATION
The AD1l45 operates as a two quadrant mUltiplying DAC over
a limited voltage range. VREF can vary between 3 and 6 volts.
Voo must track VREF within +0.6 and -0.3 volts. Logic levels
will vary with V00, with a logic low being less than 1I3VDO and
a logic high being greater than 2/3V oo. Voo and VREF may be
tied together provided the reference voltage is well buffered.
A useful application of the multiplying feature is to set the
reference voltage to 4.096 volts and configure the DAC as shown
in Figure 2b for ± IOV range. This provides a ±8.l92 volt fullscale output for a bit weight of 0.25mV per LSB.
MULTIPLE DAC APPLICATION
The AD1l45 is well suited for applications using multiple DACs
sharing the same data bus, as in automated test equipment.
Figure 5 shows a typical multiple DAC hookup. Note that the
WRLB, WRHB, LDAC, RD, CLR, and CLK lines from each
DAC are tied together. A separate chip select (CS) line is provided
to individually select each DAC. Data can be written to one or
all DACs by appropriate selection of the chip select lines. All
DACs may be simultaneously updated by strobing the LDAC
line. A separate CODE line is provided for each DAC so that
they may be independently configured for unipolar and bipolar
coding.
DIGITAL-TO-ANALOG CONVERTERS 2-153
19
L
WiiLi LiiAC -
DBO-DB15
41
31
3tl
WRHB
16
CUi -
AD1145
-WRlB
WiiHi
lDAC
~ iii)
iii)
14
ClR
1
ClK
CDDE
ClK
cs
'~t 3~
CDDE 1 CSi
19
AD1145
Simple 8-Bit and 16-Bit Data Bus Connections
The AD 1145 can be configured to directly connect to an 8-bit
or l6-bit data bus. An 8-bit microprocessor requires at least two
write cycles to supply 16 bits of input data. Utilizing the ADl145's
high byte and low byte input registers, one byte at a time is
loaded from the 8-bit tius. The l6-bit DAC register can be
latched during or after the second byte write operation. Figure
7 shows a typical AD1l45 connection to an 8-bit bus. Note
that the three logic gates can be eliminated if two address lines
are available.
41
31
WRlB
30
WiiHi
15
~
::1!
iii)
CLR
ClK
CDDE
*
DO
cs
An
13.
3~
CODE 2 CS2
AI
19
AO
WRITE
ADll45
41
31
WRlB
30
15 WRHB
lDAC
iii)
CLR
-.:.:: ClK
CODE
l>
ADDRESS
41
07
LiiAC
-To
-CSI
-CS2
ADDRESS
CS3
DECODE
-fa
r,.
r-C§N
Figure 7. 8-Bit Microprocessor Interface
cs
13+
32+
CODE 3 CS3
Figure 5. Multiple DAC Application
PARALLEL READBACK
Full parallel readback can be achieved by adding two 74ALS990
octal D-type read-back latch chips as shown in Figure 6. These
latches also reduce digital feedthrough from the data bus; an
important consideration in high accuracy systems.
A l6-bit microprocessor supplies a complete l6-bit input in a
single write cycle. This eliminates the requirement for the individual high byte and low byte input latches.' Figure 8 shows a
typical AD1l45 connection to a l6-bit bus. The l6-bit DAC
register is made transparent by grounding the LDAC line or can
be strobed for full double buffering.
015
*
74ALS990
OBI
"
DBa
1~~~1
2
9
HB
ADI145
t
12r"
e
RD
WR LB
DO
An
19
DBO
32
CS
ADl145
WRITE
30
WRiiB
30
OS
31 WRLB
11'?
e
0815
AO
OERB
"~
41
WRiiB
WRLB
LDAC
15
OERB
DB7
?
',9 ~ ~7
DB0
9
"2 ---, ;9
74ALS990
'="
Figure 8. 16-Bit Microprocessor Interface
I
Figure 6. Parallel Readback
PACKAGE INFORMATION
The AD1l45 is packaged in a 44-pad glass epoxy chip carrier.
This package is ideal for automated surface mounting due to its
excellent dimensional tolerances and planarity. As the package is
made from the same material as printed circuit boards, it has
the same temperature coefficient of expansion. This minimizes
stress and maximizes product reliability. Standard JEDEC leadless
chip carrier sockets such as those manufactured by Textool can
be used for testing. For conventional through-hole mounting,
the AD1l45 is also available in a PGA package. See Table VI
for recommended sockets.
2-154 DIGITAL-TO-ANALOG CONVERTERS
Package
Purpose
Manufacturer
Mfg. Part No.
PLLCC
Test
Textool
244-4961-000
PGA
Test
Amp
55280-4
PGA
Production
Advanced
CS044-01TG
Interconnections
Augat
Samtec
PPS044-3A0802-L
MPAS-044-ZS-8
Table VI. Recommended Sockets
1IIIIIIII ANALOG
WDEVICES
FEATURES
Low Nonlinearity
Diffarantial: :t 0.00076% max
Integral: :to.00076% max
Differantial TC: :t 1ppmI"C max
Fast Settling
Full Scale: 20,... to :t 0.00076%
LSB: 3"s to :t 0.00076%
Low Power: 375mW Including Reference
Functionally Complete
Internal Reference, Output Voltage Amplifier,
Input Latches and II-Bit Latched Input DACs
for Offset and Gain Correction.
Full Four Quadrant Multiplying
Low Cost
APPLICATIONS
Automatic Tast Equipment
Scientific Instrumentation
Beam Positionars
Robotics
Graphics Displays
Microprocessor Compatible
16-Bit D/A Converters
ADl147/ADl148 I
AD1l47/AD1l48 FUNCTIONAL BLOCK DIAGRAMS
MGND
+V
PGND -Vs
WRle
REf ,-_J REF
OUT
IN
WiiIM MSB B8
oiG
GENERAL DESCRIPTION
The AD1l47 and AD1l48 are 16-bit resolution, hybrid, latched
input, digital-to-anaiog converters. Their two 8-bit latched input
DACs allow direct offset and gain cortection via microprocessor
interface.
The ADl147 and ADl148 are constructed as hybrids in a compact
32-pin, triple wide dual-in-line package. Precision CMOS switches
and a laser-trimmed thin-fllm resistor network are used to provide
16-bit accoracy and excellent temperature stability.
The Main (l6-bit) DAC is loaded as a 16-bit word. The offset
and gain correction DACs are each loaded as 8-bit words. The
AD1l47 multiplexes both correction DACs' inputs with the
Main DAC's eight LSBs. This pin sharing allows for additional
pin connections providing: external reference input, a current
output and feedback resistors for voltage output ranges of 0 to
+ SV, 0 to + lOY, :t5V and :t lOY.
CMSB CBB
'WR/M
MBB
816
The AD1l48 correction DACs' inputs are separate from the
Main DAC's. The gain correction DAC's inputs are multiplexed
with the offset DAC's 8-bit inputs. This allows for a separate 8bit bus interface with the correction DACs - common in applications such as Automatic Test Equipment.
DIGITAL·TO·ANALOG CONVERTERS 2-155
•
SPEC IFI CAli 0NS
(typical@
+m
and ndIId supplies unless oIbalWisa specified)
MODEL
ADIl47
ADIl48
RESOLUTION
16 Bits
•
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
ACCURACY
Dilferential Nonlinearity
±0.00016% FSR' (DIU)
Integral Nonlinearity
± 0.00076% FSR' (max)
Monotonic (16 Bits)
Guaranteed
Offset
Gain
Adjustable to Zero
Adjustable to Full Scale
STABILITY
Differential Nonlinearity
Offset
BipolarOffset
Gain (Includes Int. Ref.)
STABIUTY, Long-Term
(ppm/looobr.)
Differential Nonlinearity
Offset
Bipolar Offset
Gain
REFERENCE VOLTAGE
Output Voltage
OutputCurrent
Ext. Ref Voltage Range'
Input Resistance
± Ippml"C(max)
± 20",VfC (max)
± 6ppmI"C (max)
± 10ppml"C (max)
±lppm
±3ppm
±3ppm
±12ppm
+lO.OOV, ±0.3%(max)
2mA(mu)
·-12V to + 12V
12k.(}
±0.00076%FSR'(typ),
±O.OOI5% FSR' (DIU)
±0.00076%FSR'(typ),
±O.OOI5%FSR'(DIU)
•
**
**
*.
0.15
13.81
32
1
.L
0.15 (3.81
--I
~onOM VIEW
0.1(2.5) GRID
* PIN 1 LOCATION IS IDENTIFIED BY A WHITE DOT
ON THE TOP SURFACE.
**
5 Volt CMOSlfTL Compan"ble
Binary (BIN)
Offset Binary (OBN)
Binary (BIN)
+5V,+IOV,±5V,±IOV
-2mA,±lmA
±SOOmv
6O",Vnns
±I5V(±5%)
± lZ.5Vto ± 17V
± l5mA(max)
375mWtyp,5OOmWDIU
..
±IOV
**
*
*
*
•
OFFSET ADJUSTMENT
Raqe
ResoIution(@±IOy)
± 0.05% FSR
1/4LSB
*
GAIN ADJUSTMENT
Raqe(Uoipolar/Bipolar)
Resolution (Uoipolar/Bipolar)
±O.2%FSR'/±O.I%FSR'
lLSB/I12LSB
NAI*
NAI*
TEMPERATURE RANGE
Rated PerfOl"llWlCe
Stprase Temperature
- 25'C to + 85'C
- 4O'C to + lOO'C
•
•
*
2.00"x 1.17'x 0.225" (all maximums)
(SO.8xZ9.7xS.7mm)
NOTES
*Specifica.......... uADI147.
HAD114&doeallOlproridepinCOllDCCdoastocurn::ntoutput,ftfereJM:einput,rcferaccoutputOl'thc
iD_ _ _ .Outputool.......... fiDd .. ±IOV.
Specifica..... oubjcotlO ....... ~tDOticc.
2-156 DIGITAL-TO-ANALOG CONVERTERS
0
~~DEVICE
*
±10ppm/V
+10ppm/V
'FSR ...... FuII-&:oIeRaaae.
'RalOClpedomwlceilSpedfiedwitb +lOV_.
WARNING!
**
POWER SUPPLY SENSITIVITY
Offset
Gain
SIZE
1
1
1...81
*
POWER REQUIREMENTS
Voltage(RatedPerfoII11lll1Ce)
Voltage (Operating)
Supply Current Drain
Tota1Powet@Vs = ± I5V
17
.*
~1-
Sett1ingTimeto ±0.00076%
Voltage, Full-Scale Step
Voltage, LSB Step
Current
ANALOG OUTPUT
Voltage
Current
VoitageComp1iance
Noise (lOOkHzBW)
,.
**
DYNAMIC PERFORMANCE
DIGITAL INPUT CODES
MainDAC
Uoipolar
Bipolar
Cotrec:tion DACo
L....------",...J....i..
•
•
AD1l47 PIN DESIGNATIONS
PIN
FUNCTION
PIN
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+Vs
PGND
-Vs
AMP IN
32
31
30
29
28
27
26
25
24
Vo
10k
5k
10k
REFIN
REFciuT
MGND
OIG
Bl61CB8
B151CB7
Bl41CB6
Bl31CB5
Bl21CB4
Bll/CB3
Bl0ICB2
B9/CMSB
10
MGND
WRlM
WR/C
MSB
B2
B3
B4
B5
B6
B7
B8
23
22
21
20
19
18
17
AD1l48 PIN DESIGNATIONS
PIN
FUNCTION
PIN
FUNCTION
1
2
3
4
5
6
7
S
9
10
11
12
13
14
15
16
+Vs
PGND
-Vs
MSB
B2
B3
B4
B5
B6
B7
B8
B9
Bl0
B11
B12
B13
32
Vo
MGND
WRiM
WRIC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OIG
CBS
CB7
CB6
CB5
CB4
CB3
CB2
CMSB
B16
B15
B14
ADl147/ADl148
ANALOG OUTPUT RANGE
The AD1l48 is internally connected for ± 10 volts output
range.
The AD1l47 is pin programmable to provide a variety of analog
outputs, either current or voltage. A unipolar output current of
o to - 2mA is available at pin 5, and can be offset by lmA (by
connecting pin 28 to pin 29) for a bipolar output of ± lmA.
Output voltage ranges (+5V, + lOY, ±5V and ± lOY) are
available at pin 32 by connecting the current output (pin 5) to
the amplifier input (pin 4) and the appropriate internal feedback
resistors to the amplifier output (pin 32) as shown in Figure 1.
SYMBOL PARAMETER
REQUIREMENT
MainDAC
tDS
Data Setup Time
tDH
Data Hold Time
tWR
Write Pulse Width
l40nsmin
l20nsmin
250nsmin
Correction DACs
tcs
O/G To Write Setup Time
ten
O/G To Write Hold Time
tDS
Data Valid To Write
Setup Time
tDH
Data Valid To Write Hold
tWR
Write Pulse Width
200nsmin
20nsmin
llOnsmin
Onsmin
lOOns min
Table I. Timing Requirements
MAIN OAC WRITE CYCLE TIMING DIAGRAM
o TO
+5V
OTO +10V
CORRECTtON OAts WRITE CYCLE TIMING DIAGRAM
NOTES:
1. ALL INPUT SIGNAL RISE AND FAU TIMES MEASURED FROM
10% to 90% of Voo' Voo= +5V. l,t=t,.=20ns.
2. TIMING MEASUREMENT REFERENCE LEVEL lS VItI +2VL
Figure 2. AD1147 and ADl148 Timing Diagrams
otSV
±10V
Figure 1. AD 1147 Analog Output Range Pin Programming
TIMING DIAGRAM
The timing requirements for the models AD1l47 and AD1l48
are shown in Table I. The timing diagrams for the MAIN 16-bit
DAC and the 8-bit Correction DACs are shown in Figure 2.
The three control lines operate as follows:
WRlM is the write line for the main DAC. The latches are
transparent when the write line is low, and latched when the
write line goes high.
WRlC is the write line for the correction DACs. Operation is
the same as above.
O/G selects between the offset correction DAC and the gain
correction DAC. A high level on this pin selects the offset DAC.
A low level selects the gain DAC.
OFFSET AND GAIN CALmRATION
Initial offset and gain errors can be adjusted to zero using the
two internal 8-bit calibration DAC's. There are three control
lines used in the calibration sequence: WRlM is the write line
for the Main (l6-bit) DAC - the latches are transparent when
the write line is low, and latched when the write line goes high;
WRlC is the write line for the correction DACs and operates the
same as WRlM; O/G selects between the offset correction DAC
and the gain correction DAC - a high level on this pin selects
the offset DAC and a low level selects the gain DAC.
Offset and Gain calibrations are performed as follows:
1. With WRlM low, set the digital inputs of the Main DAC to
"000 .... 00" (in unipolar mode) or "100.... 00" (in bipolar
mode).
2. Set WRlM high to latch the digital input into the Main
DAC.
3. With WRIC low and O/G high, adjust the digital inputs of
the offset correction DAC until the Main DAC's output
DIGITAL-TO-ANALOG CONVERTERS 2-157
•
voltage (pin Vo ) is as close to 0.000000 volts as possible.
Note that incrementing the digital input produces a more
negative voltage output.
4. Set WRlC high to latch the digital input into the offset correction
DAC.
5. With WRlM low, set the digital input j)f the Main DAC to
"111 .... 11".
output-amplifier's input connection short and surrounded by a
grounded guard. To avoid degrading the gain drift performance
of the DAC, always use the internal feedback resistors, since
they are matched to the internal current weighting resistors of
the DAC. It is also good practice to connect the negative input
(Pin 4, AMP IN) of the unused internal output amplifier to its
output (Pin 32, Vo ).
6. Set WRlM high to latch the digital input into the Main
DAC.
The current drift of the ADI147 is typically 3S0pAlOC from
+ 150C to + 3SOC. When using the AD OP-::7, the total offset
drift of the output signal will typically be less t.'\ll~ 21J.VfOC.
7. With WRlC low and 0/0 low, adjust the digital inputs of the
gain correction DAC until the Main DAC's output Voltage
(pin Vo ) is as close as possible to the positive full-scale voltage
shown below in Table II. Note that incrementing the digital
input produces a more negative voltage output.
As a second example, a high output current amplifier can be
connected to the ADI147 to create a programmable power supply.
The configuration is the same as shown for the AD OP-07C in
Figure 4.
8. Set WRlC high to latch the digital input into the gain correction
DAC.
9. Calibration is complete. Set WRlM low and beginlresume
normal digital-ta-analog conversion via the Main DAC.
Output Voltage Range
Positive Full-Scale Voltage
Oto +5volts
Oto + 10 volts
±5volts
± 10 volts
+ 4.999924 volts
+ 9.999847 volts
+ 4.999847 volts
+ 9.999695 volts
Table /I. Gain Calibration
GROUNDING AND GUARDING
The current from the measurement ground pin (MGND) is
constant, independent of digital input, for ease of making measurements. This is the high quality ground for the AD1l47 and
AD1l48. It should be connected to the high quality ground in
the application. Power ground (PGND) should be connected to
measurement ground (MGND) at the measurement point.
The current output pin (10 ) of the AD1l47 is sensitive to interference from the digital input lines. It should be surrounded by
a grounded guard at all times. When using the AD1l47 in the
voltage output mode, both the "10 " and "AMP IN" pins should
be guarded (see Figure 3).
AD1147
EXTERNAL
AMPUFIER
(j)
I
I
(j)
_'N~'
'.
(j)
. I
I
.
,
PIN Silo
i1
PIN"
BIPOLAR V
PIN 6
PIN 6fMGND
I
WITH EXTERNAL OUTPUT AMPLIFIER
o
= DIGITAL INPUT x VREF x
216
Sk
Rt- _
b
V REF
10k
PINS
,
•
FULL FOUR-QUADRANT MULTIPLYING DAC
The AD1l47 is a full four-quadrant multiplying DAC and can
be used with references varying between + 12 and - 12 volts.
Typical linearity vs. external reference voltage is shown in Figure
S. Output voltage ranges other than those provided can be obtained
by connecting the appropriate reference voltage to "REF IN"
(Pin 28), (see Figure 4). The DAC output voltage can be calculated
as follows:
UNIPOLAR V = DIGITAL INPUT x V REF x R
216
5k
fb
o
AD1147
PIN 41AMP IN
Figure 4. Precision DAC with :±8.192V F.S. Output
Voltage
DIFFERENTIAL
LINEARITY
ERROR 1% OF FULL-SCALE RANGEl
WITH INTERNAL
OUTPUT AMPUAER
Figure 3. Typical Guarding Techniques
0.00038%
0.00076%
" . V"
0.00153%
EXTERNAL AMPLIFIER FOR LOW DRIFI' VOLTAGE
OUTPUT OR HIGH OUTPUT CURRENT
The internal output amplifier of the AD1l47 is designed for
high-speed applications that require fast settling times. An external
precision operational amplifier like the AD OP-07C can be
applied when lower offset (less than 20",VfOC) is important (see
Figure 4). Simply connect the current output (Pin 5) to the
inverting input of the amplifier and connect the proper feedback
resistors as shown in Figure I. Be certain to keep the current
2-158 DIGITAL-TO-ANALOG CONVERTERS
0.00306%
0,0061%
0,0122%
~
~
/'
II
1/
10
12
POsmVE OR NEGATIVE REFERENCE VOLTAGE
Figure 5. Typical Differential Linearity vs. External Reference Voltage
Applications - ADl147/ADl148
8-BIT MICROPROCESSOR INTERFACE
The AD1l47/ADll48 can easily be operated with an 8-bit bus
by the addition of an octal latch. The l6-bit Main DAC is loaded
from the 8-bit bus as two 8-bit bytes. Figure 6 shows the conflglllBtion when using a 74HC573 octal latch.
A code width can be measured by determining the analog input
voltage at which the transition occurs from the code under test
to its next lower digital output code and then differencing that
analog value with the same determined for the transition from
the code under test to its next higher digital output code.
The eight most significant bits are latched into the 74HC573 by
setting the "latch enable" control line low. The eight least significant bits are then placed on the bus. Now all sixteen bits can
be simultaneously latched into the Main DAC by setting WRlM
high.
Virtually all converters exhibit a degree of noise. This will necessitate an averaging technique to determine the analog input value
for a code transition - where a reduction in analog input voltage
produces a majority of the lower digital code decisions and an
analog input increase produces a majority of the higher digital
code decisions.
The offset and gain correction DAC's are calibrated as they
were for l6-bit microprocessor applications. See the "OFFSET
AND GAIN CALIBRATION" section of this data sheet.
Begin testing by calibrating the offset and gain of the ADC
under test per the manufacturer's instructions. Set the digital
inputs of the reference DAC to the nominal value of the desired
transition edge (produces an analog input to the device under
test that is either 1I2LSB below or l/2LSB above the ideal analog
input for the code under test). Increment or decrement this
digital input until the Device Under Test (D.U.T.) outputs the
digital code below the transition 50010 of the time and the digital
code above the transition 50% of the time. Record this digital
input and repeat the procedure for the next transition of the
nominal code to be measured. Compare this second digital input
with the recorded input. The difference between these two
digital values is the width of the code being measured. A perfect
code width is 16 counts of the reference DAC. Each count
more, or less than 16, corresponds to a differential linearity
error of lIl6LSB for the D.U.T. The arithmetic average of the
two digital input values is the center of the code being tested.
Each count of difference between this actual code center and the
ideal, nominal code center represents an integral linearity error
of l/16LSB.
Figure 6. Connections for 8-Bit Bus Interface
AUTOMATIC TESTING OF 12-BIT ADC'S AND DAC'S
The AD1l47 and AD1l48 can be used as a reference DAC to
automatically test the integral and differential linearity of l2-bit
ADCs and DACs. An ideal reference DAC should be an order
of magnitude more accurate than the devices to be tested. The
AD1l47 and AD1l48 are sixteen times more accurate than the
devices to be tested and therefore can be considered ideal.
The general test procedures for ADCs and DACs are shown
below. Before actual testing proceeds, calibrate the offset and
gain of the AD1l47 or AD1l48 (see "OFFSET AND GAIN
CALIBRATION" section of this data sheet).
ADC TESTING (refer to Figures 7 and 8).
The differential nonlinearity of ADC's is the difference between
the actual code widths of the analog input voltage vs. the ideal,
one LSB, code widths of a perfect converter. A code width is
the range of analog input voltage which produces the desired
digital output word.
16·BIT"P
AND
CONTROL
B12
12·BIT ADC
(DEVICE UNDER TEST)
I----Q
STATUS
I--_~
CONVERT COMMAND
Figure 7. ADC Testing
DIGITAL-TO-ANALOG CONVERTERS 2-159
II
DAC TESTING (refer to Figure 9).
To test 12-bit DACs begin with offset and gain cslibration of
the DAC under test per the manufacturer's instructions. Set the
digital inputs of the reference DAC and the D.U.T. to the
desired code. Latch this digital input into the reference DAC.
The DACs' outputs are differenced and amplified by an ADS24A
instrumentBtion amplifier. The voltage error between the DACs
is the integral linearity error.
32(2)
IDEAL 12·BIT AID CONVERTER OUTPUT
24
~~~\
g
""t:
16(1)
~
Now null the meter and then increment or decrement the digitsl
input to the D.U.T. only, by one LSB. The meter reading will
correspond to the code width of the new digital input word.
The deviation of this voltage from the ideal value of one LSB is
the differential linearity error of the D. U. T .
(
TRANSITION
EDGE 1
Q
~
~
8
w
u
~
IDEAL CODE CENTER
0:
t:
'"'!!.
30
~
AD1147
16.BIT"P
I-
AND
Z
CONTROL
::l
o
U
w
Q
8
20
~
16(1)
~
"I
-l
10
L
INTEGRqL
LINEARITY
ERROR
ACTUAL CODE WIDTH
IDEAL 1LSB
CODE WIDTH
DIFFERENTIAL
~~R~:ITV
---I
DIGITAL
VOLTMETER
ANALOG INPUT
0.5
1
i
1.0
1.5
VOLTAGE. IN LSBs
(n
1
2.0
12·BITS
Figure 9. DAC Testing
Figure 8. 12-Bit ADC Linearity Testing
2-160 DIGITAL-TO·ANALOG CONVERTERS
16-Bit
PCM Audio OAC
A01856 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
0.0025% THO
Fast Settling Permits 2x, 4x or 8x Oversampling
:!::3V Output
Optional Trim Allows Superlinear Performance
:!::5V to :!::12V Operation
16-Pin Plastic DIP Package
Serial Input
APPLICATIONS
Compact Disc Players
Digital Audio Amplifiers
OAT Recorders and Players
Synthesizers and Keyboards
AD1856 FUNCTIONAL BLOCK DIAGRAM
-Vs
DGND
VL
Vs
TRIM
MSBADJ
lOUT
elK
lE
AGND
SJ
RF
PRODUCT DESCRIPTION
The ADl856 is a monolithic 16-bit PCM Audio DAC. Each device provides a voltage output amplifier, 16-bit DAC, 16-bit
serial-to-parallel input register and voltage reference. The digital
portion of the ADl856 is fabricated with CMOS logic elements
that are provided by Analog Devices' BiMOS II process. The
analog portion of the ADl856 is fabricated with bipolar and
MOS devices as well as thin fIlm resistors.
This combination of circuit elements, as well as careful design
and layout techniques, results in high performance audio playback. Laser trimming of the linearity error affords extremely
low total harmonic distortion. An optional linearity trim pin is
provided to allow residual differential linearity error at midscale
to be eliminated. This feature is particularly valuable for low
distortion reconstructions of low amplitude signals. Output
glitch is also small contributing to the overall high level of performance. The output amplifIer achieves fast settling and high
slew rates, providing a full ± 3V signal at load currents up to
8mA. The output amplifter is short circuit protected and can
withstand indefInite shorts to ground.
The serial input interface consists of the clock, data and latch
enable pins. The serial 2s complement data word is clocked into
the DAC, MSB fIrst, by the external data clock. The latch enable signal transfers the input word from the internal serial input register to the parallel DAC input register. The input clock
can support a 10MHz clock rate. This serial input port is compatible with popular digital fIlter chips used in consumer audio
products. These fIlters operate at oversampling rates of 2 x, 4x
and 8 x sampling frequency.
-VL
VOUT
Power dissipation is 1l0mW typical with ±5V supplies and is a
typical300mW when ±12V supplies are used.
The AD1856 is packaged in a 16-pin plastic DIP and incorporates the industry-standard pinout. Operation is guaranteed over
the temperature range of - 25"<: to + 70°C and over the voltage
supply range of ±4.75 to ±13.2V.
PRODUCT HIGHLIGHTS
1. Total harmonic distortion is 100% tested.
2. MSB trim feature allows s.!perlinear operation.
3. The ADl856 operates with ±5V to ±12V supplies.
4. Serial interface is compatible with digital fIlter chips.
5. 1.5.,.s settling time permits 2x, 4x and 8x oversampling.
6. No external components are required.
7. 96dB dynamic range.
8. ±3V or ±lmA output capability.
9. 16-bit resolution.
10. 2s complement serial input words.
11. Low cost.
12. 16-pin plastic DIP package.
The ADl856 can operate with ±5V to ±12V power supplies
making it suitable for both the portable and home-use markets.
The digital supplies, VL and -VL> can be separated from the
analog supplies, Vs and - Vs, for reduced digital crosstalk. Separate analog and digital ground pins are also provided.
DIGITAL-TO-ANALOG CONVERTERS 2-161
•
SPECIFICATIONS
-
(typical at TA = +25°C and + 5V supplies unless otherwise noted)
Parameter
Min
fu
RESOLUTION
DIGITAL INPUTS
V1H
V1L
IIH,VIH=VL
IlvVIL =0.4
Clock Input Frequency
2.4
0
Max
Units
16
Bits
VL
0.8
1.0
-50
V
V
10
IlA
ILA
MHz
ACCURACY
Gain Error
Bipolar Zero Error
Differential Linearity Error
Noise (rms, 20Hz to 20kHz) @ Bipolar Zero
±2.0
±30
±0.001
6
TOTAL HARMONIC DISTORTION
OdB,99O.5Hz
ADI856N-K
ADI856N-J
AD1856N
-20dB,99O.5Hz
AD1856N-K
AD1856N-J
AD1856N
-60dB, 990.5Hz
AD1856N-K
AD1856N-J
AD1856N
0.002
0.002
0.002
0.018
0.018
0.018
1.8
1.8
1.8
MONOTONICITY
15
Bits
DRIFT (0 to +70°C)
Total Drift
Bipolar Zero Drift
±25
±4
ppm of FSRI"C
ppm of FSRI"C
1.5
1.0
ILS
ILS
V/ILS
ns
ns
SETTLING TIME (to ±0.006% of FSR)
Voltage Output
6V Step
lLSB Step
Slew Rate
Current Output
lrnA Step 100 to 1000 Load
lkO Load
WARM-UP TIME
OUTPUT
Voltage Output Configuration
Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output ConfIguration
Bipolar Range (±30%)
Output Impedance (±30%)
POWER SUPPLY
Voltage, +VL and +Vs
Voltage, -VL and -Vs
Current, +1, VL and Vs= +5V, IOMHz Clock
Current, -I, -VL and -Vs = -5V, IOMHz Clock
Current, +1, VL and Vs = +12V, 10MHz Clock
Current, -I, -VLand -Vs =-12V, 10MHzClock
350
350
1
±3
V
rnA
0
0.1
IndefInite to Common
1.0
1.7
4.75
-13.2
0
-25
-60
%
%
%
%
%
%
%
%
%
min
±8
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at fmal test.
2-162 DIGITAL-TO-ANALOG CONVERTERS
0.0025
0.004
0.008
0.020
0.040
0.040
2.0
4.0
4.0
9
POWER DISSIPATION
Vs and VL = ±5V, 10MHz Clock
Vs and VL = ±12V, 10MHz Clock
TEMPERATURE RANGE
SpecifIcation
Operation
Storage
%
mV
% ofFSR
ILV
rnA
kO
5
-5
10
-25
12
-27
13.2
-4.75
17
110
300
260
mW
mW
+70
+70
+100
°C
°C
°C
-35
V
V
rnA
rnA
rnA
rnA
AD1856
ABSOLUTE MAXIMUM RATINGS·
PIN DESIGNATIONS
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2V
Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2V
-VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . -13.2 to OV
-Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . . -13.2 to OV
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . -0.3 to VL
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
Short Circuit Protection . . . . . . . . .Indefinite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C, lOsec
Storage Temperature . . . . . . . . . . . . . . . . -60°C to + lOO°C
·Stresses greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and func~
tional operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied. Ex~
posure to absolute maximum rating conditions for extended periods may
affect device reliability.
Pin
1
2
3
4
S
6
7
8
9
10
11
12
13
14
IS
16
Function
Description
-Vs
DGND
VL
NC
CLK
LE
DATA
-VL
VOUT
Rp
SJ
AGND
Analog Negative Power Supply
Digital Ground
Logic Positive Power Supply
No Connection
Data Clock Input
Latch Enable Input
Serial Data Input
Logic Negative Power Supply
Voltage Output
Feedback Resistor
Summing Junction
Analog Ground
Current Output
MSB Adjustment Terminal
MSB Trimming Potentiometer Terminal
Analog Positive Power Supply
lOUT
MSB ADJ
TRIM
Vs
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
ORDERING GUIDE
Model
THD@FS
Package
Options·
ADl8S6N
ADl8S6N-J
ADl8S6N-K
0.008%
0.004%
0.0025%
N-16
N-16
N-16
*See Section 14 for package outline information.
DIGITAL-TO-ANALOG CONVERTERS 2-163
•
Definition of Specifications
TOTAL HARMONIC DISTORTION
Total Harmonic Distortion (THD) is defmed as the ratio of the
square root of the sum of the squares of the values of the harmonics to the value of the fundamental input frequency. It is
expressed in percent (%) or decibels (dB).
THD is a measure of the magnitude and distribution of linearity
error and differential linearity error. The distribution of these
errors may be different, depending on the amplitude of the output signal. Therefore, to be most useful, THD should be specified for both large and small signal amplitudes.
16-BIT SERIAL-TO-PARALLEL
CONVERSION
CLOCK
LE
DATA
SETTLING TIME
Settling Time is the time required for the output to reach and
remain within a specified error band about its fmal value, measured from the digital input transition. It is the primary measure
of dynamic performance.
DYNAMIC RANGE
Dynamic Range is the specification that indicates the ratio of the
smallest signal the converter can resolve to the largest signal it is
able to produce. As a ratio, it is usually expressed in decibels
(dB). The theoretical dynamic range of an n-bit converter is
approximately (6xn) dB. In the case of the 16-bit AD1856, that
is 96dB. The actual dynamic range of a converter is less than
the theoretical value due to limitations imposed by noise and
quantization and other errors.
BIPOLAR ZERO ERROR
Bipolar Zero Error is the deviation in the actual analog output
from the ideal output (OV) when the 2s complement input code
representing half scale (all Os) is loaded in the input register.
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error is the measure of the variation in
analog value, normalized to full scale, associated with a lLSB
change in the digital input. Monotonic behavior requires that
the differential linearity error not exceed 1LSB in the negative
direction.
MONOTONICITY
A DIA converter is monotonic if the output either increases or
remains constant as the digital input increases.
2-164 DIGITAL-TO-ANALOG CONVERTERS
AD1856 Block Diagram
FUNCTIONAL DESCRIPTION
The AD1856 is a complete, monolithic 16-bit PCM audio DAC.
No additional external components are required for operation.
As shown in the block diagram, each chip contains a voltage
reference, an output amplifier, a 16-bit DAC, a 16-bit input
latch and a 16-bit serial-to-parallel input register.
The voltsge reference consists of a bandgap circuit and buffer
amplifier. This circuitry produces an output voltsge that is
stable over time and temperature changes.
The 16-bit D/A converter uses a combination of segmented
decoder and R-2R architectures to achieve consistent linearity
and differential linearity. The resistors which form the ladder
structure are fabricated with silicon-chromium thin film. Laser
trimming of these resistors further reduces linearity error
resulting in low output distortion.
The output amplifier uses both MOS and bipolar devices to
produce low offset, high slew-rate and optimum settling time.
When combined with the onboard feedback resistor, the output
op amp can convert the output current of the AD1856 to a voltage output.
AD1856
ANALOG CIRCUIT CONSIDERATIONS
+5V
GROUNDING RECOMMENDATIONS
The ADl856 has two pins, designated ANALOG and DIGITAL ground. The analog ground pin is the "high quality"
ground reference point for the device. The analog ground pin
should be connected to the analog common point in the system.
The output load should also be connected to that same point.
AD1856
The digital ground pin returns ground current from the digital
logic portions of the ADl856 circuitry. This pin should be connected to the digital common point in the system.
As illustrated in Figure I, the analog and digital grounds should
be connected together at one point in the system.
DIGITAL
COMMON
-5V
+5V
+5V
Figure 2. Alternate Recommended Schematic
ANALOG
COMMON
-5V
-5V
Figure 1. Recommended Circuit Schematic
POWER SUPPLIES AND DECOUPLING
The AD 1856 has four power supply input pins. ± Vs provide
the supply voltages to operate the linear portions of the DAC
including the voltage reference, output amplifier and control
amplifier. The ±Vs supplies are designed to operate from ±5V
to ±12V.
The ± VL supplies operate the digital portions of the chip including the input shift register and the input latching circuitry.
The ±VL supplies are also designed to operate from ±5V to
± 12V subject only to the limitation that -VL may not be more
negative than -Vs.
Decoupling capacitors should be used on all power supply pins.
Furthermore, good engineering practice suggests that these capacitors be placed as close as possible to the package pins as
well as the common points. The logic supplies, ±Vv should be
decoupled to digital common; and the analog supplies, ± Vs,
should be decoupled to analog common.
four separate voltage supplies are not necessary for good circuit
performance. For example, Figure 2 illustrates a system where
only a single positive and a single negative supply are available.
Given that these two supplies are within the range of ±5V to
±12V, they may be used to power the AD1856. In this case, the
positive logic and positive analog supplies may both be connected to the single positive supply. The negative logic and
negative analog supplies may both be connected to the single
negative supply. Performance would benefit from a measure of
isolation between the supplies introduced by using simple lowpass fIlters in the individual power supply leads.
As with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than I % ripple be incorporated into the design of any system using these devices.
TOTAL HARMONIC DISTORTION
The THD figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD specification, therefore, provides a direct method to classify and choose an audio DAC for a
desired level of performance.
Analog Devices tests and grades all ADl856s on the basis of
THD performance. A block diagram of the test setup is shown
in Figure 3. In this test setup, a digital data stream, representing a Odb, -2OdB or -60dB sine wave is sent to the device under test. The frequency of this waveform is 99O.5Hz. Input data
is sent to the ADl856 at a 4XFs rate (l76.4kHz). The ADl856
under test produces an analog output signal with the on-board
op amp.
The use of four separate power supplies will reduce feedthrough
from the digital portion of the system to the linear portions of
the system, thus contributing to good performance. However,
DIGITAL-TO-ANALOG CONVERTERS 2-165
•
I--
4xFs
DATA
RATE
16·BIT
DIGITAL
WAVEFORM
GENERATOR
DATA
LATCH
CLOCK
OUTPUT
0
1
1
I
I
..
1
1
0
:!:3V
VOUT
1
1
1
4096 PT .
FFT
ANALYZER
I
23 CYCLES--I
f\j\ ..f\/\
AD1856
1
0
0
0
1
0
0
1
1
'--'
0
1
1
0
0
1
0
1
0
I
1
0
1
LOW PASS
I
DIGITIZER
1
1
1
~
u_
990.5Hz
NOTCH
0
1
0
Figure 3. Block Diagram of Distortion Test Circuit
The automatic test equipment digitizes 4096 samples of the out·
put test waveform, incorporating 23 complete cycles of sine
wave. A 4096 point FFT is performed on the results of the test.
Based on the fIrst 9 harmonics of the fundamental 990.5Hz out·
put wave, the total harmouic distortion of the device is calcu·
lated. Neither a deglitcher nor an MSB trim is used during the
THD test.
The circuit design, layout and manufacturing techuiques em·
ployed in the production of the AD1856 result in excellent
THD performance. Figure 4 shows the typical unadjusted THD
performance of the AD1856 for various amplitudes of a 1kHz
output signal. As can be seen, the AD1856 offers excellent per·
formance, even at amplitudes as low as -60dB. Figure 5 illus·
trates the typical THD vs. frequency performance.
0.'
~
0.6
..
liS
0.02
~
I
e
0.0'
~ O.OOS
/
I
'.0
I III
'0000
OPTIONAL MSB ADJUSTMENT
Use of an optional adjustment circuit allows residual differential
linearity error around midscale to be eliminated. These errors
are especially important when low amplitude signals are being
reproduced. In those cases, as' the signal amplitude decreases,
the ratio of the midscale differential linearity error to the signal
amplitude increases and THD increases.
..........
"-
0.'
a:
c
:c
~
,GOO
'00
r-...
:i
e
,
FREQUENCY - Hz
~
~
1/
z
0
(FULL SCALE)
Figure 5. Typical THD vs. Frequency
'IZ
0
i,..-
0.002
0.001
19.0
(-2Od8)
'6 BITS..........
'-
0.0'
0.001
-60
-50
-40
-30
-20
-'0
"
VOUT - dB
Therefore, for best performance at low output levels, the op·
tional MSB adjust circuitry shown in Figure 6 may be used.
This circuit allows the differential linearity error at midscale to
be zeroed out. However, no adjustments are required to meet
data sheet specifIcations.
NOTE
Od8=FULL SCALE
470kO
Figure 4. Typical Unadjusted THD vs. Amplitude
100kO
...
200kO
@)-..I\I....\I\o..~-...Y'r~~·.\I\oI\ooo--~0-v.
MSBAOJ @-----....
TRIM
Figure 6. Optional THD Adjust Circuit
2-166 DIGITAL·TO·ANALOG CONVERTERS
AD1856
DIGITAL CIRCUIT CONSIDERATIONS
Input Data
Data is transmitted to the AD1856 in a bit stream composed of
16-bit words with a serial, MSB first format. Three signals must
be present to achieve proper operation: the Data, Clock and
Latch Enable signals. Input data bits are clocked into the input
register on the rising edge of the Clock signal. The LSB is
clocked in on the 16th clock pulse. When all data bits are
loaded, a low-going Latch Enable pulse updates the DAC input.
Figure 7 illustrates the general signal requirements for data
transfer for the AD1856.
The input pins of the AD1856 are both TIL and 5V CMOS
compatible, independent of power supply voltages used.
The input requirements illustrated in Figures 7 and 8 are compatible with the data outputs provided by popular DSP ftIter
chips used in digital audio playback systems. The AD1856 input
clock can run at a lOMHz rate. This clock rate will allow data
transfer rates for 2 x, 4 x or 8 x oversampling reconstruction.
The application section of this data sheet contains additional
guides for using the AD1856 with various DSP filter chips available from Sony, NPC and Yamaha.
CLOCK
DATA
DATA
CLOCK
LATCH1~1
_IT
"~.~,:~
~30n'~~30n.
>80"5
X'---_C
r~
>15"5
Figure 7. Signal Requirements of AD 1856
Figure 8 provides the specific timing requirements that must be
met in order for the data transfer to be accomplished properly.
Figure 8. Timing Relationships of Input Signals
APPLICATIONS OF THE ADl856 PCM AUDIO DAC
The AD1856 is a versatile digital-to-analog converter designed
for applications in consumer digital audio equipment. Portable,
car and home compact disc player, digital audio-amplifier and
DAT systems can all use the AD1856. Various circuit architectures are popular in these systems. They include stereo playback
sections featuring one DAC per system, one DAC per audio
channel (left/right) or even multiple DACs per channel. Funhermore, these architectures use different output reconstruction
rates to accomplish these functions including reproduction at the
sample rate Fs (Ix), at twice the sample rate(2xF s ), at four
times the sample rate (4xF s ) and even at eight times the sample
rate (8xFs ). Fs is 44. 1kHz for CD and 48kHz for DAT
applications.
One DAC per System
Figure 9 shows a circuit using one AD1856 per system to reproduce both stereo channels of a typical first generation digital
LEFT
SAMPLE _________________-+____________
LEFT
OUTPUT
~
DATA
CLOCK
V OUT ~~~~~--~----~~----------_,
LATCH AD1856
RIGHT
OUTPUT
SAMPLE ______________________________-'
RIGHT
Figure 9. AD1856 in a One DAC per System Architecture
DIGITAL-TO-ANALOG CONVERTERS 2-167
•
audio system. The input data is fed to the AD1856 in a format
which alternates between left channel data and right channel
data. The output of the AD1856 is switched between the left
channel and right channel output samplelhold amplifiers
(SHAs). The SHAs demultiplex and deglitch the output of the
AD1856. The timing diagram for the control signals for this circuit is shown in Figure 10.
CLOCK
DATA
I--- LEFT WORD -
..
......
~IIooI---RIGHT WORD---!
LATCHl~~r
g~
~1.5"Smin
t"-l
1.S.... mln
SAMPLE -----,
I
RIGHT
L---J
I
SAPf:~
L-J
Figure 10. Control Signals for One DAC Circuit
SAMPLE _ _ _ _ _ _ _ _ _ _ _ _
The architecture illustrated in Figure 9 is suitable for low-end
home or portable systems. However, its usefulness in mid- or
high-end digital audio reproduction is limited by the phase delay
which is introduced in the multiplexed output. This phase delay
is due to the fact that the information contained in the input bit
stream represents left and right channel audio sampled simultaneously but reconstructed alternately. One obvious solution to
this problem may be arrived at by incorporating a third, noninverting SHA to delay the output of one channel to "catch up
to" the other channel. This eliminates the phase shift by restoring simultaneous reproduction. This solution is illustrated in
Figure 11.
~
LEFT
OUTPUT
LEFT
DATA
CLOCK
OUT}----t
LATCH AD1856
SAMPLE
RIGHT
-----------------------------~~--r_~
RIGHT
OUTPUT
Figure 11. Third SHA Eliminates Phase Delay
LEFT ------t DATA
CLOCK
DATA
OUT )-""',..,..._.-_""'_------,
LATCH AD1856
LEFT
OUTPUT
RIGHT
DATA
_++-1
DATA
CLOCK
OUT ~VV~~~~~~-----~
LATCH AD1856
RIGHT
OUTPUT
Figure 12. One DAC per Channel Architecture
2-168 DIGITAL-TO-ANALOG CONVERTERS
AD1856
One DAC per Channel
Another approach used to eliminate phase delay between left
and right channels employs one DAC per channel. In this architecture, the input data bit streams for the left channel and the
right channel are simultaneously sent and latched into each
DAC. This "second generation" approach, shown in Figure 12,
is suitable for higher performance digital-audio playback units.
DATA
CLOCK
Two DACs per Channel (Four DAC System)
Another architecture uses two DACs per channel. In this
scheme, shown in Figure 13, each DAC reproduces one half of
the output waveform. The advantage obtained is that midscale
differential linearity error no longer effects the zero-crossing
points of the waveforms. Its effects are shifted to the points
where the output waveform crosses ± 3/4 full scale. The result is
that THD performance for low amplitude signals is greatly
improved. Not shown in Figure 13 is a VLSI circuit required to
separate the incoming data into the appropriate form required
by each DAC.
OUT
LATCH AD1856
LEFT
OUTPUT
DATA
CLOCK
OUT
LATCH AD1856
DATA
CLOCK
OUT
LATCH AD1856
RIGHT
OUTPUT
DATA
CLOCK
OUT
LATCH AD1856
Figure 13. Two DACs per Channel Eliminate Midscale Distortion from the Zero-Crossing Points
DIGITAL FILTERING AND OVERSAMPLING
Oversampling is a term which refers to playback techniques in
which the reconstruction frequency used is an integral (2 or
more) multiple of the original quantized data rate. For example,
in compact disc stereo digital audio playback units, the original
quantized data sample rate is 44. 1kHz. Popular oversampling
rates are 2x or 4x Fs yielding reconstruction rates of 88.2 and
176.4kHz, respectively.
Oversampling is used to ease the performance constraints of the
low-pass ftlters which usually follow the reconstruction DAC. In
any signal reconstructed from sampled data, unwanted
frequency components are introduced in the output spectrum;
these components are centered at the reconstruction frequency.
When a 44. 1kHz reconstruction frequency is used, the actual
frequency band of interest is 20Hz to 20kHz, and the band of
unwanted "image" frequency components extends from
44. 1kHz to approximately 24kHz and from 44.1kHz to 64kHz.
These unwanted components must be removed with a low-pass
ftlter of very high order. First generation digital audio systems
often use low-pass ftlters of 9, 11 and even 13 poles. Linear
implementations of these ftlters are expensive, difficult to manufacture and can produce distortion due to varying group delay
characteristics.
When a 2x reconstruction frequency (88.2kHz) is used, the
lowest unwanted frequency components now extend down to
approximately 68kHz. A 4x rate (176.4kHz) has unwanted
components extending down to approximately 156kHz. The ftlter response needed to n:move these frequency components can
now be less steep. This means that a lower order ftlter may be
used resulting in less distortion at lower cost. Linear ftlters with
3 or 5 poles are adequate to do the job and are quite common in
digital audio products employing oversampling techniques.
DIGITAL-TO-ANALOG CONVERTERS 2-169
•
Oversampling techniques require that the serial input data
stream run at the same integral multiple of the original data
rate. So, while the constraints on the output low-pass fIlter are
eased, the constraints on the serial digital input port and the
settling time of the output stage are not.
The actual oversampling operation takes place in the digital fIlter chip which is located "upstream" from the DAC. The digital
fIlter accepts data from the media and adds the additional reconstruction points according to the algorithm and coefficients
stored in the fIlter chip. Since the digital fIlters actually interpolate these additional reconstruction points, they have earned the
name "interpolation fIlters."
The ADI856 is compatible with popular digital fIlter chips used
in digital audio products such as the NPC SM5807, NPC
SM5805, Yamaha YM3414, and Sony CXD1l36.
DUAL DAC, 4x Fs OVERSAMPLING ARCHITECTURE
Figure 14 illustrates the use of an NPC digital fIlter chip with
two AD1856 audio DACs. This scheme achieves four times
oversampling reconstruction with a dedicated DAC per channel.
In this example of a typical compact disc player application, the
digital fIlter chip accepts serial input words from the digital
decoder/processor at a 44. 1kHz sample rate. Through the use of
oversampling, the SM5807 transmits data to the two DACs at a
176.4kHz rate. The serial DAC input data is sent out of the
DOUT pin to the serial inputs of the DACs. Left channel and
right channel data are sent alternately down the same wire. The
LeftlRight Channel Output signal, LRCO and two logic gates
demultiplex the data clock signals from BCKO. In this example,
the BCKO rate is 192xFs . However, a 196xFs clock can be
used if SCSL is wired to a logic zero. Finally, left and right
channel deglitching signals are provided. At the user's option,
these signals may be used to control external sample-hold amplifiers in order to obtain optimal performance.
+5V
CLOCK
LATCH
OUT
LEFT
OUTPUT
DATA AD1856
LRCO
DOUT
aCKO
SM5807
DGR
0--+.-.----.
o--+------IH
DATA
LATCH
DGL
OUT
' - - - - - - - I f CLOCK AD1856
RIGHT
OUTPUT
OPTIONAL
DEGUTCH
SIGNALS
Figure 14. NPC SM5807 and AD 1856 Interface
ACHIEVING 8x Fs OVERSAMPLING WITH AD1856S
AND YAMAHA YM3414
Figure 15 illustrates the combination of a Yamaha YM3414 digital fIlter chip and two AD1856 audio DACs. In this scheme, the
use ofaI6.9344MHz clock allows an 8 times oversampling rate
for extremely high performance. In addition, a lower-order low-
pass fIlter may be used without sacrificing performance. The
DAC input data is simultaneously transmitted to the input registers of the DACs through dedicated left and right channel output pins on the YM3414. As before, optional samplelhold
signals are provided.
,---oooooooOjICLOCK
r--ooooo can be separated from the
analog supplies, Vs and -V s, for reduced digital crosstalk.
Separate analog and digital ground pins are also provided.
Power dissipation is 1l0mW typical with ±5V supplies and is
225mW typical when + 5Vf -12V supplies are used.
The ADI860 is available in either a 16-pin plastic DIP or a 16pin plastic SOIC surface mount package. Operation is guaranteed over the temperature range of - 25°C to +70°C and over
the voltage supply range of ±4.75 to ± B.2V.
PRODUCT HIGHLIGHTS
1. 18-bit resolution provides 108dB dynamic range.
2. No external components are required.
3. Operates with ±5V to ±12V supplies.
4. 16-pin DIP or space saving SOIC package.
5. 1l0mW power dissipation.
6. 1.5 .... s settling time permits 2x, 4x and 8x oversampling.
7. ±3Vor ±lmA output capability.
8. THD + Noise is 100% tested.
DIGITAL-TO-ANALOG CONVERTERS 2-171
SPECIFICATIONS
(TA at +25°C and ±5V supplies unless otherwise noted)
Min
Typ
RESOLUTION
DIGITALINPUTS VIH
VIL
IIH' VIH=VL
IlL' VIL =0.4
Clock Input Frequency
2.0
Units
18
Bits
+VL
0.8
1.0
-10
V
V
I1A
12.5
!LA
MHz
ACCURACY
Gain Error
Midscale Output Voltage
Differential Linearity Error
±2.0
±30.
±O.OOI
TOTAL HARMONIC DISTORTION + NOISE
OdB, 990.5Hz
AD1860N-K, R-K
ADI860N-J, R-J
AD1860N, R
- 20dB, 990.5Hz AD1860N-K, R-K
ADI860N-], R-J
AD1860N, R
-60dB, 990.5Hz AD1860N-K, R-K
AD1860N-], R-J
AD1860N, R
0.002
0.002
0.004
0.006
0.010
0.010
0.9
0.9
0.9
SIGNAL TO NOISE RATIO (A-Weight Filter)
Max
%
mV
% ofFSR
0.0025
0.004
0.008
0.020
0.020
0.040
2.0
2.0
4.0
%
%
%
%
%
%
%
%
%
108
dB
DRIFT (0 to + 70°C)
Total Drift
Bipolar Zero Drift
±25
±4
ppm of FSRf'C
ppm of FSRf'C
SETTLING TIME (to ±0.0015% of FSR)
Voltage Output, 6V Step
1LSB Step
Slew Rate
Current Output 1rnA Step IOn to lOon Load
1kn Load
1.5
1.0
9
350
350
I1S
I1S
V/l1s
ns
ns
MONOTONICITY
15
Bits
OUTPUT
Voltage Output ConfIguration
Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration
Bipolar Range (±30%)
Output Impedance (±30%)
POWER SUPPLY
Voltage VL and Vs
Voltage -VL and -Vs
Current +1, VL andV s =5V, 10MHzClock
-I, -VL and -Vs= -5V, 10MHz Clock
Current +1, VL and Vs= 12V, 10MHz Clock
-I, -VL and -Vs= -12V, 10MHz Clock
Current +1, VL and +Vs= +5V, 10MHz Clock
-I, -VLand -Vs =-12V, IOMHzClock
POWER DISSIPATION
Vs and VL = ±5V, 10MHz Clock
Vs and VL = ±12V, 10MHz Clock
Vs and VL = +5V, -Vs and -VL = -12V, 10MHz Clock
2-172 DIGITAL-TO-ANALOG CONVERTERS
102
±2.88
±8
±3.0
±3.12
0.1
IndefInite to Common
±1.0
1.7
4.75
-13.2
10_0
12.0
10.5
13.5
10
14
110
300
225
V
mA
n
rnA
kn
13.2
-4.75
13.0
-15.0
V
V
rnA
rnA
rnA
rnA
rnA
rnA
mW
mW
mW
AD1860
Min
Typ
Max
Units
TEMPERATURE RANGE
Specification
Operation
Storage
0
-25
-60
+25
+70
+70
+100
°C
°C
°C
WARMUP TIME
I
min
Specifications subject to change without notice.
TYPICAL PERFORMANCE
ABSOLUTE MAXIMUM RATINGS·
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2V
Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2V
-VL to DGND . . . . . . . . . . . . . . . . . . . . . . . -13.2 to OV
-Vs to AGND . . . . . . . . . . . • . . . . . . . . . . . -13.2 to OV
Digital Inputs to DGND . . . . . . . . . • . . . . . . . . -0.3 to VL
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ± O.3V
Short Circuit . . . . . . . . . . . . . . . . Indefinite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C, lOsec
Storage Temperature . . . . . . . . . . . . . . . . -60°C to + lOO°C
350
300
±12V SUPPLIES
250
~
t
200
+5V/-12V
SUPPLIES
Ii!
.1
150
Note
·Stresses greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and func·
tional operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
-
r---
.1
100
±5V SUPPLIES
i
50
2
..l
10
4
12
CLOCK FREQUENCY - MHz
Power Dissipation vs. Clock Frequency
350
-&OdB
300
....
'"
0.1
250
~
I
I
~
-
0.010
200
Ii!
-2OdB
100
OdB ~
0.001
o
10
20
30
40
50
TEMPERATURE - ·C
THO vs. Temperature
&0
~
150
70
&0
V
L
V
L
V
~
50
10
6
11
12
±SUPPLY VOLTAGES
Power Dissipation vs. Supply Voltages
DIGITAL-TO-ANALOG CONVERTERS 2-173
CA.UTION:
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.
WARNING!
~~OEVICE
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
-Vs
DGND
VL
NC
ClK
lE
DATA
-VL
V OUT
RF
SJ
AGND
louT
MSB ADJ
TRIM
Vs
Analog Negative Power Supply
logic Ground
logic Positive Power Supply
No Connection
Data Clock Input
latch Enable Input
Serial Data Input
logic Negative Power Supply
Voltage Output
Feedback Resistor
Summing Junction
Analog Ground
Current Output
MSB Adjustment Terminal
MSB Trimming Potentiometer Terminal
Analog Positive Power Supply
ORDERING GUIDE
Model and Package Option·
DIP Package (N-16)
Surface Mount (R-16)
TUD@FS
ADl860N
ADl860N-J
AD1860N-K
ADl860R
ADl860R-J
ADl860R-K
0.008%
0.004%
0.0025%
*See Section 14 for package outline information.
2-174 DIGITAL-TO-ANALOG CONVERTERS
eJ
Definition of Specifications - AD1860
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion plus Noise (THD+ N) is defined as
the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental
input frequency. It is usually expressed in percent (%).
THD+ N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending on the amplitude of the output signal. Therefore, to be most
useful, THD+ N should be specified for both large and small
signal amplitudes.
SETTLING TIME
Settling Time is the time required for the output to reach and
remain within a specified error band about its final value, measured from the digital input transition. It is a primary measure
of dynamic performance.
DYNAMIC RANGE
Dynamic Range is the specification that indicates the ratio of the
smallest signal the converter can resolve to the largest signal it is
able to produce. As a ratio, it is usually expressed in decibels
(dBs). The theoretical dynamic range of an n-bit converter is
(6xn) dB. In the case of the l8-bit AD1860, that is 108dB.
The actual dynamic range of a converter is less than the theoretical value due to limitations imposed by noise and other errors.
MIDSCALE ERROR
Midscale Error, or bipolar zero error, is the deviation of the
actual analog output from the ideal output (OV) when the 2s
complement input code representing half scale is loaded in the
input register.
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error is the measure of the variation in
analog value, normalized to full scale, associated with a lLSB
change in the digital input. Monotonic behavior requires that
the differential linearity error not exceed lLSB in the negative
direction.
MONOTONICITY
A DfA converter is monotonic if the output either increases or
remains constant as the digital input increases.
SIGNAL-TO-NOISE RATIO
The Signal-to-Noise Ratio is defined as the ratio of the amplitude of the output with no signal present to the amplitude of the
output when a full-scale output is present. This is measured
with a standard A-Weight filter.
l8·BIT SERIAL·TO-PARALLEL
CONVERSION
CLOCK
LE
DATA
AD1860 Block Diagram
FUNCTIONAL DESCRIPTION
The ADl860 is a complete monolithic IS-bit PCM Audio DAC.
No additional external components are required for operation.
As shown in the block diagram, each chip contains a voltage
reference, an output amplifier, an IS-bit DAC, an IS-bit input
latch and an IS-bit serial to parallel input register.
The voltage reference consists of a bandgap circuit and buffer
amplifier. This combination of elements produces a reference
voltage that is unaffected by changes in temperature and age.
The DAC output voltage, which is derived from the reference
voltage, is also unaffected by these environmental changes.
The output amplifier uses both MOS and bipolar devices to produce low offset, high slew rate and optimum settling time.
When combined with the on chip feedback resistor, the output
op amp converts the output current of the AD 1860 to a voltage
output.
The IS-bit D/A converter uses a combination of segmented
decoder and R-2R architecture to achieve consistent linearity
and differential linearity. The resistors which form the ladder
structure are fabricated with silicon chromium thin mm. Laser
trimming of these resistors further reduces linearity error resulting in low output distortion.
The input register and serial to parallel converter are fabricated
with CMOS logic gates. These gates allow the achievement of
fast switching speeds and low power consumption. This contributes to the overall low power dissipation of the ADlS60.
DIGITAL-TO-ANALOG CONVERTERS 2-175
Analog Circuit Considerations
GROUNDING RECOMMENDATIONS
The AD1860 has two pins, designated Analog and Digital
ground. The analog ground pin is the "high quality" ground
reference point for the device. The analog ground pin should be
connected to the analog common point in the system. The output load should also be connected to that same point.
four separate voltage supplies are not necessary for good circuit
performance. For example, Figure 2 illustrates a system where
only a single positive and a single negative supply are available.
+5V
The digital ground pin returns ground current from the digital
logic portions of the AD1860 circuitry. This pin should be connected to the digital common point in the system.
As illustrated in Figure 1, the analog and digital grounds should
be connected together at one point in the system.
+5V
AD1860
+5V
DIGITAL
COMMON
-5V
AD1860
Figure 2. Typical Power Supply Sensitivity
ANALOG
COMMON
-5V
-5V
Figure 1. Recommended Circuit Schematic
POWER SUPPLIES AND DECOUPLING
Given that these two supplies are within the range of ±5V to
± l2\" they may be used to power the AD1860. In this case,
the positive logic and positive analog supplies may both be connected to the single positive supply. The negative logic and
negative analog supplies may both be connected to the single
negative supply. Performance would benefit from a measure of
isolation between the supplies introduc,ed by using simple low
pass filters in the individual power supply leads.
The AD1860 has four power supply input pins. ±Vs provide
the supply voltages to operate the linear portions of the DAC
including the voltage reference, output amplifier and control
amplifier. The ±Vs supplies are designed to operate from ±5V
to ± l2V.
As with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be incorporated into the design of any system using these devices.
The ± V .. supplies operate the digital portions of the chip including the input shift register and the input latching circuitry.
The ±V .. supplies are also designed to be operated from ±5V to
± 12 V subject only to the limitation that -V L may not be more
negative than -Vs.
TOTAL HARMONIC DISTORTION
Decoupling capacitors should be used on all power supply pins.
Furthermore, good engineering practice suggests that these capacitors be placed as close as possible to the package pins as
well as the common points. The logic supplies, ±V.., should be
decoupled to digital common; and the analog supplies, ±Vs,
should be decoupled to analog common.
The use of four separate power supplies will reduce feedthrough
from the digital portion of the system to the linear portion of
the system, thus contributing to good performance. However,
2-176 DIGITAL-TO-ANALOG CONVERTERS
+ NOISE
The THD figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD specification, therefore, provides a direct method to classify and choose an audio DAC for a
desired level of performance.
By combining noise measurement with THD measurement, a
THD + N specification is produced. This specification measures
all undesirable signal produced by the DAC, including harmonic
products of the test tone as well as noise.
Analog Devices tests and grades all AD l860s on the basis of
THD + N performance. A block diagram of the test setup is
shown in Figure 3. In this test setup, a digital data stream
representing a OdB, -20dB or -60dB sinewave is sent to the
device under test. The frequency of this waveform in 990.5 Hz.
Analog Circuit Details - AD1860
I--
4xFs
DATA
RATE
18-BIT
DIGITAL
WAVEFORM
GENERATOR
DATA
LATCH
CLOCK
OUTPUT
0
1
1
I-
1
I
I
--l
±3V
V OUT
1 0
1 1
1 0
0
1
1
.--.
4096 PT.
FFT
ANALYZER
1
1
0
23 CYCLES
f\J\.- -f\/\
AD1860
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
DIGITIZER
1
1
1
0
-
30kHz
LOW PASS
t--
99O.5Hz
NOTCH
f--
1
0
L...
4096 ----l
r-- SAMPLES
~
Figure 3. Block Diagram of Distortion Test Circuit
Input data is sent to the AD1860 at a 4xFs rate (176.4kHz).
The ADI860 under test produces an output signal with its
onboard op amp. The automatic test equipment digitizes 4096
samples of the output test waveform, incorporating 23 complete
cycles of the sinewave. A 4096 point FFT is performed on the
results of the test. Based on the harmonics of the fundamental
990.SHz test tone and the noise components, the total harmonic
distortion + noise of the device is calculated. Neither a deglitcher nor an MSB trim is used during this test.
..,
~
•. 5
i..
i
2
(-2OdBI
The circuit design, layout and manufacturing techniques employed in the production of the AD 1860 result in excellent
THD performance. Figure 4 shows the typical unadjusted THD
performance of the AD 1860 for various amplitudes and frequencies of output signals. As can be seen, the ADl860 offers excellent performance, even at low amplitudes.
OPTIONAL MSB ADJUSTMENT
Use of an optional adjust circuitry allows residual differential
linearity error around midscale to be eliminated. This error is
especially important when low amplitude signals are being reproduced. In those cases, as the signal amplitude decreases, the
ratio of the midscale differential linearity error to the signal amplitude increases, thereby increasing THD.
Therefore, for best performance at low output levels, the optional MSB adjust circuitry shown in Figure 5 may be used to
improve performance.
0 .• '
r·
oos
V'
-~
(FUUSCALEI
••002
....,
.
,
...
,
....
TRIM ~..7:.,}.,.!I__1"'~l\i,.,~I__2....~",!I__-0-vs
MSBADJ~~----~-
I III
FREQUENCY - Hz
,
Figure 5. Optional THD Adjust Circuit
Figure 4. Typical THD vs Frequency
DIGITAL-TO-ANALOG CONVERTERS 2-177
•
DATA
LATCH
I
1
Figure 6. Signal Requirements for AD 1860
DIGITAL CIRCUIT CONSIDERATIONS
Input Data
Data is transmitted to the ADl860 in a bit stream composed of
18-bit words with a serial, MSB first format. Three signals must
be present to achieve proper operation. They are the Data,
Clock and Latch Enable signals. Input data bits are clocked into
the input register on the rising edge of the Clock signal. The
LSB is clocked in on the 18th clock pulse. When all data bits
are loaded, a low-going Latch Enable pulse updates the DAC
input. Figure 6 illustrates the general signal requirements for
data transfer for the AD1860.
IT
\+1
DATA
>15ns
~
X
I
>30n5
..
C
>15n5
. t;=..>son5-
CLOCK~
LATCH
Timing
Figure 7 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the ADl860 are both TTL and SV
CMOS compatible, independent of the power supplies used.
The input requirements illustrated in Figures 6 and 7 are compatible with the data outputs provided by popular DSP filter
chips used in digital audio playback systems. The ADI860 input
clock can run at a 12.SMHz rate. This clock rate will allow data
transfer rates for 2 x, 4 x or 8 x oversampling reconstruction.
The application section of this datasheet contains additional
guides for using the ADI860 with various DSP filter chips available from Sony, NPC and Yamaha.
~
~~30ns
.....
>80ns
.-J
~
r
>15ns
~
\
>40ns
.~
L
/
>40ns
~
Figure 7. Timing Relationships of Input Signals
2-178 DIGITAL-TO-ANALOG CONVERTERS
r-
AD1860
APPLICATIONS OF THE ADl860 PCM AUDIO DAC
The AD 1860 is a versatile digital-to-analog converter designed
for applications in consumer digital audio equipment. Portable,
car and home compact disc player, digital audio amplifier and
DAT schemes can all use the AD186O. Various circuit architectures are popular in these systems. They include stereo playback
sections featuring one DAC per system, one DAC per audio
DATA
CLOCK
NONINVERTING
SHA
(OPTIONAL)
OUT
LATCH A01S60
SAMJI[E
LEFT
channel (left/right) or mUltiple DACs per channel. Furthermore,
these architectures use different output reconstruction rates to
accomplish these functions including reproduction at the sample
rate Fs (I x), at twice the sample rate (2xFs), at four times
the sample rate (4x Fs) and even at eight times the sample rate
(8xFs)' Fs is 44. 1kHz for CD and 48kHz for DAT applications.
_~===:::-!.
LEFT
OUTPUT
___-.J
RIGHT
OUTPUT
SAMPLE __________________________--------~~~--------~
RIGHT
Figure 8. AD1860 in a One DAC per System Architecture
One DAC per System
Figure 8 shows a circuit using one AD1860 per system to reproduce both channels of a typical first generation stereo digital
audio system. The input data is fed to the ADl860 in a format
which alternates between left channel data and right channel
data. The output of the ADI860 is switched between the left
channel and right channel output samplelhold amplifiers
(SHAs). The SHAs demultiplex and deglitch the output of the
AD 1860. The timing diag-am for the control signals for this circuit are shown in Figure 9.
However, when only two SHAs are used, the actual system performance is limited by the phase delay introduced by the demultiplexed format. This undesirable phase delay is caused by the
fact that the data words presented to the inputs of the DAC represent samples taken at precisely the same point in time. But
CLOCK
D'ITA
LATCH1~~1
I-----i '5".
g~~ ' -
I
min
~ 15". mon
r-1
'--
~
RIGHT ----,L---.....JIr-----------t-------------SA~~~
L-,jr-------
Figure 9. Control Signals for One DAC Circuit
when reconstructed and demultiplexed by a single DAC, these
same outputs occur at slightly different times.
By incorporating a noninverting SHA into the circuit, the phase
delay can be eliminated. In Figure 8, the optional SHA ensures
that the left channel output appears at the same time as the
right channel output. This minor change to the circuit eliminates the artificially induced phase delay by restoring simultaneous outputs.
Following the outputs of the SHAs are low pass filters. These
filters are required in any sampled data system to remove
unwanted aliased components introduced by the sample and
reconstruction operations.
One DAC per Channel
A second approach used to eliminate phase delay between left
and right channels employs one DAC per channel. In this architecture, the input data bitstream for each channel is transmitted
and then latched into the input register of each DAC. This
"second'generation" approach is illustrated in Figure 10. A
standard implementation of a low pass filter is shown at the output of each DAC. An optional sample/hold amplifier could be
connected between the DACs and the LPFs to deglitch the outputs. This is not required, however, to achieve the specified
performance.
Two DACs per Channel
Another architecture uses two DACs per channel. In this
scheme each DAC reproduces one half of the output waveform.
The advantage obtained with this structure is that midscale differential linearity error no longer affects the zero crossing points
of the waveforms. Its effects are shifted to the points where the
output waveform crosses ±3/4 full scale. The result is that THD
performance for low amplitude signals is greatly improved.
DIGITAL-TO-ANALOG CONVERTERS 2-179
DIGITAL
FILTER
CHIP
DATA AGND
LATCH
OUTo---~~~~~~~~~~
1/2
NJN5532
CLOCK AD1860
~ AD71.!..
L ______
LOW PASS FILTER SECTION
..L __
RIGHT
..EU..!..pu..!l
OUTPUT SECTION
WITH MUTE CONmOL
Figure 10. One DAC per Channel Architecture with LPF
DIGITAL FILTERING AND OVERSAMPLING
Oversampling is a term which refers to playback techniques in
which the reconstruction frequency used is an integral (2 or
more) multiple of the original quantized data rate. For example,
in compact disc stereo digital audio playback units, the original
quantized data sample rate is 44. 1kHz. Popular oversampling
rates are 2x or 4xFs , yielding reconstruction rates of 88.2 and
176.4kHz, respectively.
Oversampling is used to ease the performance constraints of the
low pass filters which follow the reconstruction DAC. In any
signal reconstructed from sampled data, unwanted frequency
components are introduced in the output spectrum; these components are centered at the reconstruction frequency. When a
44.1kHz reconstruction frequency is used, the actual frequency
band of interest is 20Hz to 20kHz, and the band of unwanted
"image" frequency components extends from 44. 1kHz to
approximately 24kHz. These unwanted components must be
removed with a low-pass filter of very high order. First generation digital audio systems often used low-pass filters of 9, 11 and
. even 13 poles. Linear implementations of these filters are expensive, difficult to manufacture and can produce distortion due to
varying group delay characteristics.
When a 2 x reconstruction frequency (88.2kHz) is used, the lowest frequency components now extend down to approximately
2-180 DIGITAL-TO-ANALOG CONVERTERS
68kHz. A 4Xrate (176.4kHz) has unwanted components extending down to approximately 156kHz. The filter response needed
to remove these frequency components can now be less steep.
This means that a lower order filter may be used resulting in
less distortion at lower cost. Linear filters with 3 or 5 poles, as
shown in Figure 10, are adequate to do the job and are quite
common in digital audio products employing oversampling
techniques.
Oversampling techniques require the serial input data stream to
run at the same integral multiple of the original data rate. So,
while the constraints on the output low-pass filter are eased, the
constraints on the serial digital input port and the settling time
of the output stage are not.
The actual oversampling operation takes place in the digital filter chip (DSP) which is located "upstream" from the DAC. The
digital filter accepts data from the media and adds the addit.ional
reconstruction points according to the algorithm and coefficients
stored in the filter chip. Since the digital filters actually interpolate these additional reconstruction points, they have earned the
name "interpolation filters".
The AD1860 is compatible with popular digital filter chips
used in digital audio products such as the Sony CXDI088, the
Yamaha YM3434 and the Npe SM5813.
AD1860
DAC. The digital filter chip provides 18-bit data words to the
DACs at 4xFs ' Very high performance can be achieved.
Figure II illustrates the combination of a second generation
digital filter chip, the Sony CXDI088, and the ADI860 audio
16.9344MHz
+5V
~
....-..........
} - - - ( ) CLOCK
....---Q LATCH
~
BCK ORES
Voo
DATA
03 0--+--+-1
AD1860
D2o--r~~--;--t
CXD1088Q
V 55
LEFT
OUTPUT
OUT
010-+-4
LRO
FORM APTL APTR
DATA
LATCH
RIGHT
OUTPUT
OUT
)---QCLOCK AD1860
L ___ _
OPTIONAL
SHA SECTION
OUTPUT
SECTION
24
24
BCK
LRCK
LRO -----l
R1
L1
L
R4
R3
R2
I
L2
L3
L4
J
R1
LRO----l
-
I
01
02
MSB
LSB
MSB
LSB
03 - - ,
APTL
APTR
Figure 11. 4xFs with the CXD1088Q
DIGITAL-TD-ANALOG CONVERTERS 2-181
•
Figure 12 illustrates the combination of a Yamaha YM3434 digital fIlter chip and two ADl860 audio DACs. This combination
of components results in 8xFs oversampling reconstruction
rates. This rate allows the use of lower order output low pass
fIlters than would be required with lower oversampling rates,
without sacrificing performance. In this high performance CD
player application, the DAC input data is simultaneously transmitted to the input registers of the DACs through dedicated left
and right channel output pins on the YM3434 .. This implementation does not require any external components to achieve the
full108dB dynamic range afforded by the IS-bit ADl860 audio
DAC. As before, optional samplelhold signals are provided.
Figure 13 shows the schematic for 8xFs when two ADI860s are
used with an NPC SM5813AP/APT digital fIlter chip. As can be
seen, this application is very similar to the one shown in Figure
12. See Figure 10 for an example of a typical LPF.
CLOCK
LEFT
OUTPUT
r-If---0 LATCH
XI
ST 16/18 DLO
r----ii-~!!DA!T!:A~.!;~~!/
BCO o----+-e
YM3434
WCOo-----.
SHL
SHR ORO 0-----++--0 DATA
Yf---0 LATCH
CLOCK
' - - - - - - - - - - - - - - - - S/H
LOW
PASS
FILTER
RIGHT
OUTPUT
TO OPTIONAL
DEGLITCH
CIRCUIT
Figure 12. YM3434 and AD1860 Achieve 8xFs
+5V
XI
CLOCK
r-If---0 LATCH
COB OW20 DOL 0----+-+--0_DATA
_ _ _ _ _J'
BCKO
SM5813AP/APT
LEFT
OUTPUT
o------+-.
WCKOo----..
OW18
DGL DOR o - - - - - ! - - ! - - - o DATA
YI---o LATCH
CLOCK
' - - - - - - - - - - - - S/H TO OPTIONAL
DEGLITCH
CIRCUIT
Figure 13. SM5813APIAPT and AD 1860 Achieve 8xFs
2-182 DIGITAL-TO-ANALOG CONVERTERS
RIGHT
OUTPUT
~ANALOG
WDEVICES
LOGDAC
CMOS Logarithmic OfAConverter
AD7111* I
AD7111 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Dynamic Range: 88.5dB
Resolution: 0.375dB
OnoChip Data Latches
Full ±25V Input Range Multiplying DAC
Low Distortion
Single +5V Supply
Latch·Up Free (No Protection Schottky Required)
APPLICATIONS
Digitally Controlled AGC Systems
Audio Attenuatan
Wide Dynamic Range AID Converters
Sonar Systems
Function Generators
07 06 05 04 03 02 01 DO
(MSS)
GENERAL DESCRIPTION
The LOGDACTM AD7111 is a CMOS multiplying D/A converter which can artenuate an analog input signal over the
range 0 to -88.SdB in O.37SdB steps.
The degree of attenuation is detennined by an 8-bit data word
which is latched into on-chip data latches using microprocessor compatible control signals CS and WR. Operating frequency range of the device is from dc to several hundred kHz.
The device is available in a standard 16-pin DIP and in a
20-terminal surface mount package.
DATA INPUTS
ORDERING INFORMATION1,
Specified
Accuracy
Range
(LSB)
2
Temperature Range and Package Options'
010
+ 70°C
-25oClo
+ 85°C - 55°C to + 125°C
Plastic DIP (N-16) Hermetic (Q-16) Hermetic (Q-16)
Oto60dB
Oto72dB
AD7111KN
AD7111LN
AD7111BQ
AD7111CQ
AD7111TQ
AD7111UQ
LCCC4 (E-20A)
Oto6OdB
Oto72dB
AD7111TE
AD711IUE
NOTES
·U.S. Patent No. 4521764
LOGDAC is a trademark of Analog Devices, Inc.
ITo order MIL-STD-883, Class B processed parts, addl883B to part number.
Contact your local sales office for military data sheet.
2Analog Devices reserves to right to ship ceramic (package option D-16)
packages in lielj of cerdip (package option Q-16) packages.
'See Section 14 for package outline information.
4LCCC: Leadless Ceramic Chip Carrier.
DIGITAL-TO-ANALOG CONVERTERS 2-183
-lBYdc,
SPECIFIC".'JIONS v_== +5Y,V.=
V.. =BY output amplifier AD544 except when staIId)
(Villi
p--
NOMINAL RESOLUTION
1
AD7111L/C/U GRADES
TA = +25 OC TA -Tmin, T_
AD7111K/B/T GRADES
TA =+2SOC
TA 10 Tmir., Tmax
0.375
0.375
0.375"
dB
Oto 36
Oto 30
Guaranteed attenuation ranges
Oto48
o to 30
Oto4B
dB min
Oto 54
dB min
for specified step sizes
o to 42
Oto 66
o to 42
Oto72
o to 36
Oto60
dB min
dB min
dB min
ACCURACY RELATIVE TO 0dB ATTENUATION
0.375dB Step"
Accuracy'; ±0.17dB
Oto 36
Monotonic
Oto 54
0.75dB Step"
Accuracy'; ±0.35dB
Oto48
Monotonic
Oto 72
l.5dB Steps,
Oto 54
Accuracy '" ±O,7dB
Full Range
Monotonic
3.OdB Steps,
Accuracy .; ±1.4dB
Oto 66
Full Range
Monotonic
0.375
Unia
Oto48
o to 48
Oto 78
o to 85.S
Ot042
Oto 72
Oto S4
Ot048
Full Range
dB min
Full Range
Ot060
Full Range
Ot060
Full Range
Ot060
Full Range
Ot048
Full Range
dB min
Full Range
CoDditionllComments
dB min
Full Range is from 0 to 88.SdB
6.0dB Steps;
Accuracy >IIi; ±2.7dB
Monotonic
GAIN ERROR
o to 72
±O.I
±0.15
±0.15
±0.20
dB max
VIN INPUT RESISTANCE
(PIN IS)
9/11/15
9/11115
7/11/18
7/11/18
kG min/typ/max
RFS INPUT RESISTANCE
(PIN 16)
9.3/1U/15.7 '9.3/11.5115.7
7.3111.5/18.8 '7.3/11.5/18.8
2.4
0.8
±l
2.4
0.8
±10
2.4
0.8
±I
2.4
0.8
±10
V min
V max
#lA·max
0
0
350
175
10
3
0
0
500
250
10
4.5
0
0
350
175
10
3
0
0
500
250
10
4.5
nsmin
nsmin
nsmin
nsmin
nsmin
tJSmin
+5
I
500
+5
4
1000
+5
I
500
+5
4
1000
mAmax
/lA max
DIGITAL INPUTS
Vm (Input High Yoltage)
VIL (Input Low Voltage)
Input Leakage Current
SWITCHING CHARACTERISTICS'
tes
teH
tWR
tos
tOH
tRFSH
POWER SUPPLY
VOO
100
k{l rnin/typ/max
Digital Inputs = VDD
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
Data Valid to Write Setup Time
Data Valid to Write Hold Time
Refresh Time
V
Digital Inputs = Vrn or VIL
Digital Inputs = OV or VDD. See Figurt: 7.
NOTE
I Sample tested at +2SoC to ensure compliance.
SpeculCations Sllbject to change without notice.
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and are not subject to test.
VOD -- +SV VJN -- -lOY de except where stated VPINI -- Vpg.{2 -- OV output amplifier ADS44 except where stated.
AD7111UC/U GRADES
= TmiD' T_
Parameter
TA = 2SoC
TA
DC Supply Rejection. 6Gain/LlVoo
Propagation Delay
0.001
3.0
0.005
4.5
Digital to Analog Glitch Impulse
100
Output Capacitance. Pin 1
Input Capacitance. Pin 15 and Pin 16
Feedthrough at 1kHz
Total Hanoonic Distortion
Output Noise Voltage Density
Digital Input Capadtance
185
7
-94
-91
70
7
SpecificatiODS subject to mauge without Dotic:e.
2-184 DIGITAL-TO-ANALOG CONVERTERS
AD711IK/BIT GRADES
TA = Tmin, Tmu
TA = +2SOC
0.001
3.0
0.005
4.5
Units
dB per" max
Ilsmax:
100
-
nV secs typ
185
7
185
7
-92
-91
70
7
185
7
-68
-91
70
7
pFmax:
pFmax
dB max
dB typ
nV/YHzmax
pFmax
-91
70
7
6VOO = ±lO%.lnput Code = 00000000
Full Scale Change Measured from
Wit going high. CS = OV.
-
-72
Conditions/Comments
Measured with ADLHOO32CG as Output
Amplifier for Inpu t Code Transition
10000000 to 00000000.
Cl of Figure 1 is OpF
Feedthrough is also determined by circuit
layout (see Figure 4).
VIN .. 6V nns at 1kHz
In(:ludes ADS44 Amplifier Noise
AD7111
ABSOLUTE MAXIMUM RATINGS·
+ 2SOC unless otherwise noted)
(TA =
VDD (to DGND) . . . . . . .
VIN (to AGND) . . . . . .. .
Digital Input Voltage to DGND
Output Voltage (Pin I) to AGND .
VREF to AGND .
AGND to DGND . . . . • . . .
DGND to AGND . . . . . . . .
Power Dissipation (Any Package)
To +7SoC . . . • . . .
Derates above + 7SOC by
. . . . . . . . . . +7V
. . . . . . • .. +35V
-O.3V to VDD +O.3V
-O.3V to VDD
. . ±35V
.0 to VDD
.0 to VDD
450mW
6mWI"C
Operating Temperature Range
Commercial (K, L Versions)
Industrial (8, C Versions)
Extended (T, U Versions)
Storage Temperature . . • .
Lead Temperature (Soldering, 10secs)
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
TERMINOLOGY
RESOLUTION, Nominal change in attenuation when moving
between two adjacent codes.
MONOTONICITY, The device is monotonic if the analog ou tput decreases (or remains constant) as the digital code increases.
FEEDTHROUGH ERROR, That portion of the input signal
which reaches the output when all digital inputs are high. See
section on Applications.
OUTPUT LEAKAGE CURRENT, Current which appears on
the loUT terminal with all digital inputs high.
TOTAL HARMONIC DISTORTION, A measure of the harmonics introduced by the circuit when a pure sinusoid is applied to the input. It is expressed as the harmonic energy
divided by the fundamental energy at the output.
ACCURACY, The difference (measured in d8) between the
ideal transfer function as listed in Table I and the actual transfer function as measured with the device.
o to +70°C
- 250C to + 850C
- 55°C to + 125°C
-65°C to + 150°C
. . . . . +300°C
WARNING!
~
~~=:
DIGITAL TO ANAWG GLITCH IMPULSE, The amount of
charge injected from the digital inputs to the analog output
when the inputs change state. This is normally specified as
the area of the glitch in either pA-Secs or nV-Secs depending
upon whether the glitch is measured as a current or voltage
signal. Glitch impulse is measured with VIN =AGND.
PROPAGATION DELAY, This is a measure of the internal
delays of the circuit and is defined as the time from a digital
input change to the analog output current reaching 90% of its
final value.
WRITE CYCLE TIMING DIAGRAM
... I
I~IIDO
~
CHIP
\.
sruCr
--
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES
MEASURED FROM 1'"' TO 9O%OF "00. Vob
"+6V,r,'"tr-2Onf,
2. TIMING MEASUREMENT REFERENCE LEVEL
lIDo
IS VJH
+ VJL
2
Voo
DATA IN
(00-071
OUTPUT CAPACITANCE, Capacitance from loUT to ground.
PIN CONFIGURATIONS
LCCC
DIP
~
~ j ~ I :::
3212019
.., ,
,,
DGND 4
18 V DD
17M
D7(M$B) 5
AD7111
NC 6
TOP VIEW
INot to Scale)
06 7
05.
16 NC
15
CS
14 DOILSB)
910111213
g S
~
S 15
NC = NOCONNECT
DIGITAL-TO-ANALOG CONVERTERS 2-185
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
The AD7111 consists of a 17-bit R-2R CMOS multiplying
DIA converter with extensive digital logic. The logic translates the 8-bit binary input into a 17-bit word which is used
to drive the D/A converter. Input data on the D7-DO bus is
loaded into the input data latches using CS and WR control
signals. The rising edge of WR latches the inpu t data and initiatesthe internal data transfer to the decoder. A minimum
time tRFSH, the refresh time, is required for the data to propagatf" through the decoder before a new data write is
attempted.
that the attenuation step size at any point is consistent with
the step size guaranteed for monotonic operation at that
point.
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows a simplified circuit of the DIA converter
section of the AD7111 and Figure 3 gives an approximate
equivalent circuit.
The current source ILEAKAGE is composed of surface and
junction leakages and as with most semiconductor devices,
approximately doubles every 10° C-see Figure 11. The resistor
Ro as shown in Figure 3 is the equivalent output resistance of
the device which varies with input code (excluding all O's
code) from 0.8R to 2R. R is typically 11kn-. COUT is the
capacitance due to the N channel switches and varies from
about 60pF to 185pF depending upon the digital input. For
further information on CMOS multiplying DI A converters
refer to "Application Guide to CMOS Multiplying D/A converters" which is available from Analog Devices, Publication Number G479-15-8/78.
The transfer function for the circuit of Figure 1 is given by:
Vo = -VIN 10 exp _ 0.375 N
20
I:~I
or
dB=-0.375N
Where 0.375 is the step size (resolution) in dB and N is the
input code in decimal for values 0 to 239. For 240..;No;;;;255
the output is zero. Table I gives the output attenuation
relative to OdB for all possible input codes.
V,N
The graphs on the last page give a pictorial representation of
the specified accuracy and monotonic ranges for all grades of
the AD7111. High attenuation levels are specified with less
accuracy than low attenuation levels. The range of monotonic
behavior depends upon the attenuation step size used. For
example, the AD7111L is guaranteed monotonic in 0.375dB
steps from 0 to -54dB inclusive and in 0.75dB steps from 0
to -72dB inclusive. To achieve monotonic operation over the
entire 88.5dB range it is necessary to select input codes so
"F.
~~~+-~+-~~~~-4-~---oOOT
~~~-;'~~~-~--~----~AGND
SWITCH DRIVERS
Flgure 2. Simplified D/A Circuit of AD7111
.--"'--.....--....-<1>----<> loUT
CoUT
iiRo---(13)
~----~----..............--OAGND
gIVIN, N) IS THE THEVENIN EQUIVALENT VOLTAGE GENERATOR
DUE TO THE INPUT VOLTAGE VIN. THE BINARY ATTENUATION
FACTOR N AND THE TRANSFER FUNCTION OF THE R·2R LADDER.
Figure 3. Equivalent Analog Output Circuit of AD711.1
Figure 1. Typical Circuit Configuration
......
D7-04 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
OlDl
0110
0111
0.0
6.0
12.0
18.0
24.0
30.0
36.0
42.0
0.375
6.375
12.375
18.375
24.375
30.375
36.375
42.375
0.75
6.75
12.75
18.75
24.75
30.75
36.75
42.75
1.125
7.125
13.125
19.125
25.125
31.125
37.125
43.125
1.5
7.5
13.5
19.5
25.5
31.5
37.5
43.5
1.875
7.875
13.875
19.875
25.875
31.875
37.875
43.875
2.25
8.25
14.25
20.25
26.25
32.25
38.25
44.25
2.625
8.625
14.625
20.625
26.625
32.625
38.625
44.625
3.0
9.0
15.0
21.0
27.0
33.0
39.0
45.0
3.375
9.375
15.375
21.375
27.375
33.375
39.375
45.375
3.75
9.75
15.75
21.75
27.75
33.75
39.75
45.75
4.125
10.125
16.125
22.125
28.125
34.125
40.125
46.125
4.5
10.5
16.5
22.5
28.5
34.5
40.5
46.5
4.875
10.875
16.875
22.875
28.875
34.875
40.875
46.875
5.25
11.25
17.25
23.25
29.75
35.25
41.25
47.25
5.625
11.625
17.625
23.625
29.625
35.625
41.625
47.625
1000
1001
10lD
1011
48.0
54.0
60.0
66.0
48.375
54.375
60.375
66.375
48.75
54.75
60.75
66.75
49.125
55.125
61.125
67.125
49.5
55.5
61.5
67.5
49.875
55.875
61.875
67.875
50.25
56.25
62.25
68.25
50.625 51.0
56.625 57.0
62.625 63.0
68.625 69.0
51.375
57.375
63.375
69.375
51.75
57.75
63.75
69.75
52.125
58.125
64.125
70.125
52.5
58.5
64.5
70.5
52.875
58.875
64.875
70.875
53.25
59.25
65.25
71.25
53.625
59.625
65.625
71.625
1100
1101
1110
1111
72.0
78.0
84.0
72.375 72.75
78.375 78.75
84.375 84.75
13.875 74.25
79.875 80;25
85.875 86.25
74.625 75.0
80.625 81.0
86.625 87.0
75.375 75.75
81.375 81.75
87.375 87.75
76.875 77.25
82.875 83.25
88.875 89.25
77.625
83.625
89.625
73.125 13.5
79.125 79.5
85.125 85.5
76.125 76.5
82.125 82.5
88.125 88.5
MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE
Table I. Ideal Attenuation in dB
2-186 DIGITAL-TO-ANALOG CONVERTERS
lIS.
Input Code
Applications Information - AD7111
DYNAMIC PERFORMANCE
The dynamic perfonnance of the AD7111 will depend upon
the gain and phase characteristics of the ou tpu t amplifier,
together with the optimum choice of PC board layout and
decoupling components. Figure 4 shows a printed circuit layout which minimizes feedthrough from YIN to the output in
multiplying applications. Circuit layout is most important if
the optimum perfonnance of the AD7111 is to be achieved.
Most application problems stem from either poor layout,
grounding errors, or inappropriate choice of amplifier.
"jb
OUTPUT
JVO 0 ...... PIN 1
OP.AMP
~--@?;;-
-- -v"n
- -
INPUT~
_
_
AGND
DOND
DIGITAL
INPUTS
LAVOUT SHOWS COPPER SIDE Ii.•.• BOTTOM VIEWI
GAIN TRIM RESISTORS R1 AND R20F fiGURE 1
ARE NOT INCLUDED.
Figure 4. Suggested Layout for AD7111 and Op-Amp
It is recommended that when using the AD7111 with a high
speed amplifier, a capacitor (C1) be connected in the feedback
path as shown in Figure 1. This capacitor, which should be
berween 30pF and SOpF, compensates for the phase lag introduced by the output capacitance of the D/A converter.. Figures
Sand 6 show the perfonnance of the AD7111 using the
ADS17, a fully compensated high gain superbeta amplifier,
and the ADS44, a fast FET input amplifier. The perfonnance
without C1 is shown in the middle trace and the response with
C1 in circuit is shown in the bottom trace.
C1 =OpF
VaUT
Cl.,47pF
Your
5v
20"S
DATA CHANGE FROM SOH to DOH
Figure 5. Response of AD7111 with AD517
Cl =OpF
Cl = 47pF
DATA CHANGE FROM SOH TO OOH
Figure 6. Response of AD7111 with AD544
In conventional CMOS D/A converter design parasitic capacitance in the N-channel D/A converter switches can give rise to
glitches on the D/A converter output. These glitches result
from digital feed through. The AD 71 11 has been designed to
minimize these glitches as much as possible.
For operation beyond 2S0kHz, capacitor C1 may be reduced
in value. This gives an increase in bandwidth at the expense of
a poorer transient response as shown in Figures 6 and 12. In
circuits where C1 is not included the high frequency roll-off
point is primarily detennined by the characteristics of the
output amplifier and not the AD7111.
Feedthrough and absolute accuracy are sensitive to output
leakage current effects. F or this reason it is recommended that
the operating temperature of the AD7111 be kept as close to
2SoC as is practically possible, particularly where the device's
perfonnance at high attenuation levels is important. A typical
plot of leakage current vs. temperature is shown in Figure 11.
Some solder fluxes and cleaning materials can fonn slightly
conductive films which cause leakage effects berween analog
input and output. The user is cautioned to ensure that the
manufacturing process for circuits using the AD7111 does not
allow such films to form. Otherwise the feedthrough, accuracy
and maximum usable range will be affected.
STATIC ACCURACY PERFORMANCE
The D/A converter section of the AD7111 consists of a 17-bit
R-2R type converter. To obtain optimum static perfonnance
at this level of resolution it is necessary to pay great attention
to amplifier selection, circuit grounding, etc.
Amplifier input bias current results in a dc offset at the output
of the amplifier due to the current flowing through the feedback resistor R FB . It is recommended that an amplifier with
an input bias current of less than 10nA be used (e.g., ADS17
or ADS44) to minimize this offset.
Another error arises from the output amplifier's input offset
voltage. The amplifier is operated with a fixed feedback resistance, but the equivalent source impedance (the AD7111
output impedance) varies as a function of attenuation level.
This has the effect ofvarying the "noise" gain of the amplifier,
thus creating a varying error due to amplifier offset voltage.
It is recommended that an amplifier with less than SOJ.lYof
input offset be used (such as the ADS 17 or AD OP-07) in
dc applications. Amplifiers with higher offset voltage may
cause audible "thumps" in ac applications due to dc output
changes.
The AD7111 accuracy is specified and tested using only the
internal feedback resistor. Any Gain Error (i.e., mismatch of
RFB to the R-2R ladder) that may exist in the AD7111 D/A
converter circuit results in a constant attenuation error over
the whole range. The AD7111 accuracy is specified relative
to OdB attenuation, hence "Gain" trim resistors-R1 and R2
in Figure 1-can be used to adjust YO UT = YIN precisely (i.e.,
OdB attenuation) with input code 00000000. The accuracy
and monotonic range specifications of the AD7111 are not
affected in any way by this gain trim procedure. For the
AD7111L/C/U grades, suitable values for R1 and R2 of
Figure 1 are R1 = soon, R2 = 180n; for the K/BIT grades
suitable values are R1 = 1000n, R2 = 270n. For additional
infonnation on gain error the reader is referred to Application
Note "Gain Error and Gain Temperature Coefficient of CMOS
Multiplying DACs" by Phil Burton available from Analog
Devices Inc., Publication Number E630-10-6/81.
DIGITAL-TO-ANALOG CONVERTERS 2-187
Typical Performance Characteristics
LD
1
, tOO
1
=+5V
r-
-WF!=OV
I
,.
/
t
~
/
00.0 t
•. t
V
+2
,/
V
/
.
26
,
/ \
/
s'oo
TA=+WC
~ APPLIED TO ALL DATA INPUTS
•..
I
VoN.!tOV
OATA INPUT 11t,XXXX
$
tOO
75
TEMPERATURE
Figure ". Output Leakage Current VB. Temperature
+3
.. t=1;
Ii
+4
I
O C+tiV
..-..
j
j.../
J--.,
-.......
\
\ ~~7PF~
\
\
VoD -+5V
,
1\
c'l, I J
VJN=lYrml
Figure 7. Typical Supply Current vs. Logic Input Level
+O.4r--,---,,--,-...,-..,.-..,.--r--r-.,--...,.,
A
AO~
".We
f--IDATA INPUT CODE" oooooooo
INPUT VOLTAGE - Volb
~
t26
_·c
TA"'+2!i"C
."
~~"'47PF
§-O.2
\
/\
\
,
~
\
\
,
-0Af--f--f--j--j--+--+--+--+-+---H
·to
\
-•• f--f--f--j---+--+--+--+--I--+---H
tOO
12
24
\
tM
tOOk
21
FREQUENCY - Hz
ATTENUATION - dB
Figure 8. Typical Attenuation Error for 0.75d8 Steps
.
t
tr-
-
~ ::::::- t-....
VoD ..1+6V
,
TA"'+70"e:a
~
i--
3
TA-.j.l2!i"C
Figure 12. Frequency Response with AD544 and AD517
Amplifiers
~7C
'"I"
\
.
.8V~ I
_~CODE"
00000000
T,,'"+25"C
"-
,"\.
V
\,
-tOO
tOk
tOO
to
Figure 9. Typical Attenuation Error for 3d8 Steps v&
Temperature
MONOTONICITV FOR 1.5dB ATTENUATION STEPS
\\.\\.\.~
\\.'
\.\.\.O.75dBATTENUATIONSTEPS
f// 0.37IidBATTENUATIONSTEPS/////11
.
tOOk
. . .t
FREOUENCY - Hl
ATTENUATION - dB
UUUUl
/
/
~
7
'h
J
C1" 47pF
\.\.'
\\.'
\\.\
...
Figure 13. Distortion VB. Frequency Using AD544
Amplifier
MONOTONICITY FOR t.setB ATTENUATION STEPS
O.15dB ATTENUATtoN STEPS
'// h 'II
~.376dBATTENUATIONSTEPSf,
+1.5H-+-I'-+-f--+-t--+--.t......;;Ir--=;i--If-+-f--++-I
. . '.OH-+-If-+--f--+-t--+--t----+-+-If-+-f--++-I
I""""
Y +o.sH-+-If-+-f--+-+--f--+---+-+-If-+-f--++-I
~ . t~t·~:·:·~·:·:·~~·:__:~·:·:~_:_:~~ ..... .
... -O. 17 r
···t7I'+-+-+-f-.F4-..,1-- ......;
o -- -- - - - - - - - - - - -O.171>o+-+-~"'''''''....r..-...j.,.,."jI--''''''''!
....... 1-0
-
- -
-
--
-- -
- -
~
18M30384248
ATTENUAlION - dB
"
.. "
Figure 10. Accuracy Specification for K/8/T Grade Devices
at TA =+2!f'C
2-188 DIGITAL·TO·ANALOG CONVERTERS
to
"
..
54
..
1487
ATTENUATION - dB
Figure 14. Accuracy Specification for LlC!U Grade Devices
at TA = +2!f'C
LC2MOS
8-Bit OAC with Output Amplifier
A07224 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
8-Bit CMOS DAC with Output Amplifier
Operates with Single or Dual Supplies
Low Total Unadjusted Error:
Less than 1'LSB Over Temperature
....P-COmpatible with Double Buffered Input
Standard 18-Pin DiPs and 20-Terminal Surface
Mount Packages
AD7224 FUNCTIONAL BLOCK DIAGRAM
II
GENERAL DESCRIPTION
The AD7224 is a precision 8-bit, voltage-output, digital-to-analog
converter with output amplifier and double buffered interface
logic on a monolithic CMOS chip. No external trims are required
to achieve full specified performance for the part.
The double buffered interface logic consists of two 8-bit registersan input register and a DAC register. Only the data held in the
DAC register determines the analog output of the converter.
The double buffering allows simultaneous update in a system
containing multiple AD7224's. Both registers may be made
transparent under control of three external lines, CS, WR and
LDAC. With both registers transparent, the RESET line functions
like a zero override; a useful function for system calibration
cycles. All logic inputs are TTL and CMOS (5V) level compatible
and the control logic is speed compatible with most 8-bit
microprocessors.
Specified performance is guaranteed for input reference voltages
from + 2V to + 12.5V when using dual supplies. The part is
also specified for single supply operation using a reference of
+ lOY. The output amplifier is capable of developing + lOY
across a 2kO load.
The AD7224 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
PRODUCT HIGHLIGHTS
1. DAC and Amplifier on CMOS Chip:
The single-chip design of the 8-bit DAC and output amplifier
is inherently more reliable than multi-chip designs. CMOS
fabrication means low power consumption (35mW typical
with single supply).
2. Low Total Unadjusted Error:
The fabrication of the AD7224 on Analog Devices Linear
Compatible CMOS (LC2MOS) process, coupled with a novel
DAC switch-pair arrangement, enables an excellent total
unadjusted error of less than 1LSB over the full operating
temperature range.
3. Single or Dual Supply Operation:
The voltage-mode configuration of the AD7224 allows operation
from a single power supply rail. The part can also be operated
with dual supplies giving enhanced performance for some
parameters.
4. Versatile Interface Logic:
The high speed logic allows direct interfacing to most microprocessors. Additionally, the double buffered interface enables
simultaneous update of the AD7224 in multiple DAC systems.
The part also features a zero override function.
ORDERING INFORMATIONl
Total
Unadjusted
Error (LSB)
±2
±!
±2
±!
Temperature Range and Package Options"
3
Oto +70"C
- 2SOC to + 85°C
- 55°C to + 125°C
Plastic DIP (N.18) Hennetic DIP (Q-18) Hermetic DIP (Q.18)
AD7224KN
AD7224LN
AD7224BQ
AD7224CQ
PLCC' (P.20A)
AD7224TQ
AD7224UQ
LCCCs (E·20A)
AD7224KP
AD7224LP
AD7224TE
AD7224UE
NOTES
'To order MlL-STD-883 processed parts, add 1883B to psrt number.
Contact your local sales office for military dara sheet.
2See Section 14 for package outline information.
'Also available in SOIC psckage (AD7224KR·I).
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadles. Ceramic Chip Carrier.
DIGITAL-TO-ANALOG CONVERTERS 2-189
SPECIFICATIONS
DUAL SUPPLY
= l1.4V to 1&.5V; Vss = -5V ± 10%; AGND = DGND = OV; VREF = +2V to Woo -4V)1
unless otherwise slated). All specifications Tmin to T.... unless otherwise noted.
(VIII
Parameter
R,B,T
Versions'
L,C,U
Versions
Units
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Fnil Scale Error
Full Scale Temperature Coefficient
Zero Code Error
Zero Code Error Temperature Coefficient
8
±Z
±1
±1
±3/Z
±ZO
±30
±SO
8
±1
±lIZ
±1
±1
±20
±20
±30
Bits
LSBmax
LSBmax
LSBmax
LSBmax
ppml"Cmax
mVmax
IJ.VFCtyp
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance'
2to(Voo -4)
8
100
Zto(Voo -4)
8
100
Vmm to V""",
kOmin
pFmax
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance'
Input Coding
Z.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
V min
V max
ILAmax
pFmax
Conditions/Comments
Voo = + ISV ± S%, VREF = + 10V
Guaranteed Monotonic
Voo = 14Vto 16.5V, VREF = + IOV
Occurs when DAC is loaded with alll's.
VIN=OVorVoo
DYNAMIC PERFORMANCE
Voltage Output Slew Rate'
Voltage Output Settling Time'
Positive FuJI Scale Change
Negative Full Scale Change
Digital Feedthrough
Minimum Load Resistance
2.S
2.5
V/lJ.smin
S
7
SO
2
S
7
SO
2
IJ.smax
IJ.smax
nVsecstyp
knmin
VREF = + IOV; Settling Time to ± 1/2LSB
VREF = + 10V; Settling Time to ± 1I2LSB
VREF = OV
VOUT = +10V
POWER SUPPLIES
VooRange
VssRange
11.4116.S
4.S/S.5
11.4116.S
4.S/S.S
VonmIV.....
VonmIV""",
For Specified Performance
ForSpecifiedPenormance
4
6
4
6
mAmax
mAmax
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
3
S
3
S
mAmax
mAmax
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
ISO
200
150
ZOO
nsmin
nsmin
Chip Select/Load DAC Pulse Width
ISO
200
ISO
200
nsmin
nsmin
WriteIReset PuJse Width
0
0
0
0
nsmin
Chip Select/Load DAC to Write Setup Time
@2S"c
T_toTmax
0
0
0
0
nsmin
nsmin
Chip SelectlLoad DAC to Write Hold Time
@ZS"C
TmintoTmax
90
100
90
100
nsmin
nsmin
Data Valid to Write Setup Time
@25"C
T min to Tmax
10
10
10
10
nsmin
nsmin
Data Valid to Write Hold Time
100
@2SoC
Tmm toT"""
Iss
@ZsoC
Tmm to Tmax
SWITCHING CHARACTERISTICS34
'
tl
@2SoC
T_toTmax
t2
@2S"c
T_toTmax
t,
@2S"c
T_toT"""
nsmin
4
ts
to
NOTES
1Maximum possible reference voltage.
2Temperature ranges are as follows:
K, L Versions; 0 to +700c
B, eVersions; - 2SOC to + 8SOC
T, U Versions; -SSOC to + 12SOC
'Sample Tested at 2SOC by Product Assurance to ensure comp1iance.
4S witching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
2-190 DIGITAL-TO-ANALOG CONVERTERS
SINGLE SUPPLY
(Villi
= +15V ±5%; Vss=AGND=DGND=OV;
v.
= +lOV1
AD7224
unless oIII8Iwise stabId). All specificatiolls 1m to 1... unless othanvise noIIId.
Parameter
K,B,T
Versions2
L,C,U
Versions
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Differential Nonlinearity
8
:!:2
:!:I
8
:!:2
:!:I
Bits
LSBmax
LSBmax
Guaranteed Monotonic
REFERENCE INPUT
Input Resistance
Input Capacitance'
8
100
8
100
k,Omin
pFmax
Occurs when DAC is loaded with alii's.
DIGITAL INPUTS
Input High Voltage, V INH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance'
Input Coding
2.4
0.8
:!:l
8
Binary
2.4
0.8
:!:I
V min
V max
fJoAmax
pFmax
Binary
8
VIN
= OVorVoo
DYNAMIC PERFORMANCE
Voltage Output Slew Rate'
Voltage Output Settling Time'
Positive Full Scale Change
Negative Full Scale Change
Digital Feedthrough'
Minimum Load Resistance
2
2
V/fJosmin
5
20
50
2
5
20
50
2
fJosmax
fJosmax
nV sees typ
k,Omin
SettiingTimeto :!:I/2LSB
Settling Time to :!: 1/2LSB
VREF = OV
VOUT = +IOV
POWER SUPPLIES
VooRange
14.25/15.75
14.25/15.75
VminNnw<
For Specified Performance
4
4
6
6
mAmax
mAmax
Outputs Unloaded; VIN = VINLOrVINH
Outputs Unloaded; VIN = VINL or V tNH
100
@25°C
Tmin to Tmax
ABSOLUTE MAXIMUM RATINGS·
-O.3V, + 17V
VootoAGND
-O.3V, + 17V
Voo to DGND .
-O.3V, +24V
Voo to Vss . . .
AGNDtoDGND
-O.3V, Voo
Digital Input Voltage to DGND
-O.3V, Voo +O.3V
VREF to AGND . . . . . . . . .
-O.3V, Voo
VOUT to AGND I . . . . . . . .
Vss, Voo
Power Dissipation (Any Package) to + 75°C
450mW
. 6mW/oC
Derates above 75°C by .. .
Operating Temperature
Commerica! (K, L Versions)
o to +70°C
- 25°C to + 85°C
Industrial (B, C Versions)
Extended (T, U Versions)
- 55°C to + 125°C
Storage Temperature . . . .
- 65°C to + 150°C
Lead Temperature (Soldering, IOsecs)
+ 300°C
NOTES
'The outputs may be shorted to AGND provided that the power
dissipation of the package is not exceeded. Typically short
circuit current to AGND is 6OmA.
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RESET LDAC WR
CS
Function
H
L
L
L
Both Registers are Transparent
H
X
H
X
Both Registers are Latched
H
H
X
H
Both Registers are Latched
H
H
H
H
H
L
H
L
L
X
S
I
L
S
L
L
Input Register Transparent
L
Input Register Latched
H
DAC Register Transparent
H
DhC Register Latched
X
X
Both Registers Loaded
With All Zeros
H
H
H
Both Register Latched With
All Zeros and Output Remains
at Zero
L
L
L
Both Registers are Transparent
and Output Follows Input Data
I
H = High State, L = Low State, X
All control inputs are level triggered.
= Don't Care.
Table I. AD7224 Truth Table
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
DIGITAL-TO-ANALOG CONVERTERS 2-191
PIN CONFIGURATIONS
DIP
LCCC
v..
RESET
LDAC
11
J
3
1
20 19
•
..,
'' ,
AD7224
TOP VIEW
(Not to Scale)
DGND 6
DB7 (MSSI 7
DBO (LSBI
"
DB6 •
DB1
DB2
9
DB3
ill
Q
NC
,.
,.,.
!!
J
Ii
LDAC
LDAC
17 Wii
AGND 5
CS
J;
Ii
J;
V REF 4
Wii
PLCC
= NO CONNECT
,. ,.
:;
11
Q
"z
Wii
AD7224
CS
CS
TOP VIEW
(Not to Scale)
080 eLSB)
DB1
DB6
•
13
,. ,.
13
ill :;
c !! ~
Q
~
9
Ii! Q!II
Q
NC
DBO IlSB)
DB1
= NO CONNECT
11
VDD
cs--_....J
DAC
RESET - - - - - -.....
INPUT DATA
AD7224
Figure 1. Input Control Logic
V••
Figure 3. Unipolar Output Circuit
vo
NDTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES
MEASURED FROM 10% TO 90% of V DD•
t, = It = 20n8 OVER V •• RANGE
2. TIMING MEASUREMENT REFERENCE LEVEL IS
V1NH + V1NL
---r-
Figure 2. Write Cycle Timing Diagram
2-192 DIGITAL-TO-ANALOG CONVERTERS
Figure 4. Bipolar Output Circuit
LC2MOS Quad 8-Bit OAC
with Separate Reference Inputs
A07225 I
r.ANALOG
WDEVICES
FEATURES
Four 8-Bit DACs with Output Amplifiers
Separate Reference Input for Each DAC
....p Compatible with Double-Buffered Inputs
Simultaneous Update of All Four Outputs
Operates with Single or Dual Supplies
No User Trims Required
Skinny 24-Pin DiPs and 28-Terminal Surface
Mount Packages
AD722S FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7225 contains four 8-bit voltage output digital-ta-analog
converters, with output buffer amplifiers and interface logic on
a single monolithic chip. Each D/A converter has a separate
reference input terminal. No external trims are required to
achieve full specified performance for the part.
The double-buffered interface logic consists of two 8-bit registers
per channel-an input register and a DAC register. Control inputs
AO and Al determine which input register is loaded when WR
goes low. Only the data held in the DAC registers determines
the analog outputs of the converters. The double-buffering
allows simultaneous update of all four outputs under control of
LDAC. All logic inputs are TTL and CMOS (5V) level compatible
and the control logic is speed compatible with most 8-bit
microprocessors.
Specified performance is guaranteed for input reference voltages
from + 2V to + 12.5V when using dual supplies. The part is
also specified for single supply operation using a reference of
+ IOV. Each output buffer amplifier is capable of developing
+ IOV across a 2kO load.
offers increased reliability in systems using multiple converters.
Its pinout is aimed at optimizing board layout with all analog
inputs and outputs at one end of the package and all digital
inputs at the other.
2. Single or Dual Supply Operation:
The voltage-mode configuration of the AD7225 allows single
supply operation. The part can also be operated with dual
supplies giving enhanced performance for some parameters.
The AD7225 is fabricated on an all ion-implanted high-speed
Linear Compatible CMOS (LC2 MOS) process which has been
specifically developed to integrate high-speed digital logic circuits
and precision analog circuitry on the same chip.
3. Versatile Interface Logic:
The AD7225 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. The double-buffered
interface allows simultaneous update of the four outputs.
PRODUCT HIGHLIGHTS
1. DACs and Amplifiers on CMOS Chip:
The single-chip design of four g-bit DACs and amplifiers
allows a dramatic reduction in board space requirements and
4. Separate Reference Input for Each DAC:
The AD7225 offers great flexibility in dealing with input
signals with a separate reference input provided for each
DAC and each reference having variable input voltage
capability.
ORDERING INFORMATlON1
Total
Unadjusted
Error (LSB)
Oto +70"C
:t2
:tl
Plastic DIP (N-24) Hermetic DIP (Q-24) Hermetic DIP (Q-24)
AD7225KN
AD722SBQ
AD722STQ
AD722SUQ
AD722SLN
AD722SCQ
:t2
+1
PLCC3 (p-28A)
AD722SKP
AD722SLP
Temperature Range and Package Options2
- 2S"C to + 85°C
NOTES
'To order MIL-STO·883 processed parts, add 1883B to part number.
Contact your local sales office for military data sheet.
2See Section 14 for package outline information.
- 55°C to + 125°C
LCCC4 (E-28A)
AD722STE
AD722SUE
3PLCC: Plastic Leaded Chip Carrier.
4LCCC: Leadless Ceramic Chip Carrier.
DIGITAL-TD-ANALOG CONI/ERTERS 2-193
SPECIFICATIONS
DUAL SUPPLY
=
K,B
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full Scale Error
Full Scale Temp. Coeff.
Zero Code Error@2S"C
TmintoTfJIIIl[
Zero Code Error TempCoeff.
=
=
=
=
+2V 10 (Voo -4V)1
11.4V 10 16.5V; Vss
-5V ±10%; AGND
DGND
DV; VREf
unless othelWise stated). All specifications Tmin 10 T.... unless othelWise noted.
{VIJD
Venions2
±2
±I
±I
±I
±S
±2S
±30
±30
L,C
Versions'
TVersioD
VVersion
Vails
±2
±J
±I
±I
±S
±2S
±30
±30
±I
±112
±I
±112
±S
±IS
±20
±30
Bits
LSBmax
LSBmax
LSBmax
LSBmax
ppml"Ctyp
mVmax
mVmax
...Vl"Ctyp
-70
2to(Vo o -4)
II
100
60
-70
2 to (VOD -4)
II
100
60
-70
kfimin
pFmax
dB min
dB max
2.4
0.8
±I
8
Binary
2.4
0.8
±I
8
Binary
Vmin
V max
."A max
pFmax
ViI's min
±I
±1/2
±1
±112
±S
±IS
±20
±30
ConditiooslCnmmenls
Voo
~
+ ISV ± 5%, V REF
~
Guaranteed Monotonic
Voo=14VtoI6.SV,V REF = +IOV
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance'
ChanneI-to-Channei Isolation'
AC Feedthrougb'
2to(Voo -4)
II
100
60
-70
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, V INL
Input LeakageCurrent
Input Capacitance'
Input Coding
2.4
0.8
±I
8
Binary
2.4
0.8
±I
8
Binary
2.5
2.5
2.5
2.5
5
5
SO
SO
2
5
5
SO
SO
2
5
5
SO
SO
2
5
5
SO
SO
2
nVsecstyp
nVsecstyp
kfimin
11.4116.5
10
9
11.4/16.5
10
9
11.4116.5
12
10
11.4116.5
12
10
mAmax
mAmax
95
120
95
ISO
95
ISO
nsmin
nsmin
Write Pulse Width
0
0
0
0
0
0
nsmin
nsmin
Address to Write Setup Time
0
0
0
0
0
0
nsmin
Dsmin
Address to Write Hold Time
DYNAMIC PERFORMANCE
Voltage Output Slew Rate'
Voltage Output Settling Time'
Positive Full ScaleChange
Negative Full Scale Change
Digital Feedthrough'
Digital Crosstalk'
Minimum Load Resistance
POWER SUPPLIES
vooRimse
100
Iss
SWITCIDNGCHARACTERISTICS',4
t1
@2S"C
95
120
TmiotoTmd.
tu
@2S"C
0
0
TmmtoTmu:
t,
0
@2S"C
Tmin toT_
0
.
2to(Voo -4)
II
100
60
+ 10V
Vmin 10 Vmu
JJ.smax
.... maa
V",;,/V~
Occurs when each DAC is loaded with all I 'so
VREF = 10Vp-pSineWave@IOkHz
VREF ~ 10Vp-pSineWave@IOkHz
V1N=OVorVDD
VREF ~ + IOV;SettlingTimeto ± 1I2LSB
VREF = + 10V; Settling Time to ± 1I2LSB
Code transition all O's to all! 'so
Code transition all O's to aliI's.
VOUT= +IOV
For Specified Performance
Outputs Unloaded; V IN = V1NL or V INH
Outputs Unloadedj V IN =V INL or VINH
@2S"C
TIPin to Tmu:
70
70
70
70
90
90
90
nsmin
nsmin
Data Valid to Write Setup Time
90
@2S"C
Tmin to TIDIIJl
10
10
10
10
10
10
10
10
nsmin
nsmin
Data Valid to Write Hold Time
@2S"C
95
120
95
120
95
ISO
95
ISO
nsmin
nsmin
Load DAC Pulse Width
ts
to
Tmin to Tmax
NOTES
lMaximum possible reference voltage.
l-femperanuc ranges are as foDows:
K, L Versions; 0 to + 7f1>C
B. eVersions; - 2S"C to +8S"C
T, UVenions; -SS"Cto +12S"C
"Sample Tested at 2S"C to ensure COIDpJiance.
4Switcbing characteristics apply for single and. dual supply operation.
Specifications subiect to change without notice.
CAUTION
ESD (electrostatic discharge) sensltlve device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
2-194 DIGITAL-TO-ANALOG CONVERTERS
WARNING!
~
~~:::
SINGLE SUPPLY
(VIII = + 15V ± 5%, Vss = AGND = DGND = OV; VRfF = +lOVI
unless oIhelWise stated). All specifications TmiJ to T_ unless oIheIwise noled.
Parameter
K,B
Versions 2
VersiODs2
TVersion
UVersion
±2
±I
±I
±I
8
±2
±I
±I
±I
LSBmax
LSBmax
Guaranteed Monotonic
k!lmin
pFmax
dB min
dB max
Occurs when each DAC is losded with alll·s .
VREF = IOVp-pSineWave@IOkHz
VREF = 10Vp-pSineWave@IOkHz
AD7225
L,C
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Differential Nonlinearity
Bits
REFERENCE INPUT
Input Resistance
Input Capacitance3
Channel-la-Channel Isolation
11
100
11
100
11
100
11
100
60
60
60
60
AC Feedthrough'"
-70
-70
-70
-70
2.4
0.8
±I
8
Binary
2.4
0.8
±I
8
Binary
2.4
0.8
±I
8
Binary
2.4
0.8
±I
8
Binary
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, V1NL
Input Leakage Current
Input Capacitance3
Input Coding
V min
V max
!LA max
VIN
=
OVorVDD
pFmax
DYNAMIC PERFORMANCE
Voltage Output Slew Rate 3
Voltage Output Settling Time3
Positive Full Scale Change
Negative Full Seale Change
Digital Feedthrough'"
Digital Crosstalk'
Minimum Load Resistance
V/JLsmin
Settling Time to ± 1I2LSB
Settling Time to ± 1I2LSB
Code transition all O's to aliI's.
Code transition aU O's to all I '5.
VOUT= +lOV
5
7
50
50
2
5
7
50
50
2
5
7
50
50
2
7
50
50
2
..smax
.... max
nVsecstyp
nVsecstyp
kftmin
14.25/15.75
10
14.25/15.75
10
14.25/15.75
12
14.25/15.75
12
VmJnN~
For Specified Performance
mAmax
Outputs Unloaded; VIN = V JNL or V INH
POWER SUPPLIES
VDDRange
100
ABSOLUTE MAXIMUM RATINGS·
VootoAGND
VDotoDGND .
Voo to Vss . . .
AGNDtoDGND
Digital Input Voltage to DGND
VREF to AGND . . . . . . . . .
VoUTtoAGND I . . . . • . • .
Power Dissipation (Any Package) to + 75°C
Derates above 75°C by . . . . . . . . . •
Operating Temperature
Commercial (K, L Versions)
Industrial (B, C Versions)
-
-O.3V, + 17V
-O.3V, +17V
-O.3V, +24V
-O.3V,VDO
-O.3V, VOD
-O.3V, VOD
Vss, Voo
500mW
2.0mW/C
Extended (T, U Versions)
Storage Temperature
Lead Temperature (Soldering, 10secs)
- 55"C to + 125"C
- 65°C to + 150°C
+ 300°C
NOTES
'Outputs may he shorted to any voltage in the range Vss to VDO provided
that the power dissipation of the package is not exceeded. Typical short
circuit current for a short to AGND or Vss is SOmA.
"'Stress above those listed. under "Absolute Maximum Ratings" may cause pennanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
o to +70"C
25°C to + 85°C
PIN CONFIGURATIONS
DIP
:a ' ~
YREFC
VREFD
AGND
•
VOUTO
V""
AO
NC
A1
DGND 9
LDAC 10
DB2
DB3
J
~, 8
~ >
2. 27 26
25 VREFC
24
(MSB)IDB7 11
v.....,
23 AO
AD7225
TOP VIEW
INot to Scalal
ll========~.)
,. ,.
! II!Q ~
~
NC = NO CONNECT
13
"
Z
AD7225
TOP VIEW
22NC
(Not to Scale'
21 A1
20
12
DB5
2
1
.~
DB1
DB4
"
AGND 7
ViR
DB.
3
•
•
LOAC
(MSBI CB7
§
VREFa 5
YREFA
DGNO
D80{LSBI
I
> > > z
VOUTC
VOUTA
PLCC
LCCC
WR
19 DBOILSBI
WAc
IMSBIOB7
16 17 18
;;;
lilQ :;:
Q
Q
NC ,.. NO CONNECT
DIGITAL-TO-ANALOG CONVERTERS 2-195
•
CIRCUIT INFORMATION
500
D/ASECTION
(
...
The AD7225 contains four, identical, 8-bit voltage-mode digital-toanalog converters. Each D/A converter has a separate reference
input. The output voltages from the converters have the same
polarity as the reference voltages, allowing single supply operation.
A novel DAC switch pair arrangement on the AD7225 allows a
reference voltage range from +2V to + l2.5V on each reference
input.
-
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high-speed NMOS, single-pole, double-throw switches.
The simplified circuit diagram for channel A is shown in
Figure 1. Note that AGND is common to all four DACs.
y.. = loy
r:- t--y.. =ov
...
Voo=+16V
T,,-25"C
,..
VourA
2R
AGND
,.
•
----.,r---<--_-..
VOUT - Volt.
o-......
Figure 2. Variation of ISINK with Vour
Figure 1. DIA Simplified Circuit Diagram
The input impedance at any of the reference inputs is code
dependent and can vary from Hldl minimum to infinity. The
lowest input impedance at any reference input occurs when that
DAC is loaded with the digital code 01010101. Therefore, it is
important that the reference presents a low output impedance
under changing load conditions. The nodal capacitance at the
reference terminals is also code dependent and typically varies
from 15pF to 35pF.
Each VOUT pin can be considered as a digitally programmable
voltage source with an output voltage of:
.
VOUTX = Dx . VREFX
where Ox is fractional representation of the digital
input code and can vary from 0 to 2551256.
The output impedance is that of the output buffer amplifier.
OP·AMP SECTION
Each voltage mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. This buffer amplifier is
capable of developing + 10V across a 2kn load and can drive
capacitive loads of 3300pF.
The AD7225 can be operated single or dual supply; operating
with dual supplies results in enhanced performance in some
parameters which cannot be achieved with single supply operation.
In single supply operation 01ss = OV = AGND) the sink capability
of the amplifier, which is normally 4OO,..A, is reduced as the
output voltage nears AGND. The full sink capability of 1OO,..A
is maintained over the full output voltage range by tying Vss to
-5V. This is indicared in Figure 2.
Settling-time for negative-going output signals approaching
AGND is similarly affected by V ss. Negative-going settling-time
for single supply operation is longer than for dual supply operation.
Positive-going settling-time is not affected by Vss.
Additionally, the negative Vss gives more headroom to the
output amplifiers which results in better zero code performance
and improved slew-rate at the output, than can be obtained in
the single supply mode.
DIGITAL SECTION
The AD7225 digital inputs are compatible with either TTL or
5V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than InA. Internal
input protection is achieved by an on-chip distributed diode
between DGND and each MOS gate. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (VDD and DGND) as practically
possible.
INTERFACE LOGIC INFORMATION
The AD7225 contains two registers per DAC, an input register
and a DAC register. Address 1ines AO and Al select which
input register will accept data from the input port. When the
WR signal is LOW, the input latches of the selected DAC are
transparent. The data is latched into the addressed input register
on the rising edge of WR. Table I shows the addressing for the
input registers on the AD7225.
Only the data held in the DAC register determines the analog
output of the converter. The LDAC signal is common to all
four DACs and controls the transfer of information from the
input registers to the DAC registers. Data is latched into all
four DAC registers simultaneously on the rising edge of LDAC.
The LDAC signal is level triggered and therefore the DAC
Al
AO
Selected Input Register
L
L
H
H
L
H
L
H
DAC A Input Register
DAC B Input Register
DAC C Input Register
DAC D Input Register
Table I. AD7225 Addressing
2-196 DIGITAL-TO-ANALOG CONVERTERS
AD7225
registers may be made transparent by tying LDAC LOW (in
this case the outputs of the converters will respond to the data
held in their respective input latches). LDAC is an asynchronous
signal and is independent of WR. This is useful in many applications. However, in systems where the asynchronous LDAC
can occur during a write cycle (or vice versa) care must be taken
to ensure that incorrect data is not latched through to the output.
In other words, if LDAC is activated prior to the rising edge of
WR (or WR occurs during LDAC), then LDAC must stay
LOW for If; or longer after WR goes HIGH to ensure correct
data is latched through to the output. Table II shows the truth
table for AD7225 operation. Figure 3 shows the input control
logic for the part and the write cycle timing diagram is given in
Figure 4.
[iiAc - - - - - - - - - - - - - AD
TO INPUT
LATCH A
TO INPUT
AI
LArCH B
TO INPUT
LATCH C
TO INPUT
LATCH D
Figure 3. Input Control Logic
X'~-------------.v
-____________
=x~:::
I
WR LDAC Function
H
L
H
H
H
L
H
L
i
IH
L
No Operation. Device not selected
Input Register of Selected DAC Transparent
Input Register of Selected DAC Latched
All Four DAC Registers Transparent
(i.e. Outputs respond to data held in
respective input registers)
Input Registers are Latched
All Four DAC Registers Latched
DAC Registers and Selected Input Register
Transparent
Output follows Input Data for Selected Channel.
DA~t~~';.ES
ADDRESS
I
.
----:--:--r-~r·v
;.~~
-~..~~NOTES
1. ALL INPUT SIGNAL RISE AND FAU TIMES
MEASURED FROM 10% TO 90% of + 5V
t, = t, "" ZOns OVER VDD RANGE
2. TIMING MEASUREMENT REFERENCE LEVEL IS
VINH
+ VINL
--r-Table II. AD7225 Truth Table
3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EQ!iI: OF WR THEN
IT MUST STAY LOW fOR ta OR LONGER AFTER WR GOES HIGH.
Figure 4. Write Cycle Timing Diagram
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for each channel of the
AD7225, with the output voltage having the same positive polarity
as VREF • The AD7225 can be operated single supply (Vss =
AGND) or with positive/negative supplies (see op-amp section
which outlines the advantages of having negative Vss). Connections
for the unipolar output operation are shown in Figure 5. The
voltage at any of the reference inputs must never be negative
with respect to DGND. Failure to observe this precaution may
cause parasitic transistor action and possible device destruction.
The code table for unipolar output operation is shown in
Table III.
DAC Latch Contents
MSB
LSB
Analog Output
1111 1111
+VREF
(255 )
256
1000 0001
+VREF
( 129 )
256
1000 0000
+VREF
( 128 )
VREF
256 = +-2-
1I 1I
+VREF
( 127 )
256
0000 0001
+VREF
(2~6 )
01 1 I
0000 0000
OV
Table III. UnipolarCode Table
Figure 5. Unipolar Output Circuit
DIGITAL-TO-ANALOG CONVERTERS 2-197
•
BIPOLAR OUTPUT OPERATION
Each of the DACs of the AD7225 can be individually configured
to provide bipolar output operation. This is possible using one
external amplifier and two resistors per channel. Figure 6 shows
a circuit used to implement offset binary coding (bipolar operation)
with DAC A of the AD7225. In this case
Vour =
(1 + ~). (DAV
REP) -
1SV
'6k
+4V
f\
- o----f 1-+----1
- V
REFERENCE
INPUT
.
,
-4V
(~). (V
REP)
"DIGrrAL INPUTS OMITTED
FOR CLARITY
With Rl = R2
Your = (2DA -I)· VREF
where DAis a fractional representation of the
digital word in latch A. (0 ,,;; D A ,,;; 255/256)
Mismatch between RI and R2 causes gain and offset errors and,
therefore, these resistors must match and track over temperature.
Once again the AD7225 can be operated in single supply or
from positive/negative supplies. Table IV shows the digital code
versus output voltage relationship for the circuit of Figure 6
with Rl = R2.
.,
V~,o-----~--------------------,
R1, R2
Figure 7. Applying an AC Signal to the AD7225
GROUND MANAGEMENT AND LAYOUT
Since the AD7225 contains four reference inputs which can be
driven from ac sources (see AC REFERENCE SIGNAL section)
careful layout and grounding is important to minimize analog
crosstalk between the four channels. The dynamic performance
of the four DACs depends upon the optimum choice of board
layout. Figure 8 shows the relationship between input frequency
and channel-to-channel isolation. Figure 9 shows a printed circuit
board layout which is aimed at minimizing crosstalk and feedthrough. The four input signals are screened by AGND. VREF
was limited to between 2V and 3.24V to avoid slew rate limiting
effects from the output amplifier during measurements.
= 10k!! ±O.1%
-so
·DIGITAL INPUTS OMInED
-
FOR CLARITY
Figure 6. AD7225 Bipolar Output Circuit
..
-10
";' -60
r
~
DACLatcla Contents
MSB
LSB
so
Analog Output
11 I 1
+VREF
(127 )
128
1000 0001
+VREF
(1~8
1111
1000 0000
01 1 1
1111
0000 0001
0000 0000
)
OV
-VREF (
~=
TA
VOD
Vss
t--
+25"C
+15V
= -5V
~
V REF : 1.24V pop
-40
~
-30
20k
500k
SOIl
100k
200k
INPUT FREQUENCY - Hz
Figure 8. Channel-to-Channel Isolation
1~8
SYSTEM
)
( 127 )
-VREF 128
( 128 )
- VREF 128 = - VREF
Table IV. Bipolar (Offset BinarY) Code Table
PIN 1
VOUT B 0-----0-VOUTA
VsS~
VREFB
2-198 DIGITAL-TO-ANALOG CONVERTERS
~
VAEFA ~
AGND
DGND
AC REFERENCE SIGNAL
In some applications it may be desirable to have ac reference
signals. The AD7225 has multiplying capability within the upper
(Vnn - 4V) and lower (2V) limits of reference voltage when
operated with dual supplies. Therefore ac signals need to be ac
coupled and biased up before being applied to the reference
inputs. Figure 7 shows a sine wave signal applied to V~ ~.
For input signal frequencies up to 50kHz the output distortion
typically remains less than 0.1%. The typical3dB bandwidth
figure for small signal inputs is 800kHz.
~
(
GND
~VOUTC
....c>-o----o VOUT 0
~VDD
-0------0
V REF C
....c>-o----oVAEFD
--.... --....
-.... ----....
-0------0
~
. ...c>-o----o
-0-
~
MSB -0-
~LSB
-0-
000-
-0-
-0-
-0-
Figure 9. Suggested PCB Layout for AD7225. Layout
Shows Component Side (Top View)
1M
LC 2MOS
Quad 8-Bit D/A Converter
AD7226 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
Four a-Bit DACs with Output Amplifiers
Skinny 20-Pin DIPs and 20-Terminal
Surface Mount Packages
Microprocessor Compatible
TTUCMOS Compatible
No User Trims
Single Supply Operation Possible
AD7226 FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Process Control
Automatic Test Equipment
Automatic Calibration of Large System Parameters
e.g., Gain/Offset
GENERAL DESCRIPTION
The AD7226 contains four 8-bit voltage-output digital-to-analog
converters, with output buffer amplifiers and interface logic on
a single monolithic chip. No external trims are required to
achieve full specified performance for the part.
Separate on-chip latches are provided for each of the four D/A
converters. Data is transferred into one of these data latches
through a common 8-bit TTL/CMOS (SV) compatible input
port. Control inputs AO and Al determine which DAC is loaded
when WR goes low. The control logic is speed-compatible with
most 8-bit microprocessors.
Each D/A converter includes an output buffer amplifier capable
of driving up to SmA of output current. The amplifiers' offsets
are laser-trimmed during manufacture, thereby eliminating any
requirement for offset nulling.
Specified performance is guaranteed for input reference voltages
from + 2V to + I2.SV with dual supplies. The part is also specified
for single supply operation at a reference of + I OV.
The AD7226 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC 2MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
Vss
AGND
DGND
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching:
Since all four DACs are fabricated on the same chip at the
same time, precise matching and tracking between the DACs
is inherent.
2. Single Supply Operation:
The voltage mode conftglll"ation of the DACs allows the
AD7226 to be operated from a single power supply rail.
3. Microprocessor Compatibility:
The AD7226 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered.
4. Small Size:
Combining four DACs and four op-amps plus interface logic
into either a small, 0.3" wide, 20-pin DIP or a 20-terminal
surface mount package allows a dramatic reduction in board
space requirements and offers increased reliability in systems
using multiple converters. Its pinout is aimed at optimizing
board layout with all the analog inputs and outputs at one
end of the package and all the digital inputs at the other.
ORDERING INFORMATION l
Total
Unadjusted
Error (LSB)
Temperature Range and Package Options2, 3
Oto +70"C
- 2SOC to + 8S·C
Plastic DIP (N-20) Hermetic DIP (Q-20)
+2
AD7226KN
±2
PLCC4 (P-20A)
AD7226KP
AD7226BQ
- SSOC to + 12SOC
Hermetic DIP (Q-20)
AD7226TQ
LCCCs (E-20A)
AD7226TE
NOTES
ITo order MIL·STD-883, Class B processed parts, addl883B to part number.
Contact your local sales office for military data sheet. For U.S. Standard
Military Drawing (SMD), see DESC drawing #5962·87802.
2See Section 14 for package outline information.
'Also available in sorc package (AD7226KR).
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadles. Ceramic Chip Carrier.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
~
~~=:
D/G/TAL-TO-ANALOG CONVERTERS 2-199
SPECIFICATIONS
(Voo = l1.4V to 16.5V; Vss = -5V ±11l%; AGHO = OGHO = ov; V
DUAL SUPPLY
REF
=
unless otherwise stated). All specifications TMlN to TMAI( unless othelWise noted.
K,B, TVersions1
Units
8
±50
Bits
LSBmax
LSBmax
LSBmax
LSBmax
ppmI"Ctyp
mVmax
I1VI"Ctyp
2to(Voo -4)
2
65
300
VMIN to VMAX
kOmin
pFmin
pFmax
2.4
0.8
±I
8
Binary
V min
V max
I1Amax
pFmax
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full Scale Error
Full Scale Temperature Coefficient
Zero Code Error
Zero Code Error Temperature Coefficient
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance3
DIGITAL INPUTS
Input High Voltage, V INH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance
Input Coding
DYNAMIC PERFORMANCE
Voltage Output Slew Rate4
Voltage Output Settling Time4
Positive Full Scale Change
Negative Full Scale Change
Digital Crosstalk
Minimum Load Resistance
±2
±I
±I
±11/2
±20
±30
Conditions/Comments
Voo =
+ 15V ±
5%, ViUlF =
+ 10V
Guaranteed Monotonic
Voo = 14Vto 16.5V, VREF =
+ 10V
Occurs when each DAC loaded with all O's.
Occurs when each DACloaded withalll's.
VIN = OVorVoo
2.5
5
7
50
2
I1smax
I1smax
nVsecstyp
kfimin
VREF =
VREF =
+ IOV; Settling Time to ± 1/2LSB
Vom =
+ 10V
11.4116.5
13
11
VMlNNMAX
mAmax
mAmax
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH.
Outputs Unloaded; VIN = VlNLorVINH •
o
o
nsmin
nsmin
10
10
nsmin
nsmin
90
100
nsmin
nsmin
10
10
nsmin
nsmin
150
200
nsmin
nsmin
POWER SUPPLIES
VooRange
100
Iss
SWITCHINGCHARACTERISTICS4 ,5
Address to Write Setup Time, tAS
@25°C
TMlNto TMAX
Address to Write Hold Time, tAH
@25°C
TMlNto TMAX
Data Valid to Write Setup Time, tos
@25°C
TMlNtoTMAX
Data Valid to Write Hold Time, tOH
@25°C
TMlNtoTMAX
Write Pulse Width, tWR
@25°C
TMINtoTMAX
zv to (V... -4V)1
NOTES
1Maximum possible reference voltage.
'Temperature rangea are as follows:
K Version; 0 to + 7O'C
B Version; - 25"C to + 8S"C
T Version; - SS"C to + 12S"C
'Guaraoteed by design.. Not production tested.
'Sample Tested .at 2S"C to ensure compliance.
'Switching Characteristics lipply for both single and dual supply operation.
Specifications subject to cbaoge without notice.
2-200 DIGITAL-TO-ANALOG CONVERTERS
+ 10V; Settling Time to ± 1I2LSB
SINGLE SUPPLY
AD7226
= +15V ±5%; Vss = AGND =DGND= OV; VREf = +lov l
unless otherwise stated). All specifications TMIN to Trw unless otherwise noted.
(VIII
Parameter
K,B, TVersions'
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Differential Nonlinearity
8
±2
±I
Bits
LSBmax
LSBmax
Guaranteed Monotonic
2
65
300
kOmin
pFmin
pFmax
OccurswheneachDACloadedwithalIO's.
Occurs when each DAC loaded with alii's.
REFERENCE INPUT
Input Resistance
Input Capacitance3
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance
Input Coding
2.4
0.8
±I
8
Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate'
Voltage Output Settling Time'
Positive Full Scale Change
Negative Full Scale Change
Digital Crosstalk
Minimum Load Resistance
V min
V max
....Amax
pFmax
V IN = OVorVoo
...,smax
Settling TinIe to ± 1I2LSB
Settling TinIe to ± 1I2LSB
2
5
20
50
2
POWER SUPPLIES
VooRange
.... smax
nVsecstyp
kOmin
VOUT= +IOV
14.25 to 15.75
13
100
For Specified Performance
OutputsUnloaded;V IN = VINLOrVINH
ABSOLUTE MAXIMUM RATINGS·
VootoAGND
Vooto DGND
Vss to AGND .
Vss to DGND .
Voo to Vss . .
AGNDtoDGND
Digital Input Voltage to DGND
V REF to AGND . . . . . . . . .
VoUTtoAGND 1 • • • • • • • •
Power Dissipation (Any Package) to
Derates above 75°C by .
Operating Temperature
Commerical (K Version)
-0.3V, +17V
-0.3V, + 17V
-7V,V oo
-7V, Voo
-O.3V, +24V
-O.3V, Voo
-O.3V, Voo+0.3V
-0;3V, Voo
Vss, Voo
+ 75°C
. 500mW
2.0mW/oC
- 25°C to + 85°C
- 55°C to + 125°C
-65°C to + 150°C
. . . +300°C
Industrial (B Version) .
Extended (T Version) .
Storage Temperature .
Lead Temperature (Soldering, 10secs)
NOTES
'Outputs may be shorted to AGND provided that the power
dissipation of the package is not exceeded. Typically short
circuit current to AGND is 60mA.
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
PIN CONFIGURATIONS
DIP
PLCC
LCCC
.,
" ) us "j
;: J
~
•
..,,
Voo
,,
A.
A1
AGND 5
Wi!
DGNO 6
080 (LSB)
DB7(MSB) 7
AD7226
TOP VIEW
(Not to Scalel
OB8 •
DB2
OB4
910111213
m~
! 9!
1
2'
,.
0
Voo
18 Voo
17 AD
AD7226
16 Al
TOP VIEW
INot to Scale)
15
Wii
14 DBOILSBI
DB1
2
OB8
AD
A1
,.
•
•"
11
is ill ;
12
,.
:.I
;;
Wi!
DBOILSBI
" " " " "
DIGITAL-TO-ANALOG CONVERTERS 2-201
•
INTERFACE LOGIC INFORMATION
Address lines AO and Al select which DAC will accept data
from the input port. Table I shows the selection table for the
four DACs with Figure 1 showing the input control logic. When
the WR signal is LOW, the input latches of the selected DAC
are transparent and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high the analog outputs remain
at the value corresponding to the data held in their respective
latches.
AD7226 Control Inputs
Al
AO
WR
AD7226
Operation
H
X
X
No Operation
Device Not Selected
L
L
L
DACA Transparent
L
L
DAC A Latched
S
L
H
DAC B Transparent
L
H
DAC B Latched
L
H
L
DAC C Transparent
H
L
DAC C Latched
H
H
DAC D Transparent
H
H
DAC D Latched
S
L
S
L
S
Unipolar Output Operation
This is the basic mode of operation for each channel of the
AD7226, with the output voltages having the same positive
polarity as + VREF • The AD7226 can be operated single supply
(Vss = AGND) or with positiVe/negative supplies (see op-amp
section which outlines the advantages of having negative V 88)'
Note that the voltage at VREF must never be negative with respect
to DGND in order to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in Figure 3.
L = Low State, H = High State, X
= Don't Care
Figure 3. Unipolar Output Circuit
Table I. AD7226 Truth Table
Bipolar Output Operation
Each of the DACs of the AD7226 can be individually configured
to provide bipolar output operation. This is possible using one
external amplifier and two resistors per channel. Figure 4 shows
a circuit used to implement offset binary coding (bipolar operation)
with DAC A of the AD7226. In this case
TO LATCH A
TO LATCH B
VOUT =
TOLATCHC
(1 + ~). (D
A
VREP)
-
(~). (V
REF)
WithRI = R2
Vour = (2DA -I)' VREF
lOLA1CHD
where DAis a fractional representation
of the digital word in latch A.
Figure 1. Input Control Logic
xv,.
DATA
....
Y1NL
fk=:~
tAS
x::J
ADDRESS
I
I
iiiii
'\
I
)C~~
Mismatch between RI and R2 causes gain and offset errors and
therefore these resistors must match and track over temperature.
Once again the AD7226 can be operated in single supply or
from positiVe/negative supplies.
VM'o-----~--------------------~
R1
I
two
I
t
v~
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES
MEASURED FROM 10% TO 90% of Voo.
= =
t, t, 20nl OVER VDD RANGE
2. TIMING MEASUREMENT REFERENCE LEVEL IS
---.VINH+V.,lIL
3. SELECTED INPUT LATCH IS TRANSPARENT WHILE Wii IS
LOW. THUS INVAUD DATA DURING THIS TIME CAN CAUSE
SPURIOUS OUTPUTS.
Figure 2. Write Cycle Timing Diagram
2-202 DIGITAL-TO-ANALOG CONVERTERS
c
R1, R2
= 10k0 ~O.,%
-DlGrrAL tNPUTS OMITTED
FOR CLARITY
Figure 4. AD7226 Bipolar Output Circuit
Applications - AD7226
GROUND MANAGEMENT
AC or transient voltages between AGNO and OGNO can cause
noise at the analog output. This is especially true in microprocessor
systems where digital noise is prevalent. The simplest method of
ensuring that voltages at AGNO and DGNO are equal is to tie
AGNO and OGNO together at the A07226. In more complex
systems where the AGNO and DGNO intertie is on the backplane,
it is recommended that two diodes be connected in inverse
parallel between the A07226 AGNO and OGNO pins (IN914
or equivalent).
3-PHASE SINE WAVE
The circuit of Figure 5 shows an application of the A07226 in
the generation of 3-phase sine waves which can be used to control
small 3-phase motors. The proper codes for synthesising a full
sine wave are stored in EPROM, with the required phase-shift
of 120° between the three O/A converter outputs being generated
in software.
Data is loaded into the three 01A converters from the sine
EPROM via the microprocessor or control logic. Three loops
are generated in software with each D/A converter being loaded
from a separate loop. The loops run through the look-up table
producing successive triads of sinusoidal values with 120° separation which are loaded to the DIA converters producing 3 sine
wave voltages 120° apart. A complete sine wave cycle is generated
by stepping through the full look-up table. If a 256-element sine
wave table is used then the resolution of the circuit will be 1.4°
(360°/256). Figure 7 shows typical resulting waveforms. The
sine waves can be smoothed by flltering the O/A converter outputs.
The fourth O/A converter of the A07226, OAC D, may be
used in a feedback configuration to provide a programmable
reference voltage for itself and the other three converters. This
configuration is shown in Figure 5. The relationship of VREF to
VIN is dependent upon digital code and upon the ratio of RF to
R and is given by the formula
(I + G)
VREF = (1 + G.Oo),VIN
whereG =
R~
and DD is a fractional representation of the
digital word in latch O.
Alternatively, for a given VIN and resistance ratio, the required
value of OD for a given value of VREF can be determined from
the expression
Do = (1 + RlRF)
R
VIN
•
VREF
-
RF
Figure 6 shows typical plots of VREF versus digital code for
three different values of R F. With VIN = +2.5V and RF = 3R
the peak-to-peak sine wave voltage from the converter outputs
will vary between + 2.5V and + lOY over the digital input code
range of 0 to 255.
MICROPROCESSOR
OR
CONTROL LOGIC
Figure 5. 3-Phase Sine Wave Generation Circuit
3.S VIN
~
vJ+.L
Vu=-5Y· -
S~
I-- I--
~
2.5Vw
1\ \
v~
,
" "'- '\ ')c / /
....... ......
"' ~
........
1.5VIN
1
-
-
-
VOUT..
/R,,=3R
/
........
i"""'-
.
soa....s
,:
I
VOUTB
AF '" 2R
r-
~
~
A"
=R
:::: ~ ~ """'"
Figure 7. 3-Phase Sine Wave Output
oMnaM.Hmm~_rnm~~~~
DIGITAL CODE _ DECIMAL EQUIVALENT
Figure 6. Variation of VREF with Feedback Configuration
DIGITAL-TO-ANALOG CONVERTERS 2-203
I
STAIRCASE WINDOW COMPARATOR
In many test systems, it is important to be able to determine
whether some parameter lies Within defined limits. The staircase
window comparator of Figure Sa is a circuit which can be used,
for example, to measure the VOH and VOL thresholds of a TIL
device under test. Upper and lower limits on both VOH and VOL
can be programmably set using the AD7226. Each adjacent pair
of comparators forms a window of programmable size. If V TEST
lies within a window then the output for that window will be
high. With a reference of 2.56V applied to the V REF input, the
minimum window size is IOmV.
The circuit can easily be adapted to allow for overlapping of
windows as shown in Figure 9a. If the three outputs from this
circuit are decoded then five different nonoverlapping programmable windows can again be defmed.
VTEST
FROM D.U.T.
--''''''''+-- WINDOW 1
-""""'+-- WINDOW 2
VTEST
FROMD.U.T.
-'\;'IIIr+--WINDDW 1
--'iM.-+-- WINDOW 3
--"'''-+--WINDOW 2
Figure 9a. Overlapping Windows
V ..,
WINDOW
WINDOW 3
vou,,"
VOUT"
v""",
VOUTC
WINDOW 4
WINDOWz
WINDOW
AGND
Figure 9b. Window Structure
..JY"-+--WINOOW 5
Figure 8a. Logic Level Measurement
v..,
WINDOW 1
VOUTA
VOUT8
WINDOW 2
WINDOW 3
OFFSET ADJUST
Figure 10 shows how the AD7226 can be used to provide programmable input offset voltage adjustment for the ADS44 op
amp. Each output of the AD7226 can be used to trim the input
offset voltage on one ADS44. The 620kO resistor tied to + lOY
provides a fixed bias current to one offset node. For symmetrical
adjustment, this bias current should equal the current in the
other offset node with the half-full scale code (i.e. 10000000) on
the DAC. Changing the code on the DAC varies the bias current
and hence provides offset adjust for the ADS44. For example,
the input offset voltage on the AD544J, which has a maximum
of ± 2mV, can be programmably trimmed to ± 10....V.
VOUTC
WlNOOW4
+10V
VOUTD
WINDOWS
AGND
620kU
Figure 8b. Window Structure
-15V
-DIGITAL INPUTS OMITTED FOR CLARITY
Figure 10. Offset Adjust for AD544
2-204 DIGITAL-TO-ANALOG CONVERTERS
LC 2MOS
Octal 8-Bit OAC
11IIIIIIII ANALOG
WDEVICES
A07228 I
FEATURES
Eight 8-Bit DACs with Output Amplifiers
Operates with Single or Dual Supplies
"p Compatible (95ns WR pulse)
No User Trims Required
Skinny 20-Pin DIPs and 20-Terminal Surface
Mount Packages
AD7228 FUNCTIONAL BLOCK DIAGRAM
I
GENERAL DESCRIPTION
The AD7228 contains eight 8-bit voltage-mode digital-to-analog
conveners, with output buffer amplifiers and interface logic on
a single monolithic chip. No external trims are required to
achieve full specified perfonnance for the pan.
Separate on-chip latches are provided for each of the eight D/A
conveners. Data is transferred into the data latches through a
common 8-bit TTL/CMOS (5V) compatible input pon. Address
inputs AO, Al and A2 determine which latch is loaded when
WR goes low. The control logic is speed compatible with most
8-bit microprocessors.
Specified perfonnance is guaranteed for input reference voltages
from + 2 to + IOV when using dual supplies. The pan is also
specified for single supply operation using a reference of + I OV.
Each output buffer amplifier is capable of developing + lOY
across a 2ldl load.
The AD7228 is fabricated on an all ion-implanted, high-speed,
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to integrate high-speed digital i;!gic circuits
and precision analog circuits on the same chip.
Vss
GND
PRODUCT IDGHLIGHTS
I. Eight DACs and Amplifiers in Small Package:
The single-chip design of eight 8-bit DACs and amplifiers
allows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple conveners.
Its pinout is aimed at optimizing board layout with all analog
inputs and outputs at one side of the package and all digital
inputs at the other.
2. Single or Dual Supply Operation:
The voltage-mode configuration of the DACs allows single
supply operation of the AD7228. The pan can also be operated
with dual supplies giving enhanced performance for some
parameters.
3. Microprocessor Compatibility:
The AD7228 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered and speed compatible with most highperfonnance 8-bit microprocessors.
DIGITAL-TO-ANALOG CONVERTERS 2-205
SPECIFICATIONS
(Voo
= 10.8Y 1D 16.5V; Vss = -5V ±10%; GNO = OV; VREF = +2V 1D +lOV1;
DUAL SUPPLY lit = 2kO, CL = l00pF IllIess othlllWise stated.) All specifications TIIin 1D T_ unless. othlllWise noled.
K,B
Versions2
L,C
VersioDS
TVersion
UVersion
Units
8
±2
±I
±I
±I
8
±I
±1I2
±I
±1I2
8
±2
±I
±I
±I
8
±I
± 112
±I
± 112
Bits
LSBmax
LSBmax
LSBmax
LSBmsx
±2S
±30
2
±IS
±20
2
±2S
±30
2
±IS
±20
2
mVmax
mVmax
kfimin
REFERENCE INPUT
Voltage Rangel
Input Resistance
Input Capacitance'
AC Feedthrough
2tolO
2
SOO
-70
2tolO
2
SOO
-70
2to 10
2
SOO
-70
2tolO
2
SOO
-70
V min toV max
kfimin
pFmax
Occurs when each DAC is loaded with all Is.
dBtyp
VREF =8Vp-pSineWave@IOkHz!
D1GITALINPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance'
Input Coding
2.4
0.8
±I
8
Binaty
2.4
0.8
±I
8
Binary
2.4
0.8
±I
8
Binary
2.4
0.8
±I
8
Binary
V min
V max
Il-Amax
pFmax
2
2
2
2
V/!,-smin
S
S
SO
50
S
S
SO
50
S
S
SO
50
S
S
SO
50
!,-smax
!,-smax
nVsecstyp
nVsecstyp
10.8/16.5
-4.51-5.5
10.8/16.5
-4.51-5.5
10.8/16.5
-4.S/-5.5
10.8/16.5
VmioNmax
-4.51-5.S VminNmax
16
20
16
20
16
22
16
22
mAmax
mAmax
14
18
14
18
14
20
14
20
mAmax
mAmax
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error'
Relative Accuracy
Differential Nonlinesrity
Full-Scale Error'
Zero Code Error
@2S"C
Tmin10Tmax
Minimum Load Resistance
DYNAMIC PERFORMANCE'
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Seale Change
Negative Full-Seale Change
Digital Feedthrough
Digital Crosstalk"
POWER SUPPLIES
VnnRange
VssRange
100
(cy25"C
Tmin1OTmu:
Iss
(cy25°
Conditions/Comments
Voo = + ISV ± 10%, VREF = + IOV
Guaranteed Monotonic
TypiealtempcoisSppml"CwithVREF = + 10V
rc
Typieal tempco is 30!,-V
Vour= +IOV
VIN=OVorVoo
VREF = + IOV; Settling Time to ± 112LSB
VREF = + 10V;SettlingTimeto ± 112LSB
Code transition all Os to allis. VREF = OV; WR = VDD
Code transition all Os to all Is. VREF = + IOV;WR=OV
For Specified Performance
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; V IN = V lNL or VINH
Tminto Tmax
= +15V ±10%, Vss = GNO =OV;V. = +lOV;IIt = 2kO.Ct =l00pF
SINGLE SUPPLy7(Voo
unless otherwise slalldJ All spaciIications TIIin 1D T_ IllIess IIIIawise 1IIIIIId.
STATIC PERFORMANCE
Resolution
Total Unadjusted Error'
Differential Nonlinearity
Minimum Load Resistance
8
±2
±I
2
8
±I
±I
2
8
±2
±I
2
8
±I
±I
2
Bits
LSBmsx
LSBmax
kfimin
Guaranteed Monotonic
Vour= +IOV
REFERENCE INPUT
Input Resistance
Input Capacitance'
2
500
2
500
2
500
2
SOO
kfimin
pFmax
Occurs when esch DAC is loaded with allis.
D1GITALINPUTS
DYNAMIC PERFORMANCE'
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk"
POWER SUPPLIES
VooRange
As per Dual Supply Specifications
2
2
2
2
VI!,-smin
5
7
SO
50
S
7
50
50
5
7
SO
50
5
7
50
50
!,-smax
!,-smax
nVsecstyp
nVsecstyp
Settling Time to ± 112LSB
Settling Time to ± 112LSB
Code transition all Os to all Is. VREF=OV;WR=Voo
Code transition all Os to all Is. VREF = + 10V;WR=OV
13.5/16.5
13.5/16.S
13.5/16.5
13.5/16.5
V,.;"IV""",
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH
16
20
16
20
16
22
16
22
mAmax
mAmax
100
@25"C
Tmin1OTmu:
NOTES
IVOUT must be less than VDO by 3.SV to ensure correct operation.
2Temperature ranges are as follows:
K, L Versions; 0 to + 7O"C
B, eVersions; - 2S'"C to + 8S'"C
T, UVersionsj -SS"Cto + 125"C
2~206
DIGITAL-TO-ANALOG CONVERTERS
l-fotal Unadjusted Error includes zero code error. relative accuracy and fu1I~scale error.
~ted after zero code error has been adjusted out.
sSample tested at 25"C to ensure compliance.
&rbe glitch impulse transferred to the outpUt of one converter (not addressed)
due to a change in the digital input code to another addressed converter.
'Single + 5V operation is also possible with degraded performance (see Figure 14).
SpecifICationS subject [0
change without notice.
AD7228
SWITCHING CHARACTERISTICS1,2 (See flgUl8S 1, 2;Y = +10.8YlD +l&.5Y;Yss =OYor -5Y ±10%)
DD
Limit at 25"C
All Grades
Parameters
t5
Limit at T min, T max
(K, L, B, C Grades)
Limit at T min, T max
(T, UGrades)
o
o
o
o
o
o
70
10
95
90
10
120
100
10
ISO
Units
Conditions/Comments
nsmin
nsmin
nsmin
nsmin
nsmin
Address to WR Setup Time
Address to WR Hold Time
Data Valid to WR Setup Time
Data Valid to WR Hold Time
Write Pulse Width
•
NOTES
'Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of + SV, tR = tF = Sns.
2Timing measurement reference level is
V1NH + V1NL
2
INTERFACE LOGIC INFORMATION
Address lines AO, Al and A2 select which DAC accepts data
from the input port. Table ~ shows the selection table for the
eight DACs with Figure I showing the input control logic.
When the WR signal is low, the input latch of the selected
DAC is transparent, and its output responds to activity on the
data bus. The data is latched into the addressed DAC latch on
the rising edge of WR. While WR is high, the analog outputs
remain at the value corresponding to the data held in their
respective latches.
AD7228
A2
Ai
AO
Operation
H
X
X
X
L
L
L
L
L
L
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
No Operation
Device Not Selected
DAC I Transparent
DAC I Latched
DAC 2 Transparent
DAC 3 Transparent
DAC4 Transparent
DAC S Transparent
DAC 6 Transparent
DAC 7 Transparent
DAC 8 Transparent
j
H =Higb State L= Low State X= Don'tCare
Table I. AD7228 Truth Table
TO OAC 1 LATCH
.0----01
TO OAC 2 LATCH
TO OAC 3 LATCH
•,----1
--V
--.11\
-t I-
1,
1,
I
: V-
I
...-t
SV
I " ' - - - OV
:r-- sv
5-.-..
_~
"------...II
WR
J.-tJ~ ~t..
VINH
I
~
I
DATA
------
I V1NL
:
I
OV
5V
Ov
NOTE:
THE SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW,
THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS
Figure 2. Write Cycle Timing Diagram
AD7228 Conuollnputs
WI:
L
L
L
L
L
L
L
-t I-
ADDRESS
TO OAC 4 lATCH
ABSOLUTE MAXIMUM RATINGS·
VDDtoGND . . . . . . . . .
. . . . -0.3V, +17V
V DD to Vss . . . . . . . . . .
. . . . -0.3V, +24V
Digital Input Voltage to GND
-O.3V, VDD +O.3V
VREFto GND . . . . . . . . .
-0.3V, Voo +0.3V
VoUTtoGND I . . . . . . . .
V ss , V OD
Power Dissipation (Any Package) to + 7SoC
. lOOOmW
Derates above 75°C by .. . . . . . . . .
2.0mW/C
Operating Temperature
Commercial
o to +70°C
Industrial . . . . .
- 25°C to + 85°C
Extended . . . . .
- 55°C to + 125°C
Storage Temperature
- 65°C to + 150°C
Lead Temperature (Soldering, IOsecs)
. . . . , +300°C
NOTE
'Outputs may be shorted to any voltage in the range Vss to VDD provided
that the power dissipation of the package is not exceeded. Typical short
circuit current for a short to GND or Vss is SOmA .
TO DAC 5 LATCH
.2----1
TODAC6lATCH
TO OAC 7 LATCH
TO DAC 8 LATCH
*Stresses above those listed under "Absolute Maximum Ratingsl1 may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Figure 1. InputControlLogic
CAUTION
ESD (electrostatic discharge) senSlUve device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
DIGITAL- TO-ANALOG CONVERTERS 2-207
PIN CONFIGURATIONS
DIP
LCCC
jJ J !;l
•
•
A.
2
3
PLCC
:l ;;
j
•
~
28 27 26
Jl
3
Ii :l ;;
0
A2
9lii
DB.
Vo,,",
5
Vou..
•
V"",.
1.J
24 080
NC
8
9
AD7228
20 083
,. DB4
"
DB&
12 13
OBI
;:
087(MlB)
NC ::::: NO CONNECT
J
••z
Q
CI
15 16 17
!;l
i!i
TOP VIEW
DB2
V......
V..,,,
11
••
illQ IIIQ
;: >Hl Ii !
CI
NC= NO CONNECT
ORDERING INFORMATION1
Total
Unadjusted
Error (LSB)
:t2
:tl
:t2
:tl
Temperature Range and Package Options1
- 25°C to + 85°C - 55°C to + 125°C
Oto +70"C
Plastic DIP (N-24) Hermetic (Q-24) Hermetic (Q-24)
AD7228KN
AD7228LN
AD7228BQ
AD7228CQ
AD7228TQ
AD7228UQ
PLCC3 (P-28A)
LCCC4 (E-28A)
AD7228KP
AD7228LP
AD7228TE
AD7228UE
NOTE
'To order MIL-STD-883, Class B processed parts, addl883B to part number.
Contact your local sales office for military data sheet. For U.S. Standard
Military Drawing (SMD), see DESC drawing #5962-88663.
'See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier.
4LCCC: Leadles. Ceramic Chip Carrier.
2-208 DIGITAL-TO-ANALOG CONVERTERS
NC
(Not to Scale)
21 DB2
VOUT:Z 10
DB.
AD7228
22 NC
TOP VIEW
(Not to ScaJeI
DB4
VOUT1
DBa
23 DB1
DB2
DB3
25Wii
7
VO"",
~
2
illQ
il
AD7228
.00
CIRCUIT INFORMATION
D/ASECTION
I-- r.= I_wc
500
The AD7228 contains eight identical, 8-bit, voltage-mode digitalto-analog converters. The output voltages from the converters
have the same polarity as the reference voltage, allowing single
supply operation. A novel DAC switch pair arrangement on the
AD7228 allows a reference voltage range from +2V to + 10V.
-Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high-speed NMOS switches. The simplified circuit
diagram for one channel is shown in Figure 3. Note that VREF
(Pin II) and GND (Pin 12) are common to all eight DACs.
.L
'00
~ T.=]25·C
~
fL "
300
.r T
A
r; "
200
= }'2S"C
v·:t 1Voo= + 15V
'00
,.
OUTPUYVOlTAGE - VOLTS
Figure 4. Single Supply Sink Current
The output broadband noise from the amplifier is 300....V peak-topeak. Figure S shows a plot of noise spectral density versus
frequency.
70.
... \
Figure 3. DIA Simplified Circuit Diagram
The input impedance at the VREF pin of the AD7228 is the
parallel combination of the eight individual DAC reference
input impedances. It is code dependent and can vary from 2kfl
to infinity. The lowest input impedance occurs when all eight
DACs are loaded with digital code 01010101. Therefore, it is
important that the external reference source presents a low
output impedance to the VREF terminal of the AD7228 under
changing load conditions. Due to transient currents at the reference
input during digital code changes a O.I ....F (or greater) decoupling
capacitor is recommended on the VREF input for de applications.
The nodal capacitance at the reference terminal is also code
dependent and typically varies from 120pF to 35OpF.
Each Vour pin can be considered as a digitally programmable
voltage source with an output voltage:
VOU'IN=DN' VREF
where ~ is a fractional representation of the digital
input code and can vary from 0 to 255/256.
The output impedance is that of the output buffer amplifrer as
described in the following section.
OP AMP SECTION
Each voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. This buffer amplifier is
tested with a 2kfl and lOOpF load but will typically drive a 2k.o
500
I:!
vool=.Jsv
Vas =-sv
1\
400
T..,=2S-C
1\
200
.
I'-
•so
100 200
r-
i'-
,
500 lk
-- r--
2k
5k 10k 20k
FREQUENCY - Hz
50k 100k ZOOk
SOOk
Figure 5. Noise Spectral Density vs. Frequency
DIGITAL INPUTS
The AD7228 digital inputs are compatible with either TIL or
5V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than InA. Internal
input protection is achieved by on-chip distributed diodes.
SUPPLY CURRENT
The AD7228 has a maximum IDD specification of 22mA and a
maximum Iss of 20mA over the - 55°C to + 125°C temperature
range. This maximum current specification is actually determined
by the current at - 55"C. Figure 6 shows a typical plot of power
supply current versus temperature.
,.,.
and SOOpF load.
The AD7228 can be operated single or dual supply. Operating
the part from single or dual supplies has no effect on the positivegoing settling time. However, the negative-going settling time to
voltages near OV in single supply will be slightly longer than the
settling time for dual supply operation. Additionally, to ensure
that the output voltage can go to OV in single supply, a transistor
on the output acts as a passive pull-down as the output voltage
nears OV. As a result, the sink capability of the amplifier is
reduced as the output voltage nears OV in single supply. In dual
supply operation, the full sink capability of 4OOj.I.A at 25"C is
maintained over the entire output voltage range. The single
supply output sink capability is shown in Figure 4. The negative
Vss also gives improved output amplifier performance allowing
an extended input reference voltage range and giving improved
slew rate at the output.
\
I .....
r--..
'2
10
"E,
VDD=I+15V
Vss= -5V
r-
100
C-
B
I
a
i -:
r--r---
r- r-
6
2
.......
2=Rl
1/
~ t--.
r- t-
--
r::::: ::::.,
32 48 64 80 96 112 128 144 160 176 192 208 224 240 255
DIGITAL CODE - DECIMAL EQUIVALENT
Figure 13. Variation ofVREF with Feedback Configuration
DIGITAL- TO-ANALOG CONVERTERS 2-211
SV SINGLE SUPPLY OPERATION
The AD7228 can be operated from a single + SV power supply
resulting in only slightly degraded accuracy performance from
the part. Figure 14 shows a typical plot of relative accuracy for
the part with SV VDD and a reference voltage of + 1.23V. One
important parameter which retains its specified performance is
differential nonlinearity which remains within ± lLSB ensuring
that the DACs on the AD7228 remain monotonic over the output
voltage range.
The output transfer function sits on top of the amplifier offset
voltage. Since the reference voltage is reduced, the offset voltage
amounts to a few LSBs. For parts with a true negative offset
(when V88 = - SV), the transfer function does not move off the
bottom rsil for the fIrSt few LSBs of code. Mter this the transfer
function will continue as normal. The relative accuracy plot of
Figure 14 is for a part with a true positive offset.
supply gives a considerable reduction in power dissipation (to
typically sOmW). The digital input threshold levels and digital
input currents are not affected by operating the part from the
single + 5V supply.
0.5
TA=Z&"C
-------------~:;:v&V
~
~-+~
-0.5. - - - - - - - - - - - - - - - - -
-'LO--------------~'~n~------------~.H
The required overhead voltage of 3.SV must be maintained
between VDD and the reference voltage which limits the reference
voltage range. However, operating the part from a single + SV
INPUT CODe
Figure 14. RelativeAccuraCYBt +5VVDD
MICROPROCESSOR INTERFACING
A'.
ABr----'
AO
68091
S502
Aon28*
WRr------------------L~
D7~--------------~
DO
-ADomONAL PINS OMlnED FOR CLARITV
-ADDITIONAL PINS OMITTED FOR CLARITY
1. FOR 8086A DATA BUS NEEDS TO 8E DEMULTIPLEXED
2. ZaoONLY
Figure 15. AD722BtoB085A1ZBOlnterface
Figure 16. AD722Bto6809165021nterfBce
~r-------------~
A't---,
&80oa
WI!
AO
A'
P3.0
P3.'
P3.'
P3.3
A2
AD7228'
8051
wwr--------i-/
lii'Acij.---------------------l
D7r----------------J
DO
*ADDmONALPINS OMITTED FOR ClARITY
Figure 17. AD722Bto68008lnterfBC8
2-212 DIGITAL-TO-ANALOG CONVERTERS
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
DBO
DB'
DB.
DB3
DB.
DBS
DBS
DB7
"'ADDmONAL PINS
OMmeo FOR CLARITY
Figure 1B. AD722BtoMCS-51lnterface
LC 2MOS
Dual 12-Bit DACPORT
AD7237/AD7247 I
r.ANALOG
WDEVICES
FEATURES
Complete Dual 12-Bit DAC Comprising
Two 12-Bit CMOS DACs
On-Chip Voltage Reference
Output Amplifiers
Reference Buffer Amplifiers
Parallel Loading Structure: AD7247
(8+4) Loading Structure: AD7237
Single or Dual Supply Operation
Low Power - 150 mW typ in Single Supply
AD7237 FUNCTIONAL BLOCK DIAGRAM
II
REF
OUT
.EF
..A
REF
,NB
OBO
GENERAL DESCRIPTION
The AD7237/AD7247 is a complete, dual, 12-bit, voltage output
digital-to-analog converter with output amplifiers and Zener
voltage reference on a monolithic CMOS chip. No external user
trims are required to achieve full specified performance.
0--------'
DONO
AGND
Vss
AD7247 JlUNCnONAL BLOCK DIAGRAM
Both parts are microprocessor compatible, with high speed data
latches and interface logic. The AD7247 accepts 12-bit paralll:l
data which is loaded into the respective DAC la~ lISing the:'
WR input and a separate Chip Selec~inJllAlttDi~ ~AC:Tlae
AD7237 has a double buffered intliiij'.~Mdlrii 8-bit
resPecti':ve lnl'ut lat9h i!
wide data bus with data loaded to
two write operations. An asynchronous LPAC• •1 QI!l the ,,'
AD7237 updates the DAC latches and analog.outPUts,'
,
me
A REF OUTIREF IN function is provided which ~eans that'
the on-chip 5 V reference or an external reference can be Wied
to supply the reference voltage for the part. For single suppl:y
operation, two output ranges of 0 to + 5 V and 0 to + 10 V are
available, while an additional ±5 V range is available with dual
supplies. The output amplifiers are capable of developing + 10 V
across a 2 kO load to GND.
The AD7237/AD7247 is fabricated in Linear Compatible CMOS
(LC2 MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic.
Both parts are available in a 24-pin plastic and hermetic dualin-line package (DIP) and are also packaged in a 28-terminal
plastic leaded chip carrier (PLCC).
DACPORT is a trademark of Analog Devices, Inc.
Voum
AD7247
GND
VS8
PRODUCT HIGHLIGHTS
1. The AD7237/AD7247 is a dual12-bit DACPORT™ on a
single chip. This single chip design offers considerable space
saving and increased reliability over multichip designs.
2. Between them the AD7237 and AD7247 offer a versatile
interface arrangement to either 8-bit or 16-bit data bus
structures.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-213
SPECIFICATIONS
=+15 Y, :1:5%, Yss = 0 Y or -15 Y :1:5%, AGND = DGND (GND) = 0 Y, REF IN = +5 Y,
...
RL = 2 kG, CL = 100 pF. All Specifications T to T unless otherwise noted,)
.
(VDD
min
max
Parameter
j,A'
K,B
S
Units
STATIC PERFORMANCE
Resolution
Relative Accuracy2
Differential Nonlinearity'
Unipolar Offset Error
Bipolar Zero Error
12
±I
±0.9
±3
±4
12
±1I2
±0.9
±3
±4
12
±I
±0.9
±5
±6
Bits
LSBmax
LSB max
LSB max
LSB max
±5
±5
±8
LSB max
4.9515.05
4.9515.05
±25
±30
VminlVmax
ppm/"C typ
-I
-I
mVmax
4.7515.25
4.7515.25
4.7515.25
VminlVmax 5V ± 5%
50
50
50
IlAmax
2.4
0.8
2.4
0.8
2.4
0.8
Full Scale Error,3
REFERENCE OUTPUT
REF OUT
4.9515.05
Reference Temperature Coefficient ±25
Reference Load Change
-I
(aREF OUT vs • .11)
REFERENCE INPUT
Reference Input Range
Input Current
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
lIN (Data Inputs)
IINH (Control Inputs)'
IINL (Control Inputs)'
Input Capacitance' (AD7247)
Input Capacitance' (AD7237)
Test Conditions/Comments
Guaranteed Monotonic
Vss = 0 V. DAC Latch Contents All Os
Vss = -15 V. DAC Latch Contents
1000 0000 0000
Reference Load Current Change (0-100 IlA)
±IO
ANALOG OUTPUTS
Output Range Resistors
Output Voltage Ranges
Output Voltage Ranges
DC Output Impedance
Short Circuit Current
AC CHARACTERISTICS'
Voltage Output Settling Time
Positive Full Scale Change
Negative Full Scale Change
Negative Full Scale Change
Digital-to-Analog Glitch Impulse>
Digital Feedthrough'
Digital Crosstalk2
POWER REQUIREMENTS
Voo
Vss (Dual Supplies)
100
Iss (Dual Supplies)
Vss = 0 V. Pin Strappable
Vss =-15 V. Pin Strappable
+5, +10
+5, +10, ±5
0.5
40
40
5
10
5
10
5
10
.,.smax
.,.smax
10
30
10
30
10
30
10
30
10
30
10
30
typ
nV secs typ
nV secs typ
nV secs typ
.,.S
Settling Time to Within ± 112 LSB of Final Value
Typically 3 .,.s. DAC Latch AliOs to all Is
Typically 5 .,.s. DAC Latch All Is to All Os
Vss= -15 V
DAC Latch All Is to All Os. Vss= OV
+15
-15
18
8
+15
-15
18
8
+15
-15
18
8
V nom
V nom
mAmax
mAmax
±5% for Specified Performance Uuless OtlIerwise Stated
±5% for Specified Performance Uuless OtlIerwise Stated
Output Uuloaded. Typically 10 mA
Output Uuloaded. Typically 5 mA
NOTES
'Temperature ranges are as follows: J, K Versions, -40OC to +8S'C; A, B Versions, -4O'C to +85'C; S Version, -5S'C to + 125OC.
2See Terminology.
'Measured with respect to REF IN and includes unipolarlbipolar offset error.
'Control inputs are AO, AI, <:S, WR and LDAC for the AD7237 and eSA, CSB and WR for the AD7247.
'Sample tested @+25OC to ensure compliance.
Specifications subject to change without notice.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-214 DIGITAL-TO-ANALOG CONVERTERS
AD72371AD7247
TIMING CHARACTERISTlCS1, 2 (Voo = +15 V, ±5%; Vss = 0 Vor -15 V, ±5%)
Parameter
Limit at T mm' T ......
(J, K, A, B Versions)
Limit at T min' T ......
(S Version)
Units
Conditions/Comments
t,
0
0
ns min
CS to WR Setup Time
t2
t3
t4
ts
t,;3
tl
to'
0
100
130
10
0
0
100
0
llO
ISO
IS
0
0
100
ns min
ns min
ns min
ns min
nsmin
nsmin
nsmin
CS to WR Hold Time
WR Pulse Width
Data Valid to WR Setup Time
Data Valid to WR Hold Time
Address to WR Setup Time
Address to WR Hold Time
LDAC Pulse Width
NOTES
'Sample t..ted at +2S'C to ensure compliance. AU input signals are specified with tr
and timed from a voltage level of 1.6 V.
2See Figures 3 and S.
3 AD7237 Only.
= tf = 5 ns (10% to 90% of 5 V)
i0'i~';:,~~ "'" ,~, .~;:
~~~':<"'~.:. ~,"
ABSOLUTE MAXIMUM RATINGS·
(TA = + 2S'C unless otherwise stated)
..~., ;;;,i, ~:.
Voo to GND (AD7247) ........... , ,,,,,,.:70.3 ~¥ ~"':~i\iAr<£
VDO to AGND, DGND (AD7237),<,,,,.ii~'i\.. {Q.3 ~td::}'l.'7V
Voo to Vss ......... "~~~
., .~~"",,"3(j:"Vto +~
AGND to DGND (AD7237) :'SI .....'.-0.3 V
' t~
VOUTAo V'1UTB to AGND (GND). ,Y~t~
',~'()'l!
REF OUT to AGND (GND) ..... ':;';. '.
1'0 V00
REF IN to AGND (GND) .........~to V~O.
Digital Inputs to DGND (GND) .... :-0.3 V to
Operating Temperature Range
',~",/\' ,.
Commercial (], K Versions) . . . . . . . . . . . . -40°C'to +8S oC
Industrial (A, B Versions) . . . . . . . . . . . . . -40'C to +8S oC
Extended (S Version) . . . . . . . . . . . . . . . -SsoC to +12SoC
"',,"\Y.
~;:;
Tc;JIlP~ture
-4O'C to +85'C
-4O'C to +85'C
-55'C to +l25'C
::tl max
±112 max
Plastic DIP (N-24)
AD7237JN
AD7237KN
Hermetic DIP (Q-24)
AD7237AQ
AD7237BQ
Hermetic DIP (Q-24)
AD7237SQ3
±1 max
Temperature Range and Paekage Options2
PLCC (P-28A)'
AD7237JP
AD7247KP
NOTES
ITo order MIL~STD~883, Class B processed pans, add /883B to part number.
Contact your local sales office for military data sheet.
2See Section 14 for package outline information.
JAvaiiable to 1883 processing only.
·PLCC: Plastic Leaded Chip Carrier.
Range . . . . . . . . . . . . -6S oC to
+I~O°C
J . eJI'l'Ie~a~e (Soldering, 10 sees) . . . . . . . . . . . . + 300°C
,
P~oW(Any Package) to +75°C ........ 1000 mW
allove +7SoC by . . . . . . . . . . . . . . . . . . . 10 mWrC
t may be shorted to voltages in this range provided the power disthe package is not exceeded.
above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a str..s rating only and functional
operation of the device at th... or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AD7247 ORDERING INFORMATION'
AD7237 ORDERING INFORMATION'
Relative
Accuracy
(LSB)
±112 max
•
Relative
Accuracy
(LSB)
±l max:
±112 max
±l max
±112 max
Temperature Range and Package
OptiODS2
-4O'C to +85'C
-4O'C to +85'C
-55'C to +12S'C
Plastic DIP (N-24)
AD7247JN
AD7247KN
Hermetic DIP (Q-24)
AD7247AQ
AD7247BQ
Hermetic DIP (Q-24)
AD7247SQ'
PLCC (P-28A)'
AD7247JP
AD7247KP
NOTES
ITo order MIL-STD-883, Class B processed parts, add 1883B to part number.
Contact your local sales offIce for military data sheet.
2See Section 14 for package oudine infonnation.
J Availab1e to /883 processing only.
·PLCC: Plastic Leaded Chip Carrier.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEvrcE
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-215
TERMINOLOGY
RELATIVE ACCURACY (LINEARITY)
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer function. It is measured after allowing for zero and full scale errors
and is expressed in LSBs or as a percentage of full scale reading.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±0.9 LSB max
over the operating temperature range ensures monotonicity.
SINGLE SUPPLY LINEARITY AND GAIN ERROR
The output amplifiers of the AD7237/AD7247 can have true
negative offsets even when the part is operated from a single
+ 15 V supply. However, because the negative supply rail (Vss)
is 0 V,· the output cannot actually go negative. Instead, when
the output voltage is less than the (negative) offset voltage, the
output voltage sits at 0 V, resulting in the transfer function
shown in Figure 1. This "knee" is an offset effect, not a linearity error, and the transfer function would have followed the dotted line if the output voltage could have gone negative.
in the unipolar mode is measured between full scale and the
lowest code which is guaranteed to produce a positive output
voltage. This code is calculated from the maximum specification
for negative offset. For the J, A, K, B versions, the linearity is
measured between Codes 3 and 4095. For the S grade, linearity
is measured between Code 5 and Code 4095.
UNIPOLAR OFFSET ERROR
Unipolar Offset Error is the measured output voltage from
VOUTA or VOUTB with all zeros loaded into the DAC latches
when the DACs are configured for unipolar output. It is a combination of the offset errors of the DAC and output amplifier.
BIPOLAR ZERO ERROR
Bipolar Zero Error is the voltage measured at V OUTA or VOUTB
when the DAC is connected in the bipolar mode and loaded
with code 2048. It is due to a combination of offset errors in the
DAC, amplifier offset and mismatch in the application resistors
around the amplifier.
of the output error when the
e (for the bipolar output range full
negative full scale). It is measured with
input voltage and includes the offset
OUGH
ee through is the glitch impulse injeeted for the digital
og output when the data inputs change state,
e DAC latches is not changed.
OUTPUT
VOLTAGE
it is measured with LDAC held high. For the
247 it is measured with CSA and CSB held high.
DIGITAL CROSSTALK
Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a change in digital code to the DAC
latch of the other converter. It is specified in nV sees.
OV~~~------------------~
NEGATIVE {
OFFSET
DACCODE
Figure 1. Effect of Negative Offset (Single Supply)
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is the voltage spike that appears at the output of the DAC
when the digital code changes before the output settles to its
final value. The energy in the glitch is specified in n V sees and
is measured for a I LSB change around the major carry transi, tion (0111 1111 1111 to 10000000 0000).
NormaI1y, linearity is measured between zero (all Os input code)
and full scale (all Is input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in single supply operation if the offset is negative, due to the knee in
the transfer function. Instead, linearity of the AD7237/AD7247
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-216 OIGITAL-TO-ANALOG CONVERTERS
AD7237lAD 724 7
AD7247 PIN FUNCTION DESCRIPTION (DIP PIN NUMBERS)
Mnemonic
Description
REF OUT
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the
part with internal reference, REF OUT should be connected to REF IN.
2
RoFSB
Output Offset Resistor for DAC B. This input configures the output ranges for DAC B. It is connected to VOUTB for the +5 V range, to GND for the + 10 V range and to REF IN for the ±5 V
range.
3
VOUTB
Analog Output Voltage from DAC B. This is the buffer amplifier output voltage. Three different
output voltage ranges can be chosen: 0 to +5 V, 0 to + 10 V and ± 5 V. The amplifier is capable of
developing + 10 V across a 2 kO resistor to GND.
4
DBll
Data Bit 11 (MSB).
5
DB 10
Data Bit 10.
6
GND
Ground. Ground reference for all on-chip circuitry.
7-15
DB9-DBI
Data Bit 9 to Data Bit 1.
16
DBO
Data Bit 0 (LSB).
17
CSB
18
CSA
19
WR
20
VDD
21
VOUTA
Pin
when this input is active.
\ffer amplifier output voltage. Three different
V and ±5 V. The amplifier is capable of
22
Vss
23
RoFSA
Output Offset Resistor for DAC
's input configures the output ranges for DAC A. It is connected to VOUTA for the +5 V range, to GND for the + 10 V range and to REF IN for the ±5 V
range.
24
REF IN
Voltage Reference Input. The common reference voltage for both DACs is applied to this pin. It is
internally buffered before being applied to both DACs. The nominal reference voltage for correct
operation of the AD7247 is 5 V.
AD7247 PIN CONFIGURATIONS
PLCC
DIP
AD7247
TOP VIEW
INot to Sc::atel
NC == NO CONNECT
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-217
AD7237 PIN FUNCTION DESCRIPTION (DIP PIN NUMBERS)
Mnemonic
Description
REF INA
Voltage Reference Input for DAC A. The reference voltage for DAC A is applied to this
pin. It is internally buffered before being applied to the DAC. The nominal reference volt·
age for correct operation of the AD7237 is 5 V.
2
REF OUT
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To
operate the part with internal reference REF OUT should be connected to REF INA, REF
INB.
3
REFINB
Voltage Reference Input for DAC B. The reference voltage for DAC B is applied to this
pin. It is internally buffered before being applied to the DAC. The nominal reference volt·
age for correct operation of the AD7237 is 5 V.
4
ROFSB
5
VotJTB
Output Offset Resistor for DAC B. This input confIgUreS the output ranges for DAC B. It
is connected to VOUTB for the + 5 V range, to AGND for the + 10 V range and to REF
INB for the ±5 V range.
Analog Output Voltage from DAC B. This is the buffer amplifier output voltage. Three dif·
ferent output voltage ranges can be chosen: 0 to + 5 V, 0 to + 10 V and ± 5 V. The ampli·
fier is capable of developing + 10 V across a 2 kO resistor to GND.
Pin
6
AGND
Analog Ground. Ground reference for DACs, reference and output buffer amplifiers.
7
DB7
Data Bit 7.
8-10
DB6-DB4
Data Bit 6 to Data Bit 4.
11
DB3
Data Bit 3IData Bit 11 (MSB).
12
DGND
Digital Ground. Ground reference for digital circuitry.
13
DB2
Data Bit 2IData Bit 10.
14
DBI
15
DBO
16
AO
Address Input.
the four input
17
Al
18
CS
19
WR
Write Input. WR is an active low logic in
Al to write data to the input latches.
20
LDAC
Load DAC. Logic input. A new word is loaded into the DAC latches from the respective
input latches on the falling edge of this signal.
21
Voo
VOUTA
Positive Supply, +15 V.
22
23
24
Vss
R oFsA
.s input is active.
IS
used in conjunction with CS, AO and
Analog Output Voltage from DAC A. This is the buffer amplifier output voltage. Three
different output voltage ranges can be chosen: 0 to +5 V, 0 to + 10 V and ±5 V. The
amplifier is capable of developing + 10 V across a 2 kO resistor to GND.
Negative Supply, -15 V.
Output Offset Resistor for DAC A. This input confIgUreS the output ranges for DAC A. It
is connected to VOUTA for the +5 V range, to AGND for the +10 V range and to REF
INA for the ±5 V range.
AD7237 PIN CONFIGURATIONS
DIP
PLCC
~
~ 5
0
~ ~ ~ !!
4
3
2
1
~
J .}
J
27
28
2.
0
AD7~7
TOP VIEW
(Not to Scala)
19 . .
NC= NO CONNECT
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-218 DIGITAL·TO·ANALOG CONVERTERS
AD7237/AD7247
INTERFACE LOGIC INFORMATION - AD7247
Table I shows the truth table for AD7247 operation. The part
contains a single, parallel 12-bit latch for each DAC. It can be
treated as two independent DACs, each with its own CS input
and a common WR input. CSA and WR control the loading of
data to the DAC A latch while CSB and WR control the loading
of the DAC B latch. If CSA and CSB are both low, with WR
low, the same data will be written to both DAC latches. All control signals are level triggered and therefore either or both
latches can be made transparent. Input data is latched to the
respective latch on the rising edge of WR. Figure 2 shows the
input control logic for the AD7247, while the write cycle timing
diagram for the part is shown in Figure 3.
CSA
CSB
WR
Function
X
I
0
I
0
X
I
I
0
0
I
X
0
0
0
No Data Transfer
No Data Transfer
DACA Latch Transparent
DACB Latch Transparent
Both DAC Latches Transparent
X
= Don't Care.
.~~7:
INTERFACE LOGIC INFORMATION - AD7237
The input loading structure on the AD7237 is configured for
interfacing to microprocessors with an 8-bit-wide data bus. The
part contains two I2-bit latches per DAC - an input latch and a
DAC latch. Each input latch is further subdivided into a least
significant 8-bit latch and a most significant 4-bit latch. Only
the data held in the DAC latches determines the outputs from
the part. The input control logic for the AD7237 is shown in
Figure 4, while the write cycle timing diagram is shown in
Figure S.
CS, WR, AO and Al control the loading of data to the input
latches. The eight data inputs accept right-justified data. Data
can be loaded to the input latches in any sequence. Provided
that LDAC is held high, there is no analog output change as a
result of loading data to the input latches. Address lines AO and
Al determine which latch data is loaded to when CS and WR
are low. The selection of the input latches is shown in the truth
table for AD7237 ~.tion in Table II.
:r~ L~ ~C~~IS the transfer of I2-bit data from the
;~1.! l~~, 1111
tit DAC latches. Both DAC ~tches, and hence
~olh~og outputs, are updated at the same tlIIle. The LDAC
~gn;d.is levl'1,!,~d and data is latched into the DAC latch
~tfsi~,-~e'~AC .. ~he LDA~ input is as~nc~onous
"d~entof WR. ThiS is useful ill many applicattons
daIly in the simultaneous updating of multiple AD7237s.
H9.~
care must be taken while exercising LDAC during a
"~te
. If an LDAC operation overlaps a CS and WR oper~fpn". ete is a possibility of invalid data being latched to the
odtput. To avoid this, LDAC must remain low after CS or WR
return high for a period equal to or greater than t., the minimum LDAC pulse width.
. 0lIl
CSA - - - - - - - \
WR-__4_----/
CSB
-------1
Figure 2. AD7247 Input Control Logic
t,
--I
,I--
t,
--l I-- to
lr----
Ft.~
DATA
CS WR Al AO LDAC Function
I
X
0
0
0
0
I
X
I
0
0
0
0
I
X
X
0
0
I
I
X
1-- ..
------X'-__~_~L_~A_D_ ~:========~~~
X
X
0
I
0
I
X
I
I
I
I
I
I
0
No Data Transfer
No Data Transfer
DAC A LS Input Latch Transparent
DAC A MS Input Latch Transparent
DAC B LS Input Latch Transparent
DAC B MS Input Latch Transparent
DACA and DACB DAC Latches
Updated Simultaneously from the
Respective Input Latches
X = Don't Care.
.....
Table II. AD7237 Truth Table
Figure 3. AD7247 Write Cycle Timing Diagram
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-219
•
+15V
DGND
Figure 6. Unipolar (0 to
DB7
+ 10 V) Configuration
...
Figure 4. AD7237 Input Control Logic
DAC Latch Contents
MSB
LSB
Analog Output, VOUT
+2 . REF
REF
REF
. REF
+ 2 . REF
V
AO/A1
IN
IN
IN
IN
IN
. (4095/4096)
. (204914096)
. (2048/4096) = + REF IN
. (2047/4096)
• (114096)
DATA
Figure 5. AD7237 Write Cycle Timing Diagram
APPLYING THE AD7237/AD7247
The internal scaling resistors provided on the AD7237/AD7247
allow several output voltage ranges. The part can produce unipolar output ranges of 0 to + 5 V or 0 to + 10 V and a bipolar
output range of ±5 V. Connections for the various ranges are
outlined below. Since each DAC has its own R oFs input, the
two DACs on each part can be set up for different output
ranges.
Unipolar (0 to + 10 V) Configuration
The first of the configurations provides an output voltage range
of 0 V to + 10 V. This is achieved by connecting the output offset resistor, R oFsA , or R oFsB , to GND (AGND for AD7237).
In this configuration, the AD7237/AD7247 can be operated
from single or dual supplies. Figure 6 shows the connection diagram for unipolar operation for DAC A of the AD7237, while
the table for output voltage versus digital code in the DAC latch
is shown in Table III. Similar connections apply to the AD7247.
5 V) Configuration
0+5 V output voltage range is achieved by tying
RoFSA or RoFSB to VOUTA or VOUTB ' Once again, the
AD7237/AD7247 can be operated single supply or from dual
supplies. The table for output voltage versus digital code is as in
Table III, with 2 . REF IN replaced by REF IN. Note, for this
range, lLSB = REF IN . (2. 12) = (REF IN/4096).
Bipolar Configuration
The bipolar configuration for the AD7237/AD7247, which gives
an output range of -5 V to +5 V, is achieved by connecting
RoFSA> or RoFSB' to REF IN. The AD7237/AD7247 must be
operated from dual supplies to achieve this output voltage range.
The code table for bipolar operation is shown in Table IV.
DAC Latch Contents
MSB
LSB
llll 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
Analog Output,
VOUT
+REF IN· (2047/2048)
+REF IN· (112048)
OV
-REF IN . (1/2048)
-REF IN . (2047/2048)
- REF IN . (2048/2048) = - REF IN
Note: 1 LSB = REF lNl2048.
Table IV. Bipolar Code Table
This inform~tion applies to a pr~duc:r under d~velopment. Its characteristics and specifications are subject to change without notice.
Analog DeVices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-220 DIGITAL-TO-ANALOG CONVERTERS
LC 2MOS
12-Bit DACPORTS
AD7245/AD7248 I
r.ANALOG
WDEVICES
FEATURES
12-Bit CMOS DAC with Output Amplifier and
Reference
Parallel Loading Structure: AD7245
(8+4) Loading Structure: AD7248
Single or Dual Supply Operation
Fast Digital Interface (BOns WR Pulse)
Low Power (65mW typ)
0.3", Skinny, 20- and 24-Pin DIP
20- and 28-Terminal Surface Mount Packages
AD7245/AD7248 FUNCTIONAL BLOCK DIAGRAMS
V DD REF OUT
ROFS
DBD
Voo
GENERAL DESCRIPTION
The AD7245/AD7248 is a complete l2-bit, voltage-output,
digitai-to-analog converter with output amplifier and Zener
voltage reference on a monolithic CMOS chip. No external
trims are required to achieve full specified performance for the
part.
The part features double-buffered interface logic with a l2-bit
input latch and 12-bit DAC latch. The data held in the DAC
latch detertnines the analog output of the converter. The AD7245
accepts 12-bit parallel data which is latched into the input latch
on the rising edge of CS or WR. The AD7248 has an 8-bit-wide
data bus, and data is loaded to the input latch in two write
operations, an 8-bit LSB load and a 4-bit MSB load. The input
data must be right justified. For both parts, an asynchronous
LDAC signal transfers data from the input latch to the DAC
latch. The AD7245 also has a CLR signal on the DAC latch
which allows features such as power-on reset to be implemented.
All logic inputs are level triggered and are TTL and CMOS
(5V) level compatible, while the control logic is speed compatible
with most microprocessors.
The on-chip 5V buried Zener diode provides a low-noise, temperature compensated reference for the DAC. The gain setting
resistors allow a number of ranges at the output: 0 to + 5V, 0 to
+ lOY when using single supply and 0 to + 5V, - 5V to + 5V
when operated in dual supplies. The output amplifier is capable
of developing + lOY across a 2kO load to GND.
REF OUT
DB11
DGND
ROfS
PRODUCT HIGHLIGHTS
1. Complete 12-Bit DACPORT™
The AD7245/AD7248 is a complete, voltage output, 12-bit
DAC on one chip. This single-chip design of the DAC reference
and output amplifier is inherently more reliable than multichip
designs.
2. Microprocessor Compatibility
The para1lelloading structure of the AD7245 allows connection
to microprocessors with a 16-bit-wide data bus. The AD7248
is aimed at microprocessors which have an 8-bit-wide data
bus structure. The high-speed logic of both parts allows
direct interfacing to most modern microprocessors. Additionally, the double buffered interface enables simultaneous
update of the AD7245/AD7248 in multiple DAC systems.
DACPORT is a trademark of Analog Devices, Inc.
The AD7245/AD7248 is fabricated in an all ion-implanted,
high-speed linear, compatible CMOS (LC2MOS) process. The
AD7245 is packaged in a small, O.3"-wide, 24-pin DIP and 28terminal surface mount packages. The AD7248 is available in a
O.3"-wide, 20-pin DIP and 20-terminal surface mount
packages.
DIGITAL-TO-ANALOG CONVERTERS 2-221
•
SPECIFICATIONS
SINGLE SUPPLY (Voo =
+t5V ±5%1, Yss = AGND = DGND=OV;R.. = 2kfitoGND;CL = tOOpFtoGND;REFOUTunIoadad
unJess othelWise stated, All specifications Tmin to TIIIII unless oIheIwise stated,)
'arameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity'
Unipolar Offset Error'
at + 2S"C
TmintoTmu
DAC Gain Error'"
Full-Scale Output Voltage Error'
TA = +2S'C
J,AVersion'
SVersion'
Units
Test Conditions/Comments
12
:!:I
12
001
:!:I
001.5
001
Bits
LSBmax
LSBmax
LSBmax
LSBmax
Voo= + I 1.4V to + 14.2SV
Voo= + 14.2SVto + IS.7SV
Guaranteed Monotonic
003
:!:S
:!:2
:!:3
005
002
LSBmax
LSBmax
LSBmax
000.2
Tmin to Tmu
AFull Scale!AV00
TA = +2S'C
Full-Scale Temperature
Coefficient'
AOffsetiAVoo
:!:0.2
% ofFSR max
000.6
% ofFSR max
Voo = + ISVfor],AGrades;
Voo = + 12V & + 15VforSGrade
Voo= + 12V & + 15V
000.12
%ofFSRIV max
AVoo=+S%
:!:30
001
002
ppm ofFSRrC max
mVmax
AVoo = :!:S%
4.99/5.01
4.99/5.01
V min to V max
Voo = + ISV for], A Grades;
Voo:!: +12V& +ISVforSGrade
6
:!:4O
mVNmax
ppm ofFSRrC typ
AVoo=:!:S%
FSR = SV
:!:1.5
mVmax
Reference Load Current Change (O-IOO",AJ
2.4
0.8
2.4
0.8
Vmin
:!:I
:!:10
001
0010
",A max
",A max
001
0010
001
:!:IO
",A max
",A max
150
200
8
16
ISO
200
8
16
,.A max
fJ.Amax
pFmax
pFmax
ANALOG OUTPUT
Output Range Resistors
Ranges
dc Output Impedance
Short-Circuit Current
15/30
+5, +10
0.5
40
15/30
+5, + 10
0.5
40
kO minikO max
V
Otyp
mAtyp
DYNAMIC PERFORMANCE"
Output Voltage Settling Time
Positive Full-Scale Change
Negative FUll-Scale Change
Output Voltage Slew Rate
Digital Feedthrough'·IO
Digital-ta-Analog Glitch ImpUlse
5
10
2
10
30
8
10
f.Lsmax
10
30
",styp
V/",smin
nVsecstyp
nVsecstyp
POWER SUPPLIES
VooRange
REFERENCE
Reference Output fW + 25°C
000.12
Typical Tempcois :!: 3ppmofFSR4rC
AReferencelAVDO
TA = +2S"C
6
Reference Temperature Coefficient 0030
Reference Load Sensitivity
(AReference!AI)
:!:I
D1G1TALINPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
lIN (Data Inputs)
at +2S"C
T mintoTmax
IINH (Control Inputs)·
at + 2S"C
T min to Tmax
lIN!. (Control Inputs)·
at + 25"C
T min to Tmax
Input Capacitance" (AD724S)
Input Capacitance" (AD7248)
Vma.
VtN = OVorVoo
VIN = Voo
VIN = OV
1.5
14.25/15.75
11.4/15.75
VminNmax
at + 25"C
9
9
Tmin IO Tmax
12
12
mAmax
mAmax
100
Pin Strappable. Min Load Resistance is 2kO to GND
Settling Time to :!:ILSB.RL =5kO,CL = 100pF
DAC Register all Os to allis
DACRegisteraillstoailOs
MajorCarry Transition
For Specified Performance
Output Unloaded
Typically4.5mA
NOTES
I For the S Vel'Siononly: VOD = + I2V ±5%lo + ISV ±S%
ITemperature ranges are as follows:
) Version. 610 + 700c
A Venion. - 2S"e 10 + 85"C
SVenton. -55"elo + 125"e.
)See Terminology.
"FSR means Full-Scale R.angcand is SV wilh RoFSconnected to RpB. VOL,.and IOV with Ron connecled toGND and RFBCOnnected to VOL"T'
~is error is cak:ulated with res~t to the reference volgge and is measured after the offset error has been allowed for.
"This error iscalculatcd w.r.t. an ldeaI4.9988V (on the 5V ranse}or 9.9976V (on the IOV range).
It inc:1udes the effemofintemal voltaIC reference, pin andofhet errors.
7Full-scaleT.C. "" .l.FSJ.lT,where.lFSiuhefull-scalt:changefromTA "" +2S"CtoTnlill orTma•
'control inputsareO. Wi. I:DiCandCLR for AD7245 and CSMSB,CSLSB, Wiland LDAC for AD7248.
"'Sample testedal + 25"C toensurc compliarM:c.
1«The metal lid on the AD7245(onIy)ceramic (D-24A)packaF isconnectcd to Pin 12 (I>GND).
SpecifICations subjcc::t IOchanp without notice.
2-222 DIGITAL-TO-ANALOG CONVERTERS
SPECIFICATIONS
= + 15V ±5%1. Vss = -15V ±5%1.AGND = DGND=DV; At = 2kfi to GND;
DUAL SUPPLY
AD7245/AD7248
(Villi
CL = 100pFto GND; REF OUT unloaded unless otherwise slated. All specifications Tmn to T.... unless otherwise stated.)
p-
J,AV_'
SV-"
Uu.
12
±I
12
±I
±I
±l.S
±I
Bib
LSBmu
LSBmn
LSBmaz
LSB""",
±3
±5
±l
±3
±5
±l
LSBmu
LSBmax
LSBmu
±O.2
±0.2
% ofFSR max
Test eo.ditioaoIComm...
STATIC PERFORMANCE
RcsoIUUoD
Relative Accuracy'
Diff......tial NOD!incari
4321282126
.
..
It;
r
r2 ~ !i
}
•
3
2B .7
•,
0
f
..
8
>
LDAC
WR
cs
DBO
DB'
D8&
DB.
12 13 ,. 15 1& 17 18
DB2
DONO
i§
!
D84
NC
= NO CONNECT
§ !i !
2!
!
111~i!i
Ne = NO CONNECT
DIGITAL-TO-ANALOG CONVERTERS 2-225
I
AD7248 PIN FUNCTION DESCRIPTION
(ANY PACKAGE)
Pin
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
Description
Pin
Mnemonic
Description
Vss
Negative Supply Voltage (OV for single
supply operation).
Bipolar Offset Resistor. This provides
access to the on-chip application resistors
and aJlows different output voltage ranges.
Reference Output. The on-chip reference is
provided at this pin and is used when configuring the part for bipolar outputs.
Analog Ground.
Data Bit 7.
Data Bit 6.
Data Bit 5.
Data Bit4.
Data Bit 3IData Bit II (MSB).
Digital Ground.
Data Bit 21Data Bit 10.
Data Bit lIData Bit 9.
Data Bit 0 (LSB)/Data Bit 8.
14
CSMSB
15
CSLSB
16
WR
17
LDAC
18
19
V DD
RFB
20
VOUT
Chip Select Input for MS Nibble. (Active
LOW). This selects the upper 4 bits of the
input latch. Input data is right-justified.
Chip Select Input for LS byte. (Active
LOW). This selects the lower 8 bits of the
input latch.
Write Input. This is used in conjunction
with CSMSB and CSLSB to load data into
the input latch of the AD7248.
Load DAC Input (Active LOW). This is an
asynchronous input which when active transfers data from the input latch to the DAC
latch.
Positive Supply Voltage.
Feedback Resistor. This aJlows access to
the amplifier's feedback loop.
Output Voltage. Three different output
voltage ranges can be chosen: 0 to + 5V,
Oto + IOVor -sVto + sV.
RoFS
REF OUT
AGND
DB7
DB6
DB5
DB4
DB3
DGND
DB2
DBI
DBO
AD7248PIN CONFIGURATIONS
DIP
LCCC
...
"
...
0
"il;0
v••
~
"'
"'3
R..
•
•
10 11 12
Q
Z
g
,.
DB4
•
14 CsMSB
• ,. "1lI •• ••:
! 8:
SINGLE SUPPLY LINEARITY AND GAIN ERROR
The output amplifier of the AD7245/AD7248 can have a true
negative offset even when the part is operated from a single
positive power supply. However, because the lower supply rail
to the part is OV, the output voltage cannot actually go negative.
Instead the output voltage sits on the lower rail and this results
in the transfer function shown across. This is an offset effect
and the transfer function would have followed the dotted line if
the output voltage could have gone negative. Normally, linearity
is measured after offset and full scale have been adjusted or
allowed for. On the AD7245/AD7248 the negative offset is
allowed for by calculating the linearity from the code which the
amplifier comes off the lower rail. This code is given by the
negative offset specification. For example, the single supply
linearity specification applies between Code 3 and Code 4095 for
the 25°C specification and between Code 5 and Code 4095 over
the T min to T max temperature range. Since gain error is also
INot to Sea'e)
15 CSLSB
14CSMSB
DB4 •
Ii!
Q
r
"'
19
AD7248
TOP VIEW
'IWR
INot to Scale)
OB51
20
18 Voo
AD7248
TOP VIEW
D. . .
~ } J
•"' ,
0
17LDAC
0875
2-226 DIGITAL-TO-ANALOG CONVERTERS
3
,,
LJ
AGND4
~
= >~ J
>, 20
,.
PLCC
Ii!
Q
Q
Q
Z
g
;0
Q
Q
Q
measured after offset has been allowed for, it is calculated between
the same codes as the linearity error. Bipolar linearity and gain
error are measured between Code 0 and Code 4095.
OUTPUT
VOLtAGE
NEGATrv~V{
,/
DFFSET
DACCODE
Typical Performance Graphs - AD7245/AD7248
IDO(~15V'Vi
----
=
4.995
V"LORVINH~J
f
VDD
+15V
-
"'-IO~ IVss ~ -15V, VIN = OV OR Vool
........ 'OD IVss
= OV. VIN
=
5.005
-
~SS (Vss = -15VI
-55
-25
+25
+70 +85
TEMPERATURE - "C
...
L
V
/
-25
0
+25
+70 +85
TEMPERATURE - "C
OJ....JTW1TH ALl
200
t'-....
I/
REFEiENCE
... 'f\"I'---"\ l"-II
'DO
I:I!
~
I'.
to
+r
OfCOUjLlNGI
R~FERE~CE I~ECOJPLEO'I
ill
1',
I'
OUPUTWITH ALL
L.
I'-- r-...
500
lk
2k
5k
N~,~
"
, 1",DElu~
"',
,'SONDAC
./'
20
10k
20k
.....
~
~
Voo = + 16V WITH
loom pop SIGNAL
l
•
20
200
I
r'<~JCOUPUNG
so
I
T
NO DECOUPLING
OUTPUT WITH
ALLOjSONr AC
100
~.
.~
80
c
20
50
DECO!PU!O-
O'SON DAC
Vas = ov
j=
SDk
FREQUENCY - Hz
+125
Reference Voltage vs. Temperature
Voo = +1SV
T
~
V
5.01
-55
+125
Power Supply Current vs. Temperature
,.
---..i'
OV OR Vool
I
100 200
1k
2k
"',
10k 20k
, ..k
FREQUENCV - Hz
·POWER SUPPl V DECOUPLING CAPACITORS ARE
10).L~ and O.l).Lf
·REFERENCE OECOUPUNG COMPONENTS AS PER FIGURE 8
Noise Spectral Density vs. Frequency
Power Supply Rejection Ratio vs. Frequency
-, ~ ;-1 -----------+-
L~'
Positive-Going Settling Time
= + 15l1, Vss = - 15V)
(VOO
-+
Negative-Going Settling Time
= + 15l1, Vss = - 15V)
(VOO
DIGITAL-TO-ANALOG CONVERTERS 2-227
I
CIRCUIT INFORMATION
D/ASECTION
The AD724S/AD7248 contains a 12-bit voltage-mode digital-toanalog converter. The output voltage from the converter has the
same positive polarity as the reference voltage allowing single
supply operation. The reference voltage for the DAC is provided
by an on-chip buried-Zener diode.
The DAC consists of a highly stable, thin-film, R-2R ladder and
twelve high-speed NMOS single-pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in
Figure l.
AGNDo-_-_--+-~~.._-_-
_ __='
Figure 1. DIASimplifiedCircuitDiagram
The input impedance of the DAC is code dependent and can
vary from 8kO to infinity. The input capacitance also varies
with code, typically from SOpF to 20OpF.
The small-sigilal (200mV pop) bandwidth of the output buffer
amplifier is typically IMHz. The output noise from the amplifier
is low with a figure of 2SnV/YHZ at a frequency of 1kHz. The
broadband noise from the amplifier has a typical peak-to-peak
fIgUre of ISO""V for a IMHz output bandwidth. There is no
significant difference in the output noise between single and
dual supply operation.
VOLTAGE REFERENCE
The AD724S/AD7248 contains an internal low-noise buried-Zener
diode reference which is trimmed for absolute accuracy and
temperature coefficient. The reference is internally connected to
the DAC. Since the DAC has a variable input impedance at its
reference input the Zener diode reference is buffered. This
buffered reference is available to the user to drive the circuitry
required for bipolar output ranges. It can be used as a reference
for other parts in the system provided it is externally buffered.
The reference will give long-term stability comparable with the
best discrete Zener reference diodes. The performance of the
AD724S/AD7248 is specified with internal reference, and all the
testing and trimming is done with this reference. The reference
should be decoupled at the REF OUT pin and recommended
decoupling components are 10""F and O.l""F capacitors in series
with a 100 resistor. A simplified schematic of the reference
circuitry is shown in
Figure 3.
v..
OP AMP SECTION
The output of the voltage-mode D/A converter is buffered by a
noninverting CMOS amplifier. The user has access to two gain
setting resistors which can be connected to allow different output
voltage ranges (discussed later). The buffer amplifier is capable
of developing up to 10V across a 2kO load to GND.
The output amplifier can be operated from a single positive
power supply by tying Vss = AGND = OV. The amplifier can
also be operated from dual supplies to allow a bipolar output
range of - SV to + SV. The amplifier should not be configured for
the 0 to + IOV output range when Vss is more negative than - SV.
For dual supply operation on this range a Vss of -SV should
be applied to the part. The advantage of having dual supplies
for the unipolar output ranges are faster settling time t) voltages
near OV, full-sink capability of 2.SmA maintained over the
entire output range and elimination of the effects of negative
offset on the transfer characteristic (outlined previously). Figure
2 shows the sink capability of the amplifier for single supply
operation.
.
~
11
I
V
V
REF OUT
Ie IS TEMPERATURE
COMPENSATION CURRENT
Figure 3. Internal Reference
DIGITAL SECTION
The AD724S/AD7248 digital inputs are compatible with either
TTL or SV CMOS levels. All data inputs are static-protected
MOS gates with typical input currents of less than InA. The
control inputs sink higher currents (IS0""A max) as a result of
the fast digital interfacing. Internal input protection of all logic
inputs is achieved by on-chip distributed diodes.
The AD724S/AD7248 features avery low digital feedthrough
figure of IOnV sees in a SVoutput range. This is due to the
voltage-mode configuration of theDAC. Most of the impulse is
actually as a result of feedthrough across the package. Normally,
ceramic packages show more feedthrough than the other packages
because of the metal lid. However, on the AD724S, the lid of
the ceramic package is connected to DGND (Pin 12), and this
reduces the feedthrough. The AD7248 metal lid is not connected
to DGND on the package, but this can be done externally to
reduce the feedthrough.
3
J
TODAC
TA '"
ii
MIN
OUTPUT VOLTAGE - Volb
TIM)!,
••
Figure 2. Typical Single Supply Sink Current vs.
Output Voltage
2-228 DIGITAL-TO-ANALOG CONVERTERS
AD7245/AD7248
INTERFACE LOGIC INFORMATION - AD7245
Table I shows the truth table for AD7245 operation. The part
contains two 12-bit latches, an input latch and a DAC latch. CS
and WR control the loading of the input latch while LDAC
controls the transfer of infonnation from the input latch to the
DAC latch. All control signals are level-triggered; and therefore
either or both latches may be made transparent, the input latch
by keeping CS and WR "LOW", the DAC latch by keeping
LDAC "LOW". Input data is latched on the rising edge of
WR.
The data held in the DAC latch determines the analog output of
the converter. Data is latched into the DAC latch on the rising
edge of LDAC. This LDAC signal is an asynchronous signal
and is independent of WR. This is useful in many applications.
However, in systems where the asynchronous LDAC can occur
during a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. For
example, if LDAC goes LOW while WR is "LOW", then the
LDAC signal must stay LOW for t7 or longer after WR goes
high to ensure correct data is latched through to the output.
CLR LDAC WR CS Function
L
L
L Both Latches are Transparent
H
Both Latches are Latched
X
H
H
H
X
H Both Latches are Latched
H
H
L Input Latches Transparent
H
H
L
L Input Latches Latched
H
H
~
H
L
H
H DAC Latches Transparent
H
H DAC Latches Latched
H
DAC Latches Loaded with all Os
X
X
X
L
H DAC Latches Latched with All
H
H
~
Os and Output Remains at
OVor -5V
L
L
L Both Latches are Transparent
and Output Follows Input
Data
.,
.,
H = High State L = Low State X = Don't Care
Table I. AD7245 Truth Table
The contents of the DAC latch are reset to all Os by a low level
on the CLR line. With both latches transparent, the CLR line
functions like a zero override with the output brought to OV in
the unipolar mode and - 5V in the bipolar mode for the duration
of the CLR pulse. If both latches are latched, a "LOW" pulse
on the CLR input latches all Os into the DAC latch and the
output remains at OV (or - 5V) after the CLR line has returned
"HIGH". The CLR line can be used to ensure powerup to OV
on the AD7245 output in unipolar operation and is also useful,
when used as a zero override, in system calibration cycles.
Figure 4 shows the input control logic for the AD7245 and the
write cycle timing for the part is shown in Figure 5.
ClR------J
Wi!
cs
INPUT DATA
Figure 4. AD7245 Input Control Logic
NOTES
•. SEE TIMING SPECIFICATIONS.
2. ALL INPUT RISE AND FALL TIMES MEASURED fROM '0% TO
90% OF +5V. t, '" It = 5ns.
3. TIMING MEASUREMENT REFERENCE LEVEL IS
VINH + VINl,
---.---
4. IF LDAC IS ACTIVATED WHILE Wii IS LOW THEN iliAC
MUST STAY LOW FOR t, OR LONGER AFTER WR GOES HIGH .
Figure 5. AD7245 Write-Cycle Timing Diagram
INTERFACE LOGIC INFORMATION - AD7248
The input loading structure on the AD7248 is configured for
interfacing to microprocessors with an 8-bit-wide data bus. The
part contains two 12-bit latches - an input latch and a DAC
latch. Only the data held in the DAC latch determines the analog
output from the converter. The truth table for AD7248 operation
is shown in Table II, while the input control logic diagram is
shown in Figure 6.
CSMSB, CSLSB and WR control the loading of data from the
external data bus to the input latch. The eight data inputs on
the AD7248 accept right-justified data. This data is loaded to
the input latch in two separate write operations. CSLSB and
WR control the loading of the lower 8-bits into the 12-bit-wide
latch. The loading of the upper 4-bit nibble is controlled by
CSMSB and WR. All control inputs are level triggered, and
input data for either the lower byte or upper 4-bit nibble is
latched into the input latches on the rising edge of WR (or
either CSMSB or CSLSB). The order in which the data is loaded
to the input latch (i.e., lower byte or upper 4-bit nibble first) is
not itnportant.
The LDAC input controls the transfer of 12-bit data from the
input latch to the DAC latch. This LDAC signal is also level
triggered, and data is latched into the DAC latch on the rising
edge ofLDAC. The LDAC input is asynchronous and independent
of WR. This is useful in many applications especially in the
sitnultaneous Updating of mUltiple AD7248 outputs. However,
in systems where the asynchronous LDAC can occur during a
write cycle (or vice versa) care must be taken to ensure that
DIGITAL-TO-ANALOG CONVERTERS 2-229
II
incorrect data is not latched through to the output. In other
words, if LDAC goes low while WR and either CS input are
low (or WR and either CS go low while LDAC is low), then the
LDAC signal must stay low for t7 or longer after WR rerurns
high to ensure correct data is latched through to the output.
The write cycle timing diagram for the AD7248 is shown in
Figure 7.
An alternate scheme for writing data to the AD7248 is to tie the
CSMSB and LDAC inputs together. In this case exercising
CSLSB and WR latches the lower 8 bits into the input latch.
The second write, which exercises CSMSB, WR and LDAC
loads the upper 4-bit nibble to the input latch and at the same
time transfers the l2-bit data to the DAC latch. This automatic
transfer mode updates the output of the AD7248 in two write
operations. This scheme works equally well for CSLSB and
LDAC tied together provided the upper 4-bit nibble is loaded
to the input latch followed by a write to the lower 8 bits of the
input latch.
CSLSB CSMSB WR LDAC Function
L
L
~
H
H
H
H
H
H
H
H
H
L
L
~
H
H
L
L
~
L
L
~
L
H
H
L
H
H
H
H
H
H
L
~
L
H
H
H
H
H
=
High State
L
=
Loads LS Byte into Input Latch
Latches LS Byte into Input Latch
Latches LS Byte into Input Latch
Loads MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Loads Input Latch into DAC Latch
Latches Input Latch into DAC Latch
Loads MS Nibble into Input Latch and
Loads Input Latch into DAC Latch
No Data Transfer Operation
Low State
Table II. AD7248 Truth Table
LDAC
l 1--"---1rl----------------------------i
.
r-"--I
csMs,~_1-I---..j-~-..-....,1
1..-------- ::
csm
5Y
OY
~
WR
r-"
l
--I
1
1 .rr
t.
--I t--
..j ,.. ..
t--',~
I
;-1-1---"--1-- ::
I
r
1~'r
to
to
to
SY
IIIl::
D~JA ~J/!JJJID7/J!//
Figure 7. AD7248 Write Cycle Timing Diagram
APPLYING THE AD7245/AD7248
The internal scaling resistors provided on the AD7245/AD7248
allow several output voltage ranges. The part can produce unipolar
output ranges of OV to + 5V or OV to + lOY and a bipolar
output range of - 5V to + 5V. Connections for the various
ranges are outlined below.
UNIPOLAR (OV to +lOV) CONFIGURATION
The first of the configurations provides an output voltage range
of OV to + lOY. This is achieved by connecting the bipolar
offset resistor, RoFS, to AGND and connecting RFB to VOUT• In
this configuration the AD7245/AD7248 can be operated single
supply (Vss = OV = AGND). If dual supply performance is
reqnired, a Vss of - 5V should be applied. Note that a Vss
supply more negative than - 5V should not be applied to the
AD7245/AD7248 when it is configured for a 0 to + lOY output
range. Figure 8 shows the connection diagram for unipolar
operation while the table for output voltage versus the digital
code in the DAC latch is shown in Table III.
------------------~
lOll
O.I"'F~
UPPER
4 BITS
OF INPUT
LATCH
~
IO ...F
REF OUT
ROFS
YDD
8
"DIGITAL CIRCUITRY
DGND.-~=;.J
OMITTED FOR CLARITY.
DB7- DBO
Figure 6. AD7248 Input Control Logic
2-230 DIGITAL-TO-ANALOG CONVERTERS
OY
Figure 8. Unipolar (0 to
+ 10V) Configuration
AD7245/AD7248
DAC Latch Contents
MSB
LSB
1111
1111 1111
Analog Output, Your
+2· VREF •
( 2049 )
+2· VREF · 4096
1000 0000 0000
2048 ) = +VREF
+2· VREF · ( 4096
o1 1 1
2047 )
+2· VREF · ( 4096
1111
0000 0000 0001
0000 0000 0000
NOTE: ILSB
+2·
VOUT = VB1AS + D· VREF
(=~ )
1000 0000 0001
1111
(RoFS = VOUT = R FB) the output voltage, VOUT is expressed
as:
VREF·(~)
where D is a fractional representation of the digital word
in the DAC latch and VB1AS is the voltage applied to the
AD724S/AD7248 AGND pin.
Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low impedance •
source. A circuit configuration is outlined for AGND bias in
Figure 9 using the AD589, a + 1.23V bandgap reference.
If a gain of 2 is used on the buffer amplifier the output voltage,
VOUT is expressed as
VOUT = 2(V 8IAS + D· VREF)
OV
= 2· VREP{2-12) = VREF (2~)
Table III. Unipolar Code Table (OVto + 10VRange)
UNIPOLAR (OV to +5V) CONFIGURATION
The OV to + SV output voltage range is achieved by tying RoFs,
R F8 and VOUT together. For this output range the AD724S1
AD7248 can be operated single supply (Vss = OV) or dual
supply. The table for output voltage versus digital code is as in
Table III, with 2· VREF replaced by VREF . Note that for this
range
In this case care must be taken to ensure that the maximum
output voltage is not greater than VDD - 3V. The VDD - VOUT
overhead must be greater than 3V to ensure correct operation of
the part. Note that VDD and Vss for the AD724S/AD7248 must
be referenced to DGND (system GND). The entire circuit can
be operated in single supply with the Vss pin of the AD724S1
AD7248 connected to system GND.
10H
+
~
10...F
REF OUT
ROFS
voo
+15V
2R
BIPOLAR CONFIGURATION
The bipolar configuration for the AD724S/AD7248, which gives
an output voltage range from - SV to + SV, is achieved by
connecting the RoJ's input to REF OUT and connecting RF8
and VOUT . The AD724S/AD7248 must be operated from dual
supplies to achieve this output voltage range. The code table for
bipolar operation is shown in Table IV.
DAC Latch Contents
MSB
LSB
2R
27kll
-
AGND
VOUT
V B1AS
+
AD589
Vss
SYSTEM
·DIGITAL CIRCUITRY
GND
DMITTED FOR CLARITY.
Analog Output, Your
+VREF ·
1000 0000 0001
+VREF·(2~
1000 0000 0000
Figure 9. AGND Bias Current
( 2047 )
2048
1111 1111 1111
)
PROGRAMMABLE CURRENT SINK
Figure 10 shows how the AD7245/AD7248 can be configured
with a power MOSFET transistor, the VN0300M, to provide a
OV
ton
0000 0000 0001
(2~8)
-VREF · (~~~)
0000 0000 0000
( 2048 )
-VREF • 2048 = -VREF
o1 1 1
1111 1111
-VREF •
O.1pF ~
+
~
V SOURCE
T
10 ... F
REF OUT
"0..
~LOAD
Voo
I
2ft
NOTE: ILSB = 2 • VREP{2-") = VREF ( 2c!.S)
TablelV. Bipolar Code Table
*DtGITAL CIRCUITRY
AGNDBIAS
The AD724S/AD7248 AGND pin can be biased above system
GND (AD724S/AD7248 DGND) to provide an offset "zero"
analog output voltage level. With unity gain on the amplifier
OMmED FOR CLARITY.
Vss
Figure 10. ProgrammableCurrentSink
DIGITAL-TO-ANALOG CONVERTERS 2-231
programmable current sink from VDD or VSOURCE. The VN0300M
is placed in the feedback of the AD724S/AD7248 amplifier. The
entire circuit can be operated in single supply by tying the Vss
of the AD724S/AD7248 to AGND. The sink current, ISINK , can
be expressed as:
D,VREF
ISINK =
ru-
Using the VN0300M, the voltage drop across the load can typically
be as large as (V SOURCE - 6V) with VOUT of the DAC at + SV.
Therefore, for a current of SOmA flowing in the RI (with all Is
in the DAC register) the maximum load is 200n with VSOURCE
= + ISV. The VN0300M can actually handle currents up to
SOOmA and still function correctly in the circuit, but in practice
the circuit must be used with larger values of VSOURCE otherwise
it requires a very small load.
Since the tolerance value on the reference voltage of the AD724SI
AD7248 is ± 0.2%, then the absolute value of ISINK can vary by
± 0.2% from device to device for a fixed value of RI.
Because the input bias current of the AD724S/AD7248's op amp
is only of the order of pA's, its effect on the sink current is
negligible. Tying the RoFS input to the RFB input reduces this
effect even further and prevents noise pickup which could occur
if the ROFS pin was left unconnected.
The circuit of Figure 10 can be modified to provide a programmable
current source to AGND or - VSINK (for - VSINK, dual supplies
are required on the AD724S/AD7248). The AD724S/AD7248 is
configured as before. The current through RI is mirrored with
a current mirror circuit to provide the programmable source
current (see CMOS DAC Application Guide, Publication No.
G872-30-10/84, for suitable current mirror circuit). As before
the absolute value of the source current will be affected by the
± 0.2% tolerance on VREF. In this case the performance of the
current mirror will also affect the value of the source current.
FUNCTION GENERATOR WITH PROGRAMMABLE
FREQUENCY
Figure 11 shows how the AD724S/AD7248 can be configured
with the ADS37, voltage-to-frequency converter and the AD639,
trigonometric function generator to provide a complete function
generator with programmable frequency. The circuit provides
square-wave, triwave and sinewave outputs, each output of
± IOV amplitude.
The AD724S/AD7248 provides a programmable voltage to the
ADS37 input. Since both the AD724S/AD7248 and ADS37 are
guaranteed monotonic, the output frequency will always increase
with increasing digital code. The ADS37 provides a square-wave
output which is conditioned for ± IOV by amplifier AI. The
ADS37 also provides a differential triwave output. This is conditioned by amplifiers A2 and A3 to provide the ± I.8V triwave
required at the input of the AD639. The triwave is further
scaled by amplifier A4 to provide a ± IOV output.
Adjusting the triwave applied to the AD639 adjusts the distortion
performance of the sine wave output, ( + 10V in configuration
shown). Amplitude, offset and symmetry of the triwave can
affect the distortion. By adjusting these, via VRI and VR2, an
output sine wave with harmonic distortion of better than - SOdB
can be achieved at low and intermediate frequencies.
Using the capacitor value shown in Figure 11 for CF (i.e. 680pF)
the output frequency range is 0 to 100kHz over the digital input
code range. The step size for frequency increments is 25Hz.
The accuracy of the output frequency is limited to 8 or 9 bits
by the ADS37, but it is guaranteed monotonic to 12 bits.
+15V
33k
±10V
SQUARE
WAVE
+15V
+15V
r--_. . .
~
Voo
56k
AD7245/
AD7248
VRI
10k
R'B
V OUT
c
C
AGND
Xl
+Vs
X2
W
Ul
Zl
U2
Z2
Vos
DGND
lOll
±10V
TRIWAVE
AD537
ROFS
Vss
22k
-Vs
COM
AD639
AI. A2. A3. A4 - 2x AD712
+
~10f'.F
UP
Y2
Figure ". Programmable Function Generator
2-232 DIGITAL-TQ-ANALOG CONVERTERS
-Vs
±1V
SINE WAVE
AD7245/AD7248
MICROPROCESSOR INTERFACING - AD7245
AD7245 - 8086A INTERFACE
Figure 12 shows the 8086 16-bit processor interfacing to the
AD7245. In the setup shown the double-buffering feature of the
DAC is not used and the LDAC input is tied LOW. ADO-ADII
of the 16-bit data bus are connected to the AD7245 data bus
(DBO-DBll). The 12-bit word is written to the AD7245 in one
MOV instruction and the analog output responds immediately.
In this example the DAC address is DOOO. A software routine
for Figure 12 is given in Table V.
....
ASSUME DS : DACLOAD, CS : DACLOAD
DACLOAD SEGMENT AT 000
00 8CC9
: DEANE DATA SEGMENT
REGISTER
: EQUAL TO CODE
SEGMENT REGISTER
: LOAD DI WITH DOOO
MOVCX,
CS
MOVDS,
02 8ED9
ex
04 BFOODO
07 C705
"YZWX"
OB EAOOOO
OE OOFF
MOVDI,
#DOOO
MOVMEM,
#YZWX
: DAC LOADED WITH WXYZ
: CONTROL IS RETURNED TO
THE MONITOR PROGRAM
Table V. Sample Program for Loading AD7245 from 8086
ALE
A0724S*
In a multiple DAC system the double-buffering of the AD7245
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropriate
address, CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.
AD15
ADO
AD7245 - MC68000 INTERFACE
Interfacing between the MC68000 and the AD7245 is accomplished
using the circuit of Figure 14. Once again the AD7245 is used
in the single-buffered mode. A software routine for loading data
to the AD7245 is given in Table VI. In this example the AD7245
is located at address EOOO, and the 12-bit word is written to the
DAC in one MOVE instruction.
I-----=.:"""='---'---'-------J
·LlNEAR CIRCUITRV OMITTED FOR CLARITY.
Figure 72. AD7245to8086lnterface
)
ADDRESS BUS
MC68000
8086
J
ALE
AS
Il
DTACK
AD724S*
~
.,J
RJW
I
ADDRESS
DECODE
rl
I
cs
~
""'
1
ADOI-----~-,-~~~
AD724S"
Wil
Ji
D'S
UiAC
DATA BUS
D.
DB11
DB.
C,
-LINEAR CIRCUITRY OMmED FOR CLARITY,
AD724S*
"LINEAR CIRCUITRY
OMITTED FOR
CLARITY.
Figure 74. AD7245to68000lnterface
01000
MOVE.W
#X,DO
MOVE. W
DO,$EOOO
MOVE.B
#228,D7
TRAP
#14
AD724S*
Figure 73. AD7245to8086MultipleDAClnterface
The desired DAC data, X,
is loaded into Data RegisterO. X maybe any
value between 0 and 4095
(decimal) or 0 and OFFF
(hexadecimal).
The Data X is transferred
between DO and the
DACLatch.
Control is returned to the
System Monitor Program
using these two
instructions.
Table VI. Sample Routine for Loading AD7245 from 68000
DIGITAL- TO-ANALOG CONVERTERS 2-233
IJ
MICROPROCESSOR INTERFACING - AD7248
Figure 15 shows the connection diagram for interfacing the
AD7248 to both the 8085A and 8088 microprocessors. This
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demutiplexed. Data to be
loaded to the AD7248 is right-justified. The AD7248 is memory
mapped with a separate memory address for the input latch
high byte, the input latch low byte and the DAC latch. Data is
first written to the AD7248 input latch in two write operations.
Either the high byte or the low byte data can be written first to
the AD7248 input latch. A write to the AD7248 DAC latch
address transfers the input latch data to the DAC latch and
updates the output voltage. Alternatively, the LDAC input can
be asynchronous or can be common to a number of AD7248s
for simultaneous updating of a number of voltage channels.
An interface circuit for connections to the 6502 or 6809 microprocessors is shown in Figure 17. Once again, the AD7248 is
memory mapped and data is right-justified. The procedure for
writing data to the AD7248 is as outlined for the 8085N8088.
For the 6502 microprocessor the <1>2 clock is used to generate
the WR, while for the 6809 the E signal is used.
i
ADDRESS BUS
AG-Al5
..l
~
CSlSB
CSMSB
LDAC
EN ~~~~ES
Rm
6502l6S09
AD724S'
WR
<1>2 OR E
0A~A15
DG-D7
ALE
DBG-DB7
II
ADDRESS BUS
"
(
DATA BUS
"LINEAR CIRCUITRY OMITTED FOR
C~RITY.
SOS5A/SOSS
AD724S*
1 - - - - - - - - - 1 WR
...----...1 DBG-DB7
ADG-AD7
ADDRESS/DATA BUS
~_ _~~"-l-IN~E-AR-C~I-RC-U~IT~R-Y~O~M~ln~ED~F~O~R~C~~~R=IT=y~.---J
Figure 15. AD7248 to B085AIBOBBlnterface
A connection diagram for the interface between the AD7248
and 68008 microprocessor is shown in Figure 16. Once again,
the AD7248 acts as a memory mapped device and data is rightjustified. In this case the AD7248 is configured in the automatic
transfer mode 'which means that the high byte of the input latch
has the same address as the DAC latch. Data is written to the
AD7248 by first writing data to the AD7248 low byte. Writing
data to the high byte of the input latch also transfers the input
latch contents to the DAC latch and updates the output.
Figure 17. AD7248t06502l68091nterface
Figure 18 shows a connection diagram between the AD7248 and
the 8051 microprocessor. The AD7248 is port mapped in this
interface and is configured in the automatic transfer mode. Data
to be loaded to the input latch low byte is output to Port 1.
Output Line P3.0, which is connected to CSLSB of the AD7248,
is pulsed to load data into the low byte of the input latch. Pulsing
the P3.1 line, after the high byte data has been set up on Port
I, updates the output of the AD7248. The WR input of the
AD7248 can be hardwired low in this application because spurious
address strobes on CSLSB and CSMSB do not occur.
P3.0
CSLSB
P3.1
CSMSB
S051
~
P1.0
Al9
AS
68008
RIW
DTACK
J
DB1
DB2
P1.3
DB3
P1.4
DB4
lDAC
P1.5
Uds-rr-
DB5
WR
P1.&
DB&
P1.7
DB7
CSlSB
[
L
CSMSB
AD7248'
'-
07
DATA BUS
DBG-DB7
II
DO "LINEAR CIRCUITRY OMlnED FOR
DBO
P1.2
\
1 t,.
ADDRESS
LDAC
WR
P1.1
ADDRESS BUS
AO
L
AD7248*
'ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 18. AD7248toMCS-51Interface
C~RITY.
Figure 16. AD7248to68008lnterface
2-234 DIGITAL-TO-ANALOG CONVERTERS
~
r-IIANALOG
WDEVICES
CMOS
8-Bit Buffered Multiplying OAC
A07524
FEATURES
Microprocessor Compatible (6800,8085, Z80, Etc.)
TTLICMOS Compatible Inputs
On-Chip Data Latches
End Point Linearity
Low Power Consumption
Monotonicity Guaranteed (Full Temperature Range)
Latch Free (No Protection Schottky Required)
I
AD7524 FUNCTIONAL BLOCK DIAGRAM
Voo
APPLICATIONS
Microprocessor Controlled Gain Circuits
Microprocessor Controlled Attenuator Circuits
Microprocessor Controlled Function Generation
Precision AGC Circuits
Bus Structured Instruments
DB7
DB6
DB5
(MSB)
DATA INPUTS
GENERAL DESCRIPTION
The AD7524 is a low cost, 8-bit monolithic CMOS DAC
designed for direct interface to most microprocessors.
ORDERING INFORMATION I
Basically an 8-bit DAC with input latches, the AD7524's load
cycle is similar to the "write" cycle of a random access memory. Using an advanced thin-film on CMOS fabrication
process, the AD7524 provides accuracy to 1I8LSB with a
typical power dissipation of less than 10 miIIiwatts.
Nonlinearity
(VDD = +l5V)
A newly improved design eliminates the protection Schottky
previously required and guarantees TTL compatibility when
using a +5V supply. Loading speed has been increased for
compatibility with most microprocessors.
Featuring operation from +5V to +15V, the AD7524 interfaces directly to most microprocessor buses or au tpu t ports.
Excellent multiplying characteristics (2- or 4-quadrant) make
the AD7S24 an ideal choice for many microprocessor controlled gain setting and signal control applications.
Temperature Range and Package Options2 ••
-40°Cto +85 oC
-40°C to
+ 85°C
Plastic DIP (N-16) Hermetic (Q-16)
± 112LSB
± 114LSB
± 118LSB
± 112LSB
± 114LSB
± 118LSB
AD7524JN
AD7524KN
AD7524LN
AD7524AQ
AD7524BQ
AD7524CQ
-SSOCto
+ 125°C
Hermetic (Q-16)
AD7524SQ
AD7524TQ
AD7524UQ
PLCC' (P-20A)
LCCC5 (E-20A)
AD7524JP
AD7524KP
AD7524LP
AD7524SE
AD7524TE
AD7524UE
NOTES
ITo order MIL-STD-883, Class B processed parts, add/883B to part number.
Contact your local sales office for military data sheet. For U.S. Standard
Military Drawing (SMD) see DESC drawing #5962-87700.
2See Section 14 for package outline information.
3Also available in SOlC package (AD7524JR).
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: LeadIess Ceramic Chip Carrier.
DIGITAL-TO-ANALOG CONVERTERS 2-235
SPECIFICATIONS
(VIIS'
= + lOY, Youn = YOUl7 = OY unless otherwise noted)
LIMIT, TA ""
PA!{AMETER
+zsoc
Von· +5V Von - +1SV
STATIC PERFORMANCE
Resolution
LIMJr, TMIN, TMAXI
VDD = +lSV
Voo = 5V
8
UNITS
TEST CONDITIONS/COMMENTS
Bits
Relative Accuracy
J. A, S Versions
±1/2
±1/2
K, B. T Versions
guaranteed
±21/2
±4O
±1/2
±1/4
±1/8
guaranteed
±11/4
±IO
±1/2
±1/2
±1/2
guaranteed
±3 1/2
±40
0.08
0.002
0.02
0.001
±50
±50
±1/2
L, C, U Versions
Monotonicitv
Gain Error2
Average Gain Te 3
de Supply Rejection,' &:iain/~VDD
Output Leakage Current
lOUT! (Pin 1)
lOUT> (Pin 2)
DYNAMIC PERFORMANCE
Output Current Settling lime3
(ta 1/2 LSB)
±1/2
±1/4
±1/8
LSB max
LSB max
LSB max
guaranteed
±11/2
±1O
LSD max
ppmtC
0.16
0.01
0.04
0.005
% FSRI% max
% FSRI%typ
±SO
±SO
±400
±400
±200
±200
nAmax
400
250
500
350
Dsmax
OUT1 Laad = lOOn, CEXT = 13pF; WR, Cs =
OV;DBo-DB7 = OV taVoo to OV.
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
% FSRmax
% FSRmax
VREL.:" ±1QV, 100kHz sine wave; DBo-OB7 '"
OV;WR, CS=OV
5
20
5
20
5
20
kOmin
20
120
30
30
120
120
30
30
120
120
30
30
120
120
30
30
120
nAmax
Gain TC measured from +2SoC to
Tmin or from +2SOCtoTmax
"'VOO =±10%
DBO-DB7 =OV; W&,C~OV; VREF =±10V
DBo-DB7= VDD; WR, CS=OV; VREF ±IOV
=
ac Feedthrough3
atOUTl
atOUT2
REFERENCE INPUT
RIN (pin 15 ta GND)4
knmax
ANALOG OUTPUTS
Output CapacitanceS
CoUTI (pin 1)
CoUT2 (pin 2)
CoUTI (pin 1)
CoUT2 (pin 2)
DIGITAL INPUTS
pFmax
p.Fmax
pFmax
pFmax.
. DBo-DB7 = Voo; WR, Cs' = OV
DBo-DB7 = OV;WR, Cs = OV
Input HIGH Voltage Requirement
VIH
+2.4
+13.5
+2.4
+13.5
V min
+0.8
+1.5
+0.8
... 5
Vma><
±1
±l
±10
±10
p.A
5
20
5
20
5
20
5
20
pFmax
pFmax
170
170
100
100
220
240
130
150
nsmin
nsmin
0
0
nsmin
Input LOW Voltage Requirement
VIL
Input Current
lIN
max
, VIN = OV or VDD
Input Capacitance 3
DBo-DB7
WR, Cs'
VIN =OV
YIN =OV
SWITCHING CHARACTERISTICS
Chip Select to Write Setup TimeS
tes
AD7S24J, K, L, A, B, C
AD7S24S, T, U
See timing diagram
'wR = tes
Chip Select to Write Hold Time
teH
All Grades
Write Pulse Width
'wR
AD7S24J, K, L, A, B, C
AD7S24S, T, U
tes;:' 'wR, tCH ;:. 0
170
170
100
100
220
240
130
150
nsmin
nsmin
'135
135
60
60
170
170
80
100
nsmin
nsmin
10
10
10
10
nsmin
1
100
2
100
500
2
500
mAmax
IlAmax
Data Setup Time
tos
AD7S24J, K, L, A, B,C
AD7524S, T, U
Data Hold Time
tOH
All Grades
POWER SUPPLY
100
NOTES
I Temperature ranges as follows:
J. K. L versions: -40oC to +8SoC
A. B. C versionsl -40°C to +8S oC
S. T, U versions; -SSoC to +12SoC
~Gain error is measured using internal feedback resistor. Fun Scale Range: (FSR) = VREF.
:JGuaranteed. Dot tested.
4DAC thin.film resistor temperature coefficient is approximately -30OppmfC .
• AC pa.nrneter, sample tested@ 2SoC to cnlllle coofonnance to specifkarlons.
2-236 DIGITAL-TO-ANALOG CONVERTERS
All Digital Inputs VIL or VIH
All Digital Inputs OV or VDD
AD7524
ABSOLUTE MAXIMUM RATINGS·
= + 25"C unless otherwise noted)
(TA
Vooto GND
VRFB to GND . . . . . . . . .
VREF to GND . . . . . . . . .
Digital Input Voltage to GND
OUTI, OUT2 to GND . . . .
Power Dissipation (Any Package)
To +7SoC . . . . . .
Derates above 75°C by
Operating Temperature
Commerical (1, K, L) .
Industrial (A, B, C)
Extended (S, T, U) ..
Storage Temperature ..
Lead Temperature (Soldering, IOsecs)
-O.3V, + 17V
. . . . ±2SV
. . . . ±2SV
-O.3V to Voo +O.3V
-O.3V to Voo +O.3V
·Stresses above those listed under "Absolme Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
4S0mW
6mWf'C
- 40°C to + 85°C
- 40°C to + 85°C
- 55°C to + 125°C
- 65°C to + 150°C
. . . . . +300°C
WARNING!
0
~~:EJlCE
TERMINOLOGY
measured with allIs in the DAC after offset error has been
adjusted out and is expressed in LSBs. Gain Error is adjustable to zero with an external potentiometer.
RELATIVE ACCURACY. A measure of the deviation from
a straight line through the end points of the DAC transfer
function. Normally expressed as a percentage of full scale
range. For the AD7524 DAC, this holds true over
the entire VREP range.
FEEDTHROUGH ERROR. Error caused by capacitive
coupling from VREP to output with all switches OFF.
OUTPUT CAPACITANCE. Capacity from OUTI and OUT2
terminals to ground.
RESOLUTION. Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2-n ) (VREP). A
bipolar converter of n bits has a resolution of [2-(n-l»)
[VREP). Resolution in no way implies linearity.
OUTPUT LEAKAGE CURRENT. Current which appears on
OUTl terminal with all digital inputs LOW or on OUT2
terminal when all inputs are HIGH. This is an error current
which contributes an offset voltage at the amplifier output.
GAIN ERROR. Gain Error is a measure of the output error
between an ideal DAC and the actual device output. It is
PIN CONFIGURATIONS
DIP
PLCC
I:!
l'
:> :>
LCCC
0
0
"z J J
3
2
1
20
,.
I:!
l'
:> :>
0
v=
TOP VIEW
(Not to Scale)
DBS
01 I:l
!;1 :;!
Q
Q
i!l
'
18 VOD
17
DBS 8
NC == NO CONNECT
,.J
AD7524
TOP VIEW
INot to Scale)
DB6 7
OBO (LSBI
"z1 2.J
.., ,,
DB7 fMSBI 5
Os
"
Q
2
NC.
•
NC= NO CONNECT
0
3
GND 4
WR
AD7524
0
.
• ,I:l
~
Q
WR
16 Ne
15
cs
14 DBO (LSBI
11 12 13
"
Z
Ii!Q QOJ
DIGITAL-TO-ANALOG CONVERTERS 2-237
II
CIRCUIT DESCRIPTION
CIRCUIT INFORMATION
The AD7524, an 8-bit multiplying D/A converter, consists of
a highly stable thin film R-2R ladder and eight N-channel
current switches on a monolithic chip. Most applications require the addition of only an output operational amplifier and
a voltage or current reference.
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used - that is, the binarily weighted
currents are switched between the OUTl and OUT2 bus lines,
thus maintaining a constant current in each ladder leg independent of the switch state.
icy at the DBo-DB7 data bus inputs. In this mode, theAD7524
acts like a nonlatched input D/A converter.
HOLD MODE
When either CS or WR is HIGH, the AD7S24 is in the
HOLD mode. The AD7S 24 analog ou tput holds the value corresl!2.ndini.!0 the last digital input present at DBo-DB7 prior
to WR or CS assuming the HIGH state.
MODE SELECTION TABLE
CS
-WR
MODE
L
L
Write
DAC responds to data bus
(DBO - DB7) inputs
H
X
Hold
Data bus (DBO - DB7) is
locked out;
X
H
Hold
DAC holds last data present
when WR or CS assumed
HIGH state.
DAC RESPONSE
~-+~~-rT4~'7--+~~----~OUT2
~--~~---4-r~r-~~--,---~OOUTI
L = Low State, H = High State, X = Don't Care.
RFEEDBACK
WRITE CYCLE TIMING DIAGRAM
~1___
tcs~----:,"I__
tCH.Ir-IIoO0
DB7 (MSB)
DB6
DB5
CHIP SELECT
DBO (LSB)
"
/
Figure 1. AD7524 Functional Diagram
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuit for all digital inputs LOW is shown in
Figures 2. In Figure 2 with all digital inputs LOW, the ref.erence current is switched to OUT2. The current source
ILEAKAGE is composed of surface and junction leakages to
the substrate while the
current source represents a constant l-bit current drain through the termination resistor on
the R-2R ladder. The "ON" capacitance of the output N-channel switches is l20pF, as shown on the OUT2 terminal. The
"OFF" switch capacitance is 30pF, as shown on the OUTl
terminal. Analysis of the circuit for all digital inputs high is
similar to Figure 2 however, the "ON" switches are now on
terminal OUTl, hence the l20pF appears at that terminal.
_-----Voo
WRITE
'-~----"-t-~-------O
...-tDs~tDH
...lI:o:----'""'iiL
DATA IN (OBO - DB7)
_____ 0
k
NOTES:
1. All input signal rise and fall times measured from
10% to 90% of Voo. Voo : +5V, to: tf - 2On.;
Voo = +1SV. t, m tf = 4OnI.
2. Timing Measurement Referenceleval;s VtH
.
~EED8ACK
I~
- ........--..---<
+~!~'-125-6
IV-.
~
"
I
VD~
r<
10
!
-
6511., toH = sOn••
12
R'" 10k
~ VIL
3. tos + tOH is approximately constant at 145ns min
at +25°C, VDO '" +5V and twr = 170nl min. The
AD7524 is specified for a minimum tDH of 10ns,
however. in applications where tDH > 10ns. 'los
may be reduced accordinglv up to the limit tos =
,
.-------~-4---o0~1
V.E.O>--""..
~_--Voo
v•• '~5V
I
=+1SJ
I
TA - +25°C
ALL DIGITAL INPUTS
TIED TOGETHER
1
1.200
1.ooog
\
i
BOIl
i
600
~
"
0(
E
\
j
Figure 2. AD7524 DAC Equivalent Circuit - All Digital
Inputs Low
INTERFACE LOGIC INFORMATION
MODE SELECTION
AD7524 mode selection is controlled by the CS and WR
inputs.
WRITE MODE
When CS and WRare both LOW, the AD7524 is in the WRITE
mode, and the AD7S24 analog output responds to data activ2-238 DIGITAL-TO-ANALOG CONVERTERS
2
V
» \.
\
400
"'"
Figure 3. Supply Current
10
vs.
i"oo..
12
14
VIN. VOLTS
Logic Level
Typical plots of supply current, 100, versus logic input voltage, VIN, for Voo = +SV and Voo = +15V are shown above.
Applying the AD7524
ANALOG CIRCUIT CONNECTIONS
HOY
VREF
"OY
(ec or del
VDU
VREF
VOD
RS ...
DATA
INPUTS
II
NOTES:
GND
,. R1 AND R2 USED ONLY IF GAIN
GND
ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1OpF-16pFI
IS REQUIRED WHEN USING HIGH SPEED
AMPLIFIERS TO PREVENT RINGING OR
GOO
OSCILLA nON.
Figure 4. Unipolar Binary Operation
(2-Quadrant Multiplication)
DIGITAL INPUT
MSB
LSB
11111111
NOTES:
1. ADJUST R1 FOR VOUT = OV AT CODe 10000000.
2. C1 PHASE COMPENSATION (10 -15pFI MAY BE
REQUIRED If A11SA HIGH SPEED AMPLIFIER.
Figure 5. Bipolar (4-Quadrant) Operation
DIGITAL INPUT
ANALOG OUTPUT
-VREF
10000001
-VREF
10000000
-VREF
01111111
-VREF
00000001
-VREF
00000000
-VREF
LSB
MSB
(~)
256
ANAWG OUTPUT
G~~)
(1~8 )
11111111
+VREF
10000001
+ VREF
10000000
o
01111111
-VREF
(1~8)
(2!6 )
00000001
(2~6 )= 0
-VREF
(g~)
00000000
-VREF
128 )
128
(129 )
256
(128)
256
(127 )
256
=_ VREF
2
1
2s6 (VREF )
Table II. Bipolar (Offset Binary) Code Table
Table I. Unipolar Binary Code Table
MICROPROCESSOR INTERFACE
AS-A15
AU-A'S
~-7"
VMAr---.-------~
ALE
8086A
6800
ADO-AD7
Figure 6. AD7524/8085A Interface
00-07
Figure 7. A07524/MC6800 Interface
DIGITAL-TO-ANALOG CONVERTERS 2-239
POWER GENERATION
DATA ~t-=-=~=1.(
INPUT "0"
o-H"'-"=c.t
v,
cso-H-......--<
Wiio-H.....+--<
v,
v.
v,
= -(VREFIIO)
V, • +(VREFIID')
VII· -(VREF) (on). nan odd integer
Vn • +(VREF) (on),n an even integer
WHERE,
-
0- 0:'7+ 0:6+ .. ,':0
OBn =1orO
2-240 DIGITAL-TO-ANALOG CONVERTERS
CMOS Dual 8-Bit
Buffered Multiplying DAC
AD7528 I
ANALOG
WDEVICES
11IIIIIIII
FEATURES
On-Chip Latches for Both DACs
+5V to +15V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTLJCMOS Compatible
Latch Free (Protection Schottkys not Required)
AD7528 FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Digital Control of:
Gain/Attenuation
Filter Parameters
Stereo Audio Circuits
X-V Graphics
GENERAL DESCRIPTION
The AD7528 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
skinny 0.3" wide 20-pin DIPs and in 20-terminal surface mount
packages.
PRODUCT HIGHLIGHTS
1. DAC to DAC matching: since both of the AD7528 DACs are
fabricated at the same time on the same chip, precise matching
and tracking between DAC A and DAC B is inherent.The
AD7528's matched CMOS DACs make a whole new range of
applications circuits possible, particularly in the audio, graphics
and process control areas.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
2. Small package size: combining the inputs to the on-chip
DAC latches into a common data bus and adding a DAC AI
DAC B select line has allowed the AD7528 to be packaged in
either a small 20-pin 0.3" wide DIP or in 20-terminal surface
mount packages.
Data is transferred into either of the two DAC data latches via a
common 8-bit TTUCMOS compatible input port. Control
input DAC AlDAC B determines which DAC is to be loaded.
The AD7528's load cycle is similar to the write cycle of a random
access memory and the device is bus compatible with most 8-bit
microprocessors, including 6800,8080,8085, Z80.
The device operates from a + 5V to
sipating only 20mW of power.
+ 15V power supply, dis-
Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for
each DAC.
PIN CONFIGURATIONS
LCCC
DIP
AGND
0(
~ ~ !:io"
10
OUT B
.....
os
IMBa) DB7
DBO (LSB)
0.,
DB>
0B4
.,
J
3212019
,,
"
...
VREF A 4
Wii
c
PLCC
1
20
3
0(
Q
I-
6 J
,.
18
18 VReF B
AD7528
TOP VIEW
(Not to Scale)
(MBa.DB7 7
2
I-
0
17 Voo
DGNO 5
~AlDAC B 6
.'"
., .,
J 6
2
.
DBa 8
16
\iii
15
cs
AD7528
TOP VIEW
(Not to Scale)
14 DBO fLSB)
9
10 11 12 13
~
Ii
~ ~
!
VAEF B
v..
Wii
OS
OBO ILSBI
ill O! iii III 1iiQ
" " " "
DIGITAL-TO-ANALOG CONVERTERS 2-241
SPECIFICATIONS
..........
(VRfF
VDD = +lSV
TA - +2SOC T ....,T_
Voo = +5V
T A = +2SOC T..ua,T_
Versionl
STATIC PERFORMANCE'
Resolution
Relative Accuracy
+ lOV; OUT A = OUT B = OV unless otherwise specified)
A = VRfF B =
All
I,A,S
±I
±112
±112
±I
K,B,T
L,C,U
All
DifferentialNonlinearity
I,A,S
GainError
±I
±112
±112
±I
±6
±4
±3
Vaits
TestCouditlcmslComm
This is an Endpoint Linearity Specification
±I
±112
±I
Bits
LSBmax
±112
LSBmax
±1I2
±1/2
LSBmax
±I
±I
LSBmax
±4
±2
±I
±5
±3
±I
LSBmax
LSBmax
Measured Using Intema1RFB A andRFB B.
Both DAC Latches Load£d with I III 1111.
LSBmax
Gain Error is Adjustable UsingCircuits
of Figures land2.
%t'Cmax
K,B,T
L,C,U
±4
±2
±I
AU
±O.OO7
±O.OO7
±O.OO35
±O.OO35
AU
All
All
±50
±50
8
IS
±400
±400
8
IS
±SO
±50
8
IS
±200
±200
8
IS
±I
±I
±I
±I
All Grades GuaranteedMonotonicOver
Full OperatingTemperatureRange
Gain TcmperatureCoefficient"
.6.GainI.6.Tempcrature
Output Leakage Current
OUTA(Pin2)
OUT B (PIn 20)
Input Resistance(VREFA, VREFB)
VREFANREFB loput Resistance
Match
All
DIGITAL INPUTS'
loputHigh Vol_
VJH
nAmax
DAC Latches Loaded with OOOOOOOO
oAmax
k.!lmin
k.!lmax
Input Resistance TC - -lOOppmi'C, Typical
Input Resistanceis 11kfi
%max
All
2.4
2.4
13.5
13.5
V min
All
0.8
0.8
1.5
1.5
Vmax
Input Low Voltage
V,L
InputCurrent
lIN
All
±I
±lO
±I
±lO
,.Amax
All
All
10
IS
10
IS
10
IS
10
IS
pFmax
pFmax
All
200
230
60
80
DSntin
All
20
30
10
IS
nsmin
All
200
230
60
86
nsmin
All
20
30
10
IS
nsmin
All
110
130
30
40
nsmin
All
186
200
60
86
nsmin
All
All
2
100
2
500
2
100
2
mAmax
500
~Amu
V1N=OorVDD
Input Capacitance
DBG-DB7
WR,Cs,DACAlDACB
SeeTimingDiagram
SWITCHING CHARACTERISTICs'
Chip Se1ect to Write Set Up Time
tc::s
Chip Select to Write Hold Time
t<':11
OAC Select to Write SetUpTime
lAS
DAC Select to Write Hold Time
tAM
Data ValidtoWriteSetU'pTime
tDS
Data Valid. to Write Hold Time
tOR
All
nsmin
Write Pulse Width
t...
POWER SUPPLY
100
All Digital Inputs VtL orVm
AU Digital InputsOV or Voo
AC PERFORMANCE CHARACTERISTICS5 ~a:. =ut~:m= Output Amplifiers)
Von
p-
Venioa1
= +sv
TA = +25OC Taaia,T_
Voo = +15V
TA = +2SOC T ...,T_
Units
TestConditiOJl8lComm.eJdIi
0.01
0.02
% per % max
AVoo - ±S%
To 1I2LSB. OutAlOutB load 10011.
Wi = Cs = OV.DBO-DB7 = OV to VDD orVDD toOV
DCSUPPLY REJECITON (aGAIN/aVDD)
All
0.02
0.04
CURRENT SETTLING TIME'
All
350
400
180
200
os ....
PROPAGATION DELAY (FromDigiIal
Input to 9O%ofFioaiAnalog Output Current)
All
220
270
86
100
osmax
DIGITAL TO ANALOG GLITCH IMPULSE
All
160
-
440
-
nVsectyp
ForCode Transition 0000000010 11111111
All
SO
50
120
120
SO
50
SO
120
120
pFmax
pFmax
pFmax
pFmax
DACLatchesLoad£dwithOOOOOOOO
120
120
50
50
120
120
-70
-65
-65
-70
-70
-65
-65
dB ....
dBmax
VREFA, VREFB = 20V~pSineWave
@IOOkHz
-77
-
-n
dBtyp
-n
-
-n
-
-
60
OUTPUTCAPACITANCE
CoUTA
CoUTB
CoUTA
CoUTB
ACFBEDTHROUGH
VREF A toOUTA
V... Bto OUTB
CHANNEL TOCHANNBLlSOLATION
VREFA toOUTB
All
All
VREFB to OUT A
-70
DIGITAL CROSSTALK
All
30
HARMONIC DISTORTION
All
-85
...
NOTES
ITempemureRanptueJ.K. L Versions; -4O"Cto + 85"C
A,B,evasions; -4O"Cto +8S"C
S.T.UVcrtiooa; -5S"Cto+12S"C
so
lspecificaticm applies to boI:h DACs ill AD7S28.
-85
-
~illputlareMOSGues. Typic:aIiDputcurrClIl( + 2S"C)islesscban lIlA.
4Guarantecd by deaip bul ROC production 1CItCd.
2-242 DIGITAL-TO-ANALOG CONVERTERS
VREFA = VREPB = + 10V
OUT A,OUTBLoad - lOOIlCEXT - 13pF
WR,CS = OVDBO-DB7 "" OVtoVDDOI'VDOtoOV
DAC Latches Loaded with 11111111
'Both DAC Latches Loadeci with 11111111.
nVsectyp
VREFA = 2OVp-pSineWave@I00kHz
VREPB - OV.
VREPB "" 2OVp-pSincWave@lookHz
VREFA ""_OV.
Measured forCodeTransitionOOOOOOOOto 11111111
dBtyp
VIN -6Vrms@lkHz
dBtyp
snc.edlaracterisbcaaM fordcsip pidancc only aDd. are DOt subjectto lest.
Specific:atioDal1lbjecttodlaqcwilhoutnoticc.
AD7528
INTERFACE LOGIC INFORMATION
DAC Selection:
Both DAC latches share a common 8-bit input port. The control
input DAC A IDAC B selects which DAC can accept data from
the input port.
Mode Selection:
Inputs CS and WR' control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode:
When CS and WR are both low the selected DAC is in the
write mode. The input data latches of the selected DAC are
transparent and its analog output responds to activity on DBODB7.
Hold Mode:
The selected DAC latch retains the data which was present
on DBO-DB7 just prior toCS or WR assuming a high state.
Both analog outputs remain at the values corresponding to the
data in their respective latches.
NOTES:
1. ALL INPUT stGNAL RISE AND FAU TIMES
MEASURED FROM 10% TO 90% OF V DD•
VOD +5V,t, = t,= 20ns;
=
Voo = + 15V, t, = t, '" 4On5.
2. TIMING MEASUREMENT REFERENCE LEVEL IS ~~
ABSOLUTE MAXIMUM RATINGS
DACAl
DACB
CS
L
H
X
X
L
L
L
H
X
= Low State
WR
L
L
X
H
H = High State X
DACA
WRITE
HOLD
HOLD
HOLD
(T A =
DACB
HOLD
WRITE
HOLD
HOLD
= Don't Care
Mode Selection Table
CAUTION: ______________________________
I. ESD sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected
devices subjected to high energy electrostatic fields. Unused
devices must be stored in conductive foam or shunts.
2. Do not insert this device into powered sockets. Remove power
before insertion or removal.
+ 25"<: unless otherwise noted)
Voo to AGND .
. OV, + 17V
VOO to DGND .
. OV, + 17V
AGND to DGND
VOO +0.3V
DGND to AGND
VOO +0.3V
Digital Input Voltage to DGND
-O.3V, VOO +0.3V
-0.3V, Von +O.3V
VP1N2 , VP1N20 to AGND . .
VREF A, VREF B to AGND . . . . . . . . . . . . . .. ;t 25V
VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . ±25V
450mW
Power Dissipation (Any Package) to +75°C
Derates above + 75°C by . . .
6mW/oC
Operating Temperature Range
-40°C to + 85·C
Commercial (1, K, L) Grades.
Industrial (A, B, C) Grades.
- 40°C to + 85°C
- 55°C to + 125°C
Extended (S, T, U) Grades ..
-65°C to + 150°C
Storage Temperature . . . . . .
Lead Temperature (Soldering, 10 sees.) .
. . . . , +300°C
ORDERING INFORMATION l
Relative
Accuracy
Gain
Error
TA = +25°C
Temperature Range and Package Options2 , 3
-4O"Cto
+ 85·C
-40·Cto
+ 85·C
-55·Cto
+125·C
Plastic DIP (N-20) Hermetic (Q-20) Hermetic (Q.20)
±ILSB
±1I2LSB
±1I2LSB
±4LSB
±2LSB
±ILSB
AD7528JN
AD7528KN
AD7528LN
PLCC4 (P.20A)
±ILSB
±1I2LSB
±1I2LSB
±4LSB
±2LSB
±lLSB
AD7528JP
AD7528KP
AD7528LP
AD7528AQ
AD7528BQ
AD7528CQ
AD7528SQ
AD7528TQ
AD7528UQ
LCCC5 (E.20A)
AD7528SE
AD7528TE
AD7528UE
NOTES
'To order MIL-STD·883, Class B processed parts, addI883B to part number.
Contact your local sales office for military data sheet. For U.S. Standard
Military Drawing (SMD), see DESC drawing #5962-87701.
'See Section 14 for package outline information.
3Also available in
package (AD7528KR, AD7528LR).
4pLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
sorc
DIGITAL-TO-ANALOG CONVERTERS 2-243
Applying the AD7528
NOTES:
'RI, R2' AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE 3 FOR RECOMMENDED VALUES.
"CI, C2 PHASE COMPENSATION IIOpF-15pF) IS REQUIRED WHEN
USING HIGH SPEED AMPUFIERS TO PREVENT RINGING OR
OSCILLATION.
Figure 1. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table I.
DATA
INPUTS
NOTES:
'RI, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
SEE TABLE 3 FOR RECOMMENDED VALUES.
ADJUST RI FOR VOUT A = OV WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR VOUT B = OV WITH CODE 10000000 IN DAC B LATCH.
'MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7
AND R9, RIO.
'CI, C2 PHASE COMPENSATION IIOpF-15pF) MAY BY REQUIRED IF AIIA3
IS A HIGH·SPEED AMPUFIER.
Figure 2. Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table II.
DAC Latch Contents
MSB
LSB
Analog Output
(DACA orDAC B)
DAC Latch Contents
MSB
LSB
Analog Output
(DAC A or DAC B)
I I I I I I I I
11111111
+ VIN (127)
128
1000000 I
10000001
+VIN(I~8)
10000000
10000000
0
oI
I I I I I I
01111111
-VIN(I~8)
00000001
00000001
27 )
- VIN 128
00000000
00000000
28
-VIN 128
)
Note: lLSB
e
e
= (2'~(VIN) = 2~6(VIN)
Table I. Unipolar Binary Code Table
Table II. Bipolar (Dffset Binary) Code Table
Trim
Resistor
RI;R3
R2;R4
LlCIU
JIAlS
Ik
500
200
330
ISO
82
Table III. Recommended Trim Resistor Values vs, Grade
2-244 DIGITAL-TO-ANALOG CONVERTERS
CMOS Low Cost
1O-Bit Multiplying OAC
AD7533 I
rIIIANALOG
WDEVI,CES
AD7533 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Lowest Cost 10-Bit DAC
Low Cost AD7520 Replacement
Unearity: 112. 1 or 2LSB
Low Power Dissipation
Full Four-Ouadrant Multiplying DAC
CMOSfTTL Direct Interface
Latch Free (Protection Schottky not Required)
End-Point Linearity
APPUCATIONS
Digitally Controlled Attenuators
Programmable Gain Amplifiers
Function Generation
Unear Automatic Gain Control
~-+~--~~----t+'-----~~un
~---4h--""'-i---""-i-"'"""t----oIOUT'
I
I
I
o
I
RFEEOBACK
0
BIT 1 (MSB)
BIT 2
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
Logic: A switch is closed to Ioun for its digital input in a
"HIGH" state.
GENERAL DESCRIPTION
The AD7533 is a low cost lO-bit 4-quadrant multiplying DAC
manufactured using an advanced thin-film-on-monolithic-CMOS
wafer fabrication process.
Pin and function equivalent to the industry standard AD7S20,
the AD7S33 is recommended as a lower cost alternative for old
AD7S20 sockets or new 100bit DAC designs.
AD7533 application flexibility is demonstrated by its ability to
interface to TTL or CMOS, operate on + SV to + ISV power,
and provide proper binary scaling for reference inputs of either
positive or negative polarity.
ORDERING INFORMATION1,l
Temperature Range and Package Options'
Nonlinearity
- 4O"C to
+ 85'C
-40"Cto
+ 85'C
- 5S'C to
+ 12S'C
Plastic DIP (N-16) Hermetic (Q-16) Hermetic (Q-16)
±O.20/0
±O.IO/O
±O.O50/0
AD7533JN
AD7533KN
AD7533LN
PLCC4 (P-20A)
LCCC5 (E-20A)
±O.20/0
±O.IO/O
±O.O50/0
AD7533JP
AD7533KP
AD7533LP
AD7533SE
AD7533TE
AD7533UE
AD7533AQ
AD7533BQ
AD7533CQ
AD7533SQ
AD7533TQ
AD7533UQ
NOTES
ITo order MIL-STD-883, Class B processed parts, add 1883B to part number.
Contact your local sales office for military data sheet.
2Analog Devices reserves the right to ship ceramic (package outline D-16)
packages in lieu ofcerdip (package oudine Q-16) packages,
3See Section 14 for package outline information.
4PLCC: Plastic Leaded Chip Carrier.
sLeCC: Leadless Ceramic Chip Carrier.
DIGITAL- TO-ANALOG CONVERTERS 2-245
SPECIFICATIONS IV... =+15Y; Yaun =Yam =OV; Y =+ lOY llllessolhanWse
REf
PARAMETER
=
noIIId)
Test Conditions
TA=lS"C
TA OperatiDg Range
lOBits
lOBits
± 0.2% FSR max
±O.l%FSRmax
±0.05%FSRmax
±1.4%FSmax
±0.2%FSRmax
±O.l%FSRmax
± 0.05% FSRmax
±1.5%FSmax
Digital Inputs = VINH
0.005%1%
O.OOS%I%
DigitalInputs=VINH;VDD = + l4Vto + 17V
±50nAmax
±50nAmax
±200nAmax
±200nAmax
Digital Inputs = VINL; VREP = ± lOY
Digital Inputs = VINH;VREP = ± lOY
600nsmax4
sOOnss
±0.05%FSRmaxS
±O.l%FSRmaxs
To 0.05% FSR; RLOAD = loon; Digital
Inputs = VlNHto VINL or VINL to VINH
Digital Inputs = VINL; VREP = ± 10V,
100kHz sine wave.
REFERENCE INPUT
Input Resistance (Pin 15)
5kOmin, 20kO max
5kOmin, 20kO~
ANALOG OUTPUTS
Output Capacitance
CourJ
CoUT2
lOOpFmaxS
35pFmaxS
lOOpFmaxS
35pFmaxs
Digital Inputs = VINH
35pFmax'
lOOpFmaxS
35pFmax'
lOOpFmaxs
Digital Inputs = VINL
2.4Vmin
2.4Vmin
O.SVmax
O.SVmax
±lfolAmax
±lfolAmax
SpFmaxS
SpFmaxS
+15V ±lo%
+5Vto +16V
2mAmax
+15V ±lo%
+5Vto +16V
STATIC ACCURACY
Resolution
Relative AccuracyJ
AD7533]N,AD, SD,AQ, SQ
AD7S33KN,BD, TD,BQ, TQ
AD7533LN, CD, UD, CQ, UQ
Gain Errorl,3
Supply Rejection4
AGainlAVDD
Output Leakage Current
lourJ
loUT2
DYNAMIC ACCURACY
Output Current Sett1ingTime
Feedthrough Error
Courl
CoUT2
DIGITAL INPUTS
Input High Voltage
VINH
Input Low Voltage
VINL
Input Leakage Current
lIN
Input Capacitance
CIN
POWER REQUIREMENTS
VDD
VDDRange'
IDD
NOTES
'''FSR'' is Full-Scale Range.
'Full ScaIe(FS) = (VRBP)
'Max gain c/wiaefromTA = + 2S"C to T .... orT.... is ±O.I%FSR.
4AC parameter, sample tested to ensure specification compliance.
sGuaranteed, not tested.
• Absolute temperaJUrecoefficient is approximately - 3OOppmI"C.
Specifications subject to cbaDge without notice.
2-246 DIGITAL-TO-ANALOG CONVERTERS
2mAmax
VIN=OVandVDD
Rated Accuracy
Functionality with Degraded Performance
Digital Inputs = VINL or VINH
AD7533
ABSOLUTE MAXIMUM RATINGS·
(TA = + 25°C unless otherwise noted)
Vooto GND
RFB to GND
VREFtO GND
Digital Input Voltage Range
OUT I, OUT 2 t~ GND ..
Power Dissipation (Any Package)
To +7SoC . . . . . . .
Derates above + 75°C by . . . .
Operating Temperature Range
Commercial (J, K, L Versions)
Industrial (A, B, C Versions
Extended (S, T, U Versions) .
Storage Temperature . . . . . .
Lead Temperature (Soldering, 10sec)
-O.3V, + 17V
. . . . ±25V
. . . . ±2SV
-O.3V to Voo +O.3V
-O.3V to Voo +O.3V
- 40°C to + 85°C
- 40°C to 4- 85°C
- 55°C to + 125°C
- 65°C to + 150°C
. . . . . +300°C
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
450mW
6mWrC
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
TERMINOLOGY
GAIN ERROR: Gain error is a measure of the output error
between an idea1 DAC and the actua1 device output. It is measured
with all 1s in the DAC after offset error has been adjusted out
and is expressed in Least Significant Bits. Gain error is adjustble
to zero with an extema1 potentiometer.
RELATIVE ACCURACY: Relative accuracy or end-point
DODIinearity is a measure of the maximum deviation from a
straight line passing through the endpoints of the DAC transfer
function. It is measured after adjusting for idea1 zero and full
sca1e and is expressed in % of full-scale range or (sub) multiples
of ILSB.
FEEDTHROUGH ERROR: Error caused by capacitive coupling
from V REF to output with all sWitches OFF.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- D) (VREF). A bipolar
converter ofn bits has a resolution fo [2-(D-l~ (VREF]. Resolution
in no way implies linearity.
OUTPUT CAPACITANCE: Capacity from
terminals to ground.
Iourl and Ioun
OUTPUT LEAKAGE CUlUlENT: Current which appears on
lOUT! termina1 with all digital inputs LOW or on Ioun termina1
when all inputs are HIGH.
SETTLING TIME: Time required for the output function of
the DAC to settle to within 1/2LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
PIN CONFIGURATIONS
DIP
PLCC
LCCC
N
~
&& "Z J )
"FB
3
2
1 20 19
VAEF
""
."
OND 4
VDD
SIT 101LSS)
17 BIT,O ILSB)
AD7633
HC.
BIT 9
TOP VIEW
INot to Scala)
BITZ 7
arra
BIT 7
'8 VDD
'8 VDO
lIT 11MSB) 5
18 NC
lIT!
10 11
=NO CONNECT Ii Ii
"
BIT 0
14 BIT 8
•
• . z ,... ,..
~
NC
HC
TOP VIEW
INottoSca1e1
15 BIT,
14 Brre
8
lIT 'OILSB)
AD7533
9
Ii Ii
Ne = NO CONNECT
10
11
.Ii .
12
13
Ii
DIGITAL-TO-ANALOG CONVERTERS 2-247
II
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
EQUIVALENT CIRCUIT ANALYSIS
The AD7S33, a Io-bit multiplying D/A converter, consists of a
highly stable thin film R·2R ladder and ten CMOS current
The equivalent circuits for alI digital inputs high and alI digital
inputs low are shown in Figures 3 and 4. In Figure 3 with alI
digital inputs low, the reference current is switched to 1oUT2'
The current source I LEAKAGB is composed of surface and junc-
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage or
current reference.
The simplified D/A circuit is shown in Figure 1. An inverted R·
2R ladder structure is used - that is, the binarily weighted
currents are switched between the loUT! and 1oUT2 bus lines,
thus maintaining a constant current in each 1addcr leg independent
of the switch state.
tion leakages to the substrate while the
IO~ current source
represents a constant I·bit current drain through the termination
resistor on the R-2R ladder. The "ON" capacitance of the output
N channel switch is lOOpF, as shown on the 1oUT2 terminal.
The "OFF' switch capacitance is 3SpF, as shown on the IoUTl
terminal. Analysis of the circuit for alI digital inputs high, as
shown in Figure 4, is similar to Figure 3; however, the ''ON''
switches are now on terminal loUT!> hence the lOOpF at that
terminal.
~EEDBACK
L.--+.....-+-t.....--t+_---o IOUT2
r----1r-~-O~n
L..j--.......;.--...i - - - + i -.....--oIoUTl
I
I
o
BIT 1 (MSB)
I
I
R
~
10kn
RFEEDBACK
0
BIT 2
I~
DIGITAL INPUTS (DTLlTTLlCMOS COMPATIBLE)
Figure 1. AD7533 Functional Diagram
One of the CMOS current switches is shown in Figure 2. The
geometries of devices I, 2 and 3 are optimized to make the
digital control inputs DTLrrrUCMOS compstible over the full
military temperature nmge. The input stsge drives two inverters
(devices 4, 5, 6 and 7) which in tum drive the two output N
channels. The "ON" resistances of the switches are binarily
sealed so the voltage drop across each switch is the same. For
example, switch I of Figure 2 was designed for an "ON" resistance
of 200, switch 2 for 400, and so on. For a IOV reference input,
the current through switch I is O.SmA, the current through
switch 2 is O.2SmA, and so on, thus maintaining a constant
IOmV drop across each switch. It is essential that each switch
voltage drop be equal if the binarily weighted current division
property of the ladder is to be maintained.
Figure 3. AD7533 Equivalent Circuit - All Digital Inputs
Low
I!!!!.VREF,o-~~R,!,--.,...----:-,....---,...._-o()~n
r---......,----Ana1ogGlitch Impulse
Measured with VREFA = Va... = OV. IotrrA,louTB
load = loon, CEXT = 13pF. DAC registers alternately
loaded with all Os and allis.
AC Feedthtough4
VREFA to IOUTA
VRBFB to louTB
Power Supply Rejection
.1.GainI.1.Voo
OutpUt Capacitance
CourA
CoUTB
COUTA
CoUTB
ChanneI-to-Channellsolation
VRBFA to IoUTB
VRBFB to lou'fA
-70
-70
-65
-65
dB max
dB max
VaEFA, VaBFB=20Vp-plOkHzsinewa...
DAC registers loaded with all Os.
±0.01
±0.02
% per % max
AVOO=VDDIDIX -VDDmin
70
70
140
140
70
70
140
140
pFmax
pFmax
pFmax
pFmax
DACA,DACBloadedwithallOs
-84
dBtyp
-84
dBtyp
VREFA =20Vp-p 10kHzsinewa.., VRBFB=OV.
Both DACs loaded withailis.
VRBFB= 2OVp-p iOkHzsinewave, VREFA= OV.
Both DACa loaded with allis.
Measured for a Code Ttansition ofall Os to allis.
lourA,lourB load = loon,CEXT = 13pF.
pigital Ctossta1k
nV-styp
OutpUt Noise Voltage Density
(10Hz-100kHz)
2S
Total Harmonic Distortion
-82
NOTES
ITemperaturerangc:asfollows: J~ K, L Versions: -4O"Cto +8SOC.
A~BJCVersions: -4OOCto + 85"C.
S, T, UVersions: -SSOCto + 12S"C.
2Samp1etested at2S"C toeDsurecompiiance.
3Fuoctionalat VDD"" SVwithdegraded specifications.
"'Pin 12 (DGND)onceramic: padtages isc:onnectcd to lid.
SpecificatiOllS subject to change without notice.
2-264 DIGITAL-TO-ANALOG CONVERTERS
DACA, DACB loaded with all Is
Measured between RFBA and lourA or RFB. BOd IoUTB.
FrequencyofmeasurementisIOHz-lookHz.
dBtyp
VIN -6V nus, 1kHz. Both DACs loaded with all Is.
AD7537
TIMING CHARACTERISTICS (Yoo = lD.8V1D l6.5V, V =V = + lOV, 1_ =AGNOA =OV,I_ = AGNDB =OV).
REFA
IIEFB
Parameter
Limit at
T A +250C
Limit at
T A -40°Cto + 85°C
Limit at
T A + 55°C
to + 125°C
Units
Test Conditions/Comments
t)
t2
t3
4
t5
t6
t7
t8
15
15
60
25
0
0
80
80
15
15
80
25
0
0
80
80
30
25
80
25
0
0
100
100
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
Address Valid to Write Setup Time
Address Valid to Write Hold Time
Data Setup Time
Data Hold Time
Chip Select or Update to Write Setup Time
Chip Select or Update to Write Hold Time
Write Pulse Width
Clear Pulse Width
=
=
=
•
NOTE
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS·
(TA = 25°C unless otherwise stated)
-0.3V, + 17V
Voo to DGND . . . . . . . . . . .
VREFA , VREFB to AGNDA, AGNDB
. . . . ±25V
. . . . ±25V
VRFBA , VRFBB to AGNDA, AGNDB
Digital Input Voltage to DGND
-O.3V, Voo +0.3V
-O.3V, VOD +O.3V
louTA, IOUTB to DGND . . . .
AGNDA, AGNDB to DGND
-O.3V, Voo +O.3V
Power Dissipation (Any Package)
To +75°C . . . . . . . . .
4SOmW
6mWrC
Derates above + 75°C . . . . .
Operating Temperature Range
Commercial G, K, L Versions)
- 400C to + SsoC
-40°C to +SsoC
Industrial (A, B, eVersions)
Extended(S, T, UVersions) .
- 55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . . - 65°C to + 150°C
Lead Temperature (Soldering, 10secs)
. . . . . +300°C
·Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of L'lis specification is not implied. Exposure to
absolute maximum rating conditions for extended petiods may affect device
reliability.
t:=',--j
Ao-A1
~
1-":::1
I
I
y;,""Z"V'1'J?)%'1'JV,'1'J,//,'1'JV"r.,//,""Z'"V"JIj :
I I:::"-+"~
DATA
.~
7lv,""Z"'n"V""V""Z"72'Tz'"V""V""/";V"'X
I
---\C"1
.
I
)(i,""Z"'ji.'1'J'ji.""V"r.Z""//'"I/.'1'JV"r.zm7;
:~
t -..=
: t _ - sv
~
~
1"-"-1
~------------~~r:-------r--------,----.:
aLR
------------------------------~\
..
~::
NOTES
1. AJI INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO
90% OF +5V. t.=t,=2OnS.
2. nMING MEASUREMENT REFERENCE LEVEL IS
~
Figure 1. Timing Diagram for AD7537
ORDERING INFORMATION1 ,2
Relative
Accuracy
TmiJr,-T_
Gain
±ILSB
±112LSB
±1I2LSB
± 1I2LSB
±6LSB
±3LSB
±lLSB
±2LSB
±ILSB
±1/2LSB
±112LSB
± 1I2LSB
Error
Tmin-Ttpq
±6LSB
±3LSB
±lLSB
±2LSB
Temperature Range and Package Option.'
Oto +70"C
-25OCto
-SSOCto
+8S'C
+12S'C
Plastic DIP (N-24) Hermetic (Q-24) Hermetic (Q-24)
AD7537AQ
AD7537BQ
AD7537CQ
AD7537JN
AD7537KN
AD7537LN
AD7537SQ
AD7537TQ
AD7537UQ
PLCC4 (P.28A)
LCCC' (E.28A)
AD7537JP
AD7537KP
AD7537LP
AD7537SE
AD7537TE
AD7537UQ
NOTES
ITo order MIL-STD-883, Class B processed parts, addl883B to part number.
Contact your local sales offIce for military data sheet. For U.S. Standard Military Drawing,
se. OESC drawmg #5962-87763.
2Analog Devices reserves the: right to ship ceramic packages in lieu of cerdip packages.
3See Section 14 for package outline: information.
"FLeC: Plastic Leaded Chip Carrier.
sLCCC: Lc:adJess Ceramic Chip Carriei'.
CAUTION
ESD (electrostiltic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
D/G/TAL-TO-ANALOG CONVERTERS 2-265
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the DIA
converters (DAC A) in the AD7537. A similar equivalent
circuit can be drawn for DAC B.
CIRCUIT INFORMATION - D/A SECTION
The AD7537 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows
a simplified D/A circuit for DAC A. In the R-2R ladder,
binary weighted currents are steered between IotlTA and
AGNDA. The current flowing in each ladder leg is constant,
irrespective of switch state. The feedback resistor RFBA is
used with an op amp to convert the current flowing in IotlTA
to a voltage output.
CotlT is the output capacitance due to the N-channel switches
and varies from about 50pF to 150pF with digital input
code. The current source I LKG is composed of surface and
junction leakages and approximately doubles every 10°C. Ro
is the equivalent output resistance of the device which varies
with input code.
R
R
R
2R
2R
2R
S11
S10
so
2R
RFB•
R
R
o-~--~------4----,----~-oAGNDA
L-+--"-l""",:~--~-+--+-"""-o
IOUTA
Figure 3. Equivalent Analog Circuit for DAC A
......--~--_oAGNDA
L----e-4:~----
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5V
CMOS compatible. All logic inputs are static protected MOS
gates with typical input currents of less than InA.
Figure 2. Simplified Circuit Diagram for DAC A
PIN CONFIGURATIONS
DIP
LCCC
v....
Ci
Jj
I.. l!
4
2
3
PLCC
REF
J,K
Param.eter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
+25"C
TI'OiJJT_
Gain Temperature Coefficient3 ;
- - - -....-----oOUT'
;~
r---:t.---......OOUT2
t~ILEAKAGE ~70pF
Figure 3. AD7541A DAC Equiva/ent Circuit All Digita/lnputs
HIGH
2-278 D/GITAL-TO-ANALOG CONVERTERS
RI
R2
JN/AQ/SD KNIBQITD
1000
1000
330
470
Table I. Recommended Trim Resistor Values vs. Grades
Binary Number in
DAC
MSB
LSB
I 1I I
Analog OutpUt, VOVT
1I I I
I 1I I
-ViN(:: )
1000 0000
0000
2048 ) = -1I2VIN
-VIN ( 4096
0000 0000
0001
-VIN(~
0000 0000
0000
)
oVolts
Table If. Unipolar Binary Code Tab/eforCircuit
ofFigure 4
AD7541A
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 5 and Table In illustrate the circuitry and code relationship
for bipolar operation. With a de: referenc:e (positive or negative
polarity) the circuit provides offset biDary operation. With an ac
reference the circuit provides full 4-quadrant multiplication.
With the DAC loaded to 1000 0000 0000, adjust Rl for Your
= OV (alternatively, one can omit Rl and R2 and adjust the
ratio of R3 to R4 for Vour = OV). Full scale trimmiDg can be
accomplished by adjustiDg the amplitude of VRBP or by varying
the value of RS.
As in unipolar operation, Al must be chosen for low Vos and
low lB. R3, R4 and RS must be seIec:ted for matching and
tracking. Mismatch of 2R3 to R4 causes both offset and Full
Scale error. Mismatch of RS to R4 or 2R3 causes Full Scale
error. Cl phase compensation (lOpF to 5OpF) may be required
for stability, depending on amplifier used.
Figure 6. 12-Bit Plus Sign Magnitude Operation
Sign
Bit
Binary Number in
DAC
MSB
LSB
0
1111 1111 1111
+VIN
0
0000 0000 0000
OVOlls
0000 0000 0000
OVolls
1111 111I I I I 1
Analog Output, Your
. (~~)
-VIN·
(!:)
Note: Sign bitof"O"connectsR3toGND.
-FOR VALUES OF R1 AND R2
SEe TABLE 1.
Table IV. 12-Plus Sign Magnitude Code Table for
Circuit of Figure 6
BIT1_SITt2
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
APPLICATIONS IDNTS
Binary Number in
DAC
MSB
LSB
Analog Output, Your
1111 1I 11 1111
( 2047 )
+VIN 2048
1000 0000 0001
+VINCO~8
1000 0000 0000
o1 1 I
1I 11 1111
0000 0000 0000
)
OV
-VIN (
2~8
)
(2048 )
-VIN 2048
Table Iff. Bipolar Code Table for Offset Binary Circuit of
Figure 5
Figure 6 shows an alternative method of achieving bipolar
output. The circuit operates with sign plus mapitude code and
bas the advantage that it gives 12-bit resolution in each quadrant
compared with n-bit resolution per quadrant for the circuit of
Figure 5. The AD7592 is a fully protected CMOS clJaDae-over
switch with data latchea. R4 and RS should match each other to
0.01% to maintain the aa:uracy of the D/A converter. Mismatch
between R4 and RS introduces a gain error.
Output Offset: CMOS D/A converters exhibit a code dependent
output resistance which in tum can cause a code dependent
error voltage at the output of the amplifier. The lIIlIlIimum
amplitude of this offset, which adds to the D/A converter
nonlinearity, is 0.67 Vos where Vos is the amplifier input offset
voltage. To maintain monotonic operation it is recommended
that Vos be no greater than (25 x 1ct6) (VRBP) over the temperature
range of operation. Suitable op amps are AD5l7L and AD544L.
The ADS 17L is best suited for fixed referenc:e applications with
low bandwidth requirements: it bas em-emely low offset (SO""V)
and in most applications will not require an offset trim. The
AD544L bas a much wider bandwidth and higher slew rate and
is recommended for multiplying and other applications requiring
fast settling. An offset trim on the AD544L may be necessary in
some circuits.
DiIital GIitc:hea: One cause of digital glitches is capacitive
coupling from the digital lines to the OUTI and OUT2
terminals. This should be minimiud by screenina the analog
pins of the AD7541A (pins I, 2,17,18) from the digital pins by
a ground track nm between pins 2 and 3 and between pins 16
and 17 of the AD7S4IA. Note how the analog pins are at one
end of the package and separated from the digital pins by VDD
and GND to aid screenina at the board level. On-chip capacitive
coupling can also give rise to c:rosstalk from the digital to analog
sections of the AD7541A, particularly in circuits with high
c:unents and fast rise and fall times.
DIGITAL-TO-ANALOG CONVERTERS 2-279
Tempera~. Coefficients: The gain temperature coefficient of
the AD7S41A has a maximum value of Sppml"C and a typical
value of 2ppml"C. This corresponds to worst case gain shifts of
2LSBs and O.8LSBs respectively over a 100°C temperature
range. When trim resistors RI and R2 are used to adjust full
scale range, the temperature coefficient of Rl and R2 should
also be taken into account. The reader is referred to Analog
Devices Application Note "Gain Error and Gain Temperature
Coefficient of CMOS Multiplying DACs", Publication Number
E630c-S-3f86.
SINGLE SUPPLY OPERATION
Figure 7 shows the AD7S41A connected in a voltage switching
mode. OUT! is connected to the reference voltage and OUT2 is
connected to GND. The DfA converter output voltage is
available at the VREF pin (pin 17) and has a constant output
impedance equal to R LDR • The feedback resistor RFB is not
used in this circuit.
The reference voltage must always be positive. If OUTI goes
more than O.3V less than GND an internal diode will be turned
on and a heavy current may flow causing device damage (the
AD7S41A is, however, protected from the SCR latch-up
phenomenon prevalent in many CMOS devices). Suitable
references include the AD580 and ADS84.
The loading on the reference voltage source is code dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltage at OUTI should remain
within 2.5V of GND, for a VDD of ISV. If VDD is reduced from
l5V or the reference voltage at OUTI increased to more than
2.5V the differential nonlinearity of the DAC will increase and
the linearity of the DAC will be degraded.
SUPPLEMENTAL APPLICATION MATERIAL
For further information on CMOS multiplying D/A converters
the reader is referred to the following texts:
CMOS DAC Application Guide, Publication Number
G8721>-8-1I89 available from Analog Devices.
Gain Error and Gain Temperature Coefficient of CMOS
Multiplying DACs Application Note, Publication Number
E63Oc-5-3/86 available from Analog Devices.
VOUT "" OTO + lOY
------~--------------~----~----~~~~:
Voor :VR;EFI)I1 +R2IR1J WHERE 0===0:5;1
i.e. D IS A FRAcnONAL REPRESENTATION OF THE DIGITAL INPUT
Figure 7. Single Supply Operation Using Voltage Switching
Mode
2-280 DIGITAL-TO-ANALOG CONVERTERS
Analog-Digital Conversion Handbook - available from
Analog Devices, price $32.95.
CMOS
1IIIIIIII ANALOG
WDEVICES
p.P-Compatible 12-Bit OAC
AD7542 I
AD7S42 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Resolution: 12 Bits
Nonlinearity: ±1/2LSB Tmin to Tmax
Low Gain Drift: 2ppml"C typ, 5ppml"C max
Microprocessor Compatible
Full 4-Quadrant Multiplication
Fast Interface Timing
Low Power Dissipation: 40mW max
Low Cost
Small Size: 16-Pin DIP and 20 Terminal Surface Mount
Packages
Latch Free (Protection Schottky Not Required)
GENERAL DESCRIPTION
The AD7S42 is a precision 12-bit CMOS multiplying DAC
designed for direct interface to 4- or 8-bit microprocessors.
The functional diagram shows the AD7S42 to consist of three
4-bit data registers, a 12-bit DAC register, address decoding
logic and a 12-bit CMOS multiplying DAC. Data is loaded
into the data registers in three 4-bit bytes, and subsequently
transferred to the 12-bit DAC register. All data loading or
data transfer operations are identical to the WRITE cycle of a
static RAM. A clear input allows the DAC register to be easily
reset to all zeros when powering up the device.
The AD7542 is manufactured using an advanced thin-film on
monolithic CMOS fabrication process. Multiplying capability,
low power dissipation, +SV operation, small size (16-pin DIP
and 20 terminal surface mount packages) and easy p.P interface
make the AD7S42 ideal for many instrumentation, industrial
control and avionics applications.
ORDERING INFORMATlON 1
Temperature Range and Package Options2 ,3
(Tmin to Tmax)
Gain
Error
+2S oC
Commercial
(Plastic)
o to +70oC
Industrial
(Ceramic)
_25°C to +8S oC
Extended
(Ceramic)
_SSoC to +12SoC
±lLSB
±lLSB
±3LSB
±3LSB
AD7S42]N
AD7S42]P
AD7S42AD
AD7S42AE
AD7S42SD
AD7S42SE
±1/2LSB
±l12LSB
±3LSB
±3LSB
AD7S42KN
AD7S42KP
AD7S42BD
AD7S42BE
AD7S42TD
AD7S42TE
±1/2LSB
±l12LSB
±lLSB
±lLSB
AD7S42GKN
AD7542GKP
AD7S42GBD
AD7542GBE
AD7S42GTD
AD7542GTE
Relative
Accuracy
NOTES
'To order MIL-STD-883 Class B processed partS, addl883B to part number.
'Package Designation: Plastic DIP (N-16); Plastic Leaded Chip Csrrier
(PLeC) (P.20A); Ceramic DIP (D·16); Leadless Ceramic Chip Carrier (LCCC) (E·20A).
'See Section 14 for package outline information.
DIGITAL-TO-ANALOG CONVERTERS 2-281
SPEC IFICATIONS
(VIII
=+ 5V, YREF =+ lOY, Youn =YIIUI2 =OY unless otherwise noted)
LImit At
TA-+2'·C
l'IIrIIme1IIr
ACCURACY
Resolution
Relative Accuracy'
J, A, S Versions
K. B. T Venions
GK. GB. GT Versions
Differential Nonlinearity'
J. A. S Versions
K, B, T Versions
GK. GB. GT Versions
Gain Error!
J,K,A,B,S,T
GK,GB,GT
LlmitAr'
TA • 0, +70· C,
+8'·C
.,z,·c"
Limit At'
TA --SS·C
" +12'·C
UnllI
CondldoJulCommenll
12
12
12
Bill
tl
t112
t112
tl
tll2
tll2
tl
t112
t112
LSBmax
LSBmax
LSBmax
±1
±1
±1
±1
±1
±1
t1
±1
±1
LSBmax
LSBmax
LSBmax
All grades are guaranteed monotonic
TmintoTmax
±3
t1
±4
t1
±4
±2
LSBmax
LSBmax
Using internal Rn only (gain error can b.
trimmed to zero using circuits of Figure 4 " 5)
Gain Temperature Coefficient
~ainlt.Temperature
5
5
5
ppmfCmax
Typical value is 2ppmf C
0.005
0.01
0.01
"per" max
VOO· +4.75Vto +5.25V
10
10
10
10
200
200
nAmax
nAmax
DAC Register loaded with all Os
DAC Register loaded with allIs
To 1I2LSB, OUT110ad 1000. DAC output
measured from falling edge of WR.
VREF t10V, 10kHz sine wave
Power Supply Rejection
~ainlt.Voo
Output Leakage Current
IoUT1
louT2
DYNAMIC PERFORMANCE
Current Settling Time"
Multiplying Feedthrough Error"
REFERENCE INPUT
Input Resistance
2.0
2.0
2.0
"smax
2.5
2.5
2.5
mVp-pmax
8/15/25
8/15/25
8/15/25
kO min/typ/max
75
260
75
260
75
260
75
260
75
260
75
260
pFmax
pFmax
pFmax
pfmax
=
=
ANALOG OUTPUTS
Output earacitance
CoUT!
CoUTI"
COUT2"
CoUT2"
LOGIC INPUTS
VINH (Logic HIGH Voltage)
VINJ- (Logic LOW Voltage)
lIN
C.N (Input Capacitance)"
Input Coding
SWITCHING CHARACTERISTICS'
tWR
tAWH
tcwH
tcLR
tcws
tAWS
tos
tOH
POWER SUPPLY
VDO (Supply Voltage)
100 (Supply Current)
NOTES
'Temperature RaIIges as follows:
1 See
+2.4
+2.4
+2.4
+0.8
+0.8
+0.8
1
1
1
8
8
8
12-Bit Unipolar Binary or 12-Bit Offset
Binaty (See Figures 4 and 5). Data is
Loaded into Data Registers in 4-Bit Bytes.
(See Figure
80
0
0
200
10
40
60
10
1)
120
10
10
200
20
40
100
10
160
10
10
250
20
40
100
10
+5
2.5
+5
2.5
+5
2.5
J.
K. GK venicms; 0 to +70°C
A, B. GB versions; _25°C to +85°C
S, T, GT versions; -5SoC to +125°C
defmitions OR next , ....
'Guaranteed but not tested.
LoPe inputs arc MOS ..teI. Typical input current (+25°C) is leu than lDA.
• Sample tested at +25° C to cnsurc complilDcc.
4
Specifications subject to cbaap widaout notice.
2-282 DIGITAL-TO-ANALOG CONVERTERS
V min
V max
/JAmax
pFmax
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
DAC register loaded to 0000 0000 0000
DAC registerloaded to 1111 1111 1111
DAC register loaded to 11111111 1111
DAC register loaded to 0000 0000 0000
VIN
=OV or Voo
twR' WRITE pulse width
tAWH' Address-to-WRITE hold time
tcwH' Chip select-to-WRITE hold time
tcLR' Minimum CLEAR pulse width
tcws' Chip select-to-WRITE setup time
tAWS' Addre.. valid-to-WRITE setup time
nsmin
nsmin
tDS: Data setup time
V
mAmax
tS% for specified performance
Digital Inputs =VINH or VINL
toH' Data hold time
AD7542
Power Dissipation (Package)
Plastic
To +70°C . . . . . .
Derates above + 70°C by
Ceramic
To +75°C . . . . . . .
Derates above + 7SoC by
Operating Temperature Range
Commercial (1, K, GK Versions)
Industrial (A, B, GB Versions)
Extended (S, T, GT Versions) .
Storage Temperature . . . . . . .
Lead Temperature (Soldering, IOsecs)
ABSOLUTE MAXIMUM RATINGS·
(TA = + 25"C unless otherwise noted)
VootoAGND .
. OV, +7V
Vooto DGND .
. OV, +7V
AGNDtoDGND
Voo +O.3V
DGNDtoAGND ,
Voo +O.3V
Digital Input Voltage to GND
-O.3V, Voo +O.3V
Voun , VOUT2 to AGND
. . . . . . . -O.3V, Voo +O.3V
VREF to AGND
±2SV
VRFB to AGND . . . .. . . . . . . . . . . . . . .. ±2SV
. 670mW
8.3mWrC
450mW
6mW/oC
o to +70°C
- 2SoC to + 8SoC
- SsoC to + 12SoC
-6SoC to + ISO°C
. . . . . +300°C
'COMMENTS: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
D3-DD
NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS VIM; V,L
Figure 1. AD7542 Timing Diagram
PIN CONFIGURATIONS
DIP
LCCC
I!o"
1=0"
!!
PLCC
..
I!
1=
3
2
"0 "0
3
2
1
2.
19
"
LJ
OS" (MSB) 4
DB10 5
18 Voo
DB11IMSB)
4
17 Wii
AD7545
TOP VIEW
DB9 •
16
INot to Scale)
DlI8 7
CS
DB7.
14 DB1
V..
CS
TOP VIEW
(Nat to Scale)
D87
,.
iiiiii
AD7545
15 DBa ILSB)
DB2
CO
0
V..
iiiiii
g
CO
D80 (LSBI
•
DB'
D83
9
10 "
12 13
! R ! il
~
910111213
! ! !
!!I
~
DIGITAL-TO-ANALOG CONVERTERS 2-293
SPECIFICATIONS
(VRff
= +lOV, Voun =OV,AGND =DGND unless otherwise specified)
\Too -.'v
..........
Venion
STATIC PERFORMANCE
Resolution
Relative Accuracy
All
l,A,S
Gain Error (Using Internal RFB)2
Uni...
12
±2
±1
±1I2
±1I2
Bits
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
L,C, U
GL,GC,GU
±1/2
±1I2
±112
l,A,S
K,B,T
L,C,U
GL,GC,GU
±4
±I
±1
±1
±4
±I
±1
±I
±4
±I
±I
±1
±4
±1
±I
±1
l,A,S
K,B,T
L,C,U
GL,GC,GU
±20
±10
±5
±1
±20
±IO
±6
±2
±25
±IS
±IO
±6
4.ll
±S
±S
om5
10
10
10
2
12
±2
±1
±1I2
12
±2
±1
\'nD =.uv
Limits
TA,,"+2'''c Tmla,T_ 1
12
±2
±1
±1/2
±112
K,B,T
Differential Nonlinearity
LImi..
1
TA • +25°C Tadn. Tma
Test CoDditlontlCommcntl
±25
±i5
±IO
±7
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
lO-Die Monotonic Tmin to Tmax
a·Bit Monotonic Tmin to TmlX
U ..Sit Monotonic Tmia to TmlX
lz"Sit Monotonic Tmln to TOlIX
DAC Register Loaded with
111111111111
Gain Error is Adjustable Using
the Circuiu of Figures 4, 5 and 6
tlO
±1O
ppm/Ie max
Typical Value is 2ppmfc for VDD
0,03
50
50
200
0.01
10
10
10
0.02
SO
SO
200
%per%max
nAmax
nAmu
nAmax
l:J.VDD=±S%
DBo-DB11 = OV; Wii.;cs = OV
2
2
2
".max
Gain Temperature Coefficienr
OOain/.6.Temperarure
a:
+SV
DC Supply Rejection'
l!I:i.w/{!,voo
Output Leak. Current at OUTl
DVNAMIC PERFORMANCE
CUrrent Settling Time3
All
l,K,L,GL
A,B,C,GC
S,T,U,GU
All
To 1/2LSB. OUT 1 load
~tp~measured
z 100'1. DAC
from falling edge of
.WR.CS=OV.
Propagation DelayS (from Digital
Inl;)ut Change to 90%
of f'mal Analog Output)
Digital to Analog Glitch Impulse
AC Feedthrousbs
AtlOUTl
REFERENCE INPUT
Input Resistance
(Pin 19 to GND)
ANALOG OUTPUTS
Output Capacitance'
COUTl
CoIlTI
DIGITAL INPUTS
Input High Voltage
V,H
Inp-At Low Voltage
VIL
Input CUrrent'
lIN
Input CapacitanceS
DBo-DBll
WR,CS.
SWITCHING CHARACTERISTICS'
Chip Select to Write Setup Time
-
-
nsmax
nV sec typ
OUTI LOAD =
VRBF =AGND
5
5
mVp-p typ
VREF .. tI0V, 10kHz Sinewave
7
2S
kSlmin
kOmax
Input ResistanceTC .. -300ppmlC typ
Typical Input Resistance .. llkSl
70
200
70
200
pFmax
pFmax
DBo-DBll = OV, WR,cs= OV
DBo-DBll ... VOD. Wi. CS .. OV
loo
400
All
5
All
7
2S
7
2S
7
2S
All
All
70
200
70
200
5
loon CI!XT •
250
2S0
All
All
All
2.4
2.4
13.5
13.5
V min
All
0.8
0.8
1.5
1.S
V max
All
±I
±IO
±1
±10
p.Amax
VlN .. Oor Voo
All
All
S
20
5
20
5
20
S
20
pFmax
pFmax
VIN"'O
VlN=O
All
280
200
l80
270
180
120
200
ISO
nsmin
nstyp
See Timing Diagram on next page
All
0
0
0
0
nsmin
All
250
175
400
160
280
100
240
170
nsmin
nstyp
All
140
100
210
150
90
60
120
80
nsmin
nstyp
All
10
10
10
10
nsmin
All
2
100
10
2
SOO
10
2
100
10
2
500
10
mAmax
p.A max
p.Atyp
tcs
Chip Select to Write Hold Time
tcH
Write Pu!seWidth
twR
bata Setup Time
to.
Data Hold Time
toH
POWER SUPPLY
IoD
llpF'
NOTES
ITemperatUre Ranges as follows, JI K, L, GL versions; 0
to +70°C
A, B, C, GC vemODl; _25°C to +85°C
S, T, UI GU versions, -55°C to +125°C
• This includes the effect of Sppm max pin TC.
I Guaranteed but Dot tested.
4DBO-DBll ::II OV to VDD or VDD to OV.
oFeedthroush can be further reduced by c:onnectins the metal
lid OD the ceramie paekqe to DGND,
• Logie inputs are MOS liteS. Typical input current ("'2~C) is less than lnA.
"Sample tested at +25°C to ensure c:ompliance.
SpedfieatioDl subject to chqe without notice.
2-294 DIGITAL-TO-ANALOG CONVERTERS
tcS;;'twR, tcH;;.o
All Digital Inputs VIL or VlH
All Digital Inputs OV or VOD.
All Digital Inputs OV or VOD
AD7545
WRITE CYCLE TIMING DIAGRAM
-_-_-_-_"--.;41:"tcH=:~~
smcT~_:.~~===_tcs_
,_
./
CHIP
{-~R~lt:
I-tDS
,______ 1==
(D.Po~J:111~
XV:~
DATA VALID
MODE SELECTION
VODD
WRITE MODE:
HOLD MODE:
CI and WR low. DAC respondl
Either CI or WR high. data bul
todatabus (080-0811) inputs. (DBO-D811) illoekadout; DAC
hll!.dlllA1.data p _ t when
WR or CS .umad high _ .
o
NOTES:
VDD
Yoo' +15V;",,,· 400.
VOO • +5V;,,·,,· 20m
X,,___
All Input sign" ri.. .,d fall tim.. ""alNd from 10% to
0
ABSOLUTE MAXIMUM RATINGS·
= + 25"C unless otherwise noted)
(TA
VDD to DGND . . . . . . . . . . . . . . . . . -0.3V, + 17V
Digital Input Voltage to DGND . . . . -0.3V, VDD +0.3V
VRFB , VREF to DGND . . . . . . . . . . . . . . . . . ±25V
VPlN1 to DGND. . .
-O.3V, VDD +O.3V
AGND to DGND . . . . . . . . . . .. -O.3V, VDD +O.3V
_oIVoo·
Timing me.u,.me"t ............1 is YIH + V.L/2.
Power Dissipation (Any Package) to + 75°C
Derates above 75°C by . . . . . .
Operating Temperature
Commercial (J, K, L, GL) Grades
Industrial (A, B, C, GC) Grades
Extended (S, T, U, GU) Grades .
Storage Temperature .. . . . . . .
Lead Temperature (Soldering, 10secs)
450mW
6mWrC
o to +700C
- 25°C to + 85°C
- 55°C to + 125°C
- 65°C to + 1500C
. . . • • +300OC
NOTES
·Stres8e8 above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation at or above this specification is not implied. Exposure to above maximum rating conditions for extended periods
may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before,devices are removed.
APPLICATION HINTS
Output Offset: CMOS DIA converters exhibit a code dependent output resistance which in tum causes a code dependent
amplifier noise gain. The effect is a code dependent differential nonlinearity term at the amplifier output which
depends on VOS where VOS is the amplifier input offset
voltage. To maintain monotonic operation it is recommended that VOS be no greater than (25 X 10-6 ) (VREP) over
the temperature range of operation. Suitable op amps are
ADS 17L and ADS44L. The ADS17L is best suited for fixed
reference applications with low bandwidth requirements: it
has extremely low offset (SOIlV) and in most applications
will not require an offset trim. The ADS44L has a much wider
bandwidth and higher slew rate and is recommended for multiplying and other applications requiring fast settling. An offset
trin1 on the AD544L may be necessaty in some circuits.
General Ground Management. AC or transient voltages between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages
at AGND and DGND are equal is to tie AGND and DGND
together at the AD7S4S. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel
between the AD754S AGND and DGND pins (lN914 or
equivalent).
Digital Glitches: When WR and CS are both low the latches
are transparent and the D/A converter inputs follow the data
inpu ts. In some bus systems, data on the data bus is not always
valid for the whole period during which WR is low and as a
WARNING!
.----r1
~~=:
result invalid data can briefly occur at the D/A converter
inputs during a write cycle. Such invalid data can cause unwanted glitches at the output of the D/A converter. The
solu tion to this problem, if it occurs, is to rerlme the write
pulse WR so that it only occurs when data is valid.
Another cause of digital glitches is capacitive coupling from
the digital lines to the OUTl and AGND terminals. This should
be minimized by screening the analog pins of the AD7S4S
(Pins 1, 2, 19,20) from the digital pins by a ground track
run between pins 2 and 3 and between pins 18 and 19 of
the AD7S4S. Note how the analog pins are at one end of the
package and separated from the digital pins by VDD and DGND
to aid screening at the board level. On-chip capacitive coupling
can also give rise to crosstalk from the digital to analog sections of the AD7S4S, particularly in circuits with high currents and fast rise and fall times. This type of crosstalk is
minimized by using VDD = +5 volts. However, great care
should be taken to ensure that the +SV used to power the
AD7S4S is free from digitally induced noise.
Temperature Coefficients: The gain temperature coefficient
of the AD7S4S has a maximum value of Sppm/ C and a
typical value of 2ppm/oC. This corresponds to worst case
gain shifts of 2LSBs and O.8LSBs respectively over a 100°C
temperature range. When trim resistors Rl and R2 are used
to adjust full scale range, the temperature coefficient of Rl
and R2 should also be taken into account. The reader is
referred to Analog Devices Application Note "Gain Error
and Gain Temperature Coefficient of CMOS Multiplying
DACs", Publication Number E630-10-6/81.
DIGITAL-TO-ANALOG CONVERTERS 2-295
BASIC APPLICATIONS
Figures 1 and 2 show simple unipolar and bipolar circuits using
the AD7545. Resistor Rl is used to trim for full scale. The "G"
versions (AD7S4SGLN, AD7S4SGCQ, AD7S4SGUD) have
a guaranteed maximum gain error of ±lLSB at+2SoC (VDD =
+SV) and in many applications it should be possible to dispense with gain trim resistors altogether. Capacitor C1 provides phase compensation and helps prevent overshoot and
ringing when using high speed op amps. Note that all the
circuits of Figures i and 2 have constant input impedance
at the VREF terminal.
The circuit of Figure 1 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in
the range 0 to -VIN (note the inversion introduced by the op
amp) or VIN can be an ac signal in which case the circuit behaves as an attenuator (2-Q.uadrant Multiplier). VIN can be
any voltage in the range -20<:VIN <:+20 volts (provided the
op amp can handle such voltages) since VREF is permi~d to
exceed VDD' Table II shows the code relationship for the
circuit of Figure 1.
Figure 2 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself uses offset binary code and inverter UI on the MSB line
converts 2's complement input code to offset binary code.
If appropriate. inversion of the MSB may be done in software
using an exclusive -OR instruction and the inverter omitted.
R3, R4 and RS must be selected to match within 0.01% and
they should be the same type of resistor (preferably wirewound or metal foil), so that their temperature coefficients
match. Mismatch of R3 value to R4 causes both offset and
full scale error. Mismatch of RS to R4 and R3 causes full
scale error.
·FOR VALUES OF R1 AND At
HE TABLE 1.
DATA INPUT
V,N
Figure 2. Bipolar Operation (2's Complement Code)
Data Input
-REFER TO TABLE 1.
0811-080
Figure 1. Unipolar Binary Operation
TRIM
RESISTOR
J/AIS
KlB/T
Rl
R2
soon
lS0n
200n
68n
UC/U
loon
3m
GUGC/GU
20n
6.8n
Table 1. Recommended Trim Resirtor Values VB. Grades
for Voo = +5V
Binary Number in
DAC Register
Analog Output
1111
1111
1111
-VIN {4095 }
4096
1000
0000
0000
-VIN {2048 }
4096
0000
0000
0001
-VIN
0000
0000
0000
o Volts
=-112 VIN
{40~6 }
Table II. Unipolar Binary Code Table for Circuit of Figure 1
2-296 DIG/TAL-TO-ANALOG CONVERTERS
Analog Output
0111
1111
1111
+VIN • {2047 }
2048
0000
0000
0001
+VIN •
0000
0000
0000
1111
1111
1111
-VIN • {2oi8}
1000
0000
0000
-VIN • {2048}
2048
boi8}
o Volts
Table 1/1. 2's Complement Code Table for Circuit of
Figure 2
CMOS 12-Bit
Buffered Multiplying DAC
AD7545A I
r'IIIIANALOG
WDEVICES
AD7S45A FUNCTIONAL BLOCK DIAGRAM
FEATURES
Improved Version of AD7546
Fast Interface Timing
All Grades 1Z-Bit Accurate
Small ZD-Pin 0.3" DIP and
ZO-Terminal Surface Mount Package
Low Cost
AGND
GENERAL DESCRIPTION
The AD7545A, a 12-bit CMOS multiplying DAC with intema1
data latches, is an improved version of the industry standard
AD7545. This new design features a WR pulse width of lOOns
which allows interfacing to a much wider range of fast 8-bit and
16-bit microprocessors. It is loaded by a single 12-bit wide word
under the control of the CS and WR inputs; tying these control
inputs low makes the input latches transparent allowing unbuffered
operation of the DAC.
DGND
DBll-DBO
ORDERING INFORMATION1 ,2
Relative
Gain
Accuracy, Error,LSB
LSB
Temperature Range and Package Options3
Tmiu-Tmax Tmiu-Tmax Oto +70"c
±112
± 112
± 112
± 112
±4
±2
±4
±2
- 25°C to + 85°C
- 55°C to + 125°C
Plastic DIP (N-20)
Hermetic (Q-20)
Hermetic (Q-20)
AD7545AKN
AD7545ALN
AD7545ABQ
AD7545ACQ
AD7545ATQ
AD7545AUQ
PLCC4 (P-20A)
LCCC5 (E-20A)
AD7545AKP
AD7545ALP
AD7545ATE
AD7545AUE
NOTES
'To order MIL-STD-883C, Class B processed parts, add/883B to part number.
Contact your local sales offIce for military data sheet.
•Analog Devices reserves the right to ship ceramic packages (D-20) in lieu of cerdip
packages (Q-20).
'See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carier.
'LCCC: Leadless Ceramic Chip Csrrier.
PIN CONFIGURATIONS
PLCC
LCCC
DIP
!i!
0
" ."
Z
0
3
DB11(MSBI 4
0810
5
DB9
•
DaB
7
DB7
8
2
>=
:>
0
....
1
m
'" ::
20 ,.
AD7545A
TOPVJEW
INotTo$calel
18
VDD
17
WR
16
Ci
10 11 12 13
4
AD7545A
15 DBO (LSB)
14
9
DB"IMSB)
TOP VIEW
INotToScale,
DB1
910",213
!! ! ! !
DIGITAL-TO-ANALOG CONVERTERS 2-297
•
SPEC IFI CATIONS IV. = + lOY, Vaun =OY, ASNO = OSHa IllIess obIwisespacifiad)
Venion
VDD=+SV
Limits
T,,= +2S"C T ....T ...1
VDD =+lSV
Limits
T,,= +25"C T .....T ...1 Vnits
All
K,B,T
L,C,U
All
12
±1I2
± 112
±I
12
±1I2
±I
12
±1I2
±112
±I
12
±1I2
±112
±I
Bits
LSBmax
LSBmax
LSBmax
K,B,T
L,C,U
±3
±I
±4
±2
±3
±I
±4
±2
All
AU
±5
±2
±5
±2
±5
±2
±5
±2
LSBmax
LSBmax
ppm?Cmax
ppml"Ctyp
AU
K,L
B,C
T,U
0.002
10
10
10
0.004
50
50
200
0.002
10
10
10
0.004
50
50
200
% per % max
nAmax
nAmax
nAmax
IlVoo=±5%
DBO·DBll = OV;WR,CS = OV
All
I
I
I
I
fJ.Smax
To 1/2LSB. OUT I load = loon,
Cmcr = 13pF. DAC output measured
from falling edge ofWR. CS = OV.
Propagation Delay' (from Digital)
Input Change to 90%
of Final Analog Output)
Digital·to-Analog Glitch Inpulse'
All
All
200
5
-
150
5
-
nsmax
nVsectyp
OUTl LOAD = lOOn,CEXT =13pp3
VREF = AGND. OUT I Load = loon,
Cmcr = 13pF. DAC Register
Alternately Loaded with All Os and Allis.
AC Peedthrough '.'
AtOUTl
All
5
5
5
5
mVp-ptyp
VREF = ± IOV, 10kHz Sinewave
AU
10
20
10
20
10
20
10
20
knmin
kOmax
Input Resistance TC = - 300ppm?C typ
Typical Input Resistance = ISkO
All
AU
70
ISO
70
70
70
ISO
ISO
ISO
pFmax
pFmax
DBo.DBll =OV,WR,CS=OV
DBO-DBll =VOD, WR,CS=OV
All
2.4
2.4
13.5
13.5
V min
AU
0.8
0.8
1.5
1.5
V max
All
±I
±IO
±I
±IO
.,A max
All
8
8
8
8
pPmax
K,B,L,C
T,U
100
100
130
170
75
75
85
95
nsmin
nsmin
All
K,B,L,C
T,U
0
100
100
0
130
170
0
75
75
0
85
95
nsmin
AU
100
150
60
80
nsmin
All
5
5
5
5
nsmin
All
All
5
2
100
10
5
2
100
10
IS
2
100
10
15
2
100
10
V
mAmax
.,A max
.,Atyp
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Temperature Coefficient'
IlGainiIlTemperature
DC Supply Rejection'
IlGainiIlVoo
Output Leakage Currentat OUTI
DYNAMIC PERFORMANCE
Current Settling Time'
REFERENCE INPUT
InputResistance
(Pin 19toGND)
±1/2
Test ConditioDSICommOllls
Endpoint Measuremeot
All Grades Guaranteed 12·Bit
Monotonic Over Temperature
Measured Using Internal R FB •
DAC Register Loaded with AU Is.
ANALOG OUTPUTS
Output Capacitance'
GoUTl
GoUTl
DIGITALINPUTS
Input High Voltage
VIM
Input Low Voltage
VIL
Input Current'
lIN
Input Capacitance'
DBo.DB II , WR, CS
SWITCHING CHARACTERISTICS'
Chip Select to Write Setup Time
les
Chip Select to Write Hold Time
leM
Write Pulse Width
tWR
Data Setup Time
tos
Data Hold Time
tOM
POWER SUPPLY
Voo
100
NOTES'
ITempcrarure RaDaesas follows:
K,Lversioos;
Oto +7O"C
B,Cversions;
-25'"<: to +85OC
T. U..mons;
-SS'CIO + 12S'C
2Samp1e tested to ensure compliance.
lDBO-DBll =OV to VDD or Voo to OV.
'PeedthrouJb can be further reduced by 4~:~
~ _---VDD
X~
0
DATA VALID
___
MODE SELECTION
HOLD MODE:
WRITE MODE:
CS and WR low, OAC responds Either CS or WR high, data bus
to data bus (OBO-0811) inputs. (080-0811) is locked out; OAC
I!!!!.ds IlII1.data present when
WR or CS assumed high state.
NOTES:
Voo • +5V; ~ .... 200.
VOD .. +15V; t, .. tt .. 40ns
All input sign.! rise ..d fill times me.... red from 10% to
90% of VDD.
Vi +V
Timing mRlUrement reference 1..,.1 is ~.
ABSOLUTE MAXIMUM RATINGS·
(TA = + 25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . -O.3V, + 17V
Digital Input Voltage to DGND . . . . -0.3V, V DD +0.3V
VRFB , VREF to DGND . . . . . . . . . . . . . . . . . ±25V
VPlN1 to DGND . . . . . . . . . . . .. -0.3V, VOO +0.3V
AGND to DGND . . . . . . . . . . .. -0.3V, VDO +0.3V
Powet Dissipation (Any Package) to 75°C.
450mW
Derates above 75°C by . . . . . . . . . . . . . . . 6mWrC
Opetating Tempetature
COmmetcial (K, L) Grades
Industrial (B, C) Grades
Extended (T, U) Grades .
Storage Tempetature . . . .
Lead Tempetature (Soldering, 10sec)
. . . 0 to +70OC
- 250C to + 850C
- 550C to + 125°C
-65OC to + 150°C
. . . . . +3000C
NOTES
·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation at or above this specification is not implied. Exposure to above maximum rating conditions for extended periods
may affect device re1isbility.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as Figures
I and 2 exhibit a code dependent output resistance which in
turn can cause a code dependent etrOr voltage at the output of
the amplifiet. The maximum amplitude of this error, which
adds to the D/A converter nonlinearity, depends on V os , whete
Vos is the amplifier input offset voltage. To maintain specified
accuracy with VREF at 10V, it is recommended that Vos be no
greatet than 0.25mV, or (25 x I~) (VREF), over the tempetature
range of opetation. Suitable op amps are AD517 and AD711.
The AD517 is best suited for fixed refetence applications with
low bandwidth requirements: it has extremely low offset (l50IJ.V
max for lowest grade) and in most applications will not requite
an offset trim. The AD711 has a much widet bandwidth and
highet slew rate and is recommended for multiplying and othet
applications requiring fast settling. An offset trim on the AD711
may be necessary in some circuits.
General Ground Management: AC or transient voltages between
AGND and DGND can cause noise injection into the analog
output. The simplest method of ensuring that voltages at AGND
and DGND are equal is to tie AGND and DGND together at
the AD7545A. In more complex systems whete the AGND and
DGND intertie is on the backplane, it is recommended that two
diodes be connected in invetSe parallel between the AD7545A
AGND and DGND pins (lN914 or equivalent).
Invalid Data: When WR and CS are both low, the latches are
transparent and the D/A convertet inputs follow the data inputs.
In some bus systems, data on the data bus is not always valid
for the whole petiod during which WR is low, and as a result
invalid data can briefly occur at the DIA convertet inputs during
WARNING!
0
~~DEVICE
a write cycle. Such invalid data can cause unwanted signals or
glitches at the output of the DIA converter. The solution to this
problem, if it occurs, is to retime the write pulse WR so that it
only occurs when data is valid.
Digital Glitches: Digital glitches result due to capacitive coupling
from the digital lines to the OUTl and AGND terminals. This
should be minimized by screening the analog pins of the AD7545A
(Pins I, 2, 19,20) from the digital pins by a ground track run
between Pins 2 and 3 and between Pins 18 and 19 of the AD7545A.
Note how the analog pins are at one end (DIP) or side (LCC
and PLCC) of the package and separated from the digital pins
by Voo and DGND to aid screening at the board level. On-chip
capacitive coupling can also give rise to crosstalk from the ditigalto-analog sections of the AD7545A, particularly in circuits with
high currents and fast rise and fall times. This type of crosstalk
is minimized by using VDO = +5 volts. However, great care
should be taken to ensure that the + 5V used to power the
AD7545A is free from digitally induced noise.
Temperature Coefficients: The gain temperature coefficient of
the AD7545A has a maximum value of 5ppmfOC and a typical
value of 2ppmfOC. This corresponds to worst case gain shifts of
2LSBs and 0.8LSBs respectively over a 1000C tempetature
range. When trim resistors RI and R2 (such as in Figure 4) are
used to adjust full-scale range, the tempetature coefficient of RI
and R2 should also be taken into account. The reader is refetred
to Analog Devices Application Note "Gain Error and Gain
Tempetature Coefficient to CMOS Multiplying DACs", Publication Numbet E63Oc-5-3/86.
DIGITAL-TO-ANALOG CONVERTERS 2-299
•
BASIC APPLICATIONS
Figures 1 and 2 show simple unipolar and bipolar circuits using
the AD754SA. Resistor Rl is used to trim for full scale. The L,
C, U grades have a guaranteed maximum gain error of ± lLSB
at + 25°C, and in many applications it should be possible to
dispense With gain trim resistors altogether. Capacitor Cl provides
phase compensation and helps prevent overshoot and ringing
when using high-speed op amps. Note that all the circuits of
Figures 1 and 2 have constant input impedance at the V REF
terminal.
The circuit of Figure 1 can either be used as a fixed reference
DfA converter so that it provides an analog output voltage in
the range 0 to - VIN (note the inversion introduced by the op
amp) or V IN can be an ac signa1 in which case the circuit behaves
as an attenuator (2-Quadrant Multiplier). VIN can be any voltage
in the range -20",VIN",+20 volts (provided the op amp can
handle such voltages) since VREF is permitted to exceed Voo.
Table II shows the code relationship for the circuit of Figure 1.
Figure 2 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The DfA function itself
uses offset binary code, and inverter U 1 on the MSB line converts
2's complement input code to offset binary code. If appropriate,
inversion of the MSB may be done in software using an exclusive
- OR instruction and the inverter omitted. R3, R4 and R5
must be selected to match Within 0.01%, and they should be the
same type of resistor (preferably Wire-wound or metal foil), so
that their temperature coefficients match. Mismatch of R3 value
to R4 causes both offset and full-scale error. Mismatch of R5 to
R4 and R3 causes full-scale error.
-REFER TO TABLE 1.
VDD
-FOR VALUES OF Rl AND R2
SEE TABLE 1.
DATA INPUT
Figure 2. Bipolar Operation (2's Complement Code)
DBll-DBO
Data Input
Figure 1. Unipolar Binary Operation
Analog Output
1111
1111
+VIN
0000
0000
0001
+VIN
0000
0000
0000
o Volts
1111
1111
1111
-VIN
{2~8}
1000
0000
0000
-VIN
{2048}
2048
TRIM
RESISTOR
K,B,T
RI
R2
500
270
L,C,U
200
6.80
Table I. Recommended Trim Resistor Values VB. Grades
{20i8 }
Table III. 2'5 Complement Code Table for Circuit ofFigure 2.
Binary Number in
DAC Register
{ 2047 }
2048
0111
Analog Output
1111
1111
1111
-VIN ~409S }
4096
1000
0000
0000
-VIN {2048 } =-l/2VIN
4096
0000
0000
0001
-VIN
0000
0000
0000
o Volts
{4~6 }
Table II. Unipolar Binary Code Table for Circuit ofFigure 1.
2-300 DIGITAL-TO-ANALOG CONVERTERS
LC2MOS
Parallel Loading Dual 12-Bit DAC
AD7547 I
11IIIIIIII ANALOG
WDEVICES
AD7547 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface
Mount Packages
4-Quadrant Multiplication
Low Gain Error (1LSB max Over Temperature)
Fast Interface Timing
v••
21~----~::::::::~-------,
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTION
The AD7547 contains two 12-bit current output DACs on one
monolithic chip. Also on-chip are the level shifters, data registers
and control logic for easy microprocessor interfacing. There are
12 data inputs. CSA, CSB, WR control DAC selection and
loading. Data is latched into the DAC registers on the rising
edge of WR. The device is speed compatible with most microprocessors and accepts TIL, 74HC and 5V CMOS logic level
inputs.
The DIA converters provide 4-quadrant multiplication capabilities
with separate reference inputs and feedback resistors. Monolithic
construction ensures that thermal and gain error tracking is
excellent. 12-bit monotonicity is guaranteed for both DACs over
the full temperature range.
The AD7547 is mailufactured using the Linear Compatible
CMOS (LC2MOS) process. This allows fast digital logic and
precision linear circuitry to be fabricated on the same die.
DGND
DB11 - OBO
PRODUCT HIGHLIGHTS
1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size:
The AD7547 is available in both 0.3" wide, 24-pin DIPs and
in 28-terminal surface mount packages.
3. Wide Power Supply Tolerance:
The device operates on a + l2V to + 15V VDD, with ± 10%
tolerance on this nominal fIgure. All specifIcations are guaranteed over this range.
~
em
WIt
FUNCTION
X
X
I
I
X
0
No Data Transfer
No Data Transfer
A Rising Edge on CSA or CSB Loads
Data to the Respective DAC from the Data Bus
DAC A Register Loaded from Data Bus
DAC B Register Loaded from Data Bus
DAC A and DAC B Registers Loaded
from Data Bus
S
S
0
I
0
0
0
S
J
S
NOTES
1. X = Don'tcare
2.
means rising edge triggered
S
Table I. AD7547 Truth Table
DIGITAL-TO-ANALOG CONVERTERS 2-301
•
I.A
PanmeIer
Venioao
K.B
Venioao
L.C
Venioao
SVenioa
TVenioa
UVenioa
U.
ACCURACY
Resolution
Relative Accuracy
DifferontialNODIiDearity
12
±I
±I
12
±112
±I
12
±112
±I
12
±I
±I
12
±1/2
±I
12
±1/2
±I
Bib
LSBmax
LSBmax
±6
±3
±I
±6
±3
±Z
LSBmax
All grades JlU8rllttoed
monolOllicovertemperature.
Measurcdusing R..... RPBB.
Both DAC.ten loaded
with all I'••
±5
±5
±5
±S
±S
ppml"Cmax
Typiad value is IppmI"C
10
ISO
10
ISO
10
250
10
250
10
250
nAmax
nAJIW[
DAC A RegiIter loadecI
withallO·•.
10
ISO
10
ISO
10
250
10
250
10
250
nAmax
nAJIW[
DACB RegiIter loadecI
with all 0'••
9
20
9
20
9
20
9
20
9
20
knmin
knmax
Typiad InputResistanc:e = 14kn
±3
±3
±I
±3
±3
±I
% max
Typic:alIy±0.5%
2.4
0.8
2.4
6.8
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
Vmin
V max
±I
±IO
10
±I
±IO
10
±I
±IO
10
±I
±IO
10
±I
±IO
10
±I
±IO
10
""'max
pFmax
10.8/16.5
2
10.8/16.5
2
10.8/16.5
2
10.8/16.5
2
10.8/16.5
2
10.8/16.5
2
mAmax
Gain Error
Gain Temperature Coefficient';
ded specifICation••
4pp,12(DGND) .. cenmicDIP .......... is_tolid.
Spccificatioas subject to duoapwilhout notice.
2-302 DIGITAL-TO-ANALOG CONVERTERS
dBtyp
DACA. DACB loadecIwithalll's.
Measured between RPBA and loUT... or RP8B and lours.
Frequency ofmeasurement is 10H...l00kHz.
V'N- 6V rms. 1kHz. Both DACs losded with aliI's.
AD7547
TIMING CHARACTERISTICS (voo = lO.8Vto l6.5V, VREFA = VREFB = + lOY, lourA = IoUlB =AGNO =00.
Parameter
II
12
13
14
15
Limit at
T A =+2S·C
Limit at
T A = -4O"Cto +8S·C
Limit at
T A = -SS·C
to +12S"C
Units
Test Conditions/Comments
60
2S
80
0
80
80
2S
80
0
80
80
2S
100
0
100
nsmin
nsmin
nsmin
nsmin
nsmin
Data Setup Time
Data Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
•
NOTE
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS·
(TA = 2SoC unless otherwise stated)
5V
\~-yr---- 5V
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10%
TO 90% OF +5V. t, = t, = 20ns.
V +V
2. TIMING MEASUREMENT REFERENCE LEVEL IS ~
Figure 1. Timing Diagram for AD7547
VnnloDGND . . . . . .
VREFA> VREFB to AGND, . . . .
VRFBA , VRFBB to AGND, . . . .
Digital Input Voltage to DGND
IOUTA' IOUTB to DGND . . . .
AGND to DGND . . . . . . . .
Power Dissipation (Any Package)
To +75°C . . . . . . . . .
Derates above + 75°C . . . . .
Operating Temperature Range
Commercial (J, K, L Versions)
Industrial (A, B, eVersions)
Extended (S, T, U Versions) .
Storage Temperature . . . . .
Lead Temperature (Soldering, 10secs)
-0.3V, + 17V
. . . . ±25V
. . . . ±25V
-O.3V, Vnn +0.3V
-O.3V, Von +O.3V
-0.3V, Von +0.3V
450mW
6mWf'C
-40°C to +85°C'
- 40°C to .;. 85°C
- 55°C to + 125°C
-65"C to + 150°C
. . . . . +300"C
*Stresses above those listed under "Absolute Maximum Ratings" may'
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ORDERING INFORMATION1,l
Relative
Accuracy
T ..... toTIDU
Gain
Error
±ILSB
±1I2LSB
±1I2LSB
±lI2LSB
±6LSB
±3LSB
±lLSB
±2LSB
±lLSB
±lI2LSB
±1/2LSB
±1I2LSB
TmlntoT_
±6LSB
±3LSB
±lLSB
±2LSB
Temperature Range and Package Options'
- 4O"C to + 85"<:
Plutic DIP (N.24)
- 40"<: to + 85"<:
Hermetic (Q-24)
- 55"<: to + 125"<:
Hermetic (Q-24)
AD7547JN
AD7547KN
AD7S47LN
AD7S47AQ
AD7S47BQ
AD7547CQ
AD7S47SQ
AD7547TQ
AD7547UQ
PLCC4 (P.28A)
LCCC5 (E-28A)
AD7S47JP
AD7547KP
AD7547LP
AD7547SE
AD7547TE
AD7547UQ
NOTES
ITo order MIJ...STI)..883, Class B processed partS, add 18838 to part number.
Contact your 1oca1 sales offICe for military data sheets.
'Analog Devices ......... Ihe right to ship cerami<: packages (D-24A)jn lieu of
cerdip packages (Q-24).
3Sec Section 14 for package outline information.
'PLCc: Plastic Leaded Chip Carrier.
sLCCC: Lead1css Ceramic Chip Carrier.
CAUTION
ESD (electrosratic discharge) sensltlve device. The digital control inputs are diode protect·
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be dischllrged to the destination socket before devices are removed.
WARNING! ~
~~=:
DIGITAL·TO·ANALOG CONVERTERS 2-303
PIN CONFIGURATIONS
DIP
PLCC
LCC
i
Ie
•
VREFA
j "z~ "
1
3 2
•
DBO
7
NC
8
OB1
•
j
~
Ii!
J j
. >i
J
~
!!
j J
J
28 27 28
LJ
5
CSA
Z
V..
2S VDD
24CSa
AD7547
TOP VIEW
(Not to Sc.lel
CSB
23iiiiR
AD7547
iiiii
22 NC
TOP VIEW
(Not to Scalel
NC
21 DBn
DB2 10
20 OS10
DBa 11
19 DB9
D810
0B9
12 13 14 15 16 17 18
z "
z
~ 13 g
" "
NC == NO CONNECT
! Iii" II"
:;
=NO CONNECT
Q
Ne
i! "z
""
!! II Iii II
" " "
PIN FUNCTION DESCRIPTION
PIN
MNEMONIC
DESCRIPTION
1
2
3
4
S
6-18
12
19
20
21
AGND
Analog Ground.
Current OUtput terminal ofDACA.
Feedback resistor for DACA.
Reference input to DACA.
Chip Select Input for DAC A. Active low.
12 data inputs, DBO(LSB)-DBll (MSB).
Digital Ground.
Write Input. Data transferoccurs on rising edge ofWR. See Table I.
Chip Select Input for DACB. Active low.
Power supply input. Nominally + 12Vto + ISVwith::!: 10% tolerance.
Reference input to DACB.
FeedbackresistorofDACB.
Current output terminal ofDACB.
lolITA
RFBA
VREFA
CSA
DBO-DBll
DGND
WR
CSB
VDD
VlU!FB
RFBB
22
23
24
IotrrB
CIRCUIT INFORMATION
D/ASECTION
The AD7547 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between lOlITA and AGND. The
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor RF8A is used with an op-amp
to convert the current flowing in lOlITA to a voltage output.
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the DIA converters
(DAC A) in the AD7547. A similar equivalent circuit can be
drawn for DACB. Note that AGND is common to both DAC A
andDACB.
....-----_ _- -....--_I""-OIOUTA
R
t
1,1«1
D.~REF
Ro
+
CoUT
o-~--~------~--~----~-oAGND
Figure 3. Equivalent Analog Circuit for DACA
2R
2R
2R
811
810
so
.2R
RFBA
R
L---~~~----~--~---oAGND
Figure 2. Simplified Circuit Diagram for DACA
2-304 DIGITAL-TO-ANALOG CONVERTERS
ColIT is the output capacitance due to the N-chanoel switches
and varies from about 50pF to 150pF with digital input code.
The current source I LKG is composed of surface and junction
leakages and approximately doubles every IO"C. Ro is the equivalent output resistance of the device which varies with input
code.
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TIL and 5V CMOS
compatible. All logic inputs are static-protected MOS gates with
typical input currents of less than InA.
NANALOG
WDEVICES
FEATURES
8-Bit Bus Compatible 12-Bit DAC
All Grades 12-Bit Monotonic Over Full
Temperature Ranges
Operation Specified at + 5V. + 12V
or + 15V Power Supply
Low Gain Drift of 5ppmfOC Maximum
Full 4 Quadrant Multiplication
Skinny DIP and Surface Mount Packages
LC2MOS
8-Bit p.P-Compatible 12-Bit DAC
AD7548 I
AD7548 FUNCTIONAL BLOCK DIAGRAM
Voo
APPLICATIONS
B-Bit Microprocessor Based Control Systems
Programmable Amplifiers
Function Generation
Servo Control
DB7-DBO
GENERAL DESCRIPTION
The AD7S48 is a 12-bit monolithic CMOS D/A converter for
use with 8-bit bus microprocessors. Data is loaded in two bytes
to input holding registers as shown in the block diagram opposite.
The AD7S48 can be configured to accept either left- or right-justified data, least significant byte or most significant byte first,
using standard TTL compatible control inputs.
A separate load DAC control input allows the user the choice of
updating the analog output coincident with loading new data to
the DAC input register or at any time after the data loading
event. This feature is especially important in multi-DAC systems
where simultaneous update of all DACs is required.
The new Linear Compatible CMOS (LC2MOS) process used in
the manufacture of the AD7S48 allows precision thin-fllm linear
circuitry and high-speed low-power CMOS logic to be integrated
on the same small chip. The high-speed logic allows direct
interfacing to most of the popular 8-bit microprocessors.
DGND
PRODUCT HIGHLIGHTS
1. Microprocessor Compatibility
High speed input control (TTLl5V CMOS compatible)
allow direct interfacing to most of the popular 8-bit
microprocessors.
2. Guaranteed Monotonicity
The AD7S48 is guaranteed monotonic to 12-bits over the full
temperature range for all grades and at all specified supply
voltages.
3. Selectable Data Input Format
Left- or right-justified data, least significant or most significant
byte first. This allows the AD7S48 to be interfaced with
microprocessors using either Motorola or Intel-type data
formatting.
4. Monolithic Construction
For increased reliability and reduced package size - 0.3"
20-pin DIP and 20-terminal surface mount packages.
S. Single Supply Operation - See Figure 8.
6. Low Gain Error and Gain Error T.C.
DIGITAL-TO-ANALOG CONVERTERS 2-305
SPEC IFICATIONS1
('1l1li
=+5V, Y.= + lOY; YPIIIl =YP1N2 =OY. All specifications T... to T... 1IIIess othlllWise spacifiad)
ParaiDeter
l,A
Veniou
K,B
Venl....
SVasioa
TVasioa
VDiIs
ACCURACY
Resolution
Rdarlve Accuracy
Differential Noalinearity
12
±I
±I
12
;t112
±112
12
±I
±I
12
±112
±112
Bits
LSBmax
LSBmax
TeotComlitioJuolCom..
All grades gwuantccdmonotonic to 12-bits
ovet temperature.
Full Scale Error
±6
±3
±6
±3
LSBmax
Measured usiagintemal RFB and includes
effects ofleskagc current and gain TC.
Full Scale Error can be trimmed to zero.
±S
±S
±S
±S
ppml"Cmax
Typic:al value is 2ppmI"C
±S
±2S
:!:S
±2S
±s
±ISO
±S
±150
nAmax
nAmax
All digital inputs = OV
7
20
7
20
7
20
7
20
kOmia
kOmax
Typical Input Resistance = IHd}
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
Vmia
V max
±I
±IO
7
±I
±IO
7
±I
±IO
7
±I
±IO
7
pAmax
pAmax
pFmax
VIN= OVor Vnn
4.75/5.25
2
300
4.75/5.25
2
300
4.75/5.2S
2
300
4.75/5.25
2
300
VminNmax
mAmax
pAmax
Speeific:ations gwuantccd over this range
All digital inputs VIL or Vm
All digita1 inpursOV or Vnn
Gain Temperature Coefficieat';
AGainlATemperature
OutpUt Leskage Current
lour (Pin I)
+2S"<:
TmintoTmu
REF'ERENCEINPUT
Input Resistance, Pin 19
DIGITAL INPUTS
Vm (InputHigh Voltase)
VIL(InpurLowVoltase)
lIN (Input Current)
+25"<:
T.... to T_
CIN (Input Capooitanc:e)'
POWBRSUPPLY
VnnRanae
Inn
SPEC IFICATIONS1
('1l1li = + l2Y to
+ l5V, Y. = + lOY; VI'IIII = VPIN2 = OY. All specifications T... to T.... unless othIIIWise specified)
Panmeter
l,A
Vasioas
K,B
Venloal
SVasioa
TVenioa
Vai..
ACCURACY
Resolution
Relative Acc:urocy
Differential Nonlinearity
12
±I
±I
12
±1/2
±112
12
±I
±I
12
±112
±1/2
Bits
LSBmax
LSBmax
±6
±3
±6
±3
LSBmax
Full Scale Error
Test CcmdlticmofCommeuto
All grades gwuantccd monotonic to 12-bits
over temperature.
M~usinsintemalRFBandincloo~
effects ofleakage current and gain TC.
Full Scale Error can be trimmed to zero.
Gain Temperature CoeftIc:ien";
AGainlATemperature
Output Leskage Current
louT (Pin I)
+25"<:
TmmtoTnw:
REFERENCE INPUT
Input Resistanc:e, Pin 19
DIGITAL INPUTS
VIH (Input High Voltase)
VIL (Input Low Voltase)
hN (Input Current)
+ 2S"<:
TlIlintoT...
CIN (Input Capacitance)'
POWER SUPPLY
VnnRanae
Inn
±5
±S
±5
±S
ppm/"Cmax
Typic:sl value is 2ppmI"C
±S
±2S
±5
:!:25
±5
±ISO
±5
±ISO
nAmax
nAmax
All digital inputs = OV
7
20
7
20
7
20
7
20
kOmin
kOmax
Typic:slInput Resistance = llkfi
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
V min
V max
±I
±IO
7
±I
±IO
7
±I
±IO
7
±I
±IO
7
pAmax
",A max
pFmax
VIN=OVOrVnD
11.4115.75
3
I
11.4115.75
3
I
11.4115.75
3
I
1I.4IIS.7S
3
I
V minN max
mAmax
mAmax
SpeciflCStions gwuantccd over this range
All digital inputs VIL or VIH
All digital inputsOV orVnn
NOTES
ITemperatureraaaeufollowl: J, K versions: Oto + 7O"C
A,Bvenionl: -WCIO +8SOC
S, Tvenicms: -SS'Cto + 12S'C
'Guarllllecd bydesip bulllOl prodUClion lCSlcd.
Speciru:alions subject tochaapwilboulllOlic:e.
2-306 DIGITAL-TO-ANALOG CONVERTERS
AD7548
TIMING CHARACTERISTlCS1 (Voo= +5V, VIIS'= +lOV, V
plIl1
Parameter
tos
tOH
tcws
tcwH
tLWS
tLWH
tWR
Limit at
T,,=2S"C
LimitZat
T,,=Oto +7O"C
- 4O"C to + 8S"C
LimitZat
T,,=-SS"C
to + 12SoC
Units
Test Conditions/CoJDJDents
240
50
30
15
30
15
250
240
50
40
20
40
20
280
290
70
50
25
50
25
320
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
Data Valid Setup Time
Data Valid Hold Time
CSMSB orCSLSB to WR Setup Time
CSMSBor CSLSB to WR Hold Time
LDAC to WR Setup Time
LDAC to WRHoid Time
Write Pulse Width
TIMING CHARACTERISTICS1 (Vuu= +l2Vto +l5V, V
REF =
Parameter
tos
tOH
tcws
tcwH
kws
tLWH
tWR
=VPIN2 =OVunlassothelwisestalBd)
+lOV, VPlN1 =V_=OV unless otherwise staIBd)
Limit at
T,,=2SoC
Limit 2 at
T,,=Oto +7O"C
- 4O"C to + 8SoC
Limit1at
T,,= -SsoC
to +12S"C
Units
Test Conditions/CoJDJDents
160
30
30
15
30
15
170
190
30
40
20
40
20
200
230
50
50
25
50
25
240
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
Data Valid Setup Time
Data Valid Hold Time
CSMSB or CSLSB to WR Setup Time
CSMSB orCSLSB to WR Hold Time
LDAC to WR Setup Time
LDACto WR Hold Time
Write Pulse Width
AC PERFORMANCE CHARACTERISTICS
Venioa
'-eter
Ou.pu. Curren. Se.ding Time
These characteristics are included for Design Guidance only and are not subject to test
(VREF + 1DV; VPlN1 = VPlNZ OV, Output Amplifier is AD544 except where stalBd)
VDD=+SV
T .. = +25OC TA,= TMIN. TMAX
1.5
-
=
=
VDD =+lZVto+15V
T .. =+2SOC TA=TMlN, TMAX VailS
I
-
.... 'YP
Teat CoDditioDslCommealS
ToO.Ol % offull scale range.
loUT load = loon,eEXT = 13pF.
DAC register alternalely
loaded with allis and all Os
Measured with VREF = OV,
IOUTload = lOOn, CEXT = 13pF.
DAC register allernately
loaded with allis and all Os
Digital to Analog Glitch
Impulse
400
-
330
-
nV-sectyp
Multiplying Feedthrough Error'
3
5
3
5
mVp-ptyp
VREF= ±5V, 10kHz sine wave
DAC register loaded with all Os.
Total Harmonic Distortion
-85
-
-85
-
dBtyp
VREP =6Vrms@lkHz.
DAC regisler loaded with allis.
±0.015
±0.03
±0.01
±0.02
% per % max
AVoo= ±5%
200
100
200
100
200
100
200
100
pFmax
pFmax
DACregisterioadedwithallls.
DAC register loaded with all Os.
15
-
15
-
nVf\lHztyp
Measured between RFB and lOUT
Power Supply Rejection
A GAIN/A Voo
Output Capacitance
Iour(PinI)
Output Noise Voltage Density
(lOH:o-IOOkHz)
NOTES
1Guaranteed by desip but not production tested.
2TemperaIUftranae.sfoUoars: J. K versions: 0 to + 7O"C
A.8versions: -WCto + 8SOC
S, Tversions: - SSOCIO + 12SOC
.4Fcedlhroupcan be (unherreduccd byc:onncctiDJ lhc melallid on the ceramic package (D~20) to DGND.
SpecifICations subjca IOchanaewithoul: notice.
DIGITAL-TO-ANALOG CONVERTERS 2-307
ABSOLUTE MAXIMUM RATINGS·
Operating Temperature Range
Commercial 0, K versions)
Industrial (A, B versions)
Extended (S, T versions) .
Storage Temperature . . . .
Lead Temperature (Soldering, 10secs)
(TA = +2S'Cunlessotherwisenoted)
Voo (pin 18) to DGND .
VREF (pin 19) to AGND
VRFB (pin 20) to AGND
Digital Input Voltage
(pins 4-17) to DGND
VPlN 1 to DGND . . . .
AGND to DGND . . . .
Power Dissipation (Any Package)
To +7S·C . . . . . .
Derates above + 75°C .
+17V
±25V
±25V
-O.3V, Voo+0.3V
-0.3V, Voo +O.3V
-0.3V, Voo+0.3V
. . . 0 to +70°C
~40·C to +8S·C
- 55·C to + 125°C
-65·C to + I50·C
. . . . . +300°C
*Stresses above those listed undet "Absolute Maximum Ratings" may cause
permaneot damage to the device. This is a stress rating only and functional
opetation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
450mW
6mWI"C
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~OEVICE
PIN CONFIGURATIONS
DIP
LCCC
...
Q
~
g~
v..,
PLCC
3212019
.,, ,,
".
CSMSB 4
AD7548
CTRL 6
TOP VIEW
(Not to Seale)
DB7(MSB) 7
Q
Q
~
3
2
DaOILSB'
j
,
f
II:
2.
,.}
0
v••
WR
AD7548
16 CSLSB
TOP VIEW
(Not to Scalel
15 lDAC
14 DBO(L8Bi
086 8
Z
18 Voo
17
DFfOOR 5
LDAC
Q
"
Z
j J }
DB6
8
DB2
9
10 11 12 13
!l
~ ~ ~ ~
j/; 1lI ill ;;
ill
Q
Q
Q
Q
Q
ORDERING INFORMATION1,l
Relative
Accuracy
Tmia-Tmax
Full-Scale
Error
T...u.-Tmax
±ILSB
±1I2LSB
±6LSB
±3LSB
±lLSB
±1/2LSB
±6LSB
±3LSB
Temperature Range and Package Options]
Olo +700c
Plastic DIP (N-20)
- 40°C to + 85°C
Hermetic (Q-20)
- 55°C to + 12S·C
Hermetic (Q-20)
AD7548JN
AD7548KN
AD7548AQ
AD7548BQ
PLCC4 (P-20A)
AD7548SQ
AD7548TQ
LCCCs (E-20A)
AD7548JP
AD7548KP
AD7548SE
AD7548TE
NOTES
ITo ordet MIL-STD-883, Class B processed parts, add/883B to part numhet.
Contact your local sales office for military data sheet.
ZAnalog Devices reserves the right to ship ceramic (package outline D-20) packages
in lieu of cerdip (package outline Q-20) packages.
'See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
2-308 DIGITAL-TO-ANALOG CONVERTERS
CSLSii
li5AC
DBO(LSB)
DB'
DB4
Wii
AD7548
PIN FUNCTION DESCRIPTION
PIN
MNEMONIC
DESCRIPTION
DAC current OUT bus. Normally terminated at virtual ground of output amplifier.
lOUT
AGND
DGND
CSMSB
Analog Ground.
Digital Ground.
Chip Select Most Significant eMS) Byte. Active Low Input. Used in combination with WR to load
external data into the input register or in combination with WR and LDAC to load external data into
both input and DAC registers.
Data Format/DataOvcrridc. When this input is LOW, data in the DAC register is forced toone: of
two override codes selected by CTRL. When the override signal is removed, the DAC output
returns to reflect the value in the DAC register. With DF/DOR HIGH, CTRL selcctscithcr a left
or right justified input data format For normal operation, DF/DOR is'held HIGH.
DF/DOR
DFIDml CTRL FUNCTION
DAC register contents oven idden by all O's
DAC register contents overriden by all 1'8
Left-justified input data selected
Right-justified input data selected
CTRL
Control Input. See pm S descnptlon.
~OSTSIGNIFICANTBYTE -+cr.EAST SIGNIFICANT BYTE .j
IMS~ ~~-JU~TI~lED:DA+A I I I .ILSBI xl X I X Ix I CTRL~"O"
I
I
I
I X
xl X I X 6s~. I
I RI9HT~JU~TIFiEDPAiA ~S~ CTRL~"I"
I
X=Don'tcarestates.
7
8
9
14
15
DB7
DB6
DBs
DB4
DBl
DB2
DB1
DBO
LDAC
16
CSLSB
17
WR
10
11
12
13
Data Bit 7. Most Significant Bit (MSB).
Data Bit6.
DataBitS.
Data Bit 4.
Data Bit3.
Data Bit2.
Data Bit I.
Data Bit 0, Least Significant Bit (LSD).
Load DAC Input, active LOW. This signal, in combination with others, is used to load the DAC
register from either the input register or the external data bus.
Chip Select Least Significant (LS) Byte. Active LOW input. Used in combination with WR to load
external data into the input register or in combination with WR and LDAC to load external data
into both input and DAC registers.
WRITE Input. This active low signal, in combination with mhers is used in loading external data
into the AD7548 input register and in transferring data from the input register {() the DAC register.
WIi:
~
mm
~
FUNCTION
1
1
0
0
1
X
0
0
1
1
1
X
1
0
0
X
Load LS Byte to Input Register.
Load LS Byte [0 Input Register and DAC Register.
Load MS Byte lo]nput Register.
Load MS Byte to Input Register and DAC Register.
Load Input Register to DAC Register.
No Data Transfer
+ SV to + lSV Supply Input.
Reference Voltage Input.
Feedback Resistor. Used for normal 01 A conversion.
18
19
20
CONTROL INPUT INFORMATION
Figure la shows the data load timing diagram for the AD7548.
Figure I b shows the simplified input control structure of the
AD7548.
5V
OV
5V
CSLSB
OV
OF/OOR o-------_+-+-q
5V
WR
OV
5V
DATA
OV
NOTES
1. All INPUT SIGNAL RISE AND FAll TIMES MEASURED FROM 10% TO 90% OF +SV.
t,.=t,:::2Ons.
2. TIMING MEASUREMENT REFERENCE LEVEL IS V pj
;
VI!,
3. CSMSB (PIN 4) AND CSLSB (PIN 16) MAY BE INTERCHANGED.
4. FOR LEFT· JUSTIFIED DATA CTRL::: +OV WITH DF/DOR= +5V.
FOR RIGHT· JUSTIFIED DATA CTRl::: +5V WITH DFioOii= +SV.
Figure la. AD7548 Timing Diagram
Figure lb. Simplified AD7548 Input Control Structure
DIGITAL-TO-ANALOG CONVERTERS 2-309
GENERAL CIRCUIT INFORMATION
The simplified D/A circuit is shown in Figure 2. An inverted
R-2R ladder structure is used, which steers binarily weighted
currents between lOUT and AGND, thus maintaining a constant
current in each ladder leg independent of the switch state.
Figure 4 shows the tiruing diagram for automatic transfer of 8
+ 4-bit data to the DAC register. The first write cycle loads the
first byte of data to the input register. The second write cycle
loads the second byte of data to the input register and automatically
transfers both bytes to the DAC register.
The irtput resistance at VREF is constant and equal to the value
"R" in Figure 2. Since the input resistance is constant, the
reference terruinal can be driven by a reference voltage or a
reference current, ac or dc, of positive or negative polarity. (If a
current source is used, a low temperature coefficient external
RFB is recommended to define scale factor).
Updating a single byte (High or Low) in the DAC register can
be achieved in one write cycle using the automatic transfer
mode.
DATA
LDAC
L--+~
__
~~j~
----------lr---------,
__~~~------oAGND
DATA LATCHES AND SWITCH DRIVERS
Figure 2. AD7548 Simplified Fl!nctional Diagram
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows an equivalent circuit for the analog section of
the AD7548 D/A converter. The current source ILEAKAGE is
composed of surface and junction leakages. The resistor Ro,
denotes the equivalent output resistance of the DAC which
varies with input code (excluding all O's code) from 0.8R to 2R,
where R is typically llkH. GoUT is the capacitance due to the
current steering switches and varies from about 50pF to 120pF
(typical values) depending upon the digital input. g(VREF, N) is
the Thevenin equivalent voltage generator due to the reference
input voltage, VRllF , and the transfer function of R-2R ladder,
N.
.
For further information on CMOS multiplying D/A converters
refer to "Application Guide to CMOS Multiplying D/A Converters" available from Analog Devices, Publication Number G47915-8178.
r---'\;..,....---G
R'B
r - - -....-~--....----oQ lOUT
LOAD BYTE 1 INTO
INPUT REGISTER
LOAD BYTE 2 INTO INPUT
AND DAC REGISTERS.
TRANSFER BYTE 1 TO DAC
REGISTER. ANALOG OUTPUT
UPDATED.
Figure 4. Automatic Transfer Mode
STROBED TRANSFER MODE
Figure 5 shows the tiruing diagmm for the strobed transfer of 8
+ 4-bit data to the DAC register. Three write cycles are required
for this transfer mode. The first two write cycles sequentially
load bytes 1 and 2 into the input register. The third write cycle
transfers data from the input register to the DAC register.
The strobed transfer mode allows the DAC registers of several
AD7548's to be updated simultaneously, as shown in Figure 13,
by means of a master strobe signal connected to the LDAC of
each device.
A single byte of data (High or Low) can be transferred to the
DAC register in two write cycles using the strobed transfer
mode.
DATA
BYTE.
COUT
L - - - - -....._____~----oQAGND
Figure 3. AD7548 Equivalent Analog Output Circuit
DATA LOADING
The AD7548 accepts incoming data in either left-justified format
or right-justified format depending on the control inputs DF/DOR
and CTRL.
(Sec pin description of DF/DOR and CTRL on preceding
page).
Two operating modes are possible for controlling the transfer of
data from the input register to the DAC register, the automatic
transfer mode and the strobed transfer mode.
AUTOMATIC TRANSFER MODE
This is the simplest and fastest method of transferring data to
the DAC register. It is facilitated by connecting LDAC to either
CSMSB, as shown in Figure 10, or CSLSB.
2-310 DIGITAL-TO-ANALOG CONVERTERS
uure------4r------------+------~
LOAD BYTE 1 INTO
INPUT REGISTER
LOAD BYTE 2 INTO
INPUT REGISTER
TRANSFER DATA
FROM INPUT REGISTER
TO DAC REGISTER.
ANALOG OUTPUT UPOATED.
Figure 5. Strobed Transfer Mode
DATA OVERRIDE
The contents of the DAC register can be overridden by pulling
DF/DOR (pin 5) LOW. The CTRL (pin 6) input then determines
whether the DAC register data is overidden by all Os (CTRL
LOW) or all Is (CTRL HIGH). This feature allows the user to
calibrate the AD7548 in circ\lits such as Figure 6 without calling
on the microprocessor to load calibration data.
Applying the AD7548
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 6 shows the analog circuit connections required for unipolar
binary operation. With a dc input voltage or current (positive or
negative polarity) applied at pin 19, the circuit is a unipolar
DIA converter. With an ac input voltage the circuit provides 2quadrant multipliclltion (digitally controlled attenuation).
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 7 and Table II illustrate the recommended circuit and
code relationship for bipolar operation. The circuit uses offset
binary input coding. However, 2's complement coding can be
accommodated if the MSB is inverted (done in software) before
data is loaded into the DAC.
Table I shows the code relationship for the circuit of Figure 6.
With the DAC register loaded to 100000000000, adjust Rl for
VOUT=OV (alternatively one can omit RI and R2 and adjust the
ratio of R3 and R4 for Vour=OV). Full scale trimming can be
accomplished by adjusting the amplitude of Y'N or by varying
the value of RS.
For full scale trimming the DAC register is loaded with llll
llll 1111. This is most easily accomplished by using the data
override function. Rl is then adjusted for VOUT = - VIN (40951
4096). Alternatively full scale can be adjusted by omitting RI
and R2 and trimming the reference voltage magnitude.
Capacitor CI provides phase compensation and helps prevent
overshoot and ringing when using high speed op amps.
VDD
H2'
R3, R4 and RS must be selected to match within 0.01% and
they should be the same type of resistor (preferably metal film)
so that their temperature coefficients match. Mismatch of R3 to
R4 causes both offset and full scale error. Mismatch of RS to
R4 and R3 causes full scale error.
VON
INPUT
DATA
NOTES
1. CONTROL INPUTS OMlrrEO FOR CLAfUTY.
2. R,=100n.
~=33ll
FOR ALL GRADES.
DIGITAL
GROUND
ANALOG
COMMON
NOTES
1. CONTROL INPUTS OMrTTED FOR CLARITY.
2. R, = 100U, R2 =33Jl FOR ALL GRADES.
3. SEE APPLICATION HINTS.
3. SEE APPUCAnON HINTS.
Figure 6. Unipolar Binary Operation
Figure 7. Bipolar Operation (Offset Binary Coding)
Binary Number in
DAC Register
MSB
LSB
Analog Output, VOUT
I I I I
(4095
-VIN 4096
Binary Number in
DAC Register
Analog Output, Your
MSB
LSB
2047
I I I I 1111 11I I
+VIN 2048
1000 0000 0000
- VIN e048)
4096 = - 1I2VIN
1000 0000 0001
+VIN(2~8)
0000 0000 0001
-VIN(40~6)
1000 0000 0000
OV
0000 0000 0000
OV
oI
1I I I
-VIN(2~8)
0000 0000 0000
(2048)
-VIN 2048
I I I I
I I 1I
Table I. Unipolar Binary Code Table for Circuit of Figure 6
I I
1I I I
Table II. Bipolar Code Table for Offset Binary Circuit of
Figure 7
DIGITAL-TO-ANALOG CONVERTERS 2-311
SINGLE SUPPLY OPERATION
Figure 8 shows the AD7548 connected in a voltage switching
mode. The input voltage is connected to lour. The D/A convener
output voltage is taken from the VREF pin and has a constant
impedance equal to R. RFB is not used in this circuit ..The input
voltage VIN must always be positive with respect to AGND in
order to prevent an internal diode from turning on. To maintain
linearity the input voltage should remain within 2.5V of AGND
with VDD from + 12V to + 15V.
The output voltage Your of Figure 8 is expressed as
VOUT=(VIN) (D)( R1:1Rz )
Where D is a fractional representation of the digital input word
(OsDs4095/4096).
the AD7548. In more complex systems where the AGND and
DGND intenie is on the backplane, it is recommended that two
diodes be connected in inverse parallel between the AD7548
AGND and DGND pins (lN914 or equivalent).
Temperature Coefficients: The gain temperature coefficient of
the AD7548 has a maximum value of 5ppm/"C and typical value
of 2ppm/"C. This corresponds to worst case gain shifts of 2LSBs .
and O.8LSBs respectively over a 100°C temperature range. When
trim resistors Rl and R2 are used to adjust full scale range, the
temperature coefficient of Rl and R2 should also be taken into
account. The reader is referred to Analog Devices Application
Note "Gain Error and Gain Temperature Coefficient of CMOS
Multiplying DACs", Publication Number E63~1~/81.
High Frequency Considerations: AD7548 output capacitance
works in conjunction with the amplifier feedback resistance to
add a pole to the open loop response. This can cause ringing or
oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor.
Feedthrough: The dynamic performance of the AD7548 will
depend upon the gain and phase stability of the output amplifier,
together with the optimum choice of PC board layout and decoupling components. A suggested printed circuit layout for
Figure 6 is shown in Figure 9 which minimizes feedthrough
from V REF to the output in multiplying applications.
VON
ov
INPUT
DATA
Figure 8. Single Supply Operation Using Voltage Switching
Mode
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as
Figures 6 and 7 exhibit a code dependent output resistance
which in turn cause a code dependent amplifier noise gain. The
effect is a code dependent differential nonlinearity term at the
amplifier output which, depends on Vos where Vos is the amplifier
input offset voltage. To maintain monotonic operation it is
recommended that Vos be no greater than (25 x lO-6XVREF) over
the temperature range of operation. Suitable op amps are ADS 17L
and AD544L. The AD517L is best suited for fIXed reference
applications with low bandwidth requirements: it has extremely
low offset (50fLV) and in most applications will not require an
offset trim. The AD544L has a much wider bandwidth and
higher slew rate and is recommended for multiplying and other
applications requiring fast settling. An offset trim on the AD544L
may be necessary in some circuits.
General Ground Management: AC or transient voltages between
AGND and DGND can cause noise injection into the analog
output. The simplest method of ensuring that voltages at AGND
and DGND are equal is to tie AGND and DGND together at
2~312
DIGITAL-TO-ANALOG CONVERTERS
C1 LOCATION
~~.:::;::~~=:\;:=:;;;;;;-_
o
INPUT
/
AD1548
PIN 1
Voo-Oro=---7-~
NOTE IN~'b\1~~~~
FEEDTHROUGH
0
o
0
o
o
o
o
o
o ~~~rr~
o
o
o
your
LA
SHOWS COPPER SIDE (i.e., BOTTOM VIEWI
GAIN TRIM RESISTORS R1 AND R2 OF FIGURE 6 ARE NOT INCLUDED,
Figure 9. Suggested Layout for AD7548 and Op Amp
For additional information on multiplying DACs refer to "Application Guide to CMOS Multiplying DIA Conveners", Publication Number G47~1~178, available from Analog Devices.
AD7548
MICROPROCESSOR INTERFACING
AD7548 - MC6800 INTERFACE
A typical 6800 configuration using the automatic transfer mode
of the AD7548 is shown in Figure 10. Table III gives a sample
loading routine written in re-entrant form. Data load and store
instructions use extended addressing. The 12-bit data to be
passed to the subroutine is stored in locations XXYY and XXYY
+ 1. The data is considered right-justified with the four most
significant bits occupying the lower half of XXYY + 1. The
AD7548 is assigned a base address of PPQQ. This address
selects the low byte register of the AD7548. Address PPQQ +
1 selects both the high byte register and the LDAC control
input.
Ao-A15
AD7548 - 8085A INTERFACE
Figure 11 shows a typical AD7548 to 8085A microprocessor
interface configured for automatic transfer of 8 + 4-bit right-justified data. Table IV gives a sample loading routine written in
re-entrant form. The 12-bit data to be passed to the subroutine
is stored in locations XXYY and XXYY + I. The four most
significant data bits occupy the lower half of XXYY + 1. As
before, addresses PPQQ and PPQQ + 1 select the CSLSB and
CSMSB/LDAC control inputs respectively. Since only two instructions (LHLD, SHLD) are required to both fetch and load
the 12-bit data word to the AD7548, it may be more efficient to
insert these instructions as required in the main program rather
than use a subroutine such as illustrated here.
AS·A15
ADDRESS BUS
RliN
v••
ALE
DF/DOR
VMA
CTRl
BOSSA
MC6800
Wii
,~z
AD7548*
ADO-AD7
DO-D7
~'~LI-NU~R-~R~C-UI~TR-Y-O~MI~n~ED---------------------'
FOR CLARITY
+LlNEAR CIRCUITRY OMITTED
FOR CLARITY
Figure 10. AD7548 - MC6BOO Interface (Automatic Transfer
Mode)
WWZZ
JSR
PSHA
TPA
PSHA
LDAA
STAA
LDAA
STAA'
PULA
TAP
PULA
RTS
WWZZ
Jump to AD7548 subroutine
Push A onto stack
Push CCR onto stack
$XXYY
$PPQQ
Load low byte to AD7548
$XXYY+l
$PPQQ+I Load high byte to AD7548
and update analog output
Pull CCR from stack
Pull A from stack
Return to main program
Figure ". AD7548 - BOB5A Interface (Automatic Transfer
Mode)
7548
CALL
PUSH
7548
PSW
PUSH
LHLD
SHLD
POP
H
XXYY
PPQQ
H
POP
RET
PSW
Push register contents
onto stack
Fetch 12-bitdata
Load 12-bit data
Pop register contents
from stack
Return to main program
Table ,V. Sample Routine for AD7548-B085A Interface
Table III. Sample Routine for AD7548 - MC6BOO Interface
DIGITAL-TO-ANALOG CONVERTERS 2-313
2
AD7548 - MC6809 INTERFACE
AD7S48 address, PPQQ from before, selects the CSMSB input
to load the high byte first. In this automatic transfer configuration
LDAC is tied to the CSLSB input. The AD7S48 analog output
can thus be updated using only two instructions as follows:
The AD7S48 can be interfaced to the MC6809 microprocessor
as shown in Figure 12 for automatic transfer of 8 + 4-bit data.
Similar to the 808SA instructions LHLD and SHLD, the 6809
has two instructions to fetch and store 12-bit (l6-bit) data to the
AD7S48, LDD and STD. Howev~, in the 6809, the high byte
of data is moved first, then the low byte (this is the opposite of
the 808SA). This means that if the 12-bit data is assumed to
reside at addresses XXYY and XXYY + 1 then XXYY must
contain the high byte. It also means that the address decoding
logic of Figure 11 must be slightly changed so that the even-order
AO-A15
LDD
STD
$XXYY
$PPQQ
The strobed transfer configuration is shown in Figure 13 with a dedicated decoder output assigned to each chip select input. The common LDAC signal allows simultaneous update of both AD7S48
DAC registers.
1------,
AD
RJW/------I
QIo--..r-... _
MC6809
00-07
...._
I--------------J
DATA BUS
...... *~~~~~UITRV OMITTED
Figure 12. AD7548 - MC68091nterface (Automatic Transfer
Mode)
AO-A15
1-_ _---.
MC6809
v..
RtWl----I
CTRL
Q
v..
DFIDOR
CTRL
AD7548
.------1 WR
DBO-DB7
Figure 13. AD7548- MC6809lnterface (Strobed Transfer
Mode)
2-314 DIGITAL-TO-ANALOG CONVERTERS
AD7548
AD7548 - 6502 INTERFACE
Figure 14 shows a typical AD7548 to 6502 microprocessor interface
configured for automatic transfer of right-justified data. As a
programming example, Figure 15 shows a flow chart for producing
a 12-bit (4095-step-max) voltage ramp under 6502 contro!' Index
registers X and Y of the 6502 form a 12-bit counter with the Xregister holding the.low byte of data and the V-register the high
byte. Table V shows the program listing. The X-register is
compared with FFH and the V-register with 10H to determine
when the ramp voltage has reached its maximum value (FFFH)'
By changing the comparison data in the program the maximum
ramp output voltage can be varied from levels corresponding to
FFFH down to OOOH. In the program listing of Table V the
AD7548 has been assigned contiguous addresses 0400 (low byte)
and 0401 (high byte and DAC register).
ENTER
•
DATA BUS
00·07
·UNEAR CIRCUITRY OMmED
FOR CLARITY
Figure 14. AD7548 - 6502 Interface (Automatic Transfer
ModeJ
Figure 15. FlowChartforVoltageRampGeneration
ADDRESS
OP-CODE
MNEMONIC OPERAND
0000
01
02
03
04
05
06
07
08
09
OA
OB
AO
00
LDY
* 00
A2
LDX
* 00
IMP
0008
OC
OD
OE
OF
10
11
12
13
14
15
16
17
0018
00
4C
08
00
E8
8E
00
04
8C
01
04
EO
FF
DO
F5
C8
CO
10
DO
EB
FO
E7
INX
STX
0400
STY
0401
CPX
*FF
BNE
0007
INY
CPY
* 10
BNE
0002
BEQ
0000
Table V. Program Listing for Figure 15
DIGITAL-TO-ANALOG CONVERTERS 2-315
AD7548 - Z80 INTERFACE
Figure 16 shows a typical AD7548 to Z80 microprocessor interface
configured for automatic transfer of right-justified data. Similar
to the 8085A and 6809 cases, 16-bit load instructions are available
in the Z80 which can fetch and load 12-bit data to the AD7548.
Since t\le low byte of data is moved first and assuming the 12bit data resides at addresses XXYY and XXYY + I, address
XXYY must contain the low byte. As before, addresses PPQQ
and PPQQ + I select the AD7548 CSLSB and CSMSB/LDAC
control inputs respectively. Choosing the Z80 register pair BC
to hold the 12-bit data, the two instructions required to update
the AD7548 analog output are as follows:
AO-AI15
ADDRESS BUS
v~
DF/ooii
CTRL
zao
WR~--------------------~~WR
AD7S48*
OBO--OB7
LD BC, (XXYY)
LD (PPQQ), BC
DATA BUS
·UNEAR CIRCUITRY OMITTED
FOR CLARITY
Figure 16. AD7548 - Z80 Interface (Automatic Transfer
ModeJ
2-316 DIGITAL-TO-ANALOG CONVERTERS
LC 2MOS
Dual 12-Bit f.LP-Compatible DAC
r.ANALOG
WDEVICES
AD7549 I
AD7549 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Two Doubled Buffered 12-Bit DACs
4-Quadrant Multiplication
Low Gain Error (3LSBs max)
DAC Ladder Resistance Matching: 1%
Space Saving Skinny DIP and Surface Mount Packages
Latch-Up Proof
v••
AD7549
APPLICATIONS
Programmable Filters
Automatic Test Equipment
Microcomputer Based Process Control
Audio Systems
Programmable Power Supplies
Synchro Applications
GENERAL DESCRIPTION
The AD7549 is a monolithic dual, I2-bit, current output D/A
converter. It is packaged in both 0.3" wide 20-pin DIPs and in
20-tertnina1 surface mount packages. Both DACs provide four
quadrant mUltiplication capabilities with a separate reference
input and feedback resistor for each DAC. The monolithic
construction ensures excellent thermal tracking and gain error
tracking between the two DACs.
L----------G'~~}-----~'~2--------------~
DB~D80
DGND
The DACs in the AD7549 are each loaded in three 4-bit
nibbles. The control logic is designed for easy processor interfacing.
Input and DAC register loading is accomplished using address
lines AO, AI, A2 and CS, WR lines. A logic high level on the
CLR input clears all registers. Both DACs may be simultaneously
updated using the UPD hlput.
PRODUCT HIGHLIGHTS
l. Small package size: the loading structure adopted for the
AD7549 enables two I2-Bit DACs to be packaged in either a
small 20-pin 0.3" DIP or in 20-terminal surface mount
packages.
The AD7549 is manufactured using the Linear Compatible
CMOS(LC2MOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC or 5V CMOS logic
level inputs.
2. DAC to DAC matching: since both DACs are fabricated on
the same chip, precise matching and tracking is inherent.
This opens up applications which otherwise would not be
considered, i.e., Programmable Filters, Audio Systems, etc.
ORDERING INFORMATIONl
Relative
Accuracy
Tmbl to T""",
Full-Scale
Error
TmbltoT""",
±ILSB
+1/2LSB
±6LSB
+3LSB
±ILSB
±1I2LSB
±6LSB
±3LSB
Temperature Range and Package Options2
Oto +70"C
Plastic DIP (N-20)
- 25°C to + 85°C
Hermetic (0-20)
- 55°C to + 125°C
Hermetic (0-20)
AD7549JN
AD7549KN
AD7549AD
AD7549BD
AD7549SD
AD7549TD
PLCC3 (P-20A)
LCCC4 (E-20A)
AD7549JP
AD7549KP
AD7549SE
AD7549TE
NOTES
ITo order MIL-STD-883, Class B processed parts, add/883B to part number.
Contact your local sales office for military data sheet.
'See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier.
4LCCC: Leadless Ceramic Chip Carrier.
DIGITAL-TO-ANALOG CONVERTERS 2-317
•
= :rl~ :!:5%2, VII£FA = VR£FB = 11!Y; lourA:= loUIB = AGND = OY.
SPECIF.IC"A'TIONS1 All(Yoospecifications
Tmin to T""", unless othelWJS8 specified.)
I,A
K,B
Parameter
Versions
Versions
SVersion
TVersion
Units
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
12
±I
±I
12
±112
±I
12
±I
±I
12
Bits
±112
±I
LSBmax
LSBmax
±6
±3
±6
±3
LSBmax
Measured using internal RFB and includes
effects ofleakage current and gain TC.
AGainI~Temperature
±5
±5
±5
±S
ppmI"Cmax
Typical value is IppmfC
Output Leakage Current
IOUTA (Pin 17)
+25OC
Tnrln to Tmax
IOUTB(Pin IS)
+25OC
20
150
20
ISO
20
2S0
20
250
nAmax
nAmax
DAC A Register londed with all O's
20
ISO
20
ISO
20
2S0
20
2S0
nArnu
nAmax
DAC B Register loaded with all O's
7
7
7
7
18
18
18
k.!lntin
k.!lmax
TypicaiInputResistance~
18
±3
±2
±3
±2
% max
Typically ± 1%
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
V min
V max
±I
Test Coaditions/Comments
All grades guaranteed monotonic over
temperature.
Full Scale Error
Gain TemperatureCoeft1cient~;
TndntoTmax
REFERENCE INPUT
Input Resistance (Pin 19, Pin 13)
11k.!l
VREFAIVREFB
Input Resistance Match
DIGITALINPUTS
VtR (Input High Voltage)
VtL (Input Low Voltage)
lIN (Input Current)
+2SOC
Tmin[oTmax
CIN (Input Capacitance)'
POWER SUPPLY
IDD
±I
±lO
±1O
7
7
±I
±lO
7
±I
±10
7
,.A max
,.A max
pFmax
5
S
S
S
mAmax
VIN=VDD
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test
(Yoo = + 15V; VREFA = VREFB = + IOY,lourA = 10UIII = AGND = OY, Output Amplifiers are AD644 except where stated.)
=+25OC
Parameter
TA
TA=TMIN, TMAX
Units
Test Conditions/Comments
Output Current Settling Time
1.5
-
fJ.Smax
ToO.OI%offullscalenmse. IouTload~ lOOfl,CEXT = 13pF. DACoutputmeasured
from falling edge ofWR. Typical value of Settling Time is 0.8ILs.
Digital-to-Analog Glitch
Impulse
10
-
nV-sectyp
Measured with VREFA=VRFB=OV. IOUTA,IoUTBload= lOOn'~T
DAC registers alternately loaded with all O's and alii's.
AC Feedthrough4
VREFA to IOUTA
V REFB to IoUTB
-70
-70
-65
-65
dB max
dB max
VREFA' V REFB =20Vp-pIOkHzsinewave.
DAC registers loaded with all Os.
Power Supply Rejection
J
20 '9
..
00
00
DSO •
AGND
!
Ii!
",
5
~ Ii! .}
J
3
2
'9
Q
,
20
0
17
R...
IouTA
IOUTA
A07549
16 AGND
TOP VIEW
(Not to Scale)
A' 7
10
18 RpeA
AD7549
A2 •
Q
AGND
TOP VIEW
(Not to Scale)
15 10UTB
,.
14 RFn
AO 8
DGND
•
111
2-320 DIGITAL-TO-ANALDG CONVERTERS
10 11 12 13
I~ ~
Q
2
8
j
•
'0
"
'2
If! I~ ~ i
8
'3
J
10"",
"'os
AD7549
PIN
I
2
3
4
5
6
7
8
9
10
II
12
13
14
IS
16
17
18
19
20
FUNCTION
DESCRIPTION
DB3
DB2
DBI
DBO
UPD
Data Bit 3, Data Bit 7 or Data Bit II (MSB)
Data Bit 2, Data Bit 60r Data Bit 10.
Data Bit I, Data Bit 5 or Data Bit 9.
Data Bit 0, Data Bit 4 or Data Bit 8.
Updates DAC Registers from 4-bit input registers. DAC A and DAC B both updated simultaneously.
Address line 2.
Address line I.
Address line O.
Chip Select Input. Active low.
Write Input. Active low.
Clear Input. Active High. Clears all registers.
Digital Ground.
Voltage reference input to DAC B.
Feedback resistor ofDAC B.
Current output terminal ofDAC B.
Analog ground.
Current output terminal ofDACA.
Feedback resistor ofDAC A.
Voltage reference input to DACA.
+ 15V supply input.
A2
Al
AO
CS
WR
CLR
DGND
VREFB
RFSB
IoUTB
AGND
IOUTA
RF8A
VREFA
Voo
em
~
\ft
A2
Al
AO
FUNCTION
X
X
I
I
I
X
X
X
0
V
X
X
X
0
X
X
X
0
X
X
X
0
0
V
0
0
I
I
0
V
0
I
0
0
I
0
1I
0
I
I
0
I
0
1I
I
0
0
0
I
0
1I
I
0
I
0
I
0
1I
I
I
0
0
I
0
1I
I
I
I
0
0
I
l.J"
X
X
X
No data transfer.
No data transfer.
All registers cleared.
DACA LOW NIBBLE REGISTER
loaded from Data Bus.
DAC AMID NIBBLE REGISTER
loaded from Data Bus.
DACA HIGH NIBBLE REGISTER
loaded from Data Bus.
DAC A Register loaded from
Input Registers.
DACB LOW NIBBLE REGISTER loaded
from Data Bus.
DAC B MID NIBBLE REGISTER loaded
from Data Bus.
DAC B HIGH NIBBLE REGISTER loaded
from Data Bus.
DAC B Register loaded from
Input Registers.
DAC A, DAC B Registers updated
simultaneously from Input Registers.
CLR
0
0
I
X
0
I
0
I
0
,
NOTE: X = Don tCare
Table I. AD7549 Truth Table
DIGITAL-TO-ANALOG CONVERTERS 2-321
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPUCATlON)
Figure 2 shows the circuit diagram for unipolar binary operation.
With an ac input, the circuit performs 2-quadrant multiplication.
The code table for Figure 2 is given in Table II.
Operational amplifiers Al and A2 can be in a single package
(i.e. AD644) or separate packages (AD544). Capacitors CI and
C2 provide phase compensation to help prevent overshoot and
ringing when high speed op-amps are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all O's and amplifier offset adjusted so that VOUTA
or VOUTB is at a minimum (i.e. o;;;120fLV). Full scale trimming
is accomplished by loading the DAC register with aU 1's and
adjusting RI (R3) so that VOUTA (VOUTB) = - VIN (4095/4096).
In fixed reference applications, full scale can also be adjusted by
omitting RI, R2, R3, R4 and trimming the reference voltage
magnitude.
Voo
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is shown
in Figure 3. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust RI (R3) so that VOUTA (VOUTB) = OV. Alternatively, RI,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for VOUTA (VOUTB) = OV. Full scale trimming can be
accomplished by adjusting the amplitude of VIN or by varying
the value of R5 (R8).
Resistors R5, R6, R7 (R8, R9, RIO) must be ratio matched to
0.01%. When operating over a wide temperature range, it is
important that the resistors be of the same type so that their
temperature coefficients match.
The code table for Figure 3 is given in Table III.
v_
R10,20kn
-coNTROL CIRCUITRY OMrnED FOR CLARITY
Figure 2. AD7549 Unipolar Binary Operation
Binary Number in
DAC Register
Analog Output, VOUTA or Voura
MSB
LSB
1111 1111 1111
1000 0000 0000
-VIN(~~)
-VIN e048)
4096 = - 1I2VIN
Figure 3. Bipolar Operation (Offset Binary Coding)
Binary Number in
DAC Register
Analog Output, VOUTA or Voura
MSB
LSB
1111 1111 1111
+VIN e047)
2048
1000 0000 0001
+VIN(2~)
OV
0000 0000 0001
-VIN(~)
1000 0000 0000
0000 0000 0000
OV
01 1 1 1 1 1 1 1 1 1 1
-VIN(2~8)
0000 0000 0000
-VIN(~=)
Table II. Unipolar Binary Code Table for Circuit of
Figure 2
Table 1If. Bipolar Code Table for Offset Binary Circuit of
Figure 3
2-322 DIGITAL-TO-ANALOG CONVERTERS
AD7549
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as Figures
2 and 3 exhibit a code dependent output resistance which in
tum can cause a code dependent error voltage at the output of
the amplifier. The maximum amplitude of this offset, which
adds to the D/A converter nonlinearity, depends on Vos where
Vos is the amplifier input offset voltage. To maintain monotonic operation, it is recommended that Vos be no greater than
(25 x l~) (VREF) over the temperature range of operation. Suitable
op amps are AD644L, AD517L and AD544L. The AD517L is
best suited for fIXed reference applications with low bandwidth
requirements: it has extremely low offset (50 ...V) and in most
applications will not require an offset trim. The AD544L has a
much wider bandwidth and higher slew rate and is recommended
for multiplying and other applications requiring fast settling. An
offset trim on the AD544L may be necessary in some circuits.
AD7S49 - 80SSA INTERFACE
A typical interface circuit for the AD7549 and the 8085A microprocessor is given in Figure 5. Only the bottom 4 bits of the
microprocessor data bus are used. The address decoder provides
both the CS and UPD signals for the DAC. Address lines AO,
AI, A2 select one of six DAC Input Registers for accepting
data. In applications where simultaneous loading of the DACs is
required then the UPD pin must be used to strobe both DAC
registers. Otherwise, UPD may be tied high and address lines
AO-A2, in conjunction with CS and WR signals, will select each
DAC register separately (see Pin Function Description).
Temperature Coefficients: The gain temperature coefficient of
the AD7549 has a maximum value of 5ppmf'C and typical value
of Ippmf'C. This corresponds to worst case gain shifts of 2LSBs
and O.4LSBs respectively over a lOO"C temperature range. When
trim resistors RI(R3) and R2(R4) are used to adjust full scale
range, the temperature coefficient of RI(R3) and R2(R4) should
also be taken into account.
High Frequency Considerations: AD7549 output capacitance
works in conjunction with the amplifier feedback resistance to
add a pole to the open loop response. This can cause ringing or
oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor.
Feedthrough: The dynamic performance of the AD7549 depends
upon the gain and phase stability of the output amplifier, together
with the optimum choice of PC board layout and decoup1ing
components. A suggested printed circuit layout for Figure 2 is
shown in Figure 4 which minimizes feedthrough from VREFA ,
VREFB to the output in multiplying applications.
'LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 5. AD7549-BOB5A Interface
AD7549 - Z80 INTERFACE
Figure 6 shows the AD7549 connected to the Z80 microprocessor.
The interface structure is similar to that for the 8085A.
AODRESS BUS
AO--A1S
I
~~VOUTA
VR FA
•
PIN1AD7~
o
o
o
o
o
o
o
o
~
OOC1
V DD
....... PIN 8 AD644
\,
~~.DGND
COPPER TRACKS ARE ON COMPONENT SIDE
OF PRINTED CIRCUIT BOARD
Figure 4. Suggested Layout for AD7549 with AD644 (Dual
DpAmp)
zso
MREQ
J
1
Jl
~
A2-AO
~~~: [
cs
UPD
AD7549*
WR
WR
00--07
<-
FROM
SYSTEM_ ClR
RESET
...
DATA BUS
DBO--DB3
'LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 6. AD7549-Z80 Interface
DIGITAL-TO-ANALOG CONVERTERS 2-323
AD7549 - 8048 INTERFACE
The AD7S49 can be interfaced to the 8048 single component
microcomputer using the circuit of Figure 7. A minimum number
of 1/0 lines are needed. The system is easily expanded by using
extra port lines to provide Chip Selects for more AD7549's. The
advantage of this interface lies in its simplicity. In either single
or multiple DAC applications both the software and chip select
decoding are simplified over what would be required if the
devices were memory mapped in a conventional manner.
P20
DBO
P21
DB1
P22
DB2
P23
DB3
B048
~.
ALE
LATCH
1
1=
AO
A1
and output circuitry a complete control system can be conflgured
with a minimum number of components.
AD7549 - MC6809 INTERFACE
Figure 8 is the interface circuit for the popular MC6809 8-bit
microprocessor. CS and UPD signals are decoded from the
address for the simultaneous update facility while the WR pulse
is provided by inverting the microprocessor clock, E.
AO·A15
AD7549*
MC6809
al--___r -....
AD7549*
P24
A2
P25
CLR
UPD
P26
PROG
The combination of 8048 system and AD7549 is particularly
suitable for dedicated control applications. By adding reference
WR
.qcs
OO-D7
·LlNEAR CIRCUITRY OMITTED FOR CLARITY
"LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 7. AD7549-8048 Interface
2-324 DIGITAL-TO-ANALOG CONVERTERS
Figure 8. AD7549-MC6809 Interface
CMOS Dual 8-Bit
Buffered Multiplying DAC
AD7628 I
FIIIII ANALOG
WDEVICES
FEATURES
On-Chip Latches for Both DACs
+ 12V to + 15V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible from + 12V to + 15V
Latch Free (Protection Schottkys not Required)
AD7628 FUNCTIONAL BLOCK DIAGRAM
•
APPUCATIONS
Disk Drives
Programmable Filters
X-Y Graphics
Gain/Attenuation
v""a
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. DAC to DAC matching: since both of the AD7628 DACs are
fabricated at the same time on the same chip, precise matching
and tracking between DAC A and DAC B is inherent. The
AD7628's matched CMOS DACs make a whole new range of
applications circuits possible, particularly in the audio, graphics
and process control areas.
The AD7628 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
skinny 0.3" wide 20-pin DIPs and in 20-terminal surface mount
packages.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
2. Small package size: combining the inputs to the on-chip
DAC latches into a common data bus and adding a DAC AI
DAC B select line has allowed the AD7628 to be packaged in
either a small 20-pin 0.3" wide DIP or in 20-terminal surface
mount packages.
Data is transferred into either of the two DAC data latches via a
common 8-bit TIL/CMOS compatible input port. Control
input DAC AlDAC B determines which DAC is to be loaded.
The AD7628's load cycle is similar to the write cycle of a random
access memory, and the device is bus compatible with most 8bit microprocessors, including 6502, 6809, 8085, Z80.
3. TIL-Compatibility: All digital inputs are TIL-compatible
over a + 12V to + 15V power supply range.
The device operates from a + 12V to + 15V power supply and
is TIL-compatible,over this range. Power dissipation is a low
2OmW.
Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for
each DAC.
PIN CONFIGURATIONS
DIP
LCCC
PLCC
1!gl~~
..... 0
a::
a: 0
3212019
..,
,"
VREFA 4
DGNO
V REF B
VDD
17 V OD
AD7628
TOP VIEW
~AIOACB 6
DB1 (M$B)
"
5
INot to Scale)
7
08& 8
'6
15
AD7628
Wii
cs
TOP VIEW
Wii
(Not to Scale)
co
14 DBO ILSB)
9
10 11 12 13
~ ~!!
liH
DBO (LSBI
9
10
i
~ ~ ~ ~
11
12
13
DIGITAL-TO-ANALOG CONVERTERS 2-325
III +15.75Y.
SPECIFIC A'TIONS v... =A+lD.av
= V B = + lIlY; OUT A = OUT B = IIY unless oIharwise specified)
"
(YREF
REF
T" = Oto +7O"C
+2S~1
T,,=
-25~to+85OCI
T,,= -sS'"Cto
+125OC1
Unib
Test Conditioas/Commenhl
STATICPERFORMANCEZ
Resolution
Relative Accuracy
Differential Nonlinearity
8
::112
±1
±1/2
±1
±112
±1
±2
±l
±l
Biu
LSDmu:
LSBmax
This is an Endpoint Linearity Specification
AU Grades Guarantecd Monotonic Ovcr
LSBmax
Measured UsinB lnternalRFB A and RFB B.
Full Operating Temperature Range
BothDAC Latches Loaded with 11111111.
Gain Error is Adjustable Using Circuits
of Figures land2.
Gain Temperature Cocff'aclent3
.1Gain1.ciTemperature
Output Leakage Current
OUTA(P;,,2)
OUTB(P;,,20)
InputR.esistance(VREPA, VREFB)
VII.EP ANREF B
±O.OO3S
±O.OO35
%l'Cmax
8
15
±200
±200
8
15
±200
±200
8
15
nA ....
nAmax
kO ....
kOmax
±1
+1
+1
% ....
±so
±SO
DACLatdleoLoodedwithOOOOOOOO
Inpu' ReaUtancc TC = -lOOppml'C. Typ;cat
Input Resistance is llkO
Input ResistallCe
Malch
DIGITAL INPUTS"
Input High Voltage
V'H
2.4
2.4
2.4
v ....
0.8
0.8
0.8
v ....
Input LowVoltagt
V'L
Input Current
±1
:10
±lO
.,.A max
10
15
10
15
10
15
pF ....
pF ....
160
160
210
10
10
10
160
160
210
10
10
10
''''
160
160
210
D8m
'ON
10
10
10
Dsmm
150
170
210
2
2
2.5
500.
1",
Input Capacitance
DBO-DB7
WR.Cs.DACAlDACB
VIN = OorVDD
SW1TCH1NGCHARACTBRlSTICS'
SeeTbning Imgnm
Chip SeIect to Write Set UpTime
Ics
Chip Select to Write Hold Time
leN
DACSelect toWriteSet UpTime
'AS
DACSeIect to Write Hold Time
'AN
Data vaW to Write Set Up Time
......
......
......
......
Data Valid to WritcHold Time
'Write Pulse Width
''''
"'
....
POWER SUPPLY
IOD,KGrade
B. TGradea
2
100
AIiGrades
mA
AU Digitallnpuu VILorVm
2.5
mA
AlIDiBitai Inputs Vn.orVIH
SOO
.,.A
AlIDigitallnputsOV or VDn
AC PERFORMANCE CHARACTERISTICS
=
These characteristics are included for Design Guidance only and are not subject to test
You
+ 10.BY to + 15.75Y. (Measured Using Recommended P.C. Board Layout and AD644 as Output Amplifiers)
T" = +25"C1
TAo =0 to +700c
-2S"Cto +85OC I
DC SUPPLY REjECl10N
(AGAIN/AVDo)
TAo= -SS"Cto
+USOC1
0.01
0.02
0.02
CURRENT SETTUNG TIME
l50
400
400
DlGITAL-TO·ANALOG GLITCH
IMPULSE
llO
nVsectyp
ForCodeTransitionOOOOOOOOto 11111111
25
25
60
60
25
25
60
60
25
25
60
60
pFmax
pF ....
pFmax
pF ....
DAC Latches Loaded withOOOOOOOO
-70
-70
-65
-65
-65
-65
dBm..
dBmax
VREPA, VREFB == 2OVp-pSiDeWave
@10k11z
Units
%per%max
TeltCoadition8lComaaeats
AV OD = ::!:5%
To lIZLSB. Out AlOut B low! =: 1000.
WR=Cs=OV.
DBO-DB7=OVtoVDD orVDD toOV
OUTPUT CAPACITANCE
COVTA
CouTB
CoUTA
CoUTB
DACLardtes Loaded with 11111111
ACFEEDTHROUGH
VIlEFAtoOUTA
VRBFB to OUT B
CHANNEL-TQ.CHANNEL ISOLATION
VREpAtoOUTB
-80
dB typ
Both DAC Latches Loaded with 11111111.
VRBFA =: lOV p-p Sine Wave Cit: 10kHz
VRWB;: OV
VRBFB =: 20Vp-pSineWave@.,10kHz
IVREJ"A = OV
-80
dBtyp
DIGITAL CROSSTALK
60
nVsectyp
McuurcdforCodcTransitionOOOOOOOO
roUllll11
HARMONlCDlSTORTION
-85
dBtyp
VIN =6Vrms@11dU
VRBFBtoOUT A
NOTES
ITCDlpetatare RaqesueK Venion:Oto + 7O"C
BVersion: -ZS"Cto +8S"C
TVetsioA: - SS"C to + 125"C
2Specific:ationappliel tobotb DACainAD7628.
~~n"!e~ta:::'~'4:put~t(+25"C)itJesatbaulnA.
Spr:dfu:ItiorlawbjecttocJwqcwilhautnotkc.
2-326 DIGITAL-TO-ANALOG CONVERTERS
AD7628
INTERFACE LOGIC INFORMATION
DAC Selection:
Both DAC latches share a common 8-bit input port. The control
input DAC AlDAC B selects which DAC can accept data from
the input port.
Mode Selection:
Inputs CS and WR control the operating mode of the selected
DAC. See Mode Selection Table below.
Write Mode:
When CS and WR are both low the selected DAC is in the
write mode. The input data latches of the selected DAC are
transparent and its analog output responds to activity on D~
DB7.
Hold Mode:
The selected DAC latch retains the data which was present on
DBO-DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
DACAl
DACB
L
H
X
X
CS
WR
DACA
DACB
L
L
H
X
L
L
X
H
WRITE
HOLD
HOLD
HOLD
HOLD
WRITE
HOLD
HOLD
ABSOLUTE MAXIMUM RATINGS
(T A = + 2S"C unless otherwise noted)
. OV, +17V
VootoAGND .
. OV, +17V
Vooto DGND .
AGNDtoDGND
Voo +0.3V
VDO +0.3V
DGNDto AGND
-O.3V, Voo +0.3V
Digital Input Voltage to DGND
-O.3V, Voo +0.3V
VP1N2 , VPIN20 to AGND ..
VREF A, VREF B to AGND . . . . . . .
. ±2SV
VRFB A, VRFB B to AGND . . . . . . .
. ±2SV
Power Dissipation (Any Package) to + 7S·C
4S0mW
6mW/oC
Derates above + 75°C by .
Operating Temperature Range
o to +70·C
Commercial (K) Grades.
- 25°C to + 8S·C
Industrial (B) Grades
- 55°C to + 12S·C
Extended (T) Grades . .
- 65°C to + ISO·C
Storage Temperature . . .
Lead Temperature (Soldering, 10 secs.) .
. . . . . +300°C
CAUTION:
I. ESD sensitive device. The digital control inputs are diode
protected; however, permanent damage may occur on
unconnected devices subjected to high energy electrostatic
fields. Unused devices must be stored in conductive foam
or shunts.
2. Do not insert this device into powered sockets. Remove
power before insertion or removal.
L = Low State H = High State X = Don't Care
Mode Selection Table
WRITE CYCLE TIMING DIAGRAM
ORDERING INFORMATION1
;;;;-\I"\o...---tcs'---i""~ r---- v••
CHIPSELE~
~~_ _ _ _ _ _~~
Relative
Accuracy
---J-I-.---tA'--*~ r - - - - v ••
DAC AlDAC B
Temperature Range and
Package Options2 , 3
Gain
-55OCto
-25°C to
Error
T A = +25·C Oto +70·C +85·C
+125·C
\
Plastic DIP Hermetic
(N-20)
(Q-20)
'-------i--'
~-----v
..
±1I2LSB
±2LSB
Hermetic
(Q-20)
AD7628KN AD7628BQ AD7628TQ
LCCCs
(E-20A)
PLCC4
(P-20A)
------,.
}-:-:-----'-~
DATA IN IDBO-DB7)
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES
MEASURED FROM 10% TO 90% OF +5V.
v DD "" +10.8V TO + 15.75V. tR = tF 20ns.
=
Z. TIMING MEASUREMENT REFERENCE LEVEL IS Viti ; V1L
r - - - - v..
± 1I2LSB
±2LSB
AD7628KP
AD7628TE
NOTES
ITo order MIL-STD-883, Class B processed parts, addl883B to part number.
Contact your local sales office for military data sheet.
'See Section 14 for package outline information.
3Also available in
package (AD7628KR).
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
sorc
DIGITAL-TO-ANALOG CONVERTERS 2-327
•
Applying The AD7628
NOTES:
'A1, R2 AND A3, R4 USED ONLY IF GAIN ADJUSTMENT.s REQUIRED.
SEE TABlE 3 FOR RECOMMENDED VALUES.
~~ :::~~"r~W~:SI~~~~ ==D~WHEN
OSCILLATfON.
Figure 1. Dual DAC Unipolar Binary Operation (2 Quadrant
Multiplication). See Table I.
NOTES:
'At, R2 AND R3. R4 USED ONlY tF GAIN ADJUSTMENT IS REQUIRED.
SEE TAaLl 3 FOR RECOMMENDED VALUES.
ADJUST Rt FOR Vour A '" OV WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR You, B _ IV WITH CODE 10000000 IN DAC B LATCH.
'M...TCHING AND TRACKING IS ESSENnAL FOR R£SISTOR PAIRS AI. R7
AND M. AlD.
1(:1, C2 PHASE CQMPEN$A1l0N !10pF-15pf) MAY BY REQUIRED IF AllAJ
IS A HIGH-SPEED AMPLIFIER.
Figure 2. Dual DAC Bipolar Operation (4 Quadrant
Multiplication). See Table II.
DACLatehCoateDts
MSB
LSB
AaalotIOutput
{DACAorDACB)
DACLatehConteats
Analog Output
(DACAorDACB)
MSB
LSB
11111111
-VIN(~~)
11111111
+VIN (127)
128
10000001
-VIN (I29)
256
10000001
-VINU~:)= -Yr
+
10000000
10000000
0
01111111
-VIN (127)
256
01111111
-VIN(I~8)
00000001
-VIN (127)
128
00000000
(128)
-VlNill
00000001
00000000
-VIN(2~6)
-VIN(2~6)=0
NOlO: lLSB = (2·'XVIN)
NOlO: lLSB = (z"'xvlN) = ~(VIN)
= 1~8 (VIN)
Table II. Bipolar (Offset Binary) Code Table
Table I. Unipolar Binary Code Table
Trim
Resistor
RI;R3
R2;R4
500
150
Table III. Recommended Trim Resistor Values
2-328 OIGITAL-TO-ANALOG CONVERTERS
VIN(1~8)
LC 2MOS
Complete 14-Bit OAC
A07840 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
Complete 14-Bit Voltage Output DAC
Parallel and Serial Interface Capability
SOdS Signal-to-Noise Ratio
Interfaces to High Speed DSP Processors
e.g., ADSP-2100, TMS32010, TMS32020
45ns min WR Pulse Width
Low Power - 70mW typo
Operates from ±5V Supplies
AD7840 FUNCTIONAL BLOCK DIAGRAM
VOUT
LDAC
DGND
CS/SERIAL
WR/SYNC
013/SDATA DO
GENERAL DESCRIPTION
The AD7840 is a fast, complete 14-bit voltage output D/A
converter. It consists of a 14-bit DAC, 3V buried Zener reference, DAC output amplifier and high speed control logic.
The part features double-buffered interface logic with a l4-bit
input latch and 14-bit DAC latch. Data is loaded to the input
latch in either of two modes, parallel or serial. This data is then
transferred to the DAC latch under control of an asynchronous·
LDAC signal. A fast data setup time of 21ns allows direct parallel interfacing to digital signal processors and high speed l6-bit
microprocessors. In the serial mode, the maximum serial data
clock rate can be as high as 6MHz.
The analog output from the AD7840 provides a bipolar output
range of ± 3V. The AD7840 is fully specified for dynamic performance parameters such as signal-to-noise ratio and harmonic
distortion as well as for traditional dc specifications. Full power
output signals up to 20kHz can be created.
The AD7840 is fabricated in linear compatible CMOS
(LC2 MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic.
The part is available in a 24-pin plastic and hermetic dual-in-line
package (DIP) and is also packaged in a 28-terminal plastic
leaded chip carrier (PLCC).
PRODUCT HIGHLIGHTS
1. Complete l4-Bit D/A Function
The AD7840 provides the complete function for creating ac
signals and dc voltages to l4-bit accuracy. The part features
an on-chip reference, an output buffer amplifier and l4-bit
D/A converter.
2. Dynamic Specifications for DSP Users
In addition to traditional dc specifications, the AD7840 is
specified for ac parameters including signai-to-noise ratio and
harmonic distortion. These parameters along with important
timing parameters are tested on every device.
3. Fast, Versatile Microprocessor Interface
The· AD7840 is capable of 14-bit parallel and serial interfacing. In the parallel mode, data setup times of 2lns and write
pulse widths of 45ns make the AD7840 compatible with
modem 16-bit microprocessors and digital signal processors.
In the serial mode, the part features a high data transfer rate
of6MHz.
DIGITAL- TO-ANALOG CONVERTERS 2-329
•
= -t:"~V ~5%, Vss = -5V ±5%, AGND ~ DGND = DV, REF IN = +3V, RL = 2kn, CL= 100pF.
SPEC I·FI C"A'II ONS All(Yoospecifications
T to T unless othelWlse noted.)
min
max
Parameter
I,A'
K,B'
L,C'
s'
T'
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE'
Signal to Noise Ratio' (SNR)
76
78
80
76
78
dB min
Total Harmonic Distortion (THD)
-78
-80
-84
-78
-80
dB max
Peak Harmonic or Spurious Noise
-78
-80
-84
-78
-80
dB max
VOUT = 1kHz Sine Wave, fSAMPLE = 100kHz
Typically 82dB at + 2S"C for 0 -60
5
IL
::Ii
...c......- - t
SCLX
so I--------<~ SOATA
L -_ _- - '
FORMAT
*AoomONAL PINS OMITTED FOR CLARITY
Figure 23. AD7840 - NEC7720 Serial Interface
2-340 DIGITAL-TO-ANALOG CONVERTERS
Figure 24. Power Supply Grounding Practice
AD7840
DATA ACQUISITION BOARD
Figure 25 shows the AD7840 in a data acquisition circuit. The
corresponding printed circuit board (PCB) layout and silkscreen
are shown in Figures 26 to 28. The board layout has three interface ports: one serial and two parallel. One of the parallel ports
is directly compatible with the ADSP-2100 evaluation board
expansion connector.
Some systems will require the addition of a re-construction filter
on the output of the AD7840 to complete the data acquisition
system. There is a component grid provided near the analog
output on the PCB which may be used for such a filter or any
other output conditioning circuitry. To facilitate this option,
there is a shorting plug (labeled LKI on the PCB ) on the analog output track. If this shorting plug is used, the analog output
connects to the output of the AD7840; otherwise this shorting
plug can be omitted and a wire link used to connect the analog
output to the PCB component grid.
The board also contains a simple sample-and-hold circuit which
can be used on the output of the AD7840 to extend the very
good performance of the AD7840 over a wider frequency range.
A second wire link (labelled LK2 on the PCB) connects VOUT
(SKTI) to either the output of this sample-and-hold circuit or
directly to the output of the AD7840.
INTERFACE CONNECTIONS
There are two parallel connectors, labeled SKT4 and SKT6,
and one serial connector, labeled SKT5. A shorting plug option
(LK8 in Figure 25) on the AD7840 CS/SERIAL input configures the DAC for the appropriate interface (see Pin Function
Description).
SKT6 is a 96-contact (3-row) Eurocard connector which is
directly compatible with the ADSP-2100 Evaluation Board Prototype Expansion Connector. The expansion connector on the .
ADSP-2100 has eight decoded chip enable outputs labeled ECEI
to ECE8. ECE6 is used to drive the AD7840 CS input on the
data acquisition board. To avoid selecting on-board sockets at
the same time, LK6 on the ADSP-2100 board must be
removed. The AD7840 and ADSP-2100 data lines are aligned
for left justified data transfer.
SKT4 is a 26-way (2-row) IDC connector. This connector contains the same signal contacts as SKT6 and in addition contains
decoded RJW and STRB inputs which are necessary for
TMS32020 interfacing. This decoded WR can be selected via
LK4. The pinout for this connector is shown in Figure 29.
SKT5 is a nine-way D-type connector which is meant for serial
interfacing only. The evaluation board has the facility to invert
SYNC line via LK7. This is necessary for serial interfacing
between the AD7840 and DSP processors such as the DSP56000
The SKT5 pinout is shown in Figure 30.
SKTI, SKT2 and SKT3 are three BNC connectors which provide connections for the analog output, the LDAC input and an
external reference input. The use of an external reference is
optional; the shorting plug (LK3) connects the REF IN pin to
either this external.reference or to the AD7840's own internal
reference.
Wire links LKS and LK6 connect the Dll and DIO inputs to
the data lines for parallel operation. In the serial mode, these
links allow the user to select the required format and justification for serial data (see Table I).
POWER SUPPLY CONNECTIONS
The PCB requires two analog power supplies and one 5V digital
supply. Connections to the analog supplies are made directly to
the PCB as shown on the silkscreen in Figure 26. The connections are labelled V + and V - and the range for both of these
supplies is 12V to 15V. Connection to the 5V digital supply is
made through any of the connectors (SKT4 to SKT6). The
-SV analog supply required by the AD7840 is generated from a
voltage regulator on the V - power supply input (ICS in
Figure 25).
SHORTING PLUG OPTIONS
There are eight shorting plug options which must be set before
using the board. These are outlined below:
LKI
Connects the analog output to SKTI. The analog output may also be connected to a component grid for
signal conditioning.
LK2
Selects either the AD7840 VOUT or the sample-andhold output.
LK3
Selects either the internal or external reference.
LK4
Selects the decoded RJW and STRB inputs for
TMS32020 interfacing.
LKS
Conftgures the DlllFORMAT input.
LK6
Configures the DIO/JUSTIFY input.
LK7
Selects either the inverted or noninverted SYNC.
LK8
Selects either parallel or serial interfacing.
COMPONENT LIST
ICI
AD7840 Digital-to-Analog Converter
IC2
AD711 Op Amp
IC3
ADG20lHS High Speed Switch
IC4
74HC221 Monostable
ICS
79LOS Voltage Regulator
IC6
74HC02
CI, C3, CS, C7,
Cll, Cl3, CIS, Cl7
lOf.LF Capacitors
C2, C4, C6, C8,
C12, C14, C16, Cl8
O.If.LF Capacitors
C9
330pF Capacitor
CIO
68pF Capacitor
RI, R2
2.2kO Resistors
R3
ISkO Resistor
RPI, RP2
lOOkO Resistor Packs
LKI, LK2, LK3,
LK4, LKS, LK6,
LK7, LK8
Shorting Plugs
SKTl, SKT2, SKT3
BNC Sockets
SKT4
26-Contact (2-Row) IOC Connector
SKT5
9-Contact D-Type Connector
SKT6
96-Contact (3-Row) Eurocard
Connector
DIGITAL-TO-ANALOG CONVERTERS 2-341
•
R2
2102
ClO
R3
-
.&1<
Q
~rl R'
v+-t-1'--t:::;-I"l-l
?... l i ..';!. 1...-1
· V
~~- ···f
IC4
2112
v-
.~.
¥
.•.,;,... BA
I
LK2-
'V
+IV
v.
/
~ B~
l.;" ~E(~
V..
........ IN1'UT
Cil----------Wii/SvIiC t-
You,
D,"FORMAT
ICI1
8
D••/JUSTIFY
:~ t:
~I
r
+5V
~
---.
I
•
2
I
~
••• 5 • 25," 22
•••
815
...
"T-
DIGITAL
GROUND
~
~
SKT.
DMD2
~
•
I
DMP1'
~A:
'"
=·I'~'p··~'
r.W;-~~;-;0UT~~-5~V~~~
DMD••
LKI
•• •• 11
23,"11'
5
•
2
•
I SKT5
~--------~--------~~-----~
*10CN1; PUU UP AESISTORS (RESISTOR PACKS RPt and RP21
Figure 25. Data Acquisition Circuit Using the AD7840
~A
OOB
fJ,
Q
+
Q
EUALJl,fTl~-t\oARD
REF
IN
~
~
000000000000
cR::J-o
000000000000
+
000000000000
000000000000
000000000000
o 0 C
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
~
000000000000
0
0
ICt
0
00
000000000000 CII ~2 0
0 ~+
000000000000
~
0
0
~
0
000000000000
0
0
CI3
00
000000000000
0
0
00000000000000 +
0
0
00000000000000
0
0
i
OORDo
00000000000000
A~ ~ ~ 00o OOB
00000000000000
BOO 00 00
o
OOC
00000000000000
00000000000000 0
0
00000000000000
CI8
00000000000000
~~ 00000000;[000000
00000000000000 CIS
~
00000000000000
00000000
0000000
00000000000000
00000000000000
ICi
IC6
00000000000000
00000000000000
00000000000000
~ ~+~Ct
gOt
~~
~
I
00
00
00
00
SKH 00
00
00
00
00
00
0
00
0
0
o 0
OO~
SILKSCREEN
Figure 26. PCB Silkscreen for Figure 25
2-342 DIGITAL-TO-ANALOG CONVERTERS
~~O o
0
#
I
0
AP2
I
ao
6- b
.
B5
·a11
(.~
ALKS~V.J>-..---+
T+-H +++-..:DM;;;;;;.D',3 813
V,,~.
'V
.
C22
B
A
~~DATA8U~/.ff//ff/7//).
DO-
DONO
iiMWIi
DMD15
~I
AGND
DB-
V-
B5
DMD14
D••/SCLI( I-I--++-_-------+-+-IH-++-=~
812
CJ'~ .~_
REFIN
OUTPUT
I~
f
REFOUT D••/SDATA
AD7840
~
A
LKI
INPUT
~
EDMACK
SKra
LK' )
SKT.
ANALOO
SKTI
+5V~
ft-;:::=====+---.-...--,....-----_____~
I
,~,
';!.
IJiliC
IJiliC
.~
o.!. -5V
iCii
0
0
0
0
I
I0
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
0
.
AD7840
••
3.94n
(100mm)
•••
•••
•••
•• ••
••
•• ••
••
••
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••••••••••••••
••••••••••••••
...
...
•
....
COMPONENT SIDE
Figure 27. PCB Component Side Layout for Figure 25
•
.
••••••••••••
••••••••••••
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••••••••••••••
•
SOLDER SIDE
Figure 28. PCB Solder Side Layout for Figure 25
...
DIGITAL-TO-ANALOG CONVERTERS 2-343
R/iN
NC
cs
NC
012
010
08
06
04
02
DO
5V
GNO
00
00
00
00
CD@
@@
@@
@@
@@
@@
@@
@@
@@
STRB
WR
NC
NC
013
011
.....
09
07
a;
!~ '"
'"
0 0 0 00
0 0 CD 0
'"
...J
05
03
01
5V
GNO
Figure 29. SKT4, IDC Connector Pinout
2-344 DIGITAL-TO-ANALOG CONVERTERS
<.J
Z
<.J
z<.J
<.J
z
0
<.J
z
0
z
".,
Figure 30. SKT5, 0- Type Connector Pinout
1IIIIIIII ANALOG
WDEVICES
FEATURES
12-Bit CMOS MDAC with Output Amplifier
4-Ouadrant Multiplication
Guaranteed Monotonic ITmin to T maxi
Space-Saving 0.3", 24-Pin DiPs and 28-Terminal
Surface Mount Packages
Application Resistors On Chip for Gain Ranging. etc.
Low Power LC2 MOS
LC2MOS
Complete 12-Bit Multiplying OAe
AD7845 I
AD7845 FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Automatic Test Equipment
Digital Attenuators
Programmable Power Supplies
Programmable Gain Amplifiers
Digital-to-4-20mA Converters
GENERAL DESCRIPTION
The AD7845 is the industry's first 4-quadrant multiplying D/A
converter with an on-chip ampliller. It is fabricated on the
LC2MOS process, which allows precision linear components and
digital circuitry to be implemented on the same chip.
PRODUCT HIGHLIGHTS
1. Voltage Output Multiplying DAC
The AD7845 is the first DAC which has a full4-quadrant
multiplying capability and an output ampliller on-chip.
All specifications include amplifier performance.
The 12 data inputs drive latches which are controlled by standard
CS and WR signals, making microprocessor interfacing simple.
For stand-alone operation, the CS and WR inputs can be tied to
ground, making all latches transparent. All digital inputs are
TIL and 5V CMOS compatible.
2. Matched Application Resistors
Three application resistors provide an easy facility for gain
ranging, voltage offsetting, etc.
The output amplifier can supply ± lOY into a 2k!l load. It is
internally compensated, and its input offset voltage is low due
to laser trimming at wafer level. For normal operation, RFB is
tied to VOUT, but the user may alternatively choose R A , RD or
Rc to scale the output voltage range.
3. Space Saving
The AD7845 saves space in two ways. The integration of the
output ampliller on-chip means that chip count is reduced.
The part is housed in a skinny 24-pin, 0.3" DIP and 28-terminal
surface mount package.
DIGITAL-TO-ANALOG CONVERTERS 2-345
•
.'TIONS1 = + 15V, ±5%,Vss ::; -l5V, ± 5%, V/IfF = +lOV,AGND =DGND =BY,
SPECIFIC
."
Voor connecllld to "". Your load = 2kO. 100pF. AH specifications T... to T... unless otherwise
-
(VI!D
KVenioa
AV.....
BV. . . .
SV""'"
TVenioa
u....
T"'~
12
12
12
12
12
12
Bib
ILSB =
±I
±I
±I
±112
±314
±112
±r-
"I
±1/2
~2
±I
±I
±I
±I
±I
LSBmax
LSBmax
LSSmax
AJllrades are guaranteed
±3/2
±I
±2
±4
±I
±3
±2
±4
±I
±3
±2
±I
±4
mV ....
mV ....
±5
±6
,,9
±5
±6
±9
±9
±5
,,6
±9
,,9
±lO
"VFCtyp
±3
±6
±6
LSBmax
R FR• VOVTconnected.
"g
LSBmax
LSB ....
LSBmax
Rc, VOUTconnccted., VREP = + SV
±10
±5
±3
±6
±6
,,8
±S·
±IO
±5
±3
±6
±6
±8
RB, VOUTCODDeCted., VRBF = +SV
RAJ VQUTconnected, VRfiF = 2.SV
,,2
,,2
,,2
,,2
±2
±2
ppmofFSRrC
RFB. VOUTCOOoec:ted.
ACCURACY
'Resolution
RelativeAccuracy
at +2S"C
T .... toT....
Differential NOJilinearjty
ZeroCode OffsetEnvr
at +25"<:
T.-toT_
sIaIad.)
IV.......
±I
±,L
VRl!P
ZU
~ 2.4mV
monotonic over temperature
DACrqistCl' loaded with
aliOs.
OffsetTemperaturc: Coefficientj
(<1Ofr.et1<1Temperanue)'
Gain Error
:t9
Gain TemperatureCoefficient;
(<1Gainl<1TemperatureJ'
typ
REFERENCE INPUT
8
16
8
16
8
16
8
16
8
16
8
16
knmin
APPUCATIONRESISTOR
RATIO MATCHING
0.5
0.5
0.5
0.5
0.5
0.5
%max
OIGITALINPUTS
V1H(lnputHiJbVol_)
VII. (Input Lnw Vol_)
lIN (Input Current)
CIN(lnputCapac:itancc:J'
2.4
0.8
±I
7
2.4
0.8
±I
7
2.4
0.8
±I
7
2.4
0.8
±I
7
2.4
0.8
±I
7
2.4
0.8
±I
7
Vmin
V max
POWERSUPPLr
VDDRan&e
VssRan&e
VminNrnax
14.25/15.75
14.25/15.75
14.25/15.75
14.25/15.75
14.25/15.75
14.25/15.75
-14.251-15.75 -14.251-15.75 -14.251-15.75 -14.251-15.75 -14.251-15.75 -14.251-15·.75 VminlVmax
Input Resistance. Pin 17
Power Supply Rejection
~GainlAVOD
AGain/AVss
100
I"
±O.2
±O.l
10
4
I
,,0.2
::to.2
10
4
I
±0.2
±0.2
10
I
4
±0.2
±O.2
I
10
4
,,0.2
"0.2
10
4
I
±0.2
±O.l
10
4
TypicaliDputresistance = 12k!1
klJmax
,.A max
Matching between RAJ Ra. Rc
Digital Inputs at OV and VDD
pFmax
I
% per % max
%per%max
mAmax
mAmax
VOD
= 15V ± 5%, VltEF =
-lOY
Vss'" -lSV±S%.
V OUT unloaded.
VOUTunloaded.
AC PERFORMANCE CHARACTERISTICS
111858 characteristics are included for Design Guidance and are not subject to test
OYNAMICPERFORMANCE
Output VoltageScmliag Time
5
5
5
5
5
5
.... max
To O.OI%offun·scalennae.
VOUTload = 2kll, lOOpF.
OAC register alternately loaded.
with all Os andallIs. Typically
2.5"sat 25'C.
VOUTload = Zkll.lOOpF.
Slew Rate
Oigital·...Analo8
Glitch Impulse
7
450
7
450
7
450
7
450
7
450
7
450
V/".typ
nV~styp
Measured with VRfiP ,.. OV.
DAC register alternately loaded
Multiplying Feedthrough
5
5
5
5
5
5
mVp-ptyp
VRHF ""
withallOsand allis.
Error3
:t IOV,
10kHz sine wave
OAt; register loaded withall Os.
Unity Gain Small Signal
Bandwidth
600
600
600
600
600
600
kHztyp
V0 1.ITI R""Bconneaed. DAe loaded
withallls,VRBF= lOOmVp-p
sine wave.
Full Power Bandwidth
250
250
250
250
250
250
kHztyp
VQUTI
Rpftconnected. DACloadcd.
with.n Is. VRHF = 20Vp-p
sinewave. RI . = 21tH.
TOIal Harmonic Distortion
OUTPUT CHARACTERISTICS'
Open Loop Gain
-90
-90
-90
-90
-90
-90
dBtyp
VRF.F = 6Vtms,lkHzsinewave.
85
85
85
85
85
85
dB min
V OUT, RpB Dot connected
Output Voltage Swing
:tIO
" 10
:tIO
:tIO
±IO
±IO
Vmin
R,. = 2k11,CI. = lOOpF
Output Resistance
0.2
15
0.2
15
0.2
15
0.2
15
0.2
15
0.2
IS
lltyp
mAtyp
VoUTshonedtoAGNO
VOUT= ±10V,R•. =2kU
Shott Circuit Cu.rrcnt ((I + 25"<:
Output Noise Voltage
(O.lHztolOHz)(ff +25OC
f= 10Hz
f= 100Hz
f=lkHz
f= 10kHz
f= 100kHz
2
250
100
50
50
50
2
250
100
50
50
50
2
250
100
50
50
50
NOTES
'TempennucRanaesaftasfollows: J,KVenions:Oto +7O"C
A.BV~ -25"Cto +as"C
S. TVenions: - 55'"C to + 12S'"C
lSample lelted toeasurecornpJidee.
-'Tbemelallicionthec:eramicD-24A.~isCOftMCtedIOPialZ(DGND).
4Tlwdevice .(unc:tionIlwithapowcrsupplyof:!; IN. Sec Fipre6.
'MWawmspecincdloldresistaDCeis2kO.
Spedfic:alionssub;ecl todwtpwitboul noIice.
2-346 DIGITAL-TO-ANALOG CONVERTERS
2
250
100
50
50
50
2
250
100
50
50
50
2
250
100
50
50
50
..,Vrmstyp
nVYHztyp
nVYHztyp
nVVHZtyp
nVYHztyp
nVYHztyp
RFBI VOUTconnectcd,
lndudesnoise due to output
ampJiflCTand Johnson Noise
ofRp •
AD7845
TIMING CHARACTERISTICS (Villi = +15Y, :1:5%. Vss= -15Y, :l:5%. VREF = + lOY. AGND = DGND = OY.>
Parameter
tcs
tcH
t\1VR
tos
tOH
Limit at
T A +2S'C
Limit at
TA Oto +70"C
TA
2S"C to + 8S"C
Limitat .
TA -SS"C
to +12S'C
Units
Test Conditions/Comments
100
0
100
100
20
135
0
135
100
20
140
0
140
120
20
nsmin
nsmin
nsmin
nsmin
nsmin
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
Data Setup Time
Data Hold Time
=
=
=-
=
Specifications subject to change without notice
ABSOLUTE MAXIMUM RATINGS·
(TA = + 25°C unless otherwise stated)
Vooto DGND
Vss to DGND.
VREPto AGND
VRFB to AGND
VRA to AGND
VRB toAGND
VRC to AGND
Vour to AGND 1
AGND toDGND
Digital Input Voltage to DGND
Power Dissipation (Any Package)
To +7SoC • . . . . .
Derates above + 75°C .
. -0.3V, + 17V
. +O.3V, -17V
±2SV
±2SV
±2SV
±2SV
±2SV
Voo +O.3V, Vss -O.3V
-O.3V, Voo
-O.3V, Voo +O.3V
. 6S0mW
IOmW/OC
Operating Temperature Range
Commercial G, K Versions)
Industrial (A, B Versions)
Extended (S, T Versions) •.
Storage Temperature . . . . .
Lead Temperature (Soldering, 10sec)
NOTE
'VOUT may be shorted to AGND provided that the power dissipation of the
package is not exceeded.
*Stresses above those listed under ..Abaolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indio
cated in the operational sections of this specification is not implied. ExpoSure
to abaolut. maximum rating conditions for extended periods may affect
device reliability. Only one Absolute Maximum Rating may be applied al any
onetime.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect·
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
I.....---lcs---.......I tcH
t--r-___ 5V
: y
CS\
OV
}r-----::
1///$A~---JW&::
t--t_--l
DATA
Relative
Accuracy
+2S'C
±lLSB
±1I2LSB
NOTES
1. All INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
10% to 90% of +5V. t.=t.=20no.
Figure ,. AD7B45 Timing Diagram
0
~~DEVICE
Temperature Range and Package Options2
Oto +700C -2S'Cto
-S5'Cto
+8SOC
+ 12soC3
Plastic DIP Hermetic DIP Hermetic DIP
(Q.24)
(Q.24)
(N·24)
1--
2. TIMING MEASUREMENT REFERENCE LEVEL IS V", 2+ Va
WARNING!
ORDERING INFORMATION l
WR - - - -....."
i-tDO...j tDH
. . . 0 to +70°C
- 25°C to + 8SOC
- SSOC to + 12SOC
-65°C to + IS00C
. . . . . +300OC
±ILSB
±lf2LSB
AD7845JN AD7845AQ
AD784SKN AD784SBQ
PLCC4
(P·28A)
AD784SSQ/883B
AD784STQ/883B
LCCCs
(E.28A)
AD7845JP
AD7845KP
AD7845SE
1883B
NOTES
'Analog Devices reserves the righl to ship either ceramic (D-24A) or
cerdip (Q-24A) hermetic packages.
'See Section 14 for package outline information.
'To order MIL·STD.883, Class B processed parts, add /883B 10 part
number.
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: LeadIess Ceramic Chip Carrier. Available to 883B processing only.
DIGITAL·TO·ANALOG CONVERTERS 2-347
PIN CONFIGURATIONS
DIP
PLCC
LCCC
..
~
!;
Iii
Iii
Q
Q
~
l;l
;
3
1
28 27 26
•
. J .
iD
!"'
2
,j
r1
!
rJ! rl
-
LJ
DBS 5
l;l
R.
25 R.
V••
24 Voo
DB8 6
087 7
AD7845'
NC 8
TOPVIEW
(Notto &c.Ia)
D. . .
23 Vss
AD7845'
V"
22 NC
TOPVIEW
(NottoScala)
NC
21 AGND
08510
20 V AEF
DB411
19
12 13
13Q IIIQ
"Z
Q
"
15 16
18
U
I~
Z
Iii
Q
VREF
CS
CS
Q
13
!II
Q
Q
Q
Z
g
l;l Iii
Q
+NC "" NO CONNECT
!
I~
iD
~
*Ne = NOCONNECT
TERMINOLOGY
LEAST SIGNIFICANT BIT
This is the analog weighting of 1 bit of the digital word in a
DAC. For the AD7845, lLSB =
Va;~
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., offset and gain error are
adjusted out) and is normally expressed in least significant bits
or as a percentage of full-scale range.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal ILSB change between any two adjacent
codes. A specified differential nonlinearity of + lLSB max over
the operating temperature range ensures monotonicity.
GAIN ERROR
Gain error isa measure of the output error between an ideal
DAC and the actual device output with all Is loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer. See Figure 13.
ZERO CODE OFFSET ERROR
This is the error present at the device output with all Os loaded
in the DAC. It is due to the op amp input offset voltage and
bias current and the DAC leakage current.
TOTAL HARMONIC DISTORTION
This is the ratio of the root-mean-square (rms) sum of the harmonics to the fundamental, expressed in dBs.
OUTPUT NOISE
This is the noise due to the white noise of the DAC and the
input noise of the amplifier.
2-348 DIGITAL-TO-ANALOG CONVERTERS
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nY-sees
depending upon whether the glitch is measured as a current or
voltage. The measurement takes place with VREF = AGND.
DIGITAL FEEDTHROUGH
When the DAC is not selected (i.e., CS is high) high frequency
logic activity on the device digital inputs is capacitively coupled
through the device to show up as noise on the VOUT pin. This
noise is digital feedthrough.
MULTIPLYING FEEDTHROUGH ERROR
This is ac error due to capacitive feedthrough from the VREF
terminal to VOUT when the DAC is loaded with all Os.
OPEN LOOP GAIN
Open loop gain is dermed as the ratio of a change of output
voltage to the voltage applied at the V REF pin with all Is loaded
in the DAC. It is specified at dc.
UNITY GAIN SMALL SIGNAL BANDWIDTH
This is the frequency at which the magnitude of the small signal
voltage gain of the output amplifier is 3dB below unity. The
device is operated as a closed'loop unity gain inverter (i.e.,
DAC is loaded with all Is).
OUTPUT RESISTANCE
This is the effective output source resistance.
FULL POWER BANDWIDTH
Full power bandwidth is specified as the maximum frequency,
at unity closed loop gain, for which a sinusoidal input signal
will produce full output at rated load without exceeding a distortion
level of 3%.
Typical Performance Curves - AD7845
1:2
~,
~
~ 200
-B
(a
I
1kHz
-24
,.
-40
'DO
'D'
100k
10
10M
'M
FREQUENCY _ Hz
~
100
LOAD RESISTANCE -
Figure 2. Frequency Response, G = - 1
-25
10.
"
'0
100
I.
Figure 4. Noise Spectral Density
200
V DD = +15V
V sa =-15V
VREl'=2OV pop
OAC CODE: DO ... 000
'.0
VREF=+7.5V
J
I ..
'40
~
>
INTEGRAL UNEARITY ERROR
1.--I-
_I---
-so
-7.
-
V
,.
-'00
'00
0.1
1
120
1
V
'"
.0
.0
40
20
lOOk
Figure 5. THD vs. Frequency
10
"
'2
I.
13
VoJVss-Volts
I.
,.
Figure 6. Typical AD7845 Linearity vs.
Power Supply
'00
I.
L/
10.
FREQUENCY - Hz
'OOk
Figure 7. Multiplying Feedthrough
Error vs. Frequency
DBo-
1+ ==
-
DB11
!
+
~I
t
-,--
--
:=-1 V
n!
!r'+-II~
sv
I
I
~,
Ij
,j
1M
I
6
Al!
DIFFERENTIAL UNEARITY ERROR-
0.0
FREQUENCY - Hz
,
E
J
/
10.
lOOk
10.
FREQUENCY - Hz
TA=+~'"C
...
VAEF=SVrms
GAIN=-1
n
'"
Figure 3. Output Voltage Swing vs.
Resistive Load
0_5
VOD ::::: +15V
Vss= -15V
\
w 100
v
-32
'\
l!l
VDO= +1SV
Vss =-15V
V RU =3DV pop
-,.
Voo - +15V
Vss= -15V
VREF=OV
DACCODE: 11 ... 111
300
l~
VOUT
~---
PS I
I
Figure 8. Unity Gain Inverter Pulse
Response (Large Signal)
Figure 9. Unity Gain Inverter Pulse
Response (Small Signal)
Figure 10. Digital-to-Analog Glitch
Impulse (AII1s to All Os Transition)
DIGITAL- TO-ANALOG CONVERTERS 2-349
•
PIN FUNCTION DESCRIPTION (DIP)
Pin
Mnemonic
Description
I
2-11
12
13-14
IS
16
17
18
19
20
21
22
23
24
Vour
DBll-DB2
DGND
DBI-DBO
WR
CS
VREF
AGND
Vss
VDD
RA
RB
Voltage Output Terminal
Data Bit II (MSB) to Data Bit 2
Digital Ground. The metal lid on the ceramic package is connected to this pin
Data Bit I to Data Bit 0 (LSB)
Write Input. Active low
Chip Select Input. Active low
Reference Input Voltage which can be an ac or dc signaJ
Analog Ground. This is the reference point for external analog circuitry
Negativepowersupplyfortheoutputamplifier(nominai-12Vto -lsV)
Positive power supply (nominai + 12Vto + 15V)
Application resistor. RA = 4RFB
Application resistor. RB = 2RFB
Application resistor. Rc = 2RFB
Feedback resistor in the DAC. For normal operation this is connected to Your
Rc
RFB
CIRCUIT INFORMATION
Digital Section
Figure 11 is a simplified circuit diagram of the AD7845 input
control logic. When CS and WR are both low, the DAC latch is
loaded with the data on the data inputs. All the digital inputs
are TTL, HCMOS and + 5V CMOS compatible, facilitating
easy microprocessor interfacing. All digital inputs incorporate
standard protection circuitry.
D/A Section
Figure 12 shows a simplified circuit diagram for the AD7845
D/A section and output amplifier. The D/A converter is a standard
R-2R ladder. Binarily weighted currents are switched between
AGND and the inverting terminal of the on-chip output amplifier.
The output amplifier and feedback resistor RFB perform the
current-ta-voltage conversion. When connected in the standard
configuration (i.e., RFB connected to Your),
VOUT
= -D·
V REF,
where D is the fractional representation of the digital input
code. D can vary from 0 to 4095/40%.
INPUT
BUFFERS
WR------------------r-">----1
CS-----------------L~
Figure 11. AD7845 Input Control Logic
The amplifier can maintain ± 10V across a 2kO load. It is internally
compensated and settles to 0.01% FSR (1I2LSB) in less than
5jl.s. The input offset voltage is laser trimmed at wafer level.
The amplifier slew rate is typically 7V/jl.s, and the unity gain
small signal bandwidth is 600kHz. There are three extra on-chip
resistors (RA, R B, Rc) connected to the amplifier inverting terminal. These are useful in a number of applications including
offset adjustment and gain ranging.
Figure 12. SlmpiifiBd Circuit Diagram for the AD7845 DIA
Section and Output Amplifier
2-350 DIGITAL-TO-ANALOG CONVERTERS
AD7845
UNIPOLAR BINARY OPERATION
Figure 13 shows the AD7845 connected for unipolar binary
operation. When VIN is an ac signal, the circuit performs 2quadrant multiplication. The code table for Figure 13 is given
in Table I.
v••
VlNo-W,.,..-..,
BIPOLAR OPERATION
(4-QUADRANT MULTIPUCATION)
The recommended circuit for bipolar operation is shown in
Figure 14. Offset binary coding is used.
The offset specification of this circuit is determined by the
matching of internal resistors RB and Rc and by the zero code
offset error of the device. Gain error may be adjusted by varying
the ratio of RI and Rl.
To use this circuit without trimming and keep within the gain
•
error specifications, resistors RI and Rl should be ratio matched
to 0.01%.
v..
The code table for Figure 14 is given in Table II.
R2
1QkO
R1
10kU
v,. 0-""''''''''''''''''
Vas
Figure 13. Unipolar Binary Operation
BiJwy Number In
DAC Register
AnaiogOutput,
Vour
1111
LSB
1111
-V~(::)
1000
0000
0000
-V~(=) = -1I2V~
0000
0000
0001
-V~(~)
0000
0000
0000
OV
MSB
1111
Table I. Unipolar Binary Code Table for AD7845
OFFSET AND GAIN ADJUSTMENT FOR FIGURE 13
Zero Offset AdjuSbnent
1. Load DAC with all Os.
Trim R3 until
=
2.
VOUT OV.
Gain AdjUSbnent
1. Load DAC with all Is.
2. Trim Rl so that VOUT = - VIN
V ••
Figure 14. Bipolar Offset Binary Operation
Binary Number In
DAC Register
Analog Output,
MSB
Illl
llli
LSB
1111
1000
0000
0001
+VIN(2~)
1000
0000
0000
OV
0111
1111
1111
-VIN(2~8)
0000
0000
0000
-VIN(~:) =
4095
40%
In fixed reference applications, full scale can also be adjusted by
omitting Rl and Rl and trimming the reference voltage magnitude.
For high temperature applications, resistors and potentiometers
should have a low temperature coefficient.
Vour
+V e047)
2048
~
-VIN
Table II. Bipolar Code Table for Offset Binary Circuit of
Figure 14
DIGITAL- TO-ANALOG CONVERTERS 2-351
APPLICATIONS CIRCUITS
PROGRAMMABLE GAIN AMPLIFIER (PGA)
The AD7845 performs a PGA function when connected as in
Figure 15. In this conftguration, the R-2R ladder is connected
in the amplifier feedback loop. RFB is the amplifter input resistor.
As the code decreases, the R-2R ladder resistance increases and
so the gain increases.
PROGRAMMABLE CURRENT SOURCES
The AD7845 is ideal for designing programmable current sources
using a minimum of external components. Figures 16 and 17
are examples. The circuit of Figure 16 drives a programmable
current IL into a load referenced to a negative supply. Figure 17
shows the circuit for sinking a programmable current, IL. The
same set of circuit equations apply for both diagrams.
R OAC I
( D=Oto 4095)
VOUT= -VIN'O'RFB'
4096
R OAC
I
-VIN ' -D- ' R
-OAC
=
-VIN
.
--0 ' smce RFB
= R OAC
D. IVINI, (D = Oto-4095)
II = ROAC
4096
_ J... (D . IVINI)
12 -
RI
R OAC
_ D· IVINI.
RFB -
D 'IVINI
D 'IVINI
RI
R OAC
D· IVINI .
(I + ..BL)
R
RI
_
' smce RFB - R OAC
IL = - - - + - - =
RI
OAC
Note that by making RI much smaller than R OAC , the circuit
becomes insensitive to both the absolute value of R OAC and its
temperature variations. Now, the only resistor determining load
current IL is the sense resistor RI.
If RI = lOOn, then the programming range is 0 to lOOmA, and
the resolution is 0.024mA.
Figure 15. AD7845 Connected as PGA
As the programmed gain increases, the error and noise also
increase. For this reason, the maximum gain should be limited
to 256. Table III shows gain versus code.
V.
Voo
RI
Gain
Error(%)
1111
1111
1111
4096/4095 "'I
1000
0100
0010
0001
0000
0000
0000
0000
0000
0000
0000
0000
1000
0100
0010
0001
0000
0000
0000
2
0.04
0.07
0.13
0.26
0.51
1.02
2.0
4.0
8.0
Dilitallaputs
0000
0000
0000
0000
0000
4
8
16
32
64
128
256
Table III. Gain and Error VB. Input Code for Figure 75
Note that instead of using RFB as the input resistor, it is also
possible to use combinations of the other application resistors,
R A, RD and Re. For instance, if RD is used instead of R FB , the
gain range for the same codes of Table II now goes from 112 to
128.
2-352 DIGITAL-TO-ANALOG CONVERTERS
Figure 76. Programmable Current Source
AD7845
Yx
+VSOURCE
Y ••
•
I,
Y..
Figure 17. Programmable Current Sink
4-20mA CURRENT LOOP
The AD7845 provides an excellent way of making Ii 4-20mA
current loop circuit. This is basically a variation of the circuits
in Figures 16 and 17 and is shown in Figure 18. The application
resistor RA (Value 4R) produces the effective 4mA offset.
Since 12
»
II>
Vx
(2.5
IL = - 156 = 4R x RFB
+
2.5
R DAC
and since ROAC
2.5
IL = ( 4'
+D x
X
)
I
DxRFB x 156
= RFB = R
1000 mA
2.5 ) x "156
+ (16 x D)]mA, where D goes from 0 to I with
Digital Code
= [4
When D = 0 (Code of all Os):
IL = 4mA
When D = 1 (Code of all Is):
IL = 20rnA
The above circuit succeeds in significandy reducing the circuit
component count. Both the on-chip output amplifier and the
application resistor RA contribute to this.
-VLOOP
Figure 18. 4-20mA Current Loop
APPLICATION HINTS
General Ground Management: AC or transient voltages between
AGND and DGND can cause noise injection into the analog
output. The simplest method of ensuring that voltages at AGND
and DGND are equal is to tie AGND and DGND together at
the AD7845. In more complex systems where the AGND and
DGND intertie is on the backplane, it is recommended that two
diodes be connected in inverse para1lel between the AD7845
AGND and DGND pins (IN914 or equivalent).
Digital Glitches: When a new digital word is written into the
DAC, it results in a change of voltage applied to some of the
DAC switch gates. This voltage change is coupled across the
switch stray capacitance and appears as an impulse on the current
output bus of the DAC. In the AD7845, impulses on this bus
are converted to a voltage by RFB and the output amplifier. The
output voltage glitch energy is specified as the area of the resulting
spike in nY-seconds. It is measured with VREP connected to
analog ground and for a zero to full scale input code transition.
Since microprocessor based systems genera1ly have noisy grounds
which couple into the power supplies, the AD7845 Voo and
V55 terminals should be decoupled to signaI ground.
Temperature Coefficients: The gain temperature coefficient of
the AD7845 has a maximum value of 5ppm/"C. This corresponds
to worst case gain shift of 2LSBs over a lOO"C temperature
range. When trim resistors RI and R2 in Figure 13 are used to
adjust full scale range, the temperature coefficient of RI and R2
must also be taken into account. The offset temperature coefficient
is 5ppm of FSRI"C maximum. This corresponds to a worst case
offset shift of 2 LSBs over a lOO"C temperature range.
The reader is referred to Analog Devices Application Note
"Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs," Publication Number E63OC-5-3/86.
DIG/TAL-TO-ANALOG CONVERTERS 2-353
MICROPROCESSOR INTERFACING
16-BIT MICROPROCESSOR SYSTEMS
Figures 19,20 and 21 show how the AD7845 interfaces to three
popular 16-bit microprocessor systems. These are the MC68000,
8086 and the TMS32010. The AD784S is treated as a memorymapped peripheral to the processors. In each case, a write instruction loads the AD7845 with the appropriate data. The
particular instructions used are as follows:
MC68000:
8086:
TMS32010:
MOVE
MOV
OUT
8-BIT MICROPROCESSOR SYSTEMS
Figure 22 shows an interface circuit for the AD784S to the
8085A 8-bit microprocessor. The software routine to load data
to the device is given in Table IV. Note that the transfer of the
12-bits of data requires two write operstions. The first of these
loads the 4 MSBs into the 7475 latch. The second write operstion
loads the 8 LSBs plus the 4 MSBs (which are held by the latch)
into the DAC.
AS- A15
8086A
A1-A23
~
ADDRESS BUS
----4
Ai
ADDRESS
DECODE
iffiCi(
R!W
iliii
AD7845
~
J
MCt8000
L
J
.....+--------1
cs
1
)
D88- 08'1
WA
DBO- DB"
I
*UNEARCIRCUITRY
WR
AD7845"
ADO- AD7
DATA BUS
DO-D'5
I>----~cs
ALE
OMITTED FOR CLARITY
080- DB7
r - - - - - - -....
"LINEAR CIRCUITRY OMITTED FORCLARITV
S
Figure 22. 8085A Interface
Figure 19. AD7845 to MC68000 Interface
2000 LOAD DAC : LXI
MVI
8086
ALE
H,#3000
A,#"MS" Load the 4 MSBsof
data into accumulator.
MOV M,A
r-------------~WR
ADO- AD'5
r-_____
D_A_TA_B_U_S_ _ _~ DBO- DB"
1..-_ _- - ' 'LINEAR CIRCUITRY OMITTED FOR CLARITY
AO-Al1
WEI--------t
DO-D'5
·UNEAR CIRCUITRY OMmEO FOA CLARITY
Figure 21. TMS32010 Interface
2-354 DIGITAL-TO-ANALOG CONVERTERS
Transfer data from
accumulator to latch.
INR
L
Increment H,L pair to
AD7845 address.
MVI
A,#"LS"
Load the 8 LSBs of
data into accumulator.
MOV M,A
Transfer data from
accumulator to DAC.
RET
End of routine.
Figure 20. AD7845 to 8086 Interface
TMS32010
The H,L register pair
are loaded with latch
address 3000.
Table III. Subroutine Listing for Figure 22
AD7845
Figures 23 and 24 are the interface circuits for the Z80 and
MC6809 microprocessors. Again, these use the same basic format
as the 8085A interface.
AD - A1S
McnH
ADDRESS BUS
r----------,
r-------------~
r-------.
1>--------1 cs
RiWr----<:l
Q
AD784S*
DIGITAL FEEDTHROUGH
In the preceding interface configurations, most digital inputs to
the AD7845 are directly connected to the microprocessor bus.
Even when the device is not selected, these inputs will be constantly
changing. The high frequency logic activity on the bus can feed
through the DAC package capacitance to show up as noise on
the analog output. To minimize this digital feedthrough isolate
the DAC from the noise source. Figure 25 shows an interface
circuit which uses this technique. All data inputs are latched
•
from the busy by the CS signal. One may also use other means,
such as peripheral interface devices, to reduce the digital
feedthrough.
AO- A'S
I-------..J
DBB - DB11
MICROPROCESSOR
SYSTEM
00- 07
DATA BUS
t-------.
.----------..J
DBD - DB7
AD784S*
WR .....-----~
00- 015
-LINEAR CIRCUITRY OMmED FOR CLARITY
080- DB1'
·LlNEAR CIRCUITRY OMITTED FOR CLARITY
Figure 23. AD7845 to Z80 Interface
Figure 25. AD7845 Interface Circuit Using Latches to
Minimize Digital Feedthrough
AD - A1S
ADDRESS
BUS
.-_ _ _ _ _J
\>---------Ics
lao
AD784S*
WR
HH------------------I
088- DB11
DO- 07
080- DB7
·LlNEAR CIRCUITRY OMITTED FOR CLARITY
Figure 24. MC6809 Interface
DIGITAL-TO-ANALOG CONVERTERS 2-355
2-356 DIGITAL-TO-ANALOG CONVERTERS
11IIIIIIII ANALOG
WDEVICES
FEATURES
16-Bit Monotonicity over Temperature
±2LSBs Integral Linearity Error
Microprocessor Compatible with Readback Capability
Unipolar or Bipolar Output
Multiplying Capability
Low Power (100mW typical)
GENERAL DESCRIPTION
The AD7846 is a 16-bit DAC constructed with Analog Devices'
LC2MOS process. It has VREF + and VREF - reference inputs
and an on-chip output amplifier. These can be configured to
give a unipolar output range (0 to +5V, 0 to + lOY) or liipolar
output ranges (±5V, ±IOV).
The DAC uses a segmented architecture. The 4MSBs in the
DAC latch select one of the segments in a 16-resistor string.
Both taps of the segment are buffered by amplifiers and fed to a
12-bit DAC, which provides a further 12 bits of resolution. This
architecture ensures 16-bit monotonicity. Excellent integral linearity results from tight matching between the input offset voltages of the two buffer amplifiers.
LC 2MOS
16-Bit Voltage Output OAC
A07846 I
AD7846 FUNCTIONAL BLOCK DIAGRAM
•
PRODUCT HIGHLIGHTS
I. 16-Bit Monotonicity
The guaranteed 16-bit monotonicity over temperature makes
the AD7846 ideal for closed-loop applications.
2. Readback
The ability to read back the DAC register contents minimizes
software routines when the AD7846 is used in ATE systems.
3. Power Dissipation
Power dissipation of 100mW makes the AD7846 the lowest
power, high accuracy DAC on the market.
In addition to the excellent accuracy specifications, the AD7846
also offers a comprehensive microprocessor inte,oface. There are
16 data I/O pins, plus control lines (CS, RIW, LDAC and
CLR). RIW and CS allow writing to and reading from the I/O
latch. This is the readback function which is useful in ATE applications. LDAC allows simultaneous updating of DACs in a
multi-DAC system and the CLR line will reset the contents the
DAC latch to 00 ... 000 or 10 ... 000 depending on the state
of RIW. This means that the DAC output can be reset to OV in
both the unipolar and bipolar configurations.
The AD7846 is available in 28-pin plastic, ceramic and LCCC
packages.
DIGITAL-TO-ANALOG CONVERTERS 2-357
(Yuu= +14.25V to +15.75Y. Vss= -14.25V to -15.75V. Vee = +4.75V to +5.25V. Vuur loaded
REF += +5V. RIM connected to DV. All specifications Tmm to T.... unless
SPECIFICATIONS1 ::':~'s:!o:'f to OY. V
Parameter
J, AVersions
K, B Venions
S Version'
Units
RESOLUTION
16
16
16
Bits
±16
±16
±1
±16
±16
±16
±16
±2
±2
±4
±8
±O.5
±8
±16
±8
±16
±2
±2
±16
±16
±1
±16
±24
±16
±24
±2
±2
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
ppm FSRrC typ
ppm FSRrC typ
±8
±8
±1
±8
±12
±8
±12
±8
±12
±2
±2
±2
±2
±4
±O.5
±4
±8
±4
±8
±4
±8
±2
±2
±2
±8
±8
±1
±8
±16
±8
±16
±8
±16
±2
±2
±2
LSB max
LSBmax
LSB max
LSBmax
LSB max
LSBmax
LSBmax
LSB max
LSBmax
ppm FSRrC typ
ppm FSRI'C typ
ppm FSRI'C typ
20
40
Vss +6 to
Voo -6
Vss +6 to
Voo -6
20
40
Vss +6 to
Voo -6
Vss +6 to
Voo -6
20
40
Vss +6 to
Voo -6
Vss +6 to
Voo -6
kOmin
kOmax
Volts
Vss +4 to
Voo -3
2
1000
0.3
±25
Vss +4 to
Voo -3
2
1000
0.3
±25
Vss +4 to
Voo -3
3
1000
0.3
±25
V max
kOmin
pFmax
Otyp
mAtyp
DIGITAL INPUTS
VIH (Input High Voltage)
VIL (Input Low Voltage)
lIN (Input Current)
CIN (Input Capacitance)'
2.4
0.8
±1O
10
2.4
0.8
±10
10
2.4
0.8
±IO
10
V min
V max
jLA max
pFmax
DIGITAL OUTPUTS
VOL (Output Low Voltage)
VOH (Output High Voltage)
Floating State Leakage Current
Floating State Output Capacitance'
0.4
4.0
±10
10
0.4
4.0
±10
10
0.4
4.0
±10
10
Volts max
Volts min
..A max
pFmax
+ 11.41+ 15.75
-11.4/-15.75
+4.75/+5.25
5
5
1
1.5
100
+11.41+15:75
-11.4/-15.75
+4.75/+5.25
5
5
1
1.5
100
+ 11.4/+ 15.75
-11.4/-15.75
+4.75/+5.25
5
5
1
2
100
VminIVmax
VminlVmax
VminlVmax
mAmax
mAmax
mAmax
LSBNmax
mWtyp
UNIPOLAR OUTPUT
Relative Accuracy @ 250C
T ... to Tmax
Differential Nonlinearity Error
Gain Error @ 250C
Tmin to Tmax
Offset Error @ 250C
Tmin toTI1lIIX
Gain TC'
Offset TC'
BIPOLAR OUTPUT
Relative Accuracy @ 25"C
T min to Tmax
Differential Nonlinearity Error
Gain Error @ 25'C
T min to Tmax
Offset Error @ 25'C
Tmin to Tmax
Bipolar Zero Error @ 250C
Tmii'l
to
Tmax
Gain TC'
Offset TC'
Bipolar Zero TC'
REFERENCE INPUT
Input Resistance
VRBF + Range
VRBF - Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
Resistive Load
Capacitive Load
Output Resistance
Short Circuit Current
POWER REQUIREMENTS'
Voo
Vss
Vee
100
Iss
Icc
Power Supply Sensitivity'
Power Dissipation
NOTES
'Temperature Ranges as follows: ], K versions; 0 to +70"C
A, B versions; -25"C to +85"C
S version; - 55"C to + 12S"C
2Minimum load for S version is 3kO.
2-358 DIGITAL-TO-ANALOG CONVERTERS
Test Conditions/Comments
VRBF_=OV, VOUT=OVto +lOV
lLSB=153 ..V
All Grades Guaranteed Monotonic
VOUT Load = lOMO
VRBF- =-5V, VOUT= -lOV to +lOV
lLSB=305 ..V
All Grades Guaranteed Monotonic
VOUT Load = IOMO
VOUT Load = lOMO
Resistance from VRBF - to VRBF +
Typically 30kO
Volts
ToOV
ToOV
To OV or Any Power Supply
ISINK = 1.6mA
ISOURCE = 400..A
DBO-DBI5=0 to Vee
VOUT Unloaded
VOUT Unloaded
VOUT Unloaded
'Sample tested to ensure compliance.
4AD7846 is functional with power supplies of ± 12V. See Typical Performance Curves.
'Sensitivity of Gain Error, Offset Error and Bipolar Zero Error to VDD , Vss variations.
Specifications subject to change without notice.
AD7846
AC PERFORMANCE CHARACTERISTICS The~e characteristics are included for design guidance only and are not
sublect to test. (VREF+ = +5V, Voo = + 14.25V to + 15.75V, Vss =
-14.25V to -15.75V, Vee = +4.75V to +5.25V, RIM connected to
Parameter
Output Settling Time
Digital-to-Analog Glitch
Impulse
AC Feedthrough
Digital Feedthrough
Output Noise Voltage
Density (1kHz-100kHz)
T A=
25°C
7
9
400
T A=
T min to Tmax
7
9
400
Units
ILS max
ILS max
nY-sees typ
0.5
0.5
mV pk-pk typ
10
50
10
50
nY-sees typ
nVly'Hz typ
av.)
Test Conditions/Comments
To 0.006% FSR. VOUT loaded. VREF - =OV.
To 0.003% FSR. VOUT loaded. VREF - = -5V.
DAC alternately loaded with 10 ... 0000 and 01 ... 1111.
VOUT unloaded.
VREF - =OV, VREF + = IV rms, 10kHz sine wave.
DAC loaded with all Os.
DAC alternately loaded with allis and aliOs .. CS High.
Measured at VOUT ' DAC loaded with 0111011 ... 11.
VREF + =VREF - =OV.
II
TIMING CHARACTERISTICS (Voo= + 14.25V to +15.75V, Vss= -14.25V to -15.75V, Vee = +4.75V to +5.25V.)
Parameter
t,
tz
t,
t4
t,
t6
t,
t.
t,
tlO
til
t,z
Limit at
TA=O to +70°C
T A=-25°C to +85°C
40
160
40
110
0
270
10
90
20
150
0
100
280
Limit at
TA = 25°C
40
150
40
110
0
230
10
80
20
150
0
80
240
Limit at
TA = -55°C to +125°C
50
190
50
120
0
320
10
90
20
150
0
100
330
Units
ns min
ns min
nsmin
nsmin
nsmin
nsmax
ns min
nsmax
nsmin
nsmin
nsmin
nsmin
nsmin
Test Conditions/Comments
RIW to CS Setup Time
CS Pulse Width (Write Cycle)
RiW to CS Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Bus Relinquish Time
CLR Setup Time
CLR Pulse Width
CLR Hold Time
LDAC Pulse Width
CS Pulse Width (Read Cycle)
NOTES
ITiming specifications are sample tested at 25°C to ensure compliance. All input control signals are specified with tR ::::::
(10% to 90% of +5V) and timed from a voltage level of 1.6V.
21,; is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
't, is defined as the time required for an output to change 0.5V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
13ko
DBNo-~~--"",,-'()
DBN~
~:D~:
a. High Z to VOH
b. High Z to VOL
Figure 1. Load Circuits for Access Time (ts)
DATA
I
!"
I--"~
~
I r--"
I'
1-..
I
f.--.. ~
j--'''--I
'-I-I
F+',o_.. --1-..
DATA VALID
'/:::jt,
I
I DATA VALID
I
5V
~DV
I
i
{Ill.
.,. "I .. I t-.. <:j
'--J
5V
ov
:
"0--1
5V
~IIOV
1---+:'"
~c-------------------~:
DBNo-~~--"",,-'()
3kO
5 os
1-"+:"..]
_ H',
".M~ 1
Ci
tF =
T'DPF
Figure 3. AD7846 Timing Diagram
DGND "
a. VOH to High Z
b.
VOL
to High Z
Figure 2. Load Circuits for Bus Relinquish Time (t7 )
DIGITAL-TO-ANALOG CONVERTERS 2-359
ABSOLUTE MAXIMUM RATINGS'
VDD to DGND . . . . . . . . . . . . . . . . . . . . . -O.3V to +17V
V= to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Vss to DGND . . . . . . . . . . . . . . . . . . . . . . +O.3V to -17V
VREF + to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . ±ZSV
VREF - to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . ±ZSV
VOUT to DGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . ±ZSV
RIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±ZSV
Digital Input Voltage to DGND ....... -O.3V to Vee +O.3V
Digital Output Voltage to DGND ...... -O.3V to V= +0.3V
Power Dissipation (Any Package)
To +7SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOOOmW
Derates above +7SoC . . . . . . . . . . . . . . . . . . . . lOmWI"C
Operating Temperature Range
J, K Versions . . . . . . . . . . . . . . . . . . . . . . . .0 to +70°C
A, B Versions . . . . . . . • . . . . . . . . . . . . . -Z5°C to +8S oC
S Version . . . . . . . . . . . . . . . . . . . . . . . -S5°C to +IZSoC
Storage Temperature Range . . . . . . . . . . . . -6S oC to + 150°C
Lead Temperature (Soldering) . . . . . . . . . . . . . . . . . + 300°C
NOTES
lStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indio
cated in the operational sections of this specification is not implied. Expo·
sure to absolute maximum rating conditions for extended periods of time
may affect device reliability. Only one Absolute Maximum Rating may be
applied at anyone time.
2VOUT may be shorted to DGND, Voo , Vss , Vcr; provided that the power
dissipation of the package is not exceeded.
CAUTION:
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however. permanent damage may occur on unconnected "devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
TERMINOLOGY
Least Significant Bit
This is the analog weighting of 1 bit of the digital word in a
DAC. For the AD7846, lLSB=(VREF+ - VREF_)/Z16.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the end
points of the DAC transfer function. It is measured after adjusting for both endpoints (i.e. , offset and gain errors are adjusted
out) and is normally expressed in least significant bits or as a
percentage of full scale range.
Differential Nonlinearity
Differential noulinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of ± lLSB max over the operating temperature range ensures monotonicity.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all Is loaded after offset
error has been adjusted out. Gain error is adjustable to zero with
an external potentiometer.
Offset Error
This is the error present at the device output with all Os loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
2-360 DIGITAL-TO-ANALOG CONVERTERS
Bipolar Zero Error
When the AD7846 is connected for bipolar output and
10. . . 000 is loaded to the DAC, the deviation of the analog
output from the ideal midscale of OV is called the bipolar zero
error.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or
nV-secs depending upon whether the glitch is measured as a
current or a voltage.
MUltiplying Feedthrough Error
This is an ac error due to capacitive feedthrough from either of
the VREF terminals to VOUT when the DAC is loaded with all
Os.
Digital Feedtbrough
When the DAC is not selected (i.e., CS is held high), high frequency logic activity on the digital inputs in capacitively coupled
through the device to show up as noise on the VOUT pin. This
noise is digital feedthrough.
AD7846
PIN CONFIGURATIONS
DIP
LCCC
J~~RRII
4321282728
lJ
VOUT 5
25
t6Ac
24CLR
R,• •
23CS
AD7846
Vss
22 R/W
TOPYIEW
(Not to ac.IeJ
9
21 Vee
DB1510
0814 11
20 DGND
~~======:::!JI)
19 DB6
12 13 14 15 16 17 18
ii~~I!!
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
Pin
Mnemonic
Description
1-3
DB2-DBO
Data 110 pins. DBO is LSB.
21
Vee
4
VDD
Positive supply for analog circuitry.
This is + lSV nominal.
Positive supply for digital circuitry.
This is +SV nominal.
22
RiW
S
VOUT
DAC output voltage pin.
6
RIN
Input to summing resistor of DAC
output amplifier. This is used to
select output voltage ranges. See
Table I.
RiW input. This can be used to load
data to the DAC or to read back the
DAC latch contents.
23
CS
Chip select input. This selects the
device.
24
CLR
7
VREF +
VREF + input. The DAC is specified
for VREF + = +sy.
Clear input. The DAC can be
cleared to 000 . . . 000 or
100 ... 000. See Table II.
8
VREF -
VREF - input. For unipolar
operation connect VREF - to OV
and for bipolar operation connect it
to - SV. The device is specified for
both conditions.
2S
LDAC
Asynchronous load input to DAC.
26-28
DBS-DB3
Data 1/0 pins.
Output Range
Negative supply for analog circuitry.
This is -lSV nominal.
9
Vss
10-19
DB 1S-DB6
Data 1/0 pins. DBIS is MSB.
20
DGND
Ground pin for digital circuitry.
OV to +SV
OV to +lOV
+SV to -SV
+5V to -5V
+lOV to -lOY
VREF +
+SV
+SV
+SV
+SV
+5V
VREF OV
OV
-SV
OV
-SV
RIN
VOUT
OV
VOUT
+5V
OV
Table I. AD7846 Output Voltage Ranges
ORDERING INFORMATION
Temperature Range and Package Options'
Relative
Accuracy
@ +2S·C
o to +70·C
±16LSB
±4LSB
Plastic DIP (N-28) Ceramic DIP (D-28) Ceramic DIP (D-28)
AD7846JN
AD7846AD
AD7846SD/883B
AD7846KN
AD7846BD
±16LSB
-2S·C to
+8S"C
-SS·Cto
+12S"C
LCCCl (E-28A)
AD7846SEl883B
NOTES
'See Section 14 for package outline information.
2Leadless ceramic chip corrier.
DIGITAL-TO-ANALOG CONVERTERS 2-361
Typical Performance Curves
~r--
__---'mrrrnr,,~"~
Voo=+15V
Vss=-15V
vREF+ = :t5V Sine Wave
VDD =+1SV
Vss =-15V
VREf+=1V rms
V REF_ =OV
vlIlF_=ov
H+-+++H--HI-Ht-+-H1I
GAIN=+2
20~~~-H~-H~t+~+++*~~
t
II
~ '1-~-H+-I-t+H-+-++t+-HI/+rH
J
t
>,
1\
J
/
1°1-+-tt1t-+-+t1t-1r+'ftl-HHt--iH-ttt-H-H1
1\
r-
O,~~~~C,~~~-L~,~~-L~,~~-L-L~,~
.~~~-U~~UL~~~~~~
101
11f'
'If
1r
10&
FREQUENCY - Hz
FREQUENCY - Hz
Figure 4. AC Feedthrough. VREF + = 1V rms,
10kHz Sine Wave.
10'
101
Figure 6. Large Signal
Frequency Response
Figure 5. AC Feedthrough
vs. Frequency
VREF+",VREF_",OV
GAIN=1
~_K-~D_~rL.~~D_EDTw_'TffiT~TLr'~·~HH~+-++~
~
I
i ~o~~rH+-+-t+H-1-~~~~~
~ zoo HI-t-+t+-+-++++-++Ht--+--++-H
~
!iJ
~ 100
\
~~~~UU,~~~~~,~~~-U,~~~~~,~
FREQUENCY - Hz
Figure 7. Noise Spectral Density
Figure 9. Digital-to-Analog Glitch
Impulse with Internal Deglitcher
(10 . . . 000 to 011 . . . 111
Transition)
Figure 8. Digital-to-Analog Glitch
Impulse without 'Internal Deglitcher
(10 . . . 000 to 011
1.11
Transition)
Figure 12. Spectral Response of
Digitally; Constructed Sine Wave
Figure 10. Pulse Response
Figure ". Pulse Response
(Small Signal)
(Large Signal)
•.or---r--T""-""--"'T""--.,
1.0 r---,---r----r--:r--:"':-:O
T,,=+25"C
1-_-+_ _+-_-t__ ~::::~::V
GAIN=1
o.• I--~--+----t---t---;
T... = +2&0(:
VRlEF +=+5V
3··I---+--1-----'f--~Airi::v -
3.01---+--+---1--+--;
~u
,
~
•.O/--+--+--t--+----i
u
r"
~
I-~,I---I---r--r---t
is o.• I-~rt---+----t--+--;
'-....
1.01---t--+---I--+--;
O.I,~,---:,:':,---:':,.:---~,,:----:!,,:---:!,.
VooIV.. - Volts
Figure 13. Typical Linearity vs. VoolVss
2-362 DIGITAL-TO-ANALOG CONVERTERS
0 .•
1----+--+---1---+----1
0"
"
13
1.
1.
1.
Figure 14. Typical Monotonicity vs. Voo 1Vss
AD7846
CIRCUIT DESCRIPTION
Digital Section
Figure IS shows the digital control logic and on-chip data
latches in the AD7846. Table II is the associated truth table.
The D/A converter had two latches which are controlled by four
signals: CS, RIW, LDAC and CLR. The input latch is connected to the data bus (DBIS-DBO). A word is written to the
input latch by bringing CS low and RIW low. The contents of
the input latch may be read back by bringing CS low and RIW
high. This feature is called "readback" and is used in system
diagnostic and calibration routines.
CS
R!W
LDAC
CLR
Function
I
X
X
X
3-State DAC I/O Latch in
High Z State
0
0
X
X
DAC I/O Latch Loaded with
DBIS-DBO
0
I
X
X
Contents of DAC I/O Latch
Available on DBIS-DBO
X
X
0
I
Contents of DAC I/O Latch
Transferred to DAC Latch
X
0
X
0
DAC Latch Loaded with
000 ... 000
X
I
X
0
DAC Latch Loaded with
100 ... 000
R/Wo-............- _ - ,
eLR
Table II. AD7846 Control Logic Truth Table
o-+-+----.
Data is transferred from the input latch to the DAC latch with
the LDAC strobe. The equivalent analog value of the DAC
latch contents appears at the DAC output. The CLR pin resets
the DAC latch contents to 000 ... 000 or 100 ... 000, depending on the state of RIW. Writing a CLR loads 000 ... 000 and
reading a CLR loads 100 ... 000. To reset a DAC to OV in a
unipolar system the user should exercise CLR while RIW is low;
to reset to OV in a bipolar system exercise the CLR while RIW
is high.
D/A Conversion
Figure 16 shows the D/A section of the AD7846. There are
three DACs, each of which have their own buffer amplifiers.
DACI and DAC2 are 4-bit DACs. They share a 16-resistor
string but have their own analog multiplexers. The voltage reference is applied to the resistor string. DAC3 is a 12-bit voltage
mode DAC with its own output stage.
~~--------------~
OB15
OBO
Figure 15. AD7846 Input Control Logic
The 4MSBs of the 16-bit digital code drive DACI and DAC2
while the 12LSBs control DAC3. Using DACI and DAC2, the
MSBs select a pair of adjacent nodes on the resistor string and
present that voltage to the positive and negative inputs of
DAC3. This DAC interpolates between these two voltages to
produce the analog output voltage.
VAEF+o-------------.-......,
SEGMENT 16
.-_""'---0 R'N
V OUT
SEGMENT 1
V REF _
0--+----------_---'
Figure 16. AD7846 DIA Conversion
DIGITAL-TO-ANALOG CONVERTERS 2-363
To prevent non-monotonicity in the DAC due to amplifier offset
voltages, DACI and DAC2 "leap-frog" along the resistor string.
For example, when switching from Segment I to Segment 2,
DACI switches from the bottom of Segment I to the top of Segment 2 while DAC2 stays connected to the top of Segment I.
The code driving DAC3 is automatically complemented to compensate for the inversion of its inputs. This means that any linearity effects due to amplifier offset voltages remain unchanged
when switching from one segment to the next and 16-bit monotonicity is ensured if DAC3 is monotonic. So, 12-bit resistor
matching in DAC3 guarantees overalll6-bit monotonicity. This
is much more acheivable than the 16-bit matching which a conventional R-2R structure would have needed.
UNIPOLAR BINARY OPERATION
Figure 18 shows the AD7846 in the unipolar binary circuit configuration. The DAC is driven by the AD586, +5V reference.
Since RIN is tied to OV, the output amplifier has a gain of 2 and
the output range is 0 t6 + 10V. If a 0 to +5V range is required,
RIN should be tied to VOUT ' configuring the output stage for a
gain of 1. Table III gives the code table for the circuit of Figure
18.
+15V
+5V
Output Stage
The output stage of the AD7846 is shown in Figure 17. It is
capable of driving a 2kOllooopF load. It also has a resistor
feedback network which allows the user to configure it for gains
of one or two. Table I shows the different output ranges that are
possible.
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately I",s
after the leading edge of LDAC. This short state keeps the
DAC output at its previous voltage while the AD7846 is internally changing to its new value. So, any glitches that occur in
the transition are not seen at the output. In systems where the
'LDAC is tied permanently low, the deglitching will not be in
operation. Figures 8 and 9 show the outputs of the AD7846
with and without the deglitcher.
• AoomoNAL PINS
OMITTED FOR CLARITY
BinarY Number
in DAC Latch
MSB
LSB
llli 1111 1111 llli
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
R'N
-15V
Figure 18. Unipolar Binary Operation
Analog Output
(VOUT)
+ 10 (65535/65536) V
+ 10 (32768/65536) V
+ 10 (1165536) V
ov
NOTE
10k
10k
ILSB= IOV/2'·= IOV/6SS36= IS2f.LV.
Table III. Code Table for Figure 18
DAC3
Figure 17. AD7846 Output Stage
2-364 DIGITAL-TO-ANALOG CONVERTERS
Offset and gain may be adjusted in Figure 18 as follows: To adjust offset, disconnect the VREF - input from OV, load the DAC
with aliOs and adjust the VREF - voltage until VOUT=OV. For
gain adjustment, the AD7846 should be loaded with all Is and
RI adjusted until VOUT= 10(65535)/(65536)=9.999847V. If a
simple resistor divider is used to vary the VREF - voltage, it is
important that the temperature coefficients of these rc;sistors
match that of the DAC input resistance (- 300ppmfC). Otherwise, extra offset errors will be introduced over temperature.
Many circuits will not require these offset and gain adjustments.
In these circuits, RI, can be omitted. Pin 5 of the AD586 may
be left open circuit and Pin 8 (VREF - ) of the AD7846 tied to
OV.
AD7846
+15V
+15V
+5V
R1
.:I9k
II
R2
100k
Figure 19. Bipolar ± 10V Operation
BIPOLAR OPERATION
Figure 19 shows the AD7846 set up for ± IOV bipolar operation.
The AD588 provides precision ±5V tracking outputs which are
fed to the VREF + and VREF - inputs of the AD7846. The code
table for Figure 19 is shown in Table IV.
Analog Output
(VOUT)
Binary Number
in DAC Latch
MSB
1111 1111
1000 0000
1000 0000
0111 1111
0000 0000
1111
0000
0000
1111
0000
need the output voltage to be a whole number of millivolts (i.e.
ImV, 2mV, etc.). If the AD689 (8.192V reference) is used with
the AD7846 as in Figure 20, then the LSB size is 125f1V. This
makes it possible to program whole millivolt values at the output. Table V shows the code table for Figure 20.
LSB
1111
000 I
0000
1111
0000
+15V
+5V
+ 10 (32767/32768) V
+ 10 (1132768) V
OV
-10 (1132768) V
-10 (32768/32768) V
NOTE
lLSB = JOVl2" = IOVl32768 = 305 ....V.
Table IV. Offset Binary Code Table for Figure 19
"ADDITIONAL PINS
OMITTED FOR CLARITY
Full scale and bipolar zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588 while R3 adjusts the +5V and -5V outputs together
with respect to ground.
For bipolar zero adjustment on the AD7846, load the DAC with
100 ... 000 and adjust R3 until VOUT=OV. Full scale is adjusted by loading the DAC with all Is and adjusting R2 until
VOUT = 9.999694V.
When bipolar zero and full scale adjustment are not needed, R2
and R3 can be omitted, Pin 12 on the AD588 should be connected to Pin 11 and Pin 5 should be left floating. If a user
wants a ±5V output range, there are two choices. By tying Pin
6 (R1N ) of the AD7846 to VOUT (Pin 5), the output stage gain is
reduced to unity and the output range is ± 5V. If only a positive
+ 5V reference is available, bipolar ± 5V operation is' still possible. Tie VREF - to OV and connect RIN to VREF +. This will also
give a ±5V output range. However, the linearity, gain, and offset error specifications will be the same as the unipolar 0 to
+5V range.
Other Output Voltage Ranges
In some cases, users may require output voltage ranges other
than those already mentioned. One example is systems which
-15V
Figure 20. Unipolar Output with AD689
Analog Output
(VOUT)
Binary Number
in DACLatch
MSB
LSB
1111 1111 1111 1111
1000
0000
0000
0000
0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000
1000
0100
0010
000 I
8.192V
8.192V
8.192V
8.192V
8.192V
8.192V
(65535/65536) = 8.1919V
(32768/65536) = 4.096V
(8/65536) = O.ooIV
(4/65536) = 0.0005V
(2/65536) = 0.00025V
(1165536) = O.ooo125V
NOTE
lLSB=8.192V12'6= 125 ....V.
Table V. Code Table for Figure 20
Multiplying Operation
The AD7846 is a full multiplying DAC. To get four-quadrant
multiplication, tie VREF - to OV, apply the ac input to VREF +
and tie RIN tOVREF +. Figure 6 shows the Large Signal Frequency Response when the DAC is used in this fashion.
DIGITAL-TO-ANALOG CONVERTERS 2-365
DC PARAMETRICS
I
III·BIT DATA BUS
Figure 21. Digital Test System with 16-Bit Performance
TEST APPLICATION
Figure 21 shows the AD7846 in an Automatic Test Equipment
application. The readback feature of the AD7846 is very useful
in these systems. It allows the designer to eliminate phantom
memory used for storing DAC contents and increases system
reliability since the phantom memory is now effectively on chip
with the DAC. The readback feature is used in the following
manner to control a data transfer. First, write the desired 16-bit
word to the DAC input latch using the CS and RJW inputs.
Verify that correct data has been received by reading back the
latch contents. Now, the data transfer can be completed by
bringing the asynchronous LDAC control line low. The analog
equivalent of the digital word now appears at the DAC output.
In Figure 21, each pin on the Device Under Test can be an input or output. The AD345 is the pin driver for the digital inputs, and the AD9687 is the receiver for the digital outputs.
The digital control circuitry determines the signal timing and
format.
DACs 1 and 2 set the pin driver voltage levels (VH and Vd,
and DACs 3 and 4 set the receiver voltage levels. The pin drivers used in ATE systems normally have a nonlinearity between
input and output. The 16-bit resolution of the AD7846 aHows
compensation for these input/output nonlinearities. The dc parametrics shown in Figure 21 measure the voltage at the device
pin and feed this back to the system processor. The pin voltage
can thus be fme-tuned by incrementing or decrementing DACs
1 and 2 under system processor control.-
sine wave (usually 2.skHz, 2V pk-pk). The outputs of the secondary coil are in anti-phase and their relative amplitudes depend on the position of the core in the LVDT. The AD7846
output interpolates between these two inputs in response to the
DAC input code. The AD630 is set up so that it rectifies the
DAC output signal. Thus, if the output of the DAC is in phase
with the VREF + input, the inverting input to the comparator
will be positive, and if it is in phase with VREF.' the output will
be negative. By turning on each bit of the DAC in succession
starting with the MSB, and deciding to leave it on or turn it off
based on the comparator output, a 16-bit measurement of the
core position is obtained.
O'~
.-.
-(l-xIASin
(a)
t
• AoomONAL PINS
OMITTED FOR CLARITY
POSITION MEASUREMENT APPLICATION
Figure 22 shows the AD7846 in a position measurement application using an LVDT (Linear Variable Displacement
Transducer), an AD630 synchronous demodulator and a comparator to make a 16-bit LVDT-to-Digital Convertor. The
L VDT is excited with a fixed frequency and fixed amplitude
2-366 DIGITAL-TO-ANALOG CONVERTERS
TO
L _ _ _ _.".;,.._ _ _ _ _ _ _ _ _ PROCESSOR
PORT
Figure 22. AD7846 in Position Measurement Application
AD7846
MICROPROCESSOR INTERFACING
AD7846-8086 Interface
Figure 23 shows the 8086 16-bit processor interfacing to the
AD7846. The double buffering feature of the DAC is not
used in this circuit since LDAC is permanently tied to OV.
ADD-ADI5 (the 16-bit data bus) are connected to the DAC data
bus (DBD-DBI5). The 16-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
In this example, the DAC address is DOOOH.
1000
MOVE.W #W, DO
The desired DAC data, W,
is loaded into Data Register
O. W may be any value
between 0 and 65535
(decimal) or 0 and FFFF
(hexadecimal).
The data, W, is transferred
between DO and the DAC
register.
Control is returned to the
System Monitor using these
two instructions.
MOVE.W DO, $EOOO
MOVE.W #228, D7
TRAP
#14
A1-A23
8086
MC68000
ilS
ADo-AD15
"LINEAR CIRCUITRY
Figure 23. AD7846 to 8086 Interface Circuit
00-015
In a multiple DAC system, the double buffering of the AD7846
allows the user to simultaneously update all DACs. In Figure
24, a 16-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropriate address, CS4 (i.e., LDAC) is brought low, updating all the
DACs simultaneously.
ALE
~~
16-BIT
~H
ADDRESS.US~:DR:S L csJ
r"
WAr-r--
ADO-AD15
L
I
cs
I
+5Vo-
.q
LDAC
AD7846*
R/W
080-0815
DATA BUS
"LINEAR ctRCUITRV
OMIlTED FOR CLARITY
Figure 25. AD7846 to MC68000 Interface
DIGITAL FEEDTHROUGH
In the preceding interface configurations, most digital inputs to
the AD7846 are directly connected to the microprocessor bus.
Even when the device is not selected, these inputs will be constantly changing. The high frequency logic activity on the bus
AD7846*
A1·A15
ADDRESS BUS
LDAC
"V-.J
...J
j
My
cs
+5V
-
t--___....D,;.;AT;.;,A;.:.c;,US,;;...-,
CLR
,...,..,..,-r--;
t-o
MtcRO·
PROCESSOR
CLR
080-0815
LDAC
L;=cs~
RW
R/W
AD7846*
AD7846*
H---ILiiAC
t-t+--..jR/W
+5V
CLR
t-o
,...,..,..,_ _- ; DIIt).O.'5
L~cs
'------I RM
•
.US
A
BUS
00-015
2 x
74LS245
"LINEAR CIRCUITRY
OMITTED FOR CLARITY
AD7846*
'--_ _ _ _ _-1 0Il0-0.,.
D8().DB15
Figure 26. AD7846 Interface Circuit Using Latches to Minimize Digital Feedthrough
LDAC
*UNEAR ClRCUrTRV
OMITTED FOR CLARITY
CLR
DECODE
DEN r - -
-RD 'r - - --
ADDRESS
DECODE
RW
OMITTED FOR CLARITY
8086
H
.~
DTACK
t--_____D_AT_A_._US_ _ _ _ _--t DSO-DB15
J
ADDRESS BUS
~
+5V
CLii-o
Figure 24. AD7846 to 8086 Interface: Multiple DAC System
AD7846 to MC68000 Interface
Interfacing between the AD7846 and MC68000 is accomplished
using the circuit of Figure 25. The following routine writes data
to the DAC latches and then outputs the data via the DAC
latch.
noise on the analog output. To minimize this Digital Feedthrough isolate the DAC from the noise source. Figure 26
shows an interface circuit which isolates the DAC from the bus.
Note that to make use of the AD7846 readback feature using
the isolation technique of Figure 26, the latch needs to be
bidirectional.
DIGITAL-TO-ANALOG CONVERTERS 2-367
APPLICATION HINTS
Noise
In high resolution systems, noise is often the limiting factor.
With a 10 volt span, a 16-bit LSB is IS2",V (-%dB). Thus, the
noise floor must stay below -96dB in the frequency range of
interest. Figure 7 shows the noise spectral density for the
AD7846.·
Grounding
As well as noise, the other prime consideration in high resolution DAC systems is grounding. With an LSB size of IS2",V
and a load current of SmA, lLSB of error can be introduced by
series resistance of only 0.030.
Figure 27 below shows recommended grounding for the
AD7846 in a typical application.
Rl to RS represent lead and track resistances on the printed circuit board. Rl is the resistance between the Analog Power Supply ground and the Signal Ground. Since current flowing in Rl
is very low (bias current of ADS88 sense amplifier), the effect of
RUs negligible. R2 and R3 represent track resistance between
the ADS88 outputs and the AD7846 reference inputs. Because
of the Force and Sense outputs on the ADS88, these resistances
will also have a negligible effect on accuraCy.
R4 is the resistance between the DAC output and the load. If
RL is constant, then R4 will introduce a gain error only which
can be trimmed out in the calibration cycle. RS is the resistance
between the load and the analog common. If the output voltage
is sensed across the load, RS will introduce a further gain error
which can be trimmed out. If, on the other hand, the output
voltage is sensed at the analog supply common, RS appears as
part of the load and therefore introduces no errors.
Printed Circuit Board Layout
Figure 28 shows the AD7846 in a typical application with the
ADS88 reference, producing an output analog voltage in the
± 10 volts range. Full scale and bipolar zero adjustment are provided by potentiometers R2 and R3. Latches (2 x 74LS24S) isolate the DAC digital inputs from the active microprocessor bus
and minimize digital feedthrough.
The printed circuit board layout for Figure 28 is shown in Figures 29 and 30. Figure 29 is the component side layout while
Figure 30 is the solder side layout. The component overlay is
shown in Figure 31.
In the layout, the general grounding guidelines given in Figure
27 are .followed. The ADS88 and AD7846 are as close as possible, and the decoupling capacitors for these are also kept as
close to the device pins as possible.
*ADDtnONAL PINS
OMITTED FOR CLARITY
Figure 27. AD7846 Grounding
+15V
J1
+.v
C31/A3l
C7
~ •. 1~F
2.
18
,.
,.,.,.
17
12
COlA<
C5/A5
C6/A6
e7/A7
e8/AS
C9/A9
C10/A10
e1,/A"
,.,.
17
""12
Figure 28. Schematic for AD7846 Board
2-368 DIGITAL-TO-ANALOG CONVERTERS
e12/A12
e13/A'3
C14/A14
C15/A15
e16/A16
e17/A17
e18/A1B
C19/A19
aO/A20
e2l/A21
C22/A22
C23/A23
C32/A32
AD7846
•••••••••••••
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•••••••••••••
•••••••••••••
II
Figure 29. PCB Component Side Layout for Figure 28
5.9" (150mm)
-----------.-t
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•••••••••••••
•••••••••••••
•••••••••••••
Figure 30. PCB Solder Side Layout for Figure 28
DIGITAL-TO-ANALOG CONVERTERS 2-369
JI
C9
SKT I
C14+
CI3
CIO+
D
CSC6 t
rn
c7lcal+
~
IC3
ICI
CI
C2+
CI21
+
IBI
+
1C31C4
~
IC2
DD
RO
C12+
CII
~
ICO
R3
Figure 31. Component Overlay for Circuit of Figure 28
2-370 DIGITAL-TO-ANALOG CONVERTERS
J2
r-IIANALOG
WDEVICES
LC 2MOS
Complete 12-811 DAC with DSP Interface
AD7848 I
FEATURES
Complete DAC with DSP Interface, Comprising:
- 12-Bit Voltage Mode DAC
- 3 V Zener Reference
- Output Buffer Amplifier with 4 I1s Settling Time
- 8-Word FIFO and Interface Logic
72 dB Signal-to-Noise Ratio
Interfaces to High Speed DSP Processors,
e.g., ADSP-2100, TMS32010, TMS32020
42 ns min WR Pulse Width
Low Power - 95 mW max
AD7848 FUNCTIONAL BLOCK DIAGRAM
REF OUT
RfF IN
APPLICATIONS
Digital Signal Processing
Speech Synthesis
High Speed Modems
DSP Servo Control When Used with AD7878
GENERAL DESCRIPTION
The AD7848 is a fast, complete, 12-bit, voltage output D/A
converter with a versatile DSP interface consisting of an 8-word,
first-in, first-out (FIFO) memory and associated control logic.
The FIFO memory aIlows up to eight samples to be loaded
to the AD7848 at full microprocessor speed. The sam
then loaded to the DAC register under con
nous LDAC signal. A fast data se
direct interfacing to DSP processo
microprocessors.
An on-chip status/control register allows
effective length of the FIFO and contains F
full and FIFO word count information.
The analog output from the AD7848 provides a bipolar ou
range of ±3 V. Full power output signals up to 20 kHz can e
created, and the AD7848 is fully specified for dynamic performance parameters such as signal-to-noise mtio and harmonic
distortion.
The AD7848 is fabricated in Linear Compatible CMOS
(LC2 MOS), an advanced, mixed technology, process that combines precision bipolar circuits with low power CMOS logic.
The part is available in a 28-pin plastic and hermetic dual-in-line
package (DIP) and in a 28-terminal plastic leaded chip carrier
(pLCC).
DGND
AD1848
he complete function for creating ac
acy. The part features an on-chip refertput buffer amplifier and 12-bit D/A converter.
na1 feature of an 8-word FIFO reduces the high
rheads associated with servicing peripherals in
ynamic Specifications for DSP Users
The AD7848 is fully specified and tested for ac parameters,
including signal-to-noise ratio and harmonic distortion. Key
digital timing parameters are also tested and specified over
the full opemting temperature range.
3. Fast Microprocessor Interface
Data setup times of 21 ns and write pulse widths of 42 ns
make the AD7848 compatible with all modern 16-bit microprocessors and digital signal processors.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-371
SPECIFICATIONS
=
=
=
=
=
(VDD 5 V± 5%, Vss
-5 V ±5%, AGND DGND = OV, REF IN
+3 V, RL 2 kG,
CL = 100 pF, fell( = 8 MHz. All Specifications Tml " to Tma. unless otherwise noted.)
I,A
S
Parameter
Versionsl
K,L,.B
Versions
Version
Units
Test ConditionS/Comments
DYNAMIC PERFORMANCE2
Signal to Noise Ratio' (SNR) @ ... 25'C
T min to Tmax
Total Harmonic Distortion (THD)
70
70
72
71
70
70
-so
-so
-so
dB min
dB min
dB max
-Sl
-Sl
-Sl
dB max
V OUT =1 kHz Sine Wave, fSAMPLE = 100 kHz
Typically 71.5 dB at + 25'C for 0 pt:cifica!ions for AD9700SE same a5 AD9700SD.
3Settling to GS percentage includes FS and MSB transitions.
Inherent 3ns register delay (50% points) is not included.
4Minimum update rate limited by full-scale settling time for eight bits.
Unit can be updated to 12SMHz.
sGJitch can be reduced with glitch adjustment.
6See Figure 2 for operation with TIL logic.
7FS current'" GS current + video functions'" 30mA.
sLSB value of 2.5mV used for calibration. This causes Gray Scale output to
to be 637.5mV rather than 643mV shown in idealized composite waveform
elsewhere in this data sheet; both values are well within the output and EIA
Siandard RS-170 tolerances. lOUT"" (1.26IRsliT) x 4 when RShl" '" 300n.
9Effect on analog output of logic "0" at Reference White input depends on Signal
,.
PIN
17
18
1.
20
21
22
23
2.
25
2.
27
28
V..
NOTE: CONNECT PINS 1, 2, 3, AND 15 TOGETHER AND TO
GROUND AS CLOSE TO CASE AS POSSIBLE.
lo~~o~~~r!~~h~::~s;::eS~:~,I:!~
"Co=m="",=ire"B"'I,"'nk='n=g outputs shown add to
Gray Scale analog output at Pin 13.
11Composite Sync or Composite Blanking control signals reset input registers.
Composite Sync or Composite Blanking should not be operated simultaneously
with Reference White.
IlMaximums shown are at temperature extremes.
13Maximum junction temperature = + 150°C.
14Calculated using MIL HNBK-217; Ground Fixed; + 25 C Ambient.
"See Sccti... n 14 ror package outline information.
*Specifications same as AD9700BDIBW.
Specifications subject to change without notice.
Q
-71mV
+10
-714mV
o
-785mV
-
------lO%BRIGHTLEVEL
- - - - - - - REFERENCE WHITE
LEVEL (V ...... I
REFERENCE BLACK
LEVEL (V... I
- - COMPOSITE BLANKING
LEVEL(Vbl
-40 -1071mY
l00IREUNITS", 714mV
Idealized Composite Output Waveform
DIGITAL-TO-ANALOG CONVERTERS 2-381
•
DIGITAL INPUTS VS. ANALOG OUTPUT
Ref.
White
10%
Bit
Comp.
Bk
1
Bit
2
Bit
3
Bit
Bit
6
Bit
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
4
NOTES
ISet\lp (Pin 21) grounded (0 IRE units).
2Setup(Pin21)opcn(7.5IREumts).
Bit
5
7
8
IIri&bt
IIlaakiDa
Comp.
Sync
I
I
AnolCltl
Output(mV)
0
I
I
I
I
I
I
I
I
0
0
0
0
-71
-320
-637.5
-708.5
0
-71
-637.50'
-690.75'
-708.50'
-779.50'
-922.50'
-975.75'
-993.50'
-1064.50'
-993.50'
-1046.75'
-1064.50'
-1135.50'
3Setup(Pin"21)to - 5.2Vthrough lk (10 IRE units).
4Setup(Pin21)to -S.2V(20IREunits).
Analog output values shown are based on LSB value of 2.SmV used for ease of calibration; this causes Gray Scale output to be 637.5mV rather than 643mV shown
elsewhere in this data sheet in sketch ofidealized composite output. Both values are well within the output and EIA Standard RS~ 170 tokranccs.
Table I.
USING AD9700 AS RASTER SCAN D/A
Refer to the block diagram of the AD9700 D/A converter.
The digital input bits represent the Gray Scale value of the 256
(2 8) discrete levels between Reference Black and Reference
White in a composite video signal, and are applied to Pins 3
through 10.
The output analog signal (at Pin 13) will be a function of these
digital inputs. The output will also be affected by the ECL
levels at the control inputs of 10% Bright, Reference White,
Composite Sync, and Composite Blanking; and the level of the
control signal (expressed in terms of IRE units) at the Setup
input.
The total effect of these combined signals can be illustrated in a
truth table format if arbitrary values are assigned for Gray scale
inputs and various combinations of control inputs are selected.
When Composite Blanking is operated, the analog output will
go to its full-scale value of -637.5mV plus some additional
amount, as determined by the voltage at setup. The -53.25mV
example used in the specifications section of the data sheet is
based on the setup input floating, which is equivalent to 7.5
IRE units. (For this example, the analog output would be
690.75mV.)
The internal voltage reference shown in the block diagram is a
bandgap type. Including this reference within the converter
eliminates the need for external circuits, making it markedly
easier to design the AD9700 into various applications. The
internal precision reference also provides superior power supply
rejection and gain tempco.
Details on the connections for using the AD9700 in composite
video applications are shown in Fignre I.
Refer to Table I.
As the foornote to this figure points out, the full-scale (- 637.5mV)
output of the AD9700 is different from the - 643mV output of
the idealized composite waveform shown elsewhere in this data
sheet. The reason for this discrepancy is Analog Devices' use of
2.5mV for the value of the LSB; that choice of LSB weighting
eases calibration of the converter. The disparity does not cause
any problems in using the device, since both values are well
within the tolerances of the output and the RS-170 standard.
Referring again to the block diagram, the Strobe input applied
to the AD9700 clocks the input registers when the strobe signal
makes the transition from a logic "0" to a logic "I". The purpose
of the registers is to remove time skew from the digital input
bits and minimize pertubations or "glitches" in the analog output
signal.
The signal applied to the Reference White input sets the input
registers, thereby overriding the video input word. When this
occurs, the analog output of the AD9700 goes to OVor to -7ImV,
depending upon whether or not the 10% Bright signal is also
operated.
REFERENCE WRiTE l'
'WsJJ'
BlT2
DIGITAL
{
INPUTS
4
BlT3 5
BIT4
6
BITS'
BlT&
8
BIT, •
~~
COM~ITE
10
"
(z)-....- - -•.zv
Ran 4(1~~~)
=0
A logic "0" applied to either the Composite Sync or Composite
Blanking input will reset the input registers to 00000000. The
analog output at Pin 13 will be -922.5mV (-637.5mV plus
- 285mV) if the Composite Sync input is operated; this is not
affected by the value of IRE units at the setup input.
2-382 DIGITAL-TO-ANALOG CONVERTERS
VOUT "" 4
(~) RLOADo
-RLOAD "" RLAODDER
II RTEAMlwmON
Figure 1. AD9700 DIA Connections
AD9700
The value of RSET can be established by using the first of the
two equations which are part of the connection illustration; in
the formula, the 1.26 volts is the reference voltage. When that
voltage is divided by the desired Gray Scale current, the value
which results is approximately one-fourth the resistance of
R sET .
The resistance of RsET , in turn, can be used in the calculation
of analog output voltage when the A09700 is operating as a
raster scan 01A converter. The full-scale current of the device is
the Gray Scale current plus the video functions, and is specified
at 30mA total. The user needs to keep that number in mind to
assure that the A09700 is utilized correctly in circuit designs.
In some instances, the user may be driving a lighter load than
the coaxial cable shown in Figure 1 and prefers to operate with
lower power dissipation than that in high speed raster scan use.
For these situations, the value of RSET can be doubled, which
halves the output current while still maintaining a useable current
drive from the converter. Power dissipation would be reduced
approximately 75mW; the trade-off to obtain this is a decrease
in the speed of the A09700 and a lengthening of settling time.
Ground pins 1, 12, and 22 are shown connected together and to
ground near the unit; this is the recommended procedure for
obtaining optimum performance, especially in high-speed applications. Inside the A09700, Pin 1 is register ground; Pin 12 is
analog ground; and Pin 22 is digital ground.
For some applications, in addition to by-passing the -5.2V
supply with O.OI.,.F as shown, it may be desirable to by-pass it
also with a tantalum capacitor of 3.3 - lO.,.F. Although this is
not generally necessary, it may enhance the converter's performance in some designs.
The circuit connected to Pin 21 setup is used for illustrative
purposes to demonstrate the relationships of various IRE units;
it is not intended to imply this is the preferred way to obtain
these values. At Pin 20, the circuit used for adjusting the glitch
can reduce the amount of glitch from its typical 50pV-s to a
lesser value for those applications which require it.
USING AD9700 IN TTL MODE
Most applications using the A09700 for composite video reconstruction will be in ECL systems, but there may be instances
where its high-performance characteristics need to be applied in
TTL designs.
+5V
DATA {MS'
-++......- - - - ( i )
INPUTS
-r+-----(
......- - - - - ( ,
II
UP~,~~~-----6~
STROBE
--+-..----0{,
R~.=F~K.~~.W""Hrurr.-~+_~--~
~--+1_+_._-_6y
COMPOSITE BLANKING
--+1_+_hr-_6i)
~~~±-~r+~~
CONNECT
PIN21TO
+5V
....N
1kTOOROUND
GROUND
NOTE
EXCEPT ASNOTED.ALLIN
"IF UNUSED, DATA INPUT
•• ,
RS = 2kO.
ITE. SYNC, AND
CONNECTEDTO +5V .
10%8RIQHTSHOUt.DBEOAOUNDEDORLEFTOPEN
WITH
LL·UP RESISTOR.
Figure 2. Using AD9700 in TTL Mode
USING AD9700 AS STANDARD DIA
Although designed for use in composite video applications, the
A09700 can also be utilized as a standard 01A converter with
remarkable performance. The extremely low glitch energy of the
unit makes it especially attractive, because video reconstruction
can be accomplished with exceptional spectral purity.
Refer to Figure 3.
MfB-~f------(
I
I
I
I
I
I
I
I
I
LSB -<~+-----(,
• FOR LESS THAN 8-BIT RESOLUTION.
UNUSED BITS SHOULD DE BIASED TO
LOGIC","WITH DIODETOGROUND.
A method of accomplishing this is illustrated in Figure 2.
Except as shown, all input pull-up resistors which are used are
the same value: 2kn. If some of the input bit connections are
not used because of operating with fewer than eight bits of
resolution, the unused input pins should be resistively connected
to + 5V to prevent undesirable side effects in the performance
of the converter.
This same technique of resistively connecting unused inputs to
+ 5V also applies for the Reference White, Composite Sync,
and Composite Blanking inputs. If 10% Bright is not used, Pin
19 should be either grounded or left open; no pull-up resistor
should be used.
The table which is part of Figure 2 shows the required connections
to Pin 21 for the various blanking levels when operating in the
TTL mode.
Figure 3. AD9700 as Standard DIA
When used as a standard O/A, the unused control inputs required
for video applications are connected to ground; in most cases,
this connection is made through a diode. Examples of that are
shown on Pins 16, 17, and 18, the inputs for Reference White,
Composite Sync, and Composite Blanking, respectively. The
10% Bright input (Pin 19) is left open, and setup (Pin 21) is
tied directly to ground.
If fewer than eight bits of digital input will be applied, the
unused input pins should be connected to ground via a diode
with the same technique used at Pins 16, 17, and 18. If they are
tied directly to ground, converter performance may be affected
adversely.
DIGITAL- TO-ANALOG CONVERTERS 2-383
-5.2V
cs-+t-~~
L..._ _ _
COMPOSri'ESYNC
L..._ _ _ _ _ 'COMPOSITEBLANKING
WE----====~-__1
STROBE-------------------------J
Figure 4. Using the AD9700 with Look-Up Table
USING AD9700 WITH RANDOM ACCESS MEMORY
In many applications, it may be necessary to operate the AD9700
DIA converter with look-up tables (LUT's) for raster scan display
applications. One possible way to operate with fast random
access memory (RAM) is shown in Figure 4.
Data are written into the RAM during an inactive portion of the
scan cycle. The full tables can be written during the vertical
retrace time; or small blocks of data can be written during the
horizontal retrace. Write cycle timing requirements for the
10422 RAM which is illustrated are shown in Figure S.
If the user is interested in obtaining an RGB video subsystem,
The major advantage of the configuration recommended here is
realized during the read mode of the RGB system. In the method
illustrated in Figure 4, all three OfA converter outputs are updated
simply by changing the 8-bit address. Refer to Figure 6.
the circuit which is shown would be repeated three times. The
Address Bus (A IN), Data Bus (DIN), Write enable (WE), and
Strobe lines for the three would be connected in parallel. During
write operations, the appropriate Chip Select (CS) line would be
operated to control which RAM will receive data on the Data
Bus.
This illustrates the timing relationships and the intervals for the
various operations which occur during the read cycle of the
LUT.
CHIP
SELECT
~
CHW
ADDRESS
INPUT
{
A:::xl~~
+---§-
~tX'+---~_
INPUT
DATA
Jf'--+_--4__J I'_____J
INPUT _ _
'-+----
DI:~:lr&R__t_:. . .,--____=:x___.
,
WRITE
ENABLE
STROBE
DATA
DATA TO
OUTPUT
DlA
Chlp8electPriortoWrite
Address SetupPriotto Write
Data Setup Prior to Write
twscs
twsA
'waD
tws
tw
Writ. Disable Time
WriteEnab1ePubeWidth
AddressHoldTimeAfterWrite
DataHoldTimeAfterWrite
Write Recovery Time
twHA
twHD
Chip Select Hold Time Afte,Write
tWHCS
twA
2ns(mlnl
2ns(min)
2ns(min)
Snslm.x)
&ns(mlnl
2ns(min)
2n.lmin)
9nslmax)
2nslmln)
Figure 5. LUT Write Cycle Timing Diagram
O~~T
t ••
.!
~
",.--1
\
-1J;;t:~--------~,,------------,,........
....
________
5nslmaxl
ChlpSelectAcc:essTime
AddressAccess Time
Chip Select Recovery Time
Data Setup Time
t~
10ns(mln)
2.5ns(min)
Data HoldTlme
Register Propagation Delay
tao
t ...
1.5nslmin)
5ns(maxl
D/ARiseTime
to
2ns(typ)
Snalm_x)
Figure 6. LUT Read Cycle Timing Diagram
2-384 DIGITAL-TO-ANALOG CONVERTERS
250M Hz Video
Digital-to-Analog Converter
AD9701
1IIIIIIII ANALOG
WDEVICES
I
AD9701 FUNCTIONAL BLOCK DIAGRAM
FEATURES
250MHz Update Rate
Low Glitch Impulse
Complete Composite Functions
Internal Voltage Referenee
Single -S.2V Supply
7.5 IRE
o IRE
-!o
G-----<..... I-S.2VI
SYNC
APPLICATIONS
Raster Seen Displays
Color Graphics
Automated Test Equipment
TV Video Reconstruction
~
REFERENCE WHITE
STROBE
"'"MSB'
BIT%
{
INPUTS
DIGITAL
BIT 3
BIT4
BITS
"TO
otT,
BJT81LSBI
GENERAL DESCRIPTION
The AD9701 is a high-speed, 8-bit digital-to-analog converter
with fully integrated composite video functions. High-speed
ECL input registers provide synchronous operation of data and
control functions up to 2S0MHz.
L-----====-====~r}
"'.
PIN CONFIGURATIONS
The AD9701 incorporates on-board control functions including
horizontal sync, blanking, reference white level, and a lOOA>
bright signal for highlighting. The setup level is also adjustable
from 0 IRE units to 20 IRE units, through the control pin. An
internal voltage reference allows the AD9701 to operate as a
stand-alone video reconstruction DAC.
GROUND
SETUP
NO CONNECT
10% BRIGHT
COMPOSITE BLANKING
The AD9701 is available as an industrial temperature range
device, - 2S"C to + 8S"C, and as an extended temperature range
device, - 55°C to + 12S"C. Both grades of the AD9701 are
packaged in a 22-pin ceramic DIP, with the extended temperature
device also available in a 28-pin LCC package.
COMPOSITE SYNC
REFERENCE WHITE
COMPENSATION
CURRENT SET
OUTPUT
GROUND
ORDERING INFORMATION
Device
Temperature Range
Description
Package
Options*
AD9701BQ
AD9701SE
AD9701SQ
-25'Cto + 85°e
- 55°C to + 1250C
- we to + 125'C
22-Pin DIP, Industrial Temperature
28·Pin LCC, Extended Temperature
22-Pin DIP, Extended Temperature
D-22
E-28A
D-22
*'See Section 14 for package outline information.
BIT 1 (MSB)
:: i
~ ~
CJ
~CJ
i
I
CJ
4
3
2
i
1
lJ
5
25 NO CONNECT
24
BIT2 6
BlT3
7
BIT4
8
BITS
9
(Not
1ii%BiiiGifi'
23 COMPOSITE BLANKING
AD9701
TOP VIEW
22 NO CONNECT
to Scale)
21 COMPOSITE SYNC
BIT 6 10
20 REFERENCE WHITE
BIT7 11
19 COMPENSATION
"
12 13
"
15 16 11
,.
"z "I!: ::, 't;"
~
Z "
i1 "
E
~
..
8 " "
Iii
iii
m
!
z~
"
Z
I-
I-
"
U
DIGITAL-TO-ANALOG CONVERTERS 2-385
•
SPECIFICATIONS
ABSOLUTE MAXIMUM RATlNGS 1
Supply Voltage (- Vs) . . . ; . . . . • . . • • . . • • . -7V
Digital Input Voltages (including STROBE, SYNC,
BLANKING, 10% BRIGHT, and REFERENCE
WHITE) . . . . . . . . . . . . . . . . . . .. OV to -Vs
Analog Output Current . . . . . . . . . .
.
•. 37mA
Power Dissipation (+ 25"C Free Air)2 • . . . . • • . . 780mW
Operating Temperature Range
- 25"C to + 85"C
- 55"C to + 125"C
- 65"C to + 15O"C
+ 175"C
.• +3OO"C
AD9701BQ . . • . . . . •
AD9701SQ/SE . . . . • .
Storage Temperature Range .
Junction Temperature . . . .
Lead Soldering Temperature (l0sec)
ELECTRICAL CHARACTERISTICS (SupplyVoIIages = -5.2Y;R.. = 37.50; Setup = OY,unlassolherwisestated)
Parameter
Temp
RESOLUTION
DC ACCURACY
Differential Linearity
Integral Linearity
Monotonicity
INITiAL OFFSET ERROR3
Zero-Scale Offset Error4
Zero-Scale Offset Drift Coefficient
Full-Scale Drift Coefficient
ANALOG OUTPUT
Voltage OutputS
10% Brighr6
Reference White
Blanking(Semp = oIRE)'
Sync (Semp = OIRE)8
Current OutputS
10% Bright6
Reference White
Blanking (Setup = 0 IRE)'
Sync (Setup = OIRE)8
Output Compliance Range
Output Resistance
DYNAMIC PERFORMANCE
Update Rate
Output Propagation Delay9
Output Settling Time 10
Current
Voltage
Output Slew Rate II
Output Rise Time ll
Output Fall Time II
Glitch Impulse
Min
AD9701BQ
Typ
Max
0.25
0.25
0.05
0.25
0.05
0.9
0.9
-0.9
-67.45
-698.55
-979.25
0
-71
-708.5
-993.5
Full
Full
Full
Full
Full
+ 25°C
-0.024
-1.805
-18.63
-26.11
0
-1.9
-1.996
-18.9
-19.16
-26.87
-26.5
-1.6; +0.1
800
225
250
5
+ 25°C
+ 25°C
+ 25°C 255
+25OC
+25OC
+ 25°C
8
12
300
1.7
1.7
60
SETUP CONTROL 12
Semp Level (Grounded)
Semp Level (Open)
Setup Level (Tied to - 5.2V with lkO)
Setup Level ( - 5.2V)
Full
Full
Full
Full
0
7.5
10
20
DIGITAL INPUTS
Logic" 1" Voltage
Logic "0" Voltage
Logic" 1" Current
Logic "0" Current
Input Capacitance
Data Setup Time
Data Hold Time
-1.1
Full
Full
Full
Full
+ 25°C
+ 25°C 0.1
+Z5°C 1.4
0.5
1.0
0.5
1.0
LSB
LSB
LSB
LSB
0.9
0.9
mV
mV
...vrc
...vrc
2
50
2
50
640
-74.55
-718.45
-1007.75
-0.9
-67.45
-698.55
-979.25
0
-71
-708.5
-993.5
-0.024
-1.805
-18.63
-26.11
0
-1.9
-18.9
-26.5
-1.6; +0.1
800
640
6
250
5
2.0
2.0
70
8
12
300
1.7
1.7
60
225
255
-74.55
-718.45
-1007.75
6
rna
mA
V
0
MHz
ns
V/ ...s
2.0
2.0
70
ns
ns
pV-s
IRE
IRE
IRE
IRE
-1.5
-1.5
100
15
5.5
100
15
5.5
4
mA
ns
ns
0
7.5
10
20
0.1
1.4
mV
mV
mV
mV
rna
-1.995
-19.16
-26.87
-1.1
4
Units
GUARANTEED
Full
Full
Full
Full
2-386 DIGITAL-TO-ANALOG CONVERTERS
Max
Bits
0.25
O.S
1.0
0.5
1.0
GUARANTEED
+ 25°C
Full
Full
Full
+ 25°C
+ 25°C
AD9701SQlSE
Typ
8
8
+ 25°C
Full
+ 25°C
Full
Full
Min
V
V
...A
...A
pF
ns
ns
AD9701
Parameter
Temp
POWER SUPPLY \3
Supply Current ( - 5.2V)
Min
AD9701BQ
Typ
+ 25°C
Full
+ 25°C
Full
Nominal Power Dissipation
Power Supply Rejection Ratio l4
140
Max
AD9701SQISE
Typ
Min
140
160
160
728
3
728
3
6
Max
Units
160
160
mA
rnA
mW
mVN
6
NOTES
1Absolute
maximum ratings are limiting values, to be applied individually,
and beyond which serviceability of the circuit may be impaired. Functions!
operability under any of these conditions is not necessarily implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
'Typical thennal impedance ...
22-Pin Ceramic
OJ. = 64"CIW; OJ, = 16"CIW
28-Pin Ceramic LCC
OJ. =70"CIW; OJ, =21"CIW
'SYNC, BLANKING, and REFERENCE WHITE are inactive (Lngic "I").
ISET = 1.26VIRsET'
'All bits at Ingic HIGH.
SAll values are relative to full-scale output, after being normalized
to nomins! value. Typical varistion in full-scale output from device to
device can reach ± 10%, for a fIXed RSET resistor.
"The effect of 10'% BRIGHT algebraically adds to the output waveform.
'The output level with BLANKING active (Logic "0"), is determined by
the setup controlleve!'
8In Donnal operation, the BLANKING input is activated (Logic "0") prior
to or in conjunction with the SYNC input. The effect of the SYNC
utput is relative to the setup level.
"Measured from edge of STROBE to 50% transition point of the output
signa!.
IOMeasured with full-scale change in output level, from the 10% transition
levelto within ± 0.2% of the final output value.
II Measured from 10% to 90% transition point for full-scale step output.
l'An IRE unit is 1% of the Grey Scale (GS range) with aO IRE setup level.
13Supply Voltage should remain stable within ± 5% for normal operation.
14Measuredat ±5%of - Vs.
Specifications subject to change without notice.
DIGITAL INPUTS VS. ANALOG OUTPUT
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
8
10%
Bright
White
1
1
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTES
1. Setup
2. Setup
3. Setup
4. Setup
Comp.
Ref.
Bit
2
Bit
1
Blanking
Sync
1
Analog
Output{mV)
0
-71
-320
-637.5
-708.5
0
1
1
0
0
0
0
-71
-637.501
-690.75 2
-708.503
-779.504
0
0
0
0
0
0
0
0
-922.50 1
-975.75 2
-993.503
-1064.504
0
0
0
0
0
0
0
0
-993.50 1
-1046.75 2
-1064.5W
-1135.50"
(Pin 21) grounded (0 IRE units).
(Pin 21) open (7.5 IRE units).
(Pin 21) tu - S.2V through Ik (0 IRE units).
(Pin 21) to - S.2V (20 IRE units).
DIGITAL-TO-ANALOG CONVERTERS 2-387
II
FUNCTIONAL DESCRIPTION
DESCRIPTION
PINNAME
GROUND
-Vs
BIT 1 (MSB)
BIT2-BIT7
BIT 8 (LSB)
STROBE
GROUND
SETUP
- One of three ground returns. All grounds should be connected together near the AD9701.
- Negative supply pin, nominally -S.2V.
- One of eight digital input bits. BIT 1 (MSB) is the most-significant-bit of the digital input
word.
- One of eight digital input bits.
- One of eight digital input bits. BIT 8 (LSB) is the least-significant-bit of the digital input
word.
- Data and control register strobe input. STROBE is leading edge triggered.
- One of three ground returns. All grounds should be connected together near the AD9701.
- The SETUP input determines the position of the blanking level relative to the "reference
black" level (all data bits at logic "0"). The setup level is adjustable from 0 IRE units to 20
IRE units below the reference black level (an IRE unit is 1% of the "grey scale" range).
SETUP LEVEL
CONFIGURATION (pIN 21)
oIRE Units
Ground
Open
Connection to -S.2Vthrough lkO
Connectionto -S.2V
7.SlREUnits
lOIRE Units
20 IRE Units
10% BRIGHT
-
COMPOSITE BLANKING
-
COMPOSITE SYNC
-
REFERENCE WHITE
-
COMPENSATION
-
CURRENT SET
-
OUTPUT
GROUND
-
10% BRIGHT adds an additional current to the output level, equal to roughly 10% of the
"grey scale" range. The 10% BRIGHT is active logic LOW, and operates independently of
all other inputs.
The COMPOSITE BLANKING input, active logic LOW, forces output to the blanking
level set with the SETUP input.
The COMPOSITE SYNC input, active LOW, creates a negative going horizontal synchronization pulse relative to the blanking level. Under normal operating conditions the
COMPOSITE BLANKING signal should precede and extend past the COMPOSITE SYNC
signal. See SETUP for additional information.
The REFERENCE WHITE input, active LOW, overrides the data inputs, and forces the
output to the maximum "grey scale" level.
The COMPENSATION input insures adequate gain stability for the internal reference
amplifier. Under normal operating conditions, the COMPENSATION input is decoupled
to ground through a O.l,...F capacitor.
The CURRENT SET input determines the full-scale or "grey scale" range. The effects of the
video control functions are in addition to the "grey scale" range. (1680:5 RSIIT :5 6000).
IoUTmax=4I slIT =4(1.26VIRsIIT)
Analog output.
One of three ground returns. All grounds should be connected together near the AD9701.
2-388 DIGITAL-TO-ANALOG CONVERTERS
AD9701
SYSTEM TIMING DIAGRAMS
r- P~~~D
+VIDEO PICTURE DATA--I
DIGITALINPUTS
INCLUDING
CONTROL INPUTS
REFERENCE WHITE
=t
_ _ _ __
t,
STROBE
•
SYNC LEVEL
ts
tH
t,.ww
It>wL
taT
R_CE
WlIITE
tpD
DIGITAL DATA SETUP TIME
DIGITAL DATA HOLD TIME
STROBE PULSE WIDTH HIGH
STROBE PULSE WIDTH LOW
SErrUNG TIME
MINIMUM PROPAGATION DELAY
NOTES
1. ALL INPUTS. INCLUDING THE VIDEO CONTROL
FUNCTIONS. ARE SYNCHRONIZED TO THE
10% BLANKING
STR~
2. THE 10% BRIGHT CONTROL WILL INCREASE
THE OUTPUT LEVEL BY APPROXIMATELY 10
IRE UNITS OVER THE PRESENT OUTPUT
LEVEL.
3. AN IRE UNIT IS IDEALLY 7.14mV.
DIGITAL DATA
BIT1IMSB)TO
BIT81LSBI
DIE LAYOUT AND MECHANICAL INFORMATION
REFERENCE WHITE
/
SET
BIT 1 (MSS)
BIT 5
Die Dimensions
Pad Dimensions
Metalization
Backing
Substrate Potential
Passivation
Die Attach
Bond Wire
107 x 104 x 15 (±2) mils
4x4 mils
Aluminum
None
-Vs
Oxynitride
Gold Eutectic
1.25 mil Aluminum; Ultrasonic Bonding
or 1mil Gold; Gold Ball Bonding
BIT 7
DIGITAL-TO-ANALOG CONVERTERS 2-389
APPLICATIONS INFORMATION
Raster scan video displays image data on a line by line basis,
with timing and control signals inserted between the lines. The
control signals include the horizontal synchronization pulses
which are used to align the display circuitry at the beginning of
each line. Mter the complete video image is displayed on the
monitor, the process begins again with the next image. The
vertical reset pulse(s) that initiate this timing sequence are located
between each video image.
The image data is distinguished from the timing information by
its location relative to the blanking level. The blanking reference
level is at the blackest extreme of the image data, and all timing
signals are designed to fall below the blanking level so as not to
be seen on the monitor. The actual image data is located above
the blanking level, and it may be further separated from the
timing signal by the setup level. The setup level is simply a
buffer zone between the timing and image data.
Generation of the timing signals for the AD9701 is controlled by
the COMPOSITE BLANKING and the COMPOSITE SYNC
inputs. In normal operation the output level of the AD9701 is
forced to the blanking level (black) with the COMPOSITE
BLANKING control so that when the synchronization occurs,
it will not interfere (be seen) with the monitor image. The
COMPOSITE SYNC control forces the output level below the
blanking level, generating the synchronization pulse.
The "grey scale" is the image intensity range, located above the
blanking level by the amount of the setup lev~l. The. setuP. level
is "reference black," the darkest displayable Picture IDtenSity.
The top of the "grey scale" is "reference white," or the brightest
picture intensity. As an 8-bit device, the AD9701 divides the
"grey scale" into 256 individual levels.
Normal raster scan waveforms divide the region between the
blanking level and reference white into 100 IRE units (International
Radio Engineers). The setup level can range from 0 to 20 IRE
units but typically is around lOIRE units, and the synchronization
pulse'level typically falls 40 IRE units below the blanking level.
For the AD9701, the reference white level is 10 IRE units below
the full-scale output range (OmAour).
In terms of priority, the REFERENCE WHITE control overrides the data inputs, but both COMPOSITE SYNC and
COMPOSITE BLANKING override the data inputs and the
REFERENCE WHITE control. A fourth control is active at all
times, 10% BRIGHT, which adds approximately 10 IRE units
to the output level no matter wbat the input state of the AD9701.
The 10% BRIGHT control is primarily used to highlight areas
of the video image.
As with any high-speed device, the AD9701 requires a SIIbstantial
low impedance ground plane and high quality ground co~ections
to achieve the best performance. Performance can also be 1ffiproved
with adequate power supply decoupling near the supply pins of
the AD9701. In ECL mode, the output of the AD9701 is designed
to drive 75'{} cable directly, with 75'{} terminations to ground at
both ends of the cable. For TTL configurations the output
should be terminated to + 5.0V through an 82'{} resistor (see
circuit below).
+s.ov
={~
={~
STROBE -
......- - - - - '
-S.2V
-2.0V
1.6k
STROBE - " " " ' ' ' ' ' ' ' ' ' ' - - - '
5."
Raster Graphics Configuration for TTL Systems
2-390 DIGITAL-TO-ANALOG CONVERTERS
Standard Reconstruction Configuration
Triple 4-Bit
OfAConverter
IIIIIIIIIII ANALOG
WDEVICES
A09702 I
AD9702 FUNCTIONAL BLOCK DIAGRAM
FEATURES
ECL or TIL Compatible
Composite Inputs
125MHz Update Rates Minimum
Vee 1+ 5V OR GROUND)
VEE I-S.2VI
STROBE
APPUCAnoNS
Raster Scan Displays
Color Graphics Systems
General Video Reconstruction
RED BIT 1
2
RED BIT 2
3
RED BIT 3
4
GREEN SYNC
GREEN BIT
1 6~;::~;::=:.--t:±j
GREEN BITZ
7
GREEN BIT 3
8
Z1
GREEN OUTPUT
.,...""I....-.---''ln:::J
GREEN 81T 4 " •
BLUE BIT 3
BLUE BIT 4
REFERENCE WHITE
COMPOSITE BLANKING
GENERAL DESCRIPTION
The AD9702 D/A Converter is a single monolithic IC containing
three separate 4-bit digital-to-analog (D/A) converters for red,
green, blue (RGB) graphics display applications; 4,096 colors
are available to the user. Composite blanking, green sync, and
reference white digital control inputs are also included. On-chip
data registers and a capability for varying output drive make
this a total functional solution for graphics displays.
1
1::!~==:::=~=====::::'
_____
GROUND
"':~J
with - 5.2V applied for the ECL mode; and - 5.2V and + 5V
for TIL mode. Power dissipation is 1.3 watts for ECL operation
and 1.5 watts for TTL.
Monolithic devices are inherently less expensive and more reliable
than hybrids. When combined with its small size and outstanding
electrical characteristics, these attributes make the AD9702 D/A
Converter the first choice for designers of next-generation,
medium-resolution displays.
A unique TIIJECL interface allows the designer a choice of
logic compatibility for all inputs; this can be accomplished by
applying either + 5V or ground to the Vex:. pin. Internally, the
registers and control switching signals operate at ECL logic
levels to help assure low glitch impulse at the DAC outputs.
The unit is housed in a 24-pin ceramic package and operates
DIGITAL-TO-ANALOG CONVERTERS 2-391
SPECIFICATIONS
(1JpicaI @ +25"C with IIIIIIIiIaIpllWluuppIias unless CIIIHnis8 noIIId)
Parameter
Vaits
AD970ZBDIBW
RESOLUTION
Bits
4
LEAST SIGNIFICANT BIT (LSB) WEIGHT
Voltage (Adjustsble)
Current (Adjustable)
mV
40
1
ACCURACY (GS = Gtay Scale; FS = Full Scale)
Linearity
Differential Linearity
Zero Offset (Initial)
Monotonicity
TEMPERATURE COEFFICIENTS
Linearity
Zero Offset
Gain
GainTracking
DYNAMIC CHARACTERISTICS
Sett1ingTime- Voltage'
ECLMode(to ±3.2%GS)
TTL Mode (to ±3.2%GS)
Update Rate
ECLMode
TTL Mode
Rise Time
Glitch Impulse
DIGITAL INPUTS
Logic Compatibility
Coding
ECL Logic Levels
"I"
"0"
ABSOLUTE MAXIMUM RATINGS
mA
±%GS
±%GS,max
mV,max
0.8
0.8
0.5
Gusranteed
ppmrc(max)
ppml"C(max)
ppmI"C (max)
ppml"C
20(30)
10(15)
200(400)
100
ns,max
ns,DlaX
5
6
MHz, min
MHz, min
ns
pV-s
125
75
3
80
Supply Vol_
Voc(Pin10)
V",,(PinI7)
Power Dissipation
(NominalVol_)
D/A OutpUt CUrrent
Temperature
ECLfITL
Binary (BIN)
-0.9(-1.1/-0.6)
-1.7 (- 2.0/ -1.5)
"0"
V (minimax)
V (minimax)
+3.5 ( + 2.0/ + 5.0)
+0.2(+0.0/+0.8)
Loading (Each Bit; with Typical
Input Logic Levels)
ECL"!"
ECL''O''
TTL"I"
p.AlpF
p.AlpF
p.AlpF
mA/pF
50/5
-100/5
10/5
1.5/5
TTL "0"
Setup Time (Data)
ECL
TTL
Hold Time (Data)
EeL
TTL
Propagation Delay
ECL
TTL
nS,max
ns,max
2.5
3.5
ns,max
ns,max
2
3
ns(max)
ns(max)
4(5)
5(6)
SPEED PERFORMANCE-CONTROL INPUTS
ECL and TTL Settliog Time to 1000fGSfor:
Reference White
Composite Blanking
Green Sync
10% Bright
ns,Dl8X
10
10
10
10
RED, GREEN, AND BLUE ANALOG OUTPUTS
Gray Scale Current
RefWhite2 = "0"
Ref White = "I"
Composite Blanking4 = "0"
CompositeBIanking= "I"
Green SynCS = "0"
Green Sync = "I"
Gray Scale Voltage
RefWhiteZ = "0"
RefWhite = eel"
Composite Blanking4 = "0"
Composite Blanking = "I"
Green Syncs = "0"
Green Sync = "In
2-392 DIGITAL-TD-ANALOG CONVERTERS
ns,max
ns,max
ns
mA
rnA
mA
mA
rnA
mA
mA
mV
mV
mV
mV
mV
mV
mV
Oto-16
0
Normal Operation'
-1.4
Normal Operation
-7.6
Normal Operation
Oto -600(±I%)
0
Normal Operation'
-53
Normal Operation
-285
Normal Operation
Lower
-O.IV
+l.OV
-6.0V
+0.3
l.SW
O.OV
+6.0V
-6.0V +0.3V
l.8W
30mA
30mA
-SS"Cto + 12S"C
-SS"Cto + 1SO"C
- SS"C to + 12S"C
-SS"Cto +ISO"C
PIN DESIGNATIONS
(As viewed from bottom)
PIN
FUNCTION
24
23
GROUND
GREENSVNC
2'
21
RED OUTPUT
GREEN OUTPUT
20
CURRENT SET
I.
I.I.
18
17
V (minimax)
V (minimax)
TTL Logic Levels
"I"
Operating (Case)
Storage
TIL
Upper
ECL
Vpper
Lower
14
"
GROUND
BLUE OUTPUT
VEel- 5.2V)
COMPOSITE BLANKING
STROBE
BLUE BIT 4 elSB)
BLUE BIT 3
PIN
1
2
••
••
8
•
10
1
11
12
FUNCTION
REFERENCE WHITE
RED BIT 1IMSB)
REDBIT2
REDBIT3
REDBIT4ILSB)
GREEN BIT 1 (MSSI
GREENBIT2
GREENHIl3
GREEN BIT 4ILSB)
Vcc l+5VORGROUND)
BLUE BIT 1 (Msa)
BLUEstT2
NOTE: FOR NORMAL OPERATION, CONNECT PINS 19 AND 24
TOGETHER AND TO LOW·IMPEDANCE GROUND
PLANE AS CLOSE TO CASE AS POSSIBLE.
AD9702
Parameter
RED, GREEN, AND BLUE ANALOG OUTPUTS (Cont.)
Output Impedance
Compliance
Matching
(Between any Two Gray Scale Outputs)
RGB Outputs Time Skew
RGB Outputs Cross1alk6
(IOOMHz Bandwidth)
Clock Noise on Outputs
(IOOMHz Bandwidth)
Units
AD9702BDIBW
o (minimax)
V
±%GS
IOk(5k115k)
+3.0to -1.2
1.0
nS,max
mV
2
20
mV
POWER REQUIREMENTS
- 5.2V ± 0.25V7
+ 5V ± O.25V (TTL Only)
Power Supply Rejection Ratio
ECL Power Dissipation
TTL Power Dissipation
mA(max)
mA(max)
mV/mV
W(max)
W(max)
250(288)
50(60)
0.115
1.3(1.5)
1.55 (1.8)
TEMPERATURE RANGE
Operating (Case)
Storage
°C
°C
-25to +85
-55to+150
THERMAL RESISTANCEs
Junction to Air, 6 lA (Free Air)
Junction toCase,6lc
°CIW,max
°CIW,max
40
12
PACKAGE OPTION"
D-24A
THEORY OF OPERATION
Refer to the Block Oiagram. of the AD9702 O/A Convener.
The digital inputs are applied through TIlJECL conveners to
registers within the AD9702; the purpose of the registers is to
eliminate time skew from the inputs and help reduce glitch
impulse in the output signals. The switching of the inputs through
the registers to the three internal 01A converters is controlled
by the Strobe, Green Sync, Reference White, and Composite
Blanking signals.
When operating with ECL-compatible logic, VEl! (- 5.2V) is
applied to Pin 17 and Pin 10 is connected to ground. Under
these conditions, the TI1JECL conveners at the input are
transparent to incoming signals and the signals are applied directly
to the registers. Regardless of the logic levels of the digital
inputs, the registers and control logic internal to the AD9702
are operated at ECL levels to help assure maximum switching
speed and minimum glitch on the analog outputs.
For TIL logic, Vex:. (+ 5V) is applied to Pin 10 and - 5.2V is
applied to Pin 17. The positive voltage is used only on the
TIlJECL conveners, and adds to the flexibility of the AD9702
by allowing it to be compatible with both forms of logic generally
encountered in graphics displays.
There is an alternate method of operating with TTL logic without
a need for - 5.2V supplies. In this arrangement, Pins 10, 19,
and 24 are connected to + 5V; and Pin 17 is grounded. In addition,
digital inputs (ROB Bits 1 - 4) are connected to + 5V through
2k resistors on each input line.
The disadvantage of this technique is that the output is referenced
to the + 5V supply instead of ground. When this happens, the
dc component of the output may exceed the general requirements
of RS-170 and RS-343. In addition, any noise which is on the
power supply can be coupled directly onto the video signal.
One method of overcoming these potential problems is illustrated
in Figure 1, Using AD9702 in TIL Mode.
NOTES
ISenHng to GS percentage includes FS and MSB transitions. Inherent 3DS register delay (50% points) is
not included.
2Digital "0" at "'R"""'ef<~er-en-c-e=W~h~ite control input (Pin 1) sets
registers; red, green, and blue outputs go to zero.
lIn "normal operation," GS current or GS voltage outputs for red, green, andlor blue are established by RGB
digital inputs.
4Digital "0" at "C'-om-p-o~sit-e~B~la'-nk~in-g control input (Pin 16)
resets registers; value shown is added to full-scale outputs
at red, green, and blue outputs. Reference White and
Composite Blanking should not be operated
simulraneously.
5Green Sync control signal «(c_(. Pin 23) affects only Green
Output
Pin 21); value shown is added to Green
Output established by Green digital inputs (and by
Composite Blanking if digital "0" is simultaneously
applied to Pin 16).
6Logic "0" digital inputs applied [0 D/A under test; full
scale step function "toggling" applied to active D/A.
7Power supplies should have less than IOmV p~p ripple.
8Maximum junction temperature = ISO"C.
9 See Section 14 for package outline information.
(a,
Specifications subject to change without notice.
AD9702BD
AD9702BW
In this arrangement, the strobe signal is attenuated and shifted
positively by a resistor network to minimize feedthrough of the
clock signal. The digital input signals do not require the same
kind of attenuation because their larger TIL swings do not
present any problems.
The pull-up resistors which are used on the inputs help assure
proper digital "I" logic levels regardless of which TIL logic
family is used.
The PNP level shifter shown at the analog output in Figure 1
eliminates the possible problems of TTL operation cited above.
Most of the noise which might be present on the + 5V supply is
cancelled by common mode rejection in this circuit; and level
shifting helps insure the de component of the output meets
video standards.
Minor linearity degradation and temperature drift which might
be introduced by the level shifter are not discernible on most
video displays. The level shifter circuit is repeated three times
for the Red, Green, and Blue analog outputs of the AD9702.
As shown in the block diagram and discussed in the Specifications
section, a digital "0" level of the Reference White signal (at Pin
1) is used to set the registers within the convener. This action
causes the three (ROB) analog outputs to go to zero output.
The Composite Blanking signal is applied to Pin 16; when a
digital ''0'' level is used, it resets the registers and causes the
three analog outputs to be -17.4mA or -653mV because of
the amount added to the normal full-scale outputs.
The Oreen Sync signal at Pin 23 has an effect only on the Green
Output of the AD9702 (at Pin 21). When this control and
Composite Blanking are at a digital ''0'' level, the value of the
Green analog output will be -25mA or -93SmV.
When control inputs Reference White, Composite Blanking,
and Green Sync are at digital "I" levels, the ROB analog outputs
at Pins 22, 21, and IS will be a function of their corresponding
DIGITAL-TO-ANALOG CONVERTERS 2-393
+5V
RED MSB-++H++-I+-HI++<.
RED LSB -+-I-H-I-H+.....---{!
GREEN MSB
-++H-++-I.....----{
DATA
INPUTS
GREEN LSB -+-I-H.....- - - - - {
BLUE MSB -+-I-....- - - - - - { '
- - - - - (SAME AS CIRCUIT
CUi PIN 221
BLUE LSB .-.--------{~4)
1600
STROBE
REFERENCE WHITE
-JW"""""....- - - - - - { !
----f---.-----
0
"a:
oJ
CONTROL AMP OUT
DIGITAL-Vs
REFERENCE IN
ANALOG RETURN
lOUT
lOUT
---,.,----'-
ANALOG -Vs
!z0
u
PLCC Pinout Designations
Plastic DIP Pinout Designations (Top View)
This informa1ion applies to a product under development. Its characteristics and specifica1ions are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-399
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS'
Positive Supply Voltage (+Vs)(AD9713 Only) . . . . . . . . +6 V
Negative Supply Voltage (-Vs)
(AD9712 and AD9713) . . . . . . . . . . . . . . . . . . . . . . -7 V
DAC Outputs to ANALOG RETURN ...... +0.5 V to -2 V
Digital Input Voltages (D.-D 12 , LATCH ENABLE)
AD9712 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to -Vs
AD9713 . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to +Vs
Internal Reference Output Current . . . . . . . . . . . . . . . 500 j.tA
Control Amplifier Input Voltage Range •••.••••0 V to -4 V
Control Amplifier Output Current . . . . . . . . . . . . . . ±2.S mA
REFERENCE IN Voltage Range ••••.••••• -3.7 V to -Vs
Analog Output Current (loUT or loUT) .•.••...••. 30 mA
Operating Temperature Range
AD9712JN/JP/KNIKP. ..•...•......•..•• 0 to +70"C
AD9713JN/JPIKN/KP• .........•.•••••.. 0 to +70"C
Maximum Junction Temperature2 • • • • • • • • • • • • • • • + ISO·C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . + 300"C
Storage Temperature Range •••••.••••••-6S"C to + ISO"C
ELECTRICAL CHARACTERISTICS (-Vs
= -5.2 V; +Vs = +5 V (AD971~ Only); CONTROL AMP IN = -1.2 V
(external); RS£T = 7.5 kG, unless othel'Wlse noted)
Temp
Parameter (Conditions)
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Test
Level
Units
Bits
12
m
1.0
2.0
0.75
1.0
2.0
3.0
1.0
1.5
2.5
GUARANTEED
Differential Nonlinearity (K)
m
Integral Nonlinearity
("Best Fit" Straight Line)
Integral Nonlinearity (K)
("Best Fit" Straight Line)
Monotonicity
INITIAL OFFSET ERROR
Zero-Scale Offset Error
+2S"C
Full
+2S·C
Full
+2S"C
I
VI
I
VI
V
Internal Reference Voltage Drift
Amplifier Input Impedance
Amplifier Bandwidth
+2S·C
Full
Full
+2S·C
+2S·C
I
I
V
V
V
REFERENCE INPIJf4
Reference Input Impedance
Reference Multiplying BandwidthS
+2S·C
+2S·C
V
V
+2S"C
+2S·C
+2S"C
+2S"C
+2S"C
V
IV
IV
V
IV
+2S·C
+2S·C
+2S·C
+2S·C
+2S·C
+2S"C
+2S·C
V
V
V
V
V
V
V
Full-Scale Gain Error3
Offset Drift Coefficient
REFERENCE/CONTROL AMP
Internal Reference Voltage
OUTPUT PERFORMANCE
Full-Scale Output Current6
Output Compliance Range
Output Resistance
Output Capacitance
Output Update Rate7
Output Settling Time (tST)8
Current Settling
Voltage Settling (RL = 50 G)
Output Propagation Delay (tP O)9
Glitch Impulse10
Output Slew Ratel l
Output Rise Timel l
Output Fall Timel l
0.5
-1.13
-1.11
4.0
4.0
0.03
0.03
-1.26
-1.39
-1.41
-1.13
-1.11
100
1.5
5.0
8.5
11.0
j.tA
j.tA
%
%
j.tAI"C
-1.39
-1.41
440
50
300
440
SO
300
V
V
JJ-vrc
kG
kHz
3
40
3
40
kG
MHz
20.48
-1.2
2.0
-1.26
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
2.5
30
110
30
30
8
100
400
3
2
mA
20.48
+3
3.0
-1.2
2.0
80
2.5
30
90
30
30
11
100
400
3
2
+3
3.0
V
kG
pF
MSPS
ns
ns
ns
pV-s
V/JJ-s
ns
ns
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-400 DIGITAL-TO-ANALOG CONVERTERS
AD9712/AD9713
Parameter (Conditions)
DIGITAL INPUTS
Logic "1" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitance
Input Setup Time (tS )12
Input Hold Time (tH )13
Latch Pulse Width (tLPW)
(Transparent)
AC LINEARITYI4
Spurious-Free Dynamic Range
POWER SUPPLylS
Positive Supply Current (+5.0 V)
Negative Supply Current (-5.2 V)
Nominal Power Dissipation
Power Supply
Rejection Ratio (PSRR)16
Temp
Test
Level
AD9712)NI)PIKNIKP
Typ
Min
Max
AD97131)N/)PIKNIKP
Typ
Min
Max
Full
Full
Full
Full
+ 25°C
+25°C
+25°C
VI
VI
VI
VI
V
V
V
-1.0
2.0
+25°C
-0.8
-1.7
-1.5
20
10
0.8
20
600
Units
V
V
!LA
3
3
3
3
3
3
....A
pF
ns
ns
V
2.5
4
ns
+25OC
V
-60
-55
dBc
+ 25°C
Full
+25°C
Full
+25°C
I
VI
I
VI
V
10
135
130
20
23
165
175
rnA
rnA
rnA
rnA
mW
110
....AIV
726
50
NOTES
IAbsolute maximum ratings are li
serviceability of the circuit may be impaired.
ns for an extended period of time may affect device reliability.
Functional operability is not n
'Typical thermal impedances: 28-pin plas
= 48OC/W; Ole = lOoCIW.
ratio is nominaUy 128.
'Measured as error of the ratio of full-scale c
'Full-scale variations among devices are more
'Frequency at which a 3 dB reduction in output of DAC is 0
"Based on I Fs = 128 (VRE,,!RSET) when using internal amp'
70Utput settling to 0.1%.
'Measured at midscale transition, to ±0.024%.
'Measured from falling edge of LATCH ENABLE signal to 50% point of full-scale transition.
IOGlitch impulse combines the absolute vaIue of positive and negative transitions operating in latched mode.
IIMeasured with RL = 50 (} and DAC operating in latched mode.
I'Data must remain stable prior to faIling edge of LATCH ENABLE signal for specified time.
13Data must remain stable after rising edge of LATCH ENABLE signal for specified time.
l'Update rate ,,;50 MSPS; output frequency = 5 MHz.
I'Supply voltages should remain stable within ±5% for normal operation.
I"Measured at ±5% of +Vs (AD9713 ouly) and -Vs (AD9712 or AD9713) using external reference.
Specifications subject to change without notice.
ORDERING INFORMATION
EXPLANATION OF TEST LEVELS
Package
Options*
Level
Part. No.
Description
I
II
AD9712JN
AD9712JP
AD9712KN
AD9712KP
ECL-Compatib1e
ECL-Compatib1e
ECL-Compatib1e
ECL-Compatib1e
Plastic DIP
PLCC
Plastic DIP
PLCC
N-28
P-28A
N-28
P-28A
AD9713JN
AD9713JP
AD9713KN
AD9713KP
TTL-Compatib1e
TTL-Compatible
TTL-Compatible
TTL-Compatible
Plastic DIP
PLCC
Plastic DIP
PLCC
N-28
P-28A
N-28
P-28A
- 100% production tested.
- 100% production tested at + 25°C, and sample tested at
specified temperatures.
III - Sample tested only.
IV - Parameter is guaranteed by design and
characterization testing.
V - Parameter is a typical value only.
VI - All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
*See Section 14 for package outline information.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DIGITAL-TO-ANALOG CONVERTERS 2-401
AD97121AD9713 PIN DESCRIPTIONS
Pin'
No.
Name
Function
1-10
D 2-D 11
Ten of twelve digital input bits.
11
D12 (LSB)
Least Significant Bit (LSB) of digital input word.
12
DIGITAL -Vs
One of two negative digital supply pins; nominally -5.2 V.
13
ANALOG RETURN
Analog ground return. This point and the reference side of the
DAC load resistors should be connected to the same potential
(nominally ground).
14
lOUT
Analog current output; full-scale output occurs with digital
inputs at all "1."
15
ANALOG -Vs
One of two negative analog supply pins; nominally -5.2 V.
16
loUT
Complementary analog current output; zero scale output occurs
with digital inputs at all "1."
17
REFERENCE IN
Normally connected to CONTROL AMP OUT (Pin 18). Direct
line to DAC current switch network. Voltage changes at this
point have a direct effect on the full-scale output. Full-scale
when using
current output = 128 (Reference voltag
internal amplifier.
18
CONTROL AMP OUT
19
CONTROL
17). Output of
in 20) if not
e current out = 128
internal amplifier.
20
AMP IN (Pin 19). Internal
V.
21
DIGITAL -Vs
22
REFERENCE GROUND
23
DIGITAL +Vs
Positive digital supply pin; used ouly on the AD9713; nominally
+SV.
24
RSET
Connection for external resistance reference. Full-scale current
out = 128 (Reference voltageIRsET) when using internal
amplifier.
25
ANALOG -Vs
One of two negative analog supply pins; nominally -5.2 V.
26
LATCH ENABLE
Transparent latch control line.
27
DIGITAL GROUND
Digital ground return.
28
D, (MSB)
Most Significant Bit (MSB) of digital input word.
r-\
1\
L---I
\....-
LATCH
ENABLE - - - '
LATCH ENABLE
DATA INPUTS
0UTPI1T
~
-ltHt-;"
VALID DATA
'II£
'!tII...rl....-_-_-_-_-_-_-_-_.....
~~~--------~ ~
t~_1 Y=-I______/ r - - I
l-tST-1
tLPW -
LATCH PULSE WIDTH
ts - INPUT SETUP TIME
tH _ INPUT HOLO TIME
I
tST - OUTPUT SETIUNG TIME
OUTPUT PROPAGATION DELAY
tpo -
AD97121AD9713 Timing Diagram
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-402 DIGITAL-TO-ANALOG CONVERTERS
r.ANALOG
WDEVICES
FEATURES
5ns Settling Time
100MHz Update Rate
20mA Output Current
ECl-Compatible
40MHz Multiplying Mode
Ultrahigh Speed IC
OfAConverter
AD9768 I
AD9768 FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Raster Scan & Vector Graphic Displays
High Speed Waveform Generation
Digital VCOs
Ultra-Fast Digital Attenuators
GENERAL DESCRIPTION
The Analog Devices AD9768SD D/A converter is a monolithic
current-output converter which can accept 8 bits of ECL-Ievel
digital input voltages and convert them into analog signals at
update rates as high as lOOMHz. In addition to its use as a
standard DIA converter, it can also be utilized as a two-quadrant
multiplying D/A at multiplying bandwidths as high as 40MHz.
An inherently low glitch design is used, and the complementary
current outputs are suitable for driving transmission lines directly.
Nominal full-scale output is 20rnA, which corresponds to a 1volt drop across a 50n load, or ± I volt across loon returned to
+ I volt. The actual output current is determined by the on-chip
reference voltage (VREF = - 1.26V) and an external current
setting resistor, R SET .
Full-scale output current lOUT with digital "I" at all inputs is
calculated with the equation:
VRET - VREF
R
SET
The setting resistor RSET and the output load resistor should
both have low temperature coefficients. A complementary
lOUT is also provided.
IOUT=4x
The reference voltage source is a modified bandgap type and is
nominally - 1.26 volts. This reference supply requires no external
regulation. To reduce the possibility of noise generation and/or
instability, pin 15 (REFERENCE OUT) can be decoupled using
a high-quality ceramic chip capacitor. Stabilization of the internal
loop amplifier is by a single capacitor connected from pin 17
(COMPENSATION) to ground. The miuimum value for this
capacitor is 390OpF, although a O.OIfJ.F ceramic chip capacitor
is recommended.
The incredible speed characteristics of the AD9768SD DIA
converter make it attractive for a wide range of high speed
applications. The ability of the uuit to operate as a two-quadrant
multiplying DIA converter adds another dimension to its usefulness
and makes the AD9768SD a truly versatile device.
DIGITAL-TO-ANALOG CONVERTERS 2-403
+ 25°C under following conditions unless otherwise noted;
SPECIFICATI.0. NS(typical
nominal digital input leyels; nominal power supplies; = 50H;
=. 220H; V
@
RL
Unibt
Bits
LSB WEIGHT (CURRENT)
JLA
78
±%FS
±%FS
0.2
0.2
JLA
60
ppmI'C
ppmI'C
1.5
70
TEMPERATURE COEFFICIENTS
Zero Offset
Reference Voltage ( - 1.26V)
DIGITAL DATA INPUTS
Logic Compatibility
Logic Voltage Leve!s "I" =
"0"=
RET
= 0Vl
AD97~jDISD/SE
Parameter
RESOLUTlON(FS = FULL SCALE)
ACCURACY'
Differential Nonlinearity
Integtal Nonlinearity
Monotonicity
Zero Offset (Initial)
RSET
AD9768JDlSD PIN CONNECTIONS
Guaranteed
COMPENSAnON
REFERENCE IN
V
V
REFERENCE OUT
DIGITAL
INPUTS
OUTPUTjQ
ECL
-0.9
-1.7
Binary (BIN) =' Unipolar Out
Offset Binary (OBN) = Bipolar Out
OUTPUT lIoJ
ANALOG RETURN
DIGITAL GROUND
Vcc (+5V)
OUTPUT
Current (Unipolar) FS
lour(@Pin13)
All Digital "I" Input
All Digital "0" Input
Iour(@PinI4)
All Digital "1"Input
All Digital "0" Input
Compliance
Impedance
mA(max)
2t020(30)
mA
mA
0
mA
mA
V (Pin 13)
V (Pin 14)
O(±IS%)
0
20
-0.710 +3.0
-1.1 to +3.0
750
20
SPEED PERFORMANCE
Settling Time (to 0.2% FS),
Slew Rare
Update Rare
Rise Time
Glitch Energy
ns
VI",
MHz
ns
pV~sec
100
1.8
200
REFERENCE
Intemal, MonnIithic'
External, Variable'"
V
-1.26
Voltage-Multiplying Mode
Current·Multiplying Mode
VOLTAGJ!..MULTIP!..YING MODE" (See Figure 2)
VM Ranse (at Pin 16)
VMCenrer
Resistance (at Pin 16)
Transfer Function-
Large Signal Bandwidth ( - 3dB Point)
CURRENT-MULTlPLYING MODE (See Figure 4)
1M Range (at Pins 17 & 18)
R----------{t)
DIOITALINPUTS
Figure 1. Conventional AD976BSD
The output current of the AD9768 appears at pin 13 (10 ) and
develops a voltage across the load resistor RL which is based
on:
A. 1M (the current flowing through the single-transistor
source discussed above)
B. Value of RL
1M is a function of the return voltage (VRET), the reference
voltage (VREF), and the value of R SET; all of these are selected
by the user for his application. The necessary equations for
calculating precise values for each are part ofFignre 1. As indicated,
DIGITAL-TO-ANALOG CONVERTERS 2-405
the voltage drop across RL is added to the return voltage; the
resulting voltage is the total VOUT of the converter:
VOLTAGE MULTIPLYING MODE
In addition to its use as an ultra-high speed current output DIA
converter, the AD9768 can also be used as a two-quadrant
multiplying D/A in either a voltage mode or a current mode.
Refer to Figure 2, Multiplying AD9768 (Voltage Mode).
20mA because of the maximum 30mA output drive capabilities
of the device. Different values for RSET and RL would alter the
point where limiting first appears.
CURRENT MULTIPLYING MODE
The AD9768 D/A converter can be operated at markedly higher
multiplying rates when operated in a current-multiplying mode,
as contrasted with the voltage-multiplying mode. Refer to Figure
4, Multiplying AD9768SD (Current Mode) .
.",,,.~
VOI,IT-14",,",xRJ+V...,.
NC
"
+.v
O.o1p.F
GND
D.01f'f
-6.2V
Figure 2. Multiplying AD9768 (Voltage Mode)
When operating in this mode, the analog output of the AD9768
is influenced by the digital inputs and an external multiplying
voltage (VM ) applied to pin 16 REFERENCE IN, which takes
the place of the internal reference used when the D/A is operating
in a conventional manner.
The value of 1M flowing through RSET is set by the voltage of
VRET minus the multiplying voltage (VM ), divided by R SET; the
amount of this current is part of the equation which establishes
the analog output (VOUT) of the AD9768 and is chosen by the
user for his application. As it is when operating the D/A in a
conventional fashion, VRET can be any value between 0 volts
and + 3 volts. VM (for purposes of discussion here) is some
negative voltage and can be varied over a range which is approximately I volt peak-to-peak.
If the load resistor (Rd has a value of 50 ohms, if RSET has a
value of 220 ohms, and if VRET is OV, the center of the VM
voltage will be -0.6V; and it can vary from -O.lV to -1.1V.
Typically, the frequency of these variations has an upper limit
of 250kHz when operating in the voltage multiplying mode; that
frequency is the 3dB point of the bandwidth of the internal
reference amplifier.
1 .. I--_......JI--_......Jh-......
,
=
.,~ ,,~---~-~~~---~--~
j .. ~---~~~-~~~~I---~
-
..
-1.5
Figure 3. lOUT vs. Multiplying Voltage
The combined effects of variations in VM and changes in digital
input values are shown in Figure 3, lOUT vs. Multiplying Voltage.
In this illustration, the ordinate of the graph is expressed in
terms of milliamps aT lOUT current at pin 13. VOUT , of course,
will be a function of the value of RL chosen by the user.
The negative value of VM on the horizontal axis is shown starting
at approximately -O.IV, rather than OV, because the AD9768
must have some small value of voltage applied to perform a
multiplying function. For the conditions shown in the figure,
output current starts to become nonlinear at approximately
2-406 DIGITAL-TO-ANALOG CONVERTERS
LS.
MS.
DIGITAL INPUTS
Figure 4. Multiplying AD9768SD (Current Mode)
In this mode, the internal reference amplifier and its inherent
frequency limitations are replaced by a current source comprised
of UI and associated circuits. These circuits supply a unipolar
current 1M which is one-fourth the full-scale output current
(with digital "I" applied to all inputs) and set current flow
through the load resistor.
VIN is some voltage chosen by the user for his particular application;
the' value of this voltage is based in part on the size of the load
resistor and the OmA to SmA range of 1M . VIN can have frequency
components as high as 40MHz. VAD] and RADJ provide an
offset adjustment to compensate for the dc component of VIN to
assure 1M is always a unipolar current between OmA and SmA.
The values of the required voltages and resistors can be calculated
using the equations which are part of Figure 4.
Refer to Figure 5,
1
,
lOUT
vs. Multiplying Current.
"~--4--4---~-'~~~~-~
I="~--4--~~~~~
..j
I.D
"_mA
...
...
Figure 5. lOUT vs. Multiplying Current
As shown, 1M can vary over the range of OmA to SmA; a value
of approximately O.3mA may be the practical lower limit because
of nonlinearities at extremely small current levels. These changes
in 1M are combined with variations in digital inputs, producing
complex changes in the output current (at pin 13) and in VOUT •
The "rounding" of the current curve in the graph is the result
of lou:r approaching the 30mA maximum drive capabilities of
the AD9768 and needs to be taken into account to assure optimum
performance in the selected application.
High Resolution
16-Bit D/A Converters
AD DAC71/AD DAC72* I
1IIIIIIII ANALOG
WDEVICES
FEATURES
16-Bit Resolution
% 0.003% Maximum Nonlinearity
Low Gain Drift % 7ppm/"C
o to +70"C Operation (AD DAC71. AD DAC71H.
ADDAC72CI
-25"C to + 85°C Operation (AD DAC721
Current and Voltage Models Available
Improved Second-Source
Low Cost
AD DAC71/AD DAC 72 FUNCTIONAL BLOCK DIAGRAM
6.3V REF OUT
+15V
GAIN ADJUST
SUMMING JUNCTION
COMMON
-15V
+5V
VOUT
BIT 16
BIT10
BIT 15
BIT 11
BIT 14
BIT 13
BIT 12
AD DAC71/AD DAC72
PRODUCT DESCRIPTION
The AD DAC71 and AD DACn are high resolution 16-bit
hybrid IC digital-ta-analog converters including reference, scaling
resistors and output amplifier (V models).
The devices offer outstanding accuracy, including maximum
linearity error of 0.003% at room temperature and maximum
gain drifts of lSppmf'C (AD DAC71 , AD DAC71H, AD DACnC)
and 7ppmf'C (AD DACn). This performance is possible due to
the innovative design, using proprietary monolithic D/A converter
chips. Laser-trimmed thin film resistors provide the linearity
and wide temperature range for guaranteed monotonicity.
PRODUCT HIGHLIGHTS
1. The AD DAC71 and AD DACn provide 16-bit resolution
with 0.003% linearity error.
2. The proprietary chips used in the hybrid design provide
excellent stability over temperature and improved reliability.
3. Unipolar and bipolar current and voltage output versions are
available to fill a wide range of system requirements.
4. The AD DAC71 and AD DACn are improved second source
replacements for DAC71 and DACn devices from other
manufacturers.
The AD DAC71 and AD DACn digital inputs are TTL-compatible. Coding is complementary straight binary (CSB) for
unipolar output versions and complementary offset binary (COB)
for bipolar output versions.
All versions are packaged in a 24-pin metal DIP. The AD DAC71,
AD DAC71H and AD DACnC are specified for operation from
o to + 70°C, and the AD DACn is specified from - 25°C to
+ 85°C. The AD DAC71H, AD DACn and AD DACnC are
supplied in hermetically-sealed packages.
The AD DAC71 and AD DACn are intended to serve as improved
second sources to DAC71 and DACn devices from other
manufacturers.
·Covered by Patent Numbers: 3,978,473; RE28,633; 4,020,486; 3,747,088;
3,803,590; 3,961,326; 4,213,806; 4,136,349.
DIGITAL-TO-ANALOG CONVERTERS 2-407
•
SPECIFICATIONS
(@T.
= + 25"1:, rated power supplies unless othaIwise noted)
AD DAC1VAD DAC11H
MIN
TYP
MAX
MODIIL
ADDAC7Z
ADDAC7ZC
MIN
TYP
MAX
MIN
+S.5
+0.4
+2.4
+5.5
+0
+0.4
TYP
MAX
UNITS
DIGITAL INPUTS
_wioII
16
Bits
16
16
Losi< LeftIs(Tl'L-Compuible)1
Logicol"I"
Logicol''O''
+2.4
+0
+S.S
+0.4
ACCURACY'
Linelrity Error at 25'C
"'0.01
GainErro.." VobF
Cumnt
:to.OS
:to.l
Offset Error". Voltage. Unipolar
Vol_, Bipolar
CurrClu, Unipolar
Current, Bipolar
MnnntonicityTemp.Ran&e(l4-lIiIs)
·0
"'0.003
:to.1
,.0.25
±2.0
±S.O
±1.0
±5.0
+50
+2.4
+0
",0.003
"'0.05
±0.05
±O.I
±O.OO3
;to.OS
:to.OS
±~).lS
±0.25
±2.0
zlO.O
±O.I
±l.D
±S.O
0
+50
0
±O.lS
:to.2S
±2.0
:1:10.0
±l.O
±5.0
+70
DRIF1'(Ov... SpcdficdTemp.Ran&e)
Total Bipolar Drift(includespin,offilct,
aruitinearitydrift)
Vol_
Tmin lO2S"C
±7
±7
2S"C 10 T_
Current
TJDinlOT...
:tIS
±lS
±7
±7
±IS
±IS
±5
±5
::tIS
±19
:tIl
:tIO
±15
Vdc
Vdc
%ofFSR'
%
%
mV
mV
""""
'C
ppmofFSRI'C
ppmofFSRI'C
ppm ofFSRI'C
TOTAL ERROR OVER TEMP. RANGE'
VobF, Unipolar
Tmia,to+25"C
+25"Cto T_
Voltage, Bipolar
:::!:O.O83
±O.083
TI'Ain[O+2S"C
+2SOCtoT_
Cumnt, UDipolar(T..... toT....l
Bipolar(T..wa to T...)
±0.083
±0.083
:t O. 100
::to.072
%ofFSR
%ofFSR
±0.071
::1:0.011
:to.071
±0.071
±O.IOO
%ofFSR
:1:0.23
:to.23
:to.072
±O.24
±O.24
%ofFSR
:to.23
:to.23
:tIS
±7
ppmofFSRI'C
ppm ofFSRI'C
ppmofFSRI'C
",2
±8
",I
±I
±I
ppmofFSRI'C
ppmofFSRI'C
ppmofFSRI'C
ppmofFSRI'C
ppm ofFSRI'C
ppm ofFSRI'C
10
5
....
%ofFSR
%ofFSR
TEMPERATURBCOBFFICIENTS
Gain
Vol_
T.IJlin to + 2S"C
+ 2S"C to T_
:tIS
±15
CutTCDt
0ffiIct
±15
±15
;tIS
±15
Voltaae. Unipolar
±I
Bipolar
Current, Unipolar
Bipolar
±2
±10
"'I
±I
±ls
Differential Linearity over Temperarure
SETTUNGTIMB
Vol.... Models (to ± 0.003% ofFSR)
Output: 20V Step
ILSBStep6
5
3
20
SlewRa..
Cum:otModels(to ±0.003%ofFSR)'
Outpllt: ZmAatep lOll to 1000 Load
IkfiLoad
ANALOG OUTPUT
Vol.... Models
Rangco-CSB
COB
OulpUt Current
Outplltlmpedaoce(dc)
ShorlCin::uit Duration
±is
:tIO
±2
±2
10
5
5
3
20
10
5
I
3
Switching Transient
",I
±2
",10
",I
±2
",2
Unearity Error over Temperaturc
:tlO
5
3
20
I
3
500
500
Oto+lO
:tID
Ow
500
V
V
0.05
Indefinileto Common
0.05
Indefinite toCotnmon
n
Oto -2
",I
6.0
3.0
010 -2
rnA
±I
6.0
3.0
mA
kfi
kfi
V
~5
±5
0.05
lndeflOite toCommon
~,
....
' mV
Oto +10
±IO
±ID
",5
VI"..
I
3
+ 10
~,
rnA
Current Models
Rangco-CSB
COB
010 -2
",I
6.0
3.0
Outplltlm~Unipolar
Bipolar
Compliance
INTERNAL REFERENCE VOLTAGE
-1.5
6.0
6.3
Muimum ExtemaICurrcnt'
T ....p.Coeff.ofDrift
POWER SUPPLY SENSmVITY
UDipolarOffset
±15Vdc
+SV
TO POWER COMMON
Figure 5. Use of Output Amplifier as Subtractor for Remote
Ground Sensing
TO POWER SUPPLY RETURN
Figure 3. AD DACn and AD DAC72 Connection Diagram
(Voltage Models)
In this circuit, the analog output voltage is accurately developed
between pin 17 and pin 20 of the DAC. The voltage measured
at the load will be inaccurate if there is significant resistance in
the wiring (and any connectors) between the DAC and the load.
If the load resistance is constant, the effects of RWI and RW2
can be treated as a simple gain error, and can be trinImed out.
However, if RL is variable, then RWI and RW2 should be reduced to a value less than
RL2~IN. This will reduce the effect of
the wiring resistances to a gain error of less than ILSB. The
AD DAC71 and AD DAC72 are rated at an output current of
SmA which translates to a minimum load resistance of 2k.O.
Thus wiring resistances should be held to a maximum of 30
milliohms. This corresponds to approximately six inches of #28
wire or a six inch long printed circuit track 0.050 inches wide.
The current output versions of the AD DAC7l and AD DAC72
use an external operational amplifier to conven the output current
to an output voltage. The recommended configuration is shown
in Figure 4. Notice that this configuration permits the voltage at
AD DAC71 AND
ADDMmr~~~~
D ___ _
____~~~________~~~~__,
----~~~
... =2.7""'-FOR--CS-B
R.
= 1.BkD FOR COB
__________.....
___....
____......
__D_o
--
~}VOUT
TO OTHER
ANALOG CIRCUITRY
TOPOWIR
SUPPLY COMMON
Figure 4. Connections for AD DAC71 and AD DAC72 Current
Output Versions
2-410 DIGITAL-TO-ANALOG CONVERTERS
This circuit uses the output amplifier as a subtractor stage. Any
spurious voltage developed across RW3 becomes a common
mode voltage and its error contribution is reduced by the common
mode rejection of the op amp.
In the circuits of both Figure 4 and Figure 5, RW2'S effect is
negligible since it is inside the loop of the amplifier. If current
boosting is required in order to drive heavy loads, a suitable
booster stage can be inserted between the amplifier's output and
the load. Since the loop is closed from the load end, offsets and
other errors induced by the booster are eliminated.
It is also important to minimize thermocouple effects in circuitry
using the AD DAC7l and AD DAC72. Recalling that lLSB of
a 16 bit, 10 volt scale convener is only 153 microvolts, a stray
uncompensated thermocouple can introduce several LSBs of
offset in response to minor changes in ambient temperature.
Any pan of a circuit which includes a junction between two
dissimilar metals forms a thermocouple. Such junctions include
connectors, sockets, and any soldered connections. The solution
to thermocouple errors is to insure that every junction is cancelled
by an identical, but opposite, junction at the same temperature.
While this is often automatically accomplished (for example, in
a connector carrying both signal and return leads), careful attention
should be given to the physical layout of circuits using the AD
DAC71 and AD DAC72.
Another source of signa1 degradation in high-resolution convener
circuits is magnetically-coupled interference from stray fields.
Signal and return leads should be arranged in a way which
minimizes both length and the total cross-section area of the
loop. Of course, high resolution circuits should be located as far
as possible from any sources of electromagnetic interference,
including power transformers, digital logic and electromechanical
devices.
11IIIIIIII ANALOG
WDEVICES
Complete Low Cost 12-Bit
0/AConverters
AD DAC8D/AD DAC85/AD DAC87
FEATURES
Single Chip Construction
On-Board Output Amplifier
Low Power Dissipation: 300mW
Monotonicity Guaranteed over Temperature
Guaranteed for Operation with ± 12V Supplies
Improved Replacement for Standard DAC80, DAC800
HI-5680
High Stability, High Current Output
Buried Zener Reference
Laser Trimmed to High Accuracy:
± 1/2LSB max Nonlinearity
Low Cost Plastic Packaging
AD DAC80 SERIES FUNCTIONAL BLOCK DIAGRAMS
-NC _ MONOUTHIC VERSIONS
+SV_HYBRIDVEASIONS
-Ne _ MONOUTHIC VERSIONS
+ 5\1 - HYBRID VERSIONS
PRODUCT DESCRIPTION
The AD DAC80 Series is a family of low cost 12-bit digital-to-analog converters with both a high stability voltage reference and
output amplifier combined on a single monolithic chip. The AD
DAC80 Series is recommended for all low cost 12-bit DIA converter
applications where reliability and cost are of paramount
importance.
PRODUCT HIGHLIGHTS
1. The AD DAC80 series of D/A converters directly replaces all
other devices of this type with significant increases in
performance.
Advanced circuit design and precision processing techniques
result in significant performance advantages over conventional
DAC80 devices. Innovative circuit design reduces the total
power consumption to 300mW which not only improves reliability
but also improves long term stability.
3. The high speed output amplifier has been designed to settle
within 1/2LSB for a lOY full scale transition in 2.0Il-s, when
properly compensated.
The AD DAC80 incorporates a fully differential, non-saturating
precision current switching cell structure which provides greatly
increased immunity to supply voltage variation. This same structure also reduces nonlinearities due to thermal transients as the
various bits are switched; nearly all critical components operate
at constant power dissipation. High stability, SiCr thin mm
resistors are trimmed with a fine resolution laser, resulting in
lower differential nonlinearity errors. A low noise, high stability,
subsurface Zener diode is used to produce a reference voltage
with excellent long term stability, high external current capability
and temperature drift characteristics which challenge the best
discrete Zener references.
The AD DAC80 Series is available in three performance grades
and two package types. The AD DAC80 is specified for use
over the 0 to + 70"C temperature range and is available in
both plastic and ceramic DIP packages. The AD DAC8S and
AD DAC87 are available in hermetically sealed ceramic packages
and are specified for the - 2SoC to + 8SoC and - SsoC to + 12SoC
temperature ranges.
2. Single chip construction and low power consumption provides
the optimum choice for applications where low cost and high
reliability are major considerations.
4. The precision buried Zener reference can supply up to 2.5mA
for use elsewhere in the application.
S. The low TC binary ladder guarantees that all units are
monotonic over the specified temperature range.
6. System performance upgrading is possible without redesign.
PRODUCT OFFERING
Analog Devices has developed a number of technologies to
support products within the data acquisition market. In serving
the market new products are implemented with the technology
best suited to the application. The DAC80 series of products
was first implemented in hybrid form and now it is available in
a single monolithic chip. We will provide both the hybrid and
monolithic versions of the family so that in existing designs
changes to documentation or product qualification will not have
to be done. Specifications and ordering information for both
versions are delineated in this data sheet.
DIGITAL-TO-ANALOG CONVERTERS 2-411
SPECIFICATIONS
M....I
Atin
TECHNOLOGY
DIGITAL INPUT
Binary-CBI
BCD-CCD
Logic Levels ("IlL Compatible)
VrH (Logic "1")
VIt. (Logic "0")
IIH(V1H = 5.SV)
(lA
= + 25"1:, rated power supplies IllJess oIherwise noted,)
ADDAC80
Typ
Max
....
AODACB5
Typ
Max
....
Monolithic:
Monolithic
12
ADDAC87
Typ
M ..
u....
12
Bits
Monolithic
12
Digits
+2.0
0
+5.5
+0.8
IldVIL "" O.By)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error@ + 2!SOC
CB!
ceo
:t1l4
TA@TmlntoTmIIII
+5.5
+0.8
+2.0
0
2SO
100
2SO
100
=112
~112
±112
::114
+5.5
+0.8
+2.0
•
250
100
::!:1f2
:t1l2
:112
±:II4
V
V
,..A
,..A
LSD!
LSD
LSD
Differential Linearity Error@ + zsoc
CD!
HI4
:t3/4
±3J4
±3J4
±I
:to.2
:to.l
±l
:to.2
:to.1
ceo
T/i.@TmintoT_
GainErr0r2
:to.l
:t:0.3
O!fsetError'
:to.OS
±0.15
:0.1
:!:0.05
±O.l
::to.OS
LSD
LSD
LSD
% FSR'
%FSR~
Temperature Range forGuaranteed
+70
Monotonicity
DRIFf(Tmin toT....,.}
Total Bipolar Drift. max (includes pin.
offset, and linelritydrifts)
-25
+85
:20
TotalError(TII\iato Tm •• t
Unipolar
:0.06
::to.IS
±O.IO
:tIS
±4
±I
±S
±30
±7
±3
±'O
±0.08
Bipolar
Gain
Including Internal Reference
Excluding Internal Reference
Unipolar Offset
BipolarOffsct
CONVERSION SPEED
VoltagcModel(V)5
Settling Time to ::!: O.Ol%ofFSR for
FSR change(2kOIlSOOpF load)
with 10knFeedback
with 5kflFeedback
ForLSBChange
Slew Rate
10
Current Model (I)
ScnlingTimeto ±O.OI%ofFSR
for FSRChange 1010 1000 Load
forlkOLoad
ANALOG OUTPUT
Voltage Models
Ranges-CSI
-55
+125
::20
:to.12
:to.OS
:to.18
:to.14
:to.1
::to.12
:20
::10
±3
:10
10
±30
ppmofFSRJ"C
:to.3
::to.24
%ofFSR
%ofFSR
±20
:tl0
±3
dO
ppmofFSRrC
ppmofFSlV'C
ppmofFSRrC
ppmofFSRrC
.s.s
.s
10
VI",,8
300
300
300
.'
±2.S, ::!:S, ::!:IO,
+5, +10
::!:2.5, :t5, :t"lO,
+5, +10
::!:2.S, ::!:S, :tIO,
+5, +10
V
0.05
n
-ceo
Output Current
Output Impedance(dc)
Shott Circuit Current
Current Models
Ranges- Unipolar
-Bipolar
Output Impedance- Bipolar
-Unipolar
Compliance
Internal Reference Voltage(Va)
Output Impedance
Mo External Current'
TempcoofDrift
'C
V
±5
±S
40
40
-1.96
::to.96
2.5
5.0
-2.S
+6.23
-2.0
±l.O
3.2
6.6
+6.3
1.5
::!:10
POWER SUPPLY SENSmVITY
::!: ISV ± 10%, SV lupplywhenapplicable
::!:12V±S%
-2.04
::t1.04
4.1
8.2
+10
+6.31
mA
±5
0.05
O.OS
-1.96
::to.96
2.5
5.0
-2.S
+6.23
+1.5
::!:20
-2.0
::!:1.0
3.2
6.6
+6.3
1.5
::!:IO
::to.002
::to._
-2.04
-1.96
:1.04
=0.96
2.5
5.0
-2.5
+6.23
4.1
8.2
+10
+6.31
-2.0
::!:1.0
3.2
6.6
+6.3
1.l
40
mA
-2.04
mA
mA
::t1.04
4.1
8.2
+10
+6.37
kG
kG
V
V
G
+2.5
::!:20
+2.5
::!:1O
mA
::to.002
::to.OO2
::to._
%ofFSRI%Vs
%ofFSRJ%Vs
::to.OO2
ppmofVarc
POWER SUPPLYREQUIREMENTS
RatcdVoltages
:15
±15
V
±lS
Range
Analog Supplic&
LogicSupplics
Supply Drain
+12,+15V
-12, -15V
+5V
TEAlPERATURE RANGE
S....ocarlon
Opmoting
S......
:t11.4'
:t16.5
14
0
-25
-25
.0
20
+70
+85
+125
14
-25
-55
-65
NOTES
ILeaat SipUfkant Bit.
'Adjustable to zero with external trim poteDtiometer.
J FSR meaDS "Full Scale Range" and il 20V for tbe ::!: IOV I'IIIIF and IOV for the ::!:5V Ran,e.
toaIn and offset erron adjusted to zero at + 25'"<:.
'Cp ... O, see Fipre la.
~Muimum with no desmlation of specification, !DUBt be a constant 1oIld.
2-412 DIGITAL-TO-ANALOG CONVERTERS
±16.5
±11.4'
::!:11.4'
.0
20
+85
+125
+150
14
-55
-55
-65
vol.
:t16.5
V
V
lO
20
mA
mA
mA
+125
+125
+150
'C
'C
'C
7A minimum of ::!: 12.3V II required for a ::!: 10V fuJI scale outpUt and
::!: 11.4V is required for aU other
raqes.
SpeciflCatioas aubject to chaDse without notke.
SpeciflCationa shown in boldface are tested on aU production units at fillli eb:trical test. Results from those tests are used to caJc:uktc OUtaomB quality levels. All
min and max lpecifk:ations are auuaateed, although only those shown in
boldl'acearetested"on.allproducrioDunitl.
(fA = + 25"1:, rated power supplies
unless otherwise noted.)
SPECIFICATIONS
Typ
Min
DIGITAL INPUT
Binary-CDI
BCD-CCD
Logic Levels (TTL Compatible)
V1H(Logic"!")
VIL(Logic"O")
M ..
Mi.
Typ
+2.0
0
In-I(VIH = S.5V)
III.(V IL = O.8V)
TI\(11 TminlOTmu
Min
12
12
3
+5.5
+0.8
+5.5
+0.8
+2.0
0
+2.0
±1I2
:d/4
±UZ
::t1l2
±1I4
:rlf2
:t1l4
:tIl4
Units
12
Bits
Digits
+5.5
+0.8
V
V
.A
.A
:=1/2
±114
::!:lll
LSBI
LSB
LSB
±I
LSB
LSB
LSB
+250
-100
+250
-100
±114
:tI/S
:t114
M",
Hybrid
3
+250
-100
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error ((/' + 25"C
CBI
CCO
M ..
Hybrid
Hybrid
TECHNOLOGY
ADDAC85
Typ
ADDACBSC
ADDACSO
Model
AD DAC8D/AD DAC85/AD DAC87
.:!:112
±1/2
Differential Linearity Error ((I + 2S·C
GainErrorl
±O.l
::!:314
::!:112
±I
:to.3
OffsetErro~
::to.OS
:to.IS
CBI
CCO
TACiI Tmi"IOTmlli
Temperature Range for Guaranteed
Monotonicity
DRIFT(TmintoT....,.)
Tow Bipolar Drift, max (includes gain.
offset, and Iinearitydrifta)
Total Error (Tmin to T mu)4
Unipolar
Bipolar
GUn
Including Internal Reference
Excluding Internal Reference
Unipolar Offset
Bipolar Offset
:to.08
:to.06
±I
::to.OS
+70
-25
+85
'C
::!:20
ppm ofFSRlOC
%ofFSR
%ofFSR
:t20
:t10
::!:20
::!:10
30
±I
±I
:tl0
::!:IO
10
1.5
15
1.5
20
1.5
20
300
300
300
:0:2.5, ±5, ::!:IO,
+5, + 10
:!:10
::!:2.5, :!:5, :tW,
+5,+10
+10
:0:2.5, :t5, ±IO,
ppm ofFSR/"C
ppm ofFSRIOC
ppmofFSRrC
ppmofFSRrC
0.05
Indefmite to Common
-2.0
±1.0
3.2
6.6
-1.5, +10
+6.3
1.5
-2.0
::!:1.0
3.2
6.6
-2.5, +10
+6.3
1.5
::!:IO
+6.43
+6.17
:!:IO
+6.43
+6.17
:t14.5
+4.S
10
2(1
15
35
25
20
I5
NOTES
'Least Sisnificant Bit.
aAdjustable to zero with extemal trim pOtentiometer.
J FSR mans "FuJI Scale Raqe" and is lOV for the ± lOY flIDIC od IOV for the ± 5V Raqe.
4Gain aDd offset errors adjusted to zero at + 25-c.
mA
mA
+6.43
±14.5
+4.5
20
30
20
+70
+85
+150
-25
-55
-65
k!l
k!l
V
V
n
+2.5
±20
mA
ppmofVllfC
%ofFSRI%Vs
:tIS,S
±15.S
+15.S
2(1
-25
-65
V
mA
n
:!:0.002
:!:IS,S
+70
+85
+130
-2.0
:!:1.0
3.2
6.6
-2.5, +10
+6.3
1.5
:!::l0
,2(1
::to.002
,0.002
:!:16
+l6
V
0.05
Indefinite to Common
+2.5
+2.5
±20
:tIS,S
±14
+4.5
VfJJ.s
±5
0.05
Indefinite to Common
+6.17
.''"
.'
+5, +10
+10
,5
±5
-25
-55
% FSR 3
%FSR 3
±O.l
::to.1
::to.OS
.,
POWER SUPPLY SENSmVITY
:!:: I5V::!:: 10%, 5V supply when applicable
TEMPERATURE RANGE
Specification
Operating
S""...
:t1/2
:to.15
:to.l0
:tIS
±5
,1
±5
ANALOG OUTPUT
Voltage Models
Ranges-CBI
POWER SUPPLY REQUIREMENTS
RatedVoltageS
R ....
AnaIogSupplies
Logic Supplies
Supply Drain'
+15V
-15V
+5V
:t1l2
::!:1/2
+70
CONVERSION SPEED
Voltage Model (V)s
Settling Time to :t 0.01% ofFSR for
FSR change (2kOI1500pF load)
with lOkflFeedback
with 5kOFeedback
For LSB Change
Slew Rate
10
CUrrent Model(I)
Settling Time to ::!:O.Ol%ofFSR
for FSRChange 10 to 1000 Load
forlknLoad
-CCO
OutputCurrent
Outputlmpedance(dc)
Short Circuit Duration
Current Models
Ranges- Unipolar
-Bipolar
OutpUt Impedance-Bipolar
-Unipolar
Compliance
Internal Reference Voltage(Vp)
Outputlmpedance
Max External Current 6
TempooofDrift
:till
V
±IS.5
+15.5
V
V
I5
20
25
30
I5
20
mA
mA
mA
+85
+12S
+150
'C
'C
'C
SCI''' 0, see FiJure la.
'MaximutD with DO dep-adation of specifICation, must be. constant load.
7IncludinJ; SrnA load.
Specificationa subject to chanp: without notice.
D/G/TAL-TO-ANALOG CONVERTERS 2-413
•
SPECIFICATIONS
Model
(TA
= + 25"C, rated power supplies unless otherwise noted.)
ADDACSSLD
Min
Typ
TECHNOLOGY
Max
Min
M",
Units
12
Bits
Hybrid
Digits
+5.5
+0.8
+2.0
0
VII. (Logic"O")
Typ
Min
12
12
BCD-CCO
Logic Levels (TTL Compatible)
Vm(Logic"l")
ADDAC87
Max
Hybrid
Hybrid
DIGITAL INPUT
Binary-COl
ADDAC8SMIL
Typ
+2.0
+5.5
+0.8
0
+250
-100
IIH(V1H = S.5V)
III. (VII. = O.8V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error (il + 2SOC
CBI
+5.5
+0.8
+2.0
0
+250
-100
+250
-100
±1/2
:t112
:!:112
±3/4
±114
,.A
,A
:t1l2
LSD 1
::t:314
LSD
LSD
CCD
TA(j1 TmintoT.....
DifferentialLinearityError(f(i +25'"C
CBI
:to.1
::to.l
OffsctErrotl
.0.05
::to.OS
-25
+85
.,
.,
.,
TA@TmiD,lOTmax
GainE~
Temperature Range for Guaranteed
Monotonicity
DRIFT(TmlntoT....,J
z1l2
rll2
:tIl2
CCD
-55
:to.1
::to.OS
+125
-55
V
V
:to.2
±O.l
+125
LSD
LSD
LSD
% FSR3
%FSR 3
"C
Total Bipolar Drift, max(mcludesgain,
offset, and linearity drifts)
Total Error(TnUll to T .....)4
Unipolar
Bipolar
Gain
Including Internal Reference
±IO
.,
Excluding Internal Reference
Unipolar Offset
Bipolar Offset
:tIS
dO
ppmofFSRI"C
±0.13
::!::O.ll
:to.30
±O.24
%ofFSR
%ofFSR
ppmofFSRrC
ppmofFSRrC
ppmofFSRI"C
ppmofFSRI"C
.20
.,0
.25
:t10
::tIO
.,.,
.5
.2
~S
d
:t1O
CONVERSION SPEED
Vol_Model(V)'
Settling Time to :to.Ol%ofFSRfor
FSRchange(2knIISOOpF load)
with 10kflFeedback
with SkfiFeedback
For LSB Chanse
Slew Rate
CurrentModcl (I)
SettlingTimelO ::t 0.01% ofFSR
for FSRChange 1010 1000 Load
forlkOLoaci
,."
.'
3
1.5
20
1.5
1.5
20
20
300
300
300
V/ILS
"
ANALOG OUTPUT
Voltage Models
Ranges-CBI
:t2.5, ::tS, :tIO,
+5, +10
-CCD
OutputCurrent
Output Impedance(dc)
ShonCircuit Duration
Current Models
Ranges- Unipolar
-Bipolar
Output Impedance-Bipolar
-Unipolar
Indefinite to Common
-2.0
::tl.O
3.2
6.6
-2.5,+10
+6.3
-2.0
:t1.0
3.2
6.6
-2.5, +10
+6.3
+6.17
+6.43
+6.17
::tIO
+2.5
20
10
:tIS,S
+SV
5.0
+6.43
+6.17
:t14.5
+4.5
-2.0
::tl.O
3.2
6.6
-1.5,+10
+6.3
mA
mA
4.1
8.2
Idl
Idl
+6.43
V
V
1.5
+2.5
20
.5
+2.5
10
::to.002
:to.003
::tIS,S
:tIS,S
:tIS.5
+15.5
+4.5
2.5
:to.OO2
:to.OO2
:t14.S
mA
n
0.05
lndefmite toCommon
1.5
1.5
POWER SUm.Y REQUIREMENTS
Rated Vol.....
Logic Supplies
SupptyDrain7
+15V
-15V
V
.5
0.05
lndefmitetoCommon
pOWER SUPPLY SENSITIVITY
::t ISV:t IO%,5Vsupplywbec.appJiabJe
_Su,.,...
+5, +10
.5
0.05
eun....
......
::t2.5, :tS, ::tIO,
+5, +10
V
.5
Compliance
Internal Reference Voltage (V IV
OutputImpedance
Max External
TempcoofDrift
:t2.5, ::tS, ::tIO,
:tl5.S
+15.5
15
20
IS
20
2'
30
20
25
IS
30
15
:t13.S
+4.5
10
20
10
20
n
mA
ppmofVRfC
%ofFSRI%Vs
V
±16.S
+16.5
V
V
20
mA
mA
mA
30
20
TEMPERATURE RANGE
SpecifICation
Opera....
-25
+85
-55
Storage
-,5
+125
+125
-'5
-55
-55
NOTES
ILeast Sipific:ant Bit.
2Adjuable to zero with external trim potentiometer.
5 PSR ..... "Full Scale Rance" and is 20V
die ::t IOV t8JI8e and IOV for the ± SV Ranse·
4Gam and oftieterrorsacljusted to zero at +25"<:.
eo.
2-414 DIGITAL-TO-ANALOG CONVERTERS
+125
+125
+120
-55
-55
-65
+125
+125
+150
'(:.=0, see Figure 1•.
'Maxiawm with no depadation of spcclficltion. must be • constant lMd.
'Including SmA to.d.
Specifications subject to chaqe without notK:c.
"C
"C
"C
AD DAC80/AD DAC85/AD DAC87
ABSOLUTE MAXIMUM RATINGS
+ Vs to Power Ground
....... .
- VS to Power Ground . . . . . . . .
Digital Inputs (Pins I to 12) to Power Ground
OV to +ISV
OV to -ISV
-l.OV to
+7V
Ref In to Reference Ground. . . . .
± 12V
± 12V
Bipolar Offset to Reference Ground .
lOY Span R to Reference Ground . .
± 12V
20V Span R to Reference Ground . .
± 24V
Ref Out . . . . . . . Indefinite short to power ground or + Vs
*NC _ MONOUTHIC VERSIONS
+ 5V -
*NC - MONOLITHIC VERSIONS
+5V _ HYBRID VERSIONS
HYBRID VERSIONS
Voltage Model Functional Diagram and Pin Configuration
Current Model Functional Diagram and Pin Configuration
ORDERING GUIDE
Model
Input
Code
Output
Mode
Technology
Temperature
Range
Linearity
Error
Package
Options·
ADDACSON-CBI-V
AD DACSOD-CBI-V
AD DACSOD-CBI-I
Binary
Binary
Binary
Voltage
Voltage
Current
Monolithic
Monolithic
Monolithic
Oto +70°C
Oto + 70°C
Oto +70°C
±1I2LSB
±1I2LSB
±1I2LSB
N-24
D-24
D-24
AD DACS5D-CBI-V
Binary
Voltage
Monolithic
- 25°C to + S5°C
±1I2LSB
D-24
AD DACS7D-CBI-V
Binary
Voltage
Monolithic
- 55°C to + 125°C
± 1I2LSB
D-24
ADDACSO-CBI-V
AD DACSO-CBI-I
AD DACSO-CCD-V
AD DACSO-CCD-I
AD DACSOZ-CBI-V
AD DACSOZ-CBI-I
AD DACSOZ-CCD-V
AD DACSOZ-CCD-I
Binary
Binary
Binary Coded Decimal
Binary Coded Decimal
Binary
Binary
Binary Coded Decimal
Binary Coded Decimal
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Oto +70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto +70°C
Oto+70°C
Oto + 70°C
±1I2LSB
±1I2LSB
±1I4LSB
± 1I4LSB
±1I2LSB
±1I2LSB
± 1I4LSB
±1I4LSB
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
AD DACS5C-CBI-V
AD DACS5C-CBI-I
AD DACS5-CBI-V
AD DACS5-CBI-I
AD DACS5LD-CBI-V
AD DACS5LD-CBI-I
AD DACS5MIL-CBI-V
AD DACS5MIL-CBI-I
AD DACS5C-CCD-V
AD DACS5C-CCD-I
AD DACS5-CCD-V
AD DACS5-CCD-I
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary Coded Decimal
Binary Coded Decimal
Binary Coded Decimal
Binary Coded Decimal
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Oto+70°C
Oto + 70°C
-25°Cto +S5°C
- 25°C to + 85°C
-25°Cto +S5OC
-25°Cto +S5OC
- 55°C to + 125°C
- 55°C to + 125°C
Oto + 70°C
Oto + 70°C
- 25°C to + 85°C
- 25°C to + S5°C
±1I2LSB
±1I2LSB
±1I2LSB
± 1I2LSB
± 1I2LSB
± 1I2LSB
± 1I2LSB
±1I2LSB
±1I4LSB
± 1I4LSB
±1I4LSB
± 1I4LSB
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
AD DACS7-CBI-V
AD DACS7-CBI-I
Binary
Binary
Voltage
Current
Hybrid
Hybrid
- 55°C to + 125°C
- 55°C to + 125°C
± 1I2LSB
± 1I2LSB
DH-24A
DH-24A
·See Section 14 for package outline information.
DIGITAL-TO-ANALDG CONVERTERS 2-415
DIGITAL INPUT CODES
The AD DAC80 Series accepts complementary digital input
code in binary (CBI) format. The CBI model may be connected
by the user for anyone of three complementary codes: CSB,
COB or CTC.
Digital Input
MSB
LSB
000000000000
o I I III II I 1 I I
100000000000
111111111111
Current Output Models. Two settling times are specified to ± 0.01%
ADalog Output
CSBCompl.
Straight Biaary
+ Full Scale
+ liZ Full Scale
Mid-Scale
Zero
COB Compl.
Offset Binary
+ Full Scale
Zero
-ILSB
-Full Scale
lLSB change is measured at the major carry (0 1 1 1 ... 1 I to
1 0 0 0 ... 0 0), the point at which the worst case setding time
occurs. The setding time characteristic depends on the compensation capacitor selected, the optimum value is 25pF as shown
in Figure 1a.
CTC·Compl.
Two's Compl.
-ILSB
-Full Scale
+ Full Scale
Zero
of FSR. Each is given for current models connected with two
different resistive loads: 10 to 100 ohms and 1000 to 1875 ohms.
Internal resistors are provided for connecting nominal load
resistances of approximately 1000 to 1800 ohms for output voltage
ranges of ±lVand 0 to -2V.
*Invert the MSB oftheCOB codewJth anexternal inverter toobtain CTC code.
Table I. Digital Input Codes
ACCURACY
Accuracy error of a DIA converter is the difference between the
analog output that is expected when a given digital code is applied
and the output that is actually measured with that code applied
to the converter. Accuracy error can be caused by gain error,
zero error, linearity error, or any combination of the three. Of
these three specifications, the linearity error specification is the
most important since it cannot be corrected. Linearity error is
specified over its entire temperature range. This means that the
analog output will not vary by more than its maximum specification, from an ideal straight line drawn between the end points
(inputs all "l"s and all "O"s) over the specified temperature
range.
Figure la. Voltage Model Settling Time Circuit
Differential linearity error of a DIA converter is the deviation
from an ideal lLSB voltage change from one adjacent output
state to the next. A differential linearity error specification of
± 1I2LSB means that the output voltage step sizes can range
from 1I2LSB to 1 1I2LSB when the input changes from one
adjacent input state to the next.
DRIFT
Gain Drift is a measure of the change in the fuil scale range
output over temperamre expressed in parts per million of full
scale range per °c (ppm of FSRf'C). Gain drift is established
by: 1) testing the end point differences for each AD DAC80
model at the lowest operating temperamre, + 25°C and the
highest operating temperature; 2) calculating the gain error with
respect to the + 25°C value and; 3) dividing by the temperature
change.
Offset Drift is a measure of the acmal change in output with all
"1"s on the input over the specified temperamre range. The
maximum change in offset is referenced to the offset at + 25°C
and is divided by the temperamre range. This drift is expressed
in parts per million of full scale range per °c (ppm of FSRf'C).
SETTLING TIME
Settling time for each model is the total time (including slew
time) required for the output to setde within an error band
around its fmal value after a change in input.
Voltage Output Models. Three settling times are specified to
±0.01% offull scale range (FSR); two for maximum full scale
range changes of 20V, lOY and one for a lLSB change. The
2-416 DIGITAL-TO-ANALOG CONVERTERS
Figure lb. Voltage Model Settling Time CF = 25pF
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a power
supply change on the D/A converter output. It is defined as a
per cent of FSR per per cent of change in either the positive or
negative supplies about the nominal power supply voltages.
REFERENCE SUPPLY
All models are supplied with an internal 6.3 volt reference voltage
supply. This voltage (pin 24) is accurate to ± 1% and must be
connected to the Reference Input (pin 16) for specified operation.
This reference may also be used externally with external current
drain limited to 2.5mA. An external buffer amplifier is recommended if this reference is to be used to drive other system
components. Otherwise, variations in the load driven by the
reference will result in gain variations. All gain adjustments
should be made under constant load conditions.
Performance Over Temperature - AD DAC8D/AD DAC85/AD DAC87
ANALYZING DEVICE ACCURACY OVER THE
TEMPERATURE RANGE
For the purposes of temperature drift analysis, the major device
components are shown in Figure 2. The reference element and
buffer amplifier drifts are combined to give the total reference
temperature coefficient. The input reference current to the
DAC, IREF' is developed from the internal reference and will
show the same drift rate as the reference voltage. The DAC
output current, I oAc , which is a function of the digital input
codes, is designed to track I REF ; if there is a slight mismatch in
these currents over temperature, it will contribute to the gain
T.C. The bipolar offset resistor, R BP , and gain setting resistor,
~AIN' also have temperature coefficients which contribute to
system drift errors. The input offset voltage drift of the output
amplifier, OA, also contributes a small error.
There are three types of drift errors over temperature: offset,
gain, and linearity. Offset drift causes a vertical translation of
the entire transfer curve; gain drift is a change in the slope of
the curve; and linearity drift represents a change in the shape of
the curve. The combination of these three drifts results in the
complete specification for total error over temperature.
Total error is defined as the deviation from a true straight line
transfer characteristic from exactly zero at a digital input which
calls for zero output to a point which is defined as full scale. A
specification for total error over temperature assumes that both
the zero and full scale points have been trimmed for zero error
at + 25°C. Total error is normally expressed a percentage of the
full scale range. In the bipolar situation, this means the total
range from - VFS to + V FS .
Several new design concepts not previously used in DAC80-type
devices contribute to a reduction in all the error factors over
temperature. The incorporation of low temperature coefficient
silicon-chromium thin-film resistors deposited on a single chip,
a patented, fully differential, emitter weighted, precision current
steering cell structure, and a T.C. trimmed buried zener diode
reference element results in superior wide temperature range
performance. The gain setting resistors and bipolar offset resistor
are also fabricated on the chip with the same SiCr material as
the ladder network, resulting in low gain and offset drift.
+15V
MONOTONICITY AND LINEARITY
The initial linearity error of ± lf2LSB max and the differential
linearity error of ± 3/4LSB max guarantee monotonic performance
over the specified range. It can, therefore, be assumed that
linearity errors are insignificant in computation of total temperature
errors.
UNIPOLAR ERRORS
Temperature error analysis in the unipolar mode is straightforward:
there is an offset drift and a gain drift. The offset drift (which
comes from leakage currents and drift in the output amplifier
(OA» causes a linear shift in the transfer curve as shown in
Figure 3. The gain drift causes a change in the slope of the
curve and results from reference drift, DAC drift, and drift in
~AIN relative to the DAC resistors.
BIPOLAR RANGE ERRORS
The analysis is slightly more complex in the bipolar mode. In
this mode R BP is connected to the summing node of the output
amplifier (see Figure 2) to generate a current which, exactly
balances the current of the MSB so that the output voltage is
zero with only the MSB on.
Note that if the DAC and application resistors track perfectly,
the bipolar offset drift will be zero even if the reference drifts.
A change in the reference voltage, which causes a shift in the
bipolar offset, will also cause an equivalent change in lREF and
thus IOAc, so that IOAc will always be exactly balanced by IBP
with the MSB turned on. This effect is shown in Figure 3. The
net effect of the reference drift then is simply to cause a rotation
in the transfer around bipolar zero. However, consideration of
second order effects (which are often overlooked) reveals the
errors in the bipolar mode. The unipolar offset drifts discussed
before will have the same effect on the bipolar offset. A mismatch
of RBP to the DAC resistors is usually the largest component of
bipolar drift, but in the AD DAC80 this error is held to lOppm/OC
max. Gain drift in the DAC also contributes to bipolar offset
drift, as well as full scale drift, but again is held to lOppmfC
max.
t
IDEAL
UNIPOLAR
INPUT ~
t
v-
Figure 2. Bipolar Configuration
~
~+--r':"""-'--------BIPOLAR (IDEAL CASE)
Figure 3. Unipolar and Bipolar Drifts
DIGITAL-TO-ANALOG CONVERTERS 2-417
•
Using the AD DAC8D Series
POWER SUPPLY CONNECTIONS
For optimum performance power supply decoupling capacitors
should be added as shown in the connection diagrams. These
capacitors (l/LF electrolytic recommended) should be located
close to the AD DAC80. Electrolytic capacitors, if used, should
be paralleled with O.OI/LF ceramic capacitors for optimum high
frequency performance.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by insta1ling external OFFSET and GAIN potentiometers. These potentiometers should be
connected as shown in the block diagrams and adjusted as described
below. TCR of the potentiometers should be l00ppml°C or less.
The 3.9MO and 10MO resistors (20% carbon or better) should
be located close to the AD DAC80 to prevent noise pickup. If it
is not convenient to use these high-value resistors, a functionally
equivalent "T" network, as shown in Figure 6 may be substituted
in each case. The gain adjust (pin 23) is a high impedance point
and a O.OIfJ.F ceramic capacitor should be connected from this
pin to common to prevent noise pickup.
Offset Adjustment. For unipolar (CSB) configurations, apply the
digital input code that should produce zero potential output and
adjust the OFFSET potentiometer for zero output. For bipolar
(COB, CTC) configurations, apply the digital input code that
should produce the maximum negative output voltage. Example:
If the FULL SCALE RANGE is connected for 20 volts, the
maximum negative output voltage is -IOV. See Table II for
corresponding codes.
Gain Adjustment. For either unipolar or bipolar configurations,
apply the digital input that should give the maximum positive
voltage output. Adjust the GAIN potentiometer for this positive
full scale voltage. See Table II for positive full scale voltages.
+Vs
-Vs
-Vs
L..f-~4-<>+Vs
L....-.....-4~+Vs
r--~---o-Vs
I---e---o-Vs
Figure 5. External Adjustment and Voltage Supply
Connection Diagram, Voltage Model
Figure 4. External Adjustment and Voltage Supply
Connection Diagram, Current Model
270k0
1QMn
o-'VV\r-O
3.9MO
o-wv-o
27OkO
~
T
Figure 6. Equivalent Resistances
Analog Output
Digital Input
12 Bit Resolution
Voltage·
Current
LSB
Oto +10V
±10V
Oto -2mA
±lmA
000000000000
011111111111
100000000000
111111111111
ILSB
+9.9976V
+S.OOOOV
+4.9976V
O.OOOOV
2.44mV
+9.99S1V
O.OOOOV
4.88mV
-lO.OOOOV
-0.0049V
-1.999SmA
-l.OOOOmA
-0.999SmA
O.OOOOmA
0.488/LA
-0.999SmA
O.OOOOmA
+O.OOOSmA
-1.00mA
0.488/LA
MSB
*To obtain values for other binary ranges 0 to + 5V range: divide 0 to + 10 values by 2;
± 5Vrange: divide ± IOVrange values by 2; ±2.5Vrange:divide ± IOVrangevaIuesby4.
Table II. DigitallnputiAnalog Output
2-418 DIGITAL-TO-ANALOG CONVERTERS
Applying the AD DAC8D/AD DAC85/AD DAC87
VOLTAGE OUTPUT MODELS
Internal scaling resistors provided in the AD DAC80 may be
connected to produce bipolar output voltage ranges of ± 10, ± S
or ± 2.5V or unipolar output voltage ranges of 0 to + S or 0 to
+ 10V (see Figure 7).
[
REFIN
17
5kO
15
'6
6.3kn
~
TO REF - ..............
----"VI/l.·~---....,r,;1 ~lri~t,.R
Figure B. Internal Scaling Resistors
L!!J
CONTROL CIRCUIT
~COM
SUMMING
Internal resistors are provided to scale an external op amp or to
configure a resistive load to offer two output voltage ranges of
± IV or 0 to -2V. These resistors (RLI : TCR = 20ppm/°C) are
an integral part of the AD DAC80 and maintain gain and bipolar
offset drift specifications. If the internal resistors are not used,
external RL (or Rp) resistors should have a TCR of ±2Sppm/°C
or less to minimize drift. This will typically add ± SOppmfC +
the TCR of RL (or Rp) to the total drift.
JUNCTION
RESISTOR - -.....NETWORK
G
6.3ka
'INw
~
~~ t
REF
INPUT
FROM WEIGHTED
TO REF CONTROL CIRCUIT
.......,.,...----~----t
OUTPUT
Figure 7. Output Amplifier Voltage Range
Scaling Circuit
BIPOLAR OFFSET
Gain and offset drift are minimized in the AD DAC80 because
of the thermal tracking of the scaling resistors with other device
components. Connections for various output voltage ranges are
shown in Table III. Settling time is specified for a full scale
range change: 4 microseconds for a 10kO feedback resistor; 3
microseconds for a SkO feedback resistor when using the compensation capacitor shown in Figure 1.
REFERENCE INPUT
6.3kn
17
1
16
TO REF
CONTROL
CIRCUIT
15 loUT
G~ o
TO'2mA
I6.6k0
21 COMMON
V
6.3V
or
The equivalent resistive scaling network and output circuit of
the current model are shown in Figures 8 and 9. External R LS
resistors are required to produce exactly 0 to - 2V or ± 1V
output. TCR of these resistors should be ± 100ppm/°C or less to
maintain the AD DAC80 output specifications. If exact output
ranges are not required, the external resistors are not needed.
24 REFERENCE OUT
Figure 9. AD DACBO Current Model Equivalent
Output Circuit
Output
Range
Digital
Input Codes
Connect
Pin 15to
Connect
Pin 17to
Connect
Pin 19 to
Connect
Pin 16to
±10V
±SV
±2.SV
Oto +10V
Oto +SV
Oto + IOV
COBorCTC
COBorCTC
COBorCTC
CSB
CSB
CCD
19
18
18
18
18
19
20
20
20
21
21
N.C.
IS
N.C.
20
N.C.
20
IS
24
24
24
24
24
24
Table III. Output Voltage Range Connections-Voltage Model AD DACBO
1%
Metal Film
External
Resistance
RLS
Connect
Pin 15 to
Connect
Pin 18to
Connect
Pin 20 to
Connect
Pin 16 to
Connect
Pin 17to
RLI Connections
Bipolar Offset
Reference
Digital
Input Codes
Output
Range
Internal
Resistance
RLI
CSB
Oto -2V
0.968kO
2100
20
19 & R LS
IS
24
Com (21)
Between
Pin 18&
Com (21)
COBorCTC
±lV
1.2kO
2490
18
19
RLS
24
IS
Between
Pin20&
Com (21)
CCD
Oto ±2V
3kO
N/A
N.C.
21
N.C.
24
N.C.
N/A
RLS
Table IV. Current Model/Resistive Load Connections
DIGITAL-TO-ANALOG CONVERTERS 2-419
•
DRIVING A RESISTIVE LOAD UNIPOLAR
A load resistance, RL = R LI , + R LS , connected as shown in
Figure 10 will generate a voltage range, VOUT, determined by:
\
and VOUT max ;" -2.SV
To achieve specified drift, connect the internal scaling resistor
(RLI) as shown in Table IV to an external metal film trim resistor
(RLS) to provide full scale output voltage range of 0 to - 2V.
WithRLS = 0, VOUT = -1.69V.
16
~
2mA
~~
18
"LI
...
20
1
U2kO
+
~OUT
21 COMMON
CURRENT CONTROLLEO
BY DIGITAL INPUT
Where RL max = 1.S4kO
8 ! S S
6
5
Q
co
c
~
If
J
4
ADV453 DIP
TOP VIEW
eNOl to Scalol
ADV453 PLCC
TOPYlEW
(Not to Scalel
OLD
ORDERING INFORMATION!
Speed
Package Options'
Plastic DIP (N-40A)
PLCC3 (P-44A)
66MHz
40MHz
ADV453KN66
ADV453KP66
ADV453KN40
ADV453KP40
NOTES
1All devices are specified for 0 to +70"C operation.
2See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier U-lead).
2-424 DIGITAL-TO-ANALOG CONVERTERS
0
..
::;
.} 8 ~
ADV453
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs to the
blanking level, as shown in Table V. The BLANK signal is latched on tbe rising edge of CLOCK. While BLANK is at
logical zero, the pixel and overlay inputs are ignored.
SYNC
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE current source
on the I SYNC output (see Figure 5). SYNC does not override any other control or data input, as shown in Table V;
therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.
CLOCK
Clock input (TTL compatible). The rising edge of CLOCK latches the P(}-P7 and OLO-OLI data inputs as well as tbe
SYNC and BLANK control inputs. It is typically tbe pixel clock rate of tbe video system. CLOCK should be driven by
a dedicated TTL buffer.
P(}-P7
Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the color
palette RAM is to be used to provide color information. P(}-P7 pixel select inputs are latched on the rising edge of
CLOCK. PO is the LSB. Unused pixel select inputs should be connected to GND.
OLO-OLI
Overlay select inputs (TTL compatible). These" inputs specify which palette is to be used to provide color information
(see Table IV), i.e., the 256x24 color palette or the 3x24 overlay palette. When accessing the overlay palette, tbe P(}-P7
inputs are ignored. OLO-OLI are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be
connected to GND.
lOR, lOG, lOB
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a doubly
terminated 75n coaxial cable, as shown in Figure 4a. All three current outputs should have similar output loads whether
or not they are all being used.
IsyNC
Sync current output. This high impedance current source can be directly connected to the lOG output (see F~).
This allows sync information to be encoded onto the green channel. I syNC does not output any current while SYNC is at
logical zero. The amount of current output at IsyNC while SYNC is at logical one is given by:
IsyNC (mA) = 1,728 * VREF(V)! RSET (n).
If sync information is not required on the green channel, IsyNC should be connected to GND.
FS ADJUST
Full scale adjust control. A resistor (RsET) connected between this pin and GND (see Figure 6) controls the magnitude
of the full scale video signal. Note that the IRE relationships in Figure 5 are maintained, regardless of the full scale
output current.
The relationship between RSET and the full scale output current on lOG (assuming IsyNC is connected to lOG) is given
by:
lOG (mA) = (K + 326 + 1,728) * VREF(V)IRSET (n)
The relationship between Rsn and the full scale output current on lOR and lOB is given by:
lOR, lOB (mA)=(K + 326)* VRE~V)lRsET(n)
where K = 3,993
COMP
Compensation pin. This is a compensation pin for the internal reference amplifier. A O.Ifl.F ceramic capacitor must be
connected between COMP and VAA (Figure 6).
VREF
Voltage reference input. An external 1.235V voltage reference must be connected to this pin. The use of an external
resistor divider network is not recommended. A 0.1 fl.F decoupling ceramic capacitor should be connected between VREF
and VAA (Figure 6.)
Analog power supply (5V±5%). All VAA pins on the ADV453 must be connected.
Analog ground. All GND pins must be connected.
Chip select control input (TTL compatible). CS must be at logical zero to enable the reading and writing of data to and
from the device. The lOR, lOG and lOB outputs are forced to the black level while CS is at logical zero. Note that the
ADV453 will not operate properly if CS, RD and WR are simultaneously at logical zero.
Write control input (TTL compatible). CS and WR must botb be at logical zero when writing data to the device. Do-D7
data is latched on the rising edge of WR or CS. See Figure I.
Read control input (TTL compatible). CS and RD must botb be at logical zero when reading data from the device. See
Figure I.
CO,CI
Command control inputs (TTL compatible). CO and CI specify the type of read or write operation being carried out,
i.e., address register, color palette RAM or overlay registers read or write operations. See Tables I, II, III.
Do-D7
Data bus (TTL compatible). Data is transferred to and from tbe address register, the color palette RAM and the overlay
registers over this 8-bit bidirectional data bus. DO is the least signillcant bit.
DIGITAL-TO-ANALOG CONVERTERS 2-425
•
TERMINOLOGY
BlaDking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Color Video (RGB)
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may
be visually observed.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels while a 6-bit DAC contains 64.
Sync Level
The peak level of the SYNC signal.
ADV453 CIRCUIT DESCRIPTION
MPU Interface
As illustrated in the functional block diagram, the ADV453
supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers.
The color palette RAM and overlay color registers can be accessed only when CS is low. The Pixel and Overlay Select inputs are disabled while CS is low.
The CO and CI control inputs specify whether the MPU is accessing the address register, color palette RAM or the overlay
registers, as shown in Table I. The 8-bit address register is used
to address the color palette RAM and overlay registers, eliminating the requirement for external address multiplexers.
CS
Cl
CO
Addressed by MPU
0
0
0
X
0
I
0
I
I
Address Register
Color Palette RAM
Overlay Register
Table I. Control Input Truth Table
2-426 DIGITAL-TO-ANALOG CONVERTERS
To write color data, the MPU writes to the address register with
either the address of the color palette RAM location or the address of the overlay register which is to be modified. The MPU
performs three successive write cycles (8 bits of red data, 8 bits
of green data and 8 bits of blue data). This color data is diverted
to either the color palette RAM or the overlay registers, as determined by CO and C 1. During the blue write cycle, the three
bytes of color information are concatenated into a 24-bit word
and written to the location specified by the address register. The
address register then automatically increments to the next location which the MPU may modify by simply writing another sequence of red, green and blue data.
To read back color data, the MPU loads the address register
(selecting RAM or overlay read mode) with the address of the
color palette RAM location or overlay register to be read. The
MPU performs three successive read cycles (8 bits each of red,
green and blue data), using CO and CI to select either the color
palette RAM or the overlay registers. Following the blue read
cycle, the address register increments to the next location which
the MPU may read by simply reading another sequence of red,
green and blue data.
When CS is low, i.e., during MPU read/write cycles, the video
outputs are forced to the black level. During color palette RAM
access, the address register resets to OOH following a blue read
or write operation to RAM location FFH.
ADV453
To keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in Table II. They are reset to
zero when the MPU writes to the address register and are not
reset to zero when the MPU reads the address register. The
MPU does not have access to these bits. The other eight bits of
the address register, incremented following a blue read or write
cycle, (ADDR0-7) are accessible to the MPU and are used to
address color palette RAM locations and overlay registers, as
shown in Table III. ADDRO is the LSB when the MPU is accessing the RAM or overlay registers. The MPU may read the
address register at any time without modifying its contents or
the existing read/write mode.
The three overlay registers can be accessed in the same way as
the color palette RAM. The overlays are selected using CO and
CI according to Table I. When accessing the overlay color registers, the address register increments following a blue read or
write cycle. However, while accessing the overlay color registers,
the six most significant bits of the address register (ADDRZ-7)
are ignored.
The MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM/overlay registers
and the color registers (R, G and B in the block diagram) are
synchronized by intemallogic and occur in the period between
MPU accesses. Color (RGB) data is normally loaded to the color
palette RAM/overlay registers during video screen retrace, i.e.
during the video waveform blanking period (see Figure 5).
Figure I illustrates the MPU read/write timing and Table III
shows the associated functional instructions.
Value
CI
CO
Addressed by MPU
ADDRa,b (Counts Modulo 3)
00
01
10
X
X
X
I
I
I
Red Value
Green Value
Blue Value
ADDR0-7 (Counts Binary)
OOH-FFH
XXXXXXOO
XXXXXXOI
XXXXXXIO
XXXXXXll
0
I
I
I
I
I
I
I
I
I
Color Palette RAM
Reserved
Overlay Color I
Overlay Color 2
Overlay Color 3
Note: Control input Cl determines whether a read/write operation is performed on the color
palette RAM or the overlay registers.
Table II. Address Register (ADDR) Operation
CS
RD
WR
CO
CI
ADDRb
ADDRa
Operation Performed
0
I
0
0
X
X
X
Write Address Register;
DO-D7~ADDR0-7
O~ADDRa,b
0
0
0
I
I
I
0
0
0
I
I
I
X
X
X
0
0
0
0
0
0
0
0
0
0
I
I
I
I
0
I
I
I
0
0
0
X
1
0
I
0
Write Red Value;
Write Green Value;
Write Blue Value;
Increment ADDRa-b
Increment ADDRa-b
Modify RAM/Overlay Location
Increment ADDR0-7
Increment ADDRa-b
X
X
X
X
X
0
0
I
X
0
I
0
Read Address Register;
Read Red Value;
Read Green Value;
Read Blue Value;
Increment ADDRa-b
ADDR0-7-+DO-D7
Increment ADDRa-b
Increment ADDRa-b
Increment ADDR0-7
X
X
X
Invalid Operation
Note: Control input Cl determines whether a read/write operation is performed on the color palette RAM or the overlay registers.
Table III. Truth Table for ReadIWrite Operations
DIGITAL-TO-ANALOG CONVERTERS 2-427
•
Frame Buffer Interface
The PO-P7, OLO and OLl inputs are used to address the color
palette RAM and overlay registers, as shown in Table IV. These
inputs are latched on the rising edge of CLOCK and address
any of the 256 locations in the color palette RAM or the three
overlay registers. The addressed location contains 24 bits of
color (8 bits of red, 8 bits of green and 8 bits of blue) information. This data is transferred to the three DACs and is then converted to an analog output (lOR, lOG and lOB), these outputs
then control the red green and blue electron guns in the
monitor.
The SYNC and BLANK inputs are also latched on the rising
edge of CLOCK. This is to maintain synchronization with the
color data.
OLl
OLO
PO-P7
Addressed by Frame Buffer
o
o
o
o
OOH
Color Palette RAM Location OOH
OIH
Color Palette RAM Location OIH
o
o
o
FFH
XXH
XXH
XXH
Color Palette RAM Location FFH
Overlay Color I
Overlay Color 2
Overlay Color 3
1
I
o
1
The red, green and blue analog outputs of the ADV453 are high
impedance current sources. Each one of these three RGB current outputs is capable of directly driving a 37.50 load, such as
a doubly terminated 750 coaxial cable. Figure 4a shows the required configuration for each of the three RGB outputs connected into a doubly terminated 750 load. This arrangement
will develop RS-343A video output voltage levels across a 750
monitor. A simple method of driving RS-170 video levels into a
750 monitor is shown in Figure 4b. The output current levels
of the DACs remain unchanged, but the source termination resistance, Zs, on each of the three DACs is increased from 750
to 1500.
More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is
available in an application note entitled "Video Formats & Required Load Terminations" available from Analog Devices.
Figure 5 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 750 load of Figure
4a. As well as the grey scale levels, Black Level to White Level,
the diagram also shows the contributions of SYNC and
BLANK. These control inputs add appropriately weighted currents to the analog outputs producing the specific output level
requirements for video applications. Table V details how the
SYNC and BLANK inputs modify the output levels.
lOR, lOG, lOB
Table IV. Pixel and Overlay Control Truth Table
DACs
Analog Interface
The ADV453 has three analog outputs, corresponding to the
red, green and blue video signals. A fourth analog output
(ISYNC) can be used if it is required to encode video synchronization information onto the green signal. In this case, I SYNC is
connected to lOG as shown in Figure 3. If it is not required to
encode sync information onto the green signal (as would be the
case if a separate synchronization circuit was used), ISYNC
should be connected to GND and the digital SYNC input pin
should be tied low.
r-~r--{~=:~~~~
(CABLE)
I
I
I
I
I
ZL =75ll
(MONITOR)
Zs=7511
(SOURCE TERMINATION)
Figure 4a, Recommended Analog OutputTermination for
RS-343A
-
lOR, lOG, lOB
----------,
Zo=75ll
Z.=150ll
(SOURCE TERMINATION)
Zo=75ll
(CABLE)
ZL =75ll
(MONITOR)
~--~RED
Figure 4b, Recommended Analog Output Termination for
RS-170
F~-_BLUE
Figure 3. Encoding SYNC onto Green Signal
2-428 DIGITAL-TO-ANALOG CONVERTERS
ADV453
RED,BWE
GREEN
mA
V
mA
V
19.05
0.714
26.67
1.000
-.----"..-----------"7'...---- WHITE LEVEL
1.44
0.054
9.05
0.340
~-----__\----f_-------- BLACK LEVEL
o
0
7.62
0.286
~----------~~r_~-L----------------BLANKLEVEL
o
o
~------------~~L-------------------SYNCLEVEL
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 750 LOAD.
2. VAEF = 1.235V, RSET = 2800, ISYNC CONNECTED TO lOG.
3. RS'-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 5. RGB Video Output Waveform
lOG
lOR, lOB
Description
mAl
mA
SYNC
BLANK
DAC
Input Data
White Level
Video
Video to Blank
Black Level
Black to Blank
Blank Level
SYNC Level
26.67
Video + 9.05
Video + 1.44
9.05
1.44
7.62
0
19.05
Video + 1.44
Video + 1.44
1.44
1.44
0
0
I
I
0
I
0
I
0
I
I
I
I
I
0
0
FFH
Data
Data
OOH
OOH
XXH
XXH
NOTES
'Typical with full scale lOG = 26.67mA.
VREF = 1.23SV, RsET=28on, I syNC connected to lOG.
Table V. Video Output Truth Table
PC BOARD LAYOUT CONSIDERATIONS
The ADV453 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV453, it is imperative that
great care be given to the PC board layout. The layout should
be optimized for lowest noise on the ADV453 power and ground
lines. This can be achieved by shielding the digital inputs and
providing good decoupling. The lead length between groups of
VAA and GND pins should by minimized so as to minimize inductive ringing.
Ground Planes
The ground plane should encompass all ADV453 ground pins,
voltage reference circuitry, power supply bypass circuitry, the
analog output traces and all the digital signal traces leading up
to the ADV453.
Power Planes
The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV453 (VAA) and all associated analog circuitry. This power plane should be connected to
the regular PCB power plane (Vee) at a single point through a
ferrite bead, as illustrated in Figure 6. This bead should be
located within three inches of the ADV453.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV453 power pins, voltage reference circuitry and
any output amplifiers.
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
DIGITAL-TO-ANALOG CONVERTERS 2-429
•
L1 (FERRITE BEAD)
..........._+5V(Vcc )
C5
C1
Z1
ADV453
~---'--~~'--1_-1~_------~-GROUND
R1
R2
R3
1
~AruU~
IOR~-------4---r--;---~-lOG
ISYNC
V11~O
CONNECTOR
J---......J
IOBJ-----------------------COMPONENT
DESCRIPTION
VENDOR PART NUMBER
C1-C6
C7
L1
R1. R2. R3
O.1 ...F CERAMIC CAPACITOR
10...F TANTALUM CAPACITOR
FERRITE BEAD
75(11% METAL FILM RESISTOR
280n 1% METAL FILM RESISTOR
1.235V VOLTAGE REFERENCE
FAIR-RITE 2743001111
DALE CMF-55C
DALE CMF-55C
ANALOG DEVICES AD589KH
RSET
Z1
Figure 6. ADV453 Typical Connection Diagram and Component List
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 6).
Optimum performance is achieved by the use of O.I ... F ceramic
capacitors. Each of the three groups of VAA should be individually decoupled to ground. This should be done by placing the
capacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
It is important to note that while the ADV453 contains circuitry
to reject power supply noise; this rejection decreases with frequency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) will provide
EMI supression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three-terminal voltage regulator.
Digital Signal Interconnect
The digital signal lines to the ADV453 should be isolated as
much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power
plane.
Due to the high clock rates used, long clock lines to the
ADV453 should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (Vcc), and
not the analog power plane.
Analog Signal Interconnect
The ADV453 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due
to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high frequency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 750. This termination resistance should be as close as possible to the ADV453 to
minimize reflections.
2-430 DIGITAL-TO-ANALOG CONVERTERS
r.ANALOG
WDEVICES
FEATURES
Personal System/2* and VGA* Compatible
Plug-in Replacement for INMOS 171/176
66MHz Pipelined Operation
Three 6-Bit D/A Converters
256x18 Color Palette RAM
RS-343A/RS-170 Compatible Outputs
Blank on All Three Channels
Standard MPU Interface
Asynchronous Access to All Internal Registers
+5V CMOS Monolithic Construction
Low Power Dissipation
Standard 28-Pin. 0.6" DIP
APPUCATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66MHz
50MHz
35MHz
GENERAL DESCRIPTION
The ADV476 is a pin compatible and software compatible
RAM-DAC designed specifically for VGA and Personal
Systeml2 color graphics.
Monolithic 256 x 18
CMOS Color Palette RAM-DAC
ADV476 I
ADV476 FUNCTIONAL BLOCK DIAGRAM
v.. (GND)
DO
D7
AD Wii RSO RS,
PRODUCT HIGHUGHTS
1. Standard video refresh rates, 35MHz, 50MHz and 66MHz.
2. Fully compatible with VGA and Personal Systeml2 color
graphics.
3. Guaranteed monotonic. Integra! and differential linearity
guaranteed to be a maximum of ± lLSB.
4. Low glitch energy, 75pV secs.
The ADV476 is a complete analog output RAM-DAC on a single monolithic chip. The part contains a 256x 18 color lookup
table, a pixel mask register as well as a triple 6-bit video D/A
converter. The ADV476 is capable of simultaneously displaying
up to 256 colors, from a total color palette of 262,144 addressable colors.
The on-chip asynchronous MPU bus allows access to the color
lookup table without affecting the input video data via the pixel
port. The pixel read mask register provides a convenient way of
altering the displayed colors without updating the color lookup
table. The ADV476 is capable of generating RGB video output
signals which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
The ADV476 is fabricated in a +5V CMOS process. Its monolithic CMOS construction ensures greater functionality with low
power dissipation and small board area. The part is packaged in
a 0.6", 28-pin DIP.
*Penoaal Systeml2 and VGA are trademarks of Intematioaal Business
Macbines Corp.
DIGITAL-TO-ANALOG CONVERTERS 2-431
•
SPECIFICATIONS
Parameter
(Vee = +5V ::t: 10%,
IREF = B.BBmA.
All Specifications Tmin to Tma.1 unless otherwise noted.)
AU Versions
Units
6
Bits
±O.S
±S
±O.S
±O.S
LSB max
% max
LSBmax
LSBmax
DIGITAL INPUTS
Input High Voltage, V1NH
Input Low Voltage, VINL
Input Current, lIN
Input Current (RD Input Only)
Input Capacitance, C1N
2
0.8
±10
±100
7
V min
V max
...,A max
...,A max
pF typ
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
2.4
0.4
±50
7
V min
V max
...,A max
pFtyp
ISOURCE= SOO...,A, Vee=4.SV
ISINK= S.OmA, Vee=4.SV
Vee =5.5V,0.4VADDRa,b
ADV476
Frame Buffer Interface
The PO-P7 inputs are used to address the color palette RAM, as
shown in Table IV. These inputs are latched on the rising edge
of PCLK and address any of the 256 locations in the color palette RAM. The addressed location contains 18 bits of color (6
bits of red, 6 bits of green and 6 bits of blue) information. This
data is transferred to the three DACs and is then converted to
an analog output (RED, GREEN, BLUE), these outputs then
control the red, green and blue electron guns in the monitor.
The BLANK input is also latched on the rising edge of PCLK.
This is to maintain synchronization with the color data.
This pixel masking operation can be used to alter the displayed
colors without changing the contents of either the video frame
buffer or the color palette RAM. The effect of this operation is
to partition the color palette into a user determined number of
color planes. This process can be used for special effects including animation, overlays and flashing objects.
PO _ _ _n
P7
PO-P7
Addressed by Frame Buffer
OOH
OIH
Color Palette RAM Location OOH
Color Palette RAM Location OIH
FFH
Color Palette RAM Location FFH
PIXEL
READ
MASK
REGISTER
,
:
---u
COLOR
PALETTE
RAM
Table IV. Pixel Select/Color Palette Control Truth Table
Pixel Read Mask Register
The Pixel Read Mask Register in the ADV476 can be used to
implement register level pixel processing, thereby cutting down
on software overhead. This is achieved by gating the input pixel
stream (PO-P7) with the contents of the pixel read mask register. The operation is a bitwise logical ANDing of the pixel data.
The contents of this register can be accessed and altered at any
time by the MPU (DO-D7). Table I shows the relevant control
signals.
Figure 3. Block Diagram Showing Pixel Read Mask Register
Analog Interface
The ADV476 has three analog outputs, corresponding to the
Red, Green and Blue video signals.
tance, Zs, on each of the three DACs is increased from 750 to
1500.
The Red, Green and Blue analog outputs of the ADV476 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.50 load, such
as a doubly-terminated 750 coaxial cable. Figure 4a shows the
required configuration for each of the three RGB outputs connected into a doubly-terminated 750 load. This arrangement
will develop RS-343A video output voltage levels across a 750
monitor. A simple method of driving RS-170 video levels into a
750 monitor is shown in Figure 4b. The output current levels
of the DACs remain unchanged but the source termination resisRED,GREEN,BLUE
00---07
More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is
available in an application note entitled "Video Formats &
Required Load Terminations" available from Analog Devices.
Figure 5 shows the video waveforms associated with the three
RGB outputs, driving the doubly terminated 750 load of Figure 4a. The BLANK control input drives the analog outputs to
the Black Level. BLANK is asserted prior to horizontal and
vertical screen retrace. Table V details how the BLANK input
modifies the output levels.
-
RED, GREEN, BLUE
Zo=7S,n
(CABLE)
Zs=7S,n
BIOIRECTIONALMPU DATA BUS
Z.=7S,n
(MONITOR)
(SOURCE
TERMINATION)
Figure 4a. Recommended Analog Output Termination for
RS-343A
Zs=1S0,n
Zo=7S,n
(CABLE)
Z.=7S,n
(MONITOR)
(SOURCE
TERMINATION)
Figure 4b. Recommended Analog Output Termination for
RS-170
DIGITAL-TO-ANALOG CONVERTERS 2-437
mA
V
19.05
0.714
0.00
0.000
-r---::"'"-----------~~--- WHITE LEVEL
......._ _ _ _ _ _....L._ _ _- - " ' - -_ _ _ _ _ _ _ _
BLACK/BLANK
LEVEL
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 750 LOAD.
2. IREF =8.88mA.
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 5. RGB Video Output Waveform
Description
RED,GREEN,
BLUE, (mA)l
BLANK
WHITE LEVEL
VIDEO
BLACK LEVEL
BLANK LEVEL
19.05
Video
0
0
1
1
1
0
DAC
Input Data
FFH
DATA
OOH
xxH
NOTE
'Typical with full scale RED, GREEN, BLUE = 19.0SmA. I REF =8.88mA.
Table V. Video Output Truth Table
Reference Input
The ADV476 requires an active current reference to enable tbe
DACs provide stable and accurate video output levels. The rela·
tionship between tbe output voltage and tbe required input ref·
erence current is given by:
IREF
= 37.50
= 750
where
RL
and
VO = 0.714V
=
2-438
l.OV
VO (FULL SCALE)
In a standard application which requires RS· 343A video levels to
be driven into a doubly terminated 750 load (RL = 37.50), tbe
necessary reference input current is:
IREP =8.88mA.
To drive tbe same levels into a singly terminated 750 load
(RL = 750), tbe reference current is:
I REP =4.44mA.
(for doubly terminated 750 load)
(for singly terminated 750 load)
(RS-343A video levels)
(RS·170 video levels).
DIGITAL~TO·ANALOG
CONVERTERS
A suggested current reference design for the doubly terminated
case, witb RS-343A video levels and based on tbe LM334, a
tbree-terminal adjustable current source, is shown in. Figure 6.
ADV476
,....-----~
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV476 power pins, current reference circuitry
and any output amplifiers.
IREF
v+
CURRENT
SOURCE
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
R
LM334
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors, see Figure 7.
R1
150
CR1
IN4148
R2
1500
Figure 6. Current Reference Design Using an LM334
Current Source
PC BOARD LAYOUT CONSIDERATIONS
The ADV476 is optimally designed for lowest noise performance, both radiated and conducted noise. For optimum system
noise performance, it is imperative that great care be given to
the PC board layout. The layout should be optimized for lowest
noise on the ADV476 power and ground lines. This can be
achieved by shielding the digital inputs and providing good
decoupling. The lead length between groups of Vee and GND
pins should by minimized so as to minimize inductive ringing.
Ground Planes
The ground plane should encompass all ADV476 ground pins,
voltage reference circuitry, power supply bypass circuitry, the
analog output traces and all the digital signal traces leading up
to the ADV476.
Power Planes
The PC board layout should have two distinct power planes, one
for analog circuitry and one for digital circuitry. The analog
power plane (Vee) should encompass the ADV476 and all associated analog circuitry. This power plane should be connected to
the regular PCB power plane at a single point through a ferrite
bead, as illustrated in Figure 7. This bead should be located
within three inches of the ADV476.
Optimum performance is achieved by the use of O.IfJ.F ceramic
capacitors. Thi~ should be done by placing the capacitors as
close as possible to the device with the capacitor leads as short
as possible, thus minimizing lead inductance.
It is important to note that while the ADV476 contains circuitry
to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNXOO2) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three terminal voltage regulator.
Digital Signal Interconnect
The digital signal lines to the ADV476 should be isolated as
much as possible from the analog outputs and other analog circuitry. Digital signal lines. should not overlay the analog power
plane.
Due to the high clock rates used, long clock lines to the
ADV476 should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane and not
the analog power plane.
Analog Signal Interconnect
The ADV476 shoilld be located as close as possible to the output connectors thus minimizing lioise pickup and reflections due
to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high frequency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 750. This termination resistance should be as close as possible to the ADV476 to
minimize reflections.
DIGITAL-TO-ANALOG CONVERTERS 2-439
•
ANALOG POWER PLANE
V~~. . . . . . . . . . . . . .~. . . . . . . . . .~
L1 (FERRITE BEAD)
l-...~-- +5V (PCB POWER PLANE)
IREF
I"----t-----.
C1
ADV476
GND
GROUND
R1
R2
R3
RED~---~~-t--r-~-----
GREEN~------l-~-~~~~
BLUE I-------!.-~~~
TO
VIDEO
CONNECTOR
COMPONENT
DESCRIPTION
VENDOR PART NUMBER
C1-c4
C5
C6
L1
R1. R2. R3
O.1,..F CERAMIC CAPACITOR
10,..F TANTALUM CAPACITOR
47,..F TANTALUM CAPACITOR
FERRITE BEAD
7501% METAL FILM RESISTOR
ERIE RPE112Z5U104M50V
MALLORY CSR13G106KM
MALLORY CSR13F476KM
FAIR-RITE 2743001111
DALE CMF-55C
Figure 7. ADV476 Typical Connection Diagram and Component List
2-440 DIGITAL-TO-ANALOG CONVERTERS
11IIIIIIII ANALOG
WDEVICES
CMOS 80MHz Monolithic 256 x 24(18)
Color Palette RAM-OAC
AOV478/AOV471 I
FEATURES
Personal System/2* Compatible
80MHz Pipelined Operation
Triple 8-Bit (6-Bit) D/A Converters
256x24(18) Color Palette RAM
15 x 24(18) Overlay Registers
RS-343A1RS-170 Compatible Outputs
Sync on All Three Channels
Programmable Pedestal (0 or 7.5 IRE)
External Voltage or Current Reference
Standard MPU Interface
+ 5V CMOS Monolithic Construction
44-Pin PLCC Package
Power Dissipation: 800mW
ADV478/ADV471 FUNCTIONAL BLOCK DIAGRAM
II
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
80MHz
66MHz
50MHz
35M Hz
GENERAL DESCRIPTION
The ADV478 and ADV471 are pin compatible and software
compatible RAM-DACs designed specifically for Personal
Systeml2 compatible color graphics.
The ADV478 has a 256 x 24 color lookup table with triple 8-bit
video D/A converters. It may be configured for either 6 bits or
8 bits per color operation. The ADV471 has a 256 x 18 color
lookup table with triple 6-bit video D/A converters.
NOTES
1, NUMBERS IN PARENTHESIS INDICATE PIN NAMES FOR THE ADV471.
2. NC = NO CONNECT
Options on both parts include a programmable pedestal (0 or
7.5 IRE) and use of an external voltage or current reference.
Fifteen overlay registers provide for overlaying cursors, grids,
menus, EGA emulation, etc. Also supported is a pixel read
mask register and sync generation on all three channels.
The ADV478 and ADV471 generate RS-343A compatible video
signals into a doubly terminated 750 load, and RS-170 compatible
video signals into a singly terminated 750 load, without requiring
external buffering. Differential and integral linearity errors are
guaranteed to be a maximum of ± lLSB for the ADV478 and
± 1I4LSB for the ADV471 over the full temperature range.
·Personal Systeml2 is a trademark of International Business Machines
Corp.
DIGITAL-TO-ANALOG CONVERTERS 2-441
SPEC IFI CATIONS
Parameter
(VM1 =
+5V,SElUP=&i=V.. vAIF = + 1.235V. Rsa=147o. All SpecificationsT.. tu T....2 unless otherwise noIIIII.l
All Versions
Units
8(6)
Bits
± 1 (114)
± 1 (114)
±5
Binary
LSBmax
LSBmax
% Gray Scale max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, V INL
Input Current, liN
Input Capacitance, CIN
2
0.8
±1
7
V min
V max
...,A max
pFmax
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
2.4
0.4
50
7
V min
V max
...,A max
pFmax
20
mAmax
17.69
20.40
16.74
18.50
0.95
1.90
0
50
6.29
8.96
0
50
69.1 (279.68)
5
-I
+ 1.5
10
30
rnA min
mAmax
mAmin
mAmax
rnA min
rnA max
...,A min
...,A max
mAmin
rnA max
",A min
",A max
",Atyp
% max
V min
V max
kOtyp
pFmax
1.14/1.26
10
V minIV max
",Atyp
4.75/5.25
4.50/5.50
220
0.5
1100
VminlVmax
VminlVmax
mAmax
%/%max
mWmax
-30
75
-23
dBtyp
pVsecstyp
dBtyp
STATIC PERFORMANCE
Resolution (Each DAC)~
Accuracy (Each DAC?
Integral Nonlinearity
Differential N on1inearity
Gray Scale Error
Coding
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
(SETUP = VAA)
Black Level Relative to Blank
(SETUP = GND)
Blank Level
Sync Level
LSBSize3
DAC to DAC Matching
Output Compliance, V DC
Output Impedance, Rour
Output Capacitance, Cour
VOLTAGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
POWER SUPPLY
Supply Voltage, VAA
Supply Current, lAA
Power Supply Rejection Ratio
Power Dissipation
DYNAMIC PERFORMANCE
Clock and Data Feedthrough4 •s
Glitch Impulse4 •s
DAC to DAC Crosstalk6
Test Conditions/Comments
Guaranteed Monotonic
V IN = 0.4V or 2.4V
IsoURCE = 4OO",A
ISINK = 3.2mA
Typically 19.05mA
Typically 17.62mA
Typically l.44mA
Typically 5",A
Typically 7.62mA
TypicaUy5...,A
8/6 = Logical I for ADV478
Typically 2%
Iour=OmA
Tested in Voltage Reference
Conflguration with VREF = 1.235V
80MHzParts
50MHz and 35MHz Parts
Typically 180mA
f= lkHz,COMP=O.l",F
Typically 900mW, VAA = 5V
NOTES
I ± 5% for SOMHz partS; ± 10% for 66MHz, 50MHz and 35MHz parts.
'Temperature Range (Tm;n to T ~,); 0 to + 7O"C.
'Numbers in parentheses indicate AOV471 parameter value.
'Clock and data feedthrough is. function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a
Ikfl resistor to ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, - 3dB test bandwidth = 2 x clock rate.
'TTL input values are 0 to 3 volts, with input rise/faU tim.. S3DS, measured betweeD the 10% and 90% points. Timing reference points at 50%
for inputs and outputs. Ana10g output load "'IOpF, DO - 07 output load s5OpF. See timing notes in Figure 2.
60AC to OAC crosstalk is measured by holding one OAC high while the other two are making low to high and high to low transitions.
Specif1C8tiOns subject to change without DOtice.
2-442 DIGITAL-TO-ANALOG CONVERTERS
ADV478/ADV471
Parameter
KP80Version
KP66 Version
KPSOVersion
KP35 Version
Units
ConditionslComments
fmax
80
10
10
5
40
20
10
10
50
4Xtl2
3
3
12.5
4
4
30
3
13
2
4Xt l2
66
10
10
5
40
20
10
10
50
4Xtl2
3
3
15.3
5
5
30
3
15.3
2
4Xt l2
50
10
10
5
40
20
10
10
50
4Xtl2
3
3
20
6
6
30
3
20
2
4Xt l2
35
15
15
5
40
20
15
15
50
4Xtl2
4
4
28
7
9
30
3
28
2
4Xt l2
MHz
nsmin
nsmin
nsmin
nsmax
nsmax
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmax
nstyp
nstyp
nsmax
nsmin
Clock Rate
RSO - RS2 Setup Time
RSO - RS2 Hold Time
RD Asserted to Data Bus Driven
RD Asserted to Data Valid
RD Negated to Data Bus 3-Stated
Write Data Setup Time
Write Data Hold Time
RD, WR Pulse Width Low
RD, WR Pulse Width High
Pixel and Control Setup Time
Pixel and Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output RiselFall Time
Analog Output Settling Time
Analog Output Skew
Pipeline Delay
tl
t2
t3
4
ts
t6
t7
t8
t9
t\O
til
tl2
tl3
tl4
tiS
tl6
tl74
tiS
tpo
NOTES
'TIL input values are 0 to 3 voits, with input riselfali times :s;3ns, measured between the 10% and 90% points. Timing reference
points at 50% fot inputs and outputs. Analog output ioad :s;IOpF, 37.S0. DO - D7 output ioad :S;SOpF. See timing notes in Figure 2.
2 ± 5% for BOMHz parts; ± 10% fot 66MHz, 50MHz and 3SMHz parts.
'Temperature Range (T.... to T _x); 0 to + 70,,{;.
'Settling time does not include clock and data feedthrough. For this test, the digital inputs have a lkn resistot to ground and are
driven by 74HC iogic.
Specifications subject to change without notice
TIMING DIAGRAMS
READIDO-D7)
----------~~::~~SS~==========t:~J---------------
Figure 1. MPU Read/Write Timing
-r
CLDCK
,---=-+-.....
PO - P7, OLO- OL3, .....~,............~~............,.......,.
,(~SS9f~~~~~SS§
SYNC,BLANK ~~~~,~~~~~~~~~~~--~~~~~
t
IOR,IOG,IOB _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
,.
t"
t,.
NOTES
1. OUTPUT DELAY It,.) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO
THE 50% POINT OF FULL SCALE TRANSISTION.
2. SETTLING TIME It,,) MEASURED FROM THE 50% POINT OF FULL SCALE TRANSITION TO THE
OUTPUT REMAINING WITHIN ± 1LSB IADV478) OR ± 1/4LSB IADV471).
3. OUTPUT RISE/FALL TIME It,.) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL SCALE
TRANSITION.
Figure 2. Video Input/Output Timing
DIGITAL-TO-ANALOG CONVERTERS 2-443
•
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power Supply
80MHzParts
50, 35MHzParts
Ambient Operating Temperature
Output Load
Voltage Reference Configuration
Reference Voltage
Current Reference Configuration
Reference Current
VAA
TA
RL
Min
Typ
Max
Units
4.75
4.5
0
5.00
5.00
5.25
5.5
+70
Volts
Volts
OC
1.26
Volts
-10
rnA
n
37.5
VREF
1.14
lREF
-3
1.235
CAUTION
ESD (electrostatic discharge) sensltlve device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
PLCC PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS·
VAA to GND
. . . . . . . . . . . . . . . . . . . . . +7V
Voltage on Any Digital Pin
GND - 0.5V to VAA + 0.5V
Ambient Operating Temperature (TA)
-55°C to + 125°C
Storage Temperature (Ts) . . • .
- 65°C to + 150°C
Junction Temperature (TJ )
.,
+ 1750C
Vapor Phase Soldering (2 minutes)
.. TBD
lOR, lOB, lOG to GNDI . . . . .
OV to VAA
NOTES
*Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
I Analog output sbort circuit to any power supply or common can be of an
indefmite duration.
ADV478/ADV471
TOP VIEW
INot to Scale)
29 COMP
NOTES
1, NUMBERS IN PARENTHESIS INDICATE PIN NAMES FOR THE ADV471.
2. Ne = NO CONNECT
ORDERING INFORMATION1 ,
2
Speed
Color Palette
RAM
80MHz
66MHz
SOMHz
3SMHz
Package
Options3
256x 1,8
ADV471KP80 ADV471 KP66 ADV471KP50 ADV471KP35 P-44A
256x24
ADV478KP80 ADV478KP66 ADV478KP50 ADV478KP35 P-44A
NOTES
'All devices are packaged in a 44-pin plastic leaded U-lead) cbip carrier, PLCC.
2All devices are specified for 0 to + 70'C operation.
'See Section 14 for package outline information.
2-444 DIGITAL-TO-ANALOG CONVERTERS
ADV4 78/ADV4 71
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
Composite blank control input (TTL compatible). A logic zero drives the analog outputs to the blanking level
as illustrated in Tables IV and V. It is latched on the rising edge of CLOCK. When BLANK is a logical zero,
the pixel and overlay inputs are ignored
SETUP
Setup control input. Used to specify either a 0 IRE (SETUP = GND) or 7.5 IRE (SETUP = VAA)
blanking pedestal.
SYNC
Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current
source on the analog outputs (see Figures 3 and 4). SYNC does not override any other control or data input,
as shown in Tables IV and V; therefore, it should be asserted only during the blanking interval. It is latched
on the rising edge of CLOCK.
CLOCK
Clock input (TTL compatible). The rising edge of CLOCK latches the PO - P7, OLO - OL3, SYNC, and
BLANK inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be
driven by a dedicated TTL buffer.
PO - P7
Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in
the color palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK.
PO is the LSB. Unused inputs should be connected to GND.
OLO - OL3
Overlay select inputs (TTL compatible). These inputs specify which palette is to be used to provide color
information, as illustrated in Table III. When accessing the overlay palette, the PO - P7 inputs are ignored.
They are latched on the rising edge of CLOCK. OLO is the LSB. Unused inputs should be connected to
GND.
lOR, lOG, lOB
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 750 coaxial cable (Figures 5 and 6).
IREF
Full-scale adjust control. Note that the IRE relationships in Figures 3 and 4 are maintained, regardless of the
full-scale output current.
When using an external voltage reference (Figure 5), a resistor (RsET) connected between this pin and GND
controls the magnitude of the full-scale video signal. The relationship between RSET and the full-scale output
current on each output is:
RSET (0)= K
* 1,000 * VREF (V)/IOUT (mA)
K is defined in the table below, along with corresponding RSET values for doubly terminated 750 loads.
When using an external current reference (Figure 6), the relationship between IREF and the full-scale output
current on each output is:
IREF (mA)
=
lOUT (mA)/K
Mode
Pedestal
K
RsET(O)
6-Bit
8-Bit
6-Bit
8-Bit
7.5 IRE
7.5 IRE
OIRE
OIRE
3.170
3.195
3.000
3.025
147
147
147
147
CaMP
Compensation pin. If an external voltage reference is used (Figure 5), this pin should be connected to OPA. If
an external current reference is used, this pin should be connected to I REF . A 0.1 fLF ceramic capacitor must
always be used to bypass this pin to VAA.
V REF
Voltage reference input. If an external voltage reference is used (Figure 5), it must supply this input with a
1.2V (typical) reference. If an external current reference is used (Figure 6), this pin should be left floating,
except for the bypass capacitor. A O.lfLF ceramic capacitor must always be used to decouple this input to
VAA as shown in Figures 5 and 6.
OPA
Reference amplifier output. If an external voltage reference is used (Figure 5), this pin must be connected to
CaMP. When using an external current reference (Figure 6), this pin should be left floating.
Analog power. All VAA pins must be connected to the Analog Power Plane.
Analog ground. All GND pins must be connected to the Ground Plane.
Write control input (TTL compatible). DO - D7 data is latched on the rising edge of WR, and RSO - RS2 are
latched on the falling edge of WR during MPU write operations. See Figure 1.
DIGITAL-TO-ANALOG CONVERTERS 2-445
PIN FUNCTION DESCRIPTION (Continued)
Pin
Mnemonic
Function
RD
Read control input (TTL compatible). To read data from the device, RD must be a logical zero. RSO - RS2
are latched on the falling edge of RD during MPU read operations.
RSO, RSI, RS2
Register select inputs (TTL compatible). RSO - RS2 specify the type of read or write operation being performed
as illustrated in Tables I and II.
DO - D7
Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data
bus. DO is the least significant bit.
8/6
8-bit/6-bit select input (TTL compatible). This control input specifies whether the MPU is reading and writing
8-bits (logical one) or 6-bits (logical zero) of color information each cycle. For 8-bit operation, D7 is the most
significant data bit during color read/write cycles. For 6-bit operation, DS is the most significant data bit
during color read/write cycles (D6 and D7 are ignored during color write cycles and are logical zero during
color read cycles). This control input is implemented only on the ADV478.
TERMINOLOGY
Blanking Level
Raster Scan
The level seperating the SYNC ponion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the
picture tube, resulting in the blackest possible picture.
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Color Video (RGB)
This usually refers to the technique of combining the three
primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs would
be required, one for each color.
Composite SYNC Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Setup
The difference between the reference black level and the blanking
level.
SYNC Level
The peak level of the composite SYNC signal.
Composite Video Signal
The video signal with or without setup, plus the composite
SYNC signal.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different
levels while a 6-bit DAC contains 64.
2-446 DIGITAL-TO-ANALOG CONVERTERS
Video Signal
That ponion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may
be visually observed.
ADV478/ADV471
CIRCUIT DESCRIPTION
MPU Interface
As illustrated in the functional block diagram, the ADV478 and
ADV471 support a standard MPU bus interface, allowing the
MPU direct access to the color palette RAM and overlay color
registers.
To read color data, the MPU loads the address register (selecting
RAM or overlay read mode) with the address of the color palette
RAM location or overlay register to be read. The MPU performs
three successive read cycles (8 or 6 bits each of red, green and
blue), using RSO - RS2 to select either the color palette RAM
or overlay registers. Following the blue read cycle, the address
register increments to the next location which the MPU may
read by simply reading another sequence of red, green and blue
data.
The RSO - RS2 select inputs specify whether the MPU is accessing
the address register, color palette RAM, overlay registers or
read mask register, as shown in Table I. The 8-bit address
register is used to address the color palette RAM and overlay
registers, eliminating the requirement for external address
multiplexers.
When accessing the color palette RAM, the address register
resets to OOH following a blue read or write cycle to RAM location
FFH. When accessing the overlay color registers, the address
register increments following a blue read or write cycle. However,
while accessing the overlay color registers, the four most significant
bits of the address register (ADDR4 - 7) are ignored.
To write color data, the MPU writes to the address register
(selecting RAM or overlay write mode) with the address of the
color palette RAM location or overlay register to be modified.
The MPU performs three successive write cycles (8 or 6 bits
each of red, green and blue), using RSO - RS2 to select either
the color palette RAM or overlay registers. During the blue
write cycle, the three bytes of color information are concatenated
into a 24-bit word (l8-bit word for the ADV471) and written to
the location specified by the address register. The address register
then increments to the next location which the MPU may modify
by simply writing another sequence of red, green and blue data.
RS2
RSI
RSO
Addressed by MPU
0
0
0
0
0
0
0
Address Register (RAM Write Mode)
Address Register (RAM Read Mode)
Color Palette RAM
Pixel Read Mask Register
0
I
I
0
Address Register (Overlay Write Mode)
Address Register (Overlay Read Mode)
Overlay Registers
Reserved
I
0
0
I
0
I
The MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM/overlay registers
and the color registers (R, G and B in the block diagram) are
synchronized by internal logic and occur in the period between
MPU accesses. As only one pixel clock cycle is required to
complete the transfer, the color palette RAM and overlay registers
may be accessed at any time with no noticeable disturbance on
the display screen.
To keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in Table II. They are reset to
zero when the MPU writes to the address register and are not
reset to zero when the MPU reads the address register. The
MPU does not have access to these bits. The other eight bits of
the address register, incremented following a blue read or write
cycle (ADDRO - 7), are accessible to the MPU and are used to
address color palette RAM locations and overlay registers, as
shown in Table II. ADDRO is the LSB when the MPU is accessing
the RAM or overlay registers. The MPU may read the address
register at any time without modifying its contents or the existing
read/write mode.
Table I. Control Input Truth Table
Value
ADDRa,b (Counts Modulo 3)
00
01
10
ADDRO - 7 (Counts Binary)
OOH - FFH
XXXXOOOO
XXXXOOOI
XXXXOOIO
XXXXlll1
Figure I illustrates the MPU read/write timing.
RS2
RSI
RSO
Addressed By MPU
Red Value
Green Value
Blue Value
0
0
0
0
0
Color Palette RAM
Reserved
Overlay Color 1
Overlay Color 2
0
Overlay Color 15
Table II. Address Register (ADDR) Operation
DIGITAL-TO-ANALOG CONVERTERS 2-447
II
ADV478 Data Bus Interface
On the ADV478, the 8/6 control input is used to specify whether
the MPU is reading and writing 8 bits (8/6 = logical one) or 6
bits (8/6 = logical zero) of color information each cycle.
Frame Buffer Interface
The PO - P7 and OLO - OL3 inputs are used to address the
color palette RAM and overlay registers, as shown in Table III.
For 8-bit operation, DO is the LSB and D7 is the MSB of color
data.
For 6-bit operation (and also when using the ADV471), color
data is contained on the lower six bits of the data bus, with DO
being the LSB and D5 the MSB of color data. When writing
color data, D6 and D7 are ignored; During color read cycles,
D6 and D7 will be a logical zero.
ADV471 Data Bus Interface
Color data is contained on the lower six bits of the data bus,
with DO being the LSB and D5 the MSB of color data. When
writing color data, D6 and D7 are ignored. During color read
cycles, D6 and D7 will be a logical zero.
mA
OLO-OU
PO-P7
Addressed by Frame Buffer
OH
OH
OOH
OIH
Color Palette RAM Location OOH
Color Palette RAM Location OIH
OH
FFH
IH
XXH
2H
XXH
Color Palette RAM Location FFH
Overlay Color 1
Overlay Color 2
PH
XXH
Overlay Color 15
Table III. Pixel and Overlay Control Truth Table (Pixel Read
MaskRegister = FFH)
V
26.67 1.000
9.05
0.340
1.62
0.286
-r--""7"'r-------------,.~---
~------·}----~~--------BLACKLEVEL
r--'---------- BLANK LEVEL
. . . .________._01-__________
40 IRE
0.00
0.000
WHITE LEVEL
SYNC LEVEL
NOTES
1. CONNECTED WITH A 15(1 DOUBLY TERMINATED LOAD, SETUP = VAA•
2. EXTERNAL VOLTAGE OR CURRENT REFERENCE ADJUSTED FOR 26.61mA FULL-SCALE OUTPUT.
3. RS·343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. Composite Video Output Waveform (SETUP=VAA)
Description
loUT (mA)l
SYNC
BLANK
DAC
Input Data
WHITE LEVEL
DATA
DATA-SYNC
BLACK LEVEL
BLACK-SYNC
BLANK LEVEL
SYNC LEVEL
26.67
data + 9.05
data + 1.44
9.05
1.44
7.62
0
I
1
0
I
0
I
0
I
1
1
1
1
0
0
FFH
data
data
OOH
OOH
xxH
xxH
NOTES
'Typical with full-scale lOG = 26.67mA, SETUP = V AA'
External voltage or current reference adjusted for 26.67mA full-scale output.
Table IV. Video Output Truth Table (SETUP = VAA)
2-448 DIGITAL-TO-ANALOG CONVERTERS
ADV478/ADV471
the specific output levels required for video applications, as
illustrated in Figures 3 and 4. Tables IV and V detail how the
SYNC and BLANK inputs modify the output levels.
The contents of the pixel read mask register, which may be
accessed by the MPU at any time, are bit-wise logically ANDed
with the PO - P7 inputs. Bit DO of the pixel read mask register
corresponds to pixel input PO. The addressed location provides
24 bits (18 bits for the ADV471) of color information to the
three D/A converters.
The SETUP input is used to specify whether a 0 IRE (SETUP
= GND) or 7.5 IRE (SETUP = VAA) blanking pedestal is to
be used.
The analog outputs of the ADV478 and ADV471 are capable of
directly driving a 37.50 load, such as a doubly tenninated 750
coaxial cable.
The SYNC and BLANK inputs, also latched on the rising edge
of CLOCK to maintain synchronization with the color data, add
appropriately weighted currents to the analog outputs, producing
mA
V
26.67 1.000
8.05
......- - - - " . . - - - - - - - - - - - - - - - , " " " - - - WHITE LEVEL
.--J~
0.302
_ _ _ _ _ _ _ _ BLACK/BLANK
LEVEL
0.00
0.000
~-------~~
_ _ _ _ _ _ _ _ _ _ _ _ SYNCLEVEL
NOTES
1. CONNECTED WITH A 7SU DOUBLY TERMINATED LOAD, SETUP=GND.
2. EXTERNAL VOLTAGE OR CURRENT REFERENCE ADJUSTED FOR 26.67mA FULL' SCALE OUTPUT.
3. RS·343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 4. Composite Video Output Waveform (SETUP=GND)
Description
loUT (mA)l
SYNC
WHITE LEVEL
DATA
DATA-SYNC
BLACK LEVEL
BLACK-SYNC
BLANK LEVEL
SYNC LEVEL
26.67
data + 8.05
data
8.05
0
8.05
0
I
I
0
I
0
I
0
BLANK
I
DAC
Input Data
FFH
data
data
OOH
OOH
xxH
xxH
1
1
I
1
0
0
NOTES
'Typical with full-scale IOG = 26.67mA, SETUP = GND
External voltage or current reference adjusted for 26.67mA full-scale output.
Table V. Video Output Truth Table (SETUP= GND)
DIGITAL-TO-ANALOG CONVERTERS 2-449
•
PC BOARD LAYOUT CONSIDERATIONS
PC Board Considerations
The layout should be optimized for lowest noise on the ADV478/
ADV471 power and ground lines by shielding the digital inputs
and providing good decoupling. The lead length between groups
of VAA and GND pins should by minimized so as to minimize
inductive ringing.
Ground Planes
The ground plane should encompass all ADV478/ADV471 ground
pins, current/voltage reference circuitry, power supply bypass
circuitry for the ADV478/ADV471, the analog output traces and
aU the digital signal traces leading up to the ADV478/ADV471.
Power Planes
The ADV478/ADV471 and any associated analog circuitry should
have its own power plane, referred to as the analog power plane.
This power plane should be connected to the regular PCB power
plane (Vcd at a single point through a ferrite bead, as illustrated
in Figures 5 and 6. This bead should be located within three
inches of the ADV478/ADV471.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV478/ADV471 power pins and current/voltage
reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
For optimum performance, bypass capacitors should be installed
using the shortest leads possible, consistent with reliable operation,
to reduce the lead inductance.
Best performance is obtained with a O.l/LF ceramic capacitor
decoupling each of the two groups of V AA pins to GND. These
capacitors should be placed as close as possible to the device.
It is important to note that while the ADV478 and ADV471
contain circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reducing
power supply noise and consider using a three terminal voltage
regulator for supplying power to the analog power plane.
ANALOG POWER PLANE
1--.-". +5V (Veel
C1
GND~~--~---'--"'~~~-1~'-------~-----GROUND
ADV4781
ADV471
R1
REF
I
R2
R3
!----,
]
IOR~
TO
IOGi.---------------e---1r---t----
VIDEO
CONNECTOR
IOB~------------.-------
COMPONENT
C1-CS
C6
L1
R1,R2,R3
R4
Ran
Z1
DESCRIPTION
O.1 .... F Ceramic capacitor
1Op.F Tantalum Capacitor
ferrite Bead
150 1% Matel Film Resistor
1kO 5% Resistor
1% Matel Film Resistor
1.2V Voltage Referenc.
VENDOR PART NUMBER
Erie RPE112Z5U104M50V
MalloryCSR13G106KM
Fair·Rite 2143001111
Dale CMF·55C
Dale CMF-55C
Analog Devices AD589KH
Figure 5. Typical Connection Diagram and Component List
(External Voltage Reference)
2-450 DIGITAL-TO-ANALOG CONVERTERS
ADV478/ADV471
Digital Signal Interconnect
The digital inputs to the ADV478/ADV471 should be isolated
as much as possible from the analog outputs and other analog
circuitry. Also, these input signals should not overlay the analog
power plane.
Due to the high clock rates involved, long clock lines to the
ADV478/ADV471 'should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (Vee), and not the
analog power plane.
Analog Signal Interconnect
The ADV478/ADV471 should be located as close as possible to
the output connectors to minimize noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
For maximum performance, the analog outputs should each
have a 750 load resistor connected to GND. The connection
between the current output and GND should be as close as
possible to the ADV478/ADV471 to minimize reflections.
ADV4781
ADV471
IREF
"''''---+5V (Vccl
1'-....--+---....
Cl
. .--~--. . . .~~----. .______~~___ GROUND
GND~--
R1R2R3
]
IORr---._--i---;----+---
--+--1--
lOG 1 - - - -....
V11~O
CONNECTOR
IOB~-----_.~--
'----~
COMPONENT
Cl-CS
C6
C7
Ll
Rl.R2.R3
DESCRIPTION
0.1 f&.F Ceramic Capacitor
10p.FTantalum Capacitor
47p.FTantalum Capacitor
Ferrite Bead
7S0 1% Metal Film Resistor
VENDOR PART NUMBER
Erie RPE112ZSUI 04MSOV
Mallory CSR13Gl06KM
Mallory CSR13F476KM
Fair·Rite 2743001111
Dale CMF·SSC
Figure 6. Typical Connection Diagram and Component List
(External Current Reference)
APPLICATION INFORMATION
External Voltage vs. Current Reference
The ADV478/ADV471 is designed to have excellent performance
using either an external voltage or current reference. The voltage
reference design (Figure 5) has the advantages of temperature
compensation, simplicity, lower cost and provides excellent
power supply rejection. The current reference design (Figure 6)
requires more components to provide adequate power supply
rejection and temperature compensation (two transistors, three
resistors and additional capacitors).
RS-170 Video Generation
For generation of RS-170 compatible video, it is recommended
that the DAC outputs be connected to a singly terminated 75nIoad.
If the ADV478/ADV471 is not driving a large capacitive load,
there will be negligible difference in video quality between
doubly terminated 750 and singly terminated 750 loads.
If driving a large capacitive load (load RC> lI(21rfc)), it is recommended that an output buffer (such as a MC1378 with an
unloaded gain>2) be used to drive a doubly terminated 750
load.
DIGITAL-TO-ANALOG CONVERTERS 2-451
II
2-452 DIGITAL-TO-ANALOG CONVERTERS
~ANALOG
WDEVICES
High Resolution 16- and 18-Bit
Digital-to-Analog Converters
DACl136/DACl138
I
FEATURES
DAC1138
18-Bit Resolution and Accuracy (381lV, 1 Part in 262,144)
Nonlinearity 1/2LSB max (DAC1138K)
Excellent Stability
Settling to 1/2LSB (0_0002%) in 10llS
Hermetically-Sealed Semiconductors
DAC1136
16-Bit Resolution and Accuracy (152J.tV, 1 Part in 65,536)
Low Cost
Nonlinearity 1/2LSB max (DAC1136K, L)
Settling to 1/2LSB max (0_0008%) in SIts
DAC1l36IDAC1l38 FUNCTIONAL BLOCK DIAGRAM
II
BIT 2
BIT 3
BIT 5
BIT6
BIT 7
81T8
BIT9
53 REF IN
52 REF OUT
49 GAIN
48 GAIN
47 AMP OUT
GENERAL DESCRIPTION
The DAC1136/1138 are complete self-contained current or
voltage output modular digital-to-analog converters with
resolutions and accuracies of 16 and 18 bits.
46 BIPOLAR
OFFSET OUT
44 AMP IN
-1SV
COMMON
The DAC1136/1138 combine precision current sources
with state-of-the-art steering switches to produce a very linear
output. Inputs to these converters are compatible with TTL
levels. The converters have a current output of -2mA full scale.
A voltage output can be obtained by connecting the internal
amplifier to the current output by means of jumpers. By using
additional jumpers, the user can select anyone of the following output ranges: 0 to +5V, 0 to +10V, ±5V, or ±10V.
WHERE TO USE HIGH RESOLUTION DACS
The DAC1136/1138 deliver exceptional accuracy for a broad
range of display, test and instrumentation applications. The
DAC1136, with a resolution of 16 bits or 1 part in 65,536,
and the DAC1138 with a resolution of 18 bits or 1 part in
262,144 are ideally suited for applications requiring wide
OUTPUT
AMPLIFIER
34
-DAC1138 ONLY
dynamic range measurement and control. Applications include
data acquisition systems, high resolution CRT displays, automatic semiconductor testing, photo-typesetting, frequency
synthesis and nuclear reactor control.
CERTIFICATE OF CALIBRATION
Each DACI138 has been calibrated with equipment and
methods that are traceable to the National Bureau of Standards (NBS). A Certificate of Performance is sent with each
unit, which includes linearity test data.
DIGITAL-TO-ANALOG CONVERTERS 2-453
SPEC IFICAli 0NS
(typical @
+ 25"1:, rated
power supplies unless othelWise noted)
DACll36
DACll38
K
J
RESOLUTION, BITS
16
ACCURACY
Integral Non1inearity
Differential Nonlinearity
Gain and Offset Error (Extemally Adjustable)
-2mAlOOmA
-lmAlO +lmA
lOY
±II2LSBmax
",II2LSBmax
-2mAlOOmA
-lmAlO+lmA
Oto+SV,OlO+IOV +SV +IOV
lTUCMOS' See Fiaure 2
TTUCMOS' See Fiaure 2
Complementary Binary (COMP BIN)
Compiemeotary Offset Binary (COMP OBIN)
8""
6""
10".s
8""
90""
17S""
140""
18""
2V/u.s
250""
8""
IV/"
I
I
S
!
I
S
"'0.3
"'0.4
"'0.8
"'O.S
",S
",0.5
",I
",S
"'6
",2
",2
O.5nArms
O.5nArms
4".Vpk-pk
6".Vpk-pk
9".Vpk-pk
30".Vrms
4".Vpk-pk
6".Vpk-pk
9".Vpk-pk
30"Vrms
±2mVmax
",IOO".V
",1O".Vrc
",200".Vmu
",IOO".V
",1O".Vrc
via Internal Sebottky Diodes
via Internal Sebottky Dindes
>33k1l
>SkIl
lSOpF
>33k1l
>SkIl
ISOPF
+ 6.000V (Maximum Error, ",0.024V)
3".Vpk-pk
Sppmrc
+ 6.000V (Maximum Error, "'0.024V)
3".Vpk-pk
Sppmrc
9mA
+30mA
9mA
+3OmA
80dB
'" 1I4LSB pet Volt &V.
80dB
'" 1I4LSBpetVoIt&\1
Oto +7O'C
-SS"Clo +85"C
5% lO95%, NODCODdeDoi",
Olo+7O'C
-55"Cto +85"C
5% 1095%, Nooenndoo,inl
STABILITY, LONG TERM
(ppm ofFSRlI ,000 hrs.)'
Gain (ExcludingVREF)
Offset
NOISE (Include VREP; Double for
Bipolar Mnde)
Output Current (BW ~ 100kHz)
OutputVollaS«BW ~ O.I-IOHz)
@OV(AllI'sCOOe; "ZERO")
@SV (MSB ~ OCode; "HalfScal.")
@IOV(AIIO'sCOO.;"FullScal.")
OutputVoltag«BW ~ 100kHz)
VOLTAGE COMPLIANCE (Amplifier
Offset, Ens)
Max Ens Allowed for Rated Accurscy
Initial Ens (Factory Adj.)
Ens Drift
Current Output (pin 69)
VoIlaS< Protection
Source Resistance
Unipolar Moo.
Bipolar Mnde
Source Capacitance
REFERENCE VOLTAGE (VREP)
VollaS«Zour=200fi)
Nnise(BW ~ O.I-IOHz)
TetDpco
+
",ILSBmax
",ILSBmax
Compiemeotary Binary(COMP BIN)
CompIementaryOffsetBinary (COMPOBIN)
DYNAMIC CHARACTERISTICS
Settling Time to 1I2LSB
Current
Full Scal. Step
LSBStep
VollaS<
Unipolar (IOV Step)
Bipolar (20V Step)
LSBStep
Slew Rat.
TEMPERATURE COEFFICIENTS
(ppm ofFSRrC)
Integral Nonlinearity
Differential Nonlinearity
Gain (Excluding V REP)
Offset
Unipolar MOOe
BipoIarMnde
'" II2LSBmo
",II2LSBmax
Oro +SV,Oto + lOY, +5V,
DIGITAL INPUTS
INPUT CODES
Unipolar Mnde
Bipolar Mnde
18
",ILSBmu
",ILSBmo
ANALOG OUTPUT
Unipolar Moo.
Bipolar Mnde
VoIlaS< Output Range (Pin Selectable)
K
J
POWER SUPPLYREQU!REMI!NTS'
+SVdc, "'S%
+ 15Vdc, +5%
POWERSUPPLYREJECTION(",ISVdc)
Gain or Offset VB. FSR
Differential Nonlinearity
ENVIRONMENTAL
OperatiogTetnper8ture
Storaae Tetnper8ture
Humidity
NOTES,
IRecommeaded DNLc:aIibnIioDcbcdc: 611lOD.tbs.
............... PvwcrSupply'AIII1oaomc..ModeI923.
SpecificotioDll1lbjecttoclwIa.ll86SM
ilDD.lZ06jW
Mia
hnometer
1'Jp
Mas
1'Jp
Mia
•
•
•
•
12
RESOLUTION
LSBWBIGHT(FS
(typical @ +25"1: with nominal power supplies and lkO output load unless otherwise noted)
= 10.24V)
2.5
±0.0125
ACCURACY (LiDearity)
Differential Nonlinearity
ZeroOft'set' (Initial)
MonotODicity
±112
±.35
Guaranteed
TEMPERATURE COEFFICIENTS
LiDearity
5
60
Gain
Oft'set
100
DYNAMICCHARACfERlSTlCS2
SettJing Time to ~LSB
±5.12VFSChange
ILSBChange
Internal Current DIA
S1ewRate
Gain
DIGITAL DATA INPUTS
Logic Compatibility
Logic Levels
"I"
"0"
Load (each bit)
Coding (see Table on last page)
STROBE INPUT
Logic Compatiblity
Logic Levels
"I"
"0"
Load
Risetime/Falltime(lO%-9O%)
Width
Frequency (see chan be1ow)
OUTPUT (see Coding Table)
R pB = 1,0000
Bipolar Voltage'
Unipolar Voltage
Current
RFB = 2,0000
Bipolar Voltage
Current
Residual Glitch
Output Impedsnce
Capacitive Loadins
POWER REQUIREMENTS
+ ISV ± 3%Current
-ISV ± 3%Current
+ SV ± 5% Current
Power Supply Rejection Ratio
Power Dissipation
TEMPERATURE RANGE
Operating'
SI01'1I8e
THERMAL RESISTANCE'
Junction to Air, Bja (free air)
Junction toCase, 8jc
2
60
SO
25
Adjustable
+2.4
0
+5
+0.4
One Standard
Complementaty Bioary (CBN);
Complementary Offset Bioary (COB)
.
*
*
*
·
·
·
TTL
+2.4
0
+5
+0.4
*
*
IS
. 6Slword rate
6
•
One Standard
SO
±2.S6
Oto -5.12
8
*
SO
0.1
1,000
100
I
55
30
95
60
35
130
+2
2.25
-2
1.95
0
-55
+70
+125
*
·
*
2-460 DIGITAL"TO·ANALOG CONVERTERS
LSB
mV
....
os
os
VI",s
VN
*
*
V
V
TTL(S) Load
·
·•
V
V
TTL Load
ns
ns
MHz
*
*
V
V
mA
*
*
*
*
*
*
*
*
*
*
V
mA
mV
0
pF
mA
rnA
rnA
mVN
W
-55
+125
-C
*
*
"C
*
*
HDD·1206JW
1Adjustable to zero.
%FS
ppmI"C
·
3.015 x 10'
zAlldynamiccbaracteristicsarebilCdonFS"" ±5.12V;RFB "" 2,0000.
'witbR.. = lk,ana!osoutputvol_arehalfthose.bo9'ninTableonlastpoge.
'Cue Temperatun:.
5Maximumjunc:tWn temperature is 15O"C.
•
'CakuIatedperMIJ..HDBIOI7,Ground;Fixed;CaseTemperature = 6O"C.
'·S.. Seetion 14 for padcaae outline information.
·Speciliestions ....... HDD-lZ06jW.
SpecifICations subject to change 9fitbout sOrice.
mV
ppmrc
ppmrc
*
*
•
32
13
NOTES
·•
*
*
±S.12
8
Vails
Bits
*
TTL(S)
MTBF"
Meso Time Between Failures
PACKAGE OPTIONS7
Cerantic(DH·32A)
Metal (DH.32C)
·
··
·
··
··
·
±SO
Mas
HDD·1206SM
"CIW
"CIW
Hours
Theory of Operation - HOO-1206
THEORY OF OPERATION
The equivalent circuit for the for the HDD-1206 D/A converter
is shown in functional block diagram.
The unit consists of input registers, fast-settling current output
D/A, output amplifier, timing generator, and associated circuits.
The purpose of the input register circuits is to de-skew the
input bits and assure their simultaneous arrival at the input of
the current DIA. This is critical because time skew on the input
data bits is a major contributor to discontinuities, or "glitChes,"
in the analog output of a D/A.
The Timing Generator includes a Track & Hold circuit and
generates the required internal pulses for operation whenever it
receives a Strobe input pulse. See Figure 1, the HDD-I206
timing diagram.
LJ
"1"
I
STROBE
M1N50ns
MAX 0,651
WOAD RATE
~
I
I
TIH
I
I
MAX
TRACK I -55":
I
HOLD
.-MIN 30ns
MAX 100ns·
HOLD
I
TRACK
M_AX
REGISTER
_I I
SAME AS
_~~OLDTIME
I
OUTPUT
Figure 1. HDD-1206 Timing Diagram (Digital Inputs not
Changing)
As shown, the Strobe pulse is a positive-going TTL pulse supplied
by the user of the HDD-1206. Internal timing circuits establish
the maximum 55ns delay from the leading edge of the Strobe
pulse to the leading edge of the T/H (Track/Hold) pulse; and
the maximum IOns delay from the leading edge of the T/H
pulse to the leading edge of the Register pulse. The data from
the input registers are strobed into the current DIA at the end
of this 65ns interval, so they must be valid by that time.
The user determines the width ofthe T/H pulse (and the Register
pulse) by selecting the value of the RHoLD resistor. See Figures
1 and 2. As shown, the width of the Hold pulse can vary from
approximately 30ns to approximately lOOns by using resistor
values from lk to 5k, respectively.
i
1
100
/
VALUE OF 3.6k FOR
WilL MAKE HOLD
90~-4-___~__-__-_+/?f-_-:~~~~ RHOlD
PULSE APPROXIMATELY
~
~
:
60f---j-+/-+--+1-+-l
9
3ol--f'-~-+--++-~
~
/
85n5 WIDE; THIS IS
OPTIMUM FOR MOST
APPLICATIONS.
VV
\1
1k
2k
3k
4k
VALUE OF RHOLa -
Current -switching DIA converters are inherently faster than
voltage-output types because of the absence of an output amplifier.
This means current-switching converters have no slew rate limitation which can slow settling; nor are they subject to the overshoot
and ringing problems often associated with feedback amplifiers.
Both current-switching and voltage-output converters display a
discontinuity, or "glitch," in their analog outputs because of the
basic characteristic of saturated logic (TTL is an example) which
causes the propagation delay to be less for negative-going inputs
than it is for positive-going inputs.
This difference in propagation delay manifests itself as a "worst
case glitch" at the major carry point, or mid-scale, of the output
range of the current converter. This is the point at which nearly
equal and opposite currents are being switched within the
converter.
The "glitch" at mid-scale, the switching point of the Most
Significant Bit (MSB), will be halved at the V4 and % points;
halved again at the V, and 7/, points, etc. The amplitude of the
"glitch," therefore, is a function of signal dynamics and cannot
be eliminated with filtering.
I
I
I
CURRENT-OUTPUT D/A CONVERTERS
A brief review of the salient characteristics of current DIA converters may be a useful approach to understanding the operation
of the HDD-1206 unit.
5k
n
Figure 2. Hold Time vs. RHoLD
For most applications, a value of 3.6kO and a pulse width of
approximately 85ns is the optimum choice. This pulse width
will "hold" the analog output of the HDD-I206 D/A until the
"glitch" resulting from the most recent update has passed,
without infringing on the word rate capabilities of the
HDD-I206.
The variations in glitch amplitude caused by signal dynamics
create a multitude of intermodulation (1M) products, some of
which fall into the video pass-band as spurious signals, and
increased noise level. These 1M products are also relatively
immune to elimination by filtering.
The amplitUde of the glitch can be reduced by de-skewing the
input bits; but no amount of de-skewing or filtering can negate
the physics of saturated logic which cause the glitch to be generated
initially.
The best solution, then, is to cause the glitch to remain a constant
across the entire output range of the converter. The efficiencies
of the circuit will be enhanced if the solution can also permit
using the full drive capabilities of the current-output D/A in
either unipolar or bipolar modes of operation.
The design approach used in the Analog Devices HDD-1206
D/A converter accomplishes these desired goals and provides
voltage outputs at high update rates.
NOTES ON DEGLITCHING
Refer again to the equivalent circuit for the HDD-1206. The
data bits are applied through the input register to the current-output D/A converter, which is capable of supplying up to 5.I2mA
of output current.
The output of the current D/A, in turn, is applied to the input
of the output amplifier via strapping external to the HDD-I206.
The Timing Generator supplies the necessary pulses and timing
to apply signals to the current DIA and output amplifier after
the initial glitch caused by the digital inputs has subsided.
The digital "1" (Hold) level of the T/H pulse causes the switch
at the input of the amplifier to open, holding the last value of
the current D/A converter. During this hold interval, the switching
transients caused by updating digital inputs are masked from
the amplifier, thereby avoiding HDD-I206 output discontinuities
whose amplitude would be a function of signal dynamics.
Ten nanoseconds after the T IH pulse goes to the digital "1"
level, the register pulse also changes state from "0" to "1".
DIGITAL-TO-ANALOG CONVERTERS 2-461
II
This transition moves the output of the current D/A to the new
value established by the most recent digital inputs applied to the
HDD-IZ06.
+.v
-16V
Any change in the current DIA output has stabIized by the time
the TIH pulse returns to the digital "0" (Track) level. Re-establishing the track mode closes the switch at the input of the
amplifier and the output of the HDD-IZ06 moves to the new
analog value dictated by the digital input word.
An
ANAlOG
As shown in Figure I, the output of the HDD-IZ06 will contain
switching transients associated with the TIH pulse. But these
"glitches" will be constant in amplitude and duration and will
occur at the update rate, since they are a function of the strobe
pulse applied by the user.
These switching transients will settle out in approximately SOOns,
and will have unifonn amplitude over the complete analog output
range of the D/A. For strobe rates of ZMHz and above, the
settling interval switching from "hold" to "track", and vice
versa, will produce a constant dc offset on the output. The
HDD-IZ06 is not intended to get rid of all glitches per se; it is
designed to provide a constant-amplitude glitch.
When the area under the transient curve is held constant, the
frequency spectrum of the glitch is a fine line, i.e., a single-line
spectrum at the sample rate frequencies, and harmonics of the
sample frequency.
The HDD-1206 effectively eliminates the 1M products discussed
above. When it does, the signal-to-noise (SIN) ratio approaches
that of an ideally-quantized signal, where the nns noise is
qlv12, when frequencies above Nyquist are filtered out.
GLITCH VS. PEDESTAL
In addition to the "glitch" which is a characteristic of current
D/As, the track & hold used in the HDD-IZ06 also contributes
an anomaly to the output signal.
Refer to Figure 3. This diagram compares the "glitch" created
by the HDD-IZ06 to the pedestal created by the internal T/H
circuits.
RESIDUAL
[GUTCH
~-T-TRACK·TO·HOLD
SWITCHING TRANSIENT
OUTPUT
NOlE 1: FOR UNIPOLAR NlGAnYE
OUTf'UT. REMOVl! STRAP
BETWEEN ptNS 28 AM) 29;
CONNliCT 29 TO GROUND
Figure 4. HDD-1206 Bipolar Connections
The output voltage swing is established by the value of feedback
resistor R FB • The table below indicates output levels for both
unipolar and bipolar operation, with feedback resistors of either
1,0oon or Z,OOOO.
Hold resistor R HOLD connected between the + SV supply and
Pin 31 sets the width of the Hold mode of the TIH pulse. Test
Point Pin Z is used for observing the pulse.
The Offset Adjust potentiometer is used to set the desired analog
output of the HDD-IZ06 and can be used to help assure correct
voltages are present when the DIA is installed in the system.
When operated in a unipolar mode with digital "0" applied to
all inputs but no continuous strobe pulses applied, the Offset
Adjust is set for an analog output of -S.IZV or less ILSB, with
lk for the value of R FB • (NOTE: At least one strobe pulse
needs to be applied to latch the input data into the registers.)
If the HDD-IZ06 is installed in a system and the strobe pulse is
applied continuously, the Offset Adjust is calibrated for the
desired output value with a digital "0" applied to all input pins.
HDD-1206 ANALOG OUTPUT WITH lkO LOAD
Digital
Inputs
Complementary
Offset Binary (COB)
Bipolar Output
Rm= 2k
111 ... 111
111 ... 110
110 ... 000
101. .. Ill
100 ... 000
011 ... 111
010 ... 000
001. .. 111
000 ... 001
000 ... 000
+5.l2(+FS)
+5.1175
+ 2.5625 (+ 1/2FS)
+2.56
+ 0.0025 (+ lLSB)
0.0000
- 2.5575 (- 1/2FS)
-2.56
-5.1150
-5.1175( -FS -ILSB)
HOLD-IO-TRACK
swnCHING TRANSlfNT
Figure 3. Pedestal/Glitch Relationship
As shown, the "glitch" is a transient signal which remains constant
in width and amplitude over the entire output range, at all
update rates. The pedestal, on the other hand, is an offset signal
whose amplitude can vary (because of switching transient settling)
as a function of hold time and word rate.
This pedestal is caused by charge transfer associated with the
hold capacitor; the transfer occurs when the HDD-IZ06 circuits
are switched from a "track" to "hold" condition. The pedestal
is basically an offset error in the HDD-IZ06 output and can be
compensated with the Offset Adjust when the unit is installed in
the user's system.
Figure 3 is not drawn to scale; there is no attempt to imply the
identified elements have precisely that relationship to one another.
They are exaggerated for illustrative purposes.
Applications
Bipolar connections for the HDD-IZ06 D/A converter are shown
in Figure 4. As indicated, a unipolar negative output is accomplished by connecting Bipolar Pin Z9 to ground, instead of to
Pins Z7 and 28.
2-462 DIGITAL-TO-ANALOG CONVERTERS
+1SV
Complementary Binary (CBN)
Unipclar Negative Output
Rm lk
=
-
0.0000(0)
0.00125 (+ lLSB)
1.27875
\.28(1/4)
2.55875
2.56(1/2)
3.83875
-
3.84(3/4)
-5.1175
-5.11875(FS - ILSB)
ORDERING INFORMATION
Model HDD-IZ06JW D/A converter is housed in a ceramic
package, the model HDD-IZ06SM is a hermetically sealed version;
outline dimensions are shown elsewhere.
Mating individnal pin sockets are available from AMP. Part
number 6-330808-0 are knockout end type; 6-330808-3 are open
end type.
Hybrid Video
Digital-to-Analog Converters
HOG Series I
r-IANALOG
WDEVICES
HDG SERIES FUNCTIONAL BLOCK DIAGRAM
FEATURES
Update Rates to 150MHz
Low Glitch Energy
Complete Composite Inputs
Single -5.2V Power Supply
Military Temperature Range Available
II
APPLICATIONS
Raster Scan Displays
Color Graphics
Analytical Instrumentation
TV Video Reconstruction
GENERAL DESCRIPTION
The HDG-Series DfA Converters have become the standard of
comparison for fast-settling DfAs with complete composite
inputs. The HDG-0805 is an eight-bit (256 Gray levels) device.
All versions have complete composite controls, including self-contained, digitally-controlled sync and blanking; and a reference
white control input to help assure compatibility with EIA Standards
RS-170, RS-330, and RS-343-A. Their performance is enhanced
even more with a 10% bright input capability.
Output inpedance is 75 ohms and their full-scale output current
is capable of developing standard video levels across video loads.
In addition to all of these characteristics which make them easy
to incorporate into circuits, the need for a single - 5.2V power
supply also adds to their attractiveness.
The model number without a suffix designates the "original"
HDG Series DfA Converter and is housed in 24-pin metal packages.
The model numbers with suffIxes make use internally of the
Analog Devices Model AD9700 to obtain better performance;
these devices are housed in ceramic DIP packages.
The "BD" and "BW" versions in the newer (suffIXed) units are
close equivalents to the original design, but a number of advantages
accrue by using the newer units. Note particularly the parameters
for linearity tempco; strobe input loading; Composite Sync and
Composite Blanking outputs; Power Supply Rejection Ratio
(PSRR); supply current; and power dissipation. Conversely, the
original design is slightly better in terms of voltage settling
time, glitch energy, and output compliance.
BUFFER
REGISTERS
DIGITAL
INPUT
~----~l-!X.~A~XI~S~--~--,
X&V
CONTROL
CIRCUITS
V.AXIS
Typical Raster Scan Display System
DIGITAL-TO-ANALOG CONVERTERS 2-463
SPECIFICATIONS
(typical @ + 2ft with nominal power supplies ooless otherwise noted)
Parameter
Units
RESOLUTION
Bits
LEAST SIGNIFICANT BIT (LSB)
WEIGHT
Voltage (adjustable)
Current (adjustable)
mV
I1A
2.5
67
±%GS
±%GS,max
0.2
0.2
mV,max
0.9
Guaranteed
ppml°C(max)
ppmt'C(max)
ppmfOC(max)
20(35)
50(125)
10(15)
%GS;
0.4
ns(max)
MHz (min)
Vil1s
ns
pV-s
8(10)
150(125)
200
2
50
ACCURACY
(GS = Gray Scale; FS = Full·Scale)
Linearity
Differential Linearity
Zero Offset (Initial)
Voltage
MonQronicity
TEMPERATURE COEFFICIENTS
Linearity
Gain
Zero Offset
DYNAMIC CHARACTERISTICSGRAYSCALE OUTPUT'
Settling Time
(OVtoFSGS change)
Voltage
Update Rate 2
Slew Rate
Rise Time
Glitch Energy'
DIGITAL DATA INPUTS
Logic Compatibility
Coding
Logic Levels
"I"
"0"
Loading (each bit)
STROBE INPUT
Logic Compatibility
Logic Levels
"I"
"0"
Loading
Setup Time (Data)
Hold Time (Data)
Propagation Delay
10% BRIGHT, REFERENCE WHITE,
COMPOSITE SYNC, AND
COMPOSITE BLANKING INPUTS
Logic Compatibility
Logic Levels
"I"
"0"
Loading
HDG·08OS
800-0805BDI
BW/SD
15(30)
*
9(11)
80
ECL
Complementary Binary
(CBN)
V (minimax)
V (minimax)
-0.9( -1.1/-0.6)
-1.7(-2.0/-1.5)
5pF and 50kU to - 5.2V
*
ECL
V (minimax)
V (minimax)
ns,min
ns,min
ns(max)
-0.9( -1.11-0.6)
- 1.7 (- 2.01- 1.5)
50pF and SkU to - 5.2V
5pFand50kU
to -5.2V
2.5
1.5
3(4)
ECL
V (minimax).
V (minimax)
-0.9(-1.1/-0.6)
-1.7( -2.0/-1.5)
5pF and 50kll to - 5.2V
SPEED PERFORMANCECONTROL INPUTS
Settling Time to 10% of Final Value for:
10% Bright
Reference White
Composite Sync
Composite Blanking
ns(max)
ns(max)
ns(max)
ns(max)
8(10)·
8(10)
8(10)
8(10)
SETUP CONTROL
Ground
Open
-5.2V
mV (IRE Units)
mV (IRE Units)
mV (IRE Units)
0(0)
71 (10)
142(20)
ANALOG OUTPUT
GSCurrent
GSVoitage 4
Compliance
Internal Impedance
mA(±I%)
mV
V
ll(min/max)
Oto -17
Oto -637.5
-1.1 to + 1.1
75 (71179)
2-464 DIGITAL-TO-ANALOG CONVERTERS
*
-l.2to +0.1
HOG Series
Panmeter
Units
HOG·DSDS
OUTPUT - REFERENCE WHITE'
Current
Logic "I"
mA(±4%)
Normal
Operation
Oor - 1.9
Logic "0"
Voltage
Logic "I"
mA(±4%)
Logic "0"
mV(±4%)
Normal
Operaiion
Oor -71
mA(±S%)
mA(±S%)
o
mV(±S%)
mV(±S%)
o
mV(±4%)
OUTPUT - 10% BRIGHT"
Current
Logic"l"
Logic "0"
Voltage
Logic "I"
Logic "0"
OUTPUT -COMPOSITE SYNC",7
Current
Logic "I"
Logic "0"
Voltage
Logic "I"
Logic "0"
Logic "I"
Logic "0"
POWER REQUIREMENTS
- S.2V ± 0.2SV'
Power Supply
Rejection Ratio
Power Dissipation
TEMPERATURE RANGE
Operating (Case)'
Operating ("SO" Case)
Storage
THERMAL RESISTANCE'o
junction toAir,6)A
•
- 1.9
-71
mA(±4%)
mA(±4%)
o
mV(±4%)
mV(±4%)
0
-2SS
OUTPUT -COMPOSITE BLANKING",7
(Assumes Setup is Open, Which is
Equivalent to 10 IRE Units)
Current
Logic "I"
mA(±4%)
Logic "0"
mA(±4%)
Voltage
HDG·08DSBOI
BWISO
-7.6
0
- 1.9
mV(±4%)
mV(±4%)
0
-71
mA(max)
320(360)
12S(140)
%1%
mW(max)
III
1665 (IS7S)
0.00511
6S0(730)
"C
-2Sto +SS
*(BOandBW)
-55to+125
"C
"C
- 55.to + ISO
°CIW,max
4S
°CIW,max
12
(free air)
Junction to Case, ajA
MTBF"
Mean Time Between Failures
PACKAGE OPTIONS 12
M·24A
OH·24B
Hours
3.23 x 10'
HOG·OSOS
HOG·OSOSBO
HOG·OSOSBW
HOG·080SS0
For applications assistance, phone Computer Labs Division at (919) 668-9511
NOTES
ISettiing to GS percentage includes FS and MSB transitions. Inherent 3ns register delay (50%) points) is not included.
2Minimum update rates limited by full.scale settling time for useable number of bits.
Units can be updated to lSOMHz with settling degradation.
3Glitch can be reduced with glitch adjustment.
*LSB value used for calibration causes Gray Scale output to be 637.5mV rather than 643mV shown in idealized composite waveform;
both values are well within the output and EIA Standard RS-170 tolerances.
5Effect on analog output of logic "0" at Reference White input depends on 10% Bright signal input (See Table I).
610% Bright, Composite Sync, and Composite Blanking outputs shown add to Gray scale analog output at Pin 18 (See Table I).
'Composite Sync or Composite Blanking control signals reset input registers. Composite Sync or Composite Blanking should not be operated simultaneously with Reference White.
8Power supply must have less than 5mV p-p ripple.
90perating temperature - 550C to + 1250(: on "SO" units.
IOMaximum junction temperature = 1500C.
llCalculated for HDG-0805S0B using MIL HNBK-217; Ground Fixed; +250(: Ambient.
12See Section 14 for package outline information.
* Specification same as HOG-0405.
**Specifications same as HDG..()4()5BD/BW/SD.
Specifications subject to change without notice.
DIGITAL·TO·ANALOG CONVERTERS 2-465
PIN DESIGNATIONS
Pin
12
11
10
9
8
7
6
5
4
3
2
1
Function
GROUND
BIT8(LSB)
BIT7
BIT6
BIT 5
STROBE
BIT4
BIT3
BIT2
BIT1(MSB)
-5.2V
GROUND
Pin
13
14
15
16
17
18
19
20
21
22
23
24
Function
GLITCH ADJUST
GROUND
GROUND
GROUND
GROUND
ANALOG OUTPUT
COMPOSITE SYNC
SETUP
10% BRIGHT
COMPOSITE BLANKING
REFERENCE WHITE
-5.2V
NOTE: Connect Pins 1, 12, and 14-17 together and
to low-impedance ground plane as close to
case as possible.
USING HDG-SERIES UNIT FOR RASTER SCAN
Refer to the block diagram of the HDG-Series D/A Converter
and the idealized composite output waveform.
The digital input bits represent the Gray Scale values (the discrete
levels between Reference Black and Reference White) in a composite video signal. There are 256 (28) of these levels.
The input bits are applied to Pins 3-6 or Pins 8-11 of the
HDG-OS05.
The output analog signal (at Pin IS) will be a function of these
digital inputs. The output will also be affected by the ECL
levels at the control inputs of 10% Bright, Reference White,
Composite Sync, and Composite Blanking; and the level of the
control signal (expressed in terms of IRE units) at the Setup
input.
The total effect of these combined signals can be illustrated in a
truth table fonnat if arbitrary values are assigned for Gray scale
inputs, and various combinations of control inputs are selected.
Refer to Table I.
DIGITAL INPUTS VS. ANALOG OUTPUT
BIT BIT BIT BIT BIT BIT BIT BIT
10%
1
2
3
4
5
6
7
8
BRIGHT
1
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
I
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
REF.
WIDTE
BLANKING
COMPo ANALOG OUTPUT IN mV l
SYNC
(HDG-OSOSBDIBW/SD)
0
-71
-320
-637.5
-70S.5
1
0
0
1
1
I
I
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
NOTES
'VaJucs are for Gray ScaJeoutputof8-bitD/A'•.
2Setup (Pin 20) pounded. (0 IRE W1its)
'Setup (Pin 20) open. (10 IRE W1its)
'SeNp (Pin 20) to - 5.2V (20 IRE W1its)
ACNaI analog output value of -637.SmVisdifferentfromidealvalueof -643mVbec:auseofLSBvalueuscdincslibration.
Table I. Digital Inputs vs. Analog Output
2-466 DIGITAL-TO-ANALOG CONVERTERS
0
-71
-637.5 2
-70S.5mV3
-779.5mV4
-922.5mV2
-993.5mV3
-1064.5mV4
-993.5mV2
-1064.5mV3
-1135.5mV4
11IIIIIIII
Hybrid Video
Digital-to-Analog Converter
HOG-0807 I
ANALOG
WDEVICES
FEATURES
Update Rates to 50MHz
Low Glitch
Complete Composite Inputs
Single + 5V Power Supply
TTL-Compatible Inputs
Directly Drives 750 to Ground
HDG-0807 FUNCTIONAL BLOCK DIAGRAM
+5V
BIT'
(MSa)
~
1.
IEXCEPTASNOTeO RES&STORS
H
~
BIT4 ~
BIT.
;;
BIT.
B
BITO
BIT7
AD!700
~
DlA
CONVERTER
~
(LSB)
,...
BIT8
STROBE
COMPOSITESVNC
10%BRIGHT
~
OIGITALGROUND
GENERAL DESCRIPTION
00
~
j
DIAOUTPUT
ANALOG GROUND
~
1>.P
GLITCH ADJUST
ff
'---
~
2~
CURRENTSET
8ET\JP
.5V
Model numbers with "BW" suffixes are housed in 24-pin nonhermetic ceramic dual-in-line packages. Versions with "BD"
suffixes are housed in hermetically-sealed ceramic DIP
packages.
The HDG-0807 is an eight-bit (256 levels) device.
Both versions have complete composite controls, including selfcontained, digitally-controlled sync and blanking; and a reference
white control input to help assure compatibility with EIA Standards
RS-170, RS-330, and RS-343-A. Performance is enhanced even
more with a 10% bright input capability.
1~~~~1- --- ---- ----- -- ---
r-- -----r------
71mV
mV
I
Output impedance is 75n and the full-scale output current is
capable of developing standard video levels across video loads.
An output current mirror shifts the output to ground reference
while attenuating power supply noise by means of common-mode
rejection.
The HDG-0807 DIA Converters are extensions of the technology
and capabilities of the HDG-Series high-speed raster scan DIA
converters. They offer the user increased flexibility because of
their ability to operate on a single + 5V power supply, and their
compatibility with TTL signals.
9,..,.
CURRENT
MfftROR
'Q
COMPOSITE BLANKING 22
REFERENCE WHITE
I
~ HDG-0807
BIT2
APPLICATIONS
Raster Scan Displays
Color Graphics
AnalYtical Instrumentation
TV Video Reconstruction
= 2kl
9
-- -
-
-
-
--10%8AKnfT
_
_ _ _ _ _ _ _ REFERENCE WHITE
LEVELIV_I
____ ""'"
__
637.SrnV
HDG-0807
G
690.75mV
WITH7.SIRE
8ETt"
338.25mV
285m:. : - - m
ov~
::.:j --r --------: -
IS'3.2'5mv -
SETUP
-
:c~
~~H_L
l_p~C~
_____
GROUND-- _ _ _ _ _ _ 0!f~~T.Q.5'!!!'vMA...!
I
--i pg:.rN£N
I
- --LEVELIVRBI
_~EBLANKING
________ 1
SVNCLEVElIVsl
_ _ _ _ _ _ _ _ _ L __
I
r---P~~gN----1
HDG-OB07 Composite Waveform
DIGITAL-TO-ANALOG CONVERTERS 2-467
SPEC IFI CAli 0NS (typical@ +2ft willi nominal power supplies IDlIess oUterwisa
Parameter
Uails
HDG-0887BDIBW
RESOLUTION
BilS
8
LEAST SIGNIFICANT BIT (LSB) WEIGHT
Voltage (adjustable)
mV
Current (adjustable)
".A
ACCURACY
(GS =Gray Scale; FS =Full-Scale)
Lioearity
Differential Lioearity
Zero Offset (Iaitial)
Voltage
Monotoaicity
2.5
67
±%GS
±%GS,max
0.2
0.2
mV,max
50
Guaranteed
TEMPERATURE COEFFICIENTS
Lioearity
Gaio
Zero Offset
ppmf'C (max)
ppmf'C (max)
mVI"C(max)
15(30)
350(1,000)
1.0(2.0)
DYNAMIC CHARACTERISTlCSGSOUTPUT'
Settling Time
ILSB Midscale Voltage Change
OV toFS GSVoltageChange
Slew Rate
Rise Time
.Glitch Impulse2
%GS;
ns(max)
ns(max)
V/".s
ns
pV-s
0.4
14(16)
15(18)
250
2.2
50
DIGITAL DATA INPUTS
Logic Compatibility
Codiog
Logic Levels'
"I"
"0"
Loadiog (each bit)
Data Update Rate
STROBE INPUT
Logic Compatibility
Logic Levels
"I"
"0"
Loading
Setup Time (Data)
Hold Time (Data)
Propagation Delay
10% BRIGHT, REFERENCE WHITE,
COMPOSITE SYNC, AND
COMPOSITE BLANKING INPUTS
Logic Compatibility
Logic Levels
"1"
"0"
Loadiog
SPEED PERFORMANCECONTROL INPUTS
SettlingTimeto 10% of Final Value for:
10% Bright
Reference White
Composite Sync
Composite Blanking
SETUP CONTROL
+5V
Open
ANALOG OUTPUT
OS Voltage pop'
Compliance
Internal Impedance
TTL
Binary
(BIN)
(+ 3.81 + 5.0)
(0/+3.0)
5pFand2k!l
to +5V
MH2(Guaranteed) 50(45)
V (miolmax)
V (minimax)
TTL
V (minimax)
V (miolmax)
ns,min
ns,min
ns(max)
( + 2.5/ + 5.0)
(0/+ 1.5)
IpFand 2.2kO
to +4.4V
3
3
8
TTL
V (minimax)
V (mioI"1ax)
( +3.81+5)
ns(max)
ns(max)
ns(max)
ns(max)
L5
15
15
15
mV(IREUnits)
mV(IREUnilS)
0(0)
53.25 (7.5)
mV(±4%)
V
!l(mioImax)
637.5
-3to +3
75 (71n9)
2-468 DIGITAL-TO-ANALOG CONVERTERS
(0/+3.5)
5pFand2k!l
to+5V
noIBd)
HOG-DaD7
Parameter
Units
HDG--0807BD/BW
OUTPUT REFERENCE WHITE'
(Assumes Setup is Open, Which is
Equivalent to 7.5 IRE Units)
Voltage
Logic "I"
mV(±4%)
Normal
Operation
mV
mV
1046.75
975.75
OUTPUT - 10% BRIGHT"
Voltage
Logic "I"
Logic "0"
mV(±4%)
mV(±4%)
0
71
OUTPUT -COMPOSITE SYNC"·7
Voltage
Logic "I"
Logic "0"
mV(±4%)
mV(±4%)
0
285
OUTPUT -COMPOSITE BLANKING",7
(Assumes Setup is Open)
Voltage
Logic "I"
Logic "0"
mV(±4%)
mV(±4%)
0
53.25
Logic "0"
10%Bright@"0"
lO%Bright@"I"
POWER REQUIREMENTS
+ 5V to ± 0.25V
Power Supply
Rejection Ratio
Power Dissipation
TEMPERATURE RANGE
Operating (Case)
Storage
THERMAL RESISTANCEs
Junction to Air, aJA
(Free Air)
Junction to ease, 0Je
mA(max)
185(225)
%N
mW(max)
0.025/0.25
925 (1125)
·C
·C
-25to+85
-55to + 150
OCIW,max
45
°CIW,max
12
PACKAGEOPTION9
DH-24B
HDG-0807BD
HDG-0807BW
For applications assistance, phone Computer Labs Division at (919) 668-9511
NOTES
ISettling to GS percentage includes FS and MSB transitions. Inherent 3ns register delay (50%) points) is not included.
2Glitch can be reduced with glitch adjustment.
Jlnternal 2k pull~up resistors help assure compatibility with logic levels of multiple TTL families.
4LSB value used for calibration causes Gray Scale output to be 637.5mV rather than 643mV shown in idealized composite waveform;
both values are well within the output and EIA Standard RS-170 tolerances.
5Effee( on analog output of logic "0" at Reference White input depends on 10% Bright signal input.
610% Bright, CompoSite Sync, and Composite Blanking outputs shown add to Gray scale analog output at Pin 18 and are measured with respect to sync level (Vs) shown in waveform.
'Composite Sync or Composite Blanking control signals reset input registers. Composite Sync or Composite Blanking should not be operated simultaneously with Reference White,
which sets input registers.
'Maximum junction temperature = 15O"C.
9See Section 14 for package outline information.
Speciftcations subject to change without notice.
PIN DESIGNATIONS
(As Viewed from Bottom)
Pin
Function
Pin
Function
24
23
22
21
20
19
18
ANALOG GROUND
REFERENCE WHITE
COMPOSITE BLANKING
10% BRIGHT
SETUP
COMPOSITE SYNC
ANALOG OUTPUT
+5V
+5V
+5V
+5V
GLITCH ADJUST
1
2
3
4
5
6
7
8
9
10
11
12
+5V
DIGITAL GROUND
BIT1(MSB)
BIT2
BIT3
BIT4
STROBE
BIT 5
BIT6
BIT7
BIT8(LSBI
+5V
17
16
15
14
13
NOTES: Connect Pins 2 and 24 together and to low~impedance
ground plane as close to case as possible.
+ 5V must be applied to all designated pins.
DIGITAL-TO-ANALOG CONVERTERS 2-469
THEORY OF OPERATION
Refer to the block diagram of the HDG-0807 D/A Converter
and the HDG-0807 composite output waveform.
The digital input bits represent the Gray Scale values (the discrete
levels between Reference Black and Reference White) in a composite video signal. For HDG-0807 units, there are 256 (28)
levels.
Input bits are applied to Pins 3-6 and Pins 8-11 for the HDG0807.
The output analog signal (at Pin 18) will be a function of these
digital inputs. The output will also be affected by the TTL
levels at the control inputs of 10% Bright, Reference White,
Composite Sync, and Composite Blanking; and the level of the
control signal (expressed in terms of IRE units) at the Setup
input.
The total effect of these combined signals can be illustrated in a
truth table fortnat if arbitmry values are assigned for Gray scale
inputs, and various combinations of control inputs are selected.
APPLICATIONS
The HDG-0807 is specifically designed for opemtion in raster
scan graphics applications, in which digital input data are being
changed at a relatively high rate.
The D/A output is generally ac-coupled to the monitor, which
e1iminates the changing dc offset associated with the thermal
drift of the level shift circnits. This offset drift, which is a function
of output level, is held to a maximum of 50mV and will not
affect dynamic video levels.
For optimum performance, ground pins 2 and 24 should be
connected together and to a large ground plane near the unit.
As indicated in the footnotes on the pin designations table,
+ 5V must be applied to all pins which are called out to
receive it.
The performance of the HDG devices can be enhanced with
external bypass capacitors which will supplement the internal
components. Low-frequency bypassing should be provided with
1ILF (or larger) tantalum capacitors between the + 5V supply
pins and ground. High-frequency bypassing can be provided
with ceramic capacitors of O.lILF or larger. All bypass capacitors
should be tied as closely as possible to the hybrid power supply
pins.
Refer to Table 1.
Analog Devices uses 2.5mV for weighting the LSB during calibration of the converter, which causes the full-scale 637.5mV
output of the HDG-0807 to be different from the ideal 643mV
output shown in the composite waveform in the RS-170
standard.
A 200n potentiometer between + 5V and ground with the center
arm connected to Pin 13 changes the threshold of the internal
current switches; this can reduce the amount of glitch from the
typical 5OpV-s to a lesser value when required.
This disparity does not cause any problems in using the device,
since both the ideal value and the actual value are well within
the tolemnces of the output and the RS-170 standard.
For best performance, standard 24-pin hybrid sockets should be
avoided. Individual pin sockets are preferable for evaluating
devices and are available from Analog Devices; in final designs,
the DIA should be soldered directly into the printed circuit
board without sockets.
Referring again to the block diagmm, the Strobe input applied
to the HDG D/A clocks the input registers when the strobe
signal makes the transition from a logic "0" to a logic "1". The
purpose of the registers is to remove time skew from the digital
input bits and minimize perturbations or "glitches" in the analog
output signal.
If it is necessary to route digital signals and/or strobe signals for
distances greater than one inch (2.54cm), microstrip techniques
should be used. Otherwise, the performance of the D/A converter
may be affected adversely.
A logic "0" applied to either the Composite Sync or Composite
Blanking input resets the input registers to 00 000 000. A logic
"0" signal applied to the Reference White input sets the input
registers, thereby overriding the video input word. When this
occurs, the analog output of the converter goes to 1046.75mV or
to 975.75mV, depending upon whether or not the 10% Bright
signal is also operated.
ORDERING INFORMATION
There are two versions of the 8-bit converter; both units operate
over a temperature range of - 25°C to + 85°C. The model numbers
are HDG-0807BD or HDG-0807BW. In these model numbers,
the "D" in the suffix indicates a ceramic, hermetically-sealed
DIP; and the "W" indicates a non-hermetic ceramic DIP.
Versions are available screened to military requirements; contact
the factory for details. It is also possible to order units with
synchronous functions on a "special order" basis; detailed information is available from the factory.
When Composite Blanking is operated, the analog output will
go to a Reference Black value of 338.25mV less some amount,
as determined by the voltage at Setup. The 53.25mV example
used 'in the Specifications section of the data sheet is based on
the Setup input floating, which is equivalent to 7.5 IRE units.
(For this example, the analog output would be 285mV.)
--
DIGITAL INPUTS VS. ANALOG OUTPUT
,
BlTBlTBlTBlTBlTBlTBlTBIT
1
2
4
5
7
8
1
1
1
1
1
1
0
0
•
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ID%
iiiKiiIT WiIfi'i!
iiDI\iiK- CliliP. ANALOGOUTPUTINmVI
ING
SYRC
X
X
X
X
X
X
X
X
X
X
X
X
X
975.75
409.2S
338.25
X
1046,7S
975.75
124.252
X
X
X
X
X
X
X
X
X
X
71'
X
X
X
53.252
X
X
X
NOTES
'Vahaesan: fwGray SaleOlUpUtofHDG-0801 me.aarecl willi respect roSync 1neI.
ZSetup(Pin20)to +SV.(OIREDDirI)
3Setu.p(PiD2O)~(7.51llEUJPt.)
Table I. Digitallnputs vs. Analog Output
2-470 DIGITAL-TO-ANALOG CONVERTERS
1046.75
729.25
o,
X
X
(HDGoGIi07)
338.252
28S 3
0'
Ultrahigh-Speed
Multiplying OfAConverter
11IIIIIIII ANALOG
WDEVICES
HOM-1210 I
FEATURES
12-Bit Multiplying Accuracy
Highest Speed Available
Good Drive: 10.24mA
Small Size: 24-Pin DIP
APPLICATIONS
CRT Displays
Waveform Generation
Vector Generation
MHz-Rate Digital or Analog Attenuators
HDM-1210 FUNCTIONAL BLOCK DIAGRAM
(MSBIBITI
1
10VSPAN
+15V
DIGITAL
INPUTS
CURRENT
OUTPUT
D/ACONVERTER
-15V
GND
GND
GND
GND
.....- - - { 1 5 } - - - - - -........
AMPGND
GENERAL DESCRIPTION
The HDM-I21O D/A converter is an ultrahigh-speed current
output multiplying converter which offers circuit designers a
chance to obtain high speed, good drive, and flexible design
parameters in a DIP package. Its output is the product of 12
bits of digital input data and the analog input(s), providing
flexibility for a wide variety of applications.
Typical analog settling time to 1% is only 85ns; and 3dB analog
bandwidth is 10MHz. Digital settling time to 0.1% accuracy at
the major carry transition is an incredible 80ns, making the
HDM-I2IO D/A extremely attractive for a range of high-speed
multiplying functions.
10 one mode of operation, its output current is precisely proportional to the analog input signal, multiplied by the digital input
code. The analog signal being multiplied can be a sine wave,
triangle wave, sawtooth, or anyone of a variety of complex
waveforms. The output is an accurate scaled version of the
input, with the digital input used as the scale factor.
10 another mode of operation, the analog input voltage can be
used as the scale factor for the digital input code. In addition to
this kind of flexibility, the HDM-1210 also has various offsetting
capabilities which allow the analog input, digital input, analog
output, and/or an external amplifier to be combined. With these
features, the HDM-12IO can be used to accommodate unipolar
or bipolar operation; and provide either one-quadrant or twoquadrant multiplication.
DIGITAL-TO-ANALOG CONVERTERS 2-471
I
+ 25"& with nominal power supplies; v_ (n = - 5V;
(typical @
SPECIFICATIONS and V_ (2) =OV unless otherwise noted)
Parameter
HDM·lZ1OIlD
RESOLUTION
12
LEAST SIGNIFICANT BIT (LSB) WEIGHT
Current
Vol"",,'
ACCURACY(FS - FullScaleJ'
Differential Linearity
Integral Linearity
2.5
250
±112(1)
±1I2(1)
±0.2(±0.5)
Guaranteed
Gain
Monotonicity
TEMPERATURE COEFFICIENTS
Differential Linearity
Integral Linearity
HDM·1ZlOSDISDIl
·
··
·
*
*
*
*
*
Units
Bih
"A
"V
LSB(max)
LSB(max)
%FS(max)
'Trimmed to value.
·
ppmf"C (max)
ppmFC(max)
ppmFC(m.x)
ppmFC(mox)
ppmf'C (mox)
35
80(110)
120(170)
·
ns
.. (max)
ns(max)
85(120)
200
700
*
*
*
ns(max)
TTL
*
+ 3.5 ( + 2.41 + 5.0)
+0.2(0.01+0.6)
*
*
V (minlmox)
V (minJmax)
4014.8
1.2514.8
*
*
nAlpF
mAJpF
Unipolar
All U ls"lnput
Binory (BIN)
Max Positive Output
All "Os" Input
Max Negative Output
*
*
*
Analog Offset'"
*
*
DYNAMIC CHARACTERISTICS
Voltage Settling TimeS
Digital (Major Carry Transition)
To±l%
To±O.l%
To ±0.025%
*
*
Analog Settling to ± 1% FS
(VANAI.OG(I) ~ OVto -5VStep;
All Digital Inputs «U,r U } " )
Overvoltage Recovery Time6
Glitch Impulse
DIGITAL DATA INPUTS
Logic Compotability
Logic Levels
"I"
"0"
Loading7 (Each Bit; with Typical
Input Logic Levels)
TTL"I"
TTL "0"
Coding
OUTPUT'(FS~Full Scale)
Current Range (± 1% Accurate@ FS)
Voltage Range ( ± 1% Accurate@ FS)
Digital ZeroOffset1.3
Oto + 10.24FS
Oto + 1.024FS
0.5(2.5)
2.5(10)
15
Analog Zero Offser'·'
Voltage Noise, nns(O.lHz to lOMHz)
Compliance
Impedance l ,9
·
ns
pV·s
rnA
V
"A (msx)
~(mox)
100(2)
*
*
*
*
"V
V
!l(±)
4(±5.0%)
8(±5.0%)
·
*
k!l(max)
k!l(max)
Oto-5VS
to
+2.5to -2.5FS
to
+5toOFS
*
V
*
V
*
V
Oto -IOVS
*
V
*
V
*
V
+1.5;-2
MULTIPLYINGCHARACTERISTICS'o
V ANALOG (1) Input Impedance
V ANALOG (2) Input Impedonce
V ANALOG (I) Input Rxnge(Pin 14):
V ANALOG (2) ~ OV
to
V ANALOG(2) ~ - 5V
to
VANALOG (2) ~ - IOV
VANALOG (2) Input Rxnge (Pin 16):
VANALOG(l) ~ OV
to
VANALOG(I) ~ -2.5V
to
VANALOG(I) ~ -5V
Analog Feedthrough otloAC (Output)
(V ANALOG (I) ~ 5V p.p;
All Digital Inputs @"O")
At l.4MHz Input Frequency
At lOMHz Input Frequ~
FS Analog Bondwidth (3dB)
0.024
0.1
10
POWER REQUIREMENTS
+15V ±3%
-15V ±3%
Power Dissipation
Power Supply Rejection Ratio
60(72)
25(35)
1.3(1.6)
0.01 (0.05)
TEMPERATURE RANGE
Operating (Case)
Storage
-25to +85
-55to+150
PACKAGEOPTION"
DH·24B
HDM·1210-BD
For applications assistance,
*
*
to
+5to -5FS·
to
+ 10toOFS
call
Computer
.*
*
·
·
*
*
-55to+100
*
HDM·12IOSD
HDM-I2\OSDB
Labs Division at (919) 668·9511.
2-472 DIGITAL-TO-ANALOG CONVERTERS
IRL (Pin 23) connected to I oAc (Pin 24).
ZCurrent output into short circuit.
inputs at "0" and VANALOG (1)@ -SV.
"Bit inputs at ,,} .. and VANALOG (1)@OV.
sSetding times shown are slightly longer at low levels of analog input,
6Jtecovery time shown is for O.SV analog overdrive at VANALOO (1)
with V ANALOG (2) grounded (see text).
1Value which is shown for digital "0" for Bits 3-12. Bit 1 = S.OmA;
Bit 2 = 2.SmA.
BpS accuracies are ± 1% when using V ANALOG (2) input.
3Bit
±3(±6)
±3(±6)
±20(±50)
±2(±5)
±3.5(±8)
Gain
DigitalOffset2•3
NOTES
%FS
%FS
MHz
mA(mox)
mA(mox)
W(max)
%N(mox)
°C
"<:
l17wo..quadrant and four-quadrant multiplying requires external
op amp operating in bipolar mode.
IISee Section 14 for package outline information.
*Specifications same as HDM-1210BD.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Supply Voltages . . . . . . . . . . . . . . . . . . . . . ±18V
Logic Inputs
Digital "I" . . . . . . . . , . . . . . . . • . . . . . . +7V
Digital "0" . . . . . . . . . . . . . . . . • . . . . . -0.5V
AnalogIoputs
VANALOG(I) ...................... -w
VANALOG (2)
-12V
Junction Temperature . . . . . . . . . . . . . . . . . +165"<:
.....................
PIN DESIGNATIONS
(As Viewed from Bottom)
PIN
24
23
22
21
20
19
la
17
16
IS
14
13
FUNCTION
IDAC (OUTPUT)
R..
10VSPAN
GROUND
GROUND
GROUND
GROUND
-1SV
VANA1.OG (2)
AMPUFIERGROUND
VANALOGll)
+lSV
PIN
I
2
3
4
5
6
7
a
9
10
II
12
FUNCTION
BIT 1 (MSB)
BITZ
BIT3
BIT 4
BITS
BIT 6
BIT7
BIT a
BIT9
BITIO
BIT"
BITl2(LSB)
Theory of Operation - HDM-121 0
THEORY OF OPERATION
Refer to the block diagram of the HDM-1210 D/A Converter.
The HDM-I21O uses the analog input voltages to set the reference
current, designated as lREF in the block diagram. Since this
reference current is limited to 1.25mA, maximum inputs applied
to V ANALOG (1) (Pin 14) and VANALOG (2) (Pin 16) are also
limited. When VANALOG (2) is open or grounded, the maximum
input at VANALOG (I) is - 5V; when V ANALOG (1) is open or
grounded, maximum input at V ANALOG (2) is -IOV.
If some combination of voltages in excess of those cited above is
applied to the analog inputs, the analog output becomes limited
to zero and remains at that value until the excessive analog
input(s) is removed.
The output of the unit will not be limited if:
-1 25 A <: VANALOG (1)+ VANALOG (2) <: OmA
.m_
4k
8kPermanent damage to the HDM-1210 may take place if the
input at VANALOG (1) exceeds + IV with VANALOG (2) open or
grounded; with VANALOG (1) open or grounded, voltage at
VANALOG (2) should not exceed + 2V.
The amount of overvoltage (up to the levels which may cause
damage) will have an effect on the interval required for the
converter to recover; the larger the overvoltage, the longer the
interval. As shown in the SPECIFICATIONS section, a voltage
of +O.5V overdrive is applied to VANALOG (I) when specifying
recovery time.
Maximum output at I DAC (Pin 24) is a function of the reference
current established by the inputs; with all digit,al inputs at logic
"I", the output current is based on the equation:
There are 4,096 digital steps from zero to full-scale output for
the HDM-1210, calculated with the equation:
lOUT = (D)(8.192)(IREF)
where
D = 0 to I digital word in 4,096 steps (O.024%/step)
The two analog inputs at Pins 14 and 16 provide various offsetting
capabilities which allow the HDM-1210 to accommodate either
unipolar or bipolar input operation. When one of these inputs is
properly offset to a negative voltage, the other input can be
used for both negative and positive inputs. lREF is still limited
to 1.2SmA, which limits the total output to the range from 0 to
IO.24mA. Examples of outputs versus various inputs are shown
in Table I.
Voltage@
VANALOG(I)
(Pin 14)
Voltage@
VANALOG (2)
(Pin 16)
D/A Output@Pin24
All "I"
All "0"
Digital Input Digital Input
OV
-SV
Ground
0mA
+2.5V
-2.5V
-5V
+5V
OV
-IOV
Ground
OV
-IOV
0mA
+5V
-5V
0mA
+IOV
OV
0mA
-2.SV
-5V
+10.24mA
0mA
0mA
0mA
OmA
+1.024mA
0mA
0mA
0mA
0mA
+1O.24mA
+IO.24mA
+1O.24mA
+IO.24mA
0mA
0mA
0mA
0mA
0mA
0mA
lOUT (max) = lREF (8.192)
Table I. Dutput vs.lnputs
where
IREF =
_. V ANALOG (2)
- V ANALOG (1)
4kn
+
8kn
lREF (max) is 1.25mA; therefore, maximum output current is
IO.24mA.
There are two methods of obtaining a voltage output from the
current output HDM-I21O. The first method simply requires
connecting a load resistor from Pin 24 to ground, as shown in
Figure 2.
This characteristic of the HDM-1210 means output current can
be digitallt adjusted, just as it is in a conventional DIA which
has a variable maximum output current.
CURRENT CELLS
& Rl2R LADDER
lOUT
DIGITAL
INPUT
4k
,
'REF
v,o-_'V'wo--
\.
-3.0
D••
"
o
w
~
~
~
~
H
"'ro
~
TIME-ns
Figure 7. Input for Circuit in Figure 3
"
~
0.0
\
/1 J.=J
IJ/ ,...
\\
.\'
'\ ~
~
o
w
~
J /'
,.>-!?I
II'?'
~
~
1\
,,~
~,
II V
~
D••
1/
~
I--- J'-,
1c:J
O.S
D••
-4.0
---
/ V
0.6
0.4
I
-5.0
~
0.7
I
L
V
-- --
"-
\
l"'-.
~
' ....
tEl
~
H
ro
~
"
~
TIME-ns
Figure 8. Outputs of Circuit in Figure 3
DIGITAL-TO-ANALOG CONVERTERS 2-475
The input signal at VIN in Figures 5 and 6 is shown in
Figure 9.
5.0
/
4.0
Refer to Figure 11.
" "
\.
/
\
2.0
1.0
~
0
I
I
\
I
II
II>
!:i
g
\
-1·0
-1
-2
I
\
-2.0
I
\
-3
\
-4
/
\.
-4.0
o
w
~
~
~
~
" .....
~
~
-6
00
~
~
o
./
\
r-- r-....
,
w
D
~
j
........ t--......
\
I
I
\
~0
~
~
~
~
\
A
\
I
rV
-
-5
/
i
~ !~
\
-3.0
-5.0
\
,\ /
~y
I'(;'
\
\
\
I
/ - - f@
~
~
,
//
\
I.
\
0.0
>
r'0
/
3.0
"-
~
V
~
/
~
~
~
TIME-ns
TlME-ns
Figure 9. Inputs for Circuits In Figures 5 and 6
Figure
The outputs of the two-quadrant multiplying circuits of
Figure 5 are shown in Figure 10, with the outputs labeled for
various digital multiplying inputs.
1,.
Outputs of Circuit in Figure 6
Four-quadrant multiplying of an analog input is shown in this
illustration. The changes in output which result from variations
in the digital inputs are labeled as described earlier.
SETTLING VERSUS INPUT
f
I
/
I~
II>
~
0
1$/
....
The SPECIFICATIONS table and footnote 5 point out digital
settling time is affected by the level of the analog input signal.
This characteristic of the HDM-I21O is shown in Figure 12.
- r0
r@'
----
i(c)" \
~
I;;
E
-5.0
\\
~
-1
~
~1
\\ r-....
-2
\
-3
-4
-5
-6
o
w
~
~
I 'r-.....
~
~
~
,
I-- f"'"
.:: -1.0
/~'
, " -- //
, V
~
~
~
TlME-ns
Figure 10. Outputs of Circuit in Figure 5
~
!
I ' ........
~
......
J
_
..........
.......
r--.....
-0.1
30
~
50
60
70
80
90
100
110
1~
NANOSECONDS
Figure 12. Digital Settling Time to ± 1%
Settling is fastest with high levels of analog input; settling time
increases as levels decrease, but there is no direct ratio between
the two variables.
ORDERING INFORMATION
There are three versions of the HDM-1210 D/A converter, all in
hermetic ceramic DIP housings; with the exception of temperature
ranges, all models meet the same electrical specifications.
The HDM-1210BD operates over a temperature range of -25"C
to + 85·C; the HDM-1210SD operates over a range of - 55"C
to + 1OO·C. For this latter temperature range and military screening
of components, order part number HDM-1210SDB; contact the
factory for details.
2-476 DIGITAL-TO-ANALOG CONVERTERS
Ultrahigh-Speed
12-Bit D/A Converter
HDS-1250 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
35ns Settling Time
10mA Output Current
Monotonic Over Temperature
Available to MIL-STD-883
APPUCATIONS
Waveform Generation
Analytical and Medical Instrumentation
Military Equipment
Display Systems
HDS-12S0 FUNCTIONAL BLOCK DIAGRAM
BITl
(MSB)
BIT2
2
GROUND
R LOAD (200.0.1
CURRENT
OUTPUT
DIGITAL
INPUTS
CURRENTSTEERING
SWITCHES
PRECISION
RESISTOR
NETWORK
BIPOLAR
OFFSET
+15V
-15V
GENERAL DESCRIPTION
The HDS-12S0 D/A Converter is an ultrahigh-speed current
output digital-ta-analog converter using reliable thin film construction in a 24-pin hermetically sealed hybrid package.
Active laser trimming assures precise 12-bit operation over a
wide temperature range, and the device is guaranteed to be
monotonic over its entire operating range. These characteristics
and the assembly and testing in a MIL-STD-1772-certified
facility make the HDS-12S0 attractive for a variety of military
and high-reliability applications.
Full-scale output is lO.24mA, making the converter useful for
directly driving capacitive loads and transmission lines. AD
internal precision reference eliminates the need for external
circuits for most applications.
DIGITAL-TO-ANALOG CONVERTERS 2-477
E
SPEC IFICAli 0NS
(willi nomiIaI supplies, lIIIess otIawise noIIId)
Parameterl ,2 (Conditions)
SubGroup
Temp
Min
HDS-12S0KD 1
Typ
Max
12
RESOLUTION
(FS = Full Scale)
±0.5
± 1.5
±0.5
+2.0
LSB
LSB
LSB
LSB
+ 1.5
±0.25
+0.5
±O.I
+J.S
±0.25
....A
%FS
±30
±60
±30
±60
ppml"C
+ 25°C
±0.25
±0.5
±0.25
±0.5
%FS
5,6
Full
±15
±30
±15
±30
ppml"C
4
+ 25°C
±0.1
±0.25
±0.1
±0.25
%FS
4
+ 25°C
±0.1
±0.2
±0.1
±0.2
%FS
5,6
Full
±75
ppmfOC
+ 25°C
Full
+ 25°C
Full
±0.25
± 1.0
±0.25
±0.5
±0.5
±J.S
±0.5
+2.0
1,2,3
4
Full
+ 25°C
+0.5
±O.I
5,6
Full
4
POWER REQUIREMENTS
./ +VsUPPLy (Bitsl-12Off;
+ 15V)
j - V SUPPLY (Bits 1-12 Off;
-15V)
- 1.0
Full
Full
1
2
3
1
2,3
1
2,3
BIN/OBN
TTL and SV CMOS
+0.8
+0.8
V
V
40
100
40
7.0
7.0
3.5
3.5
40
100
40
7.0
7.0
3.5
3.5
....A
f,I.A
....A
rnA
mA
rnA
rnA
+2.5
+2.5
+ 25°C
+ 125°C
-55°C
+25°C
Full
+ 25°C
Full·
+ 25°C
+ 25°C
10.24
±5.12
10.24
±5.12
mA
rnA
+25°C
+ 25°C
+25°C
+25"C
+ 1.024
±0.512
+ 1.024
±0.512
V
V
V
9
+ 25°C
+ 25°C
1
2,3
I
2,3
+2SoC
Full
+ 25°C
Full
-2.0
+J.S
200
-2.0
+J.S
200
35
35
35
35
54
54
19
19
54
54
19
19
(Continued on next page)
2-478 DIGITAL-TO-ANALOG CONVERTERS
-1.0
±75
BIN/OBN
TTLand5VCMOS
OUTPUT
CurrentFS
Unipolar
Bipolar
VoitageFS 3
Unipolar
Bipolar
Compliance
Impedance
SETTLING TIME
Current (To ±0.025%FS)
jVoltage(To ±O.I%FS; lLSB
step at midscale; Internal R LOAD)
....A
±0.25
± 1.0
±0.25
±0.5
4
5,6
4
5,6
"0"
jBitl"O"
(Bits 1- 12 @o.oV)
j Bits2-12 "0"
(Bitsl-12@0.OV)
2.5
2.5
DATA INPUTS
Coding
Logic Compatibility
Logic Levels
"1"
Logic Loading
j Bits 1-12"1"
Units
Bits
12
LSBWEIGHT
ACCURACY
j Integral Linearity
(loUT; Best Fit Line)
j Differential Linearity
(lOUT; All Major Carries)
UnipolarFS
j Offset (Bits 1- 12 Off)
j Gain (Bits 1-12 On; lOUT
or VOUT with Internal Load)
j Gain vs. Temperature
(Bits 1- 12 On; lOUT)
BipolarFS
j Offset (Bits 1-12 Off;
Pins 20 and 22 Connected)
j Offset vs. Temperature
(Bits 1- 12 Off; Pins
20 and 22 Connected)
j Gain (Bits 1-12 On;
Pins 20 and 22 Connected)
j Zero (Bit IOn; Bits 2 - 12
Off; Pins 20 and 22 Connected)
j Zerovs. Temperature (Bit 1
On;Bits2-12 Off; Pins 20
and 22 Connected)
HDS-12S0TM & TMl883B2
Typ
Max
Min
n
ns
ns
rnA
rnA
rnA
mA
HDS-1250
Parameter l ,2 (Conditions)
JPower Supply Rejection
Ratio (PSRR) (Bits 1-120n;
±Vs= ±14.5, ±IS.SV)
SubGroup
Temp
1
2,3
+ 25°C
Full
Min
HDS-1250KD l
Typ
Max
HDS-1250TM & TMl883B '
Min
Typ
Max
0.06
0.08
0.06
0.08
%1%
12
34
12
34
°C/W
°C/W
THERMAL RESISTANCE
Junction to Case (6 jc)
Case to Air (6e. ) \
MEAN TIME BETWEEN
FAILURES (MTBF)5
2.7 x 106
PACKAGEOPTIONS 6
DH-24B
M-24A
HDS-12S0KD
NOTES
'HDS-1250KD specifications preceded by a check (j) are tested at + 25°C
ambient temperature; performance is guaranteed over case temperature
range of 0 to 70OC.
2HDS-1250TM and HDS-1250TMl883B specifications preceded by a
check Cj) are tested at - SS"C case, + 2S"C ambient, and + 125°C case
temperatures unless otherwise indicated (See Subgroups).
3With internal 200.0 load resistor. Other voltages within the compliance
range may be obtained with an external load resistor using following:
VOUT
= lOUT X REQUIVALENT
Where: REQUIVALENT = 200n internal impedance
in parallel with external load resistance.
~be relationship between the device package and outside environment (eca )
varies with the application. Value shown is based on measuring case
temperature with supply voltages applied to a device in a ZIF socket
mounted on a standard uBI" burn~in board.
'MTBF calculated for HDS-1250TM/883B using MIL-HNBK 217D;
Ground Fixed; Temperature (ambient) = 25°C.
'See Section 14 for package outline information.
Specifications subject to change without norice.
Units
%/%
Hours
HDS-1250TM
HDS-12S0TM/883B
EXPLANATION OF SUBGROUPS
Subgroup 1 - Static tests at + 25°C.
(10% PDA calculated against Subgroup 1 for high-reI versions)
Subgroup 2 - Static tests at maximum rated temperature.
Subgroup 3 - Static tests at minimum rated temperature.
Subgroup 4 - Dynamic tests at + 25°C.
Subgroup 5 - Dynamic tests at maximum rated temperature.
Subgroup 6 - Dynamic tests at minimum rated temperature.
Subgroup 7 - Functional tests at + 25°C.
Subgroup 8 - Functional tests at maximum and minimum
rated temperatures.
Subgroup 9 - Switching tests at + 25°C.
Subgroup 10 - Switching tests at maximum rated temperature.
Subgroup 11 - Switching tests at minimum rated temperature.
Subgroup 12 - Periodically sample tested.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ( + V s)
Supply Voltage ( - V s)
Digital Inputs . . . . .
Storage Temperature .
Lead Soldering (lOsec)
Junction Temperature .
.. +17V
. . -17V
o to +8V
- 5SOC to + 125°C
+300OC
. . . .. + 16SOC
PIN DESIGNATIONS
(As viewed from bottom)
PIN
24
23
22
21
20
19
18
17
16
15
14
13
FUNCTION
+15V
-15V
BIPOLAR OFFSET
RLoAo (200fi)
OUTPUT
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
PIN
1
2
3
4
5
6
7
8
9
10
11
12
FUNCTION
BIT1(MSB)
BIT2
BIT 3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT 11
BIT 12 (LSB)
DIGITAL-TO-ANALOG CONVERTERS 2-479
•
THEORY OF OPERATION
Refer to the HDS-12S0 Block Diagram.
The HDS-12S0 consists of an array of high-speed, current-steering
switches and a precision R2R resistot network. An internal
Voltage reference provides current which is switched between
the digital input and the resistor network, depending on digital
input level. Full-scale output current is 10.24mA, scaled by the
binary digital input word.
or::=.::.:.......
-;~ OUTPUT
:to.s12VFSOR
::t:5.1ZmAF$
The parallel combination of the R2R network and the internal
load resistor (au causes the HDS-12S0 D/A Converter to have
a unipolar output voltage of + 1.024V. A S.I2mA current sink
contained within the device provides a bipolar function (Pin 22)
when it is connected to the output pin.
ANALOG OUTPUT CIRCUITS
The HDS-12S0 is primarily a current-output DAC which can be
operated in either a unipolar or bipolar mode. The connections
for unipolar operation are shown in Figure 1.
Figure 2.
5-10k.{)
>r=-=::..:....+-OUTPUT
OVto +-1.G24VOR
'ao:;:....--I.vg=
OTa +10.24mA
(-R1x10.24mA)
DIGrTAL
INPUTS
Figure 3.
Figure 1.
This technique allows the fastest possible settling of the combiWhen a load resistor is connected between the output (Pin 20)
and ground, the HDS-12S0 can also function as a voltage DAC.
Its output voltage must remain within a certain tolerance or the
linearity of the device will be affected adversely. This "compliance"
voltage range for the HDS-12S0 is -2.0Vto +1.SV. The voltage
output of OV to + 1.024V provided by the internal 2000 load is
well within the compliance range of the device.
nation, which is approximated by:
Bipolar use of the HDS-12S0 is illustrated in Figure 2.
The gain of the amplifier can be controlled most accurately by
varying the ratio between current flow through the feedback
resiator (RI) and the lO.24mA current output of the DAC. The
amplifier's output offset can be adjusted by sinking current
from or sourcing current to the summing node through a potentiometer connected to the positive and negative supply voltages.
The value of R3 in Figure 2 will be based on the desired range
of adjustment.
An alternate way of achieving a voltage output with the HDS-12S0
is to use an operational amplifier as a current-to-voltage converter
on the output as shown in Figure 3.
The DAC output is connected directly to the summing node of
the amplifier; the output impedance of the R2R network serves
as the Thevenin equivalent feed forward resistance in the circuit.
2-480 DIGITAL-TO-ANALOG CONVERTERS
Where: Ts = Total settling time
TD = DAC settling time
T A = Op Amp settling time
HDS-1250
DESIGN RULES
There are certain circuit layout rules that must be observed to
obtain successful high-speed data conversion. Heavy ground
currents and fast switching speeds can combine to present a
formidable challenge to noise-free performance unless precautions
are taken.
The foundation for a good high-speed design lies in the ground
plane. The HDS-12S0 should be mounted on a PC board that
has one side (or layer) dedicated as a large, low-impedance
ground plane. This helps ensure that ground loops and differences
in ground potential do not develop in the vicinity of the DAC
and erode its effective linearity.
To avoid loss of resolution due to noise, it is imperative to
decouple the power supply pins of the HDS-12S0 directly to the
ground plane as physically close to the package as possible.
Minimum decoupling should consist of a IO ....F tantalum capacitor
and a O.OI ....F ceramic capacitor in parallel at each supply voltage
pin. This will help suppress both high- and low-frequency noise
components in the supply voltage.
IT a voltage output op amp is used, locate it as close as practical
to the DAC output to minimize the length of the summing node
circuit trace. At high switching speeds, parasitic capacitance and
inductance become critical factors in determining settling characteristics, and precautions must be observed to limit their
effects. Any offset control functions connected to the summing
node must also be as short as possible to minimize output
ringing.
When selecting resistors to use as the output load or as feedback
for the op amp, the designer should bear in mind that the tem-
perature coefficient of these resistors will materially affect the
overall temperature stability of the data conversion design. Resistor
grades should be selected to support the allotted error budget of
the system.
Output "glitches" are another anomaly that plague the success
of high-speed DAC designs. These aberrations in the output are
generally caused by skewing in the transition points of the parallel
bit inputs. Small differences in the start of switching among the
input bits cause the DAC output to try to respond with each
change.
The glitches appear in the output as small triangular waveforms
at the bit transitions, and are measured in terms of area as a
function of voltage and time. Bit-weighting causes glitch impulse
to be most significant at the Bit I transition, and it diminishes
by half at each successive bit. This causes the amplitudes of the
glitches to be code-dependent, making it virtually impossible to
eliminate them with a ruter.
Glitches of 100-500 pico-volt seconds are common for high-speed
TTL DACs and can have an undesirable effect on the reconstructed
signal purity in some applications.
There are two methods for minimizing glitch impulse in applications using the HDS-12S0. In one, a set of high-speed registers
in front of the bit inputs will reduce the amount of skew in the
input data. These registers should be mounted physically close
to the HDS-12S0 package, and Bits 1-4 should be located in a
single quad package.
The second method is to utilize a deglitching amplifier on the
output of the DAC. See Figure 4.
LOW-PASS
FILTER
(OCTO
ONE-HALF
CLOCK
FREQ.1
HTS-0010
T/H
DEGLITCHED
ANALOG
OUTPUT
HOLD
COMMAND
Figure 4.
This deglitching circuit includes the input registers mentioned
above and a high-speed track-and-hold (TIH) amplifier. The
HTS-OOIO shown is timed to "hold" a constant output during
the time of the glitch activity; and update the output after DAC
settling has occurred.
The deglitching amplifler introduces its own switching anomalies,
but they occur at the update rate of the input data and are
beyond the reconstructed bandwidth of interest.
DIGITAL-TO-ANALOG CONVERTERS 2-481
_
..
DATA
CHANGING
,...A-,....:.....----"""r-----~r__--
DIGITALINPUT
--V______-III'--_
X _~~'___
V
--A
HDS-1250 ANALOG OUTPUT
CLOCK
HOLD
TRACK
DEGUTCHED OUTPUT
Figure 5.
These aberrations can be flltered with a bandpass fllter at the
output of the (TIH) deglitching amplifier. The fllter should be
selected to pass a frequency range from dc to one-half the DAC's
update rate.
interest. Their effects can be eliminated with a bandpass fllter at
the output of the HTS-OOIO.
For a better insight into the timing involved, refer to Figure S.
ORDERING INFORMATION
Three models of the HDS-12S0 D/A Converter are available; all
As shown, the analog output of the HDS-12S0 will attempt to
follow the switching of the digital inputs as they change; if time
skew exists among the input bits, the glitches which result will
be pronounced. The clock signal shown in Figure 5 serves as a
strobe for the input register and also causes the T IH to switch
from a "track" to "hold" mode of operation. Mter the glitch on
the output of the HDS-12S0 has subsided, the TIH will return
to the track condition and slew to the new value established by
the most recent digital input changes.
Minor switching transients introduced by the action of the TIH
occur at the input data rates and are outside the passband of
2-482 DIGITAL-TO-ANALOG CONVERTERS
are manufactured in a MIL-STD-1772-certified facility.
Model HDS-12S0KD operates over a case temperature range of
o to + 70"C; the KD suffix indicates a 24-pin hermetic ceramic
DIP package.
For operating case temperatures of - 55°C to + 125°C, order
either the HDS-12S0TM or the HDS-12S0TMl8838; both units
are housed in hermetic 24-pin metal packages. The 8838 designation indicates units which are intended for military or other
high-reliability applications; these devices are manufactured and
screened per the requirements of MIL-STD-883.
AID Converters
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . . .
3-3
...................... .
3-9
Orientation
AD570/571 - 8- and 10-Bit Analog-to-Digital Converters
3 - 15
AD572 - 12-Bit Successive Approximation Integrated Circuit AID Converter
3 - 21
AD573 - 10-Bit AID Converter . . . . . . . . . . . . . . . .
3 - 29
AD574A - Complete 12-Bit AID Converter . . . . . . . . . .
3 - 37
AD575 - Complete 10-Bit AID Converter with Serial Output
3 - 49
AD578 - Very Fast Complete 12-Bit ND Converter
3 - 57
AD579 - Very Fast Complete 10-Bit ND Converter
3 - 63
AD670 - Low Cost Signal Conditioning 8-Bit ADC
3 - 69
AD673 - 8-Bit AID Converter
.......... .
3 - 81
AD674A - Complete 12-Bit AID Converter . . . . .
3 - 89
AD678 - 12-Bit 200 KSPS Complete Sampling ADC
3 - 99
AD679 - 14-Bit 100 KSPS Complete Sampling ADC
3 - III
AD770 - 200 MSPS Wideband 8-Bit AID Converter
3 - 123
AD779 - 14-Bit 100 KSPS Complete Sampling ADC
3 - 135
AD1l70 - High Resolution Programmable Integrating ND Converter
3 - 147
AD1l75K - High Accuracy 22-Bit Integrating ND Converter
3 - 159
AD1376 - Complete High Speed 16-Bit AID Converter
3 - 167
AD1377 - Complete High Speed 16-Bit AID Converter
3 - 175
AD1380 - Low Cost 16-Bit Sampling ADC . . . . . .
3 - 183
AD1678 - 12-Bit 200 KSPS Complete Sampling ADC
3 - 191
AD1679 - 14-Bit 100 KSPS Complete Sampling ADC
3 - 203
ADI779 - 14-Bit 100 KSPS Complete Sampling ADC
3 - 215
AD5200/5210 Series - 12-Bit Successive Approximation High Accuracy AID Converters.
3 - 227
AD756917669 - LC 2 MOS Complete 8-Bit Analog 110 Systems
3 - 233
AD7572 - LC2 MOS Complete High Speed 12-Bit ADC
3 - 253
AD7575 - LC2MOS 5 "'s 8-Bit ADC with TrackIHold . .
3 - 265
AD7576 - LC2 MOS 10
3 - 269
"'S
,.,.,p-Compatible 8-Bit ADC ..
AD7578 - CMOS 12-Bit Successive Approximation ADC
3 - 273
AD757917580 - LC 2MOS lO-Bit Sampling AID Converters .
3 - 279
AD7581 - CMOS ",P-Compatible 8-Bit 8-Channel DAS
3 - 295
.
AD7582 - CMOS 12-Bit Successive Approximation ADC
3 - 303
AD7672 - LC2 MOS High Speed 12-Bit ADC ..
3 - 309
AD7769 - LC2MOS Analog 110 Port . . . . . . . . . . .
3 - 325
AD7772 - LC 2 MOS Serial Output 12-Bit ADC . . . . . .
3 - 341
AD7820 - LC 2MOS High Speed ",P-Compatible 8-Bit ADC with Track/Hold Function
3 - 357
AD7821 - LC 2MOS High Speed ",P-Compatible 8-Bit ADC with Track/Hold Function
3 - 367
AD782417828 - LC 2MOS High Speed 4- & 8-Channel 8-Bit ADCs .
3 - 379
AD7870 - LC2 MOS Complete 12-Bit 100 kHz Sampling ADC . . . . . . . . . . .
3 - 391
AD787117872 - LC 2MOS Complete 14-Bit Sampling ADCs
3 - 407
........... .
AD7878 - LC2 MOS Complete 12-Bit 100 kHz Sampling ADC with DSP Interface
3 - 419
AD9000 - High Speed 6-Bit AID Converter
3 - 435
..... .
AD9002 - High Speed 8-Bit Monolithic AID Converter
3 - 443
AD9003 - 12-Bit 1 MHz AID Converter . . . . . . . .
3 - 451
ANALOG-TO-OIGITAL CONVERTERS 3-1
II
Page
AD9005 - 12-Bit 10 MSPS AID Converter . . . .
3 - 459
AD9006/9016 - High Speed 6-Bit AID Converters
3-467
AD9011 - 8-Bit 100 MSPS AID Converter . . . .
3 - 483
AD9012 - High Speed 8-Bit TTL AID Converter
3 - 489
AD9028/9038 - High Speed 8-Bit AID Converters
3 -497
AD9048 - Monolithic 8-Bit Video AID Converter
3 - 509
AD9502 - Hybrid RS-170 Video Digitizer . . . .
3 - 517
AD%88 - High Speed 4-Bit Monolithic ADC
3 - 525
..
AD ADC71/72 - Complete High Resolution 16-Bit AID Converters
3 - 531
AD ADC80 - 12-Bit Successive Approximation Integrated Circuit AID Converter
3- 539
AD ADC84/85/AD5240 - Fast Complete 12-Bit AID Converters .
ADCI1301l131- 14-Bit High Speed Analog-to-Digital Converters
3 - 547
3 - 555
ADC1140 - Low Cost 16-Bit Analog-to-Digital Converter
... .
3 - 559
CAV-I040 - 10-Bit Video Analog-to-Digital Converter . . . . . .
3 - 563
CAV-1205 - 12-Bit 5 MHz Eurocard Analog-to-Digital Converter
CAV-1220 - 12-Bit Video Analog-to-Digital Converter . . . . . .
3 - 567
3 - 569
HAS-1201 - 12-Bit 1 MHz Analog-to-Digital Converter
.... .
3 - 573
HAS-1202/1202A - Ultrafast Hybrid Analog-to-Digital Converters
3 - 579
HAS-1204 - Ultrahigh Speed 12-Bit AID Converter
...
3 - 583
HAS-1409 - 14-Bit 125 kHz Analog-to-Digital Converter.
3 - 587
3 - 593
MOD-1205 - 12-Bit Video Analog-to-Digital Converter
3-2 ANALOG- TO-DIGITAL CONVERTERS
Selection Guide
Analog-to-Digital Converters
GENERAL PURPOSE ADCs
Res
Bits
Cony
Time
,..s
Int
SHA
BW
kHz'
Page
Comments
AD7821
AD7569
8
8
0.66
2
100
200
0-5 V, Ext
Int
8, ,..p
8, ,..p
N,P,Q
E,N,P,Q
C, I
C,I,M
3-367
3-233
*AD7669
8
2
200
Int
8, ,..p
N,P
C,I,M
3-233
AD7820
*AD7769
8
8
2
2.5
7
200
0-5 V, Ext
Ext
8, .,..p
8, ,..p
E,N,P,Q,R
N,P
C,I,M
C, I
3-357
3-325
AD7824
AD7828
AD7575
AD670
8
8
8
8
2.5
2.5
5
10
10
10
50
0-5 V, Ext
0-5 V, Ext
1.23 V, Ext
Int
8,
8,
8,
8,
,..p
,..p
f-LP
,..p
N,Q
E,N,P,Q
E,N,P,Q
D,E,N,P
C,I,M
C, I, M
C, I, M
C, I, M
3-379
3-379
3-265
3-69
AD7576
AD570
AD673
AD7581
AD579
AD7579
AD7580
AD571
AD573
AD575
*AD9005
8
8
8
8
10
10
10
10
10
10
12
25
30
66.7
1.8
18.5
18.5
25
30
30
0.1
1.23 V, Ext
Int
38000
-5 V-(-15 V), Ext
10 V, Int
2.5 V, Ext
2.5 V, Ext
Int
Int
Int
Int
8, f-LP
8
8, f-LP
8, f-LP
10/Seriai
8, ,..p
10, ,..p
10
8/10, ,..p
Serial
12
E,N,P,Q
D
D,N,P
D,N
D,N
E,N,P,Q
E,N,P,Q
D
D,N,P
D,N
M
C, I, M
C,M
C,M
C, I
C, I
C,I,M
C,I,M
C,M
C,M
C,M
C,M
3-269
3-15
3-81
3-295
3-63
3-279
3-279
3-15
3-29
3-49
3-459
CMOS, Bipolar or Unipolar Operation
CMOS, Complete 110 Port with DAC,
ADC, SHA, Amps and Reference
CMOS, Complete 110 Port with 2 DACS,
ADC, SHA, Amps and Reference
CMOS, 8-Bit Sampling ADC
CMOS, Two-Channel ADCIDAC with
Output Amplifiers
CMOS, 4 Channel, 8-Bit Sampling ADC
CMOS, 8 Channel, 8-Bit Sampling ADC
CMOS, Low Cost
Single Supply, Including In-Amp and
Reference
CMOS, Low Cost
15000
15000
10000
2000
Int
Int
Int
Int
12
12
12
12
Card
Card
M
M
C
C
C
C,M
3-567
3-593
3-451
3-573
Model
:h
5;
r-
aG)
~
S2
G)
~
r-
8<:
r:ii
:JJ
r;j
Bl
1>
V,)
CAV-1205
MOD-1205
AD9003
HAS-1201
12
12
12
12
10
0.2
0.5
Reference
Voltage
IntlExt>
Bus
Interface
Bits'
Package
Options'
Temp
RangeS
1m
25
25
CMOS 8-Bit ADC
CMOS, Low Cost 10-Bit Sampling ADC
CMOS, Low Cost IO-Bit Sampling ADC
Complete 12-Bit ADC with TfH, Reference
and Timing Circuitry
12-Bit, 5MSPS Eurocard
12-Bit, 5MSPS Video ADC
12-Bit, IMSPS ADC. Single 40-Pin DIP
12-Bit, IMSPS ADC
~x indicates that the internal SHA bandwidth is not specified in kHz.
Ext indicates external reference with the range of voltages listed where applicable. Ext CM) indicates external reference with multiplying capability. Int indicates reference is internal. A voltage value is given if the
reference is pinned out.
3This column lists the data fonnat for the bus with "/-LP" indicating microprocessor capability-i.e., for a 12-bit converter 8/12, /-LP indicates that the data can be fonnatted for an 8-bit bus or can be in parallel (12
bits) and is microprocessor compatible.
'Package Options: D-Side-Brazed Dual-In-Line Ceramic; E-Leadless Chip Carrier; M-Metal Hermetic Dual·In·Line; N-Plastic Molded Dual-In-Line; P-Plastic Leaded Chip Carrier (PLCC); Q-Cerdip; R-Small
Outline Plastic (SOIC).
'Temperature Ranges: C-Commercial, 0 to +70°C; I-Industrial, -40°C to +85 oC (Some older products -25°C to +85°C); M-Military, -55°C to + 125°C.
Boldface Type: Product recommended for new design.
*New product since the publication of the 1987/1988 Databooks.
II
l'
-I:.
):.
~
r-
0
Selection Guide
Analog-to-Digital Converters
'il
GENERAL PURPOSE ADCs
d
~
~
r-
Model
Res
Bits
()
0
<:
~
::0
;;:j
::0
t/)
Conv
Time
,...S
Int
SHA
BW
kHz!
Reference
Voltage
IntlExr
Bus
Interface
Bits 3
Package
Options'
Temp
RangeS
Page
Comments
Int
Int
Int
10 V, Int
-5 V, Ext
12
12
12
12
12, ,...p
D
M
D
D,N
E,N,P,Q
C,I,M
C,M
C,I,M
C,M
C,I,M
3-579
3-583
3-579
3-57
3-309
12-Bit, 641kHz ADC
12-Bit, 500kHz ADC. Single 40-Pin DIP
12-Bit, 349kHz ADC
Complete, 3,...s, 12-Bit ADC
CMOS, Unipolar or Bipolar, -12 V, +5 V
Supply
BiMOS, High-Impedance, High-Bandwidth
Sampling Input, 10 V Range
BiMOS, 12-Bit Sampling ADC, ac
Characterized
Industry Standard
CMOS 12-Bit ADC
HAS-1202A
HAS-1204
HAS-1202
AD578
AD7672
12
12
12
12
12
1.6
2
2.9
3
3
AD678
12
4
X
-5 V, Int
12, ,...p
D,N,P
C
3-99
*AD1678
12
4
500
Int
8/12, ,...p
D,N,P
C
3-191
AD5240
AD7572
12
12
5
6.3 V, Int
-5.25 V, Int
12
12, ,...p
D
E,N,P,Q
C, I
C,I,M
3-547
3-253
AD1332
12
8
125
-5 V, Int
12, ,...p
D
AD7870
AD7878
12
12
10
10
X
X
3 V, Int
3 V, Int
8/12/Serial, ,...p
12, ,...p
E,N,P,Q
E,N,P,Q
C,I,M
C,I,M
3-391
3-419
*AD7772
*AD1334
12
12
10
15
X
235
5.25,lnt
-5 V, Int
Serial, ,...p
12, ,...p
E,N,P,Q
D
C,I,M
I
3-341
9-49
ADADC84
ADADC85
AD5210
AD674A
AD368
12
12
12
12
12
10
10
12
C
C,I
I,M
C,M
I,M
3-547
3-547
3-227
3-89
9-19
AD369
7000
9-31
15
15
6.3 V, Int
6.3 V, Int
-10 V, Int/Ext
10 V, Int
40-10006.3 V, Int
12
12, ,...p
12
D
D
D
D
D
12
15
40-1000 6.3 V, Int
12
M
AD572
ADADC80
AD574A
AD363
AD364
12
12
12
12
12
25
30
35
40
50
10 V, Int
6.3 V, Int
10 V, Int
10 V, Int
10 V, Int
12
12
8/12, ,...p
12, ,...p
12, ,...p
D,M
D
D,E,N,P
D
D
I,M
I
C,M
C,M
C,M
3-21
3-539
3-37
9-5
9-5
AD5200
AD7578
12
12
50
100
-10 V, IntlExt
5 V, Ext
12
12, ,...p
D
D,N
I,M
C,I,M
3-227
3-273
13
X
X
12
9-19
Complete 12-Bit 125kHz Sampling ADC
for Digital Signal Processing
CMOS, 100kHz ThroughputCMOS, 100kHz Throughput, On-Chip
FIFO. Serial, Parallel or Byte Output
CMOS, Serial Output 12-Bit ADC
Four Channel 65kHz 12-Bit Sampling ADC
for Digital Signal Processing
Industry Standard
Industry Standard
Industry Standard
Complete 12-Bit ADC
Complete 12-Bit ADC with Programmable
Gains of 1, 8, 64, 512
Complete 12-Bit ADC with Programmable
Gains of 1, 10, 100, 500
12-Bit Successive Approximation ADC
Industry Standard
Complete ADC with Reference and Clock
High Speed 16-Channel, 12-Bit DAS
16-Channel, 12-Bit DAS with
Three-State Buffered Output
Industry Standard
CMOS, lLSB Total Unadjusted Error
GENERAL PURPOSE ADCs
Res
Bits
Conv
Time
!,-s
12
14
14
*AD1679
Bus
Interface
Bits3
Package
Options4
Temp
RangeS
Page
Comments
100
9
10
Reference
Voltage
IntlExt'
5 V, Ext
200-8001nt
X
5 V, Int
12, !,-P
14
14, !1-P
D,E,N,P
M
D,N,P
C,I,M
C
C
3-303
3-587
3-111
14
10
500
5 V, Int
8/14, !,-P
D,N,P
C
3-203
*AD7871
ADC1l31
ADC1l30
14
14
14
10
12
25
X
3 V, Int
Int
Int
8/14/Serial, !,-P
14
14
E,N,P,Q
Module
Module
C,I,M
C
C
3-407
3-555
3-555
CMOS, lLSB Total Unadjusted Error
14-Bit, l25kHz ADC. Single 40-Pin DIP
BiMOS, HiglI Impedance, HiglI Bandwidth
Sampling Input, 10 V Input Range
14-Bit BiMOS Sampling ADC, ac
Characterized
CMOS, 14-Bit, 100kHz Sampling ADC
14-Bit, HiglI Speed ADC
14-Bit, HiglI Speed ADC
DASllS2
DASllS7
DASllS3
DASllS8
*AD1377
14
14
15
15
16
40
55
50
55
10
X
X
X
X
X
10 V,
10 V,
10 V,
10 V,
Int
16
16
16
16
16, Serial
Module
Module
Module
Module
D
I
I
I
I
C
9-73
9-77
9-73
9-77
3-175
AD1376
16
15
Int
16, Serial
V
C
3-167
AD1380
16
20
Int
16, Serial
D
C
3-183
ADC1l4O
16
35
10 V, Int
16
Module
C
3-559
ADADC71
AD ADCn
DASllS9
AD1l70
AD1l7SK
16
16
16
18
22
50
50
55
1000
50ms
6.3 V, Int
6.3 V, Int
10 V, Int
5 V, Int
6.95 V, IntlExt
16
16
16
24
24
D,M
D,M
D
D
Module
C
C,I
I
C
C
3-531
3-531
9-77
3-147
3-159
Model
AD7S82
HAS-1409
AD679
~
~
r-
~
Cl
~
i;!
r-
~
Int
SHA
BW
kHz'
900
X
Int
Int
Int
Int
14-Bit HiglI Accuracy Sampling ADC
Low Power, 14-Bit Sampling ADC
IS-Bit HiglI Accuracy Sampling ADC
Low Power, IS-Bit Sampling ADC
Complete 16-Bit Converter. Industry
Standard Pin Out
Complete, HiglI Speed 16-Bit ADC
Operation over -25°C to +8SoC
Low Cost, 16-Bit Sampling ADC
Operation over -55°C to +8SoC
Temperature Range
16-Bit ADC, Operates over -25°C
to +85°C Temperature Range
Industry Standard
Industry Standard
Low Power, 16-Bit Sampling ADC
7 to 22-Bit Programmable Integrating ADC
HiglI Accuracy, 22-Bit Integrating ADC
'X indicates that the internal SHA bandwidth is not specified in kHz.
'Ext indicates external reference with the range of voltages listed where applicable. Ext (M) indicates external reference with multiplying capability. Int indicates reference is internal. A voltage value is given if the
reference is pinned out.
'This column lists the data format for the bus with "J.LI''' indicating microprocessor capability-i.e., for a 12-bit converter 8/12, fLP indicates that the data can be formatted for an 8-bit bus or can be in parallel (12
bits) and is microprocessor compatible.
'Package Options: D-Side-Brazed Dual-In-Line Ceramic; E-Leadless Chip Carrier; M-Metal Hermetic Dual-In-Line; N-Plastic Molded Dual-In-Line; P-Plastic Leaded Chip Carrier (PLCC); Q-Cerdip; R-Small
Outline Plastic (SOIC).
'Temperature Ranges: C-Commercial, 0 to +70'C; I-Industrial, -40'C to +8S'C (Some older products -2S'C to +8S'C); M-Military, -SS'C to + 12S'C.
Boldface Type: Product recommended for new design.
*New product since the publication of the 1987/1988 Databooks.
rii:xi
itI
i}l
l'
Q'1
II
cr>
0)
».
~
r-
C
Selection Guide
Analog-to-Digital Converters
ct'l
Cj
SAMPLING ADCs
S2
~
~
r-
8<:
~
~
FlI
~
Model
Res
Bits
Conv
Time
JJ.s
max
SHA
BW
kHz
typl
Reference
Volt
InttExr
Bus
Interface
Bits'
Package
Options4
Temp
RangeS
Page
Comments
8, JJ.P
8, JJ.P
N,P,Q
E,N,P,Q
C,I
C,I,M
3-367
3-233
CMOS, Bipolar or Unipolar Operation
CMOS, Complete 110 Port with DAC, ADC,
SHA, AMPs, & Reference
CMOS, Complete 110 Port with 2 DACs,
ADC, SHA, AMPs, & Reference
CMOS, 8-Bit Sampling ADC
CMOS, 4 Channel, 8-Bit Sampling ADC
CMOS, 8 Channel, 8-Bit Sampling ADC
CMOS, Low Cost
CMOS, Low Cost 10-Bit Sampling ADC
CMOS, Low Cost 10-Bit Sampling ADC
Complete 12-Bit ADC with Till, Reference
and Timing Circuitry
12-Bit, 5MSPS Eurocard
12-Bit, 5MSPS Video ADC
12-Bit, IMSPS ADC, Single 40-Pin DIP
12-Bit, IMSPS ADC
12-Bit 500kHz. ADC Single 4O-Pin DIP
BiMOS, High Impedance High Bandwidth
Sampling Input, 10 V Range
BiMOS, 12-Bit Sampling ADC, ac
Characterized
Complete 12-Bit 125kHz Sampling ADC for
Digital Signal Processing
CMOS, 100kHz Throughput Rate
CMOS, 100kHz Throughput, On-Chip FIFO
Four Channel 65kHz 12-Bit Sampling ADC
for Digital Signal Processing
Complete 12-Bit ADC with Programmable
Gains of 1, 8, 64, 512
Complete 12-Bit ADC with Programmable
Gains of 1, 10, 100, 500
16-Channel, 12-Bit DAS
High Speed, 16-Channel, 12-Bit DAS with
Three-State Buffered Output
AD7821
AD7569
8
8
0.66
2
100
200
0-5 V, Ext
Int
*AD7669
8
2
200
Int
8, JJ.P
N,P
C,I,M
3-233
AD7820
AD7824
AD7828
AD7575
AD7579
AD7580
*AD9005
8
8
8
8
10
10
12
2
2.5
2.5
5
18.5
18.5
0.1
7
10
10
50
25
25
38000
0-5 V, Ext
0-5 V, Ext
0-5 V, Ext
1.23 V, Ext
2.5 V, Ext
2.5 V, Ext
Int
8, ILP
8, JJ.P
8, JJ.P
8, ILP
8, JJ.P
10, JJ.P
12
E,N,P,Q,R
N,Q
E,N,P,Q
E,N,P,Q
E,N,P,Q
E,N,P,Q
M
C,I,M
C,I,M
C,I,M
C,I,M
C,I,M
C,I,M
C,M
3-357
3-379
3-379
3-265
3-279
3-279
3-459
12
12
12
12
12
12
0.2
0.5
1
1
2
4
15000
15000
10000
2000
7000
500
Int
Int
Int
Int
Int
5 V, Int
12
12
12
12
12
8/12, JJ.P
Card
Card
M
M
M
D,N,P
C
C
C
C,M
C,M
C,M
3-567
3-593
3-451
3-573
3-583
3-99
*AD1678
12
4
500
Int
8/12, JJ.P
D,N,P
C
3-195
AD1332
12
8
125
-5 V, lot
12, JJ.P
D
AD7870
AD7878
*AD1334
12
12
12
8
8
15
500
500
235
3 V, Int
3 V, Int
-5 V, lot
8/12/Serial, JJ.P
12, JJ.P
12, JJ.P
N,P,Q
E,N,P,Q
D
C,I,M
C,I,M
I
3-391
3-419
9-49
AD368
12
15
40-1000
6.3 V, Int
12
D
I,M
9-19
AD369
12
15
40-1000
6.3 V, Int
12
M
I
9-19
AD363
AD364
12
12
40
50
X
X
10 V, Int
10 V, Int
12, JJ.P
12, JJ.P
D
D
C,M
C,M
9-5
9-5
CAV-1205
MOD-1205
AD9003
HAS-1201
HAS-1204
AD678
9-31
SAMPLING ADCs
Res
Bits
Cony
Time
f.l.s
max
SHA
BW
kHz
typl
Reference
Volt
IntlExt'
Bus
Interface
Bits3
Package
Options4
Temp
RangeS
Page
Comments
14
14
9
10
200-800
500
Int
5 V, Int
14
8, f.l.P
M
D,N,P
C
C,M
3-587
3-111
*AD1679
14
10
500
5 V, Int
8, f.l.P
D,N,P
C
3-203
*AD779
14
10
500
5 V, Int
14, f.l.P
D,N
C,M
3-135
*AD1779
14
10
500
5 V, Int
14, f.l.P
D,N
C,M
3-215
*AD7871
*AD7872
14
14
10
12
X
X
3 V, Int
3 V, Int
8/141Serial, f.l.P
Serial, f.l.P
N,P,Q
N,Q
C,I,M
C,I,M
3-407
3-407
DAS1152
DAS1157
DAS1l53
DAS1158
AD1380
14
14
15
15
16
40
55
50
55
20
X
X
X
X
900
10 V,
10 V,
10 V,
10 V,
Int
14
14
15
15
16/Serial
D
D
D
D
D
I
I
I
I
C
9-73
9-77
9-73
9-77
3-183
DAS1159
16
55
X
10 V, Int
16
D
125kHz Word Rates; Includes TIH
BiMOS, High-Impedance High-Bandwidth
Sampling Input, 10 V Input Range
14-Bit BiMOS Sampling ADC, ac
Characterized
BiMOS, High-Impedance High-Bandwidth
Sampling Input, 10 V Input Range
14-Bit BiMOS Sampling ADC, ac
Characterized
CMOS, 14-Bit, 100kHz Sampling ADC
CMOS, 14-Bit, Sampling ADC with
Serial Output
14-Bit High Accuracy Sampling ADC
Low Power, 14-Bit Sampling ADC
IS-Bit High Accuracy Sampling ADC
Low Power, IS-Bit Sampling ADC
Low Cost, 16-Bit Sampling ADC. Operation
Over -55°C to +85°C Temperature Range
Low Power, 16-Bit Sampling ADC
Model
HAS-1409
AD679
Int
Int
Int
Int
9-77
MULTIPLEXED ADCs
Model
:t>
,...~
o
t;)
C!
S2
e
~
,...
§
fii
nl
::x:J
~
~
'J
AD7824
AD7828
AD758 I
AD363
AD364
AD7582
Res
Bits
8
8
8
12
12
12
Chan
Cony
Time
f.l.S
SHA
BW
kHz
Reference
Volt
IntlExt'
4
8
8
16
16
4
2.5
2.5
66.7
40
50
100
10
10
0-5 V, Ext
0-5 V, Ext
-5 V-(-15 V), Ext
10 V, Int
10 V, Int
4 V-6 V, Ext
#
Bus
Interface
Bits3
Package
Options4
Temp
RangeS
Page
Comments
8, f.l.P
8, f.l.P
8, ",p
12, f.l.P
12, f.l.P
12, f.l.P
N,Q
E,N,P,Q
D,N
D
D
D,E,N,P
C,I,M
C,I,M
C, I
C,M
C,M
C,I,M
3-379
3-379
3-295
9-5
9-5
3-303
CMOS, On-Chip Track-Hold
CMOS, On-Chip Track-Hold
CMOS
High Speed, 16-Channel, 12-Bit DAS
16-Channel, 12-Bit DAS with Three-State Buffers
CMOS, lLSB Total Unadjusted Error
IX indicates that the internal SHA bandwidth is not specified in kHz.
'Ext indicates external reference with the range of voltages listed where applicable. Ext (M) indicates external reference with multiplying capability. 1m indicates reference is internal. A voltage value is given if the
reference is pinned out.
3This column lists the data format for the bus with ",,"P" indicating microprocessor capability-i.e., for a 12-bit converter 8/12, ,,"P indicates that the data can be formatted for an 8-bit bus or can be in parallel (12
bits) and is microprocessor compatible.
'Package Options: D-Side-Brazed Dual-In-Line Ceramic; E-Leadless Chip Carrier; M-Metal HernIetic Dual-In-Line; N-Plastic Molded Dual-In-Line; P-Plastic Leaded Chip Carrier (PLCC); Q-Cerdip; R-Small
Outline Plastic (SOlC).
'Temperature Ranges: C-Commercial, 0 to +70°C; I-Industrial, -40°C to +85°C (Some older products -25°C to +85°C); M-Military, -55°C to + 125°C.
Boldface Type: Product recommended for new design.
*New product since the publication of the 1987/1988 Databooks.
'f
00
)::.
~,....
0
Selection Guide
Analog-to-Digital Converters
'?
d
VIDEOADCs
S1
C)
~
,....
\)
Res
Bits
Throughput
Rate
MSPS
min
Full
Power
BW
MHz
typ
Reference
Voltage
IntlExt'
Bus
Interface
Bits3
Package
Options4
Temp
RangeS
Page
Comments
<:
~
AD9688
4
175
100
0.16-6 V, Ext
4
E,Q
I,M
3-525
r;J
*AD9006
6
470
250 (min)
±1 V, Ext
6, J.lP
E,Z
C,M
3-467
*AD9016
6
470
250 (min)
±IV,Ext
6, J.lP
E, Z
C, M
3-467
AD9000
6
50
20
0.5-2 V, Ext
6
D,E
C, M
3-435
*AD9028
8
300
250
-2 V, Ext
8
E
C, M
3-497
*AD9038
8
300
250
-2 V, Ext
Dual 8
E
C, M
3-497
AD770
AD9002
8
8
200
125
250
115
(Sm. Sig.)
±2 V, Ext
0.1-(-2.1) Ext
8
8
D
D,E
C, M
I,M
3-123
3-443
*AD9011
8
100
80
Int
8
M
C, M
3-483
AD9012
*AD9048
8
8
75
35
180
15
-2 V, Ext
-2 V, Ext
8
8, J.lP
Q,E
N, P, Q, Z
I,M
C, M
3-489
3-509
AD9502
8
13
7.5
Int
8
M
CAV-1040
CAV·I04OA
CAV·l220
10
40
40
20
20
40
35
1m
10
12
Int
Int
10
10
12
Card
Card
Card
Second Source to AM688, Overrange Bits,
Stackable to 8 Bits
470MSPS, 6-Bit ADC. 8.5pF Input
Capacitance
470MSPS, 6-Bit ADC with On-Board
Demultiplexing Circuitry
MIL-STD-883, Rev. C, Devices Available.
Low Error Rate
300 MSPS, 8-Bit ADC, Guaranteed Dynamic
Performance
300 MSPS, 5-Bit ADC with On-Board
1:2 Demultiplexed Data Outputs
High Bandwidth, Error Correction
Single Supply, Low Power, Low Input
Capacitance, MIL-STD-883, Rev. C
Device Available
8-Bit, 100MSPS ADC with On-Board Amp
and Reference, Multiple Gain Selection
TTL Compatible Outputs
35MSPS, 8-Bit Video ADC, 16pF Input
Capacitance
RS·170 Video Frame Grabber. Digitizes
RS·170, NTSC, PAL Signals
Excellent Dynamic Performance over Frequency
Higher Input Bandwidth Version of CAY -1040
Fastest 12·Bit AID Converter Available
0
Model
:JJ
:JJ
(J)
3-517
C
C
C
3-563
3-563
3-569
~x indicates that the internal SHA bandwidth is not specified in kHz.
Ext indicates external reference with the range of voltages listed where applicable. Ext (M) indicates external reference with mUltiplying capability. Int indicates reference is internal. A voltage value is given if the
reference is pinned out.
3This column lists the data format for the bus with ''l-lP'' indicating microprocessor capability-i.e., for a 12-bit converter 8112, /-LP indicates that the data can be formatted for an 8-bit bus or can be in parallel (12
bits) and is microprocessor compatible.
4Package Options: D-Side·Brazed Dual-In-Line Ceramic; E-Leadless Chip Carrier; M-Metal Hermetic Dual-In·Line; N-Plastic Molded Dual-In-Line; P-Plastic Leaded Chip Carrier (PLCC); Q-Cerdip;
V-Pin-Stake; Z-{;eramic Leaded Chip Carrier.
'Temperature Ranges: C-{;ommercial, 0 to +70'C; I-Industrial, -40°C to +8SOC (Some older products -25°C to +85°C); M-Military, -55°C to + 125°C.
Boldface Type: Product recommended for new design.
*New product since the publication of the 1987/1988 Databooks.
Orientation
Analog-to-Digital Converters
FACTORS IN CHOOSING AN AID CONVERTER
Block diagrams illustrating the various conversion techniques
appear on individual data sheets.
one-half the reference and full scale. At each stage, a decision is
made as to whether the signal is larger (1) or smaller (0) than
one-half the reference; the stage's analog output becomes the
input to the next stage. The complete time for one conversion is
determined by the propagation delay of the analog signal through
all stages; however, since the decision of each stage can be latched
as soon as the stage has settled (and a new conversion can, in
principle, be started as soon as the first bit has been latched),
the rate at which conversions come out of the pipeline is considerably faster than the time for one sample to go through the
conversion process. Though fast, this process is difficult to
implement accurately for more than a few bits because of the
compounding of gain (hence errors).
The moderate-speed converters described in this catalog « IMHz)
employ two fundamental techniques - successive approximations
for moderate-to-high resolution at moderate-to-high speed, and
integration for high resolution at modest speeds. The AD574A
and ADCl 130/1 131 are examples of the former, the AD1l75 the
latter.
A subranging converter digitizes to a group of more-significant
bits and stores them in a latch. A fast, very high-accuracy D/A
converter converts them to an analog signal which is then subtracted from the input. The difference, or residue, is amplified
and digitized, and (in DCS) the result is combined digitally in
such a way as to correct for midscale conversion errors.
Like a chemist's balance with binary weights (1/2, 1/4, 1/8,
etc.), the successive approximation converter compares the unknown
input with sums of accurately-known binary fractions of full
scale starting with the largest (2- 1) and rejecting any that change
the comparator's state ("tip the scale"). At the end of conversion
(EOC), the output of the converter is a digital word representing
the ratio of the input to full scale by a fractional-binary code.
Whatever the technique, these AID converters comprise several
essential functions: an analog section, a digital data-generating
section, data outputs and digital controls.
In this catalog, there are listed approximately 50 different families
of analog-to-digital converters (ADCs). If one were to consider
all the variations, there would be considerably more than 100
different types to choose among. The reason for so many different
types is the number of degrees of freedom in selection-technological, functional, performance and package. Complete information on converters may be found in the 700-page book, AnalogDigital Conversion Handbook, published by Prentice-Hall, Inc.
FUNCTIONAL CHARACTERISTICS
Integrating types count pulses for a period proportional to the
input. The charge balancing integrating converter (essentially a
voltage-to-frequency converter) measures the input signal by
balancing a proportional current against a train of precisely
controlled reference pulses using an integrator (AD 1170). During
the integration phase, the input signal is measured; during the
computation phase, the data from the first phase is processed
and calibration factors applied. This type of converter can provide
very high resolution and accuracy.
The video converters described here (AD9002, CAV-120S, etc.)
employ two basic encoding techniques: simultaneous, or flash
conversion, and serial-Gray-Code conversion. High resolution
and high speed are obtained by subranging i.e., by performing
an n-bit conversion in two steps; Analog Devices has perfected a
form of subranging known as DCS - digitally corrected subranging
- which permits accurate resolutions of 12 bits and more. *
In flash conversion, the analog signal is compared against
2° - 1 graded voltage levels using as many comparators, and the
comparator output logic levels are processed by a priority encoder
which converts the "thermometer" output to a binary (or Gray)
code. Since the whole conversion occurs essentially simultaneously,
it is the fastest means of conversion, but it requires many accurate
comparators and large numbers of gates.
In serial analog-parallel-digital conversion, there are a number of
cascaded stages, each having a gain of + 2 for signals less than
one-half the reference, and a gain of - 2 for signals between
Analog Section
This section requires a reference, one or more high-gain comparators, and either a DIA converter (successive approximations)
or a controllable integrator. The reference may be internal or
external, fixed or variable, and of a specified polarity/sense in
relation to the analog input. In ratiometric conversion, the reference is usually external and variable.
In successive approximation converters, the comparator is generally used in the current-summing mode; that is, the current
output of the DAC is summed with the current developed in
the DAC's "feedback resistor" by the input voltage (of opposite
polarity), and the balancing action of the converter tends to
bring the summing junction towards a voltage null (much like
that of an op amp) at the end of conversion. The typical DAC
feedback options, when applied in an ADC, provide input-scaling
choices. When the bipolar-offset connection is jumpered to the
summing point, input signals of both polarities can be handled.
The current-switching action of the DAC, at the typically fast
clock rates used in successive approximation converters, can
disturb the output of the analog signal source, especially if it is
a slow high-precision op amp. In such cases, buffering may be
necessary.
Sample and Hold
When an ADC without a sample and hold is used, the analog
input must not change by more than 1/2 LSB during the conversion. For some applications this constraint is not a concern,
but it limits the bandwidth of the signal that can be applied to
the converter. A sample-and-hold circuit must be used in front
of the ADC if increased bandwidth is required. This sample and
hold can be external, or an integral part of the converter (e.g.,
AD7579/AD7580).
• A considerable amount of useful information about the differences
between video conversion and moderate-speed conversion can be found
in the article "Very High Speed Data Acquisition," by Ed Graves in
Analog Dialogue 13-2, available upon request.
ANALOG- TO-DIGITAL CONVERTERS 3-9
11
Digital Data-Generating Section
In successive-approximation types, this section consists of a
discrete or integrated successive-approximations register (SAR),
its controls and inputs from the comparator and clock (which is
on-board, but in many cases Permits external clock pulses,
frequency adjustment and/or control). In integrating types, this
section consists of the clock-pulse generator, the counter(s), the
input from the comparator and the associated controls. Often,
provisions are made for the pulse train to be jumpered to the
counter externally so that the pulse train can be operated on
externally, or can transmit its train of pulses to a remote counter.
In a few types there are no on-board counters or registers; the
pulse train, magnitude, overrange and control terminals are
intended to communicate with external counters and registers.
Data Outputs
Factors to consider here include coding, resolution, overrange
information, levels, format, validity and timing. Coding is usually
binary including jumper-connected offset-binary and/or twos
complement for bipolar input signals. For some types, BCD is
available with sign-magnitude for bipolar inputs. Output coding
specs should always be checked for digital polarity (positive- or
negative-true) of both magnitude and sign information. The
resolution (number of output bits) must be sufficient for the
application; in addition, the specifications must be checked to
ascertain that not only will all 2n (binary) output codes be present
(no missing codes), but they must all be present at any temperature
in the operating range and related to the input with sufficient
accuracy. Integrating types generally have no problems with
missing codes (except sometimes at zero, with sign-magnitude
coding); nevertheless, nonlinear integration can cause the conversion relationship to become nonlinear. Successive-approximation types have no way of determining overrange; they simply fill
up. However, counter types roll over and put out a carry flag to
signal overrange. Analog Devices offers ADCs, with 4- through
22-bit resolution, with a span of conversion times from milliseconds
to nanoseconds.
The data levels available at the converter output must be checked
(TTL, low-voltage CMOS, high-voltage CMOS, ECL), as must
the load-driving capability and fanout, and the supply conditions
under which appropriate output levels will be furnished. The
available choice of output formats must also be as desired parallel, serial, byte-serial, and/or pulse-train. ·If the converter is
intended to communicate directly with an 8-bit data bus, the
output should have three-state capability, and parallel outputs
must be enabled in bytes of eight or fewer lines (AD573, AD574A).
If the output is serial, it is usually NRZ (non-return-to-zero)
and should be accompanied by a set of synchronized
clock-pulses.
A status (or busy or EOC) output changes state to indicate when
the data becomes valid~ The exact nature ofthis transition should
be specified - polarity, timing, levels, etc. For serial data, the
exact relationship between the data and the synchronizing clock
should be specified to indicate when each bit becomes valid,
and for how long. In general, the timing of the whole conversion
process must be clearly understood, especially if high speeds are
necessary, either for conversion or for communication with a
processor (or both). The timing diagrams on specification sheets
3-10 ANALOG-TO-DIGITAL CONVERTERS
are usually accompanied by adequate descriptions of the conversion
process and specifications of the critical interface parameters.
Controls
The functions, action (levels or edges), polarity and timing of all
control inputs and outputs should be clearly understood, as well
as their loading characteristics and dependence on the supply.
In addition to the essential start-conversion-command input and a
status output, various control commands may be available, such
as clock inhibit, high- (low-) byte enable, status enable and - for
speeding up conversion at the cost of resolution in successiveapproximation converters - short-cycle.
Many ADCs are designed to interface directly to the bus of a
computer or microprocessor. These ADCs provide the necessary
control and handshake lines, as well as data bit registers, to
minimize and often eliminate the required interface circuitry.
The bus timing should be studied with respect to the timing
provided by the ADC interface, especially as the processor
executes a data read cycle to the ADC to retrieve the conversion
results. Systems with higher speed clocks require either shorter
minimum write pulse widths (such as SOns for the AD7579/
AD7580) or the use of processor-wait states when the ADC is
addressed.
STATIC AND DYNAMIC PERFORMANCE
SPECIFICATIONS
All ADCs are specified using terms such as accuracy, linearity,
offset, defmed and explained below. These static, or "dc,"
parameters are necessary and sufficient for many applications;
they may not be sufficient for others, such as those in digital
signal processing, adaptive filtering or waveform generation.
Dynamic ac specifications define how the ADC performs using
parameters such as signal-to-noise ratio (SNR), intermodulation
distortion (IMD) and total harmonic distortion (THD). These
specifications characterize the performance of the ADC output
in applications where the envelope of output changes and output
timing errors are critical.
POWER SUPPLIES
Appropriate power supplies should be made available considering
the logic levels and analog input signals to be employed in the
system. The appropriate degree of power-supply stability to
meet the accuracy specifications should be provided. Any recommended external protection circuitry should be planned for.
In many cases, separate analog and digital grounds are required;
ground wiring should follow best practice to minimize digital
interference with high-accuracy analog signals while ensuring
that a connection between grounds can always exist at one point,
even if the "mecca" point is inadvertently unplugged from the
system.
APPLICATION CHECKLIST
The designer will generally require specific information in the
following categories before proceeding to the selection process:
• Accurate description of input and output
1. Analog signal range and source or load impedance
2. Digital code needed - binary, offset binary,
twos complement, BCD, etc.
3. Logic level system, i.e., TTL/DTL compatible
•
•
•
•
What is the needed data throughput rate?
What are the control interface details?
What does the system error budget allow for the converter?
What are environmental conditions - temperature range,
time, supply voltage - over which the converter should
operate to the desired accuracy?
For AID converters, the following considerations are typical.
• What is the analog input voltage range, and to what resolution
must the signal be measured?
• What is the requirement for linearity error (or relative accuracy
error)?
• To what extent must the various sources of error be minimized
as environmental temperature changes?
• How much time can be allowed in the system for each complete
conversion? What aperture uncertainty and acquisition time
are needed for the sample-hold?
• How stable is the system power supply? What errors will
result from power supply terminal voltage variations of this
order?
• Can the system tolerate missed codes under any conditions?
• What is the character of the input signal? Is it noisy, sampled,
filtered, rapidly varying, slowly varying? What kind of pre
processing is to be (or can be) done that will affect the choice
(and cost) of the converter? Is aliasing a p~tential problem?
SPECIFICATIONS AND TERMS
Definitions of performance specifications and related information
are to be found on the following pages in alphabetical order. *
Accuracy, Absolute
The error of an AID converter at a given output code is the
difference between the theoretical and the actual analog input
voltages required to produce that code. Since the code can be
produced by any analog voltage in a finite band (see Quantizing
Uncertainty), the "input required to produce that code" is defined
as the midpoint of the band of inputs that will produce the
code. For example, if 5 volts (± 1.2mV) will theoretically produce
a 12-bit half-scale code of 100000000000, then a converter for
which any voltage from 4.997V to 4.999V will produce that
code will have absolute error of 112 (4.997 + 4.999) - 5 volts
= -2mV.
Absolute error comprises gain error, zero error and nonlinearity,
together with noise. Absolute-accuracy measurements should be
made under a set of standard conditions with sources and meters
traceable to an internationally accepted standard.
*For video converters, there are a number of additional applicationoriented specifications pertaining to the device's use in a system (e.g.,
Doise power ratio, differential phase, differential gain, signal-to-noise
ratio), Some useful references for understanding such specifications
can be found in the following publications available from Analog
Devices, Computer Labs Division, 1910 Triad Center Drive,
Greensboro, NC 27409.
Kester, W.A., "PCM Signal Codecs for Video Applications," SMPTE
Journal, Volume 88, November 1979, pp 770·778.
Pratt, W.J., "Test AID Converters Digitally," Electronic Design,
December 6, 1975.
Smith, B.F. and Pratt, W.J., "Understanding High·Speed AID
Accuracy, Relative
Relative accuracy error, expressed in %, ppm or fractions of an
LSB, is the deviation of the analog value at any code (relative to
the full analog range of the device transfer characteristic) from
its theoretical value (relative to the same range) after the full-scale
range (FSR) has been calibrated.
Since the discrete points on the theoretical transfer characteristic
lie on a straight line, this deviation can also be interpreted as a
measure of nonlinearity (see Linearity).
The "discrete points" of an AID transfer characteristic are the
midpoints of the quantization bands at each code (see Accuracy,
Absolute).
Aperture Time
This is the interval between the application of the hold command
to a sample/track-hold and the actual opening of the switch.
The aperture time consists of a delay (which depends on the
logic and the switching device - 5ns for HTS-0025) and an
uncertainty (due to jitter - 20ps max rms for HTS-0025). When
a sample-hold is used in an application where timing is critical,
the timing of the hold command can be advanced to compensate
for the known component of aperture delay. The jitter, however,
imposes the ultimate limitation on timing accuracy. When a
sample-hold is used with an ADC, the timing uncertainty of the
conversion process is reduced by the ratio of aperture jitter to
the conversion time, i.e., the maximum frequency which can be
handled with less than lLSB error due to timing is 2-n 1(7r Tau)
instead of 2-n/(7r Te), where Tau is the aperture uncertainty and Te
is the conversion time.
Common-Mode Rejection (CMR)
The ability of a device to reject the effect of voltage applied to
both input terminals simultaneously. Usually expressed as the
log of a "common-mode rejection ratio," e.g., 1,000,000:1
(CMRR) or 120dB (CMR). A CMRR of 1,000,000 to I means
that a I V common-mode voltage passes through the amplifier as
though it were a differential signal of one microvolt at the
input.
Conformance, Straight-Line
This indicates how closely the ADC transfer characteristic conforms to a reference straight line. This straight-line conformance
is critical in DSP applications where deviations from a straight
line are seen as distortion, while gain and offset errors are not as
serious. The straight-line conformance error is measured from
the center of each code to the best-fit straight line.
Conversion Time and Conversion Rate
The time required for a complete measurement by an ADC is
called conversion time. For most converters (assuming no significant
additional systemic delays), this is identical to the inverse of
conversion rate. However, in some high-speed converters, because
of pipelining, new conversions are initiated before the results of
prior conversions have been determined; thus, for example, the
CAV-1250 can provide 12-bit output data at a 3.85MHz word
rate (260ns/conversion), even though the time for anyone conversion, from start to finish, is two 280ns encode periods plus
195ns, or 755ns at 3.85MHz.
Converter Specifications," Computer Labs, 1974.
ANALOG-TO-DIGITAL CONVERTERS 3-11
II
Dual-Slope Converter
An integrating analog-to-digital converter in which the unknown
signal is convened to a proportional time interval, which is then
measured digitally. This is done by integrating the unknown for
a predetermined time. Then a reference input is switched to the
integrator and integrates "down" from the level determined by
the unknown until a "zero" level is reached. The time for the
second integration process is proportional to the average of the
unknown signal level over the predetermined integrating period.
A digital time-interval meter (i.e., counter) is generally used as
the output indicator.
INTEGRATOR
OUTPUT
C3
SIGNAL INTEGRATE
TIME
REFERENCE INTEGRATE
TIME
Feedtbrough
Undesirable signal coupling around switches or other devices
that are supposed to be turned off or provide isolation, e.g .•
feedthrough error in a multiplexer. It is variously specified in %,
ppm, fractions of ILSB, or fractions of I volt, with a given set
of inputs at a specified frequency.
"Flash" Converter
A converter in which all the bit choices are made at the same
time. It requires 2n -I voltage-divider taps and comparators,
and a comparable amount of priority encoding logic. An extremely
fast scheme, it requires large numbers of precision components.
Flash converters are often used for partial conversions in subranging
converters.
Full-Scale Error
The ideal difference between the first transition voltage and last
transition voltage for an ADC is (F.S. -2LSB). Full-Scale
Error is defined as the deviation between this ideal difference
and the measured difference.
Gain Adjustment
The "gain" of a converter is that analog scale factor setting that
provides the nominal conversion relationship, e.g., 10V full
scale in a fixed-reference converter, or 100% of full scale in a
ratiometric converter. Gain- and zero-adjustment principles are
discussed under zero.
Harmonic Distortion (and Total Harmonic Distortion)
The ADC is driven by a spectrally pure, analog sine wave from
a signal generator. The ADC outputs are analyzed via FFT and
the ratio of the rms sum of the harmonics of the ADC output to
the fundamental value is the THD. Usually, only the lower
order harmonics are included, such as second through fifth:
(V 2 + V 2 + V 2 + V 2)112
THD=20 log 2
3
4
5
Vl
where V 1 is the rms amplitude of the fundamental and V2, V3,
V4 and V5 are the rms amplitudes of the individual harmonics.
Intermodulation Distortion
The ADC is driven by an analog signal source producing two
combined sine waves of frequencies fa and fb. As with any imperfectly linear device, distortion products (of order m+n) are
produced at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1,2, 3 ... by the ADC. Intermodulation terms are
those for which m or n is not equal to zero. The second order
terms include (fa + fb), and fa - fb), and the third order terms are
(2fa+fb), (2fa-fb), (fa+2fb) and (fa-2fb). The ADC outputs are
analyzed by FFT. IMD is defined as:
IMD=20 log ~
z~
8~
S
22
~
~z
~~
~~
~
mo
~~
~23
g~
24
8
Figure 1. AD572 Functional Diagram & Pinout
The +10V reference is derived from a low T.C. zener reference diode which has its zener voltage amplified and buffered
by an op amp. The reference voltage is calibrated to +10V,
±l Om V by active laser trimming of the thin-film resistors
which determine the closed-loop gain of this op amp.
The DAC chip uses 12 precision, high speed bipolar current
steering switches, a control amplifier and a laser-trimmed thin
film resistor network to produce a very fast, high accuracy
analog output current. The DAC is laser-trimmed to calibrate
all bit ratio scale factors to a precision of 0.0005% of FSR
(full-scale range) to guarantee no missing codes over the
appropriate temperature ranges specified for the AD572A,
AD572B, and AD572S versions.
Different unipolar and bipolar analog input ranges can be
selected by changing connections at the device terminal pins.
The analog voltage input can be applied to either of the span
(direct input) resistors. Alternatively, the unity buffer follower can be connected between the analog signal and either
direct input terminal when a high impedance input is required.
THEORY OF OPERATION
On receipt of a CONVERT START command, the AD572
converts the voltage at its analog input into an equivalent
12-bit binary number. This conversion is accomplished as
follows:
The 12-bit successive-approximation register (SAR) has its
12-bit outputs connected both to the respective device bit
output pins and to the corresponding bit inputs of the feedback DAC.
The analog input is successively compared to the feedback
DAC output, one bit at a time (MSB first, LSB last). The
decision to keep or reject each bit is then made at the
completion of each bit comparison period, depending on the
state of the comparator at that time.
TIMING
The timing diagram is shown in Figure 2. Receipt of a
CONVERT START signal sets the STATUS flag, indicating
conversion in progress. This, in turn, removes the inhibit
applied to the gated clock, permitting it to run through
GATED
CLOCK
STATUS
-l-
.L-1
CONVERSION IN PROGRESS
~ INDETERMINATE
I
PARALLEL DATA VALID
BIT 2
~
BIT 3
~
BIT 4
~
BIT 5
~
BIT 6
~
BIT1
~
BIT B
~
81T9
~
BIT 10
~
BIT 11
~
BIT 12
~
fLSBI
-I
L
BIT 1
(MSB!
rU
rU
rU
U
rrU
SERIAL
Figure 2. Timing Diagram (Binary Code 110101011001)
ANALOG-TO-DIGITAL CONVERTERS 3-23
13 cycles. All SAR parallel bit and STATUS flip-flops are
initialized on the leading edge, and the gated clock inhibit
signal removed on the trailing edge of the CONVERT
START signal. At time to' B1 is reset and Bz -B 12 are
set unconditionally. At t1 the Bit 1 decision is made (keep)
and Bit 2 is unconditionally reset. At tz, the Bit 2 decision
is made (keep) and Bit 3 is reset unconditionally. This
sequence continues until the Bit 12 (LSB) decision (keep) is
made at t12. After a lOOns delay period, the STATUS flag
is reset, indicating that the conversion is complete and that
the parallel output data is valid. Resetting the STATUS flag
restores the gated clock inhibit signal, forcing the clock
output to the logic "0" state.
Corresponding serial and parallel data bits become valid on
the same positive-going clock edge. Serial data does not
change and is guaranteed valid on negative-going clock edges,
however; serial data can be transferred quite simply by clocking it into a receiving shift register on these edges (see Figure 8).
Incorporation of this lOOns delay period guarantees that
the parallel (and serial) data are valid at the Logic "I" to "0"
transition of the STATUS flag, permitting parallel data
transfer to be initiated by the trailing edge of the STATUS
signal.
-SV TO +SV INPUT RANGE
Assume FSR = 10V as above, but that the bipolar offset is
connected and 8 1 B2 B3 .. B-12 = 0110000000001. Then
from (4), Eia = (+2.SV + 1.2SV + 0.0024V) - sv = -1.2476V.
-10V TO +10V INPUT RANGE
Assume the bipolar offset is connected as above, but that the
input span is now 20V. Assuming the same digital output code
as in the -SV to +5V input range example, from (4), Eio =
(+SV +2.5V +0.0049V) -lOV = -2.49S1V, or twice the value
of the previous example (neglecting round-off errors).
The encoding process defined by the previous relations (1)
and (2) or (3) and (4) determines that the analog input lies
within one of the 212 = 4096 quantization levels between 0
and FSR (or -FSRI2 and +FSR/2). Figures 3 (A) and 3 (B)
show the actual device transfer curves for unipolar and bipolar
ranges (offset binary coding). They also show the ideal
straight-line transfer curves which pass through the center
of each quantization level. As can be seen from these
figures, the actual and ideal transfer curves differ by exactly ±¥.zLSB at the end of each quantization interval,
giving rise to the fundamental ±¥.zLSB quantization error
inherent in the digitizing process.
k1
t
BINARY CODING
The ADS72 binary output number No = B1 B2 B 3···B 12
is related to the analog input voltage Ein for all unipolar
ranges by the expression:
ACTUAL TRAN~FER CURVE
•
EIN~
Unipolar Range (Binary Coding)
(1)
212
FSR
+1
~
No
... where B1 = MSB, B12 = LSB, and FSR = full-scale range.
For all bipolar ranges a fixed bipolar offset equal to
:tE.¥-
is internally summed with Ein so that the sum of Ein plus
this offset will be positive over the rated operating range.
For bipolar ranges, expression (1) becomes:
L
1LSB
~!.iFSR
(B)
B1211 + B2 210 + B3 29 + .. + B12 20
212
Em.
+
---z
(2)
FSR
= E.m
(3)
Unipolar (Binary Coding)
... and ...
( !!L + B2 + .!3. + ... + J!I..L) FSR- FSR
2
4
8
4096
2
= E.
m
(4)
Bipolar (Offset Binary Coding)
Several examples will illustrate how this binary coding works.
o TO +10V INPUT RANGE
Assume FSR = lOV and B1 B2 B3 .. B 12 = 110001000001,
then from (3), Eia = +5V +2.5V +0.1563V + 0.OO24V =
+7.6587V.
3-24 ANALOG-TO-DIGITAL CONVERTERS
4J
+%FSR -'LSB
IDEAL TRANSFER CURVE
ACTUAL TRANSFER CURVE
1•
EIN~
Bipolar Range (Offset Binary Coding)
FSR
Expressions (1) and (2) can be put in an alternate form:
(!!L
4096 FSR
2 +.!h
4 + !h.
8 + .... +1h2..)
IDEAL TRANSFER CURVE
'LSB
No
(A)
B1 211 + B2 2 10 + B329 + ... + B12 20
L
FSR _'LSB
Figure 3.
Unipolar and Bipolar Range Transfer Curves
ANAWG INPUT AND POWER CONNECTIONS
Offset Adjust. AnaIog and power connections for 0 to +10V
unipolar and -10V to +10V bipolar input ranges are shown
in Figures 4 and 5, respectively. The Bipolar Offset pin 23 is
open-circuited for all unipolar input ranges, and connected to
Comparator Input pin 22 for all bipolar input ranges. The :
zero adjust circuit consists of a potentiometer connected
across ±Vs with its slider connected through a 3.9MO resistor to Comparator Input pin 22 for all ranges. The tolerance
of this fixed resistor is not critical, and a carbon composition
type is generally adequate. Using a carbon composition resistor having a -1200ppm/oC temp co contributes a worst-case
offset tempco of 8 x 244 x 10-6 x 1200ppm/u C = 2.3ppm/C
of FSR, if the OFFSET AD] potentiometer is set at either
end of its adjustment range. Since the maximum offset adjustment required is typically no more than ±4LSB, use of a
carbon composition offset summing resistor typically contributes no more than 1ppm/C of FSR offset temp co.
AD572
types are recommended. If the lOOn GAIN AD} potentiometer is replaced by a fixed son resistor, absolute gain calibration to ±0.1% of FSR is guaranteed.
Grounding. Analog and digital power supply grounds should
be kept separate where possible to prevent digital signals from
flowing in the analog ground circuit and inducing spurious
analog signal noise. Analog Ground pin 26 and Digital Ground
pin 15 are not connected internally; these two pins must be
connected externally for the device to operate properly.
Preferably, this connection is made at only one point, and
as close to the device as possible.
.16V
NOTE, ANALOG
tWI AND DIGITAL r*'l GNOS ARE
NOT TIED INTERNALLY AND MUST BE CONNECTED
EXTERNALLY,
Figure 4. Analog and Power Connections for Unipolar
oto +10V Input Range with Buffer Follower
Power Supply Bypassing. The ±15V and +5V power leads
should be capacitively bypassed for optimum device performance. l/-1F tantalum types are recommended; these capacitors should be located close to the device. It is not necessary
to shunt these capacitors with disc capacitors to provide additional high frequency power supply decoupling (as is required with some competitive products), since each power lead is
bypassed internally with a 0.039/-1F ceramic capacitor.
CALIBRATION
External ZERO AD} and GAIN AD} potentiometers, connected as shown in Figures 3 and 4, are used for device
calibration. To prevent interaction of these two adjustments,
Zero is always adjusted first and then Gain. Zero is adjusted
with the analog input near the most negative end of the
analog range (0 for unipolar and -Y..FSR for bipolar input
ranges). Gain is adjusted with the analog input near the most
positive end of the analog range.
NOTE: ANALOG
iW') ANO DIGITAL !?"I GNOS ARE
NOT TIED INTERNAlL V AND MUST 8E CONNECTED
EXTERNALLY,
Figure 5. Analog and Power Connections for Bipolar -10V
to +10V Input Range with Buffer Follower
An alternate offset adjust circuit, which contributes negligible offset tempco if metal film resistors (tempco < 100
ppm/oC) are used, is shown in Figure 6.
+15V
20k
2ook. M.F.
200k, M.F.
22
2oi~~---V~----~--~~~~-O~
OFFSET ADJ
(±8LSB'sl
AD572
11k, M.F.
-15V
A
Figure 6. Low Tempco Zero Adi Circuit
In either zero adjust circuit, the fixed resistor connected to
pin 22 should be located close to this pin to keep the pin
22 connection runs short, since the Comparator Input pin 22
-is quite sensitive to external noise pick-up.
Gain Adjust. The gain adjust circuit consists of a lOOn
potentiometer connected between +10V Reference Output
pin 18 and Gain Adjust Input pin 27 for all ranges. Both
GAIN and ZERO AD) potentiometers should be multi-turn,
low tempco types; 20T cermet (tempco = 10Oppm/C max)
o to +10V Range. Set analog input to +lLSB = +0.0024V.
Adjust Zero for digital output = 000000000001; Zero is now
calibrated. Set analog input to +FSR -2LSB = +9.9952V.
Adjust Gain for 111111111110 digital output code; fullscale (Gain) is now calibrated. Half-scale calibration check:
set analog input to +5.0000V; digital output code should be
100000000000.
-10V to +10V Range: Set analog input to -9.9951V; adjust
Zero for 000000000001 digital output (offset binary) code.
Set analog input to +9.9902V; adjust Gain for 111111111110
digital output (offset binary) code. Half-scale calibration
check: set analog input to O.O,?OOV; digital output (offset
binary) code should be 100000000000.
Other Ranges. Representative digital coding for 0 to +10V,
-5V to +5V, and -10V to +10V ranges is shown in Table I.
Coding relationships and calibration points for 0 to +5V and
-2.5V to +2.5V ranges can be found by halving the corresponding code equivalents listed for the 0 to +10V and -5V
to +5V ranges, respectively.
Zero and full-scale calibration can be accomplished to a pre:.
cision of approximately ±'>4LSB using the static adjustment
procedure described above .. By summing a small sine or triangular-wave voltage with the signal applied to the analog
input, the output can be cycled through each of the calibration codes of interest to more accurately determine the
center (or end points) of each discrete quantization level. A
detailed description of this dynamic calibration technique is
presented in "AID Conversion Notes", D. Sheingold, Analog
Devices, Inc., 1977, Part II, Chapter 4.
ANALOG-TO-DIGITAL CONVERTERS 3-25
•
Analog Input - Volts
(Center of Quantization Interval)
o to +10V
Range
-5V to +5V
Range
+9.9976
+9.9952
+4.9976
+4.9952
+5.0024
+5.0000
+0.0024
+0.0000
Digital Output Code
(Binary for Unipolar Ranges;
Offset Binary for Bipolar Ranges)
Input Normalized
to FSR
-10V to +10V
Range
Unipolar
Ranges
Bipolar
Ranges
+9.9951
+9.9902
+FSR-l LSB
+FSR-2 LSB
+I;FSR-1 LSB
+I;FSR-2 LSB
111111111111
111111111110
+0.0024
+0.0000
+0.0049
+0.0000
+I;FSR +1 LSB
+I;FSR
+1 LSB
ZERO
100000000001
100000000000
-4.9976
-5.0000
-9.9951
-10.0000
+1 LSB
ZERO
-I;FSR +1 LSB
-I;FSR
000000000001
000000000000
Bl
(MSB)
B12
(LSB)
Table I. Digital Output Codes vs Analog Input For Unipolar and Bipolar Ranges
RANGE AND BUFFER FOLWWER PIN CONNECTIONS
Analog pin connections for each of the ranges, with and
without the buffer follower being used, are shown in Table II.
Range
o to
Buffer
Follower
Connect
Analog
Input To Pin:
Used
30, and 29 to 24
Not Used
24
Used
30, and 29 to 24
+SV
o to +lOV
Not Used
24
Used
30, and 29 to 24
-2.5 to +2.SV
Not Used
24
Used
30, and 29 to 24
Not Used
24
Used
30, and 29 to 2S
Not Used
25
-5 to +SV
-10 to +10V
Connect
Span Pin:
Connect
Bipolar
Pin 23 To,
25 to 22
-
Figure 7. Using Buffer Follower With
Multiplexed Analog Input
25 to 22
-
f
22
~
Table II. Range and Buffer Follower Pin Connections
When the analog signal source has a low impedance (as
would be the case if it were the output of the sample-hold
amplifier of Figure 9), it can be connected to either of the
direct input pins 24 or 25. The buffer follower is used in the
application as shown in Figure 6, in which the analog input
to the converter comes directly from the output of a FET
analog multiplexer. The selected channel has a typical ron =
200n which has a 3000ppm/C tempco. If the multiplexer
output were connected to the 0 to +10V direct input pin 24
(5kn input impedance, nominal), this ron would introduce
a 4% gain scale-factor loading error, which is well beyond
the normal ±0.25% FSR external gain adjustment range, and
a tempco of approximately 3000ppm/o C x 4% = 120ppm/ C.
By connecting the buffer between the multiplexer output and
direct input, these errors are eliminated. The buffer amplifier
input bias current (50nA typical) must flow through the
analog signal source, however. This limits the upper practical
source impedance to several kilohms so that the offset voltage IBIAS RSOURCE can be kept negligible, even though the
buffer amplifier dynamic input impedance ~ 100Mn. The
buffer amplifier has a 2IJ.s settling time to 0.01% FSR for a
20V input step. This must be added to the conversion time
when the input voltage can change significantly between
successive conversions (as could be the case in the circuit
of Figure 7).
3-26 ANALOG-TO-DIGITAL CONVERTERS
Short Cycle Input. A Short Cycle Input pin 14 permits the
timing cycle shown in Figure 2 to be terminated after any
number of desired bits has been converted, permitting somewhat shorter conversion times in applications not requiring
full 12-bit resolution. When 12-bit resolution is required,
pin 14 is connected to +5V (pin 16). When lO-bit resolution
is desired, pin 14 is connected to Bit 11 output pin 2. The
conversion cycle then terminates, and the STATUS flag
resets after the Bit 10 decision (tlO + lOOns in timing diagram of Figure 2). Shott Cycle pin connections and associated maximum 12-, 10- and 8-bit conversion times are summarized in Table III.
Connect Short
Maximum Status Flag
Cycle Pin 14 to
Resolution Conversion Reset at.
Time (lJ.s) (Figure 2)
Pin:
Bits (% FSR)
16
12
0.024
25
t12 + lOOns
2
10
0.10
21
tlO + lOOns
4
8
0.39
17
ts + lOOns
Table III. Short Cycle Connections
(One should note that the calibration voltages listed in Table
I are for 12-bit resolQtion only, and are not those corresponding to the center of each discrete quantization interval at reduced bit resolutions.)
DIGITAL OUTPUT DATA
Both parallel and serial data are in positive-true form and
outputted from TTL storage registers. Parallel data output
coding is binary for unipolar ranges and either offset binary
AD572
or two's complement binary, depending on whether Bit
(pin 12) or its logical inverse BIT 1 (pin 13) is used as the
MSB. Parallel data becomes valid approximately 200ns
before the STATUS flag returns to Logic "0", permitting
parallel data transfer to be clocked on the "1" to "0" transition of the STATUS flag.
Serial data coding is binary for unipolar input ranges and
offset binary for bipolar input ranges. Serial output is by
bit (MSB first, .LSB last) in NRZ (non-return-to-zero) format.
Serial and parallel data outputs change state on positive-going
clock edges. Serial data is guaranteed valid on all negativegoing clock edges, permitting serial data to be clocked directly into a receiving register on these edges as shown in Figure
8. There are 13 negative-going clock edges in the complete
12~bit conversion cycle, as shown in Figure 2. The first edge
shifts an invalid bit into the register, which is shifted out on
the 13th negative-going clock edge. All serial data bits will
have been correctly transferred and be in the receiving shift
register locations shown at the completion of the conversion
period.
Figure 9. Sample-Hold Amplifier - AD572 Interconnections
Note that the internal (gated) clock is inhibited for the duration of the CONVERT START pulse and does not start
running until the termination of this pulse (see timing). This •
can be used to simplify control signal timing requirements.
In the circuit of Figure 9, for example, the CONVERT
START signal pulse-width can be extended beyond the aperture delay time of the SHA to assure that eo S+I is in
steady-state before conversion is initiated. This assures
accurate conversion without requiring additional delay timing circuitry. The effect of varying the CONVERT START
pulse-width on the conversion timing cycle is shown in Figure 10.
APPLICATIONS
Sample-Hold Amplifier. A sample-hold amplifier (SHA) is
normally connected between the analog signal source and
AD572 analog input when the analog signal can change by
more than 'hLSB during conversion. Typical SHA-AD572
interconnections are shown in Figure 9. The STATUS output
drives the SHA SAMPLE/HOLD input directly. On receipt of
a CONVERT START pulse, the STATUS flag changes from
"1" to "0" causing SHA mode to change from SAMPLE to
HOLD. The SHA output voltage eo SoH is then held constant
at the value existing just prior to application of the HOLD
command for the complete conversion period. At the end of
conversion, the STATUS flag returns to "1", restoring the
SHA mode to SAMPLE, and eo S+I again tracks the analog
signal voltage ein S+I (after the signal acquisition transient
has subsided).
CONVERT
ST ART
1
I
STAT~
L ____
~~'l!~.' I ·'1 ·'1"'1 ·'1
(al
86
~--------------------~~
STAT~
INVALID
LI_ _ _
~~'l!:L ~A·' I .21 ·'1"'1:' I:'1:' I ~'I:S 1·"1 ·"1
jb) WIDE CONVERT START PULSE
J
f
AD572
12·BIT ADC
~1
I
32
10t 9
SN74lS395
4·BIT S.R. W/
3-STATE OUTPUTS
q:
2
+5V
SERIAL OUT
17
STATUS L......r-
PARAllEL DATA XFR
--I"l....-
I
B1(MSB)
B5
B9
+5V?,
16 15 14 13 12111
-
1
+5V?
16 15 14 13 1d 11 1019
f
+~:
+5116 15 14
SN74lS395
4-BIT S.R. W/
3-STATE OUTPUTS
2
~
PARAllEL OUTPUT ENABLE
G1 '\.
~
Figure 10. Effect of Convert Start Pulf/e-Width on Timing
12-BIT DATA BUS
CLOCK
19 OUT
~
1.' I·' I ·'1'''1'''1
NARROW CONVERT START PULse
B12(lSB)
21
---'1
I
INVALID
~.
+~~
13 12
1019
SN74lS395
4-BIT S.R. WI
3-STATE OUTPUTS
y:
2
{~b=F~~'r
(HI Z)
J
Figure 8. Serial Data Transfer Into Shift Register With Parallel Output to Data Bus
ANALOG-TO-DIGITAL CONVERTERS 3-27
Digital Gain Control: Figure 11 shows a method of varying
the AD572 gain digitally, using an 8-bit DAC. The lOOn
GAIN ADJ potentiometer is replaced by a 15n fixed resistor.
This biases full-scale high by approximately 35n120,OOOn =
+0.18% of FSR. The AD559 has a large positive compliance
voltage which permits its Current Output pin 4 to be connected directly to the AD572 Reference Input pin 27. The AD559
2.5mA output current is established by the AD580 +2.5V
voltage reference connected through a lkn resistor to Reference Current Input pin 14. The 2.5mA DAC full-scal~ output
current removed from the AD572 pin 27 node changes the
pin 27 input current -2.5mA x 15n120kn = -1.88/JA, or
-1.88/JA/500/JA = -0.38% of FSR; this permits a digital gain
adjustment range of approximately ±0.2% FSR from nominal.
3-28 ANALOG-TO-DIGITAL CONVERTERS
Figure 11. Digital Gain Control Using 8·Bit DAC
~ANALOG
WDEVICES
1O-Bit AID Converter
AD573* I
AD573 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete 10-Bit AID Converter with Reference, Clock
and Comparator
Full 8- or 16-Bit Microprocessor Bus Interface
Fast Successive Approximation Conversion - 20jUI
typ
No Missing Codes Over Temperature
Operates on + 5V and -12V to -15V Supplies
Low Cost Monolithic Construction
v+
v-
DfGITAL
COMMON
CONVERT
MSB
089
DB.
10·BIT
SAR
DB7
D. .
DB.
r--'
BIPOLAR
OffSET -
I INT I
: CLOCK:
L. __ .J
CONTROl
HIGH
Bm;
DM
DB3
DB.
DB'} LOW
DBa
BYTE
LSB
PRODUCT DESCRIPTION
The ADS73 is a complete lO-bit successive approximation analog
to digital converter consisting of a DAC, voltage reference,
clock, comparator, successive approximation register (SAR) and
3 state output buffers-all fabricated on a single chip. No external
components are required to perform a full accuracy 10-bit conversion in 20ILS.
The ADS73 incorporates advanced integrated circuit design and
processing technologies. The successive approximation function
is implemented with I2L (integrated injection logic). Laser trimming of the high stability SiCr thin film resistor ladder network
insures high accuracy, which is maintained with a temperature
compensated sub-surface Zener reference.
Operating on supplies of + SV and -12V to -ISV, the ADS73
will accept analog inputs of 0 to + lOY or - SV to + SV. The
trailing edge of a positive pulse on the CONVERT line initiates
the 20ILs conversion cycle. DATA READY indicates completion
of the conversion. HIGH BYTE ENABLE (HBE) and LOW
BYTE ENABLE (LBE) control the 8-bit and 2-bit three state
output buffers.
The ADS73 is available in two versions for the 0 to + 700C
temperature range, the ADS73J and ADS73K. The ADS73S
guarantees :t ILSB relative accuracy and no missing codes from
- SS"C to + 125°C.
RIE
liE
PRODUCT HIGHLIGHTS
1. The ADS73 is a complete 10-bit AID converter. No external
components are required to perform a conversion.
2. The ADS73 interfaces to many popular microprocessors
without external buffers or peripheral interface adapters. The
10 bits of output data can be read as a lO-bit word or as 8and 2-bit words.
3. The device offers true lO-bit accuracy and exhibits no missing
codes over its entire operating temperature range.
4. The ADS73 adapts to either unipolar (0 to + lOY) or bipolar
( - SV to + SV) analog inputs by simply grounding or opening
a single pin.
5. Performance is guaranteed with
supplies.
+ SV and -12V or -ISV
Two package conflgurations are offered. All versions are also
offered in a 20-pin hermetically sealed ceramic DIP. The ADS73J
and ADS73K are also available in a 20-pin plastic DIP.
*Protected by U.S. PaleDt Nos. 3,940,760; 4,213,806; 4,136,349; 4,400,689;
..... 4,400,690
ANALOG-TO-OIGITAL CONVERTERS 3-29
•
SPECIFICATIONS
(TA=25"C, V+ = +5V, V- = -12V or -15V, all voltages measured willi respect to digital common,
Moclel
Min
unless otherwise indicated)
RESOLUTION
ADS73J
Typ
AD573K
Max
Min
10
RELATIVE.ACCURACY'
Typ
Mu:
10
TA = Tmin toT max
AD573S
Typ
±112
±1/2
;:2
Units
±I
±I
LSB
LSB
Bits
±2
LSB
UNIPOLAR OFFSET
±I
±1/2
±I
LSB
BIPOLAR OFFSET
±I
±112
±I
LSB
DIFFERENTIAL NONLINEARITY3
±2
Max
10
±I
±I
FULL SCALE CALIBRATION'
MiD
= TmintoTmu
10
9
TEMPERATURE RANGE
0
TA
+70
TEMPERATURE COEFFICIENTS'
Unipolar Offset
Bipolar Offset
Full Scale Calibration'
POWER SUPPLY REJECTION
Positive Supply
+4.5sV + s + 5.5V
Negative Supply
-15.75VsV - s -14.25V
-12.6VsV - s -11.4V
ANALOG INPUT IMPEDANCE
3.0
ANALOG INPUT RANGES
Unipolar
Bipolar
0
-5
OUTPUT CODING
Unipolar
Bipolar
LOGIC OUTPUT
Output SiDk Current
(VOUT =OAV max, T min to T mal()
Output Source Current'
(VouT =2.4VmiD, TnUntoT~,)
Output Leakage
LOGIC INPUTS
Input Current
Logic "I"
Logic "0"
5.0
Bits
BilS
10
10
10
10
0
+70
-55
+125
"C
±2
±2
±4
±I
±I
±2
±2
±2
±5
LSB
LSB
LSB
±2
±I
±2
LSB
±2
±2
±I
±I
±2
±2
LSB
LSB
7.0
kH
+10
+5
V
V
7.0
3.0
+10
+5
0
-5
5.0
7.0
3.0
+10
+5
0
-5
Positive True Binary
Positive True Binary
Positive True Offset Binary
Positive True Offset Binary
3.2
3.2
0.5
Positive True Binary
Positive True Offset Biliary
3.2
0.5
rnA
rnA
0.5
±40
±40
±IOO
2.0
5.0
±40
±IOO
±IOO
!LA
0.8
V
V
2.0
2.0
0.8
0.8
!LA
CONVERSION TIME
TA = Tmin10Tmax
POWER SUPPLY
V+
VOPERATING CURRENT
V+
V-
10
20
30
10
20
30
10
20
30
ftS
+4.5
-11.4
+5.0
-IS
+7.0
-16.5
+4.5
+11.4
+5.0
-15
+7.0
-16.5
+4.5
-11.4
+5.0
-15
+7.0
-16.5
V
V
15
9
20
IS
15
9
20
IS
IS
9
20
IS
rnA
rnA
NOTES
lRelative accuracy is defmed as the deviation of the code transition points from the ideal transfer point on a
straight line from the zero to the full scale of the device.
2Pull-scale calibration is guaranteed trimmable to zero with an external 50!). potentiometer in place of the 150
fixed resistor. Full scale is defined as 10 volts minus ILSB, or 9.990 volts.
3Defmed as the resolution for which no missing codes will occur.
4t:hange from + 25"C value from + 25"C to T min or T mllx'
Yrbe data output lines have active pull-ups to source O.5mA. The DATA READY line is open collector with
a nominal 6ldl internal pull-up resistor.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max: specifications are guaranteed, although only those
shown in boldface are tested on all production units.
3-30 ANALOG-TO-DIGITAL CONVERTERS
AD573
ABSOLUTE MAXIMUM RATINGS
V + to Digital Common . . . . . . .
V - to Digital Common . . . . . . .
Analog Common to Digital Common
Analog Input to Analog Common . .
Control Inputs . . . . . . . . . . . .
Digital Outputs (High Impedance State) .
Power Dissipation . . . . . . . . . . . .
o to +7V
o to -16.SV
..
±IV
±ISV
o to V+
o to V+
800mW
ADS73 ORDERING GUIDE
Model
Package Options·
Temperature
Range
Relative
Accuracy
ADS73JN
AD573KN
AD573JP
AD573KP
AD573JD
AD573KD
AD573SD
20-Pin Plastic DIP (N-20)
20-Pin Plastic DIP (N-20)
20-Pin Leaded Chip Carrier (P-20A)
20-Pin Leaded Chip Carrier (P-20A)
20-Pin Ceramic DIP (D-20)
20-Pin Ceramic DIP (D-20)
20-Pin Ceramic DIP (D-20)
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
Oto + 70°C
- 55°C to + 125°C
±lLSBmax
± 1I2LSBmax
± lLSBmax
± 1I2LSBmax
± lLSBmax
± 1I2LSBmax
± lLSBmax
'See Section 14 for package outline information.
ANALOG-TO-DIGITAL CONVERTERS 3-31
II
FUNCTIONAL DESCRIPTION
A block diagram of the ADS73 is shown in Figure 1. The positive
CONVERT pulse must be at least SOOns wide. DR goes high
within I.SILS after the leading edge of the convert pulse indicating
that the internal logic has been reset. The negative edge of the
CONVERT pulse initiates the conversion. The internal 10-bit
current output DAC is sequenced by the integrated injection
logic (I2L) successive approximation register (SAR) from its
most significant bit to least significant bit to provide an output
current which accurately balances the input signal current through
the SkO resistor. The comparator determines whether the addition
of each successively weighted bit current causes the DAC current
sum to be greater or less than the input current; if the sum is
more, the bit is turned off. After testing all bits, the SAR contains
a IO-bit binary code which accurately represents the input signal
to within If.!LSB (0.05% of full scale).
The SAR drives DR low to indicate that the conversion is complete
and that the data is available to the output buffers. HBE and
LBE can then be activated to enable the upper 8-bit and lower
2-bit buffers as desired. HBE and LBE should be brought high
prior to the next conversion to place the output buffers in the
high impedance state.
v+
y-
DIGITAL
COMMON
CONVERT
ON::OO -+_____....--1
MSB
bB.
0 ..
, ..BIT
SAR
DB7
DBS
0 ..
r--,
I INT I
BIPOLAR
OFFSET -
:L..CLOCK:
__ .J
CONTROL
HIGH
BYTE
D84
08.
DB3
~-t::::::::::::::::::::
__~~____.J
The standard unipolar 0 to + 10V range is obtained by shorting
the bipolar offset control pin (pin 16) to digital common
(pin 17).
LSB DBD 1
20 HIGH BYTE ENABLE
LOW BYTE ENABLE
~
DIGITAL COMMON
BIPOLAR OFFSET
ANALOG COMMON
ANALOG IN
vCONVERT
Figure 2. AD573 Pin Connections
Full Scale Calibration
The SkO thin film input resistor is laser trimmed to produce a
current which matches the full scale current of the internal
DAC-plus about 0.3%-when an analog input voltage of 9.990
volts (10 volts - ILSB) is applied at the input. The input resistor
is trimmed in this way so that if a fme trimming potentiometer
is inserted in series with the input signal, the input current at
the full scale input voltage can be trimmed down to match the
DAC full scale current as precisely as desired. However, for
many applications the nominal 9.99 volt full scale can be achieved
to sufficient accuracy by simply inserting a ISO resistor in series
with the analog input to pin 14. Typical full scale calibration
error will then be within ± 2LSB or ± 0.2%. If more precise
calibration is desired, a 500 trimmer should be used instead.
Set the analog input at 9.990 volts, and set the trimmer so that
the output code is just at the transition between 11111111 10
and 11111111 11. Each LSB will then have a weight of9.766mV.
If a nominal full scale of 10.24 volts is desired (which makes the
LSB have a weight of exactly 10.OOmV), a 1000 resistor and a
1000 trimmer (or a 2000 trimmer with good resolution) should
be used. Of course, larger full scale ranges can be arranged by
using a larger input resistor, but linearity and full scale temperature
coefficient may be compromised if the external resistor becomes
a sizeable percentage of SkO. Figure 3 illustrates the connections
required for full scale calibration.
Figure 1. AD573 Functional Block Diagram
The temperature compensated buried Zener reference provides
the primary voltage reference to the DAC and ensures excellent
stability with both time and temperature. The bipolar offset
ipput controls a switch which allows the positive bipolar offset
current (exactly equal to the value of the MSB less lhLSB) to be
injected into the summing ( + ) node of the comparator to offset
the DAC output. Thus the nominal 0 to + 10V unipolar input
range becomes a - SV to + SV range. The SkO thin film input
resistor is trimmed so that with a full scale input signal, an
input current will be generated which exactly matches the DAC
output with all bits on.
UNIPOLAR CONNECTION
The AD573 contains all the active components required to
perform a complete AID conversion. Thus, for many applications,
all that is necessary is connection of the power supplies ( + 5V
and -12V to -15V), the analog input and the convert pulse.
However, there are some features and special connections which
should be considered for achieving optimum performance. The
functional pin-out is shown in Figure 2.
3-32 ANALOG-TO-DIGITAL CDNVERTERS
Figure 3. Standard AD573 Connections
Unipolar Offset Calibration
Since the Unipolar Offset is less than ± I LSB for all versions of
the AD573, most applications will not require trimming. Figure
4 illustrates two trimming methods which can be used if greater
.accuracy is necessary.
Applying the AD573
Figure 4a shows how the converter zero may be offset by up to
± 3 bits to correct the device initial offset and/or input signal
offsets. As shown, the circuit gives approximately symmetrical
adjustment in unipolar mode.
BIPOLAR CONNECTION
To obtain the bipolar - SV to + SV range with an offset binary
output code, the bipolar offset control pin is left open.
AD573
r-_-_--IAco..
R1
100
R2
7.Sk
AD573
A3
4.7k
SIGNAL COMMON
decoupling will "pump up" and fail to settle resulting in conversion
errors. Power supply decoupling, which returns to analog signal
common, should go to the signal input side of the resistive
offset network.
Aco..
A.
'Ok
A - 5.000 volt signal will give a lO-bit code of 00000000 00; an
input of 0.000 volts results in an output code of 10000000 00
and + 4.99 volts at the input yields the 11111111 11 code. The
nominal transfer curve is shown in Figure 6.
SIGNAL COMMON
-15V
+1SV
'h BIT ZERO OFFSET
OUTPUT
CODE
ZERO OFFSET AD.J
:t:3 BIT RANGE
10000000 10
Figure 4a.
Figure 4b.
Figure 4. Offset Trims
Figure 5 shows the nominal transfer curve near zero for an
ADS73 in unipolar mode. The code transitions are at the edges
of the nominal bit weights. In some applications it will be preferable
to offset the code transitions so that they fall between the nominal
bit weights, as shown in the offset characteristics.
. --
OUTPUT
I
CODE
I
00000001 00
00000000 11
00000000 10
ooooaooo
01
_001-+-+-1--+--+__
ov
10mV
30mV
SOmV
INPUT VOLTAGE
NOMINAL CHARACTERISTICS
REFERRED TO ANALOG COMMON
OUTPUT
CODE
r-I
0000000'00
00000000 11
00000000
to
00000000 01
00000000 00 ovl-"'"OmI-Y-+-3=Oml-y-+-:
....
t-y-INPUT VOLTAGE
OFFSET CHARACTERISTICS WITH
2.7a IN SERIES WITH ANALOG COMMON
Figure 5. AD573 Transfer Curve - Unipolar Operation
(Approximate Bit Weights Shown for Illustration, Nominal
Bit Weights - 9.766mV)
This offset can easily be accomplished as shown in Figure 4b.
At balance (after a conversion) approximately 2mA flows into
the Analog Common terminal. A 2.7.0 resistor in series with
this terminal will result in approximately the desired 'h bit
offset of the transfer characteristics. The nominal 2mA Analog
Common current is not closely controlled in manufacture. If
high accuracy is required, a 5.0 potentiometer (connected as a
rheostat) can be used as Rl. Additional negative offset range
may be obtained by using larger values of Rl. Of course, if the
zero transition point is changed, the full scale transition point
will also move. Thus, if an offset of 'hLSB is introduced, full
scale trimming as described on the previous page should be
done with an analog input of 9.985 volts.
NOTE: During a conversion, transient currents from the Analog
Common terminal will disturb the offset voltage. Capacitive
decoupling should not be used around the offset network. These
transients will settle appropriately during a conversion. Capacitive
10000000 01
10000000 00'
0""11' l'
01111111 10
I
---'
-30 -20 -10
0
+10 +20 +30
INPUT VOLTAGE - mY
Figure 6. AD573 Transfer Curve - Bipolar Operation
Note that in the bipolar mode, the code transitions are offset
'hLSB such that an input voltage of 0 volts ± SmV yields the
code representing zero (10000000 00). Each output code is then
centered on its nominal input voltage.
Full Scale Calibration
Full Scale Calibration is accomplished in the same manner as in
Unipolar operation except the full scale input voltage is +4.985
volts.
Negative Full Scale Calibration
The circuit in Figure 4a can also be used in Bipolar operation to
offset the input voltage (nominally - SV) which results in the
00000000 00 code. R2 should be omitted to obtain a symmetrical
range.
The bipolar offset control input is not directly TTL compatible
but a TTL interface for logic control can be constructed as
shown in Figure 7.
Figure 7. Bipolar Offset Controlled by Logic Gate
Gate Output = 1 Unipolar 0- 10V Input Range
Gate Output =
Bipolar ± 5V Input Range
a
SAMPLE-HOLD AMPLIFIER CONNECTION TO THE
ADS73
Many situations in high-speed acquisition systems or digitizing
rapidly changing signals require a sample-hold amplifier (SHA)
in front of the A-D converter. The SHA can acquire and hold a
ANALOG-TO-DIGITAL CONVERTERS 3-33
•
signal faster than the converter can perform a conversion. A
SHA can also be used to accurately defme the exact point in
time at which the signal is sampled. For the ADS73, a SHA can
also serve as a high input impedance buffer.
Figure 8 shows the AD573 connected to the AD582 monolithic
SHA for high speed signal acquisition. In this configuration, the
AD582 will acquire a 10 volt signal in less than 1OI1-s with a
droop rate less than 10011-V/ms.
+5V
CONVERT PULSE
CONVERT
pulse at least sOOns wide. The rising edge of this pulse resets
the internal logic, clears the result of the previous conversion,
and sets DR high. The falling edge of CONVERT begins the
conversion cycle. When conversion is completed DR returns
low. During the conversion cycle, HBE and LBE should be
held high. If HBE or LBE goes low during a conversion, the
data output buffers will be enabled and intermediate conversion
results will be present on the data output pins. This may cause
bus conflicts if other devices in" a system are trying to use the
bus.
V+
.--_---+----; ANALOG IN
i5ATAREADV
5
~:-T
HiE
AD573
Figure 9.
Reading the Data
The three-state data output buffers are enabled by HBE and
LBE. Access time of these buffers is typically 1500s (250
maximum). The Data outputs remain valid until SOns after the
enable signal returns high, and are completely into the high-impedance state lOOns later.
VLBE OR HBE _ _..,,--,.1
VII + VII.
-15V
--.-
15 VOLT
COM
Figure 8. Sample-Hold Interface to the AD573
DR goes high after the conversion is initiated to indicate that
reset of the SAR is complete. In Figure 8 it is also used to put
the ADS82 into the hold mode while the AD573 begins its
conversion cycle. (The AD582 settles to [mal value well in advance
of the first comparator decision inside the ADS73).
DR goes low when the conversion is complete placing the AD582
back in the sample mode. Configured as shown in Figure 8, the
next conversion can be initiated after a 10l1-s delay to allow for
signal acquisition by the AD582.
Observe carefully the ground, supply, and bypass capacitor
connections between the two devices. This will minimize ground
noise and interference during the conversion cycle.
GROUNDING CONSIDERATIONS
The AD573 provides separate Analog and Digital Common
connections. The circuit will operate properly with as much as
±200mV of common mode voltage between the two commons.
This permits more flexible control of system common bussing
and digital and analog returns.
In normal operation, the Analog Common terminal may generate
transient currents of up to 2mA during a conversion. In addition
a static current of about 2mA will flow into Analog Common in
the unipolar mode after a conversion is complete. The Analog
Common current will be modulated by the variations in input
signal.
The absolute maximum voltage rating between the two commons
is ± I volt. It is recommended that a parallel pair of back-to-back
protection diodes be connected between the commons if they
are not connected locally.
CONTROL AND TIMING OF THE AD573
The operation of the AD573 is controlled by three inputs: CONVERT, HBE and LBE.
Starting a Conversion
The conversion cycle is initiated by a positive-going CONVERT
3-34 ANALOG-TO-DIGITAL CONVERTERS
D~DB1
DBa-on
_
IMPEDANCE
~~HI~GH~~~~E:~~::t===~
figure 10. Read Timing
TIMING SPECIFICATIONS (All grades, TA = Tmia - TmaJ
Parameter
Symbol Min Typ Max Units
CONVERTPuIseWidth
tcs
DR Delay from CONVERT tose
Conversion Time
tc
500
Data Access Time
too
Data Valid after HBEILBE
High
tHO
Output Float Delay
tHL
10
1
20
1.5
30
ns
I1-S
I1-S
0
150
250
ns
100
200
ns
ns
50
MICROPROCESSOR INTERFACE CONSIDERATIONS GENERAL
When an analog-to-digital converter like the AD573 is interfaced
to a microprocessor, several details of the interface must be
considered. First, a signal to start the converter must be generated;
then an appropriate delay period must be allowed to pass before
valid conversion data may be read. In most applications, the
AD573 can interface to a microprocessor system with little or no
external logic.
The most popular control signal configuration consists of decoding
the address assigned to the AD573, then gating this signal with
the system's WR signal to generate the CONVERT pulse, and
gating it with RD to enable the output buffers. The use of a
memory address and memory WR and RD signals denotes
"memory-mapped" 1/0 interfacing, while the use of a separate
1/0 address space denotes "isolated 110" interfacing. In 8-bit
bus systems, the lO-bit AD573 will occupy two locations when
data is to be read; therefore, two (usually consecutive) addresses
must be decoded. One of the addresses can also be used as
the address which produces the CONVERT signal during WR
operations.
Figure II shows a generalized diagram of the control logic for
Interfacing to the AD573
an ADS73 interfaced to an 8-bit data bus, where two .addresses
(ADC ADDR and ADC ADDR+ 1) have been decoded. ADC
ADDR starts the converter when written to (the actual data
being written to the converter does not matter) and contains the
high byte data during read operations. ADC ADDR + 1 performs
no function during write operations, but contains the low byte
data during read operations.
087
DB.
DBa
A0573
In both circuits, the short low-going WR pulse sets the CONVERT
line high through a flip-flop. The rising edge of DR (which
signifies that the internal logic has been reset) resets the flip-flop
and brings CONVERT low, which starts the conversion.
Note that tDse is slightly longer when the result of the previous
conversion contains a logic I on the LSB. This means that the
actual CONVERT pulse generated by the circuits in Figure 13
will vary slightly in width.
8·BIT DATA BUS
DBO
Wi!----,
08.
DB.
DB.
JLP
Wi!
CONVERT
A,rAo{
iiii
Figure ". General AD573 Interface to 8-Bit
Microprocessor
In systems where this read-write interface is used, at least 30
microseconds (the maximum conversion time) must be allowed
to pass between starting a conversion and reading the results.
This delay or "timeout" period can be implemented in a short
software routine such as a countdown loop, enough dummy
instructions to consume 30 microseconds, or enough actual
useful instructions to consume the required time. In tightly-timed
systems, the DR line may be read through an external three-state
buffer to determine precisely when a conversion is complete.
Higher-speed systems may choose to use DR to signal an interrupt
to the processor at the end of a conversion.
Figure 13a. Using 74LSOO
Figure 13b. Using 11274LS74
Output Data Format
The ADS73 output data is presented in a left-justified format.
The 8 MSBs (DB9-DB2, pins 10 through 3) are enabled by
HBE (pin 20) and the 2 LSBs (OBI, DBO - pins 2 and I) are
enabled by LBE (pin 19). This allows simple interface to 8-bit
system buses by overlapping the 2 MSBs and the 2 LSBs. The
organization of the data is shown in Figure 14.
When the least significant bits are read (LBE brought low), the
six remaining bits of the byte will contain meaningless data.
These unwanted bits can be masked by logically ANDing the
byte with 11000000 (CO hex), which forces the 6 lower bits to
logic 0 while preserving the two most significant bits of the
byte.
Note that it is not possible to reconfigure the AD573 for right
justified data.
LBE
I
DB1 lOBO
I
X
X
X
X
x
X
Figure 14. AD5730utputDataFormat
In systems where all 10 bits are desired at the same time, HBE
and LBE may be tied together. This is useful in interfacing to
16-bit bus systems. The resulting lO-bit word can then be placed
at the high end of the 16-bit bus for left justification or at the
low end for right justification.
Figure 12. Typical AD573 Interface Timing Diagram
CONVERT Pulse Generation
The ADS73 is tested with a CONVERT pulse width of sOOns
and will typically operate with a pulse as short as 3000s. However,
some microprocessors produce active WR pulses which are
shorter than this. Either of the circuits shown in Figure 13 can
be used to generate an adequate CONVERT pulse for the AD573.
It is also possible to use the ADS73 in a "stand-alone" mode,
where the output data buffers are automatically enabled at the
end of a conversion cycle. In this mode, the DR output is wired
to the HBE and LBE inputs. The outputs thus are forced into
the high-impedance state during the conversion period, and
valid data becomes available approximately 500ns after the DR
signal goes low at the end of the conversion. The SOOns delay
allows propagation of the least significant bit through the internal
logic.
This mode is particularly useful for bench-testing of the ADS73,
and in applications where dedicated 110 ports of peripheral
interface adapter chips are available.
ANALOG-TO-DIGITAL CONVERTERS 3-35
delay between starting and reading the converter. This can be
easily implemented by calling the Apple's WAIT subroutine
(which resides at location $FCA8) after loading the accumulator
with a number greater than or equal to two.
CONVERT
PULSE
808S-Series Microprocessor Interface
The AD573 can also be used with 8085-series microprocessors.
These processors use separate control signals for RD and WR,
as opposed to the single RfW control signal used in the 6800/6500
series processors.
Figure 15. AD573in "Stand-Alone " Mode
(Output Data Valid 500ns After DR Goes Low)
Apple II Microcomputer Interface
The AD573 can provide a flexible, low-cost analog interface for
the popular Apple II microcomputer. The Apple II, based on a
IMHz 6502 microprocessor, meets all timing requirements for
the AD573. Only a few TTL gates are required to decode the
signals available on the Apple II's peripheral connector. The
recommended connections are shown in Figure 16.
There are two constraints related to operation of the ADS73
with 808S-series processors. The first problem is the width of
the CONVERT pulse. The circuit shown in Figure 17 (essentially
the same as that shown in Figure 13) will produce a wide enough
CONVERT pulse when the 8085 is running at 5MHz. For 8085
systems running at slower clock rates (3MHz), the flip-flop-based
circuit can be eliminated since the WR pulse will be approximately
soons wide.
The other consideration is the access time of the ADS 73's threestate output data buffers, which is 2s0ns maximum. It may be
necessary to insert wait states during RD operations from the
ADs73. This will not be a problem in systems using memories
with comparable access times, since wait states will have already
been provided in the basic system design.
BOBSA
APPLE II
PERIPHERAL
CONNECTOR
AD573
~Em¥
DB'
DBB
DBB
DB.
DB'
Wii
A0573
DB'
DB.
CONVERT
41
015
DR
0'
AO
HiE
i:BE
iii)
Figure 17. AD573-BOB5A Interface Connections
A: 1/474LS32
B: 1/674LS04
Figure 16. AD573 Interface to Apple II
The BASIC routine listed here will operate the ADs73 circuit
shown in Figure 16. The conversion is started by POKEing to
the location which contains the ADs73. The relatively slow
execution speed of BASIC eliminates the need for a delay routine
between starting and reading the converter. This routine assumes
that the ADs73 is connected for a ± 5 volt input range. Variable
I represents the integer value (from 0 to 1023) read from the
ADs73. Variable V represents the actual value of the input
signal (in volts).
100
llO
120
130
140
-150
160
PRINT "WHICH SLOT IS THE AID IN";:INPUT S
A= 49280+ 16*S
POKE A,O
L=PEEK(A) :H=PEEK(A+I)
I=(4*H)+INT(Ll64)
V = (1/1024)*10-5
PRINT "THE INPUT SIGNAL IS ";V;"VOLTS."
It is also possible to write a faster-executing assembly-language
routine to control the ADS73. Such a routine will require a
3-36 ANALOG-TO-DIGITAL CONVERTERS
The following assembly-language subroutine can be used to
control an ADS73 residing at memory locations 3000H and 3OO1 H •
The 10 bits of data are returned (left-justified) in the DE register
pair.
LXI H,3OO0
MOVM,A
MVI B,06
LOOP: DCRB
JNZ LOOP
MOVA,M
ANI CO
MOVE,A
ADC:
INR L
MOVD,M
RET
; LOAD HL WITH AD573 ADDRESS
; START CONVERSION
; LOAD DELAY PERIOD
; DELAY LOOP
;
; READ LOW BYTE
; MASK LOWER 6 BITS
; STORE CLEAN LOW BYTE IN E
; LOAD HIGH BYTE ADDRESS
; MOVE HIGH BYTE TO D
; EXIT
Complete
12-Bit AID Converter
1IIIIIIII ANALOG
WDEVICES
AD574A*
FEATURES
Complete 12-Bit AID Converter with Reference
and Clock
8- and 16-Bit Microprocessor Bus Interface
Guaranteed Linearity Over Temperature
o to + 70·C - ADS74AJ, K, L
-S5·C to + 12S·C - AD574AS, T, U
No Missing Codes Over Temperature
35",s Maximum Conversion Time
Buried Zener Reference for Long-Term Stability
and Low Gain T.C. 10ppml"C max ADS74AL
12.Sppml"C max ADS74AU
Ceramic DIP, Plastic DIP or PLCC Package
AD574A BLOCK DIAGRAM
AND PIN CONFIGURATION
STATUS
STS
+6VSUPPLV
VLOGIC
DATA MODE SEL,~t
2
OS"
CHIPSELE~
3
OB10
II
MSB
BYTE ADDRESSI
SHORT CYCLE
4
DB9
REAOICONV~?l
5
DB.
Ao
CHIP ENAB~~
6
DB7
+12/+16V SUPPLY
Vee
7
DB.
DIGITAL
+1OV RE~EE'::EZB~
8
DB.
OUTPUTS
DATA
ANALOG COMMON
AC
REFERENCE INPUT
REFIN
DB.
•
DB3
-,21-1SV SUPPLY
DB2
VEE
BIPOLAR OFFSET
BIPOFF
DBI
10V SPAN INPUT
10\10
.k
DB.
LSB
20V SPAN INPUT
PRODUCT DESCRIPTION
15 ~GITAL COMMON
12
20VIN
AD574A
The AD574A is a complete 12-bit successive-approximation
analog-to-digital converter with 3-state output buffer circuitry
for direct interface to an 8- or 16-bit microprocessor bus. A
PRODUCT HIGHLIGHTS
high-precision voltage reference and clock are included on-chip,
1. The AD574A interfaces to most 8- or l6-bit microprocessors.
and the circuit guarantees full-rated performance without external
Multiple-mode three-state output buffers connect directly to
circuitry or clock signals.
the data bus while the read and convert commands are taken
The AD574A design is implemented using Analog Devices'
from the control bus. The 12 bits of output data can be read
2
all
analog
and
digital
functions
Bipolar/I L process, and integrates
either as one l2-bit word or as two 8-bit bytes (one with 8
on one chip. Offset, linearity and scaling errors are minimized
data bits, the other with 4 data bits and 4 trailing zeros).
by active laser-trimming of thin-fIlm resistors at the wafer stage.
2.
The
precision, laser-trimmed scaling and bipolar offset resistors
The voltage reference uses an implanted buried Zener for low
provide four calibrated ranges: 0 to + 10 and 0 to + 20 volts
noise and low drift. On the digital side, I2L logic is used for the
unipolar, - 5 to + 5 and -10 to + 10 volts bipolar. Typical
successive-approximation register, control circuitry and 3-state
bipolar offset and full-scale calibration errors of ±O.l% can
output buffers.
be trimmed to zero with one external component each.
The AD574A is available in six different grades. The AD574A},
3. The internal buried Zener reference is trimmed to 10.00
K, and L grades are specified for operation over the 0 to + 70°C
volts with 0.2% maximum error and 15ppmfC typical T.C.
temperature range. The AD574AS, T, and U are specified for
The reference is available externally and can drive up to
the - 55°C to + 125°C range. All grades are available in a 28-pin
1.5mA beyond the requirements of the reference and bipolar
hermetically-sealed ceramic DIP. The}, K, and L grades are
offset resistors.
also available in a 28-pin plastic DIP and PLCC.
The S, T, and U grades are available with optional processing
to MIL-STD-883C Class B. The Analog Devices' Military Products
Databook should be consulted for details on /883B testing of the
AD574A.
*Protected by U.S. Patent Nos. 3,803,590; 4,213,806; 4,511,413;
RE 28,633.
ANALOG-TO-OIGITAL CONVERTERS 3-37
SPECIFICATIONS
(@ +25"& with Vee
= +15Vor +l2V, VlOGlC = +5V,VEE = -15V or -12V
unless o1IIerwise indicated)
AD574AJ
Model
Min
Typ
AD574AL
AD574AK
Max
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
12
12
12
Bits
UNEARITY ERROR@ + 25°C
Tmin to Tmu:
±1
±1
±112
±112
±112
±112
LSB
LSB
DIFFERENTIAL LINEARITY ERROR
(Minimum resolution for which no
missing codes are guaranteed)
TmintoTmu.
11
12
Bits
12
UNIPOLAR OFFSET (Adjustable to zero)
±2
±1
±1
LSB
BIPOLAR OFFSET (Adjustable to zero)
±4
±4
±2
LSB
FULL·SCALECAUBRATION ERROR
(with fixed son resistor from REF OUT to REF IN)
(Adjustable to zero)
TEMPERATURE RANGE
0.25
0
0.125
%ofF.S.
+70
"C
±1(5)
±1(5)
±5(27)
±1(5)
±1(5)
±2(10)
LSB (ppmI"C)
LSB(ppml"C)
LSB (ppml"C)
±2
±1
±112
±112
±2
±1
±1
±112
±1
LSB
LSB
LSB
+5
+10
+10
+20
Volts
7
14
kll
kll
+5.5
+0.8
+20
Volts
Volts
+70
0.25
+70
0
0
TEMPERATURE COEFFICIENTS
(Using internal reference)
TmintoTmax
±2(1O)
±2(1O)
±9(50)
Unipolar Offset
Bipolar Offset
Full-Scale CaIibralion
POWER SUPPLY REJECTION
Max change in Full Scale Calibration
Vee = 15V ± 1.5Vorl2V ±0.6V
V LOGIC = 5V ± O.5V
V•• = -15V ± 1.5Vor -12V ±0.6V
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
DIGITAL CHARACTERISTICS' (Tmm-T~)
Inputs' (CE, <:S, RIC, Ao)
Logic "1" Voltage
Logic "0" Voltage
Current
Capacitance
Outputs(DBII-DBO, STS)
Logic "I" Voltage (lsouRcE:55001lA)
Logic "O"Voltage(l sINK :== 1.6mA)
Leakage(DBll-DBO, High·Z State)
Capacitance
POWER SUPPUES
Operating Range
V LOG1C
Vee
VEE
Operating Current
-5
-10
0
0
3
6
+2.0
-0.5
-20
-5
-10
0
0
7
14
3
6
+5.5
+0.8
+20
+2.0
-0.5
-20
+0.4
+20
-20
+,4.5
+11.4
-11.4
I..
9.98
PACKAGE OPTIONS'
Ceramic (D.28)
Plastic (N·28)
PLCC (P·28A)
7
14
3
6
+5.5
+0.8
+20
+2.0
-0.5
-20
30
2
18
40
390
725
10.0
10.02
1.5
5
30
AD574ASD
AD574AJN
AD574AJP
9.98
30
2
18
40
390
725
10.0
10.02
1.5
AD574AKD
AD574AKN
AD574AKP
9.99
Volts
+5.5
+ 16.5
-16.5
Volts
40
3-38 ANALOG· TO-DIGITAL CONVERTERS
ILA
pF
Volts
Volts
30
2
18
5
30
mA
mA
rnA
390
725
mW
10.0
10.01
1.5
Volts
mA
AD574ALD
AD574ALN
NOTES
Specifications shown in boldface are tested on all production units at fmal electri~
IDetailed TimingSpecifIcations appear in the Timing Section.
212/8 Input is not TI'L..compatibleand must be hard wired to VLOGIC or Digital Common. cal test. Results from those tests are used to calculate outgoing quality levels. AU
min and max specifications are guaranteed, although only those shown in
Yfhe reference should be buffered foroperationon ± 12V supplies.
bo1dfaceare tested. on all production units.
4See Section 14 for package outline infonnation.
Specifications subject to change without notice.
IlA
Volts
+4.5
+ 11.4
-11.4
5
30
Volts
+0.4
+20
5
+5.5
+ 16.5
-16.5
+4.5
+11.4
-11.4
Volts
Volts
pF
+2.4
-20
5
+5.5
+16.5
-16.5
5
10
5
+0.4
+20
-20
5
POWER DISSIPATION
-5
-10
0
0
+2.4
+2.4
lee
5
10
+5
+10
+10
+20
5
5
I LOGIC
INTERNAL REFERENCE VOLTAGE
Output current (available for external loads)'
(External load should not change duting conversion)
5
10
+5
+10
+10
+20
AD574A
ADS74AS
Min
Model
Typ
Mas
Min
ADS74AT
Typ
ADS74AU
'Max
Min
Typ
Mas
Unit.
RESOLUTION
12
12
12
Bits
LINEARITY ERROR @ + 2S'C
±I
±I
±1/2
±I
±112
±I
LSB
LSB
TmintoTmu:
DIFFERENTIAL LINEARITY ERROR
(Minimum resolution for which no
missing codes are guaranteed)
Tmi,p[oT mu
Bits
12
12
11
UNIPOLAR OFFSET (Adjustable to zero)
±2
±I
±I
LSB
BIPOLAR OFFSET (Adjustable to zera)
±4
±4
±2
LSB
FULL·SCALE CALIBRATION ERROR
(with fIXed son resistor from REF OUT to REF IN)
(Adjustable to zero)
TEMPERATURE RANGE
0.2S
-55
0.2S
+ 125
-55
+125
-55
0.12S
%ofF.S.
+ 125
'C
TEMPERATURE COEFFICIENTS
(Using internal reference)
TmintoTmax
Unipolar Offset
Bipolar Offset
Full~Sca1e Calibration
±2(S)
±4(10)
±20(SO)
:!: I (2.5)
±2(S)
±10(2S)
:!:1(2.S) LSB(ppml"C)
±1(2.5) LSB (ppml'C)
±S(12.S) LSB(ppml"C)
:!:2
±112
±2
±I
±112
:!:I
±I
:!:1/2
:!:I
LSB
LSB
LSB
+S
+10
+10
+20
Volts
7
14
kll
kll
+5.5
+0.8
Volts
Volts
fLA
pF
POWER SUPPLY REJECTION
Max change in Full Scale Calibration
Vee = ISV ± 1.5Vorl2V ±0.6V
VLOGIe = SV ± O.SV
VEE = -ISV ± I.SV or - 12V ± 0.6V
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
IOVoltSpon
20 Volt Span
DIGITAL CHARACTERISTICS' (T min-T~)
Inputs' (CE, CS, RIC, Aa)
Logic" 1" Voltage
Logic "0" Voltage
Current
Cspscitance
Outputs (DBII-DBO, STS)
Logic n 1" Voltage (lsQURCE:sSOOJLA)
Logic "0" Voltage (ISlNK '" 1.6rnA)
Leakage (DBII-DBO, High·Z State)
Capacitance
-S
-10
0
0
3
6
5
10
+S
+10
+10
+20
-S
-10
0
0
7
14
6
+5.5
+0.8
+20
+2.0
-0.5
-20
+2.0
-0.5
-20
3
5
10
+S
+10
+10
+20
-S
-10
0
0
7
14
6
+5.5
+0.8
+20
+2.0
-0.5
-20
3
+2.4
+2.4
+2.4
+0.4
+20
+0.4
+20
-20
-20
+0.4
+20
-20
5
5
5
+20
5
5
5
5
10
Volts
Volts
Volts
Volts
Volts
fLA
pF
POWER SUPPLIES
Operating Range
VLOGIC
Vee
VEE
+4.5
+11.4
-11.4
+5.5
+ 16.5
-16.5
+5.5
+ 16.5
-16.5
+4.5
+11.4
-11.4
+s..S
+16.5
-16.5
Volts
Volts
30
2
18
40
S
30
rnA
rnA
rnA
390
ns
mW
10.0
10.01
Volts
rnA
+4.5
+11.4
-11.4
Volts
Operating Current
lLOGIC
Icc
I..
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output current (available for externa11oads)'
(Extemalload should not changeduringconveraion)
PACKAGE OPTIONS'
Ceramic (D·28)
9.98
30
2
18
40
S
30
390
ns
10.0
10.02
1.5
ADS74ASD
9.98
30
2
18
40
S
30
390
ns
10.0
10.02
1.5
ADS74ATD
9.99
I.S
ADS74AUD
NOTES
IDetailed Timing Specifications appear in the Timing Section.
12/8 Input is not TTL-compatible and must be hard wired to VLOGIc or Digital Common.
lThe reference should be buffered for operation on ± 12V supplies.
2
4See Section 14 for package outline information.
Specifications shown in boldface are tested on all production units at fmal electricaJ test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed, although only those shown in
boldface are tested on all production units.
Specifications subject to change without notice.
ANALOG-TO-OIGITAL CONVERTERS 3-39
•
+6VSUPPLY
STATUS
STS
VLOGtc
DATA MOOESEL,~
2
DBl1
CHIPSELE~
3
OBI.
4
DB8
READICONV~?i
6
DB8
CHIP ENA8~~
MSB
BYTE AOORESS!
SHORT CYCLE
Ao
6
DB7
+12/+1SV SU'\,~
7
DB6
+1OV RE':ERFEmi~
8
DB5
ANALOG COMMON
DIGITAL
OATA
OUTPUTS
DBA
AC
REFERENCE INPUT
REF IN
DB3
-121-1SV SUPPLY
DB2
VEE
BIPOLAR OFFSET
BIPOFF
DB'
DBO
10V SPAN INPUT
llIIo\N
LSB
20V SPAN INPUT
ZOVIN
15 ~GITAL COMMON
AD574A """-2_ _ _- - '
AD574A Block Diagram and Pin Configuration
ABSOLUTEMAXIMUMRATINGS*
(Specifications apply to all grades, except where noted)
vcc to Digital Common
. .
.0 to + 16.5V
VBE to Digital Common . .
.0 to -16.5V
VLOGIC to Digital Common
o to +7V
Analog Common to Digital Common
. . . . . ±lV
ControIInputs(CE,CS,Ao,12/8,RlC)to
Digital Common .. -0.5V to VLOGIC +0.5V
AnalogInputs(REFIN,BIPOFF,lOVIN)to
Analog Common
. . . . . . . . VBE to Vcc
20VIN to Analog Common.
. . . . . . . . . . . ±24V
REF OUT . . . . . . . . . . .
Indefmite short to common
Momentary short to Vcc
Chip Temperature . . . . . .
Power Dissipation . . . . . .
Lead Temperature, Soldering
Storage Temperature (Ceramic)
(Plastic) .
175°C
. . . . 82SmW
+ 300°C, 10 sec.
-65°C to + 150°C
- 25°C to + 100°C
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a Stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ADS14A ORDERING GUIDE
Model*
Temp. Range
Linearity Error
Max (Tmin to T max)
AD574AJ(X)
AD574AK(X)
AD574AL(X)
ADS74AS(X)
AD574AT(X)
AD574AU(X)
Oto + 70°C
Oto + 70°C
Oto + 700C
- 55°C to + 125°C
~ 55°C to + 125°C
- WC to + 125°C
±lLSB
±1I2LSB
±1I2LSB
±lLSB
±lLSB
±lLSB
NOTES
*X = Package designator. Available packages are:
D (0·28) for all grsdes.
E (E-28) for J,K,S, T, Ugrsdes.
N (N·28) for J, K,andLgrsdes.
PforPLCCinJ, Kgrsdes.
Example: AOS74AKN is K grsde in plastic OIP.
3-40 ANALOG·TO·DIGITAL CONVERTERS
Resolution
No Missing Codes
(Tmin to T max)
Max
Full Scale
T.C.(ppmrC)
11 Bits
12 Bits
12 Bits
11 Bits
12 Bits
12 Bits
50.0
27.0
10.0
50.0
25.0
12.5
AD574A
THE ADS74A OFFERS GUARANTEED MAXIMUM LINEARITY ER.R.OR OVER THE FULL OPERATING
TEMPERATURE RANGE
DEFlNmONS OF SPECIFICATIONS
LINEARITY ERROR
Linearity error refers to the deviation of each individual code
from a line drawn from "zero" through "full scale". The point
used as "zero" occurs 1I2LSB (1.22mV for 10 volt span) before
the first code transition (all zeros to only the LSB "on"). "Full
scale" is defmed as a level 1 1I2LSB beyond the last code transition
(to all ones). The deviation of a code from the true straight line
is measured from the middle of each particular code.
The AD574AK, L, T, and U grades are guaranteed for maximum
nonlinearity of ± 1I2LSB. For these grades, this means that an
analog value which falls exactly in the center of a given code
width will result in the correct digital output code. Values nearer
the upper or lower transition of the code width may produce the
next upper or lower digital output code. The AD574AJ and S
grades are guaranteed to ± lLSB max error. For these grades,
an analog value which falls within a given code width will result
in either the correct code for that region or either adjacent one.
Note that the linearity error is not user-adjustable.
DIFFERENTIAL LINEARITY ERROR (NO MISSING
CODES)
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence
as the analog input level is increased. Thus every code must
have a fmite width. For the AD574AK, L, T, and U grades,
which guarantee no missing codes to 12-bit resolution, all 4096
codes must be present over the entire operating temperature
ranges. The AD574AJ and S grades guarantee no missing codes
to ll-bit resolution over temperature; this means that all code
combinations of the upper II bits must be present; in practice
very few of the 12-bit codes are missing.
UNIPOLAR OFFSET
The first transition should occur at a level 1I2LSB above analog
common. Unipolar offset is defmed as the deviation of the actual
transition from that point. This offset can be adjusted as discussed
on the following two pages. The unipolar offset temperature
coefficient specifies the maximum change of the transition point
over temperature, with or without external adjustment.
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1I2LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
QUANTIZATION UNCERTAINTY
Analog-to-digital converters exhibit an inherent quantization
uncertainty of ± 1/2LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
LEFf-JUSTIFIED DATA
The data fonnat used in the AD574A is left-justified. This
means that the data represents the analog input as a fraction of
full-scale, ranging from 0 to : . This implies a binary point
to the left of the MSB.
FULL-SCALE CALIBRATION ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1I2LSB below the nominal
full scale (9.9963 volts for 10.000 volts full scale). The full-scale
calibration error is the deviation of the actual level at the last
transition from the ideal level. This error, which is typically
0.05 to 0.1% of full scale, can be trimmed out as shown in
Figures 3 and 4.
TEMPERATURE COEFFICIENTS
The temperature coefficients for full-scale calibration, unipolar
offset, and bipolar offset specify the maximum change from the
initial (25OC) value to the value at T mOt or T max.
POWER SUPPLY REJECTION
The standard specifications for the AD574A assume use of
+5.00 and ± 15.00 or ± 12.00V supplies. The only effect of
power supply error on the perfortnance of the device will be a
small change in the full-scale calibration. This will result in a
linear change in all lower-order codes. The specifications show
the maximum full-scale change from the initial value with the
supplies at the various limits.
CODE WIDTH
A fundamental quantity for AID converter specifications is the
code width. This is defmed as the range of analog input values
for which a given digital output code will occur. The nominal
value of a code width is equivalent to I least significant bit
(LSB) of the full-scale range or 2.44mV out of 10 volts for a
12-bit ADC.
ANALOG-TO-OIGITAL CONVERTERS 3-41
•
CIRCUIT OPEltATION
The AD574A is a complete 12-bit AID converter which requires
no external components to provide the complete successiveapproximation analog-to-digital conversion function. A block
diagram of the AD574A is shown in Figure 1.
+5YSUf'PLV
v"",.
DATA MODE SEL,~
2
CHIPSELE~
3
DRIVING THE AD574 ANALOG INPUT
The internal circuitry of the ADS74 dictates that its analog
input be driven by a low source impedance. Voltage changes at
the current summing node of the internal comparator result in
abrupt modulations of the current at the analog input. For
aceumte 12-bit conversions the driving source must be capable
of holding a constant output voltage under these dynamically
changing load conditions.
FEEDBACK TO AMPLIFIER
BYTE ADDRESS/
SHORT CYCLE
4
Ao
READ!CONVERT
Ric
CHIPENABL£
eE
...,2/+1SV su~
AD674A
7
DIGITAL
DATA
OUTPUTS
""ov REFERENCE
AEFOUT
ANALOG COMMON
At
REFERENCE ~=~~
[1,ooJf-:'!"!:!:",...,h
lIN IS MODULATED BY
CHANGES IN TEST CURRENT.
AMPlIF:IER PULSE LOAD
RESPOtf§E LIMITED BY
OPEN ,~~~ OUTPUT IMPEDANCE.
.121-15Y SUPPJ-E~ 11
BIPOLAR ~:;!'~~~ 12
ANALOG COMMON
lOVSPAN I~~ l"'"]', _ _- ,
20V SPAN 1:V~
14
15 ~GITAL COMMON
Figure2. OpAmp-AD574Alnterface
Figure 1. BlockDiagramofAD574A 12-BitA-to-DConverter
When the control section is commanded to initiate a conversion
(as described later), it enables the clock and resets the successiveapproximation register (SAR) to all zeros. Once a conversion
cycle has begun, it cannot be stopped or re-started and data is
not available from the output buffers. The SAR, timed by the
clock, will sequence through the conversion cycle and return an
end-of-convert flag to the control section. The control section
will then disable the clock, bring the output status flag low, and
enable control functions to allow data read functions by external
command.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most significant bit
(MSB) to least significant bit (LSB) to provide an output current
which accumtely balances the input signal current through the
SkO (or 10kO) input resistor. The comparator determines whether
the addition of each successively-weighted bit current causes the
DAC current sum to be greater or less than the input current;
if the sum is less, the bit is left on; if more, the bit is turned
off. After testing all the bits, the SAR contains a 12-bit binary
code which accumtely represents the input signal to within
±1I2LSB.
The tempemture-compensated buried zener reference provides
the primary voltage reference to the DAC and guarantees excellent
stability with both time and temperature. The reference is trimmed
to 10.00 volts ± 0.2%; it can supply up to 1.SmA to an c;xternal
load in addition to the requirements of the reference input resistor
(O.SmA) and bipolar offset resistor (lmA) when the ADS74A is
powered from ± ISV supplies. If the AD574A is used with
± 12V supplies, or if external current must be supplied over the
full temperature range, an external buffer amplifier is recommended. Any external load on the AD574A reference must
remain constant during conversion. The thin-fIlm application
resistors are trimmed to match the full-scale output current of
the DAC. There are two SkO input scaling resistors to allow
either a 10 volt or 20 volt span. The 10kO bipolar offset resistor
is grounded for unipolar operation and connected to the 10 volt
reference for bipolar operation.
3-42 ANALOG-TO-DIGITAL CONVERTERS
The output impedance of an op amp has an open-loop value
which, in a closed loop, is divided by the loop gain available at
the frequency of interest. The amplifier should have acceptable
loop gain at SOOkHz for use with the ADS74A. To check whether
the output properties of a signal source are suitable, monitor the
AD574's input with an oscilloscope while a conversion is in
progress. Each of the 12 disturbances should subside in III-s or
less.
For applications involving the use of a sample-and-hold amplifier,
the ADS85 is recommended. The AD711 or ADS44 op amps
are recommended for dc applications.
SAMPLE-AND-HOLD AMPLIFffiRS
Although the conversion time of the ADS74A is a maximum of
3SlI-s, to achieve accurate 12-bit conversions of frequencies greater
than a few Hz requires the use of a sample-and-hold amplifier
(SHA). If the voltage of the analog input signal driving the
ADS74A changes by more than 1I2LSB over the time interval
needed to make a conversion, then the input requires a SHA.
The AD58S is a high-linearity SHA capable of directly driving
the analog input of the AD574A. The ADS8S's fast acquisition
time, low aperture and low aperture jitter are ideally suited for
high-speed data acquisition systems. Consider the ADS74A
converter with a 3SII-s conversion time and an input signal of
lOY pop: the maximum frequency which may be applied to
achieve mted accuracy is 1.5Hz. However, with the addition of
an AD58S, as shown in Figure 3, the maximum frequency
increases to 26kHz.
The ADS8S's low output impedance, fast-loop response, and
low droop maintain 12-bits of accumcy under the changing load
conditions that occur during a conversion, making it suitable for
use in high-accuracy conversion systems. Many other SHAs
cannot achieve 12-bits of accumcy and can thus compromise a
system. The ADS85 is recommended for ADS74A applications
requiring a sample and hold.
AD574A
UNIPOLAR RANGE CONNECTIONS FOR TIlE AD574A
The ADS74A contains all the active components required to
perform a complete 12-bit AID conversion. Thus, for most
situations, all that is necessary is connection of the power supplies
( + 5, + 121 + 15 and -12/ - 15 volts), the analog input, and the
conversion initiation command, as discussed on the next page.
Analog input connections and calibration are easily accomplished;
the unipolar operating mode is shown in Figure 4.
STS
OFFSET
Rl
lOOk
HIGH
BIT
Ao
-12V1-1SV
RIC
MIDDLE
BITS
AD574A
Non
1. Ct. C2, C3 ARE 47..F TANTALUM, 8YPASSED BY
lOOk
REF IN
O·'l1f CERAMIC. lOCATE AT ASSOCIATED A2 PINS.
LOW
BITS
Figure 3. AD574A with AD585 Sample and Hold
10011
SUPPLY DECOUPLING AND LAYOUT
CONSIDERATIONS
It is critically important that the ADS74A power supplies be
filtered, well regulated, and free from high~frequency noise. Use
of noisy supplies will cause unstable output codes. Switching
power supplies are not recommended for circuits attempting to
achieve 12-bit accuracy unless great care is used in filtering any
switching spikes present in the output. Remember that a few
millivolts of noise represents several counts of error in a 12-bit
ADC.
Decoupling capacitors should be used on all power supply pins;
the + SV supply decoupling capacitor should be connected
directly from pin 1 to pin IS (digital common) and the + Vcc
and - VEE pins should be decoupled directly to analog common
(pin 9). A suitable decoupling capacitor is a 4.7jLF tantalum
type in parallel with a 0.1 jLF disc ceramic type.
Circuit layout should attempt to locate the ADS74A, associated
analog input circuitry, and interconnections as far as possible
from logic circuitry. For this reason, the use of wire-wrap circuit
construction is not recommended. Careful printed-circuit construction is preferred.
GROUNDING CONSIDERATIONS
The analog common at pin 9 is the ground reference point for
the internal reference and is thus the "high quality" ground for
the ADS74A; it should be connected directly to the analog
reference point of the system. In order to achieve all of the
high-accuracy performance available from the ADS74A in an
environment of high digital noise content, the analog and digital
commons should be connected together at the package. In some
situations, the digital common at pin 15 can be connected to the
most convenient ground reference point; analog power return is
preferred.
BIP OFF
o TO
+10V
ANALOG
INPUTS
10VIN
20VIN
-15V
OTO +20V
~
Figure 4. Unipolar Input Connections
All of the thin-film application resistors of the ADS74A are
trimmed for absolute calibration. Therefore, in many applications,
no calibration trimming will be required. The absolute accuracy
for each grade is given in the specification tables. For example,
if no trims are used, the ADS74AK guarantees ± lLSB max
zero offset error and ±0.2S% (lOLSB) max full-scale error.
(Typical full-scale error is ± 2LSB.) If the offset trim is not
required, pin 12 can be connected directly to pin 9; the two
resistors and trimmer for pin 12 are then not needed. If the fullscale trim is not needed, a son ± 1% metal film resistor should
be connected between pin 8 and pin 10.
The analog input is connected between pin 13 and pin 9 for a 0
to + 10V input range, between 14 and pin 9 for a 0 to + 20V
input range. The ADS74A easily accommodates an input signal
beyond the supplies. For the 10 volt span input, the LSB has a
nominal value of 2.44mV; for the 20 volt span, 4.88mV. If a
10.24V range is desired (nominal 2.SmVlbit), the gain trimmer
(R2) should be replaced by a son resistor, and a 200n trimmer
inserted in series with the analog input to pin 13 for a full-scale
range of 20.48V (SmVlbit), use a soon trimmer into pin 14.
The gain trim described below is now done with these trimmers.
The nominal input impedance into pin 13 is SkO, and 10kO
into pin 14.
ANALOG-TO-DIGITAL CONVERTERS 3-43
•
UNIPOLAR CALIBllAll0N
The ADS74A is intended to have a nominal 1/2LSB offset so
that the exact analog input for a given ~ will be in the middle
of that code (halfway between the transitions to the codes above
and 'below it). Thus, the first transition (from 0000 0000 0000 to
0000 0000 0001) will occur for an input level of + II2LSB (1.22mV
for 10V range).
STATUS
---0< 1----+---..,....
If pin 12 is connected to pin 9, the unit will behave in this
manner, within specifications. If the offset trim (RI) is used, it
VALUE OFAO
AT LAST CONVERT
COMMAND
should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give
approximately ± ISmV of offset trim range.
J-!!""'---.,
The full-scale trim is done by applying a signal I 1/2LSB below
the nominal full scale (9.9963 for a 10V range). Trim R2 to give
the last transition (1111 1111 1110 to 1111 1111 1111).
1218
r---<".s:=-==-- EOCB} 'ROM
EOC12
~==:::;~:::::;~--F=t.,..)
lNOTEZI
NOTE 1
:::~E:' B. } TO OUTPUT
ENABLE
BUFFERS
NI88LE B=O
ENABLE
BIPOLAR OPERAll0N
The connections for bipolar ranges are shown in Figure S. Again,
as for the unipolar ranges, if the offset and gain specifications
are sufficient, one or both of the trimmers shown can be replaced
by a SOO ± 1% fIXed resistor. Bipolar calibration is similar to
unipolar calibration. First, a signal ~LSB above negative full
scale (-4.9988V for the ± SV range) is applied and RI is trimmed
to give the first transition (0000 0000 0000 to 0000 0000 0001).
Then a signall~LSB below positive full scale (+4.9963V for
the ± SV range) is applied and R2 trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
STS
HIGH
BITS
OFFSET-'lWIr..--{
±5V
ANALOG
INPUTS 0 -_ _ _ _.(
±10V
Figure 5. Bipolar Input Connections
CONTROL LOGIC
The ADS74A contains on-chip logic to provide conversion initiation and data read operations from signals commonly available
in microprocessor systems. Figure 6 shows the internal logic
circuitry of the ADS74A.
The control signals CE, CS, and RIC control the operation of
the converter'. The state of RIC when CE and CS are both asserted
determines whether a data read (RlC= 1) or a convert (RIC =
0) is in progress. The register control inputs Ao and l2i8 control
conversion length and data format. The Ao line is usually tied
to the least significant bit of the address bus. If a conversion is
started with Ao low, a full 12-bit conversion cycle is initiated. If
3-44 ANALOG-TO-DIGITAL CONVERTERS
NOTE 1: WHEN i'i'Aifi CONVERT GOES LOW, THE EOC lEND OF CONVERSIONI SIGNALS GO LOW.
EOCI RETURNS HIGH AFTER AN 8.eIT CONVERSK)N CYCLE IS COMPLETE. AND EOC1Z
RETURNS HIGH WHEN ALL 12 BITS HAVE BEEN CONVERTED. THE EDC SIGNALS PREVl:NT
DATA FROM BEING READ DU'FIINO CONVERSIONS.
NOTE 2: 12m IS NOT A TTL·COMPATIBlE INPUT AND SHOULD ALWAYS BE WlftED DIRECTLY TD
VUIGIC OR DIGITAL COMMON.
Figure 6. AD574A Control Logic
Ao is high during a convert start, a shorter 8-bit conversion
cycle results. During data read operations, Ao determines whether
the three-state buffers containing the 8 MSBs of the conversion
result (Ao = 0) or the 4 LSBs (Ao = I) are enabled. The 1218
pin determines whether the output data is to be organized as
two 8-bit words (12/8 tied to DIGITAL COMMON) or a single
12-bit word (1218 tied to VLOGlcl. The 12i8 pin is not TTLcompatible and must be hard-wired to either V LOGIC or DIGITAL
COMMON. In the 8-bit mode, the byte addressed when Ao is
high contains the 4 LSBs from the conversion followed by four
trailing zeroes. This organization allows the data lines to be
overlapped for direct interface to 8-bit buses without the need
for external three-state buffers.
It is not recommended that Ao change state during a data read
operation. Asymmetrical enable and disable times of the three-state
buffers could cause internal bus contention resulting in potential
damage to the ADS74A.
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the convel'Sion cycle is complete.
CE
B
RIC 1218
Ao
Operation
0
X
X
I
X
X
X
X
X
X
None
None
0
0
0
0
X
X
0
I
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
0
Pin I
X
Enable 12-Bit Parallel Output
0
0
Pin IS
Pin IS
0
I
Enable 8 Most Significant Bits
Enable4LSBs +4TrailingZeroes
Table I. AD574A Truth Table
TIMING
The ADS74A is easily interfaced to a wide variety of microprocessors and other digital systems. The following discussion of
the timing requirements of the ADS74A control aignals should
provide the system designer with useful insight into the operation
of the device.
AD574A
CONVERT START TIMING-FULL CONTROL MODE
MiD
Symbol
Parameter
tose
tHEe
tssc
tHSC
STS Delay from CE
CE Pulse Width
CS toCE Setup
CS Low DuringCE High
RIC to CE Setup
RIC Low DuringCE High
Ao to CE Setup
Ao Valid DuringCE High
Conversion Time
g-BitCycle
12-Bit Cycle
[SRe
tHRC
[SAC
tHAC
le
Typ
Units
400
ns
ns
ns
ns
ns
ns
ns
ns
300
300
200
250
200
0
300
10
IS
In the 8-bit bus interface mode (12/8 input wired to DIGITAL
Max
24
35
fJ.s
fJ.s
COMMON), the address bit, 110, must be stable at least ISOns
prior to CE going high and must remain stable during the entire
read cycle. If 110 is allowed to change, damage to the ADS74A
output buffers may result.
READ TIMING-FULL CONTROL MODE
Parameter
too 1
tHO
tHL2
tssa
Access Time (from CE)
Data Valid after CE Low
Output Float Delay
CS to CE Setup
RIC toCE Setup
Ao to CE Setup
CS Valid After CE Low
RIC Higb After CE Low
Ao VaJid After CE low
tSRR
Figure 7 shows a complete timing diagram for the ADS74A
convert start operation. RIC should be low before both CE and
CS are asserted; if RIC is high, a read operation will momentarily
occur, Possibly resulting in system bus contention. Either CE or
CS may be used to initiate a conversion; however, use of CE is
recommended since it includes one less propagation delay than
CS and is the faster input. In Figure 7, CE is used to initiate
the conversion.
CE
tSAR
tHSR
tHRR
tHAR
-J~~
__
~~
Max
Units
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
100
ISO
0
ISO
SO
0
SO
outjtutto crossO.4V or 2.4V.
2 tHL is defined as
the time required for the data lines to'change O.5V when loaded with the
circuit of Figure 10.
+5V
00--1...,....----41~-.
J
AO ____
Typ
IIDD is measured with the load circuit of Figure 9 and defIned as the time required for an
DBN
R/C==~=±~~=========
Min
Symbol
DB.
~3k
o----t=-
1'OOPF
'OOpF
a. High-ZtoLogic 1
b. High-ZtoLogicO
Figure 9. Load Circuit for Access Time Test
___________ _
+5V
STS
DB' 1-080
--------~~'D=~~----
---------t- HIGH IMPEDANCE - - - - - - - - - Figure 7. Convert Start Timing
Once a conversion is started and the STS line goes high, convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers cannot be enabled during
conversion.
Figure 8 shows the timing for data read operations. During data
read operations, access time is measured from the point where
CE and RIC both are high (assl1Iiling CS is already low). If CS
is used to enable the device, access time is extended by lOOns.
CE
DB.
_
J'OPF
J'OPF
a. Logic 1 to High-Z
b. LogicOtoHigh-Z
Figure 10. Load Circuit for Output Float Delay Test
"STAND-ALONE" OPERATION
The AD574A can be used in a "stand-alone" mode, which is
useful in systems with dedicated input ports available and thus
not requiring full bus interface capability.
In this mode, CE and 1218 are wired high, CS and 110 are wired
low, and conversion is controlled by RIC. The three-state buffers
are enabled when RIC is high and a conversion starts when RIC
goes low. This allows two possible control signals - a high pulse
or a low pulse. Operation with a low pulse is shown in Figure
11. In this case, the outputs are forced into the highimpedance state in response to the falling edge of RIC and return
R~4J
RiC
~s
Ao
STS
DB11·DBO
D~~
0--0r~3k--"'l-"
IMPiiiSjCf-t===j:~~t.:d
Figure 8. Read Cycle Timing
DB11-DBO
1'~1r----------'\
~~I
-1
e:~~
----
~.
t:o. I------tc---j:-l"!-'H'
I)
HIGH-Z
¢
DATA VALID
I
Figure ". Low Pulse for Ric-Outputs Enabled After
Conversion
ANALOG-TO-DIGITAL CONVERTERS 3-45
II
to valid logic levels after the conversion cycle is completed. The
STS line goes high 600ns after RIC goes low and returns low
300ns after data is valid.
If conversion is initiated by a high pulse as shown in Figure 12,
the data lines are enabled during the time when RIC is high.
The falling edge of RIC statts the next conversion, and the data
lines return to three-state (and remain three-state) until the next
high pulse of RIC.
R/C-Ji~
1
STS
~RK
"Dsll--------L
I"DR'~
I
I-i I \tOR I
DB1,-DBO
_ __
11-'- -.. ----t·1
~ DATA ~
~VAI.ID._
II--'~
HIGH-l
Figure 12. High Pulse for RiC - Outputs Enabled While
High, Otherwise High-Z
RiC
STAND-ALONE MODE TIMING
Symbol
Parameter
tHRL
tos
tHDR
tIlL
tRS
tHRH
tOOR
Low RIC Pulse Width
Min
Typ
250
STS Delay from RIC
Data Valid After RIC Low
25
Output Float Delay
STS Delay After Data Valid 300
High RIC Pulse Width
300
Data Access Time
Max
Uaits
ns
600
150
1000
os
os
os
external three-state buffer (or other input port). The STS signal
can also be used to generate an interrupt upon completion of
conversion, if the system timing requirements are critical (bear
in mind that the maximum conversion time of the AD574A is
only 35 microseconds) and the processor has other tasks to
perform during the ADC conversion cycle. Another possible
time-out method is to assume that the ADC will take 35 microseconds to convert, and insert a sufficient number of "do-nothing"
instructions to ensure that 35 microseconds of processor time is consumed.
Once it is established that the conversion is finished, the data
can be read. In the case of an ADC of 8-bit resolution (or less),
a single data read operation is sufficient. In the case of converters
with more data bits than are available on the bus, a choice of
data formats is required, and multiple read operations are needed.
The AD574A includes internal logic to permit direct interface to
8-bit or 16-bit data buses, selected by connection of the 1218
input. In 16-bit bus applications (I2/8 high) the data lines (DBll
through DBO) may be connected to either the 12 most signifi,cant
or 12 least significant bits of the data bus. The remaining four
bits should be masked in software. The interface to an 8-bit
data bus (1218 low) is done in a left-justified format. The even
address (AO low) contains the 8MSBs (OBll through DB4).
The odd address (AO high) contains the 4LSBs (OB3 through
080) in the upper half of the byte, followed by four trailing
zeroes, thus eliminating bit masking instructions.
It is not possible to rearrange the AD574A data lines for rightjustified 8-bit bus interface.
ns
os
250
ns
XXXO (EVEN ADOR):
Usually the low pulse for RIC stand-alone mode will be used.
Figure 13 illustrates a typical stand-alone confirguration for
8086 type processors. The addition of the 74F/S374 latches
improves bus access/release times and helps minimize digital
feedthrough to the analog portion of the converter.
Ro
TO
A"AS
DATA
BUS
ALE
....
WR
XXX1(ODOADDRI:
I
D7
I
DB11
(MSa) •
I I
DB3
DO
0810
DB2
DB9
DBI
DB.
DBO
(LSBI
I I
DB7
I I
0
DB.
DB5
0
SPECIFIC PROCESSOR INTERFACE EXAMPLES
Z-8O System Interface
The AD574A may be interfaced to the Z-80 processor in an 110
or memory mapped configuration. Figure 15 illustrates an 110
mapped configuration. The Z-BO uses address lines AO-A7 to
decode the 110 port address .
r----t :>0----1 RIC
DATA
BUS
iffi
....r-)o__-t CE
L-.......
Figure 13. 8086Stand-AloneConfiguration
AD574A
GENERAL AID CONVERTER INTERFACE
CONSIDERATIONS
A typical AID converter interface routine involves several operations. First, a write to the ADC address initiates a conversion.
The processor must then wait for the conversion cycle to complete,
since most ADCa take longer than one instruction cycle to complete
a conversion. Valid data can, of course, only be read after the
conversion is complete. The AD574A provides an output signal
(STS) which indicates when a conversion is in progress. This
sipal can be polled by the processor by reading it through an
3-46 ANALOG-TO-DIGITAL CONVERTERS
0
Figure 14. AD574ADataFormatforB-BitBus
TD
INTERFACING THE ADS74A TO MICROPROCESSORS
The control logic of the AD574A makes direct connection to
most microprocessor system buses possible. While it is impossible
to describe the details of the interface connections for every
microprocessor type, several representative examples will be
described here.
DB4
A1-A7
zso
--1 AD
AO \ -_ _ _ _ _ _
D7
\------t"""::-I
DO
\------1
DB8-DBl1
DBO-DB3
1218
Figure 15. Z80-AD574Alnterface
I
I
AD574A
An interesting feature of the Z-80 is that during 1/0 operations
a single wait state is automatically inserted, allowing the ADS74A
to be used with Z-80 processors having clock speeds up to 4MHz.
For applications faster than 4MHz use the wait state generator
in Figure 16. In a memory mapped configuration the ADS74A
may be interfaced to Z-80 processors with clock speeds of up to
2.SMHz.
VlOGIC
12/8
RIC
liD
Mlili
WAIT
+5V
CE
WR
CS
8086
AD574A
MREO
D
ADDRESS
S
Q
A16-A19
D
7474
.,.
•
A.
ALE
7474
BHE
e
Q
Q
ADO-AD1S
+5V
00-0'1
Figure 16. WaitStateGenerator
IBM PC Interface
The ADS74A appears in Figure 17 interfaced to the 4MHz 8088
processor of an IBM PC. Since the device resides in 1/0 space,
its address is decoded from only the lower ten address lines and
must be gated with AEN (active low) to mask out internal DMA
cycles which use the same 110 address space. This active low
signal is applied to CS. lOR and lOW are used to initiate the
conversion and read, and are gated together to drive the chip
enable, CEo Because the data bus width is limited to 8 bits, the
ADS74A data resides in two adjacent addresses selected by AO.
07
08-011
8
DO
IBMPe
CARD SLOT
t--------<--I T
OE
DEN
8286
OR
8287
Figure 18. 8086- AD574A with Buffered Bus Interface
For clock speeds greater than 4MHz wait state insertion similar
to Figure 16 is recommended to ensure sufficient CE and RIC
pulse duration.
The ADS74A can also be interfaced in a stand-alone mode (see
Figure 13). A low-going pulse derived from the 8086's WR
signal logically ORed with a low address decode starts the conversion. At the end of the conversion, STS clocks the data into
the three-state latches.
OBD-OB3
RIC
lOW
c.
AD
AD
lOR
DTIR
AD574A
cs
68000 Interface
The ADS74, when configured in the stand-alone mode, will
easily interface to the 4MHz version of the 68000 microprocessor.
The 68000 RIW signal combined with a low address decode
initiates conversion. The UDS or LDS signal, with the decoded
address, generates the DTACK input to the processor, latching
in the ADS74A's data. Figure 19 illustrates this configuration.
10RQt---~
12t8
=
Figure 17. IBMPC-AD574Alnterface
68000
ww~----------~~~
Note: Due to the large number of of optians that may be installed
in the PC, the 110 bus loading should be limited to one Schottky
TTL load. Therefore, a bufferldriver should be used when
interfacing more than two ADS74As to the 110 bus.
8086 Interface
The data mode select pin (12/8) of the ADS74A should be connected
to VLOG1C to provide a 12-bit data output. To prevent possible
bus contention, a demultiplexed and buffered address/data bus
is recommended. In the cases where the 8-bit short conversion
cycle is not used, AO should be tied to digital common. Figure
18 shows a typical 8086 configuration.
DAT.
BUS
Figure 19. 6BOOO-AD574Alnterface
ANALOG-TO-DIGITAL CONVERTERS 3-47
3-48 ANALOG-TO-DIGITAL CONVERTERS
1IIIIIIII ANALOG
WDEVICES
FEATURES
Complete Serial Output 10-Bit AID Converter with
Reference. Clock and Comparator
30 ....s Conversion
No Missing Codes Over Temperature
Operates on +5Vand -12V to -15V Supplies
Low Cost Monolithic Construction
Internal or External Clock
Triggered or Continuous Conversions
Short Cycle Capability
GENERAL DESCRIPTION
The ADS7S is a complete IO-bit successive-approximation analogto-digital converter consisting of a DAC, voltage reference,
clock, comparator, successive approximation register (SAR) and
serial interface on a single chip. No additional components are
required to perform a full-accuracy IO-bit conversion in 30j.Ul.
The ADS7S incorporates the most advanced integrated circuit
design and processing technology available. The successive
approximation function is implemented with I2L (integrated
injection logic). Laser trimming of the SiCr thin-fllm resistor
ladder network at the wafer stage insures high accuracy, which
is maintained with a temperature-compensated sub-surface zener
reference.
Operating on supplies of + SV and -12V to -ISV, the ADS7S
will accept full scale analog inputs of OV to + IOV, OV to + 20V,
- SV to + SV or -lOY to + lOY. The rising edge of a positive
pulse on the CONVERT line initiates the conversion cycle.
Eleven pulses will appear at the CLOCK OUTPUT pin with
data valid on the falling edges of the clock waveform. The data
is presented serially beginning with the MSB which is valid on
the falling edge of the second clock pulse. The part may be
programmed to perform 8Cbit conversions or short cycled to 2-,
4-, 6- or 8-bit word lengths. EOC indicates that conversion is
complete. The ADS7S may be synchronized to an external clock
if desired.
Complete 1O-Bit AID Converter
with Serial Output
AD575* I
AD575 FUNCTIONAL BLOCK DIAGRAM
v-
DIGITAL
COMMON
CONVERT
EXTERNAL
CLOCK
Two package types are available. All versions are offered in a
14-pin hermetically-sealed ceramic DIP. The ADS75J and
AD57SK are also available in a 14-pin plastic DIP.
PRODUCT HIGHLIGHTS
1. The AD575 is a complete lO-bit AJD converter. No external
active components or control signals are required to perform
a conversion.
2. The serial output of the ADS75 allows a wide range of microprocessor interfacing and data transmission possibilities.
3. The device offers true 100bit relative accuracy and exhibits
no missing codes over its entire operating temperature range.
4. The AD575 adapts to unipolar or bipolar analog inputs by
grounding or opening a single pin.
5. Performance is guaranteed with + 5V and - 12V or - 15V
supplies.
6. The AD575 can be synchronized to an external clock.
7. Conversions can be initiated externally or internally.
8. The AD575 can be short-cycled to 8 bits by pin
programming.
9. The Short Cycle and Terminate feature allows the user to
program conversions of 2, 4, 6 or 8 bits.
The ADS7S is available in two versions for the 0 to + 70°C
temperature range, the AD57SJ and AD575K. The ADS75S
guilrantees ± I LSB relative accuracy and no missing codes from
- WC to + 125°C.
*Proteeted by u.s. Patent Nos. 3,1140,760; 4,400,689;. and 4,400,690.
ANALOG-TO-DIGITAL CONVERTERS 3-49
•
SPECIFICATIONS (@2ft,V+= +5Y, V- = -l2Vor -l5Y,lIIlassollawisenollld)
AD575J
Min
RESOLUTION
For Which No Missing Codes
is Guaranteed
Tmin toT....
Typ
AD5,15S
AD575K
Max
10
Min
Typ
Max
10
10
9
Min
Typ
Max
10
10
Units
Bits
Bits
UNIPOLAR OFFSET
TmintoTmax
±2
±2
±1
±I
±2
±2
LSB
LSB
BIPOLAR ZERO
Tmin to Tmax
±2
±2
±I
±I
±2
±2
LSB
LSB
±2
±2
LSB
GAIN ERROR'
±2
GAINDRlFT'
T min to + 2S'C
+ 2S'C to T max
±2
±4
±I
±2
±5
±5
LSB
LSB
RELATIVE ACCURACy 3
Tmin to Tmax
±I
±1
±112
±1/2
±I
±I
LSB
LSB
POWER SUPPLY REJECTION
Positive Supply:
+4.SV:sV+:s+S.SV
Negative Supply:
-IS.7SV:sV -:s -14.2SV
-12.6V:sV -:s -11.4V
±2
±I
±2
LSB
±2
±2
±I
±I
±2
±2
LSB
LSB
14
kO
ANALOG INPUT IMPEDANCE
Pin I,Pin2
6
ANALOG INPUT RANGES
Unipolar
14
6
OtolO
01020
-5to +S
-1010 +10
Bipolar
OUTPUT CODING
Unipolar
Bipolar
10
10
14
Oto 10
Ot020
-S to +5
-lOto +10
NEGATIVE TRUE BINARY
NEGATIVE TRUE OFFSET
BINARY
LOGIC OUTPUTS (Tmin to T."..)
VOL @ IS'NK = 3.2mA
VOH @ IsouRCE = O.SrnA
0
2.4
0
2.4
LOGIC INPUTS (Tmin to T ."..)
IINH@VIN =5Vs
IINL@VIN=OVs
VINH
VINL
-800
2.0
0
CONVERSION TIME (Tmin to T."..)
Internal Clock
External Clock
10
25
POWER SUPPLY
V+
V-
+4.5
-11.4
0.4
5.0
0.4
5.0
+50
OPERATING CURRENT
V+
V-
5.S
0.8
IS
9
10
25
+5.5
-15.75
+4.5
-11.4
5.5
0.8
20
IS
9
+50
+5.5
-15.75
+4.5
-11.4
'Gain Error is specified with. ISO resistor in series with the IOV inpot (Pins land 2 tied together) or a
300 resistor in series with the 20V input (Pin I with Pin 2 tied to analog common).
Gain Error is guaranteed trimmable to zero (see text).
2The gain drift is calculated fromgain measurements at the extremes of the temperature range under consideration.
3ReJative Accuracy, also referred to as Integral Linearity, is defmed as the deviation oCthe code transition points
from the ideal transferpoints on a straight line from zero to full-scale. It is also a measure of the error which
remains when offset and full scale errors are trimmed to zero in an application.
'Measured atfull scale.
'Tbese specifications apply to theCONV, XCL, and SCATinpots. CU is hardwired toDGND or + Vs in most applications.
TypicallyI'NH= + 3S0,..Aand IINL = 120,..A for the CU input.
Specifications shown in boldface are tested on all production units at fmal electrical test. Results from those tests are used
to ca1cuIate outgoing quality levela. AU min and max specifications are guaranteed, although only those shown in boldfaco
are tested on all production units.
3-50 ANALOG-TO-OIGITAL CONVERTERS
0.4
S.O
-SOO
2.0
0
10
2S
NOTES
Specifications subject to change without notice.
0
2.4
30
25
15
V
V
V
V
NEGATIVE TRUE BINARY
NEGATIVE TRUE OFFSET
BINARY
+50
-800
2.0
0
30
25
15
10
01010
Ot020
-5to +S
-1010+10
NEGATIVE TRUE BINARY
NEGATIVE TRUE OFFSET
BINARY
20
6
V
V
ILA
IJ.A
20
15
9
5.5
0.8
V
V
30
ILS
ILS
+5.5
-15.75
V
V
25
15
rnA
rnA
AD575
ABSOLUTE MAXIMUM RATINGS
. . Oto +7V
V + to Digital Common . . . . . . .
.0 to -16.5V
V - to Digital Common . . . . . . .
. . . . . ±lV
Analog Common to Digital Common
(V -) -0.3V to +22V
Analog Inputs ..
o to V+
Control Inputs
. . . . . . . . 800mW
Power Dissipation
NOTE
All pins must be kept more positive than (V -) -O.3V.
AD575 ORDERING GUIDE
Model
Package
Options·
Temperature
Range-OC
Relative
Accuracy
AD575JN
A057SKN
A0575JO
AD575KO
AD575S0
N·14
N·14
0·14
0-14
0-14
Oto +70
Oto +70
010 + 70
Oto +70
-5510+125
±ILSBmax
± 112LSBmax
±ILSBmax
± 112LSBmax
±ILSBmax
*See Section 14 for package outline information.
FUNCTIONAL DESCRIPTION
A block diagram of the AD575 is shown in Figure 1. A conversion
is initiated by a positive pulse on the CONVERT line. EOC
goes high within l50ns indicating that a conversion has started.
The internal 10-bit current-output DAC is sequenced by the
successive approximation register (SAR) from most significant
bit to least significant bit to provide an output current which
accurately balances the input signal current through the 10kfl
input resistor(s). The comparator determines whether the addition
of each successively-weighted bit current causes the DAC current
be higher or lower than the input current. If the sum is less
the bit is left on (DO set low). If the sum is more, the bit is
turned off (DO set high). The result of each bit decision is
passed to DO on the rising edge of CO.
to
•
PIN 1
IDENTIAER
BIPOLAR OFFSET
DIGITAL
COMMON
AD575
v+
DATA OUTPUT
CLOCK OUTPUT
EXTERNAL
CLOCK
~
AND TERMINATE
Figure 2. AD575 Pin Connections
v-
DIGITAL
COMMON
CONVERT
EXTERNAL
CLOCK
SHOiffCY[E
AND TERMINATE
After all bits have been tested, the DAC output current will
match the input signal current to within 0.05% (1I2LSB). EOC
returns low after the fmal bit decision to indicate that the AD575
has been reset and is ready to perform a new conversion. The
output data stream can be synchronized to an external clock
using the XCL input and short cycled to any desired word
length using the SCAT line.
The AD575 contains all the active components reqnired to
perform a complete AID conversion. Thus, for many applications,
all that is necessary is to connect the power supplies ( + 5V and
-12V or -15V), and the analog input. The pinout is shown in
Figure 2.
Figure 1. AD575 Functional Block Diagram
ANALOG-TO-DIGITAL CONVERTERS 3-51
ANALOG INPUT CONNECTIONS
The AD575 can be configured for unipolar or bipolar operation
on 10V span or 20V span input signals. The appropriate input
range is selected by connecting pins 2 and 14 according to the
table of Figure 3.
The AD575's low offset and gain errors (shown in the Specifications) are adequate for most applications. For these cases, a
fixed gain resistor (R2 in Figure 3) is the only external component,
in addition to any power supply decoupJing that may be required.
Pins 3 and 13 should be connected directly together.
Figure 3 shows a trimming circuit that can be used to adjust the
offset to zero, using the appropriate value of the R1 potentiometer
as shown in the table. If gain trim is required, R2 should also
be replaced by the appropriate potentiometer as shown in the
table.
BIPOLAR CONNECTION
If the bipolar offset control (pin 14) is left open, the AD575 will
accept bipolar input voltages with OV as the nominal bipolar
zero point. The input voltage corresponding to the low side
transition of the mid-scale code (0111111111) is -1/2LSB (- 5mV
for 10V spans and -lOmV for 20V spans). The nominal location
of the code transitions are therefore offset by 1I2LSB as shown
in Figure 4. This offset may be adjusted using the trim scheme
shown in Figure 3 with a 1.2kn resistor in place of the 1kO
resistor shown.
OUTPUT
CODE
r-I
0111111101
0111111110
0111111111
ANALOG INPUT RANGE
OVTO +10V
OVTO +20V
-5VTO +5V
-10VTO +10V
CONNECTIONS
PIN2
PIN 14
COMPONENTS
Rl (OFFSETI
R2(GAINI
PIN 1
PIN3
PiN 1
PiN3
10U
2011
1011
20n
PIN13
PINn
OPEN
OPEN
15.5:1 FIXED ORSO!l POT
3011 FIXED OR 10011 POT
1000000000
1000000001
I
1sn FIXED OR 50H POT
---'
30U FIXED OR 100U POT
-3
LSB
-2 -1
LSB LSB
1
2
3
LSB LSB LSB
R2
GAIN~
+5V
Figure 4. A0575 Transfer Characteristic (Bipolar
Operation)
I
I
SEE
TABLE
lk
AD575
c~~~~'N
13
2k
-15V
The gain error should be adjusted after any offset adjustment.
An input voltage of full scale minus 1 1I2LSBs is applied (4. 985V
for -5V to +5V range, 9.971V for -lOY to + 10V range) and
R2 is adjusted until the low-side transition of the full scale code
(0000000000) occurs.
The bipolar offset control input is not directly TTL compatible,
but a TTL interface for logic control can be constructed as
shown in Figure 5.
Figure 3. A0575 Input Circuit Showing Offset and Gain
Adjustment
UNIPOLAR MODE OPERATION
In unipolar mode, the nominal location of the low side transition
of the first code (1111111110) occurs at an input voltage of
+ lLSB (lOmV for the lOY span, 20mV for the 20V span). The
offset error of the AD575 can be trimmed out, if required, by
applying an input voltage of + 1LSB to the analog input and
adjusting Rl until the low side transition of the first code
occurs.
USE
ACTIVE
PUll·UP
GATE
J jf~
30k
If the Gain Error needs to be trimmed, the gain resistor should
be replaced with a potentiometer according to Figure 3. The
nominal location of the low side transition of the full scale code
(0000000000) in unipolar mode is full scale minus 1LSB (9.99V
for 10V span, 19.98V for 20V span). Once the offset has been
adjusted, the full scale range can be set by adjusting the gain
potentiometer .
3-52 ANALOG-TO-OIGITAL CONVERTERS
-15V
GATE OUTPUT = 1
GATE OUTPUT = 0
UNIPOLAR INPUT RANGE
BIPOLAR INPUT RANGE
Figure 5. Bipolar Offset Controlled by Logic Gate
AD575
CONTROL AND TIMING OF THE ADS'S
The ADS'S has a flexible control architecture which suppons
several operating modes. It can provide its own clock or it can
be synchronized to an external clock. Conversions can be initiated
externally, or the pan can perform continuous conversions yielding
a stream of output data. In addition, the ADS7S can be shon-cycled
to any of several convenient data word lengths to tailor the
output to the specific input requirements of the system. Figure
6 shows the control logic diagram of the ADS7S. The four inputs
which control the operation of the ADS7S are CONY (conven),
CLI (clock inhibit), XCL (external clock), and SCAT (shon
cycle and terminate). Three outputs are provided: DO (Data
Out), CO (Clock Out), and EOC (End of Conversion).
EXTERNALLY INITIATED CONVERSIONS
Figure 7 is the timing diagram which illustrates the operation of
the ADS7S with an externaJly applied conven signal. Conversions
are initiated by a positive-going pulse applied to the CONY
(conven) input. This pulse should be at least 2S0ns wide and
should return low before EOC returns low to prevent the initiation
of a second conversion. If the internal clock is used, the clock
will stan on the rising edge of the conven stan pulse. If an
external clock is used, the falling edge of the clock must occur
no earlier than 900ns following the rising edge of the conven command.
INTERNAL CLOCK MODE
The ADS7S can be configured for internal clock operation by
tying CLI and XCL to +SV. CO (clock output) provides the
necessary synchronizing information in this mode. Data is transferred to DO on the rising clock edge and is stable on the falling
edge. The duty cycle of the CO waveform in this mode will be
in the range of 30% to 7()oA..
EXTERNAL CLOCK MODE
When CLI is connected to digital common, an externa1 clock
can be applied to XCL. The external clock should have a maximum
frequency of 4S0kHz with a minimum of 900ns in the high or
low phase. Arbitrarily slow clocks may be used as long as these
Figure 6. AD575 Control Logic Diagram
minimum high and low periods are observed. Conversion time
will increase as clock frequency decreases. Each data bit will be
stable within I sOns of the rising edge of the associated external
clock pulse and will remain stable until the rising edge of the
subsequent clock pulse. Data is guaranteed to be stable on the
falling edge of the clock pulse.
The state of the DO output during the first clock period is
undefmed but it is stable until the rising edge of the second
clock period. The MSB appears at DO during the second clock
period. The subsequent data bits are then clocked out until the
Nth bit or LSB is clocked out on the (N + I)th clock pulse. EOC
returns low within 1SOns of the rising edge of this final clock
pulse. In internal clock mode, the output clock pulse associated
with the LSB is shoner than the others but the LSB is guaranteed
to be stable on the falling edge of this pulse. The LSB will
remain stable until a new conversion is initiated. The value of N
will be 10 unless the conversion has been shon cycled (see "shon
cycle and terminate" text).
~~---~----I-----~--------~·I
CONY
}
\
19{
~~~
~j~
~-j
~~~
~
XCL
~
co
DO
~________~
MSB
X,,__
~a<
DB2
_ _...
LSB
Figure 7. Externallv Initiated Conversions
ANALOG-TO-DIGITAL CONVERTERS 3-53
I~----------------~----------------~
XCL
J\-I\-
co
X
__
LS_a.
___
, _J
UNDEFINED
~b
DB9
X
LSBN
Figure 8. Continuous Conversion Mode (CONV. Held High)
CONTINUOUS CONVERSIONS
Figure 8 is the timing diagram associated with the continuous
conversion mode of operation. If CONV is high when EOC goes
low, another conversion will begin immediately. EOC will be set
(high) following the falling edge of the (N + l)st CO pulse and
conversion commences with the rising edge of the next CO
pulse. The (N + I)st CO pulse is not shortened in this mode. If
CONVERT is held high the AD575 will put out a continuous
stream of conversions, punctuated by EOC which will mark the
last clock pulse of a conversion. EOC will remain low until the
falling edge of CO, the output clock, in this mode. Therefore,
the rising edge of EOC may be used to signal that conversion is
C9mplete and that data is transferred. This sequence is useful
for initiating parallel dumps from a serially loaded shift register.
SHORT CYCLE AND TERMINATE
For normal 100bit operation, the Short Cycle and Terminate
(SCAT) line should be tied high. If 8-bit conversions are required,
SCAT should be tied low. In this mode, EOC will go low after
the rising edge of the ninth clock pulse to indicate that the
eighth and final data bit is valid. This mode is useful when
parallel loads to 8-bit data buses are desired since it avoids the
complication of suppressing the 9th and 10th data bits.
Conversions of 2,4,6 or 8 bits can be perfOrtned by pulling
SCAT low during the negative clock phase prior to the positive
clock associated with the desired LSB. Figure 9 illustrates the
timing associated with this mode of operation. For example, to
terminate the conversion after six data bits, SCAT should be
driven low during the negative clock phase following the sixth
clock pulse. EOC will then go low following the rising edge of
the seventh clock pulse to indicate that the sixth and fmal data
bit is valid.
This terminate feature can also be used to program conversions
of 1,3,5,7 or 9 bits. However, the conversion immediately
following a conversion of an odd number of data bits will be
spurious. All subsequent conversions will be normal until the
conversion following another odd data word length conversion.
The negative edge of the SCAT signal should always occur
during the negative phase of a clock cycle and it should be held
low for a minimum of 900ns. SCAT may be held low into the
next conversion but it must be restored high at least one clock
cycle prior to being used to terminate a conversion. If SCAT is
not restored high prior to the eighth clock pulse, EOC will go
low and an 8-bit short cycle will occur. Care should be taken
not to pulse SCAT from high to low between conversions (when
EOC is low). This would initiate a terminate sequence which
will execute on the rising edge of the fl1"St clock pulse following
the next Convert command.
CONTINUOUS
CONVERSION
----,~
\
\r
I
~--------------~ff~----~
/
r-
\ \ ._ _,,/
__
,--
~
J~I--.r-r-l
XCL
co
X
_ _ _J
LSBN_,
X
UNDEFINED
~
X,,__ _x::::Jtx___
M..;,S_B
Figure 9. Short Cycle and Terminate Operation
3-54 ANALOG-TO-DIGITAL CONVERTERS
...JX,_....;LS..;,B__
AD575
Parameter
Symbol
I Min
Typ Mas
IUnils
EXTERNALLY.INITIATEDCONVERSIONS
Convert Pulse Width
Convert to EOC Delay
CO LSBClock Pulse Width
XCLtoEOCReset
l' CO to -Jr EOC Reset Delay
tcs
300
150
toes
tWL
tosx
tDS!
400
50
20
150
150
tDCL
tOCH
50
50
150
1000
Ice
10
20
-100
30
+100
25
30
30
900
150
160
os
os
ns
ns
ns
..IL.
CONVERT
CONTINUOUS CONVERSIONS
of- XCL to -J. EOC Reset Delay
-Jr XCL to .,. EOC Delay
INTERNAL CLOCK TIMING
Conversion Time
CO to DO Output Delay
tDDI
-v.
EXTERNAL CLOCK TIMING
Conversion Time
~~
BIPOLAR OFFSET
GAIN (REF IN)
"c
~
BIT 3
REF OUT
1llif--..rftHlttft-i
SERIAL OUT
SERiA[OijT
BIT1
21
CONVERT START
EOC
CLOCK IN
CLOCKAOJ
PRODUCT HIGHUGHTS
1. The AD578 is a complete 12-bit AID converter. No external
components are required to perform a conversion.
2. The fast conversion rate of the AD578 makes it an excellent
choice for high speed data acquisition and digital signal processing applications.
3. The internal buried zener reference is laser trimmed to IO.OOV
± 1.0% and ± 15ppmrc typical T.C. The reference is available
for external use and can provide up to lmA.
4. The scaling resistors are included on the monolithic DAC for
exceptional thermal tracking.
5. The component count is minimized, resulting in low bond
wire and chip count and high MTBF.
6. Shon cycle and external clock capabilities are provided for
applications· requiring faster conversion speeds and/or lower
resolutions.
7. The integrated package construction provides high quality
and reliability with small size and weight.
The AD578 is available with either the polymer seal (N) for use
in benign environmental applications or hermetic solderseal (D) for more harsh or rigorous surroundings. Both are
contained in a 32-pin side-brazed, ceramic DIP.
The AD578S, T are available processed to MIL-STD-883 Level
B, Method 5008.
ANALOG-TO-OIGITAL CONVERTERS 3-57
II
SPECIFICATIONS
(typical @ + 25"1:, ± 15Y and + 5Y IIIlass othelWise nolld)
Model
AD578J
AD578K
AD578L
AD578SD'
RESOLUTION
12 Bits
*
*
*
±S.OV, ±IOV
Oto +IOV,Oto +20V
*
*
Sill
*
*
*
ANALOG INPUTS
Voltage Ranges
Bipolar
Unipolar
Input Impedance
Oto+IOV,±SV
± IOV,Oto +20V
10ill
*
*
DIGITAL INPUTS
Convert Command2
Clock Input
ILSTTLLoad
ILSTTLLoad
*
TRANSFER CHARACTERISTICS
Gain Error'''
Unipolar Offset'
Bipolar Error',s
Linearity Error, 2S·C
T min to T
±O.I%FSR, ±0.2S%FSRmax
±O.I%FSR, ±0.2S%FSRmax
±O.I%FSR, ±0.2S%FSRmax
±1I2LSBmax
±3/4LSB
*
*
*
*
IIW[
AD578TD'
*
*
*
*
*
*
±3/4LSBmax
±3/4LSBmax
± SOppmI"C max
± 30ppm/"C max
± I SppmI"C max
± IOppm/"Cmax
DIFFERENTIAL LINEARITY ERROR
(Minimum resolution for which no
missing codes are guaranteed)
+2S"C
TmintoTmu
POWER SUPPLY SENSITIVITY
+ISV ±Io%
-ISV ±Io%
+SV ±Io%
TEMPERATURE COEFFICIENTS
Gain
Unipolar Offset
Bipolar Offset
12 Bits
12 Bits
O.OOS%I%.1Vsmax
O.OOS%I%.1Vsmax
O.OOS%I%.1Vsmax
*
*
± ISppmI"C typ
± 3Oppml"C max
± 3ppmI"C typ
± IOppmI"C max
± 8ppmI"C typ
± 2OppmI"C max
± 2ppmI"C typ
*
*
*
*
*
*
*
*
4.S.,..
3.,.s
6.0.,..
Differential Linearity
CONVERSION TIME6,7,8(max)
6.0.,.s
PARALLEL OUTPUTS
Unipolar Code
Bipolar Code
Output Drive
Binary
Offset Binaryrrwo's Complement
2LSTTL Loads
SERIAL OUTPUTS (NRZ FORMAT)
Unipolar Code
Bipolar Code
Output Drive
Binary/Complementary Binary
Offset Binary/Comp. Offset Binary
2LSTTL Loads
END OF CONVERSION (EOC)
Output Drive
8LSTTL Loads
INTERNALCLOCK8
Output Drive
2LSTTL Loads
INTERNAL REFERENCE
Voltase
Drift
External Current
10.000 ± lOOmV
± 12ppml"€, ± 2Oppml"C max
±lmAmax
*
*
*
POWER SUPPLY REQUIREMENTS'
Ranse for Rated Accuracy
Supply Current + ISV
-ISV
+SV
Power Dissipation
4.75 toS.2Sand ± 13.5 to ± 16.5
3mA typ, 8mA max
22mAtyp,3SmAmax
lOOmA typ, 140mA maX
87SmWtyp
*
TEMPERATURE RANGE
Operating
Storage
Oto +70"c
-SS"Cto + lSO"C
*
*
± 2SppmI"C max
± 20ppmI"C max
*
4.5.,..
*
*
*
*
*
Logic" 1" During Conversion
NOTES
I Available to MIL-STD-883. Level B. See AD! Military Products Databook foe
detail specifications.
'Positive pulse 200ns wide (min)leadingedge (Oto I) resets outputs. Trailing edge
initiates conversion.
"ith SOO. 1% fmcd resistor in place ofgain adjust potentiometer.
4Adjustable to zero.
'With SOIl, 1 % resistor berweeo Ref Out and Bipolar Off.., (Pins 24 & 26).
3-58 ANALOG-TO-DIGITAL CONVERTERS
*
*
*
- SS·C to + 12S·C
-6S"Cto + lS0"C
~yenion time is defmcdas the time between thc falling edge of
convert start and tbe faJlina edge ofthe EOC.
7Eacbgrade isspecifiedat theconvers.ion speed shown.
8Extemally adjustable by a resistor or capacitor (see Figure 7).
'For "z" models order AD578ZJ, ZK, ZL (± 11.6V ± 16.5V).
*SpeciflCations same as ADS78J.
Speciflcations subiect to change without notice.
'0
- SS"C to + 12S·C
-6S"Cto + lSO"C
THEORY OF OPERATION
......
~200ns. min
CONVER:]l
START
200n5_1 ~
CLOCK
ANALOGGND
EOC
t--'W++"2'----'
L.__
i
I
External Buffer Amplifier - In applications where the AD578 is
to be driven from high impedance sources or directly from an
analog multiplexer a fast slewing, wideband op amp like the
AD711 should be used.
VoD
GND
Vss
+5V 1"laV
16
ANALOG INPUT
O*10V
31
~15V
32
27
__ 3_____
..JI
(OPTIONAL)
74LS244
lOW BYTE
ADDRESS
(ACTIVE lOW/
...
,402
Figure 8. AD578-8085A Interface Connections
AD578
Figure 7. Input Buffer
MICROPROCESSOR INTERFACING
The 3j.1.S conversion times of the AD578 suggests several different
methods of interface to microprocessors. In systems where the
AD578 is used for high sampling rates on a single signal which
is to be digitally processed, CPU-controlled conversion may be
inefficient due to the slow cycle times of most microprocessors.
It is generally preferable to perform conversions independently,
inserting the resultant digital data directly into memory. This
can be done using direct memory access (DMA) which is totally
transparent to the CPU. Interface to user-designed DMA hardware
Clearly, 12 bits of data must be broken up for interface to an 8bit wide data bus. There are two possible formats: right-justified
and left-justified. In a right-justified system, the least-significant
8 bits occupy one byte and the four MSBs reside in the low
nybble of another byte. This format is useful when the data
from the ADC is being treated as a binary number between 0
and 4095. The left-justified format supplies the eight most-siguificant bits in one byte and the 4LSBs in the high nybble of
another byte. The data now represents the fractional binary
number relating the analog signal to the full-scale voltage. An
advantage to this organization is that the most-significant eight
bits can be read by the processor as a coarse indication of the
true signal value. The full 12-bit word can then be read only
when all 12 bits are needed. This allows faster and more efficient
control of a process.
Figure 8 shows a typical connection to an 8085-type bus, using
left-justified data format for unipolar inputs. Status polling is
ANALOG-TO-DIGITAL CONVERTERS 3-61
II
optional, and can be read simultaneously with the 4LSBs. If it
is desired to right-justify the data, pins 1 through 12 of the
AD578 should be reversed, as well as the connections to the
data bus and high and low byte address signals.
When dealing with bipolar inputs (± 5V, ± lOY ranges), using
the MSB directly yields an offset binary-coded output. If two's
complement coding is desired, it can be produced by substituting
MSB (pin 13) for the MSB. This facilitates arithmetic operations
which are subsequently performed on the ADC output data.
SAMPLED DATA SYSTEMS
The conversion speed of the AD578 allows accurate digitization
of high frequency signals and high throughput rates in multichannel data acquisition systems. The AD578LD, for example,
is capable of a full accuracy conversion in 3....s. In order to benefit
from this high speed, a fast sample-hold amplifrer (SHA) such
as the HTC-0300 is required. This SHA has an acquisition time
to 0.01% of approximately 300ns, so that a complete sample-conven-acquire cycle can be accomplished in approximately 4f.LS.
This means a sample rate of 250kHz can be realized, allowing a
signal with no frequency components above 125kHz to be sampled
with no loss of infonnation. Note that the EOC signal from the
AD578 places the SHA in the hold mode in advance of the
actual stan of the conversion cycle, and releases the SHA from
the HOLD mode only after completion of the conversion. After
allowing at least 300ns for the SHA to acquire the next analog
value, the convener can again be staned.
AD578 ORDERING GUIDE·
AD578JNOD)
AD578KN(KD)
AD578LN(LD)
AD578SD
AD578SD/883B
AD578TD/883B
Conversion
Speed
Temperature
Range
Package Option l
6.0.,.s
4.5",8
3.0",s
6.0",8
6.0",8
4.5",8
Oto + 70°C
Oto + 70°C
Oto + 70°C
....: 55°C to + 125°C
- 55°C to + 125°C
- 55°C to + 125°C
Solder Seal (DH-32B)
Solder Seal (DH-32B)
Solder Seal (DH-32B)
Solder Seal (DH-32B)
Solder Seal (DH-32B)
Solder Seal (DH-32B)
*For ± 12V operation "Z" version order: ADS78ZJN, •..
1 See Section 14 for package outline information.
3-62 ANALOG-TO-DIGITAL CONVERTERS
Very Fast, Complete
10-Bit AID Converter
ANALOG
WDEVICES
11IIIIIIII
AD579 I
AD579 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Performance
Complete 10-Bit AID Converter with Reference and Clock
Fast Successive Approximation Conversion: 1.8J.1s
Buried Zener Reference for Long Term Stability and Low
Gain T.C.: ±40ppmtC max
Max Nonlinearity: <±0.048%
Low Power: 775mW
MIL-STD-883B Processing Available
Versatility
Positive-True Parallel or Serial Logic Outputs
Short Cycle Capability
Precision +10V Reference for External Applications
Adjustable Internal Clock
"z" Models for ±12V Supplies
PRODUCT DESCRIPTION
The AD579 is a high speed low cost lO-bit successive approximation analog-to-digital converter that includes an internal
clock, reference and comparator. Its hybrid IC design utilizes MSI digital and linear monolithic chips in conjunction
with a lO-bit monolithic DAC to provide superior performance and versatility with IC size, price and reliability.
Important performance characteristics of the AD579 include
a maximum linearity error at +25°C of±O.048%, maximum
gain temperature coefficient of ±40ppm/oC, typical power
dissipation of 775mW and maximum conversion time of
1.8J.1s.
The fast conversion speeds of 1.8J.1s (K and T grades) and
2.2J,1S (J grade) make the AD579 an excellent choice in a
variety of applications where system throughput rates from
454kHz to 555kHz are required. In addition, it may be short
cycled to obtain faster conversion speeds at lower resolutions.
The design of the AD579 includes scaling resistors that provide
analog input signal ranges of ±5V, ±lOV, 0 to +lOV or 0 to
+20V. Adding flexibility and value is the +lOV precision reference which can be used for external applications.
TEST POINT
1
TEST POINT
2
A0579
-15V
ANALOOGND
ZEROADJ
20V SPAN INPUT
'"...w
10V SPAN INPUT
... ",
qi~
BIPOLAR OFFSET
-8
GAIN (REF INI
oz
:!
0
REF OUT
SERIAL OUT
81T3
SERIAL OUT
21
CONVERT STAAT
EOC
32-PINDIP
PRODUCT HIGHLIGHTS
1. The AD579 is a complete 10-bit AID converter. No external
components are required to perform a conversion.
2. The fast conversion rate of the AD579 makes it an excellent
choice for high speed data acquisition on systems requiring
high throughput rate.
3. The internal buried Zener reference is laser trimmed to
lO.OOV ±O.l % and ±15ppm/C typ T.C. The reference is
available externally and can provide up to ImA.
4. The scaling resistors are included on the monolithic DAC
for exceptional thermal tracking.
5. Short cycle and external clock capabilities are provided for
applications requiring faster conversion speeds and/or
lower resolutions.
6. The integrated package construction provides high quality
and reliability with small size and weight.
The AD579 is available with solder-seal (D) for harsh or
rigorous surroundings and is contained in a 32-pin sidebrazed, ceramic DIP.
AD579 ORDERING GUIDE
Model
AD579]N
AD579KN
AD579TD
AD579Z]N
AD579ZKN
AD579ZTD
AD579TD/883B
AD579ZTD/883B
Conversion
Speed
2.2J.1s
1.8J.1s
1.8J.1s
2.2J.1s
1.8J.1s
1.8J.1s
1.8J.1s
1.8J,1S
Package
Hermetic-Seal
Hermetic-Seal
Hermetic-Seal
Hermetic-Seal
Hermetic-Seal
Hermetic-Seal
Hermetic-Seal
Hermetic-Seal
Temperature
Range
Power Supply
Range
Package
Outline·
o to +70°C
o to +70°C
±15V ±lO%
±15V ±lO%
±15V ±lO%
±12V ±5%
±12V ±5%
±12V ±5%
±15V ±lO%
±12V ±5%
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
DH-32B
_55°C to +125°C
o to +70oC
o to +70oC
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
·See Section 14 for package outline information.
ANALOG-TO-OIGITAL CONVERTERS 3-63
•
SPECIFICATIONS
(typical @+25"C; ±15Vand +5V power supplies unless otherwise noted)
Model
AD579JN
RESOLUTION
10 Bits
ANALOG INPUTS
Voltage Ranges
Bipolar
Unipolar
Input Impedance
o to +10V, ±SV
±IOV, 0 to +20V
AD579KN
ADS79TD
±S.OV, ±IOV
o to +IOV, 0 to +20V
SkU (±20%)
10kU (±20%)
DIGITAL INPUTS
Convert Command l
Clock Input
ILS TTL Load
ILS TTL Load
TRANSFER CHARACTERISTICS
Gain Error'2,3
±O.I % FSR (±0.2S% FSR max)
±O.I % FSR (±0.2S% FSR max)
±O.I % FSR (±0.2S% FSR max)
Unipolar Offset3
Bipolar Offset'"
Linearity Error
+2S o C
Tmin to Tma.x
±II2LSB max
±3/4LSB max
DIFFERENTIAL LINEARITY ERROR
(Minimum resolution for which no
missing codes are guaranteed)
10 Bits
10 Bits
+2SoC
Tmin to Tmax
POWER SUPPLY SENSITIVITY
+ISV ±IO%
-ISV ±IO%
+5V ±IO%
0.005%1%i'>Vs max
0.005%/%6Vs max
O.OOI%I%i'>Vs max
"Z" Versions
+12V ±5%
-12V ±S%
0.007%1%i'>Vs max
0.007%1%i'>Vs max
TEMPERATURE COEFFICIENTS
Gain
Unipolar Offset
±2Sppm/0C typ
±4Oppm/oC max
±Sppmt" C typ
±15ppm/oC max
Bipolat Offset
±Sppmf"Ctyp
±20ppmtC max
Differential Linearitv
±2ppm/oC typ
CONVERSION TIME'" (max)
Conversion Time Tmin to Tmax
PARALLEL OUTPUTS
Unipolar Code
Bipolar Code
Binary
Offset Binary /Two's Complement
2LSTTL Loads
Output Drive
SERIAL OUTPUTS (NRZ FORMAT)
Unipolar Code
Binary/Complementary Binary
Offset Binary/Comp. Offset Binary
2LSTTL Loads
Bipolar Code
Output Drive
END OF CONVERSION (EOC)
Output Drive
Logic "1" During Conversion
SLSTTL Loads
INTERNAL CLOCK'
2LSTTL Loads
Output Drive
INTERNAL REFERENCE
Voltage
Temperature Coefficient
External Current
POWER SUPPLY REQUIREMENTS
Range for Rated Accuracy
Z Models·
Supply Current
+15V
-ISV
+SV
Power Dissipation
TEMPERATURE RANGE
Operating
Storage
10.000 ±lOmV typ
ISppm/oC
±lmA max
4.75 to 5.25 and ±l3.S to ±16.S
4.75 to 5.25 and ±11.4 to ±16.5
3mA typ, SmA max
22mA typ, 35mA max
100mA typ, I SOmA max
77SmW typ
o to +70o C
-SSoC to +12SoC
-SSoC to +ISO°C
NOTES
Positive pulse 200ns wide (min) leading edge (0 to 1) resets outputs. Trailing edge
initiates conversion.
son, 1% fixed resistor in place of gain adjust potentiometer.
) Adjustable to zero.
4With 50n, 1% resistor between Ref Out and Bipolar Offset (Pins 24 & 26).
I
2 With
'Conversion time is defined as the time between the falling cdp of
convert start and the falliDB' edge of the EOC.
3-64 ANALOG- TO-DIGITAL CONVERTERS
a Each grade is specified at the conversion speed shown. See Figure 7
for appropriate connections.
Externally adjustable by a resistor or capacitor .
• For "z" models order AD579ZJN, ADS79ZKN or AD579ZTD.
·Specifications same as AD579JN.
··Specifications same as ADS79.KN.
7
Specitlcations subject to change without notice.
AD579
THEORY OF OPERATION
The ADS79 is a complete 10-bit AID converter which requires
no external components to provide the successive-approximation analog-to-digital conversion function. A block diagram
of the ADS79 is shown in Figure 1.
TEST POINT
1
TEST POINT
2
AD579
-15V
+15V
ANALOG GNO
ZERO ADJ
a:
~
!:ffi
'1'>
~~
"
l!
C
BIT3
lOV SPAN INPUT
10VSPAN INPUT
BIPOLAR OFFseT
GAIN (REF INI
REF OUT
SERIAL OUT
TIMING
The timing diagram is shown in Figure 2. Receipt of a CONVERT START signal sets the STATUS flag, indicating conversion in progress. This, in tum, removes the inhibit applied to
the gated clock, permitting it to run through 10 cycles. All
SAR parallel bit and STATUS flip-flops are initialized on the
leading edge, and the gated clock inhibit signal is removed on
the trailing edge of the CONVERT START signal. At time to.
Bl is reset and B2 -BlO are set unconditionally. At tl the
Bit 1 decision is made (keep) and Bit 2 is unconditionally
reset. At t2. the Bit 2 decision is made (keep) and Bit 3 is
reset unconditionally. This sequence continues until Bit 10
(LSB) decision (keep) is made at tlO. After a lSns delay
period, the STATUS flag is reset, indicating that the conversion is complete and that the parallel output data is
valid. Resetting the STATUS flag restores the gated clock
inhibit signal, forcing the clock output to Logic "0" state.
SERIAL OUT
BIT 1
CONVERT START
EOC
SHORT CYCLE
CONVERT
START
CLOCK IN
DIGITALGND
CLOCK OUT
+5V
CLOCKADJ
GATED
CLOCK
Figure 1. AD579 Functional Diagram and Pinout
On receipt of a CONVERT START command, the ADS79
converts the voltage at its analog input into an equivalent
bit binary number. This conversion is accomplished asfollows:
the 10-bit successive-approximation register (SAR) has its
H)-bit outputs connected both to the device bit output pins
and to the cortesponding bit inputs of the feedback DAC.
The analog input is successively compared to the feedback
DAC output, one bit at a time (MSB first, LSB last). The
decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state
of the comparator at that time.
The temperature-compensated buried Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and temperature. The
reference is trimmed to 10.00 volts ±0.1 %; it is buffered and
can supply up to 1.0mA to an external load in addition to the
current required to drive the reference inpu t resistor (O.SmA)
and bipolar offset resistor (lmA). The thin film application resistors are trimmed to match the full scale ou tpu t current of
the DAC. There are two Skfl input scaling resistors to allow
either a 10 volt or 20 volt span. The 10kfl bipolar offset resistor is grounded for unipolar operation or connected to the
10 volt reference for bipolar operation.
-.u
to
EOC
BIT 1
(MSBI
;
I
I
I
BIT 2
~
BIT 3
~
BIT 4
~
BIT 5
~
BIT 6
~
BIT 7
~
BIT 8
~
BIT 9
~
BIT 10
~
SERIAL
25ns
~75n'1 ,
LJ
U
!
L-...I...._ _ _ _ _....
U
U
U
U
•• 0 .. 1 ' i I
z<4I'?'tWA 81 : B2 I._
L!!.J1::1
B4 L!!J B6 L!J B8 : 89 iS10 :
~/N////,I
,
CLOCK
INTERNAL: CONNECT CLOCK OUT (181 TO CLOCK IN 1191
EXTERNAL: CONNECT EXTERNAL CLOCK TO CLOCK IN 1191
CLOCK SHOULD BE AT LEAST 30% DUTY CYCLE WITH
MINIMUM PERIOD, TMIN OF 100ns.
Figure 2. AD579 Timing Diagram
Serial data does not change and is guaranteed valid on negativegoing clock edges. therefore; serial data can be transferred
quite simply by clocking it into a receiving shift register on
these edges (see Figure 2).
Incorporation of this lSns delay guarantees that the parallel
(and serial) data are valid at the Logic "1" to "0" transition
of the STATUS flag, permitting parallel data transfer to be
initiated by the trailing edge of the STATUS signal.
ANALOG-TO-DIGITAL CONVERTERS 3-65
UNIPOLAR CALIBRATION
The AD579 is intended to have a nominall/2LSB offset so
that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes
above and below it). Thus, when propetly calibrated, the first
transition (from 0000 0000 00 to 0000 0000 01) will occur
for an input level of +1/2LSB (4.88mV for 10V range).
If pin 26 is connected to pin 30, the unit will behave in this
manner, within specifications. Refer to Table I and Figure 3
for further clarification. If the offset trim (Rl) is used, it
should be trimmed as above, although a different offset can
be set for a particular system requirement. This circuit will
give approximately ±50mV of offset trim range.
The full scale trim is done by applying a signal 1 1/2LSB below
the nominal full scale (9.985V for a 10V range). Trim R2 to
give the last transition (1111111110 to 11111111 11).
ERROR SOURCES
The analog continuum is partitioned into 2 10 discrete ranges
for lO-bit conversion. All analog values within a given quantum are represented by the same digital code, usually assigned
to the nominal midrange value. There is an inherent quantization uncertainty of ±1I2LSB, associated with the resolution,
in addition to the actual conversion errors.
The actual conversion errors that are associated with AID
converters are combinations of analog errors due to the linear
circuitry, matching and tracking properties of the ladder and
scaling networks, reference error and power supply rejection.
The matching and tracking errors in the ADS 79 have been minimized by the use of a monolithic DAC that includes the scaling
network. The initial gain and offset errors are specified at ±O.l %
FSR typical. These errors may be trimmed to zero by the use
of the external trim circuits as shown in Figures 3 and 4. Linearity error is defined as the deviation from a true straight line
transfer characteristic from a zero analog input which calls for
a zero digital output to a point which is defined as full scale.
The linearity error is unadjustable and is the most meaningful
indication of AID converter accuracy. Differential nonlinearity
is a measure of the deviation in staircase step width between
codes from the ideal least significant bit step size (Figure S).
AD579
r-IL ___________________
~
I
~
°SEEFlaURE7
Figure 3_ Unipolar Input Connections
BIPOLAR OPERATION
The connections for bipolar ranges are shown in Figure 4.
Again, as for the unipolar ranges, if the offset and gain specifications are sufficient, the lOOn trimmer shown can be
replaced by a son ±l % fixed resistor. The analog input is
Monotonic behavior requires that the differential linearity
error be less than 1LSB, however a monotonic converter can
having missing codes; the ADS79TD is specified as having no
missing codes from -5SoC to +125°C and thus is monotonic.
There are three types of drift error over temperature: offset,
gain and linearity. Offset drift causes a shift of the transfer
characteristic left or right over the operating temperature
range. Gain drift causes a rotation of the transfer characteristic about the zero or minus full :;cale point. The worst case
accuracy drift is the summation of all three drift errors over
temperature. Statistically, however, the drift error behaves as
the root-sum-squared (RSS) and can be shown as:
AD579
...'
r-I
applied as for the unipolar ranges. Bipolar calibration is similar
to unipolar calibration. First, a signal 1I2LSB above negative
full scale (-4.9957V for the ±5V range) is applied, and R1 is
trimmed to give the first transition ~(OOOO 0000 00 to
0000000001). Then, a signel 1 1I2LSB below positive
full scale (+4.98S3V for the ±5V range) is applied and R2
trimmed to give the last transition (11111111 10 to
1111111111).
RSS=v'€G 2 +€02 +€L 2
I
~
€G = Gain Drift Error (ppm/°C)
€o = Offset Drift Error (ppm of FSR/°C)
€L = Linearity Error (ppm of FSR/oC)
L ____ - - - - -------.;EFIGU'Ri1
Figure 4. Bipolar Input Connections
Analog Input - Volts
(Center of Quantization Interval)
o to +10V o to +20V
-5V to +5V -10V to +10V
Range
Range
Digital Output Code
(Binary for Unipolar Ranges,
Offset Binary for Bipolar Ranges)
Bl
(MSB)
BI0
(LSB)
Range
Range
+9.9902
+9.9804
+19.9804 +4.9902
+19.9609 +4.9804
+9.9804
+9.9609
1111111111
1111111110
+5.0097
+5.0000
+10.0195
+10.0000
+0.0097
+0.0000
+0.0195
+0.0000
1000000001
1000000000
+0.0097
+0.0000
+0.0195
+0.0000
-4.9902
-5.0000
-9.9804
-10.0000
0000000001
0000000000
Table I. Digital Output Codes VB. Analog Input for Unipolar and Bipolar Ranges
3-66 ANALOG-TO-DIGITAL CONVERTERS
AD579
Short Cycle Input - A Short Cycle Input, pin 14, permits the
timing cycle shown in Figure 2 to be terminated after any
number of desired bits has been converted, allowing somewhat shorter conversion times in applications not requiring
fulll0-bit resolution. Short cycle pin connections and associated maximum 10- and 8-bit conversion times are summarized in Table II.
111.
'00.
Resolution (Bits)
Connect Pin 14 to Pin
Conversion Speed (~s)
000.
,
~-lLSB
8
10
2
4
1.8
1.5
Figure 5. Transfer OIaracteristic for an Ideal Bipolar AID
Table II. Short Cycle Connections
LAYOUT CONSIDERATIONS
Many data acquisition components have two or more ground
pins which are not connected together within the device. These
"grounds" are usually referred to as the Logic Power Return,
Analog Common (Analog Power Return), and Analog Signal
Ground. These grounds must be tied together at one point,
usually at the system power-supply ground. Ideally, a single
solid ground would be desirable. However, since current flows
through the ground wires and etch stripes of the circuit cards,
and since these paths have resistance and inductance, hundreds
of millivolts can be generated between the system ground point
and the ground pin of the ADS79. Separate ground returns
should be provided to minimize the current flow in the path
from sensitive points to the system ground point. In this way
supply currents and logic-gate return currents are not summed
into the same return path as analog signals where they would
cause measurement errors.
Each of the ADS79's supply terminals should be capacitively
decoupled as close to the ADS 79 as possible. A large value
capacitor such as 10~F in parallel with a O.I~F capacitor is usually sufficient. Analog supplies are bypassed to the
Analog Power Return pin and the logic supply is bypassed to
the Digital GND pin.
11+
+5V
DIGo. 1P.F
COM
rr
@
10pF
@)
Figure 6. Basic Grounding Practice
To minimize noise the reference output (Pin 24) should be
decoupled by a 6.8~F capacitor to pin 30.
CLOCK RATE CONTROL
The internal clock is preset to a nominal conversion time of
4.8~. It can be adjusted for either faster or slower conversions. For faster conversion connect the appropriate 1%
resistor between pin 17 and pin 18 and short pin 18 to pin 19.
JORADE
External Oock - An external clock may be connected direcdy
to the clock input, pin 19. When operating in this mode the
convert start should be held high for a minimum of one clock
period in order to reset the SAR and synchronize the conversion cycle.
External Buffer Amplifier - In applications where the ADS79
is to be driven from high impedance sources or directly from
an analog multiplexer a fast slewing, wideband op amp like
the AD841 should be used.
ADS1.
10·BIT
AID
J
OIGITAL
OUTPUTS
Figure 8. Input Buffer
SAMPLED DATA SYSTEMS
The conversion speed of the ADS79 allows accurate digitization of high frequency signals and high throughput rates in
multichannel data acquisition systems. The ADS79TD, for
example, is capable of a full accuracy conversion in 1.8~s. In
order to benefit from this high speed, a fast sample-hold
amplifier (SHA) such as the: HTC'()300 is required. This SHA
has an acquisition time to 0.01% of approximately 300ns, so
that a complete sample-convert-acquire cycle can be accomplished in approximately 2.S~s. This means a sample rate of
400kHz can be realized, allowing a signal with no frequency
components above 200kHz to be sampled with no loss of information. Note that the EOC signal from the ADS79 places
the SHA in the hold mode in advance of the actual start of
the conversion cycle, and releases the SHA from the HOLD
mode only after completion of the conversion. After allowing
at least 300ns for the SHA to acquire the next analog value,
the converter can again be started.
K, TGRADES
1- 200...
CONVERT
START
2.2~
CONVERSION
RATE
B491l
",
'.~s
CONVERSION
RATE
42211
,%
NOTES: tSE
Figure 7. Clock Rate Control Connection
CONVERSION OF FIRST SAMPLE L-""::':"'::;:::':":=--'
"DC
g~~~~~~~
EOC IS ASSUMED TO BE TIED TO HOLD INPUT OF SHA
=
lOOns
Figure 9. StartlEOC Timing for Sampled Data System
ANALOG-TO-D/GITAL CONVERTERS 3-67
II
:=+::::::;;::===4==:;:======:::;;::+==
ANALOG
INPUT
OTO:'OV
15
-15V
+15V
A fast (8SkHz) 10-bit DAS can be configured using the AD1362
and the ADS79. The AD1362 contains two 8-channelmultiplexers, a differential amplifier, a sample-and-hold with highspeed output amplifier, a channel address latch and control
logic. The multiplexers may be connected to the differential
amplifier in either an 8-channel differential or 16-channel
single-ended configuration. A feature of the AD1362 is an
internal user-controllable analog switch that connects the
multiplexers in either a single-ended or differential mode. This
allows a single device to perform in either mode without hardwire programming and permits a mixture of single-ended and
differential sources to be interfaced by dynamically switching
the input mode control.
Figure 10. 400kHz - 10-Sit,AiD Conversion System
ANALOG
INPUT
OTO 10V
CONVERT
START
Figure ". 154kHz - 10-Sit,AiD Conversion System
DC POWER
DATA
BITll
OUT
(101
ANALOG
INPUTS
1161
CHANNEL
SELECT
LATCH
Figure 12. High Speed 10-Sit DAS
3-68 ANALOG-TO-DIGITAL CONVERTERS
Figure 13. High Speed-165kHz-10-Sit DAS
A high speed lO-bit DAS with a throughput rate of 16SkHz
can be built around an ADS79. The DAS of Figure 13 "Ping
Pangs" two sample and hold amplifiers to eliminate the
effects of the acquisition time of the sample and hold amplifiers. By applying sequential channel address the AO of the
address enables one of the two multiplexers. The incorporation of the flip-flops on the SHA mode controls and the
switch address allows a new channel address to be latched in
while a conversion is in progress.
IIIIIIIIIII ANALOG
WDEVICES
FEATURES
Complete 8-Bit Signal Conditioning AID Converter
Including Instrumentation Amp and Reference
Microprocessor Bus Interface
10fl.S Conversion Speed
Flexible Input Stage: Instrumentation Amp Front End
Provides Differential Inputs and High Common-Mode
Rejection
No User Trims Required
No Missing Codes Over Temperature
Single + 5V Supply Operation
Convenient Input Ranges
200Pin DIP or Surface-Mount Package
Low Cost Monolithic Construction
Low Cost Signal
Conditioning 8-Bit AOC
AD670 I
AD670 BLOCK DIAGRAM AND
TERMINAL CONFIGURATION
(ALL PACKAGES)
CE
The device is configured with input scaling resistors to permit
two input ranges: 0 to 255mV (ImV/LSB) and 0 to 2.S5V
(IOmV/LSB). The AD670 can be configured for both unipolar
and bipolar inputs over these ranges. The differential inputs and
common-mode rejection of this front end are useful in applications
such as conversion of transducer signals superimposed on commonmode voltages.
The AD670 incorporates advanced circuit design and proven
processing technology. The successive approximation function is
implemented with I2L (integrated injection logic). Thin-film
SiCr resistors provide the stability required to prevent missing
codes over the entire operating temperature range while laser
wafer trimming of the resistor ladder permits calibration of the
device to within ± lLSB. Thus, no user trims for gain or offset
are required. Conversion time of the device is lOlLS.
RIW
FORMAT BPOIUPO
II
POWER GND
GENERAL DESCRIPTION
The AD670 is a complete 8-bit signal conditioning analog-to-digital
converter. It consists of an instrumentation amplifier front end
along with a DAC, comparator, successive approximation register
(SAR), precision voltage reference, and a three-state output
buffer on a single monolithic chip. No external components or
user trims are required to interface, with full accuracy, an analog
system to an 8-bit data bus. The AD670 will operate on the
+ 5V system supply. The input stage provides differential inputs
with excellent common-mode rejection and allows direct interface
to a variety of transducers.
cs
+v~
The AD670 is available in four package types and five grades.
The J and K grades are specified over 0 to + 70°C and come in
20-pin plastic DIP packages or 20-terminal PLCC packages.
The A and B grades ( - 40°C to + 85°C) and the S grade ( - 55°C
to + 125°C) come in 20-pin ceramic DIP packages.
The S grade is also available with optional processing to MIL-STD883 in 20-pin ceramic DIP or 20-terminal LCC packages. The
Analog Devices Military Products Databook should be consulted
for details on these confignrations.
PRODUCT HIGHLIGHTS
1. The AD670 is a complete 8-bit AID including three-state
outputs and microprocessor control for direct connection to
8-bit data buses. No external components are required to
perform a conversion.
2. The flexible input stage features a differential instrumentation
amp input with excellent common-mode rejection. This
allows direct interface to a variety of transducers without
preamplification.
3. No user trims are required for 8-bit accurate performance.
4. Operation from a single + 5V supply allows the AD670 to
run off of the microprocessor's supply.
5. Four convenient input ranges (two unipolar and two bipolar)
are available through internal scaling resistors: 0 to 2SSmV
(lmV/LSB) and 0 to 2.55V (lOmV/LSB).
6. Software control of the output mode is provided. The user
can easily select unipolar or bipolar inputs and binary or 2's
complement output codes.
ANALOG-TO-OIGITAL CONVERTERS 3-69
SPECIFICATIONS
(@ Vee
Model
= + 5V and + 25"1: unless otherwise noted)
AD678J
Mia
OPERATING TEMPERATURE RANGE
0
RIlSOLUTION
8
Typ
+70
AD678K
Mia
Typ
+70
0
8
Uala
"C
Bit
CONVI!RSIONTlMI!
10
10
RIlLATIVE ACCURACY
TllliDroT_
±11l
±11l
±V4
±112
LSD
LSD
±l.S
±2.0
±0.7S
±1.0
LSD
LSD
±l.S
±2.0
±0.7S
±1.0
LSD
LSD
±l.S
±2.0
±0.7S
±1.0
LSB
LSD
DIFFERENTiAL UNl!ARITY I!RROR
TIIIIiD to T ......
'"
GUAIlANTEI!D NO MISSING CODES ALL GRADES
GAiN ACCURACY
@+2S"C
TJDin to T_
UNWOLAR ZERO ERROR
@+2S"C
Tmba to T_
BIPOLAR ZERO I!RROR
@+2S"C
TllliRtoT...,..
ANALOG INPUT RANGES
DIFFI!RIlNTIAL( -VlNto + VIN)
Low Range
ABSOLUTE (Inputs to PowerGnd)
Low Range T min to T_
High Range T ..... to T ~
Oto +255
-128[0 + 127
Oto+2.SS
- 1.28 to + 1.27
Oto+2SS
-128to+ 127
010+2.55
-1.28to + 1.27
High Range
-USO
Vee -3.4
Va:
-1.50
mV
mV
V
V
-USO
Vee -3.4
-1.50
Vee
V
V
200
SOO
nA
40
200
nA
12.0
1dI
DIAS CURRIlNT (2SSmV RANGE)
Tmin to Tmu
200
SOO
40
200
OFFSET CURRIlNT (2SSmV RANGE)
TmintoTIIIIIII
2.SSVRANGEINPUTRESISTANCE
12.0
8.0
2.5SV RANGE FULL SCALE MATCH
+ AND-INPUT
8.0
LSD
±1/2
"Ill
COMMON·MODEREJI!CTION
RATIO (2SSmV RANGE)
1
1
LSD
COMMON·MODEREJECTION
RATIO(2.5SVRANGE)
I
I
LSD
5.5
45
0.015
%ofFSJ%
POWER SUPPLY
Operating Range
4.5
Current Icc
Rejection Ratio T min to T mill
30
5.5
45
0.015
4.5
30
V
mA
DIGITAL OUTPUTS
SINK CURRIlNT (VOUT = 0.4V)
Tm,iQ.lOTmu.
1.6
mA
1.6
SOURCECURRIlNT(VoUT = 2.4V)
TmintoTmu
±4O
5
OUTPUT CAPACITANCE
DIGITAL INPUT VOLTAGE
VINL
VINH
mA
0.5
0.5
THRE&STATELEAKAGECURRENT
±4O
"A
pF
0.8
V
V
5
0.8
2.0
2.0
DIGITAL INPUT CURRENT
(O:s;V1N:s;
+ SV)
-100
IINL
-100
+100
+100
IINH
INPUT CAPACITANCE
10
10
"A
.,.A
pF
NOTES
Specifications shown in boldface art tested on all production units at fmal elcctricaltest. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications art guaranteed. althougb only those shown in boldface are tested. on aU production units.
SpecifICations subject to change without notice.
~70
ANALOG-TO-DIGITAL CONVERTERS
AD670
AD670A
Model
MiD
OPERATING TEMPERATURE RANGE
-40
RESOLUTION
8
Typ
AD670S
AD670B
Max
MiD
+85
-40
Typ
Max
Mi.
+85
-55
Typ
Max
VailS
+ 125
'C
Bit
8
8
CONVERSION TIME
1O
1O
1O
~s
RELATIVE ACCURACY
±112
::tIll
:t1/4
±112
±112
±I
LSD
LSB
TminlOTmax
DIFFERENTIAL LINEARITY ERROR
GUARANTEED NO MISSING CODES ALL GRADES
Tmi"mT_II:
GAIN ACCURACY
@ +25'C
T.u.toT_
UNIPOLAR ZERO ERROR
@ +25'C
T.w.toTmu
BIPOLAR ZERO ERROR
@+25'C
TllliDloT_
±1.5
±2.5
±0.75
±l.5
±1.5
::t2.5
LSB
LSB
±I.O
±2.0
±0.5
::t1.0
:tl.0
±2.0
LSD
LSB
:tl.O
"'0.5
±I.O
::t1.0
"'2.0
LSB
LSB
::t2.0
ANALOG INPUT RANGES
DIFFERENTIAL(-VINto +V 1N)
Low Range
010+255
-12810+ 127
010+2.55
-1.2810 + 1.27
HigbRange
ABSOLUTE (InputsloPowerGnd)
Low Range T min to T IIIIIX
-8.150
010 +255
-12810+127
0[0+2.55
-1.28[0 + 1.27
-1.2810 + 1.27
Vee -3.5
Vcr;
-1.50
Higb Range Tmin to T max
Oto +255
-12810 + 127
Oto +2.55
-8.150
Vee -3.5
Vcr;
-1.50
mV
mV
V
V
-8.150
Vee -3.S
-1.50
Vcr;
V
V
200
758
.A
40
200
nA
12.0
kll
BIAS CURRENT (255mV RANGE)
TminIOT...."
200
500
40
200
200
500
40
200
OFFSET CURRENT (255mV RANGE)
TminlOTmax
2.55V RANGE INPUT RESISTANCE
8.0
2.55V RANGE FULL SCALE MATCH
+ AND - INPUT
12.0
8.0
±1/2
12.0
8.0
~112
± 112
LSB
COMMON-MODE REJECTION
RATIO(255mVRANGE)
I
I
I
LSD
COMMON-MODE REJECTION
RATIO(2.55V RANGE)
I
I
I
LSD
5.5
45
0.015
V
mA
POWER SUPPLY
Operating Range
4.5
Currentl(:c
Rejection Ratio T min to T mu
DIGITAL OUTPUTS
SINKCURRENT(VoUT
~
30
5.5
45
0.015
4.5
30
5.5
45
0.015
4.75
30
%ofFSI
0.4V)
TminlOTmu
SOURCECURRENT(VoUT
~
1.6
1.6
1.6
0.5
0.5
0.5
TminlOTmu
THREE-STATE LEAKAGE CURRENT
±40
OUTPUT CAPACITANCE
DIGITAL INPUT VOLTAGE
V 1NL
V 1NH
rnA
2.4V)
5
5
0.8
2.0
mA
±40
"'40
5
0.8
0.7
2.0
~A
pF
2.0
V
V
DIGITAL INPUT CURRENT
(OSV1N:s
+ SV)
IINL
-100
-100
INPUT CAPACITANCE
-100
+100
liNK
10
~A
+100
10
+100
10
~
pF
NOTES
Specifacations shown in boldface are tested on all production Wlits at final electrical test. Results from those tests are used to ca1cu1ate outgoing quality
levels. AU min and max specifications are JU8l'anteed. although only those shown in boldface are tested on all production units.
Specifications subject to cb8DJc without noticc.
ANALOG-TO-DIGITAL CONVERTERS 3-71
II
CE
CS
RIW
FORMAT BPOIUPO
ABSOLUTE MAXIMUM RATINGS*
Vee to Ground . . . • . • • . . • • . . . • . • OV to +7.SV
Digital Inputs (Pins 11-15) • • • . . . . -O.SV to Vee +O.SV
Digital OutpUts (Pins 1-9) . Momentary Short to Vee or Ground
Analog Inputs (Pins 16-19) •
-30V to+30V
Power Dissipation. . . . . . • . . .
• . • •. 4SOmW
Storage Temperature Range . • • . .
-6S"C to + ISO"C
Lead Temperature (Soldering, 10sec)
• . . •. + 3OO"C
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to tbe device. This is a stress rating only and
functioDal operation of tbe device at tbese or any other conditions above
those indicated in tbe operatioDal sections of tbis specification is not
implied. Exposure to absolute muimum rating conditions for extended
periods may affect device reIisbility.
POWER GND
+ Vee
Figure 1. AD670 Block Diagram and Terminal Configuration
(All Packages)
AD670 ORDERING GUIDE
Model
Temperature
Range
Relative Accuracy
@25·C
Gain Accuracy
@25·C
Package Options·
AD670JN
AD670JP
AD670KN
AD670KP
AD670AD
AD670BD
AD670SD
Oto + 70°C
Oto + 70°C
Oto+70·C
Oto+70·C
- 40°C to + 8SoC
- 40"C to + 85°C
- SsoC to + 12SoC
±1I2LSB
±1I2LSB
±1I4LSB
±1I4LSB
± 1I2LSB
±1I4LSB
± 1I2LSB
±l.SLSB
± l.SLSB
±0.7SLSB
±0.7SLSB
±1.5LSB
±0.7SLSB
±1.5LSB
Plastic DIP (N-20)
PLCC(P-20A)
Plastic DIP (N-20)
PLCC (P-20A)
Ceramic DIP (D-20)
Ceramic DIP (D-20)
Ceramic DIP (D-20)
*Section 13 for package outline information.
CIRCUIT OPERATION/FUNCTIONAL DESCRIPTION
The AD670 is a functionally complete 8-bit signal conditioning
A/D converter with microprocessor compatibility. The input
section uses an instrumentation amplifier to accomplish the
voltage to current conversion. This front end provides a high
impedance, low bias current differential amplifier. The commonmode range allows the user to directly interface the device to a
variety of transducers.
The AID conversions are controlled by R/W, CS, and CEo The
RlW line directs the converter to read or start a conversion. A
minimum write/start pulse of 300ns is required on either CE or
CS. The STATUS line goes high, indicating that a conversion is
in process. The conversion thus begun, the internal 8-bit DAC
is sequenced from MSB to LSB using a novel successive approximation technique. In conventional designs, the DAC is
stepped through the bits by a clock. This can be thought of as a
static design since the speed at which the DAC is sequenced is
determined solely by the clock. No clock is used in the AD670.
Instead, a "dynamic SAR" is created consisting of a string of
inverters with taps along the delay line. Sections of the delay
line between taps act as one shots. The pulses are used to set
and reset the DAC's bits and strobe the comparator. When
strobed, the comparator then determines whether the addition
of each successively weighted bit current causes the DAC current
3-72 ANALOG-TO-DIGITAL CONVERTERS
sum to be greater or less than the input current. If the sum is
less, the bit is turned off. After all bits are tested, the SAR
holds an 8-bit code representing the input signal to within 1I2LSB
accuracy. Ease of implementation and reduced dependence on
process related variables make this an attractive approach to a
successive approximation design.
The SAR provides an end-of-conversion signal to the control
logic which then brings the STATUS line low. Data outputs
remain in a high impedance state until RtW is brought high
with CE and CS low and allows the converter to be read. Bringing
CE or CS high during the valid data period ends the read cycle.
The output buffers cannot be enabled during a conversion. Any
convert start commands will be ignored until the conversion
cycle is completed; once a conversion cycle has been started it
cannot be stopped or restarted.
The AD670 provides the user with a great deal of flexibility by
offering two input spans and formats and a choice of output
codes. Input format and input range can each be selected. The
BPO/uPO pin controls a switch which injects a bipolar offset
current of a value equal to the MSB less 1I2LSB into the summing
node of the comparator to offset the DAC output. Two precision
10 to 1 attenuators are included on board to provide input range
selection of 0 to 2.5SV or 0 to 255mV. Additional ranges of
AD670
-1.28 to 1.27V and -128 to 127mV are possible if the BPOIUPO
switch is high when the conversion is started. Finally, output
coding can be chosen using the FORMAT pin when the conversion
is started. In the bipolar mode and with a logic I on FORMAT,
the output is in two's complement; with a logic 0, the output is
offset binary.
CONNECTING THE AD670
The AD670 has been designed for ease of use. All active components required to perform a complete AID conversion are on
board and are connected internally. In addition, all calibration
trims are performed at the factory, assuring specified accuracy
without user trims. There are, however, a number of options
and connections that should be considered to obtain maximum
flexibility from the part.
INPUT CONNECTIONS
Standard connections are shown in the figures that follow. An
input range of 0 to 2.SSV may be configured as shown in Figure
2a. This will provide a one LSB change for each 10mV of input
change. The input range of 0 to 255mV is configured as shown
in Figure 2b. In this case, each LSB represents ImV of input
change. When unipolar input signals are used, Pin II, BPOIUPO,
should be grounded. Pin II selects the input format for either
unipolar or bipolar signals. Figures 3a and 3b show the input
connections for bipolar signals. Pin 11 should be tied to + Vee
for bipolar inputs.
Although the instrumentation amplifier has a differential input,
there must be a return path to ground for the bias currents. If it
is not provided, these currents will charge stray capacitances
and cause internal circuit nodes to drift uncontrollably causing
the digital output to change. Such a return path is provided in
Figures 2a and 3a (larger input ranges) since the Ik resistor leg
V1N+G-.--t--i
2a. 0 to 2.55V (10mVILSB)
2b. 0 to 255m V (1mVILSB)
NOTE: PIN 11. BPO/UPO SHOULD BELOW WHEN
CONVERSION IS STARTED.
Figure 2. Unipolar Input Connections
AD670
V'N+
G--.---+---t
V'N-
o-...L.----;
3a. ± 1.2BV Range
AD670
V'N- 0--'--.....
3b. ± 12BrnV Range
NOTE: PIN 11. BPO/UPO SHOULD BE HIGH WHEN
CONVERSION IS STARTED.
Figure 3. Bipolar Input Connections
is tied to ground. This is not the case for Figures 2b and 3b
(the lower input ranges). When connecting the AD670 inputs to
floating sources, such as transformers and ac-coupled sources,
there must still be a dc path from each input to common. This
can be accomplished by connecting a IOkH resistor from each
input to ground.
Bipolar Operation
Through special design of the instrumentation amplifier, the
AD670 accommodates input signal excursions below ground,
even though it operates from a single SV supply. To the user,
this means that true bipolar input signals can be used without
the need for any additional external components. Bipolar signals
can be applied differentially across both inputs, or one of the
inputs can be grounded and a bipolar signal applied to the
other.
Common.Mode Performance
The AD670 is designed to reject dc and ac common-mode voltages.
In some applications it is useful to apply a differential input
signal VIN in the presence of a dc common-mode voltage VC-M'
The user must observe the absolute input signal limits listed in
the specifications, which represent the maximum voltage VIN +
VCM that can be applied to either input without affecting proper
operation. Exceeding these limits (within the range of absolute
maximum ratings), however, will not cause permanent damage.
The excellent common-mode rejection of the AD670 is due to
the instrumentation amplifier front end, which maintains the
differential signal until it reaches the output of the comparator.
In contrast to a standard operational amplifier, the instrumentation
amplifier front end provides significantly improved CMRR over
a wide frequency range (Figure 4a).
ANALOG-TO-OIGITAL CONVERTERS 3-73
II
80
"-
60
"""
BPO/UPO
FORMAT
INPUTRANGEIOUTPUTFORMAT
o
1
o
o
1
1
1
UnipolarlStraight Binary
Bipolar/Offset Binary
Unipolar/2'sCompiement
Bipolar/2's Complement
o
Table I. AD670 Input Selection/Output Format Truth Table
r-....
20
1k
'Ok
'OOk
FREQUENCY - Hz
,M
'OM
Figure 4a. CMRR over Frequency
TO
STRAIGHT BINARY
(FORMAT = 0, BPO/UPO = 0)
o
o
0000 0000
o
128mV 1000 0000
o
255mV 1111 1111
255mV
0000 0000
o
127mV
0000 0001
1mV
-127mV 255mV 1111 1111
DIFF
Y'N
-Y,N
+V'N
o
128mV
255mV
255mV
128mV
128mV
OTHER::-r---;:=t:~--------l
CIRCUITS
Figure 5a. Unipolar Output Codes (Low Range)
AD670
LOGIC
I ~~-===l""_...J
-IN~
MAIN
+5V
OFFSET BINARY
(FORMAT 0,
BPO/UPO = 1)
o
1000 0000
127mV
1111 1111
127mV
1111 1111
o
1000 0000
1mV
1000 0001
-1mV
0111 1111
-128mV 0000 0000
-128mV 0000 0000
SUPPLY
DIFF
Y'N
+V'N
+ V GND NOISE-
+v-
-
+v-
DIGITAL CURRENTS SHARE CONDUCTOR
WITH ANALOG SIGNAL
Figure 4b. A0670 Input Rejects Common-Mode Ground
Noise
Good common-mode performance is useful in a number of ,
situations. In bridge-type transducer applications, such performance facilitates the recovery of differential analog signals in the
presence of a dc common-mode or a noisy electrical environment.
High-frequency CMRR also becomes important when the analog
signal is referred to a noisy, remote digital ground. In each case,
the CMRR specification of the AD670 allows the integrity of
the input signal to be preserved.
The AD670's common-mode voltage tolerance allows great
flexibility in circuit layout. Most other AID converters require
the establishment of one point as the analog reference point.
This is necessary in order to minimize the effects of parasitic
voltages. The AD670, however, eliminates the need to make the
analog ground reference point and AID analog ground one and
the same. Instead, a system such as that shown in Figure 4b is
possible as a result of the AD670's common-mode performance.
The resistors and inductors in the ground return represent
unavoidable system parasitic impedances.
Input/Output Options
Data output coding (2's complement vs. straight binary) is
selected using Pin 12, the FORMAT pin. The selection of input
format (bipolar vs. unipolar) is controlled using Pin 11, BPO/UPO.
Prior to a write/convert, the state of FORMAT and BPO/UPO
should be available to the converter. These lines may be ped to
the data bus and may be changed with each conversion if desired.
The configurations are shown in Table I. Output coding for
representative signals in each of these configurations is shown in
Figure 5.
An output signal, STATUS, indicates the status of the conversion.
STATUS goes high at the beginning of the conversion and
returns low when the conversion cycle has been completed.
3-74 ANALOG-TO-OIGITAL CONVERTERS
-Y,N
o
0
127mV
0
1.127V
1.000V
255mV
255mV
128mV
127mV
127mV
128mV
127mV
255mV
-128mV 0
=
2'5 COMPLEMENT
(FORMAT 1,
BPO/UPO = 1)
0000 0000
0111 1111
0111 1111
0000 0000
0000 0001
1111 1111
1000 0000
1000 0000
=
Figure 5b. Bipolar Output Codes (Low Range)
Calibration
Because of its precise factory calibration, the AD670 is intended
to be operated without user trims for gain and offset; therefore,
no provisions have been made for such user trims. Figures 6a,
6b, and 6c show the transfer curves at zero and full scale for the
unipolar and bipolar modes. The code transitions are positioned
so that the desired value is centered at that code. The first LSB
transition for the unipolar mode occurs for an input of + 1I2LSB
(5mV or O.5mV). Similarly, the MSB transition for the bipolar
mode is set at -1I2LSB (-5mV or -O.SmV). The full scale
transition is located at the full scale value - 1 1I2LSB. These
values are 2.S4SV and 254.5mV.
OUTPUT
CODES
I
(0000 00111
(0000 00101
I
10000 00011
LSB TRANsmON AT +1I2LSB
10000 00001
ANALOG INPUT
ov
Figure 6a. Unipolar Transfer Curve
AD670
BPOlilPliG-------------,
F~~[}-_=====;=::~~~~:JL--JL-,
TO CONTROL
LOGIC
C§Q--+t-t--i
CE
U---++++-1
TRI·STATE ENABLE
TO OUTPUT BUFFER
HIGH::: THREE·STATE
>-------:::L.['-;::' MASTER RESET
ANALOG INPUT
STATUS
Figure 6b. Bipolar
U - - - -.....-OC:;'
NORMALL V HIGH
~--------- ~~~~:~~
STATUS OUTPUT
BUFFER
(O.255V)
2.550V
(1111 11111
Figure 7. Control Logic Block Diagram
FS TRANSITION AT 2.545V (O.2545V)
RIW
CS
CE
OPERATION
0
I
0
0
X
X
X
I
0
0
I
WRITE/CONVERT
READ
NONE
NONE
X
Figure 6c. Full Scale (Unipolar)
Table II. AD670 Control Signal Truth Table
Figure 6. Transfer Curves
CONTROL AND TIMING OF THE AD670
Control Logic
The AD670 contains on-chip logic to provide conversion and
data read operations from signals commonly available in microprocessor systems. Figure 7 shows the internal logic circuitry of
the AD670. The control signals, CE, CS, and RiW control the
operation of the converter. The read or write function is determined
by RiW when both CS and CE are low as shown in Table II. If
all three control inputs are held low longer than the conversion
time, the device will continuously convert until one input, CE,
CS, or RiW is brought high. The relative ~ of these signals
is discussed later in this section.
Timing
The AD670 is easily interfaced to a variety of microprocessors
and other digital systems. The following discussion of the timing
requirements of the AD670 control signals will provide the
designer with useful insight into the operation of the device.
WritelConvert Start Cyele
Figure 8 shows a complete timing diagram for the writelconvert
start cycle. CS (chip select) and CE (chip enable) are active low
and are interchangeable signals. Both CS and CE must be low
for the converter to read or start a conversion. The minimum
pulse width, tw, on either CS or CE is 300ns to start a
conversion.
m.
Table
AD670TIMING SPECIFICATIONS
Boldface indicates parameters tested 100% unless otherwise noted. See Specifications page for explanation.
Symbol
Parameter
Min
@+25·C
Typ
Max
Units
WRITE/CONVERT START MODE
tw
tDS
tDH
tRwe
tDC
tc
Write/Start Pulse Width
Input Data Setup Time
Input Data Hold
ReadIWrite Setup Before Control
Delay to Convert Start
Conversion Time
300
200
10
0
Read Time
Delay from Status Low to Data Read
Bus Access Time
Data Hold Time
Output Float Delay
RiW before CE or CS low
250
700
10
ns
ns
ns
ns
ns
jLs
READ MODE
tR
tSD
tTD
tDH
tOT
tRT
200
250
250
25
150
0
ns
ns
ns
ns
ns
ns
ANALOG-TO-DIGITAL CONVERTERS 3-75
II
STAND-ALONE OPERATION
The AD670 can be used in a "stand-alone" mode, which is
useful in systems with dedicated input ports available. Two
typical conditions are described and illustrated by the timing
diagrams which follow.
Figure 8. Write!Convert Start Timing
Single Conversion, Single Read
When the AD670 is used in a stand-alone mode, CS and CE
should be tied together. Conversion will be initiated by bringing
RIW low. Within 700ns, a conversion will begin. The RIW
pulse should be brought high again once the conversion has
started so that the data will be valid upon completion of the
.conversion. Data will remain valid until CE and CS are brought
high to indicate the end of the read cycle or RlWgoes low. The
timing diagram is shown in Figure 10.
The RIW line is used to direct the converter to start a conversion
(RiW low) or read data (RIW high). The relative sequencing of
the three control signals (RIW, CE, CS) is unimportant. However,
when all three signals remain low for at least 300ns (tw), STATUS
will go high to signal that a conversion is taking place.
Once a conversion is started and the STATUS line goes high,
convert start commands will be ignored until the conversion
cycle is complete. The output data buffer cannot be enabled
during a conversion.
Read Cycle
Figure 9 shows the timing for the data read operation. The data
outputs are in a high impedance state until a read cycle is initiated.
To begin the read cycle, RIW is brought high. During a read
cycle, the minimum pulse length for CE and CS is a function of
the length of time required for the output data to be valid. The
data becomes valid and is available to the data bus in a maximum
of 2S0ns. This delay between the high impedance state and
valid data is the maximum bus access time or tTD. Bringing CE
or CS high during valid data ends the read cycle. The outputs
remain valid for a minimum of 2Sns (tow and return to the
high impedance state after a delay, tOT, of 150ns maximum.
I
STATUS\
,L-_______________
RM
~
,
I
,
r="--Y---
,I~t~~
,I
~i
'I
!r--
1
~
1 I
I
DATA
OUTPUTS
I
I
I
I
1--1
~ --j
loT
I--
IMP
READ~
• I
i
~:
1
::
CE.CS
I
~
I
1
:----WRITE _ _~READ~
(LOW)
STATUS-::f.Ftoc
DATA~
~
I------tc---l
I
:
I
1
'
1
i twSOY;~r-1- - - -
--"'.\--
--I '",
Continuous Conversion, Single Read
A variety of applications may call for the AID to be resd after
several conversions. In process control systems, this is often
the case since a reading from a sensor may only need to be
updated every few conversions. Figure 11 shows the timing
relationships.
Once again, CE and CS should be tied together. Conversion will
begin when the RIW signal is brought low. The device will
convert repeatedly as indicated by the status line. A final conversion
will take place once the RIW line has been brought high. The
rising edge ofRIW must occur while STATUS is high. RIW
should not return high while STATUS is low since the circuit is
in a reset state prior to the next conversion. Since the rising
edge of RIW must occur while STATUS is high, RIW's length
must be a minimum of 10.2S,,"s (tc + tTD). Data becomes valid
upon completion of the conversion and will remain so until the
CE and CS lines are brought high indicating the end of the read
cycle or RIW goes low initiating a new series of conversions.
~
.m---)
cs
CE
ITIE TOGETHERi\
'
it
:
STATUS
tDe . .
DATA:
I
I
I
'toe ~RITE ~READ"':
WRITE tpc WRITE toe WRITE
j ~.....~......~
IOUTI~tc--LJ--tc~tc~
Figure 9. Read Cycle Timing
I-
Figure 10. Stand-Alone Mode Single Conversion!
Single Read
r--
~VALlDiLj.r-I
II I
t",
--::1. C
' ....
----I
___--;-1_1.---k6~T:.:J LHKlH
I'
}---WRITE
RIW
II
I
i
I
~'7777~~:r.~,.,~,",
-I',oj..Figure 11. Stand-Alone Mode Continuous Conversion!
Single Read
3-76 ANALOG-TO-DIGITAL CONVERTERS
AD670
APPLYING THE AD670
The AD670 has been designed for ease of use, system compatibility,
and minimization of external components. Transducer interfaces
generally require signal conditioning and preamplification before
the signal can be converted. The AD670 will reduce and even
eliminate this excess circuitry in many cases. To illustrate the
flexibility and superior solution that the AD670 can bring to a
transducer interface problem, the following discussions are
offered.
Temperature Measurements
Temperature transducers are one of the most common sources
of analog signals in data acquisition systems. These sensors
require circuitry for excitation and preamplificationlbuffering.
The instrumentation amplifier input of the AD670 eliminates
the need for this signal conditioning. The output signals from
temperature transducers are generally sufficiently slow that a
sample/hold amplifier is not required. Figure 12 shows the
AD590 IC temperature transducer interfaced to the AD670.
The AD580 voltage reference is used to offset the input for O°C
calibration. The current output of the AD590 is converted into
a voltage by Rl. The high impedance unbuffered voltage is
applied directly to the AD670 configured in the -128mV to
127mV bipolar range. The digital output will have a resolution
of 1°C.
+v.
!5VI
1000
SPA.
TRIM
.500
AD670
DIGITAL OUTPUT
BIPOLAR
± 127"C
MODE
1*C RESOLUTION
+5V
AD670
+5V
PLATINUM RTD
100n (a.. O·C
1mVI"C
DIGITAL OUTPUT
o to 2550C
-0.40I"C
10C RESOLUTION
2.5mA
2.5mA
Figure 13. Low Cost RTD Interface
Differential temperature measurements can be made using an
AD590 connected to each of the inputs as shown in Figure 14.
This configuration will allow the user to measure the relative
temperature difference between two points with a 1°C resolution.
Although the internal Ik and 9k resistors on the inputs have
± 20% tolerance, trimming the AD590 is unnecessary as most
differential temperature applications are concerned with the
relative differences between the two. However, the user may see
up to a 20% scale factor error in the differential temperature to
digital output transfer curve.
This scale factor error can be eliminated through a software
correction. Offset corrections can be made by adjusting for any
difference that results when both sensors are held at the same
temperature. A span adjustment can then be made by immersing
one AD590 in an ice bath and one in boiling water and eliminating
any deviation from lOOOC. For a low cost version of this setup,
the plastic AD592 can be substituted for the AD590.
+9V OR GREATER
Figure 12. AD670 Temperature Transducer Interface
Platinum RTDs are also a popular, temperature transducer.
Typical RTDs have a resistance of lOOn at OOC and change
resistance 0.40 per °C. If a constant excitation current is caused
to flow in the RTD, the change in voltage drop will be a
measure of the change in temperature. Figure 13 shows such a
method and the required connections to the AD670. The
AD580 2.5V reference provides the accurate voltage for the
excitation current and range offsetting for the RTD. The opamp is configured to force a constant 2.5mA current through
the RTD. The differential inputs of the AD670 measure the
difference between a fixed offset voltage and the temperature
dependent output of the op-amp which varies with the resistance
of the RTD. The RTD change of approximately 0.401"C results
in a ImVrc voltage change. With the AD670 in the ImV/LSB
range, temperatures from 0 to 255°C can be measured.
AD670
DIGITAL OUTPUT =
4.T±127"C
1G C RESOLUTION
I:!: 20%OF ABSOLUTE ERROR)
Figure 14. Differential Temperature Measurement Using
the AD590
ANALOG-TO-DIGITAL CONVERTERS 3-77
•
STRAIN GAUGE MEASUREMENTS
Many semiconductor-type strain gauges, pressure transducers,
and load cells may also be connected directly to the AD670.
These types of transducers typically produce 30 millivolts fullscale per volt of excitation. In the circuit shown in Figure IS,
the AD670 is connected directly to a Data Instruments model
JP-20 load cell. The ADS84 programmable voltage reference is
used along with an AD741 op-amp to provide the ± 2.SV
excitation for the load cell. The output of the transducer will be
± IS0mV for a force of ±20 pounds. The AD670 is configured
for the ± 128 millivolt range. The resolution is then approximately
2.1 ounces per LSB over a range of ± 17 pounds. Scaling to
exactly 2 ounces per LSB can be accomplished by trimming the
reference voltage which excites the load cell.
An AD7S02 dual 4-channel MUX appears in Figure 16 multiplexing four differential signals to the AD670. The AD7S02's
decoded address is gated with the microprocessor's write signal
to provice a latching strobe at the flip-flops. A write cycle to the
AD7S02's address then latches the two LSBs of the data word
thereby selecting the input channel for subsequent conversions.
+15
GND
-15
A+
AB+
B-
c+
+12V
c0+
0-
OO>--_":'='--h
01}----I
Figure 16. Multiplexed Analog Inputs to AD670
Figure 15. AD670 Load Cell Interface
MULTIPLEXED INPUTS
Most data acquisition systems require the measurement of
several analog signals. Multiple AID converters are often used to
digitize these inputs, requiring additional preamplification and
buffer stages per channel. Since these signals vary slowly, a
differential MUX can multiplex inputs from several transducers
into a single AD670. And since the AD670's signal-conditioning
capability is preserved, the cost of several ADCs, differential
amplifiers, and other support components can be reduced to
that of a single AD670, a MUX, and a few digital logic gates.
3-78 ANALOG-TO-DIGITAL CONVERTERS
SAMPLED INPUTS
For those applications where the input signal is capable of slewing
more than 1/2LSB during the AD670's 10""s conversion cycle,
the input should be held constant for the cycle's duration. The
circuit shown in Figure 17 uses a CMOS switch and two capacitors
to samplelhold the input. The AD670's STATUS output, once
inverted, supplies the samplelhold (SIH) signal.
A convert command applied on the CE, CS OR RiW lines will
initiate the conversion. The AD670's STATUS output, once
inverted, supplies the samplelhold signal to the CD4066. The
CD4066 CMOS switch shown in Figure 17 was chosen for its
fast transition times, low on-resistance and low cost. The control
input's propagation delay for switch-closed to switch-open should
remain less than ISOns to ensure that the sample-to-hold transition
occurs before the first bit decision in the AD670.
AD670
+sv
+sv
07
D.
OS
IBM PC
CARD SLOT
D'
03
02
01
DO
lOR
lOW
AEN
A9
a
Aa
7
A6
.,.
B13
All
J
Figure 17. Low Cost Sample-and-Hold Circuit for AD670
The fast conversion time and differential and common-mode
capabilities of the AD670 permit this simple sample-hold design
to perform well with low sample-ta-hold offset, droop rate of
about 401LV/1L8 and acquisition time under IlLS. The effective
aperture time of the AD670 is reduced by about 2 orders of
magnirude with this circuit, allowing frequencies to be converted
up to several kilohertz.
While no input anti-aliasing filter is shown, filtering will be
necessary to prevent output errors if higher frequencies are
present in the input signal. Many practical variations are possible
with this circuit, including input MUX control, for digitizing a
number of AC channels.
IBM PC INTERFACE
The AD670 appears in Figure 18 interfaced to the IBM PC.
Since the device resides in 1/0 space, its address is decoded
from only the lower ten address lines and must be gated with
AEN (active low) to mask out interoal (DMA) cycles which use
the same 110 address space. This active low signal is applied to
CS. AO, meanwhile, is reserved for the RiW input. This places
2
1
~
1
-
A
0
'" 0R
E
AI
This samplelhold approach makes use of the differential capabilities
of the AD670. Because 500pF hold capacitors are used on both
VIN + and VIN - inputs, the droop rate depends only on the
offset current of the AD670, typically 20nA. With the matched
500pF capacitors, the droop rate is 401LV/jLS. The input will
then droop only OAmV (OALSB) during the AD670's IOjLS
conversion time. The differential approach also minimizes pedestal
error since only the difference in charge injection between the
two switches results in errors at the AID.
3
A3
A2
= Cz = 500pF POLVSTYRENE ::!: 2.5%
Since settling to 1I2LSB at 8-bits of resolution requites 6.2 RC
time constants, the 500pF hold capacitors and CD4066's 3000
on-resistance yield an acquisition time of under IlLS, assuming a
low impedance source.
S
A'
A.
A9 A22
C,
•
•
A7
AO
A30
A31
-V ~
-
0.7
DB.
DBS
DB.
DB3
0.2
0.,
DBO
BPO/UPO
FORMAT
CE
AD670
0
E
g - os
0
E
RliN
Figure 18. IBMPClnterfacetoAD670
the AD670 in two adjacent addresses; one for starting the conversion and the other for reading the result. The lOR and lOW
signals are then gated and applied to CE, while the lower two
data lines are applied to FORMAT and BPOIUPO inputs to
provide software programmable input formats and output
coding.
In BASIC, a simple OUT ADDR, WORD command initiates a
conversion. While the upper six bits of the data WORD are
meaningless, the lower two bits define the analog input format
and digital output coding according to Table IV. The data is
available ten microseconds later (which is negligible in BASIC)
and can be read using INP (ADDR + I). The 3-line subroutine
in Figure 19, used in conjunction with the interface of Figure
18, converts an analog input within a bipolar range to an offset
binary coded digital word.
NOTE: Due to the large number of options that may be installed
in the PC, the 1/0 bus loading should be limited to one Schottky
TTL load. Therefore, a buffer/driver should be used when
interfacing more than two AD670's to the 1/0 bus.
DATA
INPUT FORMAT
OUTPUT CODING
o
Unipolar
Bipolar
Unipolar
Bipolar
Straight Binary
Offset Binary
2's Complement
2's Complement
I
2
3
Table IV.
10
20
30
OUT &H310.1
ANALOGIN=INP (&H311)
RETURN
'INITIATE CONVERSION
'READ ANALOG INPUT
Figure 19. Conversion Subroutine
ANALOG-TO-DIGITAL CONVERTERS 3-79
II
3-80 ANA LOG-TO-DIGITAL CONVERTERS
~ANALOG
WDEVICES
8-Bit AID Converter
AD673* I
FEATURES
Complete I-Bit AID Converter with Reference, Clock
and Comparator
30"s Maximum Conversion Time
Full I- or 16-Bit Microprocessor Bus Interface
Unipolar and Bipolar Inputs
No Missing Codes Over Temperature
Operates on +5V and -12V to -15V Supplies
AD673 FUNCTIONAL BLOCK DIAGRAM
v+
v-
DIGITAL
COMMON
CONVERT
MSB
DB7
OBI
a·BIT
CURRENT
OUTPUT
8·BIT
DB.
SAR
DAC
OM
DB3
r--,
BIPOLAR
OfFSET CONTROL
DB>
I INT I
: CLOCK:
DB'
L. __ .J
DB.
LSB
...IlAIA.
ENABLE
PRODUCT DESCRIPTION
The AD673 is a complete 8-bit successive approximation analog-todigital converter consisting of a DAC, voltage reference, clock,
comparator, successive approximation register (SAR) and 3 state
output buffers-a1l fabricated on a single chip. No external components are required to perform a full accuracy 8-bit conversion
in 20",s.
The AD673 incorporates advanced integrated circuit design and
processing technologies. The successive approximation function
is implemented with I2L (integrated injection logic). Laser trimming of the high stability SiCr thin fUm resistor ladder network
insures high accuracy, which is maintained with a temperature
compensated sub-surface Zener reference.
Operating on supplies of + SV and -12V to -lSV, the AD673
will accept analog inputs of 0 to + 10V or - SV to + SV. The
trailing edge of a positive pulse on the CONVERT line initiates
the 20",s conversion cycle. DATA READY indicates completion
of the conversion.
The AD673 is available in two versions. The AD673J as specified
over the 0 to + 70·C temperature range and the AD673S guarantees
± ~LSB relative accuracy and no missing codes from - SS·C to
+ 12SOC.
~_t:::::::::::::::::::~
READY
__A_D6_7_3____.J
PRODUCT HIGHLIGHTS
1. The AD673 is a complete 8-bit AID convener. No external
components are required to perform a conversion.
2. The AD673 interfaces to many popular microprocessors
without external buffers or peripheral interface adapters.
3. The device offers true 8-bit accuracy and exhibits no missing
codes over its entire operating temperature range.
4. The AD673 adapts to either unipolar (0 to + 10V) or bipolar
( - SV to + SV) analog inputs by simply grounding or opening
a single pin.
5. Performance is guaranteed with
supplies.
+ SV and -12V or -lSV
Two package confIgurations are offered. All versions are also
offered in a 20-pin hermetically sealed ceramic DIP. The AD673J
is also available in a 20-pin plastic DIP.
*Protectecl by
and 4,400,690
u.s. Patent Nos. 3,940,760; 4,213,806; 4,136,349; 4,400,689;
ANALOG-TO-OIGITAL CONVERTERS 3-81
•
SPECIFICATIONS
(1A=25"&, V+=+5V, V-=-l2V or -l5V, allvoJtages measured with respect to digital common,
unless otheIwisa indicated)
Model
Min
RESOLUTION
AD673J
Typ
Max
Min
AD673S
Typ
TA=TmintoTmax
FULL SCALE CALIBRATION2
±2
±2
Units
Bits
±112
±1/2
±112
±112
RELATIVE ACCURACY, I
Max
8
8
LSB
LSB
LSB
UNIPOLAR OFFSET
±112
±112
LSB
BIPOLAR OFFSET
±1I2
±1/2
LSB
DIFFERENTIAL NONLINEARlTY,'
TA=TmintoTmax
8
8
TEMPERATURE RANGE
0
Bits
Bits
8
8
+125
"C
±1
±1
±2
±1
±1
±2
LSB
LSB
LSB
±2
±2
LSB
±2
±2
±2
±2
LSB
LSB
7.0
kO
+10
+5
V
V
+70
TEMPERATURE COEFFICIENTS
Unipolar Offset
Bipolar Offset
Full Scale Calibration2
POWER SUPPLY REJECTION
Positive Supply
+4.5",V+",+S.5V
Negative Supply
-15. 75V",V - '" -14.25V
-12.6V"'V - '" -11.4V
5.0
-55
7.0
3.0
+10
+5
0
-5
5.0
ANALOG INPUT IMPEDANCE
3.0
ANALOG INPUT RANGES
Unipolar
Bipolar
0
-5
OUTPUT CODING
Unipolar
Bipolar
Positive True Binary
Positive True Offset Binary
Positive True Binary
Positive True Offset Binary
3.2
3.2
LOGIC OUTPUT
Output Sink Current
(VOUT = O.4V max, T min to T ....)
Output Source Current'
(VOUT = 2.4V min, T min to T...,.)
Output Leakage
LOGIC INPUTS
Input Current
Logic"l"
rnA
0.5
0.5
±40
±40
±100
±100
,.A
0.8
V
V
2.0
2.0
Logic "0"
0.8
rnA
",A
CONVERSION TIME, TAand
T min toT max
10
20
30
JO
20
30
",s
POWER SUPPLY
V+
V-
+4.5
-11.4
+5.0
-IS
+7.0
-16.5
+4.5
-11.4
+5.0
-IS
+7.0
-16.5
V
V
IS
9
20
IS
9
20
15
rnA
rnA
OPERATING CURRENT
V+
V-
15
NOTES
IRelative accuracy is defmed as the deviation of the code transition points from the ideal transfer point on a
straight line from tbe zero to the full scale of tbe device.
2Full scale calibration is guaranteed trimmable to zero with an external 200n potentiometer in place of the lSn
fixed resistor.
Full scale is defined as 10 volts minus lLSB, or 9.961 volts.
3Defined as the resolution for which no missing codes will occur.
"The data oUlputlines have active pull-ups to source O.SmA. The :;:D=-=AC:;T;:-;A:-::::REA="'D:;;Y line is open collector witb
a nominal 6k.n internal pull-up resistor.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those
shown in boldface are tested on all production units.
3-82 ANALOG-TO-OIGITAL CONVERTERS
AD673
ABSOLUTE MAXIMUM RATINGS
AD673 ORDERING GUIDE
V + to Digital Common . . . . . . .
V - to Digital Common . . • • • . .
Analog Common to Digital Common
Analog Input to Analog Common . .
ControlInputs . • . . . . . . . . . .
Digital Outputs (High Impedance State) .
Power Dissipation . . . . . . . . .
.. Oto +7V
o to -16.5V
::tIV
. ::t 15V
o to V+
o toV+
800mW
FUNCTIONAL DESCRIPTION
The SAR drives DR low to indicate that the conversion is complete
and that the data is available to the output buffers. DATA
ENABLE can then be activated to enable the 8-bits of data
desired. DATA ENABLE should be brought high prior to the
v-
DIGITAL
COMMON
CONVERT
MSB
8·81T
CURRENT
OUTPUT
DAC
Temperature
Range
OlD +70'C
Oto
+ 70°C
- 55'C to + 125'C
OlD +70'C
Package Options*
Plastic DIP (N-20)
Ceramic DIP(D-20)
Ceramic DIP (D-20)
PLCC(P-20A)
*See Section 14 for package outline information.
>---t- DB7
>+---t- DB6
>+---t- DB'
I-BIT
SAR
r--'
t--I>+-+
t--I>+-+
•
state.
The temperature compensated buried Zener reference provides
the primary voltage reference to the DAC and ensures excellent
stability with both time and temperature. The bipolar offset
input controls a switch which allows the positive bipolar offset
current (exactly equal to the value of the MSB less V2LSB) to be
injected into the summing ( + ) node of the comparator to offset
the DAC output. Thus the nominal 0 to + 10V unipolar input
range becomes a - 5V to + SV range. The SkO thin fllm input
resistor is trimmed so that with a full scale input signal, an
input current will be generated which exactly matches the DAC
output with all bits on.
UNIPOLAR CONNECTION
The AD673 contains all the active components required to
perform a complete AID conversion. Thus, for many applications,
all that is necessary is connection of the power supplies ( + SV
and - 12V to - ISV), the analog input and the convert pulse.
However, there are some features and special connections which
should be considered for achieving optimum performance. The
functional pin-out is shown in Figure 2.
The standard unipolar 0 to + lOY range is obtained by shorting
the bipolar offset control pin (pin 16) to digital common
(pin 17).
DB4
DB3
t;>;--;--DB2
L~Jt--I'->+-;- 081
LSB DBO
liNT:
BIPOLAR
OFFSET CONTROL
Relative
Accuracy
±1I2LSBmax
±1I2LSBmax
± 1I2LSBmax
± 1/2LSBmax
next conversion to place the output buffers in the high impedance
A block diagram of the AD673 is shown in Figu~...!: The positive
CONVERT pulse must be at least 500ns wide. DR goes high
within 1.51Ls after the leading edge of the convert pulse indicating
that the intemallogic has been reset. The negative edge of the
CONVERT pulse initiates the conversion. The internal 8-bit
current output DAC is sequenced by the integrated injection
logic (I 2 L) successive approximation register (SAR) from its
most significant bit to least significant bit to provide an output
current which accurately balances the input signal current through
the 5k.O resistor. The comparator determines whether the addition
of each successively weighted bit current causes the DAC current
sum to be greater or less than the input current; if the sum is
more, the bit is turned off. After testing all bits, the SAR contains
a 8-bit binary code which accurately represents the input signal
to within (0.05% of full scale).
Vi-
Model
AD673JN
AD673]D
AD673SD
AD673JP
3
DIGITAL COMMON
BIPOLAR OFFSET
I---l>+--+ DBO
ANALOG COMMON
ANALOG IN
vMSB DB7
~-1:::::::::::::::::::~
READY
_____J
ADe73
Figure 1. AD673 Functional Block Diagram
.PINS 1 & 2 ARE INTERNALLY CONNECTED TO TEST POINTS
AND SHOULD BE LEFT FLOATING
Figure 2. AD673 Pin Connections
ANALOG-TO-OIGITAL CONVERTERS 3-83
Full Scale Calibration
The 5k.o thin film input resistor is laser trimmed to produce a
current which matches the full scale current of the internal
DAC-plus about 0.3%-when an analog input voltage of 9.961
volts (10 volts - ILSB) is applied at the input. The input resistor
is trimmed in this way so that if a fme trimming potentiometer
is inserted in series with the input signal, the input current at
the full scale input voltage can be trimmed down to match the
DAC full scale current as precisely as desired. However, for
many applications the nominal 9.961 volt full scale can be achieved
to sufficient accuracy by simply inserting a ISO resistor in series
with the analog input to pin 14. Typical full scale calibration
error will then be within ± 2LSB or ± 0.8%. If more precise
calibration is desired, a 2000 trimmer should be used instead.
Set the analog input at 9.961 volts, and set the trimmer so that
the output code is just at the transition between 111111 10 and
11111111. Each LSB will then have a weight of 39.06mV. If a
nominal full scale of 10.24 volts is desired (which makes the
LSB have a weight of exactly 4O.0mV), a 1000 resistor and a
1000 trimmer (or a 2000 trimmer with good resolution) should
be used. Of course, larger full scale ranges can be arranged by
using a larger input resistor, but linearity and full scale temperature
coefficient may be compromised if the external resistor becomes
a sizeable percentage of 5kO. Figure 3 illustrates the connections
required for full scale calibration.
Figure 5 shows the nominal transfer curve near zero fot an
AD673 in unipolar mode. The code transitions are at the edges
of the nominal bit weights. In some applications it will be preferable
to offset the code transitions so that they fall between the nominal
bit weights, as shown in the offset characteristics.
r--
OUTPUT
I
CODE
00000100
I
00000011
00000010
00000001
00000000 ~-+~f--+--+-t--
160
2.0
ov 40
INPUT VOLTAGE -mY
NOMINAL CHARACTERISTICS
REFERRED TO ANALOG COMMON
OUTPUT
CODE
r-I
00000100
00000011
00000010
00000001
00000000 I-L-+--t-t---+~-
240
160
ov 40
INPUT VOLTAGE -mV
OFFSET CHARCTERISTICS WITH
10n IN SERIES WITH ANALOG COMMON
Figure 5. ADB73 Transfer Curve - Unipolar Operation
(Approximate Bit Weights Shown for Illustration, Nominal
Bit Weights % 39.0BmV)
Figure 3. Standard ADB73 Connections
Unipolar Offset Calibration
Since the Unipolar Offset is less than ± VzLSB for all versions
of the AD673, most applications will not require trimming.
Figure 4 illustrates two trimming methods which can be used if
greater accuracy is necessary.
Figure 4a shows how the converter zero may be offset to correct
for initial offset and/or input signal offsets. As shown, the circuit
gives approximately symmetrical adjustment in unipolar mode.
r-------------~A~
AD673
.......-.--.....---1 Aoo..
R1
1Cln
R2
7.5k
StGNAL COMMON
AD673
R1
R3
4.7k
R'
10k
SIGNAL COMMON
+15V
-15V
'h BIT ZERO OFFSET
ZERO OFFSET AOJ
Figure
4a.
Figure 4b.
Figure 4. Unipolar Offset Trimming
3-84 ANALOG-TO-DIGITAL CONVERTERS
This offset can easily be ac:c:omplished as shown in Figure 4b.
At balance (after a conversion) approximately 2mA flows into
the Analog Common terminal. A lOll resistor in series with this
terminal will result in approximately the desired Yz bit offset of
the transfer characteristics. The nominal2mA AnalQg Common
current is not closely controlled in manufacture. If high ac:c:uracy
is required, a 200 potentiometer (connected as a rheostat) can
be used as R1. Additional negative offset range maybe obtained
by using larger values of RI. Of course, if the zero transition
point is changed, the full scale transition point will also move.
Thus, if an offset of if2LSB is introduced, full scale trimming as
described on the previous page should be done with an analog
input of 9.941 volts.
NOTE: During a conversion, transient currents from the Analog
Common terminal will disturb the offset voltage. Capacitive
decoupling should not be used around the offset network. These
transients will settle appropriately during a conversion. Capacitive
dec:oupling will "pump up" and fail to settle resulting in conversion
errors. Power supply decoupling, which returns to analog signal
common, should go to the signal input side of the resistive
offset network •
Applying the AD673
BIPOLAR CONNECTION
SAMPLE-HOLD AMPLIFIER CONNECTION TO TIlE
To obtain the bipolar - SV to + SV range with an offset binary
output code, the bipolar offset control pin is left open.
AD673
A - s.oo volt signal will give a 8-bit code of 00000000; an input
of 0.00 volts results in an output code of 10000000 and + 4.961
volts at the input yields the 11111111 code. The nominal transfer
curve is shown in Figure 6.
OUTPUT
CODE
10000 010
10000001
10000000
01111 111
01' 11"0
I
I
r--
--)£-__ oJI
I
:
-100 -80 -40
0 +40 +80 +160
INPUT VOLTAGE - mV
Figure 6. AD673 Transfer Curve-Bipolar Operation
Note that in the bipolar mode, the code transitions are offset
~LSB such that an input voltage of 0 volts - SmV to + 3SmV
yields the code representing zero (10000000). Each output code
is then centered on its nominal input voltage.
Full Scale Calibration
Full Scale Calibration is accomplished in the same manner as in
Unipolar operation except the full scale input voltage is + 4.61
volts.
Many situations in high-speed acquisition systems or digitizing
rapidly changing signals require a sample-hold amplifier (SHA)
in front of the A-D converter. The SHA can acquire and hold a
signal faster than the converter can perform a conversion. A
SHA can also be used to accurately define the exact point in
time at which the signal is sampled. For the AD673, a SHA can
also serve as a high input impedance buffer.
Figure 8 shows the AD673 connected to the ADS82 monolithic
SHA for high speed signal acquisition. In this confJgUration, the
•
ADS82 will acquire a 10 volt signal in less than 10Jl.S with a
droop rate less than lOO....V/ms.
DR goes high after the conversion is initiated to indicate that
reset of the SAR is complete. In Figure 8 it is also used to put
the ADS82 into the hold mode while the AD673 begins its
conversion cycle. (The ADS82 settles to final value well in advance
of the first comparator decision inside the AD673).
DR goes low when the conversion is complete placing the ADS82
back in the sample mode. Configured as shown in Figure 8, the
next conversion can be initiated after a 10....s delay to allow for
signal acquisition by the ADS82.
Observe carefully the ground, supply, and bypass capacitor
connections between the two devices. This will minimize ground
noise and interference during the conversion cycle.
+5V
ANALOG V+
IN
r-:;;;--;:::::;:===+--~ CONVERT
Negative FuB Seale Calibration
The circuit in Figure 4a can also be used in Bipolar operation to
offset the input voltage (nominally - SV) which results in the
00000o 00 code. R2 should be omitted to obtain a symmetrical
range.
5 VOLT
COM
AD673
The bipolar offset control input is not directly TTL compatible
but a TTL interface for logic control can be constructed as
shown in Figure 7.
V-
-15V
15 VOL T
COM
Figure 8. Sample-Hold Interface to the AD673
Figure 7. Bipolar Offset Controlled by Logic Gate
Gate Output = 1 Unipolar Q-10V Input Range
Gate Output = 0 Bipolar :± 5V Input Range
ANALOG-TO-DIGITAL CONVERTERS 3-85
GROUNDING CONSIDERATIONS
The AD673 provides seParate Analog and Digital Common
connections. The circuit will operate properly with as much as
±200mV of common mode voltage between the two commons.
This permits more flexible control of system common bussing
and digital and analog returns.
In normal operation, the Analog Common terminal may generate
transient currents of up to 2mA during a conversion. In addition
a static current of about 2mA will flow into Analog Common in
the unipolar mode after a conversion is complete. The Analog
Common current will be modulated by the variations in input
signal.
The absolute maximum voltage rating between the two commons
is ± I volt. It is recommended that a parallel pair of back-to-back
protection diodes be connected between the commons if they
are not connected locally.
CONTROL AND TIMING OF THE AD673
The operation of the AD673 is controlled by two inputs: CONVERT and DATA ENABLE.
Starting a Conversion
The conversion cycle is initiated by a positive-going CONVERT
pulse at least sOOns wide. The rising edge of this pulse resets
the internal logic, clears the result of the previous conversion,
and sets DR high. The falling edge of CONVERT begins the
conversion cycle. When conversion is completed DR returns
low. During the conversion cycle, DE should be held high. If
DE goes low during a conversion, the data output buffers will
be enabled and intermediate conversion results will be present
on the data output pins. This may cause bus conflicts if other
devices in a system are trying to use the bus.
.+V'
~
t~D~ --l,
~.
CONVERT
tc
L..
~
:
TIMING SPECIFICATIONS
Symbol Min
Parameter
Typ
Mu:
Unita
CONVERT Pulse Width
tcs
DR Delay from CONVERT tose
Conversion Time
tc
500
10
1
20
1.5
30
ns
fJ.S
j.Ls
Data Access Time
Data Valid after DE
High
too
0
ISO
250
ns
tHO
SO
Output Float Delay
tHL
100
200
ns
MICROPROCESSOR INTERFACE CONSIDERATIONS GENERAL
When an analog-to-digital convener like the AD673 is interfaced
to a microprocessor, several details of the interface must be
considered. First, a signal to stan the convener must be generated;
then an appropriate delay period must be allowed to pass before
valid conversion data may be read. In most applications, the
AD673 can interface to a microprocessor system with little or no
external logic.
The most popular control signal configuration consists of decoding
the address assigned to the AD673, then gating this signal with
the system's WR signal to generate the CONVERT pulse, and
gating it with RD to enable the output buffers. The use of a
memory address and memory WR and RD signals denotes "memory-mapped" 110 interfacing, while the use of a separate 1/0
address space denotes "isolated 1/0" interfacing.
Figure 11 shows a generalized diagram of the control logic for
an AD673 interfaced to an 8-bit data bus, where an address
ADC ADDR has been decoded. ADC ADDR stans the convener
when written to (the actna! data being written to the convener
does not matter) and contains the high byte data during read
operations.
DB1
DB1
~~VOl
DR
ns
:
.
8·BIT DATA BUS
---.---
DBO
DBO
Figure 9. Convert Timing
Reading the Data
The three-state data output buffers is enabled by DE. Access
time of these buffers is typically ISOns (250 maximum). The
Data outputs remain valid until sOns after the enable signal
returns high, and are completely into the high-impedance state
lOOns later.
HIGH
IMPEDANCE
DRD-DB1
---';;';';"-'--V;~:::~~::j._--,
Figure 10. Read Timing
3-86 ANALOG-TO-DIGITAL CONVERTERS
"p
wA"_A'{
AD
~
ADDR
BUS
ADe ADDR
;:::l...)o-
CONVERT
DECODING
ADDRE"J
lOGIC
~
DE
(SEETEXTI_
illi
Figure 11. General AD673 Interface to 8-Bit
Microprocessor
AD6n
Interfacing to the AD673
In systems where this read-write interface is used, at least 30
microseconds (the maximum conversion time) must be allowed
to pass between starting a conversion and reading the results.
This delay or "timeout" period can be implemented in a short
software routine such as a countdown loop, enough dummy
instructions to consume 30 microseconds, or enough actual
useful instructions to consume the required time. In tightly-timed
systems, the DR line may be read through an external three-state
buffer to determine precisely when a conversion is complete.
Higher-speed systems may choose to use DR to signal an interrupt
to the processor at the end of a conversion.
ADC ADOR
ADDRESS
AOC ADOR
~~--------~~~----
8US
Wil~
CONVERT
DR
~n--
t
-:=r::-t'---~~L
CONVERT Pulse Generation
The AD673 is tested with a CONVERT pulse width of 500ns
and will typically operate with a pulse as short as 300ns. However,
some microprocessors produce active WR pulses which are
shorter than this. Either of the circuits shown in Figure 13 can
be used to generate an adequate CONVERT pulse for the AD673.
In both circuits, the short low-going WR pulse sets the CONVERT
line high through a flip-flop. The rising edge of DR (which
signifies that the internal logic has been reset) resets the flip-flop
and brings CONVERT low, which starts the conversion.
Note that tosc is slightly longer when the result of the previous
conversion contains a logic I on the LSB. This means that the
actual CONVERT pulse generated by the circuits in Figure 13
will vary slightly in width.
P-.......--~ CONVERT
________
Wil----,
AD673
AD673
Figure 13a. Using 74LSOO
Figure 13b. Using 112 74LS74
Figure 12. Typical AD673 Timing Diagram
ANALOG-TO-OIGITAL CONVERTERS 3-87
II
3-88 ANALOG-TO-OIGITAL CONVERTERS
Complete
12-Bit AID Converter
AD674A* I
~ANALOG
WOEVICES
FEATURES
Complete 12-Bit AID Converter with Reference
and Clock
Faster Version of AD574A
8- and 16-Bit Bus Interface
No Missing Codes Over Temperature
15 ...s max Conversion Time
:!:: 12V and :!:: 15V Operation
Unipolar and Bipolar Inputs
DIP Package
AD674AFUNCTIONAL BLOCK DIAGRAM
+5VSUPPlY
VLOGIC
DATA MODE snECT
•
DBn
12/&
CHIPSELE~
MSB
J
BYTE ADDRESSJ
SHORT CYCLE
C
Ao
READfCONVERT
RIC
CHIP ENABLE
eE
+12/+15V SUPPLY
Vee
DIGITAl.
DATA
7
+10V REFERENCE
OUTPUTS
REF OUT
ANALOG COMMON
Ae
REFERENce INPUT
REF IN
-12J-15VSUPPLY
PRODUCT DESCRIPTION
The AD674A is a complete 12-bit successive-approximation
analog-to-digital converter with three-state output buffer circuitry
for direct interface to an 8- and 16-bit microprocessor bus. A
high-precision voltage reference and clock are included on-chip,
and the circuit requires only power supplies and control signals
for operation.
The AD674A is pin compatible with the industry-standard
ADS74A but offers faster conversion time and bus-access speed.
The AD674A design is implemented with two LSI chips each
containing both analog and digital circuitry, resulting in the
maximum performance and flexibility at the lowest cost. The
chips are laser trimmed at the wafer stage to obtain full rated
performance without external trims.
The AD674A is available in six different grades. The AD674AJ,
K, and L grades are specified for operation over the 0 to + 70°C
temperature range. The AD674AS, T, and U are specified for
the - 55°C to + 125°C range. All grades are available in a 28-pin
hermetically sealed ceramic DIP.
The S, T, and U grades are also available with optional processing
to MIL-STD-883C Class B in 28-pin DIP. The Analog Devices
Military Products Databook should be consulted for details on
1883B testing of the AD674A.
V"
BIPOLAR OFFSET
BIPOFF
IOV SPAN INPUT
10VtN
20V SPAN INPUT
OSO
LSB
IS ~GITAL COMMON
2OVON
PRODUCT HIGHLIGHTS
1. The AD674A interfaces to most 8- or 16-bit microprocessors.
Multiple-mode three-state output buffers connect directly to
the data bus while the read and convert commands are taken
from the control bus. The 12 bits of output data can be read
either as one 12-bit word or as two 8-bit bytes (one with 8
data bits, the other with 4 data bits and 4 trailing zeros).
2. The precision, laser-trimmed scaling and bipolar offset resistors
provide four calibrated ranges: 0 to + 10 and 0 to + 20 volts
unipolar, - 5 to + 5 and - 10 to + 10 volts bipolar. Typical
bipolar offset and full-scale calibration errors of ±0.1% can
be trimmed to zero with one external component each.
3. The internal buried zener reference is trimmed to 10.00 volts
with 1% maximum error and ISppmfOC typical T.C. The
reference is available externally and can drive up to 2.0mA
beyond the requirements of the reference and bipolar offset
resistors.
*Protected by U.S. Patent Nos. 3,803,590; 4,213,806; 4,511,413;
HE 28,633.
ANALOG-TO-DIGITAL CONVERTERS 3-89
SPECIFICATIONS
=25ac with Vee = +15Vor +12V, VI.08IC
unless otherwise indica1lld)
(@
AD674AJ
Typ
= +5V,VEE = -15V or -12V
AD674AK
Typ
Max
UailS
12
12
12
Bits
LINEARITY ERROR
::1:1
::1:1
::1:112
::1:112
::1:112
::1:112
LSB
LSB
Min
TmintoTmax
Max
Min
Max
AD674AL
Typ
RESOLUTION
Model
Min
DIFFERENTIAL LINEARITY ERROR
(Minimum. resolution for which no
missing codes are guaranteed)
Tmia to TJIJIX
12
11
12
Bits
UNIPOLAR OFFSET (Adjustable to zero)
::1:2
::1:2
::1:2
LSB
BIPOLAR OFFSET (Adjustable to zero)
:1:10
::1:4
::1:4
LSB
0.25
%ofF.S.
+70
'C
FULL-SCALE CALIBRATION ERROR
(with flXCd son resistor from REF OUT to REF IN)
(Adjustable to zero)
TEMPERATURE RANGE
0.1
0
0.25
+70
0.1
0
0.25
+70
0.1
0
TEMPERATURE COEFFICIENTS
(Using internal reference)
Tmio to T_
Unipolar Offset
Bipolar Offset
Full-SealeCalibration
POWER SUPPLY REJECTION
Max change in Full Seale Calibration
Vee=ISV ±I.SVorI2V ±0.6V
VLOGlc=5V ±O.5V
VEE = -15V ± 1.5Vor - 12V ± 0.6V
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
-5
-10
0
0
3
6
5
10
::1:2(10)
:1:2(10)
::1:9(50)
::1:1(5)
::1:1(5)
::1:5(27)
±I (5)
::1:1(5)
::1:2(10)
LSB (ppm/"C)
LSB (ppmI"C)
LSB (ppmI"C)
::1:2
:1:112
::1:2
::1:1
::1:112
::1:1
::1:1
::1:112
::1:1
LSB
LSB
LSB
+5
+10
+10
+20
Volts
Volts
Volts
Volts
7
kn
kn
+5
+10
+10
+20
-5
-10
0
0
7
14
3
6
+5.5
+0.8
+100
+2.0
-0.5
-100
5
10
+5
+10
+10
+20
-5
-10
0
0
7
14
6
+5.5
+0.8
+100
+2.0
-0.5
-100
3
5
10
14
DIGITAL CHARACTERISTICS' (Tmin to T....,.)
Inputs
Logic "I" Voltage
Logic "0" Voltage
Current
+2.0
-0.5
-100
Capacitance
Outputs (DB I I-DBO, STS)
Logic "I" Vohase (l souRCE s500fI.A)
Logic "0" Voltage (I'INK s 1.6mA)
Leskase(DBII-DBO, Hisb-Z State)
Capacitance
5
5
+2.4
5
+2.4
+0.4
+20
-20
+2.4
+0.4
+20
-20
5
+5.5
+0.8
+100
"A
pF
Volts
+0.4
+20
Volts
+5.5.
+ 16.5
-16.5
Volts
30
2
18
40
5
29
mA
mA
mA
390
720
mW
10.0
10.1
2.0
Volts
-20
5
Volts
Volts
5
"A
pF
POWER SUPPLIES
Operating Range
VLOGIC
Vee
VEE
+4.5
+11.4
-11.4
+5.5
+ 16.5
-16.5
+4.5
+11.4
-11.4
+5.5
+16.5
-16.5
+4.5
+11.4
-11.4
Volts
Volts
OperatingCurrcut
30
2
kOGIC
Icc
IE.
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output current (available for externalloadsl'
(Extemalload should notchange during conversion)
9.9
30
2
18
40
18
40
5
29
390
720
390
720
10.0
10.1
2.0
10.0
10.1
2.0
9.9
5
29
9.9
NOTES
I Detailed Timing Specifications appear in the Timing Section.
2Thc reference should be buffered for operation on ± 12V supplies.
SpecifICations subject to change without nodce.
~90
ANALOG-TO-OIGITAL CONVERTERS
Specifications shown in boldface are tested on all production units at final electrical test. Results from tbose tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed, although only those shown in
boldface are tested on all production units.
mA
AD674A
AD674AS
Typ
Min
AD674AT
Typ
Min
AD674AU
Typ
Max
Units
RESOLUTION
12
12
12
Bits
LINEARITY ERROR
TmintoTmu
±1
±1
±1/2
±1
±112
±1
LSB
LSB
Model
j\tiD
Max
Max
DIFFERENTIAL LINEARITY ERROR
(Minimum resolution for which no
missing codes arc guaranteed)
Tmir.to Tmax
11
Bits
12
12
UNIPOLAR OFFSET (Adjustable to zero)
±2
±2
±2
LSB
BIPOLAR OFFSET (Adjustable to zero)
±10
±4
±4
LSB
FULL-SCALE CALIBRATION ERROR
(with fixed 500 resistor from REF OUT to REF IN)
(Adjustable to zero)
TEMPERATURE RANGE
0.1
-55
0.25
+ 125
TEMPERATURE COEFFICIENTS
(Using internal reference)
TmintoTmax
UnipolarOffsct
Bipolar Offset
Full·Scale Calibration
0.1
-55
0.25
+125
±2(5)
±4(10)
±20(50)
±1(2.5)
±2(5)
±10(25)
±2
±1/2
%2
%1
±1/2
±1
0.1
-55
0.25
%ofF.S.
+ 125
"C
±1(2.5)
±1(2.5)
±5(12.5)
LSB (ppmI"C)
LSB (ppml"C)
LSB (ppml"C)
POWER SUPPLY REJECTION
Max change in Full Scale Calibration
Vcc~15V ± 1.5Vorl2V ±0.6V
VLOGJc~5V ±O.5V
VEE ~ - 15V ± I.5Vor - 12V ± 0.6V
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
DIGITAL CHARACTERISTICS' (Tmi. to T_)
Inputs
Logic u 1" Voltage
Logic "0" Voltage
Current
Capacitance
Outputs(DBII-DBO,STS)
Logic "I" Voltage (I SQURCE"'500!LA)
Logic "0" Voltage (I SlNK'" 1.6rnA)
Leakage (DBII-DBO, High-Z State)
-5
-10
0
0
3
6
5
10
+2.0
-0.5
-100
+5
+10
+10
+20
-5
-10
0
0
7
14
3
+5.5
+0.8
+100
+2.0
-0.5
-100
6
5
-5
-10
0
0
7
14
3
+5.5
+0.8
+100
+2.0
-0.5
-100
+5
+10
+10
+20
Volts
Volts
Volts
Volts
7
14
kG
+5.5
+0.8
+100
+2.4
+0.4
+20
-20
5
5
10
LSB
LSB
LSB
5
+2.4
+0.4
+20
-20
6
5
+2.4
Capacitance
5
10
+5
+10
+10
+20
±1
±1/2
±1
+0.4
+20
-20
5
5
kO
Volts
Volts.
!LA
pF
Volts
Volts
!LA
pF
POWER SUPPLIES
Operating Range
VU)GIC
Vcc
VEE
Operating Current
I LOGIC
Icc
lEE
+4.5
+11.4
-11.4
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output current (available for cxremalloads)2
(External load should not change during conversion)
9.9
NOTES
IDctailed Timing Specifications appear in the Timing Section.
2Tbe reference should be buffered for operation on ± 12V supplies.
Specifications subject to change without notice.
+5.5
+16.5
-16.5
30
2
18
40
5
29
390
720
10.0
10.1
2.0
+5.5
+ 16.5
-16.5
+4.5
+11.4
-11.4
9.9
30
2
18
40
5
29
390
720
10.0
10.1
2.0
+5.5
+16.5
-16.5
Volts
Volts
2
18
40
5
29
rnA
rnA
rnA
390
720
mW
10.0
10.1
2.0
Volts
rnA
+4.5
+11.4
-11.4
30
9.9
Volts
Specifications shown in boldface are tested. on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed, although only those shown in
boldface are tested on all production units.
ANALOG-TO-DIGITAL CONVERTERS 3-91
I
ABSOLUTE MAXIMUM RATINGS·
Va:; to Digital Common . .
.0 to + 16.5V
VEE to Digital Common . .
.0 to -16.5V
VLOGIC to Digital Common
.. 0 to +7V
Analog Common to Digital Common
. . . . . ±lV
Digital Inputs to Digital Common
-0.5V to VLOGIC +0.5V
Analog Inputs to Analog Common
. . . . . . , VEE to Va:;
20VIN to Analog Common .
. . . . . . . . . . ±24V
REF OUT . . . . . . . . . . . . Indeflnite short to common
Momentary short to Vcc
Model
AD674AJD
AD674AKD
AD674ALD
AD674ASD
AD674ATD
AD674AUD
Temperature Range
Oto + 70°C
Oto + 70°C
Oto + 70°C
- 55°C to + 125°C
- 55°C to + 125°C
-55°Cto + 125°C
*See Section 14 for package outline information.
3-92 ANALOG-TO-DIGITAL CONVERTERS
Chip Temperature . . . . . .
Power Dissipation . . . . . .
Lead Temperature, Soldering
Storage Temperature . . . .
. .. 175°C
.. 825mW
300°C, 10see
-65°C to + 150°C
NOTES
"Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
AD674A ORDERING GUIDE
No Missing Codes
Linearity Error
(TmintoT......)
(TmintoT......)
±lLSB
11 Bits
±1I2LSB
12 Bits
±1I2LSB
12 Bits
11 Bits
±lLSB
12 Bits
±lLSB
±ILSB
12 Bits
Full Scale
T .C. (ppml"C)
50.0
27.0
10.0
50.0
25.0
12.5
Package
Option·
D-28
D-28
D-28
D-28
D-28
D-28
AD674A
DEFINITIONS OF SPECIFICATIONS
LINEARITY ERROR
Linearity error refers to the deviation of each individual code
from a line drawn from "zero" through "full scale". The point
used as "zero" occurs 1I2LSB (1.22mV for 10 volt span) before
the first code transition (all zeros to only the LSB "on"). "Full
scale" is defined as a level I 1I2LSB beyond the last code transition
(to all ones). The deviation of a code from the true straight line
is measured from the middle of each particular code.
The AD674AK, L, T, and U grades are guaranteed for maximum
nonlinearity of :±: 1I2LSB. For these grades, this means that an
analog value which falls exactly in the center of a given code
width will result in the correct digital output code. Values nearer
the upper or lower transition of the code width may produce the
next upper or lower digital output code. The AD674AJ and S
grades are guaranteed to :±: ILSB max error. For these grades,
an analog value which falls within a given code width will result
in either the correct code for that region or either adjacent one.
Note that the linearity error is not user adjustable.
DIFFERENTIAL LINEARITY ERROR (NO MISSING
CODES)
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence
as the analog input level is increased. Thus every code must
have a finite width. For the AD674AK, L, T, and U grades,
which guarantee no missing codes to 12-bit resolution, all 4096
codes must be present over the entire operating temperature
ranges. The AD674AJ and S grades guarantee no missing codes
to 11-bit resolution over temperature; this means that all code
combinations of the upper II bits must be present; in practice
very few of the 12-bit codes are missing.
UNIPOLAR OFFSET
The first transition should occur at a level 1I2LSB above analog
common. Unipolar offset is defined as the deviation of the actual
transition from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
maximum change of the transition point over temperature, with
or without external adjustment.
LEFT-JUSTIFIED DATA
The data format used in the AD674A is left-justified. This
means that the data represents the analog input as a fraction of
full scale, ranging from 0 to
to the left of the MSB.
:~~~.
This implies a binary point
FULL-SCALE CALIBRATION ERROR
The last transition (from 1111 Illi 1110 to Illl 1111 1111)
should occur for an analog value I 1I2LSB below the nominal
full scale (9.9963 volts for 10.000 volts full scale). The full-scale
calibration error is the deviation of the actual level at the last
transition from the ideal level. This error, which is typically
0.05 to 0.1 % of full scale, can be trimmed out as shown in
Figures 3 and 4. The full-scale calibration error over temperature
is given with and without the initial error trimmed out. The
temperature coefficients for each grade indicate the maximum
change in the full-scale gain from the initial value using the
internal IOV reference.
TEMPERATURE COEFFICIENTS
The temperature coefficients for full-scale calibration, unipolar
offset, and bipolar offset specify the maximum change from the
initial (25°C) value to the value at T min or T max.
POWER SUPPLY REJECTION
The standard specifications for the AD674A assume use of
+ 5.00 and:±: 15.00 or :±: 12.00V supplies. The only effect of
power supply error on the performance of the device will be a
small change in the full-scale calibration. This will result in a
linear change in all lower-order codes. The specifications show
the maximum full-scale change from the initial value with the
supplies at the various limits.
CODE WIDTH
A fundamental quantity for AID converter specifications is the
code width. This is defined as the range of analog input values
for which a given digital output code will occur. The nominal
value of a code width is equivalent to I least significant bit
(LSB) of the full-scale range or 2.44mV out of 10 volts for a
12-bit ADC.
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
QUANTIZATION UNCERTAINTY
Analog-to-digital converters exhibit an inherent quantization
uncertainty of :±: 1I2LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
ANALOG-TO-DIGITAL CONVERTERS 3-93
II
CIRCUIT OPERATION
The AD674A is a complete 12-bit AID converter which requires
no external components to provide the complete successive-approximation analog-to-digital conversion function. A block diagram of the AD674A is shown in Figure 1.
DRIVING THE AD674A ANALOG INPUT
The AD674A is a successive-approximation analog-ta-digital
converter. During the conversion cycle, the ADC input current
is modulated by the DAC test current at approximately a IMHz
rate. Thus it is important to recognize that the signal source
driving the AD674A must be capable of holding a constant
output voltage under dynamically-changing load conditions.
+5VSUPPLV
VLOGIC
DATAMODESEL,~
2
CHIPSELE;
3
the DAC. There are two Skn input scaling resistors to allow
either a 10 volt or 20 volt span. The 10kO bipolar offset resistor
is grounded for unipolar operation and connected to the 10 volt
reference for bipolar operation.
BYTEADDAESS/
SHORT CYCLE
4
Ao
FEEDBACK TO AMPLIFIER
REAOICONVERT
A/e
CHIP ENABLE
CE
-t12,.. ,5V SUPPLY
Vee
7
DIGITAL
DATA
OUTPUTS
"'OY REFERENCE
REF OUT
AD674A
ANALOG COMMON
AC
REFERENCE ~~:~
BIPOLAR
~r:~~~
10
t---i-+>
'IN IS MODULATED BY
CHANGES IN TEST CURRENT.
AMPLIFIER PULSE LOAD
RESPONSE LIMITED BY
OPEN LOOP OUTPUT IMPEDANCE.
12
ANALOG COMMON
tOY SPAN I~:: 13
20V SPAN I~!
14
15 ~GITAL COMMON
Figure 2. Op Amp - AD674A Interface
Figure 1. Block Diagram of AD674A 12-Bit A-to-D Converter
When the control section is commanded to initiate a conversion
(as described later), it enables the clock and resets the successiveapproximation register (SAR) to all zeros. Once a conversion
cycle has begun, it cannot be stopped or re-started and data is
not available from the output buffers. The SAR, timed by the
clock, will sequence through the conversion cycle and return an
end-of-convert flag to the control section. The control section
will then disable the clock, bring the output status flag low, and
enable control functions to allow data read functions by external
command.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most-significant-bit
(MSB) to least-signifIcant-bit (LSB) to provide an output current
which accurately balances the input signal current through the
SkO (or lOkO) input resistor. The comparator determines whether
the addition of each successively-weighted bit current causes the
DAC current sum to be greater or less than the input current;
if the sum is less, the bit is left on; if more, the bit is turned
off. After testing all the bits, the SAR contains a 12-bit binary
code which accurately represents the input signal to within
±1I2LSB.
The temperature-compensated buried zener reference provides
the primary voltage reference to the DAC and guarantees excellent
stability with both time and temperature. The reference is trimmed
to 10.00 volts ± 1%; it can supply up to l.SmA to an external
load in addition to the requirements of the reference input resistor
(O.SmA) and bipolar offset resistor (lmA) when the AD674A is
powered from ± lSV supplies. If the AD674A is used with
± 12V supplies, or if external current must be supplied over the
full temperature range, an external buffer amplifier is recommended. Any external load on the AD674A reference must
remain constant during conversion. The thin fIlm application
resistors are trimmed to match the full-scale output current of
3-94 ANALOG-TO-DIGITAL CONVERTERS
The closed-loop output impedance of an op amp is equal to the
open-loop output impedance (usually a few hundred ohms)
divided by the loop gain at the frequency of interest. It is often
assumed that the loop gain of a follower-connected op amp is
sufficiently high to reduce the closed-loop output impedance to
a negligibly small value, particularly if the signal is low frequency.
However, the amplifier driving an AD674A must either have
sufficient loop gain at IMHz to reduce the closed-loop output
impedance to a low value or have low open-loop output impedance.
This can be accomplished by using a wideband op amp, such as
the AD711.
If a sample-hold amplifier is required, the monolithic ADS8S is
recommended. Its output buffer will drive the AD674A input
directly.
SUPPLY DECOUPLING AND LAYOUT
CONSIDERATIONS
It is critically important that the AD674A power supplies be
filtered, well regulated, and free from high frequency noise. Use
of noisy supplies will cause unstable output codes. Switching
power supplies are not recommended for circuits attempting to
achieve 12-bit accuracy unless great care is used in filtering any
switching spikes present in the output. Remember that a few
millivolts of noise represents several counts of error in a 12-bit
ADC.
DecoupJing capacitors should be used on all power supply pins;
the + SV supply decoupling capacitor should be connected
directly from Pin 1 to Pin 15 (digital common) and the + Vee
and - VBE pins should be decoupled directly to analog common
(Pin 9). A suitable decoupJing capacitor is a 4.7 ....F tantalum
type in parallel with a O.l ....F disc ceramic type.
Circuit layout should attempt to locate the AD674A, associated
analog input circuitry, and interconnections as far as possible
from logic circuitry. For this reason, the use of wire-wrap circuit
construction is not recommended. Careful printed-circuit construction is preferred.
Analog Circuit Details - AD674A
UNIPOLAR RANGE CONNECTIONS FOR THE AD674A
The AD674A contains all the active components required to
perform a complete 12-bit AID conversion. Thus, for most
situations, all that is necessary is connection of the power supplies
(+ 5, + 12/ + 15 and -12/-15 volts), the analog input, and the
conversion initiation command, as discussed on the next page.
2
12/8
3
cs
OFFSET
4
Ao
R'
lOOk
5
RIC
6
CE
-121-15V
STS
MIDDLE BITS
20·23
AD674A
lOOk
28
HIGH BITS
24-27
LOW BITS
16-19
10 REF IN
8
'000
REF OUT
+5V
,
+15V
7
12 BIPOFF
OTO+l0V
ANALOG
1310VIN
INPUTS
14 20VIN
o TO +20V
;
9
ANA COM
-15V 11
DIG COM 15
If Pin 12 is connected to Pin 9, the unit will behave in this
manner, within specifications. If the offset trim (Rl) is used, it
should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give
approximately ± ISmV of offset trim range.
The full-scale trim is done by applying a signal I 1I2LSB below
the nominal full scale (9.9963 for a 10V range). Trim R2 to give
the last transition (1111 1111 1110 to 1111 1111 1111).
BIPOLAR OPERATION
The connections for bipolar ranges are shown in Figure 4. Again,
as for the unipolar ranges, if the offset and gain specifications
are sufficient, one or both of the trimmers shown can be replaced
by a son ± 1% fIXed resistor. The analog input is applied as for
the unipolar ranges. Bipolar calibration is similar to unipolar
calibration. First, a signal V,LSB above negative full scale
(-4.9988V for the ±SV range) is applied and RI is trimmed to
give the first transition (0000 0000 0000 to 0000 0000 0001).
Then a signal JlhLSB below positive full scale (+ 4.9963V for
the ± SV range) is applied and R2 trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
Figure 3. Unipolar Input Connections
All of the thin-fIlm application resistors of the AD674A are
trimmed for absolute calibration. Therefore, in many applications,
no calibration trimming will be required. The absolute accuracy
for each grade is given in the specification tables. For example,
if no trims are used, the AD674A guarantees ±2LSB max zero
offset error and ±0.2S% (10LSB) max full scale error. If the
offset trim is not required, Pin 12 can be connected directly to
Pin 9; the two resistors and trimmer for Pin 12 are then not
needed. If the full-scale trim is not required, a son ± 1% metal
film resistor should be connected between Pin 8 and Pin 10.
The analog input is connected between Pins 13 and 9 for a 0 to
+ IOV input range, between Pins 14 and 9 for a 0 to + 20V
input range. The AD674A easily accommodates input signals
beyond the supplies. For the 10 volt span input, the LSB has a
nominal value of 2.44mV; for the 20 volt span, 4.88mV. If a
10.24V range is desired (nominal 2.SmVlbit), the gain trimmer
(R2) should be replaced by a son resistor, and a 200n trimmer
inserted in series with the analog input to Pin 13 (for a full-scale
range of 20.48V (SmVlbit), use a soon trimmer into Pin 14).
The gain trim described below is now done with these trimmers.
The nominal input impedance into Pin 13 is Skn, and 10k{}
into Pin 14.
UNIPOLAR CALIBRATION
The connections for unipolar ranges are shown in Figure 3. The
AD674A is trimmed to a nominal 1I2LSB offset so that the
exact analog input for a given code will be in the middle of that
code (halfway between the transitions to the codes above and
below it). Thus, when properly calibrated, the first transition
(from 0000 0000 0000 to 0000 0000 0001) will occur for an
input level of + 1I2LSB (1.22mV for 10V range).
2
12iii
3
cs
4
Ao
5
RIC
6
CE
STS
24·21
MIDDLE BITS
20·23
AD674A
GAIN
LOW BITS
10.19
10 REF IN
8
OFFSET
28
HIGH BITS
REF OUT
+5V
,
+15V
7
12 RIP OFF
'5V
1310VIN
ANALOG
INPUTS
14 20VIN
"ov
~
9
ANACOM
-15V 11
DIG COM 15
Figure 4. Bipolar Input Connections
GROUNDING CONSIDERATIONS
The analog common at Pin 9 is the ground reference point for
the internal reference and is thus the "high quality" ground for
the AD674A; it should be connected directly to the analog
reference point of the system. In order to achieve all of the high
accuracy performance available from the AD674A in an environment of high digital noise content, it is required that the analog
and digital commons be connected together at the package. In
some situations, the digital common at Pin 15 can be connected
to the most convenient ground reference point; digital power
return is preferred.
ANALOG-TO-DIGITAL CONVERTERS 3-95
3
CONTROL LOGIC
The AD674A contains on-chip logic to provide conversion initiation and data read operations from signals commonly available
in microprocessor systems. Figure 5 shows the internal logic
circuitry of the AD674A.
-+___-'
STATUS - - _ , \ -_ _
high during a convert start, a shorter 8-bit conversion cycle
results. During data read opemtions, Ao determines whether
the three-state buffers containing the 8 MSBs of the conversion
result (Ao = 0) or the 4 LSBs (Ao = 1) are enabled. The 12ill
pin determines whether the output data is to be organized as
two 8-bit words (12i8 tied to DIGITAL COMMON) or a single
12-bit word (12/8 tied to VLOGI<:). In the 8-bit mode, the byte
addressed when Ao is high contains the 4 LSBs from the conversion
followed by four trailing zeroes. This orgauization allows the
data lines to be overlapped for direct interface to 8-bit buses
without the need for external three-state buffers.
An output signal, STS, indicates the status of the converter.
VALUE OFAO
AT LAST CONVERT
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
COMMAND
'DC'} NOTE
FROM1
'-...J----- Eoe,z
12/8
-===::::;+[>-~F~d
NOTE 1: WHENS'i'Aii'i' CONYeiif GOES LOW, THE EOC lEND OF CONVERSION} SIGNALS GO LOW.
EOca RETURNS HIGH AFTER AN 8-8IT CONVERSION CYCLE IS COMPLETE. AND EOC12
RETURNS HIGH WHEN ALL 12 BITS HAVE BEEN CONVERTED. THE EOC SIGNALS PREVENT
DATA FROM BEING READ DUFIlNG CONVERSIONS,
Figure 5. AD674A Control Logic
CE
~
~
1218
Ao Operation
0
X
X
1
X
X
X
X
X
X
None
None
1
1
0
0
0
0
X
X
0
1
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
1
0
1
1
X
Enable 12-Bit Parallel Output
1
1
0
0
1
1
0
0
0
1
Enable 8 Most Significant Bits
Enable4LSBs + 4 Tmiling Zeroes
The control signals CE, CS, and RIC control the operation of
the converter. The state of RIC when CE and CS are both asserted
detertuines whether a data read (RIC = I) or a convert (RIC =
0) is in progress. The register control inputs Ao and 12i8 control
conversion length and data format. If a conversion is started
with Ao low, a full 12-bit conversion cycle is initiated. If Ao is
Table I. AD674A Truth Table
TIMING
The AD674A is easily interfaced to a wide variety of microprocessors and other digital systems. Discussion of the tituing requirements of the AD674A control signals will provide the
system designer with useful insight into the operation of the device.
Figure 6 shows a complete timing diagram for the AD674A convert start opemtion. RIC should be low before both CE and CS
are asserted; if RIC is high, a read operation will momentarily
occur, possibly resulting in system bus contention. Either CE or
CS may be used to initiate a conversion. As shown in Figure 6,
CE is used. Note that CE includes one less propagation delay
than CS and is therefore the faster input.
Once a conversion is started and the STS line goes high, convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers cannot be enabled during
conversion.
CONVERT START TIMING-FULL CONTROL MODE
Symbol Parameter
CE
R/C~~====
Ao
ST"
____
JL+-~~~
----i:;;::=~
_________
__- - t c
tosc
DB11-DBO-----+-HIGH IMPEDANCE - - - - - -
FIgure 6. Convert Start Timing
3-96 ANALOG-TO-DIGITAL CONVERTERS
tDSC
tHEC
tssc
tHSC
tSRC
tHRC
tSAC
tH.'l.C
tc
STS Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High
RIC to CE Setup
RIC Low DuringCE High
Ao to CE Setup
AoJIa1id During CE High
Conversion Time
8-BitCycle
12-Bit Cvcle
Min
Typ
Max
Units
200
ns
ns
ns
ns
ns
ns
ns
ns
50
50
50
50
50
0
50
6
9
8
12
10
15
I.I.s
I.I.S
Analog Circuit Details - AD674A
Figure 7 shows the timing for data read operations. During data
read operations, access time is measured from the point where
CE and RIC both are high (assuming CS is already low).
In this mode, CE and 12/8 are wired high, CS and Ao are wired
low, and conversion is controlled by RIC. The three-state buffers
are enabled when RIC is high and a conversion starts when RIC
goes low. This gives rise to two possible control signals-a high
pulse or a low pulse. Operation with a low pulse is shown in
Figure 10. In this case, the outputs are forced into the highimpedance state in response to the falling edge of RIC and return
to valid logic levels after the conversion cycle is completed. The
STS line goes high 200ns after RIC goes low and returns low
600ns after data is valid.
CE
RIC
Ao
STS
DB11-DBO
"STAND-ALONE" OPERATION
The AD674A can be used in a "stand-alone" mode, which is
useful in systems with dedicated input ports available and thus
not requiring full bus interface capability.
If conversion is initiated by a high pulse as shown in Figure II,
1~~~-t-:---=-:-~3~S:=J
the data lines are enabled during the time when RIC is high.
The falling edge of RIC starts the next conversion and the data
lines return to three-state (and remain three-state) until the next
high pulse of RIC.
Figure 7. Read Cycle Timing
READ TIMING-FULL CONTROL MODE
Symbol Parameter
Min Typ
Access Time (from CE)
too 1
75
Data Valid after CE Low 25
tHo
tHL2
Output Float Delay
CS to CE Setup
tSSR
SO
RlCtoCESetup
tSRR
0
Ao to CE Setup
tSAR
50
CS Valid AfterCE Low 0
tHS&'
tHRR
RIC High AfterCE Low 0
tHAR
Ao Valid After CE low
SO
Max
Units
ISO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISO
ItOD is measured with the load circuit of Figure 8 and defined as the time required for an
OUtputto cross O.4Vor 2.4V.
time required for the data lines to change O.SV when loaded with the
circuit of Figure 9.
=\1 r-_ _ _ _ __
IHRL
RIC~STS
,'0'1..-_________\
-+~I
-j ~ 1--'- - t o:--~~.---I I-,HS
o81,-OBO
~:~~
I)
HIGH-Z
'DATA VALID
I
Figure 10. Low Pulse fo RiC-Outputs Enabled After
Conversion
2 tHL is defmed as the
1
RIC
+5V
..
~3k
DBNCO~-I~~3-k-----Jt~~·
J:
'OOpF
1'OOPF
b. High-Z to Logic 0
+5V
--I. .
DBN ~o 3-k-~Jt~.
J:'OPF
a. Logic 1 to High-Z
DBN+
J'OPF
b. Logic 0 to High-Z
Figure 9. Load Circuit for Output Float Delay Test
L
,t
---rl -7-,--:--', 11_'--.,--.-,1
t---i tHOR
~,,'_~_:l_TI~...... ......J)r-------'H.;;.IG::;.H;.:.Z'------------'-DDDDRR.
DB"-DBO
a. High-Z to Logic 1
,
STS
DBN~
Figure 8. Load Circuit for Access Time Test
-.i1\4
'HRH 1---'0'--1----:---------
I__
Figure ". High Pulse for RIC-Outputs Enable While RIC
High, Otherwise High-Z
STAND-ALONE MODE TIMING
Symbol Parameter
tHRL
tos
tHDR
tHS
tHRH
tOOR
Min Typ
Low RIC Pulse Width
50
STS Delay from RIC
Data Valid After RIC Low
25
STS Delay After Data Valid 30
High RIC Pulse Width
ISO
Data Access Time
Max
200
55
600
ISO
Units
ns
ns
ns
ns
ns
ns
ANALOG-TO-DIGITAL CONVERTERS 3-97
II
GENERAL AID CONVERTER INTERFACE
CONSIDERATIONS
A typical AID converter interface routine involves several operations. First, a write to the ADC address initiates a conversion.
The processor must then wait for the conversion cycle to complete,
since most integrated circuit ADCs take longer than one instruction
cycle to complete a conversion. Valid data can, of course, only
be read after the conversion is complete. The AD674A provides
an output signal (STS) which indicates when a conversion is in
progress. This signal can be polled by the processor by reading
it through an external three-state buffer (or other input port).
The STS signal can also be used to generate an interrupt upon
completion of conversion, if the system timing requirements are
critical (bear in mind that the maximum conversion time of the
AD674A is only IS microseconds) and the processor has other
tasks to perform during the ADC conversion cycle. Another
possible time-out method is to assume that the ADC will take
IS microseconds to convert, and insert a sufficient number of
"no-op" instructions to ensure that I 5 microseconds of processor
time is consumed.
XXXO(EVENADDRI:
XXX1IODDAOORI:
I
I
Once conversion is complete, the data can be read. For converters
with more data bits than are available on the bus, a choice of
data formats is required, and multiple read operations are needed.
The AD674A includes internal logic to permit direct interface to
8-bit and 16-bit data buses, selected by the state of the 1218
input. In 16-bit bus applications (12/8 high) the data lines (DBll
through DBO) may be connected to either the 12 most significant
or 12 least significant bits of the data bus. The remaining four
bits should be masked in software. The interface to an 8-bit
data bus (12/8 low) is done in a left-jilstified format. The even
address (AO low) contains the 8MSBs (DBll through DB4).
The odd address (AO high) contains the 4LSBs (DB3 through
DBO) in the upper half of the byte, followed by four trailing
zeroes, thus eliminating bit masking instructions.
It is not possible to rearrange the AD674A data lines for rightjustified 8-bit bus interface.
D1
DB11
(MSBI
DB3
D.
I
0810
DB9
DB'
DB2
DB'
Doo
ILSBI
I I
DB1
Daa
DB.
I• I•
Figure 12. AD674A Data Format for 8-Bit Bus
3-98 ANALOG-TO-DIGITAL CONVERTERS
D. .
•
I
I
12-Bit 200 KSPS
Complete Sampling ADC
AD678 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
AC and DC Characterized and Specified
200k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
72 dB S/N+D (K Gradel
Twos Complement Data Format (Bipolar Model
Straight Binary Data Format (Unipolar Model
10 Mil Input Impedance
8-Bit or 16-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
PRODUCT DESCRIPTION
The AD678 is a complete, multipurpose 12-bit monolithic
analog-to-digital converter, consisting of a sample-hold amplifier
(SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.
The AD678 is similar to the ADl678 in that it is specified for ac
(or "dynamic") parameters such as SIN+D ratio, THD and
IMD which are important in signal processing applications. In
addition, the AD678 is fully specified for dc parameters which
are important in measurement applications.
The AD678 offers a choice of digital interface
data bits can be accessed by a 16- .
tion or by an 8-bit bus in two rea
or left justification. Data format is
mode and twos complement binary for
has a full-scale range of 10 V with a full
1 MHz and a full linear bandwidth of 500 k
h inp
impedance (10 MO) allows direct connection to unbuffer
sources without signal degradation.
This product is fabricated on Analog Devices' BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-fUm resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD678 operates from +5 V and ± 12 V supplies and dissipates 745 mW. A 28-pin plastic DIP and a 0.6" wide ceramic
AD678 FUNCTIONAL BLOCK DIAGRAM
DIP are available. Contact factory for surface-mount package
options.
Screening to MIL-STD-883C Class B is also available.
TION: The AD678 minimizes
requirements by combining a high speed
er (SHA), ADC, 5 V reference, clock and
a single chip. This provides a fully speciction unattainable with discrete
ATIONS: The AD678 is specified for both dc and
ers. DC specifications (such as INL, gain and offrtant in control and measurement applications.
ifications (such as SIN + D ratio, THD and IMD) are
of value in signal processing applications.
3. EASE OF USE: The pinout is designed for easy board layout, and the choice of single or two read cycle output provides compatibility with 16- or 8-bit buses. Factory trimming
eliminates the need for calibration modes or external trimming to achieve rated performance.
4. RELIABILITY: The AD678 utilizes Analog Devices'
monolithic BiMOS technology. This ensures long term reliability compared to multichip and hybrid designs.
AD678 ORDERING GUIDE
Temperature Range and Package Options!
o to +70·C
o to +70OC
o to +70·C
Ceramic DIP (D-28A)
Ceramic DIP (D-28A)
-55·C to +125·C
AD678JN
AD678KN
AD678JP
AD678KP
AD678JD
AD678KD
AD678SD
AD678TD
Plastic DIP (N-28A)
PLCC (P-28A)
Integral Nonlinearity
T min to T max
±1 LSB
±1I2 LSB
SIN&D'
71
73
NOTE
'See Section 14 for package outline information.
2Typical at 10 kHz, -0.5 dB input.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-99
SPECIFICATIONS
Tma., Vee = +12 V ±~%, VEE = -12 V ±5%, Voo = + 5 V ±10%, fSAMPLE = 200 KSPS,
AC· SPECIFICATIONS (Tmln= to10.06
kHz unless otherwise noted)
1
fiN
AD678j/S
Parameter
Min
Typ
SIGNAL-TO-NOISE AND DISTORTION (SIN+D) RATIO
@ +25°C
T min to Tmax
70
70
71
71
TOTAL HARMONIC DISTORTION (THD)
@ +25OC
T min to Tmax
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
Max
Min
72
71
-80
AD678K1T
Typ
Max
73
73
dB
dB
-80
-88
0.004
-85
0.005
0.010
-78
0.012
-88
0.004
-85
0.005
0.010
-78
0.012
dB
%
dB
%
-87
-80
-87
-80
dB
MHz
FULL POWER BANDWIDTH
500
FULL LINEAR BANDWIDTH
INTERMODULATION DISTORTION (IMD)2
2nd Order Products
3rd Order Products
-90
±5%, VEE
2.4
VIN
VIN
IOH
IOH
Low Level Output Voltage
High Z Leakage Current
High Z Output Capacitance
dB
dB
= -12 V ±5%, Voo = +5 V ±10%)
Max
Parameter
LOGIC OUTPUTS
High Level Output Voltage
-80
-80
ed to a -0 dB (9.997 V p.p) input signal.
DIGITAL SPECIFICATIONS
INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
kHz
-85
NOTE
'fiN amplitude ~ -0.5 dB (9.44 V p.p)
'fA ~ 9.08 kHz, fa ~ 9.58 kHz, with f
Specifications subject to change without
LOGIC
VIH
VIL
IIH
IlL
CIN
Units
IOL
=
0.8
10
10
10
5V
= OV
= 0.1 rnA
= 0.5 rnA
= 1.6 rnA
VIN = 0 or 5 V
4.0
2.4
0.4
10
10
Units
V
V
/LA
JJ.A
pF
V
V
V
/LA
pF
NOTES
Specifications shown in boldface are tested on all devices at rmal electrical test with worst case supply voltages at O"C, +25"C and +70'C. Results from those
tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-100 ANALOG-TO-DIGITAL CONVERTERS
AD678
DC SPECIFICATIONS (Tmin to 1m.., Vee = +12 V ±5%, VEE = -12 V ±5%, V = +5 V ±10% unless otherwise indicated)
DD
Parameter
Min
TEMPERATURE RANGE
0
ACCURACY
Resolution
Integral Linearity Error
Differential Linearity
Unipolar Zero Error (@ 25°C)!
Bipolar Zero Error (@ 25°C)!
Gain Error (@ 25 oC)!,2
Ternperamre Drift (Coefficients)
Unipolar Zero3
Bipolar Zero3
Gain3
Gain'
AD678J
Typ Max
+70
12
Min
AD678K
Typ Max
0
+70
12
±1
±1I2
12
11
±2
±2
±8
±2
±2
±4
±2 (10)
±2 (10)
±9 (50)
±2 (10)
Inn
Power Consumption
(ppmrC)
(pprorC)
(ppmrC)
(pprorC)
V
V
Mil
pF
ILS
ns
ps
INTERNAL VOLTAGE REFERENCE
Output VoltageS
External Load
Unipolar Mode
Bipolar Mode
lEE
Bits
LSB
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ANALOG INPUT
Input Ranges
Unipolar Range
Bipolar Range
Input Resistance
Input Capacitance
Input Settling Time
Apermre Delay
Apermre Jitter
POWER SUPPLIES
Power Supply Rejection
Vcc = +12 V ±5%6
VEE = -12 V ±5%
Vnn = +5 V ±1O%
Operating Current
Icc
Units
°C
18
25
8
560
5.02
V
+1.5
+0.5
+1.5
+0.5
rnA
rnA
±1
±1
±1
±1
±1
±1
LSB
LSB
LSB
20
34
12
745
rnA
rnA
rnA
mW
20
34
12
745
18
25
8
560
NOTES
1Adjustable to zero. See Figures 6 and 7.
2Inc1udes internal voltage reference error.
'Includes internal voltage reference drift.
'Excludes internal voltage reference drift.
'With maximum external load applied.
61.4 V of headroom is required between Vee and AIN.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at O'C, + 25'C and + 70'C. Results from those
tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, althougb ouly those abown in boldface are tested.
This information applies to a product under development. Its characteristics and specifications are subiect to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-101
I
SPECIFICATIONS
DC SPECIFICATIONS (Tmin to Tmax. Vee = +12 V ±5%. VEE = -12 V ±5%. Voo = +5 V ±10% unless otherwise indicated)
AD678S
Parameter
Min
TEMPERATURE RANGE
-55
ACCURACY
Resolution
Integral Linearity Error
Differential Linearity
Unipolar Zero Error (@ 25 0 C)1
Bipolar Zero Error (@ 25oc)1
Gain Error (@ 25oC)1,2
Temperature Drift (Coefficients)
Unipolar Zero3
Bipolar Zero3
Typ
AD678T
Max
Min
+125
-55
12
Typ
Max
Units
+125
°C
12
:tI
11
::!:1I2
12
:t2
:t2
:t8
±2
:t2
:t4
LSB
LSB
LSB
SB
:t4 (10)
:t4 (10)
:t 18 (44)
:t4 (10)
Gain3
Gain4
ANALOG INPUT
Input Ranges
Unipolar Range
Bipolar Range
Input Resistance
Input Capacitance
Input Settling Time
Aperture Delay
Aperture Jitter
100
Power Consumption
(ppml"C)
(ppmJ"C)
(ppmJ"C)
(ppmJ"C)
ns
ps
INTERNAL VOLTAGE REFERENCE
Output VoltageS
External Load
Unipolar Mode
Bipolar Mode
POWER SUPPLIES
Power Supply Rejection
Vcc = +12 V :t5%"
VEE = -12 V :t5%
Voo = +5 V :tIO%
Opemting Current
Icc
lEE
Bits
LSB
Bits
LSB
LSB
LSB
V
18
25
8
560
+1,5
+0.5
+1,5
+0.5
mA
mA
:tl
:tl
:tl
:tl
:tI
:tl
LSB
LSB
LSB
20
34
12
745
mA
mA
mA
20
34
12
745
18
25
8
560
mW
NOTES
1Adjustable to zero. See Figures 6 and 7.
'Includes internal voltage reference error.
'Includes internal voltage reference drift.
'Excludes internal voltage reference dtift.
'With maximum external load applied.
61.4 V of headtoom is required between V cc and AIN.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at OOC, +25°C and +70'C. Results from those
tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those sbown in boldface are tested.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-102 ANALOG-TO-DIGITAL CONVERTERS
Timing - AD678
grades, Tml• to Tmax, Vee = +12 V ±5%, VEE = -12 V ±5%,
TIMING SPECIFICATIONS (All
VDD = +5 V ±10% unless otherwise noted)
Parameter
Symbol
Min
SC Delay
Conversion Rate
tsc
50
Typ
150
5
to>
Status Delay
Access Time4
Float Dela~
Update Delay
Format Setup
OE Delay
Read Pulse Width
tAD
te
te
tSD
tBA
tpo
tUD
t FS
tOE
tRP
Conversion Delay
EOCEN Delay
teD
tEO
Units
ns
",s
",s'
ns
ns
",s
5
5.23
1:cR
Convert Pulse Width
Aperture Delay
Conversion Timez
Max
20
3.9
4.1
0
10
4.47
4.70
400
100
80
",.3
II
ns
ns
ns
ns
ns
200
60
NOTES
'S,T grades in S·bit read mode (see F'
2Includes Acquisition Time.
's, T grades.
'Measured from the falling edge of 0
CE
See Figure 3; CoUT = 100 pF.
'Measured from the rising edge of OElEOCEN (2.
See Figure 3; CoUT = 10 pF.
"12-bit read mode.
'S-bit read mode.
Specifications subject to change without notice.
cs'
~
SHA
~~"C-,---r_ _ _ __
4t---f-=--=-'_CO-==LtcD-. j
II
TRACK
I
HOLD
REGISTER
I--
TRACK
I
HOLD
==-~~=_"==D=u:=:::-;;tc~4~~2~=:=
~""D~
EOC'
CON~~8f
I
DATA 0
Xr---'-DA-T-A-'--. \....--.,-1_ _ _ __
VV
cs ~tEor
EOCEN
~
~tBA~
EOC'
jr---
.II
~
rtFD
----------~~~-----
NOTE
'SEE END-Of-CONVERT (EOCI PARAGRAPH fOR DETAILS.
Figure 2. EOC Timing
TEST
ACCESS TIME HIGH Z TO LOGIC LOW
fLOAT TIME LOGIC HIGH TO HIGH Z
ACCESS T1ME HIGH Z TO LOGIC HIGH
fLOAT T1ME LOGIC LOW TO HIGH Z
Vep
COUT
5 V
5 V
oV
oV
100 pf
10 pf
100 pf
10 pf
NOTES
'IN ASYNCHRONOUS MODE. STATE OF CS DOES NOT AFFECT OPERATION. SEE THE START
CONVERSION TRUTH TABLE FOR DETAILS.
'EOCEN = LOW; FIGURE 2. IN SYNCHRONOUS MODE, EOC IS A THREEoSTATE OUTPUT.
IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT.
'DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
Figure 1. Conversion Timing
DOUT
0 0 - - -....-4(
Vep
Figure 3. Load Circuit for Bus Timing Specifications
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-103
CONVERSION CONTROL
In synchronous mode (SYNC = HIGH), both Chip Select (CS)
and Start Convert (SC) must be brought LOW to start a conversion. CS should be LOW tsc before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing SC low, regardless of the state of CS.
Before a conversion is started, End-of-Convert (EOC) is HIGH,
and the sample-hold is in track mode. After a conversion is
started, the sample-hold goes into hold mode and EOC goes
LOW, signifying that a conversion is in progress. During the
conversion, the sample-hold will go back into track mode and
start acquiring the next sample. EOC goes HIGH when the conversion is fmished.
In track mode, the sample-hold will settle to ±0.01 % (12 bits)
in 1 j.LS maximum. The acquisition time does not affect the
throughput rate as the AD678 goes back into track mode more
than I
j.LS before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW if
the maximum throughput rate is needed.
END-OF-CONVERT
In asynchronous mode, End-of-Convert (EOC) is an open drain
output (requiring a minimum 3 kG pull-up resistor) enabled by
End-of-Convert ENable (EOCEN). In synchronous mode, EOC
is a three-state output which is enabled by EOCEN and CS. See
the Conversion Status Truth Table for details. Access (tBA) and
float (tFD) timing specifications do not apply in asynchronous
mode where they are a function of the time constant formed by
the 10 pF output capacitance and the pull-up resistor.
START CONVERSION TRUTH TABLE
INPUTS
12-BIT MODE CODING FORMAT (1 LSB = 2.44 mY)
CS
Bipolar Coding
(Twos Complement)
Unipolar Coding
(Straight Binary)
VIN
Output Code
o
000 ... 0
100 ... 0
111 ..• 1
5.000 V
9.9964 V
SYNC
V IN
SC
0
Output Code
0
STATUS
X
No Conversion
1:.
Start Conversion
0
Start Conversion
(Not Recommended)
0
Continuous Conversion
X
+
+
o
No Conversion
X
1:.
Start Conversion
X
o
Continuous Conversion
OUTPUT ENABLE TRUTH TABLES
H voltage level.
LOW voltage level.
Don't care.
HIGH to LOW transition. Must stay low for t = 1:cP.
12-BIT MODE (1218 = HIGH)
INPUTS
OUTPUT
(CS U OE)
DBll-DBO
8-BIT MODE (1218
INPUTS
= LOW)
Unipolar
Mode
Bipolar
Mode
RJL
HBE
X
X
1
1
1
0
0
0
t.
1
1
0
1
0
0
0
1
0
1
1
NOTES
1 = HIGH voltage level.
o = LOW Voltage level.
X = Don't care.
U = Logical OR.
(CSUOE)
a
-
a
e
a
i
=
0
f'
b
j
High Z ________
0
g
c
k
a
f
b
a
j
k
g
c
0
h
d
1
a
h
d
1
a
b
i
e
0
f
0
a
b
i
e
0
f
j
j
0
c
k
g
0
d
1
c
k
g
0
d
1
h
0
h
0
STATUS
Converting
1
0
0
0
1
0
0
I
Not Converting
Synchronous
Mode
1
1
X
HighZ
Either
1
X
1
HighZ
Either
0
X
0
0
Converting
Asynchronous
Mode*
0
X
0
HighZ
Not Converting
0
X
1
HighZ
Either
OUTPUTS
DBll ..• DB4
0
e
a
i
t.
t.
t.
t.
t.
t.
t.
OUTPUT
SYNC CS EOCEN EOC
INPUTS
-
CONVERSION STATUS TRUTH TABLE
HighZ
Enable 12-Bit Output
1
t.
NOTES
I = HIGH voltage level.
o = LOW voltage level.
X = Don't care.
*EOC requir"" a pull-up resistor in asynchronous mode.
MSB.
I = LSB.
= HIGH to LOW transition. Must
stay low for t = t RP •
t.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-104 ANALOG-TO-DIGITAL CONVERTERS
Dynamic Performance
OUTPUT ENABLE OPERATION
The data bits (DBll-DBO) are three-state outputs enabled by
Chip Select (CS) and Output Enable (OE). CS should be LOW
tOE before OE is brought LOW. Bits DBI (R/L) and DBO
(HBE) are bidirectional. In 12-bit mode they are data output
bits. In 8-bit mode they are inputs which define the format of
the output register.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFoUT),
output coding is twos complement binary.
When EOC goes HIGH, the output register contains the results
of the previous conversion. A period of time tun is required for
the present conversion results to be loaded into the output register. Bringing OE LOW tOE after CS goes LOW makes the output register contents available on the data bits. A period of time
ten is required after OE is brought HIGH before the next SC
instruction is issued. This allows internal logic states to reset
and guarantees minimum aperture jitter for the next conversion.
Output Enable (OE) must be toggled to update the output
register in both 8- and 12-bit read modes.
Figure 4 illustrates the 8-bit read mode
only DBll-DB4 are used as
output is read in two steps,
lowed by the low byte. High
output sequence. The l2-bit !.esult ~.
depending on the state of RIL. Note till; fi
the 8-bit read mode results in a converslm rate of 5.
I" ~'o'i ~.
CO"
:
~.II
i-I
r-9
,~+~
OE - - - - . < - - - - - - - \ 1 ·..
'ro
I
DB"-DB4
AD678
Ir-
-----_<,_-----(
NOTE
_
_
',N ASYNCHRONOUS MODE, DE IS INDEPENDENT OF CS.
Figure 4. Output Timing, 8-Bit Read Mode
~
. -ffir-.,oJ---JI I-'ro-l
-----~~---~~~--------Figure 5. Output Timing, 12-Bit Read Mode
In 12-bit read mode (12/8 = HIGH), a single READ
accesses all 12 output bits on DBll-DBO for interfa
bit bus. Figure 5 provides the output timing relationships. Note
that teR must be ovserved, in that SC pulses should not be
issued at intervals closer than 5 ILS. If SC is asserted sooner than
5 ILS, conversion accuracy may deteriorate. For this reason, SC
should not be held LOW in an attempt to operate in a continuous convert mode.
POWER-UP
A conversion sequence, consisting of one SC instruction, is
required after power-up to reset internal logic.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-OIGITAL CONVERTERS 3-105
I
Definition of Specifications
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the "Nyquist
Frequency" of a converter is that input frequency which is onehalf the sampling frequency of the converter.
SIGNAL·TO·NOISE AND DISTORTION (SIN+D) RATIO
SIN + D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
INPUT SETTLING TIME
Settling time is a function of the SHA's ability to track fast
slewing signals. This is specilled as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
DIFFERENTIAL LINEARITY (DNL)
In an ideal ADC, code transitions are ILSB apart. Differential
linearity is the deviation from this ideal value. It is often specified in terms of resolution for which no missing codes (NMC)
are guaranteed.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value a full-scale input signal and is
expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
This specillcation is 12 bits from T min to T max for the AD678K
and T grades, which guarantees that all 4096 codes are present
over temperature. The AD678] and S grades specify 11 bits
NMC T min to T max' which means that missing codes do not
occur adjacent to each other.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a fullscale input signal.
UNIPOLAR ZERO ERROR
ansition should occur at a level
• Unipolar zero error is the deviarom that point. This error can be
in the Input Connections and Calibration
With inputs consisting of sine wave
and fb, any device with nonlineariti
products, of order (m + n), at sum
d
ce
ofmfa ± nfb, where m, n = 0, 1,2,3 .. ~
terms are those for which m or n is not equal
pie, the second order terms are (fa + fb) and ( - fb) and
third order terms are (2 fa + fb), (2 fa - fb), (fa + 2 fb) an
(fa - 2 fb). The IMD products are expressed as the decibel
ratio of the rms sum of the measured input signals to the rms
sum of the distortion terms. The two signals applied to the converter are of equal amplitude and the peak value of their sum is
-0.5 dB from full scale (9.44 V pop). The IMD products are
normalized to a 0 dB input signal.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than -0.1 dB. Beyond this frequency, distortion of the sampled input signal increases signillcantly.
The AD678 has been designed to optimize input bandwidth,
allowing the AD678 to undersample input signals with frequencies significantly above the converter's Nyquist frequency.
APERTURE DELAY
Aperture delay is a measure of the SHA's performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion. In synchronous mode,
Chip Select (CS) should be LOW before SC to minimize aperture delay.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the AID.
Ode, the major carry transition (1111 1111 1111
o ) should occur at an analog value 112 LSB
nd. Bipolar zero error is the deviation of the
rom that point. This error can be adjusted as
the Input Connections and Calibration section.
The last transition should occur at an analog value I 1/2 LSB
below the nominal full scale (9.9963 volts for a 0-10 V range,
4.9963 volts for a ±5 V range). The gain error is the deviation
of the actual level at the last transition from the ideal level with
the zero error trimmed out. Tlii.s error can be adjusted as shown
in the Input Connections and Calibration section.
INTEGRAL LINEARITY ERROR (INL)
The ideal transfer function for a linear ADC is a straight line
drawn between "zero" and "full scale." The point used as
"zero" occurs 1I2LSB before the first code transition. "Full
scale" is defined as a level I 1I2LSB beyond the last code transition. Integral linearity error is the worst-case deviation of a code
from the straight line. The deviation of each code is measured
from the middle of that code.
The AD678K and T grades are guaranteed for maximum integrallinearity error of ± 1I2LSB T min to T max' For these grades,
this means that an analog value which falls exactly in the center
of a given code will result in the correct digital output code.
Values nearer the upper or lower transition of the code may produce the next upper or lower digital output code. The AD678J
and S grades are guaranteed to ± ILSB max error. For these
grades, an analog value which falls within a given code width
will result in either the correct code for that region or either
adjacent one.
Note that the linearity error is not user adjustable.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-106 ANALOG-TO-DIGITAL CONVERTERS
Definition of Specifications - AD678
POWER SUPPLY REJECTION
Variations in power supply will affect the full-scale calibration.
This will result in a linear change in all lower-order codes. The
specifications show the maximum change in the full-scale transition point due to a change in power-supply voltage from the
nominal value.
TEMPERATURE COEFFICIENT
This is the maximum change in the parameter from the initial
value (@ 25°C) to the value at T min or T max'
AD678 PIN DESCRIPTION
Symbol
Pin No.
Type
Name and Function
AGND
7
P
Analog Ground. This is the ground return for AIN only.
AIN
6
Al
Analog Signal Input.
BIPOFF
10
Al
Bipolar Offset. Connect to AGND for + 10 V input unipolar mode and straight binary output
coding. Connect to REFoUT through 50 {} resistor for ±5 V input bipolar mode and twos complement binary output coding. See Figures 7 and 8.
CS
4
D1
Chip Select. Active LOW.
DGND
14
P
Digital Ground
DB 11-DB4
26-19
DO
DB3, DB2
18, 17
DB1 (RiL)
16
DBO(HBE)
15
EOC
27
ese pins provide the upper 8 bits of
s m two bytes (see RJL pin). Active HIGH.
Data Bit 3 and Data Bit 2. Active
DO
version starts and goes HIGH when the conversion
open drain output and requires an external 3 k!l
C pins for information on EOC gating.
DI
EOCEN
. Enables EOC pin. Active LOW.
HBE (DBO)
15
DI
In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output contains low byte.
OE
2
DI
Output Enable. The falling edge of OE enables DB11-DBO in 12-bit fonnat and
DB11-DB4 in 8-bit format. Gated with CS. Active LOW.
REFIN
9
AI
Reference Input. +5 V input gives 10 V full scale range.
REFoUT
8
AO
+5 V Reference Output. Tied to REFIN through 50 {} resistor for normal operation.
R/I: (DB1)
16
DI
In 8-bit format, RightlLeft justified. Sets alignment of 12-bit result within 16-bit field. Tied to
V00 for right-justified output and tied to DGND for left-justified output.
SC
3
DI
Start Convert. Active LOW. See SYNC pin for gating.
SYNC
13
DI
SYNC Control. If tied to V00 (synchronous mode), SC, EOC and EOCEN are gated by CS. If
tied to DGND (asynchronous mode), SC and EOCEN are independent of CS, and EOC is an
open drain output. EOC requires an external 3 k!l pull-up resistor in asynchronous mode.
Vee
11
P
+ 12 V Analog Power.
VEE
5
P
-12 V Analog Power.
Voo
1218
28
P
+5 V Digital Power.
12
DI
Twelve/eight bit fonnat. If tied HIGH, sets output fonnat to 12-bit parallel. If tied LOW, sets
output format to 8-bit multiplexed.
Type: AI = Analog Input.
AO = Analog Output.
DI = Digital Input (TTL and 5 V CMOS compatible).
DO = Digital Output (TTL and 5 V CMOS compatible). All DO pins are three-State drivers.
P = POWeI.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-107
•
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Specification
To
Min
Vee
VEE
Vee
VDD
AGND
AIN, REFIN
REFIN
REFIN
Digital Inputs
Digital Outputs
Max Junction
Temperature
Operating Temperature
J and K Grades
S and T Grades
Storage Temperature
Lead Temperature
(10 sec max)
AGND
AGND
VEE
DGND
DGND
AGND
VEE
Vee
DGND
DGND
-0.3
-18
-0.3
0
-1
-12
0
VEE
-0.5
-0.5
PIN CONFIGURATION
Max
Units
+18
+0.3
+26.4
+7
+1
+12
Vee
0
+7
VDD +0.3
V
V
V
V
V
V
V
V
V
V
175
·C
•
VOD
EOC.
DB11
DB10
DB9
DBI
AD678
DB7
..TOPVIEW
(Not to Scale)
DB6
DB5
0
-55
-65
+70
+125
+150
·C
DB4
OC
·C
DB3
DB2
+300
DB1 (RlL)
*Stresses above those listed under "Absolute Maximum Ratings" ma
permanent damage to the device. This is a stress rating
operation of the device at these or any 0
cated in the operational sections of this
sure to absolute maximum rating conditio
device reliability.
DBO (HBE)
ESD SENSITIVITY _ _ _ _ _ __
The AD678 features input protection cir
conSlS
polysilicon series resistors to dissipate both high energy dis
low energy pulses (Charged Device Model). Per Method
has been classified as a Category A device.
tri t
diodes and
Body Model) and fast,
.2 of MIL-STD-883C, the AD678
Proper ESD precautions are strongly recommended to avoid functional damage or penorrnance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test eqUipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices' ESD ~ention Manual.
WARNING! ~
~~::
Application Information
INPUT CONNECTIONS AND CALIBRATION
The high (10 MO) input impedance of the AD678 eases the task
of interfacing to high source impedances or multiplexer channelto-channel mismatches of up to 1000 O. The 10 V Pop full-scale
input range accepts the majority of signal voltages without the
need for voltage divider networks which could deteriorate the
accuracy of the ADC.
The AD678 is factory trimmed to minimize linearity, offset and
gain errors. In unipolar mode, the only external component that
is reqUired is a 50 0 ± 1% resistor. Two resistors are reqUired in
bipolar mode. If offset and gain are not critical (as in some ac
applications), even these components can be eliminated.
In some applications, offset and gain errors need to be trimmed
out completely. The following sections describe the correct procedure for these various situations.
UNIPOLAR RANGE INPUTS
Offset and gain errors can be trimmed out by using the configuration shown in Figure 6. This circuit allows approximately
±25 mV of offset trim range (±10 LSB) and ±0.5% of gain
trim (±20 LSB).
The nominal offset is 1/2 LSB so that the analog range that
corresponds to each code will be centered in the middle of that
code (halfway between the transitions to the codes above and
below it). Thus the first transition (from 0000 0000 0000 to 0000
0000 000 I) should nominally occur for an input level of
+112 LSB (1.22 mV above ground for a 10 V range). To trim
unipolar zero to this nominal value, apply a 1.22 mV signal to
AIN and adjust R1 until the first transition is located. range
The gain trim is done by adjusting R2. If the nominal value is
required, apply a signal I 1/2 LSB below full scale (9.9963 V for
a 10 V range) and adjust R2 until the last transition is located
(11l111l11l10 to 1111 IlIl IlIl).
This information applies to a product under development. Its characteristics and speCifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-708 ANALOG-TO-DIGITAL CONlIERTERS
Application Information - AD678
If offset adjustment is not required, BIPOFF should be connected directly to AGND. If gain adjustment is not required,
R2 should be replaced with a flxed 50 0 ± I % metal fllm resistor. If REFouT is connected directly to REFIN , the additional
gain error will be approximately 1%.
BIPOLAR RANGE INPUTS
The connections for the bipolar mode are shown in Figure 7. In
this mode, data output coding will be in twos-complement
binary. This circuit will allow approximately ±25 mV of offset
trim range (± 10 LSB) and ± 0,5% of gain trim range (20 LSB).
Either or both of the trim pots can be replaced with 50 0 ± 1%
flxed resistors if the AD678 accuracy limits are sufficient for the
application. If the pins are shorted together, the additional offset
and gain errors will be approximately 1%.
To trim bipolar zero to its nominal value, apply a signal
112 LSB below midrange (-1.22 mV for a ±5 V range) and
adjust Rl until the major carry transition is located (1111 1111
1111 to 0000 0000 0000). To trim the gain, apply a signal
1112 LSB below full scale (+4.9963 V for a ±5 V range
adjust R2 to give the last positive transition (011
0111 1111 1111). These trims are i n t "
may be necessary for con
A single-pass calibration
s
offset trim (error at minus
(error at midscale), using the s
112 LSB above minus full scale (-4.
and adjust Rl until the minus full-sc
translqon
(100000000000 to 1000 0000 001). Then perform
trim as outlined above.
0-------1.
AlN
OT010 VINPUT
:1::& V INPUT
AD678
~
GAIN
ADJUST
OFFSET
ADJUST
routed close to it. Using this approach, signal loops enclose a
small area, minimiZing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
The AD678 incorporates several features to help the user's layout. First of all, analog pins (VEE' AIN, AGND, REFoUT>
REFIN, BIPOFF, Vee) are adjacent to help isolate analog from
digital signals. In addition, the 10 MO input impedance of AIN
minimizes input trace impedance errors. Finally, ground currents have been minimized by careful circuit design. Current
through AGND is 200 j1A, with no code-dependent variation.
The only current through DGND is the return current for
DB11-DBO and EOC.
LING
supplies should be well filtered, well regufrom high-frequency noise. Switching power supcommended. These supplies generate spikes
e noise in the analog system.
·tors should be used in very close layout proxbetween all power supply pins and analog ground. A
tantalum capacitor in parallel with a 0.1 j1F ceramic proequate decoupling. The power supply pins should be
ed directly to DGND.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD678, associated analog input circuitry and interconnections as far as possible from logic circuitry. A solid analog
ground plane around the AD678 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit construction is preferred.
GROUNDING
If a single AD678 is used with separate analog and digital
Figure 6. Unipolar Input
Connections with Gain
and Offset Trims
Figure 7. Bipolar Input
Connections with Gain
and Offset Trims
BOARD LAYOUT
Designing with high-resolution data converters requires careful
attention to layout considerations. Trace impedance is the flrst
issue. At tl1e 12-bit level, a 5 rnA current through a 0.5 0 trace
will develop a voltage drop of 2.5 mV, which is 1 LSB for a
10 V full-scale span. In addition to ground drops, inductive and
capacitive coupling need to be considered, especially when highaccuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Analog and digital signals should not share a common path.
Each signa1 should have an appropriate analog or digital return
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD678. If multiple AD678s are used or the AD678 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at
each chip. This prevents large ground loops which inductively
couple noise and allow digital currents to flow tl1rough the analog system.
INTERFACING THE AD678 TO MICROPROCESSORS
The I/O capabilities of tl1e AD678 allow direct interfacing to
general purpose and DSP microprocessor buses. The asynchronous conversion control feature allows complete flexibility and
control with minimal external hardware.
The following examples illustrate typical AD678 interface
conflgurations.
if
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-OIGITAL CONVERTERS 3-109
3
AD678 TO TMS320C25
In Figure 8 the AD678 is mapped into the TMS320C25 110
space. AD678 conversions are initiated by issuing an OUT
instruction to Pon 8. EOC status and the conversion result are
read in with an IN instruction to Pon 8. A single wait state is
insened by generating the processor READY input from IS,
Pon 8 and MSC. This confIgUration suppons processor clock
speeds of 20 MHz and is capable of supponing processor clock
speeds of 40 MHz if a NOP instruction follows each ~78
read instruction.
AD678 TO 80186
Figure 9 shows the AD678 interfaced to the 80186 microprocessor. This interface allows the 80186's built-in DMA controller to
transfer the AD678 output into a RAM based FIFO buffer of
any length, with no microprocessor intervention.
..
Figure 8. AD678 to TMS320C25 Interface
In this application the AD678 is confIgUred in the asynchronous
mode, which allows conversions to be initiated by an external
trigger source independent of the microprocessor clock. After
each conversion, the AD678 EOC signal generates a DMA
request to Channell (DRQl). The subsequent DMA READ
operation resets the interrupt latch. The system designer must
assign a suffICient priority to the DMA channel to ensure that
the DMA request will be serviced before the completion
of the next conversion. This confJgUration can be used
6-MHz and 8-MHz 80186 processors.
AD678 TO Z80
The AD678 can be interfaced to
e
memory mapped confJgUration.
fIgUration, where the AD678 occupies
allow separate polling of the EOC status
The lower address bit, AO, is used to select the high an
order bytes of the result. The AD678 RlE" line is tied
resulting in right justified output data.
A useful feature of the Z80 is that a single wait state is automatically insened during 110 operations, allowing the AD678 to be
used with Z80 processors having clock speeds up to 8 MHz.
k-___DA:;.c;;TA..:;BU;,:.S--.::..-::Q-t---..l 0111-084
AD678 TO ANALOG DEVICES ADSP-2100A
Figure 11 demonstrates the AD678 interfaced to an
ADSP-2100A.With a clock frequency of 12.5 MHz, and instruction execution in one 80 ns cycle, the digital signal processor
will support the AD678 data memory interface with two hardware wait states.
The convener is confIgUred to run asynchronously using a sampling clock. The EOC output of the AD678 gets assened at the
end of each conversion and causes an interrupt. Upon interrupt,
the ADSP-2100A immediately executes a data memory write
instruction which assens HBE. In the following cycle, the processor statts a data memory read (high byte read) by providing
an address on the DMA bus. The decoded address generates OE
for the convener. OE, together with logic and latches, is used to
force the ADSP-2100A into a two cycle wait state by generating
DMACK. The read operation is thus staned and completed
within 3 processor cycles (240 ns). HBE is released during "high
byte read." This allows the processor to read the lower byte of
data as soon as "high byte read" is complete. The low byte read
operation executes in a similar manner to the first and is completed during the next 240 ns.
.............-.-l EOC
12/8
Figure 10. AD678 to Z80 Interface
AD87B
DMD
15-'~_ _ _---=":.;;T::.;ABUS=-_ _ _ _--10811-D84
Figure 11. AD678 to ADSP-2100A Interface
This information applies to a product under development. Its characteristics and specifications are subject to change without notica.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-110 ANALOG-TO-DIGITAL CONVERTERS
IIIIIIIIIII ANALOG
WDEVICES
FEATURES
AC and DC Characterized and Specified
100k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
80 dB S/N+D (K Grade)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 MO Input Impedance
8 Bit Bus Interface (See AD779 for 16-Bit Interface)
On Board Reference and Clock
10 V Unipolar or Bipolar Input Range
PRODUCT DESCRIPTION
The AD679 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-hold amplifier
(SHA), a microprocessor compatible bus interface, a voltage reference and clock generation circuitry.
The AD679 is similar to the ADl679 in that it is specified for ac
(or "dynamic") parameters such as SIN+D ratio, THD
IMD which are important in signal processing
addition, the. AD679 is fully speci
are important in measurement app
The 14 data bits are accessed in two
opera
left justification. Data format is straight b·
mode and twos complement binary for bi
has a full-scale range of 10 V with a full pow
andwidth
1 MHz and a full linear bandwidth of 500 kHz. High inpu
impedance (10 MO) allows direct connection to unbuffered
sources without signal degradation. Conversions can be initiated
either under microprocessor control or by an external clock
asynchronous to the system clock.
This product is fabricated on Analog Devices' BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.
14-Bit 100 KSPS
Complete Sampling ADC
AD679 I
AD679 FUNCTIONAL BLOCK DIAGRAM
CS
sc
DE
EOCEN SYNC
EOC
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The AD679 minimizes
external component requirements by combiuing a high speed
sample-hold amp .
), ADC, 5 V reference, clock and
digital .
e chip. This provides a fully speci.on unattainable with discrete
The AD679 is specified for both dc and
ifications (such as INL, gain and offntrol and measurement applications.
tions (such as SIN + D ratio, THD and IMD) are
signal processing applications.
SE: The pinout is designed for easy board laytwo read output provides compatibility with
- It buses. Factory trimming eliminates the need for calibration modes or external trimming to achieve rated
performance.
4. RELIABILITY: The AD679 utilizes Analog Devices'
monolithic BiMOS technology. This ensures long term reliability compared to multichip and hybrid designs.
The AD679 operates from +5 V and ±12 V supplies and dissipates 720 mW. A 28-pin plastic DIP and a 0.6" wide ceramic
DIP are available. Contact factory for surface-mount package
options.
Screening to MIL-STD-883C Class B is available.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-111
SPECIFICATIONS
T...., Vee = +12 V :l:5~, VEE = -12 V :1:5%, V
AC SP'ECIFICATIONS fl. =10.009
kHz unless otherwise noted)1
DD
(Tmlnto
Parameter
Min
SIGNAL-TO-NOISE AND DISTORTION (SIN+D) RATIO
-0.5 dB Input (Referred to -0 dB Input)
- 20 dB Input (Referred to - 20 dB Input)
-60 dB Input (Referred to -60 dB Input)
78
58
18
TOTAL HARMONIC DISTORTION (THD)
@ +25"C
T min
to
Tmax
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
= +5 V :1:10%, fSAMPLE = l00KSPS,
AD679J/S
Typ
Max
Min
79
59
19
80
60
20
AD679KJT
Typ
Max
81
61
21
dB
dB
dB
-90
-84
-90
-84
0.003
-88
0.004
0.006
-82
0.008
0.003
-88
0.004
0.006
-82
0.008
dB
%
dB
%
-90
-84
-90
-84
dB
FULLPOWERBAND~DTH
MHz
FULL LINEAR BANDWIDTH
500
INTERMODULATION DISTORTION (IMDi
2nd Order Products
3rd Order Products
INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
dB
dB
ee = +12 V :1:5%, VEE = -12 V:1:5%, VDD = +5 V:1:10%)
Test Conditions
Min
Max
Units
0.8
10
10
10
V
V
j.l.A
j.l.A
pF
0.4
10
10
V
V
V
j.t.A
pF
2.4
VIN
VIN
LOGIC OUTPUTS
VOH
High Level Output Voltage
VOL
Ioz
Coz
-84
-84
d to a -0 dB(9.997 V p-p) input signal
DIGITAL SPECIFICATIONS
LOGIC
VIH
VIL
IIH
IlL
CIN
kHz
-90
-90
NOTES
'f'N amplitude = -O.S dB (9.44 V pop)
unless otherwise noted.
'fA = 9.08 kHz, fa = 9.58 kHz, with fSAM
Parameter
Units
Low Level Output Voltage
High Z Leakage Current
High Z Output Capacitance
=
=
5V
OV
IOH = 0.1 rnA
IOH = 0.5 rnA
IOL = 1.6 rnA
VIN = 0 or 5 V
4.0
2.4
NOTES
Specifications shown in boldface are tested on all devices at final elecIrical test with worst case supply voltages at 0"<:, +25"<: and + 70"<:. Results from
those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. .
Specifications subject to change without notice.,
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-112 ANALOG-TO-DIGITAL CONVERTERS
AD679
DC SPECIFICATIONS
(lmln to 1m••, Vee = +12 V ±5%, VEE = -12 V ±5%, Voo = +5 V ±10% unless
otherwise indicated)
Parameter
Min
TEMPERATURE RANGE
0
ACCURACY
Resolution
Integra! Linearity Error @ 25°C
14
AD679J
Max
Typ
+70
AD679K
Typ Max
0
+70
14
±2
±2
Tmin to Tmax
Differential Linearity
Unipolar Zero Error! (@ 25°C)
Bipolar Zero Error! (@ 25OC)
Gain Error!,2 (@ 25OC)
Temperature Drift (Coefficients)
Unipolar Zero 3
Bipolar Zero3
Min
14
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
Input Resistance
Input Capacitance
Input Settling Time
Aperture Delay
Aperture Jitter
INTERNAL VOLTAGE REFERENCE
Output VoltageS
External Load
Unipolar Mode
Bipolar Mode
POWER SUPPLIES (Tm;n to T max)
Power Supply Rejection
Vee = + 12 V ±5%6
VEE = -12 V ±5%
Voo = +5 V ±10%
Operating Current
Icc
lEE
Ioo
Power Consumption
±4
±4
±8
±6 (8)
±6 (8)
±24 (33)
±6 (8)
LSB
LSB
LSB
LSB
+10
+5
V
V
MO
pF
14
Gain3
Gain4
I
20
150
4.95
4.98
18
2S
°C
Bits
LSB
LSB
Bits
LSB
LSB
LSB
±I
±2
±8
±8
±16
Units
,...S
V
+1.5
+0.5
+1.5
+0.5
rnA
rnA
±4
±4
±4
±4
±4
±4
LSB
LSB
LSB
20
32
12
rnA
rnA
rnA
720
mW
8
12
S60
720
18
25
8
S60
(ppm!OC)
(ppmfOC)
(ppmfOC)
(ppmfOC)
ns
ps
5.02
20
32
II
NOTES
I Adjustable to zero. See Figures 5 and 6.
'Includes internal voltage reference error.
'Includes internal voltage reference drift.
'Excludes internal voltage reference drift.
'With maximum external load applied.
61.4 V headroom is required between Vee and AIN.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at O"C, + 2S'C and +70'C. Results from those
tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-113
SPECIFICATIONS
DC SPECIFICATIONS
(Tml.
to T...., Vee
= +12 V±5%, VEE = -12 V±5%, VDD = +5 V ±10% unless
otherwise indicated)
Parameter
Min
AD679S
Typ Max
Min
TEMPERATURE RANGE
-55
+125
-55
ACCURACY
Resolution
Integral Linearity Error (@ 25"C)
Tmin to Tmax
Differential Linearity (@ 25"C)
Tmin to Tmax
Unipolar Zero Error l (@ 25"C)
Bipolar Zero Error l (@ 25"C)
Gain Error l ,2 (@ 25"C)
Temperature Drift (Coefficients)
Unipolar Zero3
Bipolar Zero3
Gain3
Gain4
AD679T
Max
Units
+125
"C
14
14
±2
TBD
±1
TBD
14
14
14
13
±8
±8
±16
±4
±4
±8
(10)
(10)
(50)
(10)
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
Input Resistance
Input Capacitance
Input Settling Time
Aperture Delay
Aperture Jitter
INTERNAL VOLTAGE REFERENCE
Output VoltageS
External Load
Unipolar Mode
Bipolar Mode
Typ
1
20
150
4.95
POWER SUPPLIES (Tmin to T maJ
Power Supply Rejection
Vcc = +12 V ±5%6
VEE = -12 V ±5%
Voo = +5 V ±10%
Operating Current
Icc
lEE
Ioo
Power Consumption
5.05
18
25
8
560
LSB
LSB
LSB
LSB
V
+1.5
+0.5
+1.5
+0.5
mA
mA
±4
±4
±4
±4
±4
±4
LSB
LSB
LSB
20
32
12
720
mA
mA
mA
mW
18
25
8
560
(ppmfC)
(ppmrC)
(ppnifC)
(PpmfC)
V
V
Mil
pF
....s
ns
ps
5.02
20
32
12
720
4.98
Bits
LSB
LSB
Bits
Bits
LSB
LSB
LSB
NOTES
1Adjustable to zero. See Figures 5 and 6.
zlncludes internal voltage reference error.
'Includes internal voltage reference drift.
4Bxc:ludes internal voltage reference drift.
'With maximum external load applied.
61.4 V headroom is required between Vex; and AIN.
Specifications shown in boldfac:e are tested on all devices at final electrical test with worst case supply voltages at - SS"C, +2S"C, and + l2S"C. Results from
thoae tests are uoed to calculate outgOing quality levels. All min and max SpeciflCBtions are guaranteed, although only those shown in bnIdface are tested.
Specifications subject to change without notice.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-114 ANALOG-TO-DIGITAL CONVERTERS
Timing - AD679
TIMING SPECIFICATIONS
=
(All device types Tm;. to Tm.., Vee +12 V ±5%,
VEE -12 V ±5%, VDD +5 V ±10%)
=
=
Parameter
Symbol
Min
SC Delay
Conversion Rate'
Convert Pulse Width
Aperture Delay
Conversion Time
Status Delay
Access Time2
Float Delay'
Update Delay
Format Setup
DE Delay
Read Pulse Width
Conversion Delay
EDCEN Delay
tsc
50
Max
10
tcR.
tcP
tAD
tc
tSD
tDA
tFO
tUD
tps
150
5
20
0
8.5
400
10
80
100
200
60
20
150
400
20
toE
tRP
tCD
tEO
Units
ns
....s
ns
ns
....s
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
'Include. Acquisition Time.
'Measured from the falling edge of 0EiE0CEN (0.8 V) to the
See Figure 4; CoUT = 100 pF.
'Measured from the rising edge of
See Figure 4; COOT = 10 pF.
Specifications subject to change wi
sc
tAD~
SHA
TRACK
I-'
t cD -./
I
I
~ISD~ lei
HOLD
HOLD
L.I~tUD~
EOC2
CONTENT OF
OUTPUT
REGISTER
100-
I
TRACK
DATA 0
X
DATAl
I
\.Ai
liE'
NOTE
'EOC IS A THREE·STATE OUTPUT IN SYNCHRONOUS
MODE AND AN OPEN DRAIN OUTPUT IN ASYNCHRO·
NOUS. ACCESS (tBA) AND FLOAT (t'D) TIMING SPECIFI·
CATIONS DO NOT APPLY IN ASYNCHRONOUS MODE
WHERE THEY ARE A FUNCTION THE TIME CONSTANT
FORMED BY THE 10 pF OUTPUT CAPACITANCE AND
THE PULL-UP RESISTOR.
NOTES
'IN ASYNCHRONOUS MODE. STATE OF CS DOES NOT AFFECT OPERATION. SEE
THE START CONVERSION TRUTH TABLE FOR DETAILS.
2EOCEN = LOW. IN SYNCHRONOUS MODE. EDC IS A THREE-STATE OUTPUT. IN
ASYNCHRONOUS MODE. EDC IS AN OPEN DRAIN OUTPUT. SEE CONVERSION
TRUTH TABLE.
'DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
Figure 3. EOC Timing
TEST
ACCESS TIME HIGH Z TO LOGIC LOW
FLOAT TIME LOGIC HIGH TO HIGH Z
ACCESS TIME HIGH Z TO LOGIC HIGH
FLOAT TIME LOGIC LOW TO HIGH Z
5 V
100 pF
5 V
10 pF
OV
oV
l00pF
10 pF
Figure 1. Conversion Timing
Vep
DB7-DBO
----.:~~§:~~>------. . . GL~O~W~B~YT~E)
Figure 4. Load Circuit for Bus Timing Specifications
Figure 2. Output Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-115
CONVERSION CONTROL
In synchronous mode (SYNC = HIGH), both Chip Select (CS)
and Start Convert (SC) must be broUght LOW to start a conversion. CS should be LOW tsc before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started
by bringing SC low, regardless of the state of CS.
Before a conversion is started, End Of Convert (EOC) is HIGH
and the sample-nold is in track mode. Mter a conversion is
started, the sample-hold goes into hold mode and EOC goes
LOW, signifying that a conversion is in progress. During the
conversion, the sample-hold will go back into track mode and
start acquiring the next sample.
In track mode, the sample-hold will settle to ±0.003% (14 bits)
in 1.5 ILS maximum. The acquisition time does not affect the
throughput rate as the AD679 goes back into track mode more
than 2 ILS before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW.
When the conversion is fmished, EOC goes HIGH and the
result is loaded into the output register after a period of time
tUD' Bringing OE LOW tOE after CS goes LOW makes the output register contents available on the output data bits
(DB7-DBO). A period of time te~ is required after OE is
brought HIGH before the next SC instruction is issued. This
allows internal logic states to reset and guarantees minim
aperture jitter for the next conversion.
END OF CONVERT
In asynchronous mode, End of Convert (EOC) is an open drain
output (requiring a minimum 3 kn pull-up resistor) enabled by
End of Convert ENable (EOCEN). In synchronous mode, EOC
is a three-state output which is enabled by EOCEN and CS. See
Conversion Status Truth Table. Access (tBA) and float (tFD)
timing specifications do not apply in asynchronous mode where
they are a function of the time constant formed by the external
load capacitance'and the pull-up resistor.
OUTPUT ENABLE OPERATION
The data bits (DB7-DBO) are three-state outputs that are
enabled by Chip Select (CS) and Output Enable (OE). CS
should be LOW tOE before OE is brought LOW. Output
Enable (OE) must be toggled to update the output register.
The output is read as a 16-bit word, with the high byte read
first, followed by the low byte. High Byte Enable (HBE) controls the output sequence. The 14-bit result is left justified
within the 16-bit field.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In
mode (BIPOFF tied to REFOUT),
ent binary.
consisting of one SC instruction, is
to reset internal logic.
If SC is held LOW, conversions .
will go HIGH for approximately 1.
INPUTS
START CONVERSION TRUTH TAB
INPUTS
SYNC
Synchronous
Mode
Asynchronous
Mode
CS
SC
1
X
0
o
o
o
t.
No Conversion
Start Conversion
t.
0
Start Conversion
(Not Recommended)
0
0
Continuous Conversion
X
1
No Conversion
X
t.
Start Conversion
X
0
Continuous Conversion
NOTES
1 = HIGH voltage level.
o = LOW voltage level.
X = Don't care.
= HIGH to LOW transition. Must stay low for t = lop.
Synchronous
Mode
STATUS
0
0
Converting
0
0
1
X
VIN
0
5.00000 V
9.99939 V
Output Code
Asynchronous
Mode*
000 ... 0
100 ... 0
111 •.• 1
Either
HighZ
Either
0
X
0
0
Converting
0
X
0
High Z
Not Converting
0
X
HighZ
Either
NOTES
1 = HIGH voltage level.
o = LOW voltage level.
X = Don't care.
= 0.61 mV)
Output Code
100
III
000
010
Oll
HighZ
OUTPUT ENABLE TRUTH TABLE
Bipolar Coding
(Twos Complement)
VIN
-5.00000 V
-0.00061 V
0
+2.50000 V
+4.99939 V
Not Converting
X
INPUTS
Unipolar Coding
(Straight Binary)
0
*EOC requires a pull-up resistor in asynchronous mode.
t.
14-BIT MODE CODING FORMAT (1 LSB
OUTPUT
CS EOCEN EOC
...
...
...
...
...
0
1
0
0
1
HBE
Unipolar or
Bipolar
(CSUOE)
X
1
0
1
~
~
.I I Idj I ..I
OUTPUTS
DB7 .•. DBO
HighZ
~ ~
c
elf g h
lJklmnOO
NOTES
1 = HIGH voltage level.
• = MSB.
o = LOW voltage level.
n = LSB.
X = Don't care.
t. = HIGH to LOW transition. Must
U = Logical OR.
stay low for t = tap.
Data coding is binary for Unipolar Mode and 20 complement binary for
Bipolar Mode.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-116 ANALOG·TO-DIGITAL CONVERTERS
AD679
ABSOLUTE MAXIMUM RATINGS·
With
Respect
Specification
To
Min
AGND
AGND
Vee
VEE
Vee
Voo
VEE
AGND
AIN,REF'N
REF'N
REFIN
Digital Inputs
Digital Outputs
Max Junction
Temperature
Operating Temperature
J and K Grades
S and T Grades
Storage Temperature
Lead Temperature
(10 sec max)
DGND
DGND
AGND
VEE
Vee
DGND
DGND
-0.3
-18
-0.3
0
-1
-12
0
VEE
-0.5
-0.5
BIN CONFIGURATION
Max
Units
+18
+0.3
+26.4
+7
+1
+12
V
V
V
V
V
V
V
V
V
V
Vee
0
+7
Voo +0.3
175
•
Voo
EOC
DB7
DB6
DB5
DB4
°C
AD679
DB3
TOP VIEW
(Not to Scalel
DB2
DB1
°C
0
-55
-65
DBO
DGND ORVoo
DGND ORVoo
'Stresses above those listed under '
permanent damage to the device.
operation of the device at these or
cated in the operational sections of this
sure to absolute maximum rating conditions
device reliability.
DGNDOR Voo
AD679 ORDERING GUIDE'
Temperature Range and Package Options2
Plastic DIP
(N-28A)
o to +700C
Ceramic DIP
(D-28A)
o to+70°C
Ceramic DIP
(D-28A)
-55°C to +l25°C
Integral Nonlinearity
SIN+D'
AD679JN
AD679KN
AD679JD
AD679KD
AD679SD
AD679TD
±2 LSB
±1 LSB
79 dB
81 dB
NOTES
'Por single cycle read (14 bits) interface to 16-bit buses, see AD779.
'See Section 14 for package outline information.
'Typical at 10kHz, -O.5dB input.
ESDSENSITI~TY
_________________________________________________________________
The AD679 features input protection circuitry cons,stmg of large "distributed" diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,
low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD679
has been classified as a Category A device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices' ESD Prevention Manual.
WARNING!
0
~~[)EV'"
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-117
AD679 PIN DESCRIPTION
Symbol
Pin No.
Type
Name and Function
AGND
7
P
Analog Ground. This is the ground return for AIN only.
AIN
6
Al
Analog Signal Input.
BIPOFF
10
Al
Bipolar Offset. Connect to AGND for + 10 V input unipolar mode and straight binary output
coding. Connect to REFoUT for ±5 V input bipolar mode and twos complement binary output
coding.
CS
4
Dl
Chip Select. Active LOW.
DGND
12,14
P
Digital Ground
DB7-DBO
26-19
DO
Data Bits. These pins provide all 14 bits in two bytes (8+6 bits). Active HIGH.
EOC
27
DO
End of Convert. EOC goes LOW when a conversion starts and goes HIGH when the conversion is fInished. In asynchronous mode, EOG is an open drain output and requires an external
3 kn pull-up resistor. See EOGEN and SYNC pins for information on EOG gating.
Dl
End of Convert Enable. Enables EOG pin. Active LOW.
HBE
IS
Dl
High Byte Enable. If LOW, output contains high byte. If HIGH, output contains low byte
(corresponding to the most recently read high byte).
OE
2
Dl
Output Enable. A down-going transition on OE enab
LOW.
REFIN
9
AI
REFoUT
8
AO
SC
3
DI
SYNC
13
DI
EOCEN
-
BO. Gated with CS. Active
EN are gated by CS. If tied
e independent of CS, and EOG is an open
resistor in asynchronous mode.
Vee
11
P
VEE
VDD
5
P
28
P
+5 V Digital Power.
16-18
U
These pins are unused and should be connected to DGND or VDD'
Type: AI = Analog Input.
AO = Analog Output.
DI = Digital Input (TTL and 5 V CMOS compatible).
DO = Digital Output (TTL and 5 V CMOS compatible). All DO pins are tbree-state drivers.
P = Power.
U = Unused.
Definition of Specifications
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the "Nyquist
Frequency" of a converter is that input frequency which is onehalf the sampling frequency of the converter.
SIGNAL·TO·NOISE AND DISTORTION (SIN+D) RATIO
SIN + D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the fust six harmonic components to the rms value of a full-scale input signal and is
expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a fullscale input signal.
This information applies to a product. under development. Its characteristics and speCifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-118 ANALOG-TO-DIGITAL CONVERTERS
Definition of Specifications - AD679
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1,2,3 . • . Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms are (fa + fb) and (fa - fb) and the third
order terms are (2 fa + fb), (2 fa - fb), (fa + 2 fb) and (fa 2 fb). The IMD products are expressed as the decibel ratio of
the rms sum of the measured input signals to the rms sum of
the distortion terms. The two signals applied to the converter
are of equal amplitude and the peak value of their sum is
-0.5 dB from full scale (9.44 V p-p). The IMD products are
normalized to a O-dB input signal.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA
At this point, the amplitude of the reco
has degraded by less than -0.1
tortion of the sampled input si
The AD679 has been designed to
allowing it to undersample input si
cantly above the converter's Nyquist freq
e
nal is suitably band-limited, the spectral co tent of the
signal can be recovered.
APERTURE DELAY
Aperture delay is a measure of the SHA's performance and is
measurea from the falling edge of Start Convert (SC) to when
the input signal is held for conversion. In synchronous mode,
Chip Select (CS) should be LOW before SC to minimize aperture delay.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the AID.
INPUT SETTLING TIME
Settling time is a function of the SHA's ability to track fast
slewing signals. This is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
This specification is 14 bits for the AD679j, K and T grades,
which guarantees that all 16,384 codes are present. The AD679S
grade specifies 13 bits NMC, which means that missing codes
do not occur adjacent to each other.
INTEGRAL LINEARITY ERROR (INL)
The ideal transfer function for a linear ADC is a straight line
drawn between "zero" and "full scale." The point used as
"zero" occurs 112 LSB before the first code transition. "Full
scale" is defmed as a level 1 112 LSB beyond the last code transition. Integral linearity error is the worst case deviation of a
code from the straight line. The deviation of each code is measured from the middle of that code.
Note that the linearity error is not user adjustable.
POWER SUPPLY REJECTION
ly will affect the full scale calibration.
r change in all lower order codes. The
. um change in the full scale transie in power supply voltage from the
um change in the parameter from the initial
5°C) to the value at T min or T max'
ode, the first transition should occur at a level
SB above analog ground. Unipolar zero error is the deviation of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
BIPOLAR ZERO ERROR
In the bipolar mode, the major carry transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value 112
LSB below analog ground. Bipolar zero error is the deviation of
the actual transition from that point. This error can be adjusted
as discussed in the Input Connections and Calibration section.
GAIN ERROR
The last transition should occur at an analog value 1 112 LSB
below the nominal full scale (9.9991 volts for a 0-10 V range,
4.9991 volts for a ±S V range). The gain error is the deviation
of the actual level at the last transition from the ideal level with
the zero error trimmed out. This error can be adjusted as shown
in the Input Connections and Calibration section.
DIFFERENTIAL LINEARITY (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
linearity is the deviation from this ideal value. It is often specified in terms of resolution for which no missing codes (NMC)
are guaranteed.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS ~119
II
Application Information - AD679
INPUT CONNECTIONS AND CALIBRATION
The high (10 MO) input impedance of the AD679 eases the task
of interfacing to high source impedances or multiplexer channelto-channel mismatches of up to 300 O. The 10 V p-p full scale
input range accepts the majority of signal voltages without the
need for voltage divider networks which could deteriomte the
accuracy of the ADC.
The AD679 is factory trimmed to minimize offset, gain and linearity errors. In unipolar mode, the only external component
that is required is a 50 0 ± 1% resistor. Two resistors are
required in bipolar mode. If offset and gain are not critical,
even these components can be eliminated.
In some applications, offset and gain errors need to be more
precisely trimmed. The following sections describe the correct
procedure for these various situations.
BIPOLAR RANGE INPUTS
The connections for the bipolar mode are shown in Figure s. In
this mode, data output coding will be twos complement binary.
This circuit will allow approximately ±2S mV of offset trim
range (±40 LSB) and ±O.S% of gain trim range (±80 LSB).
UNIPOLAR RANGE INPUTS
Offset and gain errors can be trimmed out by using the configuration shown in Figure 6. This circuit allows approximately
±2S mV of offset trim range (±40 LSB) and ±O.S% of gain
trim range (±80 LSB).
The nominal'offset is 112 LSB so that the analog range that corresponds to each code will be centered in the middle of that
code (halfway between the transitions to the codes above and
below it). Thus the first transition (from 00 0000 0000 0000 to
000000 0000 0001) should nominally occur for an input level of
+ 112 LSB (0.305 mV above ground for a 10 V mnge). To trim
unipolar zero to this nominal value, apply a 0.305 mV signal to
AIN and adjust RI until the first transition is located.
The gain trim is done by adjusting R2. If the nominal value is
required, apply a signal 1 112 LSB below full scale (9.9997 V for
a 10 V range) and adjust R2 until the last tmnsition is located
(11 1111 1111 1110 to 11 Illl 1111 1111).
uired, BIPOFF should be congain adjustment is not required,
a fixed 50 0 ± 1% metal film resisected directly to REFIN, the additional
ximately 1%.
Either or both of the trim pots can be replaced wi
fixed resistors if the AD679 accumcy r
application. If the pins are sho
and gain errors will be approximat
To trim bipolar zero to its nominal
ue,
LSB below midrange (-0.305 mV for a
Rl until the major carry transition is located
to 00 0000 0000 0000). To trim the gain, apply a signal 1
LSB below full scale (+4.9997 V for a ±S V mnge) and
R2 to give the last positive transition (01 1111 1111 1110 to
1111 1111 1111). These trims are interactive so seveml iterations
may be necessary for convergence.
A single pass calibmtion can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale), using the same circuit. First, apply a signal
112 LSB above minus full scale (-4.9997 V for a ±5 V range)
and adjust Rl until the minus full scale transition is located
(10 0000 0000 0000 to 10 000 000 0001). Then perform the gain
error trim as outlined above.
:!:5 V INPUT
Figure 5. Bipolar Input Connections with Gain and
Offset Trims
t a 10 fLF tantalum capacitor be
een REFIN (Pin 9) and ground. This has the
ving the SIN + D ratio through filtering possible
. contributions from the voltage reference.
OT010 VINPUT
~
OFFSET
ADJUST
R1
100 k
AD679
BIPOFF
Figure 6. Unipolar Input Connections with Gain and
Offset Trims
BOARD LAYOUT
Designing with high resolution data conveners requires careful
attention to board layout. Tmce impedance is the first issue. A
1.22 rnA current through a 0.5 0 trace will develop a voltage
drop of 0.6 mV, which is 1 LSB at the 14 bit level for a 10 V
full scale span. In addition to ground drops, inductive and,
capacitive coupling need to be considered, especially when high
accumcyanalog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-120 ANALOG-TO-DIGITAL CONVERTERS
Application Information - AD679
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
The AD679 incorporates several features to help the user's layout. Analog pins (VEE' AIN, AGND, REFoUT' REF1N ,
BIPOFF, Ved are adjacent to help isolate analog from digital
signals. In addition, the 10 Mil input impedance of AIN minimizes input trace impedance errors. Finally, ground currents
have been minimized by careful circuit architecture. Current
through AGND is 200 IlA, with no code dependent variation.
The current through DGND is dominated by the return current
for DB7-DBO and EOC.
SUPPLY DECOUPLING
The AD679 power supplies should be well fIlte
lated, and free from high frequency
plies are not recommended du
spikes which can induce noise
Decoupling capacitors should be used
imity between all power supply pins
10 IlF tantalum capacitor in parallel with
capacitor provides adequate decoupling.
An effort should be made to minimize the trace length
n
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD679, associated analog input circuitry and interconnections as far as possible from logic circuitry. A solid analog
ground plane around the AD679 will isolate large switclIing
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit construction is preferred.
GROUNDING
If a single AD679 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD679. If multiple AD679s are used or the AD679 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at
eac1I chip. This prevents large ground loops whic1I inductively
couple noise and allow digital currents to flow through the analog system.
INTERFACING THE AD679 TO MICROPROCESSORS
The I/O capabilities of the AD679 allow direct interfacing to
general purpose and DSP microprocessor buses. The asynchronous conversion control feature allows complete flexibility and
control with minimal external hardware.
AD679 TO TMS32OC25
In Figure 7 the AD679 is mapped into the TMS320C25 I/O
space. AD679 conversions are initiated by issuing an OUT
instruction to Port 1. EOC status and the conversion result are
read in with an IN instruction to Port 1. A single wait state is
inserted by generating the processor READY input from is,
Port 1 and MSC. Address line AO provides HBE decoding to
select between the high and low bytes of data. This confIguration supports processor clock speeds of 20 MHz and is capable
of supporting processor clock speeds of 40 MHz if a NOP
instruction follows each AD679 read instruction.
II
R/W
A3
A2
A1
+5 V
C
•
A
74F138
SYNC
SiiiB
A0679
t-------ics
~~----------------------~~
--~--------------------------~EOC
Nr____________________________
~D~M
Figure 7. AD679 to TMS320C25 Interface
AD679 TO 80186
Figure 8 shows the AD679 interfaced to the 80186 microprocessor. This interface allows the 80186's built-in DMA controller to
transfer the AD679 output into a RAM based FIFO buffer of
any length, with no microprocessor intervention.
In this application the AD679 is configured in the asynchronous
mode, which allows conversions to be initiated by an external
trigger source independent of the microprocessor clock. Mter
each conversion, the AD679 EOC signal generates a DMA
80186
L:==::§@!!!!:===~DO-D7
EXTERNAL TRIGGER - - - - - - - - - - - - - - '
The following examples illustrate typical AD679 interface
configurations.
Figure 8. AD679 to 80186 DMA Interface
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-121
request to .Channell (DRQ1). The subsequent DMA READ
sequences the high and low byte AD679 data and resets the
interrupt latch. The system designer must assign a sufficient
priority to the DMA channel to ensure that the DMA request
will be serviced before the completion of the next conversion.
This configuration can be used with 6 MHz and 8 MHz 80186
processors.
AD679 TOZSO
The AD679 can be interfaced to the Z80 processor in an 110 or
memory mapped configuration. Figure 9 illustrates an 110 configuration, where the AD679 occupies several port addresses to
allow separate polling of the EOC status and reading of the data.
The lower address bit, AO, is used to select the high and low
order bytes of the result.
A useful feature of the Z80 is that a single wait state is automatically inserted during 110 operations, allowing the AD679 to be
used with Z80 processors having clock speeds up to 8 MHz.
+5V
SYNC
AD679 TO ANALOG DEVICES' ADSP-2100A
Figure 10 demonstrates the AD679 interfaced to an ADSP2100A. With a clock frequency of 12.5 MHz, and instruction
execution in one 80 ns cycle, the digiJ:al signal processor will
support the AD679 data memory interface with a ~o hardware
wait states.
The converter is configured to run asynchronously using a sampling clock. The EOC output of the AD679 is asserted at the
end of eacIl~onversion and creates a high priority interrupt to
the processor through IRQ3. Upon interrupt, the ADSP-2100A
immediately executes a data memory write instruction which
asserts HBE. In the following cycle, the processor starts a data
memory read (high byte read) by providing an address on the
DMA bus. The decoded address generates OE for the converter.
DE, together with logic and latches, is used to force the ADSP2100A into a two-cycle wait state by generating DMACK. The
read operation is thus started and completed within three processor cycles (240 ns). HBE is released during "high byte read."
This allows the processor to read the· lower byte of data as soon
as "high byte read" is complete. Low byte read is executed in a
similar manner and is
leted during the next 240 ns.,
r----------=ji-:~------~EOCEN
SAMPUNG
CLOCK
zao
os
A.r-----------------~~
SYNC
EOCEN
D1-D0I-.r-_________D_AT_A_._U_S--:~_1r_;.j
3k1l
+5V--~r-~_t~____~
AD679
Figure 9. AD679 to Z80 Interface
ClKOUT 1-.....________--'
DMWRr-----------------------~
I~~------------_OC~--------~~
DMD 15-.
DATA BUS
~------------------------~
Figure 10. AD679 to ADSP-2100A Interface
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-122 ANALOG-TO-DIGITAL CONVERTERS
200 MSPS Wideband
8-Bit AID Converter
AD770 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
2S0MHz Full Power Bandwidth
200 MSPS Guaranteed Conversion Rate
19pF typ Input Capacitance
Unipolar and Bipolar Input Range
+SV/-S.2V Power Supplies
Overflow and Underflow Signals
PRODUCT DESCRIPTION
The AD770 is an 8-bit analog-to-digital converter that is designed
for high-speed digitization of wide-bandwidth signals. It uses an
advanced VLSI bipolar process and a proprietary design to
achieve a combination of sampling rate and signal bandwidth
previously unavailable in flash ADCs.
The AD770 incorporates 257 high speed comparators that
are optimized for low input capacitance and wide bandwidth,
unaffected by temperature or signal amplitude. The multistage
comparator design reduces the probability of errors due to metastable states or insufficient gain.
AD770 FUNCfIONAL BLOCK DIAGRAM
ANAlOGINPUT
IAINI
REF£RENCE FORCE
IREFTFI
REFERENCE SENSE
(REFTS}
aUARTERTAP
IREFTQI
MlDf'OINTTAP
(REFMIDI
The decoding logic further reduces errors by using a two-stage
error-correcting architecture to virtually eliminate "sparkle
codes." Inputs and outputs are ECL compatible. Output format
controls allow stacking of two devices for 9-bit resolution. Overflow
and underflow output signals are provided.
The AD770 can operate with unipolar and bipolar signal ranges
up to 4V p-p. End-point reference Force and Sense connections
are provided to preserve high accuracy and minimize temperature
drift. Midpoint and quarter-point reference taps are also provided
to allow linearity or transfer function corrections.
OVERRANGE
(OVRI
00-D7
r
aUART£RTAP
IREFBOl
The AD770 is available in three grades. The JD and KD grades
are specified for operation over the 0 to + 70°C temperature
range, while the SD grade is specified for the - 55°C to + 125°C
temperature range. All grades are packaged in a 4O-pin ceramic
DIP ..Other package options are available on request; please
contact the factory.
REFERENCE SENSE
(REFBSI
PRODUCT HIGHLIGHTS
I. Performance: The AD770 is specified for operation at 200
MSPS. Full power bandwidth is 250MHz; small signal
bandwidth is 4OOMHz.
2. Ease of Use: The AD770 input has a typical capacitance of
19pF, simplifying input buffering .requirements. Bipolar and
unipolar input signals can be converted without offsetting.
Differential or single-ended clock inputs can be accommodated
by pin-strapping.
REFERENCE FORCE
__________ -1
8
UNDERRANGE
IUNRI
= LATCH
{REFBF)
3. Features: Taps are provided at mid- and quarter-scale points
of the reference ladder to pertnit linearity trimming or
piecewise-linear transfer function modification. Overflow and
underflow signals are also provided. These can be wire-or'd
to provide an indication that the input signal has exceeded
the range of the converter.
ANALOG-TO-DIGITAL CONVERTERS 3-123
•
DC SPEC IFI CAli 0NS (typical at +25"1:, Vee = 5.OY, VEE = - 5.2V, VREfIS= + 1.0y, V
REfBS =-1.oy,
Parameter
Conditions
Min
TEMPERATURE RANGE
AD770J, AD770K
AD770S
0
-55
RESOLUTION
DC ACCURACY
Linearity Error
Differential Linearity
Absolute Accuracy
REFERENCE LADDER
Ladder Resistance
LadderTC
Top Force·Sense Offset
Bottom Force-Sense Offset
ANALOG INPUT
Input Current
DIGITAL OUTPUTS
Logic HIGH (VOH)
Logic LOW (VOU
VBB
+70
+125
8
+ 25·C
Tmio-Tmax
+25°C
Tmio-Tmax
+25·C
Tmio-Tmax
Tmio-Tmax
Tmin-Tmax
200
0.34
3
3
V1N = -IVto + IV
Tmio-Tmax
17
Min
AD770K
Typ
Max
0
+70
8
-1
-1.25
-0.9
-1.25
-1.75
-2
160
Input Capacitance
DIGITAL INPUTS
Logic HIGH (VIlV
Logic LOW (V1L)
Logic HIGH Current (IIH)
Logic LOW Current (IIU
Input Capacitance
AD770l/S
Typ
Max
unless otherwise spacified)
19
+1
+1.25
+0.9
+1.25
+1.75
+2
-0.75
-1
-0.75
-0.9
-1
-1.25
260
160
5
5
300
500
22
17
Units
·C
·C
Bits
200
0.34
3
3
19
+0.75
+1
+0.75
+0.9
+1
+1.25
LSB
LSB
LSB
LSB
LSB
LSB
260
5
5
0
%/OC
LSB
LSB
300
500
22
",A
",A
pF
-0.7
-1.6
200
200
V
V
",A
Tmin-Tmax
-1.0
-1.9
-0.7
-1.6
200
200
-1.0
-1.9
3
1000 Load to - 2V
1000 Load to -2V
POWER SUPPLIES
Vcc
VEE
Icc (Analog)
Icc (Digital)
lEE (Analog)
lEE (Digital)
Power Consumption
Specifications subject to change without notice.
3-124 ANALOG-TO-DIGITAL CONVERTERS
-1.0
-1.9
-0.7
-1.6
-1.0
-1.9
-1.2
4.75
-5.46
5.0
-5.2
210
62
54
69
2000
-0.7
-1.6
V
V
V
5.25
-4.9
269
78
69
V
V
rnA
-1.2
5.25
-4.9
269
78
69
88
2550
4.75
-5.46
5.0
-5.2
210
62
54
69
2000
JJ.A
pF
3
88
2550
rnA
rnA
rnA
mW
AC SPECIFICATIONS (typical + 25"C, Vcc=5.DV, VEE = -5.2V, unless otherwise
Parameter
Conditions
Min
TIMING
Max Conversion Rate
Aperture Delay
Aperture Jitter
Pipeline Delay
Output Delay
Output Rise
Output Fall
Output Skew
T min - T max, lOOn Load to
-2V
200
DYNAMIC PERFORMANCE
(@200MSPS)
Full-Power Bandwidth
Small-Signal Bandwidth
Harmonic Distortion I
FIN
(MHz)
Signal-to-Noise Ratio l
AD770J/S
Typ
Max
AD770
noted)
Min
AD770K
Typ
Max
200
340
3
340
3
1.5
6
1.5
2
1
1
1.4
Full Scale
A1N(Volts)
±1
±1
±1
±1
±1
±1
±0.5
±0.5
±0.5
±0.5
±1
±1
±1
±1
±O.s
±0.5
±0.5
±0.5
1
10
50
100
1
10
50
100
1
10
50
100
1
10
50
100
1.5
2
1.5
6
1
1
1.4
2.35
250
400
50
43.5
35.5
25.5
49
42
38
31.5
44.0(7.0)
41.5 (6.6)
34.0(5.4)
25.0(3.9)
40.5 (6.4)
39.0 (6.2)
35.5 (5.6)
30.0(4.7)
2.35
250
400
53
45.5
36
26
52
43.5
39
32
44.5 (7.1)
42.0(6.7)
34.5 (5.4)
25.5 (3.9)
41.0(6.5)
39.5 (6.3)
35.5 (5.6)
31.0(4.9)
Units
MSPS
ps
psrms
Clock Cycles
ns
ns
ns
ns
MHz
MHz
dB
dB
dB
dB
dB
dB
dB
dB
dB (ENOB)
dB (ENOB)
dB (ENOB)
dB (ENOB)
dB (ENOB)
dB (ENOB)
dB (ENOB)
dB (ENOB)
NOTES
ISignal-to-Noise Ratio includes harmonics in the noise factor.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at fmal
electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those
shown in boldface are tested on all production units.
N+2
ANALOG
INPUT
N
ClK
ClK
00-07,
OVR.
UNR
=x
N-2
X
N-1
N
X
N+1
>C
Figure 1. AD770 Timing Diagram
ANALOG-TO-DIGITAL CONVERTERS 3-125
11
ANALOG INPUT
lAIN I
REFERENCE FORCE
(REFTF)
REFERENCE SENSE
,--
OVERRANGE ONE ZERO
IORZI
---------,
OVERRANGE
IREFTSI
IOVRI
aUARTERTAP
IREFTOI
w
0
0
M
0
150
L
MIDPOINT TAP
IREFMIDI
r--
00-07
a:
0
:r
I
''i:"
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L_
aUARTERTAP
IREFSOI
r- -I
I
I
I
I
I
I
I
I
I
I
I
I
REFERENCE SENSE
(REFBS)
UNDERRANGE
(UNR)
I
L _ __________ -1
REFERENCE FORCE
IREFSFI
AD770 Block Diagram
3-126 ANALOG-TO-DIGITAL CONVERTERS
~ =LATCH
AD770
AD770 PIN DESCRIPTION
•
AVcx;
NC
SYMBOL
PIN NO.
TYPE
DVcc
AGND
AlN
AVec
AV..
ClK
CLKBAR
DGND
DVcc
DV..
DO
Dl
D2
D3
D4
D5
P
AI
P
P
DI
DI
P
P
P
DO
DO
DO
DO
DO
DO
DO
DO
P
AV EE
D2
REFBO
Dl
D7
OGND
9.12
10.11
1.2.15
7.13
20
19
36.37
38.39
23.24
26
27
28
29
31
32
33
34
30
AVec
DO
ORZ
3
DI
OVR
35
DO
REFBF
REFBO
REFBS
REFMID
REFTF
REFTO
REFTS
UNR
17
14
16
8
4
6
5
25
AI
AI
AO
AI
AI
AI
AO
DO
V..
18
DO
AVec
ORZ
DVcc
DGND
REFTS
DGND
REFTO
OVR
AV",
D7
REFMID
D6
AD770
D5
AIN
TOP VIEW
D4
AIN
INot to Scale}
OGND
AGND
D3
REFBS
UNR
REFBF
DVEE
DV..
V ••
ClKBAR
CLK
NC
20
NC
NC = NO CONNECT
AD770 Pinout (40-Pin DIP)
DB
TYPE:
AI
AO
DI
DO
P
NAME AND FUNCTION
Analog Ground
Analog Input
+ 5V Analog Power
- S.2V Analog Power
Clock Input
Complementary Clock Input
Digital Ground
+ 5V Digital Power
- S.2V Digital Power
Data Bit Output (LSB)
Data BitOutput
Data Bit O~tput
Data BitOutput
Data BitOutput
Data BltOutput
Data BitOutput
Data BltOutput (MSB)
Digital Output Ground (collectors of
output transistors.)
Overranae Zero. Sets the Polarity of
the Data Bits for Overrenge
Condition. If ORZ = HIGH. DO-D7
are LOWfor Overrange Conditions.
Overrange Outpul.lndlcates that
AIN> (REFTS-0.5LSB).
Negative Reference Force
Negative ReferenceQuarter Point
Negative Reference Sense
Reference Midpoint
Positive Reference Force
Positive Reference Quarter Point
POlitlve Reference Sense
Underrangs Output. UNR
=HIGH
when AlN«REFBS - 0.5LSB).
EeL Threshold Outputfor Clocks
Analog Input
Analog Output
Digital Input
Digital Output
Power
ANALOG-TO-DIGITAL CONVERTERS 3-127
EVALUATION BOARD
The ADEB770 Evaluation Board allows the designer to easily
evaluate the performance o( the AD770. The ADEB770 includes
a pin-socketed AD770, an input signal buffer and an adjustable
reference generator. The input buffer can be bypassed for
maximum versatility.
On the output side, latched and buffered digital data is available
at the output connector along with an output clock. Decimation
hardware allows output data to be undersampled by factors of
16 through 2, allowing the user to interface the board to commonly
available logic analyzers.
A reconstructed analog output is also provided by an on-board
D/A converter.
ABSOLUTE MAXIMUM RATINGS*
Specification
With Respect to
Min
Max
Units
AVec
DVec
AV EE
DV EE
AVec
AV EE
AIN
AIN
CLK, CLKBAR, ORZ
REFTF, REFBF
AGND
CLK
AGND
DGND
AGND
DGND
DVec
DV EE
AGND
REFTF,REFBF
AGND
AGND
DGND
CLKBAR
-0.3
-0.3
-5.72
-5.72
-0.5
-0.5
-3
-4.3
-4.0
-3
-0.5
-4.5
5.5
5.5
0.3
0.3
0.5
0.5
+2.25
4.3
0
+2.25
0.5
4.5
110
30
3
30
4
1
40
175
3
+ ISO
V
V
V
V
V
V
V
V
V
V
V
V
rnA
rnA
rnA
rnA
rnA
rnA
rnA
°C
W
°C
36
10
°C/W
°C/W
lAIN
IREFTF,IREFBF
IREFTs,IREFBs
IREFMID' IREFTQ' IREFBQ
IRR
I cLK , ICLK BAR' I oRz I
Il)()..D1' IovR' IUNR
Junction Temperature
Power Dissipation ( + 25°C)
Storage Temperature
Thermal Resistance
6 JA (Still Air) (typ)
6Jdtyp)
-65
* Stresses
above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ORDERING GUIDE
Linearity
Error Max
@+2SoC
Package
Options*
Model
Package
Temperature
RangeOC
AD770JD
40-Pin Ceramic DIP
Oto +70
±I
D-40
AD770KD
40-Pin Ceramic DIP
Oto +70
±3/4
D-40
AD770SD
4O-Pin Ceramic DIP
-55to +125
±1
D-40
ADEB770-J
Evaluation Board for AD770
±1
-
ADEB770-2
Evaluation Board for AD770
±3/4
-
'See Section 14 for package outline information.
3--128 ANALOG-TO-DIGITAL CONVERTERS
Transfer Characteristics - AD770
DEFINITION OF SPECIFICATIONS
Linearity Error
Linearity Error is the deviation of the transfer function from a
reference line. For the AD770, the linearity error is measured
from the center of each code to the best-fit straight line.
Differential Linearity
In an ideal ADC, the code transitions are exactly ILSB apart.
The Differential Linearity is the deviation of the transition
spacing from the ideal value. A Differential Linearity spec of
less than ILSB signifies that there are no missing output codes
over the entire input range.
Absolute Accuracy
The Absolute Accuracy is the deviation of the center-point of
each code from a straight line drawn between the reference
sense points (REFTS, REFBS).
Force-Sense Offset
The Force-Sense Offset is the difference between the force and
sense pin voltages divided by the input range. This offset will
cause a corresponding offset error if the full-scale range is defined
w.r. t. the reference force lines rather than with respect to the
reference sense lines.
Input
AJN>
0.996V
0.988V
0.980V
-O.004V
-0.998V
-0.996V
-1.004
x
Output
ORZ
AIN<
0.996V
O.996V
0.988V
0.980V
0.973V
UNR OVR
X
X
X
11111111
00000000
11111111
I II I I I 10
I I I I I 101
0
0
0
0
0
I
I
0
0
0
0.004V
X
10000000
0
0
0.980V
0.998V
-0.996V
-1.004V
X
X
X
X
00000010
00000001
00000000
00000000
0
0
0
I
0
0
0
0
0
I
Table I. A0770 Truth Table
,.-------------,+--,
FF OVR
FF
0Vii
FE
OVR
1/2
LSB
FD OVR
Aperture Jitter
The sample-to-sample variation in aperture delay.
I
I
Pipeline Delay
The delay from the falling edge of CLK that samples the input
to the rising edge of CLK that outputs the corresponding digital
code.
80
Output Delay
The delay between the rising edge of CLK and the time when
the output bits reach the logic threshold value for bits DO to D7
and OVR.
::
,
/
~-f./
81
7F
,
I
I
~::~' i
112112
,/
"
UNR
•• UNR
Output Skew
The bit-to-bit variation in output delay for bits DO to D7 and
OVR.
I
~f_-li---jtrr---+--'
.. U N R '
REFBS
REFMID
REFTS
ANALOG INPUT VOLTAGE
Full-Power Bandwidth
The input frequency at which the amplitude of the reconstructed
output signal is reduced by 3dB for a full-scale input.
Figure 2. A0770 Transfer Function
Total Harmonic Distortion (THD)
The rms sum of the first six harmonic components divided by
the output signal amplitude. For frequencies above the Nyquist
frequency, the aIiased components are used.
I.S
1.2
1.0
011
!l,
.
u
~
~
I!!
I~,I IJVV IV'V
IfW '1" IAnlh. ~J iIo ,A
0
0.8
0 .•
If ItJ: ~ ~ ~ "''JI Is:I'lll ~
0.0
0.2
.J~
0.0
.... ~
=>
~ -0.2
.JI
ru'
.~r
3
'KI
NV
(!)
"". »tl
it.
:'1"1'"
VREF=OV/-2V
--
® VREF=+1YI+'~_ ® V +2V1OV ,"
~ -0.4
ENOB = (SNR - 1.8)/6.02
D7 ••••• DO
= Don'tcare
Aperture Delay
The delay between the falling edge of CLK and the time at
which AIN is sampled.
Signal-to-Noise Ratio (SNR)
The ratio of the signal amplitude to the rms sum of all other
spectral components, including harmonics but excluding dc.
SNR is expressed in dB and in Effective Number Of Bits (ENOB).
These two notations are related by the following formula for
full-scale inputs:
= + I.OOOV, REFBS = -I.()()()V)
(For REFTS
AEF ""
-0.8
-0.8
-1.0
o
20
40
60
80
100 120 140 160 180 200 220 240 255
OUTPUT CODE
Figure 3. Typical Absolute Accuracy vs. Output Code for
Various Range Offsets
ANALDG-TO-D/GITAL CONVERTERS 3-129
II
Dynamic Performance
I
I
I.!.
Vee= +S.25V. VEI!= -5.46V@ -55OC
150
--
----
).- r-
~
1 '00
I: !J
~
i!-50
1/
VI v---
-100
-150
1--
I" @25"C
NOMiNAl SUPPUES
25
-0.4
Z4
-0.6
23
22
/~
21
I-
..-
.-
20
-< I'-- :l'J::.'fcITANCE
-1.6
-1.0
-0.6
0.6
1.0
-1.2
....
;:
0
....
~-1.4
-
= t:---:-:
r-
-
-
v••
r-- -I
NOMINAL SUPPUES
VEE = -4.94V
-2
-50
Vo ,
~
!
i
v.. =_ 5.46V
I
-25
26
50
76
100
125
TEMPERATURE- "C
250
-
g
11
-1.8 F--VQL
Vo ,
2.0
225
Icc (ANALOG)
,
-1
18
Figure 4. Input Current and Input Capacitance vs.
Input Voltage
~
f
w
~'"
~
-1.8
INPUT VOLTAGE - V
200
I
-0.8
>,
19
17
-2.0
'BI .
~
t:::==- ~ r:-
Figure 5. Logic Levels vs. Temperature
f----::::
l00r----r----,-----r----r----,-----r----,
1: Vee = +S.ZSV VEE = -5.48V
2: Vee = + S.OOV V rE = - 5.2DY
3: Vee= +4.7SV Va:= -4.94V
I---
75r----+----~----r----+----~_=~~-=~
1, '75 ~
1:::::= ~ t-150
!Zw
iii
125
1: Vee = +S.25V VE'E=-5.46V
2: Vee= +5.00V VEE = -S.20V -
"~ 100
u
.
."
3: Vee= +4.7SV V EE =-4.94V
76
25r_--1---~----+_---r----r_--1---~
50
Icc (DIGITAl!
25
o
-50
-25
25
50
TEMPERATURE - "C
76
100
Figure 6. Icc vs. Temperature
125
~·~50~---~25~--~----25~---50=---~76~--~,~00~~,25
TEMPERATURE - "C
Figure 7. lEE vs. Temperature
11
-jl
A: F.,=12.6122'MHI
B: F.,=I00.0'22'MHz
Figure 8. Reconstructed Output of AD770
Decimated by 1:32@,200MSPS
3-130 ANALOG-TO-DIGITAL CONVERTERS
Figure 9. Smith Chart: Input Impedance Normalized to
50n vs. Input Frequency
AD770
AIN = 25% OF j:1V FULL SCALE
AIN=95% of ±1V FULL SCALE
1
FUNDAMENTL
......
-'0
"
Vr
DC OFFSET/
-20
~
-30
-""/
-40
-50
r----.;
-
2ND HARMONIC
•
.0
~
[J \
:::.-:3~DI HtRMD7'C
....,, -.0
."
~
~
lE
'\
C
~
.00
.000
In
I
i'-
± .2V FULL SCALE
iii
~
Z
5
..
4
~
3
~
.
-40
I
-50
I
-35
i':
-30
-25
~
~
-60
-20
-70
-'5
-so
-100
1000
'00
~
.,
!/!
25.... FULL SCALE RANGE
30
• W 20
40
~
I
50
II
so
'Iii"' n
II
n
~
00 00
!
~
-20~-+--~--+---+--1---+--~--+---~~
~
.. I----l---+---+---+--+---+---+-....-t---!--!H
~ -50 I II II I II I I II
-~~-+--+---r--+--~--t--1---r--t-~
~
~ -40
~~
20
~
!2
In
~' ~I'~1'1
''rlf n,
I
-.0~-4---+--~--~--1---1---+---~-4--~
z0
12
I
'1"'IWlf~~ ~l~
Figure 13. 1024pt FFT of AD770 Output @ 200 MSPS.
~N=5MHz at ± 1V Full Scale
~JJ LLLJ RUJE
:---.
A,
FREOUENCY - MHz
Figure 12. SNR vs. Input Frequency in ENOB and dB
40
.000
"
INPUT fREQUENCY - MHz
so-t. FULL SCALE RANGE
.0
.00
INPUT FREQUENCY - MHz
II
\
...., -40
. -50
-90
50
2NDH+++k
I
I\'\
'0
h
3RD HARMONIC
-30
~~
~
0.'
•
\
'-"'
-20
-40
I""--- :'\.
± .3V FULL SCALE
6
-
DC OFFSET
-.0
-45
Iii
-30
Figure ". Harmonic Distortion vs. Input Frequency @
200 MSPS: Small Signal
±I'VIF~~L SJLE
± .5V FULL SCALE
~
-20
INPUT FREQUENCV - MHz
Figure 10. Harmonic Distortion vs. Input Frequency @
200MSPS: Full Power
FUNDAMENTAL
r-
~
'0
J
~M lAAWhJ J~A tit, .lMl\I nu, ~ 1111 tl1M ,M"hll~
-7.
-60
-80
rr"l!lrr'~ 11tr"nf~lll
, '.WI~~ ~, IMl liT lllrl~
I
-00~-+--~--+---+--1---+--~--+---~-4
0.'
'0
'00
.000
INPUT FREQUENCY _ MHz
Figure 14. SNR vs. Input Frequency at ± 1V F.S. Input
-.00.~~.0~-2~0~~~~~40=-~50~~60~~20=-~SO~~OO~-.~00
FREQUENCY - MHz
Figure 15. 1024pt FFT of AD770 Output @ 200 MSPS.
~N=95MHz at ± 1V F.S.
ANALOG-TO-DIGITAL CONVERTERS 3-131
GROUNDING AND DECOUPLING
200
500
The user is advised to provide separate, low impedance analog
and digital ground planes and tie them together at one place on
the board, preferably at, or as near to, the ADC as possible.
The dominant consideration in the selection of bypass capacitors
for the AD770 is minimization of series resistance and inductance.
Ceramic and fIlm-type capacitors generally feature lower series
inductance than tantalum or electrolytic types. The capacitors
should be installed on the board with the shortest possible lead
lengths. Chip capacitors are optimal in this respect. As shown in
Figure 18, the analog ground plane provides bypassing for the
analog power supplies (AVcc, AVEE) as well as for the reference
top, bottom, mid and quarter voltages. The digital ground plane
should be used to bypass the digital supplies (DVcc, DVEE).
500
Zs
1. IMPEDANCE SEEN BY AD770:
Zs=200 + (501150) = 45fi
2. -3dB POINT AT AD770:
f.= (21f450·19pF)-'
f.=186MHz
Figure 17a. Network for 50£1 Shunt Termination
To prevent output ringing, a ferrite bead in series with DGND
Pins 36 and 37 is recommended. Output lines should be single
fanout, properly terminated lOon striplines for best results.
son
250
DRMNG THE AD770
The AD770 can be driven directly from most signal sources.
The termination of the signal source, however, will affect the
input bandwidth. Two possibilities are shown in Figure 16.
250
Zs
19pF
1. IMPEDANCE SEEN BY AD770:
Zs=25011250+500) = 190
2. -3dB POINT AT AD770:
f.= (21f190·19pF)-'
f.=441MHz
Rs
AD770
500
19pF
Figure 17b. Network for 25lJ Series and 25Jl Shunt
Termination.
NO . .
Figure 16a. 50lJ Shunt Termination
P08ITIV~ toi:'.~"--IT]
REF£R£NCEFORCE._-----{D
m:J~IIiI---- +5.OV
-2.0V
100n~CH
REFE~=v:eNSE - - - - - - - { I ]
-uv
---,-t---,.--ti:!
DATA
+S.OV
..~~-l_~==:{'~' "~
15 AVec
REFE~~~~~NS£
NEGATIV&:
1 REFBS
17 REFBF
~~:t~~+=~
REFERENCE FORCE
100.llEACH
-2.0V
-'S.2V
Figure 16b. 50lJ Termination (-6d8J Employing 25Jl
Series and 25lJ Shunt Resistors
NOmI,
Both terminations result in son to ground; however the network
of Figure 16b provides a lower impedance to the AD770 over
frequency as well as a higher - 3dB point at the device. The
trade-off is that Figure 16b attenuates the signal source by a
factor of two ( - 6dB). These effects may be illustrated by niodeling
the input to the AD770 as a 19pF capacitor and analyzing the
two termination networks as shown in Figure 17.
The - 6dB network requires an input signal with twice the
amplitude of the simple son shunt termination, but the benefits
can be easily justified. The termination impedance reaches a
high frequency value of 2Sn, versus 14n for the standard termination network. Another advantage is that the half-power
bandwidth is more than twice that of the standard son shunt
network.
3-132 ANALOG-TO-DIGITAL CONVERTERS
*_
rtl.I =
•
""
l000pFCERAMICCH.CAP
FERRITE BEAD
SEE FIGURE ,.
(7 ..
ANALOOGROUNDPLANE
.. =
DlGfTALGROUNDPlANE
Figure 18. AD770 Application Example
LATCHING THE OUTPUT DATA
A simplified AD770 timing diagram is illustrated in Figure 19.
The input signal is sampled on the falling edge of CLK. The
output data for that sample is delayed by the Pipeline Delay
plus the Output Delay. The Pipeline Delay is two CLK low
periods and one CLK high period, and thus depends on the
conversion rate and the clock duty cycle. Output Delay is measured
from the second CLK rising edge after the falling edge which
samples the analog input signal. Output Delay is not dependent
on the conversion rate.
Applying the AD770
If the Maximum Clock Delay for T D = T Omin is greater than the
Minimum Clock Delay for T D = T Dmax, a fixed clock delay set
between these rwo values can be used to latch the output of the
AD770.
N+2
ANALOG
INPUT
N+3
N+l
N
T Dmax+ TsurnaJ:
Min Clock Delay (for T D = T I>rnaJ = T Dmax + T su
If a variable delay line is used, some means must be provided to
verify that the delay is correctly set for each device. This can be
done by providing a test signal synchronized to the system
timing and adjusting the delay to the centerpoint of the range
that gives a stable output.
ANALOG-TO-DIGITAL CONVERTERS 3-133
•
----------------.---~-----------------AGND
REFTF
RI2
REFTS
RI2
R
REFTQ~
~
LJ
•••
~
b. CLK, CLK
I
R
RI2
REFMID
RI2
R
I
-~
c. ORZ, Vaa
R
-1000
AVec
Al2
DVcc:
REFBS
RI2
DOND
REF8F
AGND
~=0.81l
R
4
ANALOG
DIGITAL
OGND
WIRING RESISTANCE <211
_
-e-
TO COMPARATORS
=
SEE RGURE 21. FOR REFERENCE INPUT DETAIL.
DIGITAL OUTPUTS
a. Reference Ladder
AV..
DVEE PIN 23
(SUBSTRATE)
DV••
PIN 24
d. Internal Supply Connections
r----flAVcx;
DGND
OGND
-1000
REFERENCE
INPUTS
REFTS. REFBS ONLY
DV..
AVu LJ----~----~
e. Reference Input Detail
AVEE
f. Digital Outputs
g. Analog Input
Figure 21. Equivalent Circuits
3-134 ANALOG-TO-DIGITAL CONVERTERS
1IIIIIIII ANALOG
WDEVICES
FEATURES
AC and DC Characterized and Specified
100k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
80 dB S/N+D (K Grade)
Twos Complement Data Format (Bipolar Mode)
Straight Binarv Data Format (Unipolar Mode)
10 Mil Input Impedance
16-Bit Bus Interface (See AD679 for 8-Bit Interface)
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
PRODUCT DESCRIPTION
The AD779 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-hold amplifier
(SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.
The AD779 is similar to the AD 1779 in that it is specified for ac
(or "dynamic") parameters such as SIN+D ratio, THD
IMD which are important in signal process·
addition, the AD779 is fully spe .
are important in measurement a
The 14 data bits are accessed by
operation. Data format is straight bina
twos complement binary for bipolar mode.
scale range of 10 V with a full power bandw
a full linear bandwidth of 500 kHz. High input impedanc
(10 MO) allows direct connection to unbuffered sources w
signal degradation.
This product is fabricated on Analog Devices' BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.
14-Bit 100 KSPS
Complete Sampling ADC
AD779 I
AD779 FUNCTIONAL BLOCK DIAGRAM
•
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The AD779 minimizes
external component requirements by combining a high speed
sample-hold amplifier HA), ADC, 5 V reference, clock and
digital interfi
e chip. This provides a fully speci.on unattainable with discrete
The AD779 is specified for both dc and
specifications (such as INL, gain and offntrol and measurement applications.
tions (such as SIN + D ratio, THD and IMD) are
ignal processing applications.
USE: The pinout is designed for easy board laysingle cycle read output provides compatibility
16-bit buses. Factory trimming eliminates the need for
calibration modes or external trimming to achieve rated
performance.
4. RELIABILITY: The AD779 utilizes Analog Devices'
monolithic BiMOS technology. This ensures long term
reliability compared to multichip and hybrid designs.
The AD779 operates from +5 V and ±12 V supplies and dissipates 720 mW. A 28-pin plastic DIP and a 0.6" wide ceramic
DIP are available. Contact factory for surface-mount package
options.
Screening to MIL-STD-883C Class B is available.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-D/GITAL CONVERTERS 3-135
SPECIFICATIONS
Tma., Vee = +12 V ±5~, VEE = -12 V ±5%, Voo = +5 V ±10%, f SAMPLE = 100 lISPS,
AC SPECIFICATIONS fiN(Tmln=to10.009
kHz unless otherwise noted)!
AD779J/S
Parameter
Min
Typ
SIGNAL-TO-NOISE AND DISTORTION (SIN+D) RATIO
-0.5 dB Input (Referred to -0 dB Input)
-20 dB Input (Referred to -20 dB Input)
-60 dB Input (Referred to -60 dB Input)
78
58
18
79
59
19
TOTAL HARMONIC DISTORTION (THD)
@ +25"C
Min
80
60
20
AD779KIT
Typ
Max
81
61
21
Units
dB
dB
dB
-90
-84
-90
-84
dB
0.003
0.003
0.004
0.006
-82
0.008
dB
0.004
0.006
-82
0.008
-90
-84
-90
-84
dB
-88
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
Max
-88
FULLPOWERBAND~DTH
%
%
MHz
FULL LINEAR BANDWIDTH
500
INTERMODULATION DISTORTION (IMD),
2nd Order Products
3rd Order Products
kHz
-90
-90
-84
-84
dB
dB
NOTES
IfIN amplitude = -0.5 dB (9.44 V pop)
input signal unless otherwise noted.
'fA = 9.08 kHz, fB = 9.58 kHz, with fSA
DIGITAL SPECIFICATIONS
Parameter
LOGIC
VIH
VIL
IIH
IlL
CIN
INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Z Leakage Current
High Z Output Capacitance
Test Conditions
Min
Max
2.4
0.8
10
10
10
VIN = 5 V
VIN = OV
IOH
IOH
IOL
VIN
=
0.1 rnA
= 0.5 rnA
1.6 rnA
= 0 or 5 V
=
4.0
2.4
0.4
10
10
Units
V
V
IIA
IIA
pF
V
V
V
IIA
pF
NOTES
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply volrages at OOC, + 25"C and + 70"C. Results from
those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-136 ANALOG-TO-DIGITAL CONVERTERS
AD779
DC SPECIFICATIONS
(Tmln to 1ma•• Vee = +12 V :!:5%. VEE = -12 V :!:~%. VDD = +5 V :!:10%
unless othelWise indicated)
Parameter
Min
TEMPERATURE RANGE
0
ACCURACY
Resolution
Integral Linearity Error
@ +25°C
T min to Tmax
Differential Linearity
Unipolar Zero Error l (@ +25°C)
Bipolar Zero Errorl @ + 25°C)
Gain Error l •2 (@ +25°C)
Temperature Drift (Coefficients)
Unipolar Zer03
Bipolar Zer03
AD779j
Max
Typ
+70
14
Min
AD779K
Typ Max
0
+70
14
Bits
±2
±2
14
±I
±2
Gain3
Gain4
INTERNAL VOLTAGE REFERENCE
Output VoltageS
External Load
Unipolar Mode
Bipolar Mode
Icc
100
Power Consumption
±6 (8)
±6 (8)
±24 (33)
±6 (8)
LSB
LSB
LSB
LSB
+10
+5
V
V
MO
pF
f1s
ns
ps
20
ISO
5.05
4.95
POWER SUPPLIES (Tmin to T max>
Power Supply Rejection
Vee = +12 V ±5%6
VEE = -12 V ±5%
VOO = +5 V ±IO%
Operating Current
lEE
±4
±4
±8
LSB
LSB
Bits
LSB
LSB
LSB
14
±8
±8
±16
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
Input Resistance
Input Capacitance
Input Settling Time
Aperture Delay
Aperture Jitter
18
25
8
560
Units
°C
5.02
V
+1.5
+0.5
+1.5
+0.5
rnA
rnA
±4
±4
±4
±4
±4
±4
LSB
LSB
LSB
20
32
12
720
rnA
rnA
mA
mW
20
32
12
720
4.98
18
25
8
560
(ppmf'C)
(ppmf'C)
(ppmf'C)
(ppmf'C)
NOTE
lAdjustable to zero. See Figures 5 and 6.
2Includes internal voltage reference error.
'Includes internal voltage reference drift.
'Excludes internal voltage reference drift.
'With maximum external load applied.
61.4 V headroom is required between Vee and AIN.
Specifications shown in boldface are tested on all devices at fmal electrical test with worst case supply voltages at O°C, + 25°C and + 70°C. Results from those
tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-OIGITAL CONVERTERS 3-137
•
DC SPECIFICATIONS
(Tmi. to 1max, Vee = +12 V ±5%, VEE
unless otherwise indicated)
= -12 V ±5%, Voo = +5 V ±10%
AD779S
Parameter
Min
TEMPERATURE RANGE
-55
ACCURACY
Resolution
Integral Linearity Error @ + 25°C
Tmin toTmax
Differential Linearity
(@ +25"C)
TriD to Tmax
Unipolar Zero Error l (@ +25°C)
Bipolar Zero Error l (@ +25°C)
Gain Error l , 2 (@ +25°C)
Temperature Drift (Coefficients)
Unipolar Zero3
Bipolar Zero3
Gain3
Gain4
AD779T
Max
Min
+125
-55
14
Typ
Max
UDits
+125
"C
±1
TBD
Bits
LSB
LSB
±4
±4
±8
Bits
Bits
LSB
LSB
LSB
14
±2
TBD
14
13
14
14
±8
±8
±16
LSB
LSB
LSB
LSB
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
Input Resistance
Input Capacitance
Input Settling Time
Aperture Delay
Aperture Jitter
INTERNAL VOLTAGE REFERENCE
Output VoltageS
External Load
Unipolar Mode
Bipolar Mode
Typ
1
20
150
150
5.05
4.95
POWER SUPPLIES (Tmin to T max)
Power Supply Rejection
Vee = +12 V ±5%6
VEE = -12 V ±5%
Vnn = +5 V ±10%
Operating Current
lee
lEE
Inn
Power Consumption
18
25
8
560
V
V
MO
pF
ILS
ns
ps
5.02
V
+1.5
+0.5
+1.5
+0.5
rnA
rnA
±4
±4
±4
±4
±4
±4
LSB
LSB
LSB
20
32
12
720
rnA
rnA
rnA
mW
20
32
12
720
4.98
18
25
8
560
(ppmI"C)
(ppm/"C)
(ppm/"C)
(ppm/"C)
NOTE
I Adjustable to zero. See Figures 5 and 6.
'Includes internal voltage reference error.
'Includes internal voltage reference drift.
'Excludes internal voltage reference drift.
'With maximum external load applied.
61.4 V headroom is required between Vcc and AlN.
Specifications shown in boldface are tested on all devices at fInal electrical test with worst case supply voltages at -55"C, +25"C and+125'C. Results from those
tests are used to calculate outgOing quality levels. All min and max specifications are guaranteed, although ouly those shown in boldface are tested.
SpecifIcations subject to change without notice.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-138 ANALOG-TO-DIGITAL CONVERTERS
Timing - AD779
+12 V ±5%, VEE
Parameter
Symbol
Conversion Rate!
Convert Pulse Width
Aperture Delay
Conversion Time
Status Delay
Access Time2
Float Delay'
Update Delay
DE Delay
Read Pulse Width
Conversion Delay
Min
teR
tep
150
5
tAD
te
Max
Units
10
j.LS
20
ns
ns
8.5
j.LS
ns
ns
ns
ns
ns
ns
ns
tso
tBA
tpo
tuo
0
400
100
10
80
toE
20
150
400
200
tRP
te~
NOTES
'Includes Acquisition Time.
_ _ __
2Measured from the falling edge of OElEOCEN (0.8 V) to the time at which the data IinesIE
See Figure 4; GoUT = 100 pF. _ _ __
'Measured from the rising edge of OElEOCEN (2.0 V) to the time at w .
See Figure 4; GoUT = 10 pF.
SHA
= -12 V±5%,
•
rO.8 V.
TRACK
----~~------~------~~~
tel
EOC' - - - - - - -
Figure 3. EOC Timing
~--'/~tUD~
CONTENT OF
i----'-----OUTPUT _ _ _ _ _ _
DATA
0 _ _ _ _---J. .
DATA
1
REGISTER
__
I
X
'L--/~---
TEST
ACCESS TIME HIGH Z TO LOGIC LOW
FLOAT TIME LOGIC HIGH TO HIGH Z
ACCESS TIME HIGH Z TO LOGIC HIGH
FLOAT TIME LOGIC LOW TO HIGH Z
V CP
5 V
5 V
0 V
0 V
COUT
100 pF
10 pF
100 pF
10 pF
NOTES
'EOCEN = LOW.
"DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
Figure 1. Conversion Timing
Figure 4. Load Circuit for Bus Timing Specifications
Figure 2. Output Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-139
CONVERSION CONTROL
Before a conversion is started, End-of-Convert (EOC) is HIGH
and the sample-hold is in track mode. A conversion is started by
bringing SC LOW, regardless of the state of CS.
END-OF-CONVERT
End-of-Convert (EOC) is a three-state output which is enabled
by End-of-Convert ENable EOCEN.
Mter a conversion is started, the sample-hold goes into hold
mode and EOC goes LOW, signifying that a conversion is in
progress. During the conversion, the sample-hold will go back
into track mode and start acquiring the next sample.
OUTPUT ENABLE OPERATION
The data bits (DBI3-DBO) are three-state outputs that are
enabled by Chip Select (CS) and Output Enable (OE). CS
should be LOW tOB before OE is brought LOW. OE must be
toggled to update the output register. The output is read in a
single cycle as a 14-bit word.
In track mode, the sample-hold will settle to ±0.003% (14 bits)
in 1.5 ILS maximum. The acquisition time does not affect the
throughput rate as the AD779 goes back into track mode more
than 2 ILS before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW if
the maximum throughput rate is needed.
When the conversion is flnished, EOC goes HIGH and the
result is loaded into the output register after a period of time
tUD. Bringing OE LOW makes the output register contents
available on the output data bits (DBI3-DBO). A period of time
teD is required after OE is brought HIGH before the next SC
instruction is issued. This is to allow internal logic states to
reset and to guarantee minimum aperture jitter for the next
conversion.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFOUT),
output coding is twos-complement binary.
POWER-UP
A conversion sequence, consisting of one SC instruction, is
required after power-up to reset intemallogic.
14-BIT MODE CODING FORMAT (I LSB =0.61 mY)
Bipolar Coding
(Twos Complement)
If SC is held LOW, conversions will occur continuously. EOC
will go HIGH for approximately 1.5 ILS between conversio
VIN
Output Code
-5.00000 V
-0.00061 V
100 ... 0
o
+2.50000 V
+4.99939 V
lll ... I
000 ... 0
010 ... 0
011 ... I
INPUTS
Mode
Start Conversion
SC EOCEN CS OE
1
l.
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Conversion Status
X
X
X
0
0
Data Access
X
X
X
X
X
X
1
X
1
1
X
0
0
NOTES
U = Logical OR.
I = HIGH voltage level.
o = LOW voltage level.
X = Don't care.
l. HIGH to LOW transition. Must stay LOW for t
EOC
Status
No Conversion
Start Conversion
Continuous Conversion
0
I
HighZ
Converting
Not Converting
Either
HighZ
HighZ
MSB ... LSB
Three-State
Three-State
Data Out
= tc,..
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-140 ANALOG-TO-DIGITAL CONVERTERS
AD779
AD779 PIN DESCRIPTION
Symbol
Pin No.
Type
Name and Function
AGND
7
P
Analog Ground. This is the ground return for AIN Ollly.
AIN
6
Al
Analog Signal Input.
BIPOFF
10
Al
Bipolar Offset. Connect to AGND for + 10 V input unipolar mode and straight binary output coding.
Connect to REFoUT for ±5 V input bipolar mode and twos-complement binary output coding.
CS
12
Dl
Chip Select. Active LOW.
DGND
14
P
Digital Ground
DB13-DBO
28-15
DO
Data Bits. These pins provide all 14 bits in one 14 bit parallel output. Active HIGH.
EOC
2
DO
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the conversion
is finished. EOC is a three-state output. See EOCEN pin for information on EOC gating.
EOCEN
13
DI
End-of-Convert Enable. Enables EOC pin. Active LOW.
OE
3
DI
Output Enable. A down-going transition on OE enables data bits. Active LOW.
REFIN
9
AI
REFoUT
8
AO
SC
4
DI
Vee
II
P
VEE
V DD
5
P
Type: AI = Analog Input.
AO = Analog Output.
DI = Digital Input (TTL and 5 V C
DO = Digital Output (TTL and 5 V
P = Power.
AD779 ORDERING GUIDE l
Plastic DIP
(N-28A?
o to +70°C
Ceramic DIP
(D-28A)2
o to+70OC
Ceramic DIP
(D-28A)2
-55°C to + 1250C
Integral
Nonlinearity
SIN+D'
AD779JN
AD779KN
AD779JD
AD779KD
AD779SD
AD779TD
±2 LSB
±I LSB
79 dB
81 dB
NOTES
'For two cycle read (8+6 bits) interface to 8-bit buses, see AD679.
'See Section 14 for package outline information.
'Typical at 10 kHz, -0.5 dB input.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-141
II
ABSOLUTE MAXIMUM RATINGS·
With
Respect
Specification
To
Min
Vee
VEE
Vee
Voo
AGND
AIN, REFIN
REFIN
REFIN
Digital Inputs
Digital Outputs
Max Junction
Temperature
Operating Temperature
J and K Grades
S and T Grades
Storage Temperature
Lead Temperature
(10 sec max)
AGND
AGND
VEE
DGND
DGND
AGND
VEE
Vee
DGND
DGND
-0.3
-18
-0.3
0
-1
-12
0
VEE
-0.5
-0.5
PIN CONFIGURATION
Max
Units
+18
+0.3
+26.4
+7
+1
+12
Vee
0
+7
Voo +0.3
V
V
V
V
V
V
V
V
V
V
•
DB13
DB12
DB11
DB10
DB9
DB8
AD779
DB7
TOP VIEW
(Not to Scale)
DB6
175
°C
+70
+125
+150
OC
OC
OC
DB4
+300
°C
DB2
DBS
0
-55
-65
DB3
·Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and fun
operation of the device at these or any other conditions
cated in the operational sections of this specificatio
sure to absolute maximum rating
device reliability.
ESD SENSITIVITY-----The AD779 features input protection circuitry consl
polysilicon series resistors to dissipate both high energy
low energy pulses (Charged Device Model). Per Meth
has been classified as a Category A device.
DB1
DBD
. ibuted" diodes and
an Body Model) and fast,
5.2 of MIL-STD-883C, the AD779
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices' ESD Prevention Manual.
WARNING! ~
~~=:
Definition of SpeCifications
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the "Nyquist
Frequency" of a converter is that input frequency which is onehalf the sampling frequency of the converter.
SIGNAL·TO·NOISE AND DISTORTION (SIN+D) RATIO
SIN + D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
TOTAL HARMONIC DISTORTION (THO)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of a full-scale input signal and is
expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a fullscale input signal.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-142 ANALOG-TO-DIGITAL CONVERTERS
Definition of Specifications - AD779
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa
and fb, any device with nonlinearities will create distortion
products, of order (m + n), at sum and difference frequencies
of mfa ± nfb, where m, n = 0, 1, 2, 3 . . . Intermodulation
terms are those for which m or n is not equal to zero. For exam·
pie, the second order terms are (fa + fb) and (fa - fb) and the
third order terms are (2 fa + fb), (2 fa - fb), (fa + 2 fb) and
(fa - 2 fb). The IMD products are expressed as the decibel
ratio of the rms sum of the measured input signals to the rms
sum of the distortion terms. The two signals applied to the converter are of equal amplitude and the peak value of their sum is
-0.5 dB from full scale (9.44 V p-p). The IMD products are
normalized to a 0 dB input signal.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which th
slew rate limit of the sample-hold-amplifier (SHA) i
At this point, the amplitude of the rec
has degraded by less than - O.
tortion of the sampled input
The AD779 has been designe
mize
allowing it to undersample input sign
cantly above the converter's Nyquist fre
nal is suitably band-limited, the spectral
signal can be recovered.
APERTURE DELAY
Aperture delay is a measure of the SHA's performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the AID.
INPUT SETTLING TIME
Settling time is a function of the SHA's ability to track fast
slewing signals. This is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
INTEGRAL LINEARITY ERROR (INL)
The ideal transfer function for a linear ADC is a straight line
drawn between "zero" and "full scale." The point used as
"zero" occurs 112 LSB before the first code transition. "Full
scale" is defined as a level 1 112 LSB beyond the last code transition. Integral linearity error is the worst case deviation of a
code from the straight line. The deviation of each code is
measured from the middle of that code.
Note that the linearity error is not user adjustable.
POWER SUPPLY REJECTION
Variations in power supply will affect the full scale calibration.
This will result in a linear change in all lower order codes. The
specifications show the maximum change in the full scale transition point due to a change in power supply voltage from the
nominal value.
hange in the parameter from the initial
e value at T min or T max'
first transition should occur at a level
g ground. Unipolar zero error is the deviaactual transition from that point. This error can be
discussed in the Input Connections and Calibration
In the bipolar mode, the major carry transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value 112
LSB below analog ground. Bipolar zero error is the deviation of
the actual transition from that point. This error can be adjusted
as discussed in the Input Connections and Calibration section.
GAIN ERROR
The last transition should occur at an analog value 1 112 LSB
below the nominal full scale (9.9991 volts for a 0-10 V range,
4.9991 volts for a ±5 V range). The gain error is the deviation
of the actual level at the last transition from the ideal level with
the zero error trimmed out. This error can be adjusted as shown
in the Input Connections and Calibration section.
DIFFERENTIAL LINEARITY (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
linearity is the deviation from this ideal value. It is often specified in terms of resolution for which no missing codes (NMC)
are guaranteed.
This specification is 14 bits for the AD779J, K and T grades,
which guarantees that all 16,384 codes are present. The AD779S
grade specifies 13 bits NMC, which means that missing codes
do not occur adjacent to each other.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-143
II
Application Information
INPUT CONNECTIONS AND CALIBRATION
The high (10 M!l) input impedance of the AD779 eases the
task of interlacing to high source impedances or multiplexer
channel-to-channel mismatches of up to 300 !l. The 10 V p-p
full scale input rimge accepts the majority of signal voltages
without the need for voltage divider networks which could
deteriorate the accuracy of the ADC.
The AD779 is factory trimmed to minimize offset, gain and linearity errors. In unipolar mode, the only external component
that is required is a SO !l ± I % resistor. Two resistors are
required in bipolar mode. If offset and gain are not critical,
even these components can be eliniinated.
In some applications, offset and gain errors need to be more
precisely trimmed. The following sections describe the correct
procedure for these various situations.
BIPOLAR RANGE INPUTS
The connections for the bipolar mode are shown in Figure 5. In
this mode, data output coding will be twos complement binary.
This circuit will allow approximately ±25 mV of offset trim
range (±40 LSB) and ±0.5% of gain trim range (±80 LSB
Either or both of the trim pots can be repla
fixed resistors if the AD779 accura
application. If the pins are shorted t
and gain errors will be approximately
To trim bipolar zero to its nominal value, a
below midrange (-0.305 mV for a ±5 V range
1111 111
until the major carry transition is located (11 I
000000 0000 0000). To trim the gain, apply a signal I 112 L
below full scale (+4.9997 V for a ±5 V range) and adjust R2
give the last positive transition (01 1111 1111 1110 to 01 1111
1111 1111). These trims are interactive so several iterations may
be necessary for convergence.
A single pass calibration can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale), using the same circuit. First, apply a signal
112 LSB above minus full scale (-4.9997 V for a ±5 V range)
and adjust RI until the minus full scale transition is located
(lO 0000 0000 0000 to 10000000 0001). Then perform the gain
error trim as outlined above.
~5
V INPUT
OT010 VINPUT
~.
AD719
OFFSET
~.DJUST
Rl s.....JJ'VIr-_--!
100 k
BIPOFF
Figure 6. Unipolar Input Connections with Gain and
Offset Trims
UNIPOLAR RANGE INPUTS
Offset and gain errors can be trimmed out by using the configuis circuit allows. approximately
ration shown in Figure
(±40 LSB) and ±0.5% of gain
±25 mVof
112 LSB so that the analog range that cor. be centered in the middle of that
ansitions to the codes above and
sition (from 00 0000 0000 0000 to
1) should nominally occur for an input level of
mV .above ground for a 10 V range). To trim
this nominal value, apply a 0.305 mV signal to
1 until the first transition is located.
trim is done by adjusting R2. If the nominal value is
required, apply a signal 1 112 LSB below full scale (9.9997 V for
a 10 V range) and adjust R2 until the last transition is located
(11 111111111110 to 11 1111 1111 1111).
If offset adjustment is not required,BIPOFF should be connected directly to AGND. If gain adjustment is not required,
R2 should be replaced with a fixed SO !l ± 1% metal film resistor. If REFouT is connected directly to REFIN , the additional
gain error will be approximately 1%.
REFERENCE DECOUPLING
It is recommended that a lO J.LF tantalum capacitor be
connected between REFIN (Pin 9) and ground. This has the
effect of improving the SIN + D ratio through filtering possible
broad-band noise contributions from the voltage reference.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedarice is the first issue. A
1.22 mA current through a 0.5 !l trace will develop a voltage
drop of 0.6 mV,which is 1 LSB at the 14-bit level for a lO V
full scale span. In addition to ground drops, inductive and
capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Figure 5. Bipolar Input Connections with Gain and
Offset Trims
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-144 ANALOG~TO-DIGITAL CONVERTERS
AD779
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
The AD779 incorporates several features to help the user's layout. Analog pins (VEE' AIN, AGND, REFOUT> REF'N'
BIPOFF, Vcr:.) are adjacent to help isolate analog from digital
signals. In addition, the 10 MO input impedance of AIN minimizes input trace impedance errors. Finally, ground currents
have been minimized by careful circuit architecture. Current
through AGND is 200 fLA, with no code dependent variation.
The current through DGND is dominated by the return current
for DB13-DBO and EOC.
AD779 TO TMS320C25
In Figure 7 the AD779 is mapped into the TMS320C25 I/O
space. AD779 conversions are initiated by issuing an OUT
instruction to Port 1. EOC status and the conversion result are
read in with an IN instruction to Port 1. A single wait state is
inserted by generating the processor READY input from is,
Port I and MSC. This configuration supports processor clock
speeds of 20 MHz and is capable of supporting processor clock
speeds of 40 MHz if a NOP instruction follows each AD779
read instruction.
A'I------t
A
74F138
SUPPLY DECOUPLING
The AD779 power supplies should be well
lated, and free from high frequenc
plies are not recommended
spikes which can induce noise
Decoupling capacitors should be use
imity between all power supply pins
10 fLF tantalum capacitor in parallel wit
capacitor provides adequate decoupling.
An effort should be made to minimize the trace lengt
een
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD779, associated analog input circuitry and interconnections as far as possible from logic circuitry. A solid analog
ground plane around the AD779 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit construction is preferred.
GROUNDING
If a single AD779 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD779. If multiple AD779s are used or the AD779 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at
each chip. This prevents large ground loops which inductively
couple noise and allow digital currents to flow through the analog system.
•
A21-----ooi
AD
AD779
DATA BUS
14
Figure 7. AD779 to TMS320C25 Interface
Figure 8 shows the AD779 interfaced to the 80186 microprocessor. This interface allows the 80186's built-in DMA controller to
transfer the AD779 output into a RAM based FIFO buffer of
any length, with no microprocessor intervention.
80'86
L:==::i!D!:AT[!A].:WUSC==~ 00-013
50
EXTERNAL TRIGGER - - - - - - - - '
INTERFACING THE AD779 TO MICROPROCESSORS
The 1/0 capabilities of the AD779 allow direct interfacing to
general purpose and DSP microprocessor buses. The asynchronous conversion control feature allows complete flexibility and
control with minimal external hardware.
Figure 8. AD779 to 80186 DMA Interface
The following examples illustrate typical AD779 interface
configurations.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-145
The AD779 is asynchronous which allows conversions to be initiated by an. external trigger source independent of the microprocessor clock. After each conversion, the AD779 EOC signal
generates a DMA request to Channell (DRQ1). The subsequent DMA READ resets the interrupt latch. The system
designer must assign a sufficient priority to the DMA channel to
ensure that the DMA request will be serviced before the completion of the next conversion. This configuration can be used
with 6 MHz and 8 MHz 80186 processors.
AD779TO ZSO
The AD779 can be interfaced to the Z80 processor in an VO or
memory mapped configuration. Figure 9 illustrates an 1/0 configuration, where the AD779 occupies several port addresses to
allow separate polling of the EOC status and reading of the data.
A useful feature of the Z80 is that a single wait state is automatically inserted during VO operations, allowing the AD779 to be
used with Z80 processors having clock speeds up to 8 MHz.
AD779 TO ANALOG DEVICES ADSP·2100A
Figure 10 demonstrates the AD779 interfaced to an ADSP2l00A. With a clock frequency of 1.25 MHz, and instruction
execution in one 80 ns cycle, the digital signal processor will
support the AD779 data memory interface with two wait states.
The converter runs asychronously using a sampling clock. The
EOC output to the AD779 gets asserted at the end of each conversion and causes an interupt. Upon interrupt, the ADSP2l00A starts a data memory read by providing an address on the
DMA bus. The decoded address generates OE for the converter.
OE, together with logic and latches, is used to force the ADSP2100A into a two cycle wait state by generating DMACK. The
read operation is thus started and completed within three processor cycles (240 ns).
DMA
1----,
SAMPUNG
CLOCK
WR
RD
RD ~--------------~
WR
~J--+:::;L)-I----"1OE
cs
1------,
lORa
SYNC
EOCEN
Al-A7
AD779
zao
D0-013
N-______......:D:;;A:.:;TA;..;B:.:U::.S____---!>--'A
+5V
Imu~-------------oC~--------~~
--=-==____________--1
DMD 15-81-__________
Figure 9. AD779 to Z80 Interface
013 _ 0
Figure 10. AD779 to ADSP-2100A Interface
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-146 ANALOG-TO-DIGITAL CONVERTERS
r-IIANALOG
WDEVICES
FEATURES
Low Nonlin..rity:
Integral: :to.001%
DiHerantial: :t 0.00035%
Microcomputer-Based Design
Programmable Integration Time: 1 to 350ms
with Resolution from 7 to 18 Bits
Programmable Output Data Format
Auto-Zeroed Operation and Electronic Calibration
(No External Trim Potentiomaters)
Microprocessor Compatible Interface
High Throughput: Over 50 Conversions/Second
for Line Cycle Integration Period
High Normal Mode Rejection: 54dB at 60Hz
Small Size: 1.24" x 2.5" x 0.55" max
High Resolution, Programmable
Integrating AID Converter
ADl170 I
AD1170 FUNCTIONAL BLOCK DIAGRAM
•
APPUCATIONS
Date Acquisition Systems
Scientific Instruments
Medicel Instruments
Weighing Systems
Automatic Test Equipment
GENERAL DESCRIPTION
The AD1170 is a high resolution integrating AID converter
.intended for applications requiring high accuracy and high
throughput at low cost. A novel conversion architecture provides
the user with outstanding accuracy, stability and ease of use.
The ADII70 is a complete microcomputer-based measurement
subsystem, composed of three major elements: a highly precise
charge balancing converter, a single chip microcomputer, and a
custom CMOS controller chip. The ADII70 offers independendy
programmable integration time (from one millisecond to 350
milliseconds) and data format (offset binary or two's complement,
from 7 to 22 bits). The converter is fully auto-zeroed and exhibits
a span drift of only 9ppmI"C, assuring stable, accurate readings.
The AD1170 may be interfaced to any microcomputer based
system in a memory mapped or 110 mapped fasbion via an 8-bit
data bus. The AD 1170's advanced features are controlled by
simple commands sent to it via this bus.
The converter utilizes surface mount technology and is housed
in a small 1.24" x 2.5" x 0.55" package. It operates from ± I5V dc
and +5V dc power.
LEAVE Nle PINS UNCONNECTED
PRODUCT IUGHLIGHTS
1. The AD1170, unlike dual slope converters, offers the user
the capability of programming the integration time by selecting
one of seven preset integration periods or by loading an
arbitrary integration period over the interface bus.
2. The ADII70 architecture provides for user programmable
data format independent of the integration time. All data is
computed to 22-bit resolution and the user may specify any
resolution from 7 to 22 bits. Usable resolution will typically
be limited to I8-bits due to measurement and calibration
noise error.
3. Electronic digital calibration eliminates the need for trim
potentiometers. Calibration can be performed at any time by
applying an external reference voltage to the input and invoking
a calibration command. The calibration data is stored in an
internal nonvolatile memory chip.
4. Internal calibration cycles may be programmed to occur
whenever the convener is idle, assuring negligible offset drift
and only 9ppmf'C span drift.
5. The conversion rate is greater than 50 conversions per second
when programmed for 60Hz line cycle integration. The
maximum conversion rate is greater than 250 conversions per
second, using a one millisecond integration period.
ANALOG-TO-OIGITAL CONVERTERS 3-147
SPEC IFICAli 0NS (1pal
MiD
@
+25"&, Vs = ± 15Y, Vo = +5Y IIIIass otherwise spec:iIied)
Tn>
RESOLUTION'
ACCURACY
Integral Non1iDeari
Max
Units
18
Bits
.... 0.001
THROUGHPUT RATE'
Time (Integrate) = Ims
Time (Integrate) = 16.667ms
Time (Integrate) = lOOms
OUTLINE DIMENSIONS
Dimcnsioos shown in inc:hcs and (mm).
I:Q
% SPAN
250
conv/S
SO
9
conv/S
coDv/S
{14.01
O.1~1
T(caI)
lIDS
16.667ms
300ms
IOms
lOOms
300ms
±0.01
±0.0008
+0.00035
% SPAN
STABILITY
Span
±9
ppmSPANI"C
POWER SUPPLY REJECTION RATIO
(Span Errorvs. Analog
Supply Voltage)
60
ppm ofResdinsN .
IN UTCHARACTERISTICS
Analog Input Rsnge
de
de Plus Normal·Mode Voltage
Absolute Maximum
(Without Dsmsge)
Normal-Mode Rejection
@60Hz
@50Hz
Input Bias Current
Input Impedsnce
REFERENCE
Output Voltage
Output Current
InputRsnse
I:':: =::::1
Ii===
% SPAN
% SPAN
1.24131AIMAX
==f
==i1
1---1.'I25.4J----I'l
20
2.•
163.51
-5
+5
+6
-6
-30
+30
54
V
10
100
nA
MO
0.8
V
V
0.45
V
V
2.0
2.4
Rated Performance
4~ES
'-1J:(1.0)
;;1(2':; ~1~O~J..j
GRID
4 PLACES
9
4.75
15
5
min
18
5.25
12
110
0
-25
WARNING!
~~DEVICE
V
V
rnA
rnA
+70
+85
"C
"C
NOTES
'The usable resolution is limited by noise, which is largely determined by the integration period
and calibration period. Consul11he chart in Figure 4 for typical peak.-to-peak noise: versus
integration and calibration period.
'
IThc integrallincarity isdefmed as the deviation from. straighllinc drawn between the
endpoints of the converter. This specification is independent of gain and/or offset errors.
''Throughput Rate is calculated by the formula: T(inl) +1::lIiseconds - minimum conversions/second
Where T(int) isexpressed in numberofmilliseconds.
SpecifICations subject 10 change wilhout notice.
IBM PCIXTIAT" compatible <1HJJIUJlion blHJrd: AC5004 (see last
dsta sheet for description).
PIN DESCRIPTIONS
PIN
1
2,3
10
"
12
,.
,.
,.
17
,.
20
'*IBM PClXT/AT is a trademark of International Bulinc:ss Machines Corp.
21
Z3
26
29
30
31.32
33-40
8,9,13,
15.22.24
25,27
28
3-148 ANALOG-TO-DIGITAL CONVERTERS
0
CAUTION: OBSERVE PROPER PLUG-IN POLARITY TO
PREVENT DAMAGE TO CONVERTER
1.24" x 2.5" x 0.55"max(31.4 x 63.5 x 14.0)mm
SIZE
(10.2)
L
min
5
15
TEMPERATURE RANGE
Storage
,11.01
.....
' Y..
Vde
rnA
Vde
BOTTOM VIEW
WARMUP TIME
to60ppmSPAN
to 20ppm SPAN
POWER REQUIREMENTS
+Vsand -Vs
+Vn
Supply Current Drain
@±15V
@+5V
V
60
5.5
MAX
V
dB
dB
4.5
DIGITAL LEVELS
Inputs
Low
High
Outputs
Low(@4rnA)
High(@IOO.,A)
page of this
RECTANGULARlEADS-
-r-
D~R~ALNONL~EARnY
T(int) @
0.02010.025
{0.051O.0I1
MAX
SIGNAL
+5V
AO,A1
RD
WR
CS
BUSY
DESCRIPTION
Digital PowerSupply
Address Control Lines
Read Datil Strobe
Write Data Strobe
Chi Select
When Low. Indicates Device Busv
When High.lndicatesDevice ReadyforCommand
DTA ROY When High,lndicates ThatOata From Most Recent
Conversion Command Is Ready
INT
When HIgh. Indicates DeviceisCurrendylntegratlng
Input Signal. Goes Low to Indicate Integration Complete
ELS
External LineSampie Input. Used with ELS Command
to Sense an Externally Provided Sanlple of the Une Frequency
PWR UP
When High, Indicates Power Up Initialization
in Progress
-15V
NegativeAnalogPowerSupply
+15V
Positive Analog Power Supply
ANA COM Analog Common: the Reference Point for Analog
PowerSupplies
+IN
PositiveSignallnput
-IN
NegativaSignallnput
REF OUT
Internal +6VRefarance Output
REF IN
Reference Input; Normally Connected to Ref Out
DIG COM DigitaJCommon;theReferencePointforthe
Digital Power Supply
ExternalConvertCommandlnput
RESET
Resat Input; UsullllyConnectedto an RC Network
for AutomaticReset Upon PowerUp
XTAL OUT. Connectionsfor 12MHzCrystaiiSeries Resonant.
XTAL IN
300 ESRI. Alternatively. Xtelln MayBe Driven
From an External 12MHz LogicSignal
D7-DO
Bidirectional Data Bus
e;:;:cc
DO NOT CONNECT
ADl170
da~
FACTORY DEFAULT SETTINGS
The AD 1170's internal nonvolatile memory stores various AID
parameters as programmed by the user (such as the integration
period, output data format, calibration coefficient, etc.). The
AD 1170 is calibrated at the factory with the following default
settings:
FORMAT: 16-bit, offset binary
DEFAULT T(int): 16.667 milliseconds
(code 2)
DEFAULT T(cal): 100 milliseconds
(code 4)
AD1l70 ARCIDTECTURAL OVERVIEW
The ADl170 is a complete microcomputer-based measurement
subsystem, containing three major elements: a highly precise
charge balancing converter, a single cbip microcomputer, and a
custom CMOS controller chip.
The heart of the measurement technique is the charge bslancing
converter (essentially a voltage to frequency converter). This
converter measures the input signal by balancing a proportional
current against a train of precisely controlled reference current
pulses using an integrator. The microprocessor, together with
the counting and gating circuitry within the CMOS controller
chip, measures the period of the reference current pulses by
interpolating them using a 12MHz clock signal. The resulting
is converted to binary representation by the use of floating
pomt fumware routines within the microprocessor.
When the AD1170 is triggered to perform a conversion, two
separate phases are performed: fIrSt, an integration phase, where
the input signal is actually measured, and then a computation
pbase, where the data from the integration phase is processed,
along with both the volatile and nonvolatile calibration data, and
formatted for output as the user desires.
The duration of the integration phase can be programmed by
the user, and may be as short as one millisecond, or as long as
350 milliseconds. The computation phase always lasts approximately three milliseconds and commences immediately after the
integration phase is over. Therefore, the total conversion time
will equal the user programmed integrate time plus a fIXed 3
milliseconds. Status signals are provided to indicate when the
data is ready and when the converter may be retriggered for the
next conversion.
For maximum stability, the AD 1170 periodically calibrates itself
by performing measurements upon a zero input signal and a
full-scale signal provided by the internal reference. This technique
cancels any drift within the charge bslancing converter itself
resulting in negligible offset drift, and gain stability equal to'
that of the reference. Calibration cycles may be programmed to
take place wheuever the AD1170 is idle, or they may be invoked
under system control.
-------. r--'''''--I~---
1.,...----
_ _---,. \'--'''---.1
RD
~
_
1_,<",,--1
cs~
I
~ '.. I+AO.Al--X
I
'o.. ~ 1+
00-07
I-'CHS--j
r
t-'00
..,.j ". /';
I
~
cs)
)r---
AO.Al
"0
".,
'AS
tcSRL
',.
to..
to.
DESCRIPTION
RD Pulse Width
Chip Select to RD low
Chip Select Hold Time
Address Setup Time
Address Hold Time
Data Valid Time
Data Hold Time
MIN
150
0
TYP
-l ' ..
X
t;:'os j
00-07
r
t CHS --...,
r,::
~ _ __
'D.
------~(
READ CYCLE TIMING REQUIREMENTS
PARAMETER
-i "r-
_ _ ~ '" ~
1_
-------«
rtcswL
WR
1+
)r----
WRITE CYCLE TIMING REQUIREMENTS
MAX
UNITS
PARAMETER
S.6V FS.
A user accessible to-tum trim potentiometer is a1so provided for fane GAIN adjust (:!:O.OO6% range).
AU units arc factory calibrated for:!::S V Nominal FuU Scale to within :!::SO "V.
'Input Bandwidth. specifications arc for true integration without cLippins.
SpccifJCations subject to chmge without notice.
WARMUP TIME
Relative Accuracy (for Rated Performance)
15 Minutes
OUTLINE DIMENSIONS
Full Rated Performance
45 Minutes
Dimensions shown in inches and (mm).
REFERENCE
Exte~ Reference In
For Rated Performance
Maximnm Input (Operating Only)
Reference Output
Voltage
Output Resistance
Temperature Coefficient
User Reference Output
Gain (Referred to Reference In)
+6.95 ±2%
250n
±0.4 ppmI'C (±O.S ppml'C, max)
HALf-HARD
BRASS
O.02510_8)SO.PlN
GOlOPLATEDIMIL-G-452(4)
±2 rnA, max
±1 J.LVfC, max
-1.11
I'
5.201132.11""'.--..-
WARNING!
ADJUSTMENTS
Offset (Programmable)
Range
Resolution
Gain·Coarse (Programmable)'
Range
Resolution
Gain-Fine Ranges,s
Gain·Balance (±Full Scale) Range'
DIGITAL LEVELS
Inputs
Low
High
::tS V Bipolar
::tVs
_
0.112.541 GRID---t
AOJ AOJ
I--
1---1.60I38.tl
::t7S mV
I LSB Steps
<4.7V to >5.6 V
0.009% Steps
±0.006% FS
±0.005% FS
0.45 V max
2.4 V min
ASSEMBLY INSTRUCTIONS
PIN DESCRIPTIONS
5
SIGNAL
CONVCMD
RESET
7
6OHzl5OHz
DO NOT CONNECT
•
•
•
9.10
11-18
±15 V (±0.3 Veach)
+5 V (-0.2 V to +0.4 V)
+55mA,-70mA
150mA
175mA
1.
2.
21
1O'C to +5O'C, 70% RH
-25'C to +7O'C
MECHANICAL
Size
Shielding
3.7" x 5.2" x 0.53" max
Weight
170 grams
Electrostatic, 6 Sides
Ele<:trOl11agnetic, 5 Sides
3-160 ANALOG-TO-DIGITAL CONVERTERS
+5V
DIGGND
DBO-DB7
AO
A1
AD
DESCRIPTION
ExternalConYertCommand
Resetlntemal MicrocomputerFollowlng Power-Up
When Set Low,lntegration Time is 1125se.:
When Set High,lntegration Time is 1130 sec
Used Only for Factory Test
Digital Power Supply
Digital Ground (Both Pins are Tied Together Internally)
Bkllrectlonal Date aus(LSB-MSBI
Address. Bit Zero
Addre ••• ."itOne
READ
22
WR
WRtTE
2.
2'
2.
CS
CHIPSELECT
BUSY. Responding to. au.Command
DATAREADV
Anetog Power Ground and Case (Tied Togethel' Intemally)
.....
68
oto +7O'C
BOTTOM VIEW
j.--1.62SI41.31~
CAUTION: This module is not an embedded assembly and is not hermeti·
cally sealed. Do not subject to a solvent or water·wash process that would
allow direct contact with free liquids or vapors. Entrapment of contaminants
may occur, causing performance degradation and permanent damage. Install
after any clean/wash process and then only spot clean by hand.
PIN
O.S V max
2.0V min
j
NOTE: SEE PAGEl-161 FOR RECOMMENDEDSOCKET.
SEEPAGE3-168 FOR EVALUATION BOARD.
2.0 MHz
150kHz
80 dB, min
-----t I
194.0)
MAX
BAlGA'.
± 10 nA, typ, ::t4O nA max
ENVIRONMENTAL
Rated Perfonnance
Operating
Storage
_
±100 mV
1000 Mn
POWER REQUIREMENTS
Supply Voltages (for Rated Accuracy)
+VD
Supply Current Drain
@±15V
After Warm·Up
During Warm·Up
@+5V
49
±12 V
::t3V
Outputs
Low(@4mA)
High (@ 100 tLA)
0
~~DfV'Cf
20 conversions/sec
16 conversions/sec
ANALOG INPUT CHARACTERISTICS
Input Resistance (Input Hi, or Input La)
Input Bias Current, Input Hi or Input Lo
(+ IO'C to + 5O'C)
Input Bandwidth9
Small Signal
Large Signal
eMRR at dc to 60 Hz
T
:!:O.0210.S)
1.000 to 1.012'
Stability: Temperature Coefficient
Voltage Range7,8
Max V1NH (at Input Hi, Without Damage)
Max V1NL (at Input Lo, Without Damage)
Max V1NLR (Input La, for Rated Performance)
1--"";"'"
1
1--------4.801121.91-------1
±I ppm/Day
±25 ppm '-"1000 hrs., max
1 ppm p-p, max
Current
THROUGHPUT RATE"
@ Integrate Time of 1/30 sec (60 Hz)
@ Integrate Time of 1125 sec (50 Hz)
ACCESS IfAR SIDE)
r=====~~======~~
Time4
Drift with
1st IS Days Operating
After IS Days Operation
Noise, 0.01 Hz to 10 Hz (95% Confidence)
TRIM-POTENTIOMETEII
NONCONDUcnVE LABEL
+6.95 V ±2%'
+9.6 V
.,••
...
62
..
iiiiSv
DATARDY
:t1SVRTN.GND
ANAINlO
ANAINHI
-16V
SIGNALRTN
+tSV
USER REF OUT
REFIN
REF OUT
~
An
N
rSupply
Sig
Current Carrying Ground)
PositiveAnalogPow.rSupply
Buffered Output of Reference ., REF IN
Referenc:.lnput., NormallyConnectedto REFOUT
Internal +6.95V ReferenceOutput. Unbuffered
AD1175K
SAMTEC Part Number SSQ-122-03-G-S (2 Each Required
Per ADll7S)
Available direct from the manufacturer or through distributors.
2.22 (56.41
- - - - - ; 1 ~2~~
----I !-.L
2.10 (53.31
auaaaaaaBDeuaaaDuuaa
T
rrn
0
18~~~H~H~H~HH~H t~~
0.100 (2.54)
.J; [
0.025 10.64'
SQ.-II--
NOTE
O.025u (0.84) SQUARE SOCKET STRIP, 22·PlN POSITIONS
GOLD PLATED CONTACTS AND PINS. BODV IS MOLDED
DUPONT RYNITE PET POL VESTER.
ARCHITECTURAL OVERVIEW
The AD1l75 is a complete, precision analog-to-digital converter.
It consists of three major elements: a linearized, auto-zeroed
integrator, a single-chip microcomputer, and a custom CMOS
controllerlbus interface chip. (See Figure I AD 1175 Functional
Block Diagram.)
Therefore, the ratio of the signal measured (its average value) to
the reference voltage, is equal to the ratio of the measured time
(to force the integrator back to zero charge) to the signal integration time (which is held constant).
The AD1l75 repeats the above sequence ten times during the
first 33-1/3 milliseconds of each conversion for a 60 Hz integrate
selection (40 milliseconds for a 50 Hz integrate selection). The
10 individual readings together with the result of a final, slow
(about 6 ms) vernier reference integration are summed. The
numeric result is then placed in the addressable output latches
and DATA is indicated as AVAILABLE. During the next ten
milliseconds, the integrator is reset and AUTO-ZERO nulls out
offset errors in preparation for the next conversion.
The device status is indicated by the addressable STATUS byte
(busy, converting, data available, etc.). DATA READY and
BUSY are also indicated by logic levels at Pins 25 and 24,
respectively.
SIGNAL INPUT CONNECTIONS
The ANA IN HI and ANA IN LO pins comprise a true, highimpedance, high CMRR, differential input pair. ANA IN LO
must be within ± 100 mV of SIGNAL RTN (Pin 62). The ANA
IN LO pin is used to remote sense the source low (ground) to
minimize system ground current related errors. Both HI AND
LO SIGNALS MUST HAVE A BIAS CURRENT PATH BACK
TO SIGNAL RTN. Figure 2 details the proper connections.
A01,75K
REf'OUT
r---'
+15V
I
I
SIGNALRTN
I
DBO
1
0.
I
D,
/
'----~
Figure 1. AD1175 Functional Block Diagram
The conversion process is similar to the classic dual-slope technique, where the input signal is integrated during a whole number of line cycles (for line noise rejection) and then a digital
measurement is made of the time required for a known reference voltage to drive the integrator output back to zero (i.e., to
zero charge). Since the process begins with zero charge in the
integrator, and also ends there, we can express this function as
follows:
CHARGE IN = CHARGE OUT
WHERE CHARGE =
fT
OR ...
OR ...
Ltl dt = ~ Ltv dt
SIG
R~T Jo VSIG dt
fT...
J. v
O. .
dt =
v.., •
To" (SINCE vo.. = CONSTANT)
TOIG
OR...
HENCE
~
v... dt
fTo"
= R: T Jo VREF dt
•TSIQ
...
= AVG. [V...) = vo"lSIG• To..
AVG·IVolO) _ To" {WHERE TREF IS MEASURED AND
vo"
- T... Vo.. " T... ARE CONSTANT
;;m;
: /SEENDTE21
L..,t-"""]!o""" ANA IN HI
"---''''If'....
,
iiiiii'iTE
I
BU.
~~~~J
'0
:t:15VRTNlcOND
DECODE
..
NOT£S
1. BOTH HIGH AND LOWSIGNALS MUST HAVEABIASCURREP/fPATH BACKTO GROUND
ATTHEAD1175. "ANA IN LO" SHOULD REFERENCETOGROUND (SIGNALRTN) ATTHE
SfGNALSOURCE. VIA A MlNIMUMOFRESISTANCE.
Z. "DIG GND" AND" ± 1SV RTN .. GND" ARE STAR CONNECTED WITHIN THE CONVERTER.
AND INTENDED TOBESEPARATE OUTSIDE Of THE CONVERTER. HOWEVER,IF :!: 1SV
AND +5VPOWER SHARE A SINGLE COMMON RETURN. THEN THAT COMMON MUSTSE
CONNECTED TOTHE":t 15V RTN a GND" PIN WHICH MUST BE CONNECTED VIA
HEAVVCOPPER TOTHE "DIGGNO" PIN. "SlGNALRTN"jpfN 6ZJ ISTHE "NON-CURRENT
CARRYING" GROUND. ONLVTO BE USEDAS SHOWN ANDAS GROUND REFERENCE FORAN
EXTERNALLVSUPPUED REFERENCE SOURCE.
Figure 2. AD 1175 Bus Driven Interface
Printed circuit board layout should insure that both analog
inputs (Pins 58 and 59) are guarded by copper which is tied to
SIGNAL RTN (Pin 62) on the front and back of the board.
Note that an offset error of up to one LSB per 120 (} of source
impedance can occur, due to input bias current, which may
approach 20 nA at elevated temperatures.
Principle of Dual-Slope Conversion
ANALOG-TO-DIGITAL CONVERTERS 3-161
I
REFERENCE CONNECTIONS
A very stable 6.95 V ±2% internal reference is filtered and
brought out to REF OUT (Pin 66) of the converter. This output
should be tied to REF IN (Pin 65) to accomplish the specifications for initial absolute accuracy. REF OUT is a high impedance output and should not. be loaded in any way other than by
REF IN (Pin 65). A buffered version of the reference applied to
REF IN, and that which is used by the converter, is available at
USER REF OUT (Pin 64).
When making ratiometric measurements, where the source excitation is derived from the converter reference, use the reference
signal present at USER REF OUT (Pin 64). The load applied to
Pin 64 should not exceed two milliamps. If an external reference
source is to be used, it should be applied to REF IN (Pin 65).
POWER SUPPLIES AND GROUNDS
The power supply pins are all well bypassed internally to their
respective conunon or ground pins. The converter is very tolerant of dc and low frequency noise (:5100 S of Hz) on any of the
supplies, as evidenced in the power supply rejection specifications. High frequency noise (;;,:1 MHz) in excess of 10 mV on
the ± IS V supplies could, however, degrade the converter's
performance.
DATA RDY (Pin 25; Output)
This signal will go to logic "1" when any conversion's new data
has become stable in the output latches. It will remain high for
the duration of the auto-zero phase (about 10 milliseconds) and
go low at the end of that phase (at the end of BUSY).
BUSY (Pin 24; Output)
When a COMMAND byte is written to the microprocessor compatible port, this line is set low and remains low for the duration
of the converter's response to that command. It is the opposite
state of the BUSY bit within the STATUS byte.
THE BUS INTERFACE
The AD117S's 8-bit microprocessor-compatible interface consists
of an 8-bit, latched ,tri-stated, bidirectional port and its associated control lines: Chip Select (CS), READ (RD), WRITE
(WR) and two address bits (AI and AO). Timing requirements
for the bus interface are shown in Figure 3, and the operation of
the interface is shown in Figure 4.
To avoid large, digital-rate, circulating ground currents, the system's analog supply conunon and that of the digital supply
should be kept separate and then tied together at the converter
by a heavy track (to supplement that which is internal to the
converter) from ± IS V RTN & GND (Pins 48 and 49) to DIG
GND (Pins 9 & 10).
PARAMETER
.........,
tao,
If the logic supply and analog supply share a single conunon,
then that conunon should be brought to ± IS V RTN & GND
(Pins 48 and 49) and then from these pins a heavy track should
be run to DIG GND (Pins 9 & 10).
RESET (Pin 5; Input)
After power-up and before access may be made to the converter,
a reset of the internal microcomputer must be accomplished.
The RESET (Pin 5) may be driven from an external source,
such as may exist in most computer-based systems, or it may be
connected to a simple RC circuit which will automatically generate a reset sequence upon power-up. See Figure 2 for the recommended circuit.
When driven from an external source, RESET must be held
high for a minimum of 3 microseconds, but must not terminate
before the +5 V logic supply and the ±IS V analog supply have
been stable (> +4.7 V, and > ± 11 V) for 300 microseconds.
60 Hz! 50 Hz (Pin 6; Input)
Pin 6 of the module selects either 33-1/3 milliseconds or 40 milliseconds for the signal integration time. This input is internally
pulled up to 5 V via 10 kG and may be left open for 60 Hz normal mode rejection. The pin should be connected to Digital
Ground for operation in a 50 Hz line frequency environment.
CONY CMD (Pin 4; Input)
A negative logic transition on this input causes a MODCON
conversion to occur (see CALIBRATION section). A minimum
hold time of 1.5 ~s is required at both the High and the Low
states, to operate properly. The BUSY output (Pin 24) will not
respond, and BUSY (Bit 0) of the STATUS word will not be
indicated, but all other bits of the STATUS word will be active.
DATA RDY (pin 25) will occur per Figure 8.
This input is provided to allow externally triggered conversions
which will use the temporari1y progranuned gain and offset values (or the start-up defaults if no changes have been made).
t..,
to.
Data Setup Time
to.
DIIta Hold TIme
...
.
MAX UNITS
MIN
0.1
0
DESCRIPTION
WRPulsewtdth
Chip Sel.etto WRLow
Chip Select Hold Time
AddressSetuptime
~.
10
.
AddressHoldTime
5
-~
~.
Write Cycle Timing Requirements
iffi
----.1- too --1,---
L---l
cs-r~~'l
:j 'AS
I
AO.A1---X
'DAV
-.f
DO-D7
...
...
.......,
PARAMETER
tcSIlL
tao,
t ..
r'c~1-
j..
.,.j
'AH
-.f
'DH
I
1+
r,:
X
r
()~--
DESCRIPTION
MIN
RD Pulse Width
Chip Select to RDLow
ChipSelectHoldnme
Address Setup Time
Address Hold nrne
DataVaHdnme
150
MAX
UNitS
,.
•
100
eo
Data Holdnme
Read Cycle Timing Requirements
Figure 3. Interface Timing Requirements
cs
READ
WRITE
L
L
L
L
L
L
L
L
X
H
iffi
iiiiii
A1
AO
L
L
L
L
H
H
H
H
H
H
H
H
H
X
H
H
H
L
L
L
L
H
X
L
L
H
H
L
L
X
X
L
H
L
H
L
H
L
X
X
FUNCTION
High CONY D... Byte READ
Mid CQNV Data Byte READ
Low CONY Data Byte READ
STATUS READ
Unused
Unused
PARAMETER WRITE
COMMAND WRITE
DEVICE NOT SELECTED
NOTE THAT X = DON'T CARE
Figure 4. Bus Control Functions
3-162 ANALOG-TO-DIGITAL CONVERTERS
ADl175K
BIT #
MSB
23
POS. OVERLOAD
1
+ 1.25 x FULL SCALE 0
+ FULL SCALE
0
+ 1/2 SCALE
0
ZERO
0
-1/2SCALE
0
-FULL SCALE
0
-1.25 x FULL SCALE 0
NEG. OVERLOAD
1
22
1
1
1
1
1
0
0
0
1
21
1
1
1
0
0
1
1
0
1
20
1
0
0
1
0
1
0
1
1
19
1
1
0
0
0
0
0
1
1
18
1
0
0
0
0
0
0
0
1
17
1
0
0
0
0
0
0
0
1
16
1
0
0
0
0
0
0
0
1
15
1
0
0
0
0
0
0
0
1
14
1
0
0
0
0
0
0
0
1
13
1
0
0
0
0
0
0
0
1
~
J
Jf,
'.f.
~'.
J
5
1
0
0
0
0
0
0
0
1
4
1
0
0
0
0
0
0
0
1
3
1
0
0
0
0
0
0
0
1
2
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
LSB
0
1
0
0
0
0
0
0
0
1
HEX
FF,FF,FF
68,00,00
60,00,00
50,00,00
40,00,00
30,00,00
20,00,00
18,00,00
FF,FF,FF
Figure 5. Data Format
OUTPUT DATA FORMAT
The result of a conversion is made available in three 8-bit bytes
(addressed as shown in Figure 4). The numeric result is presented as an offset binary number, where the offset value is
equal to 2e22 (40,00,00 Hex), i.e., zero volts input yields this
numerical output. Therefore, the nominal plus and minus full
scale are 2e22 ±2e2l, or 60,00,00 Hex and 20,00,00 Hex,
respectively. For inputs greater than approximately 1.3x nominal full scale, the converter will indicate an overload error (Bit 5
of the STATUS byte) and will also flag the occurrence by forcing all "Is" in the conversion result, i.e., FF,FF,FF Hex. Bit
23 (MSB) cannot be a "1" for any legitimate conversion result,
so that bit is used to flag an overload. The data fonnat is
depicted in Figure 5.
COMMAND BYTE
The COMMAND BYTE allows eight different instructions to
be given. Five of these will require that a parameter be loaded
into the PARAMETER* register prior to writing the command
register. The commands are written at address 00 (ADDRESS
lines Al and AO, Pins 20 and 19, respectively) while a parameter
is written to address 01. See Figure 4 for Bus Control Functions. Figure 8 details command timing requirements.
The commands are described below, preceded by an opcode
name and the digital code (in hex). Figure 6 summarizes each
command and its execution time.
DEFCON [OOJ
DEFault CONversion initiates a conversion, using the gain and
offset values which are stored in the nonvolatile memory (powerup defaults).
MODCON [OIJ
MODified CONversion initiates a conversion using the gain and
offset values which have been modified (since power-up) as in
commands 02 through 07 below.
NEWOS [02J
NEW OffSet subtracts the result of the last conversion from all
subsequent MODCON conversions, i.e., acquire a new system
offset. The maximum range of this offset is 65,536 codes
(= ±75 mY). Attempts to acquire an offset outside of this range
will be ignored and BIT 5 and BIT 6 (Overload and command
byte ERRor) will be set in the STATUS byte.
INCROS [03J
INCRease OffSet alters the offset (in LSBs) used by MODCON
in the positive direction by a number between zero and 255 (decimal), which has already been written to PARAMETER*.
*The PARAMETER register retain. the last word written to it. Any subsequent commands will repeatedly use that PARAMETER until it i. updated.
This may be perfonned repeatedly until a maximum offset of
+75 mV has been reached, as indicated by an OverioadIBIT 5
response in the STATUS byte.
DECROS[04J
DECRease OffSet alters the offset (in LSBs) used by MODCON
in the negative direction by a number between zero and 255
(decimal), which has already been written to PARAMETER*.
This may be perfonned repeatedly until a maximum offset of
-75 mV has been reached, as indicated by an OverioadIBIT S
response in the STATUS byte.
INCGAN [05J
INCrease GAiN by NxO.Ol%, where N (a decimal number
between 0 and 255) has already been written to PARAMETER*.
This may be performed repeatedly until a maximum gain
«4.7 V full scale) has been reached, as indicated by an Over10adlBIT 5 response in the STATUS byte. Further INCGAN
commands will have no other effect.
DECGAN [06J
DECrease GAiN by NXO.Ol, where N (a decimal number
between 0 and 255) has already been written to PARAMETER*.
This may be perfonned repeatedly until a minimum gain (>5.6 V
full scale) has been reached, as indicated by an OverioadIBIT 5
response in the STATUS byte. Further DECGAN commands
will have no other effect.
UPDATE [07J
Takes the current modified gain and offset values and writes
them to nonvolatile memory as the new start-up defaults. To
enable this function, decimal 165 (AS in hex) must first be
loaded into PARAMETER* - failure to do so will result in an
ERRor (BIT 6) response in the STATUS byte.
Note: Codes other than 00 through 07 will do nothiog, except cause an
ERRor (BIT 6) response in the STATUS byte.
MNEMONIC
DEFCON
FUNCTIONAL DESCRIPTION
EXECUTION TIME
(APPROXIMATE)
Initiate a Conversion Using the Power-Up
Default Offset and Gain
Initiate a Conversion Using the Modified Offset
and Gain Values
Subtract System Offset,(Last Conv. Result) from
All MODCON Conversions
Increase the Offset Used by MODCON
Conversions
Decrease the Offset Used by MODCON
Conversions
50ms
INCGAN
Increase the Gain Used by MODCON
Conversions
13S"s
DECGAN
Decrease the Gain Used by MODCON
CI"nversions
135....
UPDATE
Write Most Recent Modified Offset It Gain
Values to Nonvolatile Memory
48ms
MODCON
NEWOS
INCROS
DECROS
50ms
120"s
110".
110fLS
Figure 6. Synopsis of Commands
ANALOG-TO-OIGITAL CONVERTERS 3-163
I
THE STATUS BYTE
The STATUS byte contains eight bits of information about the
current status of the AD1l75. This byte may be examined by
the host processor at any time. The individual bits in the status
byte are assigned the following functions:
BIT 0 The BUSY bit is always set when the COMMAND
BYTE is written, and cleared when the initiated routine
has terminated. BUSY is also indicated at BUSY (Pin 24)
of the module.
BIT I The CONVerting bit is set when the converter is in the
active process of converting and computation. It is initiated by writing DEFCON or MODCON to the
COMMAND-BYTE, or by a negative transition at
CONV CMD (pin 4).
BIT 2 The Data AVailable bit indicates that a new conversion is
complete and the result is in the output latches. This bit
• sets to "I" at the conclusion of the converting process
and remains "I" for the remainder of the minimum
AUTO-ZERO time (about 10 milliseconds). It is reset to
"0" at the end of BUSY.
BIT 3 The MODified bit, when set to "I," means that modified gain and offset values are being used for the current
conversion; i.e., a conversion initiated by MODCON or
an external signal at CONY CMD (Pin 4).
BIT 4 The VALue bit responds to COMMANDS 02 through
07 by setting to "I" at the end of BUSY, and remains
until the next write to the COMMAND byte. This bit
signals that a gain or offset value used by MODCON has
been altered, or that the current MODCON gain and
offset values have been loaded to nonvolatile memory as
the new power-up defaults.
BIT 5 The Overload bit will be set following any conversion
where the integrator has been exposed to an overload
voltage. Following commands 03 through 06, it indicates
that a parameter (gain or offset) has been incremented to
its maximum or minimum possible value (note that further attempts to increment that parameter will not cause
an overflow or underflow). Also, following NEWOS (02)
command, this bit implies that an attempt was made,
and ignored, to acquire an offset outside of the allowable
range of ±75 mY.
BIT 6 The ERRor bit indicates one of the following: 1. A
COMMAND-BYTE was written which was not within
the allowable range of 00 to 07. 2. An update (07) command was attempted without the KEY number (165 decimal) having first been written to PARAMETER at
ADDRESS 01. 3. A NEWOS (02) command was
attempted for a value outside the permissible range of
±32,768 codes (>75 mY) from zero.
BIT 7 The WaRMUP bit flags the three second time-out taken
by the converter following RESET, to allow the refer~
ence and auto-zero circuits to settle. The converter will
not convert during this time.
CALmRATION
The AD1l75 is factory calibrated for plus and minus full scale
(2e21) to be within ±50 fJ. V of five volts, absolute. Since the
converter will operate within specifications for inputs up to ten
percent over nominal full scale, those inputs between ± 5.5 V
will be converted accurately. (See Figure 9 for typical linearity
vs. input voltage.)
To correct for system offset voltage (particularly larger offset
voltages - up to ±75 mY) the NEWOS (03) command subtracts
the result of the last conversion from all subsequent MODCON
conversions. If source noise is a concern when making the offset
adjustment, follow a single NEWOS command with multiple
MODCON conversions, average the results and adjust offset
incrementally using the INCROS (03) or DECROS (04)
commands.
The INCGAN 05 and DECGAN 06 commands are the coarse
gain increment and decrement controls, respectively. The minimum gain attainable will require greater than 5.6 V to achieve a
full-scale output. At maximum gain, less than 4.7 V will be
required to yield a full-scale indication. The user accessible
GAIN ADJ potentiometer is the vernier, or fine gain trim (10
turns, with a total adjustment range of about ±0.006 FS).
The modified offset and gain resulting from commands 02, 03,
04, 05 and 06 are used only when conversions are initiated by
MODCON (command 01), or conversions triggered by a negative logic transition at the CONY CMD (Pin 4 of the converter).
This pin requires a minimum hold time of 1.5 fJ.S at both the
High and the Low states in order to operate properly.
The GAIN ADJ potentiometer changes the overall gain for both
positive and negative inputs. The BAL ADJ potentiometer
changes the gain for positive inputs only and allows setting of
plus and minus full-scale tracking to within ± I ppm.
To Calibrate the AD1l7S:
1. Attach a calibration source and set its output to zero volts.
2. Perform MODCON conversions and null out any observed
offset (via external computation, or by executing one or more
of the AD1l75's offset controlling commands: INCROS,
DECROS and NEWOS).
3. Set the GAIN ADJ potentiometer fully clockwise (10 turns,
i.e., maximum gain).
4. Apply a negative full-scale calibration voltage (-4.7 V to
-5.6V).
5. Using the INCGAN or DECGAN command, coarse adjust
the gain such that a subsequent MODCON conversion yields
a result just larger than minus full scale. In other words, a
subsequent DECGAN by 01 would just yield a result that is
less than or equal to minus full scale.
6. Adjust the GAIN ADJ potentiometer to yield the precise
value desired by turning counterclockwise and observing conversion results. When the correct gain is reached, rotate the
potentiometer about 3 degrees in the opposite direction to
remove the tension from its wiper.
7. Switch the polarity of the calibration source to positive.
B5
B4
B3
B2
OL
VAL
MOD
DAV
Bl
BO
CONV
BUSY
I I
Figure 7. The Status Byte
3-164 ANALOG-TO-DIGITAL CONVERTERS
8. Adjust the BAL ADJ potentiometer to yield the same gain as
that achieved in Step 6 above.
9. Save the new offset value and coarse gain value, if you want
them to become the power-up defaults, by performing
UPDATE (Command 07).
Note: See the COMMAND BYTE section for details of command operation.
ADl175K
,"'"
SIGNAL INTEGRATION
OVER·
RANGE
LlNEARJTY ERROR
lppmFSI
.,
COMMAND WiiiTE'
·OVER·
LOAD
-, ~-----------+------------~~~--~~~
-, ov
,I2FS
BUSV
CONII
~FS
1.1 FS
.." 1.3FS
+---INPUTVOLTAGE _____
--+------! _____ {If
MOD --+1----1-+--_____ {If the Analog Input
·OVERLOAD CONDlTWN IS INDICATED BY BIT 5 OF THE STATUS BYTE
AND A "1" IN BIT 23 OF THE OUTPUT DATA BYTE.
DAII
Conversion Uses
MODified Parameters
STATUS
BITS
Is Too Large
OL--t-----+-+---
tfThereiS.
- - - - - { Command Error
ERR - - + ' ' - - - - r - t - - -
I r--n
__
0
10 20 30 40 SUms
BUSV - - ,
IPlN201
n
DATARDV
IPIN251
-
_ _ _ _ _ _ _,
L--
a. COMMAND BYTE Initiated Conversion
COMMANDWiiiTE.~j
I
BUSV~
VAL
--------~I
OL
Value Is Changed
toth_MAXIMIN
I
r---------
FACTORY TESTING
Each AD 1175 converter is factory calibrated via test apparatus
designed and constructed by Analog Devices. The heart of the
test system is a digitally programmable voltage reference capable
of sub-ppm accuracy and stability. Calibration of the test system
is verified daily using the highest precision instruments commercially available, e.g., FLUKE* model 720A Kelvin Varley voltage divider (accurate to within ±O.I ppm') and model 732A dc
secondary voltage standard (accurate to within ± 1.5 ppm of the
international volt').
IBM PC INTERFACE
Figure 10 is an example of an AD1175IIBM interface suitable
for the IBM PC, XT or AT** personal computers. In this case,
the AD 1175 is interfaced in the I/O space; a DIP switch controls the specific location of the AD 1175 within the available
address space.
D7/A21
r--"':'------ {If
I
Figure 9. Typical Linearity Transfer Function
DSIA3)
D5(A41
D4IA51
{HNEWOffsot
Is>:t:75rnV
ERR
D31ASI
D21A71
D11A81
-NOTE: COMMAND WRITE Always Causes Rewrite of the Entire STATUS Byte.
For Example: If the Overload Bit (OL) is Set as the Result of 8 Conversion.
It Will Remain Set in the STATUS Byte Until the Next COMMAND WRITE.
DOIA91
.5V
b. COMMAND BYTE Initiated Change to Gain andlor
Offset
A9IA22)
A81A231
CONVERT~
COMMAND
A71A241
A6(A261
--+--------
BUSV
{INACTIVE
A6fA261
MeA27)
AEN!All'
CONV
STATUS
BITS
DAV--r-----!
MOD
_______ {HAnalog Input
Is Too Large
OL--!----~_+--
IPIN241
~~~DV
_______
I
IrL-
iORIB141
A31A28)
I I I I
A2(A291
10 20 30 40 SOms
ii:iSV
toWIB131
A1(A301
INACTIIIE
M(Al1l
~
c. CONVERT COMMAND (Pin 4) Initiated Conversion
Figure 8. Command Timing Requirements
Figure 10. AD1175 to IBM PCIXTIAT Interface
*FLUKE is a registered trademark of John Fluke Manufacturing
Company, Inc.
**IBM PClXT/AT is a trademark of International Busin..s Machin.. Corp.
'Traceable to the NATIONAL BUREAU OF STANDARDS.
ANALOG-TO-DIGITAL CONVERTERS 3-165
I
INTERFACING TO AN 8051 MICROCONTROLLER
Figure 11 shows how the AD1l75 may be interfaced to an 8051
microcontroller using a technique commonly called "byte
banging," where the control lines and data bus of a device are
manipulated under firmware control. This "byte banging" technique can be adapted to most microprocessors and is useful in
situations where a conventional bus structure is either nonexistent or unavailable for use. 1
The AD 1175's data bus is connected to the 8051 using I/O lines
P2.0 through P2.7. The address lines AO and Al are connected
to I/O lines P1.0 and P1.1 respectively. The RDI and WRllines
are connected to P1.2 and P1.3. The CS/line of the AD1175 is
grounded when it is the only device connected to the 8051, but
multiple AD1175s could easily be connected in the same way if
each CS/line were separately controlled.
Pt.1
PU
8051
P1.l
G~)----~®20
At
«r-----<'"
~
~~
AO
4
2:l WR
PU(3
21 RO
{2B}-----{>~ DB7~~!!75
P2.5
26}.- - - - - { i
AC5005
an IBM PCIXT/AT Compatible
Evaluation Board for the ADl175K
FEATURES
Compatible to IBM PC/XT/AT* or Equivalent
Menu-Driven Demonstration Software
Full Documentation
Example Listings of BASIC Programs
Schematic
Assembly Drawing
Complete Set of Tools to Evaluate the AD1175K 22-Bit
Resolution Integrating AID Converter
APPLICATIONS
Laboratory DVM
Product Test and Measurement
Analytical Instrumentation
Material Analysis
Seismic Analysis
P2.4@25S)------(i'5)5 084
Figure ". Simple AD1175 to 8051 Interface
To initialize the interface, first write "I"s to the port pins connected to the data bus and the RDI and WRI control lines. This
puts the 8051 1/0 lines into a lightly "pulled up" state, simulating a tri-stated condition on the bus to insure that neither RDI
nor WRI are selected:
INIT:
SETB PI.2
SETB P1.3
;DISABLE RDI
;ANDWRI
MOV P2, #OFFH
;SET P2 TO ALL ONES
To write a command to the AD 1175, first set the state of the
P1.1 and Pl:O lines for the address corresponding to the byte to
be written to (OO=COMMAND BYTE, OI=PARAMETER).
Set the P2 port to the command data, then strobe the WRlline
by first clearing the P1.3 line and then setting it:
WRCMD: CLR
CLR
Pl.O
Pl.l
;FIRST CLEAR AO AND Al
;TO POINT TO CMD BYTE
MOV P2, #00
;00 IS THE OPCODE FOR
;A DEFAULT MODE
CONVERSION
CLR P1.3
SETB Pl.3
;STROBE THE WRI LINE
;ONE TIME
MOV P2, #OFFH
;SET DATA BUS TO
;ALL ONES
To read a byte from the AD1175, first set the P1.0 and P1.1lines to
point to the address of the byte desired. Bring the RD/iine low,
reading the contents of P2. Return the RD/iine high:
RDSTAT: CLR
CLR
Pl.O
Pl.l
CLR Pl.2
MOV A,P2
SETB Pl.2
;POINT TO STATUS BYTE
;BRING RDI LINE LOW
;READ CONTENTS OF BUS
;RESTORE RDI LINE HIGH
'Note that the 8051 microcontroller does contain a conventional bus structure; the "byte banging" interface shown here is presented as an example of
an alternative technique.
3-166 ANALOG-TO-DIGITAL CONVERTERS
GENERAL DESCRIPTION
The AC5005 is an evaluation board for Analog Devices'
AD1175K and is designed to plug directly into the backplane of
an IBM PC/XT/AT and compatibles. The AC5005 is offered as
a support tool to enable users to easily and quickly evaluate
Analog Devices' AD1175K 22-bit multi-slope integrating ND
converter. The AC5005 comes with a demonstration program
written in BASICA that completely exercises the functions of
the AD1175K and emulates a 6112 digit DVM. The onboard
multiplexer allows selection via software from four differential
analog input channels. A set of ten digital I/O lines are available
to the user for control of lamps and actuators as well as to test
switch positions. The AC5005 plugs directly into an IBM PC or
compatible. Armed with an IBM PC and an AC5005 evaluation
board, the user is ready to execute the demonstration program
and evaluate the operation of the AD1175K.
A user's guide provides the user with all the information
required to put the AC5005/AD1175K pair into operation. The
schematic of the AC5005 is provided as an example of how to
interface the AD1175K to a computer bus. The AC5005 is very
easy to configure. It has one set of DIP switches to select the
board's base address and one set of jumpers to select either
50 Hz or 60 Hz line cycle. All the tools needed to evaluate the
AD1175K come with the AC5005. There is even a short example program listing written in BASIC to demonstrate the ease of
programming the AD1175K.
PRODUCT HIGHLIGHTS
1. Plugs directly into IBM PC/XT/AT or compatibles.
2. Evaluates the AD1175K 22-bit multi-slope integrating AID
converter without having to build a breadboard or prototype.
3. Comes complete with software and programming examples to
exercise all of the AD1175K's functions and emulate a 6 112
digit DVM.
4. AC5005 schematic and assembly drawing are provided to be
used as examples of how to interface theAD1175K to a
microprocessor bus.
5. Turnkey solution for laboratory measurement and analytical
instrumentation.
'IBM PCIXT/AT is a trademark of International Business Machines Corp.
Complete, High Speed
16-Bit AID Converter
AD1376 I
r'IIII ANALOG
WDEVICES
FEATURES
Complete 16-Bit Converter with Reference
and Clock
±O.003% Maximum Nonlinearity
No Missing Codes to 14 Bits Over Temperature
Fast Conversion - 14",s (14 Bit)
Short Cycle Capability
Parallel and Serial Outputs
Low Power: 645mW Typical
Industry Standard Pin Out
AD1376 FUNCTIONAL BLOCK DIAGRAM
IMSBIBfTS1
1
AD1376
I-;:=:::::::::::::;-I~"~CONVERT COMMAND
,""FERENCE
r+-::-::c--l"~COMPARATOA IN
22 ANALOG COMMON
21
-15V de SUPPLY Ve
ILSB FOR 13 BITS) BIT 13 13
ILS8 FOR 14 BITS) BIT 14 14
PRODUCT DESCRIPTION
The AD 1376 is a high resolution 16-bit hybrid IC analog-to-digital
converter including reference, clock and laser-trimmed thin-film
components. The package is a compact 32-pin, ceramic DIP.
The thin-film scaling resistors allow analog input ranges of
±2.5V, ±5V, ± 10V, 0 to +5V, 0 to + 10V, and 0 to +20V.
Important performance characteristics of the devices are maximum
linearity error of ± 0.003% of FSR, and maximum 14-bit conversion time of 15""s. This performance is due to innovative
design and the use of proprietary monolithic DIA converter
chips. Laser-trimmed thin-film resistors provide the linearity
and wide temperature range for no missing codes.
The AD1376 provides data in parallel and serial form with
corresponding clock and status outputs. All digital inputs and
outputs are TTL compatible.
19 DIGITAL COMMON
PRODUCT HIGHLIGHTS
I. The AD1376 provides 16-bit resolution with maximum linearity
error less than ± 0.003% (± 0.006% for J grade) at 25·C.
2. Conversion time is 14""s typical to 14 bits with short cycle
capability, and 16""s to 16 bits.
3. Two binary codes are available on the AD1376 output. They
are complementary straight binary (CSB) for unipolar input
voltage ranges and complementary offset binary (COB) for
bipolar input ranges. Complementary twos complement (CTC)
coding may be obtained by inverting Pin 1 (MSB).
4. The proprietary chips used in this hybrid design provide
excellent stability over temperature and lower chip count for
improved reliability.
5. The AD1376 includes an internal reference and clock, with
external clock adjust pin, and a serial output.
APPLICATIONS
The AD1376 is excellent for use in applications requiring 14-bit
accuracy over extended temperature ranges. Typical applications
include medical and analytic instrumentation, precision measurement for industrial robots, automatic test equipment (ATE),
multichannel data acquisition systems, servo control systems
and anywhere that excellent stability and wide dynamic range in
the smallest space is required.
ANALOG-TO-DIGITAL CONVERTERS 3-167
SPECIFICATIONS
(typical atTA
= +25"&, Vs = ::t 15, + 5 volts unless otherwise noled)
Model
ADI376JD
AD1376KD
UDits
RESOLUTION
16 (max)
*
Bits
±2.5, :!:S,:1O
Oto +5,Oto +10,010 +20
*
*
Volts
Volts
1.88
3.75
7.50
*
*
*
k!l
kG
k!l
ANALOG INPUTS
Volrage Ranges
Bipolar
Unipolar
Impedance (Direct Input)
Oto +5V, ±2.5V
Oto + IOV, ±5.0V
Oto +20V, ± lOY
DIGITAL INPUTS'
ConvenCommand
Logic Loading
Positive Pulse 50ns Wide (min) Trailing Edge Initiates Conversion
LSTTLLoad
I
*
TRANSFERCHARACTERlSTlCS2
ACCURACY
Gain Error
Offset Error
U"ipolar
Bipolar
Linearity Error (max)
Inherent Quantization Error
Differential Linearity Error
± 0.05' (± 0.1 max)
± 0.05' (± 0.2 max)
±0.006
±112
+0.003
POWER SUPPLY SENSITIVITY
±15Vde(±0.75V)
+5Vde(±0.25V)
0.0015
0.001
CONVERSION TIME"
12 Bits
14 Bits
16Bit.
11.5(13max)
13.5(15max)
15.5 (17 max)
WARM-UPTIME
1 minute
DRIFT'
Gain
Offset
Unipolar
Bipolar
Linearity
Guaranteed No Missing Code
Temperature Range
DIGITAL OUTPlTf.'
(All Codes Complemenrary)
I'arallel & Seriali
Output Codes7
Unipolar
Bipolar
Output Drive
Status
Slams Output Drive
Internal Clock9
Clock Output Drive
Frequency
± 0.05' (± 0.2 max)
Power Consumption
TEMPERATURE RANGE
Specification
Operating
Storage
%
±0.003
%ofFSR4
%ofFSR
%ofFSR
LSB
%ofFSR
··
··
··
··
··
% ofFSRI"A.t.v s
%ofFSRJOA.AVs
,",s
,",s
,",S
Minutes
± 15 (max)
±5(±15max)
ppmfC
±2(±4max)
± 10(max)
±2(3max)
±2(±4max)
±3(± lOmax)
±0.3 (2 max)
ppm ofFSRI"C
ppmofFSRI"C
ppmofFSRI'C
oto 70 (13 Bits)
Ot070(14Bit.)
'C
CSB
COB,CTC'
5
··
·
··
··
·
··
··
LSTTLLoads
Logic "1" During Conversion
5 (max)
5 (max)
1040
POWER SUPPLY REQUIREMENTS
Rated Voltage, Analog
Rated Voltage, Digital
Supply Drain + 15V de
Supply Drain - 15V de
Supply Drain + 5V de
*
645 (850 max)
± 15 ± 0.5 (max)
+ 5 ± 0.25 (max)
+16
-21
+18
Oto +70
-25to+85
-55to+125
*
*
*
NOTES
I Logic "0" = O.8V~max. Logic"." "" 2.0V, min for inputs. FordigitaloutputsLogic"O" '" + O.4V max. Logic"t":: 2.4Vmin.
lTestedon:!:: IOV and 0 to + IOVranges.
JAdjustabletozero.
"Full Scale Range.
~Guaranteed but not 100% production tested.
6Convemon time may be shortened with "Short Cycle" set (or lower resolution.
7CSB-CompJeme.ulry Straight Binary. COB-CompJementatyOffset Binary. CTC-Complementary Twos Complement.
"eTc coding obtained by invertingMSB(Pin I).
"With Pin 23. dock rateconrrols tied to digital ground.
*Spec;iflCarionssameasAD1376JD.
Specifications subjcci to change without notice.
3-168 ANALOG-TO-DIGITAL CONVERTERS
LSTTLLoads
LSTTLLoads
kHz
mW
Vde
Vde
mA
mA
mA
'C
'C
'C
AD1376
~
i!i
,
~
~
..,
ili
>
~
!i
1···,I-_++'. . .
-+____-i_,_I2_LS_B_,_2._BIT_--I
:i" ....61---~~"It_------1-----1
t
~
II!
112lSB '4-81T
L------,L..----....J,.-----.J2•
:::I 0.001 S
+70
+2'
TEMPERATURE - "C
1/2LS8 13-81T
....31----...3I-.f....~-=----1-----1
CONVERSION TIME -II.
Figure 1. LinearityErrorvs. Temperature
Figure 2. AD 1376 Nonlinearity vs. Conversion Time
+•.,I----+--+--+---i----+--+---t
+0,088
~
~ +O.03S .....:----+--+--+---ii---2'f""'O-f--H'--,f--:>I
I
i
-0.088
-··'+---l---+-1--+--1---l--+--1
+,.
+20
+3.
+40
+50
+ID
+7.
TEMPERATURE - "C
Figure 3. AD1376 Gain DriftErrorvs. Temperature
ORDERING GUIDE
Model
Max Linearity
Error
Temperature
Range
Package
Option·
AD1376JD
AD1376KD
O.006%FSR
O.003%FSR
Oto + 70°C
Oto + 70°C
Ceramic (DH-32E)
Ceramic (DH-32E)
*See Section 14 for package outline information.
ANALOG-TO-O/GITAL CONVERTERS 3-169
I
THEORY OF OPERATION
DESCRIPTION OF OPERATION
The analog continuum is partitioned into 21.6 discrete ranges for
16-bit conversion. All analog values within a given quantum are
represented by the same digital code, usually assigned to the
nominal midrange value. There is an inherent quantization
uncertainty of ± 1/2LSB, associated with the resolution, in
addition to the actual conversion errors.
On receipt of a CONVERT START command, the AD1376
converts the voltage at its analog input into an equivalent 16-bit
binary number. This conversion is accomplished as follows: the
16-bit successive-approlrimation register (SAR) has its 16-bit
outputs connected both to the device bit output pins and to the
corresponding bit inputs of the feedback DAC. The analog
input is successively compared to the feedback DAC output,
one bit at a time (MSB first, LSB last). The decision to keep or
reject each bit is then made at the completion of each bit comparison
period, depending on the state of the comparator at that time.
The actual conversion errors that are associated with AID converters are combinations of analog errors due to the linear circuitry,
matching and tracking properties of the ladder and scaling networks, reference error and power supply rejection. The matching
and tracking errors in the converter have been minimized by the
use of monolithic DACs that include the scaling network. The
initial gain and offset errors are specified at ± 0.2% FSR for
gain and ±O.I% FSR for offset. These errors may be trimmed
to zero by the use of external trim circuits as shown in Figures
5 and 6. Linearity error is defined for unipolar ranges as the
deviation from a true straight line transfer characteristic from a
zero voltage analog input, which ca1ls for a zero digital output,
to a point which is defmed as a full scale. The linearity error is
based on the DAC resistor ratios. It is unadjustable and is the
most meaningful indication of AID converter accuracy. Differential
nonlinearity is a
of the deviation in the staircase step
width between codes from the ideal least significant bit step size
(Figure 4).
measure
Monotonic behavior requires that the differential linearity error
be less than ILSB, however a monotonic convener can have
missing codes; the AD1376 is specified as having no missing
codes over temperature ranges as specified on the data page.
There are three types of drift error over temperature: offset,
gain and linearity. Offset drift causes a shift of the transfer
characteristic left or right on the diagram over the operating
temperature range. Gain drift causes a rotation of the transfer
characteristic about the zero for unipolar ranges or minus full
scale point for bipolar ranges. The worst case accuracy drift is
the summation of all three drift errors over temperature. Statistically, however, the drift error behaves as the root-sum-squared
(RSS) and can be shown as:
RSS = Veol + eol + ELl
Gain Drift Error (ppm?C)
Offset Drift Error (ppm of FSRrC)
EL = Linearity Error (ppm of FSRrC)
eo =
eo =
GAIN ADJUSTMENT
The gain adjust circuit consists of a lOOppmf'C potentiometer
connected across ± V s with its slider connected through a 300kn
resistor to the gain adjust Pin 29 as shown in Figure 5.
If no external trim adjustment is desired, Pin 27 (offset adj) and
Pin 29 (gain adj) may be left open.
+15V
100ppmrc
l~~n ~_3..
oovkn_........
lOOkn
AD1376
-15V
Figure 5. Gain Adjustment Circuit (:t:0.2% FSR)
OFFSET ADJUSTMENT
The zero adjust circuit consists of a l00ppmf'C potentiometer
connected across ± V s with its slider connected through a 1.8Mfi
resistor to Comparator Input Pin 27 for all ranges. As shown in
Figure 6, the tolerance of this fixed resistor is not critical, and a
carbon composition type is generally adequate. Using a carbon
composition resistor having a -1200ppmI"C tempco contributes
a worst-case offset tempco of 32LSB I4 x 61ppmILSB I4 x
l200ppmI"C = 2.3ppmI"C of FSR, if the OFFSET ADJ potentiometer is set at either end of its adjustment range. Since the
maximum offset adjustment required is typically no more than
± 16LSB 14, use of a carbon composition offset summing resistor
typically contributes no more than IppmI"C of FSR offset
tempco.
,.,;r
TO
l00kn
•
1=-i>L7_ _A_D_1_37_6_--I
-15V
Figure 6. Offset Adjustment Circuit (:t: 0.3% FSR)
An alternate offset adjust circuit, which contributes negligible
offset tempco if metal ftlm resistors (tempco < lOOppmI"C) are
used, is shown in Figure 7.
AD1376
I
~-1LSB
Rgure4. TrsnsferCharacteristics for an Ideal Bipolar AID
Figure 7. Low Tempco Zero Adjustment Circuit
In either adjust circuit, the fIXed resistor connected to Pin 27
should be located close to this pin to keep the pin connection
runs shon. Comparator Input Pin 27 is quite sensitive to external
noise pick-up and should be guarded by analog common.
3-170 ANALOG-TO-DIGITAL CONVERTERS
AD1376
TIMING
' - - - - - - " ' 1 \ - 1-
I""'L
(ST:~JS~-----------:20n5 MIN TO 9On5
CLOCK~
SERIAL
co"s'\"..":,".;
.n .
CONVERSION
OUT
MSB--'
"o!3l
r.... '21
i . . i . iii . . . . . .
~ 14)
BlTz;;r Y ' ' ' I . ,-+..\-+-H\\-+-+-+--+--+\-+-+-""I
I
I
H
::;: :::r-----L....l:.". . ,"".. \fm.~:
IT
BIT_:::
..,"
=:Jesilnation
COB*
orCTC**
COB*
orCTC**
COB*
orCTC**
CSB***
CSB***
FSR
2-
20V
10V
2-
10V
2-
SV
2-
n-8
n=IO
n=12
n=13
n=14
n=15
78.13mV
19.53mV
4.88mV
2.44mV
1.22mV
0.61mV
39.06mV
9.77mV
2.44mV
1.22mV
0.61mV
O.3lmV
19.53mV
4.88mV
1.22mV
0.61mV
0.31mV
0.15mV
One Least
Significant
Bit (LSB)
za
5V
2-
39.06mV
9.77mV
2.44mV
1.22mV
0.61mV
0.31mV
19.53mV
4.88mV
1.22mV
0.61mV
0.31mV
0.15mV
NOTES
*COB = Complementary Offset Binary.
**CTC = ComplementaryTwosCom~t-achieved by using an invertcr tocomplcmcnt
the most sisnificant bit to produce (MSB).
***CSB = Complcmcntary Straight Binary.
Table IV, Input Voltage Range and LS8 Values
CALmRATION (I4-Bit Resolution Eumples)
External ZERO ADJ and GAIN ADJ potentiometers, connected
as shown in Figures 5 and 6, are used for device calibration. To
prevent interaction of these two adjustments, Zero is always
adjusted fIrst and then Gain. Zero is adjusted with the analog
input near the most negative end of the analog range (0 for
unipolar and - FS for bipolar input ranges). Gain is adjusted
with the analog input near the most positive end of the analog
range.
3-172 ANALOG-TO-DIGITAL CONVERTERS
o to
+ lOY Range: Set analog input to + ILSB 14 = O.OOO6IV.
Adjust Zero for digital output = 11111111111110. Zero is now
calibrated. Set analog input to +FSR - 2LSB = +9.99878V.
Adjust Gain for OOOOOOOOOOOOO I digital output code; full-scale
(Gain) is now calibrated. Half-scale calibration check: set analog
input to + 5.00000V; digital output code should be
01111111111111.
AD1376
-lOY to +IOV Range: Set analog input to -9.99878V; adjust
zero fOr 11111 11 III Il 0 digital output (complementary offset
binary) code. Set analog input to 9.997S6V; adjust Gain for
00000000000001 digital output (complementary offset binary)
code. Half-scale calibration check: set analog input to O.OOOOOV;
digital output (complementary offset binary) code should be
Olllllllllllll.
+15V de
1.4Mtiz@ 5V
5kU
~o------{
~
1040kHz
~t
AD1376
DGND L-_ _ _ _ _ _~
Figure 14. Clock Rate Control Circuit
15~-4---4---+---+---r---r--~
50L--~--~--~--~~'~O--~'2~~'4~"5
PIN 23 CONTROL VOLTAGE
NOTE: ANALOG (~I AND DIGITAL (~J GNDS
-15V
ARE NOT TIED INTERNALLY AND MUST BE
CONNECTED EXTERNALLY.
Figure 15. Conversion Time vs. Control Voltage
Figure 12. Analog and Power Connections for Unipolar 0
to + 10VlnputRange
NOTE: ANALOG
ci') AND DIGITAL C~) GNOS
-15V
ARE NOT TIED INTERNALLY AND MUST 8E
CONNECTED EXTERNALL V.
Figure 13. Analog and Power Connections for Bipolar
+ 10Vto + 10VlnputRange
Other Ranges: Representative digital coding for a to + lOY and
-lOY to + lOY ranges is given above. Coding relationships and
calibration points for to +SV, -2.SV to +2.SV and -SV to
+ SV ranges can be found by halving proportionally the corresponding code equivalents listed for the to + lOY and -lOY to
+ lOY ranges, respectively, as indicated in Table III.
a
a
Zero and full-scale calibration can be accomplished to a precision
of approximately ± 1I2LSB using the static adjustment procedure
described above. By summing a small sine or triangular wave
voltage with the signal applied to the analog input, the output
can be cycled through each of the calibration codes of interest to
more accurately determine the center (or end points) of each
discrete quantization level. A detailed description of this dynamic
calibration technique is presented in Analog-Digital Conversion
Htmdbook, edited by D. H. Sheingold, Prentice-Hall, Inc.,
1986.
GROUNDING, DECOUPLING AND LAYOUT
CONSIDERATIONS
Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
"grounds" are usually referred to as the Logic Power Return,
Analog Common (Analog Power Return) and Analog Signal
Ground. These grounds (Pins 19 and 22) must be tied together
at one point for the AD1376 as close as possible to the converter.
Ideally, a single solid analog ground plane under the converter
would be desirable. Current flows through the wires and etch
stripes of the circuit cards, and since these paths have resistance
and inductance, hundreds of millivolts can be generated between
the system analog ground point and the ground pins of the
AD1376. Separate wide conductor stripe ground returns should
be provided for high resolution converters to minimize noise
and IR losses from the current flow in the path from the converter
to the system ground point. In this way AD1376 supply currents
and other digital logic-gate return currents are not summed into
the same return path as analog signals where they would cause
measurement errors.
Each of the AD1376 supply terminals should be capacitively
decoupled as close to the AD1376 as possible. A large value
capacitor such as Ijl.F in parallel with a O.Ijl.F capacitor is usually
sufficient. Analog supplies are to be bypassed to the Analog
Power Return pin and the logic supply is bypassed to the Logic
Power Return pin.
The metal cover is internally grounded with respect to the power
supplies, grounds and electrical signals. Do not externally ground
the cover.
CLOCK RATE CONTROL
The AD1376 may be operated at faster conversion times by
connecting the Clock Rate Control (Pin 23) to an external multitum
trim potentiometer (TCR e=:
OUT~
-..j \+- 30n5 TO 120n5 MAX
Figure 7. Clock High to Serial Out Valid
(non-return-to-zero) format. Serial and parallel data outputs
change state on positive-going clock edges. Serial data is guaranteed valid 120ns after the rising clock edges, permitting serial
data to be clocked directly into a receiving register on the
negative-going clock edges as shown in Figure 7. There are 17
negative-going clock edges in the complete 16-bit conversion
cycle. The first negative edge shifts an invalid bit into the register, which is shifted out on the last negative-going clock edge.
All serial data bits will have been correctly transferred and be in
the receiving shift register locations shown at the completion of
the conversion period.
AD1380
INPUT SCALING
The AD1380 inputs should be scaled as close to the maximum
input signal range as possible in order to utilize the maximum
signal resolution of the ND converter. Connect the input signal
as shown in Table I. See Figure 8 for circuit details.
10VSPAN
R2
3.7Skll
Input
Signal
Line
Output
Code
Connect
Pin 4
to Pin
Connect
Pin 7
to
Connect
Input
Signal to
Connect
Pin 32
to
±IOV
±5V
±2.5V
OV to +5V
OV to +lOV
COB
COB
COB
CSB
CSB
5
5
5
NC
NC
32
Open
PinS
Pin 5
Open
31
31
31
31
31
7
6
6
6
6
NOTE
Pin 5 is extremely sensitive to noise and should be guarded by analog common.
TOSAR
Table I. AD1380 Input Scaling Connections
7 Skll
COMPARATOR
BIPOLAR ~;;:;-=----OFFSET &--yy~ VREF
ANALOG
I'ii'L--
COMMON~
Figure 8. AD1380 Input Scaling Circuit
Code Under Test
MSB
LSB
000
000*
Range
+ Full Scale
±lOV
+lOV
-3/2LSB
Low Side Transition Value
±5V
± 2.5V
o to +lOV
+2.5V
+5V
+lOV
-3/2LSB
-3/2LSB
-3/2LSB
o to +5V
+5V
-3/2LSB
011
111
Mid Scale
0-1I2LSB
0-1I2LSB
0-1I2LSB
+5V-1I2LSB
+2.5V-1I2LSB
III
110
-Full Scale
-lOY
+1I2LSB
-5V
+1I2LSB
-2.5V
+1I2LSB
OV
+1I2LSB
OV
+1I2LSB
NOTE
For LSB value for range and resolution used, see Table III.
*Voltages given are the nominal value for transition to the code specified.
Table II. Transition Values vs. Calibration Codes
Analog Input
Voltage Range
±lOV
±5V
±2.5V
OV
Code
Designation
COB*
or CTC**
COB*
orCTC**
COB*
orCTC**
CSB***
CSB***
lOY
2n
One Least FSR
Significant
(Bit LSB)
NOTES
·COB
**CTC
to
+lOV
OV to +5V
- n-
FSR
2
-
20V
2n
lOY
- n
2
SV
-n
2
-
SV
-n
2
n=8
n=lO
n=12
n=13
n=14
n=15
78.13mV
19.53mV
4.88mV
2.44mV
l.22mV
0.61mV
39.06mV
9.77mV
2.44mV
l.22mV
0.61mV
0.31mV
19.53mV
4.88mV
l.22mV
0.61mV
0.31mV
0.15mV
39.06mV
9.77mV
2.44mV
1. 22mV
0.61mV
0.31mV
19.53mV
4.88mV
1.22mV
0.61mV
0.31mV
0.15mV
= Complementary Offset Binary.
= Complementary Twos Complement -
achieved by using an inverter to complement
the most significant bit to produce (MSB).
***CSB "'" Complementary Straight Binary.
Table III. Input Voltage Range and LS8 Values
ANALOG-TO-DIGITAL CONVERTERS 3-187
II
CALIBRATION (I4-Bit .Resolution Examples)
External ZERO ADJ and GAIN ADJ potentiometers, connected
as shown in Figures 2 and 3, are used for device calibration. To
prevent interaction of these two adjustments, Zero is always
adjusted first and then Gain. Zero is adjusted with the analog
input near the most negative end oCthe analog range (0 for
unipolar and - FS for bipolar input ranges). Gain is adjusted
with the analog input near the most positive end of the analog
range.
o to + lOY Range:
Set analog input to + ILSB I4 =
0.0006IV. Adjust Zero for digital output = 11111111111110.
Zero is now calibrated. Set analog .input to + FSR - 2LSB
= + 9.99878V. Adjust Gain for 00000000000001 digital output
code; full scale (Gain) is now calibrated. Half-scale calibration
check: set analog input to +5.00000V; digital output code
should be 01111111111111.
-lOY to + lOY Range: Set analog input to -9.99878V; adjust
zero for 1111111111110 digital output (complementary offset
binary) code. Set analog input to 9.99756V; adjust Gain for
00000000000001 digital output (complementary offset binary)
code. Halt~scale calibration check: set analog input to O.OOOOOV;
digital output (complementary offset binary) code should be
olllllllllllli.
NOTE: ANALOG 1., AND DIGITAL ( ..'" GNDS
ARE NOT TIED INTERNALLY AND MUST 8E
CONNECTED EXTERNALLY.
Figure 9. Analog and Power Connections for Unipolar 0 to
+ 10V Input Range
Other Ranges: Representative digital coding for 0 to + lOY
and -lOY to + lOY ranges is given above. Coding relationships
and calibration points for 0 to +5V, -2.5V to +2.5V and -5V
to +5V ranges can be found by halving proportionally the corresponding code equivalents listed for the 0 to + lOY and -lOY to
+ lOY ranges, respectively, as indicated in "fable II.
Zero and full-scale calibration can be accomplished to a precision of approxin!ately ± 1I2LSB using the static adjustment procedure described above. By summing a small sine or triangular
wave voltage with the signal applied to the analog input, the
output can be cycled through each of the calibration codes of
interest to more accurately determine the center (or end points)
of each discrete quantization level. A detailed description of this
dynamic calibration technique is presented in Analog-Digital
Conversion Handbook, edited by D. H. Sheingold, Prentice-Hall,
Inc., 1986.
GROUNDING, DECOUPLING AND LAYOUT
CONSIDERATIONS
Many data acquisition components have two or more ground
pins which are not connected together within the device. These
"grounds" are usually referred to as the Logic Power Return,
Analog Common (Analog Power Return) and Analog Signal
Ground. These grounds (Pins 8 and 30) must be tied together at
one point for the AD 1380 as close as possible to the converter.
Ideally, a single, solid analog ground plane under the converter
would be desirable. Current flows through the wires and etch
stripes on the circuit cards, and since these paths have resistance
and inductance, hundreds of millivolts can be generated between
the system analog ground point and the ground pins of the
AD1380. Separate wide conductor stripe ground returns should
be provided for high resolution converters to minimize noise and
IR losses from the current flow in the path from the converter
to the system ground point. In this way AD1380 supply currents and other digital logic-gate return currents are not
summed into the same return path as analog signals where they
would cause measurement errors.
Each of the AD 1380 supply terminals should be capacitively
decoupled as close to the AD 1380 as possible. A large value
capacitor such as IflF in parallel with a O.lflF capacitor is usually sufficient. Analog supplies are to be bypassed to the Analog
Power Return pin and the logic supply is bypassed to the Logic
Power Return pin.
The metal cover is internally grounded with respect to the
power supplies, grounds and electrical signals. Do not externally
ground the cover.
NOTE: ANALOG IVI AND DIGITAL (~I GNDS
-15V
ARE NOT TIED INTERNALLY AND MUST BE
CONNECTED EXTERNALLY.
Figure 10. Analog and Power Connections for Bipolar -10V
to + 10V Input Range
3-188 ANALOG-TO-DIGITAL CONVERTERS
AD1380
APPLICATION
AD1380 Dynamic Performance
High performance sampling analog-to-digital converters like the
AD 1380 require dynamic characterization to assure they meet or
exceed their desired performance parameters for signal processing applications. Key dynamic parameters include signal-to-noise
ratio (SNR) and total harmonic distortion (THD), which are
characterized using Fast Fourier Transform (FFT) analysis
techniques.
The results of a 1024-point FFT demonstrate the exceptional
performance of the converter, particularly in terms of low noise
and harmonic distortion.
In Figure 11, the vertical scale is based on a full scale input referenced as OdB. In this way, all (frequency) energy cells can be
calculated with respect to full scale rms inputs.
The results of that characterization are shown in Figure 11. In
the test a 13.2kHz sine wave is applied as the analog input (fa)
at a level of 10dB below full scale; the AD1380 is operated at a
word rate of 50kHz (its maximum sampling frequency).
Total harmonic distortion is calculated by adding the RMS
energy of the first four harmonics and equals -97.5dB. Increasing the input signal amplitude to -O.4dB of full scale, causes
THD to increase to -80.6dB as shown in Figure 12.
The resulting signal-to-noise ratio is 83.2dB, which corresponds
to a noise floor of -93.2dB.
0
-20
-30
iii
~
-40
>
I-
-50
enZ
w
Q
-60
a::
-70
...
-80
3:
Q,.
w
a::
= 13232
= 50000
= -0.4
= -91.0
= -80.6
FUNDAMENTAL
SAMPLE RATE
SIGNAL
(dB)
NOISE
(dB)
THD
(dB)
-10
2f (dB)
3f (dB)
4f (dB)
-90
= -100.9
= -101.8
= -111.9
-100
-110
"'1 Ii 0."'11 Ill.d .11. ... 1.oIIJ 1~1I11
-120
44
86
129
171
214
257
I
III. dL/,l
.lit . ~1.1
299
384
342
• II.. I,~~ iii
JI
427
512
469
FREQUENCY (x 48.8281 Hz)
20V SPAN
Figure 11.
0
FUNDAMENTAL
SAMPLE RATE
SIGNAL
(dB)
NOISE
(dB)
THD
(dB)
-10
-20
iii
~
-30
>
-40
enz
-50
Q
-60
= 13232
= 50000
= -10.0
=
-93.2
= -97.5
I-
w
a::
3:
Q,.
...w
a::
-70
-80
2f (dB)
3f (dB)
4f (dB)
-90
-100
-110
-120
I
J
= -80.7
= -99.9
= -102.9
~
-
-
1
Ikjl~ .111... II~II~ ~II~I, &Jull II.. 11. t..Jj ~l IfL.",.Ui..'IJ~, lll,l'ul 1.[ Uta.
1
44
86
129
171
214
257
299
342
384
427
469
512
FREQUENCY (x48.8281Hz)
20V SPAN
Figure 12.
ANALOG-TO-DIGITAL CONVERTERS 3-189
I
At lower input frequencies, however, THD performance is
improved. Figure 13 shows a full scale (-O.3dB) input signal at
1.41kHz. THD is now -96.0dB.
The ultimate noise floor can be seen with low level input signals
of any frequency. In Figure 14 the noise floor is at -94dB, as
demonstrated with an input signal of 24kHz at - 39.8dB.
o
FUNDAMENTAL
SAMPLE RATE
(dB)
SIGNAL
(dB)
NOISE
THO
(dB)
-10
_ -20
co
~-30
>
= 1416
= 50000
= -0.3
= -91.9
= -96.0
5i -40
iiic -50
a:
::
-60
~ -70
w
a: -80
-90
2t (dB)
3t (dB)
4t (dB)
-100
-110
-120
~~Ij ~II ~,.
1
44
II.Jl.l L.tl~.
86
129
JI1
171
.III
214
I~
257
.ill.11
299
= _97.8
= -102.8
= -106.9
...I.l.~ IJ&.J.L .I
342
384
427
.lLIILII
469
512
FREQUENCY (x48.8281Hz)
20V SPAN
Figure 13.
0
=
=
=
=
FUNDAMENTAL
23975_
SAMPLE RATE
50000 I - -39.8 _
SIGNAL
(dB)
I-NOISE
(dB)
-94.3
(dB) = -107.9 _ I - THO
-10
-20
~
~
-30
>
I- -40
iii
Z
w
-50
c
a: -60
~
....w
a:
-70
-80
-90
2t (dB)
3t (dB)
4t (dB)
-100
-110
J.hl
-120
1
11.Jj1~ u
44
86
j'l
,d,
129
.1.111..1
,I. ILoIl
171
214
257
299
JI.
d,
342
FREQUENCY (x48.8281Hz)
20V SPAN
Figure 14.
3-190 ANALOG-TO-DIGITAL CONVERTERS
= -116.0
= -113.6
= -112.4
1
384
,I.
427
t- - t-
-
Ld .1
469
512
1IIIIIIII ANALOG
WDEVICES
FEATURES
AC Characterized and Specified
200k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
72 dB S/N+D (K Gradel
Twos Complement Data Format (Bipolar Model
Straight Binary Data Format (Unipolar Model
10 Mil Input Impedance
8-Bit or 16-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
PRODUCT DESCRIPTION
The AD1678 is a complete 12-bit monolithic analog-to-digital
converter, consisting of a sample-hold amplifier (SHA), a microprocessor compatible bus interface, a voltage reference and clock
generation circuitry.
The AD1678 offers a choice of digital interface formats; the 12
data bits can be accessed by a 16-bit bus in a single read operation or by an 8-bit bus in two read operations (8+4), with right
or left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of IOV with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input
impedance (10 MO) allows direct connection to unbuffered
sources without signal degradation.
This product is fabricated on Analog Devices' BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD1678 operates from +5 V and ± 12 V supplies and dissipates 745 mW. A 28-pin plastic DIP and a 0.6" wide ceramic
DIP are available. Contact factory for surface-mount package
options.
12-Bit 200 KSPS
Complete Sampling ADC
AD1678 I
AD1678 FUNCTIONAL BLOCK DIAGRAM
cs
sc
OE
EOCEN
SYNC
1218
EOC
II
PRODUCT HIGHLIGHTS
1. INTEGRATION: The AD1678 minimizes external component requirements by combining a high speed sample-hold
amplifier (SHA), ADC, 5 V reference, clock and digital
interface on a single chip. This provides a fully specified
sampling AID function unattainable with discrete designs.
2. PERFORMANCE: The AD1678 provides a throughput of
200k conversions per second. SIN + D is 72 dB (K grade) at
10 kHz and remains flat beyond the Nyquist frequency.
3. SPECIFICATIONS: The AD1678 is specified for ac (or
"dynamic") specifications such as SIN + D ratio, THD and
IMD. These parameters are important in signal processing
applications as they represent the effect on the spectral content of the input signal.
4. EASE OF USE: The pinout is designed for easy board layout, and the choice of single or two read cycle output provides compatibility with 16- or 8-bit buses. Factory trimming
eliminates the need for calibration modes or external trimming to achieve rated performance.
5. RELIABILITY: The AD1678 utilizes Analog Devices'
monolithic BiMOS technology. This ensures long term reliability compared to multichip and hybrid designs.
ANALOG-TO-DIGITAL CONVERTERS 3-191
SPECIFICATIONS
AC SPECIFICATIONS
to TmB., Vee = +12 V, VEE = -12 V, Voo = +5 V,
= 10.06 kHz!, unless otherwise noted)
(lmi.
fiN
Parameter
Min
SIGNAL-TO-NOISE AND DISTORTION (SIN+D) RATI02
@ +250(;
T min to Tmax
70
70
TOTAL HARMONIC DISTORTION (THD/
@ +250(;
Tmin to Tmax
PEA;!<. SPURIOUS OR PEAK HARMONIC COMPONENT
FULLPOWERBAND~DTH
'SAMPLE
AD167SJ
Typ
Max
= 200 lISPS,
Min
AD167SK
Typ
Max
72
71
71
71
-SO
0.010
-78
0.012
-88
0.004
-85
0.005
-SO
dB
0.010
-78
0.012
dB
-87
-SO
-87
-SO
dB
1
500
INTERMODULATION DISTORTION (IMD)4
2nd Order Products
3rd Order Products
dB
dB
-S8
0.004
-85
0.005
1
FULL LINEAR BANDWIDTH
73
73
Units
-SO
-SO
%
MH2
500
-85
-90
%
kHz
-85
-90
-SO
-80
dB
dB
NOTE
'fIN amplitude = -0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a 0 dB
(9.997 V p.p) input signal.
'See Figures 7 and 8 for higher frequencies and other input amplitudes.
'See Figure 6 for other conditions.
'fA = 9.08 kHz, f. = 9.58 kHz, with fSAMPLE = 200 KSPS. See Figure 10 and DefInition of Specifications section.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(lml. to
Parameter
LOGIC INPUTS
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current
IJH
Low Level Input Current
IlL
Input Capacitance
C IN
LOGIC OUTPUTS
VOH High Level Output Voltage
VOL
loz
Coz
Low Level Output Voltage
High Z Leakage Current
High Z Output Capacitance
T...., Vee = +12 V, VEE = -12 V, Voo = +5 V ±10%)
Test Conditions
Min
Max
Units
O.S
10
10
10
V
V
!LA
!LA
pF
2.4
VIN
VIN
= 5V
= OV
IOH
IOH
IOL
VIN
= 0.1 rnA
= 0.5 rnA
= 1.6 rnA
= 0 or 5 V
4.0
2.4
0.4
10
10
V
V
V
!LA
pF
NOTES
SpecifIcations shown in boldface are tested on all devices at fInal electrical test. Results from those tests are used to calculate outgoing quality levels.
All min and max specifIcations are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
3-192 ANALOG-TO-DIGITAL CONVERTERS
AD1678
DC SPECIFICATIONS
(@
+25°C, Vee = +12 V, VEE = -12 V, Vaa = +5 Vunless otherwise indicated)
Parameter
ACCURACY
Resolution
Differential Linearity
T min to T max (No Missing Codes)
Integral Linearity Error
Unipolar Zero Error'
Bipolar Zero Error'
Unipolar Gain Error,,2
Bipolar Gain Error,,2
Temperature Drift (Coefficients)3
Unipolar Zero
Bipolar Zero
Unipolar Gain
Bipolar Gain
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
Input Resistance
Input Capacitance (fiN = 100 kHz)
Input Settling Time
Aperture Delay
Aperture Jitter
INTERNAL VOLTAGE REFERENCE
Output Voltage'
External Load
Unipolar Mode
Bipolar Mode
POWER SUPPLIES (Tmin to T max)
Operating Voltages
Vcc
VEE
Voo
Operating Current
Icc
lEE
100
Power Consumption
Min
AD1678J
Typ
Max
12
AD1678K
Typ
Max
Min
12
Bits
12
12
±I
±4
±4
±3
±3
±I
±4
±4
±3
±3
Bits
LSB
LSB
LSB
LSB
LSB
±2 (10)
±2 (10)
±4 (20)
±4 (20)
±2 (10)
±2 (10)
±4 (20)
±4 (20)
LSB
LSB
LSB
LSB
0
-5
+10
+5
0
-5
+10
+5
10
10
10
10
I
20
5
I
20
5
ISO
4.95
ISO
5.05
4.95
+12
-12
+5
+12.6
-11.4
+5.5
18
25
8
560
20
34
12
745
+11.4
-12.6
+4.5
(ppmrC)
(ppml"C)
(ppml"C)
(ppml"C)
V
V
MO
pF
jJ.s
ns
ps
5.05
V
+1.5
+0.5
rnA
rnA
+12
-12
+5
+12.6
-11.4
+5.5
V
V
V
18
25
8
560
20
34
12
745
rnA
rnA
mA
mW
+1.5
+0.5
+11.4
-12.6
+4.5
Units
NOTES
I Adjustable to zero; see Figures 12 and 13.
2Includes internal voltage reference error.
'Includes internal voltage reference drift.
'With maximum external load applied.
Specifications shown in boldface are tested on all devices at final elecrrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
ANALOG-TO-DIGITAL CONVERTERS 3-193
TIMING SPECIFICATIONS (lmiD to Tm••, Vee =
Parameter
Symbol
Min
SC Delay
Conversion Rate
Convert Pulse Width
Aperture Delay
Conversion Time 1
Status Delay
Access Time2
Float Delay'
Update Delay
Format Setup
OE Delay
Read Pulse Width
tsc
50
Max
Typ
5
tcR
ISO
tcP
tAD
20
5
4.47
3.9
tc
tso
tBA
tpo
tuo
tps
tOE
tRP
Conversion Delay
EOCEN Delay
+12 V, VEE = -12 V, Vaa = +5 Vl
0
400
100
10
80
200
60
20
100
ns
Il.s
ns
ns
Il.s
ns
ns
ns
ns
ns
ns
ns4
nss
ns
ns
ISO
ISO
tco
tEO
Units
20
NOTES
lInc1udes Acquisition Time.
_ _ __
'Measured from the falling edge of OElEOCEN (0.8 V) to the time at which the data Iines/EOC cross 2.0 V or 0.8 V.
See Figure 3; COUT = 100 pF. _ _ __
'Measured from the rising edge of OElEOCEN (2.0 V) to the time at which the output voltage changes by 0.5 V.
See Figure 3; COUT = 10 pF.
412-bit read mode.
'8·bit read mode.
Specifications subject to change without notice.
SHA
EOC'
mACK
I
..
HOlD
I
mACK
HOLD
---'--~r-~tu-D~~--;--r-------
CONTENT OF
R~~~~~
I
-~~=====:::-;:-:"',:::;j-r-"'---DATA 0
NOTE
'SEE END-OFoCONVERT (EOCI PARAGRAPH FOR DETAILS.
Figure 2. EOC Timing
X,-__D,A_T_A_'_ __
I
vv
NOTES
'IN ASYNCHRONOUS MODE. STATE OF CS DOES NOT AFFECT OPERATION. SEE
THE START CONVERSION mUTH TABLE FOR DETAILS.
'EOCEiii = LOW; SEE RGURE 2. IN SYNCHRONOUS MODE. EOC IS A THREE·STATE
OUTPUT. IN ASYNCHRONOUS MODE. EDC IS AN OPEN DRAIN OUTPUT.
'DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
TEST
ACCESS TIME HIGH Z TO LOGIC LOW
FLOAT TIME LOGIC HIGH TO HIGH Z
ACCESS TIME HIGH Z TO LOGIC HIGH
FLOAT TIME LOGIC LOW TO HIGH Z
5V
5 V
OV
oV
l00pF
10 pF
l00pF
10 pF
Figure 1. Conversion Timing
Figure 3. Load Circuit for Bus Timing Specifications
3-194 ANALOG-TO-DIGITAL CONVERTERS
AD1678
CONVERSION CONTROL
In synchronous mode (SYNC = HIGH), both Chip Select (CS)
and Start Convert (SC) must be brought LOW to start a conversion. CS should be LOW tsc before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing SC low, regardless of the state of CS.
than 1 JLS before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW if
the maximum throughput rate is needed.
Before a conversion is started, End-Of-Convert (EOC) is HIGH,
and the sample-hold is in track mode. Mter a conversion is
started, the sample-hold goes into hold mode and EOC goes
LOW, signifying that a conversion is in progress. During the
conversion, the sample-hold will go back into track mode and
start acquiring the next sample. EOC goes HIGH when the
conversion is finished.
END·OF·CONVERT
In asynchronous mode, End-Of-Convert (EOC) is an open drain
output (requiring a minimum 3 k!l pull-up resistor) enabled by
End-Of-Convert ENable (EOCEN). In synchronous mode, EOC
is a three-state output which is enabled by EOCEN and CS. See
the Conversion Status Truth Table for details. Access (tBA) and
float (t FO) timing specifications do not apply in asynchronous
mode where they are a function of the time constant formed by
the 10 pF output capacitance and the pull-up resistor.
In track mode, the sample-hold will settle to ±0.01 % (12 bits)
in 1 JLS maximum. The acquisition time does not affect the
throughput rate as the AD1678 goes back into track mode more
START CONVERSION TRUTH TABLE
INPUTS
CS
SC
1
1
X
1
0
t.
Start Conversion
1
t.
0
Start Conversion
(Not Recommended)
1
0
0
Continuous Conversion
0
X
1
No Conversion
0
X
t.
Start Conversion
0
X
0
Continuous Conversion
12-BIT MODE CODING FORMAT (1 LSB = 2.44 mY)
Output Code
VIN
0
5.000 V
9.9964 V
Synchronous
Mode
Bipolar Coding
(Twos Complement)
Unipolar Coding
(Straight Binary)
000 ... 0
100 ... 0
Ill ... 1
Output Code
VIN
-5.000 V
-0.002 V
0
+2.500 V
+4.9964 V
100 ... 0
III ... 1
000 ... 0
010 ... 0
011 ... 1
STATUS
SYNC
Asynchronous
Mode
No Conversion
NOTES
I = HIGH voltage level.
OUTPUT ENABLE TRUTH TABLES
o =
INPUTS
OUTPUT
(CS U OE)
DBll-DBO
1
LOW voltage level.
X = Don't care.
12·BIT MODE (12/8 = IDGH)
t.
= HIGH to LOW transition. Must stay low for t =!cP.
CONVERSION STATUS TRUTH TABLE
High Z
Enable 12-Bit Output
t.
INPUTS
OUTPUT
SYNC CS EOCEN EOC
INPUTS
Unipolar
Mode
Bipolar
Mode
OUTPUTS
RIL
HBE
X
X
1
1
0
1
0
1
1:.
1:.
1:.
1:.
0
1
0
"t
I
0
0
1
1
0
0
I
(CSUOE)
DBll ... DB4
__
0
0
1
0
0
1
Not Converting
1
1
X
HighZ
Either
1
X
1
HighZ
Either
0
X
0
0
Converting
0
X
0
HighZ
Not Converting
0
X
1
HighZ
Either
Synchronous
Mode
~HighZ
c
h
d
a
i
e
k
I
0
a
f
b
a
g
c
a
h
d
a
i
e
i
j
k
I
0
0
e
a
i
a
e
1:.
1:.
1:.
0
f
b
j
a
0
g
0
b
j
f
0
b
j
f
0
c
d
k
g
0
I
c
d
k
g
0
I
h
Asynchronous
Mode*
0
h
0
STATUS
1
S·BIT MODE (12/8 = LOW)
0
Converting
NOTES
=
o
HIGH vollage level.
= LOW vollage level.
X
= Don', care.
*EOC requires a pull-up resistor in asynchronous mode.
NOTES
I = HIGH voltage level.
o
= LOW vollage level.
X = Don't care.
U = Logical OR.
a = MSB.
I = LSB.
t. =
HIGH to LOW transition. Must
stay low for t = tRP •
ANALOG-TO-DIGITAL CONVERTERS 3-195
•
OUTPUT ENABLE OPERATION
The data bits (DBll-DBO) are three-state outputs enabled by
Chip Select (CS) and Output Enable (OE). CS should be LOW
tOE before OE is brought LOW. Bits DBI (RlL) and DBO
(HBE) are bidirectional. In lZ-bit mode they are data output
bits. In 8-bit mode they are inputs which defme the format of
the output register.
POWER-UP
One conversion sequence, consisting of one SC instruction, is
required after power-up to reset internal logic.
l
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFouT),
output coding is twos complement binary.
When EOC goes HIGH, the output register contains the results
of the previous conversion. A period of time tUD is required for
the present conversion results to be loaded into the output register. Bringing OE LOW tOE after CS goes LOW makes the output register contents available on the data bits. A period of time
tCD is required after OE is brought HIGH before the next SC
instruction is issued. This allows internal logic states to reset
and guarantees minimum aperture jitter for the next conversion.
Output Enable (OE) must be toggled to update the output
register in both 8- and 12-bit read modes.
DB11-DB4
------o-'MN",,-
DB11-nB4
+'v~"""'+---f
::~==~:
12/i
Figure 16. AD1678 to Z80 Interface
74F138
1218
SYNCH
TMS3Z0C25
AD1678
DATA BUS
AD1878
Figure 14. AD1678 to TMS320C25 Interface
-i 0811-084
DMD 15-81--_ _ _ _"'o.::T.:::"'::8'--_ _ _ _
Figure 17. AD1678 to ADSP-2100A Interface
Figure 15. AD1678 to 80186 DMA Interface
ADl678 TO 80186
Figure IS shows the AD1678 interfaced to the 80186 microprocessor. This interface allows the 80186's built-in DMA controller to transfer the ADI678 output into a RAM based FIFO
buffer of any length, with no microprocessor intervention.
In this application the ADI678 is configured in the asynchronous mode, which allows conversions to be initiated b"y an external trigger source independent of the microprocessor clock.
After each conversion, the AD1678 EOC signal generates a
DMA request to Channel I (DRQI). The subsequent DMA
READ operation resets the interrupt latch. The system designer
must assign a sufficient priority to the riMA channel to ensure
that the DMA request will be serviced before the completion
of the next conversion. This configuration can be used with
6 MHz and 8 MHz 80186 processors.
3-202 ANALOG-TO-OIGITAL CONVERTERS
AD1678 TO ANALOG DEVICES' ADSP-2100A
Figure 17 demonstrates the AD1678 interfaced to an ADSP2100A. With a clock frequency of 12.5 MHz, and instruction
execution in one 80 ns cycle, the digital signal processor will
support the AD1678 data memory interface with two hardware
wait states.
The converter is configured to run asynchronously using a sampling clock. The EOC output of the AD1678 gets asserted at the
end of each conversion and causes an interrupt. Upon interrupt,
the ADSP-2100A immediately executes a data memory write
instruction which asserts HBE. In the following cycle, the processor starts a data memory read (high byte read) by providing
an address on the DMA bus. The decoded address generates OE
for the converter. OE, together with logic and latches, is used to
force the ADSP-2100A into a two cycle wait state by generating
DMACK. The read operation is thus started and completed
within three processor cycles (240 ns). HBE is released during
"high byte read." This allows the processor to read the lower
byte of data as soon as "high byte read" is complete. The low
byte read operation executes in a similar manner to the first and
is completed during the next 240 ns.
14-Bit 100 KSPS
Complete Sampling ADC
AD1679 I
r.ANALOG
WDEVICES
FEATURES
AC Characterized and Specified
100k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
80 dB S/N+D (K Grade)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 MO Input Impedance
8-Bit Bus Interface (See AD1779 for 16-Bit Interface)
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
PRODUCT DESCRIPTION
The AD1679 is a complete, 14-bit monolithic analog-to-digital
converter, consisting of a sample-hold amplifier (SHA), a microprocessor compatible bus interface, a voltage reference and clock
generation circuitry.
The 14 data bits are accessed by an 8-bit bus in two read operations (8+6), with left justification. Data format is straight binary
for unipolar mode and twos complement binary for bipolar
mode. The input has a full-scale range of 10 V with a full power
bandwidth of 1 MHz and a full linear bandwidth of SOO kHz.
High input impedance (10 MO) allows direct connection to
unbuffered sources without signal degradation.
This product is fabricated on Analog Devices' BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm, which includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD1679 operates from +S V and ±12 V supplies and dissipates 720 mW. A 28-pin plastic DIP and a 0.6" wide ceramic
DIP are available. Contact factory for surface-mount package
options.
ADl679 FUNCTIONAL BLOCK DIAGRAM
cs
sc
OE
EOCEN
SYNC
EOC
•
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The AD1679 minimizes
external component requirements by combining a high speed
sample-hold amplifier (SHA), ADC, S V reference, clock and
digital interface on a single chip. This provides a fully specified sampling AID function unattainable with discrete
designs.
2. PERFORMANCE: The AD1679 provides a throughput of
lOOk conversions per second. SIN+D is 80 dB (K grade) at
10 kHz and remains flat beyond the Nyquist frequency.
3. SPECIFICATIONS: The AD1679 is specified for ac (or
"dynamic") parameters such as SIN + D ratio, THD and
IMD. These parameters are important in signal processing
applications as they indicate the AD 1679's effect on the spectral content of the input signal.
4. EASE OF USE: The pinout is designed for easy board
layout, and the two read output provides compatibility
with 8-bit buses. Factory trimming eliminates the need for
calibration modes or external trimming to achieve rated
performance.
S. RELIABILITY: The AD1679 utilizes Analog Devices'
monolithic BiMOS technology. This ensures long term reliability compared to multichip and hybrid designs.
ANALOG-TO-DIGITAL CONVERTERS 3-203
SPECIFICATIONS
1 Vee = +12 V ±5~, VEE = -12 V ±5%, VOO =
AC SPECIFICATIONS fiN =tolD.DDS
kHz unless otherwise noted)l
(Tmi.
m,.,
+ 5 V ±lD%, fSAMPLE = 100 KSPS,
AD1679J
Parameter
Min
Typ
SIGNAL-TO-NOISE AND DISTORTION (SIN+D) RATI0 2
-0.5 dB Input (Referred to -0 dB Input)
- 20 dB Input (Referred to - 20 dB Input)
-60 dB Input (Referred to -60 dB Input)
78
58
18
79
59
19
TOTAL HARMONIC DISTORTION (THD)3
@ +25°C
AD1679K
Max
Min
Typ
80
60
20
81
61
21
Max
dB
dB
dB
-90
-84
-90
-84
0.003
-88
0.004
0.006
-82
0.008
0.003
-88
0.004
0.006
-82
0.008
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
-90
-84
-90
-84
FULL POWER BANDWIDTH
1
T min to Tmax
FULL LINEAR BANDWIDTH
1
500
INTERMODULATION DISTORTION (IMD)4
2nd Order Products
3rd Order Products
-84
-84
dB
%
dB
%
dB
MHz
500
-90
-90
Units
kHz
-90
-90
-84
-84
dB
dB
NOTES
'f,N amplitude ~ -O.S dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a -0 dB (9.997 V p.p) input signal
unless otherwise noted.
2See Figure 7 for higher frequencies and other input amplitudes.
3See Figures 5 and 6 for other conditions.
'fA ~ 9.08 kHz, fB ~ 9.58 kHz, with fSAMPLE ~ 100 KSPS. See Figure 9 and Definition of Specifications section.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(All device types 1mi • to 1m3., Vee = +12 V ±5%, VEE = -12 V ±5%, Voo= +5 V ±lD%.J
Parameter
LOGIC
VIH
VIL
IIH
IlL
CIN
LOGIC
VOH
VOL
Ioz
Coz
INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Z Leakage Current
High Z Output Capacitance
Test Conditions
Min
Max
Units
0.8
10
10
10
V
V
J.LA
J.LA
pF
0.4
10
10
V
V
V
J.LA
pF
2.4
VIN
VIN
= 5V
= 0V
IOH
IOH
IOL
VIN
= 0.1 rnA
= 0.5mA
= 1.6 rnA
= 0 or 5 V
4.0
2.4
NOTES
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at QOC, +25°C and +70°C. Results from
those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
3-204 ANALOG-TO-OIGITAL CONVERTERS
AD1679
DC SPECIFICATIONS
(@ +25°C, Vee
Parameter
ACCURACY
Resolution
Integral Linearity Error
Differential Linearity
Tm;n to Tmax (No Missing Codes)
Unipolar Zero Error'
Bipolar Zero Error'
Unipolar Gain Error" 2
Bipolar Gain Error" 2
Temperature Drift (Coefficients)'
Unipolar Zero
Bipolar Zero
Unipolar Gain
Bipolar Gain
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
Input Resistance
Input Capacitance
Input Settling Time
Aperture Delay
Aperture Jitter
INTERNAL VOLTAGE REFERENCE
Output Voltage'
External 'Load
Unipolar Mode
Bipolar Mode
Power Supply Rejection
POWER SUPPLIES (Tm;n to T rna.)
Operating Voltages
Vee
VEE
Voo
Operating Current
Icc
lEE
100
Power Consumption
= +12 V ±5%, VEE = -12 V ±5%, Vaa = +5 V ±10% unless otherwise indicated)
Min
AD1679J
Typ
Max
Min
AD1679K
Typ
Max
14
±I
Bits
LSB
±IO
±IO
±12
±12
±IO
±IO
±12
±12
Bits
LSB
LSB
LSB
LSB
±8 (10)
±8 (10)
±16 (20)
±16 (20)
±8 (10)
±8 (10)
±16 (20)
±16 (20)
LSB
LSB
LSB
LSB
14
±I
14
14
+10
+5
0
-5
0
-5
+10
+5
10
10
10
10
I
20
5
1
20
5
ISO
4.95
150
5.05
4.95
+12
-12
+5
+12,6
-11.4
+5.5
18
25
8
560
20
32
12
720
+11.4
-12,6
+4.5
V
V
MO
pF
fLS
ns
ps
V
+1.5
+0.5
rnA
rnA
mVN
+12
-12
+5
+12,6
-11.4
+5,5
V
V
V
18
25
8
560
20
32
12
720
rnA
mA
rnA
mW
1
1
(ppmf'C)
(ppmf'C)
(ppmf'C)
(ppmf'C)
5.05
+1.5
+0.5
+11.4
-12.6
+4.5
Units
NOTES
I Adjustable to zero; see Figures II and 12,
2Includes internal voltage reference error.
'Includes internal voltage reference drift,
"With maximum external load applied,
Specifications shown in boldface are tested on all devices at fmal electrical test with worst case supply voltages at O·C, + 2S·C and + 70·C, Results from
those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested,
Specifications subject to change without notice,
ANALOG-TO-DIGITAL CONVERTERS 3-205
•
TIMING SPECIFICATIONS (AlIlIevice types 1ml• to 1ml., Vee = +12 V ±5%, VEE = -12 V ±5%, Voo = +5 V ±10%)
Parameter
Symbol
Min
SC Delay
Conversion Rate l
Convert Pulse Width
Aperture Delay
Conversion Time
Status Delay
Access Time2
Float Delay3
Update Delay
Format Setup
OE Delay
Read Pulse Width
Conversion Delay
EOCEN Delay
tsc
SO
Max
10
tcR
tcP
ISO
5
tAD
20
8.5
400
te
0
tSD
tSA
tpo
tUD
tps
toE
tRP
100
10
80
200
60
20
150
400
20
teo
tEO
Units
ns
!,-s
ns
ns
!,-s
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
IIncludes Acquisition Time.
_ _ __
'Measured from the failing edge of OElEOCEN (0.8 V) to the time at which the data IinesIEOC cross 2.0 V or 0.8 V.
See Figure 4; CoUT=IOO pF.
_ _ __
'Measured from the rising edge of OElEOCEN (2.0 V) to the time at which the output voltage changes by 0.5 V.
See Figure 4; CoUT= 10 pF.
Specifications subject to change without notice.
CS
EOCEN
EOC'
SHA
EOC'
TRACK
I
HOLD
I
TRACK
I
HOLD
-j;~~tso====';:":t
o I::::::;;-~..L--_
...
----'----=LJ~t-UD~...!.--:...----
CON~~~3~
DATA 0
REGISTER
X---:1-----V\J
DATA 1
~tEDr
---l
,r---
J
8t.o
I--t....
NOTE
'EOC IS A THREE·STATE OUTPUT IN SYNCHRO·
NOUS MODE AND AN OPEN DRAIN OUTPUT IN
ASYNCHRONOUS. ACCESS It....) AND FLOAT
(tFD) TIMING SPECIFICATIONS DO NOT APPLY
IN ASYNCHRONOUS MODE WHERE THEY ARE
A FUNCTION THE nME CONSTANT FORMED BY
THE 10 pF PULL·UP CAPACITOR, OUTPUT
CAPACITANCE AND THE PULL-UP RESISTOR.
. \..
NOTES
'IN ASYNCHRONOUS MODE. STATE OF CS OOES NOT AFFECT OPERATION. SEE
THE STAAT CONVERSION TRUTH TABLE FOR DETAILS.
'EOCEN
LOW. IN SYNCHRONOUS MODE, EOC IS A THREE-STATE OUTPUT. IN
ASYNCHRONOUS MOOE, EOC IS AN OPEN DRAIN OUTPUT. SEE CONVERSION
TRUTH TABLE.
'DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
=
Figure 3. EOC Timing
TEST
ACCESS TIME HIGH Z TO LOGIC LOW
FLOAT TIME LOGIC HIGH TO HIGH Z
ACCESS nME HIGH Z TO LOGIC HIGH
FLOAT nME LOGIC LOW TO HIGH Z
Vep CoUT
5 V 100 pF
5 V 10 pF
OV l00pF
oV
10 pF
Figure 1. Conversion Timing
V""
DB7-DBO _ _ _
~~~~~)_ _ _ _ _ _~L~O~W~B~YT~E)
Figure 2. Output Timing
3-206 ANALOG-TO-DIGITAL CONVERTERS
Figure 4. Load Circuit for Bus Timing Specifications
AD1679
-70
I
-n
-7'
-7.
-80
I
'SAMPLe = 100 KSPS
FULL SCALE = ±5 V
-
......
-76
/
-80
-82
-84
-88
-88
-go
THO...-
/ ./
/'
-85
Irl"
"/
-90
/'
!II
THO
-95
1
g
"
-100
/
~
1/
~-
/2NO HARMONIC
...
2ND HARMONIC
.... 3AD HARMONIC
/3RO HARMONIC
.....
-.00 o
-110
~
/'
-94
-os
./
./
./
.....
-82
-86
./
"/'
./
.,,-
/
-115
I
a
~
~
~
~
m
-120
~
~
~
~
o
a
~
H
INPUT FREQUENCY - kHz
•
100
1~
18
1.
~
,H
INPUT FREQUENCV - kHz
Figure 5. Harmonic Distortion vs. Input Frequency
(-0.5 dB Input)
Figure 6. Harmonic Distortion vs. Input Frequency
(-20 dB Input)
.00
go
80
-0.5
~B INP~T
-'0
-
-a
t--
-30
70
'11-40
-20 dB INPUT
~ -50
III"
"i:! -80
1
~ 50
~
z
:E
;;;~
-70
C-80
-go
30
-'00 L..t.
-60 dB INPUT
a
-110
-120
.0
o
-'30
o
a
~
..
80
~
m
~
~
~
w
~
a
~
a
30
H
~
go
~
FREQUENCY - kHz
INPUT FREQUENCY - kHz
Figure 7. S/N+D vs. Input Frequency and Amplitude
Figure B. 5-Plot Averaged 2048 Point FFT at 100 KSPS,
f,N = 10.009 kHz
go
-.
0
+5V
80
0
I-
-a
70
-30
18- 40
.! -50
~ =:
!
0
-
-0.5 dB INPUT
- -
-40 dB INPUT
-.00
-11
III ... ,.It.I.
~_lllll.u. .1,,1
o
-'3or
~
-.......
TI
I
~
~
a
30
H
1.akIJ.
1"--
-12 V
f"'-
- ... -... -.... -
~
~
0
0
go
FREQUENCV - kHz
Figure 9. Nonaveraged IMD Plot for f'N = 9.0B kHz (fa)'
9.58 kHz (fb ) at 100 KSPS
100
200
_
400
BOO
.....
f'.-
+5 V
-
...
a
. ~I II
I I'
IInlli I I
II I r
I
w
"
~
+.2Y:::
0
0
-80
-80
-'2
r- r--..
~2V-..L_
'j:~~
100
700
800
9DO
1000
RIPPLE FREQUENCY - kHz
Figure 10. Power Supply Rejection (f,N = 10 kHz,
fSAMPLE = 100 KSPS, VRIPPLE = 0.1 V p-p)
ANALOG-TO-DIGITAL CONVERTERS 3-207
II
CONVERSION. CONTROL
In synchronous mode (SYNC = HIGH), both Chip Select (CS)
and Start Convert (SC) must be brought LOW to start a conversion. CS should be LOW tsc before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing SC LOW, regardless of the state of CS.
Before a conversion is started, End Of Convert (EOC) is HIGH
and the sample-hold is in track mode. Mter a conversion is
started, the sample-hold goes into hold mode and EOC goes
LOW, signifying that a conversion is in progress. During the
conversion, the sample-hold will go back into track mode and
start acquiring the next sample.
In track mode, the sample-hold will settle to ±0.003% (14 bits)
in 1.5 IJ.S maximum. The acquisition time does not affect the
throughput rate as the AOl679 goes back into track mode more
than 2 IJ.S before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW.
When"the conversion is finished, EOC goes HIGH and the
result is loaded into the output register after a period of time
t UD ' Bringing OE LOW tOE after CS goes LOW makes the output register contents available on the output data bits
(OB7-0BO). A period of time teD is required after OE is
brought HIGH before the next SC instruction is issued. This
allows internal logic states to reset and guarantees minimum
apenure jitter for the next conversion.
If SC is held LOW, conversions will occur continuously. EOC
will go HIGH for approximately 1.5 IJ.S between conversions.
END OF CONVERT
In asynchronous mode, End Of Canven (EOC) is an open drain
output (requiring a minimum 3 kn pull-up resistor) enabled by
End Of Conven ENable (EOCEN). In synchronous mode, EOC
is a three-state output which is enabled by EOCEN and CS.
(See Conversion Status Truth Table.) Access (tBA) and float
(tFD) timing specifications do not apply in asynchronous mode
where they are a function of the time constant formed by the
external load capacitance and the pull-up resistor.
OUTPUT ENABLE OPERATION
The data bits (OB7-0BO) are three-state outputs that are
enabled by Chip Select (CS) and Output Enable (OE). CS
should be LOW toE before OE is brought LOW. Output
Enable (OE) must be toggled to update the output register.
The output is read as a 16-bit word, with High-Byte Enable
(HBE) controlling the output sequence. The high byte should
be read first, as doing so updates the value in the low byte register, which is read second. The 14-bit result is left-justified
within the 16-bit field.
In unipolar mode (BIPOFF tied to AGNO), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFOUT),
output coding is twos complement binary.
POWER-UP
A conversion sequence, consisting of one SC instruction, is
required after power-up to reset internal logic.
CONVERSION STATUS TRUTH TABLE
START CONVERSION TRUTH TABLE
INPUTS
INPUTS
SYNC
CS
I
Synchronous
Mode
Asynchronous
Mode
I
I
SC
I
X
0
t.
"'t
0
OUTPUT
SYNC CS EOCEN EOC
STATUS
STATUS
No Conversion
1
0
0
0
Convening
Start Conversion
1
0
0
1
Not Converting
1
1
X
HighZ
Either
1
X
1
HighZ
Either
0
X
0
0
Convening
0
X
0
HighZ
Not Converting
0
X
1
HighZ
Either
Start Conversion
(Not Recommended)
I
0
0
Continuous Conversion
0
X
I
No Conversion
0
X
t.
Start Conversion
0
X
0
Continuous Conversion
Synchronous
Mode
Asynchronous
Mode*
NOTES
I = HIGH voltage level.
o = LOW voltage level.
X = Don't care.
NOTES
I = HIGH voltage level.
o = LOW voltage level.
X = Don't care.
t.. = HIGH to LOW transition. Must stay low for t = lep.
*EOC requires a pull-up resistor in asynchronous mode.
OUTPUT ENABLE TRUTH TABLE
14-BIT MODE CODING FORMAT (1 LSB =0.61 mV)
Unipolar Coding
(Straight Binary)
Bipolar Coding
(Twos Complement)
VIN
Output Code
VIN
0
5.00000 V
000 ... 0
100 ... 0
9.99939 V
111 ... I
-5.00000
-0.00061
0
+2.50000
+4.99939
HBE
Output Code
V
V
V
V
100
111
000
010
011
...
.•.
...
...
...
0
1
0
0
I
Unipolar or
Bipolar
INPUTS
(CSUOE)
X
1
0
1
0
0
OUTPUTS
-I I I -I
DB7 ... DBO
High Z
~I ~
dien O
figOh
l J kcl m
NOTES
I
= HIGH voltage level.
a
=
= LOW voltage level.
n
= LSB.
X
U
= Don't care.
o
MSB.
= Logical OR.
Data coding is straight binary for Unipolar Mode and
25 complement binary for Bipolar Mode.
3-208 ANALOG-TO-DIGITAL CONVERTERS
AD1679
ABSOLUTE MAXIMUM RATINGS·
With
Respect
Specification
To
Min
-0.3
AGND
Vee
-IS
AGND
VEE
-0.3
Vee
VEE
V DD
DGND
0
AGND
-I
DGND
AIN, REFIN
AGND
-12
0
REFIN
VEE
REF'N
Vee
VEE
Digital Inputs
-0.5
DGND
Digital Outputs
-0.5
DGND
Max Junction
Temperature
Operating Temperature
0
Storage Temperature
-65
Lead Temperature
(10 sec max)
PIN CONFIGURATION
Max
Voo
Units
+IS
+0.3
+26.4
+7
+1
+12
V DD +0.3
V
V
V
V
V
V
V
V
V
V
175
+70
+150
°C
°C
°C
+300
°C
Vee
0
+7
EOC
087
0 ..
OBS
0. .
BIPOFF
•
08.
DGNDORVoo
DGNDOR VDD
DGNDORVoo
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ESDSENSITnnTY _________________________________________________________________
The AD 1679 features input protection circuitry conslstmg of large "distributed" diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,
low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-SS3C, the ADl679
has been classified as a Category A device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices' ESD Prevention Manual.
WARNING!
eJ
~~DEVICE
ORDERING GUIDE
Model
Package
ADl679JN
ADl679KN
ADl679JD
ADl679KD
2S-Pin Plastic DIP
2S-Pin Plastic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
SIN+D1
79 dB
SI dB
79 dB
81 dB
Temperature
Range
o to +70°C
o to +70°C
o to +70°C
o to +70°C
Digital Interface
Formar
2 Cycle
2 Cycle
2 Cycle
2 Cycle
Read
Read
Read
Read
(S+6 Bits)
(S + 6 Bits)
(8+6 Bits)
(8+6 Bits)
Package
Options'
N-2SA
N-2SA
D-28A
D-28A
NOTES
'Typical @ 10 kHz, -0.5 dB inpnt.
'For 14-bit parallel read interface to 16-bit buses, see AD1779.
'See Section 14 for package outline information.
ANALOG-TO-DIGITAL CONVERTERS 3-209
AD1679 PIN DESCRIPTION
Symbol
Pin No.
Type
Name and Function
AGND
7
P
Analog Ground. This is the ground return for AIN only.
AIN
6
Al
Analog Signal Input.
BIPOFF
10
Al
Bipolar Offset. Connect to AGND for + 10 V input unipolar mode and straight binary output
coding. Connect to REFoUT for ±5 V input bipolar mode and twos complement binary output
coding.
.
CS
4
D1
Chip Select. Active LOW.
DGND
12,14
P
Digital Ground.
DB7-DBO
26--19
DO
Data Bits. These pins provide all 14 bits in two bytes (8+6 bits). Active HIGH.
EOC
27
DO
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the conversion is fInished. In asynchronous mode, EOC is an open drain output and requires an external
3 k!l pull-up resistor. See EOCEN and SYNC pins for information on EOC gating.
D1
End-Of-Convert Enable. Enables EOC pin. Active LOW.
HBE
15
DI
High Byte Enable. If LOW, output contains high byte. If HIGH, output contains low byte
(corresponding to the most recendy read high byte).
OE
2
DI
Output Enable. A dow-n-goirtg transition on OE enables data bits. Gated with CS; Active
LOW.
Reference Input. +5 V input gives 10 V full-scale range.
EOCEN
REFIN
9
AI
REFoUT
8
AO
+5 V Reference Output. Tied to REFIN for normal operation.
SC
3
DI
Start Convert. Active LOW. See SYNC pin for gating.
SYNC
13
DI
SYNC Control. If tied to VDO (synchronous mode), SC and EOCEN are gated by CS. If tied
to DGND (asynchronous mode), SC and EOCEN are independent of CS, and EOC is an open
drain output. EOC requires an external 3k !l pull-up resistor in asynchronous mode.
V=
VEE
Voo
11
P
+ 12 V Analog Power.
5
P
-12 V Analog Power.
28
16--18
P
U
+5 V Digital Power.
These pins are unused and should be connected to DGND or V00'
Type: AI = Analog Input.
AO = Analog Output.
DI = Digital Input (TTL and 5 V CMOS compatible).
DO = Digital Output (TTL and 5 V CMOS compatible). All DO pins ate three-state drivers.
P = Power.
U = Unused.
3-210 ANALOG-TO-DIGITAL CONVERTERS
Definition of Specifications - AD1679
FREQUENCY DOMAIN TESTING
The ADI679 is tested dynamically using a sine wave input and a
2048 point Fast Fourier Transform (FFT) to analyze the resulting output. Coherent sampling is used, wherein the ADC sampling frequency and the analog input frequency are related to
each other by a ratio of integers. This ensures that an integral
number of input cycles is captured, allowing direct FFT processing without windowing or digital filtering which could mask
some of the dynamic characteristics of the device. In addition,
the frequencies are chosen to be "relatively prime" (no common
factors) to maximize the number of different ADC codes that
are present in a sample sequence. The result, called Prime
Coherent Sampling, is a highly accurate and repeatable measure
of the actual frequency domain response of the converter.
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the "Nyquist
Frequency" of a converter is that input frequency which is onehalf the sampling frequency of the converter.
SIGNAL-TO-NOISE AND DISTORTION (SIN+D) RATIO
SIN + D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of a full-scale input signal and is
expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
components are used.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a fullscale input signal.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa
and fb, any device with nonlinearities will create distortion
products, of order (m + n), at sum and difference frequencies
of mfa ± nfb, where m, n = 0, 1, 2, 3 . . . Intermodulation
terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa - fb) and the
third order terms are (2 fa + fb), (2 fa - fb), (fa + 2 fb) and
(fa - 2 fb). The IMD products are expressed as the decibel
ratio of the rms sum of the measured input signals to the rms
sum of the distortion terms. The two signals applied to the converter are of equal amplitude and the peak value of their sum is
-0.5 dB from full scale (9.44 V p-p). The IMD products are
normalized to a 0 dB input signal.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The ADI679 has been designed to optimize input bandwidth,
allowing it to undersample input signal frequencies significantly
above the converter's Nyquist frequency. If the input signal is
suitably band-limited, the spectral content of the input signal
can be recovered.
APERTURE DELAY
Aperture delay is a measure of the SHA's performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion. In synchronous mode,
Chip Select (CS) should be LOW before SC to minimize aperture delay.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the AID.
INPUT SETTLING TIME
Settling time is a function of the SHA's ability to track fast
slewing signals. This is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
DIFFERENTIAL NONLINEARITY (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the deviation from this ideal value. It is often
specified in terms of resolution for which no missing codes are
guaranteed.
For the ADI679, this specification is 14 bits from T min to
T max' which guarantees that all 16,384 codes are present over
temperature.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level
112 LSB above analog ground. Unipolar zero error is the deviation of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
BIPOLAR ZERO ERROR
In the bipolar mode, the major carry transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value 112
LSB below analog ground. Bipolar zero error is the deviation of
the actual transition from that point. This error can be adjusted
as discussed in the Input Connections and Calibration section.
GAIN ERROR
The full-scale transition should occur at an analog value
I 112 LSB below the nominal full scale (9.9991 volts for a
0-10 V range, 4.9991 volts for a ±5 V range). The gain error is
the deviation of the actual level at the last transition from the
ideal level with the zero error trimmed out. This error can be
adjusted as shown in the Input Connections and Calibration
section.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than -0.1 dB. Beyond this frequency, distortion of the sampled input signal increases significantly.
ANALOG-TO-DIGITAL CONVERTERS 3-211
II
Application Information
INPUT CONNECTIONS AND CALmRATION
The high (10 MO) input impedance of the ADl679 eases the
task of interfacing to high source impedances or multiplexer
channel-to-channel mismatches of up to 300 O. The 10 V POp
full scale input range accepts the majority of signal voltageS
without the need for voltage divider networks which could
deteriorate the accuracy of the ADC.
In some applications, offset and gain errors need to be more
precisely trimmed. The following sections describe the correct
procedure for these various situations.
BIPOLAR RANGE INPUTS
The connections for the bipolar mode are shown in Figure 11.
In this mode, data output coding will be twos complement
binary. This circuit will allow approximately ±2S mV of offset
trim range (±40 LSB) and ±0.5% of gain trim range (±80
LSB).
Either or both of the trim pots can be replaced with SO n ± 1%
fIXed resistors if the specified AD1679 accuracy limits are sufficient for the application. If the pins are shotted together, the
additional offset and gain errors will be approximately 80 LSB.
To trim bipolar zero to its nominal value, apply a signal 112 LSB
below midrange (-0.305 mV for a ±5 V range) and adjust Rl
until the major carry transition is located (11 1111 1111 1111 to
00 0000 0000 0000). To trim the gain, apply a signal 1 1/2 LSB
below full scale (+4.9997 V for a ±S V range) and adjust R2 to
give the last positive transition (01 1111 1111 III 0 to 01 1111
1111 1111). These trims are interactive so several iterations may
be necessary for convergence.
A single pass calibration can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale), using the same circuit. First, apply a signal
1/2 LSB above minus full scale (-4.9997 V for a ±S V range)
and adjust R 1 until the minus full scale transition is located
(100000 0000 0000 to 10000 000 0001). Then perfonn the gain
error trim as outlined above.
:1::1 V INPUT
~
Figure 11. Bipolar Input Connections with Gain and
Offset Trims
UNIPOLAR RANGE INPUTS
Offset and gain errors can be trimmed out by using the configuration shown in Figure 12. This circuit allows approximately
±2S mV of offset trim range (±40 LSB) and ±O.S% of gain
trim range (±80 LSB).
The nominal offset is 112 LSB so that the analog range that corresponds to each code will be centered in the middle of that
code (halfway between the transitions to the codes above and
below it). Thus the first transition (from 00 0000 0000 0000 to
00 0000 0000 0001) should nominally occur for an input level of
~212
ANALOG-TO-DIGITAL CONVERTERS
+112 LSB (0.305 mVabove ground for a 10 V range). To trim
unipolar zero to this nominal value, apply a 0.305 mV signal to
AIN and adjust Rl until the first transition is located.
The gain trim is done by adjusting R2. If the nominal value is
required, apply signal 1 112 LSB below full scale (9.9997 V for
a 10 V range) and adjust R2 until the last transition is located
(11 1111 1111 1110 to 11 1111 1111 1111).
a
If offset adjustment is not required, BIPOFF should be connected directly to AGND. If gain adjustment is not required,
R2 should be replaced with a fIXed 50 0 ± 1% metal film resistor. If REFotlT is connected directly to REF1N, the additional
gain error will be approximately 1%.
OT010 VINPUT
~
ADI871
Figure 12. Unipolar Input Connections with Gain and
Offset Trims
REFERENCE DECOUPLING
It is recommended that a 10 ....F tantalum capacitor be
connected between REFIN (Pin 9) and ground. This has the
effect of improving the SIN +D ratio through fIltering possible
broad-band noise contributions from the voltage reference.
BOARD LAYOUT
Designing with higlI resolution data conveners requires careful
attention to board layout. Trace impedance is the first issue. A
1.22 mA current through a 0.50 trace will develop a voltage
drop of 0.6 mY, which is I LSB at the 14-bit level for a 10 V
full scale span. In addition to ground drops, inductive and
capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to
fIlter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at riglIt angles.
The AD1679 incorporates several features to help the user's layout. Analog pins (VEE' AIN, AGND, REFotlT • REF1N •
BIPOFF, VcC> are adjacent to help isolate analog from digital
signals. In addition, the 10 MO input impedance of AIN minimizes input trace impedance errors. Finally, ground currents
have been minimized by careful circuit architecture. Current
througlI AGND is 200 ....A, with no code dependent variation.
The current througlI DGND is dominated by the return current
for DB7-DBO and EOC.
AD1679
SUPPLY DECOUPLING
The ADl679 power supplies should be well fIltered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. A 10 I1F tantalum capacitor in parallel with a 0.1 I1F ceramic capacitor provides adequate decoupling .
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD1679, associated analog input circuitry and interconnections as far as possible from logic circuitry. A solid analog
ground plane around the ADl679 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit construction is preferred.
GROUNDING
If a single AD1679 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD1679. If multiple AD1679s are used or the AD1679 shares
analog supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This single interconnection of grounds prevents large
ground loops and consequently prevents digital currents from
flowing through the analog ground.
INTERFACING THE AD1679 TO MICROPROCESSORS
The 110 capabilities of the AD1679 allow direct interfacing to
general purpose and DSP microprocessor buses. The asynchronous conversion option allows complete flexibility and control
with minimal external hardware.
AD1679 TO 80186
Figure 14 shows the ADl679 interfaced to the 80186 microprocessor. This interface allows the 80186's built-in DMA controller to transfer the ADl679 output into a RAM based FIFO
buffer of any length, with no microprocessor intervention.
The following examples illustrate typical AD1679 interface
configurations.
In this application the AD 1679 is configured in the asynchronous mode, which allows conversions to be initiated by an external trigger source independent of the microprocessor clock.
After each conversion, the ADl679 EOC signal generates a
DMA request to Channel I (DRQl). The subsequent DMA
READ sequences the high and low byte ADI679 data and resets
the interrupt latch. The system designer must assign a sufficient
priority to the DMA channel to ensure that the DMA request
will be serviced before the completion of the next conversion.
This configuration can be used with 6 MHz and 8 MHz 80186
processors.
AD1679 TO TMS320C25
In Figure 13 the AD1679 is mapped into the TMS32OC25 110
space. AD1679 conversions are initiated by issuing an OUT
instruction to Port 1. EOC status and the conversion result are
read in with an IN instruction to Port 1. A single wait state is
inserted by generating the processor READY input from IS,
Port 1 and MSC. Address line AO provides HBE decoding to
select between the high and low bytes of data. This configuration supports processor clock speeds of 20 MHz and is capable
of supporting processor clock speeds of 40 MHz if a NOP
instruction follows each AD 1679 read instruction.
A31---------.l
+5 V
:,~====:::l
STRB
is
GlA
+5 V
SYNC
74F138
f - - - - - - I G2.
Gl
AD1679
PORT
Vo ONE
TMS32OC25
READY
Mse
A.~--------------~
o.~--------------~
D~D7~
______________
EXTERNAL TRIGGER - - - - - - - - '
~O~D7
Figure 14. AD1679 to 80186 DMA Interface
Figure 13. AD1679 to TMS320C25 Interface
ANALOG-TO-DIGITAL CONVERTERS 3-213
•
AD1679 TOZ80
The AD 1679 can be interfaced to the Z80 processor in an 110 or
memory mapped configuration. Figure 15 illustrates an 110 configuration, where the AD1679 occupies several port addresses to
allow separate polling of the EOC status and reading of the data.
The lower address bit, AO, is used to select the high and low
order bytes of the result.
A useful feature of the Z80 is that a single wait state is automatically inserted during 110 operations, allowing the AD1679 to be
used with Z80 processors having clock speeds up to 8 MHz.
D7_DOlr-_ _ _ _..:D~A..:TA..:.:.:U.:.S_ _ _p__,..jD7-DO
.kn
AD1679 TO ANALOG DEVICES ADSP·2100A
Figure 16 demonstrates the AD 1679 interfaced to an
ADSP-2100A. With a clock frequency of 12.5 MHz, and
instruction execution in one 80 ns cycle, the digital signal processor will support the AD1679 data memory interface with two
hardware wait states.
The converter is configured to run asynchronously using a sampling clock. The EOC output of the AD1679 is asserted at the
end of each conversion and creates a high priority interrupt to
the processor through IRQ3. Upon interrupt, the ADSP-2100A
immediately executes a data memory write instruction which
asserts HBE. In the following cycle, the processor starts a data
memory read (high byte read) by providing an address on the
DMA bus. The decoded address generates OE for the converter.
OE, together with logic and latches, is used to force the ADSP2100A into a two-cycle wait state by generating DMACK. The
read operation is thus started and completed within three processor cycles (240 ns). HBE is released during "high byte read."
This allows the processor to read the lower byte of data as soon
as "high byte read" is complete. Low byte read is executed in a
similar manner and is completed during the next 240 ns.
DMAI-""";=;;;'_
SAMPUNG
ClOCK
+5 V~'Nw_>--_iEOC
Figure 15. AD1679 to Z80 Interface
Cii
SYNC
EOCEN
AD1679
DMWRr------------~
1RQ31---------ocC
1-----_'""'
DMD1~81--_ _ _ _ _..:D:.:A..:~..:.=U.:.S_ _ _ _ _ _~
Figure 16. AD1679 to ADSP-2100A Interface
3-214 ANALOG-TO-DIGITAL CONVERTERS
~ANALOG
WDEVICES
FEATURES
AC Characterized and Specified
100k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
80 dB S/N+D (K Grade)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 MO Input Impedance
16-Bit Bus Interface (See AD1679 for 8-Bit Interface)
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
PRODUCT DESCRIPTION
The ADl779 is a complete, 14-bit monolithic analog-to-digital
converter consisting of a sample-hold amplifier (SHA), a microprocessor compatible bus interface, a voltage reference and clock
generation circuitry.
The 14 data bits are accessed by a 16-bit bus in a single read
operation. Data format is straight binary for unipolar mode and
twos complement binary for bipolar mode. The input has a fullscale range of 10 V with a full power bandwidth of 1 MHz and
a full linear bandwidth of 500 kHz. High input impedance
(10 M!l) allows direct connection to unbuffered sources without
signal degradation.
This product is fabricated on Analog Devices' BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-fllm resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm, which includes error correction and flash converter
circuitry to achieve high speed and resolution.
The ADl779 operates from +5 V and ±12 V supplies and dissipates 720 mW. A 28-pin plastic DIP and a 0.6" wide ceramic
DIP are available. Contact factory for surface-mount package
options.
14-Bit 100 KSPS
Complete Sampling ADC
AD1779 I
AD1779 FUNCTIONAL BLOCK DIAGRAM
II
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The ADl779 minimizes
external component requirements by combining a high speed
sample-hold amplifier (SHA), ADC, 5 V reference, clock and
digital interface on a single chip. This provides a fully specified sampling AJD function unattainable with discrete
designs.
2. PERFORMANCE: The ADl779 provides a throughput of
lOOk conversions per second. SIN +D is 80 dB (K grade) at
10 kHz and remains flat beyond the Nyquist frequency.
3. SPECIFICATIONS: The ADl779 is specified for ac (or
"dynamic") parameters such as SIN + D ratio, THD and
IMD. These parameters are important in signal processing
applications as they indicate the AD 1779's effect on the spectral content of the input signal.
4. EASE OF USE: The pinout is designed for easy board
layout, and the single read output provides compatibility
with 16-bit buses. Factory trimming eliminates the need for
calibration modes or external trimming to achieve rated
performance.
5. RELIABILITY: The ADl779 utilizes Analog Devices'
monolithic BiMOS technology. This ensures long term reliability compared to multichip and hybrid designs.
ANALOG-TO-DIGITAL CONVERTERS 3-215
SPECIFICATIONS
AC SPECIFICATIONS
.
(Tmin to Tmax' Vee=+12 V :t5%, VEE =-12 V :t5%, VDD=+ 5 V :tl0%, fSAMP\.E=100 KSPS,
fiN = 10.009 kHz unless otherwise noted)'
Parameter
Min
SIGNAL-TO-NOISE AND DISTORTION (SIN + D) RATIO'
-0.5 dB Input (Referred to -0 dB Input)
-20 dB Input (Referred to -20 dB Input)
-60 dB Input (Referred to -60 dB Input)
78
58
18
TOTAL HARMONIC DISTORTION (THD)3
@ +25 C
Q
T min to Tmax
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
FULLPOWERBAND~DTH
FULL LINEAR
ADI779J
Typ
Max
79
59
19
Min
80
60
20
dB
dB
dB
-90
-84
-90
-84
0.006
0.006
%
-82
dB
0.008
0.003
-88
0.004
0.008
%
-90
-84
-90
-84
dB
-82
1
500
INTERMODULATION DISTORTION (IMD)4
2nd Order Products
3rd Order Products
81
61
21
Units
0.003
-88
0.004
1
BAND~DTH
AD1779K
Typ
Max
dB
MHz,.-
500
kHz
-90
-84
-90
-90
-84
-90
-84
-84
dB
dB
NOTES
IfIN amplitude = -0.5 dB (9.44 V p-p) bipolar mode full-scale unless otberwise indicated. All measurements referred to a -0 dB
(9.997 V p-p) input signal unless otberwise noted.
'See Figure 7 for higher frequencies and other input amplirudes.
'See Figures 5 and 6 for otber conditions.
"fA =9.08 kHz, f B =9.58 kHz, witb fSAMPLE= 100 KSPS. See Figure 9 and Definition of Specifications section.
Specifications subject to change witbout notice.
DIGITAL SPECIFICATIONS
(All device types Tmln to Tmax, Vee = +12 V:t5%, VEE = -12 V:t5%, VDD = +5 V:tl0%)
Parameter
LOGIC INPUTS
High Level Input Voltage
VIH
VIL
Low Level Input Voltage
High Level Input Current
IIH
Low Level Input Current
IlL
Input Capacitance
CIN
LOGIC OUTPUTS
High Level Output Voltage
VOH
VOL
Ioz
Co.
Low Level Output Voltage
High Z Leakage Current
High Z Output Capacitance
Test Conditions
Min
Max
2.4
0.8
10
10
10
VIN=S V
VIN=O V
I oH =O.1 rnA
I OH =O.5 rnA
I OL =1.6 rnA
VIN=O or 5 V
4.0
2.4
0.4
10
10
Units
V
V
fJ.A
~
pF
V
V
V
~
pF
NOTES
Specifications shown in boldface are tested on all devices at final electrical test witb worst case supply voltages at O'C, + 250C and + 70OC. Results from
tbose tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, a1tbough only those shown in boldface are tested.
Specifications subject to change witbout notice.
3-216 ANALOG-TO-DIGITAL CONVERTERS
AD1779
DC SPECIFICATIONS
(@ +25°C, Ycc =+12 Y ±5%, YEE =-12 Y ±5%, Yoo =+5 Y ±10% unless otherwise indicated)
Parameter
ACCURACY
Resolution
Integra! Linearity Error
Differential Linearity
T mio to Tmax (No Missing Codes)
Unipolar Zero Error)
Bipolar Zero Error)
Unipolar Gain Error),2
Bipolar Gain Error),2
Temperature Drift (Coefficients?
Unipolar Zero
Bipolar Zero
Unipolar Gain
Bipolar Gain
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
Input Resistance
Input Capacitance
Input Settling Time
Aperture Delay
Aperture Jitter
INTERNAL VOLTAGE REFERENCE
Output Voltage4
External Load
Unipolar Mode
Bipolar Mode
Power Supply Rejection
POWER SUPPLIES (Tmin to T max)
Operating Voltages
Vcc
VEE
Voo
Operating Current
Icc
lEE
100
Power Consumption
Min
ADI779J
Typ
AD1779K
Max
14
Min
Typ
14
Units
±l
Bits
LSB
±10
±10
±12
±12
±10
±1O
±12
±12
Bits
LSB
LSB
LSB
LSB
±8 (10)
±8 (10)
±16 (20)
±16 (20)
±8 (10)
±8 (10)
±16 (20)
±16 (20)
LSB
LSB
LSB
LSB
±l
14
14
0
-5
+10
+5
0
-5
+10
+5
10
10
10
10
1
20
,5
1
20
5
150
4.95
150
5.05
4.95
1
+12.6
-11.4
+5.5
18
25
8
560
20
32
12
720
+11.4
-12.6
+4.5
V
V
MO
pF
jLS
ns
ps
V
+1.5
+0.5
rnA
rnA
mVN
+12
-12
+5
+12.6
-11.4
+5.5
V
V
V
18
25
8
560
20
32
12
720
rnA
rnA
rnA
mW
1
+12
-12
+5
(ppmfC)
(ppmfC)
(ppmfC)
(ppmfC)
5.05
+1.5
+0.5
+11.4
-12.6
+4.5
Max
NOTES
I Adjustable to 2ero; see Figures 11 and 12.
'Includes internal voltage reference error.
'Includes internal voltage reference drift.
'Witb maximum external load applied.
Specifications shown in boldface are tested on all devices at final electrical test witb worst case supply voltages at O'C, + 2S·C and + 70'C. Results from
tbose tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, altbough only tbose shown in boldface are tested.
Specifications subject to cbange witbout notice.
ANALOG-TO-DIGITAL CONVERTERS 3-217
TIMING SPECIFICATIONS (All device types T
onin
Parameter
Symbol
Conversion Rate'
Convert Pulse Width
Aperture Delay
Conversion Time
Status Delay
Access Time2
Float Delay'
Update Delay
OE Delay
Read Pulse Width
Conversion Delay
tcR
Min
ISO
5
tep
tAD
te
tSD
tBA
tFO
tUD
to TIAII, Vee
Max
10
Units
20
ns
p.s
0
400
ns
100
10
80
ns
ns
ns
200
tRP
teD
p.s
ns
8.5
20
ISO
400
toE
=+12 V ±5%, VEE =-12 V ±5%, VDD =+5 V ±10%)
ns
ns
ns
NOTES
'Includes Acquisition Time.
_ __
2Measured from the falling edge of OElEOCEN (0.8 V) to the time at which the data Iines/EOC cross 2.0 V or 0.8 V.
See Figure 4; GoUT = 100 pF. _ __
'Measured from the rising edge of OElEOCEN (2.0 V) to the time at which the output voltage changes by 0.5 V.
See Figure 4; toUT = 10 pF.
Specifications subject to change without notice.
T_RA_C~K-.+I__~H~O~~~__~__~TRA~C~K__-r~IL-~H=O~LD~
SHA ___
t •• ~
I--
~ts.~
EOC'
tel
Figure 3. EOC Timing
~\--I----J/~tuo~
CONri~~8~----------D-A-TA~O~----~--~)(r----~DA-T-A-l------REGISTER - - - - - - - - - - - - - - - - - - - - - - - - '
~'
;.-1_ _ _ _ _ _ _ __
'---1
NOTES
'EOCEN = LOW.
'DATA SHOU~ NOT BE ENABLED DURING A CONVERSION.
TEST
ACCESS nME HIGH Z TO LOGIC LOW
FLOAT nME lOGIC HIGH TO HIGH Z
ACCESS TIME HIGH Z TO lOGIC HIGH
FLOAT TIME LOGIC LOW TO HIGH Z
V...
5 V
5 V
0 V
0 V
COUT
100 pF
10 pF
100 pF
10 pF
Figure 1. Conversion Timing
Figure 4. Load Circuit for Bus Timing Specifications
Figure 2. Output Timing
3-218 ANALOG-TO-DIGITAL CONVERTERS
AD1779
-7.
-72
r--
-7'
-7.
-78
'IJ
-80
, -82
w
-54
::>
~ -86
Q
THD_
./
:;-88
" -go i-""'"
-92
..
-
/
.....
-85
~
"/
-go
t,
~
/
~-,
13.RD HARMONIC
H
~
00
,..... 2ND HARMONIC
.
":3RD HARMONic
-110
/
I
THD
-95
g-100
/2NO HARMONIC
-98
-'00 •
.;<'
.//'
/ ' ../
/'
./ / '
"/
/
L
-94
-80
./
'SA_. . = 100 KSPS
FULL SCALE"" :5 V
-115
J
00
~
~
~
INPUT FREQUENCY - kHz
~
~
-120
~
Figure 5. Harmonic Distortion vs. Input Frequency
(-0.5 dB Input)
•
H
40
00
80
~
~
~
INPUT FREQUENCY - kHz
~
~
~
Figure 6. Harmonic Distortion vs. Input Frequency
(-20 dB Input)
'00
••
-,.
~~BINlT- -
00
-H
-3.
70
~ -40
,
-20 dB INPUT
w -50
!II
, 00
~
5.
-00
::E -70
iil~
C -80
Q
+
z
30
..
-'00 LI.
-60 dB INPUT
-110
2.
,.
I'"
-120
-130
•
•
H
~
00
00
~
~
~
~
~
w
~
~
H
~
H
go
~
~
Figure 7. SIN+D vs. Input Frequency and Amplitude
Figure 8. 5-Plot Averaged 2048 Point FFT at 100 KSPS,
fIN = 10.009 kHz
go
.
-,.
--.. r-. r-
-H
.
~
..
70
-3.
.. -40
f- -
I -50
~
,.L
-0.5 dB INPUT
- -
-60
-70
.
~ -80
-
-'00
d..u.. .~"I
-110
-,H
"1'1
-'30
w
oJ.~.
d
IIn," ,
,.
1
H
~
30
FREQUENCY - kHz
$
1.olI.1..
'-,
,
'I'
~
go
FREQUENCY - kHz
INPUT FREQUENCY - kHz
~
~
H
II
I'
go
Figure 9. Nonaveraged IMD Plot for fIN = 9.08 kHz (f.J,
9.58 kHz (fb ) at 100 KSPS
,.
+12V::::
............
r---...
-12 V
i'-
-40 dB INPUT
- ... -... -.... - ..
30
o
100
200
vi'-
+5V
......
+5
~2V-~_
'r......
300
400
500 800
700
RIPPLE FREQUENCY - kHz
~
800
100
1000
Figure 10. Power Supply Rejection (f,N = 10 kHz,
fSAMPLE = 100 KSPS, VRIPPLE = 0.1 V p-p)
ANALOG-TO-DIGITAL CONVERTERS 3-219
II
CONVERSION CONTROL
Before a conversion is started, End Of Convert (EOC) is HIGH
and the sample-hold is in track mode. A conversion is started by
bringing SC LOW, regardless of the state of CS.
END-OF-CONVERT
End-of-Convert (EOC) is a three-state output which is enabled
by End-of-Convert ENable EOCEN.
OUTPUT ENABLE OPERATION
The data bits (DB13-DBO) are three-state outputs that are
enabled by Chip Select (CS) and Output Enable (OE). CS
should be LOW tOE before OE is brought LOW. OE must be
toggled to update the output register. The output is read in a
single cycle as a 14-bit word.
After a conversion is started, the sample-hold goes into hold
mode and EOC goes LOW, signifying that a conversion is in
progress. During the conversion, the sample-hold will go back
into track mode and start acquiring the next sample.
In track mode, the sample-hold will settle to ±0.003% (14 bits)
in I.S ILS maximum. The acquisition time does not affect the
throughput rate as the ADI779 goes back into track mode more
than 2 ILS before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW if
the maximum throughput rate is needed.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFOUT),
output coding is twos complement binary.
POWER-UP
A conversion sequence, consisting of one SC instruction, is
required after power-up to reset internal logic.
When the conversion is finished, EOC goes HIGH and the
result'is loaded into the output register after a period of time
tUD ' Bringing OE LOW makes the output register contents
available on the output data bits (DB13-DBO). A period of time
Lcn is required after OE is brought HIGH before the next SC
instruction is issued. This is to allow internal logic states to
reset and guarantees minimum aperture jitter for the next
conversion.
14-BIT MODE CODING FORMAT (I LSB =0.61 mY)
lB'ipo'Cir ""Quing
unlpUlar ....,Oulfig
(Twos Complement)
(Straight Binary)
If SC is held LOW, conversions will occur continuously. EOC
will go HIGH for approximately I.S ILS between conversions.
VIN
Output Code
VIN
Output Code
0
S.OOOOO V
9.99939 V
000 ... 0
100 ... 0
III ... I
-S.OOOOO V
-0.00061 V
0
+2.S0000 V
+4.99939 V
100
III
000
010
011
CONVERSION TRUTH TABLE
OUTPUTS
INPUTS
Mode
Start Conversion
-
-
I
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
"l.
0
Conversion Status
Data Access
-
SC EOCEN CS OE
I
X
I
I
X
0
0
EOC
No Conversion
Start Conversion
Continuous Conversion
Converting
Not Converting
Either
0
I
HighZ
NOTES
U = Logical OR.
I = HIGH voltage level.
o = LOW voltage level.
X = Don't care.
"l. = HIGH to LOW transition. Must stay LOW for t = IeP.
3-220 ANALOG-TO-DIGITAL CONVERTERS
DB13 . . . DBO Status
HighZ
HighZ
MSB ... LSB
Three-State
Three-State
Data Out
...
...
...
...
...
0
I
0
0
I
AD1779
ABSOLUTE MAXIMUM RATINGS·
With
Respect
To
Min
Specification
AGND
AGND
Vee
VEE
Vee
V DD
VEE
AGND
AIN, REFIN
REFIN
REFIN
Digital Inputs
Digital Outputs
Max Junction
Temperature
Operating Temperature
Storage Temperature
Lead Temperature
(10 sec max)
DGND
DGND
AGND
VEE
Vee
-0.3
-18
-0.3
0
-1
-12
0
VEE
DGND
DGND
-0.5
-0.5
PIN CONFIGURATION
Max
Units
+18
+0.3
+26.4
+7
+1
+12
V DD +0.3
V
V
V
V
V
V
V
V
V
V
175
+70
+150
°C
°C
°C
+300
°C
Vee
0
+7
0813
0812
DB"
0810
DB.
D. .
DB7
DB.
DB.
DB4
BIPOFF
D83
0
-65
cs
DB2
roCEN
DB1
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
ESD SENSITIVITY
The AD 1779 features input protection circuitry conslstmg of large "distributed" diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,
low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the ADI779
has been classified as a Category A device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foan! or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices' ESD Prevention Manual.
Model
Package
AD1779JN
AD1779KN
AD1779JD
AD1779KD
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
ORDERING GUIDE
Temperature
SIN+D1
Range
79 dB
81 dB
79 dB
81 dB
o to
o to
o to
o to
+70°C
+70°C
+70°C
+70°C
WARNING!
~~OEVICE
Digital Interface
Format'
1 Cycle Read
1 Cycle Read
1 Cycle Read
1 Cycle Read
0
(14 Bits)
(14 Bits)
(14 Bits)
(14 Bits)
Package
Options'
N-28A
N-28A
D-28A
D-28A
NOTES
'Typical @ 10 kHz, -0.5 dB input.
'For 2 cycle read (8+6 bits) interface to 8·bit buses, see AD1679.
'See Section 14 for package outline infonnation.
ANALOG-TO-DIGITAL CONVERTERS 3-221
AD1779 PIN DESCRIPTION
and Function
Symbol
Pin No.
Type
Name
AGND
7
P
Analog Ground. This is the ground return for AIN only.
AlN
6
Al
Analog Signal Input.
BIPOFF
10
Al
Bipolar Offset. Connect to AGND for + 10 V input unipolar mode and straight binary output
coding. Connect to REFoUT for ±5 V input bipolar mode and twos complement binary output
coding.
CS
12
Dl
Chip Select. Active LOW.
DGND
14
P
Digital Ground.
DB 13-DBO
28-15
DO
Data Bits. These pins provide all 14 bits in one 14 bit parallel output. Active HIGH.
EOC
2
DO
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the
conversion is fInished. EOC is a three-state output. See EOCEN pin for information on EOC
gating.
EOCEN
13
DI
End-of-Convert Enable. Enables EOC pin. Active LOW.
OE
3
DI
Output Enable. A down-going transition on OE enables data bits. Active LOW.
Reference Input. +5 V input gives 10 V full scale range.
REFIN
9
AI
REFoUT
8
~A..O
SC
4
DI
Vee
11
P
+12 V Analog Power.
VEE
5
P
-12 V Analog Power.
P
+5 V Digital Power.
Voo
t· 5
V Reference Output. Tied to REFIN for normal operation.
Start Convert. Active LOW.
Type: AI = Analog Input.
AO = Analog OutpUt.
Dr = Digital Input (TIL and 5 V CMOS compatible).
DO = Digital Output (TTL and 5 V CMOS compatible). All DO pins are tri-stste drivers.
P = Power.
3-222 ANALOG-TO-DIGITAL CONVERTERS
Definition of Specifications - AD1779
FREQUENCY DOMAIN TESTING
The ADI779 is tested dynamically using a sine wave input and a
2048 point Fast Fourier Transform (FFT) to analyze the resulting output. Coherent sampling is used, wherein the ADC sampling frequency and the analog input frequency are related to
each other by a ratio of integers. This ensures that an integral
number of input cycles is captured, allowing direct FFT processing without windowing or digital flltering which could mask
some of the dynamic characteristics of the device. In addition,
the frequencies are chosen to be "relatively prime" (no common
factors) to maximize the number of different ADC codes that
are present in a sample sequence. The result, called Prime
Coherent Sampling, is a highly accurate and repeatable measure
of the actual frequency domain response of the converter.
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the "Nyquist
Frequency" of a converter is that input frequency which is onehalf the sampling frequency of the converter.
SIGNAL-TO·NOISE AND DISTORTION (SIN+D) RATIO
SIN + D is the ratio of the rms value of a full-scale input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of a full-scale input signal and is
expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
components are used.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a fullscale input signal.
INTERMODULATION DISTORTION (IMO)
With inputs consisting of sine waves at two frequencies, fa
and fb, any device with nonlinearities will create distortion
products, of order (m + n), at sum and difference frequencies
of mfa ± nfb, where m, n = 0, 1, 2, 3 . . . Intermodulation
terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa - fb) and the
third order terms are (2 fa + fb), (2 fa - fb), (fa + 2 fb) and
(fa - 2 fb). The IMD products are expressed as the decibel
ratio of the rms sum of the measured input signals to the rms
sum of the distortion terms. The two signals applied to the converter are of equal amplitude and the peak value of their sum is
-0.5 dB from full scale (9.44 V pop). The IMD products are
normalized to a -0 dB input signal.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is rc;duced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than -0.1 dB. Beyond this frequency, distortion of the sampled input signal increases significantly.
The ADI779 has been designed to optimize input bandwidth,
allowing it to undersample input signal frequencies significantly
above the converter's Nyquist frequency. If the input signal is
suitably band-limited, the spectral content of the input signal
can be recovered.
APERTURE DELAY
Aperture delay is a measure of the SHA's performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion. In synchronous mode,
Chip Select (CS) should be LOW before SC to minimize aperture delay.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the AID.
INPUT SETTLING TIME
Settling time is a function of the SHA's ability to track fast
slewing signals. This is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
DIFFERENTIAL NONLINEARITY (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the deviation from this ideal value. It is often
specified in terms of resolution for which no missing codes are
guaranteed.
For the ADI779, this specification is 14 bits from Tmin to
T max' which guarantees that all 16,384 codes are present over
temperature.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level
112 LSB above analog ground. Unipolar zero error is the deviation of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
BIPOLAR ZERO ERROR
In the bipolar mode, the major carty transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value 1/2
LSB below analog ground. Bipolar zero error is the deviation of
the actual transition from that point. this error can be adjusted
as discussed in the Input Connections and Calibration section.
GAIN ERROR
The full-scale transition should occur at an analog value 1 1/2
LSB below the nominal full scale (9.9991 volts for a 0-10 V
range, 4.9991 volts for a ±S V range). The gain error is the
deviation of the actual level at the last transition from the ideal
level with the zero error trimmed out. This error can be adjusted as shown in the Input Connections and Calibration section.
ANALOG-TO-DIGITAL CONVERTERS 3-223
•
Application Information
INPUT CONNECTIONS AND CALIBRATION
The high (10 MO) input impedance of the ADI779 eases the
task of interfacing to high source impedances or multiplexer
channel-to-channel mismatches of up to 300 O. The 10 V p-p
full scale input range accepts the majority of signal voltages
without the need for voltage divider networks which could
deteriorate the accuracy of the ADC.
In some applications, offset and gain errors need to be more
precisely trimmed. The following sections describe the correct
procedure for these various situations.
BIPOLAR RANGE INPUTS
The connections for the bipolar mode are shown in Figure II.
In this mode, data output coding will be twos complement
binary. This circuit will allow approximately ±25 mV of offset
trim range (±40 LSB) and ±0.5% of gain trim range (±80
LSB).
+ 112 LSB (0.305 mV above ground for a 10 V range). To trim
unipolar zero to this nominal value, apply a 0.305 mV signal to
AIN and adjust Rl until the first transition is located.
The gain trim is done by adjusting R2. If the nominal value is
required, apply a signal I 112 LSD below full scale (9.9997 V for
a 10 V range) and adjust R2 until the last transition is located
(11 1111 1111 1110 to 11 1111 1111 1111).
If offset adjustment is not required, BIPOFF should be connected directly to AGND. If gain adjustment is not required,
R2 should be replaced with a fixed so 0 ± 1% metal film resistor. If REFoUT is connected directly to REFIN, the additional
gain error will be approximately 1%.
Either or both of the trim pots can be repiaced with 50 n ± 1%
fixed resistors if the specified ADI779 accuracy limits are sufficient for the application. If the pins are shorted together, the
additional offset and gain errors will be approximately 80 LSB.
To trim bipolar zero to its nominal value, apply a signal 112 LSB
below midrange (-0.305 mV for a ±5 V range) and adjust Rl
until the major carry transition is located (11 1111 1111 1111 to
00 0000 0000 0000). To trim the gain, apply a signal 1 112 LSB
below full scale (+4.9997 V for a ±5 V range) and adjust R2 to
give the last positive transition (01 1111 1111 1110 to 01 1111
1111 1111). These trims are interactive so several iterations may
be necessary for convergence.
A single pass calibration can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale), using the same circuit. First, apply a signal
112 LSB above.minus full scale (-4.9997 V for a ±5 V range)
and adjust RI until the minus full scale transition is located
(1000000000 0000 to 10 0000 0000 0001). Then perform the
gain error trim as outlined above.
:t6 V INPUT
~
Figure 11. Bipolar Input Connections with Gain and
Offset Trims
UNIPOLAR RANGE INPUTS
Offset and gain errors can be trimmed out by using the configuration shown in Figure 12. This circuit allows approximately
±25 mV of offset trim range (±40 LSB) and ±0.5% of gain
trim range (±80 LSB).
The nominal offset is 112 LSB so that the analog range that corresponds to each code will be centered in the middle of that
code (halfway between the transitions to the codes above and
below it). Thus the first transition (from 00 0000 0000 0000 to
00 0000 0000 000 1) should nominally occur for an input level of
3-224 ANALOG-TO-DIGITAL CONVERTERS
Figure 12. Unipolar Input Connections with Gain and
Offset Trims
REFERENCE DECOUPLING
It is recommended that a 10 j.LF tantalum capacitor be
connected between REFIN (Pin 9) and ground. This has the
effect of improving the SIN + D ratio through filtering possible
broad-band noise contributions from the voltage reference.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
1.22 rnA current through a 0.5 0 trace will develop a voltage
drop of 0.6 mY, which is I LSB at the 14-bit level for a 10 V
full scale span. In addition to ground drops, inductive and
capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
The ADI779 incorporates several features to help the user's layout. Analog pins (VEE' AIN, AGND, REFoUT' REF IN,
BIPOFF, Vee) are adjacent to help isolate analog from digital
signals. In addition, the 10 MO input impedance of AIN minimizes input trace impedance errors. Finally, ground currents
have been minimized by careful circuit architecture. Current
through AGND is 200 joLA, with no code dependent variation.
The current through DGND is dominated by the return current
for DB13-DBO and EOC.
AD1779
SUPPLY DECOUPLING
The ADI779 power supplies should be well filtered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. A 10 jl.F tantalum capacitor in parallel with a 0.1 jl.F ceramic capacitor provides adequate decoupling .
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the ADI779, associated analog input circuitry and interconnections as far as possible from logic circuitry. A solid analog
ground plane around the AD 1779 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit construction is preferred.
GROUNDING
If a single ADl779 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
ADI779. If multiple ADI779s are used or the ADI779 shares
analog supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This single interconnection of grounds prevents large
ground loops and consequently prevents digital currents from
flowing through the analog ground.
INTERFACING THE ADl779 TO MICROPROCESSORS
The I/O capabilities of the AD 1779 allow direct interfacing to
general purpose and DSP microprocessor buses. The asynchronous conversion control feature allows complete flexibility and
control with minimal external hardware.
ADl779 TO 80186
Figure 14 shows the ADI779 interfaced to the 80186 microprocessor. This interface allows the 80186's built-in DMA controller to transfer the ADI779 output into a RAM based FIFO
buffer of any length, with no microprocessor intervention.
The following examples illustrate typical AD 1779 interface
configurations.
The ADI779 is asynchronous which allows conversions to be
initiated by an external trigger source independent of the microprocessor clock. After each conversion, the ADI779 EOC signal
generates a DMA request to Channell (DRQl). The subsequent DMA READ sequences the high and low byte ADI779
data and resets the interrupt latch. The system designer must
assign a sufficient priority to the DMA channel to ensure that
the DMA request will be serviced before the completion of the
next conversion. This configuration can be used with 6 MHz
and 8 MHz 80186 processors.
AD1779 TO TMS320C25
In Figure 13 the ADl779 is mapped into the TMS320C25 I/O
space. ADI779 conversions are initiated by issuing an OUT
instruction to Port 8. EOC status and the conversion result are
read in with an IN instruction to Port 8. A single wait state is
inserted by generating the processor READY input from IS,
Port 8 and MSC. This configuration supports processor clock
speeds of 20 MHz and is capable of supporting processor clock
speeds of 40 MHz if a NOP instruction follows each ADI779
read instruction.
..,.
RIW
A>
A'
AD
•
A
14F138
STIl.
A3
G2.
G,
EXTERNAL TRIGGER - - - - - - - - '
Figure 14. AD1779 to 80186 DMA Interface
Figure 13. AD1779 to TMS320C25 Interface
ANALOG-TO-DIGITAL CONVERTERS 3-225
ADl779 TO Z80
The AD 1779 can be interfaced to the Z80 processor in an I/O or
memory mapped configuration. Figure 15 illustrates an I/O configuration, where the AD 1779 occupies several port addresses to
allow separate polling of the EOC status and reading of the data •.
A useful feature of the Z80 is that a single wait state is automatically inserted during IJO operations, allowing the AD 1779 to be
used with Z80 processors having clock speeds up to 8 MHz.
Wi!
Wi!
~ ~R~D____________~~
IORQ
1------,
AD1779
A1-A7
zao
ADl779 TO ANALOG DEVICES ADSP-2100A
Figure 16 demonstrates the ADI779 interfaced to an
ADSP-2100A. With a clock frequency of 1.25 MHz, and
instruction execution in one 80 ns cycle, the digital signal processor will support the AD 1779 data memory interface with two
wait states.
The converter runs asychronously using a sampling clock. The
EOC output of the AD 1779 gets asserted at the end of each conversion and causes an interrupt. Upon interrupt, the ADSP2100A starts a data memory read by providing an address on the
DMA bus. The decoded address generates OE for the converter.
OE, together with logic and latches, is used to force the. ADSP2100A into a two cycle wait state by generating DMACK. The
read operation is thus started and completed within three processor cycles (240 ns).
DMA
--fl
1----,
CLOCI(
sc
DATA BUS
cs
SYNC
EOCEN
AD1779
Figure 15. AD1779 to Z80 Interface
iii03l------------oC I-----------I_oc
OMD 15-2
DATA BUS
D''''''
Figure 16. AD1779 to ADSP-2100A Interface
3-226 ANALOG-TO-DIGITAL CONVERTERS
11IIIIIIII ANALOG
WOEVICES
12-Bit Successive Approximation
High Accuracy AID Converters
AD5200/AD521 0 Series I
FEATURES
True 12-Bit Operation: ±1/2LSB max Nonlinearity
Totally Adjustment-Free
Guaranteed No Missing Codes Over the Specified
Temperature Range
Hermetically-Sealed Package
Standard Temperature Range: - 2SoC to +8SoC
Extended Temperature Range: -5SoC to +12SoC
Serial and Parallel Outputs
Monolithic DAC with Scaling Resistors for Stability
Low Chip Count for High Reliability
Industry Standard Pin Out
Small 24-Pin DIP
MIL-STD-883B Processing Available
ADS200/ADS210 FUNCTIONAL BWCK DIAGRAM
START
1
1------,
SERIAL
OUT
EOC
81T7
81T8
12-8IT
SAR
BIT11
BIT 12
+16V
ANALOG
IN
GND
The innovative design of the ADS2XX series devices incorporates a monolithic 12-bit feedback DAC for reduced chip
count and higher reliability. The exceptional temperature
coefficients of the monolithic DAC guarantees ±1/2LSB linearity over the entire operating temperature ran§e of _25° C
to +8S oC for the BD grade and -55°C to +125 C for the
TO grade.
The ADS2XX series converters are available in 2 input voltage
ranges: ±SV (ADS2XI/ADS2X4) and ±10V (ADS2X2I
ADS2XS). The converters are available either complete with
an internal buried zener reference or with the option of an
external reference for improved absolute accuracy.
BIT9
BI110
TEST
POINT
ANALOG
GENERAL DESCRIPTION
The ADS2XX series devices are 12-bit successive approximation
analog-to-digital converters_ The hybrid design utilizes MSI
digital, linear monolithic chips and active laser trimming of
high-stability thin-film resistors to provide a totally adjustment
free converter-no potentiometers are required for calibration.
CLOCK IN
DIGGND
-V~:E~~
-16V
1
·PIN 12 FUNCTION: -VREF OUT - AD52X1. A~
-VREF IN - AD62X4. AD52X5
PRODUCT HIGHLIGHTS
1. The ADS 2XX series devices are laser trimmed at the factory
to provide a totally adjustment free converter-no potentiometers are required for 12-bit performance.
2. A monolithic 12-bit feedback DAC is used for reduced chip
count and higher reliability.
3. The ADS2XX series directly replaces other devices of this
type with significant increases in performance.
4. The devices offer true 12-bit accuracy and exhibits no
missing codes over the entire operating temperature range.
5_ The fast conversion rate of the ADS210 series makes it an
excellent choice for applications requiring high system
throughpu t rates_
The ADS2XX series converters are available in two performance grades; the "B" is specified from -25°C to +8S oC
and the "T" is specified from _SSoC to +12S oC. All units are
available in a 24-pin hermetically sealed ceramic DIP.
ANALOG-TO-DIGITAL CONVERTERS 3-227
•
SPECIFICATIONS
INPUT
RANGEl
(typical @
+ 25"C, ± 15V and + 5V unless otherwise noted)
INPUT
IMPEDANCE
-SV to +SV
-IOV to +IOV
S.Okn
IO.Okn
ADS2XIB
ADS2X2B
ADS2XIT
ADS2X2T
ADS2X4B
ADS2XSB
ADS2X4T
ADS2XST
External-IO.OOOV
•••
REFERENCE
RESOLUTION
Internal
12 Bits
LINEARITY ERROR, MAX
No Missing Codes Tmin to Tmax
±1I2LSB
Guaranteed
ZERO ERROR, MAX
±ILSB
ZERO ERROR, MAX
Tmin to Tmax
±2LSB
ABSOLUTE ACCURACY, MAX
±2LSB
•
ABSOLUTE ACCURACY, MAX
Tmin toTmax
±0.4% of FSR 2
±O.I% of FSR2
•••
COl\'VERSION TIME, MAX
Clock = IMHz (S2IO Series)
Clock = 260kHz (S200 Series)
13ps
SOils
•
•
LOGIC RATINGS
Input Logic Commands
Logic "0"
Logic "I"
Loading
O.BV max
+2.0V min
O.STTL Load
O.SmA
•••
S7SmW (B7SmW max)
•••
•
••
CLOCK INPUT PULSE WIDTH
lOOns min
OUTPUT LOGIC
Logic "0"
Logic "I"
0.4Vmax
3.6V (2.4 min)
FANOUT - HIGH
BTTL Loads
FANOUT-LOW
2TTL Loads
POWER SUPPLY REQUIREMENTS
VLOGIC
VCC
VDD
OPERATING CURRENT
VLOGIC
Vee
VDD
VREF
POWER SUPPLY REJECTION
VCC
VDD
POWER CONSUMPTION
OPERATING TEMPERATURE
RANGE
•
•
*
•
*
+SV ±10%
+lSV ±IO%
-lSV ±IO%
2SmA (42mA max)
lOrnA (16mA max)
20rnA (2BmA max)
±O.OOS%I% (±O.02%1% max)
±O.OOS%I% (±0.02%1% max)
•
•
S7SmW (B70mW max)
-2SoC to +BSoC
NOTES
·Same specifications as ADS2X1/X2B.
"Same specifications as ADS2X1/X2T.
·"Same specifications as AD52X4/X5B.
1 Other input ranges are available, consult factory.
• FSR is FuU Seale Range and is equal to the peak to peak input signal.
Specifications subject to cbange without notice.
3-228 ANALOG-TO-DIGITAL CONVERTERS
-SSoC to +I2SoC
AD5200/AD5210 Series
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-6S 0 C to +lS00 C
Positive Supply
+18V
-18V
Negative Supply
Logic Supply
-O.SVto +7V
±2SV
Analog Input
Digital Outputs
Logic Supply
Digital Inputs
+S.SV
Reference Supply
-lSV
START
1
t--------,
CLOCK IN
DIGGND
SE'::l~~
3
~----~
EOC
BIT7
BITS
r-__.....++-I'~:~T I-++-.------t
BIT9
BIT 10
+5Vo-+--I
1.
24
t--_,-~~-oGND
BIT 11
'kW
BIT 12
TEST
POINT
AD52XX SERIES
sooo-
r--r-r-r--o +'5V
t':2_____.2'j3r---I~-O -1SV
·DIVIDER ADDED FOR EXTERNAL REFERENCE MODELS ONLY.
+15V
ANALOG
GND
ANALOG
IN
12·81T DAC
-VREF OUT
-VREF IN
-15V
-PIN 12 FUNCTION: -VREF OUT - A052X'. AD52X2
-VREF IN - AOS2X4, AD52X5
Figure 2. Pin Designations
Figure 1. Burn In Circuit
AD52XX SERIES ORDERING GUIDE
Model
Linearity
Absolute
Accuracy
ADS21**BD
AD521··TD
ADS20··BD
ADS20·"TD
1I2LSB
1I2LSB
1I2LSB
1I2LSB
2LSB
2LSB
2LSB
2LSB
Temperature
Range
-2SoC to +8SoC
-SSoC to +12SoC
-2SoC to +8SoC
-SSoC to +12SoC
Conversion
Time
Package
Option"
Hils
Hils
SOilS
SOilS
DH-24C
DH-24C
DH-24C
DH-24C
NOTES:
TD grades are available with MIL-STD-883, Method 5008, Class B processing.
·See Section 14 for package outline information.
··Insert number according to desired input voltage range as shown in Table II.
ANALOG-TO-OIGITAL CONVERTERS 3-229
•
THEORY OF OPERATION
On receipt of a CONVERT START command, the ADS2XX
converts the voltage as its analog input into an equivalent
12-bit binary number. This conversion is accomplished as
follows: the 12·bit successive-approximation register (SAR)
has its 12 outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC.
The analog input is successively compared to the feedback
DAC output, one bit at a time (MSB first, LSB last). The
decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state
of the comparator at that time.
TIMING
The timing diagram is shown in Figure 3. A conversion is initiated by holding the ~tart convert low during a rising edge of
the clock. The start convert transition must occur at a minimum of 2S ns prior to thc clock transition. The end of conversion (E.O.C.) signal will be set simultaneously with the initia-
START - ,
CONVERT
tion of conversion. The actual conversion will not start until
the first rising edge of the clock after the start convert is again
set high. At time to. Bl is reset and B2-B12 are set unconditionally. At tl the Bit 1 decision is made and Bit 2
is unconditionally reset. At t2, the Bit 2 decision is made
(keep) and Bit 3 is reset· unconditionally. This sequence continues until the Bit 12 (LSB) decision (keep) is made at t12.
The STATUS flag is reset at time t12 indicating that the
conversion is complete and that the parallel output data is
valid.
Corresponding serial and parallel data bits become valid on
the same positive-going clock edge. Serial data does not change
and is guaranteed valid on negative-going clock edges, however;
serial data can be transferred quite simply by clocking it into a
receiving shift register on these edges (see Figure 3). An external clock of IMHz(ADS210) will yield 13lls conversion
time. An external clock of 260kHz (ADS200) will yield
SOps conversion time.
rj--------------------------------------------------
L-...J
EXTERNAL
CLOCK
ITs
STATUS
MSB : : : '
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
*
"0"
:::r-LJ"," i
:::J
L-j",,,
---J
1"0"
I
I
I
I
I
I I I I
--- J.------~·~=t----t----t_____;_____;_____;-r_I-:::J
j..o"
I I I I
:::J
LJ·,..j i i
:::Jr-----------,LJ . ,.. I I
::J
L-J~..~'..~I~~~--~----::]
1"0"
:::J
U ..,.. I
:::J~----------------------------~L_J~~~,. ~-----LSB :::J
SERIAL
BITS
BIT9
BIT '0
BIT "
"0"
DATA OUT
:::..:~
1
~..
2
..,..
: 3
..,..
I
4 : 5
"0" "0"
I
6 : 7 : S
.. ,.. ..,.. ..,..
L2.J
"0"
'0
.. , ..
LSB
..",.. L...IL.
"0;'1
Figure 3. Timing Diagram
The analog continuum is partitioned into 212 discrete ranges
for 12-bit conversion. All analog values within a given quantum are represented by the same digital code, usually assigned
to the nominal midrange value. There is an inherent quantization uncertainty of ±1/2LSB, associated with the resolution,
in addition to the actual conversion errors.
The actual conversion errors that are associated with AID
converters are combinations of analog errors due to the linear
circuitry, matching and tracking properties of the ladder and
scaling networks, reference error and power supply rejection.
The matching and tracking errors in the converter have been
minimized by the use of a monolithic DAC that includes the
scaling network. The initial gain and offset errors have been
3-230 ANALOG-TO-DIGITAL CONVERTERS
internally trimmed to provide an absolute accuracy of±O.OS%.
Linearity error is defined as the deviation from a true straight
line transfer characteristic from a zero analog input which
calls for a zero digital output to a point which is defined as
full scale. The linearity error is unadjustable and is the most
meaningful indication of AID converter accuracy. Differential
nonlinearity is a measure of the deviation in the staircase step
width between codes from the ideal least significant bit step
size (Figure 4).
Monotonic behavior requires that the differential linearity
error be less than lLSB. however a monotonic converter can
have missing codes; the ADS2XX is specified as having no
missing codes over the entire temperature range as specified
on the data page.
AD5200/AD5210 Series
There are three types of drift error over temperature: offset,
gain and linearity. Offset drift causes a shift of the transfer
characteristic left or right over the operating temperature
range. Gain drift causes a rotation of the transfer characteristic
about the zero or minus full scale point. The worst case accuracy drift is the summation of all three drift errors over
temperature. Statistically, however, the drift error behaves
as the root-sum-squared (RSS) and can be shown as:
Each of the ADS2XX's supply terminals should be capacitively
decoupled as close to the ADS2XX as possible. A large value
capacitor such as lllF in parallel with O.OlIlF capacitor is
usually sufficient. Analog supplies are bypassed to the Analog
Ground pin and the logic supply is bypassed to the Digital
Ground pin.
oo.o,.F11·+
'.o.F
@ 1I .
5v
DIGITAL
€G =Gain Drift Error (ppm/°C)
€o =Offset Drift Error (ppm of FSR/oC)
€L =Linearity Error (ppm of FSR/C)
000 .. 000
-g
U
aI
0
,
U
I-
g 011
"
0
~
::(;
GROUND
ell ·
I I
\:.:.J
I 1·
""",D.O,.F
1
@......
o.Ol.u F
+,5V
'.O.F ANALOG
GROUND
I'·OPF
...
~_...-~_...- ~ -'5V
Figure 6. Power Supply Decoupling
SAMPLED DATA SYSTEMS
Th~ conversion speed of the ADS2XX allows accurate digitization of high frequency signals and high throughput rates
in multichannel data acquisition systems. To make the
ADS2XX capable of full benefit from this high speed, a fast
sample-hold amplifier such as the AD346 or ADSHC-8S is
required. Figures 7 and 8 show the use of an AD346 and
ADSHC-8S as sample and holds in combination with the
ADS2XX.
--.------ .....___
.¢v~
..
v.
RANGE
iNT
iUSi
v..
DGND
AlB
DBO
OBl
AGND~c
AGNDo.o.c
AGND...oe
PRODUCT HIGHLIGHTS
1. Complete Analog I/O on a Single Chip.
The AD7569/AD7669 provides everything necessary to
interface a microprocessor to the analog world. No external
components or user trims are required, and the overall
accuracy of the system is tightly specified, eliminating the
need to calculate error budgets from individual component
specifications.
2. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications
the AD7569/AD7669 is specified for AC parameters, including
signal-to-noise ratio, distortion and input bandwidth.
3. Fast Microprocessor Interface.
The AD7569/AD7669 has bus interface timing compatible
with all modern microprocessors, with bus access and relinquish
times less than 75ns and Write pulse width less than 80ns.
ANALOG-TO-DIGITAL CONVERTERS 3-233
OAC SPECIFICATIONS1
(YOD = + 5V ± 5%; Vss2 = RANGE = AGNDIIAC = AGNDMIC
All specifications Tmln to TRIll unless othetwise staled.)
~
AD7569
J,AV-'
AD71i69
JVenioa
= DGND = OV; Rl = 2kO, Cl = 1OOpF to AGNDDAC unless otherwise staled.
AD7569
K,BVeniou
AD7569
SVenioa
8
±2
±I
±I
8
±2
±1/2
±2
±1.S
±2.5
±2
::!:2.5
±2
±3
AD7569
TVeraioa
UDits
8
±3
±I
±I
8
±3
Bits
LSBtyp
LSBmax
LSBmax
±1.S
±2
±2
±2.5
±2
LSBmax
LSBmax
±1.5
±2
±2
±2.5
±1.5
±2
LSBmax
LSBmax
±I
±2
±2
±4
±I
±3
LSBmax
LSBmax
CoaditioaolCommen..
STATIC PERFORMANCE
Resolution4
Total Unadjusted Error'
Relative Accuracy'
Differential Nooliuearity'
UnipolarOffsetError
@25"C
Tmm to T.-z
Bipolar ZeroOffset Error
@25"C
TauatoTmu.
Full·ScaleError'(AD7569Only)
@25"C
TmintoTmu.
±3/4
±1f2
±3/4
DACdataisaUOs;Vss =
@25"C
DACAlDACB Full Scale Error Match'
(AD7669 Only)
~FulIScslel~VDD. T. =25"C
4.FuIiScalef4.Vss, TA = 2S"C
Load ReguJationat Full Scale
DYNAMIC PERFORMANCE
Signal-t..Noioe Rallo' (SNR)
Total Harmonic Distortion' (THD)
Interm.od.uJadonDistordons (IMD)
-sv
Typical tempco is 20fLvrc for ± 1.2SV range
Voo=5V
Full·ScaIe Error' (AD76690nly)
T.-toT_
Guaranteed Monotonic
DACdata is aU Os; Vss=OV
Typical tempco is lOf,l.Vrcfor + 1.2SVrange
Voo=5V
LSBmax
±3
±4.5
LSBmax
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
0.2
LSRmax
LSBmax
LSBmax
LSBmax
RL= 2kOto OlC
44
46
48
55
44
46
48
55
dB min
dB max
dBtyp
VOVT = 20kHz full-scale sine wavewith fU.MPLING = 400kHz
VOUT = 20kHz full-scale sine wave with fSAMPLING = 400kHz
fa= 18.4kHz,fb= 14.SkHzwit:hfsAMPLlNG = 400kHz
Volts
Volts
VDO= +SV, Vss=OV
Vno = +SV, Vss= ~SV
±2.S
48
55
48
55
VDD=5V
VOUT
=
VOUT
= -2.SV;.6.Vss =
2.SVj.6.VOD
=
±5%
±S%
ANALOG OUTPUT
Output Voltage Raages
Unipolar
BipOlar
Oro + 1.2512.5
±1.2S/±2.S
LOGIC INPUTS
CS,AIB, WR,RANGE,RilS£'I', DBO-DB7
Input Low Voltage, VINL
Input High Voltage, VINH
Input LeakageCurrent
Input Capacitance'
0.8
2.4
10
10
0.8
2.4
10
10
DBO-DB7
Input Coding (Single Supply)
Input Coding(Dual Supply)
0.8
2.4
10
10
0.8
2.4
10
10
Vmas
V min
"A max
pFmax
2
4
2
15
I
".mas
nv.secstyp
nVsecstyp
60
dBtyp
V1N=OroVOO
Binary
2sComplement
ACCHARACTERlSTICS'
Voltage Output Settling Time
Positive FuJI-Scale Change
Settlingtimetowithin ± 1/2LSBoffinalvalue
2
Negative Full-Sca1eChsnge(Single Supply) 4
Ne..ti.. Full-Scale Chsnge (Dual Supply) 2
Digital-to-AnalOlGlitch ImpulseS
IS
D;,;tal Feodthrough'
I
VIN to VOllT Isolation
60
DAC to DACCrossta1k' (AD76690nly)
I
DACA to DACB lsolsllon' (AD76690nly)
-70
POWERREQUIREMBNTS
VODRanse
V.. Ranse(Dual Supplies)
100
(AD7569)
(AD71i69)
I" (Dusl SUJ'pIies)
(AD7569)
(AD71i69)
DACfADCMATCHING
GaiDMatching'
@25"C
TadGtoT_
2
4
2
15
I
60
2
4
2
IS
I
60
",max
",max
VIN = ±2.SV,SOkHzShteWave
nVsecstyp
dBmsx
4.75/5.25
- 4.75/ - 5.25
4.75/5.25
-4.75/-5.25
4.75/5.25
-4.75/-5.25
4.75/5.25
-4.75/-5.25
VminfVmax
VminfVmas
13
18
13
13
13
mAmas
mAmax
4
4
4
4
mAmax
mAmax
I
I
I
I
I
I
%typ
%typ
6
I
I
NOTES
'Specificstiooo apply to both DACo ia the AD7669. VOUTIpplioo., _
'Em:pt wbere noted, opocificsIioas apply iii< all'M"llOt _
Typical1y I".
Typic.l1y 2".
Typical1y I".
For SpeciI'ted Performsnce
SpeciflCdPerformancealsoapplies to VS5 = OV
for unipolar ranges.
VOllT = VIN = 2.SV; Logic Inputs "" 2.4V; CLK = O.8V
Output uulosded
Outputs unloaded
VOllT "" VIN = - 2.SV; Logic Inputs = 2.4V;CLK=O.8V
OutP1U unloaded
Outputs uulosded
VlNtoVoUTmatchwit:hVIN = ±2.SV,
20kHz sine wave
V..,.,A mel VOUTB of the AD7669.
with duol ..pply ......tion.
iacludiaa bipolar _
'Tcmperamrc nDpIlI't II follows: J, 1C. vc:niaoa; 0 to +7O'C
A, B ftI'IioDs; - 2S-C to +8S"C
S, T venicma; - SS"C to + lZS"C
'ILSB=4.88mV iii< 0 to + 1.25V output ....., 9.76mV iii< 0., +2.SV mel ±1.25V _
voI_ . full-scs1o voI_
'See TamiaoIoIY.
'IDc1udeo i a _
mel 19.5mV iii< ±2.5V_.
envr mel is _
...... 08iet ..... hss _
sdiosted out. Ideal uaipolor fWl-scs1o ..._
is (PS/2 - ILSB) ODd ideal bipolar _tift fWl-scs1o ~ is - FSIZ.
'Sunple tatcd ., 25"C to eaaarc ~.
SpeciIkstioos subject to chsop without aotice.
3-234 ANALOG-TO-OIGITAL CONVERTERS
is (FS - ILSB); ida! bipolor pooiti..
ADC SPECIFICATIONS
=
=
=
AD7569/AD7669
=
(Yoo + 5V ± 5%;
RANGE AGNDOAC AGNDMlC
All specifications Tmi" to Tmax unless otherwise stated.)
Specifications apply to Mode 1 interface.
Vss 1
= DGND = OV; fCLI( = 5MHz external unless otherwise stated.
AD7569
j,AVenioasz
Parameter
DC ACCURACY
Resolution 3
Total Unadjusted Error4
Relative Accuracy"
Differential Nonlinearity"
Unipolar Offset Error
@2\'C
T min to Tmu
Bipolar Zero Offset Error
@2\'C
T min to Tmu
Full-Scale ErrorS
@2\'C
T..unto Tmu
6.FulIScale/6.V OD • TA = 25°C
6.FulIScalel6,Vss , TA = 250C
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio" (SNR)
Total Hannonic Distortion4 (THD)
Intennodulation Distonion4 (IMD)
Frequency Response
TrackIHold Acquisition Time7
AD7669
AD7569
AD7569
JVenioa
K~BVenion8
SVemon
8
,,3
±I
"I
±1/2
±314
,,3
AD7569
TVersion
Units
8
,,4
"I
"I
±3/4
Bits
LSBtyp
LSBmax
LSBmax
± 1.5
"2.\
LSBmax
LSBmax
±4
± 112
Conditions/Comments
No Missing Codes
Typical tempco is lOlLV;oC for + 1.2SV range; V55 = OV
±2
,,3
"2.\
,,2
,,3
,,3
,,3.5
"2.\
,,3
±3
±4
,,2.5
±3.5
LSBmax
LS8max
-4. +0
-\.5, +1.\
0.5
0.5
-4, +0
-5.5, +LI
0.5
0.5
-4, +0
-7.S, +2
0.5
0.5
-4, +0
-7.5,+2
0.5
0.5
LSBmax
LS8max
LSBmax
LSBmax
44
46
44
48
60
0.1
200
48
60
0.1
200
48
60
0.1
300
45
48
60
0.1
300
dB min
dB max
dBtyp
dBtyp
nstyp
VIN = 100kHz full-scale smewave with fSAMPLING =400kHz6
VIN "" lOOkHzfull~scalesinewavewithfsAMPLING =4OOkHz6
fa = 99kHz, fb =: 96. 7kHz withfsAMPLING = 400kHz
VIN = ±2.5V,dcto200kHzsinewave
Volts
Volts
±300
±300
~Amax
VDD = +5V;Vss=OV
VDD= +5V;Vss= -5V
See equivalent circuit Fig. 5
10
10
pFtyp
"I.S
Typical tcmpco is 20p. Vf'C for ± 1.25V range; V 55:=
-
SV
VoD =5V
VIN
VIN
=
+ 2.5Vj6.V DD = ±5%
=
-2.SVj.dVss
=
±5%
ANALOG INPUT
Input Voltage Ranges
Unipolar
Bipolar
Input Current
Input Capacitance
,,300
10
Oto + 1.25/+2.5
± 1.2S/±2.5
±300
10
LOGIC INPUTS
CS, RD,ST,CLK,RESET, RANGE
Input Low Voltage, V INL
Input High Voltage, VINH
Input CapacitanceS
0.8
2.4
0.8
2.4
0.8
2.4
10
10
0.8
2.4
10
V max
V min
10
10
10
10
10
~Amax
VIN=OtOVDD
-1.6
40
- 1.6
40
-1.6
40
-1.6
40
rnA max
VIN=OV
VIN=VDD
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
Vrnax
10
10
10
Binary
10
10
10
10
pFmax
CS, RD, ST, RANGE, RESET
Input Leakage Current
CLK
Input Current
llNL
llNH
~Amax
LOGIC OUTPUTS
DBO-DB7,INT,BUSY
VOL. Output Low Voltage
VOH,OutputHigh Voltage
V min
ISINK = 1.6mA
IsouRcE = 200.... A
DBO-DB7
Floating State Leakage Current
Floating State Output CapacitanceS
Output Coding (Single Supply)
Output Coding (Dual Supply)
10
~Amax
pFmax
2s Complement
CONVERSION TIME
With External Clock
With Internal Clock, T A = 25°C
POWER REQUIREMENTS
2
1.6
2.6
2
1.6
2.6
2
1.6
2.6
2
1.6
2.6
~smax
....smin
~smax
fcLK =5MHz
Using recommended clock components shown in Fig~
ure 21. Clock frequency can be adjusted by varying RcLK.
As per DAC Specifications
NOTES
'Except where noted, specifications apply for all ranges including bipolar ranges with dual supply operation.
2Temperature ranges are as foUows: J, K versions; 0 to + 7WC
A, B versions; - 250C to + 850C
S, T versions; - 550C to + 1250C
JILSB = 4.88mV for 0 to + 1.25V range, 9.76mV for 0 to + 2.5V and ± 1.25V ranges and 19.5mV for ± 2.5V range.
4See Terminology.
sIncludes intema1 voltage reference error and is calculated after offset error bas been adjusted out. Idea) unipolar
last code transition occurs at (FS - 312LSB); Ideal bipolar last code transition occurs at (FSI2 - 3/2LSB).
6Exact frequencies are 101kHz and 384kHz to avoid harmonics coinciding with sampling frequency.
'Rising edge of BUSYto falling edge of ST. The time given refers to the acquisition time which gives a 3dB
degradation in SNR from the tested fIgure.
'Sample tested at 25°C to ensure compliance.
Specifications subject to change without notice.
ANALOG-TO-DIGITAL CONVERTERS 3-235
II
TIMING CHARACTERISTICS1 (See Figures 8, 10, 12; Villi = 5V ±5%;Vss = OVor -5V ±5%)
Parameter
DACTiming
tl
t2
t3
'"
ts
ADCTiming
t6
t7
ts
~
tUI(,
til
tl2
tIl
tIl
tIS
tl6
tIl
Limit at
2S·C(AllGrades)
Limit at
T mht, T""",
a,K,A,BGrades)
Limitat
T min , Tmax
(S, T Grades)
Units
Test Conditions/Comments
80
0
0
60
10
80
0
0
70
10
90
0
0
80
10
nsmin
nsmin
nsmin
nsmin
nsmin
WR Pulse Width
CS, AlB to WR Setup Time
CS, AlB to WR Hold Time
Data Valid to WR Setup Time
Data Valid to WR Hold Time
SO
110
20
0
0
60
0
60
9S
10
60
65
120
60
90
SO
130
30
0
0
75
0
75
120
10
75
75
140
75
115
SO
ISO
30
0
0
90
0
90
13S
10
85
85
160
90
135
nsmin
nsmax
nsmax
nsmin
nsmin
nsmin
nsmin
ST Pulse Width
ST to BUSY Delay
BUSY to INT Delay
BUSY to CS Delay
CS to RD Setup Time
RD Pulse Width. Determined by tl3'
CS toRD Hold Time
Data Access Time after RD; CL ~ 20pF
Data Access Time after RD; C L = l00pF
Bus Relinquish Time after RD
nsmax
nsmax
nsmin
nsmax
nsmax
nsmax
nsmax
nsmax
RD to INT Delay
RD to BUSY Delay
Data Valid Time after BUSY; C L = 20pF
Data Valid Time after BUSY; C L = l00pF
NOTES
'Sample tested at + 2S·C to ensure compliance. All input control signals are specified with tR = tF =Sns (10% to 90% of + SV) and timed from a voltage level of 1.6V.
2[13 and [17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either O.8V or 2.4V.
3[14 is defined as the time required. for the data line to change O.SV when loaded with the circuit of Figure 2.
Specifications subject to change without notice.
O~U
DGND
a. High-Z to VOH
0 ••
-4; U
~DGND
OON
+}V3kn
DBN~
T
\J
CL
DGND
b. High-Z to VOL
Figure 1. LoadCircuitsforDataAccess Time Test
ABSOLUTE MAXIMUM RATINGS
VootoAGNDoACorAGNDAIX: . . . . . . "
-0.3V, +7V
Voo to DGND . . . . . . . . . . .
. .. -0.3V, +7V
VootoVss . . . . . . .. .. . ..
. .. : -O.3V, +14V
AGNDoAC or AGNDAIX: to DGND
-0.3V, Voo +0.3V
AGNDoAC to AGNDAIX: . . . . ..
. . . . . . . . . ±5V
Logic Voltage to DGND . . .
-0.3V, Voo +0.3V
CLK Input Voltage to DGND
-0.3V, Voo +O.3V
VOUT(VOUTA, VOUTB)to
AGND IOAC .. .
. Vss -0.3V, Voo+0.3V
VIN to AGNDAIX: . . . .
Vss -O.3V, Voo +0.3V
NOTE
'Output may be shorted to any voltage in the range Vss to VDD provided that
the power dissipation of the package is not exceeded. Typical short circuit
current for a short toAGND or Vss is SOmA.
a. VOH to High-Z
DGND
b. VOL to High-Z
Figure 2. Load Circuits for Bus Relinquish Time Test
Power Dissipation (Any Package) to + 75°C
Derates above 75°C by ..
Operating Temperature Range
Commercial (], K)
Industrial (A, B) . . . . .
Extended (S, T)
Storage Temperature Range.
Lead Temperature (Soldering, 10 Secs)
450mW
6mWrC
o to +70°C
- 25°C to + 85°C
- 55°C to + 125°C
-65·C to +lSO°C
. . . . , +300°C
·Stress above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
3-236 ANALOG-TO-DIGITAL CONVERTERS
10pF
AD7569/AD7669
NOTE:
The term DAC (Digital-to-Analog Converter) throughout the
data sheet applies equally to the dual DACs in the AD7669 as
well as to the single DAC of the AD7569 unless otherwise stated.
It follows that the term VOUT applies to both VOUTA and VOUTB
of the AD7669 also.
TERMINOLOGY
Total Unadjusted Error
Total unadjusted error is a comprehensive specification which
includes internal voltage reference error, relative accuracy, gain
and offset errors.
Relative Accuracy (DAC)
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
allowing for offset and gain errors. For the bipolar output ranges
the endpoints of the DAC" transfer function are defined as those
voltages which correspond to negative full-scale and positive
full-scale codes. For the unipolar output ranges the endpoints
are code I and code 255. Code I is chosen because the amplifier
is now working in single supply and in cases where the true
offset of the amplifier is negative it cannot be seen at code o. If
the relative accuracy was calculated between code 0 and code
255 the "negative offset" would appear as a linearity error. If
the offset is negative and less than I LSB, it will appear at code
I, and hence the true linearity of the converter is seen between
code I and code 255.
Relative Accuracy (ADC)
Relative Accuracy is the deviation of the ADC's actual code
transition points from a straight line drawn between the endpoints
of the ADC transfer function. For the bipolar input ranges
these points are the measured negative full-scale transition point
and the measured positive full-scale transition point. For the
unipolar ranges the straight line is drawn between the measured
first LSB transition point and the measured full-scale transition
point.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and an ideal lLSB change between any two adjacent
codes. A specified differential nonlinearity of :!: 1LSB max ensures
monotonicity (DAC) or no missed codes (ADC). A differential
nonlinearity of :!: 3/4LSB max ensures that the minimum step
size (DAC) or code width (ADC) is 1I4LSB and the maximum
step size or code width is 3/4LSB.
Digital-to-Analog Glitch Impluse
Digital-to-Analog Glitch Impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected. It is normally specified as the area of the glitch
in nVsecs and is measured when the digital input code is changed
by I LSB at the major carry transition.
Digital Feedthrough
Digital Feedthrough is also a measure of the impulse injected to
the analog output from the digital inputs but is measured when
the DAC is not selected. It is essentially feedthrough across the
die and package. It is also a measure of the glitch impulse transferred to the analog output when data is read from the internal
ADC. It is specified in nVsecs and is measured with WR high
and a digital code .change from all Os to all Is.
DAC-to-DAC Crosstalk (AD7669 Only)
The glitch energy transferred to the output of one DAC due to
an update at the output of the second DAC. The figure given is
the worst case and is expressed in nV secs. It is measured with
an update voltage of full scale.
DAC-to-DAC Isolation (AD7669 Only)
DAC-to-DAC Isolation is the proportion of a digitized sine wave
from the output of one DAC which appears at the output of the
second DAC (loaded with all Is). The figure given is the worst
case for the second DAC output and is expressed as a ratio in
dBs. It is measured with a digitized sine wave (fSAMPLING =
100kHz) of 20kHz at 2.5V pk-pk.
Signal-to-Noise Ratio
Signal-to-Noise Ratio (SNR) is the measured signal to noise at
the output of the converter. The signal is the rms magnitUde of
the fundamental. Noise is the rms sum of all the nonfundamental
signals (excluding dc) up to half the sampling frequency. SNR
is dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical SNR for a sine wave is given by
SNR = (6.02N + 1.76) dB
where N is the number of bits. Thus for an ideal 8-bit converter,
SNR = 50dB.
Harmonic Distortion
Harmonic Distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7569/AD7669, Total Harmonic
Distortion (THD) is defined as
20 log
"
IV2+V2+V2+V2+V6 2
2
1
V4
5
V·
I
where VI is the rms amplitude of the fundamental and V2> V3,
V4, V5 and V6 are the rms amplitUdes of the individual
harmonics.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m + n), at sum and difference frequencies of
mfa:!:nfb, where m,n = 0, 1,2,3, ..... Intermodulation terms
are those for which m or n is not equal to zero. For example,
the second order terms include (fa + fb) and (fa - fb) and the
third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and
(fa -2fb).
ANALOG-TO-DIGITAL CONVERTERS 3-237
II
AD7S69 PIN CONFIGURATIONS
PLCC
DIP
~
; z
~ ~ c
"
"
v••
l!
LCCC
J
~
v"
J
~ §
.J
1282726
AGNDADC
CLK
00
RANGE 5
iNT
RESET
AD7569
BUSY
TOP VIEW
(Not to Seale'
ST
D87
7
NC
•
24 iNf
23 BUSY
AD7569
TOP VIEW
(Not to Scale)
D86 •
RD
25· eLK
L"
•
22 NC
DBS 10
OS
OB4 11
W-
083
,\I.!::====~
080
12 13 14 15 16 17
NC
S'f
iffi
19
CS
18
~~§~i!RI~
~~~~!~II
08'
)
21
20
= NO CONNECT
NC
= NO CONNECT
AD7669 PIN CONFIGURATIONS
DIP
PLCC
j
~
1- z
J ~ >8
:!
28
.7
"
,
J
~
Z6
0
25
AlII
AD7669
TOP VIEW
INot to Scale'
Ne
=
Ne
= NO CONNECT
NO CONNECT
AD7S69 ORDERING INFORMATION l
AD7669 ORDERING INFORMATION l
Relative
Accuracy (LSB)
TmiD-T ......
Relative
Accuracy (LSB)
TmiD-T""",
±l
± 1/2
±l
± 112
Temperature Range and Package Options2
Oto +70"c
- 25°C to + 85°C
Plastic DIP (N-24)
Hermetic DIP (Q-24) Hermetic DIP (Q-24)
AD7S69JN
AD7S69KN
AD7S69AQ
AD7S69BQ
- 55°C to + 12S"C
Plastic DIP (N-28)
AD7S69SQ
AD7S69TQ
±l
PLCC (P-28Ar
LCCC (E-28A)4
±l
AD7S69JP
AD7S69KP
AD7S69SE
AD7S69TE
NOTES
'To order MIL-STD-883, Class 8 processed parts, add 18838 to S Dr T grade part number.
'See Section 14 for package outline information.
3pLCC: Plastic Leaded Chip Carrier.
4LCCC: LeadIeos Ceramic Chip Carrier.
3-238 ANALOG-TO-DIGITAL CONVERTERS
Temperature Range
and Package Options2
Oto +7O"C
AD7669JN
PLCC (P-28AY
AD7669JP
NOTE
'PLCC: Plastic Leaded Chip Carrier.
'See Section 14 for package outline infonnation.
AD7569/AD7669
PIN FUNCTION DESCRIPTION
(Applies to the AD7569 and AD7669 unless otherwise stated.)
Pin
Mnemonic
AGND DAc
Pin
Mnemonic
Description
Analog Ground for the DAC(s). Separate
ground return paths are provided for the
DAC(s) and ADC to minimize crosstalk.
Description
Chip Select Input (Active Low). The device
is selected when this input is active.
CS
READ Input (Active Low). This input must
be active to access data from the part. In the
Mode 2 interface, RD going low starts conversion. It is used in conjunction with the CS
input (see Digital Interface Section).
VOUT
Output Voltage. VOUT is the buffered output
(VouTA, VouTB) voltage from the AD7569 DAC. VouTA and
VouTB are the buffered DAC output voltages
from the AD7669. Four different output
voltage ranges can be achieved (see Table I).
Vss
RANGE
BUSY Status Output (Active Low). When
this pin is active the ADC is performing a
conversion. The input signal is held prior to
the falling edge of BUSY (see Digital Interface Section).
Range Selection Input. This is used with the
Vss input to select the different ranges as per
Table I. The range selected applies to both
the analog input voltage of the ADC and the
output voltage from the DAC(s).
Reset Input (Active Low). This is an asynchronous system reset which clears the DAC
register(s) to all Os and clears the INT line of
the ADC (i.e., makes the ADC ready for new
conversion). In unipolar operation this input
sets the output voltage to OV; in bipolar operation it sets the output to negative full scale.
DB7
DB6-DB2
Start Conversion (Edge triggered). This is
used when precise sampling is required. The
falling edge of ST starts conversion and drives
BUSY low. The ST signal is not gated with
CS.
Negative Supply Voltage (- 5V for dual supply
or OV for single supply). This pin is also used
with the RANGE pin to select the different
input/output ranges and changes the data
format from binary (Vss= OV) to 2s complement (Vss= -5V) (see Table I).
INTERRUPT Output (Active Low). INT
going low indicates that the conversion is
complete. INT goes high on the rising edge
of CS or RD and is also set high by a low
pulse on RESET (see Digital Interface
Section).
A/B(AD7669
Only)
DAC Select Input. This input selects which
DAC register data is written to under control of
CS and WR. With this input low data is written
to the DACA register; with this input high data
is written to the DACB register.
CLK
A TTL compatible clock signal may be used
to determine the ADC conversion time. Internal
clock operation is achieved by connecting a
resistor and capacitor to ground.
Data Bit 7. Most Significant Bit (MSB).
Data Bit 6 to Data Bit 2.
DGND
Digital Ground.
DBI
Data Bit I.
o.
DBO
Data Bit
WR
Write Input (Edge triggered). This is used in
conjunction with CS to write data into the
AD7569 DAC register. It is used in conjunction
with CS and A/B to write data into the selected
DAC register of the AD7669. Data is transferred on the rising edge of WR.
Least Significant Bit (LSB).
Analog Ground for the ADC.
Analog Input. Various input ranges can be
selected (see Table I).
VDD
Positive Supply Voltage ( + 5V).
Range
Vss
Input/Output
Voltage Range
DBO-DB1
Data Format
0
1
0
1
OV
OV
-5V
-5V
Oto + 1.25V
010 +2.5V
± 1.25V
±2.5V
Binary
Binary
2s Complement
2s Complement
Table I. Input/Output Ranges
ANALOG-TO-DIGITAL CONVERTERS 3-239
II
Typical Performance Graphs
500
80
I
DAC-FSWfTH
......... <:::ALONVSS
Voo= +5V
Vss=OV
TA =25"C
200
100
~
I~
~
~
50
--
TA = 25"C
I
.L
IlAC + FS. voo,
60
.....
"-
REI'EREjE 'iMPUTED)
ADC - FS.
"'- ~
OU~PUTWITH
vsl
I
40
r-.... :-.
"'"
, '-
..............
ADC + FS, Voo
ALLOsONDAC
...........
-'
,
20
I
"-
20
10
50
100
200
500
1k
2k
5k
10k
20k
o
50k
20
100 200
FREQUENCY - Hz
1k
2k
10k 20k
100k 200k
FREOUENCY - Hz
Noise Spectral Density vs. Frequency
Power Supply Rejection Ratio vs. Frequency
WR
12V/DIvi
WR
(2V/DIVI
DACVoUT
(10mV/DIVI
DACVpuT
(10mV/DIVI
Positive-Going Settling Time (± 2.5V Range)
2.5V
2.475V
~
~
--
Negative-Going Settling Time (± 2.5V Range)
SAMPLE FREQUENCY = 409.6kHz
INPUT FREQUENCIES 159.4kHz. 167.8kHz
IMD=69.7dB
TA 25°C
=
Dr+-
=
I---
--- -
-20
ADC
2.45V
~
~
~
Voo= +5V
Vss=OV
RANGE=5V
u. 2.425V
-40
.!l
...
-60
-80
2.4V
-55
-25
25
TEMPERATURE -
70
85
oc
DAC/ADC Full-Scale Temperature Coefficient
3-240 ANALOG-TO-DIGITAL CONVERTERS
125
kHz
IMD Plot for ADC
AD7569/AD7669
CIRCUIT DESCRIPTION
D/ASECTION
The AD7S69 contains an g-bit, voltage-mode, D/A converter
which uses eight equally weighted current sources switched into
an R-2R ladder network to give a direct but unbuffered 0 to
+ 1.2SV output range. The AD7669 is similar but contains two
D/A converters. The current sources are fabricated using PNP
transistors. These transistors allow current sources which are
driven from positive voltage logic and give a zero-based output
range. The output voltage from the voltage switching R-2R
ladder network has the same positive polarity as the reference
and therefore the DIA converter can be operated from a single
power supply rail.
The PNP current sources are generated using the on-chip bandgap
reference and a control amplifier. The current sources are switched
to either the ladder or AGND oAC by high speed p-channel
switches. These high-speed switches ensure a fast settling time
for the output voltage of the DAC. The R-2R ladder network of
the DAC consists of highly stable, thin-film resistors. A simplified
circuit diagram for the DIA converter section is shown in Figure
3. An identical D/A converter is used as part of the AID converter
which is discussed later.
a transistor on the'output acts as a passive pull-down with output
voltages near OV with Vss = OV. This means that the sink capability
of the amplifier is reduced as the output voltage nears OV in
single supply. In dual supply operation the full sink capability
of 1.2SmA is maintained over the entire output voltage range,
For all other parameters the single and dual supply performances
of the amplifier are essentially identical. The output noise from
the amplifier with full scale on the DAC is 200....V peak-ta-peak.
The spot noise at 1kHz is 3SnV/vHZ with aliOs on the DAC.
A noise spectral density versus frequency plot for the amplifier
is shown in the typical performance graphs.
VOLTAGE REFERENCE
The AD7S69/AD7669 contains an on-chip bandgap reference
which provides a low noise, temperature compensated reference
voltage for both the DAC and the ADC. The reference is trimmed
for both absolute accuracy and temperature coefficient. The
bandgap reference is generated with respect to V00' It is buffered
by a separate control amplifier for both the DAC and the ADC
reference. This can be seen in the DAC ladder network configuration in Figure 3.
DIGITAL SECTION
The data pins on the AD7S69/AD7669 provide a connection
between the external bus and both the DAC data inputs and
ADC data outputs. The threshold levels of all digital inputs and
outputs are compatible with either TTL or SV CMOS levels.
Internal input protection of all digital pins is achieved by on-chip
distributed diodes.
The data format is straight binary when the part is used in
single supply (Vss =OV). However, when a Vssof -SV is applied,
the data format becomes 2s complement. This data format applies
to the digital inputs of the DAC and the digital outputs of the
ADC.
SHOWNFORAU 1s0NTHEDAC
Figure 3. DAC Simplified Circuit Diagram
OP AMP SECTION
The output from the D/A converter is buffered by a high speed,
noninverting op amp. This op amp is capable of developing
:!: 2.5V across a 2kO and lOOpF load to AGND oAC • The amplifier
can be operated from a single + SV supply to give two unipolar
output ranges or from dual supplies (:!: SV) to allow two bipolar
output ranges.
The feedback path of the amplifier contains a gain/offset network
which provides four voltage ranges at the output of the op amp.
The output voltage range is determined by the RANGE and Vss
inputs. (See Table I in the Pin Function Description section.)
The four output ranges possible are: 0 to + 1.2SV, 0 to +2.SV,
:!: 1.2SV and :!:2.SV. It should be noted that whatever range is
selected for the output amplifier also applies to the input voltage
range of the AID converter.
The output amplifier settles to within 1I2LSB of its final value
in typically less than SOOns. Operating the part from single or
dual supplies has no effect on the positive-going settling time.
However, the negative-going output settling time to voltages
near OV in single supply will be slightly longer than the settling
time to negative full scale for dual supply operation. Additionally,
to ensure that the output voltage can go to OV in single supply,
ADCSECTION
The analog-to-digital converter on the AD7S69/AD7669 uses the
successive approximation technique to achieve a fast conversion
time of 2....s and provide an g-bit parallel digital output. The
reference for the ADC is provided by the on-chip bandgap
reference.
Conversion start is controlled by ST or by CS and RD. Once a
conversion has been started another conversion start should not
be attempted until the conversion in progress is completed.
Exercising the RESET input does not affect conversion; the
RESET input resets the INT line high which is useful in interruptdriven systems where a READ has not been performed at the
end of the previous conversion. The INT line does not have to
be cleared at the end of conversion. The ADC will continue to
convert correctly but the function of the INT line will be
affected.
Figure 4 shows the operating waveforms for a conversion cycle.
The analog input voltage, VIN, is held SOns typical after the
falling edge of ST or (CS & RD). The MSB decision is made
approximately SOns after the second falling edge of the input
CLK following a conversion start. If tl in Figure 4 is greater
than SOns, then the falling edge of the input CLK will be seen
as the first falling clock edge. If tl is less than SOns, the first
falling clock edge of the conversion will not occur until one
clock cycle later. The succeeding bit decisions are made approximately SOns after a CLK edge until conversion is complete. At
ANALOG-TO-DIGITAL CONVERTERS 3-241
II
the end of conversion, the. SAR contents are transferrCd to the
output latch and the SAR is reset in readiness for a new conversion.
A single conversion lasts for 8 input clock cycles.
lL_______-...",• ______......Jf
~~;
BuSv
---,L-----4t----~1
I
tJ
-I to- 50ns TV.
VIN
"""'---...!'_ _ _ _ _ _ _.......________. /
eLK
INTERNAL CLOCK
Clock pulses are generated by the action of an internal current
source charging the external capacitor (CcLK) and this external
capacitor discharging through the external resistor (RcLK). When
a conversion is complete, this internal clock stops operating and
the CLK pin goes to the DGND potential. Connections for
RcLK and Cc~K are shown in the operating diagram of Figure
21. The nominal conversion tiDIe versus temperature for the
recommended RcLK and CcLK combination is shown in Figure
6. The internal clock provides a convenient clock source for the
AD7569/AD7669. Due to process variations, the actual operating
frequency for this RcLK/CcLK combination can vary from device
to device by up to ± 25%.
Figure 4. Operating Waveforms Using External Clock
3.2
ANALOG INPUT
The analog input of the AD7569/AD7669 feeds into an on-chip
track-and-hold amplifier. To accommodate different full-scale
ranges, the analog input signal is conditioned by a gain/offset
network which conditions all input ranges so that the internal
ADC always works with a 0 to + 1.25V signal. As a result, the
input current on the VIN input varies with the input range selected
as shown in Figure 5.
v,.
v••
':.
,
!:ii=
~ffi
2.8
Voo= +5V
Vss==ov
2.6
2.4
~
.,
2.0
VOLTAGE RANGE
.,.2.2
ON SWITCH
OTO +1.25V
OTO +2.5V
-1.25VTO +1.25V
- 2.5V TO + 2.5V
.3
.-/
o 2.2
I---f -
1.8
-55
I,
-25
2O.A
20llA
140p.A
280flA
y
i-"""
V
/
~
Hell( - 6.2kU
68pF
CcLK
25
TEMPERATURE - "c
70
85
=
125
Figure 6. Conversion Time vs. Temperature for Internal
Clock Operation
DIGITAL INTERFACE
Figure 5. Equivalent V,N Circuit
TRACK-AND-HOLD
The track-and-hold (T/H) amplifier on the analog input of the
AD7569/AD7669 allows the ADC to accurately convert an input
sine wave of 2.5V peak-to-peak amplitude up to a frequency of
200kHz, the Nyquist frequency of the ADC when operated at
its maximum throughput rate of 400kHz. This maximum rate of
conversion includes conversion time and time between conversions.
Because the input bandwidth of the T/H amplifier is much
larger than 200kHz, the input signal should be band~limited to
avoid converting high-frequency noise components.
The operation of this TIH amplifier is essentially transparent to
the user. The T IH amplifier goes from its tracking mode to its
hold mode at the start of conversion. This occurs when the
ADC receives a conversion start command from either ST or CS
& RD. At the end of conversion (BUSY going high) the T/H
reverts back to tracking the input signal.
EXTERNAL CLOCK
The AD7569/AD7669 ADC can be used with its on-chip clock
or with an externally applied clock. When using an external
clock, the CLK input of the AD7569/AD7669 may be driven
directly from 74HC, 4000B series buffers (such as 4049) or from
TTL buffers. When conversion is complete, the internal clock
is disabled. The external clock can continue to run between
conversions withbut being disabled. The mark/space ratio of the
external clock can vary from 70/30 to 30170.
3-242 ANALOG-TO-DIGITAL CONVERTERS
DAC TinIing and Control - AD7569
Table II shows the truth table for DAC operation for the AD7569.
The part contains an 8-bit DAC register which is loaded from
the data bus under control of CS and WR. The data contained
in the DAC register determines the analog output from the
DAC. The WR input is an edge-triggered input and data is
transferred into the DAC register on the rising edge of WR.
Holding CS and WR low does not make the DAC register
transparent.
~
WR
RESET
DACFunction
H
L
L
H
L
H
H
H
H
L
DAC Register Unaffected
DAC Register Unaffected
DAC Register Updated
DAC Register Updated
DAC Register Loaded with All Zeros
I
X
j"
L
X
L = Low State
H = High State
X = Don't Care
Table II. AD7569 DAC Truth Table
The contents of the DAC register are reset to all Os by an active
low pulse on the RESET line and for the unipolar output ranges
the output remains at OV after RESET returns high. For the
bipolar output ranges a low pulse on RESET causes the output
to go to negative full scale. In unipolar applications the RESET
line can be used to ensure power-up to OV on the AD7569 DAC
output and is also useful when used as a zero override in system
calibration cycles. If the RESET iJ;lput is connected to the system
AD7569/AD7669
RESET line, then the DAC output resets to OV when the entire
system is reset. Figure 7 shows the input control logic for the
AD7569 DAC and the write cycle timing diagram is shown in
Figure 8.
TO DAC LADDER
J
DAC REGISTER
FROM
The contents of the DAC registers are reset to all Os by an
active low pulse on the RESET line and for the unipolar output
ranges the outputs remain at OV after RESET returns high. For
the bipolar output ranges a low pulse on RESET causes the
outputs to go to negative full scale. In unipolar applications the
RESET line can be used to ensure power-up to OV on the AD7669
DAC outputs and is also useful when used as a zero override in
system calibration cycles. If the RESET input is connected to
the system RESET line, then the DAC outputs reset to OV
when the entire system is reset. Figure 9 shows the DAC input
control logic for the AD7669, and the write cycle timing diagram
is shown in Figure 8.
V"
RESET - - - - - - - - - '
TO DACA LADDER
080
DB6
DB7
INPUT DATA
TO DAce LADDER
Figure 7. AD7569 DAC Input Control Logic
R~ET
___________
FROM
~
Vss
AIB*
D80
DB6 D87
INPUT DATA
Figure 9. AD7669 DAC Control Logic
DATA
HIGH IMPEDANCE
BUS
HIGH IMPEDANCE
BUS
*AD76690NLY
NOTES
1. ALL INPUT RISE AND FAll TIMES MEASURED fROM 10% TO 90% OF +5V.
tA=tf=5ns
2. TIMING MEASUREMENT REFERENCE LEVEL IS
V'Nt!
+ V,Nt
--2-
Figure 8. AD75691AD7669 Write Cycle Timing Diagram
DAC Timing and Control - AD7669
Table III shows the truth table for the dual DAC operation of
the AD7669. The part contains two 8-bit DAC registers which
are loaded from the data bus under the control of CS, AlB and
WR. Address line AlB selects which DAC register the data is
loaded to. The data contained in the DAC registers determines
the analog output from the respective DACs. The WR input is
an edge-triggered input and data is transferred into the selected
DAC register on the rising edge of WR. Holding CS and WR
low does not make the selected DAC register transparent. The
AlB input should not be changed while CS and WR are low.
~
WIt
AlB
RESET
DAC Function
H
L
H
.f
X
L
L
H
H
X
H
H
H
H
H
L
DAC Registers Unaffected
DACA Register Updated
DACA Register Updated
DACBRegister Updated
DACB Register Updated
DAC Registers Loaded with
All Zeros
.!
L
S
X
L
.J
L
X
ADC Timing and Control
The ADC on the AD75691AD7669 is capable of two basic operating
modes. In the first mode the ST line is used to start conversion
and drive the track-and-hold into hold mode. At the end of
conversion the track-and-hold returns to its tracking mode. The
second mode is achieved by hard-wiring the ST line high. In
this case, CS and RD start conversion and the microprocessor is
driven into a WAIT state for the duration of conversion by
BUSY.
Sf
-I
H = High State
'CON;".T
1-.,
I
-,
~I--------~------------I
If
SF
I
" -.II-
'I~~I
-1 •.1cs -----------------("'--------~-;I
1',"1-
L...---!
1--'" -II- '"
-------4l1t-----,LJ
.,•...j
iW
---~i~--·"~--I t: ...j '''1:
DATA
L = Low State
-.J-1"1-I ,-
HIGH
IMPED~NCE BUS
~
X = Don't Care
Table III. AD7669 DAC Truth Table
Figure 10. ADC Mode 1 Interface Timing
ANALOG-TO-DIGITAL CONVERTERS 3-243
II
MODE 1 iNTERFACE
The timing diagram for the first mode is shown in Figure 10. It
can be used in digital signal processing and other applications
where precise sampling in time is required. In these applications
it is important that the signal sampling occurs at exactly equal
intervals to minimize errors due to sampling uncertainty or
jitter. In these cases the ST line is driven by a timer or some
precise clock source.
The falling edge of the ST pulse starts conversion and drives
the AD7S69/AD7669 track-and-hold amplifier into its hold
mode. BUSY stays low for the duration of conversion and returns
high at the end of conversion and the track-and hold amplifier
reverts to its tracking mode on this rising edge of BUSY. The
INT line can be used to interrupt the microprocessor. A READ
to the AD7S69/AD7669 address accesses the data and the INT
line is reset on the rising edge of CS or RD. Alternatively the
INT can be used to trigger a pulse which drives the CS and RD
and places the data into a FIFO or buffer memory. The microprocessor can then read a batch of data from the FIFO or buffer
memory at some convenient time. The ST input should not be
high when RD is brought low otherwise the part will not operate
correctly in this mode.
It is important, especially in systems where the conversion start
(ST pulse) is asynchronous to the microprocessor, that a READ
does not occur during a conversion. Trying to read data from
the device during a conversion can cause errors to the conversion
in progress. Also, pulsing the ST line a second time before
conversion end should be avoided since it too can cause errors
in the conversion result. In applications where precise sampling
is not critical the ST pulse can be generated from a microprocessor
WR or RD line gated with a decoded address (different to
AD7569/AD7669 CS address).
MODE 2 INTERFACE
The second interface mode is intended for use with microprocessors
which can be forced into a WAIT state for at least 2,..s. The ST
line oCthe AD7569/AD7669 must be hard-wired high to achieve
this mode. The microprocessor starts a conversion and is halted
until the result of the conversion is read from the converter.
Conversion is initiated by executing a memory READ to the
AD7569/AD7669 address, bringing CS and RD low. BUSY
subsequently goes low (forcing the microprocessor READY or
WAIT input low), placing the microprocessor into a WAIT
state. The input signal is held on the faIling edge ofRD (assuming
CS is already low or is co-incident with RD). When the conversion
is complete (BUSY goes high), the processor completes the
memory READ and acquires the newly converted data. While
conversion is in progress, the ADC places old data (from the
previous conversion) on the data bus. The timing diagram for
this interface is shown in Figure 12.
CSI
t,.--! r-
jjjj
Ir-
if
I
If
II
"
. I
t .. - ,
I
I
t,o-"IIBUSY
INT
..~t
HIGH
DATA IMPEDANCE
BUS
IS
OLD
~ATA
I
I
jlt17 t
X
+r--l
t,. ~
NEW
DATA
[
•
Figure 12. ADC Mode 2 Interface Timing
AINO
AlN.
AINN
1----01 v..
AD75691·
AD71169
087
FROMp.P
DBO
S'i' o - - -......- - - - - - t i i ' f
·ADDITIONAL PINS OMITTED FOR ClARITY
Figure ". Multichannellnputs
This interface mode is also useful in applications where a number
of input channels are required to be converted by the ADC.
Figure 11 shows the circuit configuration for such an appl:ication.
The signal which drives the ST input of the AD7569/AD7669 is
also used to drive the ENABLE input of the multiplexer. The
multiplexer is enabled on the rising edge of the ST pulse while
the input signal is held on the falling edge. Therefore, the signal
must have settled to within 8 bits over the duration of this ST
pulse. The settling time, including toN (ENABLE) of the multiplexer plus the T/H acquisition time (typically 2oons), thus
determines the width of the ST pulse. This is suited to applications
where a number of input channels need to be successively sampled
or scanned.
3-244 ANALOG-TO-DIGITAL CONVERTERS
The major advantage of this interface is that it allows the microprocessor to start conversion, WAIT and then READ data with
a single READ instruction. The user does not have to worry
about servicing interrupts or ensuring that software delays are
long enough to avoid reading during conversion. The fast conversion time of the ADC ensures that for many microprocessors,
the processor is not placed in a WAIT state for an excessive
amount of time.
DIGITAL SIGNAL PROCESSING APPLICATIONS
In Digital Signal Processing (DSP) application areas like voice
recognition, echo cancellation and adaptive filtering, the dynamic
characteristics (SNR, Harmonic Distortion, Intermodulation
Distortion) of both the ADC and DAC are critical. The
AD7569/AD7669 is specified dynamically as well &~ with standard
dc specifications. Because the tracklhold amplifier has a wide
bandwidth, an anti-aliasing filter should be placed on the VIN
input to avoid aliasing of high-frequency noise back into the
band of interest.
The dynamic performance of the ADC is evaluated by applying
a sine-wave signal of very low distortion to the VIN input which
is sampled at a 409.6kHz sampling rate. A Fast Fourier Transform
(FFT) plot or Histogram plot is then generated from which
SNR, harmonic distortion and dynamic differential nonlinearity
data can be obtained. For the DAC, the codes for an ideal sine
wave are stored in PROM and loaded down to the DAC. The
output spectrum is analyzed, using a spectrum analyzer to evaluate
AD7569/AD7669
SNR and harmonic distortion performance. Similarly, for intermodulation distortion, an input (either to VIN or DAC code)
consisting of pure sine waves at two frequencies is applied to
the AD7569/AD7669.
1 ... =25"(:
-20
-40
INPUT FREQUENCY = 13D.&kHz
SAMPLE FREQUENCY == 409.6kHz
SNR=48.4dB
T ... = 25"C
-so
-20r--------------------1----------~
!ll,
-80
~ -40 r--------------------1----------~
~
I
-
I
-'00 STARTOHl'
~
STOP SOOOOHz
VBW3Hz
RBW3DHz
ST21.NIN
Figure 15. DAC Output Spectrum
Figure 13. ADC FFT Plot
Figure 13 shows a 2048 point FFT plot of the ADC with an
input signal of 130kHz. The SNR is 48.4dB. It can be seen that
most of the harmonics are buried in the noise floor. It should be
noted that the harmonics are taken into accoUnt when calculating
the SNR. The relationship between SNR and resolution(N) is
expressed by the following equation:
SNR = (6.02N
+
1.76)dB
HISTOGRAM PLOT
When a sine wave of specified frequency is applied to the VIN
input of the AD7569/AD7669 and several thousand samples are
taken, it is possible to plot a histogram showing the frequency
of occurrence of each of the 256 ADC codes. If a particular step
is wider than the ideal lLSB width, then the code associated
with that step will accumulate more counts than for the code for
an ideal step. Likewise, a step narrower than ideal width will
have fewer counts. Missing codes are easily seen because a missing
code means zero counts for a particular code. The absence of
large spikes in the plot indicates small differential nonlinearity.
Figure 16 shows a histogram plot for the ADC indicating very
small differential nonlinearity and no missing codes for an input
frequency of 204kHz. For a sine-wave input, a perfect ADC
would produce a cusp probability density function described by
the equation
(V) _ _~1-----:-.,.,
- 1T (A2 - V2)V>
This is for an ideal part with no differential or integral linearity
errors. These errors will cause a degradation in SNR. By working
backwards from the above equation, it is possible to get a measure
of ADC performance expressed in effective number of bits (N).
This effective number of bits is plotted versus frequency in
Figure 14. The effective number of bits typically falls between
7.7 and 7.8 corresponding to SNR figures of 48.1 and 48.7dB.
The histogram plot of Figure 16 corresponds very well with this
cusp shape.
Figure 15 shows a spectrum analyzer plot of the output spectrum
from the DAC with an ideal sine-wave table loaded to the data
inputs of the DAC. In this case, the SNR is 46dB.
Further typical plots of the performance of the AD7569/AD7669
are shown in the Typical Performance Graphs section of the
data sheet.
p
where A is the peak amplitude of the sine wave and p(V) the
probability of occurrence at a voltage V.
2500 .----------,---------~------~-----~
INPUT FREQUENCY == 204.2kHz
SAMPLE FREQUENCY =409.6kHz
;
~ 7.5
~
~
z
't--------------------------------l
~
~
~
NUMBER OF SAMPLES = 100,000
t--------------------------------l
1 ... =25'1:
6.5
t-----------------------------------l
'2'0 It-------+------+--------+------~
TA = 25°C
SAMPLE FREQUENCY:: 409.6kHz
INPUT FREQUENCY - kHz
204.8
Figure 14. Effective Number of Bits vs. Frequency
64
128
192
255
COOE
Figure 16. ADC Histogram Plot
ANALOG-TO-DIGITAL CONVERTERS 3-245
II
INTERFACING THE AD7569/AD7669
AD7569/AD7669 - ZSO INTERFACE
Figure 17 shows a typical interface to the Z80 microprocessor.
The ADC is configured for operation in the Mode I interface
mode. A precise timer or clock source starts conversion in applications requiring equidistant sampling intervals. The scheme
used, whereby INT of the AD75691AD7669 generates an interrupt
on the Z80, is limited in that it does not allow the ADC to be
sampled at the maximum rate. This is because the time between
samples has to be long enough to allow the Z80 to service its
interrupt and read data from the ADC. To overcome this, some
buffer memory or FIFO could be placed between the AD75691
AD7669 and the Z80. Writing data to the relevant AD75691
AD7669 DAC simply consists of a instruction
where nn is the decoded address for that DAC. Reading data
from the ADC, after an INT has been received, consists of a
where Dn is the data
register which contains the data to be loaded to that bAC and
addr is the decoded address for the DAC. Data is read from the
ADC using a with the conversion result
placed in register Dn.
Figure 19. AD75691AD7669 to ADSP-2100 Interface
Because the instruction cycle of the ADSP-2100 is so fast (125ns
cycle) the DMWR pulse has to be stretched also for write cycles.
This is achieved using the 74121 which generates a pulse which
is fed back to DMACK. The duration of this pulse determines
how long the ADSP-2100 write cycle is stretched. The buffers
which drive the DMACK line must have open-collector outputs.
Writing data to the relevant AD7569/AD7669 DAC is achieved
using a single instruction, where addr is
the decoded address of that DAC and MRO contains the data to
be loaded to the DAC register. Data is read from the ADC
using a single instruction also, --------1 VON
SIGNAL
+5V
Vo
VOUT
1----0 'DELAYED'
OUTPUT
SIGNAL
On initial start-up the output voltage, Vo , will be invalid until
the length of the delay is reached (i.e., until the counter is
reset). From here on the delayed data is ;read from the 6116 and
loaded to the DAC before the newly converted data is written
into the same memory location. The input clock to the system
can be a square wave of maximum input frequency 200kHz
(assuming 2ILs conversion time for the ADC). The mark/space
ratio of the input clock can be varied to maximize the sampling
frequency if required. The clock low time has to be equal to the
conversion time and access time of the ADC plus the setup time
required for the 6116. The clock high time has only to be equal
to the setup time for the DAC plus the delay time through the
counter and the access time of the 6116.
The amount of memory used, as well as the sampling frequency,
determines the maximum possible delay. Using the HCT4040
and the 6116 with an input clock frequency of 200kHz, the
maximum delay is 5ms on a maximum input frequency of 100kHz.
Using 64K memory, with an 8kHz input clock frequency the
maximum delay is 8 seconds on a maximum input frequency of
4kHz.
TRANSIENT RECORDER - AD7569
The scheme just outlined can also form the basis for a transient
recorder. In this case transients on the input signal are converted
and stored in memory. The transient can then be recalled from
memory at a later time and the transient waveform can be recreated
using the AD7569 DAC.
INFINITE SAMPLE-AND·HOLD - AD7569
The AD7569 is ideal for implementing a single-chip infinite
sample-and-hold function. Basically, the ADC samples and
converts the input signal into an 8-bit digital word. The 8 bits
of data are then loaded to the DAC and the sampled value is
restored to analog form. The sampled value is held until the
DAC register is updated. The full-scale matching between the
ADC and the DAC on the AD7569 ensures a typical error of
less than 1% between the analog input voltage and the "held"
output voltage. Figure 29 shows the connections required on the
AD7569 to achieve this infinite sample-and-hold function.
VOUT
"HELD"
ANALOG
OUTPUT
AD7569*
SAMPLE
INPUT
L I 0 -.......--.1 RD
10F11
SWITCH
SELECTOR
ORMUX
ClK
IN
;,0----1 t.
"ADDITIONAL PINS OMITTED FOR CLARITY
Figure 29. Infinite Sample-and-Hold
HCT4040
MR
Figure 28. Analog Delay Line
3-250 ANALOG-TO-DIGITAL CONVERTERS
AD7569/AD7669
TARE FUNCTION FOR WEIGH SCALE - AD7569
The inflnite sample-and-hold just outlined can also form the
basis of a circuit to provide a tare function for a weigh scale
system. Figure 30 shows a circuit for a weigh scale system. It
incorporates a tare function using a simple circuit based on the
AD7569.
3 112 digit panel meter module which converts the signal for
digital readout. The input signal to the panel meter is also applied
to the analog input of the AD7569 for the tare function. When
the tare switch (81) is closed, a tare cycle commences and VIN is
sampled and held infmitely at VOUT until the next tare cycle.
VOUT drives the inverting input of the differential amplifler and
forces its output to zero. Thus, the tare function is used to give
a readout of zero for any undesired weight, such as a box, when
only the item placed in it is to be weighed. The tare function
can also be used in calibrating the system, to cancel out offset
errors due to the load cell, AD624 and differential amplifler.
The AD587 along with the 2N6285 provides a buffered + lOY
reference to supply the low impedance load cell transducer. The
load cell output is amplifled by the AD624 precision instrumentation amplifler with gain adjustment provided by Rl. The
output of the AD624 is applied to the noninverting input of a
unity gain differential summing amplifler which uses the AD707,
a high precision op amp with low drift. The AD707 feeds a
The AD7569 offers many advantages in the system outlined,
such as: simple, low cost circuit - no need for microprocessor,
software, etc. - and low power consumption.
+ 15V O- Input Low Voltage
V,NH, Input High Voltage
elN, 5 Input Capacitance
CS,RD,HBEN
IIN,lnputCurrent
CLKIN
liN, Input Current
LOGIC OUTPUTS
0I1-D0I8, BUSY, CLK OUT
VOl., Output Low Voltage
VOH , Output High Voltage
0I1-DO/8
Floating State Leakage Current
Floating State Output Capacitance'
CONVERSION TIME
AD7572XX05
Synchronous Clock
Asynchronous Clock
AD7572XXI2
Synchronous Clock
Asynchronous Clock
POWER REQUIREMENTS
Voo
Vss
IOD6
Iss'
Power Dissipation
± 112
±1/2
± 112
LSBtyp
± 112
± 112
± 112
± 112
LSBtyp
+0.8
+2.4
10
+0.8
+2.4
10
+0.8
+2.4
10
+0.8
+2.4
10
V max
V min
pFmax
Voo= 5V±5%
±1O
±1O
±IO
±IO
,.A max
Y'N = OtoVoo
±20
±20
±20
±20
,.A max
V 1N = OtOVDD
+0.4
+4.0
+0.4
+4.0
+0.4
+4.0
+0.4
+4.0
V max
V min
ISINK = 1.6mA
I souRCE = 200...A
±1O
IS
±IO
IS
±1O
15
±1O
IS
,.A max
pFmax
5
4.8/5.2
5
4.8/5.2
5
4.8/5.2
5
4.8/5.2
IJ.smax
...sminlmax
feLK = 2.5MHz. See Under
Control Inputs Synchronization
12.5
12113
12.5
12/13
12.5
12113
12.5
12113
...smax
...S mini .... max
fcLK = IMHz
+5
-IS
7
12
135
215
+5
-15
7
12
135
215
+5
-IS
7
12
135
215
+5
-IS
7
12
V NOM
V NOM
mAmax
mAmax
mWtyp
mWmax
± 5% for Specified Performance
± 5% for Speeified Performance
CS = RD = Voo,AIN=SV
CS = RD= Voo,AIN=5V
NOTES
ITempcnrurcraqeasfoJJcnn;; I, K, L VcnioDS;O to + 7O"C.
A,B,CVenions; -2S"Cro+8S"C.
S, T, UVersioas; -SS"Cro+ lZS"C.
llDcludes intemal YOItap reference error.
JFull-ScalcTC "" .b.FSI.b.T,wbere.b.FSisFull..scaaecbaqefromTA, "" + 2SOCtoT.in orT_.
'Jac:ludes intemol vol.... refcnonc:e drift.
·SompletemdlO ....... camplima:.
6PcJwersupplycurrenlismeasuredwhenAD7572isiuctive,i.c.~CS = iD "" iUSV = HIGH.
SpecifJCatioDs subject 10 cbaaae without DOtite.
~254
FSChange, Vss= -15V
Voo= +4.75Vto +5.25V
FSChange, Voo=5V
Vss = -14.25Vto -15.75V
±1/2
ANALOG-TO-DIGITAL CONVERTERS
13S
215
AD7572
TIMING CHARACTERISTlCS1
Limit at + 25°C
(All Grades)
Parameter
t(
t2
tl
0
190
90
125
t3
0
70
20
75
0
0
200
4
t5
1,;2
tl
t8
t9
tlO
5V, Vss - 15V)
Limit at T milo, T max
0, K, L, A, B, C Grades)
0
230
llO
150
t3
0
90
20
85
0
0
200
Limit at T milo, T max
(S, T, UGrades)
Units
Conditions/Comments
0
270
120
170
t3
0
100
20
90
0
0
200
nsmin
nsmax
nsmax
nsmax
nsmin
nsmin
nsmax
nsmin
nsmax
nsmin
nsmin
nsmin
CS to RD Setup Time
RD to BUSY Propagation Delay
Data Access Time after RD, CL = 20pF
Data Access Time after RD, CL = 100pF
RD Pulse Width
CS to RD Hold Time
Data Setup Time after BUSY
Bus Relinquish Time
HBEN to RD Setup Time
HBEN to RD Hold Time
Delay Between Successive
Read Operations
NOTES
'Timing Specifications are sample tested at + 25"<: to ensure compliance. All input control signals are specified with
tr ~ tf ~ 5ns(IO%t09O"Aoof + 5V) and timed from a voltage level of 1.6V.
't, and r. are measured with the load circuits of Figure I and defined as the time required for an
output to cross O.8Vor 2.4V.
't7 is defmed as the time required for the data lines to change O. 5V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
I3k!!
DBN
o--...- - -....---()
DBNo----r
3k!!
a. High-Z to VOH (t3)
and VOL to V OH (t6)
CL
~DGND
b. High-Z to VOL (t3)
and V OH to VOL (t6)
Figure 1. Load Circuits for Access Time
I3k!}
DBN
o--...- - -....---()
DBN~
T
10pF
\7DGND
a. VOH to High-Z
b.
VOL
to High-Z
Figure 2. Load Circuits for Output Float Oelay
ABSOLUTE MAXIMUM RATINGS·
(TA = + 25°C unless otherwise noted)
-0.3V to +7V
Vooto DGND .
+0.3V to -17V
Vss to DGND ..
AGND to DGND
-0.3V, Voo + 0.3V
. . . -15V to + 15V
AINtoAGND .
Digital Input Voltage to DGND
(CLK IN, HBEN, RD, CS)
-0.3V, Voo +0.3V
Digital Output Voltage to DGND
(011-00/8, CLK OUT, BUSY)
-0.3V, Voo +0.3V
Operating Temperature Range
Commercial (J, K, L Versions)
. . . 0 to +70°C
Industrial (A, B, C Versions)
- 25°C to + 85°C
- 55°C to + 125°C
Extended (S, T, U Versions) .
Storage Temperature . . . . . .
- 65°C to + 150°C
. +300°C
Lead Temperature (Soldering, 10secs)
Power Dissipation (Any Package) to + 75°C
1,000mW
Derates above + 75°C by . . . . . . . . . .
10mWI"C
·Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other condition above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
ANALOG-TO-DIGITAL CONVERTERS 3-255
ORDERING INFORMATION l
CONVERSION TIME = 5.... 5
Temperature Range and Package Options2
Full-Scale
TC
Accuracy
Grade
Oto + 70°C
- 25°C to + 85°C
- 55°C to + 125°C
45ppml"C
ZSppmf'C
Z5ppml"C
±lLSB
±lLSB
±lIZLSB
Plastic DIP (D-24A)
AD7S72JNOS
AD7S72KNOS
AD7572LN05
Hermetic3 DIP (Q-24)
AD7S72AQOS
AD7572BQ05
AD7572CQ05
45ppmJ°C
Z5ppml"C
25ppml"C
±lLSB
±lLSB
±lIZLSB
PLCC4 (P-28A)
AD7572JP05
AD7S72KPOS
AD7S72LPOS
Hermetic3 DIP (Q-24)
AD7572SQOS
AD7572TQ05
AD7S72UQOS
LCCCs (E-28A)
AD7S72SEOS
AD7572TE05
AD7S72UE05
CONVERSION TIME = 12.5 .... s
Temperature -Ra.l!ge and Package Optiona2
Full-Scale
TC
Accuracy
Grade
Oto +70°C
- 25°C to + 85°C
- 55°C to + 125°C
45ppml"C
Z5ppm/oC
25ppml"C
±lLSB
±lLSB
±lIZLSB
Plastic DIP (D-24A)
AD7572JN12
AD7572KNIZ
AD7572LNIZ
Hermetic3 DIP (Q-24)
AD7572AQ12
AD7572BQIZ
AD7S72CQIZ
Hermetic3 DIP (Q-24)
AD7572SQ12
AD7S72TQIZ
AD7572UQ12
45ppml"C
Z5ppml"C
2SppmJ°C
±lLSB
±lLSB
±1I2LSB
PLCC4 (P-28A)
AD7572JP12
AD7572KP12
AD7572LPIZ
LCCCs (E-28A)
AD7572SEIZ
AD7572TEIZ
AD7572UE12
NOTES
'To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your local
sales office for military data sheet. For U.S. Standard Military Drawing (SMD), see DESC
Drawing #5962-87591.
'See Section 14 for package outline information.
'Analog Devices reserves the right to ship either ceramic (package outline D-24A)
or cerdip hermetic (package outline Q-24) packages.
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
PIN CONFIGURATIONS
PLCC
LCCC
DIP
=I~
>8 > ..
D11
5
010
6
D9
7
..""
26
Z4
25CS
Rii
CS
RD
NC 8
08 9
TOP VIEW
{Not to Scale)
07 10
D6 11
HBEN
AD7572
23 H8EN
lOP VIEW
(Not to Scale)
AD7572
22 Ne
21 eLK OUT
NC
eLKIN
20 eLKIN
(.I2=======J;
19
19 00/8
12 13 14 15 16 17 18
NC=NOCON:~ ~ ~ ~ ~ 5
3-256 ANALOG-TO-DIGITAL CONVERTERS
is 2i !i! !l! ::
NC " NO CONNECT
g
8
i" "Q
D0J8
AD7572
DIP Pin No.
1
2
3
4 •.. 11
13 ... 16
Mnemonic
PIN FUNCTION DESCRIPTION
Description
AIN
V REF
AGND
Dll ... 04
D31ll ... DO/8
Analog Input.
Voltage Reference Output. The AD7572 has itsoWD internal - 5.25V reference.
Analog Ground.
Three State data outputs. They become active when CS and RD are brought low.
Individual pin function is dependent upon High Byte Enable (HBEN) Input.
DATA BUS OUTPUT,
Pia 4
MNEMONlC*
HBEN=LOW
HBEN=HJGH
PiaS
CS & iii = LOW
Pia 6
Pia 7
PiaS
DB DlO D9
DBB DBIO DB9
DBB DBIO DB9
08
DB8
DB8
07
D6
05
D4
D3/B 02110 01/9
DB7 DB6 DBS DB4 DB3 DB2 OBI
LOW LOW LOW LOW DBll DBIO DB9
Pia 9
Pia 10 PiaU Pial3 Pia 14 Pia IS Pia 16
00/8
DBO
DB8
II
NOTE
*011 . . . DO/8 are the ADC data output pins.
DBB ... DBO are the 12-bit conversion results, DBB is the MSB.
12
17
DGND
CLKIN
18
CLKOUT
19
HBEN
20
RD
21
CS
22
23
24
BUSY
Vss
Voo
Digital Ground.
Clock Input pin. An external TTL compatible clock may be applied to this pin. Alternatively
a crystal or ceramic resonator may be connected between CLK IN
(Pin 17) and CLK OUT (Pin 18).
Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock
is used. See CLK IN (Pin 17) description for crystal (resonator).
High Byte Enable input. Its primary function is to multiplex the 12-bits of conversion data onto
the lower D7 ... DO/8 outputs (4MSBs or 8 LSBs). See Pin description 4 •.. 11 and 13 ... 16.
It also disables conversion start when HBEN is high.
READ input. This active LOW signal, in corijunction with CS is used to enable
the output data three state drivers and initiate a conversion if CS and HBEN are low.
CHIP SELECT Input. This active LOW signal, in conjunction with RD is used to enable
the output data three state drivers and initiate a conversion if RD and HBEN are low.
BUSY output indicates converter status. BUSY is LOW during conversion.
NegativeSupply, -15V.
Positive Supply, + 5V.
OPERATIONAL DIAGRAM
An operational diagram for the AD7572 is shown in
Figure 3. The AD7572 is a 12-bit successive approximation
ND converter. The addition of just a crystal/ceramic resonator
and a few capacitors enables the device to perform the analogto-digital function.
o TO +5V
A~:~~~ o - - - - - - {
VREFOU~~~~ O--.........-vo"""f
O.lp.F
+5V
.'---n-15V
STATUS
- , - - - - OUTPUT
} ~~NTROL
INPUTS
:r---C1
~~
'--~
~
,
__ - - - - - .PDATA.US - - - - - ' ,
NOTES
AD7572XX05-2.SMH:I!:CRYSTAl/CERAMICRESONATOR.
AD7572XX12- 1.0MHz CRYSTAUCERAMIC RESONATOR.
C1 and C2 CAPACITANCE VALUES DEPEND ON CRYSTAL/CERAMIC RESONATOR
MANUFACTURER. TYPICAL VALUES ARE FROM 30 to 100pF.
Figure 3. AD7572 Operational Diagram
ANALOG-TO-DIGITAL CONVERTERS 3-257
CONVERTER DETAILS
Conversion start is controlled by the CS, RD and HBEN
inputs. At the start of conversion the successive approximation
register (SAR) is reset and the three-state data outputs are
enabled. Once a conversion cycle has begun it cannot be restarted.
During conversion, the internal 12-bit voltage mode DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 4, the AIN input connects to the comparator input
via 2.5kO. The DAC which has a similar 2.5kO output
impedance connects to the same comparator input. Bit decisions
are made by the comparator (zero crossing detector) which
checks the addition of each successive weighted bit from the
DAC output. The MSB decision is made 80ns (typically)
after the second falling edge of CLK IN following a conversion
start. Similarly, the succeeding bit decisions are made approximately 80ns after a CLK IN edge until conversion is
finished. At the end of conversion, the DAC output current
balances the AIN input current. The SAR contents (l2-bit
data word) w}\icn represent the A!~! input 8igr~ is loaded
into a 12-bit latch.
AIN
DRIVING THE ANALOG INPUT
During conversion, the AIN input current is modulated by
the DAC output current at a rate equal to the CLK IN frequency
(i.e., 2.SMHz when CLK IN = 2.5MHz). The analog input
voltage must remain fIXed during this period and as a result
must be driven from an ·op amp or sample hold with a low
output impedance. The output impedance of an op amp is
equal to the open loop output impedance divided by the loop
gain at the frequency of interest.
Suitable devices capable of driving the AD7572 AIN input
are the AD OP-27 and AD711 op amps or the AD58S sample
hold.
INTERNAL CLOCK OSCILLATOR
Figure 6 shows the AD7572 internal clock circuit. A crystal or
ceramic resonator may be connected between CLK IN (Pin 17)
and CLK OUT (Pin 18) to provide a clock oscillator for the
ADC timing. Alternatively the crystallresonator may be omitted
and an external clock source may be connected to CLK IN. For
an external clock the mark/space ratio must be 50/50. An inverted
eLK IN sig!".al will appear at the eLK OUT pin as shown in
the operating waveforms of Figure 5.
1 )...._ _,..",.,;;..._ _.....
AD7572
CLOCK
NOTES
AD1572XX05- 2.5MHzCRYSTAUCERAMlC RESONATOR.
AD7572XX12-1.0MHz CRYSTAUCERAMJC RESONATOR.
C1 andCZ CAPACITANCE VALUES DEPEND ON CRVST AUCERAMIC RESONATOR
MANUFACTURER. TYPICAL VALUES ARE FROM 30to 100pF.
Figure 6. AD7572 Internal Clock Circuit
Figure 4. AD7572 AIN Input
CS"Ro~
iillSY\
I
/
--J
r-
:: I
I
I~
BOn. TVP
eLKIN
~
I I
CLKOUT~~
t
DB11
(MSBj
t
0810
t
DBl
t
DBO
(LSBI
Figure 5. Operating Waveforms Using an External Clock
Source for CLK IN
CONTROL INPUTS SYNCHRONIZATION
In applications where the RD control input is not synchronized
with the ADC clock then conversion time can vary from 12
to 13 CLK IN periods. This is because the ADC waits for
the first falling CLK IN edge after conversion start before
the conversion procedure begins. Without synchronization,
this delay can vary from zero to an entire clock period. If a
constant conversion time is required, then the following
approach ensures a fixed 5 j.LS conversion time for the
AD7572XX05 and 12.5j.Ls for the AD7572XXI2: when initiating a conversion, RD must go low on either the rising
edge of CLK IN or the falling edge of CLK OUT.
3-258 ANALOG-TO-DIGITAL CONVERTERS
INTERNAL REFERENCE
The AD7572 has an on-chip, buffered, temperature-compensated,
buried Zener reference, which is factory trimmed to - 5.25V
± 1%. It is internally connected to the DAC and is also available
at Pin 2 to provide up to 550j.LA current to an external load.
For minimum code transition noise the reference output should
be decoupled with a capacitor to filter out wideband noise from
the reference diode (lOj.LF of tantalum in parallel with lOOnF
ceramic). However, large values of decoupling capacitor can
affect the dynamic response and stability of the reference amplifier.
A 100 resistor in series with the decoupling capacitors will
eliminate this problem without adversely affecting the filtering
effect of the capacitors. A simplified schematic of the reference
with its recommended decoupling components is shown in
Figure 7.
Figure 7. AD7572 Internal - 5.25V Reference
AD7572
UNIPOLAR OPERATION
Figure 8 shows the ideal input/output characteristic for the 0 to
5 volt input range of the AD7S72. The designed code transitions
occur midway between successive integer LSB values (i.e.,
1I2LSB, 3/2LSBs, S/2LSBs ... FS-3/2LSBs). The output code
is natural binary with ILSB = FS/4096 = (S/4096)V =
1.22mV.
OUTPUT
CODE
FULL SCALE
TRANSITION
,7
::. : ; tt
11 ... 101
, ,,"
I
:: :::~"
,
FS = 5V
"
1LSB =
4~:6
BIPOLAR OPERATION
Figures 10 and 12 show how bipolar operation can be achieved
with the AD7S72. Both circuits use an op-amp to offset the
analog signal (VIN) by 2.SV. Alternatively, the op amp (AI) can
be replaced by a sample hold as shown in Figure 24. The op
amp transfer functions are given below:
Figure 10: AIN = (V IN + 2.5) volts
Figure 12: AIN = (- VIN + 2.5) volts
Both circuits have an analog input range of ± 2.SV and an LSB
size of 1.22mV. The output codes are offset binary for Figure
10 and complementry offset binary for Figure 12. Their ideal
input/output transfer characteristics after offset and full scale
adjustment are shown in Figures II and 13.
Signal ranges other than ±2.SV are easily accommodated using
different values of R3 and R4 for Figure 10, and a different R2
value for Figure 12. These resistors should be chosen such that
the voltage range at AIN covers the full dynamic range (i.e., OV
to SV) of the ADC. All resistors should be the same type and
from the same manufacturer so that their temperature coefficients
match.
00 .. 001
--------+--+-1--
00 ... 000
o
1
2
J
FS
LSB LSB·S LSB·S
FS -1LSB
R3
ANALOG o-_6.,..19,..k_..._ _-I
INPUT V 1N
AIN.INPUT VOLTAGE (IN TERMS OF LSB's)
Figure 8. AD7572 Ideal Input/Output Transfer
Characteristic
UNIPOLAR OFFSET AND FULL-SCALE ERROR
ADJUSTMENT
In applications where absolute accuracy is important then offset
and full-scale error can be adjusted to zero. Offset error must be
adjusted before full-scale error. Figure 9 shows the extra components required for full-scale error adjustment. Zero offset is
achieved by adjusting the offset of the op amp driving AIN
(i.e., Al in Figure 9.). For zero offset error apply 0.61mV (i.e.,
1I2LSB) at VIN and adjust the op amp offset voltage until the
ADC output code flickers between 0000 0000 0000 and
0000 0000 0001.
For zero full-scale error apply an analog input of 4.99817V (i.e.,
FS-3/2LSBs or last code transition) at VIN and adjust RI until
the ADC output code flickers between llil Illl IllO and
1111 1111 lIlI.
R4
13k
'ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. AD7572 Bipolar Operation - Output Code is
Offset Binary
111. •• 111
I
100 .•• 010
100 ... 001
100 ... 000
0-5V
ANALOG
INPUT V,N
RJ
10
011 ..• 111
011 ..• 110
L-----~:O~
R2
20k
000 ... 001
000 ... 000
, ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. Unipolar
Adjust
A
111 •.. 110
a to
+ 5V Operation with Gain Error
-FS
I
I
I
I
....'Mf----t)-=.....-
....,~2--·n·-I
.....
I
I
I
fk:~::'"~
OV
V ,N• INPUT VOLTAGE
Figure 11. Ideal Input/Output Transfer Characteristic for
the Bipolar Circuit of Figure 10
ANALOG-TO-DIGITAL CONVERTERS 3-259
II
R3
6.19k
In measurement applications where absolute accuracy is required,
offset and full-scale error can be adjusted to zero as in
Figure 14.
R2
6.19k
ANALOG
INPUT CV....
IN ....../VY~~--I
ANALOG
INPUT VIN
Rl
13k
A,D7572*
R3
6.19k
~~,,2"~-----f
R4
13k
Rl
13k
• ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. AD7572 Bipolar Operation - Output Code is
Complementary Offset Binary
::: :::± n....
I
:::I! ~~!~.::
-FS
011 ... 110
~
~~l
*ADD!TIONAL PINS OMITTED FOR CLARITY
Figure 14. AD7572 Bipolar Operation with Offset and
Gain Error Adjust
-2- -ILSB
I
011 ... 111
1
'-----r--f
I ~J
OV
VIN • INPUT VOLTAGE
Figure 13. "deal Input/Output Transfer Characteristic
for the Bipolar Circuit of Figure 12
OFFSET AND FULL-SCALE ERROR
In most Digital Signal Processing (DSP) applications offset and
full-scale error have little or no effect on system performance. A
typical example is a digital fllter, where an analog signal is quanti2ed, digitally processed and recreated using a DAC. In these
type of applications the offset error can be eliminated by ac
coupling the recreated signal. Full-scale error effect is linear and
does not cause problems as long as the input signal is within the
full dynamic range of the ADC. An important parameter in
DSP applications is Differential Nonlinearity IIIId this is not
affected by either offset or full-scale error.
3-260 ANALOG-TO-DIGITAL CONVERTERS
BIPOLAR OFFSET AND FULL-SCALE ERROR
ADJUSTMENT
The bipolar circuit of Figure 10 can be adjusted for offset and
full-scale errors, by including two potentiometers RS and R6, as
shown in Figure 14. Offset must be adjusted before full-scale
error. This is achieved by applying an analog input of 0.61mV
(1I2LSB) at VIN and adjusting R5 until the ADC output code
flickers between lOOO ()()()() ()()()() and 1000 ()()()() 000 1.
For full-scale error adjustment, the analog input must be at
2,49817 volts (i.e., FS/2 - 3/2LSBs or last transition point).
Then R6 is adjusted until the ADC output code flickers between
1111 1111 1110 and 1111 1111 1111.
A similar offset and full-scale error adjustment procedure may
be employed for Figure 12 by making RI and R2 variable.
Offset must again be adjusted before full scale error. This is
achieved by applying an analog input of 0.61mV at VIN and
adjusting RI until the ADC output code flickers between
0111 1111 1110 and 0111 1111 I1ll.
For full-scale error adjust, apply a signal source of 2,49817V at
VIN and adjust R2 until the ADC output code flickers between
()()()() ()()()() ()()()() and ()()()() ()()()() 0001.
AD7572
APPLICATION HINTS
Wire wrap boards are not recommended for high resolution or
high-speed AID converters. To obtain the best performance
from the AD7572 a printed circuit board is required. Layout for
the printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an analog
signal track or underneath the AD7572. The analog input should
be screened by AGND.
A single point analog ground (STAR ground) separate from the
logic system ground should be established at Pin 3 (AGND) or
as close as possible to the AD7572 as shown in Figure 15.
Pin 12 (AD7572 DGND) and all other analog grounds should
be connected to this single analog ground point. No other digital
grounds should be connected to this analog ground point. Low
impedance analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil width
for these tracks should be as wide as possible.
Noise: Input signal leads to AIN and signal return leads from
AGND (Pin 3) should be kept as short as possible to minimize
input noise coupling. In applications where this is not possible,
a shielded cable between source and ADC is recommended.
Also, since any potential difference in grounds between the
signal source and ADC appears as an error voltage in series with
the input signal, attention should be paid to reducing the ground
circuit impedances as much as possible.
In applications where the AD7572 data outputs and control
signals are connected to a continuously active microprocessor
bus, it is possible to get LSB errors in conversion results. These
errors are due to feedthrough from the microprocessor to the
successive approximation comparator. The problem can be
eliminated by forcing the microprocessor into a WAIT state
during conversion (see Slow Memory Mode interfacing), or by
using three-state buffers to isolate the AD7572 data bus.
There are two modes of operation as outlined by the timing
diagrams of Figures 17 to 20. Slow Memory Mode is designed
for microprocessors which can be driven into aWAIT state, a
READ operation brings CS and RD low which initiates a conversion and data is read when conversion is complete.
The second is the ROM Mode which does not require microprocessor WAIT states, a READ operation brings CS and RD
low which initiates a conversion and reads the previous conversion
result.
DATA FORMAT
The output data format can either be a complete parallel load
(DBll .. DBO) for 16-bit microprocessors or a two byte load for
8-bit microprocessors. Data is always right justified (i.e., LSB is
the most right-hand bit in a 16-bit word. For a two byte read,
only data outputs D7 ... DO/8 are used. Byte selection is governed
by the HBEN input which controls an internal digital multiplexer.
This multiplexes the 12-bits of conversion data onto the lower
D7 ... DO/8 outputs (4 MSBs or 8 LSBs) where it can be read
in two read cycles. The 4 MSB's always appear on Dll ... D8
whenever the three-state output drives are turned on.
CONVERSION START
(RISING EDGE TRIGGER)
'----""=="'-.
---<.._
....
~----.:.:.===
ENABLE THREE-STATE OUTPUTS
01' ..• DOfB = DB11 ... DBO
ENABLE THREE-STATE OUTPUTS
011 ... 08 = 0811 ... DBS
07 .•. 04
LOW
D3t11 .•. 00/8 = DB11 ... DBS
=
*NOTE: 011 .. 0018 ARE THE ADC DATA OUTOUT PINS.
DB11. . DBO ARE THE 12-BIT CONVERSION RESUL15.
ANALOG
SUPPLY
+15V GND
-15V
Figure 15. Power Supply Grounding Practice
TIMING AND CONTROL
Conversion start and data read operations are controlled by
three AD7572 digital inputs; HBEN, CS and RD. Figure 16
shows the logic structure associated with these inputs. The three
signals are internally gated so that a logic "0" is required on all
three inputs to initiate a conversion. Once initiated it cannot be
re-started until conversion is complete. Converter status is indicated by the BUSY output, and this is low while conversion is
in progress.
Figure 16. Internal Logic for Control Inputs CS, RO and
HBEN
SLOW MEMORY MODE, PARALLEL READ (HBEN =
LOW)
Figure 17 and Table I shows the timing diagram and data bus
status for Slow Memory Mode, Parallel Read. CS and RD going
low triggers a conversion and the AD7572 acknowledges by
taking BUSY low. Data from the previous conversion appears
on the three state data outputs. BUSY returns high at the end
of conversion when the output latches have been updated and
the conversion result is placed on data outputs D 11 ... DO/8.
SLOW MEMORY MODE, TWO BYTE READ
For a two byte read only 8 data outputs D7 ... DO/8 are used.
Conversion start procedure and data output status for the first
read operation is identical to Slow Memory Mode, Parallel Read.
See Figure 18 timing diagram and Table II data bus status. At
the end of conversion the low data byte (DB7 ... DBO) is read
from the ADC. A second READ operation with HBEN high,
places the high byte on data outputs D3/11 ..• DO/8 and disables
conversion start. Note the 4MSB's appear on data outputs
Dll ... D8 during the two READ operations above.
ANALOG-TO-OfGfTAL CONVERTERS 3-261
II
Figure 17. Slow Memory Mode, Parallel Read Timing Diagram
AD7S72 Oata Outputs
Read
Table I. Slow Memory Mode, Parallel Read Data Bus Status
Figure 18. Slow Memory Mode, Two Byte Read Timing Diagram
AD7S72 Oata Outputs
D7
D6
OS
D4
03111
02110
0119
0018
First Read
DB7
DB6
DBS
DB4
DB3
DB2
DBI
DBO
Second Read
LOW LOW LOW LOW DB 11
DBlO
DB9
DB8
Table II. SlowMemoryMode, Two Byte Read Data Bus Status
Figure 19. ROM Mode, Parallel Read Timing Diagram
AD7S72 Oata Outputs
011
D8
D7
D6
OS
D4
03/11
D2II0
0119
DOI8
First Read (Old Data)
DBll DBlO DB9
DB8
DB7
DB6
DBS
DB4
DB3
DB2
DBI
DBO
Second Read
DBll DBIO DB9
DB8
DB7
DB6
DBS
DB4
DB3
DB2
DBI
DBO
010
D9
Table 111. ROM Mode, Parallel Read Data Bus Status
3-262 ANALOG-TO-DIGITAL CONVERTERS
AD7572
CS
RD
•
BUSY
DATA - - - - - {
OLD DATA
DB7-DBD
Figure 20. ROM Mode, Two Byte Read Timing Diagram
AD7S720ataOutputs
07
06
OS
D4
0311l
02/10
01/9
DO/8
First Read (Old Data)
DB1
DB6
DBS
DB4
DB3
DB2
DBI
DBO
Second Read
LOW LOW LOW LOW DB 11
DBIO
DB9
DBS
Third Read
DB7
DB2
DBI
DBO
DB6
DBS
DB4
DB3
Table ,V. ROM Mode, Two Byte Read Data Bus Status
ROM MODE, PARALLEL READ (HBEN = LOW)
The ROM Mode avoids placing a microprocessor into a wait
state. A conversion is started with a READ operation and the
12-bits of data from the previous conversion is available on data
outputs DlI ... DO/S (see Figure 19 and Table III). This data
may be disregarded if not required. A second READ operation
reads the new data (DB 11 ... DBO) and starts another conversion.
A delay at least as long as the AD7572 conversion time must be
allowed between READ operations.
ROM MODE, TWO BYTE READ
As previously mentioned for a two byte read, only data outputs
D7 ... DO/S are used. Conversion is started in the normal way
with a READ operation and the data output status is the same
as the ROM Mode, Parallel Read. See Figure 20 timing diagram
and Table IV data bus status. Two more READ operations are
required to access the new conversion result. A delay equal to
the AD7572 conversion time must be allowed between conversion
start and the second data READ operation. The second READ
operation, with HBEN high, disables conversion start and places
the high byte (4MSBs) on data outputs D311l ... DO/S. A
third READ operation accesses the low data byte (DB7 ... DBO)
and starts another conversion. The 4MSB's appear on data
outputs DlI ... DS during all three read operations above.
MC68000 Microprocessor
Figure 21 shows a typical interface for the 68000. The AD7572
is operating in the Slow Memory Mode. Assuming the AD7572
is located at address COOO, then the following single 16-bit MOVE
instruction both starts a conversion and reads the conversion
result.
Move. W $COOO,DO
At the beginning of the instruction cycle when the ADC address
is selected, BUSY and CS assert DTACK, so that the 68000 is
forced into a WAIT state. At the end of conversion BUSY
returns high and the conversion result is placed in the DO register
oCthe UP.
A23~----------~
Alt------.
AS r---"J
AD7572*
MC68000
I~~~----~~
H - - - - - - - - I BUSY
R/W
1------1
...;)O.---_~
L -_ _ _ _ _ _ _ _ _- - \
AD
011
011
MICROPROCESSORINTERFACUNG
The AD7572 is designed to interface with microprocessors as a
memory mapped device. The CS and RD control inputs are
common to all peripheral memory interfacing. The HBEN input
serves as a data byte select for 8-bit processors and is normally
connected to the microprocessor address bus.
DO
"LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 21. AD7572 - MC68000 Interface
ANALOG-TO-DIGITAL CONVERTERS 3-263
8085A, Z80 MICROPROCESSOR
Figure 22 shows an AD7572 interface for the Z80 and 8085A.
TheAD7572 is operating in the Slow Memory Mode and a two
byte read is required. Not shown in the figure is the 8-bit latch
required to demultiplex the 8085A common address/data bus.
AO is used to assert HBEN, so that an even address (HBEN =
LOW) to the AD7572 will start a conversion and read the low
data byte. An odd address (HBEN = HIGH) will read the high
data byte. This is accomplished with the single 16-bit LOAD
instruction below.
For the 8085A
For the Z80
A15
ADDRESS BUS
AO
oJ
lEN
I
280
I
ADDRESS
DECODE
I
Figure 23. A07572 - TMS32010 Interface
S
HBEN
cs
BUSY
AD
AD
k.
q07
DATA BUS
DO
D"~--------------------~
001------,
"LINEAR CIRCUITRY OMITTED FOR CLARITY
AD7572*
WAIT
07
AO
I,
'{
8085A
DEN~---..
TMS32010
LHLD(BOOO)
LD HL, (BOOO)
This is a two byte read instruction which loads the ADC data
(address BOOO) into the HL register pair. During the first read
operation, BUSY forces the microprocessor to WAIT for the
AD7572 conversion. No WAIT states are inserted during the
second read operation when the microprocessor is reading the
high data byte.
MREQ
PA2~---------------------,
PAO 1------,
r-.r
AD7572-AD585 SAMPLE-HOLD INTERFACE
Figure 24 shows an AD585 sample-hold amplifier driving the
AIN input of the AD7572. The interface contains resistors Rl,
R2, R3 and R4 to allow a bipolar input signal range of ±2.5
volts. The maximum sampling frequency is 125kHz for the
AD7572XX05 (51'-s conversion) and 64.5kHz for the
AD7572XXI2 (12.5l'-s conversion). This includes the sample-hold
amplifier acquisition time (3I'-s).
When an AD7572 conversion is initiated, the converter BUSY
output goes low indicating conversion is in progress. The falling
edge of this BUSY output signal places the sample-hold amplifier
into the HOLD mode "freezing" the input signal to the AD7572.
When conversion is finished, the BUSY output returns HIGH
allowing the sample-hold to track the input signal. To achieve
the maximum sampling rate, the AD7572 output data must be
read within 31'-s immediately after conversion while the samplehold amplifier is acquiring the next sample.
"LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 22. A07572 - BOB5A/ZBO Interface
TMS32010 MICROCOMPUTER
Figure 23 shows an AD7572-TMS32010 interface. The AD7572
is operating in the ROM Mode. The interface is designed for a
maximum TMS32010 clock frequency of 18MHz but will typically
work over the full TMS32010 clock frequency range.
The AD7572 is mapped at a port address. The following 110
instruction starts a conversion and reads the previous conversion
result into data memory.
ANAlOG
INPUT
-2.SVTO +2.SV
R4
INA,PA
(PA = PORT ADDRESS)
13k
When conversion is complete, a second 110 instruction reads the
up-to-date data into data memory and starts another conversion.
A delay at least as long as the ADC conversion time must be
allowed between 110 instructions.
"AOOInONAl PINS OMITTED FOR CLARITY
Figure 24. A07572 - A05B5 Sample-and-Hold Interface
3-264 ANALOG-TO-OIGITAL CONVERTERS
LC 2MOS
5fJ.s a-Bit ADC with Track/Hold
AD7575 I
~ANALOG
WDEVICES
FEATURES
Fast Conversion Time: 5"s
On-Chip Track/Hold
Low Total Unadjusted Error: 1LSB
Full Power Signal Bandwidth: 50kHz
Single + 5V Supply
100ns Data Access Time
Low Power (15mW typ)
Low Cost
Standard 18-Pin DIPs or 20-Terminal
Surface Mount Packages
AD7575 FUNCTIONAL BLOCK DIAGRAM
Voo
GENERAL DESCRIPTION
The AD7S7S is a high-speed 8-bit ADC with a built-in tracklhold
function. The successive approximation conversion technique is
used to achieve a fast conversion time of SiloS, while the built-in
tracklhold allows full-scale signals up to 50kHz (386mV/lLs slew
rate) to be digitized. The AD7S7S requires only a single + SV
supply and a low-cost, 1.23V bandgap reference in order to
convert an input signal range of 0 to 2VREF •
The AD7S7S is designed for easy interfacing to all popnlar 8-bit
microprocessors using standard microprocessor control signals
(CS and RD) to control starting of the conversion and reading
of the data. The interface logic allows the AD7S7S to be easily
configured as a memory mapped device and the part can be
interfaced as SLOW-MEMORY or ROM. All data outputs of
the AD7S7S are latched and three-state buffered to allow direct
connection to a microprocessor data bus or 110 port.
The AD7S7S is fabricated in an advanced, all ion-implanted
high-speed linear compatible CMOS (LC2MOS) process and is
available in either a small, 0.3" wide I8-pin DIP or in 20-terminal
surface mount packages.
ORDERING INFORMATION 1
Relative
Accuracy
(LSB)
Temperature Range and
Package Options2
Oto +70·C
-25·Cto
+ 85·C
-55·Cto
+ 125·C
Plastic DIP
(N-I8)
Hermetic DIP
(Q-18)
Hermetic DIP
(Q-18)
±I
AD7575JN
AD7575AQ
AD7575SQ
± 112
AD7575KN
AD7575BQ
AD7575TQ
±I
± 112
PLCC3 (P-20A)
LCCC4 (E-20A)
AD757SJP
AD7575KP
AD7575SE
AD7575TE
PRODUCT HIGHLIGHTS
1. Fast Conversion Time/Low Power
The fast, SiloS conversion time of the AD7575 makes it suitable
for digitizing wideband signals at audio and ultrasouic frequencies, while retaiuing the advantage of low CMOS power
consumption.
2. On-Chip Track/Hold
The on-chip track/hold function is completely self-contained
and requires no external hold capacitor. Signals with slew
rates up to 386mV/ILs (e.g., 2.46V peak-to-peak 50kHz sine
waves) can be digitized with full accuracy.
3. Low Total Unadjusted Error
The zero, full-scale and linearity errors of the AD757S are so
low that the total unadjusted error at any point on the transfer
function is less than ILSB and offset and gain adjustments
are not required.
4. Single Supply Operation
Operation from a single + 5V supply with a low-cost + 1.23V
bandgap reference allows the AD7S7S to be used in 5V
microprocessor systems without any additional power
supplies.
5. Fast Digital Interface
Fast interface timing allows the AD7575 to interface easily to
the fast versions of most popular microprocessors such as the
Z80H, 8085A·2, 6502B, 68B09 and the DSP processor, the
TMS320IO.
NOTES
ITo order MIL·STD·883, Class B processed parts, addl883B to part number.
Contact your local sales office for military data sheet. For U.S. Standard Military
Drawing (SMD), see DESC drawing #5962·87762.
2See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier.
4LCCC: Leadless Ceramic Chip Carrier.
ANALOG-TO-DIGITAL CONVERTERS 3-265
= + 5V; V = + 1.23V; AGND = DGND = OV; fClJ(=4MHz exbImaI;
SPECIFICATIONS All specifications
Tmil to T.... 1ll1ass oIIawise noIId.>
(VIII
Parameter
ACCURACY
Resolution
Total Unadjusted E~ror
Relative Accurscy
MinimumResolutionforwbich
No Missing Codes is Guaranteed
Full Scale Error
250C
Tmin to Tmax
Offset Error
250C
T_toT....
ANALOG INPUT
Voltage Range
DC Input Impedance
Slew Rate, Trscking
sm3
REFERENCE INPUT
AEF
I,A
Versions'
8
±2
±I
K,B
Versions
SVersion
TVersion
Units
8
±I
8
±2
±I
±1
±'h
Bits
LSBmax
LSBmax
±'h
Conditions/Comments
Bits max
.±I
±I
±I
±I
±I
±I
±I
±I
LSBmax
LSBmax
Full Scale TC is typically 5ppmI"C
±lh
±'h
±'h
±lh
±'h
±'h
LSBmax
LSBmax
Offset TC is typically 5ppmJ"C
±'h
Ot02VREF
10
0.386
45
Ot02VREF
10
0.386
45
Ot02VREF
10
0.386
45
Volts
MOmin
V/",smax
dB min
±Yi
Ot02VREF
10
0.386
45
ILSB = 2VREP'256; See Figure 4
VIN=2.46Vp-p@IOkHz;SeeFigurel
VREF (For specified Performance)
,"
.l.£~
.l • .l.::J
lREF
500
500
1.23
500
i.23
500
VOilS
".A max
0.8
2.4
0.8
2.4
0.8
2.4
0.8
2.4
V max
V min
±I
±1O
10
±I
±1O
10
±I
±1O
10
±I
±10
10
".A max
",A max
pFmax
0.8
2.4
700
700
0.8
2.4
700
700
0.8
2.4
800
800
0.8
2.4
800
800
V max
V min
".A max
",A max
VINL=OV
V'NH= Voo
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
V max
V min
ISINK = 1.6mA
IsoURCE = 4O".A
±I
10
±I
10
±1O
10
±1O
10
",A max
pFmax
VOUT=OtoVoo
5
5
IS
5
5
IS
5
5
IS
5
5
15
",S
feu< = 4MHz
Using recommended clock
components shown in Figure 3.
+5
6
IS
+5
6
15
+5
7
IS
+5
7
IS
±1/4
±V4
LOGIC INPUTS
CS,RD
VINL, Input Low Voltage
VINH , Input High Voltage
lIN, Input Current
25°C
Tmio to Tmax
ClN , Input Cspscitance3
CLK
VINL, Input Low Voltage
V,NH, Input High Voltsge
IINL,lnputLowCurrent
IINH, Input High Current
LOGIC OUTPUTS
BUSY, DBO to DB7
VOL, Output Low Voltage
VOH, Output High Voltage
DBOtoDB7
Flosting Stste Leskage Current
Fiosting Stste Output Cspacitsnce3
CONVERSION TIME"
With External Clock
With Internal Clock, TA = 250C
POWERREQUIREMENTS s
Voo
100
Power Dissipation
Power Supply Rejection
±v.
±v.
NOTES
ITemperature Ranges are as fonows:
J,KVersioDS; Oro +7O"C
A, B Versions; -25"C to +8S"C
S, T Versions; - SS"C to + lZS"C
Wset error is measured with respect to an ideal fust code transition which occurs at 1I2LSB.
3Sample tested at 2S"C to ensure compliance.
4Accuracy may degrade at conversion times other than those specified.
'Power supply current is measured when AD7575 is inactive i.e. when CS - RD - BUSY -logic HIGH.
Specifications subject to change without notice.
3-266 ANALOG-TO-OIGITAL CONVERTERS
J.Lsmin
"..max
Volts
mAmax
mWtyp
LSBmax
:t5%
VIN=OorVoo
VIN =:90rVoo
± 5% for Specified Performance
Typically 3mA with Voo= + 5V
4.75V,,;Voo,,;5.25V
AD7575
ABSOLUTE MAXIMUM RATINGS·
VooTOAGND
VooTODGND • . . . . . . .
AGND TO DGND . . . . . . .
Digital Input Voltage to DGND
Digital Output Voltage to DGND
CLK Input Voltage to DGND
VREF to AGND . . . . . . . .
AINTOAGND . . . . . • .
Operating Temperature Range
Commercial, (J, K Versions)
Industrial (A, B Versions)
Extended (S, T Versions)
Storage Temperature Range . . . . . . . . . -65°C to + 150°C
Lead Temperature (soldering, 10sec) . . . .
+ 300°C
Power Dissipation (Any Package) to + 75°C
450mW
Derates above 75°C by . . . . . . . . . . .
6mWrC
-O.3V, +7V
-O.3V, +7V
-O.3V, Voo
-O.3V, Voo +O.3V
-O.3V, Voo +O.3V
-O.3V, Voo +O.3V
-O.3V,Voo
-O.3V, Voo
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
o to +70°C
- 25°C to + 85°C
- 55°C to + 125°C
CAUTION
ESD (electrostatic discharge) sensltJve device. The digital control inputs are diode p(otected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
PIN CONFIGURATIONS
DIP
LCCC
~ I~
Voo
3
2
V REF
AIN
1
J
20 I.
..
00
00
BUSY 4
AGNO
If) .}
PLCC
eLK 5
(Not to Scale)
15 DB1
DB7 (MSB)
7
DB6
8
14 082
DBS •
DB2
AGNO
AD7575
16 080 (LSB)
TOPVfEW
DB6 7
OBI
17 AGND
AD7575
087 (MSB) 6
DBD fLSB)
•
NC
"
= NO CONNECT
TRACK·AND·HOLD
The on-chip track-and-hold on the AD7575 means that input
signals with slew rates up to 386mV//1s can be converted without
error. This corresponds to an input signal bandwidth of 50kHz
for a 2.46V peak-to-peak sine wave. Figure 1 shows a typical
plot of signal-to-noise ratio versus input frequency, over the
input bandwidth of the AD7575. The SNR figures are generated
using a 200kHz sampling frequency and the reconstructed sine
wave passes through a fIlter with a cutoff frequency of 50kHz.
40
42
T= 25°C
o
,...-1-
-.......
~
The improvement in the SNR figures seen at the higher frequencies
is due to the sharp cut-off of the fIlter (50kHz, 8th order Chebyshev)
used in the test circuit.
The input signal is held on the third falling edge of the input
clock after CS and RD go LOW. This is indicated in Figure 2
for the Slow Memory Interface. In between conversions the
input signal is tracked by the AD7575 track-and-hold. Since the
sampled signal is held on a smaIl, on-chip capacitor it is advisable that the data bus be kept as quiet as possible during a
conversion.
.........
\
EXTERNAL
52
54
= NO CONNECT
RD~L__________________~)~__________--'
!lj46
V
Ne
~~~--------~$~~$----~
44
50
OBI
DB2
10 11 12 13
u u
iii
z z z :;
a a
a
~ 48
ORO (LSB)
a
DBO
a:
TOP VIEW
(Not to Scale)
CLOCK
100
'k
'Ok
INPUT FREQUENCV - Hz
Figure 1. SNR vs. Input Frequency
100k
INPUT SIGNAL
HELD HERE
Figure 2. Track-and-Hold (Slow Memory Interface) with
External Clock
ANALOG-TO-DIGITAL CONVERTERS 3-267
II
Unipolar/Bipolar Considerations
UNIPOLAR OPERATION
The basic operation for the AD7S7S is in the unipolar single
supply mode. Figure 3 shows the circuit connections to achieve
this while the nominal transfer characteristic for unipolar operation
is given in Figure 4. Since the offset and full-scale errors on the
AD757S are very small, in many cases it will not be necessary to
adjust out these errors. If calibration is required the procedure
is as follows:
Offset Adjust
Offset error adjustment in single-supply systems is easily achievable
by means of the offset null facility of an op-amp when used as a
voltage follower for the analog input signal, AIN. The op-amp
chosen should be able to operate from a single supply and allow
a common-mode input voltage range that includes OV (e.g.,
TLC271). To adjust for zero offset the input signal source is set
to +4.8mV (i.e., 1I2LSB) while the op-amp offset is varied
until the ADC output code flickers between 000 ... 00 and
000 ..• 01.
Full Seale Adjust
The full scale or gain adjustment is made by forcing the analog
input AIN to +2.445V (Le., Full-Scale Voltage -3/2LSB).
The magnitude of the reference voltage is then adjusted until
the ADC output code flickers between III ... 10 and
111 ... 11.
+5V
BIPOLAR OPERATION
The circuit of Figure 5 shows how the AD7575 can be configured
for bipolar operation. The output code provided by the AD7S7S
is offset binary. The analog input voltage range is ± SV, although
the voltage appearing at the AIN pin of the AD7575 is in the
range OV to +2.46V. Figure 6 shows the transfer function for
bipolar operation. The LSB size is now 39.06mV. Calibration of
the bipolar operation is outlined below. Once again, because the
errors are small it may not be necessary to adjust them. To
maintain specified performance without the calibration all resistors
should be 0.1% tolerance with R4 and RS replaced by one 3.3kn
resistor and R2 and R3 replaced by one 2.5kn resistor.
Offset Adjust
Offset error adjustment is achieved by applying an analog input
voltage of - 4. 980SV ( - FS/2 + 1I2LSB). Resistor R3 is then
adjusted until the output code flickers between 000 ... 00 and
000 ... 01.
Full Seale Adjust
Full scale or gain adjustment is made by applying an analog
input voltage of +4.9414V (+FS/2 -3/2LSB). Resistor R4 is
then adjusted until the output code flickers between 111 ... 10
and III ... 11.
+.v.....,......._ ....._ - ,
+.v
- " f - - -.....- - - - ,
Ro"
100kU,1%
+5V
RCLK
100kn,1%
DB7-DBO
DATA OUT
AD589
D87-080
DATA OUT
Figure 5. AD7575 Unipolar Configuration
OUTPUT
Figure 3. AD7575 Unipolar Configuration
OUTPUT
CODE
FUUSCALE
'11"'0'
i
I
I
I
I
11'···110
_/8mo\
:::::::1
""""~iOOE
100--010
100---001
_ FS
.00-..... l--i2--.,~~--t-I----\~....,.=-'--_AIN
tp-1LSB
,
,,"
011-·-111
'
011···110
=::i
,r"
=~-----o1LSBIZLSB'S 3LS8'S
I
FS
= 10V
.LS.
=
J!&
LI ~I -1LSB
.
AIN. INPUT VOLTAGE lIN TERMS OF LS.·SI
Figure 4. Nominal Transfer Characteristic for
Unipolar Operation
3-268 ANALOG-TO-DIGITAL CONVERTERS
Figure 6. Nominal Transfer Characteristic for
Unipolar Operation
11IIIIIIII
LC 2MOS
10....5 ....PCompatible 8-BitADC
AD7576 I
ANALOG
WDEVICES
AD7576 FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single + 5V Operation with External Positive
Reference
Fast Conversion Time: 10jl.S
No Missed Codes Over Full Temperature Range
Microprocessor Compatible
Low Cost
Low Power 115mW)
100ns Data Access Time
Voo
•
GENERAL DESCRIPTION
The AD7576 is a low cost, low power, microprocessor compatible
8-bit analog-to-digital converter, which uses the successive
approximation technique to achieve a fast conversion time of
IOfLS. The device is designed to operate with an external reference
of + 1.23V (standard bandgap reference) and converts input
signals from OV to 2VREF •
The part is designed for ease of microprocessor interface with
three control inputs (CS, RD and MODE) controlling all ADC
operations such as starting conversion and reading data. The
interface logic allows the part to be easily configured as a memory
mapped device. All data outputs use latched, three-state output
buffer circuitry to allow direct connection to a microprocessor
data bus or system input port. The output latches serve to make
the conversion process transparent to the microprocessor.
The part is designed for single + 5V operation, has on-board
comparator, interface logic, and internaVexternal clock option.
This makes the AD7576 ideal for most ADClIJ.P interface
applications.
The AD7576 is fabricated in an advanced, all ion-implanted
high speed Linear Compatible CMOS (LC2MOS) process and is
available in either a small, 0.3" wide, I8-pin DIP or in 20-terminal
surface mount packages.
PRODUCT HIGHLIGHTS
I. Single Supply Operation
Operation from a single + 5V supply with a + 1.23V reference
allows operation of the AD7576 with microprocessor systems
without any additional power supplies.
2. Low Power
CMOS fabrication of the AD7576 results in a very low power
dissipation figure of I5mW typical.
3. Versatile Interface Logic
The AD7576 can be configured to perform continuous conversions or to convert on command. It can be interfaced as
SLOW-MEMORY or ROM, allowing versatile interfacing to
most microprocessors.
4. Fast Conversion Time
The fabrication of the AD7576 on Analog Devices' Linear
Compatible CMOS (LC2MOS) process enables fast conversion
times of IOlJ.s, eliminating the need for expensive Sample-andHolds in many low frequency applications.
ORDERING INFORMATIONl
Relative
Accuracy
(LSB)
Temperature Range and Package Options2
Oto +70"C
- 25"<: to + 85°C
Plastic DIP (N-18)
Hermetic DIP (Q-18) Hermetic DIP (Q-18)
±I
± 112
AD7576JN
AD7576KN
AD7576AQ
AD7576BQ
PLCC3 (P-20A)
LCCC4 (E-20A)
±I
± 112
AD7576JP
AD7576KP
AD7576SE
AD7576TE
- 55°C to + 125°C
AD7576SQ
AD7576TQ
NOTES
ITo order MIL-STD-883, Class B processed parts, addI883B to pan number.
Contact your local sales office for military data sheet.
'See Section 14 for package outline information.
'PLCC: Plastic Leaded Cbip Carrier.
4LCCC: Leadless Ceramic Cbip Carrier.
ANALOG-TO-DIGITAL CONVERTERS 3-269
= + 5Y; V = + 1.23V; AGND = DGND = OV; fcut = 21111z axlemal;
T... to T.... ooless oIIIelWisa nobId.)
SPECIFICATIONS AI spacificatiolls
(Vuo
Parameter
ACCURACY
Resolution
Totsl Unadjusted Error
Relative Accuracy
Minimum Resolution for which
No Missing Codes is Guaranteed
Full Scale Error
2So(;
TmiatoTmax
REF
I,A'
K,B
Versions
Versions
SVersion
8
±2
±1
±I
±2
±1
±Yz
8
TVersion
Units
8
±1
±~
Bits
LSBmax
LSBmax
8
Bits max
Conditions/Comments
±1
±1
±1
±1
±1
±1
±I
±1
LSBmax
LSBmax
Full Scale TC is typically Sppml"C
±~
±~
±~
±~
±~
±~
±~
LSBmax
LSBmax
Offset TC is typically Sppmt'C
±~
Oto2VREF
10
Oto2VREF
10
Volts
M!lmin
lLSB = 2VRE p/256; See Figure 4
±S%
Offset Error
2So(;
Tmin to Tmax
ANALOG INPUT
Voltage Range
DClnput Impedance
Oto2VREF
10
REFERENCE INPUT
V REF (For specified Performance)
IREF
1.23
1.23
1.23
1.23
SOO
SOO
SOO
SOO
Volts
fL1\max
0.8
2.4
0.8
2.4
0.8
2.4
0.8
2.4
V max
V min
±I
±IO
±I
±IO
±1
±10
C IN , Input Capacitance'
10
10
10
±I
±1O
10
fL1\max
fL1\max
pFmax
CLK
V INL, Input Low Voltage
VINH , Input High Voltage
IINL, Input Low Current.
IINH, Input High Current
0.8
2.4
700
700
0.8
2.4
700
700
0.8
2.4
800
800
0.8
2.4
800
800
V max
V min
f!.Amax
f!.Am.,.
VINL=OV
VINH=VOO
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
V max
V min
ISINK = 1.6mA
IsoURCE= 4Of!.A
±I
10
±1
10
±1O
10
±1O
10
f!.Am.,.
pFmax
VOUT=OtoVoo
10
10
10
10
10
30
30
30
10
10
30
f!.s
10
fcLK= 2MHz
Using recommended clock
components shown in Figure 3.
+5
LOGIC INPUTS
CS,RD,MODE
V INL, Input Low Voltage
VINH, Input High Voltage
lIN, Input Current
2So(;
TmintoTmax
LOGIC OUTPUTS
BUSY, DBO to DB7
VOL> Output Low Voltage
VOH, Output ~h Voltage
DBOtoDB7
Floating State Leakage Current
Floating State Output Capacitance'
CONVERSION TIME'
With External Clock
With Internal Clock, T A = 2SoC
POWER REQUIREMENTS'
VOD
Oto2VREF
10
100
6
+S
6
+S
+S
IS
7
IS
7
IS
Power Dissipation
Power Supply Rejection
IS
±V4
±1/4
±V4
±V4
NOTES
ITemperature Ranges are as follows:
J, K Versions; 0 to +7O"C
A, B Versions; - 2S"C to + 85°C
S. T Versions; - 5S"C to + 125"C
20ffset error is measured with respect to an ideal first code transition which occurs at 1/2LSB.
3Sampie tested at 25"C to ensure compliance.
'Accuracy may degrade at conversion times other than those specified.
5Power supply current is measured when AD7576 is inactive i.e. when CS =RD:;;:MODE = BUSY = logic HIGH.
Specifications subject to change without notice.
3-270 ANALOG-TO-DIGITAL CONVERTERS
J.l.smin
f!.Smax
Volts
mAmax
mWtyp
LSBmax
VIN=OorVoo
VIN=OorVoo
± S% for Specified Performance
Typically 3mA with Voo '" + SV
4.75VsVoosS.2SV
AD7576
ABSOLUTE MAXIMUM RATINGS·
VooTOAGND
VooTODGND
AGNDTODGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
CLK Input Voltage to DGND
VREF to AGND . . . . . . . .
AINTOAGND . . . . . . .
Operating Temperature Range
Commercial (1, K Version)
Industrial (A, B Version)
- 25°C to + 85°C
Extended (S, T Version)
- 55°C to + 125°C
Storage Temperature Range
-65°C to + 1500C
Lead Temperature (soldering, 10 sees)
. . . • . . 300°C
Power Dissipation (Any Package) to +75°C . . . . . 450mW
Derates above 75°C by . . . . . . . . . . . . . . . 6mWrC
-O.3V, +7V
-0.3V, +7V
-0.3V, Voo
-0.3V, Voo +O.3V
-0.3V, Voo +0.3V
-O.3V, Voo +0.3V
-0.3V, Voo
-0.3V, Voo
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
. 0 to +70"C
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEV'CE
PIN CONFIGURATIONS
DIP
LCCC
l!I
va.
B!
I~
J
2
1
2.
3
V,..,
A1N
BUSV
AGND
..
DB6 1
DB2
DaS 8
,.
,.
,.
(Not to Scale)
DBO (LSB)
DB1
AGND
DBO (LSB)
DBl
DB2
,.
11
12
13
I>
is
z
I>
"Z
O!
Q
i3
Q
•
8
A SAMPLED-DATA INPUT
The AD7576 makes use of a sampled-data comparator. The
equivalent input circuit is shown in Figure I. When a conversion
starts, switch S I is closed and the equivalent input capacitance
is charged to VIN. With a switch resistance of typically 5000
and an input capacitance of typically 2pF the input time constant
is Ins. Thus CIN becomes charged to within ± V. LSB in 6.9
time constants or about 7ns. Since the comparator switches are
operating at one half the input clock frequency of 2MHz, there
is ample time for the input voltage to settle before the comparator
decision is made (at the end of a clock period). Increasing the
source resistance increases the settling time required. Input
bypass capacitors placed directly at the analog input act to average
the input charging currents. This average current flowing through
any source impedance can cause full-scale errors.
,.
DB2
11 12 13
NO CONNECT
20
1
AIN
i3
a\ I>
z l;! I>
z "
=
J J
2
AD7576
TOP VIEW
(Not to Scale)
I>
Ne
I~ l;!
0
17 AGND
• ,.
DB.
3
18 AIN
AD7576
TOP VIEW
IMSS) 087 6
DBl
,.J
00
00
4
eLK 5
DBO ILSB}
PLCC
lfi!
Ne
= NO CONNECT
"
I>
REFERENCE INPUT
The reference input impedance on the AD7576 is code dependent
and varies by a ratio of approximately 3-to-1 over the digital
code range. The typical resistance range is from 6kO to 18kO.
As a result of the code dependent input impedance, the VREF
input must be driven from a low impedance source. Figure 2
shows how an AD589 can be configured to produce a nominal
reference voltage of + 1.23V.
+5V
3.3kH
+
AD589
oo-c-.-r. . . - . . .
RON. 50011
VON
N
........_
•. 5 PF ¢
51
......,.,AOO---,l
2PF~
Figure 2. Reference Circuit
Figure 1. AD7576 Equivalent Input Circuit
ANALOG-TO-DIGITAL CONVERTERS 3-271
II
Unipolar/Bipolar Considerations
UNIPOLAR OPERATION
The basic operation for the AD7576 is in the unipolar single
supply mode. Figure 3 shows the circuit connections to achieve
this while the nominal transfer characteristic for unipolar operation
is given in Figure 4. Since the offset and full-scale errors on the
AD7576 are very small, in many cases it will not be necessary to
adjust out these errors. If calibration is required the procedure
is as follows:
Offset Adjust
Offset error adjustment in single-supply systems is easily achievable
by means of the offset null facility of an op-amp when used as a
voltage follower for the analog input signal, AIN. The op-amp
chosen should be able to operate from a single supply and allow
a common-mode input voltage range that includes OV (e.g.,
TLC271). To adjust for zero offset the input signal source is set
to +4.8mV (i.e., 1I2LSB) while the op-amp offset is varied until
the ADC output code flickers between 000 ..• 00 and
000 .•. 01.
Full Scale Adjust
The full scale or gain adjustment is made by forcing the analog
input AIN to +2.445V (i.e., Full-Scale Voltage -3/2LSB). The
magnitude of the reference voltage is then adjusted until the
ADC output code flickers between III ... 10 and III ... 11.
+SV -
BIPOLAR OPERATION
The circuit of Figure 5 shows how the AD7576 can be configured
for bipolar operation. The output code provided by the AD7576
is offset binary. The analog input voltage range is ± 5V, although
the voltage appearing at the AIN pin of the AD7576 is in the
range OV to + 2.46V. Figure 6 shows the transfer function for
bipolar operation. The LSB size is now 39.06mV. Calibration of
the bipolar operation is outlined below. Once agsin, because the
errors are small it may not be necessary to adjust them. To
maintain specified performance without the calibration all resistors
should be 0.1% tolerance with R4 and R5 replaced by one 3.3kO
resistor and R2 and R3 replaced by one 2.5kO resistor.
Offset Adjust
Offset error adjustment is achieved by applying an analog input
voltage of -4.9805V (- FS/2 + 1/2LSB). Resistor R3 is then adjusted
until the output code flickers between 000 .•. 00 and
000 ... 01.
Full Scale Adjnst
Full scale or gain adjustment is made by applying an analog
input voltage of +4.9414V (+FS/2 -3/2LSB). Resistor R4 is then
adjusted until the output code flickers between III •.. 10 and
III ... 11.
....- - . . . . . , - - - - - ,
+sv
~.,.,.
ADS"
DB7-DBD
DATA OUT
Figure 5. AD7576 Bipolar Configuration
Figure 3. AD7576 Unipolar Configuration
OUTPUT
CODE
RJLLSCALE
_/NS~\
::::::::1
"'· ·"~lDE
111-110
100---010
"",,",f
100-001
I
I
I
I
,
'
"
'00-000 I-T--.;~---t-t---"T-=-'----' AIN
+~
FS=2VREI'
'LSB=;'
------ I
01LS82LSB'S 3LSB'S
011--110
I
-1LSB
011---"1
=::{LI
"
.......,
oooooooo
OUTPUT
FS= 10V
'LSB=~
I.
L~-1LSB
AIN. INPUT VOLTAGE (IN TERMS OF LSB'S)
Figure 4. Nominal Transfer Characteristic for
Unipolar Operation
3-272 ANALOG-TO-DIGITAL CONVERTERS
Figure 6. Nominal Transfer Characteristic for
Bipolar Operation
CMOS
12-Bit Successive Approximation ADC
AD7578 I
r-IIANALOG
WDEVICES
AD7S78 FUNCTIONAL BLOCK DIAGRAM
FEATURES
12-Bit Successive Approximation ADC
No Missed Codes Over Full Tempereture Range
Low Total Unadjusted Error :t1LSB max
High Impedance Analog Input
Autozero Cycle for Low Offset Voltage
Low Power, 75mW typ
Small Size: 0.3", 24-Pin Package
Conversion Time of 1oop.s
CAZ
V DD
Vss
Vee
DATA
OUT
GENERALDESCR~ON
The AD7578 is a medium speed, monolithic 12-bit CMOS AID
converter which uses the successive approximation technique to
provide a conversion time of 100",•. An auto-zero cycle occurs
at the stsrt of each conversion resulting in very low system
offset voltages, typically less than 100",V. The device is designed
for easy microprocessor interfacing using standard control signals;
CS (decoded device address), RD (READ) and WR (WRITE).
Conversion results are available in two bytes, 8LSBs and 4MSBs,
over an 8-bit three state output bus. Either byte can be read
first. Two converter busy flags are available to facilitate polling
of the converter's status.
The analog input voltage range is OV to + 5V when using a
reference voltage of + 5V.
AD Ci Wii
BYSL
DGND
PRODUCT HIGHLIGHTS
1. The AD7578 is a complete 12-bit AID converter in a 24-pin
package requiring only a few passive components and a voltage
reference.
2. Autozero cycle realizes very low offset voltages, typically
l00",V.
3. Standard microprocessor control signals to allow easy interfacing to most popular 8- and 16-bit microprocessors.
4. Monolithic construction for increased reliability and small
0.3", 24-pin DIP.
ORDERING INFORMATION l
Total
Unadjusted
Error
T..,;,,-Tmax
±lLSB
Temperature Range and Package Options2
Oto +70·C
- 2S·C to + 8S"C
- SS·C to + 12S·C
Plastic (N-24)
Hermetic3 (D-24A)
Hermetic3 (D-24A)
AD7578KN
AD7578BD
AD7578TD
NOTES
ITo order MIL·STD-883, Class B processed parts, addI883B to part number.
Contact your local sales office for military data sheet.
2See Section 14 for package outline information.
3Analog Devices reserves the right to ship either ceramic (D·24A) or cerdip (Q-24) hermetic packages.
ANALOG-TO-DIGITAL CONVERTERS 3-273
SPECIFICATIONS
(VIII =
+ 15V, Vcc= +5V, Vss= -5V, VREF = +5.OV
fCUI = 140kHz external, all specifications Tmil to T.... unless otherwise noted).
Parameter
KVersion'
BVersion'
TVersion'
Units
Conditions/Comments
ACCURACY
Resolution
Total Unadjusted Error
Differential Nonlinearity
Full Scale Error (Gain Error)
Offset Error
12
±I
±I
± 1/4
± 1/4
12
±I
±I
± 1/4
± 1/4
12
±I
±I
± 1/4
± 1/4
Bits
LSBmax
LSBmax
LSBmax
LSBmax
No missing codes guaranteed
Full Scale TC is typically I ppml"C
Offset Error TC is typically IppmrG
Oto +5
8
Oto +5
8
Oto +5
8
V
pFiyp
10
100
10
100
10
100
nAmax
nAmax
REFERENCE INPUT
VREP (For Specified Performance)
VREpRange
VREP Input Reference Current
+5
+4to +6
1.0
+5
+4to +6
1.0
+5
+4to +6
1.0
V
V
mAmax
±5%
Degraded transfer accuracy
VREP = +5.0V
POWER SUPPLY REJECTION
VooOnly
± 1/8
± 1/8
±1/8
LSBtyp
± 1/8
± 1/8
±1/8
LSBtyp
Voo= + 14.25Vto + 15.75V
Vss= -5V
Vss= -4.75Vto -5.25V
Voo= +15V
+0.8
+2.4
+0.8
+2.4
+0.8
+2.4
V max
V min
Vcc= +5V ±5%
±I
+10
10
±I
+10
10
±I
+10
10
",A max
",A max
pFmax
VIN=OtoVcc
+0.8
+3.0
±IO
+1.5
+0.8
+3.0
±IO
+ 1.5
+0.8
+3.0
±IO
+ 1.5
V max
V min
",A max
mAmax
Vcc= +5V ±5%
ANALOG INPUT
Analog Input Range
CAIN, Input Capacitance
lAIN, Input Leakage Current
+ 25°C
Tminto Tmax
VssOnly
LOGIC INPUTS
RD(pin 16), CS(Pin 17), WR(Pin 18)
BYSL(Pin 19)
V'L Input Low Voltage
VIH Input High Voltage
lIN Input Current
+25°C
TmintoTmax
CIN Input Capacitance'
CLK(Pin21)
VIL , Input Low Voltage
VIH, Input High Voltage
IlL, Input Low Current
IIH, Input High Current
VREP = +5.0V
AIN;Oto +5V
LOGIC OUTPUTS
DBO-DB7 (Pins S-15), BUSY (Pin 20)4
VOL, Output Low Voltage
VOH , Output High Voltage
Floating State Leakage Current
(PinsS-15)
Floating State Output Capacitance
+0.4
+4.0
+0.4
+4.0
+0.4
+4.0
V max
V min
Vcc= +5V ±5%,IsINK = 1.6mA4
Vcc= +5V ±5%, l soURcE = 2oo",A
±I
IS
±I
IS
±I
IS
..,A max
pFmax
VoUT=OVtoVcc
CONVERSION TIMES
With External Clock
With Internal Clock, T A= + 25°C
100
100/150
100
1001150
100
100/150
",smin
",sminlmax
feLK = 140kHz
Using recommended clock components
as shown in Figure 6.
+15
-5
+5
7.5
7.5
100
1.0
75
+15
-5
+5
7.5
7.5
100
1.0
75
+15
-5
+5
7.5
7.5
100
1.0
75
V NOM
V NOM
V NOM
mAmax
mAmax
",Atyp
mAmax
mWtyp
± 5% for specified performance
± 5% for specified performance
± 5% for specified performance
Typically4mAwith Voo= + 15V
Typically 3mA with Vss = - 5V
VIN=VILorVIH
POWERREQUIREMENTS6
Voo
Vss
Vcc
100
Iss
Icc
Power Dissipation
NOTES
'Temperature Range as follows: K Version; 0 to + 700C
B Version; - 2S"C to + 8S"C
TVersioD; - SSOCto+ 125"<:
2lncludes Full Scale Error, Offset Error and Relative Accuracy.
3Sample tested to ensure compliance.
'ISINK for BUSY (pin 20) is 1.0 milliamp.
sConversion Time includes autozero cycle time.
6Power supply current is measured when AD7S78 is inactive i.e., WR = RD =CS = BUSY = Logic HIGH.
Specifications subject to change without notice.
3-274 ANALOG"TO-DIGITAL CDNVERTERS
WR=RD= CS= BUSY= Logic HIGH
AD7578
TIMING SPECIFICATIONSl lY. = + 15V,V.. = +5V,V.= -5V,V.,=+5Vl
Parameter
t1
tz(INTi
tz(EXTi
t3
4
ts
~
t7
t8
t9
tlO
t1l 3
t1z4
Limit at + 25°C
(AU Grades)
Limit at T miD. T max Limit at T miD. T max
(K&BGrades)
(TGrade)
Units
0
200
0
240
10
0
160
250
0
0
240
0
50
0
180
240
20
160
10
0
130
200
0
0
200
0
50
0
150
200
20
130
0
280
10
0
200
300
0
0
280
0
50
0
200
280
20
180
Conditions/Comments
CS to WR Setup Time
WR Pulse Width (IntemalClock Operation)
WR Pulse Width (External Clock Operation)
CS to WR Hold Time
nsmin
nsmin
fLsmin
nsmin
nstyp
nsmax
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nstyp
nsmax
nsmin
nsmax
WR to BUSY Propagation Delay
BUSY to CS Setup Time
CS to RD Setup Time
RD Pulse Width
CS to RD Hold Time
BYSL to RD Setup Time
BYSL to RD Hold Time
RD to Valid Data (Bus Access Time)
RD to Three State Output
(Bus Relinquish Time)
NOTES
'Timing Specifications are sample tested at + 2S"C to ensure compliance. All input control signals are
specified with t, = tf = 20ns (Ul"A. to 90% of + SV) and timed from a voltage level of + 1.6V. Data is timed from
VOH,VOL •
'When using an external clock source the WR pulse width must be extended to provide the minimum
auto-zero cycle time of 10..... See "External Clock Operation".
'til is measured with the load circuits of Figure 3 anddefmed as the time required for an output to cross 0.8V or 2.4V.
4t12 is defmed as the time required for the data lines to crumge o. SV when loaded with the circuits of Figure 4.
Specifications subject to change without notice.
cs (PIN 171
t,
t,
t.
WRIPIN 18)
~
\
BUSY (PIN 20)
NOTES
THE TWO-BYTE CONVERS!Q..N R§ULT CAN BE READ IN EITHER ORDER. FIGURE IS FOR LOW BYTE. HIGH BYTE ORDER.
IF 8VSl CHANGES WHILE CS" RD ARE LOW THE DATA WILL CHANGE TO REFLECT THE BVSL INPUT.
Figure 1. Start Cycle Timing
Figure 2. Read Cycle Timing
sv
DBNr-J:
3'~___ ~ lOOpF
DGND
a. High-Z to VOH
sv
~3k
DBNT
~'OOPF
DGND
b. High-Z to VOL
Figure 3. Load Circuits for Access Time Test (t l1 )
DBNT.-r:
~3: __~'OPF
DGND
a. VOH to High-Z
~ 3.
DBN+
IOpF
JDGND
b. VOL to High-Z
Figure 4. Load Circuits for Output Float Delay Test (t I2)
ANALOG-TO-DIGITAL CONVERTERS 3-275
II
ABSOLUTE MAXIMUM RATINGS*
(TA = + 25°C unless otherwise stated)
VDDto DGND .
Vss to DGND ..
AGND to DGND
Vee to DGND
VREF to AGND .
AINtoAGND .
Digital Input Voltage to DGND
(Pins 16-19, 21) . . . . . . .
Digital Output Voltage to DGND
(Pins 8-15, 20) . . . . . . . .
. . . . -O.3V, +17V
. . . . +0.3V, -7V
-O.3V, VREF +O.3V
-O.3V, VDD +O.3V
-0.3V, VDD +0.3V
-0.3V, VDD +0.3V
-0.3V, VDD +O.3V
-O.3V, VDD +O.3V
Operating Temperature Range
Commercial (K Version)
Industrial (B Version) .
Extended (T Version) ..
Storage Temperature . . .
Lead Temperature (Soldering, lOsecs)
Power Dissipation (Any Package)
to +75°C . . . . . . . . . . . . . .
Derate above + 75°C by
v,.
NC
BYSL
WR
os
AD
OBS
DBO (LSB)
DB1
NC
= NO CONNECT
I,OOOmW
lOmWrC
*Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
DIP PIN CONFIGURATION
. . . 0 to +70°C
- 25°C to + 85°C
- 55°C to + 125°C
- 65°C to + 150°C
. +300°C
0
WARNING!
~~DEVICE
-
-
READING DATA
The 12-bit conversion data plus a converter status flag are available
over an 8-bit wide data bus. Data is transferred from the AD7578
in right-justified format (i.e., the LSB is the most right-hand bit
in a 16-bit word). Two READ operations are required, the Byte
Select (BYSL) input determining which byte-8 least significant
bits or 4 most significant bits plus status flag-is to be read first.
Since the AD7578 uses the successive approximation register
(SAR) to hold conversion results (refer to Functional Diagram),
it is necessary to wait until a conversion is finished before reading
valid 12-bit data. Executing a READ instruction (HIGH or
LOW byte) to the AD7578 while a conversion is in progress
will place the existing contents of the SAR onto the data bus.
Three different approaches can ensure valid 12-bit data is available
for reading.
1. Insert a software delay greater than the ADC conversion time
between the conversion start instruction and the data read
instructions.
2. At user-defmed intervals after a conversion start instruction,
poll the internal converter status flag, BUSY. This signal is
available on pin 10 during a HIGH byte READ instruction
and is the most left-hand bit in a 16-bit right-justified word.
The status bit can be shifted into a microprocessor's accumulator-carry position for testing (BUSY is HIGH during
conversion).
3. Use the externa1ly available BUSY (pin 20) signal as an interrupt
to the microprocessor. This signal is LOW during a conversion
and returns HIGH at conversion end.
Executing a WRITE instruction to the AD7578 while a conversion
is in progress will restart the conversion.
3-276 ANALOG-TO-DIGITAL CONVERTERS
AD7578
PIN FUNCTION DESCRIPTION
PIN
2
MNEMONIC
DESCRIPTION
CAZ
Autozero Capacitor Input. Connect other side of capacitor to AGND.
AIN
Analog Input
No Connect pin
3
N/C
4
VREF
Voltage reference input. TheAD7S7Sisspecified with VREF =
S
AGND
Analog Ground
6
DGND
Digital Ground
7
Va:.
+ S.OV.
Logic Supply. For Va:. = + SV digital inputs and outputs are TIL compatible.
Three state data outputs. They become active when CS & RD are brought low. Individual pin function
is dependent upon the Byte Select (BYSL) input.
S-IS
-
DATA BUS OUTPUT CS & RD - LOW
BYSL= ffiGH
BYSL=LOW
PinS
BUSY'
DB7
Pin 9
LOW2
DB6
PinlO
LOW2
DBS
Pin 11
LOW2
DB4
Pin 12
DB 11 (MSB)
DB3
Pin 13
DBI0
DB2
Pin 14
DB9
DBI
Pin IS
DBS
DBO(LSB)
I BUSY (Pin 8) is a converter status fIas and is HIGH during a conversion.
2Pias 9-11 output a logic LOW when BYSL is HIGH.
DBII-DBOaretbe 12-bitconversionresults, DB II is the MSB.
16
READ input. This active LOW signal, in combination with CS, is used to enable the output data threestate drivers.
17
CHIP SELECT Input. Decoded device address, active LOW. Used in combination with either RDor
WR for control.
IS
WRITE Input. This active LOW
When the AD7S7S internal clock
external clock source is used, the
autozero cycle time. For external
19
BYSL
BYTE SELECT. This control input determines whether the high or low byte of data is placed on
the output data bus during a data READ operation (CS & RD LOW). See description of pins SIS.
BUSY indicates converter status. BUSY is LOW during conversion, otherwise BUSY is held at a
logic HIGH.
20
21
signal, in combination with. CS, is used to start a new conversion.
is used, the minimum WR pulse width is t2 (INT). When an
minimum WR pulse width must be extended to include the
clock operation, the minimum WR pulse width is t2 (EXT).
CLK
CLOCK Input for internal/external clock operation.
Internal: Connect RcLK and CcLK,/CcLK2 timing components. See Figure 6 and Figure 7.
External: Connect external 74HC compatible clock source as shown in Figure S.
22
N/C
No connect pin.
23
Vss
Negativesupply, -SV.
24
Voo
Positivesupply,
+ ISV.
ANALOG-TO-DIGITAL CONVERTERS 3-277
E
Operating Information
OPERATIONAL DIAGRAM
An operational diagram for the AD7578 is shown in Figure 5.
The only passive components required are the autozero capacitor
C AZ and timing components Rcuc, Ccr.Kl & Ccua for the
internal clock oscillator. H the AD7578 is to be used with an
external clock source, then only CAZ is required. Individual pin
functions are deacribed in detail on the previous page.
Figure 5. AD7578 Operational Diagram
INTERNAL CLOCK OPERATION
The clock circuitry for internal clock operation is shown in
Figure 6 and the AD7578 operating waveforms are shown in
Figure 7.
Vee. +5V
_0.2%
IN914 2a:f=2%
Between conversions (BUSY = HIGH) the AD7578 is in the
autozero cycle. When WR goea LOW (with CS LOW) to start a
new conversion, the autozero capacitor CAZ charges to AIN Vos where Vos is the input offset voltage of the autozero
comparator.
A minimum time of lOlLS is required for this autozero cycle. In
applications using the internal clock oscillator, it is not necessary
for WR to remain LOW for this period of time since it is automatically provided by the AD7578. This is achieved by switching
a constant current load across the clock capacitors, Ccr.Kl and
CcLK2, causing the voltage at the CLK input pin to slowly
decay from Vee. This occurs after WR returns HIGH. The
Schmitt trigger circuit monitoring the voltage on the CLK input
ends the autozero cycle when its LOW input trigger level is
reached. At this point, the constant current load across the
clock capacitors is removed allowing them to charge towards
Vee via Rcr.K. When the voltage at the CLK input reaches the
HIGH trigger level, the constant current load is replaced across
Ccr.Kl and CcLK2. The MSB decision is made when the LOW
trigger level is reached. This cycle repeats itself 12 times to
provide 12 ciock pulsea for the conversion cycie. The circuit
arrangement of Figure 6 provides the relatively slow autozero
cycle time at the beginning of a conversion while allowing the
clock oscillator to speed up once the autozero cycle is complete.
EXTERNAL CLOCK OPERATION
For external clock operation Rcr.K, Ccr.Kl and Ccr.K2 are discarded
and the CLK input is driven from a 74HC compatible clock
source. The AD7578 WR pulse width must now be extended to
provide the minimum autozero cycle time of lOlLS since this is
no longer provided automatically by the AD7578. Referring to
the operating waveforms of Figure 9, the minimum WR pulse
width when using an external clock source is t2 (EXT). The CS
input must now remain valid for the extended WR pulse width.
It is not neceasary to synchronize the external clock source with
the extended WR pulse width, the MSB decision being made on
the second falling edge of the clock input after the WR input
returns HIGH.
74HC COMPATIBLE
CLOCK SOURCE,
fCLK 140kHz
X
=
L...-_.J
DGND
Figure 6. Circuitry Required for Internal Clock Operation
Figure 8. External Clock Operation
MINIMUM
AUTOZEAO
CYCLE TIME
--l\
LEVELS DEFINED BY
{
INPUT SCHMITT lRIGGER
ell(
AUTOZEROeYCLE
~
IIIIIIIIIII
I~
DB11 D810 DB9 DBa DB7 DB6 OB5 DB4 DB3 DB2 DB1 DBO
(MSB)
(LSBI
elK
AUTOZERO CYCLE
! I
DB"
DECISION POINTS
DECISION POINTS
-tzflNTIIS THE MINIMUM WRITE PULSE WIDTH WHEN USING
INTERNAL CLOCK. SEE TIMING SPECIFICATIONS.
Figure 7. Operating Waveforms - Internal Clock
3-278 ANALOG-TO-DIGITAL CONVERTERS
D810
(MBB)
*tafEXTIIS THE MINIMUM WRITE PULSE WIDTH WHEN USJNG
EXTeRNAL CLOCK. SEE TIMING SPECIFICATIONS.
Figure 9. Operating Waveforms - External Clock
11IIIIIIII ANALOG
WDEVICES
FEATURES
20p.s Conversion Time
On-Chip Sample-Hold
50kHz Sampling Rate
25kHz Full-Power Input Bandwidth
Choice of Data Formats
Single +5V Supply
Low Power (50mW)
Skinny 24-Pin DIP and 28-Terminal
Surface Mount Packages
GENERAL DESCRIPTION
The AD7579 and AD7580 are lO-bit, successive approximation
ADCs. They have differeritial analog inputs that will accept
unipolar or bipolar input signals while operating from only a
single +5V supply. Input ranges of 0 to +2.SV, 0 to +5V and
± 2.5V are possible with no external signal conditioning. Only
an external 2.SV reference and clock and control signals are
required to make them operate.
LC 2MOS
1O-Bit Sampling AID Converters
AD7579/AD7580 I
AD7579 FUNCTIONAL BLOCK DIAGRAM
II
AD7580 FUNCTIONAL BLOCK DIAGRAM
v,,
With conversion time of less than 20fLS and an on-chip sample-hold
amplifier, the devices are ideally suited for digitizing ac signals.
The maximum sampling rate is SOkHz, giving an input bandwidth
of 25kHz. The parts are specified not only with traditional static
specifications such as linearity and offset but also with dynamic
specifications (SNR, Harmonic Distortion, IMD).
The AD7579 and AD7580 are microprocessor-compatible with
standard microprocessor control inputs (CS, RD, WR, RDY,
INT) and data outputs capable of interfacing to high-speed data
buses. There is a choice of data formats, with the AD7579
offering an (8 + 2) read and the AD7S80 offering a lO-bit parallel
word.
Space saving and low power are also features of these devices.
They dissipate less than sOmW from a single + SV supply and
are offered in a 0.3", 24-pin package and in 28-terminal plastic!
ceramic chip carriers for surface mounting.
PRODUCT HIGHLIGHTS
1. 20fLS conversion time with on-chip sample-hold makes the
AD7S79 and AD7S80 ideal for audio and higher bandwidth
signals, e.g., modem applications.
2. Differential analog inputs can accept unipolar or bipolar
input signals, but only a single, + SV power supply is
needed.
3. Versatile and easy-to-use digital interface has fast bus access!
relinquish times, allowing connection to most popular microprocessors.
ANALOG-TO-DIGITAL CONVERTERS 3-279
(Voo= +5V :t5%;VREF = +2.~~,AGND. =.DGND = OV;fCIJI = 2:5MHz;A1lspecificationsT
SPECIFICATIONS1unless
othelWlSe noted. Test conditions as mFIgUre 12 unless otherMS8 stated).
mil 1oT....
Parameter
J,A
Versions
K,B
Versions
SVersion
Units
Resolution
Integral Nonlinearity
Differential Linearity Error
Full-Scale Error
Zero Code Error'
Power Supply Rejection
ConditionsiCouents
These specifications apply for the
STATIC CHARACTERISTICS
10
10
±112
10
Bits
three Analog Input Ranges.
See Differential Applications.
No missing codes guaranteed over the
±I
±0.9
±5
±2
±3
+0.5
±0.9
±5
±l
±2
+0.5
±I
±0.9
±5
±2
±3
+0.5
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
16.9
18.5
50
16.9
18.5
50
16.9
18.5
50
~sm.in
feLK = 2.5MHz, tWR = lOOns.
~smax
See Functional Description.
25012.5
25012.5
25012.5
55
58
-58
55
58
-58
full temperature range2.
Connected as in Figure 12.
Connected as in Figure 14 Of 15.
4.75V
~ ...z
J
3
2
2. 21 2.
!!. !!l !!.
I
+ +
"J
•
I
1
!!l
+
!!.
+
1 1 "J ...z J
:;;
51 c
,L.:
2.
51
:;;
c
25 CB6
DB.
24 0B5
AGND
7
NC
•
AD7579
TQPVIEW
AD7579
22 NC
TOP VIEW
(Not to SClliel
cs
9
WR
10
20 DB2
RD 11
19 DB1
(Not to Scale)
"
ROY
Ne
23 DB4
12 13
I~
v"~
AGND
NC
cs
z z
c
"
~
'"
.
>
c
ii
~
~
1 'J ...z
>
4
3
2. 21 2.
!!.
+
2
NC
1
.,
:;:
1 J
!!.
!
81 II!
c C
I
•
' ,
L.
•
•
1
AD7580
•
TOP VIEW
(Not to Scale)
9
=NO CONNECT
~
i!c
!
81 II!
c c
...z
2
0
23 DBS
AD7580
DB.
TQPVIEW
(Not to Scale)
NC
21 DB4
19 DB2
,. ,. ,.
"cz z... . ..c
~
0B4
iiiiR
oB3
'/
11
"c
ii
22 NC
11
Ne
j
>
c
.,ii
!!.
+
.
oB1
Ri5
:s...
~
'"
0B6
20 DB3
I~
...z
24 DB&
10
"
3
zc
"c
25 DB7
WR
12 13
d
= NO CONNECT
.,ii
.,
:;:
I~
i!
c
!!.
I
V1NI-IB
,.c ,.... " ,.
iiiiR
11
d
=NO CONNECT
21 DB3
~ ii
illc
I~
NC =NO CONNECT
:s...
...
z z >c
c
"c
.
ii
~
ill
c
..
c
ANALOG· TO-DIGITAL CONVERTERS 3-283
PIN FUNCTION DESCRIPTION (DIP PACKAGE)
Mnemonic:
Pin Number
Desc:ription
Pin Number
Mnemonic:
Vn~(+ )A
Vn~(+)B
1
2
Vm(-)A
3
3
VII~(-)B
4
4
VREF
5
5
AGND
CS
6
7
8
6
7
8
WR
Analog Input Pin.
Analog Input Pin.
Analog Input Pin.
Analog Input Pin. The four
analog input pins connect to
the on-chip input attenuator
(see Figure 6) and may be
configured as in Table I for
various input ranges.
VREF Input. This is nominally
+2.5V.
Analog Ground
Chip Select Input.
Write Input. Used with CS to
start conversion. See Tables
1
2
Description
AD7S79 AD7S80
AD7S79 AD7SSO
DGND
HBEN
12
13
12
RDY
14
13
DBO-DB7
15-22
DBO-DB9
Digital Ground.
High Byte Enable Input. Used
in AD7579 for 2 Byte Reading.
See Tables II, IV. Either the
High Byte or the Low Byte
may be read first.
Open Drain Output. This is
accessed during Read Cycle.
When accessed, it is low during
conversion and high impedance
when conversion is complete.
Three-State Data Outputs on
AD7579. The data format is
right justified.
Three-State Data Outputs on
AD7580.
Internal connection. This pin
i. connected internally on the
AD7579. It should be left
open and not used as a feedthrough pin in double-sided
printed circuit boards.
Positive Power Supply. This is
+ 5V nominal.
14-23
II, III.
RD
9
9
INT
10
10
CLK
11
11
Read Input. Used with CS to
read data. See Tables II, III.
Open Drain Output. High
impedance during conversion.
Goes low when conversion is
complete.
Clock Input.
I.C.
23
VDD
24
Analog Input
Ranp
V.,.(+)A
Connections
V,,.(+)B V.,.(-)A
V,,.(-)B
Analog Input Common-Mode
Span
Ra_
Figure 12
V.,.(+)
V,,.(+)
V,,.(-)
VIN( -)
2.5V
OVto +SV
Figure 14
V.,.(+)
AGND
V,,.(-)
AGND
SV
OVto +10V
Figure 15
V,,.(+)
VREF
V,,.(-)
VREF
SV
-2.SVto +7.5V
24
~
'WI[ 1m HBEN Functinn
X
1
1
0
0
0
0
X
1
1
0
0
1.[
1
I
X
X
X
0
I
Not Selected
Selected, WAITforWR, RD
Start Conversion on ofWR
EnableADC Data (8 LSBs)"
Enable ADC Data (2 MSBs)"
1.
"Data is Riaht Justifoed.
Table II. AD7579 Truth Table
Table I. Analog Input Ranges
~
'WI[ 1m
I
0
0
0
X
I
U
I
X
I
I
0
Function
Not Selected
Selected, WAIT for WR, RD
Start Conversion on ofWR
Enable ADC data (10 Bits)
1.
HBEN DB7
DB6
DBS
DB4
DB3
DB2
DBI
LOW
DB7
DB6
DBS
DB4
DB3
DB2
DBI
DBO
DBO
HIGH
EOC" 0
0
0
0
0
DB9
DB8
*EOC is an intemal End of Conversion flag.
Table III. AD7580 Truth Table
Table IV. AD7579 Output Data Format
CIRCUIT INFORMATION
ANALOG INPUT CIRCUITRY
The AD7579 is a 10-bit ADC with an (8 + 2) output bus structure
designed for 8-bit microprocessor systems. The AD7580 is a 10bit ADC with a 10-bit parallel output bus structure. The ADC
circuitry is identical in both parts. Block diagrams are shown on
the first page of this data sheet.
Figure 6 shows the input circuitry to the ADC comparator.
This comparator has differential inputs which are accessed through
the attenuatot networks made up of resistors R. The attenuators
can be used to scale and offset analog input voltages, and this is
done in Figures 14 and 15 to alter the basic ADC input range.
The analog inputs to the comparator are differential with the
provisos that V + is always greater than or equal to V -, V - is
3-284 ANALOG-TO-DIGITAL CONVERTERS
greater than or equal to AGND and that V + is less than or
equal to VDD • These conditions must be satisfied when using
the ADC in any of the voltage ranges.
R
VINI+IA
VINI+)B
R
V1Nf-)A
VIN(-)B
Figure 6. AD75791AD7580 Input Circuit
AD7579/AD7580
Figure 7 shows an ac equivalent input circuit for the AD75791
AD7580 when used in the 2.5V Unipolar Mode of Figure 12.
The ADC comparator is a sampled data comparator and the
input circuitry for this is represented by SA, Req and CA' Req is
a combination of the switch-on resistance and the input impedance
of the comparator. When conversion starts, VIN( + ) is sampled
for at least (2tcLK + tWR + 200ns) before the comparator goes
into the hold mode. This means that the analog input has a
minimum of I.lfLs (feLK = 2.5MHz, tWR = lOOns) to settle
before the comparator makes a decision. By using the typical
values in Figure 7 for R, Req and CA, the input time constant is
SOns. Settling to ± 1I4LSB in a IO-bit system takes 8.3 time
constants or 415ns in this case. This means that VIm + ) has
plenty of time to settle before the ADC comparison cycle begins.
It is important to remember that any source resistance or source
capacitance appearing at the input will also increase the settling
time and this should be kept to a minimum in all cases.
INTERNAL SAMPLE-AND-HOLD
When an ADC without sample-and-hold is used to digitize ac
signals, the analog input must not change by more than 1/2LSB
during the conversion. This puts severe limitations on the allowable
input signal bandwidth to such devices. A sample-and-hold
amplifier must be used in front of the ADC if increased bandwidth
is required. The charge balanced comparator used in the AD75791
AD7580 for the AID conversion provides the user with an inherent
sample-and-hold function. The ADC is specified to work with
sampling rates up to 50kHz. This rate allows time to do a conversion
and read the result into memory. Since at least two samples are
needed to define an input sine wave according to the Nyquist
theory, the analog input signal bandwidth for the AD75791AD7580
is 25kHz. Figures 20, 21 and 22 show the performance of the
ADC when digitizing ac signals.
Voo=+5V
R
SkU
V1N(+)A, ~-r--""""'-' SAMPLING SWITCH,
VIN! +)8
Cs
CLOSED
REO
I
O.5pF
SA
2.SkH
\7AGND
R
Ski!
VIN/-IA, ~-t---""""'-'
c,
V1N(-IB
O.SpF
T
C.
I
10pF
\7AGND
\lAGND
Figure 7. AD75791AD7580 Equivalent Input Circuit During
Sampling
With a 2.5MHz clock, the AD7579/AD7580 has a maximum
conversion time of 18.5fLS. If IfLS is allowed for reading the data
outputs, the maximum sampling rate for the device is 50kHz.
This means that the maximum analog input frequency is 25kHz
according to the Nyquist theory. The ADC input impedance in
the Unipolar Configuration of Figure 12 is IOMO. A medium
bandwidth op amp will drive this at 25kHz. When the input
attenuators are used for signal conditioning, the input impedance
is 10kO. The drive requirements on the amplifier will now be
greater but any errors resulting will be gain errors only. Suitable
op amps for driving the AD7579/AD7580 in any of the input
configurations are the AD711, AD OP-27, AD544. These will
deliver specified device performance over the input bandwidth.
Figure 8. Using the AD580 as the Reference for the
AD75791AD7580
While the AD7579/AD7580 is converting, V + (see Figure 6) is
held and V - is being tracked. This limits the rate of change,
dV/dt, on VIm - ). For example, if the Common-Mode frequency
is 60Hz, then the allowable amplitude of this to introduce no
more than 1I2LSB linearity error is 160mV pk-pk. As the CommonMode frequency increases, this allowable amplitude decreases.
Figure 9 shows how a 100mV pk-pk Common-Mode signal
affects linearity error as its frequency is increased up to 1kHz.
INTEGRAL
LINEARITY
ERROR
(LSBsj
COMMON·MODE AMPLlTUDE=100mV pk-pk
REFERENCE INPUT
The AD7579/AD7580 V REF input is connected to the on-chip
DAC. The input impedance of this is code dependent and the
greatest variation occurs when the DAC resistors are at their
lower limit. In this case, the impedance changes from I. 75kO to
5.25kO as the DAC is switched. To ensure that the error during
conversion is less than 1/2LSB, the Reference output impedance
should be less than 10. References which satisfy this are the
AD580 (shown in Figure 8) and the ADI403 from Analog Devices.
If a trimmable reference such as the AD584 is used, it is possible
to trim out the ADC full-scale error by adjusting the reference
output.
COMMON·MODE
FREQUENCY (Hz)
250
500
750
1k
Figure 9. AD75791AD7580 Error vs. Common-Mode
Frequency
ANALOG-TO-DIGITAL CONVERTERS 3-285
II
CLOCK INPUT
The AD7S79/AD7S80 is specified to operate with a 2.SMHz
clock on the CLK input pin. This pin may be driven directly
by CMOS or TTL buffers. The mark/space ratio on the clock
can vary from 40/60 to 60/40. As the clock frequency is slowed
down, it can result in slightly degraded accuracy performance.
This is due to leakage effects on the hold capacitor in the internal
sample-and-hold. Figure 10 is a typical plot of accuracy versus
clock frequency for the ADC.
f\
'" ,
f'.
/
/
is only available on the AD7S79 (see Table V). It appears on
DB7, when reading the high Byte.
When the ADC is finished the conversion, the conditions of
V +, V - and the comparators are maintained and the ADC is
now ready to start a new conversion. If WR and CLK are asynchronous, the total time from start to end of conversion is variable.
Minimum conversion time is (tWR + 42 tCLK), and maximum
conversion time is (tWR + 46 !eLK)'
APPLYING THE AD7579/AD7580
The AD7S79/AD7S80 has a flexible input stage consisting of
two input attenuators. It is possible to realize various analog
input ranges by reconfiguring these attenuators. The following diagrams show the ADC connected in the most popular
configurations.
DIFFERENTIAL APPLICATIONS
Figure 12 shows the AD7S79/AD7S80 connected in the standard
unipolar mode. Figure 13 and Table V show the ideal input/output
+5V
+2.5V
20k
Figure 10. Normalized Linearity Error vs. Clock Frequency
0-0-1.,...--1.,...----, f
1+.,<1.. _
t,·rWr--,,·r~--.,
LSB DECISION
END OF
CONVERSION
ROY
cs
r'
~TART
U'
f CLK =2.5MHz
os
AD
) CONTROL
INPUTS
ViR
V-
HBEN*
080- DB9 (087)
DATA OUT
* AD7579 ONLY
Figure 12, Unipolar 2,5V Operational Diagram
: : :I
OUTPUT
CODE
FULL-SCALE
-~y,
,,,
,,,
,,
,,
,
l
CONVERSION
CONTROL
OUTPUTS
CLK
I
ViR
}
iNT
v+
i,
CLK
9'·'W"·"
VDD
V REF
FUNCTIONAL DESCRIPTION
Figure II shows the events sequence when the AD7S79/AD7S80
is converting. The device is selected when CS goes low and the
first phase of conversion begins when WR goes low. This is an
initializaton phase and causes the internal DAC to be set to full
scale, comparators set to auto-zero and V + (see Figure 6) to be
sampled. The second phase begins some time after WR goes
back high. This time can vary between 0 and 4 clock periods
and depends on the state of an on-chip divide-by-4 counter
which is used for internal synchronization. This is the start of
the successive approximation procedure. V + is held after 2-112
clock periods have elapsed. V - is sampled and the DAC output
is switched into the comparator. There is (1-112 x tCLK) left for
comparison and then the MSB result is latched. The MSB test
takes 4 clock cycles as do each of the succeeding bit tests. Thus,
the successive approximation always takes 40 clock cycles.
/
/
/
/
/
,,
FS=2.SV
lLSB =
1~~4
//
/
.r"
::::: r
/
OO"'001~
00 ...000
,
LSB
2
3 - - - - - - - - - - - - - ...·--'--t--F:':~+·
LSBs LSBs
FS- 1LSB
Figure 13, Ideal Input/Output Transfer Characteristic
Figure 11. AD75791AD7580 Conversion Sequence
When all the bits have been tested, the SAR holds a 10-bit
word representing the input signal. After a further 2 clock cycles
this is transferred to a three state output latch, and three internal
flag bits (RDY, INT, EOC) are set. The user can access the
data outputs by bringing RD and CS low. RDY and INT are
both open drain outputs with RDY accessed by RD and INT
being permanently available. When INT is loaded with the
circuit of Figure Sea), it typically takes 60n8 to reach VOL' EOC
3-286 ANALOG-TO-DIGITAL CONVERTERS
Differential Analog
Input, Volts
Digital Output
DB9
DBO
+0.000
+0.00244
00 0000 0000
00 0000 0001
+ 1.24756
+ 1.25
+ 1.25244
01 1111 1111
10 0000 0000
10 0000 0001
+2.49512
+2.49756
II 1111 1110
II 1111 1111
Table V, Input/Output Code Table for Figure 12
AD7579/AD7580
transfer characteristic and the input/output code table respectively.
Code transitions occur between successive integer LSB values
(i.e., 1I2LSB, 3/2LSBs, etc.). The output code is straight binary
with lLSB = FS/I024 = 2.5/1024V = 2.4mV. The input
voltage span is 2.5V and the common-mode range is OV to
+ 5V, when VDD = 5V. This means that the lowest voltage
which can be tolerated at any of the analog inputs is OV, and
the highest voltage which can be tolerated is + 5V.
Figures 14 and 15 show the input attenuators on the AD75791
AD7580 configured to change the basic range of the device. A
5V range can be configured by grounding one end of each attenuator and applying the differential input to the other ends.
This is shown in Figure 14. The span is 5V and the common-mode
range is 0 to + 10V. In Figure 15, one end of each attenuator is
tied to VREF (2.5V), and this allows each of the other legs to go
to - 2.5V without causing the comparator input to go negative.
Assuming VREF is 2.5V, the span of this circuit is 5V and the
common-mode range is -2.5V to +7.5V. Note that reducing
VDD below 5 volts causes a corresponding reduction in CMR.
See Specifications page for full details.
Voo= +5V
V1N(+J - V1N(-J
ov
O.00488V
2.500V
4.99512V
OUTPUTCDDE
00 0000 0000
00 0000 0001
10 0000 0000
11 1111 1111
SINGLE-ENDED APPLICATIONS
In many cases, users of the AD7579/AD7580 will want to measure
single-ended input voltages (i.e., ground referred signals). The
circuits of Figures 12, 14 and 15 can be easily adapted to accept
such signals. If VIN( -) in Figure 12 is tied to AGND, then the
analog input range is OV to + Z. 5V. By connecting VINC - ) of
Figure 14 to AGND, the analog input range becomes OV to
+ 5V. Figure 15 can be modified as in Figure 16 to accept input
voltages in the range -2.5V to +Z.5V. Each of these circuits
are special cases of the Differential Input circuits and are achieved
by making the negative input to the internal comparator equal
to AGND.
OFFSET AND FULL-SCALE ADJUSTMENT
Figure 17 shows the AD7579/AD7580 connected in the singleended Unipolar 2.5V range with offset and full-scale calibration
circuitry. The zero error of the ADC is the deviation of the
actual LSB transition from the ideal LSB transition. In many
cases, the zero of the ADC will not need adjustment. When it
does, Rl in Figure 17 provides 25mV of adjustment which is
sufficient to null out both the op amp and ADC offset error.
Resistors R3 and R4 bias VIN( - ) to approximately 8mV and
ensure that the offset error is never positive. This allows the
error to be nulled in the single supply system of Figure 17.
Apply +0.5LSB to VIN and adjusr RI until the ADC output
code flickers between 00 ..... 000 and 00 ..... 001.
For full-scale calibration, apply a voltage of (2.5V - 1.5LSB) to
VIN' Then adjust RZ until the output code flickers between 11
..... 110 and II ..... 111. When the full-scale calibration is
complete, return to the offset adjustment procedure and check
that further adjustment is not necessary.
"DECOUPLING CIRCUITRY AND CONTROL CIRCUITRY
AS IN FIGURE 12
Figure 14. 5V Span with 0 to 10V CMR
Voo= +5V
10kH
V1N(+I- V1N(-j
OUTPUT CODE
OV
00
00
10
11
O.00488V
2.S00V
4.99512V
0000
0000
0000
1111
1.8kH
0000
0001
0000
1111
*DECOUPLING CIRCUITRY AND CONTROL CIRCUITRY
AS IN FIGURE 12
Figure 15. 5V Span with -2.5V to
+ 7.5V CMR
Voo= +5V
Figure 17. Offset and Full-Scale Calibration for Sing/eEnded Circuit
V 1N {+)
-2.500V
-2.49512V
D.OOV
+2.49S1ZV
OUTPUTCQDE
00
00
10
11
0000
0000
0000
1111
0000
0001
0000
111'
*DECOUPLING CIRCUITRY AND CONTROL CIRCUITRY
AS IN FIGURE 12
Figure 16. Single-Ended Bipolar Operation, -2.5V
to +2.5V
ANALOG-TO-OIGITAL CONVERTERS 3-287
II
v+
v+
v-
vNOTES
1. RF=19.6kU, RG=1.21kU.
2. SEE AD&25 DATA SHEET FOR RECOMMENDED INPUT
PROTECTION CIRCUITRY.
3. POWER SUPPLY AND REFERENCE DECOUPUNG
OMmED FOR CLARITY.
Figure 18a. AD75791AD7580 and AD625 in a Data
Acquisition System
AD7579/AD7580 IN DATA ACQUISITION SYSTEMS
The AD7579/AD7580 is suitable for many data acquisition
circuits. Figure 18a shows one such circuit in which a load cell
is used to produce a signal in response to an applied force.
Typically these transducers produce 30mV full scale per volt of
excitation. Since the excitation in this case is 2.5V, the output
from the load cell is ±75mV when the maximum specified force
is applied. The AD625 Instrumentation Amplifier is set for a
gain of 33.33 which means that the input signal to the ADC is
±2.5V. Thus, the AD7579/AD7580 is configured in the singleended, ± 2.5V range of Fignre 16. When no force is applied to
the load cell, the ADC output will sit at mid-scale. With maximum
negative force applied the ADC output will be all zeros; whereas,
with maximum positive force the output will be all Is. Offset
and gain calibration of this system can be accomplished by
trimming the offsets and gain of the instrumentation amplifier.
Figure 18b shows a differential transducer unbalanced by "" 100
supplying a 0 to 20mV maximum signal. The resistors are chosen
for a gain of 125, and the ADC is conftgUred to accept 0 to
2.5V differential signal. This is a lower-cost alternative to using
an instrumentation amplifier.
Note that in the circuits of Figure 18, VREF for the ADC and
the excitation voltage for the load cell are both +2.5V. If the
same reference drives both these points, then the ADC operation
is ratiometric which elimioates system errors due to reference
drift. The main reason why the same reference would not be
used to drive both load cell and ADC is physical location. When
the load cell is remote from the ADC circuitry, it might not be
practical to have the same drive for both circuits.
APPLICATIONS HINTS
Layout: To obtain the best performance from the AD7579/AD7580,
lay it out on a printed circuit board. Digital and analog lines on
the board should be separated as much as possible. In particular,
take care not to run any digital track adjacent to an analog
signal track or underneath the AD7579/AD7580. The analog
inputs should be screened by AGND.
3-288 ANALOG-TO-DIGITAL CONVERTERS
Figure 18b. AD75791AD7580 and AD648 in a Data
Acquisition System
Grounding: Establish a single-point analog ground (STAR ground)
at Pin 6 (AGND) or as close as possible to the AD7579/AD7580.
This is shown in Fignre 19. Pin 12 (AD7579/AD7580 DGND)
and all other analog grounds should be connected to this single
analog ground point. However, do not connect any other digital
grounds to this analog ground point. Low impedance analog
and digital power supply returns are essential to low noise operation
of the ADC and these tracks should be kept as wide as possible.
Noise: Input signal leads to VIIi + )A, VIIi + )B, VIIi - )A,
VI~ -
)B and signal return leads from AGND (Pin 6) should be
kept as short as possible to minimize input noise coupling. In
applications where this is not possible a shielded cable between
source and ADC is recommended.
ANALOG
SUPPLY
+15V GND
DIGITAL
SUPPLY
-15V
+
AGND
ANALOG
CIRCUITRY
Voo
AD7579
AD7580
DGND
DIGITAL
CIRCUITRY
Figure 19. Power Supply Grounding Practice
AD7579/AD7580
DIGITAL SIGNAL PROCESSING APPLICATIONS
In Digital Signal Processing (DSP) application areas like voice
recognition, echo cancellation and adaptive filtering, the dynamic
characteristics (SNR, Harmonic Distortion, IntermoduJation
Distortion) of ADCs are critical. For this reason, the AD7579/
AD7580 is specified dynamicaJIy as well as with standard D.C.
specifications (linearity error, offset error, etc.).
Figure 20 shows a 2048 point FFT plot of an AD7579/AD7580
with an input signal of 3.58kHz. The SNR is 60.ldBs. The
largest harmonic appears at 2fo (7.16kHz) and is 70dB down
from the fundamental. Harmonics above 3fo are in the noise
floor. Note that when SNR is calculated, it includes harmonics.
OdB r-----,,----------------.
-~Br--~r_------------~
INPUT FREQUENCY: 3.58kHz
SAMPLING RATE: 51.2kHz
SNR:60.11dB
:!;l
-~dBr--~r_------------~
When a sine wave of specified frequency is applied to the AD75791
AD7580 and several thousand samples are taken, it is possible
to plot a histogram showing the frequency of occurrence of each
of 1024 ADC codes. A perfect ADC would produce a cusp
probability density function described by the equation
p(V) = (A l
_
V2)1/l
A is the peak amplitUde of the sine wave and p(V) the probability
of occurrence at the voltage V. If a particular step is wider than
the ideal width, then the code associated with that step will
accumulate more counts than the code for an ideal step. Likewise,
a step narrower than ideal width will have fewer counts. Missing
codes are easily seen because a missing code means zero counts
for a particular code. The absence of large spikes in the histogram
indicates small differential nonlinearity. The actual histogram
obtained is shown in Figure 22 and corresponds very well with
the ideal cusp shape. It shows that the AD7579/AD7580 has
very small differential nonlinearity and no missing codes with an
input frequency of 25kHz.
~
~-~B~-~r-------------~
~
1200
~ -SOdB ~-t-~f-:-:--_I-.-----,---___.__-.__-~
INPUT FREQUENCY: 25kHz
SAMPLE FREQUENCY: 51.2kHz
NUMBER OF SAMPLES: 200,000
-100dS
,
25.5kHz
FREQUENCY
Figure 20. AD75791AD7580 Spectral Response
If these were excluded the SNR figure would be closer to the
ideal of 62dB for a 10-bit ADC. The relationship between Signalto-Noise Ratio (SNR) and ADC resolution is expressed in the
following equation:
SNR = (6.02N
+
~t5
9.5
~
~
9
~~
8.5
----
""
25'
1.76)dB
512
CODE
This is for an ideal ADC with no differential or integral linearity
errors. These errors will cause a degradation in SNR. By working
backwards in the above equation it is possible to get a measure
of ADC performance expressed in effective number of bits. This
is shown over frequency in Figure 21 for the AD7579/AD7580.
The effective number of bits typicaJly falls between 9.7 and 9.8
corresponding to SNRs of 60.0 and 6O.6dBs.
10
1
\.
1....
IT
1
--
SAMPUNGRATE: 51.2kHz
Z
~
10
15
INPUT FREQUENCY - kHz
20
25
Figure 21. AD75791AD7580 Effective Number of Bits
7'.
1023
Figure 22. Histogram Plot for AD75791AD7580
Whenever the AD7579/AD7580 is used to sample ac signals, it
is essential that the signal sampling occurs at exactly equal intervals.
This minimizes errors due to sampling uncertainty or jitter. The
WR command for the AD7579/AD7580 needs to be synchronized
with the CLK input to ensure equal interval sampling.
Two conditions must be satisfied to ensure proper synchronization:
1) The time interval between successive WR signals needs to be
long enough to aJlow a conversion to finish and the data to be
read into memory. 2) Because of the internal operation of the
ADC, the number of clock pulses between successive write
signals must be a multiple of four.
The conversion time for the AD7579/AD7580 has a maximum
value of (tWR + 46 tcr.K). If 4 tcLK is aJlowed for reading the
data outputs into a buffer then the interval between successive
WR signals must be at least 50 tcLK' The easiest way to satisfy
both this requirement and number 2 above is to divide fcLK by
64 to produce the WR signal. Alternatively, if a programmable
timer/counter on a processor board is available, then it will be
possible to easily divide fCLK by 52.
ANALOG-TO-DIGITAL CONVERTERS 3-289
II
MICROPROCESSOR INTERFACING
Reading Data
Conversion is started in the AD7579/AD7580 by bringing WR
low. It is recommended that the user wait until conversion is
complete before reading data. This can be achieved in any of
the following ways:
1. Insert a software delay greater than the ADC conversion time
between the conversion start instruction and the data read
instructions.
8088 Interface
The AD7579, with its (8 + 2) data fonnat, is ideal for use with
the 8088 microprocessor. Figure 24 is the interface diagram.
Again, a write instruction is required to start a conversion and a
read at the end of conversion reads data into the processor. For
the 8088 the appropriate instructions are:
MOVCOOO,AX
MOVAX,COOI
MOV AX,COOO
2. Use the externally available INT signal to interrupt the
microprocessor. This is an open drain output which goes low
at the end of conversion.
3. On the AD7579, it is possible to interrogate the EOC status
flag (See Table IV) to determine when conversion is complete.
Reading may then proceed.
MC68000 Interface
Figure 23 shows an interface diagram for the AD7580 and the
MC68000. The address decoding means that the AD7580 is a
memory mapp"'~ device. For example, if t..'le ,,6..D7580 is memory
mapped as address COOOH, then a write instruction to this
address will start a conversion, i.e.,
MOVE.W DO COOO
startS a conversion. When the conversion is complete, the MC68000
acquires the result by reading from COOOH, i.e.,
Vee
A~A15r-------------------------------~
8088
101M
~----------~~~
~----------~~ WR
AD757S*
ALE
ADO-AD7 ~________.:..DA
...TA B,...U_S------,,A DBO-DB7
'LlNEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 24. 8088 to AD7579 Interface
MOVE.W COOO, DO.
A1-A23
MN/MX
Startaconversion
Read2M.SBsofdata
Read8LSBsofdata
TMS32020Interface
Figure 25 shows the AD7580 to TMS32020 interface. OUTA,PA
starts a conversion and INA,PA reads data from the ADC when
conversion is complete. PA is the Port Address.
1---.....
RIW 1-........---+-1..-/
AO-A15
1---....,
MC68000
DTACK~----------J
H-------tCS
AD7580*
DO-D15 ~____.....:.DA:..;,TA B,...U_S______..l DBO-DB9
L -_ _ _..J
RM
~--<_-------+-J
TMS32020
'LlNEAR CIRCUITRY OMITTED FOR CLARITY.
~
AD7580'
DO-D15 ~________
D..,ATA BrU_S____--,,A DBO-DB9
Figure 23. MC68000 to AD7580 Interface
"LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 25. TMS32020 to AD7580 Interface
3-290 ANALOG-TO-DIGITAL CONVERTERS
AD7579/AD7580
PRINTED CIRCUIT BOARD LAYOUT
Figure 26 is a circuit diagram showing the AD7579 or AD7580
being used to digitize an analog signal. The circuit board contains
the ADC, reference, and a grid where the user can add additional
circuitry. If the AD7580 is used, then links L6 and L8 should
be inserted; and if AD7579 is used, L7 should be inserted with
L6 and L8 omitted. Note that Pins 13 to 23 are not labelled.
Depending on which ADC is used the function of these pins
changes. See the Pin Function Description section for full
details.
Links L I to L5 at the analog input allow the user to choose
various analog input ranges. With LI, L2 and L3 in place and
the others omitted, the input range is OV to + 2.5V. Omitting
L3 allows the user to measure input voltages which have a commonmode signal. The OV to + 5V range is achieved by inserting L2,
L3 and L4 and omitting Ll and L5. With L2, L3 and L5 in
place and LI, L4 omitted, the Analog input range is -2.5V to
+2.5V.
IC2 (AD580) provides the +2.5V reference for the ADC. All
the input and output control signals enter and leave the board
through Jl, which can be a Eurocard connector or a standard
edge connector. Resistors Rl and R2 are the pull-ups required
for the RDY and INT open-drain outputs. Note that the complete
circuit operates from a + 5V power supply.
The printed circuit board layout is shown in Figures 27 and 28.
Figure 27 is the component side layout and Figure 28 is the
solder side layout. The component overlay is shown in Figure 29.
In the layout, the AD580 is kept as close to the AD7579/AD7580
as possible. The STAR ground point is located at Pin 6 (AGND)
of the ADC. Pin 12 (DGND), reference ground and the analog
ground plane are connected to this point.
To ensure optimum performance, the AD7579/AD7580 power
supply is decoupled with Cl and C2. The VREF input to the
ADC is decoupled with C3 and C4. Note how all the decoupling
capacitors are placed as close as possible to the ADC.
J1
AGND
+5V
C1/A1
C2/A2
R2
3k
C17/A17
V'N( +) o----------!~-{
C19/A19
C7/A7
C8/A8
C9/A9
C10/A10
C11/A11
C12/A12
C13/A13
C14/A14
C15/A15
C16/A16
C18/A18
C20/A20
C21/A21
C22/A22
DGND
C32/A32
Figure 26. Schematic for AD75791AD7580 Board
ANALOG-TO-DIGITAL CONVERTERS 3-291
3
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Figure 27. PCB Component Side Layout for Figure 26
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Figure 28. PCB Solder Side Layout for Figure 26
3-292 ANALOG-TO-OIGITAL CONVERTERS
AD7579/AD7580
r
AD7579jAD7580
J:L..
BOARD
R1
VINf+)A
L1
R2
VINf+)B
VINf-)A
VIN(-)B
L6
I IL7
La
L41 L2\
•
L5
IL3
IC2
I I
C3 C4
II
IC1
L
Figure 29. Component Overlay for Circuit of Figure 26
ANALOG-TO-OIGITAL CONVERTERS 3-293
~294
ANALOG-TO-D/GITAL CONVERTERS
CMOS fJ.P-Compatible
8-Bit, 8-Channel DAS
AD1581 I
~ANALOG
WDEVICES
FEATURES
a-Bit Resolution
On-Chip a x 8 Dual-Port Memory
No Missed Codes Over Full Temperature Range
Interfaces Directly to zao/aoa5/6aoo
CMOS, TTL Compatible Digital Inputs
Three-State Data Drivers
Ratiometric Capability
Interleaved DMA Operation
Fast Conversion
A/D Process Totally Transparent to IlP
Low Cost
GENERAL DESCRIPTION
The AD7581 is a microprocessor compatible 8 bit, 8 channel,
memory buffered, data-acquisition system on a monolithic
CMOS chip. It consists of an 8 bit successive approximation
AID converter, an 8 channel multiplexer, If'X 8 dual-port
RAM, three-state DATA drivers (for interface), address latches
and microprocessor compatible control logic. The device interfaces directly to 8080, 8085, Z80, 6800 and other microprocessor systems.
The successive approximation conversion takes place on a
continuous, channel sequencing, basis using microprocessor
control signals for the clock. Data is automatically transferred
to its proper location in the 8 X 8 dual-port RAM at the end
of each conversion. When under microprocessor control, a
READ DATA operation is allowed at any time for any channel
since on-chip logic provides interleaved DMA. The facility to
latch the address inpu ts (Ao - A2) with ALE enables the
AD7581 to interface with IlP systems which feature either
shared or separate address and data buses.
AD7581 FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
Differential
Nonlinearity
Temperature Range
and Package Options·
Plastic (N-28)
Hermetic (D-28)
o to +70o C
_25°C to +85°C
±17/8LSB
±7/8LSB
±3/4LSB
AD7581JN
AD7581KN
AD7581LN
AD7581AD
AD7581BD
AD7581CD
• See Section 14 for package outline information.
ANALOG-TO-OIGITAL CONVERTERS 3-295
DC SPEC IFICAli 0NS (Yuu = + 5V, V
REF
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlineatity
Offset Error2
Gain Error
Worst Channel
Gain Match Between Channels
BOFS Gain Error
ANALOG INPUTS
Input Resistance
At VREF (pin 10)
At BOFS (pin 1)'
At Any Analog Input (pins 2-9)
VREF (For Sjecified Perfonnance)
VREF Range
Nominal Analog Input Range
Unipolar Mode
Bipolar Mode
DIGITAL INPUTS
CS (pin 13), ALE (pin 16), Ao - A2
(pins 17-19), CLK (pin 15)
VINH Logic HIGH Input Voltage
VINL Logic LOW Input Voltage
lIN Input Current
CIN Input CapacitanceS
Version!
Typical at
+2~·C
Limit Over
Temperature Units
All
IN,AD
KN,BD
LN,CD
IN,AD
KN,BD
LN,CD
IN,AD
KN,BD
LN,CD
S
±17/S
±3/4
±1I2
±17/8
±7/S
±3/4
200
80
SO
S
±1 7/S max
±3/4 max
±1I2 max
±1 7/S max
±7/S max
±3/4max
200 max
SO max
SO max
Bits
LSB
LSB
LSB
LSB
LSB
LSB
mV
mV
mV
IN,AD
KN,BD
LN,CD
±3
±2
±1
±6max
±4max
±2max
LSB
LSB
LSB
IN,AD
KN,BD
LN,CD
2
11/2
1
3 max
2 max
1 max
LSB
LSB
LSB
All
-2112
All
All
All
All
All
10/20/30
10/20/30
10/20/30
-10
-5 to -15
All
o to +VREF' o to +VREF
o to -VREF
Oto -VREF
10/20/30
10/20/30
10/20/30
-10
-5 to -15
kO min/typ/max
kO min/typ/max
kO min/typ/max
V
V
All
All
All
All
All
+2.2
+1.2
0.01
4
+2.4 min
+O.Smax
1 max
5 max
V
V
p.A
pF
+4.S
+0.4
+4.5 min
+0.6 max
V
V
0.3
lOmax
p.A
All
All
All
lOmax
pF
Unipolar Binary Figure 7
Complementary Binary Figure 8
Offset Binary Figure 9
+5
3typ
3 typ
+5
5 max
Smax
V
mA
mA
NOTES
'Temperature range as follows, IN, KN, LN (0 to +70°C), AD, BO, CO (-25°C to +8So C).
aTypical offset temperature coefficient is ±1sol'vfc.
• 'RBOFS/RAJN (0-7) mismatch causes transfer function ·rotation about positive fuU aca1e. The effect is aa offset
and a gam term when usiog the circuits of Figure 8a, and Figure 9a.
'Typical value, not guaranteed or subject to test.
• Guaranteed but not tested.
'Typical change in BOFS gam from +2s"C to Tmin or Tmax is ±2LSBs.
Specifications subject to change without notice.
3-296 ANALOG-TO-DIGITAL CONVERTERS
Conditions/Comments
Adjustable to zero, see Figure 7a.
Adjustable to zero, see Figure 7a.
Gain Error is Measured After Offset
Calibration. Max Full Scale Change
for Any Channel from +2S·C to
Tmin or T max is ±2LSB.
Adjustable to zero, see Figure ia.
LSB
V
V
-VBoFS "'VAu.",IVREF I-VBOFS
DIGITAL OUTPUTS
STAT (pin 12), DB7 to DBo (pins 20-27)
VOH Output HIGH Voltage
All
VOL Output LOW Voltage
All
ILKG DB7 to DBo Floating State
Leakage
All
Floating State Output Capacitance
All
(DB7 -DBo)
Output Code
All
POWER REQUIREMENTS
Voo
100 - Static
100 - Dynamic
= -lOY, Unipolar Operation, unless otherwise stated)
±S%
See Figure 7 and S.
See Figure 9
VIN=OV, Voo
ISOURCE = 40p.A
islNK = 1.6mA
VOUT = OV to Voo
fCLK= 1MHz
AC SPECIFICATIONS (Voo = + 5V, V
REF
Symbol Specification
tH
tALS
tALH
tLCS
tACC
tew
teF
teLZ
fCLK
Typical at
+2S oC
ALE pulse width
50
Address valid to latch set-up time
45
Address valid to latch hold time
10
Address latch to CS set-up time
10
200
CS to output propagation delay
CS pulse width
250
CS to output float propagation delay 50
CS to low impedance bus
100
Clock frequency for stated accuracy 1600
Limit Over
Temperature
Units
80 min
70 min
20 min
20 min
250 max
280 min
80 max
150 max
1200 maxI
ns
ns
ns
ns
ns
ns
ns
ns
kHz
1
ABSOLUTE MAXIMUM RATINGS
Voo to AGND .
Vooto DGND . . . . . . . .
AGND to DGND . . . . . . .
Digital Input Voltage to DGND
(Pins 13, 1&-19) . . . . . .
Digital Output Voltage to DGND
(Pins 12, 20-27) . . . . . . .
CLK (Pin IS) Input Voltage to DGND
VREF (Pin 10) to AGND . . . . . . .
AD7581
= -lOY, Unipolar Operation, unless oIherwise staled)
. . . . . +7V
. . . . . +7V
-O.3V, Voo
-0.3V, Voo +O.3V
-0.3V, Voo +O.3V
-0.3V, Voo +O.3V
. . . . . . . . ±2SV
Conditions
See "Switching Terminology"
on page 5
CL = 100pF
Guaranteed conversion time of 66.6~s/channel with 1200kHz clock.
VBOFS (Pin I) to AGND
AIN (0-7)(Pin 9-2) . . .
Operating Temperature Range
IN, KN, LN .. .
AD, BD, CD . . . . . . .
Storage Temperature . . . .
Lead Temperature (Soldering, 10secs)
Power Dissipation (Any Package)
to +7SoC . . . . . . . .
Derate above + 75°C by
CAUTION
ESD (electrostatic discharge) senslllve device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
±17V
±17V
o to +70°C
- 2SoC to + 85°C
-6SoC to + ISO°C
. +300°C
WARNING!
I,OOOmW
10mWfOC
0
~~DEVICE
PIN CONFIGURATION
Voo
DBO (LSBI
DB.
DB2
DBa
DB4
DBS
DB6
087 (MSB)
A2
A.
AD
ALE
eLK
ANALOG-TO-DIGITAL CONVERTERS 3-297
I
GENERAL CIRCUIT INFORMATION
BASIC CIRCUIT DESCRIPTION
The AD7S81 accepts eight analog inputs and sequentially converts each input into an eight-bit binary word using the successive approximation technique. The conversion results are
stored in an 8 X 8 bit dual-port RAM. The device runs either
direcdy from the microprocessor clock (in 6800 type systems)
or from some suitable signal (e.g. ALE in 808S type systems).
Most applications require only a -10V reference and a +SV
supply. Start-up logic is included on the device to establish
the correct sequences on power-up. A maximum of 800 clock
pulses are required for this period. Figure 1 shows the AD7S81
functional diagram.
Automatic interleaved DMA is provided by on-chip logic to
ensure that memory updates take place at.instants when the
microprocessor is not addressing memory. Memory locations
are addressed by Ao, Al and Az. This address may be latched
by ALE for systems which feature a multiplexed address/data
bus or alternatively, for systems which have separate address
and data buses, the address latches can be made transparent by
tying ALE (pin 16) HIGH. CS (pin 13) activates three-state
buffers to place addressed data on the DBo - DB7 data output pins.
AID CIRCUIT DETAILS
In the successive approximation technique, successive bits,
starting with the most significant bit (DB7), are applied to the
input of the DIA converter. The DAC output is then compared
to the unknown analog input voltage, AIN (n), using a comparator. If the DAC output is greater than Am(n), the data
latch for the trial bit is reset to zero, and the next smaller data
bit is tried. If the DAC output is less than AIN(n), the trial
data bit stays in the "1" state, and the next smaller data bit is
tried. Each successive bit is tried, compared to AIN(n), and set
or reset in this manner until the least significant bit (DBc)
decision is made. The successive approximation register now
contains a valid digital representation of AIN(n). AIN(n) is
assumed to be stable during conversion.
The current weighting D/A converter is a precision multiplying
DAC. Figure 2 shows the functional diagram of the DAC as
used in the AD7581. It consists of a precision Silicon Chromium thin film RI2R ladder network and 8 N-channel MOSFET
switches operated in single-pole-double-throw.
Figure 1. AD7581 Functional Diagram
Conversion of a single channel requires 80 input clock periods
and a complete scan through all channels requires 640 input
clock periods. When a channel conversion is complete, the successive approximation register contents are loaded into the
proper channel location of the 8 X 8 RAM. At this time a
status signal output, STAT (pin 12), gives a short ~Eve
going pulse (8 clock periods). This negative going STAT pulse
is extended to 72 clock periods when channel 1 conversion is
complete. An external pulse-width detector connected to the
status pin can be used to derive conversion-related timing signals for microprocessor interrupts (see Channel Identification
opposite page). Simultaneous with STAT going low, the MUX
address is decremented. Eight clock periods later the next conversion is started.
The currents in each 2R shunt arm are binarily weighted i.e.,
the current in the MSB arm is VREF divided by 2R, in the
second arm is VREF divided by 4R, etc. Depending on the
D/A logic input (AID output) from the successive approximation register, the current in the individual shunt arms is steered
either to AcND or to the comparator summing point.
AIN (01
AIN (7) BoFS
COMPARATOR
I DBS
SUCCESSIVE
APPROXIMATION REGISTER
AGND
Figure 2. D/A Converter as Used in AD7581
3-298 ANALOG-TO-DIGITAL CONVERTERS
AD7581
TIMING AND CONTROL OF THE AD7581
CHANNEL SELECTION
Table I shows the truth table for the address inputs. The input
address is latched when ALE goes LOW. When ALE is HIGH
the address input latch is transparent.
A2
Al
AO
0
0
0
0
I
I
I
I
0
0
0
I
I
0
0
0
0
I
I
I
I
I
0
I
ALE
1
I
I
I
I
I
I
Channel Data
To Be Read
Channel 0
Channell
Channel 2
Channel 3
Channel 4
ChannelS
Channel 6
Channel 7
identifying signal by staying low for an additional 64 clock
periods over normal (8 clock periods) when channel 0 is active.
This is illustrated in Figure 4. Memory update takes place on a
rising edge of a clock pulse and is completed in 200ns. This
occurs 6 clock periods before STAT goes low.
FOR CHANNELS 1 TO 7
STAT
Sur--
80 CLOCK
~~
LJS
PERIODS~I
8 CLOCK
PERIODS
PREVIOUS CHANNEL
g~~:l~~~~TE
MUX ADDRESS
DECREMENTED
FOR CHANNEL 0 _
START NEXT
~
CONVERSION
g~~~NEL
WITH MSB
TR IAL
UPDATE
COMPLETE
n
~1
STAT
TIMING AND CONTROL
A typical timing diagram is shown in Figure 3. When CS is
HIGH, the three-state data drivers are in the high-impedance
state. When CS goes LOW the data drivers switch to the lowimpedance state (i.e., low impedance to DGND or to Voo).
Output data is valid after time tACC'
II
r~
---JI U
---l ~
1...- - : -_ _ _ _ _ _ _
~~~~fL ~ ~~~:;~:ANNEL ;~~I~~ ~:::::
64 CLOCK PERIODS
Table I. Channel Selection Truth Table
I-CLOCK
I 8PERIODS
CURRENT
1
8 CLOCK
UPDATE
COMPLETE, MUX
ADDRESS RESET TO
CHANNEL 7
Figure 4. STA T Output for Channel Identification
One simple circuit using the STAT output is shown in Figure
5. The time constant RC is chosen such that X2 ignores the
normal STAT low pulse width (8 clock periods wide) but
respond to the much wider STAT low pulse width (72 clock
periods wide) occurring during channel 0 conversion. Typically
for a Ills clock period C = O.022IlF, R = 1.8kU.
1/6CD4009A
Figure 3. Timing Diagram for the AD7581
SWITCHING TERMINOLOGY
tH: ALE pulse width requirement.
tALH:Address Valid to latch hold time.
tALS:Address Valid to latch set-up time.
tLCS: Address latch to Chip Select set-up time.
tcw: Chip Select pulse width requirement.
tACC : Chip Select to valid data propagation delay.
tcF: Chip Select to output data float propagation delay.
tcLz : Chip Select to low impedance data bus.
CHANNEL IDENTIFICATION
In some real-time applications, it may be necessary to provide
an interrupt signal when a particular channel receives updated
data. To achieve this, it is necessary to identify which channel
is currendy under conversion. The STAT output provides an
1/6CD40D9A
1/6CD4009A
Figure 5. Hardware Channel Identification
Another possibility is to use the microprocessor to interrogate
the STAT output and hence determine channel identity. A
simple routine is shown in Figure 6.
STAT
Figure 6. Software Channel Identification
ANALOG-TO-DIGITAL CONVERTERS 3-299
OPERATING THE AD7581
UNIPOLAR BINARY OPERATION
Figures 7a and 7b show the analog circuit connections and
typical transfer characteristic for unipolar operation (OV to
+10V). An AD584 is used for the -10V reference. Calibration
is as follows (device clocked i.e .• continuous conversions);
OFFSET.
Comparator offset is trimmed out via the bipolar offset pin
BOFS. R10. Rll and R12 comprise a simple voltage tap
buffered by A1 and feeding into BOFS'
1. Since comparator offset will be the same regardless of
which channel is active. take Ao. A1 and A2 LOW and
and exercise ALE to latch the address.
2. With AIN 0 = 19.5mV (1I2LSB) adjust Rll. i.e .• the offset
voltage on BOFS. until OB7 - OB1 are LOW and OBo (LSB)
flickers.
.2. Select required channel n via Ao. At. A2 and latch the
Address using ALE.
3. Adjust trimmer RN of selected chaI)nel until OB7 -OB1
are HIGH and the LSB (OBo) flickers.
4. Select next channel requiring gain trim and repeat steps
2 and 3.
UNIPOLAR (COMPLEMENTARY BINARY) OPERATION
Figures 8a and 8b show the analog circuit connections and
typical transfer characteristic for unipolar (complementary
binary) operation.
Calibration is as follows (continuous conversions);
OFFSET.
Comparator offset is trimmed out via the bipolar offset pin
BOFS. R10. Rll and R12 comprise a simple voltage tap buffered by A1 and feeding into BOFS.
1. Since comparator offset will be the same regardless of
which channel is active. take Ao. A1 and A2 LOW and
exercise ALE to latch the address.
2. With AIN 0 =-9.98V (-FS + 1I2LSB) adjust Rll. i.e.,. the
offset voltage on BOFS. until OB7 - OB1 are LOW and the
LSB (OBo) flickers.
R151Oko.,,,
Rl0'
"'5%
..vo-....."""-...,
......-+-i
~'~=
NOTES:
-lOY
lA', Rl0, R1l AND R12CAN BfOMITTED IF OFFSET TRIM
IS NOT REQUIRED AND Bon CAN BE TIED TO AGND.
tA1_AB AND AS CAN BE OMITTED IF GAIN TRIM IS
o--R""2\(1,~--'
"'5%
NOT REQUIRED.
Figure 7a. AD7581 Unipolar (OVto +10V) Operation (Output
Code is Straight Binary)
-15V
R13
GAIN (FULL SCALE)
In many applications gain adjustment is not required thus
removing the need for trimmers in the analog channels. For
channels requiring gain trim. the following procedure is recommended. Offset adjustment must be performed before gain
adjustment.
1. Apply +9.941V (FS - 3I2LSB) to all input channels
AIN (0-7).
OUTPUT
NOTES:
'Rl0, Rn AND R12 CAN BE OMITTED IF OFFSET TRIM IS NOT REQUIRED.
'At - R8 AND R9 cAN BE OMITTED IF GAIN TRIM IS NOT REQUIRED.
3Rl61Rl0fR12=5kO.IF Rl0, Rn AND R12ARE NOT USED,MAKE R16=5Id1.
TRANSITION
11111110
11111101
. . . ,,{L'
I
,,
,,
)-
'
00000010
00000001
00000000
_ _ _ _ _ _,
0.4&0.80 1.20
I
I.
9.92 9.96110.00
INPUT VOLTAGE, VOLTS (REFERRED TO ANALOG GROUND)
NOTE:
VREF '-----~:::.....:=::..riil
FULL SCALE
",,,,~DtE
o
1.21<
-lOY
APPROXIMATE BIT WEIGHTS ARE SHOWN FOR ILLUSTRATION.
BIT WEIGHT FOR A -1OV REFERENCE IS "'39. 'mY.
Figure 7b. Transfer Characteristic for Unipolar Circuit of
Figure 7a
3-300 ANALOG-TO-DIGITAL CONVERTERS
Figure Sa. AD7581 (OVto -10V) Operation (Output Code
is Complementary Binary)
GAIN (FULL SCALE)
In many applications gain adjustment is not rc;quired thus
removing the need for trimmers in the analog channels. For
channels requiring gain trim. the following procedure is recommended. Offset adjustment must be performed before gain
adjustment.
1) Apply -58.6mV (3/2LSB) to all input channels AIN (0-7).
2) Select required channel n via Ao. A1. A2 and exercise ALE
to latch the address.
3) Adjust trimmer RN of selected channel until OB7 - OB1 are
HIGH and the LSB (OBo) flickers.
4) Select next channel requiring gain trim and repeat step 2
and 3.
AD7581
OUTPUT
R151OkO.''''
CODE
R10'
""" "1
11111110
, 1111101
I
I
,,
,
,,
,
,,
r
..v
27>5%
'5V'O--_~-,
A' :>~-~~-~~
~'~==p-H+o
-10V
AIN 6
R12'
56k 5%
~Jt
R1420k
0.1'"
A~~~~G
0--'\jW''--1!..!J
I R22 2k
t
1
I
-5VTO+5V
-15V
:::::::;~
00000001
rAIN 7 R122k
0-......._-----'
R,3
'Ok
-,OY
I
I
00000000
_____ I
I
-10 -9.6 -9,2
-0.160
~,08
0
-0.120 -0.040
VI'IEf
L..-------"::....;:::...::~llll
•
INPUT VOLTAGE, VOLTS (REFERRED TO ANALOG GROUND)
NOTE:
APPROXIMATE BIT WEIGHTS ARE SHOWN FOR ILLUSTRATION.
BlrWEIGHT FOR A -1OY REFERENCE rS"'I::39.1mV.
Figure 8b. Transfer Characteristic for Unipolar Circuit of
FigureBa
ANALOG
SUPPlY RETURN
DIGITAL
SUpflL Y RETURN
~~,TO~S~', AND R12 CAN BE OMITTED IF OFFseT TRIM IS NOT REQUIRED.
2Rl _ RS AND R9 CAN BE OMITTED IF GAIN TRIM IS NOT REQUIRED.
3R16/R10/R12" 6.SkO.IF R10, Rl1 AND'R12 ARE NOT USED, MAKE Rt8'" 6••n.
BIPOLAR (OFFSET BINARY) OPERATION
Figures 9a and 9b illustrate the analog circuitry and transfer
characteristic for ±SV bipolar operation. Output coding is offset binary. Comparator offset correction is again applied to the
Bops pin.
Figure 9a. AD7581 Bipolar (-5V to +5V) Operation (Output
Code is Offset Binary)
Calibration is as follows (continuous conversions);
10000100
OFFSET,
1. Apply -4.980V (-FSI2 + 1I2LSB) to all input channels.
AIN (0-7).
2. Trim R11 of the comparator offset circuit until DB7 - DB1
are LOW and the LSB (DBo) flickers.
10000011
10000010
10000001
10000000 +---<............---<-+rf-l.-+----<>--+--I--!
01111111
GAIN (FULL SCALE)
1. Apply +4.941V (+FS/2 -3I2LSB) to all input channels.
AJN (0-7).
2. Select required channel n via A.a. Ai> Az. and latch the
address using ALE.
3. Adjust trimmer RN of selected channel until DB7 -DB1
are HIGH and the LSB (DBo) flickers.
4. Select next channel requiring gain trim and repeat steps
2 and 3.
S. Apply -19.SmV to each gain-trimmed channel. If the ADC
output code does not flicker between 01111111 and
10000000 repeat the calibration procedure.
01111110
01111101
01111100
01111011 LJ~--~~--~~--~~--r-~~
-200 -160 -120 -80 -40
0 +40 +80 +120 +160 +200
INPUT VOLTAGE, MILLIVOLT5 (REFERRED TO ANALOG GROUND)
NOTE:
APPROXIMATE BIT WEIGHTS ARE SHOWN FOR ILLUSTRATION.
BJT WEIGHT FOR 10V FUll SCALE IS = 39.1mV.
Figure 9b. Transfer Characteristic Around Major Carry for
Bipolar Circuit of Figure 9a
ANALOG-TO-DIGITAL CONVERTERS 3-301
I
INTERFACING THE AD7581
AB-A16
AD-AI5
iiD~--aI
VMAI-_ _
6800
.1 ________________
~
AD1581
~
8086A
ALE~--------------4-~
~
ADO - AD7
MULTIPLEXED
ADDRESS/DATA BUS (8)
00-07
Figure 11. AD7581!8085Interface
Figure 10. AD7581/6800 Interface
NOTES:
1. ANALOG AND DIGITAL GROUND
It is recommended that AcND and DGND be connected
locally to prevent the possibility of injecting noise into the
AD7S81. In systems where the AcND - DGND interne is
not local, connect back-to-back diodes (lN914 or equivalent) between the AD7S81 AGND and DGND pins.
3-302 ANALOG-TO-DfGfTAL CONVERTERS
2. LOGIC DEGLITCHING IN IlP APPLICATIONS
Unspecified states on the address bus (due to different rise
and fall times on the address bus) can cause glitches at the
AD7S81 CS terminal. These glitches can cause unwanted
reads. The best way to avoid glitches is to gate the address
decoding logic, e.g., with RD (8080), RD (8085) or VMA
(6800).
CMOS 12-Bit
Successive Approximation ADC
AD7582 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
12-Bit Successive Approximation ADC
Four High Impedance Input Channels
Analog Input Voltage Range of 0 to + 5V with Positive
Reference of + 5V
Conversion Time of 100p.s per Channel
No Missed Codes Over Full Temperature Range
Low Total Unadjusted Error ± 1LSB max
Autozero Cycle for Low Offset Voltage
Monolithic Construction
GENERAL DESCRIPTION
The AD7582 is a medium speed, 4-channel 12-bit CMOS AID
converter which uses the successive approximation technique to
provide a conversion time of l00",s per channel. An auto-zero
cycle occurs at the start of each conversion r~sulting in very low
system offset voltages, typically less than l00",V. The device is
designed for easy microprocessor interface using standard control
signals; CS (decoded device address), RD (READ) and WR
(WRITE). The 4-channel input multiplexer is controlled via
address inputs AO and AI.
Conversion results are available in two bytes, 8LSB's and 4MSB's,
over an 8-bit three state output bus. Either byte can be read
first. Two converter busy flags are available to facilitate polling
of the converter's status.
The analog input voltage range is OV to + 5V when using a
reference voltage of +5V. The four analog inputs are all high
impedance inputs with tight channel-to-channel matchingtypically O.ILSBs.
AD7582 FUNCTIONAL BLOCK DIAGRAM
II
DATA
OUT
iii)
cs
WR
BVSl
DGND
PRODUCT HIGHLIGHTS
I. The AD7582 is a complete 4 channel 12-bit AID converter in
either a 28-pin DIP or 28-terminal surface mount package
requiring only a few passive components and a voltage
reference.
2. Autozero cycle realizes very low offset voltages, typically
IOOILV .
3. The four channel input multiplexer (user addressable) features
high input impedance and excellent channel-to-channel
matching.
4. Standard microprocessor control signals to allow easy interfacing to most popular 8- and 16-bit microprocessors.
ORDERING INFORMATION l
Total
Unadjusted
Error
Tmin-T""",
±lLSB
±lLSB
Temperature Range and Package Options2
Oto +70"C
Plastic (N-28)
- 25°C to + 85°C
Hermetic' (D-28)
AD7582KN
AD7582BD
-55°Cto + 125°C
Hermetic' (D-28)
AD7582TD
PLCC4 (P-28A)
LCCC s (E-28A)
AD7582KP
AD7582TE
NOTES
ITo order MIL-STD-883, Class B processed parts, addl883B to part number.
Contact your local sales office for military data sbeet.
'See Section 14 for package outline infortDation.
3Analog Devices reserves the right to ship either ceramic (package outline 0-28) or cerdip
(package outline Q-28) hermetic packages.
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadle.. Ceramic Chip Carrier.
ANALOG-TO-OIGITAL CONVERTERS 3-303
SPECIFICATIONS
(VIII =
+l5V, Vee = +5V, Vss= -5V, VREF = +5.DV
fCII =140kHz exIBmaI, aU spaciIications T... to T_ unless otIlIIwise noted).
Parameter
KVenion'
BVersion'
TVersion'
Units
ACCURACY
Resolution
Total Unadjusted Error>
Differentisl Non1inesrity
Full Scale Error (Gain Error)
12
±I
±I
± 114
12
±I
±I
±1/4
12
±I
±I
± 114
Bits
LSBmax
LSBmax
LSBmax
Offset Error
±1I4
±1I4
±1/4
LSBmax
Channel to Channel Mismatch
±1/4
±1I4
±1/4
LSBmax
Oto +5
S
Oto +5
S
Oto +5
S
V
pFtyp
10
100
10
100
10
100
nAmax
nAmax
REFERENCE INPUT
VREF(ForSpecifiedPerformance)
VREpRange
VREF Input Reference Current
+5
+4to +6
1.0
+5
+4to +6
1.0
+5
+4to +6
1.0
V
V
mAmax
±5%
Degraded transfer accuracy
VREF = +5.0V
POWER SUFPLY REJECTION
VnnOnly
± liS
±I/S
±IIS
LSBtyp
±IIS
±IIS
±IIS
LSBtyp
Vnn = + 14.25Vto + 15.75V
Vss= -5V
Vss= -4.75Vto -5.25V
V nn = +15V
+O.S
+2.4
+O.S
+2.4
+O.S
+2.4
V max
V min
Va;= +5V ±5%
±I
+10
10
±I
+10
10
±I
+10
10
J.LAmax
J.LAmax
pFmax
VIN=OtoVa;
+O.S
+3.0
±IO
+1.5
+O.S
+3.0
±IO
+1.5
+O.S
+3.0
±IO
+1.5
V max
V min
".Amax
mAmax
Va;= +5V±5%
ANA1.OG INPUTS
Analog Input Range
CAIN, On Channel Input Capacitance
lAIN, Input Leakage Current
+ 25·C
Tmin to Tmax
VssOnly
LOGIC INPUTS
RD(Pin IS), CS (Pin 19), WR (Pin 20)
BYSL (Pin 21), AO (Pin24), Al (Pin 25)
V,L Input Low Voltage
VIH Input High Voltage
lIN Input Current
+ 25"C
Tmm to Tmax
C IN Input Capacitance3
CLK (Pin 23)
VIL, Input Low Voltage
VIH, Input High Voltage
I'L> Input Low Current
IIH' Input High Current
Conditions/Comments
All channels, AINO-AIN3
No missing codes guaranteed
AIl channels, AINO-AIN3
Full Scale TC is typically 5ppmI"C
All channels, AINO-AIN3
Offset Error TC is typically 5ppm/"C
V REP = +5.0V
AINO-AIN3;Oto +5V
LOGIC OUTPUTS
DBO-DB7 (Pins 10-17), BUSY (Pin 22)4
VOL> Output Low Voltage
VOH , Output High Voltage
Floating State Leakage Current
(Pins 10-17)
Floating State Output Capacitance
+0.4
+4.0
+0.4
+4.0
+0.4
+4.0
V max
V min
Va;= +5V ±5%,I SINK =1.6mA4
Vee = +5V ±S%,lsoURCB =200J.LA
±I
IS
±I
IS
±I
IS
J.LAmax
pFmax
Vour=OVtoVee
CONVERSION TIMES
With External Clock
With Internal Clock, TA = + 2S·C
100
100/150
100
100/150
100
100/150
".smin
"..minlmax
fcLK = 140kHz
+15
-5
+5
7.5
7.5
100
1.0
75
+15
-5
+5
7.5
7.5
100
1.(1
75
+15
-5
+5
7.5
7.5
100
1.0
75
V NOM
V NOM
V NOM
mAmax
mAmax
".Atyp
mAmax
mWtyp
POWER REQUIREMENTS·
Vnn
Vss
Vee
Inn
Iss
Ia;
Power Dissipation
NOTES
ITemperatureRangeasfollows: K VersiOD;Oto +7O"C
BVersioDj -2SOCto +85OC
TVersionj -S5OCto+ 1250(:
2Includes Full Scale Error, Offset Error and Relative Accuracy.
3Samp1e tested to ensure compliance.
'I'INK for BUSY (pin22) is 1.0 millisrop.
5Conversion Time includes autozero cycle time.
6powersuppIycurrentismeasuredwhenAD7582isinactivei.e., WR~RD~CS=BUSY~LogicHIGH.
Specifications subiecttochange without notice.
3-304 ANALOG-TO-DIGITAL CONVERTERS
Using recommended clock components
as shown in Figure 6.
± 5% for specified performance
± 5% for specified performance
± 5% for specified performance
Typically4mA with Vnn = + 15V
Typically 3mA with V ss = - 5V
V ,N = V,L or VIH
WR = RD = CS = BUSY = Logic HIGH
AD7582
TIMING SPECIFICATlONS1 (Yuu = + 15V, Vee = +5V, Vss= -5V, vREF = +5Vl
Parameter
tl
t2(INT)2
t2(EXT)2
t3
r..
ts
tt;
t7
ts
t9
tlO
til
tl2
tIl
tl/
Limit at + 250C
(AU Grades)
Limit at T IIW" T ...... Limit at T miD. T ......
(K & B Grades)
(TGrade)
Units
0
200
10
0
130
200
0
20
0
0
200
0
50
0
150
200
20
130
0
240
0
280
10
0
200
300
0
20
0
0
280
0
50
0
200
280
20
180
10
0
160
250
0
20
0
0
240
0
50
0
180
240
20
160
Conditions/Comments
nsmin
nsmin
,,"smin
nsmin
nstyp
nsmax
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nstyp
nsmax
nsmin
nsmax
CS to WR Setup Time
WR Pulse Width (Internal Clock Operation)
WR Pulse Width (External Clock Operation)
CS to WR Hold Time
WR to BUSY Propagation Delay
AO, Al Valid to WR Setup Time
AO,Al Valid to WR Hold Time
BUSYtoCSSetupTime
CS to RD Setup Time
RD Pulse Width
CS to RD Hold Time
BYSL to RD Setup Time
BYSL to RD Hold Time
RD to Valid Data (Bus Access Time)
RD to Three State Output
(Bus Relinquish Time)
NOTES
'Timing Specifications are sample tested at + 25"<: to ensure compliance. All input control signal. are
specified with t, = t,= 20ns (10% to 90% of + 5V) and timed from a voltage level of + 1.6V. Data i. timed from
VIH, V[LorVOH, VOLo
'When u.ing an external clock source the WR pulse width must be extended to provide the minimum
auto-zero cycle time of 10..... See "External Clock Operation".
't"i. measured with the load circuits of Figure 3 and defmeda. the time required for an output to croasO.8V or 2.4V.
the circuits of Figure 4.
Specifications subject to change without notice.
4 t '4 i. defmed as the time required for the data lines to change 0.5V when loaded with
CS (PIN
19)
t,
t,
t,
WR /PIN20)
wJ:'- _______
~
BU'V IPIN 22)
t
AD, At
(PINS 24.25)
-
.!...-..,.,
!-~v'l,~P7777/77
~
Figure 1. Stan Cycle Timing
NOTES
THf TWO·BYTE CONVERS(2.N RE...I.ULT CAN BE READ IN flTHfR ORDER. fIGURE IS fOR LOW BYTE. HIGH BYTE ORDER.
IF BV8l CHANGES WHILE CS 81 RD ARE LOW THE DATA WlU CHANGE TO REFLECT THE BVSL INPUT.
Figure 2. Read Cycle Timing
5V
DBN:r--r-:
lk,&
~
'OOpF
DGND
a. High-Z to VOH
5V
~3'
DBNT
~'OOPF
OGND
b. High-Z to VOL
Figure 3, Load Circuits for Access Time Test (t ,3 )
DBN--r:-I:
~lk_~'OPF
DGND
a. VOH to High-Z
~ 3.
DBNt
10pF
JOGNO
b. VOL to High-Z
Figure 4. Load Circuits for Output Float Delay Test (t ,4 )
ANALOG-TO-DIGITAL CONVERTERS 3-305
II
Operating Temperature Range
Commercial (K Version)
Industrial (B Version) .
Extended (T Version) ..
Storage Temperature . . .
Lead Temperature (Soldering, 10secs)
Power Dissipation (any Package)
to +75°C . . . . . . . . . . . . . .
Derate above + 75°C by
ABSOLUTE MAXIMUM RATINGS·
eTA ~ + 25"C unless otherwise stated)
VDDto DGND .
Vss to DGND ..
AGNDtoDGND
Vccto DGND
VREF to AGND .
AIN (0-3) to AGND
Digital Input Voltage to DGND
(Pins 18-21, 23-25) . . . . .
Digital Output Voltage to DGND
(Pins 10-17, 22) . . . . . . . .
. . . . -0.3V, + 17V
. . . . +0.3V, -7V
-0.3V, VREF +0.3V
-0.3V, VDD +0.3V
-0.3V, VDD +O.3V
-0.3V, VDD +O.3V
-0.3V, VDD +0.3V
0 to +70°C
. "
- 25°C to + 85°C
- 55°C to + 125°C
'-- 65°C to + 150°C
. +300°C
1,OOOmW
10mW/"C
*Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
-0.3V, VDD +0.3V
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~OEVICE
PIN CONFIGURATIONS
LCCC
DIP
N
Z
Va
NC
;;
co
z
;;
:1
"
PLCC
g
>
co
N
Z
CJ
Z
;;
~
z
'"
0
!:iCJ
:}
CJ
Z
0
A1
AD
ClK
BUSY
AD7582
AD7582
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
BYSL
W-
CS
DB7
DB7
19 CS
086, 11
19
CS
Rii
DBS
DBO (LSS)
DB4
DB1
DB.
DB2
O!
l!!
0
0
NC = NO CONNECT
a
0
111
0
1ii
0
;;;
~
I~
8
NC = NO CONNECT
READING DATA
The 12-bit conversion data plus a converter status flag are available
over an 8-bit wide data bus. Data is transferred from the AD7582
in right-justified format (i.e., the LSB is the most right-hand bit
in a 16-bit word). Two READ operations are required, the Byte
Select (BYSL) input determining which byte-8 least significant
bits or 4 most significant bits plus status flag-is to be read first.
Since the AD7582 uses the successive approximation register
(SAR) to hold conversion results (refer to Functional Diagram),
it is necessary to wait until a conversion is finished before reading
valid 12-bit data. Executing a READ instruction (HIGH or
LOW byte) to the AD7582 while a conversion is in progress
will place the existing contents of the SAR onto the data bus.
Three different approaches can ensure valid 12-bit data is available
for reading.
3-306 ANALOG-TO-DIGITAL CONVERTERS
1. Insert a software delay greater than the ADC conversion time
between the conversion start instruction and the data read
instructions.
2. At user-defined intervals after a conversion start instruction,
poll the internal converter status flag, BUSY. This signal is
available on pin 10 during a HIGH byte READ instruction
and is the most left-hand bit in a 16-bit right-justified word.
The status bit can be shifted into a microprocessor's accumulator-carry position for testing (BUSY is HIGH during
conversion).
3. Use the externally available BUSY (pin 22) signal as an interrupt
to the microprocessor. This signal is LOW during a conversion
and returns HIGH at conversion end.
Executing a WRITE instruction while conversion is in progress
will restart the conversion.
AD7582
PIN FUNCTION DESCRIPTION
PIN
MNEMONIC
DESCRIPTION
I
CAZ
Autozero Capacitor Input. Connect other side of capacitor to AGND.
2
AINO
Analog Input, channel 0
3
AINI
Analog Input, channell
4
AIN2
Analog Input, channel 2
5
6
AIN3
VREF
Analog Input, channel 3
Voltage reference input. The AD7582 is specified with VREF = + 5.0V.
Analog Ground
7
AGND
8
DGND
Digital Ground
9
Vex
Logic Supply. For Vex =
+ 5V digital inputs and outputs are TTL compatible.
Three state data outputs. They become active when CS & RD are brought low. Individual pin function
is dependent upon the Byte Select (BYSL) input.
10-17
DATABUSOUTPUT,CS&RD
=LOW
BYSL = LOW
Pin 10
BYSL = HIGH
BUSyl
Pin II
LOW2
DB6
Pin 12
LOW2
DB5
Pin 13
LOW2
DB4
Pin 14
DB II (MSB)
DB3
Pin IS
DBIO
DB2
Pin 16
DB9
DBI
Pin 17
DBS
DBO(LSB)
DB7
'BUSY (Pin IO)is a converter status flag and is HIGH during a conversion.
'Pins 11-13 output a logic LOW when BYSL is HIGH.
DBll-DBOarethe l2-bit conversion results, DBII is the MSB.
18
READ input. This active LOW signal, in combination with CS, is used to enable the output data threestate drivers.
19
CHIP SELECT Input. Decoded device address, active LOW. Used in combination with either RD or
WR for control.
20
WRITE Input. This active LOW signal, in combination with CS, is used to stan a new conversion on a selected
channel. When the AD7582 internal clock is used, the minimum WR pulse width is t2 (INT). When an external
clock source is used, the minimum WR pulse width must be extended to include the autozero cycle time.
For external clock operation, the minimum WR pulse width is t2 (EXT).
21
BYSL
BYTE SELECT. This control input determines whether the high or low byte of data is placed on the output data
bus during a data READ operation (CS & RD LOW). See description of pins 10-17.
22
BUSY
BUSY indicates converter status. BUSY is LOW during conversion, otherwise BUSY is held at a logic HIGH.
23
CLK
CLOCK Input for internal/external clock operation.
Internal: Connect Rcr..K and Ca.Kl /CcLK2 timing components. See Figure 6 and Figure 7.
External: Connect extema174HC compatible clock source as shown in Figure 8.
24
AO
Address Input AO. See pin 25 description.
25
Al
Address Input AI. Address inputs AO and Al select the input channel to be converted. The address input
latch'IS transparent wh en CS & WR are LOW The address inputs are latched by WR returning HIGH.
CHANNEL SELECTED
Al AO
26
N/C
0
0
1
0
1
0
1
1
No connect pm.
AINO
AINI
AIN2
AIN3
27
Vss
Negativesupply, - 5V.
28
VDD
Positive supply,
+ 15V.
ANALOG-TO-OIGITAL CONVERTERS 3-307
II
Operating Infonnation
OPERATIONAL DIAGRAM
An operational diagram for the AD7582 is shown in Figure 5.
The only passive components required are the autozero capacitor
CAZand timing components Rcr.K, Ccr.Kl & Ccuu for the
internal clock osciJlator. If the AD7582 is to be used with an
external clock source, then only CAZ is required. Individual pin
functions are described in detail on the previous page.
ANALOG INPUTS
o TO +5V.
REfERRED TO
AGND
+5.0V~--r.;"\
~---------t~~-ov~
+5V_---"'J
DGND
Figure 5. AD7582 Operational Diagram
INTERNAL CLOCK OPERATION
The clock circuitry for internal clock operation is shown in
Figure 6 and the AD7582 operating waveforms are shown in
Figure 7.
Vee. +5V
'N.'·~DGND
4x2rri::
new conversion, the input multiplexer is switched to the selected
channel N, via address inputs AO, AI. The autozero capacitor
C AZ now charges to AIN N-Vos where Vos is the input offset
voltage of the autozero comparator.
A minimum time of lOJl.s is required for this autozero cycle. In
applications using the internal clock oscillator, it is not necessary
for WR to remain LOW for this period of time since it is automatically provided by the AD7582. This is achieved by switching
a constant current load across the clock capacitors, Ccr.Kl and
Ccr.K2, causing the voltage at the CLK input pin to slowly
decay from Vee. This occurs after WR returns HIGH; WR
returning HIGH also latches the multiplexer address inputs AO,
Al (see Figure 7). The Schmitt trigger circuit monitoring the
voltage on the CLK input ends the autozero cycle when its
LOW input trigger level is reached. At this point, the constant
current load across the clock capacitors is removed allowing
them to charge towards Vee via Rcr.K. When the voltage at the
CLK input reaches the mGH trigger level, the constant current
load is replaced across Ccr.Kl and CcLK2. The MSB decision is
made when the LOW trigger level is reached. This cycle repeats
itself 12 times to provide 12 clock pulses for the conversion
cycle. The circuit arrangement of Figure 6 provides the relatively
slow autozero cycle time at the beginning of a conversion while
allowing the clock oscillator to speed up once the autozero cycle
is complete.
EXTERNAL CLOCK OPERATION
For external clock operation Rcr.K, Ccr.Kl and CCLK2 are discarded
and the CLK input is driven from a 74HC compatible clock
source. The AD7582 WR pulse width must now be extended to
provide the minimum autozero cycle time of lOJl.s since this is
no longer provided automatically by the AD7582. Referring to
the operating waveforms of Figure 9, the minimum WR pulse
width when using an external clock source is t2 (EXT). Multiplexer
address inputs AO and AI, in addition to the CS input must
now remain valid for the external WR pulse width. It is not
necessary to synchronize the external clock source with the
extended WR pulse width, the MSB decision being made on the
second falling edge of the clock input after the WR input returns
HIGH.
L.. _ _J
74HC COMPATIBLE
CLOCK SOURCE,
felk = 140kHz
Figure 6. Circuitry Required for Internal Clock Operation
WflR
Figure 8. External Clock Operation
T =.
AO'A'~
,AII. .UTS
LATCHED
~
,--
Wfl
--------------------------------~I
MINIMUM
Vee
M,A'
C'~-j
AUTOZEAOCYCLE
LEVELS DERNED BY
_
-t=.
=x I
lEXT'·1,------J/,f-'- - - - -
I
x:=
{INPUT SCHMm TAIOGER
Itt t t t t t t t t t
t~
DBn OB10 OBI DBa DB' D88 DRS DM DB3 012 DB1 DRO
(_I
ILSBI
DECISION POINTS
"1t(INTIIS THE I'IOIMUM WRfTE PULSE WIDTH wttEN UstNG
WJERNAI. CLOCK. SEE TIMINO SPEClFlCATtONS.
Figure 7. Operating Waveforms - Internal Clock
Berween conversions (BUSY = mGH) the AD7582 is in the
autozero cycle. When WR goes LOW (with CS LOW) to start a
3-308 ANALOG-TO-DIGITAL CONVERTERS
DECISION POINTS
~EXTIIS TttE MINIMUM WAITE PULH WIDTH WHEN USING
EXTERNAL CLOCK. SEE TIMWG SPECtI'ICATIONS.
Figure 9. Operating Waveforms - External Clock
LC2MOS
High-Speed 12-Bit ADC
AD7672 I
t-.ANALOG
WDEVICES
FEATURES
12-Bit Resolution and Accuracy
Fast Conversion Time
AD7672XX03 - 3p.s
AD7672XX05 - 5p.s
AD7672XX10 - 10p.s
Unipolar or Bipolar Input Ranges
Low Power: 110mW
Fast Bus Access Times: 90ns
Small, 0.3", 24-Pin Package and 28-Terminal
Surface Mount Packages
GENERAL DESCRIPTION
The AD7672 is a high-speed 12-bit ADC, fabricated in an advanced, mixed technology, Linear-Compatible CMOS (LC2MOS)
process, which combines precision bipolar components with
low-power, high-speed CMOS logic. The AD7672 uses an accurate
high-speed DAC and comparator in an otherwise conventional
successive-approximation loop to achieve conversion times as
low as 3....s while dissipating only llOmW of power.
To allow maximum flexibility the AD7672 is designed for use
with an external reference voltage. This allows the user to choose
a reference whose performance suits the application or to drive
many AD7672s from a single system reference, since the reference
input of the AD7672 is buffered and draws litde current. For
digital signal processing applications where absolute accuracy
and temperature coefficients may be unimportant, a low-cost
reference can be used. For maximum precision, the AD7672
can be used with a high-accuracy reference, such as the ADS88,
when absolute 12-bit accuracy can be obtained over a wide
temperature range.
An on-chip clock-circuit is provided which may be used with a
crystal for accurate definition of conversion time. Alternatively,
the clock input may be driven from an external source such as a
microprocessor clock.
AD7672 FUNCTIONAL BLOCK DIAGRAM
AIN1 AIN2
•
DB11
OB4 DGND
DB3
DBO
PRODUCT HIGHLIGHTS
1. Fast, 31Ls, SILS and lOlLS conversion speeds make the AD7672
ideal for a wide range of applications in telecommunications,
sonar and radar signal processing or any high-speed data
acquisition system.
2. LC2 MOS circuitry gives high precision with low power drain
(llOmW typ).
3. Choice of 0 to + SV, 0 to + lOY or ±SV input ranges, accomplished by pin-strapping.
4. Fast, simple, digital interface has a bus access time of 90ns
allowing easy connection to most microprocessors.
S. Available in space-saving 24-pin, 0.3" DIP or surface mount
package.
The AD7672 also offers flexibility in its analog input ranges,
with a choiceofOto +SV,Oto +IOVand ±SV.
The AD7672 is also designed to operate from nominal supply
voltages of + SV and - 12V. This makes it an ideal choice for
data acquisition cards in personal computers where the negative
supply is generally -12V.
The AD7672 has a high-speed digital interface with three-state
data outputs and standard microprocessor control inputs (Chip
Select and Read). Bus access time of only 90ns allows the AD7672
to be interfaced to most modern microprocessors.
The AD7672 is available in a variety of space-saving packages;
plastic and hermetic 24-pin "skinny" DIP and 28-pin ceramic
and plastic chip carrier.
ANALOG-TO-DIGITAL CONVERTERS 3-309
SPECIFICATIONS
.
Parameter
ACCURACy2
Resolution
Integral Nonlinearity @ + 25"<:
TmlatoT....
Differential Nonlinearity
UnipolarOffsetError@ +25"<:
TmlatoT.....
UnipolarGainError@ +25"<:
TmlatoT....
Bipolar Zero Error@ + 25"<:
TmJatoT....
Bipolar Gain Error@ + 25"<:
T .... toT....
ANALOG INPUT
Unipolar Input Current
Bipolar Input Current
REFERENCE INPUT
VREF (For Specified Performance)
Input Reference Current
POWER SUPPLY REJECTION
VooOnly,CFSChange)
V ss Only, CPS Change)
LOGIC INPUTS
CS,RD,CLKIN
VINLo Input Low Voltage
V INH , Input High Voltage
C IN , 3 Input Capacitance
CS,RD
lIN' Input Current
CLKIN
lIN' Input Current
LOGIC OUTPUTS
DBII-DBO, BUSY, CLK OUT
VOL, Output Low Voltage
VOH, Output High Voltage
Floating-State Leakage Current
DBlI-DBO
Floating-State Output Capacitance3
CONVERSION TIME
AD7672XX03
Synchronous Clock
Asynchronous Clock
AD7672XX05
Synchronous Clock'
Asynchronous Clock
AD7672XXI0
Synchronous Oock
Asynchronous Clock
POWER REQUIREMENTS
Voo
Vss
100'
Iss'
Power Dissipation
(Yoo = 5V ±5%, Vss = -12V±10%, VREF = -5V unless otherwise noted.
fcur- 4MHz for AD7672XX03, 2.5MHz for AD7672XX05, 1.25MHz for AD7672XX10.
All Specifications Tnm to Tmax unless othtnwise noted. Specifications apply to Slow Memory Mode).
Test ConditionslComments
KVenion'
LVenion' BVeninn l CVenion l Units
12
±I
±I
±0.9
±5
±6
±5
±7
±5
±6
±5
±7
12
± 112
± 112
±0.9
±3
±4
±4
±6
±3
±4
±4
±6
12
±I
±I
±0.9
±5
±6
±5
±7
±5
±6
±5
±7
12
± 112
±1/2
±0.9
±3
±4
±4
±6
±3
±4
±4
±6
Bits
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
3.5
± 1.75
3.5
± 1.75
3.5
± 1.75
3.5
± 1.75
mAmax
mAmax
Input Ranges: Oto5VorOto 10V
InputRange: ±5V
-;
-5
-s
-5
-3
-3
-3
Volts
.,.Amax
± 10/0
-3
±I
±I
±I
±I
±I
±I
±I
±I
LSBtyp
LSBtyp
Vss= -12V, Voo= +4.75Vto +5.25V
Voo= +5V, Vss= - 1O.8Vto -13.2V
+0.8
+2.4
10
+0.8
+2.4
10
+0.8
+2.4
10
+0.8
+2.4
10
V max
V min
pFmax
Voo = 5V ±5%
±IO
±IO
±IO
±IO
.,.A max
VIN = OtoVoo
±20
±20
±20
±20
.,.Amax
V IN = OtoV oo
+0.4
+4.0
+0.4
+4.0
+0.4
+4.0
+0.4
+4.0
V max
Vrnin
ISINK = 1.6mA
IsouReE = 200.,.A
±IO
15
±IO
IS
±IO
IS
±IO
IS
.,.A max
3.125
3/3.25
-
3.125
3/3.25
-
5
4.8/5.2
5
4.8/5.2
5
4.8/5.2
5
4.8/5.2
.,.smax
10
9.6110.4
10
9.6/10.4
10
9.6/10.4
10
9.6110.4
.,.smax
feLK = 1.25MHz
.,.sminlmax
+5
-12
7
-12
110
179
+5
-12
7
-12
110
179
+5
-12
7
-12
110
179
+5
-12
7
-12
110
179
VNOM
VNOM
mAmax
mAmax
mWtyp
mWmax
NOTES
ITemperature range as follows: K, L versions; L 0 to + 70"C.
B, eversions; - 2SOC to + 85"<:.
'VDD~SV, Vss~ -12V, lLSB~fSl4096
3Sample tested [0 ensure compliance.
'Power supply current is measuredwbm AD7672 is iDactive, i. •. ,CS ~ RD~ BUSY~ HIGH.
SpecifICations subject to change without notice.
3-310 ANALOG-TO-DIGITAL CONVERTERS
-
Tested Range ± 5V
No Missing Codes Guaranteed
InputRange:Oto5VorOto 10V
Typical TC is 2ppml"C
Input Range: Oto5VorOto 10V
Typical TC is 2ppml"C
Input Range: ± 5V
Typical TC is 2ppml"C
Input Range: ± 5V
Typical TC is 2ppml"C
pFmax
Applies to K and B Grades Only
.,.smax
feLK = 4MHz. See Under
.,.sminlmax Control Inputs Synchronization
feLK = 2.5MHz
J.l.smin/max
± 5% for Specified Performance
± 10% for Specified Performance
CS=RD=Voo,AINI =AIN2=5V
CS = RD = Voo, AINI = AIN2 = 5V
(Yoo
=
5V ±5%, Vss = -12± 10%, VRff
=-
5V unless otherwise noted.
feu(. 2.5MHz for AD7672XX05, 1.25MHz for AD7672XX10. All Specifications T
SPECIFICK1'TIONS unless
otherwise noted. Specifications apply to Slow Memory Mode).
min
Parameter
ACCURACV2
Resolution
Integral Nonlinearity@ + 2S"C
T_toT"""
Differential Nonlinearity
UnipolsrOffsetError@ +2S"C
T_toT....
Unipolsr Gsin Error@ + 2S"C
Tmin toTmu:
Bipolar Zero Error @ + 2SoC
TJnintoTmu
Bipolsr Gain Error@ + 2S"C
Tmin toTmu:
ANALOG INPUT
U nipolsr Input Current
Bipolar Input Current
REFERENCE INPUT
V REF (For Specified Performance)
Input Reference Current
POWER SUPPLY REJECTION
VooOnly,(FSChange)
Vss Only, (FS Change)
LOGIC INPUTS
CS,RD,CLKIN
VINL> Input Low Voltage
V INH , Input High Voltage
C IN ,' Input Capacitance
CS,RD
lIN' Input Current
CLKIN
lIN' Input Current
LOGIC OUTPUTS
DBII-DBO, BUSY, CLK OUT
VOL' Output Low Voltage
VOH , Output High Voltage
Floating-State Leakage Current
DBII-DBO
Floating-State Output Capacitance'
CONVERSION TIME
AD7672XXOS
Synchronous Clock
Asynchronous Clock
AD7672XXIO
Synchronous Clock
Asynchronous Clock
POWER REQUIREMENTS
Voo
Vss
100'
Iss'
Power Dissipation
to T....
TVersion'
UVersion'
Units
12
±I
±I
±0.9
±S
±6
±S
±7
±S
±6
±S
±7
12
± 112
±3/4
±0.9
±3
±4
±4
±6
±3
±4
±4
±6
Bits
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
3.5
± 1.75
3.5
± 1.75
rnA max
rnA max
Input Ranges: 0 to SV or 0 to 10V
InputRange: ±SV
-5
-S
-3
Volts
....Amax
±l%
-3
±I
±I
±I
±I
LSBtyp
LSBtyp
Vss= -12V, Voo= +4.7SVto +S.2SV
Voo= +SV, Vss= -1O.8VIO - I3.2V
+0.8
+2.4
10
+0.8
+2.4
10
V max
V'min
pFmax
Voo = SV ±S%
±IO
±)O
....Amax
VIN = OtoV oo
±20
±20
....Amax
VIN = OtoV oo
+0.4
+4.0
+0.4
+4.0
V max
V min
ISINK = 1.6mA
ISOURCE = 200....A
±IO
IS
±IO
IS
JLAmax
pFmax
S
4.8/5.2
S
4.8/5.2
....smax
....sminlmax
fCLK '= 2.SMHz. See Under
Control Inputs Synchronization
10
9.6/10.4
10
9.6/10.4
....smax
....sminlmax
feLK = 1.25MHz
+5
-12
7
-12
llO
179
+5
-12
7
VNOM
VNOM
mAmax
mAmax
mWtyp
mWmax
± 5% for Specified Performance
± 10% for Specified Performance
CS = RD= Voo,AINI = AIN2 = 5V
CS = RD= Voo,AINI =AIN2 = 5V
-12
llO
179
AD7672
Test Conditions/Comments
Tested Range ± SV
No Missing Codes Guaranteed
Input Range: 0 to SV orO to 10V
Typical TC is 2ppmI"C
Input Range: 0 to SV or 0 to 10V
Typical TC is 2ppmI"C
InputRange: ±SV
Typical TC is 2pprnf'C
InputRange: ± SV
Typical TC is 2ppml°C
NOTES
ITempenrurerangeasfoUows: T, Uversions; - SSOCto + 12SOC.
2VDD~5V. Vss~ -12V.ILSB~FSJ4096
JSampie tested. to ensure compliance.
·PowersupplycurrentismeasuredwhenAD7672isinactive,i.e.,CS
= RD= BUSY =
HIGH.
Specifacations subject to chanae without notice.
ANALOG-TO-DIGITAL CONVERTERS 3-311
TIMING CHARACTERISTICS 1 (Voo=5V, Vss= -12V)
Parameter
t1
t2
t/
t4
t5
l{;2
t73
t8
Limitat + 25°C
(All Grades)
Limit at T min , Tmax
(K, L, B, C Grades)
Limit at T min, T max
(T, UGrades)
Units
Conditions/Comments
0
190
90
125
t3
0
70
20
75
200
0
230
110
ISO
t3
0
90
20
85
200
0
270
120
170
t3
0
100
20
90
200
nsmin
nsmax
nsmax
nsmax
nsmin
nsmin
nsmax
nsmin
nsmax
nsmin
CS to RD Setup Time
RD to BUSY Propagation Delay
Data Access Time after RD, C L = 20pF
Data Access Time after RD,C L = lOOpF
RD Pulse Width
CS to RD Hold Time
Data Setup Time after BUSY
Bus Relinquish Time
Delay Between Successive
Read Operations
NOTES
'Timing Specifications are sample tested at + 2S'C to ensure compliance. All input control signals are specified with tr ~ tf ~ Sns (10% to 90% of + SV)
and timed from a voltage level ofl.6V.
't, and to are measured with the load circuits of Figure I and defmed as the time required for an output to crossO.8V or 2.4V.
't7 is defined as the time required for the data lines to change O. SV when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
13kH
DBNo---~------~---o
DBN~
Cl
~DGND
a. High-Z to VOH (t3 )
and VOL to VOH (t6)
b. High-Z to VOL (t3 )
and VOH to VOL (t6)
Figure 1. Load Circuits for Access Time
13kll
DBNo---~--~--~---o
DBN~
10pF
~DGND
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Output Float Delay
3-312 ANALOG-TO-DIGITAL CONVERTERS
WARNING!
0
~~DEVICE
ABSOLUTE MAXIMUM RATINGS*
(TA ~ + 2S'C unless otherwise noted)
· . .. -0.3V to +7V
Vooto DGND .
· . . . +O.3V to -17V
Vss to DGND ..
AGNDtoDGND
-O.3V to Voo +0.3V
AINl, AIN2 to AGND
· . . . - l5V to + l5V
VREFtoAGND . . . .
Vss -0.3V to Voo +O.3V
Digital Input Voltage to DGND
-0.3V to V DD +0.3V
(CLK IN, CS, RD) . . . . .
Digital Output Voltage to DGND
-0.3V to VDD +O.3V
(DBll-DBO, BUSY, CLK OUT) .
Operating Temperature Range
. . . 0 to +70°C
K,L
- 25°C to + 85°C
B,C . . . . . . .
- 55°C to + 125°C
T, U . . . . . . .
- 65°C to + 150°C
Storage Temperature
Lead Temperature (Soldering, 10secs)
. +300°C
Power Dissipation (Any Package) to +75°C
1,000mW
IOmwrc
Derates above + 75°C by .. . . • . . . . .
*Stress above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
AD7672
TERMINOLOGY
UNIPOLAR OFFSET ERROR
The ideal first code transition should occur when the analog
input is 1I2LSB above AGND. The deviation of the actual
transition from that point is termed the offset error.
BIPOLAR ZERO ERROR
The ideal midscale transition (i.e., 0111 1111 1111 to
1000 0000 0000) for the ± 5V range should occur when the analog
input is 1I2LSB below AGND. Bipolar zero error is the deviation
of the actual transition from that point.
GAIN ERROR
The ideal difference between the first code transition and last
code transition is FS - 2LSBs. The Gain error is defined as the
deviation between this ideal difference and the measured difference. Ideal FS corresponds to 5V for the unipolar 0 to 5V range
and 10V for both the unipolar 0 to lOY and bipolar ± 5V
ranges.
ORDERING INFORMATION l
CONVERSION TIME = 3 ....s
Temperature Range and Package Options2
Accuracy
Grade
±ILSB
±lLSB
Oto +70"C
Plastic DIP (N-24)
- 25°C to + 85°C
Hermetic 3 (Q-24)
AD7672KN03
AD7672BQ03
PLCC4 (P-28A)
LCCC5 (E-28A)
AD7672KP03
AD7672BE03
CONVERSION TIME = 5 .... s
Temperature Range and Package Options2
Accuracy
Grade
Oto + 70°C
Plastic DIP (N-24)
- 25°C to + 85°C
Hermetic 3 (Q-24)
- 55°C to + 125°C
Hermetic3 (Q-24)
±lLSB
±1I2LSB
AD7672KN05
AD7672LNOS
AD7672BQ05
AD7672CQ05
AD7672TQOS
AD7672UQOS
PLCC4 (P-28A)
LCCC5 (E-28A)
±lLSB
+1I2LSB
AD7672KP05
AD7672LPOS
AD7672TE05
AD7672UEOS
CONVERSION TIME
=10....s
Temperature Range and Package Options 2
Accuracy
Grade
±lLSB
±1I2LSB
±lLSB
±1I2LSB
Oto + 70°C
Plastic DIP (N-24)
-25°Cto + 85°C
Hermetic3 (Q-24)
- 55°C to + 125°C
Hermetic3 (Q-24)
AD7672KNIO
AD7672LNIO
AD7672BQlO
AD7672CQIO
AD7672TQIO
AD7672UQIO
PLCC4 (P-28A)
LCCC5 (E-28A)
AD7672KPIO
AD7672LPIO
AD7672TEIO
AD7672UEIO
NOTES
ITo order MIL-STD-883, Class B processed parts, add 1883B to part
number. Contact your local sales office for military data sheet.
2See Section 14 for package outline information.
3Analog Devices reserves the right to ship either ceramic (package outline D-24A)
or cerdip hermetic (package outline Q-24) packages.
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
ANALOG-TO-DIGITAL CONVERTERS 3-313
•
DIP PIN FUNCTION DESCRIPTION
DIP
Pin No.
Mnemonic
Description
I
AINI
2
VREF
AGND
3
4 ... 11 DB11 ... DB4
13 ... 16 DB3 ... DBO
DGND
12
17
CLKIN
18
CLKOUT
19
RD
20
CS
21
BUSY
Vss
VDD
AIN2
22
23
24
Analog Input.
Voltage Reference Input. The AD7672 is specified with VREF = - SV.
Analog Ground.
Three-state data outputs. They become active when CS and RD are brought low. DB II is the
most significant bit (MSB).
Digital Ground.
Clock Input pin. An external TTL compatible clock may be applied to this pin. Alternatively
a crystal or ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT
(Pin 18).
Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock
is used. See CLK IN (Pin 17) description.
READ input. This active LOW signal, in conjunction with CS is used to enable the output data
three-state drivers and initiate a conversion.
CHIP SELECT Input. This active LOW signal, in conjunction with RD is used to enable
the output data three-state drivers and initiate a conversion.
BUSY output indicates converter status. BUSY is LOW during conversion.
Negative Supply, -12V.
Positive Supply, +SV.
Analog Input.
PIN CONFIGURATIONS
LCCC
DIP
PLCC
Q
•
Q
Z
~
~
Z
Veo
4
3
1
2
"..
~
,: 10
4
3
Z
." ,: i " " J ;:
AIN2
28 27 2.
"z
~
" "
J
•
>
2
0
Vss
BUSY
AD7672
TOP VIEW
(Not to Scale)
0:
L"
DB11IMSB) 5
0810
6
24
Ail
DB.
1
23 Ail
NC
•
DB.
9
AD1672
DB.
TOP VIEW
(Not to Scale)
20 elK IN
DB& 11
19 DBO
DB<
OB2
12 13
DGND
0B3
ill
a\Q
Q
Ne
= NO CONNECT
3-314 ANALOG-TO-DIGITAL CONVERTERS
,. ,.
Q
Z
"
Q
"
Z
16 11
(Not to SGale)
,.
Ail
NC
elK OUT
21 CLKOUT
DB1 10
DB1
AD7672
TOP VIEW
22 NC
eLKIN
DB.
CS
CS
CS
elK OUT
iUSV
2. BUSY
elKIN
OB1
DB.
/
:;: lli 10
Q
Q
Q
Ne
= NO CONNECT
~ a\Q
Q
z
8
"z
:;:Q lli a;Q
Q
AD7672
OPERATING FROM A NEGATIVE SUPPLY GREATER
THAN -12V
The AD7672 is designed to operate with a Vss input of
- 12V ± 10%. In applications where the negative supply is greater
than - 12V, then a Zener diode in series with Vss can be used
to reduce the supply. The Zener diode should have a dynamic
impedance of not greater than 4Ofl. An example is given in
Figure 3. The diode has a Zener voltage of 3V, which makes it
suitable for a negative supply of -15V ± 7%.
is finished. At the end of conversion, the DAC output current
balances the current from the analog inputs. The SAR contents
(12-bit data word) which represent the analog input signal are
loaded into a 12-bit latch.
CS &
RD_Q->-----L.!_...J....I_/L....j:.~:--'-1_.......
1_
~~~----------------iS~
~ i80nSTYP
r-~----~--05V±5%
~
eLKIN
I
CLKOUT~J\J-v-
t
OB11
{MSBI
82X85 OR IN52258
3V ZENER
- .....------------0 -15V ±7%
Figure 3. Operation from Nominal Power Supplies of 5V
and -15V
CONVERTER DETAILS
Conversion start is controlled by the CS and RD inputs. At the
start of conversion the successive approximation register (SAR)
is reset and the tbree-state data outputs are enabled. Once a
conversion cycle has begun it cannot be restarted.
During conversion, the internal 12-bit DAC is sequenced by the
SAR from the most significant bit (MSB) to the least significant
bit (LSB). Referring to Figure 4, the analog inputs (AINI &
AIN2) connect to the comparator input via 5kfl resistors. The
DAC which has 2.5kO output impedence connects to the same
comparator input. Bit decisions are made by the comparator
(zero crossing detector) which checks the addition of each successive weighted bit from the DAC output against the analog
inputs. The MSB decision is made 80ns (typically) after the
second falling edge of CLK IN following a conversion start (see
Figure 5). Similarly, the succeeding bit decisions are made
approximately 80ns after a CLK IN falling edge until conversion
t
0810
f
DB'
t
OBD
{LSBI
Figure 5. Operating Waveforms Using an External Clock
Source for CLK IN
CONTROL INPUTS SYNCHRONIZATION
In applications where the RD control input is not synchronized
with the ADC clock then conversion time can vary from 12 to
13 CLK IN periods. This is because the ADC waits for the first
falling CLK IN edge after conversion start before the conversion
procedure begins. Without synchronization, this delay can vary
from zero to an entire clock period. If a constant conversion
time is required, then the following approach may be used:
when initiating a conversion, RD must go low on either the
rising edge of CLK IN or the falling edge of CLK OUT. This
ensures a fixed conversion time that is 12.5 times the CLK IN
period.
DRIVING THE ANALOG INPUTS
During conversion current from the analog inputs is modulated
by the DAC output current at a rate equal to the CLK IN
frequency (i.e., 4MHz when CLK IN = 4MHz). This causes
voltage spikes (glitches) to appear at the analog inputs. The
magnitude and settling time of these glitches depends on the
open-loop output impedance and small signal bandwidth of the
amplifier or sample and hold driving these inputs. These devices
must have sufficient drive to ensure that the glitches have settled
within one clock period. An example of a suitable op amp is the
AD OP-27. The magnitude of the largest glitch when using this
device to drive one of the analog inputs is typically IlmV with a
200ns settling time.
Suitable devices capable of driving the AD7672 analog inputs
are the AD OP-27 and AD711 op amps and the AD585 and
AD683/681 sample and holds.
Figure 4. AD7672 AIN Input
INTERNAL CLOCK OPERATION
Figure 6 shows the AD7672 internal clock circuit. A crystal or
ceramic resonator may be connected between CLK IN (Pin 17)
and CLK OUT (Pin 18) to provide a clock oscillator for the
ADC timing. Alternatively the crystlll/ceramic resonator may be
omitted and an external clock source may be connected to CLK
IN. For an external clock the mark/space ratio must be SO/SO.
An inverted CLK IN will appear at the CLK OUT pin as shown
in the operating waveforms of Figure 5.
ANALOG-TO-DIGITAL CONVERTERS 3-315
II
AD7672
The output code is narural binary with lLSB = FS/4096. FS
is either + SV or + 10V depending on the analog inputs
configuration.
OUTPUT
CODE
CLOCK
FULL SCALE
TRANSITION
:::::+
11 .. 10,t
NOTES
AD7612XX03- 4MHzCRYSTAUCERAMIC RESONATOR.
AD1612XXOS- 2.5MHz CRYSTALJCERAMIC RESONATOR.
AD1612XX'D- '.25MHz CRYSTALJCERAMIC RESONATOR.
C1 AND C2 CAPACITANCE VALUES DEPEND ON CRYSTAL/CERAMIC RESONATOR
MANUFACTURER. TYPICAL VALUES ARE FROM 3OpFTO 'DOFF.
"
/T
lLSB = 4::6
::':::kC
Figure 6. AD7672 Internal Clock Circuit
l
,/
00 .. 001
ANALOG INPUT RANGES
The AD7672 provides three user selectable analog input ranges;
o to + SV, 0 to + lOY and ± SV. Figure 7 shows how to configure
the two analog inputs (AINI and AIN2) for these ranges.
00.
000
--------
o
LS~ LS='S ~B'S
I
I
I
,
FS
FS -1LSB
V IN• INPUT VOLTAGE UNTERMSOFLSBs)
Figure 9. AD7672 Ideal InputlOutput Transfer
Characteristic for Unipolar Operation.
TO
SA~
' - - - - - -.... ~~c
TO
SAR
L------1~c
TO
SAR
L------~~c
-ADDITIONAL PINS OMMITED FOR CLARITY
Figure 7. Analog Input Range Configurations
UNIPOLAR OPERATION
Figure 8 shows how to configure an ADS84 to produce a reference
voltage of - SV for unipolar operation.
The ideal input/output characteristic is shown in Figure 9. The
designed code transitions occur midway between successive
integer LSB values (i.e., 1I2LSB, 3/2LSBs ... FS -3/2 LSBs).
+5V
OFFSET AND FULL·SCALE ERROR
In most Digital Signal Processing (DSP) applications, offset and
full-scale error have little or no effect on system performance. A
typical example is a digital filter, where an analog input signal is
quantized, digitally processed and recreated using a DAC. In
these type of applications the offset error can be eliminated by
ac coupling the recreated signal. Full-scale error effect is linear
and does not cause problems as long as the input signal is within
the full dynamic range of the ADC. An important consideration
in DSP applications is Differential Nonlinearity and this is not
affected by either offset or full-scale error.
UNIPOLAR OFFSET AND FULL·SCALE ERROR
ADJUSTMENT
If absolute accuracy is an application requirement then offset
and full-scale error can be adjusted to zero. Offset error must be
adjusted before full-scale error. Figure 10 shows the extra compor;tents required for full-scale error adjustment. Zero offset is
achieved by adjusting the offset of the op amp driving the analog
input (i.e., Al in Figure 10.). For zero offset error apply a
voltage equal to 1I2LSB at VIN and adjust the op amp offset
voltage until the ADC output code flickers between
0000 0000 0000 and 0000 0000 0001.
o to
o to
+SV Range: 1I2LSB = 0.61mV
+ lOY Range: 1I2LSB = 1.22mV
For zero full-scale error apply an analog input voltage equal to
FS-3/2LSBs (last code transition) at VIN and adjust Rl until the
ADC output code flickers between 1111 1111 1110 and
llll 1111 1111.
o to
o to
+SV Range: FS-3/2LSBs = 4.99817
+ lOY Range: FS·3/2LSBs = 9.99634
ANALOG
INPUT
'----~:~
R2
AD7672*
200
-"DDmONAL PINS OMMTTED FOR CLARITY
··O·TO·SV RANGE: CONNECT AIN2 TO AlN1
O-TO·1OV RANGE: AtN2
OR
AGND
*ADDITIONAL PINS OMMIT£D FOR CLARtTY
"OTOSV RANGE: CONNECT AIN2 TOAIH1
OT010VRANGE:AIN2
Figure 8. Unipolar Operation Using the AD584 as a
Reference
3-316 ANALOG-TO-DIGITAL CONVERTERS
= AGND
Figure 10. Unipolar Operation with Gain Error Adjust
AD7672
BIPOLAR OPERATION
Bipolar operation is achieved by providing a + IOV span at the
AINI input which is offset to ± 5V by applying + 5V at the
AINZ input. This requires two reference voltages; - 5V for the
VREF input and + 5V for the AINZ input. Figure 11 demonstrates
how to produce these voltages from an AD584 and an inverting
amplifier configuration. Alternatively, a convenient solution is
to use the AD588 voltage reference as in Figure lZ. This device
generates the required ± 5V with a minimum of additional
components. It also offers excellent temperature stability with
voltage drifts as low as 1.5ppmrC.
The ideal input/output transfer characteristic after offset
and gain adjustment is shown in Figure 13. The LSB size is
(l0/4096)V = Z.44mV.
+5V
II
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. Bipolar Operation Using an AD588 Voltage
Reference
111.
111
111.
110
100.
'" .
-FS
~
011,
011.
-ADDITIONAL PINS OMITTED FOR CLARITY
000.
Figure ". Bipolar Operation Using an AD584 and an
AD7110pAmp
BIPOLAR OFFSET AND GAIN ADJUSTMENT
In applications where absolute accuracy is important then offset
and gain error can be adjusted to zero. Offset is adjusted by
trimming the voltage at the AINI or the AINZ input when the
analog input is at - FS/Z + lIZLSB. This can be achieved by
adjusting the offset of an external amplifier used to drive either
of these analog inputs. Alternatively the AD588 voltage reference
contains a balance control input which can be used to trim the
offset to zero. An additional potentiometer (R2 in Figure 14) is
required. The trim procedure is as follows:
Apply - 4. 99878V ( - FS/Z + lIZLSB) at VIN and adjust RZ
until the ADC ouput code flickers between 0000 0000 0000 and
0000 0000 000 1.
Gain error can be adjusted at either the last positive code transition
or the mid-scale transition (bipolar zero error adjust). Adjusting
the positive end of the transfer function is in keeping with more
conventional ADC calibration techniques where the user fixes
the two end points as in the unipolar case. Bipolar zero adjustment
is required in some applications (e.g., motor control) where the
user must be guaranteed that the 0111 1111 1111 to
1000 0000 0000 transition occurs exactly when the analog input
is lIZLSB below AGND. The trim procedures for both cases
are as follows. (See Figure 14.)
Last Code Transition Adjust
Apply a voltage of 4.99634 volts (FS/Z - 3/ZLSBs) at VIN • Adjust
R5 until the ADC output code flickers between 1111 1111 1110
and 1111 1111 1111.
'''r
001
100 .. 000
000.
", I
110
IT
I
I
I
I
I
+~2LSB
+2fS -lLSB
I
:fu:~
V IN•
lLSB
= 4~:6
0
INPUT VOLTAGE UN TERMS OF LSBs)
Figure 13. Ideal Input/Output Transfer Characteristic for
Bipolar Operation
R2
100k
-ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. Bipolar Operation with Offset and Gain Error
Adjust
Bipolar Zero Error Adjust
Apply a voltage of -I.ZZmV at VIN and adjust R5 until the
ADC output code flickers between 0 III 1111 1111 and
1000 0000 0000.
ANALOG-TO-DIGITAL CONVERTERS 3-317
TIMING AND CONTROL
ConverSion start and data read operations are controlled by two
of the AD7672 digital inputs; CS and RD. Figure 15 shows the
equivalent logic circuit of these inputs. A high-ta-low logic
transition on CS and RD initiates a conversion. Once initiated it
cannot be restarted until conversion is complete. Converter
status is indicated by the BUSY output, and this is low while
conversion is in progress.
SLOW MEMORY MODE
Figure 16 shows the timing diagram for Slow Memory Mode.
CS and RD going low triggers a conversion and the AD7672
acknowledges by taking BUSY low. Data from the previous
conversion appears on the three-state data outputs. BUSY returns
high at the end of conversion when the output latches have been
updated and the conversion result is placed on the output data
bus.
ROM MODE
The ROM Mode avoids placing a microprocessor into a wait
state. A conversion is started with a READ operation and the
12-bits of data from the previous conversion are available on the
data outputs while CS and RD are low. This data may be disregarded if not required. A second READ operation reads the
new data and starts another conversion. A delay at least as long
as the AD7672 conversion time must be allowed between READ
operations.
CONVERSION START
(RISING EDGE TRIGGER)
CLEAR
BUSY
,----:;A;,::c",nV.:,:E;..;",;:;IG::;",-- ~:~~~~.1~~EE-STATE OUTPUTS
*ADDITIONAL PINS OMITTED FOR CLARITY
MICROPROCESSOR INTERFACING
The AD7672 is designed to interface to microprocessors as a
memory mapped device. The CS and RD inputs are common
control inputs to all peripheral memory interfacing.
Figure 15. internai Logic for Controi inputs CS and flO
There are two modes of operation as outlined by the timing
diagrams of Figures 16 and 17. Slow Memory Mode is designed
for microprocessors that can be driven into aWAIT state, a
READ operation brings CS and RD low, which initiates a conversion and data is read when conversion is complete. The
second is the ROM Mode, which does not require microprocessor
WAIT states. A READ operation brings CS and RD low
which initiates a conversion and reads the previous conversion
result. The data format for both modes is designed for parallel
interfacing.
~,
f~
~ "r-
00\
-I "1-"""---1
f
BUSVI\
j - - - ..
I
OLDOATA
0811-D80
Figure 18 shows a typical interface for the MC68000. The AD7672
is operating in the Slow Memory Mode. Assuming the AD7672
is located at address COOO then the following single 16-bit MOVE
instruction both starts a conversion and reads the conversion
result.
Move. W $COOO,DO
At the beginning of the instruction cycle when the ADC address
is selected, BUSY and CS assert DTACK, so that the 68000 is
forced into a WAIT state. At the end of conversion BUSY
returns high and the conversion result is placed in the DO register
of the UP.
-j',f-
--I
.-Jt. I- -j.,f--
--I"f-
~
DATA - - , .
"L
-1"1-
MC68000 MICROPROCESSOR
~
~
~3~------------------~
All----..,
'-
C
AD7672*
MC68000
___-I cs
'--...l \,.------------1 BUSV
II-~~------
"liN
Figure 16. Slow Memory Mode Timing Diagram
1--------\ /---,---<11
A41N
S~~~E
A0588
-IN
le2
HAL
ADJ
C15JA1S
Dun
C16fA16
DATA
DB7-DBO
-v.
OUT>
}-------;lD3
4-BITBUS
,
I
e17/A17
I
I~ Q.~-~~~
GND
1. THE CORRESPONDING PCB LAVOUTOF AGURES29AND
30 CAN ACCOMMODATE EITHER THE ADS85, THEAD681
I
I
C29IA29
14HC374
}-----~D.
NOTES
C~A215
C1BfA'S
I
d6lJ.
OR THE AD683 SHA.(SEE FIGURES25 AND 26.)
2. ANALOGINPUTRANGESELECT.
3. C9ANDC10ARE REQUIRED FORTHE ±5VRANGEONlY.
4. OPTIONAL SAMPLE-AND-HOLD DELAY. IF NOTREQUIRED,
REPLACE R3 wtTH A wrRe LlNKANDOMITC27.
elKIN C30/A30
' - - -_ _ _ _ _- ' ' -_ _ _ _ _ _ _ _ _ _ _ _ _ _--''''-'---\
DGND
e32/A32
Figure 24. Data Acquisition Circuit Using the AD7672
i-I
I
I
-------,
I
Voo
V+
lIP
+ INPUT
CON":ri~
OUTPUT
IVss
I
I
I
HOLD
,
VouTI
V OUT
VOUT
I
HOLD
v-
AD585
-v.
PWR
GND
L ____ _
LOGIC
REF
AD6831
AD681 -INPUT
SIG
GND
I - - - v;'; - - - - -,
I
I
I liP
+v.
HOLD I
+VIfII
HOLD
GND
I
I
I
I
GND
I
----'
Figure 25. AD6831AD681 SHA Connection Diagram for
Figure 24
'-----
GND
_ ___
-1I
Figure 26. AD585 SHA Connection Diagram for Figure 24
ANALOG-TO-DIGITAL CONVERTERS 3-321
II
SAMPLE-AND·HOLD OPERATION
The PCB layout of Figures 29 and 30 can accommodate either
the AD683, the AD681 or the ADS8S sample.and.hold amplifier.
The choice of SHA depends mainly on the acquisition time
required.
However, another important consideration wi~ sample·and.hold
interfacing is settling time. This is the time required by the
sample and hold amplifier output to settle after receiving a
HOLD command. To allow for this, there must be a delay
which is at least as long as the SHA settling time between the
HOLD command and the AD7672's fll'St MSB decision. When
initiating a conversion, if the SHA's HOLD input and the AD7672
CS and RD inputs are asserted together, then this delay can
vary from one to two clock periods. This corresponds to a delay
of 800ns to 1600ns for the AD7672XXlO, 400ns to 800ns for
the AD7672XXOS and 2S0ns to SOOns for the AD7672XX03.
Under these conditions a settling time of less than 200ns is
required by the SHA to satisfy all speed grades of the AD7672.
This figure allows an additional SOns for the AD7672XX03
internal comparator. Both the AD683 and AD681 meet this
condition. However, since the ADS85 is specified with a settling
time of SOOns, the lO ....s version of the AD7672 is the only one
of the three-speed grades guaranteed to meet this timing requirement. This settling time requirement may be met with .the
higher speed grades by using either an additional circuit delay
or by synchronizing the control inputs with the clock. Both of
these methods are discussed below.
AD7672 -AD585 INTERFACE
The SOOns settling time requirement of the ADS8S must be
allowed for, at the start of conversion when interfacing to the
3....s and S....s versions of the AD7672. It may be achieved for the
S....s version by using either one of two methods. The first is to
synchronize the control inputs with the ADC clock as follows;
when initiating a conversion CS and RD (CSTART in Figure
24) should go low on a falling CLK IN edge. This guarantees
two clock periods between conversion start and the first MSB
decision.
The second method will work for both the 3....s and S....s parts. It
compensates for settling time by inserting an external delay
between the AD7672 CS and RD inputs and the ADS8S HOLD
input. The length of this delay should be equal to the sample-andhold amplifier settling time. It is shown as an optional RC delay
in Figure 24 which must be bypassed if not used. Note it is not
required for the slower lO ....s, AD7672XXIO or when either the
AD683 or the AD681 is used with any speed grade of the
AD7672.
EXTERNAL CONNECTIONS
The PCB layout is designed so that all external connections
except the VDD and Vss power supplies can be made by any of
three ways:
1. 32 way single sided edge connector,
2. Euro card connector, SKT3
3. 20-pin DIP socket. (SKT2 on the silk screen).
The pinout for the 20-pin DIP socket is shown below and the
other pinouts are shown in Figures 24 and 30. The VDD and
Vss power supplies are connected at the top of the board (see
Figure 28, Silk Screen).
-Nle - NO CONNECTION
PIN FUNCTION DESCRIPTION
C.START
Conversion Start going low initiates a
conversion.
Active Low, three-state control for DB7DBO.
Active Low, three-state control for DB 11DB8.
AD7672 Status Output. BUSY is low during
conversion.
CLKIN
AD7672 CLK IN input. Note the board has
a facility for an on-board crystal oscillator or
a ceramic resonator.
DB 11-DBO
Three-State data outputs.
SV
SV power supply.
DGND
Digital Ground
INPUT RANGE SELECT OPTIONS
There are three analog input ranges which are user selectable by
placing links on the PCB as shown in Table I below. These
options are located between IC2 and IC3.
Range
(Volts)
Links Required
= Open Circuit
OtoS
Connect E to F
A-B,C-D
Oto 10*
Connect C to D
A-B,E-F = Open Circuit
- 5 to + 5
Connect A to B
C-D,E-F = Open Circuit
*Due to headroom limitations at 12V power supplies, the AD585 sampleand·hold amplifier is not suitable for the O-IOV range.
Table I. Input Range Link Options
3-322 ANALOG-TO-DIGITAL CONVERTERS
AD7672
Cl, C3, CS, C7,
Cll, CIS, C17,
C19, C2l, C23
COMPONENT LIST
Sample and hold, ICI can occupy one of
ICI
two positions depending on the sample-andhold model. These positions are outlined
in Figure 27. The plated-through holes
denoted by "1" are configured for the
AD683/AD681 and the plated-through
holes denoted by "2" are configured for
the ADS8S.
IOI1F Capacitors.
C2, C4, C6, C8,
Cl2, C16, C18,
C20, C22, C24
C2S
O.lI1F Capacitors.
ll1F
IOI1F Capacitor, Required for ±SV Range
Only.
O.lI1F Capacitor, Required for ± SV Range
Only.
C9
ClO
.--_ _ _...,.../AD683IAD681
I
I
-0 0
o 0
Cl3, CI4
CrystaUCeramic Resonator Capacitors
Values Depend on the Manufacturer. For
example: 4MHz XTAL (HC - l8/U) from
IQD; Cl3, C14 = 30pF; 2.SMHz (HC 181
U) and l.2288MHz (HC 33/U) from Anderson; No Capacitors Required.
C26
C27
22pF.
470pF, Sample-and-Hold Delay (See Sample-and-Hold Operation) Omit C27 if this
delay is not required.
39k.
4.7k.
lk, Sample-and-Hold Delay (See Sampleand-Hold Operation) Replace with a wire
link if this delay is not required.
Subminiature Connector from Greenpar.
0 0
0 0
~ ~ 85 ~
o 0 0 0
o 0 0 0
o ® (£) 0
I
I
............AD585
* PIN ONE
RI
R2
R3
Figure 27. PCB Sarriple-and-Hold Amplifier Options
IC2
IC3
IC4
ICS, IC6
SKTl
ADS88 Voltage ReferenCe.
AD7672 Analog-to-Digital Converter.
74HCOO Quad NAND Gate.
74HC374 OcataILatches with Three-State
Outputs.
ov
Voo
D
R1
C7
~
<;!.+
g~ +
AD]J3/AD68¥-
c31 Ico
+
B+
c
o
F
E
AD585
TP2
R2
-
o~·
+
C231 1e24
A1
~26
~
C19
+-
'"'
l-
:.:
en
C20
R3
C27
IC4
C16
~
clll IC12
+
I
TP4
ITg
~+
IC1
C1
BOARD
+
+C9
C25
A
AD7672
TP3 -CLK IN
TP4 - AD7672 BUSY Output
C8
+T~
TPI - Analog Input
TP2 - Analog Ground
Vss
IC2
I
TEST POINTS
~'"! ,,"
C13
XTAL
IC5
IC3
~
SKT2
ICG
TP3
Figure 28. PCB Silk Screen for Figure 24
ANALOG-TO-DIGITAL CONVERTERS 3-323
II
c~
3.94
(100mm)
Figure 29. PCB Component Side Layout for Figure 24
C.START
BUSY
OUTl
OUT2
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
DB6
DB9
DB10
DBll (MSB)
ClKIN
5V
DGND
Figure 30. PCB Solder Side Layout for Figure 24
~324
ANALOG-TO-DIGITAL CONVERTERS
1IIIIIIII ANALOG
WDEVICES
FEATURES
Two-Channel. 8-Bit 2.5 JLS ADC
Two 8-Bit. 2.5 JLS DACs with Output Amplifiers
Span and Offset of ADC and DAC
Independently Adjustable
Low Power
LC 2MOS
Analog lID Port
AD7769 I
AD7769 FUNCTIONAL BLOCK DIAGRAM
•
APPLICATIONS
Winchester Disk Servo Controllers
Floppy Disk Microstepping
Closed Loop Servo Systems
GENERAL DESCRIPTION
The AD7769 is a complete, two-channel, 8-bit, analog 1/0 port.
It has versatile input and output signal conditioning features
(patent pending) that make it ideal for use in head-positioning
servos in Winchester disk systems. It is equally suitable for
floppy disk microstepping head positioning, other closed loop
digital servo systems and general purpose 8-bit data acquisition.
The AD7769 contains a high speed successive approximation
ADC, preceded by a two-channel multiplexer and signal conditioning circuits. The input span of the ADC and the offset of
the zero point from ground can be independently set by applying ground referenced voltages. The AD7769 also contains two
independent, fast settling, 8-bit DACs with output amplifiers.
The output span and offset voltage of the DACs can be set independently of those of the ADC. This makes the AD7769 especially useful in disk drives, where only a positive supply rail is
available and the ranges of the ADC and DACs must be referenced to some positive voltage less than the supply.
The AD7769 is easily interfaced to a standard 8-bit mpu bus via
an 8-bit data port and standard microprocessor control lines.
PRODUCT HIGHLIGHTS
1. Two-Channel, 8-Bit Analog 1/0 port on a Single Chip.
The AD7769 contains a two-channel, high speed ADC with
input signal conditioning and two, fast settling 8-bit DACs
with output amplifiers, on a single chip.
2. Independent Control of Span and Offset.
The input voltage span of the ADC and the midpoint of the
transfer function, the output voltage swing of the two DACs
and the half-scale output voltage, can be set independently
by applying ground referenced control voltages.
3. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7769 is specified with ac parameters including signalto-noise ratio, distortion and signal bandwidth.
4. Fast Microprocessor Interface.
The AD7669 has bus interface timing compatible with all
modern microprocessors, with bus access and relinquish
times less than 65 ns and a Write pulse width less than
90 ns.
The AD7769 is fabricated in Linear Compatible CMOS
(LC2 MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic.
The part is available in a 28-pin plastic DIP and 28-terminal
PLCC package.
ANALOG-TO-DIGITAL CONVERTERS 3-325
SPECIFICATIONS
ADC SPECIFICATIONS
Parameter
DC ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
+25"(;
T.,;n toT....
Bias Offset Match
+25"(;
T min to T max:
Plus or Minus Full-Scale Error
+25"(;
T.,;n toT....
Plus or Minus Full-Scale Match
+25OC
T.,;n toT"""
ADC TO DAC MATCHING
Bias Offset Match
+25"(;
Tmin toTmax.
Plus or Minus Full-Scale Match
+25"(;
Tmin to Tmax
DYNAMIC PERFORMANCE'
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
intermodulation Distortion (IMD)
Frequency Response
ANALOG INPUTS
input Voltage ~es,VINA,VINB
Input Currents, IINA, IINB
ADC REFERENCE INPUTS
Input Voltage Levels
VBIAS (ADC)
VSWING (ADC)
Input Currents
VBIAS (ADC) Input
VSWING (ADC) Input
(Voo = +12 V ±10%; Vee = +5 V ±5%; UND [ADC] = AGND [DAC] = DGND = 0 V;
VBIAS [ADC] = +5 V; VswlNa [ADC] = +2.5 V; feU( = 5 MHz external. All specifications Tml• to Tm".'
unless otherwise stated.)
J Version K Version Units
8
±1
±1
*
*
*
Bits
LSBmax
LSBmax
±3.0
±3.5
±2.5
±3.0
LSBmax
LSBmax
±2.5
±3.5
*
*
LSBmax
LSB max
±2.0
±2.5
*
*
LSBmax
LSBmax
±3.5
±4
*
*
LSB max
See Terminology
Channel A to Channel B
LSBmax
Channel AlB to VOUT AlB
VBIAS (DAC) = +5 V, VSWING (DAC) = +2.5 V.
±3.5
±4.0
±2.5
±3.5
LSBmax
LSBmax
±3.5
±4.0
*
*
LSBmax
LSBmax
44
48
60
0.1
*
*
*
*
dB min
dB max
dBtyp
dBtyp
VIN
VIN
f. =
VIN
V min
V max
mAmax
Whichever Is the Higher
Whichever Is the Lower
With Respect to AGND (ADC). For Specified Performance.
With Respect to AGND (ADC). For Specified Performance.
VBIAS - VSWING or 0
VBIAS + VSWING or 9.8
±0.4
*
*
*
V minimax
V minimax
±800
±1
*
*
..,A max
0.4
4.0
*
*
V max
V min
±10
10
*
*
p.Amax
pFmax
4.7515.25
*
VminlVmax
100
VooRange
@ +25"(;
T.,;n toT_
10.8113.2
20
22
*
*
*
V minIV max
mAmax
mAmax
Icc @ +25"(;
T.,;n toT""",
5
6
*
*
mAmax
mAmax
POWER REQUIREMENTS
VCC Range
See Terminology
No Missing Codes. See Terminology.
See Terminology
Channel A to Channel B
2.0/3.0
LOGIC OUTPUTS
DBO-DB7, INT
VOL> Output Low Voltage
VOH' Output High Voltage
DBO-DB7
Floating State Leakage Current
Floating SIBte Capacitance'
Output Coding
Conditions/Comments
216.8
= 100 kHz Full-Scale Sine Wave with fSAMPUNG = 400 kHz
= 100 kHz Full-Scale Sine Wave with fSAMPUNG = 400 kHz
99 kHz, fb = 96.7 kHz with fSAMPUNG = 400 kHz
= Full-Scale, dc to 200 kHz Sine Wave
p.Amax
ISINK = 1.6 mA
IsoURCE = 200 ..,A
Offset Binary
NOTES
'Temperature range as follows: J, K Versions; 0 to + 70'C.
'Sample tested at +2S'C to ensure compliance.
*Specification same as J Version.
Specifications subject to change without notice.
3-326 ANALOG-TO-OIGITAL CONVERTERS
For Specified Performance. The Part Will Function with Vcc = 5 V
± 10% with Degraded Performance.
For Specified Performance
For ADC and DAC: VBIAS = 5.0 V; VSWING = 3.0 V; VINA, VINB =
VBIAS ; DAC Code = FF (Hex); DACA and DACB Load = 5 kO to
AGND (DAC). Typically 100 = 14 mAo
Logic inputs = 2.4 V, CLK Input = 0.8 V. Typically Icc = 1.5 mAo
AD7769
DACA, DACB SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
+25°C
Tmin to Tmax
Bias Offset Match
+25OC
T min to Tmax
Plus or Minus FuU-Scale Error
+25OC
T min to Tmax
Plus or Minus Full-Scale Match
+25OC
Tmin to Tmax
(Voo = +12 V ±10%; Vee = +5 V ±5%; AGNO [OAC] = AGNO [AOC] = OGNO = 0 V;
VBIAS [OAC] = +5 V; VSWING [OAC] =
V; VomA. VouTB load to AGNO [OAC].
RL = 5 kG. CL = 100 pF. All specifications I mi• to 1mB.' unless otherwise stated.)
+2.5
J Veraion
K Veraion
Units
8
±1
±l
*
*
*
Bits
LSBmax
LSB max
±2.0
±2.5
*
*
LSB max
LSB max
±2.5
±3.5
*
*
LSB max
LSB max
±2.0
±2.0
±1.5
*
LSB max
LSB max
±3.5
±4.0
*
*
LSB max
LSBmax
As Per ADC Specifications
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Intermodulation Distortion (IMD)
44
48
55
DC Output Impedance
Short-Circuit Current
DAC REFERENCE INPUTS
Input Voltage Levels
VBIAS(DAC)
VSWING (DAC)
Input Currents
VBIAS (DAC) Input
VSWING (DAC) Input
AC CHARACTERISTICS2
Voltage Output Settling Time
Digital-to-AnaIog Glitch Impulse
Digital Feedthrough
LOGIC INPUTS
CS, RD, WR, ADC/DAC, CHAICHB,
DBO-DB7
Input Low Voltage, VfNL
Input High Voltage, VfNH
Input Leakage Current
Input Capacitance
CLK
Input Low Voltage
Input High Voltage
Input Leakage Current
DBO-DB7
Input Coding
POWER REQUIREMENTS
See Terminology
Guaranteed Monotonic. See Terminology.
See Terminology
VOUT A to VOUT B
See Terminology
VOUT A to VOUT B
ADC to DAC MATCHING
ANALOG OUTPUTS
Output Voltage Ranges
VOUTA, VOUTB
Conditions/Comments
*
*
*
dB min
dB max
dB typ
VOUT = 20 kHz FuU-Scale Sine Wave With fSAMPLING = 400 kHz
VOUT = 20 kHz FuU-Scale Sine Wave With fSAMPLING = 400 kHz
f. = 18.4 kHz, fb = 14.5 kHz with fSAMPLING = 400 kHz
VBIAS - VSWING or 0.5
V BIAS + V SWING or
VDD -2.0
0.5
*
20
*
V min
Whichever Is the Higher
V max
Otyp
mAtyp
Whichever Is the Lower
3/6.8
2.0/3.0
*
*
V minimax With Respect to AGND (DAC). For Specified Performance.
V minimax With Respect to AGND (DAC). For Specified Performance.
±2
±l
*
*
I1A max
I1A max
4
30
I
*
*
*
IJ.smax
nV sec typ
nV sec typ
0.8
2.4
±10
10
*
*
*
*
V max
V min
IJ.Amax
pFmax
0.8
2.4
±10
*
*
*
V max
V min
I1A max
Settling Time to Within ±1I2 LSB of Final Value. Typically 2.5 iJ.S.
See Terminology
See Terminology
External Clock. For Internal Clock Operation Connect
the CLK Pin to VDD'
Offset Binary
As per ADC Specifications
NOTES
'Temperature range as follows: J, K Versions; 0 to +70OC.
2Sample tested at + 250C to ensure compliance.
*Specifications same as J Version.
Specifications subject to change without notice.
ANALOG-TO-DIGITAL CONVERTERS 3-327
Y'IMING CHARACYERISYICS 1
!
Parameter
ADClDAC CONTROL TIMING
CS to WR Setup Time
CS to WR Hold Time
ADClDAC to WR Setup Time
ADClDAC to WR Hold Time
CHAlCHB to WR Setup Time
CHAlCHB to WR Hold Time
WR Pulse Width
ADC CONVERSION TIMING
Using External Clock
WR to INT Low Delay
Using Internal Clock
WR to INT Low Delay
WR to INT High Delay
2 (Vee = +5 V ±5%; Voo = +12 V ±lD%; ASNO [ADC] = AGNO [OAC] = OSNO = DV.
For AOC and OAC. VBIAS = +5 V. VSWING = +2.5 V.l
Label
Limit at
+ 25°C
Limit at
T.,.;", Tmax
Units
t1
t2
t3
t4
ts
t6
t7
0
0
0
0
0
0
80
0
0
0
0
0
0
80
nsmin
nsmin
ns
nsmin
nsmin
nsmin
nsmin
ts
2.6
2.6
j.Lsmax
ts
to
tlO
tlO
1.9/3.0
85
120
Is+70
t s + 110
1.9/3.0
85
120
Is+70
t s + 110
j.Ls minimax
ns max
nsmax
ns max
ns max
tll
0
0
nsmin
t12
t 13
t13
t14
tiS
tiS
t 16
0
15/65
30/100
15/65
80
110
t13
0
15/65
30/100
15/65
80
110
t13
t17
tiS
t 10
65
15
4
65
20
4
~
WR to Data Valid Deiay3
ADC READ TIMING
CS to RD Setup Time
CS to RD Hold Time
RD to Data Valid Delay3
Bus Relinquish Time after RD High4
RD to INT High Delay
RD Pulse Width
DAC WRITE TIMING
Data Valid to WR Setup Time
Data Valid to WR Hold Time
WR to DAC Output Settling Time
Test Conditions/Comments
Load Circuit of Figure 3, CL
= 20 pF
Load Circuit of Figure
Typically 2.5 I1S
Load Circuit of Figure
Load Circuit of Figure
Load Circuit of Figure
Load Circuit of Figure
3, CL
= 20 pF
3,
3,
1,
1,
CL
CL
CL
CL
= 20 pF
= 100 pF
= 20 pF
= 100 pF
nsmin
ns minimax
ns minimax
ns minimax
ns max
nsmax
nsmin
Load Circuit of Figure 1,
Load Circuit of Figure I,
Load Circuit of Figure 2
Load Circuit of Figure 3,
Load Circuit of Figure 3,
Determined by t13
CL
CL
= 20 pF
= 100 pF
CL
CL
= 20 pF
= 100 pF
nsmin
nsmin
j.Lsmax
Load Circuit of Figure 4
NOTES
'See Figures 11, 12 and 13.
2Sample tested at +25'C to ensure compliance. All input signals are specified with II = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
't,o and t" are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4 t '4 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
+5 V
!
DBN~
3
+5 V
3 kll
DBN-r
kll~_.~CL
CL
~DGND
DGND
a. High-Z to VOH
b. High-Z to VOL
Figure 1. Load Circuits for Data Access Time Test
INT--I--C
~D~ND
Figure 3. Load Circuit for RD and WR to INT Delay Test
3-328 ANALOG-TO-DIGITAL CONVERTERS
DBN~
~__ ••
3 kll
,;!;
10 pF
--f:
T
10 pF
\lDGND
DGND
a. VOH to High-Z
b. VOL to High-Z
V-A'*
Figure 2. Load Circuits for Bus Relinquish Time Test
AGND(DAC)
Figure 4. Load Circuit for DAC Settling Time Test
AD7769
ABSOLUTE MAXIMUM RATINGS·
VDD to AGND or DGND . . . . . . . . . . . . . . . -0.3 V, +15 V
Vee to DGND . . . . . . . . . . . . . -0.3 V, VDD +0.3 V or 7 V
(Whichever is Lower)
AGND to DGND . . . . . . . . . . . . . . . . -0.3 V, VDD +0.3 V
Digital Inputs to DGND
(Pins 12, 13, 15-18) . . . . . . . . . . . . . -0.3 V, VDD +0.3V
Digital Outputs to DGND
(Pins 3-10,11) . . . . . . . . . . . . . . . - 0.3 V, Vee + 0.3 V
Analog Inputs to AGND . . . . . . . . . . . . -0.3 V, VDD +0.3 V
Analog Outputs to AGND . . . . . . . . . . -0.3 V, VDD +0.3 V
Operating Temperature Range
Commercial (1, K Versions) . . . . . . . . . . . . . . . 0 to +70°C
Power Dissipation (Any Package)
to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Derates Above +75°C by . . . . . . . . . . . . . . . . . . 6 mWf'C
Storage Temperature Range . . . . . . . . . . . . -65°C to + 150°C
Lead Temperature (Soldering 10 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Only one Absolute Maximum Rating may be applied at anyone time.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.
ORDERING INFORMATION
~
~~=:
NOTE
Do not allow Vee to exceed VDD by more than 0.3 V. In cases
where this can happen the diode protection scheme shown below
is recommended.
Temperature Range and Package Options l
o to +70°C
Plastic DIP (N-28)
AD7769JN
AD7769KN
WARNING!
PLCC (P-28A)'
AD7769JP
AD7769KP
NOTES
!See Section 14 for package outline information.
'PLCC:Plastic Leaded Chip Carrier.
HP5082-2810
Vee
AD7769
PIN CONFIGURATION
DIP
PLCC
~
e
~
YOUTH
~ >8
}} j
2
28
,
27
28
VSWlII.. G IDAC)
AGND (DACI
V1NA
AD7769
V.ltostADC)
TOP VIEW
INotto Seale)
ANALOG-TO-OIGITAL CONVERTERS 3-329
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
VDD
2
+ 12 V Power Supply. This powers the analog circuitry.
+5 V Power Supply. This powers the logic circuitry.
3-10
Vee
DB7-DBO
11
INT
Interrupt Output (active low). INT is set high on the falling edge of RD or WR to the ADC and
goes low at the end of a conversion.
12
CLK
Clock input. A clock is required for the ADC. An external TTL-compatible clock may be applied
to this input pin. Alternatively, tying this pin to VDD enables the internal clock oscillator. With
an external clock, the mark-space ratio can vary from 30nO to 70/30.
13
CHAlCHB
Channel AlChannel B Select Input. Selects Channel A or Channel B of the DAC or ADC. Used in
conjunction with WR, RD, CS and ADClDAC for read or write operations.
14
DGND
Digital Ground.
15
ADClDAC
ADC or DAC Select Input. Selects either the ADC or the DAC for read or write operations in
conjunction with WR, RD, CS and CHAICHB.
16
WR
Input/Output Data Bus. A bidirectional data port from which ADC output data may be read and
to which DAC input data may be written. DB7 is the Most Significant Bit.
Write Input (edge triggered). This is used in conjunction with the ADClDAC, CHAlCHB and CS
control inputs to start an ADC conversion or write data to the DAC. An ADC convel'sion starts
on the rising edge of WR.
17
RD
Read Input (active low). This input must be low to access data from the ADC.
18
CS
Chip Select Input (active low). The device is selected when this input is low.
19
VSWING (ADC)
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
input voltage Full-Scale Range (FSR) of the ADC. VIN (FSR) = 2 VSWING (ADC).
20
AGND(ADC)
ADC Analog Ground.
21
VINB
Analog Input for Channel B. See VINA description.
22
VBIAS (ADC)
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
midpoint of the ADC transfer function.
23
VINA
Analog Input for Channel A. The input voltage range of both ADC channels is given by:
VIN AlB = VBIAS (ADC) ±VSWING (ADC).
24
AGND(DAC)
DAC Analog Ground.
25
VSWING (DAC)
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the output voltage Full-Scale Range (FSR) of the DACs. VOUT (FSR) = 2 VSWING (DAC).
26
VouTB
VBIAS (DAC)
Analog Output Voltage from DAC B. See VOUTA description.
27
28
VouTA
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
midpoint output voltage of the DACs.
Analog Output Voltage from DAC A. The output voltage range of both DACs is given by:
VOUT AlB = VBIAS (DAC) ± VSWING (DAC).
3-330 ANALOG-TO-DIG/TAL CONVERTERS
AD7769
TERMINOLOGY
Relative Accuracy
For an ADC, Relative Accuracy or endpoint nonlinearity is the
maximum deviation, in LSBs, of the ADC's actual code transition points from a straight line drawn between the endpoints of
the ADC transfer function, i.e., the 00 to 01 and FE to FF Hex
(01111111 to 11111111 Binary) code transitions.
For a DAC, Relative Accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function, i.e., those voltages which correspond to codes 00 and FF
Hex.
For the specified input and output ranges, I LSB = 19.5 mY,
but will vary with VSWtNG' For both DACs and ADC,
I LSB = 2 VSWING I 256 = FSR I 256.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal I LSB change between any two adjacent
codes. A specified differential nonlinearity of ± I LSB max
ensures monotonicity (DAC) or no missed codes (ADC).
Bias Offset Error
For an ideal ADC, the output code for an input voltage equal to
VBIAS (ADC), should be 80 Hex (10000000 binary). The ADC
Bias Offset Error is the difference between the actual midpoint
voltage for code 80 Hex and VBIAS (ADC), expressed in LSBs.
For an ideal DAC, the output voltage for code 80 Hex should
be equal to VBIAS (DAC). The DAC Bias Offset Error is the
difference between the actual output voltage and VBIAS (DAC),
expressed in LSBs.
Plus and Minus Full-Scale Error
The ADC and DACs in the AD7769 can be considered as
devices with bipolar (plus and minus) input ranges, but referred
to VBIAS instead of AGND. Plus Full-Scale Error for the ADC
is the difference between the actual input voltage at the FE to
FF code transition and the ideal input voltage (VBIAS + VSWING
-1.5 LSB), expressed in LSBs. Minus Full-Scale Error is similarly specified for the 0 I to 00 code transition, relative to the
ideal input voltage for this transition (VBIAS - VSWING
+0.5 LSB). Plus Full-Scale Error for the DACs is the difference, expressed in LSBs, between the actual output voltage for
input code FF and the ideal voltage (V BIAS + VSWING I LSB). Minus Full-Scale Error is similarly specified for code
00, relative to the ideal output voltage (VBIAS - VSWING)' Note
that Plus and Minus Full-Scale errors for the ADC and the
DAC outputs are measured after their respective Bias Offset
errors have been adjusted out.
Digital-to-Analog Glitch Impulse
Digital-to-Analog Glitch Impulse is the impulse injected into the
analog outputs when the digital inputs change state with either
DAC selected. It is normally specified as the area of the glitch
in n V secs and is measured when the digital input code is
changed by I LSB at the major carry transition.
Digital Feedthrough
Digital Feedthrough is also a measure of the impulse injected
into the analog outputs from the digital inputs but is measured
when the DACs are not selected. It is essentially feedthrough
across the die and package. It is important in the AD7769 since
it is a measure of the glitch impulse transferred to the analog
outputs when data is read from the ADC register. It is specified
in nV secs and is measured with WR high and a digital code
change from all Os to all Is.
Signal-to-Noise Ratio (SNR)
SNR is the measured Signal-to-Noise Ratio at the output of the
converter. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency. SNR is dependent on the number
of quantization levels used in the digitization process; the more
levels, the smaller the quantization noise. The theoretical SNR
for a sine wave is given by
SNR
=
(6.02N + 1.76) dB
where N is the number of bits. Thus for an ideal 8-bit converter, SNR = 49.92 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7769, Total Harmonic Distortion is defined as
20 log
(V 2+V 2+V 2+V 2+V 2)112
2
l
~l 5
6
where V I is the rms amplitude of the fundamental and V2'
V" V., Vs and V6 are the rms amplitudes of the individual
harmonics.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, f. and
fb' any active device with nonlinearities will create distortion
products, of order (m+n), at sum and difference frequencies of
mf.+nfb' where m, n = 0, 1,2,3 ... Intermodulation terms
are those for which m or n is not equal to zero. For example,
the second order terms include (f. +fb) and (f. -fb) and the third
order terms include (2f. +fb), (2f. -fb), (fa + 2fb) and (f. - 2fb).
ANALOG- TO-DIGITAL CONVERTERS 3-331
LOGIC TRUTH TABLE
ADC CHANNEL SELECT AND START CONVERSION
CS
ADCIDAC
CHAfCHB
WR
RD
DBo-DB7
INT
Comments
0
0
0
0
0
0
X
t.
S"
S"
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
1
1
1
0
INT Is Set on Falling Edge of WR.
Select ADC Channel A and Start Conversion.
Select ADC Channel B and Start Conversion.
INT Goes Low at End of Conversion.
WR
X
X
X
RD
DBo-DB7
INT
Comments
t.
0
~
ADC Data
ADC Data
High-Z
1
1
1
INT Is Set High on Falling Edge of RD.
ADC Data on Data Bus.
Data Outputs High Impedance.
0
1
READ ADC DATA
CS
ADClDAC
CHAlCHB
0
0
0
X
X
X
X
X
X
WRITE TO DACA OR DACB
CS
ADClDAC
CHAlCHB
WR
RD
DBo-DB7
INT
Comments
0
0
0
0
1
1
1
1
1
0
1
0
i
~
~
~
1
1
0
N/C
N/C
N/C
X
X
X
J.LP Data
J.LP Data
ADC Data
ADC Data
High-Z
J.LP Writing Data to DACA.
....p Writing Data to DACB.
Data from Last ADC Conversion Will Be Written to DACA.
Data from Last ADC Conversion Will Be Written to DACB.
No Operation.
S
0
X
NiC
N/C
NOTES
'If RO
= 1, OB{)--OB7 will remain high impedance. If RO = 0, OB{)--OB7 will output previous AOC data. The RO input should not change during a
conversion.
2X = Don't Care.
'N/C = No Change.
CIRCUIT DESCRIPTION
Analog Inputs and Outputs
The AD7769 provides the analog-to-digital and digital-to-analog
conversion functions required between the microcontroller and
the servo power amplifier in digital servo systems. It is intended
primarily for closed loop head positioning in Winchester disk
drives but may also be used for microstepping in drives with
stepper motor head positioning or other servo applications. The
AD7769 contains a high speed, 8-bit, sampling ADC with two
input channels and two 8-bit DACs with output buffer amplifiers. A unique feature of the AD7769 is the input and output
signal conditioning circuitry which allows the analog input and
output voltages to be referred to a point other than analog
ground. The input range and offset of the ADC, the output
swing and offset of the DACs may be adjusted independently by
the application of ground-referenced, positive control voltages,
VBIAS (ADC), VSWING (ADC), VBIAS (DAC) and VSWING
(DAC). Thus, for example, the peak-to-peak output swing of
the DACs could be set to 3 V above and 3 V below a bias voltageof5V.
Figures 5 and 6 show the transfer functions of the ADC and
DACs and their relationship to VBIAS and V SWING' The midpoint code of the ADC, 80 Hex (10000000 Binary), occurs at an
input voltage equal to VBIAS' The input FSR of the ADC is
equal to 2 VSWING' so that the Plus Full-Scale code transition
(FE to FF Hex) occurs at a voltage equal to VBIAS + VSWING
-1.5 LSBs and the Minus Full-Scale code transition (01 to 00
Hex) occurs at a voltage VBIAS - VSWING +0.5 LSBs. The
transfer function of the D ACs bears a similar relationship to
VBIAS and VSWING' The DAC output voltage for code 80 Hex
3-332 ANALOG-TO-DIGITAL CONVERTERS
(10000000 binary) is equal to VBIAS ' whilst FF Hex (11111111
binary) gives an output voltage of VBIAS + VSWING -1 LSB
(Plus Full-Scale) and 00 Hex gives an output voltage of VBIAS
- VSWING (Minus Full-Scale).
The ability to refer input and output signals to some voltage
other than ground is of particular importance in disk drive
applications. Typically, only + 5 V digital and + 12 V analog
supply voltages are available, and the analog signals are often
referred to a voltage around half the analog supply.
VBIAS+ VSWING
VSIAS-VSWING
ANALOG INPUT. V,.A. V'NB
Figure 5. ADC Transfer Function
AD7769
ADC Conversion Cycle
Figure 8 shows the operating waveforms for a conversion cycle.
On the rising edge of WR, the conversion cycle starts with the
acquisition and tracking of the selected ADC channel, VINA or
VINB. The analog input voltage is held 50 ns (typically) after
the fourth falling edge of the input CLK following a conversion
start. If to in Figure 8 is greater than 150 ns, then the falling
edge of the input CLK will be seen as the first falling clock
edge. If to is less than 150 ns, the first falling clock edge to be
recogruzed will not occur until one cycle later.
00
01
02
80
FE FF
V OUT
= VBlAS+VSWING
Jl.
elK
DAC A. DACB INPUT CODE (HEX)
I
(2D-1)
I
where 0 = N/256
N
I
I
I
= DAC INPUT CODE IN DECIMAL
I
I
I
I
I
Figure 6. DAC Transfer Function
DB7IMSB)
Driving the Analog Inputs and Reference Inputs
The analog inputs, VINA and VINB, must be driven from low
output impedance sources, such as from op amps. In addition,
VBIAS (ADC) must be driven from a similar type low impedance
source (e.g., voltage reference).
Op amps are not required to drive the VSWING (ADC), VBIAS
(DAC) and VSWING (DAC) inputs as these are high impedance
inputs (200 nA typical input current) that feed into on-chip
buffer amplifiers. The reference voltages for these inputs can be
derived using suitable resistor divider networks.
The analog reference available in the disk drive system can be
used to set the bias voltage of the AD7769, and could also be
attenuated to provide the reference for the input and output
swing as shown in Figure 7. The same bias voltage would generally (though not necessarily) be used for the ADC and the
DACs, though the input and output ranges might be different.
AD7769*
v••
+12 V
+5 V
Vee
ANALOG
REF
R1
L
R3
v B.....S
(DAC)
VB'AS
(ADC)
V SWING (DAe)
p---
~
~
p.FTo.,
f,.O I-lFTo.1 flFf,.O
GND
R2
pF
V SWING (ADe)
R4
1
AGND IDAe)
AGND IADel
• ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. Typical Analog Connections to the AD7769
I
I
DBO IlSB)
*nMING SHOWN FOR to GREATER THAN 150 ns
Figure 8. Operating Waveforms Using External Clock
Following the "hold" on the analog input, the MSB decision is
made approximately 50 ns after the next falling edge of the
input CLK. The succeeding bit decisions are made approximately 50 ns after a CLK edge until conversion is complete. At
the end of conversion, the INT line goes low 100 ns (typically)
after the LSB decision and the SAR contents are transferred to
the output latch. The SAR is then reset in readiness for a new
conversion.
Track-and-Hold
The track-and-hold (T/H) amplifier on the analog input to the
ADC of the AD7769 allows the ADC to accurately convert an
input sine wave of 5 V peak-to-peak amplitude up to a
frequency of 200 kHz, the Nyquist frequency of the ADC when
operated at its maximum throughput rate of 400 kHz. This
maximum rate of conversion includes conversion time and time
between conversions. Because the input bandwidth of the trackand-hold is much greater than 200 kHz, the input signal should
be band limited to avoid folding unwanted signals into the band
of interest.
DAC Outputs
The D/A converter outputs are buffered with on-board, high
speed op amps that are capable of driving 5 k!l and 100 pF
loads to AGND (DAC). Each output amplifier settles to within
112 LSB of its final output value in typically less than 2.5 /J-S.
See Figures 9 and 10 for waveforms of the typical output settling time performance.
The output noise from the amplifiers with full scale on the
DACs is typically 200 /J- V peak-to-peak.
ANALOG-TO-DIGITAL CONVERTERS 3-333
L
I
I
I
-
fairly straightforward operations of reading ADC data and writing data to the DACs, and need little explanation. Figure 11
shows the timing for ADC channel selection and conversion
start. This is more complicated as the state of the data outputs
during a conversion depends on CS and RD.
V
TA
= +25"C
Voo= +12 V
Vee = +5 V
VBlAS = +5 V
~o;orzoO;';!~: ~
ns/DIV VERnCAL: 0.6 V/DIV
il
To initiate a conversion (or any other operation) the device must
be selected by taking CS low. A conversion is started by taking
WR low, then high again (conversion starts on rising edge of
WR). There are three possibilities for the state of the data outputs during the conversion.
1. If RD is held high, the data outputs will be high impedance
throughout the conversion.
II
~
2. If RD and CS are both held low until after INT goes low,
then DBO-DB7 will initially output data from the last conversion. Mter INT goes low the new conversion data will
appear on DBO-DB7.
Figure 9. Positive-Going Settling Time
C11
T.
f--H--t--+--If---t\
= +25'C
V DD = +1Z
v
~~~: =+~5V v
+-+--i
I
I
t---\!---t--t--If---t- ~oRizo~;!~: ~5 ns/DIV
-
VERTICAL: 0,6 V/DIV
3. If RD is held low but CS is taken high during the conversion, the device will be de-selected and DBO-DB7 will revert
to their high impedance state. This will not affect completion
of the conversion, but the data cannot be read, or any other
operation performed, until CS is taken low again.
4. Note that the state of RD should not be changed during a
conversion.
1\
\
\
\.
ADC/DAC
CHA/CHB
--~\~--
__
~J~
______
4~
_____________
Figure 10. Negative-Going Settling Time
Internal 1 External Clock Operation
The AD7769 can be operated on either its own internal clock
or with an externally applied clock signal. For internal clock
operation the CLK input must be tied to Vnn. No external
components are required. The internal clock typically runs at
5 MHz giving a typical conversion time of 2.5 I1S. For external
clock operation the CLK input must be driven with a TTLI
HCMOS compatible input. The mark/space ratio of the clock
signal can vary from 30170 to 70/30. For an input frequency of
5 MHz, the conversion time is 2.5 I1S.
Digital Inputs and Outputs
The AD7769 communicates over a standard, 8-bit microprocessor data bus and is controlled by standard mpu control lines,
CS, WR, RD, INT, plus two address lines, ADClDAC and
CHAICHB, which select the DAC or ADC function and Channel A or Channel B input/output channel. The Chip Select.(CS)
line selects the device, Write (WR) is used to initiate ADC conversions or to write data to the DAC, depending on the state of
ADClDAC. INT is a status flag that indicates completion of a
conversion, while RD is used to read ADC output data. The
8-bit data port (DBO-DB7) is a bidirectional port into which
data can be wrinen to the two DAC registers, and from which
data can be read from the ADC register. ADC output data may
also be written directly into either of the DAC registers.
These logical operations are detailed in Table I and in the timing diagrams, Figures II to 13. Figures 12 and 13 show the
3-334 ANALOG-TO-DIGITAL CONVERTERS
----=-~+----=.. ~
INT _ _ _-+-JI
'''S
r------,
- - -- -- --f;:::::::'---- __ }
- - - - - - - -Sf-----"\
DBO-DB7
(iiii = 0)
PREVIOUS ADC DATA
HIGH
IMPEDANCE
NEW ADC DATA
~~~~~ ------------~H~~~H~IM~P~E~DA~N~C~E~(ri-------------
Figure 11. Timing for ADC Channel Select and Conversion
Start
."-.fo--------.,, ------~."
1'-----+-----------'1.-."
DATA
--------t-----{==~V~AL~ID~D~A~T~A==j
INT ________+-...11
Figure 12. Timing for ADC Data Read
AD7769
down to the DAC. The output spectrum is analyzed, using a
spectrum analyzer to evaluate SNR and harmonic distortion performance. Similarly, for intermodulation distortion, an input
(either to VIN or DAC code) consisting of pure sine waves at
two frequencies is applied to the AD7769.
ADC/OAC
CHA/CHB
080-081
V ouT A,8
Figure 14 shows a 2048 point FFT plot of the ADC with an
input signal of 130 kHz. The SNR is 49.2 dB. It can be seen
that most of the harmonics are buried in the noise floor. It
should be noted that the harmonics are taken into account when
calculating the SNR. The relationship between SNR and resolution (N) is expressed by the following equation:
--'I'~--+------+---'I'-4.----
------+-~~------_+--~4r------
J~t
.r
- ---------l------f'"
SNR
±1I2 LSB
NOTE 1
NOTE 1. THE TIME AXIS IS COMPRESSED FOR THIS SECTION OF THE DIAGRAM
Figure 13. Timing for DAC Channel Select and Data Write
DIGITAL SIGNAL PROCESSING APPLICATIONS
In Digital Signal Processing (DSP) application areas like voice
recognition, echo cancellation and adaptive filtering, the
dynamic characteristics (SNR, Harmonic Distortion, Intermodulation Distortion) of both the ADC and DACs are critical. The
AD7769 is specified dynamically as well as with standard dc
specifications. Because the track/hold amplifier has a wide bandwidth, an antialiasing filter should be placed on the VINA and
VINB inputs to avoid aliasing of high frequency noise back into
the bands of interest.
The dynamic performance of the ADC is evaluated by applying
a sine wave signal of very low distortion to the V1NA or VINB
input which is sampled at a 409.6 kHz sampling rate. A Fast
Fourier Transform (FFT) plot or Histogram plot is then generated from which SNR, harmonic distortion and dynamic differential nonlinearity data can be obtained. For the DACs, the
codes for an ideal sine wave are stored in PROM and loaded
=
(6.02N + 1.76) dB
This is for an ideal part with no differential or integral linearity
errors. These errors will cause a degradation in SNR. By working backwards from the above equation, it is possible to get a
measure of ADC performance expressed in effective number of
bits (N). The effective number of bits is plotted versus frequency in Figure 15. The effective number of bits typically falls
between 7.7 and 7.9, corresponding to SNR Figures 48.1 and
49.7 dB.
Figure 16 shows a spectrum analyzer plot of the output spectrum from one of the DACs with an ideal sine wave table loaded
to the data inputs of the DAC. In this case, the SNR is 47 dB.
'"
oiii 7.5 I - - - - - - - - - - - - - - - - - _ _ j
~
~
7~----------------__j
Z
w
>
i"'
=
TA
25'C
SAMPLE FREQUENCY = 409.6 kHz
INPUT FREQUENCY
~
204.8
kHz
Figure 15. Effective Number of Bits vs. Frequency
INPUT FREQUENCY 0= 1306kHz
SAMPLE FREQUENCY = 409.6 kHz
SNR = 48.4 dB
TA = 25"C
-20~----------~------1
TA=25°C
-40~----------~-----~
-'0
-40
-60
-80
I
I
J
-I"""
-100
FREQUENCY
~
kHz
Figure 14. ADC FFT Plot
START 0 Hz
RBW 30Hz
VBW3 Hz
STOP 50000 Hz
ST 28.9 MIN
Figure 16. DAC Output Spectrum
ANALOG-TO-DIGITAL CONVERTERS 3-335
II
Histogram Plot
When a sine wave of specified frequency is applied to the V1NA
or V1NB input of the AD7769 and several thousand samples are
taken, it is possible to plot a histogram showing the frequency
of occurrence of each of the 256 ADC codes. If a particular step
is wider than the ideal 1 LSB width, then the code associated
with that step will accumulate more counts than for the code for
an ideal step. Likewise, a step narrower than ideal width will
have fewer counts. Missing codes are easily seen because a
missing code means zero counts for a particular code. The
absence of large spikes in the plot indicates small differential
nonlinearity.
MICROPROCESSOR I MICROCOMPUTER
INTERFACING
The AD7769 is designed for easy interfacing to microprocessors
and microcomputers as a memory mapped peripheral or an 110
device. In addition, the AD7769 high speed bus timing allows
direct interfacing to many DSP processors such as the
TMS32OClO and ADSP-2101.
Figure 17 shows a histogram plot for the ADC indicating very
small differential nonlinearity and no missing codes for an input
frequency of 204 kHz. For a sine wave input, a perfect ADC
would produce a probability density function described by the
equation:
Conversion is initiated on the selected AD7769 ADC channel
using a single 110 instruction, . The processor
then polls INT until it goes low before reading the conversion
result using an instruction. Writing data
to the relevant AD7769 DAC consists of an
instruction.
AD7769 - TMS32OCIO Interface
A typical interface to the TMS32OClO is shown in Figure 18.
The AD7769 is mapped at a port address, and the interface is
designed for the maximum TMS32OCIO clock frequency of
20 MHz.
".vhere "AI. is t...'le peak amplitude of the sine wave and p (V) the
probability of occurrence at a voltage V. The histogram plot of
Figure 17 corresponds very well with this shape.
MEN
TMS320C10
In digital signal processing applications, where the AD7769 is
used to sample AC signals, it is essential that the signal sampling occurs at exactly equal intervals. This minimizes errors
due to sampling uncertainty or jitter. A precise timer or clock
source, to start the conversion process, is the best method of
generating equidistant sampling intervals.
H>-1
1 ) - cs
PA2
ADC/DAC
PAO
CHA/CHB
WE
WR
DEN
iiii
INT
INT
DB7
----r----,
II
2500 , - - - - . - - - - -....
DBO
D7 O
-O
D15
INPUT FREQUENCY = 204.2 kHz
SAMPlE FREQUENCV
AD7769*
PAl
= 409.6 kHz
= 100.000
DO
NUMBER OF SAMPLES
TA = 25°C
.
)
DATA BUS
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. AD7769 to TMS320C10 Interface
1250
Il----+------!------J------fl
DM13
DMol-----,
ADSP-2101
DMS
..
128
CODE
192
Figure 17. ADC Histogram Plot
255
I - -.....q
WR ~----------<"WR
iiii
iiii
IRQ2
\iiff
.-----~DB7
DI51-------'
DOI---~~~-----J
• ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. AD7769 to ADSP-2101lnterface
3-336 ANALOG-TO-DIGITAL CONVERTERS
AD7769
AD7769 - ADSP-2101 Interface
Figure 19 shows a typical interface to the DSP microcomputer,
the ADSP-2101. The ADSP-2101 is optimized for high speed
numeric processing tasks.
Because the instruction cycle of the ADSP-2101 is very fast
(80 ns cycle), the WR and RD pulses must be stretched out to
suit the AD7769. This is easily achieved as the ADSP-2101
memory interface supports slower memories and memorymapped peripherals (i.e., AD7769) with a programmable wait
state generation capability. A number of wait states, from 0 to
7, can be specified for each memory interface. One wait state is
sufficient for the interface to the AD7769.
AD7769 - 8051 Interface
A choice of two interface modes are available
microcomputer.
8051
P3.0
cs
P3.1
CHA/CHB
P3.3
ADC/DAC
P3.4
WR
P3.5
iID
P3.2
iNT
P1.7
DB7
P1.0
DBO
AD7769*
• ADDITIONAL PINS OMITTED FOR CLARITY
~o
the 80S 1
Figure 20 shows a typical interface to the 80S 1 processor bus. It
is suitable for the maximum 8051 clock frequency of 12 MHz.
In this interface mode, Port 0 provides the multiplexed low
order address and data bus and Port 2 provides the high order
address bus (As-A 15).
Figure 21 shows the AD7769 interfaced to the 80S 1 parallel 1/0
ports. This interface circuit is simpler to implement than the
previous interface to the processor bus, but, in general, the
maximum data throughput rate is much slower (for the same
clock frequencies). In addition to its simplicity, the interface to
the parallel 110 ports versus the processor bus allows independent control of both the WR and RD inputs to the AD7769.
For example, the 8051 can set both WR and RD low at the
same time. This permits data from the last ADC conversion to
be written directly from the ADC register into the selected DAC
register (see Logic Truth Table). This allows very fast transfer
of data from the ADC to the DAC and is a useful feature for
some applications such as a fast, programmable, infmite sampleand-hold function.
Figure 21. AD7769 to 8051 (Parallel 110 Ports) Interface
AD7769 - MC68HCll Interface
Figure 22 shows a typical interface between the AD7769 and the
MC68HCll microcomputer. This interface is designed for the
maximum MC68HCll clock speed of 8.4 MHz. The microcomputer is operated in the expanded multiplexed mode, with the
AD7769 as a memory mapped peripheral. The expansion bus is
made up of Ports Band C, and control signals AS and RIW.
MC68HC11
PC.7
ADDRESS/DATA BUS
~.or----------------J
• ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. AD7769 to MC68HC11 Interfaced
8051
APPLICATIONS
The AD7769 analog 1/0 port is used to convert servo related
signals between the analog and digital domains. The input structure of the two-channel ADC makes it very easy to convert the
typical output signals provided by a servo demodulator.
PO.7
PO.O
r-------------'
• ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. AD7769 to 8051 (Processor Bus) Interface
In a magnetic disk drive employing a dedicated servo surface,
the servo demodulator produces two, positive-only, quadrature
signals, generally sinusoidal or triangular, from the di-bit
patterns read from the servo surface. The quadrature signals
have the form of VBIAS ± VSWING. The very fast conversion
time of the AD7769 ADC allows sequential conversion of these
ANALOG- TO-DIGITAL CONVERTERS 3-337
II
quadrature signals without introducing significant phase delay
errors. These converted signals provide the servo microcontroller with position and track crossing information from which
velocity information can be derived. In optical disk drives, analogous servo signals can be derived from the quad photodiode
detector to provide position and focus information for the
microcontroller.
The two DACs in the AD7769 accept servo data from the
microcontroller to position the head assembly. The DACs provide positive-only output signals of the form V BIAS ± V SWING'
which are ideal for driving voice coil motors. In magnetic disk
drives, a single voice coil motor is used .to position the head
assembly and one DAC is usually sufficient to drive the motor
in both the seek and track modes. In the seek mode, the DAC
can be used to generate directly the desired analog velocity trajectory which the head must travel in order to achieve minimum
access times. Alternatively, the DAC can generate a servo error
value (computed by the microcontroller) between the actual
head velocity and the desired head velocity. In the track mode,
the DAC can be used to provide a position error signal to keep
the head over the track or to detent the head otl track, for such
purposes as thermal compensation and soft error retrys. The
second DAC in the AD7769 may be employed in this fine positioning loop. Alternatively, the second DAC can be used to control the speed of the spindle motor via a pulse width modulator.
In optical disk drives two voice coil motors are used, requiring
both DACs of the AD7769-one for the focus servo loop and
one for the radial positioning servo loop.
A typical servo control loop using the AD7769 is shown in Figure 23. In this dedicated servo drive, the servo demodulator
converts the servo information bit patterns from the disk into
the standard N and Q (normal and quadrature) servo signals.
The voice coil motor current, Iu is bidirectional and is supplied
DRIVE
INTERFACE
by the power transconductance amplifier. One input to this
amplifier is held at VBIAS (DAC), while the other input is
driven from a DAC output, V OUT AlB. Typical input/output
waveforms for this power stage are shown in Figure 24. The
transconductance, Go, of the power stage is determined by
external sense resistors.
~ ~.'-'
~'~-(
VOUT AlB
.....
VaWING
0
DAC)
>
VB1AS (DACI
----- -
o
V B1AS (DAC) VSWING (DAC)
•
VOICE
COIL
CURRENT
I,
IL MAX
IL
= ±VSWING (DAC) Go
= V AlB Go
OUT
Figure 24. Typical Relationship Between Input Voltage
and Output Current for Transconductance Amplifier
Increased Resolution DAC Output
Since both VBIAS (DAC) and V SWING (DAC) are common to
both output channels, the full-scale output voltages of both
channels are nominally identical. However, by adding an external op amp and scaling resistors, it is possible to attenuate the
full-scale output voltage of one (or both) of the DAC outputs to
effectively increase the output voltage resolution. Figure 25
shows channel A being attenuated using a resistor scaling of
10:1. The attenuated output voltage, VOUTA', is
VouTA' = VBIAS
+
(VsWINdlO)(2DA -I).
The output voltage of Channel B remains at
VouTB = VBIAS
+
VSWING
IWB -I).
SERVO
SERVO DEMODULATOR
PREAMP
R
N
,
,,,
,
AD7769
VouTA'
10R
I
Vs1As{ADCI
I
V SWlIIIG lADe)
:
10 R
VBIASIDACI
VouTA
VsWlNG{DACI
I
R
,
I
I
I
I
V B1AS (DAC)
:
V BIAS
I
L__ _
VouTB
VouTB
ValAS {DACI
V SWING
POWER
(DACI
VSWING
TRANSCONDUCTANCE
AMPLIFIER
Figure 23. Typical Dedicated Servo Control Loop Using
the AD7769
3-338 ANALOG-TO-DIGITAL CONVERTERS
Figure 25. Increasing the DAC Output Voltage Resolution
AD7769
D A and DB are fractional representations of the DAC input
codes, e.g., DA = N A /256 and DB = N B /256. For example,
with a VSWING voltage level of 2 V, the Channel B output span
is 4 V with an LSB size of 15.6 mV and (attenuated) Channel A
output span is 400 mV with an LSB size of 1.56 mY. Changing
the resistor scaling in Figure 25 obviously changes the attenuated full-scale output.
A single change to the circuit Figure 25 allows the two DAC
outputs to be combined to provide a single analog output with
resolution beyond the standard 8-bits. Figure 26 shows the rearranged circuit. The composite output, VOUT> is
or
R
lOR
AD7769
I+
lOR
VouTA
AI
1
V OUT
R
V B1AS (DACI
V B1AS
its current on-track position to permit reading of off-track data.
The circuit is shown in Figure 27. With the 10: I resistor scaling
used in the circuit the output voltage, VOUT> is
VO UT = V PE + (VsWINdIO) (2DA-I).
With no offset added, VOUT = VPE' where VPE is the position
error voltage which the servo loop normally drives to its zero
level, VBIAS ' When an offset voltage is supplied by DAC A, the
action of the servo is to move the head away from its current
on-track position until the position error voltage is equal and
opposite to the offset voltage. The position of the head about
the track centre is thus programmable.
Programmable Full-Scale Range
The output voltage span of both DACs is determined by the
VSWING (DAC) voltage level. This is normally supplied from
some fixed voltage source. However, is is possible to use one
of the DAC channels to generate a programmable VSWING voltage level. The remaining channel will thus have a full-scale
range and LSB size which is software programmable. This circuit is shown in Figure 28 where VoUTB is used in an implicit
feedback loop to generate a programmable swing voltage,
VSWING (DAC), for the AD7769 from an external fixed input
swing voltage, VSWING ' Using the 5:1 resistor scaling shown in
Figure 28, the expression for the AD7669 input swing voltage is
VSWING
VouTB
VSWlNG (DAC)
(DAC) =
VSW1NG
1- (2DB-I)
5
VSWING
For example, with a fixed input swing voltage of 2.5 V, the programmable span via DAC B is as follows:
Figure 26. Combined Vou.,A, VourB Circuit
DAC A can be programmed to produce an interpolation function between the 8-bit steps of DAC B to allow, for example,
very smooth velocity profile waveforms to be generated.
Servo Offset Facility
Most dedicated servo disk drives offer an offset facility whereby
some small voltage is injected into the track-following loop. The
purpose of the offset is to move the head to the right or left of
R
AD7769
DB = 0:
VSWING (DAC) = 2.08
DB = 112:
VSWING (DAC) = 2.5 V = VSWING
DB"" I:
VSWING (DAC) = 3.125 V
The AD7769 is specified for a VSWING (DAC) voltage range
from 2 V to 3 V, although in practice this range can be
extended while still maintaining monotonic operation.
AD7769
VouTA t - - - - - - - - - V o u T A
r - - - - - - - - - Q V B1AS (DAC)
R
10 R
lOR
V.,A_ (DACI
SR
R
V ... _ (DACII--.....-o V B1AS
SR
HI-'VV'..-~
v.,
V SWlNG
(FIXEDI
VouTBI---. VOUTB
VSWING
(DACI
V_WING (DACI t - - - - - - - - - . . . . l
1---0 VSWING
Figure 28. Generating a Software Programmable VSWING
(DAC)
Figure 27. Servo Offset Facility
ANALOG-TO-DIGITAL CONVERTERS 3-339
Closed Loop Microstepping
Microstepping is a popular technique in low density disk drives
(both floppy and hard disk) which allows higher positional resolution of the disk drive head over that obtainable from a fullstep driven stepper motor. Typically, a two-phase stepper motor
has its phase currents driven with a sine-cosine relationship.
These cosinusoidal signals are generated by two DACs driven
with the appropriate data. The resolution of the DACs determines the number of microsteps into which each full step can be
divided. For example, with a 1.8° full-step motor and a 4-bit
DAC, a microstep size of 0.11 ° (1.8°/2n) is obtainable.
The microstepping technique improves the positioning resolution possible in any control application. However, the positional
accuracy can be significantly worse than that offered by the original full-step accuracy specification due to load torque effects.
To ensure that the increased resolution is useable, it is therefore
necessary to use a closed-loop system where the position of the
disk drive head (or motor) is monitored. The closed-loop system
allows an error between the desired position and the actual position to be monitored and corrected. The correction is achieved
by adjusting the ratio of t..lte phase currents in the motor wi...~d
ings until the required head position is reached.
+12V +5V
v. v..
CONTROLLER
V.,.A VINS
V~,A
OUT1A
UDN2917
&A
VAE " "
A07769*
vo"",
V_B
o
twO
PHASE
ST~ER
MOTOR
OUT2A
OUT1B
PHASE A OUT2B
ENABLE A
PHASE B
RCB
ENABLE B
ANODE A
ANODE B
OND
RCA
YouTA
"SINE" PHASE
-
- - +VSWING
(DACI
VlJIAs(DAC)
- - - - - - - -Ys-.oIDACl
VouTB
"COSINE" PHASE
- - -
-VSWlNG
(DACI
=·I~-----..,
=-[. __
...L_ _ _ _ _...L_ _ _ __
Figure 30. Typical Control Waveforms for the Microstepping Circuit of Figure 29
Multichannel Expansion
In some applications, more than two analog input channels are
required to be converted by the ADC. Figure 31 shows a circuit
configuration for such an application. The ADG528A is a
latched, 8-channel analog multiplexer that is ideally suited for
this application since it is specified for single supply operation
(+12 V ±1O%).
The CS, ADClDAC and WR inputs of the AD7769 are gated to
drive the WR input of the ADG528A. The multiplexer input
signal is selected on the falling edge of the WR pulse while the
signal is latched on the rising edge. Also, on the rising edge of
WR, the AD7769 ADC starts conversion. Therefore, the output
signal of the multiplexer must have settled to within 8-bits over
the duration of the WR pulse (see ADC Conversion Cycle section for details). The tON (WR) and settling time of the
ADG528A thus determines the width of the WR pulse.
*ADDmoNAL PINS OMmeD FOR CLARfTY
Figure 29. Typical Closed-Loop Microstepping Circuit with
the AD7769
AD7769*
ADG528A
DB.
AINO
DBB
AIN1
The AD7769 is ideally suited for the closed-loop microstepping
technique with its dual DACs for positioning the disk drive
head and dual channel ADC for monitoring the position of the
head. A typical circuit for a closed-loop microstepping system is
shown in Figure 29. The DAC waveforms are shown in Figure
30 along with the direction information of clockwise rotation
supplied by the controller.
A typical transducer would be a moire-fringe transducer which
consists of two gratings, one fixed and one moveable. The relative positions of these two gratings will modulate the amount of
light from a LED which can pass through. In order to derive
head direction information the stationary grating has two sets of
bars, with a 90° phase relationship, and two photo-transistors.
The quadrature sinusoidal output waveforms (N & Q) can be
converted directly by the AD7769.
3-340 ANALOG-TO-DIGITAL CONVERTERS
AIN8
AIN9
wVINe
·ADDITIONAL PINS OMlneD FOR CLARITY
Figure 31. Multichannel Inputs
FROM
.p
~ANALOG
WDEVICES
FEATURES
12-Bit Resolution and Accuracy
Fast Conversion Time: 10fLS
Serial Output
Complete with On-Chip Reference
Low Power
Unipolar or Bipolar Input Ranges
Small 0.3", 20-Pin DIPs and 20-Terminal Surface
Mount Package
GENERAL DESCRIPTION
The AD7772 is a complete 12-bit ADC that offers high speed
performance combined with low, CMOS power levels. It uses
an accurate, high speed DAC and comparator in a successive
approximation loop to achieve a fast conversion time. An on-chip,
buried Zener diode provides a stable reference voltage to give
low drift performance over the full temperature range, and the
specified accuracy is achieved without any user trims. The AD7772
can be configured to have analog input ranges of 0 to + SV, 0 to
+IOV, ±SVor ±lOV.
An on-chip clock circuit is provided, which may be used with a
crystal for stand-alone operation. Alternatively, the clock input
may be driven from an external clock source such as a divided-down
microprocessor clock.
The AD7772 serial interface is compatible with digital signal
processors such as the TMS32020, ,..PD7720 and DSPS6000. It
can also be used with general purpose serial to parallel converters
such as shift registers. The device outputs the conversion result
with one leading zero and the twelve data bits following. When
using the AD7772 at top speed (CLKIN = 1.28MHz) with a
3,..s sample-and-hold amplifier like the ADS8S, it is possible to
achieve throughput rates of 76kHz. With this 76kHz sample
rate signals with spectral contents up to 38kHz can be digitized.
LC 2MOS
Serial Output 12-Bit ADC
AD7772 I
AD7772 FUNCTIONAL BLOCK DIAGRAM
•
PRODUCT HIGHLIGHTS
1. Fast, lO,..s conversion time makes the AD7772 ideal for a
wide range of applications in telecommunications, sonar and
radar signal processing and industrial data acquisition systems
requiring optical isolation.
2. Where space saving is important, the small package and
serial interface of the AD7772 minimize the amount of board
space needed to realize 12-bit data acquisition.
3. The versatile serial interface on the AD7772 makes it simple
to interface to the serial ports of DSPs as well as other
microprocessor systems.
4. On-chip buried Zener reference has temperature coefficient
as low as 2Sppmt'C, giving low full-scale drift over the operating
temperature range.
5. Stable DAC and comparator give excellent linearity and low
zero error over the full temperature range.
6. LC2 MOS circuitry gives low power drain (13SmW) from
+ 5V, - lSV supplies.
The AD7772 is fabricated in Analog Devices Linear Compatible
CMOS process (LC2MOS), an advanced, all ion-implanted
process that combines fast CMOS logic and linear, bipolar circuits
on a single chip, thus achieving excellent linear performance
while still retaining low CMOS power levels.
ANALOG-TO-DIGITAL CONVERTERS 3-341
K,B
Panmeter
C
Venioa.1
LVenioa'
Vetsi.'
Uai..
TootCoaditioaolComma..
12
",I
",I
",I
",8
",8
±lS
",9
12
",112
",112
",I
",4
12
:j:112
Bits
LSBmax
TestedRanso:Olo +5V
"'45
"'4
",10
",5
",9
",7
",35
",314
",I
",4
",4
±IO
",5
",9
",7
",35
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
LSBmax
ppml'Cmax
010 +5
010 + 10
-510+5
-1010+10
010 +5
010+10
-510 +5
-1010 +10
010 +5
010+10
-510+5
-1010+10
Volts
Volts
Volts
3
±O.4
3
±O.4
3
±O.4
mAmax
mAmax
INTERNAL REFERENCE VOLTAGE
VREFOuIPUI@ +25'C
VREFOulPUITC
Output Current Sink Capabilitys
-5.21- 5.3
",40
550
- 5.21-5.3
",25
550
- 5.21- 5.3
",25
550
ppml'ClYP
.,.Amax
POWER SUPPLY REJECTION
VooOuly
'" 112
",112
'" 112
LSBtyp
'" 112
",112
'" 112
LSBtyp
+0.8
+2.4
10
+0.8
+2.4
10
+0.8
+2.4
10
V max
V min
±IO
±10
±10
tA-Amax
VIN
±20
",20
",20
.,.a max
VIN = OtoV OD
+0.4
+4.0
±IO
+0.4
+4.0
±IO
+0.4
+4.0
±IO
V max
V min
.,.a max
ISINK
ACCURACY
Resolution
Integral NonIinearity@25'C
TmintoTmax
Diffcn:ntial Non1inearilY
UaipoiarOffsetError@ +25'C
Tmia to Tm/IX
Unipolar Full Scale Error'@ + 25'C
Bipolar Zero Error@ + 25'C
Tmin to T_
Bipolar Full Scale Error'@ + 25'C
Full Scale TC'"
ANALOG INPUTS
Input Ranges
Unipolar
Bipolar
Input Current
Unipolar
Bipolar
VssOoly
LOGIC INPUTS
CS, NORlCMP, BINI2SC
CONVST, CLKIN
VINL,InputLowVoltage
VINH, Input High Voltage
C IN5 , Input Capacitance
<:S, NORlCMP, BINI2SC
CONVST
liN' Input Current
CLKIN
IIN,InputCurrent
±IS
±IO
VmiJV_
15
15
15
pFmax
10.2
10.2
10.2
.,..max
+5
-15
7
12
135
215
+5
-15
7
12
135
215
+5
-15
7
12
135
215
VNOM
VNOM
mAmax
mAmax
mWlyp
mWmax
NOTES
'Temperature range as follows: K. L versions: 0 to + 7crc
B, C versions: - 2SOC to + 8SOC
llncludes internal voh. reference error.
JFuli Scale TC = .6.FSI.6.T. where AFS is Full Scale change from T,,= +2S"C to Tmln or Tm••.
·lncludes internal vohaae reference drift.
sSample tested to ensure compliance:.
'Power supply current is measured when AOn72 is inactive, i.e., CS:::: CONVST ... SYNC::; HIGH.
Specifications subject to change without notice.
3-342 ANALOG-TO-DIGITAL CONVERTERS
InpulRange:0105VorOlo 10V
Input Range: ± SV to ± lOY
-5.25V"'I%
(Exlernal Load Should Nol Change During Conversion.)
FSChange, Vss = -15V
Voo= +4.75Vlo + 5.25V
FS Change, VDO = + 5V
Vss= -14.25VIO -15.75V
Voo = 5V",5%
pFmax
CONVERSION TIME
Power Dissipation
InpulRanso: ",5Vor '" 10V
Volts
LOGIC OUTPUTS
SOO, SCLK, CLKOSC, SYNC
VOl., Output LowVohage
VoH,OutpulHigh Voltage
Floating State LeakageCurrent
SDO
Floating State Output CapacitanceS
POWER REQUIREMENTS
Vnn
Vss
I Do6
I ss6
No MissiDg Codes Guaranteed T .... 10 T_
Inpul Ranso: 0105VorOlo 10V
Typical TC is 2ppmI'C
InpulRanso: 010 5VorOlo 10V
Inpul Ranso: '" 5V or '" 10V
= OtoVoo
= 1.6mA
IsouacE = 200.,.a
feLK = 1.28MHz. See Control Inputs Synchronization.
±
::!;:
5% for Specified. Performance
5% for Specified. Performance
~ = CONVST = VDO' AIN = 5V
CS = CONVST = Voo,AIN = 5V
AD7772
TIMING CHARACTERISTICS1 (VIJII= +5V, Vss= -15V)
Parameter
t/
t2
t,
t/
ts
r,,'
t,
t.
10
tlO4
Limit at + 25°C
(All Grades)
Limit at T mia, T max
(K,L,B,CGrades)
780
40
545
780
45
0
40
50
60
50
100
780
50
560
780
45
0
50
50
65
50
125
145
235
10
80
t1l4
115
til
190
10
65
Units
Conditions/Comments
nsmin
nsmax
nsmax
nsmin
CLKIN Cycle Time
Propagation Delay between CLKIN and CLKOSC
Propagation Delay between CLKIN and SCLK
SCLK Cycle Time
CS to CONVST Setup Time
CS to SYNC Hold Time
CONVST Pulse Width
SCLKj" to SYNC t. Delay
SCLKj" toSYNCj" Delay
SCLKj" toSDOt. Delay, CL = 20pF
SCLK.l"" toSD0t. Delay,C L = l00pF
SCLKj" to Data Valid, CL = 20pF
SCLK.l"" toDataValid,C L = IOOpF
SCLK.l" to SDO High Impedance
nsmin
nsmin
nsmin
nsmax
nsmax
nsmax
nsmax
nsmax
nsmax
nsmin
•
nsmax
NOTES
'Timing Specifications are sample tested at + 2SOC to ensure compliance. All input control signals are specified with
tr = tf = 50S (100/0 to 90% of + SV) and timed from a voltage level of 1.6V.
'eLKIN Mark/Space Ratio Raoge is 55/45 to 45/55.
'SCLK and SYNC are loaded with the circuit of Figure I.
4[10 and til are measured with the load circuit of Figure 2 and defined as the time required for an output to cross O.8V or 2.4V.
5[12 is defined as the time required for the data lines [0 change O.SV when loaded with the circuit of Figure 3.
Specifications subject to cbange without notice.
+5V
~o, t"*~,
+5V
+5V
!
~3kn
SOD~
SODo---~------~~--o
SOD o---...- - - - - -....~--o
T
CL
..
a. To VOH (t l1 )
b. To
VOL
a. VOH to High-Z
(t I0, t l1 )
Figure 2. Load Circuits for
t 70, tl1 Test
20pF
\70GNO
'&OGNO
Figure 1. SCLK, SYNC
Load Circuit
3kll
SOO~
b. VOL to High-Z
Figure 3. Load Circuits for Bus Relinquish
Time Test (t I2).
5V
OV
ClKIN
ClKOSC
SClK
I
to
I
~~
_ _ _ _""'"'I~t5.1
CS
\...
- --,I--------~--------_7
I
:'t7.l
CONVST
----~V
I
:J
I
I
I
-..I 14- t o
SYNC --------------~I~\L______________~
I t,o I
SOD
5V
ov
I~----~--------------~--------- 5V
OV
I
\...-..J
HIGH IMPEDANCE
I
~
I
...
I I
..-t"
I
11
I
to
-+j
I4-t'2
) HIGH IMPEDANCE
I
I
SJ
~t::IJ
...r
-t
0
Figure 4. AD7772 Timing Diagram.
ANALOG-TO-DIGITAL CONVERTERS 3-343
ABSOLUTE MAXIMUM RATINGS*
= + 25'C unJess otherwise noted)
(T...
VootoDGND .
· . .. -O.3V to +7V
Vss to DGND ..
· . . . +O.3V to -17V
AGND toDGND
-O.3V to Voo +O.3V
Analog Input Voltage to AGND
(BOFS, ±IOV, ±5V,SUM,
+IOV, +5V) . . . . . . .
. . . -15V to + 15V
Digital Input Voltage to DGND
(CLKIN,CS,CONVST,NOR/CMP,
BIN/2SC) . . . . . . . . . . .
-O.3V to VDD +O.3V
Digital Output Voltage to DGND
(SDO, SCLK, SYNC, CKOSC)
· -O.3V to VDD +O.3V
Operating Temperature Range
Commercial (K, L Versions)
. . . 0 to +70·C
- 25°C to + 85·C
Industrial (B, C Versions)
Storage Temperature . . . . .
- 65·C to + 150·C
Power Dissipation (Any Package) to + 75·C
450mW
Derates above + 75·C by . . . . . . . . . . . . . . . 6mWFC
*Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability. Only one Absolute Maximum Rating may be applied at any
onetime.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam sJlould be discharged to tile destination socket before devices are removed.
WARNING!
~~OFVICF
ORDERING INFORMATION1
Accuracy
Grade
Oto +700C
45ppmFC
35ppmFC
±lLSB
±1I2LSB
PlasticDIp2(N-20) Hermetic2 (Q-20)
AD7772BQ
AD7772KN
AD7772LN
AD7772CQ
45ppmFC
35ppmFC
±lLSB
±1I2LSB
PLCC (P-20AY,3
AD7772KP
AD7772LP
Full Scale TC
- 25·C to + 85°C
NOTES
I Analog Devices reserves the right to ship either ceramic or cerdip hermetic packages.
2S ee Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier.
3-344 ANALOG-TO-DIGITAL CONVERTERS
0
AD7772
PIN CONFIGURATIONS
PLCC
DIP
AD7772
AD7772
CONVST
TOP VIEW
(Not to Scale}
TOP VIEW
INot to Scalel
BIN/2SC
elKIN
CLKQSC
SCLK
DONO
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
I
2
3
4
5
+5V
+IOV
VREF
AGND
SUM
6
7
8
±5V
±IOV
BOFS
Analog Input Pin. This is connected as in Figure 9 to provide a + 5V analog input range.
Analog Input Pin. This is connected as in Figure II to provide a + 10V analog input range.
Voltage Reference Output. The AD7772 has its own internal - 5 .25V reference.
Analog Ground
Analog Input Pin. This is connected to the inverting terminal of an op amp for ± 5V to ± 10V analog input
ranges. See Figure B.
Analog Input Pin. Figure 13 shows how this is connected for a ± 5V analog input range.
Analog Input Pin. For ± lOV analog input range see Figure B.
Bipolar Offset Pin. This is tied to VREF for either of the bipolar analog input ranges.
See Figure B.
NOR/CMP and BINf2SC determine the format of the output data. See Table I.
Digital Ground
Serial Data Output
Continuously running Serial Clock Output.
Clock Oscillator Pin. An inverted CLKIN signal appears at CLKOSC when external clock is used.
See CLKIN (Pin 14) description for crystal (resonator).
Clock Input Pin. An external TTL compatible clock may be applied to this pin. Alternatively a crystal or
ceramic resonator may be applied between CLKIN and CLKOSC. See Figure 7.
BINf2SC and NOR/CMP determine the output data format. See Table I.
Conversion Start Input. This signal starts a conversion on its rising edge when CS is low.
Chip Select Input. This active low signal, in conjunction with CONVST, starts a conversion.
This is the framing signal for the serial data output. It goes low on the first rising edge of SCLK
after conversion begins and goes high when conversion is complete.
Negative Supply, -15V
Positive Supply, + SV
12
13
NOR/CMP
DGND
SDO
SCLK
CLKOSC
14
CLKIN
15
16
17
18
BINf2SC
CONVST
CS
SYNC
19
20
Vss
VDD
9
lO
11
NOR/CMP
0
0
BINf2SC
0
1
0
Unipolar
Data Format
Bipolar
Data Format
2s Complement
Straight Binary
Complementary 2s Complement
Complementary Binary
Complementary 2s Complement
Complementary Offset Binary
2s Complement
Offset Binary
Table I. AD7772 Output Coding
ANALOG-TO-DIGITAL CONVERTERS 3-345
TERMINOLOGY
LEAST SIGNIFICANT BIT
An ADC with 12-bit resolution can resolve one part in 212 (114096
of full scale). For the AD7772 operating in the 0 to + 5V range,
ILSB is l:22mV.
NO MISSING CODES
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence
as the analog input level is increased. Thus every code must
have a finite width. For all grades of the AD7772, all 4096
codes are present over the entire operating temperature ranges.
UNIPOLAR OFFSET ERROR
For the unipolar analog input range, the first transition should
occur at a level 1I2LSB above AGND. Unipolar offset error is
defined as the deviation of the actual transition from that point.
This error can be adjusted as explained further on in this data
sheet.
BIPOLAR ZERO ERROR
In the bipolar analog input ranges, bipolar zero is defined as the
middle of code 2048. Bipolar zero error is the actual deviation
from that point. The circuit diagram on page 9 shows how to
adjust this.
3--346 ANALOG-TO-OIGITAL CONVERTERS
UNIPOLAR FULL SCALE ERROR
The last transition in the ADC (from III ... 110 to III . . .Ill
when using straight binary coding) should occur for an analog
value I 1I2LSB below the nominal full scale (4.99816 for 5.000
volts full scale). The full scale error is the deviation of the actual
level at the last transition from the ideal level with unipolar
offset error adjusted to zero. This error can be trimmed out as
shown in Figure 12. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal - 5.25 volts reference.
BIPOLAR FULL SCALE ERROR
In the bipolar mode, the ADC has a positive full scale error and
a negative full scale error. Positive full scale error is the deviation
of the actual level at the last transition from the ideal level, with
bipolar zero error adjusted to zero. Negative full scale error is
the deviation of the actual level at the first transition from the
ideal level, with bipolar zero error adjusted to zero. Full scale
error is defined as either oositive full scale error or neo:ative full
~
scale error, whichever is iargest.
AD7772
CIRCUIT INFORMATION
CONVERTER DETAILS
Conversion start on the AD7772 is controlled by the CS and
CONVST inputs. Figure 5 shows the operating signals of interest.
With CS held permanently low, a positive-going edge on CONVST
starts the conversion cycle. The successive approximation register
(SAR) is reset at this stage. On the next rising edge of SCLK,
the SYNC output goes low and the three-state data output (SDO)
is enabled.
During conversion, the internal 12-bit DAC is sequenced by the
SAR from the most significant bit (MSB) to the least significant
bit (LSB). Bit decisions are made by the comparator (zero crossing
detector) which checks the addition of each successive weighted
bit from the DAC output against the analog input. The MSB
decision is made and latched to the serial data output 90ns
(typically) after the second rising edge of SCLK following the
conversion start. Similarly, the succeeding bit decisions are
made and latched approximately 90ns after the SCLK rising
edges. When conversion is complete, the SDO output is latched
to the high impedance state and the SYNC output goes high.
SCLK
CONVST
~1Ul-fl,
/1
L..J , 13 CLOC~ CYCLES
,
,.
I
SYNC
SOO
HIGH·Z
J~
I
:,
,~
.... . .90ns TVP
\
li>B'fi)f)iUC~ HIGH-Z
Figure 5. Operating Waveforms Using an External Clock
Source for CLKIN
CONTROL INPUTS SYNCHRONIZATION
Conversion time for the AD7772 is defined as the time for which
the SYNC output is low. This is always 13 clock cycles. However,
there is a delay between CONVST going high and SYNC going
low. Without synchronization this delay can vary from zero to
an entire clock period. If a constant delay is required here, then
the following approach can be used: when starting a conversion
CONVST must go high on either the rising edge of CLKIN or
the falling edge of CLKOSC.
DRIVING THE ANALOG INPUT
Figure 6 shows the analog input stage for the AD7772. There
are four application resistors (RA, RB , Rc and R D). These can
be used with one external op amp to implement ± 5V and ± lOY
analog input ranges. RA is always connected to VREF for these
ranges and offsets the input signal by + 2. 5V. Rc and RD provide
an attenuation of 2 for the ± 5V input while R B , Rc and RD
attenuate the ± 10V input by 4. The external op amp is connected
as an inverting amplifier with its output driving Pins I and 2
and RD as the feedback resistor. Figure 13 shows the circuit
configuration.
The + 5V and + lOY inputs on the AD7772 connect to the
comparator input via the 5kO resistors RE and R F • The DAC
which has 2.5kO output impedance also connects to this point.
During conversion, current from the analog input is modulated
by the DAC output current at a rate equal to the CLKIN frequency
(1.28MHz maxinmm). This causes voltage spikes (glitches) to
appear at the analog input. The magnimde and settling tinle of
these glitches depends on the open-loop output impedance and
small signal bandwidth of the amplifier or sample-and-hold
driving the input. These devices must have sufficient drive to
ensure that the glitches have settled within one clock period. An
example of a suitable op amp is the AD OP-27. The magnitude
of the largest glitch when using this device to drive the analog
input is typically 11mV with a 200ns settling time.
Suitable devices capable of driving the AD7772 analog inputs
are the AD OP-27 and AD711 op amps and the AD585 sample-andhold .
INTERNAL CLOCK OSCILLATOR
Figure 7 shows the AD7772 internal clock circuit. A crystal or
ceramic resonator may be connected as in Figure 7 to provide a
clock oscillator for the ADC timing. Resistors R 1 and R2 ensure
that the CLKIN marklspace ratio stays between 45/55 and 55/45.
Alternatively, the crystal/resonator may be omitted and an external
clock source connected to CLKIN. The mark/space ratio of the
external clock must be in the range 45/55 to 55/45. An inverted
CLKIN signal will appear at the CLKOSC output pin.
A07772
CLOCK
BOFS
:!:1DV
~5V
SUM
+10V
NOTES
·'.28MHz CRYSTAUCERAMIC RESONATOR.
"'e, AND C2 CAPACITANCE VALUES DEPEND ON CRYSTAUCERAMIC RESONATOR
MANUFACTURER. TYPICAL VALUES ARE FROM 3DpF TO 10DpF.
Figure 7. AD7772 Internal Clock Circuit
Figure 6. AD7772 Analog Input Stage
ANALOG-TO-DIGITAL CONVERTERS 3-347
II
INTERNAL REFERENCE
The AD7772 has an on-chip, buffered, temperature compensated,
buried Zener reference, which is factory trimmed to - 5.25V
± 1%. It is internally connected to the DAC and is also available
at Pin 3 to sink up to 550....A current from an external load.
For minimum code transition noise, the reference output should
be decoupled with a capacitor to filter out wideband noise from
the reference diode (lO .... F tantalum in parallel with 100nF
ceramic). However, large values of decoupling capacitors can
affect the dynamic response and stability ofthe reference amplifier.
A Ion resistor in series with the decoupling capacitors will
eliminate this problem without adversely affecting the filtering
effect of the capacitors. A simplified schematic of the reference
with its recommended decoupling components is shown in
Figure 8.
OUTPUT CODE
(STRAIGHT BINARY)
FULL SCALE
TRANSITION
11 ... 111!
11 ... 110
11 ... 101
I
I
011~/
,
>-
,,"""
FS = 5V
lLSB =
4~~
00.
00 .. 010
00 . . 001
00.
--------+-+-f--
000
o
1
2 3
LSB LSBs LSBs
FS
FS -lLSB
AIN. INPUT VOLTAGE (IN TERMS OF LSBs)
Figure 10. Ideal Input/Output Transfer Characteristic for
Figure 9
Figure 8. AD7772 Internal -5.25V Reference
Figure 11 shows how the AD7772 can be connected for a 0 to
+ IOV input range. The + 5V pin is now connected to OV,
thereby attenuating the input by 2 and effectively doubling the
analog input range. The analog input is applied to the + IOV
pin. For this circuit, the LSB size is FS/4096 = 'l0/4096V =
2.44mV and the coding is straight binary.
APPLYING THE AD7772
The AD7772 has a flexible input stage with application resistors
which can be configured for various analog input ranges. The
following sections show the AD7772 configured for these
ranges.
UNIPOLAR OPERATION
Figure 9 shows the AD7772 connected for the unipolar 0 to
+ 5V input range. The ideal input/output characteristic for this
range is given in Figure 10. The designed code transitions occur
midway between successive integer LSB values (i.e., 1I2LSB,
3/2LSBs, 5/2LSBs ... FS - 3/2LSBs). The output code is straight
binary (see Table I) with an LSB size of FS/4096 = 5/4096V =
1.22mV. To change to complementary binary coding, NORlCMP
should be tied to + 5V.
AD777Z*
o TO
+10V
ANALOG o---+--{
INPUT
NOTE
• ADDITIONAL PINS OMITTED FOR CLARITV
Figure 11. AD7772 in 0 to + 10V Analog Input Range
AD777Z*
°A1'lL~ o--.....-{
INPUT
NOTE
"ADDITIONAL PINS oMmED FOR CLARITY
Figure 9. Unipolar 0 to + 5V Input Range
~348
ANALOG-TO-DIGITAL CONVERTERS
UNIPOLAR OFFSET AND FULL SCALE· ERROR
ADJUSTMENT
If absolute accuracy is an application requirement, then offset
and full scale error can be adjusted to zero. Offset error must be
adjusted before full scale error. Figure 12 shows the extra components required for full scale error adjustment. The analog
input range is 0 to + 5V and the coding is straight binary. Zero
offset is achieved by adjusting the offset of the op amp driving
the analog input (i.e., Al in Figure 12). For zero offset error
apply 0.61mV (+ 1I2LSB) to VIN and adjust the op amp offset
voltage until the ADC output code flickers between 0000 ...
0000 and 000 ... 0001.
To adjust the full scale error, apply an analog input of 4.998l7V
(FS - 3/2LSBs) to VIN and adjust RI until the ADC output
code flickers between 1111 . . . III 0 and 1111 . . . 1111.
AD7772
OUTPUT CODE
iOFFSET BINARY)
o TO
+ 5V
ANALOG
INPUT
111
.111
111
110
100
010
100.
001
100
. 000
011
111
011
.. 110
000 .. 001
000 . .000
NOTE
*ADDITIONAl PINS OMITTED FOR CLARITY
...
,,
+FS
,
.r
'
r
~~'LSB=~
I
flit
FS
= 10V
OV
V 1N• INPUT VOLTAGE - IN TERMS OF LSBs
Figure 12. Unipolar 0 to +5V Operation with Full-Scale
Error Adjust
Figure 14. Ideal Input/Output Transfer Characteristic for
the Bipolar Circuit of Figure 13
BIPOLAR OPERATION
Figure 13 shows the circuit configuration for implementing
± 5V and ± IOV analog input voltages on the AD7772. RA and
RD offset the input signal by a constant + 2.5V while Rc and
RD provide attenuation for the ± 5V input. R B , Rc and RD
provide attenuation for the ± 10V input. If a ± 5V input range
is needed, the input signal should be applied to Pin 6 (± 5V)
and Pin 7 left unconnected. For a ± 10V input range, apply the
signal to Pin 7 (± 10V) and leave Pin 6 open circuit. The output
code format is offset binary. Figure 14 shows the ideal input/output
characteristic for the ± 5V input range.
BIPOLAR OFFSET AND FULL SCALE ERROR
ADJUSTMENT
In measurement applications where absolute accuracy is required,
offset and full scale error can be adjusted to zero. Figure IS
shows how the ± 5V input range circuit is modified to do this.
By placing R3 in parallel with the op amp feedback resistance
RD and the RI, R2 combination in parallel with R c , an adjustment
range of ± 16LSBs is possible.
Bipolar zero error must be adjusted before full scale error. This
is achieved by applying an analog input of + 1.22mV (+ 1I2LSB)
at the ± 5V input pin and adjusting the op amp offset until the
ADC output code flickers between 1000 . . . 0000 and 1000 ..
0001.
For full scale error adjustment, the analog input must be at
4.99878 volts (i.e., FS/2 - 1/2LSB or last transition point).
Then RI is adjusted until the output code flickers between
1111 ... 1110 and 1111 ... 1111.
NOTE
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. AD7772 Connected for ±5V/± 10V Input Range
NOTE
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. AD7772 Connected for ±5V Input Range with
Full-Scale Error Adjust
ANALOG-TO-DIGITAL CONVERTERS 3-349
•
INTERFACING
TheAD7772 is a serial output device, making it suitable for use
with digital signal processors which have a serial port (TMS32020,
DSP56000, e~c.) as well as microcontrollers (8051, 6803) and
shift registers. See Figure 4 for the timing diagram. The serial
data is placed on the SDO pin as conversion is taking place.
Each data bit is valid on the falling edge of SCLK, and the
complete word is framed by the SYNC pulse.
TMS32020ITMS320C25 INTERFACE
Figure 16 shows the circuit for interfacing the AD7772 to the
TMS32020ffMS320C25 Serial Port. The AD7772 has CS tied
permanently low. In a sampling system, the SAMPLE TIMER
would control the start of conversion. When the system is nonsampling, this CONVST pulse could be software-controlled by
the processor. When conversion begins, the SYNC output goes
low. This enables the serial input of the TMS32020ffMS32OC25
which now accepts the data appearing at DR on each negative-going
edge of CLKR. After sixteen CLKR pulses the internal interrupt
(RINT) is automatically set. The service routine for this interrupt
then reads the conversion result from the DRR (data receive
register) into the accumulator or memory. Note that the word in
the DRR must be shifted right three times in order to get the
ADDRESS BUS
~
Data bits are shifted into the ,...PD7720 on the rising edge of
SCK when SIEN is asserted. This means that SCLK from the
AD7772 must be inverted before connecting to the SCK input.
The internal shift register converts the serial data to parallel and
transfers it to the SI register when 16 bits have been received.
The internal acknowledge flag, SlACK, is also set at this time.
When the parallel data is read from the SI register, this SlACK
flag is reset. It is important to read the data from the SI register
before the next conversion is complete and the data bits transferred;
otherwise the original data will be lost.
When interfacing to the ,...PD77230, the inverter for SCLK
shown in Figure 17 is not needed, since data on SI is synchronized
with the falling edge of SICK (the serial input clock). Thus,
SCLK from the AD7772 is connected directly to SICK on the
....PD77230. All other connections are as in Figure 17.
CLOCK
"P077Z0
seKI-------O< f - - - + - - - - i
Sll-----------+--....,
SIENi-----..-C{
I J
A0777Z*
SAMPLE
TIMER
L
TMS3Z020
TMS3Z0C25
~
CONVST
co
elKIN
seLK
CLKR
DR
SOD
FSR
SYNC
-LINEAR CIRCUITRY OMITTED FOR CLARITY
AD7772*
-LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 16. A07772 to TMS32020ITMS320C25 Interface
standard right-justified data format. This is also the case in the
other processor interfaces which follow.
NEC ILPD7720/ILPD77230 INTERFACE
Figure 17 shows an interface circuit for the NEC ....PD7720
digital signal processor. Unlike the FSR input on the TMS320
processors, the SIEN input on the ....PD7720/ ....PD77230 is level
sensitive rather than edge sensitive. Because the processor can
only be configured for either 8-bit or 16-bit data transfers, the
SIEN input to the ....PD7720/ ....PD77230 must be at least 16
clock pulses wide to receive the 12-bit conversion result from
the AD7772. The circuitry of Figure 17 accomplishes this by
using the CONVST and SYNC signals as the set and reset
controls on an S-R flip-flop.
In Figure 17 the processor controls the start of conversion. CS
is tied low, and the output of the address decoder drives .
CONVST.
Figure 17. AD7772 to NEC f,LPD7720 Interface
DSP56000 INTERFACE
The DSP56000 has a very versatile serial interface which can be
configured to suit various applications. Figure 18 shows an
interface circuit for the AD7772 to DSP56000. The DSP56000
is configured for normal mode, asynchronous operation. This
means that the DSP56000 serial transmitter and receiver have
their own separate clock and synchronization siguals. The processor is set up for 16-bit word and continuous clock with SCO
and SCI configured as inputs. The FSL control bit, which
selects the type of frame synchronization to be recognized,
should be set to O. All of these conditions are programmable in
the DSP56000.
ADDRESSIBUS
OSP56000
A0777Z
seo~------------~
~Dt-------------~SDO
se.
Figure 18. AD7772 to DSP56000 Interface
3-350 ANALOG-TO-DIGITAL CONVERTERS
AD7772
When the receiver is enabled, a 16-bit data word will be clocked
in each time the frame synchronization signal is detected. Once
received, the data word will be transferred from the SSI receive
shift register to the receive data register (RX). The RDF flag
(receive data register full flag) will be set to indicate that the
receiver is full and the receive interrupt will occur if it has been
enabled. The DSP program should read the data from RX
before a new data word is transferred from the receive shift
register, otherwise the receive overrun error (ROE) will be set.
AD7772 IN REMOTE CONTROL APPLICATIONS
Figure 19 shows a serial interface between the AD7772 and a
remote controller. The digital signals are transmitted differentially
along twisted pairs while optocouplers sense the signals at the
receiving end. The DS8830 is a dual differential line driver,
designed to drive long lengths of coaxial cable, strip line or
twisted pair transmission lines. The optocouplers used are HCPL2601s, which have sufficient speed (lOOOV/j.C.s slew rate) to handle
the maximum data transfer rate of 1.28M bits/sec.
The AD7772 is set up so that only one signal (CONVST) is
needed to start conversion. Three twisted pairs are needed to
transfer the data back to the controller. These take the SCLK,
SDO and SYNC signals.
+5V
2.2kll
CONV5T 1----~4--.
2
56011
3911
3911
SCLK/-_ _ _~
+5V
2
4
AD7772*
058830
10
"
12
SDO / -_ _-=.:13'-1
SYNC/----'-i
1'2
DS8830
+5V
4
• ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Using Optocouplers with the AD7772
ANALOG-TO-DIGITAL CONVERTERS 3-351
II
AD7772 - AD585 SAMPLE-HOLD INTERFACE
Figure 20 shows a typical sampling applicl!.tion for the AD7772
with an AD585 sample-and-hold amplifier driving the ADC
analog input . .The AD585 is configured as a unity gain buffer.
The :!: lOY input signal is successively sampled and held and
this signal is then fed to Pin 7 of the AD7772 which is connected
for an analog input range of :!: IOV.
For the circuit of Figure 20 to function properly, it is necessary
to have the CONVSTsignal for the ADC synchronized with
CLKIN as discussed previously. This ensures that the analog
input is always held at a fixed point in time after the CONVST
signal goes high and equal interval sampling is achieved. Without
this synchronization, the holding point would not be exactly
defined and the data acquisition system performance would
suffer accordingly.
The maximum throughput rate of the system shown in Figure
20 is 76kHz. lOllS is required for conversion while a further 311S
must be allowed for the AD585 to acquire the signal. This
yields a total time of 13I1S. Thus, the maximum sampling rate is
76kHz and the analog input bandwidth is 38kHz.
+15V
+5V
APPLICATION HINTS
Good printed circuit board (PCB) layout is as important as the
circuit design itself in achieving high speed AID performance.
The AD7772's comparator is required. to make bit decisions on
an LSB size of 1.22mV. To achieve this, the designer has to be
conscious of noise both in the ADC itself and the preceding
analog circuitry. Switching mode power supplies are not recommended as the switching spikes will feed through to the comparator
causing noisy code transitions. Other causes of concern are
ground loops and digital feedthrough from microprocessors.
These are factors which influence any ADC, and a proper PCB
layout which minimizes these effects is essential for best
performance.
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the
digital and analog signal lines separated as much as possible.
Take care not to run any digital track alongside an analog signal
track. Guard (screen) the analog input with AGND.
Establish a single point analog ground (star ground) separate
from t...lte logic system groll...-td at Pin 4 (AGND) or as close as
possible to the AD7772 as shown in Figure 21. Connect all
other grounds and Pin 10 (AD7772 DGND) to this single analog
ground point. Do not connect any other digital grounds to this
analog ground point. Low impedance analog and digital power
supply common returns are essential to low noise operation of
the ADC so make the foil width for these tracks as wide as
possible. The use of ground planes minimizes imPedance paths
while guarding the analog circuitry from digital noise. The
circuit layout of Figures 24 and 25 have both analog and digital
ground planes which are kept separate and only joined together
at the AD7772 AGND pin.
NOISE: Keep the input signal leads to the analog input and
signal return leads from AGND (Pin 4) as short as possible to
minimize input noise coupling. In applications where this is not
possible use a shielded cable between the source and the ADC.
Reduce the ground circuit impedance as much as possible, since
any potential difference in grounds between the signal source
and the ADC appears as an error voltage in series with the
input signal.
ANALOG
INPUT
-10V
TO
+10V
NOTE
• ADDITIONAL PINS OMITTED FOR CLARITV
Figure 20. AD7772 Sample-and-Hold Interface
ANALOG
SUPPLY
+15V GND
-15V
Figure 21. Power Supply Grounding Practice
3-352 ANALOG-TO-DIGITAL CONVERTERS
AD7772
J1
+15V
r--~'-""-------=:--::C::'5:---1r+",5.,V
C311A31
O.1 .... F
r---+---iq
C13fA13
C14/A14
IC2
AD585
C15JA1S
C161A16
-Vs
e11/A11
GND
6
C3
I
C4
22fl~O.1 .... F
T
\J
-15V
4l---..-------"t"---i
C3.fA30
~W"'-+-""""""'----,,~--I C32fA32
·C16. C17 VALUES DEPEND ON
CRYSTAL MANUFACTURER.
VALUES TYPICALLY RANGE
FROM 30pF TO 100pF
Figure 22. Schematic for AD7772 Board
PRINTED CIRCUIT BOARD LAYOUT
Figure 22 is a circuit diagram showing the AD7772 being used
to digitize an analog signal. The circuit board contains the ADC,
sample-and-hold and extra op amp necessary to sample a bipolar
input signal. Links LI and L2 allow the user to choose a ± 5V
or ± lOY analog input range. With LI inserted the range will
be ± IOV, and with L2 inserted it will be ± SV.
The AD58S is the input sample-and-hold. Its HOLD input is
driven from IC4 (112 7474 D-type flip-flop). The input signal is
sampled at the end of conversion, when SYNC goes high and is
held when the CONVST signal goes low. To make sure that the
sample-and-hold has enough time to acquire the input signal,
the time from sample-and-hold should be at least 3,...s. Links
L3, L4, L5 and L6 allow the user to choose the output code
format for the device. See Table I for the output code truth
table.
The PCB layout is designed so that all external connections
except the VDO and V55 power supplies can be made in any of
three ways:
1. 32-way single-sided edge connector.
2. Eurocard connector, 11.
3. 26-pin plug, 12.
The pinout for the 26-way connector is shown in Figure 23, and
the other pinouts are shown in Figure 22. The Voo and Vss
power supplies are connected at the top of the board (see Figure
26).
,... ,...
,... ;:
;::
,..,.
0
0
0
0
0
GND
+5V
ClKIN
SDO
SYNC
CONVST
CS
SClK
0
0
0
0
0
J2: 26-WAY IDC PLUG
Figure 23. J2 Pin Configuration
The printed circuit board layout is shown in Figure 24 and 25.
Figure 24 is the component side layout and Figure 25 is the
solder side layout. The component overlay is shown in Figure
26. In the layout, the STAR ground point is located at Pin 4
(AGND). Pin 10 (DGND), the ADS85 ground, AD711 ground
and the ground plane are connected directly to this point.
To ensure optimum performance, the AD7772 power supplies
are decoupled as shown. The VREF pin is decoupled with RI,
C5 and C6. All ADC decoupling capacitors are placed as close
as possible to the device.
ANALOG-TO-DIGITAL CONVERTERS 3-353
•
0000000000000
00
00
0000000
0000000
0000000
0000000
0000000000
0000000000
0000000000
0000000000
0000000000
0000000000
0000000000
00000000000
00000000000
00000000000
I~.;~;:;~,..t
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
.000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
000000000000000000000000000000000
:'==:1
Figure 24. PCB Component Side Layout for Figure 22
3-354 ANALOG-TO-DIGITAL CONVERTERS
AD7772
•
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••••
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•••••••••
•••••••••••
•••••••••••
•••••••••••
•••••••••••
...........
•••••••••••
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•••••••••
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•••••••••
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••••••••••
••••••••••
••••••••••
•••••••••••1.,••,.
.........
•••••••••
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•••••••••
•••••••••
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••••••••••
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••••••••••
'.,
••••••••••
••••••••••••••
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•••••••••••••
•••••••••••
•••••••••••
•• •••••••••••
•••••••••••
'............ .
•••••••••••••
•••••••••••
••••••••••••••
•••••••••••
••••••••••••
••••••••••
••••••••••
••••••••••••
••••••••••
•••••••••••
.".,..
............ ..'.
...........
Figure 25. PCB Solder Side Layout for Figure 22
ANALOG- TO-DIGITAL CONVERTERS 3-355
~_I
______________________~
~
+
Q
Z
~
Figure 26. Component Overlay for Circuit of Figure 22
3-356 ANALOG-TO-DIGITAL CONVERTERS
IIIIIIIIIII ANALOG
WDEVICES
LC 2 MOS High Speed J.tP-Compatible
8-Bit ADC with Track/Hold Function
AD7820 I
FEATURES
Fast Conversion Time: 1.36jJ.s max
Built-In Track-and-Hold Function
No Missed Codes
No User Trims Required
Single + 5V Supply
Ratiometric Operation
No External Clock
Skinny 20-Pin DIP and 20-Terminal
Surface Mount Packages
AD7820 FUNCTIONAL BLOCK DIAGRAM
DBD-DB7
DATA OUT
PINS2-5. '4-17
GND
MODE WRIRDY
CS
AD
iNi'
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7820 is a high speed, microprocessor-compatible 8-bit
analog-to-digital converter which uses a half-flash conversion
technique to achieve a conversion time of 1.3611-s. The converter
has a OV to + 5V analog input voltage range with a single + 5V
supply.
1. Fast Conversion Time
The half-flash conversion technique, coupled with fabrication
on Analog Devices' LC2MOS process, enables very fast conversion times. The maximum conversion time for the WR-RD
mode is 1.3611-s, with 1.611-s the maximum for the RD mode.
The half-flash technique consists of 31 comparators, a most
significant 4-bit ADC and a least significant 4-bit ADC. The
input to the AD7820 is tracked and held by the input sampling
circuitry, eliminating the need for an external sample-and-hold
for signals with slew rates less than 100mV/lI-s.
2. Total Unadjusted Error
The AD7820 features an excellent total unadjusted error
figure of less than 1I2LSB over the full operating temperature
range. The part is also guaranteed to have no missing codes
over the entire temperature range.
The part is designed for ease of microprocessor interface with
the AD7820 appearing as a memory location or 110 port without
the need for external interfacing logic. All digital outputs use
latched, three-state output buffer circuitry to allow direct connection to a microprocessor data bus or system input port. A
non-three state overflow output is also provided to allow cascading
of devices to give higher resolution.
3. Built-In Track-and-Hold
The analog input circuitry uses sampled-data comparators,
which by nature have a built-in track-and-hold function. As
a result, input signals with slew rates up to lOOmV/lI-s can be
converted to 8-bits without external sample-and-hold. This
corresponds to a 5V peak-to-peak, 7kHz sine-wave signal.
The AD7820 is fabricated in an advanced, all ion-implanted,
high speed, Linear Compatible CMOS (LC2MOS) process and
features a low maximum power dissipation of 75mW. It is available
in both O.3"-wide, 20-pin DIPs and in 20-terminal surface mount
packages.
4. Single Supply
Operation from a single + 5V supply with a positive voltage
reference allows oPeration of the AD7820 in microprocessor
systems without any additional power supplies.
ANALOG-TO-DIGITAL CONVERTERS 3-357
II
SPECIFICATIONS
=
=
(Villi +5Y; YREF ( + ) + 5Y; YREF ( - ) = GNO = OY unless oIherwise sIat8d).
All specifications T... to T_ unless oIheJwise specified. Specifications apply for RO Mode (Pin 7 oy)
Parameter
KVersi!>a'
LVersi!>a
ACCURACY
Resolution
ToW Unadjusted Error'
MiDimum ResoIutionfor wbich
No MiasiDs Codes"", guarmteed
:tl
:t 112
=
B, T Versions
C,UVemons
Units
Bits
:tl
:t 112
LSBmax
Bits
8
RBFERENCEINPUT
InputResisraace
VREF( + ) Input Voltage RaDge
V""" ( - ) Input Voltage RaDge
1.0/4.0
VREF( - )/Voo
GNDIVREF ( +)
1.014.0
VR1!F( - )/Voo
GNDIVRBF ( + )
1.014.0
VREF( - )/Voo
GNDlVREF( +)
1.014.0
V"""( - )/Voo
GNDIVREF( +)
k!l111iDlkfimax
VmiDlVmax
V miDIV mu
ANALOG INPUT
Input Voltage RaDge
Input Leakage Current
Input Capocitan<:e'
VRBFC - )/VRBFC + )
:t3
45
VRBFC - )/VRBFC + )
:t3
45
VRBFC - )/VRBFC + )
.,3
45
VRBFC - )/VRE,,( + )
:t3
45
V miDIV max
,.A max
pFtyp
LOGIC INPUTS
CS,WR,RD
VlNH
VINL _ _
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
I
I
I
I
Vmia
Vmu
,.A-
-I
-I
-I
-I
IlNH~RD)
!ift"ii(WR)
IlNL
Input Capocill1l1Ce'
MODB
VlNH
VlNL
IlNH
IlNL
Input Capociraace'
8
8
8
8
3.5
1.5
200
3.5
1.5
200
3.5
1.5
200
3.5
1.5
200
-I
-I
-I
-I
8
8
8
LOGIC OUTPUTS
DJIO.DB7,OFL,INT
VOH
VOL
Iotrr (DIlG-DB7)
Output Capocill1l1Ce'
RDY
VOL
4.0
0.4
:t3
8
4.0
0.4
:t3
8
0.4
:t3
8
0.2
0.1
Iotrr
OulpUtCapacill1l1Ce'
SI.J!WRATB, TRACKING'
POW1!llSUPPLY
Von
IDo"
Power Dissipation
Power Supply Sensitivity
ConditiDDSICommeats
IS
,.A max
pFIIUIlt
TypicaUy 5pF
50,.A typ
8
Vmia
V_
,.Amax
,.A1IUIlt
pFmu
4.0
0.4
:t3
8
4.0
0.4
:t3
8
Vmia
Vmu
,.Amu
pFmu
lSOVRCI! = 36O,.A
ISlNK= 1.6mA
F10atiaa State Leakage
TypicaUy 5pF
0.4
:t3
8
0.4
:t3
8
0.4
:t3
8
Vmu:
,.Amu
pFmu
ISINK =
0.2
0.1
0.2
0.1
0.2
0.1
V/.... typ
V/.... mu
S'
40
:t1l4
I
,
PLCC
g
> !;!
m~ J
Q
Q
J
2.
3
2
2.
,.
..,
DB3 5
WRiRDV 6
MODE 7
'
18 OFl
17 DB7 (MSB)
AD7820
TOP VIEW
(Not to Scalel
ROB
.
16 DB6
AD7820
15 DBS
TOP VIEW
(Not to Scale)
14 DB4
liD
• , " '2
I! z .!. :!: Ilj
'" J J
•
14 OB4
• ,. "
z :!:
'3
Q
Ne
I!
=NO CONNECT
Ne = NO CONNECT
ORDERING INFORMATION1 ,
Total
Unadjusted
Error
Q
2
Plastic DIP (N.20)
Hermetic (Q.20)
Hermetic (Q·20)
±ILSB
±1I2LSB
AD7820KN
AD7820LN
PLCC s (P·20A)
AD7820BQ
AD7820CQ
AD7820TQ
AD7820UQ
±ILSB
±1I2LSB
AD7820KP
AD7820LP
LCCC6 (E.20A)
AD7820TE
AD7820UE
NOTE
ITo order MIL-STD-883, Class B processed parts, addl883B to part number.
Contact your local sales office for military data sheet. For U.S. Standard
Military Drawing (SMD), see DESC drawing #5962-88650.
2 Analog Devices reserves the right to ship ceramic packages (package outline D-20)
in lieu of cerdip packages (package outline Q-20).
'See Section 14 forpackagc outline information.
4 Also available in SOIC packages (AD7820KR, AD7820LR).
5PLCC: Plastic Leaded Chip Carrier.
"LCCC: Leadless Ceramic Chip Carrier.
'2
'3
:!: Ilj
'" J >~
Temperature Range and Package Options3 , 4
- 25°C to + 85°C
- 55°C to + 125°C
Oto +70OC
3-360 ANALOG-TO-DIGITAL CONVERTERS
CJ
Z
,.
0
,,
0824
,
Typical Performance Characteristics - AD7820
12
2.0
11
,
~
~
ffi
1.5
"E,
~
z
\
i
::>
1.5
~
z
1.0
",
~,
j
j
tRl)=600ns
\
t
0
~:;::~~s
\
10
~
>
I
VOD=5V
V R £F=5V
0.5
o
r A - AMBIENT TEMPERATURE- QC
-50
50
TA - AMBIENT TEMPERATURE_
..,
~
0
ffi
1.0
~
100
2.0
\
\
;
::;
0.5
o
200
1.5
f--
~,
..ffi.
.
tw..=&oOns
\
\\
0
'"
300
...
1.0
~
Ii!
~
~
0.5
..........
...
500
700
V"Ef: 5V
'DO
1.5
~
400
500
600
o
800
900
I
VDD =5V
T .. =25<><:
o
Accuracy vs. tp
-3.
Accuracy vs VREF
(VREF = VRErl+) - VREF (-)]
2.0,---,.---,---,.----,---,
-3.
10
Vco=5V
~
~
J
1/
-42
-44
i"
~
or-.-
-
'SINK.
r--- t--
VDUT=O~
t--
j
-52
1
~:::'OUT=2.4V
~ 0.5
~i'
-50
f----+---+--+---+---j
51
~
~
-48
;:: 1.5
1.01---+---+----!..sOS""'I----j
/
-48
700
tp-ns
Accuracy vs. tRD
-40
...
1\
0.5
700
500
\
1.0
o
800
t---
...
\
VDDL
1,,=25"C
t_=600ns
t.to=60Ons
'00
..........
Accuracy vs. tWR
2.0
VDJv
VR£F=5V
T.=25"C
tp=500ns
200
150
r-...
-
2345710
20 30 40 50 70 100
INPUT FREQUENCY - kHz
ENCODE RATE ::: 400kHz
INPUT SIGNAL 5V p.p
MEA5UREMENTBANDWIDTH 80kHz
=
~,~00~---~50~-~~-~50~-~,~DO~-~,50
TA - AMBIENT TEMPERATURE- "e
o
-100
-50
50
lDO
150
Til. - AMBIENT TEMPERATURE- "c
=
Signal-Noise Ratio vs. Input Frequency
t,NTL, Internal Time Delay vs.
Temperature
Output Current vs. Temperature
ANALOG-TO-DIGITAL CONVERTERS 3-361
II
PIN FUNCTION DESCRIPTION
CIRCUIT INFORMATION
.BASIC DESCRIPTION
PIN
The AD7820 uses a half-flash conversion technique whereby
two 4-bit flash AID converters are used to achieve an 8-bit
result. Each 4-bit flash ADC contains 15 comparators which
compare the unknown input to a reference ladder to get a 4-bit
result. For a full 8-bit reading to be realized, the upper 4-bit
flash, the most significant (MS) flash, performs a conversion to
Pf?vide the 4 most significant data bits. An internal DAC,
driven by the 4 MSBs, then recreates an analog approximation
of the input voltage. This analog result is subtracted from the
input, and the difference is converted by the lower flash ADC,
the least significant (LS) flash, to provide the 4 least significant
bits of the output data. The MS flash ADC also has one additional
comparator to detect input overrange.
MNEMONIC DESCRIPTION
VIN
Analog Input. Range: V~ - ) to
V~+).
2
DBO
3
4
5
6
DBI
DB2
DB3
WRlRDY
7
Mode
8
RD
9
INT
10
GND
11
V~-)
12
V~+)
13
CS
14
15
16
17
DB4
DB5
DB6
DB7
18
OFL
19
20
~362
NC
Voo
Data Output. Three State Output, bit 0
(LSB)
Data Output. Thiee State Output, bit 1
Data Output. Three State Output, bit 2
Data Output. Three State Output, bit 3
WRITE control inputIREADY status
output. See Digital Interface section.
Mode Selection Input. It determines
whether the device operates in the WR-RD
or RD mode. It is internally tied to
GND through a 50 ....A current source.
See Digital Interface section.
READ Input. RD must be low to access
data from the part. See Digital Interface
section.
INTERRUPT Output. INT going low
indicates that the conversion is complete.
INT returns high on the rising edge
ofRD or CS. See Digital Interface section.
Ground
Lower limit of reference span.
Range: GNDsV~ - )SV~ +)
Upper limit of reference span.
Range: VREP( -)s VREP( + )sVoo
Chip Select Input. CS, the decoded
device address, must be low for
RD or WR to be recognized by the
converter.
Data Output. Three State Output, bit 4
Data Output. Three State Output, bit 5
Data Output. Three State Output, bit 6
Data Output. Three State Output, bit 7
(MSB)
Overflow Output. If the analog input is
higherthan(V~ +) -1t2LSB),OFL
will be low at the end of conversion. It
is a non three state output which
can be used to cascade 2 or more
devices to increase resolution.
No connection.
Power supply voltage, + 5V
ANALOG-TO-DIGITAL CONVERTERS
OPERATING SEQUENCE
The operating sequence for the AD7820 in the WR-RD mode is
shown in Figure 3.~set-up time of 500ns is required prior to
the falling edge of WR. (This 500ns is required between reading
data from the AD7820 and starting another conversion). When
WR is low the input comparators track the analog input signal,
VIN. On the rising edge of WR, the input signal is sampled and
the result for the four most significant bits is latched. INT goes
low approximately 700ns after the rising edge of WR. This
indicates that conversion is complete and the data result is already
in the output latch. RD going low then accesses the output
data. If a faster conversion time is required, the RD line can be
brought low 600ns after WR goes high. This latches the lower 4
bits of data and accesses the output data on DBO-DB7.
L
I
Wii
T
:~~:I~~E~=UIRED
I
~ ~~~:JEO:I~~~J,E:PLETE
1'1---
AND THAT THE DATA RESULT IS
ALREADY IN THE OUTPUT
-
x;:~r:.~g.s
-:
COMPARA"'RSPRIOR.TO
/
DOCISIONIS LATeIIOD
STARTING CONVERSION
V'NISTRACKEO
INT
\
\
\
BVINTERNAl
COMPARATORS
iii) 8ROUGHT LOW HERE LATCHES
THE 4 lSBS INTO OUTPUT LATCH
AND ACCESSES DATA ON DBo-DB7
Figure 3. Operating Sequence (WR-RD Mode)
AD7820
DIGITAL INTERFACE
The AD7820 has two basic interface modes which are determined
by the status of the MODE pin. When this pin is low the convener
is in the RD mode, with this pin high the AD7820 is set up for
the WR-RD mode.
RDMode
The timing diagram for the RD mode is shown in Figure 4. In
the RD mode configuration, conversion is initiated by taking
RD low. The RD line is then kept low until output data appears.
It is very useful with microprocessors which can be forced into
a WAIT state, with the microprocessor staning a conversion,
waiting, and then reading data with a single READ instruction.
In this mode, pin 6 of the AD7820 is configured as a status
output, RDY. This RDY output can be used to drive the processor
READY or WAIT input. It is an open drain output (no internal
pull-up device) which goes low after the falling edge of es and
goes high impedance at the end of conversion. An INT line is
also provided which goes low at the completion of conversion.
INT returns high on the rising edge of es or RD.
\
In the first of these options the processor waits for the INT
status line to go low before reading the data (see Figure 5a).
INT typically goes low 700ns after the rising edge of WR. It
indicates that conversion is complete and that the data result is
in the output latch. With es low, the data outputs (DBO-DB7)
are activated when RD goes low. INT is reset by the rising edge
ofRD or es.
The alternative option can be used to shorten the conversion
time. To achieve this, the status of the INT line is ignored and
RD can be brought low 600ns after the rising edge of WR. In
this case RD going low transfers the data result into the output
latch and activates the data outputs (DBO-DB7). INT also goes
low on the falling edge of RD and is reset on the rising edge of
RD or es. The timing for this interface is shown in Figure 5b.
\~-----
Figure 5b. WR-RD Mode (tRDtINTL)
ANALOG-TO-DIGITAL CONVERTERS 3-363
II
APPLYING THE AD7820
REFERENCE AND INPUT
The two reference inputs on the AD7820 are fully differential
and define the zero to full-scale input range of the AID converter.
As a result, the span of the analog input can easily be varied
since this range is equivalent to the voltage difference between
VIN< +) and VIN< -). By reducing the reference span, VREP( +}V~ -), to less than SV the sensivity of the converter can be
increased (i.e., ifVREF =2V then ILSB = 7.8mV). The input/reference arrangement also facilitates ratiometric operation.
This reference flexibility also allows the input span to be offset
from zero. The voltage at V~ -) sets the input level which
produces a digital output of all zeroes. Therefore, although VIN
is not itself differential, it will have nearly differential-input
capability in most measurement applications because of the
reference design. Figure 7 shows some of the configurations that
are possible.
addition, about 12pF of input stray capacitance must be charged.
For large source resistances, the analog input can be modelled
as an RC network as shown in Figure 8b. As Rs increases, it
takes longer for the input capacitance to charge.
In the RD mode, the time for which the input comparators
track the analog input is 600ns at the start of conversion. In the
WR-RD mode the input comparators track VIN for the duration
of the WR pulse. Since other factors cause this time to be at
least 600ns, input time constants of lOOns can be accommodated
without special consideration. Typical total input capacitance
values of 4SpF allow Rs to be I.SkO without lengthening WR
to give VIN more time to settle.
~12PF
-"II\,.,... . . .
Rs
JCJ
1pF
•
~1PF
15LSBCOMPARA;~OS
;!;. GND
V
O'1~
TOLS
~
LADDER-o"{ C
v,NI+I-----I1 v,.
V1NI-)
RON
V'N-_ _....
_
AD7820
+sv-......- -.....- ....-i v••
VAEFI+I
RON
VREF(-)
TOMS
'LADDER-o"'J 0
Figure 7a. Power Supply as Reference
1pF
•
~ 1pF
16 MSB COMPARA:ORS
Figure 8a. AD7820 Equivalent Input Circuit
---11--1 GND
AD7820
+ 5 V - - . - -.....---~---~Voo
VIN
.~s..
_
CST
'---.---1
12PF'V
--.!~~~
32PF
T
'V
VAEFI-)
Figure 8b. RC Network Model
Figure 7b. External Reference 2.5V Full Scale
-----Iv,.
GND
AD7820
+sv--.--.....--.-----~voo
'--"VI/~.....- I VREFI+I
INPUT FILTERING
It should be made clear that transients on the analog input
signal, caused by charging current flowing into VIN will not
nonnally degrade the ADC's performance. In effect, the AD7820
does not "look" at the input when these transients occur. The
comparators' outputs are not latched while WR is low, so at
least 600ns will be provided to charge the ADC's input capacitance.
It is therefore not necessary to fIlter out these transients with an
external capacitor at the VIN terminal.
·CURRENT PATH MUST
STILLEXISHROM
v.. I-1 TO GROUND.
Figure 7c. Input Not Referenced to GND
INPUT CURRENT
Due to the novel conversion techniques employed by the AD7820,
the analog input behaves somewhat differently than in conventional
devices. The ADC's sampled-data comparators take varying
amounts of input current depending on which cycle the conversion
is in.
The equiValent input circuit· of the AD7820 is shown in Figure
8a. When a conversion starts (WR low, WR-RD mode), all
input switches close, and VIN is connected to the most significant
and least significant comparators. Therefore, VIN is connected
to thirty one IpF input capacitors at the same time.
The input capacitors must charge to the input voltage through
the on resistance of the analog switches (about 2kO to SkO). In
3-364 ANALOG-TO-DIGITAL CONVERTERS
nftmRENTSAMPL&HOLD
A major benefit of the AD7820's input structure is its ability to
measure a variety of high speed signals without the help of an
external sample-and-hold. In a conventional SAR type converter,
regardless of its speed, the input must remain stable to at least
Y2LSB throughout the conversion process if full accuracy is to
be maintained. Consequently, for many high speed signals, this
signal must be externally sampled and held stationary during
the conversion. The AD7820 input comparators, by nature of
their input switching inherently accomplish this sample-and-hold
function. Although the conversion time for the AD7820 is 1.36l1-s,
the time through which VIN must be Y2LSB stable is much
smaller. The AD7820 "samples" VIN only when WR is low.
The value of VIN approximately lOOns (internal propagation
delay) after the rising edge of WR is the measured value. This
value is then used in the least significant flash to generate the
lower 4-bits of data.
AD7820
Input signals with slew rates typically below 200mV/,..s can be
converted without error. However, because of the input time
constsnts, and charge injection through the opened comparator
input switches, faster signals may cause errors. Still, the AD7820's
loss in accuracy for a given increase in signal slope is far less
than what would be witnessed in a conventional successive
approximation device. A SAR type converter with a conversion
time as fast as 1,..s would still not be able to measure a 5V,
1kHz sine wave without the aid of an external sample-and-hold.
The AD7820 with no such help, can typically messure 5V,
10kHz waveforms.
Applications
OUTPUT
CODE
--_.--------I Voo
+5V-....
11111111
11111110
VRFF(+I
V ,N
V,N
RD
AD7820
f
11111101
I
MODE
DB7
GND
DBO
I
I
I
I
000000"
00000010
•
FULL SCALE
TRANSITION
iL'
,,
,,
/ '"
'LSB=~:6
'
0000000'
Figure 9a, 8-Bit Resolution
00000000
o, LSB 2LSB'S
I
-- ---3LSB'S
I
I"
\.. FS
AIN, INPUT VOLTAGE (IN TERMS OF LSB'SI FS -,LSB
Figure 9b. Nominal Transfer Characteristic for 8-Bit
Resolution Circuit
+5V
**
O.'~F 47~F L
V REF
Voo
MODE
AD7820
cs
cs
WR
I
Wi
..r-'L
iffi
~ 08
VREF(+I
V ,N
...
lkU~
iffi
V,N
DB7
V REF ( - )
DBO
GNO
OFL
/00,
-
-
07
SkU
cs
+ f = VDD
MODE
lkU
WR
iffi
-
OB7
t--
AD7820
VREFI+)
V,N
.t-'-'-'
GND
--
r-- >
Plastic DIP (N-20)
AD7821KN
0B6
TOP VIEW
(Not to Seele)
10 11 12 13
~ ~
DB7(MSB}
AD7821
16 DB6
14 DB4
10-
,
0
,
0B2 •
,.
iii
Q
,. . Ifl
J}
DB'
Typical Performance Curves - AD7821
9~~-_~--~-----r-----r----,
15
2.0
3
VoCJ-sv
1
~
~ 0 r--....
VDD
s.zL
=
§
~ 1.0
~
50
-50
100
-100
150
Conversion Time (RD Mode)
vs. Temperature
I
2.0
1.0
~
~
~
0.5
J5V - r-¥:':2s~
\
1.5
tp=3S0
twR=250
1\
"'
175
200
225
...
27S
•
150
300
lAD-ita
Accuracy vs. tRD
150
200
J5V
¥:~;5~-
twFI=250
t ll l)=250
•
•
..
5
250
300
,,-no
350
...
•
vopl=sv
T.. =ZS"C
\
~
\
10
VIIEF-V
.1L8B"~
Accuracyvs VREF
lVREF= VREF ( +) - VREF ( -)]
•
Voo=5V
!,
!~r-----t----i-----+-----r----1
8
i
I
~~~OVT=2.4V
8
•
i
SAME FREQUENCY= 512kHz
T,.,=25"C
r-- r--.
150
INPUTfREO.UENCV -kHz
Effective Number of Bits vs. Input
Signal ( ;j: 2.5V) Frequency
$
r-- t-
IIIINItoVOUT"'D~
i~t_--~~~-t----_t-----r----I
s.0
300
0
8 400 t_----t----t.==!:J;;-::7.~"'F-----I
~
•
\
'50
~'r-----r---~----~-----r----'
-----
275
Accuracy vs. tWR
r----
1\
200
25.
225
tw..-ns
Accuracy vs. tp
..•
7.'
•
15'
10'
"'
2.0
!\
\
...
o
150
~
PowerSupplyCurrentvs. Temperature
(NDt Including/Reference Ladder)
2.0
1\
-50
50
TA- AMBIENTTEMPERATURE_"C
T,."'2S"C
tp=350iRD=250
\,
'.5
T "'_ AMBIENT TEMPERATURE- "C
1.5
V RlEf",5V
~
Voo"'SV
~
V~=..I
1\
i
v~ F=:::: ~
-1~
I.'
t-
2
...
~~~~--_~.=.----~--~.=.----7.,~=---~,
TA-AM8IENTTEMPERATURE- "C
tlNn, Internal Time Delay vs.
Temperature
0
-100
-50
100
50
T,._AMBIENTTEMPERATURE_ "C
150
DutputCurrentvs. Temperature
ANALOG-TO-DIGITAL CONVERTERS 3-371
II
PIN FUNCTION DESCRIPTION
Pill
Mnemonic:
Description
Pill
Mnemonic
Description
VIN
Analog Input: Range VRm - ) "" VIN ""
VRm+).
11
V~-)
Lower limit of reference span.
Range:VSSsVREp( - )tINTl) all the input switches are closed and VIN is
connected to the comparators of the internal LS and MS ADCs.
Therefore, VIN is connected to thirty-one IpF input capacitors
at the same time.
r,
0.
Rs
~:~:T~~
LADDER
•
~
~~~;W
,.MSB COMPARATORS
~
Figure 6. AD7821 Equivalent Input Circuit
INPUT TRANSIENTS
Transients on the analog input signal caused by charging current
flowing into VIN will not normally degrade the ADC's performance.
In effect, the AD7821 does not "look" at the input when these
transients occur. The comparators' inputs track VIN and are not
sampled until the falling edge of WR (WR-RD Mode) or RD
(RD Mode), so at least 3S0ns (tp) is provided to charge the
ADC's input capacitance. It is, therefore, not necessary to filter
out these transients with an external capacitor at the VIN
terminal.
INHERENT TRACK-AND-HOLD
A major benefit of the AD7821's input structure is its ability to
measure a variety of high-speed signals without the help of an
external track-and-hold. Any ADC which does not have a built-in
track-and-hold, regardless of its speed, requires the analog input
to remain stable to at least 1/2LSB for the duration of the conversion
to maintain full accuracy. This requires the use of a track-and-hold
whenever the input is a high-speed signal. The AD7821's sampleddata comparators, by nature of their input switching, inherently
accomplish this track-and-hold function. Although the conversion
time for the AD7821 is 660ns (WR-RD mode, twa +tRD+tACCl),
the. time for which VIN must be stable to 1I2LSB is much smaller.
The AD7821 tracks VIN between conversions only, and its value
on the falling edge of WR or RD in the WR-RD or RD modes
respectively is the measured value.
SINUSOIDAL INPUTS
The bandwidth of the built-in track-and-hold is 100kHz max
(150kHz typ, 5V p-p). This is limited by the analog bandwidth
of the comparators and timing skew between the comparator
switches. This means that the analog input frequency can be up
to 100kHz without the aid of an external track-and-hold. The
Nyquist criterion requires that the sampling rate be at least
twice the input frequency (i.e., ~ 2 x 100kHz). This requires an
ideal antialiasing filter with an inifinite roll-off. To ease the
ANALOG-TO-DIGITAL CONVERTERS 3-373
II
problem of antialiasing filter design, the sampling rate is usually
set much greater than the Nyquist criterion. The maximum
sampling rate (fmaJ for the AD7821 in the WR-RD mode,
(tRD < tlNTU can be calculated as follows:
f
=
DIlIlI
f
....
=
84.&'"
INPUT FREQUENCY ..
95.1IIIHz.I±2.5V)
SAMPLE FREQUENCY .. 5'Zkfk
NO: SECOND OftDER T£RMS .. &4.1dB
- 2 0 r - - - - + I T.. ",~~'!g ORDER TERMS = ....d8
1
t\lVR + tRD+ tRI + tp
1
O.25E 6+0.25E-6+0.15E-6+0.35E-6
t\lVR = Write Pulse Width
tRD = Delay Time between WR and RD Pulses
tRI = RD to INT Delay
tp = Delay Time between Conversions
This permits a maximum sampling rate of IMHz for the AD7821
which is much greater than the Nyquist criterion for sampling a
100kHz analog input signal.
DIGITAL SIGNAL PROCESSING APPLICATIONS
In Digital Signal Processing (DSP) application areas like voice
recognition, echo cancellation and adaptive f!ltering, the dynamic
characteristics (Signal-to-Noise Ratio, Harmouic Distortion,
Intermodulation Distortion) of an ADC are critical. Since the
AD7821 is a very fast ADC with a built-in track-and-hold function,
it is specified dynamically as well as with standard dc specifications
(Total Unadjusted Error etc.).
SIGNAL-TO-NOISE RATIO AND DISTORTION
The dynamic performance of the AD7821 is evaluated by applying
a very low distortion sine-wave signal to the analog input (VIN)
which is then sampled at a 512kHz sampling rate. A Fast Fourier
Transform (FFT) plot is then generated from which Signal-toNoise Ratio (SNR) and harmonic distortion data is obtained.
Figure 8 shows a 2048 point FFT plot of the AD7821 with an
input signal of 100.25kHz. The SNR is 49.1dB. It should be
noted that the harmonics are taken into account when calculating
the SNR. The theoretical relationship between SNR and resolution
(N) is expressed by the following equation:
Figure 9. FFTPlotforlMD
HISTOGRAM PLOT
When a sine wave of specified frequency is applied to the VIN
input of the AD7821 and several thousand samples are taken, it
is possible to plot a histogram showing the frequency of occurrence
of each of the 256 ADC codes. A perfect ADC produ= a probability density function described by the equation:
I
P(V) = ,,(A2 _ V2);'2
where A is the peak amplitude of the sine wave and P(V) the
probability of occurrence at a voltage V.
If a particular step is wider than the ideal 1 LSB width, then
the code associated with that step will accumulate more counts
than for the code for an ideal step. Likewise, a step narrower
than the ideal width will have fewer counts. Missing codes are
easily seen because a missing code means zero counts for a
particular code. The absence of large spikes in the plot indicates
small differential nonlinearity.
Figure 10 shows a histogram plot for the AD7821, which corresponds very well with the ideal shape. The plot indicates very
small differential nonlinearity and no missing codes for an input
frequency of IOO.25kHz.
SNR = (6.02N + 1.76)db .......... (1)
ttl
INPUT FREQUENCV = 100.25kHz (:!:2.SVI
_201-_ _ _ _ _--l~~~P:E4~~lEd~UENCV = 512kHz
INPUTFREOUENCV '" l00.25kH~r:tZ.5VI
SAMPLEFREOUENCV = 512klk
NUMBER OF SAMPLES = 100,000
T.m25"C
= 2SoC
g-40r-------+-----------~
~
TA
5
!-60r-------+---------~
FREQUENCY - kHz
Figure 8. AD7821 FFTPlot
EFFECTIVE NUMBER OF BITS
By working backwards from Equation (I) it is possible to get a
measure of ADC performance expressed in effective number of
bits (N). A plot of the effective number of bits versus input
frequency is given in the Typical Performance Characteristics
section. The effective number of bits typically falls between 7.7
and 7.9 corresponding to SNR figures of 48.1 and 49.7dB.
INTERMODULATION DISTORTION
For intermodulation distortion (IMD), an FFT plot is generated
by sampling an analog input applied to the APC consisting of
very low distortion sine waves at two frequencies. Figure 9
shows a 2048 point plot for IMD.
3-374 ANALOG-TO-DIGITAL CONVERTERS
'"
0"'"
Figure 10. AD7821 Histogram Plot
In digital signal processing applications, where the AD7821 is
used to sample ac signals, it is essential that the signal sampling
occurs at exactly equal intervals. This minimizes errors due to
sampling uncertainty or jitter. A precise timer or clock source,
to start the ADC conversion process, is the best method of
generating equidistant sampling intervals.
The two modes of operation given in the data sheet are suitable
for DSP applications because the sampling instant of the AD7821
is well defmed. VIN is sampled on the falling edge of WR or
RD in the WR-RD or RD modes respectively.
AD7821
DIGITAL INTERFACE
The AD7821 has two basic interface modes which are determined
by the status of the MODE pin. When this pin is low, the
converter is in the RD mode; with this pin high,the AD7821 is
set up for the WR-RD mode.
after the rising edge of WR. In this case RD going low transfers
the data result into the output latch and activates the data output
(DBO-DB7). INT is driven low on the falling edge of RD and is
reset on the rising edge of RD or CS. The timing for this interface
is shown in Figure 12b.
The RD mode is designed for microprocessors which can be
driven into a WAIT state. A READ operation (i.e., CS and RD
are taken low) starts a conversion and data is read when the
conversion is complete. The WR-RD mode does not require
microprocessor WAIT states. A WRITE operation (i.e., CS and
WR are taken low) initiates a conversion, and a READ operation
reads the result when the conversion is complete.
II
=
RD Mode (MODE
0)
The timing diagram for the RD mode is shown in Figure 11.
This mode is intended for use with microprocessors which have
aWAIT state facility, whereby a READ instruction cycle can
be extended to accommodate slow memory devices. A conversion
is started by taking CS and RD low (READ operation). Both
CS and RD are then kept low until output data appears.
In this mode, Pin 6 of the AD7821 is configured as a status
output, RDY. This RDY output can be used to drive the processor
READY or WAIT input. It is an open drain output (no internal
pull-up device) which goes low after the falling edge of CS and
goes high impedance at the end of conversion. An INT line is
also provided which goes low when a conversion is complete.
INT returns high on the rising edge of CS or RD.
Figure 12a. WR-ROMode(tRD>tINn)
Cs\1~---tcS"~1).t~ \,~----AD
RDV
~
1-..-J----
---rd..!-___-'~WlTHEX~NALPULL.UP
..
\
~ '~:
1J-~"'"-
~
, ....--1
1
080-087--------------(
~.ACCO~
I
~~: I
r-------
~ toN I--
Figure 12b. WR-ROMode(tRD instruction, where addr is the decoded ADC address
and Dn is the data register into which the result is placed.
n·", -----,
ADDRESS BUS
,..--------'
.....
....-'~-<-
68008
RMi
iiTACK 1-------0(
AD7821- TMS32010 INTERFACE
A typical interface to the TMS32010 is shown in Figure 16. The
AD7821 is mapped au port address and the interface is designed
for the maximum TMS32010 clock frequency of 20MHz. In this
case the AD7821 is cOl)figured in the WR-RD interface mode.
This means that a write instruction starts a conversion and a
read instruction reads the result when the conversion is completed.
A precise timer or clock source is used to start a conversion in
applications requiring equidistant sampling intervals. The scheme
used, whereby the AD7821 generates an interrupt to the
TMS3201O, is limited in that it does not allow the AD7821 to
be sampled at its maximum rate. This is because the time between
samples has to be long enough to allow the TMS32010 to service
its interrupt and read data from the AD7821. Constant interruption
of the TMS32010 by the AD7821, every time the ADC completes
a conversion, is not a very efficient use of the processor time.
To overcome these problems, some buffer memory or FIFO
could be placed between the AD7821 and the TMS3201O. The
INT line of the AD7821 could be used to trigger a pulse which
drives its CS and RD lines and places the AD7821 data into a
FIFO or buffer memory. The microprocessor can then read a
batch of data from the FIFO or buffer memory at some convenient
time. Reading data from the AD7821, after an INT has been
received, consists of < IN A, PA > instruction (PA is the decoded
ADC address).
PA2r-----,
P.,I-----,
PAO
D'~------------~
00
Nr-------------------------J
-ADDITIONAL CIRCUITRY OMITTED FOR CLARITV.
Figure 14. AD7821 to 68008 Interface
AD7821- 8088 INTERFACE
A typical interface to the 8088 is shown in Figure IS. The AD7821
is configured for the RD interface mode. One read instruction
starts a conversion and reads the result. The read cycle is stretched
out over the entire conversion period by taking the RDY line
back to the READY input of the 8088. Starting a conversion
and reading the result consists of a < MOV AX, (addr) > instruction, where addr is the decoded ADC address and AX is
the 8088 data register into which the conversion result is placed.
DEN~~::::::::~~:{=:
ffiIT~------------~
TMS32010
D'r-------~
DON-------------------J
*ADomONAL CIRCUITRV OMITTED FOR CLARITY.
Figure 16. AD7821 to TMS32010lnterface
AD7821- 8051 INTERFACE
Figure 17 shows the AD7821 interface to the 80S 1 microcomputer
The AD7821 is configured in the WR-RD interface mode and is
connected to the 80S 1 ports. The processor starts conversion
and then polls INT, until it goes low, before reading the conversion
result. Data is read from the AD7821 by using the < MOV A,
90H > instruction (90H is the address for Port 1).
P3.1
WR
Pl.2
INT
P3,3
RO
~
8051
cs
P1.0
DBO
P1.'
OBI
I
I
DB'
P1.7
"ADDITIONAL CJACUITfIY OMITTED FOR CLARfTY.
*ADOInONAL CIRCUITRV OMlnED FOR CLARJTY.
Figure 15. AD7821 to 8088 Interface
Figure 17. AD7821 to 8051 Interface
3-376 ANALDG-TO-DIGITAL CONVERTERS
AD7821'
AD7821
APPLYING THE AD7821
The AD7821 is specified for a unipolar input range of 0 to + SV
and a bipolar input range of - 2.SV to + 2.SV. The VREF ( - )
and VREF ( + ) voltages required for these input ranges are outlined
below. See the Typical Performance Characteristics section for
operation with unspecified input voltage ranges.
16-CHANNEL TELECOM AID CONVERTER
The fast sampling rate (IMHz) and bipolar operation of the
AD7821 makes it useful in Telecom applications for sampling a
number of input channels using a multiplexer. Figure 21 shows
a circuit for such an application.
+5V
-5V
Voo
Vss
VON
V1N I:t2.5V)
3kHz MAX
GND
D
AD7821'
+5V - . . . . , - -.....- - - - - - - i V••
-sv
+5V
Vss
Vao
\------lv"
V 1N (:!:2.5V)
3kHz MAX
v..
11
ADG506A
VREFI+I
+2.SV
VREF( - )
-2.SV
"ADDITIONAL CIRCUITRY OMmED FOR CLARITY.
RANGE
VON
+5V
+2.5V
2.5V
5V
UNIPOLAR
BIPOLAR
0 to + SV
-2.5Vto +2.5V
GND
Figure 18. AD7821 UnipolarlBipolarOperation
UNIPOLAR OPERATION
Figure 18 gives the configuration and reference voltages required
for 0 to + SV operation. The nominal transfer characteristic for
this input range is shown in Figure 19. The output code is
Natural Binary with ILSB
(S/256) V = 19.5mV.
i
OUTPUT
CODE
FULL SCAlE
TRANSrno\
::::
,,/ji:
11111101
I
I
I
' ,'
::::iL
,,~:::~
i
00000001
I
-
0000 0000
01LS82LS8'S US'S
-
- - - -
-r---f---+L:-
Figure 21. 16-Channel Telecom AID Converter System
The maximum signal frequency required for acceptable quality
in Telecom applications is 3kHz. The circuit given in Figure 21
permits each of the 16-input channels to be sampled at a rate of
16kHz maximum. The sampling rate takes account of such
multiplexer parameters as tON, settling time etc. The circuit also
eases the problem of the anti-aliasing filter design by sampling
at a rate much greater than that required by the Nyquist
criterion.
SIMULTANEOUS SAMPLING AID CONVERTERS
The AD7821's inherent track-and-hold and well defined sampling
instant makes it useful, in such applications as sonar, where a
number of input channels are required to be sampled simultaneously. Figure 22 shows a circuit for such an application.
-5V
1LSB
+5V
VIN INPUT VOLTAG£ liN TERMS OF LSBsI
Figure 19. Nominal Transfer Characteristic for Unipolar
(0 to + 5V) Operation
BIPOLAR OPERATION
Figure 18 gives the configuration and reference voltages required
for - 2.SV to + 2.5Voperation. The nominal transfer characteristic
for this input range is shown in Figure 20. The output code is
Offset Binary with ILSB = ([ +2.S - (-2.S)j/256)V = 19.5mV.
cso--......----i
Wlio--+-......- - t Wli
DBO
iiDl1I---r-+---i
1-----"
DB7
V IN1
---+-+--1
AD7821
OUTPUT
nn"'~looE
11111110
iiDI21 ___';--!-_--I
::::t"
10000000"2
01111111
V1N2 ----.-,----t
iT---t-t----'i~~;;;-'---v.
I
:
;;flrP
o/-'LSB
FS .. SV
I
'LS8"'~
Figure 20. Nominal Transfer Characteristic for Bipolar
(-2.5Vto +2.5V) Operation
I
I
~--(:JD7U1 --~
"'-f---- 1
!
I
I
Figure 22. Simultaneous Sampling AID Converters
ANALOG-TO-DIGITAL CONVERTERS 3-377
The actual sampiing instant which is the instant at which VIN is
meaSured, occurs approximately SOns after the falling edge of
WR or RD in the WR-RD or RD modes, respectively, due to
intemallogic delays. However, the internal logic delay and,
3-378 ANALOG-TO-OIGITAL CONVERTERS
therefore, the sampling instant can vary from device to device,
but is typically within ± Sns. This means that a maximum common
input sine wave of ± 2.SV at 32kHz, applied to any number of
AD7821s in the circuit of Figure 22, will yield a maximum
difference between the converter outputs of typically ± 1I4LSB.
1IIIIIIII ANALOG
WDEVICES
LC 2MOS
High Speed 4- &8-ChanneI8-Bit ADCs
AD 7824/AD7828 I
FEATURES
AD7824/AD7828 FUNCTIONAL BLOCK DIAGRAM
4- or 8-Analog Input Channels
Built-In Track/Hold Function
10kHz Signal Handling on Each Channel
Fast Microprocessor Interface
Single + 5V Supply
Low Power: 50mW
Fast Conversion Rate, 2.5/otsiChannel
TIght Error Specification: 1/2LSB
DB'
0..
DBS
0 ...
THREE
STATE
DRIVERS
DB3
002
DB'
DBO
iNT
AO
A1
A2··
RDY
os
Rii
·AD7824 _ 4-CHANNEL MUX
ADl828 - 8-CHANNEl MUX
··A2 - AD7828 ONLY
GENERAL DESCRIPTION
The AD7824 and AD7828 are high-speed, multichannel, 8-bit
ADCs with a choice of 4 (AD7824) or 8 (AD7828) multiplexed
analog inputs. A half-flash conversion technique gives a fast
conversion rate of 2.5fLS per channel and the_parts have a built-in
tracklhold function capable of digitizing full-scale signals of
10kHz (I57mV/",s slew rate) on all channels. The AD7824 and
AD7828 operate from a single + 5V supply and have an analog
input range of 0 to + 5V, using an external + 5V reference.
Microprocessor interfacing of the parts is simple, using standard
Chip Select (CS) and Read (RD) signals to intitiate the conversion
and read the data from the three-state data outputs. The half-flash
conversion technique means that there is no need to generate a
clock signal for the ADC. The AD7824 and AD7828 can be
interfaced easily to most popular microprocessors.
PRODUCT HIGHLIGHTS
1. 4- or 8-channel input multiplexer gives cost-effective spacesaving multichannel ADC system.
2. Fast conversion rate of 2.5fLslchannel features a per channel
sampling frequency of 100kHz for the AD7824 or 50kHz for
the AD7828.
3. Built-in track-hold function allows handling of 4- or 8-channels
up to 10kHz bandwidth (I57mV/fLs slew rate).
4. Tight total unadjusted error spec and channel-ta-channel
matching eliminate the need for user trims.
5. Single
+ 5V supply simplifies system power requirements.
6. Fast, easy-to-use digital interface allows connection to most
popular microprocessors with minimal external components.
No clock signal is required for the ADC.
The AD7824 and AD7828 are fabricated in an advanced, all
ion-implanted, Linear-Compatible CMOS process (LC2 MOS)
and have low power dissipation of 40mW (typ). The AD7824 is
available in a 0.3" wide, 24-pin "skinny" DIP, while the AD7828
is available in a 0.6" wide, 28-pin DIP and in 28-terminal surface
mount packages.
ANALOG-TO-DIGITAL CONVERTERS 3-379
•
+5V; V +)= +5V; V
)=GND =DVunless othetWise slated).
CAJI ONS All(Voo=specifications
SPEC
. .. IFI
Tm/n to T.... unless othelWise specified. Specifications apply for Mode O.
REF (
Parameter
ACCURACY
Resolution
Total UnadjustedErro~
Minimum Resolution for which
No Missing Codes are guaranteed
Channel to Channel Mismatch
REFERENCE INPUT
Input Resistance
VREF C+ ) Input Voltage Range
VREFC - ) Input Voltage Range
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance'
LOGIC INPUTS
RD,CS,AO,Al &A2
VINH
VINL
IlNH
IlNL
Input Capacitance'
LOGIC OUTPUTS
DBO-DB7&INT
VOH
VOL
loUT CDBO-DB7)
Output Capacitance'
RDY
VOL4
lOUT
Output Capacitance
SLEW RATE, TRACKING'
POWER SUPPLY
Voo
5
100
Power Dissipation
Power Supply Sensitivity
REF (-
KVersionl
LVersion
B, TVersions
C, V Versions
Vnits
8
±I
8
±1/2
8
±1
8
±1/2
Bits
LSBmax
8
±1/4
8
±1/4
8
± 114
8
± 114
Bits
LSBmax
1.0/4.0
VREFC -)/
Voo
GND/
VREF(+)
1.0/4.0
VREFC-)/
Voo
GND/
VREF(+)
1.0/4.0
VREFC-)/
Voo
ill minlkn max
VREF (+)
1.0/4.0
VREFC-)/
Voo
GND/
VREF (+)
VREPC-)1
VREFC +)
±3
45
VREFC -)/
VREFC +)
±3
45
VREPC-)I
VREFC +)
±3
45
VREFC -)/
VREFC +)
±3
45
VminIVmax
...Amax
pFtyp
Analog Input Any Channel
010 +5V
2.4
0.8
1
-I
8
2.4
0.8
1
-1
8
2.4
0.8
1
-1
8
2.4
0.8
I
-1
8
V min
V max
...Amax
...Amax
pFmax
Typically 5pF
4.0
0.4
±3
8
4.0
0.4
±3
8
4.0
0.4
±3
8
4.0
0.4
±3
8
V min
V max
...Amax
pFmax
IsouReE = 360 ...A
ISINK = 1.6mA
Floating State Leakage
Typically 5pF
0.4
±3
8
0.4
±3
8
0.4
±3
8
0.4
±3
8
V max
...Amax
pFmax
ISINK = 2.6mA
Floating State Leakage
Typically 5pF
0.7
0.157
0.7
0.157
0.7
0.157
0.7
0.157
V/ .... typ
V/ ...smax
5
5
5
5
Volts
16
50
80
± 114
16
50
80
±1I4
20
50
100
±1I4
20
50
100
±1I4
mAmax
mWtyp
mWmax
LSBmax
NOTES
'Temperature Ranges are as follows:
K, L Versions; 0 to + 70"C
B,CVersions; -25"Cto + 85°C
T, UVersions; -55"Cto + 125°C
'Total Unadjusted Error includes offset, full-scale aod linearity errors.
'Sample tested at 25"C by Product Assurance to ensure compliaoce.
4RDY is an open drain output.
5S.. Typical Performance Characteristics.
Specifications subject to change without notice.
3-380 ANALOG-TO-DIGITAL CONVERTERS
GNDI
Conditions/Comments
V minIV max
V minIV max
± 5% for Specified
Performance
CS=RD=2.4V
± 1I16LSB typ
Voo=5V ±5%
AD7824/AD7828
TIMING CHARACTERISTICS 1 (Yuu= +5V; v
REf <+)=
+5V; vREf <- )=GND=OVunless otherwise stated)
Limit at
Limitat
Tmin,Tmax
Tmin,Tmax
Parameter
Limit at 25°C
(All Grades)
(K,L,B,CGrades)
(T, U Grades)
Units
Conditions/Comments
tess
teSH
t AS
tAH
tRDy2
0
0
0
30
40
0
0
0
35
60
0
0
0
nsmin
nsmin
nsmin
nsmin
nsmax
teRD
tACCI 3
tACC23
tlNTH2
2.0
85
50
2.4
110
60
65
100
70
CS to RD Setup Time
CS to RD Hold Time
Multiplexer Address Setup Time
Multiplexer Address Hold Time
CS toRDYDelay.Pull-Up
Resistor 5kO.
Conversion Time, Mode 0
Data Access Time after RD
Data Access Time after INT , Mode 0
RD to INT Delay
40
75
tDH4
tp
tRD
60
40
60
80
2.8
120
70
70
100
70
600
80
SOO
400
SOO
500
60
600
iJ.smax
nsmax
nsmax
nstyp
nsmax
nsmax
nsmin
nsmin
nsmax
Data Hold Time
Delay Time between Conversions
Read Pulse Width, Mode I
NOTES
'Sample tested at 25°C to ensure compliance. All input control signals are specified with rr=tf=20ns (10% to 90% of +5V) and timed from a
voltage level of 1.6V.
'C L ~ SOpF.
3Measured with load circuits of Figure 1 and defined as the lime required for an outpm to cross O.8V or 2AV.
4Defined as the time required for the data lines to change O.5V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBNo---~------~~--O
T
3kfl
DGND
100pF
'V
a. High-Zto VOH
DBNo---~------~~--~
T
3kfl
DGND
10pF
'V
a. VOHtoHigh-Z
!3kfl
DBN~
~::O~:
b. High-Zto VOL
b. VOL to High-Z
Figure 1. Load Circuits for Data Access Time Test
Figure 2. Load Circuits for Data Ho/d Time Test
ANALOG-TO-DIGITAL CONVERTERS 3-381
•
ABSOLUTE MAXIMUM RATINGS·
- 25"C to + 85°C
Industrial (B, C Versions)
Extended (T, U Versions)
- 55"C to + 125°C
-65°C to + I500C
Storage Temperature Range •
Lead Temperature (Soldering, IOsecs)
+3000C
Power Dissipation (Any Package) to + 75°C
450mW
Derates above + 75°C by . . • . . • . . . .
6mWI"C
(TA = +2S"CunJessotberwisenoted)
VDD
· . . . . . OV, +7V
•••••••••••••
Digital Input Voltage to GND
(RD, CS, AO, Al & A2) .
Digital Output Voltage to GND
(DBO, DB7, RDY & INT)
VREF ( + ) to GND
VREF ( - ) to GND
Analog Input (Any Channel)
Operating Temperature Range
Commercial (K, L Versions)
-0.3V, VDD +0.3V
-0.3V, VDD +0.3V
VREF ( - ) , VDD +O.3V
· .•. OV, VREF (+)
-O.3V, VDD +0.3V
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the· device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
· . . . . 0 to +70°C
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEV'CE
PIN CONFIGURATIONS
DIP
PLCC
LCCC
•
AIN7
IA
ID
....
~ ~ ~
AIN8
.
"
~
~ ~ ~
co
i
>
. .~
z
C
~
z
C
8
>
21282726
0
AD
A1
A2
AD7828
TOP VIEW
INottoScalel
oB7
oBS
AlN2 5
2S AD
AIN1 6
24 A1
NC 7
DBO 8
081 9
A1
23A2
AD7828
A2
22 DB7
TOP VIEW
(Not to $cale'
oB7
210BS
DB2 10
20 CBS
DB3 11
19 DB4
"I!=::=====.J)
oBS
002
oBS
0B4
12 13 14 15 16 17 18
0B4
11E1!,,~'+Q
..>If]
os
ROY
AD7828
TOP VIEW
(Not to Scale)
AD
Iii! I~ zQ I
11
Ne
= NO CONNECT
> >
NC
==
+
"I }
..> If]
Q
NO CONNECT
V""'Ff+1
ORDERING INFORMATION1, 2
V",Efl-1
Total
Unadjusted
Error
NC :: NO CONNECT
Temperature Range and Package Options3
Oto +700C
- 25°C to + 85"C
- 55°C to + 125°C
PJasticDIP(N-28)
Hermetic4 (Q-28)
Hermetic4 (Q-28)
AD7828KN
AD7828LN
PLCCs (P-28A)
AD7828BQ
AD7828CQ
AD7828TQ
AD7828UQ
NC
AD
±ILSB
±1I2LSB
A1
DB7
±ILSB
AD7828KP
DB.
±1/2LSB
AD7828LP
DB'
0B4
iID
RDV
NC :: NO CONNECT
~382
±ILSB
±1I2LSB
LCCC6 (E-28A)
AD7828TE
AD7828UE
Plastic DIP (N-24)
Hermetic' (Q-24)
Hermetic' (Q-24)
AD7824KN
AD7824LN
AD7824BQ
AD7824CQ
AD7824TQ
AD7824UQ
NOTES
ITo order MIL-STD-883, Class B processed parts, addl883B to part number.
Contact your local sales office for military data sheet.
2Analog Devices reserves the right to shlp either cerdip or ceramic hermetic packages.
'See Section 14 for package outline information.
'Package outline cerdip (Q-28) or ceramic (0.28).
spLCC: Plastic Leaded Chip Carrier.
6LCCC: Leadless Ceramic Chip Carrier.
'package outline cerdip (Q-24) or ceramic (D-24A).
ANALOG-TO-DIGITAL CONVERTERS
Typical Performance Characteristics - AD7824/AD7828
,.
13
~
..~.
"u>
t
"j
In
-~
~
0
1H
11
'0
II
,~--~----~----~--~----~
-'00
12
'50
-so
-'00
TA - AMBIENT TEMPERATURE- ·C
Conversion Time vs. Temperature
2.0
~
'.5
~
0.5
o
T.., = 25"<:
'.5
~
'.0
~
"
~
"-
0.5
300
I----
..... ""'-
o
o
400
500
...
700
800
900
tp-ns
VREF-V
v_
'.
VuF =5V
T... =Z500c
\\
ID
!!l
~
v~L
\
..,
\
z
"
2.0
Voo=5V
\
i:Ii 1.0
'so
'00
Power Supply Current vs.
Temperature (not including
reference ladder)
I
'\
so
TA -AMBJENTTEMPERATURE- "C
.1lS8=.
Accuracy vs. tp
Accuracyvs. VREF
fVREF= VREF( +) - VREF( -)]
'0
-36
VDo =5V
-36
-40
/
-42
.
-
"'"'-
ISl~!' VOU1=O.~ "'"'-
V
-46
,,'"
-50
-52
r-- r-
/
-46
--
~~OUT=2i4V
,
2345710
20
30 4050 70 100
INPUT FREQUENCY-kHz
ENCODE RATE "" 400kHz
INPUT SIGNAL"" 5V pop
MEASUREMENT BANDWIDTH "" 80kHz
Signal-Noise Ratio vs. Input Frequency
o
-100
- so
so
T... - AMBIENT TEMPERATURE -
'00
'so
3c
Output Current vs. Temperature
ANALOG-TO-DIGITAL CONVERTERS 3-383
OPERATIONAL DIAGRAM
The AD7824 is a 4-channel 80bit AID convertet and the
AD7828 is an 8-channel 80bit AID convener. Operational
diagrams for both of these devices are sbown in Figures 3
and 4. The addition of just a + SV reference allows the devices
to perform the analog-to-digital function.
+5V
ANALOG INPUTS {
GTO +5V
}
"PADDRESS
BUS
}
"P4MSB
DATA BUS
"PCONTROL
INPUT
APPLYING THB AD78241AD7828
REFERENCE AND INPUT
The two reference inputs on the AD7824/AD7828 are fully
differential and defme the zero to full-scale input range of the
AID converter. As a result, the span of the analog input voltage
for all channels can easily be varied. By reducing the reference
span, VREF (+) - VREF (-), to less than SV the sensitivity of
the converter can be increased (e.g., if VREF = 2V then lLSB
= 7 .8mV). The input/reference arrangement also facilitates
ratiometric operation.
This reference flexibility also allows the input channel voltage
span to be offset from zero. The voltage at VREF ( - ) sets the
input level for all channels which produces a digital output of
all zeroes. Therefore, although the analog inputs are not themselves
differential, they have nearly differential-input capability in
most measurement applications because of the reference design.
Figures 5 to 7 show some of the configurations that are
possible.
STATUS OUTPUT
STATUS OUTPUT
V'N i +;
+5V
----oooooji AIN 1
___
- - -....---1 GND
AD7824*
AD7828*
+5V--.-----.----.~Voo
Figure 3. AD7824 Operational Diagram
V...,I+I
VREFI-I
• ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN
ANALOG INPUTS
GTO +5V
1
Figure 5. Power Supply as Reference
}
"PADDRESS
BUS
}c:,:
Y'N 1 + 1 - - - - - - - - - - _ 1 AIN 1
_ _ _ _~~-----_IGND
+5V -
....-
--------1 VDD
.....- -_ _
r-L-~~_-_-....,I
"PCONTROL
INPUT
STATUS OUTPUT
STATUS OUTPUT
Figure 4. AD78280perationalDiagram
CIllCUIT INFORMATION
BASIC DBSCBIPTlON
The AD78241AD7828 uses a half-flash conversion technique
whereby twD 4-bit fIasb AID converters are used to achieve
an 80bit result. Bach 4-bit tlasb ADC contains IS comparators
which compare the unknown input to a reference ladder to
get a 4-bit result. For a full 80bit reading to be realized, the
upper 4-bit flash, the most significant (MS) flash, performs a
conversion to provide the 4 most significant data bits. An
internal DAC, driven by the 4MSBs, then recreates an analog
approximation of the input voltqe. This analog result is
subtracted from the input, and the difference is converted by
the lower flash ADC, the least significant (LS) flash, to
provide the 4 least significant bits of the output data.
3-384 ANALOG-TO-DIGITAL CONVERTERS
AD7824*
AD7828*
VREF (+1
~-'--_>--""---I VA.. I-I
"ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN
Figure 6. External Reference Using the AD580, Full-Scale
Input is 2.5V
V'NI+I
AINl
GND
+5v-_--_-----~VDD
~.l"F ~7"F
AD7824*
AD7828* DB7
VAEFI+I
V2
VAEFI-I
DBa
"ADDITIONAL PINSOMmED FOR ClARITY.
ONLY CHANNEL 1 SHOWN
DATA
=~
v,..v, '256
IFORALLCHANNELSI
Figure 7. Input Not Referenced to GND
AD7824/AD7828
INPUT CURRENT
Due to the novel conversion techniques employed by the AD78241
AD7828, the analog input behaves somewhat differently than in
conventional devices. The ADC's sampled-data comparators
take varying amounts of input current depending on which
cycle the conversion is in.
The equivalent input circuit of the AD7824/AD7828 is shown in
Figure 8. When a conversion starts (CS and RD going low), all
input switches close, and the selected input channel is connected
to the most significant and least significant comparators. Therefore,
the analog input is connected to thirty-one IpF input capacitors
at the same time.
rl
r-"".,. ,+_-O/"C. . ."""'-..~"';,..~E-R-~O"tfr
.
fl2~F
.~-kJ
15LSBCOMPARATORS
RON
TOMS
LADDER
-xT~
•
~
lpF
16MSBCOMPARATORS
Figure 8. AD78241AD7828 Equivalent Input Circuit
The input capacitors must charge to the input voltage through
the on resistance of the analog switches (about 3k to 6k). In
addition, about 14pF of input stray capacitance must be charged.
The analog input fOl' any channel can be modelled as an RC
network as shown in Figure 9. As Rs increases, it takes longer
for the input capacitance to charge.
source impedence of not greater than 100 ohms be connected to
the analog inputs. The output impedence of an op-amp is equal
to the open loop output impedence divided by the loop gain at
the frequency of interest. It is important that the amplifier
driving the AD7824/AD7828 analog inputs have sufficient loop
gain at the input signal frequency as to make the output impedance
low.
Suitable op-amps for driving the AD7824/AD7828 are the AD544
or AD644.
INHERENT SAMPLE-HOLD
A major benefit of the AD7824's and AD7828's analog input
structure is its ability to measure a variety of high-speed signals
without the help of an external sample-and-hold. In a conventional
SAR type converter, regardless of its speed, the input must
remain stable to at least 1I2LSB throughout the conversion
process if rated accuracy is to be maintained. Consequently, for
many high-speed signals, this signal must be externally sampled
and held stationary during the conversion. The AD7824/AD7828
input comparators, by nature of their input switching inherently
accomplish this sample-and-hold function. Although the conversion time for AD78241 AD7828 is 2 ....s, the time for which any
selected analog input must be 1/2LSB stable is much smaller.
The AD7824/AD7828 tracks the selected input channel for
approximately l ....s after conversion start. The value of the analog
input at that instant o. . s from conversion start) is the measured
value. This value is then used in the least significant flash to
generate the lower 4-bits of data.
SINUSOIDAL INPUTS
The AD7824/AD7828 can measure input signals with slew rates
as high as 157mV/ ....s to the rated specifications. This means that
the analog input frequency can be up to 10kHz without the aid
of an external sample and hold. Furthermore, the AD7828 can
measure eight 10kHz signals without a sample and hold. The
Nyquist criterion requires that the sampling rate be twice the
input frequency (i.e., 2 x 10kHz). This requires an ideal anti-aliasing fllter with an infinite roll-off. To ease the problem of anti-aliasing fllter design, the sampling rate is usually much greater than
the Nyquist criterion. The maximum sampling rate (F.".,,) for
the AD7824/AD7828 can be calculated as follows:
1
F.,.. = teRD +
10
1
F .... = 2E-6+0.5E-6
= 400kHz
lcRD = AD7824/AD7828 Conversion Time
tp = Minimum Delay Between Conversion
Figure 9. RC Network Model
The time for which the input comparators track the analog
input is approximately IJl.S at the start of conversion. Because of
input transients on the analog inputs, it is recommended that a
This permits a maximum sampling rate of 50kHz for each of
the 8 channels when using the AD7828 and 100kHz for each of
the 4 channels when using the AD7824.
ANALOG-TO-DIGITAL CONVERTERS 3-385
•
UNIPOLAR OPERATION
The analog input range for any cbannd of the AD78241AD7828
is 0 to SV as shown in the unipolar operational diagram of Figure
10. Figure 11 shows the designed code transitions whic:h occur
midway between successive integer LSB values (i.e., 1I2LSB,
312LSB, SI2LSB, FS-3I2LSBs). The output code is Naturai
Binary with lLSB = FSI256 = (S/2S6)V = 19.5mV.
25kll
40kll
AINl
27kll
+SV---'V\"""...-I
AD7824'
AD7828*
+ 5V - -.....- - - -.....- - - - - - - i VDD
V••F(-I
GND
+5V--~----~-----------iVoo
SV
'ADDmONAl PINS OMITTED FOR CLARITY,
ONLY CHANNEL 1 SHOWN
Figure 12. AD7824/AD7828 Bipolar ±4VOperation
1
'ADDITIONAL PINS OMITTED FOR CLARITY,
Of'llYCHANNE!..1 SHOWN
Figure 10. AD78241AD7828 Unipolar 0 to 5V Operation
10000001
i
----J:
10000000 1--...J------4----~......
OUTPUT
CODE
11111111
01111111
FULL SCALE
01111110
TRANSmO\
11111110
1111"01
00000001
0000001°l
oooooooo
/
I
I
~--------~~----------~
AIN,lNPUTVOlTAGE (IN TERMS OF LSBsl
I
I
~,'
,
1LSB=~
'
:::::::tL'
-- ---01LSB2lSB'S 3lSB'S
Figure 13. Ideal Input/Output Transfer Characteristic for
±4VOperation
TIMING AND CONTROL
00000001
00000000
FS=8V
1 lSB = FSl256
I
I
I.
\.. FS
AIN,INPUT VOLTAGE (IN TERMS OF LSBsl
FS - 1lSB
Figure ". Ideal Input/Output Transfer Characteristic for
Unipolar 0 to + 5V Operation
BIPOLAR OPERATION
The circuit of Figure 12 is designed for bipolar operation. An
ADS44 op-amp conditions the signal input (YIN) so that only
positive voltages appear at AIN 1. The closed loop transfer
function of the op-amp for the resistor values shown is given
below:
AIN I = (2.5 - 0.625 VIN) Volts
The analog input range is ::!:4Vand the LSB size is 31.2SmV.
The output code is complementary offset binary. The ideal
input/output characteristic is shown in Figure 13.
The AD7824/AD7828 has two digit8.t inputs for timing and
control. These are Chip Select (CS) and Read (RD). A READ
operation brings CS and RD low which starts a conversion on
the channel selected by the multiplexer address inputs (see
Table I). There are two modes of operation as outlined by the
timing diagrams of Figures 14 and IS. Mode 0 is designed for
microprocessors which can be driven into a WAIT state. A
READ operation (Le., CS and RD are taken low) starts a conversion
and data is read when conversion is complete. Mode I does not
require microprocessor WAIT states. A READ operation initiates
a conversion and reads the previous conversion results.
AD78Z4
AI
At
0
0
1
0
1
0
1
1
AD7828
A2 Al
0
0
0
0
1
1
1
1
CHANNEL
AD
0
0
1
1
0
0
0
1
0
0
1
1
1
0
1
1
AINI
AIN2
AIN3
AIN4
AINS
AIN6
AIN7
AIN8
Table I. Truth Table for Input Channel Selection
3-386 ANALOG-TO-DIGITAL CONVERTERS
AD7824/AD7828
MODEl
MODE 0
Figure 14 shows the timing diagram for Mode 0 operation. This
mode can only be used for microprocessors which have a WAIT
state facility, whereby a READ instruction cycle can be extended
to accommodate slow memory devices. A READ operation
brings CS and RD low which starts a conversion. The analog
multiplexer address inputs must remain valid while CS and RD
are low. The data bus (DB7-DBO) remains in the three-state
condition until conversion is complete. There are two converter
status outputs on the AD7824/AD7828, interrupt (INT) and
ready (RDY) which can be used to drive the microprocessor
READYIWAIT input. The RDY is an open drain output (no
internal pull-up device) which goes low on the falling edge of
CS and goes high impedance at the end of conversion, when the
8-bit conversion result appears on the data outputs. If the RDY
status is not required, then the external pull-up resistor can be
omitted and the RDY output tied to GND. The INT goes low
when conversion is complete and returns high on the rising edge
ofCS or RD.
Mode I operation is designed for applications where the microprocessor is not forced into aWAIT state. A READ operation
takes CS and RD low which triggers a conversion (see Figure
15). The multiplexer address inputs are latched on the rising
edge of RD. Data from the previous conversion is read from the
three-state data outputs (DB7-DBO). This data may be disregarded
if not required. Note, the RDY output (open drain output) does
not provide any status information in this mode and must be
connected to GND. At the end of conversion INT goes low. A
second READ operation is required to access the new conversion
result. This READ operation latches a new address into the
multiplexer inputs and starts another conversion. INT returns
high at the end of the second READ operation, when CS or RD
returns high. A delay of 2.SfLS must be allowed between READ
operations.
Oh:...
'-1 (
---------------------~~~..~~=:-t-P~--t~AS~
ANALOG ~~~~----------~AD~D~R~------------~LJ-y~~~~~
~~~~~:~
VALID
RDV+-----H
INT ....----.;-...--------------
~tcAD_-:-------tI~___i_'
tACe'
DATA ______~H_I_GH~IM_P_E_DA_N_C_E~______(
Figure 14. Mode
aTiming Diagram
Figure 15. Mode 1 Timing Diagram
ANALOG-TO-DIGITAL CONVERTERS 3-387
3
MICROPROCESSOR INTERFACING
The AD78241AD7828 is designed to interface to microprocessors
as Read Only Memory (ROM). Analog channel selection, conRD
version start and data read operations are controlled by
and the channel address inputs. These signals are common to all
ml:mory peripheral devices.
es,
Z80 MICROPROCESSOR
Figure 16 shows a typical AD78241AD7828 - Z80 interface.
The AD78241AD7828 is operating in Mode o. Assume the ADC
is assigned a memory block starting at address eooo. The following
LOAD instruction to any of the addresses listed in Table II will
start a conversion of the selected channel and read the conversion
result.
LD B,
(Cooo)
At the beginning of the instruction cycle when the ADC address
is selected, RDY asserts the WAIT input, so that the Z80 is
forced into a WAIT state. At the end of conversion RDY returns
high and the conversion result is placed in the B register of the
microprocessor.
MC68000 MICROPROCESSOR
Figure 17 shows a MC68000 interface. The AD78241AD7828 is
operating in Mode o. Assume the ADC is again assigned a memory
block starting at address COOO. A MOVE instruction to. any of
the addresses in Table II starts a conversion and reads the conversion result.
MOVE·B $COOO,DO
Once conversion has begun, the MC68000 inserts WAIT states,
until INT goes low asserting DTACK at the end of conversion.
The microprocessor then places the conversion results in the DO
register.
~~--------------------------~
RIW
MeS8000
A1'
A2
...
MREQ
zao
t'"
J t i
ADDRESS BUS
AO
7
:s!
HEN
ADDRESS
DECODE
T
1
I
AO
A2**
DATA BUS
DO~------,
,..------IDBO
"LINEAR CIRCUITRY OMITTED FOR CLARITY I
cs
ROY
iiil
A1
D7~--------------~
....A2ISFORTHEAD78280NLY
5k
WAIT
I
AD7824*
AD782a*
Figure 17. AD78241AD7828-MC68000Interface
RO
07
DB7
DATA BUS
DO
I
ORO
R CIRCUITRY OMITTED FORCLARITV
THEAD782BONLV
Figure 16. AD78241AD7828-Z801nterface
TMS32010 MICROCOMPUTER
A TMS32010 interface is shown in Figure 18. The AD78241
AD7828 is operating in Mode I (i.e., no jl.P WAIT states). The
ADC is mapped at a port address. The following I/O instruction
starts a conversion and reads the previous conversion result into
the accumulator.
IN, A PA (PA = PORT ADDRESS)
The port address (000 to lll) selects the analog channel to be
converted. When conversion is complete a second I/O instruction
(IN, A PA) reads the up-to-date data into the accumulator and
starts another conversion. A delay of 2.5j1.S must be allowed
between conversions.
ADDRESS
COOO
COOl
c002
c003
COO4
COOS
COO6
c007
AD7824
Channel
AD7828
Channel
I
2
3
4
I
2
3
-
-
-
4
5
6
7
8
PA2
-----
PA1
A2**
A1
...
PAIl
TMS32010
MEN
cs
liEN
AD7824*
AD7828··
iiil
07
087
DATA BUS
DO
D80
·UNEARCIRCUITRV
Tablell. Address Channel Selection
OMITTEOFORCLARlTV
··A2ISFORTHEAD78280NLY
Figure 18. AD78241AD7828- TMS32010lnterface
3-388 ANALOG-TO-DIGITAL CONVERTERS
AD7824/AD7828
+5V
Voo
CS
AIN 1
RD
AIN 2
•
AD7828
SPEECH
INPUT
DB7
AIN 7
DBO
A2
AIN 8
+5V
Al
V REF ! +)
V REF ! -)
AO
GND
Figure 19. Speech Analysis Using Real-Time Filtering
SAMPLE
PULSE
+5V
+15V
Lf
Voo
Voo
V nEF
AIN 1
AIN2
INT
VouTA
AIN 3
AIN4
+10V
VOUT B
DB7
AD7824
AD7226 VOUTC
DBO
V OUT 0
V RE .! +)
V RE .! -)
Al
Al
GND
AO
AO
DGND
AGND
Figure 20. 4-Channel Fast Infinite Sample-and-Hold
ANALOG-TO-DIGITAL CONVERTERS 3-389
3-390 ANALOG-TO-DIGITAL CONVERTERS
~ANALOG
WDEVICES
LC 2MOS
Complete, 12-Bit, 100kHz, Sampling ADC
AD7870 I
FEATURES
Complete Monolithic 12-Bit ADC with:
2,...s Track/Hold Amplifier
8,...s A/D Converter
On-Chip Reference
Laser-Trimmed Clock
Parallel. Byte and Serial Digital Interface
72dB SNR at 10kHz Input Frequency
57ns Data Access Time
Low Power - 60mW typ
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
AD7870FUNCTIONAL BLOCK DIAGRAM
REF OUT
AGND
cs
GENERAL DESCRIPTION
The AD7870 is a fast, complete, 12-bit AID converter. It consists of a tracklhold amplifier, 8ILs successive approximation
ADC, 3V buried Zener reference and versatile interface logic.
The ADC features a self-contained internal clock which is laser
trimmed to guarantee accurate control of conversion time. No
external clock timing components are required; the on-chip
clock may be overridden by an external clock if required.
The AD7870 offers a choice of three data output formats: a single, parallel, 12-bit word; two 8-bit bytes, or serial data. ~ast
bus access times and standard control inputs ensure easy mterfacing to modern microprocessors and digital signal processors.
The AD7870 operates from ±5V power supplies, accepts bipolar
input signals of ±3V and can convert full power signals up to
50kHz.
VIN
v..
r---~-C~--~r-,
iffi
iOSVl
DB"
iiiT
PRODUCT HIGHLIGHTS
1. Complete 12-bit ADC on a chip.
The AD7870 is the most complete monolithic ADC available
and combines a 12-bit ADC with internal clock, tracklhold
amplifier and reference on a single chip.
2. Dynamic specifications for DSP users.
The AD7870 is fully specified and tested for ac parameters,
including signal-to-noise ratio, harmonic distortion and intermodulation distortion. Key digital timing parameters are also
tested and guaranteed over the full operating temperature
range.
3. Fast microprocessor interface.
Data access times of 57ns make the AD7870 compatible with
modern 8- and 16-bit microprocessors and digital signal
processors.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7870 is also fully
specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio.
The AD7870 is fabricated in Analog Devices' linear compatible
CMOS (LC2 MOS) process, a mixed technology process that
combines precision bipolar circuits with low power CMOS logic.
The part is available in a 24-pin, 0.3 inch-wide, plastic or hermetic dual-in-Iine package (DIP) and in a 28-pin plastic leaded
chip carrier (PLCC).
ANALOG-TO-D/GITAL CONVERTERS 3-391
±5%, Vss= -5V ±5%, AGND =DGND =OV, f =2.5MHz external, unless otherwise
SPECIFICATIONS (Vstated.= +5V
All Specifications T to T unless otherwise noted.)
DD
cLK
min
Parameter
D\'IIIAMIC PERFORMANCE2
Signal to Noise Ratio' (SNR)
@ +2S"C
T .... toT_
Total Harmonic Distonion (THD)
Peak Harmonic or Spurious Noise
Intennodulation Distortion (IMD)
Second Order Terms
Third Order Terms
TrackIHold Acquisition Time
DC ACCURACY
Resolution
Minimum Resolution for which
No Missing Codes are Guaranteed
Integral Nonlinearity
Integral Nonlinearity
Differenriai Noniinearity
Bipolar Zero Error
Positive Full Scale Error'
Negative Full Scale Error'
ANALOG INPUT
Input Voltage Range
Input Current
REFERENCE OUTPUT
REF OUT @ +25"C
REF OUT Tempco
Reference Load Sensitivity
(~REF OVT/~I)
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN_
Input Current (l2/8/CLK Input Only)
Input Capacitance, CIN
,
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
DBIl-DBO
Floating-State Leakage Current
.Floating-State Output Capacitance'
CONVERSION TIME
External Clock (fCLK = 2.5MHz)
Internal Clock
POWER REQUIREMENTS
Voo
Vss
100
Iss
Power Dissipation
max
I, A'
K,B'
L,C'
S'
T'
Vaits
Test Conditions/Comments
70
70
70
70
72
71
70
70
-so
-so
-so
-80
70
70
-SO
dB min
dB min
dB max
-so
-80
-80
-80
-so
dB max
VIN = 10kHz Sine Wave, fSAMPLE = 100kHz
Typically 71.5dB for 0 -------~
DATA
DB7-0BO
;
_ J
f\
11---1.
, :':-;I~" --11--.-1-.....'....."
_I
,
,
~..1
,
,
\. J
_ _---I
SDATA'
\
L~~~G
, ..
,
,
'-.I
-II;:
,
---r"""-''''''''''-"'T""T---r..----......,.---r-1---r-r--lr--r--F
I
,
,
\
,
\
,
,
,
\
,
\
,
\
,
,
I
'-oJ
~..I
L...1
,-..I
~)jY
SERIAL DATA
NOTES
'nMES t 2 • 13, ~. t .. and ~ ARE THE SAME FOR A HIGH BYTE READ
AS FOR A LOW BYTE READ.
2EXTERNAL 4.7kll PULL·UP RESISTOR.
aEXTERNAL 2kn PULL·UP RESISTOR
CONTINUOUS SCLK (DASHED UNE) WHEN 12/81CLK= -5V
NONCONTINUOUS WHEN 12/8/CLK=OV.
Figure 10. Mode 1 Timing Diagram, Byte or Serial Read
3-398 ANALOG-TO-DIGITAL CONVERTERS
\,. oJ
\....1
,-.,I
'-..I
""'oJ
--t I--_'_~_ _ _ _ _ _ _ _ __
AD7870
The Mode I timing diagram for byte and serial data is shown in
Figure 10. INT goes low at the end of conversion and is reset
high by the first falling edge of CS and RD. This first read at
the end of conversion can either access the low byte or high byte
of data depending on the status of HBEN (Figure 10 shows low
byte only for example). The diagram shows both a noncontinuously and a continuously running clock (dashed line).
MODE 2 INTERFACE
The second interface mode is achieved by hard wiring CONVST
low and conversion is initiated by taking CS low while HBEN is
low. The tracklhold amplifier goes into the hold mode on the
falling edge of CS. In this mode, the BUSY/INT pin assumes
its BUSY function. BUSY goes low at the start of conversion,
stays low during the conversion and returns high when the conversion is complete. It is normally used in parallel interfaces to
drive the microprocessor into aWAIT state for the duration of
conversion.
Figure II shows the Mode 2 timing diagram for the 12-bit
parallel data output format (l2/S/CLK = + SV). In this case, the
ADC behaves like slow memory. The major advantage of this
interface is that it allows the microprocessor to start conversion,
WAIT and then read data with a single READ instruction. The
_
cs
r-
~TRACKlHOLD
\
~
GOES INTO HOLD
·1"--1--~=t,-,=-=-; tco.v: :", ~:,===:·~Ir-r--
iiJSi
\
.~~-.jt'r-
~
THREE-8TATE
DATA
----===:..:....-----i,~
user does not have to worry about servicing interrupts or ensuring that software delays are long enough to avoid reading during
conversion.
The Mode 2 timing diagram for byte and serial data is shown in
Figure 12. For two-byte data read, the lower byte (DBO-DB7)
has to be accessed first since HBEN must be low to start conversion. The ADC behaves like slow memory for this first read,
but the second read to access the upper byte of data is a normal
read. Operation of the serial functions is identical between Mode
I and Mode 2. The timing diagram of Figure 12 shows both a
noncontinuously and a continuously running SCLK (dashed
line).
AD7870 DYNAMIC SPECIFICATIONS
The AD7870 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as
integral and differential nonlinearity. These ac specifications are
required for signal processing applications such as speech recognition, spectrum analysis and high speed modems. These applications require information on the ADC's effect on the spectral
content of the input signal. Hence, the parameters for which the
AD7870 is specified include SNR, harmonic dsistortion, intermodulation distortion and peak harmonics. These terms are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (FS/2) excluding dc. SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave input
is given by
DB11-DBO
SNR = (6.02N + 1. 76) dB
Figure ". Mode 2 Timing Diagram, 12-BitParallelRead
HBEN'
22a
W//1
II
- -~r--- ----r
~
1'~1-
J I-- '"
TRACK/HOLD
:
_
GOES 'NTO HOLD
"
J:"F=
(I)
where N is the number of bits. Thus for an ideal 12-bit converter, SNR = 74dB.
\
r-.. - j
/
H
'j'~-~I---~I-~~.'I~I
,'''-,--,---';.,,'1-r---1 ~ I
II
BUSY---~\'__ _ _ _ _ _ _ _ _ _~
-
-0{ "
.:..ST.:.;ATE~_ _ _ _ _ _ _ _ _ _ _-III-I---4.~
~~~~
OATA _ _T",HR;;:E::.E•
to
)>-I-----.....~
D87_080
0811-088
'" '\
--I,~----------4
-';r"T;-','-"-;"loT,.,
_J
SDATA'
\..J
I
\.J
'\
~G
'''~I--
~
I
\..J
,
.,
\....1
,
I
'-oJ
,
I
\-oJ
1
,
\..J
,
I
\..J
, ,
\"J
,
,
\..J
,
,
\..J
\
,
\..J
1--_'_"_ _ _ _ _ _ _ __
~~
SEA.ALDAlA
NOTES
'TIMES t .... t,._ and t..o ARE THE SAME FOR A HIGH BYTE READ
AS FOR A LOW BYTE READ.
:tEXTERNAl4.7kU PUll~UP RESISTOR.
'eXTERNAL ZkU PULL-UP RESISTOR
_
CONTtNUOUS SCLK {DASHED_LINEI WHEN 12/8/CLK=-5V
NONCONTlNUOUS WHEN 12/8/CLK=OV.
Figure 12. Mode 2 Timing Diagram, Byte or Serial Read
ANALOG-TO-DIGITAL CONVERTERS 3-399
The output spectrum from the ADC is evaluated by applying a
sine-wave signal of very low distortion to the VIN input which is
sampled at a 100kHz sampling rate. A Fast Fourier Transform
(FFT) plot is generated from which the SNR data can be obtained. Figure 13 shows a typical 2048 point FFT plot of the
AD7870KN with an input signal of 25kHz and a sampling frequency of 100kHz. The SNR obtained from this graph is
72.6dB. It should be noted that the harmonics are taken into
account when calculating the SNR.
Harmonic Distortion
Harmonic distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7870, total harmonic distortion
(THD) is defined as
THD
= 20 log Vvl+vl+vl+vl+V6 2
VI
where VI is the rms amplitude of the fundamental and V2 , V3 ,
V., V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the FFT plot of
the ADC output spectrum.
IntermoduJation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa± nfb where
m,n = 0,1,2,3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
terms include (fa + fb) and (fa - fb) while the third order terms
include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb).
INPUT FREQUENCY - 25kHz
SAMPLE FREQUENCV - 100kHz
SNR = 72.6dB
TA =25'1:
!lJ
~- •• ~--------------4---------------~
I
Using the CCIF standard where two input frequencies near the
top end of the input bandwidth are used, the second and third
order terms are of different significance. The second order terms
are usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental expressed in dBs. In this
case, the input consists of two, equal amplitude, low distortion
sine waves. Figure 15 shows a typical IMD plot for the
AD7870.
I-OO~--------------4----------------rl
50
FREQUENCY - kHz
Figure 13. AD7870FFTPIot
Effective Number of Bits
The formula given in (I) relates the SNR to the number of bits.
Rewriting the formula, as in (2), it is possible to get a measure
of performance expressed in effective number of bits (N).
INPUT FREQUENCIES
F1 =9.05kHz
f2=9.55kHz
SAMPLING FREQUENCY = 100kHz
TA=25°C
IMD
ALL TERMS =9O.06dB
N = SNR-1.76
6.02
(2)
2ND ORDER TERMS=92.73dB
3RD ORDER TERMS =93.45dB
The effective number of bits for a device can be calculated directly from its measured SNR.
Figure 14 shows a typical plot of effective number of bits versus
frequency for an AD7870KN with a sampling frequency of
100kHz. The effective number of bits typically falls between
11.7 and 11.85 corresponding to SNR figures of 72.2 and
73.ldB.
12.0
i
--------./
~
~ 11.5
50
FREQUENCY - kHz
m
~
z
11. 0
~
~
•
•o
1•.
Il;
10.
Figure 15. AD7870lMOPIot
SAMPLE FREQUENCY"" 100kHz
T.=25"C
INPUT FREQUENCY - kHz
50
Figure 14. EffectiveNumberofBitsvs. Frequency
3-400 ANALOG-TO-DIGITAL CONVERTERS
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to FS/2 and excluding de) to the rms value of the
fundamental. Normally, the value of this specification will be
AD7870
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor the peak
will be a noise peak.
AC Linearity Plot
When a sine wave of specified frequency is applied to the VIN
input of the AD7870 and several million samples are taken, a
histogram showing the frequency of occurrence of each of the
4096 ADC codes can be generated. From this histogram data it
is possible to generate an ac integrallineariry plot as shown in
Figure 16. This shows very good integral linearity performance
from the AD7870 at an input frequency of 25kHz. The absence
of large spikes in the plot shows good differential linearity. Simplified versions of the formulae used are outlined below.
D = Data Memory Address
ADC = AD7870 Address
Some applications may require that conversions be initiated by
the microprocessor rather than an external timer. One option is
to decode the AD7870 CONVST from the address bus so that a
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described earlier. Note, a read operation must not be attempted during conversion.
DMAI.
~---
_ _ _"""'_ _- ,
DMAO
ADSp·2100
INLlil = [Viii - Viol .4096]-i
V(fsl - Viol
where INL(i) is the integral linearity at code i. V(fs) and yeo)
are the estimated full scale and offset transitions and V(i) is the
estimated transition for the ith code.
IRQn
i - - - - - - - - i iiilSYlllilf
rnwmr-------~
V(i) the estimated code transition point is derived as follows:
A C [1T. cumlilJ
·
V 111=
- . os
N
DMD1.1-----...J
DMOO
'"ADDITlONAL PINS OMmED FOR CLARITY.
where A is the peak signal amplitude,
N is the number of histogram samples
and cum(i)=~i
n=O
Figure 17. AD7870-ADSP-2100 Parallel Interface
Vlnloccurrences
+0.5...------------------,
INPUT FREQUENCV = 25kHz
SAMPLE FREQUENCV == 100kHz
TA == +25'"C
..
~ +0.25
PA2
PAO
TMS32010
~
~
!
iiiT ....- - - - - - - i
iiilSYliiii'
DEN
iii
~ -0.25
Dl.I-_ _ _ _...J
-D .• L...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
DOr-----------'
' - -_ _.... '"ADDITIONAL PINS OMmED FOR CLARITY.
Figure 16. AD7870aclNLPlot
MICROPROCESSOR INTERFACE
The AD7870 has a wide variety of interfacing options. It offers
two operating modes and three data-output formats. Fast data
access times allow direct interfacing to most microprocessors
including the DSP processors.
Parallel Read Interfacing
Figures 17 to 19 show interfaces to the ADSP-2100, TMS32010
and the TMS32020 DSP processors. The AD7870 is operating
in Mode I, parallel read for all three interfaces. An external
timer controls conversion start asynchronously to the microprocessor. At the end of each conversion the ADC .BUSYlINT
interrupts the microprocessor. The conversion result is read
from the ADC with the following instruction:
Figure 18. AD7870-TMS32010 Interface
AI.
r--=__- -......---,
AO
TMS32020
iiiiTn i - - - - - - - - i
Siiii
RIW I-....o:.--...,L..J
ADSP-2100: MRO = DM(ADC)
TMS32010: IN D,ADC
TMS32020: IN D,ADC
MRO =ADSP-2100 MRO Register
D l . I - - - - - - :....
00
-ADDmDNAL PINS OMmEO FOfI CLARITV
Figure 19. AD7870-TMS32020 Interface
ANALOG-TO-DIGITAL CONVERTERS 3-401
•
Two Byte Read Interfacing
AD7870-68008 Interface
Figure 20 shows an 8-bit bus interface for the MC68008 microprocessor. For this interface, the AD7870 I2IS/CLK input is
tied to OV and DBlllHBEN pin is driven from the microprocessor least significant address bit. Conversion start control is provided by the microprocessor. In this interface example, a Move
A.S
are gated off when the AD7870 is not performing a conversion.
During conversion, data is valid on the SDATA output of the
AD7870 and is clocked into the receive data shift register of the
DSPS6000. When this register has received 16 bits of data, it
generates an internal interrupt on the DSPS6000 to read the
data from the register.
AD7870·
1----....
ADDRESS BUS
AU
CONVST
r-----:-:-r-.J
DSP56000
MC88008
12/iJCLK
SCK
t--+---...:...._-........,
VON
'O.F¥o.'.F
C4
C3
.&
~-~
ABfll',~~ -~'VC4 M IC'
121i1CLK ~
IC2
AD7870
elK
SKT3
_____-;r__-t___E..,;C_E·'022
-5V
.:~w
V+
V-
:
lK2
. 11
II-
:
A ...
AI':.~U~
'~'.¥o'i'F
lKl
SKT2
OON'VST
ClK
:!:3V
CO~VST
~~:"O[
'1
5V
"R2'J
.n~
5V
EDMACK
••
elK OUT
C6
II
"'fR4!R5~
~l~l~l~
iiiij+-
07
ElROD
BUSYJffiITr-t-~---r-,---t--t----t----t-;-i--;--t~OM~O'~51A9
AGND
r-t-~--+-+"""1--+_+----+_---+_I-+__I-+---I B11
DOlO/55mB t-+-.....--+-+-I---,r-+-+---l,-+----+~-+--I-+-;:.OM:'::-o,..,-i 0'2
DB11/HBEN
DMD14
1-+--1---+--+-t---1r-+--+"""1--+--+-----+--.....-t-+---t ."
1-+--1-__+--+-t---1I-+-+_1+-""'f"_1+--+--""'f"_--+___-oo--t_O_M_O..' 2"1 B"
I I I 1
OM011
o::~~::[j~D>-+-~7"~7"~-r7..L;'L"+"":Lirl"'?L~'L:::.'""L,..L'L:::.rrIO~AJ,.TIA"'o.L,uIs-J/:. .,I~ . .,:L: -'" :L. .,'L: :~'L: :. .,~ 'L: :~'L: :~:L: ;:'L: : :L: -:L: =:L: -~ ": L: ;":O~r047i :: A32
DB9/SCLK
OGNO
':'
V-
IN
OUT
IC3
79105
GNO
:C~7:::L:t:!:,-CB-::SK:T~41~25~'~261~5~23J:.2'~~~_'~5~3=~~0~'2~11~~,1=~21=~,'.Q'~II ~
5V
lDI1F'~O'lI1F
I
SILK
!~
~ ISKT5
~NO
SERIAL
COMMUNICATIONS
PORT
v-o
SCREEN
GNDo
V+o
.-~
lC~
CBA
°DO+IL!JC~
LK~
C41il1:
+IL!J 0
03
:
0
0000000000000
0000000000000
0000000000000
8+
l03 71L!J
.0000.00.0.0.
081L!J
0000000000000
•••••••••••••
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0000000000000
0
0
Ice
SKTe
CONVBT
~
t= t=
B A
B A
0 0 0
1000
1 1 1 00
00
LK3.LK",
0
0
"~O
"~O
"~o
0
0
0
000
I
0
00
000
.LKe.
o
o/;]
0
• • • o·
0
0
0
0
00
C18 •
0
0000000
~0000000 0
rC4
LKS
+
r
C9
U<6 LK7
0000000
~f
0000000
lOS
0
0
00
~ 1:11:11:1
BRD
06~OS
000000000000
•
8KTS
00000
0000
•
~
~r-;-;-
t--
~ooo
0
1:1o 0+
000
o BA
"00
AD 787"
EVALUATION
IilI 0"
000000000000
"':0-0
•
~
Figure 27. Data Acquisition Circuit Using the AD7870
VlN~ IilI
81(T.1
2
II
PARALLEL
COMMUNICATIONS
PORT
--
I •
v"
DBB/SDATA
"
000
000
000
000
000
000
000
000
......
-...
"
...
00
:.:
00
8KT4
00
000
00
000
00
000
00
000
00
000
00
00
00
00
00
00
00
00
"5 ~OO "6
00
00 ' - - 000
+
00
00
0
0
000
00
0
0
0
00
00
•
C1e
O~~
0 •••
00
00
00
~ 1:1
~OLK
BKT.3
000 3" 0 l ! .
• •-
FIgure 28. PCB Sllkscreen for FIgure 27
ANALOG-TO-DIGITAL CONVERTERS 3-405
3.94"
(100mm)
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
•••••••••••••
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•••••••••••••
•••••••••••••
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•••••••••••••
.
.
.
.
.
.
.
1
•••
•••
•••
•••
•••
•• ••
•• ••
••
•• ••
••
••
•• ••
••
•• ••
••
••• ••
••
•• ••
••
••
• ••
••
••• ••
••
••
• ••
•••
•••
•
..
------=======..
Figure 29. PCB Component Side Layout for Figure 27
• •
•••••••••••
•••••••
••••
•••••••
••••
•••••••
••••
•••••••
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••••
•••••••
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••••
•••••••
••••
••••••• ••••
••••••• ••••
••••••••••••
••••••••••••
••••••••••••
••••••••••••
••••••••••••
••••••••••••
••••••••••••
••••••••••••
••••••••••••
••••••••••••
Figure 30. PCB Solder Side· Layout for Figure 27
3-406 ANALOG-TO-DIGITAL CONVERTERS
1IIIIIIII ANALOG
WDEVICES
FEATURES
Complete Monolithic 14-Bit ADC
Twos Complement Coding
Parallel. Byte and Serial Digital Interface
82 dB SNR at 10 kHz Input Frequency
57 ns Data Access Time
Low Power - 60 mW typ
83 KSPS Throughput Rate
LC 2MOS
Complete 14-Bit, Sampling ADC
AD7871/AD7872 I
AD7871 FUNCTIONAL BLOCK DIAGRAM
REFOUT
AGND
V DD
VIN
•
APPLICATIONS
Digital Signal Processing
High Speed Modems
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
GENERAL DESCRIPTION
The AD7871 and AD7872 are fast, complete, 14-bit analog-todigital converters. They consist of a tracklhold amplifier,
successive-approximation ADC, 3 V buried Zener reference and
versatile interface logic. The ADC features a self-contained,
laser trimmed internal clock, so no external cleck timing components are required. The on-chip clock may be overridden to
synchronize ADC operation to the digital system for min·
noise.
CS
RD
BUSY!
OB13
DBO
DGND
Vss
Wi'
The AD7871 offers a choice of thr
gle, parallel, 14-bit word; two 8-bit
stream. The AD7872 is a serial ou
e
parts are capable of interfacing to all mod
and digital signal processors.
The AD7871 and AD7872 operate from ± 5 V power suppl
accept bipolar input signals of ± 3 V and can convert full po
signals up to 50 kHz.
In addition to the traditional dc accuracy specifications, the
AD7871 and AD7872 are also fully specified for dynamic performance parameters including distortion and signal-to-noise ratio.
Both devices are fabricated in Analog Devices' LC2 MOS mixed
technology process. The AD7871 is available in 28-pin plastic
DIP, hermetic DIP, LCCC and PLCC packages. The AD7872
is available in 16-pin plastic and hermetic DIP packages.
SsTRii
SCLK SDATA
DGND
Vss
PRODUCT HIGHLIGHTS
1. Complete 14-Bit ADC on a Chip.
2. Dynamic Specifications for DSP Users.
3. Low Power.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-407
V ±5%, Vss=-5 V ±5%, A6ND=D6ND=D v, fCUI=2 MHz external, FSAMPU:= 83 kHz unless
SPECIFICATIONS (Voo=+5
otherwise stated). All Specifications T to T unless otherwise noted.
min
max
I,A
Versions'
K,B
Version.'
T
Versionl
Units
Test ConditionsIComments
82
82
-86
82
82
-86
dB min
dB min
dB max
VIN =IO kHz Sine Wave
Total Harmonic Distortion (THO)
78
78
-84
Peak Harmonic or Spurious Noise
-86
-88
-88
dB max
Intennodulation Distortion (IMD)
Second Order Terms
Third Order Tenns
TrackIHold Acquisition Time
-85
-85
-85
-85
-85
-85
dB max
dB max
",smax
14
14
14
Bits
Bits
LSB typ
Parameter
DYNAMIC PERFORMANCE2
Signal to Noise Ratio' (SNR) @ 25'C
Tmin to Tmax
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity @ 25'C
Integra! Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Gain Error4
Negative Gain Error'
14
14
14
±1I2
±112
:t.l
±1I2
±IO
±IO
±I
±5
±5
VIN =IO kHz Sine Wave
THD Is Typically -90 dB for 0
0
0
~
0
8
: 3. ~ ~
0
0
0
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-412 ANALOG-TO-DIGITAL CONVERTERS
AD78711AD7872
CONVERTER DETAILS
The AD78711AD7872 is a complete 14-bit AJD converter,
requiring no external components apart from power supply
decoupling capacitors. It is comprised of a 14-bit successive
approximation ADC based on a fast settling voltage-output
DAC, a high speed comparator and CMOS SAR, a tracklhold
amplifier, a 3 V buried Zener reference, a clock oscillator and
control logic.
ANALOG INPUT
Figure 4 shows the AD78711AD7872 analog input. The analog
input range is ± 3 V into an input resistance of typically 15 kil.
The designed code transitions occur midway between successive
integer LSB values (i.e., 112 LSB, 3/2 LSBs, 5/2 LSBs ... FS
- 3/2 LSBs). The output code is 2s complement binary with
1 LSB=FS/16384=6 V/16384=366 I1V. Ti).e ideal input!
output transfer function is shown in Figure 5.
INTERNAL REFERENCE
The AD78711AD7872 has an on-chip temperarure compensated
buried Zener reference which is factory trimmed to 3 V
±10 mV. Internally it provides both the DAC reference and the
dc bias required for bipolar operation. The reference output is
available (REF OUT) and is capable of providing up to 500 I1A
to an external load.
II
TO INTERNAL
3 V REFERENCE
The maximum recommended capacitance on REF OUT for normal operation is 50 pF. If the reference is required for use
external to the AD78711AD7872, it should be decoupled with a
200 il resistor in series with a parallel combination of a 10 I1F
tantalum capacitor and a 0.1 I1F ceramic capacitor. T~
decoupJing components are required to remQ,~;voliage
caused by the AD78711AD7872 .
~
,,'~
lP
v••
000 ... 001
000 ... 000
111 ... 111
REF OUT
~i
111 ... 110
1
Figure 3. AD7B71IAD7B72 Reference Circuit
TRACK-AND-HOLD AMPLIFIER
The track-and-hold amplifier on the analog input of the
AD78711AD7872 allows the ADC to accurately convert an input
sine wave of 6 V peak-peak amplitude to 14-bit accuracy. The
input bandwidth of the tracklhold amplifier is much greater
than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate. The wide bandwidth of
the tracklhold allows the high frequency operation. The 0.1 dB
cutoff frequency occurs typically at 500 kHz. The track/hold
amplifier acquires an input signal to 14-bit accuracy in less than
2 I1S. The overall throughput rate is determined by the conversion time plus the tracklhold amplifier acquisition time. For
a 2 MHz input clock the throughput time is 12 I1S max.
The operation of the tracklhold amplifier is essentially transparent to the user. The track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion. If the
CONVST input is used to start conversion, then the track to
hold transition occurs on the rising edge of CONVST. If CS
on the AD7871 starts conversion, this transition occurs on the
falling edge of CS.
100 ... 001
100 ... 000
1
r
Jr
I
~j
-----f~+:S_1LSB
FS=6V
r
1 LSB = 1::84
OV
INPUT VOLTAGE
Figure 5. Bipolar Input/Output Transfer Function
BIPOLAR OFFSET AND FULL SCALE ADJUSTMENT
When the AD78711AD7872's offset and full scale errors need to
be adjusted, offset error must be adjusted first. This is achieved
by trimming the offset of the op amp driving the analog input of
the AD78711AD7872 while the input voltage is 112 LSB below
AGND. The trim procedure is as follows: apply a voltage of
-0.183 mV (-112 LSB) at VI in Figure 6 and adjust the op
amp offset voltage until the ADC output code flickers between
11 1111 1111 1111 and 00 0000 0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows
(see Figure 6).
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-413
Positive Full Scale Adjust
Apply a voltage of 2.9995 V (FS/2 -3/2 LSBs) at Vl and adjust
R2 until the ADC output code flickers between 01 1111 1111
1110 and 0111111111 1111.
Negative Full Scale Adjust
Apply a voltage of -2.9998 V (-FS/2+ 112 LSB) at Vl and
adjust R2 until the ADC output code flickers between 10 0000
00000000 and 10 0000 0000 0001.
UNIPOLAR OFFSET AND FULL-SCALE ADJUSTMENT
When absolute accuracy is required, offset and full scale error
can be adjusted to zero. Offset must be adjusted before full
scale. This is achieved by applying an input voltage of (112 LSB)
to V 1 and adjust R6 until the ADC output code flickers between
100000 0000 0000 and 1000000000 0001. For full scale adjustment apply an input voltage of (FS-3/2 LSBs) to Vl and adjust
R5 until the output code flickers between 01 1111 1111 1110
and 01 1111 1111 1111.
Rl
10kO
V, O--'WIf-.,
011 ... 111
INPUT RANGE = =3 V
OUTPUT
CODE
011 ... 110
011 ... 101
011 ... 100
V'N
AD7871 I
AD7872*
100 ... 011
100 ... 010
FS = 5 V 1100 V)
lLSB=~
16384
+FS -1 LSB
V,. INPUT VOLTAGE
Figure 6. Bipolar
UNIPOLAR OPERATION
A typical unipolar circuit is shown in Fi
AD7872 REF OUT is used to offset the
The analog input range is detennined by the ratio of R3 t
The minimum range with which the circuit will work is 0 t
+ 3 V. The resistor values are given in Figure 7 for input
s
of 0 to +5 V and 0 to + 10 V. R5 and R6 are included for offset
and full scale adjust only and should be omitted if adjustment is
not required.
The ideal input/output transfer function is shown in Figure 8.
The output can be converted to straight binary by inverting the
MSB.
R3
10k019.1 kfl)
V,O--'W~,
INPUT
RANGE = 0 TO +5 V
10) TO +10V)
R5
2000
V'N
R6
1000
R4
15 kO 13.9 kO)
AD78711
AD7872*
L
Ycle normally consists of 19 clock periods. The
n time for both external and internal clock can vary
clock cycles depending on the conversion start to
ronization. If a conversion is initiated within
to a rising edge of the ADC clock, the conversion
tlme will consist of 20 clock cycles.
There are two basic operating modes for the AD7871. In the
first mode (Mode 1) the CONVST line is used to start conversion and drive the tracklhold into its hold mode. At the end of
conversion the tracklhold returns to its tracking mode. It is
intended principally for digital signal processing and other applications where precise sampling in time is required. In these
applications, it is important that the signal sampling occurs at
exactly equal intervals to minimize errors due to sampling
uncertainty or jitter. For these cases the CONVST line is driven
by a timer or some precise clock source.
The second mode is achieved by hard-wiring the CONVST line
low. This mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data. CS and RD start conversion and the microprocessor will normally be driven into a
WAIT state for the duration of conversion by BUSYIINT.
The AD7872 has one operating mode only. This is Mode I,
described above, which uses CONVST to start conversion.
REF OUT
AGND
"ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. AD7871IAD7872 Unipolar Circuit
DATA OUTPUT FORMATS
The AD7871 offers a choice of three data output formats, one
serial and two parallel. The parallel data formats include a single
14-bit parallel word for 16-bit data buses and a two-byte format
for 8-bit data buses. The data format is controlled by the
14/8/CLK input. A logic high on this pin selects the 14-bit parallel output format only. A logic low or -5 V applied to this pin
allows the user access to either serial or byte formatted data.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-414 ANALOG-TO-DIGITAL CONVERTERS
AD7871/AD7872
Three of the pins previously assigned to the four MSBs in parallel form are now used for serial communications while the
fourth pin becomes a control input for the byte-formatted data.
The three possible data output formats can be selected in either
of the modes of operation.
The AD7872 is a serial output device only. The serial data format is exactly the same as the AD7871.
Parallel Output Format
The two parallel formats available on the AD7871 are a 14-bit
wide data word and a two-byte data word. In the first, all 14
bits of data are available at the same time on DB13 (MSB)
through DBO (LSB). In the second, two reads are required to
access the data. When this data format is selected, the DB131
HBEN pin assumes the HBEN function. HBEN selects which
byte of data is to be read from the AD7871. When HBEN is
low, the lower 8 bits of data are placed on the data bus during a
read operation; with HBEN high, the upper six bits of the 14bit word are placed on the data bus. These six bits are right justified and thereby occupy the lower six bits of the byte while the
upper two bits are zeros.
Serial Output Format
Serial data is available on the AD787
is at 0 V or -S V and in this
SCLK and DBIO/SDATA pins
The AD7872 is a serial output
Ice
on both devices is identical. Serial dat
version with a word length of 16 bits; 2
by the 14-bit conversion result starting
is synchronized to the serial clock output (SCLK) and
to
by the serial strobe (SSTRB). Data is clocked out on a
high transition of the serial clock and is valid on the falling edge
of this clock while the SSTRB output is low. SSTRB goes low
at the start of conversion and the first serial data bit (which is
the first leading zero) is valid on the first falling edge of SCLK.
All the serial lines are open-drain outputs and require external
pull-up resistors.
The serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, SCLK is
required during the serial transmission only. In these cases it
can be shut down (i.e., placed into three-state) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., TMS32020) require a
serial clock which runs continuously. Both options are available
on the AD7871 and AD7872. With the 14/8/CLK input on the
AD7871 at -S V, the serial clock (SCLK) runs continuously;
when 14/8/CLK is at 0 V, SCLK goes into three-state at the end
of transmission. The CONTROL pin on the AD7872 performs
the same function. When this is at 0 V, SCLK is noncontinuous
and when it is at -S V, SCLK is continuous.
MODE 1 INTERFACE
Conversion is initiated by a low going pulse on the CONVST
input. The rising edge of this CONVST pulse starts conversion
and drives the tracklhold amplifier into its hold mode. Note that
CS and RD should be high when CONVST is brought low. The
BUSY/INT status output assumes its INT function in this
mode. INT is normally high and goes low at the end of conversion. This INT line can be used to interrupt the microprocessor.
A read operation to the AD7871 accesses the data and the INT
line is reset high on the falling edge of CS and RD. The
CONVST input must be high when CS and RD are brought
low for the AD7871 to operate correctly in this mode. It is
important, especially in systems where the conversion start
(CONVST) pulse is asynchronous to the microprocessor, to
ensure that a parallel or byte data read is not attempted during
a conversion. Trying to read data during a conversion can
cause errors to the conversion in progress. Avoid pulsing the
CONVST line a second time before conversion end since it can
cause errors in the conversion result. In applications where precise sampling is not critical, the CONVST pulse can be generated from microprocessor WR line OR-gated with the AD7871
CS input.
Figure 9 shows the Mode I timing diagram for a 14-bit parallel
data output format (14I8/CLK=+S V). A read to the AD7871 at
the end of conversion accesses all 14 bits of data at the same
available for this data output format.
time. Serial
~
-----'-------411'
"U
4
' It:
I
io-----~ONVEm~
THREE-STATE
DATA
.,
"--I fVii:ii\'
t:: I ___
~
0811-080
Figure 9. Mode 1 Timing Diagram, 14-8it Parallel Read
The Mode I function timing diagram for byte and serial data is
shown in Figure 10. INT goes low at the end of conversion and
is reset high by the first falling edge of CS and RD. This first
read at the end of conversion can either access the low byte or
high byte of data depending on the status of HBEN (Figure 10
shows low byte for example only). The diagram shows both the
SCLK output going into three-state at the end of transmission
and a continuously running clock (dashed line).
MODE 2 INTERFACE
The second interface mode is achieved by hard-wiring CONVST
low and conversion is initiated by taking CS low while HBEN is
low. The tracklhold amplifier goes into the hold mode on the
falling edge of CS. In this mode the BUSYIINT pin assumes
its BUSY function. BUSY goes low at the start of conversion,
stays low during the conversion and returns high when the conversion is complete. It is normally used in parallel interfaces to
drive the microprocessor into aWAIT state for the duration of
conversion.
Figure 11 shows the Mode 2 timing diagram for the 14-bit parallel data output format (14/8/CLK=+S V). In this case the
ADC behaves like slow memory. The major advantage of this
interface is that it allows the microprocessor to start conversion,
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-415
II
-- ,
CONVST
~"--lL
~
TRACK/HOlD
GOESINTOHQLD
I
,~
~~~~"~'~~~~~~~-r~~
! ' , '. !
'\
SCLK3
.
-~~~~'~~"
i.., i, I
_.I
I
\...1
\...1
----i
.,,---l~
1
,
,
I
'-.I
'-.I
,
,
\...1
,
,
\....1
,
,
,
,
\...1
'-..I
,
,
\....1
'.
__
'-.I
__
~
I
SDATA
_I
--tl--~.,,----------
SERIAl DATA
NOTES
'TIMES t 2 • ~ t4. t., AND t. ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
2EXTEANAL 4.7 kfi PULL·UP RESISTOR.
_
3EXTERNAL 2 kfi PUll-UP RESISTOR. CONTINUOUS SCJ.K (DASHED UNEI WHEN 141B/CLK
_
=-5 V NONCONTINJ,JOUS WHEN 14/B/CLK = 0 V.
WAIT and then read data with a single READ instr
user does not have to worry about servici
ing that software delays are long enough
during conversion.
The Mode 2 timing diagram for byte and serial ~
Figure 12. For two-byte data read, the lower byte
has to be accessed first since HBEN must be low t t conversion. The ADC behaves like slow memory for this first read,
but the second read to access the upper byte of data is a normal
read. Operation to the serial functions is identical between Mode
I and Mode 2. Once again, the timing diagram of Figure 12
shows SCLK going into three-state or running continuously
(dashed line).
Figure ". Mode 2 Timing Diagram, 14-Bit Parallel Read
DB7DBO
SCLK'
r\
,,--J
I
r- ,
-..---r~·Tl--l,
I ,
,
_.I
,
Ii
\..J
r- ~ '" t::--I'-~i----r"T"
d7iJVLr\JVLJ\
.,,--11----lr-r-'_"_ _ _ _ _ _ _ __
2EJ
,
,
\...1
L.J
,
-r-T---r-I"""'T"T"""'I--'-'r"'T"-r-T---r"r-r-T"""T
I
,
, ,
t
, , I ,
, ,
\ I , I ,
I
\....1
'-..I
\..J
\..J
'-.I L.J L.J
\....1
,.I
I
SERIAL DATA
NOTES
'TIMES t, &. t. •. t,9' AND 120 ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
~~~:~~!':~:: ~iWttEN 12/i/eLK '" -6 V NONCONTINUOUS WHEN 12/8/CLK '" 0 V. EXTERNAL 2 kO PULL·UP RESISTOR.
Figure 12. Mode 2 Timing Diagram, Byte or Serial Read
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligati.on regarding future manufacture unless otherwise agreed to in writing.
3-416 ANALOG-TO-DIGITAL CONVERTERS
AD78711AD7872
NUCROPROCESSORINTERFACE
The AD7871 and AD7872 have a wide variety of interfacing
options. The AD7871 offers two operating modes and three
data-output formats, while the AD7872 is a dedicated serial output device. The fast data access times on the parallel modes of
the AD7871 allow interfacing to the very fast DSPs. The serial
mode on both the AD7871 and AD7872 is compatible with the
serial port structures on all the popular DSPs.
Parallel Read Interfacing
Figures 13 and 14 show interfaces to the ADSP-2100 and the
TMS32020/C25 DSP processors. The AD7871 is operating in
Mode 1, parallel read for both interfaces. An external timer controls conversion start asynchronously to the microprocessor. At
the end of each conversion the ADC BUSYIINT interrupts the
microprocessor and the conversion result is read from the ADC
with the following instruction:
A15r----------------L-------,
AO
TMS32020/C25
INTn
1+------------------1
STRB
RIW r - - " - - - - - i . .__~
DB13
ADSP-2100 MRO = DM(ADC)
TMS32020/C25: IN D,ADC
MRO = ADSP-2100 MRO Register
D = Data Memory Address
can continue to use its parallel bus regardless
7872. The interfaces show a timer driving
ut this could be generated from a decoded
ADC = AD7871 Address
DSP56000 Serial Interface
DMA14r----------------L~-
DMAO
ADSP-2100
AD7871*
14/8/CLK
IRQn I-----------------~ BUSV/INT
liD
DMRD
DB13
DMD15 r-----------....I
DMDOr------------------------J
*ADDITIONAl PINS OMITTED FOR CLARITY.
Figure 13. AD7871 to ADSP-2100 Parallel Interface
Some applications may require that conversions be initiated by
the microprocessor rather than an external timer. One option is
to decode the AD7871 CONVST from the address bus so that a
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described earlier. Note, a read operation must not be attempted during conversion.
Serial Interfacing
Both the AD7871 and the AD7872 have an identical serial interface. The diagrams that follow show the AD7872 interfaces only
but the AD7871 could just as easily be used in these circuits.
Figures 15, 16 and 17 show the AD7872 connected to three
popular DSP's. In all three interfaces, CONVST is used to start
conversion since this does not activate the parallel bus. Thus,
shows a serial interface between the AD7872 and the
. The interface arrangement is two-wire with the
7872 configured for non-continuous clock operation
(l4/8/CLK=O V). The DSP56000 is configured for Normal
Mode Synchronous Operation with Gated Clock. It is also set up
for a 16-bit word with SCK and SC2 as inputs and the FSL
control bit set to a O. In this configuration, the DSP56000
assumes valid data on the first falling edge of SCK. Since the
AD7872 provides valid data on this first edge there is no need
for a strobe or framing pulse for the data. SCLK and SDATA
are three-stated when the AD7872 is not performing a conversion. During conversion data is valid on the SDAT A output of
the AD7872 and is clocked into the Receive Data Shift Register
of the DSP56000. When this register has received 16 bits of
data, it generates an internal interrupt on the DSP56000 to read
the data from the register.
The DSP56000 and AD7872 can also be configured for continuous clock operation. In this case a strobe pulse is required by
the DSP56000 to inqicate when data is valid. The SSTRB output of the AD7872 is inverted and applied to the SC2 input of
the DSP56000 to provide this strobe pulse. All other conditions
and connections are the same as for the gated clock operation.
AD7872*
CONVST
DSP56000
SCK
CONTROL
1-+--.....------------1 SCLK
SRD
SDATA
*ADDITIONAL PINS OMITTED FOR CLARfTY.
Figure 15. AD7872 to DSP56000 Interface
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
ANALOG-TO-DIGITAL CONVERTERS 3-417
11
AD7872 - TMS32020lC25 Serial Interface
Figure 16 shows a serial interface between the AD7872 and the
TMS32020/C25. The AD7872 is configured for continuous clock
operation. Note, the ADC will not interface correctly to the
TMS32020/C25 if it is confIgured for a non-continuous clock.
Data is clocked into the Data Receive Register (DRR) of the
TMS32020/C25 during conversion. As with the previous interfaces, when a 16-bit word is received by the DSP it generates an
internal interrupt to read the dat;! from the DRR.
+5V
AD7872*
CONVST
ADSP·21011
ADSp·2102
RFS
CONTROL
4.7kll
2kll
1---+-+-+----1 SSTRB
SCLK
SCLK
DR
SDATA
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD7872*
+5V
CONVST
TMS32020/C25
CONTROL
4.7 kO
2kO
FSR
SSTRB
CLKR
SCLK
DR
SDATA
Figure 17. AD7872-ADSP-2101IADSP-2102 Serial Interface
STAND·ALONE OPERATION
The AD7871 can be used in its Mode 2, parallel mode for
stand-alone operation. In this case, conversion is initiated with a
pulse to the CS input. This pulse must be longer than the conversion time of the ADC. The BUSY output is used to drive the
RD input. Data is latched from the AD7871 DBO - DBI1 outputs to an external latch on the rising edge of BUSY.
*ADDfTlONAL PINS OMITTED FOR CLARITY.
Figure 16. AD7872 to TMS32020/C25 Interface
AD7872 - ADSP-2101IADSP-2102 Serial Interface
Figure 17 shows a serial interface between the AD78
ADSP-21OIIADSP-2102 DSP Microco
confIgured for continuous clock op
the serial port register of the micr
As with the previous interfaces, wh
received by the ADSP-21OIIADSP-2102
sor interrupt is generated and the data is rea
port register.
(PCB) layout is as important as the
high speed AID performance.
is requited to make bit decisions on an
us, the designer has to be conscious of
If and in the preceding analog cirower supplies are not recommended as
spikes will feed through to the comparator causing
sitions. Other causes of concern are ground loops
dthrough from microprocessors. These are factors
any ADC, and a proper PCB layout which mineffects is essential for best performance.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-418 ANALOG-TO-DIGITAL CONVERTERS
1IIIIIIII ANALOG
WDEVICES
LC 2MOS Complete 12-Bit
100kHz Sampling ADC with DSP Interface
AD7878 I
FEATURES
Complete ADC with DSP Interface, Comprising:
Track/Hold Amplifier with 2....s Acquisition Time
7 ....s AID Converter
3V Zener Reference
B-Word FIFO and Interface Logic
72dB SNR at 10kHz Input Frequency
Interfaces to High Speed DSP Processors, e.g.,
ADSP-2100, TMS32010, TMS32020
41 ns max Data Access Time
low Power, 60mW typ
AD7878 FUNCTIONAL BLOCK DIAGRAM
11
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
DGND
GENERAL DESCRIPTION
The AD7878 is a fast complete 12-bit AID converter with a
versatile DSP interface consisting of an 8-word, first-in, first-out
(FIFO) memory and associated control logic.
The FIFO memory allows up to eight samples to be digitized
before the microprocessor is required to servic<: the AID converter.
The eight words can then be read out of the FIFO at maximum
microprocessor speed. A fast data access time of 41ns allows
direct interfacing·to DSP processors and high speed 16-bit
microprocessors.
An on-chip statuslcontrol register allows the user to program the
effective length of the FIFO and contains the FIFO out of
range, FIFO empty and FIFO word count information.
The analog input of the AD7878 has a bipolar range of ± 3V.
The AD7878 can convert full power signals up to 50kHz and is
fully specified for dynamic parameters such as signal-to-noise
ratio and harmonic distortion.
The AD7878 is fabricated in Linear Compatible CMOS
(LC2 MOS), an advanced, mixed technology process that combines
precision bipolar circuits with low power CMOS logic. The part
is available in four package styles, 28-pin plastic and hermetic
dual-in-line package (DIP), leadless ceramic chip carrier (LCCC)
or plastic leaded chip carrier (PLCC).
DB11
DB.
v.s
PRODUCT HIGHLIGHTS
I. Complete AID Function with DSP Interface
The AD7878 provides the complete function for digitizing ac
signals to 12-bit accuracy. The part features an on-chip track!
hold, on-chip reference and 12-bit AID converter. The additional feature of an 8-word FIFO reduces the high software
overheads associated with servicing interrupts in DSP
processors.
2. Dynamic Specifications for DSP Users
The AD7878 is fully specified and tested for ac parameters,
including signal-to-noise ratio, harmonic distortion and intermodulation distortion. Key digital timing parameters are also
tested and specified over the full operating temperature
range.
3. Fast Microprocessor Interface
Data access time of 41ns is the fastest ever achieved in a
monolithic AID converter and makes the AD7878 compatible
with all modern 16-bit microprocessors and digital signal
processors.
ANALOG-TO-DIGITAL CONVERTERS 3-419
=
= +5Y ±5%, = -5Y ±5%,AGND = DGND = DY,fcLI( =BMHz.
SPECIFICATIONS tvPOAll Specifications
Tmin to Tmax unless othelWlse noted.)
~5Y.±5%,ycc
Y~
l,A
K,L,B
S
Versions'
Versions
Version
Units
Test Conditions/Comments
Total Harmonic Distortion (THD)
70
70
-SO
72
71
-SO
70
70
-SO
dB min
dB min
dB max
Peak Harmonic or Spurious Noise
-SO
-SO
-SO
dB max
V IN = 10kHz sine wave, fSAMPl.E = 100kHz
Typically 71.5dB for O
140
VH
~
A W
8#
/./'/J/
.Ff/ JY
150
,~/
"
iJI
P
0
I {f
'[
JJ
JJ
'I
'J
'/
!II / 'J
0
70
I'J
60
50
I
+VREF
-VREF,""OV
II
I
/I / /.
'/i ///
L. 1///
~ K/
40
0
0
0
-150
/if
.' r/ 1
130
120
20
-
OV
VH =3V
- - - VH=FLOATING f""1.3V)
~~
-100
".
-50
AIN
50
(il
100
ISO
COMPARATOR INPUT- mV
Comparator Switching vs. Hysteresis Voltage
Layout Considerations
The AD9000, like all high-speed circuits, requires certain precautions be taken to insure optimum performance. The foremost
of these is the use of a substantial low impedance ground plane
around and under the AD9000. Just as important are high quality
ground connections to the AD9000 itself. It is probably more
effective to keep the analog and digital grounds separate, except
at the AD9000 where they should be connected together. Sockets
should generally be avoided due to the increased interlead capacitance they induce. If socketing must be used, pin sockets are
preferred.
Decoupling is especially important to high-speed analog circuits.
Each supply should be decoupled to ground with O.lfLF ceramic
and O.OOlfLF mica capacitors. The ladder reference pins should
be treated iii a similar manner. In addition to decoupling the
reference ladder, the reference ladder should be driven from a
low output impedance source for the best noise rejection. In all
cases, chip capacitors are recommended, where practical, to
reduce the effects of lead inductance associated with standard
discrete capacitors.
MIL-STD-883 Compliance Information
The AD9000SElSD/883C are classified within microcircuits
group 57-technology group D (bipolar AID converters), and are
constructed in accordance with the latest revision of MIL-STD883. The AD9000 is electrostatic sensitive and falls within electrostatic sensitivity classification Category A. PDA (Percent
Defective Allowance) is computed based of Subgroups I of the
specified Group A test list. QA screening is in accordance with
"Alternate Method A" of method 5005. The following apply:
Bum-In per lOIS, Life Test per 1005, Electrical Testing per
5004. (Note: Group A electrical Testing assumes TA=Tc=TJ .)
ANALOG-TO-DIGITAL CONVERTERS 3-439
TYPICAL APPLICATION
The AD9000 is a relatively flexible device which can be configured
in a number of ways. One very useful feature of the AD9000 is
the open emitter outputs. The open emitters allow the outputs
of several AD9000s to be OR-WIRED in stacking applications
for increased resolution. This kind of application depends on
the return-to-zero nature of the output bits when AIN"" + VREF
(overflow). In circuits which employ only one AD9000, this is
not always an advantage. The circuit below illustrates one method
of converting the outputs to nonreturn-to-zero.
The 10197 (standard 10K EeL logic) hex-AND group senses
the active OVERFLOW output and forces all other bits to logic
HIGH. The 10151 latch is not required for AD9000 applications,
but it may ease data transfer sensitivities in asnychronous data
collection systems.
The reference driver circuits should provide a low source impedance to prevent noise on the reference inputs from affecting
the AD9000's accuracy. This is accomplished to a large extent
by adequately decoupling the reference pins to ground. An
improved method is employed below. The reference voltages
(+ VREF, - VREF) are buffered by a transistor/amplifier combination. This has the advantages of wide bandwidth (hence low
impedance over a wide frequency range to eliminate high frequency
noise components), and improved temperature stability.
+VREF
10197
CAPACITORS
0.1 ...F
-4:-VREF
-VREF
1k
VH
2k
+VREF
(MSB)
BIT1
(MSB) BIT 1
-
BIT 2
BIT 2
AD9000
BIT 3
BIT 3
100151
BIT 4
ANALOG
INPUT
'":'
LATCH
DATA
OUTPUTS
BIT 5
BIT 5
A'N
BIT 4
BIT 6
(LSB)
(lSB) BIT 6
ENCODE
ENCODE
All ECl OUTPUTS TERMINATED TO
-2.0V THROUGH 1000 RESISTORS
DIE LAYOUT
MECHANICAL INFORMATION
Die Dimensions
Pad Dimensions
Metallzation
Backing
Substrate Potential
Passivation
Die Attach
Bond Wire
3-440 ANALOG-TO-DIGITAL CONVERTERS
129x217x 15 (±2)mils
4x4mils
10,OOOAAluminum
None
-Vs
lo,oooA Oxynitride
Gold Eutectic
1.25 mil Aluminum; Ultrasonic Bonding
or lmil Gold; Gold Ball Bonding
AD9000
+5.0V
-5.2V
0.1 ..F
~r+Vs
100
~
OVERFLOW
AD1
AD2
..L
-Vs
AtN
BIT 1 (MSB)
1k
ENCODE
BIT 2
II
BIT 3
2 . 0 V - -VREF
BIT 4
BITS
r---
+VREF
BIT 6 (LSB)
LOAD RESISTORS
DIGITAL
GROUND
11K
ANALOG
GROUND
-
...
ALL RESISTORS ± 5%
ALL CAPACITORS ±20%
ALL SUPPLY VOLTAGES ±5%
OPTION #1: (STATIC) ADI=O.OV, AD2=LOGIC HIGH
OPTION #2: (DYNAMIC) SEE WAVEFORMS
-OV
-2.0V
V HIGH
VLOW
Burn-In Test Circuit
ANALOG-TO-DIGITAL CONVERTERS 3-441
AD90001PCB EVALUATION AND TEST BOARD
Evaluating and testing the AD9000 is greatly simplified with the
AD9000IPCB evaluation board. The printed circuit board contains
all of the driver and buffering circuits needed to test and evaluate
the. AD9000. The board outputs include both a high quality
reconstructed representation of the input waveform, and a dc
error waveform output which can be used to determine device
linearities.
Inputs to the AD9000/PCB evaluation board include the analog
signal to be digitized, as well as an optional ENCODE input for
high stability measurements. All components, except the AD9000,
are soldered onto the 8.S" x 6.3" board. The AD9000 is socketed
to facilitate moderate volume testing. The evaluation board is
offered with either a commercial temperature range AD9000, or
an extended temperature range device installed.
The respective ordering numbers are AD9000JDIPCB and
AD9000SDIPCB.
ERROR
OUTPUT
ANALOG
IN
0----1
~
9
I
RECONSTRUCTION
DIA
AD9000
AID
RECONSTRUCTED
ANALOG
+5V
~
ADJUSTABLE
DELAY
VARIABLE
OSCILLATOR
ENCODEO______________
PULSE
~j
AD9000/PCB Block Diagram
3-442 ANALOG-TO-DIGITAL CONVERTERS
ANALOG
OUTPUT
High Speed a-Bit
Monolithic AID Converter
AD9002 I
1IIIIIIII ANALOG
WDEVICES
AD9002 FUNCTIONAL BLOCK DIAGRAM
FEATURES
150MSPS Encode Rate
Low Input Capacitance: 17pF
Low Power: 750mW
- 5.2V Single Supply
OVERFLOW
INHIBIT
ANALOG IN
OVERFLOW
APPLICATIONS
Radar Systems
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM. ECCM. ESM)
Communication/Signal Intelligence
BIT 8 (MSB)
81T 5
BIT 4
BIT 3
GENERAL DESCRIPTION
The AD9002 is an 8-bit, high speed, analog-to-digital converter.
The AD9002 is fabricated in an advanced bipolar process which
allows operation at sampling rates in excess of ISO megasamplesl
second. Functionally, the AD9002 is comprised of 256 parallel
comparator stages whose outputs are decoded to drive the ECL
compatible output latches.
An exceptionally wide large signal analog input bandwidth of
l60MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9002 allows very accurate acquisition of
high speed pulse inputs, without an external track-and-hold.
The comparator output decoding scheme minimizes false codes
which is critical to high speed linearity.
BIT 2
BIT 1 (LSB)
GND
HYSTERESIS
- Vs
range. The AD9002 also incorporates an overflow bit to indicate
overrange inputs. This overflow output can be disabled with the
overflow inhibit pin.
The AD9002 provides an external hysteresis control pin which
can be used to optin1ize comparator sensitivity to further improve
performance. Additionally, the AD9002's low power dissipation
of 750mW makes it usable over the full extended temperature
The AD9002 is available in two grades, one with 0.5LSB linearity
and one with 0.75LSB linearity. Both versions are offered in an
industrial grade, - 25°C to + 85°C, packaged in a 28-pin DIP
and a 28-pin PLCC. The military temperature range devices,
- 55°C to + 125°C, are available in ceramic DIP and LCC packages
and are compliant to MIL-STD-883 Class B.
PIN DESIGNATIONS
LCC
DIP
PLCC
I Ig
•
%
DlGfTAL-Vs
!
OVERFtOW
~
DaCMSSJ
~
,
f
.
I
LSB
1.2
8
7,8
1.0
1.2
1.2
LSB
GUARANTEED
14
17
10
12
Sub-
14
17
10
12
GUARANTEED
7
8
7
8
8
4
20
LSB
LSB
GUARANTEED
14
17
10
12
8
4
20
14
17
10
12
mV
mV
mV
mV
",VI"C
100
200
",A
",A
k!l
pF
MHz
20
ANALOG INPUT
Input Bias CurrentS
Input Resistance
Input Capacitance
Large Signal Bandwidth6
Input Slew Rate 7
REFERENCE INPUT
Reference Ladder Resistance
Ladder Tempera[Ure Coefficient
Reference Input Bandwidth
+25"<:
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
Aperture Uncertainty (Jiuer)
+ 25 C
Output Delay (tPD)8,9
Transient Response 'O
Overvoltage Recovery Time ll
Output Rise TimeS
Output Fall TimeS
OutputTimeSkews ,12
+ 25"C
I
VI
60
100
V
V
VI
V
V
64
125
+25"<:
+ 25"C
+25"<:
+ 25"C
+25"<:
+ 25"C
I
V
V
I
V
V
I
I
V
Full
Full
Full
Full
+25"C
+25"<:
+ 25"C
VI
VI
VI
VI
V
I
I
-1.1
Full
VI
+25"<:
+ 25"C
Q
2.5
200
17
160
440
80
0.25
10
100
200
60
100
22
110
150
64
125
200
17
160
440
80
0.25
10
100
200
22
110
I
64
200
17
160
440
80
0.25
10
100
200
60
100
22
110
64
80
0.25
10
125
150
1.3
1.3
1.3
15
3.7
6
6
2.5
15
3.7
15
3.7
6
6
3.0
2.5
5.5
5.5
2.5
6
6
3.0
2.5
0.6
9
125
200
17
160
440
1.3
2.5
4
100
15
3.7
6
6
5.5
150
60
I
2,3
12
12
VI..,s
110
5.5
3.0
2.5
0.6
n
nrc
MHz
150
3.0
2.5
9
9
0.6
22
0.6
MSPS
ns
ps
na
ns
n.
ns
ns
ns
ENCODE INPUT
Logic "." VoltageS
Logic "0" VoltageS
Logic"." Current
Logic "0" Current
Input Capacitance
Encode Pulse Width (Low)H
Encode Pulse Width (High) 13
OVERFLOW INHIBIT INPUT
OV Input Current
ACLINEARITy 14
Effective Bits 15
In·Band Harmonics
de to 1.23MHz
dcto9.3MHz
de to 19.3MHz
Signai.to-Noise Ratio l6
Two Tone Intermod Rejection 11
DIGITAL OUTPUTS'
Logic"I"Vol_
Logic"O"Vol_
POWER SUPPLY"
Supply Current ( -5.2V)
Nominal Power Dissipation
Reference Ladder Dissipation
Power Supply Rejection Ratio l9
-1.1
-1.5
150
120
-1.5
150
120
3
+ 25"C
V
+25"<:
+25"<:
+25"<:
+25"<:
+25"<:
I
V
V
I
V
48
Full
Full
VI
VI
-1.1
+25"<:
Full
+25"<:
+25"<:
+ 25"C
I
VI
V
V
I
300
144
300
48
46
3--444 ANALOG-TO-DIGITAL CONVERTERS
1,2,3
175
200
1.5
-1.5
145
175
200
750
50
0.8
300
144
4
48
4
46
1,2,3
1,2,3
-1.1
1.5
1
2,3
7
55
50
44
47.6
60
48
46
300
175
200
1.5
jJ.A
7.6
Bits
dB
dB
dB
-1.5
145
jJ.A
55
50
44
47.6
60
dB
dB
-1.1
750
50
0.8
V
V
",A
pF
ns
ns
3
1.5
1.5
144
60
-1.5
-1.5
150
120
7.6
55
50
44
47.6
-1.1
145
1.5
1.5
7.6
55
50
44
47.6
60
750
50
0.8
4
4
-1.1
-1.5
150
120
3
1.5
1.5
7.6
46
-1.1
3
1.5
1.5
144
7,8
7,8
7,8
7,8
-1.5
145
750
50
0.8
175
100
1.5
V
V
mA
mA
mW
mW
mVN
AD9002
NOTES
I Absolute maximum ratings are limiting values, to be applied individually,
and beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not necessarily
implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect device reliability.
2 + VREF 2:: - VREF under all circumstances.
3Maximum junction temperature (tJ max) should Dot exceed 175°C
for ceramic packages, and 150°C for plastic packages:
tl ~ PD (SIA) + tA
PD (SIC) + tc
where
PD = power dissipation
BJA = thermal impedance from junction to ambient (OCIW)
SIC ~ thermal impedance from junction to case ("CIW)
tA = ambient temperature COe)
tc = case temperature COe)
typical thermal impedances 3re:
Ceramic DIP SIA ~ S6"CIW; SIC ~ 20"CIW
Plastic DIP SIA ~ 60"CIW; SIC ~ 20"CIW
Ceramic LCC SIA ~ 69"CIW; 0IC ~ 23"CIW
PLCC SIA ~60"CIW, SIC~ 19"CIW.
'Subgroups apply to military qualified devices only.
'Measured with AIN~OV.
6Measured by FFT analysis where fundamental is - 3dBc.
'Input slew rate derived from rise time (10 to 90%) of full scale input.
'Outputs terminated through lOOn to - 2V.
'Measured from ENCODE in to data out for LSB only.
IOFar full-scale step input, 8-bit accuracy is attained in specified time.
lIRecovers to 8-bit accuracy in specified time after 150% full-scale input
overvoltage.
120utput time skew includes high-to-Iow and low-to-high transitions as well
as bit-to-bit time skew differences.
"ENCODE signal riselfall times should be less than IOns for normal
operation.
"Measured at 12SMSPS encode rate.
15Analog input frequency ~ 1.23MHz.
16RMS signal to rms noise, with 1.23MHz analog input signal.
17lnput signals IV pop @1.23MHzand IV Pop @2.30MHz.
18Supplies should remain stable within ± 5% for normal operation.
19Measured at - 5.2V ± 5%.
Specifications subject to change without notice.
Recommended Operating Conditions
Input Voltage
Parameter
-Vs
+VREF
-VREF
Analog Input
Nominal
-5.20
O.OV
-2.0
Min
-5.46
-VREF
-2.1
-VREF
EXPLANATION OF TEST LEVELS
Test Level I
- 100% production tested.
Test Level II
- 100% production rested at + 25"C, and sample tested
at specified temperatures.
Test Level III
- Sample tested only.
Test Level IV
- Parameter is guaranteed by design and characterization testing.
Test Level V
- Parameter is a typical value only.
Test Level VI
- All devices are 100% production tested at + 25"C.
100% production tested at temperature extremes for
extended temperature devices; sample tested at
temperature extremes for commercial/industrial
devices.
Max
-4.94
+0.1
+VREF
+VREF
EXPLANATION OF SUBGROUPS
Subgroup I - Static tests at + 25"C (5% PDA calculated
against Subgroup 1 for MIL-STD-883 version).
Subgroup 2 - Static tests at maximum rated operating temperature.
Subgroup 3 - Static tests at minimum rated operating temperature.
Subgroup 4 - Dynamic tests at + 25"C.
Subgroup 5 - Dynamic tests at maximum rated operating temperature.
Subgroup 6 - Dynamic tests at minimum rated operating temperature.
Subgroup 7 - Functional tests at + 25"C.
Subgroup 8 - Functional tests at maximum and minimum fated
operating temperatures.
Subgroup 9 - Switching tests at + 25"C.
Subgroup 10 - Switching tests at maximum rated operating
temperature.
Subgroup 11 - Switching tests at minimum rated operating temperature.
Subgroup 12 - Periodically sample tested.
ORDERING INFORMATION
Device
Linearity
Temperature
Range
Description
Package
Options*
AD9002AD
AD9002BD
AD9002AN
AD9002BN
AD9002AP
AD9002BP
AD9002SD/883B
AD9002SE/883B
AD9002TD/883B
AD9002TE/883B
0.75LSB
0.50LSB
0.7SLSB
O.SOLSB
0.7SLSB
0.50LSB
0.7SLSB
0.7SLSB
O.SOLSB
O.SOLSB
-
28-Pin Ceramic DIP, Industrial
28-Pin Ceramic DIP, Industrial
28-PinPlastic DIP, Industrial
28-PinPlastic DIP, Industrial
28-Pin PLCC, Industrial
28-Pin PLCC, Industrial
28-Pin Ceramic DIP, Military
28-Pin LCC, Military
28-Pin Ceramic DIP, Military
28-Pin LCC, Military
D-28
D-28
N-28
N-28
P-28A
P-28A
D-28
E-28A
D-28
E-28A
25°C to
25°C to
25°C to
25°C to
25°C to
25"C to
55°C to
55°C to
55°C to
55°C to
+ 85°C
+ 85°C
+ 85°C
+ 85°C
+ 85°C
+ 85°C
+ 125°C
+ 125°C
+ 12S"C
+ 125°C
*See Section 14 for package outline information.
ANALOG-TO-D/GITAL CONVERTERS 3-445
•
FUNCTIONAL DESCRIPTION
Pin #
I
2
Name
DIGITAL GROUND
OVERFLOW INH
Description
One of four digital ground pins. All digital ground pins should be connected together.
OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs.
ANALOG
INPUT
VIN> +VREF
VINS+VREF
3
HYSTERESIS
4
5
6
7
+VREF
ANALOG INPUT
ANALOG GROUND
ENCODE
8
ENCODE.
ANALOG GROUND
ANALOG INPUT
-VREF
REFMID
DIGITAL GROUND
DIGITAL -Vs
9
10
II
12
13
14
Dl
15
16-19
20
21,22
DIGITAL GROUND
ANALOG -Vs
23
24,25
26
27
DIGITAL GROUND
D6,D7
D8
OVERFLOW
28
DIGITAL -Vs
D2-DS
OVERFLOW ENABLED
(FLOATING OR -5.2V)
OF D, D2 D3 D, Ds D6 D7 Ds
1
0
0
0
0
0
0
0
0
0
X X X X X X X X
OVERFLOW INHIBITED (GND)
OF D, D2 D3 D, Ds D6 D7 Ds
0
0
1
1
X X X X X X X
1
1
1
1
1
1
X
The Hysteresis control voltage varies the comparator hysteresis from Omv to lOmV, for a change
from - 5.2V to - 2.2V at the Hysteresis control pin.
The most positive reference voltage for the internal resistor ladder.
One of two analog input pins. Both analog input pins should be connected together.
One of two analog ground pins. Both analog ground pins should be connected together.
Noninverted input of the differential encode input. This pin is driven in conjunction with
ENCODE. Data is latched on the rising edge of the ENCODE signal.
Inverted input of the differential encode input. This pin is driven in conjunction with ENCODE.
One of two analog ground pins. Both analog ground pins should be connected together.
One of two analog input pins. Both analog inputs should be connected together.
The most negative reference voltage for the internal resistor ladder.
The midpoint tap on the internal resistor ladder.
One of four digital ground pins. All digital ground pins should be connected together.
One of two negative digital supply pins (nominally - 5.2V). Both digital supply pins should be
connected together.
. '
Digital data output (LSB).
Digital data output.
One of four digital ground pins. All digital ground pins should be connected together.
One of two negative analog supply pins (nominally - 5.2V). Both analog supply pins should be
connected together.
One of four digital ground pins. All digital ground pins should be connected together.
Digital data output.
Digital data output (MSB).
Overflow data output. Logic high indicates an input overvoltage (V IN > + VREF) if OVERFLOW
INHIBIT is enabled (overflow enabled, - 5.2V). See OVERFLOW INHIBIT.
One of two negative digital supply pins (nominally - 5.2V). Both digital supply pins should be
connected together.
OVERFLOW
INHIBIT
ANALOG IN
BIT 3
BIT 2
BIT 1 (lSa)
GND
HYSTERESIS
- Vs
Functional Block Diagram
3-446 ANALOG-TO-DIGITAL CONVERTERS
AD9002
TIMING DIAGRAM
II
INPUT OUTPUT CIRCUITS
AD9002
ENCODE
ANALOG
INPUT
ENCODEQ-------4-----~
DIGITAL
OUTPUT
-5.2V
~
COMPARATOR CELLS
BURN-IN DIAGRAM
r l 1---..,..-----------.....-
9
100
r·
1
HYSTERESIS
OVERFLOW
OVERFLOW INH
0,
ANALOG IN
0,
AD1
-5.2V
-Vs
t-""'..-"i
MIL-STD-883 COMPLIANCE INFORMATION
The AD9002 SD/SE/TE/TQ/883B devices are classified within
Microcircuits Group 57, Technology Group D (bipolar AID
converters), and are constructed in accordance with MIL-STD883. The AD9OO2 is electrostatic sensitive and falls within electrostatic sensitivity classification Class 1. Percent Defective
Allowance (PDA) is computed based on Subgroup 1 of the
specified Group A test list. Quality Assurance (QA) screening is
in accordance with Alternate Method A of Method 5005.
1.
AD2
ENCODE
1.
AD3
ENCODE
-2V
0,
AD9002
-VREF
0,
D.
0,
0.1*
0,
+VR£F
GROUND
STATIC BURN IN
AD1 = OV
=
AD2 Eel HIGH
0,
LOAD RESISTORS
AD3 = EeL lOW
DYNAMIC BURN IN
AD1~
OV
EClHIGH
ECllOW
AD3~
ECLHIGH
----1
All RESISTORS "5%.
The following apply: Burn-In per 1015;.Life Test per 1005;
Electrical Testing per 5004. (Note: Group A electrical testing
assumes ta = t., = ti') MIL-STD-883-compliant devices are
marked with "c" to indicate compliance.
-2V
rI
rI
rI---L-...J
L-...J
L-
AD2
= 1k
ECllOW
n
ALL CAPACITORS ::t 20%. JlF
AU SUPPUES
.:!: 5%
AD9002 BURN IN DIAGRAM
ANALOG-TO-OIGITAL CONVERTERS 3-447
DIE LAYOUT
OVERFLOW
INHIBIT
~=~,
\
~•
..
•
.V_
DIGITA,~
DIGITAL -Vs
/
GROUNj
OVERFLOW
-
ANALOG\
INPUT
:.,
••
ANALOG
GROUND _ _
•
DIGITAL
GROUND
ANALOG -Vs
DIGITAL
GROUND
ANALOG_
GROUND
D.
03
MECHANICAL INFORMATION
Die Dimensions .
Pad Dimensions .
Metalization . . .
Backing . . . . .
Substrate Potential
Passivation
Die Attach
Bond Wire
3-448 ANALOG-TO-DIGITAL CONVERTERS
. I06x 114x IS (±2) mils
4x4 mils
. Gold
None
. -Vs
. Nitride
Gold Eutectic (Ceramic)
Epoxy (Plastic)
1-1.3 mil Gold; Gold Ball Bonding
AD9002
APPLICATION INFORMATION
The AD9002 is compatible with all standard EeL logic families,
including 10K and IOKH. lOOK EeL's logic levels are temperature
compensated, and are therefore compatible with the AD9002
(and most other EeL device families) only over a limited temperature range. To operate at the highest encode rates, the
supporting logic around the AD9002 will need to be equally
fast. Whichever of the EeL logic families is used, special care
must be exercised to keep digital switching noise away from the
analog circuits around the AD9002. The two most critical items
are digital supply lines and digital ground return.
The input capacitance of the AD9002 is an exceptionally low
17pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the wide
input bandwidth of the AD9002, a hybrid amplifier such as the
AD9610 will be required. For those applications that do not
require the full input bandwidth of the AD9002, more traditional
monolithic amplifiers, such as the AD846, will work very well.
Overall performance with any amplifier can be improved by
inserting a IOn resistor in series with the amplifier output.
The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tPD), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the data
transfer to the output latches are triggered on the rising edge of
the differential, ECL compatible ENCODE signal (see timing
diagram). In applications where only a single-ended signal is
available, the AD96685, a high speed, ECL voltage comparator,
can be employed to generate the differential signals. All ECL
signals (including the overflow bit) should be terminated properly
to avoid ringing and reflection.
LAYOUT SUGGESTIONS
Designs using the AD9002, like all high speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first requirement
is for a substantial ground plane around and under the AD9002.
Separate ground plane areas for the digital and analog components
may be useful, but these separate grounds should be connected
together at the AD9002 to avoid the effects of "ground loop"
currents.
The second area that requires an extra degree of attention involves
the three reference inputs, + VREF, REFMID, and - VREF• The
+ VREF input and the - VREF input should both be driven from
a low impedance source (note that the + VREF input is typically
tied to analog ground). A low drift amplifier should provide
satisfactory results, even over an extended temperature range.
Adjustments at the REFMID input may be useful in improving
the integral linearity by correcting any reference ladder skews.
The application circuit shown below demonstrates a simple and
effective means of driving the reference circuit.
The reference inputs should be adequately decoupled to ground
through O.lfLF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; O.lfLF and
O.OlfLF chip capacitors are recommended.
The analog input signal is brought into the AD9002 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical connections. Otherwise, aperture delay errors may degrade converter
performance at high frequencies.
The AD9002 also incorporates a HYSTERESIS control pin
which provides from 0 to IOmV of additional hysteresis in the
comparator input stages. Adjustments in the HYSTERESIS
control voltage may help improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INHIBIT pin of the AD9002 determines
how the converter handles overrange inputs (AIN." + VREF). In
the "enabled" state (floating at - 5.2V), the OVERFLOW
output will be at logic HIGH and all other outputs will be at
logic LOW for overrange inputs (return-to-zero operation). In
the "inhibited" state (tied to ground), the OVERFLOW output
will be at logic LOW, and all other outputs will be at logic
HIGH for overrange inputs (nonreturn-to-zero operation).
The AD9002 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTERESIS
control pin). This level of performance is extremely important
in fault-sensitive applications such as digital radio (QAM).
Dramatic improvements in comparator design and construction
give the AD9002 excellent dynamic chara~teristics, especially
SNR (signal-to-noise ratio). The 160MHz input bandwidth and
low error rate performance give the AD9002 an SNR of 48dB
with a 1.23MHz input. High SNR performance is particularly
important in wide bandwidth applications, such as pulse signature
analysis, commonly performed in advanced radar receivers.
ANALOG
INPUT
0
tOTO +2V)
D.IMSBI
D,
D.
ADOOO2
D.
D,
D,
D,llSB)
0,0'*
*0.1
Typical A09002 Application
ANALOG-TO-OIGITAL CONVERTERS 3-449
II
AD9002 EVALUATION CIRCUIT
LINEARITY OUTPUT
(ERRORWAVEFORMI
RECONSTRUCTED
OUTPUT
HOS100
4.3k
lk
lk
-15V
50
ANALOG
INPUT
~
D,(MSBI
0,
D.
2k
-~-,~.
~
~h-'
~
tL
0.1
~O.l
lk
-15V
-=
AD9002'
0,
0,
0
0
8
R 1
I 1
V 4
E
R
0, (LSBI
~
z
z
P
Z
..
ii:
....
CLK
.....-..,."--'ij=_...
625
' - _......_,.-......_ - - '
AD96687
AD96687
AD96687
510
13k
-15V
-15V
-=
'CONTACT FACTORY ABOUT EVALUATION BOARD AVAILABILITY
AD9002 DYNAMIC PERFORMANCE
65
iii_ 60
...0'""
-ID
-I
~~
....
55
,
""':ND
,
ww
Z'"
os.!
... Z
.;.0 45
e(lt
Zll:
(!Ie(
iii~
IIIZ
Ie(
,
~~
SNR'"
40
JARM~N~C
..J~ :AR~ONIC\
!II> 50
OW
......
~
35
~.....
1\
r\ I\.
I'
30
1MHz
10MHz
100MHz
ANALOG INPUT FREQUENCY (O.1dB BELOW FULL SCALE)
125 MSPS ENCODE RATE
~50
a::
!)
S i
T 5
E 1
R
D.
L
I
N
E 1
0
-5.2V
ENCODE INPUT
(GROUNDTHRESHOLDI
R
E
G
I
ANALOG-TO-DIGITAL CONVERTERS
NOTE:
100114 LINE DRIVER OUTPUTS
REQUIRES 51011 PULL DOWN
RESISTORS TO - 5.2V. ALL OTHER
ECL OUTPUTS SHOULD BE
TERMINATED TO -2V WITH
10011 RESISTORS. UNLESS
OTHERWISE SPECIFIED.
RESISTORS ARE IN II.
CAPACITORS ARE IN "F.
12-Bit, 1MHz
AID Converter
AD9003 I
r.ANALOG
WDEVICES
AD9003 FUNCTIONAL BLOCK DIAGRAM
FEATURES
12-Bit Resolution
1MHz Word Rates
T/H and Timing Included
Single 4O-Pin DIP
APPLICATIONS
Radar Systems
Digital Oscilloscopes
Test Systems
Analytical Instrumentation
Waveform Analyzers
UNIPOLAR OFFSET
r---,
•
GAIN & OFFSET
ADJUST
ANALOG
INPUT
ENCODE
COMMAND
GENERAL DESCRIPTION
The AD9003 is a complete 12-bit, lMHz analog-to-digital converter (ADC) which combines low cost and high performance in
a single 4O-pin DIP. This unique converter includes track-and-hold
(T/H), timing, and encoding functions with a power dissipation
of only 2.2 watts.
This remarkable unit is capable of converting analog signals to
the Nyquist limit at word rates through IMHz. Its IlLS conversion
interval includes acquisition time for the internal TIH, making
it a true IMHz converter.
Proprietary conversion techniques achieve linearity equivalent to
the best successive approximation ADC along with subranging
conversion speeds. A conversion status signal simplifies transferring output data into system logic. Innovative thick- and thin-film
technologies assure excellent performance over temperature
without compromising ac characteristics.
The AD9003KM operates at case temperatures from 0 to + 70°C;
the SM/883B and TMl883B units operate from - 25°C to
+ 100°C.
ANALOG-TO-DIGITAL CONVERTERS
~51
SPEC IFI CATI0NS (Typical with noninal supplies, unless othelWise notBd)
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
±Vs . . .
Va; • . . .
Analog Input
Digital Inputs
Maximum Junction Temperature
Models AD9003SMrrMl883B
Model AD9003KM . . . . . .
Parameter,,2 (Conditions)
SubGroup
Temp.
Min
LSBWeight
DYNAMICCHARACTERIST/CS
(Conversion Rate = IMHz)'
In-Band Harmonics4
j de to 100kHz
j de to 100kHz
# 100kHz to 500kHz
j Conversion TimeS
# Effective Apei'ture Delay Time
# Aperture Uncertainty Gitter)
j Signal-to·Noise Ratio·
j Signal-to-Noise Ratio·
# Transient Response 7
# OvervoltageRecoveryTime8
# Two-Tonclntermodulation9
ANALOG INPUT
# VoltageRange(FullScale)'o
j Input Impedance
j Input Impedance
Input Bandwidth
# Small Signal, -3dB"
# Large Signal, - 3dB l2
TEMPERATURE DRIFT
Offset Temperature Coefficient
j Bipolar
j Unipolar
j Gain Temperature Coefficient
# DifferentialLinearityTempco
DIGITAL INPUTS
# Logic Compatibility
# Logic "1" Voltage
# Logic "0" Voltage
Encode Command 13
Input Current
j Logic"I"
j Logic"O"
# Width l4
# Frequency
# Rise/Fall Times
AD9003KM'
Typ
Mal<
4
5,6
4
5,6
+ 25'C
Full
+2S'C
Full
+ 25'C
Full
+ 25'C
Full
+25'C
Full
5,6
Full
12
4
5,6
+ 25'C 74
Full
72
+ 25'C
+ 25'C
+ 25'C 6
+ 25'C
+ 25'C 65
Full
65
+ 25'C
+ 25'C
+ 25'C
80
4
4
4
4
5,6
I
2,3
5,6
5,6
5,6
Full
+ 25'C
Full
±O.I
+5
±5
±0.5
±0.8
950
950
75
820
16
26
69
AD9003TMl883B2
Typ
Min
Max
Units
12
0.024
1.22
12
0.024
1.22
Bits
%FS
mV
±S
±5
±0.5
± 1.5
±1.5
±0.8
5
1000
1000
±IO
±IO
± IS
± 1.5
74
72
850
27
6
65
65
74
72
850
27
1050
1050
6
65
65
950
950
±35
±35
±40
±3.5
5
1000
1000
±10
±IO
±15
± 1.5
+2.0
-0.5
200
de
±32
±IO
±32
±1.0
±1.0
±1.5
±2.0
Bits
80
dB
dB
dB
ns
ns
ps,rms
dB
dB
ns
ns
dB
75
820
16
26
69
850
27
1500
87
1050
1050
950
950
5
1000
1000
V,p-p
1050
1050
10
8
±40
±40
±40
±3.5
%FS
%FS
mV
mV
mV
mV
LSB
LSB
LSB
LSB
12
200
±IO
±IO
±15
± 1.5
TTL
-1.2
750
1.0
10
~'n
1500
10
8
Vee
+0.8
±S
±0.8
200
60
200
dc
75
820
16
26
69
±0.2
±0.6
±0.5
±1.5
±2.0
80
±O.I
±5
87
TTL
+2.0
-0.5
±0.2
±0.6
±10
±32
±IO
±32
±1.0
12
1500
Full
Full
Full
Full
3-452 ANALOG-TO-DIGITAL CONVERTERS
±O.I
200
10
8
Full
Full
Full
Full
Full
±0.2
±0.46
±10
±23
±IO
±23
± 1.0
87
+ 25'C
+ 25'C
Full
Full
Full
1,2,3
1,2,3
.. 0 to +70°C
-25C to +100°
65°C to + 150°C
. . . . +300°C
AD9003SMl883B2
Typ
Min
M""
12
0.024
1.22
4
·
·
·
165°C
150°C
RESOLUTION
STATIC ACCURACY
j Gain Error
# GainError
J Bipolar Offset
# Bipolar Offset
j Unipolar Offset
# Unipolar Offset
j Differential Linearity
j Differential Linearity
j Integral Linearity (Best Fit)
j Integral Linearity (Best Fit)
j Resolution for Which There
are No Missing Codes
Operating Temperature Range (Case)
AD9003KM
AD9003SMrrMl883B . . . . . . .
Storage Temperature . . . . . . . .
Lead Soldering Temperature (10 sec)
. . . . . ±18V
-0.5V to +7V
. . . ±15V
-0.5 to Va;
n
n
MHz
MHz
±40
±40
±40
±3.5
ppmI'C
ppmfC
ppmfC
ppmfC
Vee
+0.8
V
V
60
fl-A
rnA
ns
MHz
ns
TTL
Vcr;
+0.8
60
-1.2
750
1.0
10
+2.0
-0.5
200
dc
-1.2
750
1.0
10
AD9003
Parameter'·' (Conditions)
DIGITAL OUTPUTS
# Logic Compatibility
j Logic "I" Voltage
j Logic "0" Voltage
# Output Drive
Format
Coding
Unipolar Mode
Bipolar Mode
POWER REQUIREMENTS
+Vs Voltage
j +VsCurrent
-Vs Voltage
j -VsCurrent
VccVoltage
j VccCurrent
j Power Dissipation
# PSRR'5
SubGroup
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Temp.
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
+ 25°C
THERMAL RESISTANCE
Junction to Air, 6ca )6
Junction to Case, 6jc
Min
AD9003KM'
Typ
Max
AD9003SMl883B'
Typ
Min
Max
TTL
+2.4
+2.4
+0.4
+0.4
+0.4
I Standard
Parallel
I Standard
Parallel
I Standard
Parallel
Complementary Binary
Complementary
Offset Binary
Complementary Binary
Complementary
Offset Binary
Complementary Binary
Complementary
Offset Binary
+ 14.5
-14.5
+4.7S
+ 15.0
78
-15.0
44
+S.O
75
2.2
45
+ 15.5
90
-15.5
49
+5.2S
200
3.2
+ 14.5
-14.5
+4.7S
MTBF17
Mean Time Between Failures
+15.0
78
-15.0
44
+5.0
75
2.2
45
+ ISS
90
-15.S
49
+5.25
200
3.2
NOTES
j 100% tested (See Notes I and 2).
#Specification guaranteed by design; not tested.
'AD9003KM parameters preceded by a check (j) are tested at + 25°C
ambient temperature; performance is guaran.teed over the commercial
temperature range (0 to + 70"C case temperature).
'AD9003SMl883B and TM/883B parameters preceded by a check (j) are
tested at - 25°C case, + 25°C ambient, and + lOOoe case temperatures.
Both grades are manufactured in full compliance to MIL-STD-883,
Rev. C.
3Converting in excess of 1.0MHz is possible; however,. acquisition time
is reduced, which may increase distortion of high-frequency analog signals.
4In-band harmonics are expressed in dB below FS in terms of spurious
in-band signals generated at IMHz encode rate and single tone analog
input in range shown.
'Measured from leading edge of encode command to trailing (rising) edge
of conversion status signal (see Timing Diagram).
6RMS signal to rms noise ratio; analog input IdB below FS @ 100kHz;
IMHz encode rate.
7Por full·scale step input, 12-bit accuracy attained in specified time.
+ 14.5
-14.5
+4.75
+IS.O
78
-IS.O
44
+5.0
75
2.2
45
+ IS.S
90
-IS.s
49
+5.25
200
3.2
19
3
19
3
7.84x
10'
7.84x
10'
AD9003KM
Units
TTL
TTL
+2.4
19
3
PACKAGE OPTIONS"
M-40
AD9003TMI883B'
Typ
Max
Min
AD9003SM/883B
V
V
TTL Load
V
rnA
V
rnA
V
rnA
W
dB
°CIW
°CIW
Hours
AD9003TM/883B
·Recovers to 12-bit accuracy in specified time after 2 X FS input
overvoltage. (See text and Figure 5 for information on overloads.)
"Intermodulation measured in dB below FS at IMHz encode rate with input
frequencies of 75kHz and 105kHz; each 7dB below FS.
"'Voltage Range = ±2.5Vor OV to -5.0V.
"With analog input 40dB below FS.
"With FS analog input. (Large-aignal !lW flat within 0.5dB, de to 500kHz.)
13Transition from ''0'' to "1" initiates conversion.
"For IMHz encode rate. At conversions below IMHz, max width is
conversion period minus 25Oos. Optimum linearity at 200 to 250ns widths.
"Power Supply Rejection Ratio (PSRR) is sensitiviry of offset to Vee. This
is parameter which is most sensitive to variations in supply voltage.
16The relationship between the device package and outside environment (Oa)
varies with the application. Value shown is based on measuring case
temperature with supply voltages applied to a device installed in a ZIF
socket mounted on a standard "EJ" burn-in board.
"Calculated for SMlTM versions using MIL-HNBK-217; Ground Fixed;
+ 80"C case temperature.
"See Section 14 for package outline information.
Specifications subject to change without notice.
EXPLANATION OF SUBGROUPS
Subgroup 1 - Static tests at + 25°C,
(10% PDA calculated against Subgroup 1 for high-rei
versions)
Subgroup 2 - Static tests at maximum rated temperature.
Subgroup 3 - Static tests at minimum rated temperature.
Subgroup 4 - Dynamic tests at + 25°C.
Subgroup 5 - Dynamic tests at maximum rated temperature.
Subgroup 6 - Dynamic tests at minimum rated temperature.
Subgroup 7 - Functional tests at + 25°C.
Subgroup 8 - Functional tests at maximum and minimum
rated temperatures.
Subgroup 9 - Switching tests at + 25°C.
Subgroup 10 - Switching tests at maximum rined temperature.
Subgroup II - Switching tests at minimum rated temperature.
Subgroup 12 - Periodically sample tested.
ANALOG-TO-DIGITAL CONVERTERS 3-453
II
PIN DESIGNATIONS
(As viewed from bottom)
PIN FUNcnON
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIN FUNcnON
DIGITAL GROUND
1
BIT 1
2
BIT 2
3
BIT3
4
BIT4
5
BIT 5
6
BIT 6
7
+5V
8
UNIPOLAR OFFS~
9
UNIPOLAR OFFSET'.z
10
+15V
11
BIT 7
12
CORRECTION Blyl
13
CORRECTION BlTa
14
BIT 8
15
BIT9
16
BIT 10
17
BIT 11
18
BIT 12
19
CONVERSION STATUS 20
+5V
REFERENCE BYPASS'
DIGITAL GROUND
DIGITAL GROUND
-15V
ANALOG INPUT
DO NOT CONNECT
GAIN 8rOFFSET ADJUST
ANALOG GROUND
ANALOG GROUND
ANALOG GROUND
ANALOG GROUND
ANALOG GROUND
ANALOG GROUND
ANALOG GROUND
ANALOG GROUND
+5V
DIGITAL GROUND
-15V
ENCODE COMMAND
NOTES
Although Grounds are Designated as Analog or Digital, All
Grounds Should Be Connected to a Single Common LowImpedance Ground Plane for Best Results.
'Pins 2 and 31 Must Be Bypassed to Ground with 0.1p.F for
Optimum Performance.
2For Uni~lar Operation, Connect Pins 31 and 32;
for Bi~lar Operation, Ground Pin 32 and Connect
Pin 31 Only to 0.1 p.F.
3Pins 27 and 28 Must Always Be Strapped Together with
No Other Connections.
THEORY OF OPERATION
Refer to the block diagram of the AD9003.
12-bit parallel output from the AD9003 AID Converter.
Basically, the design of the unit is based on successive approximation techniques. However, the AD9003 also uses parallel
encoding for the most significant bits (MSBs).
The overall linearity of the AD9003 is independent of the flash
converter, which materially enhances the performance of the
unit. In addition, the architecture used in the converter makes
it less sensitive to nonlinearities caused by D/A and/or comparator
settling.
When a TTL-compatible Encode Command signal is applied to
Pin 20, it causes the internal Timing Generator to generate
strobe pulses used for controlling the timing of the various
actions within the device.
The encode command causes the track-and-hold (TIH) to switch
from a "track" mode to a "hold" mode; switches the 6-bit flash
converter to a tracking mode of operation to allow it to reach
the held value from the T/H; and resets the SAR. When the
flash converter output has been determined, Bits 1 - 6 become
inputs to the 12-bit DIA converter.
If the DIA voltage applied to the comparator is greater than the
"held" value being applied to the comparator, a correction bit is
turned on. If the DIA voltage is less, there is no correction bit
and no change in the signal.
At this point, the D/A output voltage and the correction circuit
outputs are l2-bit accurate. Standard successive approximation
techniques are used to determine Bits 7 - 12; the end result is a
3-454 ANALOG-TO-DIGITAL CONVERTERS
Performance of the AD9003 is equivalent to that of an ultrahighspeed SAR type of design. But the desigJ;l techniques which are
used relieve the stringent comparator/DAC settling requirements
usually associated with SAR designs. Instead, the AD9003 reaps
the benefits of combining the best characteristics of flash converters
and SARs while avoiding the penalties which are inherent in
each individually.
Refer to Figure I, the timing diagram for the AD9003. In this
illustration, spacing between encode commands is shown as it
would be for a IMHz word rate, i.e., lOOOns. The width of the
encode pulse is at its minimum value of 200ns.
The period of data validity associated with each encode command
appears, in the figure, to be relatively short. Remember, however,
each encode command generates the necessary switching to
perform the digitizing function, and causes the output data to
begin changing.
AD9003
L
•
CONVERSION
STATUS
OUTPUT
DATA
tw
ENCODE COMMAND PULSE WIDTH
SPACING BETWEEN ENCODE COMMANDS
te CONVERSION TIME
tv DATA VALID
t De DATA CHANGING
tE
MIN
200ns
1000ns
MAX
750ns
850ns
50ns
35ns
Figure 1. AD9003 Timing Diagram
In Figure I, the timing is based on a maximum encode rate,
with minimum spacing between encode commands. At lower
conversion rates, this spacing would be lengthened correspondingly
and the interval when data are valid would become longer.
Internal timing within the AD9003 typically requires 770ns to
accomplish the necessary switching and processing of the analog
input "frozen" by the encode command. Since the AD9003 is a
true IMHz converter, this leaves 230ns for the T/H to re-establish
full accuracy when it returns to the "track" mode at the completion
of the digitizing period.
This addition of the required 770ns and the 230ns accuracy
increment shows up as a total of 1,000ns minimum between
encode commands iIi Figure I; any shorter interval will detract
from the overall performance of the unit. Higher encode rates,
i.e., shorter intervals between encode commands, are possible;
but they may cause distortion on high-frequency analog signals
because the T/H will not be fully settled when it is switched to
the "hold" mode.
SETIING GAIN AND OFFSET
Varying gain and offset for the AD9003 enhances performance
of the unit and increases its flexibility in applications. One
suggested method of obtaining approximately 5% variation in
each is shown in Figure 2.
The AD9003 can be operated in a unipolar mode or a bipolar
mode; strap options and adjustments of the external controls
shown in Figure 2 determine which is used. When calibrating
for either mode, apply an encode command at the word rate
frequency of the system to Pin 20.
Connect a precision voltage source between the ANALOG INPUT
connection shown in Figure 2 and ground. Set its output for the
voltage shown in Table I as being equal to - FS + 1I2LSB for
the input range to be used (-0.6mV for unipolar operation and
+ 2.4994V for bipolar operation if using the full-scale 5V input
range of the AD9003).
Adjust the OFFSET control for a digital output which "dithers"
between 0000 0000 0000 and 0000 0000 0001.
ANALOG o-------~Ar~~---{
INPUT
+15V
PART OF
AD9003
OFFSET >'II~-N.,---;----\'
10kH
-15V
Figure 2. AD9003 Gain and Offset
ANALOG-TO-DIGITAL CONVERTERS 3-455
To set gain, readjust the output of the voltage reference source
to the value shown in Table I as being equal to + FS -1-1/2LSB
for the input range to be used (-4.9982V for unipolar operation;
- 2.4982V for bipolar operation with the full-scale 5V range).
Op Amp is the recommended choice for operation with the
AD9003. This amplifier has extremely fast settling time and low
distortion; these are especially important as the selected word
rate frequency approaches the Nyquist limit.
Adjust the GAIN control for a digital output which "dithers"
between Illl lUI IUO and UU 1111 lUI.
In some applications, the analog input signals to be digitized
may be outside the 5V range of the AD9003 converter, which
can detract from the performance of the device by driving it
into saturation.
Figures 3 and 4 provide additional information about the switching
points of the LSB when adjusting for either unipolar or bipolar
operation using the full-scale 5V input.
At input frequencies greater than 50kHz, overloads larger than
approximately 25% will saturate the front-end circuits of the
internal track-and-hold. When the overload is removed, the TIH
may cause erroneous codes to be generated at the output.
Figure 5 shows a suggested circuit to avoid this.
AD9003 DRIVER CIRCUIT WITH CLAMP
The choice of the driver amplifier for an AID can have significant
effect on the performance of the converter. The ADI AD9610
For
UNIPOLAR
Input
Apply
Reference
And
Adjust
010 -5V
-O,6mV
OFFSET
-4.9982V
010 -5V
GAIN
For
"Dither"
Between
For
BIPOLAR
Input
Apply
Reference
And
Adjust
0000 0000 0000 and
00000000 000 I
1111 1111 II 10 and
111111111111
0.00
0.00
OFFSET
-2.4982V
±2.SV
GAIN
For
"Dither"
Between
nl11 1111 , , , ,
V.I"J 1 .. .1.1 1.111
~_-I
al.lu
100000000000
11111111 I 110 and
111111111111
Table I.
I
I
!: : : :r========----=
~:---L-
I
I
__ t
111...111 - - - - - - - - - - , ._ __
111 ... 110
I
I
I
I
I
...
5
o
---------rl--I
-2.4982V
-FS -FS -FS
INPUT
(LSBs) + 1 + 2
VOLTAGE
I
+2.4994V
000 ... 010
'
000 ... 001
I
I
c?
+:5 I+~S
-2
I
I
)
-FS : -FS I -FS
(LSBs)
I
+1
: +2
-0.6mV
I
-1.amV
+FS
+FS
-1
(LSBs)
I
INPUT VOLTAGE
I
I
+FS
-2
i---J------------
~---------------
000 ... 001
000 ... 000
A
-4.9982V
Figure 3. AD9003 Unipolar Adjustment
3-456 ANALOG-TO-DIGITAL CONVERTERS
+~s
-1 (LSBs)
i
OUTPUT
CODE
Figure 4. AD9003 Bipolar Adjustment
AD9003
In this diagram, the value of the feed forward resistor
calculated on the basis of the equation:
RFF =
RFF
is
IDesired Full-Scale Bipolar Voltagel x 500
The circuit eliminates saturating the internal T/H of the AD9003.
Using an Analog Devices AD9610 ahead of the converter allows
± 3x overdrives before the amplifier goes into saturation. Even
in those instances in which the input signal exceeds the ± 3x
limit, the AD9610 comes out of saturation much more quickly
than the input circuits of the converter would under the same
circumstances.
Bipolar inputs to the AD9003 are held to a maximum of ±2.5V
by the clamp circuits made up of IN2810 Schottky diodes. The
Analog Devices AD744 amplifiers and their associated circuits
are for the purpose of clamping the Schottky diodes at the desired
maximum input levels. As shown, + CLAMP ADJUST and
-CLAMP ADJUST are set for +2.530V and -2.530V
respectively.
These adjustment values take into account the gain and offset
tolerances of the AD9003. If resistors with low temperature
coefficients are selected, the clamp circuit will operate over the
entire temperature range of the converter.
The bipolar circuit in Figure 5 can also be used for unipolar
operation of the AID with only minor changes. For this mode,
the upper op amp (AD744 #1) and its associated reference
circuits are removed; the upper IN2810 clamp is connected,
instead, to ground.
With these changes, the unipolar full-scale overdrive limit is
1.5x rather than the 3x of the bipolar connections; but this will
prevent saturating the front end circuits of the AD9003. The
value of RFF in the unipolar circuit is based on:
RFF =
IDesired Full-Scale Unipolar Voltagel x 250
+15V
ADJUSTTO
+ 2.530V ~
+15V
3kH
+15V
~ O.OlJ.'F
1.lkH
IN2810
+15V
33
~
IN825
50H
ANALOG
INPUT
200l!
±2.SV
AD9003
~ 10J.'F ~ O.lJ.'F
33
~
50l!
IN825
1.1kH
IN2810
-15V
/'"
R" ~ IDESIRED FULL-SCALE BIPOLAR VOLTAGEI x 500
ADJUST TO
-2.530V
-15V
Figure 5. AD9003 Driver Circuit with Clamp
ANALOG-TO-DIGITAL CONVERTERS 3-457
II
ORDERING INFORMATION
For operating case temperatures from 0 to + 70"C, order pan
nwnber AD9003KM. Two models are available with military
processing and operation at case temperatures betweeen - 25°C
and + lOOOC. With the eXception of differential linearity, the
electrical specifications on these devices are the same. The
AD9003SMl883B guarantees no missing codes over temperature;
the AD9003TMl883B is screened for differential nonlinearity of
± lLSB maximwn.
SUGGESTED LAYOUT
To obtain optimwn performance from systems using the AD9003
or any other high-speed component, the user must exercise care
in laying out the circuit. It is critical to use the shottest possible
lead lengths and circuit runs. Construct the circuit on a large,
low-impedance ground plane containing the maximwn possible
amount of copper dedicated as ground surface.
The AD9003 also requires the use of bypass capacitors on the
power supplies; these should be connected as closely as possible
to the supply pins. A suggested layout for the AD9003 when it
is mounted on a printed circuit board is shown in Figure 6.
Both the commercial temperature and extended temperature
versions are packaged in 4O-pin metal can DIPs.
0
C!
91<;:)
za..
<~
Z
C!O
OZ
-I;:)
w
0<
o~
>
:2
<0
za:
:2
12-Bit,10MSPS
AID Converter
AD9005 I
1IIIIIIII ANALOG
WDEVICES
AD900S FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete 12-Bit AID Converter
Includes Track and Hold. Reference and Timing
Bipolar Analog Input (±1.024VI
Up to 10MSPS Sampling Rate
Low Power Dissipation: 3.1W
Low Harmonic Distortion
"H
OUT AID IN
II
APPLICATIONS
Radar
Digital Oscilloscopes
Electro-Optics
Medical Scanners
Communication/Signal Intelligence
GENERAL DESCRIPTION
The AD900S is a complete 12-bit AID converter featuring onboard track-and-hold amplifier, voltage reference and timing
circuitry. Featuring sampling rates from dc to lOMSPS, the
AD900S uses a subranging converter architecture to achieve
high speed and high resolution. Dynamic performance includes
a SNR of 64dB and harmonic distortion of -72dBc with a
4.3MHz analog input.
Critical to this performance is the use of advanced bipolar integrated circuits, custom designed for the AD900S and manufactured by Analog Devices. The AD900S is TTL compatible with
offset binary outputs. It is available in a 46-pin hermetic metal
DIP in two temperature ranges: 0 to +70°C commercial range
and -55°C to + 125°C military range (case temperature).
ORDERING INFORMATION
Device
Temperature Range
Description
Package
Options*
AD900SKM
AD900STM
0 to + 70°C
-55°C to + 125°C
46-Pin DIP
46-Pin DIP
M-46
M-46
·See Section 14 for package outline information.
ANALOG-TO-DIGITAL CONVERTERS 3-459
SPECIFICATIONS
ABSOLUTE .MAXIMUM RATINGS!
Positive Supply Voltage (+Vcd . . . . . . . . . . . . . . . . . +l8V
Negative Supply Voltage ( - VEE)' . . . . . . . . . . . . . . . -18V
Positive Supply Voltage (+Vs )' . . . . . . . . . . . . . . . . . . +6V
Negative Supply Voltage (-Vs) . . . . . . . . . . . . . . . . . . -6V
Analog Input Voltage (Pin 45) . . . . . . . . . . . . . . . . ±3.0V dc
Digital Input Voltage . . . . . . . . . . . . . . . . . . -0.5V to +Vs
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . 4mA
ELECTRICAL CHARACTERISTICS
Operating Temperature Range (Case)
AD9005KM . . . . . . . . . . . . . . . . . . . . . . . . .0 to +70·C
AD9005TM . . . . . . . . . . . . . . . . . . . . . -55OC to +125OC
Storage Temperature Range . . . . . . . . . . . . -65OC to + l50·C
Junction Temperature2 • • • • • • • • • • • • • • • • • • • • • • + l650C
Lead Soldering Temperature (lOsee) . . . . . . . . .. . .+300OC
(+Vcc =+15V, -VEE =-15V, +Vs=+5V, -Vs=-5.2V, unless otherwise stated)
Parameter
Temp
Test
Level
RESOLUTION
LSB Weight
Full
Full
I
V
12
+ 25·C
Full
+25·C
Full
Full
+25·C
Full
+25·C
Full
I
VI
I
VI
VI
I
VI
I
VI
-0.75
-1.0
Full
Full
+25·C
Full
V
VI
V
V
Full
+ 25·C
+25·C
+25·C
+25·C
+ 25·C
I
V
V
IV
IV
IV
10
+25OC
+ 25·C
Full
+ 25·C
Full
IV
I
VI
I
VI
-70
-75
-68
-72
+25·C
+ 25·C
Full
+25·C
Full
IV
I"
VI
I
VI
65
63
63
62
61
+25OC
V
STATIC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Gain Error
Offset Error
ANALOG INPUT
Input Voltage Range
Input Resistance
Input Capacitance
Large Signal Input Bandwidth3
DYNAMIC CHARACTERISTICS 5
Maximum Conversion Rate
Output Data Delay·'· (tPD)
Aperture Delay
Aperture Uncertainty
Transient Response (to ± lLSB)'
Overvoitage Recovery TimeS
(to ±ILSB)
In-Band Harmonics 1O,4
FIN = 540kHz
F IN =2.3MHz
F IN =4.3MHz
Signal to Noise Ratio ll ,4
FIN = 540kHz
F IN =2.3MHz
F IN =4.3MHz
Two-Tone Intermodulation Distortion l2
FIN = 2.2MHz+2.3MHz
3-460 ANALOG-TO-O/G/TAL CONVERTERS
AD900SKM
Typ
Max
Min
AD900STM
Typ
Max
Min
12
0.5
0.5
+0.75
+1.0
±1.0
±2.25
±2.5
GUARANTEED
±0.5
±1.0
±2.0
±4
±15
±30
950
±0.5
±1.024
1000
5
38
+0.75
+1.25
±1.0
±2.25
±2.75
GUARANTEED
±0.5
±1.0
±2.0
±4
±15
±40
950
±0.5
±1.024
1000
5
38
5
10
-69
-67
-75
-72
-66
-67
-72
-66
-63
-72
67
65
64
63
60
62
60
67
65
-65
64
-74
%FS
%FS
mV
mV
n
pF
MHz
90
20
120
250
LSB
LSB
LSB
LSB
Vp-p
1050
10
90
5
10
-66
1050
-0.75
-1.0
Units
Bits
mV
20
120
250
MSPS
ns
ns
psrms
ns
ns
dBc
dBc
dBc
dBc
dBc
64
dB
dB
dB
dB
-74
dBc
AD9005
Parameter
Temp
Test
Level
ENCODEINPUT14
Logic "1" Voltage
Logic "0" Voltage
Logic "I" Current
Logic "0" Current
Input Capacitance
Encode Pulse Width (High)
Full
Full
Full
Full
+25°C
+25°C
IV
IV
IV
IV
V
IV
2.0
DIGITAL OUTPUTS
Logic "1" Voltage (2rnA Source)
Logic "0" Voltage (4rnA Sink)
Logic Coding
Full
Full
Full
IV
IV
IV
2.4
POWER SUPPLY
Supply Voltage +Vcc
Supply Current + Vcc
Supply Voltage -VEE
Supply Current - VEE
Supply Voltage + Vs
Supply Current Analog +Vs
Supply Current Digital + Vs
Supply Voltage -Vs
Supply Current Analog -Vs
Supply Current Digital - Vs
Nominal Power Dissipation
PSRR 13 ,15
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
+25°C
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
I
+14.25 +15.0
33
-14.25 -15.0
55
4.75
5.0
124
55
-4.95 -5.2
160
73
3.1
0.01
Min
AD9005KM
Typ
Max
Min
AD9005TM
Typ
Max
2.0
0.8
150
150
0.8
150
150
5
5
25
25
2.4
0.4
Offset Binary
+15.75
40
-15.75
70
5.25
140
110
-5.45
185
115
4.1
0.02
0.4
Offset Binary
+ 14.25 +15.0
23
-14.25 -15.0
45
4.75
5.0
124
55
-4.95 -5.2
160
73
3.1
0.01
+ 15.75
25
-15.75
55
5.25
140
110
-5.45
185
115
4.1
0.02
Units
V
V
jJA
jJA
pF
ns
V
V
V
rnA
V
rnA
V
rnA
rnA
V
rnA
rnA
W
%/%
NOTES
I Absolute maximum ratings are limiting valu.. , to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. Exposure to absolute rating conditions for extended periods of time may affect device reliability.
'Maximum junction temperature should not be allowed to exceed 165'C. Hybrid thermal model:
[JUNCTION = tAMBIENT +PDISSIPATION X (OCA.+ 9JC>
= 1cASE+ PmSSIPATION x (9]e)
46 Pin metal DIP: 6CA = 14"CIW in still air;
6CA = 6"CIW with 500LFPM air flow
6lC
= 6'C/W
'Determined by 3dB reduction in reconstructed output.
'Input at ldB below full scale.
'Measured at IOMHz encode rate.
"Measured from ENCODE in to data out for LSB only.
'For full-scale step input; 12-bit accuracy is attained in the specified time.
'Recovers to 12-bit accuracy in specified time following 200% full-scale input voltage.
"Excludes pipeline delay of two clock cycl.. (see timing diagram).
u'Worst case spurious in-band signal relative to input level.
IIRMS signal to RMS noise, including harmonics.
l~orst case spurious in-band signal relative to level of input tones, which are both -7dB below full scale.
"Sensitivity of full scale gain error with respect to power supply variation within supply MinIMax limits.
14ENCODE signal rise and fall times should be less than 5ns for Donnal operation. Transition from "0" to "1" initiates conversion.
15PSRR is tested over given voltage range.
EXPLANATION OF TEST LEVELS
Test
Test
Test
Test
Test
Test
Levell
Level II
Level III
Level IV
Level V
Level VI
100% production tested.
100% production t..ted at +25'C, and sample tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
All devices are 100% production tested at +25'C. 100% production tested at temperature extrem.. for
military temperature devices. Guaranteed, not t..ted, for commercial temperature range.
RECOMMENDED OPERATING CONDITIONS
Parameter
Mill
-Vs
+Vs
-VEE
+Vcc
Analog Input
-5.45
+5.25
-15.75
+14.25
-1.024
IDputVoltase
NomiDaI
-5.2
+5.0
-15.0
+15.0
Max
-4.95
+4.75
-14.25
+15.75
+1.024
ANALOG-TO-DIGITAL CONVERTERS 3-461
II
AD9005 PIN DESIGNATIONS
GROUND
NC
ANALOG +V.
GROUND
ANALOG INPUT
+VCC
T/HOUT
-VEE
AID IN
ANALOG -V.
DNC
DNC
ANALOG -Vs
NC
DNC
DNC
GROUND
GROUND
DNC
GROUND
GROUND
MSBD"
0,.
AD9005
D.
TOP VIEW
D.
(Not to Scale)
07
0,
0,
-VEE
GROUND
DIGITAL -V.
D.
u.
ANALOG +Vs
D.
DNC
0,
ONe
(LSB) D.
DIGITAL +V.
GROUND
GROUND 23
24
DNC
GROUND
GROUND
ENCODE
NC = NO CONNECT
DNC = DO NOT CONNECT
PIN DESCRIPTIONS
Pin
I
2
3
4
S
6
7,8
9
10-19
20
Description
Name
GROUND
NC
ANALOG +Vs
TIHOUT
NDIN
ANALOG -Vs
DNC
.DII(MSB)
D,-D IO
D.(LSB)
Circuit ground. All grounds should be connected together near the AD900S.
Not internally connected.
Positive analog supply pin. Nominally + SV dc.
Output of internal track-and-hold amplifier. Connect to Pin S for normal operation.
Input to internal ND encoder. Connect to Pin 4 for normal operation.
Negative analog supply pin. Nominally -S.2V dc.
Do not connect. Internal test point.
Most significant bit of digital output data.
Digital data outputs.
Least significant bit of digital output data.
OUTPUT CODING
ANALOG
INPUT
2:+1.024V
s-1.024V
21
22,23
24
2S,26
27-29
30
31
32
33
34,3S
36
37,38
39,40
41
42
43
44
4S
46
DIGITAL +Vs
GROUND
ENCODE
GROUND
DNC
ANALOG +Vs
DIGITAL -Vs
GROUND
-VEE
GROUND
DNC
GROUND
DNC
NC
ANALOG -Vs
-VEE
+Vcc
ANALOG INPUT
GROUND
D7
I
o
I
o
I
0
I
o
I
o
I
o
D,
D.
D,
D.
I
I
I
I
o
o
o
o
D,
I
o
I
o
Positive digital supply pin. Nominally + SV dc.
Circuit ground. All grounds should be connected together near the AD900S.
Convert command. TTL compatible, rising edge triggered.
Circuit ground. All grounds should be connected together near the· AD900S.
Do not connect. Internal test point.
Positive analog supply pin. Nominally + SV dc.
Negative digital supply pin. Nominally -S.2V dc.
Circuit ground. All grounds should be connected together near the AD900S.
Negative analog supply pin. Nominally -ISV dc.
Circuit ground. All grounds should be connected together near the AD900S.
Do not connect. Internal test point.
Circuit ground. All grounds should be connected together near the AD900S.
Do not connect. Internal test point.
Not internally connected.
Negative analog supply pin. Nominally -S.2V dc.
Negative analog supply pin. Nominally -ISV dc.
Positive analog supply pin. Nominally + ISV dc.
Analog input. Full scale of ± 1.024V.
Circuit ground. All grounds should be connected together near. the AD900S.
3-462 ANALOG-TO-DIGITAL CONVERTERS
AD9005
TIMING DIAGRAM
N+2
ANALOG
INPUT
ENCODE
oum!~;~4t~DZ0WA,~~
II
EQUIVALENT INPUT/OUTPUT CIRCUITS
ANALOG
INPUT
~
~
~DX
ENCODE~
BURN-IN CIRCUIT
--u-L
-+ 5V
5,
OV
f\J
ENCODE
5EE
(5,
WAVEFORMS
S2
f=250kHz
----+w
52
+5V
AD9005
f=5MHz
-.---1
+5V - -.....
-w
(L5B) Do
ANALOG IN
0,
T/H OUT
O2
AID IN
D.
DIGITAL +VS
04
ANALOG +Vs
Os
D.
-5.2V - -.....-
...-1 DIGITAL -VS
07
ANALOG -Vs
D.
+15V
+ Vee
O.1~
-15V
09
I--Nv.,.--e ALL CAPACITORS
IN ".F±10%
(M5B) 0" 1--JVv.,.---I RESISTORS IN
OHMS±5%
1kO
-VEE
LOAD
,--_ _...:G:...R...:O..:U..;..N:...D_ _........I RESISTORS
0'0
--4----1
O.1~
ANALOG-TO-DIGITAL CONVERTERS 3-463
APPLICATIONS INFORMATION
The AD9005 is a complete analog-to-digital converter. The
AD900S uses a subranging AID architecture enhanced by hybrid
technology. This includes an on-board track-and-hold amplifier,
on-board references, timing circuitry and output latches.
The analog input of the AD900S is fed directly into the internal
track-and-hold amplifier, thus eliminating the need for external
signal conditioning in many applications. This amplifier provides low input capacitance, and a bipolar (± l.024V) input
range. Normally reverse-biased Schottky diodes on the input
provide overrange protection. If the amplitude, bandwidth or dc
voltage level of the analog input signal calls for external signal
conditioning, it is advisable to use an amplifier with low harmonic distortion and low noise characteristics. Selection of such
an amplifier is difficult because the performance of the AD900S
will likely exceed that of most commercially available amplifiers.
A good choice would be the AD961O, a wideband, low noise,
current feedback operational amplifier. It is important to remember that band limiting the analog input signal can avoid
aliasing during the AID conversion process.
Nyquist limits. Because the conversion cycle begins with the
rising edge of the encode signal, a fast, clean rising edge will
also help to reduce any clock jitter.
When the ENCODE signal of the AD9005 goes HIGH, the
internal track-and-hold enters the hold state; after 6Sns, it
returns to track mode. In applications in which the AD9005 is
clocked slowly or intermittently (i.e., in burst mode), the encode signal should be returned to a logic LOW state during the
idle periods.
The ENCODE signal pulse width should also be adjusted so
that it is in the HIGH (hold) state for a minimum of 2Sns. This
ensures that the TIH enters the hold mode before the AID conversion takes place.
The AD900S has many appealing characteristics for 12-bit AID
converter applications. Its dynamic performance is state-of-theart in hybrid technology. Typical applications include radar,
missile guidance, digital oscilloscopes, waveform analyzers, medical instrumentation, electro-optics, communications and ESM.
Timing in the AD9005 is criticai, and careful measures must be
taken to support 12-bit accuracy. One simple way to enhance
the performance of the AD9005 is to synchronize the system
clock to a crystal oscillator. This will minimize any clock jitter,
a must for maintaining the spectral purity of analog signals near
TYPICAL AD900S APPLICATION
~464
ANALOG-TO-DIGITAL CONVERTERS
r--::-::-=.-.....-
+ 15V
:H~:-=.-....-
-15V
AD9005
analog and digital power pins, can be used to isolate the digital
noise from the analog circuits.
Layout Information
The accuracy of a 12-bit converter, especially one with the
dynamic performance level of the AD9005, requires that designers pay careful attention to printed circuit board layouts. Analog
signal paths should be impedance matched, with termination!
load resistors at or near package connections. Analog signal
paths should also be isolated from digital signal paths. Otherwise digital signals can be capadtively coupled into the analog
section of the circuit, degrading the overall performance of the
AID converter.
Noise on the circuit ground is often the limiting factor in AID
converter performance. Perhaps the most critical concerns of
circuit layout are the ground connections. To reduce ground
noise, a two-sided printed circuit board is recommended, the
component side being reserved (as much as possible) for a single, low impedance ground plane. The other side should be used
for all (possible) power and signal connections. Each of the
ground connections of the AD9005 should be connected to the
ground plane, and most of the area under the AD9005 should
be part of this ground plane. The metal case of the AD9005 is
connected to ground.
Digital switching noise on power supplies can also degrade converter performance. Because of this noise (inherent with TTL
logic), the digital power supplies of the AD9005 should be separated from the analog power supplies. In addition, each power
supply should be capacitively decoupled to ground. To accomplish this, a single large value capacitor with a high resonant
frequency (a IOI1F tantalum capacitor for example) should be
used on each of the AD9005's power supplies, at or near the
package. In addition, a lower value capacitor with good high
frequency characteristics (a O.II1F ceramic chip capacitor is recommended) should be connected to each power supply pin
connection.
Operation of the AD9005 requires that Pin 4, the output of the
internal track-and-hold, be connected to Pin 5, the input to the
AD9005's AID converter circuitry. A suggested layout, showing
this connection, is shown below.
A final suggestion regarding circuit layout concerns the use of
sockets. Ideally, parts should be soldered into boards in final
designs. If sockets must be used, individual pin sockets are
recommended to avoid lead inductance and capacitive coupling
between adjacent pins. Pin sockets are available from Amp,
part #6-330808-0.
For applications in which only single +5V and/or -5.2V supplies are available, a ferrite bead, placed in series between the
SUGGESTED LAYOUT
ENCODE
COMMAND
10p.F BYPASS ~
::~~-----=-i :.~
o
p~
(i) AU.UU.
D,
@--D.
@--D6
@-- D7
o
~~:
~
l
D11IMSB)
U:
!f~ BYP~Y'~r;.':~rro" ~""!
.,.v ~-I
PIN'
80
0
0
0
0
0
0
0
0
0
AD9005
0
0
80
G=: D,.
o
o
t\
o
o
~~
-~e~
CAPACITOR
o
o
o
0 0
0
0
0 0
0
0
0
0
0
0
0
0
~
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0 0
0
0
/
8
PIN 1
ANALOG
INPUT
GND PLANE SIDE
(As Viewed from Top)
SOLDER SIDE
(As Viewed from Top)
COMPONENT MOUNTING
(As Viewed from Top)
ANALOG-TO-DIGITAL CONVERTERS 3-465
•
EVALUATION CIRCUIT
I
X-TAL
TTL
OSCILLATOR
l{>-
r
'--
74HC04
CLOCK
'--- ENCODE
AN ALOG
IN
~
ILSB) DO
D1
D2
D3
1.5kO
1.5kO
500
1
~l
-----/
500
AD961 0
a:
04-
ANALOG IN
~y
-
~
D5 ..... 74HC374
_ LATCH
D6
D7 f-
AD900S
w
zZ
0
u
oafD9
D10
IMSB) D11
T/H OUT
C
AID IN
I
rff-
-
I
I
_NC"').iOCO ..... QOCftO ... N
1-1-1-1-1-1-1::1-1----
1kO
I/-
RECONSTRUCTED {O\.
WAVEFORM
;.
liiliiliiliiliiliilll liilii
1
DAC
lOUT
HDS-12S0
HOS~~
Contact factory about evaluation board availability.
AD900S DYNAMIC PERFORMANCE (@ +2S°C)
80
77
....
r-- ..... ~Io.,
"C
I
a:
71
68
2jD
SNR
-77
3RD HARMONIC
III 74
Z
(/)
-80
I
~
"C
iiRlili~ ........ to-....
I I "" I
-74
U
Z
o
-71 ~
a:
-VREF under all circumstances.
'Typical thermal impedances:
68·pin leaded ceramic chip carrier alA = 310C1W; ale = 1.l0ClW.
68·pin ceramic LCC alA = 360C1W; a le =2.60C1W.
'Subgroups apply only to military qualified devices.
'Measured with analog input = OV.
"Measured with use of Fast Fourier Transform (FFT). See Definitions.
70utputs terminated through 1O0{} to -2.0V; CL <4pF
8Measuted from 50% point of leading edge of ENCODE command to -I.3V point of output data.
'Output time skew includes HIGH·to-LOW and LOW-to-HIGH transitions as well as bit-to-bit time skew differences.
IOMeasured from 50% point of trailing edge of ENCODE command to 50% point of Data Ready pulse.
"For fun scale step input, 6·bit accuracy is attained in the specified time.
12Recovers to 6-bit accuracy in specified time after 150% fun scale input overvoltage.
"ENCODE command rise/fall times should be less than 2.5ns for normal operation.
14Measured at 400MSPS encode rate; input level 1.0dB below fuD scale (FS).
"RMS signal to rms noise with analog input signal of IdB below fun scale at specified frequency.
I"Intermoduiation measured with analog input frequencies of 60MHz and 70MHz at 7dB below full scale.
17Measured at +Vs= +5.0V :!:5% or -Vs= -5.2V :!:5%; speciftcation shown is for worst case (see DefInitions).
Specifications subject to cha..-'1gt without notice.
EXPLANATION OF TEST LEVELS
EXPLANATION OF SUBGROUPS
Test Level
Subgroup I
-
I
II
-
Subgroup 2
-
III
IV
-
Subgroup 3
-
-
V
VI
-
Subgroup 4
Subgroup 5
Subgroup 6
-
Subgroup 7
Subgroup 8
-
Subgroup 9
Subgroup 10
-
Subgroup 11
-
Subgroup 12
-
-
100% production tested.
100% production tested at +25°C, and sample tested
at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
All devices are 100% production tested at + 25°C.
100% production tested at temperature extremes for
extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
3-470 ANALOG-TO-DIGITAL CONVERTERS
-
-
Static tests at + 25°C. (5% PDA calculated
against Subgroup I for high-rei versions)
Static tests at maximum rated operating
temperature.
Static tests at minimum rated operating
temperature.
Dynamic tests at + 25°C.
Dynamic tests at maximum rated operating
temperature.
Dynamic tests at minimum rated operating
temperature.
Functional tests at + 25°C.
Functional tests at maximum and minimum rated temperatures.
Switching tests at + 25°C.
Switching tests at maximum rated operating temperature.
Switching tests at minimum rated operating temperature.
Periodically sample tested.
Definitions - AD9006/AD9016
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectraL power of the
fundamental frequency (as determined by FFT analysis) is reduced by 3dB.
Overvoltage Recovery Time
The amount of time required for the converter to recover to 6bit accuracy after an analog input overvoltage signal of 150% is
reduced to the valid range of the converter.
Aperture Delay (tA )
The delay between the rising edge of the ENCODE command
(or falling edge of ENCODE) and the instant at which the analog input is sampled.
Pipeline Delay
This is equal to one clock cycle and is the delay between the
50% points on the rising edges of two successive ENCODE
commands (or falling edges of ENCODE commands).
Aperture Uncertainty Gitter)
The sample-to-sample variation in aperture delay.
Power Supply Rejection Ratio
The ratio of the change in power supply voltage to a
corresponding change in input offset voltage. In the AD9006
and AD9016 units, +Vs (+5V) or -Vs (-5.2V) are within
±5% of their nominal values for this test. Value shown in
SPECIFICATIONS is worst case.
Data Ready Output Delay (tDR)
The delay between the 50% point of the falling edge of the
ENCODE command (or rising edge of ENCODE) and the
-1.3V point of the leading edge of the DATA READY pulse.
Differential Nonlinearity
The deviation of any code from an ideal ILSB step.
Effective Number of Bits (ENOB)
Signal-to-noise ratio (see definition below) is expressed in dB;
but can also be expressed in Effective Number of Bits (ENOB)
if ENOB is related to full scale inputs as follows:
ENOB = (SNR -1. 78)/6.02
ENOB is calculated with a sine wave curve fit method.
In-Band Harmonics
The rms valu~ of the fundamental divided by the rms value of
the worst of the first six harmonics.
Integral Nonlinearity
This specification (often called "linearity error") is the deviation
of the transfer function from a reference line and is expressed in
either % or ppm of full scale range, or in fractions of ILSB. In
the AD9006 and AD9016 devices, this spec is measured in fractions of ILSB and uses a best-fit straight line determined by a
least square curve fit;
Output Delay (toD)
The delay between tlfe 50% point of the rising edge of the ENCODE command (or falling edge of ENCODE) and the -I.3V
point of output data.
Output Time Skew
Bit-to-bit time variations among Bits Do to Ds and the overflow
bit. In the AD9006 and AD9016 specifications, time skew includes HIGH-to-LOW and LOW-to-HIGH transitions of the
digital output bits.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude to the rms value of
"noise", which is dermed as the sum of all other spectral components, including harmonics but excluding dc, with an analog
input signal IdB below full scale.
Transient Response
The time required for the converter to achieve 6-bit accuracy
when a full scale step function input is applied to the unit.
Two-Tone Intermodulation Distortion (IMD) Rejection
The ratio of the power of a two-tone signal to the power of the
strongest third-order IMD signal.
RECOMMENDED OPERATING CONDITIONS
Input Voltage
Parameter
Min
Nominal
Max
+Vs
-Vs
+VREF
-VREF
ANALOG INPUT
+4.75
-5.46
-VREF
-1.1
-1.0
+5.00
-5.20
+1.0
-1.0
+5.25
-4.94
+1.1
+VREF
+1.0
ANALOG-TO-DIGITAL CONVERTERS 3-471
•
DIGITAL -VB
DIOrrAL-V.
OVERR.OW IMtIBtl'
BIT INVERT (Msal
D,-D.INVERT
GROUND
GROUND
NC
DATA READV.
NC
DaalLSBI
NC
OVERR.OW.
NC
MIDSCALE V REF
HYSTERESIS
DIGITAL -v.
DIGITAL -Va
OVERflOW INHIBIT
BIT INVERT IMsal
D.-D. INVERT
GROUND
Ne
GROUND
GROUND
NC
NC
NC
Ne
Ne
Ne
D...,(MSBI
NC
NC
D..
NC
NC
D~
D..
Ne
Ne
D.
Ne
Ne
Ne
~
D..
NC
D.
D,
NC
NC
Ne
Ne
Ne
D,
AD9016 Pin Designations
AD9006 Pin Designations
AD9006lAD9016 PIN DESCRIPTIONS
Not internally connected.
NC
ANALOG IN
Analog input connection. Analog input is
nominally between -l.OV and +l.OV.
ANALOG +Vs
Positive supply pins; nominally +5.0V.
+VREF
The positive reference voltage applied to
the internal resistor ladder.
+VSENSE
Voltage sense line to the most positive
reference voltage of the resistor ladder.
The sense line is intended for connection
to a high impedance node and has limited
current capability. It is intended to be
used to null offset at the top of the
reference ladder.
GROUND
OVERFLOW
INHIBIT
BIT INVERT
(MSB)
Analog and digital ground connections for
the AD9006/AD9016 units. For optimum
performance, all grounds should be
connected together and to a low impedance
ground plane as close to the device as
possible. [NOTE: On both the AD9006
and the AD9016, Pins 8, 9" 15, 16, 35, 36,
56 and 57 are digital ground (DGND);
pins 67 and 68 are analog ground
(AGND).]
Overflow bit control pin. OVERFLOW
INHIBIT is connected to ground for.
normal operation (no overflow bit,
nonreturn-to- zero operation). When
overflow inhibit is connected to -5.2V or
allowed to float, OVERFLOW = HIGH
and output bits = LOW when the analog
input voltage exceeds + VSENSE)'
Most significant bit (Dos) control pin. BIT
INVERT (MSB) is connected to ground
for normal operation. When connected to
-5.2V or allowed to float, MSB output is
inverted.
3-472 ANALOG-TO-DIGITAL CONVERTERS
Bits Do-D4 control pin, connected to
ground for normal operation. When
connected to - 5.2V or allowed to float,
Do-D4 data outputs are inverted.
OVERFLOWA
AD9016 only. Overflow data output for
Data Bank "A." Logic HIGH indicates
the analog input is greater than + VSENSE
when OVERFLOW INHIBIT pin is
LOW (-5.2V).
AD9016 only. Most significant bit (MSB)
digital data output of Data Bank "A."
AD9016 only. DIA through D4A digital
data outputs from Data Bank "A."
AD9016 only. Least significant bit (LSB)
digital data output of Data Bank "A."
DATAREADYA
AD9016 only. Output Data of Bank "A"
are valid at the rising edge of the DATA
READY A pulse. Bank "A" carries every
other sample of the AID conversion; Bank
"B" carries the remaining samples.
DIGITAL -Vs
Negative digital supply pins, nominally
-5.2V.
ANALOG -Vs
Negative analog supply pins, nominally
-5.2V.
OVERFLOWB
AD9016 only. Overflow data output for
Data Bank "B." Logic HIGH indicates
analog input is greater than + VSENSE
when OVERFLOW INHIBIT pin is
LOW (-5.2V).
AD9016 only. Most significant bit (MSB)
digital data output of Data Bank "B."
AD9016 only. DIB through D4B digital
data outputs of Data Bank "B."
AD9016 only. Least significant bit (LSB)
digital data output of Data Bank "B."
AD9006/AD9016
DATAREADYB
HYSTERESIS
AD9016 only. Output data of Bank "B"
are valid at the rising edge of the DATA
READYB pulse. Bank "B" carries every
other sample of the AID conversion; Bank
"A" carries the remaining samples.
The hysteresis control voltage varies the
amount of hysteresis in the internal
comparators. This pin normally floats at
-3.17V; making pin more positive
increases the hysteresis of the internal
comparators.
MIDSCALE
VREF
The midpoint tap on the internal reference
ladder; can be connected to an external
voltage to improve integral linearity of the
AID converter.
ENCODE
ECL-compatible noninverted input of the
encode command. The conversion cycle
begins on the rising edge of the ENCODE
signal.
ENCODE
ECL-compatible inverted input of the
encode command, used when a differential
encode signal is used. ENCODE should be
tied to a voltage corresponding to the
midpoint of the encode signal when a
single-ended encode signal is used.
-VSENSE
Voltage sense line to the most negative
reference voltage of the resistor ladder.
The sense line is intended for connection
to a high impedance node and has limited
current capability. It is intended to be
used to null offset at the bottom of the
reference ladder.
-VREF
The negative reference voltage applied to
the internal resistor ladder.
AD9006 only. Least significant bit (LSB)
of the output data.
AD9006 only. D. through D, digital data
outputs.
D5
AD9006 only. Most significant bit (MSB)
of digital data output.
OVERFLOW
AD9006 only. Overflow data output.
Logic HIGH indicates the analog input is
greater than + VSENSE when OVERFLOW
INHIBIT pin is LOW (-S.2V).
DATA READY
AD9006 only. Output data are valid at the
rising edge of the DATA READY pulse.
DATA READY
AD9006 only. Output data valid at the
falling edge of the DATA READY pUlse.
THEORY OF OPERATION
Refer to the block diagram of the AD9016 AID converter.
"Flash" architecture used in the AD9006 and AD9016 units
makes it unnecessary to use a track-and-hold (T/H) ahead of the
converter in many applications. The analog input signal is impressed across 64 parallel comparator stages.
Bias points of these comparators are established by the voltages
applied to the reference ladder via +VREF' MIDSCALEREF and
-VREF·
The outputs of the comparators are applied to the decoding
logic; from here, the data are applied to output latches as six
bits of digital data and an overflow bit. The overflow bit can be
used to stack converters to obtain additional bits of resolution
and can also be used as a "flag" for indicating positive out-ofrange inputs.
Capturing output data at the (guaranteed) encode rates of
470MSPS of the AD9016 is simplified by virtue of using two
Data Ready pulses. Output data words alternate between Bank
A and Bank B; this allows clocking demultiplexed data from the
AD9016 at half the converter's sample rate.
The Data Ready pulses track the propagation delay of the output data and relieve the need to build an external clock circuit
for tracking prop delay over the full operating temperature
range.
Demultiplexed ports connected to Bank A and Bank B allow the
user to capture output data with lOOK ECL logic even when the
converter is operating at 470MSPS. The AD9016 introduces
only one pipeline delay in the processing of these digital output
data, thereby reducing the number of clock cycles required to
obtain the digital representation of the analog input at the appropriate output port.
The analog input voltage range is determined by the usersupplied voltage references: +VREF and -VREF . The references
can be adjusted between -IV and +IV. In all cases, +VREF
should be greater than - VREF; and the differential voltage between the references should not exceed 2.IV. MIDSCALE
VREF can be used to improve the integral linearity of the
converter.
Another attractive feature of the analog input characteristics of
the AD9016 is its low input capacitance of 8pF. In many other
flash converters, this value is three or four times larger, making
them difficult to drive at high input frequencies.
For those applications in which a single output port is preferred,
the recommended choice is the AD9006 AID converter.
The AD9006 is identical to the AD9016 in performance specifications; it is best suited for systems in which demultiplexing is
not performed immediately after the flash converter. As in the
AD9016, the AD9006 produces Data Ready pulses on chip;
these can be used to clock external latches.
There are two control pins for determining the format of the
output data on the AD9006/AD9016. BIT INVERT (MSB) allows the user to invert the most significant bit (D0 5 ); and DoD, INVERT allows the five least significant bits to be inverted.
The AD9006/AD9016 Truth Table elsewhere in the data sheet
provides the necessary information to select among binary, inverted binary, twos complement and inverted twos complement
coding schemes.
ANALOG-TO-DIGITAL CONVERTERS 3--473
3
The OVERFLOW INHIBIT pin controls the overflow bit
(called out as OVERFLOW BIT in the AD9006, and OVERFLOWA and OVERFLOWB in the AD9016). In normal operation, the OVERFLOW INHIBIT is connected to -S.2V, and
OVERFLOW will be a digital HIGH whenever the analog input
voitageexceeds the most positive comparator reference
(+VSENSE)' The digital outputs (Do- Ds) will be LOW, i.e.,
returned-to-zero operation.
The DATA READY and DATA READY pulses of the AD9006
correspond, respectively, to the DATA READY BANK A and
DATA READY BANK B pulses of the AD9016. As shown in
the SPECIFICATIONS table, Data Ready Output Delay is
slightly.different in the two units: 3.2ns in the AD9006 and
3.6ns in the AD9016.
Availability and timing of a DATA READY pulse help in retrieving data from either the AD9006 or the AD9016. When
setting system timing, the user simply takes into account the
(single) pipeline delay and the Data Ready Output Delay (3.2ns
in the AD9006; 3.6ns in the AD9016) and uses the next DATA
READY (or DATA READY in the AD9006) to strobe the desired output into external circuits.
This feature means two AD9006 devices can be cascaded or
"stacked" to obtain seven-bit operation, as shown in the diagram below.
Connecting OVERFLOW INHIBIT to ground forces the
overflow bit to remain low and disables the retum-to-zero
operation.
Timing for the AD9006 and AD9016 is shown in their respective timing diagrams. In both illustrations, the complementary
encode command is shown in dashed lines.
N
ANALOG ______
INPUT
-i f-::----r----'\ ,------,.
ENCODE - - , '
ENCODE
N+3
_
-
-
N
,'- ____ JI'-_ _'I
,t
OD
f-4-
1
,
,I
1. . 1
DATA OUTPUT
---. ----N+2
N+l
===::k_j-+-.,.__~X,-_D_A_T_A_F_OR_N_.JX
DATA FOR N+l
:::itDR
x==
DATA READY
DATA READY
- APERTURE DELAY
too - OUTPUT DELAY
tpo - PIPELINE DELAY
to" - DATA READY OUTPUT DELAY
tA
AD9006 Timing Diagram
N-l
ANALOG -----.___
INPUT
'~
- - --l,
t--tA
r----.. ---- r----'
ENCODE~-'
N-l
ENCDDE
tp~
,
:
:::::1 t
op
DATA READY
BANK A
_ _ _ _ _~.
:~~AB
r----,
N+l
'- ____
J
N+2
' - ____
r-
J
I
'
I
!,\
:
________
DATA READY
BANK B
N
----"I'-----J!
--i~oE.Ji
:~~AA ~
N+2
N ~_ _ _ _ _ N+l
_ _ _- . . ...._ _ _-
XI...____D_AT_A_FD_R_N_ __
/
\... _ _ _ _ _- J .
~)(~
~
DATA FOR
N-l
N+l
=::ltOf"------,
\1.....____.
N-l
N
\
_ _ _ _ _ __
APERTURE DELAY
OUTPUT DELAY
... - PIPELINE DELAY
to. - DATA READY OUTPUT DELAY
tA
-
too -
AD9016 Timing Diagram
3-474 ANALOG-TO-DIGITAL CONVERTERS
AD9006/AD9016
APPLYING THE AD9006/AD9016
Setting Reference Levels
The AD9006/AD9016 requires that the user provide two voltage
references: +VREF and -VREF . These two voltages are applied
across the internal resistor ladder (nominally 800) and determine the analog input range of the converter.
Care should be taken to assure that these references are driven
from stable, low impedance sources. Reference connections
should be capacitively coupled to ground to reduce interference
generated by noise and/or digital switching.
Resistance between the reference connections and the point at
which the first comparator threshold is connected causes offset
errors. These errors, called "top and bottom of the ladder
offsets," can be nulled out using the + VSENSE and - VSENSE
connections. These sense lines are intended for connection only
to high impedance (low current) nodes such as the input of an
op amp.
Applying a voltage greater than 2.IV across the internal resistor
ladder will cause current densities to exceed rated values and
may cause permanent damage to the AD9006/AD90l6.The
amount of current available at the reference connections must be
limited.
One method of nulling the offset errors is shown in Figure I.
The Analog Devices ADI403 voltage reference supplies a
stable 2.SV reference for the circuit, and RUMIT determines
the range over which the reference can be adjusted. R\ adjusts
the voltage at the top of the internal reference ladder through
the AD642/2N3904 combination. Feedback from the +VSENSE
line causes the op amp to compensate for offset which appears at
the top comparator threshold. The transistor limits the amount
of current drawn directly from the op amp; resistors at the base
and emitter of the transistor stabilize its operation.
Voltage at the bottom of the reference ladder is controlled in
essentially the same way, using Rz to adjust the reference ladder
voltage; and using feedback from the - VSENSE connection to
null any offset between the reference and the threshold of the
bottom comparator.
The midpoint of the comparator reference ladder (MIDSCALE
VREF) is shown tied to ground in Figure 1. This allows the user
to adjust the voltage reference for minimum integral nonlinearity. This feature becomes important in applications with reduced
analog input ranges because integral nonlinearity increases under
these conditions.
2N3904
V~~i~~E
AD90061 AD9016
10
RUM"
REFERENCE t-""'~---1
1-----1
'---------------1
VouT =2.5V
+VREF
+VSENSE
MIDSCALE V REF
10k
10k
R, r--Y~~"""'Mr---------~--t
-VSENSE
10
2N3906
Figure 1. Reference Circuit
Driving the Analog Input
Careful design and layout of the AD9006/AD9016 have resulted
in a typical input capacitance of 8pF (9.SpF max). This is low
in comparison to most flash converters, but it is still a significant load at high input frequencies and must be taken into account when choosing a drive amplifier.
DC-coupled applications require the performance characteristics
of a wide bandwidth, low distortion op amp such as the Analog
Devices AD9611. AC-coupled applications at high frequencies
may be better served by using a low distortion gain block for
the driver.
Figure 2 illustrates possible connections for both approaches.
Regardless of which driving circuit is selected for the application, the overall dynamic performance of the amplifier is enhanced by inserting a small series resistor between the output of
the amplifier and the analog input of the converter.
Clocking the Converter
The encode command circuits of the AD9006/AD9016
(ENCODE and ENCODE) are designed to be driven by a differential ECL source.
ANALOG-TO-DIGITAL CONVERTERS 3-475
II
AD90061
AD9016
> .....__>I\Rs,.,..'""A~~~~
a.
AD90061
AD9016
ANALOG
SOURCE
150fi)
b.
Figure 2. Analog Input Circuits
A differential signal is recommended as the encode command to
reduce jitter of the encode signal; increased jitter raises the noise
floor of the converter. Full logic levels are preferred for triggering the clock circuits, but reduced levels can also be used. Caution should be exercised when using reduced-level encode commands because their slew rates will be decreased, which can
raise the noise floor.
Refer again to the timing diagrams for the AD9006 and AD9016.
The rising edge of the ENCODE signal initiates the conversion
process in the AD9006 unit. This same signal, delayed, becomes
the DATA READY and complementary DATA READY
pulses. Fast rise and fall times «0.5ns) and "clean" edges are
always required for encode commands, but are especially critical
for high frequency analog signals.
In the AD9016, the leading edges of the DATA READY A and
DATA READY B pulses are triggered by the trailing edge of an
ENCODE command. Their trailing edges are triggered by the
trailing edge of the next ENCODE command.
Although the AD9006lAD9016 is designed and tested to operate
with a 50% duty cycle, the dynamic performance at high encode
rates can be improved by changing the duty cycle.
Two possible methods of clocking the AD9006/AD9016 are
shown in Figure 3. Users planning to implement these circuits
need to be aware they may not function over the same temperature ranges possible with the converters.
Both ECL oscillators and saw filter oscillators are available as
comercial products, with each type operating at some preselected frequency. The type of oscillator which is selected is a
AD90961
AD9016
function of the desired operating frequency for the circuit being
designed.
Layout and Power Supplies
Correct layout of high speed circuits is always critical, but is
particularly important when both analog and digital signals are
involved.
Analog signal paths should be kept as short as practical, and be
properly terminated to avoid reflections and signal distortions.
The analog input and voltage references should be kept away
from digital signal paths; this reduces the possibility of capacitvely coupling digital switching noise into the analog section of
the circuit.
Digital signal paths should also be kept short, and digital run
lengths should be matched because propagation delays through
digital paths become significant at high data rates. Proper ECL
terminations should be used at or near the packages containing
successive gates.
Ideally, analog signal paths and digital signal paths should be
routed as far away from one another as possible and should
never closely parallel one another's paths. If they must cross,
they should do so at right angles to avoid interference.
In any layout of high speed circuits, the layout of ground connections is the most important factor. To reduce noise and interference on the circuit ground, a double-sided copper-clad
printed circuit board (PCB) is recommended. Every part of the
board not used for components or conducting runs should be
ground plane. Components are mounted on one side; the opposite side is used for power and signal connections.
SAW FILTER
OSCILLATOR
SINE WAVE
OUT
a.
b.
Figure 3. Clock Circuits
3-476 ANALOG-TO-DIGITAL CONVERTERS
,......-~.,
ENCODE
AD9006/AD9016
At least one high quality tanatalum capacitor of 31J.F- 20IJ.F
should be assigned to each power supply voltage, mounted as
near a6 possible to the incoming power pins to minimize low
frequency ripple.
It is especially important to retain the continuity of the ground
plane under and around the AD9006/AD9016 converter. If the
system design separates the digital and analog ground returns,
both should be connected together and to ground close to the
unit to form a continuous ground plane around the AID section
of the system.
Low noise, low ripple temperature-stable linear power supplies
are the preferred choices for high speed circuits. Switching
power supplies often seem to meet these criteria, including ripple specifications. But ripple specs are generally expressed in terms
of rms - and the spikes generated in switchers can produce hardto-filter, uncontrollable noise peaks with amplitudes of several
hundred millivolts. Their high frequency components may be
extremely difficult to keep out of the ground system.
If switching power supplies cannot be avoided for high speed
designs, they should be carefully shielded and their outputs
should be well filtered.
Handling the AD9006/AD9016 Package
Several precautions have been included in the design of the
AD9006/AD9016 converter to help reduce its sensitivity to electrostatic discharge (ESD). But the user should always use normal ESD precautions to help insure device reliability and avoid
degrading the unit's performance.
Package options which are available include both leaded and
leadless 68-pin ceramic chip carriers; these are shown in the data
sheet as leaded ceramic chip carrier and leadless chip carrier
(LC), respectively. Both of these packages have been specially
designed to maintain the converter's high frequency parameters
while operating over a standard military temperature range.
Regardless of package type, the top of the package (containing
the model number and the Analog Devices logo) is internally
connected to the device substrate and is designed to be used as a
heat sink. The substrate is connected to -V s internally; therefore the top of the package should be allowed to "float" in voltage. The bottom of the package is not connected internally on
the device.
Every power supply line leading into a high speed PCB or data
acquisition circuit must be carefully bypassed to its ground return to prevent noise from entering the circuit. Ceramic capacitors, ranging in value from O.OIIJ.F to O.IIJ.F, should be used
generously in the layout, mounted as closely as possible to the
device or circuit being bypassed.
The capacitors which are used should have a high resonant frequency to insure they maintain their characteristics in the range
of frequencies involved in the encoding process. Ceramic surface
mount (chip) capacitors meet that requirement and are easily
placed near the package connections.
High speed devices such as the AD9006/AD9016 converters
should be soldered into final applications. There is a temptation
to use sockets, but they can limit dynamic performance and
should be used only for evaluation or prototype applications.
Input Voltage
(FS=±1.0V)
True
Inverted
00
01
-1.000
MSB INVERT = I
Do-D4 INV =1
000000
MSB INVERT=O
Do-D4INV=0
111111
MSB INVERT=O
Do-D4INV=1
100000
MSB INVERT = I
D o-D4 INV=0
011111
-0.968
000001
1lI110
100001
011110
31
32
33
-0.031
0.000
+0.031
011111
100000
100001
100000
01l1ll
011110
111111
000000
000001
000000
111111
1I1110
62
63
63+
+0.938
+0.969
+ 1.000
1I1l10
111111
(0)1 1lI 11*
(1)000000#
000001
000000
(0)000000*
(1)111111#
011110
011111
(0)011111*
(1)100000#
100001
100000
(0)100000*
(1)0111l1#
Step
Binary
Offset Twos Complement
True
Inverted
·OVERFLOW INHIBIT = "I"; #OVERFLOW INHIBIT = "0."
The overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT, Do-D, INVERT
and OVERFLOW INHIBIT are considered de controls. They are tied to ground for logic "I" and -Vs for logic "0"; their
"trip point" occurs at approximately -1.3V.
AD90061AD9016 Truth Table
ANALOG-TO-DIGITAL CONVERTERS 3-477
11
-10
,...,-
FUNDAME;"'Ai.
-2
, FUNbAME!TAL
"'"
-4
-6
A,.=±O.75V (75% of ±1V FS)
'"
-8
....,
-10
-12
/
-14
H
~
OFFSET
-1.
2NDiARMINIC
-18
-20
~
~
_
~
m
~
'"
-)(,
"'-
~
A1N =±O.25V (25% of :!:1V FS)
-18
....,
-20
.,/
-22
-24
./
~
~
~
~
~
0.0
+0.5
- If
~
~
~
~
"
-
~
~
Harmonics vs. Input Frequency - Small Signal
i~lL1JHft1
-0.5
I
INPUT FREQUENCY - MHz
Harmonics vs. Input Frequency - Large Signal
-1,0
I
V F '\.
",
I
,,/
2ND HARMONIC
/
INPUT FREQUENCY - MHz
-
----. , /
3RD HARMONIC -
-30
~
-
-16
-28
I
I
...........
-14
-26
rJ.
IH_
3RD tARM~NIC
"
r--....
-12
~
5.8
..........
+1.0
---
5.4
r- ......
ANALOG INPUT - Volts
Input Capacitance vs. Input Voltage
26
~
75
100
126
5.0
i'--
1~
175
200
4 .•
""
m
]1
DC BIAS
ANALOG IN
TO
~------.. COMPARATOR
STAGES
500MHz
~liiiIiI!!!Il3lJ de
o
_10MHz
DC BIAS
I
I
a6D
ANALOG -Vs
Equivalent Analog Input
3-478 ANALOG-TO-DIGITAL CONVERTERS
250MHz
w
~
..
a:
w
::>
z
~
4.2
SNR and Effective Number of Bits (ENOB) vs. Input
Frequency
+vs
0
Z
:IE
INPUT FREQUENCY - MHz
ANAI.OG
..
,
..l!i
-i'
Normalized 50n Input Impedance vs. Input Frequency
i
AD9006/AD9016
DIGITAL
GROUND
+VREF
100.
+VSENSE
R/2
7 ~y...+--R
R
•
R/2
MIDSCALE
V REF
R/2
Encode and Encode Equivalent Circuits
R
100.
-VSENSE
R
65}'Vy...-+---
DIGITAL
GROUND
R/2
-VREF
800.
R=64"= 1.250.
DIGITAL BITS
AND OVERFLOW
*
"'V'I/'v-
=WIRING RESISTANCE = <20.
_ _ _ =TO COMPARATORS
Equivalent Digital Outputs
Reference Ladder
0
-20
III
-20
I-+-t--+-+--+-+--t-+-HH
-40
."
-60
-80
-60
-100
MHz
200
DC
MHz
200
FFT 01 AD80061 AD9016
FFT of AD9006IAD9016
400MSPS: FIN = 14.8MHz; VIN = 1.0dB Below FS
400MSPS: F'N= 192MHz; V'N= 1.0dB Below FS
ANALOG-TO-DIGITAL CONVERTERS 3-479
~
~
»
~
.....
Q
ANALOG
INPUT
rtl
o
D.
ANALOG INPUT
~
NOTE: DIGITAL OUTPUTS MUST
BE TERMINATED TO -2V
TiffROUGH 100.0.
D4
~
.....
D_
~
AD9006
D2
~
D,
~
Do
:lj
C/)
) OVERFLOW
•
I
0 OVERFLOW
ECl
I CLOCK
OVERFLOW
D. (MSB)
D.
D.
D4
D4
AD9006
D_
D_
D2
D.
D,
D,
Do (lSB)
Do (lSB)
Connections for 7-Bit Operation
,.')
r~
~
C1
C
I
ENCODE
DATA READYA
ENCODE
~
~
~4-ID
BANKAI
DATA
I
01
•
--\ClK
6,
7
ENCODE
REFERENCE + 1V
VOLTAGE
CIRCUIT -1V
+VREF
6
AD9016
-VREF
lOUT
rt
FUll-SPEED
DATA
.--.--. CONNECTOR
HYSTERESIS
...."
»
DATA
READYB
BANKB
DATA
RECONSTRUCTED
WAVEFORM
6
.....
o
¢
1
ClK
):,.
6
D
ERROR
WAVEFORM
Q
LATCH
10051
MR
I
/
0
I
~
6
~
::I>
~
I"-
~
~
IAD9768
•
D/A
CONV.
lOUT
WVERT
ANALOG
INPUT
~
6/
-,---
~:lMIDSCAU V~,MSB
Cl
,
Do-D4
INVERT
-5.2V,
~
l"e
'i'>
HALF-SPEED
DATA
CONNECTOR
c
=
=
en
CD
AD90161PCB Block Diagram
;:.
=
~
~
-=en
CD
~
~
II
+5.0V
0.1"'F~
-5.2V
1
~
+Vs
-VS
...
OVRFLA
+1V
-1V
~
+VREF
D'A
~
-VREF
D4A
.....
V"
AD2
.....
AD3
..,
,.~
'
.
A'N
D'A
ENCODE
D'A
ENCODE
DOA
1000
INPUT
RESISTORS
ALL RESISTORS ±5%
ALL CAPACITORS ±20%
ALL SUPPLY VOLTAGES ±5%
0.1 ...F
STATIC:
,~
'.......
D'A
AD1
;
T
AD1= OV
AD2 = ECL HIGH
AD3 = ECLLOW
DY NAMIC:
-+1V
AD1
r~"
-
-0.9V
-1.7V
D'B
AD9016
D4B
ONLY
D'B
-1V
,~
D'B
D'B
GROUNDl
DOB
5100
LOAD
RESISTORS
~
AD90061AD9016 Burn-In Diagram
MIL-STD-883 Compliance Infonnation
The AD9006/AD9016TErrZ/883 devices are classified within
Microcircuits Group S7, Technology Group D (bipolar AID converters) and are constructed in accordance with MIL-STD-883.
The AD9006/AD9016 are electrostatic sensitive and fall within
electrostatic sensitivity classification Class I. Percent Defective
Allowance (PDA) is computed based on Subgroup I of the speci-
fied Group A test list. Quality Assurance (QA) screening is in
accordance with Alternate Method A of Method SOOS.
The following apply: Bum-In per lOIS; Life Test per l00S;
Electrical Testing per SOO4. (Note: Group A electrical testing
assumes TA = Tc = T J .) MIL-STD-883-compliant devices are
marked with "c" to indicate compliance.
ORDERING INFORMATION
Model
Temperature
Description
AD9006KE
AD9006KZ
AD9016KE
AD9016KZ
AD9006TEl883 '
AD9006TZl883
AD9016TEl883
AD9016TZl883
AD9016KElPCB
AD90161PCB
o to +70°C
o to +70°C
o to +70·C
o to +70°C
68-Pin Ceramic LCC
68-Pin Leaded Ceramic Chip Carrier
68-Pin Ceramic LCC
68-Pin Leaded Ceramic Chip Carrier
68-Pin Ceramic LCC
68-Pin Leaded Ceramic Chip Carrier
68-Pin Ceramic LCC
68-Pin Leaded Ceramic Chip Carrier
Evaluation Board; AD9016KE Installed
Evaluation Board; No Converter
-SsoC to + 12SoC
-SsoC to + 125°C
-55°C to +125°C
-SsoC to + 125°C
oto +70°C
o to +70°C
*See Section 14 for package outline information.
3-482 ANALOG-TO-DIGITAL CONVERTERS
Package
Options*
E-68A
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Z-68
8-Bit, 100MSPS
AID Converter
AD9011 I
r'IIIIANALOG
WDEVICES
FEATURES
On-Board Amplifier and Reference
100MSPS Encode Rate
Internal Input Clamping Circuit
Multiple Gain Selection
Bipolar Inputs
AD9011 FUNCTIONAL BLOCK DIAGRAM
I
APPLICATIONS
Radar Guidance
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM. ECCM. ESM)
GENERAL DESCRIPTION
The AD9011 is a high-speed 8-bit AID converter which includes
an amplifier and a voltage reference in the same package. The
integration of these functions in one package optimizes dynamic
performance while saving board space and design time.
The current-feedback amplifier in the AD9011 features an 80MHz
bandwidth at gains of -I, -2 and -4. Voltage gain is selectable
by applying the input signal to different pins. Internal clamping
circuits protect the input of the A/D converter while still maintaining fast overvoltage recovery times. The AD90 II also includes
a voltage reference with a drift of less than 4Oppml"C, providing
accurate operation over the full temperature range.
An 8-bit AID converter performs the high speed digitizing function
within the AD90lI. Fabricated in an advanced bipolar process,
this ADC provides excellent dynamic performance at low power.
The digital outputs are ECL compatible.
The AD9011 is available in two grades, one with 0.5LSB linearity
and one with 0.75LSB linearity. Both versions are offered as a
commercial temperature range device, 0 to + 70°C, and as an
extended temperature device, - 55°C to + 125°C. All grades are
packaged in a 24-pin metal DIP package.
ORDERING INFORMATION
Device
Linearity
Temperature Range
Description
Package
Options*
AD9011JM
AD9011KM
AD9011SMB
AD9011TMB
0.75LSB
0.5LSB
0.75LSB
0.5LSB
Oto + 70°C
Oto +70°C
-55°Cto + 125°C
- 55°C to + 125°C
24-PinDlP
24-PinDlP
24-PinDlP
24-PinDlP
M-24A
M-24A
M-24A
M-24A
*See Section 14 for package outline information.
ANALOG-TO-D/GITAL CONVERTERS 3-483
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS l
Positive Supply Voltage (Vex;) . . . . . . • . . . • . . • . +6V
Negative Supply Voltage (VEE) . . • . • • . • . • . . . . -6V
Analog Input Voltage (Pin 1)
. . ± 3V
Analog Input Voltage (Pin 2) .
• . ± 1.5V
Analog Input Voltage (Pin 3) .
. ±O.75V
Digital Input Voltage. . • . .
VEE to OV
ENCODE to ENCODE Differential Voltage
•. 4V
Digital Output Current . . . . . . . . . . •
.• 20mA
Reference Output Current . . . . . . . . . • . . . . . 20mA
Package Dissipation Limit ( + 250C Free Airy. ....... 3.3W
Operating Tenlperature Range
AD901 IJMlKM (Case) . . .
.. . . 0 to +70"C
AD9011SMBfTMB (Case)
- 55°C to + 1250C
Storage Tenlperature Range . .
-65°C to + 15O"C
Junction Tenlperature . . . . .
+ 165°C
Lead Soldering T enIperature (I Osee)
• . . . . +3000C
ELECTRICAL CHARACTERISTlCScvcc = +5V,Vf.( = -5.2V,G = -l,unlessothelWisestated)
Parameter
Test
Level
Temp
AD9011JMlAD9011KM
Typ
Min
Max
RESOLUTION
IV
Full
8
I
VI
I
VI
I
VI
I
VI
VI
I
VI
I
VI
+ 25°C
Full
+ 25°C
Full
+ 25°C
Full
+ 25°C
Full
Full
+25°C
Full
+ 25°C
Full
V
V
V
V
IV
V
Full
Full
Full
+ 25°C
+25°C
+ 25°C
I
V
V
V
V
V
IV
IV
V
+ 25°C
+ 25°C
+ 25°C
+25°C
+25°C
+ 25°C
+ 25°C
+ 25°C
+ 25°C
V
V
I
STATIC ACCURACY
Differential Nonlinearity AD90i ijMiSMB
AD901lKMITMB
Integral Noninearity
AD9011]MlSMB
AD901lKMITMB
No Missing Codes
Gain Error
Offset Errorl
ANALOG INPUT
Input Voltage Range Pin I (G= -I)
Input Voltage.!tange Pin 2 (G = - 2)
InputVoltageRangePin3(G= -4)
InputResistanceG= -I, -2,-4
Input Capacitance
Large Signal Input Bandwidth ( - 3dB)4
DYNAMICCHARACTERISTICS s,6
Maximum Conversion Rate
Output Data Delay7
Aperture Delay
Aperture Uncertainty
Transient Response (to ± ILSB)8
Overvoltage Recovery Time (to ± I LSB)9
Output Rise Time
Output Fall Time
Output Time Skew 10
In-Band Harmonics II
FIN = 1.248MHz, FS -ldB
FIN = 2.438MHz, FS - IdB
FIN = 9.3MHz, FS - IdB
Signal-to-Noise Ratio 12
FIN = 1.248MHz,FS-IdB
FIN =2.438MHz,FS-IdB
FIN = 9.3MHz, FS - IdB
ENCODE INPUT
Logic" I "Voltage"
Logic "0" Voltage"
Logic" I" Current
Logic "0" Current
Input Capacitance
Encode Pulse Width (Low)
Encode Pulse Width (High)
AD9011SMB/AD9011TMB
Typ
Min
Max
O.b
0.4
0.6
0.4
GUARANTEED
±0.2
±0.3
±6
2
I
0.5
IkO/lGI
2
80
0.6
0.75
1.0
0.5
0.75
1.0
1.2
0.5
1.2
0.4
0.6
0.4
GUARANTEED
±0.2
±0.5
± 1.0
± 1.0
±4
±13
±IO
2
I
0.5
IkO/lGI
2
80
5
0.75
1.0
0.5
0.75
1.0
1.2
0.5
1.2
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
± 1.0
±2.S
±4
±24
%FS
%FS
mV
mV
5
100
Vp-p
Vp-p
Vp-p
Ohms
pF
MHz
0.6
0.6
MHz
ns
ns
ps
ns
ns
ns
ns
ns
+ 25°C
+ 25°C
+2.5°C 46
60
58
50
46
60
58
50
dBc
dBc
dBc
V
V
I
+ 25°C
+ 25°C
+25°C 40
47
47
43
40
47
47
43
dB
dB
dB
VI
VI
VI
VI
V
IV
IV
-1.1
Full
Full
Full
Full
+25°C
+25°C 2
+2SoC 2
3-484 ANALOG-TO-DIGITAL CONVERTERS
100
Units
Bits
8
3.7
-1.6
15
11
20
3.7
-1.6
15
11
20
3.0
2.5
3.0
2.5
-1.1
-1.5
150
120
-1.5
150
120
3
3
2
2
V
V
fLA
fLA
pF
ns
ns
AD9011
AD9011jMlAD9011KM
Min
Typ
Max
Parameter
Test
Level
Temp
DIGITAL OUTPUTS
Logic "I" Voltage
Logic "0" Voltage
VI
VI
Full
Full
-l.l
POWER SUPPLY
Supply Voltage Vcc
Supply Voltage VEE
Supply Current Vcc
Supply Current VEE
Nominal Power Dissipation
VI
VI
VI
VI
VI
Full
Full
Full
Full
Full
4.75
-4.95
AD9011SMBlAD9011TMB
Typ
Min
Max
-l.l
-1.5
5.0
-5.2
63
240
1.56
5.25
-5.45
72
303
1.95
-1.5
4.75
-4.95
5.0
-5.2
63
240
1.56
5.25
-5.45
72
303
1.95
Units
V
V
V
V
rnA
rnA
W
NOTES
lAbsolute maximum ratings are limiting values, [0 be applied individually, and beyond which the serviceability of the circuit may be impaired.
Functional operation under any of these conditions is not necessarily implied. Exposure to absolute rating conditions for extended periods
of time may affect device reliability.
2Package dissipation limit ...
PD (watts) :::: IJ max - tA == {J max - te
0JA
0Je
Where tA :::::ambient; tc = case; tJ=juncrion 24-pin metal DIP 8jA =41.7°CIW; 6]c=7.T'CfW.
3Unused analog inputs floating.
4Determined by 3dB reduction in reconstructed output. For under sampled applications only, not meant to imply Nyquist operation.
50utputs terminated with lOOn resistors to - 2.0V.
6Measured at IOOMHz encode rate.
7Measured from ENCODE in to data out for LSB only.
RFor full-scale step inpUl, 8-bil accuracy is attained in the specified time.
9Recovers to 8-bit accuracy in specified time, after 150% full scale input overvoltage.
100utput time skew includes high-to-Iow and low-to-high transitions as well as bit-to-bit time skew differences.
IIHarmonic content below signal.
IlRMS signal to RMS noise, including harmonics.
11ENCODE and ENCODE are differential inputs which must be driven concurrently. ECL inputs within the specified ranges are guaranteed
to produce normal switching. ENCODE rise and fall time should be less than IOns for normal operation.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level I
Test Level II
Test Level III
Test Level IV
Test Level V
Test Level VI
100% production tested.
100% production tested at + 25°C, and sampled tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
All devices are 100% production tested at + 25°C. lOO"Al production tested at temperature extremes
for military temperature devices.
ANALOG-TO-DIGITAL CONVERTERS 3-485
FUNCTIONAL DESCRIPTION
Pin No. Name
Description
I
ANALOG INPUT
Analog input with internal gain of - I. Input signal should be s2V p-p. Unused analog inputs
should be grounded.
2
ANALOG INPUT
Analog input with internal gain of - 2. Input signal should be s IV p-p. Unused analog inputs
should be grounded.
3
ANALOG INPUT
Analog input with internal gain of - 4. Input signal should be sO.SV pop. Unused analog inputs
should be grounded.
4
ANALOG GROUND
One of two analog ground pins. All ground pins should be connected together near the AD90ll.
5
VEE
Negative analog supply pin. Nominally - S.2V. Best performance is attained with sepsrate
analog and digitsl supplies.
6
ENCODE
Noninverted input of the differential encode inputs. This pin is driven in conjunction with
ENCODE.
7
ENCODE
Inverted input of the differential encode inputs. This pin is driven in conjunction with
ENCODE.
8
BIT 8 (LSB)
Least Significant Bit (LSB) of digitsl data output.
9-12
BIT 7 -BIT4
Digital data output.
i3
VEE
Negativedigitsl supply pin. Nominally - S.2V. Best performance is attained with separate
analog and digitsl supplies.
14- 16 DIGITAL GROUND
Three offour digitsl ground pins. All ground pins should be connected together near the AD90ll.
17,18
BIT3,BIT2
Digitsl data output.
19
BIT I (MSB)
Most Significant Bit (MSB) of digitsl data output.
20
DIGITAL GROUND
One offour digitsl ground pins. All ground pins should be connected together near the AD90II.
21
DNC
Do not connect. Internal test point.
22
REFoUT
Output of internal reference. - 2V output@
23
ANALOG GROUND
One of two analog ground pins. All ground pins should be connected together near the AD90II.
24
Vcr;
Positive analog supply pin. Nominally + S.OV.
+ 12mA (max).
TIMING DIAGRAM
ANALOG
INPUT
N
+ 1
PIN DESIGNATIONS
•
ANALOGVcc
ANALOG GROUND
REFOUT
ANALOG GROUND
4
ONe
DIGITAL V..
5
DIGITAL GROUND
ENCODE
6
AD9011
ENCODE
7
TOP VIEW
INot to 5ealel
BIT 8 (LSB)
8
BIT1IM5B)
BIT 2
BIT 3
DIGITAL GROUND
3-486 ANALOG-TO-DIGITAL CONVERTERS
BIT 6
DIGITAL GROUND
BIT 5
DIGITAL GROUND
BIT 4
DIGITALVE£
AD9011
BURN-IN DIAGRAM
"::"
SIGNAL-TO-NOISE RATIO
50
AIN1
Vee ANLG
An..
ANLGGND
An..
REFOUT
NC
DNC
NC
"::"
48
"::"
ANLGGND
R1
.r-!
442
"::"
46
"::"
VEE DIG
DIG GND
0.1
"::"
BIT 1 IMSBI
ENC
RZ
562
BIT 8 (LSBI
-5.2V
)
40
"::"
"::"
0.1
I/
DIG GND
BIT 6
r
/
42
1kl!
DIG GND
BIT 5
DIGGND
BIT 4
VEE DIG
1kl!
~
\
56f,.
58
zND HARMONre
60
J
"::"
R1. R2 AND R3 % 1%
ALL OTHER RESISTORS %2%
ALL CAPACITORS %ZO%
ALL SUPPLY VOLTAGES %5%
54~
a::
~
38
36
100k
-5.2V
I
~
r\
BIT 3
-5.2V
BIT 7
..,
52,;!
['\11
!Il44
!
BITZ
1kl!
R3
1870
~
I
AD9011
ENC
--
48
50
II
SNR
"::"
"::"
1ooMS~S
62
1M
10M
ANALOG INPUT FREQUENCY - Hz
100M
INPUT/OUTPUT CIRCUITS
AD9011
...---.JVI,,-"--+--o REFoUT
ENCODE
ENCODEo--------t----~
-5.2V
AD9011
AD9011
DIGITAL
OUTPUT
ANALOG-TO-DIGITAL CONVERTERS ~7
I
APPLICATION INFORMATION
Input signals to the AD9011 are buffered through the on-board
amplifier/driver. Three separate input pins provide gains of - I,
-2 and -4. Only one input pin is used at a time, with the
other two pins connected to the analog ground. On-board input
clamping circuitry protects the internal flash AID convener
from overvoltage inputs, but the input signal to the AD9011
should not exceed the absolute maximums listed in the
specifications.
The AD9011 employs a differential encode input which requires
a drive signal to both the ENCODE and the ENCODE pins.
All levels are fully ECL compatible, and proper ECL terminations
should be used to avoid ringing and reflection.
The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tpo), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the data
transfer to the output latches, are triggered on the rising edge of
the ECL compatible ENCODE signal (see timing diagram).
Dramatic improvements in comparator design and construction
give the AD90Il excellent dynamic characteristics. The AD9011
provides outstanding error rate performance. Gross error codes
occur less than once in every 10 12 conversion cycles. This is
largely due to tight control of comparator offset matching. The
80MHz input bandwidth and low error rate performance give
the AD9011 an SNR (signal-to-noise ratio) of 43dB + with a
9.3MHz input. High SNR performance is panicu1arly imponant
in video bandwidth applications, where signals may pass through
the convener several times before the processing is complete.
Pulse signature analysis, commonly performed in advanced
radar receivers, is another area that is especially dependent on
high quality dynamic performance.
LAYOUT SUGGESTIONS
Designs using the AD9011, like all high-speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first requirement
is for a substantial ground plane around and under the AD9011.
Separate ground plane areas for the digital and analog components
may be useful, but the separate grounds should be connected
together at the AD90ll to avoid the effects of "ground loop"
currents.
The power supply pins must also be decoupled to ground to
improve noise immunity, O.I ....F and O.OI ....F chip capacitors
should be vety effective. The REFoUT pin will provide up to
12mA of current at the - 2.0V AID reference voltage. This pin
should also be decoupled to ground through a O.l ....F capacitor.
The analog input signal is brought into the AD9011 through
one of three input pins. The other two input pins should be
grounded to the analog ground plane. Active switching of the
input signal between the input pins is possible, but special care
must be taken to see that the unused inputs are grounded through
a low impedance, to avoid noise problems.
GROUND UNUSED ANALOG INPUTS
NOTE
All ECl OUTPUTS SHOULD BE
TERMINATED TO -2V WITH 1000
RESISTORS. OR ANY OTHER SUITABLE
ECl TERMINATION SCHEME.
AtN' :5±1V p-p
A'N2 :5 ± O.SV p-p
A'N3 :5 ± 0.2SV p-p
ANALOG
INPUT
AD9011
±1V p-p
Os (lSB)
A'N'
A'N2
-=
50
A'N3
-=
-=
ENCODE
INPUT
(GROUND THRESHOLD)
D.
0.'
~
07
06
REFouT
ENCODE
D.
03
O2
ENCODE
-=
0, (MSB)
50
-=
~_--4_ _"""_---JTO.O'
Tvpical A 090 11 Application
3-488 ANALOG-TO-DIGITAL CONVERTERS
High Speed 8-Bit
TTL AID Converter
AD9012 I
~ANALOG
WDEVICES
FEATURES
100MSPS Encode Rate
Very Low Input Capacitance - 16pF
Low Power - 1W
TTL Compatible Outputs
AD9012 FUNCTIONAL BLOCK DIAGRAM
oy~~~~w
2r--------------,
AD9012
ANALOG IN
APPLICATIONS
Radar Guidance
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM. ECCM. ESMI
Communication/Signal Intelligence
II
R
OVERFLOW
D. (MSBI
R
2"
GENERAL DESCRIPTION
The AD9012 is an 8-bit, ultrahigh speed, analog-to-digital
converter. The AD9012 is fabricated in an advanced bipolar
process, which allows operation at sampling rates up to 100
megasamples/second. Functionally, the AD9012 is comprised of
256 parallel comparator stages whose outputs are decoded to
drive the TTL compatible output latches.
The exceptionally wide large signal analog input bandwidth of
l60MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9012 allows very accurate acquisition of
high speed pulse inputs without an external track-and-hold. The
comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
REFM10 12
R
2
D,
D,
R
ENCODE
D, (LSBI
7}-~~-------t---------J
GND
HYSTERESIS
-Vs
+Vs
The AD9012 is available in two grades, one with O.5LSB linearity
and one with O.75LSB linearity. Both versions will be offered in
an industrial grade, - 25°C to + 85°C, packaged in a 28-pin
DIP and a 28-pin PLCC. The military temperature range devices,
- 55°C to + 125°C, are available in ceramic DIP and LCC packages
and are compliant to MIL-STD-883 Class B.
PIN DESIGNATIONS
OVERFLOW INH
Z
HVS11:RESIS
3
ANALOG INPUT
5
ANALOG GROUND
8
ENCODE
7
DIGITAL Vs +
8
ANALOG GROUND
I
ANALOG INPUT 5
23 DIGITAL GROUND
25 D7
24 D.
ANALOG GROUND &
ENCODe 7
23 DIGITAL GROUND
AD9012
DIGITAL Vs + 8
TOP VIEW
(Not to Scalet
ANALOG GROUND ,
ANALOG INPUT 10
22 ANALOG Vs 21 ANALOG V.20 DIGITAL GROUND
ANALOG INPUT 10
,. ,.,
,.
".;: .;: " ".s ".s .I
+
l~
C
I
~
Q
ANALOG-TO-D/G/TAL CONVERTERS 3-489
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS l
Positive Supply Voltage ( + Vs) . . . . . . • . . . .
+ 6V
Analog to Digital Supply Voltage Differential ( - Vs)
O.5V
Negative Supply Voltage ( - Vs) .
- 6V
Analog Input Voltage . . . . . . .
- Vs to +O.5V
ENCODE Input Voltage
- O.5V to + 5V
OVERFLOW INH Input Voltage
- 5.2V to OV
Reference Input Voltage (+ VREF - VREF)2. -3.5V to +O.IV
Diffetential Refetence Voltage . . . . • . . . . • . . . . 2.IV
Refetence Midpoint Current
Digital Output Current . . .
Operating Temperature Range
AD9012AQ/BQ . . • . . .
AD9012SElSQrrElTQ/883
Storage Temperature Range .
Junction Temperature3 • • •
Lead Soldering Tempetature (IOsec)
±4mA
30mA
-25°C to +85"C
- 55°C to + 125°C
- 65°C to + 150°C
+ 175°C
+ 300°C
Electrical Characteristics (+Vs =+ 5.OV; - Vs =- 5.2V; Differential Reference Voltage =2.OV, unless otherwise noled)
Test
Parameter
Tem.p
Level
RESOLUTION
DC ACCURACY
Differential Linearity
Integral Linearity
No Missing Codes
AD90lZHQIBPIBN
AD90lZAQ/APIAN
Min
Mal<
Tn>
Min
8
8
0.6
0.75
1.0
1.0
+25OC
Full
+ 25°C
I
VI
I
Pull
VI
Full
VI
GUARANTEED
+25OC
Full
+25OC
Full
Full
I
VI
I
VI
V
6
10
7
15
18
+ 25°C
Full
+ 25°C
+25OC
+ 25°C
+25OC
1
VI
1
60
+25OC
0.6
Typ
0.4
0.4
1.2
Max
0.5
0.75
0.5
'.£
GUARANTEED
Sub·
Group4
Min
AD9Ol2SQISEI883B
Typ
Max
AD9012TQfTI!f883B
Mal<
Min
Tn>
Units
8
8
Bits
7
8
7
g
7,8
0.6
0.6
0.75
1.0
1.0
0.4
0.4
""
0.5
0.75
0.5
...
LSB
LSB
LSB
LSi)
GUARANTEED
GUARANTEED
INITIAL OFFSET ERROR
Topor"Reference Ladder
Bottom of Reference Ladder
Offset Drift Coefficient
ANALOG INPUT
Input Bias Currems
Input Resistance
Input Capacitance
Large Signal Baridwidth6
Analog Input Slew Rate 7
150
111
V
V
VI
V
V
64
+25OC
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
Aperture UncertaintyUitter)
Output Delay (tpo)8.9
Transient Response 1o
Overvoitage Recovery Time~1
Output Rise TimeS
Output Fall Times
Output Time Skew8• 12
+ 25°C
+25°C
+25°C
+ 25°C
+25OC
+:(5°C
+25OC
+ 25°C
+25OC
I
V
V
I
V
V
I
1
V
75
ENCODE INPUT
Logic" I" VoltageS
Logic "0" VoltageS
Logic "I" Current
Logic "0" Current
Input Capacitance
Encode Pulse Width (Low)13
Encode PnlsrWidth (High)"
Full
Full
Full
Full
+25OC
+ 25°C
+25OC
VI
VI
VI
VI
V
I
1
2.0
OVERFLOW INHIBIT INPUT
OV Iopul Current
Full
VI
3.2
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
100
200
60
150
18
110
64
75
6.6
3.2
8.0
4.3
2.5
200
16
160
440
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
V
+25OC
+25OC
+ 25°C
+ 25°C
+ 25°C
1
V
V
I
V
48
DIGITAL OUTPUT
Logic " ... Voltage
Logic "0" Voltage
Full
Full
VI
VI
2.4
+25OC
Full
+25OC
Full
+25OC
+25OC
+25OC
I
VI
1
VI
V
V
I
250
200
18
1
2,3
1
12
48
44
47.6
37
46
110
1
152
37.5
38.5
179
191
955
44
0.85
3-490 ANALOG-TO-DIGITAL CONVERTERS
64
75
6.6
9
3.2
8.0
4.3
9
9
7,8
7,8
7,8
7,8
2.0
0.8
250
220
4
4
2.5
2.5
2.5
33
152
955
44
0.85
15
18
250
1,2,3
200
16
160
440
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
15
18
100
200
60
150
18
110
64
75
6.6
3.2
8.0
4.3
200
16
160
440
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
46
1,2,3
1,2,3
2.4
0.4
37.5
38.5
179
191
I
2,3
1
2,3
18
1I0
6.6
8.0
4.3
2.5
2.5
2.5
250
200
. 55
50
44
47.6
37
48
46
250
955
44
0.8
37.5
38.5
179
191
2.5
11
MSPS
ns
ps
ns
ns
ns
ns
ns
ns
V
V
!LA
"A
pF
ns
ns
",A
7.5
Bits
dBc
dBc
dBc
dBc
dBc
2.4
152
",A
",A
kfl
pF
MHz
VI",s
55
50
44
47.6
37
0.4
33
mV
mV
mV
mV
",VI"C
Ilf"C
MHz
0.8
250
220
7.5
4
100
200
2.0
200
48
7
10
\3
7
0.8
250
210
4
2.5
6
25
2.5
2.4
33
150
4
55
50
44
47.6
37
0.4
10
7
60
7.5
55
50
6
\3
2.5
7.5
46
100
200
2.5
2.5
200
7
8
7
8
25
2.0
2.5
2.5
+25-OC
Nominal Power Dissipation
Reference Ladder Dissipation
Power Supply Rejection R@~io 19
200
16
160
440
10
\3
IS
18
25
0.8
250
220
ACLINEARITY"
Effective Bits IS
In-Band Harmonics
de to 1.23MHz
dcto9.3MHz
dcto 19.3MHz
Signal-te-Noise Ratio l6
Noise Power Ratio 17
Supply Current ( - 5.2V)
7
25
REFERENCE INPUT
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Input Bandwidth
POWER SUPPLY"
Positive SupplyCurrem (+ S.OV)
6
\3
0.4
33
152
955
44
0.8
37.5
38.5
179
191
2.5
V
V
mA
mA
mA
mA
mW
mW
mVIV
AD9012
NOTES
1Absolute maximum ratings are limiting values, to be applied individually,
and beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not necessarily
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2 + VREF 2: - VREF under all circumstances.
'Maximum junction temperature (tl max) should not exceed + 175'C
for ceramic packages, and + 150°C for plastic packages:
tl ~ PD (alA) + 'A
PD (alc) + tc
where
PD = power dissipation
alA ~ thermal impedance from junction to ambient ('C/W)
0Je = thermal impedance from junction to case (OCIW)
tA ~ ambient temperature ('C)
tc ~ case temperature ('C)
typical thermal impedances are:
Ceramic DIP alA ~ 56'C/W; alC ~ 20'CIW
Plastic DIP alA ~ 6O'C!W; alC ~ 20'CIW
Ceramic l.CC alA ~ 69'C1W; alc ~ 23'CIW
Pl.CC aIA~60'C!W; aIC~19'CIW.
4Su bgroups apply to military qualified devices only.
'Measured with Analog Input~OV.
6Measured by FFT analysis where fundamental is - 3dBc.
'Input slew rate derived from rise time (10'% to 90%) of full-scale step
input.
'Outputs terminated with two equivalent 'l.SOO type loads. (See load
circuit.)
"Measured from ENCODE into data out for l.SB only.
IOFor full-scale step input, 8-bit accuracy is attained in specified time.
11 Recovers to 8-bit accuracy in specified time, after 150% full-scale input
overvoltage.
l20utput time skew includes high-to-Iow and low-to-high transitions as well
as bit-to-bit time skew differences.
"ENCODE signal rise/fall times should be less than 30ns for normal
operation.
"Measured at 75MSPS encode rate. Harmonic data based on worst case
harmonics.
"Analog input frequency ~ I.23MHz.
16RMS signal to rms noise, including harmonics with I.23MHz analog input
signal.
17NPR measured @ 0.5MHz. Noise Source is 250mW (rms) from O.5MHz
to.sMHz.
"Supplies should remain stable within ± 5% for normal operation.
"Measured at - S.2V ± 5% and + S.OV ± 5%.
Specifications subject to change without notice.
Recommended Operating Conditions
LOAD CIRCUIT
Vs
Input Voltage
Parameter
Min
Nominal
Max
-Vs
+Vs
+VREF
-':V REF
Analog Input
-5.46
+4.75
-VREF
-2.1
-VREF
-5.20
5.00
O.OV
-2.0
-4.94
+5.25
+0.1
+VREF
+VREF
EXPLANATION OF TEST LEVELS
Test Levell
- 100% production tested.
Test Level II
- 100% production tested at + 25'C, and sample tested
at specified temperatures.
Test Level III
- Sample tested only.
Test Level IV
- Parameter is guaranteed by design and characterization testing.
Test Level V
- P'lrameter is a typical value only.
Test Level VI
- All devices are 100% production tested at + 25'C.
100% production tested at temperature extremes for
extended temperature devices; sample tested at
temperature extremes for commercial/industrial
devices.
TTL
OUTPUT
15pF
EXPLANATION OF SUBGROUPS
Subgroup I - Static tests at + 25'C.
Subgroup 2 - Static tests at maximum rated operating temperature.
Subgroup 3 - Static tests at minimum rated operating temperature.
Subgroup 4 - Dynamic tests at + 25'C.
Subgroup 5 - Dynamic tests at maximum rated operating temperature.
Subgroup 6 - Dynamic tests at minimum rated operating temperature.
Subgroup 7 - Functional teSts at + 25'C.
Subgroup 8 - Functional tests at maximum and minimum rated operating
temperatures.
Subgroup 9 - Switching tests at + 25'C.
Subgroup 10 - Switching tests at maximum rated operating temperature.
Subgroup II - Switching tests at minimum rated operating temperature.
Subgroup 12 - Periodically sample tested.
ORDERING INFORMATION
Device
Unearity
Temperature Range Description
Package
Options·
AD9012AQ
AD9012BQ
AD9012AN
AD9012BN
AD9012AP
AD9012BP
AD9012SQ/883B
AD9012SEl883B
AD9012TQ/883B
AD9012TE/883B
0.75LSB
0.50LSB
0.75LSB
O.50LSB
0.75LSB
0.50LSB
0.75LSB
0.75LSB
O.SOLSB
O.SOLSB
-
Q-28
Q-28
N-28
N-28
P-28A
P-28A
Q-28
E-28A
Q-28
E-28A
25°C to
25°C to
25°C to
25°C to
25°C to
25°C to
55°C to
55°C to
55°C to
55°C to
+ 85°C
+ 85°C
+ 85°C
+ 85'C
+ 85°C
+ 85°C
+ 125°C
+ 125"C
+ 125°C
+ 125°C
28-PinCeramic DIP, Industrial
28-Pin Ceramic DIP, Industrial
28-Pin Plastic DIP, Industrial
28-Pin Plastic DIP, Industrial
28-Pin PLCC, Industrial
28-Pin PLCC, Industrial
28-Pin Ceramic DIP, Military
28-Pin LCC, Military
28-Pin Ceramic DIP, Military
28-Pin LCC, Military
*See Section 14 for package outline information.
ANALOG-TO-OIGITAL CONVERTERS 3-491
•
FUNCTIONAL DESCRIPTION
Pin#
1
2
Name
Description
DIGITAL + Vs
OVERFLOW INH
One of three positive digital supply pins (nominally + 5.0V).
OVERFLOW INHIBIT controls the data output coding for overvoltage inputs (AIN;;. + VREF).
OVERFLOW ENABLED (FLOATING OVERFLOW INHIBITED (GND)
OF DI D2 D3 D4 D5 D6 D7 Ds
OF DI D2 D3 D4 D5 D6 D7 Ds
ANALOG
INPUT
1
0
V1N;;,+VREF
V1N<+VREF
3
HYSTERESIS
4
5
6
7
8
9
10
Ii
12
13
14
+VREF
ANALOG INPUT
ANALOG GROUND
ENCODE
DIGITAL +Vs
ANALOG GROUND
ANALOG INPUT
-VREF
REFMID
DIGITAL +Vs
DIGITAL -Vs
IS
16-19
20
21,22
DI(LSB)
D2-D5
DIGITAL GROUND
ANALOG -Vs
23
24,25
26
27
DIGITAL GROUND
D6,D 7
Ds(MSB)
OVERFLOW
28
DIGITAL -Vs
0
0
0
0
0
0
0
0
XXXXXXXX
1
1
XXXXXXX
X
1
1
1
1
1
1
The Hysteresis control voltage varies the comparator hysteresis from OmV to 10mV, for a change
from -5.2V to -2.2V at the Hysteresis control pin.
The most positive reference voltage for the internal resistor ladder.
One of two analog input pins. Both analog input pins should be connected together.
One of two analog ground pins. Both analog ground pins should be connected together.
TTL level encode command input. ENCODE is rising edge sensitive.
One of three positive digital supply pins (nominally + 5.0V).
One of two analog ground pins. Both analog ground pins should be connected together.
One of two analog input pins. Both analog inputs should be connected together.
The most negative reference voitage for the internai resistor iadder.
The midpoint tap on the internal resistor ladder.
One of three positive digital supply pins (nominally + 5.0V)
One of two negative digital supply pins (nominally -S.2V). Both digital supply pins should be
connected together.
Digital data output. DI (LSB) is the least significant bit of the digital output word.
Digital data output.
One of two digital ground pins. Both digital grounds pins should be connected together.
One of two negative analog supply pins (nominally - 5.2V). Both analog supply pins should be
connected together.
One of two digital ground pins. Both digital ground pins should be connected together.
Digital data output.
Digital data output Ds (MSB) is the most significant bit of the digital output word.
Overflow data output. Logic HIGH indicates an input overvoltage (V IN > + V REF), if OVERFLOW
INHIBIT is enabled (overflow enabled, floating). See OVERFLOW INHIBIT.
One of two negative digital supply pins (nominally - S.2V). Both digital supply pins should be
connected together.
0Y~~ril~W
2)-------..,
AD9012
ANALOG IN
R
0.,
R
2"
D.
R
2
D.
REFMlD 12
0.
0.
D.
R
ENCODE
D, (LSBI
7}-~---~-----~
GND
HYSTERESIS
-
v.
Functional Block Diagram
~2
0
0
ANALOG-TO-DIGITAL CONVERTERS
+ v.
AD9012
System Timing Diagram
+S.OV
I
DIGITAL
OUTPUTS
ANALOG
INPUT
ENCODE 0-.......1-..
I
I
256 COMPARATOR CELLS
L-VREF
-S.2V
Input/Output Circuits
~_ _"""-i0.1~
.----.,L-----L.....,
ALlflESl5TORS 0:5%
All CAPACITOfIS :!: 20%
ALL SUPPlY VOLTAGES :!:5"4
OPTION #1 (STATIC) AD1= -2.0V. ADZ= +2.4V
OPTION #2 (DYNAMICI SEE WAVEfORMS
MIL-STD-883 COMPLIANCE INFORMATION
The AD9012SD/SEffEffQ/883B devices are classified within
Microcircuits Group 57, Technology Group D (bipolar AID
converters), and are constructed in accordance with MIL-STD883. The AD9012 is electrostatic sensitive and falls within electrostatic sensitivity classification Class 1. Percent Defective
Allowance (PDA) is computed based on Subgroup I of the
specified Group A test list. Quality Assurance (QA) screening is
in accordance with Alternate Method A of Method 5005.
The following apply: Burn-In per 1015; Life Test per 1005;
Electrical Testing per 5004. (Note: Group A electrical testing
assumes t. = t., = tj.) MIL-STD-883-compliant devices are marked
with "C" to indicate compliance.
Burn-In Diagram
ANALOG-TO-DIGITAL CONVERTERS 3-493
Die Layout and Mechanical Information
OVERFLOW
INHIBIT
DIGITAL -Vs
'~'\
+VREF
- ~.
.~..
ANALOG\.
INPUT
•
•••
•
.•._--0. (MSBI
___1 _ - - 0 7
• •._ _-0.
DIGITAL
GROUND
ANALOG -Vs
DIGITAL
GROUND
_ _ _ _- 0 .
::. __- - 0•
Die Dimensions
Pad Dimensions
Metalization . .
Backing . . . .
Substrate Potential
Passivation
Die Attach
Bond Wire
3-494 ANALOG-TO-DIGITAL CONVERTERS
. 111 x 123x 15 (±2) mils
4x4 mils
. Gold
None
. -Vs
. Nitride
Gold Eutectic (Ceramic)
Epoxy (Plastic)
1-1.3 mil Gold; Gold Ball Bonding
AD9012
APPLICATION INFORMATION
LAYOUT SUGGESTIONS
The AD9012 is compatible with all standard TTL logic families.
However, to operate at the highest encode rates, the supporting
logic around the AD9012 will need to be equally fast. Two
possible choices are the AS and the ALS families. Whichever of
the TTL logic families is used, special care must be exercised to
keep digital switching noise away from the analog circuits around
the AD90l2. The two most critical items are the digital supply
lines and the digital ground return.
Designs using the AD9012, like all high-speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high-speed designs. The first requirement is for a substantial ground plane around and under the
AD90l2. Separate ground plane areas for the digital and analog
components may be useful, but the separate grounds should be
connected together at the AD9012 to avoid the effects of "ground
loop" currents.
The input capacitance of the AD90l2is an exceptionally low
l6pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the l60MHz
input bandwidth of the AD90l2, a hybrid amplifier like the
AD9610/AD9611 will be required. For those applications that
do not require the full input bandwidth of the AD90l2, some of
the more traditional monolithic amplifiers, like the AD846,
should work very well. Overall performance with monolithic
amplifiers can be improved by inserting a 400 resistor in series
with the amplifier output.
The output data is buffered through the TTL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tPD), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the data
transfer to the output latches, are triggered on the rising edge of
the TTL compatible ENCODE signal (see timing diagram).
The AD9012 also incorporates a HYSTERESIS control pin
which provides from 0 to IOmV of additional hysteresis in the
comparator input stages. Adjustments in the HYSTERESIS
control voltage may help to improve noise immunity and overall
performance in harsh environments.
The second area that requires an extra degree of attention involves
the three reference inputs, + VREF , REF MID, and - VREF • The
+ V REF input and the - VREF input should both be driven from
a low impedance source (note that the + VREF input is typically
tied to analog ground). A low drift amplifier should provide
satisfactory results, even over an extended temperature range.
Adjustments at the REFMID input may be useful in improving
the integral linearity by correcting any reference ladder skews.
The reference inputs should be adequately decoupled to ground
through O.IILF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; O.IILF and
O.OIILF chip capacitors should be very ~ffective.
The analog input signal is brought into the AD9012 through
two separate input pins. It is very important that the two input
pins be driven symetrically with equal length electrical connections.
Otherwise, aperture delay errors may degrade converter performance at high frequencies.
The OVERFLOW INHIBIT pin of the AD9012 determines
how the converter handles overrange inputs (AIN;;. + VREF). In
the "enabled" state (floating at - S.2V), the OVERFLOW
output will be at logic HIGH and all other outputs will be at
logic LOW for overrange inputs (return-to-zero operation). In
the "inhibited" state (tied to ground), the OVERFLOW output
will be at logic LO.W for overrange inputs, and all other digital
outputs will be at logic HIGH (nonreturn-to-zero operation).
The AD9012 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTERSIS
control pin). This level of performance is extremely important
in fault sensitive applications like digital radio (QAM).
Dramatic improvements in comparator design and construCtion
give the AD9012 excellent dynamic characteristics, namely SNR
(signal-to-noise ratio). The l60MHz input bandwidth and low
error rate performance give the AD9012 an SNR of 47dB with a
1.23MHz input. High SNR performance is particularly important
in broadcast video applications where signals may pass through
the converter several times before the processing is complete.
Pulse signature analysis, commonly performed in advanced
radar receivers, is another area that is especially dependent on
high quality dynamic performance.
Ik
.
-15V
-V"EF
ANALOG
INPUT
AIN
+VllfF
OVERFLOW
0
D.IMSBJ
(0 TO +2V1
D,
AIN
D,
AD9012
D.
D.
ENCODE
50
D.
D,
D, (LSB)
Typical AD9012 Application
ANALOG-TO-DIGITAL CONVERTERS 3-495
•
RECONSTRUCTED
OUTPUT
LINEARITY OUTPUT
(ERRORWAVEFORM)
430
50
100
50
...-_....._ _ _ _ _ _ _ _......_ _ -5.2V
+VREF
OVERFLOW
AIN
ANALOG
INPUT
(2V P-P MAX)
37.5
REFMID
"-VREF
50
EQUAL
DISTANCE
D.(MSB)
A'N
D7
AD9012
D.
ENCODE
D.
~
OF INHIBIT
r1>"
D.
7
L 4
AA
T S
C 8
H 4
3
25PIN"D"
CONNECTOR
D.
HYST.
D2
-=-
lk
D,(LSB)
CLK
560
-5.2V
-5.2V
+5.0V
0.01 T&.-_..........._ _ _....
TO.01
TIL
ENCODE
INPUT
74AS04
AD9012 Evaluation Circuit
70
65
2ND HARM~NIC
60
55
~
50
-- -.......
- HAR"?o:~
....
45
40
35
......
3RD
~N~'
r-,-...
~,
~~
'WITH HARMONICS
~.
HNPUT = 0.1dB BELOW FULL SCALE
ENCOpE RATEI = 7~M~P~
I
30
2
4
6 8 10
20
40
ANALOG INPUT FREQUENCY - MHz
Dynamic Performance
3-.496 ANALOG-TO-DIGITAL CONVERTERS
NOTE:
10124, ECL OUTPUTS, SHOULD
BE TERMINATED TO -2V WITH
loon RESISTORS.
60
100
High Speed 8-Bit
AID Converters
AD9028/AD9038
r'IIIANALOG
WDEVICES
FEATURES
300 MSPS Encode Rate
250 MHz Large Signal Input Bandwidth
Low Input Capacitance: 17 pF
Excellent SNR
Single -5.2 V Power Supply
Overflow Bit & Bit Invert Functions
1:2 Demultiplexed Outputs (AD9038)
AD9038 FUNCTIONAL BLOCK DIAGRAM
LSBs
MSB
INVERT INVERT
OVERFLOW
INHIBIT
43 OVERFLOW)
(MSBI
'"
44 D..
APPLICATIONS
Digital Oscilloscopes
Waveform Digitizers
Radar Receivers
Electronic Countermeasures
45 D....
~
Os....
i:i
47 0....
~
46
~
48 Dz•
g
49 Dz....
50 D,.
S, 004
(LSB)
MIDSCALE 87
V~,
GENERAL DESCRIPTION
The AD9028 and AD9038 are ECL-compatible 8-bit, high speed
flash analog-to-digital converters. Both are fabricated in an
advanced bipolar VLSI process which ensures exceptionally
wide analog input bandwidth (250 MHz) and encode rates up to
300 MSPS.
Output data for the AD9028 include Overflow and Data Ready
signals; control pins allow the user to invert the MSB and/or
LSBs. The AD9038 combines the features of the AD9028 with
on-board demultiplexing circuits to provide two sets of output
data. These ease the task of interfacing the converter by reducing the data rate to half the encode rate.
(Dotted Area Not Included in AD9028)
The analog input is designed for 0 to -2.0 volt operation. Sense
pins for the +VREF and -VREF inputs allow fnil-scale calibration of the input range; a tap at the midpoint of the reference
ladder is available to minimize integral nonlinearity. Dynamic
performance is enhanced by driving the ANALOG RETURN
pins with a buffered analog input; see the Applications section.
There are two linearity grades of each device. Commercial
temperature ranges of 0 to + 70°C and military temperature
ranges of - 55°C to + 125°C are available. Both components are
offered in a ceramic 68-pin LCe, and a ceramic 68-pin leaded
package. These packages are specially designed for low thermal
impedance.
ANALOG-TO-DIGITAL CONVERTERS 3-497
•
SPECIFICATIONS
ABSOLUTE MAXIMUM RATiNGS l
ANALOG INPUT . . . . . . . . . . . . . . . . . . . . -Vs to +0.5 V
ANALOG RETURN . . . . . . . . . . . . . . . . . . .0 V to + 2.0 V
-Vs to GROUND . . . . . . . . . . . . . . +0.5 V de to -6.0 V de
+VREF' -VREF' MIDSCALE VREF ...... -2.1 V to +0.1 V
+VREF to -VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 V
MIDSCALE VREF , +VSENSE ,-VSENSE Current. .... ±4 mA
MSB INVERT, LSBs INVERT, OVERFLOW INHIBIT,
ENCODE, ENCODE, HYSTERESIS . . . . . . . . - VS to 0 V
ENCODE To ENCODE . . . . . . . . . . . . . . . . . . . . . . . .4 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . 20 mA
ANALOG -Vs to DIGITAL -Vs . . . . . . . . . . . . . . ±0.5 V
Operating Temperature Range
AD9028/AD9038KE!KZ/JElJZ •.•..•....... 0 to +70°C
AD9028/AD9038TElTZ/SElSZl883 . . . . . . -SSOC to +l25°C
Maximum Junction Temperature2 • • • • • • • • • • • • • • • + 175°C
Lead Temperature (Soldering, lOsee) . . . . . . . . . . . . . +300°C
Storage Temperature Range . . . . . . . . . . . . -65°C to + 150°C
ELECTRICAL CHARACTERISTICS ~~:~~t~~s!; n:!Rd) = 0 v; -VREF = -2 V; ANALOG RETURN = 0 v.
Parameter (Conditions)
Temp
Test
Level
SubGroup'
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral NonLinearity
No Missing Codes
AD9028JE1JZ
SElSZ1883
Typ Mas
Min
AD9028KE1KZ
TElfZ1883
Typ
Min
Max
AD9038JE1JZ
SElSZ1883
Typ
Min
Max
AD9038KE/KZ
TEIfZII883
Typ
Min
Mas
Units
8
8
8
8
Bits
+25"C
Full
+25"C
Full
Full
I
VI
I
VI
VI
7
8
7
8
7,8
0.8
1.0
1.0
1.2
0.8
1.0
1.0
1.2
GUARANTEED
+25"C
Full
+25"C
+25"C
+ 25"C
I
VI
I
III
V
I
2,3
I
12
125
+25"C
Full
Full
Full
+25"C
Full
+25"C
Full
Full
I
VI
V
V
I
VI
I
VI
V
I
2,3
I
V
V
I
I
I
I
4
300
9
9
9
9
4.7
I
9
4.1
0.6
0.75
0.8
1.0
0.6
0.75
0.8
1.0
GUARANTEED
0.8
1.0
0.8
1.0
1.0
1.2
1.0
1.2
0.6
0.8
0.6
0.8
0.75
1.0
0.75
1.0
125
250
400
125
250
400
LSB
LSB
LSB
LSB
ANALOG INPUT
Input Bias Current
4
Input Resistance
Input Capacitance'
Analog Bandwidth'
REFERENCE INPUT
Reference Ladder Resistance
Ladder Tempco
Ref. Input Bandwidth
Reference Ladder Offset'
(Top)
Reference Ladder Offset'
(Bollom)
Offset Drift Coefficient
SWITCHING PERFORMANCE'"
+25"C
Maximum Conversion Rate
+ 25"C
Apenure Delay (tA)
Apenure Uncenainty (Jiller)
+25"C
Output Delay (100)
+25"C
+25"C
Output Rise Time
Output Fall Time
+25"C
+25"C
Output Time Skew
Data Ready
+25"C
Output Delay (tOR)
ENCODE INPUT
Logic" I" Voltage
Losic "0" Voltase
Logic" I" Current
Logic "0" Current
Input Capacitance
Pulse Width (High)'
Pulse Width (Low)'
Full
Full
Full
Full
.,.25"C
+25"C
+25"C
IV
IV
VI
VI
V
I
I
50
24
20
75
17
250
40
0.13
30
32
7
8
7
8
26
250
400
125
50
21
60
75
24
20
45
47
37
39
26
325
1.4
3
6
1.0
1.0
0.25
7.3
1.6
1.6
0.7
4.7
5.4
6.7
4.1
3-498 ANALOG-TO-DIGITAL CONVERTERS
21
60
75
24
20
300
-1.5
285
285
40
26
50
21
60
75
24
20
7.3
1.6
1.6
0.7
4.7
5.4
6.7
4.8
300
45
47
37
39
26
325
1.4
3
6
1.0
1.0
0.25
7.3
1.6
1.6
0.7
4.7
6.1
7.4
4.8
60
75
45
47
37
39
300
-L5
285
285
fJ.A
{}
{}
nrc
MHz
mV
mV
mV
mV
",V/"C
7.3
1.6
1.6
0.7
ns
ns
6.1
7.4
ns
125
100
3.6
2
I
",A
k!l
pF
MHz
325
1.4
3
6
1.0
1.0
0.25
MSPS
ns
ps, rms
-1.1
125
100
3.6
2
I
40
21
20
-1.1
-1.5
285
285
75
17
250
0.13
30
32
20
325
1.4
3
6
1.0
1.0
0.25
125
100
3.6
2
I
75
17
250
0.13
30
32
45
47
37
39
-1.1
125
100
3.6
2
I
50
20
-1.1
4
4
40
0.13
30
32
20
7,8
7,8
75
17
250
250
400
-1.5
285
285
ns
ns
V
V
",A
fJ.A
pF
ns
ns
AD9028/AD9038
Parameter (Conditions)
DYNAMIC PERFORMANCE'
Transient Response
Overvoltage Recovery Time
Effective Number of Bits
(ENOB)
Analog Input @ 9.3 MHz
@49MHz
@92MHz
In-Band Harmonics
Analog Input@ 9.3 MHz
@49MHz
@92MHz
Signal-to-Noise Ratio'
Analog Input @ 9.3 MHz
@49MHz
@92MHz
Signal-to-Noise Ratio'
(without harmonics)
Analog Input @ 9.3 MHz
@49MHz
@92MHz
Two-Tone Intermodulation
AD9028jE1JZ
AD9028KE1KZ
AD9038jE1JZ
SElSZ1883
TEffZ1883
SElSZ1883
Sub-
Temp
Test
Level
+25'C
+25'C
V
V
+25'C
+25'C
+25'C
I
I
I
4
4
4
7.0
6.5
5.4
7.1
7.0
5.8
7.2
6.5
5.4
7.5
7.0
5.8
7.0
6.5
5.4
7.2
7.0
5.8
+25'C
+25'C
+25'C
I
I
I
4
4
4
48
41
36
53
48
54
41
36
56
48
53
40
48
41
36
40
+25'C
+25'C
+25'C
I
I
I
4
4
4
44
40
33
45
43
36
45.5
33
47
43
36
44
40
33
45
43
36
+25'C
+25'C
+25'C
+25'C
I
I
I
I
4
4
4
4
45.5
43
38
42
48
46
43
49
45.5
43
38
42
48
46
43
49
45.5
43
38
42
48
46
43
49
Full
Full
VI
VI
1,2,3
1,2,3
-1.1
+2S'C
+2S'C
Full
+25'C
+25'C
V
I
VI
V
V
+25'C
I
Group'
Min
Typ
Max
Min
3
3
Typ
Max
Min
3
3
40
40
Typ
Max
AD9038KE1KZ
Min
TEfI'Z//883
Typ
Max
3
3
ns
ns
7.2
6.5
5.4
7.5
7.0
5.8
Bits
54
41
36
56
48
40
dBc
dBc
dBc
33
47
43
36
dB
dB
dB
45.5
43
38
42
48
46
43
49
dB
dB
dB
dB
3
3
48
Units
45.5
40
Bits
Bits
Distortion Rejection 10
DIGITAL OUTPUTS·
Logic "I" Voltage
Logic "0" Voltage
POWER SUPPLY
Analog Return
Negative Supply Current
(-Vs = -5.2 V)
Power Dissipation
Ref. Ladder Dissipation
Power Supply
Rejection Ratio (PSRR)
1
2,3
-1.1
14.4
390
1.2
-1.1
1.5
14.4
390
475
515
2.0
100
7
-1.1
-1.5
475
515
2.0
100
3
1.2
-1.5
14.4
430
495
550
2.2
100
3
1.2
1.5
14.4
430
mA
495
550
2.2
100
3
1.2
V
V
3
rnA
rnA
W
rnW
mVN
For applications assistance, phone Computer Labs Division at (919) 668-9511.
NOTES
IAbsolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
lTYPlcal thermal impedances:
68-pin leaded ceramic chip carrier a JA =31"C/W; a Jc = 1.1oCIW.
68-pin ceramic LCC aJA =36"CIW; aJc ""2.6"CIW.
"Subgroups apply only to military qualified devices.
"Measured with analog input = 0 V.
sSee definitions of specifications.
&outputs terminated through 100 n to -2.0 V; C L <4 pF
7ENCODE command rise/fall times should be less than 2.5 ns for normal operation.
t'lMeasured at 250 MSPS encode rate; analog return is tied to + I V de. (See text and diagrams.)
QltMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.
IOIntcrmodulation mcasured with analog input frequencies of 60 MHz and 70 MHz at 7 dB below full scalc.
Specifications subjcct to change without notice.
RECOMMENDED OPERATING CONDITIONS
Input Voltage
Parameter
Min
Nominal
Max
-Vs
+VREF
-VREF
ANALOG INPUT
ANALOG RETURN
-5.46
-VREF
-2.1
-VREF
Analog In
-5.2
0
-2.0
-4.94
+0.1
+VREF
+VREF
Analog In +2.0 V
ANALOG-TO-DIGITAL CONVERTERS 3-499
II
EXPLANATION OF SUBGROUPS
-
Subgroup
EXPLANATION OF TEST LEVELS
Subgroup
100% production tested.
100% production tested at +25"<:, and sample tested
at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
All devices are 100% production tested at +25"<:.
100% production tested at temperature extremes for
extended temperature devices; sample tested at temperature extremes for commerciall'mdustriaJ devices.
Subgroup
2
Test Level
I
II
-
III
IV
-
V
-
VI
-
-
-
4
Subgroup
Subgroup
5
Subgroup
6
-
-
Subgroup
Subgroup
-
-
Subgroup
Subgroup
9
Subgroup
11
-
Subgroup
12
-
10
-
Static tests at + 25"<:. (5% PDA calculated
against Subgroup I for high-rei versions.)
Static tests at maximum rated operating
temperature.
Static tests at minimum rated operating
temperature.
Oyuamic tests at + 25"<:.
Dynamic tests at maximum rated operating
temperature.
Dynamic tests at minimum rated operating
temperature.
Functional tests at + 25"<:.
Functional tests at maximum and minimum
rated temperatures.
Switcbing tests at + 25"<:.
Switcbing tests at maximum rated operating
temperature.
Switching tests at minimum rated operating
temperature.
Periodically sample tested.
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the rising edge of the ENCODE command
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Data Ready Output Delay
The delay between the 50% point of the falling edge of the
ENCODE command and the 50% point of the rising edge of
DATA READY A or DATA READY B.
Differential Nonlinearity
The deviation of any code from an ideal I LSB step.
Effective Number of Bits (ENOB)
ENOB is a measure of ac linearity and is calculated from a sine
wave curve fit according to the following expression:
ENOB = N - LOG2 [ rms error (actual)lrms error (ideal) 1
N is the resolution (number of bits) of the converter. The
actual rms error is the deviation from an ideal sine wave,
calculated from the converter outputs with a sine wave
input.
In-Band Harmonics
The rms value of the fundamental divided by the rms value of
the worst harmonic.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of I LSB using a "best straight line" determined by a least square curve fit.
Maximum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency tested drops by no more than 3 dB below the guaranteed limit.
3-500 ANALOG-TO-DIGITAL CONVERTERS
Output Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the 50% point of output data.
Output Time Skew
Bit-to-bit time variations among DO to D7 outputs. In
the AD9028 and AD9038 specifications, time skew includes
HIGH-to-LOWand LOW-to-HIGH transitions of the digital
output bits.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
8-bit accuracy after an analog input signal 150% of full scale is
reduced to the full scale (0 to -2 V) range of the converter.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage. In the AD9028 and AD9038 units, -Vs
(-5.2 V) is within ±5% ofits nominal value for this test.
Reference Ladder Offset
The deviation between the top (or bottom) comparator transition
voltage as measured at the analog input, and the voltage at the
+VREF (or -VREF ) pin. This is valuable in determining the
accuracy and adjustment range for ± V REF sources.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude to the rms value of
"noise," which is defmed as the sum of all other spectral components, including harmonics but excluding dc, with an analog
input signal I dB below full scale.
Transient Response
The time required for the converter to achieve 8-bit accuracy
when a step function is applied to the analog input.
Two-Tone Intermodulation Distortion (IMD) Rejection
The ratio of the power of either of two input signals to the
power of the strongest third-order IMD signal.
AD9028/AD9038
IJ
AD90281AD9038 Pin Designations
(Note: Chip Cavity Opening Is On Bottom of Package.)
Pin No.
Name
6,66
ANALOG INPUT
ANALOG RETURN
36
35
44-51
20-27
59,60
3, 17, 18, 29, 30, 33,
38,41, 42, 52, 53, 63
8
10
67
AD9028/AD9038 PIN DESCRIPTIONS
Function
DATA READY A
DATAREADYB
D7A-DOA
D 7D-DoD
ENCODE, ENCODE
GROUND
HYSTERESIS
LSBsINVERT
MIDSCALE VREF
9
MSB INVERT
OVERFLOW A
OVERFLOWB
OVERFLOW INHIBIT
13
57
4,32,40,64
5, 16, 31, 39, 54, 65
14
56
+VREF
-VREF
-VsANALOG
-Vs DIGITAL
+VSENSE
-VSENSE
11
43
19
Analog input is nominally between 0 and -2 Volts.
Normally grounded; supplies current to input comparator circuits. Pins can be
tied to postive potential (+ 2.0 V max), or buffered version of analog input to
reduce capacitance and enhance dynamic performance. (See Applications.)
Rising edge of signal can be used to externally latch DoA-D7A •
Rising edge of signal can be used to externally latch DoD-D7D •
ECL digital data from Data Bank A.
ECL digital data from Data Bank B.
Differential ECL convert signals.
All ground pins should be connected together.
Normally grounded; hysteresis control pin.
Normally connected to -Vs. When grounded, lower order bits are inverted.
Normally floating; midpoint of reference resistor ladder. Can be adjusted to
minimize integral nonlinearity.
Normally connected to -Vs. When grounded, MSB is inverted.
ECL-compatible output indicating ANALOG IN > +VSENSE.
ECL-compatible output indicating ANALOG IN > +VSENSE.
Normally floating or tied to -Vs. When grounded, OVERFLOW A and Bare
disabled; DO-D7 remain at ECL logic "1" when ANALOG IN> +VSENSE.
Normally 0 V; sets voltage reference at top of ladder.
Normally -2 V; sets voltage reference at bottom of ladder.
-5.2 Volts; analog supply voltage.
-5.2 Volts; digital supply voltage.
Voltage sense line to most positive comparator reference input.
Voltage sense line to most negative comparator reference input.
ANALOG-TO-DIGITAL CONVERTERS 3-501
THEORY OF OPERATION
Refer to the AD9038 Block Diagram. Both units use a "flash,"
or parallel, AID architecture. The analog input voltage range is
determined by an external voltage reference (+ VREP and
-VREP), nominally 0 to -2 V. An internal resistor ladder
diVides this reference into 255 levels, each representing a single
quantization level.
The AID conversion, triggered by the ENCODE signal, is performed by 255 comparators. The output of the comparators
indicates the appropriate quantization level of the analog input
signal. The decoding logi& processes the comparator outputs and
provides an 8-bit code to the output stage.
Flash architecture has an advantage over other AID architectures
because the conversion occurs in one step, and the performance
of the convener is limited primarily by the speed and matching
of the individual comparators. A state-of-the-an bipolar process
and careful comparator design give the AD9028/AD9038 excellent ac performance. A proprietary decoding scheme minimizes
error codes, and control pins allow the user to select among
Binary, Invened Binary, Twos Complement and Invened Twos
Complement coding.
APPLICATIONS
Voltage References
The AD9028/AD9038 requires that the user provide two voltage
references: +VREP and -VREP ' as shown in Figure 1. These
two voltages are applied across an internal resistor ladder (nominally 40 !l) and set the analog input voltage range of the convener. Each voltage reference should be driven from a stable,
low impedance source. The reference connections should be
capacitively coupled to ground to bypass noise.
+VSENSE
Applying a voltage greater than 2.1 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause permanent damage to the AD9028/AD9038. The
design of the reference circuit should limit the voltage available
to the references.
Resistance between the reference connections and the taps of the
first and last comparators causes offset errors. These errors,
called "top and bottom of the ladder offsets," can be nulled by
using the voltage sense lines, + VSENSE and -VSENSE' to adjust
the reference voltages. Current through the sense lines should be
limited to 100 IJoA.
The voltage at the midpoint of the resistor ladder, MIDSCALE
VREF, can be adjusted to improve the integral linearity of individual devices.
A suggested application in Figure 4 shows a reference circuit
which nulls out the offset errors using two op amps. Feedback
from the sense lines causes the op amps to compensate for the
offset errors. The two transistors limit the amount of current
dmwn directly from the op amp; resistors at the base and emitter stabilize their operation.
Analog Input Signal
The analog input circuit of the AD90281AD9038 consists of 255
comparator inputs and can be represented by a single tmnsistor
as shown in Figure 2.
AD90281 AD9038
14.}J\""'.....- -..
R
,,
-v. ANALOG
R
Figure 2. Preferred Analog Input Configuration
/2
~
Typically, the ANALOG INPUT has an input resistance of
100 k!l. Input capacitance is chamcterized in Figure 3.
MIDSCALE 67
VREF
R/2
With ANALOG RETURN (collector of the input tmnsistor)
connected to ground, collector base capacitance causes the analog input capacitance to be dependent on the analog input voltage. This varying capacitance is typical of flash conveners, and
requires that the ANALOG INPUT be driven from a low
impedance source. This source must be capable of driving a
capacitive load to avoid distorting the analog input signal at high
frequencies. In applications where the analog source cannot adequately drive the input capacitance, harmonic distortion will
increase; the effect will be greatest on the second harmonic .
,,
R
R
.
"'VVIr
= WIRING RESISTANCE =
_
= TO COMPARATORS
<1
n
Figure 1. Reference Ladder
3-502 ANALOG-TO-DIGITAL CONVERTERS
AC performance of the AD9028/AD9038 can be improved by
connecting the ANALOG RETURN to a dc voltage between
ground and + 1.5 V. This reduces the analog input capacitance
and lessens its dependence on the analog input voltage (see
Figure 3).
AD9028/AD9038
cancels the ac voltage between the ANALOG RETURN and
ANALOG INPUT connections, which minimizes the collectorbase component of the analog input capacitance. The analog
input capacitance characteristics under this condition are also
shown in Figure 3.
20
,.
'"
./
'1;. 11
I
~
~
,.
ANALOG RETURN
GROUNDED
~
In any of the configurations described above, the user should
drive the analog signal from a low distortion, low noise amplifier. A good choice is the AD961l, a wide bandwidth operational amplifier with excellent ac performance.
--t:
§ ,.'s
ANALOG RETURN
=
+1.5 V
0-
i'
Selection of the buffer is also iinportant for applications in
which the analog input signal is applied to the ANALOG
RETURN. The gain of the buffer should be set as close to I as
possible, and the buffer should have a low phase shift at the frequencies of interest. It must also be able to supply the current
required, typically 14 mAo
iE 13
,.
ANAj R"iAN =~ + , V
,."
-2.0
-1.5
-1.0
ANALOG INPUT CAw)
-
-0.5
VOLTS
Harmonic distortion at the ANALOG RETURN is not as criti-
Figure 3. Input Capacitance vs. Input Voltage
cal as that at the ANALOG INPUT, but should remain less
The circuits shown in Figure 2 and Figure 4 show the ANALOG RETURN driven by a buffered version of the sigual presented to the ANALOG INPUT. The dc level of this signal is
I V higher than the analog input, and thus reduces the analog
input capacitance as described above. In addition, the signal
than 40 dB (out to 100 MHz) to maximize converter performance. The input impedance at this node is approximately
6.5 kO in parallel with 25 pF. Monolithic wideband operational
amplifiers and closed loop buffers should be suitable for driving
this input.
-5.2 V
'OI1F~ ~O"I1F
-5.2 V
O"I1F~
-Vs
ANAY'bG DIGITAL
ENCODE
~'OI1F
GROUND
DOA- D7A
ENCODE
DATA READY A
ANALOG
RETURN
}o~_
LOGIC/DSP
DOB - D7B
AD9038
DATA READY B
OVERFLOW
INHIBIT
LSBslNVERT
R'B
ANALOG
INPUT
SIGNAL
MSBINVERT
Rs
ANALOG IN
~ERM
+VSENSE
~O"I1F
HYSTERESIS
MIDSCALE
+VREF
-5.2 V
+VREF
Figure 4. AD9038 Typical Application
ANALOG-TO-DIGITAL CONVERTERS 3-503
E
encode rate, converter performance is also improved (jitter
reduced) by using a crystal oscillator as the system clock.
Timing
In the AD9028, the rising edge of the ENCODE signal triggers
the NO conversion by latching the comparators. The falling
edge of the ENCODE signal returns the comparators to track
mode and triggers the Data Ready signal.
The AD9028 is designed to operate with a 50% duty cycle
ENCODE signal; adjusttnent of the duty cycle may improve the
dynamic performance of individual devices. Since the ENCODE
signal is driven differentially, the logic levels are not critical.
Users should remember, however, that reduced logic levels will
reduce the slew rate of the edges, and effectively increase the
jitter of the signal. ECL terminations for the ENCODE and
ENCODE signals should be as close as possible to the AD9028
package to avoid reflections.
ENCODE and ENCODE are ECL compatible and should be
driven differentially. Jitter on the ENCODE signal will raise the
noise floor of the converter. Differential signals, with fast clean
edges, will reduce the jitter in the signal and allow optimum ac
performance. In applications with a fixed, high frequency
N
N+2
N+l
N+3
ENCODE
--'X"-__
__+-___
D_AT_A_F_O_R_N_--'X
C
DATA FOR N+l
DATA READY A
DATA READY 8
- APERTURE DELAY
OUTPUT DELAY
t"" - PIPELINE DELAY
tDR - DATA READY OUTPUT DELAY
t.
too -
AD9028 Timing Diagram
N-l
ANALOG
INPUT
___
N+l
~t.
~--"'\
N-l
,'- ____
JI
N
---'I\...----JI
=:E±tPD~
!
:"~1AA =:J\ ~
R~:ci~A
N+2
'
--.fI
ENCODE --"'\
ENCODE
N
!
X'-____
i \"-______..J/
D_AT_A_FO_R_N_ _ __
~ t~Dr
_ _ _ _ __ _
-"X ;
::'1A8 _ _ _ _ _ _ _ _ _ _
DATA
READY 8
N
,
DATA FOR N-l
~tD·r-----,
\'--____1
N-l
t.
~R
N+l
\ ' -_ _ __
- APERTURE DELAY
too -
OUTPUT DELAY
t..., - PIPELINE DELAY
to. AD9038 Timing Diagram
3-504 ANALOG-TO-DIGITAL CONVERTERS
DATA READY OUTPUT DELAY
AD9028/AD9038
Output data of the AD9028, D OA-D7A and OVERFLOW A, as
well as the data ready signals, are also EeL compatible, and
should be terminated through 100 n to -2 V (or an equivalent
load). The output data can be latched on the rising edge of the
DATA READY A output. For the AD9028,the DATA READY
B output is simply the complement of DATA READY A.
Timing for the AD9038 is similar to the AD9028, except at the
output, where the data is demultiplexed to two separate ports.
Successive data samples alternate between the two ports, reducing the output data rate at either port to one-half the encode
rate. Data at port A (DOA-D 7A and OVERFLOW A) can be
latched externally using the rising edge of DATA READY A.
The rising edge of DATA READY B can be used to latch the
data at port B (DOB-D7B and OVERFLOW B).
The data ready outputs for both the AD9028 and AD9038 are
designed to track timing shifts over temperature.
Data Format
The format of the output data is controlled by the MSB
INVERT and LSBs INVERT pins. These inputs are dc control
inputs and should be connected to GROUND or -Vs. The
AD9028/AD9038 Truth Table gives information to choose
among Binary, Inverted Binary, Twos Complement and
Inverted Twos Complement coding.
The OVERFLOW INHIBIT pin controls how the converter
handles overflow situations (ANALOG INPUT> +VSENSE)'
For normal operation, the OVERFLOW INHIBIT is connected
to -Vs, and the output data bits (DOA-D7A "Or D OB-D7B) will be
at a logic LOW when ANALOG INPUT> + VSENSE (return to
zero operation). The overflow bit (OVERFLOW A or OVERFLOW B) will indicate this condition with a logic HIGH. When
the ANALOG INPUT is in range « + VSENSE), the overflow
bit will remain at logic LOW.
If the OVERFLOW INHIBIT pin is connected to ground, the
overflow bit will be disabled, and the output data will remain at
logic high for overflow conditions. The overflow bits are not
affected by the bit invert control pins (MSB INVERT and LSBs
INVERT).
Layout aod Power Supplies
Proper layout of high speed circuits is always critical, but is particularly important when both analog and digital signals are
involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
matched to avoid propagation delay mismatch. Proper ECL terminations should be located near the packages of successive
gates.
In high speed circuits, layout of the ground circuit is the most
important factor. A single, low impedance ground plane, on the
component side of the board, will reduce noise on the circuit
ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow
designers to layout signal traces without interrupting the
ground plane.
It is especially important to maintain the continuity of the
ground plane under and around the AD9028/AD9038. If the
system design separates the digital and analog grounds, analog
ground is the preferred ground point for the AID section of the
system.
The tops of the AD9028/AD9038 packages are internally connected to the device substrates, and electrically connected to
- Vs. The top of the package is designed to serve as a heat sink;
the bottom of the package is not internally connected.
Sockets limit the dynamic performance and should be used only
for prototypes or evaluation.
ANALOG-TO-DIGITAL CONVERTERS 3-505
II
2.
2.
30
30
••
. . . . r1
50
..
60
tNiHjMONICi/
.uyy
6
810
~
/V
2ND HARMONIC-Y
50
.
:~.
3RiiRjONIC
100
/
~i-"
,
60
60
V
I
L
40
20
!'
V
200
/
/
.... 3RO' HARMONIC
20
6 8 10
40
INPUT FREQUENCY - MHz
INPUT FREQUENCY - MHz
80
100
AD9028/AD9038 Harmonics vs. Input Frequency with
Analog Return Grounded
AD9028/AD9038 Harmonics vs. Input Frequency with
Analog Return Driven
III
..... ,
r'
O
..
~
, ... ..
DRIVEN
-~
7.2
.
ENCODE RATE=250 MSPS
ANAL£
RETURN
'j'<
",
.
...
GROUNDED
I
~
~
;:IE
... i!
::>
z
t;
'.0 ~
20
6
• 10
20
40
80
100
200
INPUT FREQUENCV - MHz
AD90281AD9038 SNR and ENOB vs. Input Frequency
GROUND
GAOUND~
KI
DIGITAL BITS
AND OVERFLOW
I
Encode and Encode Equivalent Circuits
3-506 ANALOG·TO·DIGITAL CONVERTERS
200
Equivalent Digital Outputs
AD9028/AD9038
Offset Binary
Step
Range
Ovrfl.
Inh.
0= -2 V
FS = OV
"0"
Twos Complement
True
Inverted
True
Inverted
MSB INV. = "0"
LSBs INV. = "0"
MSB INV. = "I"
LSBs INV. = "1"
MSB INV. = "1"
LSBs INV. = "0"
MSB INV. = "0"
LSBs INV. = "1"
256
256
255
254
;"'0.000
;",0.000
-0.008
-0.016
"1"
x
x
(1 )00000000
(0)111 III 11
11111111
11111110
(l) 11111111
(0)00000000
00000000
00000001
(1) I 0000000
(0)01111111
01111111
01111110
(1)01111111
(0)10000000
10000000
10000001
129
128
127
-0.992
-1.000
-1.008
x
x
x
10000000
01111111
01111110
01111111
10000000
10000001
00000000
11111111
11111110
11111111
00000000
00000001
02
01
00
-1.992
-2.000
<-2.000
x
x
x
00000010
00000001
00000000
11111101
11111110
11111111
10000010
10000001
10000000
01111101
01111110
01111111
The overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT,
LSBs INVERT, and OVERFLOW INHIBIT are considered dc controls.
AD90281AD9038 Truth Table
ALLRESISTOfIS±5%
~O.1"'F
AlL CAPAaTORS ±ZO%
ALL SUPPLY VOLTAGES d"4
STATIC: AD1 = 0 V
AD2 = ECLHlGH
AOO = ECLLOW
OYNAMIC:
AD1~=_~~:~
to-- 640",1--t
ADZ
=
Il.IUlJ1..fU1Jl =
U1.fl.flJlflIUU
--I5 ..-t--
AD3
-.jo.,jo-
MIL-STD-883 Compliance Information
The AD9028/AD9038TEfTZ/SElSZ/883 devices are classified
within Microcircuits Group 57, Technology Group D (bipolar
AID converters) and are constructed in accordance with MILSTD-883. The AD9028/AD9038 are electrostatic sensitive and
fall within electrostatic sensitivity classification Class 1. Percent
Defective Allowance (PDA) is computed based on Subgroup 1
of the specified Group A test list. Quality Assurance (QA)
screening is in accordance with Alternate Method A of Method
5005.
The following apply: Burn-In per 1015; Life Test per 1005;
Electrical Testing per 5004. (Note: Group A electrical testing
assumes TA=Tc=TJ .) MIL-STD-883-compliant devices are
marked with "C" to indicate compliance.
AD90281AD9038 Burn-In Diagram
ANALOG-TO-DIGITAL CONVERTERS 3-507
I
OVERFLOW lNHIBfT
MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . 178 x 148 x 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . .4 x 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . - Vs
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic
Bond Wire . . . . . . . . . . . . . 1.3 mil, Gold; Gold Ball Bonding
HYSTERESIS
ANALOG RETURN
-Vs DIGITAL
-VsANALOG
GROUND
ANALOG INPUT
MIDSCALE VAl.
ANALOG RfTURN
-Vs DIGITAL
-VsANALOG
GROUND
~-='F=
FJiiiillI!!!iiiiiii
ORDERING INFOP..M...<\TION
Model
Temperature
Description
Package
Options·
AD9028JE
AD9028KE
AD9028JZ
AD9028KZ
AD9028SE/883
AD9028TEl883
AD9028SZ/883
AD9028TZ/883
AD9038JE
AD9038KE
AD9038JZ
AD9038KZ
AD9038SEl883
AD9038TEl883
AD9038SZ/883
AD9038TZ/883
o to +70°C
o to +70°C
o to +70°C
o to +70°C
68·Pin Ceramic LCC
68·Pin Ceramic LCC
68·Pin Leaded Ceramic
68·Pin Leaded Ceramic
68·Pin Ceramic LCC
68·Pin Ceramic LCC
68·Pin Leaded Ceramic
68·Pin Leaded Ceramic
68·Pin Ceramic LCC
68·Pin Ceramic LCC
68·Pin Leaded Ceramic
68·Pin Leaded Ceramic
68·Pin Ceramic LCC
68·Pin Ceramic LCC
68·Pin Leaded Ceramic
68·Pin Leaded Ceramic
E·68A
E·68A
Z·68
Z·68
E·68A
E·68A
Z·68
Z·68
E·68A
E·68A
Z·68
Z·68
E·68A
E·68A
Z·68
Z·68
- 55°C to + 125°C
-55°C to +125°C
- 55°C to + 125°C
- 55°C to + 125°C
o to +70°C
o to +70°C
o to +70°C
o to +70°C
-55°C to + 125°C
- 55°C to + 125°C
-SsoC to + 12SoC
- 55°C to + 125°C
'See Section 14 for package outline information.
3-508 ANALOG·TO·DIGITAL CONVERTERS
ANALOG
WDEVICES
11IIIIIIII
Monolithic 8-Bit
Video AID Converter
AD9048 I
FEATURES
35MSPS Encode Rate
16pF Input Capacitance
550mW Power Dissipation
Industry-Standard Pinouts
AD9048 FUNCTIONAL BLOCK DIAGRAM
II
APPLICATIONS
Professional Video Systems
Special Effects Generators
Electro-Optics
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
GENERAL DESCRIPTION
The AD9048 is an 8-bit, 35MSPS flash converter, made on a
high speed bipolar process, which is an alternate source for the
TDCI048 unit but offers enhancements over its predecessor.
Lower power dissipation makes the AD9048 attractive for a
variety of system designs.
Because of its wide bandwidth, it is an ideal choice for real-time
conversion of video signals. Input bandwidth is flat with no
missing codes.
Clocked latching comparators, encoding logic and output buffer
registers operating at minimum rates of 35MSPS preclude a
need for a sample-and-hold (SIH) or track-and-hold (T/H) in
most system designs using the AD9048. All digital control inputs
and outputs are TTL compatible.
Devices operating over two ambient temperature ranges and
with two grades of linearity are available. Linearities of either
O.5LSB or O.75LSB can be ordered for a commercial range of 0
to + 70°C, or extended case temperatures of - 55°C to + 125°C.
Commercial versions are packaged in 28-pin DIPs and plastic
leaded chip carriers (PLCCs); extended temperature versions are
available in ceramic DIP and ceramic LCC packages. Both commercial units and MIL-STD-883 units are standard products.
ANALOG-TO-DIGITAL CONVERTERS 3-509
SPECIFICATIONS
(typical with oominal suppfies untess otherwise noted)
ABSOLUTE MAXIMUM RATINGS l
Output Short-Circuit Duration . . . . . .
Operating Temperature Range (Ambient)
AD9048JN/KN/JP/KP/JQ/KQ . . . . .
AD9048SE/SQITElTQ/883B . . . . . .
Maximum Junction Temperature (Plastic)
Maximum Junction Temperature (Hermetic)
Lead Temperature (Soldering, 10sec)
Storage Temperature Range . . . . . . . . .
Vee to DGND
-O.SV de to +7.0V de
AGND to DGND . . . . .
-O.SV de to +O.SV de
VEE to AGND. . . . . . .
+O.SV de to -7.0V de
VIN , VRT or VRB to AGND
. . . . . +O.5V to VEE
VRT to VRB • • . • • • • •
-2.2V de to +2.2V de
CONY, NMINVor NLINV to DGND. -O.5V de to +S.SVdc
Applied Output Voltage to DGND. -O.SV de to + S.5V dc2
Applied Output Current, Externally Forced
. . . . . . . . . . . . . . -l.OrnA to +6.0mA 3 ,4
. . . l.Osec 5
o to +70°C
- SsoC to + 12SoC
+ lS0°C6
. . . . . + 17soC6
. . . . , +300°C
-6SoC to + lS0°C
ELECTRICAL CHARACTERISTICS (Vee= +5.OV; vEE = -5.2V; Differential Reference VoHage=2.OV, unless otherwise noted)
Test
Parameter (Conditions)
Temp
Level
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
+25"C
Full
+25"C
Fun
Full
I
VI
I
VI
VI
+25"C
Full
+25"C
Fun
Fun
I
VI
I
VI
V
Fun
V
AD9048JN/JP/JQ
Typ
Mas
AD9048KNIKPIKQ
Typ
Mas
Min
Min
8
8
0.4
0.75
1.0
0.6
0.75
1.0
GUARANTEED
0.3
0.5
0.65
0.4
0.5
0.65
GUARANTEED
SubGroup7
Min
AD9048SElSQI883B
Typ
Max
AD9048TErrQ/883B
Typ
Max
Min
Uaits
8
8
Bits
7
8
7
8
7,8
0.3
0.5
0.5
0.5
0.4
0.5
GUARANTEED
0.75
1.0
0.6
0.75
1.0
GUARANTEED
0.4
LSD
LSD
LSD
LSD
INITIAL OFFSET ERROR
TopofRd~e~
Bottom of Reference Ladder
Offset Drift Coefficient
ANALOG INPUT
Input Voltage Range
5
12
12
10
10
4
5
4
20
-2.1;
+0.1
Input Bias CurrentB,9.IO
+ 25°C
Fun
+ 25°C
Fun
+25"C
+25"C
I
VI
I
VI
III
III
Reference Input Bandwidth
Full
Fun
Full
Full
Full
Fun
+ 25°C
V
V
V
VI
V
VI
V
DYNAMICPERFORMANCE"
Conversion Rate 13 • 15
Aperture Delay
Aperture Uncertainty (Jitter)
Output Delay(tpo)""
Output Hold Time (toH)"
Transient Response l7
Overvoltage Recovery Time l8
Rise Time
F.IITime
OutputTimeSkew l9
+ 25°C
+25"C
+25"C
+25"C
+25"C
+25"C
+25"C
+ 25°C
+25"C
+25"C
I
III
III
I
I
I
V
I
I
I
NMINV andNLINV INPUTS""
+O.4VlnputCurreot
+2.4VlnputCurrent
+ 5.5VlnputCurrent
Full
Full
Full
VI
VI
VI
CONVERT INPUT
Logic "1"Voltage
Logic "0" Voltage
Logic"I"Current(V,= +2.4V)·'"
Logic "I" Current (V, = + 5.5V)·'"
Logic "0" Current9 • 13
Input Capacitance
Convert Pulse Width (LOW)
Convert Pulse Width (HIGH)
Full
Full
Full
Full
Full
+25"C
+25"C
+25"C
VI
VI
VI
VI
VI
III
I
I
Input Resistance
Input Capacitance
Full Power Bandwidth II
36
200
40
10
60
100
200
40
300
16
15
20
10
12
12
10
10
7
8
7
8
5
4
5
12
12
10
10
4
20
20
20
-2.1;
+0.1
36
60
100
300
-2.1;
+0.1
-2.1;
+0.1
16
15
20
I
2,3
I
2,3
12
12
36
200
40
10
200
40
300
16
15
36
60
100
20
10
12
12
10
10
",vrc
60
100
V
",A
",A
kll
kll
300
16
15
mV
mV
mV
mV
20
pF
MHz
REFERENCE INPUT
Positive Reference Voltagel2
Negative Reference Voltage 12
Differential Reference Voltage
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Ladder Curren[13
50
35
0.0
-2.0
2.0
90
0.22
23
10
38
2.4
25
13
5
8
6
8
4.5
125
50
40
35
5
50
15
5
20
9
14
7
0.0
-2.0
2.0
90
0.22
23
10
38
2.4
25
9
8
6
8
4.5
200
10
10
0.8
15
15
400
4
3-510 ANALOG"TO-DIGITAL CONVERTERS
1,2,3
1,2,3
4
20
12
12
9
9
4
9
14
7
9
9
9
200
10
10
1,2,3
1,2,3
1,2,3
5
50
12
2.0
2.0
18
10
125
40
4
6
18
10
0.8
15
15
400
6
7,8
7,8
1,2,3
1,2,3
1,2,3
12
4
4
50
35
5
0.0
-2.0
2.0
90
0.22
23
10
38
2.4
25
9
8
6
8
4.5
125
50
40
35
5
50
12
5
20
9
14
7
0.0
-2.0
2.0
90
0.22
23
10
38
2.4
25
9
8
6
8
4.5
125
!l
40
mA
MHz
20
9
14
7
2.0
2.0
0.8
15
15
0.8
15
15
4
400
400
6
4
18
10
nrc
MHz
5
50
12
200
10
10
200
10
10
18
10
V
V
V
6
ns
ps
ns
ns
ns
os
ns
os
os
i>A
i>A
",A
V
V
",A
i>A
i>A
pF
ns
ns
AD9048
Test
AD9048JN/JP/JQ
Min
Typ
Max
AD9048KN/KPIKQ
Min
Typ
Max
Sub.
Group7
AD9048SE/SQ/883B
Min
:yp
Max
I
V
47
50
48
49
55
48
4
47
50
48
49
55
48
dBc
dBc
+ 25"C
+ 25"C
+ 25"C
+25"C
I
I
I
I
43.5
43
52.5
52
44
44
53
53
45
44
54
53
46
46
55
55
4
4
4
4
43.5
43
52.5
52
44
44
53
53
45
44
54
53
46
46
55
55
dB
dB
dB
dB
+25"C
+25"C
+ 25"C
+ 25"C
+ 25"C
I
V
III
III
III
43.5
44
40.5
39
45
46
40.5
39
4
43.5
36.5
44
40.5
39
45
46
40.5
39
1
2
12
12
12
1
2
dB
dB
dB
Degree
%
DIGITAL OUTPUTS
Logic "1" Voltage I 5
Logic "0" Voitage lO ,15
Shon Circuit CurrentS
Full
Full
Full
VI
VI
VI
2.4
1,2,3
1,2,3
1,2,3
2.4
0.5
30
0.5
30
V
V
rnA
POWER SUPPLY
Positive Supply Current ( + S.SV)
(VEE ~ - 5.5V)
Negative SuppiyCurrent (- S.5V)
+ 25"C
Full
+ 25"C
I
VI
I
40
40
110
1
2,3
1
40
40
110
rnA
rnA
rnA
Full
+ 25"C
+25"C
VI
V
V
120
2,3
120
rnA
rnW
rnW
Parameter (Conditions)
AC LINEARITY
In-Band Harmonics
de to 2.438MHz2O
dCI09.35MHz 21
Signal-ta-Noise Ratio (SNR)10
1.248MHz Input Frequency22
2.438MHz Input Frequency22
1.248MHz Input FrequencyB
2.438MHz Input FrequencyB
Signal-to-Noise Ratio (SNRi i
1.248MHz Input Frequency22
9.35MHzlnput Frequency22
Noise Power Ratio (NPRi 4
Differential Phase25
Differential Gain25
Nominal Power Dissipation
Reference Ladder Dissipation
Temp
Level
+25"C
+ 25"C
36.5
36.5
1
2
2.4
0.5
30
34
90
40
40
110
34
90
120
550
45
550
45
AD9048TErTQ/883B
Typ
Max
Min
36.5
1
2
2.4
0.5
30
34
90
34
40
40
110
90
120
550
45
550
45
Units
'Maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the deVice may be impaired. Functional operation under any 01 these
conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
2Applied voltage must be current-limited to specified range.
3Forcing voltage must be limited to specified range.
'Current is specified as negative when flowing into the device.
SOutput High; one pin to ground; one second duration.
6Typical thermal impedances (no air flow) are as follows:
Ceramic DIP: alA ""-49"CfW; ale = 15"CfW
LCC: aJA "" 69"CIW; HJe = 2l"CIW
PLCC: tl JA oc_ 59; ale = 19
Plastic DIP: aJA = 58"CIW; alC ""-16"CfW
To calculate juntion temperature (T J), use power dissipation (PD) and thermal impedance:
T J = PD(I:I]A)+ T AMBlliNT = PO (tlJc:) = + T CASh
7Military subgroups apply only to military-grade devices.
~Measured with V 1N = OV and CONVERT low (sampling mode).
9VCC =- +5.SV
IOV EE = -S.SV
11 Determined by beat frequency testing for no missing codes.
12VRT ? V RB under all circumstances.
BV EIi = -4.9V
140utputs terminated with 40pF and 8101 ~ pull-up resistors.
ISVCC= +4.5V
16Interval from 50% point ofleading edge CONVERT pulse to change in output data.
EXPLANATION OF SUBGROUPS
17Por full scale step input, 8-bit accuracy attained in specified time.
18Recovers to 8-bit accuracy in specified time after - 3V input overvohage.
Subgroup 1 - Static tests at 25°C.
190utput time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences.
lOMeasured at 20MHzencode rate with analog input IdB below full scale.
(5% PDA calculated against Subgroup
21 Measured at 35MHz encode rate with analog input IdB below full scale.
for MIL-STD-883B versions.)
22RMS signal to rms noise.
Subgroup 2 - Static tests at maximum rated
lJpeak signal to rms nOise.
HOC to 8MHz noise bandwidth with I.248MHz slot; four sigma loading; 20MHz encode.
operating temperature.
2~Clock frequency = 4 x NTSC = 14.32MHz. Measured with 4O-IRE modulated ramp.
+
Specificationssubiect to change without notice.
EXPLANATION OF TEST LEVELS
Test Levell
Test Level II
100% production tested.
100% production tested at + 25°C and
sample tested at specified temperatures.
Test Level III
Sample tested only.
Test Level IV
Parameter is guaranteed by design and
characterization testing.
Test Level V
Parameter is a typical value only.
Test Level VI - All devices are 100% production tested at
25°C. 100% production tested at temperature
extremes for military temperature devices;
sample tested at temperature extremes for
commercial/industrial devices.
I
Subgroup 3 -Static tests at minimum rated
operating temperature.
Subgroup 4 - Dynamic tests at + 25°C.
Subgroup 5 - Dynamic tests at maximum rated
operating temperature.
Subgroup 6 - Dynamic tests at minimum rated
operating temperature.
Subgroup 7 - Functional tests at + 25°C.
Subgroup 8 - Functional tests at maximum and
minimum rated operating temperature.
Subgroup 9 - Switching tests at + 25°C.
Subgroup 10 - Switching tests at maximum rated
operating temperature.
Subgroup 11 - Switching tests at minimum rated
operating temperature.
Subgroup 12 - Periodically sample tested.
ANALOG-TO-OIGITAL CONVERTERS 3-511
I
MECHANICAL INFORMATION
AGNO
NMINV--. . .
01 (MSB)-
Vee
Die Dimensions
Pad Dimensions
Metalization , ,
Backing, , , ,
Substrate Potential
Passivation
Die Attach
Bond Wire
3-512 ANALOG-TO-OIGITAL CONVERTERS
127 x 140x4 (±2) mils
4x4 mils
, Gold
None
-,
VEE
, Nitride
Gold Eutectic
1 mil Gold; Gold Ball Bonding
A09048
I
PIN CONFIGURATION
DIP
PLCC
LCC
iii
NMINV
! i> ,
Q z
I! a
s
'"
•,
RM
2
R.
AGND
rl!
28 27 2.
tJ
DGND 5
NC
1
25 AGND
24 Ne
Vee 6
Vw
23 V IN
VEE 7
NC
AD9048
VEE 8
NC
V,,- 9
21 Ne
20 NC
19 AGND
DGND"
AGND
"-
RT
12 13
NLiNV
>
CONVERT
i
D8ILSB)
DS
•
(Not to Scale)
Vcc 10
Vo<
AD9048
TOP VIEW
22 NC
TOP VIEW
(Not to Scale)
,.
IS 16 17
l!! l! 8
DO
~
z
!! 8
~
18
IE
>!!S_!i~r!
:J W
Z~
NC=NOCONNECT
!
....R
~
NC= NO CONNECT
NC=NOCONNECT
Pin
Nanie
FUNCTIONAL DESCRIPTION
Pin
Name
Description
Description
Dl - D8
Eight digital outputs. Dl (MSB) is the most
significant bit of the digital output word;
D8 (LSB) is the least significant bit.
Most negative reference voltage for internal
reference ladder.
AGND
One of two analog ground returns. Both grounds
should be connected together and to low impedance
ground plane near the AD9048.
Most positive reference voltage for internal
reference ladder.
DGND
One of two digital ground returns. Both grounds
should be connected together and to low impedance
ground plane near the AD9048.
Va:.
Positive supply terminals; nominally +5.0V.
VEE
Negative supply terminals; nominally -5.2V.
CONVERT
Input for conversion signal; sample of analog
input signal taken on rising edge of this pulse.
-S.2V
IMSBID1
tDOn
D,
D3
AD,
VIN
Analog input signal pin.
NMINV
"Not Most Significant Bit Invert." In normal
operation, this pin floats high; logic LOW at
NMINV inverts most significant bit of digital
output word [Dl (MSB)].
NLINV
"Not ~east Significant Bit Invert." In normal
operation, this pin floats high; logic LOW at
NLINV inverts the seven least significant bits of
the digital output word.
+5.0V
r-...J..._--J~-:..-...,___+-I0"~~
AD!
Midpoint tap on internal reference ladder.
-2.GV
Ik
LDAD
' - - , -_ _. . - - ' RESISTORS
OPTION #1 (STATIC): AD1:: -Z.OV; AD2:: +2.4V
OPTION #2 (DYNAMIC): SEE WAVEFORMS
MIL-STD-883 Compliance Information
The AD9048SE/TE/SQITQ/883B devices are classified within
Microcircuits Group 57, Technology Group D (bipolar AID
converters) and are constructed in accordance with MIL-STD-883.
The AD9048 is electrostatic sensitive and falls within electrostatic
sensitivity classification Class 1. Percent Defective Allowance
(PDA) is computed based on Subgroup 1 of the specified Group
A test list. Quality Assurance (QA) screening is in accordance
with Alternate Method A of Method 5005.
The following apply: Burn-In per lOIS; Life Test per 1005;
Electrical Testing per 5004. (Note: Group A electrical testing
assumes T A = Tc=TJ .) MIL-STD-883-compliant devices are
marked with "C" to indicate compliance.
AD1~=~~.OV
10-----.'--1
AD2
.f11U1.IlJlIlJ1 -
~5...sl--
-
v,"
V1L
AD9048 Burn-In Diagram
ANALOG-TO-DIGITAL CONVERTERS 3-513
System timing which provides details on delays through the
AD9048, as well as the relationships of various timing events, is
shown in Figure 2, AD9048 Timing Diagram.
THEORY OF OPERATION
Refer to the block diagram of the AD9048. The AD9048 comprises
three functional sections: a comparator array, encoding logic,
and output hitches.
Dynamic performance of the AD9048, i.e., typical signal-to-noise
ratio, is illustrated in Figures 3 and 4.
Within the array, the analog input signal to be digitized is compared
with 2SS reference voltages. The outputs of all comparators
whose references are below the input signal level will be high;
and outputs whose references are above that level will be low.
+5.DV
The n-of-2S5 code which results from this comparison is applied
to the encoding logic where it is converted into binary coding.
When it is inverted with dc signals applied to the NLINV and/or
NMINV pins, it becomes twos complement.
'-----+--o·J'u~
After encoding, the signal is applied to the output latch circuits
where it is held constant between updates controlled by the
application of CONVERT pulses.
The AD9048 uses strobed latching comparators in which comparator outputs are either high or low, as dictated by the analog
input level. Data appearing at the output pins have a pipeline
delay of one encode cycle.
~~
I
I
Input signal levels between the references applied to RT (Pin 18)
and RB (Pin 26) will appear at the output as binary numbers
between 0 and 2SS, inclusive. Signals outside that range will
show up as either full-scale positive or full-scale negative outputs.
No damage will occur to the AD9048 as long as the input is
within the voltage range of VEE to +O.SV.
RI2
-5.2Y
ANALOG
INPUT
The significantly reduced input capacitance of the AD9048
lowers the drive requirements of the input buffer/amplifier and
also induces much smaller phase shift in the analog input signal.
I
I
Applications which depend on controlled phase shift at the
converter input can benefit from using the AD9048 because of
its inherently lower phase shift.
-s.zv
-S.2V
COMPARATOR
CELLS
The CONVERT, analog input and digital output circuits are
shown in Figu~e I, AD9048 Input/Output Circuits.
Figure 1. InputiOutputCircuits
N+'
ANALOG
INPUT
CONVERT
O~mT
~~
:::=c:xx
N-'
--l
I- tpo
XX
'v'
DATA
CHANGING
N
XX';;:"--N-+-'-
'v'
DATA
CHANGING
Figure 2. AD9048 Timing Diagram
3-514 ANALOG-TO-DIGITAL CONVERTERS
RI2
~R'
...
AD9048
Ceramic O.IIJ.F decoupling capacitors should be placed as close
as possible to the supply pins of the AD9048. For decoupling
low frequency signals, use IOIJ.F tantalum capacitors, also connected as close as practical to voltage supply pins.
0
.
,
Within the AD9048, reference currents may vary because of
coupling between the clock and input signals. Because of this, it
is important that the ends of the reference ladder, RT (Pin 18)
and RB (Pin 28), be connected to low impedances (as measured
from ground).
1\
[\
38
100kHz
1MHz
10MHz
ANALOG INPUT FREQUENCY _ 1dB BELOW FULL SCALE
If the AD9048 is being used in a circuit in which the reference
is not varied, a bypass capacitor to ground is strongly recommended. In applications which use varying references, they
must be driven from a low impedance source.
Figure 3. AD9048 Dynamic Performance (20MHz Encode
Rate)
.
.
.
.
!.
.
-15V
1k
Uk
~
0
~
"- \.
!!l0
R
O.1fA.F
..--~Nv---,
r\
D1(MSBI
z
52
In
AD9048
38
100kHz
1MHz
'OMHz
ANALOG INPUT FREQUENCY -1dBBELOW FULL SCALE
TTL
CONVERT (O-r---------I CONVERT
D8(LSBI
SIGNAL
Figure 4. AD9048 Dynamic Performance (35MHz Encode
Rate)
LAYOUT SUGGESTIONS
Designs which use the AD9048 or any other high-speed device
must follow some basic layout rules to insure optimum
performance.
+5.0V
Figure 5. AD9048 Typical Connections
The first requirement is to have a large, low impedance ground
plane under and around the converter. If the system uses separate
analog and digital grounds, both should be connected solidly
together and to the ground plane as close to the AD9048 as
practical, to avoid ground loop currents.
ANALOG-TO-DIGITAL CONVERTERS 3-515
II
Binary
Step
000
001
True
Range
-2.000VFS
7.8431mV Step
-2.0480VFS
8.000mV Step
NMINV = I
NLINV = I
O.OOOOV
-0.0078V
O.OOOOV
-0.0080V
00000000
00000001
·127·
··
·
-0.9%IV
·
·
- !.OI60V
128
129
- !.OQ39V
- !.0118V
- !.0240V
- !.0320V
·
···
254
255
···
- !.9921V
-2.0000V
·
··
-2.0320V
-2.0400V
·
·
01111111
Inverted
True
0
0
0
I
I
0
11111111
11111110
10000000
10000001
01111111
01111110
·
·
10000000
·
·
11111111
··
00000000
01111111
01111110
00000000
00000001
11111111
11111110
00000000
01111111
10000000
·
10000000
10000001
··
··
·
00000001
·
11111110
11111111
Offset Twos
Complement
Inverted
·
··
·
01111110
AD9048 Truth Table
ORDERING INFORMATION
Model
Linearity
Temperature
Description
Package
Options·
AD9048JN
AD9048KN
AD9048JP
AD9048KP
AD9048JQ
AD9048KQ
AD9048SE/883B
AD9048TE/883B
AD9048SQ/883B
AD9048TQ/883B
0.75LSB
0.5LSB
0.75LSB
0.5LSB
0.75LSB
0.5LSB
0.75LSB
0.5LSB
0.75LSB
O.5LSB
Oto +70°C
Oto + 70°C
Oto + 70°C
Oto +70OC
Oto + 70°C
Oto + 70°C
- 55°C to +
- 55°C to +
- 55°C to +
- 55°C to +
28-Pin Plastic DIP
28-Pin Plastic DIP
28-PinPLCC
28-PinPLCC
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-PinLCC
28-PinLCC
28-Pin Ceramic DIP
28-Pin Ceramic DIP
N-28
N-28
P-28A
P-28A
Q-28
Q-28
E-28A
E-28A
Q-28
Q-28
·See Section 14 for package outline information.
3-516 ANALOG-TO-DIGITAL CONVERTERS
125°C
125°C
125°C
125°C
·
··
·
10000001
Hybrid RS-170
Video Digitizer
1IIIIIIII ANALOG
WDEVICES
AD9502
FEATURES
8-Bit Gray Scale Resolution
Screen Resolution to 512 x 512
Phase-Locked Pixel Clock
TTL Compatible
I
AD9502 FUNCTIONAL BLOCK DIAGRAM
COMPARATOR
ENABLE
I
APPLICATIONS
Machine Vision Systems
Automatic Inspection
Image Processing
OFFSET
ADJ
GENERAL DESCRIPTION
The Analog Devices' AD9S02 is a video digitizer which converts
RS-170, NTSC, or PAL camera signals directly into 8-bit digital
information and control signals.
All of the analog preprocessing functions needed to move from
the analog world of cameras to the digital world of signal processing
are contained in this single hybrid component.
Included are a video amplifier with dc restomtion, sync detector
and separator, phase-locked pixel clock oscillator, and an 8-bit
analog-to-digital converter. The AD9S02 is also extremely adapatable by virtue of providing for ± 3dB gain control and offset
variations of 0 to 10 IRE units. These latter chamcteristics
increase the flexibility of the device by making it useable over a
wide mnge of input signal amplitudes and set up level outputs
from various types of cameras.
A pixel clock synchronized to the sync portion of the composite
signal is generated by the phase-locked oscillator and the sync
detector/separator circuit. Depending on model number, the
nominal frequency of this clock is 7.31MHz, 9.83MHz, or
12.8SMHz. These frequencies correspond to S12 pixels per line
or 384 pixels per line, and aspect ratios of 4:3 or 1: 1.
In addition to the pixel clock, AD9S02 control signals also include
horizontal and vertical sync pulses. This combination of outputs
allows the user to II1anage frame memory efficiently; output data
can be precisely located for optimum support of complex digital
signal processing algorithms.
Six models of the AD9S02 are available; all units opemte over
case tempemture mnges of - 2SoC to + 8SC. Models AD9502AM,
AD9S02BM, and AD9S02CM with pixel clock frequencies of
7.31MHz, 9.83MHz, and 12.8SMHz, respectively, are tested at
+ 2SoC. Models AD9S02AMB, AD9S02BMB, and AD9S02CMB,
with the same clock frequencies, are tested at temperatures from
- 2SoC to + 8SoC. During their manufacturing, these latter
units also receive additional high-reliability processing.
ANALOG-TO-DIGITAL CONVERTERS 3-517
SPEC IFICATIONS (Qpical
Panmeter,z
@
+25"C with nominal su,,1es, unless otherwise noted)
Sub
Group
Temp
- 25"<: to + 85"<:
AD9502AMIBMICM1
Min
Typ
Mu
RESOLUTION
(GS = Gray Scale)
(FS = Full Scale)
II LSB WEIGHT3
ACCURACY
I Integral Linearity
I
Differential Linearity4
I
Ipitial OffsetS
IIOffsetvs. Temperature
lGain6
# Gain vs. Temperature7
DYNAMIC CHARACTERISTICS
Output Data Rate (Pixel Qock)8
I AD9502AMIAMB
I AD9502BMlBMB
I AD9502CMlCMB
# Sampling Jitter
II Digital Output Delay
I Horizontal Sync Delay
I Horizontal Sync Delay
IHorizontal Sync Width
IHorizontal Sync Width
IVertical Sync Delay
IVertical Sync Delay
ISample Delay
ISample D~y
VIDEOINPUT
Signal Type
I Impedance
I Impedance
Input level for rated performance
II Amplitude
II Amplitude
# Dynamic Range
(back porch ref. to ground)
# Dynamic Range
II Bandwidth (3dB)
II Bandwidth (3dB)
AUXILIARY SYNC INPtrr9
Comparator (Pin 10)
Width
FrequencyS
II Loading
Input Current
I lIN High (VIN = 2.75V)
IIINLow(V1N = 2.3V)
I Logic Level "I"
I Logic Level "0"
I lIN High(VIN = 2.75V)
I liN LoW(V1N = 2.3V)
I Logic Level "1"
I Logic Level "0"
4
5,6
4
5,6
4
4
9,10,11
9,10,11
9,10,11
+25OC
Full
+ 25°C
Full
+25OC
Full
+25OC
Full
1.91
- 25"C to + 85"<:
AD9502AMBIBMBICMBz
Min
Typ
Mu
8
0.4
8
0.4
Bits
%GS
8.4
0.39
8.4
0.39
mV
IRE Units
± 1.0
± 1.5
±2
±2
±50
±250
2.8
±2S0
±2.5
±3.0
±3.0
±3.0
±200
4
9
10,11
9
10,11
9
10,11
9
10,11
Full
Full
Full
+ 25°C
+ 25°C
+ 25°C
Full
+25OC
Full
+25OC
Full
+ 25°C
Full
20
-0.4
-0.4
4.5
4.5
5.5
5.5
7.9
7.9
7.31
9.83
12.85
1
30
0.3
0.3
4.8
4.8
6.0
6.0
9.0
9.0
1
2,3
+ 25°C
Full
67
67
RS-170
75
83
75
83
+ 25°C
Full
0.71
0.71
1.0
1.0
250C
Full
+ 25°C
Full
-0.83
-0.83
5
5
1.91
3-518 ANALOG-TO-OIGITAL CONVERTERS
±2.5
±3.0
±3.0
±3.0
±200
4
67
67
RS-170
75
83
75
83
1.41
1.41
0.71
0.71
1.0
1.0
+ 1.5
+ 1.5
-0.83
-0.83
5
5
6
5
50
0.7
0.7
5.4
5.4
6.7
6.7
9.4
9.4
+2.75
+2.75
n
n
V
V
MHz
MHz
6
jJoS
kHz
TTL Load
50
50
!LA
!LA
+2.3
50
50
+2.75
+2.3
jJoS
jJoS
jJoS
+ 1.5
+1.5
+2.75
+2.3
50
50
jJoS
Vp-p
Vp-p
15.75
<1
50
50
MHz
MHz
MHz
ns,rms
ns
jJoS
jJoS
jJoS
jJos
1.41
1.41
7.5
7.5
1
%FS
%FS
LSB
LSB
mV
jJovrc
VN
ppm."'C
20
-0.4
-0.4
4.5
4.5
5.6
5.6
7.9
7.9
5
50
0.7
0.7
5.4
5.4
6.7
6.7
9.4
9.4
15.75
<1
+25OC
+ 25°C
+25OC
+ 25°C
Full
Full
Full
Full
±1.0
±1.5
±2
±2
±50
±250
2.8
±2S0
7.31
9.83
12.85
1
30
0.3
0.3
4.8
4.8
6.0
6.0
9.0
9.0
7.5
7.5
1
1
1
1
1
2,3
2,3
2,3
2,3
UDita
+2.3
V
V
jJ.A
!LA
V
V
AD9502
Sub
Group
Parameter1,2
AUXILIARY SYNCH INPUT9 (Cont.)
Comparator Enable (Pin 6)
# Loading
Input Current
jIINLow(VIN = O.OV)
jIINHigh(VIN = 5.0V)
j Logic Level" I"
j Logic Level "0"
jIINHigh(VIN = OV)
jIINLow(VIN = 5.0V)
j Logic Level "I"
j Logic Level "0"
DIGITAL OUTPUTS
Coding 1O
Logic Compatibility
j Logic Level "I"
j Logic Level "0"
j Logic Level" I"
j Logic Level "0"
jDrive
jDrive
# Time Skew
# Time Skew
POWER REQUIREMENTS
j +V s (+I2to +I5Vdc)
j -V s (-12to -I5Vdc)
j +Vcc (+5Vdc ±5%)
j Power Dissipation
j + V s ( + 12to + I5Vdc)
j -Vs (-12to -15Vdc)
jVccC +5Vdc ±5%)
j Power Dissipation
Temp
25°C to + 85°C
AD9S02AMIBMlCM 1
Min
Typ
Max
+ VREP).
All other digital outputs return to zero (logic LOW) during overrange conditions.
Overrange data output. Logic HIGH indicates an input voltage overrange (VIN> + VREP). All
other digital outputs return to zero (logic LOW) during overrange conditions.
PIN CONFIGURATIONS
-- .
....
•
I
Vs +4
ANALOG INPUT 5
I
I
18D3(MSBI
DIGITAL GROUND
1
ANALOG GROUND
2
•
OVERRANGE
OVERRANGE
03 (MSB)
17 03 (MSBI
AD9688
16 REFMID
TOP VIEW
(Not to Scalel
ANALOG INPUT
4
1502
AD9688
TOP VIEW
(Not to Scale)
1401
03 (MSB)
REFMID
02
01
9
10 11
...... ......
12 13
GI
c(
GI
c(
...:z: ...:z:
0
Z
Z
u
u
~ ~
Q
iii
Z
::l
~
0:
Cl
0
Q
...
~
!2
Q
3-528 ANALOG-TO-DIGITAL CONVERTERS
LATCH ENABLE
8
DO (LSBI
LATCH ENABLE
9
DIGITAL GROUND
AD9688
DIE LAYOUT AND MECHANICAL INFORMATION
SYSTEM TIMING DIAGRAM
"SAMPLE"
MODE
"LATCHED"
MODE
"SAMPLE"
"LATCHED"
MODE
MODE
D2
D,
Die Dimensions
Pad Dimensions
Metalization
lstLevel
1ndLevei
Backing
Substrate Potential
Passivation
Die Attach
Bond Wire
118.5 x %x 16(±2)mils
4 x 4 mils
Copper-Aluminum Alloy
Aluminum
None
-Vs
Oxynitride
Gold Eutectic
1.15 mil, Aluminum; Ultrasonic Bonding
or 1mil , Gold; Gold Ball Bonding
Minimum Sample Pulse Width
Minimum Setup Time
Minimum Hold Time
Maximum Output Propagation Delay
Minimum Output Hold Time
Offset Voltage
NOTE: Comparator Dutputs are unlatched during "sampling" period. The output may become invalid during this interval as it attempts to track the
input signal.
ANALOG-TO-DIGITAL CONVERTERS 3-529
TYPICAL APPLICATION
+VIIEF
OR
V,.
OR
AD9688 03
02
LE
LE
01
DO
-VREF
+VREF
OR
VIN
R
OR
AD9688 03
02
LE
tE
01
DO
-YREF
+VREF
OR
V,N
OR
AD9688 03
02
LE
01
LE
DO
-VREF
+VRfF
OR
V,.
OR
AD9688
03
02
LE
LE
as
OUTPUTS
01
-VREF
DO
LE
LE
LATCH
INPUTS
GENERAL INFORMATION
The AD9688 is a high speed device. The 200MSPS encode mte
and analog input frequencies which can reach 200MHz, demand
careful layout pmctice typical of high speed circuit design. One
of the most important aspects of any AD9688 design is an effective
low impedance ground plane. Special attention should be paid
to the actual AD9688 ground connections, particularly if sockets
must be used.
The internal reference ladder should be properly biased with
some form of low-impedance driving source. This becomes
especially important if several AD9688s are stacked for higher
resolution. Special transfer functions can be realized when several
AD9688s are stacked and the resistor tap point voltages
are skewed to approximate the desired response curve.
3-530 ANALOG-TO-OIGITAL CONVERTERS
NOTE: ALL ECL OUTPUTS SHOULD BE TERMINATED
TO -2.0V THROUGH loon.
The AD9688 LATCH ENABLE inputs are differential and
must be driven with complementary latch signals. Output stability
in the "sampling" mode can be adversely affected by LATCH
ENABLE signal quality and precision. The effects of a poor
quality waveform can be partially compensated for by adjusting
either the average signal value or overall waveform duty cycle.
Best performance will be achieved through the use of proper
ECL terminations. The open-emitter outputs of the AD9688 are
designed to be terminated through lOOn resistors to -2.0V. If
high speed ECL signals must be routed more than a few centimeters, MicroStrip or StripLine techuiques may be required to
insure proper transition times and prevent output ringing.
1IIIIIIII ANALOG
WDEVICES
FEATURES
Complete 16-Bit Converter With Reference
and Clock
± 0.003% Maximum Nonlinearity
No Missing Codes to 14 Bits
Fast Conversion - 35!U1 (14 Bit)
Short Cycle Capability
Parallel and Serial Logic Outputs
Low Power: 645mW Typical
Industry Standard Pin Out
PRODUCT DESCRIPTION
The AD ADe7l and AD ADC72 are high resolution 16-bit
hybrid IC analog-to-digital converters including reference, clock,
and laser-trimmed thin-film components. The package is a compact
32-pin hermetic ceramic DIP. The thin-film scaling resistors
allow analog input ranges of ±2.SV, ±SV, ±IOV,Oto +SV,O
to + lOY, and 0 to +20V.
Important performance characteristics of the devices are maximum
linearity error of ± 0.003% of FSR (AD ADC7lK, AD ADC72K
and B), and maximum conversion time of SOj.ls. This performance
is due to innovative design and the use of proprietary monolithic
D/A converter chips. Laser-trimmed thin-film resistors provide
the linearity and wide temperature range for no missing codes.
The AD ADC71 and AD ADC72 provide data in parallel form
with corresponding clock and status outputs. The AD ADC71
also provides data in serial form. All digital inputs and outputs
are TTL compatible.
Complete, High Resolution
l6-Bit AID Converters
AD ADC7l/AD ADC72 I
AD ADC71/AD ADC72 FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
I. The AD ADC7l and AD ADen provide 16-bit resolution
with maximum linearity error less than ± 0.003% (± 0.006%
for J and A grades) at 25°C.
2. Conversion time is 3Sj.ls typical to 14 bits with short cycle
capability.
3. Two binary codes are available on the AD ADC7l and AD
ADC72 output. They are complementary straight binary
(CSB) for unipolar input voltage ranges and complementary
offset binary (COB) for bipolar input ranges. Complementary
two's complement (CTC) coding may be obtained by inverting
Pin I (MSB).
4. The proprietary chips used in this hybrid design provide
excellent stability over temperature and lower chip count for
improved reliability.
APPLICATIONS
The AD ADC71 and AD ADC72 are excellent for use in applications requiring 14-bit accuracy over extended temperature
ranges. Typical applications include medical and analytic instrumentation, precision measurement for industrial robots,
automatic test equipment (ATE), multichannel data acquisition
systems, servo control systems and anywhere that excellent
stability and wide dynamic range in the smallest space is
required.
ANALOG-TO-DIGITAL CONVERTERS 3-531
SPECIFICATIONS
(typical
atT. = +25"1:. Vs =
Model
AD ADC7lJDIKD
RESOLUTION
16 (max)
ANALOG INPUTS
Voltage Ranges
Bipolar
Unipolar
Impedance (Direct Input)
Oto +5V, ±2.5V
Oto + lOY, ±5.0V
0\0 +20V, ± lOY
±2.S, ::!:S, zIG
010 +5,Oto + 10,0(0 +20
1.88
3.75
7.50
I (max)
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
·
±O.1 2 (::!:O.2max)
*
Inherent Quantization Error
Differential Linearity Error
No Missing Codes (it 25OC"
POWER SUPPLY SENSITIVITY
±15Vde
+5Vde
·
··
···
·
Units
Bits
Volts
Volts
kll
kll
ldl
Positive Pulse SOns Wide (min) Trailing Edi:e Initiates Conversion
Offset Error
Bipolar
Linearity Error(max)
AD ADC72ADIBD
·
··
···
DIGITAL INPUTS'
Convert Command
Logic Loading
Unipolar
:± 15. +5 volts unless oIhelWise nDlBd)
AD ADC72JDIKD
±0.05'(±0.lmax)
±0.1'(±0.2max)
±0.006(J)
± 0.003 (K)
±112
±0.003
To 14Bits(KGrade)
0.003
0.001
·
··
··
··
··
··
·
·
··
··
± 0.006 (A)
± 0.003 (B)
±0.006G)
± 0.003 (K)
*
To 14 Bits (BGrade)
LSTTLLoad
%
%ofFSR'
%ofFSR
%ofFSR
%ofFSR
LSB
%ofFSR
Guaranteed
%ofFSRI%aVs
%ofFSRI%aVs
CONVERSION TIME '(14 BITS)
35 (SO max)
WARM-UPTIME
5 (min)
DRIFT
Gain
±15(max)
± 10(±20max)
+7(±15max)
ppmI'C
±2(±4max)
±IO(max)
±2(3max)
±2(±4max)
±8(±IOmax)
± 1.5 (2 max)
±2(±4max)
±5(±IOmax)
±1.0(2max)
ppm ofFSRI"C
ppm ofFSRI"C
ppm ofFSRI"C
01070
·
·
"C
··
·
·
··
··
··
··
··
··
··
·
··
·
·
··
·
I·"
Minutes
Offset
Unipolar
Bipolar
Linearity
Guaranteed No MissingCode
Temperature Range4
7iJD, 72JD, 72AD (13 Bits)
7lKD, 72KD, 72BD (14 Bits)
DIGITAL OUTPUT'
(AU Codes Complementary)
Parallel and Serial
Output Codes"
Unipolar
Bipolar
Output Drive
Status
Status OUtput Drive
CSB
COB,CTC'
5
Logic "I" During Conversion
5 (max)
Internal Clock
Clock Output Drive
Frequency
INTERNAL REFERENCE VOLTAGE
Error
5 (max)
400
6.3
±5max
Max External Current Drain
With no Degradation of Specs
Temperature Coefficient
±200max
±10max
POWER SUPPLY REQUIREMENTS
Power Consumption
645 (850 max)
Rated Voltage,Analog
Rated Voltage, Digital
Supply Drain + 15V de
Supply Drain -15V de
Supply Drain + 5V de
± 15 ±O.5max
+5 ±O.2Smax
TEMPERATURE RANGE
Speclficstion
Operating (Derated Specs)
Storage
+16
-21
+18
Oto +70
-25to+85
-55to+125
NOTES
I
LoP: "0" := 0.8V,max. Logic"I" = 2.0V.minforinputs. Fordigital outputs Logic "0" = +O.4Vmax.Logic:"I" =
·
··
···
···
·
-25to+85
-25to+125
2.4Vmin.
2Adjustable to zero.
"'ulIScaIeR.....
4f'ordet"mition ol"NoMislingCodes", referto'I'hcoryofOperation.
sConvenion time may be &bortened witb "Sbon Cycle" set for lower resolution.
'CsB-ComplemcfttatyStraigblBinary.COB-ComplementaryOffsctBinary.CfC-Comp1ementaryTwo'sComp1ement.
'CTC "","",obl1ined by ;n_DgMSB(Pin I).
"SpecifacationsllmeasAD ADC71JD, KD.
Specifu:ations subject to change without notice:.
~532
ANALOG-TO-DIGITAL CONVERTERS
LSTTLLoads
LSTTLLoads
LSTTLLoads
kHz
Vde
%
"A
ppmr<:
rnW
Vde
Vde
rnA
rnA
rnA
'C
"C
"C
AD ADC7l/AD ADC72
e
~ +O.OO8I------+->,-='~Io::::'>.~"""""""_¥=>r__>r_>r_>r_'<_l--_I
i
+a-I-----~~-T_>r~~~~~~~~~--_I
~
~
-•.o~---~~~~~~~~~~~~~--;
~
.~---_r~~~~~~~~~~~~--;
-..... t----b;~"'t~~:'?'\"
!=
a:
1/2LSB
:5z
::;
\
\
I-IU
IU-
2
4
6
"
~
'\ ~
8 10 12 14 16 18
CONVERSION TIME - p.s
20
22
24
26
\\
a: 3/4LSB
era:
-a:
.... 0
~>
a: I-
OBIT [ \ 2 BIT
[\ \
1/4LSB
o
lLSB
r
BBIT
\
\
1/2LSB
... a:
...
er
-IU
Cz
::; 1/4LSB
\
\
2
Figure 3. Differential Linearity Error VB.
Conversion Time (Normalized)
10 BIT\ 12 BI~
BBIT'
o
\
4
1\ "
"
6
~
8 10 12 14 16 lB
CONVERSION TIME - p.s
...a:
Ul
20
22
24
26
+0.3
'0 +0.2
?/l.
I
a: +0.1
0
a:
0
a:
Figure 4. Maximum Gain Drift Error - % of
FSR VI. Temperature
IU
I-
-0.1
0
-0.2
:;:
-0.3
-25
...a:
z
0
0
+70
+85
r;::==+===+=:::::J=====I=::;!
~
0.08
a:
O.06tT'~~I-----+---+-----...".I'fi->"""'"
~
+25
TEMPERATURE _·C
a:
IU
Ii:
a:
c
IU
Figure 5. Reference Drift - % Error
vs. Temperature
0
-0.02
~ -0.04
a:
IU -0.06
IU
...
IU
a: -0.08
-55
-25
o
+25
-1:85 +100
TEMPERATURE _·C
ANALOG-TO-DIGITAL CONVERTERS 3-541
The analog continuum is partitioned into 212 discrete ranges
for 12-bit conversion. All analog values within a given quantum are represented by the same digital code, usually assigned
to the nominal midrange value. There is an inherent quantization uncertainty of ±1/2LSB, associated with the resolution,
in addition to the actual conversion errors.
The actual conversion errors that are associated with AID
converters are combinations of analog errors due to the linear
circuitry, matching. and tracking properties of the ladder and
scaling networks, reference error and power supply rejection.
The matching and tracking errors in the AD ADCSO have been
minimized by the use of a monolithic DAC that includes the
scaling network. The initial gain and offset errors are specified
at ±0.1 % FSR for gain and ±O.OS% FSR for offset. These
errors may be trimmed to zero by the use of the external trim
circuits as shown in Figures 7 and 9. Linearity error is defined
as the deviation from a true straight line transfer characteristic
fropt a zero analog input which calls for a zero digital output
to a point which is defined as full scale. The linearity error is
unadjustable and is the most meaningful indication of AID
converter accuracy. Differential nonlinearity is a mea!IDr!~ of
the deviation in staircase step width between codes from the
ideal least significant bit step size (Figure 6).
Monotonic behavior requires that the differential linearity
error be less than 1LSB, however a monotonic converter can
have missing codes; the AD ADCSO is specified as having no
missing codes over the entire temperature range from -2So C
to +SSoC.
There are three types of drift error over temperature: offset,
gain and linearity. Offset drift causes a shift of the transfer
characteristic left or right over the operating temperature
range. Gain drift causes a rotation of the transfer characteristic
about the zero or minus full scale point. The worst case accuracy drift is the summation of all three drift errors over
temperature. Statistically, however, the drift error behaves
as the root-sum-squared (RSS) and can be shown as:
RSS =VfG 2 + f02 + fL 2
=Gain Drift Error (ppm/oC)
=Offset Drift Error (ppm of FSR/oC)
fL = Linearity Error (ppm of FSRtC)
fG
OFFSET ADJUSTMENT
The zero adjust circuit consists of a potentiometer connected
across ±Vs with its slider connected through a l.SMn resistor
to 'Comparator Input pin 11 for all ranges. As shown in Figure
7 the tolerance of this fixed resistor is not critical, and a carbon composition type is generally adequate. Using a carbon
composition resistor having a -1200ppmf Ctempco contributes
a worst-case offset tempco of SX 244X lO-6 X 1200ppmfC =
2.3ppmfC of FSR, if the OFFSET AD] potentiometer is set
at either end of its adjustment range. Since the maximum offset adjustment required is typically no more than ±4LSB, use
of a carbon composition offset summing resistor typically contributes no more than IppmfC of FSR offset tempco.
+15V
1.8MSl
11
10kSl
TO ~-"""""",-o--I AD ADC80
100kSl
-15V
Figure 7. Offset Adjustment Circuit
An alternate offset adjust circuit, which contributes negligible offset tempco if metal film resistors (tempco <100
ppmf C) are used, is shown in Figure S.
+15V
OFFSET
ADJ
80'llk"lM\-0--......,.,.,..-0--1
AD ADC80
Figure 9. Gain Adjustment Circuit
011 ... 111 +---lil----·i-~
:::l
An alternate gain adjust circuit which contributes negligible
gain tempco if metal film resistors (Tempco <1 OOppmf C) are
used is shown in Figure lO.
o
..J
~
a
2i
+15V
I,:!,OSl
~-1lSB
SoI__...2"'7Ok,.,.._....--'2"'70"'k...-_106-1
6.8kSl
-15V
Figure 6. Transfer Characteristic for an Ideal Bipolar A/D
3-542 ANALOG- TO-DIGITAL CONVERTERS
O,01~Ff
100kSl
AD ADC80
V
~7
Figure 10. Low Tempco Gain Adjustment Circuit
Applying the AD ADC80
THEORY OF OPERATION
On receipt of a CONVERT START command, the AD ADC80
converts the voltage at its analog input into an equivalent 12bit binary number. This conversion is accomplished as follows:
the 12-bit successive-approximation register (SAR) has its
12-bit outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC.
The analog input is successively compared to the feedback
DAC output, one bit at a time (MSB first, LSB last). The
decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state
of the comparator at that time.
BI is reset and B2-.-BI2 are set unconditionally. At tl the Bit 1
decision is made (keep) and Bit 2 is unconditionally reset. At
t2, the Bit 2 decision is made (keep) and Bit 3 is reset unconditionally. This sequence continues until the Bit 12 (LSB) decision (keep) is made at t12' After a 40ns delay period, the
STATUS flag is reset, indicating that the conversion is complete and that the parallel output data is valid. Resetting the
STATUS flag restores the gated clock inhibit signal, forcing the
clock output to the Logic "0" state.
Corresponding serial and parallel data bits become valid on
the same positive-going clock edge. Serial data does not change
and is guaranteed valid on negative-going clock edges, however;
serial data can be transferred quite simply by clocking it into a
receiving shift register on these edges (see Figure 11).
TIMING
The timing diagram is shown in Figure 11. Receipt of a CONVERT START signal sets the STATUS flag, indicating conversion in progress. This, in turn, removes the inhibit applied to
the gated clock, permitting it to run through 13 cycles. All
SARparallel bit and STATUS flip-flops are initialized on the
leading edge, and the gated clock inhibit signal is removed on
the trailing edge of the CONVERT START signal. At time to,
1 - 0.
1.
-
-
-
-
-
-
Incorporation of this 40ns delay guarantees that the parallel
(and serial) data are valid at the Logic "I" to "0" transition
of the STATUS flag, permitting parallel data transfer to be
initiated by the trailing edge of the STATUS signal.
MAXIMUM THROUGHPUT TIME
--------1~
t - - - - - - - - CONVERSION TIME (2) - - - - - - - '
INTERNAL
CLOCK
STATUS
*
ITa
IT6
I
I
I
MSB
---1
BIT 2
---JLj"1"
BIT3
BIT4
BIT5
BIT6
BIT7
BITS
BIT9
BIT 10
BIT 11
LSB
SERIAL
DATA
OUT
i
IT'~4)1
I
ii,
I
T'2
i
:::J
Lj"1" I I I I
I r---J
,"0"
---~--~-==t::;;-t-t-t-r--r--t--r-T~
:::j
1"0"1 I ,
I
r:::j
U"1" i i i
:::J"-- - - - - - - , L J ..
:::J
::]
:::J
:::J
:::J
1.. '
,
I
U"1'"
,"0"
LJ'1"
i
LJi-..--1..-+----
:::~
1:°"
"0"
2
"1"
:
3
"1"
I
4 :
"0"
5
"0"
I
6
"1"
I
7
"1"
: S
"1"
r-
U!...J.....".10~::;:;11~~LjL1SSjB~WlJ'a
"0"
"1"
"1"
"0:
I
NOTES:
1. THE CONVERT START PULSE WIDTH IS 100n5 MIN AND MUST REMAIN LOW DURING
A CONVERSION. THE CONVERSION IS INITIATED BY THE "RISING EDGE" OF THE
CONVERT COMMAND.
2.251'5 FOR 12 BITS AND 211'5 FOR 10 BITS (MAX).
3. MSB DECISION
4. LSB DECISION 40n5 PRIOR TO THE STATUS GOING LOW
*BIT DECISIONS
Figure ". Timing Diagram (Binary Code 011001110110)
ANALOG-TO-DIGITAL CONVERTERS 3-543
•
DIGITAL OUTPUT DATA
Both parallel and serial data from TTL stol'l\ge registers are in
negative true form. Parallel data output coding is complementary binary for unipolar ranges and either complementary offset binary or complementary two's complement binary, depending on whether BIT 1 (pin 6) or its logical inverse BIT 1
(pin 8) is used as the MSB. Parallel data becomes valid approximately 40ns before the STATUS flag returns to Logic "0",
permitting parallel data transfer to be clocked on the "1" to
"0" transition of the STATUS flag.
Connect Short
Cycle Pin 21 to
Pin:
Bits
Resolution
(%FSR)
12
10
8
0.024
0.100
0.390
9
28
30
Maximum Status Flag
Reset
Conversion
Time (ps)
25
21
17
tl2 +40ns
tlO +40ns
ts +40ns
Table I. Short Cycle Connections
INPUT SCALING
The AD ADC80 input should be scaled as close to the maximum input signal range aspossible in order to utilize the
maximum signal resolution of the AID converter. Connect the
input signal as shown in Table II. See Figure 12 for circuit
details.
Serial data coding is complementary binary for unipolar input
ranges and complementary offset binary for bipolar input
ranges. Serial output is by bit (MSB first, LSB last) in NRZ
(non-return-to-zero) format. Serial and parallel data outputs
change state on positive-going clock edges. Serial data is guaranteed valid 200ns after the rising clock edges, permitting serial
data to be clocked directly into a receiving register on these
edges as shown in Figure 11. There are 13 negative-going clock
edges in the complete 12-bit conversion cycle, as shown in Figure 11. The first edge shifts an invalid bit into the register,
which is shifted out on the 13th negative-going clock edge. All
serial data bits will have been correctly transferred and be in
the receiving shift register locations shown at the completion
of the conversion period.
0----.,
10V RANGE 13
R25kU
20V RANGE 14 O-.........W~..
COMPIN 11 o---a ..... - . Command to tniIino ..... 0...
Ready; use traiIins edp: to strobe output data into extcmaI circuirs
(see text).
7.0 x 5.0 x 0.5
tat
for d.cscriptioa. of Effective Aperture Delay Time.
4RmJ sipal to rms noise ntio wim fuU-acalc S40kHz analot; input
(... F..... 3).
sDc to 8.2MHz white noise bmcIwidm with slot frequency of 3.886MHzj
and CDCOdc nte of 2OMHz.
6f'or fuD-sc:alc step input. 12-bit accuracy attained in specified time.
'Recovers to 12-bit accuracy in specified time after 2 )( FS input
....-vol_.
SWim analog mput 40dB below FS.
~im FS analog input. (LargeooSipaJ bandwidth flat withiD
For Applications Help, Call Computer Labs Division@(919)668-9511.
O.2dB.
dcto IOMHz).
1000m frequencies applied at level 1dB below fuD scaJc.
IIStandard bipolar input is adjustable ± 5% with ou-card potentiometer
(see ~t and FiJurc 2). Unipolar 0 to + 2V input raDJC is availlblc au
~ order; COIIIIII, fottory for cleWIs.
uAdjustab1c ± 15mV without pcrformaocc degradatioD (ICC test and
F..... 2).
l'Digitai "0" to diaiW"." tnnsitioD initiates eDCOdins.
1"Bnc:odc rate spccificd by customerj ICC Ordcriaa' 1nf00000000tion. Units
opcntecl ouuide ± 10% of spcdficd. frequency (up to muimum 2OMHz)
must be returned to factory for recalibraticm. For operation at WOI'd nta
below 500kHz, COIIIIIIt r..tory.
n ± .5V must be equal and opposite witbia lOOmV and track over
_hUe.
Spcdficatious subject to chmae without notice.
3-570 ANALOG-TO-DIGITAL CONVERTERS
. ""
ORID
TOIfOLECENTERLINES---l
BOTTOM VIEW
lSee
V
TEMPERATURE RANGE
Operating
Storage
Cooling Air Requirements
I - - - - '-171'8""
17
Data Bits
Logic Levels, ECL-Compatible
(Balsnced Output)
Drive (Line·to-Line)
Time Skew
Coding
L "
"
""
-..;., 1--G.2'515.4I) TYP
0.811&.21
PIN DESIGNATIONS
On.card Potentiometer
ENCODE COMMAND INPUT"
Logic Levels, ECL-Cumpatible
(Balanced Inp,ut)
Impedance
Ri.. and Fall Tim..
Width
3.5(88.91
Theory of Operation - CAV-1220
THEORY OF OPERATION
Refer to the block diagram of the CAV-1220.
Analog input sigDals to be digitized are applied to a track-and-hold
(TIH) amplifier, which is normally operating as a buffer amplifier
in the ''track'' mode, following all changes in analog input as
they occur. The user of the CAV-1220 determines the point at
which the analog signal is to be digitized by applying an Encode
Command.
The leading edge of the ECL-compatible encode command
causes the track-and-hold to switch momentarily to the "hold"
mode of operation, "freezing" the analog input signal long
enough to begin the digitizing process. The instant this sWitching
action occurs is affected by one of the parameters of the CAV-1220,
called out as Effective Aperture Delay Time in the Specifications
table.
Basically, effective aperture delay time is a measure oCthe difference between the converter's digital and analog delays (t.r-t.)
and can assume a zero, positive, or negative value depending on
the comparative lengths of the two delays. In the CAV-I220,
the analog delay (t.) is less than the digital delay (Id), and causes
effective aperture delay to be typically 2.5ns.
The "held" value of analog signal at the output of the TIH is
applied to a 5-bit encoder. It is also applied to an analog delay
circuit, whose time delay is equal to the interval required for
the first step of the digitizing/reconstruction process.
The digitized signal is applied to a 5-bit DIA converter which
has 12-bit accuracy. Via registers, the same digital signal is
directed to the digital correction logic circuits. The stored data
will represent Bits 1-5 of the 12-bit digital output of the
CAV-I220.
The reconstructed output of the DIA converter becomes one
input to an operational amplifier; its other input is the delayed
analog signal from the delay line. The output of the wideband,
fast-settling op amp ~ts the residue which remains after a
S-bit digital ~tation of the analog input has been subtracted
from that input.
This residue, or error, signal is encoded by a second encoder
and is applied as 8-bit digital information to the digital correction
logic circuits which contain Bits 1-5.
The correction circuits combine the 5-bit and 8-bit bytes of data
to compensate for possible nonlinearities and other errors to
assure the final 12-bit output of the CAV-I220 is 12-bit
accurate.
Expressed in its simplest terms, the digital correction logic
circuits use the information in the 8-bit signal to-determine
what modifications of Bits 1-5 may be necessary. The value of
the MSB in the 8-bit byte establishes whether the S-bit data are
passed "as is" or whether they are increased by a value of binary
"I". The remaining bits (2-8) of the 8-bit byte become Bits 6-12
of the CAV-1220 digital output.
Digitally corrected subranging (DCS), the innovative technique
described here, helps compensate for a wide range of potential
errors which could otherwise be avoided only if the CAV-I220
design included expensive, high precision components.
The use of 13 bits to obtain an accurate 12 bits of output cannot
prevent gain error, tracklhold droop error, linearity error, offset
error, or any of the other inherent characteristics of "real-world"
AID converters. But DCS can, and does, help nullify their
effects and makes it economically feasible to accomplish highspeed, high-resolution digitizing of analog sigDals.
kN:E~~ggo~
c~=g:
R
MIN"" 1Oft15
MAX = 70% ENCODE
PERIOD
~-
R~~~
r
R . . ~~-=.:~FI~_~_
...R
I
ONEENCO~
,-------'55n5 :!:,ons--~·-t·--PERIOD
-=R-...
_______
#122ns:!:3ns
I
_
R...___....JR-
I
t:
N£
ENCODE
PfAIOD-
O~~~T _ _ _ _ _ _ _
X
-n~
--I
_____
5ns
X ____
(ENCODE CMND. #1'
~~
_ _ __
XfENCODE CMND. #21
~
DATA
CHANGING
Figure 1. CAV·1220 Timing Diagram
CAV-1220 TIMING
Refer to Figure 1, the CAV-1220 Timing Diagram.
The intervals shown ~t a continuous update rate of approximately 10MHz, which is considerably below the maximum
capabilities of the CAV-1220. But that frequency helps illustrate
the ''pipeline delay" characteristic of the converter.
At this word rate, spacing between encode commands is approximately 100 nanoseconds; and three encode commands have
occurred before the data associated with the first command are
valid. In Figure 1, this pipeline delay has a total time of approximately 255 nanoseconds (ISSns + lOOns). This interval will be
different at other word rates, but will always include 155ns;
depending upon the update rate, either more or fewer encode
commands may occur before the first data are available.
After the initial delay, valid data will be available at the word
rate dictated by encode commands. Note the spacing between
Encode Command #1 and Encode Command #2 is equal to one
encode period. This is the same spacing as that between Data
Ready #1 and Data Ready #2; and is also the spacing between
the first and second groups of valid data.
System timing can be adjusted as necessary to take into account
the: pipeline delay effects and assure that the data of interest are
strobed out of the converter at the appropriate time.
Figure 1 also illustrates why the trailing edge of the Data Ready
pulse is recommended as the strobe for output data. Typically,
data begin changing Sns after the leading (rising) edge of each
Data Ready pulse; they will be fully settled at the time of the
trailing (falling) edge and available for use in external circuits.
Another possibility for strobing the output data is to use the
DATA READY pulse. Its leading edge occurs at the same time
as the trailing edge of the DATA READY signal, but is a rising
edge, which may facilitate its use as a strobe.
ANALOG-TO-DIGITAL CONVERTERS 3-571
II
ANALOG INPUT IMPEDANCE
Refer again to the block diagram of the CAV-I220 and DOte the
resistor shown in dashed lines and designated asRIN.
3. Apply a precise (±0.2$mV) de level corresponding to the
most negative excursion of the desired input ranae. (For
standard units, this is - I V input.)
This resistor value is chosen by the user to allow the lIII8log
input impedanc:e of the CAV-I220 to be matched to the charac-
4. Adjust GAIN control while observing LSB (Bit 12); adjust
for output of Bits I-II 'solid "0" with LSB "toggling".
teristic impedance of the lIII8log signal source.
Without an added resistor, the input impedance of the unit is
1,0000; this is the series total of the GAIN control and the
900fi resistor shown in the block diagram.
When a resistor is added, it is in parallel with the internal impedance of the CAV-I220; various values of resistors can be
used to obtain standard impedances:
Desired Input
Impedance
SO ohms
75 ohms
93 ohms
100 ohms
I
7. Adjust OFFSET and GAIN controls alternately as necessary
to obtain analog input ranae to tolerance of ± II2LSB.
18
ValueforRIN
S2.3ohma
8O.6ohma
I020hma
1l0ohms
7.
7.
72
70
..
.
sa
For an input impedance (Z) different from those shown aoove,
the correct resistor value can be established with the equation:
I
S. Apply a precise (±0.2SmV) de level corresponding to the
most positive excursion of the desired input ranae. (For
standard units, this is + I V input.)
6. Check digital output to assure Bits 1-11 are solid "I" with
LSB "toggling".
I
RIN=Z-Ik
so
sa
The physica11ocation of RIN is shown in Figure 2.
.
-l-
.-
. ......
r- ....
I I
......
2ND HARMONIC "
I II
3RD HARMONIC
., " II
r,
SNR WiTHOU f HARMONICS
Ti"1'"I=t,..
.I
llLC::::-': ~
i"'..
SNR WITH HARMONICS
~
""
!"-,.
..
.
N'
56
"',,"FOII
MQUNnNG ....
~
52
.''''
.0
PIN"
8
1M
810M
FREQUENCY - Hz
PIN 12
Figure 3. CA V-1220 SNR and Harmonics
Figure 2. CAV-1220 Adjustment Controls
OFFSET AND GAIN ADJUSTMENTS
The design and manufacture of the CAV-I22O AID converter
are innovative and precise, and have resulted in ahigh-performance
converter which is virtually adjustment-free. This elimination of
vsriable controls helps make the unit less susceptible to performance degradstion caused by vibration, shock, or inadvertent
and/or incorrect adjustment.
Despite the complexity of the circuits required to obtain highresolution digitizing at high speeds, there are only two control
settings used in the unit. Factory adjustments during final calibration use selected fixed resistors to assure optimum performance
without a need for "tweaking" by the user.
Only OFFSET and GAIN controls are available, and even these
are sealed at the factory before shipment. In those rare instances
where they may require readjustment, the procedure outlined
below is one which should be used.
Refer to Figure 2, the CAV-I220 Adjustment Controls.
When adjusting offset and gain of the CAV-1220 in the system,
the OFFSET control should be adjusted first. The adjustment
sequence is:
I. Apply to the analog input a precise (±0.2SmV) de level
corresponding to mic:\sca1e of the desired input ranae. (For
standard units with ± IV ranae, this is OV input.)
2. Adjust OFFSET control while observing MSB (Bit I); adjust
for MSB "toggling" between. digital ''0'' and digital "I".
3-572 ANALOG-TO-DIGITAL CONVERTERS
DYNAMIC PERFORMANCE
Figure 3 shows typical performance on some of the dynamic
characteristics which play an important role in the performance
of systems using the CAV-1220 AID converter.
The AID was calibrated in final test for an encode rate of 20MHz.
As shown, signal-to-noise ratio (SNR) with harmonics is typically
66dB at an input frequency of 100kHz; and remains greater
than SOdB for full-scale inputs of SMHz. As expected, SNR
without harmonics is better and is typically S6dB at BMHz.
The level of 2nd and 3rd harmonics at a word rate of 20MHz is
also depicted; in these characteristics, too, the CAV-1220 displays
ezc:eptional performance.
ORDERING INFORMATION
For standard CAV-1220 units, order by model number CAV-1220XXX; XXX is specified by the customer to indicate the desired
optimized word rate. The decimal place is assumed (but not
shown) between the second and third places. CAV-I22().ISO, for
eumple, indicates final calibration and optimum performance at
ISMHz.
Optimum performance will be achieved within a band of frequencies approximately ± 10% around the selected word rate;
but the maximum rate of 20MHz must be considered. If later
applications require word rates beyond the limits of the original
optimum frequency, the unit must be returned to the factory
for calibratiOn; there is a: nominal charge for this service.
Mating sockets for the CAV-1220 converters are model number
MSB-2 (thru hole) or MSB-3 (clolled end). These are individual
solder-type pin sockets for mounting the AID on PC boards.
12-Bit,lMHz
Analog-to-Digital Converter
HAS-1201 I
11IIIIIIII ANALOG
LIllI DEVICES
FEATURES
HAS-1201 FUNCTIONAL BLOCK DIAGRAM
12-Bit Resolution
1MHz Word Rate
T/H and Timing Circuits Included
Single Hybrid Package
11
81T 1IMSB)
iif1IMSBI
APPLlCAnONS
Radar Systems
Medical Instrumentation
Electro-Optics Systems
Test Systems
Digital Oscilloscopes
C~:'~~:D r
3} - - - - - 1
I
I
I
~~~~L
GENERAL DESCRIPTION
The HAS-120l AID Converter combines high resolution and
speed in a single hybrid package. This is a compleu 12-bit,
IMHz unit which includes a track-and-hold and timing circuits.
It's a total solution for the system designer who needs to perform
the entire analog-to-digital conversion function in the smallest
possible space.
This remarkable converter is a full answer to the question of
digitizing analog signals into high-resolution data outputs and
doing it in the most cost-effective way. The HAS-120l is the
ideal choice for the designer who needs state-of-the-an performance
in high-resolution, high-speed AID conversion.
.r-------------~~
Full-scale analog inputs are 5 or 10 volts; and the unit can operate
with either bipolar or unipolar ranges. Analog input impedance
is 1,000 ohms or 2,000 ohms and the three-state digital outputs
are TIL compatible. The user needs to·supply only an encode
command and external power supplies for operation.
All models of the HAS-120l AID Converter are housed in 46-pin
metal hybrid packages. The HAS-1201KM operates over a
temperature range of 0 to + 70"C. The HAS-1201SM is rated
over an operating temperature range of - 2S"C to + 8S"C, but
will operate with derated performance over a range of - SS"C to
+ lOO"C. For units operating from - 2S"C to + 8S"C and military
screening, order HAS-120ISMB; contact the factory for details
about derated performance and military screening.
ANALOG-TO-D/GITAL CONVERTERS 3-573
II
SPEe IFie AT IONS(typical
@
+ 25°C with nominal power supplies unless otherwise noted)
Parameter
UDitll
HAS-1201KM
RESOLUTION (FS = Full Scale)
Bits
%FS
12
0.025
%FS
ppmI"C
%FS ±1I2LSB
ppmf'C
±3
80
0.0125
10
Guaranteed
ACCURACY
Gain
Gain VI. Temperature
Linearity@de
Diff. Nonlinearity VI. Temp.
Monotonicity
HAS-1281SMISMB
HAS-1201 PIN DESIGNATION
PIN FUNCTION
46
45
IS
43
42
DYNAMIC CHARACTERISTICS
41
40
39
In-Band Hannonic1'
(deto 100kHz)
(100kHz to 500kHz)
Conversion Rate
Conversion Time'
Over Temperature
Apenure Uncenainty Gitter)
Aperture Time (Delay)
Signal-to Noise Ratio (SNR)'
Transient Rezponse4
OvervoitageRecovery'
Input Bandwidth
Small Signal, - 3dB6
Large Signal, - 3dB'
Two-Tone Linearity (@inputfrequenciea)
(75kHz; 105kHz)
dB below FS (min)
dB below FS
MHz, max
n5,max
os,max
po,nos
os
dB (min)
n.(max)
DB
80(75)
75
1.05
950
950
30
25
68(65)
600(1000)
1000
44
1.00
1000
MHz
MH.
38
37
36
35
34
33
32
31
30
29
28
dB below FS
80
V,p-pFS
V,max
5.0/10.0
±IS
fi(max)
looo/2ooo(± 1%)
mV(max)
FSppmI"C(max)
±2(±10)
50(200)
27
26
25
ANALOG INPUT
Voltage Rausea
Impedance (SV/IOV Input)
Bipolar Offset'
Initial (SV Input)
VI. Temperature
DIGITAL INPUTS
Logic Levels, TTL-Compstible
24
+5V
-15V
UNIPOLAR POSITIVE
UNIPOLAR NEGATIVE
-;5.2V
GROUND
5V RANGE IN
10VRANGEIN
OFFSET
DO NOT CONNECT·
GROUND
-15V
NO CONNECTION
NO CONNECTION
+15V
+1SV
GROUND
GROUND
GROUNb
GROUND
GROUND
GROUND
GROUND
PIN FUNCTION
I
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
+5V
GROUND
ENCODE COMMAND
GROUND
GROUND
DO NOTCONNECT*
GROUND
REGISTER STROBE
+5V
ENABLE
BlTliMSBI
BITIIMSBI
BIT2
iiif3
iiif4
iiif5
BIT6
iii'f7
BIT8
BIT9
BITIO
BIT 11
iiif12 (LSBI
NOTE:
PINS 2. 4. 5. 7. 24-30. 36 and 41 NEED TO BE CONNECTED
TO THE SAME COMMON GROUND AS CLOSE TO CASE AS
POSSIBLE. POWER SUPPLY VOLTAGES NEEDTO BE
CONNECTED TO ALL DESIGNATED PINS.
·FOR FACTORY USE ONLY,
V
"O"=Oto +0.4
V
LS TTL Loads
"}"= +2.4to+S
Impedance
Rise and Fall Times
ns,max
Frequency
Encode.Command Width'
Min
MHz,max
10
1.05
os
ns
50
Encode Period- 350ns
dataarevalid.
~S signal torms noiseratiowith 100kHz analog input.
4Forfull...acale step input, 12-hit accuracy attained in specified time.
~ers tospecifaedperformance in specified time after 2 x FS input
ns
ns
50
Encode Period- 3SOns
~jth analoginput4OdB below FS.
ns
100
Max
Register Strobe Width
Min
Max
Enable Width
Min
DIGITAL OUTPUTS
Format
Logic Levels, ITL-Compstible'o
Drive
Time Skew
Delay: Register Strobe to
Output Data Validity
Coding
POWERREQUlREMENTS
+15V ±5%
-15V ±S%
+SV ±5%
-S.2V ±5%
Power Consumption
3
NOTES
1.00
overvoltage.
7With FS analog input. (Large-signal bandwidth flat within O.5dB,
de to 500kHz.)
8Extcrnally adjustable to zero.
'Transition from digital"O" to digital "1" initiates encoding.
1000tputdata are TIL-compatible when analog input iswitbin specified
range. Negative over.voltage inputs cause tri-state output to drift
Bit I,
Bit I-Bit 12
V
ITLLoads
ns,max
fO "high"conditionand maycreatecmmeousoutput(seetext).
3·State; NRZ
''O''=Oto +0.5
"]"= + 2.4 to +S
I
10
ns
30
Complementary Binary
(CBIN)
Complementary Offset
Binary (COB)
Complementary 2's
Complement (C2SC)
mA(max)
mA(max)
mA(max)
mA(max)
W(max)
55(70)
65(80)
19;(235)
35(40)
3.0(3.6)
'C
'C
Oto +70
-55to +150
IlCascTcmperature. Models HAS-1201SMlSMBwilloperate witb
derated performance over temperature range of - SS"C to + lOOOC;
contact factory for details.
12Muimumjuncrion temper8rureis + lSO"C.
USee Section 14 for package outline information.
Specifications subject tochange without notice.
TEMPERATURE RANGE II
Operatins
Stotage
THERMALRESISTANCE 12
Junction to Air, Sja (Free Air)
Junction to Case, Dje
'CIW
12
'CfW
2.5
-2510+85
PACKAGE OPTION"
HAS-1201KM
M-46
For applications assistance, phone Computer Labs Division at (919) 668~9511
3-574 ANALOG-TO-OIGITAL CONVERTERS
IIn~Band Harmonics expressed in terms of spurious in-band signals
generated at IMHzencode rate at analog inputs shown in ( ).
2MeasuredfromleadingedgeofEncodeCommand totimt associated
HAS-120ISM
HASI20lSMB
Theory of Operation - HAS-1201
THEORY OF OPERATION
nanoseconds, the' interval required for internal processing of
data.
Refer to the block diagram of the HAS-1201 AID Converter.
During the first 50 nanoseconds of each hold period, valid data
resulting from the previous encode command continue to be
applied to the output register. But then, internal switching
within the HAS-120l causes changes to occur until the conversion cycle initiated by the most recent encode command is
completed.
This is a functional illustration of the HAS-120l AID Converter.
Internally, the converter uses digitally corrected subranging
(OCS) pioneered by Analog Devices to generate 14 bits of digital
data. The two extra bits are used for digital correction to assure
that the 12 bits of parallel output data are an accurate representation
of the analog input signal present at the time of the encode
command.
Referenced to the leading edge of the encode command, minimum
spacing on the Register Strobe is 95Ons; maximum spacing is
shown with the Register Strobe in dotted lines.
The analog signal to be digitized is applied to an internal track-andhold (T!H), whose change between the "track" and "hold"
modes is determined by the HAS-1201 internal timing circuits.
Applying an encode command (at Pin 3) triggers these circuits
and causes the required timing signals to be generated.
Output data at Pins 11-23 remain valid until updated by a Register
Strobe. As noted, this validity interval is based on having the
ENABLE connected to either digital "0" or ground.
Timing intervals for the various signals involved in the operation
of the HAS-1201 AID Converter are shown in Figure 1.
In Figure I, the timing of the signals labeled ENABLE and
OUTPUT DATA are not referenced to the ENCODE COMMAND; their timing is related only to each other.
Understanding the operation of the HAS-1201 is easiest when
the timing of events is related to the leading edge of the Encode
Command. Minimum width of that signal is sOns; maximum
width is the period of the encode rate less 3SOns. A square wave
is always an acceptable encode signal for the HAS-120l
converter.
If the ENABLE pulse is used to strobe output data into external
circuits, the user must assure its arrival corresponds to the
availability of valid data. When the ENABLE is at digital "1",
output data present a high impedance to external circuits. Changing
ENABLE to a digital "0" causes the three-state logic outputs to
become low impedances and makes them available for strobing.
For purposes of illustration, spacing between Encode Commands
#1 and #2 in Figure I is approximately equal to a word rate of
500kHz.
In the block diagram, the external connection of the encode
command (Pin 3) to the register strobe (Pin 8) is the connection
which might be used if the HAS-120l were operating at a continuous maximum encode rate of 1.05MHz. Under these circumstances, the output data resulting from Encode Command
# I will be strobed out of the converter with the leading edge of
Encode Command #2.
When the encode command is applied, the unit switches to the
hold mode for approximately 670 nanoseconds; the length of the
track mode is a function of word rate. When operated at its
maximum frequency, the HAS-1201 will remain in "track" 280
::fl::
#1
ENCODE
COMMAND
#2
nL-._
MIN=50ns; MAX=ENCODE PERIOD- 350n&
HOLD
J
670115
TYPICAL
TRACK/HOLD,
I
• L_TR_A.;..CK_ _ _ _ _ _ _ _----'
I-- MAXIMUM = 950n. ~
~;--"'--INTE=R--N-A-LD-A-:Tc-A-VA..,.U"'D-~VVWi1il
R~~T:¥:R ~
(ENCODECOMMAND#1!..
/IfJIJIJI:Jf1
DATA TO
REGISTER
STROBE
OUTPUT
DATA'
~
MAXIMUM=lIENCODE+50ns
•
I
flL-----
MINIMUM=950ns-n
~_ _ _ _ _ _ _ _ _ _ _ _
~ L._ _ _ _ _ _ _~,
DATAVAUD
DATA VALID
(ENCODE #1)
(ENCODE #0)
'-r'
DATA
CHANGING
-. II
-.J I- MIN.= On.
--,
I MAX. =25ns
MAX.=2Sn. - I
)--
OUTPUT
.-----i
DATA' _ _ _ _ _ _H_IG_H_Z_~_'._5V_ _ _ _ _~C
NOTES
~~~ ~~t:~~ ~~~~I~IFED TO DIGITAL ·0· OR GROUND.
Figure 1. HAS-1201 Timing Diagram
ANALOG-TO-D/G/TAL CONVERTERS 3-575
OPERATING HAS-1201 AT WORD RATES LESS
THAN MAXIMUM
If encode commands,are appIiedasyncbronously, direct connection
of these pins results in variations in the times when output data
are avaiJable, because of pipeline delay through the converter
and the differences in intervals between encode commands.
With Pins 3 and 8 connected, the leading edge of each encode
command is the signal which strobes output data generated by
the preceding encode command. There is no separate, designated
output signal indicating data are valid.
As an example, assume the HAS-1201 encode rate varies around
500kHz, but with relatively large differences in the times between
encode commands. Under these conditions, the avaiJability of
output data will vary; it is often preferable to have outputs
avaiJable a specified interval after each encode command. A
method to achieve this is shown in Figure 2.
The insertion of a delay circuit between the encode command
input and the strobe input of the HAS-12Ol makes it possible to
use each digital output word at a precise time after its ass0ciated encode command, even when operating the converter'
asynchronously.
The delay circuit can take any of several forms. The user may
opt to use a fixed delay line with a delay of 950ns or more; in
other cases, shift registers could be used. Another possibility is
a variable delay, such as multivibrators, adjusted to the optimum
delay for each application.
In this latter approach, the period of the multivibrators can be
set to any desired time between a minimum of 950ns (the period
of l.05MHz) and a maximum determined by the period of the
highest word rate to be used.
FOR UNIPOLAR
NEGATIVE INPUT:
CONNECT
BIT 1 (MSB)
HAS-1201
@)TO@)
FOR UNIPOLAR
PosmVE INPUT:
CONNECT
e
BIT 1 (MSB)
BIT 2
BIT 3
TO @)
BIT4
BITS
BIT6
BIT 7
TIMING GENERATOR
iii'fii
BIT 9
BI110
BIT 11
BI112 (LSB)
-15V
Figure 2. HAS-1201 Connection Diagram
3-576 ANALOG-TO-DIGITAL CONVERTERS
HAS-1201
CONNECTING HAS·1201 AID CONVERTER
At the analog input, the user connects offset (Pin 38) externally
to either Pin 43 or Pin 44 to obtain, respectively, unipolar negative
or unipolar positive input ranging. The analog signal to be
digitized is applied to Pin 39, the IOV input; or to Pin 40, the
5V input, depending upon the application. Examples are shown
in Figures 3A·3O.
INPUT
O---y#."*{'
In Figure 30, the recommended operational amplifier is an
AD741. For 5V Unipolar Negative inputs using this circuit,
connect Pin 43 to the positive input of the op amp and leave
Pin 44 open.
•
I)....."N~-
INPUT~~_-{
Figure 3A
5V FS Bipolar input
Gain adjustment ::t 5% FS
Offset adjustment ::t 5% FS
(Adjust offset first)
Figure 38
Figure 3C
IOV FS Unipolar Positive input
Gain adjustment ::t U)°A, FS
Offset adjustment ::t 5%
(Adjust gain first)
IOV FS Bipolar input
Gain adjustment ::t 5% FS
Offset adjustment ::t 5% FS
(Adjust offset first)
39k
INPUT 0 - - - - (
INPUT O-'Yf/\.....-{
-<
INPUTo-W. . .
Figure 30
IOVFS Unipolar Negative input
Gainadjustment::t IO%FS
Offset adjustment ::t 5%
(Adjust gain first)
Figure 3E
Figure 3F
5V FS Bipolar input
Gain adjustment ::t 20% FS
No Offset adjustment
5V FS Bipolar input
No Gain adjustment
Offset adjustment ::t 5% FS
Various input ranges with fixed gain and offset are shown in
Table I.
-10.24V
Figure 3G
5V Unipolar Positive input
Offset adjustment ::t 5%
No Gain adjustment
(see text)
INPUT RANGE
CONNECT PINS
IOVBipo1ar
IOVUni. Pos.
IOVUni.Neg.
None
38 to 44
38 to 43
39
39
39
5VBipo1ar
5VUni.Pos.
5VUni.Neg.
None
38 to 44
38 to 43
40
40
40
4VBipoiar
38 to 40
(SOO ohms impedance)
40
INPUT PIN
Table I.
ANALOG-TO-OIGfTAL CONVERTERS 3-577
Regardless of the input connection being used, certain basic
rules of layout should be observed for any high-speed circuit;
this is particularly important for high-resolution devices such as
the HAS-1201.
Bypass capacitors are used intema1ly, but all power supplies
should be bypassed extema1ly, with O.OI,..F-{).I,..F ceramic
capacitors. Electrolytic capacitors of 10-22 microfarads should
also be used on each supply; all capacitors should be connected
as closely as possible to the supply pins.
A massive ground plane, careful component layout, and physically
separating analog and digital signsls are among other requirements
for assuring the high-speed, high-resolution characteristics of
the HAS-120l AID Converter.
The results of that testing are shown in Figure 4.
This diagram is an average analysis, based on ten readings. In
~ test, a 104kHz sine wave is applied as the analog input (Q,
at a level of IdB below full scale; the HAS-120l is operated at a
word rate of 1.05MHz.
The FFr is based on 512 sample points, with Hanning weighting
applied to the digital representations of the analog samples. The
resulting spectrum demonstrates the exceptional performance of
the converter, particularly in terms of low noise and harmonic
distortion.
In Figure 4, the vertical scale is based on a full-scale input
referenced as 0dB. In this way, all (frequency) energy cells can
be calculated with respect to full-scale rma inputs.
Supply voltages must be applied to all pins for which they are
designated. It is also extremely important to connect all grounds
together, and to a solid, low-impedance ground plane.
or-----~------~------r-----~------~~
Cooling air should be passed over the unit when it is being
operated; it should be supplied at 300-500 linear feet per minute
(LFPM).
The ""EN"""'AB=-L"'E signal at Pin 10 can be used for connecting the
three-state logic outputs of the HAS-1201 to a bus. A logic "1"
at this pin makes the logic outputs "float" at approximately 1. 5
volts and causes them to be high impedances during the time
other signals are applied to the computer or microprocessor bus.
-~~----~~----4_------~-----+------+_4
dB
If the HAS-1201 is not connected to a bus, i.e., it is being used
as a system AID, the ENABLE pin should be connected to
logic "0" or ground.
When using the unit as a (free-standing) system AID, the user
should keep in mind the output characteristic noted in the footnotes
of the Specifications table on Page 2 of this data sheet.
As a negative-going analog input is increased in value, the digital
output of the HAS-I20 1 follows the changes until all outputs
are at logic "}!' (unit is operating with Complementary Offset
Binary logic), indicating maximum negative analog input. Any
further increase in negative input (overranging) will cause the
tri-state digital outputs to "float".
The exception to this is the Bit 1 (MSB) at Pin 11. Internal
pulldown resistors cause it to go to logic "0" and remain.
When they are in an overrange condition, the digital outputs
need to look "high". This means the load on the output must
pull the open circuits to the "high" state; this requirement
normally presents no problem when driving standard TIL or
Schottky TIL inputs.
When driving low-power Schottky inputs, the ,change to "high"
will have a slower rise time; it may require up to lOOns. For
these, the user should avoid clocking the output data too soon.
CMOS circuits have no provision for pulling up the converter's
outputs. In this situation, the recommended procedure is to use
2k pull-up resistors connected to + 5 volts.
TESTING HAS-1201 PERFORMANCE
Sophisticated converters of the type represented by the HAS-I20 1
AID Converter require sophisticated testing to assure they meet
or exceed their specified performance parsmeters. One of these
test methods is a Fast Fourier Transform (FFT) analysis of the
converter output.
3-578 ANALOG-TO-DIGIIAL CONVERTERS
100
200
300
~o
500
kHz
Figure 4. HAS-1201 Output Fast Fourier Transform
Besides the plot shown, the computer testing also supplies numerical data stipulating the precise readings of the second and
third harmonics; and the sigoal-to-noise ratio (SNR). These
numbers have been replaced by a horizontal frequency scale for
purposes of illustration.
The original numbers indicated the peak amplitude of the second
harmonic (208kHz) was at a level of - 8IdB; the third harmonic
(312kHz) was at -85dB. The sigoal-to-noise ratio was measured
at 67.5dB, which corresponds to a noise floor of -68.5dB. All
of these numbers, like the plot, are IO-run averages of 512
sample points in each run.
The harmonic distortion numbers include five energy cells on
either side of the harmonics of 2 x t;" and 3 x t;,. Including these
cells helps negate the effects of side lobes caused by the Hanning
weighting and non-coherent sampling used for testing.
Hanning, or cosine, weighting is one of several methods of
generating FFr data; each method has certain characteristics
which make it more or less appropriate for various applications.
ORDERING INFORMATION
Three models of the HAS-I201 AID Converter are avaiJable.
For commercial operating temperatures between 0 and + 7O"C,
order model number HAS-1201KM. The HAS-1201SM is rated
over an operating temperature range of - 25"C to + 85"C, but
will operate with derated performance over a range of - 55"C to
+ loo"C. For units operating from - 25"C to + 85"C and military
screening, order HAS-1201SMB; contact the factory for details
about derated performance and military screening.
Ultrafast Hybrid
Ana Iog-to-Digital Converters
HAS-1202/HAS-1202A I
r-III ANALOG
WDEVICES
FEATURES
Conversion Time of 1.561Ls (HAS-1202A)
12-Bit Resolution
Conversion Rates to 641 kHz
Adjustment-Free Operation
APPLICATIONS
Waveform Analysis
Fast Fourier Transforms
Radar Systems
HAS-1202 FUNCTIONAL BLOCK DIAGRAM
(~{PRem~~~ED
ANALOG
GROUND
20'
:~;E:'~~~
~
SOURCE
~
DfA OUTPUT
B:rF~~~ (29
+5V
I!L,
CURRENT OUTPUT D/A CONVERTER
1+10.24mAI
J
t,
IMS.)
:::
~,
I
>;:
I
I
I
I
I
DlGITAt~
~~~:«?
COMP~~;
(~
(Z
ANALOG
INPUT'
-,5V
L;:'
~
~!~,
HAS,'2D2
140
These converters and the Analog Devices Model HTC-0300A
T IH offer designers an opportunity to go from analog to digital
with savings in power, board space, design time, and component
costs.
They are ideally suited for applications which require excellent
performance with a minimum of adjustments. Included in these
~
r4\?
~J
~
SUCCESSIVE APPROXIMAnON REGISTER
AND DIGITAL DRIVER
I
I
I
I
OA~~~AOV
I
ULTRA'~H'SPEEDL----":;;''';rt---'T'''
.----~
CO~N~~~ (:{332~_ _ _C_O_M_PA_R_AT_O_R_ _ _---70dB below FS, max
Spurious Signals >6SdB below FS, max; >68dB, typ
See Text and Timing Diagram
SMHz
±2Spsmax
30ns (±10ns from unit to unit)
66dB min; 68dB, typ
S6dB min, S8dB typ
12-Bit (0.0125%) Accuracy within 200ns
200ns
lsMHz min
10MHz min; flat within ±O.ldB, dc through SMHz
ANALOG INPUT
Voltage Range
Impedance
Offset Voltage
Offset vs. Temperature
Bias Current
ENCODE COMMAND INPUT
Logic Levels, TTL Compatible
Logic Loading
Rise and Fall Times
Duration minImax
Frequency (R~'1dom or Periodic)"
DIGITAL DATA OUTPUT
Format
Logic Levels, TTL Compatible
Drive (Not Short Circuit Protected)
Time Skew
Coding
Conversion Time
±2.048VFS
±4V Absolute max
400n with pin 30 open, son with pin 30 grounded
Adjust to 0 with On Board Potentiometer
0.02% FS/"C, type; 0.05% of FS/"C, max
InA max
"0" = 0 to +0.4V
"1" =+2.4V to +SV
2 Standard TTL Gates
IOns max
2Sns/SO% of Duty Cycle
SMHz
12 Parallel Bits, NRZ
"0" =0 to +O.4V
"1" = +2.4V to +sV
Up to 1 Schottky TTL or
2 Standard TTL Loads
IOns max
Offset Binary (OBN) or 2's complement (2SC)
See Text on the Next Page
POWER REQUIREMENTS"
+lSV ±S%
-lSV ±5%
-6V±4%
+SV±S%
Power Consumption
200mA
lS0mA
700mA
800mA
13 Watts
TEMPERATURE RANGE
Operating
Storage
Cooling Requirements
o to +70°C
-55°C to +8s o C
500 Lindar Feet Per Min (LFPM)
PHYSICAL CHARACTERISTICS
Construction
Single Printed Circuit Card
NOTES,
I AC linearity expressed in terms of spurious in-band signals generated at specified encode
rates at analog input frequencies ( ).
2rms signal to rms noise at 500kHz analog input.
.
'de to 2.4MHz white noise bandwidth with slot frequency of 512kHz.
4 For full""lcale step input, attains 12..t>it accuracy in time specified.
'Recovers to 12-bit accuracy after 2 X FS input overvoltage in time specified.
6For operation at word rates below 500kHz, consult factory.
Specifications subject to change without notice.
3-594 ANALOG-TO-DIGITAL CONVERTERS
@
+70oC
MOD-1205
BIT ,
BIT 1
MSB
PIN
1
2
••"
S
1
8
9
10
11
12
I.
,.
I.
16
FUNCTION
ENCODE COMMAND
QND"
+.V
GND·
GNC·
-'N
-BV
BITl
BITl eMSB)
81T2
81T3
SIT4
81TS
BIT6
81T7
BIT8
PIN
11
18
19
20
21
22
2"
24
2.
26
21
28
26
30
I
FUNCTION
BITD
l~
TERMINATION
81Tl0
BIT"
BIT 12 CLSSI
+lSV
I~
15
ANALOG
INPUT
:~
Ill!
1°
ANALOG
-15V
GROUND
GND*
I
GNC·
81T 12
LS8
GNO+5V
-BV
GNOGND-
ENCODE
COMMAND
.,
TERMINATION
GNC-
ENCODE
COMMAND
GROUND
.2
ANALOG INPUT
II
1
INPUT
-ALL GROUND PINS ARE CONNECTED TOGETHER
WITHIN THE MOD·l206
+16V
NOTE:
Pin Designations
- 15V
+6V
~v
WITH PIN 30 OPEN, ANALOG INPUT IMPEDANCE IS 4000. WITH PIN 30
GROUNDED. ANALOG IMPEDANCE IS son.
MOD-1205 Block Diagram
three encode command pulses are required to shift the data to
the output of the AID. For example, with a SMHz encode rate,
data is valid 67Sns ±2Sns after the application of the first encode command pulse-assuming that two pulses occur after
the first.
ORDERING INFORMATION
Order model number MOD-l20S AID converter. Mating pin
sockets for the MOD-l20S are model number MSB-2 (32
required per AID).
CONVERSION TIME
Output data is valid two encode command clock periods plus
27Sns ±2Sns after application of an initial encode command
pulse. Due to the pipeline delay effect of the AID, a total of
Use of the trailing edge of the encode command is recommended for strobing output data into external register (see
.
Figure 1).
o
200no
4oono
600n.
BOOn.
I
I
I
I
I
ENCODE
COMMAND
DATA
OUT
DATA TN-3
VALID
DATA TN+1
VALID
DATA TN (THE RESULT OF ENCODE COMMAND TN) OCCURS TWO CON·
VERSION PERIODS PLUS 275n. ±25no AFTER ENCODE COMMAND TN.
FOR A 5MHz WORD RATE AS SHOWN, DATA IS VALID 275n. ±25no
AFTER THE THIRD ENCODE COMMAND PULSE OR TN + 675no ±25n••
IN ALL CASES, THREE ENCODE COMMAND PULSES ARE REQUIRED
FOR TRANSFER OF DATA TO THE OUTPUT, DUE TO THE PIPELINE
DELAY EFFECT THROUGH THE AID. NO DATA READY PULSE IS
SUPPLIED.
Figure 1. MOD-1205 Timing Diagram
ANALOG-TO-DIGITAL CONVERTERS 3-595
GROUND CONNECTIONS
It should be noted that the MOD-120S PC board has 9 ground
pins. These are all connected to the ground plane on the board.
For best results it is recommended that ALL of these pins be
connected to a massive system or "mother board" ground
plltne.
code, observe that the digital output is changing between
100000000000 and 0 11111111111 at this adjustment level. When properly adjusted a digital code of
100000000000 will represent an analog input 112LSB
above zero volts, and. a digital code of 0 111 111 11111
will represent an analog input of 1I2LSB below zero volts.
CALIBRATION PROCEDURE (MOD-120S)
The MOD-120S AID is precisely calibrated at the factory before shipments and should need no further calibration. However, if slight readjustments of the AID are required in the
system, the following procedure should be followed. This
procedure refers to a binary output.
Gain Adjustment
The gain is adjusted by varying potentiometer R2. This adjustment is made by applying +2.046SV (FS -1 1I2LSB) to the
analog input and while monitoring the digital output, adjust
R2 for the output code varying between 111111111110
and 111111111111 (FS). If the user needs to offset the
entire range of the AID, this can be accomplished by a readjusting
R22 as required. However, in this procedure, the offset should
always be adjusted first.
Offset Adjustment
The offset is adjusted by varying potentiometer R22 with 0
volts applied to the analog input. To obtain the proper output
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
5.00 (127)
4.54 (115.3)
-r-
---------11
-
~.
_I 0.040 • 0.002 DIA
(1.0IU 0.05)
--,
I
0.167·0.173 DIA
(4.24-4.39)
4 PLACES
5.43
137.9)
5.0
(127)
'--
21 ..
L..-
CONDUCTOR SIDE
BOTTOM VIEW
WEIGHT, 5 OZ; 142 G
3-596 ANALOG-TO-DIGITAL CONVERTERS
"32
--I I--
0.2 (5.08) GRID
~
0.30' 0.02
(7.69 to.51)
_...J
~
112.7)
MAX
V/F & F/V Converters
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . . . . .
4-2
Orientation . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
AD537 - Integrated Circuit Voltage-to-Frequency Converter
4-5
AD650 - Voltage-to-Frequency and Frequency-to-Voltage Converter.
4-13
AD652 - Monolithic Synchronous Voltage-to-Frequency Converter
4 - 25
AD654 - Low Cost Monolithic Voltage-to-Frequency Converter . . .
4- 41
4-49
ADVFC32 - Voltage-to-Frequency and Frequency-to-Voltage Converter
VIF & FN CONVERTERS
~1
•
t Selection Guide
~ VIF and FN Converters
~
8
<:
VOLTAGE-TO-FREQUENCY CONVERTERS
FS
tii
CaJib
:Jj
rrI
~
Full-Scale
Frequency
Model
MHz
Linearity
%
max
Error
%
typ
Output
Format
AD652
2
0.005-0.05
0.25-0.5
Pulse Train
AD650
AD654
ADVFC32
AD537
1
0.5
0.5
0.15
0.005-0.1
0.1-0.4
0.01-0.2
0.07-0.25
5-10
10
5
5
Pulse Train
Square Wave
PuIse Train
Square Wave
Input
Range
V
oto 10
oto -10
:1:5
-10 to 0
oto (Vs-4)
oto 10
-Vs to C+Vs-4)
Package
Options!
Temp
Range2
Page
Comments
Q,P
C,I,M
4-25
Synchronous, Multiple Input Ranges,
Low Nonlinearity
D,N,P
N,R
H,N
D,H
C,I,M
C
C,I,M
C,M
4-13
4-41
4-49
4-5
Low Nonlinearity
Single Supply, Low Cost
Industry Standard
FREQUENCY-TO-VOLTAGE CONVERTERS
Model
Input
Range
kHz
Linearity
%
max
Response
Time
ms
typ
Package
Options!
Temp
Range2
Page
Comments
451
453
oto 10
oto 100
0.03-0.008
0.03-0.008
4
0.8
Module
Module
I
I
W
W
Complete, No Extemal Components
Complete, No Extetnal Components
'Package Options: D-Side-Braied Dual-In-Line Ceramic; H-Round Hermetic Metal Can (Header); N-Plastic Molded Dual-In-Line; P-Plastic Leaded Chip Carrier (PLCC); Q-Cerdip; R-Small Outlioe
Plastic (SOlG).
2Temperature Ranges: C-Commercial, 0 to +70'C; I-Industrial, -40'C to +85'C (Some older products -25'C to +85'C); M-Military, -55'C to + l25'C.
iN = Design-In product still available, but not included in catalog. Ask your local sales office for datasbeet.
Boldface Type: Product recommended for new design.
Orientation
VIF &FIV Converters
VOLTAG£-TO-FREQUENCY CONVERTERS
Voltage-to-frequency converters (VFCs) convert analog voltage
or current levels to pulse trains or square waves in a logiccompatible form (usually TTL) at frequencies that are accurately
proportional to the analog quantity. The output continuously
tracks the input signal, responding directly to changes in the
input signal; external clock synchronization is not required. VIF
converters find applications in analog-to-digital converters with
high resolution, long-term high-precision integrators, two-wire
high-noise-immunity digital transmission and digital voltmeters.
FREQUENCY-TO-VOLTAGE CONVERTERS
Frequency-to-voltage converters (FVCs) perform the inverse
operation; they accept a wide variety of periodic waveforms and
produce an analog output proportional to frequency. Combining
adjustable threshold, gain and output offset with low linearity
error, FN converters offer economical solutions to a wide variety
of applications where it is required to convert frequency to an
analog voltage. Examples are motor-speed controllers, power-line
frequency monitors and VCO stabilization circuits. In analog-toanalog data transmission, they convert serially transmitted data
in the form of pulse streams back to analog voltage.
Applications of both forms of conversion, as appropriate to
specific device types, are illustrated with varying degrees of
detail on the individual data sheets.
FACTORS IN CHOOSING VFCs AND FVCs
Voltage-to-frequency converters are available from Analog Devices
in both pulse train and square wave outputs. The output of
the change balance types which can operate up to IMHz F.S.,
is a train of pulses of constant height and width, with very low
duty cycle for small analog inputs. The output of the AD537
is unique in that its output is square wave, an advantage
in some applications.
The most popular VFC designs (Figure I) contain an integrator
which charges at a rate proportional to the value of the input
signal. Each time the integrator's charge has been increased by a
precisely metered increment, the threshold crossing produces a
pulse of accurately known area. The pulse serves both as the
output (via a buffer) and as a subtractive charge increment to
ONE SHOT
CAPACITOR
FoUTPUT
10 COMPARATOR
INPUT
7
Figure 1. Block Diagram of the ADVFC32
reduce the integrator's net charge. The next pulse is triggered
when the net integral has again reached the threshold. The
relationship between the pulse rate and the input level is linear.
The AD537 operates on a somewhat different principle (Figure
2); an input current charges a capacitor between two threshold
levels, first in one direction, then in the other, in an emitter-coupled
astable multivibrator circuit. Since the time required to reach
the switching threshold is inversely proportional to the analog
input, the frequency is directly proportional. For constant analog
input, the charging rate and the discharge rate are equal, so the
output is a square wave.
Figure 2. Block Diagram of the AD537
VlF & FN CONVERTERS 4-3
SPECIFICATIONS
The salient specifications for VFCs are (non)linearity, as a percentage of full-scale frequency; frequency range, the greater the
frequency range, the greater the resolution for a given counting
period; full-scale-calibration error; gain-temperature coefficient, in
ppm of signal per °C, where "gain" is the ratio of full-scale
frequency to full-scale voltage; input-offset temperature coefficient;
overrange capability, within rated specifications, and step response,
the worst-case time interval required for the frequency to respond
to a full-scale-step input change.
Figure 3. Block Diagram - Models 451 & 453 FVCs
Frequency-to-voltage converters (Figure 3) average a train of
equal-area pulses that are generated internally by a precision
charge dispenser in response to each crossing of an input threshold.
The analog output voltage is proportional to the sum of the
pulse areas over a given period. FN conversion can also be
. obtained by using the ADVFC32.
4-4 VlF & FN CONVERTERS
For FVCs, important specs, in addition to accuracy specs corresponding to the above, include output ripple (for specified
input frequencies), threshold (for recognition that another cycle
has been initiated and for versatility. ill interfacing various types
of sensors directly), hysteresis (to provide a degree of insensitivity
to noise superimposed on a slowly-varying input waveform) and
dynamic response (important in motor control).
Definitions of some critical specifications, and the conditions for
adjusting or measuring them, are detailed on individual data
sheets.
11IIIIIIII ANALOG
WDEVICES
FEATURES
low Cost A-D ConveRion
Versatile Input Amplifier
Positive or Negative Voltage Modes
Negative Current Mode
High Input Impedance, low Drift
Single Supply, 5 to 36 Volts
linearity: ±0_05% FS
low Power: 1_2mA Quiescent Current
Full Scale Frequency up to 100kHz
1_00 Volt Reference
Thermometer Output (1mV/K)
F-V Applications
Integrated Circuit
Voltage-to-Frequency Converter
AD537* I
AD537 PIN CONFIGURATIONS
"D" Package - TO-116
"u" Package - TO-100
7
~Vs
PRODUCT DESCRIPTION
The ADS37 is a monolithic V-F converter consisting of an input amplifier, a precision oscillator system, an accurate internal reference generator and a high current output stage. Only
a single external RC network is required to set up any full
scale (F.S.) frequency up to 100kHz and any F.S. input voltage up to ±30V. Linearity error is as low as ±0.05% for 10kHz
F.S., and operation is guaranteed over an SOdB dynamic range.
The overall temperature coefficient (excluding the effects of
external components) is typically ±30ppm/oC. The 1\D537
operates from a single supply of 5 to 36V and consumes only
1.2mA quiescent current.
A temperature-proportional output, scaled to 1.00mV/K,
enables the circuit to be used as a reliable temperature-tofrequency converter; in combination wiJh the ~xed reference
output of 1.00V, offset scales such as 0 Cor 0 F can be
generated.
The low drift (lp.V/C typ) input amplifier allows operation
directly from small signals (e.g., thermocouples or strain gages)
while offering a high (250MQ) input resistance. Unlike most
V-F converters, the ADS 37 provides a square-wave output, and
can drive up to 12 TTL loads, LEDs, very long cables, etc.
The excellent temperature characteristics and long-term stability of the AD537 are guaranteed by the primary band-gap
reference generator and the low T.C. silicon chromium thin
film resistors used throughout.
CAP
(CONNECTED TO CASE)
PRODUCT HIGHLIGHTS
1. The AD537 is a complete V-F converter requiring only an
external RC timing network to set the desired full scale
frequency and a selectable pull-up resistor for the opencollector output stage. Any full-scale input voltage range
from 100mV to 10 volts (or greater, depending on +VS) can
be accommodated by proper selection of timing resistor.
The full scale frequency is then set by the timing capacitor
from the simple relationship, f = V/I0RC.
2. The power supply requirements are minimal, only 1.2mA
quiescent current is drawn from a single positive supply
from 4.5 to 36 volts. In this mode, positive inputs can vary
from 0 volts (ground) to (+Vs ~ 4) volts. Negative inputs can
easily be connected for below ground operation.
3. F-V converters with excellent characteristic are also easy to
build by connecting the AD537 in a phase-locked loop. Application particulars are shown in Figure 6.
4. The versatile open-collector NPN output stage can sink up
to 20mA with a saturation voltage less than 0.4 volts. The
Logic Common terminal can be connected to any level between ground (or -VS) and 4 volts below +Vs. This allows
easy direct interface to any logic family with either positive
or negative logic levels.
The device is available in either a TO-1l6 ceramic DIP or a
TO-lOO metal can; both are hermetically sealed packages.
The AD537 is available in three performance/temperature
grades; the J and K grades are specified for operation over the
o to +70oC range while the AD537S is speocified for o,reration
over the extended temperature range, -55 C to +125 C.
·COVBRED BY PATENT NUMBERS 3,887,963 and RE 30,586_
VIF & FN CONVERTERS 4-5
II
SPECIFICATIONS (typical
MODEL
CURRENT-TO-FREQUENCY CONVERTER
Frequency Range
Nonlinearity'
f max = 10kHz
f max = 100kHz
Full Scale Calibration Error
C = O.Olj.1F. lIN = 1.00OmA
vs. Supply (fmax < 100kHz)
vs. Temp. (Tmin to Tmax)
ANALOG INPUT AMPLIFIER
(Voltage-to-Current Converter)
Voltage Input Range
Single Supply
Dual Supply
Input Bias Current
(Either Input)
Input Resistance (Non-Inverting)
Input Offset Voltage
(Trimmable in "D" Package Only)
vs. Supply
vs. Temp. (Tmin to TmlX )
Safe Input Voltage'
REFERENCE OUTPUTS
Voltage Reference
Absolu te Value
vs. Temp. (Tmin to T mIX)
vs. Supply
Output Resistance 4
Absolute Temperature Reference'
Nominal Output Level
Initial Calibration@+2SoC
Slope Errorfrom 1.0OmViK
Slope Nonlinearity
Outpu t Resistance'
OUTPUT INTERFACE (Open Collector Output)
(Symmetrical Square Wave)
Output Sink Current in Logic "0"
VOUT = 0.4V max, Tmin to Tmax)
Ou tpu t Leakage Current in Logic "1 "
(Tmin to Tmax)
Logic Common Level Range
Rise/Fall Times (Cy = O.Ol/lF)
lIN = 1mA
lIN = l/lA
@ +25°C with Vs (total)
=5 to 36V, unless otherwise noted)
AD537jH
ADS37JD
AD537KD
AD537KH
o to lS0kHz
0.07% max
0.1% max
0.15% max (0.1% typ)
0.2S% max (O.lS% typ)
±10%max
±O.l%N max (0.01% typ)
±lSOppmfC max (SOppm typ)
±7%max
±S% max
SOppmtc max (30ppm typ)'
100nA
2S0MO
.
5mVmax
200j.lVNmax
S/lV/oC
±VS
100/lVN max
2mVmax·
100/lVNmax
1j.1VfC
..
lOpV/oC max
.
l.00 Volt ±S% max
SOppmfC
±0.03%Nmax
3800
10Oppm/oC max'
l.OOmV/K
298mV (±SmV)
±0.02mV/K
±o.lK
900n
~98mV
20mAmin
20mAmin
(±SmV max)
20mAmin
lOmAmin
2pAmax
200nAmax
-Vs to (+Vs - 4) Volts
0.2/ls
1/lS
4.SV to 36V
±S to±18V
l.2mA (2.SmA max)
TEMPERATURE RANGE
Rated Performance
Storage
o to +70oC
-6SoC to +lS0oC
PACKAGE OPTlONS 6
TO-1l6 Ceramic DIP (D-14)
TO-100 Header (H -lOA)
ADS37JH
-SSoC to +12SoC
ADS37]D
ADS37KD
ADS37KH
NOTES
·Specifications same as ADS37JH.
··Specifications same as AD537K.
Specifications subject to change without notice.
Nonlinearity is specified for a current input level (lIN) to the
converter from 0.1 to lOOOIlA. Converter has 100% overrange
capability up to lIN = 2000IlA with slightly reduced linearity.
Nonlinearity is defined as deviation from a straight line from
zero to full scale, expressed as a percentage of full scale.
2 Guaranteed not tested.
3 Maximum
voltage input level is equal to the supply on either
input tenninal. However, large negative VOltage levels can be
applied to the negative tenninal if the input is scaled to a nominal
1mA fuD scale through an appropriate value resistor (see Figure 2).
4 Loaciing the 1.0 volt or ImV/K outputs can cause a significant change
in overall circuit performance. as indicated in the applications section.
To maintain nonnal operation, these outputs should be operated
into the external buffer or an external amplifier.
'Temperature reference output performance is specified from 0 to +70o C
for "J" and "K" devices, -SSoC to +12SoC for "s" model.
• See Section 14 for package outline information.
4-6 VIF & FN CONVERTERS
1 SOppmt C max
o to (+VS - 4) Volts (min)
-Vs to (+Vs - 4) Volts (min)
POWER SUPPLY
Voltage, Rated Performance
Single Supply
Dual Supply
Quiescent Current
I
AD537SD'
ADS37SH'
ADS37SD
ADS37SH
AD537
CIRCUIT OPERATION
Block diagrams of the A0537 are shown above. A versatile
operational amplifier (BUF) serves as the input stage; its
purpose is to convert and scale the input voltage signal to a
drive current in the NPN follower. Optimum performance is
achieved when, at the full scale input voltage, a 1mA drive cur·
rent is delivered to the current·to-frequency converter. The
drive current to the current-to-frequency converter (an astable
multivibrator) provides both the bias levels and the charging
current to the externally connected timing capacitor. This
"adaptive" bias scheme allows the oscillator to provide low
nonlinearity over the entire current input range of 0.1 to
2000/lA. The square wave oscillator output goes to the output
driver which provides a floating base drive to the NPN power
transistor. This floating drive allows the logic interface to be
referenced to a different level than -Vs. The "SYNC" input
("0" package only) allows the oscillator to be slaved to an
external master oscillator; this input can also be used to shut
off the oscillator.
As indicated by the scaling relationship in Figure 1, a 0.01/lF
timing capacitor will give a 10kHz full scale frequency, and
0.001/lF will give 100kHz with a 1mA drive current. The maximum frequency is 150kHz. Polystyrene or NPO ceramic capacitors are preferred for T .C. and dielectric absorption; polycarbonate or mica are acceptable; other types will degrade linearity. The capacitor should be wired very close to the A0537.
The reference generator uses a band-gap circuit (this allows
single-supply operation to 4.5 volts which is not possible with
low T .C. zeners) to provide the reference and bias levels for the
amplifier and oscillator stages. The reference generator also
provides the precision, low T.C. 1.00 volt output and the
VTEMP output which tracks absolute temperature at 1mV/K.
If the input signal is a true current source, Rl and R2 are not
used. Full scale calibration can be accomplished by connecting
a 200kS1 pot in series with a fixed 27kS1 from pin 7 to -Vs
(see calibration section, below).
V-F CONNECTION FOR POSITIVE INPUT VOLTAGES
The positive voltage input range is from -V s (ground in single
supply operation) to 4 volts below the positive supply. The
connection shown in Figure 1 provides a very high (2S0MS1)
input impedance. The input voltage is converted to the proper
drive current at pin 3 by selecting a scaling resistor. The full
scale current is 1mA, so, for example a 10 volt range would
require a nominal10kS1 resistor. The trim range required will
depend on capacitor tolerance. Full scale currents other than
1mA can be chosen, but linearity will be reduced; 2mA is the
maximum allowable drive.
V-F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENT
A wide range of negative input voltages can be accommodated
with proper selection of the scaling resistor, as indicated in
Figure 2. This connection, unlike the buffered positive connection, is not high impedance since the lmA F.S. drive current must be supplied by the signal source. However, very large
negative voltages beyond the supply can be handled easily; just
modify the scaling resistors appropriately. ~iode CRl (HP50822811) is necessary for overload and latchup protection for current or voltage inputs.
Figure 2. V-F Connections for Negative Input Voltage or
Current
Figure 1. Standard V-F Connection for Positive Input Voltages
VIF & FN CONVERTERS 4-7
4
CALIBRATION
There are two independent adjustments: scale and offset. The
first is trimmed by adjustment of the scaling resistor R and the
second by the (optional) potentiometer connected to +Vs and
the Vos pins ("D" package only). Precise calibration requires
the use of an accurate voltage standard set to the desired FS
value and a frequency meter; a scope is useful for monitoring
ou tpu t waveshape. Verification of linearity requires the availability of a switchable voltage source (or a DAC) having a linearity error below ±0.005%, and the use of long measurement
intervals to minimize count uncertainties. Every ADS]7 is
automatically tested for linearity, and it will not usually be
necessary to perform this verification, which is both tedious
and time-consuming.
Although drifts are small it is good practice to allow the operating environment to attain stable temperature and to ensure that the supply, source and load conditions are proper.
Begin by setting the input voltage to 1/10,000 of full scale.
Adjust the offset pot until the output frequency is 1/10,000
of full scale (for example 1Hz for FS of 10kHz). This is most
easily accomplished using a frequency meter connected to the
output. Then apply the FS input voltage and adjust the gain
pot until the desired FS frequency is indicated. In applications
where the FS input is small, this adjustment will very slightly
affect the offset voltage, due to the input bias current of the
buffer amplifier. A change of 1kn in R will affect the input
by approximately 100j.tV, which is as much as 0.1% of a
100mV FS range. Therefore, it may be necessary to repeat
the offset and scale adjustments for the highest accuracy. The
design of the input amplifier is such that the input voltage
drift after offset nulling is typically below 1j.1V 1° C.
In some cases the signal may be in the form of a negative current source. This can be handled in a similar way to a negative
input voltage. However, the scaling resistor is no longer required, eliminating the capability of trimming full scale in this
fashion. Since it will usually be impractical to vary the capacitance, an alternative calibration scheme is needed. This is
shown in Figure 3. A resistor-potentiometer connected from
the VR output to -Vs will alter the internal operating conditions in a predictable way, providing the necessary adjustment range. With the values shown, a range of ±4% is available;
a larger range can be attained by reducing R 1. This technique
does not degrade the temperature-coefficient of the converter,
and the linearity will be as for negative input voltages. The
minimum supply voltage may be used.
4-8 VlF & FIV CONVERTERS
Unless it is required to set the input node at exactly ground
potential, no offset adjustment is needed. The capacitor C is
selected to be 5% below the nominal value; with R2 in its midposition the output frequency is given by
f=
I
10.5 X C
where f is in kHz, I is in rnA and C is in j.lF. For example, for
a FS frequency of 10kHz at a FS input of 1mA, C = 9500pF.
Calibration is effected by applying the full-scale input and
adjusting R2 for the correct reading.
This alternative adjustment scheme may also be used when it
is desired to present an exact input resistance in the negativevoltage mode. The scaling relationship is then
V
• __
1_
f = -R-exact-C..-- 10.5 C
The calibration procedure is then similar to that used for positive input voltages, except that the scale adjustment is by
mea.!'!s ofR2.
VLOGIC
, .. .!!L
lOC
Figure 3. Scale Adjustment for Current Inputs
AD537
INPUT PROTECTION
The AD53 7 was designed to be used with a minimum of additional hardware. However, the successful application of a
precision IC involves a good understanding of possible pitfalls
and the use of suitable precautions.
The -VIN' +VIN and lIN pins should not be driven more than
300mV below -Vs. This would cause internal junctions to conduct, possibly damaging the IC. The AD537 can be protected
from "below -Vs" inputs by a Schottky diode. CR1 (HP50822811) as shown in Figure 3. It is also desirable not to drive
+VIN' -VIN and lIN above +Vs. In operation, the converter
will become very nonlinear for inputs above (+Vs -3.5V).
Control currents above 2mA will also cause nonlinearity.
The 80dB dynamic range of the AD537 guarantees operation from a control current of 1mA (nominal FS) down to
100nA (equivalent to 1mV to 10V FS). Below 100nA improper operation of the oscillator may result, causing a false
indication of input amplitude. In many cases this might be
due to short-lived noise spikes which become added to the
input. For example, when scaled to accept a FS input of 1V,
the -80dB level is only 100IJV, so when the mean input is
only 60dB below FS (lmV), noise spikes of O.9mV are·sufficient to cause momentary malfunction.
This effect can be minimized by using a simple low-pass
filter ahead of the converter and a guard ring around the
lIN or -VIN pins. For a FS of 10kHz a single-pole filter with
a time-constant of lOOms (Figure 2) will be suitable, but the
optimum configuration will depend on the application and
type of signal processing. Noise spikes are only likely to be a
cause of error when the input current remains near its minimum value for long periods of time; above 100nA (lmV)
full integration of additive input noise occuts.
The AD537 is somewhat susceptible to interference from
other signals. The most sensitive nodes (besides the inputs)
are the capacitor terminals and the SYNC pin. The timing
capacitor should be located as close as possible to the
AD537 to minimize signal pickup in the leads. In some
cases, guard rings or shielding may be required. The SYNC
pin should be decoupled through a O.005IJF (or larger) capacitor to pin 13 (+Vs). This minimizes the possibility that
the AD537 will attempt to synchronize to a spurious signal.
This precaution is unnecessary on the metal can package since
the SYNC function is not brought out to a package pin
and is thus not susceptible to pickup.
DECOUPLING
It is good engineering practice to use bypass capacitors on
the supply-voltage pins and to insert small-valued resistors
(10 to lOOn) in the supply lines to provide a measure of
decoupling between the various circuits in a system. Ceramic
capacitors of O.lIJF to 1.0IJF should be applied between the
supply-voltage pins and analog signal ground for proper bypassing on the AD537.
A decoupling capacitor may also be useful from +Vs to SYNC
in those applications where very low cycle-to-cycle period variation (jitter) is demanded. By placing a capacitor across +Vs
and SYNC this noise is reduced. On the 10kHz FS range, a
6.81JF capacitor reduces the jitter to one in 20,000 which is
adequate for most applications. A tantalum capacitor should
be used to avoid errors due to dc leakage.
NONLINEARITY SPECIFICATION
The preferred method for specifying linearity error is in terms
of the maximum deviation from the ideal relationship after
calibrating the converter at full scale and "zero". This error
will vary with the full scale frequency and the mode of operation. The AD537 operates best at a 10kHz full scale frequency
with a negative voltage input; the linearity is typically within
±0.05%. Operating at higher frequencies or with positive inputs
will degrade the linearity as indicates in the Specifications
table. The shape of a typical linearity plot is given in Figure 4.
TEST CONDITIONS:
+'IIs"+15VOLTS
-Vs-OVOLTS
Cr"O.ot"F
RT'"lOk{l
J
~1;~: ~~~s_ FIG. 3
.•,
~
~
~
NEGATIVE INPUT - FIG.4
--+-H---+--f-++-I
--1-+-I--"'+--I.....J...+-I--
".04
+0.02
i . ..,
".04
.....
100
fO
OUTPUT FREQUENCY - Hz
Figure 4a. Typical Nonlinearity Error Envelopes with 10kHz
F.S. Output
+0.20
".1 • f- +'ST jON~I~,JN" I
+0.1 8
".14
;I
+0.1
:
+0.1
.•
,
>
~
~
f--
~
2
~
o l....-
+'11. =+15VOLTS
-Vs"'OVOLTS
CT'"O.O(I1,.F
f;537J-
RT"',Okn
~:I;~::~~-FIG.3
NEGATIVE INPUT - FIG. 4
.....
+0. •
7
V
".02
1/
~ ".02
1'\
"""
7'-...
-tf"i"K··
1-
.....
.....
".08
10
100
lk
OUTPUT FREQUENCY - Hz
'''''
Figure 4b. Typical Nonlinearity Error with 100kHz F.S. Output
VIF & FN CONVERTERS 4--9
II
OUTPUT INTERFACING CONSIDERATIONS
The design of the output stage allows easy interfacing to all
digital logic Jamilies. The collector and emitter of the output
NPN transistor are both uncommitted; the emitter can be tied
to any voltage between -Vs and 4 volts below +Vs. The open
collector can be pulled up to a voltage 36 volts above the emitter regardless of +Vs. The high power output stage can supply
up to 20rnA (lOrnA for "H" package) at a maximum saturation voltage of 0.4 volts. The stage limits the ou tpu t current
at 2SmA; it can handle this limit indefinitely without damaging the device.
Figure S shows the ADS37 with a standard 0 to +10 volt input
connection and the output stage connections. The values for
the logic common voltage, pull-up resistor, positive logic level,
and -Vs supply are given in the accompanying chart for several
logic forms.
r-_ _ _ _ _ _ _ _ _ _--<>~~~ICCOM
=-r-~fOUT
LOGIC Vee
~-.....,.....,
+v.
(+15Vl
,Ok
NIL
v,.
.+,. ,
.. .
•
.,.
•
v"
R
GND
NO
GND
51< GND
-2
51<
·V
-810
+1.3
10k -16
Figure 5. Interfacing Standard Logic Families
APPLICATIONS
The diagrams and descriptions of the following applications
are provided to stimulate the discerning engineer with alternative circuit design ideas. "Applications of the ADS37 IC
Voltage-to-Frequency Converter", available from Analog
Devices on request, covers a wider range of topics and concepts in data conversion and data transmission using voltageto-frequency converters.
...
+
Figure 6. True Two-Wire Operation
F-V CONVERTERS
The ADS37 can be used as a high linearity VCO in a phaselocked loop to accomplish frequency-to-voltage conversion.
By operating the loop without a low-pass filter in the feedback
path (first-order system), it can lock to any frequency from
zero to an upper limit dete1;'mined by the design, iesponding
in three or four cycles to a step change of input frequency. In
practice, the overall response time is determined by the characteristics of the averaging filter which follows the PLL.
Figure 7 shows a connection using a low-power TTL quad
open-collector nand gate which serves as the phase comparator.
The input signal should be a pulse train or square wave with
characteristics similar to TTL or S-volt CMOS outputs. Any
duty cycle is acceptable, but the minimum pulse width is 40#-1s.
The output voltage is one volt for a 10kHz input frequency.
The output as shown here is at a fairly high impedance level;
for many situations an additional buffer may be required.
Trimming is similar to V-F application trimming. First set the
Vos trimmer to mid-scale. Apply a 10kHz input frequency and
trim the 2kO potentiometer for 1.00 volts out. Then apply a
10Hz waveform and trim the Vos for ImV out. Finally, retrim
the full scale output at 10kHz. Other frequency scales can be
obtained by appropriate scaling of timing components.
+5V
TRUE TWO-WIRE DATA TRANSMISSION
Figure 6 shows the ADS 37 in a true two-wire data transmission
scheme. The twisted-pair transmission lines serves the dual purpose of supplying power to the device and also carrying frequency data in the form of current modulation. The PNP circuit at the receiving end represents a fairly simple way for
converting the current modulation back into a voltage square
wave which will drive digital logic directly. The 0.6 volt square
wave which will appear on the supply line at the device terminals does not affect the performance of the ADS 37 because
of its excellent supply rejection. Also, note that the circuit
operates at nearly constant average power regardless of
frequency.
Figure 7. 10kHz F-V Converter
4-10 VIF& FNCONVERTERS
AD537
TEMPERATURE-TO-FREQUENCY CONVERSION
The linear temperature-proportional output of the ADS37 can
be used as shown in these applications to perform various direct
temperature-to-frequency conversion functions; it can also be
used with other external connections in a temperature sensing
or compensation scheme. If the sensor output is used externally,
it should be buffered through an op amp since loading that
point will cause significant error in the sensor output as well
as in the main V -F converter circuitry.
An absolute temperature (Kelvin)-to-frequency converter
is very easily accomplished,asshown in Figure 8. The ImV
per K output serves as the input to the buffer amplifier, which
then scales the oscillator drive current to a nominal 298~A at
+2SoC (298K). Use of a 1000pF capacitor results in a corresponding frequency of 2.98kHz. Setting the single 2k.l1 trimmer
for the correct frequency at a well-defined temperarure near
+2SoC will normally result in an accuracy of ±2°C from -55°C
to +12S oC (using an ADS37S). An NPO ceramic capacitor is
recommended to minimize nonlinearity due to capacitance
drift.
2. Measure temperature output at pin 6 at that temperature.
3. Calculate offset adjustment as follows:
Offset Voltage (mV) = VTEMP (pin 6) (mV) x 273.2
Room temp (K)
4. Temporarily disconnect 49.11 resistor (or soon pot) and
trim 2k.l1 pot to give the offset voltage at the indicated
node. Reconnect 49.11 resistor.
S. Adjust slope trimmer to give proper frequency at room
temperature (+2S oC = 2S0Hz).
Adjustment for of or any other scale is analogous.
~~--.()~~~rc
10k
(10HzrFI
'5V
49H
(205m
3900pF
115OOpF)
6.04k
(lOkI
2.74k
{4.02Id
) - - ' - - - 0 f= 10Hz/K
Figure 9. Offset Temperature Scale Converters-Centigrade
and (Fahrenheit) to Frequency
v
+
~Vs
(CONNECTED TO CASE)
Figure 8. Absolute Temperature to Frequency Converter
OFFSET TEMPERATURE SCALES
Many other temperature scales can be set up by offsetting the
temperature output with the voltage reference output. Such a
scheme is shown by the Celsius-to-frequency converter in
Figure 9. Corresponding component values for a Fahrenheitto-frequency converter which give 10Hz/oF are given in parentheses.
A simple calibration procedure which will provide ±2°C accuracy requires substitution of a 7.27k resistor for the series
combination of the 6.04k with the 2k trimmer; then simply
set the soon trimmer to give 2S0B:z at +2SoC.
High accuracy calibration procedure:
1. Measure room temperarure in K.
SYNCHRONOUS OPERATION
The SYNC terminal at pin 2 of the DIP package can be used to
synchronize a free running AD 537 to a master oscillator, either
at a multiple or a sub-multiple of the primary frequency. The
preferred coimection is shown in Figure 10. The diodes are
used to produce the proper drive magnitude from high level
Signals. The SYNC terminal can also be used to shut off the
oscillator. Shorting the terminal to +Vs will stop the oscillator,
and the output will go high (output NPN off).
tOUT
V'N2VH ~
USE THIS LIMITER
VSVNC
0 ·10k
....
f!'1-m
Cs
I
17
I
IN4148:
'='
-=
6
I
L-_ _ _ _ _....
I
Figure 10. Connection for Synchronous Operation
VIF & FN CONVERTERS 4-11
Figure 11 shows the maximum pull-in range available at a given
signal level; the optimum signal is a 0.8 to 1.0 volt square wave;
signals below 0.1 volt will have no effect; signals above 2 volts
pop will disable the oscillator. The ADS37 can normally be
synchronized to a signal which forces it to a higher frequency
up to 30% above the nominal free-running frequency, it can
only be brought down about 1-2%.
....... 1V RMS SIGNAL
+ 1V RMS NOISE
~OUTPUT
Figure 13. Performance of AD537 Linear PhaseLocked Loop
FREQUENCY
LOCK·IN
RANGE
0.2
OA
0.6
0.8
By connecting the multiplier output to the lower end of the
timing resistor and moving the control input to pin 5, a highresistance frequency-control input is made available. However,
due to the reduced supply voltage, this input cannot exceed
+6V.
1.0
VSYNC SQUARE·WAVE INPUT VOLTS p"p
Figure ". Maximum Frequency Lock-In Range Versus Sync.
Signal
UNEAR PHASE LOCKED LOOP
The phase·locked-loop F N circuit described earlier operates
from an essentially noise-free binary input. PLL's are also used
to extract frequency information from a noisy analog signal.
To do this, the digital phase-comparator must be replaced by a
linear multiplier. In the implementation shown in Figure 12,
the triangular waveform appearing across the timing capacitor
is used as one of the multiplier inputs; the signal provides the
other input. It can be shown that the mean value of the multiplier output is zero when the two signals are in quadrature. In
this condition, the ripple in the error signal is also quite small.
Thus, the voltage at pin 5 is essentially zero, and the frequency
is determined primarily by the current in the timing resistor,
controlled either manually or by a control voltage.
.......
~=TE
~r..gt~--t--"-!!lh L
OTO·tO'll
i1YPIt
~ '----I]iJ-..J
Figure 12. Linear Phase-Locked Loop
Noise on the input signal affects the loop operation only
slightly; it appears as noise in the timing current, but this
is averaged out by the timing capacitor. On the other hand,
if the input frequency changes there is a net error voltage
at pin 5 which acts to bring the oscillator back into quadrature. Thus, the output at pin 14 is a noise-free square-wave
having exactly the same frequency as the input signal. The
effectiveness of this circuit can be judged from Figure 13
which shows the response to an input of 1V rms 1kHz sinusoid plus 1V rms Gaussian noise. The positive supply to the
AD537 is reduced by about 4V in order to keep the voltages
at pins 11 and 12 within the common-mode range of the
AD534.
Since this is also a first-order loop the circuit possesses a very
wide capture range. However, even better noise-integrating
properties can be achieved by adding a filter between the
multiplier output and the VCO input. Details of suitable
filter characteristics can be found in the standard texts on
the subject.
4-12 VIF& FNCONVERTERS
TRANSDUCER INTERFACE
. The AD537 was specifically designed to accept a broad range
of input signals, particularly small voltage signals, which may
be converted directly (uniike many V-F converters which require signal pre-conditioning). The 1.00V stable reference output is also useful in interfacing situations, and the high input
resistance allows non-loading interfacing from a source of
varying resistance, such as the slider of a potentiometer.
THERMOCOUPLE INPUT
The output of a Chromel-Constantan (Type E) thermocouple,
using a reference junction at OoC, varies from 0 to S3.14mV
over the temperature range 0 to +7000 C with a slope of
80.678~V/degree over most of its range and some nonlinearity
over the range 0 to +2000 C. For this example, we assume that
it is desired to indicate temperature in Degrees Celsius using a
counter/display with a lOOms gate width. Thus, the V-F convertermustdeliver an output of 7kHz for an input of 53.14mV.
If very precise operation down to 0° C is imperative, some sort
of linearizing is necessary (see, for example, Analog Devices'
Nonlinear Circuits Handbook, pp92-97) but in many cases
operation is only needed over part of the range.
The circuit shown in Figure 14 provides good accuracy from
+3OOoC to +700°C. The extrapolation of the temperaturevoltage curve back to OoC shows that an offset of -3.34mV is
required to fit the curve most exactly. This small amount of
voltage can be introduced without an additional calibration
step using the +l.OOV output of the ADS37. To adjust the
scale, the thermocouple should be raised to a known reference temperature near 500u C and the frequency adjusted to
value usin~ Rl. Theoerror should be within iO.2% over the
range 400 C to 700 C.
10Hzfc
Figure 14. Thermocouple Interface with First-Order
Linearization
r.ANALOG
WDEVICES
FEATURES
V/F Conversion to 1MHz
Reliable Monolithic Construction
Very Low Nonlinearity
0.002% typ at 10kHz
0.005% typ at 100kHz
0.07% typ at 1 MHz
Input Offset Trimmable to Zero
CMOS or TIL Compatible
Unipolar, Bipolar, or Differential V/F
V/F or FN Conversion
Available in Surface Mount
Voltage-to-Frequency and
Frequency-to-Voltage Converter
AD650
AD6S0 PIN CONFIGURATION
BIPOLAR
OFFSET
CURRENT
ONE
SHOT
CAPACITOR
PRODUCT DESCRIPTION
The AD650 VIPN (voltage-to-frequency or frequency-to-voltage
converter) provides a combination of high frequency operation
and low nonlinearity previously unavailable in monolithic form.
The inherent monotonicity of the VIP transfer function makes
the AD650 useful as a high-resolution analog-to-digital converter.
A flexible input configuration allows a wide variety of input
voltage and current formats to be used, and an open-collector
output with separate digital ground allows simple interfacing to
either stsndard logic families or opto-couplers.
The linearity error of the AD650 is typically 20ppm (0.002% of
full scale) and 50ppm (0.005%) maximum at 10kHz full scale.
This corresponds to approximately 14-bit linearity in an analog-todigital converter circuit. Higher full-scale frequencies or longer
count intervals can be used for higher resolution conversions.
The AD650 has a useful dynamic range of six decades allowing
extremely high resolution measurements. Even at IMHz full
scale, linearity is guaranteed less than l000ppm (0.1%) on the
AD650KN, KP, BD and SD grades.
In addition to analog-to-digital conversion, the AD650 can be
used in isolated analog signal transmission applications, phasedlocked-loop circuits, and precision stepper motor speed controllers.
In the FN mode, the AD650 can be used in precision tachometer
and FM demodulator circuits.
The input signal range and full-scale output frequency are userprogrammable with two external capacitors and one resistor.
Input offset voltage can be trimmed to zero with an external
potentiometer.
I
4
11
~~~LOG
COMPARATOR
INPUT
The AD650JN and AD650KN are offered in a plastic 14-pin
DIP package. The AD650JP and AD650KP are avai1able in a
20-pin plastic leaded chip carrier (PLeC). Both plastic packaged
versions of the AD650 are specified for the commerical (0 to
+ 70"C) temperature range. For industrial temperature range
( - 25°C to + 85"C) applications, the AD650AD and AD650BD
are offered in a ceramic package. The AD650SD is specified for
the full - 55"C to + 125"C extended temperature range.
PRODUCT HIGHLIGHTS
1. In addition to very high linearity, the AD650 can operate at
full scale output frequency up to IMHz. The combination of
these two features makes the AD650 an inexpensive solution
for applications requiring high resolution monotonic AID
conversion.
2. The AD650 has a very versatile architecture that can be
configured to accommodate bipolar, unipolar, or differential
input voltages, or unipolar input currents.
3. TTL or CMOS compatibility is achieved using an open collector
frequency output. The pullup resistor can be connected to
voltages up to + 30V, or + l5V or + 5V for conventional
CMOS or TTL logic levels.
4. The same components used for V/F conversion can also be
used for FN conversion by adding a simple logic biasing
network and reconfiguring the AD650.
5. The AD650 provides separate analog and digital grounds.
This feature allows prevention of ground loops in real-world
applications.
VIF & FN CONVERTERS 4-13
II
SPECIFICATIONS
(@
+2ft with Vs=:l:l5Y unless aIIIeIwise noIIId)
AD6SOJ/AD650A
MiD
Model
Tn>
AD650KlAD6SOB
Mal:
Tn>
MiD
AD6SOS
Mal:
Tn>
MiD
Mal:
Vaits
I
0.005
0.02
0.05
0.1
+0.002
MHz
%
%
%
%
%
%
%ofFSRN
±75
±ISO
ppmfC
ppmfC
DYNAMIC~ORMANCE
Full Scale Frequency Rang<
Nonlinearity' t;..,. ~ 10kHz
100kHz
500kHz
IMHz
Full Scale Calibration Error', 100kHz
IMHz
vs.Supply'
vs. Temperature
0.002
0.005
0.02
0.1
±5
I
0.005
0.02
0.05
0.002
0.005
0.02
0.05
±5
±10
-0.002
I
0.005
0.02
0.05
0.1
0.002
0.005
0.02
0.05
±5
±5
±10
+0.002
-0.002
+0.002
-0.002
A, B, and S Grades
BIPOLAR OFFSET CURRENT
Activated by 1.24k.O between pins 4 aod 5
DYNAMIC RESPONSE
Maximum Settling Time for Full Scale
Steploput
Overload Recovery Time
Step Input
ANALOG INPUT AMPLIFIER (V/F Conversion)
Curren! Input Rang< (Figure I)
Voltage loput Range (Figure 5)
Differential Impedance
Conunon Mode Impedance
±75
±7S
±150
.tlOkHz
at 100kHz
J and K Grades
at 10kHz
.. 100kHz
±150
0.45
O.s
ppmfC
ppmfC
±75
±75
±ISO
±150
O.sS
0.45
O.s
O.sS
0.45
O.s
0.s5
1 PulseofNew Frequency Plus 1....8
1 Pulse of New Frequency Plus 1....8
I PulseofNew Frequency Plus 1....8
I Pulse of New Frequency Plus I,,,
I PuiseofNew FrequencyPius I,,,
I Pulse of New Frequency Plus I"s
+0.6
0
0
-10
+0.6
0
0
-10
+0.6
0
mA
V
100
",20
nA
nA
"'4
±30
mV
"VI'C
C
+1
+Vs
(0.3 x los)
V
V
0.4
100
+36
V
+10
100
V
mA
pF
±9
"'18
8
V
rnA
-55
+125
"C
"C
-65
+150
0
-10
lMOIIIOpF
lOOOMOlllOpF
2MOIIIOpF
lOOOMOlllOpF
2MflillOpF
lOOOMOIllOpF
mA
Input Bias Current
40
±8
Noninverting loput
Inverting Input
Input Offset Voltage
(Ttinunable to Zero)
",4
Safe Input Voltage
Logic II I'" Level
Pulse Width Rang<4
AMPLIFIEROUTPUT(FN Conversion)
Voltage Range (I 5000 min load resistance)
Source Current (7S00 max load resistance)
TEMPERATURE RANGE
Rated Performance-N Package
DPatkage
Storage
-NPatkage
DPatkage
",20
"'4
±30
±Vs
-I
+Vs
(0.3 x los)
-Vs
0
0.1
250
0
0.4
100
+36
0
0.4
100
+36
0
+10
0
+10
10
10
±9
"'18
8
±9
",18
8
0
-25
-25
-65
+70
+85
+85
+ ISO
0
-25
-25
-65
+70
+85
+85
+150
AD650JP
AD650)N
AD650AD
0
0
10
100
100
PACKAGE OPTIONS'
PLCC (P·20A)
P1••tic DlP (N·14)
Ceramic DIP(D·14)
-Vs
0
0.1
250
250
Capacitive Load (Without Oscillation)
POWER SUPPLY
Voltage, Rated Performance
Quiescent Current
40
±8
100
±Vs
-I
+Vs
(0.3xtos)
-Vs
0
0.1
Input Impedance
OPEN COLLECTOR OUTPUT (VIF Conversion)
Output Voltage in Logic "0"
ISINK ::s SmA, T min to T max
Output Leakage Current in Logic "1"
Voltage Range'
40
±8
±30
:tVs
vs. Temperature (Tmin to T max)
COMPARATOR (FN Conversion)
Logic "0" Level
100
±20
4-14 VIF & FN CONVERTERS
nA
V
'C
AD650KP
AD650KN
AD650BD
NOTES
'Nonlinearity is defmed as deviation from. a straight line from zero
to full scale, expressed as a fraction of full scale.
2pull scale calibration error adjustable to zero.
3Measured atfull scale output frequency of 10kHz.
4Refer to FN conversion section of the teXt.
'Referred to digital ground.
6-See Section 14 for package outline information.
"s
kG
Specifications subject to change without notice.
Specifications shown in boldface are tested. on all production units at fmal e1ectrj.
cal test. Results from those tests are used to calculate outgoing quality leveJs. All
min and max SpeciflCatiOns are guaranteed, although only those shown in
boldface are tested on aU production units.
AD650SD
"C
Unipolar Operation - AD650
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
Gain
Tempeo
Specified
100kHz
IMHz
Linearity
Temperature
Range "C
Package
150typ
150typ
150typ
150typ
150max
150max
150max
O.I%typ
O.I%max
O.I%typ
O.I%max
O.I%typ
O. 1% max
O.I%max
oto + 70
oto + 70
Part
Number
ppmI"C
AD650JN
AD650KN
AD650JP
AD650KP
AD650AD
AD650BD
AD650SD
Oto +70
Oto +70
-25to +85
- 25 to + 85
- 55 to + 125
Plastic DIP
Plastic DIP
PLCC
PLCC
Ceramic
Ceramic
Ceramic
CIRCUIT OPERATION
UNIPOLAR CONFIGURATION
The AD650 is a charge balance voltage-to-frequency converter.
In the connection diagram shown in Figure 1, or the block
diagram of Figure 2a, the input signal is conve~ted into an
equivalent current by the input resistance R/N. This current is
exactly balanced by an internal feedback current delivered in
short, timed bursts from the switched ImA internal current
. . . . . . . 36V
Total Supply Voltage + V5 to - V5
Storage Temperature Ceramic . . . . .
- 55°C to + 165°C
- 2SoC to + 12SoC
Plastic
Differential Input Voltage (Pins 2 & 3)
±IOV
Maximum Input Voltage . . . . . . .
. ±Vs
Open Collector Output Voltage Above Digital GND . 36V
Current
SOmA
Indefinite
Amplifier Short Ckt to Ground . .
Comparator Input Voltage (Pin 9) .
. .. ±Vs
source. These bursts of current may be thought of as precisely
defined packets of charge. The required number of charge packets,
each producing one pulse of the output transistor, depends
upon the amplitude of the input signal. Since the number of
charge packets delivered per unit time is dependent on the
input signal amplitude, a linear voltage-to-frequency transformation will be accomplished. The frequency output is furnished
via an open collector transistor.
R,.
}-t--"~-----'''''''-+--1
-v,
Figure 2b. Reset Mode
-v,
Figure 2c. Integrate Mode
One Shot Timing
A key part of the preceding analysis is the one shot time period
that was given in equation (I). This time period can be broken
down into approximately 300ns of propagation delay, and a
second time segment dependent linearly on timing capacitor
Cos. When the one shot is triggered, a voltage switch that holds
pin 6 at analog ground is opened allowing that voltage to change.
An internal O.SmA current source connected to pin 6 then draws
its current out of Cos, causing the voltage at pin 6 to decrease
linearly. At approximately -3.4V, the one shot resets itself,
thereby ending the timed period aod starting the VIF conversion
cycle over again. The total one shot time period cao be written
mathematically as:
~VCos
tos
IDISCHARGE + TGATEDELAY
(5)
substituting actual values quoted above,
tos
-3.4VxCos
9
-0.5 x lo-3A + 300 x 10-' sec
(6)
This simplifies into the timed period equation given above.
COMPONENT SELECTION
Figure 2d. Voltage Across C1NT
The positive input voltage develops a current (lIN = VINIRIN)
which charges the integrator capacitor CINT • As charge builds
up on C1NT, the output voltage of the integrator ramps downward
towards ground. When the integrator output voltage (pin 1)
crosses the comparator threshold ( - 0.6 volt) the comparator
triggers the one shot, whose time period, too is determined by
the one shot capacitor Cos.
4-16 VIF & FN CONVERTERS
Only four component values must be selected by the user. These
are input resistaoce R 1N, timing capacitor Cos, logic resistor R z,
aod integration capacitor C1NT• The first two determine the
input voltage aod full scale frequency, while the last two are
determined by other circuit considerations.
Of the four components to be selected, Rz is the easiest to defme.
As a pull up resistor, it should be chosen to limit the current
through the output transistor to SmA if a TTL maximum VOL
of O.4V is desired. For example, if a SV logic supply is used, Rz
should be no smaller thao SVtSmA or 6250. A larger value cao
be used if desired.
RIN aod Cos are the only two parameters available to set the full
scale frequency to accommodate the given signal range. The
Bipolar Operation - AD650
"swing" variable that is affected by the choice of RIN and Cos is
nonlinearity. The selection guide of Figure 3 shows this quite
graphically. In general, larger values of Cos and lower full scale
input currents (higher values of R IN) provide better linearity. In
Figure 3, the implications of four different choices of RIN are
shown. Although the selection guide is set up for a unipolar
configuration with a zero to lOY input signal range, the results
can be extended to other configurations and input signal ranges.
For a full scale frequency of 100kHz (corresponding to lOY
input), you can see that among the available choices, RIN =20k
and Cos = 620pF gives the lowest nonlinearity, 0.0038%. Also,
if you wish to use the highest frequency that will give the 20ppm
minimum nonlinearity, it is approximately 33kHz (40.2kfl and
lOOOpF).
When the proper value for C INT is used, the charge balance
architecture of the AD650 provides continuous integration of
the input signal, hence large amounts of noise and interference
can be rejected. If the output frequency is measured by counting
pulses during a constant gate period, the integration provides
infinite normal mode rejection for frequencies corresponding to
the gate period and its harmonics. However, if the integrator
stage becomes saturated by an excessively large noise pulse, the
continuous integration of the signal will be interrupted, allowing
the noise to appear at the output. If the approximate amount of
noise that will appear on CINT is known (VNOISE), the value of
CINT can be checked using the following inequality:
(8)
1MHz
:::-....
1 ..... 1"-
FULL SCALE
FREQUENCY
~I"-
100kHz
"
~
" "-
I
I
~
~
"-
10kHz
"
INPUT
~~SISTOR
~:}
~l2k
I
"
50
100kl
1000
100
Cos
Figure 3a. Full Scale Frequency vs. Cos
For example, consider an application calling for a maximum
frequency of 75kHz, a 0-1 volt signal range, and supply voltages
of only ± 9 volts. The component selection guide of Figure 3 is
used to select 2.0kfl for RIN and lOOOpF for Cos. This results
in a one shot time period of approximately 7f1s. Substituting
75kHz into equation 7 yields a value of 1300pF for CINT . When
the input signal is near zero, lmA flows through the integration
capacitor to the switched current sink during the reset phase,
causing the voltage across C'NT to increase by approximately 5.5
volts. Since the integrator output stage requires approximately 3
volts head room for proper operation, only 0.5 volt margin
remains for integrating extraneous noise on the signal line. A
negative noise pulse at this time might saturate the integrator,
causing an error in signal integration. Increasing CINT to 1500
or 2000pF will provide much more noise margin, thereby eliminating this potential trouble spot.
BIPOLAR V/F
Figure 4 shows how the internal bipolar current sink is used to
provide a half-scale offset for a ± 5V signal range, while providing
a 100kHz maximum output frequency. The nominally O.5mA
(± 10%) offset current sink is enabled when a 1.24kfl resistor is
connected between pins 4 and 5. Thus, with the grounded
lOkfl nominal resistance shown, a - 5V offset is developed at
pin 2. Since pin 3 must also be at -5V, the current through
RIN is lOV/40k!l= +0.25mA at VIN = +5V, and OmA at
VIN = -5V.
I INPUT
~ESIS~OR
1000ppm
i"---16.9k
r--
f---
TYPICAL
NONUNEARITY
-i
k
I ....
4O.y~
100ppm
r-- _lOOk
l'\.
I'"l\.
......
I
i
20ppm
...
""
I"""'--- ~ l"-.....;
~
Components are selected using the same guidelines outlined for
the unipolar configuration with one alteration. The voltage
~~
I
50
1000
100
ONE SHOT CAPACITOR ~
Cos IN PICOFARADS
Figure 3b. Typical Nonlinearity vs. Cos
~f--"'_~-"+15V
For input signal spans other than 10V, the.input resistance
must be scaled proportionately. For example, if 100kfl is called
out for a O-lOV span, 10k would be used with a O-lV span, or
200kfl with a ± lOY bipolar connection.
+5V
-15V
The last component to be selected is the integration capacitor
CINT . In almost all cases, the best value for CINT can be calculated
using the equation:
10·4FIsec
CINT=f--- (1000pF minimum)
MAX
(7)
~---4-O()f~,
Figure 4. Connections for ± 5V Bipolar VIF with 0 to 100kHz
TTL Output
VIF & FN CONVERTERS 4-17
II
across the total signal raugemust be equated to the maximum
input voltage in the unipolar configuration. In other words, the
value of the input resistor RJN is determined by the input voltage
spsn, not the maximum input voltage. A diode from pin I to
ground is also recommended. This is discussed further under
"Other Circuit Conditions".
r-~~~--------------oV~
.3
.,
i}--...-.....--o+15V
As in the unipolar circuit, RJN and Cos must have low temperature
coefficients to minimize the overall gain drift. The 1.24kO.
resistor used to activate the 0.5mA offset current should also
have a low temperature coefficient. The bipolar offset current
has a temperature coefficient of approximately - 200ppmI"C.
ANALOG
GROUND
-15Vo-.....- - {
UNIPOLAR VIF, NEGATIVE INPUT VOLTAGE
Figure 5 shows the connection diagram for V/F conversion of
negative input voltages. In this configuration full scale output
frequency occurs at negative full scale input, and zero output
frequency corresponds with zero input voltage.
A very high impedance signal source may be used since it only
drives the noninverting integrator input. Typical input impedance
at this terminal is lGO or higher. For V/F conversion of positive
input signals usir...g the connection diagr-.m of Figure 1, the
signal generator must be able to source the integration current
to drive the AD650. For the negative V/F conversion circuit of
Figure 5, the integration current is drawn from ground through
RI and R3, and the active input is high impedance.
i}--f-......-*---<>+15V
+V~OGIC
} -_ _ _..........
Figure 6. Connection Diagram for FN Conversion
spike that triggers the one shot on negative going edges. For
input signals with slower edges, a larger capacitor andlor resistor
may be used as long as the comparator is never exposed to a
voltage lower than - 0.6V for longer than the one shot time
period. If this happens, the one shot will trigger itself more
than once per cycle, creating discontinuities in the FIV transfer
function. An input pulse greater than lOOns but less than 0.3 x tos
is recommended (tos is dermed by equation I in the circuit
operation section, unipolar configuration).
HIGH FREQUENCY OPERATION
Proper RF techniques must be observed when operating the
AD650 at or near its maximum frequency of lMHz. Lead lengths
must be kept as short as possible, especially on the one shot and
integration capacitors, and at the integrator summing junction.
In addition, at maximum output frequencies above 500kHz, a
3.6kO pulldown resistor from pin I to - Vs is required (see
Figure 7). The additional current drawn through the pulldown
resistor reduces the op amp's output impedance and improves
its transient response.
F~,
GAIN
Figure 5. Connection Diagram for VIF Conversion, Negative
Input Voltage
Circuit operation for negative input voltages is very similar to
positive input unipolar conversion described in a previous section.
For best operating results use component equations listed in
that section.
FN CONVERSION
The AD650 also makes a very linear frequency-to-voltage converter. Figure 6 shows the connection diagram for FIV conversion
with TTL input logic levels. Each time the input signal crosses
the comparator threshhold going negative, the one shot is activated
and switches lmA into the integrator input for a measured. time
period (determined by Cos). As the frequency increases, the
amount of charge injected into the integration capacitor increases
proportionately. The voltage across the integration capacitor is
stabilized when the leakage current through Rl and R3 equals
the average current being switched into the integrator. The net
result of these two effects is an average output voltage which is
proportional to the input frequency. Optimum performance can
be obtained by selecting components using the same guidelines
and equations listed in the VIF conversion section.
The circuit of Figure 6 can be biased to accommodate almost
any input signal waveform. With a TTL input, the lOOOpF
coupling capacitor and 2.2kO resistor creates a clean negative
4--18 VlF & FN CONVERTERS
ADJUST
Ski}
VON o-~
+-+---"'f'. }--h---+
14.3kU
___
---<.......,
(12)___
+ 15V
OTO 10V
.-6~---:::1..:~~':
PlANE
-15V
Figure 7. 1MHz VIF Connection Diagram
DECOUPLING AND GROUNDING
It is good engineering practice to use bypass capacitors on the
supply-voltage pins and to insert small-valued resistors (10 to
1000) in the supply lines to provide a measure of decoupling
between the various circuits in a system. Ceramic capacitors of
O.lIJ.F to 1.0IJ.F should be applied between the supply-voltage
pins and analog signal ground for proper bypassing on the
AD650.
In addition, a larger board level decoupling capacitor of IIJ.F to
10IJ.F should be located relatively close to the AD650 on each
power supply line. Such precautions are imperative in high
resolution data acquisition applications where one expects to
Circuit Considerations - AD650
exploit the full linearity and dynamic range of the AD6S0. Although
some types of circuits may operate satisfactorily with power
supply decoupling at only one location on each circuit board,
such practice is strongly discouraged in high accuracy analog
design.
Separate digital and analog grounds are provided on the AD6S0.
The emitter of the open collector frequency output transistor is
the only node returned to the digital ground. All other signals
are referred to analog ground. The purpose of the two separate
grounds is to allow isolation between the high precision analog
signals and the digital section of the circuitry. As much as several
hundred millivolts of noise can be tolerated on the digital ground
without affecting the accuracy of the VFC. Such ground noise is
inevitable when switching the large currents associated with the
frequency output signal.
At IMHz full scale, it is necessary to use a pull-up resistor of
about soon in order to get the rise time fast enough to provide
well defined output pulses. This means that from a 5 volt logic
supply, for example, the open collector output will draw IOmA.
This much current being switched will surely cause ringing on
long ground runs due to the self inductance of the wires. For
instance, *20 gauge wire has an inductance of about 20nH per
inch; a current of 10mA being switched in SOns at the end of 12
inches of 20 gauge wire will produce a voltage spike of sOmV.
The separate digital ground of the AD6S0 will easily handle
these types of switching transients.
A problem will remain from interference caused by radiation of
electro-magnetic energy from these fast transients. Typically, a
voltage spike is produced by inductive switching transients;
these spikes can capacitively couple into other sections of the
circuit. Another problem is ringing of ground lines and power
supply lines due to the distributed capacitance and inductance
of the wires. Such ringing can also couple interference into
sensitive analog circuits. The best solution to these problems is
proper bypassing of the logic supply at the AD6S0 package. A
1fLF to 10fLF tantalum capacitor should be connected directly to
the supply side of the pull-up resistor and to the digital ground
"" pin 10. The pull-up resistor should be connected directly to
the frequency output - pin 8. The lead lengths on the bypass
capacitor and the pull up resistor should be as shon as possible.
The capacitor will supply (or absorb) the current transients, and
large ac signals will flow in a physically small loop through the
capacitor, pull up resistor, and frequency output transistor. It is
imponant that the loop be physically small for two reasons:
first, there is less self-inductance if the wires are shon, and
second, the loop will not radiate RFI efficiently.
The digital ground (pin 10) should be separately connected to
the power supply ground. Note that the leads to the digital
power supply are only carrying dc current and cannot radiate
RFI. There may also be a de ground drop due to the difference
in currents returned on the analog and digital grounds. This
will not cause any problem. In fact, the AD6S0 will tolerate as
much as 0.25 volt de potential difference between the analog
and digital grounds. These features greatly ease power distribution
and ground management in large systems. Proper technique for
grounding requires separate digital and analog ground returns to
the power supply. Also, the signal ground must be referred
directly to analog ground (pin 11) at the package. All of the
signal grounds should be tied directly to pin 11, especially the
one-shot capacitor. More infonnation on proper grounding and
reduction of interference can be found in reference 1.
TEMPERATURE COEFFICIENTS
The drift specifications of the AD6S0 do not include temperature
effects of any of the supponing resistors or capacitors. The drift
of the input resistors Rl and R3 and the timing capacitor Cos
directly affect the overall temperature stability. In the application
of Figure 2, a 10ppmFC input resistor used with a lOOppmI"C
capacitor may result in a maximum overall circuit gain drift of:
150ppm1"C (AD650A)+ lOOppmI"C (Cos)+IOppmI"C (R'N)= 26OppmI"C
In bipolar configuration, the drift of the 1.24kO resistor used to
activate the internal bipolar offset current source will directly
affect the value of this current. This resistor should be matched
to the resistor connected to the op amp noninverting input (pin
2), see Figure 4. That is, the temperature coefficients of these
two resistors should be equal. If this is the case, then the effects
of the temperature coefficients of the resistors cancel each other,
and the drift of the offset voltage developed at the op amp noninverting input will be determined solely by the AD6S0. Under
these conditions the TC of the bipolar offset voltage is typically
- 200ppmJ"C and is a maximum of - 300ppmJ"C. The offset
voltage always decreases in magnitude as temperature is
increased.
Other circuit components do not directly influence the accuracy
of the VFC over temperature changes as long as their actual
values are not so different from the nominal value as to preclude
operation. This includes the integration capacitor, CINT• A
change in the capacitance value of CINT simply results in a
different rate of voltage change across the capacitor. During the
Integration Phase (refer to Figure 2), the rate of voltage change
across C1NT has the opposite effect that it does during the Reset
Phase. The result is that the conversion accuracy is unchanged
by either drift or tolerance of CINT • The net effect of a change
in the integrator capacitor is simply to change the peak to peak
amplitude of the sawtooth waveform at the output of the
integrator.
..
,
-50
~,
-100
g
-200
;;
e
-300
TEMPERATURE - "C
-25
0
10kHz
Z
-400
Figure 8. Gain TC vs. Temperature
The gain temperature coefficient of the AD6S0 is not a constant
value. Rather the gain TC is a function of both the full scale
frequency and the ambient temperature. At a low full scale
frequency, the gain TC is determined primarily by the stability
of the internal reference-a buried zener reference. This low
speed gain TC can be quite good; at 10kHz full scale, the gain
TC near 25°C is typically 0 ± SOppmFC. Although the gain TC
changes with ambient temperature (tending to be more positive
'''Noise Reduction Techniques in Electronic Systems", by H. W. OTT,
Gobn Wiley, 1976).
VIF & FN CONVERTERS 4-19
II
at higher temperatures), the drift remains within a ± 75ppm/oC
window over the entire military temperature range. At full scale
frequencies higher than 10kHz dynamic errors become much
more important than the static drift of the dc reference. At a
full scale frequency of 100kHz and above, these timing errors
dominate the gain TC. For example, at 100kHz full scale frequency
(RIN = 40k and Cos = 330pF) the gain TC near room temperature
is typically - 80 ± 5Oppml"C, but at an ambient temperature
near + 125°C, the gain TC tends to be more positive and is
typically + 15 ± 50ppml"C. This information is presented in a
graphical form in Figure 8. The gain TC always tends to become
more positive at higher temperatures. Therefore it is possible to
adjust the gain TC of the AD650 by using a one-shot capacitor
with an appropriate TC to cancel the drift of the circuit. For
example, consider the 100kHz full scale frequency. An average
drift of -100ppm1"C means that as temperature is increased,
the circuit will produce a lower frequency in reponse to a given
input voltage. This means that the one-shot capacitor must
decrease in value as temperature increases in order to compensate
the gain TC of the AD650; that is, the capacitor must have a
TC of -100ppmI"C. Now consider the IMHz full scale frequency.
It is not possible to achieve very much improvement in perforIl"'.Jlncc
unless the expected ambient temperature range is known. For
example, in a constant low temperature application such as
gathering data in an Arctic climate (approximately - 20°C), a
Cos with a drift of - 31 Opprnl°C is called for in order to compensate
the gain drift of the AD650. However, if that circuit should see
an ambient temperature of + 75°C, the Cos cap would change
the gain TC from approximately Oppm to +3IOppml"C.
The temperature effects of the components described above are
the same when the AD650 is configured for negative or bipolar
input voltages, and for FN conversion as well.
NONLINEARITY SPECIFICATION
The linearity error of the AD650 is specified by the end point
method. That is, the error is expressed in terms of the deviation
from the ideal voltage to frequency transfer relation after calibrating
the converter at full scale and "zero". The nonlinearity will vary
with the choice of one-shot capacitor and input resistor (see
Figure 3). Verification of the linearity specification requires the
availability of a switchable voltage source (or a DAC) having a
linearity error below 20ppm, and the use of very long measurement
intervals to minimize count uncertainties. Every AD650 is automatically tested for linearity, and it will not usually be necessary
to perform this verification, which is both tedious and time
consuming. If it is required to perform a nonlinearity test either
as part of an incoming quality screening or as a fmal product
evaluation, an automated "bench-top" tester would prove useful.
Such a system based on the Analog Devices' L TS-2010 is described
in Reference 2.
The voltage-to-frequency transfer relation is shown in Figure 9
with the nonlinearity exaggerated for clarity. The first step in
determining nonlinearity is to connect the end points of the
operating range (typically at IOmVand lOY) with a straight
line. This straight line is then the ideal relationship which is
desired from the circuit. The second step is to find the difference
between this line and the actual response of the circuit at a few
points between the end points - typically ten intermediate points
will suffice. The difference between the actual and the ideal
response is a frequency error measured in hertz. Finally, these
frequency errors are normalized to the full scale frequency and
expressed either as parts per million of full-scale (ppm) or parts
'OOk
:I!
I
I
I
'DO
10mV
'OV
lNPUT VOLTAGE·
Figure 9a. Exaggerated Nonlinearity at 100kHz Full Scale
~ 1MI
>
ACTUAL VOLTAGE TO FREQUENCY
TRANSFER RELATION
~
~
IE
I
10mV
INPUT VOLTAGE
'OV
Figure 9b. Exaggerated Nonlinearity at 1MHz Full Scale
per hundred of full scale (%). For example, on a 100kHz full
scale, if the maximum frequency error is 5Hz, the nonlinearity
would be specified as 50ppm or 0.005%. Typically on the 100kHz
scale, the nonlinearity is positive and the maximum value occurs
at about midscale (Figure 9a). At higher full scale frequencies,
(500kHz to IMHz), the nonlinearity becomes "S" shaped and
the maximum value may be either positive or negative. Typically,
on the IMHz scale (RIN = 16.9k, Cos = SlpF) the nonlinearity is
positive below about 2/3 scale and is negative above this point.
This is shown graphically in Figure 9b.
PSRR
The power supply rejection ratio is a specification of the change
in gain of the AD650 as the power supply voltage is changed.
The PSRR is expressed in units of parts-per-million change of
the gain per percent change of the power supply - pprnl%. For
example, consider a VFC with a 10 volt input applied and an
output frequency of exactly 100kHz when the power supply
potential is ± 15 volts. Changing the power supply to:!: 12.5
volts is a 5 volt change out of 30 volts, or 16.7%. If the output
'000
'0
'OOk
'Ok
'M
FULL SCALE FREQUENCY - Hz
2"V·F Converters Demand Accurate Linearity Testing", by L. DeVito,
(Electronic Design, March 4, 1982)
4-20 VlF & FN CONVERTERS
Figure 10. PSRR
VS.
Full Scale Frequency
Applications - AD650
frequency changes to 99.9kHz, the gain has changed 0.1% or
lOOOppm. The PSRR is lOOOppm divided by 16.7% which
equals 6Oppml%.
The PSRR of the AD6S0 is a function of the full scale operating
frequency. At low full scale frequencies the PSRR is det~ed
by the stability of the reference circuits in the device and can be
very good. At higher frequencies there are dynamic errors which
become more important than the static reference signals, and
consequently the PSRR is not quite as good. The values of
PSRR are typically 0 ±2Oppml% at 10kHz full scale frequency
(RIN = 4Ok, Cos = 3300pF). At 100kHz (R1N=40k, Cos = 33OpF)
the PSRR is typically +80 ±4Oppml%, and at IMHz
(RIN =16.9kO, Cos=5IpF) the PSRR is +350 ±SOppm/%.
This information is summarized graphically in Figure 10.
OTHER CIRCUIT CONSIDERATIONS
The input amplifier connected to pins I, 2 and 3 is not a standard
operational amplifier. Rather, the design has been optimized for
simplicity and high speed. The single largest difference between
this amplifler and a normal op amp is the lack of an integrator
(or level shift) stage. Consequently the voltage on the output
(pin I) must always be more positive than 2 volts below the
inputs (pins 2 and 3). For example, in the F to V conversion
mode, see Figure 6, the noninverting input of the op amp (pin
2) is grounded, which means that the output (pin I) will not be
able to go below - 2 volts. Normal operation of the circuit as
shown in the figure will never call for a negative voltage at the
output but one may imagine an arrangement calling for a bipolar
output voltage (say ± 10 volts) by connecting an extra resistor
from pin 3 to a positive voltage. This will not work.
Care should be taken under conditions where a high positive
input voltage exists at or before power up. These situations can
cause a latch up at the integrator output (pin I). This is a nondestructive latch and, as such, normal operation can be restored
by cycling the power supply. Latch up can be prevented by
connecting two diodes (e.g., IN914 or IN4148) as shown in
Figure 4 thereby preventing pin I from swinging below pin 2.
A second major difference is that the output will only sink lmA
to the negative supply. There is no pulldown stage at the output
other than the lmA current source used for the V to F conversion.
The op amp will source a great deal of current from the positive
supply, and it is internally protected by current limiting. The
output of the op amp may be driven to within 3 volts of the
positive supply when it is not sourcing external current. When
sourcing 10mA the output voltage may be driven to within 6
volts of the positive supply.
A third difference between this op amp and a normal device is
that the inverting input, pin 3, is bias current compensated and
the noninverting input is not bias current compensated. The
bias current at the inverting input is nominally zero, but may be
as much as 20nA in either direction. The noninverting input
typically has a bias current of 40nA that always flows into the
node (an npn input transistor). Therefore, it is not possible to
match input voltage drops due to bias currents by matching
input resistors.
The op amp has provisions for trimming the input offset voltage.
A potentiometer of 20kO is connected to pins 13 and 14 and the
wiper is connected to the positive supply through a 2S0kO resistor.
A potential of about 0.6 volt is established across the 250kO
resistor, and the 3jJA current is injected into the null pins. It is
also possible to null the op amp offset voltage by using only one
of the null pins and use a bipolar current either into or out of
the null pin. The amount of current required will be very small
- typically less than 3jJA. This technique is shown in the applications section of this data sheet: the auto-zero circuit uses this
technique.
The bipolar offset current is activated by connecting a 1.24kO
resistor between pin 4 and the negative supply. The resultant
current delivered to the op amp noninverting input is nominally
O.SmA and has a tolerance of ± 10%. This current is then used
to provide an offset voltage when pin 2 is tied to ground through
a resistor. The O.5mA which appears at pin 2 is also flowing
through the 1.24kO resistor and this current may be measured
by observing the voltage across the 1.24kO resistor. An external
resistor is used to activate the bipolar offset current source to
provide the lowest tolerance and temperature drift of the resultant
offset voltage. It is possible to use other values of resistance
between pin 4 and - V s to obtain a bipolar offset current different
than O.SmA. Figure 11 is a graph of the relationship between
the bipolar offset current and the value of the resistor used to
activate the source.
VCM IS THE COMMON MODE INPUT_-I-15V to -5V WITH RESPECT TO ANALOG GROUND
VIN IS THE SIGNAL INPUT __ 5V WITH RESPECT TO VCM
=
~;::::=====:::;-_¥"~VZENER
IN!iZ40
,."
FREQUENCY
o TO~':'~!
_-+..................--<>
200
Figure 12. AD650 Differential Input
500
1000
1500
2000"
2500
3000
EXTERNAL RESISTOR
.3500
4000
Figure ". Bipolar Offset Current vs. External Resistor
VIF & FN CONVERTERS 4-21
II
APPUCATIONS
DIFFERENTIAL VOLTAGE-TO-FREQUENCY
CONVERSION
The circuit of Figure 12 accepts a true floating differential input
signal. The common mode input, VCM, may be in the range
+ IS to - 5 volts with respect to analog ground. The signal
input, VIN, may be ± 5 volts with respect to the common mode
input. Both inputs are low impedance: the source which drives
the common mode input muat supply the 0.5mA drawn by the
bipolar offset current source and the source which drives the
signal input must slipply the integration current.
If less common mode voltage range is required, a lower voltage
zener may be used. For example, if a 5 volt zener is used, the
VCM input may be in the range + 10 to - 5 volt. If the zener is
not used at all, the common mode range will be ± 5 volts with
repect to analog ground. If no zener is used, the 10k pulldown
resistor is not needed and the integrator output (pin I) is connected
directly to the comparator input (pin 9).
AUTO ZERO CIltCUIT
In order to exploit the full dynamic range of the AD650 VFC,
very small input voltages will need to be converted. For example,
a six decade dynamic range based on a full scale of 10 volts will
require accurate measurement of signals down to 10j1.V. In these
situations a well-controlled input offset voltage is imperative. A
constant offset voltage will not affect dynamic range but simply
shift all of the frequency readings by a few hertz. However, if
the offset should change, then it will not be possible to distinguish
between a small change in a small input voltage and a drift of
the offset voltage. Hence, the useable dynamic range is less.
The circuit shown in Figure 13 provides automatic adjustment
of the op amp offset voltage. The circuit uses an ADS82 sample
and hold amplifier to control the offset and the input voltage to
the VFC is switched between ground and the signal to be measured
via an AD7512DI analog switch. The offset of the AD650 is
adjusted by injecting a current into or drawing a current out of
pin 13. Note that only one of the offset null pins is used. During
the "VFC Norm" mode, the SHA is in the hold mode and the
hold capacitor is very large, O.Ij1.F, to hold the AD6S0 offset
constant for a long period of time.
connected to ground during the auto zero mode, the input Current
which can flow is determined by the offset voltage of the AD6SO
op amp. Since the output of the integrator stage is forced to
ground it is knnwn that the voltage is not changing (it is equal
to ground potential). Hence if the output of the integrator is
constant, its input current must be zero, so the offset voltage
has been forced to be zero. Note that the output of the DUT
could have been forced to any convenient voltage other than
ground. All that is required is that the output voltage be known
to be constant. Note also that the effect of the bias current at
the inverting input of the AD6S0 op amp is also nulled in thiS
circuit. The l000pF capacitor shunting the 200kO resistor is
compensation for the two amplifier servo loop. Two integrators
in a loop requires a single zero for compensation. Note that the
3.6kO resistor from pin 1 of the AD6S0 to the negative supply
is not part of the auto-zero circuit, but rather it is required for
VFC operation at IMHz.
PHASE LOCKED LOOP FIV CONVERSION
Although the FN conversion technique shown in Figure 6 is
quite accurate and uses only a few extra components, it is very
limited in terms of signal frequency response and carrier feedthrough. If the carrier (or input) frequency changes instantaneously, the output cannot change very rapidly due to the integrator
time constant formed by CINT and R IN . While it is possible to
decrease the integrator time constant to provide faster settling of
the F to V output voltage, the carrier feedthrough will then be
larger. For signal frequency response in excess of 2kHz, a phase
locked FN conversion technique such as the one shown in
Figure 14 is recommended.
Figure 14. Phase Locked Loop FN Conversion
In a phase locked loop circuit, the oscillator is driven to a frequency
and phase equal to an input reference signal. In applications
such as a synthesizer, the oscillator output frequency is first
processed through a programmable "divide by N" before being
applied to the phase detector as feedback. Here the oscillator
frequency is forced to be C =5k)
COMPARATOR
Input Bias Current
Common-Mode Voltage
CLOCK INPUT
Maximum Frequency
Threshold Voltage (Referred to Pin 12)
Tmin-Tmax
Input Current
(- VS'
<1>2
<1>3
_ _ _i._I--c1>4
MULTIPLEX
OUTPUT
MULTIPLEX INPUT
ONE SHOT
RECONSTRUCTED
CLOCK
<1>'
(PHASE LOCKED TO
RECONSTRUCTED
CLOCK)
DATA
Figure 25. Demultiplexer Waveforms
Figure 24. Multiplexer Waveforms
VIF & FN CONVERTERS 4-37
......PUT
+0•
1N4148
••
-
..
i2. il.... ARE PINS 15, 7, 8 01 TIMIINMA FROM DEMUX fIGURE 23
Figure 26. Demultiplexer Frequency-to-Voltage Conversion
Analog Signal Reconstruction
If it is desired to reconstruct the analog voltages from the multiplex
signal, then three more AD652 SVFC devices are used as frequency-to-voltage convert.ers, as shown in Figure 26. The comparator inputs of all the devices are strapped together, and the
" +" inputs are held at a 1.2 volt TTL threshold, while the
" -" inputs are driven by the multiplex input. The three clock
inputs are driven by the Cj) outputs of the clock chip. Remember
that data at the comparator input of the SVFC is loaded on the
falling edge of the clock signal and shifted out on the next rising
edge. Note that the frequency signals for each data channel are
available at the frequency output pin of each FVC.
completely isolated analog measurement system. The power for
the AD652 SVFC is provided by a chopper and a transformer,
and is regulated to ± 15 volts.
Both the chopper frequency and the AD652 clock frequency are
125kHz, with the clock signal being relayed to the SVFC through
the transformer. The frequency outpUt signal is relayed through
an opto-isolator and latched into a D-flop. The chopper frequency
is generated from an AD654 VFC and is frequency divided by
two to develop differential drive for the chopper transistors, and
to ensure an accurate 50 percent duty cycle. The pull-up resistors
on the D-flop outputs provide a well defmed high level voltage
to the choppers to equalize the drive in each direction. The
10jJlI inductor in the + 5V lead of the transformer primary is
necessary to equalize any residual imbalance in the drive on
each half-cycle and thus prevent saturation of the core. The
capacitor across the primary resonates the system so that under
light loading conditions on the secondary the wave shape will be
ISOLATED FRONT END
In some applications it may be necessary to have complete galvanic
isolation between the analog signals being measured and the
digital portions of the circuit. The circuit shown in Figure 27
runs off a single 5 volt power supply and provides a self-contained,
CLOCK
FREQUENCY
~----~+-~
+5.
t--1::;:========~=i---:======1l'
__1-__
-r;-----~
l'
________________~FREQUENCV
24 TURNS
.t:::..;..:.____________________...... T50-3 MlCROMETALSt...:._...:.
.....
_~
: - - - - - - - - - - - - - - - - - - - 7 - - & - 5 - - 4 - - - - - - -1sc)LAlloN'aAiUaEii -
,.15
V'N
~o-------+--------------------------,
.
,
Figure 27. Isolated Synchronous VFC
4-38 VIF & FN CONVERTERS
r-- ___ ~~TPUT
AD652
sinusoidal and the clock frequency will be relayed to the SVFC.
To adjust the chopper frequency, disconnect any load on the
secondary and tune the AD654 for a minimum in the supply
current drawn from the 5 volt supply.
A-TO-D CONVERSION
In performing an A-tOoD conversion, the output pulses of a
VFC are counted for a fixed gate interval. To achieve maximum
performance with the AD652, the fixed gate interval should be
generated using a multiple of the SVFC clock input. Counting
in this manner will eliminate any errors due to the clock (whether
it be jitter, drift with time or temperature, etc.) since it is
the ratio of the clock and output frequencies that is being
measured.
The resolution of the A-tOoD conversion measurement is determined by the clock frequency and the gate time. If, for instance,
a resolution of 12 bits is desired and the clock frequency is
IMHz (resulting in an AD652 FS frequency of 500kHz) the
gate time will be:
( FS Freq)-l
N
=
8192
1 x 106 sec
=
(!
2
Clock Freq)-l
N
= 8.192ms
=(
variables are chosen such that the gate times are multiples of SO,
60 or 400Hz, normal-mode rejection (NMR) of those line frequencies will occur.
DELTA MODULATOR
The circuit of Figure 29 shows the AD652 configured as a delta
modulator. A reference voltage is applied to the input of the
integrator (pin 7), which sets the steady state output frequency
at one-half of the AD652 full-scale frequency (1/4 of the clock
frequency). As a 0 to 10V input signal is applied to the comparator
(pin IS), the output of the integrator attempts to track this
signal. For an input in an idling condition (dc) the output frequency
will be one-half full scale. For positive going signals the output
frequency will be between one-half full scale and full scale, and
for negative going signals the output frequency will be between
zero and one-half full scale. The output frequency will correspond
to the slope of the comparator input signal.
+15V
IMHZ)-l
2(4096)
Where N is the
total number of
codes for a given
resolution.
Figure 28 shows the AD652 SVFC as an A-tOoD converter in
block diagram form.
-1SV
O.0047,...F
v,.
Figure 29. Delta Modulator
Figure 28. Block Diagram ofSVFCA-to-D Converter
To provide the + 2N block a single chip counter such as the
4020B can be used. The 4020B is a 14-stage binary ripple counter
which has a clock and master reset for inputs, and buffered
outputs from the first stage and the last eleven stages. The
output of the first stage is fcLOCK + 21 = fcr.ocK/2, while the
output of the last stage is fCLOCK + 214 = fcr.ocK/16384. Hence
using this single chip counter as the + 2N block, B-bit resolution
can be achieved. Higher resolution can be achieved by cascading
D-type flip-flops or another 4020B with the counter.
Since the output frequency corresponds to the slope of the input
signal, the delta modulator acts as a differentiator. A delta modulator is thus a direct way of rmding the derivative of a signal.
This is useful in systems where, for example, a signal corresponding
to velocity exists and it is desired to determine acceleration.
Figure 30 is a scope photo showing a 20kHz, 0 to 10V sine
wave used as the input to the comparator and its ramp-wise
approximation at the integrator output. The clock frequency
used as 2MHz and the integrating capacitor was 360pF. Figure
31 shows the same input signal and its ramp-wise approximation,
along with the output frequency corresponding to the derivative
of the input signal. In this case the clock frequency was
850kHz.
Table I shows the relationship between clock frequency and
gate time for various degrees of resolution. Note that if the
Conversion
or
Resolution
N
Clock
Gate Time
TypLin Comments
12 Bits
12 Bits
12 Bits
4 Digits
14Bits
14 Bits
14 Bits
4 112 Digits
16Bits
16 Bits
4096
4096
4096
10000
16384
16384
16384
20000
65536
65536
81.92kHz
2M Hz
4MHz
200kHz
327.68kHz
1.966MHz
1.638MHz
400kHz
655.36kHz
4MHz
lOOms
4.096ms
2.048ms
lOOms
lOOms
16.66ms
20ms
lOOms
200ms
32.77ms
0.002%
0.01%
0.02%
0.002%
0.002%
0.01%
0.01%
0.002%
0.002%
0.02%
Table I.
zI
J,!
,Z
50, 60, 400Hz NMR
...... ' .. ! " ! ~....
,.. ~
~,
~
50, 60, 400Hz NMR
50, 60, 400Hz NMR
60HzNMR
50HzNMR
50, 60, 400Hz NMR
50,60, 400Hz NMR
nL ...
~
I,....
I~
"
2
."
....
~~
I'l~
".
Figure 30. Delta Modulator Input Signal and Ramp-Wise
Approximation
VIF & FN CONVERTERS 4-39
II
BRIDGE TRANSDUCER INTERFACE
The circuit of Figure 33 illustrates a simple interface between
the AD652 and a bridge-type transducer. The AD652 is an ideal
choice because its buffered 5 volt reference can be used as the
bridge excitation thereby ratiometrically eliminating the gain
drift related errors. This reference will provide a minimum of
lOrnA of external current, which is adequate for bridge resistance
of 600fl and above. If, for example, the bridge resistance is
120n or 350n, an external pull-up resistor (Rpu) is required
and can be calculated using the formula:
Rpu (max) =
RBRIDGE
The choice of an integrating capacitor is primarily dictated by
the input signal bandwidth. Figure 32 shows this relationship.
It should be noted that as the value of CINT is lowered, the
ramp size of the integrator approximation becomes larger. This
can be compensated for by increasing the clock frequency. The
effect of the clock frequency on the ramp size is demonstrated
in Figures 30 and 31.
......
10.000
+Vs -5V
~-IOmA
Figure 31. DBlts Modulstor Input Signsl. Rsmp-Wise
Approximstion snd Output Frequency
,
An instrumentation amplifier is used to condition the bridge
signal before presenting it to the SVFC. The AD625, with its
high CMRR, minimizes common-mode errors and also can be
set to arbitrary gains between I and 10,000 via three resistors,
simplifying the scaling for the AD652's calibrated 10 volt input
range. These resistors should be selected such that the following
equation holds:
10V =
VBRIDGE(~ +
where 10kn s RF S 20kn, and VBRIDGB is the maximum output
voltage of the bridge.
The bridge output may be unipolar, as is the case for most
pressure transducers, or it may be bipolar as in some strain
measurements. If the signal is unipolar, the reference input of
the AD625 (pin 7) is simply grounded. If the bridge has a bipolar
output, however, the AD652 reference can be tied to pin 7,
thereby converting a ± 5 volt signal (after gain) into a 0 to + 10
volt input for the SVFC.
~
i'.
t"\
os.
I 1000
j
"~
100
100
I)
'i'...
1000
10.000
INPUT SIGNAL BANDWIDTH - Hz
Figure 32. Msximum Integrsting Csp Vslue VB. Input Signsl
BBndwidth
+15V
NOTES
1. "" SHOULD BE BETWEEN
10k AND2Ok.
2. Rpu NEEDED IF RORIDGE
60011.
3. SI IN POSITION 1 FOR
UNIPOLAR SIGNALS AND
POSITION 2 FOR BIPOLAR
SIGNALS.
4-40 VIF & FN CONVERTERS
F
OUT
=V
BRIDGE
(2R. + 1) (FCLOCK/2)
RG
10V
Figure 33. Bridge TrensduC41rlnterfBt:e
~ANALOG
WDEVICES
FEATURES
Low Cost
Single or Dual Supply, 5 to 36 Volts, ±5V to ± 18V
Full Scale Frequency Up to 500kHz
Minimum Number of External Components Needed
Versatile Input Amplifier
Positive or Negative Voltage Modes
Negative Current Mode
High Input Impedance, Low Drift
Low Power: 2.0mA Quiescent Current
Low Offset: 1mV
Low Cost Monolithic
Voltage-to-Frequency Converter
AD654 I
AD6S4 FUNCTIONAL BLOCK DIAGRAM
+Vs
-Vs
I
LOGIC
COMMON
PRODUCT DESCRIPTION
The AD654 is a monolithic V/F converter consisting of an input
amplifier, a precision oscillator system, and a high current output
stage. A single RC network is all that is. required to set up any
full scale (F.S.) frequency up to 500kHz and any F.S. input
voltage up to ±30V. Linearity error is only 0.03% for a 250kHz
F.S., and operation is guaranteed over an 80dB dynamic range.
The overall temperature coefficient (excluding the effects of
external components) is typically ± 50ppml"C. The AD654
operates from a single supply of 5 to 36V and consumes only
2.0mA quiescent current.
The low drift (4/LVI"C typ) input amplifier allows operation
directly from small signals such as thermocouples or strain
gauges while offering a high (250M!}) input resistance. Unlike
most V/F converters, the AD654 ·provides a square-wave output,
and can drive up to 12 TTL loads, opto-couplers, long cables,
or similar loads.
PRODUCT HIGHLIGHTS
1. Packaged in both an 8-pin mini-DIP and an· 8-pin SOIC
package, the AD654 is a complete V/F converter requiring
only an RC timing network to set the desired full scale frequency
and a selectable pull-up resistor for the open-collector output
stage. Any full scale input voltage range from lOOmV to 10
volts (or greater, depending on + Vs) can be accommodated
by proper selection of the timing resistor. The full scale
frequency is then set by the timing capacitor from the simple
relationship, f = V/IORC.
2. A minimum number of low cost external components are
necessary. A single RC network is .all that is required to set
up any full scale frequency up to 500kHz and any full scale
input voltage up to ±30V.
3. Plastic packaging allows low cost implementation of the
standard VFC applications: AID conversion, isolated signal
transmission, FN conversion, phase-locked loops, and tuning
switched-capacitor fllters.
4. Power supply requirements are minimal; only 2.0mA of
quiescent current is drawn from the single positive supply
from 4.5 to 36 volts. In this mode, positive inputs can vary
from 0 volts (ground) to ( + Vs - 4) volts. Negative inputs
can easily be connected for below ground operation.
5. The versatile open-collector output stage can sink more than
lOrnA with a saturation voltage less than 0.4 volts. The Logic
Common terminal can be connected to any level between
ground (or - Vs) and 4 volts below + Vs. This allows easy
direct interface to any logic family with either positive or
negative logic levels.
VlF & FN CONVERTERS 4-41
SPEC IFICAli 0NS (~= + 25"1: and Vs (total) = 5to 16.5V, unless otherwise specified. All testing done
@ Vs =
+ 5¥).
AD6S4JN/JR
Model
CURRENT-TO-FREQUENCY CONVERTER
Frequency Range
Nonlinearityi
fmax = 250kHz
fmax = 500kHz
Full Scale Calibration Error
C = 390pF, lIN = l.OOOrnA
vs. Supply (fmax :S 250kHz)
Vs = +4.75to +S.25V
Vs = +5.25to + l6.5V
vs. Temp (0 to 70°C)
ANALOG INPUT AMPLIFIER
(Voltage-to-Current Converter)
Voltage Input Range
Single Supply
Dual Supply
Input Bias Current
(Either Input)
Input Offset Current
Input Resistance (Non-Inverting)
Input Offset Voltage
vs. Supply
Vs = +4.7Sto +S.2SV
Vs= +S.2Sto+16.SV
vs. Temp (0 to 70°C)
OUTPUT INTERFACE (Open Collector Output)
(Symmetrical Square Wave)
Output Sink Current in Logic "0"2
VOUT = 0.4Vmax,2SoC
VOUT = 0.4Vmax,Ot070°C
Output Leakage Current in Logic" 1"
Ot070°C
Logic Common Level Range
Rise/FallTimes(CT = O.OlfLF)
I'N= ImA
lIN = IfLA
POWER SUPPLY
Voltage, Rated Performance
Voltage, Operating Range
Single Supply
Dual Supply
Quiescent Current
Vs(Total) = 5V
Vs(Total) = 30V
TEMPERATURE RANGE
Operating Range
PACKAGE OPTIONS 3
SOIC(R-8)
Plastic DIP (N-8)
Min
Typ
0
0.06
0.20
-10
0.20
0.05
50
Units
500
kHz
0.1
0.4
%
%
10
%
0.40
0.10
%N
%N
ppmI"C
(+Vs -4)
(+Vs -4)
V
V
30
5
250
0.5
50
nA
nA
Mn
mV
0.1
0.03
4
0.25
0.1
0
-Vs
10
5
Max
20
10
10
SO
-Vs
1.0
100
500
(+Vs -4)
0.2
I
mVN
mVN
fLVrC
rnA
rnA
nA
nA
V
fLS
fLS
4.5
16.5
V
4.5
±5
36
± 18
V
V
2.5
3.0
rnA
rnA
85
°C
1.5
2.0
-40
AD654JR
AD654JN
NOTES
'Atfm . . = 250kHz;R-,. = IkO,CT = 39OpF,I'N = O-lmA.
f max = 500kHz; RT = Ildl,CT = 200pF,I'N = O-lmA.
'The sink current is the amount of current that can flow into Pin I ofthe AD654 while maintaining a maximum voltage ofO.4V between Pin I and Logic Common.
'See Section 14 for package outline information.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.
All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
4-42 VIF & FN CONVERTERS
AD654
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage +Vs to -Vs
Maximum Input Voltage
(Pins 3, 4) to - Vs . • . . . . .
. . . . . . . 36V
-3OOmVto +Vs
CIRCUIT OPERATION
The AD654's block diagram appears in Figure I. A versatile
operational amplifier serves as the input stage; its purpose is to
convert and scale the input voltage signal to a drive current in
the NPN follower. Optimum performance is achieved when, at
the full scale input voltage, a lmA drive current is delivered to
the current-to-frequency converter (an astable multivibrator).
The drive current provides both the bias levels and the charging
current to the externally connected timing capacitor. This "adaptive" bias scheme allows the oscillator to provide low nonlinearity
over the entire current input range of lOOnA to 2mA. The square
wave oscillator output goes to the output driver which provides
a floating base drive to the NPN power transistor. This floating
drive allows the logic interface to be referenced to a level other
than - Vs.
.v,
1+5V TO -Vs +3O}
-v,
IOV TO -15VI
Maximum Output Current
Instantaneous . . . .
Sustained . . . . . . . .
Logic Common to - Vs . .
Storage Temperature Range .
rejection degrades as the input exceeds ( + Vs - 3.75V) and at
( + Vs - 3.5V) the output frequency goes to zero.
As indicated by the scaling relationship in Figure I, a O.OIILF
timing capacitor will give a 10kHz full scale frequency, and
O.ooIILF will give 100kHz with a lmA drive current. Good V/F
linearity requires the use of a capacitor with low dielectric absorption (DA), while the most stable operation over temperature
calls for a component having a small tempco. Polystyrene, polypropylene, or Teflon· capacitors are preferred for tempco and
dielectric absorption; other types will degrade linearity. The
capacitor should be wired very close to the AD654. In Figure I,
Schottky diode CRI (MBDIOI) prevents logic common from
dropping more than 500mV below - Vs. This diode is not
required if - Vs is equal to logic common.
VIF CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENT
The AD654 can accommodate a wide range of negative input
voltages with proper selection of the scaling resistor, as indicated
in Figure 2. This connection, unlike the buffered positive connection, is not high impedance because the signal source must
supply the lmA F.S. drive current. However, large negative
voltages beyond the supply can be handled easily by modifying
the scaling resistors appropriately. If the input is a true current
source, RI and R2 are not used. Again, diode CRI prevents
latch-up by insuring Logic Common does not drop more than
500mV below - Vs. The clamp diode (MBDIOI) protects the
AD654 input from "below - Vs " inputs.
.v,
Figure 1. Standard V-F Connection for Positive Input
Voltages
VIF CONNECTION FOR POSITIVE INPUT VOLTAGES
In the connection scheme of Figure I, the input amplifier presents
a very high (250M!}) impedance to the input voltage, which is
converted into the proper drive current by the scaling resistors
at pin 3. Resistors RI and R2 are selected to provide a lmA full
scale current with enough trim range to accommodate the AD654's
l()% FS error and the components' tolerances. Full scale currents
other than ImA can be chosen, but linearity will be reduced;
2mA is the maximum allowable drive. The AD654's positive
input voltage range spans from - Vs (ground in single supply
operation) to four volts below the positive supply. Power supply
*Teflon is a trademark of E. I. Du Pont de Nemours & Co.
· . . . . . . . . 50mA
· . . . . . . . . 25mA
-500mVto (+Vs -4)
· .. -65°C to + 150°C
(+5VTO -Vs +301
.,
-v,
(OVTO -15VI
Figure 2. V-F Connections for Negative Input Voltages or
Current
VlF & FN CONVERTERS 4-43
II
OFFSET CALIBRATION
In theory, two adjustments calibrate a V/F: scale and offset. In
practice, most applications find the AD654's ImV max voltage
offset sufficiently low to forgo offset calibration. However, the
input amplifu:r's 30nA (typ) bias currents will generate an offset
due to the difference in DC source resistance between the input
terminals. This offset can be substantial for large values of
RT = Rl + R2 and will vary as the bias currents drift over
temperature. Therefore, to maintain the AD654's low offset, the
application may require balancing the DC source resistances at
the inputs (pins 3 and 4).
±O.6V
""'_-< }_-----'
v,.o-.......,........
Figure 3d. Offset Trim Negative Input (- 10V FS)
For positive inputs, this is accomplished by adding a compensation
resistor nominally equal to RT in series with the input as shown
in Figure 3a. This limits the offset to the product of the 30nA
bias current and the mismatch between the source resistance RT
and ReoMP. A second, smaller offset arises from the inputs' 5nA
offset current flowing through the source resistance RT or ReoMP.
For negative input voltage and current connections, the compensation resistor is added at pin 4 as shown in Figure 3b in
lieu of grounding the pin directly. For both positive and negative
inputs, the use of ReoMP may lead to noise coupling at pin 4
and should therefore be bypassed for lowest noise operation.
Figure 3a. Bias Current Compensation - Positive Inputs
Figure 3b. Bias Current Compensation - Negative Inputs
If the AD654's ImV offset voltage must be trimmed, the trim
must be performed external to the device. Figure 3c shows an
optional connection for positive inputs in which RoFFI and
RoFF2 add a variable resistance in series with RT • A variable
source of ±0.6V applied to RoFFI then adjusts the offset ± ImV.
Similarly, a ± 0.6V variable source is applied to RoFF in
Figure 3d to trim offset for negative inputs. The ±0.6V bipolar
source could simply be an AD589 reference connected as shown
in Figure 3e.
Rl
10k
+5Vo-~~~~-~----,
+
R3
10k
AD589
R4
10k
-5Vo--y~
R2
10k
__--~---~
Figure 3e. Offset Trim Bias ,rvetvvork
FULL SCALE CALIBRATION
Full scale trim is the calibration of the circuit to produce the
desired output frequency with a full scale input applied. In
most cases this is accomplished by adjusting the scaling resistor
RT • Precise calibration of the AD654 requires the use of an
accurate voltage standard set to the desired FS value and an
accurate frequency meter. A scope is handy for monitoring
output waveshape. Verification of converter linearity requires
the use of a switchable voltage source or DAC having a linearity
error below ± 0.005%, and the use of long measurement intervals
to minimize count uncertainties. Since each AD654 is factory
tested for linearity, it is unnecessary for the end-user to perform
this tedious and time consuming test on a routine basis.
Sufficient FS calibration trim range must be provided to accommodate the worst-case sum of all major scaling errors. This
includes the AD654's 10% full scale error, the tolerance of the
fIXed scaling resistor, and the tolerance of the timing capacitor.
Therefore, with a resistor tolerance of 1% and a capacitor tolerance
of 5%, the fIXed part of the scaling resistor should be a maximum
of 84% of nominal, with the variable portion selected to allow
116% of the nominal.
If the input is in the form of a negative current source, the
scaling resistor is no longer required, eliminating the capability
of trimming FS frequency in this fashion. Since it is usually not
practical to smoothly vary the capacitance for trimming purposes,
an alternative scheme such as the one shown in Figure 4 is
needed. Designed for a FS of lmA, this circuit divides the
input into two current paths. One path is through the loon
R2
100n
R4
.........
39I\1U\~--~--'~~
L.{>H-IH---"
I
IOTTV)
I
~1~~
v,.
TfI"NSlSTOA~
TTL logic compatibility. Although the output stage may become
speed limited, the multivibrator core itself is able to oscillate to
IMHz or more. The designer may take advantage of this feature
in order to operate the device at frequencies in excess of
500kHz.
Figure 13 illustrates this with a circuit offering 2MHz full scale.
In this circuit the AD654 is operated at a full scale (FS) of
lmA, with a Cr of lOOpF. This achieves a basic device FS
frequency of IMHz across CT. The P channel JFETs, QI and
Q2, buffer the differential timing capacitor waveforms to a low
impedance level where the push-pull signal is then AC coupled
to the high speed comparator A2. Hysteresis is used, via R7, for
non-ambiguous switching and to eliminate the oscillations which
would otherwise occur at low frequencies.
The net result of this is a very high-speed circuit which does
not compromise the AD654 dynamic range. This is a result of
the FET buffers typically having only a few pA of bias current.
The high end dynamic range is limited, however, by parasitic
package and layout capacitances in shunt with CT, as well as
those from each node to AC ground. Minimizing the lead length
between A2-6/A2~7 a.tld Ql!Q2 in PC layout will help. A grow"ld
plane will also help stability. Figure 14 shows the waveforms VI
- V4 found at the respective points shown in Figure 13.
Figure 12. Frequency Doubler
Resistors RI - R3 are used to scale the 0 to + 10V input voltage
down to 0 to + IV as seen at pin 4 of the AD654. Recall that
VIN must be less than V SUPPLY -4V, or in this case less than
1V. The timing resistor and capacitor are selected such that this
O.to + IV signal seen at pin 4 results in a 0 to 200kHz output
frequency.
The use of R4, CI and the XOR gate doubles this 200kHz
output frequency to 400kHz. The AD654 output transistor is
basically used as a switch, switching capacitor CI between a
charging mode and a discharging mode of operation. The voltages
seen at the input of the 74LS86 are shown in the waveform
diagram. Due to the difference in the charge and discharge time
constants, the output pulse widths of the 74LS86 are not equal.
The output pulse is wider when the capacitor is charging due to
its longer rise time than fall time. The pulses should therefore
be counted on their rising, rather than falling, edges.
OPERATION AT inGBER OUTPUT FREQUENCIES
Operation of the AD654 via the conventional output (pins 1
and 2) is speed limited to approximately 500kHz for reasons of
V3
Figure 14. Waveforms of 2MHz Frequency Doubler
The output of the comparator is a complementary square wave
at IMHz FS. Unlike pulse train output V/F converters, each
half-cycle of the AD654 output conveys information about the
input. Thus it is possible to count edges, rather than full cycles
of the output, and double the effective output frequency. The
XOR gate following A2 acts as an edge detector producing a
short pulse for each input state transition. This effectively doubles
the VIP FS frequency to 2MHz. The frnal result is a IV full
scale input VIP with a 2MHz full-scale output capability; typical
nonlinearity is 0.5%.
Figure 13. 2MHz, Frequency Doubling VlF
4-48 VIF & FN CONVERTERS
IIIIIIII ANALOG
WDEVICES
FEATURES
High Linearity
±O.01% max at 10kHz FS
± 0.05% max at 100kHz FS
± 0.2% max at 500kHz FS
Output TTL/CMOS Compatible
V/F or FN Conversion
6 Decade Dynamic Range
Voltage or Current Input
Reliable Monolithic Construction
Voltage-to-Frequencyand
Frequency-to-Voltage Converter
ADVFC32 I
ADVFC32 PIN CONFIGURATION
"N"PACKAGE
ONE SHOT
10 COMPARATOR
INPUT
CAPACITOR
TOP VIEW
PRODUCT DESCRIPTION
The industry standard ADVFC32 is a low cost monolithic voltageto-frequency (yIF) converter or frequency·to-voltage (FN)
converter with good linearity (0.01% max error at 10kHz) and
operating frequency up to O.SMHz. In the VlF configuration,
positive or negative input voltages or currents can be converted
to a proportional frequency using only a few external components.
For FN conversion, the same components are used with a simple
biasing network to accommodate a wide range of input logic
levels.
TTL or CMOS compatibility is achieved in the VIP operating
mode using an open collector frequency output. The pullup
resistor can be connected to voltages up to 30 volts, or to + lSV
or + SV for conventional CMOS or TTL logic levels. This
resistor should be chosen to limit current through the open
collector output to SmA. A larger resistance can be used if
driving a high impedance load.
Input offset drift is only 3ppm of full scale per ·C, and
full scale calibration drift is held to a maximum of 100ppmrC
(ADVFC32BH) due to a low T.C. zener diode.
The ADVFC32 is available in commercial, industrial, and extended
temperature grades. The commercial grade is packaged in a 14pin plastic DIP while the two wider temperature range parts are
packaged in hermetically sealed TO-100 cans.
ORDERING GUIDE
Part
Number
Gain Tempco
ppmf'C
ADVFC32KN
±7Styp
ADVFC32BH
ADVFC32SH
±lOOmax
±150max
Temp Range
Paclcage
"C
Oto +70
l4-Pin
Plastic DIP
-25to +85 TO-IOO
-55to +125 TO-IOO
"u" PACKAGE - TO-lOO
TOP VIEW
PRODUCT HIGHLIGHTS
1. The ADVFC32 uses a charge balancing circuit technique (see
Functional Block Diagram) which is well suited to high
accuracy voltage-to· frequency conversion. The full-scale
operating frequency is determined by only one precision
resistor and capacitor. The tolerance of other support components (including the integration capacitor) is not critical.
Inexpensive ± 20% resistors and capacitors can be used without
affecting linearity or temperature drift.
2. The ADVFC32 is easily configured to satisfy a wide range of
system requirements. Input voltage scaling is set by selecting
the input resistor which sets the input current to 0.25mA at
the maximum input voltage.
3. The same components used for VIF conversion can also be
used for FN conversion by adding a simple logic biasing
network and reconfiguring the ADVFC32.
4. The ADVFC32 is intended as a pin-for-pin replacement for
VFC32 devices from other manufacturers.
VIF & FN CONVERTERS 4-49
II
SPECIFICATIONS (typical
ADVFC32K
Tn>
DYNAMIC PERFORMANCE
Full Scale Frequency Range
Nonlinearity'
f~= 10kHz
f~= 100kHz
f.... = O.5MHz
Full Scale Calibration Error
(Adju.tabletoZero)
v •. Supply
(Full Scale Freq~.ency = 100kHz)
VB. Temperature
(Full Scale Frequency = 10kHz)
500
0
500
kHz
-0.01
-0.05
-0.20
+0.01
+0.05
+0.20
-0.01
-0.05
-0.20
+0.01
+0.05
+0.20
%
%
%
:0.01
+0.05
+0.20
Tn>
:0.05
:5
+0.015
I Pulse of New Frequency Plu. II"
I Pulse of New Frequency Plu. 11"
ANALOG INPUT AMPLIFIER
(VIFConversion)
Current Input Range
Voltage Input Range
0
0
+0.25
-10,
x
+0.015
-0.015
+0.015
%ofFSRI%
+ 100
+1SO
+158
ppmI"C
1 Pulse of New Frequency Plus 1f.4S
I Pulse of New Frequency Plu. 11"
+0.25
-10,
0.25
0
0
Noninverting Input
40
±8
-100
OPEN COLLECTOR OUTPUT
(VIF Conversion)
Output Voltage in Logic "0"
ISJNK = 8mA
Output Leakage Current in Logic "I"
Voltage Range
Fall Times (Load = 500pF and
ISJNK = 5mA)
AMPLIFIER OUTPUT (FIV Conversion)
Voltage Range (0mA",Io ",7mA)
Source Corrent (0",Vo "'7V)
Capacitive Load (Without Oscillation)
Closed Loop Output Impedance
POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current
TEMPERATURE RANGE
Specified Range
Operating Range
Storage
PACKAGE OPTIONS'
PlasticDIP(N-14)
TO-IOO(H-IOA)
40
:8
-100
-0.6
+Vs
0.15/f.....
2SOkn
0.4
1
+30
0
-Vs
+1
0.1
50kOlilOpF
+10
0.4
1
+30
+10
0
10
-Vs
+1
0.1
50knillOpF
±18
:9
6
8
0
-25
-25
+70
+85
+85
-25
- 55
-65
INonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a percentage of full scale.
'See FtgUre 3.
'See Figure I.
4fmn expressed in units of MHz.
5See Section 14 for package outline information.
Specifications subiect to change without notice.
Specifications obown in boldface are ...ted on all production units at final electrical ...t. Results from thooe ..... are used to caleulate oulJlOing quality levels. All
min and maK specifieations are guaranteed, although only thooe sbOWll in
boldface are tested OIl all production units.
4
mV
I'vrc
a.IS/fmlx
V
V
1"
0.4
1
+30
V
I'A
V
400
os
+10
V
mA
pF
Il
250kn
0
10
100
I
:.tIS
±IS
8
±9
+85
+ 125
+ 150
-55
-55
-65
8
V
V
mA
+125
+125
+ ISO
"C
"C
"C
±18
6
ADVFC32KN
ADVFC32BH
nA
nA
-0.6
+Vs
0
±IS
±IS
±9
258
+100
30
100
1
NOTES
4-50 VlF & FN CONVERTERS
40
±8
-100
400
100
I
6
X RIN 3
±Vs
250kn
400
0
10
258
+100
-0.6
+Vs
0.15/f.....
0
mA
V'
mA
3OOknIIIOpF 2MIl~IOpF
3OOMO~3pF 750MIlIIIOpF
±Vs
±Vs
-Vs
+1
0.1
50knillOpF
+0.25
-10,
0.25
0
0
4
30
4
30
vs. Temperature (Tmin to Tmax)
Safe Input Voltage
COMPARATOR (FN Converaion)
Logic "0" Level
Logic "I" Level
Pulse Width Range'
Input Impedance
258
+100
1 Pulse of New Frequency Plus If.Ls
I Pulse of New Frequency Plu. 11"
X RIN 3
300kn~IOpF 2MO~IOpF
300MO~3pF 750MOlilOpF
300Mn113pF 7SOMO~3pF
%
-100
R(N3
300kn~IOpF 2MO~IOpF
Ullils
-0.015
0.25
Inverting Input
Input Offset Voltage
(Trimmable to Zero)'·'
±0.05
:5
:5
±75
Max
0
500
-0.01
-0.05
-0.20
DYNAMIC RESPONSE
Maximum Settling Time for Full Scale
Step Input
Overload Recovery Time
Differential Impedance
Common-Mode Impedance
Input Bias Current
Tn>
Mia
0
-0.015
ADVFC32S
Max
Mia
:0.05
noted)
ADVFC32B
Max
Mia
Model
+ 25"& with Vs = ± 15V unless otherwise
@
ADVFC32SH
Applying the ADVFC32
UNIPOLAR V/F, PosmVE INPUT VOLTAGE
fol-.....- - - - O N l C Y C L . - - - - - - - ...,1
When operated as a V/F converter, the transformation from
voltage to frequency is based on a comparison of input signal
magnitude to the lmA internal current source.
A more complete understanding of the ADVFC32 requires a
close examination of the internal circuitry of this part. Consider
the operation of the ADVFC32 when connected as shown in
Fignre 1. At the start of a cycle, a current proportional to the
t,
CHARGE
I
t~
DISCHARGE
t,
I
i
i
i
'
i
:~T~"tos
I
......... ·.-tos
:
I
I
I
I
I
I
...............'
1
;-
v"'"
/
I i
DV
~~~__~t:==
___tos_=-:i_~i~__________________-+!___
C2
v,.o-o¥J""'_...·)----,
I
I
i
~.s~----~i~~~---~--------------------~:"c--
CA=I~R
~-3.4V
i
i
i}-....--I-o.'sv
I
RIN =
Rz ;;"
_ _- {
Figure 1. Connection Diagram for VIF Conversion,
Positive Input Voltage
input voltage flows through R3 and Rl to charge integration
capacitor C2. As charge builds up on C2, the output voltage of
the input amplifier decreases. When the amplifier output voltage
(pin 13) crosses ground (see Figure 2 at time tl), the comparator
triggers a one shot whose time period is determined by capacitor
C1. Specifically, the one shot time period (in nanoseconds) is:
tos "" (C I
+ 44pF)
(ImA -lIN) x tos = lIN
X (
-1--tos)
FOUT
or, rearranging terms,
lIN
- .,--..,--OUT - ImA x tos
The complete transfer equation can now be derived by substituting
lIN = VINIRIN and the equation relating Cl and tos. The final
equation describing ADVFC32 operation is:
FOUT = lmA
X
VINIRIN
(C I + 44pF) x 6.7kO
Components should be selected to optimize performance over
the desired input voltage and output frequency range using the
equations listed below:
C - 3.7 x WpF/sec
I F OUTFS
VINFS
0.25mA
+VLOGIC
---smx-
Both RIN and C I should have very low temperature coefficients
as changes in their values will result in a proportionate change
in the V/F transfer function. Other component values and temperature coefficients are not critical.
VINFS
FOUTFS
C1
RIN
C2
IV
10V
IV
lOY
10kHz
10kHz
100kHz
100kHz
3650pF
3650pF
330pF
330pF
4.0kO
40kO
4.0kO
4OkO
O.OIILF
O.OIILF
IOOOpF
l000pF
Table I. Suggested Values for CI , R'N and C2
x 6.7kO
During this period, a current of (lmA - lIN) flows out of the
integration capacitor. The total amount of charge depleted during
on!! cycle is, therefore (ImA - lIN) x tos. This charge is replaced
during the remainder of the cycle to return the integrator to its
original voltage. Since the charge taken out of C2 is equal to the
charge that is put on C2 every cycle,
F
I
Figure 2. Voltage-to-Frequency Conversion Waveforms
-'5V o--.....-;::{.
fOUTG-<~
:
i
-44pF
C z = 10-; Farads/sec (IOOOpF minimum)
OUTF8
Input resistance RIN is composed of a fixed resistor (R 1) and a
variable resistor (R3) to atlow for initial gain error compensation.
To cover all possible situations, R3 should be 20% of R 1N, and
Rl should be 90% of R IN . This allows a ± 10% gain adjustment
to compensate for the ADVFC32 full-scale error and the tolerance
of C1.
If more accurate initial offset is required, the circuit of R4 and
RS can be added. RS can have a value between IOkO and lOOkO,
and R4 should be approxinlately 10MO. The amount of current
required to trim zero offset will be relatively small, so the temperature coefficients of these resistors are not critical. If large
offsets are added using this circuit, temperature drift of both of
these resistors is much more important.
BIPOLAR VIP
By adding another resistor from pin I (pin 2 of TO-IOO can) to
a stable positive voltage, the ADVFC32 can be operated with a
bipolar input voltage. For example, an 80kO resistor to + lOY
causes an additional current of 0.125mA to flow into the integrator
so that the net current flow to the integrator is positive even for
negative input voltages. At negative full scale input voltage,
0.125mA will flow into the integrator from VIN cancelling out
the 0.125mA from the offset resistor, resulting in an output
frequency of zero. At positive full scale, the sum of the two
currents will be 0.25mA and the output will be at its maximum
frequency.
VlF & FIV CONVERTERS 4-51
II
UNIPOLAR VIF, NEGATIVE INPUT VOLTAGE
Figure 3 shows the connection diagram for VIF conversion of
negative input voltages. In this configuration full scale output
frequency occurs at negative fuJI scale input, and zero output
frequency corresponds to zero input voltage.
A very high impedance signal source may be used since it only
drive the noninverting integrator input. Typical input impedance
at this terminal is 2S0M!} or higher. For V/F conversion of
positive input signals the signal generator must be able to source
O.2SmA to properly drive the ADVFC32, but for negative VIF
conversion the O.2SmA integration current is drawn from ground
through Rl and R3.
c•
.-----~~--------~
FN CONVERSION
Although the mathematics ofFN conversion can be very complex,
the basic principle is easy to understand. Figure 4 shows the
connection diagram for FN conversion with TTL input logic
levels. Each time the input signal crosses the comparator threshold
going negative, the one shot is activated and switches lmA into
the integrator input for a measured time period (determined by
Cl). As the frequency increases, the amount of charge injected
into the integration capacitor increases proportionately. The
voltage across the integration capacitor is stabilized when the
leakage current through Rl and R3 equals the average current
being switched into the integrator. The net result of these two
effects is an average output voltage which is proportional to the
input frequency. Optimum performance can be obtained by
selecting components using the same guidelines and equations
listed in the VIF conversion section.
GAIN ADJUST
-lOVo--....- - (
i).-.--_~".V
-l.Vo--....-...(.
fOUT
0-4>----{
Figure 3. Connection DiB(Jram for VIF Conversion,
Negative Input VoltB(Je
Circuit operation for negative input voltages is very similar to
positive input unipolar conversion described in the previous
section. For best operating results use component equations
listed in that section.
4-52 VIF & FN CONVERTERS
121<11
i)-~-----II-oIIN
'-'
Figure 4. Connection Diagram for FN Conversion, TTL
Input
Application Hints - ADVFC32
DECOUPLING
Decoupling power supplies at the device is good practice in any
system, but absolutely imperative in high resolution applications.
For the ADVFC32, it is important to remC!1Ilber where the
voltage transients and ground currents flow. For example, the
current drawn through the output pulldown transistor originates
from the logic supply, and is directed to ground through pin II
(pin S ofTO-lOO). Therefore, the logic supply should be decoupled
near the ADVFC32 to provide a low impedance return path for
switching transients. Also, if there is a separate digital ground it
should be connected to the analog ground at the ADVFC32.
This will prevent ground offsets that could be created by directing
the full SmA output current into the analog ground, and subsequently back to the logic supply.
Although some circuits may operate satisfactorily with the power
supplies decoupled at only one location on each board, this
practice is not recommended for the ADVFC32. For best results,
each supply should be decoupled with O.I ....F capacitor at the
ADVFC32. In addition, a larger board level decoupling capacitor
of I ....F to lO ....F should be located relatively close to the ADVFC32
on each power supply.
COMPONENT TEMPERATURE COEFFICIENTS
The drift specifications of the ADVFC32 do not include temperature effects of any of the supporting resistors or capacitors.
The drift of the input resistors Rl and R3 and the timing capacitor
C 1 directly affect the overall temperature stability. In the application of Figure 2, a IOppml"C input resistor used with a
lOOppml"C capacitor may result in a maximum overall circuit
gain drift of:
lOOppmrc (ADVFC32BH) + 100ppml"C (Cl)
+ 10ppmrc (R1N) = 210ppmI"C
Although RIN and C 1 have the most pronounced effect on temperature stability, the offset circuit of resistors R4 and R5 may
also have a slight effect on the offset temperature drift of the
circuit. The offset will change with variations in-the resistance
of R4 and supply voltage changes. In most applications the
offset adjustment is very small, and the offset drift attributable
to this circuit will be negligible. In the bipolar mode, however,
both the positive reference and the resistor used to offset the
signal range will have a pronounced effect on offset drift. A
high quality reference and resistor should be used to minimize
offset drift errors.
Other circuit components do not directly influence temperature
performance as long as their actual values are not so different
from nominal value as to preclude operation. This includes
integration capacitor C2. A change in the capacitance value of
C2 results in a different rate of voltage change across C2, but
this is compensated by an equal effect when C2 is discharged by
the switched lmA current source so that no net effect occurs.
The temperature effects of the components described above are
the same when the ADVFC32 is configured for negative or
bipolar input ranges, or FIV conversion.
OTHER CIRCUIT CONSIDERATIONS
•
The input amplifier connected to pins 1, 13, and 14 is not a
•
standard operational amplifier. Although it operates like an op
amp in most applications, two key differences should be noted.
First, the bias current of the positive input is typically 40nA
while the bias current of the inverting input is ± SnA. Therefore,
any attempt to cancel input offset voltage due to bias currents
by matching input resistors will create worse offsets. Second,
the output of this amplifier will sink only ImA, even though it
will source as much as 10mA. When used in the FIV mode, the
amplifier must be buffered if large sink currents are required.
MICROPROCESSOR OPERATED AID CONVERTER
With the addition of a few external components the ADVFC32
can be used as a ± lOV AID microprocessor front end. Although
the nonlinearity of the ADVFC32 is only 0.05% maximum
(0.01% typ), the resolution is much higher, allowing it to be
used in 16-bit measurement and control systems where a monotonic
transfer function is essential. The resolution of the circuit shown
in Figure 5 is dependent on the amount of time allowed to
count the ADVFC32 frequency output. Using a full scale frequency
of 100kHz, an 8-bit conversion can be made in about lOms, and
a 2 second time period allows a 16-bit measurement, including
offset and gain calibration cycles.
As shown in Figure. 5, the input signal is selected via the AD7590
input multiplexer. Positive and negative references as well as a
1DOOpF
AD7S90
-V••F,o-~f---Y
'1-1r-""--t- +15V
o---t--.
O,'p.F
--C,..- o - - - t -
lNPUT04I-l.....
- 15V -
....- - - - ( 4 )
TO MlcRO.t..ocessoR
TO COUNT INPUT OF "p ....~.....-----""""""'(
Figure 5. High Resolution, Self-Calibrating, Microprocessor
Operated AID Converter
VIF & FN CONVERTERS 4-53
+15V
AQ'"
1'.5V1
+15V
+15V
12kll
AD...
12.6V)
V'No--'\fII\r+(
0-10V
;I; •. '.F
v
Figure 6. High Noise Immunity Data Link
ground input are provided to calibrate the AlD. This is very
important in systems subject to moderate or extreme temperature
changes since the gain temperature coefficient of the ADVFC32
is as high as ± 150ppml"C. By using the calibration cycles, the
AlD conversion will be as accurate as the references provided.
The AD542 following the input multiplexer provides a high
impedance input (10 12 ohms) and buffers the switch resistance
from the relatively low impedance ADVFC32 input.
If higher linearity is required, the ADVFC32 can be operated at
10kHz, but this will require a proportionately longer conversion
time. Conversely, the conversion time can be decreased at the
expense of nonlinearity by increasing the maximum frequency
to as high as 500kHz.
HIGH NOISE IMMUNITY, HIGH eMU ANALOG DATA
LINK
In many applications, a signal must be sensed at a remote site
and sent through a very noisy environment to a central location
for further processing. In these cas<;s, even a shielded cable may
not protect the signal from noise pickup. The circuit of Figure
6 provides a solution in these cases. Due to the optocoupler and
voltage-to-frequency conversion, this data link is extremely
insensitive to noise and common mode voltage interference. For
even more protection, an optical fiber link substituted for the
HCPL2630 will provide common mode rejection of more than
several hundred kilovolts and virtually total immunity to electrical
noise. For most applications, however, the frequency modulated
signal has sufficient noise immunity without using an optical
fiber link, and the optocoupler provides common mode isolation
up to 3000V dc.
The data link input voltage is changed in a frequency modulated
signal by the first ADVFC32. A 42.2kO input resistor and a
lookn offset resistor set the scaling so that a OV input signal
corresponds to 50kHz, and a lOY input results in the maximum
output frequency of 500kHz. A high frequency optocoupler is
then used to transmit the signal across any common mode voltage
potentials to the receiving ADVFC32. The optocoupler is not
necessary in systems where common mode noise is either very
smaIl or a constant low level dc voltage. In systems where common
mode voltage may present a problem, the connection between
the two locations should be through the optocoupler; no power
or ground connections need to be made.
4-54 VlF & FN CONVERTERS
The output of the optocoupler drives an ADVFC32 hooked up
in the F N configuration. Since the reconstructed signal at pin
10 has a considerable amount of carrier feedthrough, it is desirable
to filter out any frequencies in the carrier range of 50kHz to
500kHz. The frequency response of the FN converter is only
3kHz due to the pole made by the integrator, so a second 3kHz
filter will not significantly limit the bandwidth. With the simple
one pole filter shown in Figure 6, the input to output 3dB point
is approximately 2kHz, and the output noise is less than 15mV.
If a lower output impedance drive is needed, a two pole active
filter is recommended as an output stage.
Although the FN conversion technique used in this circuit is
quite simple, it is also very limited in terms of its frequency
response and output ripple. The frequency response is limited
by the integrator time constant and while it is possible to decrease
that time constant, either signal range or output ripple must be
sacrificed. The performance of the circuit of Figure 6 is shown
in ·the photograph below. The top trace is the input signal, the
middle trace is the frequency-modulated signal at the optocoupler's
output, and the bottom trace is the recovered signal at the output
of the FN converter.
Synchro & Resolver Converters
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5
DRC1745/1746 - High Power Output, Hybrid Digital-to-SynchrolResolver Converters
5-7
IPA1764 - Hybrid Inductosyn Preamplifier . . . . . . . . . . . . . . . . . . . . . . .
5 - 15
OSC1758 - Hybrid Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .
SDClRDCI740/174111742 - 12- and 14-Bit Hybrid SynchrolResolver-to-Digital Converters
5 - 17
IS14/24/44/64 - Tachogenerator Output Hybrid Resolver-to-Digital Converters . . . . . .
5 - 27
IS20/40/60/61 - Hybrid Tracking Resolver-to-Digital Converters . . . . . . . . . . . . . .
5 - 35
IS74 - Tachogenerator Output Variable Resolution, Hybrid Resolver-to-Digital Converter
5 - 43
2S50 - LVDT-to-Digital Converter . . . . . . . . . . . . . . . . . .
5 - 51
.... .
5 - 53
2S54/56/58 - High Resolution LVDT-to-Digital Converters
5 - 19
2S80 - Variable Resolution, Monolithic Resolver-to-Digital Converter
5 - 65
2S81 - Low Cost Monolithic 12-Bit Resolver-to-Digital Converter ..
5 -77
2S82 - Variable Resolution, Monolithic Resolver-to-Digital Converter
5 - 89
5S70/72 - Synchro and Resolver Isolation Transformers
6S04 - Digital Director . . . . . . . . . . . . . . . . . . . . . . . .
5 - 103
5 - 101
SYNCHRO & RESOL VER CONVERTERS 5-1
•
'f
'"
(I)
~
~
lJ
Selection Guide
Synchro & Resolver Converters
0
Ro
SYNCHRO, RESOLVER, INDUCTOSYNt AND LVDT·TO·DIGITAL CONVERTERS
m
0
Input
Format '
Accuracy
arc mins
Tracking Rate
Options
revs/sec'
Reference
Frequency
Options Hz
Input
Isol
Package
Options3
Temp
Range4
~
:J:j
Model
Res
Bits
Page
Comments
C')
IS14
10
I, R
±25
680
2k->10k
No
D,M
C,M
5-27
SDCIRDC1741
12
S,R
±15.3
IS
400,2.6 k
Yes
M
C,M
5-19
SDCIRDC1742
l2
S,R
±S.5
IS
400,2.6 k
Yes
M
C,M
5-19
IS20
12
I, R
±8.5
50,90, 170
400->2.6 k,
2.6 k->5 k,
5 k->1O k
No
D,M
C,M
5-35
IS24
12
I, R
±8.5
170
2k->10k
No
D,M
C,M
5-27
2SS1
12
I, R
±30 5
260
400->20 k
No
D
C
5-77
SDCIRDC1740
14
S,R
±5.3
12
400,2.6 k
Yes
M
C,M
5-19
IS40
14
I, R
±5.3
12.5, 22.5, 42.5
400->2.6 k,
2.6 k->5 k,
5 k->10 k
No
D,M
C,M
5-35
IS44
14
I, R
±5.3
42.5
2k--->10k
No
D,M
C,M
5-27
2S54
14
LVDT
±0.006 6
360 LSB/ms 7
360->5 k
No
M
C,M
5-53
IS60
16
I, R
±4.0, ±2.65
3, 5.5, 10.5
400--->2.6 k,
2.6 k->5 k,
5 k->1O k
No
D,M
C,M
5-35
Error, Ripple Carry,
Direction and High
Quality Tachometer Output
Tristate, Latched Output
Internal Transformer Isolation
Tristate, Latched Output
Internal Transformer Isolation
High Tracking Rate with Velocity,
Error, Ripple Carry and
Direction Outputs, Latched,
Tristate Output. Low Cost
Error, Ripple Carry,
Direction and High
Quality Tachometer Output
Monolithic, User Selectable
Dynamic Characteristics
High Tracking Rate,
Quality Velocity Output
Tristate, Latched Output
Internal Transformer Isolation
High Tracking Rate with Velocity,
Ripple Carry and Direction
Outputs, Latched, Tristate
Output. Low Cost
Error, Ripple Carry,
Direction and High
Quality Tachometer Output
Direct Ratiometric Conversion
of L VDT Signal, Selectable
Input Gain. No External Trims
High Tracking Rate with Velocity,
Error, Ripple Carry and
Direction Outputs. Latched
Tristate Output. Low Cost
r-
0
<
~
:J:j
i1
~
SYNCHRO, RESOLVER, INDUCTOSYNt AND LVDT-TO-DIGITAL CONVERTERS
Res
Bits
Input
Format!
Accuracy
arc mins
Tracking Rate
Options
revs/sec'
Reference
Frequency
Options Hz
Input
Isol
Package
Options'
Temp
Range4
Page
Comments
IS61
16
I, R
±1O, ±4.05
3, 5.5, 10.5
400~2.6
No
D,M
C,M
5-35
Lower Accuracy Version of
lS60. Low Cost
1S64
16
I, R
±4.0, ±2.6 5
10.5
k,
2.6 k~5 k,
5 k->l0 k
2k->10k
No
D,M
C,M
5-27
2S56
16
LVDT
±0.006 5
360 LSB/ms7
360~5
No
M
M
5-53
1S74
10,12,
14,16
16
I, R
±4.0, ±2.65
6809
2k~lOk
No
D,M
C,M
5-43
LVDT
±0.003 6
680 LSB/ms 7
7k->l1k
No
M
C,M
5-53
Error, Ripple Carry,
Direction and High
Quality Tachometer Output
Direct Ratiometric Conversion
of LVDT Signal, Selectable
Input Gain. No External Trims
High Quality Tachometer
Output, Variable Resolution
Direct Ratiometric Conversion
of L VDT Signal, High Gain,
Ultra-Linear
Monolithic, User Selectable
Dynamic Characteristics, and
Resolution High Tracking Rate
and Quality Velocity Output
Model
*2S58
(J)
~
~
o
Ill>
2S80
16,14,
12, 10'
I, R
±2, ±4, ±8
10409
50-20 k
No
D
C,M
5-65
2S82
16,14,
12, 10'
I, R
±2, ±4, ±8
10409
50-20 k
No
P
C
5-89
2S50
11
LVDT
±0.025 6
200 LSB/ms7
400, 1 k->IO k
No
D,M
C,M
5-51
IS = Synchro; R = Resolver; I = Inductosyn.
2Revsfsec equivalent to pitches/sec in the case of an Inductosyn; in general higher reference frequency options have higher tracking rates.
'Package Options: D-Side·Brazed Dual-In·Line Ceramic; M-Metal Hermetic Dual-In-Line; P-Plastic Leaded Chip Carrier (PLCC).
4Temperature Ranges: C-Commercial, 0 to +70"C; I-Industrial, -40"C to +85"C (Some older products -25"C to +85"C); M-Military, -55"C to +125"C.
'Consult data sheet.
6LVDT converter accuracy given as % full scale linearity.
7Slew Rate (min).
m
8Resolution is user selectable.
9Depends on resolution selected.
Boldface type: product recommended for new design.
t;:i
*New product since the publication of the 1987/1988 Databooks.
tlnductosyn is a registered trademark of Farrand Industries, Inc.
~
k
:l;J
~
t;:i
:l;J
rM
i}l
'f'
t.)
II
Direct Conversion of L VDT
Signal, No External Trims
Required, Tristate Output
'f'
....
CJ)
~
2
Selection Guide
Synchro & Resolver Converters
lj
0
Ro
DIGITAL-TO-SYNCHRO AND RESOLVER CONVERTER
~
Q
~
Model
Res
Bits
8<:
DR1745
14
Output
Format1
R4
DR1746
16
R4
lj
Accuracy
arc mins
±2, ±45
Load
Driving
Capability
2.0VA6
±2, ±45
2.0VA6
Reference
Frequency
Options
Hz
Reference
Input Volt
Options
Vrms
Signal
Output Volt
Options
Vrms
dc~2600
O~3.4
O~.8
dc~2600
O~3.4
O~.8
Transformer
Output
Isolations
~
Package
Options'
Temp
Range'
Page
Comments
Use Ext. STM1680
and STM1683
Transformer
M
M
5-7
Use Ext. STM1680
and STM1683
Transformer
M
M
5-7
Digital-to-Resolver Converter with Int. 2VA
Power Amplifier. Optional
Int. TransZorb~ Protection.
2 Byte Latched Inputs.
16-Bit Version of DRC1745
lj
i1
~
INPUT TRANSFORMERS
Model
5sn
5S70
Description
Frequency
Hz
Accuracy
arc mins
Input Voltage
Options
Vrms7
Package
Options
Ref Isolation for lSI4/24/44/64174
and IS20/40/60/61
Signal Input for ISI4/24/44/64174
and IS20/40/60/61
360 to
3000
360 to
3000
N/A
1l.S, 26, 115
Module
±0.33 (typ)
±1.5 (max)
1l.S, 26, 90
Module
Package
Size
Inches (mm)
1.12 x 1.12 x 0.4
(2S.5 x 2S.5 x 10.2)
2.25 x 1.12 x 0.4
(57.0 x 2S.5 x 10.2)
Page
5-101
5-101
DIGITAL DIRECTOR
Model
Description
Frequency
Hz
6S04
Universal Synchro Simulator and
Test Instrument
60 to
400
Output
Drive
VA
Accuracy
Degrees
Output Voltage
Vrms
5 (60 Hz)
15 (400 Hz)
±0.1 (60 Hz)
±0.15 (400 Hz)
90 V Synchro (CoarselFine)
4.25 V Slab (Coarse)
1l.S V Slab (Fine)
1 R = Resolver.
2Package Options: M-Metai Hermetic Dual-In-Line.
'Temperature Ranges: C-Commerciai, 0 to +70°C; I-Industrial, -40°C to +85°C (Some older products -25°C to +85°C); M-Military, -55°C to +I25'C.
'Synchro format output with external output transformer STM1683.
'Depends on option.
'Can be used with pUlsating power supply for reduced dissipation.
'Synchro and resolver format available on all models.
Boldface type: Product recommended for new design.
'New product since the publication of the 1987/1988 Databooks.
*TransZorb is a trademark of General Senticonductor Industries, Inc.
Package
Size
Inches (mm)
IS.3 x 17 x 7
(466 x 432 x 17S)
Page
5-103
Orientation
Synchro & Resolver Converters
These products constitute a complete line of devices for the
digital measurement and control of angular and linear displacements by means of synchros, resolvers, Inductosyns and LVDTs.
All use the tracking conversion technique in which the digital
output follows the synchro or resolver shaft automatically without
the need for convert commands or wait loops. Apart from producing instantaneous angular data, this inherently ratiometric
conversion method is also very tolerant of noise on the signal
inputs as well as voltage drops between the transducer and the
converter.
In addition to the integrated circuits, hybrids and modules that
perform the conversions, the line also includes support components
such as power oscillators, transformers and preamplifiers.
The range of synchro processing modules now available covers a
wide area of applications. They are widely used in military and
radar applications, but there are additional fields in which they
could be used to advantage because of the proven ruggedness
and high precision of the electromechanical hardware, their
standardized specifications and their low cost. They have a
number of advantages over potentiometers and optical systems.
In this introductory section, there will be provided a brief set of
device definitions. Detailed data and applications information is
given in the data sheets. For a complete introduction to synchrol
digital conversion, Analog Devices has available a 208-page
book, Synchro and Resolver Conversion, edited by G. Boyes
(1980), $11.50.
In this section and in much of the text, the word "Synchro"
appears frequently. In many cases, the word "ResolveI:" could
be used in its place. The modules make use of angular data in
resolver form; if the input data is in three-wire synchro form,
transformers in "Scott T" configuration convert it to resolver
form; analog outputs are available in both forms. There are a
number of voltage and frequency options.
Linear Variable displacement Transducer (LVDT) conveners
such as the 2S50 series provide the L VDT phase-sensitive
demodulation and digitization for these extremely rugged
transducers, which precisely measure displacement over limited
distances.
Digital-to-Synchro Converters (DRC176S, 1746)
Devices that accept parallel binary digital inputs (14 or 16 bits)
and an ac reference signal, and provide outputs in 3-wire synchro
form.
InductosynlResolver-to-Digital Converter
A device that produces a digital output capable of resolving (to
12 bits) intermediate distances within a single track-pitch of a
Farrand linear-Inductosyn stator in displacement- and anglemeasuring Inductosyn systems. The moving element is used as
though it were a resolver input; hence the device will also convert
resolver information to digital.
Synchro-to-Digital Converters (2S80 Family)
Devices that accept either 3-wire synchro or 4-wire resolver
inputs, together with a 2-wire ac reference, and outputs angular
binary data in a continuously tracking mode employing a Type
2 servo loop. The inputs may be from either remote synchros or
from electrically simulated synchros (e.g., DSCs).
Velocity Output
A velocity output is useful when the rate of change of position the velocity - as well as the absolute position information is
needed for monitoring and closed loop control. The 2S80 series
of monolithic resolver-te-digital converters provides an analog
velocity signal output in addition to the digital output.
Support Devices
Puwer Oscillators such as the OSC1758 act as the drive oscillator
for Inductosyns.
Input Transformers such as the 5S70 and 5S72 isolate the reference
input from the converter.
High-Gain Preamps such as the IPA1764 amplify the Inductosyn
voltages to convener levels.
REPRESENTATION OF ANGLES IN DIGITAL FORM
Binary
The most commonly used method of representing angles in
digital form is simple natural binary weighting, where the most
significant bit (MSB) represents 1800 , the next represents 900 ,
etc. The table shows the bit weights in degrees, degrees and
minutes, and radians for this coding method.
Bit No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Degrees
180
90
45
22.5
11.25
5.625
2.8125
1.40625
0.70312
0.35156
0.17578
0.08789
0.04395
0.02197
0.01099
0.00549
Degrees, Minutes
180
0
90
0
45
0
22
30
11
15
5
37.5
2
48.75
1
24.38
42.19
0
0
21.09
0
10.55
5.27
0
2.64
0
1.32
0
0
0.66
0
0.33
Radians
3.141593
1.570796
0.785398
0.392699
0.1%349
0.098175
0.049087
0.024544
0.012272
0.006136
0.003068
0.001534
0.000767
0.000383
0.000192
0.000096
SYNCHRO & RESOL VER CONVERTERS 5-5
II
5-6 SYNCHRO & RESOL VER CONVERTERS
r.ANALOG
WDEVICES
High Power Output, Hybrid
Digital-to-Synchro/Resolver Converters
DRC1745/DRC1746 I
FEATURES
1.... or 16-Bit Resolution
2 or 4 Arc-Minutes ACcuracy
2VA max Mean Output Drive Capability
Full Accuracy for dc to 2.6kHz Reference
Full Accuracy with dc or Pulsating Power
Supplies (PPS)
Guaranteed Operation With 3V dc Pedestal on PPS
Can Drive Pure Inductive. Resistive or Highly
Capacitive Loads
LS or CMOS Latched Inputs With Separate High/Low
Byte Enable
Low Radius Vector Variation (0.03%)
Optional TransZorb™ Protection Against
Inductive Spikes on Output
Protected Against + 200% Overvoltage on
Analog Input
Remote Output Sensing Facility
No Trims or External Adjustments
Full Output Short Circuit Protection
Single 4O-Pin Package
Hi Rei. MIL-STD 883B Versions Available
APPUCAnONS
Driving Synchro and Resolver Control Transformers
Avionic Equipment (e.g •• Air Data Computers)
Interfacing With Servo Systems
Fire Control System Outputs
Naval Ratransmission Unit Outputs
Outputs to Radars and Navigational Aids
Aircraft and Naval Simulators
GENERAL DESCRIPTION
The DRC1745 and DRC1746 are hybrid packaged Digital-toResolver converters. They accept a 14-bit or 16-bit digital input
word representing angle and output sine and cosine voltages
multiplied by an analog input. The converters msintain full
accuracy when the analog input frequency is in the range dc to
2.6kHz.
The units have internal power amplifiers capable of driving a
2VA load which can be pure inductive, resistive or highly capacitive. The output is fully short-circuit protected against overcurrent.
The output of the converter can be used to drive directly into
resolver control transformers or in conjunction with an external
transformer module to drive synchro control transformers. The
power available is more than adequate to drive all standard
synchro control transformers.
The separately powered output stage is compatible with conventional ± lSV dc power supplies or pulsating power supplies with
pedestal components as low as 3V de.
The use of pulsating power supplies greatly reduces the internal
power dissipation in the hybrid package which in tum maximizes
the converter's Mean Time Between Failures (MTBF).
DRC17451DRC1746 FUNCTIONAL BLOCK DIAGRAM
+15V
+ 15VIPj
-1SV
SIN SENSE
SIN
12A SIN ..,t SIN ul
SIG GND
COS SENSE
COS
(2A SIN
A.
._,t COS II)
+5V
IL OPTIONS
ONLYI
LBE
HBE
DIGITAL
INPUT
GND
-15VIPJ
'HI
NOTE: "A\.O", "GND", AND "SIG GND" ARE INTERNALLY CONNECTED
IN STAR POINT.
A particular feature of the converters is that they have a remote
sensing facility which means that output accuracy can be maintained even when long lines have to be driven.
The converter's data inputs are latched and the latches can be
CMOS or Low Power Schottky (LS). The former gives advantages
in terms of power dissipation and the latter in terms of glitch
performance when used in fast dynamic update modes. The
latches are transparent and have a separate high and low byte
enable.
As an option, the output stage can be fitted with internal TransZorb™ protection. This gives full protection against transient
voltages generated by an inductive load in response to an abrupt
change in load current. This condition can occur at switch off
or as a consequence of external power supply fault conditions.
The units are packaged in 4O-pin dual in line hybrid packages
and require no external trims or adjustments.
MODELS AVAILABLE
The DRC 1745 (l4-bit resolution) and DRC 1746 (16-bit resolution)
are available with accuracies of ± 2 or ± 4 arc-minutes. Both
units have optional TransZorb protection and a choice of either
LS or CMOS inputs (see Ordering Information).
Two sets of reference and output transformers are available.
The STMl660/STMl663 operates over 47Hz to 440Hz while
the STM1680/STM1683 operates over 360Hz to 2.6kHz. The
transformers can be Scott T connected to provide a synchro
output format.
TransZorb is a registered trademark of General Semiconductor
Industries, Inc.
SYNCHRO & RESOLVER CONVERTERS 5-7
•
SPECIFICATIONS
Model.
(typical @ +25"1: and :!:15V power supplies, unless otherwise noted)
DIGITAL INPUT RESOLUTION
DRC1745
14 Bits (1.32 arc-minutes)
DIGITAL INPUT FORMAT
Parallel natural binary, TTLcom.patible.
Includes internal21k!l pull-up resistors.
RECOMMENDED ANALOG INPUT
3.4V ons (single ended input)
3.S3V rms(max)
(VREF)'
OUTPUT WITH RECOMMENDED
ANALOG INPUT
6.8Vnns
7 .07V rms(max)
GAIN (VREplO Vo)
2±O.1%
GAIN TEMPERATURE
COEFFICIENT
25ppmI"C (max)
ANALOG INPUT (V...)
FREQUENCYRANGE
dcto2.6kHz
ANALOG INPUT IMPEDANCE
1O.2k!l
ANALOG OUTPUT IMPEDANCE
O.2m!lmax
OUTPUT OFFSET VOLTAGE
2SmV(max)
OUTPUT OFFSET VOLTAGE DRIFT
50~VI"C(msx)
OUTPUT DRIVE CAPABILITY
2VA (max mean)
PHASE SHIFT (VREF to Yo)
0.08"@!400Hz
+
OUTPUT PROTECTION
Overvoltage
Overcurrem
377mApeak@JIO.6Vpeak
TransZorb(optional)
± 12V standoff. ± ISV clamp
Limitset@SSOmApeak.(Casebeader
mustbemaintained@125OCmax).
RESPONSE TO A STEP INPUT
20fL5 (max) to within accuracy ofconverter.
Any size digital step input.
VECTOR ACCURACY
Radius Error z
0.03%
Angular Error
+20r ±4arc-minutes
POWER SUPPLY (NO LOAD)"'"
LS Latch Options
+ 15 Volts
-15 Volts
+ 15(P) Volts
CMOS Latch Options
Additional Current
(Load Dependent)
-15(P)Volts
+5Volts
+lSVolls
-ISVolts
+ 15(P)Volts
-15(P)Volt.
+ 15(P) Volts
-15(P)Volt.
15rnA(typ)22rnA(max)
15mA(IYP)22mA(max)
20mA (IYP) 34mA (max)
20mA (IYP) 34mA (max)
44mA (IYP) 72mA (max)
24mA (IYP) 30mA (max)
ISmA(typ)22mA(max)
2OmA(typ) 34mA (max)
20mA (typ) 34mA (max)
400mA Peak (max)
400mA Peak (max)
PULSATING POWER SUPPLY
PEDESTAL
3V de (min)
POWER DISSIPATION
See Power Dissipation section ohhis data sheet.
CASE TEMPERATURE RANGE'
- 55°C to + 125°C Operating
SIZE
40-Pin DIL 1.14x 2.14xO.18~
WEIGHT
O.90z(2Sgrams)
-6S Cto
0
+ 150°C Storage
(29.0 x 54.4 x 4.6mm)
NOTES
IVRE" is internally clamped to 1: ISV power supplies. Input current should not exceed lOrnA.
lWont case error over operatinl! temperature range.
~The + S volt power supply must never go more than O.3V below GND potential.
"Correct polariry voJtages must be maimained on the ± ISV Ind the :t ISV(P) pins.
sTracking of The ± ISV and.:!: IS(P) supplies mUST be maintained.
6Adequate heat sinking must be provided to keep the case temperature Iess than lZS"C.
*Specifications same as DRCI74S.
Specifications subject to chanse without norke,
DRC1746
16 Bits
. _m.33 arc-minutes
·
··
·
·
··
···
··
··
*
·
··
···
··
·
···
··
·
··
··
Ilofereftc:el_
Transformer
STM168OiSTMl6450
Output
Transformer
STMl683iSTMl663
11.8,26,IISVnns
6.8Vrms
depending on option
OUTPUT VOLTAGES
OUTPUT FORMAT
RHhRLO
Sin,Cos
3.4Vrms ± 1%
11.8,26,90Vrms ±5%
AHhALO
SI,S2,S3,(84)
N/A
Synchro or resolver
.k:pcndingonoption
FREQUENCY RANGE
STM1680
STMl660
STM1683
STMl663
3601b-2.6kHz
47H;o-44()Hz
3601b-2.6kHz
47H;o-44()Hz
INPUT IMPEDANCE
11.8Vlnput
26VInput
115Vlnput
ACCURACY
O.lVALoad
1.4VALoad
2.0VALoad
TemperatureCoefi1cient
SOkO(min)
3Okll(min)
SOOk!l(min)
N/A
N/A
N/A
± 1.0arc:-min(max)
N/A
N/A
N/A
N/A
±2.0arc-min(max.)
± 3.0arc-min (max)
N/A
N/A
N/A
2.90 (typ)
13.60 (IYP)
1560 (IYP)
lOOOV
lOOOV
±O.02arc-minI"C(max)
OUTPUT IMPEDANCE
11.8VOutput
26VOutput
9OVOutput
DC ISOLATION
Voltage
SIZE
STM1680
1.12x 1.12 x 0.4"
(28.5 x 28.5 x 1O.2mm)
l.12x Ll2x 1.0'"
(28.5 x 28.5 x 25.4mm)
STM1660
STM1683
2.25xl.12xO.4"
(57.1 x28.5 x 1O.2mm)
2.25x 1.12 x 1.0"
(57.1 x28.5 x 25.4mm)
STMl663
TEMPERATURE RANGE
()pe S1
,
~~~~~~_~_~_-_~,~~~P~ISINORC~)
,,
~
I
COSt--......-~
It JLdl
L.L_-......-_-_-:.-_-_-_-_-_J...'----' -.J
)-i-'- - - 0 S3
-------000 54
DRCI74511746
:}-----oS2
at
SJOGND
NO PROTECnDN
}-----oR.,
Figure 8. DRC17451DRC1746 Output Stage Showing
TransZorb Protection
)-----oR,o
NOTE: FOR SYNCHRO OUTPUT "CT" MUST BE CONNECTED TO "Te".
FOR RESOLVER OUTPUT ''Te'' IS 54 (NO LlNKl
OUTPUT CURRENT
Figure 10. Connecting the DRC1745 to the STM1680 and
STM1683 Transformers
POWER SUPPLY
INTERRUPTED
V CLAMP
f - -....---::.-",
.- .-
TRANSZORB CLAMPLEVEL
TRANSZORB EXTINGUISHED
~
_~ VOLTAGE WHICH WOULD HAVE EXISTED
/ r-
WITHOUT TRANSZORB PROTECTION
/
I
I
v/
I
Figure 9. Transient Waveforms and TransZorb Clamping
In addition, there are conventional diode cIamps on the ± 15V(P)
power supplies.
OUTPUT AND REFERENCE TRANSFORMERS
A set of low profile (0.4" high) reference and output transformers
(which are capable of handling the full drive capability of the
DRC1745 and DRC1746 over a frequency range of 360Hz to
2.6kHz) are available in order to accept the standard voltage
formats of synchros and resolvers.
volts rms in order to provide a full scale analog output. The
maximum output voltage of the converter is proportional to the
input voltage (gain of 2) and therefore the resistor tolerance
should be chosen so that the correct voltage appears across the
AHI , ALO pins. Note that the input to the reference transformer
should not exceed the rated max.
Note that the best de output offset performance is achieved
when the STM1680/STM166O transformer is used. However the
use of resistive scaling can never cause an additional offset of
greater than 6.5mV (max), 2.6mV (typ).
OTHER PRODUCTS
We manufacture a wide range of hybrid and modular circuits
for processing synchro and resolver information. Please ask for
our comprehensive literature.
PROCESSING FOR HIGH RELIABILITY
The reference transformer, STM1680, can accept voltages of
11.8 volts, 26 volts or 115 volts depending on the option and its
output is 3.4 volts rms which is suitable for connecting to AHI
and ALO on the converter.
STANDARD PROCESSING
As part of the standard manufacturing procedure, all converters
receive the following processing:
The output transformer pair, STM1683, accepts the 6.8 volts
rms output of the converter and provides a synchro or resolver
format depending on the option.
1. Pre-Cap Visual Inspection
In-House Criteria
2. Constant Acceleration
3000g
Note: For resolver option for the STM1683 transformer, part
number is RTM1683.
The pin out and dimensions of the STM1680 and STM1683 are
shown on the next page, and the connection to the converter in
Figure 10.
Note: For operation over the frequency range 47Hz to 440Hz a
similar set of transformers are available (1.0" profile height).
Part numbers are STMl660 (reference transformer) and
STM1663 (output transformer).
RESISTIVE INPUT SCALING
The analog reference input can be externally resistively scaled to
cater for a wide range of voltage both when used with or without
the reference transformer, STM1680/STM166O.
When the converters are used with the STM1680/STMl660
transformer, a resistance of value 3k.O per extra volt required
should be inserted in the AHI line. Care should be taken to
ensure that the voltage on the analog input (AHI , ALO) is 3.4
PROCESS
CONDmONS
3. Bum-In
160 hrs. at 125°C
4. Gross Leak Test
In-House Criteria
5. Final Electrial Test
Performed at 25°C
HI-REL PROCESSING
Ail models ordered to high reliability requirements will be identified with a B suffix, and will have received the following
processing:
1.
2.
3.
4.
5.
6.
7.
8.
Internal visual inspection
Stabilization bake, 24 hours at 150°C
Temperature cycling, -65°C to + 15O"C
Constant acceleration, 3000g
Powered bum-in, 160 hours at 125°C
Final electrical test at T MIN and T MAX
Seat test, fme and gross
External visual inspection
SYNCHRO & RESOLVER CONVERTERS 5-13
II
OUTLINE DIMENSIONS
PACKAGING SPECIFICATIONS
Dimensions shown in inches and (mm).
STM1683/STM1663
STM1680/STMl660
r3~'~ ~
T-!
0,875
(22..231
1.,.
_yov
0.12313.12)
r
STM1680
Il=~
OPTIONMARIC.£O
IN THIS POSITION
/
I
-0,
.L
:;A-
I
,
0'
•..,.
'!.'~!\!'-A ..i ••"
L ____ J 2VOYT
T
FIXING _
T
'I
::.
I
l--O.799120.291~
0.437
(11." I
.
.0
'0
SIG GNO lei
0.123 (3.12)
DEVICES
83.'
0
• 437
DPT"'N
0
I
.
o
I
12.361
-
•
I
.1
I
-@,
o
0
• 0
7
"''''
L_-O-
I
c::{ -..1
2.016151.211
I
~;~:ED
CTri- •
1.923 (48.141
l
t-~
,
SIG GNO \S)
STM1683
I
T 1:----:
I---
1
SIN
ClANALOG
_oT<:'
.12.361
1.120
'0
2.000(&q.80I~.
.
1.125128.581---:----f
~~fi1-1r-;-__._._".;.I22_'.;.31_----I_-I+-+_
' ______.;."
-<>
...
1
J J
0
I
1---0 .892122.181
M2)CO.25!6.35IDEEp
(6 FULL THREADS
~
1---0.875122.231---1
1.120
"uS!
RXING IN 2: P08moN
M2xUS 16.351 DEEP
(6 FULL THMADSI
,
o
! - - , . , 2 0 128.451----1 BOTTOM VIEW
,
0
~
1
I
1-------2.245157.021--------1
BOTTOM VIEW
NOTES
1.
"rc" READS "54" .net "cr READS "He" ON RESOLVER DEVICE IRTMl883l.
2. OIMENSION "A" IS 0•• t1D.21 FOR STM1180 AND STM11183. ANO 1.0 125.4) FOR STM 1lIII0 AM) 8rM 1113.
THE TOlERANCES ARE +0.010". -0.008" OR +O.25mm, -0.13mm.
r
ORDERING INFORMATION
DRC1745/1746
DRCI745/LT4IB
".,-,."'-~
-.J
1746 = I6-Bit Resolution
L = Low power Schottky
~==-.
reqwred.
2 = ± 2 Arc·Mins Accuracy
4 = ± 4 Arc·Mins Accuracy
input latches
T = Internal TrBDSZorb protection
C = CMOS input latches
o
= Without TransZorb protection
STMI68O.A
1680 =
1-1.-------
1
36OHZ-2'6kHz-I~A = 26V
(26V reference, synchro)
A = 115V (1I5V reference, synchro)
A = IIV8 (1I.8V reference, redver)
~
1660 = 47Hz-440Hz
2, 1 4 0 1 5 4 . 4 1 - - - - - -..
- BOTTOM VIEW
A = 26V (26V reference, resolver)
·PINS 15 & 16 ARE NOT CONNECTED INIC) ON DAC174S.
PIN 31 IS "N!C" ON "C" OPTION AND "+5V"
STMI683.4YZ
ON "L" OPTION.
TOLERANCES ±O.OOS"(1.3)
UNLESS OTHERWISE STATED
STMforsynchr0j
output options
RTM for resolver
outpUt options
1683 = 360Hz - 2.6kHz
1663 = 47Hz - 440Hz
5-14 SYNCHRO & RESOLVER CONVERTERS
~ZZ = 2I (90V
(1I.8Vnussynchrooutput)
rms synchro output)
=
Z = 3 (1I.8V nus resolver output)
Z = 4 (26V nns resolver output)
Z = 8 (I I.8V nus resolver output)
Y = 1360Hz to 2.6kHz (STM1683 only)
Y = 247Hz to 440Hz (STMI663 only)
4 = - 55"C to + 125"C operating
temperature range.
~ANALOG
WDEVICES
Hybrid Inductosyn Preamplifier
IPA1764 I
FEATURES
Hybrid Construction
Phase Shift <5·
Phase Match <1·
Load Capacity 10,OOOpF
Full Military Temperature Range
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
... ANALOG
WDEVICES
IPA1764
APPLICATIONS
The IPA1764 is recommended for use with the
1S10/20, 1S14/24 and other 10- and 12-bit
Inductosyn*IResolver-to-Digital Converters.
GENERAL DESCRIPTION
The output signals from an Inductosyn slider are at a low level
of the order millivolts and require amplification and buffering
before transmission to an Inductosyn-to-digital converter. The
IPAI764 provides the necessary gain and output impedance for
this purpose.
•
~1111111I11
0.112.541
_I
1_
11
1
~O.8 (20.32,--1
PIN ONE (GREEN GLASS BEAD)
Any gain mismatch in the two channels amplifying the sine and
cosine outputs of the Inductosyn slider contributes to the system
error. The IPA I 764 with a 0.15% gain match over the temperature
range only contributes an error of 0.23 micron using a 2mm
pitch Inductosyn. By carefully controlling phase mismatch to
less than 1°, the error contribution is only 0.2 micron in a 2mm
pitch Inductosyn.
oo
o o ~o o1o
o 0 T :ALL UNMARKED PINS
+~ I
!;+
8
>
;
~
T
~
-ur-
>
..
~
7 8
~~~:,g,~~RNAL
0.77.
~
~11.''''1
~
000000000
I---
0.975 (24.785)----1
The IPAI764 with an output resistance of less than 3 ohms and
a capability of driving a cable capacity of 1O,OOOpF is totally
suited to machine tool applications where the Inductosyn-to-digital
converter is remote from the measuring Inductosyn.
The IPAI764 is of hybrid manufacturing techniques, and available
in two temperature range versions-industrial temperature range
(0 to + 70°C) and extended temperature range ( - 55°C to
+ 125°C).
ORDERING INFORMATION
Both versions of the IPAI764 are housed in an IS-pin metal
case.
IPAl764
APPLICATION
The diagram below shows a "hookup" with the preamplifier,
power oscillator and a IS60 with an Inductosyn. Precise application
information is not possible as the Inductosyn in its application
has many variables.
Current Set Resistor
This resistor is used to match the voltage output of the oscillator
to the Inductosyn track resistance and provide the manufacturer's
recommended current. By variation of the voltage outputs and
current resistance, track by this up to approximately 10 feet (3
meters) can be accommodated.
DecoupJing
The preamplifier and oscillator have internal high frequency
decoupling capacitors on the supply lines, however, it is recommended that electrolytic decoupJing capacitors are connected
close to the hybrid pins.
x
60
B
L_ . . bili~_
X=5
o to
X=4
- 55°C to + 125°C
Operating Temperature Range
+70°C
Operating Temperature Range
*lDduetosyn is a registered trademark of Farrand IDdustries, IDe.
SYNCHRO & RESOLVER CONVERTERS 5-15
SPEC IFI CATI0NS
!tJpicaI @
+ 25"C 0181' full range of power supply _
unless otII8Iwis8 noI8d)
Model
IPA17641S60
IPA17641460
GAIN
12S0 ±S%
*
GAIN MISMATCH
Channel to Channel Over
Full Temperature Range
±O.IS%(equivalent
t02.Sarcmins)
±0.3%
PHASESIDFT
= load phase angle
NOTE: Although the power amplifier stage has internal shon
circuit protection, a heat sink should be employed for protection
against continuous shon circuit conditions.
Inductosyn® is a registered trademark of Farrand Industries, Inc.
SYNCHRO & RESOLVER CONVERTERS 5-17
•
SPECIFICATIONS
(typical @ +25"& with ±15Y power supplies unless otherwise noted)
Model
OSC17S81SOO
OSC17S81400
FREQUENCY RANGE
FREQUENCY STABILITYl,z
REFERENCE 1 OUTPUT l
O-lOkHz
*
*
*
REFERENCE 2 OUTPUT l
2.SVrms ±S%@3mArms
90' Phase Advanced with Respect to
Ref. 1 Output
AMPLIFIER OUTPUT3
7Vrms@21SmAmax
CAPAcmVE LOAD
AMPLIFIER GAIN l
2.8 ±l%
±S%
2.SVrms ±S%@3mArms
*
*
*
*
*
*
*
*
lOnF(max)
AMPLIFIER INPUT RESISTANCE
S.3SkO ±l%
POWER DISSIPATION
4.0 Watts (max)
POWER SUPPLy4
±lSV
60mA (max) No Load
160mA (max) Full Load
TEMPERATURE RANGE
Operating
Storage
Oto +70'C
-6S"Cto + lSO'C
SIZE
0.975" x 0.775" x 0.175"
(24.8mmx 19.7mmx 4.Smm)
WEIGHT
0.2Sozs.
7 grams
- SS"C to + 12S'C
*
*
*
NOTES
lOver fuJI operating temperature range.
2See section on "Stability".
'Derated to SV rms @ 2lSmA if using ± 12 volt power supply.
.
VI is multiplied by COS and V2 is multiplied by SIN to give:
K Eo sin wt sin 0 cos
and K Eo sin wt cos 0 sin <1>.
These signals are subtracted by the error amplifier to give:
K Eo sin wt (sin 0 cos -cos 0 sin <1»
or K Eo sin wt sin (0-<1».
A phase sensitive detector, integrator and voltage controlled
oscillator (VCO) form a closed loop system which seeks to null
sin (0-<1». The digital output (counter <1», then represents the
synchro/resolver shaft angle e within the specified accuracy of
the converter.
INHIBIT INPUT
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a busy pulse to refresh the
output data.
ENABLE INPUTS
The ENABLE inputs determine the state of the output data. A
Logic High maintains the output data pins in the high impedance condition, and application of a Logic Low presents the
data in the latches to the output pins. ENABLE M enables the
most significant 8 bits, while ENABLE L, enables the least significant 4 bits (6 bits in the SDClRDCI740). The operation of
the ENABLE inputs has no effect on the conversion process.
DATA TRANSFER
Data transfer can be accomplished using either the INHIBIT
input or the trailing edge, positive to negative transition of the
BUSY pulse output.
The data will be valid 640ns after the application of a Logic Lo
to the INHIBIT input. This is regardless of the time when the
INHIBIT is applied and allows time for an active busy pulse to
clear. By using the ENABLE M and ENABLE L inputs the
two bytes of data can be transferred after which the INHIBIT
should be returned to a Logic Hi state to enable the output
latches to be updated.
I..
BUSY
---1
600n. MAX
200n5 MIN
.....I
...I
MAX DEPENDS ON
INPUT RATE
r---------,~
~~·~~~r
DATA
~---------VA-L-ID----------:><:~____V_A_Ll_D__
Figure 2. Timing Diagram
SYNCHRO & RESOL VER CONVERTERS 5-23
BUSY OUTPUT
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL levels. A BUSY is initiated each time the input moves by
an analog equivalent of an LSB and the internal counter is
incremented or decremented or the INHIBIT input is released.
in series with RHI. In the case of a resolver-to-digital converter,
add 2.22kO in series with S1 and S2 per extra volt of signal and
lkO per extra volt of reference in series with RHI.
DYNAMIC PERFORMANCE
The transfer function 'of the converter is given below.
Typically the width of the BUSY pulse is 400ns during the position data output updates. The trailing edge, positive to negative
transition, of the BUSY pulse indicates that the position data
output has been updated and is ready for transfer (data valid).
The maximum load on the BUSY output using the trailing edge
of the BUSY pulse is 2 TTL loads.
1+ ST1
1 + 8T2
Figure 3. Transfer Function of
SDCIRDC17401174111742
CONNECTING THE CONVERTER
The power supply voltages connected to + Vsand - Vspins
should be ±15V and must not be reversed. The digital logic
supply VL is connected to +5V.
It is suggested that a parallel combination of a O.lIl-F ceramic
and a 6.81l-F electrolytic capacitor is placed from each of the
r..hJ'ee supply pins to G~-lD.
Open loop gain:
OOUT
K. I+ST]
6iN = ST· 1+:;12
The pin marked CASE is connected electrically to the case
and should be taken to a convenient zero volt potential in the
system.
Closed loop gain:
OOUT
OIN
1
=
+ ST]
S2
S3T2
1 + STI + K; + -x;
The digital output is taken from Pin 1 through to Pin 12 for
the SDClRDC174111742 and Pin 1 through to Pin 14 for the
SDClRDC1740 where Pin 1 is the MSB.
Model SDClRDC1740
The reference connections are made to REF HI and REF LO.
In the case of a synchro, the signals are connected to S1, S2 and
S3 according to the following convention:
Where K.=56,000
Tl=O.OI
T2=0.001525
ESI-S3=ERLO-RHI sin wt sin 0
K,
s·
The gain and phase diagrams are shown in Figures 4 and 5.
ES3_S2=ERLO_RHI sin wt sin (0+ 120°)
Model SDClRDC174111742
ES2-SI=ERLO_RHI sin wt sin (0+240°)
Where K.=80,000
Tl=0.0087
T2=0.001569
For a resolver, the signals are connected to SI, S2, S3 and S4
according to the following convention:
Es I-S3 = ERLO_RHI sin wt sin 0
ESZ-S4=ERHI-RLO sin wt cos 0
The BUSY, INHIBIT and ""E""'N'""'"A=B";""L=E pins should be connected
as described under the heading Data Transfer.
RESISTIVE SCALING OF INPUTS
A feature of these converters is that the signal and reference
inputs can be resistively scaled to accommodate any change of
input signal and reference voltages_
This means that a standard converter can be used with a personality card in systems where a wide range of input and reference
voltages are encountered.
Note: The accuracy of the converter will be affected by the
matching accuracies of resistors used for external scaling.
To calculate the values of the external scaling resistors in the
case of a synchro converter, add 1.1lkO per extra volt of signal
in series with SI, S2 and S3 and lkO per extra volt of reference
~24
SYNCHRO & RESOLVER CONVERTERS
The gain and phase diagrams are shown in Figures 6 and 7.
ACCELERATION ERROR
A tracking converter employing a type 2 servo loop does not
suffer any velocity lag, however, there is an additional error due
to acceleration. This additional error can be defined using the
acceleration constant K. of the converter.
K _ Input Acceleration
• - Error lD Output Angle
The numerator and denominator have the same units. K. does
not define maximum acceleration, only the error due to acceleration, maximum acceleration is in the region of 5 times the K.
figure. The following is an example using the K. of the
SDCI74O.
Acceleration of 50 revolutions sec- 2 with K.=56000
.
50x 16384
Error lD LSBs = 56000 = 14.62LSBs
SDC/RDC1740/1741/1742
4
4
--
2
/"
"\
/'
2
m
\
\
\
\
-2
25
50
~
~
"Z
I
-3
-4
12.5
~
,
-2
-3
\
-4
100
200
25
12.5
180
135
135
90
90
----
0
I
.,«w
...
-45
:I:
-90
~
~I
:ll
~
-135
-180
12.5
50
25
f
.......
100
---
200
Figure 5. SDClRDC1740 Phase Plot
128
"
a:
~
>64
32
25
40
200
---
45
---
0
-45
r--
~
-135
-180
12.5
25
50
,
~
100
200
FREQUENCY - Hz
Figure 7. SDCIRDC174111742 Phase Plot
~
., 96
100
II
-90
...........
FREQUENCY - Hz
160
50
FREQUENCY - Hz
Figure 6. SDCIRDC174111742 Gain Plot
180
45
"'"
\
\
\
\
C
Figure 4. SDCIRDC1740 Gain Plot
Q
\
Cl -1
FREQUENCY - Hz
::l!!
./
RELIABILITY
'" '"
55
The reliability of these products is very high due to the extensive use of custom chip circuits that decrease the active component count. Calculations of the MTBF figure under various
environmental conditions are available on request.
r-......
70
-i'----85
100
As an example of the Mean Time Between Failures (MTBF)
calculated according to MIL-HDBK-217E, Figure 8 shows the
MTBF in years versus case temperature in naval sheltered conditions for SDClRDC1740/41142.
125
TEMPERATURE -'C
Figure 8. SDCIRDC1740141142 MTBF Curve
SYNCHRO & RESOL VER CONVERTERS 5-25
STANDARD PROCESSING (SYZ OPTION)
As part of the standard manufacturing procedure, all converters
receive the following processing:
Process
Conditions
I .. Preseal Burn In
64 hrs at + 125·C
2. Precap Visual Inspection
In-house criteria
3. Seal Test, Fine and Gross In-house criteria
4. Final Electrical Test
Performed at + 2S·C
Extended temperature range versions receive additional
processing as follows:
Final Electrical Test
Performed at max and min
operating temperatures
The SDCIRDC1767 and SDClRDC1768 are hybrid synchroto-digital converters with isolating microtransformers similar
to the SDClRDC1740/41142 described on this data sheet with
the additional features of analog velocity output and dc error
output.
The OSC1758 is a hybrid sine/cosine power oscillator which can
provide a maximum power output of 1.5 watts, over a frequency
range of 0 to 10kHz.
PROCESSING FOR HIGH RELIABILITY
Process
1. Preseal Burn In
2. Precap Visual Inspection
3. Temperature Cycling
4. Constant Acceleration
S. Interim Electrical Tests
6. Operating Burn In
7. Seal Test, Fine and Gross
8. Final Electrical Testing
(Group A)
9. External Visual Inspection
OTHER PRODUCTS
Many other hybrid products concerned with the conversion of
synchro data are manufactured by Analog Devices, some of
which are listed below. If you have any questions about our
products or require advice about their use for a particular application, please contact our Applications Engineering Department.
Conditions
64 hrs at + l2S·C
2017
10 Cycles, -6S·C to + IS0·C
SOOOG, YI Plane
The DRC1745 and DRC1746 are 14- and l6-bit natural binary
latched output hybrid digital-to-resolver converters. The accuracies available are ±2 and ±4 arc mins, and the outputs can supply 2VA at 7V rms.
96 hours @ +125°C
1014
Performed at T min' T ambient
and Tmax
2009
NOTE
Test and screening data can be supplied. Further information on request.
ORDERING INFORMATION
For full definition, the converter part number should be suffixed by an option code. All the standard options and their
option codes are shown below. For options not shown, please
consult Analog Devices.
L
J
SDC
SDC~ S""","-~D;,i,,"
174A X
Y Z B
"L-
am_,
RDC=Resolver-to-Digital Converter
1740= l4-Bit Resolution, ±5.3 arc min Accuracy
1741= l2-Bit Resolution, ± 15.3 arc min Accuracy
1742= 12-Bit Resolution, ±8.S arc min Acc\lracy
Z=1
Z=2
Z=3
Z=4
Z=8
Hlgh-Rcl"""',"",
Signal 11.8V Reference
Signal
90V Reference
Signal 11.8V Reference
Signal
26V Reference
Signal 11.8V Reference
26V
llSV
11.8V
26V
26V
Synchro
Synchro
Resolver
Resolver
Resolver
Y = 1400Hz Reference Frequency
Y=4 2.6kHz Reference Frequency
X=4 -ss·e to + l2Soe Operating Temperature Range
X=S 0 to +70°C Operating Temperature Range
5-26 SYNCHRO & RESOL VER CONVERTERS
rIIIANALOG
WDEVICES
FEATURES
4O-Pin Hybrid
Tachogenerator Velocity Output
DC Error Output
Sub LSB Output
Angle Offset Input
Reference Frequency of 2kHz to 10kHz
Logic Outputs for Extension Pitch Counter
Tachogenerator Output, Hybrid
Resolver-to-Digital Converters
1S14/1 S24/1 S44/1 S64 I
IS14/IS24/1S44/1S64 FUNCTIONAL BLOCK DIAGRAM
"
E. . . .
ANGLE
OffSET INPUT
APPLlCAnONS
Numerical Control of Machine Tools
Feed Forward Velocity Stabilizing Loops
Robotics
Closed Loop Motor Drives
Brushless Tachometry
Single Board Controllers
GENERAL DESCRIPTION
The ISN4* are hybrid devices that convert standard resolver
inputs to digital position and analog velocity outputs. All the
essential features for multiturn or multipitch operation are included
for numerically controlled machine tool and velocity feedback
applications.
Typically the input signals would be obtained from a brushless
resolver and the resolver/converter combination gives a parallel
absolute angular output word similar to that provided by an
absolute encoder. The ratiometric conversion principle of the
ISN4 ensures high noise immunity and tolerance of lead length
when the converter is at a distance from the resolver.
The output word is in three-state digital logic form with a high
and low byte enable input so that the converter can communicate
with an 8- or 16-bit digital highway.
A unique feature of the converter is its internally generated
tachogenerator velocity output offering a linear voltage-speed
relationship. Ouly one external resistor is required to scale the
velocity output to the users chosen volts/rpm relationship.
Repeatability is ILSB under constant temperature conditions.
Four resolutions are available all operating over a frequency
range of 2kHz to 10kHz.
ISI4 is
IS24 is
1844 is
IS64 is
IO-bit up
12-bit up
14-bit up
16-bit up
to
to
to
to
~-. . . ._~
VELOCITY
INTERLSB
'------~OUTPUT
~""~-----~~
DIGITAL ANGLE
~,
APPLICATIONS
The I SN4 has been specifically designed for motor position
control for the numerically controlled machine and robot industry,
using the type 2 servo loop tracking principle that ideally suits
these converters to the electrically noisy environment found in
these industrial applications.
USER BENEFITS
Allows both velocity and position measurement from a single,
low cost, standard, brushless resolver.
80dB dynamic range of velocity output.
0.5% ripple on velocity signal.
0.1% linearity of velocity signal.
Cost effective tachogenerator replacement.
Tracks at 5 to 10 times the rate of equivalent resolution
encoders.
Analog output for interpOlation between digital codes.
Direction and Ripple Qock (Datum) outputs facilitate revolution
counting.
Hybrid construction offering small size and MTBF of >200
years at 50'C GB.
40,800 revolutions per minute.
10,200 revolutions per minute.
2,550 revolutions per minute.
630 revolutions per minute.
*N is I, 2, 4 or 6 depending upon resolution of model.
SYNCHRO & RESOL VER CONVERTERS 5-27
II
for both commercial (5YO) and extended (4YO) temperature range options
SPECIFICATIONS (typical
± 15V or ± 12V power supplies, unless otherwise noted)
._ten
@ 25"& and
Models
RESOLVERINPUTS
Signal Voltage
Reference Voltage
Signal & Reference Frequency
Signal Input Impedance
Reference Input Impedance
Allowable Phase Shift
(Signal to Reference)
POSmONOUTPUT
Resolution
lLSB
Accuracy (max error
over temp. rsuge)
5YO
4YO
Digital Position Output Format
Load
Monotooicity
Repeatability
DATA TRANSFER
Busy Output
Load
Busy Width
ENABLE Inputs
Losd
Enable & Disable Times
INHIBIT Input
Load
Direction Output (D1R)
Losd
Ripple Qock (RC)
Load
Width
DYNAMIC CHARACTERISTICS
Tracking Rate (min)
with ± 15V supplies
with ± 12V supplies
Acceleration Constant
Ka
Sett1ing time (179" step input)
Bandwidth
VELOCITY OUTPUT
Polarity
Tachogenerator Voltage Scaling
Scale Factor Accuracy
Scale FactorTempco
Reversion Error
Reversion Error Tempco
Linearity
Over full temp rsuge
Ripple and Noise
SteadyState@IOkHz(200Hzb/w)
Dynamic Ripple (av-pk)
ZeroOffaet
Zero Offset Tempco
Output Load
~28 SYNCHRO
1814
1814
1844
ISM
UIlitB
2.0±50/0
2.0 + 500/01- 200/0
2k-l0k
100min)
125
*
*
*
*
*
*
*
*
*
•
Vrms
Vrms
Hz
MO
kO
±10
*
•
•
*
*
*
*
•
Degrees
10
0.35
±25.0(0.42)
±0.12
± 25.0 (0.42)
±0.012
Parallel natural binary
6 (max)
12
0.088
±8.5(0.14)
±0.04
±8.5(0.14)
±0.04
14
0.022
±5.3(0.09)
±0.025
±5.3(0.09)
±0.025
16
0.0055
±4.0(0.07)
±0.019
±2.6(0.04)
±0.012
Bits
Degrees
Arc-mins(degrees)
%F.S.
Arc-mins (degrees)
%F.S.
•
•
..•
*
*
*
*
*
Logic "Hi" when Busy
6 (max)
380 (min) 530 (max)
Logic "Lo" to Enable
1
250 (max)
Logic "Lo" to Inhibit
1
Logic "Hi" when counting up,
Logic "Lo" when counting down.
6 (max)
Negative pulse indicating when
internal counters change from all
"J's" to all "O's" or vice versa.
6 (max)
1f.L{max) 85On(min)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
•
*
*
*
*
LSTTL
*
*
*
*
*
*
*
*
*
LSTTL
Sees
40,800
10,200
8,670
2,550
2,168
630
536
rpm
rpm
*
*
*
*
*
*
See-2
ms
Hz
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Guaranteed
34,680
220,000
25 (max)
230
Positive for incressing angle
0.25
±1(max)
200 (max)
±0.2(max)
50 (max)
0.1
0.25 (max)
100
0.5 (max)
±500
50 (max)
S(min)
& RESOLVER CONVERTERS
35 (max)
•
60 (max)
4
*
•
120 (max)
16
150
300
1300
*
*
*
*
*
*
*
*
*
*
*
*
LSTfL
LSB
LSTTL
ns
LSTfL
ns
LSTfL
V/Krpm
% of output
ppmI"C
%
ppmI"C
% ofoutput
% of output
!LVrms
% of output
!LV
",V/"C
kO
lS14/1S24/1S44/1S64
Models
Parameters
SPECIAL FUNCTIONS
DC Error Output Voltage
Intet LSB Output
Load
Angle Offset Input (ovet
operating temperature range)
Maximum Input
1514
1524
1544
1564
Units
450
±1(±20%)
I (min)
*
*
*
*
*
*
*
*
*
mY/degree
VILSB
kO
320(± 10%)
32
*
*
*
*
*
*
nAlLSB
LSB
*
•
Vdc
Vdc
POWER REQUIREMENTS
Power Supplies
±Vs
+5V
Power Supply Consumption
±Vs
+5V
Power Dissipation
± l5(±5%)or ± l2(±5%)
+4.75 to +5.25
*
*
•
30 (max)
125 (max)
1.5 (max)
*
*
*
*
*
*
TEMPERATURE RANGE
Operating 5YOoption
4YOoption
Storage 5YOoption
4YOoption
Oto +70
-55to +125
-55to + 125
-60 to +150
•
•
•
*
*
•
•
•
•
•
•
DIMENSIONS
5YOoption
4YOoption
2.1" xU" xO.195(5.3 x 28 x 4.95)
2.14"x 1.14"xO.18(54.4x29 x 4.6)
•
•
WEIGHT
1(28)
*
•
•
•
*
•
*
•
•
•
mA
mA
W
'c
'c
'c
'c
Inches(mm)
Inches(mm)
oz.(grms)
NOTES
·Specificarionssameas IS14.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM INPUTS (with respect to GND)
+Vs·
-VS· ..
+SV2 ••
Reference
Sine . . .
Cosine . .
Any Logical Input
OVto +l7Vdc
OVto -l7Vde
OV to + 6.0V de
:t17V de
:t 17V de
:t 17V de
-OAV to +S.SV de
CAUTION:
1. Correct polarity voltages must be maintained on the + Vs and
-Vs pins.
2. The + 5 volt power supply must neoer go below GND
potential.
SYNCHRO & RESOL VER CONVERTERS 5-29
OPERATION OF THE CONVERTER
The ISN4 are tracking converters, this means that the outpUt
automatically follows the input for speeds up to the maximum
tracking rate for the resolution option. No convert command is
necessary as the conversion is initiated by each LSB increment
for the input. Each LSB increment of the converter initiates a
BUSY pulse.
POsmON OUTPUT
The resolver shaft position is represented at the converter output
by a natural binary parallel digital word.
The static angular accuracy quoted for each converter type is
the worst case error that can occur over the full operating temperature range with the following input conditions:
a) Signal input amplitudes within 5% of the nominal values.
b) Signal and reference frequency within the specified opersting
range.
c) Phase shift between signal and reference less than 10 degrees.
d) Signal and reference waveform harmonic distortion less than
10 percent.
These test conditions are selected pdma.....iJy to establish a repeatable
acceptance test procedure which can be traced to national standards. In practice the converters can be used well outside these
operating conditions providing the following points are
observed:
Signal Amplitude (Sine and Cosine Inputs)
The amplitude of the signal inputs should be maintained within
5% of the nominal values if full performance is required from
the analog outputs and inputs of the converter such as velocity,
inter LSB position and angle offset.
Signal and Reference Frequency
Any frequency within the specified range of the converter may
be used. It should be noted that the same frequency must be
used on both inputs.
Reference Voltage Level
The amplitude of the reference signal applied to the converter's
input is very uncritical, however it is essential that the zero
crossing points are maintained in the correct place to drive the
converter's phase sensitive detector.
Harmonic Distortion
The amount of harmonic distortion allowable on the signal and
reference lines mainly depends on the type of transducer being
used.
Square and triangle waveforms can be used but the input levels
should be adjusted so that the average value after rectification is
1.9 volts. (For example - a square wave should be 1.9V peak).
Note: The figure specified of 10% harmonic distortion is for
calibration convenience only.
Phase Shift (Between Signal and Reference)
See Section on "Dyn-amic ACC"..L.'"acy ,\'s. Resolver Phase Shift".
DATA TRANSFER
BUSY Output:
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses of
TTL levels. A BUSY pulse is initiated each time the input
moves by the analog equivalent of an LSB and the internal
counter is incremented or decremented.
The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a dramatic loss in accuracy due to internal overload.
Reducing level will result in a steady decline in accuracy. With
the signal levels at 50% of the correct value, the angular error
will increase to an amount equivalent to 1.3LSB. At this level
the repeatability will also degrade to 2LSB and the dynamic
response will also change, since the factor Ka is proportional to
signal level.
INHIBIT Input:
PIN CONNECTIONS
ENABLE Inputs:
Two ENABLE inputs are provided, ENABLE M for the most
significant 8-bits and ENABLE L for the least significant remainder. These ENABLES determine the state of the output
data. A TTL logic "Hi" maintains the output data pins in a
high impedance condition, the application of a logic "Lo" presents
the data in the latches to the output pins. The operation of
these ENABLES has no effect on the conversion process.
12
0
PINtO
13
n
0
0
0
0
14
0
0
0
0
0
0
0
0
10
9
8
7
6
BOTIOM VIEW
15
16
NIC
N/c
iNH
so
o
BUSV
4
3
0
0
0
o
2
0
o
RUT
VEL
ANGLE OFFSET
GND REF
,
0
EN[
0
ENM
GNO
+5V
0
0
0
o
o
o
o
o
+Vs
-Vs
0
0
o
REF
o
AGNQ
NIC
DeER
0
0
o
o
SIN
NOTES
1. nAEX," SHOULD BE CONNECTED TO
NO SCALING REQUIRED.
INTER LSB
RC
DIA
CASE
cos
HVEL~
WHEN
2. CASE PIN CONNECTED ON 460 OPTION ONLY.
5-30 SYNCHRO & RESOL VER CONVERTERS
The INHffiIT logic input only inhibits the data transfer from
the up-down counter to the output latches and therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
Note: With the INHIBIT input pin in the "Hi" TTL state,
data will be transferred automatically to the output latches.
1S14/1 S24/1 S44/1 S64
Two methods are available for transferring data, by using the
inputs and outputs described.
One method is to transfer data when the BUSY is in a "Lo"
state or clock the data out on the trailing edge of the BUSY
pulse. Both the INHIBIT and the ENABLES must be in their
correct state of "Hi" and "Lo's" respectively.
The alternative method is to use the INHIBIT input. Data will
always be valid one microsecond after the application of a logic
"Lo" to the INHIBIT. This is regardless of the time when the
INHIBIT is applied.
I_
SJOnsm••
31C1n$min
.1.
min'" 936"5 (II 40,800rpm'
nYlfDEPfNOSON
INPUTRAlE
.1
I
BUSY
LOGIC
STATE
L-_-_~~:
I
I
DATA
VAlID
00
-j
~ ::::'';;''
I
L....._ _.....
Where A = required rps to be represented by ± lOY FS
----~
-------------lO
~=n':~"_i ~
...
75ns
DAlECTlON
VALID
[>(XXX)
NOTE:
1.1514
SOns
mm
VAUD
However, a full scale output of ± 10V dc can be obtained for
lower speeds by chaoging the gain of the internal scaling amplifier
using only one external resistor. The external resistor, R EXT ,
should be connected between "REXT" pin and the GND REF
pin, and calculated using the following equation.
10xA
RnxT = B-A kO
VALID
VALID
Figure 2. CMOS External Counter
IXXXX><
Figure 1. Timing Diagram
RIPPLE CLOCK (RC) and DIRECTION (DIR) Outputs:
As the digital output of the converter passes through the major
carry, i.e. all "l's" to all "O's" or the converse, a RIPPLE
CLOCK (RC) logic output is initiated indicating that a revolution
or a pitch of the input has been completed.
The DIRECTION (DIR) logic output indicates the direction of
input rotation and this data is always valid in advance of the
RIPPLE CLOCK pulse, and stays valid until the direction
changes (see Timing Diagram - Figure I).
These two logic outputs are provided so that the user can count
the input revolutions or pitches. An external extension counter
is required. Figure 7 shows the application circuit which should
be used to perform this counting function.
Note: CMOS external counters can be used (see Figure 2) but it
is not advisable as great care must be taken to keep stray capacitances low because of the high tracking rate of the converter.
VELOCITY OUTPUT
The tracking conversion technique produces an internal signal
at the input to the voltage controlled oscillator (VCO) that is
proportional to the rate of the input angle. In the ISN4 series
additional circuitry is included to linearize this signal, which is
closely characterized, producing a high quality tachogenerator
velocity output at the VELOCITY (VEL) pin.
This analog tachogenerator velocity output is resistively scaled
internally to give a full scale output of ± 10V dc at the specified
tracking rate for the converter.
and B = specified rps for the converter.
Note: A cannot be greater than B and for unity gain "VEL"
and "REXT" pins should be linked (no external resistor
required).
When the external resistor facility is used to provide large magnifications there is an additional velocity output offset generated
due to the inevitable common ground impedance inherent with
a single ground connection point. While these offsets will still
be in spec, they can be code dependent. They can be minimized
by taking the external scaling resistor from "REXT" to GND
REF instead of "GND". This means that the velocity output
will be unaffected by the varying current drawn from the + SV
supply as the digital output changes.
Ripple and noise on the velocity signal consists of two components
- steady state noise and dynamic noise.
Steady state noise - this is internally generated noise produced
by the converter's circuitry and is the only noise signal present
under static input conditions.
Dynamic noise - this is the noise produced, in addition to steady
state noise, under dynamic operating conditions.
The two main components of the dynamic noise signal are due
to the "non-zero" angular error of the resolver/converter combination. The figures given in the specification are typical for a
size 11, 7 arc-minutes, brushless resolver.
It should be noted that when operating at low tracking rates it
is critical to maintain the signal input voltage at its nominal
value in order to keep the noise level on the velocity signal to an
absolute minimum. The effect of variation in signal voltage at
low tracking rates is to produce low energy spikes on the velocity
output on the rising edge of the BUSY pulse. The amplitude of
these spikes will be in the region of 30...V per percent variation
in signal input voltage level.
Note: The velocity signal output and max tracking rate derates
by 15% (max) for operation with ± 12 volt power supplies.
SYNCHRO & RESOL VER CONVERTERS 5-31
•
SPECIAL FUNCTIONS
DC Error: The signal at the output of the phase sensitive detector
is the input to the internal nulling loop and hence is proportional
to the error between the input angle and the output digital
angle. As the converters are a type 2 servo loop, this DC ERROR
signal will increase if the output angle fails to track the input
for any reason. It is therefore an indication that the input has
exceeded the maximum tracking rate of the convener, or, due
to some internal malfunction, the convener is unable to reach a
null. By the use of two external comparators this voltage can be
used as a "built in test".
INTER LSB Output: In order to overcome the "free play"
inherent in a servo system using digitized position feedback,
an analog output voltage is available representing the resolver
shaft position within the least significant bit of the digital angle
output.
Tachogenerator Transfer Function:
Tachogenerator Output _ K!(1
8IN
-
s(1
+ sT I) 0
Loo
+ sTz) pen
p
Tachogenerator Output
81N
Closed Loop
Where: KI
Kz
K.
T!
Tz
3.23
68.2 X 103
220 x 103
4.46ms
= 0.21ms
=
=
=
=
Refer: Figures 4 and 5
'2
The output is therefore proportional to the inter LSB resolved
position with a maximum output representing ILSB.
I
I,
~
! I
II
,'I
INPUT!
ANGLr
II
,I
..
I
Z
...
1/f
1
3
t--
I
.......
C
'" -3
I~i
'\
-6
~
-9
-'2
DIGITAL
COUNT
0
OUTPUT _1
10
100
200
500
1k
FREQUENCY - Hz
Figure 4. Gain Plot
INTER LSB
'80
OUTPUT
-lV
'3&
l:l
:l!
Figure 3
!i!Q
Figure 3 illustrates how the INTER LSB output compensates
for the instances where, due to hysteresis, there is no change in
the digital count output for ILSB change in input angle. The
sum of the digital count output and INTER LSB output equals
the actual input angle.
Injecting a current of 320nA into the angle offset input pin will
offset the digital output of the converter by lLSB relative to the
angle defined by the resolver inputs. It is recommended that an
offset equivalent to no greater than 30LSB's be applied to this
input.
TACHOGENERATOROUTPUT
&ouT
+ sT! Open Loop
+ ST2
os
0
r--..
........ i"o!.
-90
........
-,3&
-'80'0
20
50
100
200
FREQUENCY - Hz
r--..
500
1k
Figure 5. Phase Plot
DYNAMIC ACCURACY VS. RESOLVER PHASE SHIFr
Under static operating conditions phase shift between signal and
reference lines theoretically does not effect the convener's static
accuracy.
However, when rotating, most resolvers, particularly those of
the brushless type, exhibit a phase shift between the signal and
the reference. This phase shift will give rise under dynamic
conditions to an additional error defined by:
DYNAMIC PERFORMANCE
The transfer function of the converter is given below.
Positional Transfer Function:
90
i-os
ANGLE OFFSET Input: A unique feature of the ISN4 series
of convener is their angle offset input which allows the user to
electrically "rotate" the input shaft of the resolver.
80UT = K!K2. 1
81N
S2
1
50
20
Shaft Speed (RPS) x Phase Shift (DEGS)
Reference Frequency
For example, for a phase shift of 20°, a shaft rotation of 22rps
and a reference frequency of 5kHz, the converter will exhibit an
additional error of:
2~~2
= 0.0880
This effect can be eliminated by putting a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver.
Note: Capacitive and inductive crosstalk in the signal and reference
leads and wiring can cause similar problems.
5-32 SYNCHRO & RESOLVER CONVERTERS
1S14/1 S24/1 S44/1 S64
ptN ' ..........
"
OUWUT{
ANGLE
"
I.
12
11
,.
'SN.
11ILSS)
OIC
N/c
DATA {
TRANSfER
OUTPUT ANGLE
iii
BUSY
REXT
TACHOGENERATOR
VEL
OUTPUT
ANGLE OfFSET
+V,
GND REF
INTER LSB
OUTPUT
IMSB)'
Em
INTER LSB
PtTCH {
COUNTER
RC
ENM
DIR
GNO
CASE
+,V
REF
+V,
AGND
-V,
SIN
COS
}
DATA TRANSFER
}~MR
SUPPllES
(NOTE 21
•
CASE
BITE OUTPUT
DC ERROR
(NOTE 61
NOTES
1. GND. GND REF AND AGND ARE INTEANAU Y CONNECTED.
2. EACH SUPPLY SHOULD BE DECOUPLED WITH 100nf CERAMIC CAPACtTOR
IN PARALLEL WITH A S,..F TANTALlUM CAPACITOR.
3. REXT IS EXTERNAL TACHOGENERATOR SENSlnvtTY SCAUNG RESISTOR
Uf REQUIREDI- SEE TEXT UNDER HEADING "VelOCITY OUTPUT".
4. R1 AND R2 ARE ANGlE OFfSET INPUT SCAUNG RESISTORS (IF REQUIREDI- SEE TEXT.
S. CASE PIN CONNECTED ON 460 OPTtoN ONLY.
I. POSSIBLE USE AS BUILT·IN TEST EQUIPMENT. {SEE HEADING "SPECIAL FUNCTIONS".!
Figure 6. Electrical Connections
COS
DC ERROR
N/c
-V,
+V.
+SV
GNO
ENM
ENL
11MSBJ
SIN
AGND
REF
CASE
CURRENT SET
RESISTOR
DOl
RC
} REfERENCE
INTER Ula
GND REF
ANGLE OFFSET
VEL
R~II.T
BUSV
CLEAR
iiiiii
'SN<
N/C
O/C
,.
11
,.,.
12
13
(LSBj18
-TO FURTHER
STAGES IF
REQUIRED
PITCH
CO~NT DATA
Figure 7. Connections for Use with Inductosynl"LS" External Counters
CONNECTING THE CONVERTER
The electrical connection of the converter is straight-forward.
The power supply voltages connected to + Vs and - Vs pins
can be ± 12V to ± 15V but must not be reversed. The + SV
supply connects to the + SV pin and should not be allowed to
become negative with respect to the GND pin.
It is suggested that decoupling capacitors are connected in parallel
between the power lines ( + Vs, - Vs and + SV) and GND
adjacent to the converter.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The converter has some HIF decoupling provided internally, as
well as input protection on the signal and reference inputs.
The resolver connections are made to the sine and cosine inputs,
reference and analog ground as shown in the electrical connection
diagram (Figure 6).
SYNCHRO & RESOLVER CONVERTERS 5-33
PROCESSING FOR IUGH RELIABILITY
OUTLINE DIMENSIONS
PACKAGING SPECIFICATIONS
STANDARD PROCESSING
pjmensions shown in inches and (mm).
As part of the standard manufacturing procedure, all converters
receive the following processins:
Process
Condition
I. Pre-Cap Visual Inspection
2. Burn-In
3. ConstantAcce1eration
4. GrossLeskTest
S. Final Electrical Test
In-House Criteria
700c
SOOOG
In-House Criteria
Performed at 25"C
. . ANALOG
.... DEVICES
15154
OP'I"IDN
r:::J
0.14 :1:0.01313.58 :1:0.33)
~==============================::=::==1 .1..IF====:j=!-L
0.'(2.$4)-\1-
1-----1.9148.31----0011
HIGH REL PROCESSING
All models ordered to high reIiabilityrequirements will be identified with a B suffIX, and will have received the following proc-
00000000000000000000
essing:
T
~
-r
0.01
~:'=t
(OZS~::S I
I
1--:1:
l---o.aI22.91~
14451
1.09 :1:0.011
I. Internal visual inspection
2. Stabilization bake, 24 hours at 1500c
3. Temperature cycling, -65'C to + 150'C
4. Constant acceleration, 5000g
.
5. Powered burn-in, 160 hours at 125"C
6. Final electrical test at T MIN and T MAX
7. Seal test, fine and gross
8. External visual inspection
00000000000000000000
I_
'1. . . '
2.015 :1:0.021153.2 :to.53I----j BonuM VIEW
PACKAGE FOR S60 OPTION.
"ANALOG
.... DEVICES
15154
OPTION
[:::J-"'---+-OPTIONCODE
PIN ONE GREEN GLASS 8£AO
booooooooooooooooooo
1
J
1.140
129.01
00000000000000000000
TOLERANCES :to.005"11.31
UNLESS OTHERWISE STATED
~====;2.~'40~f;;;";:;.4;:'====~IBOTTOMVJEW
PACKAGE FOR 450 AND ...08 OPTIONS
ORDERING INFORMATION
ISN4 X60 B
N=1
N = 2
N = 4
N = 6
lO-bit resolution
12-bit resolution
14-bit resolution
16-bit resolution
5-34 SYNCHRO & RESOL VER CONVERTERS
~
~
High Reliability Processins
2kHz to 10kHz reference frequency
x=S
o to + 700c operating temperature range
x
- 55"C to + 12S"C operating
temperature range
= 4
Hybrid, Tracking
Resolver-to-Digital Converters
r-IANALOG
WDEVICES
lS20/1S40/1S60/1S61
IS20/1S40/1S60/1S61 FUNCTIONAL BWCK DIAGRAM
FEATURES
Low Cost
32-Pin Hybrid
High Tracking Rate 170rps at 12 Bits
Velocity Output
DC Error Output
Logic Outputs for Extension Pitch Counter
APPLICATIONS
Numerical Control of Machine Tools
Robotics
I
REF
SINH
COSH
DIRECTION <>------1
1---+----<> VELOCITY
RIPPlEo-----i.,-~==--,J
CLOCK
ro:;;;.c;;r----------o iNH!"T
f--------_-oBUSV
ENABlEM----'---L----~---,
ENABLEL---~,_rT,_rr,,_rTO,_rT,_~
DIGITAL ANGLE.I'>
GENERAL DESCRIPTION
The IS20/40/60/61 are a series of low cost hybrid converters
with a high tracking rate and all essential features for numerically
controlled machine applications. These converters are housed in
a 32-pin triple DIP ceramic package measuring 1.1" x 1.7" x 0.205"
(28 x 43.2 x s.2mm).
APPLICATIONS/uSER BENEFITS
The IS20/40/6O/61 has been specifically designed for the numerically controlled machine and robot industry. Using the type 2
servo loop tracking principle ideally suits these converters to
the electrically noisy environment found in these industrial
applications.
The IS20/40/60/61 convert resolver format input signals into a
parallel natural binary digital word. Typically, these signals
would be obtained from a brushless resolver and the resolver/
converter combination gives a parallel absolute angular output
word similar to that provided by an absolute encoder. The
ratiometric conversion principle of the lS20/40/6O/61 series.
ensures high noise immunity and tolerance of lead length when
the converter is at a distance from the resolver.
By using hybrid construction techniques, small size, low power
and high reliability are further benefits offered by these converters.
This small size with the three-state digital outputs makes these
converters ideal for multichannel operation.
The output word is in three-state digital logic form with a high
and low byte enable input so that the converter can communicate
with an 8- or 16-bit digital'highway. In this series there are 12-,
14- and two 16-bit resolution (± 4 arc mins and ± 10 arc mins
accuracy) models available.
The layout of the connections simplifies the parallel connection
to a digital highway.
The provision of the digital outputs of DIRECTION and RIPPLE
CLOCK allow simple extension counters for multi-pitch operation
to be implemented.
Analog outputs of velocity and dc error for control loop stabilization and bite (built in test) provide two more features required
in these applications.
Repeatability is 1LSB for all models under constant temperature
conditions.
The lS20/40/6O/61 are available with three frequency options
covering the range 400Hz to 10kHz.
Models Available
Four models are available in this range and three frequency
options for each model.
lS20 is
lS40 is
lS60 is
lS61 is
a
a
a
a
12-bit
14-bit
16-bit
16-bit
up
up
up
up
to
to
to
to
170 revolutions per second
42.5 revolutions per second
10.5 revolutions per second
10.5 revolutions per second
SYNCHRO & RESOL VER CONVERTERS 5-35
II
SPEC IFI CAli ONS
(typical@
+2ft, unless oIbanIIsa specifiad)
UDiIli
Modela
1520
1540
12
14
ISt10
16
1561
RESOLUTION
16
Bill
ACCURACY'
+8.5
+5.3
±4.0
±IO
arc·mins
REPI!AT ABILITY'
LSB
SIGNAL AND REFBRBNCEFREQUENCY'
400-IOk
Hz
DIGITAL OUTPUT
Max Load
ParaUeI natural binary
20
LSTTL
TRACKING RATE (min)
4OOHz-2.6kHz
2.6kHz-5kHz
5kHz-10kHz
SO
12.~
90
22.5
42.5
3.0
5.5
10.5
ISO
SO
25
170
3.0
5.5
10.5
rps
rps
rps
350
130
350
130
60
60
m.
ms
ms
SETTLING TIME
4OOHz-2.6kHz
2.6kHz-5kHz
5kHz-10kHz
20
ACCELERATION CONSTANT (K,)
4OOHz-2.6kHz
2.6kHz-5kHz
5kHz-10kHz
9,500
144,000
713,000
SIGNAL VOLTAGE
2.0
Vrms
SIGNAL INPUT IMPEDANCE
>10
REFERENCE VOLTAGE
2.0
REPERENCE INPUT IMPEDANCE
ISO
40
sec-2
sec-2
sec-2
125
MIl
Vrms
Idl
ALLOWABLE PHASE SHIFT'
(Signal 10Ref'ereace)
±IO
Degrees
BUSY OUTPUT'
Max Load
Logic "Hi" when Busy
20
LSTTL
BUSY WIDTH
430
os
ENABLE INPUTS
Logic "Lo" 10 ENABLE
I
LSTTL
ENABLE AND DISABLE TIMES
120(typ)
220(max)
os
os
INHIBIT INPUT
Logic "Lo" 10 INHIBIT
Load
Load
I
DIRECTION OUTPUT (DIR)'
Logic "'Hi" when counting up
Logic uLo" when counting down
MaxLosd
RIPPLE CLOCK'
LSTTL
20
LSTTL
Negative pulse indicating when
internal counters change from all
"1 's" to all "O's" or vice versa.
Mylpad
20
VELOCITY OUTPUT'(al specified min tracking rate).
positive for increasing angle
PoIarilY
OulpulVoltage'
±IO
Accuracy
:!::10
ZeroOffset
±8
DC ERROR OUTPUT VOLTAGE6
40
POWER SUPPLIES
+Vs
+ 1!.Slo + 16
-Vs
-11.510 -16
+5V
+4.7510 +5.25
POWER SUPPLY CONSUMPTION'
+Vs
20,3O(max)
-Vs
2O,3O(max)
+5V
105,125 (max)
POWER DISSIPATION'
1.1, 1.5 (max)
TEMPERATURE RANGE
Operaliotl
010 +70
Storage
-5510+125
PACKAGEOPTION8
WEIGHT
LSTTL
Vdc
%FSD
mV
10
2.5
2.5
DH-32E
1(28)
mV/LSB
V
V
V
rnA
rnA
rnA
W
"C
"C
oz.(grm.)
NOTES
ISpedfied. over the operadng temperature raoae and for:
a). ± 10% signal and refC1'CJlCC amplitude variation.
b).IO% ...... ond..r......,..........., ~~ROR
o,REcnoNC>--_ _ _--il---:-==:-I~~-~;;.;-;;;.~~
1----+--<> VELOCITY
RIPPLE
CLOCK
rtATc;-}------------o~H!BIT
j - - - - - - - - -__-o BUSY
ENA8UM ___-J----L---~L---_,
5
6
7
8
9
COSe
10
11
12
13
14
15
16
Weight in Degrees
180.0000
90.0000
45.0000
22.5000
11.2500
5.6250
2.8125
1.4063
0.7031
0.3516
0.1758
0.0879
0.0440
0.0220
0.01l0
0.0055
ENABLE L
DIGITAL ANGLE
~
THEORY OF OPERATION
The sine and cosine signals are applied to the signal input.
VI = K Eo Sin o>t Sin 0
V2 = K Eo Sin o>t Cos 0
Where 0 is the angle of the resolver shaft or the distance through
a particular pitch of the InductosynTM.
To understand the conversion process, then assume that the
current word state of the up-down counter is <1>.
VI is multiplied by Cos and V2 is multiplied by S'm to give:
K Eo Sin o>t Sin 0 Cos
and K Eo Sin o>t Cos 0 Sin
These signals are subtracted by the error amplifier to give:
or
K'Eo Sin o>t (Sin 0 Cos - Cos 0 Sin
K'Eo Sin o>t Sin (0 - <1»
<1»
A phase sensitive detector, integrator and Voltage Controlled
Oscillator (VCO) form a closed loop system which seeks to null
Sin (9 - <1».
When this is accomplished, the word state of the up-down counter
(<1», equals, within the rated accuracy of the converter, the
resolver shaft angle O.
OPERATION OF THE CONVERTER
The IS20/40/60/61 are tracking converters, this means that the
output automatically follows the input for speeds up to the
maximum tracking rate for the frequency option specified. No
convert command is necessary as the conversion is initiated by
each LSB increment of the input. Each LSB increment of the
converter initiates a BUSY pulse.
As the digital output of the converter passes through the major
carry; i.e., all "l's" to all "O's" or the converse, a RIPPLE
CLOCK (RC) logic output is initiated indicating that a revolution
or a pitch of the input has been completed.
The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in advance
of a RIPPLE CLOCK pulse.
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and therefore does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
Two ENABLE inputs are provided, ENABLE M for the Most
Significant 8 bits and ENABLE L for the Least Significant
remainder. The operation of these enables has no effect on the
conversion process.
The tracking conversion technique produces an internal signal
at the input to the VCO that is proportional to the rate of the
input angle. This is a bipolar dc analog signal that is made
available at the VELOCITY (VEL) pin. As this is an internal
control signal it is not closely characterized.
The signal at the output of the phase sensitive detector is the
input to the internal nulling loop and hence is proportional to
the error between the input angle and the output digital angle.
As the converter is a type 2 servo loop, this DC ERROR signal
will increase if the output angle fails to track the input for any
reason, it IS therefore an indication that the input has exceeded
the maximum tracking rate of the converter or due to some
internal malfunction, the convener is unable to reach a null. By
the use of two external comparators this voltage can be used as
a "built in test".
NOTE: The DC ERROR voltage has no internal filtering.
™lnductosyn is a registered trademark of Farrand Industries, Inc.
SYNCHRO & RESOLVER CONVERTERS 5-37
II
RESOLVER
COS
DC ERROR
SIN
VELOCITY
-V.
TO OTHER
RDes
(IF REQUIRED)
AGND
+V.
REF
-11--...----++~,-.-.n-:F-I +5V
DIRECTION
RIPPLE
CLOCK
GND
DATA {
TRANSFER
ENABLE M
ENABLE L
}
PITCH
COUNTER
}
DATA
TRANSFER
2Vrms
REFERENCE
BUSY
I.I.
I.
INHIBIT
1 (MSB)
13
OUTPUT
ANGLE
"
"
OUTPUT
ANGLE
I.
•
9
NOTES:
1. GND AND AGND ARE INTERNAllY CONNECTED.
2. THE 100nF CAPACITORS ARE CERAMIC TYPE.
3. THE 6p.F CAPACITORS ARE TANTALUM TVPF
Figure 1. Electrical Connections
cos
DCER
VEL
SIN
-Vs
AGND
+Vs
REF
+5V
GND
DIR
RC
ENM
BUSV
EN[
CURRENT SET
RESISTOR
} REFERENCE
iNti
1 (MSB)
16
I.
"
I."
*
*
15
13
•
CLEAR
9
LS169A
*TO FURTHER
STAGES IF
REQUIRED
+5V
PITCH COUNT DATA
Figure 2. Connections for Use with Industosynl"LS" External Counters
CONNECTING THE CONVERTER
The electrical connection of the converter is straight-forward.
The power supply voltages connected to + Vs and - Vspins
can be ± 12V to ± 15V but must not be reversed. The + 5V
supply connects to the + 5V pin and should not be allowed to
become negative with respect to the GND pin.
It is suggested that decoupling capacitors of lOOnF are connected
in parallel between the power lines ( + Vs, - Vs and + 5V) and
GND adjacent to the converter.
~38
SYNCHRO & RESOL VER CONVERTERS
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter (refer
to Figure 1).
The converter has some HIF decoupling provided internally, as
well as input protection on the signal and reference inputs.
The resolver connections are made to the sine and cosine inputs,
reference and analog ground as shown in the electrical connection
diagram (Figure 1).
1S20/l S40/l S60/l S6l
min
I•
500n5 max
370n5 min
. I. max
= 936ns (f/
170APS2
DEPENDS ON
INPUT RATE
.1
I
BUSY
LOGIC
STATE
I
NOTE 1
C-_~~~~:
365n5 max
~7~~:~1
DATA
VAUD
I
IXJ
VAUD
VALID
--I II--RIPPLE
CLOCK
----HI
J
1______________ LO
,-_N_O_TE_'_...J
r--+- ~'!'=In ..,
DIRECTION
VALID
'OOn. max
46ns typ
t--
15n5
SOns
min
min
IXxxX)
VAUD
II
NOTES:
1. DUE TO SAME UP·DATE
2. 1520-560
Figure 3. Timing Diagram
r-------------------..--CLEAR
5k
~r~~--~~r---~~
DIRECTION
--..-+-4
5k
}
TO FURTHER
STAGES IF
REQUIRED
v
PITCH COUNT DATA
Figure 4. CMOS External Counter
DATA TRANSFER
The readiness of the converter for data transfer is given by the
state of the BUSY output. The signal appearing on the BUSY
output pin is a series of pulses of TTL levels when the angular
input of the converter is changing. A BUSY pulse is initiated
each time the input moves by an LSB and the internal counter
is incremented or decremented. With the INHIBIT input pin in
the "Hi" TTL state, data will be transferred automatically to
the output latches.
The ENABLE input pin determines the state of the output
data. A TTL logic "Hi" maintains the output data pins in a
high impedance condition, the application of a logic "Lo" presents
the data in the latches to the output pins.
From the above it can be seen that there are two methods available
for transferring data.
One method is to transfer data when the BUSY is in a "Lo"
state or clock the data out on the trailing edge of the BUSY
pulse. Both the INHIBIT and the ENABLES must be in their
correct state of "Hi" and "Lo's" respectively.
The alternative method is to use the INHIBIT input. Data will
always be valid one microsecond after the application of a logic
"Lo" to the INHIBIT. This is regardless of the time when the
INHIBIT is applied.
In order to count input revolutions or pitches, an external extension
counter is required. A circuit performing this function is shown
in Figure 2.
The DIRECTION (DIR) and RIPPLE CLOCK (RG) logic
outputs should always be used in the manner shown in the
application circuit. We recommend the circuit in Figure 2 to be
used as the circuit in Figure 4 uses CMOS and great care must
be taken to keep the stray capacitances low because of the high
tracking rate of the converter.
SYNCHRO & RESOL VER CONVERTERS 5-39
DYNANUCPERFORMANCE
The transfer function of the converter is given below.
~"'-090UT
·
·•
3
Open loop gain:
80UT
a;;:;-
1 + ST\
= S2 'I + ST z
K.
-,
-
V--
["...
\
\
2
2.
50
100
200
\
FREQUENCY _ Hz
Closed loop gain:
80UT =
\
Figure 7
+ ST\
+ ST\ + ~ + S3T z
1
1
K.
K.
IS20/1S40/1S60/1S61 (typical values)
~
~
510
Constant
550
~I I I I I
I
560
·
--....... ~
-45
K.
9,500
144,000
713,000
T\
l7.4ms
4.1ms
1.85ms
T2
2.6ms
0.6ms
0.25ms
Gain Plot
FigureS
Figure 7
Figure 9
........ i'.
-eo
........... r--.
--180
200
10
fREOUENCY - Ha
Phase Plot
Figure 6
I I
--
r--
500
Figure 10
Figure 8
Figure 8
'2
'2
~-
I'-..
•
·
·
·
·
\
-6
\
\
-12
26
'00
200
-l--- r--.. ~
...
i'.
~
..
,
2
2•
FREQUENCY - Hz
FREQUENCY _ Hz
Figure 5
Figure 9
200
\
'36
.
-..
"-
-90
-'35
,.
-.......
"'-
-'60
........
-eo
........
r---
It
260
~
""""r--.
-'35
...
fR£O.UENCY - Hz
Figure 6
~40
"
SYNCHRO & RESOLVER CONVERTERS
"
~
2.
so
.00
FREOUENCY _ Hz
Figure 10
"
1S20/1 S40/1 S60/1 S61
ACCELERATION ERROR
A tracking converter like the I S20 employing a type 2 servo
loop does not suffer any velocity lag, however, there is an additional
error due to acceleration. This additional error can be defined
using the acceleration constant K. of the converter.
The graph below shows the typical variation of MTBF with
temperature for the IS20, under ground benign environment.
~
K = Input acceleration
•
Error in output angle
The numerator and denominator have the same units. K. does
not define maximum acceleration only the error due to acceleration,
maximum acceleration is in the region of 10 times the K. figure
(deg/sec2 ).
An example using the K. of the IS60/560
Acceleration of 33 revolutions sec-2 with K. = 713,000
Additional error = I arc-min
..
~
r---..
~
r--
"
Shaft Speed (RPS) x Phase Shift (DEGS)
Reference Frequency
For example, for a phase shift of 20°, a shaft rotation of 22rps
and a reference frequency of 5kHz, the converter will exhibit an
additional error of:
= 0.0880
This effect can be eliminated by putting a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver.
ABSOLUTE MAXIMUM INPUTS (with respect to GND)
+VSI
_VSI ..
+SV2 ••
Reference
Sine . . .
Cosine ..
Any Logical Input
STANDARD PROCESSING
As part of the standard manufacturing procedure, all converters
receive the following processing:
Process
Condition
1.
2.
3.
4.
5.
In-House Criteria
70°C
5000G
In-House Criteria
Performed at 25°C
. OV to +17V dc
. OV to -17V dc
OV to +7.0V de
±17V dc
±17V de
±17V dc
-O.4V to +S.SV de
CAUTION:
I. Correct polarity voltages must be maintained on the + Vs
and - Vs pins.
2. The + 5 volt power supply must never go below GND
potential.
PROCESSING FOR HIGH RELIABILITY
Pre-Cap Visual Inspection
Burn-In
Constant Acceleration
Gross Leak Test
Final Electrical Test
""
0
DYNAMIC ACCURACY VS. RESOLVER PHASE SHIFT
Most resolvers, particularly those of the brushless type, exhibit
a phase shift between the signal and the reference. This phase
shift will give rise under dynamic conditions to an additional
error defmed by:
2~~ ~
'"""
PIN CONFIGURATION
cos
DCER
VEL
SIN
-v,
AGND
+v.
+.v
REF
GND
DIR
TOP VIEW
ENM
RC
BUSY
ENL
INH
,.
(MSBI1
I.
I.
MEAN TIME BETWEEN FAILURES (MTBF)
The reliability of these products is very high due to the extensive
use of custom chip circuitry. For details of MTBF figures under
particular conditions please consult the factory.
13
12
11
PIN 1 IDENTIFICATION ~.
,.
SYNCHRO & RESOL VER CONVERTERS 5-41
•
OTHER PRODUCTS
IRDC1732IPA1751OSC1754OSC1758IPA1764MCI1794-
Inductosyn™lResolver to Digital Converter (Hybrid)
Inductosyn™ Pre-Amplifier
Power Oscillator
Power Oscillator (Hybrid)
Inductosyn™ Pre-Amplifier (Hybrid)
3 Channel Inductosyn™IResolver
to Digital Converter (Multibus Compatible Card)
™Inductosyn i. a registered trademark of Farrand Industries, Inc.
ORDERING INFORMATION
5YO
T
IS20 IS40 IS60 IS61 -
~42
SYNCHRO & RESOLVER CONVERTERS
12
14
16
16
~
Bit
Bit
Bit
Bit
I = 400Hz - 2.6kHz
5 = 2.6kHz - 5kHz
6 = 5kHz - 10kHz
11IIIIIIII ANALOG
L.III DEVICES
Tachogenerator
Output, Variable Resolution,
Hybrid, Resolver-to-Digital Converter
lS74
FEATURES
4O·Pin Hybrid
Tachogenerator Velocity Output
User Selectable Resolution
DC Error Output
Sub LSB Output
Angle Offset Input
Reference Frequency of 2kHz to 10kHz
Logic Outputs for Extension Pitch Counter
APPLICATIONS
Numerical Control of Machine Tools
Feed Forward Velocity Stabilizing Loops
Robotics
Closed Loop Motor Drives
Brushless Tachometry
Single Board Controllers
IS74 FUNCTIONAL BLOCK DIAGRAM
REF
SIN
Typically, the input signal would be obtained from a brushless
resolver and the resolver/converter combination gives a parallel
absolute angular output word similar to that provided by an
absolute encoder. The ratiometrlc conversion principle of the
lS74 ensures high noise immunity and tolerance of lead length
when the converter is at a distance from the resolver.
In conjunction with the IPA1764 preamplifier, the lS74 is also
suitable for use with Inductosyns®.
The output word is in three·state digital logic form with a high
and low byte enable input so that the converter can communicate
with an 8· or l6-bit digital highway.
A unique feature of the converter is its internally generated
tachogenerator velocity output offering a linear Voltage-speed
relationship. Only one external resistor is required to scale the
velocity output to the user's chosen volts/rpm relationship.
DC
~----or~~~~
------I~-------O~~~
INPUT
DIRECTION
t--<'---_--OOVELOCIlY
~..::;=:::.----
SC'
SC'
__----o
INTER LSB
OUTPUT
INHIBIT
L~~j::===::::;:::::::: BUSY
ENABLEM~~~--L------L---,
ENABLE l
GENERAL DESCRIPTION
The lS74 is a hybrid device that converts standard resolver
inputs to digital position and analog velocity outputs. All the
essential features of multiturn or multipitch operation are included
for numerically controlled machine tool and velocity feedback
applications.
--"Tr==rT1rT1==r'
MS8
DIGITAL ANGLE ell
LSB
1180")
APPLICATIONS
The lS74 has been designed for motor position control in the
CNC, robotic and military fields. The use of a type 2 tracking
servo loop circuit with high inherent noise immunity, makes the
product ideally suited to these applications.
USER BENEFITS
Allows both velocity and position measurement from a single,
low cost, standard, brushless resolver.
80dB dynamic range of velocity output.
0.5% ripple on velocity signal.
0.1 % linearity of velocity signal.
Cost effective tachogenerator/encoder replacement.
Tracks at 5 to 10 times the rate of equivalent resolution
encoders.
Analog output for interpolation between digital codes.
Repeatability is lLSB under constant temperature conditions.
Direction and Ripple Clock (Datum) outputs facilitate revolution
counting.
The resolution of the lS74 converter is user selectable by means
of applying a specific binary code to two of the converter's pins.
Hybrid construction offering small size and MTBF of >200
years at 50·C GB.
Four resolutions can be selected, all operating over a frequency
range of 2kHz to 10kHz.
10 bit
12 bit
14 bit
16 bit
up
up
up
up
to
to
to
to
I
MIL operating temperature range and spec. options available.
Induetosyn® is a registered trademark of Fanand Industries, Inc.
40,800 revolutions per minute.
10,200 revolutions per minute.
2,550 revolutions per minute.
630 revolutions per minute.
SYNCHRO & RESOL VER CONVERTERS 5-43
IJ
SPECIFICATIONS
(typical for boll! commercial (5YO) and ex1Bnded (4YO) temperature range options
@ 2ft and ± 15V or ± 1ZII power supplies, unless othalWise noted)
Resolution
10 Bits
12 Bits
14 Bits
16 Bits
Units
2.0(±5%)
2.0 ( + 500Al - 200/0)
2k-l0k
10 (min)
125
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Vrms
Vrms
Hz
±10
*
*
*
Degrees
10
0.35
12
0.088
14
0.022
16
0.0055
Degrees
±25.0(0.42)
±0.12
± 25.0 (0.42)
±0.12
Parallel natural binary
6 (max)
Guaranteed
1
±8.S(0.14)
±0.04
±8.5 (0. 14)
±0.04
±5.3(O.09)
±0.025
±5.3(O.09)
±O,02S
±4.0(0.07)
±0.019
±2.6(O.04)
±O.O12
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
40,800 (min)
34,680 (min)
10,200 (min)
8,670 (min)
2,550 (min)
2,168 (min)
630 (min)
536 (min)
rpm
rpm
220,000
25 (max)
230
*
RESOLVER INPUTS
Signal Voltage
Reference Voltage
Signal & Reference Frequency
Signal Input Impedance
Reference Input Impedance
Allowable Phase Shift
(Signal to Reference)
POSITION OUTPUT
Resolution
lLSB
Accuracy (maximum error over
temperature range)
5YO
4YO
Digitai Position Output Format
Load
Monotonicity
Repeatability
M!l
kO
Bits
arc-mins(degrees)
%F.S.
arc-mins (degrees)
%P.S.
LSTTL
LSB
DATA TRANSFER
Busy Output
Load
BusXWidth
Logic "Hi" when busy
6 (max)
380 (min) 530 (max)
ENABLE INPUTS
Load
Enable & Disable Times
Logic "Lo" to enable
1
250 (max)
INHIBIT INPUT
Load
Direction Output (DIR)
Load
Ripple Clock (RC)
Logic "Lo" to inhibit
LSTTL
1
Logic "Hi" when counting up, logic "Lo" when counting down.
6 (max)
LSTTL
*
*
*
Negative pulse indicating when internaI counters change from alI "I's" to alI "O's" or
vice versa.
6 (max)
LSTTL
*
*
*
1". (max) 850n (min)
sees
*
*
*
Load
Width
DYNAMIC CHARACTERISTICS
Tracking Rate
with ± 15V Supplies
with ± 12V Supplies
Acceleration Constant
K.
Settling Time (179" step input)
Bandwidth
VELOCITY OUTPUT
Polarity
Tachogenerator Voltage Scaling
Scale Factor Accuracy
Scale FactorTempco
Reversion Error
Reversion Error Tempco
Linearity
Over Full Temperature Range
Ripple and Noise
Steady State (200Hz BIW)
Dynamic Ripple (av-pk)
Zero Offset
Zero Offset Tempco
Output Load
Positive for increasing angle
0.25
± 1 (max)
200 (max)
±0.2(max)
50 (max)
0.1
0.25 (max)
100
0.5 (max)
±500
50 (max)
5 (min)
5-44 SYNCHRO & RESOLVER CONVERTERS
LSTTL
ns
LSTTL
ns
35 (max)
60 (max)
*
*
120 (max)
sec-2
ms
*
*
*
Hz
*
1.00
4
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
16
150
300
1300
*
*
*
*
*
*
*
*
*
*
*
*
V/Krpm
% of output
ppmI"C
%
ppmI"C
% of output
% of output
".Vrms
% of output
".V
".VI"C
KO
lS74
Resolution
SPECIAL FUNCTIONS
de Error Output Voltage
Inter LSB Output
Load
Angle Offset Input (over operating
temperature range)
Maximum Input
10 Bits
12 Bits
14 Bits
16 Bits
Units
450
±1(±20%)
Ik(min)
*
*
*
*
*
*
*
*
*
mV/deg
V/LSB
320(± 10%)
32
*
*
*
*
•
*
nAlLSB
LSB
n
POWER REQUIREMENTS
Power Supplies
±Vs
+5V
Power Supply Consumption
+Vs
-Vs
+5V
Power Dissipation
±15(±5%)or ±12(±5%)
+4.75 to + 5.25
*
*
*
*
*
*
Vde
Vdc
30 (max)
30 (max)
125 (max)
1.5 (max)
*
*
*
*
*
*
*
*
*
*
*
*
rnA
mA
rnA
W
TEMPERATURE RANGE
Operating 5YO Option
4YOOption
Storage 5YO Option
4YOOption
Oto +70
-55to + 125
- 55 to + 125
-60to+150
*
*
*
*
*
*
*
*
*
*
*
*
°C
°C
°C
°C
2.1 x 1.1 xO.195
(53.5 x 28 x 4.95)
2.14 x 1.14 x 0.18
(54.5 x 29 x 4.6)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
DIMENSIONS
5YOOption
4YOOption
WEIGHT
1(28)
Inches
(mm)
Inches
(mm)
oz. (grams)
SpeciflCations subject to change without notice.
ABSOLUTE MAXIMUM INPUTS (with respect to GND)
..
+VSl
_VSl . .
+5V2 ••
Reference
Sine . . . .
Cosine . . .
Any Logical Input
. ..
....
OV to +17V de
OV to -17V de
. OV to +6.0V de
±17V de
±17V de
±17V de
• -O.4V to +5.sV de
CAUTION:
I. Correct polarity voltages must be maintained on the + Vs
and - Vs pins.
2. The + 5 volt power supply must never go below GND
potential.
SYNCHRO & RESOL VER CONVERTERS 5-45
II
FUNCTIONAL DIAGRAM
PIN CONNECTIONS
REF
12
11
10
SIN
DC
I--.--.....--<>r:~~
----I~----o~~~
INPUT
1
ENL
ENM
GND
DIRECTION
~~~o-----i
+5V
+Vs
-Vs
NIC
DeER
......' - -.....--oVELOCITV
~....;.;;C:=~
st1
-
st,
____
....,INTER LSB
OUTPUT
~~~~===:::::::::::INHIBI1
~
BUSY
Msa
DIGITAL ANGLE..
LSB
1180"1
OPERATION OF THE CONVERTER
The IS74 is a tracking converter, this means that the output
automatically follows the input for speeds up to the maximum
tracking rate for the resolution option. No convert command is
necessary as the conversion is initiated by each LSB increment
of the input. Each LSB increment of the converter initiates a
BUSY pulse.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BOTTOM
VIEW
,.,.
13
"
SC2
SC1
INH
BUSY
REXT
VEL
ANGLE OFFSET
GND REF
INTER LSB
RC
DIR
CASE
REF
AGNO
SIN
COS
NOTES
1. "R~)(T" SHOULD BE CONNECTED TO
"VEL" FOR UNITY GAIN.
~ft-_r--=~-=-=-=L---'
~V--Lnnnnnnn.,~--''''_;
II
- ve Position
FullS.ale
Max -ve
Position
Overrange
1 11 1
111 1
1111
1111
-1
RATIO OF V2IVREF
Figure 2. Output Code Format
PHASE SHIFT AND QUADRATURE EFFECTS
CONNECTING LVDTS
Reference to signal phase shift can be high in L VDTs, sometimes in the order of 70 degrees. If the converter is cOnnected as
in Figures 3 and 4, any effects due to this phase shift are minimized. This connection method, therefore, provides outstanding
benefits.
Since all input connections to 2S56 converters are truly differential, there is great flexibility in the input sensor connection configuration. Some of the various methods are shown in Figures 3,
4 and 5.
The additional gain error caused by reference to signal phase
shifts is given by:
(1 - cosa) x 100% of FSR
where
a=
phase shift between VREF and VI.
When the phase shift between VREF and VI is zero, additional
quadrature on the signal will have no effect on the converter.
This is another benefit of the conversion method.
(It should be noted that a ground reference point should always
be included and connected to either the VREF or V 1 inputs.)
It is suggested that decoupling capacitors be connected in parallel between the power supply lines (+Vs , -Vs, +5 V) and
GND, adjacent to the converter. Suggested values are: 6.8 ILF
tantalum and 47 nF disc capacitors connected in parallel. When
more than one converter is on a card, separate decoupling
should be used for each converter, particularly the 47 nF
capacitors.
The + V s and the - Vs pins should be connected to dc power
supplies of the appropriate polarity in the range of ± 15 V ± 5%.
Care should be taken to ensure that the polarity can never
become reversed. The + 5 V pins should be connected to a
+5 V ±5% dc supply. The +S V supply must never be allowed
to go negative with respect to ground.
SYNCHRO & RESOLVER CONVERTERS 5-57
Gl
POWER SUPPLY AND ALL DIGITAL
CONNECTIONS NOT SHOWN
G2
HI
AGND
2S5N
OIGITAL
POSITION
L-_oo-_ _--IA
Three or Four Wire LVDT Connection
In this method of connection, shown in Figure 4, the converters
digital output is proportional to the ratio:
B
'BRIDGE COMPLETION RESISTORS ARE
INTERNAL ONLY ON THE 2S54/2866
(A-B)
(A+B)/2
Figure 3. Half Bridge L VOT Connection
POWER SUPPLY AND ALL DIGITAL
CONNECTIONS NOT SHOWN
G'
where A and B all': the individual L VDT secondary output voltages. Inspection of Figure 4 should demonstrate why this relationship is true. (A - B) is simply the voltage across the series
connected secondaries of the L VDT and is applied to the VI
input to the converter. (A +B)/2 is effectively the average of
the two secondary voltages as computed by the balanced bridge
completion resistors and the grounding of the secondary
center-tap.
G2
LO
2S5N
DIGITAL
POSITION
PISTON
A
Half Bridge Type L VDT Connection
In this method of connection, shown in Figure 3, the internal
bridge completion resistors, RI and R2, in the 2S54 and 2S56
are used. If this configuration is used with the 2S58, external
precision resistors must be employed. The "BRIDGE COMPLETION RESISTORS" in the SPECIFICATIONS section
details the required precision. The internal resistors in the 2S54
and 2S56 have nominal values of lO kG and are matched sufficiently to ensure that the null position of the L VDT is represented by the correct output code. The common connection
between the two resistors (i.e., Rc2 to RC3 on the 2S54, 2S56)
can be replaced by a potentiometer if the null needs to be
adjusted. For differential measurements, the resistors can be
replaced by another LVDT. The system is nonisolated.
B
Note: This method of connection is appropriate only for
where (A +B) is a constant, independent of L VDT position.
Any lack of constancy in (A+B) will be reflected as an additional non-linearity in the output. It is up to the user to determine if (A +B) is sufficiently constant over the particular
stroke length employed. (A+B)12 can be monitored on the
"REF OIP" pin.
This method will usually restrict the usable L VDT range to
half of its full range. The restriction can be eliminated, however, by attenuating VI by a factor of 2 or increasing VREF by
a factor of 2.
'BRIDGE COMPLETION RESISTORS ARE
INTERNAL ONLY ON THE 2S54/2S56
Figure 4. Three- or Four-Wire LVOT Connection
G,
POWER SUPPLY AND ALL DIGITAL
CONNECTIONS NOT SHOWN
This connection method has the tremendous advantage of being
insensitive to temperature related phase shifts and excitation
oscillator instabililty effects usually associated with more conventional L VDT conversion systems.
G2
LO
As in the case of the Half Bridge Type L VDT Connection, RI
and R2 are the bridge completion resistors' (internal on the
2S54, 2S56; external on the 2S58) and are matched to a degree
sufficient to ensure that the digital output representing the null
position does not vary from the LVDT's natural null position. If
null adjustment is required, a potentiometer can be used in
place of the common connection between the two resistors.
AGND
V REF
~4-_~-i_ _~HI~
2S5N
OIGITAL
POSITION
PHASE LEAD
~
ARC TAN 2,,',RC
~T
R
PHASE LAG
~
ARC TAN 2" IRC
~
~
PHASE SHIFT CIRCUITS
C
Figure 5. Two-Wire L VOT Connection
5-58 SYNCHRO & RESOLVER CONVERTERS
Two-Wire LVDT Connection
This method should be used in cases where the sum of the
L VDT secondary output voltages (A + B) is not constant with
LVDT displacement over the desired stroke length. The method
of connection, shown in Figure 5, still maintains the ratiometric
operation and the insensitivity to variations in reference amplitude and frequency. However, the phase shift between VREF
and VI should be minimized to maintain accuracy (see Section
"PHASE SHIFT AND QUADRATURE EFFECTS"). Suggested phase compensation circuits are shown in Figure 5.
2S54/2S56/2S58
REF
LO
REF
HI
AGND
2554
OR
2556
ANALOG
MUX
4T01
E.G.
1'2AD1501
A
>-
"
ENL
;:
!2
'"
ENM
Gl
:J:
e"
G2
!
SELECT
II
SELECT
SELECT
TO
MUX
ADDRESS
DECODE
Figure 6. Multiplexing 4 LVDT5 into the 255412556
MULTIPLEXING THE CONVERTERS
Although the 2S56 series of converters are primarily intended
for use as single channel, continuous conversion devices, they
can also be used in small multiplexed systems as shown in Figure 6. However, when switching between LVDT channels,
ample time must be allowed for the converters to settle prior to
transferring data.
Using the 2S541X40 as in Figure 6 and allowing a time between
samples of 70 ms, the maximum settling time of the converter
can yield four 14-bit results from the 4 LVDTs in 280 ms. The
gain can be programmed, as shown, to accommodate various
transformation rations of dissimilar LVDTs. Note, however,
that the finite "ON" resistance of the analog switch used with
the gain setting resistor can introduce gain inaccuracies. This
error is minimized for lower gains as the "ON" resistance of the
switch will be negligible compared to the gain setting resistor.
The error introduced can be calculated from the equation for
the preamplifier gain in the "INPUT GAIN" section.
SCALING THE INPUTS
In cases where there is a requirement for a particular L VDT
stroke length to correspond to full-scale on the digital output,
the input gain must be chosen accordingly. It is important to
remember that it is the relationship between V2 and VREF' not
VI and VREF, which determines the full-scale digital output.
Furthermore, it should be ensured that these voltages are each
2 V rms ±10%, respectively. For monitoring purposes, V2 is
brought to the "DIFF OIP" pin and VREF is brought to the
"REF OIP" pin.
Figure 7. Transfer Function
DYNAMIC PERFORMANCE
The transfer function of the converters, shown in Figure 7 is
given by:
Open Loop Gain:
AOUT
Ka
I +sTI
--=<'2'-AJN
S
1 +sT2
Closed Loop Gain:
where:
2S54/56 XIO options
2S54/56 X40 options
2S58
k.
12000 sec- 2
93600 sec- 2
450000 sec- 2
Tl
T2
14.7 ms
5.9 ms
2.4 ms
2.3 ms
1.0 ms
0.4ms
The gain and phase response of each of the three options is
shown in Figures 8, 9, 10, 11, 12 and 13.
5YNCHRO & RE50L VER CONVERTERS 5-59
180
12
135
90
...........
!II
I
Z
0
~
"\
-3
-6
\
-9
-12
10
1
50
20
r--......
.L45
""'
-90
-135
\
-180
5
1
100
FREQUENCY - Hz
Figure 8. Gain Plot 410 and 510 Options (255412556)
10
20
FREQUENCY - Hz
l"-...
50
100
Figure 9. Phase Plot 410 and 510 Options (255412556)
180
12
135
90
....
I
Z
~
I.-..- ~
0
""1\
-3
~
I
~
,
if
\
-6
50
"\
I,
-135
~
20
............... r-..
-45
-90
-9
-12
10
45
i
l"- t - -
-180
100
200
FREQUENCY - Hz
500
1000
Figure 10. Gain Plot 440 and 540 Options (255412556)
10
20
50
100
200
FREQUENCY - Hz
500
1000
Figure 11. Phase Plot 440 and 540 Options (255412556)
lao
12
135
90
---
-3
~
.........
r-..... .......
1\
\
-6
-9
'"
-90
\,
-135
-12
~
r"-
-180
10
20
50
100
200
FREQUENCY - Hz
500
Figure 12. Gain Plot for 2558
5-60 5YNCHRO & RE50LVER CONVERTER5
1000
10
.20
50
100
200
FREQUENCY - Hz
!IOO
Figure 13. Phase Plot for 2558
1000
2S5412S56/2S58
and then transfer the data when the BUSY is "Lo". Both
INHIBIT, ENABLE M and ENABLE L must be in their correct state of "Hi" and "Lo" respectively, in order that the data
is presented to the output.
ACCELERATION ERROR
Tracking converters such as the 2S56 series, employing a type 2
servo loop, do not suffer any velocity lag. However, there is
an additional error when the L VDT is undergoing periods of
acceleration.
The alternative method is to use the INHIBIT input. Taking
this input to a "Lo" state prevents the internal monostable circuits being triggered and consequently the latches being
updated. Data will always be valid 1 ILs after the application of a
logic "Lo" to the INHIBIT. However, if INHIBIT is applied
while BUSY is in the "Lo" state (with ENABLE M and
ENABLE L also "Lo"), data is valid instantaneously.
The additional error can be defined using the K. constant of
the converter (see DYNAMIC PERFORMANCE section) as
follows:
K
=
a
Input acceleration
E TTor in output position
where the numerator and the denominator are defined in the
same units.
The internal tracking operation of the converter cannot in any
way be affected by the logic state present on either the
INHIBIT or the ENABLE pins.
K. does not defme the maximum acceleration, only the error
due to the acceleration.
DATA TRANSFER
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, due
to a change in displacement of the L VDT, the signal appearing
on the converter's BUSY output pin is a series of pulses of TTL
levels. A BUSY pulse is initiated each time the input moves by
the equivalent of an LSB and the internal up-down counter is
incremented or decremented.
With the INHIBIT input pin in the "Hi" state, data will be
transferred automatically to the output latches.
The two three-state enable inputs, ENABLE L and ENABLE
M, allow the digital input to be transferred on to a data bus in
two separate bytes. ENABLE M enables the most significant 8
bits of the output word while ENABLE L enables the remaining least significant bits.
There are two methods of transferring the output data. The first
is to detect the state of the "BUSY" which is 'Hi" for 1 ILS max
530 n5 MAX
380 n5 MIN
_I"
1
BUSY _ _.....
70n5
--l :~tt:!I
Direction (OIR)
This TTL output signal indicates the direction of the
transducer. It is a logic "Hi" when counting up and a logic
"Lo" when counting down.
Reference Output (REF O/P)
This is the reference signal after the input buffer stage. It can
be used as a single ended measurement point for the VREF
input.
It can also be used as a BITE (Built in Test Equipment) signal
to detect if the L VDT has become disconnected or the reference
supply has failed.
Figure 14 shows the timing diagram.
I_
OTHER INPUTS AND OUTPUTS
Differential Output (DIFF O/P)
This signal is in fact V2 and is brought out to a pin in order to
simplify scaling of the VI signal.
SUPPORT OSCILLATOR
A power oscillator, OSC1758, is available for use as a reference
generator for LVDT and RVDT transducers. It is capable of
providing up to 7 volts rms at 1.4 VA.
MAX DEPENDS ON
INPUT RATE
J
VALID
600n5 MIN
_ 1.,.5 MAX
I--
IX]
~~f+~
~--------~I------'~:
I
MIN--j
DATA
_I
VALID
VALID
DIRECTION
Figure 14. 2S56 Data Transfer Timing Diagram
SYNCHRO & RESOL VER CONVERTERS 5-61
I
PIN FUNCTION DESCRIPTION
PIN CONFIGURATIONS
BIT9
BJTl0
Brrll
Brr12
BITl3
BIT 14
BJT15
BIT 16 {LSBI
INH
BUSY
DIR
AGND
VREFHI
VAEFLO
Vl(AI
Vl(BI
Gl
G2
DIFFO/P
REFO/P
o
o
1
2
03
0 4
05
06
7
08
9
010
011
012
013
014
015
016
017
018
019
020
o
o
TOP
VIEW
400
390
380
370
360
350
340
330
320
310
300
290
280
270
260
250
240
230
220
21 0
-Vs
BIT 8
BIT 7
BIT I
BITS
BIT4
BIT3
BIT 2
{MSBIBITl
ENL
ENM
Main positive power supply.
+5 V
Logic power supply.
GND
Power supply ground. Digital ground.
Bit 1-14 (2S54)
Bit 1-16
Parallel output data bits.
(2S56, 2S58»
INHIBIT
Inhibit logic input. Taking this pin "Lo"
inhibits data transfer from counter to
output latches. The conversion loop
continues to track.
BUSY
Converter BUSY. A "Hi" output indicates
that the output latches are being updated.
Data should not be transferred from the
converter while BUSY is "Hi."
ENABLEM
The 8 most significant output data bits are
set to a high impedance state by
application of a logic "Hi."
ENABLE L
The 6 least significant bits of a 2S54, or
the 8 least significant bits of a 2S56 "and
2S58," are set to a high impedance state
by application of a logic "Hi."
GND
+SV
+V.
-V.
~
} NIC ON ZS58
Roo
TP
CASE
NIC = NO CONNECT
MEAN TIME BETWEEN FAILURES (MTBF)
The predicted reliability of these converters is exceptionally high
due to the extensive uses of LSI custom circuitry. Figure 15
shows the MTBF of the 4YZ options as calculated according to
MIL HDBK 217D at various temperatures under ground
benign environment. For MTBF calculations under other environments, please consult the factory.
Main negative power supply.
+Vs
Connections to Rl, internal bridge
completion resistor (2S54/2S56 only).
Connections to R2, internal bridge
completion resistor (2S5412S56 only).
TTL output indicating the direction of
movement of the transducer.
40.
32.
~
'~
.
25
Analog ground.
VREF HI }
Input pins for the Reference signal.
VREF LO
~
•
AGND
4.
~
55
7.
TEMPERATURE - "C
...........
----
8.
VI (A) }
VI (B)
Input pins for the Signal.
Gl }
G2
A gain setting resistor, or a link, can be
connected between these pins.
DIFF OIP
This is a VI after scaling (V2).
REF OIP
This is the reference signal after the input
buffer stage.
CASE
This should normally be grounded. Case
can be taken to any voltage with a low
impedance up to ±20 V.
TP
Test Point. Do not make connections to
this pin.
100
Figure 15.
5-62 SYNCHRO & RESOLVER CONVERTERS
2S54/2S5S/2S58
STANDARD PROCESSING
As part of the standard manufacturing procedure, all converters
receive the following processing:
OTHER TRANSDUCER INTERFACE PRODUCTS
2S80/2S8112S82
10-16 Bit Variable Resolution Resolver to
Digital Converter (Monolithic IC)
Process
2S50
10 Bit + Sign, L VDT to Digital
Converter (Hybrid)
OSC1758
Power Oscillator (Hybrid)
IS 14/24/44/64
10-, 12-, 14-, and 16-Bit Resolverto-Digital Converters with High Accuracy
Velocity OIP
IS74
Variable Resolution (10 to 16 Bits)
Resolver-to-Digital Converter with High
Accuracy Velocity Output.
IS1O/lS20/1S401
IS6O/lS61
10-, 12-, 14- and Two 16-Bit Inductosyn*
Resolver-to-Digital Converters (Hybrid)
5S70172
Input Isolation Transformers for the IS
Series of Converters. Also Convert from
Synchro Format.
IPA1764
Inductosyn Pre-Amplifier (Hybrid)
1.
2.
3.
4.
Condition
Preseal Burn In
64 Hours at +125°C
Precap Visual Inspection In-House Criteria
Seal Test, Fine and Gross In-House Criteria
Final Electrical Test
Extended temperature range versions receive additional
processing as follows:
4. Final Electrical Test
Performed at Maximum and Minimum Operating Temperatures
PROCESSING FOR HIGH RELIABILITY
All extended temperature range models are available with high
reliability screening. The parts are identified with a B suffIx,
and will receive the following processing.
Process
I. Preseal Burn In
2. Precap Visual Inspection
3. Temperature Cycling
4. Constant Acceleration
5. Interim Electrical Tests
6. Operating Burn In
7. Seal Test, Fine and Gross
8. Final Electrical Testing
(Group A)
9. External Visual Inspection
Conditions
64 Hours at + 125°C
MIL-STD-883, Method 2017
10 Cycles, -65°C to + 150°C
5000G, Yl Plane
*Inductosyn is a trademark of Farrand Industries, Inc.
96 Hours at + 125°C
MIL-STD-883, Method 1014
Performed at T min' T AMB'
and Tmax
MIL-STD-883, Method 2009
NOTE: Test and screening data can be supplied. Further information on request.
SYNCHRO & RESOL VER CONVERTERS 5-63
II
ORDERING INFORMATION
255NI
N
=
4 14-Bit Binary
N
=6
16-Bit Binary
N
=8
16-Bit Binary
High Precision
5-64 SYNCHRO & RESOL VER CONVERTERS
Xy
o
B
L
High Reliability Process
Y
=1
Y
=
4 140 Hz Bandwidth (2554, 2556 Only)
(Ref 1 kHz-5 kHz)
Y
=
0 300 Hz Bandwidth (2S58 Only)
50 Hz Bandwidth (2554, 2556 Only)
(Ref 360 Hz-5 kHz)
x=
5 0 to +70°C Operating Temperature Range
x
4 -55°C to + 125°C Operating Temperature Range
=
r-III ANALOG
WDEVICES
Variable Resolution, Monolithic
Resolver-to-Digital Converter
2SBO
FEATURES
Monolithic (BiMOS II) Tracking RID Converter
4O-Pin DIL Package
10-. 12-. 14- and US-Bit Resolution Set by User
Ratiometric Conversion
Low-Power Consumption - 300mW typ
Dynamic Performance Set by User
High Max Tracking Rate 1040 rps (10 Bits)
Velocity Output
Military Temperatura Range Version
APPLICATIONS
Brushlass Motor Control
Process Control
Numericel Control of Machine Tools
Robotics
Axis Control
Military Servo Control
GENERAL DESCRIPTION
The 2S80 is a monolithic 10-, 12-, 14- or 16-bit tracking resolverto-digital converter contained in a 4O-pin, dual-in-line ceramic
package. It is manufactured on a BiMOS II process that combines
the advantages of CMOS logic and Bipolar high-accuracy linear
circuits on the same chip.
The converter allows users to select their own resolution and
dynamic performance with external components. This allows
the users great flexibility in defining the converter thilt best
suits their system requirements. The converter allows users to
select the resolution to be 10, 12, 14 or 16 bits and to track
resolver signals rotating at up to 1040 revs per second (62,400
rpm) when set to lO-bit resolution.
The 2S80 converts resolver format input signals into a parallel
natural binary digital word using a ratiometric tracking conversion
method. This ensures high-noise immunity and tolerance of lead
length when the converter is remote from the resolver.
2S80 PIN CONFIGURATION
REFERENCE lIP
DEMODIIP
2
AC ERROR
3
ANALOG GND
5
SIGNAlGND
II
SIN
+v.
PRODUCT HIGHLIGHTS
Monolithic. A one-chip solution reduces the package size required
and increases the reliability.
Resolution Set by User. Two control pins are used to select the
resolution of the 2S80 to be 10, 12, 14 or 16 bits allowing the
user to use the 2S80 with the optimum resolution for each
application.
Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion delay
and is insensitive to absolute signal levels. It also provides good
noise immunity and a tolerance to harmonic distortion on the
reference and input signals.
Dynamic Performance Set by the User. By selecting external
resistor and capacitor values the user can determine bandwidth,
maximum tracking rate and velocity scaling of the converter to
match the system requirements. The external components required
are alilow-cost preferred value resistors and capacitors and the
component values are easy to select using the simple instructions
given.
The 10-, 12-, 14- or 16-bit output word is in a three-state digital
logic form available in 2 bytes on the 16 output data lines. BYTE
SELECT, ENABLE and INHIBIT pins ensure easy data transfer
to 8- and 16-bit data buses, and outputs are provided to allow
for cycle or pitch counting in external counters.
Velocity Output. An analog signal proportional to velocity is
available and is linear to typically one percent. This can be used
in place of a velocity transducer in many applications to provide
loop stabilization and velocity feedback data.
An analog signal proportional to velocity is also available.
Low-Power Consumption. Typically only 300mW.
The 2S80 operates over 50 to 20,000 Hertz reference
frequency.
I
MODELS AVAILABLE
Information on the models available is given in the section
"Ordering Information."
SYNCHRO & RESOLVER CONVERTERS 5-65
•
SPECIFICATIONS (lJpi:aI at 2ft 1IIIess . . . . spacIiad)
I
Model
l.S80
UDits
Notes
TYPICAL CONVERTER PERFORMANCE (Connected as shown in Figure I)
Resolution
Accuracy ]D, SD Options
KD, TDOptions
LD,UDOptions
Tracking Rate Raoge
10-Bit Resolution
12-Bit Resolution
14-BitResolution
16-Bit Resolution
Operating Frequency Range
Repeatability of Position Output
Bandwidth
Velocity Signal
Linearity
Over Full Range
10,12, 140r 16
±8 +ILSB
±4 +ILSB
±2 +ILSB
Oto 1040
Ot026O
Ot065
Oto 16.25
50 to 20,000
I
User Selectable
bits
arcmins
arcmins
Accuracy will be affected by the offset at the
INTEGRATOR liP.
arcmins
rps
rps
rps
rps
Hz
LSB
User Selected, max rate limited to 1116 of the
reference frequency.
See "Using the Velocity Signal."
Zero Offset
±I
±I
+6
% of output
%
mV
SeeVCOspec.
With power supplies adjusted for best performance.
For max tracking rate range. Depends on VCOIIP
resistor (R6).
Zero Offset Tempco
-22
...Vi"C
For max tracking rate range. Depends on VCO liP
resistor (R6).
Gain Scaling Accuracy
Output Voltage
Noise and Ripple
at LSB Rate
Dynamic Ripple (Peak)
±IO
±S
%FSD
Vdc
2
1.5
mV
% of mean output
Reversion Error
See section "Using the Velocity Output."
ANALOG INPUTS
Protection
REFERENCE INPUT
Frequency
Voltage Level Nominal
Max
Input Bias Current
Input Impedance
All analog inputs are diode
protected against overvoltage at ± SV.
50-20,000
2
II
60 (typ), 150 (max)
>1
Hz
Vrms
V peak
nA
MO
SIGNAL INPUTS (SIN, COS)
Frequency
Allowable Phase Shift
(Signal to Reference)
Voltage Level
Input Bias Current
Input Impedance
Maximum VoltageNominaI
50-20,000
Hz
10
2, ±IO%
60 (typ), 150(max)
>1
±8
Degrees
Vrms
nA
MO
V
DlGlTALINPUTS
TTL Compatible
Except DATA LOAD and SHORT CYCLE INPUTS.
INmBIT
Senae
Time to Data Stable (After
Negative Going Edge of
INHIBIT)
DATA LOAD
Sense
Logic LO to inhibit
600
ns
Internally pulled up to + 12V.
Unconnected for normaioperation.
Logic LO allows data to be loaded
into the counters from the data lines.
Connect when multiplexing the 2SS0 or when using
as a control transformer.
Ensore data lines are in high impedance state
when loading data.
SHORT CYCLE INPUTS (SCI, SC2)
For IO-Bit Resolution
For 12-Bit Resolution
For I4-Bit Resolution
For I6-Bit Resolution
BYTE SELECT
Senae Logic HI
LogicLO
Time to Data Available
(After Change in State)
SCI
0
0
I
I
SC2
0
I
0
I
S MSBs selected on data lines I t08.
LS Byte selected on data lines 9 to 16.
LS Byte selected on data lines I to S
and 9 to 16.
150(typ),450(max)
5-66 SYNCHRO & RESOLVER CONVERTERS
Internally pulled up to + Vs.
Used to select the resolution of the converter.
0= Digital Ground. Drive low with open collector TTL.
I = Open Circuit (internally pulled up through IOOkO).
The size of the LS Byte will be between 2 and 8 bits depending
on the resolution selected.
ns
2S80
Model
2580
ENABLE
Sense
I
Unils
Notes
Logic LO to enable position outputs.
Logic HI position oUtPUIS in high
Enable and Disable Times
impedance state.
200 (typ), 550 (max)
ns
ANALOG OUTPUTS
Protection
Output Voltage Range, typ
max
min
Short-circuit output current
limited to ± SmA, ± 30%.
+9to -9
V
+ 10.5 to -10.5
V
+810-8
V
With ImA load.
DIGITAL OUTPUTS
Format
V L = +5V
V L =+12V
TTL Compatible
CMOS Compatible
Vollage on V L sets the voltage level of the digital outputs.
POSITION OUTPUTS
Number of Data Lines
Max Load
Three-slate natural binary
10,12, 140r 16
bits
16
3
LSTTL
Monotonicity
JD, KD, SO, TO Options
LD and UD Options
Guaranteed 1014 bils
Guaranteed to 16 bits
Format
Resolution
II
DIRECTION
Logic HI when counting up.
Logic LO when counting down.
Sense
Timing
Only changes, if required, at start of output
Max Load
position data cycle.
3
RIPPLE CLOCK
Sense
Timing
Width
Reset
Max Load
BUSY
Sense
LSTTL
Positive going edge when counting up
from all "Is" and when counting down
from all "Os" as data changes.
Edge occurs at least 3OOn8 before change
in DIR can occur.
300 (min)
ns
By sIan of nexl data update.
3
LSTTL
Logic HI when converter position output
changing.
Positive going edge SOns before change in
Timing
Max Load
position output.
300
200
600
3
ns
ns
ns
LSTTL
POWER SUPPLIES
Voltage Levels
+Vs
-Vs
+VL
+12 ± 10%
-12 ± 10%
+sto+14
V
V
V
12 (typ), 23 (max)
19 (typ), 30 (max)
0.5 (typ), 1.5 (max)
rnA
rnA
rnA
Oto +70
-ssto + 125
-6Oto + ISO
°C
°C
°C
0.2(5)
oz(grams)
Width
typ
min
max
The 2S80 may latch up if + Vsisapplied without - Vs.
Current
+Vs ,-Vs atI2V
+Vs , -Vs atl3.2V
+VL
GENERAL
Operating Temperature Range
JD, KD, LD Options
SO, TO, UD Options
Storage Temperature Range
(All Options)
Weight
Over operating temperature range.
SYNCHRO & RESOLVER CONVERTERS 5-67
CONVERTER CHARACTERISTICS
Model
2580
RATIO MULTIPLIER
Function
AC ERROR Output Scaling
IO-Bit Resolution
12-Bit Resolution
I4-BitResolution
160Bit Resolution
Accuracy
JD and SD Options
KD and TDOptions
LD and UD Options
Differential Nonlinearity
JD, KD, SD, TD Options
LD, UDOptions
Units
AC ERROR output represents the
difference between the angle at the SIN
and COS inputs compared to the position
output angle.
177.6
44.4
11.1
2.775
mVibit
mVlbit
mVlbit
mV/bit
±S
±4
±2
arcmins
arcmins
arcmins
1
Input Voltage Range
+Sto -S
nA
MO
V
INTEGRATOR
Open Loop Gain at 10kHz
Dead Zone Current
Input"Offset Voltage
Input Bias Current
Output Voltage Range (min)
Input Impedance
Input Voltage Range
60 ±3
100
I (typ), 5 (max)
60 (typ), 150(max)
+Sto -S
>1
+Sto -8
dB
nAlLSB
mV
nA
V
MO
V
VCO
Maximum Rate
VCORate
VCO Rate Tempco
Input Offset Voltage
Input Bias Current
Input Bias Current Tempco
Input Voltage Range
Linearity of Absolute Rate
Over Full Range
Over 0 to SO%of Max Range
Reversion Error
Sensitivity of Reversion Error
to Symmetty of Power Supplies
Specifications subject
[0
Specified over operating frequency range. Tested at 1kHz.
1.1
MHz
7.4 ± 10%
-0.05
I (typ), 5 (max)
120(typ),3OO(max)
-0.55
-8to+8
oM"<:
mV
nA
nArc
V
±I(typ), ±3(max)
+ I (max)
<3 (max)
8
%
%
%
%N of Asymmetry
kHzI~
change without notice.
CAUTION:
1. Correct polarity voltages must be maintained on the + Vs
and - Vs pins.
SYNCHRO & RESOL VER CONVERTERS
Guaranteed monotonic to 14 bits when connected in tracking mode.
Guaranteed monotonic to 16 bits when connected in tracking mode.
mV
ABSOLUTE MAXIMUM INPUTS (with respect to GND)
+VSI
OVto +14Vde
-Vs. . .
OV to -14V de
+VL
OVto +Vs
Reference
+ 14V to - Vs
Sin
+14V to -Vs
Cos •.•
+14V to -Vs
Any Logical Input
-O.4V to + VL de
Demodulator Input
+ 14V to - Vs
Integrator Input .
+ 14V to - Vs
veo Input .
+ 14V to - Vs
~68
Notes
See section "Integrator."
With ± 12V supplies.
Symmetrical power supplies.
See section "Using the Velocity Output."
2S80
OPERATION OF THE CONVERTER
When connected in a circuit such as is shown in Figure I the
2S80 operates as a tracking resolver-to-digital converter and
forms a type 2 closed loop system. This means that the output
will automatically follow the input for speeds up to the selected
maximum tracking rate. No convert command is necessary as
the conversion is initiated by each LSB increment of the input.
Each LSB increment of the converter initiates a BUSY pulse.
The 2S80 will not be damaged if the signal inputs are applied to
the converter without the power supplies and/or the reference.
Reference Voltage Level
The amplitude of the reference signal applied to the converter's
input is not critical, but care should be taken to ensure it is
kept below the absolute maximum voltage.
Because the conversion depends on the ratio of the input signals
the 2S80 is remarkably tolerant of input amplitude and frequency
(there is no need of an accurate, stable oscillator to produce the
reference signal). The inclusion of a phase sensitive detector in
the conversion loop ensures a high immunity to signals that are
not coherent or are in quadrature with the reference signal.
Harmonic Distortion
The amount of harmonic distortion allowable on the signal and
reference lines mainly depends on the type of transducer being
used.
Two major areas of the 2S80 specification can be selected by the
user to optimize the total system performance. The resolution of
the digital output is set by the state of the inputs SCI and SC2
to be 10, 12, 14 or 16 bits and the dynamic characteristics of
bandwidth and tracking rate are selected by the choice of external
components.
Position Output
The resolver shaft position is represented at the converter output
by a natural binary parallel digital word.
The 2S80 will not be damaged if the reference is supplied to the
converter without the power supplies and/or the signal inputs.
Square waveforms can be used but the input levels should be
adjusted so that the average value is 1. 9V rms. (For example, a
square wave should be 1.9V peak.)
Note: The figure specified of 10% harmonic distortion is for
calibration convenience only.
Velocity Signal
The tracking converter technique generates an internal signal at
the output of the integrator (the INTEGRATOR OUTPUT
Pin) that is proportional to the rate of change of the input angle.
This is a dc analog output referred to as the VELOCITY signal.
Both the RIPPLE CLOCK pulse and the DIRECTION data
are unaffected by the application of the INHIBIT.
DC Error Signal
The signal at the output of the phase sensitive detector
(DEMODULATOR OUTPUT) is the signal to be nulled by the
tracking loop and is therefore proportional to the error between
the input angle and the output digital angle. This is the DC
ERROR of the converter; and as the converter is a type 2 servo
loop, it will increase if the output fails to track the input for any
reason. It is an indication that the input has exceeded the maximum
tracking rate of the converter or, due to some internal malfunction,
the converter is unable to reach a null. By connecting two external
comparators, this voltage can be used as a "built-in test".
The static accuracy quoted is the worst case error that can occur
over the full operating temperature excluding the effect of offset
signals at the INTEGRATOR INPUT (which can be trimmed
out) and with the following conditions: input signal amplitudes
are within 5% of the nominal values; signal and reference frequency
is within the specified operating range; phase shift between
signal and reference is less than 10 degrees; signal and reference
waveform harmonic distortion is less than 10%.
CONNECTING THE CONVERTER
The power supply voltages connected to + Vs and - Vspins
should be ± 12V and must not be reversed. If one rail is connected
without the other, the converter will not operate and may "latch
up". In this case, the removal of both rails is necessary in order
for the converter to function correctly again. The voltage applied
to VL can be +SVto +Vs.
These test conditions are selected primarily to establish a repeatable acceptance test procedure which can be traced to national
standards. In practice, the 2S80 can be used well outside
these operating conditions providing the following points are
observed.
It is suggested that decoupJing capacitors are connected in parallel
between the power lines + Vs, - Vs and ANALOG GROUND
adjacent to the converter. Suggested values of 100nF (ceramic)
and 1Oj1.F (tantalum). Decoupling capacitors of 100nF and 1Oj1.F
should also be connected between + VL and DIGITAL GROUND
adjacent to the converter.
As the digital output of the converter passes through the major
carries, i.e., all "Is" to all "Os" or the converse, a RIPPLE
CLOCK (RC) logic output is initiated indicating that a revolution
or a pitch of the input has been completed.
The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in advance
of a RIPPLE CLOCK pulse and, as it is internally latched, only
changes with a change in direction.
Signal Amplitude (Sine and Cosine Inputs)
The amplitude of the signal inputs should be maintained within
5% of the nominal values if full performance is required from
the velocity signal.
The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a dramatic loss in accuracy due to internal overload.
Reducing level will result in a steady decline in accuracy. With
the signal levels at 50% of the correct value, the angular error
will increase to an amount equivalent to 1.3LSB. At this level
the repeatability will also degrade to 2LSB and the dynamic
response will also change, since the dynamic characteristics are
proportional to the signal level.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
shown in Figure 7 and described in section "CONNECTING
THE RESOLVER". The two signal ground wires from the
resolver should be joined at the SIGNAL GROUND pin of the
converter to minimize the coupling between the sine and cosine
signals. For this reason it is also recommended that the resolver
is connected using twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GROUND and ANALOG GROUND are connected
SYNCHRO & RESOL VER CONVERTERS 5-69
II
REFERENCE
UP
OFFSET ADJUST
R9
HF FILTER
+12V~-12V
R8
SIN
PHASE
SENSITIVE
DETECTOR
veo + DATA
VCO
i/F
TRANSFER LOGIC
-12V
R7
;r,C6
DATA
LOAD
SC1
+5V
ENABLE
DIG
GND
BUSY
DIRN
INHIBIT
16 DATA BITS
Figure 7. 2580 Connection Diagram
internally. ANALOG GROUND and DIGITAL GROUND
must be connected externally.
The external components required should be connected as shown
in Figure 1.
SELECTING THE RESOLUTION
The resolution of the 2S80 can be selected to be 10, 12, 14 or
16 bits by use of the short cycling inputs SCI and SC2. The
required resolution can be selected as shown in the specification
section.
The choice of resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO respectively
(see section "COMPONENT SELECTION"). If the resolution
is changed, then new values of R4 and R6 must be switched
into the circuit.
Note: When changing resolution under dynamic conditions, a
period of uncertainty will exist before position' and velocity data
is valid.
COMPONENT SELECTION
The following instructions describe how to select the external
components to the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest "preferred
value" component should be used and a 5% tolerance will not
degrade the overall performance of the convener. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. The components should
be connected as. shown in Figure 1.
For more detailed information and explanation, see
section "CIRCUIT FUNCTIONS AND DYNAMIC
PERFORMANCE".
1. HF Filter (RI, R2, CI, C2)
5-70 SYNCHRO & RESOLVER CONVERTERS
The function of the HF filter is to reduce the amount of
noise present on the signal inputs to the 2S80, reaching the
Phase Sensitive Detector and affecting the outputs. RI and
C2 may be omitted - in which case R2 = R3 and CI = C3,
calculated below - but their use is. particularly recommended
if noise from a switch mode motor drive is present.
Values should be chosen so that
RI = R2,.:; 56kO
CI
= C2 =
1
2'11' RI fREF
and fREF = Reference frequency
(Hz)
This filter gives an attenuation of 3 times at the input to the
phase sensitive detector.
2. Gain Scaling Resistor (R4)
If RI, C2 are fitted then:
Eoc
1
R4 = 100 x 10-9 X 3 n
If Rl, C2 are not fitted then:
Eoc
R4 = 100 x 10- 9 n
where Eoc = 160 x 10 - 3 for 10 bits resolution
40 x 10- 3 for 12 bits
10 x 10- 3 for 14 bits
2.5 x 10- 3 for 16 bits
Scaling at the DC ERROR in volts
3. AC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,
2S80
R3 = lOOldl
PIN FUNCTIONS
I
4. Maximum Tracking Rate (R6)
The VCO input resistor R6 sets the maximum tracking rate
of the converter and hence the velocity scaling as at the max
tracking rate the velocity output will be 8V.
Decide on your required maximum tracking rate, "T", in
revolutions per second. Note that "T" must not exceed the
specified maximum tracking rate or 1116 of the reference
frequency.
R6 = 5.92 x IQ7 kO
Txp
where p = bit per rev
1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
5. Closed Loop Bandwidth Selection (C4, C5, R5)
a. Choose the Closed Loop 3dB Bandwidth (fBw) required
ensuring that
fREF
> 2.5
X fBw
Typical values may be 100Hz for 400Hz reference frequency
and 500 to 1000Hz for 5kHz reference frequency.
REFERENCE lIP
DEMODIIP
ACERROROIP
COS
ANALOG GROUND
SIGNAL GROUND
SIN
+Vs
BIT 1- BIT 16
VL
ENABLE
BYTE SELECT
INHIBIT
DIGITAL GROUND
SCI, Scl
DATA LOAD
b. Select C4 so that
C4 _ 20.2
- R6
X
10- 3
BUSY
X fBw2
with R6 in kO and fBw in Hz selected above.
DIRECTION
c. C5 is given by
C5=5xC4
RIPPLE CLOCK
d. RS is given by
R5 =
2 x
'TI' X
4
0
f Bw x C5
6. VCO Phase Compensation
The following values of C6 and R7 should be fitted.
C6 = 470pF
R7 = 680
7. Offset Adjust
Offset and bias current at the integrator input can cause an
additional positional offset at the output of the converter of 1
arc min typical, 5.3 arc mins maximum. If this can be tolerated,
then R8 and R9 can be omitted from the circuit.
If fitted, the following values of R8 and R9 should be used:
R8 = 4.7MO, R9 = IMO potentiometer.
To adjust for zero offset, ensure the resolver is disconnected
and all the other external components are fitted. Connect the
COS pin to the REFERENCE INPUT and the SIN pin to
the SIGNAL GROUND and with the power and reference
applied, adjust the potentiometer to give all "Os" on the
digital output bits.
The potentiometer may be replaced by select on test resistors
if preferred.
-Vs
VCO lIP
INTEGRATOR lIP
INTEGRATOR OIP
DEMODOIP
Input pin for the Reference Signal.
Demodulator input pin.
Output of Ratio Multiplier.
Input pin for Cosine signal from
resolver.
Power ground.
Ground pin for signals from resolver.
Input pin for Sine signal from
resolver.
Main positive power supply.
Parallel output data bits.
Logic power supply.
Logic "HI" sets the output data bits
to a high impedance state, a logic
"LO" presents the data in the latches
to the output pins.
Selects the data output bits presented
on data bits I to 8. Logic "HI" will
present the 8 most significant bits; a
logic "LO" will present the least significant byte.
Logic "LO" inhibits the data transfer
from the counter to the output
latches.
Ground pin for digital circuitry.
Logic inputs used for selecting the
resolution of the converter.
Logic "LO" allows data to be loaded
into the counters.
Converter BUSY. A logic "HI" indicates that the output latches are being
updated and data should not be
transferred.
Logic output indicating the direction
of rotation of the input signals.
A negative going pulse whenever the
output of the converter changes from
all "Is" top all "Os" or the converse.
Main negative power supply.
Input pin to VCO.
Input pin of Integrator.
Output pin of Integrator.
Output pin of Demodulator.
DATA TRANSFER
To transfer data the INHIBI'f input should be used. The data
will be valid 600ns after the application of a logic "Lo" to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic "Hi"
state to enable the output latches to be updated.
BUSY Output:
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL levels. A BUSY pulse is initiated each time the input
moves by the analog equivalent of an LSB and the internal
counter is incremented or decremented.
SYNCHRO & RESOLVER CONVERTERS 5-71
•
INHIBIT Input:
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
ENABLE Input:
The ENABLE input determines the state of the output data. A
logic "Hi" maintains the output data pins in the high impedance
condition, and application of a logic "Lo" presents the data in
the latches to the output pins. The operation of the ENABLE
has no effect on the conversion process.
BYTE SELECT Input:
The BYTE SELECT input selects the byte of position data to
be presented at the data output bits 1 to 8. The least significant
byte will be presented on data output bits 9 to 16 (with the
ENABLE input taken to a logic "Lo") regardless of the state of
the BYTE SELECT pin. Note that when the 2S80 is used with
a resolution less than 16 bits the unused data lines are pulled to
a iogic "Lo". A logic "Hi" on the BYTE SELECT input will
present the eight most significant data bits on data output Bits I
and 8. A logic "Lo" will present the least significant byte on
data outputs I to 8, i.e., data outputs 1 to 8 will duplicate data
outputs 9 to 16.
The operation of the BYTE SELECT has no effect on the
conversion process of the converter.
RIPPLE CLOCK Output:
As the output of the converter passes through the major carry,
i.e., all "Is" to all "Os" or the converse, a positive going edge
on the RIPPLE CLOCK (RC) output is initiated indicating that
a revolution, or a pitch, of the input has been completed. The
pulse has a minimum width of 300ns and is reset by the start of
the next data update cycle.
DIRECTION Output:
The DIRECTION (DIR) logic output indicates the direction of
the input rotation, and this data is valid in advance of the RIPPLE
CLOCK pulse and stays valid until the direction changes. This
is the start of the next data update cycle - if the direction of
rotation of the inputs has changed - and will be at least 300ns
after the rising edge of the RIPPLE clock (see Figure 2).
The DIR and RC outputs are unaffected by the state of the
INHIBIT input.
CIRCUIT FUNCTIONS AND DYNAMIC
PERFORMANCE
The 2S80 allows the user great flexibility in choosing the dynamic
characteristics of the resolver-to-digital conversion to ensure the
optimum system performance. The characteristics are set by the
extema1 components shown in Figure I, and the section "COMPONENT SELECTION" explains how to select desired maximum
tracking rate and bandwidth values. The following paragraphs
explain in greater detail the circuit of the 2S80 and the variations
in the dynamic performance available to the user.
Loop Compensation
The 2S80 (connected as shown in Figure I) behaves as a type 2
tracking servo loop where the VCO/counter combination and
the Integrator perform the two integration functions inherent in
a type 2 loop.
Additional compensation in the form of a pole/zero pair is required
to stabilize any type 2 loop to avoid the loop gain characteristic
crossing the 0dB axis with 180" of additional phase lag, as shown
in Figure 4. This compensation is implemented by the integrator
components (R4, C4, RS, C5).
The overall response of such a system is that of a unity gain
second order low pass filter, with the angle of the resolver as
the input and the digital position data as the output.
The 2S80 does not have to be connected as tracking converter,
parts of the circuit can be used independently. This is particularily
true of the Ratio Multiplier which can be used as a control
transformer .
A block diagram of the 2S80 is given in Figure 3.
Ratio Multiplier
The Ratio Multiplier is the input section of the 2S80 and compares
the signal from the resolver inputs, 9, to the digital angle, <1>,
held in the counter. Any difference between these two angles
results in an analog voltage at the AC ERROR OUTPUT. This
circuit function has historically been called a ''Control Transformer" as it was originally performed by a mechanical device
known by that name.
The AC ERROR signal is given by
Al sin (9-<1» sinoot.
where 00 = 2'11' fREF
fREF=reference frequency
AI, the gain of the ratio multiplier stage is 14.5 times
So for 2V rms inputs signals
AC ERROR output in voltsl(bit of error)
= 2xsin
BUSY
DATA
~_ _ _
VA_L_ID_ _",,",XI...__V:;,A=lID=--_
~~:SO::PUT~ n:~~~VSTARTOFNEXTDATA
~
RIPPLE
CLOCK IRC)
DI.
______
~V
~
300nsmin
-----t
--------~t~----START OF NEXT DATA UPDATE
Figure 2. Timing Diagram
5-72 SYNCHRO & RESOLVER CONVERTERS
e:)
x Al
where p = bits per rev
1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
Giving AC ERROR output
= 178mV rmsIbit @ 10 bits resolution
44.5mV rmslbit @ 12 bits
= 1l.125mV rmsIbit @ 14 bits
2.78mV rmsIbit @ 16 bits
The Ratio Multiplier will operate in exactly the same way whether
the 2S80 is connected as a tracking converter or as a control
transformer, where data is preset into the counters using the
DATA LOAD pin.
2S80
HF Filter
The AC ERROR OUTPUT may be fed to the PSD via a simple
ac coupling network (R2, CI) to remove any DC offset at this
point. Note, however, that the PSD of the 2S80 is a wideband
demodulator and is capable of aliasing HF noise down to within
the loop bandwidth. This is most likely to happen where the
resolver is situated in particularly noisy environments, and the
user is advised to fit a simple HF filter RI, C2 prior to the
phase sensitive demodulator.
The attenuation and frequency response of a fIlter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. The suggested fIlter (RI, CI, R2, C2) is
shown in Figure I and gives an attenuation at the reference
frequency (fREF) of 3 times at the input to the phase sensitive
demodulator.
Values of the components used in the fIlter must be chosen to
ensure that the phase shift at fREF is within the allowable signal
to reference phase shift of the converter.
Phase Sensitive Demodulator
The Phase Sensitive Demodulator is effectively ideal and develops
a mean dc output at the DEMODULATOR OUTPUT pin of
±2
v'2
1T
x (DEMODULATOR INPUT rms voltage)
for sinusoidal signals in phase or antiphase with the reference
(for a square wave the DEMODULATOR OUTPUT voltage
will equal the DEMODULATOR INPUT). This provides a
signa! at the DEMODULATOR OUTPUT which is a dc level
proportional to the positional error of the converter.
DC Error Scaling = 160mVibit (10 bits resolution)
4OmV/bit (12 bits resolution)
IOmV/bit (14 bits resolution)
2.5mVlbit (16 bits resolution)
When the tracking loop is closed, this error is nulled to zero
unless the converter input angle is accelerating.
Integrator
The integrator components (R4, C4, R5, C5) are external to the
2S80 to allow the user to determine the optimum dynamic characteristics for any given application. The section "COMPONENT
SELECTION" explains how to select components for a chosen
bandwidth.
Since the output from the integrator is fed to the VCO INPUT,
it is proportional to velocity (rate of change of output angle) and
can be scaled by selection of R6, the VCO input resistor. This
is explained in the section "VOLTAGE CONTROLLED
OSCILLATOR (VCO)" below.
To prevent the converter from "flickering" (i.e., continually
toggling by ± I bit when the quantized digital angle, cj>, is not
an exact representation of the input angle, 9) feedback is internally
applied from the VCO to the integrator input to ensure that the
VCO will only update the counter when the error is greater than
or equal to I bit. In order to ensure that this feedback "hysteresis"
is set to ILSB the input current to the integrator must be scaled
~o be lOOnAlbit. So,
R4 = DC Error Scaling (mVlbit)
100 (nA/bit)
added for each 100nA of input bias current. The method of
adjusting out this offset is given in the section "COMPONENT
SELECTION".
Voltage Controlled Oscillator (VCO)
The VCO is essentially a simple integrator feeding a pair of dc
level comparators. Whenever the integrator output reaches one
of the comparator threshold voltages, a fixed charge is injected
into the integrator input to balance the input current. At the
same time the counter is clocked either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the VCO.
During the reset period the input continues to be integrated
although the reset period is constant at 4OOns.
The VCO rate is fixed for a given input current by the VCO
scaling factor,
=
7.4kHz/jLA
The tracking rate in rps per jLA of VCO input current can be
found by dividing the VCO scaling factor by the number of
LSB changes per rev (i.e., 4096 for 12-bit resolution).
The input resistor R6 determines the scaling between the converter
velocity signal voltage at the INTEGRATOR OUTPUT pin and
the VCO input current. Thus to achieve a 5V output at 100 rps
(6000 rpm) and 12-bit resolution the VCO input current must
be:
(100 x 40%)/(7400) = 55.3jLA
Thus, R6 would be set to: 5/(55.3 x 10- 6) = 9OkO
The velocity offset voltage depends on the VCO input resistor,
R6, and the VCO bias current and is given by
Velocity Offset Voltage = R6 x (VCO bias current)
The temperature coefficient of this offset is given by
Velocity Offset Tempco = R6 x (VCO bias current
tempco)
where the VCO bias current tempco is typically -0.55nArC.
The maximum recommended rate for the VCO is I.IMHz which
sets the maximum possible tracking rate.
Since the maximum voltage swing available at the integrator
output is ± 8V, this implies that the minimum value for R6 is
54k!l. As
Max Current
Min Value
1.1
= 7.4
X 106
x 103
~ = 149
: 10
= 149jLA
6
= 54kO
R5
C5
sin8sinwt
cas
Q sin wt
MO
Any offset at the input of the integrator will affect the accuracy
of the conversion as it will be treated as an error signal and
offset the digital output. One LSB of extra error will be
Figure 3. 2580 Functional Diagram
SYNCHRO & RESOLVER CONVERTERS 5-73
•
Transfer FUDCtion
By selecting components Using the method outlined in the section
"Component Selection" the converter will have a critically damped
time response and maximum phase matgin. The Cosed-Loop
Transfer Function is given by:
80UT
14 (1 + liN)
8 IN = (liN + 2.4) (liNz + 3.4 liN + 5.8)
where, IN, the normalized frequency variable is
2 s
liN = 1i faw
12
and fsw is the closed-loop 3dB bandwidth (selected by the choice
of external components).
The acceleration constsnt, KA, is given approximately by
KA = 6x(fBw)z
sec- z
The normalized gain and phase diagrams are given in Figures 4
and 5.
The amall signal step response is shown in Figure 6. The time
from the step to the first peak is t 1 and the tz is the time from
the step until the converter as settled to lLSB. The times tl and
t2 are given approximately by
1
tl = faw
5
tz = faw x
...
~
3
.......- I-"'""
~
"
where R=resolution, i.e., 10, 12, 14 or 16.
\
" -3
-6
-"
-12
The large signal step response (for steps greater than 10 degrees)
applies when the error voltage will exceed the linear range of
the converter. Typically the converter will take 3 times longer
to reach the first peak for a 179 degrees step.
1\
\
I
_-'--_'------..L._-'--_-'---->J\
LI
O.02fBw O.04faw
O·1few O.2faw O.4faw
FREQUENCY
R
12
taw
2'BW
Figure 4. 2S80 Gain Plot
The response to a Velocity step, the Velocity output will exhibit
the same time response characteristics as outlined above for the
position output.
OUTPUT
POSITION
180
135
90
~
45
~
0
D.
-45
"=---1
--.......
"'"
-90
-135
1'-.....
TIME
-180
O.02faw O.04faw
~ICATIONS
O.1faw
O.2'aw
O.4fsw
faw
ztew
Figure 5. 2S80 Phase Plot
Figure 6. 2S80 Small Step Response
_________________________________________________________________
USING THE 2S8O AS A CONTROL TRANSFORMER
The ratio multiplier section of the 2S80 can be used independently
to the rest of the converter to perform the function of Control
Transformer. In this mode the signal from the resolver inputs,
6, is compared to a digital angle, "', loaded into the counters.
Any difference between these two angles results in an analog
voltage at the AC ERROR OUTPUT. To use the device in this
way the DATA LOAD pin is used.
Applying a logic "Lo" to the DATA LOAD pin will allow data
to be loaded into the counters of the converter from the data
lines. It is important that the data lines are placed in the. high
impedance state before loading data.
To operate the 2S80 as a tracking resolver-to-digital converter
the DATA LOAD pin should be left unconnected as it is pulled
high internally to + 12V.
CAUSES OF ADDITIONAL ERROR
Integrator OffSet
Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator as it will
5-74 SYNCHRO & RESOLVER CONVERTERS
be treated as an error signal. This error will be typically 1 arc
minute over the operating temperature range.
A description of how to adjust for zero offset is given in the
section "COMPONENT SELECTION" and the circuit required
is shown in Figure 1.
Differential Phase Shift
Phase shift between the sine and the cosine signals from the
resolver is known as differential phase shift and can cause static
error. Some differential phase shift will be present on all resolvers
as a result of coupling. A-smaIl resolver residual voltage (quadrature
Voltage) indicates a small differential phase shift. Additional
phase shift can be introduced if the sine channel wires and the
cosine channel wires are treated differently. For instance, different
cable lengths or different loads could cause differential phase
shift.
The additional error caused by differential phase shift on the
input signals approximates to
Error = 0.53 a.b arc minutes
where a = differential phase shift in degrees
and b = signal to reference phase shift in degrees.
2S80
This error can be minimized by choosing a resolver with a small
residual voltge, ensuring that the sine and cosine signals are
handled identically and removing the reference phase shift (see
section "CONNECTING THE RESOLVER"). By taking these
precautions, the extra error can be made insignificant.
A resolver is chosen that has a low residual voltage, i.e., a
small signal in quadrature with the reference.
Components are selected to operate the 2S80 with the lowest
acceptable bandwidth.
Feedthrough of the reference frequency should be removed
by a filter on the velocity signal.
Resolver Phase Shift
Under static operating conditions phase shift between the reference
and the signal lines alone will not theoretically affect the converter's
static accuracy.
The signal voltages are 2V rms to prevent a ripple at the
LSB switching rate. This is because the ILSB of analog
feedback that prevents the output from flickering will be
incorrectly scaled (see section "INTEGRATOR").
However, most resolvers exhibit a phase shift between the signal
and the reference. This phase shift will give rise under dynamic
conditions to an additional error defined by:
If the above precautions are taken, a very good noise and
ripple performance is obtainable making the 2S80 velocity
signal usable in very noisy environments, for instance in
motor drive applications with PWM switching noise.
Shaft Speed (rps) x Phase Shift (Degs)
Reference Frequency
The positional error curve of the converter and the resolver
will result in an apparent acceleration when the resolver is
rotating at a constant velocity. The main result of this will be •
a ripple on the velocity signal twice per revolution.
For example, for a phase shift of 20 degrees, a shaft rotation of
22rps and a reference frequency of 5kHz, the converter will
exhibit an additional error of:
22 x 20
~
= 0.088 degrees
This effect can be eliminated by putting a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver (see section "CONNECTING THE RESOLVER").
NOTE: Capacitive and inductive crosstalk in the signal and
reference leads and wiring can cause similar problems.
USING THE VELOCITY SIGNAL
The signal at the INTEGRATOR OUTPUT pin relative to the
ANALOG GROUND pin is an analog voltage proportional to
the rate of change of the input angle. This signal can be used to
stabilize servo loops or in place of a velocity transducer. Although
the conversion loop of the 2S80 includes a digital section there
is an additional totally analog feedback loop around the velocity
signal. This ensures that there is no digital effects on the output
signal and that the loop is closed even when the input signals
are such that the digital output does not change.
A better quality velocity signal will be achieved if the following
points are considered.
1. Protection.
The velocity signal should be buffered before use.
2. Reversion Error.
If necessaty, the reversion error can be reduced by a simple
trimming circuit. Reversion error, or side-to-side nonlinearity,
is a result of differences in the up and down rates of the
VCO. The reversion error can be nulled by varying one
supply rail relative to the other.
3. Ripple and Noise.
Noise on the input signals to the converter is the major
cause of noise on the velocity signal. This can be reduced
to a minimum if the following precautions are taken:
The resolver is connected to the converter using separate
screened twisted pair cable for the sine, cosine and reference
signals.
Care is taken to reduce the external noise wherever possible.
An HF filter is fitted before the Phase Sensitive Demodulator
(as described in the section HF FILTER).
CONNECTING THE RESOLVER
The recommended connection circuit is shown in Figure 7.
---- f::::J--01-t:)x'ri
r- TW-L-~C-~-:~-~-i~-~. .J=f ~~~-
2S80
.. ;:" ~t====
R2
51·
RESOLVER
----
7=X:::J«:::)l(::::'..-----
POWER RETURN
Figure 7. Connecting the 2580 to a Resolver
In cases where the reference phase relative to the input signals
from the resolver requires adjustment, this can be easily achieved
by varying the value of the resistor R2 of the HF filter (see
Figure I).
Assuming that RI =R2 = Rand CI = C2 = C
I
and Reference Frequency = 21T R C
By altering the value of R2 the phase of the reference relative to
the input signals will change in an approximately linear manner
for phase shifts of up to 10 degrees.
Increasing R2 by 10% introduces a phase lag of 2 degrees.
Decreasing R2 by 10% introduces a phase lead of 2 degrees.
For signal and reference voltages greater than 2V rms a simple
voltage divider circuit of resistors can be used to generate the
correct signal level at the converter. Care should be taken to
ensure that the ratios of the resistors between the sine signal
line and ground and the cosine signal line and ground are the
same. Any difference will result in an additional position error.
SYNCHRO & RESOL VER CONVERTERS ~75
1Mn
4.7MU
'5
kn
REFERENCE
INPUT
t-4--I--+---{j,LJ •
PIN'
151d1
COSHIGH
RESOLVER
SIGNALS
REFLOW
-+-+--------;:IJ
-+-.-.....- - - - - - - ; I ' l
100nF
l~J----------t--_-'2V
COS LOW
SIN LOW
SIN HIGH
-+___--'
2580
TOP VIEW
INottoScalel
+,2V ....- -_ _ _-'
DATA
OUTPUT
r----.....---~-OV
i l l } - - - - -.....-
+5V
l ==~====~==::JII
LSB _ _ _ _ _ _ _ _ _ _- - '
Figure 8.
360
TYPICAL CIRCUIT CONFIGURATION
315
Figure 8 shows a typical circuit configuration for the 2S80 in a
12-bit resolution mode. Values of the external components have
been chosen for a reference frequency of 5kHz and to give a
maximum tracking rate of 260 rps and a bandwidth of 520Hz.
The resistors are 0.125W, 5% tolerance preferred values. The
capacitors are lOOV ceramic, 10% tolerance components.
w
w 270
a:
Cl 225
w
Q
I
/
180
II
w
135
Cl
Z
....I
An offset adjustment potentiometer is included at the integrator
input to remove the offset error. Obviously this can be left out
of the circuit if the extra inaccuracy can be tolerated.
ct
90
I
./
45
0
4
'
8
12
16
20
24
TIME- ms
Figure 9. Large Step Response Curves for Typical Circuit
Shown in Figure 8
ORDERING INFORMATION
Operating
Temperature
Model
2S80JO
2S80KO
2S80LO
2S80S0
2S80TO
2S80UO
Accuracy
(Arcmins)
8
4
2
8
4
2
Range
Package
("C)
Option·
Oto +70
Oto +70
Oto +70
0-40
0-40
0-40
-55to+125
- 55 to + 125
- 55 to + 125
0-40
0-40
0-40
·See Section 14 for package outline information.
5-76 SYNCHRO & RESOLVER CONVERTERS
1IIIIIIII ANALOG
WDEVICES
FEATURES
Low Cost
Monolithic Construction
28-Pin DIP Package
Ratiomatric Conversion
Low Power Consumption: 300mW typical
Dynamic Performance Set by User
High Tracking Rate: 260 rps max
Velocity Output
Low-Cost, Monolithic 12-Bit
Resolver-to-Digital Converter
2S81 I
2S81 PIN CONFIGURATION
APPUCATIONS
Brushless Motor Control
Programmable Limit Switches
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
GENERAL DESCRIPTION
The 2S81 is a monolithic 12-bit tracking resolver-to-digital converter packaged in a 28-pin DIP. It is manufactured in Analog
Devices' proprietary BiMOS II process which combines highdensity and low-power CMOS logic with high-accuracy bipolar
linear circuitry.
The converter can track resolver signals at rates up to 260 revolutions per second (15,600 rpm). Users can set the converter's
dynamic performance with external components, providing
greater flexibility in tailoring the converter to suit system
requirements.
The 2S81 converts resolver format input signals into a 12-bit
natural binary digital word using a ratiometric tracking conversion
method. This ensures high noise immunity and tolerance of
long lead lengths when the converter is located remotely from
the resolver. The 12-bit output word is in a three-state digital
logic form, available in 2 bytes on the 8 output data lines. BYTE
SELECT and INHIBIT pins ensure easy data transfer. In addition,
output pins are available to permit the use of extemal counters
to count cycle or pitch. An analog signal proportional to velocity
is also available.
II
PRODUCT HIGHLIGHTS
Monolithic: The single-chip construction reduces package size
and increases inherent reliability.
Low Cost: The use of a single integrated circuit to perform the
conversion ensures low cost.
Ratiometric Tracking Conversion: Conversion technique provides continuous output position data without conversion delay
and is insensitive to absolute signal levels. It also provides good
noise immunity and tolerates harmonic distortion in the reference
and input signals.
Dynamic Performance Set by User: By selecting external resistor
and capacitor values, the user can determine bandwidth, maximum
tracking rate and velocity scaling of the converter to match the
system reqnirements. The extemal components required are all
low-cost preferred value resistors and capacitors.
Velocity Output: An analog signal proportional to velocity is
linear to 1% (typical). This can be used in place of a velocity
transducer in many applications to provide loop stabilization
and velocity feedback data.
MODELS AVAILABLE
The 2S81 operates over 0 to + 70°C temperature range. The
reference frequency can range from 400 to 20,OOOHz.
SYNCHRO & RESOLVER CONVERTERS 5-77
SPEC IFICAli ONS (typical at 25"1: unIass otherwise specified)
2S81JD
Uoits
Accuracy
12
±30 + ILSB
Bits
Arc Minutes
Tracking Rate Range
Ot0260(max)
rps
Operating Frequency Range
Repeatability of Position Output
Bandwidth
400 to 20,000
I
User Selecmble
Hz
LSB
Velocity Signal
Linearity Over Full Range
Over 0 to 6000 rpm
Reversion Error
± I (typ), ±3(max)
±I(max)
±S(max)
%
%
%
±2(max)
%
Model
OVERALL CONVERTER SPECIFICATIONS
(CONNECTED AS SHOWN INFIGUREJ)
Resolution
Zero Offset (for 260 rps Max
Tracking Rate)
Zero Offset Tempco (for 260 rps Max
Tracking Rate)
Gain Scaling Accurl\CY
Output Volll\ge
Noise and Ripple (I\v-pk)
ANALOG INPUTS
Protection
Depends on veo iiP Resistor (R6).
-22
fl.vrc
Depends on VCO I1PResistor (R6).
±IO
%FSD
Vdc
%
See Section "Using the Velocity Signal"
+ 16 (max)
±S
1.5
All Analog Inputs Are Diode Protected
Against Overvoltage at ± SV
Hz
Vrms
V peak
nA
MO
SIGNAL INPUTS (SIN, COS)
Frequency
Allowable Phase Shift (Signal to Reference)
Volll\ge Level
Input Bias Current
Input Impedance
Maximum Volmge Nominal
400-20,000
10
2,±10%
60 (typ), 150 (max)
>1
±S
Hz
Degrees
Vrms
nA
MO
V
DIGITAL INPUTS
TTL-Compatible
Dam Available
(Mter Change in State)
ENABLE
Sense
Enable and Disable Times
ANALOG OUTPUTS
Protection
Output Voltage Range (typ)
(max)
(min)
DIGITAL OUTPUTS
Format
Symmetry of - V sand + Vs Power
Supplies to be within ± S%~
With - V s Adjusted for Best
Performance.
mV
1. 6 (t"jp)
400-20,000
2
II
6O(typ),150(max)
>1
BYTE SELECT
Sense
Accurl\cy will be Affected by the Offset
at the INTEGRATOR liP.
User Selected, Max Rate Limited at
Lower Operating Frequencies.
See "Using the Velocity Signal"
REFERENCE INPUT
Frequency
Voltage Level Nominal
max
Input Bias Current
Input Impedance
INHIBIT
Sense
Time to Dam Stable (After Negative Going
Edge ofiNHIBIT)
Notes
Logic LO to Inhibit
I
fl.s
Logic HI Selects SMSBs on Pins S-15
Logic LO Selects 4LSBs on Pins S-II;
Pins 12-15 Are Logic LO
150(typ),450(max)
ns
Logic LO to Enable Position Outputs
Logic HI Position Outputs in High Impedance Smte
200 (typ), 550 (max)
ns
Short Circuit Output Current Limited to ± SmA, ± 30%
Output Volmge Range Will Be Degraded for Currents> 3mA
+9to -9
V
+ 10.5 to -10.5
V
+Sto -S
V
V L = + SV TTL Compatible
VL = + 12V CMOS Compatible
5-78 SYNCHRO & RESOLVER CONVERTERS
Voltage on V L Sets the Volmge
Level of Digital Outputs.
2S81
Model
2S81JO
POSITION OUTPUTS
Format
Resolution
Number of Oata Lines
Max Load
Monotonicity
Three-State Natural Binary
12
Bits
8
3
LSTTL
Guaranteed
DIRECTION (DIR)
Sense
Timing
Max Load
RIPPLE CLOCK (RC)
Sense
Timing
Width (min)
Reset
Max Load
BUSY
Sense
Timing
Width (typ)
(min)
(max)
Load, (max)
Units
GENERAL
Operating Temperature Range
Storage Temperature Range
Weight
Pins8to 15
Logic "HI" When Counting Up
Logic "LO" When Counting Down
Only Changes, if Required, at Start of
Output Position Data Update Cycle
LSTTL
3
Positive Going Edge When Counting Up from
AU "1s" and When Counting Down from All "Os"
as Data Changes
Edge Occurs at Least 300ns Before Change in
DIR Can Occur
300
ns
By Start of Next Data Update
3
LSTTL
Logic "HI" When Converter Position Output Changing
Positive Going Edge sOns Before Change in Position Output
300
ns
200
ns
ns
600
3
LSTTL
The Device May Latch Up If + Vs
is Applied without - Vs ,
POWER SUPPLIES
Voltage Levels
+Vs
-Vs
+VL 5
Current
+Vs
-Vs
+VL
Power Dissipation
Notes
+ 12 ±IO%
-12 ±Io%
+5to+14
V
V
V
12 (typ), 23 (max)
12 (typ), 23 (max)
0,5 (typ), 1.5 (max)
300 (typ), 600 (max)
rnA
mA
rnA
mW
Oto +70
-65to + ISO
0,2(5)
·C
·C
Oz,(Grams)
SYNCHRO & RESOL VER CONVERTERS 5-79
II
Model
2S81jD
CONVERTER CHARACTERISTICS
RATIO MULTIPLIER
Function
Units
Notes
AC ERROR Output Represents the Difference
between the Angle at the SIN and COS Inputs
Compared to the Position Output Angle
mVlBit
44.4
30
Are Minutes
± 0.25 (max)
LSB
AC Error Output Scaling
Accuracy
Differential Nonlinearity
PHASE SENSITIVE DETECTOR
Specified Over the Operating
Frequency Range. Tested at 1kHz.
Output Offset Voltage (max)
Gain of Signal (de out, rms in)
In Phase w .r. t. Reference
In Quadrature w.r. t. Reference
Input Bias Current
Input Impedaoce
Input Voltage Range
15
mV
-0.9 ±2%
±0.02(max)
60 (typ), 150 (max)
>1
+8to -8
nA
MO
V
INTEGRATOR
Open Loop Gain at 10kHz
Output Impedaoce at 10kHz (max)
Dead Zone Current
Input Offset Voltage
Input Bias Current
Output Voltage Range (min)
Input Impedaoce
Input Voltage Range
60 ±3
0.5
100
1 (typ), 5 (max)
60 (typ), 150 (max)
+8to -8
>1
+8to -8
dB
1.1
7.4 ± 10%
1 (typ), 5 (max)
120 (typ), 300 (max)
-0.55
+8to -8
±5
+3
MHz
kHzlfJ.A
mV
nA
nArC
V
%
%
-7
%IV
+2
%IV
VCO
Maximum Rate
VCORate
Input Offset Voltage
Input Bias Current
Input Bias Current Tempco
Input Voltage Range
Reversion Error
Linearity of Absolute Rate
SensitivityofVCO Rate in "Up
Direction" to - Vs
Sensitivity ofVCO Rate in "Down
Direction"to - Vs
0
nA/LSB
mV
nA
V
MO
V
See Section "Integrator"
NOTE
Specifications subject to change without notice.
ABSOLUTE MAXIMUM INPUTS (with respect to GND)
+Vs'
-Vs . . .
+VL
Reference
Sin
Cos . . .
Any Logic Input
Demodulator Input
Integrator Input
VCO Input . . . .
PIN CONFIGURATION
OV to +14V de
OV to -14V de
OV to +Vs
+14Vto -Vs
+14Vto -Vs
+14Vto -Vs
-O.4Vto +VLde
+14Vto -Vs
+14Vto -Vs
+14Vto -Vs
DEMODOIP
INTEGRATOR OIP
INTEGRATOR liP
V.C.O.IIP
-Vs
RC
DIR
CAUTION:
I. Correct polarity voltages must be maintained on the + VS
and - Vs pins.
Model
2S8ljD
ORDERING INFORMATION
Operating
Package
Temperature Frequency
Option*
Range
Range
D-28
Oto +70·C
400 to 20,OOOHz
*See Section 14 for package outline information.
5-80 SYNCHRO & RESOL VER CONVERTERS
DIGITALGND
INHIBIT
BYTE SELECT
BITS
ENABLE
BIT&
+V,
BIT7
BIT8LSB
2S81
OPERATION OF THE CONVERTER
When connected in a circuit such as is shown in Figure I the
2S81 operates as a tracking resolver-to-digital converter and
forms a type 2 closed loop system. This means that the digital
output will automatically follow the input for speeds up to the
maximum tracking rate, set by the choice of external components.
No convert command is necessary as the conversion is initiated
by each LSB increment of the input. Each LSB increment of
the converter initiates a BUSY pulse.
points are maintained in the correct place to drive the converter's
phase sensitive detector.
As the digital output of the converter passes through the major
carry, i.e., all "Is" to all "Os" or the converse, a RIPPLE CLOCK
(RC) logic output is initiated indicating that a revolution or a
pitch of the input has been completed.
Square waveforms can be used but the input levels should be
adjusted so that the average value is 1.9 volts rms. (For example
- a square wave should be 1.9V peak.)
The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in advance
of a RIPPLE CLOCK pulse and, as it is internally latched, only
changes with a change in direction.
Both the RIPPLE clock pulse and DIRECTION data
fected by the application of the INHIBIT.
a~e
unaf-
Position Output
The resolver shaft position is rePresented at the converter output
by a natural binary digital word.
The static angular accuracy quoted is the worst case error that
can occur over the full operating temperature range with the
following input conditions:
a) Signal input amplitudes within 5% of the nominal values.
b) Signal and reference frequency within the specified operating
range.
c) Phase shift between signal and reference less than 10 degrees.
d) Signal and reference waveform harmonic distortion less than
10 percent.
These test conditions are selected primarily to establish a repeatable acceptance test procedure which can be traced to national
standards. In practice, the converters can be used well outside
these operating conditions providing the following points are
observed.
Signal Amplitude (Sine and Cosine Inputs)
The amplitude of the signal inputs should be maintained within
5% of the nominal values if full performance is required from
the velocity signal.
The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a dramatic loss in accuracy due to internal overload.
Reducing level will result in a steady decline in accuracy. With
the signal levels at SO"A. of the correct value, the angular error
will increase to an amount equivalent to 1.3LSB. At this level
the repeatability will also degrade to 2LSB and the dynamic
response will also change, since the dynamic characteristics are
proportional to the signal level.
The 2S8l will not be damaged if the signal inputs are applied to
the converter without the power supplies and/or the
reference.
Reference Voltage Level
The amplitude of the reference signal applied to the converter's
input is noncritical; however, it is essential that the zero crossing
The 2S81 will not be damaged if the reference is supplied to the
converter without the power supplies and/or the signal inputs.
Harmonic Distortion
The amount of harmonic distortion allowable on the signal and
reference lines mainly depends on the type of transducer being
used.
Note: The figure specified of 10"/0 harmonic distortion is for
calibration convenience only.
Velocity Signal
The tracking converter technique generates an internal signal at
the output of the integrator (the INTEGRATOR OUTPUT
pin) that is proportional to the rate of change of the input angle.
This is a dc analog output referred to as the VELOCITY signal.
DC Error Signal
The signal at the output of the phase sensitive detector (DEMODULATOR OUTPUT) is the signal to be nulled by the
tracking loop and is therefore proportional to the error between
the input angle and the output digital angle. This is the DC
ERROR of the converter; and as the converter is a type 2 servo
loop, it will increase if the output fails to track the input for any
reason. It is an indication that the input has exceeded the maximum
tracking rate of the converter or, due to some internal malfunction,
the converter is unable to reach a null. By connecting two external
comparators this voltage can be used as a "built-in test".
CONNECTING THE CONVERTER
The power supply voltages connected to + V s and - V spins
should be :t 12V and must not be reversed. If one rail is connected
without the other, the converter will not operate and may "latch
up". In this case the removal of both rails is necessary in order
for the converter to function correctly again. The voltage applied
to VL can be +SVto +Vs.
It is suggested that decoupling capacitors are connected in parallel
between the power lines + V s , - Vs and ANALOG GROUND
adjacent to the converter. Suggested values are lOOnF (ceramic)
and IO",F (tantalum). Decoupling capacitors of lOOnF and IO",F
should also be connected between + VLand DIGITAL GROUND
adjacent to the converter.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and ANALOG GROUND as
shown in Figure 7 and described in section "CONNECTING
THE RESOLVER". The two signal ground Wires from the
resolver should be joined at the ANALOG GROUND pin of
the converter to minimize the coupling between the sine and
cosine signals. For this reason it is also recommended that the
resolver is connected using twisted pair cables with the sine,
cosine and reference signals twisted separately.
The external components required should be connected as shown
in Figure 1.
SYNCHRO & RESOLVER CONVERTERS 5-81
•
REFERENCE liP
OFFSET ADJUST
1MH
+12V~-12V
HF FILTER
4.7MH
BANDWIDTH
SELECTION
CS
SIN liP
ANALOG
GND
VELOCITY
SiGNAL
COS liP
RCI__~~~~~~~
VCO
DATA TRANSFER
LOGIC
+12V
VCOIIP
R7
-12V
ENABLE
8 DATA BITS
BYTE
SELECT
+SV
DIG.
GND
BUSY
DIR
TRACKING
RATE
SELECTION
C6;r,
INHIBIT
Figure 7. 2S87 Connection Diagram
COMPONENT SELECTION
The following instructions describe how to select the external
components to the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest "preferred
value" component should be used and a S percent tolerance will
not degrade the overall performance of the converter. Care
should be taken that the resistors and capacitors will function
over the required operating temperature range. The components
should be connected as shown in Figure I.
For more detailed information and explanation, see section "CffiCUlT FUNCTIONS AND DYNAMIC PERFORMANCE".
1. HF Filter (RI, R2, CI, C2)
The function of the HF filter is to reduce the amount of
noise present on the signal inputs to the 2S81 reaching the
Phase Sensitive Detector and affecting the outputs. Rl and
C2 may be omitted - in which case R2 = R3 and CI = C3,
calculated below - but their use is particularly recommended
if noise from a switch mode motor drive is present.
Values should be chosen so that
and
2. Gain Scaling Resistor (R4)
If RI, C2 are fitted then: R4 = 120kO
If RI, C2 are not fitted then: R4 = 390kO
3. AC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,
R3=IOOkO
C3> __I_105 x fREF
4. Maximum Tracking Rate (R6)
The VCO input resistor R6 sets the maximum tracking rate
of the converter and hence the velocity scaling as at the max
tracking rate the velocity output will be 8 volts.
Decide on your required maximum tracking rate, "T" in
revolutions per second. Note that "T" must not exceed 260
rps and 1/8 of the reference frequency.
Rl = R2 = SOkO (max)
R6 = 14.S x 103 kO
CI=C2=
This gives a scale factor of
21r
T
I
fREF
RI
fREF = Reference frequency
(Hz)
This filter gives an attenuation of 3 times at the input to the
phase sensitive detector.
5-82 SYNCHRO & RESOLVER CONVERTERS
I
rps/volt
2S81
5. Closed-Loop Bandwidth Selection (C4, C5, R5)
a. Choose the Closed-Loop 3dB Bandwidth (Bcu required
ensuring that
fREF > 2.5 X BCL
Typical values may be 100Hz for 400Hz reference frequency and 500 to 1000Hz for 5kHz reference frequency.
b.
Select C4 so that
C4 = 20Ax 10- 3
R6xBcl2
with R6 in k.o and BCL in Hz selected above.
c.
R5 is given by
R5 =
4
.0
2 x 1T X BCl xC5
6. VCO Phase Compensation
The following values of C6 and R7 should be fitted.
C6=470pF
BYTE SELECT Input:
The BYTE SELECT input selects the byte of position data to
be presented at the data output pins. A logic "HI" on the BYTE
SELECT input will present the 8 most significant data bits on
pins 8 to 15 when the ENABLE input is taken to a logic "LO".
A logic "LO" will present the 4 least significant data bits on
pins 8 to 11 and place a logic "LO" on pins 12 to 15 (with the
ENABLE input taken to a logic "LO").
The operation of the BYTE SELECT has no effect on the conversion process of the convener.
C5 is given by
C5=5xC4
d.
ENABLE Input:
The ENABLE input determines the state of the output data. A
logic "HI" maintains the output data pins in the high impedance
condition, and application of a logic "LO" presents the data in
the latches to the output pins. The operation of the ENABLE
has no effect on the conversion process.
R7=68.o.
7. Offset Adjust
Input bias current at the integrator input can cause an additional
positional offset at the output of the convener of 4 arc mins
typical, 10 arc mins maximum. If this can be tolerated then
the 4.7M.o resistor and the lM.o potentiometer can be omitted
from the circuit.
To transfer data the INHIBIT input should be used. The data
will be valid 600ns after the application of a logic "LO" to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the BYTE SELECT input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic "HI"
state to enable the output latches to be updated.
RIPPLE CLOCK (RC) and DIRECTION (DIR) Outputs: As
the output of the convener passes through the major carty, i.e.,
all "Is" to all "Os" or the converse, a positive going edge on the
RIPPLE CLOCK (RC) output is initiated indicating that a
revolution or a pitch of the input has been completed. The
pulse has a minimum width of 300ns and is reset by the stan of
the next data update cycle.
To adjust for zero offset, ensure the resolver is disconnected
and all the other external components are fitted. Connect
COS to the REFERENCE INPUT and SIN to the ANALOG
GROUND and with the power and reference applied, adjust
the potentiometer to give all "Os" on the digital output bits.
The DIRECTION (DIR) logic output indicates the direction of
the input rotation, and this data is valid in advance of the RIPPLE
CLOCK pulse and stays valid until the direction changes. This
is the stan of the next data update cycle - if the direction of
rotation of the inputs has changed - and will be at least 300ns
after the rising edge of the RIPPLE CLOCK (see Figure 2).
The potentiometer may be replaced by select on test resistors
if preferred.
The DIR and RC outputs are unaffected by the state of the
INHIBIT input.
DATA TRANSFER
BUSY Output:
The validity of the output data is indicated by the state of the
BUSX output. When the input to the convener is changing, the
signal appearing on the BUSY output is a series of pulses of
TTL levels. A BUSY pulse is initiated each time the input
moves by the analog equivalent of an LSB and the internal
counter is incremented or decremented.
INHIBIT Input:
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and therefore,. does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
NOTE: With the IN1DBIT input pin in the "Hi" TTL state,
data will be transferred automatically to the output latches.
BUSY
_____v_A_uD____~)(~___V_A_UD____
~DEPE~~~SO:I:PUT~ ~~~:y START QF NEXT DATA
RIPPLE
CLOCK (Re)
DO"
~
l---
~~------
300n5 min
------i
-----------~r~-------START Of NEXT DATA UPDATE
Figure 2. Timing Diagram
SYNCHRO & RESOL VER CONVERTERS 5-83
CIRCUIT FUNCTIONS AND DYNAMIC
PERFORMANCE
The 2S81 allows the user great flexibility in choosing the dynamic
characteristics of the resolver-to-digital conversion to ensure the
optimum system performance. The characteristics are set by the
exernal components shown in Figure I, and the section "COMPONENT SELECfION" explains how to select desired maximum
tracking rate and bandwidth values. The following paragraphs
explain in greater detail the circuit of the 2S81 and the variations
in. the dynamic performance available to the user.
Loop Compensation
The 2S81 (connected as shown in Figure I) behaves as a type 2
tracking servo loop where the VCO/counter combination and
the Integrator perform the 2 integration functions inherent in a
type 2 loop.
Additional compensation in the form of a pole/zero pair is required
to stabilize any type 2 loop to avoid the loop gain characteristic
crossing the 0dB axis with 180 degrees of additional phase lag,
as shown in Figure 4. This compensation is implemented by the
integrator components (R4, C4, R5, C5).
The attenuation and frequency response of a ftlter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. The suggested ftlter (RI, CI, R2, C2) is shown
in Figure I and gives an attenuation at the reference frequency
(fREF) of 3 times at the input to the phase sensitive demodulator.
Values of the components used in the ftlter must be chosen to
ensure that the phase shift at fREF is within the allowable signal
to reference phase shift of the converter.
Phase Sensitive Demodulator
The Phase Sensitive Demodulator is effectively ideal and develops
a mean dc output at the DEMODULATOR OUTPUT pin of
±2l"i
x (DEMODULATOR INPUT rms Voltage)
for sinusoidal signals in phase or antiphase with the reference
(for a square wave the DEMODULATOR OUTPUT voltage
will equal the DEMODULATOR INPUT). This provides a
signal at the DEMODULATOR OUTPUT which is a dc level
proportional to the positional error of the converter.
DC Error=40mVlbit
The overall response of such a system is that of a unity gain
second order low pass ftlter, with the angle of the resolver as
the input and the digital position data as the output.
When the tracking loop is closed, this error is nulled to zero
uuless the converter input angle is accelerating.
A block diagram of the 2S81 is given in Figure 3.
Integrator
The integrator components (R4, C4, R5, C5) are external to the
2S81 to allow the user to determine the optimum dynamic characteristics for any given application. The section "COMPONENT
SELECTION" explains how to select components for a chosen
bandwidth.
Ratio Multiplier
The Ratio Multiplier is the input section of the 2S81 and compares
the signal from the resolver inputs, 9, to the output digital
angle, <1>, held in the counter. Any difference between these two
angles results in an analog voltage at the AC ERROR OUTPUT.
This circuit function has historically been called a "Control
Transformer" as it was originally performed by a mechanical
device known by that name.
The AC ERROR signal is given by
AC ERROR OUTPUT=AI sin (9 - <1» sinoot.
where
00=211" fREF
fREF=reference frequency
AI, the gain of the ratio multiplier stage, is 14.5 times
So for 2V rms input signals
AC ERROR output in volts/(bit of error)
=2xsin
(!:) x Al
= 44.5mV/rms/bit
HF Filter
The AC ERROR OUTPUT may be fed to the PSD via a simple
ac coupling network (R2, CI) to remove any DC offset at this
point. Note, however, that the PSD of the 2S81 is a wideband
demodulator and is capable of aliasing HF noise down to within
the loop bandwidth. This is most likely to happen where the
resolver is situated in particularly noise environments, and the
user is advised to fit a simple HF ftlter (RI, C2) prior to the
phase sensitive demodulator.
5-84 SYNCHRO & RESOL VER CONVERTERS
Since the output from the integrator is fed to the VCO INPUT,
it is proportional to velocity (rate of change of output angle)
and can be scaled by selection of R6, the VCO input resistor.
This is explained in the section "VOLTAGE CONTROLLED
OSCILLATOR (YCO)" below.
To prevent the converter from 'flickering' (i.e., continually
toggling by ± I bit when the quantized digital angle, <1>, is not
an exact representation of the input angle, 9) feedback is interna1ly
applied from the VCO to the integrator input to ensure that the
VCO will only update the counter when the error is greater than
or equal to I bit. In order to ensure that this feedback "hysteresis"
is set to ILSB the input current to the integrator must be scaled
to be lOOnAIbit. So
R4 = 40mVlbit = 4OOkO (390kO is the nearest
lOOnAlbit
preferred value).
Any offset at the input of the integrator will affect the accuracy
of the conversion as it will be treated as an error signal and
offset the digital output. One LSB (5.3 arc mins) of extra error
will be added for each lOOnA of input bias current. The method
of adjusting out this offset is given in the section "COMPONENT
SELECTION" .
2S81
Voltage Controlled Oscillator (YCO)
The VCO is essentially a simple integrator feeding a pair of dc
level comparators. Whenever the integrator output reaches one
of the comparator threshold voltages, a fixed charge is injected
into the integrator input to balance the input current. At the
same time the counter is clocked either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the VCO.
During the reset period the input continues to be integrated
although the reset period is constant at 4OOns.
The VCO rate is fixed for a given input current by the VCO
scaling factor,
= 7.4kHzllIA
This is equivalent to a tracking rate of 7400/4096 = 1.807 rps
per IIA of VCO input current.
The input resistor R6 determines the scaling between the converter
velocity signal voltage at the INTEGRATOR OUTPUT pin and
the VCO input current. Thus to achieve a 5 volt output at 100
rps (6000 rpm) the VCO input current must be:
(100 x 4096)/(7400) = SS.411A
Thus R6would be set to: 51(55.4 x 10- 6) = 9OkO
The velocity offset voltage depends on the VCO input resistor,
R6, and the VCO bias current and is given by
Velocity Offset Voltage = R6 x (YCO bias current)
The temperature coefficient of this offset is given by
Velocity Offset Tempco = R6 x (VCO bias current
tempco)
where the VCO bias current tempco is typically -O.SSnAf'C.
The maximum recommended rate for the VCO is 1.IMHz which
sets the maximum possible tracking rate at
1.1 x
~
Transfer Function
By selecting components using the method outlined in the section
"Component Selection" the converter will have a critically damped
time response and maximum phase margin. The Closed-Loop
Transfer Function is given by:
80UT =
14 (l +8N)
(8N+2.4) (SN2 +3.4 sN+S.8)
81N
where,
~
SN,
the normalized frequency variable is
2
=:rr
s
fBw
and fBw is the closed-loop 3dB bandwidth (selected by the choice
of external components).
The acceleration constant, KA is given approximately by
KA = 6 X (fBw)2
sec-2
The normalized gain and phase diagrams are given in Figures 4
and S.
The small signal step response is shown in Figure 6. The time
from the step to the first peak is t 1 and the t2 is the time from
the step until the converter has settled to lLSB. The times
t1 and t2 are given approximately by
t\
=~
f Bw
5
t2 = f Bw
The large signal step response (for steps greater than 10 degrees)
applies when the error voltage will exceed the linear range of
the converter. Typically the converter will take 3 times longer
to reach the first peak for a 179" step.
In response to a velocity step the velocity output will exhibit the
same time response characteristics as outlined above for the
position output.
12
revs/second
--
Since the maximum voltage swing available at the integrator
output is :!: 8 volts, this implies that the minimum value for R6
is S4kO. As
1.1 106
Max Current = 7.4x 103 = 149j.t.A
Min Value
~
-8
",
f-"""
'\
\
-9
= 149:10
6
= 54kO
-'2
O.02fsw O.04f8W
O.
"aw
O.2faw O·4f8W
FREQUENCY
few
\
2faw
Figure 4. 2581 Gain Plot
'80
.35
sin tI sin wt
sin8sinwt
.............
"-
-10
Figure 3. 2S81 Functional Diagram
-'35
-'80
O.02faw O.D4faw
O.1faw
O.2faw O.4'aw
.......
faw
2faw
Figure 5. 2581 Phase Plot
SYNCHRO & RESOL VER CONVERTERS 5-85
•
OUTPUT
POSmON
and a reference frequency of 5kHz, the converter will exhibit an
additional error of:
"=---1
2~~ 20
= 0.088.
This effect can be eliminated by putting a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver (see section ''CONNECTING THE RESOLVER").
NOTE: Capacitive and inductive crosstalk in the signal and
reference leads and wiring can cause similar problems.
nME
Figure 6. 2S81 Small Step Response
APPUCATIONS
Causes of Additional Error
Integrator Offset
Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator as it will
be treated as an error signal. This error will be a maximum of
10 arc minutes over the operating temperature range, and if it
can be tolerated in the performance of the converter, then the
4.7MO resistor and the IMO potentiometer shown in Figure 1
can be omitted. (An offset of 40mV at the input to the integrator will cause an additional error of 1LSB in the accuracy of
the converter.)
A description of how to adjust for zero offset is given in the
section "COMPONENT SELECTION" and the circuit required
is shown in Figure 1.
Differential Phase Shift
Phase shift between the sine and the cosine signals from the
resolver is known as differential phase shift and will cause static
error. Some differential phase shift will be present on all resolvers
as a result of coupling. A small resolver residual voltage (quadrature
voltage) indicates a small differential phase shift. Additional
phase shift can be introduced if the sine channel wires and the
cosine channel wires are treated differently. For instance, different
cable lengths or different loads could cause differential phase
shift.
The additional error caused by differential phase shift on the
input signals approximates to
Error = 0.53 a.b arc minutes
where a = differential phase shift in degrees
and b = signal to reference phase shift in degrees.
This error can be minimized by choosing a resolver with a small
residual voltage, ensuring that the sine and cosine signals are
handled identically and removing the reference phase shift (see
section "CONNECTING THE RESOLVER"). By taking these
precautions, the extra error can be made insignificant.
Resol'lJer Phase Shift
Under static operating conditions phase shift between the reference
and the signal lines alone will not theoretically effect the converter's
static accuracy.
However, when rotating, most resolvers, particularly those of
the brushless type, exhibit a phase shift between the signal and
the reference. This phase shift will give rise under dynamic
conditions to an additional error defmed by:
Shaft Speed (RPS) x Phase Shift (DEGS)
Reference Frequency
For example, for a phase shift of 20", a shaft rotation of 22rps
5-86 SYNCHRO & RESOL VER CONVERTERS
Using the Velocity Signal
The signal at the INTEGRATOR OUTPUT pin relative to the
ANALOG GROUND pin is an analog voltage proportional to
the rate of change of the input angle. This signal can be used to
stabilize servo loops or in place of a velocity transducer. Although
the conversion loop of the 2S81 includes a digital section there
is an additional totally analog feedback loop around the velocity
signal. This ensures that there is no digital effects on the output
signal and that the loop is closed even when the input signals
are such that the digital output does not change.
A better quality velocity signal will be achieved if the following
points are considered.
1. Protection.
The velocity signal should be buffered before use.
2. Reversion Error.
If necessary, the reversion error can be reduced by a simple
trimming circuit. Reversion error, or side-ta-side nonlinearity,
is a result of differences in the up and down rates of the
VCO. Because the sensitivity of the VCO rate to - Vs depends
on the direction of rotation, the reversion error can be reduced
by varying the magnitude of - Vs. By trimming a reversion
error of less than 1% is achievable.
3. Ripple and Noise.
Noise on the input signals to the CODverter is the major
cause of noise on the velocity signal. This can be reduced
to a minimum if the following precautions are taken:
The resolver is connected to the converter using screened
separate twisted pair cables for the sine, cosine and reference
signals.
Care is taken to reduce the external noise wherever possible.
An HF filter is fitted before the Phase Sensitive Demodulator
(as described in the section HF FILTER).
A resolver is chosen that has a low residual voltage, i.e., a
small signal in quadrature with the reference.
Components are selected to operate the 2S81 with the lowest
acceptable bandwidth.
Feedthrough of the reference frequency should be removed
by a filter on the vc:locity signal.
The signal voltages are 2V rms to prevent a ripple at the
LSB switching rate. This is because the lLSB of analog
feedback that prevents the output from flickering will be
incorrectly scaled (see section "INTEGRATOR").
If the above precautions are taken, a very good noise and
ripple performance is obtainable making the 2881 velocity
signal usable in very noisy environments, for instance in
motor drive applications with PWM switching noise.
The positional error curve of the converter and the resolver
will result in an apparent acceleration when the resolver is
rotating at a constant velocity. The main result of this will be
a ripple on the velocity signal twice per revolution.
2S81
For signal and reference voltages greater than 2V rms a simple
voltage divider circuit of resistors can be used to generate the
correct signal level at the converter. Care should be taken to
ensure that the ratios of the resistors between the sine signal
line and ground and the cosine signal line and ground are the
same. Any difference will result in an additional position error.
Connecting the Resolver
The recommended connection circuit is shown in Figure 7.
TWISTED PAIR
SCREENED
CABLE
S2LS4
::
----r-----;z-- -----1
1
REF liP
2581
xyr====
5
Typical Circuit ConfIgUration
Figure 8 shows a typical circuit configuration for the 2S81.
Values of the external components have been chosen for a reference
frequency of 5kHz and to give a maximum tracking rate of 260
rps and a bandwidth of 520Hz. The resistors are O.25W (except
for the 4.7MO which is O.5W) 5 percent tolerance preferred
values. The capacitors are lOOV ceramic 5 percent tolerance
components.
ANALOGGNO
~ ::: ~ 7=====_~-~7L::...jL.___
...J
RESOLVER
Figure 7. Connecting the 2S81 to a Resolver
An offset adjustment potentiometer is included at the integrator
input to remove the offset error. Obviously this can be left out
of the circuit if the extra inaccuracy can be tolerated.
In cases where the reference phase relative to the input signals
from the resolver requires adjustment this can be easily achieved
by varying the value of the resistor R2 of the HF filter (see
Figure I).
360
315
w
w 270
II:
t:I 225
w
Assuming that RI = R2 = R and CI = C2 = C
and Reference Frequency = 21T
iC
I
c
I 180
w
135
t:I
2
90
-0:
..I
By altering the value of R2 the phase of the reference relative to
the input signals will change in an approximately linear manner
for phase shifts of up to 10 degrees.
45
Increasing R2 by 10% introduces a phase lag of 2 degrees.
Decreasing R2 by 10"10 introduces a phase lead of 2 degrees.
0
II
1
./ 4
8
12
16
TlME- ms
20
24
Figure 9. Large Step Response Curves for Typical Circuit
Shown in Figure 8
1Mn
4.1MO
REFE~~~~~-II--+'-100nI-F'''''_+_+--I
r1..--+....--....--+t--Ir--~~~OCITV
100nF
[241f-----------.....--12V
+ 12V-.....--+-+-------!
COS LOW
----I
SIN LOW - - - - - - '
Figure 8. Typical Circuit for the 2S81
SYNCHRO & RESOL VER CONVERTERS 5-87
II
5-88 SYNCHRO & RESOLVER CONVERTERS
Variable Resolution, Monolithic
Resolver-to-Digital Converter
2S82 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
Monolithic (BiMOS II) Tracking RID Converter
44-Pin J Leaded Chip Carrier (LCC)
10-, 12-, 14- and 16-Bit Resolution Set by User
Ratiometric Conversion
Low Power Consumption - 300mW typ
Dynamic Performance Set by User
High max Tracking Rate 1040 rps (10 Bits)
Velocity Output
veo Output (Inter LSB Output)
Data Complement Facility
Military Temperature Range Version
2S82 FUNCTIONAL BLOCK DIAGRAM
eos
APPLICATIONS
Brushless Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
GENERAL DESCRIPTION
The 2S82 is a monolithic 10-, 12-, 14- or 16-bit tracking resolverto-digital converter contained in a 44-pin J leaded chip carrier
package. Two extra functions are provided in the new surface
mount package - COMPLEMENT and VCO OUTPUT. All
other functions are identical to the 2S80.
The converter allows users to select their own resolution and
dynamic performance with external components. This allows the
users great flexibility in defining the converter that best suits
their system requirements. The converter allows users to select
the resolution to be 10, 12, 14 or 16 bits and to track resolver
signals rotating at up to 1040 revs per second (62,400 rpm)
when set to IO-bit resolution.
The 2S82 converts resolver format input signals into a parallel
natural binary digital word using a ratiometric tracking conversion
method. This ensures high noise immunity and tolerance of lead
length when the converter is remote from the resolver.
The 10-, 12-, 14- or 16-bit output word is tristate available in
two bytes on the 16 output data lines. BYTE SELECT, ENABLE
and INHIBIT pins ensure easy data transfer to 8- and 16-bit
data buses, and outputs are provided to allow for cycle or pitch
counting in external counters.
An analog signal proportional to velocity is also available.
veo
lIP
+5V
V
16 DATA BITS
PRODUCT HIGHLIGHTS
Monolithic. A one-chip surface mount package solution reduces
the package size required and increases reliability.
Resolution Set by User. Two control pins are used to select
the resolution of the 2S82 to be 10, 12, 14 or 16 bits allowing
the user to use the 2S82 with optimum resolution for each
application.
Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion delay
and is insensitive to absolute signal levels. It also provides good
noise immunity and a tolerance to harmonic distortion on the
reference and input signals.
Dynamic Performance Set by the User. By selecting external
resistor and capacitor values, the user can determine bandwidth,
maximum tracking rate and velocity scaling of the converter to
match the system requirements. The external components required
are all low cost, preferred value resistors and capacitors, and the
component values are easy to select using the simple instructions
given.
Velocity Output. An analog signal proportional to velocity is
available and is linear to typically one percent. This can be used
in place of a velocity transducer in many applications to provide
loop stabilization and velocity feedback data.
Low Power Consumption. Typically only 300mW.
ORDERING INFORMATION
Reference frequency operating range for the 2S82 is 50Hz to
20,OOOHz.
Model
Accuracy
(Arcmins)
Operating
Temperature
Range
Package
Options
2S82HP
22 + ILSB
Oto + 70°C
PlasticLCC
2S82JP
2S82KP
8 + ILSB
4 + ILSB
Oto + 70°C
Oto + 70°C
PlasticLCC
PlasticLCC
2S82LP
2 + ILSB
Oto + 70°C
PlasticLCC
SYNCHRO & RESOL VER CONVERTERS 5-89
II
SPECIFICATIONS (typical at 25"C unless ofJIelWise specified)
2582
Model
Unils
NOles
TYPICAL CONVERTER PERFORMANCE (Connected as shown in Figure I)
Resolution
IO,I2,I40rl6
bits
Accuracy HP Option
JPOption
KPOption
LPOption
Tracking Rate Range
IO..Bit Resolution
12..Bit Resolution
I4-Bit Resolution
16..Bil Resolution
Operating Frequency Range
Repeatability of PoSition Output
Bandwidth
Velocity Signal
:t22 + ILSB
:t8 +ILSB
:t4 + ILSB
:t2 +ILSB
arcmins
arentins
aremins
arcmins
Oto 1040
tpS
tps
rps
rps
Hz
LSB
oto 260
01065
Oto 16.25
50 to 20,000
I
User Selectable
Accuracy will be affected by the offset at the
INTEGRATOR lIP.
User Selected, max rate limited to 1I160fthe
reference frequency.
See "Using the Velocity Signal."
Linearity
Zero Offset
:tl
:tl
+6
% of output
%
mV
Zero Offset Tempco
-22
,.vrc
Over Full Range
Reversion Error
See VCO spec.
With power supplies adjusted for best performance.
For max tracking rate range. Depends on VCO liP
resistor (R6).
For max tracking rate range. Depends on veo lIP
resistor (R6).
Gain Scaling Accuracy
Output Voltage
Noise and Ripple
at LSB Rate
Dynamic Ripple (Peak)
:t1O
:t8
%FSD
Vdc
2
1.5
% of mean output
mV
See section "Using the Velocity Output."
ANALOG INPUTS
Protection
All analog inputs are diode
protected against overvoltage at ± 8V.
REFERENCE INPUT
Frequency
Voltage Level Nominal
Max
50-20,000
2
II
6O(typ),150(max)
>1
Hz
Vrms
V peak
nA
MO
Frequency
50-20,000
Hz
Allowable Phase Shift
(Signal to Reference)
Voltage Level
10
2, ± 10%
Degrees
Vrms
nA
MO
V
Input Bias Current
Input Impedance
SIGNAL INPUTS (SIN, COS)
Input Bias Current
Input Impedance
Maximum Voltage Nominal
DlGITALINPUTS
60(typ),150(max)
>1
:t8
TTL Compatible
Except DATA LOAD and SHORT CYCLE INPUTS.
INHIBIT
Sense
Logic LO to inhibit
Time to Data Stable (After
Negative Going Edge of
INHIBIT)
600
See section "INHIBIT Input."
ns
DATA LOAD
Internally pulled up to + 12V.
Sense
Unconnected for normal operation.
Logic LO allows data to be loaded
into the counters from the data lines.
Connect when multiplexing the 2S82 or when using
as a control transformer.
Ensure data lines are in high impedance state
when loading data.
SHORT CYCLE INPUTS (SCI, SC2)
Internally pulled up to + V s.
For IO.. Bit Resolution
For I2~Bj[ Resolution
For 14-Bit Resolution
For 16-Bjt Resolution
BYTE SELECT
Sense Logic HI
LogicLO
Time (0 Data Available
SCI
0
0
I
I
SC2
0
I
0
I
Used to select the resolution of the converter.
o= Digital Ground. Drive low with open collector TTL.
I ~ Open Circuit (internally pulled up through I ookO).
8 MSBsselected on data lines I t08.
The size of the LS Byte will be between 2 and 8 bits depending
LS Byte selected on data lines 9 to 16.
on the resolution selected.
LS Byte selected on data lines I to 8
and9to 16.
150 (typ),450 (max)
ns
(After Change in State)
5-90 SYNCHRO & RESOLVER CONVERTERS
2S82
j\lodel
COMPLEMENT
ENABLE
Sense
Enable and Disable Times
ANALOG OUTPUTS
Protection
Output Voltage Range, typ
max
min
DIGITAL OUTPUTS
Format
POSITION OUTPUTS
Format
Resolution
Number of Data Lines
Max Load
Monotonicity
HP, JP, KP Options
LPOption
DIRECTION
Sense
Timing
Max Load
RIPPLE CLOCK
Sense
Timing
Width
Reset
Max Load
BUSY
Sense
Timing
typ
min
max
Max Load
Width
POWER SUPPLIES
Voltage Levels
+Vs
-Vs
+ VI.
Curren[
+ Vs, - Vsat 12V
+ Vs , - Vsat 13.2V
+VL,
2S82
Units
Notes
Internally pulled up to + 12V.
Unconnected for normal operation.
Losic LO to activate.
Logic LO to enable position outputs.
Logic HI position outputs in high
impedance state.
200 (typ), 550 (max)
ns
Short-circuit output current
limited to ± SmA, ± 30%.
+9to -9
V
+ 10.5 to -10.5
V
+8to-8
V
V L = +5V
V L = +12V
TTL Compatible
CMOS Compatible
With I rnA load.
Voltage on V L sets the voltage level of the digital outputs.
Three-state natural binary
10,12, 140r 16
bits
16
3
LSTTL
II
Guaranteed to 14 bits
Guaranteed to 16 bits
Logic HI when counting up.
Logic LO when counting down.
Only changes, if required, at start of output
position data cycle.
3
LSTTL
Positive going edge when counting up
from all U 1s" and when counting down
from all "Os" as data changes.
Edge occurs at least 300ns before change
in DIR can occur.
300 (min)
ns
By start of next data update.
3
LSTTL
Logic HI when converter position output
changing.
Positive going edge SOns before change in
position output.
300
ns
200
ns
600
ns
LSTTL
3
See Section "BUSY Output."
The 2S82 may latch up if + Vs is applied without - Vs.
+12 ± 10%
-12 ± 10%
+5to+14
V
V
V
12 (typ), 23 (max)
19 (typ), 30 (max)
0.5 (typ), 1.5 (max)
rnA
mA
mA
Over operating temperature range.
GENERAL
Operating Temperature Range
HP, JP, KP, LP Options
Storage Temperature Range
(All Options)
Weight
Oto + 70
-25to +85
°C
°C
0.2(5)
oz(grams)
VCOOUTPUT
±3(±10%)
V/LSB
The VCO output swings between ± 3V depending on the
resolver direction.
SYNCHRO & RESOLVER CONVERTERS 5-91
CONVERTER CHARACTERISTICS
Model
Units
2582
RATIO MULTIPLIER
Function
AC ERROR Output Scaling
Io-Bit Resolution
12-Bit Resolution
14-Bit Resolution
If>.Bit Resolution
Accuracy
HPOption
JPQption
KPOption
LPOption
Differential Nonlinearity
HP, JP, KP Options
LPOption
AC ERROR output represents the
difference between the angle at the SIN
and COS inputs compared to the position
output angle.
177.6
44.4
Il.l
2.77S
mVlbit
mVlbit
mVlbit
mVlbit
±22
±8
±4
±2
arcmins
arcmins
arcmins
arcmins
1
Input Voltage Range
+8to -8
nA
MO
V
INTEGRATOR
Open Loop Gain at 10kHz
Dead Zone Current
Input Offset Voltage
Input Bias Current
Output Voltage Range (min)
Input Impedance
Input Voltage Range
dB
nAlLSB
mV
nA
V
MO
V
VCO
Maximum Rate
VCORate
VCORateTempco
Input Offset Voltage
Input Bias Current
Input Bias Current Tempco
Input Voltage Range
Linearity of Absolute Rate
Over Full Range
Over 0 to SO% of Max Range
Reversion Error
Sensitivity of Reversion Error
to Symmetry of Power Supplies
Spedfications subject
(0
Notes
I
60 ±3
100
I (typ), S (max)
60 (typ), ISO (max)
+8to -8
>1
+8to -8
1.1
7.4 ±IO%
-O.OS
I (typ), 5 (max)
120 (typ), 300 (max)
-O.SS
-8to +8
± I (typ), ± 3 (max)
+ I (max)
<3 (max)
8
Guaranteed monotonic to 14 bits when connected in tracking mode.
Guaranteed monotonic to 16 bits when connected in tracking mode.
Specified over operating frequency range. Tested at 1kHz.
mV
MHz
kHzlJLA
See section "Integrator."
With ± 12V supplies.
%rC
mV
nA
nAI"C
V
%
%
%
%IV of Asymmetry
Symmetrical power supplies.
See section "Using the Velocity Output. n
change without notice.
PIN CONFIGURATION
~ i ~
ABSOLUTE MAXIMUM INPUTS (with respect to GND)
+VSl
-VS· ..
+VL
Reference
Sin
Cos
Any Logical Input
Demodulator Input
Integrator Input
veo Input
a • 8~
OV to + 14V de
OV to -14V de
OV to +VS
+14Vto -Vs
+14V to -Vs
+14V to -Vs
-O.4V to + VL de
+14V to -Vs
+ 14V to -Vs
+14V to -Vs
5-92 SYNCHRO & RESOL VER CONVERTERS
~ ~
i
•
2S82
TOPVIEW
INotloSclle'
arT.
NOTE
lCAUTION - Correct polarity voltages must be maintained on
the + Vs and - Vs pins.
a
I ; ~ aa~ a
11
!
~ ! ~ ~
2S82
OPERATION OF THE CONVERTER
When connected in a circuit such as is shown in Figure I, the
2S82 operates as a tracking resolver-to-digital converter and
forms a type 2 closed loop system. This means that the output
will automatically follow the input for speeds up to the selected
maximum tracking rate. No convert command is necessary as
the conversion is initiated by each LSB increment of the input.
Each LSB increment of the converter initiates a BUSY pulse.
Because the conversion depends on the ratio of the input signals,
the 2S82 is remarkably tolerant of input amplitude and frequency
(there is no need of an accurate, stable oscillator to produce the
reference signal). The inclusion of a phase sensitive detector in
the conversion loop ensures a high immunity to signals that are
not coherent or are in quadrature with the reference signal.
Two major areas of the 2S82 specification can be selected by the
user to optimize the total system performance. The resolution of
the digital output is set by the state of the inputs SC 1 and SC2
to be 10, 12, 14 or 16 bits, and the dynamic characteristics of
bandwidth and tracking rate are selected by the choice of external
components.
Position Output
The resolver shaft position is represented at the converter output
by a natural binary parallel digital word.
As the digital output of the converter passes through the major
carries, i.e., all "is" to all "Os" or the converse, a RIPPLE
CLOCK (RC) logic output is initiated indicating that a revolution
or a pitch of the input has been completed.
The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in advance
of a RIPPLE CLOCK pulse and, as it is internally latched, only
changes with a change in direction.
Both the RIPPLE CLOCK pulse and the DIRECTION data
are unaffected by the application of the INHIBIT.
The static accuracy quoted is the worst case error that can occur
over the fnll operating temperature excluding the effect of offset
signals at the INTEGRATOR INPUT (which can be trimmed
out) and with the following conditions: input signal amplitudes
are within 5% of the nominal values; signal and reference frequency
is within the specified operating range; phase shift between
signal and reference is less than 10 degrees; signal and reference
waveform harmonic distortion is less than 10%.
These test conditions are selected primarily to establish a repeatable acceptance test procedure which can be traced to national
standards. In practice, the 2S82 can be used well outside
these operating conditions providing the following points are
observed.
Signal Amplitude (Sine and Cosine Inputs)
The amplitude of the signal inputs should be maintained within
5% of the nominal values if full performance is required from
the velocity signal.
The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a dramatic loss in accuracy due to internal overload.
Reducing level will result in a steady decline in accuracy. With
the signal levels at SOOA> of the correct value, the angular error
will increase to an amount equivalent to 1.3LSB. At this level
the repeatability will also degrade to 2LSB and the dynamic
response will also change, since the dynamic characteristics are
proportional to the signal level.
The 2S82 will not be damaged if the signal inputs are applied to
the converter without the power supplies and/or the reference.
Reference Voltage Level
The amplitUde of the reference signal applied to the converter's
input is not critical, but care should be taken to ensure it is
kept below the absolute maximum voltage.
The 2S82 will not be damaged if the reference is supplied to the
converter without the power supplies and/or the signal inputs.
Harmonic Distortion
The amount of harmonic distortion allowable on the signal and
reference lines mainly depends on the type of transducer being
used.
Square waveforms can be used but the input levels should be
adjusted so that the average value is 1.9V rms. (For example, a
square wave should be 1.9V peak.)
Note: The figure specified of 10% harmonic distortion is for
calibration convenience only.
Velocity Signal
The tracking converter technique generates an internal signal at
the output of the integrator (the INTEGRATOR OUTPUT
pin) that is proportional to the rate of change of the input angle.
This is a dc analog output referred to as the VELOCITY signal.
DC Error Signal
The signal at the output of the phase sensitive detector
(DEMODULATOR OUTPUT) is the signal to be nulled by the
tracking loop and is therefore proportional to the error between
the input angle and the output digital angle. This is the DC
ERROR of the converter; and as the converter is a type 2 servo
loop, it will increase if the output fails to track the input for any
reason. It is an indication that the input has exceeded the maximum
tracking rate of the converter or, due to some internal malfunction,
the converter is unable to reach a null. By connecting two external
comparators, this voltage can be used as a "built-in test."
CONNECTING THE CONVERTER
The power supply voltages connected to + Vsand - Vspins
should be ± 12V and must not be reversed. If one rail is connected
without the other, the converter will not operate and may "latch
up." In this case, the removal of both rails is necessary in order
for the converter to function correctly again. The voltage applied
to VLcan be +SVto +Vs.
It is suggested that decoupling capacitors are connected in parallel
between the power lines + Vs, - Vs and ANALOG GROUND
adjacent to the converter. Suggested values of 100nF (ceramic)
and IO",F (tantalum). Decoupling capacitors of 100nF and IO",F
should also be connected between + VL and DIGITAL GROUND
adjacent to the converter.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
shown in Figure 7 and described in section "CONNECTING
THE RESOLVER". The two signal ground wires from the
SYNCHRO & RESOLVER CONVERTERS 5-93
•
resolver should be joined at the SIGNAL GROUND pin of the
converter to minimize the coupling between the sine and cosine
signals. For this reason it is also recommended that the resolver
is connected using twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GROUND and ANALOG GROUND are connected
internally. ANALOG GROUND and DIGITAL GROUND
must be connected externally.
The external components required should be connected as shown
in Figure 1.
REFERENCE
liP
OFFSET ADJUST
R9
HF FILTER
+12V~-12V
R8
SIN
PHASE
SENSITIVE
DETECTOR
SIG GND
VELOCITY
SIGNAL
COS
GND
-f_____- '
RIPPLE.L_~--~L.L..Iu..._...L..I...u...u..u...u.._---"J.-_ _ _ _
ClK
+12V
VCO + DATA
TRANSFER lOGIC
-12V
VCO
liP
R7
COMPLEMENT
;r,C6
DIG BUSY VCO DIRN INHIBIT
GND
OIP
16 DATA BITS
Figure 1. 2S82 Connection Diagram
SELECTING THE RESOLUTION
The resolution of the 2S82 can be selected to be 10, 12, 14 or
16 bits by use of the short cycling inputs SCI and SC2. The
required resolution can be selected as shown in the specification
section.
noise present on the signal inputs to the 2S82, reaching the
Phase Sensitive Detector and affecting the outputs. RI and
C2 may be omitted - in which case R2 = R3 and CI = C3,
calculated below - but their use is particularly recommended
if noise from a switch mode motor drive is present.
The choice of resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO respectively
(see section "COMPONENT SELECTION"). If the resolution
is changed, then new values of R4 and R6 must be switched
into the circuit.
Values should be chosen so that
Note: When changing resolution under dynamic conditions, a
period of uncertainty will exist before position and velocity data
is valid.
and fREF = reference frequency.
COMPONENT SELECTION
The following instructions describe how to select the external
components to the converter in order to achieve the req\lired
bandwidth and tracking rate. In all cases the nearest "preferred
value" component should be used and a 5% tolerance will not
degrade the overall performance of the converter. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. The components should
be connected as shown in Figure I.
For more detailed information and explanation, see
section "CIRCUIT FUNCTIONS AND DYNAMIC
PERFORMANCE. "
1. HF Filter (RI, R2, CI, C2)
The function of the HF filter is to reduce the amount of
5-94 SYNCHRO & RESOLVER CONVERTERS
RI = R2..;; 56kn
CI
= C2 = ---=-2'IT Rl fREF
(Hz)
This filter gives an attenuation of 3 times at the input to the
phase sensitive detector.
2. Gain Scaling Resistor (R4)
If RI, C2 are fitted then:
Ene
I
R4 = 100 x 10 9 X 3' n
If Rl, C2 are not fitted then:
Ene
R4 = 100 x 10- 9
n
where Ene = 160 x 10 - 3 for 10 bits resolution
40 x 10- 3 for 12 bits
lOx 10- 3 for 14 bits
2.5 x 10- 3 for 16 bits
Scaling at the DC ERROR in volts
2S82
3. AC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,
R3 = lOOk{}
C3>WS
PIN FUNCTIONS
1
x £REF
4. Maximum Tracking Rate (R6)
The VCO input resistor R6 sets the maximum tracking rate
of the converter and hence the velocity scaling as at the max
tracking rate the velocity output will be 8V.
Decide on your required maximum tracking rate, "T," in
revolutions per second. Note that "T" must not exceed the
specified maximum tracking rate or 1116 of the reference
frequency.
R6 = 5.92 x 107 k{}
Txp
where p = bit per rev
1,024 for 10
= 4,096 for 12
= 16,384 for 14
= 65,536 for 16
bits resolution
bits
bits
bits
5. Closed Loop Bandwidth Selection (C4, C5, R5)
a. Choose the Closed Loop 3dB Bandwidth (faw) required
ensuring that
fREF > 2.5
The potentiometer may be replaced by select on test resistors
if preferred.
X
REFERENCE liP
DEMODI/P
AC ERROROIP
COS
ANALOG GROUND
SIGNAL GROUND
SIN
+Vs
BIT 1- BIT 16
VL
ENABLE
BYTE SELECT
INHIBIT
faw
Typical values may be 100Hz for 400Hz reference frequency
and 500 to 1000Hz for 5kHz reference frequency.
b. Select C4 so that
DIGITAL GROUND
SCl,SC2
DATA LOAD
C4 _ 20.2 X 10- 3
- R6 X faw 2
BUSY
with R6 in kn and faw in Hz selected above.
c. C5 is given by
DIRECTION
C5=5xC4
d. R5 is given by
R5 =
RIPPLE CLOCK
4
2 x 1T X faw x C5
n
6. VCO Phase Compensation
The following values of C6 and R7 should be fitted.
C6 = 470pF
R7 = 68n
7. Offset Adjust
Offset and bias current at the integrator input can cause an
additional positional offset at the output of the converter of 1
arc min typical, 5.3 arc mins maximum. If this can be tolerated,
then R8 and R9 can be omitted from the circuit.
If fitted, the following values of R8 and R9 should be used:
R8 = 4.7Mn, R9 = IMn potentiometer.
To adjust for zero offset, ensure the resolver is disconnected
and all the other external components are fitted. Connect the
COS pin to the REFERENCE INPUT and the SIN pin to
the SIGNAL GROUND and with the power and reference
applied, adjust the potentiometer to give all "Os" on the
digital output bits.
-Vs
VCO lIP
INTEGRATOR liP
INTEGRATOR OIP
DEMODO/P
COMPLEMENT
VCOO/P
Input pin for the reference signal.
Demodulator input pin.
Output of ratio multiplier.
Input pin for cosine signal from
resolver.
Power ground.
Ground pin for signals from resolver.
Input pin for sine signal from
resolver.
Main positive power supply.
Parallel output data bits.
Logic power supply.
Logic "HI" sets the output data bits
to a high impedance state, a logic
"LO" presents the data in the latches
to the output pins.
Selects the data output bits presented
on data bits 1 to 8. Logic "HI" will
present the 8 most significant bits; a
logic "LO" will present the least significant byte.
Logic "LO" inhibits the data transfer
from the counter to the output
latches.
Ground pin for digital circuitry.
Logic inputs used for selecting the
resolution of the converter.
Logic "LO" allows data to be loaded
into the counters.
Converter BUSY. A logic "HI" indicates that the output latches are being
updated and data should not be
transferred.
Logic output indicating the direction
of rotation of the input signals.
A negative going pulse whenever the
output of the converter changes from
all "Is" top all "Os" or the converse.
Main negative power supply.
Input pin to VCO.
Input pin of integrator.
Output pin of integrator.
Output pin of demodulator.
Logic "LO" to activate
Output pin of VCO.
DATA TRANSFER
Data transfer can be accomplished using either the INHIBIT
input or the trailing edge of the BUSY pulse output.
INHIBIT Input:
The INHIBIT logic input only inhibits the data transfer from
the internal up-down counter to the output latches and, therefore,
does not interrupt the operation of the tracking loop. Releasing
the INHIBIT automatically generates a BUSY pulse to refresh
the output data.
SYNCHRO & RESOL VER CONVERTERS 5-95
II
The output data is valid 3S0ns after the application of a logic
"Lo" to the INHIBIT but the INHIBIT input must remain
"Lo" for at least 6OOns; otherwise the BUSY pulse generated by
the logic "Lo" to "Hi" transition of the INHIBIT input may
overlap the BUSY pulse that may have occurred at the time the
INHIBIT is applied. The time required to assert the INHIBIT
is lOOns.
BUSY Output:
The validity of the outpUt data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL levels. A BUSY pulse is initiated each time the input
moves by an analog equivalent of an LSB and the internal counter
is incremented or decremented or the INHIBIT input is
released.
Typically the width of the BUSY pulse is 3SOos during the
position data output updates. The trailing edge of the BUSY
pulse indicates that the position data output has been updated
and is ready for transfer. The maximum load on the BUSY
output using the trailing edge of the BUSY pulse is 3 LSTTL
loads.
I:::::e -Ir---l
=:: ,...
1
...___
lUX DEPENDS ON
I-
BUSY
N~~'
DATA
:1'=r-I1-
___V_AL_'D____~)(~====~=LI=D===
NOTE 1
THE USE Of THE LEADING EDGE OF THE BUSY TO PREDICT DATA UPDATES IS ADVERSELY
AFFECTED BY THE CAPAcmVE LOADING ON THE BUSY PULSE. TO ENSURE THAT THE LEADING
EDGE OF THE BUSY PULSE OVERLAPS DATA TRANSITIONS. THE MAXIMUM lOAD ON BUSY
OUTPUT SHOULD BE 1&pF AND IT SHOULD BE PULLED UP TO -5 VOLT SUPPLY VIA A 5kn. THIS
WILL RESTRICT THE MAXIMUM LOAD ON THE BUSY OUTPUT TO 1 LSlTL LOAD.
Figure 2. Timing Diagram
ENABLE Input:
The ENABLE input determines the state of the output data. A
logic "Hi" maintains the output data pins in the high impedance
condition, and application of a logic "Lo" presents the data in
the latches to the output pins. The operation of the ENABLE
has no effect on the conversion process.
BYTE SELECT Input:
The BYTE SELECT input selects the byte of position data to
be presented at the data output Bits 1 to 8. The least significant
byte will be presented on data output Bits 9 to 16 (with the
ENABLE input taken to a logic "Lo") regardless of the state of
the BYTE SELECT pin. Note that when the 2S82 is used with
a resolution less than 16 bits the unused data lines are pulled to
a logic "Lo." A logic "Hi" on the BYTE SELECT input will
present the eight most significant data bits on data output Bits 1
and 8. A logic "Lo" will present the least significant byte on
data outputs 1 to 8, i.e., data outputs 1 to 8 will duplicate 4ata
outputs 9 to 16.
The operation of the BYTE SELECT has no effect on the
conversion process of the converter.
RIPPLE CLOCK Output:
As the output of the converter passes through the major carry,
i.e., all "Is" to all "Os" or the converse, a positive going edge
on the RIPPLE CLOCK (RC) output is initiated indicating that
a revolution, or a pitch, of the input has been completed. The
~96
SYNCHRO & RESOL VER CONVERTERS
pulse has a minimum width of 300ns and is reset by the stan of
the next data update cycle.
DIRECTION Output:
The DIRECTION (DIR) logic output indicates the direction of
the input rotation, and this data is valid in advance of the RIPPLE
CLOCK pulse and stays valid until the direction changes. This
is the stan of the next data update cycle - if the direction of
rotation of the inputs has changed - and will be at least 300ns
after the rising edge of the RIPPLE clock.
The DIR and RC outputs are unaffected by the state of the
INHIBIT input.
COMPLEMENT
The COMPLEMENT pin is internally pulled up to + 12V in
the INACTIVATE STATE. It is pulled down to DIGITAL
GROUND (-I00 ....A) to ACTIVATE.
When used in conjunction with the DATA LOAD pin, Strobing
Data Load and COMPLEMENT pins "LOW" will set the logic
"HIGH" bits of the 2S82 counter to a "LOW" state. Those bits
of the applied data which are logic "LOW" will not change the
corresponding bits in the 2S82 counter.
For example:
Initial Counter State
Applied Data Word
Counter State after Data Load Only
- - - 1 0 1 0 1- - ---11000-----11000---
Initial Counter State
Applied Data Word
Counter State after Data Load
and Complement
---10101-----11000-----00101---
In order to read the output the following procedure should be
followed:
1. Place outputs in high impedance state (ENABLE- "HIGH").
2. Present data to pins.
3. Pull DATA LOAD and COMPLEMENT pins to ground.
4. Wait lOOns.
5. Remove data from pins.
6. Remove outputs from high impedance state (ENABLE"LOW").
7. Read Outputs.
CIRCUIT FUNCTIONS AND DYNAMIC
PERFORMANCE
The 2S82 allows the user great flexibility in choosing the dynamic
characteristics of the resolver-to-digital conversion to ensure the
optimum system performance. The characteristics are set by the
external components shown in Figure 1, and the section "COMPONENT SELECTION" explains how to select desired maximum
tracking rate and bandwidth values. The following paragraphs
explain in greater detail the circuit of the 2S82 and the variations
in the dynamic performance available to the user.
Loop Compensation
The 2S82 (connected as shown in Figure 1) behaves as a type 2
tracking servo loop where the VCO/counter combination and
the integrator perform the two integration functions inherent in
a type 2 loop.
Additional compensation in the form of a pole/zero pair is required
to stabilize any type 2 loop to avoid the loop gain characteristic
crossing the OdB axis with 180" of additional phase lag, as shown
in Figure 4. This compensation is implemented by the integrator
components (R4, C4, RS, CS).
2S82
The overall response of such a system is that of a unity gain
second order low pass filter, with the angle of the resolver as
the input and the digital position data as the output.
resolver is situated in particularly noisy environments, and the
user is advised to fit a simple HF fllter RI, C2 prior to the
phase sensitive demodulator.
The 2S82 does not have to be connected as tracking converter;
parts of the circuit can be used independently. This is particularily
true of the ratio multiplier which can be used as a control
transformer.
The attenuation and frequency response of a fllter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. The suggested fllter (RI, CI, R2, C2) is
shown in Figure I and gives an attenuation at the reference
frequency (fREP) of 3 times at the input to the phase sensitive
demodulator.
A block diagram of the 2S82 is given in Figure 3.
Values of the components used in the fllter must be chosen to
ensure that the phase shift at fREF is within the allowable signal
to reference phase shift of the converter.
sin II sin wt
CO& II
Phase Sensitive Demodulator
The phase sensitive demodulator is effectively ideal and develops
a mean dc output at the DEMODULATOR OUTPUT pin of
sin wt
-=--.r-
+2Y2
Figure 3. 2S82 Functional Diagram
Ratio Multiplier
The ratio multiplier is the input section of the 2S82 and compares
the signal from the resolver inputs, 6, to the digital angle, cj>,
held in the counter. Any difference between these two angles
results in an analog voltage at the AC ERROR OUTPUT. This
circuit function has historically been called a "Control Transformer" as it was originally performed by a mechanical device
known by that name.
The AC ERROR signal is given by
Al sin (6-cj» sinwt.
where w=2"IT fREP
fREP=reference frequency
AI, the gain of the ratio multiplier stage is 14.5 times.
So for 2V rms inputs signals
AC ERROR output in volts/(bit of error)
= 2xsin (3:) x Al
where p = bits per rev
1,024 for 10
= 4,096 for 12
= 16,384 for 14
= 65,536 for 16
bits resolution
bits
bits
bits
Giving AC ERROR output
178mV rms/bit @ 10 bits resolution
44.5mV rmslbit @ 12 bits
11.l25mV rmslbit @ 14 bits
2.78mV rmslbit @ 16 bits.
The ratio multiplier will operate in exactly the same way whether
the 2S82 is connected as a tracking converter or as a control
transformer, where data is preset into the counters using the
DATA LOAD pin.
HF Filter
The AC ERROR OUTPUT may be fed to the PSD via a simple
ac coupling network (R2, CI) to remove any dc offset at this
point. Note, however, that the PSD of the 2S82 is a wideband
demodulator and is capable of aliasing HF noise down to within
the loop bandwidth. This is most likely to happen where the
x (DEMODULATOR INPUT rms voltage)
for sinusoidal signals in phase or antiphase with the reference
(for a square wave the DEMODULATOR OUTPUT voltage
will equal the DEMODULATOR INPUT). This provides a
signal at the DEMODULATOR OUTPUT which is a dc level
proportional to the positional error of the converter.
DC Error Scaling = 160mVlbit (10 bits resolution)
40mVlbit (12 bits resolution)
IOmVlbit (14 bits resolution)
2.5mVlbit (16 bits resolution)
When the tracking loop is closed, this error is nulled to zero
unless the converter input angle is accelerating.
Integrator
The integrator components (R4, C4, R5, C5) are external to the
2S82 to allow the user to determine the optimum dynamic characteristics for any given application. The section "COMPONENT
SELECTION" explains how to select components for a chosen
bandwidth.
Since the output from the integrator is fed to the VCO INPUT,
it is proportional to velocity (rate of change of output angle) and
can be scaled by selection of R6, the VCO input resistor. This
is explained in the section "VOLTAGE CONTROLLED
OSCILLATOR (VCO)" below.
To prevent the converter from "flickering" (i.e., continually
toggling by ± I bit when the quantized digital angle, cj>, is not
an exact representation of the input angle, 6) feedback is internally
applied from the VCO to the integrator input to ensure that the
VCO will only update the counter when the error is greater than
or equal to I bit. In order to ensure that this feedback "hysteresis"
is set to ILSB the input current to the integrator must be scaled
to be lOOnAIbit. So,
R4 = DC Error Scaling (mVlbit)
100 (nAlbit)
MO
Any offset at the input of the integrator will affect the accuracy
of the conversion as it will be treated as an error signal and
offset the digital output. One LSB of extra error will be
added for each lOOnA of input bias current. The method of
adjusting out this offset is given in the section "COMPONENT
SELECTION."
SYNCHRO & RESOL VER CONVERTERS 5-97
II
Voltage Controlled Oscillator (VCO)
The veo is essentially a simple integrator feeding a pair of dc
level comparators. Whenever the integrator output reaches one
of the comparator threshold voltages, a fixed charge is injected
into the integrator input to balance the input current. At the
same time the counter is clocked either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the yeo.
The converter updates the output if the error is an LSB or
greater and the VCO output gives the positional error smaller
than lLSB.
During the reset period the input continues to be integrated
although the reset period is constant at 4OOns.
Transfer Function
By selecting components using the method outlined in the section
"Component Selection" the converter will have a critically damped
time response and maximum phase margin. The closed-loop
transfer function is given by:
The VCO rate is fixed for a given input current by the VCO
scaling factor,
=7.4kHzI,...A
The tracking rate in rps per ,...A of VCO input current can be
found by dividing the VCO scaling factor by the number of
LSB changes per rev (Le., 40% for 12-bit resolution).
The input resistor R6 determines the scaling between the converter
velocity signal voltage at the INTEGRATOR OUTPUT pin and
the veo input current. Thus to achieve a 5V output at 100 rps
(6000 rpm) and 12-bit resolution the VCO input current must
be:
(100 x 4096)/(7400) = 55.3,..,A
Figure 4 illustrates how the VCO output compensates for the
instances where, due to hysteresis, there is no change in the
digital count output for lLSB change in input angle. The sum
of the digital count output and VCO output equals the actual
input angle.
80UT =
8'N
(sN
14 (1 + SN)
+ 2.4) (SN 2 + 3.4 SN + 5.8)
where, SN, the normalized frequency variable is
=
SN
2 s
7i f Bw
and fBw is the closed-loop 3dB bandwidth (selected by the choice
of external components).
The acceleration constant, K A , is given approximately by
KA = 6 x (fBwi
Thus, R6 would be set to: 5/(55.3 x 10- 6) = 90kfl
The velocity offset voltage depends on the VCO input resistor,
R6, and the VCO bias current and is given by
Velocity Offset Voltage = R6 x (VCO bias current)
sec- 2
The normalized gain and phase diagrams are given in Figures 5
and 6.
The small signal step response is shown in Figure 6. The time
from the step to the first peak is tl> and the t2 is the time from
The temperature coefficient of this offset is given by
12
Velocity Offset Tempco = R6 x (VCO bias current
tetnpco)
where the
veo bias current tempco is typically
9
-0.5SnAfC.
The maximum recommended rate for the VCO is 1.1MHz which
sets the maximum possible tracking rate.
~
Since the maximum voltage swing available at the integrator
output is ± 8V, this implies that the minimum value for R6 is
54kfl. As
~
-9
= 149 : 10- 6 = 54kfl
O.02fBW O.04fBW
I
~
OUTPUT - . L S B :
O·2fsw
O.4faw
few
\
2faw
Figure 5. 2582 Gain Plot
I
I
180
135
I
~
I
·w
iI
i
H
I
I
I
I
I
I
II
I
I
I
I
Figure 4.
5-98 5YNCHRO & RE50L VER CONVERTERS
45
~
............
a.. -45
"
I
r
-90
I
-135
vco~1
I I
-3V I :
: I I
I I
OUTPUT
a.1faw
90
I
+3V
\
FREQUENCY
I
DIGITAL +.LSB
COUNT
0
\
-12
VCOOUTPUT
VCO OUTPUT: In order to overcome the "free play" inherent
in a servo system using digitized position feedback, an analog
output voltage is available representing the resolver shaft position
within the least significant bit of the digital angle output.
INPUT
ANGLE
"
-6
1.1 X 106
Max Current = 7.4 x 103 = 149,...A
Min Value
I--"""'
-180
O.02'BW O.04fBW
a·1faw
O.2faw
..... ~
O.4faw
FREQUENCY
Figure 6. 2582 Phase Plot
~
law
21aw
2S82
the step until the convener as settled to lLSB. The times t1 and
t2 are given approximately by
t2
= .1...
fow
OUTPUT
POSITION
x R
12
where R=resolution, Le., 10, 12, 14 or 16.
The large signal step response (for steps greater than 10 degrees)
applies when the error voltage will exceed the linear range of
the convener. Typically the converter will take 3 times longer
to reach the first peak for a 179 degrees step.
The response to a velocity step, the velocity output will exhibit
the same time response characteristics as outlined above for the
position output.
TIME
Figure 7. 2S82 Small Step Response
I
APPLICATIONS
USING THE 2S82 AS A CONTROL TRANSFORMER
The ratio multiplier section of the 2S82 can be used independently
to the rest of the convener to perform the function of control
transformer. In this mode the signal from the resolver inputs, 6,
is compared to a digital angle, <1>, loaded into the counters. Any
difference between these two angles results in an analog voltage
at the AC ERROR OUTPUT. To use the device in this way the
DATA LOAD pin is used.
where a = differential phase shift in degrees
and b = signal to reference phase shift in degrees.
This error can be minimized by choosing a resolver with a small
residual voltage, ensuring that the sine and cosine signals are
handled identically and removing the reference phase shift (see
section ''CONNECTING THE RESOLVER"). By taking these
precautions, the extra error can be made insignificant.
Applying a logic "Lo" to the DATA LOAD pin will allow data
to be loaded into the counters of the converter from the data
lines. It is imponant that the data lines are placed in the high
impedance state before loading data.
Resolver Phase Shift
Under static operating conditions phase shift between the reference
and the signal lines alone will not theoreticaJIy affect the converter's
static accuracy.
To operate the 2S82 as a tracking resolver-to-digital convener
the DATA LOAD pin should be left unconnected as it is pulled
high internally to + 12V.
However, most resolvers exhibit a phase shift between the signal
and the reference. This phase shift will give rise under dynamic
conditions to an additional error defined by:
CAUSES OF ADDITIONAL ERROR
Integrator Offset
Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator as it will
be treated as an error signal. This error will be typically 1 arc
minute over the operating temperature range.
A description of how to adjust for zero offset is given in the
section "COMPONENT SELECTION" and the circuit required
is shown in Figure 1.
Differential Phase Shift
Phase shift between the sine and the cosine signals from the
resolver is known as differential phase shift and can cause static
error. Some differential phase shift will be present on all resolvers
as a result of coupling. A small resolver residual voltage (quadrature
voltage) indicates a smaIl differential phase shift. Additional
phase shift can be introduced if the sine channel wires and the
cosine channel wires are treated differently. For instance, different
cable lengths or different loads could cause differential phase
shift.
The additional error caused by differential phase shift on the
input signals approximates to
Error = 0.53 a·b arc minutes
Shaft Speed (rps) x Phase Shift (Degs)
Reference Frequency
For example, for a phase shift of 20 degrees, a shaft rotation of
22 rps and a reference frequency of 5kHz, the convener will
exhibit an additional error of:
22 x 20
= 0.088 degrees
5000
This effect can be eliminated by putting a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver (see section "CONNECTING THE RESOLVER").
NOTE: Capacitive and inductive crosstalk in the signal and
reference leads and wiring can cause similar problems.
USING THE VELOCITY SIGNAL
The signal at the INTEGRATOR OUTPUT pin relative to the
ANALOG GROUND pin is an analog voltage proportional to
the rate of change of the input angle. This signal can be used to
stabilize servo loops or in place of a velocity transducer. Although
the conversion loop of the 2S82 includes a digital section there
is an additional totally analog feedback loop around the velocity
signal. This ensures that there is no digital effects on the output
signal and that the loop is closed even when the input signals
are such that the digital output does not change.
SYNCHRO & RESOL VER CONVERTERS 5-99
A better quality velocity signal will be achieved if the following
points are considered.
CONNECTING THE RESOLVER
The recommended connection circuit is shown in Figure 8.
1. Protection.
The velocity signal should be buffered before use.
2. Reversion Error.
If necessary, the reversion error can be reduced by a simple
trimming circuit. Reversion error, or side-to-side nonlinearity,
is a result of differences in the up and down rates of the
VCO. The reversion error can be nulled by varying one
supply rail relative to the other.
----7-::::J--o-0X"r1
lWISTEllPAI·Z-- ----
2S82
SCREENED
CABLE
3. Ripple and Noise.
L
Noise on the input signals to the converter is the major cause
of noise on the velocity signal. This can be reduced to a
minimum if the following precautions are taken:
.,
The resolver is connected to the converter using separate
screened twisted pair cable for the sine, cosine and reference
signals.
52
DIG&,:- 21
~(===
i'::~ 7-I-~==Jy reference to the part
numbers shown in the Specifications above.
r'IIII ANALOG
WDEVICES
Digital Director
SS04 I
FEATURES
15 VA Output Drive Capability at 400 Hz
±0.15° Accuracy
Measurement of External Synchro Inputs
Angle Position Indicator
Control Transformer Function
Coarse-Fine Synchro Transmission
User Selectable Output Functions (Motion Patterns)
Internal Isolating Transformers
IEEE (GPIB 488) Interface (Optional)
Isolated 16-Bit Natural Binary Outputs (Optional)
Tachogenerator Output (Optional)
APPLICATIONS
Simulation and Test of:
Synchro Transmitters
Synchro Receivers
Gun Mounting Servo Systems
Radar Processing Equipment
Naval Retransmission Systems
Measurement of Backlash in Servo System Gear
Boxes
Test of Digitally Controlled Machines
ATE Systems
6S04 FUNCTIONAL BLOCK DIAGRAM
KEYBOARD!
DISPLAY
CPU
DIRECTOR
a-lO-R
OUTPUT AMPLIFIER
It is designed as a portable Test Instrument and Synchro Simulator (Dummy Director) and its uses are the synchro transmitter
electrical output simulation and testing of equipment with synchro inputs such as gun mounting sensors, radar processing and
equipment and naval retransmission systems.
}
COARSE
SVNCHRO DIP
} FINE
SYNCHRO
INPUT RANGING
90 V, 26 V. 11.8 V, 4.25 V
API
5·TO·O
SYNCHRO liP SELECT
SYNCHRO·TO-DIGITAL
(TRANSFORMER IIPI
SSCT
OUTPUT AMPLIFIER
DIP PROPORTIONAL
TO DIFFERENCE BETWEEN
liP & DIP ANGLES
fmANSFORMER OIPI
IEEE 488
(OPTIONAL)
DIP
rOA~E
SVNCHROI/P
FINE
5VNCHRD IfP
} COARSE CT.
OUTPUT
} FINE CT.
OUTPUT
} IEEE-488
GPIB
DIGITAL OUTPUT
OPTO-ISOLATED
(OPTIONAL)
16
16
TACHO OUTPUT
OIP PROPORTIONAL TO
COARSE CHANNEL VELOCITY
(OPTIONAL)
GENERAL DESCRIPTION
The 6S04 Digital Director is a microprocessor based Universal
Synchro Simulator and Test Instrument.
RESOLVER TO SVNCHRO
ITRANSFORMER OIPI
DIGITAL-TO·RESOLVER
} COARSE 16-BIT
NATURAL BJNARY DIP
}ANE1fj...BIT
NATURAL BINARY O/P
}TACHOO/P
The Angle Position Indicator measures and displays synchro
format signals from either the director or an external synchro
transmitter. The angular position of the selected source is displayed on the front panel of the instrument.
The Solid State Control Transformer simulates the action of a
conventional control transformer by generating an analog signal
proportional to the. angular difference between the director output and the input from an external synchro transmitter.
The 6S04 can be considered as three autonomous units.
The Director simulates the electrical outputs of a synchro
coarse/fme transmitter. An operator can set the output of the
director at any fixed angle and also select from a suite of predefined patterns of motion, referred to as "output functions."
SYNCHRO & RESOLVER CONVERTERS 5-103
II
SPECIFICATIONS (typical at +25°C unless otherwise specified)
Electrical Specification
MAINS POWER SUPPLY (Single Phase)
Voltage Range
Supply Current
1.4 A (typ)
0.7 A (typ)
Dissipation 160W (typ)
Supply Frequency
Fuse
Isolation
115 V ac (90 V ac-132 Vac)
220 V acl240 V ac (180 V ac-265 Vac)
2 A (max) (115 V ac)
1 A (max) (230 V ac)
200 Watts (max)
47 Hz to 63 Hz
2.5 A Anti-Surge (115 V ac)
1.25 A Anti-Surge (230 V ac)
Both 5 mm x 20 mm
1000 V dc Input to Output
1000 V dc Input to Case
DUMMY DIRECTOR
COARSE AND FINE REFERENCE INPUT (User Provided)
Voltage
115 V rms ± 10% for Rated OfP
3 V to 120 V rms for API Function
Frequency
60 Hz ±10% or 400 Hz ±10%
Input Impedance
220 kO (Nominal)
Isolation
500 V dc Galvanic Isolation
INTERNAL COARSE OUTPUT
Voltage
(Synchro) 90 V ±2% Line-to-Line at Nominal
Reference and 100% Output Level
(SLAB) 4.25 V ±2% Line-to-Line at Nominal
Reference and 100% Output Level
Transformation Ratio
0.782 ±2% (Synchro)
0.037 ±2% (SLAB)
Voltage Range
50% to 110% of Nominal,
Resolution 1%, Accuracy ±0.5%
Resolution
0.01% of Output
±0.1°@ 5 VA
Angular Accuracy
±0.15°@ IS VA
±0.1%
Radius Vector Error
Energizing Power
15 VA @ 400 Hz Reference
5 VA @ 60 Hz Reference
Energizing Current
200 mA(max)
Regulation
Better than 5% at 5 VA
Better than 10% at 15 VA
Protected Against Open and Short
Protection
Circuits, and Thermal Overload with
Automatic Reset
500 V de Galvanic Isolation
Isolation
Update Interval
0.977 ms
Effective Stator
20 0 for 90 V Synchro Output
dc Resistance
1 0 for SLAB Output
INTERNAL FINE OUTPUT
As Above Except:
Voltage
(Synchro) 90 V ±2% Line-to-Line at
Nominal Reference and 100% Ouput Level
(SLAB) 11.8 V ±2% Line-to-Line at
Nominal Reference and 100% Output Level
Transformation Ratio
0.782 ±2% (Synchro)
0.037 ±2% (SLAB)
Effective Stator
20 0 for 90 V Synchro Output
2.4 0 for SLAB Output
de Resistance
~104
SYNCHRO & RESOLVER CONVERTERS
EXTERNAL COARSE AND FINE INPUT (for API)
Voltage
(a) 90 V ±20%
(b) 26 V ±20%
(c) 11.8 V ±20%
(d) 4.25 V ±20%
Frequency
Same as Reference
Allowable Phase Shift
±300 Under Static Conditions
(Signal to Reference)
Input Impedance
(a) 200 ill (Nominal)
(b) 58 kO (Nominal)
(e) 26 kO (Nominal)
(d) 9.5 ill (Nominal)
500 V de Galvanic Isolation
Isolation
±0.1°
Accuracy
0.01°
Resolution
CONTROL TRANSFORMER OUTPUT
VQ!tage
57.5 V ±5% at Nominai Externai
Synchro Input Level, No Load 90° Angular
Difference
Transformation Ratio
Tolerance ±5%
Load Impedance
Regulation
Angular Accuracy
Null Voltage
Protection
Isolation
Update Interval
Voltage Gradient
Effective Rotor dc
Resistance
(a) 0.638 for 90 V Range Selected
(b) 2.212 for 26 V Range Selected
(c) 4.873 for 11.8 V Range Selected
(d) 13.53 for 4.25 V Range Selected
00 to 10 ill
10%
±9 arc mins @ 0° Difference
IS0mV(max)
Protected Against Open and
Short Circuits
500 V de Galvanic Isolation
0.977 ms
IV Per Degree at Angles <5°
3300
DIGITAL OUTPUT (Option 090)
Collector Voltage
30 V de max
Collector Current (On)
1.6 mA min
500 nA nuix
Collector Current (Oft)
Isolation
500 V de
Data Strobe Low
20 II-S min
Duration
0.977 ms
Update Interval
TACHO OUTPUT (Option 900)
Resolution
0.1 deg/sec
Accuracy
± 1% of Output
0.977 ms
Update Interval
Voltage
10 V ± 1% at Velocity of 90 deg/sec
Relative to the Coarse Channel
Scaling Factor
III mVldeg/sec
Load Impedance
'" to 10kO
Protected Against Short Circuits
Protection
Specifications subject to change without notice.
6S04
DIRECTOR FUNCTIONAL DESCRIPTION
The director consists of two electronically geared transmitters,
each capable of providing a synchro transmitter output to an
accuracy of ±O.IO under full load conditions. The combined
accuracy of the two signals is determined by the gearing
employed.
The signals may be selected to be either Synchro 90 V rms on
both coarse and fine, or SLAB format, 4.25 V rms on coarse
and 11.8V rms on fine.
OUTPUT FUNCTIONS
The user may select from the output functions below.
I. Datum Angle
The combined coarse/fine output angle may be set at any
angle between 0.00° to 359.99° to accuracy of ±O.IO and
resolution of 0.01°.
2. Constant Velocity
The synchro output can be made to rotate at constant rates
in either direction at velocities from ±0.010 per second to
±359.99° per second.
3. Square Wave
The output can be made to oscillate with a square waveform
with a period selectable to any integer between I and 100
second and a peak-to-peak amplitude of between 0.00° and
± 179.99°. The starting datum angle may be set at any angle
in the range 0.00° to ±359.99°.
4. Sine Wave
The output can be made to oscillate sinusoidally with a
period selectable to any integer between I and 100 second
and a peak amplitude of between 0.00° to ± 179.99°. The center of oscillation may be set to any angle within the range
0.00° to ±359.9~.
5. Velocity + Square Wave
This function superimposes the velocity and square wave
functions as described above.
ANGLE POSITION INDICATOR (API)
The API may be set to measure either the angle output from the
Director or the angle input to the to the instrument from an
external synchro transmitter. Either the coarse, the fine or the
combined coarse and fine angle may be displayed. The display
will normally be updated at a rate of approximately three times
a second.
SOLID STATE CONTROL TRANSFORMER (SSCT)
The Solid State Control Transformer provides signals from both
the coarse and fine channels, which are an indication of the
angular difference between the director output, and the input
from an external synchro transmitter. When used with 90 V,
26 V, 11.8 V and 4.25 Van error signal is produced which is
scaled to give a I volt per degree of error. The null voltage is
150 mV maximum, which corresponds to an angular accuracy
of 0.15°.
IEEE INTERFACE (Option 009)
The instrument can be provided with an IEEE 488 standard 24
wire General Purpose Interface Bus, which allows any standard
IEEE controller to remotely operate the unit.
The IEEE standard 488 is a byte serial bit parallel interface system structured with 16 transmission lines of which 8 are data
bus lines, 3 are data byte transfer control lines (handshake) and
the remaining 5 are interface management lines.
The controller can set the unit to either Talk or Listen mode.
In the Listen mode the controller can operate the various key
functions, and in the Talk mode it can read the instruments API
display. Please refer to operating manual for operator setup procedure for the IEEE Bus.
Interconnections
Refer to an IEEE handbook for detailed information and
specifications.
6. Manual Control
Using the control knob, the velocity of the output angle can
be varied mannually between 0° and ±90° per second on a
logarithimic scale. In this mode, two push buttons are also
enabled which allow the output angle to be stepped, either
forwards or backwards by a fixed preselected amount between
0.00° to ±179.W. These "INCH" keys are also enabled with
the velocity function thus allowing manual steps to be superimposed on constant velocity.
SYNCHRO & RESOLVER CONVERTERS 5-105
..
..
DIGITAL OUTPUT (Option 090)
The digital output consists of two 16-bit parallel data channels
carrying digital representations of the coarse and fme output
angles. These are automatically updated with the coarse and fine
output angles. Data is in .the form of an unsigned 16-bit binary
integer with the most significant bit representing 180 degrees.
BIT NO.
11MSBI
2
3
4
45
5
6
7
8
9
10
11
12
13
14
15
161LSBI
DATA
BIT WEIGHT 1°1
180
90
22.5
11.25
5.625
2.812
1.406
0.703
0.352
0.176
0.088
0.044
0.022
0.011
0.005
~~___DA_T_A_VA_L_'D__~~~__D_M_A_V_AL_'D____
PHYSICAL SPECIFICATIONS
Depth = 478 rom (18.8'~
Width = 432 rom (17")
Height = 178 rom (7")
Dimensions
Weight
18.5 kg (40.78Ibs)
Low Temperature
Storage - 25°C; Operating O°C per
MIL-STD-810D, Method 502.2,
Procedure II
High Temperature
Storage + 70°C; Operating +45°C
per MIL-STD-810D, Medthod 501.2,
Procedure II
Humidity
90% RH at 30°C per MIL-STD-810D,
Method 507.2, Procedure III
Moisture Ingress
MIL-STD-810D, Method 507.2
Procedure II
Vibration
DEF STAN 66-31 CAT II
Fusing
1.25 A, 2.5 A Anti-Surge (5 rom x 20 mm)
Dissipation
200 Watts max
Safety
Designed to Comply with BS4743 Class I
Finish
Anodized per BS1615
Painted per BS3900 Part A8
Light Grey
OUTLINE DIMENSIONS
Dimensions shown in inches and (rom).
Tolerances ± 1 rom unless otherwise stated.
Digital Output Timing
TACHO OUTPUT (Option 900)
The tacho output provides an analogue voltage signal via a BNC
output socket which is proportional to the angular velocity of
the coarse channel outputs.
IO(e)o.
.
.
..
P~~:L 0··
.@
°
•
..
°
ORDERING INFORMATION
1
6S04999
_ I_ _
,--I~
IEEE 488 Interface
TOP
SIDE
PANEL
COVER
15.6 (398)
Digital Output
Tacho Output
NOTES
Insert 0 in place of 9 if option is not required.
Options are factory fitted only.
An operating manual is available upon request.
...1...1.571401
••
_"====!J
-r---
'n--------rr'J
1:1
1:1
FRONT
PANEL
fI
~OODO~D~.C] •
I.
5-106 SYNCHRO & RESOLVER CONVERTERS
•
17(432)
.1
~
SamplelTrack-Hold Amplifiers
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . . .
Orientation . . . . . . . . . . . . . . . . . . . .
AD346 - High Speed Sample-and-Hold Amplifier
AD386 AD389 AD582 AD583 AD585 -
True 16-Bit Track-and-Hold Amplifier .
High Resolution Track-and-Hold Amplifier
Low Cost Sample-and-Hold Amplifier . . .
Sample-and-Hold Amplifier . . . . . . . . .
High Speed Precision Sample-and-Hold Amplifier
AD684 - Four Channel Sample-and-Hold Amplifier . . . .
ADll54 - Low Cost l6-Bit Accurate Sample-and-Hold Amplifier
HTC-0300A - Ultrahigh Speed Hybrid Track-and-Hold Amplifier
HTS-OOIO - Ultrahigh Speed Hybrid Track-and-Hold Amplifier
HTS-0025 - Ultrahigh Speed Hybrid Track-and-Hold Amplifier .
6-2
6-3
6-5
6-11
6- 25
6 - 31
6- 35
6666-
37
43
51
57
6 - 61
6 - 67
1m
SAMPLEITRACK-HOLD AMPLIFIERS 6-1
?'
Selection Guide
3:::
Sample/Track and Hold Amplifiers
'"~
~
~
~
Acquisition
Time
.... s
max
Aperture
Time
ns
Model
Specified
Accuracy
%
*AD1154
*AD386
AD389
HTC-0300A
*AD684
AD346
AD585
AD583
HTS-OOI0
HTS-0025
AD582
0.00076
0.00076
0.003
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.1
3.5
4.5
2.5
0.1
1.0
2.0
3.0
5.0
0.014
0.025
6.0
~
~
r-
\:)
~
~
r:!i
Sl
til
typ
Aperture
Jitter
ns
typ
Droop
Rate
....V/ ....s
max
80
12
30
6
25
60
35
50
2
5
200
0.15
0.040
0.4
0.05
0.2
0.4
0.5
5
0.005
0.02
15
0.1
0.1
0.1
0.5
0.001
0.5
Package
Options'
Temp
Range'
Page
Comments
D
D
D
D
P,Q
D
E,P,Q
D
D
D
D,H
C,I
I,M
C,I
I,M
C,I,M
C,M
C,I,M
C
C,I
C, I
C,M
6-51
6-11
6-25
6-57
6-43
6-5
6-37
6--35
6-61
6-67
6--31
Hi-Bit Accurate Sample-and-Hold Amplifier
Hi-Bit Accurate Sample-and-Hold Amplifier
High Resolution Track-and-Hold Amplifier
Ultrahigh Speed Track-and-Hold Amplifier
Ql~ad, Monolithic l .... s SHA
High Speed Sample-and-Hold
H1igh Speed, Precision. On-Board Hold Cap
5~,s SHA
Ulltrahigh Speed Track-and-Hold Amplifier
UItrahigh Speed Track-and-Hold Amplifier
Low Cost, 15fLS
1 Package Options: D-Side-Brazed Dual-In-Line Cerantic; E-Leadless Chip Carrier; H-Round Hermetic Metal Can (Header); P-Plastic Leaded Chip Carrier (PLCC); Q-Cerdip.
'Temperature Ranges: C-Commercial, 0 to + 70°C; I-Industrial, -40°C to +85°C (Some older products -25°C to +85°C); M-Military, -55°C to + l25'C_
Boldface Type: Product recommended for new design_
*New product since the publication of the 1987/1988 Databooks.
Orientation
Sample/Track-Hold Amplifiers
The technical data in this volume embrace high-performance
(high-resolution and high-speed) sample/track-holds in the form
of monolithic and hybrid ICs. Besides the products in this section
(stand-alone devices for performing the sample/track-hold function) similar functions can be found integrated into a variety of
component and subsystem products. Component examples: a
number of video A/D converters have on-board track-holds
(MOD-120S); the monolithic AD7S79/7S80 AID converters have
integral sample-hold functions; and high-resolution D/A converters
have deglitcher options (Deglitcher IV for the DACl138). Besides
these, sample-hold functions are inherent in data-acquisition
subsystems and microcomputer analog 1/0 boards.
The principal application for sample/track-hold amplifiers is to
maintain an analog-to-digital converter's input constant during
conversion at a value representing the analog input as of a certain
precisely known time. The characteristics of the SHA are crucial
to system accuracy and the reliability of the digital data, especially
in 2: 12-bit and/or high-throughput-rate applications.
A sample/track-hold amplifier (sib or SHA), as its name indicates,
has two modes of operation, programmed by a digital control
input. In the lTack or sample mode, the output follows the input,
usually with a gain of + 1. When the mode input switches to
hold, the output of the SHA ideally retains the last value it had
when the command to hold was given, and it retains that value
until the logic input dictates lTack (sample), at which time the
output ideally jumps to the input value and follows the input
until the next hold command is given.
Analog Devices' lTack-holds and sample-holds are functionally
identical; they are designed to acquire input signals for either
immediate hold or for a possibly extended period of tracking.
They should not be confused with ac devices termed "sample-hold"
that can only obtain quick samples and cannot track the input
continuously.
SHA CIRCUITRY AND HARDWARE
A sample-hold amplifier usually consists of a storage capacitor,
input- and output-buffer amplifiers and a switch and its drive
circuitry. During sample, the circuit is connected to promote
rapid charging of the capacitor. During hold, the capacitor is
disconnected from its charging source and ideally retains its
charge. The following figure shows a typical feedback confignration: the input buffer is a high-gain differential amplifier with a
current output that charges the capacitor through the logic-controlled switch. The capacitor is unloaded by a unity-gain buffer-fol-
HIGH GAIN
.~:?:ffi+~
_1MODE CONTROL
lower. The output is fed back to the negative input (as in an op
amp follower configuration), and thus, in sample the charge on
the capacitor is compelled to follow the input. In hold, the input
amplifier no longer drives the capacitor; it retains its charge,
unloaded by the output follower. In another popnlar configuration,
the capacitor is used as the feedback element of an inside-the-loop
integrator (AD346). The highest-speed devices usually run openloop.
Since drive current is finite and leakage current in hold is not
zero, the capacitance, if large, limits the slewing rate in sample
and, if small, converts leakage current to "droop" in hold. In
sib modules, the capacitance is usually fixed, and the properties
of the complete device are optimized for one condition, and so
specified. In slh monolichic les, the capacitor may be omitted
and furnished by the user (both for flexibility and because good
capacitors for this purpose are hard to integrate); the AD346
and ADS85 have internal hold capacitors. The optimum capacitance can be selected for the specific application.
PERFORMANCE
In the sample mode, it is useful to consider that a SHA's performance can be characterized by specifications similar to those
of a closed-loop operational amplifier (offset, drift, nonlinearity,
gain error, bias current, etc.), but with somewhat slower response
(gain-bandwidth, slewing rate, settling time) because of the need
to charge the storage capacitor.
However, during the sample-to-hold, hold and hold-co-sample
states, the dynamic nature of the mode-switching introduces a
number of specifications that are peculiar to SHAs. The most
important of these are defined below and illustrated in the adjoining
figure. They include the aperture time and its uncertainty, the
sample-co-hold step, feedthrough and droop (in hold) and acquisition
time.
SAMPLEITRACK-HOLD AMPLIFIERS 6-3
6
HOLD/SAMPLE DELAY
establishes the ultimate timing error, hence, the maximum sampling frequency to a given resolution. For example, the HTC0300A specs are 8ns aperture time and lOOps aperture jitter.
Charge Transfer (or offset step), the principal component of sampleto-hold offset (or pedestaT), is the charge transferred to the storage
capacitor via stray capacitance when switching to the hold mode.
HOLD
~r--I/~~--~~_
SAMPLE
LOGIC INPUT
SAMPLE
DEFINITIONS
ACq".li.,"ir:wn Time is the tinle required by the output of the device
to reach its final value, within a specified error band, after the
sample command has been given. Included are switch-delay
time, the slewing interval and settling time for a specified outputvoltage change.
Aperture (Delay) Time is the time required after the hold command
for the switch to open fully. The sample is, in effect, delayed by
this interval, and the hold command would have to be advanced
by this amount for precise timing.
Aperture Uncertainty - or Aperture (Delay) Jiller - is the range of
variation in the aperture time. If the aperture time is "tuned out"
by advancing the hold command a suitable amount, this spec
6-4 SAMPLEITRACK-HOLD AMPLIFIERS
It can sometimes be reduced by lightly coupling an appropriate
polarity version of the hold signal to the capacitor for cancellation.
The associated voltage error (boQ/C) can be reduced by using
greater capacitance for storage, but this increases response time.
Droop is the change of the output voltage during hold as
II result
of leakage or bias currents flowing through the storage capacitor.
Its polarity depends on the sources of leakage current within a
given device. In les) it is specified as a (droqp or drift) current,
in modules, a dV/dt. [Note: I = C(dV/dt).]
F eedthrough is the fraction of the input signal variation or ac
input waveform that appears at the output in hold. It is caused
by stray capacitive coupling froljl the input to the storage capacitor,
principally across the open switch.
Sample-to-Hold Offset, a shift in level between the last value in
sample and the value settled-to in hold, is the residual step error
after the charge transfer is accounted for and/or cancelled. Since
it is unpredictable in magnitude and may be a function of the
signal, it is also known as offset nonlinearity.
High Speed
Sample-and-Hold Amplifier
AD346
r'IIANALOG
WDEVICES
FEATURES
Fast 2.0jLs Acquisition Time to :!:0.01%
Low Droop Rate: 0.5mV/ms
Low Offset
Low Glitch: <40mV
Aperture Jitter: 400ps
Extended Temperature Range: -55°C to
Internal Hold Capacitor
MIL-STD-8838 Processing Available
I
AD346 FUNCTIONAL BLOCK DIAGRAM
+ 125°C
ANALOG
OUTPUT
ANALOG
GND
PRODUCT DESCRIPTION
The AD346 is a high speed (2J.Ls to 0.01%), adjustment free
samp1e-and-hold amplifier designed for high throughput rate
data acquisition applications. The fast acquisition time (21'-s to
0.01%) and low aperture jitter (400ps) make it suitable for use
with fast AID converters to digitize signals up to 97kHz.
PRODUCT HIGHLIGHTS
1. The AD346 is an improved second source for other sample
and holds of the same pin configuration.
The AD346 is complete with an internal hold capacitor and it
incorporates a compensation network which minimizes the sample
to hold charge offset. The AD346 is also laser trimmed to eliminate
the need for external trimming potentiometers.
3. The droop rate is only 0.5mV/ms so that it may be used in
slower high accuracy systems without the loss of accuracy.
Typical applications for the AD346 include sampled data systems,
D/A deglitchers, peak hold functions, strobed measurement
systems and simultaneous sampling converter systems.
The device is available in two versions: the "1" specified for
operation over the 0 to + 70°C commercial temperature range
and the "s" specified over the extended temperature range,
- 55°C to + 125°C.
2. The AD346 provides separate analog and digital grounds,
thus improving the device's immunity to ground and switching
transients.
4. The fast acquisition time and low aperture make it suitable
for very high speed data acquisition systems.
PIN CONFIGURATION
DIGITAL INPUT
-15V
ANALOG INPUT
SUMMING PT
+15V
ORDERING GUIDE
NIC
Model
Temperature
Range
Package
Option*
AD346]D
AD346SD
AD346SD/883B
Oto + 70°C
- 55°C to + 125°C
- 55°C to + 125°C
DH-14A
DH-14A
DH-14A
"'See Section 14 for package outline information.
SAMPLEITRACK-HOLD AMPLIFIERS 6-5
II
SPECI FICAT ION S(typical
@
+ 25°C, Vs = ± 15V unless otherwise noted)
Model
AD346JD
AD346SD
Units
ANALOG INPUT
Voltage Range
Input Impedance
±10.0
3.0
*
*
Volts
kO
DIGITAL INPUT
"0" Input Threshold Voltage (Hold)
"I" Input Threshold Voltage (Sample)
"0" Input Current
"I" Input Current
+O.Smax
2.0 min
- 360ILA (max)
2OILA(max)
*
*
*
*
Volts
Volts
ILA
",A
TRANSFER CHARACTERISTICS
Gain
Gain Error
Gain Error, T min - T max
Offset Voltage
Offset Voltage, T min - Tmax
Pedestal
Pedestal, T min - T max
Droop Rate
Droop Rate, T min - T max
-1.0
±O.02max(±O.0l typ)
±O.OS max(±0.03typ)
±3max(±ltyp)
±20max(±6typ)
±4max(±2typ)
±20max(±Styp)
O.5rl1ax(O.1 typ)
60 max (20 typ)
*
*
*
*
*
*
±20max(± lOtyp)
VN
%FSR
%FSR
mV
mV
mV
mV
"700 max (200 typ)
mV/ms
mV/ms
1.4
50
*
*
MHz
VI",s
2.0 max (1.0 typ)
2.5max(1.6typ)
60 max (30 typ)
0.4
*
*
*
*
",s
ns
ns
2.0max (1.0 typ)
500
*
*
",s
ns
0.02max(0.OOStyp)
*
%FSR
40
*
mV
± 10.Omin
3.0
*
*
Volts
rnA
± 12 to ± 18
*
Volts
IS max (9 typ)
-lOmax( -3typ)
100
500 max (200 typ)
*
*
*
*
mA
rnA
",VN
mW
DYNAMIC CHARACTERISTICS
Full Power Bandwidth
VOUT = + IOV, -3dB
Output Slew Rate
Acquisition Time
To ± 0.01 % lOY Step
To ±0.01%20VStep
Aperture Delay
Aperture Jitter
Settling Time
Sample Mode (IOV Step)
Sample to Hold
Feedthrough (Hold Mode)
at 1kHz
Transient Peak Amplitude
Sample/Hold/Sample
ANALOG OUTPUT
Output Voltage Swing'
Output Current
POWER REQUIREMENTS
Operating Voltage Range
Supply Current
+V
-V
Power Supply Rejection Ratio
Power Consumption
",S
NOTES
'Maximum output swing is 4V less than + Vs.
·SpecificationsssmeasAD346JD.
Specifications subject to change without notice.
+v,
Figure 1. Functional Block Diagram
6-6 SAMPLEITRACK-HOLD AMPLIFIERS
AD346
3.2
+5
2.8
w 2.4
!Z
~
5
~
-
2.0
1.6
1.2
0.01% FSR
~
SlH
........
0.8
.--
r-
OFFSET
INMV
-5
O.I%FSR
V
~
~
............
~
0.4
10
-55
20
15
+25
25
+70
+125
TEMPERATURE _ °C
OUTPUT VOLTAGE SWING
Figure 2. Acquisition Time vs. Output Voltage
Figure 4. SIH Offset Drift (Typical)
4.0
450
3.6
V Input"" ±5V
405
3.2
360
2.8
,.'"
0.01% FSR
2.4
::!
/
2.0
::!
.
;::
1.6
0
51
0.1% FSR
"
1.2
315
I
160
I
135
0.8
90
0.4
45
/
-25
+25
+70
+125
-55
-25
+25
+125
+70
TEMPERATURE - "C
TEMPERATURE - OC
Figure 3. Acquisition Time vs. Temperature
/
,,/
o
o
-55
I
1
270
225
Figure 5. Droop vs. Temperature (± 5 Volts)
TERMINOLOGY
Aperture Time is the time required after the "hold" command
HOLO/SAMPLE OELAV
until the switch is fully open and produces a delay in the effective
sampling timing.
Aperture Jitter is the uncertainty in Aperture Time. If the Aperture
Time is "tuned out" by advancing the sample-to-hold command
with respect to the input signal, the Aperture Jitter now determines
the maximum sampling frequency.
Acquisition Time is the time required by the device to reach its
fInal value within a given error band after the sample command
has been given. This includes switch delay time, slewing time
and settling time for a given output voltage change.
Droop is the change in the output voltage from the "held" value
as a result of device leakage.
Feedthrough is that component of the output which follows the
input signal after the switch is open. As a percentage of the
input, feedthrough is determined as the ratio of the feedthrough
capacitance to the hold capacitance (CF/CW.
Pedestal during hold is a sample-to-hold offset. This is an offset
~~____________
H_O_LD
__________~
LOGIC INPUT
Figure 6. Pictorial Showing Various SIH Characteristics
that occurs from such phenomena as charge dumps when switches
are opened, coupling of the logic signal transients.
Transients are the spikes or glitches that occur on the output at
the start and end of hold time.
SAMPLEITRACK-HOLD AMPLIFIERS 6-7
•
GROUNDING
Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
"grounds" are usually referred to as the Logic Power Return,
Analog Common (Analog Power Return), and Analog Signal
Ground. These grounds must be tied together at one point,
usually at the system power-supply ground. Ideally, a single
solid ground would be desirable. However, since current flows
through the ground wires and etch stripes of the circuit cards,
and since these paths have resistance and inductance, hundreds
of millivolts can be generated between the system ground point
and the ground pins of the AD346. Separate ground returns
should be provided to minimize the current flow in the path
from sensitive points to the system ground point. In this way
supply currents and logic-gate return currents are not summed
into the same return path as analog signals where they would
cause measurement errors.
:::t:=1::::::~::::;:::::::::::=1;:~~:+16V
-16V
ANALOG
INPUT
OTO 10V
13
1'0346 6t-------~
20
21
STATUS
CONVERT
START
Figure 9. 142.8kHz-12-Bit, AID Conversion System
:::t::1=::::::~:::;:::::::::::::;::~:::~~~~
r---~-1r--1r-+6V
DIGITAL
DATA
1-_::":':::"':'=_--124
ANALOG
INPUT
OTO 10V
13
OUTPUT
1'0346 61------~
AD ADCB5
·IF INDEPENDENT, OTHERWISE
RETURN AMPLIfiER REfERENCE
TO MECCA AT ANALOG P.S. COMMON
Figure 7. Basic Grounding Practice
20
SAMPLED DATA SYSTEMS
The fast acquisition time of the AD346 when used with a high
speed AID converter allows accurate digitization of high frequency
signals and high throughput rates in multichannel data acqusition
systems. The AD346 can be used with a number of different
AID converters to achieve high throughput rates. Figures 8, 9
and 10 show the use of an AD346 with the AD578, AD5240
and AD ADC8S.
:::t:=1::::::=l::::;:::::::::::~;:~~:+15V
-15V
. - - -......- + - + - + 5 V
t---';":':'--=---f 27
ANALOG
INPUT
OTO IOV
13
1'0346 6 1 - - - - - - - , ... 30
A057BK
~----
CONVERT
START
______~16
STATUS
Figure 8. 153kHz-12-Bit, AID Conversion System
6-8 SAMPLEITRACK-HOLD AMPLIFIERS
CONVERT
START
21
STATUS
Figure 10. 83.3kHz-12-Bit, AID Conversion System
In sampled data systems there are two limiting factors in digitizing
high frequency signals. The first limitation is the bandwidth
and aperture uncertainty of the sample-and-hold amplifier. The
second limitation is the maximum update rate for the SHA and
AID converter combination. For high throughput rate data
acquisition systems all factors must be understood .
The aperture time is the time required for the sample and hold
amplifier to switch from sample to hold. Since this is a constant
it can' be tuned out by advancing the sample-to-hold command
by 60ns with respect to the input signal and, therefore, can be
eliminated as an error source. Once the aperture time has been
eliminated the aperture jitter which is the variation aperture
time from sample-to-sample, remains. The aperture jitter is a
true error source and must be considered. The aperture jitter is
a result of noise within the switching network which modulates
the phase of the hold command and is manifested in the variations
in the value of the analog input that has been held. The aperture
error which results from this jitter is directly related to the dVI
dt of the analog input.
AD346
The error due to aperture jitter is easily calculated as shown
below. The error calculation takes into account the desired
accuracy corresponding to the resolution of the AID converter.
=
F
max
(Full Scale Voltage) (2·N )
(2) (Full Scale Voltage) 'IT (Aperture Jitter)
:. For an application with a 10-bit AID converter with a IOV full
scale:
(10) 2- 10
Fmax = (2) (10) 'IT (4 x 10- 10 sec)
Fmax = 388.6kHz.
For an application with a 12-bit AID converter with a IOV full
scale:
(10) 2-12
2 (10) 'IT (4 X 10- 10 sec)
Fmax = 97.lkHz.
The maximum throughput rate is the sum of the sample-and-hold
acquisition time, settling time and the AID conversion time as
shown in Figure II.
CONVERT
START
nL-____
The maximum input frequency is constrained by the Nyquist
sampling theorem to be half of the maximum throughput rate.
Input frequencies higher than half the maximum throughput
rate result in "under sampling" or aliasing errors of the input
signal. In the following table the maximum input frequency is
reported as half of the throughput rate, what has been assumed
is that an ideal brickwall filter has been placed in the signal
path prior to the AD346 and AID converter.
AD346in
Combination Throughput
With an
Rate
Input Frequency
Range
AD578K
AD5240
ADADC85
AD579
HASI202
dc to 76.5kHz
dc to 71.5kHz
dc to 41.6kHz
dcto 131kHz
dcto 125kHz
153kHz
143kHz
83.3kHz
263kHz
250kHz
Table I. SHA & ADC Combinations and Maximum
Throughput Rate
~_ _ _ _ _ _ _ _......
I--- T CONV ---I
STATUS _ _ _- '
STATUS CONNECTED TO SAMPLE AND HOLD MODE CONTROL
Figure ". Start/Status Timing for Sampled Data System
MULTICHANNEL CONVERSION
In multichannel conversion systems, elements of the acquisition
chain may be shared by two or more input sources. This sharing
may occur in a number of ways, depending on the desired properties of the multiplexed system.
The data acquisition system shown in Figure 12 is one solution
to digitizing data from many analog channels. For most efficient
use of time, the multiplexer is acquiring the next channel to be
converted while the sample-hold is holding the previous output
level for conversion. When conversion is complete, the status
line from the converter causes the SIH to return to the sample
mode and acquire the new data. After the acquisition time is
completed, the sample hold can be switched to hold. A conversion
can then begin and the multiplexer can be switched to the next
channel.
In applications where the AD346 is to be driven from high
impedance sources or directly from an analog mUltiplexer, a fast
slewing, fast settling wideband op amp like the ADLH0032
should be used as an input buffer.
Figure 12. Data Acquisition System
SAMPLEITRACK-HOLD AMPLIFIERS 6-9
6-10 SAMPLEITRACK-HOLD AMPLIFIERS
True 16-Bit
Track-and-Hold Amplifier
AD386 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
Companion to True 16-Bit AID Converters
16-Bit Linear (-40°C to +8S0 C)
14-Bit Linear (-55°C to +12S 0 C)
Fast Acquisition Time: 3.6 ~s to 0.00076%
Low Droop Rate: 20 ~V/ms
Differential Amplifier for Ground Sense
Low Aperture Jitter: 40 ps
AD386 FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Medical and Analytical Instrumentation
Signal Processing
Multichannel Data Acquisition Systems
Automatic Test Equipment
Guidance and Control
Sonar
PRODUCT DESCRIPTION
The AD386 is a high accuracy, adjustment free track-andhold amplifier designed for high resolution data acquisition
applications. The fast acquisition time (3.6 IJ.S to 7S IJ.V) and
low aperture jitter (40 ps) make it ideal for use with fast AID
converters.
The AD386 is complete with an internal hold capacitor, and it
incorporates a compensation network which minimizes the
track-to-hold charge offset and dielectric absorption. The
AD386 also includes an internal differential amplifier for very
high accuracy applications.
II
Tiji
Typical applications for the AD386 include sampled data system, peak hold function, strobe measurement system and simultaneous sampling converter systems. When used with autozero
and autocalibration techniques, this T/H combined with a high
linearity AID will offer true 16-bit performance (0.00076%
linearity) over the industrial temperature range, and 14-bit performance (0.003% linearity) over the military temperature range.
GND
+DIFF IN
-DIFF IN
ORDERING GUIDE
DIFF DUT
~odel
Max Linearity
Error
Temperature
Range
Package
Option*
GND
AD386BD
AD386TD
0.00076% FSR
0.003% FSR
-40°C to +8SoC
-SsoC to +12SoC
Ceramic (DH-24B)
Ceramic (DH24B)
NC
·See Section 14 for package outline information.
SHAIN
GND
NC
NC
NC
NC
NC= NO CONNECT
:.t1S Vb - DIFF AMP ONLY
:t15 Va - SHA ONLY
AD386 Pin Configuration
SAMPLEITRACK-HOLD AMPLIFIERS 6-11
SPECIFICATIONS
Model
(@ +25°C unless otherwise noted, Vs
Conditions
Min
= ±15 V ±10%)
AD386BD
Typ
Max
Min
AD386TD
Typ
Max
Units
DIFFERENTIAL AMPLIFIER
INPUT CHARACTERISTICS
Input Range
Common-Mode Range
Input Resistance'
Signal
Ground Sense
Offset'
Offset Drift
CMRR
PSRR3
TRANSFER CHARACTERISTICS
Gain
Gain Error
Gain Error Drift
Gain Linearity
Gail! Linea. . ity Drift
Noise (ENBW = 1.8 MHz)
DYNAMIC CHARACTERISTICS
Small Signal Bandwidth
Slew Rate
Settling Time'
10 V Step to 112 LSBI6
10 V Step to 1/2 LSBI4
20 V Step to 1/2 LSBI6
20 V Step to 112 LSBI6
20 V Step to 1/2 LSB 14
20 V Step to 1/2 LSBI4
OUTPUT
Voltage
T min to Tmax
VCM = ±IO
80
76
5
10
0.6
10
90
85
2.0
30
80
76
-I
T min to Tmax
'T'
1
0.0002
0.01
32
.. _ 'T'
.Lmin lU .lmax
2.0
0.8
2.0
2.0
0.8
0.8
T min to Tmax
Two to Tmax
V
V
5
10
0.6
10
90
85
2.0
30
I
0.0002
0.01
32
0.05
45
",VI'C
VN
0.02
5
0.003
0.05
45
6
65
3.0
1.5
3.0
3.0
1.5
1.5
kG
kG
mV
dB
dB
-I
0.02
5
0.00076
6
65
%
ppml'C
%
ppml'C
",Vrms
MHz
V/",s
",s
0.8
1.5
",S
",s
",S
0.8
0.8
1.5
1.5
",S
",S
R LoAo >3.5 kG,
Tmin to Tmax
Current
±1O
±IO
±1O
±IO
±10
Short Circuit
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
±10
15
±15
±5
4.2
V
mA
15
±15
±18
5.0
±5
4.2
±18
5.0
V
V
rnA
TRACK-AND-HOLD
INPUT CHARACTERISTICS
Input Range
Input Resistance'
Offset2
Offset Drift
TRANSFER CHARACTERISTICS
Gain
Gain Error
Gain Error Drift
Gain Linearity
Gain Linearity Drift
PSRR3
±10
T min to Tmax
5
0.6
10
2.0
30
T min to Tmax
T min to Tmax
76
I
0.0002
0.01
85
0.02
5
0.00076
0.05
76
2
IS
0.5
T min to Tmax
T rnin to Truax
0.0004
12
6-12 SAMPLEITRACK-HOLD AMPLIFIERS
600
400
I
0.0002
0.01
85
1.5
5.0
0.00076
0.5
0.0004
12
40
400
",VI'C
%
ppml'C
%
ppml'C
dB
MHz
VI",.
1.5
7.5
0.003
mV
mV
%
ns
ps
800
500
V
kG
mV
VN
0.02
5
0.003
0.05
2
IS
40
TOlin to Tmax
T_ to Tmax
2.0
30
-I
-I
DYNAMIC CHARACTERISTICS
Small Signal Bandwidth
Slew Rate
TRACK-TO-HOLD SWITCHING
Pedestal + Offset
Pedestal + Offset
Pedestal Linearity
Aperture Delay
Aperture Jitter
Transient Settling'
to 1/2 LSBI6
to 112 LSBI4
±10
5
0.6
10
500
ns
ns
AD386
Conditions
Model
HOLD MODE
Droop Rate
Droop Rate
Feedthrough'
Noise (ENBW = 1.7 MHz)
PSRR3
Dielectric Absorption"
HOLD-TO-TRACK
Acquisition Time'
10 V Step to 112
10 V Step to 112
20 V Step to 1/2
20 V Step to 112
20 V Step to 112
20 V Step to 112
Min
AD386BD
Typ
Max
20
0.2
Tmax
60
100
1.0
-99
-94
32
66
7
50
3.6
3.1
3.6
4.0
3.1
3.5
4.1
3.6
4.1
4.5
3.6
4.0
60
10
Typ
Max
Units
20
3.6
-99
32
66
7
100
IB
Vis
3.1
3.6
3.1
4.0
3.6
4.5
IL S
ILS
ILS
ILS
ILS
ILS
0.8
+10
+10
V
V
ILA
ILA
-94
50
10
mWs
dB
ILVrms
dB
ppm
DYNAMICS
LSBI6
LSB14
LSB 16
LSBI6
LSB 14
LSB14
T olln to Tmax
T min to Tmax
DIGITAL INPUTS
VIH
V'L
IIH
IlL
Tm.io
to
Tmax
T min to T max
T roin to Tmax
T min to Tmax
OUTPUT
Voltage
2.4
2.4
0.8
+10
+10
-10
-10
-10
-10
R LoAD >3.5 kG,
Tmin to Tmax
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Positive Supply
Negative Supply
±1O
±10
Shon Circuit
Current
-6.0
Gain Linearity
Acquisition Time" 7
20 V Step to 112 LSB 16
20 V Step to 1/2 LSB16
20 V Step to 1/2 LSB14
20 V Step to 1/2 LSB14
Power Dissipation
Tmin to Tmax
T min to Tmax
T min to Tmax
TEMPERATURE RANGE
Operating
Storage
±IB
B.O
-5.4
12.0
0.0003
0.00076
4.1
4.5
3.2
3.6
312
5.1
5.4
3.9
4.3
435
+15 V, -Vs
=
+B5
-55
-60
+150
-60
V
V
B.O
-5.4
12.0
rnA
rnA
0.0003
0.003
%
3.9
435
ILS
ILS
ILS
ILS
mW
+125
+150
°C
°C
3.2
4.1
312
-40
-16 V to -14 V and +Vs = +14 V to +16 V, -Vs
±IB
± 8
-6.0
NOTES
iTypical resistance tolerance is ±25%.
lAfter 5 minute warmup at +25"C.
=
rnA
± 15
±15
±B
V
15
15
SYSTEM
---
3'fest conditions: +Vs
AD386TD
Min
4.B
= -15 V.
= 5 ldl, CLOAD = ]0 pF, settling measured to 1/2 LSB at output.
Measured at 1 kHz.
6Dielectric Absorption represents the magnitude of long-term setding artifacts for hold times up to 80 I-LS as a fraction of the difference in
voltages between two successive held samples.
7Specifications also apply for 10 V step.
Specifications subject to change without notice.
Specifications in bold are 100% production tested.
4RLOAD
S
ABSOLUTE MAXIMUM RATINGS l
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . 800 mW
Input Voltage 2 • • • • • • • • • • • • • • • • • • • • • • • • • • • • ± 18 V
Till Input Voltage . . . . . . . . . . . . . . . . . . . -0.5 V, + 16 V
Output Short Circuit Duration . . . . . . . . . . . . . . . .Indefinite
Storage Temperature Range . . . . . . . . . . . . -65°C to + 150°C
Operating Temperature Range
AD386B . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +8S oC
AD386T . . . . . . . . . . . . . . . . . . . . . . . -SsoC to +12SoC
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
NOTES
'Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indi~
cated in the operational section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.
2For supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
SAMPLEITRACK-HOLD AMPLIFIERS 6-13
II
Typical Perfonnance Characteristics
'00
'00
-85
90
\
'-..,.
r\.
"
......
V
V
.........
/
"
I'\.
'\
;:5RR
"-
-PSRR
""V
r--.
Vs= ::t15V
1 V p.p SINE WAVE INPUT
30
-94
1k
'00
10k
FREQUENCY - Hz
,.ok
'M
Figure 1. Differential Amplifier Common
Mode Rejection vs. Frequency
-50
3.• I-+Z
" .""':--+----+---+----1
I
3.01----+-----+---+----1
~
;!
Z.•
I-----I----+---+----I
~
~
"~
fI)
.T
1.5
1.0
r---I===::j:===*=7.=~
14 BIT
0 .•
1----+----+---+----1
____
~
______
15
3.
..
,
+25°C
~
~
3.5
t.,L
3.0
'M
lOOk
Figure 3. Differential Amplifier Power
Supply Rejection \IS. Frequency
.
..
r-.
"
'\.
[\
1681T
;PSRR
'\
2.0
-PSRR
'Y
1.5
~
40
"
BIT
0.5
ZO
10k
FREQUENCY - Hz
20 V STEP
'.0
~
r-...
lk
,
~
;:
~
+125
4.0
!E
10
+100
-c
~
Z.O
o
+75
~ 2.5
M~
OL-____- L______
0
+25
+50
TEMPERATURE -
Figure 2. Differential Amplifier Common
!'l1ode Rejection 1.'5. Temperature
(100 Hz)
4.0 , - - - - , - - - - , - - - , - - - - ,
Va= ±1SV
;.
-25
-50
STEP sIZe - y p-p
-25
+25
+50
TEMPERATURE -
+75
+100
+125
oc
Vs= ±1SV
1 V p-p SINE WAVE INPU
+2Sec
..
1k
'00
'\
10k
,M
100k
FREQUENCY - Hz
Figure 5. Differential Amplifier Settling Figure 6. TIH Power Supply Rejection
Time VS. Temperature
Frequency, Track Mode
Figure 4. Differential Amplifier Settling
Time VS. Step Size
'00
r------,-------y-------,,-------,
5 .•
4.51----+-----1----+----1
4.5
•.0
VS.
Vs=±1SV
20V STEP
.."
90
1
~ 4.0
, 80
~
~
70
~
t ..
+PSRR
-
r-...
ijl
I"
J
I"
Ys = ±15V
40
1 V pop SINE WAVE INPUT
30
J""'lill I 1111
'00
1k
'.0 I----"'"""""""""'''''''''''''''''''....''''''''''''=~
~
z.• I - - - - I - - - - t - - - + - - - - 1
1----"'"""""""""'''''''''''''''''''...."";;;,;;;;,,,,~
"""
"BIT
111
~ Z.O 1 - - - - I - - - - t - - - + - - - - 1
r\
10k
FREQUENCV - Hz
'.51----1----t---+----1
'.0 L...._ _ _'---_ _- '_ _ _-'-_ _ _...
I'-.
lOOk
'.0
'M
Figure 7. TIH Power Supply Rejection
Frequency, Hold Mode
VS.
~
;:
z
-PSRR
V
~ V . /V
;t.:-V
/'"
~m
3.•
e
I
~o~ :r':pv
1----1----+---+------1
,
;!
10
STEP SIZE - V p-p
Figure 8. TIH Acquisition Time
Size
6-14 SAMPLEITRACK-HOLD AMPLIFIERS
zo
15
1.5
-so
-21
o
+25
+50
+15
+100
+125
TEMPERATURE - ec
VS.
Step
Figure 9. TIH Acquisition Time
Temperature
VS.
AD386
'"
.
,.
~
'l,!
z0 a.
~
10
i
~
~
'"
J
00.1
60
/
'"~
~ 50
/
V
e,
~~
~
"
~
0
+
.-/
••
,
1\
>
/
S
:z:
"5
1
"'"
"
-2
0.01
..
1k
10k
100k
1M
-50
-25
FREQUENCY - Hz
Figure 10. Feedthrough
Frequency
VS.
o
+25
+50
TEMPERATURE
+75
+100
+125
-.
-so
-25
o
-·e
C~=20pF
+25
+50
TEMPERATURE
_·c
+75
"-
"
+100
+125
Figure 12. (Pedestal + Offset)
Temperature
Figure ". Droop Rate
Temperature
VS.
VS.
•
+FS
ANALOG
INPUT
-FS
r
TRACK
COMMAND
H-~~--------------------------~I
+FS
ANALOG
OUTPUT
~:E ~ETTUNG
:-:LD
:l
J__ 1
DROOP + DIELECTRIC
ABSORPTION
TI:
~E:HRO:
_
1
I
I--T
:
--1
ACQUISITION TIME
TO SPECIFIED ACCURACY
,I
1--
Figure 13. TIH Characteristic Features
TERMINOLOGY
Aperture Delay: the time required by the internal switch(es) to
Feedthrough: the fraction of input signal variation which appears
at the output in hold mode as a result of capacitive coupling.
disconnect the hold capacitor from the input, which produces an
effective delay in the sample timing.
Dielectric Absorption: the tendency of charges within a capacitor
Aperture Jitter: the uncertainty in Aperture Delay caused by
to redistribute themselves over time, resulting in "creep" in the
voltage of an open circuit capacitor after a large rapid change.
internal noise and the variation of switching thresholds with signal level. The error caused by aperture jitter depends on the
rate of change of the input and as such determines the maximum input frequency which can be sampled without error.
Acquisition Time: the time required after entering track mode for
Pedestal: a step change in the output voltage which occurs when
Settling Time: the time required in track mode for the output to
switching from track mode to hold mode.
the voltage on the hold capacitor to settle to within.a specified
fraction of full scale. This is usually specified for a full-scale
step change in output voltage.
Hold Mode Settling Time: the time required for the pedestal to
reach its final value within a specified fraction of full scale following a step change in the input voltage.
reach its final value to within a specified fraction of full scale.
Nonlinearity: the degree to which a plot of output versus input
Droop: the change in the held output voltage resulting from
deviates from the straight line defined by the end points. It is
usually specified as a percentage of full scale.
leakage currents.
SAMPLEITRACK-HOLD AMPLIFIERS 6-15
THEORY OF OPERATION
The architecture of the AD386 differs from that usually encountered in inverting Track-and-Hold (TIH) circuits. The hold
capacitor in a conventional T/H (Figure 14) is always connected
from the amplifier's output to its inverting input. In track mode
switch A is open and switch B is closed. Since the summing
junction is a virtual ground, the voltage across the capacitor follows the input. The switches change state in hold mode which
disconnects the capacitor from the input and holds the output
voltage constant. The clamping action of switch A reduces the
variations across switch B, improving feedthrough performance.
R
VOUT
T/H - - - '....--~
Figure 14. Conventional Inverting Integrator TIH
This circuit forces several tradeoffs. The hold capacitor's charging current is limited by the input resistor. Either the resistor or
the capacitor, or both, must be made small to obtain fast acquisition times. A small resistor creates greater demands on the circuit which drives the TIH, while a small capacitor leads to
increased pedestal and droop. In addition, the parallel combination of the feedback resistor and the hold capacitor acts as a low
pass filter and constrains both bandwidth and acquisition time.
The AD386 uses a four-switch fiyback architecture which removes the hold capacitor from the feedback loop during track
mode (Figure IS). Switches A and C are open in track mode
while switches Band D are closed. This maximizes bandwidth
and provides minimum acquisition time because the charging
R
current delivered to the hold capacitor is limited only by the
amplifier's output capability. The hold capacitor can be made
larger, subject to amplifier stability, since it no longer appears in
parallel with the feedback resistor. This helps to reduce droop
and pedestal. Switches A and C close in hold mode while
switches Band D open, which connects the hold capacitor to
the amplifier's inverting input.
Additional switches and capacitors, not shown in the figure,
provide first order cancellation of amplifier and switch leakage
currents, switching charge injection, and switch feedthrough.
Finally, a small amount of positive feedback is used to reduce
dielectric absorption effects.
TRACK·AND-HOLD ERROR CONTRIBUTIONS IN
SAMPLED-DATA SYSTEM
Any track-and-hold amplifier imposes performance limits on the
system in which it is used. Some of these limits can be derived
from the theory of sampled-data systems, some are intrinsic to
the TIH, and some depend on details of the system design.
Many subtle effects come into playas system resolution
increases to 14 or 16 bits, and these can contribute significant
errors. Unden~landing T/H error sources is critical to maintaining signal integrity in a high resolution data acquisition system.
FREQUENCY LIMITATIONS
Three factors set fundamental limits on system performance
when digitizing high frequency signals. These are: TIH amplifier bandwidth, aperture uncertainty, and the maximum update
rate of the TIH and AID combination. The track mode bandwidth of the T/H must be significantly greater than the bandwidth of the signals being digitized to prevent the introduction
of amplitude and phase errors. The 2 MHz small signal bandwidth of the AD386 attenuates a 35 kHz signal by 0.001 dB and
shifts its phase by 1.0 degrees.
There are two different aperture related error terms. The first is
aperture delay time, the delay between the HOLD command
and the complete opening of internal switches in the T/H. This
time amounts to a negative phase delay applied to the input signal because the T/H output can actually continue to track the
input for a brief time after the HOLD command. Aperture
delay time can be "tuned out" by advancing the assertion of
HOLD.
Aperture jitter, the random variations in aperture delay time,
causes errors which are directly related to the rate of change of
the input signal and which cannot be eliminated by circuit
adjustments.
A simple calculation provides the frequency at which aperture
jitter produces an error of 112 LSB when the input is a full-scale
sinusoid. The general result for an N -bit AID converter is
V OUT
T/H - -.....>-(l.)<~)
VI'S
Fmax = Vpp x 2N+l
x
1T
x A perture J'Itter
where VFS is the AID converter's input range and Vpp is
the peak-to-peak value of the input sinusoid. The worst case
(minimum) value of Fmax occurs when Vpp is equal to VFS '
If the TIH has an aperture jitter of 100 ps and is used with a
16-bit linear AID, the maximum input frequency is 24.3 kHz.
Figure 15. Four-Switch Inverting Flyback TIH
6--16 SAMPLEITRACK-HOLD AMPLIFIERS
AD386
The same TIH, when used with a 14-bit linear AlD, permits
the processing of signals up to 97.1 kHz before aperture jittererrors become observable. Figure 16 shows these errors as
a function of frequency, assuming a full scale input sinusoid, for
several values of aperture jitter.
0.1 r-----,----.,--::~-,
i
:
0.01
r - - - - i - 1'-_-+_-,"-_-1 1/2 LSD,a
..,
"&
1/2 LSB,.
i
NONLINEARITIES
Two phenomena directly affect the fidelity of a TIH's transfer
function and can degrade system linearity. One of these error
sources is track mode nonlinearity. It arises primarily from gain
nonlinearity in the T/H's internal amplifier(s). Mismatches in
the temperature coefficients of internal resistors may also contribute, but usually do so only for very low frequency signals.
The AD386's track mode nonlinearity is about 1/6 16-bit LSB
(Figure 17), as is the nonlinearity of the AD386's differential
amplifier.
System linearity will also be reduced if the pedestal varies nonlinearly with signal level. Pedestal nonlinearity in the AD386 is
below 8 microvolts per volt of input signal, or about liZ 16-bit
LSB .
.. 0.001 t---T--1r--::~--+-
~
0.0001
'-_...L_--'_ _.L.._-l._ _L._..J
1
10
100
APERTURE JmER - ps rms
1000
•
Figure 76. TIH Error vs. Aperture Jitter and Input
Frequency
Aperture jitter is often expressed as an rms number. "Peak-topeak" aperture jitter is usually defined as 6 times this rms value.
This comes from probability theory, where 99.7% of the measurements of a random variable will be within 3 standard deviations of the variable's average value. Aperture jitter arises from
broadband electrical noise, which is very nearly an ideal random
process with a standard deviation equal to its rms value, so multiplication by 6 gives a good approximation to the noise's peakto-peak value.
A second limit on the input frequency is imposed by the finite
time required for signal acquisition and conversion. It is possible
to reconstruct any uniformly sampled signal without loss of
information provided the sampling rate is at least twice the
bandwidth of the input signal; this is the Nyquist criterion, a
fundamental result in sampling theory. This limits input
frequency to
F
=
max
:0--------Z X (tACQ + tCONV + tAP I
where t ACQ is the TIH acquisition time, T coNV is the time required for the AID conversion, and TAP is the aperture delay of
the T/H. The last term is usually very small and can be ignored.
A system composed of a 3.6 f.LS TIH and a 10 f.LS AID can be
used successfully to digitize signals with frequency components
up to 36.76 kHz. This limit is independent of input signal
amplitude. Throughput rates and input frequency ranges for the
AD386 in combination with various AlD converters are shown
in Table I.
AID
Conversion Time
Minimum
Throughput
ADADC71
AD 1376178
AD1377
50 f.LS max
17 f.LS max
10 f.LS max
18.7 kHz
48.8 kHz
73.5 kHz
Table I. Throughput for AD386 with Various AID
Converters
INPUT VOLTAGE
Figure 17. AD386 Track Mode Nonlinearity
FEEDTHROUGH, DROOP, AND DIELECTRIC
ABSORPTION
Errors resulting from signal feedthrough and "roop must be less
than liZ LSB in order for the system's linearity to be maintained. The AD386 uses a symmetrical, compensated architecture to minimize both these effects. Feedthrough varies slightly
with input frequency from -100 dB below 1 kHz to -86 dB
above 100 kHz (Figure 10). This provides 16-bit accuracy for
full-scale inputs up to at least 5 kHz and 14-bit performance to
beyond 100 kHz.
The circuit's symmetry causes the droop rate to depend on differences in leakage currents between identical junctions under
nearly identical bias conditions. The resulting droop is less than
liZ 16-bit LSB (10 V scale) at temperatures up to 85°C and
liZ 14-bit LSB (10 V scale) over the full military temperature
range for hold times up to 100 f.LS.
Capacitors exhibit a memory phenomenon, dielectric absorption
(DA), in fast charge, long hold applications. This arises from
nonideal behavior of the dielectric material which allows charge
storage in the bulk of the dielectric. This bulk charge cannot be
removed rapidly because of the long time constant associated
with the dielectric's high resistance. A capacitor with dielectric
absorption can be modeled as an ideal capacitor in parallel with
a series R-C circuit as shown in Figure 18. When such a capacitor is used as the hold capacitor in a TIH the held voltage will
tend to creep back towards the voltage held for the previous
conversion cycle. The degree and time constant of this behavior
depends on the capacitor's dielectric material, as well as on the
charge and hold time of the circuit.
SAMPLEITRACK-HOLD AMPLIFIERS 6-77
Dielectric absorption will cause a variable "offset" if a TIH is
used to sample multiple channels with widely varying signals.
This causes an apparently nonlinear pedestal because the difference between the currently measured voltage and the previously
measured voltage determines the magnitude of the DA error.
The AD386 uses a high quality hold capacitor with low intrinsic
DA. Residual DA errors are further reduced by laser trinu!ling
a compensation network during the manufacturing process. The
trimming is performed under typical system timing conditions of
5 ,...S track, 45 ,...s hold. The post-trim dielectric absorption error
is less than 1/2 16-bit LSB for full-scale changes between samples and hold times between 10 ,...s and 100 ,...s.
Rx
COA
R
NOISE GAIN
=2
a. Track Mode
= C x D.A.
Figure 18. Capacitor Model with Dielectric Absorption
b. Hold Mode
NOISE
Noise generated in a T IH adds to the held signal and causes
variations in the output code of an AID. This noise has two
components, one which arises during track mode and another
contributed during hold mode. The rms sum of these terms
determines the noise performance of the TIH in the system.
Track noise is the noise which gets sampled when entering hold
mode. An inverting TIH architecture such as that used in the
AD386 has a noise gain of 2. This noise is low pass filtered in
the R-C network comprised of the hold capacitor and the switch
on resistance (see Figure 19a). The rms value of the track noise
is
=
lop amp noise) x Inoise gain' x IENBW,1I2
Op amp noise is the rms sum of the amplifier's broadband voltage noise and the thermal noise contributions of the input and
feedback resistors, about 17 nVtv'Hz. Other noise sources,
including amplifier current noise and switch thermal noise, are
negligible. ENBW, the equivalent noise bandwidth, is
'IT
ENBW
=
2"
Figure 19. Dominant AD386 Noise Sources
of the comparator in a successive approximation AID converter
is filtered by the converter's input resistance and the summing
junction capacitance. ENBW is calculated as before, but now
BWI is the TIH's small signal bandwidth in hold mode (4 MHz
for the AD386), and BW2 is the bandwidth of the AID's input
R-C. BW2 is about 700 kHz in the AD ADC71 and ADI376
and roughly 1.7 MHz in the AD1377 and AD1378 (assuming a
10 V span). The respective values of ENBW are 940 kHz and
1.9 MHz. The hold noise contribution of the AD386 is about 16
,...V rms when used with the AD ADC7l or AD1376 and 22 ,...V
rms when used with the AD1377 or AD1378; this noise is
30% less for a 20 V span and 40% greater for a 5 V span
because changes in the AID's input resistance cause changes
in BW2.
The total noise is the rms sum of these two results:
BWI x BW2
x BWI + BW2
where BWI is the small signal bandwidth of the T/H in track
mode (2 MHz for the AD386) and BW2 is the corner frequency
of the RSWITCH-CHOLD combination (2.7 MHz). The resulting
track noise in the AD386 is at most 46 ,... V rms.'
Noise gain is reduced to I in hold mode, and input and feedback resistor thermal noise makes no contribution (Figure 19b).
The equivalent noise bandwidth now depends on the TIH's
small signal bandwidth and the characteristics of the AID converter used in the system. This is because the signal at the input
6-18 SAMPLEITRACK-HOLD AMPLIFIERS
This yields 49 ,...V rms and 51 ,...V rms for the two cases.
Track noise dominates in both instances.
When the AD386's differential amplifier is used, its noise contribution will be band limited and sampled by the TIH. The
equivalent bandwidth for this noise is also 1.8 MHz and the
contribution to the track noise is 46 ,...V rms. The total track
noise is the rms sum of 46 ,...V and 46 fJ. V, or 65 fJ. V rms, and
the overall noise for the cpmplete AD386 used with any of the
above AID converters is at most 70 fJ. V rms.
AD386
The rms value represents one standard deviation if the noise has
a Gaussian distribution, which is usually the case for wideband
electrical noise. If a constant noise-free voltage is sampled a
large number of times, the held result will be within one standard deviation of the ideal value 32% of the time, within two
standard deviations 95% of the time, and within three standard
deviations 99.7% of the time. The entries in Table II were calculated using three standard deviations as the definition of the
peak-to-peak noise.
Span
10V
20 V
lOY
20 V
No.
Bits
rms Noise
LSBs
pop Noise
LSBs
14
14
16
16
0.11
0.06
0.45
0.23
0.66
0.36
2.7
1.4
Table II. AD386 Noise Contribution as a Function of AID
Span and Resolution
POWER SUPPLY REJECTION
Variations on the power supply lines, both dc and ac, can lead
to unwanted changes in the voltage acquired by a TIH. Power
supply variations in track mode cause the output voltage, and
hence the voltage across the hold capacitor, to vary. PSRR
decreases with increasing frequency, making well regulated, low
noise linear power supplies and proper bypassing essential in a
high resolution data acquisition system.
Equally important, but usually forgotten or omitted, is hold
PSRR. This is frequently much worse than track PSRR because
parasitic capacitances which are not significant in track mode
couple into the extremely high impedance nodes which exist in a
T/H during hold mode. This specification is essential to the system designer, as hold mode PSRR often determines the performance required from the system's power supplies. The power
supply rejection of the AD386 is specified and characterized in
both track and hold modes.
Pedestal arises from the transfer of charge from the internal
switching circuitry to the hold capacitor during the transition
from track mode to hold mode. Pedestal in some T/H circuits is
extremely sensitive to changes in the high and low levels of the
external control signal. The AD386 uses an internal + 5 V supply and logic buffers to prevent this behavior.
GROUNDING
All voltage measurements in a data acquisition system are eventually referenced to ground. Variations in the "ground" potential through the system resulting from resistive drops of power
supply and signal return currents as well as from interference
from external sources may add to the signal being digitized and
produce false results. The grounding scheme in a high resolution system cannot be left to chance and must be planned as
carefully as any other aspect of the system's design. Proper
grounding and the reduction of externally induced ground noise
are discussed at length in the following Applications section.
Applications
GROUNDING. DECOUPLING, AND LAYOUT
CONSIDERATIONS
Many data acquisition systems have two or more ground pins
which are not connected together within the device(s). These
"grounds" may be referred to as Logic Power Return, Digital
Return, Analog Ground, Analog Power Return, Signal Ground,
etc., and they must be connected together somewhere within the
system to establish a measurement reference point. Good
grounding practice dictates that these grounds be tied at a single
point, sometimes called a star or "Mecca" ground. In high resolution systems the star point is often located at the ND, with a
single, short, low impedance trace leading from there to the analog supply "common" terminal. The ideal is to use a solid analog ground plane beneath the T/H and ND as the star point.
Because circuit traces have resistance and inductance, currents
in the various ground runs can create voltage differences of hundreds of millivolts between '''ground'' in different parts of the
system. Power supply and signal ground traces should be separate to prevent summing power supply return currents with analog signal currents, which would lead to measurement errors. It
is also important to avoid closed circuit loops in system ground
connections. A loop can act as a very effective antenna, coupling
voltages created by stray magnetic fields into the measurement
system.
Each of the AD386's power supply terminals should be capacitively bypassed to the ground plane as closely as possible to the
device. This is best done using 0.0 I Io'F to 0.1 Io'F ceramic
capacitors. High frequency supply noise rejection may be further improved by placing small (4.7 n to 10 n ) carbon composition resistors in series with the supply leads. These resistors,
in combination with the ceramic capacitors, act as local low pass
filters and prevent crosstalk between system components. The
bypassing scheme should also include solid Tantalum capacitors
of I Io'F to 10 Io'F from each supply to ground in the critical
areas of the board. Proper grounding and bypassing techniques
are shown in Figure 20.
All AD386 ground pins (Pins 2, 5, 7, 9, 18, 19, and 24) should
be connected to the analog ground plane.
WARNING: Improper bypassing can result in poor settling
performance or high frequency oscillations.
The metal cover of the AD386 is internally grounded to provide
additional shielding. Do not make any external connection to
the cover.
DIFFERENTIAL AMPLIFIER
Many high resolution applications require the ability to sense
ground at the signal source. This is especially true in systems
with physical or thermal constraints that make it necessary to
locate the T/H and AID at some distance from the transducer.
Under these conditions stray electromagnetic fields may cause
"ground" at the signal source to be at a different potential from
"ground" at the AID despite the designer's best efforts. This
will give rise to measurement errors because the potential difference will appear to be added to the true signal. The AD386's
differential amplifier may be used to eliminate this type of
ground noise as shown in Figure 21.
SAMPLEITRACK-HOLD AMPLIFIERS 6-19
6
100
28
DIGITAL
DATA
OUTPUT
AD1377
*AD386 INTERNAL STAR POINT IS AT PINS 5, 7.
PINS 2, 9, 18, 19, 24 MUST ALSO BE CON·
NECTED TO ANALOG GROUND PLANE.
Figure 20. Proper Grounding and Supply Bypassing Techniques for a High Resolution Data Acquisition System
INPUT
SIGNAL
COMMON
OUTPUT
) - - - 4 > - - - - - - - SIGNAL
COMMON
COMMON MODE
GROUND NOISE
a. Without Differential Amplifier
R
R
In extremely noisy environments it may be necessary to connect
the differential amplifier to the signal source with shielded
twisted pair cable. The shield should be connected to ground at
the transducer and should be left floating at the AD386. This
shielding technique is shown in Figure 22. The cable presents a
capacitive load, and the signal source must be capable of driving
this load without ringing or oscillations. The differential amplifier's noninverting input should be connected to Pin 24 if ground
sensing is not required.
Another use of the differential amplifier is to restore signal
polarity. Like most high resolution T/H amplifiers, the TIH in
the AD386 operates in the inverting mode. The differential
amplifier may be used to provide a second inversion so that the
T/H output has the same polarity as the sensor output.
The differential amplifier also provides a low dynamic source
impedance to the T/H section. This absorbs transients produced
when the T/H switches from hold mode to track mode, providing optimal settling performance.
+
INPUT
SIGNAL - ¥ - - - - - - { 1-"''---.....COMMON
COMMON MODE
GROUND NOISE
OUTPUT
SIGNAL
COMMON
The T/H and differential amplifier have independent power supply connections. This permits a reduction in system power dissipation when the differential amplifier function is not needed.
b. With Differential Amplifier
Figure 21. Effects of Common Mode Noise
AD386
SHIELDED TWISTED PAIR
REMOTE SIGNAL--1"'''';';~',''' - --- - -- - -- - - - - - - -
REMOTE GROUND -
......-\-:~
-"-_-j.'",,,,;.,...=:22=-+......M ....-l
I
I
~
: 23
Figure 22. Remote Ground Sensing in a Noisy Environment
6-20 SAMPLEITRACK-HOLD AMPLIFIERS
AD386
~~----------~----------------------------~--+15V
~
____
~
______
~
__
~,-
________________
~
__
~
__ 15V
+5V
1.10
22
28
3.6
AD1377KD
AD386BD
ANALOG INPUT
-10V TO +10V
41----------------1
BITS
1-16
23
7 1--------------,:tIt22
21
19
20
8
18
31
CONVERT_-Il____________________________~
START
Figure 23. Basic Data Acquisition System (Some Supply Bypassing Omitted for Clarity)
_ . - - - - - -.......- - - - - - - - - - - - " t - + 1 5 V
GAIN AND OFFSET ADJUSTMENT
The usual practice in the design of data acquisition systems is to
incorporate a single system level trim for offsets and a second
for gain errors, rather than to trim each element in the signal
processing chain. Traditionally these trims involve potentiometers or fixed resistors. The trims should be designed so that
nulling static errors does not introduce new errors such as noise,
increased thermal drift, or nonlinearity.
-+-_.----t--+--------.......-+--15V
r - -.......-+-t- +5V
The offset, drift, and gain errors of the AD386 are laser
trimmed during manufacture and no external adjustment capabilities are provided. This prevents the introduction of noise
through offset adjust terminals and preserves the excellent gain
linearity and drift performance. Most AIDs provide for nulling
gain and offset errors with a range sufficient to include the
contributions of the AD386. Of course, it is also possible to
include calibration routines in the system's software to eliminate
mechanical adjustments.
HIGH RESOLUTION DATA ACQUISITION SYSTEM
The essential details of a high resolution data acquisition system
using the AD386 are shown in Figure 23. Conversion is initiated
by the falling edge of the CONVERT START pulse. This edge
drives the AID's STATUS line high. The inverter then drives
the AD386 into hold mode. STATUS remains high throughout
the conversion and returns low once the conversion is completed. This allows the AD386 to reenter track mode. The
throughputs given in Table I were calculated based upon this
circuit configuration.
One drawback of this connection becomes apparent if the system's grounding is marginal. The falling edge of CONVERTSTART resets the successive approximation register within
the ND, causing transient currents in both the analog and digital return paths. These transients vary depending on the input
signal and the prior conversion result. The same edge also drives
the T/H into hold mode. The exact timing relationship of these
two events depends upon differences in propagation delays. The
T/H's held value may be affected if the ND reset transient
begins before the T/H has fully entered hold mode. The end
result is system nonlinearity.
Figure 24. Improved Data Acquisition System
(Some Supply Bypassing Omitted for Clarity)
This problem can be avoided with the addition of a flip flop as
shown in Figure 24. The rising edge of CONVERT START
places the TIH into hold mode before the ND reset transients
begin. The falling edge of STATUS places the AD386 back
into track mode. System throughput will be reduced if a long
CONVERT START pulse is used. Throughput can be
calculated from
Throughput = T
ACQ
+
TCONV
+
Tcs
where T ACQ is the TIH acquisition time, T CONY is the time
required for the ND conversion, and Tcs is the duration of
CONVERT START. No significant T/H droop error will be
introduced provided the width of CONVERT START is small
compared with the ND's conversion time.
SAMPLEITRACK-HOLD AMPLIFIERS 6-21
•
-
VLOAD =
RLOAD
IIoFF
X V,N
(a) Single Switch
(b) T-Switch
Figure 25. Single and or' Analog Switches (Shown in OFF Position)
MULTICHANNEL SYSTEMS
The design of multiplexed data acquisition systems which maintain 14- or 16-bit signal fidelity is an extremely demanding task.
One of the first difficulties encountered is the lack of adequate
analog switches. The specified feedthrough performance of most
switches and multiplexers is seldom better than -80 dB. This is
an order of magnitude too high for a 16-bit system with its g
parts-per-million sensitivity. A "T" switch configuration can
be used to reduce feedthrough as shown in Figure 25. The
improvement in "off' isolation relative to a single switch is
substantial.
CHANNEL I IN
A few monolithic video T-switch ICs are now available and provide the necessary isolation in the dc-50 kHz frequency range.
Unfortunately, these devices have voltage limitations which
restrict their utility. It will usually be necessary to design a multiplexer using analog multiplexer and switch ICs. Figure 26
shows a simple 4-channel single-ended T -switch multiplexer and
includes a high performance buffer (see below).
The on-resistance of analog switches and multiplexers is a nonlinear function of signal voltage. This will produce severe nonlinearity in a system in which a multiplexer supplies signals
---t-="'--o
SIA
5 pF
112ADG509
DA
CHANNEL 3 IN
OUTPUT
---+-'=--(1
S3A
AI
AD
EN
A1
VO
112
VI
A
HC139
1--+-_>--- AO
B1-......- - -
"-+-----lV2
AO CHANNEL
o
o
+5
AI
'-------IV3 _
G
Figure 26. Four-Channel T-Switch Multiplexer(Power Supply Connections Not Shown)
6-22 SAMPLEITRACK-HOLD AMPLIFIERS
AD386
directly to an AD386. A high-impedance buffer between the
multiplexer and the TIH's input can solve this problem but may
introduce several others.
An op amp in the noninverting gain-of-I configuration is the
obvious candidate for a buffer. The amplifier must settle quickly
to maximize system throughput and must be extremely linear to
maintain system performance. The linearity of this configuration
depends upon the linearity of both the amplifier's open loop
gain and common-mode rejection (linear errors in these parameters result only in system gain error, but nonlinear gain and
CMRR produce system nonlinearity). Neither of these parameters is specified by most amplifier manufacturers.
A buffer may also increase system noise. Applications which
require ground- sensing will require two buffers, resulting in
40% more noise than a one-buffer system.
Finally, a buffer will add its own offset to the signal being measured. Software calibration of the error and its drift is possible
using a permanently grounded mUltiplexer channel.
The AD744 is a nearly ideal buffer for multiplexed systems.
This amplifier provides offsets as low as 250 ....V and an offset
drift of 3 ....vrc while maintaining 16-bit linearity over the
-40°C to + 85°C temperature range. Typical settling times at
room temperature are 2.3 ....5 (14 bits) and 3.5 .... s (16 bits) for
the AD744 combined with the AD386's differential amplifier.
The increase in noise at the differential amplifier's output will
be about 6 ....V rms in a one-buffer system and roughly 12 ....V
rms in a two buffer system (recall that a 16-bit LSB in a 20 volt
system is 305 ....V). The AD744 is not unity-gain stable, and
compensation is required. A 5 pF compensating capacitor is sufficient to ensure stability. The settling times listed above were
measured using a 9 pF compensation capacitor which provides
greater stability with moderate capacitive loads.
The NE5534 can also be used as a buffer to deliver 16-bit linearity. This amplifier also requires slight compensation to
achieve unity-gain stability; 10 pF is sufficient. Settling is somewhat slower than the AD744, about 5 ....s to 14 bits and 6 ....s to
16 bits, including the AD386's differential amplifier when measured at room temperature. The 5534 has lower voltage noise
and will cause only a I or 2 ....V rms increase in the total noise at
the differential amplifier's output. The NE5534 lacks the precision offset and drift performance of the AD744.
Multiplexed throughput can be improved with the proper choice
of system timing. If the new input channel is selected while the
AD386 is in Hold mode, then multiplexer, buffer, and differential amplifier settling can occur during the AID conversion. In
this case throughput is determined only by the sum of the T/H
acquisition and ND conversion times. The effects of T/H feedthrough must be considered when using this type of overlap in
system timing.
There is another solution to many of the problems of multiplexed systems when the speed of channel switching is not critical: relays. Relays should be selected for good shielding, low
thermal EMF, and low on-resistance. The only significant drawback of this approach, other than switching speed and size, is
power dissipation. In all other respects relays offer a nearperfect solution to the problems of high resolution system design
discussed above.
DYNAMIC PERFORMANCE
Dynamic characteristics such as signal-to-noise ratio (SNR) and
total harmonic distortion (THD) are important in many signal
processing applications. SNR and THD are affected by both
the T/H and ND. The errors contributed by the T/H are generally dependent upon the input signal frequency, while those
contributed by the ND converter usually are not. The dynamic
performance of a TIH-ND pair is characterized using Fast
Fourier Transform (FFT) techniques.
Figures 27-31 show the results of several 1024-point FFTs
which demonstrate the exceptional distortion and noise performance of the AD386 when combined with the AD1377. These
FFTs were obtained using a circuit similar to that of Figure 24.
The input signal was processed by both the differential amplifier
and T/H sections of the AD386 and was sampled at an
83.333 kHz rate. The AD 1377's clock was adjusted to yield an
8.0 .... s conversion time, which provided 4.0 ....s for the AD386 to
acquire each new sample. The vertical scale for these figures is
based on a full-scale input referenced as 0 dB. The system was
configured for a 10 volt span.
Figures 27 and 28 illustrate the system's low frequency noise
and distortion performance. The input frequency is 1.546 kHz.
When the input is -0.3 dB, nearly full scale, the largest harmonic component is -102.8 dB (Figure 27). Total harmonic
distortion, the rms sum of the second through fifth harmonics,
is -99.9 dB. The signal to noise ratio is 89.9 dB. The ultimate
noise floor can be determined using a lower level input. Reducing the input level about 20 dB, as in Figure 28, decreases the
-20
~ -30
I
~
ifio
-40
-50
-60
~ -70
Q.
~
= '546
= 83333
= -0.3
= -90.2
= -99.9
FUNDAMENTAL
SAMPLE RATE
SIGNAL
(dB)
NOISE
(dB)
(dB)
THO
-'0
=
=
2f (dB)
-'06.6
3f (dB)
-'02.8
7.8
.: (dB)t
-80
-90
-'f
-100
-'10
-'20
I."
III
1
44
86
129
lI.tIII, I'jj~
171
214
257
.1.1
299
342
l ••~ ~jJli ....lh ...1
384
427
469
512
FREQUENCY (x 81.3802 Hz)
10 V SPAN
Figure 27.
FUNDAMENTAL
SAMPLE RATE
SIGNAL
(dB)
NOISE
(dB)
(dB)
THO
-'0
-20
f8
I
>
-30
-40
55
-50
f5
-60
o
1546
= 83333
= -'9.'
= -91.9
= -83.1
a: -70
~
~
2f (dB)
3f (dB)
-80
~ -90
4' (dB)
-100
-110
.IIL
-120
1
44
86
l,h .. I~ lhll.!... Uk. bLj"
129
171
214
257
= -'07.2
= - '07.3
= -11'.8
I
dlro.l .
299
.t. ~l. ~JII~,.,.I.u, ~••
342
384
427
469
512
FREQUENCY (x 81.3802 Hz)
10V SPAN
Figure 28.
SAMPLEITRACK-HOLD AMPLIFIERS 6-23
II
•
noise floor by 1. 8 dB to - 91. 9 dB. This corresponds to a total
AD386 noise contribution of about 45 ,....V rms. The FFT noise
floor would improve about 2 dB with the .system configured for
a 20 volt span because the effect of noise contributed by the
AD386 is reduced as a result of the increased LSB size.
order harmonics; the second through fifth harmonics have been
excluded from the noise floor calculations, but higher harmonics
are considered to be "noise". These harmonics arise from the
AD386's aperture jitter. The additional noise is consistent with
an rms jitter of 40 ps.
System performance just beyond the high end of the audio band
is shown in Figure 29. Here the input is a -Q.3 dB sinusoid at
21.24 kHz. The only significant harmonic component, the second harmonic, is -91.9 dB with respect to the fundamental,
and THD is -91.1 dB. The noise floor is 0.5 dB greater than
in Figure 27. The additional noise is contributed by higher-
In Figures 30 and 31, -0.3 dB and -20.1 dB inpUtS at 40.61
kHz show system performance near the Nyquist frequency.
Even at this high frequency a full-scale input produces THD of
only -84.6 dB, dominated by the second harmonic at -85.1 dB
(Figure 31). In Figure 31 the harmonics have been eliminated
by reducing the input level by a factor of 10.
I
-10
'8
-30
~ -40
(ij -50
I
~-60
.. -so
~ -so
I
21240
83333
-0.3
-88.7
-91.1
I
41 (dBI = -102.1I
I
I
I
-100
-120
I
=
=
=
=
=
~ :~:l ~:: ~:~-
~ -70
-',0
I
FUNDAMENTAL
SAMPLE RATE
SIGNAL
(dBI
NOISE
(dBI
(dBI
THD
-20
II
I
I
k.IU IbUhlJ
I•. L.II~ U~I IdlJ~ , ILI",I.LII.",I ••,I,IJ
86 129 171 214 257 299 342 384 427
FREQUENCY I x 81,3802 Hz)
10V SPAN
44
I
I
1hI,(j
WJ dull
1
I
I
III~
469
512
Figure 29.
1
-10
III
"tI
I
SIGNAL
NOISE
THO
I
-60
a: -90
I
-100
-120
(dBI = -0.3
(dBI = -88.7
(dBI = -84.6
I
I--
I
III
L"I. l.lli.
III
. ~ -30
I--
~ -40
~
w
I
1
44
I.
86
129
171
214
~:I
I
~
III
I
299
342
384
427 469
Figure 30.
6-24 SAMPLEITRACK-HOLD AMPLIFIERS
I
I
SIGNAL
{dBI = -20.1-
:~:l ~ :::~:~-
J~dB;j= '~'~89
31 {dBI = -108.4
2
1:- 41 {dB'L
I
-110
~~J"I. ,I.
-120
512
I
NOISE
THO
-100
I
10V SPAN
I
I
-7
-90
l t1II.ILUlidlill.JI.IL
257
-
-70
uj -80
a:
I
I
I
~~~~~~~W ~ ~;~;-
-50
0-60
I
FREQUENCY ()( 81.3802 Hz)
-20
c-
2f (~BI = I -85.\
31 (dBI = -102.3
41 (dBI = -99.2
-80
-110
= 83333
SAMPLE RATE
~ -70
~
-10
-30
~ -50
Q
I
FUNDAMENTAL = 40609
~ -40
a:
I
-20
,
44
iUJUlI
86 129
!.!I,L,
..I.
171
214
I
I
~II_, '" 1'11.0111.
257
I
299
342
FREQUENCY I x 81.3802 Hz!
10V SPAN
Figure 31.
384
i~.IJ ~.L
427
469
512
High Resolution
Track-and-Hold Amplifier
AD389 I
r-IIANALOG
WDEVICES
FEATURES
Companion to High Resolution AID Converters
Fast Acquisition Time: 2.5,..5 to ±O.003%
Low Droop Rate: O.1,..vt,..s
Aperture Jitter: 400ps
Internal Hold Capacitor
Unity Gain Inverter
Low Power Dissipation: 300mW
PRODUCT DESCRIPTION
The AD389 is a high accuracy, adjustment free track-and-hold
amplifier designed for high resolution data acquisition applications.
The fast acquisition time (2.5f.Ls to ±0.OO3%) and low aperture
jitter (400ps) make it suitable for use with fast AID converters
to digitize signals up to 40kHz.
The AD389 is complete with an internal hold capacitor and it
incorporates a compensation network which minimizes the sample
to hold charge offset.
Typical applications for the AD389 include sampled daia systems,
peak hold functions, strobed measurement systems and simultaneous sampling converter systems. When used with autozero
and autocalibration techniques, this TIH combined with a high
linearity AID will offer 14-bit performance over the converter's
full no-missing-code temperature range.
The device is available in two versions: the "K" specified for
operation over the 0 to + 70°C commercial temperature range
and the "B" specified over the full industrial temperature range,
- 25°C to + 8S"C. High reliability processing is available; contact
factory for information.
AD389 FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The AD389 is the ideal companion track-and-hold amplifier
to 14-bit accurate AID converters.
2. The AD389 provides separate analog and digital grounds,
thus improving the device's immunity to ground and switching
transients.
3. The droop rate is only O.lf.LV/f.Ls so that it may be used in
slower high resolution systems without the loss of accuracy.
4. The fast acquisition time and low aperture make it suitable
for high speed data acquisition systems and digital audio recording.
S. The AD389 TIH amplifier is ideal for applications requiring
wide_dynamic range.
6. Clever circuit design eliminates any measurable thermal tail
(see Figures lla and lib).
PIN CONFIGURATION
DIGITAL INPUT
ORDERING GUIDE
-15V
ANALOG INPUT
Model
Temperature
Range
Package
Option'
AD389KD
AD389BD
Oto +70°C
- 25°C to + 85°C
DH-14A
DH-14A
SUMMING PT
+15V
N/C
·See Section 14 for package outline infonnalion.
SAMPLEffRACK-HOLD AMPLIFIERS 6--25
•
SPECIFICAT ION S(typical
@
+ 25"1: and nominal power supply voltage of ± 15V unless othelWise noted)
Model
AD389KD
AD389BD
Units
ANALOG INPUT
Voltage Range
Overvoltage, no damage
Impedance
± 10 min
± 15 max
3000
*
*
*
V
V
DIGITAL INPUT (TTL Compatible)
TrackMode,Logic "I"
Hold Mode, Logic "0"
Logic" 1" Current
Logic "0" Current
2t05.5V
OtoO.8V
20 (max)
-360(max)
*
*
*
*
V
V
ANALOG OUTPUT
Voltage
Current
Short Circuit Current
Impedance
± 10 min
3
20
1
*
*
*
*
V
mA
rnA
-1.00
±0.01 (± 0.02 max)
VN
MHz
MHz
n
,.A
,..A
n
DC ACCURACY/STABILITY
Gain
Gain Error
Gain Nonlineariry( ~ lOV Output Track)
Gain Temperature Coefficient
Offset Voltage
Output Offset@ T min, T max (Track)
1 (5 max)
± 3 max, adjustable to zero
±6
*
*
*
*
*
*
TRACK MODE DYNAMICS
Frequency Response
Small Signal ( - 3dB)
Full Power Bandwidth
Slew Rate
Noise in Track Mode, de to 1.0MHz
1.5
0.5
30
200
*
*
*
*
V/,..s
30
0.4
±2(4max)
±4
*
*
*
±6
ns
ns
mV
mV
200
0.5 (2 max)
1.0 (3 max)
*
*
*
mV
,..s
,..s
HOLD MODE DYNAMICS
Droop Rate
Droop Rate at T max
Feedthrough Rejection (IOV p-p@20kHz)
0.1 (I max)
lOmax
86 (74 min)
*
40 max
,..V/,..s
,..V/,..s
*
dB
HOLD-TO-TRACK DYNAMICS
Acquisition Time to ±0.01%of20V
Acquisition Time to ±0.003%of20V
1.5 (3 max)
2.5 (5 max)
*
*
,..s
,..s
TRACK-TO-HOLD SWITCHING
Aperture Time
Aperture Uncertainty (Jitter)
Offset Step (Pedestal)
Pedestal with Temperature
Switching Transient
Amplitude
Settling to ImV
SettIingto O.3mV
±O.OOI
%
%
ppml"C
mV
mV
,..Vrms
POWER REQUIREMENTS
Nominal Voltages for Rated Performance
Operating Range I
Power Supply Rejection
Supply Current
+Vs
-Vs
Power Dissipation
±15(±3%)
± 11 to ± 18
100
*
*
*
V
V
15 (20 max)
-4(IOmax)
300 (500 max)
*
*
*
mA
mA
mW
TEMPERATURE RANGE
Operating
Storage
Oto +70
-55 to + 125
-25to +85
*
°C
°C
THERMAL RESISTANCE
Junction to Air, alA (free air)
Junction to Case, ale
60
20
*
*
NOTES
'Operating to derated performance with IV .NI 2k
+15V HTL
LOW
VOLTAGE
SIGNAL
ANALOG
AD582
GND
-15V
Figure 2. Sample and Hold with A
= (1 + R FIR ,)
Figure 3C. High Threshold Logic Connection
SAMPLEITRACK-HOLD AMPLIFIERS 6-33
DEFINITION OF TERMS
Figure 4 illusrrates various dynamic characteristics of the
ADS82.
,.
", ,
'r-.
'4
r-.
HOLD/SAMPLE DELAY
,
, ,
;;;A-rLS;:~ JITTER
......
......
200nt /
APERTURE TIM E
t'....
r'-..
I. . . . "
I........
f',
HOLD
2
SAMPLE
Figure 4. Pictorial Showing Various SIH Characteristics
Aperture Delay is the time required after the "hold" command
until the switch is Culiy open and produces a deiay in the effective sample timing. Figure S is a plot giving the maximum frequency at which the ADS82 can sample an input with a given
accuracy (lower curve).
Aperture Jitter is the uncertainty in Aperture Time. The
Aperture Time can be eliminated by advancing the sampleto-hold command 200ns with respect to the input signal. The
Aperture Jitter now determines the maximum sampling frequency (upper curve of Figure S).
Acquisition Time is the time required by the device to reach its
final value within a given error band after the sample command
has been given. This includes switch delay time, slewing time
and settling time for a given output voltage change.
Droop is the change in the output voltage from the "held"
value as a result of device leakage. In the ADS82, droop can
be in either the positive or negative direction. Droop rate may
be calculated from droop current using the following formula:
t:N (Volts/sec) = I(pA)
l:::.T
CH(pF)
(See also Figure 6.)
Sample-to-Hold Offset is an output shift or st~p caused by
charge injection into the hold capacitor as the device is
switched from sample to hold. The charge transfer generates
a sample-to-hold offset where:
Charge (pC)
()
'M
Figure 5. Maximum Frequency of Input Signal for W1LSB
Sampling Accuracy
'00.000
I
10,000
ACQUISITION TIME
~I
10V STEP TO 0.0'" ~
'.000
~
'00
!"--..
.........
'0
,.0
o. , I0.0
eROOPRATE
mvlSEC
l'--.
FEEOTHRU-m
,OY INPUT
,
r--
r-V
K
r-
r--....
r--...
vI-" r---.
SAMPLElHOLD
OFFSET-mV
'""N
I
O.01pF
'.OOOpF
'OOpF
r--....
O.1pF
,.000F
CH VALUE
Figure 6. Sample-and-Hold Performance as a Function of
Hold capacitance
v"""
+'06
+86
I--
+86
V
IL V
..... V+2
CH pF
•
..... 1--
V-
This offset also has a dc component as shown in Figure 6.
.,
6
'0
I'"
,0'
,
'0
DROOP CURRENT - pA
,0'
Figure 7. Droop Current VB. Temperature
6-34 SAMPLEITRACK-HOLD AMPLIFIERS
I'.
'00k
1k
10k
SINUSOIDAL INPUT FREQUENCV - Hz
+'26
Feedthrough is that component of the output which follows
the input signal after the switch is open. As a percentage of the
input, feed through is determined as the ratio of the feedthrough capacitance to the hold capacitance (Cp/CH).
SIH Offset (V) =
'0
SAMPLE
LOGIC INPUT
,00
r-.
'0'
1IIIIIIII ANALOG
WDEVICES
Sample-and-Hold Amplifier
AD583
I
FEATURES
High Sample-to-Hold Current Retia: 106
High SI_ Rate: 5V11J1
High Bandwidth: 2MHz
Low Aperture Time: 50nl
Low Charge Transfer: 10pC
DTL/TTL Compatible
May Be Used al Gated Op Amp
AD583 PIN CONFIGURATION
SAMPLE/HOLD
IN-
CONTROL
IN+
GND
N.C.
HOLD CAP.
v-
N.C.
v+
OUT
PRODUCTION DESCRIPTION
The ADS83 is a monolithic sample-and hold circuit consisting
of a high performance operational amplifier in series with a
low leakage analog switch and unity gain amplifier. An external hold capacitor, connected to the switch output, completes
the sample-and-hold or track-and-hold function.
With the analog switch closed, the ADS83 functions like a standard op amp; any feedback network may be connected around
the device to control gain and frequency response. With the
switch open the capacitor holds the output at its previous level.
The ADS83 may also be used as a versatile operational amplifier with a gated output for applications such as analog switches,
peak holding circuits, etc.
CASE
PRODUCT HIGHLIGHTS
1. Sample-and-hold operation is obtained with the addition of
one external capacitor.
2. Low charge transfer (lOpe) and high sample-to-hold current
ratio insure accurate tracking.
3. Any gain or frequency response is available using standard
op amp feedback networks.
4. High slew rate and low aperture time permit sampling of
rapidly changing signals.
S. Output, gated through a low leakage analog switch, also
makes the ADS83 useful for applications such as analog
switches, peak holding circuits, etc.
SAMPLEITRACK-HOLD AMPLIFIERS 6-35
II
SPECIFICATIONS (typical @+25°C, hold capacitor of 1000pF and ±15V dc Uriless otherwise specified)
MODEL
ADS83Kl)
OPEN LOOP GAIN
RL =2kn, Tmin to T max
2Sk min (SOk typ)
OUTPUT VOLT AGE SWING
RL = 2kn, T min to T max
±10V min
OUTPUT CURRENT
±10mAmin
OUTPUT RESISTANCE
OFFSET VOLT AGE
Tmin tOTmax
6mV max (3mV typ)
8mV max (4mV typ)
BIAS CURRENT
Tmin to Tmax
OFFSET CURRENT
Tmin to Tmax
INPUT RESISTANCE
200nA max (SOnA typ)
400nAmax
COMMON MODE RANGE
±10V min
COMMON MODE REJECTION
Tmin to Tmax
GAIN BANDWIDTH PRODUCT
74dB min (90dB typ)
SLEW RATE
Av = +1, RL = 2kn, CL = SOpF,
Vout = ±10V p-p
SV/!l-s
RISE TIME
Av = +1, RL = 2kn, CL = SOpF,
Vout = 400mV p-p
lOOns
OVERSHOOT
Av = +1, RL = 2kn, CL = SOpF,
Vout = 400m V p-p
20%
SOnAmax (lOnA typ)
100nAmax
SMn min (lOMn typ)
2MHz
DIGITAL INPUT CURRENT
Yin = 0, Tmin to Tmax
Yin = +S.OV, Tmin to Tmax
0.8mA max (Logic "Sample")
20!l-A max (Logic "Hold")
DIGITAL INPUT VOLTAGE
Low T min to T max
High T min to T max
0.8V max
2.0Vmin
ACQUISITION TIME
Av = +1, RL =2kn, CL
to 0.1% offinal value:
to 0.01% of final value:
=SOpF
APERTURE TIME
SOns
APERTURE JITTER
Sns
DRIFT CURRENT!
Tmin toT max
SOpA max (SpA typ)
1.0nA max (O.OSnA typ)
CHARGE TRANSFER
20pC max (lOpC typ)
SUPPLY CURRENT
S.OmA max (2.SmA typ)
POWER SUPPLY RE]ECTION 1
74dB min (90dB typ)
OPERATING TEMP
STORAGE TEMP
PACKAGE OPTION 3
D-14
AD583KD
NOTES
1 Voltage on hold is zero.
• Sample mode only.
• See Section 14 for package outline information.
Specifications subject to change without notice.
6-36 SAMPLEITRACK-HOLD AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Voltage between V+ and
V-Terminals
Differential Input Voltage
Digital Voltage (Pin 14)
Output Current
Internal Power Dissipation
40V
±30V
+8V, -lSV
Short Circuit Protected
·30mW (Derate power
dissipation by 4.3mW/oC
above +150o C ambient
temperature)
High Speed, Precision
Sample-and-Hold Amplifier
11IIIIIIII ANALOG
WDEVICES
AD585
FEATURES
Acquisition Time to ±0.01% max
Low Droop Rate: 1.0mV/ms max
Sample/Hold Offset Step: 3mV max
Aperture Jitter: 0.5ns
Extended Temperature Range: - 55·C to
Internal Hold Capacitor
Internal Application Resistors
± 12V or ± 15V Operation
Available in Surface Mount
I
AD585 FUNCTIONAL BLOCK DIAGRAMS
3.0~s
DIP
LOGIC
HOLD
REF HOLD
+ Vs
AI".
HI'S
Your
GND
CH
+ 125·C
APPLICATIONS
Data Acquisition Systems
Data Distribution Systems
Analog Delay & Storage
Peak Amplitude Measurements
PRODUCT DESCRIPTION
-VIN
+VIN
NULL
-Vs NULL
LCC/PLCC PACKAGE
The AD585 is a complete monolithic sample-and-hold circuit
consisting of a high performance operational amplifier in series
with an ultralow leakage analog switch and a FET input integrating
amplifier. An internal holding capacitor and matched applications
resistors have been provided for high precision and applications
flexibility.
The performance of the AD585 makes it ideal for high speed
10- and 12-bit data acquisition systems, where fast acquisition
time, low sample-to-hold offset, and low droop are critical. The
AD585 can acquire a signal to ±O.OI% in 311-s maximum, and
then hold that signal with a maximum sample-to-hold offset of
3mV and less than ImV/ms droop, using the on-chip hold
capacitor. If lower droop is required, it is possible to add a
larger external hold capacitor.
The high-speed analog switch used in the AD585 exhibits aperture
jitter of O.Sns, enabling the device to sample full-scale (20V
peak-to-peak) signals at frequencies up to 78kHz with 12-bit
precision.
The AD585 can be used with any user-defined feedback network
to provide any desired gain in the sample mode. On-chip precision
thin-film resistors can be used to provide gains of + I, - I, or
+ 2. Output impedance in the hold mode is sufficiently low to
maintain an accurate output signal even when driving the dynamic
load presented by a successive-approximation A/D converter.
However, the output is protected against damage from accidental
short circuits.
The control signal for the HOLD command can be either
active high or active low. The differential HOLD signal is compatible with all logic families, if a suitable reference level is
provided. An on-chip TTL reference level is provided for TTL
compatibility.
The AD585 is available in three performance grades. The JP
grade is specified for the 0 to + 70·C commercial temperature
range and packaged in a 20-pin PLCC. The AQ grade is specified
for the - 25°C to + 85°C industrial temperature range and is
packaged in a 14-pin cerdip. The SQ and SE grades are specified
for the - SS·C to + 125°C military temperature range and are
packaged in a 14-pin cerdip and 20-pin LCC.
Ne "" NO CONNECT
PRODUCT HIGHLIGHTS
1. The fast acquisition time (3I1-s) and low aperture jitter (O.5ns)
make it the first choice for very high speed data acquisition
systems.
2. The droop rate is only 1.0mV/ms so that it may be used in
slower high accuracy systems without the loss of accuracy.
3. The low charge transfer of the analog switch keeps sample-tohold offset below 3mV with the on-chip lOOpF hold capacitor,
eliminating the trade-off between acquisition time and S/H
offset required with other SHAs.
4. The AD585 has internal pretrimmed application resistors for
applications versatility.
5. The AD585 is complete with an internal hold capacitor for
ease of use. Capacitance can be added externally to reduce
the droop rate when long hold times and high accuracy are
required.
6. The AD58S is recommended for use with 10- and 12-bit
successive-approximation AID converters such as AD573,
AD574A, AD674A, AD7572 and AD7672.
SAMPLEITRACK-HOLD AMPLIFIERS 6--37
II
SPECIFICATIONS
(typical @ +2SOC and Vs
and
= :t:12V or :t:15V,
eH = Internal, A = + 1, HOLD active unless otherwise specified)
SAMPLBlHOLDCHARACTERISTICS
Acquisition Time, 10V Step toO.OI%
20VSteptoO.01%
Aperture Time, 20V pop Input,
HOLDOV
Aperture Jitter, 20V pop Input,
HOLDOV
Settling Time, 20V pop Input,
HOLDOV, toO.OI%
Droop Rate
Droop Rate T min to T max
Charge Transfer
Sample-to-Hold Offset
Feedthrough
20V p'p, 10kHz Input
1YP
Mal<
MiD
1YP
Mal<
1YP
MiD
Mal<
Ullils
....
3
3
3
5
5
5
I/oS
35
3S
35
ns
0.5
0.5
0.5
ns
0.5
0.5
0.5
1
Doubles Every IO"C
0.3
3
-3
1
Doubles Every IO"C
0.3
-3
3
0.5
TRANSFER CHARACTERISTICS'
Open Loop Gain
VOUT = 20V Pop, RL = 2k
Application Resistor Mismatch
AD585S
AD585A
AD585J
MiD
Model
0.3
3
mV
0.5
C.3
0.3
pC
mV
200,000
200,000
0.3
mVlms
Doubles Every IO"C
-3
0.5
200,000
....
1
VN
%
Common Mode Rejection
VCM= ;:IOV
Small Signal Gain Bandwidth
VOUT = loomVp-p
Full Power Bandwidth
VOUT = 20Vpop
Slew Rate
VOUT = 20Vp-p
Output Resistance (Sample Mode)
lOUT = ;:IOmA
Output Short Circuit Current
Output Short Circuit Duration
2.0
2.0
2.0
MHz
160
160
160
kHz
10
10
10
Bias Current
Bias Current T min to T
Input Capacitance, f = IMHz
Input Resistance, Sample or Hold
20V pop Input, A = + I
5
2
6
2
3
2
5
10
10
10"
10"
10"
1.2
1.4
1.6
1.2
1.4
1.6
POWER SUPPLY CHARACTERISTICS
Operating Voltage Range
Supply Current, R I . = oc
Power Supply Rejection, Sample Mode
+5, -IO.S
6
70
TEMPERATURE RANGE
Specified Performance
0
;: IS
10
+70
;: IS
10
+5, -IO.S
6
70
+85
ADS85AQ
+5, -IO.S
6
-55
I Maximum
AD5S5SQ
AD5S5SE
AD5S5JP
input signal is the minimum supply minus a headroom voltage
of 2.5V.
SpecifICations subject to change without notice.
6-38 SAMPLEITRACK-HOLD AMPLIFIERS
pF
1.6
SpeciflCations shown in boldface are tested OD aU production units at final
electrical test. Results from those tests are used. to calculate outgoing quality
levels. AU min and max specifICations are guaranteed, although only those
shown in boldface are tested on all production units.
V
0.7
50
V
I/oA
;: IS
10
V
mA
dB
+125
NOTES
lNot tested at - SS"C.
JSee Section 14 for packase outline information.
nA
nA
n
70
-25
mV
mV
V
O.S
SO
O.S
SO
Logic Input Current (Either Input)
2
3
2
50'
2.0
2.0
2.0
1.4
1.2
n
mA
50
Indefmite
20
10
TmintoTmax
PACKAGE OPTIONS'
Cerdip(Q-14)
LCC(E-20A)
PLCC(P-20A)
50
Indefmite
5
mill(
Vi....
0.05
O.OS
0.05
50
Indefinite
ANALOG INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage, T min to T max
DIGITAL INPUT CHARACTERISTICS
TTL Reference Output
Logic Input High Voltage
T min to Tmax
Logic Input Low Voltage
dB
80
80
80
"C
AD585
ABSOLUTE MAXIMUM RATINGS
Supplies (+ Vs , - Vs )
Logic Inputs
Analog Inputs . . . .
RIN, RFB Pins . . . .
Storage Temperature
Lead Temperature (Soldering)
Output Short Circuit to Ground
TTL Logic Reference Shon
Circuit to Ground
±18V
±Vs
. ±Vs
. ±Vs
-65°C to + 150°C
300°C
Indefinite
Indefinite
cttANG£IN
SAMPlE-To.lfOLO
OfFSET
Figure 3. Large Signal Response, Sample Mode
....v
-1 ... V
.
~
!
t
Figure 1. Sample-to-Hold Offset vs. Logic Level
(HOLD Active)
.
-
~-
I
I
I
--i--
I
Figure 4. Sample-to-Hold Settling Time (HOLD Active)
;.
500
,
~
z
l=
0
~a
:;1
50
/
TTl. LOGIC REF
HOLD
'nF
'OOpF
10kU
+Vs
NULL
R,.
10nf
HOLD CAPACITANCE
Figure 2. Acquisition Time vs. Hold Capacitance
(10V Step to 0.01%)
Figure 5. DIP Pin Configuration
SiH COMMAND
SlHCOMMAND
SIGNAL
SM
INPUT
OUTPUT
I
I
I
I
I
I
CH
I
J
I
.l..OPTlONAl
.....,
~O~~Al
TCA~TOR
SIGNAL
INPUT
I
L~~~~J
'NPUT
Figure 6. Connection Diagram,
Gain = + 1, HOLD Active
Figure 7. Connection Diagram,
Gain = + 2, HOLD Active
Figure 8. Connection Diagram,
Gain = - 1, HOLD Active
SAMPLEITRACK-HOLD AMPLIFIERS 6-39
SAMPLED DATA SYSTEMS
In sampled data systems there are a number of limiting factors
in digitizing high frequency signals accurately. Figure 9 shows
pictorially the sample-and-hold errors that are the limiting factors.
In the following discussions of error sources the errors will be
divided into the following groups: 1. Sample-to-Hold Transition,
2. Hold Mode and 3. Hold-to-Sample Transition.
The error due to aperture jitter is easily calculated as shown
below. The error calculation takes into account the desired
accuracy corresponding to the resolution of the N-bit AID
converter.
2-(N+1)
Fmax =
(Aperture Jitter)
'If
For an application with a 10-bit AID converter with a 10V full
scale to a 1I2LSB error maximum.
HOLD/SAMPLE DELAY
Fmax =
2-(10+1)
-=----9
(0.5 x 10-
'If
Fmax
I
I
)
= 310.8kHz.
For an application with a 12-bit AID converter with a IOV full
scale to a 1/2LSB error maximum:
I
I
APERTURE I
UNCERTAINTY I
2-(12+1)
L_____ J
Fmax =
-=----9
'If
~l~~~~-2H1&]~D~--------j;~Ui--...
LOGIC INPUT
(0.5 x 10-
)
Fmax = 77.7kHz.
Figure II shows the entire range of errors induced by aperture
jitter with respect to the input signal frequency.
Figure 9. Pictorial Showing Various SIH Characterstics
SAMPLE-TO-HOLD TRANSITION
The aperture delay time is the time required for the sample-andhold amplifier to switch from sample to hold. Since this is effectively a constant then it may be tuned out. If however, the
aperture delay tilrie is not accounted for then errors of the magnitude as shown in Figure 10 will result.
'"
kvfUJ.JJ
lIZ.ITt<
BBITS
'"
lVl'ULlSCALE
11281TCft
/
"BITS"
..A
lOVrULLllE
112 iIT 111
11 BITS
••;;:-
,%
'12," ~
. .ITS
V
.,%
".rr:~
112 BtT (0
" .....
/
112811'
) .1,1
- iRTUi' Till"T ii
'O*Hz
.
0:'
"..,.
112 BIT
/
"at
V.~DIiLAY
CoIlSnsl
112 ItT~
I~~\.
rI'
,
DO
lk
1011
SIGNAL FMEQUENCY _ Hz
.
''''
"Ok
Figure 10. Aperture Delay Error vs. Frequency
To eliminate the aperture delay as an error source the sample-tohold command may be advanced with respect to the input
signal.
Once the aperture delay time has been eliminated as an error
source then the aperture jitter which is the variation in aperture
delay time from sample-ta-sample remains. The aperture jitter is
a true error source and must be considered. The aperture jitter
is a result of noise within the switching network which modulates
the phase of the hold command and is manifested in the variations
in the value of the analog input that has been held. The aperture
error which results from this jitter is directly related to the
dV/dT of the analog input.
Sample-to-hold offset is caused by the transfer of charge to the
holding capacitor via the gate capacitance of the switch when
switching into hold. Since the gate capacitance couples the
switch-control voltage applied to the gate on to the hold capacitor,
the resulting sample-to-hold offset is a function of the logic
level.
The logic inputs were designed for application flexibility and,
therefore, a wide range of logic thresholds. This was achieved
by using a differential input stage for HOLD and HOLD.
Figure I shows the change in the sample-to-hold offset voltage
based upon an independently programmed reference voltage.
Since the input stage is a differential configuration, the offset
voltage is a function of the control voltage range around the
programmed threshold voltage.
The sample-to-hold offset can be reduced by adding capacitance
to the internal 100pF capacitor and by using HOLD instead of
HOLD. This may be easily accomplished by adding an external
capacitor between Pins 7 and 8. The sample-to-hold offset is
then governed by the relationship:
Charge (pC)
S/H Offset (V) = CH Total (pF)
For the AD585 in particular it becomes:
0.3 pC
S/H Offset (V) = lOOpF + (CEXT)
6-40 SAMPLEITRACK-HOLD AMPLIFIERS
'OM"
Figure 11. Aperture Jitter Error vs. Frequency
AD585
The addition of an external hold capacitor also affects the acquisition time of the ADS8S. The change in acquisition time
with respect to the CEXT is shown graphically in Figure 2.
HOLD MODE
In the hold mode there are two important specifications that
must be considered; feedthrough and the droop rate. Feedthrough
errors appear as an attenuated version of the input at the output
while in the hold mode. Hold-Mode feedthrough varies with
frequency, increasing at higher frequencies. Feedthrough is an
important specification when a sample and hold follows an
analog multiplexer that switches among many different
channels.
Hold-mode droop rate is the change in output voltage per uuit
of time while in the hold mode. Hold mode droop originates as
leakage from the hold capacitor, of which the major leakage
current contributors are switch leakage current and bias current.
The rate of voltage change on the capacitor dV/dT is the ratio
of the total leakage current II. to the hold capacitance CH •
Droop Rate =
dVOUT
-aT (Volts/Sec)
IL(pA)
CH(pF)
HOLD-TO-SAMPLE TRANSITION
The Nyquist theorem states that a band-limited signal which is
sampled at a rate at least twice the maximum signal frequency
can be reconstructed without loss of information. This means
that a sampled data system must sample, convert and acquire
the next point at a rate at least twice the signal frequency. Thus
the maximum input frequency is equal to
f
1
MAX-2(TACQ + T CONV + TAP)
Where T ACQ is the acquisition time of the sample-to-hold
amplifier, TAP is the maximum aperture time (small enough to
be ignored) and T CONY is the conversion time of the AID
converter.
DATA ACQUISITION SYSTEMS
The fast acquisition time of the AD585 when used with a high
speed AID converter allows accurate digitization of high frequency
signals and high throughput rates in multichannel data acquisition
systems. The ADS85 can be used with a number of different
AID converters to achieve high throughput rates. Figures 12
and 13 show the use of an AD585 with the AD578 and
AD574A.
--.o-_ _..-_ _ _ _ _ _---..._+1SV
For the AD585 in particular;
lOOpA
_
Droop Rate - IOOpF + (C EXT )
Additionally the leakage current doubles for every 10°C increase
in temperature above 25°C; therefore, the hold-mode droop rate
characteristic will also double in the same fashion. The hold-mode
droop rate can be traded-off with acquisition time to provide the
best combination of droop error and acquisition time. The tradeoff
is easily accomplished by varying the value of C EXT '
Since a sample and hold is used typically in combination with
an AID converter, then the total droop in the output voltage has
to be less than 1I2LSB during the period of a conversion. The
maximum allowable signal change on the input of an AID converter
is:
!:J.V max
ANALOG
IN..."
OT01OV
CONVERT C>_ _ _
COMMAND
~======='-__.J
Figure 12. AID Conversion System, 117.6kHz Throughput
58. 8kHz max Signal Input
= Full Scale Voltage
2(N+l)
Once the maximum !:J. V is determined then the conversion time
of the AID converter (TCONV) is required to calculate the maximum
allowable dV/dT.
dV max
-d-t-
=
!:J.V max
TCONV
ANALOG
'NPUT
---crr-
.
dV max as sown
h
by th
'
. .IS
The maXImum
e prevIous
equation
OT010V
the limit not only at 25°C but at the maximum expected operating
temperature range. Therefore, over the operating temperature
range the following criteria must be met (TOPERATION - 25°C)
= !:J.T.
(1!.1"C)
dV 25°C
--ar-
x
2 1ii'C
dV max
$--ar
CONVERT
START
o _ _ _~=======~J
Figure 13. 12 Bit AID Conversion System, 26.3kHz
Throughput Rate, 13. 1kHz max Signal Input
SAMPLEffRACK-HOLD AMPLIFIERS 6-41
I
LOGIC INPUT
The sample-and-hold logic control was designed for versatile
logic interfacing. The HOLD and HOLD inputs may be used
with both low and high level CMOS, TTL and ECL logic systems.
Logic threshold programmability was achieved by using a differential amplifier as the input stage for the digital inputs. A predictable logic threshold may be programmed by referencing
either HOLD or HOLD to the appropriate threshold voltage.
For example, if the internal IAV reference is applied to HOLD
an input signal to HOLD between + l.8V and + Vs will place
the AD585 in the hold mode. The AD585 will go into the sample
mode for this case when the input is between - Vs and + l.OV.
The range of references which may be applied is from ( - Vs
+4V) to (+ Vs -3V).
OPTIONAL CAPACITOR SELECTION
If an additional capacitor is going to be used in conjunction
with the internal lOOpF capacitor it must have a low dielectric
absorption. Dielectric absorption is just that; it is the charge
absorbed into the dielectric that is not immediately added to or
removed from the capacitor when rapidly charged or discharged.
The capacitor with dielectric absorption is modeled in
Figure 14.
GROUNDING
Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
"grounds" are usually referred to as the Logic Power Return,
Analog Common (Analog Power Return), and Analog Signal
Ground. These grounds must be tied together at one point,
usually at the system power-supply ground. Ideally, a single
solid ground would be desirable. However, since current flows
through the ground wires and etch stripes of the circuit cards,
and since these paths have resistance and inductance, hundreds
of millivolts can be generated between the system ground point
and the ground pin of the AD585. Separate ground returns
should be provided to minimize the current flow in the path
from sensitive points to the system ground point. In this way
supply currents and logic-gate return currents are not summed
into the same return path as analog signals where they would
cause measurement errors.
~~
Rx
CPA = (D.A.) X (C)
Figure 14. Capacitor Model with Dielectric Absorption
If the capacitor is charged slowly, COA will eventually charge to
the same value as C. But unfortunately, good dielectrics have
very high resistances, so while COA may be small, Rx is large
and the time constant Rx COA typically runs into the millisecond
range. In fast-charge, fast-discharge situations the effect of dielectric absorption resembles "memory". In a data acquisition system
where many channels with widely varying data are being sampled
the effect is to have an ever changing offset which appears as a
very nonlinear sample-to-hold offset since the difference between
the voltage being measured and the voltage previously measured
determines the fraction by which the dielectric absorption figure
is multiplied. It is impossible to readily correct for this error
source. The only solution is to use a capacitor with dielectric
absorption less than the maximum tolerable error. Capacitor
types such as polystyrene, polypropylene or Teflon are
recommended.
6-42 SAMPLE/TRACK-HOLD AMPLIFIERS
Figure 15. Basic Grounding Practice
11IIIIIIII ANALOG
WDEVICES
FEATURES
Four Matched Sample-and-Hold Amplifiers
Independent Inputs, Outputs and Control Pins
500ns Hold Mode Settling
1fLS Maximum Acquisition Time to 0.01%
Low Droop Rate: 0.01fLV/,..S
Internal Hold Capacitors
200ps Maximum Aperture Jitter
Low Power Dissipation: 360 mW
0.3" Skinny DIP Package
Four-Channel
Sample-and-Hold Amplifier
AD684 I
AD684 FUNCTIONAL BLOCK DIAGRAM
AD684
PRODUCT DESCRIPTION
The AD684 is a monolithic quad sample-and-hold amplifier
(SHA). It features four complete sampling channels, each controlled by an independent hold command. Each SHA is complete with an internal hold capacitor. The high accuracy SHA
channels are self-contained and require no external components
or adjustments. The AD684 is manufactured on a BiMOS
process which provides a merger of high performance bipolar
circuitry and low power CMOS logic.
The AD684 is ideal for high performance, multichannel data
acquisition systems. Each SHA channel can acquire a signal in
less than IfLS and retain the held value with a droop rate of less
than O.OI ....V/ ....s. Excellent linearity and ac performance make
the AD684 an ideal front end for high speed 12- and 14-bit
ADCs.
PRODUCT HIGHLIGHTS
1. Fast acquisition time (I .... s) and low aperture jiner (200ps)
make the AD684 the best choice for multiple channel data
acquisition systems.
2. Monolithic construction insures excellent interchannel
matching in terms of timing and accuracy, as well as high
reliability.
3. Independent inputs, outputs and sample-and-hold controls
allow user flexibility in system architecture.
4. Low droop (O.OI ....V/ ....s) and internally compensated hold
mode error results in superior system accuracy.
5. The AD684's fast settling time and low output impedance
make it ideal for driving high speed analog to digital converters such as the AD578, AD674, AD7572 and the AD7672.
The AD684 has a self-correcting architecture that minimizes
hold mode errors and insures accuracy over temperature. Each
channel of the AD684 is capable of sourcing SmA and incorporates output short circuit protection.
The AD684 is specified for three temperature ranges. The J
grade device is specified for operation from 0 to 70°C, the A
grade from -40°C to +8SoC and the S grade from -SsoC to
+ 125°C.
SAMPLEITRACK-HOLD AMPLIFIERS 6-43
•
SPECIFICATIONS (typical
@ +25°C, Vee
=+l12V, VEE =-12V, unless otherwise specified)
AD684J
Parameter
Min
SAMPLING CHARACTERISTICS
Acquisition Time (Tmin to T ~.)
10V Step to 0.01%
IOV Step to 0.1%
Small Signal Bandwidth
Full Power Bandwidth
HOLD CHARACTERISTICS
Effective ApertUre Delay
ApertUre Jitter
Hold Settling Time (to ImV)
Droop Rate (Tmin to T _)'
Feedthrough
(VIN =±5V, 100kHz)
ACCURACY CHARACTERISTICS (Tmin to T ",..)'
Hold Mode Offset
Hold Mode Offset Drift
Track Mode Offset
Nonlinearity
Gain Error
INTERCHANNEL CHARACTERISTICS
Interchannel Isolation
(VIN=±SV, 100kHz)
Interchannel Apenure Offset
Interchannel Offset
OUTPUT CHARACTERISTICS
Output Drive Current2
(Tmin to T-J
Output Resistance, dc
Total Output Noise
(dcto 5MHz)
Sampled de Uncertainty
Hold Mode Noise
(de to SMHz)
Shon Circuit Current'
Source
Sink
INPUT CHARACTERISTICS (Tmin to T ....)
Input Voltage Range
Bias Current
Input Impedance
Input Capacitance
DIGITAL CHARACTERISTICS (T..,;n to T_)
Input Voltage Low
Input Voltage High
Input Current (VIN = 5V)
POWER SUPPLY CHARACTERISTICS
(T..... toT-J
Operating Voltage Range (Vee, VEE)
Supply Current
+ PSRR (+12V, ±IO%)
-PSRR (-12V, ±IO%)
Power Consumption
TEMPERATURE RANGE
Specified Petformance
-30
AD684A
Tn>
Max
0.75
0.5
1.0
0.6
Min
80
Max
0.75
0.5
1.0
0.6
0.75
0.5
1.0
0.6
4
I
I
-20
100
250
0.01
-10
200
500
1
-30
-4
-20
100
250
0.01
-10
200
500
5
-30
-90
+3
10
50
±0.002
±0.03
200
±0.003
±O.OS
86
150
0.1
300
1.2
0.3
+S
0.5
-7
80
-4
jLS
"jLS
MHz
MHz
-10
200
500
7
ns
ps
ns
p.V/p.s
-90
+3
10
SO
±0.002
+0.03
200
±0.003
±O.OS
86
ISO
0.1
300
1.2
0.3
+S
0.5
-S
-20
100
250
0.01
Units
-7
-4
dB
+3
10
80
mV
;.;.V,toC
mV
%FS
%FS
SO
±0.003
+0.03
200
±0.005
±O.OS
86
ISO
0.1
300
1.2
mV
0.3
+S
0.5
rnA
0
-S
dB
ps
ISO
85
ISO
85
ISO
85
.,.Vrms
.,.Vrms
125
125
125
.,.Vrms
20
10
20
10
20
10
rnA
rnA
100
50
2
+5
200
-5
100
50
2
0.8
2.0
0
Max
4
-5
6S
60
Tn>
I
-S
±10.8
Min
4
-90
-7
AD684S
Tn>
+5
200
20
±12
IS
70
65
360
±l3.2
22
±1O.8
65
60
530
+70
100
50
2
0.8
2.0
2
-5
-40
+5
200
MO
pF
0.8
2.0
2
20
±12
IS
70
65
360
±l3.2
22
±10.8
6S
60
530
+85
-55
V
nA
2
20
±12
IS
70
65
360
±l3.2
24
V
V
p.A
V
rnA
580
dB
dB
mW
+125
"C
NOTE
'Specified and tested over an input range of ±5V.
2Maximum current the AD684 can source (or sink). Testing guarantees that the accuracy of the held sipal remains within 2.5mV of its initial value.
'The output is protected for a shan circuit to common, +Vcc and -VEl!.
Specifications shown in boIdfaee are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.
All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
6-44 SAMPLEfTRACK-HOLD AMPLIFIERS
AD684
ABSOLUTE MAXIMUM RATINGS*
Spec
Vee
VEE
Control Inputs
Analog Inputs
Output Short Circuit to
Ground, Vee, or VEE
Max Junction
Temperature
Storage
Lead Temperature
(lOsec max)
Power Dissipation
PIN CONFIGURATION
With
Respect to
Min
Max
Unit
Common
Common
Common
Common
-0.3
-15
-0.5
-12
+15
+0.3
+7
+12
V
V
V
V
OUT1
StHl
OUT2
StH2
AD684
TOP VIEW
INot to Scale)
Indefinite
oun
StH3
-65
+175
+150
·C
·C
+300
640
·C
mW
COMMON
7
OUT4
NC = NO CONNECT
·Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
eJ I
~~OEVJCE
ORDERING GUIDE
Model
Temperature Range
AD684JQ
AD684AQ
AD684SQ
oto +70·C
-40°C to +8S oC
- S50C to + 125°C
Package
Options*
Q-16
Q-16
Q-16
·See Section 14 for package outline information.
SAMPLEITRACK-HOLD AMPLIFIERS 6-45
Typical Characteristics
••
100
10.0
7.
I
v~
i'
6.
90
1'--1'-ill
I
.....
~ .0
'"
1.•
~
50
~
v~
ill
~ 3.
i
o. 1
1.!.
~
i
2.
70
/
/
I
~
I 40
/
0.01
/
10
so
1
10
100
lk
FREQUENCY - Hz
10k
..
,. ,
o
1000
1
,.
0.001
'"
lOOk
1M
FREQUENCY - Hz
-1.
150
..
,
i
1
I
~-20
50
I
.........
~
; -50
1-25
50
75
100
TEMPERATURE - ·C
125
150
20
,.
200
~
I -15
25
Droop Rate vs. Temperature, V/N = OV
Power Supply Rejection Ratio
vs. Frequency
Interchannel Isolation vs. Frequency
•
/
-100
/
/
/
/
,.
./
V
V
//
/'
-150
-3.
10.
10k
lOOk
1M
-1.
-5
•
INPUT VOLTAGE - V
FREQUENCY - Hl
Effective Aperture Delay vs. Frequency
16
14
,.
.. '"
v
.:!:10
-50
-25
0
25
500
I
--
:11
:12
:13
SUPPLY VOLTAGE - V
:14
"5
Supply Current vs. Supply Voltage
SAMPLEITRACK-HOLD AMPLIFIERS
o
•
75
100
125
Supply Current vs. Temperature
!i!
>=
z
50
TEMPERATURE - "C
750
250
4
-75
1000
,.
12
•
Bias Current vs. Input Voltage
20
~6
,.
-200
1k
V
~
V
./
/
,.
INPUT STEP - V
Acquisition Time (to 0.01%)
vs. Input Step Size
150
AD684
DEFINITIONS OF SPECIFICATIONS
Acquisition Time - The length of time that the SHA must
remain in the sample mode in order to acquire a full scale input
step to a given level of accuracy.
Small Signal Bandwidth - The frequency at which the held
output amplitude is 3dB below the input amplitude, under an
input condition of a 100mV p-p sine wave.
Full Power Bandwidth - The frequency at which the held output amplitude is 3dB below the input amplitude, under an input
condition of a IOV p-p sine wave.
Effective Aperture Delay - The difference between the switch
delay and the analog delay of the SHA channel. A negative
number indicates that the analog portion of the overall delay is
greater than the switch portion. This effective delay represents
the point in time, relative to the hold command, that the input
signal will be sampled.
Tracking Mode Offset - The difference between the input and
output signals when the SHA is in the track mode.
Nonlinearity - The deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of -SV and +SV.
Gain Error - Deviation from a gain of + I on the transfer
function of input vs. held output.
Interchannel Isolation - The level of crosstalk between adjacent channels while in the sample (track) mode with a full scale
100kHz input signal.
Interchannel Aperture Offset - The variation in aperture time
between the four channels for a simultaneous hold command.
Differential Offset - The difference in hold mode offset
between the four SHA channels.
Aperture Jitter - The variations in aperture delay for successive samples. Aperture jitter puts an upper limit on the maximum frequency that can be accurately sampled.
Power Supply Rejection Ratio - A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Hold Settling Time - The time required for the output to settle to within a specified level of accuracy of its final held value
after the hold command has been given.
Sampled dc Uncertainty - The internal rms SHA noise that is
sampled onto the hold capacitor.
Droop Rate - The drift in output voltage while in the hold
mode.
Feedthrough - The attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Hold Mode Offset - The difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of OV.
Hold Mode Noise - The rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Total Output Noise - The total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms summation of the sampled dc uncertainty and the hold mode noise.
Output Drive Current - The maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.SmV.
FUNCTIONAL DESCRIPTION
The AD684 is a complete quad sample-and hold amplifier that
provides high speed sampling to 12-bit accuracy in less than
I ...s.
The AD684 is completely self-contained, including on-chip hold
capacitors, and requires no external components or adjustments
to perform the sampling function. Each SHA channel can operate independently, having its own input, output and sample/hold
command. Both inputs and outputs are treated as single ended
signals, referred to common.
The AD684 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit corrects for internal errors after the hold command has been given,
by compensating for amplifier gain and offset errors, and charge
injection errors. Due to the nature of the design, the SHA output in the sample mode is not intended to provide an accurate
representation of the input. However, in hold mode, the internal
circuitry is reconfigured to produce an accurately held version of
the input signal. To the right is a block diagram of the AD684.
AD684
Functional Block Diagram
SAMPLEITRACK-HOLD AMPLIFIERS
~7
II
DYNAMUCPERFORMANCE
The AD684 is compatible with l2-bit A-to-D conveners in
terms of both accuracy and sPeed. The fast acquisition time, fast
hold settling time and good output drive capability allow the
AD684 to.·be used with high speed, high resolution A-to-D conveners like the AD674 and AD7672. The AD684's fast acquisition time provides high throughput rates for multichannel data
acquisition systems. Typically, the sample and hold can acquire
a IOV step in less than 750ns. Figure 1 shows the settling accuracy as a function of acquisition time.
..
t;
~
VIN• VOLTS
-5
0.08
-2
-1
-2
HOLD MODE OFFSET
-3
GAIN ERROR
t
---00-=':-:';-::':;-:':-:':-::':-
:O-T-------....-~-~---..;;-:.:-:.:,:...
0.04
-5
a~
\
NONLINEARJTV
-6
~ 0.02
J
+5
0.06
~
~
-3
-1
::>
z
-4
J
Figure 3. Hold Mode Offset, Gain Error and Nonlinearity
\..
250
500
750
ACQUISmON TIME - ns
1000
Figure 1. VOUT Settling vs. Acquisition Time
The hold settling determines the required time, after the hold
command is given, for the output to settle to its fmal specified
accuracy. The typical settling behavior of the AD684 is shown
in Figure 2. The settling time of the AD684 is sufficiently fast
to allow the SHA, in most cases, to directly drive an A-to-D
converter without the need for an added "stan conven" delay.
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accomplished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD71l). Only a single
adjustment of the offset is necessary for the four SHA channels
as a result of the excellent matching among them. The offset
will change less than O.5mV over the specified temperature
range.
SUPPLY DECOUPLING AND GROUNDING
CONSIDERATIONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from excessive high frequency noise (ripple). The supply connection to the
AD684 should also be capable of delivering transient currents to
the device. To achieve the specified accuracy and dynamic performance, decoupling capacitors must be placed directly at both
the positive and negative supply pins to common. Ceramic type
O.IILF capacitors should be connected from Vee and VEE to
common.
ANALOG
P.S.
DIGITAL
P.8.
Figure 2. Typical AD684 Hold Mode
HOLD MODE OFFSET
The dc accuracy of the AD684 is determined primarily by the
hold mode offset. The hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. The hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. The nominal hold
mode offset is specified for a OV input condition. Over the input
range of -SV to +SV, the AD684 is also characterized for an
effective gain error and nonlinearity of the held value, as shown
in Figure 3. As indicated by the AD684 specifications, the hold
mode offset is very well matched between channels and stable
over temperature.
6--48 SAMPLEITRACK-HOLD AMPLIFIERS
DIGITAL
DATA
OUTPUT
~------------~~~D
Figure 4. Basic Grounding and Decoupling Diagram
AD684
The AD684 does not provide separate analog and digital ground
leads as' is the case with most A-to-D converters. The common
pin is the single ground terminal for the device. It is the reference point for the sampled input voltage and the held output
voltage and also the digital ground return path. The common
pin should be connected to the reference (analog) ground of the
A-to-D converter with a separate ground lead. Since the analog
and digital grounds in the 684 are connected internally, the
common pin should also be connected to the digital ground,
which is usually tied to analog common at the A-to-D converter.
Figure 4 illustrates the recommended decoupling and grounding
practice.
A graph showing the magnitude of the jitter induced error vs.
frequency of the input signal is given in Figure 6.
The accuracy in sampling high frequency signals is also constrained by the distortion and noise created by the sample-andhold. The level of distortion increases with frequency and
reduces the "effective number of bits" of the conversion.
'"
lf2 BIT (a..
/
0.1%
NOISE CHARACTERISTICS
Designers of data conversion circuits must also consider the
effect of noise sources on the accuracy for the data acquisition
system. A sample-and-hold amplifier that precedes the A-to-D
converter introduces some noise and represents another source
of uncertainty in the conversion process. The noise from the
AD684 is specified as the total output noise, which includes
both the sampled wideband noise of the SHA in addition to the
band limited output noise. The total output noise is the rms
sum 'of the sampled dc uncertainty and the hold mode noise. A
plot of the total output noise vs. the equivalent input bandwidth
of the converter being used is given in Figure 5.
"'
8 BITS
11281TCa-
'-
10 BITS
1/2 BIT ~
12 BITS
/
.~
/
o
1/2 BIT (1'1
14 BITS
.....
L
APERTURE JITTER TYptCAL AT 0.2n5
I
./
"
II
1M
10k
tOOk
FREQUENCY - Hz
Figure 6. Error Magnitude vs. Frequency
-60
300
/
-6.
-70
/
'""I -75
....
~
,,'"
V
-8•
V
-85
o
"
-90 / '
100
10k
tOOk
FREQUENCY - Hz
1M
10M
Figure 5. RMS Noise vs. Input Bandwidth of ADC
V
lk
10k
FREQUENCY - Hz
tOOk
1M
Figure 7. Total Harmonic Distortion vs. Frequency
9Or--r-r-rT'r-r--r-rr-r--r-,-r-n
DRIVING THE ANALOG INPUTS
For best performance, it is important to drive the AD684 analog
inputs from a low impedance signal source. This enhances the
sampling accuracy by minimizing the analog and digital
crosstalk. Signals which come from higher impedance sources
(e.g., over 5k ohms) will have a relatively higher level of
crosstalk. For applications where signals have high source
impedance, an operational amplifier buffer in front of the
AD684 is required. The AD713 (precision quad BiFET op amp)
is recommended for these applications.
HIGH FREQUENCY SAMPLING
Aperture jitter and distortion are the primary factors which limit
frequency domain performance of a sample-and-hold amplifier.
Aperture jitter modulates the phase of the hold command and
produces an effective noise on the sampled analog input. The
magnitude of the jitter induced noise is directly related to the
frequency of the input signal.
8.~~-+-+++--t-~~+--+~-+~
!lI
6.~~-+-+++--t-~~+--+~-+~
I •• ~~-+-+++--t-~~+--+~-+~
~z"~-+--+-+++--+---+--H+--+-l-+-H
iii
3.~-+--+-+++--+---+--H+--+-l-+-H
2O~-+--+-+++--+---+--H+--+-l-+-H
FREQUENCY - Hz
Figure 8. Signall(Noise and Distortion) vs. Frequency
Measurements of Figures 7 and 8 were made using a 14-bit
A-to-D converter with VIN = lOY p-p and a sample frequency of
lOOKSPS.
SAMPLEITRACK-HOLD AMPLIFIERS 6-49
•
DATA ACQUISITION APPLICATIONS
Figure 9 shows a typical data acquisition circuit using the
AD684 and the high speed 12-bit A-to-D converter, the
AD7672. Four input signals are simultaneously sampled by the
AD684 as the HOLD command is given. One of the four held
outputs is selected by the ADG201, quad CMOS switch, and
buffered by the AD71l. The ADS88 provides the reference voltage with switches A-8 and C-D Selecting a -SV to +SV or 0 .to
+SV input range.
+,2V
SHA
CONTROL
IS/H)
CHANNEL
r- SELECT ~
+12V
OUT1
INPUTS
CH'
IN'
IN2
CH3
IN3
S2
D3
siii3
CH4
1N4
OUT4
S/H4
C4~
O.,,,,F
S,
S/H2
OUT3
~O.''''F
ADG201A
D2
+5V
+12V
C3
S/H'
OUT2
CH2
VDD
D'
53
D4
Vo.
~.....= + - - - t - - - - - . . . - - - - - - t A I N '
·54
COMMON
AD684
AlN2
R2
A41N
GND
SENSE
-IN
BAL
ADJ
AD588
,on
AD7672
1C2
IC3
A40UT
SENSE
A40UT
FORCE
V'"
NOTES
'ANALOG INPUT RANGE SELECT.
'C9 AND C,O REQUIRED FOR :SV RANGE.
CONNECT C TO D IA TO B OPEN)
FOR TO +5V RANGE
OR A TO B IC TO DOPEN)
FOR -SV TO. +5V RANGE.
°
-v.
- ' 2 V - -..............,
C7
C8
'O"'F~O.''''F
-'2V--........."
C'7
C'8
'O",FYO.,,,,F
Figure 9. Data Acquisition System Using the AD684 and the AD7672
6-50 SAMPLEITRACK-HOLD AMPLIFIERS
1IIIIIIII ANALOG
WDEVICES
Low Cost 16-Bit Accurate
Sample-and-Hold Amplifier
ADl154 I
FEATURES
Low Nonlinearity: :!::7.6 ppm max (t/2 LSB @ 16-Bit
Accuracyl
Fast Acquisition Time to :!::0.00076%: 3.5 Jl.S
Low Droop Rate: 0.02 Jl.V/Jl.s
Aperture Jitter: 150 ps
:!:: 10 V Input Range
Hold Mode Feedthrough Rejection of -106 dB
14-Pin Metal DIP
Gain of +1 V/V
Low Cost
APPLICATIONS
Medical and Analytical Instrumentation
Automatic Test Equipment
Data Acquisition for Signal Processing
Simultaneous Sample-and-Hold
Peak Measurement Detection
Event Analysis
GENERAL DESCRIPTION
The ADllS4 is a high accuracy, low cost sample-and-hold
amplifier (SHA) designed to be used in high resolution data
acquisition systems. It is complete with internal hold capacitor
and proprietary capacitor trimmed compensation circuitry. Its
accuracy (0.00076% of full scale range) and dynamic performance allow it to be used with high speed 16-bit AID converters.
The ADllS4's low price enables users to upgrade the front end
perfortnance of 14-bit systems without increasing system cost.
Its gain accuracy and droop rate in "hold" mode also allow accurate conversion by slower 16-bit AID converters having conversion times of up to 7.6 ms.
ADllS4 FUNCTIONAL BLOCK DIAGRAM
AGNDI
DACOMP
OFFSET
ADJ
SHA
CONTROL
PRODUCT HIGHLIGHTS
1. Fast acquisition and low jitter make it the right choice for
high speed, high accuracy data acquisition.
2. Its low droop rate (0.02 ....V/ ....s) allows it to be used in. slower
systems without noticeable performance degradation.
3. The ADllS4 is ideal for systems requiring wide dynamic
range.
4. Low price reduces overall system cost.
S. Unity gain buffer architecture allows ease of use.
The ADllS4 is a hybrid noninverting sample-and-hold amplifier
(SHA) with a gain of + I VN. It can be utilized in most inverting SHA applications by inverting the digital data. The ADllS4
is packaged in a compact 14-pin metal DIP.
Typical applications for the ADllS4 include data acquisition
systems, strobed measurement systems, peak hold circuits and
simultaneous sample-and-hold functions. The ADllS4 is available in two grades, both operating over the - 2SoC to + 8SoC
temperature range. The "A" grade is specified for IS-bit accurate systems, while the "B" grade offers superior performance
for true 16-bit applications.
SAMPLEITRACK-HOLD AMPLIFIERS 6-51
II
SPECIFICATIONS (typical
@ 25°C and nominal power supply of ±15V unless otherwise noted)
Model
ADl154AW
ADl154BW
Dimensions are shown in inches and (mm).
±IO min
±Vs
1012
10
*
*
*
*
DIGITAL INPUT (TTL COMPATIBLE)
Sample Mode Logic "I"
Hold Mode Logic "0"
Logic .. I" Current
Logic "0" Current
2.0 min
O.S max
I
3
*
*
*
*
ANALOG OUTPUT
Voltage (RLOAo 2:2 ill)
Short Circuit Current
Impedance
±IO min
20
0.1
*
*
*
V
rnA
n@' 1kHz
+1
±0.OO3 (±0.0l max)
±O.I (±I max)
*
*
*
VN
±0.0015
±0.0015 max
±0.3
±3 (±20 max)
±0.6
±0.5
*
±0.OOO76 max
%
%
*
*
*
*
ppmlmV
mV
mV
,..VfClmV
120
10
40
*
*
*
*
MHz
kHz
V/,..s
SO
ISO
±S
*
n.
*
DC ACCURACYISTABILITY
Gain
Gain Error
Gain Temperature Coefficient
Nonlinea...-ity
Sample Mode'
Hold Mode
Per mV of Offset Adjust (Hold Mode)
Offset Error (Adjustable to Zero)
Offset Error @ T min> T rna';
Offset Tempco per mV of Offset Adjust
SAMPLE MODE DYNAMICS
Small Signal Bandwidth ( - 3 dB)
FuJI Power Bandwidth
Slew Rate
Noise (dc to I MHz)
OUTLINE DIMENSIONS
Units
ANALOG INPUT
Voltage Range
Overvoltage (No Damage)
Input Impedance
Input Capacitance
I
SAMPLE-TO-HOLD SWITCHING
Aperture Delay
Aperture Uncertainty (Jitter)
Offset Step (Pedestal)
Switching Transient
Amplitude
Setding to ±0.003%
Setding to ±0.OOO76%
Dielectric Absorption Error (Uncompensated)
±75
0.4
I
0.003
HOLD MODE DYNAMICS
Droop Rate
Droop Rate @' T max
Feedthrougb Rejection (20 V Pop @' 10 kHz)
HOLD-TO-TRACK SWITCHING
Acquisition Time to ±0.OOO76% of 20 V3
V
V
n
14·LEAD METAL PLATFORM DIP
pF
%
ppml"C
~~-i
B
1.0.29& (7.49.!.1
,..Vrms
ps
I-- •.
mV
..L
*
*
mV
1....1
j
*
%
0.05 (0.1 max)
I
-106 (-96 max)
0.02 (0.05 max)
*
*
,..V/,..s
,..V/,..s
dB
5 (S max)
3.5 (5 max)
,..s
±15 (±3%)
20
*
*
V
10
10
300
*
*
*
mA
mA
mW
TEMPERATURE RANGE
Rated Performance
Storage
-25 to +S5
-40 to +125
"C
PACKAGE
14-Pin DIP
*
*
*
POWER REQUIREMENTS
Nominal Voltage for Rated Performance (Vs)
Power Supply Rejection
Supply Current
+Vs
-Vs
Power Dissipation
*
*
1
--I
--.l •.•
0.180
,...
,...
500 (12.'1
BOTTOM VIEW
-ED
--
BO
_ , 12.031
ED
@@@@@@@
~
~:r"1
----r
STANDOff DETAIL
PIN DESIGNATIONS
,..VN
·C
NOTE
IThe AD1l54 was designed specifically for l&-bit accurate samplelhold applications (tailored for hold mode performance),
but it may be used as a tnck·and·hold amplifier with IS~bit accurate tracking performance.
2Error at + 2SOC adjusted to zero.
'Tested with 5 kO load.
'Specification same as AD1I54AW
Specifications sub~ct to change without notice.
6-52 SAMPLEITRACK·HOLD AMPLIFIERS
PIN
1
2
3
4
DESCRIPTION
SHACDNTRDL
NO CONNECTION
NO CONNECTION
DIGITAL GROUND
PIN
8
11
+15V
NO CONNECTION
6
7
ANALOG GROUND
OFFSET ADJUST
12
13
14
ANA GND/DA COMP
SHA INPUT
•
9
I.
DESCRIPTIDN
SHAOUTPUT
OFFSET ADJUST
NO CONNECTION
-15V
ADl154
I .•
v
V
TO
I
!
-'ov
V
1)(10- 1
TO +10Y
i'
{
~
L
I
~
I
V
i
i ..,
1)(10-2
1
\
\
\
\
.001
/
\
V
-25 -15
V
IL
-5
+5
+15 +25 +35 +45 +55 +65 +75 +85 +90 +100
TEMPERATURE - "C
ACQUISIOON nME - "..
Figure 1. Acquisition Time vs. Final Error Band for 20 Volt
Step
Figure 2. Droop Rate vs. Temperature
Figure 3. Hold-to-Sample Acquisition Time
Figure 4. Sample-to-Hold Settling Time
+15
-15
SkU
AIN
Figure 5. Input Feedthrough
0---------.. . . ----\
Figure 6. Acquisition Time Test Circuit
SAMPLEITRACK-HOLD AMPLIFIERS 6-53
I
TERMINOLOGY
Accura~
is the peak deviation of the output from a straight line
through the endpoints ·of the transfer function. It is expressed as
a percentage of the full scale output range. Note that this
parameter is measured in hold mode because the actual voltage
to be converted is the voltage present at the output of the device
during the hold mode.
Acquisition Time is the time required by the device to reach its
final value within a given error band after the sample/track command has been given assuming that the input amplifier has settled. This includes switch delay time, slewing time and settling
time for a given output voltage change.
Aperture Time is the time required after the hold command for
the switch to open fully. The sample is, in effect, delayed by
this interval, and the hold command would have to be advanced
by this amount for precise timing.
Aperture Jitter is the range of variation in the aperture time. If
the aperture time is "tuned out" by advancing the hold command a suitable amount, this spec establishes the ultimate timing error, hence, the maximum sampling frequency to a given
resolution.
Charge Transfer (or offset step or pedestal) is the charge transferred to the storage capacitor when switching to the hold mode.
Droop Rate is the rate of change in output voltage over time
while in the hold mode. The droop rate will determine how
long a signal can be accurately held before it changes more than
I LSB.
Feedthrough is the fraction of the input signal variation or ac
input waveform that appears at the output in hold. It is caused
by stray capacitive coupling from the input to the storage capacitor, principally across the open switch.
INVERTING VS. NONINVERnNG ARCHITECTURE
The AD11S4 has a gain of +1 VN. Many SIH amplifiers use an
inverting architecture and hence have again of ~ 1 VN. The
AD1154, because of its noninverting architecture, does not have
an externally accessible summing point. This pin is found on
most inverting SlHs and is typically not used. In applications
where the summing junction is not connected, the AD1154 can
be used as a direct hardware replacement by tying Pin 12 to
ground, but the output is of opposite polarity.
GROUNDING CONSIDERATIONS
The AD1154 is a true 16-bit performance sample/hold amplifier.
In order to insure proper operation of the device, great care
must be taken in managing the ground tracks. It is recommended.that Pins 4,6 and 12 ofthe AD1154 be tied together
directly outside of the package. This point should then be tied
to the analog ground of the AID converter, as shown in Figure
8. This track should be as short and wide as possible to minimize voltage drops. Also note from the figure that any other
analog grounds in the signal path should be joined to the AID
converter analog ground.
ANALOG
POWER SUPPLY
-15V
10p,F
OIGrrAL
POWER SUPPLY
+15V
+5V
10"F
Small Signal Bandwidth is the maximum analog signal frequency
that can be tracked before the gain is reduced by 3 dB. This
assumes the signal amplitude is small enough so as not to be
slew rate limited.
Switching Transient Settling Time is the time required for the
device to stabilize in the hold mode to within specified limits of
its fmal value after the hold mode signiu has been given.
Figure 8: Basic Grounding and Power· Supply Bypassing
Practioe
DIELECTRIC ABSORPTION COMPENSATION
The hold capacitor used in the AD1154 is a high quality ceramic
chip capacitor. This capacitor's dielectric absorption characteristics are typically better than high quality film capacitors. In
addition, the AD1l54 provides a means for compensating for
the dielectric absorption of the caJ)acitodf better performance is
required. If dielectric absorption compensation is not used, Pin
12 should be tied to ground. Please refer to the Section titled
"DISCUSSION OF DIELECfRIC ABSORPTION" for more
detailed information.
POWER SUPPLY BYPASSING
Figure 7. TIH Characteristics
6-54 SAMPLEITRACK-HOLD AMPLIFIERS
The AD 11 54 utilizes high speed amplifiers in its design. These
amplifiers require quiet Power supplies thar.are free from
spikes. For maximum performance it is recommended that both
power supplies be bypassed with 0.1 j.LF ceramic capacitors in
parallel with 10 j.LF tantalum "capacitors located as close to the
device as possible (see Figure 8).
ADl154
DISCUSSION OF DffiLECTRIC ABSORPTION
The hold capacitor of the AD1154 was chosen for its low dielectric absorption (D.A.) characteristics. D.A. is directly affected
by the sampleJhold mode switching durations and input levels.
The AD1154 provides the user with a pin for external D.A.
compensation circuitry. The AD1l54's uncompensated D.A.
performance is inherently superior, and in most applications the
D.A. compensation pin should be connected to ground. Where
additional compensation is desired to tailor the AD 1154 to a
specific user's application, only three resistors and a capacitor
are required to optimize the AD 1154's D.A. performance (see
Figure 11).
If a capacitor is charged to a voltage, discharged for a moderate
period of time, and then open circuited, the voltage on the
capacitor will begin to creep back towards its initial value. This
creep voltage is known as dielectric absorption. Dielectric
absorption occurs because the dielectric material doesn't polarize
instantly, the molecules need time to align themselves. As a
result, not all of the energy stored in a capacitor can be quickly
recovered upon discharge.
A first order model of the hold capacitor to include dielectric
absorption effects is shown in Figure 9. In addition to the main
capacitance, CM' and the insulation resistance, R1, there is an
+15V
A,
Figure 9. First Order Model of D. A. Effects
RDA and a C DA . When the capacitor is charged to some value,
CDA is also charged. When the capacitor is discharged, CDA also
discharges. But it must discharge through RDA , and, if the
capacitor is not disclIarged for a long enough period of time,
CDA will not completely discharge. As a result, when the capacitor is open circuited, C DA will discharge into CM causing the
voltage across it to creep back towards its initial value. The
actual model of the capacitor should contain additional RDAS
and CDAs with increasing time constants in parallel with the one
shown.
Figure 10 shows a circuit suitable for measuring the dielectric
absorption of sampleJhold amplifiers. The circuit operates as
follows: Rl and Cl set the frequency of the SHA control; R2
and C2 set the amount of acquisition time allowed for the SHA.
See the timing diagram of Figure 10.
+1SV
SHACONTROL
--I
LL--.Jr_____
L--
+1QV---,
SHAANALOGINP~~ ____
+5V
I
,
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
SHACONTR~~
~T" --t""--T.---1
I
Te :-I
Figure 10. Dielectric Absorption Measurement Circuit
During T s, the CONTROL line is high, the ADl154 is in the
sample mode and the analog input charges the hold capacitor to
+ 10 V. During Tc the analog input to the SHA is switched to
ground, effectively shorting the hold capacitor for the remainder
of the sample period. During T A' the SHA is switched into hold
mode and the hold capacitor is open circuited. The dielectric
rebound can be observed on the oscilloscope during T A' Refer
to Figure 12.
changing Rl, R2, CI and C2.
Note that the dielectric absorption error is dependent on several
factors: it is a function of how long the capacitor is charged
(Ts), how long it is discharged (Tc) and how long it is observed
while open circuited (TA)' These parameters can be modified by
2. Observe the dielectric absorption error on the oscilloscope.
The AD1154 provides a pin to compensate for dielectric absorption. To use it, the circuit of Figure 11 must be employed.
To fmd the optimum values for Rl, R2, R3 and Cl follow this
procedure:
I. Adjust the D.A. measurement circuit (see Figure 10) to represent a typical sampling rate.
3. Pick (RIIIR2) • Cl to be equal to the approximate time constant (Tcon~t) of the dielectric rebound on the oscilloscope
(see photo m Figure 12).
SAMPLEITRACK-HOLD AMPLIFIERS 6-55
II
•
4. R3 is used to adjust the magnitude of the compensation. To
fmdail initial approximation for R3, the following relationship can be used:
R3 = [Magnitude of D.A. error x(RI +R2)]/I0 x
lI(e-TcfTcoNST _e-T.ifl'coNST)
5. R3 can then be fine trimmed for the flattest output during
hold.
Using this method it is possible to reduce the effect of dielectric
absorption by a factor of four or five. The typical values for
resistors and capacitor given in Figure 11 are for a sample time
of 20 ....s, acquisition time of 5 .... s and a hold time of 20 ....s.
When determining the values, R3 should be less than 10 n, and
Cl should be as small as possible.
IN
.,
15kU
~~OPF
Figure 11. DIA Compensation Circuit with Typical Values
DYNAMIC SIGNALS
The primary purpose of using a sample/hold in front of an ND
converter is to hold the input constant while the ND performs
its conversion. Without a sample/hold, a 16-bit ND converter
would not be able to accurately digitize any signal whose. slew
rate exceeded 1 LSB divided by the conversion time. Or, for
15 fl.S AID with an input range of ± 10 V this says:
a
Input Signal Slew RateMAX = 1 LSB + Conversion Time
=20.3 VIS
Since the maximum slew rate of a sinusoid is defined as:
Slew RateMAX = 2 • 'IT • Amplitude. Frequency
This translates into a maximum input frequency of:
FIN MAX = Slew RateMAX + (2. 'IT. Amplitude) = 0.32 Hz
By using a sample/hold, however, the maximum slew rate of the
input signal is now limited by the aperture jitter of the sample!
hold, which is usually orders of magnitude better than a conversion time. Specifically, for an AD1l54 the analysis is:
Input Signal Slew RateMAX
2.035 V/.,.s.
= 1 LSB
+ Aperture Jitter
=
Now the maximum input frequency becomes:
FIN MAX = Slew RateMAX + (2.
'IT •
This represents a dramatic improvement over using the AID
converter by itself. The AD1I54's 222 kHz throughput
(lI(TACQ + T SETT)) and 150 ps aperture jitter allow it to digitize input signals of up to 32 kHz to 16-bit accuracy or up to a
128 kHz signal to 14-bits.
+15V
t
Figure 13. Offset Adjust Circuit
OPERATING INSTRUCTIONS
Offset Adjust
In most data acquisition systems only one offset adjustment is
made. Usually the offset adjust of the ND converter is used to
null the combined system offsets. However, the offset or pedestal of the ADli54 can be nulled by connecting a trim potentiometer between Pins 7 and 9, and tying the wiper to + 15 V
(refer to Figure 13.) To null the pedestal, ground the input of
the SHA and toggle the SHA CONTROL. Then adjust the pot
until the output of the SHA in hold mode reads 0 V. Please
note that each millivolt of offset adjust adjustment degrades linearity by 0.3 ppm.
APPLICATIONS
50kHz Sampling AID System
Figure 14 shows a typical connection of the AD1l54 to the
AD1376 (16-bit 15.5 ....s AID converter). This combination will
result in an AID conversion system capable of sampling a
25 kHz signal at a 50 kHz throughput rate. (Where Throughput
Rate = TACQ + TSETTLE + T coNv = 3.5 ....s + 1 ....s +
15.5 ....s = 20 ....s.) This example has an input range of ±10 V,
power consumption of < 1 Wand 16-bit resolution. The
accuracy of this system is limited to the AD 1376's 14-bit
performance.
Track-and-Hold
The AD1154's design is optimized for sample-and-hold applications and is internally compensated to guarantee 16-bit
(0.00076%) hold mode gain nonlinearity. Even though the
AD1l54 is tailored specifically as a SHA, it may be used as a
track-and-hold amplifier providing IS-bit (0.0015%) track mode
gain nonlinearity.
-15V +15V +5V
Amplitude) = 32.4 kHz.
Figure 14. 50 kHz Sampling AID Conversion System
Figure 12. Dielectric Absorption
6-56 SAMPLEITRACK-HOLD AMPLIFIERS
Ultrahigh-Speed Hybrid
Track-and-Hold Amplifier
HTC-0300A I
1IIIIIIII ANALOG
WDEVICES
FEATURES
Aperture Jitter of SOps
Input Range ±10V
Output Current ± SOmA
Max Droop Rate Sfl.V/fl.s
Max 200ns Acquisition Time (0.01%; 10V Stepl
APPLICATIONS
Data Acquisition Systems
Peak Measurement Systems
Simultaneous Sample &. Hold
Analog Delay
HTC-0300A FUNCTIONAL BLOCK DIAGRAM
ANALOG
INPUT
ANALOG
OUTPUT
INPUT
GROUND
HOLD
COMMAND
HOLD
COMMAND
LOGIC
GROUND
POWER
GROUND
+15V -15V +5V
NOTES: WHEN APPLYING HOLD COMMAND TO PIN 11, CONNECT
HOLDCOMMANDle!!U21 TO GROUND,
WHEN APPLYING HOLD COMMAND TO PIN 12, CONNECT
HOLD COMMAND (PIN 11ITO +5V.
GENERAL DESCRIPTION
The HTC-0300A is a hybrid microcircuit track-and-hold amplifier
useful in a wide range of signal processing applications, including
waveform measurements, analog signal delay, and signal
sampling.
The unit has a typical aperture jitter of only 50 picoseconds
rms; wide dynamic input range of ± 10 volts; and laser-trimmed
gain and offset which preclude a need for external adjustments.
Its speed and precision are the result of innovative design techniques using a high-speed op amp and DMOSFET switches.
These techniques also enhance device performance in feed through
rejection, linearity, harmonic distortion, droop rate, and output
voltage swing.
ORDERING INFORMATION
For a case temperature range of - 25°C to + 85°C, order the
HTC-0300A; it is packaged in a 24-pin hermetically-sealed ceramic
DIP,
A case temperature range of - 55°C to + 125°C is available with
the HTC-0300AM, HTC-0300AMl883B, and the HTC-0300ATDI
883B. The first two units are housed in 24-pin metal packages,
and the latter unit is packaged in a hermetic 24-pin ceramic
DIP.
All versions of the HTC-0300A are manufactured in a facility
which has been certified to MIL-STD-1772.
SAMPLEITRACK-HOLD AMPLIFIERS 6-57
SPEC IFICATIONS (Typical wiIh nominal ~ IIIIess oIharwise
s.....
Pu.........."(Coaditicms)
ANALOG INPUT
(FS = Fun Scale = 10V;
FSR =Full·Sca1e Ranae = ZOV)
# VoltqeRanae
# Overvoltqe,Noi>amage
j Input Impedance (VJN= 10V;
Pins 11 & IZ ="0")
# Initial Offset Vol_
(V,N = OV; Pins 11 & 12 = ''0'')
DIGITAL INPUT MODE
CONTROL
(TI'LCompatible)
j LOBi<''()''InputVol_
j LOBi< ''()" Input Current
1,2,3
+ZS'C
+ZS'C
Fun
I
+ZS'C
1,2,3
I,Z
# Logic ''0'' Input Current
j Loaic"I"InputVol_
j Logic ''()'' Input Current
1,2,3
I,Z
:/I Logic "0" Input Current
ANALOG OUTPUT
# Vol_
:/I Current
(Not Short Circuit Pro[ccted)
# Impedance
Capacitive Load (See text)
:/I Noise in Track Mode3
de to 100kHz
detolMHz
de to 5MHz
HTC-0300AM
Am/883BAMI883B'
HTC-03OOA1
Group Temp.
Min
9S0
T1P
Mas
1000
±IO
±IS
10SO
±O.s
±S.O
Full
0.0
+ZS'CI
+ IZS'C
-SS'C
Full
Z.O
+ZS'CI
+IZS'C
-SS'C
noIId)
0.8
±l.O
±1.0
S.S
±1.0
Min
9S0
ABSOLUTE MAXIMUM RATINGS
T1P
Mas
1000
±IO
±IS
10SO
n
±O.S
±S.O
mV
Supply Voltages
±Vs . . . . . . .
Vee ..... . . .
Storage Temperature
Junction Temperature
Junction Temperature
0.8
V
Lead Soldering (I Osee)
Digital Inputs
Analog Input .....
±1.0
JLA
0.0
±1.0
Z.O
±l.O
Uaito
V
V
JLA
S.S
V
±l.O
JLA
±1.0
JLA
+2S'C
±IO
±IO
V
+2S'C
+ZS'C
+25'C
+2S'C
±SO
±50
rnA
0.1
Z50
1.0
0.1
250
IS
34
0.1
1.0
..........
- 65°C to + 150°C
+ 150°C (A & AM)
+ 165°C (/8838 units)
... + 300°C
-0.5V to Vee
. ... ±15V
TRACKlHOLD FUNCTION
TRUTH TABLE
With 10gic levels shown at
HOLD
HOLD
(Fin H)
(Pinl2)
0
1
0
1
0
0
1
1
n
pF
).LVnns
IS
34
0.1
...... ±18V
... -0.5, +7V
Operating Mode
oiHTC-0300Ais
Track
Track
Hold
Track
IJ.Vrms
mVrms
DCACCURACY/STABILITY
# Gain
j
GsinError
./ Gain Nonlinesrity
./ Gain TemperatureCoeffic:ient
./ Input Offset
TemperatureCoefficient
TRACK (SAMPLE) MODE
DYNAMICS
Frequency Response
(V'N= IVp·p;Pin.11 & IZ=''()'')
./ Small Signal ( - 3dB)
Full Power ( - 3dB)
J
Slew Rate(VIN c: lOVp--p;
#
~onic Distortion4
Pins 11& IZ=''()'')
TRACK (SAMPLErTO-HOLD
DYNAMICS
Aperture Time
Aperture Uncertainty Qitter)
./ Pedestal(OffsetStep)
./ Pedestal Temp. Coeff.
:/I Pedestal Sensitivity
to + 5V Supply Changes
I
2,3
I
Z,3
2,3
+250(;
+Z5'C
Full
+2S'C
Full
Full
Z,3
Full
-1.0
-1.0
±O.OS
±O.l
±O.OS
±O.S
+5
±O.l
±O.IS
±O.OO5 ±O.O}
±O.O1
±O.S
±S
±3
±IS
±3
±O.OOS ±O.Ot
±lS
VN
%
%
%
%
ppmFsrc
ppmFSRI'C
Settling Time
ToO. 1%
ToO.I%
ToO.OI%
ToO.OI%
HOLD MODE DYNAMICS
./ DroopRate
j
Feedthrough Rej«tion
(V =ZOVp-p@Z.5MHz)
,N
4
5,6
4
5,6
+25'C
+2S'C
+25'C
Full
+2S'C
8
+Z5'C
+25'C
+25'C
Full
4
220
180
16
8
300
300
80
8
220
180
6
SO
8
±2.5
±20
4
MHz
MHz
VI,...
VlJLs
dB
16
8
300
300
80
6
SO
±2.S
8
DB
±20
±8
mV
ppmFsrc
ps,rms
+ZS'C
S
+25'C
Fun
180
180
380
380
180
180
380
380
7
8
7
8
+25'C
Full
+25'C
Fun
40
40
60
60
8S
85
100
100
40
40
60
60
8S
85
100
100
4
S
6
7
+ 25"C
+ IZ5'C
-55'C
+Z5'C
±O.S
±5
±O.S
±5
±l.!
±S
7
8
7
8
+25'C
Full
+2S'C
Full
+25'C
4
5,6
5
mVN
64
74
64
74
mVp·p
mVp-p
n.
n.
n.
n.
,..VI,...
,..V/,...
mVl~
dB
HOLD (SAMPLE)·TO·TRACK
DYNAMICS
./ Acquisition Time toO. 1%
./
(IOVp-pStep)
Acquisition TimetoO.Ol%
(IOV p-p Step)
Acquisition TimetoO.l%
(ZOV p-p Step)
RJNCTION
1
+16V
POWER GROUND 2
-15V
3
4
GROUND
5
NlA
6
N/A
7
N/A
8
N/A
9
N/A
INPUT GROUND 10
11
NIA
12
ANALOG INPUT
20
4
Switching Transient
j
PIN
24
23
22
21
'*
./ Amplitude
PIN DESIGNATIONS
(As viewed from bottom)
6-58 SAMPLEITRACK-HOLD AMPLIFIERS
100
100
160
160
110
170
170
200
200
100
100
160
160
110
170
170
200
200
n.
DB
n.
n.
ns
19
18
17
16
15
14
13
PIN
FUNCTION
ANALOG OUTPUT
N/A
N/A
NlA
N/A
NlA
NIA
NlA
+5V
LOGIC GROUND
!:IQbQCOMMAND
HOLD COMMAND
HTC-0300A
Parameter1,2 (Conditions)
SubGroup
HTC-0300A'
Typ
Max
Temp.
Min
±2S"C
+25"C
±14.25 ±IS
+4.75 +5.0
HTC-0300AM
ATDI883BAMl883B'
Typ
Min
Max
Explanation of Subgroups
Units
POWER REQUIREMENTS
Supply Voltages
±Vs
Vcc (Logic Supply)
±15.75 ±14.25 ±15
+5.25 +4.75 +5.0
± 15.75 V
+5.25 V
Supply Currents (VIN = OV;
Pins 11 & 12 = "0")
I
±Vs
I
Vcc(LogicSupply)
/ Power Dissipation
I
± V,POWERSUPPLY
REJECTION RATIO (PSSR)
(VIN~ IOV;Pin, II & 12~"0")
±21
±25
+25
+5
+5
I
2,3
I
2,3
I
2,3
+25"C
Full
+ 25<1C
Full
+ZSOC
FuU
650
650
n5
n5
+21
+4
+4
650
650
I
2,3
+ 25°C
Full
± 0.3
±O.3
±0.5
±O.5
±O.3
±O.3
±21
+21
+4
+4
±25
+25
+5
+5
775
rnA
rnA
n5
rnA
mA
rnW
rnW
±0.5
±O.s
rnVN
mVN
Subgroup 1 - Static tests at + 25"C.
(10% PDA calculated against Subgroup 1 for rugh-rel versions)
Subgroup 2 - Stark tests at maximum rated temperature.
Subgroup 3 - Static tests at minimum rated temperatu~.
Subgroup 4 - Dynamic tests at + 250(;.
Subgroup 5 - Dynamic tests at maximum rated temperature.
Subgroup 6 - Dynamic tests at minimum rated temperature.
Subgroup 7 - Functional tests at + 25"C.
Subgroup 8 - Functional tests at maximum and minimum
rated temperatures.
Subgroup 9 - Switching tests at + 25"<:.
Subgroup 10 - Switching tests at maximum rated temperatures.
Subgroup 11 - Switcbing tests at minimum rated temperatures.
Subgroup 12 - Periodically sample tested.
THERMAL RESISTANCE
CasetoAir,Oca5
Junction toCase, 9jc
34
34
28
28
MEAN TIME BETWEEN
FAILURES (MTBF)6
"C/W
"C/W
2.1 x 1(J6
PACKAGE OPTIONS'
DH-24B
M-24A
HTC·0300A
Hours
HTC.o300ATD/883B
HTC-0300AM
HTC-0300AMl883B
NOTES
j100% [CIted (See Notes 1 and 2).
#Specification guaranteed by design; not tested.
IHTC-0300A parame[Crs precc:dc:d by a chc:c:k (j) are tested at + 2S"C ambient temperature; perfonnancc:
is guar&ntc:cd ovc:r the industrial tc:mpuature range (- 25"C to + 85OC) case temperature.
2HTC-03OOAM. ATD1883B, AMl883B parameters precc:dc:d by a chc:ck (j) are rested at -55OC case,
+ 250C ambimt, and + 1250C case temperatures.
)Noise lc:ycJ incrc:asc:s witb incraslDs duty ~cle of Hold Couunand. Noise fIgUres shown
Track. mode are
meuured witb input grounded and filters for frequencies shown on output.
"V1N ",20V Pop, 200kHz sine wave; RL"" lkO; Mode: ControJ Track.
~he relationship between [be device packqe ami outside environment (8.,.) varies with the application. Value
shown is based on lllHSuring case tempe:rature with supply voltages applic:d to a device installed
in a ZIF socket mounted on a standard "EJ" bum-in board.
6MTBF calcuJ.ted for 18838 unit using MIL-HNBK 217D; Ground Fixed; Temperature (Ambient)= + 25"C.
7See Section 14 for packqc outline information.
I
eo..
=
Specifications subjc:ct to change without notice.
APPLICATIONS
Track-and-hold (TIH) amplifiers can be used in a wide variety
of ways, but the most common application for these units is to
place them ahead of an AID converter. The combination of a
TIH and converter is used when the bandwidth of the signal to
be digitized is wider than the converter can handle by itself,
i.e., the analog input is changing more than one LSB during the
converter's conversion interval.
In applications of this type, the HTC-0300A "freezes" the incoming
signal on command to present a nonchanging signal at the input
stage of the conve~ter.
The HTC-0300A TIH can reduce the aperture window to 100
picoseconds when used with the appropriate AID. It can also be
used for peak-holding functions, simultaneous sampling AIDs
(when combined with analog multiplexers), and other high-speed
analog signal processing applications.
Pin 11, Hold Command input (Pin 12) must be connected to
ground.
For applications which require an inverted Hold Command, this
"freezing" of the inverted analog output can be accomplished
with a digital "0" applied to the Hold Command (Pin 12) input.
In this case, a digital "I" establishes the "track" mode of operation.
For these, the Hold Command input (Pin 11) must be connected
to +sV.
Refer to Figure 1, the HTC-0300A TracklHold Waveforms.
APEIITIIfIE
ERROR
ACTUAL
SA=D
ANAlOGINPUT
When a TTL-compatible digital logic "I" is applied to the Hold
Command input of the TIH, the inverted analog output of the
HTC-0300A is "held" at the value which was present at the
time of the Hold Command, plus the apertUre time. If the change
from the "track" mode to the "hold" mode is accomplished via
-1---
I:
II I
APEATUR£
--II t-UNCERTAtNTV
"t"HOLD
HCM.DCOMMANDINPUT
THEORY OF OPERATION
When operated in the "track" mode, the HTC-0300A functions
as an operational amplifier with a gain of - I, following all
changes in the analog input signal as they occur.
_1 ___ _
I
~ .--nME
:
1-=:0-;
,
,
ANALOG OUTPUT
:
-------}EMOR
I'
~
_L'/
- '
TRANSIENTS :
T--
ERRCNIRANGf:
DUETOAPERTUAE
UNCERTAINTY
_
BAND
----1r-:
I DROOP
~
---I
~
I
I-- ACOUISJT1ONTlME
Figure 1. Track/Hold Waveforms - HTC-0300A
SAMPLEITRACK-HOLD AMPLIFIERS 6-59
Two different intervals of time can affect the point on the analog
mput which is sampled when the TIH is switched from "track"
to "hold". There is no major difference m operation whether
this change in state is accomplished via the Hold Command or
Hold Command; the functioning of the HTC-0300A is essentially
the same, with only a slight difference in timing because of an
additional logic package in the Hold Command signal path.
The delay interval, aperture time, is a constant and should not
be regarded as an error source. The design of the HTC-0300A
assures that aperture time is within its spec from unit to unit;
and is also repeatable from one "hold" command to the next in
any given unit. In this way, aperture time can be compensated
with system timing to assure an optimum sampling point.
The width of the the sample pulse applied to the Hold Command
input (or, if using inverted logic, the Hold Command input) is
determined by (1) the acquisition time of the HTC-0300A, and
(2) the desired accuracy of the sampled output. Output accuracy
will also be a function of the amount of change which has occurred
since. the preceding sample.
This latter phenonmenon is illustrated in Figure 3. Note the
analog input has changed drastically between the first and second
hold commands. There is a considerably smaller change between
the third and fourth pulses; as a consequence, movement in the
held value of the output is correspondingly smaller.
V
ANALOGINP::
Aperture uncertamty, or "jitter", is the other interval affecting
the held value. It is the result of noise signals which modulate
the phase of the hold command and shows up as sample-ta-sample
variations in the value of the analog signal being "frozen."
As expected, the error resulting from jitter is directly related to
the dV/dt of the analog input. If very-high-speed inputs are
sampled, any given value of jitter will result in larger errors in
the held value at the output as dV/dr increases. See Figure 2.
The high feedthrough rejection of the HTC-0300A in the hold
mode is an important characteristic; it precludes errors being
introduced during the conversion interval of the digitizer.
15..
:> 12.6
-1.V~P INPUT SIGNAL
i •
ffi •
•
~
10.
/
7.5
/
5.
2.5
./
50
500
5000
-5V
RUm
COMMAND
0 :V:1\V!( \
TRACK
!
: I
1
!
I
:1
!
l
I
I
1
I
I
I
•
I
I
I
I
I
I
I
H
ANALOG OUTPUT
----u
I
I
I
r
I
r
_!~i·
------.!
L
Figure 3. Sample/Hold Operation
Figure 4 illustrates settling accuracy versus acquisition time;
closer accuracies require more time. The relationShip approaches
an asymptotic curve and is not a linear function.
The HTC-0300A is a "closed loop" TIH and is suitable for most
applications requiring a track-and-hold for update rates up to
5-10MHz. (Note: 5MHzconversion rates are only a guide and
are based on system acquisition time, not logic speed. Higher
rates are possible with trade-offs in acquisition time.)
INPUT ANALOG BANDWIDTH - kHz
Figure 2. HTC-0300A Error Due to Aperture Uncertainty
As shown in Figure 1, droop is the amount the output changes
during the hold period; this is the result of loading on the internal
hold capacitor. Low droop rates are important in TIH amplifiers
to insure they are appropriate for high-resolution digitizing.
Excessive droop rates can negate the effectiveness of having
converters of 10 or 12 bits or more. Lower-order bits may be in
error because of changes in the held value during the conversion
cycle, especially for successive-approximation converters.
The return to the "track" mode is accomplished by changing
the digital logic level of the hold command; Figure 1 shows the
hold command as it would appear at the (Pin 11) Hold Command
input.
Acquisition Time is the interval required for the analog output
to re-establish accurate tracking of the changing input and remain
within a specified error band around its final value. The greater
the change m the input value during the hold period, the longer
this mterval is. Nyquist sampling is the most stringent
application.
Transients shown in Figure 1 are "spikes" which occur at the
output of the T/H at the beginning and end of each "hold"
period because of switching transients within the unit. When a
T/H is used at the output of a D/A converter for "deglitching"
discontinuities in the output of the converter, these transients
occur at the update rate and can be fIltered.
SAMPLE-AND-HOLD (SIH) MODE
Although it is generally used in the track-and-hold mode, the
HTC-0300A can also be used as a sample-and-hold device. In
the SIH mode, the output of the unit is usually in the "hold"
mode, but is switched briefly to the "sample" (track) mode.
6-60 SAMPLEfTRACK-HOLD AMPLIFIERS
i.
~
1.0
'\
"- 10VOUTJUTCHANG~
0.3
0.1
"- ..........
~ 0.03
!j
~ 0.01
50
150
100
TlME-ns
-- 200
Figure 4. Settling Accuracy vs. Acquisition Time
For optimum performance, the HTC-0300A must have external
bypass capacitors connected to the power supply pins close to
the device. Electrolytic capacitors of 10 - 22J.1-F and ceramic
capacitors of 0.01- O.I,.,.F on each supply will enhance performance
of the unit.
Output loading has some restrictions. To avoid oscillations,
limit capacitive loads to 250pF; the recommended resistive
loading is 5000. Acquisition and settling times are relatively
unaffected by capacitive loads up to 50pF and resistive loads
down to 2500.
A massive ground plane, careful component layout, and physically
separating digital and analog signals as much as possible are also
among the multitude of items which can affect the operation of
circuits that include the HTC-0300A TIH.
Cross coupling of analog and digital signals is often a majo!'
problem at high frequencies. Relatively low levels of ground
plane noise can "mask" lower-order bits when the HTC-0300A
is used in high-resolution digitizing. The user must exercise
care in electrical and mechanical design to assure satisfactory
performance.
Ultrahigh-Speed Hybrid
Track-and-Hold Amplifiers
HTS-0010 I
1IIIIIIII ANALOG
LIllI DEVICES
HTS-OOIO FUNCTIONAL BLOCK DIAGRAM
FEATURES
Aperture Jitter of 2ps rms
Acquisition Time 10ns
Output Current ± 40mA
Slew Rate 3OOV/fA.S
APPLICATIONS
Data Acquisition Systems
Radar Systems
Instrumentation Systems
Medical Electronics
HTS·OO10
t - - - -.....--{18 ~~~~~~
HOLD
COMMAND
19
Vcc +
GENERAL DESCRIPTION
The Analog Devices HTS-OOIO Track-and-Hold is another
example of Analog's continuing efforts to advance the state of
the art in high-speed circuits.
The HTS-OOIO adds breadth to a line of devices which offers
designers the industry's widest range of track-and-hold and
sample-and-hold units.
Its pinouts are similar to its predecessor HTS-0025 Track-andHold, but it provides enchanced performance in many of the
characteristics established by that device. Two pins which are
unused on the HTS-0025 are used on the HTS-OOIO, but with
those exceptions, the two devices have identical pin assignments.
This plug-in compatibility gives designers remarkable flexibility
~~~~~
PWR
GND
in selecting those parameters which are optimum for their
applications.
The HTS-OOIO Track-and-Hold (T/H) uses many of the proven
design concepts which have made the HTS-0025 TIH the standard
of comparison for high-speed circuits of this type. A dc-coupled
Schottky diode bridge is driven by a high impedance buffer
amplifier and followed by a low impedance output amplifier to
achieve the best possible combination of speed and drive
capabilities.
All models of the HTS-OOIO are housed in a standard 24-pin
metal DIP. The unit operating over a temperature range of 0 to
+ 70·C is HTS-OOIOKD; the unit for a range of - 55·C to + lOO·C
is HTS-OOIOSD.
SAMPLEITRACK-HOLD AMPLIFIERS 6-61
I
SPECIFICATIONS
(typical @
+ 25"1: and nominal power supplies unless otherwise nobld)
Parameter
Units
HTS·OOIOKD
HTS.ooIOSD
ANALOG INPUT
Voltage Range
For Rated Performance
Maximum Without Damage
Impedance
Capacitance
Bias Current
Vp-p
V
0
pF(max)
,..A(max)
2
±3
7
20
*
*
*
*
*
DIGITAL INPUT (ECL Compatible)
Mode Control
Hold Command Input
"0" = Track
"1" = Hold
V
V
-1.5to - I.8
-0.8to -1.l
*
*
mA(max)
o (max)
±4O
9(12)
*
*
,..Vrms(max)
20(40)
*
VN(min)
% (max)
% (max)
ppm/oC (max)
mV(max)
./LvrC(max)
0.%(0.93)
0.1
0.01
30(40)
±2(±5)
*
*
*
125.(175)
*
*
MHz (min)
MHz (min)
V/,..s(min)
40
60
300(250)
*
*
*
dB (max)
dB (max)
dB (max)
dB (max)
-68
-65
*
*
*
*
ns(max)
ps(rmsmax)
mV(max)
,..VrC(max)
mVN(max)
ns
-2(± 1)
2
±2(±1O)
50
10
1.5
*
*
*
mV(max)
ns(max)
± 15(30)
5(14)
*
*
mV/,..s(max)
mV/,..s(max)
0.1
3.0
*
*
dB(niin)
dB (min)
62
52
*
*
ns(max)
ns(max)
10(16)
14(19)
*
*
ns(max)
ns(max)
13(16)
16(22)
1.5
*
*
*
ANALOG OUTPUT
Current (Not Short Circuit Protected)
Impedance
Noise in Track Mode
@5.0MHzBandwidth
DCACCURACY/STAB!L!TY(FS
Gain (No Load)!
Gain Nonlinearity; 2V FS Input
Gain Nonlinearity; I V FS Input
Gain Temperature Coefficient
Initial Offset Voltage
Offset vs. Temperature
~
lOs
Full Scale)
TRACK (SAMPLE) MODE DYNAMICS
Frequency Response
Full Power Bandwidth
Small Signal ( - 3dB) Bandwidth
Slew Rate
Harmonic Distortion (Track Mode;
4MHz, 2V pop Input)
RL = IkO
RL = 5000
RL = 200n
RL = 750
TRACK (SAMPLE).TO-HOLD SWITCHING
Effective Aperture Delay Time2
Aperture Uncertainty (Jitter)
Offset Step (Pedestal)
Sensitivity to Temperature
Sensitivity to - 5.2V
Switch Delay Time
Switching Transient
Amplitude
Settling to ±5mV
HOLD MODE DYNAMICS
DroopRate(@ +25°C)
Droop Rate (@TemperatureExtremes)
Feedthrough Rejection
(2V p-p Input)
@IMHz
@IOMHz
HOLD-TO-TRACK (SAMPLE) DYNAMICS4
Acquisition Time (1 V Step)
to ±I%
to ±0.1%
Acquisition Time (2V Step)
to ±1%
to ±O.I%
Switch Delay Time
6-62 SAMPLEITRACK·HOLD AMPLIFIERS
DS
-64
-50
30(50)
2503
*
*
HTS-0010
Parameter
Units
HTS-OOIOKD
HTS-OOIOSD
POWER REQUIREMENTS
V + (+ 15V ±0.5V)
V - (-15V ±0.5V)
Vcc + (+ 5.0V ±0.25)
Vcc - (- 5.0V ±0.25)s
VEE(-5.2V ±0.25)s
Power Dissipation
Power Supply Rejection Ratio'
(dc to 10kHz)
rnA (max)
mA(max)
mA(max)
mA(max)
mA(max)
W(max)
mVN(max)
36
48
22
25
45
1.73
10
*
TEMPERATURE RANGE
Operating (Case)
Storage
"C
°C
Oto +70
-55to+125
*
°crw
°crw
42
12
*
*
THERMAL RESISTANCE7
Junction to Air, aJA (Free Air)
Junction to Case, a]e
MTBF8
Mean Time Between Failures
*
*
*
*
*
*
-55to+l00
6.83 X 105
Hours
PACKAGE OPTION 9
M-24A
HTS-OOI0KD
HTS-OOIOSD
II
For applications assistance, call (919) 668-9511.
PIN DESIGNATIONS
2Effective Aperture Delay Time is delay between
Hold strobe and held value of analog output,
referenced to analog input (see text).
3Pedestal temperature variation on HTS-OOIOSD
is same as HTS-OOIOKD below + 70"C, but increases
between + 70°C and + 100°C.
For acquisition time measurements, RL = 2000; C L == 3pF.
5Vcc - may be tied to VEE with adequate bypass capacitors
4
(see text).
6Variarions in V - ( - lSV) have greater effect on
unit performance than variations in other supplies;
PSRR shown is for V - .
7Maximumjunction temperature is + ISaac.
'Calculated using MIL-HNBK 217; Ground; Fixed; + 70,,{; case temperature.
9See Section 14 for package outline information.
'Specifications same as HTS-OOIOKD.
Specifications subject to change without notice.
PIN
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V cc + (+5V)
V cc - (-5V)
V ( 15V)
V ee (-5.2V)
HOLD COMMAND
DIGITAL GROUND
POWER GROUND
V+ (+15V)
V .... + (+5V)
V CC - (-5V)
POWER GROUND
V- [-15V)
ANALOG INPUT
N/A
N/A
N/A
N/A
ANALOG GROUND
ANALOG GROUND
AUXILIARY HOLD
POWER GROUND
V+(+15V)
N/A
ANALOG OUTPUT
POWER GROUND (PINS 7,11 AND
21), ANALOG GROUND (PINS 18
AND 19), AND DIGITAL GROUND
(PIN 6) MUST BE CONNECTED TOGETHER AND TO A LOW-IMPEDANCE GROUND FOR PROPER OPERATION. MAKE CONNECTIONS
AS CLOSE TO DEVICE AS POSSIBLE.
HYBRID CASE IS CONNECTED TO
ANALOG GROUND INTERNALLY.
SAMPLEITRACK-HOLD AMPLIFIERS 6-63
Applications
be done by applying an external ECL-compatible HOLD
COMMAND to Pin S.
One of the main uses for track-and-hold (T/H) units is ahead of
analog-to-digital (AID) converters to allow digitizing signals with
bandwidths higher than the AID can handle by itself. The use
of an appropriate T/H allows the converter to become a true
"Nyquist converter", i.e., capable of digitizing analog signals
whose maximum bandwidth is one-half the encoding rate.
Refer to Figure 2, Track/Hold Waveforms.
The characteristics of the HTS-OOIO T/H make it useful in
multiple other applications beside this "standard" use of devices
of this kind. It can be used in sample and hold circuits, peak
holding applications, simultaneous sampling AIDs (with appropriate analog multiplexing), and for many other data processing
needs.
Refer to Figure I, HTS-OOIO Interconnection Diagram.
+1V
ANALOG
INPUT
-1V
TRACjHOLD
ITRACK
:~MAND=---""''''''f~ SwrrcHDE1AYTIME~
+ lV
TRANSIENT
I
AMPLITUDE I
r-
TRANSIENT
I_SETT~~
ANALOG
OUTPUT
I
______IJ_
FEEOTHROUGH
___
VFTP-P
I
DROOP RATE .., ~
rr-
-1V
Figure 2. TrackIHold Waveforms
Vcc + Ycc- v-
Va
v+
Figure 1. HTS-0010 Interconnection Diagram
A varying, ideal analog input is shown at the top of Figure 2 for
purposes of illustrating the response of the HTS-OO 10 to various
types of inputs. This method of presentation helps show some
of the critical, and often ruisleading, parameters of high-speed
track-and-hold devices.
During the track mode, the unit operates as a high-speed buffer
amplifier, with the output following input changes as they occur.
In this mode, the response of the HTS-OOIO is limited primarily
by the slew rate characteristics of the device. As a result, the
analog output is a faithful reproduction of the input as long as
the highest frequency component of the input signal does not
exceed the bandwidth of the unit.
Bypass capacitors are used internally on all power supply leads
on the HTS-OOIO track-and-hold. External bypassing of all
power supplies with O.OIILF-O.IILF ceramics will help performance. In addition, electrolytic capacitors of 10-22 microfarads on
each supply will also enhance the HTS-OOIO's operation
The analog output shown on the bottom of Figure 2 tracks the
input until a HOLD COMMAND is applied to Pin S. When
this pulse arrives, the sample bridge of the HTS-OOIO disconnects
the hold capacitor from the input. The short, but finite, interval
required for this action is called aperture time.
A massive ground plane, careful component layout, and physically
separating analog and digital signals are among the other considerations which can have major effects in improving the high-speed
characteristics of the HTS-OOIO track-and-hold.
Two other delay intervals combine with aperture time. One is
delay in the hold command caused by propagation delay in the
bridge driver; for purposes of discussion, this is a digital delay
(I=
"3
20 19
"
•
•
Q
,;
..
EN 4
A2
"
z l!
,.
17
..
O~l 5
NC
NC.
15 OUT
sa 7
14 52
'7 8
,. "
17
NC
TOP VIEW
INot to Scale)
"
1.
OUT 1-4
52
:l;
"3
:; "
z l!
2
1
2.
Q
,.,;
z :;
l! l!
•
"3
2
1
20
,.;
51
Ne
OUT
OUT
"8
12
13
ill III !!
~
:a
Ne '" NO CONNECT
S1
AD7502
NC
TQPVIEW
PLCC'(P.ZOA)
LCCC4 (E·20A)
AD750IJP
AD7501KP
AD7502JP
AD7502KP
AD7503JP
AD7503KP
AD750ISE
AD750ISE
AD7503SE
INotto Scale)
"
52
AD7501
A,
0
0
0
0
Ao
0
EN
0
0
1
0
1
1
1
0
0
0
III III l! :l; l:
Ne '" NO CONNECT
X
1
1
X
X
1
0
AD7S03
AD1502
"ON"
AI
1
2
0
0
4
5
6
7
8
1
X
,
,, , , ,
AI
0
,, , , ,,
,
1
11
AD750ISQ
AD7502SQ
AD7503SQ
V""
52
• ,.
AD750IJQ
AD7501KQ
AD7502JQ
AD7502KQ
AD7503JQ
AD7503KQ
TRUTH TABLES
V""
AD7501/AD7503
TOP VIEW
(Not to Scale)
AD7501]N
AD7501KN
AD7502JN
AD7502KN
AD7503JN
AD7503KN
3PLCC: Plastic Leaded Chip Carrier.
4LCCC: Leadless Ceramic Chip Carrier.
0
EN
Hermetic (Q.16)
2See Section 14 for package outline information.
PLCC
Z
- SS"C to + 12S"C
Hermetic (Q·16)
NOTES
ITo order MIL~STI)..883, Class B processed parts, add/883B to part number.
See Analog Devices' 1987 Military Databook for military data sheet.
l:
NC '" NO CONNECT
Q
- 2S"C to + 8S"C
Plastic DIP (N·16)
12 13
10 "
ill III l!
Ne '" NO CONNECT
18 V""
AD7502
•
12 13
III III l! :l; l:
20 19
""
EN •
.,
V""
1
2
Oto +70"C
Ao
.... ·"ON··
, ,, ,,,
,&,
2&6
'&7
4&8
X
None
0
1
0
None
0
A,
AI
0
0
0
0
0
0
1
A.
0
1
0
,, , ,
, , ,
0
0
1
1
X
X
0
1
0
X
EN
0
0
0
0
0
0
0
0
1
,
,
"ON"
2
4
5
6
7
8
No~
CMOS SWITCHES & MUL TIPLEXERS 7-7
SPECIFICATIONS (voo = + 15V,Vss = -15VunlessolheJWiseno1ed)
PARAMI!TER
VERSION'
SWITCH
CONDITION
@2SoC
AD750l, AD7503
AD7502
ANALOG SWITCH
··
··
··
·
OVER SPECIFIED
TEMP. RANGE
AD7S01,
AD7502
AD7503
TEST CONDITIONS
-IOV';; Vs .;; +lOV
IS = 1.0mA
All
All
ON
ON
170n typ, 300n max
20% typ
RON vs. Temperature
.6.RON Between Switches
RON vs. Temperature Between
Switches
All
All
ON
ON
0.5%i"C typ
4% typ
All
ON
±O.OI%/"C
IS
J, K
S
OFF
OFF
O.2oA typo 20A max
O.SnA max
J,K
OFF
InA typ, lOnA max
0.6nA typ, 5nA max
2S0nA max
··
S
OFF
SnA max
3nA max
250nA max
12SnA max
J,K
ON
ON
12nA max
S.SnA max
7nA max
3.SnA max
300nA max
17SnA max
17SnA max
RON
RON VS, Vs
loUT
IlouT - lsi
S
DIGITAL CONTROL
VINL
VINH
3.0V min
2.4V i1\il)
IINL or IINH
= Ii
2
1
"
0
~
Vi
§
o
AD7510DI
AD7511DI
TOP VIEW
AD7512DI
TOP VIEW
(Not to Scalel
(Not to Scatel
A4
>1:3
14 OUT 2
8
~
J
NC "" NO CONNECT
~
!
;Z
9
10
11 12
13
~
J
~ ~
CI
NC ::: NO CONNECT
CMOS SWITCHES & MUL TIPLEXERS 7-9
SPECIFICATIONS tv
DII
= + 15V.Vss= -l5Vunlessolhnisenolad)
COMMERCIAL AND INDUSTRIAL VERSIONS
PARAMETER
,
ANALOG SWITCH
RON
RoN VS Vo (Vs )
MODEL
VERSION
+2'·C
(N. p. Q, E)
All
All
J. K
J. K
75n typo 100n max
20'H0 typ
0. K)
o to +70·C (N. P)
TEST CONDITIONS
-2'·C to +S,·C (Q)
175n max
-10V " Vo " +lOV
los m 1.0mA
RON Drift
RON Match
RoN Drift
Match
All
All
J.K
J. K
+0.596/"C typ
196 typ
All
J.K
O.OI%/"C typ
10 (15)01'1''
All
J. K
0.5nA typo 5nA max
10 (IS>ON'
All
J.K
10nAmax
AD75l2D1
J. K
l5nA max
All
All
All
All
All
All
J.
J
K
J.
J.
J.
K
K
K
K
7pF typ
lOnAmax
lOnAmax
~NSrrJON
AD75l0Dl
AD7511DI
AD75l0Dl
AD7511D1
AD75l2D1
J.
J.
J.
J.
J.
K
K
K
K
K
l80no
350no
350ns
lSOns
300ns
Gi (Co)OFF
Cs (Co)ON
Cos (CS - OUT )
Coo (Gis)
COU,\:
All
All
All
All
AD7S12D1
J. K
J. K
J. K
J. K
J. K
8pF typ
l7pF typ
lpF typ
O.SpF typ
l7pF typ
~J
All
J. K
30pC typ
All
All
J. K
800j1A max
SOOj.!Amax
800j.!Amax
800j.!Amax
All digital inpu ts
J. K
All
All
J. K
J. K
500j.!Amax
SOOj.!A max
500j.!Amax
SOOj.!A max
All digital inputs = VINL
'oUT
,
Vo = O. los = 1.0rnA
500nA max
Vo = -lOY. Vs = +IOV and
Vo =... lOV. Vs = -lOY
Vs = Vo =+10V
Vs =Vo =-IOV
l500nA max
VS1 = VOUT =tlOV. VS2 =+lOV
and VS2 = VOUT =tlOV. VS1 =+lOV
DIGITAL CONTROL
VINL '
VINH '
8 !! g
~
NC "" NO CONNECT
NC
•
•
l~
I. 11 12
J
13
l!! l!! i:!
NC "" NO CONNECT
CMOS SWITCHES & MULTIPLEXERS 7-13
SPECIFICATIONS(Voo =15V,Vss = -l5Vunlessolherwisenotad)
Model
Panmeter
ANALOG SWITCH
Analog Signal Range
AU
AU
AU,
AU
AU
AD7590DI
AD7591DI
AU
RoN'
RoN Match'
RoN Match Drift'
T,,= +2S"C
AUVenions'
K,B
Veni_
±IO
60
90
±IO
±IO
120
ISO
2
louT'
AD7592DI
C s (Co) OFF'
C s (Co) oN'
Cos (Cs.our)·
Coo(CsS)'
All
All
All
All
COVT4
AD7592DI
0,01
0.5
5
0.5
5
0.5
5
I
10
10
30
I
0.5
40
All
All
All
All
0,8
2.4
7
I
0.8
2.4
7
I
AD7590DI
AD7591DI
AD7590DI
AD7591DI
AD7592DI
250
400
400
250
350
250
300
380
500
500
380
450
300
300
20
30
10 OFF'
Is OFF'
10 (Is) ON'
AU
TVenioa
50
200
50
200
50
200
100
400
2-4
7
I
U11iIa
Volta
Otyp
o max
Otyp
IlrCtyp
nAtyp
nAmax
nAtyp
nAmax
nAtyp
nAmax
nAtyp
nAmax
pFtyp
pFtyp
pFtyp
pFtyp
pFlyp
TestCcmditioaslCommenta
-IOV""Vs "" +IOV,Ios=lmA;
T",Circui, I
Vs=O,Ios=lmA
Vs=O,Ios = lmA
Test Circuil 2
T ..,CiraJita2&3
Tesl Circuil 4
Test Circuil 3
DIGITAL CONTROL
VINL1
V INH2
C lN'
IINL or IINH2•5
O.S
Vmax
Vmin
pFlyp
"A max
VIN=OorVDD
DYNAMIC CHARACTERISTICS
toN'
toFF'
,
tTRANsmON
All
All
All
Write Pulse-Width (I...)'
Address SctupTime(IAs)'
Address Hold Time (IAR)'
Offlsolation4
(Analog Inpul 10 AnalogOulpuI)
380
SOO
500
380
450
400
400
40
nsmax
nsmax
nsmax
nsmax
nsmax
nsmin
DSmin
nsmin
Test Circuit 5
Test Circuil 5
Test Circuil 6
SccFigUre I
Sec Figure I
SccFigUrel
All
-85
dBlyp
A, WR=0.8V;Vs= 10V(Pk-Pk);
f=lkHz,RL=IOkO
AU
5
mVpeak,IYP
R L=IMO,CL=15pF;
VINH=3V, VINL=OV;
tRISE = tpALL =2Ons;
WRheJdHIGH
AU
55
pClYP
T .., Circuit 7
All
All
I
I
mAmax
mAmax
Digital Inputs = VINL or V INH
Crosstalk4
(Digitallnpul to Analog OulpuI)
QIN/'
(Charge Injection)
,
100
POWER SUPPLY
15sl
1.5
I
2
I
NOTES
'Temperature Rangesasfollows: K Versionj 0 to + 7O"C
BVenion; -2SOCto +85OC
TVersion; -5S"CI. +12S"C
'100% tested.
lGuaranteed, not production tested.
+rypical values for information only, not subject to test.
'Inputs are MOS gates typica1 current less s=
::~,
--:_--'''''-_--:-,.-.
'V_--i-Wi!
Ov
1.
:\
I
. I
~tA$~1
YlB
tAH: A1-A4 VALID TO
HOLD TIME
1A s: A1-A4 VALID TO WR SETUP TIME
tWA: WR PULSE WIDTH
Figure 1_ Timing and Control Sequence
7-14 CMOS SWITCHES & MULTIPLEXERS
TIMING AND CONTROL SEQUENCE
Figure 1 shows the timing sequence for latching the switch
address inputs. The latches are level sensitive and, therefore,
while WR is held low the latches are transparent and the switches
respond to the address inputs. The digital inputs are latched on
the rising edge of WR.
NOTE: All digital input signals rise and fall times measured
from 10% to 90% of 3V. tR=tp=20ns.
AD7590DI/AD7591 Dl/AD7592D1
ABSOLUTE MAXIMUM RATINGS·
(TA = + 2S'C unless otherwise noted)
VDDtoGND . . . . . . . . . • . . • .
VSS toGND . . . . . . . . . . . . . . .
Overvoltage at VD 01s), One Switch Only
( lsec surge) .
+17V
-17V
VDD +2SV
orVss -2SV
(Continuous)
. VDD +20V
orVss -20V
or 20rnA, Whichever Occurs First
Switch Current (IDs, Continuous) .
. SOmA
Switch Current (IDs, Surge)
Ims Duration, 10% Duty Cycle
. ISOrnA
Digital Input Voltage Range
-0.3V to VDD +0.3V
Power Dissipation (Any Package)
Up to +7SoC . . . . . .
Derates above + 7SoC by
Storage Temperature .•.
Operating Temperature
Commercial (K Version)
Industrial (B Version) .
Extended (T Version) ..
4S0mW
6mWI"C
- 6SOC to + IS0°C
. .. 0 to +70·C
-2SoC to +8SoC
- SsoC to + 12SoC
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
CAUTION------------------------______________________
WARNING!
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
0
~~DEV'CE
Typical Performance Characteristics and Test Circuits
TEST CIRCUIT 1
150
1!
a:
I
-
lmA
120
lA ±1.5V
./
A
90
I-..
60
r--...
---
v
±10V -
1~4~---Vl ----~... I
--:15V
D
30
o
-20
-15
-10
-5
0
10
15
RON
20
Vl
= 1mA
•
V.- VOLTS
RON AS A FUNCTION OF V D (V.l
FOR DIFFERENT SUPPLY VOLTAGES
TEST CIRCUIT 2
TEST CIRCUIT 3
(AD7590DI, AD759IDI)
(AD7592D1 ONLY)
Is (OFF)
51
IDIOFFI
OUT
~1---+-...;;.5-o~"()o!>--tI---I~
~
",10V
±10V
52
~
=-
±10V
"
..:. :;:10V
~
CMOS SWITCHES & MULTIPLEXERS 7-15
Typical Performance Characteristics and Test CircuitsCont'd
TEST CIRCUIT 4
51
OUT
52
=- ±10V
~
B.
AD7590DI, AD7591DI
b. AD7592DI
TEST CIRCUIT 5
SWITCHING TIME OF AD7590DI AND AD7591DI, toN, toFF
+15V
-15V
±10V
3V
AD7590DI .50%
OV
3V·
)
ADDRESS
DRIVE (V'N)
.1 _________ ~
V DD
S
D
f - -.....- - _ - o Vo
---.J.,
~~.___
1,.-_ __
~OV
I --~~\
AD7591DI
14pF
- - - - - -
1
_I,
r.
ADDRESS
DRIVE (V'N)
I
I
90%
)
1
I
I
I
:
- - 1Ii--J
- I +_..
'"UfII
)
--I
toFF
I--
TEST CIRCUIT 6
SWITCHING TIME OF AD7592DI, truNsmoN
+15V
±10V
"'10V
-15V
3V
S1
S2
OUT
--_-o
f - -......
~---------\Vo
I
OV
I
14pF
ADDRESS
DRIVE (V'N)
IL-----
90%
:
I
1
1
I
I
I
I
- -_
-~I-J
-.
---I
tTAANSI110N
I
1-
tTRANSmoN
TEST CIRCUIT 7
CHARGE INJECTION
+15V
-15V
SWITCH ON
3V
Vo
~
SWrCHOFF
OV
~~Vo
Q'NJ=ClX~VO
7-16 CMOS SWITCHES & MUL T1PLEXERS
t
4 x 1 Wideband
Video Multiplexer
1IIIIIIII ANALOG
WDEVICES
AD9300 I
FEATURES
34MHz Full Power Bandwidth
:!:0.1dB Gain Flatness to 8MHz
75dB Crosstalk Rejection @ 10MHz
0.05% .05% Differential Phase/Gain
Cascadable for Switch Matrices
AD9300 FUNCTIONAL BLOCK DIAGRAM
(Based on Cerdip)
AD9300
APPLICATIONS
Video Routing
Medical Imaging
Electro-Optics
ECM Systems
Radar Systems
Data Acquisition
GENERAL DESCRIPTION
The AD9300 is a monolithic high-speed video signal multiplexer
useable in a wide variety of applications.
'3·r---~cr----~r----
GROUND
RETURN
Its four channels of video input signals can be randomly switched
at megahertz rates to the single output. In addition, multiple
devices can be configured in either parallel or cascade arrangements
to form switch matrices. This flexibility in using the AD9300 is
possible because the output of the device is in a high-impedance
state when the chip is not enabled; when the chip is enabled,
the unit acts as a buffer with a high input impedance al)d low
output impedance.
BYPASS
~ •. '~F
The AD9300KQ is packaged in a 16-pin ceramic DIP, and the
AD9300KP is packaged in a 20-pin PLCC; both are designed to
operate over the commercial temperature range of 0 to + 70°C.
For military temperatures of - 55°C to + J25°C, order part
number AD9300TQ, which is also a 16-pin ceramic DIP. In
addition, the AD9300 is available in a 20-pin LCC as the model
AD9300TE, which operates over a temperature range of - 5SoC
to + l2SOC.
An advanced bipolar process provides fast, wideband switching
capabilities while maintaining crosstalk rejection of 7SdB at
10MHz. Full power bandwidth is a minimum 30MHz. The
device can be operated from ± lOY to ± ISV power supplies.
ORDERING INFORMATION
Device
Temperature
Range
Description
Package
Options*
AD9300KQ
AD9300TQ
AD9300TE
AD9300KP
Oto + 70°C
- 55°C to + 125°C
- 55°C to + 125°C
Oto + 70°C
16-Pin Cerdip, Commercial
16-Pin Cerdip, Military Temperature
20-Pin LCC, Military Temperature
20-Pin PLCC, Commercial
Q-16
Q-16
E-2OA
P-20A
·See Section 14 for package outline information.
CMOS SWITCHES & MULTIPLEXERS 7-17
I
SPECIFICATIONS
ABSOLUTEMAXIMUMRATINGS 1
Supply Voltages (±Vs) . . . . .
Analog Input Voltage Each Input
(IN I thru IN4 ) • • • • • • • •
Differential Voltage Between Any Two
Inputs (INI thru IN4 ) • • • • • • • •
Digital Input Voltages (Ao, AI> ENABLE)
±16V
±3.SV
. . SV
-O.5Vto +5.5V
Output Current
Sinking . . . . . . . . . . .
Sourcing . . . . . . . . . .
Operating Temperature Range
AD9300KQ/KP . . . . . .
AD9300TQITE
Storage Temperature Range.
Junction Temperature.
Lead Soldering (1 Osec) . . .
6.OmA
6.OmA
o to +70°C
- 55°C to + 125°C
-65°C to + 150°C
+ 175°C
. . . . . +300°C
ELECTRICAL CHARACTERISTICS (±Vs = ±12V ±5%; C =10pF;R.. =2kn,unlessothelWisenoted)
L
Parameter (Conditions)
Temp
INPUT CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage
Input Offset Voltage Drift'
Input Bias Current
Input Bias Current
Input Resistance
Input Capacitance
Input NoiseVoltage(dc to8MHz)
Full
Full
+ 25"C
Full
+ 25°C
+ 25"C
+25"C
TRANSFER CHARACTERISTICS
Voltage Gain4
Voltage Gain4
DC LinearityS
GainTolerance(VIN = ± IV)
dcto 5MHz
5MHzto8MHz
Small-Signal Bandwidth
(VIN = lOOmVp-p)
Full Power Bandwidth6
(VIN = 2Vp-p)
Output Swing
Output Current (Sinking@ = 25°C)
Output Resistance
DYNAMIC CHARACTERISTICS
Slew Rate7
Settling Time
(toO.I%on ±2VOutput)
Overshoot
ToT-StepS
To Pulse9
Differential PhaselO
Differential Gain lO
Crosstalk Rejection
Three Channels II
One Channel l2
SWITCHING CHARACTERISTICS I'
Ax Input to Channel HIGH Time 14
(tHIGH)
Ax Input to Channel LOW Time ls
(t\.Ow)
Enable to Channel ON Time l6
(toN)
Enable to Channel OFF Time 17
(toFF)
Switching Transient IS
+25°C
Test
Level
COMMERCIAL
Oto +70"C
AD9300KQIKP
Min
Typ
Max
I
3
VI
V
I
75
15
VI
V
V
V
Military
SUbgroup2
iO
14
1
2,3
37
55
I
2,3
MILITARY
- 55"C to + 125"C
AD9300TQITE
Min
Typ
Max
3
.83
15
3.0
2
16
10
18
37
55
3.0
2
16
Units
mV
mV
,..VI"C
,..A
ILA
MO
pF
IL Vrms
+ 25°C
Full
+ 25°C
I
+ 25°C
+ 25°C
+ 25"C
I
I
V
+ 25°C
I
30
Full
+ 25°C
+25"C
VI
V
±2
III
+ 25°C
I
+ 25°C
III
70
+ 25°C
+ 25"C
V
V
+ 25"C
+ 25°C
III
III
<0.1
<10
0.05
0.05
+ 25°C
+ 25°C
IV
IV
+ 25°C
I
40
50
9
40
50
ns
+ 25"C
I
35
45
9
35
45
.os
+ 25°C
I
30
40
9
30
40
ns
+ 25°C
I
20
30
9
20
30
ns
+ 25°C
V
60
VI
V
7-18 CMOS SWITCHES & MUL TIPLEXERS
0.990
0.985
I
2,3
0.994
0.990
0.985
0.01
0.05
0.1
350
190
VN
VN
%
0.01
0.1
0.3
34
5
9
0.994
IS
215
4
4
4
30
1,2,3
±2
0.1
0.1
·12
12
12
70
75
78(75) 80
190
0.1
0.3
<0.1
<10
0.05
0.05
15
0
VII'S
100
ns
0.1
0.1
%
%
°
%
70
75
78(75) 80
60
dB
MHz
V
mA
215
70
dB
MHz
34
5
9
12
4
100
0.05
0.1
350
dB
dB
mV
AD9300
COMMERCIAL
Oto +700C
AD9300KQIKP
Parameter (Conditions)
DIGITAL INPUTS
Logic" I" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
POWER SUPPLY
Positive Supply Current ( + 12V)
Positive Supply Current ( + 12V)
Negative ~upply Current ( - 12V)
Negative Supply Current ( - 12V)
Power Supply Rejection Ratio
(±Vs = ± 12V ±5%)
Power Dissipstion (± 12V)19
Temp
Test
Level
Full
Full
Full
Full
VI
VI
VI
VI
+ 25·C
Full
+25"C
Full
Full
I
VI
I
VI
VI
+25"C
V
MILITARY
- SS·C to + 12S·C
AD9300TQ1TE
Military
Min
Max
Subgroup'
Min
I
1,2,3
1,2,3
1,2,3
1,2,3
2
0.8
5
13
13
16
16
I
2,3
13
13
16
16
12.5
12.5
75
IS
I
16
2,3
1,2,3
12.5
12.5
75
16
Typ
2
67
306
Typ
Max
0.8
5
I
67
306
IS
Units
V
V
",A
!l-A
rnA
rnA
rnA
rnA
dB
rnW
NOTES
For applications assistance, phone Computer Labs Division at (919) 668-9511
Ipermanent damage may occur if anyone absolute maximum rating is exceeded. Functional operation is not implied,
and device reliability may be impaired by exposure to higher-than-recommended voltages for extended periods of time.
'Military Subgroups apply to military-qualified devices only.
3Measured at extremes of temperature range.
'Measured as slope of VOUT versus V IN with V IN = ± IV.
sMeasured as worst deviation from end-point fit with VIN = ± IV.
"Full Power Bandwith (FPBW) based on Slew Rate (SR). FPBW = SRl2",VPEAK
'Measured between 20% and 80% transition points of ± IV output.
'T.Step = Sin'X Step, when Step between OV and + 700mV points bas 10%·to·9O% risetime = 12Sns.
"Measured with a pulse input having slew rate >2S0V/",s.
tOMeasured at output between 0.28Vdc and l.OVdc with VIN = 284mV p.p at 3.S8MHz and 4.43MHz.
"This specification is critically dependent on circuit layout. Value shown is measuted with selected channel grounded and IOMHz 2V p-p signal
applied to remaining three channels. If selected channel is grounded through 750, value is approximately 6dB higher.
"This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and IOMHz 2V p.p signal
applied to one other channel. If selected channel is grounded through 750, value is approximately 6dB higher. Minimum specification in ( ) applies to DIPs.
"Consult system timing diagram.
14Measured from address change to 900/0 point of - 2V to + 2V output LOW-to-HIGH transition.
"Measured from address cbange to 10% point of + 2V to - 2V output HIGH-to·LOW transition.
t"Measured from 500/0 transition point of ENABLE input to 90% transition of OV to - 2V output.
"Measured from SOOiO transition point of ENABLE input to 10% transition of + 2V to OV output.
"Measured while switching between two grounded channels.
"Maximum power dissipation is a package·dependent parameter related to the following typical thermal impedances:
16·Pin Ceramic alA = 87"CIW; a lC = 2SoC/W
20·Pin Lee
alA = 74"CIW; alc = IO°C/W
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level I
Test Level II
-
1000/0 production tested.
100% production tested at
TestLevellJl
-
Sample tested only.
Test Level IV
Test Level V
Test Level VI
-
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
All devices are 100% production tested at + 2SD C. 100% production tested at temperature extremes for
military temperature devices; sample tested at temperature extremes for commercial/industrial
devices.
+ 25"<:, and sample tested at specified temperatures.
EXPLANATION OF GROUP A MILlTARY SUBGROUPS
+ 25"C.
Subgroup I
-
Subgroup 2
Subgroup 3
Subgroup4
Subgroup 5
Subgroup 6
Subgroup 7
SubgroupS
Subgroup9
Subgroup 10
Subgroup II
Subgroup 12
-
Static tests at maximum rated temperature.
Static tests at minimum rated temperature.
Dynamic tests at + 25"C.
Dynamic tests at maximum rated temperature.
Dynamic tests at minimum rated temperature.
Functional tests at + 25°C.
Functional tests at maximum and minimum rated temperatures.
Switching teslS at + 25"C.
Switching tests at maximum rated temperature.
Switching tests at minimum rated temperature.
-
Periodically sample tested.
Static tests at
(5% PDA calculated against Subgroup I for high.rel versions)
CMOS SWITCHES & MULTIPLEXERS 7-19
•
AD9300 BURN·INDIAGRAM
SUGGESTED LAYOUT OF AD9300PCBOARD
D,
D,
S, _ _ _ _ _ _ _ _ _ _ _ _ -2.DV
D,
1kU
r-,
r-, __
DO~
L-..J
L +O.4V
GROUND
S,
IN,
GROUND
S,
IN,
BYPASS
+2.4V
--!
D,.-J
IN,
100,..
U
GROUND
l-
n n n n
2kU
GROUND
S,
GROUNO
S, _ _ _ _ _ _ _ _ _ _ _ _ +2.0V
ENABLE
INPUT
RESISTORS
II.._J
OUTPUT • • •
U
U
---+2.4V
L
+O.4V
GROUND
S,
D,-------'
O.lfiF
OPTION#1(STATIC)S, - -2.OV.S2 '" +2.0V
Og=D,= +2.4V:Da =OV
~ +1SV
OPTION #2 (DVNAMIC) SEE WAVEFORMS
GROUND
A,
ALLRESISTOAS :t 5%
ALL CAPACITORS =20%
ALLSUPPlVVOlTAGES :5%
-v.
PIN DESIGNATIONS
(Bottom View- Not to Scale)
Component Side Should be Ground Plane
DIP
METALIZATION PHOTOGRAPH
LCC
Q
Q
2
:>
2
:>
!5
1
:>
0
20
i ~ Ii!!!J
3
2
~
-
II:
~
::>
o
\
Figure 6. Test Circuit for Harmonic Distortion, Pulse
Response, T-Step Response and Disable Characteristics
\
-5
\
-10
OV--------____________- ,
\
Ov ______________--,
-15
5V ________-,
-20
10
100
1GHz
ENABLE
INPUT FREQUENCY -MHz
A,
Ao
GROUND
Figure 4. Dutput vs. Frequency
IN,
-50
GROUND
-55
.,
l' -60 r---2
B
-65
OJ
II:
-70
'"
-75
w
-'
;!
II)
II)
0
II:
I---
./
-80
(J
/
-85
-90
I.
V
---
~
/
.-~~-t---l IN2
i
CROSJTAlL
INa = INJ =IN 4 =
2V p.p SINE WAVE,\
,/
GROUND
V
AD9300
IN,
GROUND
/'
1.0
10
100
FREQUENCY-MHz
Figure 7. Crosstalk Rejection Test Circuit
Figure 5. Crosstalkvs. Frequency
:::I:v
-
I, . .
'
•=1
; ;;
---
=-
;;; ~
N'\JT
! ....
Figure 8. Pulse Response
5. . . .
.
~-.
JJ
JJ
!Uj
Jj
P . .... I~""
• OUTPUT
Figure 9. T-Step Response
Figure 10. Enable to Channel
"Off" Response
CMOS SWITCHES & MUL TIPLEXERS 7-23
II
CROSSPOINT CIRCUIT APPLICATIONS
Four AD9300 multiplexers can be used to implement an 8 x 2
crosspoint, as shown in Figure 11. The circuit is modular in
concept, with each pair of multiplexers (#1 and #2; #3 and
#4) forming an 8 x I crosspoint. When the inputs to all four
units are connected as shown, the result is an 8 x 2 crosspoint
circuit.
D2
or
Ds
Dl
or
D4
Do
or
D3
OUT1
or
OUT2
0
0
0
0
I
I
I
I
0
0
I
1
0
0
I
I
0
I
0
I
0
I
0
I
SI
S2
S3
S4
Ss
S6
S7
S8
The truth table describes the relationships among the digital
inputs (Do - Ds) and the analog inputs (SI - S8); and which
signal input is selected at the outputs (OUT I and OUT2 ). The
number of crosspoint modules that can be connected in parallel
is limited by the drive capabilities of the input signal sources.
High input impedance (3Mfl) and low input capacitance (2pF)
of the AD9300 help minimize this limitation.
Adding to the number of inputs applied to each crosspoint
module is simply a matter of adding AD9300 multiplexers in
parallel to the module. Eight devices connected in parallel result
in a 32 x I crosspoint which can be used with input signals
having 30MHz bandwidth and IV peak-to-peak amplitude.
Even more AD9300 units can be added if input signal amplitude
and/or bandwidth are reduced; if they are not, distortion of the
output signals can result.
When an AD9300 is enabled, its low output impedance causes
the "off' isolation of disabled parallel devices to be greater than
the crosstalk rejection of a single unit. .
8 x 2 Crosspoint Truth Table
D.
0,
......
D.
I
E
5,
I I
A,
IN,
IN.
IN.
IN.
S.
5,
54
Ao
OUT f#1
.-0 OUT,
I I
E
IN,
S.
S.
57
S.
A,
IN.
IN,
IN.
0,
04
D.
.....
v
I
E
A.
OUT
-
#2
1
A,
IN,
IN.
IN.
IN.
J
A.
OUT
-
#3
~ OUT.
I I
E
A,
Ao
IN,
IN.
IN.
IN.
OUT
>-
#4
8 X 2 SIGNAL CROSSPOINT USING FOUR AD9300 MULTIPLEXERS
Figure 11. 8 x 2 Signal Crosspoint Using Four AD9300
Multiplexers
7-24 CMOS SWITCHES & MUL TIPLEXERS
CMOS
Quad SPST Switches
ADG201A1ADG202A I
1IIIIIIII ANALOG
WDEVICES
FEATURES
44V Supply Maximum Rating
:f: 15V Analog Signal Range
Low RON (60.0)
Low Leakage (0.5nA)
Extended Plastic Temperature Range
( - 4O"C to + 85"C)
Low Power Dissipation (33mW)
Standard 16-Pin Dips and 20-Terminal
Surface Mount Packages
Superior Second Source:
ADG201A Replaces DG201A. HI-201
ADG202A Replaces DG202
ADG201AlADG202A FUNCTIONAL BLOCK DIAGRAM
ADG202A
S,
5'
IN'
IN'
D'
D'
52
IN2
52
IN2
D2
D2
53
53
IN3
IN3
D3
D3
54
54
IN4
IN4
D4
D4
SWITCHES SHOWN FOR A LOGIC "'"INPUT
GENERAL DESCRIPTION
The ADG201A and ADG202A are monolithic CMOS devices
comprising four independently selectable switches. They are
designed on an enhanced LC2MOS process which gives an increased signal handling capability of ± 1SV. These switches also
feature high switching speeds and low RoN.
The ADG20lA and ADG20ZA consist of four SPST switches.
They differ only in that the digital control logic is inverted. All
devices exhibit break before make switching action. Inherent in
the design is low charge injection for minimum transients when
switching the digital inputs.
ORDERING INFORMATION 1
Temperature Range and Package Options 2, 3
-400Cto +SS·C
-40·Cto +S5·C
-55·Cto +125·C
Plastic DIP (N-16)
Hermetic (Q-16)
Hermetic (Q-16)
ADG201AKN
ADG202AKN
ADG20lABQ
ADG202ABQ
ADG201ATQ
ADG202ATQ
PLCC4 (P-20A)
ADG201AKP
ADG202AKP
LCCC 5 (E-20A)
ADG201ATE
ADG202ATE
PRODUCT HIGHLIGHTS
1. Extended Signal Range:
These switches are fabricated on an enhanced LC2 MOS
process, resulting in high breakdown and an increased analog
signal range of ± 1SV.
2. Single Supply Operation:
For applications where the. analog signal is unipolar (OV to
lSV), the switches can be operated from a single + lSV
supply.
3. Low Leakage:
Leakage currents in the range of SOOpA make these switches
suitable for high precision circuits. The added feature of
Break before Make allows for multiple: outputs to be tied
together for multiplexer applications while keeping leakage
errors to a minimum.
ADG20IA
IN
o
1
ADG202A
IN
SWITCH
CONDmON
1
ON
o
OFF
Table I. Truth Table
NOTES
ITo order MIL·STD·883, Class B processed parts, add/883B to part
number. See Analog Devices Military Products Data Book (1987) for
military data sheet.
2See Section 14 for package outline information.
'Also available in SOIC packages (ADG20IAKR, ADG202AKR)
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
CMOS SWITCHES & MUL TIPLEXERS 7-25
II
SPECIFICATIONS
(VIII =
+ 15V. Vss= -15V. unless otheIwise Il0lIIII)
KVersion
BVersion
-4O"<:to
2S'C
+8S·C
TVersion
-SS'Cto
2S'C
+12S"C
:!: 15
:!: 15
60
:!: 15
:!: 15
60
±15
145
90
145
90
145
-40"<: to
Parameter
2S'C
+8S·C
ANALOG SWITCH
Analog Signal Range
RoN
± 15
60
90
Units
Test Conditions
Volts
Otyp
o max
-IOV .. Vs .. +IOV
los= 1.0mA
Test Circuit I
RONvs. Vo(V s)
RoN Drift
RoN Match
20
0.5
5
20
0.5
5
20
0.5
5
%typ
%/"Ctyp
%typ
Is (OFF)
OFF Input Leakage
0.5
2
100
0.5
I
100
nAtyp
nAmax
Vo= :!: 14V; Vs + 14V; Test Circuit 2
100
0.5
2
10 (OFF)
0.5
2
100
0.5
I
100
nAtyp
nAmax
Vo=:!: 14V; Vs= + 14V; Test Circuit 2
100
0.5
2
0.5
2
0.5
2
200
0.5
I
200
nAtyp
nAmax
Vo = ± 14V; Test Circuit 3
200
2.4
0.8
I
V min
V max
",A max
OFF Output Leakage
10 (ON)
ON Channel Leakage
DIGITAL CONTROL
VINH, Input High Voltage
V;:NL, Input Low Voltage
2.4
2.4
0.8
0.8
1
I
IINLor IINH
Vs=OV,los= ImA
DYNAMIC CHARACTERISTICS
OFF Isolation
30
300
250
80
30
300
250
80
30
300
250
80
nstyp
nsmax
l1:smax
dBtyp
Channel-to-Channel Crosstalk
Cs(OFF)
Co (OFF)
Co,Cs(ON)
CIN Digital Input Capacitance
QINJ Charge Injection
80
5
5
16
5
20
80
5
5
16
5
20
80
5
5
16
5
20
dBtyp
pFtyp
pFtyp
pFtyp
pFtyp
pCtyp
IoPEN
ioN'
IoFF
,
Test Circuit 4
Test Circuit 4
Vs= IOV(p-p);f= 100kHz
RL = 750; Test Circuit 6
Test Circuit 7
Rs=OO;Ct.=IOOOpF;Vs=OV
Test Circuit 5
POWER SUPPLY
0.6
100
0.6
0.1
Iss
Iss
Power Dissipation
0.6
2
2
100
2
0.1
0.2
33
0.1
0.2
33
0.2
33
mAtyp
mAmax
mAtyp
mAmax
mWmax
Digital Inputs = V INt. or V INH
NOTES
'Sample teseed at 25°C to ensure compliance.
Specifications subject to change without notice.
PIN CONFIGURATIONS
DIP
LCCC
E
•
IN2
iii "z ~ S
2
02
S2
V..
NC
SI <
1
..L.
20
,.
NC •
7-26 CMOS SWITCHES & MUL TIPLEXERS
2.
s
,.
0
S2
15 Ne
14 S3
S4
10 11 12 I.
= NO CONNECT
~
1
16 NC
S< •
NC
"z
2
ADG201A
ADG202A
TOP VIEW
tNot to Scale)
03
0
iii
•
17 VDD
(Not to Scale)
1! ~ !Il !E
E
18 82
ADG201A
ADG202A
TOP VIEW
V.. 5
GND 7
S3
PLCC
Nt
NC
NC
•
S3
12
13
1! ~ !Il !E
s
0
s
v••
= NO CONNECT
I.
11
ADG201 AlADG202A
ABSOLUTE MAXIMUM RATINGS·
(TA = + 25°C unless otherwise stated)
. 44V
. 25V
-25V
Voo to Vss .
Voo to GND
Vss to GND .
Analog Inputs·
Voltage at S, D
Vss -O.3V to
Voo +O.3V
30mA
Continuous Current, S or D
Pulsed Current S or D
Ims Duration, 10% Duty Cycle
Digital Inputs·
Voltage at IN . . . . . . . .
70mA
Vss -2V to
Voo +2Vor
20mA, Whichever Occurs First
Power Dissipation (Any Package)
Up to +75°C . . . . . . .
Derates above + 75°C by
Operating Temperature
Commercial (K Version)
Industrial (B Version) . .
Extended (T Version) . .
Storage Temperature Range .
Lead Temperature (Soldering JOsec)
470mW
6mWI"C
-40°C to +85°C
-40°C to +85°C
- 55°C to + 125°C
- 65°C to + 150°C
. . . .. +300°C
NOTE
'Overvoltageat IN, S or D will be clamped by diodes. Current should be
limited to the Maximum Rating above.
·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is nor implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at
anyone time.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~D'ViCE
Typical Performance Characteristics and Test Circuits
The switc:hes are guaranteed functional with reduc:ed single or dual supplies down to 4.SV.
..
,
V~'+~~I\
v... -sv
'20
1mA
TA",\aoc
---
~
\
=90
..
..
-20
1-·;---V1--~"-1
Voo",+10.8V
V.. "'-10~
V"
"'--" VAT15V
-15
-10
Vs
.+5
-5
....-f~s~
~ ""-
VDD =+15V
+10
.+15
~
D
RON=V1/1mA
+20
VD IVel - Volts
RON as a Function of Va (Vs): Dual Supply Voltage
Test Circuit 1
'50
T,,-+2!rC
'20
v~,+,o.~/~
V"i ov
vool
v.. =ov
..
+15V
1\
V' ~ ~
3D
Test Circuit 2
o
-20
-15
-10
-5
+5
+10
+15
+20
VD(V.i-VDIts
RON as a Function of Va (Vs): Single Supply Voltage
CMOS SWITCHES & MUL TIPLEXERS 7-27
•
Typical Performance Characteristics and Test Circuits Cont'd
..
,
,/'
V
,/"
V
Yoo. +16.6V
V.. =-16.5V
,,/
"''':''
/v,.
vV
D.'
VV
a
H
,,//
(0fFI.1o (OFF,
,/'
/'" V
,,/
s
D
">
,/"
G
•
-
•
~
§
M
~
m
m
Test Circuit 3
TEMPERATURE _ '"C
Leakage Current as a Function of Temperature (Note:
Leakage Currents Reduce as the Supply Voltages Reduce)
+15V
3V
ADG201A7\
Y,N ~ 50%
1
11 50%
i'------.....J,
3vl
~
V,:v !/. 50%
1, 50%
ADG202A~,
,,.
Vo
:f
'!I
90%
--I toN l--
:
\90%
,l'---
--I to.. j--
Test Circuit 4
+15V
,.------,
:
Rs '
,
I
5V
V DD
~
~~: f--~
'"
VIN
-L
~.1Vo
Jl
QINJ=CL x.1VO
+--
Test Circuit 5. Charge Injection
+15V
VDD
~--=-------~~~)~~~D+--_----~-_-__
-~t-__<)Vo
--V----
RL
750
ADG201A V,N =5V
ADG20ZA V,N=OV
Test Circuit 6. Off Isolation
7-28 CMOS SWITCHES & MUL TIPLEXERS
OFF ISOLATION
20 xLOG IVsNol
=
ADG201A V'N=OV
ADG20ZA V'N=5V
CHANNELISOLATION =
20 x LOG iVslVoI
Test Circuit 7. Channel to Channel/so/ation
LC 2MOS
High Speed, Quad SPST Switch
FIlII ANALOG
WDEVICES
ADG201HS I
FEATURES
SOns max Switching Time Over Full Temperature
Range
Low RON (30n typ)
Single Supply Specifications for + 10.8V to
+ 16.SV Operation
Extended Plastic Temperature Range
(-40·C to +8S·C)
Break-Before-Make Switching
Low Leakage (100pA typ)
44V Supply max Rating
ADG201HS (K,B,T) Replaces HI-201HS
ADG201HS (J,A,S) Replaces DG271
ADG201HS FUNCTIONAL BLOCK DIAGRAM
S1
IN1
01
S2
IN2
02
S3
IN3
D3
54
IN4
04
GENERAL DESCRIPTION
The ADG20lHS is a monolithic CMOS device comprising four
independently selectable SPST switches. It is designed on an
enhanced LC2 MOS process which gives very fast switching
speeds and low RON.
The switches also feature break-before-make switching action
for use in multiplexer applications and low charge injection for
minimum transients on the output when switching the digital
inputs.
ORDERING INFORMATION l
Temperature Range and Package Options2, 3
-40·Cto
+ 85·C
-40·Cto
+ 85·C
Plastic DIP (N-16) Hermetic (Q-16)
ADG20lHS}N
ADG20lHSKN
PLCC4 (P-20A)
ADG20lHS}P
ADG20lHSKP
ADG20lHSAQ
ADG20lHSBQ
-55·Cto
+125·C
Hermetic (Q-16)
ADG20lHSSQ
ADG20lHSTQ
LCCCs (E-20A)
ADG20lHSTE
PRODUCT HIGHLIGHTS
1. SOns max tON and tOFF:
The ADG20lHS top grades (K, B, T) have guaranteed SOns
max turn-on and turn-off times over the full operating temperature range. The lower grades (J ,A,S) have guaranteed
7Sns switching times over the full operating temperature
range.
2. Single Supply Specifications:
The ADG20lHS is fully specified for applications which
require a single positive power supply in the + IO.8V to
+ l6.SV range.
3. Low Leakage:
Leakage currents in the range of IOOpA make these switches
suitable for high precision circuits. The added feature of
break-before-make allows for multiple outputs to be tied
together for mUltiplexer applications while keeping leakage
errors to a minimum.
IN
0
1
NOTES
'To order MIL·STD-883, Class B processed parts, add /883B to T grade part
nwnbers. Contact your local sales office for military data sheet. For U.S.
Standard Military Drawing (SMD), see DESC drawing 5962-86716.
'See Section 14 for package outline information.
3Also available in SOIC package (ADG201HSKR).
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
Switch
Condition
ON
OFF
Truth Table
CMOS SWITCHES & MUL TIPLEXERS 7-29
7
SP~CIFICATIONS
Dual Supply
+ 13.5Y1D + 16.5V,Vss = -13.5Y1D -16.5Y,GMD = DV,
VII = 3V (Logic High Level) or D.8V (logic Low Level) unless otherwise noIad)
(VIII=
Parameter
ANALOG SWITCH
Analog Signal Range
Version
+2S"C
T_-T....1
Unita
All
All
Vss
Voo
Vss
Voo
Vmin
V max
AU
All
AU
AU
30
50
0.5
3
75
o max
AU
J,K,A,B
S,T
AU
J,K,A,B
S,T
All
J,K,A,B
s;r
0.1
I
I
0.1
I
I
0.1
I
I
All
All
AU
AU
Commenta
Otyp
-IOV",Vs '" + 10V,Ios= ImA; Test Circuit I
%l"Ctyp
%typ
-IOV",Vs'" + IOV,Ios= lmA
-IOV",Vs '" + IOV,Ios= lmA
Vo=:!: 14V;Vs= :;:14V;TestCircuit2
20
60
nAtyp
nAmax
nAmax
nAtyp
nAmax
nAmax
nAtyp
nAmax
nAmax
2.4
0.8
I
8
2.4
0.8
I
8
V min
V max
.,.Amax
pFmax
50
75
50
75
150
5
180
72
50
75
50
75
toPEN
Output Settling Time to 0.1 %
OFF Isolation
K,B,T
J,A,S
K,B,T
J,A,S
All
All
AU
AU
nsmax
nsmax
nsmax
nsmax
nstyp
nstyp
nstyp
dBtyp
Channel-to-Channel Crosstalk
AU
86
dBtyp
QINJ, Charge Injection
Cs(OFF)
Co (OFF)
Co,Cs(ON)
Cos (OFF)
All
All
All
All
AU
10
10
30
0.5
pCtyp
pFtyp
pFtyp
pFtyp
pFtyp
All
All
10
6
10
6
mAmax
mAmax
AU
240
240
mWmax
RoN
RoN Drift
RoN Match
Is (OFF), Off Input Leakage2
I o (OFF),OffOutputLeakage2
10 (ON), On Channel Leakage2
DIGITAL CONTROL
VINH, Input High Voltage
VINI., Input Low Voltage
IINLor IINH
CIN
20
60
20
60
Vo=:!: 14V;Vs= :;: 14V; Test Circuit 2
Vo=:!: 14V; Test Circuit 3
DYNAMIC CHARACTERISTICS
toN
toFF'
toFF2
5
10
Test Circuit 4
Test Circuit 4
Test Circuit 4
to..-toFF'; Test Circuit 4
VIN = 3V toOV; Test Circuit 4
Vs =3Vrms,f= 100kHz,RL = IkO;
CL = IOpF; Test Circuit 5
Vs = 3V fms, f = 100kHz, RL = IkO;
C L = IOpF; Test Circuit 6
Rs = 00, V s = OV; Test Circuit 7
POWER SUPPLY
100
Iss
Power Dissipation
Voo =
+ 15V, Vss = -15V
NOTES
'Temperature ranges ore as follows: ADG20IHSJ.K; -4O"Cto +85"C
ADG20IHSA,e; -4O"Cto +85"C
ADG20IHSS. T; - 55"C to + 125"C
2Leakage specifICations apply with a VD (V5)of ± 14V or with aVo (V5) ofO.5V within [he supply Voltages (V DO, V55), whichever is the minimum.
Specifications suhlect to change without notice.
7-30 CMOS SWITCHES & MUL TIPLEXERS
ADG201HS
Single Supply
(VIII
=+ IO.av to + 16.5V, Vss =GND = oy, VIN =3Y [logic High Level] or D.av [Logic Low Level] unless otherwise noted)
Version
+250(;
T_-T....
Units
All
All
Vss
Voo
Vss
Voo
Vmin
V max
All
All
All
All
65
90
0.5
3
All
J,K,A,B
S,T
All
J,K,A,B
S,T
All
J,K,A,B
S,T
0.1
1
1
0.1
1
1
0.1
1
1
20
60
nAtyp
nAmax
nAmax
nAtyp
nAmax
nAmax
nAtyp
nAmax
nAmax
All
All
All
All
2.4
0.8
1
8
2.4
0.8
1
8
V min
V max
fl-Amax
pFmax
50
75
50
75
ISO
5
180
72
70
90
70
90
Output Settling Time toO.I%
OFF Isolation
K,B,T
J,A,S
K,B,T
J,A,S
All
All
All
All
nsmax
nsmax
nsmax
nsmax
nstyp
nstyp
nstyp
dBtyp
Channel-ta-Channel Crosstalk
All
86
dBtyp
QIN}, Charge Injection
Cs(OFF)
Co (OFF)
Co, Cs (ON)
Cos (OFF)
All
All
All
All
All
10
10
10
30
0.5
pCtyp
pFtyp
pFtyp
pFtyp
pFtyp
Parameter
ANALOG SWITCH
Analog Signal Range
RoN
RoN Drift
RoN Match
Is (OFF), Off Input Leakage'
10 (OFF), Off Output Leakage'
10 (ON), On Channel Leakage'
DIGITAL CONTROL
VINH , Input High Voltage
VINI., Input Low Voltage
IIN.. OrlINH
CIN
120
20
60
20
60
fltyp
flmax
%I"Ctyp
%typ
Comments
OV "'vs'" + IOV, los = ImA; Test Circuit I
OV",Vs'" + IOV, Ios= ImA
OV",Vs'" + IOV,Ios= ImA
Vo= + IOV/+0.5V;Vs = +0.5V/+ 10V; Test Circuit 2
Vo= + IOVI+ O.5V; Vs= +O.5V/+ 10V; Test Circuit 2
Vo= + 10V/+ O.5V; Test Circuit 3
DYNAMIC CHARACTERISTICS
toN
tOFFI
tOFF2
tOPEN
POWER SUPPLY
100
Power Dissipation
All
10
10
mAmax
All
ISO
ISO
mWmax
Test Circuil 4
Test Circuit 4
Test Circuit 4
to,.-tOFF'; Test Circuit 4
VIN = 3VtoOV; Test Circuit 4
Vs= 3V rms, f= 100kHz, R.. = Ikfl;
C.. = IOpF; Test Circuit 5
Vs =3Vrms,f= lOOkHz,R.. = IkO;
CL = IOpF; Test Circuit 6
Rs=Ofl, Vs=OV; Test Circuit 7
Voo= +15V
NOTE
'The leakage specifications degrade marginally (typically InA at 2S'C) with VD (Vs) = V.s.
Specifications subject to cbange without notice.
CMOS SWITCHES & MUL T1PLEXERS 7-31
ABSOLUTE MAXIMUM RATINGS·
(TA = 25°C unless otherwise noted)
Power Dissipation (Any Package)
Up to +7SoC . . . . . .
Derates above + 75°C by
Operating Temperature
Cornmerical (1, K Version)
Industrial (A, B Version) .
Extended (S, T Version) .
Storage Temperature Range .
Lead Temperature (Soldering !Osee)
. . . . . 44V
. -0.3V,2SV
+0.3V, -2SV
Voo to Vss .
Voo to GND
Vss to GNDI
Analog Inputs 2
Voltage at S, D
. . . . . . . . . . Vss -2V to
Voo +2Vor
2OrnA, Whichever Occurs First
. . . . . . . . . . 20rnA
Continuous Current, S or D
Pulsed Current S or D
Ims Duration, 10% Duty Cycle . . . . . . .
70rnA
Digital Inputs2
Voltage at IN . . . . . . . . . . . . . . . . . . Vss -4V to
VoD +4Vor
20mA, Whichever Occurs First
470mW
6mW/oC
- 40°C to + 85°C
- 40°C to + 85°C
- 55°C to + 125°C
-65°C to + 150°C
. . . . . +300°C
NOTES
'If V ss is open circuited with V DD and GND applied, the Vss pin will he pulled
positive, exceeding the Absolute Maximum Ratings. If this possibility exists,
a Schottky diode from V ss to GND (cathode end to GND) ensures that the
Absolute Maximum Ratings will be observed.
'Overvoltage at IN, S or D, will be clamped by diodes. Current
should be limited to the maximum rating above.
·COMMENT: Stresses above those listed under U Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
.....-1
~'~
li"=fTTl' ~
:sIO'
DEVICE
PIN CONFIGURATIONS
DIP
Q ~ ~
3
IN1
IN2
01
02
S1 4
S1
S2
Vos 5
Vss
GNO
PLCC
LCCC
ADG201HS
Voo
TOP VIEW
(Not to Scale)
NC
S4
S3
D4
03
IN4
IN3
2
1
! s
20 19
,,
',
18 S2
L ..
NC 6
16 NC
TOP VIEW
(Not to Scale)
GNO 7
15 NC
14 S3
548
Voo
Vss
ADG201HS
NC
NC
TOP VIEW
(Not to S.ale)
GND
NC
S3
S4
9
10 11 12 13
! i
~ ~
a
NC = NO CONNECT
NC
52
S1
17 Voo
ADG201HS
= NO CONNECT
7-32 CMOS SWITCHES & MUL TIPLEXERS
~
NC
i
= NO CONNECT
~
~
S
Typical Performance Characteristics - ADG201 HS
The switches are guaranteed functional with reduced single or dual supplies down to 4.SV.
80
0
70
70
VOD = +15V
Vss = -1SV
60
/\
1/
50
V
/ '~
"-...
0
~
0
A 1\
\
Voo = +sv
Vss = -5V
60
~
"-...
20
;"'? " ~~DD=
+'~
Vss == -'O.8V
}
r-
.......
",,- i----
,/
, 40
125°C
0
25"C
Voo
Vss
20
55°C
~
= +13.5V
= -13.5V
~
~
0
0
o
-20
-15
-10
-5
0
VD IVs' - Volts
0
-20
20
15
10
-15
-10
-5
15
10
0
20
Vo (Vs) - Volts
RON as a Function of Va (Vs): Dual Supply Voltage
RON as a Function of Va (Vs): Dual Supply Voltage,
TA = +25°C
100
80
I
J
Vao = +16.5V
Vss
70
60
VDD
VSS
= + 10.8V
=0
50
VDD = +15V
Vss == 0
~40
A
I 1\\,V\
......-:::
I. (OFfI
10 ( 0 %
/\ f.-../ ~'\..
.....-':/""
}
30
o. I
20
V/
V
10
o
-20
-15
-10
= -16.5V
-5
10
15
25
20
".-:: ~
::-l:/
~~
V((ONI
V
,/
35
45
55
Vo IVsl- Votts
65
75
85
95
105
115
125
TEMPERATURE - "C
RON as a Function of Va (Vs): Single Supply Voltage,
TA = +25°C
Leakage Current as a Function of Temperature Dual
Supply Voltage. (Note: Leakage Currents Reduce as
the Supply Voltages Reduce)
120
1.8
100
1.7
&I
",
z
~
/
I---I---
-
t--
80
~
60
I!i
40
r---..
1--.......1---I'-..
..............
~
...
!!!
1.4
~=100f!
~
20
1.3
5
8
9
10
l'
12
SUPPLY VOLTAGE - Voh.
13
'4
15
Trigger Levels vs. Power Supply Voltage, Dual or Single
Supply, TA = + 25°C
o
10k
lOOk
1M
10M
FREQUENCV - Hz
Off Isolation vs. Signal Frequency; Dual or Single 15V
Supplies, TA = + 25°C
CMOS SWITCHES & MUL TIPLEXERS 7-33
•
Typical Performance Characteristics (Continued)
,.0
'60
'40
'40
to",
'20
"'"- t---
tOFF2
'20
'00
.~
~
I
60
j
40
t::-...
60
-----
40
to..
tOR"
20
20
10
11
12
SUPPLY VOLTAGE - Volts
13
14
t--
9
10
11
12
SUPPLY VOLTAGE - Volts
,.
'40f---r--f--f--+-+-+--+--+--l
'40
0
VDO
Vss
15
+10.8V
-
= ov
tOFF2
120
~'OOf---+--f--+--+-+-+--+--+--l
14
Switching Time vs. Supply Voltage (Single Supply):
T.4 = + 25°C. (Note: See Test Circuit 4.
For Voo <10V, Vs = Voo)
,.O'r--..--,--,---....--r--.---,----,.---,
Vuo = +15V
Vss = -15V
13
B
15
Switching Time vs. Supply Voltage (Dual Supply):
TA = +25°C. (Note: See Test Circuit 4.
For Voo <10V, Vs = Voo)
tON
tOFF1
0
~
~ 6O~-+--~--+-~--~--+---~-+~
j
6Or--+--+--+--~--r--r--+--+-~
toN
0
20f---+--+--+--4--+-+--1---+--4
-55
35
-15
5
Z5
65
45
85
105
125
0
- 55 - 35
Voo = +10.8V
VSS = -to.8V
20
;'
0
V
0
./
0
-30
85
'05
'25
TEMPERATURE - 'C
Switching Time vs. Temperature: Single Supply Voltage
.... /
./
./
V
V
V
V
0
V
V
Voo
VSS
0
../vVssoo == ov+1D,8V_
0
-3
°v
-15V lL
,/
/
V
./
/"
0
/
/'
V
= +15V
=
L
0
V
V
L
0
~VDD ==
Vss
+15V
= ov
-
1 1
-40
-40
-10
5254565
0
0
I
'5
50
0
'a
r--
0
TEMPERATURE - 'C
Switching Time vs. Temperature: Dual Supply Voltage
t:---- f---
tOFF'
-8
-6
-4
-2
0
4
SOURCE VOLTAGE (V.I- Volts
'0
Charge Injection vs. Source Voltage (Vs) for Dual and
Single 10.8V Supplies: TA = +25°C
7-34 CMOS SWITCHES & MUL TIPLEXERS
-10
-8
-.
-4
-2
0
2
4
SOURCE VOLTAGE (V.I- Volts
'0
Charge Injection vs. Source Voltage (Vs) for Dual and
Single 15V Supplies: TA = +25°C
Test Circuits - ADG201 HS
Note: All digital input signal rise and fall times measured from 10% to 90% of 3V. tR = tF = 5ns. Decoupling capacitors (O.OlILF
min) from Voo and Vss to GND are recommended to achieve specified perfornrance.
TEST CIRCUIT 1
RON
-
TEST CIRCUIT 2
Is (OFF), 10 (OFF)
los
•
TEST CIRCUIT 3
ID(ON)
Voo
V1
Voo
Voo
Voo
S
0
I
Voo
S
IN
~
O.SV
RON
=~
os
Voo
TEST CIRCUIT 4
tON, tOFF, £OPEN, SETTLING TIME
3V
Voo
~_0_%_ _ _ _...Ji50%
V'N - : \....
Vo
10V
1~_...1
0
L-
Vs-=-
O.SV
I
I
~
35pF
Vo
t
I
I
....toFF',_
1'90%
90%
~
- - - ,---II
I
~tOFF214-
- I tON ~
TEST CIRCUIT 6
CHANNEL-TO-CHANNEL CROSSTALK
TEST CIRCUIT 5
OFF ISOLATION
Vo
Voo
Voo
S
OFF ISOLATION
20 x LOGIVs/Vol
=
TEST CIRCUIT 7
CHARGE INJECTION
Voo
Vo
CMOS SWITCHES & MUL TIPLEXERS 7-35
•
SINGLE SUPPLY DISK DRIVE APPLICATION
The excellent performance of the ADG201HS with single supply
operation makes it suitable in applications such as disk drives
where only positive power supply voltages are normally available.
The accompanying circuit shows a typical application for the
ADG20lHS in the read/write head switching section of a disk
drive. The circuit allows data (Os and Is) to be written to and
read from a disk. The principal advantage offered by the
ADG20lHS is that it retains very fast switching speed with
single supply operation (see Single Supply Specifications). This
allows disk drives to run at higher data rates.
.... -, r----- -------,
WRITE
PATH
12V-....;-.;..'....V.iY
I~/
READ
PATH
r-
-+
I
---..,...o-r
OV
I ....- co-......
I
_ _ ...J L _ _ _ _ _ _ _ _ _ _ _ _ _ J
L.. _ _
SWITCHES 1 TO 5 ALL ADG201.HS
SWITCH STATES/FUNCTION
SWITCH
WRITE
'0"
'1"
READ
NUMBER
1
OFF ON
OFF
ON
OFF
OFF
2
OFF OFF ON
3
4
OFF OFF
ON
5
ION
ON 1 OFF
ADG201HS in the ReadlWrite Head Switching Circuit of a
Disk Drive
7-36 CMOS SWITCHES & MUL TIPLEXERS
LC2MOS
Quad SPST Switches
ADG211 AIADG212A I
1IIIIIIII ANALOG
WDEVICES
ADG211A1ADG212A FUNCTIONAL BLOCK DIAGRAMS
FEATURES
44V Supply Maximum Rating
± 15V Analog Signal Range
low RON (115fl max)
low leakage (O.5nA typ)
Single Supply Operation Possible
Extended Plastic Temperature Range
( - 40°C to + 85°C)
TTUCMOS Compatible
Standard 16-Pin DIPs and 20-Terminal
PlCC Packages
Superior Second Source:
ADG211A Replaces DG211
ADG212A Replaces DG212
ADG211A
51
51
INI
INI
01
01
52
S2
IN2
IN2
02
02
53
53
IN3
IN3
03
03
54
54
IN4
IN4
04
04
SWITCHES SHOWN FOR A LOGIC "I" INPUT
GENERAL DESCRIPTION
The ADG211A and ADG212A are monolithic CMOS devices
comprising four independently selectable switches. They are
designed on an enhanced LC2 MOS process which gives an increased signal handling capability of ± I SV. These switches also
feature high switching speeds and low RoN.
The ADG2JlA and ADG212A consist of four SPST switches.
They differ only in that the digital control logic is inverted. In
multiplexer applications, all switches exhibit break-before-make
switching action when driven simultaneously. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
ORDERING INFORMATION
Temperature Range and Package1,
PRODUCT HIGHLIGHTS
1. Extended Signal Range:
These switches are fabricated on an enhanced LC 2MOS
process, resulting in high breakdown and an increased analog
signal range of ± I SV.
2. Single Supply Operation:
For applications where the analog signal is unipolar (OV to
ISV), the switches can be operated from a single + lSV
supply.
3. Low Leakage:
Leakage currents in the range of 500pA make these switches
suitable for high precision circuits. The added feature of
Break before Make allows for multiple outputs to be tied
together for multiplexer applications while keeping leakage
errors to a minimum.
2
Plastic DIP (N-16)
-40°C to + 85°C
PLCC3 (P-20A)
- 40°C to + 85°C
ADG211AKN
ADG212AKN
ADG211AKP
ADG212AKP
NOTE
1See Section 14 for package outline information.
'Also available in SOIC packages (ADG211AKR, ADG212AKR).
'PLCC: Plastic Leaded Chip Carrier.
ADG211A
IN
o
ADG212A
IN
SWITCH
CONDITION
I
ON
OFF
o
Table I. Truth Table
CMOS SWITCHES & MUL TlPLEXERS 7-37
•
SPEC IFI CAli ONS
(Villi =
+ 15V. Vss= -15V. VL =5V. unless oIhlllWise noted)
KVersion
Parameter
25"C
-4OOCto +85"C
Units
ANALOG SWITCH
Analog Signal Range
RoN
±IS
115
±IS
175
Volts
Omax
RoNVS. Vo(Vs)
RoN Drift
RoN Match
20
0.5
5
Is (OFF)
OFF Input Leakage
0.5
5
10 (OFF)
OFF Output Leakage
0.5
5
10 (ON)
ON Channel Leakage
0.5
5
.,
Test Conditions
-IOV",V s '" + 10V, los = lmA,
Test Circuit I
%typ
%/"Ctyp
%typ
Vs=OV, los = lmA
Vo= ± 14V; Vs + 14V; Test Circuit 2
100
nAtyp
nAmax
nAtyp
nAmax
Vo= ±14V;Vs =+14V;TestCircuit2
100
nAtyp
nAmax
Vo = ± 14V; Test Circuit 3
200
TTL Compatibility is Independent of V L
5
V min
V max
!1Amax
pFtyp
OFF Isolation
30
600
450
80
nstyp
nsmax
nsmax
dBtyp
Channel-to-Channel Crosstalk
Cs(OFF)
CD (OFF)
Cs,Co(ON)
QINJ' Charge Injection
80
5
5
16
20
dBtyp
pFtyp
pFtyp
pFtyp
pCtyp
Test Circuit 4
Test Circuit 5
Test Circuit 5
Vs= 10V(p-p);f= 100kHz
RL = 750; Test Circuit 6
Test Circuit 7
0.6
I
0.1
0.2
0.9
mAtyp
mAmax
mAtyp
mAmax
mAmax
DIGITAL CONTROL
VINH, Input High Voltage
VINL , Input Low Voltage
IINLorIINH
CIN, Digital Input Capacitance
2.4
0.8
I
DYNAMIC CHARACTERISTICS
toPEN
tON
1
1
toFF
1
Rs=OO;CL=IOOOpF;Vs=OV
Test Circuit 8
POWER SUPPLY
100
100
Iss
Iss
IL
Digital Inputs = VINL or VINH
NOTE
'Sample tested at 2S"C to ensure compliance.
SpecifICations subject to change without notice.
PIN CONFIGURATIONS
DIP
PLCC
18
ADG211A
ADG212A
TOP VIEW
(Not to Scale)
g ~ ~ ~
NC ... NO CONNECT
7-38 CMOS SWITCHES & MUL TIPLEXERS
a
so
ADG211 AlADG212A
ABSOLUTE MAXIMUM RATINGS*
Digital Inputs'
Voltage at IN
(TA = 25°C unless otherwise stated)
Vnn to Vss .
. 44V
Vnn to GND
. 25V
Vss to GND .
-25V
VL to GND .
:"'0.3V,25V
Analog Inputs'
Voltage at S, D
Vss -0.3V to Vnn +O.3V
Continuous Current, S or D
30mA
Pulsed Current S or D
1ms Duration, 10% Duty Cycle
70rnA
. . . . . . . . . . Vss -2V to
Vnn +2Vor
20rnA, Whichever Occurs First
Power Dissipation (Any Package)
Up to +75°C . . . . . .
Derates above + 75°C by .
Operating Temperature . . .
Storage Temperature Range .
Lead Temperature (Soldering 10sec)
· . . . . 470mW
· . . . . 6mWfOC
- 40°C to + 85°C
-65°C to + 150·C
· . . . . +300·C
NOTE
'Overvoltage at IN, S or D will be clamped by diodes. Current should be
limited to the Maximum Rating above.
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is. stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifICation is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may
be applied at anyone time.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
~
~~:::
Typical Performance Characteristics
The switches can comfortably operate and are TTL compatible anywhere in the 10V
to lSV single or dual supply range, with only a slight degradation in performance.
The following graphs show some relevant performance curves. The test circuit is
given in the following section, "Test Circuits."
150
150
VDD =15V
Voo=15V
Vss='O
Vss ,,-,-1SV
c:
,
120
120
90
--: 90
J
h
60
:..-
F'""I: ~
30
=---==
-15
-10
-5
0
5
Vo (Vsl- VOLTS
10
~8
J
60
70·C
25"<:
'0
15
1'-'
~170.C
25·C
"0
J
30
o
-20
1/\
o
-20
20
Figure 1. RON as a Function ofVo (Vs): Dual :t: 15Supplies
-15
-10
-5
0
5
Vo (Vsl- VOLTS
10
Figure 2. RON as a Function ofVo (Vs): Single
15
20
+ 15VSupply
Test Circuits
los
I-----Vl
~
~ ~'O(ONI
..
~V
D
Test Circuit 1
Test Circuit 2
TestCircuit3
CMOS SWITCHES & MUL TIPLEXERS 7-39
•
+15V
+5V
3V
ADG211A~
VL
S1
I
r-J
S2
I
-.I
IN1
I
I
I
IN2
I
D1
~
_
'-----1
VIN
3V
VI~
D2
ADG212A
V
Va
50%
---~
I
I
I
I
I
I
--.t
....
tOPEN
"BOTH THE BUFFER AND INVERTER SHOULD
HAVE THE SAME PROPAGATION DELAY.
TestCircuit4
+5V
VDD
~
S
-
~---:D+
3V
ADG211A"7,"\
Y'N
_ _I--_ _ _-o Va
J
~ 50%
50%
1\-------'1
3vI I
\1 ~O%
v,:v!L 50%
ADG212A~
I
14pF
I
I
Va
.
I
I f 90%
:
I!I
I
--l
tON
l--
\90%
IL--
-I to__ I--
Test Circuit 5
+5V
VDD
D
S
I
_____ .JI
+5V
r-----
r--~------~S---o~I--~~-~-~-~-~-~-~~~-oVo
I
_____ ..JI
--~---- RL
7511
______
I is
D
Voo-'-~--~~~~~~~~--~~~~~ONC
RL
f
-- --
750
GND
\-__.-----:.;:::......1
:!:V
Vss
OFF ISOLATION =
20 x LOG IvsIV01
ADG211A V,N =5V
ADG212A V,N=OV
Test Circuit 6. Offlsolation
+5V
Test Circuit 7. Channel-to-Channel Crosstalk
V DD
,...-- ---,
:
Rs I
I
I
5V
~
S
~~: f--J
~
Y'N
CHANNEL ISOLATION =
20 x LOG IVslVol
ADG211A V,N=OV
ADG212A V IN =5V
--L
---l-
~.1Vo
~
J1.
Test Circuit 8. Charge Injection
7-40 CMOS SWITCHES & MUL TIPLEXERS
QINJ=C L x.1VO
CMOS
Quad SPST Switches
ADG221 /ADG222 I
1IIIIIIII ANALOG
WDEVICES
FEATURES
44V Supply Maximum Rating
:t: 15V Analog Signal Range
Low RON (60m
Low Leakage (O.5nA)
Extended Plastic Temperature Range
(- 4O·C to + 85·C)
Low Power Dissipation (25.5mW)
I1P, TTL, CMOS Compatible
Standard 16-Pin DIPs and 20-Terminal
Surface Mount Packages
Superior DG221 Replacement
ADG22l1ADG222 FUNCTIONAL BLOCK DIAGRAM
51
IN1
01
52
IN2
02
53
IN3
03
54
IN4
D4
WR
GENERAL DESCRIPTION
The ADG221 and ADG222 are monolithic CMOS devices comprising four independently selectable switches. On-chip latches
facilitate microprocessor interfacing. They are designed on an
enhanced LC2MOS process which gives an increased signal
handling capability of ± lSV. These switches also feature high
switching speeds and low RoN'
The ADG221 and ADG222 consist of four SPST switches. They
differ only in that the digital control logic is inverted. All devices
exhibit break before make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
ORDERING INFORMATION l
Temperature Range and Package Options2 , 3
- 40·C to + 85·C
- 400C to + 85·C
- 55·C to + 125·C
ADG221
ADG222
PRODUCT HIGHLIGHTS
I. Easily Interfaced:
Digital inputs are latched with a WR signal for microprocessor
interfacing. A SV regulated supply is internally generated
permitting wider tolerances on the supplies without affecting
the TTL digital input switching levels.
2. Single Supply Operation:
For applications where the analog signal is unipolar (OV to
15V), the switches can be operated from a single + lSV
supply.
3. Low Leakage:
Leakage currents in the range of 500pA make these switches
suitable for high precision circuits. The added feature of
Break before Make allows for multiple outputs to be tied
together for multiplexer applications while keeping leakage
errors to a minimum.
Plastic DIP (N-16)
Hermetic (Q-16)
Hermetic (Q-16)
ADG221KN
ADG222KN
ADG221BQ
ADG222BQ
ADG221TQ
ADG222TQ
WR
ADG221
IN
PLCC4 (P-20A)
LCCCS (E-20A)
0
0
1
0
1
ADG221KP
ADG222KP
ADG221TE
ADG222TE
1
X
0
X
NOTES
ITo order MIL·STD-883, Class B processed parts, add 1883B to T grade part
numbers. See Analog Devices Military Products Data Book (1987) for
military data sheet.
'See Section 14 for package outline information.
3Also available in SOIC packages (ADG221KR, ADG222KR).
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
ADG222
IN
SWITCH
CONDmON
ON
OFF
Retains Previous
Switch Condition
Table I. Truth Table
CMOS SWITCHES & MUL TIPLEXERS 7-41
II
SPECIFICATIONS
(V... =
+15Y, Vss= -l5Y,unlessotharwisenollld)
KVersion
Parameter
25"<:
ANALOG SWITCH
Analog Signal Ranse
RoN
:!; 15
60
90
TVersion
BVersion
-4O"Cto
+85"<:
:!; 15
-4O"Cto
+85"<:
25"<:
:!; 15
60
90
145
:!; 15
145
-55"<:to
+ 125"<:
25"<:
:!; 15
:!; 15
60
90
145
Units
Volts
Otyp
o max
Test Conditions
-10V .. Vs" + 10V
los = 1.0rnA
Test Circuit I
RoNVS. Vo(Vs)
RoN Drift
RoN Match
20
0.5
5
20
0.5
5
20
0.5
5
%typ
%i"Ctyp
%typ
Is (OFF)
OFF Input Leakage
0.5
2
0.5
2
0.5
1
Vo= :!;14V;V s +14V;TestCircuit2
100
nAtyp
nAmax
10 (OFF)
0.5
nAtyp
Vo= :!;14V;Vs =+14V;TestCircuit2
OFF Output Leakage
2
100
2
100
1
100
nAmax
In (ON)
ON Channel Leakage
0.5
2
200
0.5
2
200
0.5
I
200
nAtyp
nAmax
2.4
0.8
I
V min
V max
.,A max
DIGITAL CONTROL
Vir..;b Input High Voltage
VINl., Input Low Voltage
IINLorl lNH
100
100
0.5
0.5
...
' ,
2.4
0.8
I
~
0.8
I
Vs=OV,los= lmA
Vn =:!; 14V; Test Circuit 3
DYNAMIC CHARACTERISTICS
30
300
250
30
300
250
tOPEN
,
IoFF
ioN'
tw' Write Pulse Width
ts' Digital Input Setup Time
tH' Digital Input Hold Time
100
100
20
nstyp
nsmax
nsmax
30
300
250
100
100
20
100
100
20
120
120
20
nsmin
nsmin
nsmin
OFF Isolation
80
80
80
dBtyp
ChanneJ-to-Channel Crosstalk
Cs(OFF)
Cn(OFF)
C n , C s (ON)
CIN Digital Input Capacitance
QINJ Charge Injection
80
5
5
16
5
20
80
5
5
16
5
20
80
5
5
16
5
20
dBtyp
pFtyp
pFtyp
pFtyp
pFtyp
pCtyp
POWER SUPPLY
Inn
Inn
Iss
Iss
Power Dissipation
0.6
0.6
0.6
1.5
1.5
1.5
0.1
0.1
0.1
0.2
25.5
0.2
25.5
0.2
25.5
Test Circuit 4
Test Circuit 4
mAtyp
mAmax
mAtyp
mAmax
mWmax
Vs= IOV(p-p);f= 100kHz
RL = 750; Test Circuit 6
Test Circuit 7
Rs=OO;CL=IOOOpF;Vs=OV
Test CircuitS
Digital Inputs = V INL or V INH
NOTE
'Sample tested at ZS"C to ensure compliance.
IoN. low ue the same for both IN and WR disital input changes.
SpecifICations subject to change without notice.
PIN CONFIGURATIONS
DIP
LCCC
coi "z
,
••
V.. 5
ADG221
ADG222
...
NC
7-42 CMOS SWITCHES & MUL TlPLEXERS
~
s
0
,,
U
TOPvtEW
(Not to Seale)
GND 7
iii fi!
Q
~ S
20 ,.
•, 4
NC.
PLCC
,. 52
ADG221
ADG222
TOP VIEW
17 VDO
16 Ne
15
Wii
9
10 11 12 13
~
= NO CONNECT
fi! i B
VDD
NC
(Not to Scale)
,.
14 S3
eI
.
, ••
• ,. " ,. ,.
eI ~ z" ~ B
NC = NO CONNECT
Wil
S3
ADG221/ADG222
ABSOLUTE MAXIMUM RATINGS·
(TA = + 2SoC unless otherwise stated)
. 44V
Voo to Vss .
VootoGND .
Vss to GND ..
Analog Inputs'
Voltage at S, D
. 2SV
-2SV
Vss -O.3V to
Voo +O.3V
30mA
Continuous Current, S or D
Pulsed Current S or D
Ims Duration, 10% Duty Cycle
Digital Inputs I
Voltage at IN, WR . . . . .
70mA
Vss -2V to
Voo +2Vor
20mA, Whichever Occurs First
Power Dissipation (Any Package)
Up to +7SoC . . . . . .
Derates above + 7SoC by
Operating Temperature
Commercial (K Version)
Industrial (B Version) .
Extended (T Version) ..
Storage Temperature . . .
Lead Temperature (Soldering IOsee)
470mW
6mW/oC
- 40°C to + 8SoC
- 40°C to + 8SoC
- SsoC to + 12SoC
- 6SoC to + IS0°C
. . . . . +300°C
NOTE
IOvervoltage at IN, WR, S or D will be clamped by diodes. Current should be
limited to tbe Maximum Rating above.
·COMMENT: Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at the.. or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one Absolute Maximum Rating may be applied at
anyone time.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
Typical Performance Characteristics and Test Circuits
The switches are guaranteed functional with reduced single or dual supplies down to 4.SV.
'5O
V~.15~/\
...
Vas =-5V
/
=, •
.
V'"
1----V1
..
Vou '" +1o.8V
6
Vas llZ
-
1O.8V
:t:
~
--- vu-r ---vDD = +1SV
30
-20
los
\
0
J
r... ",}zs"C
VI
-15
-10
-5
+5
Vo IVsl- Volts
+10
+15
+20
TestCircuit 1
RON as a Function of Vo (Vs): Dual Supply Voltage
...
...
vrv~-+"'~J\V\
OY
=
,
T..,='+2S"C
0
I
.
J
vDD = +15V
Vss""OV
V" ~
Test Circuit 2
30
•
-20
-15
-10
-5
+5
VofV.l- Volts
+10
+15
+20
RON as a Function of Va (Vs ): Single Supply Voltage
CMOS SWITCHES & MUL TIPLEXERS 7-43
•
Typical Performance Characteristics and Test Circuits Cont'd
.
,
t~. },8.5V
V.. =-18.&V
0
Ip{VvV'
,
,
I. (OfF), 10 (Off)
./
I/'
V
,..-1/'
V
vv
V
I/'
./
V
V
s
V V
D
vV
Test Circuit 3
TEMPERATURe _ "C
Leakage Current as a Function of Temperature (Note:
Leakage Currents Reduce as the Supply Voltages
Reduce)
+15V
-,-
3V
ADG221 ....-~
i'------.....J,i 50%
3VI I
V,:v 1. 50%
\1 50%
Y'N
+-........01NO....~D+-....-1~........~--OVO
r-............
14pF
ADG222
" 50%
~
Vo
I
I
:190%
:
I!I
I
--l
tON
~
__
.
\90%
iL-
ltoFF ~
Test Circuit 4
+15V
,--
- ---,
:
Ro I
I
I
VDO
AD711
~~: f--J
~
V,N.n.
Test Circuit 5. Charge Injection
+15V
Voo
ADG221 V ,N = 5V
ADG222 Y,N = OV
OFF ISOLATION =
20 x LOG "'slVoi
ADG221 V,N=OV
ADG222V,N =5V
Test Circuit 6. Off Isolation
7-44 CMOS SWITCHES & MUL TIPLEXERS
CHANNEL ISOLATION
20 x LOG IVoNol
Test Circuit 7. Channel to Channel Isolation
=
1IIIIIIII ANALOG
WDEVICES
FEATURES
44V Supply Maximum Rating
Vss to VDD Analog Signal Range
Single/Dual Supply Specifications
Wide Supply Ranges (10.8V to 16.5V)
Extended Plastic Temperature Range
(-40"C to +85"C)
Low Power Dissipation (28mW max)
Low Leakage (20pA typ)
Superior Alternative to:
DG506A. HI-506
DG507A, HI-507
CMOS
8/16 Channel Analog Multiplexers
ADG506A1ADG507A I
ADG506A1ADG507A FUNCTIONAL BLOCK DIAGRAM
ADG506A
D
51
DB
816
AO AI A2 A3 EN
GENERAL DESCRIPTION
The ADGS06A and ADG507A are CMOS monolithic analog
multiplexers with 16 channels and dual 8 channels respectively.
The ADGS06A switches one of 16 inputs to a common output
depending on the state of four binary addresses and an enable
input. The ADG507A switches one of 8 differential inpnts to a
common differential output depending on the state of three
binary addresses and an enable input. Both devices have TTL
and SV CMOS logic compatible digital inputs.
The ADGS06A and ADGS07A are designed on an enhanced
LC2MOS process which gives an increased signal capability of
VS8 to VDD and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
1O.8V to 16.SV single or dual supply range. These multiplexers
also feature high switching speeds and low RoN.
PRODUCT HIGHLIGHTS
1. Single/Dual Supply Specifications with a Wide Tolerance:
The devices are specified in the 10.8V to 16.SV range for
both single and dual supplies.
2. Extended Signal Range:
The enhanced LC2MOS processing results in a high breakdown
and an increased analog signal range of V8S to VDD.
DA
II
II
II
II
II
AO
AI A2 EN
3. Break-Before-Make Switching:
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
4. Low Leakage:
Leakage currents in the range of20pA make these multiplexers
suitable for high precision circuits.
ORDERING INFORMATION l
Temperature Range and Package Options2
-4O"Cto
+85OC
-40°Cto
+ 85°C
-55°Cto
+ 125°C
Plastic DIP (N-28)
ADGS06AKN
ADGS07AKN
Hermetic (Q-28)
ADGS06ABQ
ADGS07ABQ
Hermetic (Q-28)
ADGS06ATQ
ADG507ATQ
PLCC 3 (P-28A)
ADG506AKP
ADG507AKP
LCCC4 (E-28A)
ADGS06ATE
ADGS07ATE
NOTES
'To order MIL-STD-883, Class B processed parts, add 1883B to part number.
Contact your local sales office for military data sheet.
2See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier.
4LCCC: Leadless Ceramic Chip Carrier.
CMOS SWITCHES & MUL TlPLEXERS 7-45
I
SPECIFICATIONS
Dual Supply
(v..
=+ 1D.8V 10 + 16.5Y, Vss = -1D.8V 10 -16.5V unless oIII8Iwise noI8d)
ADG507A
ADGSG6A
ADGS07A
ADGSG6A
ADGS07A
KVeraion
BVersion
TVenion
ADG5G6A
+25"<:
+85"<:
+25"<:
+85"<:
+25"<:
-55"<: to
+125"<:
Uails
Vss
VDO
Vss
VDD
Vss
VDO
Vss
Voo
Vss
VOD
Vss
Voo
V min
V max
280
450
300
600
400
280
450
300
600
400
280
450
600
o max
o max
o max
-4O"Cto
Parameter
ANALOG SWITCH
Ana10g Sigoa1 Raoge
RoN
-4O"Cto
300
0.6
5
400
Otyp
-IOV,,;;Vs ";; + 10V, 108= lmA; Test Circuit I
%rCtyp
%typ
Voo= 15V(± )(1%), V.s= -15V(± 10%)
Voo=lSV(±S%), Vss= -ISV(±S%)
-IOV,,;;Vs'" + 10V, los = lmA
-IOV,,;;Vs'" + IOV, los = lmA
RoN Drift
RoNMatch
0.6
5
Is (OFF), Offlnput Leakage
0.02
I
50
0.02
I
50
0.02
I
50
ID(OFF),OffOutputLeakage
ADGS06A
ADG507A
0.04
I
I
200
100
0.04
I
1
200
lOll
0.04
I
1
200
100
ID (ON), On Channel Leakage
ADGS06A
ADGS07A
IDlFP, Differential Off Output
Leakage(ADG507Aooly)
0.04
I
I
0.04
I
I
200
lOll
0.04
I
I
200
lOll
nAtyp
nAmax
nAmax
VI = ± IOV, V2= + IOV; Test Circuit 4
200
lOll
VI = + IOV, V2= +IOV;TestCircuitS.
DIGITAL CONTROL
VINH, Input High Voltage
V INL, Input Low Voltage
IINLor IINH
CIN Digital Input Capacitance
toN (EN)'
toFP(EN)'
OFF Isolation
Cs(OFF)
CD (OFF)
ADGS06A
ADGS07A
QINJ' Chars. Injection
POWER SUPPLY
100
nAtyp
VI = ± 10V, V2= + IOV; Test Circuit 3
n...I\ma."!:
nAmax
2S
nAmax
2.4
0.8
I
2.4
0.8
I
2.4
0.8
I
V min
V max
tJAmax
pFmax
8
8
VJN= =OtOVDD
200
300
400
200
300
400
nstyp
nsmax
VI = ± 10V, V2= +IOV; Test Circuit 6
400
50
25
50
25
Test Circuit 7
10
50
25
nstyp
10
10
nsmin
200
300
200
300
400
200
300
400
nstyp
nsmax
Test Circuit 8
400
200
300
200
300
400
200
300
400
nstyp
nsmax
Test Circuit 8
400
68
50
dBtyp
dB min
VBN=0.8V,RL = 1k!l,CL = ISpF,
Vs= 7Vrms, f= 100kHz
68
50
68
50
5
5
S
pFtyp
VBN=0.8V
44
22
4
44
22
4
44
22
4
pFtyp
pFtyp
pCtyp
VBN=0.8V
mAtyp
mAmax
VIN= VINLorVINH
1.5
tJAtyp
mAmax
V IN = VINLOrVINH
0.2
28
mWtyp
mWmax
0.6
0.6
0.6
20
I.S
20
0.2
Power Dissipation
VI= ± 10V, V2= + 10V; Test Circuit 2
25
1.5
Iss
nAtyp
nAmax
25
8
DYNAMIC CHARACTERISTICS
I
200
lTRANsmoN
300
'oPEN'
0.6
S
Commeals
10
20
0.2
10
28
NOTE
ISample tested at 2Sec to ensure com.p1ianc:c.
Spec:ifkations subiett tochause without norice.
7-46 CMOS SWITCHES & MUL TIPLEXERS
10
28
Rs =OO,Vs=OV; Test Circuit 9
ADG506A1ADG507 A
Single Supply (VIII =+ 10.8V til + 16.5Y, Yss =&NO =OY unless aIIawise noIad)
Parameter
ADGS06A
ADGS07A
ADGS06A
ADGS07A
KVersion
BVersion
+ZS'C
ANALOG SWITCH
Analog Signal Range
RoN
RoN Drift
RoN Match
V..
Voo
500
700
0.6
5
-4O"Cto
+8S'C
V..
Voo
-4O"Cto
+8S'C
+ZS'C
V.s
Voo
500
700
0.6
5
1000
ADGS06A
ADGS07A
TVenion
V.s
Voo
+ZS'C
Vss
Voo
500
700
0.6
5
1000
-sS'Cto
+lZS'C
Units
Comments
V min
V max
Otyp
OV",Vs'" + 10V, los=0.5mA; Test Circuit I
%rCtyp
%typ
OV ""V. "" + 10V,los = 0.5mA
OV""Vs'" + 10V, los = 0.5mA
V.s
Voo
o max
1000
0.02
I
50
0.02
I
50
0.02
I
50
nAtyp
IlAmax
VI= + 10V/OV, V2-0V/+IOV;
Test Circuit 2
10(OFF),OffOutputLeakage
ADG506A
ADGS07A
0.04
I
I
200
100
0.04
I
I
200
100
0.04
I
I
200
100
nAtyp
nAmax
nAmax
VI= + IOVlOV,V2 = OVi + 10V;
Test Circuit 3
10 (ON), On Channel Leakage
ADG506A
ADG507A
IDIFF' Differential Off Output
Leakage (ADG507 A only)
0.04
I
I
200
100
0.04
I
I
200
100
0.04
I
I
200
100
nAtyp
nAmax
nAmax
VI= + IOVlOV,V2=OV/+ 10V;
Test Circuit 4
Is (OFF), Off Input Leakage
DIGITAL CONTROL
V1NH,lnputHigh Voltage
VINL, Input Low Voltage
IINLor IrNH
C1N Digital Input Capacitance
25
25
25
nAmax
2.4
0.8
I
2.4
0.8
I
2.4
0.8
1
V min
V max
f.LAmax
pFmax
8
8
8
VI = + IOVlOV, V2=OV/+ IOV;
Test Circuit 5.
V1N=OtOVOD
DYNAMIC CHARACTERISTICS
tTRANsmON
toPEN
\
\
toN (EN)\
toFF(EN)\
300
450
300
450
600
300
450
600
nstyp
nsmax
VI = + 10V/OV, V2=OV/+ 10V; Test Circuit 6
600
50
25
50
25
10
50
25
10
nstyp
nsmin
Test Circuit 7
10
250
450
250
450
600
250
450
600
nstyp
nsmax
Test Circuit 8
600
250
450
250
450
600
250
450
600
nstyp
nsmax
Test Circuit 8
600
OFF Isolation
68
50
68
50
68
50
dBtyp
dB min
VEN-0.8V,RL= 1k!l,CL= 15pF,
Vs =3.5Vrms, f= 100kHz
Cs(OFF)
Co (OFF)
ADG506A
ADG507A
QINJ' Charge Injection
5
5
5
pFtyp
VEN=0.8V
44
22
4
44
22
4
44
22
4
pFtyp
pFtyp
pCtyp
VEN=0.8V
mAtyp
mAmax
VIN=VINLorVINH
1.5
25
mWtyp
mWmax
POWER SUPPLY
100
0.6
0.6
0.6
1.5
1.5
Power Dissipation
10
10
10
25
25
NOTE
I Sample tested at 25"C toeDSUrc compliance.
SpecifICations subject to change without notice.
..
.
TRUTH TABLES
Al
AI
\
X
X
.
X
0
,
•,
0
0
0
0
1
1
0
1
\
0
0
1
0
1
\
\
\
\
0
1
1
0
0
\
\
·
1
1
0
1
7
1
1
1
1
,
,
•
•
ON
Swrl'Ql
Al
A\
X
x
x
0
0
0
0
0
0
0
0
0
\
0
0
0
\
\
\
\
\
\
0
0
0
0
0
0
\
0
\
\I
\
\
\
\
12
\
\
\
\3
\
0
0
0
\
14
\
1
\
0
\
\
1
1
1
1
1
1
"
\
\
Rs = on, Vs = OV; Test Circuit 9
EN
x
0
0
0
0
\
\
\
\
0
\
\
\
\
0
0
0
\
\
0
\
0
\
\
\
\
\
\
NONE
2
•7
·•
\0
....
ON
SW\TOl
EN
NONE
2
ADG507A
16
ADG506A
CMOS SWITCHES & MUL TlPLEXERS 7-47
II
Digital Inputs l
Voltage at A, EN
ABSOLUTEMAXIMUMRATINGS*
(TA = 250Cunless otherwise noted)
. 44V
. 25V
-2SV
Voo to Vss .
VootoGND
Vss toGND.
Analog Inputs l
Voltage at S, D
. . . . . . . . . . Vss -4V to
.Voo+4Vor
20rnA, Whichever Occurs First
Power Dissipation (Any Package)
Up to +75OC . . . . . .
470mW
Derates above + 7SOCby
6mWrC
Operating Temperature
Commercial (K Version)
-4O"C to +8S"C
Industrial (8 Version) . .
-4O"C to +8SOC
Extended (T Version) . .
- SS"C to + 12S"C
Storage Temperature Range .
- 6S·C to + ISO"C
Lead Temperature (Soldering, IOsecs) . . . . . . . . . . + 300·C
. . . . . . . . . . Vss -2V to.
Voo +2Vor
20rnA, Whichever Occurs First
Continuous Current, S or D
. . . . . . . . • . 20mA
Pulaed Current S or D
Ims Duration, 10% Duty Cycle
40mA
NOTE
'Overvoltase at A, EN, S or D will be clamped by diodes. Current should be
limited to the Maximum Rating above.
·COMMENT: Sttesses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a sttess rating ollly and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifIcation is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
CAiJTION
ESD (electrostatic discharge) sensltlve device. The digital control inputs are diode protected; however, pemlanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
WARNING!
0
~~DEVICE
PIN CONFIGURATIONS
DIP
LCCC
PLCC
~~~>o;;
~~~JoJfJ
4321282726
..
515 5
514 6
•
,
2
2557
25 S1
24$6
513 7
23S'
ADG506A
512 8
TQPVIEW
lNottoScale)
511 9
2284
ADG506A
TOP VIEW
21"
(Not to Scale)
51010
2082
59"
1951
12 13
"
2
!1
I.
~
15 16 17
~
~
0
'" '"
"NC = NO CONNECT
,.
iii
12
13 14
~~~~:(~:i
"
NC
= NO CONNECT
He "" NO CONNECT
57• •
........
8O• •
l
m u2
~
i
>
3
2
1
•
.
aJ =
III
!
,:
28 27 26
..
l!
J
28
27
0
I ' 25.57'
245. .
235SA
55. 7
ADGS07A
TOP VIEW
(Not to Scale)
20'"
51811
19 S1A
"z
"
AOG507A
TOP VIEW
22S4A
INot to Scale)
21 S3A
$2810
12 13 14 15 16 11
I.
!i! i! :o! :c 11 iii
Ne "" NO CONNECT
i
~ ~
~
:c
"Ne "" NO CONNICT
NC
= NO CONNECT
7-48 CMOS SWITCHES & MUL TIPLEXERS
=
26
:t i5
Typical Periormance Characteristics - ADG50SAlADG507A
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.SV.
700
100
600
600
J
Voo = +5V
= -sv
Vss
500
c::I
~
a: 300
f--
v:)/Z
200
I
~
a: 300
/' '-..
/ ......
.............
+isv
V DD =
Vss = -15V
=
ov
I~ "(
II'- )
c::-
\
Voo = +1D.8V
Vas
600
JV \
400
.!
Voo = +10.8V
f\
VDD
Vss
"'"
zoo
r--
100
+16V
ov
=
I"
100
-20
-15
-10
-S
10
15
-20
20
-15
-10
-5
RON as a Function of VD(VS): Dual Supply Voltage,
TA = +25°C
100
10
15
20
Vo(Vsl- Volts
VDIVsl-Volts
RON as a Function of VD(VS): Single Supply Voltage,
TA = +25°C
1.9
VD~ == +16.sv
V
-16.5V
DO
i1
'0 ION I
v
IDIOF
'0
~
,,/'
V
,/'
/
./.
0.1
1.8
~
I
V""
V
~OFFI
V
~~
V
1.7
ill
'"'~"
/''"
II
I
..........
/
35
45
55
65
75
85
TEMPERATURE - "C
95
105
115
---- -
J
1.5
25
~
1.6
/f-"'"
,,/
/
V
V
,/
125
I
I
9
10
11
12
SUPPLY VOLTAGE- Volts
13
14
15
•
Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply Voltages
Reduce)
Trigger Levels vs. Power Supply Voltage, Dual or Single
Supply, TA = +25°C
800
700
600
\
0.8
'"
0.6
..!.
DUAL
300
200
~
~I
~GLE
SUPPLY
ji
i'----
I-- I--
0.4
-
0.2
l,----
/
-
~
....
~
100
8
9
10
11
12
13
'4
15
SUPPLV VOLTAGE- Volts
t1RANSITION vs. Supply Voltage: Dual and Single Supplies,
TA = +25°C
(Note: For VDD and /Vss/ < 10V; VI = VDDIV,ss,
V2 = VsslV/JDo See Test Circuit 6)
10
11
12
13
SUPPLVVOLTAGE-Volts
14
15
16
17
IDD vs. Supply Voltage: Dual or Single Supply, TA =
+25"C
CMOS SWITCHES & MUL TIPLEXERS 7-49
Test Circuits
Note: All Digital Input Signal Rise and Fall Times Measured from 10% to 90% of 3V. tR = tF = 2Ons.
TEST CIRCUIT 1
TEST CIRCUIT 2
Is (OFF)
RoN
-
TEST CIRCUIT 3
ID(OFF)
IDS
v••
Voo
Voo
Vss
~-----V1------~
D
D
S
D
+O.8V
EN
+O.8V
EN
GND
GND
Vs
TEST CIRCUIT 4
ID(ON)
Vuu
TEST CIRCUIT 5
IDiFF
'-'55
EN
D
O.8V
o-+D;;.;A-=--I A
ADG507A
V1
~
DB
-=- V2
o-+---(A
~
t---+-'---<>GND
~
~
IDIFF
=
IDA (OFF)-IDs(OFF)
TEST CIRCUIT 6
SWITCHING TIME OF MULTIPLEXER, tTRANSITION
Voo
3V ___ I
Vss
1 ADDRESS
~E(V'N)
OV
1
1
1
)
1
1
1
1
,.-----......-.--1
A3
A2
S1
I
A1
1
1
AO ADG506A*
EN
--l
S16
-l
tTRANSITION
V1
S2 THRU S15 r - - - - . . . ,
1
1
V2
35pF
tTRANSITION
'SIMILAR CONNECTION FOR AD507A
TEST CIRCUIT 7
BREAK-BEFORE-MAKE DELAY, toPEN
Voo
3V~DDRESS
DRIVE (V'N)
, . - - -.....-.-1 A3
OV
Vss
S1 r--- points of
both switches when switching from one address
state to another
Maximum input voltage for Logic "0"
Minimum input voltage for Logic "I"
Input current of the digital input
Most positive voltage supply
Most negative voltage supply
Positive supply current
Negative supply current
CMOS
4/8 Channel Analog Multiplexers
AOG5D8A1AOG5D9A I
r.ANALOG
WDEVICES
ADGSOSAlADGS09A FUNCTIONAL BLOCK DIAGRAMS
FEATURES
44V Supply Maximum Rating
Vss to Voo Analog Signal Range
Single/Dual Supply Specifications
Wide Supply Ranges nO.BV to 16.5V)
Extended Plastic Temperature Range
(-40"C to +85"C)
Low Power Dissipation (28mW max)
Low Leakage (20pA typ)
Superior Alternative to:
DG50BA, HI·50B
DG509A, HI·509
51
0---_...00
......---~ODA
DB
580--1---.......,.,
AO A1 A2 EN
GENERAL DESCRIPTION
The ADG50SA and ADG509A are CMOS monolithic analog
multiplexers with S channels and dual 4 channels respectively.
The ADGSOSA switches one of S inputs to a common output
depending on the state of three binary addresses and an enable
input. The ADG509A switches one of 4 differential inputs to a
common differential output depending on the state of two binary
addresses and an enable input. Both devices have TTL and 5V
CMOS logic compatible digital inputs.
The ADGSOSA and ADG509A are designed on an enhanced
LC2MOS process which gives an increased signal C8p8bility of
Vss to VDD and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
IO.SV to 16.5V single or dual supply range. These mUltiplexers
also feature high switching speeds and low RoN.
AO A1 EN
PRODUCT HIGHLIGHTS
1. Single/Dual Supply Specifications with a Wide Tolerance:
The devices are specified in the IO.SV to 16.5V range for
both single and dual supplies.
2. Extended Signal Range:
The enhanced LC2 MOS processing results in a high breakdown
and an increased analog signal range ofVss to VDD •
3. Break-Before-Make Switching:
Switches are guaranteed break·before-make so that input
signals are protected against momentary shorting.
4. Low Leakage:
Leakage currents in the range of 20pA make these multiplexers
suitable for high precision circuits.
ORDERING INFORMATION!
Temperature Range and Package Options2, 3
-40·Cto
+SS·C
-40·Cto
+SS·C
-55·Cto
+12S·C
Plastic DIP (N.16)
ADG50SAKN
ADG509AKN
Hermetic (Q.16)
ADG50SABQ
ADG509ABQ
Hermetic (Q.16)
ADG508ATQ
ADG509ATQ
LCCC s (E.20A)
ADG508ATE
ADG509ATE
PLCC4 (P.20A)
ADG508AKP
ADG509AKP
NOTES
'To order MIL·STD-883, Class B processed parts, add /883B to part number.
Contact your local sales omce for military data sheet. For U.S. Standard Military
Drawing (SMD), see DESC drawing #S962-770S2.
'See Section 14 for package outline information.
3Also available in SOlC packages (ADGS08AKR, ADGS09AKR).
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
CMOS SWITCHES & MUL T/PLEXERS 7-53
7
SPECIFICATIONS
Dual Supply
(VIII= +lOJYID
+ 16.5Y.Vss = -lOJYIo -l6.5Vunlessothelwisenollld)
ADGS08A
ADGS09A
KVenion
Parameter
ANALOG SWITCH
Analog SignaI~
RoN
ADGS08A
ADGS09A
BVersion
ADGS08A
ADGS09A
TVersion
+lS"C
-4O'Cto
+85"C
25"C
-4O'Cto
+8S"C
+2S"C
-SS"Cto
+125"C
Units
Vss
Voo
Vss
Voo
Vss
Voo
Vss
Voo
Vss
Voo
Vss
Voo
V min
V max
280
450
300
600
400
280
450
300
600
280
450
600
400
300
0.6
5
400
Iltyp
Ilmax
Ilmax
Ilmax
%f'Ctyp
%typ
Comments
-IOV",Vs'" + 10V, los = lmA
Voo=ISV(±lo%),Vss= -ISV(±lo%)
Voo=ISV(±S%),Vss= -ISV(±S%)
Vs=O,Ios=lmA
-IOV",Vs'" + 10V, los = lmA
RoNDrift
RoNMatch
0.6
5
Is (OFF), OffInput Leakage
0.02
I
0.02
I
SO
0.02
1
SO
nAtyp
nAmax
VSI - ± 10V, VO=VS2 toVSN -+IOV
SO
0.04
1
1
0.04
I
I
100
SO
0.04
1
1
100
SO
nAtyp
nAmax
nAmax
VSI to VSN = ±IOV, Vo= +IOV
100
SO
0.04
i
I
0.04
1
1
100
SO
nAtyp
nAmax
nAmax
VS2 toVSN = ± JOV~ Vn=V:n = +!OV
100
SO
VSIAIBtoVS4A1B = ±IOV, VOA=VDB=+IOV
10 (OFF), Off Output Leakage
ADGSOSA
ADGS09A
0.6
5
10 (ON), On Ouumel Leakage
}'..DG508A
0.04
1
100
ADGS09A
IDlFF, Differential OffOutput
Leakage (ADGS09A only)
1
SO
DIGITALCONTROL
V 1NH, Input High Voltage
V 1NL, Input Low VoItsge
lINLorIINH
C rN Digital InputCapacitance
Cs(OFF)
Co (OFF)
ADGS08A
ADG509A
QmJ, Charge Injection
nAmax
2.4
0.8
1
2.4
0.8
I
2.4
0.8
1
V min
V max
8
8
IlAmax
VIN=OtoVoo
pFmax
200
300
400
300
400
nstyp
nsmax
RL = IMIl, CL = 3SpF
400
SO
25
RL = IkIl, CL = 35pF
10
50
25
nstyp
10
10
nsmin
200
300
400
300
400
nstyp
nsmax
RL = IkIl, CL = 35pF
400
200
300
400
200
300
400
nstyp
nsmax
RL = IkIl, CL = 35pF
400
dBtyp
dB min
VEN=0.8V,RL = IkIl,CL = ISpF,
Vs=7Vrms,f= 100kHz
200
300
OFF Isolation
25
200
300
'oFF(EN)1
25
8
DYNAMICCHARACTERISTlCS
I
200
tnANSmON
300
I
SO
'oPEN
25
'oN(EN)I
25
68
SO
200
200
68
50
68
SO
5
5
5
pFtyp
VEN=0.8V
22
II
4
22
II
4
22
II
4
pFtyp
pFtyp
pCtyp
VEN =0.8V
mAtyp
mAmax
VIN=VINLorVINH
I.S
0.2
IlA typ
mAmax
28
mWtyp
mWmax
Rs=OIl,CL=IOOOpF,Vs=OV
POWER SUPPLY
100
0.6
0.6
1.5
Iss
20
20
0.2
Power Dissipation
0.6
1.5
10
20
0.2
10
28
NOTE
I Sample tested at 2S"C to ensure compliance.
Specifications subject to change without notice.
7-54 CMOS SWITCHES & MUL TIPLEXERS
10
28
VIN=VINLorVINH
ADG508A1ADG509A
Single Supply (Voo= + ID.BVtD + 16.5V, Vss = GNU = DVlDllesso1hetwise noIIId)
ADGS08A
ADGS09A
ADGS08A
ADGS09A
ADG50BA
ADGS09A
KVenion
BVersion
TVersion
+2S"C
Parameter
ANALOG SWITCH
Analog Signal Range
GND
Voo
500
700
0.6
5
RoN
RoN Drift
RON Match
Is (OFF), Offinput Leakage
-4O"Clo
+8S"C
GND
Voo
1000
+2S"C
GND
Voo
500
700
0.6
5
-4O"Clo
+8S"C
GND
Voo
1000
+2S"C
GND
Voo
500
700
0.6
5
-SS"CIO
+12S"C
GND
Voo
1000
V min
V max
lltyp
o max
%I"Ctyp
%typ
0.02
I
50
0.02
1
50
0.02
I
50
10 (OFF), Off Output Leakage
ADG508A
ADG509A
0.04
I
I
100
50
0.04
1
I
100
50
0.04
I
I
100
50
10 (ON), On Channel Leakage
ADG508A
ADG509A
IDtFF' Differential OffOntput
Leakage (ADG509A only)
0.04
I
I
100
50
0.04
I
I
100
50
0.04
I
1
100
50
nAtyp
nAmax
nAmax
DIGITAL CONTROL
V1NH, Input High Voltage
V INL, Input Low Voltage
I 1NL orl:iNH
C'N Digital Input Capacitance
Comments
Units
GND",Vs'" + IOV,IDS~O.5mA
Vs=O,Ios=O.SmA
GND",Vs'" + IOV,los~0.5mA
nAtyp
nAmax
VSI ~ + lOV/GND, VD~
nAtyp
nAmax
VSitOVSN~
+ lOV/GND, VD~GND/+ lOY
VS2toVsN~
+ lOV/GND, VD~VSI ~GND/+ 10V
VS2toVSN~GND/+
lOY
nAmax
VS'AlBtOVS4A1B~ + IOV/GND, VDA~VOB~GND/+ lOY
25
25
25
nAmax
2.4
0.8
I
2.4
0.8
I
2.4
0.8
I
V min
V max
8
8
J.LAmax
V1N=OtoVDD
pFmax
8
•
DYNAMIC CHARACTERISTICS
tTRANsmON
I
600
300
450
600
300
450
600
nstyp
nsmax
RL~IMll,CL~35pF
450
50
25
50
25
10
50
25
10
nstyp
nsmin
RL ~ Ikll, C L ~ 35pF
10
250
450
250
450
600
250
450
600
nstyp
nsmax
RL ~ Ikll, CL ~ 35pF
600
RL ~ Ikll, C L ~ 35pF
600
250
450
nstyp
600
250
450
300
,
toPEN
toN (EN)'
toFF(EN)'
250
450
OFF Isolation
68
50
68
50
68
50
dBtyp
dB min
5
5
5
pFtyp
VEN~0.8V
22
11
22
11
4
22
11
pFtyp
pFtyp
pCtyp
VEN~0.8V
mAtyp
mAmax
VIN =V1NL or VINH
Cs(OFF)
Co (OFF)
ADG508A
ADG509A
QINJ' Charge Injection
4
POWER SUPPLY
100
0.6
4
0.6
0.6
1.5
Power Dissipation
J.5
10
10
600
1.5
25
VEN~0.8V,RL~ Ikll,CL~
Vs~3.5Vrms,f~
RS~On,CL~
15pF,
100kHz
lOOOpF, Vs~OV
mWtyp
10
25
nsmax
25
mWmax
NOTE
'Sample tested at 25"C to ensure compliance.
Specifications subject to change without notice.
TRUTH TABLES
A2
Al
AO
EN
ON SWITCH
X
X
X
0
NONE
0
0
0
I
I
0
0
I
I
2
0
I
0
I
3
0
I
I
I
I
0
0
I
5
I
0
I
1
6
1
1
0
1
7
1
1
1
1
8
X=Don'tCare
4
Al
AO
EN
ON
SWITCH
PAIR
NONE
X
X
0
0
0
I
1
0
I
I
2
I
0
1
3
1
I
I
4
x = Don't Care
ADG509A
ADG508A
CMOS SWITCHES & MUL TIPLEXERS 7-55
ABSOLUTE MAXIMUM RATINGS·
Digital Inputs!
Voltage at A, EN
(TA = 2SoC unless otherwise noted)
. 44V
. 2SV
-25V
VDD to Vss .
VOD to GND
Vss to GND .
Analog Inputs!
Voltage at S, D
. . . . . . . . . . Vss -4V to
VDD +4Vor
20mA, Whichever Occurs First
Power Dissipation (Any Package)
Up to +7SoC . . . . . .
Derates above + 7SoC by
Operating Temperature
Commercial (K Version)
Industrial (B Version) ..
Extended (T Version) ..
Storage Temperature Range
Lead Temperature Range (Soldering, 10sec)
. . . . . . . . . Vss -2V to
Voo +2Vor
20mA, Whichever Occurs First
. . . . . . . . . . 20mA
Continuous Current, S or D
Pulsed Current S or D
Ims Duration, 10% Duty Cycle . . . . . . . . . . 40mA
470mW
6mWf'C
- 40°C to + 8SoC
- 40°C to + 8SoC
- S5°C to + 12SoC
- 6SoC to + lSO°C
+ 300°C
NOTE
'Overvoltage at A, EN, S or D will be clamped by diodes. Current should be
limited to the Maximum Rating above.
·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
~
WARNING!
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
~:r~
PIN CONFIGURATIONS
LCCC
DIP
PLCC
~
iii
A,
.,
:r
iii
~
!!
3
2
1 2. 19
,.
NC 6
55
.2 7
17 VOO
ADG500A
TOP VIEW
(Not to Scalel
• ,.
.7
1011 12 13
Q
!! ill
A,
~
!! :;
3
2
1
&;
Ne
~
= NO CONNECT
Q
iii
~
3
2
...
.'8
S38
"
"
13
l1 ill
&;
Vu
18 Voo
ADG509A
TOP VIEW
(Not to Scalel
S2A 7
Ne '" NO CONNECT
,."
!! :; i!
1
20
•
10
...
ADG509A
TOP VIEW
Scale)
NC
(Not to
16 NC
15 S2B
53A
8
"
14 538
S3A 8
v••
.,8
17 S1B
S1A 5
NC •
.6
0
2. 19
"
Va'
Voo
Z
,."
GND
S.
11 12
Q
iii
NC
15 55
,.56
•
V"
ADG508A
TOP VIEW
(Not to Sc.lel
16 Ne
53 8
:;
~
18 GND
51 5
v"
:r
18 GNO
""
VIIS 4
GND
!!
::/
53.
S48
DA
7-56 CMOS SWITCHES & MULTIPLEXERS
9
1011 12 13
~ g l! l!:
!
NC
= NO CONNECT
~
g Ii! l!:
!
NC '" NO CONNECT
CMOS Latched
8/16 Channel Analog Multiplexers
ADG526A1ADG527A I
1IIIIIIII ANALOG
WDEVICES
FEATURES
44V Supply Maximum Rating
Vss to VDO Analog Signal Range
Single/Dual Supply Specifications
Wide Supply Ranges (10.8V to 16.5VI
Microprocessor Compatible (100ns WR Pulsel
Extended Plastic Temperature Range
(-40"C to +85"C1
Low Leakage (20pA typl
Low Power Dissipation (28mW maxi
Superior Alternative to:
DG526
DG527
ADG526A1ADG527A FUNCTIONAL BLOCK DIAGRAM
ADG527A
ADG526A
S1
----'~D
I
I
I
0-----....0
S1A
"
DA
I
SBA'm
I :
I
I
I
,
I
S16 Q---+---_r!
I
I
I
S1B I I
I
I
SBB . .
I
I
I
AO A1 A2 EN RS
AD A1 A2 A3 EN RS
GENERAL DESCRIPTION
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 channels and dual 8 channels respectively.
On-chip latches facilitate microprocessor interfacing. The
ADGS26A switches one of 16 inputs to a common output depending on the state of four binary addresses and an enable
input. The ADGS27A switches one of 8 differential inputs to a
common differential output depending on the state of three
binary addresses and an enable input. Both devices have TTL
and SV CMOS logic compatible digital inputs.
The ADGS26A and ADGS27A are designed on an enhanced
LC2MOS process which gives an increased signal capability of
Vss to VDO and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
1O.8V to 16.SV single or dual supply range. These multiplexers
also feature high switching speeds and low RON.
--...c:J DB
4. Break-Before-Make Switching:
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
S. Low Leakage:
Leakage currents in the range of 20pA make these multiplexers
suitable for high precision circuits.
ORDERING INFORMATION l
Temperature Range and Package Options 2
-40°C to
+ 85°C
-40°C to
+ 85°C
-55°Cto
+ 125°C
Plastic DIP (N-28)
ADG526AKN
ADG527AKN
Hermetic (Q-28)
ADGS26ABQ
ADGS27ABQ
Hermetic (Q-28)
ADGS26ATQ
ADG527ATQ
PRODUCT HIGHLIGHTS
1. Single/Dual Supply Specifications with a Wide Tolerance:
The devices are specified in the IO.8V to 16.SV range for
both single and dual supplies.
PLCC3 (P-28A)
LCCC4 (E-28A)
ADG526AKP
ADG527AKP
ADG526ATE
ADGS27ATE
2. Easily Interfaced:
The ADGS26A and ADGS27A can be easily interfaced with
microprocessors. The WR signal latches the state of the
Address control lines and the Enable line. The RS signal
clears both the address and enable data in the latches resulting
in no output (all switches oft). RS can be tied to the microprocessor reset pin.
NOTES
'To order MIL·STD-883, Class B processed parts, add /883B to
part number.
Contact your local sales office for military data sheet.
2 See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier.
4LCCC: Leadless Ceramic Chip Carrier.
3. Extended Signal Range:
The enhanced LC 2MOS processing results in a high breakdown
and an increased analog signal range of Vss to VDO'
CMOS SWITCHES & MUL T/PLEXERS 7-57
•
SPECIFICATIONS
Dual Supply
/
lo(~
10 ION)
w
a:
a:
:0
u
~
~
./'"
1.7
ffi
II
""~
./'" ~OFFI
1.6
~
-
I---
,/
./'"
I
1.5
25
'"
...........
35
45
55
65
75
85
TEMPERATURE _ °C
95
105
'15
125
5
I
I
10
11
12
13
14
15
SUPPLYVQLTAGE- Volts
•
Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply Voltages
Reduce)
Trigger Levels vs. Power Supply Voltage, Dual or Single Supply, TA = + 25°C
CMOS SWITCHES & MUL TIPLEXERS 7-61
800
700
BOO
~
I
i
j
500
1\
0.8
~
..
~NGLE
SUPPLY
I
,J
400
DUAL
200
~::l r-- !'---.
100
I
300
~
0.6
E
--
-
10
11
12
J
-
'"-
13
14
0.4
0.2
V
---
t...--
10
15
L.--
11
12
l.---
13
14
SUPPLY VOLTAGE- Volts
SUPPLY VOLTAGE- Volts
+ 25°C
Test Circuits
TEST CIRCUIT 3
ID(OFF)
TEST CIRCUIT 2
Is (OFF)
RoN
'
-..
V pp
VOP
Vss
Vss
v,
TEST CIRCUIT 5
IDIFF
TEST CIRCUIT 4
ID(ON)
V DD
Vss
Voo
Vss
Voo
Vo
EN
V'~
O.BV
GND
~
V2
-b v,
-b
GND
Ipl.Fl'
=
Voo
_I
I
-~
DV ----"" •• ,.
I
I
I
I
I
I
-I
tTMNSlTION
7-62 CMOS SWITCHES & MUL TIPLEXERS
Vss
ADDR~S
DRivEIV.NI
}-=
I
I
I
:
V2
IDA (OFF) -l p8 (OFF)
TEST CIRCUIT 6
SWITCHING TIME OF MULTIPLEXER, tTRANSITION
3V
16
'00 vs. Supply Voltage: Dual or Single Supply, TA
tTRANSITION vs Supply Voltage: Dual and Single Supplies,
TA = +25°C
(Note: For Voo and /Vssl < 10V; V1 = VoolVs,s,
V2 = VsslVoo. See Test Circuit 6)
TEST CIRCUIT 1
15
35pF
17
ADG526A1ADG527A
TEST CIRCUIT 7
BREAK-BEFORE-MAKE DELAY, tOPEN
V!'>D
Vss
3V~DDRESS
DRIVE (VINI
OV
--U--=UT
I
I
~I
j-"
tOPEN
TEST CIRCUIT 8
ENABLE DELAY, toN (EN), tOFF(EN)
Voo
3V~NABlE
-----
OV
I
I
I
I
2.4V
DRIVE (V IN )
1 50%
Vss
s,
I
! 90%FT\ OUTPUT
--Li] !
~toN~1
A'
~%
AO ADG526A*
I
,---.---j EN
-..j:ENI~
lEN}
+5V
v,.
35pF
·SIMILAR CONNECTION FOR ADG527A
TEST CIRCUIT 9
WRITE TURN-ON TIME, toN (WR)
3V~WR
OV-I
50°'0
DRIVE IV I
IN
2.4V
Voo
Vss
Voo
Vss
EN
51
+5V
s,
+5V
I
1
.;::: OUTPUT
I
,
I
I--
tON
20%
IWRI--!
TEST CIRCUIT 10
RESET TURN-OFF TIME, toFF(RS)
Voo
3V
~ RSDR'VE (VINi
ov
---1
50%
V D,
2.4V
Vss
v"
I
I
II
_
I
I+-
tOfF
I OUTPUT
~
I
(RS) .......
CMOS SWITCHES & MUL TIPLEXERS 7-63
TEST CIRCUIT 11
CHARGE INJECTION
VDD
3V
VIN
r
\
Vo
v..
AS
"--------'
.-1
.1'
Vss
2.4V
~VDr----.,
I
R.
I
a.~
= CL )(
.lVo
~~~~~,--------~~- r~--+-~--~
L_+
__ .Jv,.
¢
I
-
I
~
~
...
·SIMILAR CONNECTION FOR ADG527A
TERMINOLOGY
toFF (EN)
RoN
RoN Match
RoN Drift
tTRANSITION
Is (OFF)
10 (OFF)
10 (ON)
Vs (V o )
Cs (OFF)
Co (OFF)
CIN
toN (EN)
Ohmic resistance between terminals D and S
Difference between the RON of arty two channels
Change in RON versus temperature
Source terminal leakage current when the switch
is off
Drain terminai ieakage current when the switch
is off
Leakage current that flows from the closed switch
into the body
Analog voltage on terminal S or D
Channel input capacitance for "OFF" condition
Channel output capacitance for "OFF" condition
Digital input capacitance
Delay time between the 50% and 90% points of
the digital input and switch "ON" condition
7-64 CMOS SWITCHES & MUL TlPLEXERS
toPEN
V1NL
VINH
IINL (IINH)
Voo
Vss
100
Iss
Delay time between the 50% and 10% points of
the digital input and switch "OFF" condition
Delay time between the 50% and 90% points of
the digital inputs and switch "ON" condition
when switching from one address state to
another
"OFF" time measured between 500/0 points uf
both switches when switching from one address
state to another
Maximum input voltage for Logic "0"
Minimum input voltage for Logic "1"
Input current of the digital input
Most positive voltage supply
Most negative voltage supply
Positive supply current
Negative supply current
r-IANALOG
WDEVICES
CMOS
Latched 4/8 Channel Analog Multiplexers
ADG528A1ADG529A I
FEATURES
44V Supply Maximum Rating
Vss to Voo Analog Signal Range
Single/Dual Supply Specifications
Wide Supply Ranges 110.8V to 16.5V)
Microprocessor Compatible (100ns WR Pulse)
Extended Plastic Temperature Range
1- 4O"C to + 85OC)
Low Leakage 120pA typ)
Low Power Dissipation 128mW max)
Superior Alternative to:
DG528
DG529
GENERAL DESCRIPTION
The ADG528A and ADG529A are CMOS monolithic analog
multiplexers with 8 channels and dual 4 channels respectively.
On-chip latches facilitate microprocessor interfacing. The
ADG528A switches one of 8 inputs to a common output depending
on the state of three binary addresses and an enable input. The
ADGS29A switches one of 4 differential inputs to a common
differential output depending on the state of two binary addresses
and an enable input. Both devices have TTL and SV CMOS
logic compatible digital inputs.
The ADGS28A and ADG529A are designed on an enhanced
LC2 MOS process which gives an increased signal capability of
Vss to Voo and enables operation over a wide range of supply
voltages. The devices can comfortably operate anywhere in the
IO.8V to 16.5V single or dual supply range. These multiplexers
also feature high switching speeds and low RoN.
ORDERING INFORMATION1
Temperature Range and Package Options2
-40°C to
-40°C to
-55°C to
+ 85°C
+ 85°C
+ 125°C
Plastic DIP (N-18)
ADGS28AKN
ADGS29AKN
Hermetic (Q-18)
ADGS28ABQ
ADGS29ABQ
Hermetic (Q-18)
ADG528ATQ
ADG529ATQ
PLCC] (P-20A)
LCCC' (E-20A)
ADG528AKP
ADG529AKP
ADG528ATE
ADG529ATE
ADG528A1ADG529A FUNCTIONAL BLOCK DIAGRAMS
AOG528A
0----_-00
51
_ - - -.....OOA
I'
II
II
II
II
II
II
II
58
OB
t:)--I---,""
AO A1 A2 EN
54Bo--,:",,,,,;,,,,,,,;,,,,,,,-
iiS
AO A1 EN
iiS
PRODUCT HIGHLIGHTS
1. SinglelDual Supply Specifications with a Wide Tolerance:
The devices are specified in the lO.8V to 16.5V range for
both single and dual supplies.
2. Easily Interfaced:
The ADGS28A and ADGS29A can be easily interfaced with
microprocessors. The WR signal latches the state of the
address control lines and the enable line. The RS signal
clears both the address and enable data in the latches resulting
in no output (all switches off). RS can be tied to the microprocessor reset pin.
3. Extended Signal Range:
The enhanced LC 2 MOS processing results in a high breakdown
and an increased analog signal range of Vss to Voo.
4. Break-Before-Make Switching:
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
5. Low Leakage:
Leakage currents in the range of 20pA make these multiplexers
suitable for high precision circuits.
NOTES
'To order MIL-STD-883, Class B processed parts, add 1883B to
part number.
Contact your local sales office for military data sheet.
'See Section 14 for package outline information.
'PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadless Ceramic Chip Carrier.
CMOS SWITCHES & MUL TlPLEXERS 7-65
I
SPECIFICATIONS
Dual Supply
(VIII
=+ lOJY 111 +16.5Y. Yss = -10.8Y 111 -16.5Y unless oIheIwise notad)
ADGSZSA
ADGSZ9A
ADGSZSA
ADGSZ9A
BVersion
KVersion
Parameter
ANALOG SWITCH
Analog Signal Range
RoN
ADGS28A
ADGSZ9A
TVenion
+ZS'C
-4O"Cto
+8S'C
+Z5'C
-4O"Cto
+8S'C
+ZS'C
-SS'Cto
+12S'C
Units
Vss
Voo
Vss
Voo
Vss
Voo
Vss
Voo
Vss
Voo
V ..
VDO
V min
V max
280
450
300
600
400
280
4S0
300
600
400
280
450
600
300
400
o max
o max
o max
RoN Drift
RoN Match
0.6
5
Is (OFF), Offloput Leakage
0.02
I
50
0.02
I
50
0.02
I
50
0.04
I
I
100
50
0.04
I
I
100
50
0.04
I
I
100
50
100
50
0.04
I
I
100
50
10 (OFF), Off Output Leakage
ADG528A
ADG529A
In (ON), On Channel I.ealtoge
ADG528A
ADG529A
IDIFF' Differential Off Output
Leakage (ADG529A only)
0_04
I
I
DIGITAL CONTROL
V'NH, Input High Voltage
V1NL,InputLowVoltage
IINLor IINH
CIN Digital Input Capacitance
0.6
5
0.6
5
v.v"'"
I
I
%I'Ctyp
%typ
Voo= 15V(± 10%), Vss= -ISV(± 10%)
Voo =15V(±5%), Vss= -15V(±5%)
-IOV,.Vs,.+ 10V, los = IrnA
-IOV,.Vs,.+ 10V, los = IrnA
uAtyp
nAmax
VS1 = ±IOV, Vo=VsztoVsN=+lOV
uAtyp
VS1 toVSN = ± lOY, VD = =+=lOV
nAmax
uAmax
DAtyp
uAmax
uAmax
25
2.4
0.8
I
2.4
0.8
I
2.4
0.8
I
8
-IOV,.Vs,.+ 10V,los= ImA
nAmax
25
8
Otyp
100
50
25
8
Comments
VsztoVSN = ± lOV, Vo=Vsr==' +IOV
VS1AIB toVS 4A1B= ± lOY, VDA=VDB = +10V
V min
V max
.,Am""
pFmax
VJN=OtoV OD
nstyp
RL = IMO, CL = 35pF
DYNAMIC CHARACfERISTICS ,
tTRANsmoN
!oPEN
!oN (EN,WR)
tOFF(EN,RS)
tw Write Pulse Width
ts Address, Enable Setup Time
tH Address, Enable Hold Time
'as Reset Pulse Width
200
300
400
200
300
400
200
300
400
nsmax
50
2S
50
25
10
50
2S
10
nstyp
nsmin
RL = IkO, CL = 3SpF
10
200
300
200
300
RL = IkO, CL = 35pF
400
200
300
nstyp
400
400
nsmax
400
nsmax
130
100
10
100
nsmin
nsmin
nsmin
nsmin
See Figure I
See Figure I
See Figure I
See Figure 2
200
300
100
400
120
100
10
100
200
300
100
400
120
100
10
100
200
300
100
DStyp
RL = lkO, CL = 35pF
OFF Isolation
68
50
68
50
68
50
dBtyp
dB min
VEN =0.8V,RI. = Ikll, Cl. = 15pF,
Vs= 7Vrms,f= 100kHz
Cs(OFF)
CD (OFF)
ADGS28A
ADG529A
QINJ' Charge Injection
5
5
5
pFtyp
VEN =0.8V
22
22
11
4
22
II
4
pFtyp
pFtyp
pCtyp
VEN =0.8V
rnAtyp
mAmax
VIN=VINLorVINH
1.5
",Atyp
mAmax
VIN=VINLorVINH
0.2
POWER SUPPLY
Ion
11
4
0.6
0.6
1.5
Iss
20
20
0.2
Power Dissipation
0.6
1.5
10
20
0.2
NOTE
I Sample tested at + 250C to ensure compliance.
Specifications subiect tochangewithout notice.
7-66 CMOS SWITCHES & MUL TIPLEXERS
mWtyp
10
10
28
28
28
mWmax
Rs=OO,CI.= 1000pF, Vs=OV
ADG528A1ADG529A
Single Supply (VIII =+ 10.8V to + 16.5V, Vss =GND =OV IIIIess otherwise noIIId)
Parameter
ADG528A
ADG529A
ADG528A
ADG529A
ADG528A
ADG529A
KVersion
BVenioD
TVersioD
-4O"C10
+85"<:
+ 25"C
ANALOG SWITCH
Analog Signal Range
GND
Voo
500
700
0.6
5
RoN
RoN Drift
RON Match
Is (OFF), Off Input Leakage
GND
Voo
1000
0.02
I
+ 25"C
GND
Voo
500
700
0.6
5
50
0.02
I
10 (OFF), Off Output Leakage
ADG528A
ADG529A
0.04
I
I
100
50
0.04
I
I
10 (ON), OnChanneI Leakage
ADG528A
ADG529A
IDIFF' Differential Off OutpUt
Leakage (ADG529A only)
0.04
I
I
100
50
0.04
I
I
-4O"Clo
+85"<:
GND
Voo
1000
+25"<:
GND
Voo
500
700
0.6
5
50
0.02
I
- 55"<:10
+ 125"<:
Units
GND
Voo
V min
1000
o max
Comments
V max
Otyp
GNDsVss + 10V, los = O.5mA
%/"Ctyp
%typ
GND""Vs""+ 10V,los=0.5mA
GND""Vs ""+ 10V,los=0.5mA
50
nAtyp
nAmax
VS1 = +lOV/GND, Vo=VsztoVsN=GNDJ+lOV
100
50
nAtyp
nAmax
nAmax
VS1toVSN = +IOV/GND, Vo=GND/+IOV
100
50
0.04
I
I
0.04
I
I
100
50
nAtyp
nAmax
nAmax
VS2toVSN= +IOV/GND, Vo=Vsl=GND/+IOV
100
50
VSINBtoVS4A1B=
DIGITAL CONTROL
VtNH,lnput High Voltage
VINL, Input Low Voltage
IINLor IINH
CIN Digital Input Capacitance
25
25
25
nAmax
2.4
0.8
I
2.4
0.8
I
2.4
0.8
I
Vmin
8
8
+ IOV/GND, VOA=VPB=GND/+ IOV
V max
!LAma.
8
V1N=OtOVOD
pFmax
DYNAMIC CHARACTERISTICS I
tTRANsmON
!oPEN
!oN (EN,WR)
tOFF(EN,RS)
300
450
600
300
450
600
300
450
600
nsmax
50
25
10
50
25
10
50
25
10
nsmin
250
450
600
250
450
600
250
450
600
Dstyp
nsmax
nstyp
RL = Ikn, CL = 35pF
600
130
100
10
100
nsmax
nsmin
nsmin
nsmin
nsmin
See Figore I
See Figure I
See Figore I
See Figore2
250
450
100
tw Write Pulse Width
ts Address, Enable Setup Time
tH Address, Enable Hold Time
tRS Reset Pulse Widlh
600
120
100
10
100
250
450
100
250
450
100
600
120
100
10
100
nstyp
nstyp
RL = ImO, CL = 35pF
RL = IkO, CL = 35pF
RL = IkO, CL = 35pF
OFF Isolation
68
50
68
50
68
50
dBtyp
dB min
V EN =0.8V,RL= Ikn,CL -15pF,
Vs =3.5Vrms,f= 100kHz
Cs(OFF)
Co (OFF)
ADG528A
ADG529A
5
5
5
pFtyp
VEN=0.8V
22
22
22
pFtyp
pFtyp
pCtyp
VEN =0.8V
mAtyp
mAma.
V IN =V 1NL or V INH
QINJ' Charge Injection
POWER SUPPLY
100
II
II
II
4
4
4
0.6
0.6
1.5
Power Dissipation
II
0.6
I.S
1.5
II
25
II
25
RS=OO,CL= IOOOpF, Vs=OV
mWtyp
mWmax
25
NOTE
ISample reSled at + 2S"C to ensure compliance.
Specifications subject to cbange without notice.
TRUTH TABLES
Al AI AD EN
X
X
X
X
X
X
0
0
0
0
0
0
I
I
I
0
I
0
I
I
I
I
X
X
X
X
WI
as
S
I
0
X
ON SWITCH PAIR
Retains Previous Switch ConcIitinn
NONB(Address and Enable
Latches Cleared)
Al
AO
EN
WJI.
as
X
X
X
X
X
X
S
X
I
0
X
X
0
0
I
I
I
2
I
3
I
4
X
0
0
I
0
0
I
I
NONE
I
0
I
0
I
I
I
I
0
0
I
I
2
3
I
I
0
0
I
I
I
I
I
0
0
I
I
I
0
0
4
5
6
7
0
I
0
I
I
I
I
0
I
0
0
I
8
X-Don'tCare
0
I
X=Don'tCare
ADG52BA
0
I
0
ON SWITCH PAIR
Retains Previous Switch ConcIitinn
NONE (Address and Enable
LatcbesCleared)
NONB
I
ADG529A
CMOS SWITCHES & MUL TIPLEXERS 7-67
II
Digital Inputs l
Voltage at A, EN, WR, RS . . . . . . . . . . . Vss -4V to
Voo +4Vor
20rnA, Whichever Occurs First
Power Dissipation (Any Package)
Up to +75·C . . . . . .
470mW
Derates above + 7S·C by
6mWrC
Operating Temperature
CommericaI (K Version)
- 4O·C to + 8S·C
- 4O·C to + 8S·C
Industrial (B Version) . .
- SsoC to + 12SoC
Extended (T Version) ..
Storage Temperature Range
-6S·C to + IS0·C
Lead Temperature (Soldering, lOsec)
. . . . . +300OC
ABSOLUTE MAXIMUM RATINGS*
(TA = + 25·C unless otherwise noted)
. 44V
Voo to VSS .
Vooto GND
VSS to GND .
Analog Inputs l
Voltage at S, D
. 25V
-25V
. . . . . . . . . . Vss -2V to
Voo +2Vor
20mA, Whichever Occurs First
. . . . . . . . . . 20rnA
Continuous Current, S or D
Pulsed Current S or D
Ims Duration, 10% Duty Cycle
. . . . . . . . . . 40mA
NOTE
IOvervoltage at A, EN, WR, RS, S or D
clamped by diodes. Current
should be limited to tbe maximum rating above.
will.,.,
·COMMENT: Stresses above those listed under "Abaolute Maximum Ratinga" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational aections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
WARNING!
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on uncunnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
0
~~DEVICE
PIN CONFIGURATIONS
DIP
LCCC
PLCC
...
:! I~ z Ill! :;
:! I~ !illll! :;
3
2
"
3
..
EN 4
v"
1 20 I.
.
2
1
2.
,.
0
""
18 A2
A2
17 GND
5
ADG528A
16 VOD
TOP VIEW
INottos.:.Ie,
521
GND
ADG528A
.. 55
TOPYIEW
(Not to
Y"
55
Scale'
I, 56
5. 8
.3
9
10 11 12 13
iZ
Q
~
:I In
8
14
NC::: NO CONNECT
II>
:! I~ !ill::! :;
3
2
1
Q
!! III in
Ne '" NO CONNECT
II I~ !! Ill! :;
20 19
..
""
EN'
v" •
18 GND
GND
17 VOD
ADG529A
TOP VIEW
(Not to ScaNI
Sf A 6
S2A 1
18 StB
V••
ADG529A
S18
T()II'ViEW
15 S2B
S3A 8
INottoScale1
528
14 S3B
14
9
56
"8
10 11 12 13
Ne
= NO CONNECT
i
g i! !l
!
NC "" NO CONNECT
TIMING DIAGRAMS
.r--
3V~ ••"
iiiiiio ___~~
3V
~=:3 . V~
---""'\I>
A
EN. AO. A1. CA21
2.GV
O.
"--
8V
I
I
AS
f
-Eo. :::::jiRS)----I
3V \
ov
1.5V
tOFF
SWITCH Vo
~
O U T P U T o . a Vo
OV
-
Figure 1
Figure 2
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore,
while WR is held low, the latches are transparent and the switches
respond to the address and enable inputs. This input data is
latched on the rising edge of WR.
Figure 2 shows the Reset Pulse Width, tRS , and Reset Tum-off
Time, !:oFF (RS).
7-68 CMOS SWITCHES & MUL TIPLEXERS
Note: All digital input signals rise and faIl times measured from
10% to 90% of 3V. tR =tp=20ns.
Voltage References
Contents
Page
Selection Guide . . . . . . . . . . . . . . . . .
.8-2
Orientation . . . . . . . . . . . . . . . . . . .
AD580 - High Precision 2.5 Volt Ie Reference .
.8-3
.8-5
AD581 - High Precision 10 Volt Ie Reference .
AD584 - Pin Programmable Precision Voltage Reference.
AD586 - High Precision 5 V Reference . . .
.8-9
· 8 - 15
.8- 23
AD587 - High Precision 10 V Reference ..
AD588 - High Precision Voltage Reference .
· 8 - 31
AD589 - Two-Terminal Ie 1.2 V Reference
· 8 - 51
AD689 - High Precision 8.192 V Reference
· 8 - 55
.8- 63
AD1403/1403A - Low eost Precision 2.5 V Ie References
AD2700/270112702 - ± 10 Volt Precision Reference Series
AD2710/2712 - ± 10.000 Volt Ultrahigh Precision Reference Series
ADREFOll02 - 5 V
+ 10 V References . . . . . . . . . . . . ..
· 8 - 39
· 8 - 67
.8-71
· 8 - 75
•
VOLTAGE REFERENCES 8-1
CJ'l
'"
6r~
Selection Guide
Voltage References
G)
I'll
:JJ
I'll
Model
Ouput
Voltage
V
AD589
AD580
ADI403
AD586
ADREF02
AD689
1\D2700
AD581
AD587
ADREFOI
AD2710
AD2712
AD2702
AD2701
ADS88
AD584
+1.235
+2.5
+2.5
+5
+5
+8.129
+10
+10
+10
+10
+10
±10
±10
-10
Selectable
Selectable
M:l
~
f;l
CJ)
Initial
Accuracy
O/OF.S.
max
Temp
Stability
ppml"C
max
Package
Options'
Temp
Range2
Page
Comments
1.2-2.8
0.4-3
0.4--1
10-100
10-85
25-40
5-25
8.5-25
5-25
3-10
5-30
5-20
8.5-25
1-5
1-5
3-10
3-10
1.5-4
5-30
H
H
N
Q,R
Q
Q
D
H
Q,R
Q
N
N
D
D
D
E,H
C,M
C,M
C
C,M
C,M
C,M
C,M
C,M
C,M
C,M
C
C
C,M
C,M
I,M
C,M
8-51
8-5
8-63
8-23
8-75
8-55
8-67
8-9
8-31
8-75
8-71
8-71
8-67
8-67
8-39
8-15
Two Terminal, 1.2 V Reference
Precision, Three Terminal, 2.5 'V Reference
Second Source, 2.5 V Reference
Precision, Buried Zener 5 V Reference
Second Source, 5 V Reference
Precision, 8.192 Volt Reference
Very High Precision 10 V Reference
Three Terminal 10 V Bandgap Rtierence
Precision Buried Zener 10 V Reference
Second Source 10 V Reference
Ultrahigh Precision 10 V Reference
Ultrahigh Precision ±10 V Reference
Very High Precision ±10 V Reference over Full Military Temp Range
Very High Precision -10 V Reference
Ultrahigh Precision, Monolithic l~rogrammable Reference
Precision, Programmable Bandgap Reference
0.05~.4
0.3-0.5
0.05~.2
0.025-0.05
0.05-0.3
0.05~.1
0.3-0.5
0.01
0.01
0.025~.05
0.025~.05
0.01~.03
0.05~.3
'Package Options: D-Side-Bra2ed Dual-In·Line Ceramic; E-Leadless Chip Carrier; H-Round Hermetic Metal Can (Header); N-Plastic Molded Dual-In-Line; Q-Cerdip; R-SmaIl Outline Plastic (SOIC).
'Temperature Ranges: C-Commercial, 0 to +700C; I-Industrial, -400C to +85°C (Some older products -25°C to +85°C); M-Military, -SSOC to +125°C.
Boldface Type: Product recommended for new design.
Orientation
Voltage References
A voltage reference is used to provide an accurately known
voltage which can be utilized in a circuit or system. For example,
measurement systems rely on precision references in order to
establish a basis for absolute measurement accuracy. Any reference
inaccuracy will undermine the accuracy of the overall system.
Thus, ideal references are characterized by ac(;urately set (and
traceable to recognized fundamental standards) constant output
voltage, independent of temperature, load changes, input voltage
variation and time.
TYPES OF REFERENCES
Some of the available Ie reference circuits use the bandgap
principle: the VBE of any silicon transistor has a negative tempco
of about 2mV/oe, which can be extrapolated to approximately
1.2 volts at absolute zero (the bandgap voltage of silicon). Since
identical transistors operating at constant current densities will
have predictably different temperature coefficients of base-emitter
voltage, it is possible to arrange circuit elements so as to null
out the temperature coefficients associated with the two phenomena
and produce a constant voltage (usually 1.2 volts). This
temperature-invariant voltage can be amplified and buffered to
produce a standard voltage value, such as 2.SV or 1O.OV. The
bandgap types cataloged here include the AD1403 and the ADS80
(2.SV), the ADS8l (lO.OV) and the multi-output ADS84 (2.5,
S.O, 7.S and/or 10.OV).
Another popular form of reference circuit uses a selected low-drift
Zener diode, followed by a buffer-amplifier-and-precision-gain
stage to provide a standard output voltage.
A buried-Zener design provides lower noise and drift than bandgap
references, with laser trimming of thin-film resistors for excellent
accuracy and low drift versus temperature. This technique provides
initial accuracy to ± 1mV and temperature drifts as low as 1. Sppm
in the ADS88 ( + lOV, + SV, ± SV tracking, - SV and - lOY
outputs). Similar reference designs with single voltage outputs
(ADS86 and ADS87, + SV and + lOY respectively) have accuracies
and temperature coefficients that are nearly as good as the
ADS88.
Several of the references allow the user to optionally connect a
capacitor to a noise reduction pin on the Ie and so further
reduce the noise output of the reference. In the ADS86, the
wideband noise (to lMHz) of 200,.,. V peak-to-peak (p-p) is reduced
to 160,.,.V p-p by adding a l,.,.F capacitor to the noise reduction
point.
Kelvin connections provide output sense and force connections,
so that the actual voltage at the load is sensed and any IR drops
in the leads are compensated. The ADS88 provides sense and
force connections in its design.
DEFINITIONS OF SPECIFICATIONS
Line regulation. The change in output voltage due to a specified
change in input voltage. It is usually expressed in percent per
volt or microvolts per volt of input change.
Load regulation. The change in output voltage for a specified
change in load current. It is generally expressed in microvolts
per milliampere, or ohms of dc output resistance. This specification
includes the effect of self-heating due to increased power dissipation
at higher load currents.
Output voltage tolerance. The deviation from the nominal output
voltage at 2Soe and specified input voltage as measured by a
device traceable to a recognized fundamental voltage standard.
Output voltage change with temperature. The change in output
voltage from the value at 2Soe ambient; it is independent of
variations in the other operating conditions. Analog Devices
specifies both an error band and an equivalent temperature
coefficient (in ppmfOC) for most references. The error band
(e.g., ± SmV, - ssoe to + 125°C) is defined graphically in
terms of a box (voltage vertically, temperature horizontally)
whose diagonals extend from 2Soe to T max and 2Soe to T min'
with a slope equal to the stated temperature coefficient. Thus,
the total absolute error for a particular reference over its specified
temperature range is equal to the output voltage tolerance at
2Soe plus the error band.
Turn-on settling time. The time, from a cold start, for the reference
output to settle within a specified error band. This definition
relates only to the electrical turn-on of the chip, and does not
include thermal settling time which depends on the package,
heat-sinking and load-current change.
Long-term stability. The change in output voltage versus time,
specified in ppm/lOOO hours.
Noise. The narrowband (0.1 to 10Hz) and wideband (to lMHz)
random noise on the reference output. It may be measured in
fLY p-p or in nV/YHz.
Output current capability of the voltage reference must also be
considered when selecting a reference. The amount of current
that the reference must source, or sink, for the rest of the system
affects which references are acceptable or may need additional
buffering.
VOL TAGE REFERENCES ~3
•
:
8-4 VOL rAGE REFERENCES
High Precision
2.5V Ie Reference
AD580* I
1IIIIIIII ANALOG
WDEVICES
FEATURES
Laser Trimmed to High Accuracy: 2.500V ±O.4%
3-Terminal Device: Voltage InNoltage Out
Excellent Temperature Stability: 10ppmfC (AD580M, U)
Excellent Long Term Stability: 251l1tV (25/lV!Month)
Low Quiescent Current: 1.5mA max
Small, Hermetic IC Package: T0-52 Can
AD580 FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD580 is a three-terminal, low cost, temperature compensated, bandgap voltage reference which provides a fixed 2.5V
output for inputs between 4.5V and 30V. A unique combination of advanced circuit design and laser-wafer-trimmed
thin-film resistors provide the AD580 with an initial tolerance
of ±0.4%, a temperature stability of better than 10ppmt"C
and long-term stability of better than 250/lV. In addition,
the low quiescent current drain of 1.5mA max offers a clear
advantage over classical zener techniques.
PRODUCT HIGHLIGHTS
1. Laser-trimming of the thin-film resistors minimizes the
AD580 output error. For example, the AD580L output
tolerance is ±lOmV.
2. The three-terminal voltage in/voltage out operation of the
AD580 provides regulated output voltage without any
external components.
3. The AD580 provides a stable 2.SV output voltage for
input voltages between 4.5V and 30V. The capability to
provide a stable output voltage using a 5-volt input makes
the AD580 an ideal choice for systems that contain a
single logic power supply.
4. Thin film resistor technology and tightly controlled bipolar
processing .rrovide the AD 580 with temperature stabilities
to 10ppm/ C and long term stability better than 250/lV.
5. The low quiescent current drain of the AD580 makes it
ideal for CMOS and other low power applications.
The AD580 is recommended as a stable reference for alI8-,
lo. and 12-bit D-to-A converters that require an external reference. In addition, the wide input range of the AD580 allows
operation with 5 volt logic supplies making the AD580 ideal
for digital panel meter applications or whenever only a single
logic power supply is available.
The AD580J, K, Land M are specified for operation over the
o to +70°C temperature range; the AD580S, T and U arespecified for operation over the extended temperature range of
-55°C to +125°C.
·Covered by Patent Nos. 3,887,863; RE30,S86.
TO-52
AD580 CHIP DIMENSIONS
AND PAD LAYOUT
Dimensions shown in inches and (mm).
1 - - - - - - 0.06211.571
•
I
~~f71~T
0.037
10.94)
.J
EOUT
-E
The AD580 is also available
in chip form. Consult the factory
for specifications and applications
information.
VOL TAGE REFERENCES 8-5
II
SPECIFICATIONS
Model
(@E. =+l5Yand2ft)
AD580J
Tn>
Mia
OUTPUT VOLTAGE TOLERANCE
(Error from Nominal 2.500 Volt Output)
AD580K
Mas
Mia
Tn>
Mas
Mia
AD580L
Tn>
AD580M
Mas
Mia
Tn>
Mas
Units
%75
",25
:10
:10
mV
15
S5
7
40
4.3
25
1.75
10
mV
ppmI'C
4
2
2
I
2
I
mV
mV
OUTPUT VOLTAGE CHANGE
TmintoTawr;
LINE REGULATION
7vsVINs30V
4.SVsV JN s7V
0.3
6
3
QUIESCENT CURRENT
1.0
1.5
NOISE(O.IHzto 10Hz)
60
60
60
60
~V(p-p)
250
25
250
25
250
25
250
25
~V
1.5
LOAD REGULATION
.!ol= 10mA
1.5
0.3
10
10
10
1.0
1.0
1.5
1.5
1.0
10
mV
1.5
mA
STABILITY
Long Term
Per Month
TEMPERATURE PERFORMANCE
Specified
Operating
S!o!'Bge
+70
+ 125
+ 175
0
-55
65
PACKAGE OPTION'
TO-52 (H-03A)
0
-55
-65
*
Min
Tn>
OUTPUT VOLTAGE TOLERANCE
(Error from Nominal 2.500 Volt Output)
0
-55
+70
+ 125
-65
+ 175
Mia
Tn>
Mas
Min
Tn>
Max
Vaits
%25
:10
:10
mV
25
55
11
25
4.5
10
mV
ppml"C
6
3
2
2
I
I
mV
mV
10
mV
1.5
mA
OUTPUT VOLTAGE CHANGE
Tminto Tmlnl
LINE REGULATION
7VSV1N S30V
1.5
4.5VsV 1N s7V
0.3
LOAD REGULATION
.!ol= 10mA
10
10
I.S
1.0
1.0
1.5
QUIESCENT CURRENT
1.0
NOISE (0. 1Hz to 10Hz)
60
60
60
~V(p-p)
STABILITY
Long Term
Per Month
250
25
250
25
250
25
~V
TEMPERATURE PERFORMANCE
Specified
Operating
Storage
ABSOLUTE MAXIMUM RATINGS
Input Voltage
Power Dissipation ~l' + 2SOC
Ambient Temperature
Derale above + 2S"C
Lead Temperature (Soldering, 10 sec)
Thermal Resistance
Junction-to-Case
Junction-la-Ambient
-55
- 55
-65
+ 125
+ 150
+ 175
+ 125
+150
+ 175
-55
-55
-65
-55
-55
-65
350mW
2.SmWI"C
300"C
100"CIW
36O"CIW
PACKAGE OPTION'
TO-52 (H-03A)
*
NOTES
I See Sectioa 14 for package outline information.
Specificati.ons subject tochange without notice.
Specifications shown in boldface are tested on all production units at fmal electrical test. Results from those tests are used to calculate outgoing quality levels. All
min and max speciflcations ue guaranteed. although only those shown in
boldface are tested on aU production units.
8-6 VOLTAGE REFERENCES
*
~V
+ 125
+150
+ 175
40V
*
+70
+ 125
+ 175
*
AD580U
ADS80T
Mas
0
-55
-65
*
*
AD580S
Model
+70
+ 125
+ 175
"C
°C
"C
~V
°C
°C
"C
Applying the AD580
THEORY OF OPERATION
Most precision IC references use complex multichip hybrid
designs based on expensive temperature-compensated zener
diodes. Others are monolithic with on-chip zener diodes; these
often require more than one power supply and, with the zener
breakdown occuring near 6.3 volts, will not operate from a
low voltage logic supply.
The AD580 family (AD580, AD581, AD584, AD589) uses
the "bandgap" concept to produce a stable, low-temperaturecoefficient voltage reference suitable for high accuracy dataacquisition components and systems. The device makes use
of the underlying physical nature of a silicon transistor baseemitter voltage in the forward-biased operating region. All
such transistors have approximately a -2mV/C temperature
coefficient, unsuitable for use directly as a low TC reference;
however, extrapolation of the temperature characteristic of
anyone of these devices to absolute zero (with emitter current proportional to absolute temperature) reveals that it will
go to a VBE of 1.205 volts at OK, as shown in Figure 1. Thus,
if a voltage could be developed with an opposing temperature
coefficient to sum with VBE to total 1.205 volts, a zero-TC
reference would result and operation from a single, low-voltage
supply would be possible. The ADS80 circuit provides such a
compensating voltage, V1 in Figure 2, by driving two transistors at different current densities and amplifying the resulting
VBE difference (.6VBE - which now has a positive TC); the
sum (Vz) is then buffered and amplified up to 2.5 volts to provide a usable reference-voltage output. Figure 3 is the schematic diagram of the AD580.
The AD580 operates as a three-terminal reference, which
means that no additional components are required for biasing
or current setting. The connection diagram, Figure 4 is quite
simple.
"V~--~------~------'-------'
1.205V
~
....~.~.::.:::::
------:-
I.OV
..
;p-,
0
VeE VS. TEMPERATURE
~
DEVICES fie
>
i
FOR TWO TYPICAL
/I T)
,ov
ov
.......
::-:.~:;"'-
~~-
-100·C
'73K
100·C
o"c
273.
37. .
TEMPERATURE
Figure 1. Extrapolated Variation of Base-Emitter Voltage with
Temperature (lEaT), and Required Compensation, Shown for
Two Different Devices
Figure 3. AD580 Schematic Diagram
+E
EOUT:-l
A0580
LOAD
_E
Figure 4. AD580 Connection Diagram
VOLTAGE VARIATION VS. TEMPERATURE
Some confusion exists in the area of defining and specifying
reference voltage error over temperature. Historically, references are characterized using a maximum deviation per degree
Centigrade; i.e., 10ppm/C. However, because of the inconsistent nonlinearities in zener references (butterfly or "s"
type characteristics), most manufacturers use a maximum
limit error band approach to characterize their references.
This technique measures the output voltage at 3 to 5 different
temperatures and guarantees that the output voltage deviation
will fall within the guaranteed error band at these discrete
temperatures. This approach, of course, makes no mention or
guarantee of performance at any other temperature within the
operating temperature range of the device.
The consistent Voltage vs. Temperature performance of a typical AD580 is shown in Figure 5. Note that the characteristic
is quasi-parabolic, not the possible "S" type characteristics of
classical zener references. This parabolic characteristic permits
a maximum output deviation specification over the device's
full operating temperature range, rather than just at 3 to 5
discrete temperatures.
I
------.. ~=---~-~=-!;\'o'+
f-,.
.• ..,.+--j
'" VBE
T
bVaE
.1
CUI-
+v,
R,
kT
........
.......... ..
~--~--4-~·~i--~--+---+-~
R,
= VBE+2R;l'.VSE
J1
~i
'" VeE + 2F\2---qIn-:;;= l.20SV
TEMPERATURE
Figure 2. Basic Bandgap-Reference Regulator Circuit
_·c
Figure 5. Typical AD580K Output Voltage vs. Temperature
VOL TAGE REFERENCES 8-7
II
The ADS80M guarantees a maximum deviation of 1. 7SmV
over the 0 to +70oC temeerature range. This can be shown to
be equivalent to 10ppm/C average maximum; i.e...
1.7Sr:!V max X _1_ = 10ppmtC max average
70 C
2.SV
The ADS80 typically exhibits a variation of 1.SmV over the
power supply range of 7 to 30 volts. Figure 6 is a plot of
ADS80 line rejection versus frequency.
to a specially selected factory set current limit; it can be programmed from 1 to lOrnA with the insertion of a single external resistor. The approximate temperature coefficient of
current limit for the ADS80 used in this mode is O.13%tC
for ILIM = 1mA and 0.01 %t C for ILIM = 13mA (see Figure 9).
Figure 8 displays the high output impedance of the ADS80
used as a current limiter for ILIM =1, 2, 3,4, SmA.
NOISE PERFORMANCE
Figure 7 represents the peak-to-peak noise of the ADS80
from 1Hz (3dB point) to a 3dB high end shown on the
horizontal axis. Peak-to-peak noise from 1Hz to 1MHz is
approximately 600IlV.
THE ADS80 AS A CURRENT LIMITER
The ADS80 represents an excellent alternative to current
limiter diodes which require factory-selection to achieve a
desired current. This approach often results in temperature
coefficients of 1%/C. The ADS80 approach is not limited
140
100
~.
__ ,
I--
e~23Vp"p'"
r-
E=18.5V
t= Cc
'
I
L... J
.............
AD58O-
-----t~
k eoutp.p
~
80
~
ror------r---~-----T---_+~
j
eo
E IN COMPOSITE 17V"
V~
.;: lOYI
r-----+-----+------+---+-I
"r-----r----~------+_---j'--~
2Or-----+-----+------+-/+---I
ot;;;;±;;;;~::::L:==:j
10
100
10k
lOOk
LINE FREQUENCY - Hz
Figure 6. AD580 Line Rejection Plot
lmV
/
-
.....-
".
100
Figure 9. A Two-Component Precision Current Limiter
,.
lOOk
~5V + 1mA
THE AD580 AS A LOW POWER, LOW VOLTAGE PRECISION REFERENCE FOR DATA CONVERTERS
The AD580 has a number of features that make it ideally
suited for use with AID and D/A data converters used in
complex microprocessor-based systems. The calibrated
2.500 volt output minimizes user trim requirements and
allows operation from a single low voltage supply. Low
power consumption (lmA quiescent current) is commensurate with that of CMOS-type devices, while the low
cost and small package complements the decreasing cost and
size of the latest converters.
Figure 10 shows the ADS80 used as a reference for the
AD7542 12-bit CMOS DAC with complete microprocessor
interface. The AD580 and the AD7S42 are specified to
operate from a single S volt supply; this eliminates the need
to provide a + lS volt power supply for the sole purpose of
operating a reference. The AD7S42 includes three 4-bit data
registers, a 12-bit DAC register, and address decoding logic;
it may thus be interfaced directly to a 4-, 8- or 16-bit data bus.
Only 8mA of quiescent current from the single +S volt supply
is required to operate the AD7542 which is packaged in a
small 16-pin DIP. The AD544 output amplifier is also low
power, requiring only 2.SmA quiescent current. Its lasertrimmed offset voltage preserves the ±1I2LSB linearity of
the AD7S42KN without user trims and it typically settles
to ±1I2 LSB in less than 31ls. It will provide the 0 to -2.S
volt output swing from ±S volt supplies.
r---,..----,---.,---,
"'r---+---+---+-i_--i
120
110f--
j:!!
••v
FREQUENCY - Hz
Figure 7. Peak-to-Peak Output Noise
vs.
Frequency
SYSTEM
8-811 DATA BUS
AD7
ADO
FROM SYSTENI RESET
FROM ADDRESS {AD
"';A
Yv'
Figure 8. Input Current
vs.
Input Voltage (Integral Loads)
8-8 VOLTAGE REFERENCES
BUS
A1 _ _ _...J
FROM WR _ - - - - - '
FROM ADDRESS DECODER - - - - - - - - - - '
Figure 10. Low Power, Low Voltage Reference for the
AD7542 Microprocessor-Compatible 12-Bit DAC
ANALOG
WDEVICES
11IIIIIIII
FEATURES
Laser-Trimmed to High Accuracy:
10_000 Volts ±5mV (L and U)
Trimmed Temperature Coefficient:
5ppmfC max, 0 to +70°C (L)
10ppmfC max, -55°C to +125°C (U)
Excallent Long-Term Stability:
25ppm/1000 hrs_ (Noncumulative)
Negative 10 Volt Reference Capability
Low Quiescant Current: 1_0mA max
10mA Current Output Capability
3-Terminal TO-5 Package
High Precision
10V Ie Reference
AD581* I
ADS81 FUNCTIONAL BLOCK DIAGRAM
TO-S
BOTTOM VIEW
PRODUCT DESCRIPTION
The ADS81 is a three-terminal, temperature compensated,
monolithic band-gap voltage reference which provides a precise 10.00 volt output from an unregulated input level from
12 to 30 volts. Laser Wafer Trimming (LWT) is used to trim
both the initial error at +2SoC as well as the temperature
coefficient, which results in high precision performance previously available only in expensive hybrids or oven-r~lated
modules. The SmV initial error tolerance and Sppml C guaranteed temperature coefficient of the ADS81L represent the
best performance combination available in a monoiithic voltage reference.
The band-gap circuit design used in the ADS81 offers several
advantages over classical Zener breakdown diode techniques.
Most important, no external components are required to
achieve full accuracy and stability of significance to low power
systems. In addition, total supply current to the device, including the output buffer amplifier (which can supply up to lOrnA)
is typically 750pA. The long-term stability of the band-gap
design is equivalent or superior to selected Zener reference
diodes.
PRODUCT HIGHLIGHTS
1. Laser trimming of both initial accuracy and temperature
coefficient results in very low errors over temperature without the use of external components. The ADS81L has a
maximum deviation from 10.000 volts of ±7.2SmV from
Oto +70oC, while the ADS81U guarantees ±lSmV maximum . '
total error without external trims from -SSoC to +12SoC.
2. Since the laser trimming is done on the wafer prior to separation into individual chips, the ADS81 will be extremely
valuable to hybrid designers for its ease of use, lack of
required external trims, and inherent high performance.
3. The ADS81 can also be operated in a two-terminal "Zener"
mode to provide a precision negative 10 volt reference with
just one external resistor to the unregulated supply. The performance in this mode is nearly equal to that of the standard three-terminal configuration.
4. Advanced circuit design using the band-gap concept allows
the ADS81 to give full performance with an unregulated input voltage down to 13 volts. With an external resistor, the
device will operate with a supply as low as 11.4 volts.
The ADS81 is recommended for use as a reference for 8-, 10or 12-bit D/A converters which require an external precision reference. The device is also ideal for all types of AID converters
up to 14 bit accuracy, either successive approximation or integrating designs, and in general can offer better performance
than that provided by standard self-contained references.
The ADS81], K, and L are specified for operation from 0 to
+70°C; the ADS81S, T, and U are specified for the -SSoC to
+12SoC range. All grades are packaged in a hermeticallysealed three-terminal TO-S metal can.
·Covered by Patent Nos. 3,887,863; RE 30,586
VOL TAGE REFERENCES 8-9
SPECIFICATIONS
Model
(@
v. = +15Y and 2ft)
ADS81J
Min
Typ
Max
AD58IK
Typ
Min
AD58IL
Max
Max
Uaito
±S
mV
±6.7S
±Z.ZS
mV
15
5
ppml"C
3.0
(0.002)
1.0
(0.005)
mV
%N
mV
%N
OUTPUT VOLTAGE TOLERANCE
(ErrorfromnominallO,OOOV·output)
±30
OUTPUT VOLTAGE CHANGE
Maximum Deviationfrom + 25<><:
Value,TmlntoTlJUlx
(Temperature Coefficient)
±13.S
30
3.0
(0.002)
1.0
(0.005)
3.0
(0.002)
1.0
(0.005)
Min
Typ
±IO
LINE REGULATION
lSV!SVIN~30V
13VsV1w s15V
LOAD REGULATION
O:sIm.:T s5mA
200
SOO
200
SOO
200
SOO
.,.V1rnA
QUIESCENT CURRENT
0.75
1.0
0.75
1.0
0.75
1.0
mA
TURN·ON SETTLING TIME TOO.I%'
200
200
200
NOISE (0. I to 10Hz)
50
50
50
.,.V1p'P
LONG·TERM STABILITY
25
25
25
ppmllOOOhrs.
SHORT-CIRCUIT CURRENT
30
30
30
mA
OUTPUT CURRENT
Soun.:e eel + 2S"C
Source T min to T max
Sink T min to T mil[
Sink - 55°C to + 85"C
-
TEMPERATURE RANGE
Specified
Operating
0
-65
10
5
5
10
5
5
10
5
5
-
PACKAGE OPTION'
TO-5 (H-03B)
+70
+ 150
+70
+ ISO
ADS81JH
Model
Typ
ADS8IT
Typ
Min
Max
mA
.,.A
mA
0
-65
ADS81KH
ADS81S
Min
mA
-
0
-65
.,..
+70
+ 150
"C
°C
Max
Units
±S
mV
AD581LH
Max
Min
ADS81U
Typ
OUTPUT VOLTAGE TOLERANCE
(Error from nominallO,OOOV output)
±30
OUTPUT VOLTAGE CHANGE
Maximum Deviation from + 2S C
Value, T min to T max
(Temperature Coefficient)
±30
±15
±IO
mV
30
15
10
ppml"C
3.0
(0.002)
1.0
(0.005)
3.0
(0.002)
1.0
(0.005)
3.0
(0.002)
1.0
(0.005)
mV
%N
mV
%IV
Q
±lO
LINE REGULATION
15VsVrN:s;30V
13VSVtNS lSV
LOAD REGULATION
O::=;!ot:TsSmA
200
500
200
SOO
200
500
J.lY'mA
QUIESCENT CURRENT
0.75
1.0
0.75
1.0
0.75
1.0
mA
TURN-ONSETTLINGTIMETOO.I%'
NOISE (0.1 to 10Hz)
200
200
200
SO
SO
SO
LONG-TERM STABILITY
25
25
25
"V/P'P
ppml1000 hrs.
SHORT-CIRCUIT CURRENT
30
30
30
mA
OUTPUT CURRENT
Source (il + 250C
Source T min to T max
Sink T min to T malt
Sink -- 55"C to + 85°C
10
5
200
5
10
5
200
5
TEMPERATURE RANGE
Specified
Operating
, 125
, 150
55
65
PACKAGE OPTION'
TO-5 (H-03B)
NOTES
·SeeFigure7.
See Section 14 for package outline information.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electri
cal test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed. although only those shown in
boldface are tested on all production units.
M
8-10 VOLTAGE REFERENCES
t 125
+ 150
ADS8lTH
2
mA
mA
"A
mA
10
5
200
5
55
65
AD581SH
.,.s
--55
65
+ 125
+ ISO
°C
°C
ADS8lUH
ABSOLUTE MAX RATINGS
Input Voltage VIN to Ground .
Power Dissipation Ca., + 25°C .
Operating Junction Temperature Range
Lead Temperature (Soldering IOsec)
Thermal Resistance
Junction-to-Ambient
. . , . . . . 40V
600mW
- 55°C to + 150°C
+ 300°C
150°CIW
Applying the AD581
APPLYING THE ADS81
The ADS81 is easy to use in virtually all precision reference
applications. The three terminals are simply primary supply,
ground, and output, with the case grounded. No external components are required even for high precision applications; the
degree of desired absolute accuracy is achieved simply by
selecting the required device grade. The ADS81 requires less
than ImA quiescent current from an operating supply range
of 12 to 30 volts.
An external fine trim may be desired to set the output level
to exactly 10.000 volts within less than a millivolt (calibrated
to a main system reference). System calibration may also require a reference slightly different from 10.00 volts. In either
case, the optional trim circuit shown in Figure 2 can offset the
output by up to ±30 millivolts (with the 22n resistor), if
needed, with minimal effect on other device characteristics.
+lSV
+12VTO +4OV
+10.0OV
6.8k.fl
+10.00V
MAX
.6TCR
220
1m
3.9n
3SppmJ"C
2.OppmtC
o....mtc
-15V
4.3kS1
Figure 1. AD581 Pin Configuration (Top View)
Figure 2. Optional Fine Trim Configuration
Figure 3. Simplified Schematic
VOLTAGE REFERENCES 8-11
VOLTAGE VARIATION VB. TEMPERATURE
Some confusion exists in.the area of defining and specifying
reference voltage error over temperature. Historically, references have been characterized using a maximum deviation per
degree Centigrade; i.e., 10ppm/C. However, because of nonlinearities in temperature characteristics, which originated in
standard Zener references (such as "S" type characteristics)
most manufacturers have begun to use a maximum limit error
band approach to specify devices. This technique involves
measurement of the output at 3, 5 or more different. temperatures to guarantee that the output voltage will fall within the
given error band. The temperature characteristic of the ADS81
consistently follows the S-curve shown in Figure 4. Five-point
measurement of each device guarantees the error band over the
-55°C to +125°C range; three;point measurement guarantees
the error band from 0 to +70 C.
The error band which is guaranteed with the AD581 is the
maximum deviation from the initial value at +25°C; this error
band is of more use to a designer than one which simply guarantees the maximum total change over the entire range (i.e.,
in the latter definition, all of the changes could occur in the
positive direction). Thus, with a given grade of the ADS81, the
designer can easily determine the maximum total error from
initial tolerance plus temperature variation (e.g., for the
AD581T, the initial tolerance is ±10mV, the temperature error
band is ±15mV, thus the unit is guaranteed to be 10.000 volts
±25mV from _55°C to +125°C).
rent is positive. Note that the short circuit current (i.e., zero
volts output) is about 28mA; when shorted to +15 volts, the
sink current goes to about 20mA.
DYNAMIC PERFORMANCE
Many low power instrument manufacturers are becoming increasingly concerned with the turn-on characteristics of the
components being used in their systems. Fast turn-on components often enable the end user to keep power off when not
needed, and yet respond quickly when the power is turned on
for operation. Figure 6 displays the turn-on characteristic of
the AD581. This characteristic is generated from cold-start
operation and represents the true turn-on waveform after an
extended period with the supplies off. The figure shows both
the coarse and fine transient characteristics of the device; the
total settling time to within ±1 millivolt is about 180~s, and
there is no long thermal tail appearing after the point.
j
'ZV
OUTPUT
10,030v
11V
10,02OV
l,w
10,OlOV
l
10.000v
f
OUTPUT
INPurr::
o
10,005
50 100 150 200 250
SETTLING TIME
-lAS
Figure 6. Output Settling Characteristic
VOUT -
Volts
10.000
~
.....
~
"
r-.. ~
i"""
~
r-r-
1I
.."
~
1000
NOISE SPECTRAL DENSITY (nVfV'Hz1
I"'--
-56-60 -40 -30
20
10
0
1020
30
4050
TEMPERATURE _
60
70
80
90
10011012012
~
100
°c
1..0'"
Figure 4. Typical Temperature Characteristic
OUTPUT CURRENT CHARACTERISTICS
The AD581 has the capability to either source or sink current
and provide good load regulation in either direction, although
it has better characteristics in the source mode (positive current into the load). The circuit is protected for shorts to either
positive supply or ground. The output voltage vs. output current characteristics of the device are shown in Figure 5. Source
current is displayed as negative current in the figure; sink cur-
~
0
~OTAL
NOISE bNrmsl UP TO
SPECIFIED FREQUENCY
1
10k
I--
100k
1M
Figure 7. Spectral Noise Densitv and Total rms Noise
vs. Frequency
"
12
10
OUTPUT
VOLTAGE
i' ".r-20
-15 -10
-5
SOURCE
OUTPUT CURRENT -
10
15
20
SINK
-55-60 -40 -30 -20
10
0
10
20
30
40
50
eo
.... .... ~
70
80
90
",.
1.5pAfc
100 110 120126
mA
Figure 5. AD581 Output Voltage vs. Sink and Source Current
8-12 VOLTAGE REFERENCES
...
.... ~ ~ '"""
r"'" r"'"
i.o-"
Figure 8. Quiescent Current vs. Temperature
AD581
PRECISION HIGH CURRENT SUPPLY
The ADS81 can be easily connected with power pnp or power
darlington pnp devices to provide much greater output current
capability. The circuit shown in Figure 9 delivers a precision
10 volt output with up to 4 amperes supplied to the load. The
O.l~F capacitor is required only if the load has a significant
capacitive component. If the load is purely resistive, improved
high frequency supply rejection results from removing the
capacitor.
Y,N ~ 15 Volts
o-.....----~
is!! ''';' +O.75mA
BOTTOM VIEW OF
10 VOLT PRECISION
REFERENCE CIRCUIT
IN TO-5 CASE
Figure ". A Two-Component Precision Current Limiter
470n
J 2N6040
Figure 9. High Current Precision Supply
CONNECTION FOR REDUCED PRIMARY SUPPLY
While line regulation is specified down to 13 volts, the typical
ADS81 will work as specified down to 12 volts or below. The
current sink capability allows even lower supply voltage capability such as operation from 12V ±S% as shown in Figure 10.
The S60n resistor reduces the current supplied by the ADS81
to a manageable level at full SmA load. Note that the other
bandgap references, without current sink capability, may be
damaged by use in this circuit configuration.
_
AD581
.....- . - _ 1 2 V t5%
10V@Oto5mA
NEGATIVE IO-VOLT REFERENCE
The ADS81 can also be used in a two-terminal "Zener" mode
to provide a precision -10.00 volt reference. As shown in Figure 13, the VIN and VOUT terminals are connected together
to the high supply (in this case, ground). The ground pin is
connected through a resistor to the negative supply. The output is now taken from the ground pin instead of VOUT ' With
1mA flowing through the ADS81 in this mode, a typical unit
will show a 2mV increase in output level over that produced
in the three-terminal mode. Note also that the effective output
impedance in this connection increases from 0.2n typical to
2 ohms. It is essential to arrange the output load and the supply resistor, Rs, so that the net current through the ADS81 is
always between 1 and SmA. The temperature characteristics
and long-term stability of the device will be essentially the
same as that of a unit used in the standard three-terminal
mode. The operating temperature range is limited to -55°C
to +8S o C.
The ADS81 can also be used in a two-terminal mode to develop
a positive reference. VIN and VOUT are tied together and to
the positive supply through an appropriate supply resistor. The
performance characteristics will be similar to those of the negative two-terminal connection. The only advantage of this connection over the standard three-terminal connection is that a
lower primary supply can be used, as low as 10.5 volts. This
type of operation will require considerable attention to load
and primary supply regulation to be sure the ADS81 always
remains within its regulating range of 1 to SmA.
Figure 10. 12-Volt Supply Connection
-
THE ADS81 AS A CURRENT LIMITER
The ADS81 represents an alternative to current limiter diodes
which require factory selection to achieve a desired current.
This approach often results in temperature coefficients of
l%/C. The ADS81 approach is not limited to a defined
set current limit; it can be programmed from 0.75 to SmA
with the insertion of a single external resistor. Of course, the
minimum voltage required to drive the connection is 13 volts.
The ADS80, which is a 2.5 volt reference, can be used in this
type of circuit with compliance voltage down to 4.5 volts.
.....- - - - 1.......----1r-_~~~lOG
O.lpF
GND
V REF
'----+------10V
1.2k!! 5%
-15V
Figure 12. Two-Terminal -10 Volt Reference
VOLTAGE REFERENCES 8-13
g,
10 VOLT REFERENCE WITH MULTIPLYING CMOS D/A
OR AID CONVERTERS
The AD581 is ideal for application with the entire AD7533
series of 10- and 12-bit mUltiplying CMOS D/A converters,
especially for low power applications. It is equally suitable for
the AD7574 8-bit AID converter. In the standard hook-up, as
shown in Figure 14, the +10 volt reference is inverted by the
amplifier/DAC configuration to produce a 0 to -10 volt range.
If an AD308 amplifier is used, total quiescent supply current
will typically be 2mA. If a 0 to +10 volt full scale range is
desired, the AD581 can be connected to the CMOS DAC in its
-10 volt "Zener" mode, as shown in Figure 12 (the -1OVREF
output is connected directly to the VREF IN of the CMOS
DAC). The AD581 will normally be used in the -10 volt mode
with the AD7S74 to give a 0 to +10 volt ADC range. This is
shown in Figure 14. Bipolar output applications and other
operating details can be found in the data sheets for the
CMOS products.
PRECISION 12-BIT D/A CONVERTER REFERENCE
The ADS62,like most D/A converters, is designed to operate
with a +10 volt reference element. In the ADS62, this 10 volt
reference voltage is converted into a reference current of approximately O.SmA via the internal 19.9Skn resistor (in series
with the external100n trimmer). The gain temperature coefficient of the ADS62 is primarily governed by the temperature
tracking of the 19.95kn resistor and the Sk/10k span resistors;
this gain T.C. is gu~teed to 3ppm/C. Thus, using the
ADS81L (at Sppml C) as the 10 volt reference guarantees a
maximum full scale temperature coefficient of 8ppm/oC over
the commercial range. The 10 volt reference also supplies the
normal1mA bipolar offset current through the 9.9Sk bipolar
offset resistor. The bipolar offset T.C. thus depends only on
the T .C. matching of the bipolar offset resistor to the input
reference resistor and is guaranteed to 3ppmlC.
+16V
Y
-15V
+5V
AIl68'
R3
AD581
,.
1.2k
5%
GAIN TRIM'
R22k
-10V REF
'81-'-==-----,
SIGNAL C>-JW~~
INPUT
OV TO +1DV
0----,.
A07533
ANALOG
SUPPLY
RETURN
IoUT2
o-..J....---I'3
BIT 10 (UBI
GROUND
-16V
NOTE 1: R1 AND R2CAN BE OMITTED IF GAIN TRIM
'---;..----'
IS NOT REQUIRED
Figure 13. Low Power 10-Bit CMOS DAC Application
-15V
Figure 14. AD581 as Negative 10-Volt Reference for
CMOSADC
+5/+15V
I
I
A
---
~~- -------- -- ----- ~:- -- ------ --j
1:fpo~:1 OFFSET ADJ.
A" ANALOG GROUND
Figure 15. Precision 12-Bit DIA Converter
8-14 VOLTAGE REFERENCES
GROUND
INTERTIE
'- ANALOG
r-IANALOG
WDEVICES
FEATURES
Four Programmable Output Voltages:
10.000V, 7.S00V, S.OOOV, 2.S00V
Laser-Trimmed to High Accuracies
No External Components Required
Trimmed Temperature Coefficient:
Sppml"C max, 0 to + 7O"C (ADS84L)
1Sppml"C max, -SS"C to + 12S"C (ADS84T)
Zero Output Strobe Terminal Provided
Two Terminal Negative Reference
Capability (SV & Above)
Output Sources or Sinks Current
Low Quiescent Current: 1.0mA max
10mA Current Output Capability
Pin Programmable
Precision Voltage Reference
AD584* I
AD584 PIN CONFIGURATIONS
8-Pin DIP
8-Pin TO-99
TAB
•
AD584
TOP VIEW
(NottoScale)
COMMON
20-Pin LCC
>
0
~ g
3
PRODUCT DESCRIPTION
The AD584 is an eight-terminal precision voltage reference
offering pin-programmable selection of four popular output
voltages: 10.000V, 7.s00V, 5.000V and 2.500V. Other output voltages, above, below or between the four standard outputs, are available by the addition of external resistors. Input
voltage may vary between 4.5 and 30 volts.
Laser Wafer Trimming (LWT) is used to adjust the pin-programmable output levels and temperature coefficients, resulting in
the most flexible high precision voltage reference available in
monolithic form.
In addition to the programmable output voltages, the AD584
offers a unique strobe terminal which permits the device to be
turned on or off. When the ADS84 is used as a power supply
reference, the supply can be switched off with a single, lowpower signal. In the "off" state the current drain by the
ADS84 is reduced to about 100pA. In the "on" state the total
supply current is typically 7S0pA including the output buffer
amplifier.
The AD584 is recommended for use as a reference for 8-, 10or 12-bit DIA converters which require an external precision reference. The device is also ideal for all types of AID converters
of up to 14 bit accuracy, either successive approximation or
integrating designs, and in general can offer better performance
than that provided by standard self-contained references.
The ADS84J, K, and L are specified for operation from 0 to
+70o C and packaged in 8-pin plastic pack~e; the ADS84S
and T are specified for the _SSoC to-+12S C range. All
grades are packaged in a hermetically sealed eightterminal TO-99 metal can and 20-pin LCC for surface
mount applications.
·Covered by
u.s. Patent No. 3,887,863, RE 30,586
2
C.>
2
1
+
U
> 2
20 19
,
0'
00
NC 4
18 NC
.~
17 CAP
S.OV/S
AD584
NC 6
16 NC
TOP VIEW
INo. '0 Scalel
2.SV 7
15 Vac
14 NC
NC 8
9
u
2
10 11
u
2
0 2
:IE
:IE
8
12 13
III
III
0
U
2
~
NC = NO CONNECT
PRODUCT HIGHUGHTS
1. The flexibility of the ADS84 eliminates the need to designin and inventory several different voltage references. Furthermore one ADS84 can serve as several references simultaneously when buffered properly.
2. Laser trimming of both initial accuracy and temperature
coefficient results in very low errors over temperature without the use of external components. The ADS84LH has a
maximum deviation from 10.000 volts of ±7.2SmV from
o to +70°C.
3. The ADS84 can be operated in a two-terminal "Zener"
mode at 5 volts output and above. By connecting the input
and the output, the ADS84 can be used in this "Zener"
configuration as a negative reference.
4. The output of the ADS84 is configured to sink or source
currents. This means that small reverse currents can be
tolerated in circuits using the ADS84 without damage to
the reference and without disturbing the output voltage
(lOV, 7.SV and SVoutputs).
VOLTAGE REFERENCES 8-15
•
SPECIFICATIONS
(@
v. =
Model
Min
15V and 25"C)
AD584J
Typ
OUTPUTVOLTAGETQLERANCE
Maximum Error l for Nominal
OutpulSof:
lO.oooV
7.500V
5.000V
2.500V
Max
Min
AD584K
Typ
Max
Min
AD584L
Typ
Maz
Units
:1:30
:1:20
:1:15
:1:7.5
:1:10
:1:8
:1:6
±3.5
:1:5
:1:4
:1:3
±2.5
mV
mV
mV
mV
30
30
IS
IS
5
ppmFC
ppmFC
OUTPUT VOLTAGE CHANGE
Maximum Deviation from + 25°C
Value, T min to T max 2
10.000, 7.500, 5.000VOutputs
2.500V Output
Differential Temperature
Coefficients Between Outputs
5
QUIESCENT CURRENT
Temperature Variation
0.75
1.5
I.5
0.75
1.5
TURN·ON SETTLING TIME TO 0.1 %
200
200
200
iJ.S
NOISE
(0.1 to 10Hz)
50
50
50
".Vp-p
LONG·TERM STABILITY
25
25
25
ppmllooo Hrs.
SHORT·CIRCUIT CURRENT
30
30
30
mA
0.75
1.0
20
Sink T min to T mAlI:
Sink - 55·C to + 85"C
-
TEMPERATURE RANGE
Operating
Storage
0
-65
PACKAGE OPTIONS'
TO·99 (H-08A)
Plastic (N-8)
LCC(E-20A)
O.OOS
SO
10
5
5
Source T min to T max
+70
+ 175
20
SO
20
\0
5
5
\0
5
5
-
-
0
-65
ADS84JH
AD584JN
ADS84JE
NOTES
IArPinl.
2Calculated as average over the operating temperature range.
lSee Section 14 for package outline information.
Specifications subject to change without notice.
1.0
0.002
0.002
0.005
OUTPUT CURRENT
VIN2:VOUT + 2.5V
Source (CV + 25°C
+70
+175
. . . . . . . 40V
- SS·C to
%N
SO
ppmlmA
ADS84LH
AD584LN
AD584LE
ADS84KH
ADS84KN
ADS84KE
600mW
+ 12S·C
+300°C
mA
".AI"C
0.002
0.005
+70
+ 175
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed. although only those shown in
boldface are tested on all production units.
Input Voltage VIN to Ground . . . . .
Power Dissipation @ + 2S oC . . . . .
Operating Junction Temperature Range
Lead Temperature (Soldering 10sec)
Thermal Resistance
Junction-to-Ambient (R-OSA)
(E-20A)
1.0
%N
mA
mA
mA
mA
0
-65
ABSOLUTE MAXIMUM RATINGS
8-16 VOLTAGE REFERENCES
ppmFC
3
3
LINE REGULATION (No Load)
lSVsVI N:s30V
(VOUT +2.5V)"'V!N"'15V
LOAD REGULATION
O:sIouT:sSmA, All OUlputs
10
·C
·C
AD584
Model
Min
ADSlI4S
Typ
Min
AD584T
Typ
Max
Units
±30
±20
±15
±7.5
±IO
±8
±6
±3.5
mV
mV
mV
mV
30
30
15
20
ppmrc
ppmrG
1.0
rnA
IIAI"C
Max
OUTPUT VOLTAGE TOLERANCE
Maximum Error l for Nominal
Outputs of:
lO.oooV
7.500V
5.OOOV
2.500V
OUTPUT VOLTAGE CHANGE
Maximum Deviation from + 2SoC
Value, TmintoTmax2
10.000,7.500,5.oooVOutputs
2.500V Output
Differential Temperature
Coefficients Between Outputs
Temperature Variation
TURN-ON SETTLING TIME TO O. 1%
ppmrG
3
5
0.75
1.5
QUIESCENT CURRENT
1.0
0.75
1.5
200
200
fL'
NOISE
(0.1 to 10Hz)
50
50
fLVp-P
LONG-TERM STABILITY
25
25
ppm/lOOO Hrs.
SHORT-CIRCUIT CURRENT
30
30
rnA
LINE REGULATION (No Load)
15V",VlN "'30V
(VOUT +2.5V)",VIN",15V
0.002
0.005
LOAD REGULATION
0",IouT"'5mA, All Outputs
OUTPUT CURRENT
VIN",VOUT + 2.5V
Source (fv + 25"C
Source T min to T max
Sink Tmin to Trna.
Sink - 55°C to + 85°C
20
10
5
200
5
TEMPERATURE RANGE
Operating
Storage
-55
-65
PACKAGE OPTIONS'
TO-99 (H-08A)
LCC(E-20A)
NOTES
'AlPin\,
2Calculated as average over the operating temperature range.
3See Section 14 for package outline information.
Specifications subject to change without notice.
20
SO
0.002
0.005
%IV
SO
ppm/rnA
AD584SH
AD584SE
-55
-65
•
rnA
10
5
200
5
+125
+ 175
%IV
rnA
fLA
rnA
+ 125
+ 175
"C
"C
AD584TH
AD584TE
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed, although only those shown in
boldface are tested on all production units.
VOLTAGE REFERENCES 8-17
Applying the AD584
APPLYING THE ADS84
With power applied to pins 8 and 4 and all other pins open the
AD584 will produce a buffered nominal10.0V output between
pins 1 and 4 (see Figure 1). The stabilized output voltage
may be reduced to 7.5V, S .OV or 2.5V by connecting the
programming pins as follows:
PIN PROGRAMMING
OUTPUT VOLTAGE
7.SV
Join the 2.5V and S.OV pins (2)
and (3).
Connect the 5 .OV pin (2) to the
output pin (1).
Connect the 2.SV pin (3) to the
output pin (1).
S.OV
2.5V
The options shown above are available without the use of any
additional components. Multiple outputs using only one
ADS84, are also possible by simply buffering each voltage
programming pin with a unity-gain noninverting op amp.
I
I +1.215V
not be omitted; its value should be chosen to limit the output
to a value which can be tolerated by the load circuits. If R2 is
zero, adjusting R 1· to its lower limit will result in a loss of
control over the output voltage. If precision voltages are required to be set at levels other than the standard outputs, the
20% absolute tolerance in the internal resistor ladder must be
accounted for.
Alternatively, the output voltage can be raised by loading the
2.SV tap with R3 alone. The output voltage can be lowered by
connecting R4 alone. Either of these resistors can be a fixed
resistor selected by test or an adjustable resistor. In all cases
the resistors should have a low temperature coefficient to
match the ADS84 internal resistors, which have a negative T.C.
less than 60ppmfC. If both R3 and R4are used, these resistors
should have matched temperature coefficients.
When only small adjustments or trims are required, the circuit
of Figure 2 offers better resolution over a limited trim range.
The circuit can be programmed to S.OV, 7.SVor 10V and
adjusted by means of R1 over a range of about ±200mV. To
trim the 2.SVoutput option, R2 (Figure 2) can be reconnected
to the bandgap reference (pin 6). In this configuration, the
adjustment should be limited to ±100mV in order to avoid
affecting the performance of the ADS84.
I
I
V+
: +5V
I
I.
8k
1+2.5V
,--
Rl
4k
VeG
I
I
3
I
*
I
R3
R2
4k
COMMON
COMMON
L _ _ _ _ _ _ _ _ _ _ _ _ ..J
Figure 2. Output Trimming
·THE 2.6V TAP IS USED INTERNALLY ASA BIAS POINT
AND SHOULD NOT BE CHANGED BY MORE THAN 100mV
IN ANY TRIM CONFIGURATION.
Figure 1.
Variable Output Options
The ADS84 can also be programmed over a wide range of output voltages, including voltages greater than 10V, by the addition of one or more external resistors. Figure 1 illustrates
the general adjustment procedure, with approximate values
given for the internal resistors of the ADS84. The ADS84 may
be modeled as an op amp with a noninverting feedback connection, driven by a high stability 1.21 S volt bandgap reference (see Figure 3 for schematic).
When the feedback ratio is adjusted with external resistors, the
output amplifier can be made to multiply the reference voltage
by almost any convenient amount, making popular outputs of
10.24V, S.12V, 2.S6V or 6.3V easy to obtain. The mostgeneral adjustment (which gives the greatest range and poorest resolution) uses R1 and R2 alone (see Figure 1). As R1 is adjusted
to its upper limit the 2.SV pin 3 will be connected to the output, which will reduce to 2.SV. As R1 is adjusted to its lower
limit, the output voltage will rise to a value limited by R2. For
example, if R2 is about 6kn, the upper limit of the output
range will be about 20V even for large values of Rl. R2 should
R3.
Figure 3. Schematic Diagram
8-18 VOLTAGE REFERENCES
Performance of the AD584
PERFORMANCE OVER TEMPERATURE
Each ADS84 is tested at five temperatures over the -SSoC to
+12SoC range to ensure that each device falls within the
Maximum Error Band (see Figure 4) specified for a particular
grade (i.e., Sand T grades); three-point measurement l!,uarantees performance within the error band from 0 to +70 C (Le.,
J, K, or L grades). The error band guaranteed for the ADS84
is the maximum deviation from the initial value at +25°C.
Thus, given the grade of the ADS84, the designer can easily
determine the maximum total error from initial tolerance ·plus
temperature variation. For example, for the AD584T, the
initial tolerance is ±lOmV and the error band is ±1SmV.
Hence, the unit is guaranteed to be 10.000 volts ±2SmV from
-SSoC to +12S°C.
needed, and yet respond quickly when the power is turned on
for operation. Figure 6 displays the rurn-on characteristic of
the AD584. Figure 6a is generated from cold-start operation
and represents the true turn-<>n waveform after an extended
period with the su pplies off. The figure shows both the coarse
and fine transient characteristics of the device; the total settling
time to within ±1 millivolt is about 180ILS, and there is no
long thermal tail appearing after the point.
j
'2V
OUTPUT
10.0lOV}
10.020V
l1V
OUTPUT
10,01OV
10V
10.000V
10.005
/
VUlJT -
Volts
~
/
V
/
/
o
25
TEMPERATURE
100 150 200 250
Figure 6. Output Settling Characteristic
9.995
-55
50
SETTLING TIME - PI
125
_·c
Figure 4. Typical Temperature Characteristic
OUTPUT CURRENT CHARACTERISTICS
The ADS84 has the capability to either source or sink current
and provide good load regulation in either direction, although
it has better characteristics in the source mode (positive current into the load). The circuit is protected for shorts to either
positive supply or ground. The output voltage vs. output current characteristics of the device is shown in Figure 5. Source
current is displayed as negative current in the figure; sink current is positive. Note that the short circuit current (i.e., zero
volts output) is about 28mA; when shorted to +15 volts, the
sink current goes to about 20mA.
NOISE FILTERING
The bandwidth of the output amplifier in the ADS 84 can be
reduced to filter the output noise. A capacitor ranging between
O.OlILF and O.lILF connected between the Cap and VBG terminals will further reduce the wide band and feedthrough noise
in the output of the AD584, as shown in Figure 8. However,
this will tend to increase the turn-<>n settling time of the
device so ample warm-up time should be allowed.
SUPPLY
VOUT
IlaGL--T_-'
COMMON
*INCREASES TURN ON TIME
Figure 7. Additional Noise Filtering
with an External Capacitor
14
1000
12
10
NOISE SPECTRAL DENSITY !nV/\ Hz)
'l
OUTPUT
VOLTAGE
I
100
O.OlllF
=" '<
~~
-15
-10
SOURCE
-5
10
15
20
SINK
10
-
100pF
........
,..
~
NO CAP
-20
N6cAP
....... t-J
V
I
~g~~I~I~gl~~~~Er;:C5~ UP TO
-
OUTPUT CURRENT - mA
Figure 5. AD584 Output Voltage
vs. Sink and Source Current
1
10
DYNAMIC PERFORMANCE
Many low power instrument manufacturers are becoming increasingly concerned with the turn-on characteristics of the
components being used in their systems. Fast turn-on components often enable the end user to keep power off when not
100
1k
10k
lOOk
1M
FREQUENCY - Hz
Figure 8. Spectral Noise Density and Total rms Noise
vs. Frequency
VOLTAGE REFERENCES 8-19
II'
Applications of the AD584
USING THE STROBE TERMINAL
The ADS84 has a strobe input which can be used to zero the
output. This unique feature permits a variety of new applications in signal and power conditioning circuits.
Figure 9 illustrates the strobe connection. A simple NPN
switch can be used to translate a TTL logic signal into a strobe
of the output. The ADS84 operates normally when there is
no current drawn from pin S. Bringing this terminal low, to
less than 200mV, will allow the output voltage to go to zero.
In this mode the ADS84 should not be required to source or
sink current (unless a 0.7V residual output is permissible). If
the ADS 84 is required to sink a transient current while strobed
off, the strobe terminal input current should be limited by a
100il resistor as shown in Figure 9.
The strobe terminal will tolerate up to Sf.,IA leakage and its
driver should be capable of sinking SOOf.,lA continuous. A low
leakage open collector gate can be used to drive the strobe
terminal directly, provided the gate can withstand the ADS84
The ADS84 can also use an NPN or Darlington NPN transistor
to boost its output current. Simply connect the 10V output
terminal of the ADS84 to the base of the NPN booster and take
the output from the booster emitter ·as shown in Figure 11.
The S.OV or 2.SV pin must connect to the actual output in
this configuration. Variable or adjustable outputs (as shown in
Figures 1 and 2) may be combined with +S.OV connection to
obtain outputs above +S.OV.
RAWSUPPLV
(~5V
>VoUTI
DARLINGTON NPN
2N8057
+Vs
VOUT
AD584
r-'--L..t-----....-
~':~itb~NI
output voltage plus one volt.
4
Ik
+Vs
~~~;"""VOUT
Figure ". NPN Output Cu"ent Booster
STROBE
,...-
loon
~_
AD584
20kn
LOGIC INPUT
LO:,,:HI;-:-:~;,-~:..F-JVI/I,~~
2N2Z22
IOkn
COMMON
Figure 9. Use of the Strobe Terminal
PRECISION HIGH CURRENT SUPPLY
The ADS84 can be easily connected to a power PNP or power
Darlington PNP device to provide much greater output current
capability. The circuit shown in Figure 10 delivers a precision
10 volt output with up to 4 amperes supplied to the load. The
O.lf.,1F capacitor is required only if the load has a significant
capacitive component. If the load is purely resistive, improved
high frequency supply rejection results from removing the
capacitor.
V1N :> 15 Volts
o-.....-----ooQ
470n
THE ADS84 AS A CURRENT LIMITER
The ADS84 represents an alternative to current limiter diodes
which require factory selection to achieve a desired current.
Use of current limiting diodes often results in temperature
coefficients of 1%fc. Use of the ADS84 in this mode is not
limited to a set current limit; it can be programmed from 0.75
to SmA with the insertion of a single external resistor (see
Figure 12). Of course, the minimum voltage required to drive
the connection is 5 volts.
+Vs
VOUT =2.5V
AD584
2.5V
TAP
i==
~+o.75mA
COMMON
Figure 12. A Two-Component Precision Current Limiter
I
I
I
IL __ _
J
2N6040
--o +~g~~ 4 Amps
I-V..:;O,;:,UT'--_ _
Figure 10. High Current Precision Supply
8-20 VOL TAGE REFERENCES
COMMON
NEGATIVE REFERENCE VOLTAGES FROM AN ADS84
The ADS84 can also be used in a two-terminal "zener" mode
to provide a precision -10, -7.5 or -5.0 volt reference. As
shown in Figure 13, the VIN and VOUT terminals are connected together to the positive supply (in this case, ground).
The ADS84 common pin is connected through a resistor to the
negative supply. The output is now taken from the common
pin instead of VOUT. With 1mA flowing through the ADS84 in
this mode, a typical unit will show a 2mV increase in output
level over that produced in the three-terminal mode. Note also
that the effective output impedance in this connection increases from 0.2il typical to 2il. It is essential to arrange
the output load and the supply resistor, Rs, so that the net
current through the ADS84 is always between 1 and SmA.
The temperature chatactetistics and long-term stability of the
AD584
the amplifierlDAC configuration to produce converted voltage
ranges. For example, a +10V reference produces a 0 to -10V
range. If an AD308 amplifier is used, total quiescent supply
current will typically be 2mA. The AD584 will normally be
used in the -10 volt mode with the AD7574 to give a 0 to +10
volt ADC range. This is shown in Figure 16. Bipolar output
applications and other operating details can be found in the
data sheets for the CMOS products.
5.0V
TAP
AD584
VREF
~-----t-----------. ~V
Rs
+15V
2.4k05%
-15V
+10V
Figure 13. Two·Terminal-5 Volt Reference
device will be essentially the same as that of a unit used in the
standard three-terminal mode. The operating temperature range
is limited to _SSoC to +8S oC.
The ADS84 can also be used in a two·terminal mode to develop
a positive reference. VIN and VOUT are tied together and to
the positive supply through an appropriate supply resistor. The
performance characteristics will be similar to those of the neg·
ative two-terminal connection. The only advantage of this c.onnection over the standard three-terminal connection is that a
lower primary supply can be used, as low as 0.5 volts above
the desired output voltage. This type of operation will require
considerable attention to load and primary supply regulation
to be sure the AD584 always remains within its regulating
range of 1 to 5mA.
10 VOLT REFERENCE WITH MULTIPLYING CMOS D/A
OR AID CONVERTERS
The AD584 is ideal for application with the entire AD7520
series of 10- and 12-bit mUltiplying CMOS D/A converters,
especially for low power applications. It is equally suitable for
the AD7574 8-bit AID converter. In the standard hook-up as
shown in Figure 14, the standard output voltages are inverted by
,4
BIT , (MSB)
RFEEDBACK
'6~~~~--------,
'OUTl
AD7533
IOUTZ
~B--'T'-'O-(:-LS--B-)",,'3
-15V
COMMON
Figure 14. Low Power 10-Bit CMOS DAC Application
PRECISION D/A CONVERTER REFERENCE
The AD562, like many D/A converters, is designed to operate
with a +10 volt reference element (Figure 15). In the AD562,
this 10 volt reference voltage is converted into a reference current of approximately 0.5mA via the internal 19.95kU resistor
(in series with the externallOOU trimmer). The gain temperature coefficient of the AD562 is primarily governed by the
temperature tracking of the 19.95kU resistor and the 5kllOk
-15V +5/+15V
----------,
11
I
'0
390pF I
I
I
I
AD562
I
I
7
A
i
-,5V
~------------------------------~
Rl
loon, 1ST
A '" ANALOG GROUND
BIPOLAR OFFSET ADJ.
Figure 15. Precision 12-Bit D/A Converter
VOLTAGE REFERENCES 8-21
I
span resistors; this gain T.C. is guaranteed to 3ppmlC. Thus,
using the ADS84L (at Sppm/°C) as the 10 volt reference
guarantees a maximum full scale temperature coefficient of
8ppmtC over the commercial range. The 10 volt reference
also supplies the normal 1mA bipolar offset current through
the 9.9Sk bipolar offset resistor. The bipolar offset T.C. thus
depends only on the T.C. matching of the bipolar offset resistor to the input reference resistor and is guaranteed to 3ppmlC.
Figure 17 demonstrates the flexibility of the AD584 applied
to another popular D/A configuration.
-15V
AI
RI4 = RI5
+5V
R3
AD584
V,N
Vee
AS
Uk
5%
GAIN TRIM'
R22k
-IOV REF
0-"""_....,
SIGNAL
INPUT
OV TO +IOV .Q----::2/t
Figure 17. Current Output 8-Bit D/A
ANALOG
SUPPLY
RETURN
NOTE 1: Po, AND R2 CAN BE OMiTTED iF GAiN iRiM
IS NOT REOUIRED
Figure 16. AD584 as Negative 10 Volt Reference for
CMOSADC
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (nun).
1 4 - - - - - - - - - 0 . 0 8 0 - - - - - - -- - CAP
(2.03)
.....1
---~r-
V+ 8
SUBSTRATE 9**
0.061
(1.55)
5 STROBE
10V 1*
. . . . . .~. . . . . . . . . .
~
2
3
5V*
2.5V*
4 COMMON
ORV-
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE TO-99, 8-PIN METAL PACKAGE.
*INTERCONNECTIONS REQUIRED; SEE PIN DESIGNATIONS FOR INFORMATIONS.
**NOT BROUGHT OUT IN PACKAGED DEVICE.
8-22 VOL TAGE REFERENCES
High-Precision
5V Reference
AD586
-.ANALOG
WDEVICES
FEATURES
Laser Trimmed to High Accuracy:
S.OOOV :t 2.SmV IL Gradel
Trimmed Temperature Coefficient:
SppmfC max, 0 to + 70°C IL Gradel
10ppmfC max, -SsoC to + 12SoC IT Gradel
Noise Reduction Capability
Low Quiescent Current: 3mA max
Output Trim Capability
ADS86 FUNCTIONAL BLOCK DIAGRAM
NOISE REDUCTION
AD586
Rs
R,
~------------~4r-------------~
GROUND
NOTE: PINS 1, 3 & 7 ARE INTERNAL TEST POINTS.
MAKE NO CONNECTIONS TO THESE POINTS.
PRODUCT DESCRIPTION
The AD586 represents a major advance in the state-of-the-art in
monolithic voltage references. Using a proprietary ion-implanted
buried Zener diode and laser wafer trimming of high stability
thin-fLlm resistors, the AD586 provides outstanding performance
at low cost.
The AD586 offers much higher performance than most other
5V references. Because the AD586 uses an industry standard
pinout, many systems can be upgraded instantly with the AD586.
The buried Zener approach to reference design provides lower
noise and drift than bandgap voltage references. The AD586
offers a noise reduction pin which can be used to further reduce
the noise level generated by the buried Zener.
The AD586 is recommended for use as a reference for 8-, 10-,
12-, 14- or 16-bit D/A converters which require an external
precision reference. The device is also ideal for successive approximation or integrating ND converters with up to 14 bits of
accuracy and, in general, can offer better performance than the
standard on-chip references.
PRODUCT HIGHLIGHTS
I. Laser trimming of both initial accuracy and temperature
coefficients results in very low errors over temperature without
the use of external components. The AD586L has a maximum
deviation from 5.000V of :t3.625mV between 0 and +70°C,
and the AD586T guarantees ±7.5mV maximum total error
between - 55°C and + 125°C.
2. For applications requiring higher precision, an optional fmetrim connection is provided.
3. Any system using an industry standard pinout reference can
be upgraded instantly with the AD586.
4. Output noise of the AD586 is very low, typically 4JLV Pop. A
noise reduction pin is provided for additional noise fLltering
using an external capacitor.
The AD5861, K and L are specified for operation from 0 to
+ 70°C, and the AD586S and T are specified for - 55°C to
+ 1250C operation. All grades are packaged in an 8-pin cerdip
package. The AD5861 and the AD586K are also available in an
8-pin plastic surface mount small outline (SO) package.
VOL TAGE REFERENCES 8-23
•
SPEC IFICAli 0NS
Model
Min
Output Voltage
4.980
(TA =
+ 25OC, YIN = + 15V unless otherwise specified)
AD5861
Typ Max
Output Voltage Drift'
Oto +70"C
- 55'C to + 125'C
Gain Adjustment
Min
AD586K
Typ Max
Min
AD586L
Typ Max
Min
AD586S
Typ Max
5.020 4.995
5.005 4.9975
5.0025 4.990
25
15
5
+6
-2
+6
-2
Line Regulation'
10.8V< +VIN <36V
Tmin to Tmax
Il.4V< +V1N <36V
Tminto Tmax
100
Load Regulation'
Sourcing 0 < lOUT < lOrnA
25'C
T min to Tmax
Sinking - 10 < lOUT .,...+--...,..-0 V
VOUT
OUT
500n
AD586
a. Electrical Turn-On
Figure 6a. Transient Load Test Circuit
5
~v
I
~
IW!
U
_
I
01
~
~ I
·····1····
~
b. Extended Time Scale
c. Turn-on with lp.F CN
~
'~
I I
··· ~
~· ~
I
II
I
~
I
I~
I
I...
I
II
Figure 6b. Large-Scale Transient Response
Figure 6c. Fine-Scale Settling for Transient Load
Figure 5. Turn-on Characteristics
VOL TAGE REFERENCES 8-27
•
In some applications, a varying load may be both resistive and
capacitive in nature, or the load may be connected to the AD586
by a long capacitive cable.
Figure 7 displays the output amplifier characteristics driving a
lOOOpF, 0 to lOrnA load.
> .....-+~-..,..--o V
OUT
50011
AD586
Figure 7a. Capacitive Load Transient Response Test
Circuit
Some confusion exists in the area of defining and specifying
reference voltage error over temperature. Historically, references
have been characterized using a maximum deviation per degree
Centrigrade; i.e., ppml"C. However, because of nonlinearities in
temperature characteristics which originated in standard Zener
references (such as "S" type characteristics), most manufacturers
have begun to use a maximum limit error band approach to
specify devices. This technique involves the measurement of the
output at three or more different temperatures to specify an
output voltage error band.
Figure 9 shows the typical output voltage drift for the AD586L
and illustrates the test methodology. The box in Figure 9 is
bounded on the sides by the operating temperature extremes,
and on the top and the bottom by the maximum and minimum
output voltages measured over the operating temperature range.
The slope of the diagonal drawn from the lower left to the upper
right corner of the box determines the performance grade of the
device.
-
, r-'" -'- '.
•.003
Tlnin
T....
,
,
~
"-.,~*.-
= 170"C-O)x5x105.0027 - 5.00'2
'" 4.3ppmrc
I
I
.....
..
- - - Ymu
v_
I
I
I
I
I
I
I
-20
20
. .I
so
TEMPERATURE - "c
Figure 7b. Output Response with Capacitive Load
LOAD REGULATION
The AD586 has excellent load regulation characteristics. Figure
8 shows that varying the load several rnA changes the output by
a few !LV. The AD586 has somewhat better load regulation
performance sourcing current than sinking current.
1000
500
+2
+4
+6
+8 +10
LOAD (rnA)
500
Figure 9. Typical AD586L Temperature Drift
Each AD586JQ, KQ and LQ grade unit is tested at 0, + 25°C
and + 70°C. Each AD586SQ and TQ grade unit is tested at
- 55°C, + 25°C and + 125°C. This approach ensures that the
variations of output voltage that occur as the temperature changes
within the specified range will be contained within a box whose
diagonal has a slope equal to the maximum specified drift. The
position of the box on the vertical scale will change from device
to device as initial error and the shape of the curve vary. The
maximum height of the box for the appropriate temperature
range and device grade is shown in Figure 10. Duplication of
these results requires a combination of high accuracy and stable
temperature control in a test system. Evaluation of the AD586
will produce a curve similar to that in Figure 9, but output
readings may vary depending on the test methods and equipment
utilized.
1000
DEVICE
GRADE
Figure 8. Typical Load Regulation Characteristics
TEMPERATURE PERFORMANCE
The AD586 is designed for precision reference applications
where temperature performance is critical. Extensive temperature
testing ensures that the device's high level of performance is
maintained over the operating temperature range.
8-28 VOL TAGE REFERENCES
AD586J
AD586K
AD586L
AD586S
AD586T
MAXIMUM OUTPUT CHANGE
(mV)
-55°C TO + 125°C
OTO +70°C
8.75
5.25
1.75
18.00
9.00
Figure 10. Maximum Output Change in mV
1
Applying the AD586
NEGATIVE REFERENCE VOLTAGE FROM AN AD586
The ADS86 can be used to provide a precision - S.OOOV output
as shown in Figure 11. The VIN pin is tied to at least a + 6V
supply, the output pin is grounded, and the ADS86 ground pin
is connected through a resistor, Rg, to a -ISV supply. The
- 5V output is now taken from the ground pin (Pin 4) ins~ead
of Your. It is essential to arrange the output load and the ~upply
resistor Rs so that the net current through the ADS86 is between
2.SmA and IO.OmA. The temperature characteristics and longterm stability of the device will be essentially the same as that of
a unit used in the standard + SV output confIguration.
+6V
-+
to produce 0 to - SV outputs. Because both DACs are on the
same die and share a common reference and output op amps,
the DAC outputs will exhibit similar gain TCs.
+15V
+15V
+30V
2.SmA <
w.-
-IL <10mA
Figure 13. AD586 as a 5V Reference for a CMOS Dual
DAC
~--~--5V
-15V
Figure ". AD586 as a Negative 5V Reference
USING THE AD586 WITH CONVERTERS
The AD586 is an ideal reference for a wide variety of 8-, 12-,
14- and 16-bit AID and D/A converters. Several representative
examples follow.
5V REFERENCE WITH MULTIPLYING CMOS D/A OR
AID CONVERTERS
The AD586 is ideal for applications with 10- and 12-bit multiplying
CMOS D/A converters. In the standard hookup, as shown in
Figure 12, the AD586 is paired with the AD7545 12-bit multiplying
DAC and the AD711 high-speed BiFET Op Amp. The amplifIer
DAC configuration produces a unipolar 0 to - 5V output range.
Bipolar output applications and other operating details can be
found on the individual product data sheets.
STACKED PRECISION REFERENCES FOR MULTIPLE
VOLTAGES
Often, a design requires several reference voltages. Three AD586s
can be stacked, as shown in Figure 14, to produce +S.OOOV,
+ IO.OOOV, and + IS.OOOV outputs. This scheme can be extended
to any number of AD586s as long as the maximum load current
is not exceeded. This design provides the additional advantage
of improved line regulation on the + s.OV output. Changes in
VIN of + 18V to + 50V produces an output change that is below
the noise level of the references.
+22VTO +4&V
.~t----+-----_--o +1S.000V
H---+------<: 10k"
6BH
.2
~-~--o + 10.000V
10kU
}----+-----4---o +5.000V
Figure 12. Low-Power 12-8it CMOS DAC Application
The AD586 can also be used as a precision reference for multiple
DACs. Figure 13 shows the AD586, the AD7628 dual DAC and
the AD712 dual op amp hooked up for single supply operation
Figure 14. Multiple AD586s Stacked for Precision 5V, 10V
and 15V Outputs
VOLTAGE REFERENCES 8-29
II.
PRECISION CURRENT SOURCE
+VIN
The design of the AD586 allows it to be easily configured as a
current source. By choosing the control resistor Rc in Figure
15, you can vary the load current from the quiescent current
(2mA typically) to approximately lOmA. The compliance voltage
of this circuit varies from about + 5V to + 21 V depending upon
the value ofVIN•
Figure 15. Precision Current Source
PRECISION HIGH CURRENT SUPPLY
For higher currents, the ADS86 can easily be connected to a
power PNP or power Darlington PNP device. The circuit in
Figure 16 can deliver up to 4 amps to the load. The O.lIJ.F
., '" t ';-ft
+15V 0 -......- - - - - . . . ,
r---- -,
220n
I
II
capacitor is required only if the load has a significant capacitive
component. If the load is purely resistive, improved high-frequency
supply rejection results can be obtained by removing the
capacitor.
I
220n
1..'529<
I·" .
I
I
~
. : 2NG2SS
I
I
L ____ ..J
I
I
L ____ ..J
O.1 ...F
O.1p.F
}---.. . .
-"""'~_-o
Il
=~
+ IBIAS
Rc
Figure 168. Precision High-Current Current Source
8-30 VOLTAGE REFERENCES
Figure 16b. Precision High-Current Voltage Source
High Precision
10V Reference
AD587 I
11IIIIIIII ANALOG
WDEVICES
FEATURES
Laser Trimmed to High Accuracy:
10.000V ±5mV (L and U Grades)
Trimmed Temperature Coefficient:
5ppml"C max. (L and U Grades)
Noise Reduction Capability
Low Quiescent Current: 4mA max
Output Trim Capability
AD587 FUNCTIONAL BLOCK DIAGRAM
NOISE
+ V 1N
REDUCTION
GROUND
NOTE: MAKE NO CONNECTIONS TO PINS 1. 7 AND 8.
PRODUCT DESCRIPTION
The AD587 represents a major advance in the state-of-the-art in
monolithic voltage references. Using a proprietary ion-implanted
buried Zener diode and laser wafer trimming of high stability
thin-film resistors, the AD587 provides outstanding performance
at low cost.
The AD587 offers much higher performance than most other
IOV references. Because the AD587 uses an industry standard
pinout, many systems can be upgraded instantly with the AD587.
The buried Zener approach to reference design provides lower
noise and drift than band-gap voltage references. The AD587
offers a noise reduction pin which can be used to further reduce
the noise level generated by the buried Zener.
The AD587 is recommended for use as a reference for 8-, 10-,
12-, 14- or 16-bit D/A converters which require an external
precision reference. The device is also ideal for successive approximation or integrating AID converters with up to 14 bits of
accuracy and, in general, can offer better performance than the
standard on-chip references.
PRODUCT HIGHLIGHTS
I. Laser trimming of both initial accuracy and temperature
coefficients results in very low errors over temperature without
the use of external components. The AD587L has a maximum
deviation from 10.000Vof ±8.5mV between 0 and +70°C,
and the AD587U guarantees ± 14mV maximum total error
between - 55°C and + 125°C.
2. For applications requiring higher precision, an optional finetrim connection is provided.
3. Any system using an industry standard pinout 10 volt reference
can be upgraded instantly with the AD587.
4. Output noise of the AD58? is very low, typically 4fLV POp. A
noise reduction pin is provided for additional noise filtering
using an external capacitor.
The AD587J, K and L are specified for operation from 0 to
+ 70°C, and the AD587S, T and U are specified for - 55°C to
+ 125°C operation. All grades are available in 8-pin cerdip. The
J version is also available in an 8-pin Small Outline IC (SOIC)
package for surface mount applications and the J and K grades
also come in an 8-pin plastic package.
VOL TAGE REFERENCES 8-31
SPEC IFICAli 0NS CT. =+25"1:, VII =+ 15V unless otherwise specified}
Model
Min
Output Voltage
9.990
AD587J/S
Typ Max
Min
10.010
Output Voltage Drift'
Oto +70"C
- 55°C to + 125°C
AD587KIT
Typ Max
9.995
10.005
+3
-1
Load Regulation'
Sourcing 0 < lOUT < lOrnA
T min to T max
Sinking - 10 < lOUT ...,..-+--.......>---0
V OUT
1kU
AD587
a. Electrical Turn-On
VOUT
Figure 6a. Transient Load Test Circuit
Ii••••••••••••
b. Extended Time Scale
c. Turn-on with l/LF CN
II
Figure 6b. Large-Scale Transient Response
Figure 6c. Fine Scale Settling for Transient Load
Figure 5. Turn-on Characteristics
VOL TAGE REFERENCES 8-35
In some applications, a varying load may be both resistive and
capacitive in nature, or the load may be connected to the AD587
by a long capacitive cable.
Figure 7 displays the output amplifier characteristics driving a
lOOOpF, 0 to lOrnA load.
> .....+ ......- .....- ...
V OUT
AD587
Figure 7a. Capacitive Load Transient Response Test
Circuit
Some confusion exists in the area of defining and specifying
reference voltage error over temperature. Historically, references
have been characterized using a maximum deviation per degree
Centrigrade; i.e., ppmrc. However, because of nonlinearities in
temperamre characteristics which originated in standard Zener
references (such as "S" type characteristics), most manufacmrers
have begun to use a maximum limit error band approach to
specify devices. This technique involves the measurement of the
output at 3 or more different temperamres to specify an output
voltage error band.
Figure 9 shows the typical output voltage drift for the AD587L
and illustrates the test methodology. The box in Figure 9 is
bounded on the sides by the operating temperature extremes,
and on the top and the bottom by the maximum and minimum
output voltages measured over the operating temperamre range.
The slope of the diagonal drawn from the lower left to the upper
right comer of the box determines the performance grade of the
device.
-----k=i
1
10.010
T
T
~'"
10.000
-2.
I
I
I
I
~
2.
LOAD REGULATION
The AD587 has excellent load regulation characteristics. Figure
8 shows that varying the load several rnA changes the output by
only a few fJ.V.
1000
500
+2
6
4
+4
+6
+8
+10
LOAD (mAl
-2
500
1000
Figure 8. Typical Load Regulation Characteristics
TEMPERATURE PERFORMANCE
The AD587 is designed for precision reference applications
where temperamre performance is critical. Extensive temperamre
testing ensures that the device's high level of performance is
maintained over the operating temperature range.
8-36 VOL TAGE REFERENCES
=
v... v••
---~~'~."
..
I
I
I
:
4.
TEMPERATURE -
Figure 7b. Output Response with Capacitive Load
SLOPE = T.C.
s.
so
~c
Figure 9. Typical AD587L Temperature Drift
Each AD587J, K, L grade unit is tested at 0, + 25°C and + 70°C.
Each AD587S, T, and U grade unit is tested at - 55°C, + 25°C
and + 125°C. This approach ensures that the variations of output
voltage that occur as the temperature changes within the specified
range will be contained within a box whose diagonal has a slope
equal to the maximum specified drift. The position of the box
on the vertical scale will change from device to device as initial
error and the shape of the curve vary. The maximum height of
the box for the appropriate temperamre range and device grade
is shown in Figure 10. Duplication of these results requires a
combination of high accuracy and stable temperamre control in
a test system. Evaluation of the AD587 will produce a curve
similar to that in Figure 9, but output readings may vary depending
on the test methods and equipment utilized.
DEVICE
GRADE
AD587J
AD587K
AD587L
AD587S
AD587T
AD587U
MAXIMUM OUTPUT CHANGE
(mV)
oTO + 70"C
- 55"C TO
+ 125°C
24
12
8.5
46
23
14
Figure 10. Maximum Output Change in mV
Applying the AD587
NEGATIVE REFERENCE VOLTAGE FROM AN AD587
The AD587 can be used to provide a precision - 1O.0OOV output
as shown in Figure 11. The V IN pin is tied to at least a + 3. SV
supply, the output pin is grounded, and the AD587 ground pin
is connected through a resistor, R s , to a-I SV supply. The
-lOY output is now taken from the ground pin (Pin 4) instead
of VOUT • It is essential to arrange the output load and the supply
resistor Rs so that the net current through the ADS87 is between
2.5mA and 1O.0mA. The temperature characteristics and longterm stability of the device will be essentially the same as that of
a unit used in the standard + lOY output configuration.
The ADS87 can also be used as a precision reference for multiple
DACs. Figure I3 shows the ADS87, the AD7628 dual DAC and
the AD712 dual op amp hooked up for single supply operation
to produce 0 to - lOY outputs. Because both DACs are on the
same die and share a common reference and output op amps;
the DAC outputs will exhibit similar gain TCs.
+15V
+15V
+3.5V ...... +26V
GND
,--+__..:.....
=..:1,- -10V
1nF*
Rs
2.SmA < ~ -IL <10mA
Figure 13. AD587 as a 10V Reference for a CMOS Dual
DAC
-15V
Figure ". AD587 as a Negative 10V Reference
USING THE AD587 WITH CONVERTERS
The ADS87 is an ideal reference for a wide variety of 8-, 12-,
14- and 16-bit AID and D/A converters. Several representative
examples follow.
PRECISION CURRENT SOURCE
The design of the ADS87 allows it to be easily configured as a
current source. By choosing the control resistor Rc in Figure
14, you can vary the load current from the quiescent current
(2mA typically) to approximately 10mA.
IOV REFERENCE WITH MULTIPLYING CMOS D/A OR
AID CONVERTERS
The AD587 is ideal for applications with 10- and 12-bit multiplying
CMOS D/A converters. In the standard hookup, as shown in
Figure 12, the ADS87 is paired with the AD7S4S 12-bit multiplying
DAC and the AD711 high-speed BiFET Op Amp. The amplifier
DAC configuration produces a unipolar 0 to - lOY output
range. Bipolar output applications and other operating details
can be found on the individual product data sheets.
.2
Figure 14. Precision Current Source
Figure 12. Low-Power 12-8it CMOS DAC Application
VOL TAGE REFERENCES 8-37
8
PRECISION HIGH CURRENT SUPPLY
For higher currents, the AD587 can easily be connected to a
power PNP or power Darlington PNP device. The circuit in
Figure 15 can deliver up to 4 amps to the load. The O.I/1F
+VIN
0-.._-----.....,
22011
r---- -,
I
I
I
: 2N&285
I
I
I
L ____ .J
capacitor is required only if the load has a significant capacitive
component. If the load is purely resistive, improved high-frequency
supply rejection results can be obtained by removing the
capacitor.
+V~O-.._-----.....,
r---- -,
220n
I
I
I
I
: 2N&285
I
I
L ____ .J
O.,..,F
;}---_'---'~-.....-o Il = ':: + (alAs
lie
Figure 15a. Precision High-Current Current Source
8-38 VOLTAGE REFERENCES
) - - - - 4 - - ~o.rov (a
4 AMPS
Figure 15b. Precision High-Current Voltage Source
r-IANALOG
WDEVICES
High Precision Voltage Reference
A0588* I
FEATURES
Low Drift - 1.5ppm/oC
Low Initial Error - 1mV
Pin-Programmable Output
+10V. +5V. ±5VTracking. -5V. -10V
Flexible Output Force and Sense Terminals
High Impedance Ground Sense
Machine-Insertable DIP and Surface Mount Packaging
AD588 FUNCTIONAL BLOCK DIAGRAM
AlOUT
A31N
SENSE
3}---...,
+v.
"3
-v.
PRODUCT DESCRIPTION
The ADS88 represents a major advance in the state-of-the-art in
monolithic voltage references. Low initial error and low temperature drift give the ADS88 absolute accuracy performance previously not available in monolithic form. The ADS88 uses a proprietary ion-implanted buried Zener diode, and laser-wafer-drifttrimming of high stability thin-film resistors to provide outstanding
performance at low cost.
The ADS88 includes the basic reference cell and three additional
amplifiers which provide pin-programmable output ranges. The
amplifiers are laser-trimmed for low offset and low drift to
maintain the accuracy of the reference. The amplifiers are configured to allow Kelvin connections to the load and/or boosters
for driving long lines or high-currem loads, delivering the full
accuracy of the ADS88 where it is required in the application
circuit.
The low initial error allows the ADS88 to be used as a system
reference in precision measurement applications requiring 12-bit
absolute accuracy. In such systems, the ADS88 can provide a
known voltage for system calibration in software and the low
drift allows compensation for the drift of other components in a
system. Manual system calibration and the cost of periodic
recalibration can therefore be eliminated. Furthermore, the
mechanical instability of a trimming potentiometer and the
potemial for improper calibration can be eliminated by using
the ADS88 in conjunction autocalibration software.
The ADS88 is available in six versions. ADS88AD and BD
grades are packaged in a l6-pin side-brazed ceramic DIP and
are specified for the - 2S·e to + 8s·e industrial temperature
range. The ceramic ADS88SD and TD grades are specified for
GAIN
ADJ
9
10
GND
SENSE
GND
SENSE
+IN
-IN
v,ow
VCT
A41N
the full military/aerospace temperature range. For surface mount
applications, the ADS88AE, SE and TE grades will also be
available in 20-pin Lee packages.
PRODUCT HIGHLIGHTS
I. The ADS88 offers l2-bit absolute accuracy without any user
adjustments. Optional fine-trim connections are provided for
applications requiring higher precision. The fine-trimming
does not alter the operating conditions of the Zener or the
buffer amplifiers and thus does not increase the temperature
drift.
2. Output noise of the ADS88 is very low - typically 6",V POp.
A pin is provided for additional noise filtering using an external
capacitor.
3. A precision ± SV tracking mode with Kelvin output connections is available with no external components. Tracking
error is less than one millivolt and a fine-trim is available for
applications requiring exact symmetry between the + SV and
- SV outputs.
4. Pin strapping capability allows configuration of a wide variety
of outputs: ±SV, +SV& +lOV, -SV& -IOVdualoutputs
or +SV, -SV, +IOV, -10V single outputs.
S. Extensive temperature testing at - ss·e, - 2S·e, 0, + 2S·e,
+ so·e, + 70·e, + 8S·e and + 12S·e ensures that the specified
temperature coefficient is truly representative of device
performance.
·Covered by Patent Number 4,644,253
VOL TAGE REFERENCES 8-39
II
SPECIFICATIONS
(typicaI@
+2ft. + lOVoulput,Ys= ±15YunlessolbalwisanolBd1)
Min
AD588SD/SE
Typ
Max
AD588ADITD/AEITE
Min
Typ
Max
Min
OUTPUT VOLTAGE ERROR
+IOV, -IOVOutputs
+ SV, - SV Outputs
-5
-5
+5
+5
-3
-3
+3
+3
± 5VTRACKING MODE
Symmetry Error
-1.5
+1.5
-1.5
+1.5
+6
-3
-4
OUTPUT VOLTAGE DRIFT
Oto +70"C(A,B,C)
-25°C to +SSOC(A,B)
- WC to + 125°C(S, T)
±2
-6
GAIN AD] AND BAL AD]2
Trim Range
Input Resistance
±4
ISO
+3
+4
AD588BD
Typ
Max
Units
-1
-1
+1
+1
mV
mV
-0.75
+0.75
mV
-1.5
-3
+1.5
+3
ppml"C
ppml"C
ppml"C
±4
150
mV
k!l
±4
150
LINE REGULATION
Tminto Tmax
3
LOAD REGULATION
T min toTmax
+ IOV Output, Or
NOISE
REDUCTION
GND SENSE -IN
LCC
,, ,,
...
A3 OUT SENSE 4
18 A4 OUT SENSE
17 A41N
A31N 5
AD588
NC 6
(Not to Scale)
GAIN ADJ 7
9
2
10 11
Q ~
wI:; >
",=>
6[D
211:
NC
= NO CONNECT
16 NC
TOP VIEW
CJ
2
12
w
15 BAl ADJ
13
w
'"22
22
w- '"
w-
",+
",I
Q
Q
2
2
" "
Amplifier Al performs several functions. Al primarily acts to
amplify the Zener voltage from 6.5V to the required IOV output.
In addition, Al also provides for external adjustment of the IOV
output through pin 5, the GAIN ADJUST. Using the bias
compensation resistor between the Zener output and the non-inverting input to AI, a capacitor can be; added at the NOISE
REDUCTION pin (pin 7) to form a low pass filter and reduce
the noise contribution of the Zener to the circuit. Two matched
10k!} nominal thin mffi resistors (R4 & RS) divide the 10V
output in half. Pin Vcr (pin 11) provides access to the center of
the voltage span and pin 12 (BALANCE ADJUST) can be used
for fme adjustment of this division.
Ground sensing for the circuit is provided by amplifier A2. The
noninverting input (pin 9) senses the system ground which will
be transferred to the point on the circuit where the inverting
input (pin 10) is connected. This may be pin 6,8 or II. The
output of A2 drives pin 8 to the appropriate voltage. Thus, if
pin 10 is connected to pin 8, the VLOW pin will be the same
voltage as the system ground. Alternatively, if pin 10 is connected
to the Vcr pin, it will be ground and pin 6 and pin 8 will be
+ 5V and - 5V respectively.
Amplifiers A3 and A4 are internally compensated and are used
to buffer the voltages at pins 6, 8 and 11 as well as to provide a
full Kelvin output. Thus, the AD588 has a full Kelvin capability
by providing the means to sense a system ground and provide
forced and sensed outputs referenced to that ground.
VOLTAGE REFERENCES 8-41
I
Applying the A0588
APPLYING THE ADS88
The AD588 can be configured to provide + lOY and - lOY
reference outputs as shown in Figures 2a and 2c respectively. It
can also be used to provide + 5V, - 5V or a ± 5V tracking
reference as shown in Figure 2b. Table I details the appropriate
pin connections for each output range. In each case, pin 9 is
connected to system ground and power is applied to pins 2
and 16.
The architecture of the AD588 provides ground sense and uncommitted output buffer amplifiers which offer the user a great
deal of functional flexibility. The AD588 is specified and tested
in the configurations shown in Figure 2. The user may choose
to take advantage of the many other configuration options available
with the AD588. However, performance in these configurations
is not guaranteed to meet the extremely stringent data sheet
specifications.
As indicated in Table I, a + 5V buffered output can be provided
using amplifier A4 in the + IOV configuration (Figure 2a). A
- 5V buffered output can be provided using amplifier A3 in the
-IOV configuration (Figure 2c). Specifications are not guaranteed
for the + 5V or - 5V outputs in these configurations. Performance
will be similar to that specified for the + IOV or -lOY outputs.
As indicated in Table I, unbuffered outputs are available at pins
6, 8 and II. Loading of these unbuffered outputs will impair
circuit performance.
Amplifiers A3 and A4 can be used interchangeably. However,
the AD588 is tested (and the specifications are guaranteed) with
the amplifiers connected as indicated in Figure 2 and Table I.
When either A3 or A4 is unused, its output force and sense pins
should be connected and the input tied to ground.
Two outputs of the same voltage may be obtained by connecting
both A3 and A4 to the appropriate unbuffered output on pin 6,
8 or 11. Performance in these dual output configurations will
typically meet data sheet specifications.
Range
Connect
Pin 10
to Pin:
+IOV
8
-5Vor+5V
-IOV
CALIBRATION
Generally, the AD588 will meet the requirements of a precision
system without additional adjustment. Initial output voltage
error of ImV and output noise specs of IOILV POp allow for
accuracies of 12-16 bits. However, in applications where an even
greater level of accuracy is required, additional calibration may
be called for. Provision for trimming has been made through
the use of the GAIN ADJUST and BALANCE ADJUST pins
(pins 5 and 12 respectively).
The AD588 provides a precision IOV span with a center tap
-0-......- - - +tOV
;}-.....- - - + 5 V
~-e--
-15V
SYSTEM
r--------....
+ 10V
Input impedance on both the GAIN ADJUST and BALANCE
ADJUST pins is approximately 150kO. The GAIN ADJUST
trim network effectively attenuates the 10V across the trim
potentiometer by a factor of about 1500 to provide a trim range
of - 3.5mV to + 7.5mV with a resolution of approximately
550JLV/turn (20 turn potentiometer). The BALANCE ADJUST
trim network attenuates the trim voltage by a factor of about
1400, providing a trim range of ±4.SmV with resolution of
450f.LV/turn.
Trimming the AD588 introduces no additional errors over temperature so precision potentiometers are not required.
GROUND
Figure 2a.
In single output configurations, GAIN ADJ is used to trim
outputs utilizing the full span ( + lOV or - lOY) while BAL
ADJ is used to trim outputs using half the span (+ 5V or
-5V).
Output
For single output voltage ranges, or in cases when BALANCE
ADJUST is not required, pin 12 should be connected to pin 11.
If GAIN ADJUST is not required, pin S should be left floating.
39kn
--.~"""- +15V
>-C0--~-- +5V
i}-......- - - - 5 V
NOISE PERFORMANCE AND REDUCTION
The noise generated by the AD588 is typically less than 6JLV
p-p over the O.IHz to 10Hz band. Noise in a IMHz bandwidth
is approximately 600JLV p-p. The dominant source of this noise
is the buried Zener which contributes approximately lOOnV/YHZ.
In comparison, the op amp's contribution is negligible. Figure 3
shows the O.IHz to 10Hz noise of a typical AD588.
'-~.......--t5V
lOOk
20T
GAIN ADJUST
Figure 2b. +5Vand -5V Outputs
Figure 3. O. 1Hz to 10Hz Noise
)--+----5V
>-®-......- - -tOV
'--e---15V
If further noise reduction is desired, an optional capacitor may
be added between the NOISE REDUCTION pin and ground as
shown in Figure 2b. This will form a low pass filter with the
4kO Rs on the output of the Zener cell. A IJLF capacitor will
have a 3dB point at 40Hz and will reduce the high frequency
(to IMHz) noise to about 200JLV pop. Figure 4 shows the IMHz
noise of a typical AD588 both with and without a IJLF
capacitor.
Note that a second capacitor is needed in order to implement
the NOISE REDUCTION feature when using the AD588 in
the -lOY mode (Figure 2c.). The NOISE REDUCTION
capacitor is limited to O.IJLF maximum in this mode.
Figure 2c. - 10V Output
VOL TAGE REFERENCES 8-43
+V.
I
CN""'p.F
-
->
---T-
j
j
I
-VS
NOCN
~
! _1- ~
I
VO""
Figure 6. Turn-on with 1p.F CN
Figure 4. Effect of 1p.F Noise Reduction Capacitor on
Broadband Noise
TURN-ON TIME
Upon application of power (cold start), the time required for the
output voltage to reach its final value within a specified error
band is the turn-on settling time. Two components normally
associated with this are: time for active circuits to settle and
time for thermal gradients on the chip to stabilize. Figure 5
shows the turn-on characteristics of the AD588. It shows the
settling to be about 6OOILS. Note the absence of any thermal
tails when the horizontal scale is expanded to 2ms/cm in
Figure 5b.
...
omt
J!Ei'I
U
'~····
I
00 S
TEMPERATURE PERFORMANCE
The AD588 is designed for precision reference applications
where temperature performance is critical. Extensive temperature
testing ensures that the device's high level of performance is
maintained over the operating temperature range.
. Figure 7 shows typical output voltage drift for the AD588BD
and illustrates the test methodology. The box in Figure 7 is
bounded on the sides by the operating temperature extremes
and on top and bottom by the maximum and minimum output
voltages measured over the operating temperature range. The
slope of the diagonal drawn from the lower left comer of the
box determines the performance grade of the device.
OUTPUT
VOLTS
10.002
L/1
I
~
VMAX-VMlN
SL PE "" T.C. = IT......-T
10xl0-
I
~
~
1
l
II
10.001
=
1
"1'
Y10.000
I'
m1n ) x
1
lD,0013V - 10.OD025V
(85OC - -25'"<:1 x 10X 10- 8
_
I
I
I
I
= O.95ppmf'C
I
I
-36 :-15
5
25 45 65
I
TEMPERATURE - "C
Tmln
85
I
T_
a. Electrical Turn-On
Figure 7. Typical AD588BD Temperature Drift
Om
+Vs
H
, ••...
~
1
11
V II,
..1.....
0'
0'
mS
11.0
......
I::
=
VOUT
b. Extended Time Scale
Figure 5. Turn-On Characteristics
Each AD588A and B grade unit is tested at - 25°C, O°C, + 25°C,
+ 50°C, + 70°C and + 85°C. Each AD588S and T grade unit is
tested at - 55°C, - 25°C, O°C, + 25°C, + 50°C, + 70°C and
+ 125°C. This approach ensures that the variations of output
voltage that occur as the temperature changes within the specified
range will be contained within a box whose diagonal has a slope
equal to the maximum specified drift. The position of the box
on the vertical scale will change from device to device as initial
error and the shape of the curve vary. Maximum height of the
box for the appropriate temperature range is shown in Figure 8.
Duplication of these results requires a combination of high
accuracy and stable temperature control in a test system. Evaluation
of the AD588 will produce a curve similar to that in Figure 7,
but output readings may vary depending on the test methods
and equipment utilized.
MAXIMUM OUTPUT CHANGE
Output turn-on time is modified when an external noise reduction
capacitor is used. When present, this capacitor presents an
additional load to the internal Zener diode's current source,
resulting in a somewhat longer tum-on time. In the case of a
l ....F capacitor, the initial turn-on time is approximately 60ms
(see Figure 6).
Note: If the NOISE REDUCTION feature is used in the ± 5V
configuration, a 39kfl resistor between pins 6 and 2 is required
for proper startup.
8-44 VOLTAGE REFERENCES
DEVICE
GRADE
mY
o TO
+70"C
-25"C TO +85OC
AD588AD
1.40 (typl
3.30
AD588BD
1.05
3.30
- 55"C TO
+ 125 C
AD588SD
10.80
AD588TD
7.20
G
Figure 8. Maximum Output Change - mV
Using Buffer Amplifiers - AD588
R
KELVIN CONNECTIONS
Force and sense connections, also referred to as Kelvin connections, offer a convenient method of eliminating the effects of
voltage drops in circuit wires. As seen in Figure 9a, the load
current and wire resistance produce an error (VERROR = Rx I L )
at the load. The Kelvin connection of Figure 9b overcomes the
problem by including the wire resistance within the forcing loop
of the amplifier and sensing the load voltage. The amplifier
corrects for any errors.in the load voltage. In the circuit shown,
the output of the amplifier would actually be at 10 volts +
V ERROR and the voltage at the load would be the desired 10
volts.
The AD588 has three amplifiers which can be used to implement
Kelvin connections. Amplifier AZ is dedicated to the ground
force-sense function while uncommitted amplifiers A3 and A4
are free for other force-sense chores.
In some single-output applications, one amplifier may be unused.
100
'!!
I
Z
~
.. "'-"
0
15
40
9
z
~
-
' ,PHAS!
'" Gf.>."
~
"
20
,.
-20
10
IOV
V=10V-RIL
~
~
~
RLoAo
I,
a.
b.
Figure 9. Advantage of Kelvin Connection
In such cases, the unused amplifier should be connected as a
unity-gain follower (force + sense pin tied together) and the
input should be connected to ground.
An unused amplifier section may be used for other circuit functions
as well. The curves on this page show the typical performance
of A3 and A4.
110
,,
"
60
R
100
VS=±15V
VCM = 1V pop +2Sg C
"
-eo
100
I
I
Z
"
,
-~~
'" '"
10k
90
\
~
<
..
~
.. .
I
'"'"
u
i
w
\
-120
,
\
\
40
-150
20
180
10M
•
['-..\
lOOk
"
80
'!!
1M
10
1.
100
FREQUENCY - H;j:
Open Loop Frequency Response (A3, A4)
~
10k
lOOk
FREQUENCY - Hl
I'"
1M
II
10M
Common Mode Rejection vs. Frequency (A3, A4)
11 0
100
Vs" :!:15VWITH
W p.p SINE WAVE
so
~~ 80
100
'":""
>
I'
~PPLY
7.
i
00
~
50
"
;2
~
~
0
100
I
\
1\
c
0
10
~
+SUPPLY
10k
40
!l;
ill
0
z
~
lOOk
1M
' .....
30
20
10
10M
fREQUENCY - Hz
0,
I.
I ••
1k
10'
FREQUENCY - Hl
Power Supply Rejection vs. Frequency (A3, A4)
Input Noise Voltage Spectral Density
0)1
5
.!.......
:l
·I~
r~
iJJ
I
'1+III'
nL
.
M
l'I
I
II
. , ... .... ....
Unity Gain Follower Pulse Response (Large Signal)
Unity Gain Follower Pulse Response (Small Signal)
VOL TAGE REFERENCES 8-45
DYNAMIC PERFORMANCE
The output buffer amplifiers (A3 and A4) are designed to provide
the ADS88 with static and dynamic load regulation superior to
less complete references.
Many AID and DlA converters present transient current loads
to the reference, and poor reference response can degrade the
converter's performance.
VOUT
'mV/eM
VOUT
200mVlCM
Figure 10 displays the characteristics of the ADS88 output
amplifier driving a 0 to IOmA load.
Figure 77b. Transient Response 5-70mA Load
In some applications, a varying load may be both resistive and
capacitive in nature, or be connected to the ADS88 by a long
capacitive cable.
Figure 70a. Transient Load Test Circuit
_ olm
500 S
5V
:=
U
'z·l l· ...
I
II
I~
I~I
-
,III ...I.I....
II'
I!J...
..
. . . . I. . . .
I
I
Figure 72a. Capacitive Load Transient Response Test
Circuit
III
Figure 70b. Large-Scale Transient Response
~-~
~l=V
sv
·
,z2~1.IV
•
bSI
lit I
... ....
I
.,
I
....
II
I II
I
I
I
i,
±
I
I
·1·1...
5V
I··
II
I
I
Figure 72b. Output Response with Capacitive Load
Figure 70e. Fine Scale Settling for Transient Load
Figure II displays the output amplifier characteristics driving a
SmA to lOrnA load, a common situation found when the reference
is shared among multiple converters or is used to provide a
bipolar offset current.
Figure 13 displays the crosstalk between output amplifiers. The
top trace shows the output of A4, dc-coupled and offset by 10
volts, while the output of A3 is subjected to a O-to-lOmA load
current step. The transient at A4 settles in about I."s, and the
load-induced offset is about 100."V.
?
+A4
VOUT
+
2k
Figure 11a. Transient and Constant Load Test Circuit
lk
10V
_
8-46 VOL TAGE REFERENCES
11~S
II ..
E'I
i
,I
.g....
~
I
H
.. II....1.
II
!~
... . .. . . . . \ . .
I~
,
Figure 12 displays the output amplifier characteristics driving a
1,ooOpF, O-to-IOmA load.
VL
ill
!~V
Figure 73a. Load Crosstalk Test Circuit
',. +
11-IV
5V
1
AD588
lMO
I_ill
~~
,."
!!II
I I-j
•
'I
liN
.. ,
II
I
'IpS
-=
I
!II
,,-
I' d
1-
-
i-'-
"I '
•
-
t-,
II
1' I I i I
,
Figure 14b. Compensation for Capacitive Loads
Figure 13b. Load Crosstalk
Attempts to drive a large capacitive load (in excess of I,OOOpF)
may result in ringing or oscillation, as shown in the step response
photo (Figure 14a). This is due to the additional pole formed by
the load capacitance and the output impedance of the amplifier,
which consumes phase margin. The recommended method of
driving capacitive loads of this magnitude is shown in Figure
14b. The ISOn resistor isolates the capacitive load from the
output stage, while the IMn resistor provides a dc feedback
path and preserves the output accuracy. The ISOpF capacitor
provides a high-frequency feedback loop. The performance of
this circuit is shown in Figure 14<:.
I
U
'Z
ii i
riO
IS '!liS
I' II
V ,N
t
-1
VOUT
1-
1111'
nL1" i'grJ.. , , 'n: .... '1"1,1......
rA
111
I
I
Figure 14c. Output Amplifier Step Response Using Figure
14b Compensation
USING THE AD588 WITH CONVERTERS
The ADS88 is an ideal reference for a wide variety of AID and
D/A converters, Several representative examples follow.
14-Bit Digital-to-Analog Converter - AD7535
High resolution CMOS D/A converters require a reference voltage
of high precision to maintain rated accuracy. The combination
of the AD588 and AD7535 takes advantage of the initial accuracy,
drift and full Kelvin output capability of the AD588 as well as
the resolution, monotonicity and accuracy of the AD7535 to
produce a subsystem with outstanding characteristics.
Figure 14a. Output Amplifier Step Response, CL = 1/LF
N.C.
Voo
Figure 15. AD588IAD7535 Connections
VOL TAGE REFERENCES 8-47
•
,----------------t--------
r----------------+------.---
+12V
-12V
AD569
17 Vour
-5VTO
+5V
AD588
Figure 16. High-Accuracy ±5V Tracking Reference for
AD569
16-Bit Digital-to-Analog Converter - ADS69
Another application which fully utilizes the capabilities of the
AD588 is supplying a reference for the AD569, as shown in
Figure 16. Amplifier A2 senses system common and forces Vcr
to assume this value, producing + 5V and - 5V at pins 6 and 8
respectively. Amplifiers A3 and A4 buffer these voltages out to
the appropriate reference force-sense pins of the AD569. The
full Kelvin scheme eliminates the effect of the circuit traces or
wires and the wire bonds of the AD588 and AD569 themselves,
which would otherwise degrade system performance.
SUBSTITUTING FOR INTERNAL REFERENCES
Many converters include built-in references. Unfortunately,
such references are the major source of drift in these converters.
By using a more stable external reference like the ADS88, drift
performance can be improved dramatically.
12-Bit Analog-to-Digital Conveter - ADS74A
The AD574A is specified for gain drift from lOppmf'C to SOppm/
°C, (depending on grade) using the on-chip reference. The
reference contributes typically 75% of this drift. Therefore, the
total drift using an AD588 to supply the referehce can be improved
by a factor of 3 to 4.
STS
HIGH
BITS
MIDDLE
BITS
AD574A
REF IN
rL
I
____________ _
Figure 17. AD588IAD574A Connections
8-48 VOL rAGE REFERENCES
AD588
Using this combination may result in apparent increases in fullscale error due to the difference between the on-board reference
by which the device is laser trimmed and the external reference
with which the device is actually applied. The on-board reference
is specified to be lOY ± IOOmV while the externid reference is
specified to be lOY ± ImV. This may result in up to IOlmV of
apparent full-scale error beyond the ± 2SmV specified ADS74
gain error. Resistors R2 and R3 allow this error to be nulled.
Their contribution to full-scale drift is negligible.
BOOSTED PRECISION CURRENT SOURCE
In the RTD current-source application the load current is limited
to ± IOmA by the output drive capability of amplifier A3. In
the event that more drive current is needed, a series pass transistor
can be inserted inside the feedback loop to provide higher current.
Accuracy and drift performance are unaffected by the pass
transistor.
The high output drive capability allows the ADS88 to drive up
to 6 converters in a multi-converter system. All converters will
have gain errors that track to better than ± Sppm/"C.
RTD EXCITATION
The Resistance Temperature Detector (RTD) is a circuit element
whose resistance is characterized by a positive temperature coefficient. A measurement of resistance indicates the measured
temperature. Unfortunately, the resistance of the wires leading
to the RTD often adds error to this measurement. The 4-wire
ohms measurement overcomes this problem. This method uses
two wires to bring an excitation current to the RTD and two
additional wires to tap off the resulting RTD voltage. If these
additional two wires go to a high input impedance measurement
circuit, the effect of their resistance is negligible. Therefore,
they transmit the true RTD voltage.
Figure 20. Boosted Precision Current· Source
i=O
R
--<[
BRIDGE DRIVER CIRCUITS
-
w~:
i =O
Figure 18. 4-Wire Ohms Measurement
A practical consideration when using the 4-wire ohms technique
with an RTD is the self-heating effect that the excitation current
has on the temperature of the RTD. The designer must choose
the smallest practical excitation current that still gives the desired
resolution. RTD manufactures usually specify the self-heating
effect of each of their models or types of RTDs.
Figure 19 shows an ADS88 providing the precision excitation
current for a lOOn RTD. The small excitation current of ImA
dissipates a mere O.lmW of power in the RTD.
The Wheatstone bridge is a common transducer. In its simplest
form, a bridge consists of 4 two terminal elements connected to
form a quadrilateral, a source of excitation connected along one
of the diagonals and a detector comprising the other diagonal.
Figure 21a shows a simple bridge driven from a unipolar excitation
supply. Eo, a differential voltage, is proportional to the deviation
of the element from the initial bridge values. Unfortunately, this
bridge output voltage is riding on a common-mode voltage equal
to approximately VIN/2. Further processing of this signal may
necessarily be limited to high common-mode rejection techniques
such as instrumentation or isolation amplifiers.
Figure 21b shows the same bridge transducer, but this time it is
driven from pair of bipolar supplies. This configuration ideally
eliminates the common-mode voltage and relaxes the restrictions
on any processing elements that follow.
R,
VI$HAV S102C
OR SIMILAR
+
a. Unipolar Drive
VOUT
RTD =
OMEGA K4515
O.24-cJmW SELF HEATING
Figure 19. Precision Current Source for RTD
b. Bipolar Drive
Figure 21. Bridge Transducer Excitation
VOLTAGE REFERENCES 8-49
I_
+15V
Figure 22. Bipolar Bridge Drive
As shown in Figure 22, the AD588 is an excellent choice for the
control element in a bipolar bridge driver scheme. Transistors
Q I and Q2 serve as series pass elements to boost the current
drive capability to the 28mA required by a typical 3500 bridge.
A differential gain stage may still be required if the bridge balance
is not perfect. Such gain stages can be expensive.
Additional common-mode voltage reduction is realized by using
the circuit illustrated in Figure 23. AI, the ground sense amplifier,
servo's the supplies on the bridge to maintain a virtual ground
at one center tap. The voltage which appears on the opposite
center tap is now single-ended (referred to ground) and can be
amplified by a less expensive circuit.
+15V
Figure 23. Floating Bipolar Bridge Drive with Minimum
CMV
8-50 VOL TAGE REFERENCES
11IIIIIIII ANALOG
WDEVICES
FEATURES
Superior Replacement for Other 1.2V References
Wide Operating Range: 50",A to 5mA
Low'Power: 60",W Total Po at 50",A
Low Temperature Coefficient:
10ppmfC max, 0 to +70°C (AD589M)
25ppmfC max, _55°C to +125°C (AD589U)
Two Terminal "Zener" Operation
Low Output Impedance: O.6n
No Frequency Compensation Required
Low Cost
Two-TerminallC
1.2V Reference
AD589 I
ADS89 FUNCTIONAL BLOCK DIAGRAM
V+
VBOTTOM VIEW
PRODUCT DESCRIPTION
The AD589 is a two-tenninal, low cost, temperature compensated.bandgap voltage reference which provides a fixed
lo23V output voltage for input currents between SOIlA and
S.OmA.
The high stability of the ADS89 is primarily dependent upon
the matching and thennal tracking of the on-chip components.
Analog Devices' precision bipolar processing and thin-film
technology combine to provide excellent perfonnance at
low cost.
Additionally, the active circuit produces an output impedance
ten times lower than typicallow-TC zener diodes. This feature allows operation with no external components required
to maintain full accuracy under changing load conditions.
The ADS89 is available in seven versions. The ADS89J. K. L
and M grades are specified for 0 to +70° C operation, while
the S, T and U grades are rated for the full-55°C to +12S oC
temperature range.
PRODUCT HIGHLIGHTS
1. The ADS89 is a two-tenninal device which delivers a
a constant reference voltage for a wide range of input
current.
2. Output impedance of 0.6n and temperature coefficients
as low as 1Oppmf C insure stable ou tpu t voltage over a
wide range of operating conditions.
3. The ADS89 can be operated as a positive or negative
reference. "Floating" operation is also possible.
4. The ADS89 will operate with total current as low as SO",A
(60",W total power dissipation), ideal for battery powered
instrument applications.
S. The ADS89 is an exact replacement for other 1.2V references, offering superior temperature performance and
reduced sensitivity to capacitive loading.
VOL TAGE REFERENCES 8-51
I
SPECIFICATIONS
(typical @ lIN
Model
Min
OUTPUT VOLTAGE, TA = +25"C
= 500JIA aIid TA = +25"1: unless otherwise noted)
ADS89JH
Typ
Max
1.235
1.250
DYNAMIC OUTPUT IMPEDANCE
0.6
2
RMS NOISE VOLTAGE
10Hz
I
w 1.2360
'~"
g
0-
1.2355
i20-
B
V
/ .....
-
............
" "I'.
/
II
1.2350
-25
DYNAMIC PERFORMANCE
Many low power insttument manufacturers are becoming increasingly concerned with the turn-on characteristics of the
components being used in their systems. Fast turn-on components often enable the end user to keep power off when not
needed, and yet respond quickly when the power is turned on
for operation. Figure 3 displays the turn-on characteristic of
the AD589. This characteristic is generated from cold-start
operation and represents the true turn-on waveform after an
extended period with the supplies off. The figure shows both
the coarse and fine transient characteristics of the device; the
total settling time to within ±l millivolt is about 25[.ls, and
there is no long thermal tail appearing after that point.
+25
+75
+50
TEMPERATURE _
"
.........
+100
I
+125
Figure 3. Output Settling Characteristics
°c
Figure 1. Typical AD589 Temperature Characteristics
v+--~t-------~t----------------.----,
1000
R6
~:;;
I
>
0-
1'-1"-
100
" I'-
iii
zw
..
Q
-'
II:
0-
&l
Q9
lD
ll;
w
~
10
100
l'
10k
FREQUENCY - Hz
Figure 2. Noise Spectral Density
lOOk
1M
v---~~----~------~--------e---~
Figure 4. Schematic Diagram
VOLTAGE REFERENCES 8-53
---.-----~----~V
S.6kl"!
APPLICATION INFORMATION
The ADS89 functions as a two-tenninal shunt-type regulator.
It provides a constant 1.23V output for a wide range of input
current from SOj.tA to SmA. Figure S shows the simplest configuration for an output voltage of 1.2V or less. Note that no
frequency compensation is required. If additional filtering is
desired for ultra low noise applications, minimum recommended capacitance is lOOOpF.
6.6kl"!
V+
AD589
7109
2kl"!
~"""--iREF+
'---....----1 REFL-_ _-j REF OUT
- - 4 1 - - - - - - - +5V
6.8kl"!
+
+
AD589
a. With 7109 12-Bit Binary AID
VOUT
--~--------~--+5V
6.2kl"!
Figure 5. Basic Configuration for 1.2Vor Less
V+
7107
10kl"!
The ADS89 can also be used as a building block to generate
other values of reference voltage. Figure 6 shows a circuit
which produces a buffered lOV output. Total supply current
for this circuit is approximately 2mA.
~----i REF HI
lkl"!
'----~----__lREFLO
COMMON
AD589
b. With 7107 Panel Meter AID
r~I-----o+
10V
lkl"!
'-----_-< lkl"!
~-
8.2kl"!
Figure 7. AD589 Used as Reference for CMOS AID Converters
The ADS89 also is useful as a reference for CMOS multiplying DACs such as the AD7S33. These DACs require a
negative reference voltage in order to provide a positive output range. Figure 8 shows the AD589 used to supply an equivalent -1.0V reference to an AD7533.
BIT
1 2
Figure 6. Single-Supply Buffered 10V Reference
The low power operation of the ADS89 makes it ideal for use
in battery operated portable equipment. It is especially useful
as a reference for CMOS analog-to-digital converters. Figure 7
shows the ADS89 used in conjunction with two popular integrating type CMOS AID converters.
3
4
5
6
7
8
9
BIT
10
VDD 14
REF
....--J\M_---j15
AD7533 SERIES
R2
3~h
5kl"!
GND 3
16
-15V
RoB
>-_-0+ VOUT
=
~OtOl.00V
Figure 8. AD589 as Reference for 10-Bit CMOS DAC
8-54 VOLTAGE REFERENCES
High Precision
8.192V Reference
AD689 I
~ANALOG
WDEVICES
FEATURES
Laser Trimmed to High Accuracy:
8.192V :r4mV IL, T Grades)
Input Voltage Range from 10.8V to 36V
Provides Convenient Scaling for Converters:
2mV/LSB for 12-Bit Converters
Trimmed Temperature Coefficients:
5ppml"C max, 0 to + 70·C IL Grade)
10ppmI"C max, - 55 to + 125"C IT Grade)
Noise Reduction Capability
Versatile Force and Sense Connections
AD689 FUNCTIONAL BLOCK DIAGRAM
NOISE REOUCTION
~--------~8}--------,
AD689
V OUT
FORCE
V OUT
SENSE
TRIM
PRODUCT DESCRIPTION
The AD689 is the industry's first precision reference to deliver
a voltage between traditional 5V and 10V references. The AD689
will accurately deliver 8.192V while operating on supply voltages
of ± 12V, with ± 10% tolerances. All 10V references require
greater than 10.8V (12V-IO%) to operate properly, forcing the
use of 5V references in most 12V systems. An 8.192V reference
provides a major increase in signal range. The AD689 also
features excellent static and dynamic line and load regulation
characteristics.
The AD689 uses a proprietary ion-implanted buried Zener
diode and laser wafer trimming of high stability thin-mm resistors.
Trimming is performed for initial accuracy and temperature
coefficient, resulting in very low errors over temperature without
the use of additional components.
The AD689 includes the reference cell and an amplifier which is
laser trimmed for low drift. Force and sense connections can be
made on both the amplifier output and ground to maintain the
accuracy of the reference cell. This allows the AD689 to be used
with boosters for driving long lines or high current loads while
maintaining full accuracy at the load.
GND
SENSE
GND
PRODUCT HIGHLIGHTS
I. Laser trimming of both the initial accuracy and the temperature
coefficient results in very low errors over temperature without
the use of external components.
2. For applications requiring higher initial accuracy, an optional
fme trim connection is provided. The trim range allows the
output voltage to be accurately set down to 8.000V.
3. Output noise of the AD689 is very low, typically 2ILV p-p. A
noise reduction pin is provided for additional noise mtering
with an external capacitor.
4. Force and sense connections allow remote sensing of load
and ground variations to accurately supply 8.192V at the
load.
5. The AD689 sources and sinks current with excellent regulation,
allowing a variety of both positive and negative output voltage
configurations.
The AD689 is recommended for use in all data conversion applications where ± 12V ± 10% supplies preclude the use of both
external and intemallOV references.
The AD689J, K and L are tested and specified for operation
from 0 to + 70°C, and the AD689S and T are tested and specified
for - 55°C to + 125°C operation. All grades are packaged in an
8-pin cerdip.
VOL rAGE REFERENCES 8-55
8
SPECIFICATIONS
CTa = +25OC, VIII = +12V, ±111% unless othenvisespecifiad}
AD689J
Model
Min
Output Voltage
8.176
Typ
Output Voltage Drift'
Oto +70·C
- 55·C to + 125·C
Gain Adjustment
AD689K
Max
Min
Typ
AD689L
Max
Min
Typ
AD689S
Max
Typ
Min
8.208 8.184
8.200 8.188
8.196 8.176
25
15
5
Max
Min
8.196 V
20
10
ppmfC
+8
+8
+8
+8
+8
-3
-3
-3
-3
200
200
Units
8.208 8.188
-3
Line Regulation
1O.8V < + VIN <36V
Tminto Tmax
AD689T
Typ Max
200
%
250
250
±jJ.VN
Load Regulation
SourcingO< lOUT <8.192rnA
Sinking - 8.192 < lOUT 8.192Vr.' 4A
Figure 18a. Precision High-Current Voltage Source
+------
-8.192V
{SmA+ILOAOI Rs==12-S.192V
Rs
-12V
WHERE,l lOAD ,..S.192mA
IF ILOAD =8.192mA
THEN Rs=288U
Figure 16. AD6B9 as a Negative B.192V Reference
PRECISION CURRENT SOURCE
The d~ign of the AD689 allows it to· be easily configured as a
precision current source. By choosing the control resistor Rc in
Figure 17, you can vary the load current (10 from the quiescent
8-62 VOLTAGE REFERENCES
Figure 1Bb. Precision High-Current Current Source
Low Cost, Precision
2.5V IC References
ANALOG
WDEVICES
11IIIIIIII
AD1403/AD1403A* I
FEATURES
Improved, Lower Cost, Replacements for Standard 1403, 1403A
3-Terminal Device: Voltage InNoltage Out
Laser Trimmed to High Accuracy: 2.500V ±10mV (AD1403A)
Excellent Temperature Stability: 25ppmfC (AD1403A)
Low Quiescent Current: 1.5mA max
10mA Current Output Capability
AD1403/AD1403A FUNCTIONAL BLOCK DIAGRAM
NC
Low Cost
7
NC
Convenient Mini-DIP Package
PRODUCT DESCRIPTION
The AD1403 and AD1403A are improved three-terminal, low
cost, temperature compensated, bandgap voltage references
that provide a fixed 2.5V output voltage for inputs between
4.5V and 40V. A unique combination of advanced circuit design and laser-wafer-trimmed thin-film resistors provides the
AD1403/AD1403A with an initial tolerance of ±10mV and a
temperature stability of better than 25ppmt C. In addition,
the low quiescent current drain of 1.5mA (max) offers a clear
advantage over classical zener techniques.
The AD1403 or AD1403A is recommended as a stable reference for all 8-, 10- and 12-bit D-to-A converters that require
an external reference. In addition, the wide input range of the
AD1403/AD1403A allows operation with 5 volt logic supplies,
making these devices ideal for digital panel meter applications
and when only a single logic supply is available.
The AD1403 and AD1403A are specified for operation over
the 0 to +70oC temperature range. The AD580 series of 2.5
volt precision IC references is recommended for applications
where operation over the -55°C to +125°C range is required.
GND
3
6
NC
NC
4
5
NC
PRODUCT HIGHLIGHTS
1. The AD1403A offers improved initial tolerance over the
2.
3.
4.
5.
industry-standard 1403A: ±10mV versus ±25mV at a
lower cost.
The three-terminal voltage in/voltage out operation of the
AD1403/AD1403A provides a regulated output voltage
without any external components.
The AD1403/AD1403A provides a stable 2.5V output
voltage for input voltages between 4.5V and 40V making
these devices ideal for systems that contain a single logic
supply.
Thin film resistor technology and tighdy controlled bipolar
processing provide the AD1403A with temperature stabilities of 2 Sppm/o C.
The low 1.5rnA maximum quiescent current drain of the
AD1403 and AD 1403A makes them ideal for CMOS and
other low power applications.
·Covered by Patent Numbers. 3,887,863; RE30,S86.
VOL TAGE REFERENCES 8-63
I.
SPECIFICATIONS
(VIN
= 15V. TA = 25°C unless otherwise noted)
Typ
Max
Unit
2.475
2.490
2.500
2.500
2.525
2.510
V
-
10
10
40
25
-
-
-
7.0
4.4
-
1.2
0.6
4.5
3.0
Otaracteristic
Symbol Min
Output Voltage
(10 = OmA)
AD1403
AD1403A
Vo
ppm/oC
Temperature Coefficient of Output Voltage
AD1403
AD1403A
l::NO/6.T
Output Voltage Change, 0 to +70°C
AD1403
AD1403A
6.Vo
Line Regulation
(15V.;;;vINQOV)
(4.5.;;;vIN";;15V)
Regin
Load Regulation
(OmA-~~-oVOUT
COM,-----<'--------4
Figure 1. Simplified AD 1403 Schematic
8-64 VOLTAGE REFERENCES
±25mV
±10mV
Typical Performance Curves-AD1403/AD1403A
--
70°C-,..
1.5
>
E
1.0
I
~
:>
~
./'
0.5
w
'"
Z
"
:>
V
V
~~
./
!!:
:I:
0
~
'/
./
V
./
-0,5
~
~
-1.0
~25°C
O°C_
~ y'"
v
15
20
r--...
l'
..........
1. VIN =5V
2. VIN::: 15V
loUT' ~mA
10
10
2
25
30
35
40
20
30
40
TA. TEMPERATURE -
50
60
80
70
°c
VIN. INPUT VOLTAGE - Volts
Figure 5. Change in VOUT vs. Temperature
(Normalized to VOUT@ V/N = 15V)
Figure 2. Typical Change in VOUT vs. V/N
(Normalized to VOUT@V/N=15V@TC=25"C)
0.5
>
E
I
w
"...'..."
0
>
...
~
::>
0
---r---... --
.........
-0.5
-1.0
I
......
r--
O°C
j"'-...
'"
"
-1.5
............
:I:
0
~
:>
Or".q
~
·~ii
~"'~~4'"
....""~.q...
!!:
25°C
w
z
,--
-1
?
~::
..........
!!:
$~~
I
~
:>
.....
--t:-.
r-.. ...
__'p..-
>E
w
'"
-2
z
.... ~
"
:I:
0
~
11
-3
:>
~oC
?
...z
0
--
----
f.-- I-'
20
30
40
TAl TEMPERATURE _
loUT. OUTPUT CURRENT - rnA
........- f.--
50
60
70
°c
Figure 6. Change in VOUT vs. Temperature
(Normalized to VOUT@ V/N = 15V, 'OUT=OmA)
f.-- -
1.00
w
~
:;
0.96
0
0.90
10
20
30
40
TA. TEMPERATURE _
50
60
70
90
°c
Figure 4. Ouiescent Current vs. Temperature
(V,N = 15V, 10UT= OmA)
VOL TAGE REFERENCES 8-65
Applying the AD1403/AD1403A
VOLTAGE VARIATION VS. TEMPERATURE AND LINE
Some confusion exists in the area of defining and specifying
reference voltage error over temperature. Historically, references are characterized using a maximum deviation per degree
Centigrade; i.e., 10ppmtC. However, because of the inconsistent nonlinearities in zener references (butterfly or .. s .. type
characteristics), most manufacturers use a maximum limit
error band approach to characterize their references. This technique measures the output voltage at 3 to 5 different temperatures and guarantees that the output voltage deviation will fall
within the guaranteed error band at these discrete temperatures. This approach, of course, makes no mention or guarantee
of performance at any other temperature within the operating
temperature range of the device.
The consistent Voltage vs. Temperature performance of a typical AD1403 is shown in Figure 6. Note that the characteristic
is quasi-parabolic, not the possible "s" type characteristics of
classical zener references. This parabolic characteristic permits
a maximum output deviation specification over the device's
full operating temperature range, rather than just at 3 to 5
discrete temperatures.
The AD1403 exhibits a worst-case shift of 7.5mV over the entire range of operating input voltage, 4.5 volts to 40 volts.
Typically, the shift is less than ImV as shown in Figure 3.
THE AD1403A AS A LOW POWER, LOW VOLTAGE
PRECISION REFERENCE FOR DATA CONVERTERS
The AD1403A has a number of features that make it ideally
suited for use with AID and DIA data converters used in complex microprocessor-based systems. The calibrated 2.500 v~lt
output minimizes user trim requirements and allows operatIOn
from a single low voltage supply. Low power consumption
(1.5mA quiescent current) is commensurate with that of
CMOS-type devices, while the low cost and small package
complements the decreasing cost and size of the latest
converters.
DECODED
SYSTEM
MEMW
DEVICE
ADDRESS
+5V
12
lIL=OTo10mA
,
'" 2.5OV
""
c.-
RSET
Wo
13
4
DBS
DB4
B81TS
AD7524
DAC
DB3
DB2
ANALOG
i
I
11
1500
~
I.
+5V
Figure 8a. The AD 1403 as a Precision Programmable
Current Source
OUTPUT
OBI
DBO
THE AD1403 AS A PRECISION PROGRAMMABLE
CURRENT SOURCE
The AD1403 is an excellent building block for precision
current sources. Its wide range of operating voltages, 4. SV to
40V, along with excellent line tegulation over that range
(7 .5mV) result in high insensitivity to varying load impedances.
The low quiescent current (II) of 1.5mA (max) and the maximum specified maximum load current of lOrnA allows the
user to program current to any value between l.SmA and
lOrnA.
Figure lOa shows the AD1403 connected as a current source.
Total current is equal to the quiescent current plus the load
current. Most of the temperature coefficient comes from th~
quiescent current term I.. which has a typical TC of 0.13%1 C
(130OppmtC). The load voltage (and hence current) TC is
much lower at ±40ppmt C max (AD 1403). Therefore, the over-·
all temperature coefficient decreases rapidly as the load current is increased. Figure lOb shows the typical temperature
coefficient for currents between 1.5mA and lOrnA. Use of an
AD1403A will not improve the TC appreciably.
..11
DATA
BUS
DB7
DBG
Figure 9 shows the ADl403A used as a reference for the
AD752410w-cost 8-bit CMOS DAC with complete microprocessor interface. The AD1403A and the AD7524 are
specified to operate from a single 5 volt supply; this eliminates the need to provide a +15 volt power supply for the sole
purpose of operating a reference. The AD7524 includes an
8-bit data register, and address decoding logic; it may thus be
interfaced direcdy to an 8- or 16-bit data bus. Only 3001lA of
quiescent current from the single +5 volt supply is required
to operate the AD7524 which is packaged in a small 16 pin
DIP. The AD542 output amplifier is also low power, requiring
only 1.5mA quiescent current. Its laser-trimmed offset voltage
preserves the ±1/2LSB linearity of the AD7524KN without
user trims and it typically settles to ±1I2LSB in less than 5
microseconds. It will provide the 0 volt to -2.5 volt output
swing from ±5 volt supplies.
j
'.11
GAIN
ADJUST
ADI403
2
VOUT
600
Figure 7; Low Power, Low Voltage Reference for the AD7524
Microprocessor-Compatible 8-Bit DAC
8-66 VOLTAGE REFERENCES
10
'SOURCE - .:'IA
Figure 8b. Typical Temperature Coefficient of Current
Source
11IIIIIIII ANALOG
WDEVICES
FEATURES
Very High Accuracy: 10.000 Volts ±2.5mV (L and UI
Low Temperature Coefficient: 3ppmfC
Performance Guaranteed _55°C to +125°C
10mA Output Current Capability
Low Noise
Short Circuit Protected
Available as /8838
± 10 Volt Precision
Reference Series
AD2700/AD2701 /AD2702 I
AD2700 SERmS FUNCTIONAL BLOCK DIAGRAMS
FINE
+15.0V
ADJUST
COMMON
FINE
AOJUST
FINE
FINE
ADJUST
+15.0V
ADJUST
12
PRODUCT DESCRIPTION
The AD2700 family of precision 10 volt references offer the
user excellent accuracy and stability at a moderate price by
combining the recognized advantages of thin film technology
and active laser trimming. The low temperature drift
(3ppm/oC) achieved with these technologies can be matched
only by the use of ovens, chip heaters for temperature regulation, or with hand selected components and manual trimming. In addition, temperature-regulated devices are guaranteed only up to +85° C operation, whereas the U- and S-grade
devices in the AD2700 family are guaranteed to +l2SoC.
The AD2700 is a +10 volt reference which is designed to
interface with high accuracy bipolar D/A converters of 10
and 12 bit resolution. The lOrnA output drive capability
also makes the AD2700 ideal for use as a general positive
system reference.
The AD2701 is a negative 10 volt reference especially designed to interface with CMOS D/A and AID converters, as
shown in the applications. F or systems requiring a dual tracking
reference, the AD2702 offers both positive and negative precision 10 volt outputs in a single package. Both are often used
with S2XX Series 12-bit AID converters which require
-10V external references for high accuracy over wide
temperature ranges.
All three devices are offered in "J" and "L" grades for operation from _25°C to +8S o C and "s" and "u" grades for the
-55°C to +12S o C temperature range. Screening to MIL-STD883 is available for "S" and "u" grades of the AD2700
family.
3
.------+---{"13
~J~~~
-10.DOODV
OUTPUT
FINE
COMMON
-15.0V
ADJUST
FINE
ADJUST
PRODUCT IDGHLIGHTS
1. Active laser trimming of both initial accuracy and temperature performance results in very high accuracy over the
temperature range without external components. The
AD2700/01l02 LD grades have a maximum output
voltage error at 25°C of ±2.SmV with no external
adjustments.
2. The performance of the AD2700 series is achieved by a
well-characterized design and precise control over the
manufacturing process.
3. The AD2700 series is well suited for a broad range of
applications requiring an accurate, stable reference source
such as high resolution data converters (12 or 14 bits),
test and measurement systems and calibration standards.
Model
Output
AD2700
AD2701
AD2702
+10.000V
-10.000V
±10.000V
VOL TAGE REFERENCES 8-67
I
SPECIFICATIONS
(max or min @
EIN
±
15V @
+ 25"1:, Rt. = 2110 unless otherwise noted)
MODEL
JD
ABSOLUTE MAX RATINGS
Input Voltage (for applicable supply)
Power Dissipation @ +2SoC - AD2700, 01
- AD2702
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, lOs)
Short Circuit Protection (to GND)
±20V
300mW
4S0mW
-2SoC to +8SoC
-6SoC to +lSO°C
+300°C
Continuous
OUTPUT VOLTAGE ERROR @ +2SoC
AD2700
lO.OOOV
AD2701
-lO.OOOV
AD2702
±lO.OOOV
±O.OOSV
±O.OOSV
±O.OOSV
±0.002SV
±0.002SV
±0.002SV
OUTPUT CURRENT! - @ +2SoC
(VIN = ±13 to ±18V) over op. temp. range
±lOmA
±SmA
+SmA, -2mA
OUTPUT VOLTAGE ERROR - AD2700,01
10ppmtC
±11.0mV
(Tmin to Tmax)2
AD2702
lOppmtC
±l1.OmV
LINE REGULATION
VIN = ±13.5 to ±16.SV
LOAD REGULATION
Oto ±lOmA
SOp.V/mA
OUTPUT RESISTANCE
o.osn
LD
INPUT VOLTAGE, OPERATING
±13V to ±18V
±14mA
+17mA,-4mA
NOISE
(0.1 to 10Hz)
SO/lV p-p typ
LONG TERM STABILITY (@ +SSoC)
100ppm/lOOO Hrs. (typ)
OFFSET ADJUST RANGE
(See Diagrams)
±20mV (min)
OFFSET ADJUST TEMP DRIFT EFFECT
±4/lV/oC per mV
of Adjust (typ)
PACKAGE OPTION 3,4
•••
3ppmtC
±4.3mV
5ppm/oC
±S.SmV
....
..
••
••
••
••
±8mV
±lO.OmV
±S.SmV
3ppmioC
±S.SmV
DH-14C
DH-l4C
..
DH-14C
•
DH-14C
NOTES
·Same as HJO" grade performance.
··Sarne as "LD" grade perfonnance.
···Same as "SD" grade performance.
Specified with resistive load to common. Device not intended for
use in· driving a dynamic load.
2 Output VOltage error as a function of temperature is determined using the box method.
Each unit is tested at T min, T max and +2SoC. At each temperature VOUT must raU
within the rectangular afea bounded by the minimum and maximum temperature and
whose maximum VOUT value is equal to VOUT nominal plus or minus the maximum
+2 SoC error plus the maximum drift error from +2SoC. The box limits are noted
below the drift values used to calculate the box.
• Analog Devices reserves the right to ship metal packages (outline DH-14B) in lieu of
the standard ceramic packages for J and L grade parIS.
4See Section 14 for package outline information.
Specifications subject to change without notice.
8-68 VOL TAGE REFERENCES
UD
300p.VN
QUIESCENT CURRENT - AD2700, 01
- AD2702
1
SD
AD2700/AD2701/AD2702
-15V
N/C
N/C
N/C
FINE Your FINE
ADJUST +10 ADJUST +15
N/C
NIC COMMON
TEST
POINT
Nle
-15V-_"....-,
N/C
+15V
AD2102: .HO.OOO VOLT REFERENCE
*eXTERNAL 10k POTENTIOMETER
PROVIDES t30mV OUTPUT OFFSET ADJUST. TEMPERATURE
EFFECT IS ±4jJ.vr PER mV OF
FINE
-10
FINE
-15
N/C
Nle COMMON
OFFSET CORRECTION (EXTER-
NAL ADJUSTMENT OPTIONAL).
ADJUST VOUT ADJUST
Pin Designations
Fine Trim Connections
--_'~--------------------~----------e-----------+15V
-15V
---i---+----------~--;_--4_----------+_--t__.~--+5V
Using AD2702 Reference with the Fast, High Accuracy
AD5215 - 12-Bit ADC
VOL TAGE REFERENCES 8-69
I
USING AD2700 REFERENCE WITH THE AD7520
AND AN IC AMPLIFIER TO BUILD A DAC
The AD2700 series is ideal for use with the AD7520 series of
CMOS DIA converters. A CMOS converter in a unipolar application as shown below performs an inversion of the voltage
reference input. Thus, use of the +10 volt AD2700 reference
will result in a 0 to -10 volt output range. Alternatively, using
the -10 volt AD2701 will result in a 0 to +10 volt range. Two
operational amplifiers are used to give a bipolar output range
of -10 volt to + 10 volt, as shown in the lower figure. Either
the AD2700 or AD2701 can be used, depending on the transfer code characteristic desired. For more detailed applications
information, refer to the AD7S20 Data Sheet.
+15V lOR -15 FOR AD2701 I
"
AO.700
USING THE AD2700 VOLTAGE REFERENCE WITH
D/A CONVERTER
An AD2700 Voltage Reference can be used with an inverting
operational amplifier and an R-2R ladder network. If all bits
but the MSB are off (i.e., grounded), the output voltage is
(-RI2R)EREF . If all bits but Bit 2 are off, it can be shown
that the output voltage is 'n(-R/2R)EREF = 'AEREF: The
lumped resistance of all the less-significant-bit circuitry (to
the left of Bit 2) is 2R; the Thevenin equivalent looking
back from the MSB towards Bit 2 is the generator, EREFI2,
and the series resistance 2R; since the grounded MSB series
resistance, 2R, has virtually no influence - because the
amplifier summing point is at virtual ground - the output
voltage is therefore -EREF/4. The same line of thinking can
be employed to show that the nth bit produces an increment
of output equal to 2-n EREF .
~~Ol'3 nov)
DIGITAL INPUT CODE
BIT 1 (MSB)
r--I 5 AD7520 1
DIGITOA-L""11
GND
iNP"uT
;
BIT3
BIT2
I
I
lOUT 1
10UT 2
C>8--IT--'~~--(L~S8~1 13
'--"';"'=-'
OUTPUT
Unipolar Binary Operation
DIGITAL INPUT
ANALOG OUTPUT
a. Basic Circuit
1111111111
BIT 2 SWITCH CLOSED
1000000001
.---..,/:
i'ov-l
1000000000
I
0111111111
I
I
:
L_EREF_J
2R
.R
0000000001
o
0000000000
NOTE, 1 LSB
AD2700
= 2·"
\
I
I
2R
R
LUMPED RESISTANCE
OF LESS-SIGNlfICANT BITS
VREF
Table I. Code Table - Unipolar Binary Operation
b. Example: Contribution of Bit 2; All Other Bits "0"
+15V
t--+--__.......
VREF-.......
R3
15
BIT 1 (MSBI
10 MEGOHM
14
16f---I----~==~__,
IoUTl
DIGITAL
INPUT
AD1520
10k
BIT 10 ILSB)
R2
10k
13
c. Simplified Equivalent of Circuit (b.)
Bipolar Operation (4·Quadrant Multiplication)
DIGITAL INPUT
ANALOG OUTPUT
1111111111
-VREF (1 - 2"9)
1000000001
-VREF (2.9 )
1000000000
0
0111111111
VR"" (2-9 )
0000000001
V REF (1 - 2-9 )
0000000000
V REF
NOTE, 1 LSB
= 2-'
VREF
Table II. Code Table - Bipolar (Offsllt Binary) Operation
8-70 VOLTAGE REFERENCES
~ANALOG
WDEVICES
FEATURES
Laser Trimmed to High Accuracy: 10.000V ± 1.0mV
Low Temperature Coefficient: 1ppmfC (L Grade)
Excellent Long Term Stability: 25ppm!1000hrs.
5mA Output Current Capability
Low Noise: 3Oj.lV p.p
Short Circuit Protected
No Heater Utilized
Small Size (Standard 14.pin DIP Package)
± 10.000 Volt Ultrahigh
Precision Reference Series
AD2710/AD2712
AD2710/AD2712 FUNCTIONAL BLOCK DIAGRAMS
COMMON
FINE
ADJUST
PRODUCT DESCRIPTION
The AD2710 and AD2712 are temperature-compensated,
hybrid voltage references which provide precise 1O.000Voutput from an unregulated input level from 13.5 to 16.5 volts.
Active laser trimming is used to trim both the initial error at
+2S oC as well as the temperature coefficient, which results in
ultra high precision performance previously available only in
oven-regulated modules. The 1.0mV maximum initial error
and 1ppmtC guaranteed maximum temperature coefficient
of the AD2710L and AD2712L represent the best performance combination available without using ovens or heated
substrates for temperature regulation.
The AD2710 series of precision 10.000 volt references offer
the user unequalled accuracy and stability with performance
guaranteed over the 0 to +70 oC temperature range. The devices
combine the recognized advantages of thin film technology
and active laser trimming with a unique integrated ceramic
package design to provide an excellent reference for use in
applications requiring high accuracy and stability.
The AD2710 is recommended for use as a reference for 10-,
12- and 14-bit D/A converters which require an external reference. The device is also suitable for many types of high resolution AID converters, either successive approximation or integrating designs. The SmA output drive capability of the device
also makes the AD2710 ideal for use as a master system
reference.
For systems requiring a dual tracking reference, the AD2712
offers both positive and negative outputs in a single package.
All units are packaged in an integrated ceramic 14-pin sidebrazed package offering superior reliability over other package
designs.
I
COMMON
-15.0V
-FINE
ADJUST
PRODUCT HIGHLIGHTS
1. Active laser trimming of both initial accuracy and tempera-
ture coefficient results in very high accuracy over the temperature range without the use of external components.
AD2710 has a maximum deviation from 10.000 volts of
±1.00mV at 2SoC with no external adjustments.
2. The AD2710 and AD2712 are well suited for a broad range
of applications requiring an accurate, stable reference source
such as data converters, test and measurement systems and
calibration standards.
3. The performance of the AD2710 series is achieved by a
well-characterized design and close control over the manufacturing process. This eliminates the need for temperaturecontrolled ovens to provide stability.
4. The advanced multilayer integrated ceramic package results
in superior electrical performance as well as inherent high
reliability.
VOL rAGE REFERENCES 8-71
SPECIFICATIONS
(typical @ Vs ± 15V after a 5 minute warm-up at
Model
ABSOLUTE MAXIMUM RATINGS
Input Voltage (for applicable supply)
Power Dissipation @ +2SoC
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 20s)
Short Circuit Protection (to GND)
OUTPUT VOLTAGE ERROR!
+2S oC
±18V
300mW
o to +70 oC
-Ssoc to +IOOoC
+260°C
Continuous
OUTPUT VOLTAGE TEMPERATURE
COEFFICIENT 2
+10V Output
+2S 0 C to +70oC
o to + 2S oc
-lOY Output4
+2SoC to +70oC
o to +2SoC
LINE REGULATION
Vs = ±13.S to ±16.S s
±2ppm/oC max
±SppmfCmax
Not Applicable
Not Applicable
OUTPUT CURRENT
10mA
AD2710KN
+ 25"C,
no load condition unless otherwise specified)
AD2710LN
AD2712KN
AD271ZLN
4S0mW
••
*
±1.0mVmax
±lppmfCmax
±2ppm/o C max
•
±lppmfC max
.3
Not Applicable
Not Applicable
±3ppmfC max
±SppmfCmax
±2ppmfCmax
Not Applicable
12mA (16mA max) ••
2mA (4mA max)
••
SO/LV/mA(IOO/LV/mA max)
OUTPUT RESISTANCE
O.OSO
INPUT VOLTAGEs
Operating Range
Specified Performance
±13V to ±18V
±13.SV to ±16.SV
QUIESCENT SUPPLY CURRENT
VS+
Vs_s
9mA(14mAmax)
Not Applicable
NOISE
0.1 to 10Hz
30/LV
pop
LONG-TERM STABILITY
TA = +2SoC
2Sppm/l000 Hours
EXTERNAL TRIM RANGE 6
±10mV
PACKAGE OPTION?
DH-14A
*
*
*
NOTES
'Same asAD2710KN. ··Same asAD2712KN performance.
Specifications apply to both outputs of the AD2712.
to next page for definition of temperature~related error specifications.
'The AD2710LN and AD2712LN outputs are guaranteed for a maximum ±2ppmfC temperature
coefficient over the + lSoC to +25°C temperature range. Refer to Figure 1.
4The +10V and -10V outputs of the AD2712 typically track within ± lppmf C over the specified temperature range.
S Negative power supply not required for AD2710.
• Use of the output trim will change the temperature coefficient approximately O.3ppmf C for each
millivolt of adjustment.
7 See Section 14 for package outline information.
Specifications subject to change without notice.
I
8-72 VOLTAGE REFERENCES
••
12S/LVIV(200/LVIV max)
LOAD REGULATION
10 =0 to ±SmA
:I Refer
.3
*
Applying the A02710/A02712
UNDERSTANDING THE SPECIFICATIONS
The AD2710 and AD2712 precision references are designed
for applications requiring both the lowest possible initial error
at room temperature and the lowest possible temperature drift.
The specification for initial error is relatively straight-forward,
and is the absolute error from exactly 10.000V. The specification for temperature drift, however, must be explained.
the full scale output range. It is this reference which will ultimately determine the absolute accuracy of the converter.
While many conveners include internal reference sources,
better overall performance can be obtained if a higher precision external reference is used.
+15V
Various methods have been used to specify the temperature
drift of voltage references, including the "butterfly", "box",
and "modified-box" (or total error) methods. The AD2710
and AD2712 are specified with the "butterfly" method.
Using three or more temperatures provides the user with a
tigh ter drift specification, eliminating possible mid-range excursions. The AD2710 and AD2712 have been designed and
characterized as having a smooth drift curve with a virtually
straight segment from +2SoC to +700 C. The typical curve as
shown is concave downward and gradually increases slope
near O°C.
As can be seen from Figure 1, the AD2710L and AD2712L
+10V outputs will exhibit a maximum temperature coefficient
of ±lppmfC (±2ppmfC for "K" grade) from +2S oC to
+70°C. Over the short range between +1SoC and +2SoC, the
AD2710L and AD2712L +10V outputs have a maximum
drift of only ±2ppmf C and a maximum drift of ±SppmfC
from 0 to +1SoC. The negative output ofthe AD2712L has a
similar temperature coefficient characteristic with a maximum
slope of ±2ppmfC from +2So C to +70° C. This limit continues
from +2SoC to +1SoC and then increases to a ±SppmfC
maximum slope from +15°C and O°C. Every unit is 100 percent tested and guaranteed to meet these specifications over
the full 0 to +70°C temperature range.
r------,.----,---------------,+2mV
TYPICAL CURVE
~~~ ••'mv
~
+O.46mV
-O.45mV
·O.9rnV
!:------:''::-O--:''::-5--:20=--:2=-6-30~--40-!::----:':50:---:':
..:---~70-2mv
Figure 3. Low Drift 12-Bit D/A Converter
Figure 3 shows the AD2710 used with the ADs66A high-speed
12-bit DAC. The ADS 66AKD is laser trimmed for ±1I4LSB
maximum nonlinearity, and exhibits a gain temperature coefficient of 3ppmfC. Use of the AD2710LN reference will
result in a worst case total gain temperature coefficient of
4ppmf C. After initial calibration of the DAC scale factor at
room temperature, 12-bit absolute accuracy can be maintained
over the +1SoC to +70°C temperature range. The high output
current capability of the AD2710 allows it to serve as a reference for up to 10 such converters in a system.
The resolution of the ADS66A can be extended as shown in
Figure 3 by summing the output of another DAC. In this example, an ADss9 is used to provide 4 additional bits. Since
the ADSS9 is driven from the same AD2710 reference as the
ADS66A which provides the higher-order bits, and uses a
similar internal thin-film resistor ladder, it will exhibit firstorder temperature tracking. While this circuit provides 16-bits
of resolution, it is only as accurate as the ADS66A used for
the most significant bits. Use of an ADS66AKD will typically
achieve ±0.003% accuracy (±1I2LSB at 14 bits).
TEMPERATURE _·C
Figure 1. Maximum Change from +10V Output from +25"C
Value v&. Temperature
All grades of the AD2710 and AD 2712 are tested after a five
minute warm-up period. This warm-up allows the entire circuit
to atrain thermal equilibrium. The warm-up drift is approximately SOO microvolts and is completely settled approximately three minutes after turn-on. Figure 2 shows the
typical warm-up characteristics of the AD2710.
w
10.0(110
~
10.0005
>
10.0000
>::>
9.9996
~
0
I!:::>
0
SPECIFIEO
INITIAL
} ACCURACV
....-
9.9990
1MIN
2MIN
3MIN
4MIN
TURN-ON
Figure 2. AD2710 Typical Warm-Up Drift
USING THE AD2710 AS A DAC REFERENCE
Digital-to-analog converters require a reference to establish
Fit/ure 4. 16-Bit Binary DAC with AD2710 Reference
VOL TAGE REFERENCES 8-73
II
ruGH RESOLUTION ANALOG-TO-D1GITAL CONVERSION
The AD2710 is well-suited to both system and instrument-level
analog-to-digital converter reference requirements. The excellent absolute accuracy and low temperature drift allow lowcost measurement systems to offer high levels of performance.
The AD7555 is a 4'>S15'>S digit ADC subsystem which uses the
quad-slope conversion technique to achieve high accuracy at
low cost. This patented conversion process performs automatic correction for offsets and other errors in the analog
circuitry as a parr of each conversion. Total scale factor drift
1.2ppmtC is possible using the AD2710L reference and medium-precision external amplifiers. This represents a full scale
drift of less than ±10 counts in ±200,OOO from +15°C to
+45°C. Less than 1 count of drift will occur in the 4112
digit mode.
The AD7555 was designed for use with a 4.096V reference,
which produces a ±2 volt input range. When the AD2710 is
used, the input range is increased to ±4.88281 V (24.4IlV I
count). The new scaling can be handled either by using a precision gain stage before the AD7555 analog input as shown or by
using a microprocessor to digitally correct the scale. The actual
input signal value can be computed by multiplying the count
produced by the AD7555 by VREFl (10 volts in this case), and
dividing the result by 409600. Details of the digital circuitry
of the AD7555 can be found on the AD7555 data sheet.
It should be noted that when the AD755S is used with the
AD2710 10 volt reference, it is necessary to use a Vee greater
than 10 volts. Thus the digital inputs and outputS of the ADC
will be compatible with CMOS logic levels.
Vss~-5V
NOTES:
1. RS Cl VALUES SHOWN ARE FOR 5 1/2 DIGIT MODE. FOR 41/2 DIGIT MODE As ~ 36Ok. C, '" O.22I/F.
SUITABLE CAPACITORS AVAILABLE fROM COMPONENT RESEARCH CO. INC., 1655 261h STREET.
SANTA MONICA, CA. 90404. (STOCK NUMBER FOR O.22JJF CAPACITOR IS Dl1B224KXWI.
2. R4, R6. R7 1% TOl.ERANCE
3. Rl, R3 SHOULD TRACK WITHIN O.5ppmtC. EITHER BULK METAL OR WIRE·WOUND RESISTORS
(OR A THIN·fILM NElWDRK) SHOULD BE USED. R2 SHOULD BE A LOW·TC TYPE POTENTIOMETER
OR A SELECTED LOW DRIFT FixeD RESISTOR.
AD2710: +10.000 VOLT REFERENCE
Figure 5. High Accuracy Low Drift AID Converter
~~~T Vf,'ll A~~~iT
13
AD2712: ±10.000 VOLT REFERENCE
Figure 7. Pin Connections (Top View)
-15V _ _ _
~
_ _--,.
+15V
Figure 6. Optional Fine Trim Connections
8-74 VOLTAGE REFERENCES
~ANALOG
WDEVICES
FEATURES
Replacement for Industry Standard REF01/REF02
Laser Trimmed to High Accuracy:
10.000V ±30mV (REF01)
5.000V ± 15mV (REF02)
(A and E Grades)
Trimmed Temperature Coefficient: 8.5ppmrc max
(A and E Grades)
Low Noise: 4p.V p-p Typical
Output Trim Capability
Temperature Output Pin (REF02)
Machine Insertable Hermetic Cerdip Package
10V + 5V References
ADREF01/ADREF02 I
ADREFOI FUNCTIONAL BLOCK DIAGRAM
~------~4r-----------~
GROUND
NOTE: MAKE NO CONNECTIONS TO
PINS 1. 3. 7 AND B.
ADREF02 FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The ADREFOI and ADREF02 are a lOY and SV reference,
respectively, that utilize a buried Zener diode for minimal noise
and drift over temperature. The Zener diode provides a precise
10.OV (S.OV for REF02) output from an unregulated input
voltage of 13.SV (1O.8V for REF02) to 36V. Laser Wafer Trimming
(LWT) is used to trim both the initial error at + 25°C as well as
the temperature coefficient.
The + lOY output can be adjusted over a + 3%, - 1% range
with minimal effect on device characteristics. The + SV output
can also be adjusted over a + 6%, - 2% range with minimal
effect on device characteristics. The ADREFOI and ADREF02
offer good drift characteristics, low power consumption, and
good accumcy for applications requiring a low-cost reference.
These devices are recommended as references for 8-, 10- and
12-bit D/A converters that require an external reference. They
are also ideal for all types of AID converters with up to 12-bit
accuracy.
The ADREFOIE/ADREF02E and ADREFOIHlADREF02H are
specified for opemtion from 0 to + 70°C, and the ADREFOIl
ADREF02 and ADREFOIA/ADREF02A are specified for operation between - ssoe and + 12Soe. All grades are packaged in a
hermetic 8-pin cerdip package.
PRODUCT HIGHLIGHTS
1. The ADREFOI is a second source equivalent to the industry
standard REFOL
2. The ADREFOI provides a stable 10.000Voutput for input
voltages between 13.SV and 36V.
3. Laser Wafer Trimming reduces ADREFOI initial offset error
to 30mV (A and E grades).
TEMP
ADREF02
I
Rs
RZ2
GROUND
NOTE: PINS 1. 7 & B ARE INTERNAL TEST POINTS.
MAKE NO CONNECTIONS TO THESE POINTS.
5. The ADREF02 provides a stable S.OOOV output for input
voltages between 10.8V and 36V.
6. Laser Wafer Trimming reduces ADREF02 initial offset error
to ISmV (A and E grades).
7. Temperature out pin enables the ADREF02
as a temperature transducer.
to
be configured
8. The buried Zener diode reference on both devices reduces
noise to 4 ....V p-p and improves temperature stability to
8.Sppm/oe max (A and E grades).
9. Cerdip packaging provides hermeticity and machine insertability at a low price for the devices.
4. The ADREF02 is a second source equivalent to the industry
standard REF02.
VOL TAGE REFERENCES 8-75
SPEC IFI CATIONS ITA = +25"1:, V = + 15V unless otherwise specified)
IN
ADREF01H
Typ Max
Model
Min
Output Voltage
9.950
Output Voltage Drift
Oto +70"C
- 55°C to + 125°C
Gain Adjustment
ADREF01E
Min Typ Max
25
ADREF01
Typ Max
10.030 9.950
10.050 9.970
10
Min
3
10.050 9.970
-1
+3
Line Regulation (Tmin to T ."..)
13.5Vs +VIN s36V
Load Regulation
Sourcing 0 < lOUT < 10mA
TmintoTmax
Sinking -10 < lOUT < OmA
T min to Tmax
Units
10.030 V
±ppmf'C
8.5
10
-1
+3
ADREF01A
Min Typ Max
25
3
8.5
-I
+3
-I
+3
%
100
100
100
100
± fLVN
100
100
100
100
±fLV/mA
100
100
100
4
2
4
2
100
2
4
rnA
4
Quiescent Current
2
Power Dissipation
30
30
30
30
mW
Output Noise
O.IHzto 10Hz
Spectral Density, 100Hz
4
100
4
100
4
100
4
100
fLVp-P
nV/vHz
IS
30
50
30
50
30
50
30
50
rnA
Short-CircuitCurrent-to-VIN
30
50
30
50
30
50
30
50
mA
Turn-On Settling Time
toO.Ol%FS
60
Temperature Range
Specified Performance
0
IS
IS
ppmll000Hr
Long-Term Stability
Short-Circuit Current-to-Ground
60
60
+70
0
15
+70
60
+ 125 -55
-55
fLS
+ 125 °C
NOTE
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS· (ADREF01 and
ADREF02)
VIN to Ground
. . . . . . . 36V
Power Dissipation (25°C)
. . . . . 500mW
Storage Temperature ..
- 65°C to + 150°C
Lead Temp (Soldering, 10sec)
Package Thermal Resistance
0Je . . . . . . . . . . . . .
22°CIW
OJA • . • • • • • . • • • • .
1l0°CIW
Output Protection: Output safe for indefinite short to ground
and momentary short to VIN•
+V'N
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
NC
NC
NC
NC
ADREF01
TOP VIEW
(Not to Scale)
GND
TRIM
NC = NO CONNECT
+V'N
TEMP
NC
ADREF02
TOP VIEW
(Not to Scal.)
GND
NC
VOUT
TRIM
NC = NO CONNECT
8-76 VOLTAGE REFERENCES
NC
VOUT
SPECIFICATIONS
(TA
ADREFOl/ADREF02
=+ 25"C, VIII =+ 15V unless otherwise specified)
ADREF02H
Typ Max
Model
Min
Output Voltage
4.975
Output Voltage Drift
Oto + 70°C
- 55°C to + 125°C
ADREF02E
Min Typ Max
5.025 4.985
10
25
Min
ADREF02
Typ Max
5.015 4.975
3
5.025 4.985
-2
+6
-2
+6
Line Regulation (Tmin to T max)
10.8V < + VIN <36V
11.4V < + VIN <36V
100
Load Regulation
Sourcing 0 < lOUT < 10mA
+25°C
T min to Tmax
Sinking - 10 < lOUT
Reference Out, +IOV
Analog Common (AC)
Reference In
Analog Power-Supply, -15V (VEE)
Bipolar Offset
10 Yolt Span Input
20 Volt Span Input
Digital Common (DC)
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11
Status Out
Theory of Operation - AD363/AD364
The normal sequence of events is as follows:
1. The appropriate Channel Select Address is latched into the
address register. Time is allowed for the multiplexers to
settle.
2. A Convert Start command is issued to the ADC which, in
response, indicates that it is "busy" by placing a Logic "1"
on its Status line.
3. The ADC Status controls the sample-and-hold. When the
ADC is "busy", the sample-and-hold is in the Hold mode.
4. The ADC goes into its conversion routine. Since the sampleand-hold is holding the proper analog value, the address
may be updated during conversion. Thus multiplexer settling time can coincide with conversion and need not affect
throughput rate.
CHANNEL
SELECT
I
LATCH
"LOW" ANALOG INPUTS
AIS Functional Block Diagram
S. The ADC indicates completion of its conversion by returning Status to Logic "0". The sample-and-hold returns to
the Sample mode.
6. If the input signal has changed full-scale (different channels
may have widely-varying data) the sample-and-hold will
typically require 10 microseconds to "acquire" the next
input to sufficient accuracy for 12-bit conversion.
Concept
Figure 1 shows a general DAS application.
After allowing a suitable interval for the sample-and-hold to
stabilize at its new value, another Convert Start command may
be issued to the ADC.
-[
::~('
DKiITAL
DP.YA
~
.~.
"
Figure 1. AD363
By dividing the data acquisition task into two sections, several
important advantages are realized. Performance of each design
is optimized for its specific function. Production yields are
increased thus decreasing costs. Furthermore, the standard
configuration packages plug into standard sockets and are
easier to handle than larger packages with higher pin counts.
System Til!!i.!lg
Figure 2 is a timing diagram for the circuit shown in Figure 1
and operating at maximum conversion rate.
ADDRESS MAY BE CHANGED
ADDRESS
~ D - - - - - - - - - - - - - - - '
CAPACITOR ) -_ _ _ _ _ _ _ _ _- - ,
roAr--~~---,
DATA
"-_.:..;.;c:-_ _--,
R£FIN>-------......
REF OUT
f----------i
PULSE
OUT
CLoc;:>-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
PRODUCT DESCRIPTION
The AD367 is a wide dynamic range integrated circuit which
contains all the analog functions needed to construct a high
resolution, high accuracy integrating Data Acquisition System.
It utilizes hybrid technology to incorporate a programmable gain
amplifier, integration amplifier, - lOY reference, comparator,
and control logic in a 24-pin hermetic dual-in-line package.
The programmable gain amplifier provides 6-bits (I of 64) gain
control which are digitally selectable with CMOS voltage levels.
The dual slope converter uses time to quantitize the analog
input signal. The differential front-end allows true differential
inputs with high common mode rejection, or single-ended inputs
with ground sense capability. This conversion technique has
inherent high frequency noise immunity and excellent normal
mode noise rejection at frequencies that are integal multiples of
Iff 1 (T 1 = the signal integration period). The conversion accuracy
is independent of both the integration capacitance and clock
frequency, since they affect both the signal integration phase
and reference integration phase in the same ratio. A microprocessor
and software routine or any digitizing timer that accepts TTL
inputs can be used to count clock pulses to digitiz.e the AD367
output. The integration capacitor is external, therefore conversion
time may be adjusted by the user. The nominal value is O.012,...F
for an integration time of 4ms and total conversion time of
lOms. By choice of integration capacitor and clock frequency
the integration time is programmed from a minimum of 2ms to
a maximum of 20ms. The maximum conversion rate is 200
samples per second.
PRODUCT HIGHLIGHTS
I. The AD367KM provides true IS-bit (± 0.00305% FSR
maximum linearity error) performance with 30Sf1V
resolution.
2. The differential input programmable gain amplifier front end
has 6-bit (I of 64) gain control. This provides gains of
0.282VN to 24VN, or input full-scale ranges of0.417V to
1O.OV for maximum flexibility.
3. The integration capacitor is external. Integration time is
user-programmable, from 2ms to 20ms. The maximum conversion rate is 200 conversions per second.
4. The dual slope integration conversion technique provides
superior high frequency noise immunity, and excellent normal
mode noise rejection of frequencies which are multiples of
the inverse of the integration period.
5. An internal precision -lO.OV reference is provided, but an
external reference may be used for multi-channel applications
where use of a system reference is required.
6. The pulse-width output is easily converted to digital binary
format by the addition of external IC counter-timers. The
counter clock rate is independent of the integrator clock rate.
ORDERING GUIDE
Model
Linearity
Error
AD367KM
±0.OO30S%FSR ±30Sf1V
Resolution
Temperature
Range
DATA ACQUISITION SUBSYSTEMS 9-13
•
SPECIFICATIONS
(lypicaI@
+25"&. Vs = ±15V. +5V. n = 4.11OOms,CIIr
=O.012p.FI unlassolhllwise noIIId)
AD367KM
Parameter
Min
ACCURACYIRESOLUTION
Integral Nonlinearity Error 2
Resolution 3
±305
ANALOG INPUTS
Range
Input Resistance
Common Mode Rejection Ratio4
VREF Input Resistance
Shorting Switch Isolations
0
80
90
300
45
DIGITAL INPUTS
Clock
VIH
VII.
Gain Bits·
VIH
VII.
viGi 1 ALOUTPUT (LSTIL Compatible)
VOH
VOl.
IOH
1m.
DYNAMIC PERFORMANCE
Conversion Time
Offset Pulse Width7
Scale Factor
Over Temperature
PSRR8
+15V±3%
-15V±3%
+5V±3%
POWER REQUIREMENTS
Positive Supply Range
Negative Supply Range
Logic Supply Range
Supply Current
+15V
-15V
+5V
Power Dissipation
TEMPERATURE RANGE
Specification
Operating
Storage
PACKAGE OPTION 1o(DH-24D)
Max
Units
0.00305
%FSR
....V
10
V
kO
dB
kO
dB
100
56
2.0
0.7
V
V
0.5
V
V
14.5
2.4
V
V
.... A
mA
0.4
-370
6
152
361
200
384
±IO
10
248
407
ms
....s
....sN
ppml"C
0.5
0.5
I
PROGRAMMABLE GAIN AMPLIFIER9
Maximum Gain
Minimum Gain
Resolution
Gain Error, Any Range
Gain Linearity Error
INTERNAL VOLTAGE REFERENCE
VREF
vs. Temperature
Maximum External Current without Degradation
Typ
....sN
....slV
.... slV
24
0.282
6
±2
±0.00305
VN
VN
Bits
%
%FSR
-9.95
-10
10
-10.05
15
500
V
ppml"C
....A
14.55
-14.55
4.75
15
-15
5
15.45
-15.45
5.25
V
V
V
lIOO
mA
mA
mA
mW
70
+85
+125
°C
°C
°C
18
23
27
750
0
-25
-55
24-PinDIP
NOTES
'Polystyrene or Teflon.
'Referenced to the input.
'Referenced to lbe output of lbe programmable gain stage (Pin 4).
'Source impedance < 10 0 to 10V
'A'NL (Pin 2)at analog ground.
'Open collector TTL and 15V CMOS compatible.
9-14 DATA ACQUISITION SUBSYSTEMS
.
VOSCRlNT,
.
'OffsetPulsewidlb(VlN=OV) = --V;;;-' Rim, = 327knnOIDmai.
"YIN = IOV,Gain = 1.03.
"Gain = 24 x (128 x BI + 64 x B2
+ 32
x B3 + 16 x B4 + 8 x B5
255
,oSee Section 14 for package outline information.
Specifications subject to change without notice.
+4 x
B6 + 3)
Principles of Operation - AD367
INTEGRATION
CAPACITOR
INTEGRATOR STAGE
>
---------->-_________
-, - - - - ,
MAr--~---__,
DATA
'---':.:....:::=----_ _-,
REF IN
>-_____-..J
REF OUT ~---------1
CLOC':
PULSE
OUT
>-______________---..J
AD367 Functional Block Diagram
BASIC OPERATION
The AD367 is a high resolution dual slope integrating converter
building block. Its output is a pulse width whose duration is
proportional to the input voltage and the gain selected. The
active-low output pulse is used to gate a separate counter which
accumulates pulses from a high speed clock. This partition of
the analog-to-digital conversion function into an analog processing
section and digital counting greatly reduces the potential for
crosstalk between the noisy digital function and the low-level
signal processing performed by the analog front-end. This preserves the inherent rejection of high frequency normal mode
noise that is a prime advantage of the dual slope conversion
technique.
The AD367 integrator stage uses the dual slope conversion
technique. A simplified dual slope converter is shown in Figure
I. While the input pulse is applied to clock in, the input signal
is applied to the integrator. After a predetermined period the
input pulse is removed, a reference signal of opposite polarity is
applied to the integrator, and the output pulse is initiated. At
the moment the integrator is switched to the reference (deintegration) phase the accumulated charge on the integrating capacitor
is proportional to the average value of the input over the integration
interval. The deintegration of the reference is an opposite going
ramp with slope VRJ;FiRC. When the integrator output reaches
zero, the comparator is tripped and the output pulse is terminated.
This completes the conversion cycle. Since the charge gained in
the integration phase is proportional to VIN X T (see Figure I)
and the amount of charge lost is proportional to VREF X t (and
equal to the amount of charge gained) t is proportional to VINNREF.
The converter output is thus a pulse whose width is proportional
to the input voltage. A dual slope converter is therefore a Voltageto-Time converter. If the output pulse is used to gate a binary
counter, the output of the counter will be binary digital representation of the input voltage.
INTEGRATION
CAPACITOR
INPUT STAGE
The AD367 is internally partitioned into a differential-input
amplifier, a single-ended user-programmable gain amplifier, and
the actual dual-slope converter. The differential amplifier allows
digitization of input signals with common mode voltages of up
to ± IOV. It has a nominal input impedance of IOOIdl and is
configured for unity gain.
COMPARATOR IS TRIPPED WHEN
(VINI T _ (VREFI ~t
~-~
The programmable gain amplifier (PGA) is programmed via a
6-bit digital code. If "B,", represents the logical value of the
most significant gain-selected bit, "B 2" the next most significant
bit, etc., then the gain of the PGA is:
G
=
(128B, + 64B2 + 32B3 + 16B. + 8B5 + 4B6 + 3) x 24
255
The gain-select pins are internally pulled-Up to the + 15V supply.
Gain programming can be accomplished using either an open
collector TIL Driver such as the 7406 or with 4OOO-series CMOS
(VDO = 15V). For fixed gain applications the gain-select pins can
be tied to analog ground or left open as required.
B,
II,
B,
B.
B,
B.,
GAlN(VN)
o
0
0
0
0
0
0
0
0
0
1
0.282
0.659
o
o
o
o
o
12.33
o
24.00
Table I. AD367PGA Truth Table
Figure 1. Simplified Basic Dual Slope Converter
ADVANTAGES OF DUAL-SLOPE INTEGRATION
Conversion accuracy is independent of the length of the clock
period and the integrating capacitance. Theoretical accuracy
depends only on the absolute value of the reference and the
stability of the clock. Even changes in other components such as
the comparator input offset voltage have no effect as long as
they do not change during a conversion. Differential linearity is
excellent since the technique is analog and inherently free from
discontinuities.
AD367 DETAILED OPERATION
The input differential amplifier operates with input voltages
within the common mode range of 0 to IOV. The input resistance
is lOOIdl (801d1 minimum) and there is a shorting switch on the
noninverting input for user calibration in single-ended mode.
DATA ACQUISITION SUBSYSTEMS 9-15
The input shorting switch shorts + VIN to ground through
20k!1 to limit the short circuit current of the driver. The AD367
inputs must be buffered. The AD OP-07 is well recommended
for this purpose, due to its low noise. For source impedances of
less than 5-10k!1 the AD OP-27 would be an even better choice.
Note: The high IIf noise of most FET and BiFET amplifiers
make them unsuitable for this application.
The offset of the PGA section is not trimmable per se, however,
the direct PGA output is available on Pin 4. Great care must be
exercised to avoid introducing extraneous signals at this point.
A more detailed procedure for offset trim and calibration of the
AD367 is given below in the calibration section.
The dual slope converter section is configured for a nominal
full-scale input voltage of lOY. In addition, the zero point of the
converter is offset by 5% full scale. This guarantees that the
converter linearity will not be degraded for inputs near zero.
Maximum linearity is obtained when the gain is programmed so
that the maximum full-scale input voltage produces an output
pulse of maximum duration consistent with the desired conversion
rate. Alternatively the gain can be set to provide a lOY signal to
the integrator (or Pin 4, the output of the PGA) when a fUll-scale
input is supplied.
The built-in offset is also used to protect against possible negative
polarity inputs while taking very low level measurements (or
"dark current" readings from optical sensors). The offset pulse
is accomplished by using a portion of the internal reference as
the threshold voltage to signal the end of conversion as shown
in Figure 2. This voltage appears on Pin 7 and is factory set for
The AD367 Transfer Function is:
Pulse Width
=
- VIN
VREF
X
RINT2 T 1
RINTl
+ Vos C RINT2
VREF
Where:
T 1 = The clock period
Vos = Voltage Offset (-O.SIOV nominal)
C = Integration Capacitor
RINTI = Signal Integration Resistor = 340k!1
RJNT2 = Reference Integration Resistor = 327k!1
VREF = -lOY (if internal voltage reference is used)
Figure 4 shows the AD367 operation for a near full-scale input
voltage. The input signal is integrated as the negative slope, and
the reference voltage as the positive slope. The output pulse is
low until the positive going edge (the reference integration phase)
exceeds - Vos (+ O.SIOV). The rising edge of the clock coincides
with the knee of the integrator and the falling edge of the
output.
Figure 5 shows a good view of the offset at work. A slight negative
input voltage will not cause an absence of output pulse
(VIN > - O.05V).
CONDo
OUTPUTPW-
C=O.OIS"F
T1==3.8ms
INTEGRATOR _
T2=6ms
Vos= -O.SI0V
V1N =9.59V
INPUT CLOCK-
FROM
INTEGRATOR
Figure 4.
74.4kO
COMPARATOR
OUTPUTPW _
VIN=OV
4kO
INTEGRATOR _
Figure 2.
INPUT CLOCK -
-O.SIOV, which yields a nominal200,...s offset pulse with a
O.012,...F integration capacitor. This offset pulse width may be
adjusted by using a 100k!1 potentiometer as shown in Figure 3.
tL
100kO
OFFSET PULSE
WIDTH ADJUST
Figure 3.
The leading edge of an externally applied negative going clock
pulse initiates a conversion. The AD367 will output a pulse
whose width is proportional to the input signal. The output
pulse is active low. Its leading (falling) edge is triggered by the
rising edge of the external clock, and its trailing edge is dependent
upon the input signal level. When using the internal reference
or with an external -lOY reference a clock pulse of 4ms provides
an integrator thll-scale range of lOY with a 0.012,...F integration
cap.
For other reference and integration capacitor values the signal
integration period should be adjusted to prevent saturation of
the integrator, i.e., the maximum integrator deflection should
not exceed lOY.
9-16 DATA ACQUISITION SUBSYSTEMS
Figure 5.
To maximize the resolution and accuracy of the converter, the
PGA gain should be set such that the maximum input signal
voltage provides a lOY signal to the integrator (Pin 4). Then the
clock pulse width and integratioD capacitor should be selected
using the relation:
Tl
-c
"" RINTl = 340k!1
INT
This ensures that the maximum dynamic range of the integrator
is used, and will result in the best linearity from the converter.
Polystyrene or Teflon capacitors only are recommended. The
AD367 Timing Diagram is shown in Figure 6.
PGA settling under worst-case conditions (Gain = 24, full-scale
input voltage step) is typically 70,...s, as shown in Figure 8. The
PGA output must be allowed to settle before a conversion is
initiated, or the first conversion result after an input voltage
change ignored if the AD367 is operated in continuous conversion
mode. Figure 9 shows the PGA settling after a change from
minimum to maximum gain (0.282 to 24 VIV), which is also
70,...s typically.
Applications - AD367
CLOCK IN (PIN 12)
ov
--4.,.......---r'~A--P.-1'"\
INTEGRATOR (PIN 19)
I
I
1
I
1
I_ T2 (REFERENCE INTEGRATION.
I
INCLUDING OFFSET) = PULSE WIDTH
point as close to the converter as possible. Ideally, a single solid
ground plane under the converter is desirable. Current flows
through the wires and etch stripes of circuit cards, and since
these paths have resistance and inductance, hundreds of millivolts
can be generated between the system analog ground and the
ground pins of the AD367. Separate wide conductor stripe
ground returns should be provided for high resolution converters
to minimize IR losses from current flow in the converter to
system ground run. Care must be taken to prevent digital logic
return currents from being summed into the same return path
as analog signals to prevent measurement errors.
OUTPUT (PIN 13)
Each of the AD367's supply terminals should be capacitively
decoupled as close to the AD367 as possible. A large value
capacitor, such as l(JoF, in parallel with a O.l(JoF capacitor is
usually sufficient. Analog supplies should be decoupled to the
analog ground pin, and the logic supply to the digital ground
pin.
Figure 6. AD367 Timing Diagram
CALIBRATION
The AD367 should be endpoint calibrated for maximum system
accuracy. Calibration is a straightforward procedure:
1. Choose a gain consistent with keeping the output of the
programmable gain amplifier at or below lOY when a full-scale
input voltage is applied.
2. Apply a zero input signal, Vz . Use the shorting switch if the
input is single-ended. The shorting switch will ensure a good
ground potential at the input.
3. Measure the output offset pulse, PWos.
4. Apply a known full-scale voltage, VFS, to the inputs.
5. Measure the output full-scale pulse, PWFS '
6. Subsequent measurements will give, to within ± 0.00305%
FSR, the input voltage according to the following equation:
(VFS-VZ )
VIN = (Pulse Out-PWos) x (pWFS-PWOS)
+
GAIN=24
V1N=O.OO TO O.417V STEP
(ZERO TO FULL SCALE)
Figure 8. AD367 PGA Section Settling
Vz
V1N =O.4167V
INPUT, GROUNDING, AND DECOUPLING
CONSIDERATIONS
For most applications, the AD367 will be used with single-ended
inputs and the internal - 10V reference. The connections for
this mode of operation are shown in Figure 7, including input
buffering, power supply decoupJing, and input ground sense.
As with many data acquisition components, the AD367 has
separate analog and digital grounds. These pins (15 and 17) are
not connected internally, but should be tied together at one
GAIN TRANSITION
FROM 000000
TO 111111
(0.282 TO 24VN)
Figure 9. AD367 PGA Section Gain Settling
The metal case is at analog ground potential for shielding. Care
should be exercised to prevent shorting to board circuitry beneath
the part.
GENERAL INTERFACE CONSIDERATIONS
The control logic of the AD367 and the synchronous counter
scheme shown in Figure 10 makes direct connection to most
microprocessor buses possible. While it is impossible to describe
the details of the interface connections for every microprocessor,
a representative example is presented here.
S/G
v.
OUT
G~~-------<
CLOCK IN
Figure 7. Input Connections for Single-Ended Operation
Anaiog-to-dit;ital converters, like any 110 device, may be interfaced
to microprocessors by several methods. These include direct
memory access (DMA), isolated or accumulator 110, and memorymapped 110. DMA is the fastest, since conversions occur automatically and data updates into memory are transparent to the
processor. DMA logic is very processor-dependent and requires
specialized dedicated hardware.
DATA ACQUISITION SUBSYSTEMS 9-17
IJ
+1"
•
11
SCUi
LD
FOOM
3.7
'AST
CLOCK
-02
iNii
-~
CCK
,
ulii
74ALS569A
EN'i' OE
ACLR ~
~ZJ'
8
18
,. '"I.
Q,
+jV
,
20
V"
•
7
RCO
+51'
,
20
11
•
,
20
7
.!!...!!
Q g GND
I"
13~O
8
18
,.
7
.2!...!!
74ALS589A
Z
I"
~a
13
00
.!!....:!!
z
74ALS569A
Z
I.
+i
• "
V
11
.
'8
,.
,.
'3
t7
OEH
20
74ALS569A
•
,. ,. ,.
13~O
I"
CLO
Msa
I
8-BIT BUS
Figure 10. General Counter Scheme 8-Bit Bus
Memory-mapped and accumulator 110 are more often used and
easier to implement. Accumulator 110 uses a distinct set of
control signals which, combined with the address bus, define a
totally separate 110 address space. The architecture is simple
from a hardware standpoint, since address decoding requirements
are not severe, and distinct 110 pulses are easily located for
system debugging. However, processors using accumulator 110
can generally only send data to an outpUt device from the accumulator. This can make for cumbersome software, since processor controlled transfers of 110 data to a memory location
cannot be accomplished in a single instruction.
Memory-mapped 110 assigns the 110 device to one or more
locations in the logical memory space of the microprocessor.
This technique has the advantage that the full range of memory
reference instructions may be used to operate on the data. The
potential disadvantages include limiting the memory space available for program and data memory, somewhat more complex
address decoding and more difficult isolation of device select
pulses for system debugging. Nevertheless, many microprocessors
offer only the memory-mapped 110.
CONNECTING COUNTERS FOR DIGITAL OUTPUT
Figure 10 shows a simple circuit for converting the AD367
pulse width output to binary digital code using the 74LS569A
synchronous counter. This scheme is compatible with fLP systems
using an 8-bit wide data bus structure, such 11& the 6809. It is
easily upgraded to l6-bit structures by connecting OEH to OEL
and connecting the 16 outputs directly to the bus instead of
together.
Decode logic for the 6809fLP is shown in Figure 11.
AO
RDIWR - - - - -.....-1 -'~--.._,
Figure 11. Decode Scheme for 6809
PIN CONFIGURATION
•
BUFFIOUT
3
PGAIOUT
4
REF IN
5
OFFSETITRIM
INPUT
SHORTING SWITCH
T.P.
CLOCK IN
9-18 DATA ACQUISITION SUBSYSTEMS
AD367
REF OUT
I-IOV)
7
TOP VIEW
(Not to Scalel
INTEGRATION
CAPACITOR
Complete 12-Bit AID Converters
with Programmable Gain
AD368/AD369 I
IIIIIIIIIII ANALOG
WDEVICES
FEATURES
Low Cost Data Acquisition Systems Including:
Programmable Gain Instrumentation Amplifier
Track-and-Hold Amplifier
12-Bit AID Converter
Digitally Controlled Gains:
AD368 Gains=1, 8, 64, 512
AD369 Gains=1, 10, 100, 500
50kHz Throughput Rate
Small Size: 28-Pin Hermetic Double DIP
Guaranteed No Missing Codes Over
Specified Temperature
True 12-Bit Linear; Error ..;1/2LSB IB-Gradel
Unipolar or Bipolar Operation
MIL-STD-883B Screening Available
AD368/AD369 FUNCTIONAL BLOCK DIAGRAM
DIFF
INPUT
GAIN
RIP
OFF
SELECT
APPLICATIONS
Microprocessor Based Data Acquisition
Wide Dynamic Range Measurement Systems
Analytic and Medical Instruments
Multichannel Systems With High/Low Level Signals
PRODUCT DESCRIPTION
The AD368/AD369 are low cost, wide dynamic range data
acquisition systems which condition and subsequently convert
an analog signal into a 12-bit digital word. They include a programmable gain amplifier, a track-and-hold amplifier, and a
12-bit analog-to-digital converter - all in a 28-pin dual in-line
package.
The digitally programmable-gain amplifier (PGA) of the AD368
enables the user to select binary-based gains of I, 8, 64, and
512. These gain steps are especially useful in extending system
dynamic range in DSP applications. The PGA of the AD369,
with gains of I, 10, 100, and 500, allows the user to choose full-
START
CONVERT
scale input voltage ranges of lOY, IV, 100mV, and 20mV,
respectively. In addition, the precision differential input of the
PGA provides the AD368/AD369 with excellent common-mode
rejection.
The track-and-hold amplifier (TIH) features excellent linearity,
low noise, and an internal hold capacitor.
The successive approximation analog-to-digital converter (ADC)
features true 12-bit operation, with 0.012% max nonlinearity
(B-grade). The user can select bipolar or unipolar operation to
digitize both ac and dc input signals.
The AD368/AD369 provide a completely specified (industrial
and military temperature ranges) and tested function in a space
saving 28-pin hermetic package for system designers with cost,
space, and time constraints.
ORDERING GUIDE
Model
AD368AD
AD368BD
AD368SD
AD369AD
AD369BD
AD369SD
Monotonic Temperature Range
10 Bits
12 Bits
- 55°C to + 125°C
- 55°C to + 125°C
-25°Cto
- 25°C to
- 55°C to
- 25°C to
- 25°C to
- 55°C to
+ 85°C
+ 85°C
+ 85°C
+ 85°C
+ 85°C
+ 125°C
Offset Temperature
Drift
Units
25 + 0.2
10 + 0.1
25 + 0.2
25 + 0.2
10 + 0.1
25 + 0.2
mV
mV
mV
mV
mV
mV
x
x
x
x
x
x
G
G
G
G
G
G
DATA ACQUISITION SUBSYSTEMS 9-19
•
•
SPECIFICATIONS
(typical @ +25"1:, Vs = ±l5V, +5V, RspNi = 630 and R(BlP) = 310 unless otherwise noted)
AD368AD/SD
AD369AD/SD
Parameter
ANALOG INPUT
Voltage Range, Unipolar(G= I)
Voltage Range, Bipolar(G= 1)
Common-Mode Voltage
Resistance
Capacitance
Bias Current (IB)
IB vs. Ternperamre
Input Offset Current (los)
los vs. Temperature
Noise Current (0.1 to 10Hz)
Output Offset Voltage (Vas)'
Vosvs. Temperature
Vosvs.Common-ModeVoltage2
Vas vs. Supply Voltage'
Output Noise Voltage (rms)
G=I
G=8,10
G=64,I00
G=512,500
DIGITAL INPUTS'
VIH
V1L
IIH' IlL
CIS Pulse Width
DIGITAL OUTPUTS, 12-BITPARALLEL
VoH@loH = -40",A
VoL@loL = 1.6mA
Min
Typ
0
-5
AD368BD
AD369BD
Max
Min
+10
+5
*
*
12 -(VDIFFXG/2)
10"
5
10
50
2
20
60
5+0.02xG
70+0.2xG
6O+0.5xG
100+ 1.0xG
50
20
25+0.2xG
300+2.0xG
320+3.2 xG
2300+ 10xG
250
•
*
*
*
0.01
Vee
0.8
1.0
ACCURACY
Integral Nonlinearity
Differential Nonlinearity (DNL)6
Gain Error@G= 1
@ Other Gains Referred to G = 17
Gainvs. Temperamre@G=1
@ Other Gains Referred to G = 1
Gain vs. Supply Voltage
Vp ±lo%
VN ±10%
Vee ±lO%
9-20 DA TA ACQUISITION SUBSYSTEMS
*
*
*
50
SIGNAL DYNAMICS
Conversion Time (tc)
Ie vs. Temperature
System Throughput RateS
G=I,8,1O
G=64,IOO
G=512,500
Gain Switching Time·
PGA Settling Time (to 112LSB)
G=I,8,1O
G=64,IOO
G=512,500
Amplifier - 3dB Bandwidth
G=1
G=8,10
G=64,I00
G=512,500
Tt!! Acquisition Time (tACQ to 112LSB)
T/H Aperture Delay Time (tAP)
tAP vs. Temperature
Apermre Jitter
*
*
*
*
*
*
*
*
*
*
*
*
260
340
600
3.0
0.0
3.6
Typ
5.0
0.2
0.4
12
15
-10
*
Max
Units
*
*
V
V
V
n
pF
25
nA
10
nA
pArC
10+0.lxG
*
150+ 1.5 xG
l000+4xG
",V
",V
",V
",V
*
*
*
*
*
*
*
*
*
*
"'S
nsf'C
kHz
kHz
kHz
fLs
fLS
fLS
1.5
50
50
20
2.0
*
*
*
*
*
8
12
40
10
15
50
*
*
*
*
*
*
1000
400
150
40
140
-0.3
I
3
250
pArC
pAp-p
mV
",Vf'C
",VN
",VN
*
*
*
*
*
*
*
V
V
",A
ns
V
V
fLS
kHz
kHz
kHz
kHz
*
*
fLS
ns
nsf'C
ns
0.30
0.30
0.05
0.01
3
3
0.75
0.90
0.5
0.1
30
10
*
*
*
*
*
*
0.5
0.5
0.2
0.05
*
*
LSB
LSB
%
%
ppmf'C
ppmf'C
10
5
5
30
30
15
*
*
*
*
*
*
ppm/%
ppm/%
ppm/%
AD368/AD369
Min
Parameter
MONOTONIC TEMPERATURE RANGE
12 Bits
10 Bits
REFERENCE
Voltage (VREF)
VREFVS. Temperature
Internal Resistance
External Load
AD368AD/SD
AD369AD/SD
Typ
Max
-25
- 55 (S Grade)
- 55 (S Grade)
6.28
6.30
AD368BD
AD369BD
Typ
Min
Max Units
+85
+ 85 (S Grade)
+ 125 (S Grade)
-25
6.32
20
*
*
2
0.5
POWER REQUIREMENTS
Positive Supply Range
Negative Supply Range
Logic Supply Range
Supply Current, VIN = lOY, fc=50kHz
+15V
-15V
+5V
Power Consumption
+ 13.5
-13.5
4.5
15
-IS
5.0
IS
30
20
775
THERMAL RESISTANCE (J-A)
16.5
-16.5
5.5
*
*
*
20
40
35
*
25
PACKAGE OPTIONS
DH-28A
*
+85
°C
°C
°C
*
*
V
ppmfOC
n
*
rnA
*
*
*
*
*
*
V
V
V
*
*
*
*
*
*
rnA
rnA
*
rnA
mW
°CIW
AD368BD
AD369BD
AD368AD/SD
AD369AD/SD
NOTES
*Same specifications as A Grade.
IOffset voltage applies to both bipolar aod unipolar operatiog modes.
'VCM = ±lOV.
'Vs = ±IO%.
'For digital ioputs, pull-up resistors needed (typ SIdl) when ioterfaciog with TILIDTL logic.
SAssumes pipelioiog, i.e., signal is ioputted to LA. when T/H goes ioto hold mode, allowing voltage
to settle concurrently with AID conversion (see timiog diagram).
6Inc!udes TIH droop rate.
'This is gaio error (% FS) after error at G = I is caoceDed by adjustment. Without adjustment, total error becomes:
E(TotaI) = E(G= I) + E(G=8/1O,641100,orS12/S00).
'See Section 14 for package outline information.
Specifications subject to chaoge without notice.
Parameter
ABSOLUTE MAXIMUM RATINGS
Min
Max
Positive Supply, Vp
Negative Supply, VN
Digital-to-Analog Ground
Logic Supply
Analog Input (Either)
Analog Input Current
Lead Soldering, 10 sec
Storage Temperature
-0.3
+0.3
-1
-0.3
VN
-10
-65
+ 17
-17
+1
+7
Vp
+ 10
+300
+ 150
II
Units
V
V
V
V
V
rnA
°C
°C
DATA ACQUISITION SUBSYSTEMS 9-21
LOGIC OUTPUTS TYPICAL PERFORMANCE GRAPHS
-....
-....
TEMP=25OC
r
Vcx:=8V
I"-..
6.5V
t-....
5V.......
i'o..
r---.... 4~
~ ........
"" "'"
I'.,.
r.....
Vee
--
=
4.5V
4V
V
V
J....-':
5.SV
5V
V V V
14
16
18
20
o
-2
-4
OUTPUT SINK CURRENT-rnA
Logic Low Level Output Voltage vs. Sink Current
i"'-...
r-.... i"...
.......
.........
r--..
I"
'\
1\
~
\
~ t;::::-
12
""'"
'\
6V
o
10
TEMP::::25'"C
\
\
\
ro....
"\.
"\.
\
1\
\ \
\
\
\
I\.
\
,
\
-6
-8
-10
-12
-14
OUTPUT SOURCE CURRENT - rnA
-16
-18
-20
Logic High Level Output Voltage vs. Source Current
1
1
Vee= +5V
Vee:::: +5V
~k...
,
I"::' t---...
........ ............
..........
"""''\. r--..
2S'C
TEMP=125"C
./
.,/
,.--
i.--"':
o
o
10
12
./
./
\
----
,.
16
'\
TEMP=l25OC\
-55'C
H
-2
OUTPUT SINK CURRENT - rnA
Logic Low Level Output Voltage vs. Sink Current
-4
\ TEMP= - sS'C
y~!!,!=\
\
\
18
"'" \
1\
\1
\f
1\
-6
-8
-10
-12
-14
OUTPUT SOURCE CURRENT - rnA
-16
-18
-20
Logic High Level Output Voltage vs. Source Current
AMPLIFIER LARGE SIGNAL RESPONSE
O.01%/DIV.
10,"s/DIV.
AD369 Input Stage Output Voltage
9-22 DATA ACQUISITION SUBSYSTEMS
10,"s/DIV.
AD369 Input Stage Settling Time
Theory of Operation - AD368/AD369
ANALOG INPUT
An analog multiplexer and resistor network form the gain switching
circuit of the PGA. As shown in Table I, the user selects a gain
according to the state of binary address inputs GO and G I.
pulse is 15",s, maximum. A low output on the Status line indicates
that the conversion is complete. The data at the output is valid
at least 15ns before the Status goes low (see timing diagram).
This gives sufficient setup time so that data may be latched to
an external register on the falling edge of the Status pulse. The
TIH amplifier returns to the tracking mode when the Status line
goes low. Data is valid at the output until the next falling edge
of a CIS pulse. After a maximum of 3",s acquisition time, a new
CIS pulse may be issued to begin a new conversion. Timing
diagrams are shown in Figure 1.
Also shown in the table is the input range data. The full-scale
range of the DAS is IOV, and an LSB value is 4.8",V/4.9",V in
the gain 512/500 mode; therefore, the dynamic range of the
AD368/AD369 is 126dB.
The PGA uses a monolithic instrumentation amplifier, which is
based on the classic three-op-amp approach. The differential
analog input is amplified, according to gain selection, by two
input op amps. The third amplifier, a unity gain subtractor,
removes any common-mode signal and yields a single-ended
output.
Figure la shows timing when a conversion sequence has first
begun. All functions are being performed in series. This is the
timing for the first data conversion, assuming a new gain must
be selected.
The timing in Figure I b assumes conversions are progressing
continuously. After a conversion has been initiated by the falling
edge of the CIS pulse, a new analog signal may be inputted to
the DAS or a new gain may be selected. The fIgure shows that
if a new gain is selected, no more than 2",s later, the new voltage
begins settling at the PGA output. In the G = 512/500 mode, the
determining factor for conversion speed is the amplifier settling
time and, if necessary, the gain switching time. If the PGA gain
is not switched, the conversion time for G = 512/500 becomes
50",s, maximum, and a minimum throughput rate of 20kHz can
be achieved.
DATA CONVERSION
The track-and-hold amplifier is a monolithic device with an
internal hold capacitor. It has an acquisition time of ,.;;3",s.
Input signals are digitized using a successive-approximation AID
converter. The rising (L to H) edge of the Convert Start pulse
resets the internal flip-flops of the SAR. The falling (H to L)
edge of the pulse initiates the conversion. After an aperture
delay of 230ns, the track and hold amplifier goes into the hold
mode, and the Status output goes High, indicating a conversion
is in progress. Conversion time from the falling edge of the CS
--if4-tClS~50t0'
CON"'~~TART
VOLTAGE
SELECT
CODE
G1, GO GAIN
"«~h::=====~'fIJ,~WJ.~OOOI'fIJ,OOOI»X===
IW
~tosMAX
r- ---1'L-
-----It
ANALOG INPUT
1
-'~~A=~=~~U.=E=.aA~V-"~~-",------------1I~--
STATUS OUTPUT---.l.J
I
V2CONVERSION
m:=COV'N••.
.- ON
~~~I~I.~~«»~CO~N~""~M~I~~T~'M~'~"~5·~'~~«O'~I~~~I~~.~.<;~
D:T~rgu';1.2UT =Vl CODE
V2 CODE
DATAREADYOi!=15n5BEFOAE-!1.STATUS LOW
I
ANALOG OUTPUT
~--------~I--_~
VOLTAGE OF THE
AD3t9 PROGRAMMABLE
INPUT AMPLIFIER
I
TlMEl
I-"GA. TIH SETTLING
. " .... t" 0=1,8,10
16ps(O/ 0"64,100
SOpl(II G=512,600
--I
ANALOG INPUT
VOLTAGE
tc....-=50n&
~
CONVERT/START
PULS.
I
j,...
STATUS OUTPUT - - - - ,
I
L--
THE PROGRAMMABLE
GAIN AMPLIFIER
t---CONVERSION TIME S 151l.----i
I--- PGA aTlH S.TTUNG TIM.
~ ~ DA!A,~!LlD
~
J.--MAXIMUM CONVEftSION TIME: . Z.... (#! G"','.10 --..j
B'rgU'WJ?"TA"IIII/t1
,_0
I
OUTPUT VOLTAGE OF
APERTURE DELA V s 350nl
I
'" "Il' (i. 0=1.8,10
. 33...1'" G=64.100
. 87...,1<' 0=512,500
I
ACQUISITION
-='---jf---++-<(S)
SUPPlY >-=---+"t--{~
AGND
Figure 3. AD3681AD369 in the Un~Dolar Mode with RTI
Vos, RTO Vos and Span Trimpots
Calibration steps for input stage offset voltage (Vos)
cancellation:
1. Connect the inputs to analog ground.
2. Set G=512/500 and turn RRTI all the way clockwise (CW).
This shifts the transfer function to the right, causing the
output code to be all ones. The LED will light up.
3. Now turn RRTI counterclockwise (CCW) until the LED dims
to half brightness. The first transition is now positioned at
the VIN=O line.
4. Switch to G = 1 and turn RRTO all the way CW. This will
cause the output code to be all ones again.
5. Turn RRTO CCW until the LED dims; the first transition is
at OV again.
6. Switch the gain to G=5121500, turn RRTI CW just enough to
assure an all ones code, then tum it CCW until the LED
dims to half brightness.
7. Switch the gain back to one, turn RRTO CW enough to assure
an all ones code, then turn it CCW until the LED dims.
8. Repeat steps 5 and 6 until the LED brightness does not
change when switching between G = 1 and G = 5121500. The
input stage offset voltage is now zero.
Calibration steps for the output stage offset voltage (Vos)
cancellation:
1. Connect the inputs to a 2.44mV supply, as in Figure 4.
2. Set G= I, turn RRTO all the way CW, assuring an all ones
output and lighting the LED.
3. Turn RRTO CCW until the LED dims to half brightness.
The first transition is now ILSB above OV.
+15V
Rl
6l.2kfi
2.44mV
t---.+
R2
10fi
OIFFERENTIAL
INPUT
Figure 4. Input Connection for the RRTO Calibration
Using the AD368/AD369
Calibration steps for Gain Error (SPAN) cancellation:
BIPOLAR MODE CALIBRATION
1. Apply a precise IOV-2.44mV across the input of the AD3681
AD369. A voltage divider as shown in Figure 5 can be employed;
in conjunction with a precision voltmeter to verify an input
of 9.997,S6V.
2. Set G= I, turn RSPAN all the way CCW, assuring an output
of all zeros.
3. Turn R SPAN CW until the LED begins to light up (about
half-brightness). At this point the last transition will be at
+FS -ILSB.
The AD368/AD369, with calibration hardware, are shown in
Figure 6 for operation in the bipolar mode. The adjustments
begin, as in the unipolar case, with the input stage Vos cancellation.
In this case however, the calibration is different because the OV
point is now at mid-scale; the MSB is used instead of the LSB.
Next in the calibration is to adjust RRTO and put the first LSB
transition at an input voltage of - SV + ILSB. Last is the RsPAN
adjust to put the last bit transition ILSB below +SV.
The calibration in the unipolar mode is now complete.
I. Conoect the inputs to analog ground.
2. Select G=SI2I500 and turn RRTI until the MSB LED is at
half-brightness.
3. Switch to G= I and adjust RRTO until the LED is again at
half-brightness.
4. Repeat steps 2. and 3. until the LED brightness does not
change when gains are switched. This indicates that the
input stage Vos = OV.
+15V ±1%
2.49kll
9.997.56 V
--_+
~-o--......
DIFFERENTIAL
INPUT
Input stage Vos cancellation steps:
Output stage Vos cancellation steps:
Figure 5. Input Connection for the RSPAN Calibration
1. SetG=1.
2. Conoect the plus input to ground and the minus input to
4.997,56 volts using a voltage divider such as in Figure 7.
3. Turn RRTO completely CW to assure an output code of all
ones.
4. Now turn RRTO CCW until the LSB LED dims to halfbrightness. The first transition is now ILSB above - FS.
+1SV±1%
4.99kll
tCW
4.997.56 V
RIBIP!
ANALOG>-'~-+--H~
SUPPLY
.)--<~,-,-,,=---_+-..l
zoo
)-'=-----+lo(
~-o--_--.+
DIFFERENTIAL
INPUT
AGND
Figure 7. Voltage Divider to Derive RTO Vos and Span
Calibration Voltage
Gain Error cancellation steps:
Figure 6. AD368/AD369 in the Bipolar Mode with Offset
and Gain Trimpots
1. Set G= 1.
2. Now conoect the plus input to 4.997,56 Volts and the minus
input to analog ground.
3. Turn RsPAN completely CCW to assure an output code of all
zeros.
4. Now turn ~AN CW until the LSB LED begins to light up.
At this point the last bit transition will be at + FS -ILSB.
Calibration in the bipolar mode is now complete.
DATA ACQUISITION SUBSYSTEMS 9-25
I
,.
CALmRATING THE ,\1)3681,\1)369 WITHOUT
TRIMPOTS
Figure 8 shows the AD3681AD369 in the unipolar mode with
calibration hardware consisting of a Quad 8-Bit D/A Converter
(AD7226) circuit instead of the previous trimpot configuration.
The calibration procedure is basically the same as before except
tbat instead of adjusting the potentiometers, three DACs are
used to correct for offsets and gain error. Bipolar calibration
may be accomplished by referring to Figure 6.
This calibration routine has some excellent benefits in addition
to the elimination of potentiometers. Dipswitches may be used
initially to set the 8-bit word values needed for each connection;
however, after the word values are determined, this data
may be stored into a memory (i.e., RAM) for auto-calibration
in the field. The entire calibration may be accomplished
under microprocessor control. Temperature offsets may be
cancelled by using a temperature sensor in conjunction with
a microprocessor.
12
GAIN 1
-
-8
!
GAIN 10 - - - - GAIN100------
-
-,
I
I
GAIN 500 -
,.,,,.-'
,. ,.
I
-1.-1. I
,
-1'
/,'
,
I
----
./
".-'
1
-
--
Ir--- i - - -
-1'
-
I
,,
-
I
!
,
,-1"
,
I,"
v::t
~
-,
I
/
I
I
/
-8
I
(
r
/
-
~ ,.
,...--
AD369
c---
-15V
,.
DIFFERENTIAL INPUT VOLTAGE - V
Figure 9. Input Current vs. Differential Input Voltage
Without Input Protection
Vp = +15V
VOUTD
19
DATA
8US
15
WR
16
A1
17
DIFFERENTIAL
INPUT
r- . . .
-I ............
+IN
20
AD722&
AD368/AD369
FD333
lkH
V OUTC
10 VREF
-IN
V.otJT4
I
lkH
-I ".- ".-
00
>---+[Ij1J.~~g=~~~1:-Jl<
>
V
FD333
GAIN
".-
V N = -15V
CODE
Figure 10. Input Protection Circuit for AD36B1AD369
-15V>-+--+-/-t
A::~~ AGND >---+H.!~
>-___
+15V
~.'
»--____--<
} + - - - - = " ' ( LOGIC
SUPPLY
Figure 8. AD36B1AD369 in the Unipolar Mode with DIA
Circuit Replacing Trimpots
INPUT PROTECTION
There are two considerations when applying input protection for
the PGA: 1) tbat maximum input current must be limited to
less than 20rnA and 2) that input voltages must not exceed the
supplies. Outside the linear operating range, the input iI!tpedance
of the AD368/AD369 becomes low and nonlinear due to the
input transistors going into saturation. The graph in Figure 9
illustrates the input current vs. differential input voltage relationship without input protection.
Resistors of lkO in series with each input would keep the currents
within safe limits for input voltages in the range of Vp= + 15V
to VN = - 15V. Figure 10 shows the external components necessary
to protect the AD368/AD369 under all overload conditions at
any gain. The diodes to the supplies are necessary if input voltages
outside of the range of the supplies are encountered.
9-26 DA TA ACQUISITION SUBSYSTEMS
The equivalent noise resistance of the AD368/AD369 input
stage is only lkO. Input protection resistors, however, will
quickly degrade this excellent Iioise performance. To reduce the
noise encountered with added resistors, FETs may be used to
limit the input current. FETs, such as the 2N4416, with low
loss and low on-resistance should be used. Figure 11 shows the
protection circuit and Figure 12 shows the input current vs. the
differential input voltage with the PET protection circuit. The
20kO resistor is put in series with the gate to limit the "reverse"
loss current and does not add to the noise.
The above input protection circuits also protect the AD368/AD369
in case there is a voltage applied to the input while the supplies
are shut off.
Vp
AD368/AD369
+IN
-IN
1' ......
-l
............
I
>
--I
//
1,../
Figure ". Low Noise Input Protection Circuit for AD36B1
AD369
Using the AD368/AD369
If using multiplexers, proper device selection can provide AD3681
GROUND CONNECTIONS
AD369 input protection. Some MUXes limit the maximum
current as well as the maximum output voltage to safe levels.
Keep in mind that the on resistance of the MUX will add to the
input stage noise.
The digital and analog ground pins of the AD368/AD369 should
be tied together as close to the package as possible to avoid
noise coupling from the digital ground to the analog circuit.
When an application calls for separate grounding entirely, a
O.I ...F capacitor should be Connected between the AGND and
DGND pins to filter out any noise.
15
,.
,
,~:
~,
I
J-- -5
a...
I
-10
,
J~'
1//
~
!: -15
GAIN 1
GAIN10
Each of the AD368/AD369 supply terminals should be capacitively
decoupled as close to the IC as possible. A I ...F in parallel with
a O.I ...F capacitor is usually sufficient. Analog supplies are
decoupled to the analog ground pin and the Logic supply is
decoupled to the digital ground pin.
-----
t--
GAINSOO------RIG) "" 20kn
DSS '
-25
-20
-15
-10
10
15
20
25
30
DIFFERENTIAL INPUT VOLTAGE - V
Figure 12. AD625 Input Protection with 2N4416 FETs and
FD333 Clamping Diodes
GROUND RETURNS FOR INPUT BIAS CURRENTS
There must be a direct return path for the input bias currents
of the PGA input transistors; otherwise, they will charge external
capacitances, causing the output to drift uncontrollably or saturate.
Therefore, when amplifying floating input sources such as transformers, or ac-coupled sources, there must be a dc path from
each input to ground as shown in Figure 13.
AD368/AD369
1',
~ ~S---+-i
">
~ C=;i~-+-t- --I
TRACK-AND-HOLD ERRORS
The aperture delay time is the time required for the track-and-hold
amplifier to switch from track to hold. Since this is effectively a
constant, it may be tuned out by advancing the track-ta-hold
command with respect to the input signal.
,i 'I ,.mj
/
-3.-30
POWER SUPPLY DECOUPLING
!J
GAIN 100 - - - - - - -
/'
-2.
-25
'
. / ,-
--
' j r-
", ",
Unlike the aperture delay time, aperture jitter is a true error
source and must be considered. Aperture jitter is a result of
noise within the switching network. It causes variations in the
value of the analog input being held. The aperture error which
results from this jitter is directly related to the dVIdT of the
analog input and may limit the signal bandwidth. The aperture
jitter of the TIH in the AD3681AD369, however, is small enough
that the instrumentation amplifier will limit the signal frequency
well below the frequency at which the jitter error would be of
concern.
Droop rate is the change in output Voltage per unit of time
while in the hold mode. Hold mode droop originates as leakage
from the hold capacitor, of which the major contributors are
switch leakage current and bias current. This dVotrrldT is
equal to the ratio of the total leakage current, I. to the hold
capacitance, CH • The droop rate of the TIH in the AD3681AD369
is included in the differential nonlinearity specification.
COMMON-MODE REJECTION
",'"
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change. Care should be taken to assure that both input lines are
balanced with regard to parasitic capacitances and source resistances; otherwise, the excellent common-mode rejection of the
AD368/AD369 will be degraded.
TO ANALOG GROUND
Figure 13a. Ground Returns for Bias Currents with
Transformer Coupled Input
ERRORS DUE TO BANDWIDTH LIMITATIONS OF
A_AD. .
1',
\
-l
"I
'>
",
",
-l
1,.-/
lOOk!!
THE AD368JAD369
When using the AD368/AD369 to digitize sine-wave signals, it
is important to know the frequency at which the system response
roll-off will cause an error of 1/2LSB.
The ratio of output to input voltage for the instrumentation
amplifier of the AD368/AD369 is:
lOOk!!
I VoNll = GIl (I +jflf.) I = G/[I + (flf.)2f·s
TO ANALOG GROUND
V
Figure 13b. Ground Returns for Bias Currents with ac
Coupled Inputs
where f. equals the - 3dB bandwidth and a single-pole roll-off
is assumed.
It can be shown that the VoNl ratio will have an error of 1I2LSB
for a 12-bit AID converter when:
f(1I2LSB)
= f/ViTI) = f.l64.
DA TA ACQUISITION SUBSYSTEMS 9-27
I
I
The instrumentation amplifier will have reached the limit of
12-bit precision for signal frequencies of f./M. The frequency
can be doubled at the expense of two bits of accuracy.
The frequency at which the amplitude of a 10V p-p sine wave
is reduced by one half of an LSB is typically 10kHz,
3.5kHz, 1.7kHz, and O.SkHz at gains of I, 10, 100, and 500
respectively.
NOISE CONSIDERATIONS
Assuming normally distributed or white noise, the rms noise
voltage En of a system is a function of its noise bandwidth BWN •
The corre1ation between - 3dB bandwidth (BW) and BWN is
dependant upon the frequency response of the system under
consideration.! For a 6dB/octave filter, the ratio is '11"12= 1.57.
For a "brick wall" filter it is one. The noise correlation is simply:
~=~VBWN' where ~ is the noise density (nVl'v'HZ).
The noise of the input signal must also be added to the noise of
the DAS. Again, in calculating the rms noise contribution of the
signal, the BWN of the source must be considered. If not filter
limited before the AD368/AD369 input, the BWN of the PGA,
as stated above, must be used, wbich is about 'rr/2 times its
- 3dB bandwidth.
Input protection resistors will also contribute to the total system
noise. The rms noise voltage of a lkO resistor over a noise bandwidth of 1Hz is 4nV. So, the noise voltage of a resistor, R(kO)
and a noise bandwidth, BWN(Hz) is: E N(R)=4nVVRxBWN.
The total system rms noise is given by the equation:
ENCsystem) =VENCAD369)Z + [G x ~(RIN)JZ + [G X ENCsig)]2
Once the system rms noise value is known, the probability of
the peak-ta-peak value of the noise exceeding an LSB is given
in Table II.
Probability of Noise
Exc:eedinglLSB
1.0
2.0
3.0
4.0
5.0
5.15
6.0
6.6
62.0%
32.0%
13.0%
4.6%
1.2%
1.0%
0.27%
0.10%
Tablsll.
'See "Low Noise E1eetrcmic Desip," by C. D. Motcheabacher,
F. C. Fitchen.
9-28 DATA ACQUISITION SUBSYSTEMS
OTHER CONSIDERATIONS
One of the more overlooked problems in designing ultra-low-drift
dc amplifiers is thermocouple induced offset. In a circuit comprised
of two dissimilar conductors (Le., copper, kovar), a voltage
known as the "Seebeck" or thermocouple emf is generated
when the two junctions are at different temperatures. Standard
IC lead material (kovar) and copper form a thermocouple with a
high thermoelectric potential (about 3SIJoVfC). This means that
care must be taken to insure that all connections in the input
circuit of the AD368/AD369 remain isothermal. In addition, the
user should also avoid air currents over the circuitry since slowly
fluctuating thermocouple voltages will appear as "flicker" noise.
.The base emitter junction of an input transistor can rectify outof-band signals (Le., RF interference). These rectified voltages
act as small dc offset errors. In the case of a resistive transducer,
a small capacitor (e.g. ISOpF) across the input working against
the internal resistance of the transducer may suffice to provide
an RC filter without affecting system bandwidth. Again, every
effort should be made to match the capacitance at Pins 1 and 2,
to preserve CMR.
l8-Bit Floating Point
Data Acquisition System
AD1330 I
r.ANALOG
WDEVICES
FEATURES
18-Bit Dynamic Range
12-Bit Significand
6-Bit Normalization
100 kHz Conversion Rate
Sample-and-Hold Included
Status Word
AD1330 FUNCTIONAL BLOCK DIAGRAM
ANALOG
INPUT
APPLICATIONS
Sonar Signal Processing
Vibration Analysis
PC Data Acquisition
Medical Instrumentation
General Purpose DSP
PRODUCT DESCRIPTION
The AD1330 is an I8-bit Floating Point Data Acquisition System. The device will digitize signals up to 50 kHz, at conversion
rates up to 100 kHz. The output word format consists of an 18bit word expressed as a I2-bit 2s complement significand and a
6-bit normalization term. The device offers I2-bits of resolution
and I8-bits of dynamic range.
The AD 1330 incorporates all of the nec
acquire, hold and digitize the .
representation. A complete AD
a 32-pin and the other a 48-pin
"front end" or Analog Input Section (
package contains the "back-end" or Co
Section (CCS).
The analog input section consists of: differential amplifi
sample-and-hold and programmable gain amplifier. The
erential amplifier and sample-and-hold have been optimized for
low noise, low harmonic distortion and wide dynamic range.
The differential amplifier provides optional ground sensing.
Ground sensing is enabled by connecting the sense input to analog ground at the signal source. In addition, the user may select
whether to bypass the differential amplifier since the input and
output connections are made available at the package pins.
Operation of the sample-and-hold is via the SHAIH-L and
SHA I S-L signals which are internally generated by the control
logic. The SHA is compensated for droop, distortion and feedthrough. The PGA incorporates an auto-zero loop to remove de
offsets. The auto-zero loop is enabled by connecting the autozero out to PGA in. All control signals to the PGA-AUTOZ-L,
SHORT-L and GAIN-L through GAIN64-L are generated by
the control logic.
The CCS contains a 7-bit flash ADC, a second SHA, I2-bit
ADC, control logic and bus interface logic. The flash ADC generates the first conversion product (normalization constant)
t the gain of the PGA. The SHA is
which in tum is
g input and to hold it for conversion
tion 12-bit ADC. The congrollogic
e required timing and control signals to the
s interface circuitry (BI) provides a high
-bit data bus. The AD1330 generates an
y be used to iuitiate a read cycle.
put data clears the interrupt; otherwise the intermatically cleared and output data is updated after
nds.
ersion cycle there are three output words available
the AD1330. The first two contain the ADC and normalization outputs; the third contains the status world. A complete
result is obtained by multiplying (or scaling) the ADC result by
the normalization constant.
The AD1330 has four operating modes: auto gain, fixed gain,
forced gain and autocalibrate . .In auto gain mode the PGA gain
is set during each conversion cycle according to the result from
the flash ADC. This process maximizes the amplitude of the
signal presented to the 12-bit ADC thereby optimizing the resolution and accuracy of the conversion process. The fixed gain
mode holds the last gain setting and inhibits any further updates
to the PGA. The forced gain mode allows the user to set a specific gain via the data bus. In autocalibrate, the AD1330 corrects
for any offset voltages in the second SHA and 12-bit ADC.
Mode selection should be made immediately after reading the
previous result. Changing modes before readback may overwrite
the output data and is not recommended. Autocalibrate takes 10
microseconds, and one such cycle is initiated on powerup and at
any time RST-L is asserted.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DATA ACQUISITION SUBSYSTEMS 9-29
I
9-30 DA TA ACQUISITION SUBSYSTEMS
1IIIIIIII ANALOG
WDEVICES
Complete 12-Bit Sampling AID Converter
for Digital Signal Processing
AD1332 I
FEATURES
Complete AID System for DSP Includes:
4th Order Antialiasing Filter
12-Bit Sampling AID Converter
32-Word FIFO Memory
Fully Asynchronous, High Speed Digital Interface
Sample Rate up to 125kHz
Entire System is Dynamically Specified
15ns Data Access Time Allows "No Wait State"
Interface to: ADSP-2100 (AI, TMS320C25
DSP56000, NEC....PD77230
AD1332 FUNCTIONAL BWCK DIAGRAM
FILTER
SELECT
-5Vdc
REF OUT
FILTER IN
FILTER OUT
Do-D11
SlH IN
AO
os
RST
APPLICATIONS
Sonar Signal Processing
Vibration Analysis
Ultrasound Imaging
PC Data Acquisition
High Speed Modems
Motion Control
Speech Processing
PRODUCT DESCRIPTION
The AD 1332 is a complete, 12-bit AID converter system optimized
for use in high speed digital signal processing (DSP) applications.
The device consists of a fourth order antialiasing filter, a 12-bit
sampling AID, a fully asynchronous high speed digital interface
and a 32-word FIFO memory. The AD1332 is manufactured
using highly reliable advanced hybrid circuit assembly techniques
and is packaged in a 4O-pin hermetic DIP.
The antialiasing filter is an active four-pole Butterworth. Cut-off
frequencies (fel are user-selectable (capacitor programmable),
and operation is specified for fc up to 50kHz. The filter may be
bypassed entirely if desired.
AD
WR
SAMPlE SAMPLE elK IN
IN
OUT
PTe
ENB
The digital interface provides a true asynchronous link between
the AID and a high speed microprocessor. Data transfer is controlled by generating an interrupt signal when data is available.
Interrupts can be generated when the FIFO is full (32 words),
half-full (16 words), or when a single word of data is ready
(FIFO bypassed). In addition, the AD1332 can generate an
interrupt signal when the AID conversion results are overrange.
The AD1332 provides a completely specified and tested system
that bridges the interface and specification gap between AID
converters and high speed DSP.
The 12-bit sampling AID converter can convert ± 5V full-scale
signals at sample rates up to 125kHz. The rate is programmable
by means of a single external clock. The entire converter system
is specified and tested for signal-to-noise ratio and total harmonic
distortion.
DA TA ACQUISITION SUBSYSTEMS 9-31
I
SPECIFICATIONS
(TA= +2SOC, Vs= ±15V, Vou= +5V, unless otherwise noted)
Parameter
FILTERCCI-C4=500pF ± 1%)
Input Impedance
Voltage Range
Output Voltage Range R L ",,4k
Comer Frequency, Accuracy
Drift
Gain1@dc
0.8fc
fe
4fe
IOfc
SettlingTimetoO.Ol%,lOVStep
Offset
Drift
Noise
SAMPLING AID CONVERTER2
Input Impedance
Voltage Range
Output Coding
CLK IN Frequency
High Time
Low Time
Sampling Rate Cf8 )
SIH
Acquisition Time
Droop Rate
Over Temperature
Aperture Delay Time
Static Characteristics
Integral Nonlinearity
Over Temperature
Resolution for No Missing Codes
Over Temperature
- Full-Scale Error
Over Temperature
+ Full-Scale Error
Over Temperature
PSRR, ±Vs
Dynamic Characteristics !,3
With Filter Cfe = 50kHz)
Signal-to-Noise Ratio,
fIN = 38.7kHz
Total Harmonic Distortion, fIN = 38.7kHz
Intermodulation Distortion, fIN! = 32.8kHz
&fIN2 =34.3kHz
Without Filter
Signal-ta-Noise Ratio,
fIN = 6O.9kHz
Total Harmonic Distortion, fIN = 60.9kHz
Intermodulation Distortion, fIN! = 58. 7kHz
& fIN2= 6O.9kHz
Reference Voltage
Output Current
Drift
9-32 DA TA ACQUISITION SUBSYSTEMS
AD1332BD
Typ
Max
Min
kO
V
V
%
10
8
±10
±10
±2
±0.01
-0.05
-1
4
%rC
+0.05
+1
-3
-48
-76
100
±2
±20
75
-45
125
:1:5
±100
2.5
125
2.8
0.5
1.0
Doubles Every 10°C
35
70
MHz
ns
ns
kHz
f.Ls
mV/ms
ns
:1:1
±l
±1
±2
±1
±2
±2
:1:2
±8
:1:2
±8
±6
LSB
LSB
Bits
Bits
LSB
LSB
LSB
LSB
LSB
72
-82
-72
dB
dB
-82
-72
dB
72
-78
-68
dB
dB
-78
-5.05
±1
dB
dB
dB
dB
f.Ls
mV
f.LVrC
f.LVrms
± 112
12
12
70
dB
kO
V
5
-5to +5
Offset Binary
0.5
200
200
Units
-68
-4.95
±2
±5
dB
V
rnA
±25
ppml"C
AD1332
AD1332BD
Parameter
DIGITAL INPUTS 1
RO, WR, CS, RST,AO,
OO-Dll,PTCENB
Input Voltage, Logic Low
Input Voltage, Logic High
Input Current
SAMPLE IN, CLK IN
Input Voltage, Logic Low
Input Voltage, Logic High
Input Current
Input Capacitance
RST LOW Pulse Width
DIGITAL OUTPUTS 1
DO-Oil, SAMPLE OUT
Output Voltage, Logic Low, IOL = 4rnA
Output Voltage, Logic High
DO-Dll,IoH = -4rnA
SAMPLE OUT, IoH = -0.4rnA
High Impedance Leakage Current
IRQ, PTC ENB
Output Voltage, Logic Low IOL = 4mA
Off-State Leakage
Output Capacitance
IRQ LOW to DO-Dl I Valid4
POWER REQUIREMENTS
Operating Range
:tVs
Voo
+ V s Supply Current
- Vs Supply Current
+ VooSupplyCurrent
Consumption
±Vs = ±12V
:tVs=±ISV
TEMPERATURE RANGE
Operating and Specified
Storage
Min
Typ
Max
Units
+0.8
V
V
f.LA
+2.0
:t200
+1.5
:tID
V
V
f.LA
pF
ns
+0.4
V
+3.5
5
10
V
+2.4
+4.0
:tID
f.LA
+0.4
:tl0
,...A
0
pF
ns
V
5
± 15.75
+5.25
47
46
2
65
5
V
V
rnA
rnA
rnA
1.2
1.5
1.4
1.75
W
W
-40
+85
-65
+ 150
°C
°C
±11.4
+4.75
66
NOTES
IGuaranteed over operating temperarure range, tested at + 250(: only':""'feLK = 2.5MH., SAMPLE IN connected to SAMPLE OUT, PTe ENB = Low.
'THD of harmonics 2·7 of the fundamental. SNR of fundamental less hannonics 2·7.
'RD,(;S,AO= "Low;"WR, RST= "High."
Specifications subject to cbange without notice.
Specifications in boldface are tested on all production units.
All other specifications are guaranteed but not tested.
DATA ACQUISITION SUBSYSTEMS 9-33
I
(over operating temperature and power supply voltage range,
SWITCHING CHARACTERISTICS withC
our =30pF or lDDpF except where noted)
Max
Parameter
Description
Conditions
Min
READ CYCLE
tRC
Read Cycle Time
COUT = 30pF
COUT =100pF
25
35
tA
Data Access Time
COUT = 30pF
CoUT = l00pF
COUT = 150pF
tLZ
Output Low Z Time
tHZ
Output High Z Time
toH
Output Hold Time
2
ns
tAORO
AOValid to RD LOW
3
ns
tRoAO
RD HIGH to AO Invalid
3
ns
tAOCS
AO Valid to CS LOW
3
ns
tcSAO
CS HIGH to AO Invalid
3
ns
Write Cycle Time
15
ns
Write Pulse Width
5
ns
tsu
Data Setup Time
2
ns
tlH
Input Hold Time
3
ns
tAOWR
AO Valid to WR LOW
3
ns
tWRAO
WR HIGH to AO Invalid
3
ns
tAOCS
AO Valid to CS LOW
3
ns
tcSAO
CS HIGH to AO Invalid
3
ns
WRITE CYCLE
twc
twp
Units
ns
ns
15
25
30
2
ns
ns
ns
ns
15
25
COUT = 30pF
COUT = l00pF
ns
ns
NOTE
Specifications subject to change without notice.
Specifications are guaranteed. but not tested.
ABSOLUTE MAXIMUMRATINGS·
+17V
+ VS to APWRIASIG GND .
-17V
-Vs to APWRIASIG GND ..
. +7V
Vooto DGND . . . . . . . .
-0.3V to +0.3V
APWRIASIG GND to DGND
Analog Input to APWRIASIG GND
S/H IN, FILTER IN, Clvg-C4vg
-VS to +Vs
Digital Input to APWR GND
-0.3V to +7V
SAMPLE IN, CLK IN . . . . .
Digital Input to DGND
DO-DIl,RD, WR,CS,AO,RST,
PTC ENB . . . . . . . . . . . . . -0.3V to Voo+0.3V
Output Short Circuit Duration
FILTER OUT, REF OUT or Clwv-C4wv . . .. Indeftuite
Digital Output . . . .
1 Output for lsec
Lead Temperature Range,
. . . .. + 300°C
Soldering for IOsec
NOTES
·Slresses above Ihose lisled under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
funclional operation of the device al these or any other conditions above
Ihose indicaled in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affeel device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
ORDERING GUIDE
Model
Temperature
Range
AD1332BD
- 40°C to + 85°C
AD1332TD/883B - 55°C to + 125°C
·See Section 14 for package outline information.
9-34 DATA ACQUISITION SUBSYSTEMS
Package
Option·
DH-40A
DH-40A
WARNING!
0
~~DEVICE
AD1332
AO
~-A""D--:-----
14------twc------~
AO
rrrrT"7"":...-r";'"7
DOUT ------+~
DIN
~TES
__
CS IS VALID BEFORE OR COINCIDENT WITH RD HIGH-TO-lOW TRANSITION.
CS IS INVALID AFTER OR COINCIDENT WITH lID lOW-TO-HIGH TRANSITION.
WR IS NOT ACTIVE DURING READ CYCLE.
Figure la_ Timing Waveform for Read Cycle No_l (RO
Controlled)
AO~-Ao-es~--t~----~
NOTES
CS IS VALID BEFORE OR COINCIDENT WITH WR HIGH-TO-lOWTRANSITION.
~IS INVALID AFTER OR COINCIDENT WITH WR lOW-TO-HIGH TRANSITION.
RD IS NOT ACTIVE DURING WRITE CYCLE.
Figure 2a. Timing Waveform for Write Cycle No. 1 (WR
Controlled)
! . - - - - - - twe ------~
AO
I /,,?"77"77"7777
DOUT ------+-i~X)0(
DIN
~TES
__
!l!2IS VALID BEFORE OR COINCIDENT WITH c;§..HIGH-TO-lOW TRANSITION.
RD IS INVALID AFTER OR COINCIDENT WITH CS lOW-TO-HIGH TRANSITION.
WR IS NOT ACTIVE· DURING READ CYCLE.
Figure lb_ Timing Waveform for Read Cycle No.2 (CS
Controlled)
!l!QTES
__
WR IS VALID BEFORE OR COINCIOENTWITH c;§..HIGH-TO-lOW TRANSITION.
WR IS INVALID AFTER OR COINCIDENT WITH CS lOW-TO-HIGH TRANSITION.
lID IS NOT ACTIVE DURING WRITE CYCLE.
Figure 2b_ Timing Waveform for Write Cycle No.2 (CS
Controlled)
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Timing Reference Levels
Inputs
Outputs
LOW
HIGH
Enabled to LOW
Enabled to HIGH
Disabled from LOW
Disabled from HIGH
VT
= I.SV,
DGND to + 3.0V
<5ns
1.5V
OAV
2AV
VT -O.IV
VT +O_IV
VOL +O.5V
VOH -O.5V
+1.5V
Figure 3_ Output Load
the voltage to which 3-stated outputs are forced.
OA TA ACQUISITION SUBSYSTEMS 9-35
11
Typical Characteristics
+ .•
'D
+.•
!II,
+.•
~
+.,
f-"
!i •
I=~
V
-,N
'--
E5.0
,
~
-20
/1--
~ +.2
1\
f c =20kHz
~ 1.0
----.....:;
-80
-.5
.3
'.,lie
.4
.5
~
_.....1\
~
-
fc=ZOkHz...,
'c=SOkHZt1
-.'
.2
t\
'c=10kHz-
.....J
'c = 50kHz
.,
:-....
~
THE~:=...JjVX
.. -.3
'\.
~ 2.0
-'00
.6 .1 .8 .91.0
Figure 4. Filter Passband Response
Normalized to the Cutoff Frequency
/""
..........
~
.5
'\.
L
:-....
.,
'D
30
20
40
'D
50 60 10 80 90 100
f.Nl'fc
so
2D
Ie - kHz
Figure 5. Filter Stopband Response
Normalized to the Cutoff Frequency
Figure 6. Filter Settling Time to 0.01%
vs. Cutoff Frequency
80
-,.
7D
f s=125kHz
-2D
60
's=125kHz
..
..i
..,
.. -4D
'4D
~
-80
-7D
2.
,.
-80
D
20
'D
30
'IN- kHz
4D
50
6D
-'00 D
Figure 7. AID SNR vs. Frequency
SNR""72.12d8
~
-30
~
-so
.~
.~
-80
-4D
-6D
-70
-9D
'D
20
4D
3D
'IN-kHz
-110
.D
so
FRACTKlN OF SAMPLING FREQUENCY '.
Figure 8. AID THD vs. Frequency
,.•
Figure 9. Filter & AID Spectral
Response
,s
'.3
T A =25"C
'.2
,. ,~
,.,
~
"
~
!!
D••
D••
D.7
'.D
i
"-
D.•
'.5
,/
/
V
V
V
/
'D
,/
5.D
5.2&
5.5
/"
/"
Voo-V
Figure 10. Normalized Data Access
Time vs. VDD
9-36 DA TA ACQUISITION SUBSYSTEMS
+2&
TEMPERATURE - "C
D
+70 +85
Figure ". Normalized Data Access
Time vs. Temperature
V
/'
VDO=5.OV
./
D
-4D
/"
/
D.7
4.75
I-T.=~
Voo=5.OV
f--
1.2
"~
THO = - 81.06dB
~ -100
-'D
D
's=1ZSkHz
flN =38.696kHz
i..
Q-60
.D
-'D
-20
~
-.D
so
!f!,
/'
D
2&
50
75
'00
'26
CAPACITANCE - pf
Figure 12. Change in Data Access
Time vs. Loading
'so
AD1332
PIN CONFIGURATION
C3wv
C2wv
01
400
C2 vG
02
390
elvG
C1 vG
03
380
C4vG
C4wv
Clwv
04
370
FILTER IN
05
360
FILTER OUT
+V.
06
350
S/HIN
REF OUT
07
ASIGGNO
08
APWRGNO
09
AD1332
TOP VIEW
340
-Vs
330
SAMPLE IN
(Not to
320
SAMPLE OUT
Scalel
310
CLKIN
PTC ENB
010
IRQ
011
300
RST
CS
012
290
WR
iffi
AO
013
280
(MSBIOII
014
270
OO(LSBI
010
015
260
01
09
016
250
02
08
017
240
03
07
018
230
D4
06
019
220
05
OGNO
020
210
VDD
PIN DESCRIPTIONS
Pin
Mnemonic
Function
3,4
2,1
39,40
38,37
Clvg,Clwv
C2vg,C2wv
C3vg,C3wv
C4vg,C4wv
Pins where 4 equal value capacitors are added to set filter corner.
Frequency fc according to:
5
36
35
8
7
FILTER IN
FILTER OUT
.S/HIN
ASIGGND
REF OUT
fc
=25kHz -+- C,CinnF
I
Filter input.
Filter output.
Sample and hold analog input.
Analog signal ground.
- SV reference output.
6,34
9
+V s , -Vs
APWRGND
31
CLKIN
External clock input to the AID converter and the Periodic Timing Circuit.
32
33
SAMPLE OUT
SAMPLE IN
Periodic Timing Circuit output. Connection to SAMPLE IN sets sample rate at fCLK -+- 20.
SIH and AID converter control input.
Analog power supplies.
Analog power ground.
10
PTCENB
Input and (open-drain) output used to enable periodic timing externally or through floP interface.
11
IRQ
12
13
CS
AO
Open drain interrupt request. User programmable to become active on any of the following
conditions:
One AID conversion result available;
FIFO half full or full;
AID conversion results overrange.
Chip select inpu~.
Address bit zero. Selects data path from FIFOllatch (low) or fromlto Status/Control
register (high).
27-22
19-14
DO-D5
O6-D11
Bidirectional3-state data lines. D 11 is AID converter MSB when DO-Dll are outputs.
D7 is Status/Control register MSB.
28
29
RD
WR
Read control input (DO-Dll).
Write control input (OO-D7).
30
RST
Reset. In reset state, FIFO is transparent & overrange detector is disabled.
20,21
DGND,VDD
Digital power supply.
DA TA ACQUISITION SUBSYSTEMS 9-37
COMPONENT LIST
Ul: AD1332
U2: CONNER·WINFIELD
HCI6R5-2MHz
Cl-C4: 1000pF ±5%
•
C5-C1: 2.2p.F TANTALUM
C8-Cl0: O.I ....F CERAMIC
Rl. R2: 2kfl
~~~--~------------~
+15V -..-::c:--p----[]O
~r_-_;:::::!::=~-
-15V
+5V
AD1332
(Ull
~4-~~~--~----;111
~}-----------~~ RST
~--~------------;1~
~r_-------- WR
I----------iiii
AO--~------------;
011
+----------------[1!J
~r_-----~+OO
~J_-------------.
~-~------------~~
05
21
Cl0
~~~~ --+-----------.....---------i I-c::'I:c-_____......_________o-_ +5V
Figure 13. Typical Interface Circuit (fc =25kHz, fs= 100kHz)
CONTROL AND STATUS REGISTER DESCRIPTIONS
Control
Bit--- 7
6
5
I PTCENI LIF ! HF/F
Bit
7
6
5
4
ORNG
3
X
2
X
1
X
o
Xl
Status
Bit.... 7
6
5
Mnemonic Function
Bit
Mnemonic Function
PTCEN
7
6
FLAG
DATA
5
ORUN
4
ORNG
3-0
X
[IF
HF/F
4
ORNG
3-0
X
A "0" in this bit position will disable the
periodic timing circuit.
A "I" in this bit position will enable the
periodic timing circuit.
A "0" in this bit position will reset the FIFO
and enable the transparent latch. IRQ will
become active on the completion of an AID
conversion cycle. IRQ will become inactive on
the start of the next AID conversion cycle.
A" I " in this bit position will enable the FIFO
and activate IRQ when the FIFO is half full or
full (depending on CBIT 5). IRQ will become
inactive on the start of the next AID conversion
cycle or when the FIFO is read from.
A "0" in this bit position will cause IRQ to
become active when the 16th word is shifted
into the FIFO (if the FIFO is enabled).
A" 1" in this bit position will cause IRQ to
become active when the 32nd word is shifted
into the FIFO (ifthe FIFO is enabled).
A "0" in this bit position will disable the
overrange interrupt capability.
A "1" in this bit position will activate IRQ
if overranged (all "O"s or all "1 "s) data is
shifted into the FIFO. IRQ will become
inactive when this bit is reset to "0."
Not defined.
9-38 DA TA ACQUISITION SUBSYSTEMS
4
3
2
! FLAG! DATA! ORUN!ORNG!X ! X
1
0
X
X
Logical ORofstatus Bits 4 & 6.
Set ifIRQ becomes active because data is
available. Reset when FIFO is read from if
FIFO used. Reset when IRQ becomes inactive
iflatchis used.
Set when FIFO has overrun.
Reset by control Bit 6.
Set ifIRQ became active because of overrange
condition. Reset by control Bit 4.
Not defined.
AD1332
DISCUSSION
General
The AD1332 is a complete solution for sampling and quantifying
signals in the audio bandwidth and provides a direct parallel
interface to a high speed microprocessor for digital signal
processing (DSP). A block diagram of the AD1332 is shown on
page 1.
DSP is the mathematical manipulation of dynamic signals which
have been represented in numerical form. To successfully process
a signal, the signal must be sampled and quantified such that
accuracy is preserved and aliasing is avoided. The AD1332
provides this capability by enabling the user to coorpinate its
antialiasing filter cutoff frequency with the converter sample
rate, completely independent from the DSP processor speed.
Sampled Data Systems
The process of sampling a continuous-time signal x(t) at a sample
rate fs causes a periodic replication in the frequency domain of
the continuous time Fourier transform (CTFT) x(f) of the original
signal about integer multiples of fs . If the sample rate is selected
too low for the bandwidth of x(t), the replicated transforms will
overlap with adjacent transforms as illustrated in Figure 14b.
This overlap is known as frequency aliasing and will cause distortion if the samples are used in an attempt to reconstruct the
original time signal.
be reduced by attenuating interferences outside of the frequency
bandwidth of interest as illustrated in Figure 14c. Similarly, for
a fixed amount of attenuation outside of the frequency bandwidth
of interest, the amount of aliasing that occurs can be reduced by
increasing the sampling rate as illustrated in Figure 14d.
The amount of aliasing that is acceptable in a given application
should be less than the minimum detectable signal, which is set
by the AID converter signal-to-noise ratio. The amount of aliasing
that will occur is a function of the
(I)
(2)
(3)
(4)
frequency bandwidth of interest
strength of interferences outside of (I)
filter order and
sample rate.
The user must select (3) and (4) given a converter with a particular
SNR to correctly sample a signal in (I) given (2).
Quantization Effects
For an ideal AID converter, the noise floor is determined by the
quantization level used in the digitization process. The signal-tonoise ratio (SNR) for an AID converter is the ratio of the rms
magnitude of the fundamental frequency to the rms sum of all
nonbarmonically related signals up to half the sampling frequency.
SNR is therefore a figure of merit associated· with a converter
that defines the minimum detectable signal. The theoretical
limit on SNR due to quantization noise is
SNR max (dB) = 6.02N + 1.76
where N is the number of bits in the converter. For a 12-bit
converter such as the AD1332, the maximum SNR is 74dB.
o
Figure 14a. Original Continuous-Time Fourier Transform
(CTFT) or x(t)
-fs
- 2fs
-fs
0
fs
2'
2fs
fs
2'
Figure 14b. Sampling Produces Aliased Replications of
x(f)
ANTIALIASING FILTER
Features Description
The antialiasing filter in the AD 1332 is an active 4th order
Butterworth approximation of a low pass filter. A key feature of
the Butterworth approximation is a maximally flat magnitude
response. For Butterworth filters, attenuation at the cutoff frequency fc is 3dB and "rolloff' after fc is 20dB per decade, per
pole. Actual AD 1332 filter frequency responses for 25kHz and
50kHz cutoff frequencies are shown in Figures ISa and ISb.
It can be shown that an LC ladder fIlter designed for maximum
power transfer from the source exhibits extremely low sensitivity
to component variations. This property of the LC filter is exploited
\00,&,001
-zts
-fs
-fs
fs
0
2'
fs
2fs
2'
Figure 14c. Replications of x(f) when x(t) is Band Limited
I
,,61~,6/
slll
_~
_~
2'
0
~
~
2'
Figure 14d. Replications of x(f) when x(t) is Over
Sampled
Aliasing can be avoided by limiting the bandwidth of x(t) to a
maximum frequency Fo with an antialiasing filter and sampling
at fs > 2Fo, which is known as the Nyquist criteria. In practice,
for a fixed sample rate, the amount of aliasing that occurs can
Figure 15a. Fifter Response, fc =25kHz & 50kHz
(C1-C4= 1000pF & C1-C4=500pF)
DATA ACQUISITION SUBSYSTEMS 9-39
11
factor capacitors such as monolithic ceramic, metallized polycarbonate or polystyrene should be used. If polystyrene capacitors
are used, the lead connected to the outer foil should be connected
to the AD1332 Cwv (working voltage) pins. If the filter is not
used; Clvg (Pin 3), C2vg (Pin 2), C3vg (Pin 39) and C4vg (Pin
38) should all be tied to ASIG GND (pin 8).
Figure 15b. Filter Passband Response, fc =25kHz & 50kHz
(C1-C4= 7000pF @ C1-C4=500pF)
in the design of the AD 1332 antialiasing filter, which is an RCactive simulation of an LC "prototype." The active components
consist of low noise, high-speed operational amplifiers which
enable the AD 1332 filter to maintain extremely low distortion
and consistent response characteristics for cutoff frequencies up
to 50kHz. The passive components are precisely trimmed thin-film
resistors and external capacitors supplied by the user.
Since the circuit configuration is extremely insensitive to component variations, tight (1%-2%) tolerance capacitors are not
required unless the cutoff frequency must be precisely controlled.
For example, Figure 16 compares the passband response when
capacitors CI-C4 are lOOOpF 1% tolerance versus the response
when one of the capacitors (C3) is 10% high (lIOOpF). Note
that no additional passband "peaking" is observable, although
the cutoff frequency has changed approximately 5% from Figure
IS's 25kHz to 23.7SkHz.
In contrast to switched capacitor filters, the AD1332 filter does
not require a clock, prefiltering nor post-filtering since it is not
a sampled data system.
SAMPLING AID CONVERTER
Features Description
The AD1332 provides a complete analog to digital converter
function that allows the user to select a sample rate up to 125kHz
while maintaining true 12-bit accuracy. As shown on page I, the
AD1332 includes an on-board sample and hold amplifier and
low drift voltage reference. The analog input voltage range is
from - SV to + SV and the digital output coding is Offset Binary
(see Table I). Twos complement coding can be obtained by
inverting the MSB (011).
Output Code
Center of Code
Voltage (V)
000 ... 000
-5.000000
011 ... III
100 ... 000
-0.002441
0.000000
111 ... 111
+4.997559
Table I. AID Conversion Relationship
Operational Description
Analog signal information is converted to a 12-bit digital word
by means of sampling the waveform and digitizing the sample
using the successive approximation conversion technique. Two
timing modes are available for sampling and converting the
analog input.
Periodic Timing Mode
The periodic timing mode samples the input signal at equally
spaced time intervals at a rate that is proportional to the input
clock frequency. The connections required for the periodic
timing mode for sample rates between 25kHz and 125kHz are
shown in Figure 17. In this mode, the clock input is divided
down internally to generate the SAMPLE OUT signal which is
connected to the SAMPLE IN pin. The periodic timing circuit
allots 7 clock periods to sample and hold acquisition and 13
clock periods to AID conversion. The sample rate is therefore:
fs = feLK
-i-
20
which is 125kHz for a 2.SMHz clock. The timing diagram for
this mode is shown in Figure 18.
felK
's
ClKIN
SAMPLE OUT
('cLK1201
SAMPLE IN
Figure 76. Filter Passband Response, fc =25kHz
(C1-C4= 1000pF & C7, C2, C4= 7000pF, C3= 1100pF)
AD1332
PTe ENB
Operational Description
Four equal value capacitors are used to select the cutoff frequency
fc according to the equation:
fc = 25kHz
-i-
C
where C is the capacitor value in nF. Good quality, low dissipation
9-40 DA TA ACQUISITION SUBSYSTEMS
Figure 17. Periodic Timing Mode Connections
AD1332
J--15-16CP -r-7 CP-et---13 CP --T-7 CP-T"-13 CP
SAMPLE
OUTIIN
"
~
__ __
~.
"
f
-A~.~-~
RESET
PHASE
ACQUIRE
SAMPLE 1
__
"
~.~
__
CONVERT
SAMPLE 1
L......-J
A-~.~-~
ACQUIRE
SAMPLE 2
--to- 7CP"1
"
__ __
~.~
~'-____
~
CONVERT
SAMPLE 2
ACQUIRE
SAMPLE 3
Figure 18a. Timing Diagram for Periodic Timing Mode (PTC ENB=O)
~~ ~'~I--+'t~---1I~I---~'~I---~"~---4'~
.ruuuuuuuuuuu~ 15-16CP-+-7 CP-+---13 CP --+-7CP-+---13CP--!--7CP-ej
s~~:k~
____-fl~,..r-~,....r--~
~'~·---r.--~-~.~A---~.--_~
RESET
ACQUIRE
CONVERT
ACQUIRE
CONVERT
ACQUIRE
SAMPLE 1
SAMPLE 2
SAMPLE 2
SAMPLE 3
PHASE
SAMPLE 1
Figure 18b. Timing Diagram for Periodic Timing Mode (RST= 1)
PTC ENB functions as an "on/off' switch for the periodic
timing circuit and is both an input and an open drain output.
The periodic timing circuit can therefore be activated either
through the microprocessor interface (via Control Register Bit 7)
or externally by an open drain driver (such as the 74HC03).
The circuit can also be permanently enabled by grounding
PTC ENB.
As shown in Figure 19, slowing the clock down below IMHz
will result in degraded performance at high temperatures when
the sampled input "droops" during the AID conversion. Figure
20 shows the modifications required to the circuit shown in
Figure 17 to maintain 12-bit linearity over temperature. This
circuit simply divides the SAMPLE OUT signal by an appropriate
power of two to sample at the correct rate while maintaining a
500kHz to 2.5MHz AID converter clock.
•
+5V
LD
ENP
ENT
HC161
PO
QO
Ql
PI
2.5M
J:
I
P3
1M
>
<.J
Z
w
500k 1 - - - - -
- -
-
-
-
::l
--
0
w
..:
LL
'"
9
<.J
AD1332
P2
N
/
100k
<.J
10k
-40
o
+25
/
I
PTC ENB
Jumper
JO
Jl
J2
J3
J4
+70
+85
fCLlclfs
fs Ringe wI
500kHz .;;;fcuc >E;2.SMHz
20
40
80
160
320
25.00kHz- 125.00kHz
62.500
12.50
6.25
31.250
15.625
3.125
7.8125
1.5625
Figure 20. Periodic Timing Mode Connections when
500kHzsfcLKs2.5MHz
TEMPERATURE _OC
Figure 19. Range of Clock Frequencies vs. Temperature
for 12-Bit Linearity
It is important to note that since the clock is used to define the
amount oftime between samples that it should be crystal controlled
since instability in the clock circuit will appear as additional
timing uncertainty ("jitter") in the sample and hold, which will
result in degraded SNR.
DATA ACQUISITION SUBSYSTEMS 9-41
Externally Triggered Mode
If the periodic timing circuit is not used, conversions can be
triggered externally by connecting the AD 1332 as shown in
Figure 21. The timing diagram for this mode is shown in Figure
22. The duty cycle for the CONVERT START command must
allow a minimum of 2.8fLS for sample and hold acquisition.
Note that if the CONVERT START command is not synchronized
to the clock input, up to IS clock periods will be required to
complete the conversion cycle so the maximum sampling rate in
this mode will be 110kHz when a 2.5MHz clock is used.
ClKIN
---0(.:
Figures 26 - 31 illustrate how the AD1332 interfaces to a number
of popular single-chip digital signal processors.
NC
CONVERTSTART ----tOo{.
SAMPLE IN
AD1332
NC
PTC ENB
Figure 21. Externally Triggered Mode Connections
elKIN
CONVERT
r-- 2;:I~s -~'t"~===-~13~.'~5C~P~==::;·~1
11111
IIIIL--
START - - ,
~
__ __-J'
~,
.~
Data Transfer
The data lines DO-Dll are bidirectional 110 that are TTL compatible and have 4mA drive capability. The data lines are used
to transfer control information into, and AID conversion results
with status information out of, the AD1332. Address line AO is
an input that is used to select as the data path either AID conversion
results (AO = 0) or the Control/Status Registers (AO = 1) and
would typically be the least significant address bit in the system
if the AD1332 is "mapped" to adjacent memory locations. ChipSelect (CS) is used to defme a unique location in memory for
the AD1332 and should be formed by decoding the upper address
bits. Read (RD) and Write (WR) define the type of data
transfer.
____
~.~
____
ACQUIRE
CONVERT
SAMPLE
SAMPLE
~
Figure 22. Timing Diagram for Externally Triggered Mode
Since the clock does not define the amount of time between
samples, it need not be crystal controlled.
HIGH-SPEED DIGITAL INTERFACE
Features Description
The AD1332 completes the solution for AID conversion in DSP
applications by providing the systems designer a direct, high
speed parallel digital interface. The prime feature of this interface
architecture is that it operates completely asynchronously from
the AID converter and therefore allows the AD1332 to appear as
"memory" to a microprocessor.
The combination of fully asynchronous operation with respect
to the AID conversion process and fast data access time allows
the AD 1332 user to upgrade to faster versions, or even different
vendors, of DSP hardware without having to add synchronization
or wait state logic. In addition, by virtue of hybrid circuit technology, the user is not required to add external circuitry to
prevent digital feed through into the analog section.
The AD1332 data transfer is accomplished by employing an
interrupt driven architecture. Interrupts can be programmed by
the microprocessor to be generated when the FIFO is full (32
conversion results), half-full (16 conversion results) or after
every conversion (FIFO is bypassed). The AD 1332 digital interface
also includes an overrange detect circuit, which can generate an
interrupt if the sampled analog input signal exceeds positive or
negative full scale, to alert the system that a conversion result
has been generated that will result in a nonlinearity in the subsequent signal processing.
Operational Description
The AD 1332 can interface directly to a microprocessor via standard
data (DO-Dll), address (AO) and control lines (RD, WR, CS,
IRQ and RST).
9-42 DA TA ACQUISITION SUBSYSTEMS
Interrupts
Interrupt Request (IRQ) is an open drain output that can be
used to interrupt the processor on any of the conditions programmed in the control register. The processor should be programmed to interrupt on the falling edge of its Interrupt Request
input.
FIFO Half-Full Interrupt
The timing for interrupts that are generated when the FIFO is
half full is shown in Figures 23a and 23b. In both figures, IRQ
becomes active when the 16th AID conversion result is shifted
into the FIFO. In Figure 23a, the processor responds immediately
and a read cycle takes place before the next conversion cycle
begins. Here, the completion of the read cycle shifts the first
conversion result (which was just read by the processor) out of
the FIFO, replaces it with the second conversion result and
causes IRQ to become inactive since there are now 15 conversion
results in the FIFO.
In Figure 23b, the processor does not respond before the next
conversion cycle begins and IRQ becomes inactive. The FIFO
continues to accept conversion results and the processor can
read from the FIFO at any time so long as the FIFO has not
overrun.
This mode allows the AD1332 to have a low interrupting priority
since the processor has 340 AID converter clock periods (17
conversions x 20 clock periods per conversion) in the periodic
timing mode before the FIFO overruns. Therefore, the processor
will have up to 13611-s to respond at the maximum sample rate
of 125kHz (since feLK = 2.5MHz).
FIFO Full Interrupt
The timing for interrupts that are generated when the FIFO is
full is shown in Figures 24a and 24b. In both figures, IRQ
becomes active when the 32nd ND conversion result is shifted
into the FIFO. In Figure 24a, the processor responds immediately
and a read cycle takes place before the next conversion cycle
begins. Here, the completion of the read cycle shifts the first
conversion result (which was just read by the processor) out of
the FIFO, replaces it with the second conversion result and
causes IRQ to become inactive because there are now 31 conversion
results in the FIFO.
In Figure 24b, the processor does not respond before the next
conversion cycle begins and IRQ becomes inactive. The processor
must read from the FIFO before the completion of the current
conversion cycle or the FIFO will overrun.
This mode maximizes the memory capability of the AD1332 but
requires a fairly high interrupting priority in the processor since
the processor has only 20 ND converter clock periods (1 conversion
AD1332
16TH CONVERSION RESULT
SHIFTED IN
ClKIN
-I
r-
1CP
'
11111 11111111111111111111111111111 111111111111111111
11111
SAMPLE IN
--~~i
ICS :: O. AO ~l
-I
____~rr---------------------------
\0-0.5-1.5 CP
-------...,U...-L.....'-.-U,.......,L""'-,..U,.......,I..;,·--.-.U..........LTI-.-,U.----.L'·......,U........u,-·-nUr-TLT• """'Ur-Tu"-'
Figure 23a. Timing Diagram for Half-Full Interrupt
(Read before 17th Conversion Started)
,
16TH CONVERSION RESULT
SHIFTED IN
-t f.-l CP
CONVERSION RESULT
SHIFTED IN
,
CLKIN
11111
SAMPLE IN
1111111"
11111
1111111"
Figure 23b. Timing Diagram for Half-Full Interrupt
(Read after 17th Conversion Started)
32ND CONVERSION RESULT
SHIFTED IN
""'I
1-1 CP ,
CLKIN
SAMPLE IN
--'I"T1l1mll
i
....j
•
II III 1111 i II III i 111111111 11111111111111111111 1111111
I
I- 0.5-1.5 CP
iffi
-"U"'-'LT,""U"'l;T,""u""""'LT,""wr-TLr-,
U"'---"'U~i.ar.--'i..:""·~U""""'LCTI""""U""""'LT.
(CS=O.AO=1)
Figure 24a. Timing Diagram for Full Interrupt
(Read before 33rd Conversion Started)
32ND CONVERSION RESULT
SHIFTED IN
""'I
,
CONVERSION RESULT
SHIFTED IN
1-1CP'
ClKIN
SAMPLE IN
11111
IRQ
--~-li__________~a~I'Zt~/~··~-:~::::~::::::::::::~:
Ri)
----'---'-----------*"1.fLj
(CS=O.AO=I)
..j
I- 0.5 _ 1.5 CP
, / READ BEFORE 33RD CONVERSION RESULT SHIFTED IN.
u
i..!
w:'
w"
'. .
"
:! ..
:
-
I
....
w"
Figure 24b. Timing Diagram for Full Interrupt
(Read after 33rd Conversion Started)
x 20 clock periods per conversion) in the periodic timing mode
before the FIFO overruns. Therefore, the processor will have
only 8,...s to respond at the maximum sample rate of 125kHz
(since feLK = 2.5MHz).
Conversion Results Overrange Interrupt
If the FIFO is used, the AD1332 can be programmed to generate
interrupts when overranged conversion results are shifted into
the FIFO. If IRQ became active as a result of an overrange
condition, the only way it can become inactive is to clear Bit 4
of the control register. Typically, the user should clear the
entire control register which will, in effect, remove the interrupt,
reset the FIFO and reset the periodic timing circuit.
Should the overrange interrupt capability be used, Status Register
Bits 4 and 6 can be used to identify whether the interrupt occurred
as a result of an overrange condition or FIFO half full (or full).
DATA ACQUISITION SUBSYSTEMS
~
ull~II~I__~I.~:'====~!I~I~Ii::~I~~~
SAMPLE IN
ACQUIRE
SAMPLE'
0.5 - '.5
--t
I--
----~--ll
IRQ
CONVERT
SAMPLE'
ACQUIRE"
SAMPLE 2
,
w
CONVERT
SAMPLE 2
__~;~P---1~·~I-------,~~
.
PREVIOUS
CONVERSION RESULTS
VAliD
SAMPLE'
CONVERSION RESULTS
VALID
Figure 25. Timing Diagram for Single Conversion Interrupt
Single Conversion Interrupt (FIFO Bypassed)
The timing for interrupts that are generated when the FIFO is
bypassed is shown in Figure 25. Here, IRQ becomes active at
the completion of a single AID conversion cycle, which may be
up to two AID converter clock periods after the sample and
hold starts acquiring the next sample. IRQ remains active,
independent of the read cycle, until the next conversion cycle
begins. Data is valid so long as IRQ remains active.
Since IRQ wi1I only be valid for six AID converter clock periods
in periodic timing mode (2.4jJ.s with a 2.5MHz clock), a high
interrupting priority should be assigned by the processor. Should
the single conversion result be necessary to adjust a system
parameter as described above, it may be more efficient to "poll"
the Status Register to determine when the conversion result is
available.
This mode makes data available immediately after the conversion
process has been completed, and is therefore very similar to the
operation of a conventional AID converter if IRQ is taken to
mean conversion STATUS. This mode is most useful when a
single conversion result is necessary to adjust a system parameter,
such as the gain of a PGA that may be in front of an AD1332.
Operation Other than with a Microprocessor
The AD1332 can be used in other microprocessor environments
by grounding Pins 12, 13 and 28 (CS, AO and RD), connecting
Pin 29 (WR) to VDD and pulsing RST low. This will permanently
enable the AD 1332 3-state outputs and clear the control register,
causing the FIFO to be bypassed.
+5V
+5V
1
1
V oo
I
I.
oMA
I
..J
OMS
ADSI>o2'OOAI
DMACK
iiiQ
.J
rf
l
~MA1J
ADDRESS
DECODE
r
oMAl
\
AO-A'S
.J !J"-A'5
I
[AD
os
VDI)
J
AD
os
DSP56000
AD'332
iiiQ
DMWR
WR
WR
oMRO
Ro
iiii
fiESEj
RST
oMo
GNo
...
I
r
RESET
011-00
oMo11_0MO."j
DGNO
~
00-023
I
I
RESET
Figure 26. ADSP-2100A to AD 1332 Interface
9-44 DA TA ACQUISITION SUBSYSTEMS
I
xiV
IRQ
,.
I
Vc<
I
Vss
...
T
ADDRESS
DECODE
y
J
[
I
I
A.
V oo
cs
AD'332
IRQ
WR
RD
I
RST
00-01' DGND
00-011"1
~
I
I
Figure 27. DSP56000 to AD 1332 Interface
I
AD1332
+5V
+5V
1
I
I
V'"
A16-AO
..J
is
TMS320C25
READV
iNT
I
+5V
~'5 A'
ADDRESS
DECODE
T
H
[
I
I
AO-A11
V••
AO
A,
"PD77230
CS
AD'332
iNT
VIii
IRQ
Lc
STIiii
liS
r-b!
WR
H-J
015- DO
MIS
RST
?
00-031
011-00 OGND
011-00'"1
t
I
ADDRESS
DECODE
'(
~
;?-
I
cs
AD'332
VIii
iffi
RST
I
:I
DO-D11
IlD-D11~
DGND
~
I
I
I
T
J
VDD
AO
IRQ
1
GND
~
I
iffi
I
V..
T
J
I
RESET
RD
I
I" A'-A11
~
I
~
RIW
I
v••
Figure 29. /-LPD77230 to AD1332 Interface
RESET
Figure 28. TMS320C25 to AD 1332 Interface
+5V
+5V
1
r
V••
PSEL
+5V
DSP'6
INT
"1-
i
.J
l
AD'332
m
RSTS
liST
I
AD-A'S
cs
PODS
PBO-PB15
~
V••
~
I
Veo
AO
VIii
iffi
PQDS
V"
~
1
l
ZR34,6'
VIii
ICLK
PBO-PB11j
J
I
DOND
iffi
iiESET
~
ADDRESS
DECODE
"V'
I
V••
LAO
'(
cs
~
VIii
,----(l
RD
AD'332
I
RST
r::mo
I
\
I
A' A'5
~"\.
DSlS
00-011
~
00-01'
DBO-D.11~
DGND
~
DBD-DB1S
V..
~
Figure 30. DSP16 to AD 1332 Interface
ET
I
L----.
I
TO CONTROLLER
Figure 31. ZR34161 to AD 1332 Interface
DA TA ACQUISITION SUBSYSTEMS 9-45
I
Multiple AD1332s
The architecture of the AD1332 allows multiple devices to be
used in a microprocessor based system. Figure 32 illustrates
how four ADB32s can be configured to simultaneously sample
their analog inputs and reside in eight sequential locations in a
microprocessor's memory address space. Since the AD1332s are
sampling at the same rate, one AD 1332 functions as the "master"
and drives its own SAMPLE IN pin as well as those of the
remaining devices ("slaves"). The Control Register of each
device should be programmed to interrupt on the same condition
so that the same number of conversion results are available from
all devices.
Since each channel is sampled on every 16th rising edge of the
SAMPLE OUT signal, the effective sampling rate is:
fs = (fcr.K + 20) + (Number of Channels)
=
{CLK
+ 320
Any number of channels can be sequentially sampled with slight
'
modifications to the circuit shown in Figure 33.
CHANNElOIN
SIHIN
DOUT
ANALOG
INO
ALl IN
[
T__
~
~
ANALOG
IN'
ANAlOG
1N2
- r-c
-
--e
DO-D11
ALTOUT
SlH IN
(MASTER)
AD1332
INl
-
'16:1 MUXI
cs~
SAMPLE IN
AO
I
CHANNEll~ IN
iRa
AD1332
SAMPLE IN
AD1332
Wo,
AO
eLKIN
SAMPLE IN
ALliN
FlLTOUT
SJHIN
csN
Figure 33. 16-Channel Sequential Sampling System
DO-D11"
-csN
loa
SUCCESSFULLY APPLYING THE AD1332
RD
RsT'
AO
elKIN
SJH IN
f- CLKIN
L...,.
ao
a,
a2
03
SAMPLE OUT
OST
DO-Dn
DO-011
10Q
00
IRQ
00'
Wii
WO
OST
O$T
AO
AO
-
A2
A::S
ENP
ENT
HC161
116
SfH IN
AD1332
eLKIN
(2015 1
EN
DO 011
FU.TOUT
elKIN
LO
G
A'
ALliN
elKIN
"CLK =20151
V
OST
AO
ALliN
f- FlLTOUT
[
ADG50SA
PTe ENS
~ SAMPLE IN
ANALOG
00
wo
elKIN
SAMPLE OUT
AD1332
r--o
+5V
IRQ
SAMPLE IN
CSN
y
A'
A2
ADDRESS
DECODE
A3·AMAX
Figure 32. 4-Channel Simultaneous Sampling System
Sequential Sampling
Figure 33 illustrates how an AD1332 can be configured to sequentially sample sixteen channels of analog inputs. The circuit
works as follows. The HCI61 outputs QO-Q3 form the address
bits for the AD7506 muliplexer. Through the microprocessor
interface, the periodic timing circuit is enabled and the HCI61
is taken out of reset by setting Control Register Bit 7. Since the
HCl61 was reset, Channel 0 is initially selected. Following an
AD1332 reset cycle (15-16 clock periods), 7 clock periods are
used to acquire the Channel 0 input. Once acquired, the rising
edge of SAMPLE OUT puts the AD1332 sample and hold into
hold mode, starts the AID conversion and advances the HCI61
one count. Therefore, while Channel 0 is being converted, the
multiplexer switches to Channel I and settles during the 13
clock periods required for AID conversion.
The above continues until Channel IS has been sampled, at
which point the HCl6l returns to an all zero count and commences
another pass through the 16 channels. The process can be terminated by clearing Control Register Bit 7.
9-46 DATA ACQUISITION SUBSYSTEMS
Grounding
In order to obtain the specified performance of the AD1332,
proper grounding and power supply decoupling techniques must
be observed. First, it is imperative that a ground plane be used.
A ground plane provides a low resistance, low inductance path
for currents to flow back to their source. Without a ground
plane, currents will return to the source in such a way as to
minimize the energy of the system and therefore parasitic inductances will exist in such undesirable locations as power supply
lines and signal grounds.
Second, all three ground connections on the AD1332 must be
tied together to the ground plane. The AD1332 APWR GND
(Pin 9) carries the imbalance current from the analog power
supplies (±Vs). APWR GND is also connected to the package
seal ringllid and therefore can cause coupling between the analog
and digital sections if it is not tied directly to the ground plane.
ASIG GND (Pin 8) is the signal ground internal to the AD1332
and is "common" for the filter, - 5V reference, sample and
hold, and AID converter. The current that flows through this
pin from the AID converter is a dynamic current that changes
on every clock cycle. Inductance in this trace will therefore
cause a reduction in performance in the entire analog section.
DGND (Pin 20) is a separate ground connection for the digital
interface chip. It carries a dynamic current every time a digital
output changes state, .and inductance in the trace that connects
to this pin will reduce the noise margin between the AID converter
and the digital interface chip.
Power Supply Deeoupling
The power supply decoupling capacitors supply the instantaneous
current to the AD1332 and also provide some high frequency
filtering. The filtering aspect of the capacitors should not be
counted on however, and the user should make every effort to
AD1332
supply quiet, well regulated power supplies to the ADB32.
Switching mode power supplies are not recommended for the
analog power supplies ± Vs.
Decoupling capacitors should be placed as close to the device as
possible to minimize inductances in power supply traces. A
2.2j.LF (or greater) solid tantalum capacitor in parallel with a
O.Ij.LF ceramic capacitor should be used for decoupling each
+ Vs and - Vs. A I.Oj.LF (or greater) solid tantalum capacitor
should be used for decoupling VDO,
Transmission Line Effects
The digital interface has 10K ECL speed and with 15pF loading
exhibits a typical edge rate of l.4ns. High speed CMOS systems
that incorporate the ADB32 must use careful PCB layout and
impedance matching techniques to reduce crosstalk and voltage
reflections.
The effect will be most severe on "clock" lines in synchronous
systems such as Read, Write and Chip Select lines. For example,
should the ADB32 Read control input (RD) be double clocked
as a result of a reflection while in a read cycle, in most cases the
digital interface chip will be fast enough to respond. If the
FIFO is being read from, a second shift out will occur and AID
conversion results will be lost.
Since CMOS output stages are not capable of delivering enough
current to the load when a transmission line (PCB trace) is
terminated in its characteristic impedance, a series damping is
recommended when reflections must be reduced or eliminated.
Here, a small resistor (typically IOn to 75.0) is inserted in series
with the transmission line as close to the source as possible. The
goal is to match the series resistance plus driver output impedance
to the transmission line impedance. This will keep the wave that
is reflected back from the load to source from reflecting back to
the load.
Crosstalk
The fast edge rates with large voltage swings of CMOS systems
can result in capacitive and inductive coupling (crosstalk) between
adjacent PCB signal traces and may compromise signal integrity
and reduce noise margins. The effect can be most severe on
data lines that are near "clocked" control lines, such as Read,
Write and Chip Select lines, when they actually change their
logic state as a result of crosstalk.
The primary disadvantage of series termination is that due to
the voltage divider formed by the source resistance and line
impedance, the voltage at the input to the line is midway between
logic levels during the two way propagation delay time. This
means that although any number of device inputs may be attached
at the load end, other device inputs cannot be distributed along
the transmission line.
To reduce crosstalk, the PCB layout should minimize long
parallel traces. If this can not be avoided, clock lines should be
shielded from data and address lines by running ground traces
along side them.
REFERENCES
Voltage Reflections
The gross impedance mismatch between high impedance CMOS
inputs and low impedance CMOS outputs invites unwanted
voltage reflections and "ringing" that can also compromise
signal integrity and reduce noise margins. This level of mismatch
causes a nearly equal and opposite negative pulse to be reflected
back from the load to the source ·when the round trip delay of
the line exceeds t\le rise or fall time of the driving signal. For a
typical line delay of O.055nslcm with a l.4ns edge rate, this
translates to only Bcm (S inches) for the ADB32. Provided the
signal lines are over a ground plane, this may never be a problem
since the added capacitance will reduce the edge rate.
1. Oppenheim, Alan V. and Schafer, Ronald W., Digital Signal
Processing, Prentice Hall, 1975.
2. Marple, S. Lawrence, Digital Spectral Analysis with Applications,
Prentice, Hall 1987.
3. Cypress Semiconductor, CMOS Data Book, Cypress
Semiconductor, 1987.
DA TA ACQUISITION SUBSYSTEMS 9-47
I
•
9-48 DA TA ACQUISITION SUBSYSTEMS
IIIIIIIIIII ANALOG Four-Channel 12-Bit Sampling AID Converter
W DEVICES
for Digital Signal Processing
AD1334 I
I
FEATURES
Four-Channel AID Converter for DSP Includes:
Simultaneous or Independent Sampling
Capability
12-Bit Accurate AID Converter
2-Bit Channel ID Tags Each Conversion Result
32-Word FIFO Memory
Fully Asynchronous, High Speed Digital Interface
Single-Channel Sample Rate Up to 67kHz
Four-Channel Simultaneous Sample
Rate Up to 28kHz
Entire System Dynamically Characterized
Minimal Effective Aperture Delay Mismatch from
Channel-to-Channel III Device-to-Device
15ns Data Access Time Allows "No Wait State"
Interface to: ADSP-2100 (AI, TMS320C25
DSP56000, NEC,..PD77230
Low Power, 250mW/Channel
APPLICATIONS
Sonar Signal Processing
Robotics/Machine Control
Disk-Drive Head Positioning
Vibration Analysis
PRODUCT DESCRIPTION
The AD1334 is a four-channel, 12-bit, sampling AID converter
system optimized for use in multichannel digital signal processing
(DSP) applications. The device consists of four independent
sample-and-hold amplifiers, a multiplexer, an AID converter, a
controller, a 32-word FIFO memory and a fully asynchronous
high speed digital interface. The" product is packaged in a 4O-pin
hermetic DIP.
The channel controller enables the AD 1334 to appear as four
independent channels of analog input by generating all of the
timing necessary to ensure that the sampled channel is digitized
to 12-bit accuracy. Upon receipt of a sample command, the
controller will immediately place the sample-and-hold amplifier
into hold mode and then prioritize and schedule the held value
for AID conversion. At the appropriate time, the sampled input
is gated through the multiplexer and, after settling, is digitized
by the AID converter. The sample-and-hold amplifier is then
returned to sample mode so that it can acquire the next sample.
AD1334 FUNCTIONAL BLOCK DIAGRAM
REF OUT
CHANa IN
CHANllN
DO- 013
CHAN2 IN
AO
os
}--++~ORSf
liD
CHAN3 IN
Wii
iRQ
SiMULT
3 2
1
0
SAMPLE
eLK
IN
RfADY CONTROL
ENB
For effective use in simultaneous sampling applications, the
sample-and-hold amplifiers are designed to provide a minimum
amount of aperture delay time mismatch from channel-to-channel
and device-to-device.
The 12-bit AID converter can convert ± SV full scale signals at
sample rates up to 67kHz for single-channel operation. In the
simultaneous mode, the AD1334 has a four-channel sample rate
up to 28kHz. The entire converter system is specified and tested
for signal-to-noise ratio, total harmonic distortion and channel-tochannel isolation.
The digital interface provides a true asynchronous link between
the AID and a high speed microprocessor. Data transfer is controlled by generating an interrupt signal when data is available.
Interrupts can be generated when the FIFO is full (32 words),
half-full (16 words), or when a single word of data is ready
(FIFO bypassed). The AD1334 can also generate an interrupt
when the AID conversion results are overrange.
The AD 1334 provides a completely specified and tested system
that bridges the interface and specification gap between AID
converters and high speed DSP.
DA TA ACQUISITION SUBSYSTEMS 9-49
II
SPECIFICATIONS
(TA= +25"1:, Vs= ±15V, Voo= +5V and fClJ( =2.5MHz unless noted)
Parameter
S/H, Mux & A/D Converter'
Input Impedance
Voltage Range
Output Coding
CLK IN Frequency, (feLK)
High Time
Low Time
Sampling Rate Per Channel (fs)
Simultaneous Mode (SIMULT = LOW)
I Channel
2 Channels
3 Channels
4 Channels
Independent Mode (SIMULT = HIGH)
I Channel
2 Channels
3 Channels
4 Channels
S/H
Acquisition Time to 0.01%
Droop Rate
Over Temperature
- 3dB Small Signal Bandwidth
Group Delay2 (flN< 10kHz)
Aperture Delay 3
Effective Aperture Delay 4 (fIN< 10kHz)
Static Characteristics
Integral Nonlinearity
Over Temperature
Resolution for No Missing Codes
Over Temperature
- Full-Scale Error
Over Temperature
+ Full-Scale Error
Over Temperature
PSRR, ±Vs
Dynamic Characteristics s,6
Signal-to-Noise Ratio,
fIN = 13.6kHz
Total Harmonic Distortion, fIN = 13.6kHz
Intermodulation Distortion, fIN' = 13.1kHz
& fIN2 = 13.6kHz
Channel-to-Channel Isolation 7 , fIN = 8.009kHz
SIMULT=LOW
SIMUL T = HIGH
Reference Voltage
Output Current
Drift
9-50 DATA ACQUISITION SUBSYSTEMS
AD1334BD
Typ
Max
Min
2
k!1
V
2.5
-5to +5
Offset Binary
1.0
200
200
2.5
MHz
ns
ns
67
46
35
28
kHz
kHz
kHz
kHz
67
67
kHz
kHz
kHz
kHz
44
33
6.5
7.5
0.2
1.0
Doubles Every 10°C
200
785
10
15
0
-700
-775
-850
± 112
±1
±1
±2
±4
±2
±4
± 112
±4
±8
±4
±8
12
12
70
70
-5.05
±1
Units
J..Ls
mV/ms
kHz
ns
ns
ns
LSB
LSB
Bits
Bits
LSB
LSB
LSB
LSB
LSBIV
72
-86
-76
dB
dB
-86
-76
dB
-4.95
dB
dB
V
rnA
ppmfOC
78
74
±2
±5
±25
AD1334
AD1334BD
Parameter
DIGITAL INPUTS 6
Voltage Input, LOW
HIGH
Input Current
Input Capacitance
RST LOW Pulse Width
DIGITAL OUTPUTS 6
DO-DB, READY
Output Voltage, Logic LOW, IOI• = 4rnA
OutputVoltage,LogicHIGH,loH = -4rnA
3-State Leakage Current
IRQ, CONTROL ENB
OutputVoltage,LogicLOW,loL = 4rnA
IRQ Off-State Leakage
Output Capacitance
FIFO Fall-Thru Time
IRQ LOW to DO-D B Valid8
POWER REQUIREMENTS
Operating Range
:tVs
VDD
Supply Current
+Vs
-Vs
+VDD
Consumption
±Vs=±12V
±Vs= ±15V
TEMPERATURE RANGE
Operating and Specified
Storage
Min
Typ
Max
Units
+0.8
V
V
fLA
pF
ns
+2.0
:t2S0
5
IO
+0.4
V
V
fLA
+2.4
:t 10
+0.4
:t1O
800
0
V
fLA
pF
ns
ns
± 15.75
+5.25
V
V
42
40
2
60
57
5
rnA
rnA
rnA
1.0
1.2
1.2
1.5
W
W
+85
+ ISO
°C
°C
5
400
± 11.4
+4.75
-40
-65
NOTES
'Specifications are per channel in 4 Channel Simultaneous Mode (SAMPLE 0-3 connected together and SIMULT 15< CONTROL ENB = LOW),
at fs = 28kHz, and with SAMPLE 0-3 having an 80% duty cycle unless noted.
'Group delay is the negative ofthe 1st derivative of phase with respect to frequency and is a measure ofthe analog time delay through the S/H.
'Aperture delay is the time delay from the SAMPLE input to S/H switch opening and is a measure of the digital time delay through the SIH.
'Effective aperture delay is the difference between analog and digital time delays described in (2) and (3).
'THD of harmonics 2-7 ofthe fundamental.
SNR offundamentalless harmonics 2-7.
6Guaranteed over operating temperature and power supply voltage range tested at + 25°C only.
'Isolation of anyone channel from remaining three channels which have near maximum amplitude ae signals at their inputs.
'RD,CS,AO=LOW;WR,RST= HIGH.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units. All other specifications are guaranteed but not tested.
DA TA ACQUISITION SUBSYSTEMS 9-51
Max
Parameter
Description
Conditions
Min
READ CYCLE
tRC
Read Cycle Time
COUT = 30pF
CoUT=IOOpF
2S
35
tA
Data Access Time
COUT = 30pF
COUT = lOOpF
tLZ
Output Low Z Time
tHZ
Output High Z Time
toH
tAORD
Output Hold Time
AO Valid to RD LOW
2
3
ns
ns
tRoAO
RD HIGH to AO Invalid
3
ns
tAOCS
AO Valid to CS LOW
3
ns
tcsAo
CS HIGH to AO Invalid
3
ns
Write Cycle Time
IS
ns
Write Pulse Width
5
ns
tsu
Data Setup Time
2
ns
tm
Input Hold Time
3
ns
tAOWR
AO Valid to WR LOW
3
ns
tWRAO
WR HIGH to AO Invalid
3
ns
tAOCS
AOValidtoCSLOW
3
ns
tcsAO
CS HIGH to AO Invalid
3
ns
WRITE CYCLE
twc
twp
Units
ns
ns
IS
2S
ns
ns
ns
2
IS
25
CoUT = 30pF
COUT = lOOpF
ns
ns
Specifications subject to change without notice.
All specifications are guaranteed but not tested.
ABSOLUTE MAXIMUM RATINGS·
+Vs to APWRIASIG GND .
- VS to APWRIASIG GND . .
VDoto DGND . . . . . . . .
APWR/ASIG GND to DGND
Analog Input to APWRIASIG GND
Digital Input to APWR GND
SAMPLEO-SAMPLE3, CLK IN,
SIMULT, CONTROL ENB ..
Digital Input to DGND
D~DJ3, RD, WR, CS, AO, RST
+17V
-17V
. +7V
-O.3V to +O.3V
-Vs to +Vs
. ..
-O.3V to +7V
-O.3V to VDO + O.3V
Output Short Circuit Duration
REF OUT, TP . . . .
Digital Output . . . .
Lead Temperature Range,
Soldering for lOsec . .
ORDERING GUIDE
Temperature
Range
Package
Options·
ADJ334BD
-40°C to + 85°C DH-40A
AD1334TD883B - 55°C to + 125°C DH-40A
·See Section 14 for package outline information.
9-52 DATA ACQUISITION SUBSYSTEMS
. . . . . +300°C
NOTES
·Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure 10 absolute maximum rating conditions for extended
periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
Model
. . .. Indefinite
1 Output for lsec
WARNING!
0
~~OEVICE
AD1334
AO
~-AO-"D--:-------:----'
~-------~--------~
AO
rr:m"'7'?"'7'?'"7
NQTES
__
~ IS VAllO BEFORE OR COINCIDENT WITH I!Q..HIGH· TO·LOW TRANSITION.
CS IS INVALID AFTER OR COINCIDENT WITH RD LOW·TO·HIGH TRANSmON.
WR IS NOT ACTIVE DURING READ CYCLE.
!l!QTES
_
~IS VALID BEFORE OR COINCIDENT WITH VlltHIGH·TO·LOWTRANSmON.
~IS INVALID AFTER OR COINCIDENT WITH WR LOW· TO-HIGH TRANSITION.
RD IS NOT ACTIVE DURING WRITE CYCLE.
Timing Waveform for Read Cycle No. 1 (RD Controlled)
Timing Waveform for Write Cycle No. 1 (WR Controlled)
Figure 1.
~"'I------t"C-------<~
AO
~--------twc-------~
~~AOC-S-----"--
AO
rr.,...r-rr...,..,.,.,
'WP
DIN
DOUT ------+__~
~'SU
'O"M
NQTES
__
!!Q IS VALID BEFORE OR COINCIDENT WITH qHIGH·TO·LOW TRANSITION.
RD IS INVALID AFTER OR COINCIDENT WITH CS LOW·TO·HIGH TRANsmON.
WR IS NOT ACTIVE DURING READ CYCLE.
Timing Waveform for Read Cycle No. 2 (CS Controlled)
Timing Waveform for Write Cycle No. 2 (CS Controlled)
Figure 2.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Timing Reference Levels
Inputs
Outputs
LOW
HIGH
Enabled to LOW
Enabled to HIGH
Disabled from LOW
Disabled from HIGH
DGNDto +3.0V
.
770
~ 780
20 1---:::;;_=-
Ii
~:::;;;....=:::::---+_------__l
!
790
101--------1--------~--------~
O~------~------
O~____~~~-------L--------~
1.0
2.0
1.S
1.D
2.5
1.5
'elK-MHz
Figure 4. Maximum Sample Rate vs.
Clock Frequency (Simultaneous Mode)
__
- L________
2.0
'cu:- MHz
~
20
2.5
Figure 5. Maximum Sample Rate vs.
Clock Frequency (Independent Mode)
Figure 6. Effective Aperture Delay
vs. Frequency
100
-10
70
,80
-30
~
-40
Ii ..
50
's=28kHz
.....
50
i!:
's,..28kHz
Q40
;
-70
20
~
-80
10
-90
o
o
6
8
'IN- kHz
1D
,.
12
-100
0
10
12
f s =28kHz
30
20
101---t---+---+_--+_--~--~--~
,.
''''- kHz
Figure 7. AID SNR vs. Frequency
(Average of Four Channels,
Simultaneous Mode)
Figure 8. AID THO vs. Frequency
(Average of Four Channels,
Simultaneous Mode)
1.3
1.3
Figure 9. Channel-to-Channel
Isolation vs. Frequency
15
I-
T,,=25"C
~
I
t--
1.2
1.2
"- -....,
1.0
1
~
~
D."
0.8
----
0.8
0.7
0.7
'.5
4.75
5.0
5.25
5.5
VDD - V
Figure 10. Normalized Data
Access Time vs. Voo
~54
-
50
-
30
7D
1
.
Q -50
40
-
90
!II
-20
~
20k
' .. _Hz
..
1.1
2.
200
DA TA ACQUISITION SUBSYSTEMS
y
-.D
V
/
V
/
TA=~5"C
YDO=S.OV
10
./'
./'
/'
./'
/"
./'
Voo=5.0V
o
D
+25
+70 +85
TEMPERAtURE - "C
Figure ". Normalized Data
Access Time vs. Temperature
V
D
25
50
7S
100
125
CAPACITANCE - pF
Figure 12. Change in Data
Access Time vs. Loading
160
AD1334
PIN CONFIGURATION
CHAN11N
01
400
CHANZIN
CHANOIN
02
390
CHAN31N
+V.
03
380
-V.
SAMPLE 0
04
370
SAMPLE 3
SAMPLE 1
Os
360
SAMPLE 2
TP
06
350
SIMULT
REF OUT
07
340
READY
ASIG GND
08
APWRGND
09
AD1334
330
CLKIN
(Not to
320
CONTROL ENB
Scale)
310
RST
TOP VIEW
IRO
010
CS
011
300
WR
AO
012
290
iiii
(CHID MSB) D13
013
280
DO (AID LSB)
(CHID LSB) D12
014
270
D1
(AID MSB) D11
015
260
D2
D10
016
250
D3
D4
D9
017
240
D8
018
230
D5
D7
019
220
D6
DGND
020
210
V DD
PIN DESCRIPTIONS
Pin
Mnemonic
Function
2
1
40
39
6
32
34
CHANOIN
CHANIIN
CHAN 2 IN
CHAN3IN
TP
CONTROLENB
READY
35
SIMULT
8
7
3,38
9
33
4
5
36
37
10
ASIGGND
REF OUT
+ Vs , -Vs
APWRGND
CLKIN
SAMPLE 0
SAMPLE 1
SAMPLE 2
SAMPLE 3
IRQ
II
12
28-22
19-13
29
30
31
20,21
CS
AO
DO-D6
07-D13
RD
Channel 0 analog input.
Channell analog input.
Channel 2 analog input.
Channel 3 analog input.
Test Point (no connect).
Input and (open drain) output used to enable controller externally or through I1P interface.
Output that, in simultaneous mode, indicates all channels have been successfully convened
and device is ready to sample.
Input that when LOW sets controller to simultaneous mode which keeps S/Hs in hold mode until
all channels have been convened.
Analog signal ground.
- 5V reference output.
Analog power supplies.
Analog power ground.
External clock input to the A/D convener and channel controller.
Channel 0 SIH control input.
Channell SIH control input.
Channel 2 S/H control input.
Channel 3 SIH control input.
Open drain interrupt request. User programmable to become active on any of the following
conditions:
One AID Conversion Result Available;
FIFO Half Full or Full;
AID Conversion Results Over range.
Chip select input.
Address bit zero. Selects data path from FIFO/latch (low) or fromlto Status!Control register (high).
Bidirectional3-state datalines. D II is AID convener MSB when DO-D 13 are outputs. D7 is Status!
Control register MSB. D 12 and D 13 carry channel ID number.
Read control input (DO-D13).
Write control input (DO-D7).
Reset. In reset state, FIFO is transparent & overrange detector is disabled.
Digital power supply.
WR
RST
DGND,Voo
DATA ACQUISITION SUBSYSTEMS 9-55
I
COMPONENTUST
CHANNELO
Ul :AD1334
INPUT
Cl-C3: 2.2p.FTANTAWM
C4-C6: 0.1p.FCERAMIC
Rl.R2:2kfl
CHANNELl
INPUT
CHANNEL 2
INPUT
CHANNEL 3
INPUT
--1-- -
+15V
U!!CI----.....
____
,.-.....
15V
'---_--1.
./
ANALOG
GROUND --I!~--""'1r-i
~l_----------~---I~
+5V
IRQ -;:~~::4.~>L---i
..
1---------130}---------
--------1
AO ---------Ll!.l
CS - .....
RST
WR
ni}---------ijD
1--------------_ DO
D13·_-------~rm
[22:1--------
D7---......"..,-11,,-----....,,.---------------
.
_ _ _ _ _ <...
, --~,.......,..........r-t'~'
ACQUIREB
ACQUIREB
SAMPLEC ______IIII_-----*II~III>_----*"~I1>_~~...
I------~!!!--------------~
--I
IRQ _____
3~c;.Q~RE~
~
3CP
14-
ACOUIREC
~,~,------~,,~~~~~,~---------------~~
CONVERT A
CONVERTB CONVERTC
SYNC (17CPI SYNC (17CPI SYNC (17CPI
(1-2CPI
(1-2CPI
(1-2CPI
----->f""""........, -----II~....----"'"'--<......----........,..! --~II---
SAMPLE A ______
ACOUIRE A
SAMPLE
ACQUIRE A
Ii --I;~I______-!tfti-4,,~t---ff--~s------4fo---oo(i..
' ------~,,---~
4 CHANNELS
~
ACQUIRE B
SAMPLE C
ACQUIRE B
~...
, _ _---lI.......t-----I~~-I-----4 .......~1---
.
.
ACQUIREC
ACOUIREC
~
I
.--It--I....
, --""'If-.---
SAMPLE D - - I I - I----il!-it-I----~H-1It-1__~~'~:::;:~=
3CP
iRO
ACOUIRE D
.-<~ MIN ~ ~~ t+- -t :,~~ t+- - - - - - I....
, ------........
,,' .
'-I;r~;.r~r---
.............
_"-v---"-v-
ACOUIRE D
•
_____....- -............--~~
CONVERT A CONVERTB CONVERTC CONVERTD
SYNC (17CPI SYNC (17CPI SYNC (17CPI SYNC (17CPI
(1-2CPI
(1-2CPI
(1-2CPI
(1-2CPI
Figure 16. Timing for Independent Sampling (SIMULT=High, FIFO Not Used)
wlWorst Case Skew of SAMPLE Control Inputs
DA TA ACQUISITION SUBSYSTEMS 9-59
II
If the FIFO is used, the falling edge of the READY signal, can
be used as an interrupt signal to notify a processor that the 1,2,
3 or 4 channels have been successfully converted and have been
shifted into the fIFO. All conversion results can be read from
the FIFO with the exception of the last one, which must fall
through to the output (fall-through time is typically 4OOns).
READY can also be used as a signal to the device generating
the sample command that the previous group of samples have
been converted and that the next group of samples are being
acquired.
lndependent~ode
Independent mode is selected by connecting the SIMULT pin
to logic high. This mode should be used when any number of
channels are sampled independently. In contrast to simultaneous
mode, this mode returns the sample-and-hold amplifier on the
sampled channel to sample mode when the channel input has
been digitized. This mode allows the AD1334 to emulate up to
four independent sampling AID converters, each of which can
accommodate different sample rates and hence different signal
bandwidths. The timing diagram for this mode is shown in
Figure 16. Note that IRQ becomes active on the completion of
every AID conversion since the FIFO is not being used.
The READY signal has no implicit definition in this mode,
other than the falling edge indicating that the controller has no
conversions pending.
AID CONVERTER
The analog input voltage range goes from - SV to + 5V and the
digital output coding is Offset Binary (see Table II). Twos
complement coding can be obtained by inverting the MSB
(011).
Center of Code
Voltage (V)
Output Code
-5.000000
-0.002441
0.000000
+4.997SS9
000
011
100
III
... 000
... III
... 000
... IJ I
Table II. AID Conversion Relationship
HIGH SPEED DIGITAL INTERFACE
The AD1334 completes the solution for AID conversion in DSP
applications by providing the system's designer a direct, high
speed parallel digital interface. The prime feature of this interface
architecture is that it operates completely asynchronously from
the AID converter and therefore allows the AD1334 to appear as
"memory" to a microprocessor.
The combination of fully asynchronous operation with respect
to the AID conversion process and fast data access time allows
the AD1334 user to upgrade to faster versions, or even different
vendors, of DSP hardware without having to add synchronization
or wait state logic. In addition, by virtue of hybrid circuit technology, the user is not required to add external circuitry to
prevent digital feedthrough into the analog section.
The AD1334 data transfer is accomplished by employing an
interrupt driven architecture. Interrupts can be programmed by
the microprocessor to be generated when the FIFO is full (32
conversion results), half-full (16 conversion results) or after
every conversion (FIFO is bypassed). The AD 1334 digital interface
also includes an overrange detect circuit, which
generate an
interrupt if the sampled analog input signal exceeds positive or
negative full scale, to alert the system that a conversion result
has been generated that will result in a nonlinearity in the subsequent signal processing.
=
Operational Description
The AD1334 can interface directly to a microprocessor via standard
data (DO - DB), address (AO) and control lines read (RD, WR,
CS, IRQ and RST).
Data Transfer
The data lines DO - DB are bidirectional 1/0 that are TTL
compatible and have 4mA drive capability. The data lines are
used to transfer control information into, and AID conversion
results with status information and channel identification out of
the AD 1334. Address line AO is an input that is used to select
as the data path either AID conversion results with channel ID
(AO =0) or the Control/Status Registers (AO = 1) and would
typically be the least significant address bit in the system if the
ADI334 is "mapped" to adjacent memory locations. Chip Select
(CS) is used to define a unique location in memory for the AD1334
and should be formed by decoding the upper address bits. Read
(RD) and Write (WR) define the type of data transfer.
Figures 17-22 illustrate how the AD 1334 interfaces to a number
of popular single chip digital signal processors.
Operational Description
Analog signal information is converted to a l2-bit digital word
by sampling the waveform and digitizing it using the successiveapproximation conversion technique. Since the clock does not
define the amount of time between samples, it need not be
crystal controlled. Best performance will be obtained by operating
the clock at the maximum 2.5MHz clock frequency.
9-60 DA TA ACQUISITION SUBSYSTEMS
Interrupts
Interrupt Request (IRQ) is an open drain output that can be
used to interrupt the processor on any of the conditions programmed in the control register. READY can be used in simultaneous applications as an alternative processor interrupt signal
as described above. In either case, the processor should be
programmed to interrupt on the falling edge of its Interrupt
Request input.
AD1334
+.v
+.v
1
1.
v~
I
14
J
DMA
J
~MA13
ADDRESS
DECODE
DMS
ADSP-21DOA
OMACK
H
'[
DMAI
oJ
V ••
I
TMS320C25
\Vii
OD
RESET
DMD
Riw
00- D13
. ...
.r--..
Lp
DM013 - DMDO
STRB
DGND
I
I
rl:d
WR
OD
H-J
RS
~
"1
I
GND
iRQ
OST
I
,.
V••
AO
cs
1NT
10Q
DMRD
[
I
I
I
A01334
AD1334
DMWO
T
READY H V
CO
~15 AI
ADDRESS
DECODE
IS
AO
V
10Q
A15_AO
1
I
[AO
1
v~
fiST
D1!i_DO
~
Figure 17. ADSP-2100A to AD 1334 Interface
013-00")
~
I
V"
RESET
00- D13 DGNO
r
I
I
RESET
Figure 18. TMS320C25 to AD 1334 Interface
+5V
1
I
v~
AU-A1S
..! 1#'
os
1
xiV
0$P56ooo
1iiQ
ADDRESS
DECODE
[
T
AI.
I
e
+5V
I
r
I
I
PSEL
AO
CO
DSP16
AD1334
INT
IRQ
WR
WR
ii6
RD
RESET
...
r
DO-013"
~
I
A01334
10Q
WR
PIDS
OD
RSTB
RST
1
P80_ P815
00- 013 DGND
PRO - P813 .,
~
I
V"
I
co
PODS
00- 013 OGND
I
VA
"'..J
T
v••
AO
RST
I
DO-D2l
I
f
Voo
v ••
"#
I
I
RESET
Figure 20. DSP16 to AD1334 Interface
Figure 19. DSP56000 to AD 1334 Interface
+SV
+5V
1
I
v ••
AU-An
.!_~Al-Al1
A.
T
,..P077230
iNT
\Vii
ii6
DO-031
GND
~
'(
I t
I
AO
Voo
CO
AD1334
I
1
DSmr-------------==~~P-----~
\Viif----------------I
IRQ
leLK
WR
h
lr------.
ZR34161
r=:==~~==;::.::r=p------1
Aiil-
MSfl~------------~----------~
OD
RESET
MIS
I
ADDRESS
DECODE
AO_ A1S
\
RST
00- D13
OBO-DB13"'1
DGND
~
I
I
Figure 21. f.LPD77230 to AD1334 Interface
I
DB~~ 0815 N"-------------,-------,------------,...J
RESET~----
_______________J
Figure 22. ZR34161 to AD1334 Interface
DATA ACQUISITION SUBSYSTEMS 9-61
•
FIFO Half-Full Interrupt
The timing for interrupts that are generated when the FIFO is
half-full is shown in Figures 23a and 23b. In both figures, IRQ
becomes active· when the 16th AID conversion result is shifted
into the FIFO. In Figure 23a, the processor responds immediately
and a read cycle takes place before the next conversion cycle
begins. Here, the completion of the read cycle shifts the 1st
conversion result (which was just read by the processor) out of
the FIFO, replaces it with the second conversion result and
causes IRQ to become inactive since there are now 15 conversion
results in the FIFO.
FIFO Full Interrupt
The timing for interrupts that are generated when the FIFO is
full is shown in Figures 24a and 24b. In both figures, IRQ
becomes active when the 32nd AID conversion result is shifted
into the FIFO. In Figure 24a, the processor responds immediately
and a read cycle takes place before the next conversion cycle
begins. Here, the completion of the read cycle shifts the first
conversion result (which was just read by the processor) out of
the FIFO, replaces it with the second conversion result and
causes IRQ to become inactive because there are now 31 conversion
results in the FIFO.
In Figure 23b, the processor does not respond before the next
conversion cycle begins and IRQ becomes inactive. The FIFO
continues to accept conversion results and the processor can
read from the FIFO at any time so long as the FIFO has not
overrun.
In Figure 24b, the processor does not respond before the next
conversion cycle begins and IRQ becomes inactive. The processor
must read from the FIFO before the completion of the current
conversion cycle or the FIFO will overrun. This mode maximizes
the memory capability of the AD1334 but requires a fairly high
interrupting priority in the processor since the processor has
only one AID conversion before the FIFO overruns. Therefore,
the processor will have only 15",s to respond at the maximum
sample rate of 65kHz.
This mode allows the AD1334 to have a low interrupting priority
since the processor has up to 17 additional AID conversions
before the FIFO overruns. Therefore, the processor will have
up to 26O",s to respond at the maximum sample rate of 65kHz.
16TH CONVERSION RESULT
SHIFTED IN I
cP-.j
j.-
+
l
32ND CONVERSION RESULT
SHIFTED IN I
NEXT CONVERSION
BEGINS
CP-.j
IRO ~----------------------------
~O.AO ~I -------,U,.~~"",....".u..."u.......
u"""!"u,......u,......u,.....,l.'",~.."..,~..""'-L...., -u....·...".-
Figure 23a. Timing Diagram for Half-Full Interrupt (Read
Before 17th Conversion Started)
16TH CONVERSION RESULT
NEXT CONVERSION
SHI~EDIN
BEGINS
I
CP...j
I-
t
CONVERSION RESULT
SHIFTED IN
+
ClKIN
,...I1J1.J"l.I"
IRO
~ READ~EFORE33RDCONVERSIONSHIFTEDIN
I*-~~:--t ------1,,.....-----------------
Ri5
(CS=O.AO~I)
NEXT CONVERSION
I BEGINS
t
ClKIN
CLKIN
(CS
1-+
,~UuUuu:.Ju
ma~----------------------------
jffi-------,u
(CS~O,AO=I)
u u u
u
J u u U
u:.! n
u u
Figure 24a. Timing Diagram for Full Interrupt (Read
Before 33rd Conversion Started)
32ND CONVERSION RESULT
SHIFTED IN I
CP--i
NEXT CONVERSION
BEGINS
14-.
ClKIN
CONVERSION RESULT
SHIFTED IN
t
14--~~~--I
IRO~--~"~------------------
READ BEFORE 33RD CDNVERSIDN'SHIFTED IN.
jffi ------------I,~
(CS~O.AO~11
L L L u
u
u u
Figure 23b. Timing Diagram for Half-Full Interrupt (Read
After 17th Conversion Started)
Figure 24b. Timing Diagram for Full Interrupt (Read
After 33rd Conversion Started)
Conversion Results Overrange Interrupt
If the FIFO is used, the AD1334 can be programmed to generate
interrupts when overranged conversion results are shifted into
the FIFO. If IRQ became active as a result of an overrange
condition, the only way it can become inactive is to clear Bit 4
of the control register. Typically, the user should clear the
entire control register which will, in effect, remove the interrupt,
reset the FIFO and disable the controller.
This mode makes data available immediately after the conversion
process has been completed and is therefore very similar to the
operation of a conventional AID converter if IRQ is taken to
mean conversion STATUS. This mode is most useful when a
single conversion result is necessary to adjust a system parameter,
such as the gain of a PGA that may be in front of an AD1334.
Should the overrange interrupt capability be used, Status Register
Bits 4 and 6 can be used to identify whether the interrupt occurred
as a result of an overrange condition or FIFO half-full (or full).
Single Conversion Interrupt (FIFO Bypassed)
The timing for interrupts that are generated when the FIFO is
bypassed is shown in Figures 15 and 16. Here, IRQ becomes
active at the completion of each AID conversion cycle. IRQ
remains active, independent of the read cycle, until the next
conversion cycle begins, which is a minimum of three clock
periods (1.2",s with 2.5MHz clock). Data is valid so long as
IRQ remains active.
9-62 DA TA ACQUISITION SUBSYSTEMS
Since IRQ will only be valid for only three AID clock periods
(1.2",s with a 2.5MHz clock), a high interrupting priority should
be assigned by the processor. Should the single conversion
result be necessary to adjust a system parameter as described
above, it may be more efficient to "poll" the Status Register to
determine when the conversion result is available.
Operation Other Than with a Microprocessor
The AD1334 can be used in other than microprocessor environments by grounding pins 11, 12 and 29 (CS, AO and RD), connecting Pin 30 (WR) to Voo and pulsing RST low. This will
permanently enable the AD 1334 three-state outputs and clear
the control register, causing the FIFO to be bypassed.
AD1334
Multiple AD1334s
The architecture of the AD1334 allows multiple devices to be
used in a microprocessor based system. Figure 25 illustrates
how four AD1334s can be configured to simultaneously sample
their analog inputs and reside in eight sequential locations in a
microprocessor's memory address space. The control register of
each device should be programmed to interrupt on the same
condition so that the same number of conversion results are
available from all devices.
!
CHANOIN
CHAN 1 IN
CHAN21N
CHAN31N
~J
CHAN 0
IRQ
IN
iiD
+5V
WR
RST
AD1334
CS
CLKIN
CHAN 1
U
:~
SAMPLE
r---<
I Xl)
DO-013
JANALOGIN
3
r-f
For each group of four samples, a processor can be used to
discard the three AID conversion results that were not converted
on the optimum range. The system shown can provide results at
sample rates up to 28kHz.
IN
V,N
CHAN2
IN
CHAN 3
OJ
CHAN41N
CHAN51N
1
CHAN61N
2
CHAN71N
3
~
!
CHAN91N
CHAN11 IN
~
CHAN151N
f.
2.SMHz
DO- D13
AD1334
CLKIN
ANALOG IN
; J ADI334
2
SAMPLE
3
elKIN
~--~--------------------4-~
=ro
} J SAMPLE
!OJ
-~
IRO
RO
WR
RST
}NALOGIN
3
t
CHAN 131N
CHAN 141N
=rcl
)sAMPLE
eLKIN
CHAN81N
IN
RO
WR
RST
AD1334
~
CHAN lOIN
CHAN 121N
00-013
IIili
ANALOG IN
00
----------------------...p
2.5MHz - -....
013
DO_ D13
IRQ
RO
WR
RST
IRQ
RO
AD
csN~
DECODE
WR
RST
AO
AI
.2
A3_ AMAX
Figure 25. Sixteen-Channel Simultaneous Sampling System
Floating Point Converter
Figure 26 illustrates how to boost the dynamic range of the
AD1334 by including it in a floating point AID converter architecture: The AD526 is a single-ended programmable gain
amplifier with gains of 1,2,4,8 and 16. Here, four AD526s are
"hardwired" into gains of 1,2,4 and 8 to extend the dynamic
range of the AD 1334 to IS bits. Fully differential inputs with
gains up to 500 can be obtained by substituting the AD365 for
the AD526.
The AD1334 is operated in simultaneous mode, with one AD526
per channel. Upon receipt of a sample command, the four channels
are sampled and converted. Table III summarizes the input
voltage range for each channel.
Channel
o
I
2
3
Input
Voltage Range
-5Vto +5V
-2.5Vto +2.SV
-I.2SVto + I.2SV
-62SmVto + 625mV
Table III.
SAMPLE
CHAN 3
eLK IN
Figure 26. Fifteen-Bit Floating Point AID Converter
SUCCESSFULLY APPLYING THE ADl334
Grounding
In order to obtain the specified performance of the AD1334,
proper grounding and power supply decoupling techniques must
be observed. First, it is imperative that a ground plane be used.
A ground plane provides a low resistance, low inductance path
for currents to flow back to their source. Without a ground
plane, currents will return to the source in such a way as to
minimize the energy of the system and therefore parasitic inductances will exist in such undesirable locations as power supply
lines and signal grounds.
Second, all three ground connections on the AD1334 must be
tied together to the ground plane. The AD1334 APWR GND
(Pin 9) carries the imbalance current from the analog power
supplies (±Vs). APWR GND is also connected to the package
seal ring/lid and therefore can cause coupling between the analog
and digital sections if it is not tied directly to the ground plane.
ASIG GND (Pin 8) is the signal ground internal to the AD1334
and is "common" for the - SV reference, sample-and-hold
amplifiers, multiplexer and AID converter. The current that
flows through this pin from the AID converter is a dynamic
current that changes on every clock cycle. Inductance in this
trace will therefore cause a reduction in perfonnance in the
entire analog section.
DGND (Pin 20) is a separate ground connection for the digital
interface chip. It carries a dynamic current every time a digital
output changes state, and inductance in the trace that connects
to this pin will reduce the noise margin between the AID converter
and the digital interface chip.
DA TA ACQUISITION SUBSYSTEMS 9-63
II
Power Supply Decoupling
The power supply decoupling capacitors supply the instantaneous
current to the AD1334 and also provide some high frequency
filtering. The filtering aspect of the capacitors should not be
counted on how~er, and the user should make every effort to
supply quiet, well regulated power supplies to the AD1334.
Switching mode power supplies are not recommended for the
analog power supplies ± Vs.
Decoupling capacitors should be placed as close to the device as
possible to minimize inductances in power supply traces. A
2.2j1.F (or greater) solid tantalum capacitor in parallel with a
O.Ij1.F ceramic capacitor should be used for decoupling each
+ Vs and - Vs. A l.Oj1.F (or greater) solid tantalum capacitor
should be used for decoupling Voo.
Transmission Line Effects
The digital interface has 10K ECL speed and with 15pF loading
exhibits a typical edge rate of I Ans. High speed CMOS systems
that incorporate the AD1334 must use careful PCB layout and
impedance matching techniques to reduce crosstalk and voltage
reflections.
Crosstalk
The fast edge rates with large voltage swings of CMOS systems
can result in capacitive and inductive coupling (crosstalk) between
adjacent PCB signal traces and may compromise signal integrity
and reduce noise margins. The effect can be most severe on
data lines "that are near "clocked" control lines, such as Read,
Write and Chip Select lines, when they actually change their
logic state as a result of crosstalk.
To reduce crosstalk, the PCB layout should minimize long
parallel traces. If this can not be avoided, clock lines should be
shielded from data and address lines by running ground traces
along side them.
Voltage Reflections
The gross impedance mismatch between high impedance cMos
inputs and low impedance CMOS outputs invites unwanted
9-64 DATA ACQUISmON SUBSYSTEMS
voltage reflections and "ringing" that can also compromise
signal integrity and reduce noise margins. This level of mismatch
causes a nearly equal and opposite negative pulse to be reflected
back from the load to the source when the round trip delay of
the line exceeds the rise or fall time of the driving signal. For a
typical line delay of O.055ns/cm with a lAns edge rate, this
translates to only Bcm (5 inches) for the ADB34. Provided the
signal lines are over a ground plane, this may never be a problem
since the added capacitance will reduce the edge rate.
The effect will be most severe on "clock" lines in synchronous
systems such as Read, Write and Chip Select lines. For example,
should the ADB34 Read control input (RD) be double clocked
as a result of a reflection while in a read cycle, in most cases the
digital interface chip will be fast enough to respond. If the
FIFO is being read from, a second shift out will occur and AID
conversion results will be lost.
Since CMOS output stages are not capable of delivering enough
current to the load when a transmission line (PCB trace) is
terminated in its characteristic impedance, series damping is
recommended when reflections must be reduced or eliminated.
Here, a small resistor (typically 100 to 750) is inserted in series
with the transmission line as close to the source as possible. The
goal is to match the series resistance plus driver output impedance
to the transmission line impedance. This will keep the wave that
is reflected back from the load to source from reflecting back to
the load.
The primary disadvantage of series termination is that due to
the voltage divider formed by the source resistance and line
impedance, the voltage at the input to the line is midway between
logic levels during the two-way propagation delay time. This
means that although any number of device inputs may be attached
at the load end, other device inputs cannot be distributed along
the transmission line.
REFERENCES
Cypress Semiconductor, CMOS DallJ Book, Cypress Semiconductor, 1987.
16-Channel, 12-Bit
Data Acquisition System
AD1362 I
~ANALOG
WDEVICES
FEATURES
Pin and Functional Replacement for AD362:
Lower Power Dissipation
Lower Noise
Internal Hold Capacitor
16 Single-Ended or S Differential Channels with
Switchable Mode Control
True 12-Bit Precision: Nonlinearity :s0.005%
High Speed: 10...s Acquisition Time to 0.01%
Complete and Calibrated: No Additional Parts
Required
Versatile: Simple Interface to Popular Analog-to-Digital
Converters
High Differential Input Impedance (10,on) and
Common Mode Rejection (SOdB)
Fully Protected Multiplexer Inputs
AD1362 FUNCTIONAL BLOCK DIAGRAM
DGND
The sample-and-hold mode control is designed to connect
directly to the "Status" output of an analog-to-digital converter
so that a convert command to the ADC will automatically put
the sample-and-hold into the "Hold" mode. An internal precision hold capacitor is included with each AD1362. The AD1362
output amplifier is capable of driving the unbuffered analog
input of most high speed, 12-bit successive-approximation
ADCs. The interface is thereby reduced to two simple connections with no additional components required.
+1SV
-1SV
AGND
CH.
CH,
CH2
SHACMO
OM'
CM<
CHO
CHI
ANALOG
ANALOG CH7
INPUTS
OU,,"UT
CHI
C",
CH"
eN',
eN1!
e""
eM"
eH15
LATCH
SELECT
PRODUCT DESCRIPTION
The AD 1362 is a complete, precision 16-channel data acquisition
system. The device contains two 8-channel multiplexers, a differential amplifier, a sample-and-hold with high-speed output
amplifier, a channel address latch and control logic. The multiplexers may be connected to the differential amplifier in either
an 8-channel differential or 16-channel single-ended configuration. A unique feature of the AD 1362 is an internal usercontrollable analog switch that connects the multiplexers in
either a single-ended or differential mode. This allows a single
device to perform in either mode without hard-wire programming and permits a mixture of single-ended and differential
sources to be interfaced by dynamically switching the input
mode control.
+5V
CHANNEL
saECT
SINGLEJDIFF
CONTROL
PRODUCT HIGHLIGHTS
1. The AD1362, when used with a precision analog to digital
converter, forms a complete, accurate, high-speed data
acquisition system.
2. The 16-input channels may be configured in single-ended,
differential or a mixture of both modes. Mode switching is
provided by a user controllable internal analog switch.
3. Multiplexers, differential amplifier, sample-and-hold and
high-speed output buffer provide complete analog interfacing
capabilities.
4. Internal channel address latches are provided to facilitate
interfacing the AD 1362 to data, address or control buses.
5. The AD 1362 is specified over the entire military temperature
range, -55°C to + l25°C. Processing to MIL-STD-883, Class
B is available.
The AD1362KD is specified for operation over a 0 to +70°C
temperature range while the AD 1362SD operates to specification
from -55°C to + 125°C. Processing to MIL-STD-883, Class B
is available for the AD1362SD. Both grades are packaged in a
hermetic 32-pin ceramic dual-in-line package.
DA TA ACQUISITION SUBSYSTEMS 9-65
11
SPECIFICATIONS
(typical @ +25°C, ±15V and +5V unless otherwise noted)
Parameter
Test Condition
Min
ANALOG INPUTS
Input Voltage Range
Input Bias Current
Input Impedance
T.run to T max
Per Channel
On Channel
-10
AD1362KD
Typ Max
ACCURACY
Gain Error
Offset Error
Linearity Error
Power Off or On
Diff Mode, 1kHz, 20V p-p
70
80
1kHz, 20V p-p
-80
-90
TEMPERATURE COEFFICIENTS
Gain
Offset
SAMPLE AND HOLD DYNAMICS
Aperture Delay
Aperture Uncertainty
Acquisition Time
Feedthrough
Droop Rate
Pedestal Voltage
±2.5
T min to Tmax
T min to T max
25°C, 0.1 to IMHz
T.run to T max' 0.1 to IMHz
±0.02
±4
±O.OO5
±0.01
0.5
1.0
T min to Tmax
± IOV Range, T min to T max
±4
±2
@25°C
ISO
100
10
-80
20V Step to ±0.01%
1kHz
I
-15
POWER SUPPLY REQUIREMENTS
+V, Analog Voltage
- V, Analog Voltage
+V, Digital Voltage
+ V, Analog Current
- V, Analog Current
+ V, Digital Current
Total Power Dissipation
11
+ 14.25
-14.25
+4.75
O.
-55
200
500
18
-70
2
+15
+ 15.75
-14.75
+5.25
30
30
40
0.5
TEMPERATURE RANGE
Specification
Stomge
*
*
*
*
20
T min to Tmax
Noise Error
*
10
100
10
10
Off Channel
Input Fault Current
Common Mode Rejection
Mux Crosstalk, Any Off Ch
to Any On Ch
Ch to Ch Offset
+10
±50
ADl362SD
Min Typ Max
*
*
*
*
V
nA
GO
pF
GO
pF
mA
dB
*
dB
mV
*
*
*
%FSR
mV
%
%
mVp-p
mVp-p
±2
±'1.5
ppmfC
ppmfC
..
*
*
*
*
*
*
*
ns
ps
*
*
dB
*
*
mV
*
*
*
*
*
*
*
V
V
V
mA
mA
rnA
W
+125
+150
°C
°C
*
*
*
*
*
*
1.1
+70
+85
*
*
Units
-55
-55
*
fJ.S
mV/ms
*
DIGITAL INPUT SIGNALS
Signal
Pins
Input Channel Select
Channel Select Latch
Single Ended/Diff Mode Select
Sample-and-Hold Command
28-31
32
13
1
TTLl
Loads
Logic High
lLS
8LS
3LS
2LS
(4-Bit Binary Address)
Transparent
Latched
Differential
Single Ended
Hold
Sample
Logic Low
1
NOTE
'One TTL Load is defmed as IlL =-1.6mA max @ VIL =O.4V, IIH =40,.A max @ VlH=2.4V. One LSTTL Load is defined as IlL =-0.36mA @ VIL =O.4V,
I'H=20,.A max @ VlH=2.7V.
'Specifications same as AD1362KD.
9-66 DATA ACQUISITION SUBSYSTEMS
AD1362
ABSOLUTE MAXIMUM RATINGS
+V, Digital Supply . . . . . . . . . . . . . . . . . . . . . . . . . +S.SV
+ V, Analog Supply . . . . . . . . . . . . . . . . . . . . . . . . . + 17V
- V, Analog Supply . . . . . . . . . . . . . . . . . . . . . . . . . -17V
VIN ' Signal . . . . . . . . . . . . . . . . . . . . . . ±V Analog Supply
VIN ' Digital . . . . . . . . . . . . . . . . . . 0 to +V, Digital Supply
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . • . ±IV
AD1362 PIN ASSIGNMENT
SlNGLEIDIFF CONTROl
1
•
LATCH SELECT
Al
AO
AE
CHIlO)
CH911)
CH10 (21
CH11 (3)
CH12(.'
CH'3 (51
NO CONNECT
12
OFFSET ADJUST
'4
CH14 (81
OFFSET ADJUST
15
CH1&17I
-'BV
ANALOG OUTPUT
Function
SinglelDiff Control
DGND
+SV
Ch 7
Ch 6
Ch 5
Ch 4
Ch 3
Ch 2
Ch I
Ch 0
NC
SHACmd
Offset Adjust
Offset Adjust
Analog Output
AGND
Ch IS
Ch 14
-ISV
+ISV
Ch i3
Ch 12
Ch 11
Ch 10
Ch 9
Ch 8
AE
AO
Al
A2
Latch Select
Number
I
2
3
4
5
6
7
8
9
10
11
12
13
14
IS
16
17
18
19
20
21
22
23
24
2S
26
27
28
29
30
31
32
AGND
Description
Mode Select, Differential or Single Ended
Digital Ground
Digital Power Supply, + SV dc
"High" Analog Input Channel 7
"High" Analog Input Channel 6
"High" Analog Input ChannelS
"High" Analog Input Channel 4
"High" Analog Input Channel 3
"High" Analog Input Channel 2
"High" Analog Input Channel I
"High" Analog Input Channel 0
No Connect
Sample/Hold Control Input to SHA
Offset Adjustment Input # I
Offset Adjustment Input #2
Analog Output to ADC
Analog Ground
"High" ("Low") Analog Input Channel IS
"High" ("Low") Analog Input Channel 14
Negative Analog Power Supply -15V dc
Positive Analog Power Supply + ISV dc
"High" ("Low") Analog Input Channel IS
"High" ("Low") Analog Input Channel 14
"High" ("Low") Analog Input Channel 13
"High" ("Low") Analog Input Channel 12
"High" ("Low") Analog Input Channel 11
"High" ("Low") Analog Input Channel 10
Input Channel Address MSB
Input Channel Address Bit 0
Input Channel Address Bit I
Input Channel Address Bit 2
Channel Select Latch Control Input
•
(7)'
(6)
(5)
(4)
(3)
(2)
(I)
(0)
DA TA ACQUISITION SUBSYSTEMS 9-67
FUNCTIONAL DESCRIPTION
The AD1362 consists of two 8-channel multiplexers, a differential amplifier, a sample-and-hold with high speed output buffer,
channeL address latches and conttollogic as shown in the block
diagram. The multiplexers can be connected to the differential
amplifier in either an 8-channel differential or 16-channel singleended configumtion. A unique feature of the AD1362 is an
internal analog switch controlled by a digital input that performs
switching between single-ended and differential modes. This
feature allows a single AD1362 t~ perform in either mode without external hard-wire interconnections. Of more significance is
the ability to serve a mixture of both single-ended and differential sources with a single AD 1362 by dynamically switching the
input mode control.
DGND
+sv
+1SV
-16V
AGND
3
Multiplexer channel address inputs are interfaced through a
level-triggered ("transparent") input register. With a Logic" I"
at the Latch Select input, the address signals feed through the .
register to directly select the appropriate input channel. This
address iuformation can be held in the register by placing a
Logic "0" on the Latch Select input. Internal logic monitors the
status of the Single-Ended/Differential Mode input and
addresses the multiplexers accordingly.
A differential amplifier buffers the multiplexer outputs while
providing high input impedance in both differential and singleended modes.
The sample-and-hold is a high speed device that can also function as a gated opemtional amplifier. Its uncommitted differential inputs allow it to serve a second role as the output subtractor in the differential amplifier. A Logic "1" on the Sampleand-Hold Command input will cause the sample-and-hold to
"freeze" the analog signal while the ADC performs the conversion. Normally the Sample-and-Hold Command is connected to
the ADC Status output which is at Logic "I" during conversion
and Logic "0" between conversions. For slowly changing
inputs, throughput speed may be increased by grounding the
Sample-and-Hold Comtnand input instead of connecting it to
the ADC status.
The output buffer is a high speed amplifier whose output
impedance remains low and constant at high frequencies. Therefore, the AD1362 tnay drive a fast, unbuffered, precision ADC
without loss of accuracy.
SINGLEIOIFF
CONTROl
AD1362 Block Diagram
THEORY OF OPERATION
Concept
The AD1362 is intended to be used in conjunction with a high
speed, precision analog-to-digital converter to form a complete
data acquisition system (DAS). Figure 1 shows a general
AD1362 with ADC DAS application.
By dividing the data acquisition task into two sections, several
important advantages are realized. Performance of each design is
optimized for its specific function. Production yields are
increased thus decreasing costs. Furthermore, the standard configuration packages plug into standard sockets and are easier to
handle than larger packages with higher pin counts.
ANALOG·TO·DIGITAL
CONVERTER
~ MSBl
B3
B4
as
B6
B7
B8
as
810
BI1
B12 LSB
STATUS
, AE
A2 AI AU
/
CHANNEL
SELECT
CONVERT START
FigurB 1. AD1362 with ADC as a ComplBtB Data Acquisition 'SystBm
9-68 DA TA ACQUISITION SUBSYSTEMS
~
!:
~
J
AD1362
System Timing
Figure 2 is a timing diagram for the AD 1362 connected as
shown in Figure I and operating at maximum conversion rate.
The ADC is assumed to be a conventional 12-bit type such as
the ADS73 or AD ADC80.
NOTE
Valid Output Data
Not all ADCs have all data bits available when Status indicates
that the conversion is complete. Some successive approximation
ADCs must have a Status delay built in or the final data bit will
lag Status. This will result in two problems:
1. The sample-and-hold will return to Sample, disturbing the
analog input to the ADC as it is attempting to convert the
least significant bit. This may result in an error.
2. If the falling edge of Status is being used to load the data
into a register, the least significant bit will not be valid when
loaded.
ADDRESS
LATCH
CONVERT
COMMAND
STATUS
-I1t"~ :~:
STATE DOESN'T MATTER
~ MIN CONY COMMAND lADe)
II
(SAMPLE·HOLD)
GATED CLOCK
Figure 2. DAS Timing Diagram
The normal sequence of events is as follows:
1. The appropriate Channel Select Address is latched into the
address register. Time is allowed for the multiplexers to
settle.
2. A Conven Stan command is issued to the ADC which, in
response, indicates that it is "busy" by placing a Logic "1"
on its Status Line.
3. The ADC Status controls the sample-and-hold. When the
ADC is "busy," the sample-and-hold is in the Hold mode.
4. The ADC goes into its conversion routine. Since the sampleand-hold is holding the proper analog value, the address may
be updated during conversion. Thus multiplexer settling time
can coincide with conversion and need not affect throughput
rate.
5. The ADC indicates completion of its conversion by returning
Status to Logic "0." The sample-and-hold returns to the
Sample mode.
6. If the input signal has changed full scale (different channels
may have widely-varying data), the sampre-and-hold will typically require 10 microseconds to "acquire" the next input to
sufficient accuracy for 12-bit conversion.
After allowing a suitable interval for the sample-and-hold to stabilize at its new value, another Convert Start command may be
issued to the ADC.
An external delay or use of an ADC with a valid Status output
is necessary to prevent this problem.
Single-EndedlDifferential Mode Control
The AD 1362 features an internal analog switch that configures
the Analog Input Section in either a 16-channel single-ended or
8-channel differential mode. This switch is controlled by a TTL
logic input applied to Pin I:
"0": Single-Ended (16 channels)
"1": Differential (8 channels)
When in the differential mode, a differential source may be
applied between corresponding "High" and "Low" analog input
channels.
It is possible to mix SE and DIFF inputs by using the mode
control to command the appropriate mode. In this case, four
microseconds must be allowed for the output to settle to within
±0.01% of its final value, but if the mode is switched concurrent with changing the channel address, no significant additional
delay is introduced. The effect of this delay may be eliminated
by changing modes while a conversion is in progress (with the
sample-and-hold in the "Hold" mode). When SE and DIFF
signals are being processed concurrently, the DIFF signals must
be applied between corresponding "High" and "Low" analog
input channels. Another application of this feature is the capability of measuring 16 sources individually and/or measuring
differences between pairs of those sources.
Input Channel Addressing
Table I is the truth table for input channel addressing in both
the single-ended and differential modes. The 16 single-ended
channels may be addressed by applying the corresponding digital number to the four Channel Select address bits, AE, AO, AI,
A2 (Pins 28-31). In the differential mode, the eight channels are
addressed by applying the appropriate digital code to AO, AI,
and A2; AE must be enabled with a Logic "1." Internal logic
monitors the status of the SEIDIFF Mode input and addresses
the multiplexers singularly or in pairs as required.
DATA ACQUISITION SUBSYSTEMS
~69
9
ADDUSS
ON CHANNEL
AE
A2
Al
AD
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
I
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Single Ended
Differential
"Hi" "Lo"
0
1
2
3
4
5
.6
7
8
9
10
11
12
13
14
15
None
None
None
None
None
None
None
None
Analog Input Section Offset Adjust Circuit
Although the offset voltage of the AD1362 may be adjusted,
that adjustment is nortnally performed at the ADC. In some
special applications, however, it may be helpful to adjust the
offset of the Data Acquisition System. An example of such a
case would be if the input signals were small «IOmV) relative
to AD 1362 offset and gain errors. To adjust the offset of the
AD1362, the circuit shown in Figure 3 is recommended.
ADl362
0
1
2
3
4
5
6
0
1
2
3
5
5
6
7
7
OUTPUT
TOV+ANALOG
(+15VI
Table I. Input Channel Addressing Truth Table
When the channel address is changed, six microseconds must be
allowed for the AD1362 to settle to within ±0.01 % ofits final
output (including settling times of all elements in the signal
path). The effect of this delay may be eliminated by performing
the address change while a conversion is in progress (with the
sample-and-hold in the "Hold" mode).
Input Channel Address Latch
The AD1362is equipped with a latch for the input Channel
Select address bits. If the Latch Select pin is at Logic "I,"
input channel select address information is passed through to
the multiplexers. A Logic "0" "freezes" the input channel
address present at the inputs at the "1"-to-"O" transition (leveltriggered).
This feature is useful when input channel address information is
provided from an address, data or control bus that may be
required to service many devices. The ability to latch an address
is helpful whenever the user has no control of when address
information may change.
Sample-and-Hold Mode Control
The Sample-and-Hold Mode Control input is normally
connected to the Status output from an analog to digital converter. When a conversion is initiated by applying a Convert
Start command to the ADC, Status goes to Logic" 1" putting
the sample-and-hold into the "Hold" mode. This "freezes" the
information to be digitized for the period of conversion. When
the conversion is complete, Status returns to Logic "0" and the
sample-and·hold returns to the "Sample" mode. Eighteen
microseconds must be allowed for the sample-and-hold to
acquire ("catch up" to) the analog input to within ±0.01% of
the final value before a new Convert Start command is issued.
The purpose of a sample-and-hold is to "stop" fast changing
input signals long enough to be converted. In this applicataion,
it also allows the user to change channels andlor SEIDIFF mode
while a conversion is in progress thus eliminating the effects of
multiplexer, analog switch and differential amplifier settling
times. If maximum throughput rate is required for slowly
changing signals, the Sample-and-Hold Mode Control may be
wired to ground (Logic "0") rather than to ADC Status thus
leaving the sample-and-hold in a continuous Sample mode.
9-70 DATA ACQUISITION SUBSYSTEMS
Figure 3. AD1362 Offset Voltage Adjustment
Under normal conditions, all calibration is performed at the
ADC Section.
Other Considerations
Grounding: Analog and digital signal grounds should be kept
separate where possible to prevent digital signals from flowing in
the analog ground circuit and inducing spurious analog signal
noise. Analog Ground and Digital Ground are not connected
internally; these pins must be connected externally for the system to operate properly. Preferably, this connection is made at
only one point, as close to the AD1362 as possible. The case is
connected internally ·to Digital Ground to provide good electrostatic shielding. If the grounds are not tied common on the same
card with the AD1362, the digital and analog grounds should be
connected locally with back-to-back general-purpose diodes as
shown in Figure 4. This will protect the AD1362 from possible
damage caused by voltages in excess of ± 1 volt between the
ground systems which could occur if the key grounding card
should be removed from the overall system. The device will
operate properly with as much as ±200mV between grounds;
however, this difference will be reflected directly as an input
offset voltage.
AD1362
DGNDl
TO
CARD
CONNECTOR
AGND
ADC
DGNDI
AGND
ilN914
OR
EQUIVALENT
Figure 4. Ground-Fault Protection Diodes
AD1362
Power Supply Bypassing: The ± IsV and +SV power leads
shoula be capacitively bypassed to Analog Ground and Digital
Ground respectively for optimum device performance. One
microfarad tantalum types are recommended; these capacitors
should be located close to the system. It is not necessary to
shunt these capacitors with disk capacitors to provide additional
high frequency power supply d!=Coupling since each power lead
is bypassed internally with a 0.039jJ.F ceramic capacitor.
Interfacing to Popular Analog to Digital CODverters
The AD 1362 has been designed to interface directly to most
analog to digital converters; often no additional components are
required and only two interconnections must be made. The
direct interface requirements for the ADC are as follows:
1. The ADC Status output must be positive-true Logic ("I"
during conversion).
2. Transition from "0" to "I" must occur at least 200ns before
the most significant bit decision is made (successive approximation ADC) or before input integration starts (integrating
type ADC).
3. Status must not return to "0" before the LSB decision is
made.
Complete system throughput performance is determined by
combining the worst-case specifications of the AD 1362 and the
ADC. If guaranteed system performance is required, the AD363
and AD364 are recommended. The AD363 includes an AD1362
and an ADs72 12-bit, 2s-microsecond precision ADC. The
AD364 consists of an AD1362 and an ADs74 12-bit, microprocessor compatible, low cost ADC. Each is specified as a
complete, two-package system.
Figure Sa shows the AD1362 driving an AD ADC80. The
AD ADC80 is a 12-bit, 2s-microsecond, low cost ADC that
meets all of the requirements listed above. Throughput rate is
typically 30kHz with no missing codes over the operating temperature range.
Figure sb shows a lO-bit application based on the AD1362 and
the ADs73, a complete low cost 10-bit, 2s-microsecond ADC.
In this case, one of the above requirements is not met:
1. DR (DATA READY), as Status, is positive-true, but ...
2. DR does not indicate that a conversion is in progress until
1. sjJ.s after conversion starts.
The gating provided by UI allows the applied convert command
(CC) to initiate input hold at the AD1362. CC must last for
more than I.sjJ.s so that DR may then assume control of Hold.
4. If Status is being used to latch output data, it must not
return to Logic "0" until all output data bits are valid and
available.
DC POWER
DC POWER
DATA
BITS
OUT
(101
ANALOG
INPUTS
(181
SAMPLE/HOLD
OATA
BITS
OUT
(121
ANALOG
INPUTS
1181
CONV
INPUT
CHANNEL
SELECT
(4)
CHANNEL
SELECT
LATCH
1/474LS32
Jl
INPUT
CHANNEL
SELECT
141
CHANNEL
SELECT
LATCH
CONVERT
START
OATA STROBE
{TO OUTPUT
REGISTERI
-r-1.... 1.s,..
..:J I:: MIN
DATASTRoaE
~-------_ ITO OUTPUT
REGISTER)
a. 12-8it DAS Using AD 1362 and AD ADC80
b. 10-8it Using AD1362 and AD573
Figure 5. Data Acquisition Systsems Based on the AD1362 and Popular ADCs
DA TA ACQUISITION SUBSYSTEMS
~71
II
ANALOG
co~¥mo-
______________
ANALOG
INPUTS
co~mi
0-_ _ _ _ _ _ _ _ _ _ _ _ _ _--1
Figure 6. High Speed Data Acquisition Systems Based on AD1362 and Fast ADCs.
AD1362 ORDERING GUIDE
Model
AD1362KD
AD1362SD
AD1362SD/883B
Specification
Temperature Range
Max Gain
TC
Package
Options*
o to +70·C
±4ppml"C
±2ppml"C
±2ppml"C
DH-32E
DH-32E
DH-32E
-55°C to +12S·C
-SS·C to + 125°C
·See Section 14 for package outline information.
9-72 DATA ACQUISITION SUBSYSTEMS
~
-
o
~
:
:
~
O
______________---J
C
INPUTS
~ANALOG
WDEVICES
FEATURES
Complete with High Accuracy Sample/Hold and
AID Converter
Differential Nonlinearity: :!: 0.002% FSR max
IDAS1153)
Nonlinearity: DAS1152: :!:0.005% FSR max
DAS1153: :!:0.003% FSR max
Low Differential Nonlinearity T.C.: :!:2ppmfC max
High Throughput Rate: 25kHz min IDAS1152)
High Feedthrough Rejection: -96dB
Byte-Selectable Tri-State Buffered Outputs
Internal Gain & Offset Potentiometers
Improved Second Source to AID/AIM 824 and
AID/AIM 825 Modules
APPLICATIONS
Process Control Data Acquisition
Automated Test Equipment
Seismic Data Acquisition
Nuclear Instrumentation
Medical Instrumentation
Robotics
GENERAL DESCRIPTION
The DAS1l52IDAS1l53 are 14-/15-bit sampling analog-to-digital
converters having a maximum throughput rate of 25kHz/20kHz.
They provide high accuracy, high stability, and functional
completeness all in a 2" x 4" x 0.44" metal case.
Guaranteed high accuracy system performance such as nonlinearity
of ±0.OO5% FSR (DAS1l52)/±0.OO3% FSR (DAS1l53) and
differential nonlinearity of ±0.OO3% FSR (DAS1l52)/±0.002%
FSR (DAS1l53) are provided. Guaranteed stability such as
differential nonlinearity T.C. of ± 2ppmfC(DASl153) maximum,
zero T.C. of :!:80",VfC maximum, gain T. C. of ±8ppmfC
maximum and power supply sensitivity of ±O.OOl% FSRI% Vs
are also provided by the DAS1l521DAS1l53.
14-Bit &15-Bit Sampling
Analog-to-Digital Converters
DASl152/DASl153 I
DAS1l521DAS1l53 FUNCTIONAL BLOCK DIAGRAM
I----~REF OUT
HI ENABLE
{
,
ANALOG
INPUT
MSB
MSB
BIT 2
:
BIT 3
BI. .
BIT 5
BIT 6
BIT 7
SIH OUTPUT~-----,
LO ENABLE
°SlH INPUT
SlH CONTROL
L...J--"1-....I\arr 8
BIT 9
TRIBIT 10
STATE
BUFFERS
BIT"
BIT 12
BIT 13
BIT 14 (LSB FOR DA51,521
L _ _ _ _ -'r-t_ _~-..BIT 15 ILSB fOR DA51153i
+SV
ANALOG
DIGITAL GND
GNO
0S/H INPUT IS THE ANALOG SIGNAL INPUT IF TtlE
INTl:RNAL SAMPLEMOLD AMPUFIER IS USED.
The DAS1l521DAS1l53 make extensive use of both integrated
circuit and thin film components to obtain their excellent
performance, small size, and low cost. The devices contain a
precision samplelhold amplifier, high accuracy 14-/15-bit analogto-digital converter, tri-state output buffers, internal gain and
offset trim potentiometers, and power supply bypass capacitors
(as shown in Figure I).
Four analog input voltage ranges are selectable via user pin
programming: Oto +5V,Oto +lOV, ±5V, and ±lOV. Unipolar coding is provided in true binary format with bipolar
coding displayed in offset binary and two's complement.
Tri-state buffers provide easy interface to bus structured
applications.
DATA ACQUISITION SUBSYSTEMS 9-73
I
SPECIFICATIONS
(fP:aI @ + 25"1: unless oth8IWise noI8d)
MODEL
DAS1l52
DAS1l53
RESOLUTION
14 Bits
IS Bit.
25kHz min
20kHz min
44",. max
S",max
DYNAMIC PERFORMANCE
Throughput Rate
Conversion Time
3S",ma.
4",max
StH Acquisition Time
StH Apenure Delay
StH Aperture Uncenainty
Feedthrough Rejection'
Droop Rate
-%dB
O.OS",Vt",. (0. I",VI",. max)
Dielectric Absorption Error
± 0.005% oflnput Voltage Change
ACCURACY
Integral Nonlinearity'
Differential Nonlinearity
No Missing Codes
±3aNoise(StHpiusAlD)
± 3a Noise(AlD)
GainT.C.
ZeroT.C.
Power Supply Sensitivity
ANALOG INPUT
Voltage Range
Bipolar
Unipolar
ADC Input Impedance 0 to +SV
Oto + lOY, ±5V
±IOV
SIH Input Impedance
SIHControl
Low Enable, High Enable
DIGITAL OUTPUTS
Parallel Data Output.
Unipolar
Bipolar
Output Drive
Starus
Output Drive
INTERNAL REFERENCE VOLTAGE
External Load Current (Rated Perfortnance)
Temperature Stability
POWER REQUIREMENTS
Rated Voltage.
Operating VoltageS'
Supply Current Drain ± 15V
+SV
TEMPERATURE RANGE
Specified
Operatiug
Storage
Relative Humidity
Shielding
SIZE
NONCONDUCTlVE LABEL
In.
,
_
..021102.11
METAL CASE--,
± O.OOS% FSR' max
±0.003%FSR'max
Guaranteed
7S",Vrms
SO",Vrms
±0.003%FSR'max
± 0.002% FSR' max
..
MS'
.
01
.....
± 2ppmf'C max
±8ppml'Cmax
±30f,LVf'Ctyp, ±80JLVf'Cmax
±O.OOI%FSR'I%V,
;~~
TOP VIEW
"fOR MOOEL DAS''153 _ BIT 15 1L881.
"FOIiiiiOi)iiLllASnU_Rlr'4tLSSI.
CASE 18 NOT HUlMEl'lCAU. Y sP.LED
±SV, ± lOY
010 +SV,Oto + 10V
2.5k!)
Sk!)
10.0k!)
100MllISpF
DIGITAL INPUTS
Convert Command4
C
SOn.
STABILITY
Differential Nonlinearity T .C.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
ITTL Load, Positive Pulse
Negative Edge Triggered
HOLD = Logic 0
SAMPLE = Lug;c I
ENABLE = LositO
Binary
Offset Binary. Z'sComplement
2TTLLoad.
Logic U I" During Conversion
2TTLLoad.
+lOV,±O.3%
2mAmax
±SppmfCmax
±15V(±3%), +5V(±S%)
±12Vto+I7V,+4.7SVto+S.25V
±37mA
•
SOmA
Oto + 7O"C
- 2S'C to + 8S'C
-25'Cto + 85'C
Meet. MIL-STD-202E, Method 103B •
Electrostatic (RFI) 6 Side.,
•
Electromagnetic (EM!) S Sides
2"
x 4" x 0.44" Metal Package
NOTBS
"SpecifICations same as DASI152
'Measured in hold mode. input 20V pk-pk (~ 10kHz.
lW'orst-case summation of SIH and AID nonlinearity errors.
JpSR means FuU Scaie Rlnac.
~ connectiDJ the Convert Command and the SIH control terminals together. the pulse width must be long enough few the SIR
amplifter to acquire the input signal to the required lICturac:y 4".s (max. DASlIS2)1Sp,s (max. DASIIS3). If the AID convener
is only used. the Ccmve:rt Command pUlse width should be lOOns min (see Figure 2).
5Jf only the ADC portion is 1ISed. the operatiaJ power supply voItaJe can be maintained at ~ I2V to ~ 17V. But if the SIH sectioa is
requited. tbeoperatiDs: voltage must be: ~ntaincd at ±ISV (±3%) or the SIR input voltqc must be limited to -7V
to + IOV few a ± 12V supply voltaIC.
~mended Power Supply: AnaIos Devic:u Model 923.
Speci.fu:ations subject to change without notice.
9-74 DATA ACQUISITION SUBSYSTEMS
-11-•., ....., ....
Applying the DASl152/DASl153
OPERATION
TIMING DIAGRAM
The DAS1l52/DAS1153 are functionally complete data acquisition
subsystems being fully characterized as such. All the necessary
data acquisition and microprocessor interface elements are
provided internal to these devices. Accuracy and performance
criteria are tested and specified for the entire system. Thus,
design time and associated high accuracy problems are minimized
because layout and component optimization have already been
performed.
The timing diagram for the DASllS2IDASllS3 is illustrated in
Figure 3. This figure also includes the sample/hold amplifier
acquisition time.
For operation, the only connections necessary to the DAS1l52/
DASl153 are the ± 15V and + 5V power supplies, analog input
signal, trigger pulse, and the HI-ENABLE/LO-ENABLE tristate controls. Analog input and digital output programming are
user selectable via external jumper connections.
ANALOG INPUT SECTION
The analog input can be applied to just the AID converter or to
the internal samplelhold amplifier ahead of the A/D converter.
When using just the AID converter, apply the analog input per
the voltage range pin programming shown in Table I. When
using the sample/hold amplifier in conjunction with A/D converter, apply the analog input to the SIR INPUT terminal and
connect the S/H OUTPUT terminal to the appropriate A/D
converter analog input.
Analog Voltage
Input
Range
Oro +SV
Connect
Analog Common
To
Connect
V.N or SIH Out
To
Conncet
Ref Out
To
ANA IN I,
ANA IN 2,
ANA IN 3
Ground
NC'
Oro + 10V
ANAIN2
ANAIN3
Ground
ANA IN I
NC'
±SV
ANA IN I
Ground,
ANAIN3
ANAIN2
If the sample/hold amplifier is required, the TRIGGER input
and S/H CONTROL terminal can be tied together providing
only one conversion control signal. When the trigger pulse goes
high, it places the sample/hold amplifier in the sample mode
allowing it to acquire the present input signal. The trigger pulse
must remain high for a minimum of 411-s (DASllS2)/SlI-s
(DASII53) to insure accuracy is attained. If the sample/hold
amplifier is not used, the trigger pulse needs to be only lOOns
(min) in length to satisfy the A/D converter trigger requirements.
At the falling edge of the trigger pulse, the sample/hold
amplifier is placed in the hold mode, the A/D conversion
begins, and all internal logic is reset. Once the conversion
process is initiated, it cannot be retriggered until after the end
of conversion.
With this negative edge of the trigger pulse the MSB is set low
with the remaining digital outputs set to logic high state, and
the status line is set high and remains high through the full
conversion cycle. During conversion each bit, starting with the
MSB, is sequentially switched low at the rising edge of the
internal clock. The DAC output is then compared to the analog
input and the bit decision is made. Each comparison lasts one
clock cycle with the complete 14-/15-bit conversion taking 3511-s/
44l1-s maximum for the DASllS2IDASllS3 respectively. At this
time, the STATUS line goes low signifying that the conversion
is complete. For microprocessor bus applications, the digital
output can now be applied to the data bus by enabling the tristate buffers. For maximum data throughput, the digital output
data should be read while the sampleJhold amplifier is acquiring
the new analog input signal.
TRIGGER!
±IOV
Ground,
ANA IN I
ANAIN3
SIH CONTROL
ANAIN2
-No Connection
Table I. Analog Input Pin Programming
r----CONNECT
I
FOR
REF oUT
+1OV
GAIN
REFERENCE
ADJUST
0
-FS
-,-----------
5tH OUTPUT-FS
0-
nnnn
nnn
W W 4T-1 w W L...-
I
EOC
~35P.S
MAX{t'~
44~. MAX (D:~m~:-L-
MSB
---lJ
BIT 2
ANA IN 1
IL ____ _
ANA IN 2
~
ANA IN 3
f
ANALOG
INPUT
RANGE
SELECTION
f--
(LSB
14115
---,..,
~s
J L.J
I
I
I
~[ ~lS11521==]
BIT
AID
CONVERTER
SlH CONTROL
I
I
I
I
s~
1
Ss---, VIIIfI1f)
LW#h
1
NOTES
SIH OUTPUT
SIH INPUT
ss
BIT3----~S
ADJUST
I~~~N
-I
INTERNAL
CLOCK ----..I W
,OFFSET
I
,
-:===========
+FS~
Errors due to source loading are eliminated since the sample/hold
amplifier is a high-impedance unity-gain amplifier. High
feedthrough rejection is provided for either single-channel or
multichannel applications. Feedthrough rejection can be
optimized, in multichannel applications, by changing channels
at the rising or falling edge of the SIR control pulse.
I
I
I
: _ _ _ _ _ _ _ _ _ __
:1j - :: - - - - - - - - - - -
+FS
INPUT
SIGNAL
n
W~ 1. Output Data Valid.
I SAMPWHOlD}J
l AMPUFIER
I
*
2. If SIH Control and Trigger are tied together, Pulse Width
must be 4".$ (DAS1152)I5p.s (DAS1153) min to allow the S/H'
Amplifier to acquire the Input Signal. If the ADC is onlv
'--
Figure 2. Analog Input Block Diagram
used, the Trigger Pulse must be 100n$ min.
Figure 3. DAS11521DAS1153 Timing Diagram
DA TA ACQUISITION SUBSYSTEMS 9-75
II
GAIN AND OFFSET ADJUSTMENT
The DAS1152/DAS1153 contain internal.gain and offset
adjustment potentiometers. Each potentiometer has ample
adjustment range so that gain and offset errors can be trimmed
to zero.
Since offset calibration is not affected by changes in gain
calibration, it should be performed prior to gain calibration.
Proper gain and offset calibration requires great care and the
use of extremely sensitive and accurate reference instruments.
The voltage standard used as a signal source must be very stable
and be capable of being set to within ± 1I10LSB of the desired
value at any point within its range.
NOMINAL BIPOLAR INPUT·OUTPUT RELATIONSHIPS
Oto +SVRaage
DAS1lS2
+4.99969V
+2.S0000V
+0.62S00V
+0.0003V
+o.oooov
For the ± 5V bipolar range set the input voltage precisely to
+3051LV for the DAS1l52 and + 153ILV for the DAS1l53. For
a ± lOY bipolar range set the input voltage precisely to + 6101LV
for the DAS1152 and +3051LV for the DAS1l53. Adjust the
zero potentiometer until the offset binary coded units are just
on the verge of switching from 000 ........ 000 to 000 ........001
and the iwo's complement coded units are just on the verge of
switching from 100 ........ 000 to 100 ........ 001.
GAIN CALIBRATION
Set the input voltage precisely to +9.99909V (DAS1152)1
+9.99954V (DAS1153) for the 0 to + 10V units, +4.99954V
(DAS1152)1 + 4.99977V (DAS1153) for 0 to + 5V units,
+9.99817V (DAS1152)1 + 9.99909V (DAS1153) for ± lOV
units, or + 4. 99909V (DAS1152)1 + 4.99954V (DAS1153) for
± 5V units. Note that these values are I 112LSBs less than
nominal full scale. Adjust the gain potentiometer until binary
and offset binary coded units are just on the verge of switching
from 11 ..... 10 to 11.. ... 11 and two's complement coded units
are just on the verge of switching from 011.. ... 10 to 011 ..•.. 11.
DAS1l52IDAS1l53 INPUT/OUTPUT RELATIONSHIPS
The DAS1152/DAS1l53 produces a true binary coded output
when configured as a unipolar device. Configured as a bipolar
device, it can produce either offset binary or two's complement
output codes. The most significant bit (MSB) is used to obtain
the binary and offset binary codes while (MSB) is used to obtain
two's complement coding. Table II shows the DAS1152/DAS1153
unipolar analog input/digital output relationships. Tables III
and IV show the DAS1152/DAS1153 bipolar analog input/digital
output relationships.
DASllS2
DAS1l53
+9.99939V
+9.99969V
+s.oooov
+s.ooooov
+I.ZS000V
+O.OOO6V
+O.OOOOV
+ I.2S000V
+0.0003V
+O.OOOOV
DIGITAL OUTPUT
Bin.ryCode
DAS1l52
DAS1l53
II III III III III
III III III III III
10 000 000 000 000
100 000 000 000 000
00 100 000 000 000
001 000 000 000 000
00 000 000 000 001
000 000 000 000 00 I
00 000 000 000 000
000 000 000 000 000
OFFSET CALIBRATION
For a 0 to + lOY unipolar range set the input voltage precisely
to + 305ILV for the DASI152 and + 153ILV for the DASIl53.
For a 0 to + 5V unipolar range set the input to + 1531LV for the
DAS1152 and + 76ILV for the DAS1153. Then adjust the zero
potentiometer until the converter is just on the verge of
switching from 000........ 000 to 000 ........001.
ANALOG INPUT
Oto+l0VR.....
DASllS3
+4.99984V
+Z.SOOOOV
+0.6ZS00V
+O.OOOISV
+O.OOOOV
Table II. Unipolar Input/Output Relationships
Analo, Input
:tSVR.nge :tlOVRange
+4.99939V
+9.99878V
+Z.SOOOOV
+S.OOOOV
+O.OOO6IV
+0.00122V
+O.OOOOOV
+O.OOOOOV
-IO.OOOOOV
-S.OOOOOV
Dipt.1 Output
Offset Binary Code
Two's Complement Code
II III III III III
01 III 111111 III
II 000 000 000 000
01 000 000 000 000
10 000 000 000 001
00 000 000 000 001
10000000000000
00000000000000
00 000 000·000 000
10 000 000 000 000
Table 11/. DAS1152 Bipolar Input/Output Relationships
Analo,lnput
:t5VRange :tlOVR.....
+4.99969V
+9.99939V
+s.oooov
+2.S0000V
+0.0003V
+O.OOO6IV
+o.ooooov
-s.ooooov
+o.ooooov
-IO.OOOOOV
DiJjtal Output
Offset Binary Code
Two'.Comp1ementCode
111 III III III III
110 000 000 000 000
100 000 000 000 001
100 000 000 000 000
000 000 000 000 000
011 III III III III
010 000 000 000 000
000 000 000 000 001
000 000 000 000 000
100 000 000 000 000
Table IV. DAS1153 Bipolar Input/Output Relationships
TRI·STATE DIGITAL OUTPUT
The ADC digital outputs are provided in parallel format to the
output tri·state buffers. The output information can be applied
to a data bus in either a one-byte or a two-byte format by using
the HIGH BYTE ENABLE and LOW BYTE ENABLE
terminals. If the tri-state feature is not required, normal digital
outputs can be obtained by connecting the enable pins to
ground.
POWER SUPPLY AND GROUNDING CONNECTIONS
Although the analog power ground and the digital ground are
connected in the DAS1152/DAS1153, care must still be taken to
provide proper grounding due to the high accuracy nature of
these devices. Though only general guidelines can be given,
grounding should be arranged in such a manner as to avoid
ground loops and to minimize the coupling of voltage drops (on
the high current carrying logic supply ground) to the sensitive
analog circuit sections. Analog and digital grounds should
remain separated on the PC board and terminated at the
respective DAS1152/DAS1153 terminals.
No power supply decoupling.is required since, the DAS11521
DAS1l53, contain high quality tantalum capacitors on each of
the power supply inputs to ground.
9-76 DATA ACQUISITION SUBSYSTEMS
~ANALOG
WDEVICES
Low Power 14-Bit, l5-Bit & l6-Bit
Sampling Analog-to-Digital Converters
DASl157/DASl158/DASl159
I
FEATURES
Complete .wlth High Accuracy Sample/Hold and
AID Converter
.
Low Power Consumption: BmW max, Vs
:15V
Rated Performance: -25"C to +85"C
Low Nonlinearity (DASn58 and DASn59)
Differential: :0.0015% FSR max
Integral: :0.003'% FSR max
Differential T.C.: : 1pprnJ"C max
High Throughput Rete: 18kHz min
Byte-Selectable Tri-Stata Buffered Outputa
Intarnal Gain. Offset Potentiometers
Improved Second Source to AlD/A1M-834 and
AlD/AIM-836 Modules
DASllS7IDASllS8IDASllS9
FUNCTIONAL BLOCK DIAGRAM
=
APPUCAnONS
Seismic Data Acquisition
Portable Field Instrumentation
Autometed Test Equipment
Process Control Data Acquimion
Medical Instrumentation
GENERAL DESClllPTlON
The DASllS7IDASllS8IDASllS9 are 14-/IS-/16-bit sampling
analog-to-digital converters. They are ideally suited for use in
ponable and remote data acquisition equipment where low
power consumption (6SOmW maximum) and wide temperature
range ( - 2S"C to + SS"C rated performance) are required.
DASllS7IDASllSSIDASllS9 provide guaranteed high accuracy
and high stability system performance essential to medical,
analytical and process control equipment: differential nonlinearity
of ±O.OOIS% max and integral nonlinearity of ±O.OO3% max
(DASllSS and DASllS9); no missing codes guaranteed; gain
T.C. of ±SppmI"C max, zero T.C. of ±SOjl.vrc max and
differential nonlinearity T.C. of ± IppmI"C max.
t - - - - - - 9 R E F OUT
HI ENABLE
r---'-'--'--~Mn
:~Bzf~~~J,
INPUTOO{'2
ANA'
BIT 3
3
BIT •
BIT •
BIT •
SIH OUTPUT9----------,
BIT 7
LO ENABLE
eS/H INPUT
.......,
----~-"BIT
TAl·
"ATE
BUFfeRS
lac
TRIGGER
' - -_ _--.J
•
BIT.
BIT 10
BIT "
81T 12
BtT 13
BIT '4 ILSB FOR DAS11511
L _ _---' ·,,811 15 fLSB FOR DAS"511
+5V
DJGfTAL OND
-SIt! INPUT IS THE ANAlOG SIGNAL INPUT IF THE
INTERNAL SAMPLEIHOLD AWUF1ER 1& USED.
The DASllS7IDASll581DASllS9 make use of Analog Devices'
proprietary CMOS teclmology to achieve low power operation,
while utilizing the latest integrated circuit and thin-film components to achieve the highest level of performance and reliability.
As shown in Figure I, each device contains a precision samplelhold
amplifier, high accuracy I4-IIS-I16-bit analog-to-digital converter,
precision reference, CMOS tri-state output buffers (for direct Sbit or 16-bit bus interface), user accesSible gain and offset adjust
potentiometers, and power supply bypass capacitors, all in a
compact low profile 2" x 4" x 0.37S· metal case package. No
additional components are required for operation.
The wide dynamic range will enhance the performance of critical
measurements in gas and liquid chromatography, blood analyzers,
distributed data acquisition in factory automation and power
generating equipment, and in automatic test equipment.
DATA ACQUISITION SUBSYSTEMS 9-77
I
SPECIFICATIONS {tJpIcaI@ +25"C, v =:t:15Y, v
D-
l
MODEL
RESOLUTION
DYNAMIC PERFORMANCE
Throughput Rate
Coovetsion Time
SlH AcquilitioD Time
SlHApenur.Delay
S/H Aperture Uncertainty
DASU57
14 Bits
J8kHzmin
SO"smax
5JLSmax
2500.
Ins
Fcedthroush Rejection I
-9OdBmin
O.OSp.V/ti$,O.Ip.Vip.smax
±O.OOS%oflnpuIVoltageChange
DroopRate
Die1ectric: Absorption Error
ACCURACY
::!:O.OOS%FSR.J max
::!: 0.003% FSR 3 max
Guaranteed
0.0022% p'p(75;' V""s)
Integral Nonlincarity2
Differential Nonlinearity"
No MissingCocies
::t3aNoise(SlHplusAlD)
:t3aNoise(AlD)
0.OOI5%p'p(50~V nn.)
STABILITY
± 2ppmI"C max
± 8ppmf'C max
::t30p.VFCtyp, ±80p.VI"Crnax
Differential Nonlinearity T ,C.
GainT.C.
ZeroT.C.
Conversion Time T .C.
I'owc:r Supply Sensitivity
Wann-UpTime
::to.OS%I"C
::1:0.001% FSR]/% Vs
Less than I Minute
ANALOG INPUT
VoltaseRange
Bipolar
Unipolar"
AOC Inpullmpedana: 010 + SV
010 + IOV. ±SV
±IOV
SIH Input Impedance
±SV; ±IOV
Oto +SV,Oto + lOV
2.Sldl
Sid!
10kll
100MIlIISpF
DIGITALINPUTS
Positive Pulse. Neg. EdgeTrjgered.
5VCMOSCompat;ble
AfDTriacr 5
Logic:LeveJs
SAMPLE"" Logic I. TTL Compatible
SlHControl
Low Enable, Hish Enable'
ENABLE =u..;.O. CMOSfITL Compot;b\e
DIGITAL OUTPUTS
Parallel DataOUIPUIS
Unipolar
Bmary
Bipolar
Offset Binary, 2'sCompiement
ITTLLoads
Output Drive
EndofConversion
Output Drive
Logic "I" DuringConversioo
2TTLLoads
INTERNAL REFERENCE VOLTAGE
+ IOV,±O.3%
Ext,rnaI Load Current (Rated Performance) 2rnAmax
POWER REQUIREMENTS
Rated Voltages
Opentinl Voltages·,9
Supply Current Drain ± ISV
±15V(±3%). +5V(:!::5%)
± I2Vto ± 17V, +4.7SVto +5.2SV
±15mA
+5V
IOnIA
SOOmW' tyP. 650mW max
TotalPowerConsumption, V,,,,, ± 15V
TEMPERATURE RANGE
Rated Performance
Operating
-2S"<:lo +85"<:
-25"<: to +85"C
-40"<: to + 100"C
Meets MIL-STD·102E. Method 103B
Electrostatic(RFI) 6Sides
Electl'01lUl8Detic(EMI) S Side'll
St......
Relative Humidity
Shielding
r
SIZE
x 4" x 0.37S" Mew Package
NOTES
·SpecificationSIlllllCIl DASIIS7
*·SpecifIClIKms_uDASIISI
'Measured in bold mode, input 20V p.pk (it 10kHz.
~onl-caK" sulllllUllioD. of SIH and AID nonlinearity errors.
'FSR JnWII FuU ScaIt IWIF.
4Diffctcnlilll NontiDCariIy in lbe 0 to + SV inpul
is specified illS
±O.OO3% Iypklll forthc DASIIS7, DASIISB lind DASlIS9.
~n amnec:rinl cbc Triuct and the SIH conlrol terminals
toptbcr, the pulse width mUlt be lona eaouah ror the SIH
lIIII1p1iflU to .:quire the inpul .isnailO the required K(:uncy (S ....
mid). U the AID convener only ill ullCd, the Trigu puJsc width
mould be IlLS min (see Fipue 3).
ril .
+5Yunllssalllnilesplllillld)
DASU58
IS Bits
DASU59
16 Bits
··
··
··
··
··
·
·
···
·
··
··
··
··
··
··
·
···
·
··
··
·
··
·
···
·
···
0.003% FSR3 max
±O.OOIS%FSRJmax
±
±lppml"Cmax
··
···
....
·
··..
··
··
·
··
··
··
·
···
SeeNote7
SeeNole7
···
··
··
··
·
··
·
···
·
"Low Byle Enllble pin connections arc Bits I Ihrough IS; HiIh
Byte Enlblc pin con,*IWns arc MSii, MSB or Bit 16 and
Bib 2 Ihrouah 7.
'DASIIS9 UBipolar c:odilll is provided in III modified binary rormlll
(MSB complement) while bipolar codinJ i. two's compJemcnt
only. The MSB mUll be invcned ror binuy lind offaet binary
""'...
IWJ.en the SIH SCC:lion is required, - V5 mUlt be III least S VOlb
more nqltive IhIn tbe molt ncptivc anaiDS inpul voItqc lcxamplc:
Vs = ± 12V dc, Ihcrcfwe, maximum aaaJos: input is + 10 and
-7V).
~Ddcd Power Supply: Aaalo& Devica Mudd 9Zl.
SpcciflcalklnllUbjecttocblllnpwidtoutnoticc.
9-78 DATA ACQUISITION SUBSYSTEMS
OUTLINE DIMENSIONS
DImensions s/!own in inches and (mm).
rNOfWCONDUCTlVlLABfL
r...l
-r~8RAU
GOLO ......TEOIMtL4"'12CM!
J±_x
......
ij.I.HIU,IMIN
IT
SoI"MI!
I >0.
h='''''''~
'1.1I311••II)!Mlt
METAL CASE""""'I
1--",1127.11
l!.l!.
"""
....
........
IlL·"
... ::-
_. ,,
.....
~.~I5V
-'IV
ANA OND
..... .
. ..........
ANA IN I
flU OUT
.S::.
~,
... """",n
IllliNA8lI
iii
.T"n.dI
........
--i I-a.l 1:t.54) GRID
"fORMOOI!LIJAl,USJ_BlTMIUI8J
""FOR MODB. DAS1111 _ Iff I'll lUI'
T
[
"""fDA MODB. bAlUn_lIT "lUll
ASSBMIILY INSTRUCDONS
CAUTION: Tb;s IIIOduIe is DOl ......bodded _bIy II1II is
QOt benaetkaIly 1eaIed. Do DOt aubject to llIOlveal or water-. . .
,...... ..... --.u---wibfncliquidaor
_.~of
lIIIIYoccur
.......
perI\mIIIuxe""-l1111 _
duDIp.
__
..............
IItJ _ _ II1II _
oaIy _
...... by
boDd.
Applying the DASl157/DASl158/DASl159
OPERATION
For operation, the only connections necessary to the DASllS71
DASllS8IDASllS9 are the ± ISV and + SV power supplies,
analog input signal, trigger pulse, and the HI-ENABLElLOENABLE tri-state controls. Analog input and digital output
programming are user selectable via external jumper
connections.
Input voltage ranges are selectable via user pin programming: 0
to +SV, Oto + lOY, ±SV and ± lOY. Unipolar coding is provided
in true binsry format with bipolar coding displayed in offset
binsry and twO'S complement (DASllS7 and DASllS8). DASllS9
unipolar coding is provided in a modified binsry format (MSB
complement) while bipolar coding is two's complement only.
ANALOG INPUT SECTION
The analog input can be applied to just the AID converter or to
the internal samplelhold amplifier ahead of the AID converter.
When using just the AID converter, apply the analog input per
the voltage range pin programming shown in Table I. When
using the samplelhold amplifier in conjunction with AID converter, apply the analog input to the SIH INPUT terminal and
connect the SIH OUTPUT terminal to the appropriate AID
converter analog input.
Analog Voltage
Input
Range
010 +5V
Connect
VINor SIH Out
To
Connect
Analog Common
To
Connect
Ref Out
To
ANA IN I,
ANAIN2,
ANA IN 3
Ground
NC'
010 + lOY
ANAIN2
ANAIN3
Ground
ANA IN 1
NC'
±5V
ANA IN 1
Ground,
ANAIN3
ANAIN2
±IOV
ANAIN3
Ground,
ANA IN 1
ANAIN2
*NoConnection
Table I. Analog Input Pin Programming
r------
REF OUT
I
I
,
I CONNECT
I
ANA IN 1
I
ANA IN 2
I
1.-----
ANA IN 3
I
ANALOG
INPUT
RANGE
SEl.ECTION
-
TIMING DIAGRAM
The timing diagram for the DAS1l57/DASllS8IDASllS9 is
illustrated in Figure 3. This figure also includes the samplelhold
amplifier acquisition time.
If the samplelhold amplifier is required, the TRIGGER input
and SIH CONTROL terminal can be tied together providing
only one conversion control signal. When the trigger pulse goes
high, it places the samplelhold amplifier in the sample mode
allowing it to acquire the present input signal. The trigger pulse
must remain high for a minimum of SjJ.s to insure accuracy. If
the samplelhold amplifier is not used, the trigger pulse needs to
be I jJ.S (minimum) in 1ength to satisfy the AID convener trigger
requirements. At the falling edge of the trigger pulse, the sample!
hold amplifier is placed in the hold mode, all internal logic is
reset and the AID conversion begins. The conversion procesa
can be retriggered at any time, including during conversion.
With this negative edge of the trigger pulse, the MSB is set
high with the remaining digital outputs set to logic low state,
and the end of conversion is set high and remains high through
the full conversion cycle. During conversion each bit, starting
with the MSB, is sequentially switched high at the rising edge
of the internal clock. The DAC output is then compared to the
analog input and the bit decision is made. Each comparison
lasts one clock cycle with the complete 14-/IS-/I6-bit conversion
taking SOjJ.S maximum. At this time, the end of conversion line
•
goes low signifying that the conversion is complete. For microprocessor bus applications, the digital output can now be applied
to the data bus by ensbling the tri-state buffers. For maximum
data throughput, the digital output data should be read while
the samplelhold amplifier is acquiring the new analog input
signal.
TRIGGER!
S/H CONTROL
INPUT
SIGNAL
~
14..f15·/16·
BIT
AID
CONVERTER
\
SlH CONTROL
+FS:I--1-. . :jl:===========
-~ --:--------------------0
I
+FS~:
a-
EOC
~===========
-,
~50"S
H
MAX
, . . ~O~lput Dtotoo VoUd.
II SAMPLEIHOLD}J
AMPUFIER
I
r
S/H OUTPUT-FS
SlH OUTPUT
SlH INPUT
n ___________
I
OFFSET
ADJUST
FOR
I C:~~~N
GAIN
ADJUST
+IDV
REFERENCE
Errors due to source loading are eliminated since the samplelhold
amplifier is a high-impedance unity-gain amplifier. High feedthrough rejection is provided for either single-channel or multichannel applications. Feedthrough rejection can be optimized,
in multichannel applications, by changing channels at the rising
or falling edge of the SIH control pulse.
•
2. tf SiH Control end Trigger .re ned Together.
Pulse Width Must Be 5.... Min to Allow the
5/H Amplifier to Acquire the Input Signel. If
'--
Figure 2. Analog Input Block Diagram
the
AD~
is Only Used. the Trigger Pulse Must
Be 1p.s Min.
Figure 3. DAS11571DAS1158/DAS1159 Timing Diagram
DATA ACQUISITION SUBSYSTEMS 9-79
IDput Voltap-Output Code Relationships
GAIN AND QFFSET ADJUSTMENT
The DAS1157/l)AS1l581DAS1lS9 contain internal gain and
offset adjustment potentiometers. Each potentiometer has ample
adjustment range 59 that. gain and offset errors can be trimmed
Unipolar Input Voltaps
Dilital Output
Analog Input
to zero.
Oto +SVRange
Oto +lOVRange
Offset cah'bration is not affected by changes in gain ca1ibration,
and should be performed prior to gain ca1ibration. Proper gain
and offset ca1ibration requires great care and the use of extremely
sensitive and accurate reference instruments. The voltage standard
used as a signal source must be very stable and be capable of
being set to within ± I/IOLSB of the desired value at any point
within its range.
DAS 11 57
+4.99969V
+O.OOOOOV
+9.99939V
+O.OOOOOV
Binary Code
11 1111 1111 1111
00 0000 0000 0000
DAS1158
+4.99985V
+O.OOOOOV
+9.99969V
+O.OOOOOV
Binary Code
III 1111 1111 1111
000 0000 0000 0000
DAS1159
+4.99992V
+O.OOOOOV
+9.99985V
+O.OOOOOV
Modified Binary Code
0111 1111 1111 1111
1000 0000 0000.0000
OFFSET CALIBRATION
For a 0 to + 10V unipolar range, set the input voltage precisely
to + 305 ....V for the DAS1157, + 153....V for the DAS1l58 and
+ 76....V for the DASllS9. For a 0 to + 5V unipolar range, set
the inputto + 153....V for the DAS1157, + 76....V for the DAS1l58
and + 38....V for the DAS1159. Then adjust the zero potentiometer
until the converter is just on the verge of switching from
000...... 000 to 000......001 (DAS1157/DAS1158) or from
100........000 to 100........ 001 (DAS1159).
For the ± 5V bipolar range, set the input voltage precisely to
+305 ....V for the DAS1157, + 153....V for the DAS1158 and
+ 76 ....V for the DAS1159. For a ± 10V bipolar range, set the
input voltage precisely to +610....V for the DAS1157, +305 ....V
for the DAS1158 and + 153....V for the DAS1159. Adjust the
zero potentiometer until the offset binary coded units are just
on the verge of switching from 000........000 to 000........001
and the two's complement coded units are just on the verge of
switching from 100........ 000 to 100........001.
GAIN CALIBRATION
Set the input voltage precisely to +9.99909V (DAS1157)1
+9.99954V (DAS1158)1 + 9.99977V (DAS1159) for the 0 to
+ 10V units, +4.99954V (DAS1lS7)1+4.99977V (DAS1lS8)1
+4.99989V (DAS1159) for 0 to +5V units, +9.99817V
(DAS1157)1+9.99909V (DAS1l58)1 + 9.99954V (DAS1lS9) for
± 10V units, or + 4.99909V (DAS1157)1 +4.99954V (DAS1158)1
+4.99977V (DAS1159) for ±5V units. Note that these values
are 1 1/2LSBs less than nominal full scale. Adjust the gain
potentiometer until binary and offset binary coded units are just
on the verge of switching from 11 ..... 10 to 11 ..... 11 or modified
binary and two's complement coded units are just on the verge
of switching from 011 ..... 10 to 011.. ... 11.
DASllS7IDAS1l58lDASllS9 INPUT/OUTPUT
RELATIONSHIPS
The DAS1157IDAS1158 produces a true binary coded output
when configured as a unipolar device. Configured as a bipolar
device, it can produce either offset binary or two's complement
output codes. The most significant bit (MSB) is used to obtain
the binary and offset binary codes while (MSB) is used to obtain
two's complement coding. The DAS1159 produces a modified
binary coded output when configured as a unipolar device.
Configured as a bipolar device it can only produce two's complement output codes. The DAS1159 uses MSB to obtain the
modified binary and two's complement output codes; the DAS1159
does not have an MSB output. Table II shows the DAS1157/
DAS11581DAS1159 unipolar analog input/digital output relationships. Table III shows the DAS1157IDAS1l581DAS1l59
bipolar analog input/digital output relationships.
9-80 DATA ACQUISITION SUBSYSTEMS
Table II. Unipolar Input-Output Relationships
BipoIuID"'V~
D;,itaI Output
Ywo'sCompiem_Code
OIfselllbwyCode
"'sv .....
AaaIoaID'"
"'IOV .....
DAS!!S7
+4.99939V
+o.ooooov
-s.ooooov
+9.99878V
+o.ooooov
-IO.OOOOOV
II 1111·1111 1111
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
10 0000 0000 0000
DAS1lS8
+4.99969V
+o.ooooov
-s.ooooov
+9.99939V
+o.ooooov
-IO.OOOOOV
III 1111 llli Illl
100 0000 0000 0000
000 0000 0000 0000
011 1111 1111 llli
000 0000 0000 0000
100 0000 0000 0000
DASIl59
+4.9998SV
+o.ooooov
-S.OOOOOV
+9.99969V
+o.ooooov
-IO.OOOOOV
Olll llli 1111 1111
0000 0000 0000 0000
1000 0000 0000 0000
Table III. Bipolar Input-Output Relationships
TRI-STATE DIGITAL OUTPUT
The ADC digital outputs are provided in parallel format to the
output tri-state buffers. The output information can be applied
to a data bus in either a one-byte or a two-byte format by using
the HIGH BYTE ENABLE and LOW BYTE ENABLE terminals.
If the tri-state feature is not required, normal digital outputs
can be obtained by connecting the enable pins to ground.
POWER SUPPLY AND GROUNDING CONNECTIONS
No power supply decoupling is required since the DAS1157/
DAS1158IDAS1159 contain high quality tantalum capacitors on
each of the power supply inputs to ground.
The analog and digital grounds are internally connected in the
DAS11571DAS11581DAS1159. But in many applications, an
extemal connection between the digital ground pin and analog
ground pin is advisable for optimum performance.
DI~W~'8:'U:DS
, _ _ _ _ _ _ _ _ _ _ _,
•
l:~~~~
I
OIGITAL
POWER
SUPPLY
:
STAR-POiNT
OF
ANALOG
GROUNDS
a=1I
DASl157IDAS11581DAS1159
l
~----------)
ANALOG
POWER
SUPPLY
COMMON
COMMON
Figure 4. Typical Ground Layout for DAS 1157/DAS 1158/
DAS1159
Microcomputer 110 Boards
The RTl® Series consists of analog and digital input/output
boards that are compatible with all of the popular microcomputer bus standards including:
•
•
•
•
•
IBM PCIXT/AT*
IBM PS/2*, Micro Channel* Architecture
STDBus
VMEbus
MULTIBUS*
All boards are 100% bus compatible and are optimized for peak
performance on each bus. Different analogldigital conversion
speeds, resolution and choice of analog output and channel
expansion capability are available allowing customization of the
bus based solutions. They are cost effective and provide a con·
venient means to interface a computer to the real world.
SIGNAL CONDITIONERS
For data acquisition applications requiring signal conditioning
and transducer interface with high-voltage isolation, the 3B and
5B Series of signal conditioners or one of the analog signal conditioning panels can be connected directly to the R Tl Series
boards.
Both the 3B and 5B Series are unmatched in terms of isolation,
reliability and ease of use. The 3B Series interfaces to the widest
range of signals and is user configurable. The SB Series consists
of functionally complete, high performance, low cost signal conditioners. A family of multiplexed analog signal conditioning
panels offers an alternative for systems with high point counts
where single channel modularity is not required.
SOFTWARE
Many RTl Series boards are supported by MS-DOS* 110 driver
software that provides easy to use, high level calls and
commands for user written software programs for languages like
Microsoft* BASIC (Interpreted and Compiled), QuickBASIC,
C, Pascal, TURBO Pascal*, FORTRAN and MACRO
Assembler.
Popular menu-driven data acquisition application software
supports many of the RTl Series boards, including ASYST*,
LABTECH* NOTEBOOK, LABTECH CONTROL,
UnkeIScope*, SNAPSHOT STORAGE SCOPE*, Control EG*
and THE FIX*. These software packages make it easy to configure a complete solution using Analog Devices 110 and your
choice of computer.
RTI is a registered trademark of Analog Devices, Inc.
*ASYST is a trademark of ASYST Software Technologies, Inc.
Control EG is a trademark of Quinn-Curtis.
IBM PCIXT/AT, PS/2 and Micro Channel are trademarks of
International Business Machines Corporation.
LABTECH i. a registered trademark of Laboratory Technologies
Corporation.
MS·DOS and Microsoft are registered trademarks of Microsoft
Corporation.
MULTlBUS is a registered trademark of Intel Corporation.
SNAPSHOT STORAGE SCOPE is a trademark of HEM DATA
Corporation.
THE FIX is a trademark of Intellution, loc.
TURBO PASCAL is a trademark of Borland International Corp.
UnkelScope is a trademark of the Massachusetts Institute of
Technology.
Via a variety of optional backplanes and convenient ribbon
cabling to the RTI Series 1/0 Boards, signal conditioners bring
real-world signals into the computer, including millivoltage,
voltage, current, thermocouple, RTD, strain gage, LVDT and
frequency. For further information on signal conditioners, see
Linear Products Databook.
MICROCOMPUTER I/O BOARDS 10-1
~
Selection Guide
~
~
Microcomputer 1/0 Boards
c
8
IBM PClXT/AT COMPATmLE BOARDS
c::~
Analog
Input
Channels
Throughput
Resolution XT
AT
Other Analog
Input Features
RTI-SOO Analog Input
and Digital I/O
32SElI6D1
12 Bits
Direct Connection
to 3B/5B Signal
Conditioning
RTI-S02 Analog Output
N/A
~
~
0
III
~
~
Model
Function
RTI-SI5 Multifunction
AnaIogand
Digital I/O
32SEl16D1
RTI-SI7 Digital I/O
N/A
RTI-S20 Modular
Analog and
Digital I/O
Up to 64
Inputs
31kHz 27kHz
5SkHz 5SkHz
91kHz 5SkHz
Analog
Output
Channels
Resolution Digital I/O
N/A
4 (-4 Version)
S (-S Version) 12 Bits
12 Bits
12 Bits
31kHz 27kHz
5SkHz 5SkHz
91kHz 5SkHz
19kHz 19kHz
Direct Connection
to 3B/5B Signal
Conditioning
2
N/A
N/A
Supports Direct
Up to 16
Connection Up to
Outputs
4 Signal Conditioning Panels
STB-HL02, STB-TC,
STB-HL!, STB-Tel,
5B02
Other Features
Compabllle
S Digital Inputs
3 Counterrrimers PC/XT/AT
S Digital Outputs
12 Bits
12 Bits
N/A
Remote
Sensing
PC/XT/AT
S Digital Inputs
3 Counterrrimers PC/XT/AT
S Digital Outputs
Three S-Bit Ports
Interrupt on
Each Port
Change of .State.
Conflgurable as
Input or Output
Compatible to
Solid-State Relay
Modules
Three S-Bit Ports
PC/XT/AT
PC/XT/AT
Each Port Con-
flgurable as Input
or Output
RTI-S50 High-Resolution SD
Analog Input
16 Bits
15 Bits
14 Bits
N/A
50kHz
52kHz
55kHz
Extensive Triggering
N/A
N/A
256K On-Board
Sample Memory
AT
RTI-S60 High Speed
Simultaneous
Analog Input
12 Bits
S Bits
N/A
250kHz Extensive Triggering
330kHz Simultaneous SIH
N/A
N/A
256K On-Board
Sample Memory
AT
16SE
sm BUS COMPATmLE I/O BOARDS
smBUS
(NMOS)
Analog Devices
Part Number RTI·1226 RTI·1225
Board Type
Channel Capacity
Input
Input/Output
Output
Input
(Single Ended!
Differential)
Output
Input Resolution
10 Bits
12 Bits
Output Resolution
8 Bits
12 Bits
Additional Features
Programmable Gain Amplification
Single +5V Operation
4-20mA Output
Direct Sensor Interface
Thermocouples, RTDs
mM PC Software Compatible
•
1618
•
1618
RTI·1260 RTI·1262
•
•
•
•
RTI-l265 RTI·1266 RTI·1267 RTI·1270 RTI·1280 RTI·1281
•
•
•
•
32116
2
•
5mBUS
(CMOS)
64
•
•
•
•
•
•
•
•
--
-
•
•
•
•
--
•
•
-----
mM PS/2 MICROCHANNEL COMPATmLE HARDWARE
~
~
C
8
c:~
ill::Q
Channel Capacity
Analog Input
Analog Output
Digital I/O
AID Resolution (Bits)
DfA Resolution (Bits)
Acquisition Thruput
';:
0
tXI
~
~
C/)
f
III
RTI·204
RTI·205
8SE
8SE
2
8
12
8
19kHz
12
12
19kHz
•
16116
•
•
•
--
24
Digital
I/O
64
16
4
•
•
RTI·217
I 32
•
•
•
1618
•
•
•
•
RTI·1282 RTI·1287
•
1618
2
4 or 8
•
•
•
•
•
•
•
•
24
Digital
I/O
•
~
....
Selection Guide
~
~
Microcomputer liD Boards
c::
~
VMEbus COMPATmLE YO BOARDS
0
Analog Devices
Part Number
8
~';::
II)
~
~
Board Type
Channel Capacity
Input
Input/Output
Output
Input
(Single Ended!
Differential)
OutEut
Input Resolution
10 Bits
12 Bits
Output Resolution
8 Bits
12 Bits
Additional Features
Programmable Gain Amplification
Single +5V Operation
4-20mA Output
Direct Sensor Interface
Thermocouples, RTDs
MULTmus COMPATmLE YO BOARDS
Analog Devices
Part Number
VMEbus
RTI·600 RTI·602
Board Type
•
•
Channel Capacity
32116
4
•
•
•
•
•
•
Input
Input/Output
Output
Input
(Single Ended!
Differential)
Output
Input Resolution
10 Bits
12 Bits
Output Resolution
8 Bits
12 Bits
Additional Features
Programmable Gain Amplification
Single + 5V Operation
4-20mA Output
Direct Sensor Interfa.ce
Thermocouples, RTDs
MULTmUS
RTI·711 RTI·724 RTI·732
•
•
32116
4
•
•
•
•
•
•
32116
2
•
•
•
•
•
Application Specific Integrated Circuits
Analog Devices offers a full spectrum of capabilities in application
specific integrated circuits (ASICs). These chip-level systems
can implement designs with 12-bit accuracy and 16-bit resolution
that formerly required board-level solutions.
an 8-channel multiplexer, programmable-gain amplifier, sampleand-hold and l2-bit AID converter with internal voltage
reference.
AD75003 DATA ACQUISITION SYSTEM
Analog Devices can incorporate most of the functions of its
standard monolithic parts in full-custom and semicustom ICs.
Full-custom parts optimize performance and space requirements,
while cell-based semicustom parts reduce development time and
engineering expense. Development costs can be cut further by
tailoring a predefined system-on-a-chip known as a Linear System
Macro to your application.
Analog's experienced design engineers work with powerful computer-aided design tools to design and layout your circuit.
Design centers are currently in Massachusetts, California and
England.
Multiple locations for fabrication, assembly and testing ensure a
ready supply of production parts. Products can be processed in
full MIL-385IO certified facilities.
CH7
CHI
PROGIIAMUABLE GAIN
AMPLIFIER AND
SAMPLE AND HOLD
V, ....
VIIEFOUT
VD'
V..
ES
WIi
iiD
AGND
••
co
DESIGN EXAMPLES
Analog Devices has created a variety of customer-specific and
function-specific ASIC parts. Described here are two Linear
System Macros, a custom chipset and a semicustom chip.
AD75004 QUAD DAC
VAIifOUT
VflEF,"
Voun
07
01
D.
Voun
O.
0'
0'
0'
D.
V.""
V.'"
+12V
V..
·12V
V..
ANA LOa GROUND
AGND
DIGITAL GROUND
DONO
Derivative Circuits
The circuits outlined above can be modified to suit a specific
customer's application. One such device is a semicustom, seria1interface DAS. The AD75003 design was altered to have programmable gains of I to 20 instead of I to 16, and a serial UART
instead of an 8-bit parallel interface. In addition to the AD75003
functions, this part contains a precision instrumentation amplifier,
a programmable line-frequency notch filter, a 7-bit trim DAC
and a temperature sensor.
Modem Chipset
Library cells can be combined to form macro building blocks
for high speed modems. This two-chip design concept filters
and converts data to interface a digital signal processor with the
analog circuitry of a 9600-baud modem. On one chip, the received
signal passes through an antialiasing filter, sample-and-hold,
l2-bit AID converter, 8th-order digital filter and decimation.
On the other chip, transmit data is 8 x oversampled, then goes
to an 8th-order filter, a 12-bit DAC and an active reconstruction
filter.
HIGH SPEED MODEM CHIPSET
AD7S004 Quad DAC
This circuit contains four separate 12-bit D/A converters with
amplifiers for voltage output and an on-board reference. Doublebuffering latches interface with an 8-bit parallel bus and permit
updating of all four channels individually or simultaneously.
AD7S003 Data Acquisition System
This DAS converts analog signals on 8 input channels to l2-bit
values and interfaces via an 8-bit parallel bus. The chip integrates
APPLICA TION SPECIFIC ICs 11-1
Transversal Filter Element
This circuit implements five taps of a finite-impulse response
ftIter. Each tap comprises an 8-bit DAC and a multiplier, which
handle signals up to 40 MHz. A parallel interface sets the tap
weights.
TRANSVERSAL FILTER ELEMENT
The BiMOS II and Linear Compatible CMOS (LC2MOS) processes
combine bipolar and CMOS devices on one chip. Functional
density is an order of magnitude greater than previous mixed-signal
processes; over 20,000 devices can be placed on a single chip.
Bipolar transistors provide low noise, low offset input stages and
high power output stages. The CMOS devices offer high input
impedance, and make dense logic and good switches for data
converters, multiplexers and switched-capacitor ftIters. LC2 MOS
also provides a JFET for very low input noise.
The bipolar-CMOS processes operate on supply voltages ranging
from single + 5 volts to split ± IS V, with signal levels ranging
from single-ended + 3 V to ± 10 V. These processes are ideally
suited for applications in data acquisition, instrumentation,
industrial automation and telecommunications.
The High Voltage Switch (HVS) process provides quality analog
switches that can operate with supply voltages up to ± 22 volts.
It can combine switches and multiplexers with CMOS logic.
ANALOG
OUTPUT.
HIGH PERFORMANCE PROCESSES
Analog Devices' semicustom and custom circuits are fabricated
using the same high performance processes as our standard ICs.
These technologies include two mixed bipolar-CMOS processes,
a high voltage CMOS process and high speed and low power
bipolar processes. These processes can include thin-ftIm resistors
which may be laser trimmed for precise matching and stable
performance over a wide temperature range.
The Flash bipolar process makes high speed linear signal processing, data conversion and ECL logic functions on one chip.
Signal levels are ±4 volts with ±5 V supplies or up to + 10 V
with a + 12 V supply. Applications include disk-drive read/write
circuitry and high speed telecommunications equipment.
The Complementary Bipolar (CB) process features high speed
PNP and NPN devices for precision, low power linear applications.
It also offers low noise buried Zener references and dual-gate
JFETs. CB runs on + 5 V to ± IS V supplies.
The table below summarizes the processes available for designing
ASICs. Other processes in development will offer even higher
speed, denser logic and higher integration of analog and digital
functions.
ANALOG DEVICES HIGH-PERFORMANCE PROCESSES FOR ASICs
Process
Power
Signal
Features
BiMOSII
LC2MOS
HVS
Flash
CB
±12V
+5Vto ±15V
+5Vto ±22V
±5Vor + 12V
+5Vto ±15V
±8V
+3Vto ±IOV
+2Vto ±18V
±4Vor +10V
+2Vto ± lOY
Wide Variety of Precision Linear and Digital Functions
Wide Variety of Precision Linear and Digital Functions
High Voltage Switches, Muxes and Logic Functions
High Speed Linear and Digital Functions
High Speed, Low Power Linear Functions
11-2 APPLICA TION SPECIFIC ICs
CELL LIBRARIES
Ce1llibraries for the bipolar CMOS processes are described
below. These libraries are growing with the development of new
processes, macrocells and cells. Many new catalog parts will also
be available as cells. Your local sales office can give you current
information on the cell libraries and available Linear System
Macros.
Operational amplifiers are available in bipolar, JFET and CMOS
configurations. Representative bipolar op amp cells 'have performance characteristics similar to an AD OP-27 and a slewenhanced AD741. The LC2MOS process offers JFET op amps,
including an AD544 equivalent.
The following figure shows the standard design cycle which
begins with schematic entry. After logic and initial electrical
simulation, the designer uses the graphics editor to layout the
circuit. Parasitics and other data are extracted from the layout
and circuit operation is simulated again. Finally, the system
checks that the layout follows process design rules and matches
the schematic.
IC OESIGN WITH
COMMERCIAL CAD SYSTEM
Instrumentation amplifiers with performance comparable to the
AD521 and AD524 are available. Comparators suitable for 12-bitaccurate applications are available. Linear comparators have
response times down to 100 nanoseconds and strobed comparators
have setup/access times down to SO nanoseconds.
Digital-to-analog converters range in resolution from 8 to 14
bits, and include cells similar to the AD667 and AD1856. Analogto-digital converters vary from 8 to 12 bits in resolution, and
include cells equivalent to the AD7572 and AD674. One halfflash ADC cell converts to 8-bit accuracy in 500 nanoseconds,
and one successive approximation cell converts to 12 bits in
5 microseconds.
In addition to using these commercial CAD tools, Analog Devices
has developed a proprietary compiler for mixed-signal IC design,
called JANUS. By integrating all design functions into one
environment with a common database, JANUS reduces design
time by an order of magnitude.
Support cells include sample-and-hold amplifiers with performance
comparable to the AD585, low-voltage bandgap references comparable to the AD584 and low noise buried Zener references.
IC DESIGN WITH JANUS
PROPRIETARY CAD SYSTEM
RC active filters and programmable switched-capacitor filters
are available with specifications in these ranges:
Topology: all classical filter types
Frequency Range: 200Hz to 20kHz (switched-cap) or
100Hz tolMHz (RC)
Number of Sections: up to 10th-order (switched-cap)
or 4th-order (RC)
SignallNoise and THD: >72dB, compatible with
12-bit data acquisition.
I
Logic cells include gates, counters, registers, PLA, RAM and
ROM. Interface cells include 8-bit and 16-bit parallel 110 ports
and UARTs.
DESIGN AND LAYOUT
Analog Devices engineers will design your integrated circuit,
drawing on their years of experience and using powerful computeraided design (CAD) tools. These comprehensive CAD tools help
design, simulate and layout the circuit and aid in generating
test programs.
APPLICA TION SPECIFIC ICs 11-3
To speed schematic entry, the designer selects devices, cells and
macrocells from comprehensive menus. Device generators allow
the designer to specify devices for maximum performance and
minimum size. Analog, logic and functional simulators verify
the performance of individual cells and the overall chip design.
Placement and routing algorithms complete circuit layouts automatically, yet allow interaction with the designer to handle
special cases. When placing devices and cells, JANUS considers
thermal and electrical matching as well as die area. An expert
system optimizes routing to minimize interconnect length and
number of vias. Post-layout simulation comprehends the parasitics
of the final routing and is more accurate than the initial simulation.
Future goals for JANUS include automatically generating
programs for production trim and test of aruiIog/digital ICs.
TEST AND TRIM
Analog Devices has over 20 years of experience in testing complex
circuits and manufactures commercial test systems for precision
linear ICs. In each fabrication facility, a computer network
integrates Analog Devices, Teradyne and L TX test equipment.
The design, wafer probe and test areas share data on the network
for statistical analysis and device modelling.
All Analog Devices ASICs are tested at the wafer level, and
most are laser-wafer trimmed to achieve high accuracy. Untrimmed
thin-fIlm resistors match within 1% to 0.1%, depending on area.
Trimmed resistors can match to better than 0.01%. Wafers may
be laser drift trimmed with a hot-chuck probe to minimize the
effects oftemperature on accuracy.
After packaging, all parts are tested to assure that they meet
guaranteed specifications. Environmental handlers can verify
parts at multiple temperatures. Bum-in is performed as specified
by the customer.
PACKAGING
Analog Devices ICs are available in most modem package
types, including high pin-count and surface mount varieties.
ASICs may be assembled in any of Analog Devices' standard
packages, listed below. This list is constantly expanded and
other packages may be used if they are suitable for high performance applications.
Available Packages
Pin-grid array (PGA): 68 to 144 pins
Leaded ceramic chip carrier (LDCC): 44 pins
Leadless ceramic chip carrier (LCC): 20 to 68 1I0s
Plastic quad flat pack (PQFP): 100 pins
Plastic leaded chip carrier (PLCC): 20 to 52 pins
Plastic dual in-line package (DIP): 14 to 64 pins
Side-brazed DIP: 14 to 64 pins
Frit-seal DIP (Cerdip): 14 to 28 pins
Small outline (SO): 14 and 16 pins
11-4 APPLICA TlON SPECIFIC ICs
PROGRAM RESPONSIBILITIES AND
INTERFACES
The following chart shows the major phases in developing an
ASIC and responsibilities during each phase. The overall development time depends on the complexity of the circuit and on
how custom the design is.
Your Analog Devices Sales Engineer is your first interface for
ASIC development. Your local sales office can provide further
iuformation on Analog Devices' customlsemicustom capabilities.
PROGRAM RESPONSIBILITIES AND INTERFACES
Power Supplies
Modular AC/DC Power Supplies
GENERAL DESCRIPTION
GENERAL SPECIFICATIONS
Analog Devices offers a broad line of modular aeldc power supplies that provide both OEMs and designers a reliable, easy to
use, low-cost solution to their power requirements. Models are
available in PC mountable and chassis mountable designs with
5 volt to 15 volt (single, dual, triple) outputs and current ratings
from 25 rnA to 5 amps. Since these modular supplies are fully
encapsulated, no trimming or external component selection is
necessary; simply mount the unit, connect power and output
leads, and you're on the air! Most Analog Devices' power supplies are available from stock in both large and small quantities
with substantial discounts being applied to large quantity orders.
Power Requirements
Input Voltage Range:
Frequency:
Electrical Specifications
Temperature Coefficient:
Output Voltage Accuracy:
Breakdown Voltage:
Isolation Resistance:
Short Circuit Protection:
AC/DC POWER SUPPLY FEATURES
• Current Limit Short Circuit Protection
• PC Mounted and Chassis Mounted Versions
• Single (+5 V), Dual (±12 V, ±IS V), and Triple
(±15 V/+S V, ±IS V/+1 V to +15 V) Output Supplies
• Current Outputs:
25 rnA to 1000 rnA for Dual and Triple Output Supplies
250 rnA to 5000 rnA for Single Output Supplies
• Wide Input Voltage Range
• Low Output Ripple and Noise
• Excellent Line & Load Regulation Characteristics
• High Temperature Stability
• Free-Air Convection Cooling; No External Heat Sink Required
Environmental Requirements
Operating Temperature
Range:
Storage Temperature
Range:
105 V ac to 125 V ac
50 Hz to 250 Hz
0.02%fC
±2%, max
See Specifications Table
500 V rms, min
SOMO
All aeldc power supplies
employ current limiting. They
can withstand substantial
overload including direct
short. Prolonged operation
should be avoided since
excessive temperature rises
will occur.
-25°C to +71°C
-25°C to +8S 0 C
SPECIFICATIONS - Typical @ +2S oC and 115 V ac 60 Hz unless otherwise noted*
Type
Dual
Output
]
j
J
~
Single
Output
Triple
Output
Output
Output
Line Reg.
Load Reg.
Output
Current
mA
±SO
max
max
904
Voltage
Volts
±IS
%
0.02
%
0.02
902
±IS
±IOO
0.02
0.02
902·2
±IS
±lOO
0.02
0.02
920
±IS
±200
0.02
0.02
92S
921
±lS
:tI2
±3S0
0.02
0.02
0.02
0.02
Voltage
Error max
±200 mV
-OmV
+300mV
-OmV
+300 mV
-OmV
+300mV
-OmV
±l%
+300 mV
-OmV
O.OS
O.OS
0.10
0.02
O.OS
0.02
0.10
0.1
0.1
0.02
0.02
1000
3000
5000
0.02
0.02
O.OS
0.02
0.02
0.02
0.02
0.08
0.08
0.01
0.01
O.OS
O.OS
O.OS
O.OS
O.OS
0.05
0.05
±ISO
300
±ISO
1000
0.02
0.02
0.02
0.02
0.02
0.10
0.02
0.\0
Model
90S
922
928
923
927
2B3SJ
2B3SK
Dual
Output
J
J
SiDgIe
Output
Triple
Output
9S2
970
973
97S
9SS
976
977
972
974
±lS
+S
±IS
+S
±IS
+lto+15**
±IS
+1 to +15**
±IS
±IS
±IS
±IS
±IS
+5
±IS
+S
±240
1000
2000
3000
±IOO
SOO
±ISO
1000
±6S
12S
±65
12S
±IOO
±200
±3S0
±SOO
O.OS
O.OS
O.OS
O.OS
O.IS
0.10
0.10
±I%
±l%
±2%
±I%
-1%
±2%
±2%
(-0, +300 mY)
(-0, +300 mY)
±2%
±2%
±2%
±2%
±2%
±2%
±2%
±2%
±2%
±2%
±2%
Ripple &
Noise
Dimensions
mVl'IIlSmax
Inobe.
O.S
3.Sx2.SxO.87S
O.S
3.5x2.5xI.2S
0.5
3.5x2.5xO.87S
O.S
3.Sx2.5xI.2S
O.S
O.S
3.Sx2.SxI.62
3.Sx2.Sx 1.2S
I
1
S (typ)
3.Sx2.SxI.2S
3.Sx2.5xI.62
3.Sx2.5x 1.2S
3.S x2.S X 1.2S
O.S
0.5
O.S (typ)
1.0 (typ)
O.S
0.2S
0.5
0.2S
I
I
I
I
2
S (typ)
S (typ)
0.5 (typ)
1.0 (typ)
0.5 (typ)
1.0 (typ)
3.Sx2.SxI.62
3.5x2.SxI.2S
3.Sx2.Sx 1.25
4.4x2.7x I.4S
4.4x2. 7x 1.4S
4.4x2.7x2.00
4.4x2.7x2.00
4.4x2. 7x 1.4S
4.7Sx2.7xI.4S
4.7Sx2.7xI.4S
4.7Sx2.7xI.4S
4.7Sx2.7xI.4S
*Consult Analog Devices Power Supplies Catalog for additional information•
..Resistor programmable.
SpecifICations subject to clumge without DOtice.
POWER SUPPLIES
12-1
Modular DC/DC Converters
GENERAL DESCRIPTION
Analog Devices' line of compact dc/dc converters offers system
designers a means of supplying a reliable, easy to use, low cost
solution to a variety of floating (analog and digital) power applications. These devices provide high accuracy, short circuit protected, regulated outputs with very low output noise and ripple
characteristics.
Fourteen models are offered in five power levels of I watt, 1.8
watts, 4.5 watts, 6 watts and 12 watts. Input voltage versions
include 5 volt, 12 volt, 24 volt and 28 volt with output ranges
as follows: +5 volt, ± 12 volts and ± 15 volts at ±60 mA to
1000 mA output current capability.
Most models are high efficiency (typicaly over 60% at full load)
and feature complete 6-sided continuous shielding for EMlIRFI
protection. A 'lr-type input filter is contaUied, in some models,
which virtually eliminates the effects of reflected input ripple
current. Most Analog Devices' dc/dc converters are available
from stock in both large and small quantities with substantial
discounts being applied to large quantity orders.
DClDC POWER SUPPLY FEATURES
• Inaudible (>20 kHz) Converter Switching Frequency
• Continuous, Six-Sided EMlIRFI Shielding Except on 1 Watt
and 1.8 Watt Models
• Output Short Circuit Protection (Either Output to Common)
• Automatic Restart Mter Short Condition Removed
• Automatic Starting with Reverse Current Injected into
Outputs
• Low Output Ripple and Noise
• High Temperature Stability
• Free Air Convection Cooling
No external heat sink or specification derating is
required over the operating temperature range.
GENERAL SPECIFICATIONS FOR 1 W AND
1.8W MODELS
Line Regulation.., Full Range: ±0.3% (±l% max, 949)
Load Regulation - No Load to Full Load: ±0.4% (±0.5% max,
949)
Output Noise and Ripple: 20 mV POp (with 15 IJ.F tantalum
capacitor across each output) 2 mV rms max, 949)
Breakdown Voltage: 300 V dc min (500 V dc min, 949)
Input Filter Type: '11"
Operating Temperature Range: -25°C to +71°C
Storage Temperature Range: -40"C to + 125°C (+ 100OC, 949)
Fusing: If input fusing is desired, we recommend the use of a
slow blow type fuse that is rated at 150%-200% of the
dc/dc converter's full load input current.
GENERAL SPECIFICATIONS FOR 4.5 W, 6 W AND
12W MODELS
Line Regulation - Full Range: ±0.07% max (±0.02% max, 951,
960 Series) (±0.1% max, 943)
Load Regulation - No Load to Full Load: ±0.07% max
(±0.02% max, 951, 960 Series) (±O.l% max, 943)
Output Noise and Ripple: 1 mV rms max
Breakdown Voltage: 500 V dc min
Input Filter Type: '11"
Operating Temperature Range: -25°C to +71OC
Storage Temperature Range: -40°C to + l250C
Fusing: If input fusing is desired, we recommend the use of a
slow blow type fuse that is rated at 150%-200% of the
dc/dc converter's full load input current.
SPECIFICATIONS - Typical @ + 25°C at nominal input voltage unless otherwise noted*
Model
943
9S8
941
960
%2
%4
96S
966
967
949
940
953
94S
951
Output
Voltage
Volts
Output
Current
mA
Input
Voltage
Volts
Inputl
Voltage
Range
Volts
Input
Current
Full Load
Output
Voltage
Error max
Temperature
Coefficient
rCmax
Efficiency
Full Load
min
Dimensions
Inches
5
5
±12
±12
±lS
±lS
±15
±lS
±IS
±IS
±lS
±lS
±lS
±lS
1000
100
±lS0
±40
±33
±33
±190
±190
±190
±60**
±IS0
±lS0
±lSO
±410
5
5
S
S
S
12
5
12
24
5
5
12
28
5
4.7S/S.2S
4.5/S.S
4.7515.25
4.S/S.S
4.515.5
10.8/13.2
4.6515.5
11.2113.2
22.3/26.4
4.65/S.5
4.7515.25
11113
23/31
4.6515.5
I.S2A
200mA
1.17A
384mA
3%mA
165 mA
1.7 A
7l0mA
3S0mA
0.6A
1.35 A
0.6A
250 mA
3.7 A
±l%
±5%
±1%
±5%
±S%
±5%
±1%
±I%
±l%
±2%
±1%
±O.S%
±O.S%
±O.S%
±0.02%
-0.01 % (typ)
±0.01%
±0.01 % (typ)
±0.01% (typ)
±0.01 % (typ)
±0.OO5% (typ)
±0.005% (typ)
±O.OOS% (typ)
±0.03%
±0.01%
±0.01%
±0.01%
±0.01%
62%
50%
58%
50%
50%
SO%
62% (typ)
62% (typ)
62% (typ)
58%
62%
62%
61%
62%
2.0x2.0xO.38
1.2SxO.8xOA
2.0x2.0xO.38
1.2SxO.8xO.4
1.2SxO.8xO.4
1.25xO.8xO.4
2.0x2.0xO.38
2.0x2.0xO.38
2.0x2.0xO.38
2.0x 1.0xO.375
2.0x2.0xO.38
2.0x2.0xO.38
2.0x2.0xO.38
3.Sx2.SxO.88
NOTES
'Models 940 and 941 will deliver up to 120 mA output current (and Model 943 will deliver up to 600 mA) over an input voltage range of 4.65 V dc
and 5.5 V dc.
·Consult Analog Devices Power Suppies Catalog for additional information.
··Single-ended or unbalanced operstion is permissible such that total output current load does not exceed a total of 120 mAo
Specifications subject to change without notice.
12-2 POWER SUPPLIES
LTS-2020 Component Test Systems
HANDLER INTERFACE FOR
HANDLER CONTROL SIGNALS
BIDIRECTIONAL RS·232 PORT
FOR COMMUNICATING WITH
ANY RS-232 DEVICE
"-
\
DUAL DISK DRIVES, DOUBLE·SIDED FOR
OPERATING SYSTEM, MASS STORAGE OF DATA,
USER PROGRAMS, AND SUPPUED PROGRAMS
UNIDIREcnONAL RS-232 PORT --..
FOR OPTIONAL PRINTER
--..
DEVICE SOCKET
START TEST BUTTON - OPERATOR
INSTALLS DEVICE IN THE SOCKET
AND PUSHES THE BUTTON
.r::
SOCKET PC BOARD - - - - - . ;...
PLUG·IN SOCKET ASSEMBLY
PLUG·IN FAMILY BOARD MODULE (E.G., UNEAR, DIGITAl.
DATA CONVERSION, DISCRETE, MIXED SIGNAL!
THE LTS CONCEPT
The L TS·2020 is a versatile component test system which tests a
multitude of components to the manufacturer's specifications
(linear, digital, data conversion, and discrete devices). The sys·
tem offers such features as RS·232 ports for networking, IEEE
for compatibility with handlers and probers, dual disk drives for
mass storage of data, automatic self-calibration, and a full statistical analysis software package.
The L TS-2020 provides several data output formats - datalog,
yield analysis, and statistical analysis. The console provides the
primary measurement and control functions to test a specific
class of devices. The socket assembly is the mechanical and electronic interface for the family board and the DDT board. The
DUT board plugs directly into the socket assembly and contains
the circuitry and socket, specific to the actual device under test.
Analog Devices' component test systems are the first benchtop
testers that are programmable in BASIC and fill-in·the-blanks
CREATE. CREATE is menu-driven software which prompts
the user for data sheet limits and conditions, then builds a completed test program for the specified device. Turnkey program
libraries are available for each of the device families.
Far more than just comprehensive production testers, these test
systems can handle complex engineering analysis and incoming
inspection. They are the first systems that can provide all the
capabilities of today's large centra1ized test systems at a price
that is approximately one-third the cost. The L TS-2020 not only
provides the flexibility of distributed or decentralized testing, it
allows for cost effective multiple system purchases. They
increase overall test reliability since the threat of a single big
failure is eliminated in a distributed testing environment.
LTS-2020 Test Capabilities
MIXED SIGNAL TEST CAPABILITY
The L TS-2800 Milted Signal Family Board and L TS-0680 Test
Head perform a wide variety of ae and dc parametric tests on
devices such as complex hybrids, octal DACs, ASICs, converters, and pulse width modulators. The family board supplies the
dc pin drivers, the dc force and measure system, a Vee buffer,
an rms-to-dc conversion circuit, voltage and current sources,
and a 24 x 5 switching maw. With its 24 programmable pin
drivers, the system can provide high and low digital voltages, a
three-state (high impedance) output mode, and accurate voltages
and currents (VII source).
The family board incorporates a series of l2-bit calibrated
sources, used for programming V 1L and VIH voltage levels at the
digital inputs of the device under test. A threshold source for
programming voltage levels on a comparator is used to detect
•
digital output voltage levels accurately. For forcing and measuring currents, a VII source provides and measures 10 ..,A to
400 IDA and voltages to ±20 V.
A switching matrilt provides system flexibility by allowing any
one of several capabilities to be switched to any of the pin drivers. These include the measure system, VII source, VIH and VIL
sources, the rms-to-dc circuit, and BNC input and output connectors for interconnection with external instruments using the
IEEE-488 bus.
The LTS-0680 Mixed Signal Test Head contains a precise and
versatile time measure unit which provides accurate ac measurement of ph-pagation delays, slew rates, pulse widths, and rise
and fall times. It also incorporates a 16-bit user data bus, l6-bit
relay driver bus, four 12-bit programmable sources, and a user's
expansion board. A square wave source to the DUT provides up
to ±1O 1T01t signals, from 1.22 kHz to 2.5 MHz.
COMPONENT TEST SYSTEMS 13-1
LTS-2020 Test Capabilities (Continued)
UNEAR DEVICE TEST CAPABILITY
The LTS-2101 Operational Amplifier Family Board tests today's
very demanding high precision op amps, comparators, and regulators. This board houses the test loop used in testing op amps
and comparators and the pulse load circuitry used in developing
the high currents needed for voltage regulator testing.
TogetJier with the L TS-0655 remote ac test fixture, dynamic
parametric testing of 24-pin SSIIMSI TTL digital devices can be
achieved. Accuracies are achieved down to ±40/0 + 1.5 ns at a
resolution of 500 ps. Dynamic parameters tested are propagation
delay, setup, and hold times.
For testing devices under 100 !LV, the LTS-2101 offers a tight
offset spec of ±(0.250/0 + 5 !LV). Use of low thermal Emf relays
and a test loop gain of 10,045 ensures superior low level Vos
measurement performance for optimum repeatability of low
level signals.
DISCRETE DEVICE TEST CAPABILITY
The LTS-2600 Transistor Family Board tests bipolar transistors,
JFETs, diodes, and optocouplers. An on-board 16-bit microprocessor with 4K bytes of memory acts as a slave for the LTS
system and coordinates the timing and pulse width control of
the stimulus and measurement signals. In addition, the microprocessor monitors the interlock circuitry to insure safe handling
of high power test signals.
Testing oflow current devices is achieved with the LTS-0614
Socket Assembly which is designed to test bias and offset currents with an accuracy of ±(50/0 + 25 fA) for any FET amplifier, including quad devices. Program libraries containing prewritten test programs for many standard op amps, comparators
and regulators are available on disk.
ANALOG-TO-DIGITAL TEST CAPABILITY
The L TS-2200 ADC Family Board provides the test circuitry
required for testing monolithic, hybrid, or modular ADCs. An
on-board 16-bit microprocessor with 8K bytes of memory acts as
a slave for the system console and executes preprogrammed test
routines such as linearity, all codes existence, transition noise
measurements, and conversion time measurements at high
speed. Absolute accuracy can be measured within 200 !LV. Linearity, differential nonlinearity, offset, gain, and PSSR are
tested to ±0.05 DUT LSB +200 !LV. Turnkey test packages are
available for many of the standard ADCs currently in use.
DIGITAL-TO-ANALOG TEST CAPABIUTY
The L TS-2302 DAC Family Board utilizes advanced state-ofthe-an test techniques to provide comprehensive test capabilities for a wide variety of D/A conveners. It will test both voltage and current output DACs, DACs with and without buffer
registers, and serial or parallel input DACs to 16-bit accuracy.
High repeatability on low level signals is achieved because of the
grounding scheme on the LTS-2302. The incorporation of high
level components in the VII circuits ensures true accuracy. In
addition, the methodology for measuring low bit currents allows
appropriate testing of this parameter on CMOS DACs.
Output leakage currenton the LTS-2302 is measured with the
bit drivers to the DAC set to logic O. Current is measured using
the I to V convener. A I Mn resistor within the I to V circuitry
ensures sensitivity, thereby measuring current down to ± I !LA
full scale.
DIGITAL DEVICE TEST CAPABILITY
The LTS-2510 Digital Device Family Board provides 24-pin
driver/detectors and a precision, four quadrant VII source for
testing SSIIMSI TTL and CMOS digital devices. This board
contains four programmable device supplies and switching circuitry necessary for performing accurate parametric measurements on all device pins.
13-2 COMPONENT TEST SYSTEMS
MOSFET software packages suppon the testing of N and P
channel enhancement mode and N channel depletion mode
devices. Tests which may be perfonned on MOSFET devices
include Idss, Igss, Igssf, Igssr, Id (oft), Id (on), B Vdss, B
Vgss, B Vgssf, B Vgssr, Vds (on), Vgs (th), Vgsoff, Vsd, Rds
(on), and Gsf.
The Smanpower Test Fixture will support fast, accurate testing
of devices such as Darlington Arrays, Differential Line
Drivers/Receivers, and Transceivers/Repeaters. It contains a
matrix board which facilitates the muxing of High VoltagelHigh
Current VIIs, a nonometer, diffamp, 16-bit measure system, and
mecca ground reference to anyone of eight matrix points at the
DUT site and eight dc pin drivers programmable to anyone of
four modes - VII, V1H, V1L or Tristate. This configuration
allows true digital dc parametric testing of the front end of
smartpower devices while providing the high voltage and high
current capability to test the discrete output stage.
ANALOG SWITCH TEST CAPABILITY
The L TS-2700 Analog Switch Family Board adds switch and
multiplexer testing capability to the LTS-2020. This test capability, with CREATE software, allows datalogged device testing
at the incoming inspection and semiconductor manufacturing
levels and includes software power for use in component evaluation applications.
The L TS-2700 tests on and off drain to source leakage currents
with an accuracy of 250 pA while forcing differential voltages up
to 50 V (± 25 V from GND). Other tests performed are drain
to source on resistance, greatest change in drain-source on resistance between channels, digital input current and supply current.
Twenty high integrity analog lines are provided - four to be
used as drain connections and sixteen for source connections.
Also provided are eight programmable digital drivers, four digital control bits, six variable power supplies, and one fixed + 5 V
supply. These combinations of sources provide testing of devices
such as 4-channel switches, 16 to I multiplexers, and other combinations of switches and multiplexers.
Package Information
Contents
ADI LETTER
DESIGNATOR DESCRIPTION
PAGE
Side Brazed DIP (Ceramic)
D-14
D-16
D-18
D-20
~22
D-24
D-24A
D-28
D-28A
D-40
14 Lead
16 Lead
18 Lead
20 Lead
22 Lead
24 Lead
24 Lead (Single Width)
28 Lead
28 Lead
40 Lead
24 Lead
24 Lead (Large Cavity)
28 Lead (Large Cavity)
32 Lead ("Skinny")
32 Lead (Small Cavity)
32 Lead (Medium Cavity)
48 Lead
N-S
N-14
N-16
N-1S
N-20
N-24
N-24A
N-2S
N-2SA
N-4OA
14 - 12
14 - 13
14 - 14
14 - 15
14 - 16
14 - 17
14 -18
P-20A
P-2SA
P-44A
14 Lead
14 Lead
24 Lead
28 Lead
32 Lead
40 Lead
14 - 19
14 -20
14 - 21
14'::' 22
14 - 23
14-24
Metal Platform DIP
DH-14B
DH-16B
DH-24D
DH-28B
OH-32A
M-24A
M-32
M-40
M-46
14 Lead
16 Lead
24 Lead
28 Lead
32 Lead
24 Lead
32 Lead
40 Lead
46 Lead
SLead
14 Lead
16 Lead
IS Lead
20 Lead
24 Lead
24 Lead CDouble Width)
2SLead
28 Lead
40 Lead
14 -44
14-45
14-46
14- 47
14- 4S
14- 49
14- 50
14 - 51
14 - 52
14 - 53
Plastic Leaded Chip Carrier (PLCC)
Bottom Brazed DIP (Ceramic)
DH-14A
OH-l4C
DH-24B
DH-28A
OH-32E
DH-4OA
PAGE
Plastic DIP
14 - 2
14 - 3
14- 4
14- 5
14- 6
14 -7
14 - 8
14- 9
14 - 10
14 - 11
Side Brazed DIP for Hybrids (Ceramic)
DH-24A
OH-24C
DH-28
OH-32B
OH-32C
DH-32D
OH-48
ADI LETTER
DESIGNATOR DESCRIPTION
14 - 25
14 - 26
14 - 27
14- 2S
14- 29
14- 30
14 - 31
14- 32
14- 33
20 Lead
28 Lead
44 Lead
14- 54
14 - 55
14 - 56
8 Lead
14 Lead
16 Lead
18 Lead
20 Lead
22 Lead
24 Lead
20 Lead
14 - 57
14 - 58
14 - 59
14- 60
14 - 61
14- 62
14 - 63
14- 64
Cerdip
Q-8
Q-14
Q-16
Q-1S
Q-20
Q-22
Q-24
Q-28
Small Outline (SOIC)
R-S
R-16
R-20
SLead
16 Lead
20 Lead
14- 65
14- 66
14- 67
Leaded Chip Carrier (Ceramic)
Z-6S
68 Lead
14-68
Leadless Chip Carrier (Ceramic)
E-20A
E-28A
E-44A
E-68A
20 Terminal
28 Terminal
44 Terminal
68 Terminal
14- 34
14- 35
14- 36
14- 37
2 Lead
3 LeadCTO-52)
3 LeadCTO-5 Style)
S Lead CTO-99)
S Lead (TO-99 Style)
10 Lead CTO-100)
14 - 38
14- 39
14-40
14 - 41
14-42
14-43
Metal Can
H-02A
H-03A
H-03B
H-08A
H-OSB
H-1OA
PACKAGE INFORMATION 14--1
Package Outline Dimensions
0.14
14·Lead Side Brazeci Ceramic: DIP
SYMBOL
MIN
INCHES
MAX
MIWMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.785
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
19.94
7.87
8.13
2.79
5.08
A
b
b1
c
D
E
E1
0.014
0.030
0.008
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S1
0.005
e
L
L1
0.060
0.098
14-2 PACKAGE INFORMATION
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
2.49
NOTES
6
2,6
6
4
4
7
3
5
5
NOTES
1. Index aree; a notch or alllllCl one Identlflcetlon mark
Is located edla..nt to lead one.
2. The minimum limit for dimension b1 may be 0.023"
(O.58mml for all four corner leeds only.
3. Dimension Q shall be meesured from the seetlng plane
to the base plane.
4. This dimension allows for off_nter lid. meniscus
and gl_ overrun.
5. Applies to all four comers.
•• Alii. . . - inc_ maximum limit by 0.003" (O.08mml
measured at the center of the flat. when hot solder
dip leW finish is applied.
7. Twelve apaees.
D-16
16-Lead Side Brazed Ceramic DIP
PlM.+~-tr
'~
JL
A
SEATING
Q
L
.L-
•
L,
b..jj.- ...j
INCHES
SYMBOL
A
b
b,
c
MIN
0.014
0.030
0.008
D
E
E,
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0._
e
L
L,
MAX
MIWMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.840
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
21.34
7.87
8.13
2.79
5.08
0.080
0.080
0.38
0.78
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
2.03
e \.-
NOTES
8
2,6
8
4
4
7
3
5
5
b,
R
I-E,-I
NOTES
1. Index _ ; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mm) for all four comer leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid, meniscus
and gla.. overrun.
5. Applies to all four corners.
8. All leads - increase maximum limit by 0.003" (O.08mm)
measured at the canter of the flat. when hot solder
dip lead finish is applied.
7. Fourteen spaces.
PACKAGE INFORMA nON 14-3
D-18
I8-Lead Side Brazed Ceramic: DIP
18
SEE
NOTE 1
.'"
1
~
r- S
~
~S,
D
D..
10
9
-I
.
. ..:-i-~.
.
- -JL'
-tr
..L..
L
b../\.-
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
MIN
INCHES
• MAX
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.200
0.023
0.070
0.015
0.9&0
0.310
0.320
0.110
0.200
0.060
0.098
0.005
14-4 PACKAGE INFORMATION
.
-I J.e
MILLIMETERS
MIN
MAX
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
5.08
0.58
1.78
0.38·
24.38
7.87
8.13
2.79
5.08
1.52
2.49
NOTES
6
2.6
6
4
4
7
3
5
5
b,
_....;+. .
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58mm) for all four comer leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-canter lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. All leads - increase maximum limit by 0.003" 10.08mml
measured at the center of the flat. when hot solder
dip lead finish 15 applied.
7. Sixteen spaces.
D·20
20-Lead Side Brazed Ceramic DIP
~S,
20
,
SEE
NOTE 1
10
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.200
0.023
0.070
0.015
1.060
0.310
0.320
0.110
0.200
5.08
0.56
1.78
0.38
26.92
7.87
8.13
2.79
5.08
0.014
0.030
0.008
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.005
0.060
0.080
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
2.03
NOTES
6
2.6
6
4
4
7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
.
5. Applies to all four corners.
6. All leads - increase maximum limit by 0.003" (O.08mml
measured at the center of the flat. when hot solder
dip lead finish is applied.
7. Eighteen spaces.
II
PACKAGE INFORMATION 14-5
0-22
22-Lead Side Brazed Ceramic DIP
11-- 5 ,
~
r- s
12
22
,
SEE
NOTE 1
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
MIN
11
INCHES
MAX
MILUMETERS
MIN
MAX
0.200
0.023
0.070
0.015
1.111
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
28.22
7.87
8.13
2.79
5.08
0.014
0.030
0.008
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.005
0.060
0.080
14-6 PACKAGE INFORMATION
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
-2.03
NOTES
6
2.6
6
4
4
7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plene
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. All leads - increase maximum limit by 0.003" (0.08mml
measured at the center of the flat. when hot solder
dip lead finish is applied.
7. Twenty spaces.
D·24
24·Lead Side Brazed Ceramic DIP
., I-- S,
24
13
1
12
SEE
NOTE 1
"
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
MIN
INCHES
MAX
0.014
0.030
0.008
Q
0.500
0.590
0.090
0.120
0.150
0.015
S
S,
0.005
0.225
0.023
0.070
0.015
1.290
0.610
0.620
0.110
0.200
0.075
0.098
MILLIMETERS
MIN
MAX
NOTES
5.n
0.36
0.76
0.20
12.70
14.99
2.29
3.05
3.81
0.38
0.13
0.58
1.78
0.38
32.77
15.49
15.75
2.79
5.08
1.91
2.49
6
2.6
6
4
4
7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid, meniscus
and glass overrun.
5. Applies to all four corners.
6. All leads - increase maximum limit by 0.003" (O.08mm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
7. Twenty-two spaces.
I
PACKAGE INFORMATION 14-7
D-24A
24-Lead Side Brazed Ceramic DIP (Single Width)
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
MIN
INCHES
MAX
MIWMETERS
MIN
MAX
0.200
0.023
0.070
0.015
1.280
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
32.51
7.87
8.13
2.79
5.08
0.Ot4
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.060
0.098
0.005
14-8 PACKAGE INFORMATION
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
1.52
2.49
NOTES
6
2.6
6
4
4
7
3
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. All leads - increase maximum limit by 0.003" (0.08mm)
measured at the center of the flat. When hot solder
dip lead finish is applied.
7. Twenty·two spaces.
D-28
28-Lead Side Brazed Ceramic DIP
r"""'I
......
~
.....................
_
...............
28
_P"'-"'I~
15
SEE
NOTE 1
'" - - - - - 1
14
I4-r--E-~1
SEAnNG
PLANE
Ie-~--E, ---..!.I
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.225
0.026
0.070
0.018
1.490
0.610
0.620
0.110
0.200
5.72
0.66
1.78
0.46
37.85
15.49
15.75
2.79
5.08
0.014
0.030
0.008
0.500
0.590
0.090
0.125
0.150
0.015
0.005
0.060
0.100
0.36
0.76
0.20
12.70
14.99
2.29
3.18
3.81
0.38
0.13
1.52
2.54
NOTES
6
2,6
6
4
4
7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid, meniscus
and glass overrun.
5. Applies to all four corners.
6. All leads - increase maximum limit by 0.003" (0.08mm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
7. Twenty-six spaces.
I
PACKAGE INFORMATION 14-9
D·28A
28·Pin Side Brazed
~
28
.......................
15
SEE
NOTE 1
'" --------- - 1
-
-14
"'~--E1-~i
f
A
SEAnNG
PLANE
•
c-el-
~I,,-- .A--~.I
MAX
MILUMETERS
MIN
MAX
0.175
4.45
INCHES
SYMBOL
A
A,
B
B,
C
D
E,
aA
e,
L
MIN
0.040
0.015
0.045
0.008
0.020
0.055
0.012
1.420
0.580
0.605
O.600TYP
0.095
0.105
0.200
1.02
0.38
1.14
0.20
0.51
1.40
0.30
36.07
15.37
14.73
15.24TVP
2.41
2.67
5.08
14-10 PACKAGE INFORMATION
NOTES
3
5
2,5
5
4
4
6
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension B, may be 0.023"
(O.58mm) for all four corner leads only.
3. Dimension shall be measured from the seating plane
to the base plane.
4. This dlmanslon allows for off-center lid. meniscus
and glass overrun.
5. All leads - Increase maximum limit by 0.003" (0.08mm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
6. Twenty-six spaces.
D-40
4O-Lead Side Brazed Ceramic: DIP
-t I-s.
_.r-t
P"""'II
..-.
.-..
.....
.....
.....
.....
.....
.....
....
.....
.....
.......
.....
.....
,......
1""""1
__
..-.
40
21
1
20
SEE
NOTE
~
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.225
0.023
0.070
0.015
2.096
0.620
0.630
0.110
0.200
5.72
0.58
1.78
0.38
53.24
15.75
16.00
2.79
5.08
0.014
0.030
0.008
Q
0.590
0.520
0.090
0.125
0.150
0.015
S
S,
0.005
0.060
0.098
0.36
0.76
0.20
12.95
13.21
2.29
3.18
3.81
0.38
0.13
1.52
2.49
NOTES
6
2.6
6
4
4
7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
S. Applies to all four corners.
6. All leads - increase maximum limit by 0.003" (O.08mml
measured at the center of the flat. when hot solder
dip lead finish is applied.
7. Thirty-eight spaces.
II
PACKAGE INFORMATION 14-11
DH·24A
24·Lead Size Brazed Ceramic DIP for Hybrid
13
SEE
NOTE 1
-..
12
joe---------D---------.j
f
c ... _
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.225
0.014
0.023
0.030
0.070
0.008
0.015
1.212
0.580
0.600
0.590
0.620
0.100BSC
0.120
0.200
0.180
0.015
0.075
0.098
0.005
5.72
0.36
0.58
0.76
1.78
0.20
0.38
29.69
14.21
14.70
14.99
15.75
2.54BSC
3.05
5.08
4.57
0.38
1.91
2.49
0.13
14-12 PACKAGE INFORMATION
NOTES
2
6
4,7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
'
4. The basic pin spacing is 0.100" 12.54mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Twenty-two spaces.
DH-24C
24-Lead Side Brazed Ceramic DIP for Hybrid (Large Cavity)
. , ~S,
24
13
,
SEE
NOTE 1
12
~-----------------------------------D---------------------------"
"'~---E, - - 4 0 1..1
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
INCHES
MAX
MILLIMETERS
MIN
MAX
0.245
0.014
0.023
0.030
0.070
0.008
0.015
1.270
0.585
0.610
0.590
0.620
0.100BSC
0.120
0.200
0.180
0.015
0.075
0.098
0.005
6.22
0.36
0.58
1.78
0.76
0.20
0.38
31.11
14.33
15.49
14.99
15.75
2.MBSC
3.05
5.08
4.57
0.38
1.91
2.49
0.13
MIN
NOTES
2
6
4,7
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Twenty-two spaces.
3
5
5
III
PACKAGE INFORMATION 14-13
DH-28
28-Lead Side Brazed Ceramic DIP for Hybrid (Large Cavity)
15
28
SEE
NOTE 1
"
14
I. -
~
D
~~-t~JL- --T~
-I . Ib
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
-.II-
b,
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.225
0.014
0.023
0.030
0.070
0.008
0.015
1.414
0.580
0.610
0.590
0.620
0.1OOBSC
0.120
0.200
0.180
0.015
0.075
0.098
0.005
5.72
0.36
0.58
0.76
1.78
0.20
0.38
34.64
14.73
15.49
14.99
15.75
2.54BSC
3.05
5.08
4.57
0.38
1.91
2.49
0.13
14-14 PACKAGE INFORMATION
NOTES
2
6
4.7
3
5
5
1101.. - - E
--.t-1
IOI--~- E , --.t~
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54mm) between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Twenty-six spaces.
DH·32B
32-Lead Side Brazed Ceramic DIP for Hybrid ("Skinny")
1-5
17
SEE
NOTE 1
"
16
. . . ----------D-----------4j
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
INCHES
MAX
MILUMETERS
MIN
MAX
0.280
0.016
0.020
0.035
0.045
0.009
0.012
1.584
1.640
0.580
0.605
0.590
0.610
0.100BSC
0.125
0.200
0.180
0.015
0.060
0.098
0.005
7.11
0.41
0.51
1.14
0.89
0.23
0.31
41.66
4O.1i4
14.73
15.24
14.99
15.49
2.54BSC
3.18
5.08
4.57
1.02
1.52
2.49
0.13
MIN
NOTES
2
6
4,7
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seeting plane
to the base plane.
4. The basic pin spacing is 0.100" 12.54mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Thirty spaces.
3
5
5
I
PACKAGE INFORMATION 14-15
DH·32C
32·Lead Side Brazed Ceramic DIP for Hybrid (smaU Cavity)
... I--s,
I ................ ,....., ..........
32
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
'7
INCHES
MAX
MILLIMETERS
MIN
MAX
0.280
0.016
0.020
0.035
0.055
0.009
0.012
1.620
0.870
0.910
0.890
0.930
0.100BSC
0.150
0.180
0.190
0.230
0.015
0.060
0.098
0.005
7.11
0.41
0.51
1.40
0.89
0.23
0.31
41.14
22.10
23.11
22.61
23.62
2.54BSC
3.81
4.57
4.83
5.84
1.02
1.52
2.49
0.13
MIN
14-16 PACKAGE INFORMATION
.............. _==- .... -:L
NOTES
2
6
4.7
3
5
5
r- s
NOTES
1. Index area; a notch or a lead one identification mark
Is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" 12.54mml between
centerllnes.
5. Applies to all four corners.
6. E, shall be measured at the centerline of tI1e leads.
7. Thirty spaces.
DH-32D
32-Lead Side Brazed Ceramic DIP for Hybrid (Medium Cavity)
.,
~s.
17
32
SEE
NOTE 1
"
16
MAX
MILLIMETERS
MIN
MAX
0.280
0.020
0.016
0.035
0.055
0.009
0.012
1.616
0.870
0.910
0.890
0.930
0.1ooBSC
0.125
0.200
0.180
0.015
0.060
0.098
0.005
7.11
0.41
0.51
0.89
1.40
0.31
0.23
39.59
22.10
23.11
22.61
23.62
2.54BSc
3.18
5.08
4.57
1.52
'.02
2.49
0.13
INCHES
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
MIN
NOTES
2
6
4.7
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" 12.54mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Thirty spaces.
3
5
5
III
PACKAGE INFORMATION 14-17
DH-48
48-Lead Side Brazed Ceramic: DIP for Hybrid
....................................
25
48
SEE
NOTE 1
24
--
INCHES
SYMBOL MIN MAX
A
0.240
b
0.016 0.020
b,
0.045 0.055
c
O.OOS 0.012
D
2.45\) 2.500
E
0.985 1.005
E,
0.990 1.010
e
0.100 SSC
L
0.140 0.175
0.180
L,
Q
0.040 0.060
S
0.104
S,
0.049
14-18 PACKAGE INFORMATION
MILLIMETERS
MIN
MAX
6.10
0.41 0.51
1.14
1.39
0.20
0.31
62.23 63.50
25.02 25.53
25.15 25.65
2.54BSC
3.56
4.44
4.57
1.02 1.52
2.03
0.13
NOTES
2
6
4.7
3
5
5
NOTES
1. Index area; a notch or a lead one identHication mark
is loc:ated adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58 mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54 mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Forty-six spaces.
DH-14A
14-Lead Bottom Brazed Ceramic DIP
14
8
SEE
NOTE1 "-
7
fA
I I I I I I
LII
I
I
- - - - -
i
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
INCHES
MAX
MILLIMETERS
MIN
MAX
0.220
0.023
0.070
0.015
0.805
0.480
0.505
0.290
0.320
0.100BSC
0.125
0.200
0.180
0.015
0.060
0.098
0.005
5.59
0.58
1.78
0.38
20.45
12.19
12.83
7.37
8.13
2.54BSC
3.18
5.08
4.57
0.38
1.52
2.49
0.13
MIN
0.014
0.030
0.008
0.36
0.76
0.20
I I
I I
II
!*"r
TL,
Q
I
i
NOTES
2
6
4,7
c
!.- E,--I
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54mm) betwean
centerlines.
5. Applies to all four comers.
6. E, shall be measured at the centerline of the leads.
7. Twelve spaces.
3
5
5
II
PACKAGE INFORMATION 14-19
DH-l4C
14-Lead Bottom Brazed Ceramic DIP
8
14
7
SEE
NOTE 1
I
-----.!-I
I
........- - - - -
o
., ls;:::===========::;:;::~
Q
f1
~ Jl-i.1- •
I
b,
SYMBOL
A
b
b,
c
0
E
E,
e
L
L,
Q
S
S,
INCHES
MIN
MAX
0.140 0.200
0.014 0.023
0.030 0.070
0.008 0.015
0.770 0.810
0.* 0.510
0.295 0.305
0.100 SSC
0.150 0.200
0.180
0.015 0.035
0.137
0.060
MILLIMETERS
MIN
MAX
3.56
5.08
0.36
0.58
1.78
0.76
0.20
0.38
19.56 20.57
12.19 12.95
7.49
7.75
2.54 BSC
3.05
5.08
4.57
1.91
0.38
3.48
0.52
14-20 PACKAGE INFORMATION
c
!--E, -.j
NOTES
2
6
4 7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58 mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100· 12.54 mm) between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Twelve spaces.
DH-24B
24-Lead Bottom Brazed Ceramic DIP
13
24
SEE
NOTE1 "12
14
~I
D
-~-rt~-~-tt~j~t~-~Jl~-1±~
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.225
0.014
0.023
0.030
0.070
0.008
0.015
1.320
0.770
0.810
0.550
0.620
0.100BSC
0.120
0.200
0.180
0.015
0.075
0.098
O.OOS
5.72
0.36
0.58
0.76
1.78
0.38
0.20
33.53
20.57
19.56
14.99
15.75
2.54BSC
3.OS
5.08
4.57
0.38
1.91
2.49
0.13
NOTES
2
6
4.7
i
14-14- - E - -.....
1
[114---4
E,-----..!·f
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Twenty-two spaces.
I
3
5
5
PACKAGE INFORMA TION 14-21
DH-28A
28-Lead Bottom Brazed Ceramic DIP
15
28
SEE
NOTE1
~
14
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
INCHES
MAX
MILLIMETERS
MIN
MAX
0.225
0.014
0.023
0.030
0.070
0.008
0.015
1.575
0.770
0.810
0.620
0.550
0.100BSC
0.120
0.200
0.180
0.075
0.015
0.137
0.005
5.72
0.36
0.58
0.76
1.78
0.20
0.38
40.00
19.56
20.57
14.99
15.75
2.54BSC
3.05
5.08
4.57
0.38
1.91
3.48
0.13
MIN
74-22 PACKAGE INFORMA TION
NOTES
2
6
4,7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The base pin spacing is 0.100" (2.54mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of all the leads.
7. Twenty-six spaces.
DH-32E
32-Lead Bottom Brazed Ceramic DIP
17
32
SEE
NOTE' '"
"
J--r- - - E
---1"1
tJ
1
.+
~Ie---E, ----.1.1
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
INCHES
MAX
MILLIMETERS
MIN
MAX
0.225
0.014
0.023
0.030
0.070
0.006
0.015
1.750
1.105
1.075
0.850
0.920
0.1ooBSC
0.120
0.200
0.180
0.015
0.075
0.120
0.005
5.72
0.36
0.58
0.76
1.76
0.20
0.38
44.31
28.07
27.31
21.59
23.37
2.54BSC
3.05
5.08
4.57
0.38
1.91
3.05
0.13
MIN
NOTES
2
6
4.7
NOTES
1. Index area; a notch or a lead one identification mark is
located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54mml between centerlines.
5. Applies to all four corners.
6. E, shall be measured atthe centerline olthe leads.
7. Thirtyspaces.
3
5
5
PACKAGE INFORMA TION 14-23
DH-40A
4O-Lead Bottom Brazed Ceramic DIP
21
40
SEE
NOTE 1
1--1.- - E,·---.j.1
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
7~24
INCHES
MIN
MAX
0.225
0.014 0.023
0.030 0.060
O.OOS 0.015
2.120
0.770 0.810
0.580 0.620
0.100 BSC
0.120 0.200
0.180
0.015 0.075
0.098
0.005
MILLIMETERS
MIN
MAX
5.72
0.36
0.58
0.76
1.78
0.20
0.38
53.85
19.56 20.57
14.73 15.75
2.54BSC
3.05
5.08
4.57
0.38 1.91
2.49
0.13
PACKAGE INFORMATION
NOTES
2
6
4.7
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58 mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54 mm) between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Thirtv-eight spaces.
DH·14B
14·Lead Metal Platform DIP
14
SEE
NOTE 1
[
1
D===i
I-
SEATING
PLANE
TIr
t
-
-
~
A
tl>b
D
E
E,
e
L
L,
Q
cfIb
*
INCHES
MAX
MILLIMETERS
MIN
MAX
0.225
0.014
0.023
0.885
0.490
0.520
0.295
0.305
0.100BSC
0.140
0.200
0.160
0.015
0.075
5.72
0.58
MIN
,-h
L,
L
SYMBOL
Q
0.36
NOTES
2
22.48
12.45
13.21
7.49
7.75
2.54BSC
3.56
5.08
4.57
0.38
1.91
6
4.7
3
NOTES
1. Index area; a square comer or a lead one Identification
mark is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the ba.. plane.
4. The basic pin spacing is 0.100" (2.54mml between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Twelve spaces.
I
PACKAGE INFORMATION 14-25
DH-16B
16-Lead Metal Platform DIP
:]
16
SEE
NOTE 1
[
~
-
...,
-
-
1-
L
!
SYMBOL
A
ct>b
0
E
E,
e
L,
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.175
0.016
0.960
0.490
0.295
0.095
0.160
4.45
0.41
24.40
12.45
7.49
2.41
4.06
0.215
0.020
0.985
0.520
0.305
0.105
0.255
14-26 PACKAGE INFORMA TION
5.46
0.51
25.00
13.21
7.75
2.67
6.48
NOTES
4
5
NOTES
1. Index area; a square comer or a lead one Identification
mark is located adjacent to lead one.
2. Pin 6 is electrically connected to the case.
3. Case has metal bottom surface.
4. E, shall be measured at the centerline of the leads.
5. Fourteen spaces.
DH-24D
24-Lead Metal Platform DIP
13
24
SEE
NOTE 1
"
12
~I-------D
11
A
1.
I
t
L,
*
svP.liSOL
A
+b
D
E
E,
e
L,
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.250
0.016
0.020
1.385
0.810
0.590
0.610
0.100BSC
0.140
0.210
6.35
0.41
0.51
35.18
20.57
15.00
15.50
2.54BSC
3.56
5.33
NOTES
"'~--E,-~.j
NOTES
1. Index area; a colored bead or identification mark is
located at lead one.
2. The basic pin spacing is 0.100" 12.54mml between
centerlines.
3. E, shall be measured at the centerline of the leads.
3
2
III
PACKAGE INFORMATION 14-27
DH-28B
28-LeadMetai Platform DIP
28
15
SEE
NOTE 1
"l
SEATING
PLANE
SYMBOL
A
b
D
E
E,
e
L
Q
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.185
0.205
0.016
0.020
1.555
1.585
0.785
0.805
0.590
0.610
0.100BSC
0.140
0.210
0.020
0.030
4.70
5.21
0.41
0.51
39.50
40.26
19.93
20.48
15.00
15.50
2.54BSC
3.56 I 5.33
0.51
0.76
14-28 PACKAGE INFORMA TlON
NOTES
4
3
2
NOTES
1. Index area; a colored bead or identification mark is
located at lead one.
2. Dimension Q shall be measured from the seating
plane to the base plane.
3. The basic spacing is 0.100" (2.54mm) between
centerlines.
4. E, shall be measured at the centerline of the leads.
DH-32A
32-Lead Metal Platform DIP
,7
32
SEE
NOTE'
'6
-rtl
SEATING
PlANE
·
SYMBOL
+b
D
E
E,
e
L
L,
Q
==:::::::::-_E-=--==~jl
I'I--li'---(
Lrn H~ ~ ~ HHHn-tr ~ " · ",,+
... ...(1--
A
11.
INCHES
MAX
MILUMETERS
MIN
MAX
0.280
0.016
0.020
1.755
1.125
1.155
0.890
0.910
0.100BSC
0.140
0.210
0.160
0.020
0.030
7.11
0.41
0.51
44.58
28.58
29.34
23.11
22.61
2.54BSC
3.56
5.33
3.81
0.52
0.75
MIN
~I.--- E, -----I-I
...f • I--
NOTES
2
6
4.7
3
NOTES
1. Index area; a colored bead or identification mark is
located at lead one.
2. The minimum limit for dimension +b may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100"(2.54mm) between
centerlines.
5. Applies to all four corners.
6. E, shall be measured at the centerline of the leads.
7. Thirty spaces.
II
PACKAGE INFORMATION 14-29
M·24A
24-Lead Metal Platform DIP
~
~
"
n
~
~
n
n
~
nan
M
~
SEE
NOTE 1
"
.,1 ., .,
,,,;
.,
,~
..-~---D------t-I
l
~I·-------E--------~-I
J
1
L,
-.1
INCHES
SYMBOL
b
D
E
E,
e
L
S
MIN
MAX
0.014
1.265
0.765
0.590
0.090
0.230
0.023
1.280
0.780
0.620
0.110
0.270
0.090
14-30 PACKAGE INFORMATION
MILLIMETERS
MIN
MAX
0.36
32.131
19.431
12.95
2.29
5.84
0.58
32.51
19.80
15.75
2.79
6.85
~.29
NOTES
3
4
2
M-~- - E, ---.....~
NOTES
1. Index area; a notch or a lead one identification mark
is locatad adjacent to lead one.
2. Applies to all four corners.
3. E, shall be measured at the centerline of the leads.
7. Twenty-two spaces.
M-32
32-Lead Metal Platform DIP
:==ccocc~=cccccc
32
17
SEE
NOTE 1
'"
1
c
C
c
ceo
COO
C
C
ceo
0
16
0
~~-----------D----------~~
T[~~------------~]
I
J.14--~_ _
I-~{.l ~~~
e
-.l_l--b_D,_-.l__
SYMBOL
A
b
D
D,
E
E,
e
L,
S
S,
MIN
INCHES
MAX
MILLIMETERS
MAX
MIN
0.200
0.020
1.745
1.494
0.880
0.098
0.240
0.115
0.115
1.506
1.145
0.920
0.102
0.135
0.135
~r------------E---------~.I
37.948
22.352
2.49
6.09
2.92
2.92
NOTES
5.08
0.51
44.323
38.252
29.083
23.368
2.59
3
4
3.43
3.43
2
2
-E,----eott
l
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. Applies to all four corners.
3. E, shall be measured at the centerline of the leads.
4. Thirty spaces.
PACKAGE INFORMATION 14-31
M-40
4O-Lead Metal Platform DIP
=C
0
C C
~
C
C
40
=0 =C
C C
=
~
c c c _
21
SEE
NOTE 1
"
1
C
c c c ceo
C
C C
C
ceQ c e c c c 20
c
~I
'--r- - - - - - D
Il
~ 'IrOT""'n"~
n --n--n-1~
J~~
~
J
--II-- b
S
1
~ ~ rr-rr-r~
~ ~r-rr-rrn"1T"""TI"11~
n--.r-n-"~~
UIT"""lT--n-.
D,
..j
.1
-\0--
~~-------E------~~
l
SYMBOL
MIN
INCHES
MAX
A
0
0,
1.894
E
E,
e
L,
S
S,
0.880
0.098
0.240
0.115
0.115
0.19
2.145
1.906
1.145
0.920
0.102
0.135
0.135
14-32 PACKAGE INFORMATION
J
MILLIMETERS
MIN
MAX
48.108
22.352
2.49
6.09
2.92
2.92
NOTES
4.83
54.483
48.412
29.083
23.368
2.59
3
4
3.43
3.43
2
2
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. Applies to all four corners.
3. E, shall be measured at the centerline of the leads.
4. Thirty-Eight spaces.
M-46
46-Lead Metal Platform DIP
==e
~
0
1
=c
46
=== C
c ceo
eGO 0
0 0 0 COO
24
SEE
NOTE 1
"
o
~
~
0
c
~
= Gee
C C : C
Q
C
~
=C
ceo
~I~~---------E----------~~
L'-n--_ _ _"""Tr""""J
~~...--E,-~lL
SYMBOL
MIN
INCHES
MAX
A
b
0.016
D
D,
2.194
E
E,
e
1.280
0.098
L,
S
S,
0.080
0.130
0.231
0.020
2.380
2.206
1.580
1.320
0.102
0.210
0.100
0.150
MILLIMETERS
MAX
MIN
0.410
55.728
32.512
2.49
2.032
3.302
5.86
0.510
60.452
56.032
40.132
33.528
2.59
5.334
2.54
3.81
NOTES
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. Applies to all four corners.
3. E, shall be measured at the centerline of the leads.
4. Forty-four spaces.
3
4
2
2
PACKAGE INFORMATION 14-33
III
III
E·20A
20-Terminal Leadless Ceramic Chip Carrier
BOTTOM VIEW
Ihx45°,
3PLACES
L
I
~I--:= D
.fT
...lQX450 ,
I IH HHHHill
SYMBOL
A
B,
D
D,
MIN
INCHES
MAX
0.100
0.064
0.022
0.028
0.342
0.358
0.075 REF
e
O.05OBSC
j
h
0.020 REF
0.040 REF
0.045
0.055
L
14-34 PACKAGE INFORMA TlON
MILLIMETERS
MIN
MAX
2.54
1.63
0.71
0.56
9.09
8.69
1.91 REF
1.27BSC
0.51
1.02
1.14
1.40
NOTES
1
2
NOTES
1. Dimension A controls the overell pacuge thickness.
2. Applies to ell 4 sides.
3. All termlnels ere gold pleted.
E-28A
28-Terminal Leadless Ceramic Chip Carrier
--*fB,
L
......NO.1 PIN INDEX
e
t
Ih x 45°'
3 PLACES
L
BOTTOM VIEW
I
I
'f
-*- Ii
P
D
x 450 ,
IIHHHHHHHITI
SYMBOL
A
B,
D
D,
e
i
h
L
MIN
INCHES
MAX
0.064
0.100
0.022
0.028
0.442
G.458
0.075 REF
O.05OBSC
0.020 REF
0.040 REF
0.045
0.055
MILUMETERS
MIN
MAX
1.63
2.54
0.56
0.71
11.23
11.63
1.91 REF
1.27BSC
0.51
1.02
1.14
I 1.40
NOTES
1
2
NOTES
1. Dimension A controls the overall package thickness.
2. Applies to all 4 sides.
3. All terminals are gold plated.
PACKAGE INFORMA TION 14-35
E-44A
44-Terminal Leadless Ceramic: Chip Carrier
L
T
SYMBOL
A
B,
0
0,
e
j
h
L
it
BOTTOM VIE"vV
INCHES
MAX
MILLIMETERS
MIN
MAX
NOTES
0.064
0.100
0.022
0.028
0.640
0.662
0.075 REF
0.050BSC
0.020 REF
0.040 REF
0.045
0.055
2.54
1.63
0.56
0.71
16.27
16.82
1.91 REF
1.27BSC
0.51
1.02
1.14
1.40
MIN
14-38 PACKAGE INFORMA TION
1
2
NOTES
1. Dimension A controls the overall package thickness.
2. Applies to all 4 sides.
3. All terminals are gold plated.
E·68A
68·Tenninal Leadless Chip Carrier
Le
BOTTOM
VIEW
.L.
-1.
....
Ih x 45°)
3 PLACES r+~
'-"...n....rc.~KJri..Ir"'-"'u-tL.H..H..H..H..JH...J"'--.L.TT Ii x 45°)
r
~
IIHHH'HHHHNNMNNHHTIHN
D
SYMBOL
A,
B
D
e
h
i
Lz
INCHES
MAX
MILLIMETERS
MIN
MAX
0.065
0.103
0.020
0.030
0.940
0.965
0.045
0.055
O.04OTYP
0.020TYP
0.045
0.055
1.65
2.62
0.51
0.76
23.88
24.51
1.14
1.40
1.02TYP
0.51TYP
1.14
1.40
MIN
NOTES
1
2
111
NOTES
1. Dimension controls the overall package thickness.
2. Applies to all 4 sides.
3. All terminals are gold plated.
III
PACKAGE INFORMATION 14-37
H·02A
2·Lead Metal Can
SYMBOL
A
ebb
ebD
ebD,
e,
k
k,
L
IX
INCHES
MAX
MILLIMETERS
MIN
MAX
0.125
0.150
0.015
0.019
0.209
0.230
0.178
0.195
0.100BSC
0,036
0.045
0.028
0.048
0.500
0.750
45°BSC
3.17
3.81
0.38
0.48
5.31
5.84
4.52
4.95
2.54BSC
1.17
0.91
0.71
1.22
12.70
19.05
45°BSC
MIN
14-38 PACKAGE INFORMATION
NOTES
2
1
1
NOTES
1. Leads having maximum diameter 0.019" (O.48mml
measured in gauging plane 0.54" (1.37mml + 0.001"
(O.03mm) - 0.000" (O.OOmm) below the seating plane
of the device are within 0.007" (0.18mm) of their true
positions relative to the maximum-width tab.
2. All leads - increase maximum limit by 0.003" (0.08mml
when hot solder dip finish is applied.
H-03A
3-Lead Metal Can (TO-52)
e,
r-
F-I
INCHES
MAX
SYMBOL
MIN
A
+b
+bz
+D
+D,
e
e,
0.115
F
j
k
L
L,
Lz
II
0.150
0.021
0.016
0.019
0.209
0.230
0.178
0.195
0.100T.P.
O.05OT.P.
0.030
0.046
0.036
0.028
0.048
0.500
0.050
0.250
45°T.P.
MILLIMETERS
MIN
MAX
3.81
0.53
0.41
0.48
5.31
5.84
4.52
4.95
2.54T.P.
1.27T.P.
0.76
0.91
1.17
0.71
1.22
12.70
1.27
6.35
NOTES
2.92
1.4
1.4
2
2
3
1
1
NOTES
1. (Three Leeds) +bz applies between L, and Lz• +b applies
between Lz and 0.5" (12.70mm) from seating plane.
Diameter is uncontrolled in L, and beyond 0.5"
(12.7Omm) from seating plane.
2. Leads having maximum diameter 0.019" (O.48mm)
measured in gauging plane 0.054" (1.4mm) + 0.001"
(O.03mm) - 0.000" (O.OOmm) below the seating plane
of the device are within 0.007" (0.18mm) of their true
positions relative to a maximum-width tab.
3. Measured from maximum diameter of the actual
device.
4. All leads - increase maximum limit by 0.003" (0.08mm)
when hot solder dip finish is applied.
III
PACKAGE INFORMA TION 14-39
H-03B
3-Lead Metal Can (TO-S Style)
r-·--:§r:'lI7l
.l'r . ~I
PLANE
===::J
\
h--ll-P
SYMBOL
A
+b
+bz
+0
+0,
e
e,
h
I
k
L
L,
Lz
P
MIN
INCHES
MAX
Q....j
MILLIMETERS
MIN
MAX
0.165
0.185
0.016
0.021
0.016
0.019
0.335
0.370
0.305
0.335
O.200T.P.
0.100T.P.
0.015
0.035
0.028
0.034
0.029
0.045
0.500
0.050
0.250
0.100
4.19
4.70
0.41
0.53
0.41
0.48
8.51
9.40
7.75
8.51
5.08T.P.
2.54T.P.
0.38
0.89
0.71
0.86
1.14
0.74
12.70
1.27
6.35
2.54
0.007
45°T.P.
0.18
Q
r
CIt
14-40 PACKAGE INFORMA TlON
NOTES
2.7
2.7
4
3
2
2
2
1
5
NOTES
1. This zone is controlled for automatic handling. The
variation in actual diameter within the zone shall not
exceed 0.010" (O.25mm).
2. (Three leads) +bz applies between L, and Lz. +b applies
between Lz and 0.500" (12.70mm) from seating plane.
Diameter is uncontrolled in L, and beyond 0.500"
(12.70mm) from seating plane.
3. Measured from maximum diameter of the actual
device.
4. Leads having maximum diameter 0.019" (O.48mm)
measured in gauging plane 0.54" (1.37mm) + 0.001"
(O.03mm) - 0.000" (O.OOmm) below the seating plane
of the device are within 0.007" (0.18mm) of their true
positions relative to the maximum-width tab.
5. Details of outline in this zone optional.
6. Lead #3 connected to casa.
7. All leads - increasa maximum limit by 0.003" (O.08mm)
when hot solder dip finish is applied.
H-OSA
8-Lead Metal Can (TO-99)
SYMBOL
A
.b
• b,
.D
• D,
.Dz
e
e,
F
k
k,
L
L,
Lz
Q
II!
INCHES
MAX
MILLIMETERS
MIN
MAX
0.185
0.186
0.016
0.019
0.016
0.021
0.335
0.370
0.305
0.335
0.110
0.160
O.200BSC
0.100BSC
0.040
0.027
0.034
0.027
0.045
0.500
0.750
0.050
0.250
0.010
0.045
45°BSC
4.19
4.70
0.41
0.48
0.41
0.53
8.51
9.40
7.75
8.51
2.79
4.06
5.08BSC
2.54BSC
1.02
0.69
0.86
0.69
1.14
12.70
19.05
1.27
6.35
1.14
0.25
45°BSC
MIN
NOTES
1,4
1,4
3
3
NOTES
1. (Alileadsl.b applies between L, and Lz.•b, applies
between L2 and 0.500" (12.70mml from the reference
plane. Diameter is uncontrolled in L, and beyond 0.500"
(12.70mml from the reference plane•
2. Measured from the maximum diameter of the
product.
3. Leads having a maximum diameter 0.019" (O.48mml
measued in gauging plane 0.054"11.37mm) + 0.001"
(O.03mm) - 0.000" (O.OOmm) below the base plane of
the product are within o.oor (0.18mml of their true
position relative to the maximum width tab.
4. All leads - increase maximum limit 0.003" (0.08mm)
when hot solder dip finish is applied.
•
3
PACKAGE INFORMATION 14-41
H-08B
8-Lead Metal Can (TO-99 Style)
INCHES
SYMBOL
A
+b
+b,
+D
+D,
+Dz
e
e,
F
k
k,
L
L,
'-«
Q
CI
1~2
MAX
MILUMETERS
MIN
MAX
0.165
0.185
0.016
0.019
0.016
0.021
0.336
0.370
0.305
0.336
0.110
0.160
O.230BSC
0.115BSC
0.040
0.027
0.034
0.027
0.045
0.750
0.500
0.050
0.250
0.010
0.045
45°BSC
4.19
4.70
0.41
0.48
0.41
0.53
8.51
9.40
7.75
8.51
2.79
4.06
5.84BSC
2.92BSC
1.02
0.86
0.69
0.69
1.14
12.70
19.05
1.27
6.35
G.25
1.14
WBSC
MIN
PACKAGE INFORMATION
NOTES
1~4
1.4
3
3
2
1
1
1
3
NOTES
1. (All leads) +b applies between L, and ,-«. +b, applies
between '-« and 0.500" (12.70mm) from the reference
plane. Diameter Is uncontrolled in L, and beyond 0.500"
(12.70mm) from the reference plane.
2. Measured from the maximum diameter of the
product.
3. Leads having a maximum diameter 0.019" (O.48mm)
measued In gauging plane 0.054" (1.37mm) + 0.001"
(O.03mm) - 0.000" (O.OOmm) below the base plane of
the product are within o.oor (0.18mm) of their true
position relative to the maximum width tab.
4. All leads - increase maximum limit 0.003" (O.08mm)
when hot solder dip finish is applied.
H-1OA
lO-Lead Metal Can (TO-IOO)
rAt14'
rr
ii'l
~
!
I
~:II\I\
I:
F~
Q
SYMBOL
A
+b
+b,
+D
+D,
+Dz
e
e,
F
k
k,
L
L,
La
Q
II!
+b
SEATING PLANE
INCHES
MAX
MILUMETERS
MIN
MAX
0.185
0.185
0.016
0.019
0.016
0.021
0.335
0.370
0.305
0.335
0.110
0.160
O.230BSC
0.115BSC
0.040
0.027
0.034
0.027
0.045
0.500
0.750
0.050
0.250
0.010
0.045
36"BSC
4.19
4.70
0.41
0.48
0.41
0.53
8.51
9.40
7.75
8.51
2.79
4.06
5.84BSC
2.92BSC
1.02
0.69
0.86
0.69
1.14
12.70
19.05
1.27
6.35
1.14
0.25
36"BSC
MIN
+b,
NOTES
1,4
1,4
3
3
NOTES
1. (Three Leads) +ba applies between L, and La. +b applies
between La and 0.5" (12.70mm) from seating plane.
Diameter is uncontrolled in L, and beyond 0.5"
(12.70mm) from seating plane.
2. Leads having maximum diameter 0.019" (O.48mm)
measured in gauging plane 0.054" (1.4mm) + 0.001"
(O.03mm) - 0.000" (O.OOmm) below the seating plane
ot the devlee are within 0.007" (0.18mm) of their true
positions relative to a maximum-width tab.
3. Measured from maximum diameter of the actual
deviee.
4. All leads - increase maximum limit by 0.003" (O.08mm)
when hot solder dip finish is applied.
2
1
1
1
3
PACKAGE INFORMA TION 11H13
N·S
8-Lead Plastic DIP
b
SYMBOL
A
A2
b
b,
c
0
E
E,
e
L
L,
Q
e
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.210
0.115
0.195
0.014
0.022
0.045
0.070
O.OOS
0.015
0.348
0.430
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
2.93
4.95
0.356
0.558
1.77
1.15
0.204
0.381
8.84
10.92
7.62
8.25
6.10
7.11
2.54BSC
3.18
5.05
3.81
0.38
1.52
14-44 PACKAGE INFORMA TlON
b,
NOTES
2
2
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
N-14
14-Lead Plastic DIP
SEE
NOTE 1
--.-
I
"
E,
7rJ
&""'-:'-""T""T"""1I'"""1""'T'""'T""T""1.......-r-r-
~D~
-.l
T~Q~f
SEATING
,
PLANE-.-
-
-
-
--
-
-,
~ .--li-- -1.1-- ~ ~..
SYMBOL
A
A2
b
b,
c
D
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MAX
MIN
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.725
0.795
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
4.95
2.93
0.558
0.356
1.77 .
1.15
0.381
0.204
18.42
20.19
8.25
7.62
7.11
6.10
2.54BSC
3.18
5.05
3.81
1.52
0.38
NOTES
'+
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
III
PACKAGE INFORMA TION 14-45
N-16
16-Lead Plastic DIP
SYMBOL
A
A2
b
b,
c
D
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.745
0.840
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
4.95
2.93
0.356
0.558
1.15
1.77
0.204
0.381
21.33
18.93
7.62
8.25
6.10
7.11
2.54BSC
5.05
3.18
3.81
1.52
0.38
14--46 PACKAGE INFORMA TION
NOTES
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
N-18
IS-Lead Plastic DIP
SYMBOL
A
A.
b
b,
c
0
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.015
0.008
0.845
0.925
0.300
0.325
0.240
0.280
0.100BSC
0.125 I 0.200
0.150
0.015
0.060
5.33
2.93
4.95
0.558
0.356
1.15
1.77
0.381
0.204
21.47
23.49
7.62
8.25
6.10
7.11
2.54BSC
5.05
3.18
3.81
0.38
1.52
NOTES
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
II
PACKAGE INFORMA TlON 14-47
N·20
20·Lead Plastic DIP
SYMBOL
A
Az
b
b,
c
0
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.925
1.060
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060
5.33
4.95
2.93
0.356
0.558
1.77
1.15
0.204
0.381
23.50
26.90
7.62
8.25
6.10
7.11
2.548SC
5.05
3.18
3.81
0.38
1.52
14-48 PACKAGE INFORMA TlON
NOTES
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
N-24
24·Lead Plastic DIP
SYMBOL
A
Az
b
b,
c
0
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MAX
MIN
0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
1.125
1.275
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.060
0.015
5.33
2.93
4.95
0.356
0.558
1.77
1.15
0.204
0.381
32.30
28.60
7.62
8.25
7.11
6.10
2.54BSC
3.18
5.05
3.81
0.38
1.52
NOTES
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
III
PACKAGE INFORMA TlON 14-49
N-24A
24-Lead Plastic DIP (Double Width)
"1
1
24
E,
NOTE
SEE1
'~~~
SEATING
PLANE
SYMBOL
A
A2
b
b,
c
D
E
E,
e
L
L,
Q
I·
D
-olio-.
.10-
~.
I.=E~-L
l~~t·
~
~ ~~
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.250
0.125
0.195
0.014
0.022
0.030
0.070
0.008
0.015
1.150
1.290
0.600
0.625
0.485
0.580
0.100BSC
0.125
0.200
0.150
0.015
0.060
6.35
3.18
4.95
0.356
0.558
1.77
0.77
0.381
0.204
29.30
32.70
15.24
15.87
12.32
14.73
2.54BSC
3.18
5.05
3.81
0.38
1.52
14-50 PACKAGE INFORMA TION
NOTES
2
2
\~
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
N-28
28-Lead Plastic DIP
SYMBOL
A
A2
b
b,
c
0
E
E,
e
L
L,
Q
INCHES
MIN
MAX
MILLIMETERS
MAX
MIN
0.250
0.125
0.195
0.014
0.022
0.070
O.OOS
0.015
1.380
1.565
0.600
0.625
0.485
0.580
0.100BSC
0.125
0.200
0.150
0.015
0.060
6.35
4.95
3.18
0.356
0.558
1.77
0.381
0.204
35.10
39.70
15.24
15.87
12.32
14.73
2.54BSC
3.18
5.05
3.81
0.38
1.52
NOTES
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.
2
2
I
PACKAGE INFORMA TION
14-51
N-28A
28-Pin Plastic DIP
SEATING
PLANE
SYMBOL
A
b
c
0
E
E,
e
L
Q
a
INCHES
MIN
MAX
0.015
0.008
1.440
0.530
0.594
0.096
0.120
0.020
0°
0.200
0.020
0.012
1.450
0.550
0.606
0.105
0.175
0.060
15°
14-52 PACKAGE INFORMATION
MILLIMETERS
MIN
MAX
0.381
0.203
35.580
13.470
15.090
2.420
3.050
0.560
0°
5.080
0.508
0.305
36.830
13.970
15.400
2.670
4.450
1.580
15°
NOTES
3
3
2
4
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. Lead center when a is 0°. E, shall be measured at the
centerline of the leads.
3. All leads - increase maximum limit by 0.003" (0.08mml
measured at the center of the flat, when hot solder
dip lead finish is applied.
4. Twenty-six spaces.
N-40A
40·Pin Plastic DIP
NOTE:
LEADS ARE SOLDER-PLATED KOVAR OR ALLOY 42
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
A
0_015
0_040
0_008
0_200
0_025
0_060
0_015
-
b
b,
-
e
2.08
0.550
0.550
0.580
0.620
0.100BSC
L
L,
Q
0.120
0.140
0.015
SYMBOL
c
0
E
E,
S
S,
..
-
-
0.175
0.060
0.110
0.005
-
O·
15·
0_38
1_02
5_08
0_64
1_52
0.20
0.38
52.83
13.46
13.97
14.73
15.75
2.54BSC
3.05
4.45
3.56
0.38
1.52
2.79
0.13
O·
15·
III
-
-
PACKAGE INFORMATION 14-53
P-20A
20-Lead Plastic: Leaded Chip Carrier (PLCC)
19m
PIN 1
IDENTIFIER
18
U
B
SYMBOL
A
B
C
D
E
F
G
H
J
K
R
U
V
W
X
Y
14--54 PACKAGE INFORMA TION
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.025
0.040
0.085
0.110
0.013
0.021
Q.050BSC
0.026
0.032
0.015
0.025
0.290
0.330
0.350
0.356
0.350
0.356
0.042
0.048
0.042
O.o4a
0.042
0.056
0.020
9.78
10.02
9.78
10.02
4.19
4.57
0.64
1.01
2.16
2.79
0.33
0.53
1.27BSC
0.66
0.81
0.38
0.63
7.37
8.38
8.89
9.04
9.04
8.89
1.07
1.21
1.21
1.07
1.07
1.42
0.50
P-28A
28-Lead Plastic Leaded Chip Carrier (PLCC)
YR
PIN 1
IDENTIFIER
o
PIN 1
IDENTIFIER
TOP
VIEW
BOTTOM
VIEW
SYMBOL
A
B
C
0
E
F
G
H
J
K
R
U
V
W
X
Y
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.025
0.040
0.085
0.110
0.013
0.021
0.050BSC
0.026
0.032
0.015
0.025
0.390
0.430
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
0.020
12.32
12.57
12.32
12.57
4.19
4.57
0.64
1.01
2.79
2.16
0.33
0.53
1.27BSC
0.66
0.81
0.38
0.63
9.91
10.92
11.43
11.58
11.58
11.43
1.07
1.21
1.07
1.21
1.07
1.42
0.50
III
PACKAGE INFORMA TION 14-55
P-44A
44-Lead Plastic Leaded Chip Carrier (PLCC)
VR
PIN 1
IDENTIFIER
TOP
VIEW
SYMBOL
A
B
C
0
E
F
G
H
J
K
R
U
V
W
X
Y
14-56 PACKAGE INFORMA TION
INCHES
MAX
MIN
0.685 0.695
0.685 0.695
0.165 0.180
0.025 0.040
0.085 0.110
0.013 0.021
0.050 BSC
0.026 0.032
0.015 0.025
0.650 0.656
0.850 0.656
0.650 0.656
0.042 0.048
0.042 0.048
0.042 0.056
0.020
MILLIMETERS
MIN
MAX
17.40 17.65
17.40 17.65
4.19
4.57
0.64
1.01
2.16
2.79
0.33
0.53
1.27 BSC
0.66
0.81
0.63
0.38
16.51 16.66
16.51 16.66
16.51 16.66
1.21
1.07
1.21
1.07
1.42
1.07
0.50
Q-8
8-Lead Cerdip
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
II
MIN
INCHES
MAX
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.006
0"
0.200
0.023
0.070
0.015
0.405
0.310
0.320
0.110
0.200
0.060
0.055
15·
MILLIMETERS
MIN
MAX
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
0"
5.08
0.58
1.78
0.38
10.29
7.87
8.13
2.79
5.08
1.52
1.35
NOTES
7
2.7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when II is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.08mm)
measured at the center of the flat. when hot solder
dip lead finish is applied.
8. Six spaces.
III
15°
PACKAGE INFORMA TION 14-57
Q-14
14-Lead Cerdip
11--
-.f
S,
r
S
~~:::::: :1
~
s~
D
-01.
~j
~
L ~.
~
SEE
NOTE 7
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
MIN
INCHES
MAX
MILUMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.785
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
19.94
7.87
8.13
2.79
5.08
0.014
0.030
0.008
Q
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.005
ClI
0"
0.060
0.098
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
1.52
2.49
0.13
15°
14-58 PACKAGEINFORMATION
0"
15°
NOTES
7
2.7
7
4
4
6
8
3
5
5
NOTES
1. Index aree; a notch or a lead one identification mark
is locatad adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the bese plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four comers.
6. Lead center when ClI Is 0". E, shall be measurad at the
centerline of the leeds.
7. All leads - increase maximum limit by 0.003" 10.08mml
measured at the center of the flat. when hot solder
dip lead finish is applied.
8. Twelve spaces.
Q-16
16-Lead Cerdip
INCHES
SYMBOL
MIN
A
b
b,
c
D
E
E,
•L
L,
Q
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
S
S,
0.005
Cl
0"
MAX
MILLIMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.840
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
21.34
7.87
8.13
2.79
5.08
0.060
0.080
0.38
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
1.52
2.03
0.13
15°
0"
NOTES
7
2,7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead One identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
S. Applies to all four corners.
6. Lead center when Cl is 0·. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by O.003"(O.OSmml
measured at the center of the flat. when hot solder
dip lead finish is applied.
S. Fourteen spaces.
15°
PACKAGE INFORMA TlON 14-59
Q-18
18-LeadCerdip
11-- s,
r
-.j
~4: :::::::1
~
PLANE
~
D
JL
L
~I--
-oj
.1--
S
.
b,
L,
~.
E,
SEE
NOTE 7
SYMBOL
A
b
b,
c
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
0.200
0.023
0.070
0.015
0.960
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
24.38
7.87
8.13
2.79
5.08
0.014
0.030
0.008
D
E
E,
•L
L,
Q
S
S,
ex
0.220
0.290
0.090
0.125
0.150
0.015
0.005
0"
0.060
0.098
15°
14-60 PACKAGE INFORMA TlON
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
0.13
0"
1.52
2.49
15°
NOTES
7
2.7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when ex is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.08mm)
measured at the center of the flat. when hot solder
dip lead finish is applied.
8. Sixteen spaces.
Q-20
20·Lead Cerdip
1~S'
-.j
r
~~:I. :::::::::l·1
s
D
S~
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
ClI
MIN
~ .~
INCHES
MAX
MIWMETERS
MIN
MAX
0.200
0.023
0.070
0.015
1.060
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
26.92
7.87
8.13
2.79
5.08
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.005
0°
0.060
0.098
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
1.52
2.49
0.13
15°
0"
NOTES
7
2,7
7
4
4
6
8
3
5
5
JL
~.
E'.-oIl-SEE
NOTE 7
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
10.58mm} for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off·center lid, meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when ClI is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"10.08mm}
measured at the center of the flat, when hot solder
dip lead finish is applied.
8. Eighteen spaces.
15°
III
PACKAGE INFORMA TION
14-61
Q-22
22·Lead Cerdip
NOTE 7
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
a
INCHES
MAX
MIN
0.200
0.014 0.023
0.030 0.070
0.008 0.015
1.175
0.320 0.410
0.390 0.420
0.100 BSC
0.125 0.200
0.150
0.015 0.060
0.098
0.005
015°
MILLIMETERS
MIN
MAX
5.08
0.36
0.58
1.78
0.76
0.20
0.38
29.85
8.13 10.41
9.09 10.67
2.54BSC
3.18
5.08
3.81
0.38
1.52
2.4$
0.13
15°
0-
14-62 PACKAGE INFORMA TION
NOTES
7
2.7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58 mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun. .
5. Applies to all four corners.
6. Lead center when a is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003" (0.08 mm)
measured .at the center of the flat. when hot solder dip
lead finish is applied.
8. Twenty spaces.
Q-24
24-Lead Cerdip
-1'-5,
N~i:I- :::::::::::J
JL
~
D
PLANE
r5
-I
L
-*--b -II-
..j e I-
b,
L'
*-.of u
E,
c...\\r
5EE
NOTE 7
5YMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
MIN
INCHES
MAX
MIWMETER5
MIN
MAX
0.200
0.023
0.070
0.015
1.280
0.310
0.320
0.110
0.200
5.08
0.58
1.78
0.38
32.51
7.87
8.13
2.79
5.08
0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
5
5,
0.005
u
0"
0.060
0.098
0.36
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38
1.52
2.49
0.13
15°
0"
NOTES
7
2.7
7
4
4
6
8
3
5
5
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when u is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.OSmm)
measured at the center of the flat. when hot solder
dip lead finish is applied.
S. Twenty-two spaces.
15°
III
PACKAGE INFORMA TlON 14-63
Q-28
2S-Lead Cerdip
., !-S,
I-
-I
~Q
~~
SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q
S
S,
'"
MIN
~.~
INCHES
MAX
MILLIMETERS
MIN
MAX
0.225
0.026
0.070
0.018
1.490
0.610
0.620
0.110
0.200
5.72
0.66
1.78
0.46
37.85
15.49
15.75
2.79
5.08
0.014
0.030
0.008
0.500
0.590
0.090
0.125
0.150
0.015
0.36
0.76
0.20
12.70
14.99
2.29
3.18
3.81
0.38
0.100
0.005
0"
15°
14-64 PACKAGE INFORMATION
2.54
0.13
0°
15°
NOTES
7
2.7
7
4
4
6
8
3
5
5
JL~~.
\4--- E ----t
l ~-------L'
U
SEE
NOTE 7
,. . .
NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when u is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.08mm)
measured at the center of the flat. when hot solder
dip lead finish is applied.
8. Twenty-six spaces.
R-8
8-Lead Small Outline (SOIC)
SYMBOL
A
B
C
D
F
G
J
K
L
P
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
0.188
0.198
0.150
0.158
0.089
0.107
0.014
0.022
0.018
0.034
0.050BSC
0.007
0.015
0.005
0.011
0.195
0.205
0.224
0.248
4.77
5.03
3.81
4.01
2.26
2.72
0.56
0.36
0.46
0.86
1.27BSC
0.18
0.38
0.125
0.275
4.95
5.21
5.69
6.29
IE
PACKAGE INFORMATION 14-65
R-16
16-Lead Small Outline (SOIC)
SYMBOL
A
B
C
D
F
G
J
K
L
P
14-66 PACKAGE INFORMATION
INCHES
MIN
MAX
0.398 0.413
0.291 0.299
0.089 0.107
0.014 0.022
0.018 0.034
0.050 BSC
0.007 0.015
0.005 0.011
0.195 0.205
0.404 0.419
MILUMETERS
MIN
MAX
10.50
10.10
7.40
7.60
2.26
2.72
0.36
0.56
0.46
0.86
1.27 BSC
0.18
0.38
0.125 0.275
4.95
5.21
10.26
10.65
R·20
20-Lead Small Outline (SOIC)
SYMBOL
A
B
C
0
F
G
J
K
L
P
INCHES
MIN
MAX
0.496 0.512
0.291 0.299
0.089 0.107
0.014 0.022
0.018 0.034
0.050 BSC
0.007 0.015
0.005 0.011
0.195 0.205
0.404 0.419
MILLIMETERS
MIN
MAX
12.60
13.00
7.40
7.60
2.72
2.26
0.56
0.36
0.46
0.86
1.27 BSC
0.18
0.38
0.125 0.275
5.21
4.95
10.00
10.65
PACKAGE INFORMATION 14--67
Z-68
68·Lead Leaded Chip Carrier (Ceramic)
r------
I DDDDDDI
E
,PIN1
...rL...In....n.~'L..J""L.J""LJ"LILfLIL...rL...IrLrL.IL..J"LrI
= II
1
61
60
1
TOP VIEW
SYMBOL
A
b,
D
e
E
F
G
K
L
14--68 PACKAGE INFORMATION
INCHES
MIN
MAX
0.092 0.118
0.016 0.020
0.841 0.859
0.050 BSC
0.940 0.960
0.040
0.695 0.7OS
0.025
1.200 1.220
MILLIMETERS
MIN
MAX
2.337
2.997
0.452
0.462
21.361 21.819
1.27 BSC
23.876 24.384
1.016
17.663 17.907
0.625
30.476 30.984
F
Appendix
Contents
Page
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . .
· IS - 2
Product Families Still Available . . . . . . . . . . . . . . . .
· IS - 4
Substitution Guide for Product Families No Longer Available
· IS - 5
Technical Publications
· IS - 6
...
Worldwide Service Directory . . . . . . . . . . . . . . . . .
· IS - 9
APPENDIX
1~1
Ordering Guide
INTRODUCTION
This Ordering Guide should make it easy to order Analog Devices products, whether you're buying one IC op amp, a
multi-option subsystem, or 1000 each of 15 different items. It will help you:
1. Find the correct part number for the options you want.
2. Get a price quotation and place an order with us.
3. Know our warranty for components and subsystems.
For answers to further questions, call the nearest sales office (listed at the back of the book) or our main office in Norwood,
Mass. U.S.A. (617-329-4700).
MODEL NUMBERING
Many of the data sheets in the Databook for products having a number of standard options contain an Ordering Guide.
Use it to specify the correct part number for the exact combination of options you want. I.C. and hybrid part numbers are
created using one of these two systems:
Figure 1 shows the form of model number used for our proprietary standard monolithic les and many of our hybrids. It
consists of an "AD" (Analog Devices) prefix, a 3-to-5-digit model number*, an alphabetic performance/temperature-range
designator and a package designator. One or two additional letters may immediately follow the digits ("A" for second-generation
redesigned ICs, "DI" for dielectrica1ly isolated CMOS switches, e.g., AD536A}H, AD7512DIKD).
Figure 2 shows the somewhat different numbering scheme used by our Computer Labs Division for some hybrid circuits.
The number starts with a three-character alphabetic prefix, followed by a hyphen, a three- or four-digit number, and
alphabetic designators (as applicable) to indicate additional functional designations or options and packaging options.
I
ANALOG
DEVICES
PREFIX
[NANN]
AD XXXX A Y Z
r-
T-
I
I
THREE·TO· FIVE
DIGIT NUMBERS
II
1 OR 2 LETTERS
PROVIDE ADDITIONAL
GENERAL INFORMATION
A: SECOND GENERATION
01: DIELECTRICALLY
ISOLATED
r-
Z: OPERATION ON ±12V SUPPUES
PERFORMANCE·
TEMPERATURE RANGE
DESIGNATOR'
/
fl'-
PARAMETRIC
K PERFORMANCE
L
M BEST OVERALL
PERFORMANCE
J
o TO
+7O"C
- 25"C OR - 4O"C TO + 85"C
{:t~~~:~~E
C BEST OVERALL
PERFORMANCE
{
-55"C TO+125"C
t INCREASING
~ PERFORMANCE
U BEST OVERAU
PERFORMANCE
PACKAGE OPTIONS:
o
HERMETICALLY SEALED DIP.
CERAMIC OR METAL
E
LEADLESS CHIP CARRIER
F
CERAMICFLATPACK
H
METAL CAN. HERMETICALLY
SEALED
M
METAL·CAN DIP. HERMETICALLY
SEALED-COMPUTER LABS
N
PLASTIC DIP
P
PLASTIC LEADLESS CHIP
CARRIER
a
CERDIP
R
SMALL OUTLINE
CHIPS MONOLOTHIC CHIP'
EXAMPLES:
AD52'KCHIPS
AD7524AD
AD636ASH/883B
AD7512DIKD
'MONOLITHIC CMOS CHIPS IN THE AD75XX
SERIES WERE FORMERLY DESIGNATED
A075XX/COMICHIPS AND AD75XX/MIUCHIPS
AND MAY APPEAR ON PRICE LISTS WITH
THOSE DESIGNATIONS. CONSULT ANALOG
DEVICES FOR CURRENT PRICING OF AD7SXX
CHIPS.
Figure 1. Model-Number Designations for Standard
Analog Devices Monolithic and Hybrid Ie Products.
S, T and U Grades have the Added Suffix, /8838 for
Devices that Qualify to the Latest Revision of MIL-STD883, Level 8.
'For some models, the combination [digit][letter][two or three digits] is used insteacJ of ADXXXX, e.g., ZSSO.
15-2 APPENDIX
1
MILITARY OPTIONS
/883: SCREENED TO
MIl·STD 883. PER
METHOD 5008
B: SCREENED
TO MIl·STD 883
CLASS B
PACKAGE OPTION
OR H
'-- M
HERMETICALLV
SEALED
METAl·CASE DIP
ADDITIONAL FUNCTIONAL
DESIGNATION OR OPTION
e.g., E. C. A. ETC.
EXAMPLES:
JA S-
H Y B R I D ; U12
H
AID
CONVERTER
12-81T
HYBRID ; 1 j H
S-w
10D
15 E
~02
~
HERMEnC
METAL CASE
2.2p.s
HDS-1015EM
L- METAL
HERMETIC
CASE
g::NVERTER
10-81T5
15n$ TO 0.1%
(VOLTAGEI
ECl - - - - - - - - - - - '
HDS-1015EMB
L
100% SCREENED
TO MIl·STD 883
CLASSB
Figure 2. Computer Labs Video Hybrid Product Designations
SECOND SOURCE
In addition to our many proprietary products, we also manufacture devices that are fit-, form-, and function-compatible
(and often superior in performance and reliability) to populll1" products that originated elsewhere. For such products, we
usually add the prefix "AD" to the familiar model number (example: ADDACS5C-CBI-V).
ORDERING FROM ANALOG DEVICES
When placing an order, please provide specific information regarding model type, number, option designations, quantity,
ship-to and bill-to address. Prices quoted are list; they do not include applicable taxes, customs, or shipping charges. All
shipments are F.O.R factory. Please specify if air shipment is required.
Place your orders with our local sales office or representative, or directly with our customer service group located in the
Norwood facility. Orders and requests for quotations may be telephoned, sent via TWX or TELEX, or mailed. Orders
will be acknowledged when received; billing and delivery information is included.
Payments for new accounts, where open-account credit has not yet been established, will be C.O.D. or prepaid. On all
orders under fifty dollars ($50.00), a five-dollar ($5.00) processing charge is required.
When prepaid, orders should include $2.50 additional for packaging and postage (and a 5% sales tax on the price of the
goods if you are ordering for delivery to a destination in Massachusetts).
WARRANTY AND REPAIR CHARGE POLICIES
All Analog Devices, Inc., products are warranted against defects in workmanship and materials under normal use and
service for one year from the date of their shipment by Analog Devices, Inc., except that components obtained from others
are warranted only to the extent of the original manufacturers' warranties, if any, except for component test systems, which
have a ISO-day warranty, and ",MAC and MACSYM systems, which have a 9O-day warranty. This warranty does not
extend to any products which have been subjected to misuse, neglect, accident, or improper installation or application, or
which have been repaired or altered by others. Analog Devices' sole liability and the Purchaser's sole remedy under this
warranty is limited to repairing or replacing defective products. (The repair or replacement of defective products does not
extend the warranty period. This warranty does not apply to components which are normally consumed in operation or
which have a normal life inherently shorter than one year.) Analog Devices, Inc., shall not be liable for consequential
damages under any circumstances.
THE FOREGOING WARRANTY AND REMEDY ARE IN LIEU OF ALL OTHER REMEDIES AND ALL OTHER
WARRANTIES, WRITTEN OR ORAL, STATUTORY, EXPRESS, OR IMPLIED, INCLUDING ANY WARRANTY
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
APPENDIX 15-3
a
Product Families Not Included in the Oatabook
(But Still Available)
The information published in this Databook is intended to assist the user in choosing components for the design of new
equipment, using the most cost-effective products available from Analog Devices. The popular product types listed below
may have been designed into your circuits in the past, but they are no longer likely to be the most economic choice for
your new designs. Nevertheless, we recognize that it is often a wise choice to refrain from redesigning proven equipment,
and we are continuing to make these products available for use in existing designs or in designs for which they are uniquely
suitable. Data sheets on these products are available upon request.
Model
Model
Model
Model
Model
ADlOI
ADl08/208/308
AD 108N208A/308A
ADl1ll21l1311
AD293
AD294
AD351
AD370/371
AD503
ADS06
AD5lO
AD515
AD518
ADS28
ADS30
AD531
AD533
ADS35
AD545
AD567
AD611
AD651
AD801
AD2004
AD2006
AD2008
AD2009
AD2016
AD2020
AD2033
AD2036
AD2037
AD2038
AD2040
AD3554
AD3860
AD6012
AD7110
AD7118
AD7506
AD7507
AD7520
AD7521
AD7522
AD7523
AD7525
AD7530
AD7531
AD7541
AD7546
AD7550
AD7552
AD7571
AD7574
AD ADC-816
ADC-lOZ
ADC-12QZ
ADC-14I1l71
ADCllOO
ADCll05
ADCllll
ADC1l43
ADC-QM
AD DAC-08
ADG201
ADSHC-85
APIl620/1718
BDM 1615/16
BDM 1617
CAV-0920
CAV-1210
DAC-M
DAC-QS
DAC-QZ
DAC-I0Z
DACl009
DAC 11 08
DACl132
DACl146
DAC1420
DAC1422
DAC1423
DAS1128
DAS1150
DAS1151
DAS1155
DAS1l56
DRC1765/66
DSC1705/06
DTMI716/17
HAS-0802
HAS-l002
HDD-1409
HDH-0802
HDH-l003
HDH-1205
HDL-3806
HDS-0810E
HDS-0820
HDS-lOI5E
HDS-1025
HDS-1240E
IPA1751
IRDC1730
IRDC1731
IRDC1732
IRDC1733
MATV-0811
MATV-0816
MATV-0820
MCIl794
MOD-l005
MOD-I020
OSC1754
RDCI721
RTM Series
SAC1763
SBCD1752/53
SBCDl756/57
SCDX1623
SCMI677
SDCI604
SDC1700IRDC1700
SOC 1702/RDC 1702
SDCI704/RDCI704
SDCI71l1RDCI711
SDCI721
SDCl72SIRDCl725
SDCI726IRDCI726
SDC1768IRDC1768
SHA-2A
SHA-5
SHA-I114
SHA-ll34
SHA-l144
SSCTl621
STM Series
TSL1612
2B24
2B34
2B52
2B53
2B56
2B57A-l
2B58A
2B59A
2S20
40
44
45
46
48
50
51
52
118
171
233
234
235
260
261
272
273
275
276
277
285
288
310
426
428
429
432
433
434
435
436
440
442
450
452
458
460
606
610
756
903
906
915
926
947
959
968
15-4 APPENDIX
Substitution Guide for Product Families
No Longer Available
The products listed in the left-hand column are no longer available from Analog Devices. In many cases, comparable functions
and performance may be obtained with newer models, but - as a rule - they are not directly interchangeable. The closest
recommended Analog Devices equivalent, physically and electrically, is listed in the right-hand column. If no equivalent is
listed, or for further information, contact your local sales office.
Model
Closest
Recommended
Equivalent
Model
Closest
Recommended
Equivalent
Model
AD362
AD376
AD501
AD502
AD505
AD50S
AD511
ADS12
ADS 13
AD514
AD516
AD520
AD523
AD546
ADS55
AD559
AD6l2
AD614
ADSIO-S13
ADS14-S16
ADS1S
ADS20-S22
ADS30-S33
ADS35-S39
ADl40S
AD150S
AD2003
AD2022
AD2023
AD2024
AD2025
AD2027
AD202S
AD5010/6020
AD7115
AD7513
AD7516
AD7519
AD7527
AD7544
AD7555
AD7560
AD7570
AD75S3
ADC-SS
ADCll02
ADCll03
ADCl109
ADC1121
ADC1133
ADDAC100
ADG200
AD 1362
AD1376
AD711
AD711
AD509
AD517
AD711
AD711
AD711
AD711
AD711
AD524
ADS49
AD711
AD7519
None
ADS24
AD524
None
None
None
None
None
None
None
None
AD2021
None
None
None
None
None
None
AD9000
None
None
AD7510DI
None
None
None
None
None
None
None
None
None
None
None
AD7550
None
None
None
ADM5011506
ADP511
HTC-0300
MOD-1020
None
None
DAC-10Z
None
DAC12QS
None
AD7541
AD7533
HDL-3S06
HTC-0300
IRDC1730/1731
HAS-OS02
HAS-1002
HAS-OS02
HAS-1002
HAS-1202
None
None
None
None
None
None
None
AD7521
None
None
None
AD976S
HDM-1210
HDM-1210
None
None
HDS-OS20
HDS-OS20
None
None
HDS-IOZ5
HDS-1025
None
HDS-OSZO
None
HDS-1025
None
HDS-1250
None
RTI-711 Series
RTI-711 Series
RTI-711
SERDEX
SHA-IA
SHA-3
SHA-4
SHA-6
THC-0300
THC-0750
THC-1500
THS-0025
THS-0060
THS-0225
TSDC160S-1611
2N3954
2N5900
41
43
47
101 (Module)
102
106
107
lOS
110
III
114
115
120
141
142
143
146
149
153
161
163
165
170
ISO
lS3
220
230
231
232
274}
279
280
2S2}
2S3}
301 (Module)
302
311
350
ADM501
ADP501
ADSHM-5
CAV-1020
CAV-1202
DAC-100F
DAC-lOH
DACll06
DACll 12
DACll IS
DAC1122
DAC1l25
HDL-3S05
HTC-0500
IDC1703
MAH-OS01
MAH-100l
MAS-OS01
MAS-100I
MAS-1202
MDA-LB
MDA-LD
MDA-UB
MDA-UD
MDA-8H
MDA-I0H
MDA-10Z
MDA-llMF
MDH-OS70
MDH-1001
MDH-1202
MDMS-OS01
MDMS-1001
MDMS-ll01
MDS-OS15
MDS-OS15E
MDS-OS30
MDS-OS50
MDS-1020
MDS-1020E
MDS-104O
MDS-10S0
MDS-124O
MDSL-OS02
MDSL-OS25
MDSL-IOOZ
MDSL-1035
MDSL-120l
MDSL-1250
RTI-1200
RTI-1Z0l
RTI-1202
Closest
Recommended
Equivalent
fLMAC-5000
None
None
None
SHAl144
HTC-0300
None
None
HTC-0300
HTC-0300
None
TSL1612
None
None
AD515
ADS49
4S
45
4S
lIS
lIS
52
4S
AD30S
None
None
50
40
4S
52
AD3S2
SO
AD517
None
None
None
l71
ADOP-07
lS4
234
235
Model
424
427
454
456
602} 10
602}1O0
602K100
603
60S
752
901
907
90S
909
931
932
933
935
942
944
946
94S
956
971
Closest
Recommended
Equivalent
435/AD534
None
AD537
AD537
AD524
AD524
ADS24
AD524
ADS24
759
904
921
921
921
None
None
None
None
None
None
None
947
None
921
a
Z33
235
2S4}
286}
2S1
29ZA
292A
52
310 (Module)
None
None
APPENDIX 15-5
Technical Publications
TECHNICAL PUBLICATIONS
Analog Devices provides a wide array of FREE technical publications. These include Data Sheets for all products, Catalogs,
Application Notes and Guides and four serial publications.
Analog Productlog, a digest of new-production inforntation;
DSPatch", a newsletter about digital signal-processing (applications); Analog Briefings, current inforntation about products
for militarY/avionics and the status of reliability at ADI; and
Analog Dialogue, our technical magazine, with in-depth discussions of products, technologies and applications.
In addition to the free publications, five technical reference
books are available at reasonable cost. Subsystem products are
supported with hardware, software, and user documentation, at
prices related to content.
Brief descriptions of typical publications appear below. For copies of any items, to subscribe to any of our free serials or to
request any other publications, please get in touch with Analog
Devices or the nearest sales office.
CATALOGS
Data Acquisition Products Databooks. Contain selection
guides, data sheets and other useful information about all Analog Devices ICs, hybrids, modules and subsystem components recommended for new designs. The 1989/90 series
consists of:
DATA CONVERSION PRODUCTS DATABOOK-1989190.
Data Sheets and Selection Guides on D/A, AID, VIF, and FN
Converters, Sample-TrackIHold Amplifrers, Voltage References,
Multiplexers & Switches, Synchro-Resolver Converters, Data
Acquisition Subsystems, Application-Specific ICs. (Available
FREE.)
DSP PRODUCTS DATABOOK-1989. Data Sheets, Selection
Guides and Application Notes on DSP Microprocessor, Microcoded Support Components, Floating-Point Components and
Fixed-Point Components. (Available FREE.)
LINEAR PRODUCTS DATABOOK-1989/90. Data Sheets
and Selection Guides on Op Amps, Instrumentation Amplifiers,
Isolators, RMS-to-DC Converters, Multipliers/Dividers, Log!
Antilog Amplifiers, RMS-to-DC Converters, Comparators,
Temperature-Measuring Components and Transducers, Special
Function Components, Digital Panel Instruments, SignalConditioning Components and Subsystems. (Available FREE.)
MILITARY PRODUCTS DATABOOK. Information and
data on products processed in accordance with MIL-STD-883
Class B.
PERSONAL-COMPUTER BASED MEASUREMENT &
CONTROL SOLUTIONS-Hardware and Software. Data
acquisition for various buses, including PClXT1AT* and PS/2*
Micro Channel*, Modular Signal Conditioners, SignalConditioning Panels, Application Software, and Driver Software. Includes Do-It-Yourself Ordering Guides and Hot Line
(l-800-4-ANALOG).
POWER SUPPLIES-Linear SupplieseDC-DC Converters.
12-page short-form catalog listing acldc power supplies, modular
dc/de converters, power-supply test procedures, transients, thermal derating, mechanical outlines of packages and sockets.
1~6
APPENDIX
APPLICATION NOTES AND GUIDES
All are available upon request.
Application Notes.
AID Converters:
"Exploring the AD667 12-Bit Analog Output Port."
"Interacing the AD7572 to High-Speed DSP Processors."
"The AD7574 Analog-to-Microprocessor Interface."
Amplifiers:
"An IC Amplifier User's Guide to Decoupling, Grounding,
and Making Things Go Right for a Change."
"Applications of High-Performance BiFET Op Amps."
"A User's Guide to IC Instrumentation Amplifiers."
"How to Select Operational Amplifiers."
"How to Test Basic Operational Amplifier Parameters."
"Low-Cost Two-Chip Voltage-Controlled Amplifier and
Video Switch."
"Using the AD9610 Transimpedance Amplifier."
D/A Converters:
"AD7528 Dual 8-Bit CMOS DAC Application Note."
"Analog Panning Circuits Provide Almost Constant Output
Power."
"Bipolar Operation with the AD7572."
"Circuit Applications of the AD7226 Quad CMOS DAC."
"CMOS D/A Converter Circuits for +5-Volt Supplies."
"CMOS DACs and Operational Amplifiers Combine to
Build Programmable-Gain Amplifiers."
"Eighth Order Programmable Low-Pass Analog Filter
Using Dual 12-Bit DACs."
"Gain, Error, and Tempco of CMOS Multiplying DACs."
"Generate 4 Channels of Analog Output Using AD7542
12-Bit D/A Converters and Control the Lot with Only
Two Wires."
"How to Obtain the Best Performance from the AD7572."
"Interfacing dre AD7549 Dual 12-Bit DAC to the MCS-48
and MCS-51 Microcomputer Families."
"Simple DAC-Based Circuit Implements Constant Linear
Velocity (CLV) Motor Speed Control."
"Simple Interface Between D/A Converter and
Microcomputer Leads to Programmable Sine-Wave
Oscillator. "
"The AD7224 DAC Provides Programmable Voltages Over
Varying Ranges."
"Three-Phase Sine Wave Generation Using the AD7226
QuadDAC."
Digital Signal-Processing (Note: Four additional DSP Application Notes will be found in the 1989 DSP Products Databook);
"Considerations for Selecting a DSP Processor."
(ADSP-2100A vs. TMS32OC25)
"Implement a Cache Memory in Your Word-Slicec!!>
System."
"Implement a Writeable Control Store in Your
Word-Slice@ System."
"Loading an ADSP-2101 Program via the Serial Port."
"Sharing the Output Bus of the ADSP-1401 Microprogram
Sequencer."
DSPatch is a trademark of Analog Devices, Inc.
Word-Slice i. a registered trademark of Analog Devices, Inc.
PClXT/AT, PS/2 and Micro Channel are trademarks of International
Business Machines Corporation.
"Variable-Width Bit Reversing with the ADSP-1410
Address Generator."
Resolver-to-Digital Conversion:
"Circuit Applications of the 2S81 and 2S80 Resolverto-Digital Converters."
"Dynamic Characteristics of Tracking Converters."
"Dynamic Resolution-Switching on the 1S74 Resolverto-Digital Converter."
"Why the Velocity Output of the 1S74 and 1S64 Series RID
Converters Is Continuous and Step-Free Down to Zero
Speed."
Sample-Holds:
"Applying IC Sample-Hold Amplifiers."
"Generate 4 Channels of Analog Output Using AD7542
12-Bit D/A Converters and Control It All with Only Two
Wires."
Switches:
"ADG201Al202A and ADG2211222 Performance with
Reduced Power Supplies."
"Overvoltage Protection for the ADG5XXA Multiplexer
Series."
Temperature Measurement:
"A Cost-Effective Approach to Thermocouple Interfacing in
Industrial Systems."
"Use of the AD590 Temperature Transducer in a Remote
Sensing Application."
V/F Converters:
"Analog-to-Digital Conversion Using Voltage-to-Frequency
Converters (AD65l)."
"Operation and Applications of the AD654 IC V-to-F
Converter. "
Video Applications:
"Changing Your VGA Design from a 1711176 to an
ADV471."
"Improved PCB Layouts for Video RAM-DACs Can Use
Either PLCC or DIP Package Types."
"The AD9502 Video Signal Digitizer and Its Application."
"Video Formats & Required Load Terminations."
Application Guides.
Analog CMOS Switches and Multiplexers. A 16-page short-form
guide to high-speed CMOS switches, CMOS switches with
dielectric isolation and CMOS multiplexers. Also included are
reliability data and information on single-supply operation.
Applications Guide for Isolation Amplifiers and Signal Conditioners.
A 20-page guide to specifications and applications of galvanically
isolated amplifiers and signal conditioners for industrial, instrumentation and medical applications.
CMOS DAC Application Guide 3rd Edition by Phil Burton
(1989-64 pages). Introduction to CMOS DACs, Inside CMOS
DACs, Basic Application Circuits in Current-Steering Mode,
Single-Supply Operation Using Voltage-Switching Mode, The
Logic Interface, Applications.
ESD Prevention Manual- Protecting ICs from electrostatic discharges. Thirty pages of information that will assist the reader
in implementing an appropriate and effective program to assure
protection against electrostatic discharge (ESD) failures.
High-Speed Data Conversion - A 24-page short-form guide to
video and other high-speed AID and D/A converters and
accessories, in forms ranging from monolithic ICs to card-level
products.
RMS-to-DC Conversion Application Guide 2nd Edition by
C. Kitchin and L. Counts (1986-61 pages). RMS-DC Conversion: Theory, Basic Design Considerations; RMS Application
Circuits; Testing Critical Parameters; Input Buffer Amplifier
Requirements; Programs for Computing Errors, Ripple and
Settling Time.
Surface Mount IC-A 28 page guide to ICs in SO and PLCC
packages. Products include op amps, rms-to-dc converters,
DACs, ADCs, VFCs, sample-holds and CMOS switches.
DSPMANUALS
Available at no charge for single copies; write on letterhead.
ADSP·2100 Family Support Publications-for the ADSP-2100
and ADSP-2l0l single-chip signal processors.
ADSP-2100 USER'S MANUAL. Introduction, Computational
Units, Data Moves, Program Control, System Interface, Instruction Set Overview, Appendixes. 162 pages.
ADSP-2100 CROSS-SOFTWARE MANUAL. Overview, System Builder, Assembler, Linker, Simulator, PROM Splitter,
C Compiler, Instruction Set Overview, Appendixes. 240 pages
plus Programmer's Reference Card.
ADSP-2100 EMULATOR MANUAL. Overview, Installation,
Configuration, Operation, Development Examples, Trace
Buffer, Appendixes. 144 pages.
ADSP-2100 EVALUATION BOARD MANUAL. Overview;
Installation; Configuration; Operation; Analog Interface; Prototyping Connector; Demonstration Programs; Appendixes: Specification, Replacing Hardware, Terminal Emulation, Memory
Expansion, Demo Disk, Schematics/Data Sheets. 156 pages.
ADSP-2101 USER'S MANUAL-Architecture. Introduction,
Computational Units, Data Moves, Program Control, Timer,
Serial Ports, System Interface, Memory Interface, Instruction
Set Overview, Appendixes. 184 pages.
ADSP-2100 FAMILY APPLICATIONS HANDBOOK,
Volume 1. Introduction, Fixed-Point Arithmetic, Floating-Point
Arithmetic, Fixed-Coefficient Digital Filters, FFTs, Adaptive
Filters, Image Processing, Linear Predictive Speech Coding,
High-Speed Modem Algorithms, Bibliography. 178 pages.
ADSP-2100 FAMILY APPLICATIONS HANDBOOK,
Volume 2. Overview, Graphics, Multirate Filters, PCM,
ADPCM, Dual-Tone Multi-Frequency (DTMF). 248 pages.
ADSP-2100 FAMILY APPLICATIONS HANDBOOK,
Volume 3. Introduction, Fast Fourier Transforms, Memory
Interface, Multiprocessing, Host Interface, Sonar Beamforming.
168 pages.
Word·Slice User's Manual (ADSP-14Oll ADSP-1402 Program
Sequencers and ADSP-14l0 Address Generator). Introduction;
Program Sequencers: Internal Architecture, Jumps, Interrupt
Processing, System Interface, Instruction Set; ADSP-141O:
Internal Architecture, Addressing Operations, Precision Modes,
System Interface, Instruction Set. 218 pages.
APPENDIX 15-7
Technical Publications
TECHNICAL REFERENCE BOOKS-Can be purchased
from Analog Devices, Inc.; send check for indicated amount to
One Technology Way, P.O. Box 796, Norwood, MA 02062. If
more than one book is ordered, deduct a discount of $1 from
the price of each book. VISA accepted; phone (617) 461-3392.
ANALOG-DIGITAL CONVERSION HANDBOOK: Third
Edition, by the Engineering Staff of Analog Devices, edited by
Daniel H. Sheingold. Englewood Cliffs, NJ: Prentice-Hall
(1986). A comprehensive guide to AID and D/A converters and
their applications. This third edition of our classic is in hardcover and has more than 700 pages, an Index, a Bibliography,
and much new material, including: video-speed, synchroresolver, VlF, high-resolution, and logarithmic converters, ICs
for DSP, and a "Guide for the Troubled." Seven of its i2 chapters are totally i1ew.
$32.95
NEW-DIGITAL SIGNAL PROCESSING IN VLSI, by
Richard J. Higgins. Englewood Cliffs NJ: Prentice-Hall (1990).
An introductory 614-page guide for the engineer and scientist
.who needs to understand and use DSP algorithms and
special-purpose DSP hardware ICs-and the software tools
developed to carry them out efficiently. Real-World Signal
Processing; Sampled Signals and Systems; The DFT and the
FFT Algorithm; Digital Filters; The Bridge to VLSI; Real DSP
Hardware; Software Development for the DSP System; DSP
Applications; plus Bibliography and Index.
$38.00
15-8 APPENDIX
NONLINEAR CIRCUITS HANDBOOK: Designing with
Analog Function Modules and ICs, by the Engineering Staff of
Analog Devices, edited by Daniel H. Sheingold. Norwood MA:
Analog Devices, Inc. (1974). A 540-page guide to multiplying
and dividing, squaring and rooting, rms-to-dc conversion, and
multifunction devices. Principles, circuitry, performance, specifications, testing, and application of these devices-Contains 325
illustrations.
$5.95
SYNCHRO & RESOLVER CONVERSION, edited by Geoff
Boyes. Norwood, MA; Analog Devices, Inc. (1980). Principles
and practice of interfacing synchros, resolvers, and Inductosyns*
to digital and analog circuitry.
$11.50
TRANSDUCER INTERFACING HANDBOOK: A Guide to
Analog Signal Conditioning, edited by Daniel H. Sheingo!d. Norwood MA: Analog Devices, Inc. (1980). A book for the electronic engineer who must interface transducers for temperature,
pressure, force, level, or flow to electronics, these 260 pages tell
how transducers work-as circuit elements-and how to connect
them to electronic circuits for effective processing of their
signals.
$14.50
*lnduc:tosyn is a registered tmdemark of Farrand Industries, Inc.
Worldwide Service Directory
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*Analog Devices, Inc. Direct Sales Offices
WORLDWIDE HEADQUARTERS
One Technology Way, P.O. Box 9106, Norwood, Massachusetts 02062-9106 U.S.A.
Tel: (617) 329-4700, TWX: (710) 394-6577, FAX: (617) 326-8703, Telex: 924491
Cable: ANALOG NORWOODMASS
APPENDIX 15-9
Worldwide Service Directory
International
Australia
(02) 4383900
(613) 5931033
Austria
*(222) 885504
Belgium
*(3) 2371672
Brazil
(11) 531-9355
Denmark
*(42) 845800
Finland
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Holland
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Hong Kong
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People's Republic
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*(222) 885504
(Austria)
Singapore
(65) 2848537
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(1) 7543001
(3) 3007712
Sweden
*(8) 282740
Switzerland
*(22) 731-5760
*(1) 8200102
*Analog Devices, Inc. Direct Sales Offices
WORLDWIDE HEADQUARTERS
One Technology Way, P.O. Box 9106, Norwood, Massachusetts 02062-9106 U.S.A.
Tel: (617) 329-4700, TWX: (710) 394-6577, FAX: (617) 326-8703, Telex: 924491
Cable: ANALOG NORWOODMASS
15-10 APPENDIX
Taiwan
(2) 501-8170
Turkey
(1) 3372245
United Kingdom
*(932) 232222
*(932) 253320
(Sales)
*(1) 9411066
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America
*(617) 329-4700
West Germany
*(89) 570050
*(4181) 8051
*(721) 48567
*(30) 316441
*(221) 686006
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*(222) 885504
(Austria)
Product Index
Alpha-Numeric by Model Number
Model
Page·
AC2626 . . . . .
.. L
ADIOI . . . . .
· C 15-4
AD 108/208/308 .
· C 15-4
ADI08A1208A1308A .
. . . . . . C 15-4
ADI11I2111311 .
· .. C 15-4
AD202/204 .
L
HADl03N
L
ADlI0
L
L
ADl46
AD293
. . . . . . .
. C 15-4
. . . . . . .
. C 15-4
ADl94
ADl95
.......... L
AD345
· .. L
AD346
· C 6-5
AD351
· C 15-4
AD363
C 9-5
AD364
· C 9-5
AD365
· .. L
AD367
· .. C 9-13
AD368
· . . C 9-19
AD369
· . . C 9-19
AD370/371 .
· . C 15·4
AD380
L
AD381
· .. L
AD382
..... L
eAD386
· . . C 6-11
AD389
· C 6-25
AD390
· . C 2-13
AD392
· . C 2·21
AD394
· . C 2·27
AD395
· . . C 2-27
AD3%
· .. C 2-35
AD503
· . . C 15-4
ADS06
· . . C 15-4
ADS07
..... L
AD509
..... L
ADSI0
. . . . . . . C 15-4
AD515
. . . . . . . C 15·4
ADSI5A . .
......... L
AD517
.............. L
AD518
. . . . . . .
. . C 15-4
..................... L
AD521
AD522 . . . . . . . . . . . . . . . . . . . . . . . . . . L
AD524 . . . . . . . . . . . . . . . . . . . . . . . . . . L
L
AD526 . . . . . .
AD528
· C 15-4
AD530
· C 15·4
AD531
· C 15-4
AD532
... L
AD533
· C 15-4
AD534
... L
AD535
· C 15-4
AD536A . . . . • . .
... L
AD537 . . . . . . • .
.. C 4-5
Model
ADS38
ADS39
AD542
AD544
AD545
eeAD545A
HAD546
AD547
AD548
AD549
AD557
ADS58
AD561
AD562
ADS63
AD565A
AD566A .
ADS67 . . . . . . . . . . .
ADS68
ADS69
AD570
AD571
AD572
AD573
AD574A ..
AD575
AD578
AD579
AD580
AD581
AD582
AD583
...... .
...... .
AD584
ADS85
AD586
AD587
ADS 88
ADS 89
AD590
AD592
AD594
AD595
AD596
AD597
AD611
AD624
AD625
AD630
AD632
AD636
AD637
AD639
HAD640
AD642
Page·
L
L
L
L
· C 15-4
L
L
L
L
L
· . C 2-43
· . C 2-47
· . C 2-55
· . C 2-59
· C 2-59
· C 2-63
· C 2-63
· C 15-4
· . C 2-71
. . . C 2-83
· C 3-15
· C 3-15
· C 3-21
· C 3-29
. . . C 3-37
· C 3-49
· C 3-57
· C 3-63
· C 8-5
· C 8-9
· C 6-31
· C 6-35
· C 8-15
· C 6-37
· C 8-23
· C 8-31
· C 8-39
· C 8-51
L
L
L
L
L
L
· C 15-4
L
L
L
tim
L
L
L
*C = DafIJ ComJeTSion Produ£ts Databook, D = DSP Products DafIJbook, L = Linear Produ£ts DafIJbook .
• New product since publication of 1988 DafIJ ComJeTSion Produ£ts DafIJbook.
"New product since publication of 1988 Linear Products DafIJbook. Call or write for individual data sheet.
PRODUCTINDEX
1~1
Model
Page*
AD644 . . . . . . . . . . . . . . . . .
L
AD647 . . . . . . . . . • . . .
.. L
AD648 . . • . . . . . . . . .
.. L
.. C 4-13
AD650
AD651
.. C 15-4
. . . • . . . . . . . C 4-25
AD652
AD654
· •.. "
.. C 4-41
eAD662
· . . • .. .. C 2-95
AD664
C 2-103
AD667
· . . . .. . C 2-123
AD668
· . . . . . . . C 2-131
AD670
· . . . . . . . . C 3-69
AD673
· . . . . . . . . C 3-81
AD674A
· . . . .. .. C 3-89
AD678
· C 3-99
AD679
C 3-111
eAD684
· C 6-43
AD689
· C 8-55
L
AD693
AD707
L
L
AD708
AD711
L
L
AD712
L
AD713
L
AD736
L
AD737
AD741 Series .
L
AD744
L
L
AD746
C 2-135
AD767
C 3-123
AD770
eAD779
C 3-135
. .... L
AD790 . . . . • .
. . . . . . . C 15-4
AD801
AD821
............
L
........ .
.............
L
AD834
AD840
..........
L
AD841
...............
L
.....•... ...............
L
AD842
. .AD843
.......
L
eeAD844
L
AD845
L
L
AD846
L
AD847
L
AD848
AD849
L
AD890
L
L
AD891
ADl139 . . . . .
C 2-143
AD1145 ..
C 2-149
AD1147 ..
C 2-155
ADl148 ..
· . . . . .
C 2-155
eAD1154 ..
· . . . . .
. .•. C 6-51
AD1l70 ..
· . . • . . . . . . . C 3-147
Model
AD1175K . . .
eAD1330 . • . .
AD1332 ..
eAD1334 . . . .
eAD1362 . . . .
AD1376 . . • .
eAD1377 . . . .
AD1380 . . . .
ADI403/1403A
eADl678 . . . .
eAD1679.
eADI779,
eAD1856.
eADl860 .
AD2004 .
AD2006 .
AD2008.
AD2009.
AD2010.
AD2016.
AD2020.
AD2021.
AD2026.
AD2033.
AD2036.
AD2037.
AD2038.
AD2040.
AD2050.
AD2051 ..
AD2060.
AD2061.
AD2070.
AD2071 .
AD2700/2701l2702
AD2710/2712 .
AD3554 . . . .
AD3860 . . . .
AD5200 Series
AD5210 Series
AD5240 .
AD5539.
AD6012.
AD7110.
AD7111 ..
AD7118 ..
AD7224 ..
AD7225 ..
AD7226.
AD7228.
eAD7237.
AD724S .
eAD7247.
AD7248.
*C = Data Conversion Products Databook, D = DSP Products Databook, L = Linear Products Databook.
eNew product since publication of 1988 Data Conversion Products Databook.
"New product since publication of 1988 Linear Products Databook. Call or write for individual dsta sheet.
16-2 PRODUCTINDEX
Page*
. . . . . . . . . . . . . C 3-159
. . . . . . . . . . . . C 9-29
. . . . . . . . . . . . C 9-31
· . . . . . . . . . C 9-49
· . . • . . . . . . C 9-65
· . . . . .
C 3-167
· . . . . . . . . C 3-175
· . . . . .
. C 3-183
· . . . . • . . . . C 8-63
· . . . . . ..
C 3-191
· . . . . .
C 3-203
· . . . . . . . . C 3-215
C 2-161
C 2-171
· . C 15-4
· C 15-4
· . C 15-4
· . C 15-4
.... L
· C 15-4
· C 15-4
· .. L
· .. L
. . . . . . C 15-4
· C 15-4
· C IS-4
· C 15-4
· C 15-4
L
L
L
L
L
L
C 8-67
C 8-71
C 15-4
· C IS-4
C 3-227
C 3-227
C 3-547
. .. L
· C IS-4
· C 15-4
C 2-183
· C IS-4
C 2-189
C 2-193
C 2-199
C 2-20S
C 2-213
C 2-221
C 2-213
C 2-221
Model
eeAD7341.
eeAD7371.
AD7501.
AD7502 . . .
AD7503.
AD7506 . . .
AD7507 ..
AD7510DI
AD7511DI
AD7512DI
AD7520.
AD7521.
AD7522.
AD7523.
AD7524.
AD7525.
AD7528.
AD7530.
AD7531.
AD7533.
AD7534.
AD7535.
AD7536.
AD7537.
AD7538.
AD7541.
AD7541A .
AD7542.
AD7543 ..
AD7545 ..
AD7545A .
AD7546.
AD7547.
AD7548.
AD7549.
AD7550.
AD7552.
AD7569.
AD7571 .
AD7572 .
AD7574.
AD7575.
AD7576.
AD7578.
AD7579.
AD7580.
AD7581.
AD7582.
AD7590DI
AD7591DI
AD7592DI
AD7628 ..
eAD7669 ..
AD7672 . . . .
Page·
..
..
. .....
..
...........
.. ...... .. .. . ..
L
L
C 7-7
C 7-7
C 7-7
· C 15-4
· C 15-4
C 7-9
· . C 7-9
C 7-9
· C 15-4
· C 15-4
· C 15-4
· . C 15-4
C 2-235
· C 15-4
C 2-241
· C 15-4
· . C 15-4
C 2-245
C 2-251
C 2-255
C 2-259
C 2-263
C 2-267
· C 15-4
C 2-275
C 2-281
C 2-289
C 2-293
C 2-297
· C 15-4
C 2-301
C 2-305
C 2-317
· C 15-4
· C 15-4
C 3-233
· C 15-4
C 3-253
· C 15-4
C 3-265
C 3-269
C 3-273
C 3-279
C 3-279
C 3-295
C 3-303
· C 7-13
· C 7-13
· C 7-13
C 2-325
C 3-233
C 3-309
Page·
Model
eAD7769.
eAD7772 ..
AD7820 ..
AD7821 ..
AD7824 ..
AD7828 ..
eAD7840 ..
AD7845 ..
eAD7846 ..
eAD7848 ..
AD7870.
eAD7871 .
eAD7872 .
AD7878.
AD9000.
AD9002.
AD9003.
eAD9005 ..
eAD9006 ..
eAD9011 . . .
eAD9012 ..
eAD9016 ..
eAD9028 ..
eAD9038 .. · .....
eAD9048 ..
eAD9300 ..
AD9500 ..
eeAD9501 ..
AD9502 .. · ......
AD9521 .. · ......
AD9610 . . .
AD9611 . . . . .
-AD9615 . . . . .
AD9685/87 . . .
AD9686 . . . . .
AD9688 ..
_AD9696 ..
eeAD9698 ..
AD9700 ..
AD9701 ..
AD9702 ..
AD9703 ..
eAD9712 ..
eAD9713 ..
AD9768 ..
_AD9901 ..
AD75003 .
AD75004 .
· ......
.........
· .....
· .....
· .....
......
·
·
·
AD96685/87
·
AD ADC71172
AD ADC80
AD ADC84/85
AD ADC-816
ADC-lOZ. · .......
·
·
C 3-325
C 3-341
C 3-357
C 3-367
C 3-379
C 3-379
C 2-329
C 2-345
C 2-357
C 2-371
C 3-391
C 3-407
C 3-407
C 3-419
C 3-435
C 3-443
C 3-451
C 3-459
C 3-467
C 3-483
C 3-489
C 3-467
C 3-497
C 3-497
C 3-509
· C 7-17
· .. L
· .. L
C 3-517
L
L
L
L
L
L
C 3-525
· .. L
· .. L
C 2-379
C 2-385
C 2-391
C 2-395
C 2-399
C 2-399
C 2-403
... L
. C 11-1
. C 11-1
... L
C 3-531
C 3-539
C 3-457
. C 15-4
. C 15-4
*C = Data Con...monProducts Databook, D = DSP Products Databook, L = Linear Products Dalabook.
eNew product since publication of 1988 Dala Con...mon Products Dalabook.
eeNew product since publication of 1988 Linear Products Dalabook. Can or write for individual data sbeet.
PRODUCTINDEX 16-3
I
Model
Page·
ADC-12QZ . . . . . . . . . . . . • . . . . . . . . . C 15-4
ADC-14I1171 . . . . . . . . . . • . . . . . . • . . • C 15-4
ADC1100 . . . . . . . . . • . . . . . . . . . . . . . C 15-4
ADC110S . . . . . . . . . . . . . . . . . . . . . .. C 15-4
ADCllll • . . . . . . . . . . . . . . . . . . . . • . C 15-4
ADC 1130111 31 . . . . • . . . . . . . . • . . • . . C 3-555
ADCl140 . . . . • . . . • . . . . . . . . . . . . . C 3-559
ADC1143 . . . . . . . . . . . . . . . . . . • . . .. C 15-4
ADC-QM . . . . . . . . . . . . • . . . . . . . . . . C 15-4
AD DAC08 . . . . . . . . . . . . . . . . . . . .. C 15-4
AD DAC71172 . . . . . . . . . . . . . • . . . . . C 2-407
AD DAC80 . . . . . . . . • . . . . . • . . . . . C 2-411
AD DAC85 . . . . . . . . . . . . . . . . . . . . C 2-411
AD DAC87 . . . . . . . . . . . . . . . . . . . . C 2-411
ADDS-21XX (Hardware) . . . . . . . . . . . . . . . . D
ADDS-21XX (Software) . . . . . . . . . . . . . . . .. D
ADG201 . . . . . . . . . . . . . . . . . . . . . . . C 15-4
ADG201A . . . . . . . . . . . . . . . . . . . • . . C 7-25
eADG20IHS . . . . . . . . . . . . • . . . . . . • . . C 7-29
ADG202A . • . . . . . . . . . . . . . . . . . . . . C 7-25
ADG211A . . . . • . . . . . . . . . . . . . . . . . C 7-37
ADG212A . . . . . . . . . . . . . . . . . . . . . . C 7-37
ADG221 . . . . . . . . . . . . . . . . . . . . . . . C 7-41
ADG222 . . . . . . . . . . . . . . . . . . . . . . . C 7-41
ADG506A . . . . . . . . . . . . . . . . . . . . . . C 7-45
ADGS07A . . . . . . . . . . . . . . . . . . . . • . C 7-45
ADGS08A . . . . . . . . . . . . • . . . . . . . . . C 7-53
ADG509A . . • . . . • . . . . . . . . . . . . . . . C 7-53
ADGS26A . . • . . . . . . . . . . . . . . . . . . . C 7-57
ADGS27A . . . . . . . . . . . . . . . . . . . . . . C 7-57
ADG528A . . . . . . . . . . . . . . . . . . . . . . C 7-65
ADG529A . . • . . . . . . . . . . . . . . . . . . . C 7-65
ADLH0032G/CG . . . . . . . . . . . . . . . . . . . .. L
ADLHOO33G/CG . . . . . . . . . . . . . . . . . . . .. L
AD OP-07 . . . . . . . . . . . . . . . . . . . . . . . . L
AD OP-27 . . . . . . . . . . . . . . . . . . . . . . . . L
AD OP-37 • . . . . . . . . . . . . . . . . . . . . . . . L
ADREFOI . . . . . . . . . . . . . . . . . . . . . . C 8-75
ADREF02 . . . . . . . . . . . • . . . . . . . . . . C 8-75
ADSHC-8S . . . . . . . . . . . . . . . . . . . . . . C 15-4
ADSP-l008A . . . . . . . . . . . . . . . . . . . . . .. D
ADSP-l009A . . . . . . . . . . . . . . . . . . . . . .. D
ADSP-I0I0A . . . . . . . . . . . . . . . . . . . . . .. D
ADSP-IOIOB . . . . . . . . . . . . . . . . . . . . . .. D
ADSP-I012A . . . . . . . . . . . . . . . . . . • . . .. D
ADSP-I016A . . . . . . . . • . . . . . . . . . . . . .. D
ADSP-I024A . . • . . . . . . . . . . . . . . . . . . .. D
ADSP-I080A . . . . . . . . • . . . . . . . . . . . . .• D
ADSP-I081A . . . . . . . . • . . . . . . . . . . . . .. D
ADSP-llOI . . . . . . . . . . . . . . . . . . . . . . .. D
ADSP-lllOA . . . . . . . . . . . . . . . . . . . . . .• D
ADSP-I401 • . . . . . . . . . • . . . . . • . . . . • .. D
ADSP-I402 . . . . . . . . . . . . . . . . . . . . . . .. D
ADSP-1410 . . . . . . • . . . . . . . . . . . . . . . .. D
Model
*C =Data ConfJerlion Prod""/S Databook, D =DSP Prod""/S Databook, L =Linear Prod""/S Databaak.
eNew product since publication of 1988 Data CtmfIII'Sion Produers Databook .
. .New product since pUblication of 1988 Linear PrDduc/S Databook. Call or write for individual data sheet.
16-4 PRODUCTINDEX
Page·
ADSP-2100 • . . . . . . . . . . . • . . . . . . . . . .. D
ADSP-2100A . . . . . • . . . . . . . . . . . . . . . .. D
ADSP-2IOI . . . . . . . . . . . . . . . . . . . . . . .. D
ADSP-2IOI Emulator . . . . . . . . . • . • . . . . . . D
ADSP-2102 . . . . . . . . . . . . . . . . . . • . . • .. D
ADSP-3128A . . . . . . . . . . . . . . . . . . . . . .. D
ADSP-3201l02 .. . . . . . . . . . . . . . . . . . . .. D
ADSP-3210/11 . . . . . . . • . . . • . . . . . . . . . . D
ADSP-3212 . . • . • . . . . . . . . • . . . . . . . . .. D
ADSP-3220121 . . . . • . . . . • . . . • . . . . • . . . D
ADSP-3222 . . . . . . . . . . • . . . . . . . . . . . .. D
ADV4S3 . . . . . . . . . . . . . , . ' . . . . . . C 2-421
ADV471 . . . . . . . . . . . . . . . • . . . . . . C 2-441
ADV476 . . . . . . . . . . . . . . . . . . . . . . C 2-431
ADV478 . . . . . . . . . . . . . . . . . . • . . . C 2-441
ADVFC32 . . . . . . . . . . . . . . . . . . . . . . C 4-49
APIl620/1718 . . . . . . • . . . . . . . . . . . . • . C 15-4
BDM 1615/1616 . . • . . . . . . . . . . . . . . . . C 15-4
BDM 1617 . . . . . . . . . . . . . . . . . . . . . . C 15-4
CAV-0920 . . . . . . . . . . . . • . . . . . . . . . C 15-4
CAV-I040 . • . . . . . . . . . . . . . . . . . . . C 3-563
CAV-1205 . . . . . . . . . . . . . . . . . . . . . C 3-567
CAV-1210 . . . . . . . . . . . . . . . . . . . . . . C 15-4
CAV-1220 . . . . . . . . . . • . . . . . . . . . . C 3-569
DAC-M . . . . . . . . . . . . . . . . . . . . . . . . C 15-4
DAC-QS . . . . . . . . . . . . . . . . . . . . . . . C 15-4
DAC-QZ . . . . • . . . . • . . . . . • • . . . . . . C 15-4
DAC-08 (see AD DAC-08)
DAC-I0Z . . . . . . . . . . . . . . . . . . . . . . . C 15-4
DAC71172 (see AD DAC71I72)
DAC80 (see AD DAC80)
DAC8S (see AD DAC8S)
DAC87 (see AD DAC87)
DACl009 . . . . . . . . . . . . • • . . . . . . . . . C 15-4
DACll08 . . . . . . . . . . . • . . . . . . . . . . . C 15-4
DACll32 • . . . . . . . . . . . . . . . . • . . . . . C 15-4
DAC1136 . . . . . . . . . . . • . . . . . . . . . . C 2-453
DACl138 . • . . . . . . . . . • . . . . . . . . . . C 2-453
DACll46 . . . . . • . . . . . • . . . . . . . . . . . C 15-4
DACI420 . . . • . . . . . . . • . . . . . . • . . . . C 15-4
DAC1422 . . . . . • . . . • . . . . • . . . . . . .• C 15-4
DACI423 • . . . . . • . . . . . . . • . . . . . . . . C 15-4
DASlI28 . . . . . . . . . . . . . . . . • . . . . • . C 15-4
DAS1l50 . . . . . . . . . . . . . . . • . . . . . . . C 15-4
DASlI51 . • . . . . . . . • . . • . • . . . . . . . . C 15-4
DASllS2 . . . . . . . . . . . . • . • . . . . ..... C 9-73
DASlI53 . . . . . . . . . . . . . . . . . . . . . . . C 9-73
DAS1l5S • . . . . • . . . . . . • . . . . . . . • • . C 15-4
DASlIS6 . . . . . . . . . . . . • . . . . . . . . . . C15-4
DAS11S7 . . . . • . • . . . . . . . . . . . . . . . . C .9-77
DAS1l58 . . . . . . . . • . . . . . . . . . . . . . . C 9-77
DASlI59 . . . . . . • . . . . . . . . . • . . . . . . C 9-77
DRCI74S/46 .. . . . . . . . . • . . . . . . . . .. C 5-7
DRC1765/66 . • . . . • . • . . • . . . . . . . . . . C 15-4
DSC170S/06 . . . . . . . . . . . . . . . . . . . . . C 15-4
Model
Page·
DTM1716/17 . . . . . . . . . . . . . . . . . . . . . C 15-4
HAS-0802 . . .
. . C 15-4
HAS-1002 . . .
. . C 15-4
HAS-120 1 . . .
C 3-573
HAS-1202/1202A
C 3-579
HAS-1204
C 3-583
HAS-I409 ..
. . . . . . . . . . . . . . . . C 3-587
HDD-1206 . .
. . . . . . . . . . . . . . . . C 2-459
HDD-I409 . .
. . . . . . . . . . . . . . . . . C 15-4
HDG Series . . . . . . . . . . . . . . . . . . . . C 2-463
HDG-0807 . . . . . . . . . . . . . . . . . . . . . C 2-467
HDH-0802
. . . . . . . . . . . . . . . . . . . C 15-4
HDH-1003
. C 15-4
HDH-1205
. . C 15-4
HDL-3806
. . . . . . . . . . . . . . . . . . . C 15-4
HDM-121O
. . . . . . . . . . . . . . . . . . . C 2-471
HDS-08IOE. .
. . . . . ..
.. . . . . C 15-4
HDS-0820 . . . . . . . . . . . . . . . . . . . . . . C 15-4
HDS-101SE . . . . . . . . . . . . . . . . . . . . . . C 15-4
HDS-I025 .
. C 15-4
HDS-1240E. . . . . .
. .. C 15-4
HDS-1250 . . . . . . . . . . . . . . . . . . . . . C 2-477
HOS-050/0S0Al05OC . . . . . . . . . . . . . . . . . .. L
HOS-06O . . . .
L
HOS-100AHlSH . . . . . . . . . . . . . . . . . . . .. L
HOS-200 . . . . . . . . . . . . . . . . . . . . . . . . . L
HTC-0300A.
. . . . . . . . . . . . . . . . . C 6-33
HTS-00I0
. . . . . . . . . . . . . . . C 6-61
HTS-0025 . . . . . . . . . . . . . . . . . . . . . . C 6-67
IPA1751 . . . . . . . . . . . . . . . . . . . . . . . C 15-4
IPA1764 . . .
.. . . . . . . . . . . . .. .. C 5-15
IRDC1730 . . . . . . . . . . . . . . . . . . . . . . C 15-4
IRDC1731 . . . . . . . . . . . . . . . . . . . . . . C 15-4
IRDC1732
. . . C 15-4
IRDC1733
. . . . . . . . .
. . . . C 15-4
LTS-2020 . . . . . . . . . . . . . . . . . . . . . . . C 13-1
MATV-0811 . . . . . . . . . . . . . . . . . . . . . C 15-4
MATV-0816 . . . . . . . . . . . . . .
. C 15-4
MATV-0820 . . . . . . . . . . . . . . . . . . . . . C 15-4
MCIl794 . . . . . . . . . . . . . . . . . . . . . . . C 15-4
MOD-l00S
. C 15-4
MOD-I020 . .
. C 15-4
MOD-1205 . . . . . . . . . . . . . . . . . . . . . C 3-593
OSC1754 . . . . . . . . . . . . . . . . . . . . . . . C 15-4
OSC1758 . . . . . .
. C 5-17
RDCI721 . . . . . .
. C 15-4
RDC1740/174111742
. C 5-19
RTI-600 . . . . . .
. C 10-4
RTI-602
.
.
. . C 10-4
RTI-711 . . . . . . . . . . . . . . . . . . . . . . . C 10-4
RTI-724 . . . . . . . . . . . . . . . . . . . . . . . C 10-4
RTI-732
. C 10-4
RTI-800
. . C 10-2
RTI-802 . . . . . . . . . . . . . . . . . . . . . . . C 10-2
RTI-815 . . . . . . . . . . . . . . . . . . . . . .. C 10-2
Page·
Model
RTI-817 . . . . . . . . . . . . . . . . . . . .
.
RTI-820
.
RTI-850
.
RTI-860
.
RTI-1225
.
RTI-1226 . . .
.
RTI-126O . . . . . . . . . . . . . . . . . . . . . . .
RTI-1262 . . . . . . . . . . . . . . . . . . . . . . .
RTI-1263 .
.
RTI-1266 . . . . .
.
RTI-1267 . . . . .
.
RTI-1270 . . . . .
.
RTI-1280 . .
.
RTI-1281 . . . . . . . . . . . . . . . . . . . . . . .
RTI-1282 . . . . . . . . . . . . . . . . . . . . . . .
RTI-1287 . .
. .
RTM Series . . .
. .
SAC1763 . . . . .
. .
SBCDl752/53 . . .
. .
SBCDl756/57 . .
.
SCDX1623 . . . . . . . . . . . . . ..
.....
SCMI677 . . . . . . . . . . . . . . . . . . . . . . .
SDC1604 . . . . . .
. . . . .
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
10-2
10-2
10-2
10-2
10-3
10-3
10-3
10-3
10-3
10-3
10-3
10-3
10-3
10-3
10-3
10-3
15-4
15-4
15-4
15-4
15-4
15-4
15-4
SDCI700/RDCI700. . .
. .
15-4
SDC1702/RDC1702 . . . . . . . . . . . . . . . . . .
15-4
SDCI704/RDCI704 . . . . . . . . . . . . . . . . . .
15-4
SDCI71l1RDCI711 . . .
. .
15-4
SDCI721 . . . . . . . . . . . . . . . . . . . . . . .
15-4
SDCI725/RDCI725 . . . . . . . . . . . . . . . . . .
15-4
SDCI726/RDCI726.
. .
15-4
SDC1740/174111742 ..
. .
5-19
SDC17681RDC1768. . .
. ....
15-4
SHA-2A . . . . . . . .
. . . ..
15-4
SHA-5 . . . .
.
15-4
SHA-1ll4 . . . . . . . . . . . . . . .
. ....
15-4
SHA-I134 . . . . . . . . . . . . . . . . . . . . . .
15-4
SHAl144 . . . . . . .
. . .
15-4
SSCTl621 . . .
. .
15-4
STM Series. . . . . .
. . . . . ..
15-4
TSL1612 . . . . . . .
. . . . . . .
15-4
IB21
L
IB22 . . . . . . . . . . . . .
. . . . . . . .. L
IB31 . . . . . . . . . . . . . . . . . . . . . . . . . . . L
IB32
. . . . . . . .
L
IB41
L
L
lB51
. . . . . . • .
IS14
. . . . . . . .
. .. C 5-27
IS20
. ...
. . . . . . .
. . C 5-35
IS24 . . . . . . . . . . . . . . . . . . . . . . . . . C 5-27
IS40 . . . . . . . . . . . . . . . . . . . . . . . . . C 5-35
IS44
. . . . ..
. . . . . . . . .
. . C 5-27
IS60
. . . . . .
. . . . . . .
. . C 5-35
IS61
. . . . . .
. . C 5-35
IS64
. . . . . .
. . . . . . .
. . C 5-27
*C =Data Con""rsion Prodlll:ts Databook, D = DSP Prodlll:ts Databook, L = Linear Products Databaak.
-New product since publication of 1988 Data Con_non Prodlll:ts Databook •
. .New product since pUblication of 1988 Linear Products Databook. Call or write for individual data sheet.
PRODUCTINDEX 16-5
I
page*
Model
. . . . . . . . . . . . . . . . . . . . C 5-43
IS74
L
2B20
... L
2B22
... L
2B23
2B24
· C 15-4
2B30
· .. L
2B31
· .. L
.. C 15-4
2B34
.. C 12-1
2B35
... L
2B50
2B52
· C 15-4
2B53
· C 15-4
2B54
'"
L
... L
2B55
2B56
· C 15-4
2B57A-l .
· C 15-4
. . . C 15-4
2B58A ..
. . . C 15-4
2B59A ..
... L
2B Series.
2S20
· C 15-4
. . . . . . . . .
. C 5-51
2S50
. . . . . . . . . . . . . . . . . C 5-53
2S54 · . . . . .
. . . . . . . . . . . . . . . . . C 5-53
2S56 · . . . . .
e2S58 · . . . . . . . . . • . . . . . . . . . . . . . . C 5-53
.. .. ..
. C 5-65
2S80
2S81 . . . . . . .
. . . . . . .. . C 5-77
.. . . . . . C 5-89
2S82
3B Series.
L
4B Series.
'"
L
. .. L
5B Series.
C 5-101
5S70 .. .
5S72 .. .
C 5-101
-6B Series.
... L
C 5-103
e6S04 ..
40.
· C 15-4
44.
· C 15-4
45.
· C 15-4
46.
· C 15-4
48 .
. . . . . .
. C 15-4
50 . .
. C 15-4
51 . .
. C 15-4
52 . .
. C 15-4
U8
. C 15-4
171
. . . . . . . . . . .
. C 15-4
233
. . . . . . . . . . . .
. C 15-4
234
. . . . . . . . . .
. . . . C 15-4
235
. . . . . . . . . .
. C 15-4
260
. . . . . . . . .
. . . . C 15-4
261
. . . . . . . . . . . . .
. . . . C 15-4
. . C 15-4
272
. . • . • . • . . . . .
. . . . . . . . . . . . . . . . . . . . . . C 15-4
273
. . . . . . . . . . . . . . . . . . . . . . C 15-4
275
. . . . . . . . . . . . . . • . • • . . • C 15-4
276
277 . . . . . . . . . . . . . . . . • . . . . . . . . . C 15-4
284J
Model
285 .
286J/281
288 .. .
289 .. .
290A/292A . . .
310
426
428
429
432
433
434
435
436
440
442
450
451
452
453
458
460
606
610
7551759 •
756 .. .
757 .. .
902/902-2
903
904
905
906
915
920
921
922
923
925
926
927
928
940
941
...... .
943 . . . . . . . .
945
947
949
951
952
953 . . . . . .
955 . . . . . .
958
959
·C = Data CcnwersionProdru:ts Databook, D =DSP Products Databook, L = Linear Products Databook.
eNew product since publication of 1988 Data C07fI)ersion Prodru:ts Databook.
"New product since publication of 1988 Linear Products Databook. Coil or write for individual data sheet.
16-6 PRODUCTINDEX
Page*
..
L
· C 15-4
... L
· . C 15-4
....... L
....... L
· . . . . . . . . C 15-4
· . . . . C 15-4
· . . . . C 15-4
· . . . . . . . . . . C 15-4
· . . . . C 15-4
. . . C 15-4
· . . . . . C 15-4
· . . . . . C 15-4
· . . . . . C 15-4
. . . C 15-4
· . . . . . C 15-4
· . . . . . C 15-4
.. . . . . C 4-2
· C 15-4
· . . . . . C 4-2
· . . . . . C 15-4
· . . . . . C 15-4
· C 15-4
· . . . C 15-4
. ..... L
· . . . C 15-4
. .. L
· C 12-1
· C 15-4
· C 12-1
· C 12-1
· C 15-4
· . C 15-4
· . . . . . . . C 12-1
· . C 12-1
· . . . . . . . C 12-1
. . . . . . . C 12-1
· . . . . . . . . . . C 12-1
· . . . . .
. . C 15-4
· . . . . . . . C 12-1
. . . . . . . . . . . . . . C 12-1
· . . . . . . . . C 12-2
· . . . . . . . . C12-2
· . . . . . . . . C 12-2
· C 12-2
· C 15-4
· C 12-2
· C 12-2
. . . . . . . . . . C 12-1
. . . . . . . C 12-2
· . . . . C12-1
· . . . C 12-2
· . . . . C 15-4
Model
960
962
964
965
966
967
968
Page·
C
. C
C
C
C
C
C
12-2
12-2
12-2
12-2
12-2
12-2
15-4
Page·
Model
970
972
973
974
975
976
977
·
·
·
·
·
C
C
C
C
C
C
C
12-1
12-1
12-1
12-1
12-1
12-1
12-1
·C = Data Conversion Products Databook, D = DSP Products Databook, L = Linear Products Databook.
eNew product since publication of 1988 Data Conversion Products Databook .
. .New product since publication of 1988 Linear Products Databook. Call or write for individual data sheet.
PRODUCTINDEX 16-7
16-8 PRODUCTINDEX
•
G 1182a-175- 7/89
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