1989_Chips_And_Technologies_Short_Form_Catalog 1989 Chips And Technologies Short Form Catalog

User Manual: 1989_Chips_And_Technologies_Short_Form_Catalog

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SHORT FORM CATALOG
FALL 1989

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CHIPS AND TECHNOLOGIES, INC. IS
THE WORLD'S LEADING SUPPLIER OF
PROPRIETARY VLSI HARDWARE AND
INTEGRATED SOFTWARE SOLUTIONS
FOR HIGH PERFORMANCE MICROCOMPUTER SYSTEMS BASED ON EVOLVING
INDUSTRY STANDARD ARCHITECTURES.
CHIPSANDTECHNOLOGIESPROVIDES
A BROAD RANGE OF VLSI SILICON
PRODUCTS, INTEGRATED SOFTWARE
SUPPOR~ AND COMPLETE SYSTEM
DESIGN SERVICES SPANNING ENTRYLEVEL, MID-RANGE, AND HIGH-PERFORMANCE APPLICATIONS IN NOTEBOOK, LAPTOP AND DESKTOP COMPUTERS.
THE FOLLOWING PAGES GIVESA BRIEF
OVERVIEW OF CHIPS AND TECHNOLOGIES' LATEST DEVELOPMENTS IN
COMPLETE MICROCOMPUTER SYSTEMS SOLUTIONS. FOR MORE INFORMATION ON THESE AND OTHER CHIPS
AND TECHNOLOGIES PRODUCTS,
PLEASE CONTACT THE CHIPS SALES
OFFICE IN YOUR AREA LISTED IN THE
BACK OF THIS CATALOG.

CHiPS _______________
PRODUCT INDEX
ENTRY-LEVEL CHIPSet SOLUTIONS
Systems Logic

82C100
82C230
82C235

Super XT System Controller
High Peformance Model 30 Controller
SCAT Single Chip AT System Controller

Graphics

82C451

Integrated VGA Controller

Communications

82C578
82C606

Single Chip "3270" Terminal Controller
CHIPSpak Multifunction Controller

Mass Storage

82C710
82C785

Multifunction Floppy Controller
SCAT Single Chip AT-Compatible Hard Disk Controller

Integrated Software Operation

OC82C235
DR82C235

SCAT Single Chip AT-Compatible Bios
SCAT Single Chip AT-Compatible EMS Driver Kit

MID·RANGE CHIPSet SOLUTIONS
Systems Logic

CS8221
CS8281
CHIPS/250
82C611/82C612

82C614

NEAT New Enhanced AT-Compatible CHIPSet
NEATsx New Enhanced AT-Compatible CHIPSet
PS/2 Model 50/60-Compatible CHIPSet
MicroCHIPS Micro Channel Interface
MicroCHIPS Bus Master

Graphics

82C451

Integrated VGA Controller

Communications

82C574
82C575
82C578
82C601

Micro Channel Interface Chip
Communication Micro Channel Interface Chip
Single Chip "3270" Terminal Controller
Single Chip Peripheral Controller

Mass Storage

82C710
82C780
82C781
82C782
82C784

Multifunction Floppy Controller
Single Chip Micro Channel Hard Disk Controller
Micro Channel Interface Chip
Fixed Disk Data Manager Chip
Data Separator & MFM/RLL Endec

Integrated Software Operation

OSS8281

NEATsx New Enhanced AT-Compatible BIOS

Design Services Operation
DK82C611/82C612
MicroCHIPS Development Kit

\:r;ifi!i ___________________________________________
HIGH·END CHIPSet SOLUTIONS
Systems Logic

CS8231
CS8233
CHIPS/280
82C614

Turbo Cache-Based 386/AT-Compatible CHIPSet
PEAKset/386 CHIPSet
PS/2 Model 70/80-Compatible CHIPSet
MicroCHIPS Bus Master

Graphics

82C452
82C480
82B484

Super VGA Controller
8514/A-Compatible Controller
Video Support Chip

Communications

82C601
82C607

Single Chip Peripheral Controller
CHIPS/280 Multifunction Controller

Mass Storage

82C710
82C780
82C781
82C782
82C784

Multifunction Floppy Controller
Single Chip Micro Channel Hard Disk Controller
Micro Channel Interface Chip
Fixed Disk Data Manager Chip
Data Separator & MFM/RLL Endec

Integrated Software Operation

OC8233

PEAKset/386 AT-Compatible BIOS

LAPTOP CHIPSet SOLUTIONS
Systems Logic

CS8223/CS8283
82C100
82C230

LeAPset/LeAPsetsx Laptop Support CHIPSet
Super XT System Controller
High Peformance Model 30 Controller

Graphics

82C455

VGA Flat Panel Controller

Communications

82C605

CHIPSpak Multifunction Controller

Integrated Software Operation

OC8223

LeAPsetsx AT-Compatible BIOS

MICRO CHANNEL COMPATIBLE SOLUTIONS
(These pages are marked with a grey band)
Systems Logic

CHIPS/250
CHIPS/280
82C611182C612
82C614

PS/2 Model 50/60-Compatible CHIPSet
PS/2 ModeI70/80-Compatible CHIPSet
MicroCHIPS Micro Channel Interface
MicroCHIPS Bus Master

Communications

82C607

CHIPS/280 Multifunction Controller

Mass Storage

82C781

Micro Channel Interface Chip

Design Services Operation

DK82C611/82C612

MicroCHIPS Development Kit

CHiPS _________________________

ENTRY-LEVEL CHIPSet SOLUTIONS

<:1i1~:;

___________________________A_D_VA_N_C_E__IN_FO__RM_A_T_IO__N
82C100

IBMT. PS/2 Model 30 and Super XTT. Compatible Chip
•

100% PC/XT compatible

iii

Build IBM PS/2T• Model 30 with XT software compatibility

Key superset features: EMS control, dual
clock, and power management

l!I

Bus Interface compatible with 8086, 80C86,
V30, 8088, 80C88, V20

Complete system requires 12 ICs plus
memory

iii

10 MHz Zero wait state operation

Applicable for high performance Desktop
PCs, Laptop PCs and CMOS Industrial
Control Applications

1'/1

Includes all PC/XT functional units compatible with:
8284, 8288, 8237, 8259, 8254, 8255, DRAM
control, SRAM control, Keyboard control,
Parity Generation and Configuration registers

The 82C100 is a single chip implementation
of most of the system logic necessary to
implement a super XT compatible system with
PS/2 Model 30 functionality using either an
8086 or 8088 microprocessor. The 82C100 can
be used with either 8 or 16-bit microprocessors. The 82C100 includes features which
will enable the PC manufacturer to design a
super PS/2 Model 30/XT compatible system
with the highest performance at 10 MHz zero
wait state system with an 8086, the highest
functionality with dual clock and 2.5 MB
CPU BUS

[] Single chip implementation available irl
100-pin flat pacl(

DRAM (with integrated Extended Memory
System control logic), the lowest power
implementation by utilizing the on-chip power
management features and the highest integration with the lowest component count
SMT design.
The 82C100 can be combined with CHIPS'
82C601 Multifunction Controller and 82C451
VGA Graphics Controller to provide a high
performance, high integration PS/2 Model 30
type system.

1/0 CHANNEL

SERIAL PORT

MOUSE HOOK·UP
BI~DIRECTIONAL

PARALLEL PORT

Super XT Model 30 Compatible System

<:tti~:;

________________________________________________

The 82C100 supports most of the peripheral
functions on the PS/2 Model 30 planar board:
8284 compatible clock generator with the
option of 2 independent oscillators, 8288
compatible bus controller, 8237 compatible
DMA controller, 8259 compatible interrupt
controller, 8254 compatible timer/counter,
8255 compatible peripheral I/O port, XT Keyboard interface, Parity Generation and Checking for DRAM memory and memory controller
for DRAM and SRAM memory sUb-systems.
The 82C100 enables the user to add PS/2
Model 30 superset functionality on the planar
board: dual clock with synchronized switching
between the two clocks, built-in Lotus-IntelMicrosoW" (LIM) EMS support for up to
2.5 Megabytes of DRAM and power management features for SLEEP mode as well as
SUSPEND/RESUME operations. The SLEEP
and SUSPEND/RESUME features help in

preserving the battery life in laptop portable
applications.
The 82C100 supports a very flexible memory
architecture. For systems with DRAMs, the
DRAM controller supports 64K, 256K and 1M
DRAMs. These DRAMs can be organized in
four banks of up to a maximum of 2.5 MB on
the planar board. The 2.5 MB memory can be
implemented with 2 banks of 1M x 1 DRAMs,
partitioned locally as 640KB of real memory
and 1.875MB of EMS memory. For systems
which require low operating power and
minimum standby power dissipation, the
chips provide the decode logic which in conjunction with external decoders allows selection of up to 640KB of static RAM. This option
is useful in laptop portable applications.
The 82C100 is packaged in a 100-pin plastic
flatpack.

CHiPS ________________
82C230
High Performance Model 30 Compatible CHIPSet™
II

100% IBM Model 30 (8086) Compatible,
but uses the 80286 CPU for increased
performance.
Single chip includes:

Supports 8 or 16 bit 82C451 VGA interfaces.

Supports 82C601 Multi-Function Peripheral
Chip.

• Has flexible bus timing to solve adapter
compatibility problems.

CPU Support Logic
Memory Controller w/ EMS
Keyboard and Mouse Ports
Bus Interface/Conversion Logic
8237, 8254, 8255, 8259 Equivalents
Numeric Processor Interface
Peripheral Chip Selects
II

• Supports either 8 or 16 bit ROMs for space
and cost savings.

Supports up to 8 Megabytes of Memory with
EMS and Shadow RAM capabilities.

iii

High level of integration allows a Model 30
footprint without the need to surface mount
all components.

III

Single chip implementation in 144 Pin
Flat Pack.

.. Supports CPU speeds of 8, 10, 12.5,
16 and 20 MHz

80286

A19-0

CPU

82C230

SYSTEH
CONTROLLER

8DZ87
NPX

82C4$l
VCA

CONTROLLER

1-0

MODEL 30 SYSTEM BLOCK DIAGRAM
10/88 REV. 0

CHiPS _________________
The 82C230 is a single chip that contains most of the core logic required to support the system logic functions
required to build a 100% IBM Model 30 (8086) Compatible computer, but based on the higher performance
80286 processor. This allows the OEM to offer a compatible solution for the low end of the marketplace that
out-performs the offerings from IBM or compatibles based on the 8086 CPU.
The 82C230 contains CPU control logic including clocks, a DRAM controller that supports up to 8 megabytes
of memory with EMS and Shadow RAM capabilities, 8259, 8237, 8254 and 8255 equivalents, refresh controller,
expansion bus interface, keyboard and mouse interfaces, numeric processor interface, and peripheral chip
selects for floppy and hard disks, real-time-clock, video, serial and parallel ports.
The 82C230 can be combined with the 82C601 multi-function peripheral chip and the 82C451 VGA chip to
build a complete Model 30 compatible motherboard that offers superior performance with much higher integration.
The 82C230 can support the 82C451 on the 8-bit system bus, or on the 16 bit local bus for higher performance.
The 82C230 DRAM controller can support zero wait state designs at CPU speeds of 12.5 MHz using 80 ns
DRAM, or 16 MHz with 60 ns DRAM. Wait states can be inserted so that lower speed DRAMs may be used
with high speed processors.
The 82C230 memory controller supports up to 8 megabytes of DRAM. The CPU can access this memory
directly or through an EMS 4.0 compatible register set. BIOS ROM support is provided for both 8 and 16 bit
wide data paths. Since Shadow RAM is also supported, an OEM can choose to save board space and costs
by using a single 8 bit ROM and copying it to shadow RAM for fast execution.
For today's low-end machines, which must have performance levels greater than yesterday's high-end machines,
the 82C230 is the clear choice.

<:t1ifi~

__________________________________~P~R~E=L~IM~I~N~A~RY
82C235/SCATTM
Single Chip AT Systems Logic

80286 control logic and clocks which support CPU speeds of up to 12.5 MHz with 0
or 1 wait states

.. A memory controller which provides
shadow RAM and support for either 8-bit
or 16-bit BIOS ROM configurations

.. 32 EMS Page Registers (supporting LIM
EMS 4.0)

.. A 146818-compatible real time clock with
114 bytes of CMOS RAM

.. Two 8237-compatible DMA controllers

.. A DRAM refresh controller

.. Two 8259-compatible interrupt controllers

.. Interface logic for 80287 numeric
coprocessor

An 8254-compatible programmable interval timer

An 8255-compatible peripheral interface

III

An 82284-compatible clock generation
and READY interface

An 82288-compatible bus controller

A DRAM controller which supports up to
16MB of DRAM

82C235-SCAT
The 82C235 is a VLSI device that incorporates
most of the motherboard logic required to
build a low-cost, highly-integrated IBM®PC ApM
compatible computer. It is designed to be used
in conjunction with other Chips and Technologies controllers such as the 82C451 VGA

.. Interface logic for 8042 keyboard
controller
II

Fast Gate A20 and Fast CPU Reset logic

Power management features

III

Packaged in a single 160-pin plastic flat
pack

Controller, the 82C601 Peripheral Controller,
and the 82C765 Floppy Disk Controller. When
used with these devices, the 82C235 serves as
the heart of a highly-integrated system, significantly reducing the system's motherboard
size and component count, and the need for
many I/O Channel (AT Bus) slots.

SA23:00

L _

80287
L-_N_pu---J

ILD
15:00

CHIPS
82C235
SYSTEM
~L~A-23-:0~0~ CONTROLLER
X015:00

LOCAL
BUS

AT 1/0
CHANNEL

KEYBOARD

XBUS

Figure 1. 82C235 - Single Chip AT System Controller Block Diagram

<:ttl~:;

______________________________

A_D_V~A~N~C_E_I~N~FO~R~M~A~~~IO~N

82C451 CHIPS Integrated VGA
•

Fully IBMT• VGA Compatible at hardware,
register and BIOS level.

•

Dual Bus Architecture. Integrated interface
to PC-Bus and Mlcrochannel (CHIPS/250
and CHIPS/280).

•

Single Chip Solution.

•

Proprietary High Speed Interface to
CHIPS/250 and CHIPS/280 Systems.

•

Supports 8 and 16 bit CPU interface for
memory and I/O cycles.
Supports external palette DAC of up to 16
million colors.

•

CPU Interface

Resolutions up to 640*480 in 16 colors,
960*720 in 4 colors and 1280*960 monochrome.

•

Enhanced backward compatibility with
EGA, CGA, HerculesT. , MDA without using
NMI.

•

Processor Latches and Attribute Flip Flop
are readable.

•

Pinout Compatible with 82C452. Same
design can use both parts.

If the 16 bit interface is chosen, then depending
on the state of AO and BHE, either a 8 bit or 16
bit cycle will actually be executed. This ensures
compatibility with old software.

82C451 has a strap option to select a PC-Bus
Interface or a Microchannel Interface. All control signals for both the interfaces are integrated into the single chip.

All I/O cycles are completed without· wait
states. For memory cycles, the cycles are
extended with wait states.

82C451 supports both a 8 bit and 16 bit CPU
interface. The 16 bit interface can be independently enabled/disabled for memory and
I/O cycles. On reset, the chip is configured
for 8 bit accesses for memory and I/O cycles.
16 bit interface for I/O cycles is restricted to
index/data pair of registers. This includes the
Sequencer (3C4h), Graphics Controller (3CEh),
CRT Controller (3B4h/3D4h) and the Attribute
Controller (3COh). All other I/O addresses
(color palette, Misc Output and Status) are
always treated as 8 bit ports.

ADDRESS!
DATA MULTIPLEXER

•

BIOS ROM Interface
In the PC-BUS Interface, the 82C451 supports
an external BIOS ROM. The ROM address is
decoded and the ROMCS pin is asserted to
enable ROM data on the CPU bus. In the
Microchannel Interface, the system BIOS includes the video BIOS.

82C451

EXTERNAL CPU
INTERFACE

ATIRIBUTE
CONTROLLER

MEMORY GRAPHICS CRT CONCONTROLLER CONTROL- TROLLER
(SEQUENCER)
LER

I
T'

PALETIE

~ ANALOG
VIDEO

DAC
DIGITAL
VIDEO

I
DRAM

82C451 System Diagram

1/88 REV 0

CH.PS _______________
Display Modes and Resolution
82C451 supports a superset of all VGA display
modes. It supports resolutions upto 640*480
in 16 colors, 960*720 in 4 colors and 1280*960
in monochrome.

Memory Interface
The entire display memory (256 Kbytes) is
always available to the CPU in regular 4 plane
mode, chained 2 plane mode and in super
chained 1 plane mode.
The display memory control signals are derived from the dot clock. The MCLK is used
for internal sequencing of 16 bit memory cycles. MCLK should be 25-40 MHz.

Extended Registers
All functionality of the extended registers in
82C451 are disabled on reset. Before the extended registers can be written into, they
must be enabled by two sets of control bits
(disabled on reset). The Processor Latches in

the Graphics Controller and the Attribute
Flipflop are readable in the extended register
space. No new bits are defined or any of the
unused bits used in the regular VGA registers.

External Palette Interface
82C451 supports programming of an external
palette DAC by decoding the CPU addresses
and generating the RD and WR signals to the
external palette. 82C451 decodes 1/0 addresses
3C6-3C9h as valid external palette addresses.

High Speed CPU Interface
82C451 supports a high speed interface to
CHIPS/250 and CHIPS/280 systems. There
are special interface pins on the CHIPS/250,
CHIPS/280 and 82C451. Using these special
interface pins, CPU accesses to the 82C451
can be executed faster than CPU accesses to
other peripheral devices.
The 82C451 is packaged in a 144 pin plastic
flat pack (PFP).

\:t1i~!)

_____________________________________P~R~E~L~I~M~IN~A~R~Y
82C578 CHIPSterm'M
SINGLE CHIP 3270 TERMINAL CONTROLLER

•

Complete 3270 Terminal Controller on a
single chip

•

High speed microengine (10 MIPS) with
64K Bytes of Memory, 32K of 1/0, and
128K of Font

•

User-definable screen formats:
-

Color remapping and background color
Variety of Rules: cross-hair, vertical and
horizontal
Overscan

•

Unique 3-way arbiter to evenly balanced
memory cycles

•

Flexible display list processor for soft
screen formats, multiple windows, multiple interlaced and non-interlaced displays

User definable Character size: 5-16 wide
by 1-32 pixels high

•

Download feature for more economical
solution

•

Supports both color and monochrome
monitor up to 60MHz dot clock

•

Programmable wait-states for slow
peripherals

•

16mA Centronics'· parallel interface

•

Supports individual scan line display and
random scan line

Supports both AT- and PS/2-Compatible
style keyboards

•

EEPROM support

•

Light-pen interface

•

Supports all 3270 modes and receives
3299 packets

CMOS technology in 144-pin PFP package

BUZZER(4)
FAO-15
FONT

FDO-15

--CODE
--

-il

ATTRIBUTE DECODER

(OPT)

MCS1,MCS2,RD,WR
SRAM
8Kx8

EEPROM

DISPLAY LIST
PROCESSOR

I
I

AO-15
DO-15
EECS

- -f
BUS
IIF

I
3WAY
ARBITER

'-------

18.8696MHz

c::::J
~

KEYBOAR D IIF
LlGHTPEN

LS125

KBCLK,KBDATA
LPSTRB, LPSW
PDO-7,SLCTIN,AFX

PRINTER IIF
TIMER
DISPLAY IIF

COAX ENGINE

COAX IIF REG

SEQUENCER

COAX Tx/Rx

INIT,STRB,ACK,PE
BUSY,SLCT,ERROR
RGB,INT,VSYNC
HSYNC, DCLK1-3

TxDLY,TxD
TxACT,RxD

POR-

Figure 1_ 82C578 Application Block Diagram

LS37

TRANS-\
FORMER

CHiPS _______________
3270-compatible terminal consists of 2 buffer
SRAM, 1 fonts EPROM, 1 configuration
EEPROM, a transformer, an LS374 to drive the
RGBI signals, and an LS125 for the buzzer.

The 82C578 is a highly-integrated single chip
processor to be used to design 3270 Display
Stations such as 3191 and 3192-compatible
display terminals. It has all necessary logic to
handle 3270 coax protocol, coax transmitter/receiver, video sync generation, 3270 attribute, light-pen, keyboard, Centronics compatible parallel interface, security keylock,
buzzer control, and many more. A complete

Ordering Information
Order Number

Package 'lYpe

P82C578

144-pin Plastic Flat Pack

Absolute Maximum Ratings
Parameter

Symbol

Supply Voltage

Vee

Input Voltage

Min

-0.5

Mal(

Units

7.0

5.5

Output Voltage

-0.5

5.5

Operating Temperature

Top

-25

·C

Storage Temperature

TSTG

-40

125

·C

Note 1: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions described under Operating Conditions.

Normal Operating Conditions
Parameter

Symbol

Min

iVlal(

Units

Supply Voltage

Vee

4.75

5.25

Ambient Temperature

Power Supply Current

lee

Input Low Voltage

VIL

-0.5

O.S

Input High Voltage (except Xi, DX1)

VIH

2.0

Vee + 0.5

Input High Voltage (Xi, DX1)

VIH

3.5

Vee + 0.5

Output Low Voltage (note 2)

VOL

Output High Voltage (note 2)

VOH

0.4

Input Leakage Current

ilL

-10

Output Tri-State Leakage

IOL

-10

J.lA
pF

2.4

V
V
J.lA

Input Capacitance (Fe = 1MHz)

CIN

Output Capacitance

COUT

I/O Capacitance

CliO

Note 2: IOL = 16mA, IOH = -2mA for pins PPDo-7, SDATAo-1L- __

IOL = SmA, 10H = -2mA for pins SADo-14, MCS1-2, SWR, SRD, EXTINTR, RQT, EXTIO
IOL = 4mA, IOH = -2mA for all other pins.

<:til~!i

____________________________________P_R_E_L_IM_I_N_A_RY_

82C605/82C606
CHIPSpak/CHIPSport MULTIFUNCTION CONTROLLERS
•

100% Compatible to IBM" PC, XT and
AT

Ii!

Fully compatible to the NS16450 Asynchronous Communications Element, and the
Motorola'· 146818A Real Time Clock
(82C606 only)

•

Provides a parallel interface which can
be configured for use with either a printer
or a scanner
Provides two UART channels which can
be powered from external sources

The 82C606 CHIPSpak Multifunction Controller incorporates two UARTs, one parallel port,
one game port decoder and one Real Time
Clock. The UARTs are fully compatible to the
NS16450 and the Real Time Clock is fully
compatible with the Motorola 146818A. The
82C606 thus offers a single chip implementation of the most commonly used IBM PC, XT
or AT peripherals. While offering complete
compatibility with the IBM architecture, the
chip offers enhanced features. These include
support for power derived from three sources
(main, auxiliary and standby), an additional
64 bytes of user RAM for the Real Time Clock
and a software configuration scheme which

•

Support for a game port

•

Provides a Real Time Clock with 100
year calendar (82C606 only)

•

CMOS Configuration RAM with Battery
Backup support permits software selection of internal register base addresses
(82C606 only)

•

114 bytes of CMOS RAM

•

Single chip 68-pin CMOS implementation

permits development of a system configuration program.
The CHIPSpak Multifunction Controller can
be used on the system board to provide serial
and parallel ports or on a multifunction card
to create a low cost, high density peripheral
for use with general purpose microcomputer
systems.
The 82C605 CHIPSport is a functional sub-set
of 82C606 CHIPSpak. The two products are
identical, with the exception of the Real Time
Clock. The 82C605 does not integrate the
Real Time Clock.

1./'---"",-

PARALLEL PORT

Figure 1. 82C60S/606 CHIPSpak/CHIPSport Multifunction Controller Block Diagram

<:t1i~!i

______________________________________PR~E~L~I~M~IN~A~R~Y

82C710 PC AT·COMPATIBLE MULTIFUNCTION FLOPPY CONTROLLER
•

Low Power Advanced 1.51' CMOS Technology, 100 QFP Package

l1li

Integrated Floppy Subsystem
-

jlPD72065B-Compatible Floppy
Controller

•

16450-Compatible Serial Port

•

Enhanced Bi-Directional Parallel Port
with 16 rnA Output Drive

Analog PLL with Transfer Rates Up To
1 Mbits

•

General Purpose Programmable Chip
Select

48 rnA Floppy Drive Interface Buffers

III

PS/2 T"-Compatible Type Mouse Port Logic
With Driver Support

Programmable Precompensation
Modes

iii

IDE Interface For Embedded PC ATT" and
PC XT'" Hard Disk Drives

100% IBM® PC XT/AT-Compatible Register
Set

(;] 16 rnA PC XT/AT-Compatible Host Interface
Drive Capability
I1lI

Complete On-Board Power Management
Features

PS/2 MOUSE PORT

MDATA, MCLK

SERIAL PORT

TxD,RTS,DTR
RxD, CTS, RI
DSR, DCD

PARALLEL PORT

ACK, PC, ERROR
BUSY,SLCT
PDO·7
STROBE,INIT
SLCTIN, AUTOFD

IDE INTERFACE

IDEENL,IDEENH
HDCSO, HDCS1
IDE7,IOCS16

MINTR, FINTR
SINTR, PINTR
Ao-Ag, AEN
lOR, lOW, RST
Do-D7, DAK
, DRO, TC
DBDIR, PWRGD

HOST INTERFACE

FDC

GPCS,RTCCS

DECODER

ANALOG PLL

Figure 1. 82C710 Block Diagram

RDATA,WDATA,WGATE
DRVO,DRV1,MTRO,MTR1
DIR, STEP, TRKO, HDSEL
WRPT, INDEX, DSKCHG
FILTER, FGND 250/500
PUMP/PREN, DRVTYP
SETCUR, RPM/LC, RVI

\:t1i~!i

__________________________________________________

The 82C710 is a single chip offering the complete I/O solution for the PC XT- & PC ATcompatible motherboard environments today.
The 82C710 provides the functionality of a
16450-compatible UART, which when coupled
with a 145406 and a 1488 results in the
implementation of a complete PC XT/ATcompatible serial port. The parallel port is just
like the one on the PC XT/AT-compatible and
supports the PS/2-compatible bi-directional
mode of operation. In addition it supports a
drive capability of 16 rnA, which alleviates the
need for external buffers. A PS/2-Compatible
mouse port is provided, along with the drivers

necessary to support it in a PC XT/AT-compatible environment. The IDE interface logic
needed on the host end to support embedded
XT/AT-compatible hard disk drives is provided
by the 82C710, thereby contributing to lower
chip count on the motherboard. A complete
floppy subsystem consisting of apPD720658
floppy core, an analog data separator, capable
of transfer rates up to 1 Mbits/s and the host
interface registers, is on-board in the 82C710.
The 82C710 provides complete power management, and software configurability, thus
providing the most optimum solution of its
kind in the market today.

<:r;I~!i

________________________________~P~R~E~LI~M~IN~A~RY

82C785 SINGLE CHIP PC-AT HARD DISK CONTROLLER
Low Power Advanced 1.5j.1 CMOS Technology, 100 QFP/84PLCC

Control for Implementation of a 64K Dual
Port Static RAM Buffer

100% IBM PC/AT Compatible Task File
Support

•

Optional Auto-Increment of Address
Pointer for Local CPU to Buffer Access

24 mA Drivers for Direct Interface to the
PC/AT Bus

Higher Buffer Memory Throughput, Up
To 10 MBytes/s

•

Auto-Generated Wait States For Interfacing to Fast Hosts

Supports Disk Data Rates Up To 24
Mbits/s

Ell

PIO and DMA Modes for Buffer Data
Transfers Up To 8 MBytes/s

III

Programmable Disk Sequencer RAM of
30x 4 Bytes

Auto-Command Mode to Speed Up Disk
Command Response

III

Optional Dual Brand Registers

III

Support for Daisy Chaining of Two Embedded Drives

m Support for 16-Bit CRC and 32/56-Bit
Programmable ECC
iii

I
IOCHRDY
DREO,INTRQ
~

CHRESET
IORD,rnwR
AO-2, A9, CSii
XDO-IS

RAO-IS
RDATo-7
BMOE,BWE
BUFCLK

TASK
FILE

I·

Provides Complete On-Board Power
Management Features

<=>
..
LOCALCPU
INTERFACE

ADo-7
ALE
CS,WR,RD
INT
RST

-.
<::::>

g
-

AT
INTERFACE

FORMATTER
&
DISK
INTERFACE

..
..
.

Functional Block Diagram

AM/SECTOR
INDEX

INOUT
RG,WG

BUFER
MEMORY
INTERFACE

RRFCLK
II

NRZ

CHiPS ___________________________

""~
1

RDATA5

RAO

SLVOO

3
4
5

SLV01

78
77
76
75
74
73

XDO
XD1

NC
RDATA4

RDATA3

XD2

RDATA2

XD3

8
9
10

RDATA1

VSS
VSS

RDATAO
BMOE

11
12

BWE

INT
82C785
100-QFP

XD4

XD5

XD6

XD7
XD8

68
67

VSS

XD9

VSS

XD10

17
18

XD11
VSS

64
63

TOP

AD7

19
20

AD6

VSS

ADS

XD12

AD4

XD13

61
60

AD3

XD14

AD2

XD15

24
25

AD1

CHRESET

58
57

ADO

IOWR

26
27

ALE

VCC

INOUT

INDEX

NC
NC

en~I

m""

o-1-1
~I

~ ~

m_
~!ii0

OZOO«-i

~ ~ ~ ~

r "" r
"N:;IIi;mCl)CI)

>1 .g c
C m
> > > ~ 01$
C -c ""
0 ~I ~I

O...l.N

~
~

'"
Physical Pin Out of the 100-Pin QFP Package

CHIPS ___________________________
The 82C785 is an enhanced, high-performance VLSI circuit that provides an optimum
implementation of a Winchester disk controllerforthe PC-AT compatible interface. It incorporates the function of a disk formatter, buffer
memory controller and AT bus interface controller. It is capable of accomplishing 1:1 interleave format with concurrent transfers of up to
24 Mbits/s on the disk and 8 MBytes/s on the
host. The built-in AT interface logic, with 24

mA drive capability, allows the chip to support
the 40-pin Conners interface, popular with the
embedded disk drive designs. In addition the
82C785 provides support for complete power
management, thereby lending itself to drive
implementations oriented towards the laptop
market. Also because of its high integration
levels, it provides an opportunity for the OEM
to develop low-cost solutions for the add-on
board market.

\:t1i~!i

______________________________________~P~R~E~L~IM~I~N~A~R~Y
OC82C235
SCATT" AT·Compatible BIOS

1:1

Fully compatible with the IBM ArM BIOS

1:1

Built-in support for CHIPS Multifunction
Controller

•

Optimized for performance with the
82C235 SCAT CHIPSet""

•

Developed using Clean-Room Methodology

•

Easy customization of key BIOS
parameters

•

Built-In Development/Debug Support

•

Total Hardware/Software Support

Embedded SETUP program for machine
configuration

Moving BIOS to Shadow RAM to improve
performance

Dynamic memory sizing

Setup of 82C235 EMS registers

•

Includes Keyboard Controller BIOS

•

Supports 80286 processor at speeds up
to 16 MHz

•

SETUP embedded in BIOS

Overview
The OC82C235 Single Chip AT (SCAT) Basic
Input/Output System (BIOS) is an enhanced,
high performance product that is used with
the 82C235 SCAT CHIPSet to provide an integrated hardware and software solution. The
BIOS is fully compatible with the IBM® AT
BIOS. It provides all of the standard features,
including support for:
-

80286 processor and 80287 math
coprocessor operating at clock speeds
from 8 MHz to 16 MHz

84, 101, or 102 key keyboards

High and low capacity 5.25-inch or3.5-inch
diskette drives

Monochrome and CGA video adapters

Power-on self test diagnostics

BIOS Extensions
The BIOS utilizes the extended capabilities of
the 82C235 CHIPSet to provide the user with
enhanced functionality and better performance. The BIOS is also designed to be customized by the OEM and to be easily used in
the development/debug process. The additional functions include support for:
-

82C601 Multifunction Controller with two
serial ports, one parallel port, 16-Bit IDE
hard disk interface, and floppy controller
chip select.

Complete BIOS Solution
The OC82C235 BIOS is available in two forms
to best meet the needs of the OEM. The
SK82C235 BIOS Software Kit provides a
production-ready master copy of the system
BIOS, a keyboard controller BIOS, and utility
programs to customize the BIOS and support the development/debug process. The
SC82C235 BIOS Source Kit provides the
source code and documentation for the system and Keyboard Controller BIOS, as well as
all support utilities.
All CHIPS BIOS products are designed to be
customized to meet OEM requirements. A
BIOS modification utility program is provided
in both the software and source kit. It allows
many common modifications of BIOS and
CHIPSet configuration parameters, including
the fixed disk table, the default CMOS values,
and the sign-on message. This provides a
method for an OEM to customize the BIOS
without requiring access to the source code.
The consistent, modular structure of CHIPS'
BIOS products allows creation of additional
modules to support custom applications.
Once a module is developed, it can be in-

\:r;i~!i

___________________________________________

tegrated into the BIOS with minimal effort.
CHIPS also provides in-house customization
services.
CHIPS system BIOS products are designed
with built-in support to aid in the development/debug process. The BIOS is designed
to allow the CHIPSet registers to be loaded
from saved information during power-up. The
registers and their values that will be loaded
can be controlled by a program that is included in the software kit.

Clean Room Methodology
The BIOS was developed using a clean-room
methodology that helps ensure CHIPS BIOS
products do not infringe on any applicable
copyrights. The methodology used is well
documented and is available for review upon
request.

Total Hardware/Software Support
CHIPS offers complete hardware and
software support for customers using the
82C235 Single Chip AT with the BIOS. The
CHIPSet together with the BIOS have been
extensively tested for quality, reliability and
compatibility. CHIPS has an in-house com-

patibility test department that tests all CHIPS
BIOS products using industry standard
software and hardware. CH I PS has a tech nical
support staff available to assist in resolving
any hardware or software problems that may
arise.

Ordering Information
OC82C235 SCAT BIOS (Label)
CB82C235

82C235 SCAT CHIPSet with
OC82C235 BIOS (Label)

SK82C235

SCAT BIOS Software Kit

SC82C235

SCAT BIOS Source Kit

CHIPS BIOS products are licensed on a per
copy royalty basis. A CHIPS BIOS Object
Code or Source Code license must be signed
and returned before ordering a CHIPS BIOS
product. A software kit or source kit can then
be ordered to obtain a master copy of the
BIOS. For each BIOS ordered, the OEM
receives an EPROM label and is entitled to
make one copy of the BIOS from the master.
To obtain further information please contact
your local Chips & Technologies, Inc. sales
representative.

CHiPS ____________

----:..P.;.:,:RE=L.:.:.;,;IM;,;.;.;IN;.;.,;;AR;.;.;.,Y

DR82C235
SCATT. EMS Driver Kit
•

Optimizedforthe82C235SCATCHIPSet T•

•

Supports LIM 4.0 EMS Specification

•

Total Hardware/Software Support

Overview
The DR82C235 Single Chip AT (SCAT) EMS
Driver Kit provides driver software to support
EMS based on the 82C235 SCAT CHIPSet.
The DR82C235 software is designed to utilize
the capability of the Single Chip AT to operate
according to the LIM (Lotus®, Intel®, &
Microsoft®) 4.0 EMS Specification.

Total Hardware/Software Support
CHIPS offers complete hardware and software support for customers using the 82C235
Single Chip AT-compatible CHIPSet with the
DR82C235 drivers and utilities. The Single
Chip AT-compatible CHIPSet, together with
the drivers and utilities, have been extensively
tested for quality, reliability and compatibility.
CHIPS has an in-house compatibility test
department that tests CHIPS products with
industry standard hardware and software.
CHIPS has a technical support staff available
to assist in resolving any hardware or software problems that may arise.

Ordering Information
The Driver's main job is to initialize the 82C235
EMS registers to function according to the
specified setup. Once the driver is installed, it
acts as an interface between the system and
the EMS hardware. It provides service function calls that allow an application to access
the EMS memory.
The EMS Driver is capable of handling up to 16
megabytes of memory. The EMS memory size
must be setup either by the BIOS or a CHIPSet
configuration program. The driver has options
to select the base EMS I/O address, the page
frame address, the maximum number of open
processes, and enable an extensive memory
diagnostic test during initialization.
Included on the diskette with the driver is
documentation describing installation and
usage of the EMS driver.

DR82C235

SCAT EMS Driver/Utility Kit

DS82C235

SCAT EMS Driver/Utility
Source Kit

CHIPS software products are obtained by an
OEM through license agreement. An OEM
Software License Agreement must be signed
and returned before ordering a CHIPS
Driver/Utility product. This agreement entitles
the OEM to reproduce and distribute one copy
of the driver/utility software with each product
containing the appropriate CHIPSet.
To obtain further information please contact
Chips and Technologies, Inc. or your local
sales representative.

CHiPS _________________________

MID-RANGE CHIPSet SOLUTIONS

C:r;i~:;

________________________________

~P~RE~L~IM~I~N~A~RY

CS8221 NEW ENHANCED AT (NEATTM) DATA BOOK
82C211 J'82C212J'82C215J'82C206 (lPC) CHIPSet™
•

100% IBM'· PC/AT Compatible New Enhanced CHIPSet'· for 12MHz to 16MHz
systems

•

Supports 16MHz 80286 operation with only
0.5-0.7 wait states for 100ns DRAMs and 12
MHz operation with 150ns DRAMs, 0 wait
state 12MHz operation with 80ns DRAMs

•

Separate CPU and AT Bus clocks

•

Page Interleaved Memory supports single
bank page mode, 2 way and 4 way page
interleaved mode

•

Integrated Lotus-Intel-Microsoft Expanded
Memory Specification (LIM EMS) Memory
Controller. Supports EMS 4.0.

The CS8221 PC/AT compatible NEAT
CHIPSet'M is an enhanced, high performance
4 chip VLSI implementation (including the
82C206 IPC) of the control logic used on the
IBM" Personal Computer AT. The flexible

•

Software Configurable Command Delays,
Wait states and Memory Organization

•

Optimized for OS/2 operation

•

Shadow RAM for BIOS and video ROM to
improve system performance

•

Complete AT/286 system board requires
only 28 logic components plus memory
and processor

•

Targeted at Desktop PC/ATs, Laptops and
CMOS Industrial Control Applications

•

Available as four CMOS 84-pin PLCC or
100-pin PFP components.

architecture of the NEAT CHIPSet'M allows it
to be used in any 80286 based system.
The CS 8221 NEAT CHIPSet'" provides a
complete 286 PC/AT compatible system,

_ _ _ _ _ _ _ _ _ _r -_ _ _ _ _ _ _ _ LA11-23

- - - - - - - - - - f - - - - - - r - - - - S D.." }5-BUS
- - - - - r - - - - - - f - - . - - - - + - - - - SA 1•
0-

..... }CPU·BUS

M-1+-..I-+--+---+--f----D15
0-

MAO-9

---i-I:.-----i-.-----...L..---

Figure 1. NEAT System Block Diagram

MDO-15

}

M-BUS

CHIPS _______________
requIring only 24 logic components plus
memory devices.
The CS8221 NEAT CHIPSet'" consists of the
82C211 CPU/Bus controller, the 82C212
Page/Interleave and EMS Memory controller,
the 82C215 Data/Address buffer and the
82C206 Integrated Peripherals Controller (IPC).
The NEAT CHIPSet'" supports the local CPU
bus, a 16 bit system memory bus, and the AT
buses as shown in the NEAT System Block
Diagram. The 82C211 provides synchronization and control signals for all buses. The
82C211 also provides an independent AT bus
clock and allows for dynamic selection between the processor clock and the user selectable AT bus clock. Command delays and wait
states are software configurable, providing
flexibility for slow or fast peripheral boards.
The 82C212 Page/Interleave and EMS Memory
controller provides an interleaved memory
sUb-system design with page mode operation.
It supports up to 8 MB of on-board DRAM
with combinations of 64Kbit, 256Kbit and 1Mbit
DRAMs. The processor can operate at 16MHz
with 0.5-0.7 wait state memory accesses, using
100 nsec DRAMs. This is possible through
the Page Interleaved memory scheme. The
Shadow RAM feature allows faster execution
of code stored in EPROM, by down loading
code from EPROM to RAM. The RAM then
shadows the EPROM for further code execution. In a DOS environment, memory above
1Mb can be treated as LIM EMS memory.
The 82C215 Data/Address buffer provides the
buffering and latching between the local CPU
address bus and the Peripheral address bus.
It also provides buffering between the local

CPU data bus and the memory data bus. The
parity bit generation and error detection logic
resides in the 82C215.
The 82C206 Integrated Peripherals Controller
is an integral part of the NEAT CHIPSet'". It
is described in the 82C206 Integrated Peripherals Controller data book.

System Overview
The CS8221 NEAT CHIPSet'" is designed for
use in 12 to 16 MHz 80286 based systems
and provides complete support for the IBM
PC/AT bus. There are four buses supported
by the CS8221 NEAT CHIPSet'" as shown in
Figure 1: CPU local bus (A and D), system
memory bus (MA and MD), I/O channel bus
(SA and SO), and X bus (XA and XO). The
system memory bus is used to interface the
CPU to the DRAMs and EPROMs controlled
by the 82C212. The I/O channel bus refers to
the bus supporting the AT bus adapters which
could be either 8 bit or 16 bit devices. The X
bus refers to the peripheral bus to which the
82C206 IPC and other peripherals are attached
in an IBM PC/AT.

Notation and Glossary
The following notations are used to refer to
the configuration and diagnostics registers
internal to the 82C211 and 82C212:
REGnH denotes the internal register of index
n in hexadecimal notation.

REGnH denotes the bit field from bits x
to Y of the internal register with index n in
hexadecimal notation.

<:l1lfi!i _______________________________________P_R_E_L_IM__IN_A_R__
y

CS8281
New Enhanced AT CHIPSet for the 386SX
NEATsx
• 100% IBM'· PC/AT Compatible New
Enhanced CHIPSet'· for the 386SX
microprocessor.
• Supports 387SX coprocessor.
• Supports 16 MHz, 20 MHz and beyond with
only 0.5 - 0.7 wait states.
• Single bank, 2-way and 4-way interleaved
paging with 100 ns DRAMs for 16 MHz.

• Optimized for OS/2 operations.
• Shadow RAM for AT BIOS and graphics
BIOS for improved performance.
• Complete AT/386SX system board
requires 24 logic components.
• Four CMOS components available in 84pin PLCC or 100-pin QFP packages.

• Supports the full EMS 4.0 with on-chip or
off-chip EMS page registers.
The NEATsx'·, CS8281 CHIPSet'" is an enhanced, high performance 4 chip VLSI implementation of the control logic to build PC/AT
compatibles based on the 386SX microprocessor.
Based on the proven NEAT CHIPSet'· architecture, NEATsx provides a complete 386SX AT
system board with 24 components plus memory
devices.
The CS8281 CHIPSet is optimized for OS/2 and
will run OS/2 applications as fast as equivalent
PS/2 systems. The CHIPSet also supports fast
task switching under DOS environment. Besides the on-chip 4 EMS page registers, NEATsx
supports up to 512 page registers in hardware.
There is a hook to external EMS Mapper Chips
which can be nested together. Each one of
these mapper chips carry 128 page registers.
The CS8281 NEATsx CHIPSet'· consists of the
82C811 CPU/Bus controller, the 82C812 the
Page interleave/EMS memory controller, the
82C215 Data/Address buffer and the 82C206
Integrated Peripheral Controller.
Since NEATsx supports asynchronous CPU and
AT bus architecture as well as synchronous, the
AT bus can be run independent of the CPU bus.
82C811 also provides dynamic clock selection
between the processor clock and the user
selectable AT bus clock. Command delays and
wait states are software configurable, providing
flexibility for slow and fast peripheral boards.
The advanced memory controller, 82C812 provides an interleaved memory subsystem design
with page mode operation. Two banks, four
banks can be interleave-paged. Single bank
paging using slow memories is also available
for cost sensitive memory designs.

The 82C215 Data/Address buffer provides the
latching and buffering between the local CPU
address bus and the Peripheral address bus. It
also provides buffering between the local CPU
data bus and the memory data bus. The parity
bit generation and error detection logic resides
in the 82C215.
82C206 is an integral part of the NEATsx
CHIPSet. It is explained in detail in the 82C206
data book.
NEATsx CHIPSet will support the 386SX at
higher speeds as the processor becomes available at those speeds.
Now, a cost competitive 386SX based AT compatible can be designed with the most advanced
NEATsx CHIPSet.
NEATsx BASED SYSTEM BLOCK DIAGRAM

<:t1i~!i

______________________________A_D_V_A_N_C_E_I_N_FO__R_M_A_~_IO__N

82C221,82C222,82C223,82C225,82C226,82C60~82C451

CIHIPS/250: Complete IBM® PS/2™ MODEL 50/60 Compatible CHIPSet™
III

•

100% IBM PS/2 Model 50/60 Compatible
Chipset
Supports 10, 12, 16 and 20 MHz 80286
based Systems
Complete IBM PS/2 Model 50 Compatible
Mother Board requires 68 components plus
memory
Available as CMOS PLCC and PFP Components

SYSTEM LOGIC CS8225 CHIPSET
iii Asynchronous CPU, DMA and Micro
Channel™ Operation
I!lI

II!

Advanced Page/Interleave Memory Controller with Integrated Bad Block Remapping Capability, Shadow RAM and LIM
EMS 4.0 Support
Slow DRAMs at high CPU clock speeds,
without Wait State penalty - 0.5 to 0.7 wait
states with:
150ns DRAMs @ 12.5 MHz
120ns DRAMs @ 16 MHz
80ns DRAMs @ 20 MHz

CHIPS/250 is a 7-chip, Enhanced CMOS implementation of most of the system logic
necessary to implement IBM PS/2 Model 50/60
compatible personal computers. CHIPS/250
will enable OEMs to offer PCs that are more
functional, more integrated and clearly higher
in performance than IBM's Model 50 and
Model 60.
CHIPS/250 includes the CS8225 System Logic
CHIPSet, the 82C607 Multi-Function Controller with an Analog FDC Data Separator and
16550 compatible serial port, and the Enhanced
Gate-Level Compatible 82C451 VGA chip.
With these 7 VLSI devices, it requires only 61
additional components plus memory to implement superior PCs to IBM's models.

System Logic CS8225 CHIPSet
The CS8225 System Logic CHIPSet consists
of the 82C221 CPU and Micro Channel Controller, the 82C222 Page/Interleave and EMS
Memory Controller, the 82C223 DMA Controller, the 82C225 Data/Address Bus Buffer

III

Integrated Lotus-Intel-Microsoft Expanded
Memory Specification (LIM OMS 4.0)
Memory Controller expandable to full LIM
EMS 4.0 specification with 8 register sets
of 64 mapping registers

•

High performance, proprietary Matched
Memory interface for Micro Channel
Memory Adapters

GRAPHICS
III

Enhanced Gate-level Compatible VGA

High performance, proprietary FAST VGA
interface to CPU controller

PERIPHERAL SUPPORT
iii

Integrated Analog Data Separator and
16550 compatible serial port

and the 82C226 System Peripherals Controller.
Each of these 5 components is available in
84-pin PLCC and 100-pin PFP.
The 82C221 CPU and Micro Channel Controller manages the system timing for the asynchronous CPU, DMA and Micro Channel
cycles. It supports CPU clock speeds from 10,
12, 16 to 20 MHz. It supports all Micro Channel
cycles, along with Matched Memory and Fast
VGA cycles. It includes state machines for
command and control logic signal generation,
DMA and refresh logic control.
The 82C222 Page/Interleave and EMS Memory
Controller provides an interleaved memory
subsystem design with page mode operation.
It supports 4 memory banks, with memory
configurations from 640KB to 8MB. While
operating under DOS, memory above 1MB
can be treated as EMS memory, improving
significantly the value of the large memory
organizations of the OS/2 era. The on-chip
EMS logic provides 4 mapping registers,
however, with external EMS mappers, the full

;

....

CHIPS ______________________
LIM EMS 4.0 specification with 8 sets of 64
mapping registers can be implemented.
The 82C223 DMA Controller provides 8 DMA
channels for slave devices and the Central
Arbitration Control Point (CACP) for the entire
system. Each DMA Channel has 24-bit address
capability and can perform 8-bit or 16-bit
transfers. It also supports Virtual DMA so that
DMA Channels 0 and 4 can be used to service
multiple DMA slaves by multiplexing the DMA
Channels between the arbitration levels assigned to those slaves. It supports Multiple
Bus Masters via the CACP arbitrator and control signals which enable Bus Masters to
monitor the readiness and data size of other
adapters and system board components. The
Bus Arbitration logic includes protection
mechanisms against error conditions, like
burst-mode devices not relinquishing the bus
within the specified time.
The 82C225 Data Bus Buffer provides high
speed bus switching support to enable the
use of low speed DRAMs at high clock speeds.
The 82C226 System Peripherals Controller
integrates PS/2 compatible peripherals in one
compact package, with an optimized bus interface to the Peripheral Bus. It includes two
8259 compatible interrupt controllers, one
8254 compatible timer, one 146818 compatible
real-time clock, 114 bytes of CMOS battery
back-up RAM and one PS/2 compatible Bidirectional Parallel Port.

Graphics
The 82C451 Gate Level compatible VGA provides 100% VGA compatible graphics with
backwards compatibility to EGA, CGA, MDA
and Hercules. In VGA Graphics modes, it
provides resolutions from 320 x 200 with 256
colors to 640 x 480 with 16 colors. In VGA
text mode, it supports fonts up to 9 x 32. It
supports all standard monitors-IBM PS/2
analog, Multi-frequency, EGA, CGA and
Monochrome. The 82C451 boosts graphics
performance with a tightly coupled high performance interface to the CPU and a 16-bit
memory interface. The 82C451 is packaged in
a 144 pin PFP package.

Peripheral Support
The 82C607 Multi-Function Controller integrates additional PS/2 compatible peripherals
in one compact package. It includes one 16550
Compatible UART, an Analog Data Separator,
POS registers and Glue Logic for a NEC 765A
Floppy Disk Controller. The 82C607 is available in a 68 pin PLCC package.
Additional components that complement
CHIPS/250 are the MicroCHIPS for Micro
Channel Adapters and EMS Mapper Chips.
The 82C610 and 82C611 MicroCHIPs can be
used for I/O intensive Micro Channel Adapters,
while the 82C612 is applicable to Adapters
that require Slave DMA support.

\:rll~:;

________________________________P_RE_L_IM_I_NA_R_Y
82C611, 82C612

MicroCHIPST": Micro Channel T" Interface Parts
II

Implements 100% IBM® PS/2T• Compatible
Micro Channel Adapters

82C611 Supports Multi-function, I/O and
Memory Adapters.

82C612 Supports Controller-type Adapters
Including All DMA Slave Arbitration Functions.

Programmable Option Select (POS) Support Including:
Adapter I D Support
Flexible I/O and Memory Relocation
Support
POS Port Decode Logic and Handshaking

.. Full Micro Channel Interface Including:
Command and Status Decoding
Response Signal Generation
Full DMA Slave Arbitration and Handshake (82C612 only)
II

Meets all IBM specified Timing and Drive
Specifications.

.. Simplifies migration of XT/AT adapter designs to the Micro Channel.
II

Available as 68-pin PLCC or 80-pin PFP
components.

Description
The MicroCHIPS (Micro Channel Interface
Parts) family of components integrates most
of the interface logic required on an adapter
card for the Micro Channel-IBM's new high
speed bus for its latest generation of PCs.
MicroCHIPS provide many benefits to de-

signers of add-in adapters for the Micro
Channel: Space savings because of the singlechip VLSI approach, cost savings because of
the integration of many components into one,
and time savings because of the ease of
design.

r------------------i
MICRO CHANNEL

ADAPTER

CYCLE

EXTENSION
TRANSCEIVER

\+-_ _ _ _-+_CONTROL

RESPONSE
SIGNALS

EXTERNAL

L - - - - t -.... AcPe~~~s:
MICRO CHANNEL
BUS
CONTROL
SIGNALS

LOCAL

1-~----t_COMMAND
SIGNAL

gLME~~
:
M~~I-

L.......D~~~~D

~
I
o

PLEX

SIGNALS

I
I
POS
1 - - - - - - - ; - REGISTER

'--_--.,._ _..J

BITS

LOCAL

/!-o>------l+.... ARBITRATION

I
IL __________________ JI
Simplified Block Diagram of the 82C611/612

SIGNAlS

CHiPS ______________________________
There are currently two members of the
MicroCHIPS family: The 82C611 is optimized
for memory and 1/0 interfaces such as those
on multi-function cards. It does not support
the DMA arbitration and handshaking signals.
The 82C612 adds full support for DMA arbitration and handshaking including single
cycle and burst modes. It also supports both
"preempt" and "fairness" modes as defined
by IBM. Both chips are available in either a
68-pin PLCC (plastic lead less chip carrier) or
80-pin PFP (plastic flat pack) packages.

In addition to the standard functions supplied
by the 82C611 and 82C612, CHIPS has the
capability to customize these standard devices
for dedicated high-volume applications. The
macrocells for these parts can be integrated
into custom controller designs.

Note: IBM uses a leading minus sign (-) to indicate an active low signal. The convention used in this data
sheet is the overbar. Therefore a signal such as -ADL in th IBM documentation would be represented
as ADL herein.

CHiPS _______________P_RE_L_'M_'_N_A_RY
82C614
Bus Master MicroCHIPTM

Highlights
II

Single Chip Bus Master Interface for the
Micro Channep·

Compatible with Subsystem Control Block
Architecture

Transfer Rates up to 20 Megabytes per
Second

Four Programmable Decode Outputs Provided

High Speed, Cost Effective Alternative to
DMA Slaves

Eight Multi-Function Pins Provide Maximum
Flexibility

Contains 4 DMA Channels with Integral
FIFO Buffer

Jointly Developed by Chips and Technologies and IBM®

101

Complete Micro Channel Interface Requires
Just 1 Component

III

Adapter Side has AT-like Structure for
Ease of Interfacing

Applications Include SCSI Host Adapters,
Hard Disk Controllers, LAN Adapters, High
Speed Communication Adapters, Modem/
FAX Adapters and many more.

III

144 Pin Plastic Flat Pack

iii

32 bit Address and 16 bit Data Support

Supports New Micro Channel Features
including:
- Steaming Data Transfers
- Data Parity Checking and Generation
- Extended POS
- Synchronous CHCK

MICRO
g~.~~NEL. _ _......'--I
DPARO 1

0iiAiiEN
INITROM
ARB/-GNT
BURST
PREEMPT

DREOS

DACKS

ADL CMD
SO Sl
SRO
SD STROBE

COMMANDS

MICRO
CHANNEL

AO-31

PROGRAMMABLE
DECODES

MULTI
FUNC
PINS

Figure 1. 82C614 MicroCHIPS Block Diagram

CHiPS ----------------------------------Overview
The 82C614 Bus Master MicroCHIP (Micro
CHannel Interface Part) is a single chip that
contains all ofthe logic required on an adapter
card to implement a Bus Master interface to
the Micro Channel. It is intended to give bus
mastering capabilities to adapter cards that
would normally use the system DMA controller. The advantages of bus mastering vs.
standard DMA include faster transfer rates
(up to 4 times) and the ability to easily
implement "full duplex" DMA. One of the
goals of the 82C614 is to allow adapter card
deSigners to take advantage of the performance improvements offered by bus mastering
while remaining cost competitive with standard DMA slave designs.
The 82C614 has four complete DMA Channels. Each channel has DREQ and DACK
signals on the local or adapter side to interface
to standard peripherals. The local side also
supports a full 16 bit data bus and up to 24
address lines. An integral 80 byte FIFO Buffer
is provided to "speed match" peripherals to
the Micro Channel and allow simultaneous
transfers to occur on the Micro Channel and
local sides for increased throughput. The
DMA Channels are compatible with the newly
defined Subsystem Control Block Architecture, including linked list chaining ability.
The 82C614 requires just one external '245
type transceiver to form the complete interface
to the Micro Channel. It supports a full 32 bit
address path and a 16 bit data path with parity
generation and checking. It supports the new
Streaming Data Procedure to achievetransfer
rates up to 20 megabytes per second, which is
four times the bandwidth available using the
DMA controllers in existing systems.

The local side features an AT-like set of
signals that ease in the interfacing of standard
peripheral components, as well as providing a
familiar environment for the designer to work
with. Eight Multi-Function Pins are provided
which may be programmed to provide a
variety of useful functions. This allows the
adapter side interface to be optimized for
individual applications while eliminating external components.
The 82C614 provides four Programmable Decode outputs that allow an adapter card to
also function as a slave. One of these outputs
is optimized for large memory spaces, one for
BIOS ROMs and the remaining two for I/O
spaces. I n addition, five more decode outputs
are available on the mUlti-function pins.
In summary, the 82C614 Bus Master MicroCHIP is intended to make it easy for the
designer to implement a high speed peripheral
adapter using bus mastering instead of standard DMA, with no cost penalties. Because of
the high level of integration provided by the
82C614, the design may require no external
components to interface to standard peripheral chips, and only one component forthe
Micro Channel side. It supports the new
features of the Micro Channel so that new
designs will be in step with both today's and
tomorrow's systems. New designs may never
be DMA slaves again.

MicroCHIP is a trademark of Chips and Technologies, Inc. Micro Channel is a trademark of International Business Machines Corporation.

<:rti~:;

________________________~A~D~V.~~N~C~E~IN~FO~R~M~A~~~IO~N
82C451 CHIPS Integrated VGA

•

Fully IBMT• VGA Compatible at hardware,
register and BIOS level.

•

Dual Bus Architecture. Integrated interface
to PC-Bus and Microchannel (CHIPS/250
and CHIPS/280).

•

Single Chip Solution.

•

Proprietary High Speed Interface to
CHIPS/250 and CHIPS/280 Systems.

•

Supports 8 and 16 bit CPU interface for
memory and I/O cycles.
Supports external palette DAC of up to 16
million colors.

•

CPU Interface

Resolutions up to 640*480 in 16 colors,
960*720 in 4 colors and 1280*960 monochrome.

•

Enhanced backward compatibility with
EGA, CGA, HerculesT. , MDA without using
NMI.

•

Processor Latches and Attribute Flip Flop
are readable.

•

Pinout Compatible with 82C452. Same
design can use both parts.

if the 16 bit interface is chosen, then depending
on the state of AD and BHE, either a 8 bit or 16
bit cycle will actually be executed. This ensures
compatibility with old software.

82C451 has a strap option to select a PC-Bus
Interface or a Microchannel Interface. All control signals for both the interfaces are integrated into the single chip.

All lID cycles are completed without wait
states. For memory cycles, the cycles are
extended with wait states.

82C451 supports both a 8 bit and 16 bit CPU
interface. The 16 bit interface can be independently enabled/disabled for memory and
lID cycles. On reset, the chip is configured
for 8 bit accesses for memory and I/O cycles.
16 bit interface for lID cycles is restricted to
index/data pair of registers. This includes the
Sequencer (3C4h), Graphics Controller (3CEh),
CRT Controller (3B4h/3D4h) and the Attribute
Controller (3COh). All other I/O addresses
(color palette, Misc Output and Status) are
always treated as 8 bit ports.

ADDRESSI
DATA MULTI·
PLEXER

•

82C451
~

EXTERNAL CPU
INTERFACE

ATTRIBUTE
CONTROLLER

MEMORY GRAPHICS CRT CON.
CONTROLLER CONTROL· TROLLER
(SEQUENCER)
LER

I
if'

PALETTE
DAC

ANALOG
VIDEO
DIGITAL
VIDEO

DRAM

82C451 System Diagram

1/88 REV 0

CHiPS _____________________________
Display Modes and Resolution
82C451 supports a superset of all VGA display
modes. It supports resolutions upto 640*480
in 16 colors, 960*720 in 4 colors and 1280*960
in monochrome.

the Graphics Controller and the Attribute
Flipflop are readable in the extended register
space. No new bits are defined or any of the
unused bits used in the regular VGA registers.

External Palette Interface
82C451 supports programming of an external
palette DAC by decoding the CPU addresses
and generating the RD and WR signals to the
external palette. 82C451 decodes liD addresses
3C6-3C9h as valid external palette addresses.

CH.PS _______________
CHIPS 82C574
MICROCHANNEL INTERFACE CHIP
[;I

Compatible with IBM Microchannel specifications

Sophisticated Card Channel Ready signal
generator.

I!!I

Provides highly integrated Microchannel
interface solution

III

Flexible Card 10 assignment

Two modes of operation:
Mode 1 for general purpose 8 bit slave 1/0
peripherals

Ell

Supports POS registers

Mode 0 for 82C570 CHIPSLlNK application

Resource relocation capability to avoid
address conflict

Ii]

Low power CMOS technology

.. 68 pins PLCC package

Flexible Interrupt level selection
In mode 1 operation, the 82C574 supports the
microchannel bus interface to most 8 bit 10
slave devices. The adapter 10 address can be
programmable during the setup procedure.
This resource relocation capability avoids conflicts with the adapter's address. The interrupt
level can also be selected via software. The
82C574 greatly simplifies the circuitry to interface to the microchannel bus.

The 82C574 is a highly integrated Microchannel
interface chip for IBM PS/2 personal computer
application. It can be configured to operate in
either of two modes; "mode 0" for 82C570
CHIPSLlNK 3270 coaxial protocol controller
or "mode 1" for tbe 8 bit general purpose 10
slave peripherals.
When mode 0 is selected, the chip decodes
the 10 address of 02DXH and 022XH for IBM
& IRMA registers and generates the lORD,
10WR signals for 82C570. It also decodes the
memory space of OCEOOO to OCFFFF for the
display buffer and external micro code access
by activating the MEMRD, MEMWR signals.
00-7

100-15

-I

DATA

The 82C574 is fabricated using advanced
CMOS technology and is packaged in a 68
pin PLCC.

BUFFER

P;= ~

POSIO

REGISTERS

Rl0a,101

MADE24

CDsEffiii

So, ii, MiiO

R102-105

READY
CONTROL
LOGIC

IRQSLO-1

RDYIN
CDCHRDY

lonD

COMMAND
DECODE

CMD

POS
REGISTERS

PERIPHERAL
COMMAND
GENERATOR

IOWA
MEMRD

MEMWR

•

CARD SELECT
FEEDBACK

LOGIC

AD-23

ADL
MASKo-3

MATCH

Lo.
RESOURCE
RELOCATOR

•

ADDRESS
LATCH

Figure 1. 82C574 Functional Block Diagram

A00-3

CHiPS _______________
82C575
COMMUNICATION MICROCHANNEL'M INTERFACE CHIP
•

Compatible with IBM Microchannel'M specifications
• Provides highly integrated Microchannel'·
compatible interface solution for most
communication adapter applications
I!! Suitable for most 8 bit slave 10 peripheral
applications
• Unique and flexible Card I D assignment
• Supports POS registers
• Four POS register bit outputs for system
configuration

•

The 82C575 is a highly integrated Microchannel'· compatible interface chip for use in
personal computer applications compatible
with the IBM PS/2 standard. It supports the
Microchannel'· compatible interface to most
of the 8 bit 10 slave devices. The adapter 10
address can be programed during the setup
procedure, this resource relocation capability
avoids adapter address conflicts. The interrupt
level can also be selected via software. The
on-chip wait state generator allows the user
to optimize the system bus timing to his/her
specific needs. A unique Card 10 generator
does not require any external components.

All these features greatly simplify the design
of a circuit to interface to the Microchannel'·
compatible bus.
The 82C575 supports application markets such
as intelligent Modems, SOLC/BISYNC/UART
adapter card applications, instrumentation, etc.
The dual resource relocater provides the
capability to support multiple peripheral system with a maximum of 32 10 address space.
The 82C575 is fabricated using advanced
CMOS technology and is packaged in a 68
pin PLCC.

•
•
•
•
•

Resource relocation capability to avoid
address conflict
Dual resource relocators to support multiple peripherals per card
Sophisticated Card Channel Ready signal
generator
On chip system wait state generator
Low power CMOS technology
68 pins PLCC package

• IBM is a trademark of International Business
Machine corporation.

DO.'

RESET

COSETuP
SO,51, M/iO
COMMAND
OE~ODE

CARD SELECT

FEEDBACK
LOGIC

CTLA

CTL"

DUAL

RESOURCE

MASK2_3

PRMCs

RELOCATOR
ADDRESS LATCH

,..."
Figure 1. 82C575 Functional Block Diagram

Publication No. 4-475-8

3/88 REV 0

\:tti~!i

__________________________________~P~R~E~LI~M~IN~A~R~Y
82C578 CHIPSterm™
SINGLE CHIP 3270 TERMINAL CONTROLLER

iii

Complete 3270 Terminal Controller on a
single chip

III

High speed microengine (10 MIPS) with
64K Bytes of Memory, 32K of I/O, and
128K of Font

iii

User-definable screen formats:
Color remapping and background color

•

Unique 3-way arbiter to evenly balanced
memory cycles

III

Flexible display list processor for soft
screen formats, multiple windows, multiple interlaced and non-interlaced displays

III

Supports both color and monochrome
monitor up to 60MHz dot clock

III

16mA Centronics™ parallel interface

Supports individual scan line display and
random scan line

Light-pen interface

Supports all 3270 modes and receives
3299 packets

Variety of Rules: cross-hair, vertical and
horizontal
Overscan
III

User definable Character size: 5-16 wide
by 1-32 pixels high

Download feature for more economical
solution

[] Programmable wait-states for slow
peripherals
IJ

Supports both AT- and PS/2-Compatible
style keyboards

EEPROM support

CMOS technology in 144-pin PFP package

BUZZER(4)
FONT

----CODE

FAO-15
FDO-15

DISPLAY LIST
PROCESSOR
ATTRIBUTE DECODER

(OPT)

rll

MCS1,MCS2,RD,WR
AO-15
00-15
EECS

SRAM
8Kx8

EEPROM

BUS
IIF

-1

3WAY
ARBITER

I
~

18,8696MHz

c:::::::::J
~

KEYBOARD IIF
LIGHTPEN

LS125

KBCLK,KBDATA
LPSTRB, LPSW
PDO-7,SLCTIN,AFX

PRINTER IIF
TIMER
DISPLAY IIF

COAX ENGINE

COAX IIF REG

SEQUENCER

COAX Tx/Rx

INIT,STRB,ACK,PE
BUSY,SLCT,EFiFiQR
RGB,INT,VSYNC
HSYNC,DCLK1·3

TxDLY,TxD
TxACT,RxD

POR-

Figure 1. 82C578 Application Block Diagram

LS37

TRANS· \
FORMER

\:tiifi:i __________________________________________________
3270-compatible terminal consists of 2 buffer
SRAM, 1 fonts EPROM, 1 configuration
EEPROM, a transformer, an LS374 to drive the
RGBI signals, and an LS125 for the buzzer.

Ordering Information
Order Number

Package Type

P82C578

144-pin Plastic Flat Pack

Absolute Maximum Ratings
Parameter

Symbol

Supply Voltage

Vee

Input Voltage

Min

Max

Units

7.0

V
V

-0.5

5.5

Output Voltage

-0.5

5.5

Operating Temperature

Top

-25

°C

Storage Temperature

TSTG

-40

125

°C

Note 1: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions described under Operating Conditions.

Normal Operating Conditions
Parameter

Symbol

Min

Max

Units

Supply Voltage

Vee

4.75

5.25

Ambient Temperature

0.8

Power Supply Current

lee

Input Low Voltage

VIL

-0.5

Input High Voltage (except X1, DX1)

VIH

2.0

Vee+0.5

3.5

Vec+0.5

0.4

Input High Voltage (X1, DX1)

VIH

Output Low Voltage (note 2)

VOL

Output High Voltage (note 2)

VOH

Input Leakage Current

ilL

-10

/loA

Output Tri-State Leakage

IOL

-10

/loA

Input Capacitance (Fe = 1MHz)

CIN

Output Capacitance

COUT

I/O Capacitance

CliO

2.4

Note 2: IOL = 16mA, IOH = -2mA for pins PPD0-7, SDATAO-~ __
IOL = 8mA, IOH = -2mA for pins SADo-14, MCS1-2, SWR, SRD, EXTINTR, ROT, EXTIO
10L = 4mA, IOH = -2mA for all other pins.

\:ttl~!i

___________________________________P~R~EL~I~M~IN~A~R~Y
82C601
SINGLE CHIP PERIPHERAIL CONTROLLER

iii

100% Compatible with IBM PC XT/ATT"

[;I

Two 16450-Compatible UARTs

Ell

One IBM PC XT/AT-Compatible Enhanced
Parallel

ADAPTER mode functions:

Game Port Decodes

Select Pins for Serial & Parallel ports

III

Schmitt Trigger RESET Input

c:J

Internal Address Decoders

III

EISA Ready (MOTHERBOARD mode)

MOTHERBOARD mode functions:
-

IDE Interface

Real-Time Clock Chip Select

General Purpose Chip Select

Relocatable Ports

Relocatable IRQ

Interrupt Sharing Capability

c Low Power CMOS

The 82C601 features two 16450-compatible
UARTs, an enhanced parallel port, an IDE hard
disk interface and chip selects (MOTHERBOARD mode) or select pins and Game port
decodes (ADAPTER mode).
ADAPTER mode where the base addresses
are determined by the select pins.
MOTHERBOARD mode where all the ports are
relocatable, and power management that invcc

Power Saving & Power Down Modes

c 16mA and 24mA Output Drivers

80-pin PFP or 84-pln PLCC packages

cludes power down for each port, oscillator
disable, and chip power down using the
PWRGNO pin.
The host interface is PC-compatible, i.e. DOD?, AO-A9, lOR, lOW, AEN, INTR1, INTR2,
INTR3, INTR4, and RESET, and can be connected directly to the bus. The system bus
interface buffers (00-07, INTRl-4) are capable
of sinking 24mA, the parallel port interface
signals are capable of sinking 16mA.

vss

PWRGD
DBDIR
MODE

ACK, PE, ERROR
BUSY, SLCT
PDD-7
STROBE,INIT
SLCTIN. AUTOFD
TxD,m, DTR

SAO-9
SDO-7
INTRl-4
DRO.DACK
iQii, lOW
AEN, RESET

RxD.~iIT

,----....r.-DSIl, u<;D

U-r---"1--L.- TxD, !IT§, QJR
!!!Q, m,.RI
DSR,DCD

Xl
X2

Figure 1. 82C601 Block Diagram

CHiPS
Absolute Maximum Ratings
Parameter

Symbol

Min.

Max.

Unit

Supply Voltage

Vee

3.0

7.0

Supply Current

lee

tbd

Input Voltage

-0.5

5.5

Operating Temperature

°C

Storage Temperature

TSTG

125

°C

-40

82C601 DC Characteristics
Symbol

Test Condition

Vee

Min

Typ

Max

Unit

4.57

5.0

5.25

tbd

p,A

lee

PWRGD active, 1.8432MHz Osc. is on

ISTBY

Standby current without clocks,
@Vee MIN, PWRGD is inactive

IOL

VOL
VOL
VOL
VOL

IOH

VOH MIN = 2.4V
VOH MIN = 2.4V
VOH MIN = 2.4V

IlL

Vee MAX, VIL = 0.4v, all inputs

-20

p,A

IIH

Vec MAX, VIH = 2.7V, all inputs

-20

p,A

VIL

All inputs

VIH

All inputs

VOL

IOL MAX, Vee MIN, VIL MAX, VIH = 2V

VOH

IOH MAX, Vee MIN, VIL = 0.5V, VIH = 2V

MAX = O.4V
MAX = 0.4V
MAX = O.4V
MAX=O.5V

Ordering Information
Part Number

Package Type

P82C601

84 PLCC

F82C601

80PFP

ISTBY

2.0
8.0
16
24

mA
mA
mA
mA

-0.2
-1.0
-8.0

mA
mA
mA

0.8
2.0
0.4
2.4

V
V
V

<:rtl~!i

_________________________________________P_R_E_L_IM__IN_A_R__Y

82C710 PC-AT MULTIFUNCTION FLOPPY CONTROLLER
I:iI

Low Power Advanced 1.5J.t CMOS Technology, 100 QFP Package

I:J

16450-Compatible Serial Port

l1li

.. Integrated Floppy Subsystem
-

J.tPD72065B-Compatible Floppy Controller

Enhanced Bi-Directional Parallel Port
with 16 mA Output Drive

Analog PLL with Transfer Rates Up To
1 Mbits/s

III

General Purpose Programmable Chip
Select

48 mA Floppy Drive Interface Buffers

III

PS/2-Type Mouse Port Logic With Driver
Support

Programmable Precompensation
Modes

I DE Interface For Embedded AT & XT
Hard Disk Drives

1:1

100% IBM PC-XT/AT Compatible Register
Set

16 mA PC-XT/AT Host Interface Drive
Capability

III

Complete On-Board Power Management
Features

PS/2 MOUSE PORT

MDATA, MCLK

SERIAL PORT

TxO,RTS,OTR
RxD, CTS, RI
OSR,OCO

PARALLEL PORT

ACK, PC, ERROR
BUSY,SLCT
PDO-7
STROBE, INIT
SLCTIN, AUTOFO

IDE INTERFACE

IDEENL,IOEENH
HDCSO, HDCS1
IOE7,IOCS16

MINTR, FINTR
SINTR, PINTR
Ao-A9,AEN
lOR, lOW, RST
Do-D7, OAK
ORO, TC
OBOIR, PWRGO

HOST INTERFACE

FDC

GPCS,RTCCS

DECODER

ANALOGPLL

Functional Block Diagram

RDATA, WOATA, WGATE
DRVO,DRV1,MTRO,MTR1
OIR, STEP, TRKO, HDSEL
WRPT, INDEX, OSKCHG
FILTER, FGN 0250/500
PUMP/PREN, ORVTYP
SETCUR, RPM/LC, RVI

CHIPS _ _ _ _ _ _ _ _ _ __
The 82C710 is a single chip offering the complete I/O solution for the PC-XT & PC-AT
motherboard environments today. The 82C710
provides the functionality of a 16450-compatible UART, which when coupled with a
145406 and a 1488 results in the implementation of a complete PC-XT/AT serial port. The
parallel port is just like the oneon the PC-XT/AT
and supports the PS/2-like bi-directional mode
of operation. In addition it supports a drive
capability of 16 mA, which alleviates the need
for external buffers. A PS/2-like mouse port is
provided, along with the drivers necessary to

support it in a PC-XT/ATenvironment. The IDE
interface logic needed on the host end to support embedded XT/AT hard disk drives is
provided by the 82C710, thereby contributing
to lower chip count on the motherboard. A
complete floppy subsystem consisting of a
JLPD720658 floppy core, an analog data
separator, capable of transfer rates up to 1
Mbits/s and the host interface registers, is onboard in the 82C710. The 82C710 provides
complete power management, and software
configurability, thus providing the most optimum solution of its kind in the market today.

c:t1B~:;

________________________________

~P~RE~L~IM~I~N~A~RY

82C780 MICRO CHANNEL-COMPATIBLE HARD DISK CONTROLLER
iii

Low Power advanced 1.5p CMOS technology, 144 QFP package

NRZ Disk Data rates up to 15 Mbits/s

III

Provides 16-bit CRC and 32/48-bit ECC with
hardware correction

[] 5 volt single power supply
I:J

On board Micro Channel'" Compatible
Arbitration & Bus Acquisition logic

III

Programmable Disk Sequencer RAM (30 x
4) bytes

III

On board Fixed Disk POS registers & programmable Card 10 support

III

Supports 8751 & 68HC11-compatible microcontrollers

Programmable burst length for DMA
transfers

III

Provides support for microcontroller access
of local buffer

[] Supports ST506 Fixed Disk register file for
command & status

Supports 1:1 interleave

48 mA configurable 1/0 port for disk control
signals

Slave DMA controller supports up to 5
Mbytesls microchannel bandwidth

Capability to address up to 64K of local
buffer memory (static RAMs)

'''..M'·i

MICRO CHANNEL SIGNALS

...

BURST, CHRDY,
CMD, MilO, etc.

6
o

DMA STATE M/C

I
I
I
NRZIN
T
NRZOU

~
III

w
0
:;

'I
o

:l;

III

BUFFER
MANAGER

I
J

r---t-I

HOLD 1&2
DATA 0-7

--------

SEQUENCER

----;

CONTROLS

DISK DATA PATH SIGNALS
~

---<

SYNC DETECT

ECC LOGIC

o a:
a:

DECODER
+
/JPREG
INTERFACE

00-7

I
1= H
~I
-1=
t=-- rl
_______________ J

-f+-

r--

I
1

SERDESAND
COMPARATOR

STACK

w
....I

~I-

MICRO CHANNEL
INTERFACE &
ARBITRATION

-l

MICROCONTROLLER

MEMORY STROBES

~I
a:

ill I

lI::

:Sl

l;!1

....I

---<

CLOCK GNTR

FORMATTER

Figure 1. 82C780 Block Diagram

til

t.'

w
w

Ii:0

If
a:

§1

II:

w
li!!:
W
>

...
c(

...co

\:l1iF'!i _________________________________________
The 82C780 is a single chip hard disk controller for Micro Channel based IBM PS/2T"Compatible personal computers. It consists
of three main blocks, viz. the microchannel
interface block which controls the microchannel arbitration and bus acquisition, the data
manager block which controls the transfer of
data between the local buffer memory and the
host or disk and the formatter block which
controls the disk sequencing process as well
as the interface to the local microprocessor.
When used in conjuction with the 82C784, it

facilitates the implementation of a low cost
Fixed Disk Adapter for the PS/2-Micro Channel-Compatible environment. This solution
optimizes board space, cost savings, while
providing increased performance. The high
level of integration requires only a microcontroller like 8751, microcode ROM and a
pair of buffers in addition to realize the
complete Fixed Disk Adapter. Also the flexibility of the 82C780 & 82C784, results in
simultaneous handling of MFM, 2,7 RLL and
even ESDI type of disk drives.

<:rti~:;

__________________________________

~P~R~EL~I~M~IN~A~R~Y

82C781 HARD DISK MICRO CHANNEL INTERFACE CHIP
III

Low power advanced 1.51l CMOS technology

III

Provides optional, register-definable
CAR D ID in conjunction with the 82C782.

III

On-board Micro Channel'· Compatible
Arbitration Logic

III

Provides synchronous and asynchronous
bus transfer cycle extension

•

On-board Bus Acquisition Logic

III

Programmable burst length capability

On-board POS 102 and 103 register

III

Provides CARD ID read controls

Provides external read decodes for diagnostic registers

Provides programmable address select
capability through the POS 104 and 105
registers

III

68-pin PLCC or SO-pin Flat Pack

Functional Description:
The 82C781 Hard Disk Micro Channel Compatible Interface Chip provides the interface
between the Micro Channel bus and the hard
disk controller orother DMA/IO slave-oriented
peripherals.
When used in a hard disk mode, it works in
conjunction with the 82C782 Hard Disk Data
Manager Chip to facilitate bus acquisition and
DMA transfers. It also decodes the bus addresses and status (MilO, SO, S1) for I/O slave
reads. When used in the general purpose
mode, it will work in conjunction with other

DMA or liD slave peripherals (as long as the
handshake requirements are met) to provide
the Micro Channel interface functions.
Together with the 82C782, a disk formatter and
a data separatorlendec,the 82C781 provides a
very cost-effective and high-performance implementation of the Fixed Disk Adapter for
systems compatible to the PS/2 environment.
On the other hand, the 82C781 provides the
Micro Channel interface for other DMAIIO
slave oriented peripheral adapters, thus allowing the designer to concentrate on the main
task of adapter design.
XDO-7 (HOST DATA)

- BURST

-PREMPT

.
'II

BURST
LOGIC
&

CNTR

BRST<4:7>

r--r
r--r
~

AR8Q-3

•
PREMPT •

ARB/GNT

ARB
LOGIC
& DMA
STATE
MIC

DACK
DMAREQ
CDCHRDY

L--.J

POS 102

lDMACONTRO L

POS 103

ARB & BURST

I/O RELOC-L

POS 104

<7:0>
<11:8>

POS 105

1/0 RELOC-U & MASK

ARBID<3:0>
RAO-ll
AO-1S

I4
I

ADDRESS
DECODE

CDSFDBK

CHRDY
STATE MIC

• DTRDT (P)

CDSFDBK

Figure 1. 82C781 Block Diagram

\:r;i~:;

______________________________________~PR~EL~'~M~'~N~A~R~Y
82C782 HARD DISK DATA MANAGER

•

Low power advanced 1.Sp CMOS technology

•

PS/2 T • Model SO/60-compatible

•

On-board register file for command and
status

•

Slave DMA controller, max 2.S M Bytes/s
to the host

•

8-/16-but data pipeline to sustain high
bus transfer rates

•

On-board address generation for local
buffer

•

Provides address generation during local
CPU buffer accesses, with optional autoincrement capabilities

Functional Description:

•

Addresses up to 64K of static RAM

•

Supports both 87S1 and 68HC11
microcontro"er families

•

Provides interrupt to the local CPU

•

Supports Adaptec AIC-011 and compatible formatters

•

Supports 1:1 interleave

•

Supports STS06 type drives

•

84-pin PLCC package

transfer of data between the disk and local
buffer and also between the local buffer and
the host. It ensures an interleaved data transfer
between disk and host, and hence facilitates a
1:1 interleave capability. It operates at 10MHz
and supports up to 64K of direct static RAM

The 82C782 Hard Disk Data Manager Chip
provides the DMA, buffer management and
register file functions forthe Fixed Disk Adapter in the PS/2-Micro Channep· environment.
The slave DMA controller is responsible for

RAO 15
ADO-7

HOST DATA BUS

ATTENTION
STATUS

l
CONTROL

INTR STATUS

DREO
DACK.

FIFO
& DATA
ALIGNER

HOST DMA
MACHINE

HOSTPTR
DISK PTR

-.!!.!!L
ClK

~
~

D-SKClK.
D--SKREO.

STOP

1co

CONTROL

BUFFER
MANAGER

WR BYTECTR

•

'--

ADAPTERID
RDATAO-7 (FROM RAM)

Figure 1. 82C782 Block Diagram

\:ttl~!)

__________________________________________________

addressing capability. It also provides the
PS/2-Compatible register file of Control,
Status, Atention and Interupt Status register.
The 82C782 works in conjunction with the
82C781 and a local microcontroller to provide

the data path functions between the disk and
the host. This, combined with a disk formatter
and a data separator/endec, results in a lowcost Fixed Disk Adapter implementation for
systems compatible with the PS/2 environment.

<:ttifi!) _______________________________________P~R~E~L~IM~I~N~A~R~Y
82C784 MFM/RLL DATA SEPARATOR & ENDEC
•

Low Power advanced 1.511 CMOS
technology

•

Onboard 5 Mbits/s MFM(1,3) encoder/
decoder

•

Onboard 7.5 Mbits/s RLL(2,7) encoder/
decoder

•

Synchronous start-up Phase-Locked Oscillator (PLO)

•

MFM Write Precompensation with built in
delay line

•

Onboard Address Mark Detection circuitry

•

Provides NRZ interface to the disk controller chip

•

Dedicated Analog Vcc/Gnd for better noise
immunity

•

Onboard 48 mA drivers/receivers for disk
data lines

Single +5V operation (Digital & Analog)

44 pin PLCC package

De-glitched Read/Reference Clock output
82C780, it results in the implementation of a
low cost Fixed Disk Adapter for the PS/2_T"
Micro Channel T" Compatible environment and
greatly reduces board space, while enhancing
the performance.

The 82C784 provides the Data Separation
function and a user selectable MFM or 2,7RLL
encode/decode function, for the Disk Data
Path. When used in conjunction with the
Xl
X2
WG

==1

REFCLK
GENR

~WCLK
MFM

MFM/2,7

r--

ENCODER

EN DATA

PRECOMP
DELAY
GENR

WCLK
AMGENR

PCEN

f--+

MUX
&
DIFF
DRYRS
EN

27DATAr

RLLlMFM

-'
-'
-'
-'

WDATA1+
WDATA1WDATA2+
WDATA2-

DRVSEL 1,2

I AM DETECT
I
NRZ
RD/REFCLK

MFM/2,7
DECODER

~ ---<

=p.

DLYDATA

VCOCLK

TPO
TPl

PHASE
DETECT
&
CONTROL
LOGIC

I
11111

SYNC
DETECTOR
&
DIFF
RCVRS

PLO

. . . Iii

!::

!Zo ...U):::!oa~
- ~ •.
9
Figure 1. 82C784 Block Diagram

...

---

RGATE

RDATA1+
RDATA1RDATA2+
RDATA2-

CHiPS ________________
The 82C784 boasts of a high level of integration
by supporting both the MFM & RLL encode/
decode schemes, along with the synchronous
start-up Phase Locked Oscillator and the dif-

ferential driver/receiver pairs for the disk data
path signals. The advanced architecture also
results in the use of a minimum number of
passive components.

C:tti~!i

____________________________________~P~R=EL~I~M~IN~A~R~Y
OC8281
NEATsX™ PC AT®-COMPATIBLE BIOS

•

Fully compatible with the IBMTM AT BIOS

•

Optimized for performance with the
CS8281 NEATsx CHIPSetT•

Built-in support for CHIPS Multifunction
Controllers

•

Developed using Clean-Room Methodology

•

Easy customization of key BIOS
parameters

•

Includes Keyboard Controller BIOS

•

Supports 80386SX processor

•

Supports CPU speeds up to 20 MHz

•

Built-In Development/Debug Support

•

SETUP embedded in BIOS

•

Total Hardware/Software Support

Embedded SETUP program for machine
configuration

Moving BIOS to shadow RAM to improve
performance

Dynamic memory sizing

Setup of CHIPSet EMS registers

The OC8281 New Enhanced AT-Compatible
(NEATsx) Basic Input/Output System (BIOS)
is an enhanced, high performance product
that is used with the CS8281 NEATsx CHIPSet
to provide an integrated hardware and software solution. The BIOS is fully compatible
with the IBM AT BIOS. It provides all of the
standard features, including support for:
-

80386sx processor and 80387sx math
coprocessor operating at clock speeds
from 6 MHz to 20 MHz

84, 101, or 102 key keyboards

High and low capacity S.2S-inch or3.S-inch
diskette drives

Monochrome and CGA video adapters

Power-on self test diagnostics

Complete BIOS Solution
The OC8281 BIOS is available in two forms to
best meet the needs of the OEM. The SK8281
BIOS Software Kit provides a productionready master copy of the system BIOS, a keyboard controller BIOS, and utility programs to
customize the BIOS and support the development/debug process. The SC8281 BIOS
Source Kit provides the source code and
documentation for the system and Keyboard
Controller BIOS, as well as all support utilities.

BIOS Extensions
The BIOS utilizes the extended capabilities of
the CS8281 CHIPSet to provide the user with
enhanced functionality and better performance. The BIOS is also designed to be customized by the OEM and to be easily used in
the development/debug process. The additional functions include support for:
-

B2C2061ntegrated Peripheral Controller

82C601, 82C604, and 82C60S Multifunction
Controllers

All CHIPS BIOS products are designed to be
customized to meet OEM requirements. A
BIOS modification utility program is provided
in both the software and source kit. It allows
many common modifications of BIOS and
CHIPSet configuration parameters, including
the fixed disk table, the default CMOS values,
and the sign-on message. This provides a
method for an OEM to customize the BIOS
without requiring access to the source code.
The consistent, modular structure of CHIPS'
BIOS products allows creation of additional
modules to support custom applications.

c:rti~!i

_____________________________________________

Once a module is developed, it can be integrated into the BIOS with minimal effort.
CHIPS also provid!3s in-house customization
services.

products using industry standard software
and hardware. CHIPS has a technical support
staff available to assist in resolving any
hardware or software problems that may arise.

CHIPS system BIOS products are designed
with built-in support to aid in the development/debug process. The BIOS is designed
to allow the CHIPSet registers to be loaded
from saved information during power-up. The
registers and their values that will be loaded
can be controlled by a program that is included in the software kit.

Ordering Information

Clean Room Methodology

The BIOS was developed using a clean-room
methodology that helps ensure CHIPS BIOS
products do not infringe on any applicable
copyrights. The methodology used is well
documented and is available for review.

Total Hardware/Software Support
CHIPS offers complete hardware and
software support for customers using the
CS8281 CHIPSet with the BIOS. The CHIPSet
together with the BIOS have been extensively
tested for quality, reliability and compatibility.
CHIPS has an in-house compatibility test
department that tests all CHIPS BIOS

OC8281

NEATsx BIOS (Label)

CB8281 CS8281 NEATsx CHIPSet with
OC8221 BIOS (Label)
SK8281

NEATsx BIOS Software Kit

SC8281

NEATsx BIOS Source Kit

To obtain further information contact Chips
and Technologies, Inc. oryour local sales representative.

<:;;i~!i

________________________________________

P_R_E_L_IM
__IN_A_R_Y_

DK82C611/82C612
MicroCHIPSTM Development Kit
•

Provides general-purpose Micro Channel™-Compatible Interface with Large prototyping area

•

Double Height board provides plenty of
prototyping area but can be converted to
standard height card

•

Evaluate CHIPS 82CSn or 82CS12
MicroCHIPS

•

Interface meets all Micro Channel
Specifications

•

Saves time in prototyping your adapter
design

•

Proven prototyping pattern designed by
Vector Electronic™

•

Contains 82C611 and 82CS12 with commonly used support circuitry consisting
of:
- I/O and Memory Address Decode PAL
sockets

•

16-bit Micro Channel connector with
Video Extension

•

Low-power operation

•

Includes both 82C611 and 82C612 components.

":".,

Data Bus Buffers (for 8- and/or 16-bit
operation)

Address Latches for all 24 address
lines

ID driver for any 16-bit ID value

Overview
The DK82C611 /82C612 is designed to facilitate
both the evaluation process for the CHIPS
82C611 or 82C612 and the design process of
your adapter circuitry. This is accomplished by

combining a pre-wired general purpose interface to the Micro Channel with a generous
amount of prototyping area.
The DK82C611182C612 consists of an 82C611
or 82C612 MircroCHIp, data bus buffers for
8-bit operation (socket provided for optional
buffer 16-bit operation). sockets for memory
and I/O address decode PALs and sockets for
optional address latches for all 24 address
lines.

PROTOTYPING AREA
LATCHED
AOORESES

10
SELECT

20L8

82C611
OR
82C612
AO-23

07·0

SOSl

MIlO
MICRO CHANNEL

Figure 1. DK82CS11/82CS12 Block Diagram

CHIPS _______________
Because we have provided the majority of the
interface to the Micro Channel, you save time
and effort. You can use our circuit design in
yourfinal product, oryou may wish to optimize
it further. In any case, the DK82C611/82C612 is
an optimal vehicle for getting started.

placement. Wire-wrap and solder techniques
may be used equally well. The board is twice
the height of a normal Micro Channel card to
provide extra room for prototyping. However.
it may optionally be converted to a standard
height card.

The prototyping area ofthe DK82C611/82C612
is based on the proven "pads and planes" pattern developed by Vector Electronicspecialists in the field of prototyping boards.
This pattern provides a maximum of noise immunity and flexibility in component type and

The standard Micro Channel brackets are
provided. The rear of the card has a pattern
useful for mounting liD connectors and the
rear bracket has punch-outs to accommodate
a wide variety of connectors.

CHiPS _________________________

HIGH-END CHIPSet SOLUTIONS

CHiPS ____________________________
CS8231: TURBO CACHE-BASED 386/AT CHIPSet
82C301 BUS CONTROLER
82A303 HIGH ORDER ADDRESS BUFFER
82A304 LOW ORDER ADDRESS BUFFER
82B305 DATA BUFFER
82A306 CONTROL BUFFER
82C307 INTEGRATED CACHE/DRAM CONTROLLER
T•

80387
NPX

8742

KBD
CNTR

82C206

IPC

ROM
BIOS

82C306
CNTR

BUFFER

Figure 1. Chips Turbo 3S6/AT Cache Based System Block Diagram

The CS8231 TURBO CACHE BASED 386/AT
CHIPSet is a seven chip VLSI implementation
of most of the system logic to implement a
CACHE BASED iAPX 386 based system. The
CHIPSet is designed to offer a 100% Ar~
compatible integrated solution. The flexible
architecture of the CHIPSet allows it to be
used in any iAPX386 based system design,
such as CAD/CAE workstations, office systems, industrial and financial transaction
systems.
The CS8231 CHIPSet combined with CHIP's
82C206, Integrated Peripherals Controller,
provides a complete PC AT-compatible system using only 40 components plus memory
devices.
The CS8231 CHIPSet consists of one 82C301

Bus Controller, one 82C307 Integrated
CACHE/DRAM controller, one each of 82A303
and 82A304 Address Bus Interfaces, two
82B305 Data Bus Interfaces, and a 82A306
Control Signal Buffer.
The CHIPSet supports a local CPU bus, a
32-bit system memory bus, and AT buses as
shown in the system diagram below. The
82C301 and 82A306 provide the generation
and synchronization of control signals for all
buses. The 82C301 also supports an independent AT bus clock, and allows for dynamic
selection of the processor clock between the
16MHz, 20M Hz, or 25MHz clocks and the AT
bus clock. The 82A306 provides buffers for
bus control Signals in addition to other
miscellaneous logic functions.

CHiPS ______________________________
The 82C307 is a high performance and
high integration CACHE/DRAM controller
designed to interface directly to the 80386
microprocessor. It maintains frequently accessed code and data in high speed memory,
allowing the 80386 to operate at its maximum
rated frequency with near zero waitstates. By
integrating DRAM control functions on-chip,
it supports simultaneous activation of cache
and DRAM access, thereby minimizing the
cache miss cycle penalty. It has hardware
support to allow the user to designate up to
four blocks (of variable size from 2KB to
128KB) of main memory as non-cacheable
address space. This feature is important for
compatibility issues when operating in a
multiprocessing or LAN environment, or
where dual-port memory is used, and to
deSignate certain regions of video RAM as
non-cacheable. This feature eliminates the
need to use very fast PALs externally to
decode non-cacheable regions and gives the
user much more flexibility. Optional EDC
support logic is integrated on to the 82C307
which allows it to interface to any of the
generically available 32-bit Error Detection

and Correction Circuits to realize a highly
reliable memory subsystem.
Cache coherency is maintained during DMA
cycles by channeling all accesses through
the cache controller logic. During DMA read
operations, the cache RAM is not accessed
and data is retrieved from the main memory.
During DMA write operations, if a cache hit is
detected, the cache RAM is updated and the
corresponding tag validated. Cache coherency is maintained at all times, with no performance penalty. The 82C307 is available in
a 100 pin PFP package.
The 82A303 and 32A304 interface between all
address buses, and the addresses needed for
proper data path conversion. Two 82B305 are
used to interface between the local, system
memory, and at data buses. In addition to
having high current drive, they also perform
the conversion necessary between the different sized data paths.

\:rtifi!i __________________________________________P_R_E_L_I_M_IN_A__R_Y
CS8233: PEAKset/386
82C311 CPU/CACHE/DRAM CONTROLLER
82C315 BUS CONTROLLER
82C316 PERIPHERAL CONTROLLER
T"

4KB to 4M) of main memory as noncacheable address space
Supports caching of data and code

•

100% IBM® PC AT®-Compatible CACHE
BASED 386/AT Compatible CHIPSet

•

Supports 16, 20, 25, 33 and 40 MHz 80386
based Systems

•

Independent clock to support correct AT
bus timing (SYSNC/ASYNC AT bus clock
option)

Supports control mechanism for preventing unnecessary disturbance of cache contents during I/O operation

•

Tightly coupled 80386 interface
Designed to interface directly with the
80386
Supports 16, 20, 25, 33, and 40 MHz
operation
Integrated support for 80387 and Weitek
3167 co-processor

•

DRAM Controller supports page mode
operation

•

Flexible memory architecture
Supports memory configurations up to
128MB
Programmable wait states
Supports 256K, 1MB, and 4MB DRAMs
in configurations of up to 4 blocks and
8 banks
Supports static column mode DRAMs
Supports staggared RAS during
refresh
Supports hidden refresh and burst
refresh
Supports 256K/512K/1M PROMs

•

Supports shadowing of BIOS EPROMs

•

Cache hit rate up to 99%

•

Includes interface logic to support the
82C636 Power Control Unit (PCU) for very
high-performance 386/AT based laptops
and portables

•

Flexible architecture allows usage in any
iAPX 386 T" design

•

A complete 386/AT CACHE BASED PC AT
now requires only 19 IC's plus memory

•

Integrates
Cache
Directory
and
CPU/CACHE/DRAM CONTROLLER on a
single chip to provide PEAK Integration and
PEAK performance

•

Integrated CPU/CACHE/DRAM Controller
enhances 80386 CPU and memory system
performance
Averages to nearly zero wait state
memory access
Zero wait state non-pipelined/pipelines
read hit access
Zero wait state non-pipelined/pipelined
write access
Buffered-write through DRAM update
scheme to minimize write cycle penalty

•

Supports 32KB, 64KB, and 128KB two-way
set associative cache organization
64 byte line size
4 byte sub-line size with associative
valid bit
Supports 4 blocks (of variable size

The CS8233 PEAKset/386 T" is a three chip
VLSI implementation of most of the system
logic required to implement a CACHE BASED
iAPX 386 T " based system. The CHIPSet is
designed to offer a 100% PC AT®-compatible

integrated solution. The flexible architecture
of the CHIPSet allows it to be used in any
iAPX386 T " based system design, such as
CAD/CAE workstations, office systems, industrial and financial transaction systems.

Printed in U.S.A.lS-89/Rev. 0

r:.!:

82C316
PERIPHERAL
/..l1li CONTROLLER

11_,

V'.

jr-

/I.

ADDRESS

o ,~O I ~OFS I""·

CONTROLLER

~~
h
/

CPU LOCAL BUS

IJ--

BUFFERS

MEMORY BUS

BIOS

82C315
.A
BUS
CONTROLLER
")
"'J.4ii

DATA
/,

VII
y. '7

80387
NPX

WEITEK
3167

CACHE
DATA RAM

~fY

82C452
SUPER VGA
CONTROLLER

DRAMS

82C311
CPu/CACHEI
DRAM
CONTROLLER

}

V/.

"82C601
SINGLE CHIP
PERIPHERAL
CONTROLLER

82C765
SINGLE CHIP
FLOPPY DISK
CONTROLLER

i,.'

/.
V

~
A

/
AT BUS

PEAK/38S'" SYSTEM BLOCK DIAGRAM

-rii=ii
::

-g~

_:::

/;
V

PERIPHEii~r
80386
CPU

..
:=
.1:::

\:tti~!i

____________________________________________________

The CS8233 PEAKsetl386™ provides a complete CACHE BASED 386/AT system using
only 19 components plus memory devices.
The CS8233 PEAKsetl386™ consists of one
82C311 CPU/CACHE/DRAM Controller, one
82C315 Bus Controller, and one 82C316
Peripherals Controller.
The CHIPSet supports a local CPU bus, a 32bit system memory bus, and AT bus as shown
in the system diagram.

82C311 CPU/Cache/
DRAM Controller
The 82C311 CPU/CACHE/DRAM Controller
provide the generation and synchronization of
control signals for all buses. The 82C311 also
supports an independent AT bus clock, and
allows for dynamic selection of the processor
clock between the 16MHz (or 20M Hz, or
25M Hz, or 33M Hz, or40MHz) clock and the AT
bus clock.
The 82C311 also contains a high performance
and high integration CACH E/DRAM controller
designed to interface directly to the 80386
microprocessor. It maintains frequently accessed code and data in high speed memory,
allowing the 80386 to operate at its maximum
rated frequency with near zero waitstates. By
integrating DRAM control functions on-chip, it
supports simultaneous activation of cache and
DRAM access, thereby minimizing the cache
miss cycle penalty. It has hardware support to
allow the user to designate up to four blocks
(of variable size from 4KB to 4MB) of main
memory as non-cacheable address space.
This feature is important for compatibility issues when operating in a multiprocessing or
LAN environment, or where dual-port memory

is used, and to designate certain regions of
video RAM as non-cacheable. This feature
eliminates the need to use very fast PALs externally to decode non-cacheable regions and
gives the user much more flexibility.
The 82C311 Cache Controller supports a twoway set associative cache architecture and
cache sizes of either 32KB, 64KB or 128KB. It
implements a buffered-write thru scheme and
a Least Recently Used (LRU) replacement algorithm.

82C315 Bus Controller
The 82C315 Bus Controller contains the data
buffers used to interface between the local,
system memory and AT data buses. In addition
to having high current drive, they also perform
the conversion necessary between the different sized data paths. The 82C315 also includes all the interface logic required to directly interface to the 80387 and Weitek 3167
co-processors with no additional discrete
logic required.

82C316 Peripheral Controller
The 82C316 Peripheral Controller contains the
address buffers used to interface between all
address buses and the addresses needed for
proper data path conversion. It also contains
an equivalent 82C206 Integrated Peripheral
Controller which incorporates two 8237 DMA
controllers, two 8259 Interrupt controllers, one
8254 Timer/Counter, one MC146818 Real Time
Clock, 74LS612 memory mapper, in addition to
several other TTL/SSI interface logic chips.
The 82C311, 82C315, and the 82C316 are all
available in 160 pin PFP packages.

<:;;ifi!i ____________________________~A~D~V~A~N~C~E~I~N~FO~R~M~A~T~IO~N
82C321,82C322,82C223,82C325,82C226,82C60~82C452

CHIPS/280™: COMPLETE IBM®PS/2TM MODEL 80.COMPATIBLE CHIPSet™
II

100% IBM PS/2 Model SO Compatible Chipset

III

Supports 20, 25 and 33 MHz S0386-based
Systems

I!I

Complete IBM PS/2 Model SO Compatible
Motherboard requires only 66 components plus memory
Available as CMOS PFP Components

Asynchronous CPU, DMA and Micro
Channel T" Operation

III

Advanced Page/Interleave Memory Controller with Integrated Bad Block Remapping Capability, Shadow RAM and LIM
EMS 4.0 Support

iii

Supports 4Mb DRAMs

SOns DRAMs @ 20MHz

SOns DRAMs @ 25MHz

60ns DRAMs @ 33MHz

Integrated Lotus®-Intel®-Microsoft® Expanded Memory Specification (LIM EMS
4.0) Memory Controller expandable to
full LIM EMS 4.0 specification with S
register sets of 64 mapping registers

High-performance Matched Memory interface for Micro Channel Memory Adapters at 20M Hz, 25MHz and 33MHz

PS/2 Model SO Compatible Address
Recovery Logic

r:J

User-Programmable I/O Decodes

SYSTEM LOGIC CS8238 CHIPSet
c

Slow DRAMs at high CPU clock speeds,
without wait state penalty: 0.5 to 0.7 wait
states with:

.;;:;;:;;-:;-i-.....-----T~-----;l,...-~--___:!-+-----.--.....+-PERIPHERAL
BUS

80386
CPU

r--~~~---~~---~~---~~----~~---LOCAL
r---~;_~--~~---~L----~L-----~~----

BUS

~A~0-~3~1~---------±~L-----~-----L-~--MICRO
_ _ _ _ _ _ _ _ _L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ CHANNEL
~M~D~0-~3~1

DEVICES FROM
CHIPS & TECHNOLOGIES

386-BASED MODEL 80
COMPATIBLE SYSTEM

Figure 1. CHIPS/2S0 Block Diagram

CHiPS ----------------------------------GRAPHICS
•

Enhanced Gate-level Compatible VGA

•

High-performance FAST VGA interface
to CPU controller

PERIPHERAL SUPPORT
•

Integrated Analog Data Separator and a
NS 16550-compatible serial port

CHIPS/280 is a 7-chip, Enhanced CMOS implementation of most of the system logic
necessary to implement IBM PS/2 Model 80
compatible personal computers. CHIPS/280
enables OEMs to offer PCs that are more functional, more integrated and higher in performance than IBM's Model 80.
CHIPS/280 includes the CS8238 System Logic
CHIPSet, the 82C607 Multi-Function Controller with an Analog FDC Data Separator and a
NS16550-compatible serial port, and the Enhanced Gate-Level Compatible 82C451 VGA
chip. With these 7 VLSI devices,it requires only
66 additional components plus memory to implement superior PCs to IBM's models.

System Logic CS8238 CHIPSet
The CS8238 System Logic CHIPSet consists
of the 82C321 CPU and Micro Channel Controller, the 82C322 Page/Interleave and EMS
Memory Controller, the 82C223 DMA Controller, the 82C325 Data/Buffer Controller and the
82C226 System Peripherals Controller. The
82C321 is available in a 100 pin PFP, the 82C322
and the 82C225 are available in a 144 pin
PFp, and the 82C223 and 82C226 are available
in both a 84-pin PLCC and 100-pin PFP
packages.
The 82C321 CPU and Micro Channel Controller manages the system timing for the
asyncrhonous 80386 CPU, DMA and Micro
Channel cycles. It supports CPU clock speeds
of 20, 25 and 33MHz. It supports all Micro
Channel cycles, along with Matched Memory
and Fast VGA cycles at 16, 20, 25 and 33M Hz.
It includes state machines for command and
control logic signal generation, DMA and
refresh logic control.

The 82C322 Page/lnterleave and EMS
Memory Controller provides an interleaved
memory subsystem design with page mode
operation. It supports 4 memory banks, with
memory configurations from 1MB to 16MB.
While operating under DOS, memory above
1MB can be treated as EMS memory, improving significantly the value of he large memory
organizations of the OS/2 era. The on-chip
EMS logic provides 4 mapping registers, however,with external EMS mappers, the full LIM
EMS 4.0 specification with 8 sets of 64 mapping registers can be implemented. Itsupports
static colum n DRAMS and shadow RAM BIOS.
It contains on-board I/O decode logic and IBM
PS/2 Model 80-compatible Address Recovery
Logic.
The 82C223 DMA Controller provides 8 DMA
channels for slave devices and the Central Arbitration Control Point (CACP) for the entire
system. Each DMA Channel has 24-bit address capability and can perform 8-bitor 16-bit
transfers. It also supports Virtual DMA so that
DMA Channels 0 and 4 can be used to service
multiple DMA slaves by multiplexing the DMA
Channels between the arbitration levels assigned to those slaves. It supports Multiple Bus
Masters via the CACP arbitrator and control
signals which enable Bus Masters to monitor
the readiness and data size of other adapters
and system board components. The Bus Arbitration logic includes protection mechanisms against error conditions, like burst-mode
devices not relinquishing the bus within the
specified time.
The 82C325 Data Buffer/Controller provides
high speed bus sizing and conversion to
enable the use of low speed DRAMs at high
clock speeds. It contains system POS
registers, and NMI as well as DRAM parity
generation and detection logic. Userprogrammable I/O ports, 82C607 Decode Signals, and 82C451 VGA Setup and Enable Signals are also contained in the 82C325.
The 82C226 System Peripherals Controller integrates PS/2-compatible peripherals in one
compact package, with an optimized bus interface to the Peripheral Bus. It includes two

CHiPS ----------------------------------8259-compatible interrupt controllers, one
8254-compatibletimer, one 146818-compatible
real-time clock, 114 bytes of CMOS battery
back-up SRAM and one PS/2-compatible Bidirectional Parallel Port.

Graphics
The 82C452 Gate Level-compatible VGA
provides 100% VGA-compatible graphics with
backwards compatibility to EGA, CGA, MDA
and Hercules. In VGA Graphics modes, it
provides resolutions from 320 x 200 with 256
colors to 640 x 480 with 16 colors. In VGA text
mode, it supports fonts up to 9 x 32.lt supports
all standard monitors - IBM PS/2 analog,
Multi-frequency, EGA, CGA and Monochrome.
The 82C452 boosts graphics performance
with a tightly-coupled high performance interface to the CPU and a 16-bit memory interface.
The 82C452 is packaged in a 144-pin PFP
package.

Peripheral Support
The 82C607 Multi-Function Controller integrates additional PS/2-compatible peripherals in one compact package. It includes one
NS16550 Compatible UART, an Analog Data
Separator, POS registers and Glue Logic for a
NEC® 765A Floppy' Disk Controller. The
82C607 is available in a 68-pin PLCC package.
Additional components that complement
CHIPS/280 are the MicroCHIPST• for Micro
Channel Adapters and EMS Mapper Chips.
The 82C610 and 82C611 MicroCHIPs can be
used for I/O intensive Micro Channel Adapters, while the 82C612 is applicable to Adapters
that require Slave DMA support.

<:rtl~:;

______________________________________

P_R_E_L~IM~IN
__A_R~Y

82C614
Bus Master MicroCHIPT.
Highlights
•

Single Chip Bus Master Interface for the
Micro ChannelT.

•

Compatible with Subsystem Control Block
Architecture

•

Transfer Rates up to 20 Megabytes per
Second

•

Four Programmable Decode Outputs Provided

•

High Speed, Cost Effective Alternative to
DMASlaves

•

Eight Multi-Function Pins Provide Maximum
Flexibility

•

Contains 4 DMA Channels with Integral
FIFO Buffer

•

Jointly Developed by Chips and Technologies and IBM®

•

Complete Micro Channel Interface Requires
Just 1 Component

•

Adapter Side has AT-like Structure for
Ease of Interfacing

Applications Include SCSI Host Adapters,
Hard Disk Controllers, LAN Adapters, High
Speed Communication Adapters, Modem/
FAX Adapters and many more.

•

144 Pin Plastic Flat Pack

•

32 bit Address and 16 bit Data Support

•

Supports New Micro Channel Features
including:
- Steaming Data Transfers
- Data Parity Checking and Generation
- Extended POS
- Synchronous CHCK

MICRO
g~_~~NEL _ _r''-f
DPARO 1

iiPAREN
INITROM

ARB/-GNT
BURST
PREEMPT

DREOS
DACKS

ADLCMD
SOSl
SRO
SO STROBE
MICRO
CHANNEL
AO-31

COMMANDS

PROGRAMMABLE
DeCODES

MULTI
FUNC
PINS

Figure 1. 82C614 MicroCHIPS Block Diagram

\:tilfi!i ___________________________________________________
Overview
The 82C614 Bus Master MicroCHIP (Micro
CHannel Interface Part) is a single chip that
contains all ofthe logic required on an adapter
card to implement a Bus Master interface to
the Micro Channel. It is intended to give bus
mastering capabilities to adapter cards that
would normally use the system DMA controller. The advantages of bus mastering vs.
standard DMA include faster transfer rates
(up to 4 times) and the ability to easily
implement "full duplex" DMA. One of the
goals of the 82C614 is to allow adapter card
designers to take advantage of the performance improvements offered by bus mastering
while remaining cost competitive with standard DMA slave designs.
The B2C614 has four complete DMA Channels. Each channel has DREQ and DACK
signals on the local or adapter side to interface
to standard peripherals. The local side also
supports a full 16 bit data bus and up to 24
address lines. An integral 80 byte FIFO Buffer
is provided to "speed match" peripherals to
the Micro Channel and allow simultaneous
transfers to occur on the Micro Channel and
local sides for increased throughput. The
DMA Channels are compatible with the newly
defined Subsystem Control Block Architecture, including linked list chaining ability.
The 82C614 requires just one external '245
type transceiver to form the complete interface
to the Micro Channel. It supports a full 32 bit
add ress path and a 16 bit data path with parity
generation and checking. It supports the new
Stream i ng Data Procedure to achieve transfer
rates up to 20 megabytes per second, which is
four times the bandwidth available using the
DMA controllers in existing systems.

The local side features an AT-like set of
signals that ease in the interfacing of standard
peripheral components, as well as providing a
familiar environment for the designer to work
with. Eight Multi-Function Pins are provided
which may be programmed to provide a
variety of useful functions. This allows the
adapter side interface to be optimized for
individual applications while eliminating external components.
The 82C614 provides four Programmable Decode outputs that allow an adapter card to
also function as a slave. One of these outputs
is opti mized for large memory spaces, one for
BIOS ROMs and the remaining two for 1/0
spaces. In addition, five more decode outputs
are available on the multi-function pins.
In summary, the 82C614 Bus Master MicroCHIP is intended to make it easy for the
designer to implement a high speed peripheral
adapter using bus mastering instead of standard DMA, with no cost penalties. Because of
the high level of integration provided by the
82C614, the design may require no external
components to interface to standard peripheral chips, and only one component for the
Micro Channel side. It supports the new
features of the Micro Channel so that new
designs will be in step with both today's and
tomorrow's systems. New designs may never
be DMA slaves again.

MicroCHIP is a trademark of Chips and Technologies, Inc. Micro Channel is a trademark of International Business Machines Corporation.

<:r;i~:;

____________________________~A~D~~~A~N~C~E~IN~F~O~R~M~A~~~IO~N
82C452 CHIPS Super VGA

•

Fully IBMT" VGA Compatible at hardware,
register and BIOS level.

•

Dual Bus Architecture. Integrated interface
to PC-Bus and Microchannel (CHIPS/250
and CHIPS/280).

•

Single Chip Solution.

•

Proprietary High Speed Interface to
CHIPS/250 and CHIPS/280 Systems.

•

Supports 8 and 16 bit CPU interface.

•

Graphics Cursor with transparency.

•

Resolutions up to 640*480 in 256 colors,
960*720 in 16 colors and 1280*960 in 4
colors

•

Enhanced backward compatibility with
EGA, CGA, HerculesT", MDA without using
NMI.

•

Intelligent memory cycle arbitration to
maximize CPU bandwidth.

•

Pinout compatible with 82C451. Same
board design can use both parts.

•

New Patented Write Mode to speed up
graphics text.

CPU Interface
82C452 has a strap option to select the PCBus Interface or the Microchannel Interface.
All control signals for both the interfaces are
integrated on the single chip.

If the 16 bit interface is selected, then software
can still execute 8 bit cycles. This ensures
compatibility with old software.

All I/O cycles are completed without wait
states. Memory cycles are arbitrated using an
intelligent algorithm and is completed in the
fastest possible time.

82C452 supports both 8 and 16 bit CPU interface. The 16 bit interface can be independently
enabled/disabled for memory and I/O cycles.
On reset, the chip is configured for 8 bit
cycles. The 16 bit interface for I/O cycles is
restricted to the index/data pair of registers.
This includes the Sequencer, Graphics Controller, CRT Controller and the Attribute Controller. All other registers are always treated
as 8 bit ports.

ADDRESSI
DATA MULTI·
I-PLEXER

BIOS ROM Interface
In the PC-BUS Interface, the 82C452 supports
an external BIOS ROM. The ROM address is
decoded and the ROMCS pin is asserted to
enable ROM data to the CPU.

82C452
EXTERNAL CPU-l ATTRIBUTE
INTERFACE
CONTROLLER
MEMORY GRAPHICS CRT CON.
CONTROLLER CONTROL· TROLLER
(SEQUENCER)
LER

rTlI

PALETTE
DAC

~ ANALOG
VIDEO
DIGITAL
VIDEO

I
DRAM

82C452 System Diagram

1/88 REV 0

CHIPS ___________________________
Display Memory Interface

colors (both planar and packed pixel mode).

The 82C452 supports a high speed page mode
DRAM interface. This along with the 16 bit data
path and intelligent CPU arbitration, can improve CPU performance by upto 8 times.

Extended Registers

The 82C452 supports 256 KB, 512 KB and 1
MB of display memory as follows:
8 devices 64k*4
16 devices 64k*4
8 devices 256k*4

256KB
512KB
1MB

The entire display memory (256 Kbytes, 512
Kbytes or 1 Mbyte) is always available to the
CPU in regular 4 plane mode, chained 2
plane mode and in super chained 1 plane
mode.
The display memory control signals are derived from an independent clock (MCLK). For
120ns DRAMs, the MCLK frequency should
be in the range of 30-33 MHz. This can support a 50 MHz (4 bits/pixel) video data stream.
With 100ns DRAMs, the MCLK frequency can
be upto 35-36 MHz. At this frequency, the
average number of wait states for the CPU is
reduced resulting in higher performance.

Display Modes and Resolution
82C452 supports a superset of all VGA display
modes. The maximum display bandwidth is
200 Mbits/s - 25 MHz at 8 bit/pixel or 50 MHz
at 4 bit/pixel. This translates to resolutions up
to 640*480 in 256 colors (packed pixel mode),
up to 960*720 in 16 colors (both planar and
packed pixel mode) and up to 1280*960 in 4

All functionality of the extended registers in
82C452 are disabled on reset. Before the extended registers can be written into, they
must be enabled by two sets of control bits
(disabled on reset). The Processor Latches
in the Graphics Controller and the Attribute
Flipflop are readable in the extended register
space. No new bits are defined or any of the
unused bits in the regular VGA registers are
used.

Graphics Cursor
82C452 supports a 32 pixel wide and 512
pixel high hardware graphics cursor. The
graphics cursor supports transparency and
can be any arbitrary shape within the outline
box. The hardware cursor is based on the
definition of the graphics pointer in Microsoft
Windows'·. Use of the hardware cursor frees
the CPU of the responsibility of managing
the pointer in any graphics environment like
Windows'· or Presentation Manager, leading
to improved performance of the application
programs.

External PaleHe Interface
The 82C452 supports programming an external
palette DAC by decoding the CPU addresses
and generating the READ and WRITE signals
for the external palette.
The 82C452 is packaged in a 144 pin plastic
flat pack (PFP).

)

CHiPS ______________
82C480 8514/A-COMPATIBLE
GRAPHICS CONTROLLER
•

Fully Compatible with IBM® 8514/A at both
register and software (,Adapter Interface'
or AI) level

•

Runs Windows and Presentation Manager
for the 8514/A without special drivers

•

Single Chip Solution:
Flatpack

•

Integrated MicroChannel and Industry
Standard Architecture (PC Bus) Interfaces

•

Autoconfigurable for 8-bit or 16-bit System
Interface

•

Demultiplexed bus interface resulting in
lower chip count. Total of 9 chips required
for a complete 8514/A implementation
including memory:
1 82C480 Graphics Controller
1 74lS245 Bus Tranceiver
1 RAMDAC
1 lM339 Comparator
4 256Kx4 VRAMs (+4 for 256 colors)
1 82B484 Support Chip
+1 EPROM (optional)

•

Supports both 256K and 1M VRAMs
16
32
4 8
256K 256K 1M 1M
x
x x
640x480x16-color
x
640x480x256-color
x
x x x
x
x x
1024x768x16-color
x
1024x768x256-color
x
x

160-Pin Plastic
•

Hardware Graphics Functions:
- Bit Bit
- Polygon Fill
- Line Draw
- Pattern Fill
- Color Mixing
-Scissoring

•

External palette DAC support for up to 16
million colors (Autoconfigurable for 6-bit or
8-bit RAMDACs)

•

Resolutions supported up to 2540x2048
(either interlaced or non-interlaced)

•

Video rates supported up to 300 MHz
(with ECl external logic)

•

low-Power CMOS process

r----'
EPROM

A23:0

gl-...L";':;;:;;;;"+r-J
~

Control

8
PALRO/, PALWR/, BBITDAC

SENSE
MS2:0
HSYNC, VSYNC

;;;

A1:0

07:0
VP7:0

VPCLK, VBLANKI

External (VGA)Video Connector

82C480 System Block Diagram

\:;;i~:;

_________________________________________
828484
VIDEO SUPPORT CHIP

•

Allows an 8514/A-compatible display
adaptor to be implemented with 9 chips
(including memory):
1
1
1
1
1
4
+1

•

82C480 Graphics Controller
82B484 Video Support Chip
74LS245 Bus Tranceiver
RAMDAC
LM339 Comparator
256Kx4 VRAMs (minimum)
EPROM (optional)

•

Reduces chip count for 82C480 based
8514/A-compatible display adaptors

•

Select up to 4 clock sources

•

Contains VGA Video pass-through circuitry

•

Implements VESA-compatible video pass
through logic

•

Supports video rates to 80 MHz

II High-speed Bi-CMOS process

80-pin Plastic Flat Package

III Pinouts optimized for PCB layout

Overview
Designed to work with the 82C480, the
82B484 Video Support Chip integrates all TTL
components required for 8514/A-compatible
display adaptors_
With the 82B484, a
minimum system 1024x768 non-interlaced
8514/A-compatible display adaptor can be
implemented in 9 chips including VRAM

memory_ Included in the 82B484 is all clock
selection circuitry, video shift registers, and
VGA video pass through logic. The 82B484
CMOS circuitry allows 80 MHz clock
frequencies supporting non-interlaced monitor
resolutions up to 1024x768 and interlaced
monitor resolutions up to 1280x1024.

S407:0 (VP7:0 from VGA)

S4:007

S4:006
S4:00S

:l
~
>

E
!:!

S4:004

-..-

'PSEUOO
a-PLANE
MOOE'
LOGIC

lll-

S-BIT SHIFT REG
S-BIT SHIFT REG
S-BIT SHIFT REG
S-BIT SHIFT REG

S4:003

S-BIT SHIFT REG

S4:002

S-BIT SHIFT REG

S4:001

S-BIT SHIFT REG

S4:000

S-BIT SHIFT REG
l

r-<'
r-<'
r-<'
I"<

r-<'
r-<'
r-<'
l-(

P4
P3
P2
P1

Q
c

~
B

PO
f-PCLK
I-MBLANIC5

__ VBL
ANI

;:,

co
..,.

CHIPS ___________________________
The 82C780 is a single chip hard disk controller for Micro Channel based IBM PS/2T"Compatible personal computers. It consists
of three main blocks, viz. the microchannel
interface block which controls the microchannel arbitration and bus acquisition, the data
manager block which controls the transfer of
data between the local buffer memory and the
host or disk and the formatter block which
controls the disk sequencing process as well
as the interface to the local microprocessor.
When used in conjuction with the 82C784, it

\:rti~!)

__________________________________~P~R~EL~I~M~IN~A_R_Y

82C781 HARD DISK MICRO CHANNEL INTERFACE CHIP
II

Low power advanced 1.5J.L CMOS technology

Provides optional, register-definable
CAR D ID in conjunction with the 82C782.

On-board Micro Channel'· Compatible
Arbitration Logic

Provides synchronous and asynchronous
bus transfer cycle extension

On-board Bus Acquisition Logic

Programmable burst length capability

On-board POS 102 and 103 register

Provides CARD ID read controls

Provides external read decodes for diagnostic registers

Provides programmable address select
capability through the POS 104 and 105
registers

III

58-pin PLCC or 80-pin Flat Pack

Functional Description:
The 82C781 Hard Disk Micro Channel Compatible Interface Chip provides the interface
between the Micro Channel bus and the hard
disk controller or other DMA/IO slave-oriented
peripherals.
When used in a hard disk mode, it works in
conjunction with the 82C782 Hard Disk Data
Manager Chip to facilitate bus acquisition and
DMA transfers. It also decodes the bus addresses and status (M/IO, 80, 81) for I/O slave
reads. When used in the general purpose
mode, it will work in conjunction with other

DMA or I/O slave peripherals (as long as the
handshake requirements are met) to provide
the Micro Channel interface functions.
Together with the 82C782, a disk formatter and
a data separator/endec,the 82C781 provides a
very cost-effective and high-performance implementation of the Fixed Disk Adapter for
systems compatible to the PS/2 environment.
On the other hand, the 82C781 provides the
Micro Channel interface for other DMAIIO
slave oriented peripheral adapters, thus allowing the designer to concentrate on the main
task of adapter design.

XDO-7 (HOST DATA)

-BURST

-PREMPT

BURST
LOGIC
&
CNTR

BRST<4:7>

t---r

POS 102

IDMACONTRO L

POS 103

IARB & BURST

I
~

ARBO-3

.. PREMPT ••
..
•
ARBfGNT

DACK
DMAREQ

ARB
LOGIC
& DMA
STATE
M/C

CDCHRDY

L-f

110 RELOC-L

POS 104

<7:0>
<11:8>

POS 105

1/0 RELOC-U & MASK

ARBID<3:0>
AO-15

I
r

RAO-11
ADDRESS
DECODE

CHRDY
STATE MIC

CDSFDBK

I .. CDSFDBK
DTRDT(P)

Figure 1. 82C781 Block Diagram

c:ttl~!i

________________________________________

~P~R~E~L~IM~IN~A~R~Y

82C782 HARD DISK DATA MANAGER
•

Low power advanced 1.Sp CMOS technology

•

PS/2'· Model SO/60-compatible

•

On-board register file for command and
status

•

Slave DMA controller, max 2.S MBytes/s
to the host

•

8-/16-but data pipeline to sustain high
bus transfer rates

•

On-board address generation for local
buffer

•

Provides address generation during local
CPU buffer accesses, with optional autoincrement capabilities

Functional Description:

•

Addresses up to 64K of static RAM

•

Supports both 87S1 and 68HC11
microcontroller families

•

Provides interrupt to the local CPU

•

Supports Adaptec AIC-011 and compatible formatters

•

Supports 1:1 inter/eave

•

Supports STS06 type drives

•

84-pin PLCC package

The 82C782 Hard Disk Data Manager Chip
provides the DMA, buffer management and
register file functions for the Fixed Disk Adapter in the PS/2-Micro Channel'· environment.
The slave DMA controller is responsible for
RAO .15
AOO·7
HOST DATA BUS

i
ATTENTION
STATUS

~
DACK.

1 II

~~
~

DISK PTR

D--

SKClK.
D-SKREQ.

STOP

1co

CONTROL

BUFFER
MANAGER

I--

HOSTPTR

.,.!!Q:L
ClK

INTR STATUS

CONTROL

FIFO
& DATA
ALIGNER

HOST DMA
MACHINE

WR BYTECTR

'--

ADAPTER ID
RDATAO·7 (FROM RAM)

Figure 1. 82C782 Block Diagram

'::i-il~::;

____________________________________________________________

C:tti~!i

_______________________________________

P_R~E~L~IM~I~N~A~R~Y

82C784 MFM/RLL DATA SEPARATOR & ENDEC
•

Low Power advanced 1.5#1 CMOS
technology

•

Onboard 5 Mblts/s MFM{1,3) encoder/
decoder

•

Onboard 7.5 Mbits/s RLL{2,7) encoder/
decoder

•

Synchronous start-up Phase-Locked Oscillator (PLO)

•

MFM Write Precompensation with built in
delay line

•

Onboard Address Mark Detection circuitry

•

Provides NRZ interface to the disk controller chip

•

Dedicated Analog Vcc/Gnd for better noise
immunity

•

Onboard 48 mA drivers/receivers for disk
data lines

•

Single +5Voperation (Digital & Analog)

•

44 pin PLCC package

De-glitched Read/Reference Clock output

The 82C784 provides the Data Separation
function and a user selectable MFM or 2,7RLL
encode/decode function, for the Disk Data
Path. When used in conjunction with the
Xl
X2

==1

REFCLK
GENR

82C780, it results in the implementation of a
low cost Fixed Disk Adapter for the PS/2-'·
Micro Channel'· Compatible environment and
greatly reduces board space, while enhancing
the performance.

~WCLK
MFM

MFM/2,7

.......

ENCODER

EN DATA
WCLK

AMGENR

PCEN

PRECOMP
DELAY
GENR

MUX
&
DIFF
DRVRS
EN

27DATAr

r-----

WDATA1+

f----'WDATA1-

r---'WDATA2+
f---- WDATA2-

RLLlMFM
DRVSEL 1,2

1~=-

ILAM DETECT
I

NRZ
RD/REFCLK

TPO
TPl

MFM/2,7
DECODER

I.
1

t
PHASE
DETECT
&
CONTROL
LOGIC

DLYDATA

VCOCLK

PLO

11111
Figure 1. 82C784 Block Diagram

SYNC
DETECTOR
&
DIFF
RCVRS

RGATE

RDATA1+
RDATA1-

~ RDATA2+
~ RDATA2-

CHiPS _____________________________
The 82C784 boasts of a high level of integration
by supporting both the MFM & RLL encode/
decode schemes. along with the synchronous
start-up Phase Locked Oscillator and the dif-

ferential driver/receiver pairs for the disk data
path signals. The advanced architecture also
results in the use of a minimum number of
passive components.

\:r;i~!i

______________________________________~P~R~E~L'~M~'~N~A~R~Y
OC8233PEAK/386 AT-Compatible BIOS
T

•

Fully compatible with the IBM Ar· BIOS

•

Developed using Clean-Room Methodology

•

Optimized for performance with the
CS8233 PEAK/38S CHIPSetT•

•

Includes Keyboard Controller BIOS

Easy customization of key BIOS
parameters

•

Supports CPU speeds up to 40 MHz

•

Built-In Development/Debug Support

•

SETUP embedded in BIOS

•

Total Hardware/Software Support

•

Built-in support for CHIPS Multifunction
Controllers

Overview

Setup and usage of cache options

The OC8233 PEAK/386 Basic Input/Output
System (BIOS) is an enhanced, high performance product that is used with the CS8233
PEAK/386 CHIPSet to provide an integrated
hardware and software solution. The BIOS is
fully compatible with the IBM AT BIOS. It
provides all of the standard features, including
support for:

Embedded SETUP program for machine
configuration

Moving BIOS to shadow RAM to improve
performance

Dynamic memory sizing

80386 processor and 80387 math
coprocessor operating at clock speeds
from 20 MHz to 40 MHz

84, 101, or 102 key keyboards

High and lowcapacityS.2S-inch or3.S-inch
diskette drives

Monochrome and CGA video adapters

Power-on self test diagnostics

BIOS Extensions
The BIOS utilizes the extended capabilities of
the CS8233 CHIPSet to provide the user with
enhanced functionality and beUer performance. The BIOS is also designed to be customized by the OEM and to be easily used in
the development/debug process. The additional functions include support for:
-

32 bit memory operations

82C206 Integrated Peripheral Controller

82C601, 82C604, and 82C60S Multifunction
Controllers

Complete BIOS Solution
The OC8233 BIOS is available in two forms to
best meet the needs of the OEM. The SK8233
BIOS Software Kit provides a productionready master copy of the system BIOS, a keyboard controller BIOS, and utility programs to
customize the BIOS and support the development/debug process.
The SC8233 BIOS Source Kit provides the
source code and documentation for the system and Keyboard Controller BIOS, as well as
all support utilities.
All CHIPS BIOS products are designed to be
customized to meet OEM requirements. A
BIOS modification utility program is provided
in both the software and source kit. It allows
many common modifications of BIOS and
CHIPSet configuration parameters, including
the fixed disk table, the default CMOS values,
and the sign-on message. This provides a
method for an OEM to customize the BIOS
without requiring access to the source code.
The consistent, modular structure of CHIPS'
BIOS products allows creation of additional
modules to support custom applications.
Once a module is developed, it can be in-

\:i1ifi:i __________________________________________
tegrated into the BIOS with minimal effort.
CHIPS also provides in-house customization
services.
CHIPS system BIOS products are designed
with built-in support to aid in the development/debug process. The BIOS is designed
to allow the CHIPSet registers to be loaded
from saved information during power-up. The
registers and their values that will be loaded
can be controlled by a program that is included in the software kit.

Total Hardware/Software Support
CHIPS offers complete hardware and
software support for customers using the
CS8233 CHIPSet with the BIOS. The CHIPSet
together with the BIOS have been extensively
tested for quality, reliability and compatibility.
CHIPS has an in-house compatibility test

department that tests all CHIPS BIOS
products using industry standard software
and hardware. CHIPS has a technical support
staff available to assist in resolving any
hardware or software problems that may arise.

Ordering Information
OC8233 PEAK/386 BIOS (Label)
CB8233 CS8233 PEAK/386 CHIPSet with
OC8233 BIOS (Label)
SK8233

PEAK/386 BIOS Software Kit

SC8233 PEAK/386 BIOS Source Code Kit

CHIPS BIOS products are licensed on a per
copy royalty basis. A CHIPS BIOS Object
Code or Source Code license must be signed
and returned before ordering a CHIPS BIOS
product. A software kit or source kit can then
be ordered to obtain a master copy of the
BIOS. For each BIOS ordered, the OEM
receives an EPROM label and is entitled to
make one copy of the BIOS from the master.
To obtain further information contact your
local Chips and Technologies, Inc. sales representative.

CHiPS _________________________

LAPTOP CHIPSet SOLUTIONS

<:tti~!i

________________________________________~P~R~E~L~IM~IN~A~R~Y~

CS8223/CS8283 LeAPset™ LAPTOP SUPPORT CIRCUITS
•

Part of a complete laptop solution from
Chips and Technologies

•

Optimized power conservation

Full support for EMS 4.0

•

High-performance, low-power memory
controller

Sleep mode for short intervals of
power reduction

Stand-by mode for maximum power
savings

Support for slow refresh DRAMs
Software selectable operating
frequency
Auto-power off for display backlight
Power-on at user request, after a
programmable interval or in response
to a modem ring

•

100% PC/AT™-compatible

•

Supports both the '286/,C286 and the
'386SX

•

Multiple speeds: 12, 16 and 20MHz

•

Optimizations for OS/2 T•

The LeAPset package of integrated circuits is
the first complete solution for full-function
battery-powered portable computers. All of
the CPU and AT bus control functions,
memory control logic, VGA graphics,
peripheral support and special laptop features
are integrated into 6 CMOS flat-pack devices.
LeAPset CS8223 supports the 80286 and the
802C286 while LeAPset-sx CS8283 supports
the 80386SX. Both work together with the
82C601 Multifunction Controller, the 82C455
Flat Panel/CRT VGA Controller and the
82C456 Advanced Flat Panel/CRT Controller.
Using the LeAPset solution, a complete laptop
motherboard requires a total of only 29 ICs
plus memory.
Four chips are included in the LeAPset system
controller circuits: the 82C242 data/address
buffers and bus conversion logic, the 82C636
Power Control Unit (PCU) and the 82C206
Integrated Peripheral Controller (IPC) and the

Page interleaving increases
performance
Slow access DRAMs reduce costs
Slow refresh DRAMs reduce power
consumption

•

Backward-compatible with NEAr·
CHIPSet T•

•

Compatible with other members of
CHIPS'Iaptop solutions
-

•
-

82C455 Flat Panel/CRT VGA
Controller
82C456 Advanced Flat Panel/CRT
Controller
83C601 Multifunction Controller
Convenience features
Security password support
ROM/RAM card

appropriate CPU/bus/memory controller. The
82C241 is the CPU controller used with the
'286 and contained in the CS8223. The 82C841
is the CPU controller used with the '386SX
and contained in the CS8283.

Power Saving Features
Both CHIPSets support features tailored for
laptops, such as power conservation features
to increase battery life. Such features include
sleep mode, stand-by mode and automatic
shut-off for power-hungry devices.
In sleep mode, clocks to static devices (such
as the 'C286) are shut off. Clock to dynamic
devices (such as the '386SX) are reduced to the
1/2, 1/4 or 1/8 of normal operating frequency.
In stand-by mode, all devices except DRAM
and memory controller chips are powered off;
DRAM chips are refreshed. The state of the
machine, including the display buffer, can be
saved in battery-backed slow refresh DRAMs.
After the user strikes the power switch, a

CH.PS ________________

80C286
80286
80386-SX

Figure 1. CS8223/CS8283 Block Diagram

C:r;i~:;

_______________________________________________

programmed interval or the telephone lines to
the modem ring, power is turned back on, state
is restored and the application can be resumed
where it was left off.
Power-hungry subsystems such as the display
backlight can be automatically shut off. For
example, ifthe user does not strike a key within
a programmed interval, the LeAPset PCU
will automatically turn off power to the backlight. If the power has been shut off, power is
restored as soon as the user strikes any key.

Board Space
When using the LeAPset system, the designer
can take advantage of several features to help
reduce space on the main system board. For
example, both system and VGA BIOS can be
squeezed into a single 128 kilobyte EPROM. In
addition there are several programmable
decoders that can be used to replace external
SSI for decoding addresses to subsystems on
the motherboard. All LeAPset circuits are
packaged in space-saving surface mount flat
packs.

Performance Features
The LeAPset circuits are backward-compatible with the NEAT CHIPSet CS8221; all

LeAPset internal registers are a superset of
NEAT registers. As a result, all of the performance features that have been designed into
the NEAT CHIPSet are available for laptops.
These features include optimization for OS/2,
2-way and 4-way page interleaving, shadow
RAM and software-selectable command
delays, wait states and memory organizations,
and 4 on-chip EMS page registers.

Complete Solutions
Because optimum designs must take into account system-wide issues, CHIPS offers complementary integrated circuits and services.
The 82C455 VGA Flat Panel/CRT Controller
and the 82C456 Advanced VGA Flat
Panel/CRT Controller drive LCD, gas plasma,
electroluminescent displays as well as CRTs.
Both provide 100% compatibility with IBM
VGA along with intelligent color to gray scale
conversion and power save modes. The
82C601 Single Chip Peripheral Controller is
also 100% IBM compatible and contains 2
UARTs, one bi-directional parallel port and an
IDE hard disk interface. In addition, CHIPS
offers ready-made BIOS as well as software
and hardware design services.

<:rtl~!i

____________________________A_D_VA_N_C_E__IN_F_O_R_M_AT_I__ON

82C100
IBMT. PS/2 Model 30 and Super XTT. Compatible Chip
•

100% PCIXT compatible

•

Build IBM PS/2 • Model 30 with XT software compatibility

Key superset features: EMS control, dual
clock, and power management

III

Bus Interface compatible with 8086, 80C86,
V30, 8088, 80C88, V20

Complete system requires 12 ICs plus
memory

•

10 MHz Zero wait state operation

•

Applicable for high performance Desktop
PCs, Laptop PCs and CMOS Industrial
Control Applications

•

Single chip implementation available in
100-pin flat pack

•
•

Includes all PC/XT functional units compatible with:
8284, 8288, 8237, 8259, 8254, 8255, DRAM
control, SRAM control, Keyboard control,
Parity Generation and Configuration registers

1/0 CHANNEL

8086/8088

SERIAL PORT

V30N20
CPU

MOUSE HOOK·UP

BI-DIRECTIONAL
PARALLEL PORT

Super XT Model 30 Compatible System

\:rti~!i

_____________________________________________

The 82C100 supports most of the peripheral
functions on the PS/2 Model 30 planar board:
8284 compatible clock generator with the
option of 2 independent oscillators, 8288
compatible bus controller, 8237 compatible
DMA controller, 8259 compatible interrupt
controller, 8254 compatible timer/counter,
8255 compatible peripheral 1/0 port, XT Keyboard interface, Parity Generation and Checking for DRAM memory and memory controller
for DRAM and SRAM memory sUb-systems.
The 82C100 enables the user to add PS/2
Model 30 superset functionality on the planar
board: dual clock with synchronized switching
between the two clocks, built-in Lotus-IntelMicrosoft T• (LIM) EMS support for up to
2.5 Megabytes of DRAM and power management features for SLEEP mode as well as
SUSPEND/RESUME operations. The SLEEP
and SUSPEND/RESUME features help in

CHiPS _______________________________
82C230
High Performance Model 30 Compatible CHIPSet™
• 100% IBM Model 30 (8086) Compatible,
but uses the 80286 CPU for increased
performance.

• Supports 8 or 16 bit 82C451 VGA interfaces.
• Supports 82C601 Multi-Function Peripheral
Chip .

• Single chip includes:

• Has flexible bus timing to solve adapter
compatibility problems.

CPU Support Logic
Memory Controller w/ EMS
Keyboard and Mouse Ports
Bus Interface/Conversion Logic
8237, 8254, 8255, 8259 Equivalents
Numeric Processor Interface
Peripheral Chip Selects
iii

Supports up to 8 Megabytes of Memory with
EMS and Shadow RAM capabilities.

£!

Supports CPU speeds of 8, 10, 12.5,
16 and 20 MHz

• Supports either 8 or 16 bit ROMs for space
and cost savings.
• High level of integration allows a Model 30
footprint without the need to surface mount
all components.
II

Single chip implementation in 144 Pin
Flat Pack.

r
80286

A19-o

CPU

82C230
SYSTEM

CONTROLLER

80287
NPX

82C451

vc.
CONTROLLER

MODEL 30 SYSTEM BLOCK DIAGRAM
10/88 REV. 0

'tiIPS ____~-----------The 82C230 is a single chip that contains most of the core logic required to support the system logic functions
required to build a 100% IBM Model 30 (8086) Compatible computer, but based on the higher performance
80286 processor. This allows the OEM to offer a compatible solution for the low end of the marketplace that
out-performs the offerings from IBM or compatibles based on the 8086 CPU.
The 82C230 contains CPU control logic including clocks, a DRAM controller that supports up to 8 megabytes
of memory with EMS and Shadow RAM capabilities, 8259, 8237, 8254 and 8255 equivalents, refresh controller,
expansion bus interface, keyboard and mouse interfaces, numeric processor interface, and peripheral chip
selects for floppy and hard disks, real-time-clock, video, serial and parallel ports.
The 82C230 can be combined with the 82C601 multi-function peripheral chip and the 82C451 VGA chip to
build a complete Model 30 compatible motherboard that offers superior performance with much higher integration.
The 82C230 can support the 82C451 on the 8-bit system bus, or on the 16 bit local bus for higher performance.
The 82C230 DRAM controller can support zero wait state designs at CPU speeds of 12.5 MHz using 80 ns
DRAM, or 16 MHz with 60 ns DRAM. Wait states can be inserted so that lower speed DRAMs may be used
with high speed processors.
The 82C230 memory controller supports up to 8 megabytes of DRAM. The CPU can access this memory
directly or through an EMS 4.0 compatible register set. BIOS ROM support is provided for both 8 and 16 bit
wide data paths. Since Shadow RAM is also supported, an OEM can choose to save board space and costs
by using a single 8 bit ROM and copying it to shadow RAM for fast execution.
For today's low-end machines, which must have performance levels greater than yesterday's high-end machines,
the 82C230 is the clear choice.

C:iii~:;

_______________________________

PR_E_L1_M_IN_AR_Y

82C455 VGA FLAT PANEUCRT CONTROLLER DATA SHEET
•

VGA-Compatible flat panel controller optimized for laptop computer applications.

III Up to 40 MHz dot clock speed for graphics and
text modes.

III Supports CRT, LCO, Plasma and ElectroLuminescent displays of varying resolutions.

I\lI Can utilize an external palette OAC with up to
16 million colors.

• Single chip implementation tightly couples to
theCHIPSl250 and CHIPS/280 and interfaces
with 8 and 16 bit PC bus and MCA (an interface compatible with the MicroChanneI™).

•

The 82C455 Graphics Controller provides a
complete solution for implementing a Video
Graphics Array-compatible controller. The
82C455 is supplied in a 144-pin PFP package. It
can be used in 8 and 16-bit PC bus and in 16-bit
MCA bus environments.

tive solution for PS/2 compatible systems. When
used with one of these CHIPSets®, the 82C455
can execute FAST memory cycles at a speed
greater than that normally available on the MCA
bus.

Display Types Supported

The 82C455 is compatible with IBM's EGA, CGA
and MDA, in addition to offering a Hercules
monochrome-graphics-compatible mode. Onchip compensation registers permit software
designed for low resolution displays to utilize the
entire screen area on a flat panel with higher
resolution.

CGA, EGA, MOA, Multifrequency, IBM PSI2™
and other monitors can be used. The choice of
flat panel displays includes EL, plasma, as well
as single panel/single drive, dual panel/single
drive and dual panel/double drive LCOs. Both
gray scale and monochrome panels are supported; a proprietary frame rate control algorithm
provides gray scale capability on monochrome
panels.

CHIPS/250 and CHIPS/280 Interface
The 82C455 interfaces directly to the CHIPS/250
and CHIPS/280, providing a simple, cost-effec-

Provides intelligent backward compatibility to
the EGA, CGA, Hercules™, and MDA on Flat
Panel displays.

Backward Compatibility

Hardware Support for Context
Switching
Multitasking and windowing environments can
be implemented easily since all internal registers
of the 82C455 can be read and written.

DATA

CRT

82C455
TO

ADDRESS

FLAT
PANEL

MEMpRY

Figure 1: 82C455 System Implementation

CHiPS ----------------------------------82C455 Functional Description

Graphics Controller

The 82C455 offers a complete solution for implementing a VGNMCGNEGNCGAlMDNHercules-compatible display system. By integrating
all necessary logic the device ensures that total
chip count for a VGA-compatible solution can be
as low as 14 chips (includes 82C455, display
memory, buffers and drivers).

The Graphics Controller interfaces the 8 or 16bit CPU data bus to the 32-bit data bus used by
the four planes (Maps) of display memory. It also
latches and supplies to the Attribute Controller
display memory data for use in refreshing the
screen image. For text modes this data is supplied in parallel form (character generator data
and an attribute code); for graphics modes it is
converted to serial form (one bitfrom each of four
bytes form a single pixel). The Graphics Controller also performs anyone of several types of logical operations on data while reading it from or
writing it to display memory or the CPU data bus.

Anyone of a variety of CRT monitors or flat panel
displays can be driven. Internal compensation
registers ensure that industry-standard software
designed for different displays can be executed
on the single flat panel used in an implementation. Mode initialization is supported at the BIOS
and register levels, ensuring compatibility with all
application software. The 256 Kbytes of display
memory size is comprised of 8 64K'4 DRAMs.
Display memory refresh is controlled by the
82C455; it is transparent to the CPU.
For support of multitasking environments and
context switching, the entire state of the 82C455
(internal registers and latches) is readable and
writeable. This feature is 100% compatible to
IBM'sVGA.
The 82C455 directly interfaces to 8-bit PC and
PC/XT, 16-bit PCIAT and 8 or 16-bit MCA buses.
All operations necessary to ensure proper operation in these various environments are handled
in a fashion transparent to the CPU. These include internal decoding of all memory and 1/0 addresses, bus width translations and generation
of the necessary control signals.
The 82C455 contains 16 color palette registers.
It also interfaces directly to an external Inmos
G171 (or compatible} color palette and DIA converter. Like the VGA, it is capable of display
resolutions of 640'480 with 16 on-screen colors
(internal palette) and 320*200 with 256 onscreen colors from an external palette of 256
thousand (or 16 million) colors. The 82C455 can
also be programmed for higher resolutions up to
800'600 in 16 colors.
The 82C455 integrates four different modules as
follows:

Sequencer
The Sequencer generates all CPU and display
memory timing signals. It controls CPU access
of display memory by inserting cycles dedicated
to CPU access and contains mask registers
which can prevent writes of individual display
memory planes.

Attribute Controller
The Attribute Controller generates the 4-bit-wide
video data stream used to refresh the display.
This is created in text modes from a font pattern
and an attribute code which pass through a
parallel to serial conversion. In graphics modes,
the display memory contains the 4-bit pixel data.
In text and graphic modes the 4-bit pixel data
acts as an index into a set of internal palette
registers which generate a 6-bit stream. Two additional bits of color data are added if 256-color
mode is enabled. Text blink, underline and cursor are also the responsibility of the Attribute
Controller.

CRT Controller
The CRT Controller generates all the sync and
timing signals for the display and also generates
the multiplexed row and column addresses used
for both display refresh and CPU access of display memory.

<:rti~:;

________________________________PR_E_L_IM_IN_A_R_Y
82C605/82C606

CHIPSpak/CHIPSport MULTIFUNCTION CONTROLLERS
•

100% Compatible to IBM T " PC, XT and
AT

•

Fully compatible to the NS16450 Asynchronous Communications Element, and the
Motorola T " 146818A Real Time Clock
(82C606 only)

•

Provides a parallel interface which can
be configured for use with either a printer
or a scanner
Provides two UART channels which can
be powered from external sources

•

Support for a game port

•

Provides a Real Time Clock with 100
year calendar (82C606 only)

I!I

CMOS Configuration RAM with Battery
Backup support permits software selection of internal register base addresses
(82C606 only)

114 bytes of CMOS RAM

iii!

Single chip 68-pin CMOS implementation

' - - - - - - - - - - - _ GAME ENABLES

Figure 1. 82CSOS/SOS CHIPSpak/CHIPSport Multifunction Controller Block Diagram

c:t;ifi:; _____________________________________P~R~E~L~I~M~IN~A~R~Y
OC8223
LEAPSet™'LEAPSetsxTM AT.Compatible BIOS
•

Fully compatible with the IBM ATTM BIOS

•

Includes AT Keyboard Controller BIOS

•

Optimized for the CS8223 LEAPSet and
CS8283 LEAPSetsx

•

Built-in Support for CHIPS Multifunction
Controllers

•

Suspend/Resume Mode

•

Sleep Mode and Smart Sleep Mode

Developed using Clean-Room Methodology

•

Clock Speed Selection

•

Easy customization of key BIOS
parameters

•

Automatic Screen Blanking

•

Built-In Development/Debug Support

•

Pop-Up Laptop Set-Up Window and Embedded System Set-Up

•

Total Hardware/Software Support

Overview
The OC8223 LEAPSetiLEAPSetsx BIOS is an
enhanced, high performance BIOS that is
used with the CS8223 LEAPSet or CS8283
LEAPSetsx to provide an integrated hardware
and software solution for Laptop computers.
The BIOS is fully compatible with the IBM AT
BIOS, is optimized to utilize the extended
capabilities of LEAPSet and LEAPSetsx and
provides several extended features, including
Smart Sleep Mode. The BIOS is also designed
to be easily customized by the OEM and to be
easily used in the developmentldebug
process.

BIOS Extensions
The Laptop features of LEAPSet and LEAPSetsx supported by the BIOS include
Suspend/Resume Mode, Sleep Mode, clock
speed selection and automatic screen blanking. A pop-up window and hot-keys are
provided for the user to set-up, enter and exit
these modes.
Suspend/Resume Mode places the system in
an ultra low power mode of operation that
appears as ifthe system is turned off. Suspend
is entered by turning power off, pressing a
hot-key or by calling a BIOS function from an
application. Resume to normal operation is
performed by turning the power switch on.
Sleep Mode puts the system in a low power
mode of operation that appears as if the sys-

tem is operating normally. Sleep Mode is
entered automatically whenever the BIOS is
idle, such as waiting for a key to be pressed, or
when selected by the user. The system will
wake up when the BIOS is no longer idle or
when the user presses a key.
The screen is automatically blanked and shut
off to conserve power after a user-specified
time of keyboard inactivity. The time is
specified by the user in the pop-up window.
The BIOS supports Smart Sleep Mode to allow
a Laptop computer to operate with an even
longer battery life. Smart Sleep Mode automatically detects when an application is idle
and puts the system to sleep until the application is no longer idle.
The extended AT-Compatible features contained in the OC8223 BIOS include an embedded set-up, dynamic memory sizing,
shadow RAM support, EMS register initialization and support for other CHIPS multifunction controllers. The set-up capability allows
the system configuration to be set up without
the need for an external set-up program.
Dynamic memory sizing automatically initializes the system for the type and amount of
memory used. The Shadow RAM support
feature moves the BIOS into RAM atthe same
location as the BIOS ROM to improve BIOS
operation speed. The CHIPS multifunction
controllers suported by the BIOS include the
82C601, 82C605 and 82C710.

CHiPS _____________________________
Complete BIOS Solution
The SK8223 BIOS Software Kit provides a
production-ready master copy of the OC8223
BIOS, a production-ready master copy of the
AT keyboard controller BIOS, and utility
programs to customize the BIOS and to support the development/debug process. The
SC8223 BIOS Source Kit provides the source
code for the BIOS and keyboard controller
BIOS and all of the contents of the SK8223.
All CHIPS BIOS products are designed to be
customized to meet OEM requirements. A
BIOS modification utility program allows
modifications of BIOS and CHIPSet'· configuration parameters, including the fixed disk
table, the default Laptop and system set-up
values, and the sign-on message. This
provides a method for an OEM to customize
the BIOS without requiring access to the
source code.
The consistent, modular structure of CHIPS'
BIOS products allows creation of additional
modules by a source code OEM to support
custom applications. Once a module is
developed, it can be integrated into the BIOS
with minimal effort. CHIPS also provides inhouse customization services.
CHIPS system BIOS products are designed
with built-in support to aid the development/debug process. The BIOS is designed
to allow the CHIPSet registers to be loaded
from battery backed-up memory on power-up.
A utility program is provided to edit which
registers are to be loaded and the values that
are to be loaded.
The BIOS was developed using a clean-room
methodology that helps ensure CHIPS BIOS
products do not infringe on any applicable
copyrights. The methodology used is well
documented and is available for review.

Total Hardware/Software Support
CHIPS offers complete hardware and
software support for customers using the
CS8223 LEAPSet or CS8283 LEAPSetsx with
the OC8223 BIOS. The CHIPSet together with
the BIOS have been extensively tested for

quality, reliability and compatibility. CHIPS
has an in-house compatibility test department
that tests all CHIPS BIOS products using industry standard software and hardware.
CHIPS has a technical support staff available
to assist in resolving any hardware or software
problems that may arise.

Ordering Information
OC8223 LEAPSetiLEAPSetsx BIOS (Label)
CB8223 CS8223 LEAPSet with OC8223
BIOS (Label)
CB8283 CS8283 LEAPSetsx with OC8223
BIOS (Label)
SK8223

LEAPSet/LEAPSetsx BIOS
Software Kit

SC8223 LEAPSetiLEAPSetsx BIOS
Source Code Kit
CHIPS BIOS products are licensed on a per
copy royalty basis. A CHIPS BIOS Object
Code or Source Code license must be signed
and returned before ordering a CHIPS BIOS
product. A software kit or source kit can then
be ordered to obtain a master copy of the
BIOS. For each BIOS ordered, the OEM
receives an EPROM label and is entitled to
make one copy of the BIOS from the master.
To obtain further information contact Chips
and Technologies, Inc. or your local sales representative.

C:;;i~!i

_________________________________________________________

CHIPS Regional Sales Offices
UNITED STATES
California, Irvine
Chips & Technologies, Inc.

714-852-8721
California, San Jose
Chips & Technologies, Inc.

408-437-8877
Georgia, Norcross
Chips & Technologies, Inc.

404-662-5098

Illinois, Itasca
Chips & Technologies, Inc.

312-250-0075
Massachusetts, Burlington
Chips & Technologies, Inc.

617-273-3500
Pennsylvania, Blue Bell
Chips & Technologies, Inc.

215-540-2214
Texas, Dallas
Chips & Technologies, Inc.

214-702-9856

INTERNATIONAL
Germany, Munich
Chips & Technologies, Inc.

4989-463-074
Korea, Seoul
Chips & Technologies, Inc.

82-2-558-5559
Taiwan, R.O.C.
Taipei
Chips & Technologies, Inc.

8862-717-5595

Chips and Technologies, Inc.
3050 Zanker Road, San Jose, CA 95134 408-434-0600 telex 272929 CHIPS UR
CHIPSet. CHIPSpak. CHIPSterm. CHIPS/250. CHIPS/280. LeAPset. LeAPsetsx. MicroCHIPS. NEAT, NEATsx, PEAKsetl386,
PEAKsetl486 and SCAT are trademarks of Chips and Technologies, Inc.
CHIPS is a registered trademark of Chips and Technologies, Inc.
IBM, 8514/A, AT, XT, Color Graphics Adapter, Enhanced Graphics Adapter, Micro Channel, PS/2, Personal System/2 are
trademarks of International BUSiness Machines.
Centronics is a trademark of Centronics

Copyright 1989 Chips and Technologies, Inc.
These datasheets are provided for the general Information of the customer. Chips and Technologies, Inc. reserves the right to
modify these parameters as necessary and customer should ensure that it has the most recent revision of the data sheet. Chips
makes no warranty for the use of its products and bears no responsibility for any errors which may appear in this document. The

customer should be on notice that the field of personal computers is the subject of many patents held by different parties.
Customers should ensure that they take appropriate actions so that their use of the products does not infringe upon any patents.
It is the policy of Chips and Technologies, Inc. to respect the valid patent rights of third parties and not to infringe upon or assist
others to Infringe upon such rights.

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:07:04 18:50:51-08:00
Modify Date                     : 2017:07:04 19:34:28-07:00
Metadata Date                   : 2017:07:04 19:34:28-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:7c74d69d-5170-fd4e-bd37-5825674ce40a
Instance ID                     : uuid:354473b7-04b7-3344-8115-1b5c04295f40
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 102

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