1989_Cypress_Bi CMOS_CMOS_Data_Book 1989 Cypress Bi CMOS Data Book

User Manual: 1989_Cypress_BiCMOS_CMOS_Data_Book

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Cypress Semiconductor is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor, 3901 North First St., San Jose, CA 95134 (408) 943-2600
Telex: 821032 CYPRESS SNJ UD, TWX: 910 997 0753, FAX: (408) 943-2741

How To Use This Book
This book has been organized by product type, beginning
with Product Information. The products then follow, beginning with SRAMs, then PROMs, EPLDs, LOGIC
(FIFO products are included in this section), RISC, Modules, and ECL. A section containing military information
is next, followed by the BridgeMOSTM product family, the
Cypress programming board, QuickPro, and Cypress' programmable logic design tool, the PLD ToolKit. Wit/tin
each section, data sheets are arranged in order of part riumber. Quality and Reliability aspects follow next, then Application Briefs, and finally Thermal Data and Packages.

A Numeric Device Index is included after the Table of
Contents that identifies products by numeric order, rather
than by device type. To further help you in identifying
parts, a Product Line Cross Reference is in the Product
Information section. It can be used to find the Cypress part
number that is comparable to another manufacturer's part
number.

Published February I, 1989
BridgeMOSTM is a trademark of Cypress Semiconductor Corporation.
@) Cypress Semiconductor Corporation, 1989. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation
assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey
or imply any license under patent or other rights. "Cypress Semiconductor does not authorize its products for use as critical components in life support
systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress
Semiconductor against all damages."

PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO
PLDTOOLKIT
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
PACKAGES

,.

•

1[1

~
Table of Contents
~r~===================
General Product Information

Page Number

Cypress Semiconductor Background ....................................................................... 1-1
Cypress Process Technology .............................................................................. 1-2
Product Selection Guide ................................................................................. 1-3
Ordering Information .................................................................................... 1-6
Product Line Cross Reference ............................................................................. 1-8

Static RAMs (Random Access Memory)
Device Number
CY2147
CY2148
CY21U8
CY2149
CY21L49
CY6116
CY6117
CY6116A
CY6117A
CY7C122
CY7C123
CY7C128
CY7C128A
CY7C130
CY7C131
CY7C140
CY7C141
CY7C132
CY7C136
CY7C142
CY7C146
CY7C147
CY7C148
CY7C149
CY7C150
CY7C157
CY7C161-1O
CY7C162-10
CY7C161-20
CY7C162-20
CY7Cl64-10
CY7C166-1O
CY7Cl64-20
CY7C166-20
CY7C167
CY7C167A
CY7C168
CY7C169
CY7C168A
CY7C169A
CY7C170
CY7C170A
CY7Cl71
CY7Cl72
CY7Cl71A
CY7Cl72A
CY7C183
CY7C184
CY7C185-12
CY7C186-12
CY7C185-20
CY7C186-20
CY7C187

Description
4096 x 1 Static RAM ...................................................... 2-1
1024 x 4 Static RAM ...................................................... 2-6
1024 x 4 Static RAM, Low Power ............................................ 2-6
1024 x 4 Static RAM ...................................................... 2-6
1024 x 4 Static RAM, Low Power ............................................ 2-6
2048 x 8 Static RAM ..................................................... 2-12
2048 x 8 Static RAM ..................................................... 2-12
2048 x 8 Static RAM ..................................................... 2-19
2048 x 8 Static RAM ..................................................... 2-19
256 x 4 Static RAM Separate I/O .......................................... 2-26
256 x 4 Static RAM Separate I/O .......................................... 2-33
2048 x 8 Static RAM ..................................................... 2-40
2048 x 8 Static RAM ..................................................... 2-47
1024 x 8 Dual Port Static RAM ............................................ 2-54
1024 x 8 Dual Port Static RAM ............................................ 2-54
1024 x 8 Dual Port Static RAM ............................................ 2-54
1024 x 8 Dual Port Static RAM ............................................ 2-54
2048 x 8 Dual Port Static RAM ............................................ 2-65
2048 x 8 Dual Port Static RAM ............................................ 2-65
2048 x 8 Dual Port Static RAM ............................................ 2-65
2048 x 8 Dual Port Static RAM ............................................ 2-65
4096 x 1 Static RAM ..................................................... 2-76
1024 x 4 Static RAM ..................................................... 2-83
1024 x 4 Static RAM ..................................................... 2-83
1024 x 4 Static RAM Separate I/O .......................................... 2-90
16,384 x 16 Static Cache RAM ............................................... 2-98
16,384 x 4 Static RAM Separate I/O ......................................... 2-104
16,384 x 4 Static RAM Separate I/O ......................................... 2-104
16,384 x 4 Static RAM Separate I/O ......................................... 2-110
16,384 x 4 Static RAM Separate I/O ......................................... 2-110
16,384x4StaticRAM .................................................... 2-117
16,384 x 4 Static RAM ..................................................... 2-117
16,384x4StaticRAM .................................................... 2-123
16,384 x 4 Static RAM with Output Enable ................................... 2-123
16,384 x 1 Static RAM .................................................... 2-131
16,384 x 1 Static RAM .................................................... 2-138
4096 x 4 Static RAM .................................................... 2-145
4096 x 4 Static RAM .................................................... 2-145
4096 x 4 Static RAM .................................................... 2-152
4096 x 4 Static RAM .................................................... 2-152
4096 x 4 Static RAM with Output Enable ................................... 2-159
4096 x 4 Static RAM with Output Enable ................................... 2-165
4096 x 4 Static RAM Separate I/O ............................ -. ............ 2-171
4096 x 4 Static RAM Separate I/O ......................................... 2-171
4096 x 4 Static RAM Separate I/O ......................................... 2-178
4096 x 4 Static RAM Separate I/O ......................................... 2-178
2x4096x 16 Cache RAM ................................................ 2-185
2x4096x 16 Cache RAM ................................................ 2-185
8192 x 8 Static RAM .................................................... 2-193
8192 x 8 Static RAM .................................................... 2-193
8192 x 8 Static RAM .................................................... 2-199
8192x8StaticRAM .................................................... 2-199
65,536 x 1 Static RAM .................................................... 2-207

~

Table of Contents (Continued)
~~~~=============================================================
Static RAMs (Random Access Memory) (Continued)

Device Number

Description

CY7C189
CY7C190
CY7C191
CY7C192
CY7C194
CY7C196
CY7C197
CY7C198
CY7C199
CY74S189
CY27LS03
CY27S03
CY27S07
CY93422A
CY93L422A
CY93422
CY93L422
CYM1420
CYM1421
CYM1422
CYM1460
CYM1461
CYM1610
CYM1611
CYM1620
CYM1621
CYM1622
CYM1623
CYM1626
CYM1641
CYM1804
CYM1821
CYM1822
CYM1830
CYM1831
CYM1832

16x4StaticRAM .................................................... 2-215
16x4StaticRAM ....................................... ~ ............ 2-215
65,536 x 4 Static RAM Separate I/O ...................... ~ .................. 2-222
65,536 x 4 Static RAM Separate I/O ......................................... 2-222
65,536 x 4 Static RAM .................................................... 2-228
65,536 x 4 Static RAM with Output Enable ................................... 2-228
262,144 x 1 Static RAM .................................................... 2-234
32,768 x 8 Static RAM ..................................................... 2-240
32,768 x 8 Static RAM .................................................... 2-240
16 x 4 Static RAM .................................................... 2-246
16 x 4 Static RAM .................................................... 2-246
16x4StaticRAM .................................................... 2-246
16 x 4 Static RAM .................................................... 2-246
256 x 4 Static RAM Separate I/O ......................................... 2-252
256 x 4 Static RAM Separate I/O ......................................... 2-252
256 x 4 Static RAM Separate I/O ......................................... 2-252
256 x 4 Static RAM Separate I/O ......................................... 2-252
128K x 8 Static RAM Module ............................................. 2-259
128K x 8 Static RAM Module ............................................. 2-265
128K x 8 Static RAM Module ............................................. 2-271
512K x 8 Static RAM Module ............................................. 2-277
512K x 8 Static RAM Module ............................................. 2-282
16K x 16 Static RAM Module ............................................. 2-287
16K x 16 Static RAM Module ............................................. 2-293
64K x 16 Static RAM Module ............................................. 2-299
64K x 16 Static RAM Module ............................................. 2-305
64K x 16 Static RAM Module ............................................. 2-311
64K x 16 Static RAM Module ............................................. 2-312
64K x 16 Static RAM Module ............................................. 2-318
256K x 16 Static RAM Module ............................................. 2-324
lK x 32 Static RAM Module Separate I/O .................................. 2-330
16K x 32 Static RAM Module ............................................. 2-331
16K x 32 Static RAM Module Separate I/O .................................. 2-337
64K x 32 Static RAM Module ............................................. 2-343
64K x 32 Static RAM Module ............................................. 2-349
64K x 32 Static RAM Module ............................................. 2-355

Page Number

PROMs (Programmable Read Only Memory)
Introduction to PROMs .................................................................................. 3-1

Device Number

Description

CY7C225
CY7C235
CY7C245
CY7C245A
CY7C251
CY7C254
CY7C261
CY7C263
CY7C264
CY7C265
CY7C266
CY7C268
CY7C269
CY7C27I
CY7C274
CY7C277
CY7C279
CY7C281
CY7C282
CY7C285

512 x 8 Registered PROM .................................................. 3-4
1024 x 8 Registered PROM ...........................................•..... 3-15
2048 x 8 Reprogrammable Registered PROM .................................. 3-26
2048 x 8 Reprogrammable Registered PROM .................................. 3c38
16,384 x 8 Reprogrammable Power Switched PROM ............................. 3-50
16,384 x 8 Reprogrammable PROM ........................................... 3-50
8192 x 8 Reprogrammable Power Switched PROM ............................. 3-60
8192 x 8 Reprogrammable PROM ........................................... 3-60
8192 x 8 Reprogrammable PROM ........................................... 3-60
64KRegisteredPROM ................................................. 3-71
8192 x 8 Reprogrammable EPROM .......................................... 3-81
8192 x 8 Reprogrammable Registered Diagnostic PROM ..•..................... 3-86
8192 x 8 Reprogrammable Registered Diagnostic PROM ........................ 3-86
32,768 x 8 Reprogrammable Power Switched PROM ............................. 3-99
32,768 x 8 Reprogrammable PROM ........................................... 3-99
32,768 x 8 Reprogrammable Registered PROM ................................. 3-107
32,768 x 8 Reprogrammable Registered PROM ................................. 3-107
1024 x 8 PROM .................................................... : ..... 3-118
1024x8PROM ......................................................... 3-118
65,536 x 8 Reprogrammable Fast Column Access PROM ......................... 3-127

~

Table of Contents (Continued)
~~~U~ ===================================================================
PROMs (Programmable Read Only Memory) (Continued)
Device Number

Description

Page Number

CY7C289
65,536 x 8 Reprogrammable Fast Column Access PROM ......................... 3-127
CY7C286
65,536 x 8 Reprogrammable Registered PROM ................................. 3-128
CY7C287
65,536 x 8 Reprogrammable Registered PROM ................................. 3-128
CY7C291
2048 x 8 Reprogrammable PROM .......................................... 3-129
2048 x 8 PROM ......................................................... 3-129
CY7C292
CY7C291A
2048 x 8 Reprogrammable PROM .......................................... 3-138
2048 x 8 Reprogrammable PROM .......................................... 3-138
CY7C292A
2048 x 8 Reprogrammable PROM .......................................... 3-138
CY7C293A
PROM Programming Information ....................................................................... 3-147

EPLDs (Eraseable Programmable Logic Devices)
Introduction to EPLDs ................................................................................. .4-1

Device Number

Description

PAL® C 20 Series
16L8, 16R8, 16R6, 16R4 Reprogrammable CMOS PAL® Device ................... .4-7
PLD C 18G8
CMOS Generic 20 Pin Programmable Logic Device ............................. .4-26
PLD C 2OG1OB
CMOS Generic 24 Pin Reprogrammable PLD ................................... 4-33
PLD C 20GI0
CMOS Generic 24 Pin Reprogrammable PLD .................................. .4-33
PLD C 20RA1O
Reprogrammable Asynchronous CMOS Programmable Logic Device ................ 4-52
PAL C 22V1OB
Reprogrammable CMOS PAL Device ......................................... .4-61
PAL C 22V1O
Reprogrammable CMOS PAL Device ......................................... .4-61
CY7C330
Synchronous State Machine ................................................. .4-80
CY7C331
Asynchronous Registered EPLD .............................................. 4-91
CY7C332
Combinatorial Registered EPLD ............................................. 4-103
Multiple Array Matrix High Density EPLDs .................................. .4-112
CY7C340 EPLD Family
CY7C361
Ultra High Speed State Machine ............................................ .4-123
PLD Programming Information ......................................................................... 4-129

LOGIC
Device Number

Description

CY2901C
CY2909A
CY2911A
CY2910A
CY3341
CY7C401
CY7C402
CY7C403
CY7C404
CY7C408A
CY7C409A
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
CY7C51O
CY7C516
CY7C517
CY7C901
CY7C909
CY7C911
CY7C910
CY7C9101
CY7C9115
CY7C9116
CY7C9117

CMOS 4-Bit Slice ............................................................ 5-1
CMOS Microprogram Sequencer ............................................... 5-9
CMOS Microprogram Sequencer ............................................... 5-9
CMOS Microprogram Controller .............................................. 5-14
64 x 4 FIFO Serial Memory .................................................. 5-19
Cascadeable 64 x 4 FIFO .................................................... 5-24
Cascadeable 64 x 5 FIFO .................................................... 5-24
Cascadeable 64 x 4 FIFO with Output Enable ................................... 5-24
Cascadeable 64 x 5 FIFO with Output Enable ................................... 5-24
Cascadeable 64 x 8 FIFO with Output Enable ................................... 5-34
Cascadeable 64 x 9 FIFO .................................................... 5-34
Cascadeable 512 x 9 FIFO ................................................... 5-48
Cascadeable 512 x 9 FIFO ................................................... 5-48
Cascadeable 1024 x 9 FIFO .................................................. 5-48
Cascadeable 1024 x 9 FIFO .................................................. 5-48
Cascadeable 2048 x 9 FIFO .................................................. 5-48
Cascadeable 2048 x 9 FIFO .................................................. 5-48
16 x 16 Multiplier Accumulator ............................................... 5-60
16 x 16 Multiplier ........................................................... 5-72
16 x 16 Multiplier ........................................................... 5-72
CMOS 4-Bit Slice ........................................................... 5-84
Microprogram Sequencer .................................................... 5-99
Microprogram Sequencer .................................................... 5-99
Microprogram Controller ................................................... 5-110
CMOS 16-Bit Slice ................................................... , ..... 5-121
CMOS 16-Bit Microprogrammed ALU ........................................ 5-138
CMOS 16-Bit Microprogrammed ALU ........................................ 5-138
CMOS 16-Bit Microprogrammed ALU ........................................ 5-138

PALlID is a registered trademark of Monolithic Memories Inc.

~
Table of Contents (Continued)
'~r~===================
RISC

Page Number

Introduction to RISC .................................................................................... 6-1

Device Number

Description

CY7C601
CY7C602
CY7C604
CY7C605
CY7C608
CY7C609

32-Bit RISC Integer Unit ..................................................... 6-6
Floating-Point Unit ......................................................... 6-12
Cache Controller and Memory Management Unit ................................ 6-13
Multiprocessor Cache Controller and Memory Management Unit ................... 6-17
Floating-Point Controller .................................................... 6-18
Floating-Point Processor ..................................................... 6-23

Modules
Custom Module Capabilities .............................................................................. 7-1

ECL
Device Number

Description

CYI0E301
CY100E30l
CYIOE302
CYIOOE302
CYI0E422
CYlOOE422
CYI0E474
CY100E474

Combinatorial ECL 16P8 PLD ................................................. 8-1
Combinatorial ECL 16P8 PLD ................................................. 8-1
Combinatorial ECL 16P4 PLD ................................................. 8-6
Combinatorial ECL 16P4 PLD ................................................. 8-6
256 x 4 ECL Static RAM .................................................... 8-11
256 x 4 ECL Static RAM .................................................... 8-11
1024 x 4 ECL Static RAM ................................................... 8-16
1024 x 4 ECL Static RAM ................. '.................................. 8-16

Military Information
Military Overview ....................................................................................... 9-1
Military Product Selection Guide ....•..................................................................... 9-2
Military Ordering Information ............................................................................ 9-5

BridgeMOS
BridgeMOS Overview .................................................................................. 10-1

Device Number

Description

CY8CI50
CY8C245
CY8C29I
CY8C901
CY8C909
CY8C911

BridgeMOS 1024 x 4 Static RAM Separate I/O .................................. 10-1
BridgeMOS 2048 x 8 Reprogrammable Registered PROM ......................... 10-1
BridgeMOS Reprogrammable 2048 x 8 PROM ............ " .................... 10-1
BridgeMOS 4-Bit Slice ....................................................... 10-1
BridgeMOS Microprogram Sequencer .......................................... 10-1
BridgeMOS Microprogram Sequencer .......................................... 10-1

QuickPro
Device Number

Description

CY3000

Combined PROM, PLD, and EPROM Programmer .............................. 11-1

PLDToolKit
Device Number

Description

CY3101

Programmable Logic Design Tool ............................................. 12-1

Quality and Reliability
Quality, Reliability and Process Flows ..................................................................... 13-1

Application Briefs

RAM Input and Output Characteristics .................................. >..................•.......•...... 14-1
Power Characteristics of Cypress Products ......................................................... '" ..... 14-8
Pin-Out Compatibility Considerations ofSRAMs and PROMs .................. ; ........ " ................... 14-15

Packages
Thermal Management and Component Reliability ..................................... " .................... 15-1
Package Diagrams ..................................................................................... 15-6

~
Numeric Device Index
~~~aoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Page Number

Device Number

Description

10E301
lOE302
1OE422
lOE474
l00E301
l00E302
l00E422
l00E474
2147
2148
21IA8
2149
21IA9
27L503
27503
27S07
2901C
2909A
2910A
2911A
3000
3101
3341
6116
6116A
6117
6117A
74S189
7C122
7C123
7CI28
7CI28A
7C130
7C131
7C132
7C136
7C14O
7C141
7CI42
7C146
7CI47
7CI48
7CI49
7CI50
7CI57
7C161-10
7C161-20
7C162-10
7C162-20
7CI64-10
7CI64-20
7C166-1O
7C166-20
7CI67
7C167A
7CI68
7C168A
7CI69
7CI69A
7CI70
7CI70A

Combinatorial ECL 16P8 PLD ................................................. 8-1
Combinatorial ECL 16P4 PLD ................................................. 8-6
256 x 4 ECL Static RAM ................................................. 8-11
1024 x 4 ECL Static RAM ................................................. 8-16
Combinatorial ECL 16P8 PLD ................................................. 8-1
Combinatorial ECL 16P4 PLD ................................................. 8-6
256 x 4 ECL Static RAM ................................................. 8-11
1024 x 4 ECL Static RAM .. , ..................... , .............. , ......... 8-16
4096 x I Static RAM ...................................................... 2-1
1024 x 4 Static RAM ....................................................... 2-6
1024 x 4 Static RAM, Low Power ............................................ 2-6
1024 x 4 Static RAM ...................................................... 2-6
1024 x 4 Static RAM, Low Power ............................................ 2-6
16 x 4 Static RAM .................................................... 2-246
16x4StaticRAM .................................................... 2-246
16 x 4 Static RAM .................................................... 2-246
CMOS 4-Bit Slice ............................................................ 5-1
CMOS Microprogram Sequencer ............................................... 5-9
CMOS Microprogram Controller .............................................. 5-14
CMOS Microprogram Sequencer ............................................... 5-9
Combined PROM, PLD, and EPROM Programmer .............................. 11-1
Programmable Logic Design Tool ............................................. 12-1
64 x 4 FIFO Serial Memory .............................................. 5-19
2048 x 8 Static RAM ..................................................... 2-12
2048 x 8 Static RAM ..................................................... 2-19
2048 x 8 Static RAM ................. " .. , ............................... 2-12
2048 x 8 Static RAM ..................................................... 2-19
16 x 4 Static RAM .................................................... 2-246
256 x 4 Static RAM Separate I/O .......................................... 2-26
256 x 4 Static RAM Separate I/O .......................................... 2-33
2048 x 8 Static RAM ..................................................... 2-40
2048 x 8 Static RAM ..................................................... 2-47
1024 x 8 Dual Port Static RAM ............................................ 2-54
1024 x 8 Dual Port Static RAM ............................................ 2-54
2048 x 8 Dual Port Static RAM ............................................ 2-65
2048 x 8 Dual Port Static RAM ............................................ 2-65
1024 x 8 Dual Port Static RAM ............................................ 2-54
1024 x 8 Dual Port Static RAM ............................................ 2-54
2048 x 8 Dual Port Static RAM ............................................ 2-65
2048 x 8 Dual Port Static RAM ............................................ 2-65
4096 x 1 Static RAM ..................................................... 2-76
1024 x 4 Static RAM ..................................................... 2-83
1024 x 4 Static RAM ..................................................... 2-83
1024 x 4 Static RAM Separate I/O .......................................... 2-90
16,384 x 16 Static Cache RAM ............................................... 2-98
16,384 x 4 Static RAM Separate I/O ......................................... 2-104
16,384 x 4 Static RAM Separate I/O ......................................... 2-110
16,384 x 4 Static RAM Separate I/O ......................................... 2-104
16,384 x 4 Static RAM Separate I/O .......... , .............................. 2-110
16,384 x 4 Static RAM .................................................... 2-117
16,384x4StaticRAM .................................................... 2-123
16,384 x 4 Static RAM .................................................... 2-117
16,384x4StaticRAM .................................................... 2-123
16,384 x I Static RAM .................................................... 2-131
16,384 x I Static RAM .................................................... 2-138
4096 x 4 Static RAM .................................................... 2-145
4096 x 4 Static RAM .................................................... 2-152
4096 x 4 Static RAM .................................................... 2-145
4096 x 4 Static RAM .................................................... 2-152
4096 x 4 Static RAM with Output Enable ................................... 2-159
4096 x 4 Static RAM with Output Enable ................................... 2-165

~

Numeric Device Index (Continued)
~~~UaoR================================================================
Page Number

Device Number

Description

7Cl71
7Cl71A
7Cl72
7Cl72A
7C183
7C184
7C185-12
7C185-20
7C186-12
7C186-20
7C187
7C189
7C190
7C191
7C192
7C194
7C196
7C197
7C198
7C199
7C225
7C235
7C245
7C245A
7C251
7C254
7C261
7C263
7C264
7C265
7C266
7C268
7C269
7C271
7C274
7C277
7C279
7C281
7C282
7C285
7C286
7C287
7C289
7C291
7C291A
7C292
7C292A
7C293A
7C330
7C331
7C332
7C34O EPLD Family
7C361
7C401
7C402
7C403
7C404
7C408A
7C409A

4096 x 4 Static RAM Separate I/O ......................................... 2-171
4096 x 4 Static RAM Separate I/O ......................................... 2-178
4096 x 4 Static RAM Separate I/O ......................................... 2-171
4096 x 4 Static RAM Separate I/O ......................................... 2-178
2 x 4096 x 16 Cache RAM •.............•................................. 2-185
2 x 4096 x 16 Cache RAM ............ ; ................................... 2-185
8192x 8 Static RAM .................................................... 2-193
8192x 8 Static RAM .................................................... 2-199
8192x 8 Static RAM .................................................... 2-193
8192x 8 Static RAM .................................................... 2-199
65,536 x 1 Static RAM .................................................... 2-207
16x4StaticRAM .................................................... 2-215
16 x 4 Static RAM .................................................... 2-215
65,536 x 4 Static RAM Separate I/O ......................................... 2-222
65,536 x 4 Static RAM Separate I/O ......................................... 2-222
65,536 x 4 Static RAM .................................................... 2-228
65,536 x 4 Static RAM with Output Enable ................................... 2-228
262,144 x 1 Static RAM ..................................................... 2-234
32,768 x 8 Static RAM .................................................... 2-240
32,768 x 8 Static RAM .................................................... 2-240
512 x 8 Registered PROM ................................................. 3-4
1024 x 8 Registered PROM ................................................ 3-15
2048 x 8 Reprogrammable Registered PROM ................................. 3-26
2048 x 8 Reprogrammable Registered PROM ................................. 3-38
16,384 x 8 Reprogrammable Power Switched PROM ............................ 3-50
16,384 x 8 Reprogrammable PROM .......................................... 3-50
8192 x 8 Reprogrammable Power Switched PROM ............................ 3-60
8192 x 8 Reprogrammable PROM .......................................... 3-60
8192 x 8 Reprogrammable PROM .......................................... 3-60
64K Registered PROM ................................................ 3-71
8192 x 8 Reprogrammable EPROM ......................................... 3-81
8192 x 8 Reprogrammable Registered Diagnostic PROM ....................... 3-86
8192 x 8 Reprogrammable Registered Diagnostic PROM ....................... 3-86
32,768 x 8 Reprogrammable Power Switched PROM ............................ 3-99
32,768 x 8 Reprogrammable PROM .......................................... 3-99
32,768 x 8 Reprogrammable Registered PROM ................................ 3-107
32,768 x 8 Reprogrammable Registered PROM ................................ 3-107
1024 x 8 PROM ........................................................ 3-118
1024 x 8 PROM ........................................................ 3-118
65,536 x 8 Reprogrammable Fast Column Access PROM ........................ 3-127
65,536 x 8 Reprogrammable Registered PROM ................................ 3-128
65,536 x 8 Reprogrammable Registered PROM ................................ 3-128
65,536 x 8 Reprogrammable Fast Column Access PROM ........................ 3-127
2048 x 8 Reprogrammable PROM ......................................... 3-129
2048 x 8 Reprogrammable PROM ......................................... 3-138
2048 x 8 PROM ........................................................ 3-129
2048 x 8 Reprogrammable PROM ......................................... 3-138
2048 x 8 Reprogrammable PROM ......................................... 3-138
Synchronous State Machine Reprogrammable PLD ................... '............ 4-80
Asynchronous Registered EPLD ............................................. .4-91
Combinatorial Registered EPLD ............................................. 4-103
Multiple Array Matrix High Density EPLDs ................................... 4-112
Ultra High Speed State Machine ............................................. 4-123
Cascadeable 64 x 4 FIFO .................................................... 5-24
Cascadeable 64 x 5 FIFO .................................................... 5-24
Cascadeable 64 x 4 FIFO with Output Enable ................................... 5-24
Cascadeable 64 x 5 FIFO with Output Enable ................................... 5-24
Cascadeable 64 x 8 FIFO with Output Enable ................................... 5-34
Cascadeable 64 x 9 FIFO ............ ; ....................................... 5-34

~CYPRFSS

Numeric Device Index (Continued)
,..,~~~~==========================================================
Device Number

Description

Page Number

7C420
Cascadeable 512 x 9 FIFO ................................................... 5-48
7C421
Cascadeable 512 x 9 FIFO ................................................... 5-48
7C424
Cascadeable 1024 x 9 FIFO .................................................. 5-48
7C425
Cascadeable 1024 x 9 FIFO .................................................. 5-48
7C428
Cascadeable 2048 x 9 FIFO .................................................. 5-48
7C429
Cascadeable 2048 x 9 FIFO .................................................. 5-48
7C510
16 x 16 Multiplier Accumulator ............................................... 5-60
7C516
16x 16 Multiplier ........................................................... 5-72
7C517
16 x 16 Multiplier ........................................................... 5-72
7C601
32-Bit RISC Integer Unit ..................................................... 6-6
7C602
Floating Point Unit ......................................................... 6-12
7C604
Cache Controller and Memory Management Unit ................................ 6-13
7C605
Multiprocessor Cache Controller and Memory Management Unit ................... 6-17
7C608
Floating-Point Controller .................................................... 6-18
7C609
Floating-Point Processor ..................................................... 6-23
7C901
CMOS Four-Bit Slice ........................................................ 5-84
7C909
Microprogram Sequencer .................................................... 5-99
7C910
Microprogram Controller ................................................... 5-110
7C911
Microprogram Sequencer .................................................... 5-99
7C9101
CMOS 16-Bit Slice ......................................................... 5-121
7C9115
CMOS 16-Bit Microprogrammed ALU ........................................ 5-138
CMOS 16-Bit Microprogrammed ALU ........................................ 5-138
7C9116
7C9117
CMOS 16-Bit Microprogrammed ALU ........................................ 5-138
8C150
BridgeMOS 1024 x 4 Static RAM Separate I/O .................................. 10-1
8C245
BridgeMOS 2048 x 8 Reprogrammable Registered PROM ......................... 10-1
8C291
BridgeMOS Reprogrammable 2048 x 8 PROM .................................. 10-1
8C901
BridgeMOS Four-Bit Slice ................................................... 10-1
8C909
BridgeMOS Microprogram Sequencer .......................................... 10-1
8C911
BridgeMOS Microprogram Sequencer ....... , .................................. 10-1
93422
256 x 4 Static RAM Separate I/O ............................................ 2-252
93422A
256 x 4 Static RAM Separate I/O ............................................ 2-252
93U22
256 x 4 Static RAM Separate I/O ............................................ 2-252
93U22A
256 x 4 Static RAM Separate I/O ............................................ 2-252
M1420
128K x 8 Static RAM Module ............................................... 2-259
M1421
128K x 8 Static RAM Module ............................................... 2-265
M1422
128K x 8 Static RAM Module ............................................... 2-271
M1460
512K x 8 Static RAM Module ............................................... 2-277
M1461
512K x 8 Static RAM Module ............................................... 2-282
M1610
16K x 16 Static RAM Module ............................................... 2-287
M1611
16Kx 16 Static RAM Module ............................................... 2-293
M1620
64K x 16 Static RAM Module ............................................... 2-299
M1621
64K x 16 Static RAM Module ............................................... 2-305
M1622
64Kx 16 Static RAM Module ............................................... 2-311
M1623
64K x 16 Static RAM Module ............................................... 2-312
M1626
64K x 16 Static RAM Module ............................................... 2-318
Ml641
256K x 16 Static RAM Module .............................................. 2-324
M1804
lK x 32 Static RAM Module Separate I/O ..................................... 2-330
M1821
16K x 32 Static RAM Module ............................................... 2-331
M1822
16K x 32 Static RAM Module Separate I/O .................................... 2-337
M1830
64K x 32 Static RAM Module ............................................... 2-343
M1831
64K x 32 Static RAM Module ............................................... 2-349
M1832
64K x 32 Static RAM Module ............................................... 2-355
PAL C 20 Series
Reprogrammable CMOS PAL Device ........................................... 4-7
16L8 .............................................................................................. .4-7
16R4 .............................................................................................. .4-7
16R6 ............................................................................................... 4-7
16R8 .............................................................................................. .4-7
PAL C 22V10
Reprogrammable CMOS PAL Device ......................................... .4-61
PAL C 22V1OB
Reprogrammable CMOS PAL Device .......................................... 4-61
PLD C 18G8
CMOS Generic 20 Pin Programmable Logic Device .............................. 4-26
PLD C 20G1O
CMOS Generic 24 Pin Reprogrammable PLD .................................. .4-33
PLD C 20G lOB
CMOS Generic 24 Pin Reprogrammable PLD .................................. .4-33
PLD C 20RA10
Reprogrammable Asynchronous CMOS Programmable Logic Device ............... .4-52

PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO
PLDTOOLKIT
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
PACKAGES

,.

•I'.

Section Contents
~~~~~O®UcrOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PRESS
•
General Product Information

Page Number

Cypress Semiconductor Background ....................................................................... 1·1
Cypress Process Technology .............................................................................. 1·2
Product Selection Guide ................................................................................. 1·3
Ordering Information .................................................................................... 1·6
Product Line Cross Reference ............................................................................. 1·8

~~UaoR=============================================================
Cypress Semiconductor Background

the PLD ToolKit software are updated via floppy disk,
thereby allowing quick support of all Cypress programmable products.
Logic products include circuits such as 4-bit and 16-bit
slices, 16 x 16 multipliers, and 16-bit microprogrammable
ALUs, as well as a family of FIFOs that range from 64 x 4
to 2048 x 9. FIFOs provide the interface between digital
information paths of widely varying speeds. This allows the
information source to operate at its own intrinsic speed
while the results may be processed or distributed at a speed
commensurate with need.
Until 1988, all Cypress products were TTL I/O compatible. In 1989, Cypress will introduce ECL products having
access times (propagation delays) of less than 3 ns in either
of the popular I/O configurations, lOOK or 10KlIO~!i'
ECL RAMs include 256 x 4 and 1K x 4 RAM famlhes
with balanced read/write cycles. The ECL PLDs are combinatorial 16P8 and 16P4 devices that can be programmed
on QuickPro and other commercially available programming tools. Both the RAMs and PLDs are offered in low
power versions, reducing operating power by 30 to 40 percent, while achieving 5 ns access time (RAM) and 6 ns tpD
(PLD).
The module family consists of both standard and custom
modules incorporating circuits from the other six product
families. This capability provides a fast, low risk solution
for designs requiring the ultimate in system performance
and density. Several module configurations are available
depending on height and board real estate constrai1l:ts.
Modules include Single-In-Line, Dual-In-Line, Dual Smgle-In-Line, Vertical Dual-In-Line, Quad-In-Line, and
(Staggered) Zig-Zag-In-Line packages.
Cypress' CY7C600 family of RISC microprocessor pr?ducts provides state-of-the-art high performance computmg
for applications ranging from UNIX-based business computers and workstations to embedded controls. Based on
the SPARCTM RISC architecture, the family provides a
complete solution with Integer Unit (IU), Floating-Point
Unit (FPU), Cache Control and Memory Management
Unit (CMU) and Cache RAMs (CRAMs). The family is
functionally partitioned to provide a range of features, performance, and price to suit each type of application.
Situated in California's Silicon Valley (San Jose) and
Round Rock (Austin), Texas, Cypress houses R&D, design, wafer fabrication, assembly, and ad~inistrati?n. The
facilities are designed to the most demandmg techrucal and
environmental specifications in the industry. At the Texas
facility, the entire wafer fabrication area is specified to be a
Class 1 environment. This means that the ambient air has
less than 1 particle of greater than 0.2 microns in diameter
per cubic foot of air. Other environmental considerations
are carefully insured: temperature is controlled to a ± 0.2
degree Fahrenheit tolerance; filtered air is completely exchanged more than 10 times each minute throughout the
fab; and critical equipment is situated on isolated slabs to
minimize vibration.

Cypress Semiconductor was founded in April 1983 with
the stated goal of serving the high performance semiconductor market. This market is served by producing the
highest performance integrated circuits using state-of-theart processes and circuit design. Cypress is a complete
semiconductor manufacturer, performing its own process
development, circuit design, wafer fabrication, assembly,
and test. The company went public in May 1986 and was
listed on the New York Stock Exchange in October 1988.
The initial semiconductor process, a CMOS process employing 1.2 micron geometries, was introduced in Mar~h
1984. This process is used in the manufacturing of Static
RAMs and Logic circuits. In the third quarter of 1984, a
1.2 micron CMOS EPROM process was introduced for the
production of programmable products. At the time of introduction, these processes were the most advanced production processes in the industry. Following the 1.2 micron
processes, a 0.8 micron CMOS SRAM process was i~ple­
mented in the first quarter of 1986, and a 0.8 micron
EPROM process in the third quarter of 1987.
In keeping with the strategy of serving the high performance markets with state-of-the-art integrated circuits, Cypress will introdu~ two new processes in 1989. Th~se ~ill
be a bipolar submlCron process, targeted for ECL CirCUits,
and a BiCMOS process to be used for most types of TTL
and ECL circuits.
The circuit design technology used by Cypress is also stateof-the-art. This design technology, along with advanced
process technology, allows Cypress to introduce the fastest,
highest performance circuits in the industry. Cypress'
products fall into seven families: high speed Static RAMs,
PROMS, Erasable Programmable Logic Devices, Logic,
RISC microprocessors, ECL, and module products. Members of the Static RAM family include devices in densities
of 64 bits to 256K bits, and performance from 7 ns to
35 ns. The various organizations, 16 x 4, 256 x 4 through
256K x 1, 32K x 8, and 64K x 4, provide optimal solutions
for applications such as large mainframes, high-speed controllers, communications, and graphics display.
Cypress' programmable products consist of high speed
CMOS PROMs and Erasable Programmable Logic Devices (EPLDs), both employing an EPROM programming element. Like the high speed Static RAM family, these products are the natural choice to replace older devices because
they provide superior performance at one half of the power
consumption. PROM densities range from 4K to 256K bits
in byte wide organization. EPLD products range from 20pins to 68-pins with performance as fast as 12 ns. To support new programmable products, Cypress introduced the
QuickPro™ programming system (CY3000) for PLDs and
PROMs, and the PLD ToolKit for PLDs. QuickPro is a
development tool which includes a single, IBM PC® compatible add-on board, and a software utility program. The
PLD ToolKit is a software design tool that assembles and
simulates logic functions, generates JEDEC files, and reverse assembles to create source files. Both QuickPro and

IBM PC® is a registered trademark of International Business Corporation.
QuickPro™ is a trademark of Cypress Semiconductor Corporation.
SPARCTM is a trademark of Sun MicroSystems, Inc.

I-I

II

~~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Cypress Semiconductor Background (Continued)
Attention to assembly is equally as critical. Cypress assembles and tests 55 packages in the United States at its San
Jose, California, plant. Assembly is completed in a clean
room until the silicon die is sealed in a package. Lead
frames are handled in carriers or cassettes through the entire operation. Automated robots remove and replace parts
into cassettes. Using sophisticated automated equipment,
parts are assembled and tested in less than five days. The
Cypress assembly line is the most flexible, automated line
in the United States.
The Cypress motto has always been "only the best-the
best facilities, the best equipment, the best employees ...
all striving to make the best CMOS, BiCMOS and bipolar
products."
Cypress Process Technology
In the last decade, there has been a tremendous need for
high performance semiconductor products manufactured
with a balance of SPEED, RELIABILITY, and POWER.
Cypress Semiconductor has overcome the classically held
perceptions that CMOS is a moderate performance technology.
Cypress initially introduced a 1.2 micron "N" well technology with double layer poly, and a single layer metal.
The process employs lightly doped extensions of the heavily doped source and drain regions for both "N" and "P"
channel transistors for significant improvement in gate delays. Further improvements in performance, through the
use of substrate bias techniques, have added the benefit of
eliminating the input and output latchup characteristics associated with the older CMOS technologies.
Cypress pushed process development to new limits in the
area of PROMs (programmable Read Only Memory) and
EPLDs (Eraseable Programmable Logic Devices). Both
PROMs and EPLDs have existed since the early 19708 in a
bipolar process which employed various fuse technologies
and was the only viable high speed non-volatile process
available. Cypress PROMs and EPLDs use EPROM technology, which has also been in use in MOS (Metal Oxide
Silicon) also since the early 19708. EPROM technology has
traditionally emphasized density advantages, while forsaking performance. Through improved technology, Cypress
has produced the first high performance CMOS PROMs
and EPLDs, replacing their bipolar counterparts.
To maintain our leadership position in CMOS Technology,
Cypress has introduced a sub-micron technology into production. This process reduces the drawn channel length
from the current 1.2 microns to 0.8 microns. This sub-micron breakthrough makes Cypress' CMOS one of the most
advanced production processes in the world.
To further enhance the technology from the reliability direction, improvements have been incorporated in the process and design, minimizing electrostatic discharge and input signal clipping ptoblems.
Finally, although not a requirement in the high performance arena, CMOS technology substantially reduces the

1-2

power consumption for any device. This improves reliability by allowing the device to operate at a lower die temperature. Now higher levels of integration are possible without
trading performance for power. For instance, devices may
now be delivered in plastic packages, without any impact
on reliability.
While addressing the performance issues of CMOS technology, Cypress has not ignored the quality and reliability
aspects of technology development. Rather, the traditional
failure mechanisms of electrostatic discharge (ESD) and
latchup have been addressed and solved through process
and design technology innovation.
ESD-induced failure has been a generic problem for many
high performance MOS and bipolar products. Although in
its earliest years MOS technology experienced oxide reliability failures, this problem has largely been eliminated
through improved oxide growth techniques and a better
understanding of the ESD problem. The effort to adequately protect against ESD failures is perturbed by circuit delays associated with ESD protection circuits. Focusing on
these constraints, Cypress has developed ESD protection
circuitry specific to 1.2 and 0.8 micron CMOS process
technology. Cypress products are designed to withstand
voltage and energy levels in excess of 2001 volts and
0.4 milli-joules, more than twice the energy level specified
by MIL STD 883C.
Latchup, a traditional problem with CMOS technologies,
has been eliminated through the use of substrate bias generation techniques, the elimination of the "P" MOS pullups in the output drivers, the use of guardring structures,
and care in the physical layout of the products.
Cypress has also developed additional process innovations
and enhancements: the use of multi-layer metal interconnections, advanced metal deposition techniques, silicides,
exclusive use of plasma for etching and ashing process
steps, and 100% stepper technology with the world's most
advanced equipment.
A wholly owned subsidiary of Cypress, Aspen Semiconductor, has developed both advanced Bipolar and BiCMOS
technologies augmenting the capabilities of the Cypress
CMOS processes. Both the new Bipolar and BiCMOS technologies are based on the Cypress 0.8 micron CMOS process for enhanced manufacturability. Like CMOS, these
processes are scalable to take advantage offmerline lithography. Where speed is critical, Cypress BiCMOS allows
increased transistor performance. It also allows reduced
power in the non-speed critical sections of the design to
optimize the speed/power balance. The Bipolar and
BiCMOS processes make possible memories and logic operating up to 400 MHz. The drive to maintain process
technology leadership has not stopped with the 0.8 micron
devices. Cypress is developing fine line geometries beyond
this to insure technology leadership in the next decade.
Cypress technologies have been carefully designed, creating
products that are "only the best" in high speed, excellent
reliability, and low power.

Product Selection Guide

SEMJCONDUCI'OR

Size

Organization

Pins

64
64
64
64
64
64
IK
IK
IK
IK
4K
4K
4K
4K
4K
4K
4K
8K
8K
8K
8K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
128K
128K
256K
256K
256K
256K
256K
256K
256K
256K

16 x 4-lnverting
16 x 4-Non-Inverting
16 x 4-lnverting
16 x 4-Inverting
16 x 4-Non-Inverting
16 x 4-Inv. Low Power
256x4
256 x 4
256x4
256x4
4096 x I-CS Power Down
4096 x I-CS Power Down
1024 x 4-CS Power Down
1024 x 4-CS Power Down
1024 x4
1024 x4
1024 x 4-Separate I/O, Reset
1024 x 8-Dual Port
1024 x 8-Dual Port (Slave)
1024 x 8-Dual Port
1024 x 8-Dual Port
2048 x 8-CS Power Down
2048 x 8-CS Power Down
2048 x 8-CS Power Down
2048 x 8-CS Power Down
2048 x 8-CS Power Down
2048 x 8-CS Power Down
16384 x I-CS Power Down
16384 x I-CS Power Down
4096 x 4-CS Power Down
4096 x 4-CS Power Down
4096x4
4096x4
4096 x 4-Output Enable
4096 x 4-Output Enable
4096 x 4-Separate I/O
4096 x 4-Separate I/O
4096 x 4-Separate I/O
4096 x 4-Separate I/O
2048 x 8-Dual Port
2048 x 8-Dual Port (Slave)
2048 x 8
2048 x 8
8192 x 8
8192 x 8
8192 x 8-CS Power Down
8192 x 8-CS Power Down
16384 x 4
16384 x 4-CS Power Down
16384 x4
16384 x 4-Output Enable
16384 x4
16384 x4
16384 x 4-Separate I/O
16384 x 4-Separate I/O
65536 x I-CS Power Down
8192 x 16-Addresses Latched except A-12
8192 x 16-Addresses Latched
16384 x 16
32768 x 8-CS Power Down
32768 x 8-CS Power Down
65536 x 4-CS Power Down
65536 x 4-CS Power Down With OE
65536 x 4-Separate I/O
65536 x 4-Separate I/O
262144 x I-CS Power Down

16
16
16
16
16
16
22
24S
22
22
18
18
18
18
18
18
24S
48
48
52
52
24S
24
24
24
32S
32S
20
20
20
20
20
20
22S
20
24S
24S
24S
24S
48
48
52
52
28
28
28S
28
22
22S
24
24S
28
28
28S
28S
22S
52
52
52
28
28S
24S
28S
28S
28S
24S

Part Number

Speed (ns)

CY7CI89
tAA = 15, 25
CY7CI90
tAA = 15,25
CY74S189
tAA=35
CY27S03A
tAA =25,35
CY27S07A
tAA =25,35
CY27LS03M
tAA =65
CY7CI22
tAA = IS, 25, 35
CY7CI23
tAA =7,9,12
CY9122/9I L22
tAA = 25, 35, 45
CY93422A/93L422A
tAA = 35, 45, 60
CY7CI47
tAA = 25, 35, 45
CY2147/2IL47
tAA = 35, 45, 55
CY7CI48
tAA = 25, 35, 45
CY2148/21 L48
tAA = 35, 45, 55
CY7CI49
tAA = 25, 35, 45
CY2149/21L49
tAA = 35, 45, 55
CY7CI50
tAA = 12, 15,25,35
CY7C130
tAA = 25, 35, 45, 55
CY7CI40
tAA = 25, 35,45, 55
CY7Cl3l
tAA = 25, 35,45, 55
CY7CI41
tAA = 25, 35,45, 55
CY7CI28
tAA = 35, 45, 55
CY7CI28A
tAA = 20, 25, 35, 45, 55
CY6116
tAA = 35, 45, 55
CY6116A
tAA = 20, 25, 35, 45, 55
CY6117
tAA = 35, 45, 55
CY6117A
tAA = 20, 25, 35, 45, 55
CY7CI67
tAA = 25, 35,45
CY7CI67A
tAA = 20, 25, 35, 45
CY7CI68
tAA = 25, 35, 45
CY7CI68A
tAA = 20, 25, 35, 45
CY7CI69
tAA = 25, 35,40
CY7CI69A
tAA = 20, 25, 35, 40
CY7CI70
tAA = 25, 35,45
CY7CI70A
tAA = 20, 25, 35, 45
CY7C171
tAA = 20, 25, 35, 45
CY7C171A
tAA = 20, 25, 35, 45
CY7C172
tAA = 20, 25, 35, 45
CY7C172A
tAA = 20, 25, 35, 45
CY7C132
tAA = 25, 35,45, 55
CY7CI42
tAA = 25, 35,45, 55
CY7C136
tAA = 25, 35,45, 55
CY7CI46
tAA = 25, 35, 45, 55
CY7C185-12
tAA= 12, 15
CY7C186-12
tAA= 12, 15
CY7C185-2O
tAA = 20, 25, 35, 45
CY7C186-20
tAA = 20, 25, 35, 45
CY7CI64-1O
tAA = 10, 12, 15
CY7CI64-20
tAA = 20, 25, 35, 45
CY7C166-1O
tAA = 10, 12, IS
CY7C166-20
tAA = 20, 25, 35, 45
CY7C161-1O
tAA = 10, 12, IS
CY7C162-10
tAA = 10, 12, IS
CY7C161-20
tAA = 20, 25, 35, 45
CY7C I62-20
tAA = 20, 25, 35, 45
CY7CI87
tAA = 20, 25, 35, 45
CY7CI83
tAA = 25, 35, 45
CY7CI84
tAA = 25, 35, 45
CY7CI57
tAA =20,24
CY7CI98
tAA = 35, 45, 55
CY7CI99
tAA = 35, 45, 55
CY7CI94
tAA = 25, 35,45
CY7CI96
tAA = 25, 35,45
CY7CI91
tAA = 25, 35,45
CY7CI92
tAA = 25, 35, 45
CY7CI97
tAA = 25, 35,45
Notes:
Paekage Code:
B = PLASTIC PIN GRID
R
The above specifications are for the commercial temperature range of O'C to
70'C.
ARRAY
S
Military temperature range (- 55°C to + 125°C) product processed to MILD = CERDIP
T
STD-883 Revision C is also available. Speed and power selections may vary
F = FLATPAK
V
from those above.
G = PIN GRID ARRAY
W
Commercial grade product is available in plastic, CERDIP, or LCC. Military
X
H = WINDOWED
grade product is available in CERDIP or LCC. PLCC, SOJ, and SOiC
HD
HERMETIC LCC
packages are available on some products.
J = PLCC
HV
All power supplies are Vee = SV ± 10%.
K = CERPAK
22S stands for 22-pin 300 mil. 24S stands for 24-pin 300 mil. 28S stands for
L = LCC
PF
28-pin 300 mil.
P = PLASTIC
PS
F, K and T packages are special order only.
Q = WINDOWED LCC
PZ
SRAMs

1-3

IccllsullCCDR
(mA@ns)
55@25
55@25
90@35
90@25
90@25
38@65
6O@25
120@7
120@25
80@45
80/1O@ 35
125/25 @35
80/1O@ 35
120/2O@35
80@35
120@35
90@ 12
170@ 25
170@ 25
170@25
170@ 25
90/20@ 55
90/20@55
120/20@45
80/20@55
130/20@ 55
loo/20@55
50/15 @25
50/15@45
90/15 @ 25
70/15@45
90@25
70@45
90@45
90@45
90/15 @ 25
90@45
90/15@25
90@45
170@25
170@25
170@ 25
170@ 25
115/50@ 15
115/50@ 15
loo/20@25
loo/20@25
115/50@ 15
70/20@25
115/50@ IS
70/20@25
115/50@ IS
115/50@ 15
70/20@25
70/20@ 25
70/20@25
220@25
220@25
TBD
llO/20@35
110/20@35
80/20@25
80/20@ 25
80/20@ 25
80/20@25
70/20@25

Packages
D,L,P
D,L,P
D,P
D,L,P
D,L,P
D,L
D,L,P,S
D,L,P,Y
D,P
D,P,L
D,L,P,S
D,P
D,L,P,S
D,P,S
D,L,P,S
D,P
D,L,P,S
D,L,P
D,L,P
L,J
L,J
D,L,P,Y
D,L,P,Y
D,L
D,L
L
L
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,V
D,L,P,Y
D,L,P,Y
D,L,P,V

D,L,P,Y
D,L,P
D,L,P
L,J
L,J
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,P
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,L,P,Y
D,J,L
D,J,L
J,L
D,P
D,L,P,Y
D,L,P,Y
D,L,P,V

D,L,P,Y
D,L,P,Y
D,L,P,Y

= WINDOWED PGA
= SOIC
= WINDOWED CERPAK
= SOJ
= WINDOWED CERDIP
= DICE
= HERMETIC DIP
= HERMETIC VERTICAL
DIP
= PLASTIC FLAT SIP
= PLASTIC SIP
= PLASTIC ZIP

Product Selection Guide (Continued)
SEMICXJNDUCTOR
Size
PROMs

PW.

FIFOs

Organization

Pins

Part Number

Speed ins)
tSA/CO = 25/12, 30/15
tSA/cO = 25/12, 30/15

4K
8K
8K
8K
16K
16K
16K
16K
16K
16K
64K
64K
64K
64K
64K
64K
64K
128K
128K
256K
256K
256K
256K
512K
512K
512K
512K

512 x 8-Registered
1024 x 8-Registered
1024 x 8
1024 x 8
2048 x 8-Registered
2048 x 8-Registered
2048 x 8
2048 x 8
2048 x 8
2048 x 8-C8 Power Dowo
8192 • 8-C8 Power Down
8192 x 8
8192 x 8
8192 x 8-Registered
8192 x 8
8192 x 8-Registered, Diagnostic
8192 x 8-Registered, Diagnostic
16384 x 8-CS Power Down
16384.8
32768 x 8-CS Power Down
32768 x 8
32768 x 8-Registered
32768 x 8-Address Latch
65536 • 8-FCA
65536 • 8-CE Power Down
65536 x 8-Registered
65536 x 8-FCA

24S
248
248
24
248
248
248
248
24
248
248
248
24
288
28
288
32
288
28
288
28
288
288
288
28
288
328

CY7C225
CY7C235
CY7C28I
CY7C282
CY7C245/L
CY7C245AIL
CY7C291/L
CY7C291AIL
CY7C292/L
CY7C293AIL
CY7C261
CY7C263
CY7C264
CY7C265
CY7C266
CY7C269
CY7C268
CY7C25 I
CY7C254
CY7C271
CY7C274
CY7C277
CY7C279
CY7C285
CY7C286
CY7C287
CY7C289

PALC20
PALC20
PALC20
PALC20
PLDC20
PLDC24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC28
PLDC28
PLDC28
PLDC28
MAXC28
MAXC40
MAXC40
MAXC68

16L8
16R8
16R6
16R4
18G8-Generic
22VIO-Macro Cell
22VIO-Macro Cell
200 IO-Geoeric
200 IO-Generic
20RAIO-Asynchronons
7C330-State Machine
7C331-Asynchronons
7C332-Combioatorial
7C361-State Machine
7C344-32-Macro Cell
7C343-64-Macro Cell
7C345-128-Macro Cell
7C342-128-Macro Cell

20
20
20
20
20
248
248
248
248
248
288
288
288
288
288
40/44
40/44
68

PALCI6L8/L
PALCI6R8/L
PALCI6R6/L
PALCI6R4/L
PLDCI8G8
PALC22VIO/L
PALC22VIOB
PLDC2ooIO
PLDC2ool0B
PLDC20RAIO
CY7C330
CY7C331
CY7C332
CY7C361
CY7C344
CY7C343
CY7C345
CY7C342

256
256
256
320
320
512
576
4608
4608
9216
9216
18432
18432

64 x 4-Cascadeable
64 x 4-Cascadeable
64 x 4-Cascadeable/OE
64 x 5-Cascadeable
64 x 5-Cascadeable/OE
64 • 8-Cascadeable/OE
64 x 9-Cascadeable
512 x 9-Cascadeable
512 x 9-Cascadeable
1024 x 9-Cascadeable
1024 x 9-Cascadeable
2048 x 9-Cascadeable
2048 • 9-Cascadeable

16
16
16
18
18
288
288
28
288
28
288
28
288

CY3341
CY7C401
CY7C403
CY7C402
CY7C404
CY7C408A
CY7C409A
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429

Notes:
The above specifications are for the commercial temperature range of O"C to
70"C.
Military temperature range (-55°C to + 125°C) product processed to MILSTD-883 Revision C is also available. Speed and power selections may vary
from those above.
Commercial grade product is available in plastic, CERDIP, or LCC. Military
grade product is available in CERDIP or LCC. PLCC, 80J, and SOIC
packages are available on some products.
All power supplies are VCC = 5V ± 10%.
22S stands for 22-pin 300 mil. 24S stands for 24-pin 300 mil. 28S stands for
28-pin 300 mil.
F, K and T packages are special order only.

1-4

IccllsufIccoR
(mA@ns)

Packages

90
90
90
90
100,60
6O@35
90,60
6O@35
90,60
60/15 @35
100/30
100
100
80
80/15
100
100
100/30
100
100/30
120/30
120/30
120
180
120/40
180
180

D,L,P
D,L,P
D,L,P
D,L,P
D,L,P,Q, W,8
D,L,P,Q, W,8
D,L,P,Q, W,8
D, lo P, Q, W, 8
D,P
D, lo P, Q, W, 8
D, lo P, Q, W, 8
D, loP,Q, W,8
D,P
D,L,P,Q, W,8
D,loP,Q, W
D,L,P,Q, W,8
D,L,Q,W
D,L,P,Q, W,8
D,P
D, loP,Q, W,8
D,L,P,Q, W
D,L,P,Q, W
D,loP,Q, W
D,L,P,Q,W
D,L,P,Q,W
D,L,P,Q,W
D,L,P,Q,W

fMAX, tIS, tco = 66 MHz/3 ns/12 os
tPOlSlCO = 20/12/20
tPO= 20 os
fMAx/ts/tco = 125 MHz/2 ns/12 os
tpolSlCO = TBD
tpolSlCO = TBD
tpolSlCO = TBD
tpOlSlCO = TBD

70,45
70,45
70,45
70,45
90
90,55
90
55
70
80
130
120
120
140
Icc=TBD
Icc=TBD
ICC = TBD
ICC = TBD

D,L,P,Q,V,W
D,L,P,Q, V, W
D,L,P,Q, V, W
D,L,P,Q, V, W
D,L,P,Q, V, W
D,L,P,Q, W,J
D,L,P,Q, W,J
D,loP,Q, W,J
D, loP,Q, W,J
D,L,P,Q, W,J
D,L,P,Q, W,J
D,L,P,Q, W,J
D,L,P,Q, W,J
D,L,P,Q, W,J
D,L,P,Q, W,J
D,L,P, W,J,H
D,L,P, W,J,H
L,J,G,H,R

1.2,2MHz
5, 10, IS, 25 MHz
10, 15, 25 MHz
5, 10, IS, 25 MHz
10, 15,25 MHz
15, 25, 35 MHz
15,25,35 MHz
30,40,65 ns
30,40,65 ns
30,40,65 ns
30,40,65 ns
30,40,65 ns
30,40,65 ns

45
75
75
75
75
120
120
100
100
100
100
100
100

D,P
D, loP, V
D, loP, V
D,L,P,V
D,L,P,V
D,L,P,V
D,L,P,V
D,P
D,J,L,P,V
D,P
D,J,L,P
D,P
D,J,L,P, V

tAA =30,45
tAA =30,45
tSA/CO = 25/12, 35/15

tSA/CO = 18/12
tAA =35,50
tAA = 25, 30, 35, 50
tAA =35,50
tAA = 25, 30, 35, 50
tAA = 35, 40, 45, 55
tAA = 35, 40, 45,55
tAA = 35, 40, 45, 55
tSA/CO=4O/2O
tAA =55
tSA/CO = 40/20, 50/25
tSA/CO = 40/20, 50/25
tAA = 45, 55, 65
tAA = 45, 55, 65
tAA = 45, 55, 65
tAA=45
tSA/CO = 40/20
tAA =45
tAAICAA = 65/30
tAA =65
tSA/CO = 55/20
tAAICA = 75/30
tpo=20
tS/CO= 15/12
tpOlSlCO = 20/20/15
tpolSlCO = 20/20/15
tPO/S/CO = 12/12/10
tpo/S/CO = 25/15/15
tpolSlCO= 15/10/10
tpO/S/CO = 25/15/15
tpO/S/CO= 15/12/10
tPO/S/CO = 20/10/20

Package Code:
B = PLASTIC PIN GRID
ARRAY
D = CERDIP
F = FLATPAK
G = PIN GRID ARRAY
H = WINDOWED
HERMETIC LCC
J = PLCC
K = CERPAK
L= LCC
P = PLASTIC
Q = WINDOWED LCC

WINDOWED PGA
SOIC
WINDOWEDCERPAK
SOJ
WINDOWED CERDIP
DICE
HERMETIC DIP
HERMETIC VERTICAL
DIP
PF = PLASTIC FLAT SIP
PS = PLASTIC SIP
PZ = PLASTIC ZIP

R
S
T
V
W
X
HD
HV

=
=
=
=
=
=
=
=

Product Selection Guide (Continued)
SEMICONDUCTOR

Size
WGIC

RISC

IU
FPC
FPP
FPU

CMU
CMU-MP
Modules

ECL
SRAMs

ECL
PLDs

32K
256K
256K
512K
512K
1M
1M
1M
1M
1M
1M
1M
1M
2M
2M
2M
4M
4M
4M
IK
IK
IK
IK
4K
4K
4K
4K
32x64
32x64
32x64
32x64
32x32
32 x 32
32x32
32 x 32

Organization

Pins

2901-4 Bit Slice
2901-4 Bit Slice
4 x 2901-16 Bit Slice
29116-16 Bit Controller
29116-16 Bit Controller
29117 -16 Bit Controller
2909-Sequencer
291 I-Sequencer
2909-Sequencer
29 II-Sequencer
291O-Controller (17 Word Slack)
291O-Controller(9 Word Stack)
16x 16-Multiplier
16 x I6-Multiplier
16x 16-Multiplier/Accumulator

40
40
64
52
52
68
28
20
28
20
40
40
64
64
64

SPARC 32 Bit Integer Unit
Floating-Point Controller
Floating-Point Processor
Floating-Point Unit
(Controller & Processor)
Cache Controlled Memory
Management Unit
Cache Controller and Multiprocessing
Memory Management Unit
IK x 32--SRAM
16K x 16--SRAM (JEDEC)
16Kx 16--SRAM
16K x 32--SRAM
16K x 32--SRAM Separate I/O
128K x 8--SRAM (JEDEC)
128K x 8--SRAM (JEDEC)
128K x 8-SRAM
64K x 16--SRAM (JEDEC)
64Kx 16--SRAM
64Kx 16--SRAM
64K x 16--SRAM (JEDEC)
64K x 16--SRAM
64K x 32--SRAM
64K x 32--SRAM
64K x 32--SRAM
512K x 8--SRAM
512Kx8--SRAM
256K x 16--SRAM
256K x 4--10K/1O KH
256K x 4--1OK/1O KH
256K x 4--IOOK
256K x 4--IOOK
1024K x 4--1OK/1O KH
I024K x 4--1OK/1O KH
1024K x 4--IOOK
1024K x 4--IOOK
16P8-IOKH
16P8-IOKH
16P8-IOOK
16P8-IOOK
16P4--IOKH
16P4--IOKH
16P4--IOOK
16P4--IOOK

Part Number

Speed (os)

Icc!IsslICCDR
(mA@ns)

Packages

!eLK = 23, 31
C
tCLK=30, 40
!eLK = 35, 45, 53, 79, 100
tCLK = 35, 45, 53, 79, 100
!eLK = 35, 45, 53, 79, 100
!eLK = 30, 40
tCLK= 30, 40
A
A
tCLK =40,50,93
A
tMC = 38, 45, 55, 75
tMC = 38, 45, 55, 75
tMC = 45, 55, 65, 75

70
140
60
145
145
145
55
55
70
70
100
170
lOO@ IOMHz
lOO@ 10 MHz
lOO@ IOMHz

J
D,L,G,J
L,G, J
D,L,P,J
D,L,P,J
D,P
D,P
D,L,P,J
D,L,P,J
D,L,P,G,J
D,L,P,G,J
D,L,P,G,J

208
281
208
299/144

CY7C901
CY2901
CY7C9101
CY7C9115
CY7C9116
CY7C9117
CY7C909
CY7C911
CY2909
CY2911
CY7C910
CY2910
CY7C516
CY7C517
CY7C51O
CY7C601
CY7C608
CY7C609
CY7C602

tCYC = 40, 33, 25 MHz
!eYC = 33, 25 MHz
tCYC=33,25 MHz
tCYc= 40, 33, 25 MHz

650
600
600
650

G,B
G
G
G,K

207/196

CY7C604

tcyc = 40, 33, 25 MHz

650

G,K

207/196

CY7C605

tCYC = 40, 33, 25 MHz

650

G,K

56
40
36
64
88
32
32
30
40
40
40
40
40
60
64
64
36
36
48
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24

CYMI804
CYMI610
CYMI611
CYMI821
CYMI822
CYMI420
CYMI421
CYMI422
CYMI620
CYMI621
CYMI622
CYMI623
CYMI626
CYMI830
CYMI831
CYMI832
CYMI460
CYMI461
CYMI641
CYIOE422
CYIOE422L
CYlOOE422
CYlOOE422L
CYIOE474
CYIOE474L
CYlOOE474
CY100E474L

tAA = 15,17
tAA = 25, 35, 45, 50
tAA = 25, 30, 35, 45
tAA = 25, 35, 45
tAA = 25, 30, 35, 45
tAA =45,55
tAA =70,85
tAA = 35, 45, 55
tAA=45,55
tAA = 25, 30, 35, 45
tAA = 35, 45, S5
tAA = 70, 85, 100
tAA = 30, 35, 45
tAA = 35, 45, S5
tAA = 30, 35, 45
tAA = 35, 45, 55
tAA = 45, 55, 70
tAA =70,85,100
tAA = 35, 45, 55

720@ 15
330@25
330@25
720@25
720@25
210@4S
120@70
220@3S
34O@45
1250@25
4OO@3S
240@70
34O@30
550@45
670@30
980@35
450@45
120@70
1760@35

tAA=3,5
tAA=5,7
tAA =3,5
tAA=5,7
tAA=3,5
tAA=5,7
tAA=3,5
tAA =5,7
tAA=3,4
tAA=6
tAA=3,4
tAA=6
tAA =2,5,4
tAA=6
tAA =2,5,4
tAA=6

205
150
200
150
275
190
275
190
240
150
240
150
220
150
220
150

PZ
HD
HV
PZ
HV
HD
HD
PF,PS
HD
HD
HV
HD
PF,PS
HD
PZ
PZ
PF,PS
PF,PS
HD
D,L
D,L
D,L
D,L
D,L
D,L
D,L
D,L

CYIOE301
CYIOE30lL
CYlOOE301
CYlOOE30lL
CYIOE302
CYIOE302L
CYlOOE302
CYlOOE302L

Notes:
The above specifications are for the commercial temperature range of O"C to
70"C.
Military temperature range (- 55'C to + 125'C) product processed to MILSTD-883 Revision C is also available. Speed and power selections may vary
from those above.
Commercial grade product is available in plastic, CERDIP, or LCC. Military
grade product is available in CERDIP or LCC. PLCC, SOl, and SOIC
packages are available on some products.
All power supplies are Vcc = 5V ± 10%.
22S stands for 22-pin 300 mil. 24S stands for 24-pin 300 mil. 28S stands for
28-pin 300 mil.
F, K and T packages are special order only.

1-5

Package Code:
B = PLASTIC PIN GRID
ARRAY
D = CERDIP
F = FLATPAK
G = PIN GRID ARRAY
H = WINDOWED
HERMETIC LCC
J = PLCC
K = CERPAK
L= LCC
P = PLASTIC
Q = WINDOWED LCC

R
S
T
V
W
X
HD
HV

D,L,P,J
D,P
D,L,P,J

D,L
D,P,L,J
D,L
D,P,L,J
D,L
D,P,L,J
D,L
D,P,L,J

= WINDOWED PGA
= SOIC
= WINDOWEDCERPAK
= SOJ
= WINDOWED CERDIP
= DICE
= HERMETIC DIP
= HERMETIC VERTICAL
DIP
PF = PLASTIC FLAT SIP
PS = PLASTIC SIP
PZ = PLASTIC ZIP

II

&r~====================
Ordering Information
Specific ordering codes are indicated in the detailed data sheets. In general, the codes for all products
(except modules) follow the format below:
PAL &: PlD
PREFIX

DEVICE

'PAL C'
PAL C
PAL C
PlD C
CY
CY
CY

16R8
16R8
22Vl0
20Gl0
7C330
10E302
100E302

RAM. PROM. 1'11'0. J-lP • ECl
PREFIX
DEVICE

I"""'CY""
CY
CY
CY
CY
CY

7C 1 28
7C245
7C404
7C901
10E415
100E415

sumx
' -25 P
l-35 P
-25 W
-25 W
-33 P
-2.50
-2.50

FAMilY
' PAL 20
lOW POWER PAL 20
PAL 24 VARIABLE PRODUCT TERMS
GENERIC PlD 24
PlD SYNCHRONOUS STATE MACHINE
10K ECl PlD
lOOK ECl PlD

C
C
C
C
C
C
C

sumx
, -45 0 M B
l-35 P C
-250M B
-23 P C

-3
-3

0 C
I' C

I

t

FAMilY
, SRAM
PROM
1'11'0
J-lP
10K ECl SRAM
lOOK ECl SRAM
PROCESSING
B = HI REl Mil STD 883 C
FOR MILITARY· PRODUCT
= lEVEL 2 PROCESSING I'OR COMMERCIAL PRODUCT
TEMPERATURE RANGE
C = COMMERCIAL (0<><: TO 70<><:)
M=MllITARY(-550C TO +125<><:)
PACKAGE
D=CERDIP
I' =l'lATPAK
G = PIN GRID ARRAY (PGA)
J =PlCC
K = CERPAK (GLASS SEALED FLAT PACKAGE)
l = lEADlESS CHIP CARRIER
P=PLASTIC
Q = WINDOWED lEADlESS CHIP CARRIER
S = SOIC (GUll WING)
T = WINDOWED CERPAK
V=SOIC (J lEAD)
W= WINDOWED CERDIP
X DICE (WAFFLE PACK)

=

' - - - - SPEED (ns or MHz)
......- - - l = lOW POWER OPTION
A. B. C = REVISION lEVEL

i.e. CY7C128-35PC, PALC16R8L-25PC

Cypress FSCM # 65786

1-6

0018-1

~~NDU~================================================================
Ordering Information (Continued)
The codes for module products follow the format below:
PREFIX

DEVICE

SUFFIX

1001

H 0-120 M B

r--1
CYM

IL ,"0""''''

B = MILITARY STANDARD BB3
= STANDARD

TEMPERATURE RANGE
C = OOC TO 70°C
I = -40OC TO B50C
M= -550C TO 125°C
L..-_ _

SPEED

' - - - - - CONFIGURATION
0= DUAL-IN-LINE
G = PIN GRID ARRAY
Q= QUAD-IN-L1NE
S = SINGLE-IN-L1NE
V = VERTICAL DIP
Z = ZIGZAG-IN-L1NE
' - - - - - - TYPE
H=HERMETIC
P = PLASTIC

Cypress FSCM # 65786

1-7

0018-2

II

Product Line Cross Reference

SEMICONDUCI'OR

CYPRESS
2147-35C
2147-45C
2147-4SC
2147-45M+
2147-55C

CYPRESS
7C147-35C
2147-35C
7C147-4SC
7CI47-45M+
2147-4SC

CYPRml
2911AM
3341-2C
3341-2M
334IC
3341M

CYPRESS
7C9I1-40M
7C401-5C+
7C401-IOM
3341-2C
3341-2M

CYPRESS
7C150-25C
7C15(}'35C
7C15(}'35M
7C167-35C
7C167-4SM

CYPRESS
7C15(}'15C
7C15(}'25C
7C15(}'25M
7C167-25C
7CI67-35M+

CYPRESS
7C251-65M
7C253-65M
7C254-45C
7C254-55C
7C2S4-65C

CYPRESS
7C251-55M
7C253-5SM
7C254-45C
7C254-45C
7C254-55C

2147-55M
2148-35C
2148-35C
2148-35M
Z148-45C
2148-45C

2147-45M
21L48-35C
7C148-35C
7C148-35M
ZI48-35C
21L48-45C

54S189M
6116-35C
6116-45C
6116-4SM
6116-55C
6116-55M

27S03M
6116-3SC
6116-35C
6116-4SM
6116-4SC
6116-4SM

7C168-35C
7C168-45M
7C169-35C
7C169-40M
7C17(}'35C
7C170-45C

7C168-25C
7CI68-35M+
7C169-2SC
7CI69-35M+
7CI7(}'25C
7CI7(}'3SC

7C254-65M
7C261-35C
7C261-45C
7C261-45M
7C261-55C
7CZ61-55M

7C254-55M
7C261-35C
7C261-35C
7C261-45M
7C261-45C
7C261-45M

2148-45M
ZI48-4SM +
Z148-55C
Z148-55C
Z148-5SM
Z149-35C

2148-35M
7CI48-45M+
Z148-45C
ZIL48-55C
Z148-45M
ZIL49-35C

74S189C
7CIZ2-Z5C
7CI22-35C
7CI22-35M
7CI23-12C
7C128-35C

27S03C
7CI22-15C+
7CIZZ-25C
7CI2Z-2SM
7C123-7C
7C128-25C

7CI7a-45M
7C171-35C
7CI7I-35M
7CI7I-45M
7CI72-35C
7CI72-45M

7CI7(}'35M
7CI7I-Z5C
7CI7I-35M
7CI7I-35M+
7CI72-25C
7CI72-35M+

7C263-35C
7C263-45C
7CZ63-45M
7C263-55C
7C263-55M
7C264-35C

7C263-35C
7C263-35C
7C263-45M
7C263-4SC
7C263-45M
7C264-35C

2149-35C
2149-3SM
2149-45C
2149-45M
2149-45M
2149-55C

7C149-35C
7C149-35M
21L49-45C
2149-35M
7C149-45M
2149-45C

7CI28-35M
7C128-45C
7C128-45M
7C128-55C
7C128-55M
7C13a-45C

7C128-35M
7C128-35C
7CI28-35M+
7CI28-45C+
7CI28-45M+
7CI3(}'35C

7C186L-45M
7C189-25C
7C19(}'25C
7C191-45M
7C192-45M
7C194-35C

7C186-45M
7CI89-15C+
7CI90-15C+
7C191-3SM
7C192-35M
7C194-25C

7C264-45C
7C264-45M
7C264-55C
7C264-55M
7C268-5OC
7C268-6OC

7C264-35C
7C264-45M
7C264-45C
7C264-4SM
7C268-4OC+
7C268-5OC

2149-55C
2149-S5M
21L48-35C
21L48-45C
21L48-45C
21L48-5SC

21L49-55C
2149-45M
7C148-35C
21L48-35C
7C148-45C
21L48-45C

7CI3a-45M
7CI3(}'55C
7CI3(}'55M
7CI3I-45C
7CI3I-45M
7CI3I-55C

7CI3a-45M
7C13a-45C
7C130-45M
7CI3I-35C
7C131-45M
7CI3I-45C

7C194-45C
7C194-45M
7C196-35C
7C196-35M
7C196-45C
7C197-35C

7CI94-35C+
7C194-35M
7C196-25C
7C196-35M
7CI96-35C+
7C197-25C

7C268-60M
7C269-5OC
7C269-6OC
7C269-60M
7C281-45C
7C282-45C

7C268-S0M+
7C269-4OC+
7C269-5OC
7C269-50M+
7C281-3OC
7C282-3OC+

21L49-35C
21L49-45C
21L49-45C
21L49-55C
27S03AC
27S03AM

7C149-25C
21L49-35C
7C149-45C
21L49-45C
7C189-25C
7C189-25M

7CI3I-5SM
7CI32-3SC
7C132-45C
7C132-55C
7C132-55M
7C136-35C

7CI3I-45M
7CI32-35C
7C132-3SC
7C132-45C
7C132-45M
7C136-3SC

7C197-4SC
7C197-45M
7C198-45C
7C198-55C
7C198-55M
7C199-45C

7CI97-35C+
7C197-35M
7C198-3SC
7CI98-45C+
7C198-45M
7C199-3SC

7C282-45M
7C291-35C
7C291-35M
7C291-SOC
7C291-50M
7C29IA-35C

7C282-45M
7C291-25C+
7C291-3SM
7C291-35C
7C291-35M
7C291AL-35C

27S03C
27S03C
27S03M
27S03M
27S07AC
27S07AM

27S03AC
74S189C
27S03AM
S4S189M
7CI9a-2SC
7CI9a-25M

7C136-45C
7C136-S5C
7C136-55M
7CI4a-3SC
7CI4a-45C
7CI4a-S5C

7C136-3SC
7C136-45C
7C136-45M
7CI4a-2SC
7CI4a-35C
7CI4a-45C

7CI99-SSC
7CI99-55M
7C225-3OC
7C225-3OM
7C225-40C
7C225-40M

7CI99-4SC+
7C199-45M
7C225-25C
7C225-25M
7C225-3OC
7C225-3SM

7C29IA-35M
7C29IA-5OC
7C291A-50M
7C291AL-35C
7C29IAL-SOC
7C291L-35C

7C291A-30M
7C291AL-50C
7C29IA-35M
7C291A-25C +
7C291AL-35C
7C291-35C+

27S07C
27S07M
27S07M
290ICC
290ICM
2909AC

27S07AC
27S07AM
7CI90-25M
7C901-3IC
7C901-32M
7C909-4OC

7C141-35C
7C141-4SC
7C141-55C
7C147-3SC
7CI47-35M+
7C147-45C

7C141-2SC
7C141-3SC
7C141-4SC
7CI47-2SC+
7CI47-35M+
7C147-35C

7C235-40C
7C245-35C
7C245-45C
7C245-45M
7C245A-2SC
7C245A-3SC

7C235-3OC
7C24S-25C
7C24S-3SC
7C24S-35M
7C245A-18C
7C245AL-35C

7C291L-SOC
7C292-35C
7C292-50C
7C292L-35C
7C292L-5OC
7C293A-35C

7C291L-35C
7C292-25C+
7C292-3SC
7C292-35C+
7C292L-35C
7C293AL-35C

2909AM
2910AC
2910AM
2910C
2910M
2911AC

7C909-40M
7C91(}'5OC
7C91(}'5IM
2910AC
2910AM
7C911-4OC

7C148-2SC
7C148-35C
7CI48-45C
7C149-35C
7C149-45C
7C149-45M

7C148-25C
7CI48-25C+
7C148-35C
7CI49-25C+
7C149-35C
7C149-35M

7C245A-35M
7C245AL-35C
7C245L-3SC
7C245L-45C
7C251-5SC
7C251-65C

7C245A-25M
7C245A-2SC +
7C245-35C+
7C24SL-3SC
7C2SI-45C
7C251-55C

7C293A-35M
7C293A-50C
7C293A-50M
7C293AL-35C
7C293AL-5OC
7C401-IOC

7C293A-30M
7C293AL-SOC
7C293A-35M
7C293A-2OC +
7C293AL-3SC
7C401-15C

Note: Unless otherwtSe noted. product meets all performance specs and IS WIthin 10 mA on Icc and 5 mA on ISH;
+ = meets all performance specs but may not meet Icc or ISH;
• = meets all performance specs except 2V data retention-may not meet Icc or ISH;
- = functionally equivalent

1-8

SEMICONDUCI'OR

Product Line Cross Reference (Continued)

CYPRESS
7C401-IOM
7C401-5C
7C402-IOC
7C402-10M
7C402-SC

CYPRESS
7C401-15M
7C401-IOC
7C402-15C
7C402-15M
7C402-IOC

CYPRESS
7C517-45C
7C517-55C
7C5I7-55M
7C517-75C
7C517-7SM

CYPRESS
7C517-3SC
7C517-45C
7C5I7-42M
7C517-55C
7C517-55M

CYPRESS
PALCI6RS-35C
PALCI6RS-40M
PALCI6RSL-35C
PALC22V10-35C
PALC22VI0-40M

CYPRESS
PALCI6RS-25C
PALCI6RS-30M
PALCI6RSL-25C
PALC22VI0-25C
PALC22VI0-30M

AMD
216S-45M
216S-55C
216S-55M
2168-7OC
216S-70M

CYPRESS
7C16S-45M
7C16S-45C
7C16S-45M
7CI6S-45C
7C16S-45M

7C403-IOC
7C403-IOM
7C403-15C
7C403-15M
7C404-IOC
7C404-IOM

7C403-15C
7C403-15M
7C403-25C
7C403-25M
7C404-15C
7C404-ISM

7C901-31C
7C901-32M
7C909-4OC
7C909-40M
7C910-5OC
7C91O-5IM

7C901-23C+
7C901-27M
7C909-3OC
7C909-30M
7C91O-4OC
7C9I0-46M

PALC22VIOL-25C
PALC22VIOL-35C
PLDC20GIO-35C
PLDC20GIO-40M

PALC22V10-25C
PALC22VI0L-25C
PLDC20G10-25C
PLDC2OGIO-30M

AMD

CYPRESS

2169-4OC
2169-5OC
2169-50M
2169-7OC
2169-70M
21L47-45C

7C169-40C
7C169-4OC
7C169-40M
7C169-4OC
7C169-40M
7C147-45C

7C404-15C
7C404-15M
7C40S-15C
7C40S-15M
7C40S-25C
7C409-15C

7C404-25C
7C404-25M
7C40S-25C
7C40S-25M
7C40S-35C
7C409-25C

7C910-93C
7C910-99M
7C9101-4OC
7C9101-45M
7C911-4OC
7C911-40M

7C91O-5OC
7C910-51M
7C9101-3OC
7C9101-35M
7C911-3OC
7C911-30M

PREFIX:Am
PREFIX:SN
SUFFIX:B
SUFFIX:D
SUFFIX:F
SUFFIX:L

PREFIX:CY
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:F
SUFFIX:L

21L47-55C
21L47-7OC
21L4S-45C
21L4S-55C
21L4S-70C
21L49-45C

7C147-45C
7C147-45C
21L48-45C
21L48-55C
21L48-55C
21L49-45C

7C409-15M
7C409-25C
7C42O-4OC
7C420-40M
7C420-65C
7C420-65M

7C409-25M
7C409-35C
7C420-3OC
7C420-30M
7C420-4OC
7C420-40M

9122-25C
9122-25C
9122-35C
9122-35C
9122-45C
91L22-25C

7C122-15C
91L22-25C
9122-25C
91L22-35C
93L422C
7C122-25C

SUFFIX:P
2130-100c
2130-12OC
2130-7OC
2147-35C
2147-45C

SUFFIX:P
7C130-55C
7C130-55C
7C130-55C
2147-35C
2147-4SC

21L49-55C
21L49-70C
27C191-25C
27C191-35C
27C191-35C
27C191-35C

21L49-55C
21L49-55C
7C292A-25C
7C291A-25C +
7C291A-35C
7C292A-35C

7C421-4OC
7C421-40M
7C421-6SC
7C421-6SM
7C424-4OC
7C424-40M

7C421-3OC
7C421-30M
7C421-40C
7C421-40M
7C424-3OC
7C424-30M

9IL22-35C
91L22-45C
93422AC
93422AC
93422AM
93422C

7C122-35C
93L422AC
7C122-35C
9122-35C
7C122-35M
93L422AC

2147-4SM
2147-55C
2147-55M
2147-7OC
2147-70M
214S-35C

2147-45M
2147-5SC
2147-55M
2147-55C
2147-5SM
214S-35C

27C191-3SC
27C191-35M
27C191-45M
27C291-25C
27C291-35C
27C291-45M

7C292AL-35C
7C292A-30M
7C291A-45M
7C291A-25C
7C291AL-35C
7C291A-35M

7C424-65C
7C424-65M
7C425-4OC
7C425-40M
7C425-6SC
7C425-65M

7C424-4OC
7C424-40M
7C42S-30C
7C425-30M
7C425-4OC
7C425-40M

93422M
93422M
93L422AC
93L422AC
93L422AM
93L422C

93422AM
93L422AM
7C122-35C
91L22-45C
7C122-35M
93L422AC

214S-35M
214S-45C
214S-45M
214S-SSC
214S-55M
214S-7OC

214S-35M
214S-4SC
214S-45M
214S-55C
2148-55M
2148-55C

27C291A-30M
27LS03C
27LS03M
27LS07C
27LS191C
27LS291C

7C291A-30M
27LS03C
27LS03M+
27S07C+
7C292-35C
7C291-35C

7C42S-4OC
7C42S-40M
7C42S-65C
7C42S-65M
7C429-4OC
7C429-40M

7C42S-3OC
7C42S-30M
7C42S-40C
7C42S-40M
7C429-3OC
7C429-30M

93L422M
PALCI6LS-25C
PALCI6LS-30M
PALCI6LS-3SC
PALCI6LS-40M
PALCI6LSL-35C

93L422AM
PALCI6LSL-25C
PALCI6LS-20M
PALCI6LS-25C
PALCI6LS-30M
PALCI6LSL-25C

214S-70M
2149-35C
2149-45C
2149-4SM
2149-55C
2149-55M

214S-55M
2149-35C
2149-45C
2149-45M
2149-55C
2149-55M

27LS291M
27PSISIAC
27PS1S1AM
27PS1S1C
27PS1S1M
27PS191AC

7C291-35M
7C2S2-45C
7C2S2-45M+
7C2S2-45C
7C2S2-45M+
7C292-5OC

7C429-65C
7C429-65M
7CS10-55C
7C510-65C
7C510-65M
7CS10-75C

7C429-40C
7C429-40M
7CS10-45C
7C510-55C
7C510-55M
7C510-6SC

PALCI6R4-25C
PALCI6R4-30M
PALCI6R4-35C
PALCI6R4-40M
PALCI6R4L-35C
PALCI6R6-25C

PALCI6R4L-25C
PALCI6R4-20M
PALCI6R4-25C
PALCI6R4-30M
PALCI6R4L-25C
PALC16R6L-25C

2149-7OC
2149-70M
2167-35C
2167-3SM
2167-45C
2167-45M

2149-55C
2149-55M
7C167-35C
7C167-3SM
7C167-45C
7C167-4SM

27PS191AM
27PS191C
27PS191M
27PS2S1AC
27PS2S1AM
27PS2S1C

7C292-50M+
7C292-SOC
7C292-50M+
7C2SI-45C
7C2SI-45M+
7C2SI-4SC

7C510-75M
7C516-45C
7C516-55C
7C516-55M
7C516-75C
7C516-75M

7CS10-65M
7C516-3SC
7C516-45C
7CSI6-42M
7C516-55C
7C516-5SM

PALCI6R6-30M
PALCI6R6-35C
PALCI6R6-40M
PALCI6R6L-35C
PALCI6RS-25C
PALCI6RS-30M

PALCI6R6-20M
PALCI6R6-25C
PALCI6R6-30M
PALC16R6L-25C
PALCI6RSL-25C
PALCI6RS-20M

2167-55C
2167-55M
2167-7OC
2167-70M
216S-35C
216S-45C

7C167-45C
7C167-45M
7C167-45C
7C167-45M
7C16S-35C
7CI6S-4SC

27PS2S1M
27PS291AC
27PS291AM
27PS291C
27PS291M
27S03AC

7C2SI-45M+
7C291-5OC
7C291-50M+
7C291-5OC
7C291-50M+
27S03AC

Note: Unless otherwise noted, product meets all performance specs and IS within 10 mA on Icc and S rnA on ISB ;
+ = meets all performance specs but may not meet ICC or ISB ;
• = meets all performance specs except 2V data retention-may not meet Icc or ISB ;
- = functionally equivalent

1-9

II

Product Line Cross Reference (Continued)
SEMICONDUCTOR

AMD
27S03AM
27S03C
27S03M
27S07AC
27S07AM

CYPRESS
27S03AM
27S03C
27S03M
27S07AC
27S07AM

290IBC
290IBM
290ICC
290ICM
2909AC

CYPRESS
290ICC
290ICM
290ICC
290ICM
2909AC

AMD
29L5lOM
29L5l6C
29L516M
29L517C
29L5l7M

CYPRESS
7C51()'75M
7C5l6·75C
7C516-75M
7C5l7·75C
7C5l7·75M

99C165·55C
99C165·55M
99C165·7OC
99C165·70M
99C641·25C

CYPRFSS
7CI66-45C+
7CI66·45M+
7CI66-45C+
7CI66-45M+
7C187·25C

27S07C
27S07M
27S181AC
27Sl8lAM
27Sl8lC
27S18lM

27S07C
27S07M
7C282·3OC
7C282-45M
7C282-45C
7C282-45M

2909AM
2909C
2909M
291()'IC
291()'IM
2910AC

2909AM
2909AC
2909M
29lOC
2910M
2910AC

334lC
334lM
54S189M
74Sl89C
9122.25C
9122-35C

334lC
334lM
54S189M
74Sl89C
9122·25C
9122·35C

99C641·35C
99C64l-45C
99C64l-45M
99C64I·55C
99C641·55M
99C641·7OC

7C187·35C
7C187-45C
7C187-45M
7C187-45C
7C187-45M
7C187-45C

27Sl9lAC
27Sl91AM
27Sl9lC
27Sl9lM
27Sl9lSAC
27S25AC

7C292·35C
7C292·50M
7C292·5OC
7C292·50M
7C292A·2OC
7C225·3OC

2910AM
2910C
29lOM
29116AC
29116AM
29116C

2910AM
2910C
29lOM
7C9116AC
7C9116AM
7C9116AC

9122·35M
9l28·100c
9l28·l20M
9l28-l5OC
9l28·l50M
9128·200C

7C122·35M
6116·55C
6116-55M
6116·55C
6116·55M
6116-55C

99C64I·70M
99C68·35C
99C68-45C
99C68-45M
99C68·55C
99C68·55M

7C187-45M
7C168·35C
7CI68·45C·
7C168-45M'
7C168·45C'
7C168·45M'

27S25AM
27S25C
27S25M
27S25SAC
27S25SAM
27S28lAC

7C225·35M
7C225-40C
7C225-40M
7C225·25C
7Cm·35M
7C281·3OC

29116M
29117C
29117M
2911AC
2911AM
2911C

7C9116AM
7C9117AC
7C9117AM
2911AC
2911AM
2911AC

9l28·2---- DO

Ao

Vee

A,

A6

A2

A7

A3

As

Ao

Ag

As

A,o

DO

A"

WE

01

GND

CE
00'3-2

WE

0013-1

Selection Guide (For higher performance and lower power refer to CY7C147 data sheet.)
Maximum Access Time (ns)
Maximum Operating
Current (rnA)

Commercial

Maximum Standby
Current (rnA)

Commercial

2147·35

2147·45

35

45

55

125

125

125

140

140

25

25

25

25

Military
25

Military

2-1

2147·55

•

~
CY2147
~~~====================
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C
Static Discharge Voltage .................•... > 200 IV
(Per MIL-STD-883 Method 3015)
Ambient Temperature with
Power Applied .......•.....•...... - 55°C to + 125°C

Latchup Current .......•......•.....••.... > 200 mA

Supply Voltage to Ground Potential
(pin 18 to Pin 9) ..................... -0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State. ~ ............•....... -0.5V to +7.0V
DC Input Voltage •...........•...... - 3.0V to + 7.0V
Output Current into Outputs (Low) ..•.......... 20 mA

Ambient
Temperature

Range
Commercial
Military[S)

Vee

O"Cto +70"C

5V ±10%

- 55°C to + 125°C

5V ±10%

Electrical Characteristics Over Operating Range[4]
Parameters

Description
Output HIGH Voltage
Output LOW Voltage

VOH
VOL
VIH

Min.
2.4

Max.

Vee

Test Conditions

2.0
-3.0
-10

Vee
0.8

V

+10

/LA

-50

+50

/LA

-350

mA

125
140

rnA

= Min.,IOH = -4.0mA
Vee = Min., IOL = 12.0 mA

VIL

Input HIGH Voltage
Input LOW Voltage

IIX

Input Load Current

GND";; VI";; Vee

Ioz

Output Leakage Current

GND";; Vo";; Vee
Output Disabled

los

Output Short Circuit
Current[l)

Vee

lee

Vee Operating Supply
Current

Vee = Max.
lOUT = OmA

Commercial

ISB

Automatic CE(2)
Power Down Current

Max. Vee,
CE:2: VIH

Commercial
Military

0.4

= Max., VOUT = GND
Military

Units
V
V
V

25

mA

25

Capacitance [3]
Description

Parameters

Test Conditions
TA = 25°C, f
Vee = S.OV

Input Capacitance
Output Capacitance

CIN
CoUT

Notes:
1. Duration of the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vcc on the Ct! input is required to keep the
device deselected during Vee power-up, otherwise ISB will exceed
values given.

= I MHz

Max.

Units

5
6

pF

3. Tested initially and after any design or process changes that may

affect these parameters.
4. See the last page of this specification for Group A subgroup testing

information.

S. TA is the "instant on" case temperature.

AC Test Loads and Waveforms
Rl329U

Rl329!!

5Vo-------~~~

5Vo-------~~_,

OUTPUT 0-----........-------1

OUTPUT 0-----_----4

INCLUDING
JIG AND
SCOPE

1

30 pF

R2

20211

6pF
INCLUOINl
JIG AND
SCOPE
':"

INPUT PULSES

"'~

R2

202!!

GND

llWo911'10

<:Sns

I.--

0013-3

Figure 1&

Figure Ib

Equivalent to:
THEVENIN EQUIVALENT
126!J
DUTPUT~l.90V

0013-4

Figure 2

0013-5

2-2

~

CY2147

~~~DUcroR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Switching Characteristics Over Operating Range[4, 6)
Parameters

2147-35

Description

Min.

2147-45

Max.

Min.

2147-55

Max.

Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

45

35
35

tOHA

Data Hold from Address Change

tACE

CE LOW to Data Valid

tLzCE

CE LOW to Low Z[S]

tHzCE

c:E HIGH to High Z[7, s]

tpu

CE LOW to Power Up

tpo

CE HIGH to Power Down

55

ns

45

5

55

5
35

5

ns

45

5

55

5
30

ns
30

ns
ns

0

0
20

ns

5
30

0

ns

20

20

ns

WRITE CYCLE[9]
twc

Write Cycle Time

35

45

55

ns

tscE

CE LOW to Write End

35

45

45

ns

tAW

Address Set-up to Write End

35

45

45

ns

tRA

Address Hold from Write End

0

0

10

ns

tSA

Address Set-up to Write Start

0

0

0

ns

tpwE

WE Pulse Width

20

25

25

ns

tso

Data Set-up to Write End

20

25

25

ns

tHO

Data Hold from Write End

10

10

10

ns

tLZWE

WE HIGH to Low Z[S]

0

0

0

tHZWE

WE LOW to High Z[7. s]

0

20

0

ns

0

25

25

ns

Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified Im/IoH and 30 pF load capacitance.
7. tHZCE and tHZWE are tested with CL = 5 pF as in Figure lb. Transition is measured ± 500 m V from steady state voltage.
8. At any given temperature and voltage condition, tHZ is less than tLZ
for all devices.

9. The internal write time of the memory is defined by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
10. WE is HIGH for read cycle.
II. Device is continuously selected, CE = VIL.
12. Address valid prior to or coincident with CE transition LOW.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

-*_

~
ADDRESS~--"'Aizmi-"

-----------t.e------------Il

tOHA~
CATAOUT

PREVIOUS DATA

VAUO

_________DA_T_A_V_AL_'_D_ _ _ _ _ _ __
0013-6

Read Cycle No.2 (Notes 10, 12)

toe

--\tACE

~tHze'~1

tLze.~

-

1

Vee _ _ _ _ _
SUPPLY

CURRENT

DATA VALID

I

..u

HIGH
IMPEDANCE

HIGH IMPEDANCE

CATAOUT

J

I---tpo

~,cc

-1\--'88

-

_

0013-7

2-3

II

~
CY2147
~~~~=============================================================
Switching Waveforms (Continued)

Write Cycle No.1 (WE Controlled) (Note 9)

ADDRESS

""

---..

-

'."

~ l\{
i----

'1111, 'jllllllll,

·A.

tHA-

I----t"'.~

~A

\\\'

..,

I

DATA IN

"'::1

-'"""::::j
DATA OUT

I

DATA-CN VALID

)

DATA UNDEFINED

~tLZWEI
HIGH IMPEDANCE

(

0013-8

Write Cycle No.2 (CE Controlled) (Note 9)

ADDRESS

+tI+t1f-++- 1/oo

>+++++1+---1/0,

>+tI#--1/03

>+tI""'--l/o.
>wO'----I/OS

CE-_--dl'"'
WE -t--.--dlL~

L.-+i~~----I/07

1iE---1~~;;;;;;;;::I--'

0087-1

Selection Guide
CY6116-35
CY6117-35
Maximum Access Time (ns)

CY6116-45
CY6117-45

CY6116-55
CY6117-55

35

45

55

Maximum Operating
Current (rnA)

Commercial

120

120

120

Military

130

130

130

Maximum Standby
Current (rnA)

Commercial

20

20

20

Military

20

20

20

2-12

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -6SoC to + ISO"C

Static Discharge Voltage ..................... >2001V
(Per MIL-STD-883 Method 301S)

Ambient Temperature with
Power Applied .................... - SsoC to + 12SoC

Latch-up Current .......................... > 200 rnA

Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -O.SV to +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SVto +7.0V

Range

DC Input Voltage ................... -3.0V to +7.0V

Commercial

Output Current into Outputs (Low) ............. 20 rnA

Military 141

Ambient
Temperature

Vee

O"C to +70"C

SV ±1O%

- SsoC to + 12SoC

SV ±1O%

Electrical Characteristics Over Operating Range l3 ]
Parameters

Description

CY6116
CY6117

Test Conditions
Min.

Units

Max.

VOH

Output HIGH Voltage

Vee = Min., IOH = -4.0 mA

VOL

Output LOW Voltage

Vee = Min., IOL = 8.0 mA

VIH

Input HIGH Voltage

2.0

VIL

Input LOW Voltage

IIX

Input Load Current

GND:S: VI:S: Vee

loz

Output Leakage
Current

GND:S: VI:S: Vee
Output Disabled

los

Output Short
Circuit Current! 1]

Vee = Max., Vour = GND

Icc

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

Commercial

120

Military

130

Automatic CE
Power Down Current

Max. Vee,

Commercial

20

CE:;;' VIH

Military

20

ISB

2.4

V
0.4

V

-3.0

Vee
0.8

V

-10

10

/LA

10

/LA

-300

mA

V

mA
mA

Capacitance [2]
Parameters

Description
Input Capacitance

CIN

Output Capacitance

Cour

Test Conditions

Max.

TA = 2SoC, f = 1 MHz
Vee = S.OV

S

Units
pF

7

Note.:
I. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

3. See the last page of this specification for Group A subgroup testing
information.
4. TA is the "instant on" case temperature.

AC Test Loads and Waveforms
Rl481n

Rl481n

SVo-------~~~~

5V

0-----_-------+

OUTPUT

OUTPUT

I

30 pF

I

SpF
INCLUDING
_JIG AND
_
- SCOPE
-

25sn
00B7-4

Figure 18
Equivalent to:

Figure 1b

THEVENIN EQUIVALENT
16m

- -....0

OUTPUT 0--~·.'1""''1·w-.

1.73 V

3.0V-~-----l!=---~~~

0-----_------....

R2

INCLUDING
_JIGAND _
- SCOPE
-

ALL INPUT PULSES

o-------...JooN'-...,

0087-7

2-13

~:Sn

GNO -;:::fl~

~~
0087-6

00B7-5

Figure 2

II

Switching Characteristics Over Operating Range[4, 6]
CY6116·35
CY6117·35

Description

Parameters

Min.

Max.

CY6116-45
CY6117-45
Min.

Max.

CY6116-55
CY6117·55
Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

35

45
35

5

toHA

Data Hold from Address Change

tACE

CE LOW to Data Valid

tDOE

OE LOW to Data Valid

tLZOE

0

tHZOE

OE LOW to Low Z
OE HIGH to High Z[7]

tLZCE

CE LOW to Low Z[8)

5

tHZCE

CE HIGH to High Z[7, 8)

tpu

CE LOW to Power Up

tPD

CE HIGH to Power Down

55
45
5

5
35
15

45
20
15
5

15
0

5

0
20

ns

ns
ns

20
0

25

ns

ns

20

20

ns
ns

55
25
0

0
15

ns

55

ns
ns

25

ns

WRITE CYCLE(9)
twc

Write Cycle Time

tSCE

CE LOW to Write End

tAW

Address Set-up to Write End

tHA

Address Hold from Write End

tSA

Address Set-up to Write Start

tpwE

WE Pulse Width

tSD

Data Set-up to Write End

tHD

Data Hold from Write End

tHZWE

WE LOW to High Z
WE HIGH to Low Z

35
30
30
0
0
20
15
0

45

55

ns

40

40

ns

40

40

ns

0
0
20
20
0

0
0
25
25
0

ns

15
0

15
0

tLZWE
Notes:
5. Data I/O Pins enter high-impedance state, as shown, when OE is
held LOW during write.
6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading ofthe specified 100/loH and 30 pF load capacitance.
7. tHZOE, tHZCE and tHzwE are specified with CL = 5 pF as in Figure
lb. Transition is measured ± 500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.

ns
ns
ns
ns

20
0

ns
ns

9. The internal write time of the memory is defined by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
10. WE is HIGH for read cyele.
11. Device is continuously selected. OE, ~ = VIL.
12. Address valid prior to or coincident with CE transition LOW.

Switching Waveforms
Read Cycle No.1 (Notes la, 11)

~------------------------tRC--------------------------J~.

- . . ~- - - ¥ DATA OUT

~_H_A___~_A_~T------------------------------------

I_:_____
_____
PREVIOUS
DATA VALID

~

DATA VALID

0087-8

2-14

fin
,

CY6116
CY6117

~OOcroR===================================================================

Switching Waveforms (Continued)
Read Cycle No.2 (Notes 10, 12)
'Ae

~ ....

fI

...,rtACE

~

f

tOOE

I4---.LZOEi
HIGH IMPEDANCE

DATA OUT

-I

tlZCE
;"'-'PU

.HZOE---I--'HzeE-

,,,,

HIGH
IMPEDANCE
DATA VALID

'\ '\ '\ '\

1------------==j"""""~ICC

Vee
SUPPLY _ _ _ _ _ _
CURRENT
_

~'PO

50%

50%

158

0087-9

Write Cycle No.1 (WE Controlled) (Notes 5, 9)
twe
ADDRESS

,~

(

~
'SCE

~ ~\\

~II
'AW
'PWE

"A

'\\'

tH~

'SD

*

DATA IN

DATA-IN VALID

'I

DATAI~

III 'II IIIIII I.
'HA-

-'HZWE

*

-I)~!---~H~IG~H~IM~P~E~D~AN~C~E~ --(~~~
!---'LZWE

_ _ _ _ _ _ _ _ _ _D_A_T_A_U_N_D_EF_I_NE_D_ _ _ _ _ _ _ _

__

t

_____________

0087-10

Write Cycle No.2 (CE Controlled) (Notes 5, 9)
~--------------------------twe--------------------------~

____~::::::::~~::::::~-::~-----------.seE----------~I~------_+------------------

..D---------.,I-DATA-IN VALID
tHZWE------t

,P'------------------------------------------

---------------------------------~
DATA I/O

DATA UNDEFINED

HIGH IMPEDANCE

•

Note: If CE goes HIGH simultaneously with WI! HIGH, the output remains in a high impedance state,

2-15

0087-11

&n
. ~==================================================
CY6116
CY6117

.

Typical DC and AC Characteristics
NORM~SUPPLYCURRENT

.:;

J!
0
w

0.8

w

w
u

0.6

1'58

6.0

5.5

1.6

.

1,2

..........

1,0

i'-.....

0.9
0.8

4.0

4.5

-- 5.5

5.0

1:1

::J

«

g
6.0

~

60

..

0:::l
0:::l

40

0,8 1 7 " , r : ; . . . . - - - t - - - - - - - 1

0

20

-1j5

26

2.0

!

20.0

1.5

~

16.0

.

/

1.0

2.0

3.0

/'

4.0

SUPPLY VOLTAGE (VI

5.0
0,0

5,0

V
o

1.3

11

/
V

0

L
1,0

2,0

4,0

3.0

I

_~ee·5.0V

TA' 25°C
V,N =O.5V

w
N

/
TA' 26°C

::J

«

1,1

:i
II:
0

z

1.0

vee -4.50 V

0,9

400

Vee =5,OV

TA = 26°C

1.2

0.8

200

'"

NORMALIZED Icc
VB. CYCLE TIME

,.-

~ 10.0

/

/

OUTPUT VOLTAGE (VI

1,4

~

0,0

0.0

TYPICAL ACCESS TIME CHANGE
VB. OUTPUT LOADING

26.0

-~

/

o

126

AMBIENT TEMPERATURE (OCI

2.5

0.0

I

"in

30.0

0.5

80

z

3.0

1.0

/

100

W

0.6 '--_ _ _-..1._ _ _ _ _- '

:i
II:

Z

II:
II:

1-------,,10""''-------1

1,0

TYPICAL POWER·ON CURRENT
VB. SUPPLY VOLTAGE

j

!

:::l
U

SUPPLY VOLTAGE (VI

0

140

0-

+-___"IC-_-I

1,21-_ _ _ _

::J

~

4,0

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

r-----r------,

N

TA • 25°C

'"

3,0

OUTPUT VOLTAGE (VI

1,4...-----t-------1

Ii!

'"

2.0

C( 120

:J

N

1,0

0.0

NORMALIZED ACCESS TIME
vs. AMBffiNT TEMPERATURE

1,4

Vee =5.0V

TA = 25"C

Q

125,0

26,0

AMBIENT TEMPERATURE (OCI

1,3

0
w

20

"-...

0

-55

NORMALIZED ACCESS TIME

z

0:::l

0,0

vs. SUPPLY VOLTAGE

0

..

40

!;

0.2

SUPPLY VOLTAGE (VI

«

~

Vee -s.OV
V,N -s.OV

i
5.0

"

60

:::l

0.4

ISB
4,5

80

II:

«

II:

:i

II:
II:

100

U

N

OA

::J 1.1

!Zw
:::l

:IE

0,0
4.0

II:

~

::J

0,2

..
:J

C(

!

0

:i

~

~

1.0

.1i

./'

N

120

.!I

[/"

0,8

::J 0,6
«
II:

1.2

./
Icy

1,0

OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE

VB.

1,2

.!I

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

vs. SUPPLY VOLTAGE

1,4

800

CAPACITANCE (pFI

800

1000

............

o

~

10

............
20

---

30

40

CYCLE FREQUENCY (MHz!
0087-12

2-16

CY6116
CY6117

(;r~crOR
Pin Configurations
A7

Vee

A.

As
As

A.

WE
OE

~

CE

5

AS

6

'4 '3 2'1 ' 32 3i 30

A31 8
A21 9

1107
liD,

A6

I

I

A41 7

A,.

A.
A,

z z z >tloo
z z

... 0 0 0

oC

29

A8

28

As

27.NC
26
25

CY6117

At

Aotl

23CE

110.

NC 12

22 1/07

1/03
0087-2

24

OE

110.
110.

I/O.
GND

10

J~

1/00 13
21
14 15 16 17 18 19 20

AtO

4 3 2liJ 28 27 26 ) _
2S)~
24 OE
23 AtO
CY6116
22 NC
2t NC
20 CE
19 1/08
,"!.n~~~16t718
N tt) c
.... I() co ,....

A3 ~5
A2 )6
NC 7
NC 8
At 9
Ao 10
I/Ot 11

1/06

~~i3~~~~

0087-3

0087-'4

Ordering Information
Speed
(ns)
35

45

55

Package
Type

Operating
Range

CY6116-35PC

Pll

Commercial

CY6116-35DC

D12

CY6116-35LC

L64

55

CY6116-35DMB

D12

CY6116-35LMB

L64

Ordering Code

CY6116-45PC

Pll

CY6116-45DC

012

CY6116-45LC

L64

CY6116-45DMB

012

CY6116-45LMB

L64

CY6116-55PC

Pll

CY6116-55DC

012

CY6116-55LC

L64

CY6116-55DMB

D12

CY6116-55LMB

L64

Military
Commercial

Military
Commercial

Military

2-17

Speed
(ns)

Ordering Code

Package
Type

Operating
Range

35

CY6117-35LMB

L55

Military

45

CY6117-45LMB

L55

Military

CY6117-55LMB

L55

Military

II

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

ISB

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

taHA

7,8,9,10,11

tACE

7,8,9,10,11

tOOE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

Document #: 38-OO055-C

2-18

CY6116A
CY6117A

CYPRESS
SEMICONDUCTOR

2048

X

8 Static R/W RAM

Features

Functional Description

• Automatic power·down when
deselected

The CY6116A and CY6117A are high
performance CMOS static RAMs orga·
nized as 2048 words by 8 bits. Easy
memory expansion is provided by an
active LOW chip enable (CE), and active LOW output enable (OE) and
three-state drivers. The CY6116A and
CY61l7A have an automatic powerdown feature, reducing the power consumption by 83% when deselected.

tion addressed by the address present
on the address pins (Ao through AIO).
Reading the device is accomplished by
selecting the device and enabling the
outputs, CE and OE active LOW,
while (WE) remains inactive or HIGH.
Under these conditions, the contents of
the location addressed by the information on address pins is present on the
eight data input/output pins.

An active LOW write enable signal
(WE) controls the writing/reading operation of the memory. When the chip
enable (CE) and write enable (WE) inputs are both LOW, data on the eight
data input/output pins (1/00 through
1/07) is written into the memory loca-

The input/output pins remain in a high
impedance state unless the chip is selected, ~uts are enabled, and write
enable (WE) is HIGH.

• CMOS for optimum
speed/power

• High speed-20 ns
• Low active power
- 550 mW
• Low standby power
-110 mW
• TTL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

The CY6116A and CY6117A utilize a
die coat to ensure alpha immunity.

Logic Block Diagram

1/0.
1/0,

1/02
1/0 3
1/0.
IIOs

1/0.

CE--<.---2001V
(Per MIL-STD-883 Method 301S)

Ambient Temperature with
Power Applied .................... - SS·C to + 12S·C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -O.SV to + 7.0V

Latch-up Current .......................... > 200 rnA

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to +7.0V

Ambient
Temperature
O·Cto +70"C
- SS·C to + 12S·C

Rilnge
Commercial
Militaryl4]

DC Input Voltage ................... -3.0V to +7.0V
Output Current into Outputs (Low) ............. 20 mA

Vee
SV ±1O%
SV ±1O%

Electrical Characteristics Over Operating Range[3]
Parameters

Description

CY6116A-20
CY6117A-20

Test Conditions

Min.
Output HIGH Voltage

VOH
VOL
VIR
VIL
IIX

Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[4A)

Vee = Min.,loH = -4.0mA
Vee = Min., IOL = 8.0 rnA

GND":; VI":; Vee

los

Input Load Current
Output Leakage
Current
Output Short
Circuit Current[ 11

Icc

Vee Operating
Supply Current

Vee = Max.
lOUT = ornA

ISBI

Automatic CE
Power Down Current

Max. Vee,
CEI;'" VIR,
Min. Duty
Cycle = 100%

loz

Automatic CE
Power Down Current

ISB2

CY6116A-25, 35, 45
CY6117A-25, 35, 45
Min.
Max.
2.4
0.4
2.2
Vee
-0.5
0.8
-10
10

Max.

2.4
0.4
2.2
-O.S
-10

Vee
0.8

-10

+10

GND":; VI":; Vee
Output Disabled
Vee = Max., VOUT = GND

10

-10

-300

-300

100

100
125
100
20
40

Coml.

MiL~
. 35,45
Coml.

40

.~

Mil.

+10

35,45

CY6116A-55
CY6117A-55 Units

Min.

Max.

2.4
2.2
-0.5
-10

Vee
0.8

V
V
V
V

10

/LA

-10

+10

/LA

-300

rnA

0.4

80
100
20
rnA
20

20

Max. Vee,
CEI ;", Vee - 0.3V, Coml.
VIN;'" Vee - 0.3V
Mil.
orVIN":; 0.3V

20

rnA

20

20

20

20

rnA

·35 ns and 55 ns only

Capacitance [21
Parameters

Description
Input Capacitance
Output Capacitance

CIN

CoUT
Notes:
1. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
a!Tect these parameters.

Test Conditions

Max.

TA = 2S·C,f= 1 MHz
Vee = 5.0V

5

Units
pF

7

3. See the last page of this specification for Group A subgroup testing
information.
4. TA is the "instant on" case"temperature.

4A. VIL min.

= -

3.0V for pulse durations less than 30 ns.

AC Test Loads and Waveforms
R1481n
5 v o-----"M...-.

5v

OUTPUT o---...,..--~

OUTl'UTo--...,..---t

r

30PF
INCLUDIN
_ JIGAND _
-'SCOPE
-

ALL INPUT PULSES

Rl481n

0------'\,.,.,---,

~n

I
0167-5

Figure la

5PF
INCLUDING
_JIG AND _
- SCOPE
-

Figure Ib

Equivalent to: THtVENIN EQUIVALENT
16m
OUTPUT O--~""'''I'I\o.---o l.73V

0167-8

2-20

::Sn
0167-6

0167-7

Figure 2

(;n
.

CY6116A
CY6117A

~UcrOR===================================================================

Switching Characteristics Over Operating Range[4, 6]
Parameters

Description

CY6116A-20
CY6117A-20

CY6116A-2S
CY6117A-2S

CY6116A-3S
CY6117A-3S

CY6116A-4S
CY6117A-4S

CY6116A-SS
CY6117A-SS Units

Min.

Min.

Min.

Min.

Min.

Max.

Max.

Max.

Max.

Max.

READ CYCLE
20

25

45

55

tRc

Read Cycle Time

tAA

Address to Data Valid

taHA

Data Hold from Address Change

tACE

cP; LOW to Data Valid

20

25

35

45

55

ns

tDOE

OE LOW to Data Valid

10

12

15

20

25

ns

tLZOE

OE LOW to Low Z

tHZOE

OE HIGH to High Z[7]

tLzCE

CE LOW to Low Z[S]

tHZcE

CE HIGH to High Z[7, s]

tpu

cP; LOW to Power Up

tpD

CE HIGH to Power Down

35
25

20
5

5

5

3

3

8
8

10
0

20

5

0
20

5

0
20

ns
20

15

15

ns
ns

20
0

25

ns
ns

3
15

12

ns
55

5

3

5

5

45
5

3
10

5

0

35

ns
ns

25

ns

WRITE CYCLE[9]
25

40

50

ns

20

25

30

40

ns

15

20

25

30

40

ns

0

0

0

0

0

ns

Address Set-up to Write Start

0

0

0

0

0

ns

tPWE

WE Pulse Width

15

15

20

20

25

ns

tSD

Data Set-up to Write End

10

10

15

15

25

ns

tHD

Data Hold from Write End

0

0

0

0

0

tHzwE

WE LOW to High Z

twc

Write Cycle Time

tSCE

CE LOW to Write End

15

tAw

Address Set-up to Write End

tHA

Address Hold from Write End

tSA

WE HIGH to Low Z

20

20

7

7

5

5

tLZWE
Notes:
5. Data I/O Pins enter high-impedance state, as shown, when OE is
held LOW during write.
6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading ofthe specified IOrJIOH and 30 pF load capacitance.
7. tHZOE, tHzCE and tHzwE are specified with CL ~ 5 pF as in Figure
1b. Transition is measured ± 500 mV from steady state voltage.
S. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.

10
5

5

ns
20

15
5

ns
ns

9. The internal write time of the memory is defined by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a

write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
10. WE is HIGH for read cycle.
II. Device is continuously selected. OB, CE ~ VIL.
12. Address valid prior to or coincident with CE transition LOW.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

~t:~~--------------------------I"C--------------------------~J.

ADDRES_~~ ~ -H_A~ ~ -I_A~A- ~-!- - - - - .-',- ~~~~~~~~~~~~~~~~~~~~~~~:-_~__.================
_________-___-_____

DATA OUT

PREVIOUS DATA VALID

~

DATA VALID

0167-9

2-21

. .
&n
.

CY6116A
CY6117A

~U~.~===========================================================

Switching Waveforms (Continued)
Read Cycle No•.2 (Notes 10, 12)
IRe

..,,...

J~
tACE

{

-'
tOOE

HIGH IMPEDANCE
DATA OUT

1

Vee _ _ _ _ _ _
SUPPLY
CURRENT
_

II

I

I

HIGH
IMPEDANCE

I

DATA VALID

·1"'"

tL2CE

!--IPU

'HZOEi--'HzeE-

!---ILZOE,

t----'PO

50%

0167-10

Write Cycle No.1 (WE Controlled) (Notes 5, 9)
twe

ADDRESS

~

--'
ISCE

~/II/I rIllIII

\\ i\\\
lAW

I II.

IHA..... E

ISA

,\\
IH~

ISO

*

DATA IN

DATA-IN VALID

'I

!---'HZWE

»'---..:.H:;;IG;;;.H:";I;;;M:";PE::D::;;A:::NC::E;..._~·~,,

.

!---ILZWE

DATA 110 _ _ _ _ _ _ _ _ _D_A_T_A_U_N_D_EF_IN_E_D_ _ _ _ _ _ _ _...

_ _ _ _ _ __

0167-11

Write Cycle No.2 (eli Controlled) (Notes 5, 9)
~--------------------------twc--------------------------~

ADDRESS

·~~-----------~eE----------~

a --~--------------~

~-----~------------

"0'--------'DATA-IN. VALID

DATA IN

tHZWE~
DATA I/O

-------------..;..---~
DATA UNDEFINED

/>---------....:;::;.:.:::::.:::::.:=------HIGH IMPEDANCE

0167-12

Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

2-22

fin
.

CY6116A
CY6117A

~~~================================================================

Typical DC and AC Characteristics
NORMAUZEDSUPPLYCURRENT
VB. SUPPLY VOLTAGE
1.4

Icy

1.2

~

1.0

c

O.B

~

/'

IU

N

:.
«

0.6

c
z

1.2

~

/

1.0

N

:.
II:

0.4

6.0

5.5

..

1.0

.............

~

--- 5.0

4.5

:.«

To. - 25'C

II:

.,/

1.0

L

z
O.B

i

25

30.0

2.5

25.0

!

2.0

..

~

1.5

/

20.0

/

15.0

~

0.5

0.0

1.0

2.0

3.0

l!l

L

V

0.0

10.0
5.0
0.0

4.0

SUPPLY VOLTAGE (VI

::>
u

60

z

60

::>

40

::>
0

20

125

5.0

/

V

/

/

V
o
0.0

1.0

--

4.0

3.0

NORMALIZED Icc
CYCLE TIME

1.4
1.3

u

~

c
IU

I
_yee=5.OV
TA • 25'C
V,N -O.SV

1.2

N

::;

1.1

::Ii
0

1.0

«

L

II:

TA = 25'C
vee -4.50 V

z

0.8
400

2.0

VS.

...,...,... ~

0.9

200

Vee =5.OV
TA = 25'C

OUTPUT VOLTAGE (VI

/

o

I'

/

a:
a:

TYPICAL ACCESS TIME CHANGE
VB. OUTPUT LOADING

3.0

1.0

./

100

AMBIENT TEMPERATURE ('CI

N

~

i

120

in

Vee -5.0V

0.6
-55

SUPPLY VOLTAGE (VI

II:

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

oS
zIU

L

1.2

'"

4.0

3.0

YS.

.
.
...

1.4

TYPICAL POWER·ON CURRENT
vs. SUPPLY VOLTAGE

"

OUTPUT VOLTAGE (VI

C

0

6.0

5.5

2.0

1.0

140

N

4.0

:.

0.0

125.0

25.0

NORMALIZED ACCESS TIME

:J
c
IU

0.8

.

o

·55

Vee =5.0 V
TA = 2S·C

20

vs AMBIENT TEMPERATURE

1.2

...........

40

AMBIENT TEMPERATURE I'CI

1.3

0.9

j

::>
0

1.6

1.1

"- ~

::>

lsa

0.0
5.0

NORMALIZED ACCESS TIME

c

....

III

Vee -5.OV
V,N =5.OV

VB. SUPPLY VOLTAGE

:.
~
II:
0
z

60

a:

0.2

1.4

N

60

::>
0

SUPPLY VOLTAGE (VI

.

a:
a:
u
u

...

z

4.5

100

Z

IU

0.6

0

ISB

.

oS

::>

«

::Ii

0.0
4.0

.

~

U 0.8
Jl

0.2

:J
c

C

c

IU

0.4

OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE

VS.

120

:-............

J

~

II:

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VS.

600

CAPACITANCE (pFI

800

1000

~

o

~

10

20

30

40

CYCLE FREQUENCY (MHz!

0167-13

2·23

fin
. .

CY6116A
CY6117A

~=======================================

Pin Configurations
z z z >!::loo
z z

... 0 0 0

Vee

ocC

As
A6

5

"

A5 ~6

284 Ag

A4 ~7

274 HC

A2 9

..._-_.-

110.

AI

10

IIOs

Ao

11

110,

254

0167-2

Of

24 A10
23 CE

HC 12

I/OJ

A3
A2
HC
HC
AI
Ao

264 WE
CY6117A

22

)f~~~ ocC"~

4 3 2

294 A8

A3 ~8

GND

ocC--

'4 '3 '2, T '32 3i 30

1/°1

5
6
7
8
9
10

II 128 27 26 "....

6116A

1" 2 13 14 15 16 171

25 WE
24 Of
23 A10
22 HC
21 ~ HC
20)CE

~ 9 ) 1/°8

1/07

1/00 13
21 1/06
14 15 16 17 18 19 20

J

0167-4

0167-3

Ordering Information
Speed
(ns)

20
25

35

45

55

Package
Type

Operating
Range

Speed

CY6ll6A-20PC

Pll

Commercial

CY6ll6A-20DC

D12

CY6ll6A-25PC

Pll

CY61l6A-25DC

D12

CY6116A-25LC

L64

CY6116A-25DMB

D12

CY6116A-25LMB

L64

Ordering Code

CY6l16A-35PC

Pll

CY6ll6A-35DC

D12

CY6ll6A-35LC

L64

CY6ll6A-35DMB

D12

CY6ll6A-35LMB

L64

CY6ll6A-45PC

Pll

CY6ll6A-45DC

D12

CY6ll6A-45LC

L64

CY6ll6A-45DMB

D12

CY6116A-45LMB

L64

CY6116A-55PC

Pll

CY6116A-55DC

D12

CY6ll6A-55LC

L64

CY6ll6A-55DMB

D12

CY6ll6A-55LMB

L64

Ordering Code

Package
Type

Operating
Range

25

CY6ll7A-25LMB

L55

Military

35

CY6117A-35LMB

L55

Military

45

CY6ll7A-45LMB

L55

Military

55

CY6ll7A-55LMB

L55

Military

(ns)

Commercial

Military
Commercial

Military
Commercial

Military
Commercial

Military

2-24

(;n
.

CY6116A
CY6117A

~~====================

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

IOZ

1,2,3

ICC

1,2,3

ISB

1,2,3

II

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tAcE

7,8,9,10,11

tOOE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAw

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpWE

7,8,9,10,11

tso

7,8,9,10,11

tHo

7,8,9,10,11

Document #: 38-00105

2-25

CY7C122

CYPRESS
SEMICONDUCTOR

256

Features

Functional Description

• 256 x 4 static RAM for control
store in high speed computers

The CY7C122 is a high performance
CMOS static RAM organized as 256
words x 4 bits. Easy memory expansion
is provided by an active LOW chip select one (CS\) input, an active HIGH
chip select two (CS2) input, and threestate outputs.

• CMOS for optimum
speed/power
• High speed
- 15 us (commercial)
- 25 us (military)
• Low power
- 330 mW (commercial)
- 495 mW (military)
• Separate inputs and outputs
• 5 volt power supply ± 10%
tolerance both commercial and
military
• Capable of withstanding greater
than 2000V static discharge
• TIL compatible inputs and
outputs

An active LOW write enable input
(WE) controls the writing/reading operation ofthe memory. When the ~
select one (CS\) and write enable (WE)
inputs are LOW and the chip select
two (CS2) input is HIGH, the information on the four data inputs Do to D3 is
written into the addressed memory
word and the output circuitry is preconditioned so that the correct data is
present at the outputs when the write
cycle is complete. This preconditioning

Logic Block Diagram

X

4 Static R/W RAM
operation insures minimum write. recovery times by eliminating the "write
recovery glitch."
Reading is performed with the chip select one (CS\) input LOW, the chip select two input (CS2) and write enable
(WE) inputs HIGH, and the output enable input (OE) LOW. The information
stored in the addressed word is read
out on the four non-inverting outputs
00 to 03.
The outputs of the memory go to an
active high impedance state whenever
chip select one (CS\) is HIGH, chip select two (CS2) is LOW, output enable
(OE) is HIGH, or during the writing
operation when write enable (WE) is
LOW.

Pin Configurations

0003-2

"'1
"'0

"'5
"'6
"'7
GND
Do

3 2 1 2423
22
21
6
20
7
19
8
18
9
17
10
16
1112131415
4
5

"'4

WE
~1

OE
CS 2

03
03

0003-10

Selection Guide

Maximum Access Time (ns)
Maximum Operating Current (rnA)

Commercial

7C122-15

7C122-25

7C122-35

15

25

35
35

Military

NA

25

Commercial

90

60

60

Military

NA

90

90

2-26

~
CY7C122
~~~~================================================================
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C

Static Discharge Voltage ........•............ >2001V
(per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latchup Current .......................... > 200 mA

Supply Voltage to Ground Potential
Pin22toPin8) ..................... -0.5Vto +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial
Military [s)

Output Current, into Outputs (Low) ...........•. 20 rnA

Ambient
Temperature

Vee

O°C to + 70"C

5V ±1O%

- 55°C to + 125°C

5V ±1O%

Logic Table
Inputs
OE

CSt

CS2

X
H
X
X
X
L
L
L
H
X
L
H
X
L
H
H
L
H
Notes: H = HIGH Voltage
L = LOW Voltage
High Z = High Impedance

WE

00-0 3

X
X
H
L
L
H

X
X
X
L
H
X

x=

Outputs

Mode

HighZ
HighZ
00-03
HighZ
HighZ
HighZ

Not Selected
Not Selected
Read Stored Data
Write "0"
Write "I"
Output Disabled

Don't Care

Electrical Characteristics Over the Operating Range[4)
Parameters

Description

Min.
VOH

Output HIGH Voltage

Vee = Min., IOH = - 5.2 rnA

VOL

Output LOW Voltage

Vee = Min., IOL = 8.0 rnA

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

IIX

Input Load Current

VCD

Input Diode Clamp
Voltage

loz

Output Current (High-Z)

VOL:::;; VOUT :::;; VOH
Output Disabled

Output Short Circuit
Current (Note 1)

Vcc = Max.,
VOUT = GND

Commercial

los

Military

Vcc = Max.,
lOUT = OmA

Power Supply
Current

Icc

7C122-2S
7C122·3S

7C122-1S

Test Conditions

Max.

2.4

Min.

Units

Max.
V

2.4
0.4

V

Vee
0.8

V

10

10

/LA

Note 2

Note 2

V

+10

/LA

-70

-70

rnA

-80

-80

rnA

Commercial

90

60

rnA

Military

NA

90

rnA

0.4
2.1
-3.0

GND:::;; VI:::;; Vec

-10

Vee
0.8

+10

2.1
-3.0

-10

V

Capacitance [3]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions
TA = 25°C, f
Vee = 5.0V

Notes:
I. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
2. The CMOS process does not provide a clamp diode. However, the
eY7Cl22 is insensitive to -3V dc input levels and -SV undershoot
pulses of less than 10 ns (measured at SO% point).

=

1 MHz

Max.
4

Units
pF

7

3. Tested initially and after any design or process changes that may
affect these parameters.
4. See the last page of this specification for Group A subgroup testing
information.
S. TA is the "instant on" case temperature.

2-27

II

~
CY7C122
~~~~aoR================================================================
Switching Characteristics Over the Operating Range[6, 71
Parameters

Description

Test
Conditions

CY7C122·15
Min.

Max.

CY7C122·35

CY7C122·2S
Min.

Max.

Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tACS

Chip Select Time

tZRCS

Chip Select to High·Z

tAOS

Output Enable Time

Output Enable to High·Z
tZROS
Address Access Time
tAA
WRITE CYCLE
twc

Write Cycle Time

tzws

Write Disable to High.Z

tWR

Write Recovery Time

tw

Write Pulse Width

tWSD
tWHD
tWSA

Address Setup Time

Note 8
Note 8

15

2S

DS

12

20

30

DS

8

15

25

ns

12

20

30

ns

15

25

35

DS

30

os
os

25
12

20

11

15

Data Setup Time Prior to Write

0

Data Hold Time After Write

2
Note 6

35
20

12
Note 6

DS

8

15
Note 8

3S

2S

15

25

ns

25

ns

5

5

ns

5

5

ns

0

S

10

ns

tWHA

Address Hold Time

4

5

5

ns

twscs

Chip Select Setup Time

0

5

S

ns

2

5

5

ns

Chip Select Hold Time
tWHCS
Notes:
6. tw measured at tWSA = min.; tWSA measured at tw = min.
7. Test conditions assume signal transition times of S ns or less for the
-IS product and \0 ns or less for the - 25 and - 3S product. Timing
reference levels of 1.5V and output loading of the specified IorJIOH
and 30 pF load capacitance as in Figure 1Q.

8. Transition is measured at steady state HIGH level - 500 mVor
steady state LOW level + 500 mV on the output from 1.5V level on
the input with load shown in Figure lb.

BitMap
Address Designators
Address
Function

Pin
Number

Ao

AXO

4

Al

AXl

3

A2

AX2

2

A3

AX3

1

A4

AX4

21

A5

AYO

5

A6

AYI

6

A7

AY2

7

Address
Name

0003-3

2·28

AC Test Loads and Waveforms
Input Pulses

AC Test Loads
R1470n

Rl470n

5V~

5V~

30 pF

1

R2

0003-5

Figure 2

--

--

Figure la
Equivalent to:

R2
224n

5PF

'=" 224n

fJI

GND _ _.....r

OUTPUT

OUTPUT

I

3.0V-----~~~--""""ll

0003-4

Figure Ib

THEVENIN EQUIVALENT
152n
OUTPUT

a..---·'II..'II/+....--~O 1.62 v
0003-6

Read Mode
Ao~A7

_~I--....--_ _
___
,oe-==--====~*=

ADDRESS

'AA

0

~

-

lAos
DATA
OUTPUTS

rNOTEO

DATA VALID

"\"\"\\."\"\

00.0,

.....-tZROS

~tZRCS""

tACS

LNOTE6

0003-7

Write Mode

twe
Ao-A1
ADDRESS

-l

-.
B,-cSz
CHIP SELECT

-.
00-0 3

DATA IN

WIt
WRITE ENABLE

OO~03

DATA OUTPUTS

LOAD ,.

'WSA

-J(twscs

--l t-

-

- -

-

twHA

-iE-

- -

---

twHCS

-;r

twso

tw

-',

'.

'ZWI

"'HO-

i:
r

'

NOTE 8

....

_two

1_

_-----~--(

------------------"""'LNOTE6

0003-8

(All above measurements referenced to l.SV unless otherwise stated.)

Note:
Timing diagram represents one solution which results in an optimum cycle time. Timing may be changed in various applications as long as the worst case
limits are not violated.

2-29

~
CY7C122
~~~aoR=============================================================
Typical DC and AC Characteristics
NORMALIZED Icc
vs. AMBIENT TEMPERATURE

NORMALIZED Icc
vs. SUPPLY VOLTAGE

v
V

1.2

u

1.0

!:
Q

w

N

:::;

~
0
z

0.8

II:

0.6

V

0.4
4.0

/

11

w

5l

:::>

"w
":::>

N

51

1.2

NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

0.8

TA

0.6
4.0

4.5

5.0

"'"z
iii

:::>

:IE

II:

~

/

0.6
-55

~0

25

/

~5'C

TA •
Vee =4.5V
20

j

~

/

10

/

V

V

T

400

2.0

3.0

4.0

6.0

OUTPUT VOLTAGE (VI

NORMALIZED Icc
vs. FREQUENCY
1.4

...--

/

1.3

/

V

V~
1
1.0

200

Vee = 5.0 V
TA = 25'C
1.0

AMBIENT TEMPERATURE rCI

30

4.0

-

/

125

26

"

J

50

:::>

Vee' 5.0V
6.0

3.0

2.0

V

75

I-

ACCESS TIME CHANGE
vs. OUTPUT LOADING

~

100

:i

SUPPLY VOLTAGE (VI

!

zw

II:
II:

26'C

5.5

125

0

.

---i -

1
I-

W
N

z

'r-...

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

:J

1.0

~

150

.

.. '-.."""'-

1.0

Vee' 5.0 V
TA -25'C

OUTPUT VOLTAGE (VI

AMBIENT TEMPERATURE ('CI

N

:IE
II:
0

o
o

1.4

:i

10

0·~5~5-----:l25:-----~125

6.0

NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE

0
w

20

...5
50

Vee = 5.5V
V,N =5.0V

V,N =5.0V
TA 26'C

1.6

lA

30

II:

~

5.5

'" "

40

II:
II:

~
II:

5.0

i'-..

:IE

:::;

i

50

I-

1.2

SUPPLY VOLTAGE (VI

..
:J

60

;(
.§

V
4.5

OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE

1.4r------,------,

600

800

C!O

1000

CAPACITANCE (pFI

/

/

10203040508070
FREQUENCY (MHz)
0003-9

2-30

~

CY7C122

~~~~==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Ordering Information
Speed
(ns)

15
25

35

Package
Type

Operating
Range

CY7C122-15PC

P7

Commercial

CY7C122-15DC

D8

Commercial

CY7C122-25PC

P7

Commercial

CY7C122-25DC

D8

Commercial

CY7C122-25LC

L53

Commercial

CY7C122-25DMB

D8

Military

CY7C122-35PC

P7

Commercial

CY7C122-35DC

D8

Commercial

CY7C122-35LC

L53

Commercial

CY7CI22-35DMB

D8

Military

CY7CI22-35LMB

L53

Military

Ordering Code

2-31

fI

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

. VILMax.

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tACS

7,8,9,10,11

tAOS

7,8,9,10,11

tAA

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tWR

7,8,9,10,11

tw

7,8,9,10,11

tWSD

7,8,9,10,11

tWHD

7,8,9,10,11

tWSA

7,8,9,10,11

tWHA

7,8,9,10,11

twscs

7,8,9,10,11

tWHCS

7,8,9,10,11

Document #: 38-00025-B

2-32

PRELIMINARY

CYPRESS
SEMICONDUCTOR

256

Features

Functional Description

• 256 x 4 static RAM for control
store in high speed computers

The CY7C123 is a high performance
CMOS static RAM organized as 256
words x 4 bits. Easy memory expansion
is provided by an active LOW chip select one (CSl) input, an active HIGH
chip select two (CS2) input, and threestate outputs.
An active LOW write enable input
(WE) controls the writing/reading operation of the memory. When the chip
select one (CSl) and write enable (WE)
inputs are LOW and the chip select
two (CS2) input is HIGH, the information on the four data inputs DO to D3 is
written into the addressed memory
word and the output circuitry is preconditioned so that the write data is
present at the outputs when the write
cycle is complete. This preconditioning
operation insures minimum write re-

• CMOS for optimum
speed/power
• High speed

-

7 ns (commercial)
10 ns (military)

• Low power
- 660 mW (commercial)
- 825 mW (military)
• Separate inputs and outputs
• 5 volt power supply ± 10%
tolerance both commercial and
military
• TTL compatible inputs and
outputs
• 24 pin
• 300 MIL package

Logic Block Diagram

X

CY7C123

4 Static R/W RAM
covery times by eliminating the "write
recovery glitch."
Reading ~erformed with the chip select one (CSl) input LOW, the chip select two input (CS2) and write enable
(WE) inputs HIGH, and the output enable input (DE) LOW. The information
stored in the addressed word is read
out on the four non-inverting outputs
00 to 03.
The outputs of the memory go to an
active high impedance state whenever
chip select one (CSl) is HIGH, chip select two (CS2) is LOW, output enable
(aE) is HIGH, or during the writing
operation when write enable (WE) is
LOW.
A die coat is used to insure alpha immunity.

Pin Configurations
A2

Vee

A3

A,

A.

Ao

As

WE

A6

CS,

A7

liE

Vss

A2

es,

0,

°3

II:

00

Q

0,

°2
03

Vss

°2

Ao
A,

vee

00

'"
8
'"
Q

0088-2

~

A3

0
II:

A4
As

A,

COLUMN
DECODER

A7

" ,2,3,4,5
0088-3

Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)

Commercial
Military
Commercial
Military

7C123-7
7
NA
120
NA
2-33

7Cl23-9
9

7C123-10
NA

NA
120
NA

NA
150

10

7C123·12
12
12
120
150

7C123-15
NA
15
NA
150

II

~

PRELIMINARY

CY7C123

..,,-~~====================================~
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C

Output Current, into Outputs (Low) ............. 20 rnA

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latchup Current .......................... > 200 rnA

Operating Range

Supply Voltage to Ground Potential
Pins 24 & 18 to Pins 7 & 12 ........... -0.5V to + 7.0V

Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V

Commercial
Military[2]

DC Input Voltage ................... - 3.0V to + 7.0V

Ambient
Temperature

Vee

O"C to + 70"C

SV ±1O%

- 55°C to + 12S0C

SV ±1O%

Logic Table
Inputs
OE

~1

Outputs

WE

Do- D3

Mode

X

H

CS2
X

X

X

HighZ

X

X

L

X

X

HighZ

Not Selected

L

L

H

H

X

Read Stored Data

X

L

H

L

L

00-03
HighZ

X

L

H

L

H

HighZ

Write "I"

X

HighZ

Output Disabled

H
L
Notes: H = mGH Voltage

H
L = LOW Voltage

H

x=

Not Selected

Write "0"

Don't Care

High Z = High Impedance

Electrical Characteristics Over the Operating Range(3)
Parameters

Deseription

7CI23-7
7C123-9

Test Conditions

Min.

=
=

= -5.2mA
= 8.0 mA

Max.

Min.

7Cl23-12

Max.

Vou

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee

VIH

Input HIGH Voltage

2.2

VIL

Input LOW Voltage

-3.0

Vee
0.8

-3.0

Vee
0.8

IIX

Input Load Current

Vss:S; VI:S; Vee

-10

10

-10

loz

Output Current
(High-Z)

Vss :s; VOUT :s; Vee
Output Disabled

-10

+10

-10

lee

Power Supply
Current

Vee = Max.,
lOUT = OmA

Min.,Iou
Min., IOL

2.4

7C123-10
7C123-15
2.4

0.4

I Commercial
I Military

Min.

V

2.4
0.4

2.2

Units

Max.
0.4

V

Vee
0.8

V

-3.0

10

-10

10

/-LA

+10

-10

+10

/-LA

2.2

V

120

NA

120

mA

NA

150

150

mA

Capacitance [1]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions
TA = 25°C, f
Vee = 5.0V

=

1 MHz

Max.
4

Units
pF

7

Notes:
3. See the last page oflhis specification for Group A subgroup testing

1. Tested initially and after any design or process changes that may
affect these parameters.
2. TA is the "instant on" case temperature.

information.

2-34

Switching Characteristics Over the Operating Range[3)
Parameters

Description

Test
Conditions

7Cl23·7

7C123·9

7C123·10

7Cl23·12

7C123·15

Units

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address Access Time

7

9

10

12

15

ns

tACS

Chip Select Time

7

8

8

8

10

ns

tOOE

Output Enable Time

7

8

8

8

10

ns

tHZcS

Chip Select to Output Hi·Z

Notes 4,5

5

6

6

6.5

8

ns

tHZOE

Output Enable to Out Hi·Z

Note 4

5

6

6

6.5

8

ns

tLZCS

Chip Select to Out Low-Z

tLzOE

Output Enable to Out Low-Z

9

7

12

10

15

ns

Notes 4,5

2

2

2

2

2

ns

Note 4

2

2

2

2

2

ns

WRITE CYCLE
twc

Write Cycle Time

tHZWE

Write Enable to Hi-Z

tLZWE

Write Enable to Low-Z

2

2

2

2

2

ns

tPWE

Write Pulse Width

5

6.5

7

8

11

ns

tsn

Data Setup to End of Write

5

6

7

8

11

ns

tHn

Data Hold Time After Write

1

1

1

1

1

ns

tSA

Add Setup to Start of Write

0.5

1

1

2

2

ns

tHA

Address Hold Time

1.5

1.5

2

2

2

ns

tscs

CS Active Low to End of Write

5

6.5

7

8

11

ns

tAW

Add Setup to End of Write

5.5

7.5

8

10

13

ns

9

7
5.5

Notes:
4. Transition is measured at steady state HIGH level - 500 mV or

10
6

12
6

15

ns

8

7

ns

5. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.

steady state LOW level + 500 mV on the output from 1.5V level on
the input with load shown in Figure lb.

2-35

fI

~
PRELIMINARY CY7C123
~~~~~==============================================================
AC Test Loads and Waveforms

AC Test Loads

5V~R141On
OUTPUT

r

Input Pulses
3.0 v-----;~:::----s..

5V~RU70n
OUTPUT

ISo':n

~~n

20pF

':"

OND
0088-5

Figure 2

":"":'

":"

0088-4

Figure la
Equivalent to:

Figure Ib

THEVENIN EQUIVALENT
152!l
OUTPUT O.....--·'II~'II
.."".--.....O 1.62 v
0088-6

Read Mode
~,,~---------tRC-----------'~'

*"-_____

ooIX

ADDRESS _ _ _ _ _

CS 1/CS2

~,.:::::::::ttAA~:::::::::.,:----------J

----------1X :

X
,

i

o..-tHZCS _

:-tACSt LZCS ,"
•
,

,

OE

,

,

----------.;...-~\ :

:

I,

"--tOOE'-'
tLZOE~ ,

"

:,

,
,
-tHZOE~

~~----------------~(~(~«~{r(:::::::j:::::}j-----0088-11

Write Mode
"

~rn

twc

~,

*

"

______-J~_____________________________',~------

,"

,

I I_
tAW ------------~~-tHA~
,I
tscs

,

X
,

X

,

tSA

"

..

,

~

,',,

\,

t pWE - :

l,

tsD

,
HZWE ....
" t

Ii"

,
-

t LZWE ,-

~~:::::::::::::::::::::::J)--------~OC(X~~

____

0088-12

(All above measurements referenced to J.5V unless otherwise stated.)

Note:
Timing diagram represents one solution which results in an optimum cycle time. Timing may be changed in various applications as long as the worst case
limits are not violated.

2-36

~

PRELIMINARY

CY7C123

~r~~====================
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE

NORMALIZED SUPPLY CURRENT
VB. AMBIENT TEMPERATURE

VB.

1.4
1.2

If/
./

~ 1.0
U
2

.. /
..
Q

0.8

1.0

]

..

~

0.8

Q

N

z

~

~

:; 0.6
:Ii
II!
0

1.2

./
N

0.6

C
:Ii

0.4

:;
a:

0.4

Vee =5.0 V
VIN =5.0 V

0

z

0.2

0.2 r---ISB

lsa

•
...
..'"
...'"fi!
'"
!

Z
a:
a:
u
u
a:

'"

90
75

"-

60
45

30
15

'" "

0

0.0
4.0

0.0
4.5

5.0

5.5

6.0

·55

25.0

SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIME
SUPPLY VOLTAGE

1.3

"

.

..
..

:J

:J 1.2

Q

..
N

:; 1.1

z

.............

1.0

~

0.9
0.8
4.0

4.5

Q

--

-

360

1

1.2

1.0

/'

Z

0.8

6.0

-55

T4

a:

i

]

2.0

....."

'~'C

20

:J

1.5

/

....

1.0
0.5
0.0
0.0

2.0

3.0

Q

/

V
1.0

4.0

SUPPLY VOLTAGE (V)

/'

240

/

a:
a:

il,.

180

iii

120

o

60

z

Vee' 5.0 V

Vee· 4.5V

Ii!N

:;

300

~'"

5.0

10

I

200

V

V

4.0

-

j

/
V

vee' 5.0 V
T4 • jS'C
1.0

125

2.0

3.0

4.0

5.0

OUTPUT VOLTAGE (V)

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30

2.5

C
:Ii

.ili

AMBIENT TEMPERATURE ('C)

3.0

j

L

./

25

SUPPLY VOLTAGE (V)

TYPICAL POWER·ON CURRENT
VB. SUPPLY VOLTAGE

"

OUTPUT SINK CURRENT

0.6

5.5

3.0

vs. OUTPUT VOLTAGE

N

:Ii
a:
0

2.0

NORMALIZED ACCESS TIME

:;

TA ·25·C

5.0

1.0

"'"

vs. AMBIENT TEMPERATURE

1.4

"

o
o

Vee' 5.0 V
T4 • 2S'C

OUTPUT VOLTAGE (V)

1.6

1.4

:Ii
a:
0

125.0

AMBIEI\IT TEMPERATURE ('C)

VB.

•

OUTPUT SOURCE CURRENT
VB. OUTPUT VOLTAGE

NORMALIZED ICC
VS. CYCLE TIME
1.1

,,-

Vee = 5.0 V
T4 ·2S'C
VIN = 0.5 V

u

2

1.0

53

..

N

:;
:IE

a:
0

z

400

600

CAPACITANCE (oFI

800

1000

0.8
10

20

30

40

CYCLE FREQUENCY (MHz)

0088-13

2·37

~

PRELIMINARY

CY7C123

~r~~====================
Ordering Information
Speed
(os)

7

9

10

12

15

Package
Type

Operating
Range

CY7C123-7PC

P13A

Commercial

CY7C123-7DC

014

Ordering Code

CY7C123-7LC

LS3

CY7C123-9PC

P13A

CY7C123-9DC

014

CY7C123-9LC

LS3

CY7C123-lODMB

014

CY7C123-lOLMB

L53

CY7C123-10KMB

K73

CY7C123-12PC

P13A

CY7C123-12DC

014

CY7C123-12LC

L53

CY7C123-12DMB

D14

CY7C123-12LMB

L53

CY7C123-12KMB

K73

CY7C123-15DMB

D14

CY7C123-15LMB

L53

CY7C123-15KMB

K73

Commercial

Military

Commercial

Military

Military

2-38

~

PRELIMINARY

CY7C123

~r~~====================
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

IOZ

1,2,3

IcC

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tACS

7,8,9,10,11

tOOE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tpWE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

tSA

7,8,9,10,11

tHA

7,8,9,10,11

tscs

7,8,9,10,11

tAW

7,8,9,10,11

Document #: 38-00060-D

2-39

CY7C128

CYPRESS
SEMICONDUCTOR

2048 x 8 Static R/W RAM

Features

Functional Description

• Automatic power-down when
deselected

The CY7C128 is a high performance
CMOS static RAM organized as 2048
words by 8 bits. Easy memory expansion is provided by an active LOW chip
enable (eE). and active LOW output
enable (OB) and three-state drivers.
The CY7C128 has an automatic powerdown feature. reducing the power consumption by 83% when deselected.

• CMOS for optimum
speed!power
• High speed-35 lis
• Low active power
- 660 mW (commercial)
- 825 mW (military)
• Low standby power
-llOmW

• SOJ package
• TIL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

An active LOW write enable signal
(WE) controls the writing/reading operation of the memory. When the chip
enable (CE) and write enable (WE) inputs are both LOW. data on the eight
data input/output pins (1/00 through
1/07) is written into the memory loca-

Logic Block Diagram

tion addressed by the address present
on the address pins (Ao through AIO).
Reading the device is accomplished by
selecting the device and enabling the
outputs. CE and OE active LOW.
while (WE) remains inactive or HIGH.
Under these conditions. the contents of
the location addressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high
impedance state unless the chip is selected. ~uts are enabled. and write
enable (WE) is HIGH.
The 7Cl28 utilizes a die coat to ensure
alpha immunity.

Pin Configurations

>-++++Hf++- lIoo
.--+-II>++H+#--I/O,

>-+++-++<0--- 1/02
r-H1~+l#~--I/03

'i+Hi+---I/O.

.p~:-~.t
3
A4
A3
A2
AI
Ao

L..-t-t>-++---I/O.

...

CE--~-

WE ---,....--.._1

Oe-t:~r;ct----.J

1/°0

I/O,
0036-1

i

6
7

\TJ24 23
22
21
20
19

8

18

4

5

9
17
10
16
1112131415
NC

If')

....

Ag

WE
OE
A0
'

Ct

1/°7

I/0.

It'll

~~~~~

0036-3

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)

Commercial

Maximum Standby
Current (mA)

Commercial

7C128·35

7C128-4S

35

45

55

120

120

90

130

100
20
20

Military

20

20
20

Military

2-40

7C128·55

~
CY7C128
~~~~==========================================================~
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -6S'C to + IS0'C

Static Discharge Voltage ..................... >2001V
(Per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied .................... - SS'C to + 125'C

Latch-up Current .......................... > 200 rnA

Supply Voltage to Ground Potential
(pin 24 to Pin 12) .................... -O.SV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to + 7.0V

Range

DC Input Voltage ................... - 3.OV to + 7.0V

Commercial
Military!4]

Output Current into Outputs (Low) ............. 20 rnA

Ambient
Temperature
O'Cto +70'C
- 55'C to + 125'C

Vee
5V ±10%
5V ±1O%

Electrical Characteristics Over Operating RangeD]
Parameters

Description

lOS

Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Current!l]

lee

Vee Operating
Supply Current

VOH
VOL
VIR
VIL
IIX
IOZ

Min.
2.4

Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA

7Cl2S
Max.

2.0
-3.0

Vee
0.8

-10

10

V
V
V
V
}J-A

-40

40

}J-A

-300

rnA

Vee = Max., VOUT = GND
Commercial-25, -35, -45
Commercial -55
Military -35
Military -45
Military -55
Commercial
Military'

Max. Vee,
CE;:;, VIR

Units

0.4

GND:S;; VI:S;; Vee
GND:S;; VI:S;; Vee
Output Disabled

Vee = Max.
lOUT = ornA

Automatic CE
Power Down Current

ISB

Test Conditions

120
90
150
130
100
20
20

rnA

rnA
rnA
rnA

rnA
rnA

*35 ns and 55 ns only

Capacitance [2]
Parameters

Description
Input Capacitance
Output Capacitance

CIN
COUT

Test Conditions

= 25'C, f = 1 MHz
Vee = S.OV

TA

Notes:
1. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

Max.
5
7

Units
pF

3. See the last page of this specification for Group A subgroup testing
information.
4. TA is the "instant on" case temperature.

AC Test Loads and Waveforms
Rl481n
5 v o----..I\I"Ar---.

Rl48Hl
5V

OUTPUT o---~---",

I
_
-

JOpF

I

25sn

10%

SpF

INCLUDING
_JIG AND
_
- SCOPE

0036-4

Figure Ib

Figure la
Equivalent to:

THEVENIN EQUIVALENT
16W

OUTPUT

~

OUTPUT O---~----i

R2

INCLUDING
JIG AND _
SCOPE
-

ALL INPUT PULSES

O------J4>/1.1I.--.

O---....,.....,.~...--"""O

1.73V

0036-13

2-41

~~n

5ns

0036-6

0036-5

Figure 2

•

Switching Characteristics Over Operating Rangel3, 6]
Parameters

7C128·35

Description

Min.

Max.

7Cl28-45
Min.

Max.

7Cl28·55

Min.

Max.

Units

READ CYCLE

35

iRc

Read Cycle Time

tAA

Address to Data Valid

toHA

Data Hold from Address Change

tACE

tHzoE

CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[7]

tLZCE

CE LOW to Low Z[S]

tHZCE

CE HIGH to High Z[7, S]

tpu

CE LOW to Power Up

tpD

CE HIGH to Power Down

tDOE
tLZOE

45
35

5

55
45

5
35
15

0

5
45
20

0
15

5

0

5

5

0

0
20

ns

ns
ns

20
0

25

ns

ns

20

20

ns
ns

55
25

15

15

ns

55

ns
ns

25

ns

WRITE CYCLE19]
twc

Write Cycle Time

tSCE

CE LOW to Write End

tAW

Address Set·up to Write End

tHA

Address Hold from Write End

tSA

Address Set·up to Write Start

tpWE

WE Pulse Width

tSD

Data Set·up to Write End

tHO

Data Hold from Write End

tHZwE

WE LOW to High Z[7]

tLZWE

WE HIGH to Low Z

35
30
30
0
0
20
15
0

45

55
50
50
0
0
25
25
0

40
40

0
0
20
20
0
15

0

15
0

ns
ns
ns
ns
ns
ns
ns
ns

20
0

ns
ns

Notes:

s. Data 1/0 Pins enter high·impedance state, as shown, when OE is
held LOW during write.
6. Test conditions assume signal transition times of 5 os or less, timing
reference levels of I.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOrJIOH and 30 pF load capacitance.
7. tHZO& tHZCE and tHZWE are specified with CL = 5 pF as in Figure
lb. Transition is measured ± 500 m V from steady state voltage.
S. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.

9. The internal write time of the memory is defined by the overlap of
<::Ii LOW and WI! LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
10. WI! is HIGH for read cycle.
11. Device is continuously selected. UI!, et! = VIL.
12. Address valid prior to or coincident with CE transition LOW.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

~t:~~------------------------tRC------------------------~J~.

I_:~ ~ ~ to~H~A~ ~ _tA-_-A-~-'-----.-'I-~~~~~~~~~~~~~~~~~~~~~~_*_~~~_-_-_-_-:_-_-_-_-_-_-_-

ADDRESS _
___{
DATA DUT

PREVIOUS DATA VALID

~

DATA VALID

0036-7

2·42

~

CY7C128

~~~W~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;;~==
Switching Waveforms (Continued)
Read Cycle No.2 (Notes 10, 12)
IRC

)

fI

....

~
tACE

~~

-{

1\
lODE

I

tHZOE -------

I--ILZOE
HIGH IMPEDANCE

DATA OUT

1

Vec _ _ _ _ _ _
SUPPLY
CURRENT

HIGH
IMPEDANCE

V· / / / L

DATA VALID

-I" '\ " '\ '\

tLZCE

_lpU

r--'HZCE-

I---'po

--j

ICC

5:~'SB

50%

_

0036-8

Write Cycle No.1 (WE Controlled) (Notes 5, 9)

ADDRESS

,

twc

--J
ISCE

~ r\\\

'lllill rlllllllll,
'AW
'sA

m:

'l
ISO

*

DATA IN

IHA-

IPWE

tH~

~
..J)>-,__-.,;,;H;,;IG; ,;H;, ;IM; ;P;,;E; D;,;AN; ,;C;,;E;. . _. . . (·~

DATA-IN VALID

·1

-tHzwe

!---ILZWE

DATA I/O _ _ _ _ _ _ _ _ _D_A_T_A_U_N_D_EF_'_NE_D_ _ _ _ _ _ _ _

.
_____________

0036-9

Write Cycle No.2 (CE Controlled) (Notes 5, 9)
~--------------------------IWC--------------------------~

__4:====:..:::~===:.-::t-------------ISCE

-----------t----+----------

tsD--------_1--DATA-IN VALID
tHZWE-----t

-----------------~
DATA 110

DATA UNDEFINED

HIGH IMPEDANCE

1~----------------------0036-10

Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

2-43

Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4

ley

1.2

~ 1.0

...0

0.8

/

N

::; 0.6
<[

!i

1.0

U 0.8

N

::;

~

II:

0.6
0.4

6.0

N

............

1.0

~

0.8
5.0

4.5

5.5

1.0

1-----"....,'-------1

0.8

1-7""'----+-------1

!i

-

~

0.9

4.0

1.2 I-----I-----~:....--I

<[

~

3.0

25.0

::; 1.5

! 20.0
"
;;:" 15.0

:I

~

2.0

0

N

<[

i

1.0
0.5

_V

0.0

0.0

1.0

2.0

3.0

/

5.0
0.0
5.0

-

...z

0-

100

II:
II:

:>
(J

BO

L
/V"

/

V

'zin"

60

.
0-

40

0

20

0-

:>

0

/
V

/

0.0

1.0

1.3

4.0

II
0

=5.0V
TA -25'C
V,N =0.5V

1.2

w

::;

1.1

:E
II:

TA =26'C
Vee =4.50 V

0
Z

1.0

0.8
400

3.0

I

~Vee

0.9

200

2.0

NORMALIZED Icc
vs. CYCLE TIME
1.4

<[

V
o

Vee =5.0V
TA • 25'C

N

/
/

"

4.0

OUTPUT VOLTAGE IV)

/

~ 10.0

/

4.0

SUPPLY VOLTAGE IVI

120

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0

2.5

II:

C

!

AMBIENT TEMPERATURE I'C)

TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE

3.0

OUTPUT SINK CURRENT

:>

SUPPLY VOLTAGE IVI

""

vs. OUTPUT VOLTAGE

0.6 .....- - - - - ' - - - - - - - '
-55
26
126

6.0

2.0

140

::;
TA = 25'C

Vee =5.0 V
TA = 25'C

OUTPUT VOLTAGE IVI

NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

N

<[

1.0

0.0

AMBIENT TEMPERATURE I'C)

1.2

~

20

o

125.0

26.0

1.41-----1------,

:Ii

40

0

-55

0

...

~

:>

1.6

::; 1.1

~

!;

0.0
5.5

5.0

$
5l

E

60

~

Vee o5.0V
V,N =5.0V
I"S8

1.3

z

...
(J

0.2

1.4

0

80

II:

NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE

II:

II:
II:

:>

z

4.5

100

:>

SUPPLY VOLTAGE IVI

...

0-

...Z

(J

0

IS8

0.0
4.0

!

~

0

0.2

:J"

C

.!!

...

0.4

OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120

~

~

:I

II:

1.2

./

V

oj

.!!

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

600

CAPACITANCE IpFI

800

1000

t,........"
o

.......-

10

..,........... .......20

30

40

CYCLE FREQUENCY IMHZ)
0036-11

2-44

~

CY7C128

~r~~====================
Ordering Information
Speed
(ns)

35

45

55

Type

Operating
Range

CY7C128-35PC

Pl3

Commercial

CY7C128-35VC

Vl3

CY7C128-35DC

Dl4

Ordering Code

Package

CY7C128-35LC

L53

CY7CI28-35KMB

K73

Military

CY7C128-45PC

Pl3

Commercial

CY7CI 28-45VC

Vl3

CY7C128-45DC

Dl4

CY7C128-45LC

L53

CY7CI 28-45DMB

Dl4

CY7CI 28-45LMB

L53

CY7C128-45KMB

K73

CY7C128-55PC

Pl3

CY7C128-55VC

Vl3

CY7C128-55DC

Dl4

CY7C128-55LC

L53

CY7CI28-55DMB

Dl4

CY7CI28-55LMB

L53

CY7C128-55KMB

K73

II

Military

Commercial

Military

2-45

~

CY7C128

~~~~NOOaDR================================================================

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

VrL Max.

1,2,3

Irx

1,2,3

Ioz

1,2,3

ICC

1,2,3

ISB

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACE

7,8,9,10,11

tDOE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

Document #: 38-00026-C

2-46

CY7C128A

CYPRESS
SEMICONDUCTOR

2048 x 8 Static R/W RAM

Features

Functional Description

• Automatic power-down when
deselected
• CMOS for optimum
speed/power
• High speed-20 ns
• Low active power
- 440 mW (commercial)
- 550 mW (military)

The CY7C128A is a high performance
CMOS static RAM organized as 2048
words by.8 bits. Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output
enable (OE) and three-state drivers.
The CY7C128A has an automatic power-down feature, reducing the power
consumption by 83% when deselected.

• Low standby power

An active LOW write enable signal
(WE) controls the writing/reading operation of the memory. When the chip
enable (CE) and write enable (WE) inputs are both LOW, data on the eight
data input/output pins (1/00 through
1/07) is written into the memory loca-

-llOmW
• SOJ package
• TIL compatible inputs and
outputs
• Capable of withstanding greater
than 2001 V electrostatic
discharge

tion addressed by the address present
on the address pins (Ao through Alo).
Reading the device is accomplished by
selecting the device and enabling the
outputs, CE and OE active LOW,
while (WE) remains inactive or HIGH.
Under these conditions, the contents of
the location addressed by the information on address pins is present on the
eight data input/output pins.
The input!output pins remain in a high
impedance state unless the chip is selected, outputs are enabled, and write
enable (WE) is HIGH.
The 7C128A utilizes a die coat to ensure alpha immunity.

• VIR of 2.2V

Pin Configurations

Logic Block Diagram

Vc:<
A,

Aa

WE
OE

1/00
1/0,
Au
110,
110,

1/0.

110,

1/03

1/03

0164-2

1/0,

~ 200 IV
(Per MIL-STD-883 Method 301S)
Latch-up Current. ......................... > 200 mA

Supply Voltage to Ground Potential
(pin 24 to Pin 12) .................... -O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State ........... , .......... -O.SV to + 7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
Output Current into Outputs (Low) ............. 20 mA

Operating Range
Range
Commercial
Military[4)

Ambient
Temperature
O"C to + 70"C
- 55°C to + 125°C

Vee
5V ±1O%
5V ±1O%

Electrical Characteristics Over Operating Range£3]
Parameters

Description

Vee = Min.,IOH = -4.0 rnA
Vee = Min., IOL = 8.0!8A

los

Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[4A!
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[l)

Icc

Vee Operating
Supply Current

Vee = Max.
lOUT = ornA

ISBI

Automatic CE
Power Down Current

Max. Vee,
CEI ~ VIH,
Min. Duty
Cycle =:' 100%

VOH
VOL
VIH
VIL
IIX
Ioz

Automatic CE
Power Down Current

ISB2

7C128A-20
Min. Max.
2.4
0.4
2.2 Vee
-O.S 0.8
-10
10

Test Conditions

GND ~ VI ~ Vee
GND ~ VI ~ Vee
Output Disabled

-10

Vee = Max., VOUT = GND
Coml.

+10

Max. Vee,
Coml.
~ Vee - O.3V,
VIN ~ Vee - 0.3V
Mil.
orVIN ~ 0.3V

+10
-300

100

100
125
100
20
40

40

20

a!1

-10

-300

Mil.~
35,45
Coml.
25
Mil. 35,45

7C128A-25, 35, 45
Min.
Max.
2.4
0.4
2.2
Vee
-0.5
0.8
-10
10

7C128A-55
Units
Min. Max.
2.4
V
0.4
V
2.2 Vee
V
-0.5 0.8
V
-10
10
/LA
-10

+10

/LA

-300 mA
80
100

rnA

20
rnA

20

20

20

20

20

20

mA

'35 ns and 55 ns only

Capacitance [2]
Parameters

Description
Input Capacitance
Output Capacitance

CIN
COUT

Test Conditions
TA = 25°C, f = 1 MHz
Vee = 5.0V

Max.
5
7

Units
pF

Notes:
3. See the last page of this specification for Group A subgroup testing
information.
4. TA is the "instant on" case temperature.
4A. VIL min. = -3.0V for pulse durations less than 30 ns.

1. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
aITect these parameters.

AC Test Loads and Waveforms
ALL INPUT PULSES

RI481n

R1481Sl

6Vo---.....,..,.,.-,

6Vo---~W\......,

OUTPUTo--...,..---t

OUTPUTo--_---i

r
_

- SCOPE

Equivalent to:

I

6PF
INCLUDING
_JIGAND _

30 F

:Sll
•
INCLUDIN
JIGAND _

-

0164-4

Figure 18
THEVENIN EQUIVALENT

- SCOPE

Figure 1b

16m

OUTPUT

o--....·y..\iI\
..._ -....O 1.73V

0164-12

2-48

-

~

:an
.

5no

0164-6

0164-5

Figure 2

~
CY7C128A
~~~~~=============================================================
Switching Characteristics Over Operating Range[3, 6]
Parameters

7CI28A-20

Description

Min.

Max.

7C128A-25
Min.

Max.

7C128A-35
Min.

Max.

7CI28A-45
Min.

Max.

7Cl28A-55
Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

20

25

tORA

Data Hold from Address Change

tACE

CE LOW to Data Valid

20

25

35

45

55

ns

tDOE

OE LOW to Data Valid

10

12

15

20

25

ns

tLZOE

OE LOW to Low Z

tHZOE

OE HIGH to High Z[7]

tLZCE

CE LOW to Low Z[8]

tHZCE

CE HIGH to High Z[7, 8]

tpu

CE LOW to Power Up

tpD

CE HIGH to Power Down

20

35
25

5

5

3

5

5

8
0
20

5
15

0
20

5

0
20

ns
20

15

ns
ns

20
0

25

ns
ns

3
15

5

ns
55

5

3
12

10

0

5

3

10

55
45

5

3

8

45
35

ns
ns

25

ns

WRITE CYCLE[9]
twc

Write Cycle Time

20

20

25

40

50

ns

tSCE

CE LOW to Write End

15

20

25

30

40

ns

tAW

Address Set-up to Write End

15

20

25

30

40

ns

tHA

Address Hold from Write End

0

0

0

0

0

ns

tSA

Address Set-up to Write Start

0

0

0

0

0

ns

tpWE

WE Pulse Width

15

15

20

20

25

ns

tSD

Data Set-up to Write End

10

10

15

15

25

ns

tHD

Data Hold from Write End

0

0

0

0

0

ns

tHZwE

WE LOW to High Z[7]

7

10

7

WE HIGH to Low Z
5
tLZwE
Notes:
5. Data 1/0 Pins enter high-impedance state, as shown, when ()l;; is
held LOW during write.
6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOrJIOH and 30 pF load capacitance.
7. tHZOE, tHZCE and tHZWE are specified with CL = 5 pF as in Figure
lb. Transition is measured ± 500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHzCE is less than
tLZCE for any given device.

5

5

15
5

20
5

ns
ns

9. The internal write time of the memory is defined by the overlap of
~ LOW and WI! LOW. Both signals must be LOW to initiate a

write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
10. WE is HIGH for read cycle.
II. Device is continuously selected. ()l;;, ~ = VIL.
12. Address valid prior to or coincident with CE transition LOW.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)
~------------------------_tRC--------------------------~J.

ADDRESS

DATA OUT

=i- - - ¥ _
______~______tO_H_A____~__A~:-------------------------------------PREVIOUS DATA VALID

~

DATA VALID

0164-7

2-49

III

~~~=====================================C=Y=7C==12=8=A
Switching Waveforms

(Continued)

Read Cycle No.2 (Notes 10, 12)

'RC

J

-,~

k-lACE

f

~
IOOE

'HZOE!--'HZCE--

i---.LZOEi
HIGH IMPEDANCE

DATA OUT

II

I

I

HIGH
IMPEDANCE

I

DATA VALID

·1" " " " "

tLZCE

cJ~~:~~--------__~-5-~----------------------------~------------~--------:::1-5-~--~::
f----.pu

j+-'po

0164-8

Write Cycle No.1 (WE Controlled) (Notes 5, 9)

ADDRESS

'We

-

......I

'SCE

\\ ~\\

~/III, rillI
'AW

tsA

'PWE

,\\

. ..=1

'SD

DATA IN

*

J(

DATA-IN VALID

'I

DATAI~

I I I II

'HA---

!--'HZWE

___________________
DA_T_A_U_N_D_E_FI_N_ED________________

.

!+--'LZWE

-"»!----~H~IG~H~I=MP~E~D~A~NC~E~ -4·~,_____________
__

0164-9

Write Cycle No.2 (CE Controlled) (Notes 5, 9)
~--------------------------'WC----------------------------

---------~~----------~CE-----------~

--~---------------~

-------------------"'"

~------~-----------------

I+-+--------~.------O+O>­

DATA-IN VALID
tHZWE----i

-------------------------..;..-----~
DATA 110

DATA UNDEFINED

HIGH IMPEDANCE

,>--------------------;,;;.;;;.;.;;;.;.;;;;,,;,;;;;;;;,-------------0164-10

Note: If~ goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

2-50

~
CY7C128A
~~~~============================================================~
Typical DC and AC Characteristics
NORMAUZED SUPPLY CURRENT

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

w. SUPPLY VOLTAGE
1.4
1.2

11

.Ii
...
Q

0.8

N

:::; 0.6

~
II:

S!

I~

1.0

IU

N

:::;
II:

0.4

0.8

0."

Vee o6.0V
V,N -6.0V

51

40

~

20

...~

!"SB

5.5

6.0

-55

o

0.0

125.0

25.0

......
Q

...
Q

N

1.0

I'-..

:II!

II:

r--

1.0

/

/

0

-

0.9

z
0.8

0.8

/

1.2

C

TA =25'C

C

120

6.0

4.5

....

100

Z

5.5

6.0

80

z'"

60

....::>

40

0

20

5
126

26.0

!

2.0

!:! 1.5

.
~

II:

!:i

IU

-

~

1.0

2.0

3.0

V-'

0.0

/

15.0

5.0
0.0
5.0

V

4.0

NORMALIZED Icc
CYCLE TIME

1.4
1.3
u

.!l

...

1.2

:::;

1.1

:IE
0

1.0

Q

c

/

II:

TA _25°C
vee -4.60 V

z

0.8
400

3.0

VS.

0.9

200

2.0

I
_Vee=5.0V
TA' 25'C
VIN aO.5V

N

V

o

1.0

OUTPUT VOLTAGE (VI

--

/

20.0

~ 10.0

/

4.0

SUPPLY VOLTAGE {VI

/

TYPICAL ACCESS TIME CHANGE
VB. OUTPUT WADING
30.0

0.6

II

AMBIENT TEMPERATURE rCI

2.5

0.0
0.0

25

Vee =5.0V
TA = 25'C

/

::>
u

OJ

Vee =5.0V

-$

TYPICAL POWER·ON CURRENT
w. SUPPLY VOLTAGE

1.0

/'

o

SUPPLY VOLTAGE {VI

4.0

~

IU

II:
II:

0.6
4.0

~

3.0

vs. OUTPUT VOLTAGE

!

:::;

............

2.0

140

1.4

c
:f

c

"-

OUTPUTS~CURRENT

NORMALIZED ACCESS TIME
VB. AMBIENT TEMPERATURE

:f 1.2

Vee = 5.0 V
TA = 25'C

OUTPUT VOLTAGE (VI

1.6

1.3

~

1.0

AMBIENT TEMPERATURE {'CI

NORMALIZED ACCESS TIME
SUPPLY VOLTAGE

:::; 1.1

~

0

0.0
5.0

4.5

VB.

...
i
S!

60

::>

0.2

1.4

j

80

u
u

II:

z

lsa

100

II:
II:

...

0.8

SUPPL Y VOLTAGE {VI

Q

...!Z
::>

Q

0.0
4.0

!

~

c

:II!

3.0

C

Q

0.2

~
II:
Q
z

120

~

1.0

!I
j

V

V

1.2

./

•

OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE

VB.

VB.

600

CAPACITANCE

600
(OF I

1000

~

~
~
10
o

20

.....-

30

40

CYCLE FREQUENCY (MHz}
0164-11

2·51

~

CY7C128A
~~~=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=
Ordering Information
Speed
(ns)

20

25

35

45

55

Ordering Code

Type

Operating
Range
Commercial

Package

CY7CI28A-20PC

P13

CY7CI28A-20VC

Vl3

CY7CI28A-20DC

014

CY7CI28A-20LC

L53

CY7CI28A-25PC

Pl3

CY7CI28A-25VC

V13

CY7CI28A-25DC

D14

CY7CI28A-25LC

L53

CY7CI28A-25DMB

D14

CY7CI28A-25LMB

L53

CY7CI28A-35PC

P13

CY7CI28A-35VC

Vl3

CY7CI28A-35DC

D14

CY7CI28A-35LC

L53

CY7CI28A-35DMB

D14

CY7CI28A-35LMB

L53

CY7CI28A-35KMB

K73

CY7CI28A-45PC

P13

CY7CI28A-45VC

V13

CY7CI28A-45DC

D14

CY7CI28A-45LC

L53

CY7CI28A-45DMB

014

CY7CI28A-45LMB

LS3

CY7CI28A-45KMB

K73

CY7CI28A-55PC

P13

CY7CI28A-55VC

V13

CY7C128A-55DC

D14

CY7CI28A-55LC

L53

CY7CI28A-55DMB

014

CY7CI28A-55LMB

L53

CY7CI28A-55KMB

K73

Commercial

Military
Commercial

Military

Commercial

Military

Commercial

Military

2-52

~

CY7C128A

~r~~===================
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

VILMax.

1,2,3

IJX

1,2,3

IOZ

1,2,3

Icc

1,2,3

ISB

1,2,3

tI

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

taHA

7,8,9,10,11

tACE

7,8,9,10,11

tDOE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tscE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpwE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

Document #: 38-00094

2-53

CY7C130/CY7C131
CY7C140/CY7C141

CYPRESS
SEMICONDUCTOR

1024

Features

Functional Description

• 0.8 micron CMOS for optimum
speed/power
• Automatic power-down
• TIL compatible
• Capable of withstanding greater
than 2001V electrostatic
discharge
• Fully asynchronous operation
• Master CY7C130/CY7C131
easily expands data bus width to
16 or more bits using SLAVE
CY7CI40/CY7CI41
• BUSY output flag on CY7C130/
CY7C131j BUSY input on
CY7CI40/CY7CI41
• !NT flag for port to port
communication

The CY7C130/CY7Cl40/CY7C131/
CY7C141 are high speed CMOS lK x
8 Dual Port Static RAMS. Two ports
are provided permitting independent
access to any location in memory. The
CY7C130/CY7C131 can be utilized as
either a stand-alone 8-bit Dual Port
Static RAM or as a MASTER Dual
Port RAM in conjunction with the
CY7Cl40/CY7C141 SLAVE Dual
Port device in systems requiring 16-bit
or greater word widths. It is the solution to applications requiring shared or
buffered data such as cache memory
for DSP, Bit-Slice, or multiprocessor
designs.
Each port has independent control
pins; Chip Enable (CB), Write Enable

Logic Block Diagram

8 Dual Port
Static RAM

~, and Output Enable (OE). Two
flags are provided on each port, BUSY
and INT. BUSY signals that the port is
trying to access the same location currently being accessed by the other port.
INT is an interrupt flag indicating that
data has been placed in a unique location by the other port. An automatic
power down feature is controlled independently on each port by the Chip Enable (CE) pin.
The CY7C130/CY7Cl40 are available
in both 48-pin DIP and 48-pin LCC.
The CY7C131/CY7C141 are available
in both 52-pin LCC and PLCC.
A die coat is used to insure alpha immunity.

Pin Configuration

r----(:J::::r;:R~R
CE"

iiL
R/WL
BUSYL

~

'tL===t¢::;--,
An
I/OOL

X

3

iNTL

04-

OEt,.

5

---+.,..;:::-1-1":::::::::1<....

I/O" --~:....t.:::...I-L~....JI.-, ["""1"'-.::..:....J-L.=:~+--- VO"
BUSYL(1)

AsL

BUSYR<1)

---I::-+r-=::-l

"L ---f'+l=::.J

1.:::-14-::1---

'5R

L:.::'::'.J+''I--- "oR

0114-1

Notes:
1. CY7C 130/CY7C 131 (Master): BUSY is open drain output and requires pullup resistor.
CY7CI40/CY7CI41 (Slave): BUSY is input.
2. Open drain outputs: pullup resistor required.

Selection Guide

Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
Shaded area contains preliminary information.
2-54

DIP
Top View

0114-2

5n
.

CY7C130/CY7C131
CY7C140/CY7C141

~OO~================================================================

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... >2001V
Storage Temperature ............... -65·C to + 150·C
(Per MIL-STD-883 Method 3015)
Ambient Temperature with
Power Applied .................... - 55·C to + 125·C
Latch-up Current .......................... > 200 mA
Supply Voltage to Ground Potential
Operating Range
(pin 48 to Pin 24) .................... - 0.5V to + 7.0V
Ambient
DC Voltage Applied to Outputs
Range
Vee
Temperature
in High Z State ...................... -0.5V to + 7.0V
Commercial
O'C to +70'C
5V ±IO%
DC Input Voltage ................... - 3.5V to + 7.0V
Military[6]
- 55°C to + 125°C
5V ±IO%
Output Current into Outputs (Low) ............. 20 mA

Electrical Characteristics Over Operating Range[7]
Parameters

Description

Test Conditions

lOS
Icc

Vee Operating
Supply Current

CE = VIL
Outputs Open
f=

ISB!

Standby Current
Both Ports, TTL Inputs

CEL and CER :;, VIH
f = fMAX

ISB2

Standby Current
One Port, TTL Inputs

CELor CER :;, VIH
Active Port Outputs Open
f= fMAX

ISB3

Both Ports CEL and CER
Standby Current
:;, Vee - 0.2V
Both Ports, CMOS Inputs VIN:;' Vee - 0.2Vor
VIN";; 0.2V,f= 0

Standby Current
One Port, CMOS Inputs

ISB4

rnA

Military

One Port CEL or CER
:;, Vee - 0.2V
VIN :;, Vee - 0.2V or VIN ,,;; 0.2V 1 - - - - t~i~rts Outputs Open
Military

15

15

85

70

105

85

rnA

Shaded area contains preliminary information.

Capacitance [4]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Condtlons

Max.

TA = 25°C, f = 1 MHz
Vee = 5.0V

10

Notes:
3. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may
affect these parameters.
5. BUSY and !NT pins only.

Units
pF

10

6. TA is the "instant on" case temperature.
7. See the last page of this specification for Group A subgroup testing
information.

2-55

II

fin

CY7C130/CY7C131
CY7C140/CY7C141

.

~~==~~~~~~~~~~~~~~~~~~~~~~~~~~~==~=
AC Test Loads and Waveforms
5vo-------~AA~

OUTPUT ~----_-------1

OUTPUT ~----......- - - - - -..

INCLUDING
JIG AND

I

5V

R18830

R18830
5V~--------~~~

_~280fi

BUSY

OR
30 pF

R2
3470

SCOPE

5pF
INCLUDINl
JIG AND
.
SCOPE

R2
3470

iiiiT

I

~

30PF
0114-4

0114-5

Figure 1
Equivalent to:

Figure 3. BUSY Output Load
(CY7C130/CY7C131 Only)

Figure 2

THEVENIN EQUIVALENT
25011
OUTPUT

O---"I"M

ALL INPUT PULSES

01.40Y
0114-7

3.0V=;?[
90%

GND

10%

50.

b

50'

0114-6

Figure 4

Switching Characteristics Over Operating Range!7, 9]
Parameters

Deseription

Units

Shaded area contains preliminary information.
2-56

(in
.

CY7C130/CY7C131
CY7C140/CY7C141

~U~===================================================================

Switching Characteristics Over Operating Range[7, 9]
Parameters

(Continued)

-----------r----------r----------r---,

Description

Units

Shaded area contains preliminary information.
• CY7C140/CY7C141 Only
Not••:
8. Data I/O pins enter high impedance state, as shown when OE is held
LOW during write.
9. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels ofOV to 3.0V and output
loading of the specified lor/IOH and 30 pF load capacitance.
10. tHZOE, tHZcE, and tHZWE are specified with CL = 5 pF in Figure 2.
Transition is measured ± 500 m V from steady state voltage.
II. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
12. The internal write time of the memory is defined by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.

13.
14.
15.
16.

WE is HIGH for read cycle.
Device is continuously selected OE, CE = VIL.
Address valid prior to or coincident with CE transition LOW.
A write operation on Port A, where Port A has priority, leaves the
data on Port B's outputs undisturbed until one access time after one
of the following:
A. 'BUSY on Port B goes HIGH.
B. Port B's address toggled.
C. CE for Port B is toggled.
D. WE for Port B is toggled.
17. These parameters are measured from the input signal changing, until
the output pin goes to a high impedance state.
18. For master/slave combinations twc = tpWE + tBLA.

Switching Waveforms
Read Cycle No.1 (Notes 13, 14)
Either Port Address Access

ADDRESS
DATA OUT

_=*- -.;. .:~_:~=. .; .-to=H'; ';"'A:~=-:" ':A :::':::i':-,=~~=~~-=-~~-=-~~-=-~~*_-=--=--=-===
:::::?:,

PREVIOUS DATA VALID

~

DATA VALID

0114-8

2-57

EI

5n

CY7C130/CY7C131
CY7C140/CY7C141

. cm<

~"h
'-.~,~

CEL
CER
BUSYR

X

ADDRESS MATCH

t,}
0114-14

CER Valid First:
ADDRESS
LAND R

CER
CEL
BUSYL

==><

X

ADDRESS MATCH

~"h."'~

t,}
0114-15

2-59

fin

CY7C130/CY7C131
CY7C140/CY7C141

. .

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Switching Waveforms (Continued)

Busy Timing Diagram No.2 (Address Arbitration)

l

Left Address Valid First:
t RC OR twc

--

ADDRESS L

ADDRESS MATCH

ADDRESS MISMATCH

X

-tpsADDRESS R
f4--tBLA

I--tBHA

BUSYR
0114-16

Right Address Valid First:
t RC OR twc
ADDRESS R

ADDRESS MATCH

- - _ tps -

ADDRESS MISMATCH

X

;e::::.

I-

ADDRESS L

f4--tBLA

I--tBHA
0114-17

Busy Timing Diagram No.3
Write with BUSY (Slave: CY7Cl40/CY7C141) (Note 19):

-ij4------ -----4--1
tpWE

,,=

r= . . ~,....---

--t_tW_B_=r
_ _ _ _ _ _ _ _ _....

0114-11

2-60

fin

CY7C130/CY7C131
CY7C140/CY7C141
~~============~~~

• CYPRESS

Switching Waveforms (Continued)
Interrupt Timing Diagrams
Left Side Sets INTR:

-

-

~

UX

lk

I--- tSA

X

I--tHA -

t INS - - -

/

~tEINS"'"

WE L

fJI

twc
WRITE 3FF

lk
-,:::::: tWINS
0114-18

Right Side Clears INTR:

INTR

----------------------------~

0114-19

Right Side Sets INTV

--

twc

tiNS -----

X

EO{

WRITE 3FE
I--tHA -

\:

/

~tEINS"'"

\:

I--tSA~

tWINS
0114-20

Left Side Clears INTV

INTL ____________________________________

~

0114-21

2-61

fin
.

CY7C130/CY7C131
CY7C140/CY7C141

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=

Typical DC and AC Characteristics
NOR~~SUPPLYCURRENT

VB.

1.2

Ie/,

~ 1.0
0.8

V

N

:; 0.6
C

./

1.2

..

1.0

.;

0.8

r--..........

Jt
N

:;

~

=e

a: 0.4
0

a:

0.2

0.6

4.5

5.0

0.4

ACCESS TIME
SUPPLY VOLTAGE

..

:1

N

w

............

1.0

1.4

=ea:

-

r--

Q

z

0.8
4.5

~

zw

100

/

a:
a:

:l

Vee -S.OV

60

..
I-

40

0

20

:>
:>

125

!

2.0

...

w

N

;C
!:i

1.5

=e
1.0
0.5

-

/

V

1.0

2.0

3.0

5.0
0.0

4.0

SUPPLY VOLTAGE (VI

/

S.O

200

vee

400

4.0

3.0

'----'T'---'---'
Vee = 5.0 V
TA = 25'C
V'N-O.5V

1 . 0 1 - - - - i - - - - + - - . . . . ,...

600

=4.60 V

CAPACITANCE (.FI

800

i

z 0.751----:1:.,.0---+----1

TA = 25°C

/

o

2.0

iiiN

/

/

1.0

NORMALIZED Icc
vs. CYCLE TIME

II

/

~ 10.0

/

/

OUTPUT VOLTAGE (VI

1.25

15.0

/

0.0

~

20.0

Vee -S.OV
TA • 2S'C

V

"inz

30.0

Q

./

I-

25.0

4.0

V

/

U

25

'"

3.0

.1

80

TYPICAL ACCESS TIME CHANGE
VS. OUTPUT LOADING

2.S

0.0
0.0

i

120

AMBIENT TEMPERATURE ('CI

TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE

!il

/

-55

SUPPLY VOLTAGE IVI

3.0

"

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

0.6

6.0

5.5

S.O

1.0

0.8

2.0

1.0

VB.

I-

./

1.2

C

TA - 25'C

0.9

4.0

Vee -S.OV
TA - 25'C

140

:;

.............

i"-.

OUTPUT VOLTAGE (VI

NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE

N

a:

0.0

VB.

w

C

o

12S.0

1.6

1.1

20

AMBIENT TEMPERATURE ('CI

1.3

C

"

40

:l
:l

25.0

Q

:;

....
51

Vee -5.0V
V,N -5.DV

6.0

5.5

Q

E

80

a:

0

:1 1.2

z

u

0.0

1.4

0

80

:l

NO~IZED

=e
a:

a:
a:

...w

SUPPL Y VOLTAGE (VI

VB

100

':l

0.2 r--IS8

IS8

0.0
4.0

:;

~

!il

Z

..

C

.

!
zw

Q

w

OUTPUT SOURCE CURRENT
VB. OUTPUT VOLTAGE
120

~

/'

U

Jt
Q

w

NORMALIZED SUPPLY CURRENT
VB. AMBIENT TEMPERATURE

SUPPLY VOLTAGE

1.4

1000

0.50110~_---,120,.....--..,30,.,..--....J4O

CYCLE FREQUENCY (MHz)
0114-23

2-62

&n
.

CY7C130/CY7C131
CY7Cl40/CY7C141

~~u~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Pin Configurations

A1L
A2L
A3L
A4L
ASL
AOL
A7L
ABL
A9L
I/ODL
1/0 1L
1/0 2L
1/0 3L

7 6 5 4 3 2 ~525150494847
8
46
9
4S
44
10
11
43
12
42
13
41
40
14
15
39
16
38
17
37
18
36
19
35
20
34
21222324252627282930313233

OER

6 5 4 3 2 CJ484746454443

As.

A1L

A1•
A2•
A3•
A4•
A••
Ao.
A7•
AS.
A9•

A2l
A3l
A4L

AgL
ASL
A7L
ASL

A9l
I/ODL
1/01L
1/02L

He
1/°7.

0114-3

52-Pin LCC/PLCC
Top View

7

As.

8
9

A1•
A2.
A3.

42
41
40
3.
10
38
11
37
12
36
13
14
35
34
15
16
33
17
32
31
18
192021222324252627282930

48-PinLCC
Top View

•

A4•

A••
Ao.
A7.
As.

Ag.
1/°7.
1/°0•

0114-22

Ordering Information

Military

Military
45

45

Commercial

Military

Military
55

Commercial

Commercial

55

Commercial

Military

Military

45

55

Shaded area contains preliminary information.
2-63

fiA

CY7C130/CY7C131
CY7C140/CY7C141

CYPRESS

S~!OO®ucr~~~~~~~~~~~~~~~~~~~~~~~~~~~~====~~==

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

Parameters

Subgroups

VOH

1,2,3

ISB4

1,2,3

VOL

1,2,3

Subgroups

Parameters

Subgroups

tAA

7,8,9,10,11

BUSY/INTERRUPT
TIMING (Continued)

tOHA

7,8,9,10,11

tOINR

7,8,9,10,11

tACE

7,8,9,10,11

tEINR

7,8,9,10,11

tOOE

7,8,9,10,11

tINR

7,8,9,10,11

VIH

1,2,3

VIL Max.

1,2,3

IIX

1,2,3

loz

1,2,3

los

1,2,3

Icc

1,2,3

ISB!

1,2,3

ISB2

1,2,3

ISB3

1,2,3

Switching Characteristics
Parameters
READ CYCLE

BUSY TIMING

WRITE CYCLE
tSCE
tAW
tHA

7,8,9,10,11

tWB[ll

7,8,9,10,11

7,8,9,10,11

tWH

7,8,9,10,11

7,8,9,10,11

tBOO

7,8,9,10,11

tO~~

7,8,9,10,11

twoo

7,8,9,10,11

tSA

7,8,9,10,11

tpwE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

BUSY/INTERRUPT
TIMING
tBLA

7,8,9,10,11

tBHA

7,8,9,10,11

tBLC

7,8,9,10,11

tBHC

7,8,9,10,11

tps

7,8,9,10,11

tWINS

7,8,9,10,11

tEINS

7,8,9,10,11

tINS

7,8,9,10,11

Note:
1. CY7CI40 only.

Document #: 38-00027-D

2-64

CY7C132/CY7C136
CY7C 142/CY7C146

CYPRESS
SEMICONDUCTOR

2048

Features

Functional Description

• 0.8 micron CMOS for optimum
speed/power
• Automatic power-down
• TIL compatible
• Capable of withstanding greater
than 2001V electrostatic
discharge
• FuUy asynchronous operation
• MASTER CY7C132/CY7C136
easily expands databus width to
16 or more bits using SLAVE
CY7C142/CY7C146
• 'BUSY output flag on CY7C132/
CY7C136; BUSY input on
CY7C142/CY7C146
• INT flag for port to port
communication (LCC/PLCC
versions)

The CY7C 132/CY7C 142/CY7C 136/
CY7Cl46 are high speed CMOS 2K x
8 Dual Port Static RAMs. Two ports
are provided permitting independent
access to any location in memory. The
CY7C 132/CY7C 136 can be utilized as
either a stand-alone 8-Bit Dual Port
RAM or as a MASTER Dual Port
RAM in conjunction with the
CY7C142/CY7C146 SLAVE Dual
Port device in systems requiring 16-Bit
or greater word widths. It is the solution to applications requiring shared or
buffered data such as cache memory
for DSP, bit-slice or multiprocessor designs.
Each port has independent control
pins; Chip Enable (CE), Write Enable
(WE), and Output Enable (OB). BUSY

Logic Block Diagram

X

8 Dual Port
Static RAM

flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin LCC
or PLCC versions. BUSY signals that
the port is trying to access the same
location currently being accessed by
the other port. On the LCC/PLCC
versions, INT is an interrupt flag indicating that data has been placed in a
unique location by the other port.
An automatic power-down feature is
controlled independently on each port
by the Chip Enable (CE) pin.
The CY7C132/CY7C142 are available
in both 48-pin DIP and 48-pin LCC.
The CY7C136/CY7CI46 are available
in both 52-pin LCC and 52-pin PLCC.
A die coat is used to insure alpha immunity.

Pin Configuration

'~L:~:::jC:>-------l
r-------<:Jb:::~:R~,
CE
CE,
L

OEL~~

OER

r-;:::t¢=== A"

A OL
'

A,OR

A7L

I/O" ----I~=l-f==1+-'
1/07L

~r:::::=l-f=l1:t----- I/0..

----+'-I...:::..Jf-L.::;....J'r-

BUSYL(I) _ _......_ _ _..J

L..::.:.....H..:::..J-'.....- - -

----1:+1'-:::::-1
A" ----I=+I...::::::...J
A"

I/o,.

1...-_ _ _- - + BUSY,.(I)

A..

r.=-1+:I---- AOR
L.:::::J+=t----

A..

AS,
A..

AOR

A"
As.
31

I/O SR
I/OSR
I/0 4R

I/0 3R
I/OlR

Notes:

0106-1

I. CY7C132/CY7C136 (MASTER):JUSY is open drain output and requires pullup resistor.

CY7C142/CY7C146 (SLAVE): B SY is input.
2. Open drain outputs: pullup resistor required.

I/O,R
I/OOR

GND

DIP
Top View

Selection Guide

Maximum Operating
Current (rnA)
Maximum Standby
Current (rnA)
Shaded area contains preliminary information.
2-65

0106-2

fin

CY7C132/CY7C136
CY7C142/CY7C146

..

.~~====================

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... > 2001 V
(per MIL-STD-883 Method 3015)
Latch-up Current. ......................... > 200 rnA

Storage Temperature ............... -65'C to + l50"C
Ambient Temperature with
Power Applied .................... - 55'C to + 125'C
Supply Voltage to Ground Potential
(pin 48 to Pin 24) .................... -0.5Vto +7.0V
DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V
DC Input Voltage ................... -3.5Vto +7.0V
Output Current into Outputs (Low) ............. 20 mA

Operating Range
Range
Commercial
Military!71

Ambient
Temperature

Vee

O'Cto +70'C

5V ±IO%

-55'Cto +125'C

5V ±IO%

Electrical Characteristics Over Operating Range[8]
Parameters

Description

Test Conditions

los

Output Short [3]
Circuit Current

lee

Vee Operating
Supply Current

ISBI

Standby Current
Both Ports, TTL Inputs

ISB2

Standby Current
One Port, TTL Inputs

ISB3

Both Ports CEL and CER
;;, Vee - 0.2V
Standby Current
Both Ports, CMOS Inputs VIN;;' Vee - 0.2Vor
VIN ,;;: 0.2V, f = 0

mA

Standby Current
One Port, CMOS Inputs

ISB4

Units

rnA
Military

One Port CEL or CER
;;, Vee - 0.2V
VIN;;' Vee - 0.2Vor
VIN';;: 0.2V
Active Ports Outputs Open Military
f=

15

15

85

70

rnA
105

85

Shaded area contains preliminary information.

Capacitance [4]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions
TA = 25'C, f
Vee = 5.0V

= I MHz

Max.
10

Units

pF

10

Notes:

6. 'BiJSY and tNT pins only.
7. TA is the "instant on" case temperature.
8. See the last page of this specification for Group A subgroup testing
information.

3. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may
affect these parameters.
s. LCC version only.

2-66

&l
.

CY7C132/CY7C136
CY7C142/CY7Cl46

~aoR================================================================

AC Test Loads and Waveforms
R189311

R189311
5Vo---------~~,
OUTPUT

0-----_-------+

'NCLUD'NGI30 pF
JIG AND
SCOPE

5V

5Vo---------~~,

OUTPUT

R2
34711

5pF
'NCLUD'Nl
JIG AND
SCOPE
_

0106-4

Figure 1

_~280.n

0-----_-------+

til

BUSY

R2
34711

OR

INT

I

0106-5

30P

'

Figure 2

0106-6

Figure 3. BUSY Output Load
(CY7C132/CY7C136 Only)
Equivalent to:

THE-VENIN EQUIVALENT
ALL INPUT PULSES

2500
OUTPUT

O------'l"NI.or---C

~~k

CEL
CER

""'---=il

BUSYR

CER Valid First:
ADDRESS
LAND R

CER
CEL
BUSYL

:::::::>C

X

ADDRESS tolATCH

L
u
w
u
II:
:>

60

CI)

40

'" ""

I-

...:>

0.2 0 - 1 . 8

1.8

4'
i
I-

0

0.4

z

0.2

I-

:>

20

0

0.0
4.0

0.0
4.5

5.0

6.0

5.5

o
-55

NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE

NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE

.

:!

.

..

:!

1.2

0

@
N

::;

.............

z

1.0

r----.....

0.9

0.8
4.0

4.5

---

II:

-

i

I-

100

1.2

II:

80

""z
in

60

I-

40

./

1.0

0
Z

O.B

I"

6.0

30.0

2.5

25.0

2.0

!

1.5

"" 15.0
;(


0

1.0
0.5

_/

0.0
0.0

1.0

2.0

3.0

/

20.0

/

~ 10.0

/

4.0

SUPPL V VOLTAGE (V)

125

25

~

:IE

II:

Vee = 5.0 V

5.0

0.0

5.0

V

V

o

200

4.0

--

I

V'
/

I

/
V
o

Vee - 5.0 V

/

TA = 25"C

/

20

0.0

1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING

3.0

0

::;

:>

AMBIENT TEMPERATURE ('C)

TYPICAL POWER·ON CURRENT
VS. SUPPLY VOLTAGE

N

/

-55

SUPPLY VOLTAGE (V)

.E

/

0.6

5.5

5.0

li

120

...II:z

 0
a: m
_-c~
-J

All
A2l
A3l
A4L
ASl
ASl
A7l
ABl
Agl
1/0Dl
I/Oll
1/0 2l
1/0 3l

i

7 6 5 4 3
Ej52 51 50 49 48 47
8
46
9
45
44
10
11
43
12
42
13
41
40
14
15
39
16
38
17
37
18
36
19
35
20
34
21222324252627282930313233

(

6 5 4 3 2 l!l48474645444342

AOR
AIR
A2R
A3R
A4R
A5R
ASR
A7R
ABR
AgR
Ne
1/07,

All
A2l
A3l
A4L
A5l
Asl
A7l
ABl
Agl
1/00l
I/Oll
1/0 2l

0106-23

52·Pin LCCIPLCC

f

.f I~ Ji '!111 Jlllf~ ~ JI~

0Et,

7
8
41
9
40
10
39
II
38
12
37
13
3s
14
35
15
34
16
33
17
32
18
31
192021222324252627282930

48·PinLCC

Top View

"oR
AIR
A2R
A3R
A4R
AsR
ASR
A7R
ABR
AgR
1/07R
I/OSR

0106-24

Top View

Ordering Information

Military
45

Military
45

Commercial

Military
55

Commercial

Military

Commercial

55

Military

Commercial

Military

Shaded area contains preliminary information.
2-74

&n

CY7C132/CY7C136
CY7C142/CY7C146
~~NDUcroR ~~~~~~~~~~~~~~~~~~~~~~~~~====~==~=======

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

Parameters

Subgroups

VOH

1,2,3

ISB4

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

loz
los

1,2,3

Icc

1,2,3

ISB!

1,2,3

ISB2

1,2,3

ISB3

1,2,3

Subgroups

Parameters

Subgroups

tAA

7,8,9,10,11

BUSY/INTERRUPT
TIMING (Continued)

toHA

7,8,9,10,11

toINR

7,8,9,10,11

7,8,9,10,11

tEINR

7,8,9,10,11

7,8,9,10,11

tINR

7,8,9,10,11

1,2,3

Switching Characteristics
Parameters
READ CYCLE

tACE
tOOE

BUSY TIMING

WRITE CYCLE
tscE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpWE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

tWB[I]

7,8,9,10,11

tWH

7,8,9,10,11

tBOO

7,8,9,10,11

tO~~

7,8,9,10,11

twoo

7,8,9,10,11

BUSY/INTERRUPT
TIMING
tBLA

7,8,9,10,11

tBHA

7,8,9,10,11

tBLC

7,8,9,10,11

tBHC

7,8,9,10,11

tps

7,8,9,10,11

tWINS

7,8,9,10,11

tEINS

7,8,9,10,11

tINS

7,8,9,10,11

Note:
\. CY7Cl42 only.

Document #: 38-00061-C

2-75

tI

CY7C147

CYPRESS
SEMICONDUCTOR

4096

Features

Functional Description

• Automatic power-down when
deselected

The CY7C147 is a high performance
CMOS static RAM organized as 4096
words by 1 bit. Easy memory expansion is provided by an active LOW chip
enable (CE) and three-state drivers.
The CY7C147 has an automatic power-down feature, reducing the power
consumption by 80% when deselected.

• CMOS for optimum
speed/power

• High speed-25 ns
• Low active power
- 440 mW (commercial)
- 605 mW (military)
• Low standby power
-55mW
• TTL compatible inputs and
outputs

Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW.
Data on the input pin (01) is written
into the memory location specified on
the address pins (Ao through All).

X

1 Static R/W RAM
Reading the device is accomplished by
taking the chip enable (CE) LOW,
while write enable (WE) remains
HIGH. Under these conditions the
contents of the memory location specified on the address pins will appear on
the data output (DO) pin.
The output pin stays in high impedance
state when chip enable (CE) is HIGH
or write enable (WE) is LOW.

• Capable of withstanding
greater than 2000V
electrostatic discharge

Logic Block Diagram

Pin Configurations
r-------2oo1V
(Per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied .................... - 5SoC to + 12SoC

Latchup Current .......................... > 200 rnA

Supply Voltage to Ground Potential
(pin 18 to Pin 9) ..................... -O.SV to +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to + 7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial

Output Current into Outputs (Low) ............. 20 mA

Military [3]

Ambient
Temperature

Vee

O"Cto +70"C

SV

- S5°C to + 12SoC

5V

± 10%
± 10%

Electrical Characteristics Over Operating Range[4]
Parameters

7C147-25

Test Conditions

Description

Min.
VOH

Output HIGH Voltage

Vee = Min.

IOH = -4.0mA

VOL

Output LOW Voltage

Vee = Min.

IOL = 12.0mA

VIH

Input High Voltage

2.0

VIL

Input Low Voltage

-3.0

IIX

Input Load Current

GND:S: VI:S: Vee

-10

Ioz

Output Leakage
Current

GND:S: Vo:S: Vee
Output Disabled

-so

los

Output ShortU]
Circuit Current

Vee = Max.

VOUT = GND

lee

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

Commercial

Automatic CE[2]
Power Down Current

Max. Vee,

Commercial

CE:..:c

1/02

A.
A.

2~1S17'
1/0 3

A4
A3
AO
A,
A2

cs

3
4
5
6
7

16
15
14
13
12
S 9 1011

I~ ~I~

WE

"

0001-1

AS

Ag
1/00
1/0 ,
1/0 2

0'"

~

0001-3

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)

Commercial

Maximum Standby
Current (rnA)

Commercial

7Cl48-25

7Cl48-35

7CI48-45

7C149-25

7C149-35

7C149-45

25
90

35
80
110

45
80

25
90

35
80

45
80

110

110

110

15

10

10

10

10

Military
Military

2-83

•

5n
.

CY7C148
CY7C149

~UaoR================================================================

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .. , ............ -65°C to

+ 150°C

Ambient Temperature with
Power Applied .................... - 55°C to

+ 125°C

Supply Voltage to Ground Potential
(Pin 18 to Pin 9) ..................... -O.SV to

Static Discharge Voltage
(PerMIL-STD-883 Method 3015) ............. >2001V
Latchup Current. . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA

+ 7.0V

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to

Operating Range

+ 7.0V
+ 7.0V

DC Input Voltage ................... - 3.0V to

Output Current into Outputs (Low) ............. 20 rnA

Range

Ambient
Temperature

Commercial
Military [I 11

OOCto +700C
- SsoC to + 12SoC

VCC
SV ±1O%
SV ±1O%

Electrical Characteristics Over Operating Range[12]
Parameters

Description

7Cl48/9-25

Test Conditions

= 2.4V
= 0.4V

= 4.SV

IOH
IOL

Output High Current

VIR

Input High Voltage

VIL

Input Low Voltage

IIX

Input Load Current

loz

CliO

Output Leakage Current GND"; VO"; Vee Output Disabled
Input Capacitance[13]
Test Frequency = 1.0 MHz
Input/Output
TA = 2SoC, All Pins at OV, Vee = 5V
Capacitance[13]

Icc

Vee Operating
Supply Current

Max. Vee, CS ,,; VIL
Output Open

ISB

Automatic CS
Power Down Current

Max. Vee,
CS:?: VIR

7C148
only

Commercial

Peak Power-On
Current

Max. Vee,
CS:?: VIR[3]

7C148
only

Commercial

Output Short
Circuit Current

GND"; Vo";
Vee[lO]

VOH
VOL

Output Low Current

CI

IpO
los

Vee

Min. Max.
-4
8

GND"; VI"; Vee

7C148/9-35, 45
Min.
-4

rnA

rnA

8

2.0
-3.0

6.0

2.0

6.0

0.8

-3.0

0.8

V

-10

10

-10

10

/-LA

-SO

SO

-SO

SO

/-LA

S

S

7

7

V

pF

Commercial

90

Military

80

rnA

110
IS

Military

10

rnA

10
15

Military

10

rnA

10

Commercial
Military

Notes:
I. Test conditions assume signal transition times of 10 ns or less, timing
reference levels of I.SV, input pulse levels of 0 to 3.0V and output
loading ofthe specified IOL/IoH and 30 pF load capacitance. Output
timing reference is I. SV.
2. The internal write time of the memory is defined by the overlap of
~ low and WE low. Both signals must be low to initiate a write and
either signal can terminate a write by going high. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
3. A pull up resistor to Vee on the CS input is required to keep the
device deselected during Vee power up. Otherwise current will exceed values given (eY7CI4S only).
4. Chip deselected greater than 25 ns prior to selection.
5. Chip deselected less than 25 ns prior to selection.

Units

Max.

±275

±275

rnA

±350

6. At any given temperature and voltage condition, tHZ is less than tLZ
for all devices. Transition is measured ± 500 mV from steady state
voltage with specified loading in Figure lb.
7. WE is high for read cycle.
S. Device is continuously selected, CS = VIL.
9. Address valid prior to or coincident with CS transition low.
10. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
11. TA is the "instant on" case temperature.

12. See the last page of this specification for Group A subgroup testing
information.
13. Tested iuitially and after any design or process changes that may
alTect these parameters.

AC Test Loads and Waveforms
R148m
5 v O-----'\M--,
OUTPUT

R14810

5V

0--.....----+

I

30 pF

ALL INPUT PULSES

OUTPUT o--~---'"
R2

INCLUDING

_JIG AND
- SCOPE

0----"""......,

3.0V-----.J!~~--~L

6pF

265"

R2

255n

I,NCLUO,NG

_
-

-:::-~~~~D

GNO

-=-

Figure 1a

';10ns
0001-5

::5:10n8

0001-4

Figure 1b

Equivalent To:

Figure 2
THEVENIN EQUIVALENT
16m

OUTPUT 0>----..,,"'
.."'''.---_01.73V

0001-12

2-84

fin~®u~================================================================
CY7Cl48
CY7C149

.

Switching Characteristics Over Operating Range[J2]
Parameters

7Cl48/9-25

Description

Min.

Max.

7Cl48/9-35
Min.

Max.

7Cl48/9-45

Min.

Units

Max.

READ CYCLE
tRC

Address Valid to Address Do Not
Care Time (Read Cycle Time)

tAA

Address Valid to Data Out
Valid Delay (Address Access Time)

tACSI
tACS2

Chip Select Low to Data Out Valid
(CY7C148 only)

tACS

Chip Select Low to Data Out Valid
(CY7C149 only)

tLZ[6)

Chip Select Low to
Data Out On

25

35

45

25

35

25[4)

35

45

30[5)

35

45

15

15

20

45

7Cl48

8

10

10

7CI49

5

5

5

tHZ[6)

Chip Select High to Data
Out Off

0

toH

Address Unknown to Data Out
Unknown Time

0

tpo

Chip Select High to
Power-Down Delay

7CI48

tpu

Chip Select Low to
Power-Up Delay

7CI48

ns

15

0

20

0

0
20

ns
ns
ns

20

5
30

ns

ns
ns

30

ns

0

0

0

ns

WRITE CYCLE
twc

Address Valid to Address Do Not
Care (Write Cycle Time)

25

35

45

ns

twp[2)

Write Enable Low to
Write Enable High

20

30

35

ns

tWR

Address Hold from Write End

5

5

5

ns

twz[6)

Write Enable to Output
inHighZ

0

tow

Data in Valid to Write Enable High

12

20

20

ns

tOH

Data Hold Time

0

0

0

ns

tAS

Address Valid to Write
Enable Low

0

0

0

ns

tCW[2)

Chip Select Low to Write
EnablcHigh

20

30

40

ns

tow[6)

Write Enable High to Output
in LowZ

0

0

0

ns

tAW

Address Valid to End of Write

20

30

35

ns

8

0

10

0

15

ns

Switching Waveforms
Read Cycle No.1 (Notes 7, 8)

~- - - ¥ _
~-----------------------tRC------------------------~j.

ADDRESS

DATA OUT

______~_______tO_H____t_AA_~I-----------------------------------PREVIOUS DATA VALID

~

DATA VALID

0001-6

2-85

II

&n
.

CY7C148
CY7C149

.~~=============================================================

Switching Waveforms (Continued)
Read Cycle No.2 (Notes 7, 9)
IRe

~ It-

..,'tACS

_IHZ_

ILz:l
HIGH IMPEDANCE

DATA OUT

1

HIGH
IMPEDANCE

,, ,,

II I

I

I

I

DATA VALID

I----'pu

Vee _ _ _ _ _ _
SUPPLY
CURRENT
_

-100

----j

ICC

~ISB

50%

0001-7

Write Cycle No.1 (WE Controlled)
Iwe
ADDRESS

~II

~~

_1\

~\'

lew

'\\\

~IIIII rIllI
lAW
lAS

IWp

m\
'I

~~

~w

f

DATA 110

I I I II.

IWR-

DATA-IN VALID

_IWz

. J) o!__

DATA 110 _ _ _ _ _ _ _ _ _D_AT_A_U_N_D_E;..FI_N_ED_ _ _ _ _ _ _ _

'I
-~

·. .(~\o

...;.;H;.;IG;..H;..IM;.;P.;E;;.DA;..N.;.;C.;E_ _ _

_ _ _ _ __
0001-8

Write Cycle No.2 (CS Controlled)
~--------------------------twe--------------------------~

*r

.'. IOH1_ _ _ _ _ __

DATA 110 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

::A-IN VALID

t:=twz--i

J)o------------------

--------------------~
DATA 110

DATA UNDEFINED

Note: If

HIGH IMPEDANCE

cs goes high simultaneously with WE high, the output remains in a high impedance state.
2-86

0001-9

&n
.

CY7Cl48
CY7C149

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~;

Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE
1.2

./

1.2

~
c3

J:
0

1.0

Y

/

0.8

~

1.0

!1

]

0.8

w

N

:::l

5.0

~

0.8
4.0

5.5

-55

6.0

1.8

4.5

--

fil

i

TA _25°C

6.0

r--

1.2

1.0

1--------1f-----,;Ic----I

I----~I'-------I

-55

i

2.0
1.6

ISB

1.0
0.5

zw

100

:::l

80

a:
a:

1.0

2.0

-

3.0

!

"

60

~

40

0

20

I!::::l

o

4.0

6.0

/

L

10'

1/

1.0

Vee -5.0V
TA =25°C

2.0

3.0

4.0

OUTPUT VOLTAGE (VI

NORMALIZED Icc
vs. ACCESS TIME
1.4

/

20.0

1.2

"\.

0
w

N

:;

ia:

/

/

V
a

1.3

]

/

10.0

0.0

SUPPLY VOLTAGE (VI

/

0.0

,.-

$
« 15.0
:;
5.0

4.0

3.0

...,. ~
/

z

1ii

TYPICAL ACCESS TIME CHANGE
VS. OUTPUT LOADING

~

/

V

0.0
0.0

120

125

26

25.0
C .,....,.,.,PULL-UP
RESISTOR TO Vee
0

:&

a:

<

!,..

AMBI ENT TEMPERATUR E (OCI

J25
lK n CS

"'"

140

0.8 .....r::....------1f---------I

2.6

2.0

1.0

OUTPUT SUNK CURRENT
VS. OUTPUT VOLTAGE

NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

30.0

0
w

a

OUTPUT VOLTAGE (VI

~

B.O

Vee =5.0V
TA = 25°C

20

U

TYPICAL POWER-ON CURRENT
VB. SUPPLY VOLTAGE (7Cl48)

N

"-

0.0

0.6 L-_ _ _.....I._ _ _ _ _..J

5.6

TA

'\.

40

125.0

N

::i

3.0

«

25.0

~

AMBIENT TEMPERATURE (OCI

SUPPLY VOLTAGE (VI

:;

~

0

$

0.9

j

:::l

0.0
4.5

.'"

1.2

1.0

..

ISB

1.4

0
w

z

iii,..

Vee = 6.0 V
V,N = 5.0 V

lsa

1.3

0

80

0.2

NORMALIZED ACCESS TIME
vs SUPPLY VOLTAGE

ia:

80

:& 0.4
a:

1.4

1.1

z

a:
a:
:::l
u
w
u
a:

0.6

SUPPLY VOLTAGE (VI

N

w

z

0.0
4.0

::i

~

0

0.2

..

100

!,..

«

V,N = 6 V
TA = 25°C

z

:J

<

::i

a: 0.4
0

VB.

Icc

0

V

w
N
::i 0.6
«
:&

OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE

NORMALIZED SUPPLY CURRENT
vs AMBIENT TEMPERATURE

VS.

1.4

0

z

TA = 25°C

1.1

.............
1.0

r-

Vee =4.6V
0.9
0.8

200

400

600

CAPACITANCE (pFI

800

1000

10

20

30

40

50

80

tAA (nlf

0001-10

2-87

Ordering Information
Speed
(ns)
25

35

45

Address Designators
Type

Operating
Range

Address
Name

Address
Function

Pin
Number

CY7C148-25PC
CY7C149-25PC

P3

Commercial

AD

Yo

5

Al

YI

6

CY7C148-25DC
CY7C149-25DC

D4

A2

Y2

7

CY7C148-25LC
CY7C149-25LC

L50

A3

Y3

4

A4

Xc

3

As

X3

2

A6

X2

1

A7

Xs

17

As

X4

16

A9

XI

15

Ordering Code

Package

CY7C148-35PC
CY7C149-35PC

P3

CY7C148-35DC
CY7C149-35DC

D4

CY7C148-35LC
CY7C149-35LC

L50

CY7CI48-35DMB
CY7CI49-35DMB

D4

CY7CI48-35LMB
CY7C149-35LMB

L50

CY7CI48-45PC
CY7CI49-45PC

P3

CY7C148-45DC
CY7C149-45DC

D4

CY7CI48-45LC
CY7CI49-45LC

L50

CY7CI48-45DMB
CY7CI49-45DMB

D4

CY7CI48-45LMB
CY7CI49-4SLMB

L50

Commercial

Military

BitMap

Commercial

Military

0001-11

2-88

fin
.

CY7C148
CY7C149

~~========================================================~

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

IOH

1,2,3

IOL

1,2,3

VIH

1,2,3

VlLMax.

1,2,3

IlX

1,2,3

IOZ

1,2,3

ICC

1,2,3

ISB[I]

1,2,3

II

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9, lO, 11

tAA

7,8,9,lO,11

tACSI[I]

7,8,9,10,11

tACS2[1l

7,8,9,lO,11

tACS[2]

7,8,9,lO,11

toH

7,8,9,lO,11

WRITE CYCLE
twc

7,8,9, lO, 11

twp

7,8,9, lO, 11

tWR

7,8,9,lO,11

tDW

7,8,9, lO, 11

tDH

7,8,9,10,11

tAS

7,8,9, lO, 11

tAW

7,8,9,lO,11

Notes:
I. 7CI48 only.
2. 7CI49 only.

Document #: 38-00031-B

2-89

CY7C150

CYPRESS
SEMICONDUCTOR

1024

Features

Functional Description

• Memory reset function

The CY7C150 is a high performance
CMOS static RAM designed for use in
cache memory, high speed graphics,
and data aquisition applications. Organized as 1024 words x 4 bits, the entire
memory can be reset to zero in two
memory cycles.

• 1024 x 4 static RAM for control
store in high speed computers
• CMOS for optimum
speed/power
• High speed
- 12 ns (commercial)
- 15 ns (military)
• Low power
- 495 mW (commercial)
- 550 mW (military)
• Separate inputs and outputs
• 5 volt power supply ± 10%
tolerance both commercial and
military
• Capable of withstanding greater
than 2001V static discharge
• TIL compatible inputs and
outputs

X

4 Static R/W RAM
eration ofthe memory. When the chip
select (CS) and write enable (WE) inputs are LOW, the information on the
four data inputs Do to D3 is written
into the addressed memory location
and the output circuitry is preconditioned so that the write data is present
at the outputs when the write cycle is
completed.

Separate I/O paths eliminate the need
to multiplex data in and data out, providing for simpler board layout and
faster system performance. Outputs are
tri-stated during write, reset, deselect,
or when output enable (OE) is held
HIGH, allowing for easy memory expansion.

Read~ is performed with the chip select (CS) input LOW, and the write enable (WE) input HIGH, and the output
enable input (00) LOW. The information stored in the addressed word is
read out on the four non-inverting outputs 00 to 03.

Reset is initiated by selecting the device
(CS = LOW) and pulsing the reset
(RS) input LOW. Within two memory
cycles all bits are internally cleared to
zero. Since chip select must be LOW
for the device to be reset, a global reset
signal can be employed, with only selected devices being cleared at any given time.

The outputs of the memory go to an
active high impedance state whenever
chip select (CS) is HIGH, Reset (RS) is
LOW, output enable (OE) is HIGH, or
during the writing operation when
Write Enable (WE) is LOW.

A die coat is used to ensure alpha immunity.

An active LOW write enable input
(WE) controls the writing/reading op-

Logic Block Diagram

Pin Configurations
RS

<.. .R~

cs

DE

As
A6

WE

A7
A8

NC

00
Ao
Al
A2
A3
A4
A5

Ag
01

DO
01

O2

00

~~

3 2 11 12827
l!..I
26
4
5
25
6
24
7
23
8
22
9
21
10
20
11
194
12
184
1314151617

03

-00

N

A3
A4

A2

AO

A5

Al

RS
Cs

A6

Ao

A7

RS

NC

As

WE

As

WE

DO

DE

01

03

OE
03

O2

."

0%%00

"

vee

Al

cs

°0

O2

°1
GNO

03

0028-13

°2
0028-2

0028-1

Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)

Commercial
Military
Commercial
Military

7C150-12
12
90

2-90

7C150-15
15
15
90
100

7C150-25
25
25
90
100

7C150-35
35
35
90
100

~
CY7C150
~~~UaoR================================================================
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... >2OO1V
Storage Temperature ............... -65°C to + 150"C
(Per MIL-STD-883 Method 3015)
Ambient Temperature with
Power Applied .................... - SSoC to + 125°C
Latch-up Current .......................... > 200 rnA
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... - 0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V
DClnputVoltage ................... -3.0Vto +7.0V

Range
Commercial
Military [3]

Output Current into Outputs (Low) ............. 20 rnA

Ambient
Temperature

Vee

O"Cto +70"C

SV ±10%

- 55°C to + 12SoC

SV ±lO%

Electrical Characteristics Over Operating Range[4)
Description

Parameters

7CI50-12,15,25,35

Test Conditions

Min.

VOH

Output HIGH Voltage

Vee = Min.,IOH = -4.0rnA

VOL

Output LOW Voltage

Vee = Min., IOL = 12.0 rnA

VIR

Input High Voltage

2.0

Units

Max.

V

2.4
0.4

V

Input Low Voltage

Vee
0.8

V

-3.0

IIX

Input Load Current

GND

Vee

-lO

+lO

/LA

loz

Output Leakage
Current

GND ~ Va ~ Vee
Output Disabled

-50

+50

/LA

los

Output Short[l]

Vee = Max., VOUT = GND

-300

rnA

VIL

VI

~

Vee = Max.
lOUT = ornA

Vee Operating
Supply Current

Icc

~

I
I

Commercial

90

Military'

100

V

rnA

*-15, -25 and -35 only

Capacitance [2]
Test Conditions

Max.

Units

CIN

Input Capacitance

TA = 25°C, f = 1 MHz, Vee = 5.0V

5

pF

CoUT

Output Capacitance

TA = 25°C, f = 1 MHz, Vee = 5.0V

7

pF

Description

Parameters

Notes:
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

1. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

AC Test Loads and Waveforms
R1329 n

R1329n

5Vo---------~~~

5Vo---------~~,

OUTPUTo-----_------~

OUTPUT

3.0V----~~---~

0-----_------,.

GND-....;=~

R2
202n

'NCLUD'NGI 30 pF
JIG AND

5 pF
'NCLUD'Nl
JIG AND

SCOPE

SCOPE

R2
202n

,;;3118
0028-5

Figure 2. All Input Pulses

-:'
0028-3

Figure la

,;;3118

Figure lb

Equivalent To:

THEVENIN EQUIVALENT
125n
OUTPUT O--_.Jo'\NI..,---_01.90 V
0028-4

2-91

fI

Switching Characteristics Over Operating Range[4, 51
Description

Parameters

7C150-12
Min.

Max.

7C150-15
Min.

Max.

7C150-25
Min.

Max.

7C150-35
Min.

Max.

Units

READ CYCLE
tRc

Read Cycle Time

tAA

Address to Data Valid

toHA

Output Hold from Address Change

tACS

CS LOW to Data Valid

tLZCS

CS LOW to Low Z[71

tHZCS

CS HIGH to High Z[6, 71

8

tDOE

OE LOW to Data Valid
OE LOW to Low Z(7)

8
0

OE HIGH to High Z[6, 71

0

twc

Write Cycle Time

12

15

25

35

ns

tscs

CS LOW to Write End

8

11

15

20

ns

tAW

Address Set-up to Write End

10

13

20

30

ns

tHA

Address Hold from Write End

2

2

5

5

ns

tSA

Address Set-up to Write Start

2

2

5

5

ns

tpWE

WE Pulse Width

8

11

15

20

ns

tSD

Data Set-up to Write End

8

11

15

20

ns

tLZOE

tHZoE
WRITE CYCLE[SI

12

15
12

2

25
15

2
10

0

2
12

0
0

11

15
0

0

0
20

0
9

0

0

0

ns
ns

25

ns

20

ns

0
20

ns
ns

20

15

10

ns
35

2

0

0
8

35
25

ns
25

ns

tHD

Data Hold from Write End

2

2

5

5

ns

tLZWE

WE HIGH to Low Z[71

0

0

0

0

ns

WE LOW to High Z[6, 71

0

tRRC

Reset Cycle Time

24

30

50

70

ns

tSAR

Address Valid to Beginning of Reset

0

0

0

0

ns

tSWER

Write Enable HIGH to Beginning of Reset

0

0

0

0

ns

tSCSR

Chip Select LOW to Beginning of Reset

0

0

0

0

ns

tPRs

Reset Pulse Width

12

15

20

30

ns

tHCSR

Chip Select Hold after End of Reset

0

0

0

0

ns

tHWER

Write Enable Hold after End of Reset

12

15

30

40

ns

tHAR

Address Hold after End of Reset

12

15

30

40

ns

tLZRS

Reset HIGH to Output in Low Z[71

0

tHZRS

Reset LOW to Output in High Z[6, 71

0

tHZWE
RESET CYCLE

8

0

12

0
8

0

0

20

0
12

0

0

25

0
20

0

ns

ns
25

ns

Notes:

Test conditions assume signal transition times of 5 ns or less, timing
reference levels of l.5V, input pulse levels of 0 to 3.0V and output
loading of the specified Ior/IoH and 30 pF load capacitance.
6. tHZCS. tHZOEo tHZR and tHzWE are tested with CL = 5 pF as in
Figure lb. Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZ is less than tLZ
for any given deVice.

8. The internal write time of the memory is defined by the overlap of
CS LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
9. Wl'l is HIGH for read cycle.
10. Device is continuously selected, CS and OIl = VIL.
11. Address valid prior to or coincident with cs transition LOW.

5.

2-92

Switching Waveforms
Read Cycle No.1 (Notes 9, 10)

---*_

~

~-------------------------t"C--------------------------~J.

ADDRESS

DATA OUT

~

~_H_A

~_A_~
.'

_____ ____
_ _____
PREVIOUS DATA VALID

DATA VALID

-----------------------------------

0028-6

Read Cycle No.2 (Notes 9, 11)

tRC

J

,If.-

 (Note 8)
twe

ADDRESS

~

-

~
!ses

\\ ~\,

~/II II 'ILl/
tAW

/ / / //1

'HAtrwE

'SA

\\\'~
DATA IN

'SD

i

DATA-IN VALID

IH~
'I

'I

-'HZWE

~

!--'LZWE

~______________

HIGH IMPEDANCE
DATAmrr __________________D_A_T_A_U_ND_E_F_IN_E_D________________J/~----~~~~~~-----(\~

0028-9

2-93

fII

Switching Waveforms (Continued)
Write Cycle No.2 (CS Controlled) (Note 8)
twe

~f

ADDRESS

---.J~
lacs

'SA

-',
'AW

'HA-

tpwE

'1//// / / / / / / / / /1

\\\\\ \ \ \ \ \ \ \ \\s.
tao

'l

DATA IN

DATA 110

'HO

DATA-IN VALID

I---'HZWE:::::j
HIGH IMPEDANCE
DATA UNDEFINED
'\:)0----------...;;....;....;.;.....;.;.;;...------

-----------------,

0028-10

Note: Ifes goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

Reset Cycle

ADDRESS

-------,.~'__~------------->K,-----tHAR

J.
01-04~~~~~~~~~~~~~~--~~~~-~~~--~~~~~~~~-----

(DATA OUTPUT)

HIGH
IMPEDANCE

OUTPUT VALID ZERO

0028-11

Note: Reset cycle is defined by the overlap ofH and CS for the minimum reset pulse width.

2-94

~
CY7C150
~~~UaoR================================================================
Typical DC and AC Characteristics
NORMAUZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4

1.0
ICC/,

~ 1.0

...
Q

1.2

.,,/

1.2

1i

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VS.

0.8

./"

N

:::; 0.6
«

~

]

...N
:I

a:

a: 0.4
0

w
"
"a:

:1

1.1

............

:I

z

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

1.0

"'-

0.9
0.8
4.0

4.5

--

«

:IE

a:

1.0

0

-

z
0.8

~

/

125

Z

100

a:

::l

"z
'"
in

....

Vee' 5.0 V

6.0

25

0

I

TYPICAL POWER·ON CURRENT
vs.SUPPLYVOLTAGE

~r---~---r--~----~--~

j

!

2.0

20~--+---~--~~--+---~

Q

:::; 1.5

..i

~

«

:I

1.0
0.5

-

/

V

0.0
0.0

1.0

2.0

3.0

~

4.0

SUPPLY VOLTAGE (VI

5.0

3.0

4.0

5.0

Vee = 5.0 V
TA ·26·C
V,N = 0.6 V

11

1.0

5l

$

N

2.0

1.1

2.5

...

j5"C

NORMAUZED Icc
vs. CYCLE TIME

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING

3.0

Vee = 5.0 V
TA =

OUTPUT VOLTAGE (VI

AMBIENT TEMPERATURE ('CI

SUPPLY VOLTAGE (VI

/
1.0

125

25

-55

j

50

0.6

5.5

/

75

::l

::l

..-

V

a:

/

:::;

TA = 25'C

5.0

/

1.2

-______-1

ARRAY 0

ARRAY 1

8096 x 16

8096 x 16

DATA-OUT 0-7 LATCH

..

------------------+-~

0153-1

2-98

~
PRELIMINARY CY7C157
~~~U~================================================================
Selection Guide
Maximum Clock to
Output (ns)

Commercial

Maximum Output Enable to
Output Time (ns)

Commercial

7C157·20

7C157·24

7C157·33

20

24

33

24

33

8

10

15

10

15

250

250

250

300

300

Military
Military
Commercial

Maximum Current (rnA)

Military

II

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -6SoC to + ISO"C

Static Discharge Voltage ..................... >2001V
(Per MIL·STD-883 Method 301S)

Ambient Temperature with
Power Applied .................... - SsoC to + l2SoC

Latch-up Current .......................... > 200 rnA

Supply Voltage to Ground Potential .... -0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to + 7.0V

Ambient
Temperature

Vee

OOCto +700C

5V ± 10%

- 55°C to + 125°C

5V ±10%

Range

DC Input Voltage ................... - 3.0V to + 7.0V
Commercial

Output Current into Outputs (LOW) ............ SO rnA

Military

Electrical Characteristics Over Operating Range
Parameters

Description

7C157·20

Test Conditions

7C157·24

7C157·33

Units

Min. Max. Min. Max. Min. Max.
VOH

Output HIGH Voltage

Vee

=

Min,loH

=

-4.0mA

VOL

Output LOW Voltage

Vee

=

Min, IOL

=

8.0 rnA

VIH

Input HIGH Voltage

2.2

VIL

Input LOW Voltage

-3.0
GND < VI < Vee

IIX
loz

Output Leakage Current GND < Vo < Vee, Output Disabled

los

Output Short Circuit
Currentl11

Vee

lee

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

Max, VOUT

=

2.4

2.4
0.4

Input Load Current

=

2.4

0.4
2.2

Vee
0.8

V

-3.0

+10

-10

+10

-10

+10

/LA

+50

-50

+50

-50

+50

/LA

-350

-350

rnA

250

250

300

300

-3.0

-10
-50

-350

ICommercial
IMilitary

V

Vee
0.8

Vee
0.8

GND

V
0.4

250

2.2

V

rnA

Capacitance [2]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions

Max.

TA = 25°C, f = 1 MHz
Vee = 5.ov[31

5

Units
pF

8

Notes:
I. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.

2. Tested initially and after any design or process changes that may
affect these parameters.
3. TA is the "instant on" case temperature.

2-99

~
PRELIMINARY CY7C157
~~~~========================================================
AC Test Loads and Waveforms
5v

OUTPUT

0--_---"
I
1.. ,F

_

INCLUDING
JIGANO _

- SCOPE

svo----..,........,

-

SpF

A2

TINCLUDING
,J;;IGANO _

- SCOPE

0153-3

Figure la
Equivalent to:

3.0V

OUTPUT o--~---"i
A2
2&5tl

d-

All Input Pulses

Aua1n

0-----'\,.,.,--.

GNO

2&In

I""

s3ne

~

0153-5

-

0153-4

Figure 2

Figure lb

THEVENIN EQUIVALENT
167n
OUTPUT

0 - -.........."'
..",
..---01.73V

0153-6

Switching Characteristics Over Operating Range [4, S]
Parameters

7C157-20[6]

Description

Min.

Max.

7C157.24[6]

Min.

Max.

7C157-33

Min.

Units

Max.

READ CYCLE[7, 8]

25
20

30
24

tcHCH

Clock Cycle Time

tCHQV

Clock HIGH to Output Valid

tcHQX

Output Data Hold

toLQV

OE LOW to Output Valid

8

10

toHQZ

OR HIGH to Output Tristate

8

10

toHCH

OE HIGH to Next Clock HIGH

7

7

7

tAVCH

Address Setup

2

2

3

ns

tcHAX

Address Hold

6

6

6

ns

5

5

40

ns

33

ns

5

ns

15
15

ns
ns
ns

WRITE CYCLE!9]

10

15

tOHQZ

OE HIGH to Output Trlstate[!O)

tOHCH

OE HIGH to Next Clock HIGH

7

7

7

ns

tDVCL

Data in Setup to Clock

6

6

7

ns

tcLDX

Data in Hold from Clock

ns

WEX LOW to Clock LOW[t2, 13]

6

ns

tCLWH

Clock LOW to WEx HIGH[12, 13]
Address Setup

3
3

ns

tAvCH

2
4
3
2

2

tWLcL

2
4
3
2
6

6

6

ns

Address Hold
tCHAX
Notes:
4. See the last page of this specification for Group A subgroup testing

8

ns

ns

10. toHQZ is specified with CL = S pF as in Figure lb. Transition is
measured ± 500 mV from steady state voltage.
I!. Self Tinted Write is triggered on falling edge of either W~ or WEI.
12. X = 0 or 1 for low byte and high byte, respectively.
13. Self Timed Write is triggered on falling edge of registered WEo or
WEI signals.

information.

S. Test conditions assume signal transition times of 3 ns or less, timing
reference levels of I.SV, input pulse levels of 0 to 3.0V and output
loading of the specified Ior/IOH and 100 pF load capacitance.
6. Surface mount package only.
7. WE is HIOH for read cycle.
8. OIl is selected (LOW).
9. OE must be high for data-in to propagate to latch.

2·100

~

PRELIMINARY CY7C157
~~~~R==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Switching Waveforms
Read Cycle
CLOCK

ADDRESS

•

------'1
ADD(N)

ADD(N+ 1)
........,~--~~~,~~~~~

~~~~-+--~--~

0153-7

Write Cycle
CLOCK

-----'I

D(N+ 1)

0153-8

2-101

~~===========================PR==E=Ll=M=I=N.=~=R=Y====C=Y=7C==15=7
Pin Timing Cross Reference

Pin Configuration

Timing
Reference

Pin Name

Description

Clock

C

Clock Inputs

Ao-A13

A

Address Inputs

1/00-1/015 (Input)

D

Data Inputs

1/00-1/015 (Output)

Q

Data Outputs

WEo. WEI. WEx

W

Write Enable

OE

G

Output Enable

S

...

0

-

'"

.c~ "'<~.£> ~~~.c.c.c

Ao
Vsso
1/°0
1/°1
1/°2
1/°3

Vsso
1/°4
1/°5
1/°6
1/°7

Vsso
Vsso

7 6 5 4 3 2 t!J525150494847
8
46
9
45
44
10
11
43
12
42
13
41
40
14
15
39
16
38
17
37
18
36
19
35
20
34
21222324252627282930313233

~ ,{ 8 81~

-?-?

iii iii iii ~

8

A13

VSSO
1/°15
1/°14
1/0 13
1/°12

Vsso
1/°11
1/°10

I/Og
I/os

VSSO
VSSO

8ni ~

»>o-?-?

0153-2

PLCC
Top View

Truth Table
Inputs
OE

WEo (.! CLOCK)

WEl (.! CLOCK)

X

X

H

H

HighZ

L

H

H

1/0 0-1/015

H

L

H

1/00-1/07

H

H

L

I/Os-I/015

H

L

L

1/0 0-1/ 0 15

Ordering Information
Speed
20

24

33

HighZ

X
H

Noles:
14. Data In latch is transparent when clock tHIGH.
15. Data In latch is closed when clock ,j. LOW.

(ns)

Outputs

Ordering Code

Package
Type

Operating
Range
Commercial

CY7C1 57-20LC

L69

CY7C1 57-20JC

J69

CY7C157-24LC

L69

CY7C157-24JC

J69

CY7ClS7-24LMB

L69

Military
Commercial

CY7CIS7-33LC

L69

CY7C157-33JC

J69

CY7CIS7-33LMB

L69

Military

2-102

~
PRELIMINARY
CY7C157
~~~aoR==========================================================~
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

llX

1,2,3

loz

1,2,3

loS

1,2,3

IcC

1,2,3

II

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tCHCH

7,8,9,10,11

tCHQV

7,8,9,10,11

tGHQZ

7,8,9,10,11

tCHQX

7,8,9,10,11

tGHQV

7,8,9,10,11

WRITE CYCLE
tcHCH

7,8,9,10,11

tDVCL

7,8,9,10,11

tAVCH

7,8,9,10,11

tCHAX

7,8,9,10,11

tCLDX

7,8,9,10,11

tDVWL

7,8,9,10,11

tWLDX

7,8,9,10,11

Document #: 38-00098

2-103

CY7C161
CY7C162

ADVANCED INFORMATION

16,384
Features

Functional Description

• Automatic power-down when
deselected
• Transparent Write (7CI61)
• CMOS for optimum speed!
power
• High speed
-10 ns tAA
• Low active power
- 525 mW at 40 MHz
• Low standby power
-150mW
• TTL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

The CY7Cl61 and CY7C162 are high
performance CMOS static RAMs organized as 16,384 x 4 bits with separate
I/O. These RAMs are developed by
Aspen Semiconductor Corporation, a
subsidiary of Cypress Semiconductor.
Easy memory expansion iSEovided by
active LOW chip enables (CEI, CB2)
and three-state drivers. They have an
automatic power-down feature, reducing the power consumption by 75%
when deselected.

4 Static RAM
Separate I/O

(10 through 13) is written into the memory location specified on the address
pins (Ao through A13)·
Reading the device is accomplished by
taking the chip enables (eEl. CB2)
LOW, while write enable (WE) remains HIGH. Under these conditions
the contents of the memory location
specified on the address pins will appear on the four data output pins.
The output pins stay in h~impedance
state when write enable (WE) is LOW
(7C162 only), or one of the chip enables (eEl. CE2) are HIGH.

Writing to the device is accomplished
when the chip enable (eEl, CB2) and
write enable (WE) inputs are both
LOW. Data on the four input pins

Logic Block Diagram

X

Pin Configurations
I.

As

I-+--_Cl-___ I.

..
AI

A,

I+-I--C>---o,

"A.

1+-1---1 >---02

..,

A,

1
2

A7

3

As
As

r'H--"'c>---o.

Ao

A,

Vee

2'
26
25

A.
A,

~.;:~~;

A2
A,

[!]2827
26 A12
25 A11
24 A,.
23
As
As
22 13
A,
A.
2' '2
20 0,
I. '0
11
19 °2
I. 0,
CE:," 12
1314151617

.10

6

24
23

A.11

7

22

A.
I,

2'
2.

'2
03

A'2

A"
10

L....J-I"'+-...c>---o.

2.

10

'9

.,

11

I.

°2
0,

CE,

DE

12
13

17
16

GND

'4

15

o.
WE
CE2

A,
A.
A.

4
5

3

i

I~ ~ It1NI~ cf
0152-3

0152-2

0152-1

Selection Guide
7C161-10
7C162-10

7C161-12
7C162-12

7C161-15
7C162-15

10

12
120
150
30
50

15
115

Maximum Access Time (ns)
Maximum 0serating
Current(mA
Maximum Standby
Current (rnA)

125

Commercial
Military
Commercial
Military

30

2-104

135

30
50

&n
.

ADVANCED INFORMATION

CY7C161
CY7C162

~UcroR================================================================~

Maximum Ratings
(Above which the useful life may be impaired. Exposure to absolute maximum rated conditions for extended periods may
affect device reliability. For user guidelines, not tested.)
Static Discharge Voltage ..................... > 2001 V
(Per MIL-STD-883 Method 3015)
Latch-up Current .......................... > 200 mA

Storage Temperature ............... - 65°C to + 150°C
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V
Input Voltage! 14) .................... - 3.0V to + 7.0V
Output Current into Outputs (Low) ............. 20 mA

Operating Range
Range

Ambient
Temperature

Vee

Commercial
Military!3]

O°C to +700C
- 55°C to + 125°C

5V ±1O%
5V ±IO%

Electrical Characteristics Over Operating Range!4]
Parameters

Description

7C161-10
7C161-12
7C161-15
7C162-10
7C162-12
7C162-15
Units
Min. Max. Min. Max. Min. Max.
2.4
2.4
2.4
V
0.4
0.4
0.4
V
2.2
2.2
V
Vee
Vee 2.2
Vee
-0.5 0.8
-0.5 0.8 -0.5 0.8
V
-10 +10 -10 +10 -10 +10 p.A

Test Conditions
Vee = Min.,loH = -4.0mA
Vee = Min.,IOL = 8.0 rnA

los

Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(14)
Input Load Current
Output Leakage
Current
Output Short Circuit
Current!l]

leel

Automatic CE
Power Down Current

Vee = Max.
lOUT = OmA
f=40MHz

Commercial

Vee = Max.
lOUT = OmA
f = fmax.

Commercial

VOH
VOL
VIR
VIL
IIX
IOZ

Vee Operating
Supply Current

lee2

Automatic CE
Power Down Current

ISB

GND S; VI S; Vee
GND S; Vo S; Vee,
Output Dsbld.

-10

Vee = Max., VOUT = GND

+10

-10

+10

-10

+10

p.A
rnA

-350

-350

-350

105

105

105

130

130

125

120

115

30

150
30
50

135
30
50

rnA
Military

mA

Military
Commercial
Max. Vee, CE ~ VIR
Min. Duty Cycle = 100% Military

rnA

Capacitance [2]
Description
Input Capacitance
Output Capacitance

Parameters
CIN
COUT

Test Conditions
TA = 25°C, f = I MHz, Vee = 5.0V
TA = 25°C, f = I MHz, Vee = 5.0V

Notes:
\. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

Max.l13]
5
7

Units
pF
pF

3. TA is the Hinstant on" case temperature.
4. See the last page of this specification for Group A subgroup testing

infonnation.

AC Test Loads and Waveforms
R1 481Jl.

5V

5V O-----.JV'i/lr---,

OUWUTO--1--------i

I-=

CL
INCLUDING
JIG AND
SCOPE

OUTPUT

~;5Jl.

0--..--------+

I-=

-=

Figure 1a
Equivalent to:

3.0 V----.I.-::::::----i.

R1 481Jl.

o------"IIIV---,

GND
R2
255Jl.

5pF
INCLUDING
JIG AND
SCOPE

Figure 1b

THEVENIN EQUIVALENT
16712

OUTPUT

O---'·"'.·"'A...- - o

1.73V

0152-6

2-105

0152-5
0152-4

Figure 2

~
r
.

(;n
.

CY7C161
CY7C162

ADVANCED INFORMATION

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==

Switching Characteristics Over Operating Range[4, 5, 12]
Parameters

7C161-10
7C162-10

Description

Min.

7C161-12
7C162-12

Max.

Min.

7C161-15
7C162-15

Max.

Min.

Units

Max.

READ CYCLE

10

tRC

Read Cycle Time

tAA

Address to Data Valid

12

taHA

Output Hold from Address Change

tACE

CE LOW to Data Valid

tLZCE

CE LOW to Low Z[7]

tHZCE

CE HIGH to High Z[6, 7]

6

8

8

ns

tDOE

OE LOW to Data Valid

8

10

10

ns

tLZOE

OE LOW to LOW Z

tHZOE

OE HIGH to HIGH Z

tpu

CE LOW to Power Up

tpD

CE HIGH to Power Down

10

15
12

3

2

10

3
12

3

2

0

0

ns

8
0

12

10

ns
ns

2

8

6

ns
ns

15

3

3

2

ns
15

ns
ns

15

ns

WRITE CYCLE[8]
twc

Write Cycle Time

10

12

15

ns

tSCE

CE LOW to Write End

8

10

12

ns

tAW

Address Set-up to Write End

8

10

12

ns

tHA

Address Hold from Write End

0

0

0

ns

tSA

Address Set-up to Write Start

0

0

0

ns

tPWE

WE Pulse Width

8

10

12

ns

tSD

Data Set-up to Write End

8

10

10

ns

tHD

Data Hold from Write End

0

0

0

ns

tLzwE

WE HIGH to Low Z[7] (7CI62)

3

5

5

tHZWE

WE LOW to High Z[6, 7] (7CI62)

5

7

7

ns

tAwE

WE LOW to Data Valid (7CI61)

10

12

15

ns

10

12

15

ns

Data Valid to Output Valid (7CI61)
tADV
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOrJIOH and CL = 30 pF load capacitance
for 15 ns tAA devices and CL = 20 pF load capacitance for 10 ns and
12 ns tAA devices.
6. tHZCE and tHZWE are specified with CL = 5 pF as in Figure lb.
Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZ is less than tLZ
for any given device.

ns

8. The internal write time of the memory is defined by the overlap of
CEIo CEz LOW and WE LOW. Both signals must be LOW to initi-

9.
10.

II.
12.
13.
14.

ate a write and either signal can terminate a write by going HIGH.
The data input setup and hold timing should be referenced to the
rising edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CEIo CEz = VIL.
Address valid prior to or coincident with CEIo CEz transition LOW.
Both CE 1 and CEz are represented by CE in the Switching Characteristics and Waveforms.
For all packages except cerdip (022) which has maximums of CIN
= 10 pF, CoUT = 12 pF.
VIdmin.) = -3.0V for pulse width < 20ns.

Switching Waveforms[12]
Read Cycle No. 1[9,10]

~~~------------------------t"C----------------------~1~.

-_~~~~~~~~~~~~~~~~~~~~_*_~~~~~~~~~~~~~~

tA A
ADDRESS - { ' - - - t o - H - A - -- - _
- -- },
-,-',
DATA OUT

PREVIOUS DATA VALID

~'liJf.

2-106

DATA VALID

0152-7

fin
.

ADVANCED INFORMATION

CY7C161
CY7C162

~~=============================================================

Switching Waveforms[12]

(Continued)

Read Cycle!9, 111
'ftC

j

,Il

....
tACE

L

~

tOOE

~'LZOEI
DATA OUT

II I

HIGH IMPEDANCE

f.--tpu

l

Vcc _ _ _ _ _
SUPPLV
CURRENT
_

HIGH
IMPEDANCE

I

DATA VALID

·1"""""

tLZCE

'HZOE-

f4- tH ZCE-

!---'PD

--1

ICC

5~~ ISB

~

Write Cycle No.1 (WE Controlled)!81

ADDRESS

-\\

twc

.

tSCE

r-IIII 111111111

.\\~
tAW

t HA -

tSA

- tpWE -

~\

.1 tHO

tso

X

DATA-IN VALID

DATA IN

I--tHZW~
DATA OUT
(7C162)

I---tLZWE
HIGH IMPEDANCE

DATA UNDEFINED
-tADY

DATA OUT

DATA UNDEFINED

(7CI61)

::I.
J""'"'-_
DATA
_
VALID _ _
0152-9

Write Cycle No.2 (CE Controlled)!81
twc
ADDRESS
tSA

t SCE -

\;
tAW

\\ .\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \.

,/11111111111/

D
.C r - t S
DATA-IN VALID

I

DATA IN

I-- tHZWE..=I
DATA OUT
(7CI62)

t HA --

~tpWE-

DATA UNDEFINED

tHO

I

HIGH IMPEDANCE

- tAWE
DATA OUT -------DA-T-A-U-N-DE-F-IN-EO-------?--D-A-TA-VA-L-ID----

=:JK

(7CI61)

Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7C162 only).

2-107

0152-10

0152-8

1m~~==========================================================~
.

ADVANCED INFORMATION

CY7C161
CY7C162

Truth Tables

CY7C161
CEI CE2 WE OE Output

CY7C162

eEl CE2 WE OE Output

Input

Mode

X

X

HighZ

X

Deselect Power Down

H

X

X

HighZ

X

Deselect Power Down

L

H

L Data Out

L

L

L

Data In Data In

Input

Mode

X

X

HighZ

X

Deselect Power Down

H

X

H

X

X

HighZ

X

Deselect Power Down

X

L

H

L Data Out

X

Read

L

L

L

L

X

HighZ Data In

Write

L

L

L

H

H

HighZ

H

X

X
L

X

Deselect

X

Read

L

L

L

H

HighZ Data In

L

L

H

H

HighZ

X

Write
Write
Deselect

Ordering Information
Speed
(ns)
10
12

15

Ordering Code
CY7C161-10VC
CY7C161-IOLC
CY7C161-12PC
CY7C161-12VC
CY7C161-12DC
CY7C161-12LC
CY7C161-12DMB
CY7C161-12LMB
CY7C161-15PC
CY7C161-15VC
CY7C161-15DC
CY7C161-15LC
CY7C161-15DMB
CY7CI61-15LMB

Paekage
Type
V21
L54
P21
V21
D22
L54
D22
L54
P21
V21
D22
L54
D22
L54

Operating
Range
Commercial

Speed
(ns)

Commercial

12

10

Military
Commercial

15

Military

2-108

Ordering Code
CY7C1 62-IOVC
CY7C162-IOLC
CY7C162-12PC
CY7C162-12VC
CY7C162-12DC
CY7C162-12LC
CY7C162-12DMB
CY7C162-12LMB
CY7C162-15PC
CY7C162-15VC
CY7C162-15DC
CY7C162-15LC
CY7CI62-15DMB
CY7C162-15LMB

Paekage
Type
V21
L54
P21
V21
D22
L54
D22
L54
P21
V21
D22
L54
D22
L54

Operating
Range
Commercial
Commercial

Military
Commercial

Military

(in
.

ADVANCED INFORMATION

CY7C161
CY7C162

~~R==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

Ioz

1,2,3

IcC

1,2,3

ISB

1,2,3

fI

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tAA

1,8,9,10,11

taHA

1,8,9,10,11

tACE

1,8,9,10,11

tOOE

1,8,9,10,11

WRITE CYCLE
tSCE

1,8,9,10,11

tAW

1,8,9,10,11

tHA

1,8,9,10,11

tSA

1,8,9,10,11

tpWE

1,8,9,10,11

tso

1,8,9,10,11

tHO

1,8,9,10,11

tAWE[I]

1,8,9,10,11

tAOV[I]

1,8,9,10,11

Note:
1. 7Cl61 only.

Document #: 38-A-OOOI4

2-109

CY7C161
CY7C162

CYPRESS
SEMICONDUCTOR

16,384

X

4 Static R/W RAM
Separate I/O

Features
• Automatic power·down when
deselected
• Transparent Write (7C161)
• CMOS for optimum speed!
power
• High speed
- 20 us tAA

• Low active power
- 275 mW
• Low standby power
-110 mW
• TIL compatible inputs and

outputs

• Capable of withstanding greater
than 2001V electrostatic
discharge

LOW. Data on the four input pins (10
through h) is written into the memory
location specified on the address pins
(Ao through A13)·
Reading the device is accomplished by
taking the chip enables (CEl, CE2)
LOW, while write enable (WE) reo
mains HIGH. Under these conditions
the contents of the memory location
specified on the address pins will appear on the four data output pins.

Functional Description
The CY7C161 and CY7C162 are high
performance CMOS static RAMs organized as 16,384 x 4 bits with separate
I/O. Easy memory expansion is provided by active LOW chip enables
(CE\. CE2) and three-state drivers.
They have an automatic power-down
feature, reducing the power consump·
tion by 60% when deselected.

The output pins stay in high impedance
state when write enable (WE) is LOW
(7C162 only), or one of the chip enables (CEl, CE2) are HIGH.

Writing to the device is acco~lished
when the chip enable (CEl, CE2) and
write enable (WE) inputs are both

Logic Block Diagram

A die coat is used to insure alpha immunity.

Pin Configurations

r---------------~~---~

'2
I.

Ao

0,
°2

A7

0.

Vee

27
26

A.
A3

25
2.
23

A.
A,

A"
A,.
A,.

A.

A.
A.

28

A.
A7
A8
A.
A,o

°0

A,
A2
A.

A.

~
I,

CE,
OE
OND

~1

3

•
5

22

Ao
I.

8

2'
20

'2
°3

'0

19
18

•

"'2
13
14

'7
16
'5

CE 2

°2
0,
00

~~.p~:;

-.
A3

As

A.
A7

As
10
I,

CE,

Wi'

3

i

1!.l2827
26
25
2.
7
23
8
22
9
2'
10
20
11
'9
12
18
1314151617

•

A..

A"
A,o

As
I.
'2
°3
°2
0,

I~ ~~1~8

CE2

0062-3

0062-2

WE
OE

0062-1

Selection Guide
Maximum Access Time (ns)
Maximum o),rating
Current(mA
Maximum Standby
Current (mA)

Commercial
Military
Commercial
Military

7C161·20
7C162·20
20
80
40/20

2·110

7C161·25
7C162·25
25
70
80
20/20
40/20

7C161·35
7C162·35
35
70
70
20/20
20/20

7C161-45
7C162-45
45
50
70
20/20
20/20

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... - 6SoC to + ISO"C
Ambient Temperature with
Power Applied .................... - SsoC to + 12SoC
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ...................... -O.SVto +7.0V
DC Input Voltage ................... -3.0Vto +7.0V
Output Current into Outputs (Low) ............. 20 rnA

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883 Method 301S)
Latch-up Current .......................... > 200 rnA

Operating Range
Range

Ambient
Temperature

Commercial
Military(3)

O"C to + 70"C
- SSOC to + 12SOC

Vee
SV ±1O%
SV ±10%

Electrical Characteristics Over Operating Range[4]
Description

Parameters

7C161-20
7C162-20

Test Conditions

Min.
VOH

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee

VIH

Input HIGH Voltage

VIL

Input LOW Voltage!4A)

IIX

Input Load Current

loz

= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA

Max.

2.4

7CI61-2S,3S
7CI62-2S, 3S
Min.

Max.

7CI61-4S
7CI62-4S
Min.

2.4
0.4

2.4
0.4

2.2

V

Vee
0.8

V

+10

}J-A

+10

}J-A

-3S0

-3S0

rnA

70

SO

Vee
0.8

-3.0

Vee
0.8

GND,,; VI:S: Vee

-10

+10

-10

+10

2.2
-3.0
-10

Output Leakage
Current

GND :s: Vo :s: Vee,
Output Dsbld.

-10

+10

-10

+10

-10

los

Output Short Circuit
Current!I)

Vee

lee

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

-3S0

Cornl.
Mil.

80

~

80

3S

Coml.
Max. Vee, CE:?: VIH
Min. Duty Cycle = 100% Mil.

Automatic CE
Power Down Current

ISBI

Max. Vee,
CE:?: Vee - 0.3V
VIN:?: Vee -0.3Vor
VIN:S: 0.3V

Automatic CE
Power Down Current

40

1*

Coml.

r---

70

20

20

V

rnA

70

40

~

rnA

20

20

3S

ISB2

V
0.4

2.2
-3.0

= Max., VOUT = GND

Units

Max.

20

20

20

20

20

rnA
Mil.

Capacitance [2]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions

Max.

Units

= 2SoC, f = 1 MHz, Vee = S.OV
TA = 2SoC, f = 1 MHz, Vee = S.OV

S

pF

7

pF

TA

Notes:
1. Not more than 1 output should be shorted at one time. Duration of

3. TA is the "instant on" case temperature.

the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

4. See the last page of this specification for Group A subgroup testing
information.
4A. VIL min. = -3.0V for pulse durations less than 30 ns.

AC Test Loads and Waveforms
R1481U

R1481S!

5Vo----..J,jO"'-...,
OUTPUTo--~----t

r

30PF
INCLUDING
"_JIGAND _
-

SCOPE

~n

-

Figure la
Equivalent to:

3.• V----j,~--~

5 v o-----'lf'oII.-,
OUTPUT o--~----t

OND

I':"~~O:~D
6pF

INCLUDING

R2
266S!

"::"

Figure Ib

THEVENIN EQUIVALENT
167U

OUTPUT

0 - -...."'.,...--0 1,73V

0062-5

2-111

0062-6
0062-4

Figure 2

fI

&1
.

CY7C161
CY7C162
~~~~~~~~~~~~~~~~~~~~~~~~~~~~========~

Switching Characteristics Over Operating Range[4, 5, 121
Parameters

I

7C16l·20
7C162·20

Description

Min.

7C16l·25
7C162-25

~.

Min.

Max.

7C16l·35
7C162·35
Min.

Max.

7C16l·45
7C162-45
Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

toHA
tACE

Output Hold from Address Change
~ LOW to Data Valid

tLZCE

~ LOW to Low Z[7]

tHZCE

~ HIGH to High Z[6, 71

tOOE

OIl LOW to Data Valid
OIl LOW to LOW Z

tLZOE
tHZOE
tpu

20

25
20
5

5

0

0
20

ns

15

ns

20

ns

ns
ns

nS

3
12

0
20

45

15
0

20

ns
ns

25

ns

twc

Write Cycle Time

20

20

25

40

ns

tscE

CE LOW to Write End

15

20

25

30

ns

tAW

Address Set-up to Write End

15

20

25

30

ns

tHA

Address Hold from Write End

0

0

0

0

ns

tSA
tpWE

Address Set-up to Write Start

0

0

0

0

ns

WE Pulse Width

15

15

20

20

ns

tSD

Data Set-up to Write End

10

10

15

15

ns

tHD

Data Hold from Write End

0

0

0

0

ns

tLZWE

WE HIGH to Low Z[71 (7CI62)

5

5

5

5

tHzwE

WE LOW to High Z[6, 71 (7CI62)

tAWE

WE LOW to Data Valid (7CI61)

tADV

Data Valid to Output Valid (7CI61)

7

ns

7

10

15

ns

20

25

30

35

ns

20

20

30

35

ns

Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IoIlIoH and 30 pF load capacitance.
6. tHZCE and tHZWE are specified with CL = 5 pF as in Figure lb.
7.

15

10

ns

5
15

3

3
8

CE HIGH to Power Down
tPD
WRITE CYCLE[8]

5
12

10

3

ns
45

5
35

10

8

LOW to Power Up

5

5

5

45
35

25

20

OE HIGH to HIGH Z
~

35
25

8.

Transition is measured ± 500 mV from steady state voltage.
At any given temperature and voltage condition, tHZ is less than tLZ
for any given device.

9.

10.
11.
12.

The internal write time of the memory is defined by the overlap of
CIllo CIl2 LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH.
The data input setup and hold timing should be referenced to the
rising edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CIlIo·CE2 = VIL.
Address valid prior to or coincident with CEIo CE2 transition LOW.
BOth CEI and CE2 are represented by CE in the Switching Characteristics and Waveforms.

Switching Waveforms[12]
Read Cycle No.1 (Notes 9, 10)

AD RES _: j- -.;. :~_:~ to:H_A:":"-;:'-"'_A~ ~ ~=~:'=~~=~~=~_-~~_-~=*_-=--=-====
,

DATA OUT

PREVIOUS DATA VALID

~

DATA VALID

0062-7

2-112

(;n
.

CY7C161
CY7C162

~U~==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===

Switching Waveforms [12] (Continued)
Read Cycle (Notes 9, 11)
tRC

j

t-

~

tACE

C

ktDOE

I---tLZOEi
DATA OUT

HIGH
IMPEDANCE

HIGH IMPEDANCE

1

Vee _ _ _ _ _
SUPPLY
CURRENT

DATA VALID

·1

tLZCE

!--tpu

I---tPO

Write Cycle No.1 (WE Controlled) (Note 8)

Ice

.

twe

\\

----j

5~~ ISB

50%

_

ADDRESS

tHzOE,..-tHZCE-

.

tscE

.\\~

~I

tAW

I II VIIIIIIII
t HA -

tSA

I - - - tpWE -

"\:\ \
tso -

I

DATA IN

otHO

I-tHZW~
DATA OUT

I-tLZWE
HIGH IMPEDANCE

DATA UNDEFINED

(7CI62)

It:

DATA-IN VALID

I--- tAOV(7CI61)
_UNDEFINED
_________
DATA
OUT _ _ _ _ _ _ _ _
DATA

l"'-__________
_
~L
DATA VALID
0062-9

Write Cycle No.2 (CE Controlled) (Note 8)

ADDRESS

-

.

twe

.

tSA

t scE -

.

3ktAW

.~

.I::

(7CI62)

- tHA --

~I I

,\"'-\\\\\ \ \\\ \\\\ \
f---tso

It:

DATA IN
DATA OUT

~tpWE-

tHO

It:

DATA-IN VALID

I- tHzwE-:1

HIGH IMPEDANCE

DATA UNDEFINED

- tAWE

I I I I /1 I IIII

-

)K

DATA OUT -------D-AT-A-U-N-DE-F-,N-ED----------1--D-A-TA-V-A-LI-O----

(7CI61) _ _ _ _ _.....;;;.;;.;.~==;....._ _ _ _ _ _ _....

0062-10

Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7C162 only).

2-113

0062-8

.
&n
.

CY7C161
CY7C162

~~~~~~~~~~~~~~~~~~~~~~~~~==~~~~~~

Typical DC and AC Characteristics
NORM~SUPPLYCURRENT

VB.

1.4

Icy
/'

1.2

11
.:;
2

1.0

.. V
0

0.8

0.8

N

0.6

::;

""

0.4

0.4
Vee -5.0V
V,N =5.0V

5.0

5.5

6.0

""lEa:0

1.0

z

...........

""""-

0.8
4.0

0.0

4.5

""

1.0

./

:Ii
a:
0

-

5.5

/

z

0.8

Vee' 5.0 V

25

2.5

25.0

!

2.0

0

N

~

~
a:

!:;

::; 1.5

1.0

2.0

-V
3.0

5.0

0.0
4.0

SUPPLY VOLTAGE (V,

5.0

4.0

3.0

Ci

120

...Z

..

100

II:

::>
u

80

"inz
...::>
...

60

/'v

/

a:

.

40

0

20

Vee' 5.0 V
TA • 25'C

V

/

0.0

/

/
1.0

2.0

3.0

4.0

NORMALIZED Icc
CYCLE TIME

VB.

1.2S,---"'T'"---'----'
Vee = 5.0 V
TA = 25'C
VIN"O.5V

/

~ 10.0

/

"" '"

OUTPUT VOLTAGE (VI

-

/

20.0

.:( 15.0

0.5

125

TYPICAL ACCESS TIME CHANGE
VB. OUTPUT LOADING
30.0

5.0 V

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

AMBIENT TEMPERATURE ('CI

3.0

2.0

=

VB.

'"

0.6
-55

6.0

TYPICAL POWER·ON CURRENT
VB. SUPPLY VOLTAGE

0.0
0.0

/

::;

1.0

1.0

Vee

TA • 25'C

OUTPUT VOLTAGE (VI

!

N

TA • 25'C

5.0

1.2

.............

140

SUPPLY VOLTAGE (V,

i

o

125.0

25.0

1.4

.
0

--

"

20

NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE

.
:s

0.9

.E

40

1.6

1.2

::;

'g"
...

VB.

U

1.3

1.1

60

AMBIENT TEMPERATURE ('CI

NORMALIZED ACCESS TIME
SUPPLY VOLTAGE

0

80

u

::>
0

-55

VB

N

a:
a:

0.0
4.5

100

z

......::>

1---10.

SUPPLY VOLTAGE (V,

.

.....
..'"
a:

0.2

Isa

Ci
!

u

z

0.0
4.0

.
:s

~

Q

lE
a:
0

0.2

OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE

VB.

120

~

1.0

.!I
~

..

N

i

1.2

./

::; 0.6

""lEa:

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

SUPPLY VOLTAGE

/

/
TA -25'C
vee -4.50V

V

o

200

400

600

CAPACITANCE (pFI

800

1000

O.50'~O---2~O:----~30~--""'4O
CYCLE FREQUENCY (MHzl
0062-12

2·114

5n
.

CY7C161
CY7C162

~U~================================================================

Ordering Information
Speed
(ns)

Ordering Code

Package
Type

Operating
Range

Speed
(ns)

20

CY7C161-20PC
CY7C161-20VC
CY7C161-20DC
CY7C161-20LC

P21
V21
D22
L54

Commercial

20

25

CY7C161-25PC
CY7C161-25VC
CY7C161-25DC
CY7C161-25LC
CY7CI61-25DMB
CY7CI61-25LMB

P21
V2l
D22
L54

Commercial

25

D22
L54
P2l
V2l

Military

35

45

CY7C161-35PC
CY7C161-35VC
CY7C161-35DC
CY7C161-35LC
CY7CI61-35DMB
CY7CI61-35LMB
CY7C161-45PC
CY7C161-45VC
CY7C161-45DC
CY7C161-45LC
CY7C161-45DMB
CY7C161-45LMB

D22
L54
D22
L54
P2l
V2l
D22
L54
D22
L54

Commercial
35

Military
Commercial
45
Military

BitMap

Ordering Code
CY7C162-20PC
CY7C162-20VC
CY7C162-20DC
CY7C162-20LC
CY7C162-25PC
CY7C162-25VC
CY7CI 62-25DC
CY7C162-25LC
CY7CI 62-25DMB
CY7C162-25LMB
CY7C162-25KMB
CY7C162-35PC
CY7C162-35VC
CY7C162-35DC
CY7C162-35LC
CY7CI62-35DMB
CY7C162-35LMB
CY7CI62-35KMB
CY7C162-45PC
CY7C162-45VC
CY7C162-45DC
CY7C162-45LC
CY7CI62-45DMB
CY7CI62-45LMB
CY7CI62-45KMB

Package
Type
P21
V21
D22
L54
P2l
V2l
D22
L54
D22
L54
K74
P2l
V2l
D22
L54
D22
L54
K74
P2l
V2l
D22
L54
D22
L54
K74

Operating
Range
Commercial

Commercial

Military

Commercial

Military

Commercial

Military

Address Designators

0062-13

2-115

Address
Name

Address
Function

Pin
Number

A5

X3

1

A6

X4

2

A7

X5

3

A8

X6

4

A9

X7

5

AlO

YO

6

All

Yl

7

AI2

Y5

g

AI3

Y4

9

AO

Y3

23

AI

Y2

24

A2

XO

25

A3

Xl

26

A4

X2

27

fJI

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

hx

1,2,3

Ioz

1,2,3

los

1,2,3

Icc

1,2,3

ISB!

1,2,3

ISB2

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRc

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACE

7,8,9,10,11

tOOE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

tAWE[1]

7,8,9,10,11

tAOy[1]

7,8,9,10,11

Note:
1. 7C!6! only.

Document #: 38-00029-0

2-116

CY7C164
CY7C166

ADVANCED INFORMATION

CYPRESS
SEMICONDUCTOR

16,384

Features

Functional Description

• Automatic power-down when
deselected
• Output Enable (OE) Feature
(7CI66)
• CMOS for optimum speed!
power
• High speed
-10 ns tAA
• Low active power
- 525 mW at 40 MHz
• Low standby power
-150 mW
• TIL compatible inputs and
outputs
• Capable of withstanding greater
than 2001 V electrostatic
discharge

The CY7C164 and CY7C166 are high
performance CMOS static RAMs organized as 16,384 x 4 bits. These RAMs
are developed by Aspen Semiconductor
Corporation, a subsidiary of Cypress
Semiconductor. Easy memory expansion is provided by an active LOW chip
enable (CE) and three-state drivers.
The CY7C166 has an active low output
enable (OB) feature. Both devices have
an automatic power-down feature, reducing the power consumption by 60%
when deselected.
Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW
(and the output enable (OE) is LOW

Logic Block Diagram

X

4 Static RAM

for the 7C166). Data on the four input/output pins (1/00 through 1/03) is
written into the memory location specified on the address pins (~ through
A13)·
Reading the device is accomplished by
taking chip enable (CE) LOW (and OE
LOW for 7C166), while write enable
(WE) remains HIGH. Under these
conditions the contents of the memory
location specified on the address pins
will appear on the four data I/O pins.
The I/O pins stay in high impedance
state when chip enable (CE) is HIGH,
or write enable (WE) is LOW (or output enable (OE) is HIGH for 7C166).

DIP Pin Configurations

"Ao
Ne

va,
1/°2
15

""
'."
"~

1/00

WE

OND

1/°2

A.

I/O,

6E

1/°3

0150-4

LCC Pin Configurations

I/O,
1/0 0

onU u

8u

z
"73
AS 4
A9 5
AID 6
All 7
"12 8

CE

-...,---~)

AU

(7C166 ONLY)

9

2 1 2221
20A3
19 Az
18 AI
17 Ao
16 1/03
15 1/02

'4

I/O,

10111213

0150-1
0150-5

0150-6

Selection Guide
7CI64-10
7CI66-10

7CI64-12
7CI66-12

7CIM-IS
7C166-IS

10

12
120

115

Maximum Access Time (ns)
Maximum Operating
Current (rnA)

Commercial

Maximum Standby
Current (rnA)

Commercial

125

Military

150
30

Military

2-117

15

30

135
30

50

50

II

&n
.

ADVANCED INFORMATION

CY7C164
CY7Cl66

~~~~~~~~~~~~~~~~~~~~~~~~~==
Maximum Ratings

(Above which the useful life may be impaired. Exposure to absolute maximum rated conditions for extended periods may
affect device reliability. For user guidelines, not tested.)
Static Discharge Voltage ..................... >2oolV
Storage Temperature ............... - 6SOC to + lSO"C
(per MIL-STD-883 Method 301S)
Ambient Temperature with
Latch-up Current. ......................... > 200 mA
Power Applied , ................... - SsoC to + l2SoC
Supply Voltage to Ground Potential .... -O.SV to

+ 7.0V

DC Voltage Applied to Outputs
in High Z State ...................... - O.SV to

+ 7.0V

Input Voltage[l4] .................... - 3.0V to

+ 7.0V

Operating Range

Output Current into Outputs (Low) ............. 20 mA

RaDge

Ambient
Temperature

Commercial
Military[3]

O"C to + 70"C
- SSOC to + 12SoC

Vee
SV ±1O%
SV ±10%

Electrical Characteristics Over Operating Range l4]
Parameters

llescription

7CIM-IO
7C164-12
'CIM-IS
7Cl66-10
7C166-12
7Cl66-1S
Units
Min. Max. Min. Max. Min. Max.

Test Conditions

VOH

Output HIGH Voltage

Vee = Min., IOH = -4.0 mA

VOL
VIH

Output LOW Voltage

Vee = Min., IOL = 8.0 mA

2.4

Input HIGH Voltage
Input LOW Voltageli4]

VIL
IIX

s::
s::

s:: Vee
Vo s:: Vee,

GND

los

Input Load Current
Output Leakage
Current
Output Short Circuit
Currentli]

lee!

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA
f=40MHz

Commercial

Vee = Max.
lOUT = OmA
f = fmax.

Commercial

loz

2.4
0.4

0.4

V
V

2.2
-0.5
-10

Vee
0.8
+10

2.2
-0.5
-10

Vee
0.8
+10

2.2
-0.5
-10

Vee
0.8

V

+10

/LA

-10

+10

-10

+10

-10

+10

/LA
mA

Vee = Max., VOUT = GND

-3S0

-350

-350

105

105

lOS

130

130

125

120

115

30

150
30

135
30

50

SO

Military

Military

Commercial
Max. Vee. CE ~ VIH
Min. Duty Cycle = 100% Military

Automatic CE[2]
Power Down Current

ISB

VI

GND
Output Disabled

Vee Operating
Supply Current

lee2

2.4
0.4

V

mA

mA
mA

Capacitance [5]
Parameters

llescription

Test Conditions
TA = 2SoC. f = 1 MHz.
Vee = S.OV

Input Capacitance
Output Capacitance

CIN
CoUT

Max,!15]

Units

S
7

pF

Notes:
1. Not more than ! output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the CI! input is required to keep the
device deselected during Vee power-up. otherwise ISB will exceed
values given.

3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.
S. Tested initially and after any design or process changes that may
affect these parameters.

AC Test Loads and Waveforms
Rl04811l

Rl 4811l

5V
OUTPUT

OUTPUT

I-=

R2
2551l
CL
INCLUDING
JIG AND
SCOPE

GND

I-=

-=

R2
2551l
0150-8

5PF
INCLUDING
JIG AND
SCOPE

-=

Figure Ib

Figure la
Equivalent to:

3.0V----~~--_i.

5V

THEVENIN EQUIVALENT

.,.,.
187U

OUTPUT 0

01.13V

0150-9

2-118

0150-7

Figure 2

&Ii~~==============================================================~
.

CY7Cl64
CY7C166

ADVANCED INFORMATION

Switching Characteristics Over Operating Range[4, 6]
Parameters

7C164·12
7C166·12

7CI64·10
7CI66·10

Description

Min.

Max.

Min.

Max.

7CI64-1S
7CI66·IS
Min.

Units

Max.

READ CYCLE

10

tRC

Read Cycle Time

tAA

Address to Data Valid

toHA

Output Hold from Address
Change

tACE

CE LOW to Data Valid

tOOE

OE LOW to Data Valid

7C166

tLZOE

OE LOW to LOW Z

7C166

tHZOE

OE HIGH to HIGH Z

7C166

tLZCE

CE LOW to Low Z[8]

tHZCE

CE HIGH to High Z[7, 8]

tpu

CE LOW to Power Up

tpo

CE HIGH to Power Down

12

10

15
12

3

3

2

10

12

8

2

10

2
8

0

0
10

ns

10

ns
ns

3

0
12

ns
ns

8

8

6

15

8

9

ns
ns

3

3

2

ns
15

ns
ns

15

ns

WRITE CYCLE[9]
twc

Write Cycle Time

10

12

15

ns

tSCE

CE LOW to Write End

8

10

12

ns

tAW

Address Set·up to Write End

8

10

12

ns

tHA

Address Hold from Write End

0

0

0

ns

tSA

Address Set·up to Write Start

0

0

0

ns

tpwE

WE Pulse Width

8

10

12

ns

tso

Data Set·up to Write End

8

10

10

ns

tHO

Data Hold from Write End

0

0

0

ns

tLZWE

WE HIGH to Low Z[8]

3

5

5

WE LOW to High Z[7, 8]
0
tHZWE
Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOL/IoH and CL = 30 pF load capacitance
for IS ns tAA devices and CL = 20 pF load capacitance for 10 and
12 ns tAA devices.
7. tHZCE and tHZWE are specified with CL = 5 pF as in Figure lb.
Transition is measured ± 500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device. These parameters are guaranteed and not
100% tested.
9. The internal write time of the memory is defined by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.

2·119

5

0

7

0

ns
7

ns

10. WE is HIGH for read cycle.
II. Oevice is continuously selected, CE = VIL. (7CI66: OE = VIL
also.)
12. Address valid prior to or coincident with cg transition low.
13. 7CI66 only: Data VO will be high impedance ifOE = V/H.
14. Vldmin.) = - 3.0V for pulse width < 20 ns.
IS. For all packages except cerdip (010, 014) which has maximums of
CIN = 10 pF, COUT = 12 pF.

&1
.

ADVANCED INFORMATION

CY7Cl64
CY7C166

~aoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==

Switching Waveforms
Read Cycle No. l.(Notes 10, 11)

~: . - - - * ~-------------------------tRC--------------------------~1.

ADDRESS

DATA OUT

~

~_HA

~_A ~

_ ____________ ____ _ _
PREVIOUS DATA VALID

DATA VALID

-----------------------------------

0150-10

Read Cycle No.2 (Notes 10, 12)
tRe

~t-

-,
tACE

DE

(7Cl66)

L

-'

!----------tDD'
foo--tLZD',
DATA OUT

HIGH

IMPEDANCE

HIGH IMPEDANCE

1

tLZCE

----I" \. \. \. \.

DATA VALID

!+--tpo

!--IPU

Vee _ _ _ _ _
SUPPLY
CURRENT

tHZOE ___

f--tHZCE-

50%

t

50%

_

lCC

IS8

0150-11

Write Cycle No.1 (WE Controlled) (Notes 9, 13)
twe

ADDRESS

-'"'""""

lSOE

\\ ,\\

~ffffl rff
tAW

f f / / f f f.

tHAtPWE

tSA

l\\
tso

I"
DATA IN

¥

IH:j.

DATA-IN VA-LID

f,.--tHZWE:::::j

'\1

I
!+--tLZWE

HIGH 1MPEDANCE

1,., ______

DATAI~ ________________D_A_T_A_UN_D_E_FI_NE_D______________-J/~--~~~~~~--~'_

0150-12

2-120

5n
.

ADVANCED INFORMATION

CY7C164
CY7C166

~aoR================================================================

Switching Waveforms

(Continued)

Write Cycle No.2 (CE Controlled) (Notes 9, 13)

II

~---------------------~c--------------------~

1 - - - - - tSA

-------t--------tSCE------

I--+------------~
DATA-IN VALID

DATA IN

----------......;.------..J
tHZWE---i

DATA I/O

DATA UNDEFINED

HIGH IMPEDANCE

J~-------.......;.;;;;;.;.;;;;;.,;.;;;.;=----0150-13

Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

7C164 Truth Table

7C166 Truth Table

CE

WE

Input/Outputs

Mode

CE

WE

OE

Inputs/Outputs

Mode

H

X

HighZ

Deselect Power Down

H

X

X

HighZ

Deselect Power Down

L

H

Data Out

Read

L

H

L

Data Out

Read

L

L

Data In

Write

L

L

X

Data In

Write

L

H

H

HighZ

Deselect

Ordering Information
Speed
(ns)

Ordering Code

10

CY7CI64-IOVC

12

CY7CI 64-IOLC
CY7C164-12PC
CY7C164-12VC
CY7C164-12DC
CY7C164-12LC
CY7CI64-12DMB

15

Package
Type
Vl3

Speed
(ns)
10

CY7C166-10VC

Package
Type
V13

CY7C166-10LC

L54

Commercial

12

CY7C166-12PC
CY7C166-12VC

Pl3
Vl3

CY7C166-12DC
CY7C166-12LC

014
L54

CY7CI66-12DMB
CY7CI66-12LMB

014
L54

Military

CY7C166-15PC

P13
V13
014

Commercial

L52
P9
Vl3

Operating
Range
Commercial

Operating
Range
Commercial

DIO
L52
DIO
L52

Military

CY7CI64-12LMB
CY7C164-15PC
CY7C164-15VC
CY7CI64-15DC

P9

Commercial

V13
DI0

CY7CI64-15LC
CY7CI64-15DMB

010

CY7CI64-15LMB

L52

15

Ordering Code

CY7C166-15VC
CY7C166-15DC

L52
Military

2-121

CY7C166-15LC

L54

CY7CI66-15DMB
CY7CI66-15LMB

D14
L54

Commercial

Military

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

loz

1,2,3

Icc

1,2,3

ISB

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tAA

7,8,9,10,11

toHA

7,8,9,10,11

tACE

7,8,9,10,11

tOOEU]

7,8,9,10,11

WRITE CYCLE
tSCE

7,8,9,10,11

tAw

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

Note:
1. 7CI66 only.

Document #: 38-A-00015

2-122

CY7C164
CY7C166

CYPRESS
SEMICONDUCTOR

16,384

X

4 Static R/W RAM

Features

Functional Description

• Automatic power-down when
deselected
• Output Enable (00) Feature
(7C166)
• CMOS for optimum speed!
power

The CY7C164 and CY7C166 are high
performance CMOS static RAMs organized as 16,384 x 4 bits. Easy memory
expansion is provided by an active
LOW chip enable (CE) and three-state
drivers. The CY7C166 has an active
low output enable (OE) feature. Both
devices have an automatic power-down
feature, reducing the power consumption by 60% when deselected.

is written into the memory location
specified on the address pins (Ao
through AD).
Reading the device is accomplished by
taking chip enable (CE) LOW (and OE
LOW for 7C166), while write enable
(WE) remains HIGH. Under these
conditions the contents of the memory
location specified on the address pins
will appear on the four data I/O pins.

Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW
(and the output enable (OE) is LOW
for the 7CI66). Data on the four
input/output pins (1/00 through 1/03)

The 110 pins stay in high impedance
state when chip enable (CE) is HIGH,
or write enable (WE) is LOW (or output enable (OE) is HIGH for 7CI66).
A die coat is used to insure alpha immunity.

• High speed
- 20 ns tAA
• Low active power
-440mW
• Low standby power
-110 mW
• TIL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

Logic Block Diagram

DIP Pin Configurations
A.

Vee

A,
A,

A.

Vee
2

...

...
...

At

A,.
A"

A"

A,
A,

A,.

A"
1/0 3

""
"

0056-2

..

1/°2

A.
A,

I/O,

~

.r~~<.

1/°0

"A,A, '
A,. •

.......- - C E

A"
A12
A"

WE

,-.p""--(OE)
(7C166 ONLY)

0056-1

..... ,,

20 2221

2.

'8
17
16
15

6
7
8
9

,.
10111213

Itl31~~

-con~ [:;! ~~

" 3

A,

2 W282~6

A,

" "A,

4

-

0056-3

0056-16

LCC Pin Configurations

At
A,.
A"
A"
A"CE

A.

1/°3

1/°2

1/°1

,
7

2.2.

9

23
22
21

11
12

"

,.

2.

'8
1314151617

II:: 3~1~~

0056-4

NC

A.
A,

.,

"A.
1/03

1/°2
I/O,
0056-5

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)

Commercial

Maximum Standby
Current (rnA)

Commercial

7Cl64-20
7C166-20

7Cl64-25
7C166-25

20
80

Military
40/20

Military

2-123

7Cl64-35
7C166-35

7Cl64-45
7C166-45

25

35

45

70

70

50

80

70

70

20/20

20/20

20/20

40/20

20/20

20/20

•

fin
.

CY7Cl64
CY7C166

~~===================

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static DischaiJe Voltage ..................... > 200 I V
Storage Temperature ............... - 65°C to + 150"C
Ambient Temperature with
(per MIL-ST -883 Method 3015)
Power Applied .................... - 55°C to + 125°C
Latch-up Current .......................... > 200 rnA

Operating Range

Supply Voltage to Ground Potential .... -0.5V to + 7.0V
DC Voltage Applied to Outputs
in HighZ State ...................... -0.5Vto +7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
Output Current into Outputs (Low) ............. 20 mA

Range

Ambient
Temperature

Vee

Commercial
Military(3)

O"C to + 70"C
- 55°C to + 125°C

5V ±10%
5V ±10%

Electrical Characteristics Over Operating Range[4]
Parameters

Deseription

Test Conditions
Vee
Vee

los

Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[SA)
Input Load Current
Output Leakage
Current
Output Short Circuit
Current!I)

Icc

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

VOH
VOL
VIH
VIL
IIX
Ioz

=
=

Min.,loH = -4.0mA
Min.• IOL = 8.0 rnA

GND::;; VI::;; Vee
GND ::;; Vo ::;; Vee.
Output Disabled
Vee

=

Max.• VOUT

7Cl64-20
7Cl66-20
Min. Max.
2.4
0.4
2.2 Vee
-3.0 0.8
-10 +10

7Cl64-25, 35
7Cl66-25, 35
Min. Max.
2.4
0.4
2.2
Vee
-3.0
0.8
-10 +10

7Cl64-45
7Cl66-45 Units
Min. Max.
2.4
V
0.4
V
2.2 Vee
V
-3.0 0.8
V
-10 +10 p.A

-10

-10

-10

-350

GND

=

+10

80

Com!.
Mi!.

t*
35

Automatic m(2)
Power Down Current

ISBI

Com!.
Max. Vee. CE :;:, VIH
Min. Duty Cycle = 100% Mil.

40

~
35

Automatic CE(2)
Power Down Current

ISB2

Max. Vee.
CE:;:, Vee - 0.3V
VIN:;:' Vee -0.3Vor
VIN::;; 0.3V

-350

+10

p.A

-350 rnA

70
80
70
20

70

50

~

20

rnA

20
rnA

20
20

Com!.

+10

20

20

20

20

rnA
Mil.

Capacitance [5]
Parameters

Description
Input Capacitance
Output Capacitance

CIN
COUT

Test Conditions
TA = 25°C. f = 1 MHz.
Vee = 5.0V

Max.
5
7

Units
pF

Notes:
4. See the last page of this specification for Group A subgroup testing
information.
5. Tested initially and after any design or process changes that may
affect these parameters.
SA. VIL min. = -3.0V for pulse durations less than 30 ns.

I. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vcc on the CE input is required to keep the
device deselected during Vee power-up. otherwise ISB will exceed
values given.
3. TA is the "instant on" case temperature.

AC Test Loads and Waveforms
Rl48m
5 v O----AI'>I'r-...,
OUTPUT

Rl481U

5Vo----Jo/I,..,...,

0--_---+

r

30PF
INCLUDING

_JIGAND
- SCOPE

OUTPUT

':sn

_
-

Figure la
Equivalent to:

0--_--...

I':"~o~~O
5pF

INCLUDING

R2
26611

-=

Figure Ib

THEVENIN EQUIVALENT
187IZ
OUTPUT

O - -...\I'v.....- - O 1,73V

0056-8

2-124

0056-6

0056-7

Figure 2

5A~~===================
CY7C164
CY7C166

.

Switching Characteristics Over Operating Rangel4, 6]
7C164-ZO
7C166-20

Description

Parameters

Min.

Max.

7Cl64-25
7Cl66-25
Min.

Max.

7Cl64-35
7C166-35
Min.

Max.

7Cl64-45
7Cl66-45
Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

tOHA

Output Hold from Address
Change

20

25
20

5

tACE

CE LOW to Data Valid

tDOE

OE LOW to Data Valid

7C166

tLZOE

OE LOW to LOW Z

7C166

tHZOE

OE HIGH to HIGH Z

7C166

tLZCE

CE LOW to Low Zls]

tHZCE

CE HIGH to High Z[7, s]

tpu

CE LOW to Power Up

tPD

CE HIGH to Power Down

45

35
25

5

35
5

ns
45

5

ns
ns

20

25

35

45

ns

10

12

15

20

ns

3

3

8
5

3

10

0

12

5

5

8

10
0

20

15
5

15
0

20

ns

3

ns
15

0
20

ns

ns
ns

25

ns

WRITE CYCLE[9]
twc

Write Cycle Time

20

20

25

40

ns

tSCE

CE LOW to Write End

15

20

25

30

ns

tAW

Address Set-up to Write End

15

20

25

30

ns

tHA

Address Hold from Write End

0

0

0

0

ns

tSA

Address Set-up to Write Start

0

0

0

0

ns

tPWE

WE Pulse Width

15

15

20

20

ns

tSD

Data Set-up to Write End

10

10

15

15

ns

tHD

Data Hold from Write End

0

0

0

0

ns

tLZWE

WE HIGH to Low Zls]

5

5

5

5

tHzwE

WE LOW to High Z17, S]

7

7

10

ns
15

ns

Notes:

6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of I.SV, input pulse levels of 0 to 3.0V and output
loading of the specified Ior/IOH and 30 pF load capacitance.
7. tHZCE and tHzwE are specified with CL = 5 pF as in Figure I h.
Transition is measured ± 500 mV from steady state voltage.
S. At any given temperature and voltage condition, tHzcE is less than
tLZCE for any given device. These parameters are guaranteed and not
100% tested.

9. The internal write time of the memory is defmed by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
10. WE is HIGH for read cycle.
I!. Device is continuously selected, CE = VIL. (7CI66: OE = VIL
also.)
12. Address valid prior to or coincident with CE transition low.
13. 7CI66 only: Data I/O will be high impedance ifOE = VIH.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

~t:~~--------------------------tRc----------------------------1~.
ADDRESS
DATA OUT

_---1
___I:_~~~~~~-to~_H-A~~~~_t-A~A~:+:::::j-!------.-'I-~~~~~~~~~~~~~~~~~~~~~~~~__*_~~~~_-_-_-_-_-_-_-_-_-_-_-_PREVIOUS DATA VALID

~

DATA VALID
0056-9

2-125

til

fin~~=============================================================
.

CY7C164
CY7C166

.

Switching Waveforms (Continued)
Read Cycle No.2 (Notes 10, 12)
'RC

)t-

..,fotACE

DE

L

(Tel")

~tDDE
!--tLZDEi

DATA OUT

HIGH
IMPEDANCE

HIGH IMPEDANCE

1

VCC _ _ _ _ _
SUPPLY

CURRENT

DATA VALID

·1"'"

tLZCE

I---tpu

... ZOE .........
r--tHZCE-

~tPD

60%

_

0056-10

Write Cycle No.1 (WE Controlled) (Notes 9, 13)

ADDRESS

twc

--

tacE

\\ ,\\

[IIIIL r/LI/// / / I.
tAW

tHA-

tSA

t"'E

~\\
'I

tH~

tSD

t

DATA IN

DATA-IN VALID

'I

I---tHZWE~

-J'..

DATA I/O _ _ _ _ _ _ _ _ _D_A_T_A_U_N_DE_F_'N_E_D_ _ _ _ _ _ _

'\i

!--tLZWE

,

CE N '
HIGH IMPED A

--...:.;::;:;,:.,;::;:,.=;;,:,::=----(\'"._ _ _ _ __
0056-11

Write Cycle No.2 (<:;E Controlled) (Notes 9, 13)
~-------------------------twc------------------------~

~------- tSA

--------++0--

- - - t s c E - _ · · __ ·

~4---------------~--------~DATA-IN VALID

DATA IN

tHZWE:::j
DATA 110 --------DA-T-A-U-N-DE-F-,N-E-D.;...---

)

HIGH IMPEDANCE

0056-12

Note: If <:2 goes HIGH simultaneously with WI! HIGH, the output remains in a high impedance state,

2-126

(;n
.

CY7C164
CY7C166

~OO~================================================================

Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE

1.4

'/
Icy
./

1.2

~ 1.0

~
0

w

0.8

V

N

:::i 0.6
«

~
II:

0

z

1.2

<

!

~

~
U 0.8

5l

...
....:>

Vee: =5.0V
V,N =5.0V

'""

40

:>

0.2 r--ISB

ISB

60

:>

0.4

~

0.2

80

u
w
u
II:

«

II:

II:
II:

:>

0.6

:::i
:&

...

100

ffi

.1:
0
w

20

0

0.0
4.0

0.0
4.5

5.0

5.5

6.0

-55

SUPPLY VOLTAGE (VI

NORMALIZED ACCESS TIME

,

0

w

N

::;

«

:&
II:
0

z

..

:J

1.1

0

w

1.0

---

0.9
0.8
4.0

140

1.4

...

/'

1.2

5.0

4.5

:&
II:
0

-

5.5

1.0

z

0.8

., /

SUPPLY VOLTAGE (VI

j

:::i

«

30.0

2.5

25.0

!

2.0
1.5

-

../

0.0
0.0

1.0

2.0

3.0

/

4.0

SUPPLY VOLTAGE (VI

~ 10.0
5.0
0.0
5.0

V

---

0

20

200

0.0

1.0

2.0

3.0

4.0

NORMALIZED Icc

vs. CYCLE TIME

1.25 r----r-----r----.,
Vee:=5.OV
TA - 25'C
V,N-O.5V

~ 1.01----+----f--~

51

::;

/
TA ·2S'C
Vee -4.SOV

400

/
V

/

N

~

o

V

OUTPUT VOLTAGE (VI

/

~

0.5

40

Vee =5.0V
TA = 25'C

/

60

...

125

/

;;; 15.0

1.0

z

25

20.0

)"".

u;

...:>~

~

:&

Sl

80

TYPICAL ACCESS TIME CHANGE
vo. OUTPUT LOADING

3.0

0

II:

II:
II:

AMBIENT TEMPERATURE ('CI

TYPICAL POWER-ON CURRENT
VB. SUPPLY VOLTAGE

..'"

100

w

:>
u

Vee -5.0V

0.6
-55

6.0

4.0

l.

120

Z

..

/

'"

«

TA - 25'C

3.0

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

<
!

::;

..............

""

VS.

1.6

:J 1.2

2.0

1.0

OUTPUT VOLTAGE (VI

NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE

1.4

.

0.0

VS.

1.3

Vee = 5.0 V
TA = 25'C

o

125.0

25.0
AMBIENT TEMPERATURE ('CI

vs SUPPLY VOLTAGE

II

120

~

1.0

N

0.4

OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VS.

500

CAPACITANCE (pFI

800

1000

ii

0.751-----I7"!!::..-+----I

0.SOl·':0:----~20:---~30!o:---~40
CYCLE FREQUENCY (MHzl
0056-14

2-127

1m
.

CY7C164
CY7C166

~aoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

7C164 Truth Table

7C166 Truth Table

CE

WE

Input/Outputs

Mode

CE

WE

OE

Inputs/Outputs

Mode

H

X

HighZ

Deselect Power Down

H

X

X

HighZ

Deselect Power Down

L

H

Data Out

Read

L

H

L

Data Out

Read

L

L

Data In

Write

L

L

X

Data In

Write

L

H

H

HighZ

Deselect

Ordering Information
Speed
(ns)

20

25

35

45

Ordering Code

Package
Type

Operating
Range

Speed

Commercial

20

(ns)

Package
Type

Operating
Range

CY7C1 66-20PC

Pl3

Commercial

CY7C1 66-20VC

Vl3

Ordering Code

CY7C1 64-20PC

P9

CY7Cl64-20VC

Vl3

CY7Cl64-20DC

DIO

CY7C1 66-20DC

D14

CY7C1 64-20LC

L52

CY7C166-20LC

L54

CY7C1 64-25PC

P9

CY7C1 64-25VC

Vl3

CY7Cl64-25DC
CY7Cl64-25LC
CY7C1 64-25DMB

DIO

CY7C1 64-25LMB

L52

CY7C164-25KMB

K73

CY7C166-25PC

Pl3

CY7C166-25VC

Vl3

DIO

CY7C166-25DC

D14

L52

CY7C166-25LC

L54

CY7C166-25DMB

D14

CY7C166-25LMB

L54

CY7C166-25KMB

K73

Commercial

25

Military

CY7C166-35PC

Pl3

CY7C166-35VC

Vl3

DIO

CY7C166-35DC

D14

L52

CY7C166-35LC

L54

CY7C166-35DMB

014

CY7C166-35LMB

L54

CY7C166-35KMB

K73

CY7C164-35PC

P9

CY7C164-35VC

Vl3

CY7C164-35DC
CY7Cl64-35LC
CY7Cl64-35DMB

DIO

CY7Cl64-35LMB

L52

CY7Cl64-35KMB

K73

CY7Cl64-45PC

P9

CY7Cl64-45VC

Vl3

CY7C1 64-45DC
CY7Cl64-45LC
CY7Cl64-45DMB

DIO

CY7C164-45LMB
CY7C164-45KMB

Commercial

35

Military

Commercial

45

CY7C166-45PC

Pl3

CY7C166-45VC

V13

DIO

CY7C166-45DC

014

L52

CY7C166-45LC

L54

CY7C1 66-45DMB

014

L52

CY7C166-45LMB

L54

K73

CY7C166-45KMB

K73

Military

2-128

Commercial

Military

Commercial

Military

Commercial

Military

CY7Cl64
CY7C166

&n -=~~==~==~~~~~:A:d:M:e:SS:D::eS:i:gn;a;t;OD;r~s:::::::~:::::Pi;;n;:::i
~DUcroR
'UU~=- ~I _~A~d~dr~e~S ~ +-__~N~U~m~be~r= =
.

____

Function

A5

X4

3

A6
A7

X5

4

X3

A8
A9
AlO

All
A12
A13

AO
Al
A2
A3
A4

2-129

__

Address
Name

X6
I

X7

__

Y5
Y4

1

2

5

----+-

6

7
8

YO

9

Yl

17

Y2
Y3

18
19

XO

20

Xl

21

X2

fiA

• CYPRESS
SEMICONDUCTOR

CY7C164
CY7C166

===========================~~~~~

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

Ilx

1,2,3

IOZ

1,2,3

los

1,2,3

ICC

1,2,3

ISBI

1,2,3

ISB2

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

toHA

7,8,9,10,11

tACE

7,8,9,10,11

tOOE[I]

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAw

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

Note:
1. 7Cl66 only.

Document #: 38-00032-C

2-130

CY7C167

CYPRESS
SEMICONDUCTOR

16,384

Features

Functional Description

• Automatic power-down when
deselected

The CY7C167 is a high performance
CMOS static RAM organized as
16,384 words x 1 bit. Easy memory expansion is provided by an active LOW
chip enable (CE) and three-state drivers. The CY7C167 has an automatic
power-down feature, reducing the power consumption by 67% when deselected.

• CMOS for optimum
speed/power
• High speed-2S ns
• Low active power
-27SmW
• Low standby power
-83mW
• TIL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

X

Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW.
Data on the input pin (01) is written
into the memory location specified on
the address pins (Ao through A13).

Logic Block Diagram

1 Static R/W RAM
Reading the device is accomplished by
taking the chip enable (CE) LOW,
while write enable (WE) remains
HIGH. Under these conditions the
contents of the memory location specified on the address pins will appear on
the data output (DO) pin.
The output pin stays in lligh impedance
state when chip enable (CE) is HIGH
or write enable (WE) is LOW.

A die coat is used to insure alpha immunity.

Pin Configurations

u ....
-ou-

~~>~

2

I--+--t>---oo

A2
A3
A4
As
A6

3
4

17
16

S

DO
I~

!i I~
C)

A12
All
A10
Ag
AS
A7

is
0017-3

0017-2

WE

0017-1

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)

I

STD

I
I

Commercial
Military

2-131

7C167-25

7C167-35

7C167-45

25

35

45

60

60

50

60

50

•

~
CY7C167
~~~~R=============================================================
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C
Static Discharge Voltage ..................... > 2001 V
Ambient Temperature with
(per MIL-STD-883 Method 3015)
Latch-up Current. ......................... > 200 rnA
Power Applied .................... - 55°C to + 125°C

Operating Range

Supply Voltage to Ground Potential
(Pin 20 to Pin 10) .................... -0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V
DC Input Voltage ................... -3.0Vto +7.0V
Output Current into Outputs (Low) ............. 20 rnA

Ambient
Temperature
O"C to + 70"C
- 55°C to + 125°C

Range
Commercial
Military!3]

Vee
5V ±1O%
5V ±1O%

Electrical Characteristics Over Operating Range[4]
Description

Parameters

Test Conditions

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH
VIL
IIX

Icc

Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output ShortU]
Circuit Current
Vee Operating
Supply Current

ISB

Automatic Cil[2]
Power Down Current

Ioz
los

Vee = Min.,loH = -4.0mA
Vee = Min.,IOL = 12.0mA,
8.0 rnA Mil

GND:S;: VI:S;: Vee
GND::;; Vo::;; Vee
Output Disabled
Vee = Max.,
VOUT = GND
Vee = Max.
lOUT = OmA

7C167-25
Min. Max.
2.4
0.4

7C167-45
Min. Max.
2.4

0.4

Units
V

0.4

V

2.0
-3.0
-10

Vee
0.8
+10

2.0
-3.0
-10

Vee
0.8
+10

2.0
-3.0
-10

Vee
0.8
+10

V
V
p.A

-50

+50

-50

+50

-50

+50

p.A
rnA

Commercial
Military
Commercial
Military

Max. Vee,
CE ~ VIH

7C167-35
Max.
2.4

Min.

-350

-350

-350

60

60
60
20

50
50
IS
20

20

20

rnA
rnA

Capacitance [5]
Parameters

Description
Input Capacitance
Output Capacitance
Chip Enable Capacitance

CIN
COUT
CeE

Test Conditions
TA = 25°C, f = I MHz
Vee = 5.0V

Max.
4
6
5

Units
pF

Notes:
3. TA is the "instant on" case temperature.
4. See the last page ofthis specification for Group A subgroup testing
information.
S. Tested iuitially and after any design or process changes that may
affect these parameters.

1. Duration of the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vcc on the CE input is required to keep the
device deselected during Vee power-up, otherwise ISB will exceed
values given.

AC Test Loads and Waveforms
6v

R13290
(481 o MIL)

5v

O----""VI/Ir...,

OUTPUTo---~--4

INCLUDINOr30 pF
JIG AND
SCOPE

Rl3290
(481 o MIL)

:::-~-.:-.-:.-0%--r9O%~--~-'"

OUTPUTo---~--4
R2
20211
(26611 MILl

5.F

2020
(2550 MILl

INCLUDINGT"
JIG AND
SCOPE
'":'

J..

125n.

Figure Ib

COIOIERCIAL

167n.
OUTPUTOo-'INv---01.73V MILITARY

0017-6
0017-4

THEVENIN EQUIVALENT
OUTPUT 00-'INv---0 1.9V

90%10: ..
5

R2

Figure la
Equivalent to:

All Input Pulses

o---"";'''''VI/Ir...,

0017-5

2-132

Figure 2

~CYPRESS

CY7C167

~r~~==============~~
Switching Characteristics Over Operating Rangel4, 6]
Parameters

7C167·25

Description

Min.

Max.

7C167·35
Min.

Max.

7C167·4S
Min.

Units

Max.

READ CYCLE
Read Cycle Time (Commercial)

25

tRc

Read Cycle Time (Military)

25

tAA

Address to Data Valid (Commercial)

tAA

Address to Data Valid (Military)

toHA

Data Hold from Address Change

tACE

CE LOW to Data Valid

tLZCE

CE LOW to Low Z[B]

tHzcE

CE HIGH to High Z[7, B]

tpu

CE LOW to Power Up

tpD

CE HIGH to Power Down

tRC

30

40

35
25

3

40
40

ns

35

40

ns

3

5
15

0

ns

35

25

45
5

0

ns

ns

20

20

ns

30

3

5

ns

25
0

ns
ns

25

30

ns

WRITE CYCLE(9)
twc

Write Cycle Time

25

30

40

ns

tSCE

CE LOW to Write End

25

30

40

ns

tAW

Address Set-up to Write End

25

30

40

ns

tHA

Address Hold from Write End

0

0

0

ns
ns

tSA

Address Set-up to Write Start

0

0

0

tPWE

WE Pulse Width

15

20

20

ns

tSD

Data Set-up to Write End

15

15

15

ns

tHD

Data Hold from Write End

0

tHzWE

WE LOW to High Z[7, B)

tLZWE

WE HIGH to Low Z[B)

0

0
15

0

0

Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IorJIOH and 30 pF load capacitance.
7. tHZCE and tHZWE are specified with CL = 5 pF as in Figure 1h.
Transition is measured ± 500 mV from steady state voltage.
B. At any given temperature and voltage condition, tHZ is less than tLz
for any given device.

ns

20

20
0

ns
ns

9. The internal write time of the memory is defined by the overlap of
CE LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going high. The data
input setup and hold timing should be referenced to the rising edge

of the signal that terminates the write.

10. WE is HIGH for read cycle.
II. Device is continuously selected, CE

=

VIL.

12. Address valid prior to or coincident with CE transition LOW.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

.

~~~~-----------------------tRc-------------------------1~.

I:_~ ~ ~ ~to~H~A~ ~ t-A_A-: : : j-'- - - .-'~~~~~~~~~~~~~~~~~~~~~~~~~_*__-_-_-_-_-_-_-_-_-_~-_-_-_-_~

ADDRESS ._
-_
-_{
DATA OUT

PREVIOUS DATA VALID

I

~

DATA VALID

0017-7

2-133

EI

Switching Waveforms (Continued)
Read Cycle No.2 (Notes 10, 12)

'Re

J

IttACE

.-.HzeE-1

.LzeE::--!
HIGH IMPEDANCE

DATA OUT

1

If 1

Vee

I 1

DATA VALID

I'"'L~ '".~

I---'pu

SUPPLY _ _ _ _ _ _
CURRENT
_

I

HIGH
IMPEDANCE

J

-'PO --J

SQ;-'1c-

SO%

ICC
ISS
0017-8

Write Cycle No.1 (WE Controlled) (Note 9)

ADDRESS

,

twe

~~
'SCE

~'

~II

\.\\
tAw

II, 'II I I I I I I I,
'HA-

tpwE

tsA

\\\'

"}

I

t

DATA IN

'H~

tsD

DATA-IN VALID
')

!---'HZWE

==\!

!--'UWE

~

HIGH IMPEDANCE
DATAlro _______________D_A_TA
__
UN_D_E_FI_N_ED
_ _ _ _ _ _ _ _ _ _ _-J/~----~~~~~~----~\~
_____________
0017-9

Write Cycle No.2 (CE Controlled) (Note 9)
~-----------------------twe------------------------~
ADDRESS

-----1-o-------••e'------+\

I---+-------·SD-----+DATA-IN VALID

DATA IN

tHzwe----t
DATA I/O

-------------------------;.------~
DATA UNDEFINED

HIGH IMPEDANCE

I~-------------------;;.;,;.;.;.;.;;;.;;;;.;,;.;;.;..--------0017-10

Note: IfeE goes HIGH simultaneously with WI! HIGH, the output remains in a high impedance state.

2-134

~
CY7C167
~~~aoR================================================================
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
VB. SUPPLY VOLTAGE
1.4

lev / '

1.2

.!l
U

Jt

1.0
0.8

~
N
:; 0.6

"

./'

V

0

z

r---...

1.0

N

:;

'"

:;:
II:

0.0
4.0

w

0.6

u

0.4

5.S

6.0

1.3

N

"

1.0

.............

"

TA - 25°C

:;:

II:

-

............-.

0.9

5.0

6.5

./

",.".,./

1.0

/
.....

z
0.8

6.0

TYPICAL POWER·ON CURRENT

:;

0

z

2.0

.

oS

20

"

~
w

1.0
O.S

-

,/

0.0

1.0

2.0

3.0

/

4.0

SUPPLY VOLTAGE (VI

C

/

10

/
5.0

200

3.0

"

4.0

50

.
.

25

..-

/
I

/

/

Vee =5.0V
TA = is'C

1.0

125

2.0

3.0

4.0

5.0

OUTPUT VOLTAGE (VI

NORMALIZED ICC
CYCLE TIME

VB.

1.1r-----r----r----,

~5·C

:!

I.S

0.0

75

TYPICAL ACCESS TIME CHANGE
VI. OUTPUT LOADING

Vee = 4.S V

:;:
II:

u

"
iii
z

:J

TA •

N

"

zw 100

II:
II:

0

30

2.5

0

,/'

AMBIENT TEMPERATURE (CI

vs. SUPPLY VOLTAGE

.

125

~

25

SUPPLY VOLTAGE (VI

1

"..!
:J

Vee'" 5.0 V

-55

3.0

2.0

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

0.6
4.5

1.0

OUTPUT VOLTAGE (VI

1.4

0

0.8

4.0

"-

150

:!
1.2
~
N
:;

:! 1.2

0

~

10

NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

.

............

20

o
o

125.0

25.0

1.6

:;:

30

AMBIENT TEMPERATURE ("CI

.
z

:J
0

-55

NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE

:; 1.1

""-

40

Vee" 5.0 V
TA = 25"C

:J

0.2 - 1 ' 8

1.4

0

.'"
::

Vee =5.0V
VtN "'5.0V

0.0
5.0

4.5

til

t'-..

II:
:3

0

SUPPLY VOLTAGE (VI

II:

Z
w

II:
II:

50

U

z

fSB

.."!
:J

0

0.2

.

~

.!l
cw

0.4

OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
60

U 0.8
Jt

:;:
II:

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VB.
1.2

V

/

~

Vee

1l

V

1.01----1---....,1----".1

5l

N

:;

!
~

400

= 5.0

TA = 25'C
VIN = 0.5 V

600

CAPACITANCE (pFI

800

1000

0.91----1r-71.c....-\----\

20

40

30

CYCLE FREQUENCY (MHz)

0017-11

2-135

~

CY7C167

~r~~==================~
Ordering Information

I

Speed

Icc

(ns)

mA

25

60

35

45

60

50

Ordering
Code
CY7C167-25PC

Package
Type

Operating
Range

P5

Commercial

CY7C167-250C

06

CY7C167-25LC

L51

CY7C167-25VC

V5

CY7C167-35PC

P5

CY7C167-350C

06

CY7C167-35LC

L51

CY7C167-35VC

V5

CY7C167-350MB

06

CY7C167-35LMB

L51

CY7C167-45PC

P5

CY7C167-450C

06

CY7CI67-45LC

L51

CY7C167-45VC

V5

CY7C167-450MB

06

CY7CI67-45LMB

L51

Commercial

Military
Commercial

Military

2-136

MILITARY SPECIFICATIONS
Group A Subgroup Testing

•

DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

ISB

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

taHA

7,8,9,10,11

tACE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpWE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

Document #: 38-00033-0

2-137

CY7C167A

CYPRESS
SEMICONDUCTOR

16,384

Features

Functional Description

• Automatic power·down when
deselected

The CY7C167A is a high performance
CMOS static RAM organized as
16,384 words x 1 bit. Easy memory expansion is provided by an active LOW
chip enable (CE) and three-state drivers. The CY7C167A has an automatic
power-down feature, reducing the power consumption by 67% when deselected.

• CMOS for optimum
speed/power
• High speed-20 ns
• Low active power
-275 mW
• Low standby power
-83mW

X

Reading the device is accomplished by
taking the chip enable (CE) LOW,
while write enable (WE) remains
HIGH. Under these conditions the
contents of the memory location specified on the address pins will appear on
the data output (DO) pin.
The output pin stays in high impedance
state when chip enable (CE) is HIGH
or write enable (WE) is LOW.

Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW.
Data on the input pin (01) is written
into the memory location specified on
the address pins (Ao through A13).

• TTL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

1 Static R/W RAM

A die coat is used to insure alpha immunity.

• VIH of 2.2V

Logic Block Diagram

Pin Configurations

_

r-+---f>---DO

A2
A3
A4
A5
As

DO

0

u"'
u_

-c-c>-c

AD

Vee

2

A,

A'3

A2

A'2

A3

An

AI.

A'D

A.

At!

18
17
16
15
14
13

3
4
5
6
7
8

A'2
All
A '0
Ag
A8

A.

A7

I~ (!)
~Il:! is

DO

A7

WE

01
~

GND

0161-3

0161-2

0161-1

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)

I

STD

I
I

Commercial

7C167A·20

7C167A·25

7C167A·35

7C167A·45

20

25

35

45

80

60

60

50

70

60

50

Military

2-138

~
CY7C167A
~~~~R================================================================
Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65'C to + 150"C
Static Discharge Voltage ..................... > 2001 V
(Per MIL-STD-883 Method 3015)
Ambient Temperature with
Latch-up Current .......................... > 200 rnA
Power Applied .................... - 55'C to + 125'C
Supply Voltage to Ground Potential
Operating Range
(Pin 20 to Pin 10) .................... -0.5V to + 7.0V
Ambient
DC Voltage Applied to Outputs
Range
Vee
Temperature
in High Z State ...................... -0.5V to +7.0V
Commercial
O"Cto +70"C
5V ±IO%
DC Input Voltage ................... - 3.0V to + 7.0V
Military[3]
- 5S'C to + 125'C
SV ±IO%
Output Current into Outputs (Low) ............. 20 rnA

Electrical Characteristics Over Operating Range[4)
Parameters

Description

7C167A-20

Test Conditions

Min.
VOH

Output HIGH Voltage

Vee = Min., IOH = - 4.0 rnA

VOL

Output LOW Voltage

Vee = Min.,IOL = 12.0 rnA,
S.OmAMii

VIR

Input HIGH Voltage

VIL

Input LOW Voltage[SA]

IIX

Input Load Current

GND

loz

7C167A-25

7C167A-35

7C167A-45

Units

Max. Min. Max. Min. Max. Min. Max.

2.4

2.4

2.4

0.4

2.4
0.4

0.4

V
0.4

V
V

2.2

Vee

2.2

Vee

2.2

Vee

2.2

Vee

-0.5

O.S

-0.5

O.S

-0.5

O.S

-0.5

O.S

V

Vee

-10

+10

-10

+10

-10

+10

-10

+10

/LA

Output Leakage
Current

GND S; Vo S; Vee
Output Disabled

-10

+10

-10

+10

-10

+10

-10

+10

/LA

los

Output Short(1)
Circuit Current

Vee = Max.,
VOUT = GND

rnA

Icc

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

Automatic CIt[2]
Power Down Current

Max. Vee.
CE;;' VIR

ISB

S;

VI

S;

Commercial

-350

-350

-350

-350

SO

60

60

50

70

60

50

Military

40

Commercial
Military

20

20

15

20

20

20

rnA
rnA

Capacitance [5]
Parameters

Description

Max.

Test Conditions

CIN

Input Capacitance

CoUT

Output Capacitance

CeE

Chip Enable Capacitance

Units

4

TA = 25'C, f = I MHz
Vee = 5.0V

6

pF

5

Notes:
\. Duration of the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the CE input is required to keep the
device deselected during Vee power-up, otherwise ISB will exceed

4. See the last page of this specification for Group A subgroup testing
information.
5. Tested initially and after any design or process changes that may
affect these parameters.
SA. VIL min. = - 3.0V for pulse durations less than 30 ns.

values given.

3. TA is the "instant on" case temperature.

AC Test Loads and Waveforms
R13290
(481 o MIL)

R13290
(481 o MIL)

6Vo-------~~_,

OUTPUT o-----~----.......

'NCLUD'NGI30 pF
JIG AND
SCOPE

5

3.0

.......
2020
(2550 MILl

'NCLUD,Nl
JIG AND
SCOPE

-=-

-=-

Figure Ib

125Jl

COMMERCIAL

167Jl

OUTPUT~1.73V MILITARY

GND

R2
6pF

THEVENIN EQUIVALENT
OUTPUT~1.9V

V-----.z.=----i..

OUTPUT o-----~----

R2
2020
(2&60 MIL)

Figure la
Equivalent to:

All Input Pulses

v o-------~~_,

0161-5

2-139

0161-6

0161-4

Figure 2

fII

~

CY7C167A

CYPRESS

~~~~u~====================================================~~==~~
Switching Characteristics Over Operating Rangel4, 6]
Parameters

7C167A-20

Description

Min.

7C167A-25

Max.

Min.

Max.

7C167A-35
Min.

7C167A-45

Max.

Min.

Units

Max.

READ CYCLE

20

tRC

Read Cycle Time (Commercial)

tRC

Read Cycle Time (Military)

tAA

Address to Data Valid (Commercial)

tAA

Address to Data Valid (Military)

tOHA

Data Hold from Address Change

tACE

CE LOW to Data Valid

tLZCE

CE LOW to Low Z[S]

tHZCE

CE HIGH to High Z[7, S]

tpu

CE LOW to Power Up

tpD

CE HIGH to Power Down

25

30

40

ns

25

35

40

ns

20

25

5

5
20

30
35
5

0

0
20

5
15

20

0
20

ns

ns
ns

15

0

ns

ns

45

5
10

8

5
35

25
5

5

40
40

ns
ns

25

ns

WRITE CYCLE[9]
twc

Write Cycle Time

20

20

25

40

ns

tSCE

CE LOW to Write End
Address Set-up to Write End

20
20

25
25

30
30

ns

tAW

15
15

tHA

Address Hold from Write End

0

0

0

0

ns

tSA

Address Set-up to Write Start

0

0

0

0

ns

tPWE

WE Pulse Width

15

15

Data Set-up to Write End

10

10

20
15

tHD

Data Hold from Write End

0

0

20
15
0

ns

tSD

tHzWE

WE LOW to High Z[7, S]

tLZWE

WE HIGH to Low ZIS]

7

5

5

ns

0

ns

15

10

7

ns

5

5

ns
ns

Notes:

9. The internal write time of the memory is defined by the overlap of
ell: LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going high. The data
input setup and hold timing should be referenced to the rising edge
of the signal that terminates the write.
10. m is HIGH for read cycle.
I!. Device is continuously selected, CE = VII..
12. Address valid prior to or coincident with CE transition LOW.

6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOr/IOH and 30 pF load capacitance.
7. tHZCE and tHzwE are specified with CL = 5 pF as in Figure lb.
Transition is measured ± 500 mV from steady state voltage.
S. At any given temperature and voltage condition, tHZ is less than tLZ
for any given device.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

ADDRESS

~~------------------------tRC--------------------------*
.!
-

~

DATA OUT

tOHA

tAA

-

-

______

.'

PREVIOUS DATA VALID

DATA VALID

0161-7

2-140

~
CY7C167A
~~~~~================================================================
Switching Waveforms (Continued)

Read Cycle No.2 (Notes 10, 12)

j

'RC
tACE

I--'Hzc'-I

'LZCE=-!
DATA OUT

VCC

II

-,f-

~

IJ' I

HIGH IMPEDANCE

1

I~

I

I

'\. ~ '\.

L

DATA VALID

~

I----',u

SUPPLY _ _ _ _ _
CURRENT
_

HIGH
IMPEDANCE

f

!---'PO ---j

ICC

~ISB

50%

0161-8

Write Cycle No.1 (WE Controlled) (Note 9)

ADDRESS

,
-

twc

'SCE

\\ r-,.\\

IIIII 'II I I I I I I I.
lAw

,

!sA

. . .E

"'A-

\\\

J.

DATA IN

'so
DATA-IN VALID

-'HZWE ==\!

"'::1
I:
-'LZWEV

HIGH IMPEDANCE

______________

DATAI~ __________________D_A_TA
__
UN_D_E_F_IN_E_D________________JI}----~~~~~~----~\~

0161-9

Write Cycle No.2 (CE Controlled) (Note 9)
~--------------------------twc--------------------------~

____+====.!:..:===~I-----------'SCE ------t-------+------------------

~_t_-------------'.D-------_+-

DATA-IN VALID
tHZW1----i

,>------------------======-----------

---------------------------------~
DATA I/O

DATA UNDEFINED

HIGH IMPEDANCE

0161-10

Note: IfCl'! goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

2-141

~

CY7C167A

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Typical DC and AC Characteristics
NOR~SUPPLYCURRENT
VS.

Icy
../'

1.2

II

lic

NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

SUPPLY VOLTAGE

1.4

1.0

O.B

.. V

./

1.0

...c

::!

.

cz

0
2

N

:::;

::!

a: 0.4

a:

4.5

5.0

0

0.4

~

:!

!

r---.....

0.9
O.B
4.0

4.5

--

..
a:

-

5.5

5.0

::!

./

1.2

1.0

z
0.8

6.0

0.0

1.0

2.0

-V
3.0

4.0

SUPPLY VOL TAG E (VI

/

0

5.0

4.0

oV

200

...-

50
25

/

1

Vee =5.0V
TA ",SOC
1.0

2.0

3.0

4.0

5.0

OUTPUT VOLTAGE (VI

NORMALIZED ICC
CYCLE TIME

VS.

1.1,----,---.,...---.,

"~'C

20

0.0

.

0

N

/

'"

/

75

125

25

TA
Vee =4.5V

0.5

'"
...1i'i::>
...::>

TYPICAL ACCESS TIME CHANGE
VS. OUTPUT LOADING

2.5
2.0

3.0

z

Vee" 5.0 V

0.6
-55

30

1.0

u

AMBIENT TEMPERATURE rCI

3.0

~

V

100

0

TYPICAL POWER·ON CURRENT
VS. SUPPLY VOLTAGE

1.5

Z

OJ

a:

to:
::>

/'

/

0

SUPPLY VOLTAGE (VI

~

125

I-

"'N:::;

TA = 25"C

2.0

OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
~

1.4

z

1.0

150

~

0

5.0V

OUTPUT VOLTAGE (VI

1.6

............

10

o
o

125.0

=

= 25"C

"I'-.

::>

::>
0

25.0

20

I-

NORMALIZED ACCESS TIME

a: 1.0
0

a:



vs. SUPPLY VOLTAGE

::!

~

::>

6.0

5.5

1.3

..

OJ

a:
a:

0.0

1.4

::l

~

50

Z

0.6

SUPPLY VOLTAGE (VI

fil
N

!

I-

0.2 t--ISB

fSB

0.0
4.0

~

U 0.8
2

::l 0.6

OUTPUT SOURCE CURRENT
VB. OUTPUT VOLTAGE
60

II

"'N

0.2

r---..-

1.2

V
400

V

600

CAPACITANCE (pFI

V

800

1DOD

CYCLE FREQUENCY (MHzI

0161-11

2·142

~
CY7C167A
~~~DUcroR================================================================~
Ordering Information
Speed
(ns)

Icc

20

60

2S

3S

45

rnA

60

60

50

Ordering
Code

Package
Type

Operating
Range

CY7CI67A-20PC

PS

Commercial

CY7CI67A-20DC

D6

CY7CI67A-20VC

VS

CY7C167A-2SPC

PS

CY7C167A-2SDC

D6

CY7CI67A-2SLC

LSI

CY7CI67A-2SVC

VS

CY7CI67A-2SDMB

D6

CY7CI67A-2SLMB

LSI

CY7C167A-3SPC

PS

CY7CI67A-3SDC

D6

CY7CI67A-3SLC

LSI

CY7CI67A-35VC

V5

CY7CI67A-35DMB

D6

CY7CI67A-35LMB

L51

CY7CI67A-4SPC

PS

CY7CI 67A-45DC

D6

CY7CI67A-45LC

L51

CY7CI67A-45VC

VS

CY7CI67A-35PC

PS

CY7CI67A-45DMB

D6

CY7CI67A-45LMB

L51

Commercial

Military
Commercial

Military
Commercial

Military

2-143

fJI

~

CY7C167A

~r~~===================
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics

I

Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

ISB

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

taHA

7,8,9,10,11

tACE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpWE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

Document 11: 38-00093

2-144

CY7C168
CY7C169

CYPRESS
SEMICONDUCTOR

4096

X

4 Static R/W RAM

Features
Data on the four input/output pins
(1/00 through 1/03) is written into the
memory location specified on the address pins (Ao through All).
Reading the device is accomplished by
taking chip enable (CE) LOW, while
write enable (WE) remains HIGH. Under these conditions the contents of the
memory location specified on the address pins will appear on the four data
I/O pins.
The I/O pins stay in high impedance
state when chip enable (CE) is HIGH,
or write enable (WE) is LOW.
A die coat is used to insure alpha immunity.

• Capable of withstanding greater
than 2001V electrostatic
discharge

• Automatic power-down when
deselected (7CI68)
• CMOS for optimum speed!
power

Functional Description

• High speed
- 25 ns tAA
- 15 ns tACE (7CI69)

The CY7Cl68 and CY7Cl69 are high
performance CMOS static RAMs organized as 4096 x 4 bits. Easy memory
expansion is provided by an active
LOW chip enable (CE) and three-state
drivers. The CY7Cl68 has an automatic power-down feature, reducing the
power consumption by 77% when deselected.
Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW.

• Low active power
-385 mW
• Low standby power (7CI68)
-83mW
• TIL compatible inputs and
outputs

Logic Block Diagram

Pin Configurations

AO

1/0 0

Al

A.

Vee

A5

A3

Ao

A2

A7

Al

As

Ao

Ag

1/0 0

AlO

1/0,

A11

1/02

CE

1/03

GND

WE

1/0,

A2

0021-2

A3

1/02

A4

It')

....

~,.,

«><

A6
1/0 3

AS--'_L_-'

A2
A,

A6
A7
As
Ag
A'0

CE

WE

Ao
1/°0
1/°1
1/°2

All
0021-1

I.....
°1 . . . '"
()~~~
0021-3

Selection Guide
7C168-2S
7C169-2S
Maximum Access Time (ns)
Maximum Operating
Current (mA)

I

STD

I
I

Commercial
Military
2-145

7C168-3S
7C169-3S

7C169-40

7C168-4S

25

35

40

45

90

90

70

70

90

70

70

EI

fin
.

CY7C168
CY7C169

~~===================

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + l50"C

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latch-up Current .......................... > 200 mA

Supply Voltage to Ground Potential
(Pin 20 to Pin 10) .................... -0.5Vto +7.0V

Operating Range
Ambient
Temperature

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to + 7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial
Military[2]

Output Current into Outputs (Low) ............. 20 mA

Vee

O"Cto +70"C

5V ±1O%

- 55°C to + 125°C

5V ±1O%

Electrical Characteristics Over Operating Range!3]
Parameters

Description

7C168-25
7C169-25

Test Conditions

Min.

Max.

7C168-45
7C169-40

7C168-35
7C169-35
Min.

Max.

VOH

Output HIGH Voltage

Vee = Min.,loH = -4.0rnA

VOL

Output LOW Voltage

Vee = Min., IOL = 8.0 rnA

VIH

Input HIGH Voltage

2.0

Vee

Input LOW Voltage

-3.0

Vee
0.8

2.0

VIL

-3.0

0.8

IIX

Input Load Current

GND:S: VI:S: Vee

-10

+10

-10

+10

loz

Output Leakage
Current

GND :S: Vo :S: Vee,
Output Disabled

-50

+50

-50

+50

los

Output Short Circuit
Current[!l

Vee = Max., VOUT = GND

lee

Vee Operating
Supply Current

Vee = Max.
lOUT = ornA

Commercial

Automatic CE
Power Down Current

Max. Vee,
CE;;:: VIH

Commercial

ISB!

Automatic CI!
Power Down Current

Max. Vee,
CE;;:: Vee - 0.3V

Commercial

ISB2

2.4

Min.

2.4
0.4

2.4
0.4

90

Military
20

Military
11

Military

V
0.4

V

2.0

Vee

V

-3.0

0.8

V

-10

+10

/LA

-50

+50

/LA

-350

rnA

-350

-350

Units

Max.

70

70

90

70

20

15

20

20

11

11

20

20

rnA
rnA
rnA

Capacitance [4]
Test Conditions

Max.

Units

CIN

Parameters

Input Capacitance

Description

TA = 25°C, f = 1 MHz, Vee = 5.0V

4

pF

CoUT

Output Capacitance

TA = 25°C, f = 1 MHz, Vee = 5.0V

7

pF

Notes:
I. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.

3. See the last page of this specification for Group A subgroup testing
information.
4. Tested iuitially and after any design or process changes that may
affect these parameters.

2. TA is the "instant on" case temperature.

AC Test Loads and Waveforms
OUTPUT

5 V o---------"''''''~

o------

u
w
u

0.6

:::l

:Ii

:Ii

'"~

0.4
0.2

'51"

80

60

0.4

.

Vee -S.OV
V,N -S.OV

.a

::>

~

20

0

0.0
4.0

0.0
5.0

4.5

5.5

6.0

SUPPLY VOLTAGE IVI

NORMALIZED ACCESS TIME
SUPPLY VOLTAGE

1.3

0

0

.

1.1

'"z

1.0

:::l

............

:Ii
0

""-

0.9
0.8
4.0

--

.

!

..

./

1.2

:::l

:Ii
0

-

'"z

0.8

~

-55

30.0

2.5

25.0

2.0

!

1.5

;; 15.0

25

20.0

0.5
0.0

0.0

1.0

2.0

-

3.0

~ 10.0

/

V

5.0
0.0

4.0

SUPPLY VOLTAGE IVI

....

60

::>

.a

::>
0

20

/V'

I

L
V

5.0

V
200

1.0

2.0

3.0

4.0

NORMALIZED Icc
VI. CYCLE TIME
1.1 .....- - ' " " ' - - - . . , . - - - - ,

Vee - &.0 V
TA

~

= 25'C

-+__"""'::III

1.0 t-_I/J_N_"_Ot.5_V
__

~

:::l

/
TA = 2S'C
Vee =4.50 V

400

Vee ·S.OV
TA • 2S·C

/

0
0.0

.--

~

o

/

OUTPUT VOLTAGE IV)

/

~
1.0

80

'"'"
u
z"
in

125

/

:

w

i
i'"

::>

TYPICAL ACCESS TIME CHANGE
VS. OUTPUT LOADING

3.0

N

:::l

Vee' 5.0 V

100

AMBIENT TEMPERATURE I·CI

TYPICAL POWER·ON CURRENT
vs. SUPPLY VOLTAGE

0

/"

zw

0.6

6.0

5.5

1.0

SUPPLY VOLTAGE IVI

j

/'

N

TA • 25·C

5.0

4.5

w

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

C 120

1.4

c

;1

"

4.0

3.0

VI.

l.a

1.6

c
;1 1.2

2.0

OUTPUT VOLTAGE IVI

NORMALIZED ACCESS TIME
vo. AMBIENT TEMPERATURE

VI.

w

1.0

0.0

125.0

25.0
AMBIENT TEMPERATURE I·CI

1.4

N

o

-55

" '" "

Vee' S.OV
TA • 25'C

::>

0.2 r - - I ••

lsa

100

zw

0

w

•

OUTPUT SOURCE CURRENT
VI OUTPUT VOLTAGE

120

i.

-.........::..

J!

:::l 0.6

'"~

~

1.0

~

[/"

0.8

1.2

./

. V

w

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

vs SUPPLY VOLTAGE

1.•

600

CAPACITANCE IpFI

800

1000

i~

0.91----+-----::o>l'----i----I

20

.a

30

CYCLE FREQUENCY IMHz!

0021-11

2-149

Speed

Icc

(ns)

mA

25

90

35

45

90

70

Ordering Code

Package
Type

Operating
Range

Speed
(ns)

ICC

COlIlIJlercial,

25

90

mA

Ordering Code

Package
Type

Operating
Range
Commercial

CY7CI68-2SPC

PS

CY7CI69-2SPC

PS

CY7CI68-2SDC

D6

CY7CI69-2SDC

D6

CY7CI68-2SLC

LSI

CY7CI69-2SLC

LSI

CY7CI68-2SVC

VS

CY7CI69-2SVC

VS

CY7CI68-3SPC

PS

CY7CI68-3SDC

CY7CI69-3SPC

PS

D6

CY7CI69-3SDC

D6

CY7CI68-3SLC

LSI

CY7CI69-3SLC

LSI

CY7CI68-3SVC

VS

CY7CI69-3SVC

VS

CY7CI68-3SDMB

D6

CY7CI69-3SDMB·

D6

CY7CI68-3SLMB

LSI

CY7CI69-3SLMB

LSI

Commercial

35

90

Military

CY7CI68-4SPC

PS

CY7CI69-4OPC

PS

CY7CI68-4SDC

D6

CY7CI69-4ODC

D6

CY7CI68-4SLC

LSI

CY7CI69-4OLC

LSI

CY7CI68-4SVC

VS

CY7CI68-4SDMB

D6

CY7CI68-45LMB

L51

Commercial

40

Military

2-150

70

CY7CI69-4OVC

VS

CY7CI69-4ODMB

D6

CY7CI69-4OLMB

LSI

Commercial

Military
Commercial

Military

&n
.

CY7C168
CY7C169

~~=======================================

MILITARY SPECIFICATIONS

Group A Subgroup Testing

•

DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

loz

1,2,3

Icc

1,2,3

ISBI [I2]

1,2,3

ISB2[12]

1,2,3

Note:
12. 7Cl68 only.

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

toHA

7,8,9,10,11

tACE

7,8,9,10,11

tRCS

7,8,9,10,11

tRCH

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpwE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

Document #: 38-00034-0

2-151

CY7C168A
CY7C169A

CYPRESS
SEMICONDUCTOR

4096

X

4 Static R/W RAM

Features
• Capable of withstanding greater
than 2001V electrostatic
discharge

• Automatic power·down when
deselected (7CI68A)
• CMOS for optimum speed/
power

Functional Description

• High speed
- 20 us tAA
- 15 us tACE (7CI69A)
• Low active power
-385 mW
• Low standby power (7CI68A)
-83mW

• TIL compatible inputs and
outputs

The CY7C168A and CY7C169A are
high performance CMOS static RAMs
organized as 4096 x 4 bits. Easy memo·
ry expansion is provided by an active
LOW chip enable (CE) and three·state
drivers. The CY7C168A has an automatic power-down feature, reducing
the power consumption by 77% when
deselected.
Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW.

• VIH of 2.2V

Logic Block Diagram

Data on the four input/output pins
(1/00 through 1/03) is written into the
memory location specified on the address pins (Ao through All).
Reading the device is accomplished by
taking chip enable (CE) LOW, while
write enable (WE) remains HIGH. Under these conditions the contents of the
memory location specified on the address pins will appear on the four data
I/O pins.
The I/O pins stay in high impedance
state when chip enable (CE) is HIGH,
or write enable (WE) is LOW.
A die coat is used to insure alpha immunity.

Pin Configurations

1100

Ao

Vee

A5

A3

lie

A2

A7

A,

lie

Ao

As

1100

A,o

liD,

A11

1/02

CE

1/03

GND

WE

1/0,

0162-2



0162-3

Selection Guide
7C168A-20
7C169A·20
Maximum Access Time (ns)
MaximJlm Operating
Current (mA)

I

STO

I

I

Commercial
Military

7Cl68A-25
7C169A·25

7Cl68A-35
7C169A·35

20

25

35

90

70
80

70
70

2-152

7C169A-40

7Cl68A-4S

40
50

45

70

50
70

5A~~==========================================================~
CY7C168A
CY7C169A

.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... > 200IV
(Per MIL-STD-883 Method 3015)

Storage Temperature ............... -65·C to + 150·C
Ambient Temperature with
Power Applied .................... - 55·C to + 125·C

Latch-up Current .......................... > 200 rnA

Supply Voltage to Ground Potential
(Pin 20 to Pin 10) .................... -0.5Vto +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... - O.5V to + 7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial
Military(2)

Output Current into Outputs (Low) ............. 20 rnA

Ambient
Temperature
O·Cto +700C
- 55°C to + 125°C

Vee
5V ±to%
5V ±to%

Electrical Characteristics Over Operating Range[3]
Description

Test Conditions
Vee = Min., IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA

los

Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[4A)
Input Load Current
Output Leakage
Current
Output Short Circuit
Currentlll

IcC

Vee Operating
Supply Current

Vee = Max.
lOUT = ornA

ISBI

Automatic CE
Power Down Current

a!

ISB2

Automatic CE
Power Down Current

Parameters
VOH
VOL
VIH
VIL
IIX
Ioz

7Cl68A·20
7C169A·20
Min. Max.
2.4
0.4
2.2 Vee
-0.5 0.8
-10 +10

GND::;; VI::;; Vee
GND ::;; Vo ::;; Vee,
Output Disabled

7Cl68A·25
7C169A·25
Min. Max.
2.4
0.4
2.2 Vee
-0.5 0.8
-10 +10

7Cl68A·35
7C169A·35
Min. Max.
2.4
0.4
2.2 Vee
-0.5 0.8
-to +10

7Cl68A·45
7C169A·40 Units
Min. Max.
2.4
V
0.4
V
2.2 Vee
V
-0.5 0.8
V
-to +10 p.A

-to +to -to +to -to +to -to +10

Vee = Max., VOUT = GND

-350

-350

-350

Commercial
Military

90

Commercial
Military
Commercial
Max. Vee,
CE ~ Vee - 0.3V Military

40

70
80
20
20
20
20

70
70
20
20
20
20

Max. Vee,
~ VIH

20

p.A

-350 rnA
70
70
20
20
20
20

rnA
rnA
rnA

Capacitance [4]
Parameters

Description
Input Capacitance
Output Capacitance

CIN
CoUT
Notes:

Test Conditions
TA = 25°C, f = I MHz, Vee = 5.0V
TA = 25·C, f = 1 MHz, Vee = 5.0V

I. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.

Max.
5
7

Units
pF
pF

3. See the last page of this specification for Group A subgroup testing
information.
4. Tested initially and after any design or process changes that may
affect these parameters.
4A. VIL min. = - 3.0V for pulse durations less than 30 ns.

2. TA is the "instant on" case temperature.

AC Test Loads and Waveforms
5V~------~~r-~

RI48llZ

RI481l!
5 v Q--------J

0.6

III:

0.4

~

...::>
...::>

Vee -5.0V
V,N =5.0V

A-

Vee =5.0 V
TA = 25°C

""'"

::>

0.2 r-ISB

ISB

...z
W

0

:::;

OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE

VB

120

C

~

./'

V

N

II:

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VB

VB

1.4

40
20

0

0.0
4.0

0.0
4.5

5.0

5.5

6.0

-55

SUPPLY VOLTAGE (VI

NORMALIZED ACCESS TIME
SUPPLY VOLTAGE

...

NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE

1.3

:::; 1.1

............

~

z

1.4

0
w

1.2

./

1.0

r--

:&

II:

4.5

5.0

5.5

/

z
0.8

TYPICAL POWER-ON CURRENT
VB. SUPPLY VOLTAGE

0

2.5

25.0

2.0

1 20 .0
;( 15.0

:&

!:i

c

1.0
0.5

0.0
0.0

1.0

2.0

-

3.0

4.0

SUPPLY VOLTAGE (VI

80

'"z

60

125

5.0

5.0

0.0

/

200

Vee =5.0V
TA = 25'C

V

20

/

/

V

0.0

1.0

2.0

4.0

3.0

NORMALIZED Icc
VB. CYCLE TIME
1.1.---...,.----r---.....,

~
51

~

/
TA = 25'C
Vee =4.50 V

400

/"

Vee' 5.0 V
TA = 25'C
V,N = 0.5 V
1.01-----+----+---""

N

V

o

4.0

OUTPUT VOLTAGE (VI

-

/
/

/

40

0

~ 10.0

/

/

::>
u

...::>
.....::>

25

..

:::; 1.5

i

100

W
III:
III:

TYPICAL ACCESS TIME CHANGE
VB. OUTPUT LOADING
30.0

N

II:

...z

AMBIENT TEMPERATURE ('CI

3.0

~
3.0

l

iii

Vee = 5.0 V

0.6
-1i5

6.0

SUPPLY VOLTAGE (VI

...

120

0

0.8
4.0

1.0

0

-

0.9

E

/

C

TA = 25'C

C

!

:::;

............

"

140

N

N

0

..

$

1.2

2.0

OUTPUT SINK CURRENT
VB. OUTPUT VOLTAGE

1.6

0

II:

1.0

OUTPUT VOLTAGE (VI

VB.

VB.

..

0.0

AMBIENT TEMPERATURE ('CI

1.4

$

o

125.0

25.0

600

CAPACITANCE (pFI

800

1000

i

0.91----+--::11'--+---1

20

30

40

CYCLE FREQUENCY (MHz)
0162-11

2-156

fiA
.

CY7C168A
CY7C169A

~NDU~ ================================================================~

Ordering Information
Speed ICC
(ns)
rnA
20
90

Ordering Code
CY7C168A-20PC
CY7C168A-200C
CY7CI68A-20VC

25

90

CY7CI68A-25PC
CY7C168A-250C
CY7CI68A-25LC
CY7CI68A-25VC
CY7C168A-250MB
CY7CI68A-25LMB

35

90

CY7CI68A-35PC
CY7C168A-350C
CY7CI68A-35LC
CY7CI68A-35VC
CY7C168A-350MB

45

70

CY7CI68A-35LMB
CY7CI68A-45PC
CY7C168A-450C
CY7CI68A-45LC
CY7CI68A-45VC
CY7C168A-450MB
CY7CI68A-45LMB

Package
Type

Operating
Range

Speed
(ns)

Icc

P5
06

Commercial

20

90

V5
P5

Commercial

25

rnA

90

06
L51
V5
06
L51
P5

Military
Commercial

35

90

06
L51
V5
06
L51
P5

Military
Commercial

40

06
L51
V5
06
L51

Military

2-157

70

Ordering Code
CY7CI 69A-20PC
CY7C169A-200C
CY7CI69A-20VC
CY7CI69A-25PC

Package
Type

Operating
Range

P5
06
V5

Commercial

P5

Commercial

CY7C169A-250C
CY7CI69A-25LC

06
L51

CY7CI69A-25VC
CY7C169A-250MB

V5
06

CY7CI69A-25LMB

L51

CY7CI69A-35PC
CY7C169A-350C

P5
06

CY7CI69A-35LC
CY7C169A-35VC

L51
V5

Military
Commercial

06

Military
Commercial

CY7C169A-400C

L51
P5
06

CY7CI69A-4OLC
CY7CI69A-4OVC

L51
V5

CY7CI69A-400MB
CY7CI69A-40LMB

06
L51

CY7C169A-350MB
CY7CI69A-35LMB
CY7CI69A-4OPC

Military

II

fin

CY7C168A
CY7C169A

• CYPRESS

~IOO~UaoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~====

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

loz

1,2,3

Icc

1,2,3

ISB1[12]

1,2,3

ISB2[12]

1,2,3

Note:
12. 7C168A only.

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACE

7,8,9,10,11

tRCS

7,8,9,10,11

tRCH

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAw

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

Document #: 38-00095

2-158

CY7C170

CYPRESS
SEMICONDUCTOR

4096 x 4 Static R/W RAM

Features

Functional Description

• CMOS for optimum
speed/power

The CY7Cl70 is a high performance
CMOS static RAM organized as 4096
words x 4 bits. Easy memory expansion
is provided by an active LOW chip sew
lect (CS), an active LOW output enable
(OE), and three·state drivers.

• High speed
- 25 os tAA
-IS os tACS
• Low active power
- 495 mW (commercial)
- 660 mW (military)
• TIL compatible inputs and
outputs
• Capable of withstanding
greater than 200lV
electrostatic discharge

Writing to the device is accomplished
when the chip select (CS) and write en·
able (WE) inputs are both LOW. Data
on the four input/output pins
(1/00 through 1/03) is written into the
memory location specified on the ad·
dress pins (Ao through Al1).

Reading the device is accomplished by
taking chip select (CS) and output enable (OE) LOW, while write enable
(WE) remains HIGH. Under these
conditions the contents of the memory
location specified on the address pins
will appear on the four data I/O pins.
The I/O pins stay in high impedance
state when chip select (CS) or output
enable (OE) is HIGH, or write enable
(WE) is LOW.
A die coat is used to insure alpha im·
munity.

• Output enable

Logic Block Diagram

Pin Configurations
DIP
A4

Vee

AS

A3

AS

A2

A7

AI

AS
Ag
A10

AO

Ne
1/°0

A11

1/°1

cs

1/°2

liE
1/°0

!o

1/°3

WE

GND

I/o,

A'
A2
A3
A4

0037-2

SOJ
1/°2

~

1/°3

CS
WE
lIE
0037-1

Figure I

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)

I
I

7C170·25

7C170·35

7CI70·45

25
90

35
90
120

45
90
120

Commercial
Military
2·159

fI

Maximum Ratings

.

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C

Static Discharge Voltage ..........•.......... >200IV
(per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latch-up Current. ......................... > 200 rnA

Supply Voltage to Ground Potential
(pin 22 to Pin ll) .................... -0.5Vto +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to + 7.0V

Ambient
Temperature
ozcs-

DATA VALID

'\ '\

·1

0037-7

Write Cycle No.1 (WE ControUed) (Notes 8, 12)

twc
ADDRESS

~~

-J
ISCS

\\ ~\\

/IIIIJ /111// / / /1
lAW

IHAtpwE

"A

.,

~\\'

tH~

Iso

*

DATA IN

~

DATA-IN VALID

'I

-IHZWE

==\J

!---ILZWE
I

HIGH IMPEDANCE •
DATA 110 _ _ _ _ _ _ _ _ _D_A_TA_UN_D_E_FI_N_ED
_ _ _ _ _ _ _ _-',~--...;;;.;;;.;.;.;;;;.;:;:;;;.;;:;:...---(\\"._ _ _ _ _ __

0037-8

Write Cycle No.2 (CS Controlled) (Notes 8, 12)
~--------------------------twc--------------------------~

___+=::::::~~::::::::~--~------- ..cs-·--------~I,------+_--------------~---------I~E------------~

tso--------.j.DATA-IN VALID
tHZWE--t

-------------;....---~
DATA 110

DATA

UNDEFINE~

HIGH IMPEDANCE
,)-----------------------

0037-9

Note: ICes goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

2-162

Ordering Information
Speed
(ns)

Ordering Code

25

CY7C170-25PC
CY7C170-250C
CY7C170-25VC

35

CY7C170-35PC

45

Package
Type

P9
010
Vl3
P9

CY7C170-350C
CY7C170-35VC
CY7C170-350MB

010
Vl3
010

CY7C170-45PC
CY7C170-450C

P9
010

CY7C170-45VC
CY7C170-450MB

010

Operating
Range
Commercial

Commercial

Military
Commercial

V13
Military

2-163

II

CY7C170
~PRESS
~~~camucroR================================================================
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

IOZ

1,2,3

ICC

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACS

7,8,9,10,11

tOOE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tscs

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpwE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

Document #: 38-00035-E

2-164

CY7C170A

CYPRESS
SEMICONDUCTOR

4096

Features

Functional Description

• CMOS for optimum
speed/power

The CY7Cl70A is a high performance
CMOS static RAM organized as 4096
words x 4 bits. Easy memory expansion
is provided by an active LOW chip select (CS), an active LOW output enable
(OE), and three-state drivers.

• High speed
- 20 ns tAA
-15 os tACS
• Low active power
- 495 mW (commercial)
- 660 mW (military)
• TIL compatible inputs and
outputs
• Capable of withstanding
greater than 2001V
electrostatic discharge

Writing to the device is accomplished
when the chip select (CS) and write enable (WE) inputs are both LOW. Data
on the four input/output pins
(1100 through 1103) is written into the
memory location specified on the address pins (All through All).

X

4 Static R/W RAM
Reading the device is accomplished by
taking chip select (CS) and output enable (OE) LOW, while write enable
(WE) remains HIGH. Under these
conditions the contents of the memory
location specified on the address pins
will appear on the four data 110 pins.
The I/O pins stay in hi~ impedance
state when chip select (CS) or output
enable (OE) is HIGH, or write enable
(WE) is LOW.
A die coat is used to insure alpha immunity.

• Output enable
• Vrn of 2.2V

Logic Block Diagram

Pin Configurations
DIP
A4

vcc

A5

A3

A6

A2

A7

Al

A8

AO
NC

Ag
A10

1/0 0

All

1/°1

cs
or

1/°0

1/°2
1/°3

WE

GNO

0149-2

1/°1

SOJ
1/°2

Vee

1/°3

cs

As

A3

A6

A2

A7

Al

Ao
NC
NC

As

WE
OE
0149-1

A10

1/°0

cs

1/°1
1/°2

OE

1/°3

WE

GNO

0149-3

Figure 1

Selection Guide
Maximum Access Time (ns)
Maximum Operating
I Commercial
Current (mA)
I Military

7C170A-20
20
90

2-165

7C170A-25
25
90
120

7C170A-35
35
90
120

7C170A-45
45
90
120

~
CY7C170A
""~~ocroR====================================================

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + ISO"C

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latch-up Current .......................... > 200 rnA

Supply Voltage to Ground Potential
(Pin 22 to Pin 11) .................... -O.SV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SVto +7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial
Military [4]

Output Current into Outputs (Low) ............. 20 rnA

Ambient
Temperature

Vee

O"C to + 70"C

5V ±1O%

+ 12SoC

- SsoC to

SV ±1O%

Electrical Characteristics Over Operating Range l3]
Parameters

Description

7C170A

Test Conditions

VOH

Output HIGH Voltage

Vee = Min.,IOH = -4.0rnA

VOL

Output LOW Voltage

Vee = Min., IOL = 8.0 rnA

VrH

Input HIGH Voltage

Units

Max.

Min.

2.4

V

2.2

0.4

V
V

VrL

Input LOW Voltage

-3.0

Vee
0.8

Irx

Input Load Current

GND"; VI"; Vee

-10

+10

/LA

Ioz

Output Leakage
Current

GND"; Vo"; Vee
Output Disabled

-10

+10

/LA

los

Output Short[t]
Circuit Current

Vee = Max., VOUT = GND

-3S0

rnA

ICC

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

I
I

Commercial

90

Military'

120

V

mA

• -25, -35 and -45 only

Capacitance [2]
Test Conditions

Max.

TA = 2soC,f= 1 MHz
Vee = S.OV

4

Description

Parameters
CrN

Input Capacitance

CoUT

Output Capacitance

Units
pF

7

Notes:
1. Not more than I output should be shorted at one time. Duration of

3. See the last page of this specification for Group A subgroup testing
information.
4. T A is the "instant on" case temperature.

the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

AC Test Loads and Waveforms
OUTPUT

5v
OUTPUT

O----r-------t

I
_
-

30 pF

3.0 V -------.z.~---_i.

0-------........""........,

o--__

R2

INCLUDING
JIGAND _
SCOPE
-

ALL INPUT PULSES

R14811!

Rl481!!
5V~------~~--,

255S!

I

--~

5 pF

R2

INCLUDING
_JIG AND
_
- SCOPE
-

25511

-"- 5 ns

5ns

0149-6
0149-4

Equivalent to:

THEVENIN EQUIVALENT
167!!
OUTPUT O--~"~Vl\o.---O 1.73 V

~

Figure 2

Figure Ib

Figure la

GND

0149-5

2-166

~

.
CY7C170A
~~~UcroR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Switching Characteristics Over Operating Range[3, 5)
Parameters

7C170A-20

Description

Min.

Max.

7C170A-25
Min.

Max.

7C170A-35
Min.

Max.

7C170A-4S
Min.

Units

Max.

READ CYCLE
tRC

20

Read Cycle Time

25
20

tAA

Address to Data Valid

toHA

Data Hold from Address Change

25

5

5

tACS

CS Low to Data Valid

15

tDOE

OE LOW to Data Valid

10

tLZOE

OE LOW to Low Z

tHZOE

OE HIGH to High Z[6]

tLZCS

CS LOW to Low Z[7]

tHZCS

CE HIGH to High Z[6, 71

35
5

15
12

3

3
8

3

5
8·

45

5

30

ns

20

ns

15

ns

ns

5
15

ns
ns

3
12

10

ns

5

25
15

10

5

45

35

ns

15

ns

WRITE CYCLE[S]
twc

Write Cycle Time

20

20

25

40

ns

tscs

CS LOW to Write End

15

20

25

30

ns

tAW

Address Set-up to Write End

tHA

Address Hold from Write End

15
0

20
0

25
0

30
0

ns

tSA

Address Set-up to Write Start

0

0

0

0

ns

tpwE

WE Pulse Width

15

15

20

20

ns

tSD

Data Set-up to Write End

10

10

15

15

ns

0

0

tHD

Data Hold from Write End

tHZWE

WE LOW to High Z

tLZWE

WE HIGH to Low Z

7

5

5

Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IorJloH and 30 pF load capacitance.
6. tHWE, tHZCS and tHZWE are tested with Cr. = 5 pF as in Figure 1h.
Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCS is less than
tLZCS for all devices. These parameters are sampled and not 100%
tested.

0

0

5

ns

15

10

7

ns

5

ns
ns

8. The internal write time of the memory is defined by the overlap of
CS LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The

9.
10.

11.
12.

data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL and OR = VIL.
Address valid prior to or coincident with CS transition LOW.
Data VO will be high impedance ifOE = VIH'

Switching Waveforms
Read Cycle No.1 (Notes 9, 10)

~t:~~-------------------------tRC--------------------------~:1.
ADDRESS
DATA OUT

_---t
___I_:~~~~~~to~_H-A~~~~_tA-_A-;:::::j-,
-----,-"~~~~~~~~~~~~~~~~~~~~~~~_*_~~~~~~========~
PREVIOUS DATA VALID

~

DATA VALID

0149-7

2-167

fI

Switching Waveforms (Continued)
Read Cycle No. 2 (Notes 9, 11)
IRe

J.

-j

t..cs

I

~

'I,

tDOE

IH%OE-----

!--lHzcs--

I---ILZOE~
HIGH IMPEDANCE
DATA OUT

lues

HIGH
IMPEDANCE

'

DATA VALID

'\

·1

0149-8

Write Cycle No.1 ----

O2

I---IH-D---

03

Cf

°2
03

GND

WE
0051-2

As

--""--CE

At
NC
NC

-"",,"~,

A,o
Al1
13

_...r--r- WE
I

4 3 2 !!J282726
25
24
23
22
2'
20
'9
'2'3'415161718

5
6
7
8
9
10

"

.!ilt:

~I~

Ot')ON

A,

Ao
10
NC
NC
I,

00

O

0051-3

0051-1

Selection Guide
7C171·25
7Cl72·25
Maximum Access Time (ns)
Maximum Operating
Current (mA)

I

STD

I
J

Commercial
Military

2-l7l

7C171·35
7Cl72·35

7C171·45
7Cl72-45

25

35

45

90

90

70

90

70

fin
.

CY7Cl71
CY7Cl72

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... > 200 1V
(Per MIL-STD-883 Method 3015)

Storage Temperature ............... - 65°C to + 150°C
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latch-up Current .......................... > 200 mA

Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V

Range

DClnputVoltage ................... -3.0Vto +7.0V

Commercial
Military[2]

Output Current into Outputs (Low) ............. 20 mA

Ambient
Temperature

Vee

OOCto +700C

5V ±10%

- 55°C to + 125°C

5V ±10%

Electrical Characteristics Over Operating Range[3)
Description

Parameters

7C171-25
7Cl72-25

Test Conditions

Min.

VOH

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee

VIH

Input HIGH Voltage

= Min.,IOH = -4.0 mA
= Min., IOL = 8.0 rnA

7C171-35
7C172-35

Max.

2.4

Min.

7C171-45
7Cl72-45

Max.

Min.

2.4
0.4

2.4

V

2.2

2.2

V

-3.0

0.8

-3.0

0.8

-3.0

0.8

V

-10

+10

-10

+10

-10

+10

/LA

-50

+50

-50

+50

-50

+50

/LA

-350

mA

VIL

Input LOW Voltage

IIX

Input Load Current

GND S VI

loz

Output Leakage Current

GND S Va ~ Vee,
Output Disabled

los

Output Short Circuit
Current[t]

Vee

ICC

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

Commercial

90

90

70

Military

90

90

70

Automatic CE
Power Down Current

Max. Vee,
CE;:: VIH

Commercial

20

20

15

ISBI

Military

40

20

20

Automatic CE
Power Down Current

Max. Vee,

Commercial

15

15

15

ISB2

c:E ;:: Vee -0.3V

Military

20

20

20

~

Vee

V

0.4

0.4

2.2

Units

Max.

= Max., VOUT = GND

-350

-350

rnA
rnA
rnA

Capacitance [4]
Parameters

Test Conditions

Max.

Units

= 25°C, f = 1 MHz, Vee = 5.0V
TA = 25°C, f = I MHz, Vee = 5.0V

4

pF

7

pF

Description

CIN

Input Capacitance

CoUT

Output Capacitance

TA

Notes:
I. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. TA is the "instant on" case temperature.

3. See the last page of this specification for Group A subgroup testing
information.
4. Tested iuitially and after any design or process changes that may
affect these parameters.

AC Test Loads and Waveforms
Rl 481!!

Rl 481!!

5Vo-------~~~

5V

o----------

'3

As

1.0

A9

10

A,a

"0 0

Al1
°0

0,
'2

I---H-D-----

0,

I---HH :::-----

02

I---HH ::-----

°3

CE

°2
03

GND

WE
014B-2

.t:t./!",,-->'d.:!2001V
(Per MIL-STD-883 Method 301S)
Latch-up Current. ......................... > 200 rnA

Operating Range
Range

Ambient
Temperature

Commercial
Military [2]

O"C to + 70"C
- 55°C to + 125°C

Vee
5V ±1O%
5V ±1O%

Electrical Characteristics Over Operating Range[3]
Description

Parameters
VOH

Output HIGH Voltage Vee

=

Min.,IOH

=

-4.0rnA

VOL
VIH

Output LOW Voltage Vee
Input HIGH Voltage

=

Min., IOL

=

8.0 rnA

VIL
IIX

Input LOW Voltage
Input Load Current

loz

Output Leakage
Current

GND:S: VI:S: Vee
GND :s: Vo :s: Vee,
Output Disabled

los

Output Short Circuit
CurrentU]

Vee

Icc

Vee Operating
Supply Current

=

Max., VOUT

=

-350

-350

-350

Commercial
Military

80

70
80

70
70

70

Commercial
Military

40

20

20

20

20

20

20

Commercial

20

20

20

20

20

20

20

GND

Max. Vee,
Automatic CE
CE:2: Vee -0.3V
Power Down Current VIN:2: Vee -0.3Vor
VIN:S: 0.3V

ISB2

V
0.4
0.4
0.4
0.4
2.2
2.2
2.2
V
2.2
-3.0 0.8 -3.0 0.8 -3.0 0.8 -3.0 0.8
V
-10 +10 -10 +10 -10 +10 -10 +10 p,A
-10 +10 -10 +10 -10 +10 -10 +10 p,A

Vee = Max.
lOUT = OmA
Automatic CE
Max. Vee, CE:2: VIH
Power Down Current Min. Duty Cycle = 100%

ISBI

7C171A-20 7C171A-25 7C171A-35 7CI71A-45
7CI72A-20 7CI72A-25 7CI72A-35 7CI72A-45 Units
Min. Max. Min. Max. Min. Max. Min. Max.
2.4
2.4
V
2.4
2.4

Test Conditions

-350 rnA
50

rnA

rnA

rnA
Military

Capacitance [4]
Parameters

Description
Input Capacitance
Output Capacitance

CIN
COUT

TA
TA

Test Conditions
25°C, f = I MHz, Vee
25°C, f = 1 MHz, Vee

=
=

Notes:
I. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. TA is the "instant on" case temperature.

=
=

5.0V
S.OV

Max.
5

Units
pF

7

pF

3. See the last page of this specification for Group A subgroup testing
information.
4. Tested initially and after any design or process changes that may
affect these parameters.

AC Test Loads and Waveforms
Rl481!!

5v

R1481!!

o----J\l"'I'Y--.

OUTPUT O---p-----t

I
_
-

30 pF
INCLUDING
JIGAND _
SCOPE
-

OUTPUT

O---------....,..V,...---O
167!!

OUTPUT

3.0V-----~.....---~

5Vo----~~~

1.73 V

0148-5

2-179

R2
255!!

,,6 ns

-" 5 ns
0148-6

0148-4

Figure 2

-=-

r.

&n~~============================================================~
CY7C171A
CY7Cl72A

.

Switching Characteristics Over Operating Range[3, 5]
Parameters

Description

7C171A·20
7Cl72A·20

Min.

Max.

7C171A·25
7Cl72A·25

Min.

Max.

7C171A·35
7Cl72A·35

Min.

Max.

7C171A·45
7Cl72A·45

Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

tOHA

Output Hold from Address Change

tACE
tLZCE

eE LOW to Data Valid
eE LOW to Low Z[7]

tHZCE

CE HIGH to High Z[6, 7]

tpu

0

tpD

eE LOW to Power Up
eE HIGH to Power Down

tRCS

Read Command Set·up

0

0

0

0

ns

tRCH

Read Command Hold

0

0

0

0

ns

20

35

25
20

5

25
5

20

5
25

5

5

8
20

5

5
15

20

ns
ns

15
0

ns
ns

25

20

ns
ns

45
5

0

0

45

35

10

ns

45
35

ns

WRITE CYCLErS]
twc

Write Cycle Time

20

20

25

40

ns

tSCE

CE LOW to Write End

15

20

25

30

ns

tAW

Address Set-up to Write End

15

20

25

30

ns

tHA

Address Hold from Write End

0

0

0

0

ns

tSA

Address Set·up to Write Start

0

0

0

0

ns

tpWE

WE Pulse Width

15

15

20

20

ns

tSD

Data Set-up to Write End

10

10

15

15

ns

tHD

Data Hold from Write End

0

0

0

0

ns

tLzwE

WE HIGH to Low Z[7] (7CI72)

5

5

5

5

ns

tHZWE

WE LOW to High Z[6, 7] (7CI72)

7

7

10

15

ns

tAWE

WE LOW to Data Valid (7CI71)

20

25

30

35

ns

tADv

Data Valid to Output Valid (7CI71)

20

25

30

35

ns

Notes:

5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of I.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IorJIOH and 30 pF load capacitance.
6. tHZCE and tHZWE are tested with CL = 5 pF as in Figure 1h. Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZ is less than tLZ
for any given device.

8. The internal write time of the memory is defined by tbe overlap of
CE LOW and WE LOW. Botb signals must be low to initiate a write
and either signal can terminate a write by going high. The data input
setup and hold timing should be referenced to tbe rising edge of tbe
signal that terminates the write.
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = VIL.
II. Address valid prior to or coincident witb CE transition LOW.

Switching Waveforms
Read Cycle No.1 (Notes 9, 10)

-,. ~"':~~~~~-t-O~H-A---------tA~A~-.--'--:------:-----'-":-,---------------------------------------------:-=*~-------DATA OUT

PREVIOUS DATA VALID

DATA VALID
0148-7

2·180

fjn
.

CY7C171A
CY7C172A

~~=============================================================

Switching Waveforms (Continued)
Read Cycle (Notes 9, 11)

fJI

'Re

~r-

-'HZ-

'-

'LZ::!

HIGH IMPEDANCE

DATA OUT

II

I

I

I

I

"""""

!--tpu_

HIGH
IMPEDANCE

DATA VALID

~tPD-=1
ICC

Vee

50%

} ' - 50%

SUPPLY
CURRENT

IS8

..J

-

i--tReH--o

i--tRes

0148-8

Write Cycle No.1 (WE Controlled) (Note 8)
twc
ADDRESS

t
tsCE

\\

'(-1111 II I I I I I I II

.\\~

t HA .-.

tAW

tsA

I - - - - tPWE -

~\\
tsD

I

I

DATA IN

/HD

DATA-IN VALID

I-tHZW~
DATA OUT
(7CI72A)

DATA UNDEFINED

DATA OUT
(7CI71A)

DATA UNDEFINED

•

j--tUWE
HIGH IMPEDANCE

I+- tADY

::1.
DATA VALID
J ___
__
0148-9

Write Cycle No.2 (CE Controlled) (Note 8)
twc
ADDRESS

-

tsA

tsCE-

~
tHA ......

tAW
I----tPWE -

\\ ,\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \

.t:

•

DATA IN
DATA OUT
(7C172A)

'I I I I I I I I I I I II
~tsD

tHD

DATA-IN VALID

I--tHZWE~

DATA UNDEFINED

•

HIGH IMPEDANCE

DA~OUT-------------DA-T-A-U-N-DE-F-IN-ED----------------::1~--DA-T-A-V-AL-ID-------=:::J('--...;;;~.;.;.;;;;;.._ __
- tAWE

(7C171 A)

0148-10

Note: If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7CI72A).

2-181

~

CY7C171A

'Wr~ ====================CY=7C=1=7=2;;;;::A
Typical DC and AC Characteristics
NORMA~SUPPLYCURRENT
TS. SUPPLY VOLTAGE

f .

1.4
1.2

J

1.0

Q

0.8

N
~

0.6

leV

~
II:

i

1.2

./

..

'N
~

~
II:
0
z

0.2

0.8

4.S

0.6

CJ

VOLTAG~

;:)

0.4

6.0

;:)

AMBIENT

z

.

1.2

............

1.0

,

~
II:

1.0

Q

-

0

z
0.8

0.8
4.0

S,o

4.5

"

TYPICAL POWER-ON CURRENT
VB. SUPPLY VOLTAGE

«

30.0

2.5

26.0

2.0
1.5

II:

!

20.0

«~

IS.0

:;

:E

i

1.0
0.5
0.0
0.0

2.0

-

3.0

6.0

0.0
4.0

SUPPLY VOLTAGE (VI

.
II:
II:

.

;:)

/

80

I

CJ

z

&0

....

40

iii

Vee ·S.OV

~

;:)

0

126

26

20

/
V

0
0.0

/

5.0

V
Vee -S.OV
TA = 25'C

/

/
1.0

2.0

4.0

3.0

OUTPUT VOLTAGE (VI

NORM~Icc
VI.

1.1

---

CYCLE TIME

r'---"T'"--""'--"""
Vee· 5.0 V
TA ·25"C

V,N ·0.& V

/
/

:!l10.0

/

V

1.0

120
100

TYPICAL ACCESS TIME CHANGE
VB. OUTPUT LOADING

3.0

Q

N
~

/

C

oS
....z

AMBIENT TEMPERATURE ('CI

SUPPLY VOLTAGE (VI

.

OUTPUT SINK CURRENT
TS. OUTPUT VOLTAGE

/

0.6
-55

6.0

5.5

4.0

3.0

OUTPUT VOLTAGE IVI

./

~

r--.

'" "

140

N

TA -25'C

Vee -S.OV
TA = 2S'C

2.0

1.0

('CI

NORMALIZED ACCESS TIME
VB. AMBIENT TEMPERATURE

$

0.9

j

TEMPERATUR~

1.4

1.1

20

0.0

12S.0

2S.0

C'

1.2

40

o

(VI

1.3

«

......

Vee -S.OV
V,N =6.0V

-S6

1.4

:E
II:
0

51
!5

1.6

c

" """

60

II:

0
S.S

5.0

80

CJ

NORMALIZED ACCESS TIME
VOLTAGE

N
~

II:
II:

100

;:)

TS. SUPPLY

$

..
..

~

0.0
SUPPLY

.'"

oS
....z

0.2

IS8

0.0
4.0

c

Q

0.4

OUTPUT SOURCE CURRENT
VI OUTPUT VOLTAGE
120

~

1.0

J
]

.. / ' /
li

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VB.

V

/

o

200

TA -26'C
Vee -4.&OV

400

&00

CAPACITANCE (pFI

800

1000
CYCLE FREQUENCY (MHz)

0148-11

2-182

&l
.

CY7C171A
CY7Cl72A

~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Ordering Information
Speed
(ns)
20

25

35

45

Package
Type

Operating
Range

Speed
(n5)

CY7CI7IA-20PC

P13

Commercial

20

CY7C171A-200C

014

CY7CI71A-20LC

L64

CY7CI72A-20LC

L64

CY7C171A-20VC

V13

CY7CI72A-20VC

Vl3

Ordering Code

Commercial

25

Package
Type

Operating
Range

CY7CI 72A-20PC

P13

Commercial

CY7CI72A-200C

014

Ordering Code

CY7CI71A-25PC

P13

CY7CI72A-25PC

P13

CY7C171A-250C

014

CY7CI72A-250C

014

CY7CI71A-25LC

L64

CY7CI72A-25LC

L64

CY7CI71A-25VC

Vl3

CY7CI72A-25VC

V13

CY7CI7IA-250MB

014

CY7CI72A-250MB

014

CY7CI71A-25LMB

L64

CY7CI72A-25LMB

L64

CY7CI71A-35PC

Pl3

CY7C171A-350C

Military

CY7CI72A-35PC

P13

014

CY7CI72A-350C

014

CY7CI7IA-35LC

L64

CY7CI72A-35LC

L64

CY7CI71A-35VC

V13

CY7CI72A-35VC

V13

CY7C171A-350MB

014

CY7CI7IA-35LMB

L64

CY7CI7IA-45PC

Pl3

CY7C171A-450C
CY7CI7IA-45LC

Commercial

35

Military

CY7CI72A-350MB

014

CY7CI72A-35LMB

L64

CY7CI72A-45PC

P13

014

CY7CI72A-450C

014

L64

CY7CI72A-45LC

L64

CY7CI7IA-45VC

Vl3

CY7CI72A-45VC

V13

CY7CI7IA-450MB

014

CY7CI72A-450MB

014

CY7CI71A-45LMB

L64

CY7CI72A-45LMB

L64

Commercial

45

Military

2-183

Commercial

Military
Commercial

Military
Commercial

Military

II

5A

CY7C171A
CY7Cl72A

• CYPRESS

,
~oo~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MILITARY SPECIFICATIONS
Group A Subgroup Testing

DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

ISB!

1,2,3

ISB2

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACE

7,8,9,10,11

tRes

7,8,9,10,11

tRCH

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpWE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

t AWE I12]

7,8,9,10,11

tADV I12]

7,8,9,10,11

Note:
!2. 7CI71A only.

Document #: 38-00104

2-184

PRELIMINAR Y

CYPRESS
SEMICONDUCTOR

2

4096

X

X

CY7C183
CY7C184

16 Cache RAM

Features
They are designed specifically for use
with the Intel 82385 Cache Controller,
and their addresses are latched on the
falling edge of the Address Latch Enable (ALE) signal. When ALE is
HIGH, the latch is transparent. The
CY7C183 has all address bits latched
by the ALE signal except A12, which is
unlatched. A12, which bypasses the
latch, has a faster access time. All address bits are latched by the ALE signal in the CY7C184. The mode pin
controls whether they are configured as
direct mapped 8K x 16 or two-way set
associative 2 x 4K x 16 RAMs. When
mode is HIGH, the circuits are placed
in the two-way mode. In the two-way
mode, the upper address bit, A12 is a
"don't care", and is externally wired to
ground. When mode is LOW, the circuits are placed in the direct mode.
Writing is accomplished, in the twoway mode, by taking CE LOW and by
inserting the respective CSx and WEx
signals LOW. CSo enables bits Do-D7
while CS, enables bits Ds-D'5. WEA

• Pin programmable into direct
mapped or two-way set
associative format
• CMOS for optimum speed/
power
• High speed-25 ns
• Common I/O
• Internal address latch
• TTL compatible inputs and
outputs
• Capable of withstanding greater
than 2001 V electrostatic
discharge
• Compatible with Intel 82385
Cache Controller

Functional Description
The CY7C183 and CY7C184 are high
performance monolithic CMOS static
RAMs which contain 128K bits organized into either two, two-way set associative blocks of 4K x 16 RAM, or one
directly mapped 8K x 16-bit RAM.

enables cache bank A, and WEB enables cache bank B to receive whatever
data resides on the data bus. OEA and
OEB similarly enable cache banks A
and B, respectively, to drive the data
bus.
Writing is accomplished, in the direct
mode, by tying WEA and WEB together externally, and using A12 to determine which 4K x 16 memory bank is
selected.
Reading is accomplished, in the twoway mode, by taking CE LOW, inserting the respective OEx and CSx signals LOW, and the respective WEx
signal HIGH. The contents of the
memory location specified on the address pins will appear on the 16 outputs. Activation ofOEA and OEB
simultaneously will cause both banks
to be deselected. Reading is accomplished, in the direct mode, by tying
OEA and OEB together externally. A12
will determine which 4K x 16 memory
bank is enabled.

Logic Block Diagrams
Two-Way Set Associative (Mode

=

HIGH)

Direct Map (Mode

0[,-----1
WE,-----I

-

.....----1M~~XO~y
Array

=

LOW)
M~':nxo~y
Array

AO

ALE

0[,-----\
WEe-----I
Way B

0145-2
0145-1

Selection Guide
Maximum Address
Access Time (ns)

Commercial

Maximum Output Enable
Access Time (ns)

Commercial

Maximum Operating
Current (rnA)

Commercial

7C183-25
7C184-25

7C183-35
7C184-35

7C183-45
7C184-45

25

35

45

35

45

Military
10

Military
220

Military

2-185

14

16

14

16

170

140

200

160

fin~~=============================================================
.

.

PRELIMINARY

CY7C183
CY7C184

Maximum Ratings

(AlJove which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............•.. - 6SoC to + ISO"C
Static Discharge Voltage ....•..........•..... > 2001 V
(per MIL-STD-883 Method 301S)
Ambient Temperature with
Power Applied ..•............•.... - SsoC to + 12SoC

Latch-up Current ....................•..... > 200mA

Supply Voltage to Ground Potential .... -O.SV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to + 7.0V

Ambient
Temperature

Range

DC Input Voltage ................... -3.0V to +7.0V

O"C to + 70"C

5V ±1O%

- SsoC to + 125°C

SV ±1O%

Commercial

Output Current into Outputs (LOW) ..•..•...... 20 mA

Military

Vee

Electrical Characteristics Over Operating Range
Parameters

Description

7C183·25
7C184-25

Test Conditions

Min.

7C183·35
7C184-35

Max.

Min.

Max.

7C183-45
7C184-45
Min.

Units

Max.

VOH

Output HIGH Voltage Vee = Min., IOH = -1.0 mA

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

2.2

Vee

2.2

Vee

2.2

VIL

Input LOW Voltage

-3.0

0.8

-3.0

0.8

-3.0

0.8

V

IIX

Input Load Current

GND

-10

+10

-10

+10

-10

+10

fJ.A

Ioz

Output Leakage
Current

GND
Output Disabled

-10

+10

-10

+10

-10

+10

fJ.A

los

Output Short Circuit
Currentt1l

Vee = Max.,
VOUT = GND

mA

Icc

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA
Duty Cycle = 45%
Single Way Write

2.4

Vee = Min., IOL = 4.0 mA

2.4

< VI < Vee
< Vo < Vee,

Commercial

2.4
0.4

0.4

V
0.4

V

Vee

V

-350

-350

-350

220

170

140

200

160

mA
Military

Capacitance [2]
Description

Parameters
CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions

Max.

TA = 2SoC, f = 1 MHz
Vee = 5.0V[3]

5

Notes:
I. Not more than I output.should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.
3. TA is the "inst.ant on" case temperature.

AC Test Loads and Waveforms

5VFl

INCLUDING
JIG AND
SCOPE

I

100 f

-=

-=

INCLUDING
JIG AND
SCOPE
0145-3

Figure la
Equivalent to:

reference levels of I.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOI/IOH aod 100 pF load capacit.ance.

I

5 f

P

-=

GND
~3no

R2

66m

0145-5

0145-4

Figure Ib

400.0.

o----¥tIIt---O

v -----::Ir:::::---""1

Figure 2. All Input Pulses

THE-VENIN EQUIVALENT
OUTPUT

3.0

OUTPUT

R2
667n.

P

information.

5. Test conditions assume signal transition times of 3 ns or less, timing

Rl 1000n.

OUTPUT

pF

8

4. See the last page of this specification for Group A subgroup testing

5Vf.1

Rl 1000n.

Units

2.00V
0145-6

2-186

fin
.

CY7C183
CY7C184

PRELIMINARY

~~R==============================================================~

Switching Characteristics Over Operating Range [4. 5)
Parameters

7C183-25
7Cl84-25

Description

Min.

7C183-45
7C184-45

7C183-35
7C184-35

Max.

Min.

Max.

Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

25
25

35
35

45
45

ns

tAA A I2[!2]

Address to Data Valid Al2

17

25

35

ns

teE

Chip Enable to Data Valid

12

15

20

ns

tcs

Chip Select to Data Valid

12

15

20

ns

10

14

16

ns

ns

toE

Output Enable to Data Valid

toH

Output Hold from Address Change

3

3

3

ns

tLZCE

Chip Enable to Low Z[7)

3

3

3

ns

tLZOE

Output Enable to Low Z[7. 8)

0

tHZCE

Chip Enable to High Z

15

25

30

ns

tHZOE

Output Enable to High Z

9

10

12

ns

tpALE

ALE Pulse Width

8

10

12

ns

tSALE

Address Set-up to ALE Low

4

6

8

ns

tHALE

Address Hold from ALE Low

4

4

4

ns

0

0

ns

WRITE CYCLE[S)
Write Cycle Time

25

35

45

ns

tAW

Address Set-up to Write End

tSCE

Chip Enable to Write End

20

30

40

ns

20

25

30

tscs

ns

Chip Select to Write End

20

25

30

ns

tSD

Data Set-up to Write End

10

10

10

ns

tHD

Data Hold from Write End

0

0

0

ns

tPWE

Write Enable Pulse Width

20

25

30

ns

tSA

Address Set-up to Write Enable

0

0

0

ns

tHA

Address Hold from Write Enable

2

2

2

ns

tLZWE

Write Enable HIGH to Low Z(7)

3

tHZWE

Write Enable LOW to High Z[7. 8)

twc

3

ns

3

15

15

20

ns

tpALE

ALE Pulse Width

8

10

12

ns

tSALE

Address ICE Set-up to ALE Low

4

6

8

ns

tHALE

Address ICE Hold from ALE Low

4

4

4

ns

Notes:
6. tHZCE and tLZCE are specified with CL = 5 pF as in Figure 1h.
Transition is measured ± SOO mV from steady state voltage.

8. Both WEA and WEB must be HIGH for read cycle.
9. Device is continuously selected. CE and CS are LOW.
10. Address valid prior to or coincident with CE transition LOW.
11. OR is selected (LOW).
12. CY7Cl83 only.

7. The internal write time of the memory is defined by the overlap of CE.
CSx. and WEx. All signals must be LOW to initiate a write and any
signal can terminate a write by going HIGH. The data input set-up
and hold timing should be referenced to the rising edge of the signal
that terminates the write.

2-187

5n
.

CY7C183
PRELIMINARY
CY7C184
~~u~~~~~~~~~~~~~~~~~~~~~~~==~~~==========~

Switching Waveforms
Read Cycle No. 1[9,10,121

ALE

-----~tpALE

--::::\~::::=====t=~===~/___
~"'~-:J:
'00 ''''-'

ADDRESS

it

~tM--'t~M---A-12-----------------------------

-------------

tOHA
DATA ____~P~R~EV~IO~U~S~D=A~T~A~V~A~L1~D____~~~~'_________~D~A~T~A~V~A~L1~D_________
0145-7

Read Cycle No. 2[9, 10, 121
t Rc
ALE

ADDRESS AI2

(7C183)
ADDRESS
AO - Al1 (7C183)
AO-A I2 (7CI84)

\.
1

tpALE
tSALE
.CtM-AI2-

-I

f
tHALE

)(

)(

'I

tM

I---tOHA~
DATA

PREVIOUS DATA VALID

IXXX

DATA VALID
0145-8

Read Cycle No. 3[91

ALE

ADDRESS

--------J-;---~EtPALE;-4l..tR-C--------t-H-AL-E----------J-. r

_
..J _

-----tl!...:====:t.":-::===:::i---------t-

0145-9

2-188

&n

CY7C183
CY7C184

PRELIMINAR Y

• CYPRFSS

~~~===========================================================

Switching Waveforms (Continued)
Write Cycle No.1 (WE Controlled)

ALE

fI

-----J~I4--tPALE---li\.----------...Jr
.
.
tSALE

tHALE

twc

1-

ADDRESS

1-

tAW
tSCE,tSCS

XXXXXX

X'X.XXlt

~x

tpWE

I----tSA

x

tHA

WE

~

.... tHzwEI-'
DATA I/O

f--(

DATA OUT VALID

I--t LZWE !-tH~

)l(OATA IN VALI0lC::)--

_______________;r=_______________________ ,t

~

tso

HZOE

_

t
~,--L_ZO_E
_ _ _ __
0145-10

Write Cycle No.1 (CE, CS Controlled)

ALE

-----J~.j4---tPALE--_Ii\.----------...Jr
.
.
SALE

ADDRESS

tAW
WE

tpWE

XXXXXX) IXXXX)(1t
I----tSA

CE,CS

tHALE

twc

1XXXXXX.X)( IXXXX
.1

tHA

tscE,tscS

\.
tSD

!-tHD

DATA IN VALID

DATA I/O

0145-11

2-189

&n
.

CY7C183
CY7C184

PRELIMINAR Y

~aoR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=
Pin Configurations
Vee

AO

A12

VSS

CE

VSS

VSS

1/°4
1/°5
1/°6
1/°7
NC

6 5 4

"",tn ...
fQ

3

>8 ~

VSS

I/O,
1/°2
1/°3

_

~~~~~

2 111484746454443

VSS

1/°5

1/°10

1/°6

I/Og
I/Os

Vee

Vee

Cso

Vee

WEa

MODE

WEA

Cs 1
OEa
OEA

A12

Ao

CE

VSS

VSS

40

VSS

1/°0

39

1/°'5
1/°14

I/O,
7C183
7C184
LCC

1/°2
1/°3

38
37
36

VSS

35

VSS

34

1/°'1

33
32

1/°'0

31

1/°8

1/°5
1/°6
1/°7

16
17
18

0145-13

1/°13
1/°12

1/°4

1/°12

I/O"

42
41

'-'

1/°'5
1/°14
1/°13

1/°4

VSS

A,

CE

VSS

1/°7
0145-12

""",It)

VSS

1/°0

lo1f 1"'< III III 1.3- lo1f IY! I:!l >8 >8
>8 >81~
<.> ~ ~ > > 0 0 - 0
:::E

..r <

A12

VSS

NC

Ala
A11

AI
Ao

1/°11
1/°10

I/Og
I/Os

o

As
Ag

A2

1/°15
1/°14
1/°13
1/°12

7C183
7C,84
PLCC

A7

As
A4
A3

VSS

1/°0
1/°1
1/°2
1/°3

ALE

A6

I/Og

19 20 21 22 23 24 25 26 27 28 29 30

8°111 <"''''<111-''' 88
'" >"'I'"0 I'"0 I~ c~ > >
> I~ I'"
~ I'"
~ >
0145-14

2-190

Truth Tables
Two·Way Mode (MODE = HIGH)
Operation

CE

cSo

CSt

OEA

OEB

WEA

WEB

H

X

X

X

X

X

X

Outputs Hi-Z, Write Disabled

L

H

H

X

X

X

X

Outputs Hi-Z, Write Disabled

X

X

X

H

H

X

X

Outputs Hi-Z

X

X

X

L

L

X

X

Outputs Hi-Z

L

L

H

L

H

H

H

Read 1/00-1/07

L

L

H

H

L

H

H

Read 1/00-1/07

WayB

L

H

L

L

H

H

H

Read 1/08-1/015

Way A

L

H

L

H

L

H

H

Read 1/08-1/015

WayB

L

L

L

L

H

H

H

Read 1/00-1/015

Way A

Way A

L

L

L

H

L

H

H

Read 1/00-1/015

WayB

L

L

H

X

X

L

H

Write 1/00-1/07

Way A

L

L

H

X

X

H

L

Write 1/00-1/07

WayB

L

H.

L

X

X

L

H

Write 1/08-1/015

Way A

L

H

L

X

X

H

L

Write 1/08-1/°15

WayB

L

L

L

X

X

L

H

Write 1/00-1/015

Way A
WayB

L

L

L

X

X

H

L

Write 1/00-1/015

L

L

H

X

X

L

L

Write 1/00-1/°7

Way A&B

L

H

L

X

X

L

L

Write 1/08-1/015

Way A&B

L

L

L

X

X

L

L

Write 1/00-1/015

Way A&B

Direct Mode (MODE = LOW)
CE

CSo

CSt

OEA

OEB

WEA

WEB

Operation

H

X

X

X

X

X

X

Outputs Hi-Z, Write Disabled

L

H

H

X

X

X

X

Outputs Hi-Z, Write Disabled

X

X

X

H

H

X

X

Outputs Hi-Z

L

L

H

L

L

H

H

Read 1/00-1/07

L

H

L

L

L

H

H

Read 1/08-1/015

L

L

L

L

L

H

H

Read 1/00-1/015

L

L

H

X

X

L

L

Write 1/°0-1/°7

L

H

L

X

X

L

L

Write 1/08-1/015

L

L

L

X

X

L

L

Write 1/00-1/015

Ordering Information
Speed
(ns)
25
35

45

Package
Type

Operating
Range

Speed
(ns)

CY7C183-25DC

D26

Commercial

25

CY7C183-25JC

J69

CY7C183-35DC

D26

CY7C183-35JC

J69

CY7C183-35DMB

D26

CY7C183-35LMB

L68

CY7C183-45DC

D26

CY7C183·45JC

J69

CY7C183-45DMB

D26

CY7C183-45LMB

L68

Ordering Code

35
Military
45

Commercial
Military

2-191

Package
Type

Operating
Range

CY7C184-25DC

D26

Commercial

CY7C184-25JC

J69

CY7C184-35DC

D26

Ordering Code

CY7C184-35JC

J69

CY7C184-35DMB

D26

CY7C184-35LMB

L68

CY7C184·45DC

D26

CY7C184-45JC

J69

CY7C184-45DMB

D26

CY7C 184-45LMB

L68

Military
Comme~cial

Military

I

&Ii

PRELIMINAR Y

. CYPRESS

CY7C183
CY7C184

~~R========================================================

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

lIx
loz
los

1,2,3

Icc

1,2,3

1,2,3
1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

toHA

7,8,9,10,11

tACE

7,8,9,10,11

toE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

Document #: 38-00090

2-192

ADVANCED INFORMATION

CYPRESS
SEMICONDUCTOR

8192 x 8 Static RAM

Features

Functional Description

• Automatic power-down when
deselected

The CY7C185 and CY7C186 are high
performance CMOS static RAMs organized as 8192 words by 8 bits. These
RAMs are developed by Aspen Semiconductor Corporation, a subsidiary of
Cypress Semiconductor. Easy memory
expansion is provided by an active
LOW chip enable (CEI), an active
HIGH chip enable (CE2), and active
LOW output enable (OE) and threestate drivers. Both devices have an automatic power-down feature (CEI), reducing the power consumption by 75%
when deselected. The CY7C185 is in
the space saving 300 mil wide DIP
package and leadless chip carrier. The
CY7C186 is in the standard 600 mil
wide package.
An active LOW write enable signal
(WE) controls the writing/reading

• CMOS for optimum speed!
power
• High speed-12 ns
• Low active power
- 550 mW at 40 MHz
• Low standby power
-150 mW
• TIL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

CY7C185
CY7C186

Logic Block Diagram

operation of the memory. When CEI
and WE inputs are both LOW, data on
the eight data input/output pins (1/00
through 1/07) is written into the memory location addressed by the address
present on the address pins (Ao
through AI2). Reading the device is accomplished by selecting the device and
enabling the outputs, CEI and OE active LOW, CE2 active HIGH, while
(WE) remains inactive or HIGH. Under these conditions, the contents of
the location addressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high
impedance state unless the chip is selected, outputs are enabled, and write
enable (WE) is HIGH.

Pin Configurations
Vee

WE

A.

C',

A,

A,
A,

A,

A,
Jog

A,

DE

7

>1++++1-'--1/0,
>1++++_-1/0,
>1++#--1/0,

ON'

0147-2

.f1+++---1/0.

3
NC
A7
A,
A.
A,.
Al1
A"

>1+<1---1/0,
>1-'----1/0,
>_---1/07

26

,.
23

C',
A,
A,
A,

'0

'2
21
'0

CEI

7
8
9

25

OF:
Ao

19

1/07

18
1/01 12
1314151617

I/Os

1/°0

0147-1

•
5

•
11

~~~~~

0147-3

Selection Guide
7C185-12
7C186-12
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)

7C185-15
7C186-15

12

15

Commercial

125

120
145

Military

155

Commercial

30

30

Military

50

50

2-193

,.

fin
.

CY7C185
CY7C186

ADVANCED INFORMATION

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=
Maximum Ratings

(Above which the useful life may be impaired.· Exposure to absolute maximum rated conditions for exiended periods may
affect device reliability. For user guidelines, not tested.)
Static Discharge Voltage ..................... > 200 IV
Storage Temperature ............... - 65°C to + 1500C
(Per MIL-STD-883 Method 3015)
Ambient Temperature with
Latch-up Current .......................... > 200 rnA
Power Applied .................... - 55°C to + 125°C
Supply Voltage to Ground Potential
Operating Range
(pin 28 to Pin 14) .................... -0.5V to + 7.0V
Ambient
Range
DC Voltage Applied to Outputs
Vee
Temperature
inHighZState ...................... -0.5Vto +7.0V
Commercial
OOCto +700C
5V ±1O%
Input Voltage[!4] .................... - 3.0V to + 7.0V
Military[3]
55°C
to
+
125°C
5V ±1O%
Output Current into Outputs (Low) ............. 20 mA

Electrical Characteristics Over Operating Range[4]
Parameters

Description

Test Conditions
Vee = Min.,IOH = -4.0mA
Vee = Min.,loL = 8.0mA

lOS

Output HIGH Voliage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[14]
Input Load Current
Output Leakage
Current
Output Short
Circuit CurrentUl

leel

Vee Operations
Supply

Vee = Max.
lOUT = OmA
f= 40 MHz

VOH
VOL
VIR
VIL
IIX
IOZ

GND';; VI';; Vee
GND';; VI';; Vee
Output Disabled

7C185·12
7C186-12
Min.
Max.
2.4
0.4
2.2
Vee
-0.5
0.8
-10
10

7C185·15
7C186·15
Min.
Max.
2.4
0.4
2.2
Vee
-0.5
0.8
-10
10

-10

-10

lee2

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

ISB

Automatic CE I
Power Down Current

Max. Vee,
CEI <': VIH,
Min. Duty
Cycle = 100%

V
V
V
V
/LA

+10

/LA

-300

-300

rnA

Commercial

110

110

Military
Commercial
Military

135
125
155

135
120
145

Commercial

30

30

Military

50

50

Vee = Max., VOUT = GND

+10

Units

rnA
rnA

rnA

Capacitance [2]
Description

Test Conditions

MaxJ131

Input Capacitance

TA = 25°C,f= 1 MHz

5

Vee = 5.0V

7

Parameters
CIN

Output Capacitance

CoUT

Units
pF

Notes:
1. Not more than I output should be shorted at one time. Duration of

3. TA is the ''instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

AC Test Loads and Waveforms
R,.1n

r

CL
INCLUDIN
_JIGANO _
- SCOPE
-

5V

O----J<".,.,.......
3.0V

OUTPUT O - - _ - - - - i

r

:sn

6PF
INCLUDING

_JIG AND
- SCOPE

0147-4

Figure 1s
Equivalent to:

All Input Pulses

R1481n

6Vo---.J¥V>r-...,
OUTPUTo---r----t

_
-

Figure 1b

THEVENIN EQUIVALENT
167!l
OUTPUT 0_-""1
.."'
..•....-

____01.73 V

0147-7

2-194

~n
0147-5

GND

d
:s;5ns

llY'A.-

i0147-6

Figure 2

fiJi~D~R================================================================~
.

ADVANCED INFORMATION

CY7C185
CY7C186

Switching Characteristics Over Operating Range[4, 5]
Parameters

7C185-12
7C186-12

Description

Min.

7C185-15
7C186-15

Max.

Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

12

15

tOHA

Data Hold from Address Change

tACEI

CEI LOW to Data Valid

12

15

ns

tAC~

CEz HIGH to Data Valid

12

IS

ns

12

3

ns
15

3

ns

10

10

ns

tDOE

OE LOW to Data Valid

tLZOE

OE LOW to Low Z

tHZOE

OE HIGH to High Z[6]

tLZCEI

CEI LOW to Low Z[7]

3

5

ns

tLZCEZ

CEz HIGH to Low Z

3

3

ns

tHZCE

CEI HIGH to High Z[6, 7]
CEZ LOW to High Z

3

3
8

tpu

CEI LOW to Power Up

tpD

CEI HIGH to Power Down

8

8

8
0

0
12

ns
ns
ns

ns
ns

15

ns

WRITE CYCLE[8]
twc

Write Cycle Time

12

15

ns

tSCEI

CEI LOW to Write End

10

12

ns

tSCEZ

CEz HIGH to Write End

10

12

ns

tAW

Address Set-up to Write End

10

12

ns

tHA

Address Hold from Write End

0

0

ns

tSA

Address Set-up to Write Start

0

0

ns

tpwE

WE Pulse Width

10

12

ns

tSD

Data Set-up to Write End

10

10

ns

tHD

Data Hold from Write End

0

0

tHZWE

WE LOW to High Z[6]

WE HIGH to Low Z
tLZWE
Noles:
5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified Iou'IOH and CL = 30 pF load capacitance
for 15 ns tAA devices and CL = 20 pF load capacitance for 12 ns
tAA devices.
6. tHZO& tHZCE and tHZWE are specified with CL = 5 pF as in Figure
lb. Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
8. The internal write time of the memory is defined by the overlap of
CEI LOW, CE2 HIGH and WE LOW. Both signals must be LOW

5

ns

7

7
5

9.
10.
II.
12.
13.
14.

ns
ns

to initiate a write and either signal can terminate a write by going
HIGH. The data input setup and hold timing should be referenced to
the rising edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected. <:>E, CE = VIL. CE2 = VIH.
Address valid prior to or coincident with CE transition LOW.
Data I/O is HIGH impedance ifOE = VIH.
For all packages except cerdip (DZZ, DI6) which has maximums of
CIN = 10 pF, CoUT = 12 pF.
VIdmin.) = -3.0V for pulse width < ZOns.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

--=€_~,

DATA OUT

PREVIOUS OATA VA~

*-

~:::::::::::==:=::D:A:T:A:VA:L:IO::::::::::::::::=
2-195

0147-8

tI

fin
.

CY7C185
CY7C186

ADVANCED INFORMATION

~U~================================================================

Switching Waveforms (Continued)
Read Cycle No.2 (Notes 9, 11)
~------------------tRC------------~v-

__________

HIGH

DATA OUT

--l:=7.==~EtE:t====]D~AT~A~V~AL~IDC=::t:=:J~IM!!::PE~D~AN:!!:C~E
PO

SUP~~~

CURRENT _ _ _ _..J

=--

t
~---------------.-5~
ICC

ISB

0147-9

.

Write Cycle No.1 (WE Controlled) (Notes 8, 12)
ADDRESS

--

twc

tscE1

\V

[1111 11111111/

I I 'I If-

:\\\\1\\\\\\\\"
tscE2

:.u

1\\\\\\\\"
t HA ......

tAW
tSA.

t pWE ------

-

~\\
Iso

.1

~

DATA IN

DATA-IN VALID

..:!

~tLZWE

I-- t HZWE
DATA I/o

.1 tHO
~

HIGH IMPEDANCE

DATA UNDEFINED

0147-10

Write Cycle No.2 (CE Controlled) (Notes 8, 12)
twc
ADDRESS
tSCE1

~
tSA

tAW

f'1--- tSCE2 - - -

.r-

\\\\\\\\\\\\\\\\\\\~

t HA tPWE - - -

.I-tso
DATA-IN VALID

*1

DATA IN

~I
----~
I--tHzWE -

DATA I/O

DATA UNDEFINED

/111111/1111/
tHO

*

HIGH IMPEDANCE

Note: IfeE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

2-196

0147-11

fin
.

ADVANCED INFORMATION

CY7C185
CY7C186

~NDU~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===

Truth Table
CEl

CE2

WE

OE

Input/Outputs

Mode

H

X

X

X

HighZ

Deselect Power Down

X

L

X

X

HighZ

Deselect

L

H

H

L

Data Out

Read

L

H

L

X

Data In

Write

L

H

H

H

HighZ

Deselect

til

Ordering Information
Speed
(ns)

12

IS

Package
Type

Operating
Range

Speed

CY7C185-12PC

P21

Commercial

12

CY7C185-12VC

V21

Ordering Code

CY7C185-12DC

D22

CY7C185-12LC

L54

CY7CI85-12DMB

D22

CY7C185-12LMB

L54

CY7C185-15PC

P21

CY7C185-15VC

V21

CY7C185-15DC

D22

CY7C185-15LC

L54

CY7C185-15DMB

D22

CY7CI85-15LMB

L54

(ns)

15
Military
Commercial

Military

2-197

Package
Type

Operating
Range

CY7C186-12PC

P21

Commercial

CY7C186-12DC

D22

CY7CI86-12DMB

D22

Military

CY7C186-15PC

P21

Commercial

CY7C186-15DC

D22

CY7CI86-15DMB

022

Ordering Code

Military

(;n
.

ADVANCED INFORMATION

CY7C185
CY7C186

~~~====================================================~

MILITARY SPECIFICATIONS
Grou~ A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

IoZ

1,2,3

Icc

1,2,3

ISBI

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACEI

7,8,9,10,11

tACE2

7,8,9,10,11

tDOE

7,8,9,10,11

WRITE CYCLE
tSCEI

7,8,9,10,11

tSCE2

7,8,9,10,11

tAw

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

Document #: 38-A-OOOI6

2-198

CY7C185
CY7C186

CYPRESS
SEMICONDUCTOR

8192 x 8 Static R/W RAM

Features

Functional Description

• Automatic power-down when
deselected

The CY7C185 and CY7C186 are high
performance CMOS static RAMs organized as 8192 words by 8 bits. Easy
memory expansion is provided by an
active LOW chip enable (CEi), an active HIGH chip enable (CE2), and active LOW output enable (DE) and
three-state drivers. Both devices have
an automatic power-down feature
(eEl), reducing the power consumption by 73% when deselected. The
CY7C185 is in the space saving 300 mil
wide DIP package and leadless chip
carrier. The CY7C186 is in the standard 600 mil wide package.
An active LOW write enable signal
(WE) controls the writing/reading operation of the memory. When CEI and
WE inputs are both LOW, data on

• CMOS for optimum speed!
power
• High speed-20 ns
• Low active power
-550mW
• Low standby power
-110 mW
• TIL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

the eight data input/output pins (1100
through 1/07) is written into the memory location addressed by the address
present on the address pins (Ao
through AI2). Reading the device is accomplished by selecting the device and
enabling the outputs, CE! and OE active LOW, CE2 active HIGH, while
(WE) remains inactive or HIGH. Under these conditions, the contents of
the location addressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high
impedance state unless the chip is selected, outputs are enabled, and write
enable (WE) is HIGH. A die coat is
used to ensure alpha immunity.

Logic Block Diagram

Pin Configurations
NC

Vee

WE
CE,

'.

"
"iiE

>I+t+l-I+I+t+l-t+--I/O,

'"

>I+t+l-~-1/02

1/00

11

I/O,

I/O,

>I+t~--I/O.

GND

0055-2

... ~ ... Jl~
3iEl2827

>1+<1---1/0.

NC
11.7

4

26

5

2$"3

A8

24

>..----1/0.

At

><~---I/O,

A'0
A'1
A12

23
22
21
20

10

1/°0 "
I/O, 12

eE2
A,2

11.,

Cff
AD

CE,

,. I/O,
18 I/O.

1314151617

0055-1

0055-3

Selection Guide
7Cl8S-20
7Cl86·20
Maximum Access Time (ns)
Maximum Operating
Current (mA)

Commercial

Maximum Standby
Current (rnA)

Commercial

7Cl85·25
7Cl86-25

7Cl8S·3S
7Cl86-35

7Cl85·45
7Cl86·45
45

7Cl8S-S5
7Cl86·55
55

80
100

20

25

35

125

100

100

100

125

100
20/20

100
20/20

20/20

20/20

20/20

20/20

Military

40/20

20/20
40/20

Military

2-199

r;n
.

•

CY7C185
CY7C186

~ocroR================================================

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... >2001V
Storage Temperature ............... -65°C to + 150°C
Ambient Temperature with
(Per MIL-STD-883 Method 3015)
Power Applied .................... - 55°C to + 125°C
Latch-up Current .......................... > 200 mA
Supply Volt~ge to Ground Potential
Operating Range
(pm 28 to Pm 14) .................... -0.5V to + 7.0V
Ambient
DC Voltage Applied to Outputs
Range
Vee
Temperature
inHighZState ...................... -0.5Vto +7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
Commercial
OOCto +700C
5V ±1O%
Output Current into Outputs (Low) ............. 20 mA
Military!3!
- 55°C to + 125°C
5V ±1O%

Electrical Characteristics Over Operating Rangef4!
Description

Parameters

Test Conditions

Output HIGH Voltage Vee = Min., IoH = -4.0 rnA
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
Input HIGH Voltage
Input LOW Voltage[4A!

VOH
VOL
VIH
VIL
IIX

GND:5: VI:5: Vee
GND:5: VI:5: Vee
Output Disabled

los

Input Load Current
Output Leakage
Current
Output Short
Circuit Current[l]

lee

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

Automatic CEI
Power Down Current

Max. Vee,
CEI ~ VIH,
Min. Duty
Cycle = 100%

Coml.

ISBI

Automatic CEI
Power Down Current

Max. Vee,
CEI ~ Vee- 0.3V,
VIN ~ Vee-0.3V
orVIN:5: 0.3V

Coml.

ISB2

Ioz

7C185-20
7C186·20
Min. Max.
2.4
0.4
2.2
Vee
-3.0 0.8
-10
10

7C185·25, 35, 45
7C186·25, 35, 45
Min.
Max.
2.4
0.4
2.2
Vee
-3.0
0.8
-10
10

7C185·55
7C186-55
Units
Min. Max.
2.4
V
0.4
V
2.2
V
Vee
-3.0 0.8
V
-10
10
/LA

-10

-10

-10

Vee = Max., VOUT = GND
Coml.

+10

+10

+10

/LA

rnA

-300

-300

-300

100

100

80

40

125
100
20
40
20

MiI.~
35,45
Mil.~
35,45
20

100

rnA

20
20

20

20

20

20

rnA

rnA

Mil.

Capacitance [2]
Parameters

Description

CoUT

Max.

Test Conditions
TA = 25°C,f
Vee = 5.0V

Input Capacitance

CrN

Output Capacitance

=

1 MHz

Units

5

pF

7

Notes:
1. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.
4A. VIL min. = -3.0V for pulse durations less than 30 ns.

AC Test Loads and Waveforms
R1481n
5V

30pF

OUT.UT 0 - -......

- SCOPE

25511

_

-

5PF

INCLUDING

-=-~~~~D

0055-4

Figure 1a
Equivalent to:

r

R2

INCLUDING

_JIG AND

-=-

Figure 1b

THEVENIN EQUIVALENT
16711

OUTPUT

....

O>----,\,,,YI\oo,--o 1.13V

0055-7

2-200

....

3'OV~

---+

---4

I

An Input Pulses

O--_.-J..,.,......,
R14B1n

• v 0 - - -......."""--,
OUT.UTo--......

~n

GND

1'""
:S::5ns

I---

10%
:S::Sns

0055-6

0055-5

Figure 2

(in

CY7C185
CY7C186
~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Switching Characteristics Over Operating Range[4, 5]
.

Parameters

7C185·20
7C186·20

Description

Min.

Max.

7C185·25
7C186·25
Min.

Max.

7C185·35
7C186·35
Min.

Max.

7C185·45
7C186-45
Min.

Max.

7C185·55
7C186·55
Min.

Units

Max.

READ CYCLE
tRc

Read Cycle Time

tAA

Address to Data Valid

20

25

35

20

45
35

5

ns

55
45

Data Hold from Address Change
CEI LOW to Data Valid

20

25

35

45

55

ns

tACE2

CE2 HIGH to Data Valid

20

25

25

30

40

ns

tDOE

OE LOW to Data Valid

10

12

15

20

25

ns

tLZOE

OE LOW to Low Z

tHZOE

OE HIGH to High Z[6]

tLZCEI

CEI LOW to Low Z[7]

5

5

5

5

5

ns

tLZCq

CE2 HIGH to Low Z

3

3

3

3

3

ns

3

3

3

8

CE1 HIGH to High Z[6, 7]

8

CE2 LOW to High Z

tpu

CEI LOW to Power Up

tpD

CEI HIGH to Power Down

0

10
0

3
12

10

20

ns
20

20

15
0

20

ns

3
15

15
0

20

5

ns

toHA

5

5

55

tACEI

tHZCE

5

25

0
25

ns

ns
ns

25

ns

WRITE CYCLE[8]
twc

Write Cycle Time

20

20

25

40

50

ns

tSCEI

CEI LOW to Write End

15

20

25

30

40

ns

tSCE2

CE2 HIGH to Write End

15

20

20

25

30

ns

tAW

Address Set·up to Write End

15

20

25

30

40

ns

tHA

Address Hold from Write End

0

0

0

0

0

ns

tSA

Address Set-up to Write Start

0

0

0

0

0

ns

tpWE

WE Pulse Width

15

15

20

20

25

ns

tSD

Data Set-up to Write End

10

10

15

15

25

ns

tHO

Data Hold from Write End

0

tHZWE

WE LOW to High Z[6]

0

0

7

WE HIGH to Low Z
5
tLZWE
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified lOr/lOR and 30 pF load capacitance.
6. tHZOE. tHZCE and tRZWE are specified with CL = 5 pF as in Figure
1h. Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, tRZCE is less than
tLZCE for any given device.
8. The internal write time of the memory is defined by the overlap of
CEI LOW, CE2 HIGH and WE LOW. Both signals must be LOW

7
5

5

9.
10.
11.
12.

0

10

0

5

ns
20

15
5

ns
ns

to initiate a write and either signal can terminate a write by going
HIGH. The data input setup and hold timing should be referenced to
the rising edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected. OE, <::E = VIL. CE2 = VIR.
Address valid prior to or coincident with CE transition LOW.
Data I/O is HIGH impedance ifOB = VIH.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

----------------------tRC-----------------------J~.

~
-~ =i~~
==;:::;::t.Aiimi====:;--"- ¥ toHA

DATA OUT

-'-"'--I

PREVIOUS DATA VAuo

_ _ _ _ _ _ _ _D_A_T_A_VA_L_ID_ _ _ _ _ _ __

0055-8

2-201

•

5n
.

CY7C185
CY7C186

,

~~~~~~~~~~~~~~~~~~~~~~~~~~~====~~~=
Switching Waveforms (Continued)
Read Cycle No.2 (Notes 9, 11)
tRc

~

CE2

---I
tACE

~
t LZOE

f

..

t HZOE -----

F tOOE -

t HZCE

HIGH
IMPEDANCE

DATA OUT

-

HIGH
IMPEDANCE

DATA VALID

- - t LZCE -----

SUP~~

- - tpu

1
. . -so-,,----------------s:t :~~
-tpo

____

CURRENT

0055-9

.

Write Cycle No.1 (WE Controlled) (Notes 8, 12)
twc
ADDRESS

.

tSCEl

CE1

\\?

CE2

II I If-

~I

I I I 11111111/

:\ \ \ \ \\\\\\\\'

'I

tscE2

I.LJ

I\\""-\\"'-\\.'
tAW

t HA---

!sA

- tpWE -

.3k:\\
t so - -

,I

•

DATA IN

DATA

I/O

DATA-IN VALID

I-- tHZWE.:I

d

tHO

•

i-- t LZWE
HIGH IMPEDANCE

DATA UNDEFINED

0055-10

Write Cycle No.2 (CE Controlled) (Notes 8, 12)
twc
ADDRESS
~

tSCE1 -

.3k:
\sA
CE2

.

ftAW

'I--- t SCE2 -- t HA -

. l - - tpWE -

~I I

\\\\\\\\\\\\\\\\\\\~

.1--'-- tso

.1

DATA IN

I/O

DATA UNDEFINED

tHO

DATA-IN VALID

I--tHZWEj
DATA

I I I I I I I I I 1/

•

HIGH IMPEDANCE
0055-11

-

Note: IfCE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state,

2-202

fin
.

CY7C185
CY7C186

~~================================================================

Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT

VI

leV

1.2

~ 1.0
0.8

V

N

::; 0.6
«

N

::;

'"0z

0.4

:>
0

0.4

«

5.0

5.S

6.0

0

z

.

1.4

...

1.2

.............

«
0:

r--

~

4.0

4.5

S.5

S.O

1.0

0

-

z
0.8

I'

..

;; 15.0

....
~ 10.0

IE

0.5

-

/

V

0.0
0.0

1.0

2.0

3.0

5.0
0.0

4.0

SUPPL V VOL TAG E (VI

5.0

/

-

200

/
TA • 25'C
vee -4.SOV

400

/1'
100

/

80

Vee' 5.0 V
TA - 25'C

If

60

:>

40

:>
0

20

/
V

0.0

/
1.0

2.0

3.0

4.0

NORMALIZED Icc
VS. CYCLE TIME

----r-----,

1.25 . - - -.....

]

Vee - 5.0 V
TA - 25'C
V'N-O.5V
1.ot----;----+----::;01

~

/

a

~

OUTPUT VOLTAGE IVI

/

..

1.5
1.0

'"::>
"z

125

/

20.0

4.0

120

II:

TYPICAL ACCESS TIME CHANGE
VI. OUTPUT LOADING

!

2.0

w

51

z

.......

25

25.0

N

II:

....

"in

Vee - 5.0 V

30.0

2.5

::;

/

"

3.0

OUTPUT SINK CURRENT

AMBIENT TEMPERATURE eCI

TYPICAL POWER·ON CURRENT
VI. SUPPLY VOLTAGE

«

/

·55

SUPPL V VOLTAGE IVI

3.0

2.0

1.0

vs. OUTPUT VOLTAGE

0.6

6.0

"-

OUTPUT VOLTAGE IVI

!

::;
:;;

Vee -5.0 V
TA ·25'C

140

N

0.8

0

0.0

NORMAUZED ACCESS TIME
AMBIENT TEMPERATURE

TA -2S'C

~

a
125.0

25.0

·55

~
0

1.0

20

VI.

1.2

0.9

j

:>
0

;{

...........

40

AMBIENT TEMPERATURE ('CI

1.3

1.1

'"

60

:>

1.6

~

II:

.....

Vee -5.0V
V,N -S.OV

NORMALIZED ACCESS TIME
vs SUPPLY VOLTAGE

::;

..

80

II:

0.0
4.5

1.4

S
N

z

0.2 I--Is.

Is.

II

100

w

'":>
"<.>
w

II:

0.6

SUPPL V VOLTAGE (VI

.

~

«

0.2

~

..
!

~

0
w

OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE

VI

120
;{

U 0.8

IE

0.0
4.0

~

1.0

1)

IE

'"~

1.2

./

/'

]

...0

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

vs SUPPLY VOLTAGE

1.4

600

CAPACITANCE loFI

800

1000

i

~ 0.751-----:I;"..".:;..--+----~

0.50,·':0---~20:---~30~--~4O
CYCLE FREQUENCY (MHzl
0055-13

2·203

&n~~============================================================~
CY7C185
CY7C186

. .

Truth Table
CEl

CEz

WE

OE

Input/Outputs

Mode

H

X

X

X

HighZ

Deselect Power Down
Deselect

X

L

X

X

HighZ

L

H

H

L

Data Out

Read

L

X

L

X

Data In

Write

L

H

H

H

HighZ

Deselect

Ordering Information
Speed
(ns)
20

25

35

45

55

Ordering Code

Package
Type

Operating
Range

Speed
(ns)

Commercial

20

CY7C185-20PC

P21

CY7C185-20VC

V21

CY7C185-20DC

D22

CY7C186-20LC

L54

CY7C185-25PC

P21

CY7C185-25VC

V21

25
Commercial
35

Package
Type

Operating
Range

CY7C186-20PC

P21

Commercial

CY7C186-20DC

D22

Ordering Code

CY7C186-25PC

P21

CY7C186-25DC

D22

Commercial

CY7C186-25DMB

D22

Military

CY7C186-35PC

P21

Commercial

CY7C185-25DC

D22

CY7C186-35DC

022

CY7C185-25LC

L54

CY7C186-35DMB

D22

Military

CY7C185-25DMB

D22

CY7C186-45PC

P21

Commercial

CY7C185-25LMB

L54

CY7C186-45DC

D22

CY7C185-25KMB

K74

CY7C185-35PC

P21

Military

45

Commercial

55

CY7C186-45DMB

D22

Military

CY7C186-55PC

P21

Commercial

CY7C185-35VC

V21

CY7C186-55DC

D22

CY7C185-35DC

D22

CY7C186-55DMB

D22

CY7C185-35LC

L54

CY7C185-35DMB

D22

CY7C185-35LMB

L54

CY7C185-35KMB

K74

CY7C185-45PC

P21

CY7C185-45VC

V21

CY7C185-45DC

D22

CY7C185-45LC

L54

CY7C185-45DMB

D22

CY7C185-45LMB

L54

CY7C185-45KMB

K74

CY7C185-55PC

P21

CY7C185-55VC

V21

CY7C185-55DC

D22

CY7C185-55LC

L54

CY7C185-55DMB

D22

CY7C185-55LMB

L54

CY7C185-55KMB

K74

Military

Commercial

Military

Commercial

Military

2-204

Military

&l

. CYPRESS

SEMICONDUCTOR

CY7C185
CY7C186

=============================~~~~

BitMap

Address Designators
Address
Name
A4
AS
A6
A7
A8
A9
AlO
All
AI2
AO
Al
A2
A3

0055-14

2-205

Address
Function
X3
X4
X5
X6
X7
YI
Y4
Y3
YO
Y2
XO
XI
X2

Pin
Number
2
3
4
5
6
7
8
9
10
21
23
24
25

II

r;n
.

. CYPRESS
SEMICONDUCTOR

CY7C185
CY7C186

===========================;;;;;;;====

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

Vm

1,2,3

VILMax.

1,2,3

IIX

1,2,3

IOZ

1,2,3

lOS

1,2,3

ICC

1,2,3

ISBI

1,2,3

ISB2

1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACE!

7,8,9,10,11

tACE2

7,8,9,10,11

tOOE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE!

7,8,9,10,11

tSCE2

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

Document #: 38-00037-0

2-206

CY7C187

CYPRESS
SEMICONDUCTOR

65,536

Features

Functional Description

• Automatic power-down when
deselected
• CMOS for optimum speed/
power
• High speed-20 ns
• Low active power
-440mW
• Low standby power

The CY7Cl87 is a high performance
CMOS static RAM organized as
65,536 words x 1 bit. Easy memory expansion is provided by an active LOW
chip enable (CE) and three-state drivers. The CY7Cl87 has an automatic
power-down feature, reducing the power consumption by 80% when deselected.
Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW.
Data on the input pin (DI) is written
into the memory location specified on
the address pins (Ao through A15).

-llOmW

• TIL compatible inputs and
outputs
• Capable of withstanding greater
than 2001V electrostatic
discharge

Logic Block Diagram

X

1 Static R/W RAM
Reading the device is accomplished by
taking the chip enable (CE) LOW,
while write enable (WE) remains
HIGH. Under these conditions the
contents of the memory location specified on the address pins will appear on
the data output (DO) pin.
The output pin stays in high impedance
state when chip enable (CE) is HIGH
or write enable (WE) is LOW.
The 7Cl87 utilizes a Die Coat to ensure alpha immunity.

Pin Configurations

~----------~C.---------DI

",.
A,

Vee

A,

A'5
A,.

A2

A3

A13

A3

A'2
NC

A.
A6

A"
A,o

A6

A"
A,o

A7

A9

A7

A9

iloUT

As

As

WE

DIN

DIN

GND

CE

>-----00

"'6
....

Ao

A'5
A,.
A.
As
NC

",.",.

Vee

GND

Ao
Ao

A'3
A12

A5

CE

0029-2

u.,

0029-16

c~.,;>c

Vee

_....-_-We

A5

A"
Ne

A2
A3
A4
A5
A6
A7

A6

A,o

DOUT

A,

A'5
A,.
A13

0029-1

A12

Ag
A8

WE

DIN

GND

CE

2 1 2221
20
3
4
19
5
18
6
7

8
9

17

16
15
14
10111213

I~ ~Itl

J

A'4
A13
A12
All
AID
A9
A8

0029-3

0029-17

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
Maximum Standby
Current (rnA)

Commercial
Military
Commercial
Military

7C187-20
20
80
40/20

2-207

7C187-25
25
70
70
20/20
40/20

7C187-35
35
70
70
20/20
20/20

7C187-45
45
50
70
20/20
20/20

fI

~

CY7C187

~~~ND~ ========================================================~====~~
Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... >2001V
Storage Temperature ............... -6S'C to + ISO"C
(Per MIL-STD-883 Method 3015)
Ambient Temperature with
Power Applied .................... - SS'C to + 12S'C
Latch-up Current .......................... > 200 rnA
Supply Voltage to Ground Potential
Operating Range
(pin 22 to Pin 11) .................... -O.SV to +7.0V
Ambient
DC Voltage Applied to Outputs
Range
Vee
Temperature
in High Z State ...................... - 0.5V to + 7.0V
O"Cto +70"C
5V ±IO%
Commercial
DC Input Voltage ................... - 3.0V to + 7.0V
Military [4]
-55'Cto + 12S'C
SV ±1O%
Output Current into Outputs (Low) ............. 20 rnA

Electrical Characteristics Over Operating RangeCS)
Parameters

Description

7C187-20

Test Conditions

Min. Max.
Output HIGH Voltage

VOH

Vee = Min.,IOH = -4.0mA
Vee = Min. IIOL = 8.0 rnA
I IOL = 12.0 rnA

2.4
Military

VOL

Output LOW Voltage

VIH
VIL

Input HIGH Voltage
Input LOW Voltagel5A]

IIX

Input Load Current

loz

Output Leakage Current GND ,,; Vo ,,; Vee, Output Disabled

los

Output Short Circuit
Current U]

Vee = Max., VOUT = GND

lee

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

ISB!

Automatic CE[2]
Power Down Current

CE~ VIH

Max.

2.4
0.4

0.4

0.4

V

2.2
-3.0

Vee
0.8

Vee
0.8

-3.0

Vee
0.8

V

-3.0

-10

+10

-10

+10

-10

+10

",A

-10

+10

-10

+10

-10

2.2

-350
Commercial

2.2

+10

",A

-350

rnA

70

50

70

70
20

20

40

Military~
35

V

-350

80

Commercial

Max. Vee, CE ~ Vee - 0.3V,
VIN ~ Vee - 0.3Vor
VIN"; 0.3V

Units
V

2.4

Military

Max. Vee,

7C187-45
Min. Max.

Commercial

GND"; VI"; Vee

Automatic CE[2]
Power Down Current

ISB2

7C187-25,35
Min.

40

20

rnA

rnA

20

Commercial

20

20

20

20

20

rnA

Military

Capacitance [3]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions

Max.

TA = 25'C,f= 1 MHz
Vee = 5.0V

5

Notes:
1. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vcc on the CE input is required to keep the
device deselected during Vee power-up, otherwise ISB will exceed
values given.

7

Units
pF

3. Tested iuitially and after any design or process changes that may
affect these parameters.
4. TA is the "instant on" case temperature.

5. See the last page of this specification for Group A subgroup testing
information.
SA. VIL min. = - 3.0V for pulse durations less than 30 ns.

AC Test Loads and Waveforms
R1 329 n
(480n MILl

R13290
1480  200 IV
(per MIL-STD-883 Method 3015)

Storage Temperature ............... -65°C to + ISO"C
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latchup Current .......................... > 200mA

Supply Voltage to Ground Potenial
(Pin 16 to Pin 8) ..................... -O.SV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in HighZ State ...................... -O.SV to +7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial
Military[4]

Output Current, into Outputs (Low) ............. 20 rnA

Ambient
Temperature

Vee

O"Cto +70"C

5V ±1O%

- 55°C to + 125°C

5V ±1O%

Electrical Characteristics Over the Operating Range[5]
Description

Parameters

7C189-15
7C190-15

Test Conditions

Min.

7C189-25
7C190-25

Max.

Min.

Units

Max.

VOH

Output HIGH Voltage

VCC = Min.,IOH = -5.2rnA

VOL

Output LOW Voltage

Vcc = Min.,IoL = 16.0mA

Vrn

Input HIGH Voltage

2.0

Vcc

2.0

VIL

Input LOW Voltage

-3.0

0.8

-3.0

0.8

V

IIX

Input Leakage Current

GND:;;: VI:;;: VCC

-10

+10

-10

+10

/LA

VCD

Input Diode Clamp
Voltage U]

Ioz

Output Leakage Current

GND :;;:Vo:;;: Vee

-40

+40

-40

+40

/LA

los

Output Short
Circuit Current12]

Vcc = Max., VOUT = GND

-90

rnA

Icc

Power Supply Current

Vcc = Max.,
loUT = ornA

55

mA

70

mA

2.4

2.4
0.45

I Commercial
I Military

-90
90

V
0.45

V

Vcc

V

Capacitance [6]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions

Max.

TA = 25°C, f = 1 MHz
Vcc = 5.0V

4

Units
pF

7

Notes:
1. The CMOS process does not provide a clamp diode. However the
CY7Cl89 and CY7CI90 are insensitive to - 3V dc input levels and
- 5V undershoot pulses of less than 5 ns (measured at 50% points).
2. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
3. Output is preconditioned to data in (inverted or non-inverted) during
write to insure correct data is present on all outputs when write is
terminated. (No write recovery glitch).

4. T A is the "instant on" case temperature.
5. See the last page of this specification for Group A subgroup testing
information.
6. Tested initially and after any design or process changes that may
affect these parameters.

2-216

fin

CY7C189
CY7C190

.

~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Switching Characteristics Over the Operating Range[5, 71
Parameter

Description

Test
Conditions

7C189-15
7Cl90-15
Min.

7C189-25
7C190-25

Max.

Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tACS

Chip Select to Output Valid

tHZCS

Chip Select Inactive to High Z

tLZCS

Chip Select Active to Low Z

tOHA

Output Hold from Address Change

tAA

Address Access Time

25

15

ns

12
12
12

Note 10
Notes 9,11

15
15
15

5

5

ns
ns
ns

25

15

Note 10

ns

ns

WRITE CYCLE[3, 8)
twc

Write Cycle Time

tHZWE

Write Enable Active to High Z

tLZWE

Write Enable Inactive to Low Z

tAwE

Write Enable Inactive to Output Valid

tpwE

Write Enable Pulse Width

tso

Data Setup to Write End

tHO

Data Hold from Write End

tSA

Address Setup to Write Start

15
Notes 9,11

20

Note 10

20
20
20

15
15
0
0
0

Address Hold from Write End

tHA
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of I.5V, output loading of the specified IOL /IOH
and 30 pF load capacitance.
8. The internal write time of the memory is defined by the overlap of
CS LOW and ~ LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.

ns

12
12
12
20
20
0
0
0

ns
ns
ns
ns
ns
ns
ns

9. Transition is measured at steady state HIGH level - 500 mV or
steady state LOW level + 500 mV on the output from 1.5V level on
the input.
10. tAA, tACS and tAWE are tested with CL = 30 pF as in Figure lao
Timing is referenced to 1.5V on the inputs and outputs.
11. tHZCS and tHZWE are tested with CL = 5 pF as in Figure lb.

BitMap

Address Designators

0011-5

2-217

Address
Name

Address
Function

Pin
Number

Ao

AXO

1

AI

AXI

15

A2

AYO

14

A3

AYI

13

fI

CY7C189
W'r~ ====================C=Y=7C=1=9==O
~

AC Test Loads and Waveforms
ALL INPUT PULSES
R12311fi

R12311n

5V~------~~~.,

5V O-----J
N_.,

OUWUT~---'------~

OU~UT~--~-----1

3.0V----~~--_

GND----~

I

R2

30pF

I

1500

'NCLUD'NG
JIG AND

"::" SCOPE

<5ns

R2

5pF

<5"s

1500

0011-8

INCLUDING
_JIGAND _

"::"

- SCOPE

0011-6

Figure 18
Equivalent to:

Figure Ib
THEVENIN EQUIVALENT

OUTPUT OO------'\~..---OO I.S2V
0011-1

Read Mode

J;~~----tRC--------~~

A~~~~------~~:~~~~~~~~-~-A-_-_-_-_--_-_-_-_-~.-'----~-~-H-A---------------------------------~
eI --------------~.

CHIP SELECT

DATA _____________________~----~~~~~----------~~~~r-------II------15
OUTPUTS
I)-~!!---------00-03
NOTES
0011-9

twc---}

Write Mode

Ao-A3

ADDRESS

JtsA

es

I-tHA

CHIP SELECT

tHD_

tso
00-0 3
DA'fAIN

WE

WRITE ENABLE

-l f-

....;

-j I-

tpw.

r
tHzw.

--

-.L..NOTE9

00-03
DATA OUTPUTS
LOAD

_tAWE ---!

~

L

NOTE9

-tLZWEJ
0011-10

(All above measurementE referenced to t.5V,)

Note:
Timing diagram representE one solution which resuitE in an optimum cycle time. Timing may he changed in various applications as long as the worst case
limitE are not violated.

2-218

(;n

CY7C189
CY7C190

• CYPRESS

~OOID~==~~~~~~~~~~~~~~~~~~~~~~~~~~

Typical DC and AC Characteristics
NORMAUZED Icc
1.2

11

1.0

~

~
a:

i

0.8

0.6

V

O.4
4.0

1.4

/

V

c

:::;

vs. AMBIENT
TEMPERATURE
.

60

Vee =5.5 V
TA -ZS'C

6.0

I
6.6

AMBIENT TEMPERATURE

1.4

" " "-

5.0

5.5

100

~

.

5

0;

50

I

1.0

2.0

3.0

4.0

5.0

NORMALIZED Icc
FREQUENCY

VB.

~/

11

~

~
~

10'1----hi£....+---l---~-_l

1.2

i

1000

00

v

V~

1. 1
1.0

BOO

Vee =5.0V
TA = ZS'C

1.4

~~-+--4---~~-+-~

600

J

OUTPUT VOLTAGE (V)

1.3

400

/

ZS

AMBIENT TEMPERATURE ('C)

200

V

/
oV

!5o

O'~~----::ZS~-----:!IZS

~~-~-~----~---

:!l

4.0

3.0

OUTPUT SINK CURRENT
VB. OUTPUT VOLTAGE

z

ACCESS TUME CHANGE
VS. OUTPUT LOADING

$
~

2.0

J...ooo""

5
Vee -s.OV

6.0

1.0

125

~

a:

SUPPLY VOLTAGE (VI

!

o

1

i
i ZS'C

i\...

ro...

0

160

~

1.0

z

4.6

0

NORMALIZED ACCESS TUME
AMBIENT TEMPERATURE

:::;

0.6
4.0

~
5o

VS.

N

N

:::;

fI

Vee =s.ov
TA = 26'C

OUTPUT VOLTAGE (V)

c
W

1.2

TA

20

rc)

c
$

c
$

0.8

fil

0·~5L.5----.JZS-----...J126

6.0

1.4

2
0

"

30

::>

NORMALIZED ACCESS TIME

a:

40

a:

VB. SUPPLY VOLTAGE

C

a:
a:

t\..

::>

1.6

w

50

u
~

SUPPLY VOLTAGE (V)

Q

1
~

//
4.6

OUTPUT SOURCE CURRENT
VI. OUTPUT VOLTAGE

NORMALIZED Icc

vs SUPPLY VOLTAGE

/

V

1020~40506070
FREQUENCY (MHz)

CAPACITANCE (pF)

0011-11

2-219

fin
..

CY7C189
CY7C190

~~=======================================

Ordering Information
Speed
(os)

15

25

Ordering Code
CY7C189-15PC
CY7C190-15PC
CY7C189-15DC
CY7Cl90-15DC
CY7C189-15LC
CY7C190-15LC
CY7C189-25PC
CY7CI90-25PC
CY7C189-25DC
CY7C190-25DC
CY7C189-25LC
CY7C190-25LC
CY7C189-25DMB
CY7CI90-25DMB
CY7C189-25LMB
CY7C190-25LMB

Pin Configuration

Package
Type
PI

Operating
Range
Commercial

D2
L61

WE

4

DO

5

17

"2

(00)00
01

6
7

16

"3

15

03

NC

8

14

03(03)

NC

PI

D2
L61
D2

0011-4

Military

L61

2-220

(7C189)
7Cl90

&n
.

CY7C189
CY7C190
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

IOZ

1,2,3

IcC

1,2,3

EI

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tACS

7;8,9,10,11

taHA

7,8,9,10,11

tAA

7,8,9,10,11

WRITE CYCLE

twc

7,8,9,10,11

tAWE

7,8,9,10,11

tpWE

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

tSA

7,8,9,10,11

tHA

7,8,9,10,11

Document #: 38-ooo39-B

2-221

CY7C191
CY7C192

PRELIMINARY

CYPRESS
SEMICONDUCTOR

65,536

X

4 Static R/W RAM
Separate I/O

Features
• Automatic power-down when
deselected
• Transparent write (7CI91)
• CMOS for optimum speed!
power
• High speed
- 25 ns tAA
• Low active power
- 385mW
• Low standby power
-110mW

• TTL compatible inputs and
outputs

• Capable of withstanding greater
than 2001V electrostatic
discharge

Functional Description

Data on the four input pins (10 through
13) is written into the memory location
specified on the address pins (Ao
through A1S).

The CY7C191 and CY7C192 are high
perfonnance CMOS static RAMs organized as 65,536 x 4 bits with separate
VO. Easy memory expansion is provided by active LOW chip enable (CE)
and three-state drivers. They have an
automatic power-down feature, reducing the power consumption by 71 %
when deselected.

Reading the device is accomplished by
taking the chip enable (CE) LOW,
while the write enable (WE) remains
HIGH. Under these conditions the
contents of the memory location specified on the address pins will appear on
the four data output pins.
The output pins stay in high impedance
state when write enable (WE) is LOW
(7C192 only), or chip enable (CE) is

Writing to the device is accomplished
when the chip enable (CE) and write
enable (WE) inputs are both LOW.

HIGH.
A die coat is used to insure alpha im-

Logic Block Diagram

munity.

Pin Configurations

'0

A.

1

28

Vee

A7

2
3

27
26

As

Ag

2.

A'D
A"

24
23

A3
A2
A,

22

AD

As

''3

Ao

A,
A2
A.

DO

A,.
A,.
A,.
A,.

A.A.

D,

'0

A.

D_

CE"

"

21

'3

2D

'-

19

12

18

D.
D_

17

D,
DO

WE

GNO

A7

A.
Ag

6
7
8
9
lD

A.

D3

0108-2

..~~J'~:R
A'D

A"
A,_
A,.
A,.
A,.

WE

'0
"

.............................

0108-1

3

i

1I12827
26
25
24 A_
23 A,
22 Ao
21
lD
2D
19 O.
12
'8 D.
13104151617

Ag •

CE

A.
A.

S

''..

"

Itl ~I~ 80"
0108-10

Selection Guide

Maximum Access Time (ns)
Maximum Operating
Current (mA)

Commercial
Military

Maximum Standby
Current (rnA)

Cornrnercisl
Military

7C191-25
7C192-25
25
80
20

2-2.22

7C191-35
7C192-35
35
80
90
20
20

7C191-45
7C192-45
45
70
90
20
20

5A~~============================================================~
.

CY7C191
CY7C192

PRELIMINARY

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... > 2001V
(Per MIL-STD-883, Method 3015)

Storage Temperature ............... -65°C to + 150"C
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latch-up Current .......................... > 200 mA

Supply Voltage to Ground Potential
(Pin 28 to Pin 14) .................... -0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V

Range

Ambient
Temperature

Vee

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial

O"C to + 70"C

5V ±1O%

Output Current into Outputs (LOW) ............ 20 mA

Military!2]

- 55°C to + 125'C

5V ±1O%

Electrical Characteristics Over Operating Range!3]
Deseription

Parameters

7C191·25
7C192·25

Test Conditions

7C191-45
7C192-45

7C191·35
7C192·35

Units

Min. Max. Min. Max. Min. Max.
VOH

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee

= Min., IOH = -4.0 mA
= Min., IOL = 8.0 mA

2.4

VIH

Input HIGH Voltage

2.2

VIL

Input LOW Voltage

-3.0
-10

IIX

Input Load Current

loz

Output Leakage Current GND ::;;; Vo::;;; Vee, Output Disabled

lOS

Output Short Circuit
Current!l]

Vee

Icc

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

ISBI

Automatic CE
Power Down Current

Commercial
Max. Vee, CE;;:: VIH
Min. Duty Cycle = 100% Military

ISB2

Automatic CE
Power Down Current

Max. Vee,
CE;;:: Vee - 0.3V
VIN;;:: Vee - 0.3Vor
VIN::;;; 0.3V

GND::;;; VI::;;; Vee

-10

= Max., VOUT = GND

Vee
0.8

0.4
2.2

+10

-3.0
-10

+10

-10

-350

Commercial

2.4

2.4
0.4

V
0.4

V

Vee
0.8

V

+10

2.2
-3.0
-10

+10

J.IoA

+10

-10

+10

J.IoA

-350

-350

rnA

Vee
0.8

80

V

80

70

90

90

20

20

20

20

20

20

20

20

20

Military

20

20

Test Conditions

Max.

Units

= 25°C, f = 1 MHz, Vee = 5.0V
TA = 25°C, f = 1 MHz, Vee = 5.0V

5

pF

7

pF

Military

Commercial

rnA
mA

mA

Capacitance [4]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

TA

Notes:
1. Not more than one output should shorted at one time. Duration of

3. See the last page of this specification for Group A subgroup testing
information.
4. Tested initially and after any design or process changes that may
affect these parameters.

the short circuit should not exceed 30 seconds.
2. TA is the "instont on" case temperature.

AC Test Loads and Waveforms
Rl481!!

Rl 4811!

5VO-------~~~

5V
OUTPUT

OUTPUT 0----1'"""""--......

r
_
-

30PF
INCLUDING
JIGAND _
SCOPE
-

0-------.......""".-.,

0 - -_ _- -......

I

~:51!

INCLUDING
_JIG AND
_
- SCOPE
-

Figure la
Equivalent to:

3.0V----~~::_--~

~:Sl!

5pF

Figure Ib
167!!

0 - -.......
'''''
..·''''.--.....0

1.73 V

< 5nl

0106-3

0108-5

Figure 2

THEVENIN EQUIVALENT
OUTPUT

OND _ _-Z"

0106-4

2·223

fI

.
Q
~==================
.

CY7C191
CY7C192

PRELIMINARY

Switching Characteristics Over Operating Range!3, 5]
Parameters

Description

7C191-25
7C192-25
Min.

Max.

7C191-35
7C192-35
Min.

Max.

7C191-45
7C192-45
Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

toHA

Output Hold from Address Change

25
3
3

tHZCE

en LOW to Data Valid
en LOW to LOW Z[71
en HIGH to High Z!6, 71

tpu

CE LOW to Power Up

0

tACE
tLZCE

35
25
3

15

Write Cycle Time

20

tSCE

en LOW to Write End

tAw

Address Set-up to Write End

tHA

ns
ns

IS
0

35

ns
ns

45
3

0
25

twc

3

3
10

ns
45

35

25

tpD
CE HIGH to Power Down
WRITE CYCLE[81

45
35

ns
ns

45

ns

30

40

ns

20

30

35

ns

20

25

35

ns

Address Hold from Write End

2

2

2

ns

tSA

Address Set-up to Write Start

0

0

0

ns

tpWE

WE Pulse Width

20

25

35

ns

tSD

Data Set-up to Write End

10

IS

20

ns

tHD

Data Hold from Write End

0

0

0

ns

tLZWE

WE HIGH to Low Z[7] (7CI92)

3

3

3

tHzwE

WE LOW to High Z[6, 71 (7CI92)

10

10

IS

ns

tAWE

WE LOW to Data Valid (7CI91)

25

30

35

ns

tADV

Data Valid to Output Valid (7CI91)

20

30

35

ns

Notes:

5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of I.5V, input pulse levels ofOV to 3.0V and output
loading of the specified Ior/IoH and 30 pF load capacitance.
6. tHZCE and tHzWE are specified with CL = 5 pF as in Figure 1b.
Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, tm is less than tLZ
for any given device.

ns

8. The internal write time of the memory is defmed by the overlap of
CE WW and WE LOW. Both signals must be LOW to initiate a

write and either signal can terminate a write by going HIGH. The

data input setup and hold timing should be referenced to the rising

edge of the signal that terminates the write.
9. WB is HIGH for read cycle.
10. Device is continuously selected. CE = VIL.
t I. Address valid prior to or coincident with CE transition LOW.

Switching Waveforms
Read Cycle No.1 (Notes 9, 10)

---*-

~

~-----------------------tRC-------------------------1~.

ADDRESS

DATA OUT

~_H_A____~_A_~,------------------------------------------

______I_.:_______
PREVIOUS DATA VALID

~

DATA VALID

0108-6

2-224

&1
.

PRELIMINARY

CY7C191
CY7C192

~U~==============================================================~

Switching Waveforms (Continued)
Read Cycle (Notes 9, 11)
tRe

j

fI

...,

.....
tACE

..-tHzCE .......

HIGH IMPEDANCE

DATA OUT

ILZCE

!---tpu

IJ'

HIGH
IMPEDANCE

J' J' 'J' J'

DATA VALID

·1" " " " "

!--tPD

1,-------------------------1---,

CUS~~~~~ ____--150%

~t_ISB

ICC

0108-7

Write Cycle No.1 (WE Controlled) (Note 8)
twc
ADDRESS

-

~
tSCE

~\ ,~\3k

:;IU1IIIIIIill
tAW
tSA

t HA -

~tpWE-

'I

3k\\
.1 tHD

tSD
DATA IN

•

DATA-IN VALID

~tHZW:=I
DATA OUT

- - tLZWE
HIGH IMPEDANCE

DATA UNDEFINED

(7C192)

~tADV

DATA OUT

DATA UNDEFINED

(7C191 )

:::::I.
DATA VALID
J""----_
_
0108-8

Write Cycle No.2 (CE Controlled) (Note 8)
twc
ADDRESS

-

tSA

tSCE -

3k

1

tAW

t HA -

I---tpWE -

~I ILl I

\\ \\\ \ \\ \ \ \ \ \ \ \ \ \ \ \:
tSD

*

DATA IN
DATA OUT

(7C192)

X

DATA-IN VALID

I - t HzWE

--:1

DATA UNDEFINED

-t
AWE

I I I I ILb

tHD

HIGH IMPEDANCE

-

~

DATAOUT-------------D-Ar-A-U-N-D-EF-IN-E-D----------------~

----DA-r-A-V-AL-ID-------(7C191) ____________________________________..J. ,-,
_ _ _ _ _ _ __

Note: lfeE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state (7C192 Duly).

2-225

0108-9

~

CY7C191

..,;-~~========================P=~=E=L=IM=I=N,=~=R=Y===C=Y=7=C=1==92
Ordering Information
Speed
(os)

25

35

45

Package
Type

Operating
Range

CY7C192-25PC

P21

Commercial

CY7C192-25VC

V21

022

CY7C1 92-25DC

022

L54

CY7C192-25LC

L54

Package

Operating

Speed

Type

Range

(os)

CY7C191-25PC

P21

Commercial

25

CY7C191-25VC

V21

CY7C191-250C
CY7C191-25LC

Ordering Code

CY7C191-35PC

P21

CY7C191-35VC

V21

CY7C191-350C
CY7C191-35LC
CY7C191-350MB

022

CY7C191-35LMB

L54

CY7C192-35PC

P21

CY7C192-35VC

V21

022

CY7C192-350C

022

L54

CY7C192-35LC

L54

CY7C192-350MB

022

CY7C192-35LMB

L54

CY7C191-45PC

P21

CY7C191-45VC

V21

CY7C191-450C
CY7C191-45LC

Commercial

Ordering Code

35

Military

CY7C192-45PC

P21

CY7C1 92-45VC

V21

022

CY7C192-450C

022

L54

CY7C192-45LC

L54

CY7C1 92-450MB

022

CY7C192-45LMB

L54

CY7C191-450MB

022

CY7C191-45LMB

L54

Commercial

45

Military

2-226

COmmercial

Military
Commercial

Military

riA

PRELIMINAR Y

CY7C191
CY7C192

~~~UcrOR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

IOZ

1,2,3

los

1,2,3

IcC

1,2,3

ISBI

1,2,3

ISB2

1,2,3

fI

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACE

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAw

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tPWE

7,8,9,10,11

tso

7,8,9,10,11

tHO

7,8,9,10,11

tAWE[I]

7,8,9,10,11

tAOy[l]

7,8,9,10,11

Note:
1. 7Cl9l only.

Document #: 38-00076-A

2-227

PRELIMINARY

CYPRESS
SEMICONDUCTOR

65,536

CY7C194
CY7C196

4 Static R/W RAM

X

Features
• Automatic power·down when
deselected
• Output Enable (00) feature
(7C196)
• CMOS for optimum speed!
power
• High speed
- 25 ns tAA

• Low active power
-385mW
• Low standby power

-llOmW
• TTL compatible inputs and
outputs

• Capable of withstanding greater
than 2001V electrostatic
discharge

Functional Description
The CY7C194 and CY7C196 are high
performance CMOS static RAMs orga·
nized as 65,536 x 4 bits. Easy memory
expansion is provided by active LOW
chip enable(s) (CE on the CY7C194,
CEl, CE2 on the CY7C196) and threestate drivers. They have an automatic
power-down feature, reducing the power consumption by 71 % when deselected.
Writing to the device is accomplished
when the chip enable(s) (CE on the

CY7C194, CE" CE2 on the CY7C196)
and write enable (WE) inputs are both
LOW. Data on the four input pins
(1/00 through 1/03) is written into the
memory location, specified on the address pins (Ao through AIS).
Reading the device is accomplished by
taking the chip enable(s) (CE on the
CY7C194, CE" CE2 on the CY7C196)
LOW, while write enable (WE) remains HIGH. Under these conditions
the contents of the memory location
specified on the address pins will appear on the four data output pins. A
die coat is used to insure alpha immunity.

Pin Configurations

Logic Block Diagram

Vet;

Vet;

As

A.
A.
A2
A,

Ao
I/0.

21

I/0.

I/O,

1/°2

1/°0

I/O,
'/0.
WE

WE
1/0 3

0109-2

I-+H:>-l+..... '10,

Ne

CE2

A,.

1/°2

I-+--I:>-lr+-++-

..'.'..,
.

0109-3

1-+H:>-i:-4-- I/O,
I-+H:>-ll..--

'10.

...

'---r:=~==1~=~+~;;:;:::L'CE2(7C196ONLYI
 2001 V
(Per MIL-STD-883 Method 301S)

Storage Temperature ............... -6SoC to + ISO"C
Ambient Temperature with
Power Applied .................... - SsoC to + 12SoC

Latch-up Current .......................... > 200 rnA

Supply Voltage to Ground Potential .... -O.SV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to +7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial
Military!3]

Output Current into Outputs (Low) ............. 20 mA

Ambient
Temperature
O"Cto +70"C
- SSOC to + 12SOC

Vee
SV ±1O%
SV ±1O%

Electrical Characteristics Over Operating Range[4]
Parameters

Description

Test Conditions
Vee = Min.,IOH = -4.0mA
Vee = Min., IOL = 8.0 mA

los

Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short Circuit
Currentl1]

lee

Vee Operating
Supply Current

ISB!

Automatic CEI2]
Power Down Current

Commercial
Military
Commercial
Max. Vee, CE::: VIH
Min. Duty Cycle = 100% Military

ISB2

Automatic CE12]
Power Down Current

VOH
VOL
VIH
VIL
IIX
loz

GND:s; VI:S; Vee
GND :s; Vo :s; Vee, Output Disabled

7CI94-25
7CI94-35
7CI94-45
7CI96-25
7C196-35
7CI96-45 Units
Min. Max. Min. Max. Min. Max.
2.4
2.4
2.4
V
0.4
0.4
0.4
V
V
2.2 Vee 2.2 Vee 2.2 Vee
-3.0 0.8 -3.0 0.8 -3.0 0.8
V
-10 +10 -10 +10 -10 +10 /LA
-10 +10 -10 +10 -10 +10 /LA

Vee = Max., VOUT = GND
Vee = Max.
lOUT = o rnA

Max. Vee,
CE::: Vee - 0.3V
VIN ::: Vee -0.3Vor
VIN:S; 0.3V

Commercial

-350

-3S0

80

80
90
20
20

70
90
20
20

20

20

20

20

20
20

-3S0 rnA
rnA

rnA

rnA

Military

Capacitance [5]
Parameters
CIN
COUT

Description
Input Capacitance
Output Capacitance

Max.
5
7

Test Conditions
TA = 25°C, f = 1 MHz,
Vee = S.OV

Units
pF

Notes:
I. Not more than! output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the c:E input is required to keep the
device deselected during Vcc power-up, otherwise ISB will exceed
values given.

3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.
5. Tested initially and after any design or process changes that may
affect these parameters.

AC Test Loads and Waveforms
R148111

OUTPUT

0----1'----+

r
_

30PF
INCLUDING
JIG AND _

- SCOPE

~:5n

-

Figure la
Equivalent to:

3.0V----.~::_--_i..

R1481H

0----...,..11,,-,
OUTPUT 0--_----+
5v

5 v O-----"\M.--,

I

5pF

INCLUDING
_JIG AND
_
- SCOPE
-

GND
R2
255U

Figure Ib

THEVENIN EQUIVALENT
16m
OUTPUT O>------'·'Y~'Y~....- - - O 1.73 v

0109-6

2-229

0109-5
0109-4

Figure 2

fJI

Switching Characteristics Over Operating Range[4, 6)
Parameters

7CI94·25
7C196-25

Description

Min.

Max.

7CI94-35
7CI96-35

Min.

Max.

7CI94·45
7CI96-45
Min.

Units

Max.

READ CYCLE

tRc

Read Cycle Time

tAA

Address to Data Valid

25

toRA

Output Hold from Address Change

tACEl,AC~

CE LOW to Data Valid

tDOE

OE LOW to Data Valid
OE LOW to LOW Z

7Cl96

tLZOE
tHZOE

<:m HIGH to HIGH Z

7Cl96

tLZCEl,CE2
tHZCEl'C~

tpu

3

en LOW to LOW ZIS)
en HIGH to High ZI7, S]
en LOW to Power Up
en HIGH to Power Down

35

15

25

3

15

0

15

ns

30

ns

15

ns

ns
ns
15

35

ns
ns

0

0
25

ns

3

3
10

ns

45
3

3
15

tpD
WRITE CYCLE[9]

3

3

3

ns
45

35

25
7Cl96

45

35
25

45

ns

twc

Write Cycle Time

20

30

40

ns

tSCE

en LOW to Write End

20

30

35

ns

tAW

Address Set·up to Write End

20

25

35

ns

tRA

Address Hold from Write End

2

2

2

ns

tSA

Address Set·up to Write Start

0

0

0

ns
ns

tpWE

WE Pulse Width

20

25

35

tSD

Data Set·up to Write End

10

15

20

ns

tHO

Data Hold from Write End

0

0

0

ns

tLZWE

~ HIGH to LOW Z[S]

3

3

3

WE LOW to HIGH Z[7, s]
tHZWE
Notes:
6. Test conditions assume signal transition times of S ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IorJIOH and 30 pF load capacitance.
7. tHZCE and tHZWE are specified with CL = 5 pF as in Figure lb.
Transition is measured ± 500 mV from steady stste voltsge.
S. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.

0

10

0

10

0

ns
15

ns

9. The internal write time of the memory is defined by the overlap of
Clh LOW, CEz LOW and WE LOW. Both signals must be LOW to
initiate a write and either signal can terminate a write by going
HIGH. The dats input setup and hold timing should be referenced to
the rising edge of the signa1 that terminates the write.
10. WE is HIGH for read cycle.
I!. Device is continuousJLselected, CEI = VII/CEz = VIL.
(7CI96: OE = VII., CEz = VIL also.)
12. Address valid prior to or coincident with CEI and CEz transition
LOW.
13. 7Cl96 only: Dats I/O will be high impedance ifOE = VIH.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

-------*--

~----------------------_tRC-------------------------J~.

ADDRESS

DATA OUT

~

______~_______~_HA____~_A_~~-------------------------------------PREVIOUS DATA VALID

~

DATA VALID

0109-7

2-230

5'n~U~================================================================
.

PRELIMINAR Y

CY7C194
CY7C196

Switching Waveforms (Continued)
Read Cycle No.2 (Notes 10, 12)

FJ

'Re

~

.-

..,ftACE

~

~

(7C196)

C

tOOE

~'LZOEI
DATA OUT

",

HIGH IMPEDANCE

1

Vee _ _ _ _ _
SUPPLY
CURRENT

,

DATA VALID

I" " " " "

tLZCE

-'PU

'HZOE~

~tHZCE-

I---'po

HIGH
IMPEDANCE

-j

ICC

~ISB

50%

_

0109-8

Write Cycle No.1 2OO1V
Ambient Temperature with
(Per MIL-STD-883 Method 3015)
Power Applied .................... - 55°C to + 125°C
Latch-up Current .......................... > 200 mA
Supply Voltage to Ground Potential
Operating Range
(pin 24 to Pin 12) .................... -0.5Vto +7.0V
Ambient
DC Voltage Applied to Outputs
Range
Vee
Temperature
in High Z State ...................... -0.5V to +7.0V
Commercial
O"Cto +70"C
5V ±10%
DC Input Voltage ................... - 3.0V to + 7:0V
- SSOC to + 12S0C
Military141
SV ±1O%
Output Current into Outputs (Low) ............. 20 rnA

Electrical Characteristics Over Operating Range[5]
Parameters

Description

7C197-25

Test Conditions

Min.
VOH

Output HIGH Voltage

Vee = Min., IOH = -4.0 mA

VOL

Output LOW Voltage

Vee = Min.

I IOL =

I IOL =

Max.

2.4
Military

S.OmA

7C197-35
Min.

Max.

2.4

7C197-45
Min.

Units

Max.

2.4

0.4

V

0.4

0.4

V

12.0 mA Commercial

VIH

Input HIGH Voltage

2.2

Vcc

2.2

-3.0

-3.0

O.S

-3.0

Vee
O.S

V

Input LOW Voltage

Vee
O.S

2.2

VIL
IIX

Input Load Current

-10

+10

-10

+10

-10

+10

/LA

loz

Output Leakage Current GND ;:; Vo ;:; Vee, Output Disabled

-50

+50

-SO

+SO

-50

+50

/LA

los

Output Short Circuit
Currendll

Vee = Max., VOUT = GND

mA

Icc

Vee Operating
Supply Current

Vee = Max.
lOUT = OmA

ISBI

Automatic m12]
Power Down Current

Max. Vee,
CE~ VIH

ISB2

Automatic m121
Power Down Current

Max. Vee,
~ Vee - 0.3V,
VIN ~ Vee - 0.3Vor
VIN;:; 0.3V

GND;:; VI;:; Vee

Commercial

-3S0

-350

-350

70

70

60

SO

SO

Military
20

Commercial
Military

rn

Commercial

V

20

Military

20

20

20

20

20

20

20

20

mA
mA
mA

Capacitance [3]
Description

Parameters
CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions

Max.

TA=25°C,f= 1 MHz
Vee = 5.0V

5

Notes:
I. Not more than I output should be shorted at one time. Duration of
tbe sbort circuit sbould not exceed 30 seconds.
2. A pull-up resistor to Vcc on the CE input is required to keep tbe
device deselected during Vee power-up, otherwise ISB will exceed
values given.

3. Tested initially and after any design or process changes that may
affect these parameters.
4. TA is the "instant on" case temperature.
S. See the last page of this specification for Group A subgroup testing
information.

Rl 329!l
(480!l MILl

5vo---------~~,

5 Vo-----A,/'t,f'v--,

OUTPUT 0----.......------1

OUTPUT 0-----........- - - - -..

R2
INCLUDINGI30 pF
JIG AND

202 !l

SCOPE

INCLUDINGf
JIG AND

SCOPE

Figure la
Equivalent to:

J..
':"

GND

-os;;; 5 ns

"5 ns

0110-4

Figure 2

1670

. . ---.. .

Commercial

----i.

V-----..I....

0110-3

Figure Ib

THtVENIN EQUIVALENT
1250
OUTPUT o---~-~~.~·

3.0

R2
202 !l
(255!l MILl

5pF

(255!l MIL)

pF

7

AC Test Loads and Waveforms
Rl32911
(480!l MILl

Units

OUTPUT~1.73V

Military

0 1.90 V
0110-5

2-235

0110-6

til

Switching Characteristics Over Operating Range[5, 61
Parameters

7Cl97·25

Description

Min.

Max.

7Cl97·45

7Cl97·35
Min.

Max.

Min.

U ..its

Max.

READ CYCLE
tRC

25

Read Cycle Time

tAA

Address to Data Valid

tOHA

Output Hold from Address Change

tACE

CE LOW to Data Valid

tLZCE

CE LOW to Low Z!S]

3

tHZCE

CE HIGH to High Z!7, S]

0

tpu

CE LOW to Power Up

0

tpD

CE HIGH to Power Down

35
25

3

35

0
0

20

45
3

20

0

ns
ns

20

0
25

ns
ns

3

3
15

45

35
3

25

ns

45

ns
ns

30

ns

WRITE CYCLE!9]
twc

Write Cycle Time

25

35

45

ns

tSCE

CE LOW to Write End

20

tAW

Address Set-up to Write End

20

30

40

ns

30

40

tHA

Address Hold from Write End

ns

2

2

2

tSA

ns

Address Set-up to Write Start

0

0

0

ns

tpWE

WE Pulse Width

20

25

25

ns

tSD

Data Set-up to Write End

15

20

25

ns

tHD

Data Hold from Write End

0

0

0

ns

tLZWE

WE HIGH to Low Z!S]

0

0

0

WE LOW to High Z!7, S]

0

tHZWE
Notes:
6. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOr/IoH and 30 pF load capacitance.
7. tHzcE and tHZWE are specified with CL = 5 pF as in Figure lb.
Transition is measured ± 500 mV from steady state voltage.
S. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.

15

0

20

0

ns
20

ns

9. The internal write time of the memory is defmed by the overlap of

CE LOW and WE LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
10. wt! is HIGH for read cycle.
II. Device is continuously selected, <:::E = VIL.
12. Address valid prior to or coincident with CE transition LOW.

Switching Waveforms
Read Cycle No. 1[10,111

~t:~~----------------------~tRC--------------~----------~J.

~~~~~~~~to~_H-A~~~~_t-A_A~-~-!------.-'I-~~~~~~~~~~~~~~~~~~~~~~~_-_*__~~~~~~~~~~~~~~~~

ADDRESS ____
{
DATA OUT

PREVIOUS DATA VALID

~

DATA VALID
0110-7

2-236

~

PRELIMINARY

CY7C197

~~~DU~================================================================
Switching Waveforms

(Continued)

Read Cycle No. 2(11)
'Re

J

~
tACE

'LzeE~
HIGH IMPEDANCE

DATA OUT

I--',u
Vee

)

SUPPLY _ _ _ _ _ _
CURRENT
_

II

I

I" "

""

fI

,r.

.

~'HzeE1

I

DATA VALID

HIGH
IMPEDANCE

J

i---'PD

-----I

50%

5Q;t-

ICC
IS8

0110-8

Write Cycle No.1 (WE Controlled)[lO)
twe

---..
ADDRESS

~Il
~

---'
tSCE

\\ r\\~

jill) rll/////1L
tHA"--'

'AW

'PWE

'SA

.,Il

1\.\\

l

OATA IN

DATA OUT

tH:j

'SD

l

DATA-IN VALID

I---'HZWE~

!+--tLZWE

1,,_______

>
-----------------------------~

HIGH IMPEDANCE
)--...;.=...;.;.;;;....;.;.;..--~\

DATA UNDEFINED

0110-9

Write Cycle No.2 (CE Controlled)ltO)
twe
ADDRESS

~

-

)
tSCE

'SA

~r

J
'HA---O

'AW

IPWE

\\\ \ \ \ \ \ \ \\\ \ \~~
DATA IN

1
'I

V/ / / / / / / / / / / / /J
tSD

DATA-IN VALID

~'HZWE::::j

tH~,

~
HIGH IMPEDANCE

DATA OUT _ _ _ _ _ _ _ _D_A_T_A_U_N_D_EF_'N_E_D_ _ _ _ _

-'>~---------------------0110-10

Note: IfCIl goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state,

2-237

~

PRELIMINARY

CY7C197

~r~~===================
Truth Table
CE

WE

H

X

HighZ

L

H

DataOnt

Read

L

L

Data In

Write

InpntlOutputs

Mode
DeselectJPower Down

Ordering Information
Speed
(os)

25

35

45

Ordering Code

CY7C197-25PC

Operating

Package

Type

Range

P13

Commercial

CY7C197-25VC

V13

CY7C197-25DC

014

CY7C197-25LC

L54

CY7C197-35PC

P13

CY7C197-35VC

Vl3

CY7C197-35DC

014

CY7C197-35LC

L54

CY7C197-35DMB

D14

CY7C197-35LMB

L54

CY7C197-45PC

Pl3

CY7C197-45VC

V13

CY7C197-45DC

014

CY7C197-45LC

L54

CY7C197-45DMB

014

CY7C197-45LMB

L54

Commercial

Military
Commercial

Military

2-238

~

PRELIMINARY

CY7C197

~~~===================
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

Ioz

1,2,3

los

1,2,3

Icc

1,2,3

ISB!

1,2,3

ISB2

1,2,3

II

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tOHA

7,8,9,10,11

tACE

7,8,9,10,11

WRITE CYCLE

twc

7,8,9,10,11

tSCE

7,8,9,10,11

tAW

7,8,9,10,11

tHA

7,8,9,10,11

tSA

7,8,9,10,11

tpwE

7,8,9,10,11

tSD

7,8,9,10,11

tHO

7,8,9,10,11

Document "": 38-00078-A

2-239

CY7C198
CY7C199

PRELIMINARY

CYPRESS
SEMICONDUCTOR

32,768 x 8 Static R/W RAM

Features

Functional Description

• Automatic power-down when
deselected

The CY7C198 and CY7C199 are high
performance CMOS static RAMs organized as 32,768 words by 8 bits. Easy
memory expansion is provided by an
active LOW chip enable (CE) and active LOW output enable (OE) and
three-state drivers. Both devices have
an automatic power-down feature, reducing the power consumption by 80%
when deselected. The CY7Cl99 is in
the space saving 300 mil wide DIP
package and leadless chip carrier. The
CY7Cl98 is in the standard 600 mil
wide package.
An active LOW write enable signal
(WE) controls the writing/reading operation of the memory. When CE and
WE inputs are both LOW, data on

• CMOS for optimum speed!
power
•
•
•
•

High speed-35 ns
Low active power-S50 mW
Low standby power-ll0 mW
TTL compatible inputs and
outputs

• Capable of withstanding greater
than 2001V electrostatic
discharge

the eight data input/output pins (1/00
through 1/07) is written into the memory location addressed by the address
present on the address pins (Ao
through A14). Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while (WE) remains inactive or HIGH. Under these conditions,
the contents of the location addressed
by the information on address pins is
present on the eight data input/output
pins.
The input/output pins remain in a high
impedance state unless the chip is selected, outputs are enabled, and write
enable (WE) is HIGH. A die coat is
used to ensure alpha immunity.

Pin Configurations

Logic Block Diagram

GND

0111-2

~:t :t JlI~
'a
As

"D
'"
"2
Au

3
4

iITJ2827

2.

5

10

5E--o.....'
0111-1

'2

"

23
22 5E
21 ..
20 CE
1. 1/0.,
18 1/0,

',. •

1/0.
1/0,

'.

25 A3

2.

a

11

12

1314151617
NQ

1").

II)

~i§~~~

0111-11

Selection Guide
7C198-35
7Cl99-35
Maximum Access Time (ns)
Maximum Operating
Current (mA)

Commercial

Maximum Standby
Current (rnA)

Commercial

2-240

7C198-55
7Cl99-55

35

45

55

110

110

100

120

120

20/20

20/20

20/20

20/20

20/20

Military
Military

7C198-45
7Cl99-45

1M~mu~===================================================================
.

PRELIMINAR Y

CY7C198
CY7C199

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ......... , ..... -65°C to + 150"C
Static Discharge Voltage ..................... >2001V
Ambient Temperature with
(Per MIL-STD-883 Method 3015)
Latch-up Current .......................... > 200 rnA
Power Applied .................... - 55°C to + 125°C
Supply Voltage to Ground Potential
Operating
Range
(pin 28 to Pin 14) .................... -0.5V to + 7.0V
Ambient
DC Voltage Applied to Outputs
Range
Vee
Temperature
in High Z State ...................... -0.5V to +7.0V
+70"C
SV
±10%
Commercial
O"Cto
DC Input Voltage ................... -3.0V to +7.0V
Military
(3)
SsoC
to
+
12SoC
SV
±IO%
Output Current into Outputs (Low) ............. 20 rnA

Electrical Characteristics Over Operating Range l4]
Description

Parameters

Test Conditions

Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current

VOH
VOL
VIH
VIL
IIX

Vee = Min., IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA

los

GND,,; VI"; Vee
GND";
VI"; Vee
Output Leakage CUrrent
Output Disabled
Output Short Circuit
Vee = Max., VOUT = GND
CUrrent!!]

lee

Vee Operating
Supply CUrrent

Vee = Max.
lOUT = ornA

IISBI

Automatic CE
Power Down Current

Max. Vee,
CE ~ VIH,
Min. Duty
Cycle = 100%

Automatic CE
Power Down Current

Max. Vee,
Commercial
CE ~ Vee - 0.3V,
VIN ~ Vee - 0.3Vor
Military
VIN"; 0.3V

Ioz

ISB2

7C198-35
7C199-35
Min. Max.
2.4
0.4
2.2
Vee
-3.0 0.8
-10
10

7C198-45
7C199-45
Min. Max.
2.4
0.4
2.2
Vee
-3.0 0.8
-10
10

7C198-55
7C199-55
Min. Max.
2.4
0.4
2.2
Vee
-3.0 0.8
-10 +10

-10

-10

-10

+10

+10

Units
V
V
V
V
/LA

+10

/LA

-300

-300

-300

rnA

Commercial
Military

110

110
120

100
120

rnA

Commercial

20

20

20

20

20

20

20

20

20

rnA
Military
20

rnA

Capacitance [2]
DeSCription
Input Capacitance
Output Capacitance

Parameters
CIN
CoUT

Test Conditions
TA = 2SoC, f = 1 MHz
Vee = S.OV

Notes:
I. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested iuitially and after any design or process changes that may
affect these parameters.

Max.
S
7

Units
pF

3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

AC Test Loads and Waveforms
RI481n

6v

0----_'1.-...,

..,.
..,.
3'DV~

OU~UTo--_----+

OUTPUT 0 - - _ - - - - +

I

5pF
INCLUDING
_JIG AND
_

- SCOPE

0111-3

Figure 1a
Equivalent to:

All Input Pulses

RI481n

6 v o---~W'l.-...,

~n

GND

THEVENIN EQUIVALENT
16m
OUTPUT O~-~·\J~\J"'I0-.---O 1.73V

0111-6

2-241

,""

s;;5ns

0111-5

-

0111-4

Figure 1b

t.--

10%

:S:5na

Figure 2

fill

Q"
.

CY7C198
CY7C199

PRELIMINARY

~~~======================================================

Switching Characteristics Over Operating Range[4, 5)
Parameters

7C198·35
7Cl99·35

Description

7C198·45
7Cl99·45

Max.

Min.

Min.

Max.

7C198·55
7C199·55

Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

35

tOHA

Data Hold from Address Change

tACE

CE LOW to Data Valid

tOOE

OE LOW to Data Valid

tLZOE

OE LOW to Low Z

tHZOE

OE HIGH to High Z(6)
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]

tLZCE
tHZCE
tpu
tpD

45
35

3

3

3

3

3
25

15
0

3

0
20

0
25

ns
ns
ns

20

20

ns

ns

30

3

3

ns
ns

55
25

45
20

20

ns

55

3
35
20

CE LOW to Power Up
CE HIGH to Power Down

55
45

ns
ns

25

ns

WRITE CYCLE[S]
twc

Write Cycle Time

tSCE

CE LOW to Write End

tAW

Address Set·up to Write End

tHA

Address Hold from Write End

tSA

Address Set·up to Write Start

tpwE

WE Pulse Width

tSD

Data Set·up to Write End

tHD

Data Hold from Write End

tHZWE

WE LOW to High Z[6]

tLZWE

WI! HIGH to Low Z

35
30
30
2
0
20
15
0

45

50
50
50
2
0
30
25
0

40
40

2
0
25
20
0
15

ns
ns

ns
ns
ns
ns
ns

25

20
3

3

ns

3

ns
ns

Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V and output loading
of the specified lor/lOR and 30 pF load capacitance.
6. tHZOE, IHzcE and tHZWE are specified with CL = 5 pF as in Figure
1h. Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
8. The internal write time of the memory is defined by the overlap of
rn WW and WE WW. Both signals must be WW to initiate a

9.
10.
II.

12.

write and either signal can terminate a write by going HIGH. The
data input setup and hold timing should be referenced to the rising
edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected. 00, CE = VIL.
Address valid prior to or coincident with CE transition WW.
Data I/O is high impedance if 00 = VIR.

Switching Waveforms
Read Cycle No.1 (Notes 10, 11)

-----,J;~~------------------------t"C--------------------------:1~.

ADDR~~~~ ~~-H_A~~~~-~A--~-!----------'-!-,~~~~~~~~~~~~~~~~~~~~~~~~_~~~~~~~~~~~~~~~~~
_____

DATA OUT

_____________

PREVIOUS DATA VALID

____

__

~

DATA VALID
0111-7

2~242

&n~~=============================================================
.

PRELIMINARY

Switching Waveforms

CY7C198
CY7C199

(Continued)

Read Cycle No.2 (Notes 9, 11)

til

t RC
~

tACE

-II - - - tOOE -

t HZOE -

t LZOE

t HZCE 1 -

HIGH
IMPEDANCE

DATA OUT

DATA VALID

HIGH
IMPEDANCE

- tLZCE ,-- tpu
Vee
)
SUPPLY _ _ _ _~

~tpo

50%

:t:

50%

CURRENT

ICC
ISB
0111-8

Write Cycle No.1 2001 V
Storage Temperature ............... -65·Cto +150"C
(per MIL-STD-883 Method 3015)
Ambient Temperature with
Power applied ..................... - 55·C to + 125·C
Latchup Current .......................... > 200 rnA
Supply Voltage to Ground Potential
(Pin 16 to 8) ........................ -0.5V to +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ..................... , -0.5V to + 7.0V

Range

Commercial
Military [51

DC Input Voltage ................... -3.0Vto +7.0V
Output Current, into Outputs (Low) ............. 20 rnA

Ambient
Temperature
O"Cto +70"C
- SS·C to + 12S·C

Vee
5V ±1O%
SV ±10%

Electrical Characteristics Over the Operating Range[6]
748189,

Parameters

Description

Test Conditions

27S03, 27S07
Min.

VOH

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee
Vee

= Min.,loH = -S.2mA
= Min., IOL = 16.0mA
= Min., IOL = 8.0 mA

Max.

2.4

27LS03
Min.

Units

Max.

2.4

V

0.45

V
0.45

V

VIH

Input HIGH Voltage

2.0

Input LOW Voltage

-3.0

Vee
0.8

-3.0

Vee
0.8

V

VIL
IIX

Input Leakage Current

-10

+10

-10

+10

/-LA

-40

+40

-40

+40

-90

/-LA
mA

38

rnA

VeD

\

GND~

~

VI

Vee

V

Input Diode Clamp VoltageU]
~

~

Output Leakage Current

GND

los

Output Short Circuit Current [2]

lee

Power Supply Current

= Max., VOUT = GND
I Commercial
Vee = Max.,
lOUT = OmA
1Military

loz

2.0

\

\

Vo

Vee

Vee

-90
90

mA

100

Capacitance [4]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions
TA = 25·C, f
Vee = 5.0V

=

I MHz

Max.
4
7

Units

pF

Notes:
1. The eMOS process does not provide a clamp diode. However these
devices are insensitive to - 3V dc input levels and - SV undershoot
pulses oftess than 5 ns (measured at 50% points).
2. Not more than I output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
3. Output is precoditioned to data in (inverted or non-inverted) during
write to insure correct data is present on all outputs when write is
terminated. (No write recovery glitch.)

4. Tested initially and after any design or process changes that may
affect these parameters.
5. TA is the "instant on" case temperature.
6. See the last page of this specification for Group A subgroup testing
information.

2-247

II

. .
(;n

CY74S189, CY27LS03
CY27S03,CY27S07

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Switching Characteristics Over the Operating Range[6, 71
Parameters

27S03A
27S07A

Description

Min.

27S03
27S07

Max.

Min.

74S189

Max.

Min.

27LS03

Max.

MIn.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid[lO]

25

35

35

65

ns

tACS

CS Low to Data Valid[JO]

15

17

22

35

ns

tHZCS

CS HIGH to High Z[9, 11, 12]

15

20

17

35

ns

25

35

35

65

ns

WRITE CYCLE[3, 7, 81
twc

Write Cycle Time

25

35

35

65

ns

tSA

Address Set-up to Write Start

0

0

0

0

ns

tHA

Address Hold from Write End

0

0

0

0

tscs

~ Set-up to Write Start

ns

0

ns

tHCS

~ Hold from Write End

tSD

Data Set-up to Write End

20

25

20

55

ns

tHD

Data Hold from Write End

0

0

0

0

ns

tpWE

WE Pulse Width

20

tHZWE

WE LOW to High Z[9, 11, 121
WE HIGH to Output Valid[lO]

0

25

ns

20

55

ns

20

25

20

35

ns

20
tAWE
Notes:
7. Test conditions assume signal transition times of5 us or less, timing
reference levels of 1.5V, output loading of the specified IOrJIOH and
30 pF load capacitance.
8. The internal write time of the memory is defined by the overlap of
LOW and WE LOW. Both signals must be LOW to intiate a write
and either signal can terminate a write by going HIGH. The data
input setup and hold timing should be referenced to the rising edge of
the signal that terminates the write.

35

30

35

ns

9. Transition is measured at steady state HIGH level -500 mY or
steady state LOW level + 500 m V on the output from 1.5V level on
the input.
10. tAA, tACS and tAWE are tested with CL = 30 pF as in Figure lao
Timing is referenced to 1.5V on the inputs and outputs.
11. tHZCS and tHZWE are tested with CL = 5 pF as in Figure 1h.
12. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.

es

BitMap

Address Designators

~------------COLUMN
~------------OUTPUTS

ROW 0

ROW 3

0006-9

2-248

Address
Name

Address
Function

Pin
Number

Ao

AXO

I

AI

AXI

15

A2

AYO

14

A3

AYI

13

&n
.

CY74S189, CY27LS03
CY27S03, CY27S07

~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

AC Test Loads and Waveforms
ALL INPUT PULSES
Rl2380

Rl2380

5 v o-----'lNIr-.....

3.0

----+

OUTPUT 0 - - -.....

I

OUTPUT

fI

O---.....- - - - i
GND----"I

R2

30pF

I

150!!

,NCLUD,NG
JIG AND

":::' SCOPE

v----:lr:=---"'!L

_

":::'

~6

R2

5pF

n5

.;;;5n5

150!!

0006-6

INCLUDING
JIG AND _

- SCOPE

0006-4

Figure la
Equivalent to:

Figure Ib

THEVENIN EQUIVALENT

VV\

OUTPUT 0

01.92V

9211

0006-5

Read Mode

~----'RC-------j~.

AD~~~~

~

___

-------*~---------C

-

.,1

cs
CHIP SELECT
DATA ____________________
OUTPUTS
00-03

~----~~~~-----------,~~~~------_t------~~~--------NOTE 7

0006-7

Write Mode

JI+-----

_-------I~-

-_tw_c-

AO-A3
ADDRESS

CS
CHIP SELECT

--

tsA

I--

tscs

I+-

_"'A

-'Hes

tSD

4-

00-0 3
DATA IN
I

WE
WRITE ENABLE

-'IrI,

",.::.I

I

'PWE

..,f-

j~

NOTE 6

"'ZWE

00-03 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~'AWE

-~

DATA OUTPUTS
LOAD

LNOTE6

0006-8

(All above measurements referenced to 1.5V)
Note: Timing diagram represents one solution which results in optimum cycle time. Timing may be changed in various applications as long as the worst
case limits are not violated.

2-249

~

CY74S189, CY27LS03

..,;-~================================CY==2=7=SO=3=,=CY==27~S==07
Ordering Information
Speed
(os)

25

35

65

Package
Type

Operating
Range

CY27S03APC
CY27S07APC

PI

Commercial

CY27S03AOC
CY27S07AOC

02

CY27S03ALMB
CY27S07ALMB

L61

CY27S03AOMB
CY27S07AOMB

02

CY27S03PC
CY27S07PC
CY74SI 89PC

PI

CY27S030C
CY27S070C
CY74S1890C

02

CY27S03LC
CY27S07LC

L61

CY27S03LMB
CY27S07LMB

L61

CY27S030MB
CY27S07DMB

02

CY27LS03LMB

L61

CY27LS030MB

02

Ordering Code

Military

Commercial

Military

Military

2-250

&n

• CY!'RF.$

SEMICONDUCTOR

CY74S189, CY27LS03
CY27S03, CY27S07

===========~~~~~

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX
Ioz
Icc

1,2,3

II

1,2,3
1,2,3

Switching Characteristics
Parameters

Subgroups

READ CYCLE
tRC

7,8,9,10,11

tAA

7,8,9,10,11

tACS

7,8,9,10,11

WRITE CYCLE
twc

7,8,9,10,11

tSA

7,8,9,10,11

tHA

7,8,9,10,11

tscs

7,8,9,10,11

tHCS

7,8,9,10,11

tSD

7,8,9,10,11

tHD

7,8,9,10,11

tpWE

7,8,9,10,11

tAwE

7,8,9,10,11

Document #: 38-00041-C

2-251

CY93422A/93L422A
CY93422/93L422

CYPRESS
SEMICONDUCTOR

256

Features

Functional Description

• 256 x 4 static RAM for control
stores in high speed computer

The CY93422 is a high performance
CMOS static RAM organized as
256 x 4 bits. Easy memory expansion is
provided by an active LOW chip select
one (CS,) input, an active HIGH chip
select two (CS2) input, and three-state
outputs.
An active LOW write enable input
(WE) controls the writing/reading operation ofthe memory. When the ~
select one (CS,) and write enable (WE)
inputs are LOW and the chip select
two (CS2) input is HIGH, the information on the four data inputs Do to D3 is
written into the addressed memory
word and the output circuitry is preconditioned so that the correct data is
present at the outputs when the write
cycle is complete. This preconditioning

• Processed with high speed
CMOS for optimum
speed/power
• Separate inputs and outputs
• Low power
- Standard power:
660 mW (commercial)
715 mW (military)
- Low power:
440 mW (commercial)
495 mW (military)
• 5 volt power supply ± 10%
tolerance both commercial and
military
• Capable of withstanding greater
than 2001V static discharge

Logic Block Diagram

X

4 Static R/W RAM
operation insures minimum write recovery times by eliminating the "write
recovery glitch."
Reading is performed with the chip select one (CS,) input LOW, the chip select two input (CS2) and write enable
(WE) inputs HIGH, and the output euable input (OE) LOW. The information
stored in the addressed word is read
out on the four non-inverting outputs
00 to 03.
The outputs of the memory go to an
active high impedance state whenever
chip select one (CS,) is HIGH, chip select two (CS2) is LOW, output enable
(OE) is HIGH, or during the writing
operation when write enable (WE) is
LOW.

Pin Configurations

03
03

Ao

0,

A,

0,

A2
A3

0002-2

A.

-eN)

~ ~~..t

3 iEJ2827
4
26
5
25
24
Ao 6
As 7
23
A6 8
22
A7 9
21
Ne 10
20
19
Ne 11
18
Ne 12
1314151617
A2
A,

A.

A.
A7

0002-1

WE

CS,

OE
eS2
0,
0,
°2
02
°1

~i88Q

"

0002-8

Selection Guide (For higher performance and lower power refer to CY7Cl22 data sheet)
Maximum Access Time (ns)
Maximum Operating Current (mA)

93422A
35
45
120
130

Commercial
Military
Commercial
Military
2-252

93IA22A
45
55
80
90

93422
45
60
120
130

93IA22
60

75
80
90

(;n
.

CY93422A/93L422A
CY93422/93L422

~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Maximum Ratings
Function Table

(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 22 to Pin 8) ..................... -0.5V to + 7.0V
DC Voltage Applied to Outputs
for High Output State .............. -0.5V to Vee Max
DC Input Voltage ................... -O.5V to + 5.5V
Output Current, into Outputs (Low) ............. 20 mA
DC Input Current ............... - 30 mA to + 5.0 mA
Static Discharge Voltage ..................... > 200 I V
(per MIL-STD-883 Method 3015)
Latchup Current .......................... > 200 mA

Inputs

Outputs

Mode

CSz

CSl

WE

OE

Dn

On

L

X

X

X

X

*HIGHZ

Not Select

X

H

X

X

X

*HIGHZ

Not Select

H

L

H

H

X

*HIGHZ

Output Disable

X

Selected
Data

Read Data

H

L

H

L

H

L

L

X

L

*HIGHZ

Write "0"

H

L

L

X

H

°HIGHZ

Write "I"

H = High Voltage Level L = Low Voltage Level
X = Don't eare
"HIGH Z implies outputs are disabled or off. This condition is defmed
as a high impedance state for the eY93422.

Operating Range
Range

Vee

Commercial
Military [6]

5V ±1O%

5V ±1O%

Ambient
Temperature
O"C to + 75°C
- 55°C to + 125°C

DC Electrical Characteristics Over Operating Range[5]
Parameters

Description

93422
93422A

Test Conditions

Min.
VOH

Output HIGH Voltage

Vee = Min.,
VIN = VIH or VIL

IOH

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIH or VIL

IOL = S.OmA

VIH

Input HIGH Level U]

Guaranteed Input Logical HIGH
Voltage for all Inputs

VIL

Input LOW Level U]

Guaranteed Input Logical LOW
Voltage for all Inputs

hL

Input LOW Current

Vee = Max., VIN = 0.4OV

IIH

Input HIGH Current

Vee

Ise

Output Short
Circuit Current

Vee = Max., VOUT

lee

Power Supply Current

All Inputs = GND,
Vee = Max.

VeL

Input Clamp Voltage

IcEX

Output Leakage Current

= Max., VIN

=

-5.2mA

2.4

Min.

2.1

= 4.SV

= 0.OV[2]

0.4S
2.1

V
V

O.S

O.S

V

-300

-300

p.A

40

40

p.A

-90

-90

mA

110

70

= 7SoC
TA = O"C

110

70

120

SO

130

90

See Note 4

See Note 4

50

VOUT = 2.4V

= O.SV, Vee = Max.

V

TA = 125°C
TA

Units

Max.

2.4
0.45

TA = -S5°C

VOUT

Max.

93IA22
93IA22A

-SO

50
-SO

mA

p.A

CIN

Input Pin Capacitance

See Note 3

4

4

pF

COUT

Output Pin Capacitance

See Note 3

7

7

pF

Notes:
I. These are absolute voltages with respect to device ground pin and
include all overshoots due to system andlor tester noise. Do not at-

4. The eMOS process does not provide a clamp diode. However, the
eY93422 is insensitive to - 3V dc input levels and - 5V undershoot
pulses ofIess than 10 ns (measured at 50% point).
5. See the last page of this specification for Group A subgroup testing
information.

tempt to test these values without suitable equipment.
2. Not more than one output should be shorted at a time. Duration of
the short circuit should not be more than one second.
3. Tested initially and after any design or process changes that may
affect these parameters.

6. TA is the "instant on" case temperature.

2-253

fI

&n~==============================~===

CY93422A193L422A
CY93422/93L422

.

Commercial Switching Characteristics vcc
Parameters

=

sv ± 10%, TA

Description

93422A
Min.

Max.

= O"C to +7SoC (Unless Otherwise Noted)

93422

93L422A

Min.

Max.

Min.

Max.

93L422

Min.

Max.

Units

tPLH(A)II)
tPHL(A)U)

Delay from Address to Output
(Address Access Time) (See Figure 2)

35

45

45

60

ns

tPZH (CSt. CS2)
tPZL (CSI, CS2)

Delay from Chip Select to Active
Output and Correct Data (See Figure 2)

25

30

30

35

ns

tPZH(Wn)
tPZL(WE)

Delay from Write Enable to
Active Output and Correct Data
(Write Recovery) (See Figure 1)

25

40

40

45

ns

tPZH(OIl)
tPZL(OE)

Delay from Output Enable to Active
Output and Correct Data (See Figure 2)

25

30

30

35

ns

10 (A)

Setup Time Address (prior to
Initiation of Write) (See Figure 1)

5

5

10

10

ns

th (A)

Hold Time Address (After
Termination of Write) (See Figure 1)

5

5

5

5

ns

10 (OJ)

Setup Time Data Input (prior to
Initiation of Write) (See Figure 1)

5

5

5

5

ns

th (OJ)

Hold Time Data Input (After
Termination of Write) (See Figure 1)

5

5

5

5

ns

10 (CSt. CS2)

Setup Time Chip Select (Prior to
Initiation of Write) (See Figure 1)

5

5

5

5

ns

th (CSt. CS2)

Hold Time Chip Select (After
Termination of Write) (See Figure 1)

5

5

5

5

ns

tpw(WE)

Minimum Write Enable Pulse Width
to Insure Write (See Figure 1)

20

40

30

45

ns

tpHZ (CSI, CS2)
tpLZ (CS 1. CS2)

Delay from Chip Select to Inactive
Output (HIGH Z) (See Figure 2)

30

40

30

45

ns

tPHZ(WE)
tPLZ(WE)

Delay from Write Enable to Inactive
Output (HIGH Z) (See Figure 1)

30

40

35

45

ns

Delay from Output Enable to Inactive
Output (HIGH Z) (See Figure 2)

30

40

30

45

ns

tPHz(OE)
tpLz(OE)
Notes:

timing referenced to 1.5V. tpHZ (WE), tPHZ ---'"
SI

3.0V
Rl

soon

10%

GND
OUTPUT

<10nl

0 - - - -.....- - -.....
3.0V

90%

R2

1200n
GND

-=

0002-7
0002-6

Figure 4

Figure 3
See Notes I and 2 of Switching Characteristics

2-256

5n
.

CY93422A/93L422A
CY93422/93L422

~~============================================================~

Ordering Information
Ordering Code

Speed
(ns)

Std. Power

35

CY93422APC
CY93422AOC
CY93422ALC

45

CY93422PC
CY934220C
CY93422LC

Package
Type

Operating
Range

P7
08
L54

Commercial

P7
08
L54

Commercial

08
L54

Military

08
L54

Military

08
L54

Military

CY93L422PC
CY93L4220C
CY93L422LC

P7
08
L54

Commercial

CY93L4220MB
CY93L422LMB

08
L54

Military

Low Power

CY93L422APC
CY93L422AOC
CY93L422ALC

CY93422AOMB
CY93422ALMB
55

60

75

CY93L422AOMB
CY93L422ALMB
CY934220MB
CY93422LMB

2-257

til

5n

CY93422A/93L422A
CY93422/93L422

• CYPRESS

~IOO~U~R~~~~~~~~~~~~~~~~~~~~~~~====~~~~~

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

VILMax.

1,2,3

IlL

1,2,3

IIR

1,2,3

Icc

1,2,3

ICEX

1,2,3

Switching Characteristics
Parameters

Subgroups

tPLH(A)

7,8,9,10,11

tpHL(A)

7,8,9,10,11

tPZH (CS t,CS2)

7,8,9,10,11

tpzL (CSt,CS2)

7,8,9,10,11

tpZH(WE)

7,8,9,10,11

tpZL(WE)

7,8,9,10,11

tPZH(OE)

7,8,9,10,11

tpZL(OE)

7,8,9,10,11

ts(A)

7,8,9,10,11

th (A)

7,8,9,10,11

ts (DI)

7,8,9,10,11

th (DI)

7,8,9,10,11

ts (CSt. CS2)

7,8,9,10,11

th (CSt, CS2)

7,8,9,10,11

tpw(WE)

7,8,9,10,11

Document #: 38-00022-C

2-258

CYM1420

PRELIMINARY

CYPRESS
SEMICONDUCTOR

128K X 8 Static RAM
Module

Features

Functional Description

• High-density 1 Megabit SRAM Module
• High speed CMOS SRAMs
- Access time - 45 ns
• 32 pin - 0.6 in. wide DIP package
• JEDEC compatible pin-out
• Low active power - 1.2 W (max)
• Hermetic SMD Technology
• TTL compatible inputs and outputs
• Commercial and Military
Temperature Ranges
• 2 V data retention (L version)

The CYMI420 is a very high performance
1 Megabit Static RAM module organized
as 128K words by 8 bits. The module is
constructed using four 32K x 8 Static
RAMs in Leadless Chip Carriers mounted
onto a double sided multilayer ceramic
substrate. A decoder is used to interpret
the higher order addresses A,. and A,.
and select one of the four RAMs.
Writing to the memory module is accomplished when the chip select (CS) and
write enable (WE) inputs are both WW.
Data on the eight input/output pins (110.

Logic Block Diagram

through 1/07) is Mitten into the memory
location specified on the address pins (Ao
through A,.). Reading the device is
accomplished by taking chip select (CS),
and output enable (OE) WW, while Mite
enable (WE) remains inactive or HIGH.
Under these conditions, the contents of
the memory location specified on the
address pins will appear on the eight data
input/output pins.
The input/output pins remain in a high
impedance state unless the module is
selected, outputs are enabled, and write
enable (WE) is HIGH.

Pin Configuration
NC

AO-A'4--~~'5~-------------'------------'

Vee

A,e
A'4
A'2
A7
Ae
A5
A4
A3
A2
A,
Ao

~----------------~~-------,
~-------------,,r+------.

A'5
NC

WE
A'3
As
Ag
A"

m-

A,o

~

1/07

1/0 6
1/0 5

1100

A'B

lID,
1/0 2
GND

10f4
Decoder

1/04

1/0 3

DIP

1/00 -1/0 7

'42().2

'420·'

Selection Guide
1420HD-45
Maximum Access time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)

Commercial
Military
Commercial
Military

2-259

1420HD-55

45

55

210
210
80
80

210
210
80
80

II

fiA~NDlK:TOR

PRELIMINARY

CYM14~O

Operating Range

Maximum Ratings
(Above which the usefullife may be impaired)

Range

Ambient
Temperature

Vee

Commercial

O°C to +70°C

SV ± 10%

Storage Temperature ..................... -65°C to + 150°C
Ambient Temperature with
Power Applied ......................... -55°C to + 125°C

Military

-55°C to

+ 125°C

5V ± 10%

Supply Voltage to Ground Potential. . . . . . . .. -O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State.. .. .. .. .. .. .. .. .. .. .. .. ... -O.SV to + 7.0V
DC Input Voltage ........................ -O.5V to

+ 7.0V

Output Current into Outputs (Low) .................. 20 rnA

Electrical Characteristics
Parameters

Over Operating Range

Description

CYM1420HD

Test Conditions

Min.
2.4

VOH

Output HIGH Voltage

Vee = Min., IOH = -4.0 rnA

\bL

Output LOW Voltage

Vee = Min., IoL = 8.0 rnA

\iH

Input HIGH Voltage

22

\iL

Input LOW Voltage

-0.5

IIX

Input Load Current

loz

Output Leakage Current

los

Output Short Circuit
Current I!)
Vee Operating
Supply Current
Automatic CS [2)
Power Down Current

Ice
IsB!

Automatic CS [2)
Power Down Current

IsB2

Units
Max.
V
0.4

V

Vee
0.8

V

GND S; \l S; \te

-15

+15

j.LA

GND S; Va S; \te, Output Disabled

-15

+15

j.LA

Vee = Max., VOUT = GND

-300

rnA

~e = Max., lOUT = 0 rnA
CS = VIL

210

rnA

Max. Vee, CS : 2OO1V
(per MJL.STD-883 Method 3015.2)

Ambient Temperature with
Power Applied ......................... -55°C to + 12SoC

Latch-up Current ............................... >200 rnA

Supply Voltage to Ground Potential. . . . . . . .. -O.sV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -O.sV to + 7.0V
DC Input Voltage ........................ -3.0V to + 7.0V
Output Current into Outputs (Low) .................. 20 rnA

Range

Ambient
Temperature

Vee

Commercial

O°C to +70°C

SV ± 10%

-55°C to + 125°C

5V ± 10%

Military

Electrical Characteristics Over Operating Range
Parameters

CYM1610HD

Test Conditions

Description

Min.
'bH

Output HIGH Voltage

Vee = Min., IOH = -4.0 rnA

'bL
\fH

Output WW Voltage

Vee = Min., IOL = 8.0 rnA

Input HIGH Voltage

2.2

\fL
IIX

Input WWVoltage
Input Load Current

loz

Units

Max.

2.4

V
0.4

V
V

-3.0

Vee
0.8

GND S; \f S; \tc

-15

+15

Output Leakage Current

GND S; Vo S; \te, Output Disabled

-15

+15

J.IA
J.IA

los

Output Short Circuit
Current[!J

Vee = Max., VOUT = GND

-350

rnA

IcCx16

Vee Operating
Supply Current

Vee = Max., lOUT = 0 rnA
CS, VB, & LB = VIL

330

rnA

Vee = Max., lOUT = 0 rnA
CS = VIL, VB or LB = VIL

200

rnA

IsB!

Vee Operating
Supply Current
Automatic CS [2J
Power Down Current

Max. Vee, CS ~ VIH,
Min. Duty Cycle = 100%

80

rnA

IsB2

Automatic CS [2J
Power Down Current

Max. Vee, CS ~ \te - O.3V,
VIN ~ \te - O.3V or
VIN S; 0.3V

80

rnA

IcCx8

V

Capacitance[3J
Parameters

Description

Test Conditions

Max.

CIN

Input Capacitance

TA = 2SoC, f = 1 MHz,

35

CoUT

Output Capacitance

\te = s.OV

40

Notes:
1. Not more than 1 output should be shorted atone time. Duration ofthe
short circuit should not exceed 30 seconds.
2. A pull-up resistor to 'Cc on the eE input is required to keep the device

Units
pF

deselected during 'Cc power-up, otherwise ISB will exceed values
given.
3. Tested on a sample basis.

AC Test Loads and Waveforms
R1 4810

5V~
. .I 30 pF 2550

OUTPUT

5V~
.I 5PF ~550

[NCLUD[NG
JIG AND
SCOPE

--

--

INCLUDING
JIG AND
SCOPE

--

1670
o---------wv--o

1.73V

1610·5

GND

---"I
S;5 ns

Figure 2

THEVENIN EQUIVALENT

OUTPUT

90%

1610·3

Figure Ib

Figure la
Equivalent to:

3.OV----

OUTPUT

R2

--

All Input Pulses

R1 4810

2-288

1610·4

~"~ICONDUcrOR
PRF5S
•

CYM1610

Switching Characteristics
Parameters

Over Operating Range [41

Oescription

1610HO-25
Min.

Max.

1610HO-35
Min.

Max.

1610HO-45
Min.

Max.

1610H0-50
Min.

Units

Max.

READ CYCLE

25

45

lRc

Read Cycle Time

tAA

Address to Data Valid

tORA

Data Hold from Address Change

tACS

CS LOW to Data Valid

25

35

45

50

tOOE

OE LOW to Data Valid

15

20

25

30

tlZOE

m! LOW to LOW Z

tHZOE

OE HIGH to HIGH Z

tlZes

CS LOW to Low Z

tHZes

CS HIGH to High Z [5,61

tpu

CS LOW to Power Up

tpo

CS HIGH to Power Down

[61

35

25

45

35
5

5

5

5

5
5

10
0

0

25

50

15

0

20

ns
ns
ns

20
0

40

35

ns
ns

5
15

ns
ns

5

5
15

ns

5

5

15

15
5

50

ns
ns

50

ns

WRITE CYCLE [71

twc

Write Cycle Time

20

25

35

45

ns

tses

CS LOW to Write End

45

ns

Address Set-up to Write End

30

40

ns

tRA

Address Hold from Write End

25
25
2

35

tAW

22
22
2

2

2

ns

tSA

Address Set-up to Write Start

2

2

2

2

ns

tpWE

WE Pulse Width

20

25

30

30

ns

tso

Data Set-up to Write End

13

15

15

20

ns

tHO

Data Hold from Write End

3

3

5

5

ns

tlZWE

WE HIGH to Low Z[61

3

5

5

5

tHZWE

WE LOW to High Z[5, 61

0

7

0

12

0

12

0

ns

15

ns

Notes:

4. Test conditions assume signal transition times of 5 os or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V and output loading
of the specified lodloH and 30 pF load capacitance.
5. t HZCS and tHZWE are specified with CL = 5 pF as in Figure lb.
Transition is measured ±SOO mV from steady state voltage.
6. At any given temperature and voltage condition, t HZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.

7. The internal write time of the memory is defmed by the overlap oft::s
LOW and WELOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
S. WE is HIGH for read cycle.
9. Device is continuously selected, ~ = \'IL and Oil = \'IL'
10. Address valid prior to or coincident with 'CS'transition low.
11. Data I/O will be high impedance if OE = VIH

2-289

II

~PR£SS
~nEMICONDUCTOR

CYM1610

Data RetentIon CharacterlstIcs (L Version Only
Parameter

Vee for Retention Data

ICCDR

Data Retention Current

tcDR[13]

Chip Deselect to Data Retention Time
Operation Recovery Time

IU[13]

Input Leakage Current

Min.

Max.

20

\DR

tR[13]

CYM1610

Test Conditions

Description

V

4

\tc = 20V,
CS ~ Vee- 0.2V
\iN ~ \t::C - 0.2V
or\iN:S: 0.2V

Units

rnA

ns

0

ns

tRC[12]

8

IlA

Notes:
12.

tRC

= Read Cyc[e Time.

13. Guaranteed, not tested.

Data Retention Waveform

:J:

DATA RETENT[ON MODE

:):

tc:t. .__4_'5_v~~ _---:-:-:-~-----I'~~:::l
IZZZZ7ffv'H
4 SSSS \
.....

I

1610.6

Switching Waveforms [10]
Read Cycle No. 1[7,8]

~M_ ~-~~~-~-t-~~~~~-.I~~~~~~~~~~
DATA OUT

PREVIOUS DATA

~===================D=A=T=A=V=A=LI=D=================
1610.7

2-290

~PRES

CYM1610

W'nlCONDUCTOR

Switching Waveforms (Continued)
Read Cycle No. 2[8, 10J
~

t RC

-.~

~
tACS
-'

...., ~

.....

~

tOOE

t HZDE -

tUDE
HIGH IMPEDANCE

DATA OUT

I---

SUPPLY
CURRENT

HIGH IMPEDANCE

DATA VALID

tucs--

___________~-OO-%--------------------------------------------------~-%~r------::
100--

VCC

t HZCS

I+--tPD

tpu

1610-8

Write Cycle No.1 (WE Controlled) [7, l1J

ADDRESS

-

twc

...,f-

-jt"

-,,,,-'\ c"-\.\.~

tscs

....,""L/// / / / / / / / / /

tAW
tSA

t HA tPWE

L

WE

~\

I

'\...:l .....

I~
tHD

tSD

DATA IN

-l f-

----------------------------------------------~L--~HI~GH~IM~PE~D~AN~C~E-----:f
~----------::)---k
-

DATA 1/0

~f-

DATA-IN VALID

I--

t HZWE

tLZWE

__

DATA UNDEFINED

1610-9

Write Cycle No.2 (CS Controlled)[7, l1J
twc

ADDRESS

-

~ f-

-'ftSA

tscs

-: ~

~

tHA

tAW

WE

*"1

--:

tSD

.1

DATA IN
DATA 110

tPWE

'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.~["""

DATA-IN VALID
-

tHZWE

f/ / / / / / / / / / / / / /
,I

tHD

*"1
HIGH IMPEDANCi

DATA UNDEFINED

Note: If CS goes HIGH simuItaneouslywith WE HIGH, the output remains in a high impedance state.

2-291

1610-10

fW;~OOcroR

CYM1610
Ordering Information

Truth Table
CS UB LB ()E WE Input/Outputs

Deselect Power Down

H

X

X

X

L

H
L

H
L

X

H
L
L

L
H
L

L
X

Deselect Power Down
Read Word
Read Lower Byte
H Data Out0-7
H Data OutS-IS Read Upper Byte
Write Word
L Data InO_IS

H
L
L

L

X

L

H
L

X

L

H
H
H

L
L
L
L
L
L
L

L
L

H
L

L

H

L
L

X

Mode

X

HighZ
HighZ

H

Data OUto-lS

H

Data In 0-7
Data InS_IS
HighZ

Write Lower Byte
Write Upper Byte
Deselect

H
H

HighZ
HighZ

Deselect
Deselect

Speed

Ordering Code

Package

25

CYM1610HD-25C
CYM161OLHD·25C
CYM1610HD-3SC
CYM1610LHD·35C
CYM1610HD·35MB
CYM1610LHD·35MB
CYM1610HD-45C
CYM1610LHD-45C
CYM1610HD-45MB
CYM1610LHD-45MB
CYM1610HD·SOC
CYM161OLHD·5OC
CYM1610HD-50MB
CYM161OLHD·50MB

HDOl
HDOl
HDOl
HDOl
HDOl
HDOl
HDOl
HDOl
HDOl
HDOl
HDOl
HDOl
HDOl
HDOl

3S

4S

SO

Document #: 38-M-00OO6

2-292

Type

Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military

CYM1611

CYPRESS
SEMICONDUCTOR

16K X 16 Static RAM
Module

Features

Functional Description

• High·density 256K bit SRAM Module

The CYM1611 is a very high performance
256K-bit Static RAM module organized
as 16K words by 16 bits. The module is
constructed from four 16K x 4 SRAMs in
Leadless Chip Carriers mounted on a ceo
ramic substrate with pins. A vertical DIP
format minimizes board space (footprint
= 0.4 sq in.) while still keeping a maximum height of 0.5 in.
Writing to the memory module is accomplished when the chip select (CS) and
wnte enable (WE) inputs are both LOW.
Data on the sixteen input/output pins (Do

• High speed
- Access time - 25 ns
• 16 bit wide organization
• Low active power - 1.8 W (max)
• Hermetic SMD Technology
• TTL compatible inputs and outputs
• Low profile
- Max. height - .0.5 in.
• Small PCB footprint - 0.4 sq in.
• 2V data retention (L version)

Logic Block Diagram

through D,.) is written into the memory
location specified on the address pins (Ao
through A'3~
Reading the device is accomplished by
taking chip select @ and output enable
(OE) LOW, while WE remains inactive or
HIGH. Under these conditions, the con·
tents of the memory location specified on
the address pins will appear on the sixteen
data input/output pins.
The input/output pins remain in a high
impedance state unless the module is
selected, outputs are enabled, and write
enable (WE) is HIGH.

Pin Configuration

AO-~3--~14~-------'----------------~

~-------.-+----------~
~-----'r4-4--------~

OE"----...-1H-4------......,

VDIP

1611·2

1611-1

Selection Guide
1611HV·25
Maximum Access time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)

Commercial

1611HV·35

1611HV·45

25

30

35

45

330

330

330

330

330

330

330

80

80

80

80

80

80

Military
Commercial

1611HV·30

80

Military

2-293

fJI

~EM~NDUCTOR

CYM1611

Maximum Ratings
(Above which the useful life may be impaired)
Storage Temperature ..................... -65°C to + 150°C

Static Discharge Voltage ......................... >2001V
(per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied ......................... -55°C to + 125°C

Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 mA

Supply Voltage to Ground Potential. . . . . . . .. -O.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State .. .. .. . . .. .. .. .. .. .. .. .. ... -O.5V to + 7.0V

Range

DC Input Voltage ........................ -3.0V to +7.0V

Commercial

Output Current into Outputs (Low) .................. 20 rnA

Military

Ambient
Temperature
ODC to +70 DC

5V ± 10%

-55°C to + 125°C

5V ± 10%

Vee

Electrical Characteristics Over Operating Range
Parameters

Description

CYM1611HV

Test Conditions

Max.

Min.
VOH

Output HIGH Voltage

Vee = Min., IoH = -4.0 mA

\bL

Output WW Voltage

Vee = Min., IoL = 8.0 mA

24

\1H

Input HIGH Voltage

\1L

Input WW Voltage

IIX

Input Load Current

GND ~ \1 ~ \te

Ioz

Output Leakage Current

GND

los

Output Short Circuit
Current ll]

Vee = Max., VOUT = GND

Ice

Vee Operating
Supply Current

Vee = Max., lOUT = 0 mA, CS

IsBl

Automatic CS
Power Down Current

IsB2

Automatic CS
Power Down Current

Units
V

0.4

V

22

Vee

V

-3.0

0.8

V

-20

+20

j.I.A

-20

+20

j.I.A

-350

rnA

330

rnA

Max. Vee, CS :i;!: VIR,
Min. Duty Cycle = 100%

80

mA

Max. Vee, CS :i;!: Vee- 0.3V,
VIN :i;!: 'te - 0.3V or
VIN ~ 0.3V

80

mA

~

\1

~

\te, Output Disabled

~

VIL

Capacitancel2]
Parameters

Test Conditions

Max.

0 = 25 DC,f = 1 MHz
ee= 5.0V

35

Description

CIN

Input Capacitance

COUT

Output Capacitance

Notes:
1. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.

Units
pF

15

2. Tested on a sample basis.

AC Test Loads and Waveforms
R1 481 0

R1 481 0

5V~ R2

O~P~

J

5V~ R2

O~P~

-

-

Figure 18
Equivalent to:

J

30pF _ 2550

INCLUDING
JIG AND
SCOPE

All Input Pulses

5pF _ 2550

--

INCLUDING
JIG AND
SCOPE

_ _ _ _~

90%
GND--'""""I
~5ns

S5ns

1611-4

Figure 2

1670

0----'IMr---0 1.73V

--.~

1611-3

Figure lb

TI:lEVENIN EQUIVAlENT

O~PUT

3.01/ - - - -

1611-5

2-294

~&~NDUCTOR

CYM1611

Switching Characteristics
Parameters

Over Operating Range [2J

Description

1611HV-25
Min.

1611HV-30
Min.

Max.

Max.

1611HV-35
Min.

Max.

1611HV-45
Min.

Units

II

Max.

READ CYCLE
tRC

Read Cycle Time

tAA

Address to Data Valid

tOHA

Data Hold from Address Change

25

30
25

35

30

3

45

35

3

ns

45
5

3

ns
ns

tACS

CS LOW to Data Valid

25

30

35

45

ns

tDOE

OE LOW to Data Valid

15

20

25

30

ns

tLZOE

(jE LOW to Low Z

tHZOE

OE HIGH to High Z[4J

tLZes

CS LOW to Low Z[sJ

tHZes

CS HIGH to High Z[4, SJ

tpu

CS' LOW to Power Up

tpD

CS HIGH to Power Down

0

0

0
15

10
10

5

20

0

10
15
0

ns
ns

45

35

ns
ns

20

0
30

20

ns

20

10

15

10

0

0

ns

WRITE CYCLE [6J
twc

Write Cycle Time

20

25

25

35

ns

tscs

CS LOW to Write End

20

25

30

40

ns

tAW

Address Set-up to Write End

20

25

30

40

ns

tHA

Address Hold from Write End

2

2

2

2

ns

tSA

Address Set-up to Write Start

2

2

2

2

ns

tpWE

WE Pulse Width

20

25

25

ns

tSD

Data Set-up to Write End

13

20

20

30
25

tHO

Data Hold from Write End

2

2

2

2

tHzWE

WE LOW to High Z[4J

0

7

0

tLZWE
WE HIGH to Low Z
3
Notes:
3. Test conditions assume signaJ transition times of 5 ns or less, liming
reference levels of 1.5V, input levels of 0 to 3,OV and output loading of
the specified IOL/I OH and 30 pF load capacitance,
4, tHZOE,tHZCS and\JzWE arespecifiedwithCL = 5pFasinFigure1b.
Transition is measured ±500 mV from steady state voltage.
5. At any given temperature and voltage condition, t HZCS is less than
tLZCs for any given device. These parameters are guaranteed and not
100% tested.

5

12

0

12

0

5

5

ns
ns

15

ns
ns

6. The internal write time of the memory is defined by the overlap ofrs
LOW and W'ELOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
7. WE is HIGH for read cycle.
8. Device is continuously selected. 00,
= VIL
9. Address valid prior to or coincident with"CS transition LOW.
10. Data I/O is HIGH impedance if OE = VIH•

2-295

-rs

5i7~NDUC1DR

CYM1611

Data Retention Characteristics (L Version Only)
Parameter
\bR

Description

CYM1611

Test Conditions

Min.

Max.

2.0

Vee for Retention of Data

IeeDR

Data Retention Current

!cDR
tR

Chip Deselect to Data Retention Time

IU

Input Leakage Current

Operation Recovery Time

V
4

Vee = 2.0V,
CS :2001V
(per MIlrSTD-883 Method 3015)
Ambient Temperature with
Latch-up Current. . . . . . . . . . . . . . .. . .. . . . . . . . . . . .. > 200 rnA
Power Applied ......................... -55°C to + 125°C
Supply Voltage to Ground Potential. . . . . . . ..

~.5V

to + 7.0V

DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . ..

~.5V

to + 7.0V

Operating Range

DC Input Voltage ........................ -3.0V to +7.0V
Output Current into Outputs (Low) .................. 20 rnA

Range

Ambient
Temperature

Vee

Commercial

OOC to +70 o C

5V ± 10%

-55°C to + 125 °C

5V ± 10%

Military

[41

Electrical Characteristics Over Operating Range
Parameters

Description

CYM1621HD

Test Conditions

Min.
2.4

Output HIGH Voltage

Vee = Min., IOH = -4.0 rnA

VoL

Output WW Voltage

. I IOL = 8.0 rnA
Vee = Mm.

\fH

Input HIGH Voltage

22

\fL

Input WW Voltage

IIX

Input Load Current

loz

VOH

Max.

Military

Units
V

0.4

V

Vee
0.8

V

-3.0
GND::;;;\l ::;;;'\te

-20

+20

jJ.A

Output Leakage Current

GND ::;;; Va ::;;; \te, Output Disabled

-20

+20

jJ.A

los

Output Short Circuit
Current [11

Vee = Max., VOUT = GND

Iccx16

Vee Operating Supply
Current by 16 mode

~ = Max., lOUT = 0 lOA

Icexs

Vee Operating Supply
Current by 8 mode

~e = Max., lOUT = 0 rnA

Vee = Max., lOUT = 0 rnA

IsB1

Vee Operating Supply
Current by 4 mode
Automatic cs [ZI
Power Down Current

IsBz

Automatic CS[ZI
Power Down Current

IcCx4

I IOL =

120 rnA Commercial

V

-350

rnA

1250

rnA

850

rnA

~::;;;\lL

650

rnA

Max. Vee, CSxx ;;::; \fH
Min. Duty Cycle = 100%

320

rnA

Max. Vee, CSxx ;;::; Vee - 0.3V,
VIN ;;::; Vee - 0.3V or VIN ::;;; 0.3V

320

rnA

::;;;VIL

xx::;;; VIL

Capacitance[31
Parameters
CIN
COUT
Notes:

Description
Input Capacitance
Output Capacitance

1. Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the ~ input is required to keep the device
deselected during Vee power-up, otherwise ISB will exceed values
given.

Test Conditions

Max.

TA= 25°C, f = 1MHz
Vee = 5.0V

130

Units
pF

35

3. Tested initially and after any design or process changes that may affect
these parameters.
4. TA is the "instant on" case temperature.

2-306

~ffifSS

CYM1621

~~ICONDUCfOR
Switching Characteristics
Parameters

Over Operating Range lSI
1621HD-2S

Description

1621HD-30
Min.

Max.

Min.

1621HD-35
Min.

Max.

Max.

1621HD-45
Min.

Unit

Max.

READ CYCLE

2S

tRC

Read Cycle Time

tAA

Address to Data Valid

tOHA

Output Hold from Address Change

tACS

CS LOW to Data Valid

tLZCS

CS'LOW to Low ZI7]

tHZCS

CS' HIGH to High ZI6.7]

tpu

CS LOW to Power Up

30

2S

35

30

5

5

5

2S

30

5

5

2S

0

CS' HIGH to Power Down
tPD
WRITE CYCLE 181

2S

0

30

ns

45

ns

ns

5
30

0

ns

45
5

35

5

20

45
35

ns

30
0

35

ns
ns

35

ns

twc

Write Cycle Time

25

30

35

45

ns

tscs

CS LOW to Write End

22

40

ns

tAw

Address Set-up to Write End

22

2S
2S

30

30

40

ns

tHA

Address Hold from Write End

0

0

0

0

ns

tsA

Address Set-up to Write Start

3

5

5

ns

tpWE

Wl! Pulse Width

20

ns

Data Set-up to Write End

20

2S
20

30

tSD

2
20
15

2S

ns

tHD

Data Hold from Write End
WI! HIGH to Low ZI 71

3

5

5

5

ns

5

5

5

5

ns

tLZWE

WE LOW to High Z16. 71
tHZWE
0
20
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels ofl.5V. input levels of 0 to 3.0V and output loading of
the specified loUIoH and 30 pF load capacitance.
6. t HZCS and tHZWB are specified with Ct. = 5 pF as in Figure lb.
Transition is measured ± 500 mV from steady state voltage.
7. At any given temperature and voltage condition, t HZCS is less than
tLZCs for any given device.

0

2S

0

2S

0

2S

ns

8. The internal write time of the memory is defmed by the overlap ofrsLOW andWI! LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
9. WE is HIGH for read cycle.
lO.Device is continuously selected, CS = Vu,
l1.Address valid prior to or coincident with CS transition LOW.

AC Test Loads and Waveforms

B(481
~

R1

5V

R1

0 MIL)

OUTPUT

3~

~(481
0 MIL)

5V

3.OV - - - - ~~-----.J
90%

OUTPUT

~

30 pF

R2
2020

~

-= (255 0 MIL)

Figure 1a

R2
2020

-= (255 0 MIL)

INCLUDING
JIG AND
SCOPE

INCLUDING
JIG AND
SCOPE

Equivalent to:

5 pF

Figure 1b

10%

GND---"'I

:S: 5 ns
1621-4

1621-3

Figure 2

THEVENIN EQUIVAlENT

OUTPUT

~
Military

1.73V

OUTPUT

~
Commercial

1621·5

2-307

1.9OV
1621-6

•

CYM1621
Data Retention Characteristics (L Version Onl r)
Parameter

I

\DR

Description

CYM1621

Test Conditions

Min.

Max.

20

Vee for Retention of Data

IeCDR

Data Retention Current

\te = 20V,

!cDR

Chip Deselect to Data Retention Time

CS ;::: Vee- 0.2V

tR

Operation Recovery Time

IU

Input Leakage Current

V
16

mA

ns

0

\iN;::: 'te - 0.2V
or \iN s: 0.2V

Units

ns

tRe (12)
10

IIA

Notes:
12. IRe = Read Cycle Time.

Data Retention Waveform

*. ---:
4.5V

~

DATA RETENTION MODE

1

o<><*_________

D_A_T_A_V_A_LI_D_ _ _ _ _ _ __

1621·8

2-308

~~EM~~DUCTOR

CYM1621

Switching Waveforms

(Continued)

Read Cycle No. 2[9,10]

fI

t AC

~~

..... jL.

tACS

~

t HZCS

t LZCS -

HIGH IMPEDANCE

DATA OUT

HIGH IMPEDANCE

DATA VALID

___________~-~-%--------------------------------------------------~-%~r------::
- tpD

- - tpu

VCC

SUPPLY
CURRENT

1621-9

Write Cycle No.1 (WE Controlled)[8]
ADDRESS

--

two

-:; f-

-:;ftscs

'\. '\. \ '\. '\. '\.-T

-, ~////
tAW
tSA

/////////

t HA tPWE

1

-,f-

-T\.\.-' r1

tSD

DATA IN

j

IE-

DATA OUT

tHO

-:it-

DATA-IN VALID

~HI;G~H~IM~PE~DA~N~C~E~_~~~

t HZWE

-

tLZWE

----------------------------------------------=:;L-__
::)---k
__

DATA UNDEFINED

...: : : : : : : : : :

1621-10

Write Cycle No.2 (CS Controlled)[8]
two

ADDRESS

-

~~

~ftSA

tscs

~

--: ~
tHA

tAW
tPWE

'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.~ ~

.1.

DATA IN

*"
'I

DATA OUT

DATA UNDEFINED

tSD
DATA-IN VALID

~ tHZWE

..... fo/ /

/ / / / / / / / / / //
,I

tHO

*"
1

HIGH IMPEDANCE

Note: IfCS goes H1GHsimultaneouslvwith WE HIGH, the output remains in a high impedance state.

2-309

1621-11

&7~DUcroR

CYM1621

Truth Table
CSxx

WE

Input/Outputs

Mode

H

X

HighZ

Deselect Power Down

L

H

Data Out

Read

L

L

Data In

Write

Ordering Information
Speed
2S
30

35

45

Package
Type

Operating
Range

HD02
HD02

Commercial

CYM1621LHD·2SC
CYMl621HD·3OC
CYM1621LHD·3OC
CYMl621HD·30MB

HD02
HD02
HD02

Commercial

CYM1621LHD·30MB

HD02

CYMl62lHD·35C
CYM1621LHD·35C

HD02
HD02

Commercial

CYM1621HD·35MB

HD02

Military

CYM1621LHD·35MB
CYM1621HD-4SC

HD02
HD02

Commercial

CYM1621LHD-45C

HD02

CYM1621HD-4SMB

HD02

CYM1621LHD-45MB

HD02

Ordering Code
CYM1621HD·2SC

Military

Military

Document #: 38-M-00009

2-310

ADVANCED INFORMATION

CYPRESS
SEMICONDUCTOR

64K X 16 Static RAM
Module

Features

Functional Description

• High-density 1M bit SRAM Module

The CYMI622 is a very high perfonnance
1M-bit Static RAM module organized
as 64K words by 16 bits. The module is
constructed from four 64K x 4 SRAMs in
Leadless Chip Carriers mounted on a ceramic substrate with pins. A vertical DIP
fonnat minimizes board space (footprint
= 0.45 sq in.) while still keeping a maximum height of 0.5 in.
Writing to the memory module is accomplished when the chip select (CS) and
write enable ~} inputs are both LOW.
Data on the sixteen input/output pins (Do
through D,.) is written into the memory
location specified on the address pins (Ao
through A,.~

• High speed
- Access time - 30 ns
• 16 bit wide organization
• 40 pin Vertical DIP
• Low active power - 1.8 W
• Hermetic SMD Technology
• TTL compatible inputs and outputs

• Low profile
- Max. height - 0.5 in.
• Small PCB footprint - 0.45 sq in.
• 2V data retention (L version)

Reading the device is accomplished by
taking chip select (CS) and output enable
(OE) LOW, while 'WE remains inactive or
HIGH. Under these conditions, the contents of the memory location specified on
the address pins will appear on the sixteen
data input/output pins.
The input/output pins remain in a high
impedance state unless the module is
selected, outputs are enabled, and write
enable ~) is HIGH.

Package Configuration

Logic Block Diagram

~0.5'=J

Ao-A16~~16--------~----------------'

~--------~+-----------~

WE

CYM1622

------~+-+---------~

- [:=J

~ ----,-~~-+--------,

D 2.0'
D
[:=J

16

Do - 0 15
1622·1

[:=J

1622·2

2-311

II

CYM1623

CYPRESS
SEMICONDUCTOR

64K X 16 Static RAM
Module

Features

Functional Description

• High-density 1 Megabit SRAM Module
• High speed CMOS SRAMs
- Access time - 70 ns
• 40 pin - 0.6 in. wide DIP package
• JEDEC compatible pin-out
• Low active power - 1.3 W (max)
• Hermetic SMD Technology
• TTL compatible inputs and outputs
• Commercial and Military
Temperature Ranges
• 2 V data retention (L version)

The CYM1623 is a high performance
1 Megabit Static RAM module organized
as 64K words by 16 bits. The module is
constructed using four 32K x 8 Static
RAMs in Leadless Chip Carners mounted
onto a double sided multilayer ceramic
substrate. A decoder is used to interpret
the higher order address A,. and select
one of the two pairs of RAMs.
Writing to the memory module is accomplished when the chip select (CS), ~
select (UB, LB) and write enable (WE)
inputs are both LOW. Data on the
input/output pins of the selected byte

Logic Block Diagram

(I/O. - I/O,., I/Oo - I/07) is written into
the memory location specified on the
address pins (Ao through A,.~
Reading the device is accomplishedJ?I.
taking chip select (CS), ~ select (VB,
LB) and output enable (OE) LOW, while
WE remains inactive or HIGH. Under
these conditions, the contents of the
memory location specified on the address
pins will appear on the appropriate data
input/output pins.
The input/output pins re~ain in a ~h
impedance state when chip select (CS),
b~ select (UB, LB)?r output enable.
(OE) is HIGH, or wnte enable (WE) IS
LOW.

Pin Configuration
A,S

Ao-A,4----?'~6--------------~----------i

~

rn:----~------_,rr------,

1/0,5
1/0,4
1/0 ,3
1/0'2
1/0
1/0 ",0

~------------._rr----_,

I/0g
I/0a
GND
1/0 7
1/0 6
1/0 5
1/0 4
1/0 3

A,s ----,.----1
~---,-+--I
'---r-~

UB ---+-+-----'

1102

1/0,
1/0 0

UE"
DIP

L------------'--"""7.<- 1/00 - 1/07

1623·2

1823-1

SeIectlon GUI°de
1623HD-70
Maximum Access time (ns)
Maximum Operating CUrrent (rnA)
Maximum Standby Current (rnA)

1623HD-85

1623HD-100

70

8S

100

Commercial

2AO

2AO

Military

2AO

2AO

2AO
2AO

Commercial

70

70

70

Military

70

70

70

2-312

~PRFSS
~~ICONDUCTOR

CYM1623

Operating Range

Maximum Ratings
(Above which the useful life may be impaired.)

Range

Storage Temperature ..................... -65·C to + 150·C

Commercial

Ambient Temperature with
Power Applied , ... , .................... -55 DC to + 12S DC

Military

Ambient
Temperature
ODC to +70 DC

5V ± 10%

-55°C to + 12S DC

SV ± 10%

Vee

Supply Voltage to Ground Potential. . . . . . . .. -0.3V to + 7.0V
DC Voltage Applied to Outputs
in High Z State.. .. .. . . .. .. .. . . .. .. .. . .... -0.3V to + 7.0V
DC Input Voltage ........................ -{).3V to +7.0V
Output Current into Outputs (Low) .................. SO rnA

EIectrIca
' I Charac te'ti
ns cs 0 ver 0)peratin~R ange
Parameters

Description

CYM1623HD

Test Conditions

Max,

Min,
'bH

Output HIGH Voltage

Vee

'bL

Output LOW Voltage

Vee

\oiH

Input HIGH Voltage

\oiL

Input LOW Voltage

IIX

Input Load Current

Ioz

\tc

= Min., IOH = -1.0 rnA
= Min., IoL = 4.0 rnA

2.4

Units
V

0.4

V

2.2

Vee

V

-{).3

0.8

V

GND:;;;\i :;;;\tc

-10

+10

~

Output Leakage Current

GND :;;; Va :;;; \t:c. Output Disabled

-10

+10

~

IcCx16

Vee Operating
Supply Current

~ = Maxnf0UT = 0 rnA
S, tm,&
= VIL

240

rnA

Icexs

Vee Operating
Supply Current

CS

120

rnA

IsBl

Automatic CS [21
Power Down Current

Max. Vee, CS:2:: VlH,
Min. Duty Cycle = 100%

70

rnA

IsB2

Automatic CS [21
Power Down Current

Max. Vee, CS :2:: \te - 0.2V,
VIN :2:: 'tc - 0.2V or
VIN :;;; 0.2V

20

rnA

= Max., lOUT = 0 rnA
= VIL, UBorlli = VIL

Capacitance [3]
Parameters

Description

Max,

Test Conditions

CIN

Input Capacitance

COUT

Output Capacitance

= 2S DC, f = 1 MHz,
\t;e = 5.0V

35

TA

Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.

Units
pF

40

2. A pull-up resistor to \t:c on the CS input is required to keep the device
deselected during 'Cc power-up, otherwise ISB will exceed values
given.
3. Tested on a sample basis.

AC Test Loads and Waveforms
R1 10000

5V~

OUTPUT

.l30 PF

-=

[NCLUD[NG
JIG AND
SCOPE

5V~ R2

OUTPUT

~7Q

-=

J

5pF

-

INCLUDING
JIG AND
SCOPE

_ 6670

-

4000
o---vw-----o

2.OV

90%
GND

---"I
:;;;5 ns
1623-4

Figure 2

THEVENIN EQUIVALENT

OUTPUT

3.0V----

1623-3

Figure Ib

Figure la
Equivalent to:

All Input Pulses

R1 10000

1623-5

2-313

II

Q~DUCTOR

CYM1623

Switching Characteristics Over Operating Range [4J
1623HJ)..70

Description

Parameters

Min.

1623HD-85

Max.

Min.

Max.

1623HJ)..100

Min.

Units

Max.

READ CYCLE

tRC

Read Cycle Time

tAA

Address to Data Valid

tOHA

Data Hold from Address Change

tACS

CS LOW to Data Valid

tOOE

DE LOW to Data Valid

tlZOE
tHZOE

~LOWtoLowZ

tlZCS

DE HIGH to High Z
CS LOW to Low Z[6J

tHZCS

CS HIGH to High Z [5, 6)

70

85
70

5

85

40

5

50
5

35
5

ns

100

ns

60

ns

40

ns

40

ns

ns

5
35

5
35

100
5

5
70

ns

100
85

ns

ns

5
35

WRITE CYCLE [7J

twc
tscs

Write Cycle Time

70

85

100

ns

CS LOW to Write End

75

90

ns

tAW

Address Set-up to Write End

65
65

75

90

ns

tHA

Address Hold from Write End

10

15

ns

tSA

Address Set-up to Write Start

25

15
25

30

ns

tpWE

WE Pulse Width

30

35

35

ns
ns

tso

Data Set-up to Write End

20

20

25

tHO
tlZWE

Data Hold from Write End
WE HIGH to Low Z[6J

10

10

15

ns

5

5

5

ns

tHZWE

WI! LOW to High Z[S, 6)

0

Notes:
4.Test conditions assume signaJ transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V and output loading of
the specified IOIJlOH and 30 pF load capacitanCe.
5.t Hzcs and t HzWB are specified with CL - 5 pF as in Figure lb.
Transition is measured ±500 mV from steady state voltage.
6.At any given temperature and voltage condition, t HZCS is less than
t LZCS for any given device. These parameters are guaranteed and not
100% tested.

30

0

35

0

40

ns

7.The internal write time of the memory is defined by the overlap ofrs
WW and Wiiww. Both signals must be WW to initiate a write and
either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced. to the rising edge of the
signal that terminates the write.
S.WE is HIGH for read cycle.
9.0evice is continuously selected, rs = VlLand OIl = V 1L•
10.Address valid prior to or coincident with CS transition low.
11.0ata 110 will be high impedance if
= VJH.

rnr

2-314

~pp£ss
•

CYM1623

ilWnMlCONDUCTOR

Data Retention Characteristics (L Version Onl
CYM1623

Parameter

Test Conditions

Description

\DR

Vee for Retention Data

IeCDR

Data Retention Current

!cDR (13]

Chip Deselect to Data Retention Time

tR[ 131

Operation Recovery Time

Min.
2.0

Vee = 2.0V,
CS:--_4_.5_V

::k

:_A-A~-':N----_/c:,:::l
;;j'2001V
(per MIL-STD-883 Method 3015)
Ambient Temperature with
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA
Power Applied ......................... -55°C to + 125°C
Supply Voltage to Ground Potential ......... -0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -O.SV to + 7.0V

Range

DC Input Voltage .......................... -3.0V to 7.0V

Commercial

Output Current into Outputs (Low) .................. 20 rnA

Military

[41

Ambient
Temperature
OOC to

Vee

+70 o C

5V ± 10%

-55°C to + 125°C

5V ± 10%

Electrical Characteristics Over Operating Range
Parameters

CYM164IHD

Test Conditions

Description

Min.
VOH
VOL

Output HIGH Voltage
Output LOW Voltage

2.4

Vee = Min., IOH = -4.0 rnA
.

Vee = Mm.

1 IOL = 8.0 rnA Military

"I

Max.

IOL = 12.0 rnA Commercial

Units
V

0.4

V

Vee
0.8

V

\iH

Input HIGH Voltage

22

\iL

Input LOW Voltage

-3.0

Irx

Input Load Current

GND :5; Vi :5; Vee

-80

+80

~A

loz

Output Leakage Current

GND :5; VO:5; Vee. Output Disabled

-10

+ 10

~

los

Output Short Circuit
Current[!]

Vee = Max., VOUT = GND

Icex16

Vee Operating Supply
Current by 16 mode

Icex8

Vee Operating Supply
Current by 8 mode

IcCx4

Vee Operating Supply
Current by 4 mode

IsB!
ISB2

V

-350

rnA

CSxx :5; VrL

1310

rnA

CSxx

Vee = Max., lOUT = 0 rnA
:5; VrL

850

rnA

CSxx

Vee = Max., lOUT = 0 rnA
:5; VIL

650

rnA

Automatic CS [21
Power Down Current

Max. Vee, cSxx ~ \iH
Min. Duty Cycle = 100%

320

rnA

Automatic CS [21
Power Down Current

Max. Vee, CSxx ~ Vee - O.3V,
VIN ~ Vee - O.3V or VIN :5; O.3V

320

rnA

Vee = Max., lOUT = 0 rnA

Capacitance[3I
Parameters
CrN
COUT
Notes:

Description
Input Capacitance
Output Capacitance

Test Conditions

Max.

TA= 25°C,f = 1 MHz
Vee = S.OV

130

Units
pF

35

1. Not more than 1 output should be shorted at one time. Duration ofthe

3. Tested initially and after any design or process changes that may affect

short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the es input is required to keep the device
deselected during Vee power-up, otherwise ISB will exceed values
given.

4. TA is the "instant on" case temperature.

these parameters.

2-325

OIl

&!~NDUcrOR

PRELIMINARY CYMl641

Switching Characteristics
Parameters

Over Operating Range (5)
1641HD-35

1641HD-25

Description

Min.

Max.

Min.

1641HD-45

Max.

Min.

Max.

1641HD-55

Min.

Unit

Max.

READ CYCLE

35

2S

tRC

Read Cycle Time

tAA

Address to Data Valid

2S

loRA

Output Hold from Address Change

tACS

CS LOW to Data Valid

tues

CS LOW to Low Z[7]

tnzcs

<::S' HIGH to High Z[6,7]

tpu

CS LOW to Power Up

45

5

5
2S

5
35

3
15

20

2S

5

3

55
3

2S

0

<::S' HIGH to Power Down
tPD
WRITE CYCLE [8]

55

45

3

0

55
45

35

0

35

2S
0

45

55

ns
ns
ns
ns
ns
ns
ns
ns

twc

Write Cycle Time

2S

35

45

55

ns

tscs

CS LOW to Write End
Address Set-up to Write End

35
35

45

tAW

2S
2S

45

55
55

ns
ns

tRA

Address Hold from Write End

2

2

2

2

ns

tSA

Address Set-up to Write Start

0

0

2

2

tpWE

WE Pulse Width

2S

35

35

35

ns
ns

tSD

Data Set-up to Write End

15

20

20

2S

tHO

Data Hold from Write End

0

0

0

0

tlZWE

~HIGH to

3

3

Low Z[7J

LOW to High

Z[6, 7J
tHZWE
20
0
Notes:
S. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V and output loading of
the specified 10UIoH and 30 pF load capacitance.
6. t HZCS and tHzWE are specified with G. = 5 pF as in Figure lb.
Transition is measured ±SOO mV from steady state voltage.
7. At any given temperature and voltage condition, t HZCS is less than
tLZCS for any given device.
WE

0

3
2S

0

ns
ns

3
2S

0

2S

ns
ns

8. The internal write time of the memory is defined by the overlap oft::S'
LOW and'WELOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going mOHo The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
9. WE is HIOH for read cycle.
10.Device is continuously selected, CS = Vn:.
1l.Address valid prior to or coincident with CS transition LOW.
12.CS0-3, CS4-7, CS8_II , and CS12-1S are represented by CS and
'WEu and W&. are represented by WE in the switching characteristics and timing waveforms.

ACTest Loads and Waveforms
R1 3290

OlTTP~~ ~(481
0 MIL)

R1 3290

~(481
0 MIL)

OlTTP:

5 pF
.1
-::'

R2
30 pF
2020
-::'
-::' (255 0 MIL)

.1

Figure la

90%

R2
2020
-::' (255 0 MIL)

INCLUDING
JIG AND
SCOPE

INCLUDING
JIG AND
SCOPE

3.OV-----

Figure Ib

1641-3

TIlEVENIN EQUIVALENT
1670
OlTTPUT C>---"W'v---O 1.73V

GND---"'I
~5ns

1841-4

Figure 2

Equivalent to:

Military

OUTPUT~
Commercial

1841-5

2-326

1.9OV
1641-8

PRELIMINARY CYM1641
Data Retentlon characterlstlcs

(L Version Onl ,)

Description

Parameter

Test Conditions

'DR

Vee for Retention of Data

IeeDR

Data Retention Current

tCOR

Chip Deselect to Data Retention Time

tR

Operation Recovery Time

IU

Input Leakage Current

CYM1641

Min.

Max.

20
Vee = 2.0V,
CS ~ Vee- 0.2V
\iN ~ 'tC - 0.2V
or\fN~0.2V

Units
V

64

mA
ns

0
tRe[12]

ns
32

jJ.A

Notes:
12. IRe = Read Cycle Time.

Data Retention Waveform
~

DATA RETENTION MODE

:}:

1.·--4-·5V-!-----:-D-R2!-~----. . ."i::~
1641-7

Switching Waveforms [10.12]
Read Cycle No. 1[9, 101

ADDRESS

DATA OUT

=t:,--;~ __*_----=--=
PREVIOUSDATA~_ _ _ _ _ _ _ _ _D_A_T_A_Il_AL_ID_ _ _ _ _ _ _ __

1641-8

2-327

~~NDUcrOR

PRELIMINARY CYM1641

Switching Waveforms

(Continued)

Read Cycle No. 2[9,10J
t RC

~I['"

-:l

I£-

tACs

HIGH IMPEDANCE

DATA OUT

SUPPLY
CURRENT

HIGH IMPEDANCE

DATA VALID

----------~-~-%-----------------------------------------------~--%~------::
-

Vee

t HZCS

t LZCS -

-

t pu

- t pD

1641-11

Write Cycle No, 1 (WE Controlled)[8J

ADDRESS

--

twc

~ f-

-;ftscs

'\'\\ !'\'\'\~

--, ~////
tAw
tSA

tPWE

1

~'\V I['"
1

"'7r

L

_I

.1

tSD

J

DATA IN

*"

tHO

*"

DATA-IN VALID

'I

DATA OUT

'/////////

t HA -

I

---------------------------------------------;!~
__~HIG~H~IM~P_E~DA~N~CE~_=-:t~=:::::::::
::)'----k.~ tHZWE

4 - - - tLZWE

__

DATA UNDEFINED

1641-10

Write Cycle No.2 (CS Controlled)[8J
twc

ADDRESS

:::J

~

-'Jl'tscs

tSA

,I"-

-T

tHA

tAW

tPWE

,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\~L

,I

DATA IN

*"
I

DATA OUT

-;
tSD

DATA UNDEFINED

DATA-IN VALID

-

t HZWE

f/ / // / / // / / / / / /
.1 tHO

~
HIGH IMPEDANCE

Note: IfCS goes HlGHsimultaneouslywithWEHlGH, the output remains in a high impedance state.

2-328

1641-11

~WFSS
"'~ICONDucroR

PRELIMINARY

~lMl

Truth Table
CS xx

WEn

Input/Outputs

Mode

H

X

HighZ

Deselect Power Down

L

H

Data Out

Read

L

L

Data In

Write

•

Ordering Information
Speed
25
35

45

55

Ordering Code

Package
Type

Operating
Range
Commercial

CYMl641HD-25C

HD05

CYMl641UID-25C

HD05

CYM1641HD-35C

HD05

Commercial

CYMl64lUID-35C
CYM1641HD-35MB

HD05
HD05

Military

CYM1641LHD-35MB

HD05

CYM1641HD-45C
CYM1641UID-45C

HD05

CYMl641HD-45MB

HD05

CYMl641LHD-45MB
CYM1641HD-55C

HD05

CYMl641LHD-55C

HD05

CYM1641HD-55MB

HD05

CYM1641UID-55MB

HD05

Commercial

HD05

HD05

Military
Commercial
Military

Document #: 38-M-00013

2-329

QM1804

ADVANCED INFORMATION

CYPRESS
SEMICONDUCTOR
Features
• Ideal for Cache Tag Applications
• High speed CMOS SRAMs
- Access time - 15 ns
• Low active power - 4 W (max)
• SMD Technology
• TTL compatible inputs and outputs
• 84 pin ZIP
• Low profile
- Max. height - .50 in.
• Small PCB footprint - 1.4 sq in.
• Two cycle reset for cache flush
• Separate WE for ''Valid Bits" update

lK X 32 Static RAM
Module with Separate I/O

Functional Description
The CYM1804 is a high performance
32K-bit Static RAM module organized
as 1K words by 32 bits. This module is
constructed from eight resettable lK x 4
SRAMs in SOJ packages mounted on
an epoxy laminate board with pins. The
module's reset capability combined with
the 15 ns access time makes it ideal for
cache tag applications.
Writing to the module is accomplished
when chip select (CS) and the appropriate
write enables (WE, and/or WE.) are both
LOW. Data on the input pins (Ix) is written into the memory location specified on
the address pins (Ao through Ag).

Logic Block Diagram

Reading the device is accomplished by
taking the chip sel~CS) LOW, while
the write enables (WEN) remain HIGH.
Under these conditions the contents of
the memory location specified on the address pins will appear on the data output
pins (Ox).
The data output pins stay in the high impedance state whenever chip select (CS)
is HIGH, Reset (RS) is LOW, output enable (DE) is HIGH, or during the writing
operation when Write Enable (WIlN) is
LOW.
Reset is initiated by selecting the device
(CS = LOW) and pulsing the reset (RS)
input LOW. Within two memory cycles all
bits are internally cleared to zero.

Package Configuration

r-

0.5"-1

Ao-A9~~10----~-------------------------'

~----~rr-------------------'

o

~1----,-+4--------------------.

~2----~~------------------~

CJ

D

110 8 -1/0 11

o
o
CJ

1/0 20 -1/0 23

110 24 -1/0 27

CJ

__________________
~~~------~------------~--------~
~-L

4.2"

~

1804·1

CJ

3
2-330

-L
10.33 "

T

1804·2

CYM1821

CYPRESS
SEMICONDUCTOR

16K X 32 Static RAM
Module.
location specified on the address pins

Features

Functional Description

• High-density 512K bit SRAM Module

The CYM1821 is a high performance
512K-bit Static RAM module organized as
16K words by 32 bits. This module is constructed from eight 16K x 4 SRAMs SOJ
packages mounted on an epoxy laminate
board with pins. Four chip selects (CS"
CS•• Cs.. and CS4 ) are used to independently enable the four bytes. Reading or
writing can be executed on individual
bytes or any combination of multiple
bytes through proper use of selects.

• High speed CMOS SRAMs
- Access time - 25 ns
• Low active power - 4 W (max)
• SMD Technology
• TTL compatible inputs and outputs
• Low profile
- Max. height - .50 in.
• SmaIl PCB footprint - 1.0 sq in.
• JEDEC compatible pinout
• 2V data retention (L version)

(Ao through A,.).
Reading the device is accomplished by
taking the chi~lects (CSN) WW. while
write enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified on the address pins
will appear on the data input/output pins
(Il0X>.

The data input/output pins stay in the
~ impedance state when write enable
(WE) is WW. or the appropriate chip
selects are HIGH.
Two pins (pDO and PD1) are used to
identify module memory density in
applications where alternate versions
of the JEDEC standard modules can be
interchanged.

Writing to each byte is accomplished
when the appropriate chip selects (CSN)
and write enable (WE) inputs are both
WW. Data on the input/output pins
(Il0X> is written into the memory

Logic Block Diagram
Ao-A13-'f14~----r-----------------------;

PDO-GND
PD1-0pen

~-----'rr-----------------,

~----~~---------------.
1/0 0 -1/0 3

1/0 4 -1/0 7

1/08 -1/011

1/012 -1/015

1/016 -1/019

11020 -1/°23

I/O 24 - 1/0 27

110 28 -1/0 31

~1

~2

~3

~4

ZIP
Top View

1821-1

1821-2

Selection Guide
1821PZ-25

1821PZ-35

25

35

4S

Maximum Operating Current (rnA)

7'2J)

720

720

Maximum Standby Current (rnA)

160

160

160

Maximum Access time (ns)

2-331

1821PZ-45

~PR£SS
~nEMICONDUC!'OR

CYM1821

Maximum Ratings
(AbOve which the useful life may be impaired)
Storage Temperature ..................... -65·C to + 150·C

Static Discharge Voltage ......................... > 2001V
(per MJL.STD-883 Method 3015.2)

Ambient Temperature with
Power Applied ............................ OOCto +70°C

Latch-up Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA

Supply Voltage to Ground Potential ......... -O.SY to +7.0V
DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -O.SY to + 7.0V

Operating Range
Ambient
Temperature

Range

DC Input Voltage ........................ -3.0V to + 7.0V
Output Current into Outputs (Low) .................. 20 rnA

OOC to

Commercial

Vee

+70 o C

5V ± 10%

EIectrIca
' ICharac te°f
ns ICS 0 ver 0Jperating R ange
Parameters

Description

CYM1821PZ

Test Conditions

Min.

= Min., IOH = -4.0 rnA

Output HIGH Voltage
Output WW Voltage
Input HIGH Voltage
Input WW Voltage

Vee
Vee

Input Load Current

GND~Vr ~\tc

Output Leakage Current
Output Short Circuit
Current!l!

GND

Units

Max.

2.4
0.4

V
V

2.2
-3.0

Vee
0.8

V
V

-20

+20

jJ.A

-20

+20

jJ.A

Vee

-350

rnA

CSN ~ \lL
Max. Vee; CSN ~ VlH
Min. Duty Cycle = 100%

720

rnA

IsBl

Vee Operating
Supply Current
Automatic CS [2J
Power Down Current

160

rnA

IsB2

Automatic CS [2]
Power Down Current

Max. Vee; CSN ~ 'tc - 0.3V,
VIN ~ Vee - 0.3V or
VIN ~ 0.3V

160

rnA

VaH
VaL
\lH
\lL
IIX

Ioz

los
Ice

= Min., IOL = 8.0 rnA

~

Vo ~ Vee, Output Disabled

= Max., VOUT = GND
Vee = Max., lOUT = 0 rnA

Capacitance!3J
Parameters

Description

Test Conditions

CIN

Input Capacitance

COUT

Output Capacitance

TA = 25°C, f
Vee = 5.0V

Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.

Max.
70

= 1 MHz,

Units
pF

35

2. A pull-up resistor to \Cc on the -rs input is required to keep the device
deselected during 'Cc power-up, otherwise ISB will exceed values
given.
3. Tested on a sample basis.

AC Test Loads and Waveforms
R1 4810

5V~ R2
.I 30 pF 2550

OUTPUT

--

INCLUDING
JIG AND
SCOPE

All Input Pulses

R1 4810

5V~ R2

3.av----

OUTPUT

--

Figure la
THEVENIN EQUIVALENT
1670
OUTPUT 0-----'vIIIr--0 1.7'JIJ

J

5pF

-

INCLUDING
JIG AND
SCOPE

_ 2550

-

GND

90%

---'I
~5ns

1821.3

1821·4

Figure 2

Figure Ib

Equivalent to:

1821-5

2-332

Q~NDUCTOR

CYM1821

Switching Characteristics Over Operating Range [4]
1821PZ-25

Description

Parameters

Min.

1821PZ-35

Max.

Min.

Max.

1821PZ-45
Min.

Units

Max.

READ CYCLE
tRC
tAA

25

Read Cycle Time
Data Hold from Address Change

3

3

ns
4S

3S

25

Address to Data Valid

45

35

ns
ns

3

toHA
tACS

CS LOW to Data Valid

25

35

45

ns

loOE

OE LOW to Data Valid

15

25

30

ns

tLZOE
tHZOE

(JE LOW to LOW

tLZes

CS LOW to Low Z

tazes
tpu

CS HIGH to High

Z

DE HIGH to HIGH Z
[6]

0

tAw
tHA

20

10
15

10

35

ns
ns

20

ns

45

ns

0

0
25

tpo
CS HIGH to Power Down
WRITE CYCLE [7]
twc
tscs

10

5

ns

3

20

15

Z[5.6]

~ LOW to Power Up

3

3

ns

Write Cycle Time

20

30

40

ns

CS LOW to Write End

20

25

35

ns

Address Set-up to Write End

20

25

3S

ns

Address Hold from Write End

2

2

2

ns

tSA
tpWE
tso

Address Set-up to Write Start

2

2

2

ns

WE Pulse Width

25

30

Data Set-up to Write End

20
13

15

20

ns
ns

tHO

Data Hold from Write End

2

2

2

ns

tLZWE
tHZWE

WE HIGH to Low Z[6]
~ LOW to High Z [5. 6]

3

5

S

0

Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of I.SV, input levels of 0 to 3.0V and output loading
of the specified IodIoH and 30 pF load capacitance.
5. tHZCS and tHZWE are specified with C L = 5 pF as in Figure lb.
Transition is measured ±SOO mV from steady state voltage.
6. At any given temperature and voltage condition, t HZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.

7

0

10

0

ns

15

ns

7. The internal write time of the memory is defined by the overlap 0(CS'
WWandWEWW.BothsignalsmustbeWWtoinitiateawriteand
either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
8. WE is HIGH for read cycle.
9. Device is continuously selected, es = ViL and OE = VII;
10. Address valid prior to or coincident with CS' transition low.
11. CS;, ~, CS3 and ~ are represented by L:s in the switching Characteristics and Waveforms.

2-333

II

~&~~DUCTOR

CYM1821

Data Retention Characteristics
Parameter
YbR

(L Version Only)

Description

CYM1821

Test Conditions

Min.

Max.

2.0

VCC for Retention Data

ICCDR

Data Retention Current

tCDR[13J

Chip Deselect to Data Retention Time

t R [13J

Operation Recovery Time

IU[13J

Input Leakage Current

VCC = 2.0V,
CS ~ VCC- 0.2V
\iN ~ \tc - 0.2V
or\iN:S;; 0.2V

V

8
0

rnA

ns
ns

tRC[12J
10

Notes:
12. tRe = Read Cycle Time.

Units

j.i.A.

13. Guaranteed, not tested.

Data Retention Waveform

DATA RETENTION MODE

~

::k

1
.
r--_4._5v_f-----V.-~:-R-~-2V-----/~:~
'z/ZZZVIH

~SSSS\

I

1621-6

*________

Switching Waveforms [I1J

=f=_______

Read Cycle No. 1[8,9J

tRc__ _ _ _ _ _ _

'DD",SS

DATA OUT

~

...

~~

PREVIOUS DATA VAUD

~===================D=A=T=A=V=A=LI=D=================
1821-7

2-334

~~DUcroR

CYM1821

Switching Waveforms (Continued)
Read Cycle No. 2[8, 10]

fI

tRC

~ tr

-:: I'tACS
-'~

-::'""
f--

tooe

t Hzoe -

tLZOE

DATA OUT

f---

HIGH IMPEDANCE

DATAVAUD

tLZOS-

~tpD

----------~-~-%------------------------------------------------~~-----:~
14-

Vee
SUPPLY
CURRENT

tHzcs

HIGH IMPeDANCE

tpu

1821-8

Write Cycle No.1 (WE Controlled)[7]

ADDRESS

--

twc

-:l~

-l f-

"" I"""T

tscs

-:

\

{o// / /. ' / / / / / / / / /

tAw

t HA -

tSA

tPWE

.3k-\. V1tr

I~

I

J

,I

tSD

DATA IN

'1 f-

I

--------------------------------------------~L---H-IG-H-IM~P~E-DANC~E-----=i---(---------:::)----k
-

DATA OUT

tHO

"*

DATA-IN VALID

~

t HZWE

tLZWE

DATA UNDEFINED

1821-9

Write Cycle No.2 (CS Controlled)[7]
ADDRESS

--

twc
~f-

~f-

tSA

tscs

-: ~

-T

tHA

tAW

"""'''''''''''''''''''''''''''''''''''''''~
DATA IN

*"
I

DATA OUT

DATA UNDEFINED

Note:

tPWE
~

-:: ~// ///.//

tSD
DATA-IN VAUD

I--

tHZWE

*"

I
!:IIS!!:! IMPEe.e~CE

If CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

2-335

/ // / / / /

tHO

1821-10

~PffSS
~~MICONDUcrOR

CYM1821

Truth Table
CSN WE OE

H

X

L

X
H

L

L

L

H

X
H

L

Input/Outputs

Mode

HighZ
Data Out
Data In
HighZ

Deselect Power Down
Read
Write
Deselect

Ordering Information
Speed

Ordering Code

Package
Type

Operating
Range

25

CYM1821PZ-25C

PZOI

Commercial

CYM1821LPZ-25C

PZOI

35

CYM1821PZ-35C

PZOI

45

CYM1821LPZ-35C
CYM1821PZ-45C

PZOI
PZOI

CYM1821LPZ-45C

PZOI

Document #: 38-M-OOOlS

2-336

CYM1822

CYPRESS
SEMICONDUCTOR

16K X 32 Static RAM Module •
with Separate I/O

Features

Functional Description

• High-density 512K bit SRAM Module

The CYM1822 is a high performance
512K-bit Static RAM module organized
as 16K words by 32 bits. This module is
constructed from eight 16K x 4 Separate
I/O SRAMs in Leadless Chip Carriers
mounted on a ceramic substrate with pins.
Two chip selects (CSu and CSd are used
to independently enable the upper and
lower 16-bit Data words.

• High speed CMOS SRAMs
- Access time - 25 ns
• Low active power - 4 W (max)
• Hermetic SMD Technology
• TTL compatible inputs and outputs
• Low profile
- Max_ height - _52 in_
• Small PCB footprint - 1_0 sq in_
• 2V data retention (L version)

Writing to the device i~accomplished
when the chip selects (CSU andlor CSr)
and write enable (WE) inputs are both

LOW. Data on the input pins (DIX> is
written into the memory location specified
on the address pins (Ao through A,.).
Reading the device is accomplished ~
taking the chip selects (CSu and/or CSr)
and ou~enable (OE) LOW, while write
enable (WE) remains HIGH. Under these
conditions the contents of the memory
location specified on the address pins will
appear on the data output pins (DOX>.
The output pins stay in the hi@l.mpedance state when write enable (WE) is
LOW, the ~ropriate chip selects are
HIGH, or OE is HIGH.

Pin Configuration

Logic Block Diagram

vee

GNO
010
011
012

Ao-A13--~14~-r-----------r----------~-----------,

001
002
003
D04
005
D06
007

013

~~~+------,~------r+-------,

014
Dl5
016
Dl7
AD

~--T4~-----'-r+------'1-r-----,
01 16- 0131

000

++++---,..---+++---....---t-++---.----+++------,

A1

A2
A4

A3
AS

018
019
0110
0111
0112
0113
0114
0115

008
D09
0010
0011
0012
0013
0014
0015

m

WE:
vee

GNO
llm

~

0116
0117
0118
0119
0120
0121
0122
0123
A6

0016
0017
0018
0019
0020
0021
0022
0023
A7
A8

A8

~L------~~r-------L-~----~~r-----~
L..________--.JL-________--L.________---'+. 00 _ 00
0
15

A10
A12

A11
A1a

0124

0024
0025
0026
0027
0028
0029

0125

0126
0127
Dl28
0129
Dl30
Dl31

1822-1

D030

0031

vec

GNO

VDIP

1822-2

Selection Guide
Maximum Access time (ns)
Maximum Operating Current (rnA
Maximum Standby Current (rnA)

Commercial
Military
Commercial
Military

1822HV-25

1822HV-30

25
720

30

35

4S

720

720

720

720

720

720

160
160

160

160

160

160

160

2-337

1822HV-35

1822HV-45

~CfPRESS

CYM1822

~I1&IcONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired)
Storage Temperature ..................... -6S·C to + 150·C

Static Discharge Voltage ......................... >2001V
(per MIWTD-883 Method 3015.2)

Ambient Temperature with
Power Applied ......................... -55°C to + 125°C

Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA

Supply Voltage to Ground Potential. . . . . . . .. -n.SY to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State.. .. .. .. .. .. .. .. . . .. .. . .... -n.SY to + 7.0V

Ambient
Temperature

Vee

O°C to +70°C

SV ± 10%

-55°C to + 125°C

5V ± 10%

Range

DC Input Voltage ........................ -3.0V to +7.0V

Commercial

Output Current into Outputs (Low) .................. 20 rnA

Military

Electrical Characteristics oVer Operating Range
Parameters

Description

CYM1822HV

Test Conditions

Units
Min.

= Min., IOH = -4.0 rnA
Vee = Min., IOL = B.O rnA

Max.

24

\bH

Output HIGH Voltage

\bL

Output LOW Voltage

\fH

Input HIGH Voltage

\fL

Input LOW Voltage

IIX

Input Load Current

GNDS\f S\te

loz

Output Leakage Current

GND ::s;; Vo ::s;; Vee. Output Disabled

los

Output Short Circuit
Current[!J

Vee

Icc

Vee Operating
Supply Current

IsB!
IsB2

Vee

V
0.4

V

22

Vee

v

-3.0

O.B

V

-20

+20

-20

+20

JJA
JJA

-350

rnA

\te
CSLCSU::S;;VIL

720

rnA

Automatic CS [2J
Power Down Current

Max. Vee; CSu, CSL~ VIH
Min. Duty Cycle = 100%

160

rnA

Automatic CS [2J
Power Down Current

Max. Vee; CSu, CSL~ \te - 0.3V,
VIN ~ \te - 0.3V or
VIN ::s;; 0.3V

160

rnA

= Max., VOUT = GND
= Max., lOUT = 0 rnA

Capacitance[3J
Parameters

Description

Test Conditions

Input Capacitance

TA

CoUT

Output Capacitance

\tC

Notes:
1. Not more than 1 output should beshorled atone time. Duration oflhe
shorl circuit should not exceed 30 seconds.

Max.

= 25°C, f = 1 MHz,

CIN

70

= S.OV

Units
pF

35

2. A pull-up resistor to ~c on the CE input is required to keep the device
deselected during 'tc power-up, otherwise ISB will exceed values
given.
3. Tested on a sample basis.

AC Test Loads and Waveforms
R1 481 Q

5V~

OUTPUT

J.

30pF

5V~

OUTPUT

-= ~5Q

INCLUDING
JIG AND
SCOPE

J.

5pF

INCLUDING
JIG AND
SCOPE

Figure la
Equivalent to:

All Input Pulses

R1 481 Q

-= ~55Q

1670
o-----vvv----o

1822-5

GND

---'I
::S;;5 ns
1822-4

Figure 2

Figure Ib

1.73V

90%

1822-3

THEVENIN EQUIVALENT

OUTPUT

3.OV----

2-338

&n.

CYM1822

CYPRESS
SEMlCONDUCIOR

Switchin2 Characteristics Over Operating Range [4J
Description

Parameters

1822HV-25
Min.

1822HV-30

Max.

Min.

Max.

1822HV-35
Min.

Max.

1822HV-45
Min.

Units

Max.

READ CYCLE

tRC

Read Cycle Time

tAA

Address to Data Valid

tOHA

Data Hold from Address Change

tACS

CS LOW to Data Valid

tDOE

OE LOW to Data Valid

tLZOE
tHZOE

tm LOW to LOW Z

25
25

IUcs

~

tHZCS

CS HIGH to High Z[S.6J

tpu

~ LOW to Power Up

LOW to Low Z[6J

5

25
15

25
5

20
10

5
0

10

0

25

45

ns

30

ns

20

ns

20

ns

45

ns

ns

ns

ns

10

15
0

ns

0
35

30

ns

5

20

15

10

45
5

35

20
5

15

CS HIGH to Power Down
tPD
WRITE CYCLE [7J

5
30

3

OE HIGH to HIGH Z

35

30

5

ns

45

35

30

twc

Write Cycle Time

20

25

25

35

ns

tscs

CS LOW to Write End

20

25

30

40

ns

tAW

Address Set-up to Write End

25

30

40

ns

tHA

Address Hold from Write End

20
2

2

2

2

ns

tSA

Address Set-up to Write Start

2

2

2

2

ns

tpWE

WB' Pulse Width

20

25

25

30

ns

tSD

Data Set-up to Write End

13

20

20

25

ns

tHD

Data Hold from Write End

3

3

3

3

ns

tLZWE

WE HIGH to Low Z[6J

3

5

5

5

tHZWE

WE LOW to High Z[S.6J

0

7

Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of l.SV, input levels of 0 to 3.0V and output loading
of the specified IOLlIoH and 30 pF load capacitance.
5. tHzcs and tHZWE are specified with C L = 5 pF as in Figure lb.
Transition is measured ±SOO mV from steady state voltage.
6. At any given temperature and voltage condition, t HZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.

0

12

0

12

0

ns
15

ns

7. The internal write time of the memol}' is defined by the overlap orrs
LOWandWELOW.BothsignalsmustbeLOWtoinitiateawriteand
either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
8. WE is HIGH for read cycle.
9. Device is continuously selected, CS = \'!Land OE = VII;
10. Address valid prior to or coincident with CS'transition low.
11. Both CS"L and CS"uare represented by CS'" in the switching Characteristics and Waveforms.

2-339

til

CYM1822
Data etentIon

aractenstics (L Version Only

Parameter

Vee for Retention Data

IeCDR

Data Retention Current

tcoR[I3]

Chip Deselect to Data Retention Time

tR[13]

Operation Recovery Time
Input Leakage Current

Min.

Max.

2.0

\bR

IU[13]

CYM1822

Test Conditions

Description

V

S

\te = 2.OV,
CS ~ Vee - 0.2V
\iN ~ \tc - 0.2V
or \iNS 0.2V

0

mA
ns
ns

tRe[12]
10

Notes:
12. tac = Read Cycle Time.

Units

j.IA

13. Guaranteed, not tested.

Data Retention Waveform

:J:

DATA RETENTION MODE :}:

1. f . . ----"o-V.-:R-2001V
(per MIWTD-883 Method 3015)
Ambient Temperature with
Latch-Up Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 rnA
Power Applied ......................... -55°C to + 12S°C
Supply Voltage to Ground Potential. . . . . . . .. -o.SV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -o.SV to + 7.0V
DC Input Voltage ......................... -o.SV to + 70V
Output Current into Outputs (Low) .................. 20 rnA

Range

Ambient
Temperature

Vee

Commercial

OOC to +70 o C

SV ± 10%

-55°C to + 12S°C

SV ± 10%

Military

[4)

Electrical Characteristics Over Operating Range
Description

Parameters

CYM1830HD

Test Conditions

Min.
2.4

Output HIGH Voltage

Vee = Min., IOH = -4.0 rnA

\bL

Output LOW Voltage

. I IOL = 8.0 rnA
Vee = Mm. I

\fH

Input HIGH Voltage

22

\fL

Input LOW Voltage

IIX

Input Load Current

GND

Ioz

Output Leakage Current

GND

Ios

Output Short Circuit
Current[!)

Vee = Max., Your = GND

Icc

Vee Operating Supply
Current by 16 mode

~ = Max., lour = 0 rnA

IsB!

Automatic CS (2)
Power Down Current

IsB2

Automatic CS(2)
Power Down Current

\bH

Max.

Military

Units
V

0.4

V

Vee
0.8

V

0.5
-20

+20

-10

10

IJ.A
IJ.A

-350

rnA

880

rnA

Max. \te, CSx ~ VrH
Min. Duty Cycle = 100%

320

rnA

Max. Vee, CSx ~ \te - 0.3V,
VIN ~ Vee - 0.3V or VIN S 0.3V

160

rnA

IOL = 120 rnA Commercial

s: \f s: \te
s: Vo s: \te, Output Disabled

SVIL

V

Capacitance[3)
Parameters

Description

CrN

Input Capacitance

cour

Output Capacitance

Test Conditions

Max.

TA = 2SoC,f = 1 MHz
Vee=S.OV

90

Units
pF

30

Notes:

1. Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the CS input is r~quired to keep the device
dese)ected during Vee power-up, otherwise Iso will exceed values
given.

3. Tested initially and after any design or process changes that may affect
these parameters.
4. TA is the "instant on" case temperature.

2-344

Q~NDUcrOR

PRELIMINARY

Switching Characteristics

CYMl830

Over Operating Range [SI
1830HD-30

183OHD-45

1830HD-35

1830HD-55

Description

Parameters

Min.

Max.

Min.

Min.

Max.

Min.

Max.

Unit

Max.

READ CYCLE
Read Cycle Time

tRC
tAA

45

35

30

Address to Data Valid

35

30

loHA

Output Hold from Address Change

tACS

CS LOW to Data Valid

tLZes

CS LOW to Low Z(7)

tHZes

CS" HIGH to High Z16, 71

tpu

CS LOW to Power Up

tpo

CS" HIGH to Power Down

3

3
3

3

15

0

0

ns

20

ns

ns

ns

0
45

35

30

55
3

20

20

ns

ns

3
45

3

0

55

3
35

30

ns

55
45

55

ns

WRITE CYCLE [81
twc
tses

Write Cycle Time

30

35

45

55

ns

CS LOW to Write End

30

40
40
2

ns
ns

tAW

Address Set-up to Write End

tHA

Address Hold from Write End

25
25
2

2

40
40
2

tSA

Address Set-up to Write Start

2

2

2

2

ns

tpWE

WE Pulse Width

25

25

30

Data Set-up to Write End

20

20

tHO

Data Hold from Write End

2

2

25
2

40
25
2

ns

tso
tLZWE

WS' HIGH to Low Zl71

3

tHzwB

WE LOW to High Z16, 71

0

30

3
20

0

ns

ns

3

3

0

20

ns

20

0

ns
20

ns

Notes:

5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input levels of 0 to 3.0V and output loading of
the specified 100JlOH and 30 pF load capacitance.
6. t HZCS and tHZWE are specified with G. = 5 pF as in Figure lb.
Transition is measured ±500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.

8. The internal write time of the memory is defined by the overlap of~

LOW andWilLOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
9. WE.is HIGH for read cycle.
lO.Oevice is continuously selected, es = Vu,
l1.Address valid prior to or coincident with CS transition LOW.

AC Test Loads and Waveforms
R1 3290

5V

R1 3290

~(481
n MIL)

~(481
n MIL)

5V

OUTPUT

3.0V----

90%

OUTPUT

J

30 pF

":'

R2
2020
(255 0 MIL)

J

":'

GND

---"I
:S;5 ns

INCLUDING
JIG AND

INCLUDING
JIG AND

SCOPE

SCOPE

Figure la
Equivalent to:

5 pF

R2
2020
(255 0 MIL)

1830-4

1830-3

Figure Ib

Figure 2

THEVBNIN BQUIVALENT

OUTPUT

~
Military

OUTPUT

1.73V

1250

~

Commercial

1830-5

2-345

1.9OV
1830-8

Q~NDUcroR

PRELIMINARY

CYMl830

Data Retention Characteristics(L Version Only)
Parameter
\DR

Test Conditions

Description

CYM1830
Max.

Min.

Units

20

VCC for Retention of Data

ICCOR

Data Retention Current

tCOR

Chip Deselect to Data Retention Time

tR

Operation Recovery Time

Iu

Input Leakage Current

\t:C = 20V,
CS ~ Vcc- 0.2V
\iN ~ \t:c - O.2V
or\iN::S; 0.2V

V
32

rnA

0

ns

tRC[12)

ns
8

J.I.A

Notes:
12. IRe

= Read Cycle Time.
Data Retention Waveform

J::

DATA RETENTION MODE

~

f-----"o-R-2!:-'ZII-----/~~:::l

tc:J:I
....;...-_4_.5_'

"oR

'ZZZZZ7fv'H

I·

.

~SSS\
1830-7

Switching Waveforms [10)
Read Cycle No. 1(9· 10)

ADDRESS

DATA OUT

=tJ,~-;~ __*_--=--=
PREVIOUS DATA

1iALi~_________D_A_T_A_V_A_Ll_D_ _ _ _ _ _ __

1830-8

2-346

~PRF£S
"~ICONDUCTOR

PRELIMINARY

Switching Waveforms

CYMl830

(Continued)

Read Cycle No. 2[9. 101

II

tAC

~ It"

""l

"-

tACS

+

-~
tooe

t Hzoe -

tLZOe

t HZCS
HIGH IMPEOANCE

DATA OUT

I---

r--

HIGH IMPEOANCE

DATA VALID

t LZcs - tpD

t pu

ICC

Vee
SUPPLY
CURRENT

ISB

183(Hl

Write Cycle No.1 (WE Controlled)(81

ADDRESS

--

twc

-l ~

oj Etscs

\. \. \ \. \. \.T

-:

'-// / /. ' / / / / / / / / /

tAW
tSA

t HA tPWE

I

...., <-

-lk-\. \.~ I2001V
(per MIl,STD-883 Method 3015.2)
Latch-up Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. > 200 mA

Operating Range

DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . . . . .. -tl.SV to + 7.0V
DC Input Voltage ........................ -3.0V to +7.0V

Range

Ambient
Temperature

Vee

Commercial

O°Cto +70 o C

SV ± 10%

Output Current into Outputs (Low) ... ; .............. 20 mA

. tics Over Operating Range
EIec t'alCh
nc
arac t ens
Parameters

Description

CYM1831PZ

Test Conditions

Units
Min.

= Min.• IoH = -4.0 mA
= Min·.IoL = 8.0 mA

Max.

24

\bH
\bL

Output HIGH Voltage

Vee

Output LOW Voltage

Vee

\1H

Input HIGH Voltage

22

\1L

Input LOW Voltage

IIX

Input Load Current

GND S \'I S

Ioz

Output Leakage Current

GND S Vo S \to Output Disabled

Ios

Output Short Circuit
Current[1J

\te

Ice

Vee Operating
Supply Current

IsBI

Automatic CS [21
Power Down Current

IsBI

Automatic CS [2J
Power Down Current

V
0.4

V

-3.0

Vee
0.8

V

-20

+20

-20

+20

J.LA
J.LA

-350

mA

720

mA

160

rnA

160

mA

\tc

= Max.. VOUT = GND
~ = Max., lOUT = 0 mA
N S\'IL
Max. Vee: CSN ~ VIH
Min. Duty Cycle = 100%
Max. Vee: CSN ~ '<::c - 0.3V.
VIN ~ 't:c - 0.3V or
VIN S 0.3V

V

Capacitance[3J
Parameters

Description

Test Conditions

CJN

Input Capacitance

COUT

Output Capacitance

TA = 2S°C. f
Vee = S.OV

Notes:
1. Not more than 1 output shouJd be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.

Max.
70

= 1 MHz.

Units
pF

35

2. A pull-up resistor to \tc on then; input is required to keep the device
deselected during 'b: power-up. otherwise ISB will exceed values
given.
3. Tested on a sample basis.

AC Test Loads and Waveforms
R1 4810

R1 4810

5V~ R2 OllTP:~

OllTPlIT

J

1 l ~550

30pF _ 2550

-

INCLUDING
JIG AND
SCOPE

5PF

-

INCLUDING
JIG AND
SCOPE

1670

o-----vw---o

1.73V

GND---""I

S5ns

S5ns
1831-4

Figure 2

THEVENIN EQUIVALENT

OllTPUT

All Input Pulses
_ _ _~
90%

,,~:--

1831-3

Figure Ib

Figure la
Equivalent to:

3JN - - - -

1831-6

2-350

~PR2BS

PRELIMINARY

CYlMl~l

..
I1&IGalDUCTOR

Switching Characteristics Over Operating Range [4J
1831PZ-35

1831PZ-25

Description

Parameters

Min.

Max.

Min.

Max.

1831PZ-45
Min.

Units

Max.

READ CYCLE
tRC

Read Cycle Time

25

45

35

45

tAA

Address to Data Valid

tOHA

Data Hold from Address Change

tACS

CS LOW to Data Valid

25

35

45

ns

tOOE

OE LOW to Data Valid

15

25

30

ns

tUOE

<:m LOW to LOW Z

tHZOE

00 HIGH to HIGH Z

tues

'e8 LOW to Low Z [6J

tHZes

CS HIGH to High Z[5.6)

tpu

CS' LOW to Power Up

25

ns

3

35

0
3

20
3

10
0

CS HIGH to Power Down
WRITE CYCLE [7J

ns

20
20

15
0
35

ns

ns

3

0

25

tpo

0

0
10

ns
ns

3

3

ns
ns

45

ns

twc

Write Cycle Time

20

25

35

ns

18cs

CS LOW to Write End

20

30

40

ns

tAW

Address Set-up to Write End

20

30

40

ns

tHA

Address Hold from Write End

2

2

2

ns

tSA

Address Set-up to Write Start

2

2

2

ns

tPWE

W£ Pulse Width

20

25

30

ns

180

Data Set-up to Write End

13

20

25

ns

tHO

Data Hold from Write End

2

2

2

ns

tUWE

WE HIGH to Low Z[6J
W£ LOW to High Z [5. 6)

3

5

5

ns

tHZWE

0

Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.SV, input levels of 0 to 3.0V and output loading
of the specified IOLlIoH and 30 pF load capacitance.
S. tHZCS and tHzWE are specified with CL = 5 pF as in FIgUre lb.
Transition is measured ± 500 mV from steady state voltage.
6. At any given temperature and voltage condition. t HZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.

10

0

12

0

15

ns

7. The internal write time of the memory is defined by the overlap otrS'
LOWand'WllLOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
8. WI:! is HIGH for read cycle.
9. Oevice is continuously selected, CS = 'kand OE = VIl;
10. Address valid prior to or coincident with CS' transition low.
11. CS;. 'CS'z. CS"3 and <:S"4 are represented by ~ in the switching Characteristics and Waveforms.

2-351

Ell

~FJSS
~~ICONDUcrOR

PRELIMINARY

CYMl~l

Data Retention Characteristics (L Version Only
Parameter

CYM1831

Test Conditions

Description

Min.

Max.

2.0

\DR

Vee for Retention Data

ICCDR

Data Retention Current

tcnR[13J

Chip Deselect to Data Retention Time

tR[13I

Operation Recovery Time

IU[13J

Input Leakage Current

Vee = 2.0V,
CS ~ VCC- 0.2V
"iN ~ '\te - 0.2V

V
32

0

rnA

ns
ns

tRe[12J

or"iN~0.2V

Units

20

jJA

Notes:

12.

tRC a

13. Guaranteed, not tested.

Read Cycle Time.

Data Retention Waveform

4.5V

~

DATA RETENTION MODE

1

_____
"o_R_~_';N_____

*---:

_4.5V

---l

I

I
"'H1\SSSS\

tR

"oR

'Z/ZZZVIH

1831-6

Switching Waveforms[llJ
1[8,9J

Read Cycle No.

ADDRESS

DATA OUT

=f=-------t-~-------*-----~ ,~-;~
PREVIOUS DATA VAUD

~===================D=A=T=A=V=A=LI=D=================
1831-7

2-352

~PRESS
~nMlCONDUcrOR

PRELIMINARY

~1~1

Switching Waveforms (Continued)
Read Cycle No. 2[8, 10]
tRc

~~

.., ~

tACS

-'r-

..,jjC

I--

tOOE

t HZOE -

tLZOE

t HZCS
HIGH IMPEDANCE

HIGH IMPEDANCE

DATA OUT

I---

DATA VALID

t LZCS -

I---

__________~-~-%------------------------------------------------~J------::
~ tpu

VCC

SUPPLY
CURRENT

t pD

1831-8

Write Cycle No. 1 (WE Controlled) [7]
two

ADDRESS

~~
---:.;

~f.
tscs

\.\. \ I'\.'\. '\.T

""""

~////

tAW

t HA t PWE

tSA

T'\. '\...3 r

~

I

tHO

tSD

DATA[N

-H-

~~

DATA-IN VALID

----------------------------------------------;~
~HIG~H~IM~P~E~DA~N~CE~_--:t-r---------:::)-----k
i--

DATA OUT

'/////////

t HZWE

-

tLZWE

__

DATA UNDEFINED

__

1831-9

Write Cycle No.2 (CS Controlled)[7]

ADDRESS

--

two

~~

4f"
tSA

tscs

...., ~

~

tHA

tAW
tPWE

'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.\.\.\.\.\.\.\.\.\.\.\.~r-

...., 'f-//

/ /7777777777

tSD

DATA IN

*"
'I

DATA OUT

DATA UNDEFINED

DATA-IN VALID

I--

t HZWE

tHO

*"
'I

HIGH IMPEDANCE

Note: If CS goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

2-353

&t~DUCTOR

PRELIMINARY CYMl831

Truth Table
CSN WE OE

Input/Outputs

Mode

X

HighZ

Deselect Power Down

H

L

Data Out

Read

L

X

Data In

Write

H

H

HighZ

Deselect

H

X

L
L
L

Ordering Information
Speed
25
35
45

Ordering Code

Package
Type

Operating
Range
Commercial

CYM1831PZ-25C

PZOI

CYM1831LPZ-25C

PZOI

CYM1831PZ-35C

PZOI

CYM1831LPZ-35C
CYM1831PZ-45C

PZOI
PZOI

CYM1831LPZ-45C

PZOI

Document #: 38-M-00018

2-354

CYM1832

CYPRESS
SEMICONDUCTOR

64K X 32 Static RAM
Module.
(Il0X> is written into the memory

Features

Functional Description

• High-density 2M bit SRAM Module
• High speed CMOS SRAMs
- Access time - 35 ns
• Low active power - 5.4 W (max)
• SMD Technology
• TTL compatible inputs and outputs

The CYM1832 is a high performance
2M-bit Static RAM module organized as
64K words by 32 bits. This module is constructed from eight 64K x 4 SRAMs SOJ
packages mounted on an epoxy laminate
board with pi~ Four chip selects (CS"
CS.,
and CS.) are used to independently enable the four bytes. Reading or
writing can be executed on individual
bytes or any combination of multiple
bytes through proper use of selects.
Writing to each byte is accomplished
when the appropriate chip selects (CSN)
and write enable (WE) inputs are both
WW. Data on the input/output pins

location specified on the address pins
(Ao through A,.).
Reading the device is accomplished by
taking the chi~lects (CSN) WW, while
write enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified on the address pins
will appear on the data input/output pins
(IJOx)·
The data input/output pins stay in the
~ impedance state when write enable
(WE) is WW, or the appropriate chip
selects are HIGH.

cs.

• Low profile
- Max. height - .50 in.
• Small PCB footprint - 1.0 sq in.

Logic Block Diagram
Ao-A15~~1e~--~----------------------~

~----r-+-------------~
1/0 0

-

1/0 3

~1----+--+--J-------------~~--~

~2----~-+---L------------~~~~

1/020 -1/0 23
~3----~-+---L------------~~--~

~4----------J-------------------~
ZIP
Top View
1832-2

1632-1

Selection Guide
1832PZ-55

1832PZ-35

1832PZ-45

Maximum Access time (ns)

3S

4S

SS

Maximum Operating Current (rnA)

980

980

980

Maximum Standby Current (rnA)

240

240

240

2-355

~~~DUCTOR

CYMl832
Operating Range

Maximum Ratings
(Above which the useful life may be impaired)

Range

Ambient
Temperature

Vee

Commercial

0°Cto+70oC

5V ± 10%

Storage Temperature ..................... -45°C to + 12S°C
Ambient Temperature with
PowerApplied ........................... 1O°Cto+85°C
Supply Voltage to Ground Potential. . . . . . . .. -O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State.. . . . . . . . . . . . . . . . . . .. .. .... -O.5V to + 7.0V
DC Input Voltage ........................ -O.5V to +7.0V
Output Current into Outputs (Low) .................. 20 rnA

Electrical Characteristics Over Operating Range
Description

Parameters

CYM1832PZ

Test Conditions

Min.
VOH

Output HIGH Voltage

Vee = Min., IOH = -4.0 rnA

VOL

Output WW Voltage

Vee

VrH

Input HIGH Voltage

VrL

Input WW Voltage[11

IIX

Input Load Current

Ioz

Max.

2.4

= Min., IOL = 8.0 rnA

Units
V

0.4

V

22

Vee

V

-0.5

0.8

V

GND::;;\l ::;;\te

-20

+20

Output Leakage Current

GND ::;; Vo ::;; vee, Output Disabled

-100

+100

JJA
JJA

Ice

Vee Operating
Supply Current

Vee = Max., lour
CSN ::;;VrL

980

rnA

IsBl

Automatic CS [21
Power Down Current

Max. vee; CSN : ISooV
(Per MIL-STD-883 Method 3015)

Storage Temperature ............... -6S·C to + ISO·C
Ambient Temperature with
Power Applied .................... - 5S·C to + 125°C

Latch-up Current .......................... > 200 rnA

Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to +7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial
Military[6]

DC Program Voltage (pins 7, 18,20) ............. 14.OV

Ambient
Temperature

Vee

OOCto +700C

SV ±10%

- 55°C to + 125°C

5V ±10%

Electrical Characteristics Over Operating Range!7]
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

Vee = Min., IOH = -4.0 mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = Min.,IoL = -16 mA
VIN = VlH or VIL

VIH

Input HIGH Level

Guaranteed Input Logical HIGH
Voltage for All Inputs[2]

VIL

Input LOW Level

Guaranteed Input Logical LOW
Voltage for All inputs[2]

IIX

Input Leakage Current

GNDS; VIN S; Vee

Veo

Input Clamp Diode
Voltage

Note 1

loz

Output Leakage Current

GND S; Vo S; Vee Output Disabled[4]

los

Output Short Circuit Current

Vee

Icc

Power Supply Current

GND S; VIN S; Vee
Vee = Max.

= Max., VOUT = 0.OV[3]

I
I

Max.

Min.

Units

2.4

V
0.4

V
V

2.0
0.8

V

-10

+10

,...A

-40

+40

,...A

-20

-90

mA

Cominercial

90

Military

120

mA

Capacitance [5]
Parameters
CIN
COUT
Notes:

Description

Test Conditions

Input Capacitance

TA

Output Capacitance

TA

= 25°C, f =
= 25°C, f =

= S.OV
1 MHz, Vee = S.OV
1 MHz, Vee

Max.

Units

5

pF

8

pF

4. For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
5. Tested initially and after any design or process changes that may
affect these parameters.
6. TA is the Uinstant on" case temperature.
7. See the last page of this specification for Group A subgroup testing
information.

1. The CMOS process does not provide a clamp diode. However, the
CY7C22S is insensitive to - 3V dc input levels and - SV undershoot
pulses ofless than \0 ns (measured at 50% point).
2. These are absolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment (see Notes on
Testing).
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.

3-5

•

~

CY7C225

~~~~~~~~~~~~~~~~~~~~~~~~~~~~==~~~~~=
Switching Characteristics Over Operating Range!7, s]
Panuneters

7C225-25

Description

7C225-30

7C225-35

7C225·40

Min. Max. Min. Max. Min. Max. Min. Max.

25
0

30
0

3S
0

Units

tSA

Address Setup to Clock HIGH

tHA

Address Hold from Clock HIGH

teo

Clock HIGH to Valid Output

tpwe

Clock Pulse Width

10

15

20

20

ns

tsEs

ES Setup to Clock HIGH

10

10

10

10

ns

tHEs

ES Hold from Clock HIGH

0

top, toe

Delay from PImSlIT or CLEAR to Valid Output

tRP, tRe

PRESET or ~ Recovery to Cloc~ HIGH

15

12

15
15

Valid Output from
Clock HIGHIi)

0

ns

2S

5

5

20

20

20
20

ns

40

20

5
20

tpwP, tpwe PRESET or ~ Pulse Width
tcos

:

ns

20

20
20

ns

20
20

ns
ns
ns

20

20

25

30

ns

tHze

Inactive Output from Clock HIGHIi, 3)
Valid Output from Ii LOW[2)

20
20

20
20

25
25

30
30

ns

tOOE
tHZE

Inactive Output from
liHIGH[2,3)

20

20

25

30

ns

Notes:
1. Applies only when the synchronous (lls) function is used.
2. Applies only when the asynchronous (E) function is used.
3. Transition is measured at steady state HIGH level -500 mV or
steady state LOW level + 500 mV on the output from the 1.5V level
on the input with loads shown in Figure lb.
4. Tests are performed with rise and fall times of 5 ns or less.

ns

5. See Figure la for all swi1ching characteristics except tHZ.
6. See Figure 1b for tHZ.
7. All device test loads should be located within 2' of device outputs.
8. See the last page of this specification for Group A subgroup testing
information.

AC Test Loads and Waveforms [5, 6, 7]
R1250n

Rl250n

5v

5Vo-------JV~-,

50PF

R2
l67!l

INCLUDING
JIG AND
'::' SCOPE
':"

I

5 pf

---"!i..

ALL INPUT PULSES

OUTPUT o-----~----_i

OUTPUT O----1~----4

I

0--------'\1...,..---,
3.0 V

R2
l67!l

--------.i-......

f

GND - -.....

<:5nl

os;;;6nl

INCLUDING
_ JIG AND _
- SCOPE
-

0020-5
0020-3

Figure la

Figure 2

Figure Ib

Equivalent to:
THEVENIN EQUIVALENT
loon
OUTPUT ~2.0V
0020-4

Functional Description
applying the memory location to the address inputs (AoAs) and a logic LOW to the enable (Es) input. The stored
data is accessed and loaded into the master flip·flops of the
data register during the address set·up time. At the next
LOW·to·HIGH transition of the clock (CP), data is trans·
ferred to the slave flip·flops, which drive the output buff·
ers, and the accessed data will appear at the outputs (0007) provided the asynchronous enable (E) is also LOW.

The CY7C225 is a CMOS electrically Programmable Read
Only Memory organized as 512 words x 8·bits and is a pin·
for.pin replacement for bipolar TTL fusible link PROMs.
The CY7C225 incorporates a D·type, master·slave register
on chip, reducing the cost and size of pipelined micropro·
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is provided with synchronous (Es) and asFchronous
(E) output enables, and CLEAR and PRES T inputs.

The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the enable to a
logic LOW.

Upon power·up, the synchronous enable (Es) flip-flop will
be in the set condition causing the outputs (00-07) to be
in the OFF or high impedance state. Data is read by

3.·6

~
CY7C225
~~~~~OR==========================================================~~~
Functional Description

(Continued)
The CY7C225 has buffered asynchronous CI:EAR and
PRESET input (INIT). The initialize function is useful
during power-up and time-out sequences.

Regardless of the condition ofE, the outputs will go to the
OFF or high impedance state upon the next positive clock
edge after the synchronous enable (Es) input is switched to
a HIGH level. If the synchronous enable pin is switched to
a logic LOW, the subsequent positive clock edge will return the output to the active state ifE is LOW. Following a
positive clock edge, the address and synchronous enable
inputs are free to change since no change in the output will
occur until the next low to high transition of the clock.
This unique feature allows the CY7C225 decoders and
sense amplifiers to access the next location while previously
addressed data remains stable on the outputs.

Applying a LOW to the PRESET input causes an immediate load of all ones into the master and slave flip-flops of
the register, independent of all other inputs, including the
clock (CP). Applying a LOW to the CLEAR input, resets
the flip-flops to all zeros. The initialize data will appear at
the device outputs after the outputs are enabled by bringing
the asynchronous enable (E) LOW.
When power is applied the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in
the high impedance state. In order to enable the outputs a
clock must occur and the Es input pin must be LOW at
least a setup time prior to the clock LOW to HIGH transition. The E input may then be used to enable the outputs.

System timing is simplified in that the on-chip edge triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar
to those of discrete registers available in the market.

Switching Waveforms
A~Al0

+-____

__________________________________

~~~----~----~~~~~~~-------------------

CP

tooe

0020-6

Notes on Testing
Incoming test procedures on these devices should be carefully planned,
taking into account the high performance and output drive capabilities of
the parts. The following notes may be useful.
\. Ensure that adequate decoupling capacitance is employed across the
device Vcc and ground terminals. Multiple capacitors are recommended, including a 0.1 /JoF or larger capacitor and a om /JoF or
smaller capacitor placed as close to the device terminals as possible.
Inadequate decoupling may result in large variations of power supply
voltage, creating erroneous. function or transient performance failures.
2. Do not leave any inputs disconnected (floating) during any tests.

3. Do not attempt to perform threshold tests under AC conditions.
Large amplitude, fast ground current transients normally occur as the
device outputs discharge the load capacitances. These transients flowing through the parasitic inductance between the device ground pin
and the test system ground can create significant reductions in observable input noise immunity.
4. Output levels are measured at \.5V reference levels.
5. Transition is measured at steady state HIGH level - 500 m Vor
steady state LOW level + 500 m V on the output from the I.5V level
on inputs with load shown in Figure 1h.

3-7

3

~
CY7C225
~I'~=======================================
Typical DC and AC Characteristics
NOR~~SUPPLYCURRENT

1.2,----...,.........,...,...-----,

1A

!:
Q

1.2

/

N

::;

"

:i
0:

1.0

V

i

0.8
0.6

/

/

e

5.0

4.5

0.80L...._ _ _---li-._ _ _ _---l
-55
26
126

S.O

CLOCK TO OUTPUT TIME
1.6 vs TEMPERATURE

CJ

!

:i

i=

1A

1.0

/"

/

~

0:
0:
:::I

40

CJ

0:
:::I

Ii

i...

0.6

.

""

N

~
0:

O.S

-

TA j26'C
4.0

5.0

4.8

5.8

6.0

SUPPLY VOLTAGE (V)

NORMALIZED SETUP TIME
vs. TEMPERATURE

1.6

'"

0.8

---

..
.~

1.4

:::I

""-

Q

1.2

-

N

::;

~

1.0

t-'

0:

i

0.8

TA j2S'C

60

CJ

~

IIIQ

i

O.S
-86

!

.
.

1.0

::;

0.8

60

...z

i

1.2

26

30

0.4
4.0

126

AMBI ENT TEMPERATUR E

C

0.8

NORMALIZED SETUP TIME

. r---......

iii
N
::;

i

vs. SUPPLY VOLTAGE

>=

1.2

,

"""

1.0

AMBIENT TEMPERATURE ('C)

:i

'"
9

1.4

~
~::;

SUPPLY VOLTAGE (V)

Ie

!:i

CLOCK TO OUTPUT TIME
vs. Vee

S
o 1.2 .......

TA -26"C
'=MAX.

4.0

..

.

1.6

!

u

..

NORNUUJZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

vs.SUPPLYVOLTAGE

1.6

rc)

4.6

6.0

0.6

S.O

6.5

OUTPUT SOURCE CURRENT
vs.VOLTAGE

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING

,-

26.0

~

!

~

20

10

:::I

0

1.0

"

176

/

'"""
3.0

OUTPUT VOLTAGE (V)

4.0

E10.0
Q

6.0
0.0

V

/
o

1
...

..

/

20.0

3
" 15.0

2.0

26

126

0:
0:
:::I
CJ

100

'"

75

in

~

TA· 'c
Vee -4.6V

0

200

400

600

CAPACITANCE (pF)

800

1000

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

.., ..--

160

z

z

/

126

AMBIENT TEMPERATURE ('C)

30.0

"

-55

SUPPLY VOLTAGE (V)

50
25

/

/

/

'"
Vee -5.0V

L

TA -26'C

oV
0.0

1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

0020-7

3·8

Device Programming
Overview:
There is a programmable function contained in the 7C225
CMOS 512 x 8 Registered PROM; the 512 x 8 array. All of
the programming elements are "EPROM" cells, and are in
an erased state when the device is shipped.

DC Programming Parameters TA =

The 512 x 8 array uses a differential memory cell, with
differential sensing techniques. In the erased state the cell
contains neither a one nor a zero. The erased state of this
array may be verified by using the "BLANK CHECK
ONES" and "BLANK CHECK ZEROS" function, see
Table 3.

25°C
Table 1

Parameter
Vpp[l]
Vccp
VIHP
VILP
VOH[2]
VOL[2]
Ipp

Description

Min.
13.0

Max.
14.0

Units

4.75

5.25

V

0.4

V
V

Output Low Voltage

0.4

V
V

Programming Supply Current

50

rnA

Programming Voltage
Supply Voltage
Input High Voltage

3.0

Input Low Voltage
Output High Voltage

AC Programming Parameters TA

2.4

V

= 25°C
Table 2

Parameter
tpp

Deseription

Min.

Max.

Units

Programming Pulse Width

10,000

IA-s

tAS
tos
tAH

Address Setup Time
Data Setup Time
Address Hold Time

100
1.0

tOH
tR, tp[3]

Data Hold Time
Vpp Rise and Fall Time

tvo
tvp

Delay to Verify

1.0

Verify Pulse Width
Verify Data Valid
Verify HIGH to High Z

2.0

tov
toz

IA-s
IA-s

1.0
1.0

IA-s
IA-s
ns

1.0
50

IA-s
IA-S
1.0
1.0

Notes:
1. Vccp must be applied prior to Vpp.
2. Ouring verify operation.

3. Measured 10% and 90% points.

3-9

IA-S
IA-s

Table 3
Pin Function(1)
Read or Output Disable

Mode

Other

Pin
Read[2,3)

Output Disable(5)
Output Disable
CLEAR
PRESET
Program(4)
Program Verify(4)
Program Inhibitl4)
Intelligent Program(4)
Blank Check Ones(4)
Blank Check Zeros(4)

CP

Es

~

E

PGM

'WY

Vpp

(18)

(19)

(20)

E
(21)

(22)

X
X
X
X
X
VILP
VIHP
VIHP
VILP
Vpp
Vpp

VIL
VIH
X
VIL
VIL
VIHP
VILP
VIHP
VIHP
VILP
VIHP

VIH
VIH
VIH
VIL
VIH
Vpp
Vpp
Vpp
Vpp

VIL
X
VIH
VIL
VIL
VIHP
VIHP
VIHP
VIHP
VILP
VILP

VIH
VIH
VIH
VIH
VIL
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP

Notes:
\. X = Don't care but not to exceed Vpp.
2. Durin, read operation, the output latches are loaded on a ''0'' to "I"

VILP.

The CY7C225 programming algorithm allows significantly
faster programming than the "worst case" specification of
lOmsec.
Typical programming time for a byte is less than 2.5 msec.
The use of EPROM cells allows factory testing of programmed cells, measurement of data retention and erasure
to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.
The algorithm utilizes two differen;gulse types: initial and
M pulse (tpp) is 0.1
overprogram. The duration of the
msec which will then be followed by a longer overprogram
pulse of 24 (0.1) (X) msec. X is an iteration counter and is
equal to the NUMBER of the initial 0.1 msec pulses applied before verification occurs. Up to four 0.1 msec pulses
are provided before the overprogram pulse is applied.
The entire sequence of program pulses and byte verifications is performed at VCCP = 5.0V. When all bytes have
been programmed all bytes should be compared (Read
mode) to original data with Vec = 5.0V.

A6
As

E
VPP

Az
A,

PGM (tP)

Ao

D7

Do

D6

ii'FY (Es)

D,

D5

D2

D.

VSS

D3

Data Out
HighZ
HighZ
Zeros
Ones
Data In
Data Out
HighZ
Data In
Ones
Zeros

5. Pin 19 must be HIGH prior to the ''0'' to "I" transition on CP (18)
that loads the register.

A7

A3

Outputs
(9-11,13-17)

4. During programming and verification. all unspecified pins to be at

transition ofCP.
3. Pin 19 must be LOW prior to the "0" to "I" transition on CP (18)
that loads the register.

A.

VILP
VILP

liS
liS

0020-8

Figure 3. Programming Pinouts

3-10

~

CY7C225

. .,-~~===============================
START
Vecp - S.OV. Vpp - 13.5V

1
ADDR 1ST LOCATION

II

T

1
x=o

T

1
PROGRAM ONE PULSE
OFO.1msee

1
x-x + 1

1
X-4?

I

YES

J

INO
FAIL.

•

VERIFY ONE BYTE?

1

PASS

PROGRAM ONE PULSE
OF 2410.1) IX) m_

1

YES

X -4?

VERIFY BYTE

1

FAIL

DEVICE BAD

1

'PASS

r

NO

•

I

INC.ADDR

•
•

NO

•
•

LAST ADDRESS?

1

YES
FAIL

READ ALL BYTES?
Vee -S.OV

••

•

DEVICE BAD

I

I PASS
DEVICE GOOD
0020-9

Figure 4. Programming Flowchart

3-11

~
CY7C225
•
~~~~NDUcrOR======================================================================
Programming Sequence 512 x 8 Array
Power the device for normal read mode operation with pin
18, 19,20 and 21 at VIH. Per Figure 5 take pin 20 to Vpp.
The device is now in the program inhibit mode of operation
with the output lines in a high impedance state; see Figure
5. Again per Figure 5 address, program, and verify one
byte of data. Repeat this for each location to be programmed.

additional programming pulse should be applied of duration 24X the sum of the previous programming pulses before advancing to the next address to repeat the process.

Blank Check
A virgin device contains neither one's nor zero's because of
the differential cell used for high speed. To verify that a
PROM is unprogrammed, use the two blank check modes
provided in Table 3. In both of these modes, address and
read locations 0 thru 511. A device is considered virgin if
all locations are respectively'" 's" and "O's" when addressed in the "BLANK ONES AND ZEROS" modes.
Because a virgin device contains neither ones nor zeros, it
is necessary to program both one's and zero's. It is recommended that all locations be programmed to ensure that
ambiguous states do not exist.

If the brute force programming method is used, the pulse
width of the program pulse should be 10 ms, and each
location is programmed with a single pulse. Any location
that fails to verify causes the device to be rejected.

If the intelligent programming technique is used, the program pulse width should be 100 J.Ls. Each location is ultimately programmed and verified until it verifies correctly
up to and including 4 times. When the location verifies, one

PROGRAM
OTHER BYTES

PROGRAM

VERIFY

1-,

VIHP - - -

ADDRESS STABLE

ADDRESS
VllP - - -

....--tAS
.........
··~tDS"'"

'f

DATA

---

VILP - - -

tRI--

I+--tAS-

Vpp - - -

r-

PROGRAMMIN G
VOLTAGE !PIN 201
VIHP - - -

\

"-Ii

DATA IN

--

---

(

tov

\

DATA OUT

'-

~~----

tOH

(

Ii

~5

r

J

-----:;;j f-

_tpp--.

r

VIHP - - -

LJ

f-

5

tvP----'

i-----tvo

(

f0020-10

Figure 5. PROM Programming Waveforms

3-12

~
CY7C225
•
~~~NDUcrOR===================================================================
Ordering Information
Speed
ns
tSA
25

teo
12

30

15

35

20

40

25

Ordering
Code

Package
Type

Operating
Range

CY7C225-25PC
CY7C225-25DC
CY7C225-25LC
CY7C225-30PC
CY7C225-30DC
CY7C225-30LC
CY7C225-30DMB
CY7C225-30LMB
CY7C225-35DMB
CY7C225-35LMB
CY7C225-40PC
CY7C225-40DC
CY7C225-40LC
CY7C225-40DMB
CY7C225-40LMB

P13
014
L64
P13
014
L64
014
L64
DI4
L64
PI3
DI4
L64
DI4
L64

Commercial

Commercial

Military
Military
Commercial

Military

3-13

~
CY7C225
~~~D~==========================================================~
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH
VOL
VIH
VIL
IIX
Ioz
Icc

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

Switching Characteristics
Parameters

Subgroups

tSA

7,8,9,10,11

tHA

7,8,9,10,11

teo

7,8,9,10,11

tDP

7,8,9,10,11

tRP

7,8,9,10,11

Document #: 38-00002-B

3-14

CY7C235

CYPRESS
SEMICONDUCTOR

1024

X

8 Registered PROM

Features
• CMOS for optimum
speed/power

• 5V ± 10% Vee, commercial and
military

• High speed
- 25 ns max set-up
- 12 ns clock to output

• TTL compatible 110
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater
than 1500V static discharge

• Low power
- 495 mW (commercial)
- 660 mW (military)

Product Characteristics

• Synchronous and asynchronous
output enables

The CY7C235 is a high performance
1024 word by 8 bit electrically Programmable Read Only Memory packaged in a slim 300 mil plastic or hermetic DIP or 28-pin Leadless Chip carrier. The memory cells utilize proven
EPROM floating gate technology and
byte-wide intelligent programming algorithms.
The CY7C235 replaces bipolar devices
and offers the advantages oflower

• On-chip edge-triggered registers
• Programmable asynchronous
register (lNIT)
• EPROM technology, 100%
programmable
• Slim, 300 mil, 24 pin plastic or
hermetic DIP or 28 pin LCC

Logic Block Diagram

power, superior performance and high
programming yield. The EPROM cell
requires only 13.5V for the supervoltage and low current requirements allow
for gang programming. The EPROM
cells allow for each memory location to
be tested 100%, as each location is
written into, erased, and repeatedly
exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that after customer
programming the product will meet
AC specification limits.
The CY7C235 has an asynchronous
initialize function (INIT). This function acts as a 1025th 8-bit word loaded
into the on-chip register. It is user programmable with any desired word or
may be used as a PRESET or CLEAR
function on the outputs.

Pin Configurations

~-----i~~-----------------------,
0,

ROW

64 x 128

DECODER

PROGRAMMABLE
ARRAY

10F64

1+-0_0,
1+-0-0,

1+-0-0,
A3
A,
A,

0005-2

0,

COLUMN
DECODER
1 OF 16

0,

Au

./} ISooV
(Per MIL-STD-883 Method 301S)

Storage Temperature ............... -6SoC to + ISO"C
Ambient Temperature with
Power Applied .................... - SsoC to + 12SoC

Latch-up Current. ......................... > 200 rnA

Supply Voltage to Ground Potential
(Pin 24 to Pin 12for DIP) ............. -O.SV to +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to.+7.0V

Ambient
Temperature

Range

DClnputVoltage ................... -3.0Vto +7.0V

Commercial
Military(6)

DC Program Voltage
(Pins 7, 18,20 for DIP) ........................ 14.0V

Vee

O"Cto +70"C

sv ±1O%

- 55°C to + 125°C

SV ±1O%

Electrical Characteristics Over Operating Range(7)
Parameters

Desc:ription

Test Conditions

Min..

VOH

Output HIGH Voltage

Vee = Min.,IOH = -4.0rnA
VIN = VIR or VIL

VOL

Output LOW Voltage

Vee = Min.,IOL = 16mA
VIN = VIR or VIL

VIH

Input HIGH Level

Guaranteed Input Logical HIGH
Voltage for All Inputs(2)

VIL

Input LOW Level

Guaranteed Input Logical LOW
Voltage for All Inputs!2]

IIX

Input Leakage Current

GND!5: VIN!5: Vee

VeD

Input Clamp Diode
Voltage

Note 1

loz

Output Leakage Current

GND !5: Vo !5: Vee Output Disabled!4]

los

Output Short Circuit
Current

Vee

lee

Power Supply Current

GND !5: VIN !5: Vee
Vee = Max.

Units

2.4

V
0.4

= Max., VOUT = 0.OV!3]'

I
I

Max.

V

2.0

V
0.8

V

-10

+10

/-LA

-40

+40

/-LA

-20

-90

rnA

Commercial

90

Military

120

mA

Capacitance [5]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions
TA = 25°C, f
Vee = S.OV

Notes:
1. The eMOS process does not provide a clamp diode. However, the
eY7e23S is insensitive to - 3V dc input levels and - SV undershoot
pulses ofless than 10 ns (measured at SO% point).
2. These are absolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise. Do not at·
tempt to test these values without suitable equipment (see Notes on
Testing).
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.

=

1 MHz

Max.
5
8

Units
pF

4. For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
S. Tested initially and after any design or process changes that may
affect these parameters.
6. TA is the "instant on" case temperature.
7. See the last page of this specification for Group A subgroup testing
information.

3-16

~

CY7C235

~~~DUcroR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
Switching Characteristics Over Operating Range[4, 8]
Parameters

7C23S-30

7C23S-2S

Description

Min.

Max.

Min.

Max.

7C23S-40
Min.

Units

Max.

tSA

Address Setup to Clock HIGH

25

30

40

tHA

Address Hold from Clock HIGH

0

0

0

teo

Clock HIGH to Valid Output

tpwe

Clock Pulse Width

12

15

20

ns

tSEs

Es Setup to Clock HIGH

10

10

15

ns

tHEg

Es Hold from Clock HIGH

5

5

5

tm

Delay from INIT to Valid Output

tRI

INIT Recovery to Clock HIGH

20

tpwi

INIT Pulse Width

20

teos

Inactive to Valid Output from Clock HIGH[I]

20

20

25

ns

tHze

Inactive Output from Clock HIGH[J, 3]

20

20

25

ns

tOOE

Valid Output from E LOW[2]

20

20

25

ns

Inactive Output from E HIGH[2, 3]

20

20

25

ns

tHZE
Notes:

12

15

25

4.
S.
6.
7.
8.

1. Applies only when the synchronous (ES) function is used.
2. Applies only when the asynchronous (E) function is used.
3. Transition is measured at steady state High level - SOO m V or steady
state Low level + SOO m Von the output from the I.SV level on the
input with loads shown in Figure 1b.

ns·

20

25
20

ns

ns

35
20

20

ns

ns
ns

25

ns

Tests are performed with rise and fall times of S ns or less.
See Figure 1a for all switching characteristics except tHZ.
See Figure 1 b for tHZ.
All device test loads shonld be located within 2" of device outputs.
See the last page of this specification for Group A subgroup testing
information.

AC Test Loads and Waveforms [5,6,71
Rl 250 U

Rl 250 U

ALL INPUT PULSES

5Vo-------JV~-,

5Vo-------~~~,

OUTPUT o---~p---------i

OUTPUT o - - - - - _ - - - - - - - i

I

I

R2
167 Sl

50pF

INCLUDING
JIG AND
-::' SCOPE
-::'

5 pF

3.0 V ---------.z=~--"""!IL

R2
167Sl

GND

--""f

<;5 os

<5ns

0005-5

INCLUDING
_JIGAND _
- SCOPE
-

Figure 2
0005-3

Figure 1b

Figure 1a
Equivalent to:

THEVENIN EQUIVALENT
looU

OUTPUT~2.0V

0005-4

Functional Description
applying the memory location to the address input (AoA9) and a logic LOW to the enable (Es) input. The stored
data is accessed and loaded into the master flip-flops of the
data register during the address set-up time. At the next
LOW·to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (0007) provided the asynchronous enable (E) is also LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the enable to a
logic LOW.

The CY7C235 is a CMOS electrically Programmable Read
Only Memory organized as 1024 word x 8-bits and is a pin·
for·pin replacement for bipolar TTL fusible link PROMs.
The CY7C235 incorporates a D·type, master·slave register
on chip, reducing the cost and size of pipelined micropro·
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is provided with synchronous (Es) and asynchronous
(E) output enables and asynchronous initialization (INIT).
Upon power-up, the synchronous enable (ES) flip-flop will
be in the set condition causing the outputs (00-07) to be
in the OFF or high impedance state. Data is read by
3-17

~
CY7C235
~~~~u~==============================================================~
Functional Description (Continued)

Regardless of the condition of B, the outputs will go to the
OFF or high impedance state upon the next positive clock
edge after the synchronous enable (Bs) input is switched to
a HIGH level. If the synchronous enable pin is switched to
a logic LOW, the subsequent positive clock edge will return the output to the active state ifE is LOW. Following a
positive clock edge, the address and synchronous enable
inputs are free to change since no change in the output will
occur until the next low to high transition of the clock.
This unique feature allows the CY7C235 decoders and
sense amplifiers to access the next location while previously
addressed data remains stable on the outputs.

and the initialize function can be used to load any desired
combination of"I"s and "O"s into the register. In the unprogrammed state, activating mrr will generate a register
CLEAR (all outputs LOW). If all the bits of the initialize
word are programmed, activating 00'f performs a register
PRESET (all outputs HIGH).
Applying a LOW to the !NIT input causes an immediate
load of the programmed initialize word into the master and
slave flip-flops of the register, independent of all other inputs, including the clock (CP). The initialize data will appear at the device outputs after the outputs are enabled by
bringing the asynchronous enable (B) LOW.
When power is applied the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in
the high impedance state. In order to enable the outputs, a
clock must occur and the ES input pin must be LOW at
least a setu~time prior to the clock LOW to HIGH transition. The E input may then be used to enable the outputs.
When the asynchronous initialize input, INIT, is LOW,
the data in the initialize byte will be asynchronously loaded
into the output register. It will not, however, appear on the
output pins until they are enabled, as described in the preceding paragraph.

System timing is simplified in that the on-chip edge triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar
to those of discrete registers available in the market.
The CY7C235 has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and timeout sequences and can facilitate implementation of other
sophisticated functions such as a built-in "jump start" address. When activated the initialize control input causes the
contents of a user programmed 1025th 8-bit word to be
loaded into the on-chip register. Each bit is programmable

Switching Waveforms
A~A,O ________________________________~---J~~~----~--~WW~~~~~-------------------

Es

- - - - -......"'l

cp

00-07

----~----~~--~

0005-6

Notes on Testing
Incoming test procedures on these devices should be carefully planned,
taking into account the high performance and output drive capabilities of
the parts. The following notes may be useful.
1. Ensure that adequate decoupling capacitance is employed across the
device Vee and ground terminals. Multiple capacitors are recommended, including a 0.1 p.F or larger capacitor and a 0.01 p.F or
smaller capacitor placed as close to the device terminals as pcssible.
Inadequate decoupling may result in large varistions of pcwer supply
voltage, creating erroneous function or transient performance failures.
2. Do not leave any inputs disconnected (floating) during any tests.

3. Do not attempt to perform threshold tests under AC conditions.
Large amplitude, fast ground current transients normally occur as the
device outputs dischar~ the load capacitances. These transients flowing through the parasitIC inductance between the device ground pin
and the test system ground can create significant reductions in observable input noise immunity.
4. Output levels are measured at l.SV reference levels.
S. Transition is measured at steady state HIGH level - 500 mV or
steady state LOW level + 500 mV on the output from the l.SV level
on inputs with load shown in Figure lb.

3-18

~
CY7C235
~~~NDU~~~===============================================================
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
1.8

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VI. SUPPLY VOLTAGE

NORMALIZED CLOCK TO OUTPUT
TIME VI. Vee

VI.

1.2.-----.,.....-----..,

w

1.6

~

;::
1.4

o

"':::;N

.~

~

1.2

/

1.0

IV V

~

~o

/

]

...'"

~
w

.

TA·25'C
I-MAle.

4.5

5.0

0·&~55~---~25~-----~125

8.0

5.5

o
z

NORMALIZED CLOCK TO OUTPUT
TIME VI. TEMPERATURE

NORMALIZED SETUP TIME
VI. SUPPLY VOLTAGE

"'~

;::

...

/

~

TA
0.6
4.0

4.5

.............
1.0

/

"':::;

NORMALIZED SETUP TIME
TEMPERATURE

~

0.&

...

..
"'
..

i'-...

Q

~

1.2

C

~

1.0

0

z

0.6

-

-

N

:::;

C

~

1.4

:)

t;

N

.

6.0

YS.

............

~

0

i 25'C

5.5

1.6

:)

~

5.0

SUPPLY VOLTAGE (VI

1.2

1.2

0.8

AMBIENT TEMPERATURE ('CI

1.4

1.0

--- -

:::;

SUPPLY VOLTAGE (VI

1.6

" b-....

1,0

N

~

II

r-...

1.2

I=!

o.

O.6
4.0

1.4

0.8

TA i25'C
0.4
4.0

0.6
-5&

25

125

AMBI ENT TEMPERATUR E ('CI

60

4.5

5.0

5.5

.."'

Ii

OUTPUT SOURCE CURRENT
VI. OUTPUT VOLTAGE

30.0

50

40

~

u

."'
u

~

51

30
20

"""

~

S
0

10

o
o

1.0

!

-

".'"
2.0

~
C
!:i

/

20.0

/

15.0

~ 10.0

"'"

3.0

OUTPUT VOLTAGE (VI

4.0

5.0
0.0

V
200

175
;(

!

..

125

~

100

iii

!5...
!50

TA·25'C
Vee -4.5V

400

600

CAPACITANCE (pFI

BOO

125

1000

OUTPUT SINK CURRENT
VI. OUTPUT VOLTAGE

150

z~w

"'Z"

/

/

o

25
AMBIENT TEMPERATURE ('CI

TYPICAL ACCESS TIME CHANGE
VI. OUTPUT LOADING

25.0

~

-55

SUPPLY VOLTAGE (VI

;(

!

0.6

8.0

",.

/

1/

75
50
25

I
o
0.0

V'

/

Vee -5.0 V
TA -25'C

J
1.0

--

2.0

3.0

4.0

OUTPUT VOLTAGE (VI
0005-7

3-19

Device Programming
Overview:
There are two independent programmable functions contained in the 7C235 CMOS lK x 8 Registered PROM; the
lK x 8 array, and the INITIAL BYTE. All of the programming elements are "EPROM" cells, and are in an
erased state when the device is shipped. The erased state
for the "INITIAL BYTE" is all "O's" or "LOW". The
"INITIAL BYTE" may be accessed operationally through

DC Programming Parameters

TA

the use of the initialize function. The lK x 8 array uses a
differential memory cell, with differential sensing techniques. In the erased state the cell contains neither a one
nor a zero. The erased state of this array may be verified by
using the "BLANK CHECK ONES" and "BLANK
CHECK ZEROS" function, see Table 3.

= 25°C
Table 1

Parameter
Vpp!t!

Description

Min.

Max.

Units

Programming Voltage

13.0

14.0

V

Vccp

Supply Voltage

4.75

5.25

V

VIHP

Input High Voltage

3.0

VILP
VOH[2!

Input Low Voltage

0.4

V

Output High Voltage

VOL[2!

Output Low Voltage

0.4

V

Ipp

Programming Supply Current

50

mA

AC Programming Parameters TA

V

2.4

V

= 25°C

Table 2
Description

Min.

Max.

Units

tpp

Parameter

Programming Pulse Width

100

10,000

/Ls

tAS

Address Setup Time

1.0

/Ls

tos

Data Setup Time

1.0

/Ls

tAH

Address Hold Time

1.0

/Ls

tOH
tR,tp[3!

Data Hold Time

1.0

JLs

Vpp Rise and Fall Time

1.0

/Ls

tvo

Delay to Verify

1.0

/Ls

tvp

Verify Pulse Width

2.0

tov

Verify Data Valid

1.0

/Ls

toz

Verify HIGH to High Z

1.0

/Ls

Notes:
I. Vccp must be applied prior to Vpp.
2. Ouring verify operation.
3. Measured 10% and 90% points.

3-20

/Ls

~

CY7C235

~~~6NDUcrOR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Mode Selection
Table 3
Pin Function
CP

Es

INIT

Other

A2
A2

PGM

VFY

Vpp

E
E

Al
Al

(DIP) Pin

Read or Output Disable
Mode

Outputs
(9-11,13-17)
DIP

(6)

(18)

(19)

(20)

(21)

(7)

Read[2,3]

X

X

VIL

VIH

VIL

X

Data Out

Output Disabld5]

X

X

VIH

VIH

X

X

HighZ

Output Disable

X

X

X

VIH

VIH

X

HighZ

Initialize[6]

X

X

X

VIL

VIL

X

1025th word

Program [1,4]

X

VILP

VIHP

Vpp

VIHP

X

Data In

Program Verify [1,4]

X

VIHP

VILP

Vpp

VIHP

X

Data Out

Program Inhibit[I,4]

X

VIHP

VIHP

Vpp

VIHP

X

HighZ

Intelligent Program[I,4]

X

VILP

VIHP

Vpp

VIHP

X

Data In

Program Initial Byte [4]

VILP

VILP

VIHP

Vpp

VIHP

Vpp

Data In

Blank Check Ones[I,4]

X

Vpp

VILP

X

Ones

Blank Check Zeros[I,4]

X

Vpp

VILP

X

Zeros

VILP
VIHP

Notes:
1. X = Don't care but not to exceed Vpp.

VILP
VILP

4. During programming and verification, all unspecified pins to be at
VILP·

2. During read operation, the output latches are loaded on a "0" to "1"

5. Pin 19 must be HIGH prior to the "0" to "I" transition on CP (18)
that loads the register.
6. LOW to HIGH clock transition required to enable outputs.

transition of CPo
3. Pin 19 must be LOW prior to the "0" to "I" transition on CP (18)
that loads the register.

The CY7C23S programming algorithm allows significantly
faster programming than the "worst case" specification of
IOmsec.
A,

Vee

A6

As

A,

A.

A.

E

AJ

Vpp liiiITfl

A2
A,

VFV IEsl
PGM ICPI

Ao

D,

Do

D,

D,

D,

D2

D.

Vss

D3

Typical programming time for a byte is less than 2.5 msec.
The use of EPROM cells allows factory testing of programmed cells, measurement of data retention and erasure
to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.
The algorithm utilizes two different pulse types: initial and
overprogram. The duration of the PGM pulse (tpp) is 0.1
msec which will then be followed by a longer overprogram
pulse of 24 (0.1) (X) msec. X is an iteration counter and is
equal to the NUMBER of the initial 0.1 msec pulses applied before verification occurs. Up to four 0.1 msec pulses
are provided before the overprogram pulse is applied.
The entire sequence of program pulses and byte verifications is performed at VCCP = S.OV. When all bytes have
been programmed all bytes should be compared (Read
mode) to original data with V cc = S.OV.

0005-6

Figure 3. Programming Pinouts

3-21

START
Vecp - 5.OV. Vpp

= 13.5V

1
ADDR 1ST LOCATION

I

1
x-o

I

1
PROGRAM ONE PULSE
OFO.1msec

1
X-X'1

I
X-4?

I

YES

I

INO
FAIL

I

1

VERIFY ONE BYTE?

1

PASS

PROGRAM ONE PULSE
OF 24 10.nIX) msec

1

YES

X -4?

FAIL
DEVICE BAD

VERIFY BYTE

1

1

'PASS

r

NO

I
I

INC.ADDR

I
I

NO

I
I

LAST ADDR ESS?

!

YES

FAIL

READ ALL BYTES?
Vee -s.OV

J
I

DEVICE BAD

I

1

PASS

DEVICE GOOD

0005-9

Figure 4. Programming Flowchart

3-22

~

CY7C23S

~ ~~aOR===================================================================

Programming Sequence lK x 8 Array
Power the device for normal read mode operation with pin
18, 19,20 and 21 at VIH. Per Figure 6 take pin 20 to Vpp.
The device is now in the program inhibit mode of operation
with the output lines in a high impedance state; see Figures
5 and 6. Again per Figure 6 address program and verify
one byte of data. Repeat this for each location to be programmed.
If the brute force programming method is used, the pulse
width of the program pulse should be 10 ms, and each

location is programmed with a single pulse. Any location
that fails to verify causes the deviceto be rejected.
If the intelligent programming technique is used, the program pulse width should be 100 !kS. Each location is ultimately programmed and verified until it verifies correctly
up to and including 4 times. When the location verifies, one
additional programming pulse should be applied of duration 24X the sum of the previous programming pulses before advancing to the next address to repeat the process.

:1

PROGRAM

1----- PROGRAM _ _ _-t-_--VERIFY--_t---OT-H~ER BYTES
VIHP

-A:~RESS

- - -... I / - - - - - - A - D - D - R E - S S - S T - A B - L E - I - - - - - - - - - . . I . r - - - l

VILP - - -

----

•
tAS

Vu..P - - -

J---+-"""; 1 1 - - - - - -

DATA IN

DATA - - - - - - (

'--+--~to"'H.II

V'lP - - -

'----=='""!I~

Vpp - - -

VIHP---

VILP--VIHP---

PG!.l
VILP---

tv,

VIHP - - -

0005-10

Figure 5. PROM Programming Waveforms

_ _~I~----------------PROGRAMI------------------.k--VIL.P---

I/pp - - -

VIHP---

VIHP---

DATA

---+---_....

VILP---

!---------.AH----------I
I/pp---

PROGRAMMING
VOLTAGE (PIN 20, Dip)
VIHP---

...
PGM
0005-11

Figure 6. Initial Byte Programming Waveforms

3-23

3

~
CY7C235
~~~aoR;============================================================
Programming the Initial Byte

Blank Check

The CY7C235 registered PROM has a 1025th byte of data
used to initialize the value of the register. This initial byte
is value "0" when the part is received. If the user desires to
have a value other than "0" for register initialization, this
must be programmed into the 1025th byte. This byte is
programmed in a similar manner to the 1024 normal bytes
in the array except for two considerations. First, since all of
the normal addresses of the part are used up, a super voltage will be used to create additional effective addresses.
The actual address has Vpp on Al pin 7, and VILP on A2,
pin 6, per Table 3. The programming and verification of
"INITIAL BYTE" is accomplished operationally by performing an initialize function.

A virgin device contains neither one's nor zero's because of
the differential cell used for high speed. To verify that a
PROM is unprogrammed, use the two blank check modes
provided in Table 3. In both of these modes, address and
read locations 0 thru 1023. A device is considered virgin if
all locations are respectively "I 's" and "O's" when addresses in the "BLANK ONES AND ZEROS" modes.

Bit Map Data

Ordering Information

Because a virgin device contains neither ones nor zeros, it
is necessary to program both one's and zero's. It is recommended that all locations be programmed to ensure that
ambiguous states do not exist.

RAM Data

Speed

Decimal

Hex

Contents

ns

0

0

Data

Programmer Address

•
•
•

1023
1024

•
•
•

3FF
400

•
•
•

Data
Init Byte

Package
Type

Operating
Range
Commercial

tSA

teo

25

12

CY7C235-25PC
CY7C235-25DC

P13
D14

30

15

CY7C235-30PC
CY7C235-30DC
CY7C235-3OJC

P13
D14
J64

CY7C235-30DMB
CY7C235-30LMB

D14
L64

Military

CY7C235-4OPC
CY7C235-4ODC

P13
D14

Commercial

CY7C235-40DMB
CY7C235-40LMB

D14
L64

Military

40

3-24

Ordering
Code

20

~
CY7C235
•
~~~NDUaoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

IOZ

1,2,3

Icc

1,2,3

Switching Characteristics
Parameters

Subgroups

tSA

7,8,9,10,11

tHA

7,8,9,10,11

teo

7,8,9,10,11

Document #: 38-00003-B

3-25

CY7C245

CYPRESS
SEMICONDUCTOR

Reprogrammable 2048 X 8
Registered PROM

Features
• Windowed for reprogrammabllity
• CMOS for optimum
speed/power
• High speed

-

25 os max set-up
12 os clock to output

• Low power
- 330 mW (commercial) for
-35 ns, -45 os
- 660 mW (military)

• Programmable synchronous or
asynchronous output enable
• On-chip edge-triggered registers
• Programmable asynchronous
register (INlT)

• 5V ± 10% Vcc. commercIal and
military

• EPROM technology, 100%
programmable

• Capable of withstanding greater
than 2000V static discharge

• TIL compatIlIle I/O
• Direct replacement for bipolar
PROMs

• Slim, 300 mil, 24 pin plastic or
hermetic DIP

Logic Block Diagram

Pin Configurations

~------r>~----------------------,

A'D

Ae
A8
A7
As

iiiii'i'

I--D-O,

A,.
ROW
OECODER
1 OF 128

128 x 128

E/Es
CP

1-+-1::1- 0 •

PROGRAMMABLE
ARRAY

07
06

I-+...D-o,

A.
A,

Os

1-+-0_0,

O.

-O,

"'-_ _....r 03

L...J...........

A,
A,
A,

An

COLUMN
DECODER
1 OF 16

0016... 2

1-+-0_0,

1-----------------'

I-----------------...,j

~~.("~~~~

0,

A45
A3 6

e(![s----il

A2

CP--t;>-."IL........J
0016... 1

4 3 2 :,'282726
•••
25~
24 INIT

7

AlB
9
HC 10

Ao

00

0

23 flEs
22CP
21
20

NC
07

'\2'3'4'5'6'7,~9

0&

0016... 13

Selection Guide
7C245-25

7C245-35

7C245-45

25
12
90

Military

35
15
90
120

45
25
90
120

Commercial

60

60

Maximum Setup Time (ns)
Maximum Clock to Output (ns)
Maximum Operating
Current (mA)

STD
L

Commercial

3-26

~

CY7C245

~~~~R~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Product Characteristics

Maximum Ratings

The CY7C24S is a high performance 2048 word by 8 bit
electrically Programmable Read Only Memory packaged
in a slim 300 mil plastic or hermetic DIP. The ceramic
package may be equipped with an erasure window; when
exposed to UV light the PROM is erased and can then be
reprogrammed. The memory cells utilize proven EPROM
floating gate technology and byte-wide intelligent programming algorithms.
The CY7C24S replaces bipolar devices and offers the advantages oflower power, reprogrammability, superior performance and high programming yield. The EPROM cell
requires only 13.SV for the supervoltage and low current
requirements allow for gang programming. The EPROM
cells allow for each memory location to be tested 100%, as
each location is written into, erased, and repeatedly exercized prior to encapsulation. Each PROM is also tested for
AC performance to guarantee that after customer programming the product will meet AC specification limits.
The CY7C24S has an asynchronous initialize function
(INIT). This function acts as a 2049th 8-bit word loaded
into the on-chip register. It is user programmable with any
desired word or may be used as a PRESET or CLEAR
function on the outputs.

(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ............... - 65°C to + 150"C
Ambient Temperature with
Power Applied .................... - 5S0C to + 12S0C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... - O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to + 7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
DC Program Voltage (Pins 7, 18,20) ............. 13.0V
UV Erasure .......................... 7258 Wsec/cm2
Static Discharge Voltage ..................... > 200 1V
(per MIL-STD-883 Method 3015)
Latchup Current .......................... > 200 mA

Operating Range
Range

Ambient
Temperature

Commercial
Military!71

O"Cto +70"C
- SsoC to + 12SoC

Vee
SV ±1O%
SV ±1O%

Electrical Characteristics Over Operating Range!61
Parameters

Description

7C245L-35, 45

Test Conditions
Vee = Min.,IOH = -4.0mA
VIN = VIH or VIL
Vee = Min., IOL = 16mA
VIN = VIH or VIL
Guaranteed Input Lo~cal HIGH
Voltage for All Inputs II

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Level

VIL

Input LOW Level

Guaranteed Input Lo~cal LOW
Voltage for All Inputs II

IIX

Input Leakage Current

GND ::;; VIN ::;; Vee

Veo

Input Clamp Diode
Voltage

NoteS

lOS

Output Leakage Current GND::;; VO::;; Vw:
Output Disabled!3
Output Short Circuit
Vee = Max., VOUT
Current

lee

Power Supply Current

IOZ

7C245-25

7C245-35, 45

Min.

Max. Min. Max.

Min.

2.4

2.4

2.4

0.4
2.0

Vee
0.8

-10

+10

0.4
2.0

Vee

Units
V

0.4

V

Vee

V

0.8

V

-10

+10

/LA

2.0

0.8

-10 +10

Max.

NoteS

= 0.OVC21

GND ::;; VIN ::;; Vee
Vee = Max.

-40

+40

-40 +40

-40

+40

/LA

-20

-90

-20 -90

-20

-90

rnA

ICommercial
IMilitary

60

90

90

rnA

120

Capacitance [4]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions
TA = 25°C, f
Vee = S.OV

Notes:
1. These are absolute voltages witb respee! to device ground pin and
include all overshoots due to system and/or tester noise. Do not at·
tempt to test tbese values without suitable equipment (see Notes on
Testing).
2. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
3. For devices using tbe synchronous enable, the device must be clocked
after applying tbese voltages to perform tbis measurement.

=

I MHz

Max.
5

Units
pF

8

4. Tested initially aud after any design or process changes that may
affect these parameters.
5. The eMOS process does not provide a clamp diode. However, the
eY7e245 is insensitive to - 3V dc input levels and - 5V undershoot
pulses ofless than 10 ns (measured at 50% point).
6. See the last page of tbis specification for Group A subgroup testing
information.
7. TA is the "instant on" case temperature.
3-27

II

~

CY7C245

~~~==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Switching Characteristics Over Operating Range[8]
Parameters

7C245-35

7C245-25

Description

Min.

Max.

Min.

7C245-45

Max.

Min.

Units

Max.

tSA

Address Setup to Clock HIGH

25

35

45

tHA

Address Hold from Clock HIGH

0

0

0

teo

Clock HIGH to Valid Output

tpwc

Clock Pulse Width

15

20

20

ns

tSEg

12

15

15

ns

12

15

ns
ns
25

ns

tHEg

Es Setup to Clock HIGH
Es Hold from Clock HIGH

tOl

Delay from INIT to Valid Output

tRI

INIT Recovery to Clock HIGH

15

20

20

ns

tpWI

INIT Pulse Width

15

20

25

ns

!cos

Valid Output from
Clock HIGHU]

15

20

30

ns

tHZc

Inactive Output from Clock HIGH[l, 3]

15

20

30

ns

tDOE

Valid Output from E LOW[2]

15

20

30

ns

tHZE

Inactive Output from
EHIGH[2,3j

15

20

30

ns

5

5

5
20

Notes:
1. Applies only when the syochronous (Es) function is used.
2. Applies only when the asyochronous (E) function is used.
3. Transition is measured at steady state High level - 500 m V or steady
state Low level + 500 mV on the output from the 1.5V level on the
input with loads shown in Figure 1h.
4. Tests are performed with rise and fall times of 5 ns or less.

5.
6.
7.
8.

20

ns
35

ns

See Figure 1a for all switching characteristics except tHZ.
See Figure 1 h for tHZ.
All device test loads should he located within 2' of device outputs.
See the last page of this specification for Group A subgroup testing
information.
.

AC Test Loads and Waveforms[5, 6, 7]
OUTPUT

5v

0--_-----.

I

50pF

ALL INPUT PULSES

R1250fl:

R1 250 U
5 V O----J\f\I'y--,

OUTPUT

0----'1""'-,
0--_-----1

I-:-

~:7 n

,NCLUDING
JIG AND
":'" SCOPE
':"'

5pF

3.0 V-----~'!'"'---_'!l.

R2
187n

GND

~~~:D

1l'i;5ns

..;;5 ns

INCLUDING

-=

0016-5

Figure 2

0016-3

Figure Ib

Figure la
Equivalent to:

THEVENIN EQUIVALENT
100n

OUTPUT ~2.0V

0016-4

Functional Description
(00-07) to be in the OFF or high impedance siate. If the
asynchronous enable (E) is being used, the outputs will
come up in the OFF or high impedance state only if the
enable (E) input is at a HIGH logic level. Data is read by
applying the memory location to the address inputs
(Ao-AIO) and a logic LOW to the enable input. The stored
data is accessed and loaded into the master flip-flops of the
data register during the address set-up time. At the next
LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs
(00-0 7).
If the asynchronous enable (E) is being used, the outputs
may be disabled at any time by switching the enable to a

The CY7C245 is a CMOS electrically Programmable Read
Only Memory organized as 2048 words x 8-bits and is a
pin-for-pin replacement for bipolar TTL fusible link
PROMs. The CY7C245 incorporates a D-type, masterslave register on chip, reducing the cost and size of pipelined microprogrammed systems and applications where
accessed PROM data is stored temporarily in a register.
Additional flexibility is provided with a programmable
synchronous (Es) or asynchronous (E) output enable and
asynchronous initialization (INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (Es or E). If the
synchronous enable (Es) has been programmed, the register will be in the set condition causing the outputs
3-28

~CYPRESS

CY7C245

~~~IOO~~======================================================~~~~~
Functional Description (Continued)
logic HIGH, and may be returned to the active state by
switching the enable to a logic LOW.
If the synchronous enable (Es) is being used, the outputs
will. ~o to the OFF or high impedance state upon the next
pO~ltlve clock edge after the synchronous enable input is
sw~tched to a HI~H level. Ifthe synchronous enable pin is
SWItched to a lOgic LOW, the subsequent positive clock
edge will return the output to the active state. Following a
positive clock edge, the address and synchronous enable
inputs are. free to change since no change in the output will
occur until the next low to high transition of the clock.
This unique feature allows the CY7C245 decoders and
sense amplifiers to access the next location while previously
addressed data remains stable on the outputs.
System ti~ing is simplified in that the on-chip edge triggered regIster allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar
to those of discrete registers available in the market.

The CY7C245 has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and timeout sequences and can facilitate implementation of other
sophisticated functions such as a built-in "jump start" address. When activated the initialize control input causes the
contents of a user programmed 2049th 8-bit word to be
loaded into the on-chip register. Each bit is programmable
and the initialize function can be used to load any desired
combination of"l"s and "O"s into the register. In the unprogrammed state, activating mIT will generate a register
CLEAR (all outputs LOW). If all the bits of the initialize
word are programmed, activating INIT performs a register
PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate
load of the programmed initialize word into the master and
slave flip-flops ofthe register, independent of all other inputs, including the clock (CP). The initialize data will appear at the device outputs after the outputs are enabled by
bringing the asynchronous enable (E) LOW.

Switching Waveforms

CP

0016-6

Notes on Testing
Inc?m~g test procedur~ on these devices should be carefully planned.
taking Into account the high performance and output drive capabilities of
the parts. The following notes may be useful.
1. Ensure that adequate decoupling capacitance is employed across the
device Vee and ground terminals. Multiple capacitors are recommended, incl~ding a 0.1 p.F or larger capacitor and a om p.F or
smaller capllCltor placed as close to the device terminals as possible.
Inadequate decoupling may result in large variations of power supply
voltage. creating erroneous function or transient performance failures.
2. Do not leave any inputs disconnected (floating) during any tests.

3. Do not attempt to perform threshold tests under AC conditions.
Large amplitude. fast ground current transients normally occur as the
~evice outputs discharl!e the load capacitances. These transients flowIng through the parasitic Inductance between the device ground pin
and the test system ground can create significant reductions in observable input noise immunity.
4. Output levels are measured at l.SV reference levels.
S. Transition is measured at steady state HIGH level -500mV or
steady state LOW level + 500 m Von the output from the 1.5V level
on inputs with load shown in Figure 1b.

3-29

3

~

CY7C245

~r~~~=================
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE

CLOCK TO OUTPUT TIME
vs. Vee

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

1.2.------T""------,

1.6

w
:Ii

1.6

i=

1A

/

1.2
1.0

0.8

/

V

V

5
~
o
l:!

d
Q

TA

~

=25'C

4.5

5.0

6.6

O.S~56~~----:'25~----~I25

6.0

SUPPLY VOLTAGE (V)

~

l:!

9u

a

1.4

i=

./

~
::;

~

i

/

-----

1.0

Q

0.8

...

I-

w
w

O.S

N

::;

~

"02

""

25

0.4
4.0

125

rc)

50

25.0

~

:;)

u
u

30

"

20

:;)

~

.....

"

~

I-

:;)

10

:;)

0

o

o

1.0

5.5

6.0

1.4

~Q

1.2

:;)

"

-

w

N

::;

«

a

"02

"

4.5

!

20.0

1.0
~

0.8

'"""
3.0

OUTPUT VOLTAGE (V)

0.6

6.0

5.5

«~

15.0

/

-56

4.0

:!:

10.0
5.0
0.0

V

-

/

175

1
!Zw

""G
'"05Z

i5

TA·25'C
vee -4.6V

0

V

o

200

400

600

CAPACITANCE (pF)

25

125

AMBIENT TEMPERATURE ('C)

L

~

2.0

6.0

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0

w

...

SUPPLY VOLTAGE (V)

60

40

6.0

NORMALIZED SETUP TIME
vs. TEMPERATURE

0.6

OUTPUT SOURCE CURRENT
vs.VOLTAGE

2
w

4.5

TA i2S'C

AMBIENT TEMPERATURE

.s<
I-

""-

:;)

III
Q

0.6

-55

TA j25°C
0.6
4.0

1.6

..............
1.0

-

SUPPLY VOLTAGE (V)

,

1.2

w

1.2

~

---

O.B

NORMALIZED SETUP TIME
vs. SUPPLY VOLTAGE

i=

I.-

1.0

rc)

AMBIENT TEMPERATURE

CWCK TO OUTPUT TIME
vs. TEMPERATURE

1.6

",

r-....

1.2

~
::;
'-MAX.

O.6
4.0

1.4

SOD

1000

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

150
125

/

100

25

....... ~

I/

75

50

V-

Vee -6.0V

I

TA -25'C

/

If
o
0.0

1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

0016-7

3-30

Erasure Characteristics

Device Programming

Wavelengths of light less than 4000 Angstroms begin to
erase the 7C245. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.

OVERVIEW:
There are three independent programmable functions contained in the 7C245 CMOS 2K x 8 Registered PROM; the
2K x 8 array, the initial byte, and the synchronous enable
bit. All of the programming elements are "EPROM" cells,
and are in an erased state when the device is shipped. This
erased state manifests itself differently in each case. The
erased state for ENABLE bit is the "ASYNCHRONOUS
ENABLE" mode. The erased state for the "INITIAL
BYTE" is all "O's" or "LOW". The "INITIAL BYTE"
may be accessed operationally thru the use of the initialize
function. The 2K x 8 array uses a differential memory cell,
with differential sensing techniques. In the erased state the
cell contains neither a one nor a zero. The erased state of
this array may be verified by using the "BLANK CHECK
ONES" and "BLANK CHECK ZEROS" function, see
Table 3.

The recommended dose for erasure is ultraviolet light with
a wavelength of2537 Angstroms for a minimum dose (UV
intensity X exposure time) of25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 30-35 minutes. The 7C245
needs to be within 1 inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high
intensity UV light for an extended period of time. 7258
Wsec/cm2 is the recommended maximum dosage.

DC Programming Parameters TA

= 25°C

Table 1
Parameter
Vpp[I)

Description

Min.

Max.

Units

Programming Voltage

12.0

13.0

V

Vccp

Supply Voltage

4.75

5.25

V

VIHP

Input High Voltage

3.0

VILP
VOH[2)

Input Low Voltage
Output High Voltage

VOL[2)

Output Low Voltage

0.4

V

Ipp

Programming Supply Current

50

rnA

AC Programming Parameters TA

V
0.4

2.4

V
V

= 25°C

Table 2
Description

Min.

Max.

Units

tpp

Programming Pulse Width

100

10,000

/Ls

tAS

Address Setup Time

1.0

tos

Data Setup Time

1.0

/Ls

tAH

Address Hold Time

1.0

/Ls

tOH
tR, tp[3)

Data Hold Time

1.0

/Ls

Vpp Rise and Fall Time

1.0

/Ls

tvo

Delay to Verify

1.0

/Ls

tvp

Verify Pulse Width

2.0

tov

Verify Data Valid

1.0

/Ls

toz

Verify HIGH to High Z

1.0

JJ.s

Parameter

Notes:
1. Vccp must be applied prior to Vpp.
2. ~uring verify operation.
3. Measured 10% and 90% points.

3-31

/Ls

/Ls

II

Table 3
Pin Function

Read or Output Disable
Other
Pin

Mode

A2
A2

CP

EIEs

INIT

PGM

VFY

Vpp

At
Al

(6)

(18)

(19)

20

(7)

Read[2,3)

X

X

X

X

X

VILP
VIHP
VIRP
VILP
VILP
VILP
Vpp
Vpp

VIR
VIR
Vpp
Vpp
Vpp
Vpp
Vpp
Vpp

X

Output Disable[5)
Program [!,4)

VIL
VIR
VIHP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VIHP

Program Verify[!,4)
X
Program Inhibit[I,4)
X
Intelligent Program[I,4)
X
Program Synch Enable[4)
VIHP
Program Initial Byte[4)
VILP
Blank Check Ones[!A)
X
Blank Check Zeros [1,4)
X
Notes:
1. X = Don't care but not to exceed Vpp.
2. During read operation, the output latehes are loaded on a "0" to "I"
transition of CPo
3. If the registered device is being operated in a synchronous mode, pin
19 must be LOW prior to the "0" to "I" transition on CP (18) that
loads the register.

A7

Vee

A6
As

As
As

A.

A,o

A3

VPP flNIT)

A2
A,

ffi(E/Esl
07

Do

D.

0,

Os

02

D.

Vss

03

X
X

Vpp
Vpp
X
X

VILP·

The CY7C245 programming algorithm aJlows significantly
faster programming than the "worst case" specification of
JOmsec.
Typical programming time for a byte is less than 2.5 msec.
The use of EPROM cells allows factory testing of programmed cells, measurement of data retention and erasure
to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.
The algorithm utilizes two different pulse types: initial and
overprogram. The duration of the PGM pulse (tpp) is 0.1
msec which will then be followed by a longer overprogram
pulse of 24 (0.1) (X) msec. X is an iteration counter and is
equal to the NUMBER of the initial 0.1 msec pulses applied before verification occurs. Up to four 0.1 msec pulses
are provided before the overprogram pulse is applied.
The entire sequence of program pulses and byte verifications is performed at VCCP = 5.0V. When aJI bytes have
been programmed all bytes should be compared (Read
mode) to original data with VCC = 5.0V.

00'6-6

BitMap Data
Programmer
Decimal
0

Address
Hex
0

RAM Data
Contents
DATA

•
•

•
•

•
•

2047
2048
2049

X

5. If the registered device is being operated in a synchronous mode, pin
19 must be HIGH prior to the "0" to "I" transition on CP (18) that
loads the register.

Figure 3. Programming Pinouts

•

X

Data Out
HighZ
Data In
Data Out
HighZ
Data In
HighZ
Data In
Ones
Zeros

4. During programming and verification, all unspecified pins to be at

liGM(CPI

Ao

VILP
VILP

X

Outputs
(9-11,13-17)

•

7FF
800
801

•

DATA
INITBYTE
CONTROL BYTE

Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
3-32

START

Vccp

= S.OV. Vpp = 13.SV

i
ADDR 1ST LOCATION

II

I

'1

x-o

I

1
PROGRAM ONE PULSE
OF 0.1 m...

1
X=X+l

1
X-4?

1

YES

I

i

NO

FAIL

I

1

VERI FY ONE BYTE?

1

PASS

PROGRAM ONE PULSE
OF 24 (0.1) (X) m...

1

FAIL

YES

I

~

INC.ADDR

I

r

NO

I

1

l

DEVICE BAD

VERIFY BYTE

X·4?

I

lPASS
NO

LAST ADDRESS?

lYES

FAIL

REAO ALL BYTES?
Vee =5.0

.1
I

DEVICE BAO

I

1

PASS

DEVICE GOOD

0016-9

Figure 4. Programming Flowchart

3-33

Programming Sequence 2K x 8 Array
Power the device for normal read mode operation with pin
18, 19 and 20 at VIH. Per Figure 5 take pin 20 to Vpp. The
device is now in the program inhibit mode of operation
with the output lines in a high impedance state; see Figures
5 and 6. Again per Figure 5 address program and verify
one byte of data. Repeat this for each location to be programmed.
If the brute force programming method is used, the pulse
width of the program pulse should be 10 ms, and each

location is programmed with a single pulse. Any location
that fails to verify causes the device to be rejected.
If the intelligent programming technique is used, the program plilse width should be 100 /Ls. Each location is ultimately programmed and verified until it verifies correctly
up to and including 4 times. When the location verifies, one
additional programming pulse should be applied of duration 24X the sum of the previous programming pulses before advancing to the next address to repeat the process.
PROGRAM

,

VIHP---

ADDRESS
VILP - - -

PROGRAM

VERIFY

,

r--"'~

VIHP---

'I

DATA

..... tR~

VILP - - -

DATA IN

\

I---tAS _ _
Vpp---

PROGRAMMING
VOLTAGE (PIN 201
VIHP - - -

---=

-

1\

---0

-~

~

ADDRESS STABLE

-,r

tov

J.

\

DATA OUT

"!Ii

r

~~--

tOH

-

~

VILP---

i--tpp ....

~

VILP---

5

r
tvp---o

f--tvo

1\

VllP---

5

r

0016-10

Figure 5. PROM Programming Waveforms
~-------------------------PROGRAMI--------------------------~

1,-----

----~
VllP---

Vpp---

VIHP---

VILP---

VIHP - - DATA
VII,.P---

---+-----1
1-----------------tAH

-----------------1

v,,--PROGRAMMING
VOLTAGE (PIN 201
VIHP - - -

VllP---

VIH' - - -

PiiM
VILP---

0018-11

Figure 6. Initial Byte Programming Waveforms
3-34

Programming the Initialization Byte

Programming Synchronous Enable

The CY7C245 registered PROM has a 2049th byte of data
used to initialize the value of the register. This initial byte
is value "0" when the part is received. If the user desires to
have a value other than "0" for register initialization, this
must be programmed into the 2049th byte. This byte is
programmed in a similar manner to the 2048 normal bytes
in the array except for two considerations. First, since all of
the normal addresses of the part are used up, a super voltage will be used to create additional effective addresses.
The actual address has Vpp on Al pin 7, and VILP on A2,
pin 6, per Table 3. The programming and verification of
"INITIAL BYTE" is accomplished operationally by performing an initialize function.

The CY7C245 provides for both a synchronous and asynchronous enable function. The device is delivered in an
asynchronous mode of operation and only requires that the
user alter the device if synchronous operation is required.
The determination of the option is accomplished thru the
use of an EPROM cell which is programmed only if synchronous operation is required. As with the INITIAL byte,
this function is addressed thru the use of a supervoltage.
Per Table 3, Vpp is applied to pin 7 (AI) with pin 6 (A2) at
VIHP. This addresses the cell that programs synchronous
enable. Programming the cell is accomplished with a 10 ms
program pulse on pin 18 (PGM) but does not require any
data as there is no choice as to how synchronous enable
may be programmed, only if it is to be programmed.

VILP - - -

1-o--tAs - - - - I

VIHP---

PGM
VILP---

~----~s----__~:::::::::t;w::::::::::~

VIHP - - -

iiFY
VILP---

Vw---

Vpp---

PROGRAMMING
VOLTAGE (PIN 201

VILP - - -

0016-12

Figure 7. Program Synchronous Enable

Verification of Synchronous Enable

Blank Check

Verification of the synchronous enable function is accomplished operationally. Power the device for read operation
with pin 20 at VIH, cause clock pin 18 to transition from
VIL to VIR. The output should be in a High Z state. Take
pin 20, ENABLE, to VIL. The outputs should remain in a
high Z state. Transition the clock from VIL to VIR, the
outputs should now contain the data that is present. Again
set pin 19 to VIH. The output should remain driven. Clocking pin 18 once more from VIL to VIH should place the
outputs again in a High Z state.

A virgin device contains neither one's nor zero's because of
the differential cell used for high speed. To verify that a
PROM is unprogrammed, use the two blank check modes
provided in Table 3. In both of these modes, address and
read locations 0 thru 2047. A device is considered virgin if
all locations are respectively" 1's" and "O's" when addressed in the "BLANK ONES AND ZEROS" modes.
Because a virgin device contains neither ones nor zeros, it
is necessary to program both one's and zero's. It is recommended that all locations be programmed to ensure that
ambiguous states do not exist.

3-35

.:.

1:11

~
CY7C245
~r~====================
Ordering Information
Speed (ns)

tsA

ICC

teo mA

Ordering
Code

25

12

90 CY7C24S-2SPC

35

15

60 CY7C245L-35PC

CY7C24S-25WC
CY7C245L-35WC
90 CY7C245-35PC

Package
Type

Operating
Range

P13

Commercial

W14
P13

Speed(ns)

ICC

tsA teo

mA

45

60 CY7C245L-45PC

25

Ordering
Code

CY7C245L-45WC
90 CY7C245-45PC

Commercial

Type

Operating
Range

P13

Cominercial

Package

W14
P13

W14

CY7C245-45SC

S13

P13

CY7C245-4SWC

W14

CY7C245-35SC

S13

CY7C245-35WC

W14

CY7C245-35LC

L64

120 CY7C245-35DMB

D14

CY7C245-35QMB

Q64

CY7C245-35WMB

W14

CY7C245-35LMB

L64

CY7C245-45LC
120 CY7C245-45WMB
Military

3-36

L64
W14

CY7C24S-45LMB

L64

CY7C245-45DMB

D14

CY7C245-45QMB

Q64

Military

~
CY7C245
~~~~R========================================================~
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

IOZ

1,2,3

ICC

1,2,3

Switching Characteristics
Parameters

Subgroups

tSA

7,8,9,10,11

tHA

7,8,9,10,11

teo

7,8,9,10,11

Document #: 38-00004-0

3-37

CY7C245A

CYPRESS
SEMICONDUCTOR

Reprogrammable 2048 X 8
Registered PROM

Features
• Windowed for reprogrammability
• CMOS for optimum
speed/power
• High speed
- 15 ns max set-up
- 10 ns clock to output
• Low power
- 330 mW (commercial) for
-35 ns

-

• Programmable synchronous or
asynchronous output enable

• 5V ± 10% Vee, commercial and
military

• On-chip edge-triggered registers
• Programmable asynchronous
register (lNIT)

• TTL compatible I/O
• Direct replacement for bipolar
PROMs

• EPROM technology, 100%
programmable

• Capable of withstanding greater
than 2000V static discharge

• Slim, 300 mil, 24 pin plastic or
hermetic DIP

660 mW (military)

Logic Block Diagram

Pin Configurations

INIT----~~----------------------_,
AID

A,
As
A7

ROW
DECODER

A4

10F 128

128 x 128
PROGRAMMABLE
ARRAY

As

A,

I-+-D-o,
0,
COLUMN

1----------------'

DECODER

1------------------'

10F 16

E1ES-----+-jDal-t.::===:J

0121-2

1-+-D_ 0 2
0,

LL.;.JW-°o

~

lNIT

CP

CP---f JI"'""1HC

HC
0121-1

HC

10

00

11
19
12131415161718

20

0... NCI 0

,., ....

07
Os

It)

0%%000
C>

0121-3

Selection Guide
7C245A-15

7C245A-18

7C245A-25

7C245A-35

Maximum Setup Time (n8)

15

Maximum Clock to Output (n8)

10

18
12
120

25
15
90
120

35
20
90
120

Maximum Operating
Current (mA)

STD

Commercial

120

Military
L

Commercial

60

3-38

~

CY7C245A

~~~NDUcroR================================================================~
Product Characteristics

Maximum Ratings

The CY7C245A is a high performance 2048 word by 8 bit
electrically Programmable Read Only Memory packaged
in a slim 300 mil plastic or hermetic DIP. The ceramic
package may be equipped with an erasure window; when
exposed to UV light the PROM is erased and can then be
reprogrammed. The memory cells utilize proven EPROM
floating gate technology and byte-wide intelligent programming algorithms.

(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ............... - 65°C to + 150°C
Ambient Temperature with
Power Applied .................... - 5SoC to + 12SoC
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to +7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
DC Program Voltage (pins 7,18,20) ............. 13.0V
UV Erasure .......................... 7258 Wsec/cm2
Static Discharge Voltage ..................... > 200IV
(per MIL-STD-883 Method 3015)
Latchup Current .......................... > 200 mA

The CY7C245A rep1aces bipolar devices and offers the advantages oflower power, reprogrammability, superior performance and high programming yield. The EPROM cell
requires only 12.5V for the supervoltage and low current
requirements allow for gang programming. The EPROM
cells allow for each memory location to be tested 100%, as
each location is written into, erased, and repeatedly exercized prior to encapsulation. Each PROM is also tested for
AC performance to guarantee that after customer programming the product will meet AC specification limits.

Operating Range

The CY7C245A has an asynchronous initialize function
(lNIT). This function acts as a 2049th 8-bit word loaded
into the on-chip register. It is user programmable with any
desired word or may be used as a PRESET or CLEAR
function on the outputs.

Range

Ambient
Temperature

Commercial
Military(4)

O"Cto +70"C
- SSOC to + 12SOC

Vee
SV ±1O%
SV ±1O%

Electrical Characteristics Over Operating Range!7]
Parameters

Description

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Level

VIL

Input LOW Level

IIX

Input Leakage Current
Input Clamp Diode
Voltage

VeD

Vee = Min.,IoH = -4.0 rnA
VIN = VIH or VIL
Vee = Min.,IOL = 16 rnA
VIN = VIH or VIL
Guaranteed Input Lo~ical HIGH
Voltage for All Inputs 11

2.4

2.4

GND

~

VIN

~

2.0

Vee

0.4
2.0

Vee

0.8
-10

Vee

+10

-10

+10

V
0.4

V

Vee

V

0.8

V

-10

+10

p.A

2.0

0.8

NoteS

NoteS

los
IcC

Power Supply Current

GND ~ VIN ~ Vee
Vee = Max.

2.4

0.4

Guaranteed Input Lo~cal LOW
Voltage for AllInputs 11

Output Leakage Current GND ~ Vo ~ V~e
Output Disabled!3
Output Short Circuit
Vee = Max., VOUT = 0.OV!2]
Current

Ioz

7C245A-15,18 7C245A-25, 35 7C245AL-35
Units
Min. Max. Min. Max. Min. Max.

Test Conditions

-40

+40

-40

+40

-40

+40

p.A

-20

-90

-20

-90

-20

-90

rnA

ICommercial
IMilitary

90

120

60

mA

120

Capacitance [6]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions
TA = 2soC,f = 1 MHz
Vee = S.OV

Notes:
1. These are absolute voltages with respect to device ground pin and
include aU overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment (see Notes on
Testing).
2. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
3. For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.

Max.

Units

S

pF

8

4. TA is the Uinstant on" case temperature.

5. The CMOS process does not provide a clamp diode. However, the
CY7e24SA is insensitive to - 3V dc input levels and - SV undershoot pulses of less than \0 ns (measured at 50% point).
6. Tested initially and after any design or process changes that may
affect these parameters.
7. See the last page ofthi. specification for Group A subgroup testing
information.

3-39

•

,Switching Characteristics Over Operating RangerS]
Parameters

7C245A-15

Description

Min.

Max.

7C245A-18
Min.

7C245A-25

Max.

Min.

Max.

7C245A-35
Min.

Units

Max.

tSA
tHA

Address Setup to Clock HIGH

15

18

25

35

ns

Address Hold from Clock HIGH

0

0

0

0

ns

teo

Clock HIGH to Valid Output

tpwc

Clock Pulse Width

10

12

15

20

ns

ts~

Es Setup to Clock HIGH

10

10

12

15

ns

tHEs

Es Hold from Clock HIGH

5.

tOl

Delay from mIT to Valid Output

tRI

'fiil'IT Recovery to Clock HIGH

10

15

15

20

ns

tPWI

mrr Pulse Width

10

15

15

20

ns

teos

Valid Output from
Clock HIGH!I]

15

15

tHZC

Inactive Output from Clock HIGHl1. 3]

15

tOOE

Valid Output from E LOW[2]

12

tHZE

Inactive Output from
EHIGH!2.3j

15

10

12

5

5

15

Notes:
I. Applies only when the synchronous (Eg) function is used.
2. Applies only when the asynchronous (E) function is used.
3. Transition is measured at steady state High level - 500 mV or steady
state Low level + 500 mVon the outputfrom the 1.5V level on the
input with loads shown in Figure 1h.

4.
5.
6.
7.
8.

15

12

20

5
20

ns

ns
20

ns

15

20

ns

15

15

20

ns

15

15

20

ns

15

15

20

·ns

Tests are performed with rise and fall times of 5 ns or less.
See Figure la for all switching characteristics except tHZ.
See Figure 1h for tHZ.
All device test loads should be located within 2· of device outputs.
See the last page of this specification for Group A subgroup testing
information.

AC Test Loads and Waveforms[4, 5, 6, 71
R1 250 n
• v o----'VIIIr-.,

OUTPUT

R12&00

O--..;p----+

I

OUTPUT

I

,NCLUDING

JIG AND
":' SCOPE

3.0V-----i-~---"!L.

o--..;p----+

~7U

50pF

ALL INPUT PULSES

5Vo---~""'''''''

6pF

r

R2
167'u

GND - -.....

":'

<601

<5nl

INCLUDING
_JIGAND _
- SCOPE
-

0121-5

Figure 2

0121-4

Figure Ib

Figure 18
Equivalent to:

nffiVENIN EQUIVALENT
100n

OUTPUT ~2.0V

0121-6

Functional Description
(00-07) to be in the OFF or high impedance state. If the
asynchronous enable (E) is being used, the outputs will
come u~in the OFF or high impedance state only if the
enable (E) input is at a HIGH logic level. Data is read by
applying the memory location to the address inputs
(Ao-AIO) and a logic LOW to the enable input. The stored
data is accessed and loaded into the master flip-flops of the
data register during the address set-up time. At the next
LOW-to-HIGH transition ofthe clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs
(00-07).
If the asynchronous enable (E) is being used, the outputs
may be disabled at any time by switching the enable to a

The CY7C245A is a CMOS electrically Programmable
Read Only Memory organized as 2048 words x 8-bits and
is a pin-for-pin replacement for bipolar TTL fusible link
PROMs. The CY7C245A incorporates a D-type. masterslave register on chip. reducing the cost and size of pipelined microprogrammed systems and applications where
accessed PROM data is stored temporarily in a register.
Additional flexibility is provided with a programmable
synchronous (Es) or asynchronous (E) output enable and
asynchronous initialization (lNlT),
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (Es or E). If the
synchronous enable (Eg) has been programmed. the register will be in the set condition causing the outputs

3-40

Functional Description (Continued)
logic HIGH, and may be returned to the active state by
switching the enable to a logic LOW.

The CY7C245A has an asynchronous initialize input
(INI'!). The initialize function is useful during power-up
and time-out sequences and can facilitate implementation
of other sophisticated functions such as a built-in "jump
start" address. When activated the initialize control input
causes the contents of a user programmed 2049th 8-bit
word to be loaded into the on-chip register. Each bit is
programmable and the initialize function can be used to
load any desired combination of "I "s and "O"s into the
register. In the unprogrammed state, activating INIT will
generate a register CLEAR (all outputs LOW). If all the
bits of the initialize word are programmed, activating INIT
perfonns a register PRESET (all outputs HIGH).

If.the synchronous enal?le (Es) is being used, the outputs
Will. ~o to the OFF or high impedance state upon the next
pO~It1ve clock edge after the synchronous enable input is
sw~tched to a HI~H level. If the synchronous enable pin is
SWitched to a logiC LOW, the subsequent positive clock
edge will return the output to the active state. Following a
positive clock edge, the address and synchronous enable
inputs are. free to change since no change in the output will
occur until the next low to high transition of the clock.
This unique feature allows the CY7C245A decoders and
sense amplifiers to access the next location while previously
addressed data remains stable on the outputs.

Applying a LOW to the INIT input causes an immediate
load of the programmed initialize word into the master and
slave flip-flops of the register, independent of all other inputs, including the clock (CP). The initialize data will appear at the device outputs after the outputs are enabled by
bringing the asynchronous enable (E) LOW.

System ti~ing is simplified in that the on-chip edge triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar
to those of discrete registers available in the market.

Switching Waveforms

A.-A,.

______________

~~L-~~~~~-------

Es _ _ _ _..t..I..11
CP

0121-7

Notes on Testing
Inc?mi.ng test procedur~ on these devices should be carefully planned,
taking mto account the high perfonnance and output drive capabilities of
the parts. The following notes may be useful.
1. Ensure that adequate decoupling capacitance is employed across the
device Vee and ground terminals. Multiple capacitors are recommended, incl~ding a 0.1 /LF or larger capacitor and a 0.0 I /LF or
smaller capaCitor placed as close to tbe device tenninals as possible.
Inadequate d<:""upling may resul.t in large v~ations of power supply
voltage, creating erroneous function or tranSient performance failures.
2. Do not leave any inputs disconnected (floating) during any tests.

3. Do not attempt to perfonn threshold tests under AC conditions.
Lar!!e amplitude! fast ground current tr~ients nonnally occur as tbe
deVice outputs discharge the load capacitances. These transients flowing tbrough the parasitic inductance between the device ground pin
and the test system ground can create significant reductions in observable input noise immunity.
4. Output levels are measured at I.SV reference levels.
S. Transition is measured at steady state HIGH level - 500 m V or
steady state LOW level + 500 m Von the output from the I.SV level
on inputs with load shown in Figure lb.

3-41

3

~
CY7C24SA
~~~~R=============================================================
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
va. SUPPLY VOLTAGE

1.8
1.4

w

1.2

:.
~

1.0

/

/

N

.

~
0.8

./

/

6.0

6.6

8.0

1.2

g

1.2

./

1.0

-<

~

0.8

I

0.8
-55

/

----'"

!

1.0

Q

0.8

~

w

~~

N

:.

..
-<
:II

i...

~

25

.

30

...i

20

;;)

u
u

w
;;)

~

0

o
o

"

2.0

"

3.0

OUTPUT VOLTAGE (VI

...t:i

1.4

Q

1.2

6.5

6.0

:.

..
-<

1.0

r-

0.8

0.8

8.0

-66

17&

4.0

0.0

126

;;)

100

"~

7&

~

TA - ~'C
Vee - 4.6 V

/
400

800

CAPACITANCE (pFI

800

1000

OUTPUT SINK CURRENT
VI. OUTPUT VOLTAGE

"...

./

2&

f--

V-

I/
Vcc-&.OV

/

&0

o
200

126

180

zw

u

V
o

i...

...

/
/

2&

AMBIENT TEMPERATURE ('CI

/

20.0

&.0

-

w

N

TA ~ 2&'C
4.6

!:i

.",

1.0

Q,

,,-

10.0

&.0

;;)

~

-<1 16.0

:!l

6.6

NORMALIZED SETUP TIME
TEMPERATURE

30.0

!

6.0

1.&

TYPICAL ACCESS TIME CHANGE
VI. OUTPUT LOADING

~

10

4.6

VI.

, "-

25.0

"

TA j25'C
4.0

SUPPL Y VOLTAGE (VI

80

...

0.8

" i'--..... --... SUPPLY VOLTAGE (VI

0.8

0.4
4.0

125

OUTPUT SOURCE CURRENT
'". VOLTAGE

40 ~

zw

"

0.&

:II

AMBIENT TEMPERATURE ('CI

80

1.0

NORMALIZED SETUP TIME
SUPPLY VOLTAGE

VI.

w

U

~

AMBIENT TEMPERATURE ('C)

1.6

i:!

1.2

0.801.-_ _ _---"1.-_ _ _ _---"
-66
25
126

CLOCK TO OUTPUT TIME
VS. TEMPERATURE

1.4

1.4

I

TA -25"C
'-MAX.

SUPPLY VOLTAGE (V)

~

~

§i:!
Q

CLOCK TO OUTPUT TIME
va.Vcc

1.8

~

4.6

!Ii!
i=

w

!

11

Q

. NORMALIZED SUPPLY CURRENT
VI. AMBIENT TEMPERATURE
12r-------~----------,

I

0.0

TA -25'C

/
1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (VI
0121-9

3-42

Erasure Characteristics

Device Programming

Wavelengths of light less than 4000 Angstroms begin to
erase the 7C245A. For this reason, an opaque label should
be placed over the window if the PROM is exposed to
sunlight or fluorescent lighting for extended periods of
time.

OVERVIEW:
There are three independent programmable functions contained in the 7C245A CMOS 2K x 8 Registered PROM;
the 2K x 8 array, the initial byte, and the synchronous
enable bit. All of the programming elements are
"EPROM" cells, and are in an erased state when the device is shipped. This erased state manifests itself differently
in each case. The erased state for ENABLE bit is the
"ASYNCHRONOUS ENABLE" mode. The erased state
for the "INITIAL BYTE" is all "O's" or "LOW". The
"INITIAL BYTE" may be accessed operationally thru the
use of the initialize function.

The recommended dose for erasure is ultraviolet light with
a wavelength of 2537 Angstroms for a minimum dose (UV
intensity X exposure time) of25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 30-35 minutes. The 7C245A
needs to be within I inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high
intensity UV light for an extended period of time. 7258
Wsec/cm2 is the recommended maximum dosage.

DC Programming Parameters TA

= 25°C

Table 1
Parameter
Vppl11

Min.

Max.

Units

Programming Voltage

12.0

13.0

V

Vccp

Supply Voltage

4.75

5.25

V

VIHP

Input High Voltage

3.0

VILP
VOH[21

Input Low Voltage

0.4

V

Output High Voltage

VOL[2]

Output Low Voltage

0.4

V

Ipp

Programming Supply Current

50

rnA

Description

AC Programming Parameters TA =

V

2.4

V

25°C
Table 2

Parameter

Description

Min.

Max.

Units

tpp

Programming Pulse Width

200

10,000

,""S

tAS

Address Setup Time

1.0

,""S

tDS

Data Setup Time

1.0

,""S

tAH

Address Hold Time

1.0

,""S

tDH
tao tp[3]

Data Hold Time

1.0

,""S

Vpp Rise and Fall Time

1.0

,""S

tYD
typ

Delay to Verify

1.0

,""S

Verify Pulse Width

2.0

,""S

tDY

Verify Data Valid

1.0

,""S

tDZ

Verify HIGH to High Z

1.0

,""S

Notes:
1. Yccp must be applied prior to Ypp.
2. During verify operation.
3. Measured 10% and 90% points.

3-43

3

Mode Selection
Table 3
Pin Function[t)

A3
A3

CP

EIEs

IN1'l'

Ao

Other

PGM

VFY

Vpp

Ao

Pin

Read or Output Disable

Mode

Outputs
(9-11,13-17>

(5)

(18)

(19)

20

(8)

Read[2,3)

X

X

VIL

VIH

X

Output Disable[S)

X

X

X

HighZ

X

Data In
Data Out

Data Out

Program[4)

X

VILP

VIHP

VIH
Vpp

Program Verify[4)

X

VIHP

VILP

Vpp

X

Program Inhibit[4)

X

VIHP

VIHP

Vpp

X

HighZ

Intelligent Program[4)

X

VILP

VIHP

Vpp

X

Data In

Program Synch Enabl!l[4)

VIHP

VILP

VUiP

Vpp

Vpp

HighZ

Program Initial Byte[4)

VILP

VILP

VIHP

Vpp

Vpp

Data In

VIH

Notes:
I. X = Don't care but not to exceed Vpp.
2. DuriJ;tll read operation. the output latches are loaded on a ''0'' to "I"
transition ofCP.
3. If the registered device is being operated in a srnchronous mode, pin
19 must be LOW prior to the ''0'' to "I" transition on CP (18) that
loads the register.

A7

4. During programming and verification, all unspecified pins to be at
VILP.

s. If the registered device is being operated in a synchronous mode, pin
19 must be HIGH prior to the ''0'' to "I" transition on CP (18) that
loads the register.

The CY7C245A programming algorithm allows significantly faster programming than the "worst case" specification of 10 msec.
Typical programming time for a byte is less than 2.5 msec.
The use of EPROM cells allows factory testing of programmed cells, measurement of data retention and erasure
to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.

Vee

A6

As

As

Ae

A.

Al0

A3

VPPIINIT)
VFY

Al

PliM" (ep)

Ao

D7

Do

D.

Dl

D6

D2

D.

Vss

D3

The algorithm utilizes two different guise types: initial and
overprogram. The duration ofthe P M pulse (tpp) is 0.2
msec which will then be followed by a longer overprogram
pulse of 4 (0.1) (X) msec. X is an iteration counter and is
equal to the NUMBER ofthe initial 0.2 msec pulses applied before verification occurs. Up to ten 0.2 msec pulses
are provided before the overprogram pulse is applied.

(E/Es)

Aa

The entire sequence of program pulses and byte verifications is performed at VCCP = 5.0V. When all bytes have
been programmed all bytes should be compared (Read
mode) to original data with Vcc = 5.0V.

0121-10

Figure 3. Pro~ng Pinouts

BitMap Data
Progranuner Address

RAM Data

Decimal

Hex

Contents

0

0

DATA

•
•
•

2047
2048
2049

•

•
•
•

•
•

DATA
INITBYTE
CONTROL BYTE

7FF
800
801

Control Byte
00
01

Asynchronous output enable (default state)
Synchronous output enable

3-44

~
CY7C245A
~~~~========================================================~

II

0121-8

Figure 4. Programming Flowchart

3·45

~

CY7C245A

~r~==================~
Programming Sequence 2K x 8 Array
Power the device for normal read mode operation with pin
18, 19 and 20 at VIH. Per Figure 5 take pin 20 to Vpp. The
device is now in the program inhibit mode of operation
with the output lines in a high impedance state; see Figures
5 and 6. Again per Figure 5 address program and verify
one byte of data. Repeat this for each location to be programmed.

location is programmed with a single pulse. Any location
that fails to verify causes the device to be rejected.
If the intelligent programming technique is used, the program pulse width should be 200 ,""S. Each location is ultimately programmed and verified until it verifies correctly
up to and including 10 times. When the location verifies,
one additional programming pulse should be applied of duration 4X the sum of the previous programming pulses
before advancing to the next address to repeat the process.

If the brute force programming method is used, the pulse
width ofthe program pulse should be 10 ms, and each

VERIFY

PROGRAM

--i.

VIHP---

ADDRESS STABLE

ADDRESS
VILP---

~tA~~

VIHP - - -

-

DATA
VILP---

v.,.--PROGRAMMING
VOLTAGE (PIN 201

'I

____o

'-

DATA IN

tRI-i---tAS----O

-

~

tov

J..

\

DATA OUT

~

J..
~-;:.--

tOH

~

_f

-

~r-

VIHP---

VILP - - -

I-- .... ~

5

VIHP---

I'GM

~

r~tvo

typ____o

r

VIHP---

1\

VILP - - -

r0121-11

Figure 5. PROM Programming Waveforms

~-------------------------PROGRAM--------------------------YIHP---

Vpp---

AO

VILP - - -

VIHP - - -

DATA
VILP---

---+-----11'-_-+ ___+_..J 1
1----------------- tAH -----------------1

v.,. --PROGRAMMING
VOLTAGE (PIN 201

VILP--VIHP---

VslP--0121-12

Figure 6. Initial Byte Programming Waveforms

3-46

~

CY7C245A

~~~JtDU~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Programming the Initialization Byte

Programming Synchronous Enable

The CY7C245A registered PROM has a 2049th byte of
data used to initialize the value of the register. This initial
byte is value "0" when the part is received. If the user
desires to have a value other than "0" for register initialization, this must be programmed into the 2049th byte. This
byte is programmed in a similar manner to the 2048 normal bytes in the array except for two considerations. First,
since all of the normal addresses of the part are used up, a
super voltage will be used to create additional effective addresses. The actual address has Vpp on Ao pin 8, and VILP
on A3, pin 5, per Table 3. The programming and verification of "INITIAL BYTE" is accomplished operationally
by performing an initialize function.

The CY7C245A provides for both a synchronous and asynchronous enable function. The device is delivered in an
asynchronous mode of operation and only requires that the
user alter the device if synchronous operation is reqnired.
The determination of the option is accomplished thru the
use of an EPROM cell which is programmed only if synchronous operation is required. As with the INITIAL byte,
this function is addressed thru the use of a supervoltage.
Per Table 3, Vpp is applied to pin 8 (Ao) with pin 5 (A3) at
VIHP. This addresses the cell that programs synchronous
enable. Programming the cell is accomplished with a 10 ms
program pulse on pin 18 (pGM) but does not require any
data as there is no choice as to how synchronous enable
may be programmed, only if it is to be programmed.

VIHP - - -

V'LP - - -

14---"'s----I

VIHP---

PGM
VILP - - -

t---"'s----It-----tpp

VIHP - - -

VFv
V'LP--Vpp---

AO
V'HP---

V'LP - - Vpp---

PROGRAMMING
VOLTAGE (PIN 201
V'HP---

V'LP--0121-13

Figure 7. Program Synchronous Enable

Verification of Synchronous Enable

Blank Check

Verification of the synchronous enable function is accomplished operationally. Power the device for read operation
with pin 20 at VIH, cause clock pin 18 to transition from
VIL to VIH. The output should be in a High Z state. Take
pin 20, ENABLE, to VIL. The outputs should remain in a
high Z state. Transition the clock from VIL to VIH, the
outputs should now contain the data that is present. Again
set pin 19 to VIH. The output should remain driven. Clocking pin 18 once more from VIL to VIH should place the
outputs again in a High Z state.

A virgin device contains all zeros. To blank check this
PROM, use the verify mode to read locations 0 thru 2047.
A device is considered virgin if all locations are "O's" when
addressed.

3-47

n
a

Ordering Information
Speed (ns)

Icc

Ordering

.tsA teo

mA

Code

15

10

120 CY7C245A-15PC
CY7C245A-15WC

18

12

120 CY7C245A-18PC
CY7C245A-18WC

25

15

90 CY7C245A-25PC

Package Operating
Type
Range
P13

Speed (ns) Icc

Commercial

W14
P13

CY7C24SA-25SC

S13

CY7C245A-25WC

W14

CY7C245A-25LC

L64

120 CY7C24SA-25DMB

014

CY7C24SA-25QMB

Q64

CY7C24SA-25WMB

W14

CY7C245A-25LMB

L64

tsA teo
35

60 CY7C245AL-3SPC

20

CY7C245AL-35WC

90 CY7C245A-35PC

Commercial

W14
P13

Ordering
Code

mA

Commercial

Commercial

P13
S13

CY7C245A-35WC

W14

CY7C245A-35LC

3-48

P13
W14

CY7C245A-35SC

120 CY7C245A-35WMB
Military

Package Operating
Type
Range

L64
W14

CY7C24SA-35LMB

L64

CY7C245A-35DMB

014

CY7C245A-35QMB

Q64

Military

~
CY7C245A
•
~)r;~mru~~~~~~~~~~~~~~~~~~~~~~~~~
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

II

Switching Characteristics
Parameters

Subgroups

tSA

7,8,9,10,11

tHA

7,8,9,10,11

teo

7,8,9,10,11

Document #: 38-00004-B

3-49

CY7C251
CY7C254

CYPRESS
SEMICONDUCTOR

16,384 X 8 PROM
Power Switched and
Reprogrammable

Features
• CMOS for optimum
speed/power

• Direct replacement for bipolar
PROMs

• Windowed for reprogrammabiHty

• Capable of withstanding
static discharge

• High speed
- 45 os (commercial)
- 55 os (military)
• Low power
- 550 mW (commercial)
- 660 mW (military)
• Super low standby power
(7C251)
- Less than 165 mW when
deselected
- Fast access: 50 os
• EPROM technology 100%
programmable
• Slim 300 mil or standard 600
mil packaging available
• 5V ± 10% Vce, commercial and
military

> 2001V

Product Characteristics
The CY7C251 and CY7C254 are high
performance 16,384 word by 8 bit
CMOS PROMs. When deselected, the
7C251 automatically powers down into
a low power stand-by mode. It is packaged in the 300 mil wide package. The
7C254 is packaged in 600 mil wide
packages and does not power down
when deselected. The 7C251 and
7C254 reprogrammable CERDIP
packages are equipped with an erasure
window; when exposed to UV light,
these PROMs are erased and can then
be reprogrammed. The memory cells
utilize proven EPROM floating gate
technology and byte-wide intelligent
programming algorithms.

The CY7C251 and CY7C254 are plugin replacements for bipolar devices and
offer the advantages oflower power,
superior performance and programming yield. The EPROM cell requires
only 12.5V for the supervoltage and
low current requirements allow for
gang programming. The EPROM cells
allow for each memory location to be
tested 100%, as each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Bach PROM is
also tested for AC performance to
guarantee that after customer programming the product will meet DC and
AC specification limits.
Reading is accomplished by placing all
four chip selects in their active states.
The contents of the memory location
addressed by the address lines (AoA13) will become available on the output lines (00-07).

• TIL compatible 1/0

Logic Block Diagram

Pin Configurations

A"
A"
A"

',.At

..,At
....
A,

.,

...

.,

..
A,

..

'OS,
os,
'OS,

I!

A2

Xl

A,

:-::

NC

!ii
Ji!
iii

00

~H A"

Ii!
:i!

0

r~

cs"

1!!
r!!

NC

0088-1

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)

Commercial

Standby Current (mA)
(7C251 only)

Commercial

Military

30

Military

3-50

07

ooe8-11

Top View

7C151·55
7C254-55
55
100
120
30
35

OS2

~5:

Ooe8-2

7C151-45
7C254-45
45
100

cs 1

rii cs,

.-, ,-.. -, ,-, .-. ,-,
:'4: :It: :17: :11: :1.: :zo:
,-,

••

0;,

:e::

A,

..

A,
A,

.,

A,

A.

7Cl51·65
7Cl54-65
65
100
120
30
35

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -6S"C to + Is00C
Ambient Temperature with
Power Applied .................... - ss"C to + 12S"C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) .................... -O.sV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to +7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
DC Program Voltage (Pin 22) ................... 13.SV

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883, Method 3015)
Latchup Current .......................... > 200 mA
UV Exposure ........................ 7258 Wsec/cm2

Operating Range
Range
Commercial
Military!S)

Ambient
Temperature

Vee

O"Cto +70"C

5V ±IO%

-S5·C to + 125"C

5V ±IO%

Electrical Characteristics Over the Operating Range[6)
Parameters

Description

7C251-45
7C254-45

Test Conditions

Min.
VOH

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee

VIH

Input HIGH Leve1!ll

= Min., IOH = -4.0mA
= Min., IoL = 16.0mA

2.4

VIL

Input LOW Leve1!ll
Input Current

Ven

Input Diode Clamp
Voltage

loz

Output Leakage Current

VOL

OS;

los

Output Short
Circuit Current(3)

Vee

= Max., VOUT = GND

lee

Power Supply
Current

Vee = Max., VIN
lOUT = OmA

Standby Supply
Current (7C2S I)

Vee = Max., CS:2: VIH
lOUT = OmA

Min.

OS;

-10

Vee

OS;

VOH, Output Disabled

= 2.0V

Commercial

+10

-10

V
0.8

V

+10

/loA

Note 2

-40

+40

-40

+40

/loA

-20

-90

-20

-90

rnA

100

mA

120

mA

30

mA

35

mA

100

Military
Commercial

V

2.0

Note 2
VOUT

V
0.5

0.8
GND:2: VIN

Units

Max.

2.4
0.5

2.0

IIX

ISB

Max.

7C251-55,65
7C254-55,65

30

Military

Capacitance [4]
Parameters

Test Conditions

Max.

TA = 2S·C,f= 1 MHz
Vee = S.OV

10

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Notes:
1. These are absolute voltages with respect to device ground pin and
include all overshoots due to system andlor tester noise. Do not at·
tempt to test these values without suitable equipment.
2. The CMOS process does not provide a clamp diode. However, the
CY7C2S 1 and CY7C254 are insensitive to - 3V dc input levels and
- 5V undershoot pulses ofless than 10 ns (measured at 50% point).

10

Units
pF

3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may
affect these parameters.
5. TA is the "instant on" case temperature.
6. See the last page of this specification for Group A subgroup testing
information.

3-51

II

r;n
.

.

CY7C251
CY7C254
~~:=:=:=:=:===:=:=:=:=======:=:=:=:=:=~

Switching Characteristics Over the Operating Range[6, 71
Parameten

7C251-45
7C254-45

Description

7C25I·55
7C254-55
Min.

Max.

Min.

Max.

7C251-65
7C254·65
Min.

Units

Max.

tAA

Address to Output Valid

45

55

65

ns

tHZCSl

Chip Select Inactive to High Zls, 9)

25

30

35

ns

tazes2

Chip Select Inactive to High Z (7C25I, ~l Only)IS)

50

60

70

ns

tACSl

Chip Select Active to Output Valid(9)

25

30

35

ns

tACS2

Chip Select Active to Output Valid (7C251, ~l Only)

50

60

70

ns

tpu

Chip Select Active to Power Up (7C251)

tpD

Chip Select Inactive to Power Down (7C251)

AC Test Loads and Waveforms
R123SA

SVFl

OUTPUT·

INCLUDING
JIG AND
SCOPE

I

30 f
P

SV

OUTPUT

R2
lS9A

-=

R

INCLUDING
JIG AND
SCOPE

0

R123SA

I

S f

P

0

50

60

ns
70

ns

3~V--------~~~---------~
GND--...;Ir

R2
lS9A

:s;

In.

-=

s Sna
0086-6

Figure 2. Input Pulses
0086-4

Figure Ib

Figure 18
Equivalent to:

0

THEVENIN EQUIVALENT
9SA

OUTPUT

~

2.02 V

0086-5

.:1

I--tPD

Vee

,50%

SUPPLY
CURRENT

-

tpu

I

Note: Power Down controlled by <::Sh only.

fSO%

"o-A'3
ADDRESS

CS3

CS"CS2. CS4
~tM

00- 0 7

---------------~:j.:::::::::::~~~N;,O;T~E~8~·--------------:j~E~t::::::::::::
XX4
~NOTE
~
- tACS

I+-tHZCS

8

0086-7

Notes:
7. Test conditions assume signal transition times of 5 ns or less. timing
reference levels of 1.5V, output loading oftbe specified IoIlloH and
loads shown in Figure 1D, lb.

8. tHZCS is tested with load shown in Figure lb. Transition is measured
at steady state High level - 500 mV or steady state Low level + 500
mV on the output from the 1.5V level on the input.
9. tHZCSj and tACSj refers to 7C254 (all chip selects); and 7C25l (CS2.
CS3 and CS4 only).

Erasure Characteristics
intensity X exposure time) or 25 Wsec/cm2. For an ultra·
violet lamp with a 12 m W /cm2 power rating the exposure
time would be approximately 45 minutes. The 7C251 or
7C254 needs to be within 1 inch ofthe lamp during erasure. Permanent damage may result if the PROM is ex·
posed to high intensity UV light for an extended period of
time. 7258WX sec/em2 is the recommended maximum
dosage.

Wavelengths of light less than 4000 Angstroms begin to
erase the 7C25 I and 7C254 in the windowed package. For
this reason, an opaque label should be placed over the win·
dow if the PROM is exposed to sunlight or fluorescent
lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 Angstroms for a minimum dose (UV

3·52

CY7C251
CY7C254

~

~~~NDUcrOR ~=================================================================
Programming Algorithm
Device Programming

Programming is accomplished with an intelligent algorithm. The sequence of operations is to enter the programming mode by placing Vpp on pin 22. This should be done
after a minimum delay from power up, and be removed
prior to power down by the same delay (see the timing
diagram and AC specifications for details). Once in this
mode, programming is accomplished by addressing a location, placing the data to be programmed into a location on
the data pins, and clocking the PGM signal from VIHP to
VILP and back to VIHP with a pulse width of 200 ,""S. The
data is removed from the data pins and the content of the
location is then verified by taking the VFY signal from
VIHP to VILP, comparing the output with the desired data
and then returning VFY to VIHP. lethe contents are correct, a second overprogram pulse of 4 times the original.
200 ,""S is delivered with the data to be programmed agam
on the data pins. If the data is not correct, a second 200 ,""S
pulse is applied to PGM with the data to be programm~d
on the data pins. The compare and overprogram operatIOn
is repeated with an overprogram pulse width 4 times the
sum of the initial program pulses. This operation is continued until the location is programmed or 10 initial program
pulses have been attempted. If on the 10th attempt, t~e
location fails to verify, an overprogram pulse of 8 ms IS
applied, and the content of the location is once more verified. If the location still fails to verify, the device is rejected. Once a location verifies successfully, the address is advanced to the next location, and the process is repeated
until all locations are programmed. After all locations are
programmed, they should be verified at Vccp = 5.0V.

The CY7C251 and CY7C254 all program identically. They
utilize an intelligent programming algorithm to assure consistent programming quality. These l28K PROMS use a
single ended memory cell design. In an unprogrammed
state, the memory contains all "O"s. During programming,
a "1" on a data-in pin causes the addressed location to be
programmed, and a "0" causes the location to remain unprogrammed.

Programming Pinout
The Programming Pinout of all three devices are shown in
Figure 3 below, and are identical. The programming mode
is entered by raising the pin 22 to Vpp. The addressed
location is programmed and verified with the application of
a PGM and VFY pulse applied to pins 23 and 21 respectively. Entering and exiting the programming mode should
be done with care. Proper sequencing as described in the
dialog on the programmtng algorithm and shown in t~e
timing diagram and programming flow chart must be Implemented.

Programming And Blankcheck
Blankcheck
Blankcheck is accomplished by performing a verify cycle
(VFY toggles on each address), sequencing through all
memory address locations, where all the data read will be
"O"s.

A9
A8
A7
A6
AS
A4
A3
A2
AI
AD
DO
01
02
VSS

vee

1
2
3
4
5
6
7
8
9
10
11
12
13
14

26
25
24
23
22
21
20
19
18
17
16
15

AID
All
A12
A13
PGM
VPP
VFY

NA
07
06
05
04
03
0086-8

Figure 3. Programming Pinout (DIP Package)

3-53

II

(in

CY7C251
CY7C254

~~~~========================================================~

Operating Modes

Programming Sequence

Read

The flowchart in Figure 4 is a detailed description of the
intelligent programming cycle used to program the devices
covered in this specification. Of particular importance are
the areas of power sequencing used to enter and exit the
programming operation. This flowchart combined with the
timing diagrams AC and DC parameters accurately describe this complete operation.

Read is the normal operating mode for a programmed device. In this mode, all signals are normal TTL levels. The
PROM is addressed with a 14 bit field, 4 chip select bits,
and the contents of the addressed location appear on the
data out pins.
Program, Program Inhibit, Program Verify

The timing diagram in Figure 5 contains all of the timing
information necessary for describing the relations required
for programming the devices covered in this specification.
Some of the information pertains to each cycle of programming as specified in Figure 4, and some pertains only to
entry and exit from the programming mode of operation.

These modes are entered by placing a high voltage Vpp on
pin 22. Pin 23 becomes an active LOW program (PGM)
signal and pin 21 becomes an active LOW verify (VFY)
signal. Pins 21 and 23 should never be active LOW at the
same time. The PROGRAM mode exists when PGM is
LOW, and VFY is HIGH. The VERIFY mode exists when
the reverse is true, PGM HIGH and VFY LOW and the
PROGRAM INHIBIT mode is entered with both PGM
and VFY HIGH. PROGRAM INHIBIT is specifically
provided to allow data to be placed on and removed from
the data pins without conflict.

Tp, Tpo and THP refer to the entry and exit from the
programming mode of operation. Note that this is referenced to PGM and VFY operations.
Tos, TAS, TAH and TOH refer to the req(fed setup and
hold times for the address and data for P M and VFY
operations. These parameters must be adhered to, in all
operations, including Vpy. This precludes the option then
ofverifying the device by holding the Vpy signal LOW,
and sequencing the addresses.

Blankeheck
Blankcheck mode is identical to PROGRAM VERIFY
and is entered in the same manner as described above.

Table 1. Operating Modes
Pin Function
Read or Output Disable

CS4

CS3

Other

N/A

VFY

CSl
Vpp

PGM

Pin Number

(20)

(21)

(22)

(23)

VIL

VIH

VIL

VIL

Data Out

Output Disable[l)

X

X

X

VIH

HighZ

Output Disable[!)

X

X

VIH

X

HighZ

Output Disable[!)

X

VIL

X

X

HighZ

Output Disable[l)

Mode

Read

CSl

Outputs
(11-13,15-19)

VIH

X

X

X

HighZ

Program

X

VIHP

Vpp

VILP

Data In

Program Verify

X

VILP

Vpp

VIHP

Data Out

Program Inhibit

X

VIHP

Vpp

VIHP

HighZ

Blank Check

X

VILP

Vpp

VIHP

Data Out

Note:
1. X = Don't care but not to exceed Vee

+ 5%.

3-54

&n~NDUcroR================================================================~
CY7C251
CY7C254

.

Typical AC and DC Characteristics
NORNUUJZED SUPPLY CURRENT
SUPPLY VOLTAGE

NORNUUJZED SUPPLY CURRENT
1.2 vs.AMBIENTTEMPERATURE

VI

1.6

NORMALIZED ACCESS TIME
1.2 vs.SUPPLYVOLTAGE

1.4

S
N

./

1.2

:::;

..

-c

~

1.0

./

V

0

z

/"

.08

0.6

./

0.8

",

TA =25OC
f=MAX.

0.6
4.0

5.0

5.5

TA =~5OC
0.8 ' - - - - - - ' - - - - - - - - '
-55
25
125

6.Q

SUPPLY VOLTAGE (V)

1.6

'"F
~

~

~

NORMALIZED ACCESS TIME
vs. TEMPERATURE

'"

.

50

tj

30

~

1.2

..

1.0

::J

0

,

V!
::J

~

.5-

"

"

J

0

-55

25

125

.........

10

'"
Q

~

.........

o
o

1.0

AMBIENT TEMPERATURE (OC)

2.0

15.0

~

~

....I

::J

0.6

TYPICAL ACCESS TIME
CHANGE VI. OUTPUT LOADING

25.0

I-

0.8

30.0

'OJ' 20.0

20

3.0

6.Q

5.5

SUPPLY VOLTAGE(V)

OUTPUT SOURCE CURRENT
VOLTAGE

0

5.0

4.0

VS.

::J

-c
~

..
l-

....I

0
Z

60

!

1.4

Q

!::!

0.4

AMBIENT TEMPERATURE (OC)

V!

0

- r---

r-- r---

1.0

~

4.0

./

10.0

s.o

,

./V
200

. . .v

TA =25OC
VCC= j'5V

V

o
o

V
/

400

600

800

1000

CAPACITANCE (pf)

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
175

~

.'"

150

I:"
z

125

::J

100

.."..

/

0

><
z
iii

75

I-

50

::J
D..

I-

::J

0

25

/

/

:.--

".

/

VCC= 5.0V
TA =25OC -

If

o
o

1.0

2.Q

3.0

4.0

OUTPUT VOLTAGE (V)
0086-12

3-55

Q
.

CY7C251
CY7C254
SEMlcomucroR=======~~

• CYPRESS

0086-13

Figure 4. Programming Flowchart

3-56

~Tp

v

Vcc PIN 28 CCP
VSS
Vpp
VPP PIN 22 V,HP
VSS

-

--

--

T,.....

~TR

TF .....

{

-

TOp

TOp -

X

..... TOH1

DON'T PROG7AM "0"

11.

j

I:r;:;::J
Tpp

TOZ

D"TA OUT
!--TOV

~

_

-..I

"1"-

1- --!

DATA IN

_
V,HP
VFY PIN 21 V,LP

II

...-TAH-

XXX.XXXA
, T05 PROGRAM "I"

V,HP
PGM PIN 23 V,LP

i\ " - -

T"H

TAS
!--TAS -

V,HP
ADDRESS V,LP

THP-

THP

TOp

...-

"0"

Tov-

j

-..I
...-TVp

--!
0086-14

Figure S. Programming Waveforms
Note: Power, Vpp and Vee should not be cycled for each program verify cycle but remain static during programming.

Table 2. DC Programming Parameters TA = 2SOC
Parameter

Description

Min.

Max.

Units

Vpp

Programming Voltage

12.0

13.0

V

Vccp

Power Supply Voltage During Programming

4.75

5.25

V

Ipp

Vpp Supply Current

SO

rnA

VIHP

Input High Voltage During Programming

3.0

Vccp

V

VILP

Input Low Voltage During Programming

-3.0

0.4

V

VOH

Output High Voltage

VOL

Output Low Voltage

V

2.4
0.4

V

Table 3. AC Programming Parameters TA = 2S·C
Parameter

Description

Min.

Max.

Units

,....

tAS

Address Setup Time to PGMJVF'Y

1.0

tAH

Address Hold Time from PGMJVF'Y

1.0

tDS

Data Setup Time to PGM

1.0

tDH

Data Hold Time PGM

1.0

tpp

Program Pulse Width

0.2

tR,F

Vpp Rise and Fan Time

100

ns

tDV

Delay to Verify

1.0

,....

,...S
,...S
,...S
10

ms

tVD

Verify to Data Out

1.0

,...S

tVH

Data Hold Time from Verify

1.0

tvp

Verify Pulse Width

,....
,....

tDZ

Verify to High Z

tDP

Delay to Function

tHP

Hold from Function

tp

Power Up/Down

2.0
1.0

3-57

,...S

1.0

,....
,....

20.0

ms

1.0

Ordering Information
Speed

Ordering

(os)

Code

Package
Type

Operating
Commercial

Range

45

CY7C251-45PC
CY7C2S1-4SWC
CY7C2S4-4SWC
CY7C2S4-4SPC
CY7C2S4-4SDC

P21
W22
Wl6
PIS
016

55

CY7C251-55PC
CY7C251-55WC
CY7C254-SSWC
CY7C2S4-55PC
CY7C254-5SDC

P21
W22
Wl6
PIS
Dl6

CY7C251-55WMB
CY7C251-55DMB
CY7C254-S5WMB
CY7C2S4-55DMB

W22
D22
Wl6
Dl6

Military

CY7C2S1-65PC
CY7C2S1-65WC
CY7C254-6SWC
CY7C2S4-65PC
CY7C254-65DC

P21
W22
Wl6
PIS
016

Commercial

CY7C251-6SWMB
CY7C251-65DMB
CY7C251-65LMB
CY7C251-65QMB
CY7C2S4-65WMB
CY7C254-65LMB
CY7C254-6SQMB
CY7C254-6SDMB

W22
D22
L5S
Q55
Wl6
L55
Q55
Dl6

Military

65

3-58

(;n
.

CY7C251
CY7C254
~OOaoR~~~~~~~~~~~~~~~~~~~~~~~~~~~==~===

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

Von

1,2,3

VOL

1,2,3

VIn

1,2,3

VIL

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

ISBI2l

1,2,3

Switching Characteristics
Parameters

Subgroups

tAA

7,8,9,10,11

tACSl l11

7,8,9,10,11

tAcs2 12l

7,8,9,10,11

Note.:
I. 7C254 and 7C251 (CS2, CS3 and ~ only).
2. 7C251 (CS\ only).

Document #: 38-000S6-C

3-59

CY7C261
CY7C263/CY7C264

CYPRESS
SEMICONDUCTOR

8192 X 8 PROM
Power Switched and
Reprogrammable

Features
• CMOS for optimum
speed/power

• Direct replacement for bipolar
PROMs

• Windowed for reptogrammabllity

• Capable of withstanding
static discharge

• High speed
- 35 os (commercial)
- 45 os (mIlitary)

> 2000V

Product Characteristics
The CY7C261, CY7C263 and
CY7C264 are high performance 8192
)\ford by 8 bit CMOS PROMs. When
deselected, the 7C261 automatically
powers down into a low power standby mode. It is packaged in the 300 mil
wide package. The 7C263 and 7C264
are packaged in 300 mil and 600 mil
wide packages respectively and do not
power down when deselected. The reprogrammable CERDIP packages are
equipped with ail erasure window;
when exposed to UV light, these
PROMs are erased and can then be reprogrammed. The memory cells utilize
proven EPROM floating gate technology and byte-wide intelligent programming algorithms.

• Low power
- 550 mW (commercial)
- 660 mW (military)
• Super low standby power
(7C261)
- Less than 185 mW when
deselected
- Fast access: 35 os
• EPROM technology 100%
programmable
• Slim 300 mll or itandard 600

mil packaging avaIlable
• 5V ± 10% Vcc, commercial and
military
• TIL compatible I/O

Logic Block Diagram

The CY7C26l, CY7C263 and
CY7C264 are plug-in replacements for
bipolar devices and offer the advantages oflower power, superior performance and programming yield. The
EPROM cell requires only 12.SV for
the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each
memory location to be tested 100%, as
each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that
after customer programming the product will meet DC and AC specification
limits.
Reading is accomplished by placing an
active LOW signal on "CS. The contents
of the memory location addressed by
the address lines (Ao-A12) will become
available on the output lines (00-07).

Pin Configurations

A"
A"

A"
A,

0,

AI

"

0,

AI
As

0052-2

"
"

..
..

'-----1--1":100--°2

A,

0,

~

~

~

~

B

L-------~~o--oo

__________

____________-J
0052-1

0052-3

Selection Guide

Maximum Access Time (ns)
Maximum ~ting
CUrrent(mA
Standby Current (mA)
(7C261 only)

Commercial
Military
Commercial
Military

7C261-35
7C263-35
7C264-35
35
100

7C261-40
7C263-40
7C264-40
40
100

30

30

3-60

7C261-4S
7C263-4S
7C264-45
45
100
120
30
30

7C261-55
7C263-55
7C264-55
55
100
120
30
30

&n~U~=============================================================
CY7C261
CY7C263/CY7C264

.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C
Static Discharge Voltage ..................... >2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C
Latchup Current .......................... > 200 mA
Supply Voltage to Ground Potential
UV Exposure ........................ 7258 Wsec/cm2
(pin 24 to Pin 12) .................... -0.5Vto +7.0V
Operating Range
DC Voltage Applied to Outputs
in High Z State ...................... -0.5Vto +7.0V
Ambient
Range
Vee
Temperature
DC Input Voltage ................... - 3.0V to + 7.0V
Commercial
O'Cto +70'C
5V ±10%
DC Program Voltage
Military [51
- SS·C to + 12S·C
SV ± 10%
(pin 19 DIP, Pin 23 LCC) ...................... 13.0V

Electrical Characteristics Over the Operating Range l61
Parameters

Description

Min.
VOH

Output HIGH Voltage

Vee = Min., IOH = -4.0 mA

VOL

Output LOW Voltage

Vee = Min., IOL = 16.0mA

VIR

Input HIGH Level UI

VIL

Input LOW Level UI

IIX

Input Current

VeD

Input Diode Clamp
Voltage

Ioz

Output Leakage Current

los

Output Short
Circuit Current[31

Icc
ISB

7C261-45,55
7C263-45,55
7C264-45,55

7C261-35,40
7C263-35,40
7C264-35,40

Test Conditions

Max.

Min.

2.4

V
0.4

2.0
-10

V

-10

+10

VOUT

~

VOH, Output Disabled

Vee = Max., VOUT = GND

Power Supply
Current

Vee = Max., VIN = 2.0V
lOUT = OmA

Standby Supply
Current (7C261)

Vee = Max., CS
lOUT = OmA

~

VIH

Commercial

V

+10

/LA

-40

+40

-40

+40

/LA

-20

-90

-20

-90

mA

100

mA

120

mA

30

mA

30

mA

100

Military
Commercial

0.8

Note 2

Note 2
~

V

2.0
0.8

VOL

Max.

2.4
0.4

GND ~ VIN ~ Vee

Units

30

Military

Capacitance [4]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions
TA = 2soC,f= I MHz
Vee = S.OV

Notes:
1. These are absolute voltages with respect to device ground pin and

Max.
5
8

Units
pF

3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may
affect these parameters.
5. TA is the "instant on" case temperature.
6. See the last page of this specification for Group A subgroup testing
information.

include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.
2. The CMOS process does not provide a clamp diode. However, the
CY7C261, CY7C263 & CY7C264 are insensitive to - 3V dc input
levels and - 5V undershoot pulses ofless than 10 ns (measured at
50% point).

3-61

•

Switching Characteristics Over the Operating Range[5. 6]
Parameters

7C261-35
7C263·35
7C264-35

Description

Min.

Max.

7C261.40
7C263-40
7C264-40
Min.

Max.

7C261-45
7C263·45
7C264-45

Min.

Max.

7C261·55
7C263·55
7C264-55

Min.

Units

Max.

tAA

Address to Output Valid

35

40

45

55

ns

tHZCSI

Chip Select Inactive to High Z[8l

25

25

30

35

ns

tHzCS2

Chip Select Inactive to High Z (7C261)18l

30

35

45

55

ns

tACSI

Chip Select Active to Output Valid

2S

2S

30

3S

ns

tACS2

Chip Select Active to Output Valid (7C261)

40

45

45

5S

tpu

Chip Select Active to Power Up (7C261)

tpD

Chip Select Inactive to Power Down (7C261)

0

0
35

0
40

0

4S

ns
ns

S5

ns

AC Test Loads and Waveforms
RI2500

RI2500

5Vo-------~~~

5Vo-------~~~

OUTPUT 0-----......------"

I

INCLUDING
JIG AND
SCOPE

OUTPUT

0-----_----.....

R2

30 pF

1870

INCLUDING
JIG AND
SCOPE

I

R2

6 pF

1670

0052-6

Figure 2. Input Pulses

-:

-:
0052-4

Figure la
Equivalent to:

Figure Ib

THEVENIN EQUIVALENT
1000

OUTPUT

O-----'·..,;.,..,.,..""----~O 2.0 V

0052-5

-

Vee
SUPPLY
CURRENT

r--

tpD
~

50"

-

tpu

r-"1 50"

Ao-A 12

ADDRESS

~tACS

00-07-----x~~====:ll~:~::~:~:----~~s~~=====
I--tAA

I-tHZCS

0052-7

Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of l.5V, output loading of the specified IoxJIOH and
loads shown in Figure 1a, 1b.

8. tHZCS is tested with load shown in Figure 1b. Transition is measured
at steady state High level - 500 mV or steady state Low level + 500
mV on the output from the 1.5V level on the input.

Erasure Characteristics
intensity X exposure time) or 25 Wsec/cm2• For an ultraviolet lamp with a 12 m W /cm2 power rating the exposure
time would be approximately 45 minutes. The 7C261 or
7C263 needs to be within 1 inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high intensity UV light for an extended period of
time. 7258wxsec/cm2 is the recommended maximum
dosage.

Wavelengths of light less than 4000 Angstroms begin to
erase the devices in the windowed package. For this reason,
an opaque label should be placed over the window if the
PROM is exposed to sunlight or fluorescent lighting for
extended periods of time.
The recommended dose of ultraviolet light for eraaure is a
wavelength of 2537 Angstroms for a minimum dose (UV

3-62

5A~U~================================================================

CY7C261
CY7C263/CY7C264

.

loaded into an onboard register by clocking pin 21, the
latch signal, from VILP to VIHP and back to VILP. The
lower 8 address bits are then placed on pins 8 through I,
with the least significant bit on pin 8. The upper 5 bits
remain in the onboard latch until a new value is loaded or
power is removed from the device. All 256 bytes addressed
by the lower 8 bits may be accessed by sequencing the
lower 8 addresses without changing the upper 5 bits or relatching the value in the onboard register.

Device Programming

The CY7C26I, CY7C263 & CY7C264 all program identically. They utilize an intelligent programming algorithm to
assure consistent programming quality. These 64K
PROMS use a single ended memory cell design. In an unprogrammed state, the memory contains all "O"s. During
programming, a "I" on a data-in pin causes the addressed
location to be programmed, and a "0" causes the location
to remain unprogrammed.

Blankcheck
BIankcheek is accomplished by performing a verify cycle,
sequencing through all memory address locations, where
all the data read will be "O"s.

Programming Pinout
The Programming Pinout of all three devices are shown in
Figure 3 below, and are identical. The programming mode
is entered by raising the pin 19 to Vpp. In this mode, pin 21
becomes a latch signal, allowing the upper 5 address bits to
be latched and held in an onboard register, while the lower
8 address bits are presented on the same pins for selecting
one of 256 memory bytes. The addressed location is programmed and verified with the application of a PGM and
VFY pulse applied to pins 22 and 23 respectively. Entering
and exiting the programming mode should be done with
care. Proper sequencing as described in the dialog on the
programming algorithm and shown in the timing diagram
and programming flow chart must be implemented.

Programming Algorithm
Programming is accomplished with an intelligent algorithm. The sequence of operations is to enter the programming mode by placing Vpp on pin 19. This should be done
after a minimum delay from power up, and be removed
prior to power down by the same delay (see the timing
diagram and AC specifications for details). Once in this
mode, programming is accomplished by addressing a location as described above, placing the data to be pro~ed
into a location on the data pins, and clocking the PGM
signal from VIHP to VILP and back to VIHP with a pulse
width of 200 ,""s. The data is removed from the data pins
and the content of the location is then verified by taking
the VFY signal from VIHP to VILP, com",F!Yg the output
with the desired data and then returning
to VIHP. If
the contents are correct, a second overprogram pulse of 4
times the original 200 ,",,8 is delivered with the data to be
programmed again on the data pins. If the data is not correet, a second 200 ,""S pulse is applied to PGM with the
data to be programmed on the data pins. The compare and
overprogram operation is repeated with an overprogram
pulse width 4 times the sum of the initial program pulses.
This operation is continued until the location is programmed or 10 initial program pulses have been attempted.
If on the 10th attempt, the location fails to verify, an overprogram pulse of 8 ms is applied, and the content of the

Programming And Blankcheck
Addressing During Programming and Blankcheck
Addressing to these devices in all modes of operation other
than normal read operation is accomplished by multiplexing the upper 5 address bits with the lower 8. The address
designations for the lower 8 addressing bits is AXO through
AX7 and the upper 5 address bits are designated A Y8
through A YI2. This allows sufficient pins for an intelligent
programming algorithm to be implemented without the
need to switch high voltage signals during the bIankcheek,
programming, and verification operation.
Addressing while in these modes is accomplished by placing the upper 5 bits of address on pins 8, 7, 6, 5, and 4 with
the least significant bit on pin 8. These address bits are

AX7

1

AX6

2

AX5

3

PGM

AX4/AY12

4

LATCH

AX3/AYll

5

CS

AX2/AY10

6

Vpp

AXl/AY9

7

NA

AXO/AYB

B

017

010

9

016

011

10

015

012

11

Vss

12

24

Vcc

VN

014
13

013
0052-8

Figure 3. Programming Pinout (DIP Package)

3-63

•

~

.,rs~~

CY7C261
=================C=Y=7=C=26=3=I=C=Y=7C=2=6=4

location is once more verified. If the location still fails to
verify, the device. is rejected. Once a location verifies successfully, the address. is advanced to the nextlocation, and
the process is repeated until all locations are programmed.
After all locations are programmed, they should be verified
at Vccp = 5.0V.

Programming Sequence
The flowchart in Figure 4 is a detailed description of the
intelligent programming cycle used to program the devices
covered in this specification. Of particular importance are
the areas of power sequencing used to enter and exit the
programming operation. This flowchart combined with the
timing diagrams AC and DC parameters accurately describe this complete operation. Note should be taken of the
inner and outer addressing loops which allow 256 bytes to
be programmed each time the onboard register containing
the upper 5 address bits is loaded.

Operating Modes
Read

I>

Read is the normal operating mode for a programmed device. In this mode, all signals are normal TIL levels. The
PROM is addressed with a 13 bit field, a chip select, (active
LOW), is applied to the CS pin, and the contents of the
addressed location appear on the data out pins.

The timing diagram in Figure 5 contains all of the timing
information necessary for describing the relations required
for programming the devices covered in this specification.
Some of the information pertains to each cycle of programming as specified in the inner loops of Figure 5, some for
the outer loop where the upper address is advanced, and
some pertains only to entry and exit from the programming
mode of operation.

Program, Program Inhibit, Program Verify
These modes are entered by placing a high voltageVpp on
pin 19, with pins 18 and 20 set to VILP. In this state, pin 21
becomes a latch signal, allowing the upper 5 address bits to
be latched into an onboard register, pin 22 becomes an
active LOW program (PGM) signal and pin 23 becomes an
active LOW verify (VFY) signal. Pins 22 and 23 should
never be active LOW at the same time. The PROGRAM
mode exists when PGM is LOW, and VFY is HIGH. The
VERIFY mode exists when the reverse is true, PG'M
HIGH and 'V'F'Y LOW and the PROGRAM INHIBIT
mode is entered with both PGM: and VFY HIGH. PROGRAM INHIBIT is specifically provided to allow data to
be placed on and removed from the data pins without con.
flict.

In particular, the timing sequence associated with the
Latch signal on pin 21 and addresses A Y8 through A Y12
pertain only to the outer loop where the upper 5 (N in the
flow chart) address bits are incremented.
Tp, Tpo and THP refer to the entry and exit from the
programming mod~eration. Note that this is referenced to LATCH, PGM and VFY operations.
ToS, TAg, T AH and TOH refer to the required set~d
hold times for the address and data for PaM and
operations. These parameters must be adhered to, in all
operations, including Vpy. This precludes the option then
of verifying the device by holding the Vpy signal LOW,
and sequencing the addresses.

Blankcheck
Blankcheck mode is identical to PROGRAM VERIFY
and is entered in the same manner as described above.

Table 1. Operating Modes
Mode

Pins 4thru 8
Pins 1 thru3
Pins 9 thru 11 Pins 13 thru 17
A4-AO, AX4-AXO
A7-AS, AX7-AXS
DO thru D2
D3thruD7
AY12-AY8

Pin
19

Pin
20

Pin
21

Pin
22

Pin
23

DOOthruD02 D03thruD07 Al2 All

CS

AIO

A9

A8

Pin
18

Read

A7thru AS

A4thruAO

Program

AX7thruAXS

AX4thruAXO
AYI2-AY8

DIothruDil
Input

DI3 thruDI7
Input

VILP Vpp VILP LAT VILP VIHP

Program Inhibit AX7thruAXS

AX4thruAXO
AYI2-AY8

HighZ

HighZ

VILP Vpp VILP LAT VIHP VIHP

Program Verify AX7thruAXS

AX4thruAXO
AYI2~AY8

Blank Check

AX7thruAXS

AX4thruAXO
AYI2-AY8

DOOthruD02 D03thruD07
VILP Vpp VILP LAT VIHP VILP
Output
Output
DIothruDI2
Output

3-64

Dhthru DI 7
Output

VILP Vpp VILP LAT VIHP VILP

fin~~==============================================================~
CY7C261
CY7C263/CY7C264

.

Typical AC and DC Characteristics
NORMA~DSUPPLYCURRENT

NORMALIZED SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
1.2r-------,-----------,

vs. SUPPLY VOLTAGE

1.6

..,.

jl
!oJ

~
!l

0126-1

4

3

"3 5
"2 6

, ,

..., ...

2' 1 '282726
25 ",0
24 "II
23 "12
22 E/Es,i

GND 7

CLK 8
"I

0126-2

CY7C265

21 GND

9

20 GND
"0 10
19 °7
0 0 11
12 13 14 15 16 17 18

o

N

Q

",

o i!j 0

.....

0

It)

0

CD

0

0126-3

3-71

II

7C265·40

7C265·50

7C265-60

Maximum Set·Up Time (ns)

40

SO

60

Maximum Clock to Output (ns)

20

25

25

100

80

80

120

100

Maximum Operating
Current (mA)

I
I

Commercial
Military

Functional Description (Continued)
return the output to the active state. Following a positive
clock edge, the address and synchronous enable inputs are
free to change: since no change in the output will occur
until the next low to high transition of the clock. This
unique feature allows the CY7C265 decoders and sense·
amplifiers to access the next location while previously ad·
dressed data remains stable on the outputs.
If the Ell pin is used for mIT (asynchronous) then the
outputs are permanently enabled. The initialize function is
useful during power·up and time-out sequences and can
facilitate implementation of other sophisticated functions
such as a built·in "jump start" address. When activated the
initialize control input causes the contents of a user pro·
grammed 8193rd 8·bit word to be loaded into the on-chip
register. Each bit is programmable and the initialize func·
tion can be used to load any desired combination of"l"s
and "O"s into the register. In the unprogrammed state, activating mIT will generate a register CLEAR (all outputs
LOW). If all the bits of the initialize word are pro·
grammed, activating
performs a register PRESET
(all outputs HIGH).

Maximum Ratings

..

(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ..............• - 65°C to + 150"C
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C
Supply Voltage to Ground Potential .... - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
DC Program Voltage .......................... 13.0V
Static Discharge Voltage ..................... >2OO1V
(per MIL-STD-883, Method 3015)
.
Latchup Current .......................... > 200 rnA
UV Exposure ........................ 7258 Wsec/cm2

Operating Range

mrr

Ambient
Temperature

Range

Applying a LOW to the INIT input causes an immediate
load of the programmed initialize word into the pipeline
register and onto the outputs. The mIT LOW disables
clock and must return HIGH to enable CLOCK independent of all other inputs, including the clock.

Commercial
Military [I]

Vee

O"C to 70"C

5V ±10%

- SS·C to + 125°C

SV ±1O%

Electrical Characteristics Over the Operating Ranget2)
Parameters

Description

Test Conditions

Commerclal
Min.

= Min.,IOH = -2rnA
= Min.,IOL = 12 mA
= 8 rnA for Military)

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee
(IOL

VlH

Input HIGH Voltage

VIL

Input LOW Voltage

IIX

Input Load Current

GND

loz

Output Leakage
Current

Output Disabled

los

Output Short Circuit
Current

Vee

lee

Vee Operating Supply
Current

Vee = Max.
lOUT = ornA

VOH

Max.

2.4

Military
Min.
2.4

0.4
2.0

Units

Max.
V
0.4

2.0

V
V

0.8

0.8

V

10

10

,...A

40

40

,...A

= Max., VOUT = GND

90

90

mA

7C265·40

100
rnA

s: VIN s: Vee
GND s: VOUT s: Vee

7C26S·50

80

120

7C26S·6O

80

100

3·72

Parameters

Description

CIN

Input Capacitance

Cour

Output Capacitance

Test Conditions
TA = 25·C, f
VCC = 5.0V

=

Max.

1 MHz

Units

5

pF

8

Switching Characteristics Over the Operating Range[2]
Parameters

7C265-40

Description

Min.

Max.

7C265·50
Min.

Max.

7C265·60
Min.

Units

Max.

tAS

Address Set·Up to Clock

40

50

60

as

tHA

Address Hold from Clock

0

0

0

as

tco

Clock to Output Valid

tpw

Clock Pulse Width

15

20

20

as
as

tSES

ES Set·Up to Clock (Sync Enable Only)

15

15

15

as

tHES

ES Hold from Clock

5

5

5

tm

Init to Out Valid

tRI

Init Recovery to Clock

20

tpwI

Init Pulse Width

25

tcos

Output Valid from Clock (Sync. Mode)

20

25

25

ns

tHZC

Output Inactive from Clock (Sync. Mode)

20

25

25

ns

tDOE

Output Valid from E Low (Async. Mode)

20

25

25

ns

Output Inactive from Ii High (Async. Mode)

20

25

25

ns

tHZE
Notes:

20

25

25

1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.

25

25

ns
35

35
35

ns

as

25
35

ns

3. Tested initially and after any design or proeess cbanges that may
affect these parameters.

AC Test Loads and Waveforms
RI3380

5Vo----JI,f'o,I'I.-..,

(1000 FOR MIL.)
OUTPUT

I

OUTPUT

o--'"'"1r----i
GND _ _......r

R2
2480

I

(U30 FOR MIL.)

INCLUDING
JIG AND
.". SCOPE
.".

1430
(2000 FOR MIL)

OUTPUT

aov----~~------~

(1000 FOR MIL.)

o--'"'"1r----+
50pF

ALL INPUT PULSES

RI3380

5 v o------'w'v-.,

5pF

:..,
(3330 FDR MIL.)

.".~;~D

_

2.1IY

~ (2,OVFORMIL)
0126-6

3-73

<6nl
0126-5

INCLUDING

0126-4

II

ADDRESS _ _ _ _ _ _ _ _ __

SYNCHRONOUS ENABLE
(PROGRAMMABLE) _ _ _ _I

CLOCK

---..,..,.,1

OUTPUT~~~~~~~~r-----~:::::::::::)
~
INIT.~
t_DLt_lp~W_I_-.J. . J

(PROGRAMMABLE)
ASYNCHRONOUS
__

_
•
. , , - - - - - " " \ \ . , ,_ _ _ _ _ _ _C
tHZE.
1J

ASYNCHRONOUS
ENABLE

_ _ _ _ __
0126-7

Notes on Testing:

Incoming test procedures on these devices should be carefully planned,
taking into account the high performance and output drive capabilities of
the parts. The foUowing notes may be useful.
\. Ensure that adequate decoupling capacitance is employed across the
device Vee and ground terminals. Multiple capacitors are recommended, including a 0.1 ,.F or larger capacitor and a O.ot ,.F or
smaller capacitor placed as close to the device terminals as possible.
Inadequate decoupling may result in large variations of power supply
voltage, creating erroneous function or transient performance failures.
2. Do not leave any inputs disconnected (floating) during any tests.

3. Do not attempt to perform threshold tests under AC conditions.

Large amplitude, fast ground current transients normaUy occur as the
device outputs discharge the load capacitances. These transients flowing through the parasitic inductance between the device ground pin
and the test system ground can create significant reductions in observable input noise immunity.
4. Output levels are measured at I.5V reference levels.
S. Transition is measured at steady state HIGH level - 500 mVor
steady state LOW level + 500 mVon the output from the I.5V level
on inputs with load shown in Figure lb.
Programming Algorithm
Programming is accomplished with an intelligent algorithm. The sequence of operations is to enter the programming mode by placing l2.5V on Vpp. This should be done
after a minimum delay from power up, and be removed
prior to power down by the same delay (see the timing
diagram and AC specifications for details). Once in this
mode, programming is accomplished by addressing a location as described above, placing the data to be prolGMed
into a location on the data pins, and clocking. the
signal from VIHP to VILP and back to VIHP with a pulse
width of 200 p.s. The data is removed from the data pins
and the content of the location is then verified by taking
the VFY signal from VIHP to VILP, com"piyg the output
with the desired data and then returning
to VIHP. If
the contents are correct, a second overprogram pulse of 4
times the origina1200 p.s is delivered with the data to be
programmed again on the data pins. If the data is not correct, a second 200 p.s pulse is applied to PGM with the
data to be programmed on the data pins. The compare and
overprogram operation is repeated with an overprogram
pulse width 4 times the sum of the initial program pulses.
This operation is continued until the location is programmed or 10 initial program pulses have been attempted.
If on the 10th attempt, the location fails to verify, an overprogram pulse of 8 ms is applied, and the content ofthe

Device Programming
The CY7C265 utilizes an intelligent programming algorithm to assure consistent programming quality. These
64K PROMs use a single ended memory cell design. In an
unprogrammed state, the memory contains all "O"s. During programming, a "I" on a data-in pin causes the addressed location to be programmed, and a "0" causes the
location to remain unprogrammed.

Programming Pinout
The Programming Pinout is shown in Figure 3. The programming mode is entered by putting l2.5V on the Vpp
pin. The addressed location is programmed and verified
with the application ofa POM and VFY pulse. Entering
and exiting the programming mode should be done with
care. Proper sequencing as described in the dialog on the
programming algorithm and shown in the timing diagram
and programming flow chart must be implemented.

Programming and Blankcheck (Memory Bits)
Blankcheck
Blankcheck is accomplished by performing a verify cycle
(VFY toggles on each address), sequencing through all
memory address locations, where all the data read will be
"O"s. (Refer to mode table for pin states)

3-74

~

CY7C265

~~~ND~R~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
Programming and Blankcheck (Memory Bits) (Continued)
with a single 10 ms wide pulse in place of the intelligent
algorithm mainly because these features are verified operationally, not with the VFY pin. Architecture programming
is implemented by applying the supervoltage to two additional pins during programming. In programming the
7C265 architecture Vpp is applied to pins 3, 9 and 22.
Specific choice of a particular mode will depend on the
states of the other pins during programming so it is important that the condition of the other pins be met as set forth
in the mode table. The same considerations with respect to
power up and power down apply during architecture programming as during intelligent programming. Once the supervoltages have been established and the correct logic
states exist on the other device pins, programmiIifoMY
begin. Programming is accomplished by pulling
from
HIGH to LOW and then back to HIGH with a pulse width
equal to 10 ms.

Vee

"7

"8As

"e
"s

"4

"10

"3

"11

"2
PGIA

"12
Vpp

CLOCK

GNO

"1

VrY

"0DO

07

01

Os

O2

04

Vss

03

06

To check whether a 7C265 has been ~ogrammed as output
enable or initialize enable, pin 22 (Ell) should be pulled
LOW followed by a LOW to HIGH transition on pin 8
(CLOCK). The data read at the outputs is stored and complement data is shifted into the shadow register. A shift
from shadow to pipeline is performed and the CLOCK is
again pulled from LOW to HIGH. At this point, if the new
data read is data-complement, the device has been programmed as Output enable while if the new data read-true
then the device is programmed as Initialize enable. The
configuration of the Initialize byte can be read directly by
pulling Ell from HIGH to LOW.

0126-8

Figure 3. 7C265 Programming Pinout
location is once more verified. If the location still fails to
verify, the device is rejected. Once a location verifies successfully, the address is advanced to the next location, and
the process is repeated until all locations are programmed.
After all locations are programmed, they should be verified
at Vccp = 5.0V.
Programming Algorithm for the Architecture
The CY7C265 offers a liInited selection of programmed
architecture. Programming these features should be done

Mode Table
Mode Select

P2
A6

P3
AS

P26
All

P6
A2

Prn\I

P8
CLK

P9
At

P7

PtD
AD

VFY

P24
All

P20

P22

Ell
Vpp

P23
All

Normal Read

A6

AS

A9

A2

L

L/H

Al

AO

HIZ

All

H/L

AI2

Program (Memory)

A6

AS

A9

A2

L

L

Al

AO

H

All

Vpp

AI2

Program Verify

A6

AS

A9

A2

H

L

Al

AO

L

All

Vpp

AI2

Program Inhibit

A6

AS

A9

A2

H

L

Al

AO

H

All

Vpp

AI2

Async. Enable Read

A6

AS

A9

A2

L

L

Al

AO

HIZ

All

L

AI2

Sync. Enable Read

A6

AS

A9

A2

L

L/H

Al

AO

HIZ

All

L

AI2

Async. lnit. Read

A6

AS

A9

A2

L

L

Al

AO

HIZ

All

L

AI2

Program Sync. Enable[!)

H

Vpp

A9

H

L

L

Vpp

L

H

H

Vpp

H

Program lnitialize(2)

H

Vpp

A9

L

L

L

Vpp

L

H

H

Vpp

L

Program Initial Byte

H

Vpp

A9

L

L

L

Vpp

H

H

L

Vpp

AI2

Notes:
1. Default is Async. Enable.
2. Default is Enable.

3-75

3

DC Programming Parameters TA =

25·C
Min.

Max.

Units

Vccp
Ipp

I>escription
Programming Voltage
Power Supply Voltage During Programming
Vpp Supply Current

12.0
4.75

13.0
5.25
50

V
V

VIHP

Input High Voltage During Programming

VILP
VOH
VOL

Input Low Voltage During Programming
Output High Voltage
Output Low Voltage

3.0
-3.0

Parameter
Vpp

AC Programming Parameters TA =
Parameter
tpp
tAS
tAH
tOH
tos
tR,F

tov
tvo
tVH
typ
toz

mA
V

0.4

2.4
0.4

V
V
V

25·C

Description

Min.

Program Pulse Width (per Byte)
Address Set-Up Time
Address Hold Time
Data Hold Time
Data Set-Up Time
Vpp Rise and FaIl Time
Delay to Verify
Verify to Data Out

Max.
10.0

1.0

,",,8

1.0
1.0

,""S

1.0
1.0

,",,5

,""S

,",,8

1.0

Data Hold Time from Verify
Verify Pulse Width
Verify to High Z

Units
ms

,",,5

1.0

,",,8

1.0

,",,5

2.0

,",,8

1.0

,",,8

Erasure Characteristics
intensity X exposure time) or 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 45 minutes. The CY7C265
needs to be within I inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high
intensity UV light for an extended period of time. 7258
Wsec/cm2 is the recommended maximum dosage.

Wavelengths of light less than 4000 Angstroms begin to
erase the CY7C265 in the windowed package. For this reason, an opaque label should be placed over the window if
the PROM is exposed to sunlight or fluorescent lighting
for extended periods of time.
The recommended dose ofnltraviolet light for erasure is a
wavelength of2537 Angstroms for a minimum dose (UV

BitMap Data
RAM Data

Programmer Address
Hex
DeclmaI
0

•
•
•

8191
8192
8193

Contents
DATA

0

•
•

•
•

•

•

IFFF
2000
2001

DATA
INITBYTE
CONTROL BYTE

Control Byte
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize

3-76

II

0126-9

Figure 4. Programming Fiowchart

3-77

~~C1OR

CY7CZ65

vee
~------------top------------~

VPP

VSS
VIHP

---

top

r-

ADDRESS

I-

t AH -

.AO-A12
VllP
VIHP

,tOs--t
PROGRAM "1"

DATA

-l r-

DATA IN
VllP

PGM

tAH

I

t AS

DONT"T PRO'GRAM "0"
tpp-j
~
,It

T

VIHP
VllP

Vrv

~

"1.01 toz

tOH

)- I--!

OATA OUT

"0"

...

I- tov

-I-tovl

VIHP

I- t vp

"

1

---.J

VllP

0126-10

Figure 5. Programming Waveforms (Memory)
Note:
Power. Vpp and Vee should not be cycled for each program verity cycle but remain static during programming,

VPP
PIN 22 (DIP)
~

______

t~

______

~

~-------tHP--------~

PINS 3.9 (DIP)
V
___
IHP
ADDRESS
VllP - - VOHP
DATA·
VOlP
VIHP
PGM

VllP
0126-11

·Data required on I/O's only during initial programming,

Figure 6. Programming Waveforms for the Architecture

3-78

~

CY7C265

~~~D~R ==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
Typical DC and AC Characteristics
NORMALIZED SUPPLY
CURRENT vs. SUPPLY
VOLTAGE

NORMALIZED SUPPLY
CURRENT VI. AMBIENT
TEMPERATURE

NORMALIZED ACCESS TIME

vs. TEMPERATURE

1.2r-------~--------~

1.6

1.6
!oJ

::E

1.4

./

~
c

..

!oJ

1.2

::E

1.0
0.8

V

V

0.6

o

~o

'"z

TA =25 OC
f=MAX.

4.0

4.5

5.0

5.5

l'O~--~~----~

f----t_-----I

0.9

-55

25.0

'"'"

40

(,.)

30

" ',- "

'"0

20

::>

(,.)

::>

II)

I-

::>

10

D-

I-

::>
0

o

0.0

1.0

25

.s
J.

15.0

~
!oJ

10.0

0

........

3.0

OUTPUT VOLTAGE (V)

'"0z

0.8

::E

~
-55

5.0

"

0.0

4.0

175

.5
I-

V

II<

100

(,.)

/

l-

::>

/

75
SO

D-

TA=250 C
Vee =4.5V
200

125

'"
"iiiz

OUTPUT SINK CURRENT
vo. OUTPUT VOLTAGE

ISO

z
!oJ
::>

/

/
o

400

600

800

125

25
AMBIENT TEMPERATURE (OC)

-;(

/'

~

0.6

125

TYPICAL ACCESS TIME
CHANGE vs. OUTPUT
LOADING

'Vi' 20.0

"'"

1.0

AMBIENT TEMPERATURE(OC)

so

!oJ

..

.....

0

0.8~------~--------~

30.0

Z

1.2

...J

60

!oJ

~
!::!

6.0

OUTPUT SOURCE
CURRENT vs. VOLTAGE
-;(

1.4

VI
VI

!oJ

SUPPLY VOLTAGE (V)

.5
I-

F

!oJ

!oJ

./

N

:::;

'"0z

~

~.---t_-----I

1.1

1000

I-

::>
0

25

oV

/

0.0

CAPACITANCE (pF)

-

V

/
Vee = 5.0V
TAj250C

1.0

2.0

4.0

3.0

OUTPUT VOLTAGE (V)
0126-12

Ordering Information
Speed

Icc

(ns)

(mA)

40

100

50

SO

120

Package
Type

Operating
Range

Speed

Icc

(ns)

(mA)

CY7C265-40PC

P21

Commercial

60

SO

CY7C265·400C

022

CY7C265-40WC

W22

CY7C265-50PC

P21

CY7C265-500C

022

CY7C265-50WC

W22

CY7C265-500MB

022

CY7C265-50WMB

W22

CY7C265-50LMB

L64

CY7C265-5OQMB

Q64

Ordering
Code

100

Military

3-79

Ordering
Code

Package
Type

Operating
Range

CY7C265-60PC

P21

Commercial

CY7C265-600C

022

CY7C265-60WC

W22

CY7C265-600MB

022

CY7C265-60WMB

W22

CY7C265-60LMB

L64

CY7C265-6OQMB

Q64

Military

~
CY7C265
~r~====================
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

Vrn

1,2,3

VIL

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

ISB

1,2,3

Switching Characteristics
Parameters

Subgroups

tAS

7,8,9,10,11

tHA

7,8,9,10,11

teo

7,8,9,10,11

tpw

7,8,9,10,11

tSES

7,8,9,10,11

tHES

7,8,9,10,11

tcos

7,8,9,10,11

Document #: 38-OOO84-A

3-80

CY7C266

PRELIMINARY

CYPRESS
SEMICONDUCTOR

8192 X 8 PROM
Power Switched and
Reprogrananaable

Features
• CMOS for optimum
speed/power

• Direct replacement for
EPROMs

• Windowed for reprogrammability

• Capable of withstanding
static discharge

• High speed
- 55 ns (commercial)
- 55 ns (military)
• Low power
- 440 mW (commercial)
- 495 mW (military)
• Super low standby power
- Less than 85 mW when
deselected
• EPROM technology 100%
programmable
• 5V ± 10% VCC, commercial and
military
• TTL compatible I/O

> 2000V

Product Characteristics
The CY7C266 is a high performance
8192 word by 8 bit CMOS PROM.
When deselected, the 7C266 automatically powers down into a low power
stand-by mode. It is packaged in the
600 mil wide package. The reprogrammabIe CERDIP packages are equipped
with an erasure window; when exposed
to UV light, these PROMs are erased
and can then be reprogrammed. The
memory cells utilize proven EPROM
floating gate technology and byte-wide
intelligent programming algorithms.

Logic Block Diagram

The CY7C266 is a plug-in replacement
for EPROM devices. The EPROM cell
requires only 12.SV for the supervoltage and low current requirements allow
for gang programming. The EPROM
cells allow for each memory location to
be tested 100%, as each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that after customer
programming the product will meet
DC and AC specification limits.
Reading is accomplished by placing an
active LOW signal on OE and CEo The
contents of the memory location addressed by the address lines (Ao-AI2)
will become available on the output
lines (00-07).

Pin Configurations
Vee
vee
NC

.."

°7

'"
''"
10
"
"'7

0,

'.

0,

"'0

0.

0,

A,

0,
0,

0,

"
"
"
"
"

0137-2

.t';~~~~~

0,

"
5
A5 •

0,

•

'. 7
A, •

0,

2

l~! 32

31 3°29 As

,.,7

0

"A, ''0
0137-1

3

'0"

A,

'"

26 NC
25 01'

2.4 1.,0

CE
220,

23

Ne 12

00 13
21 06
14 HI 18 17 18 19 20
_

N

Q

CJ

I')

'"

01')

oo~zooo

Selection Guide
7C266-SS
Maximum Access Time (ns)

55

Maximum Operating
Current (rnA)

Commercial

80

Military

90

Standby Current (rnA)

Commercial

15

Military

15

3-81

0137-3

3

~

PRELIMINARY

CY7C266

~~~D~================================================================
Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... - 6S·C to + ISO"C

Static Discharge Voltage .......... '" .•...... >2001V
(per MIL·SID·883, Method 3015)
Latchup Current .......................... > 200 rnA
UV Exposure .........•.............. 72S8 Wsec/cm2

Ambient Temperature with
Power Applied .................... - SS·C to + 12S·C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) .......... ; .......... -O.SV to + 7.0V
DC Voltage Applied to Outputs
in HighZ State ...................... -0.5Vto +7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
DC Program Voltage .......................... 14.0V

Operating Range
Range
Commercial
Military!5]

Ambient
Temperature

Vee

O"Cto +70"C

5V ±10%

- SS·C to + 125·C

5V ±10%

Electrical Characteristics Over the Operating Range(6)
Parameters

Deseription

7C266·55

Test Conditions

Min.

Units

Max.

VOH

Output HIGH Voltage

Vee "" Min.,IOH = -4.0mA

VOL

Output LOW Voltage

Vce "" Min.,IoL = 16.0rnA

VIH

Input HIGH Level li]

VIL

Input LOW LevclU]

IIX

Input Current

Veo

Input Diode Clamp
Voltage

loz

Output Leakage Current

VOL :;;; VOUT :;;; VOH, Output Disabled

-10

+10

JJ.A

los

Output Short
Circuit Current!3]

Vee = Max., VOUT = GND

-20

-90

rnA

leci

Power Suyply
Current!s

CMOS Inputs: GND ±0.3Vor
Vcc ±0.3V

Commercial

20

mA

Military

30

mA

Ic~

Power Supply
Current!S]

TTL Inputs
VIL :;;; 0.8V, VIH

Commercial

25

rnA

Military

35

rnA

ISBI

Standby Supply
Current!?]

CE = Vee ±0.3V

Commercial

IS

rnA

CMOS Inputs (GND or Vee) ±0.3V

Military

15

mA

TTL Inputs
VIL :;;; 0.8V, VIH

Commercial

15

V

mA

Military

IS

rnA

V

0.4
2.0

GND

Standby Supply
Current!?]

ISB2

2.4

S;

VIN

S;

V

-10

Vce

0.8

V

+10

JJ.A

Note 2

~

~

2.0V

2.0V

Capacitance [4]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions
TA = 2S·C, f
Vcc"" S.OV

Notes:

= 1 MHz

Max.
5
8

Units
pF

4. Tested initially and after any design or process changes that may
affect these parameters.
5. TA is the "instant on" case temperature.
6. See the last page of this specification for Group A subgroup testing
information.
7. AC power component add I mA/MHz, vee = max, lOUT = O.
S. AC power component add 3 mA/MHz, Vee = max,IoUT = o.

1. These are absolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise. Do not at·

tempt to test these values without suitable equipment.
2. The CMOS process does not provide a clamp diode. However, the
CY?C266 is insensitive to - 3V dc input levels and - 5V undershoot
pulses oftess than 10 ns (measured at 50% point).
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.

3·82

~
PRELIMINARY CY7C266
~~~~u~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Switching Characteristics Over the Opex:ating Range[5, 6, 9)
7C266·55

Description

Parameters

Min.

Units
Max.

Address to Output Valid
Chip Enable Inactive to High Z[!O]

55

Output Enable Inactive to High Z[IO)

20
20

ns
ns

tACE

Output Enable Active to Output Valid
Chip Enable Active to Output Valid

55

DS

taHA

Data Hold from Address Change

tAA
tHZCE
tHZOE
tADE

ns
ns

55

III

ns

3

AC Test Loads and Waveforms
Rl 250.0.

R1250.o.

o---WIt--1

5V

o---WIt--1

OUTPUT 0 - -....- -....

OUTPUT

o--.....---t

5V

I

INCLUDING
JIG AND
SCOPE
~

I

R2
167.0.

30 pr

INCLUDING
JIG AND
SCOPE
~

3.0V ---~=--~

GND
R2
167.0.

5 pr

0137-5

Figure 2. Input Pulses
0137-4

Figure 1b

Figure 1a
Equivalent to:

THEVENIN EQUIVALENT
100.0.

OUTPUT ()--IINI,---O 2.0V
0137-6

Vee _ _ _ _ _ _ _ _ _ _ _ _ _ _

POWER DOWN CONTROLLED BY

CE

--J/

SUPPLY
CURRENT
Ao-A12
ADDRESS

\'-_ _ _
-

I--tAA toHAi--!

I-:HZC~_

~:ACE----I
AOE

HZOE

NOTE 8

XXX

NOTE 8
0137-7

Notes:
9. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of l.SV, output loading ofthe specified IOIJIOH and
loads shown in Figure 1a. lb.

10.

tHZCS is tested with load shown in Figure lb. Transition is measured
at steady state High level - 500 mVor steady state Low level + 500
mVon the output from the l.SV level on the input.

Erasure Characteristics
intensity X exposure time) or 25 Wsec/cm2. For an ultra·
violet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 45 minutes. The 7C266 needs
to be within 1 inch of the lamp during erasure. Permanent
damage may result if the EPROM is exposed to high intensity UV light for an extended period of time.
7258W X sec/cm2 is the recommended maximum dosage.

Wavelengths of light less than 4000 Angstroms begin to
erase the devices in the windowed package. For this reason,
an opaque label should be placed over the window if the
EPROM is exposed to sunlight or fluorescent lighting for
extended periods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 Angstroms for a minimum dose (UV

3·83

~
PRELIMINARY
CY7C266
~~~~UaoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Ordering Information
Speed
(os)

55

Ordering
Code

Package
Type

Operating
Range

CY7C266-55PC

P15

Commercial

CY7C266-55WC

W16

CY7C266-55DC

Dl6

CY7C266-55WMB

W16

CY7C266-55DMB

Dl6

CY7C266-55LMB

L55

CY7C266-55QMB

Q55

Military

3-84

~
PRELIMINARY
CY7C266
~~~OOaoR==========================================================~
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

IOZ

1,2,3

ICC

1,2,3

ISB

1,2,3

Switching Characteristics
Parameters

Subgroups

tAA

7,8,9,10,11

tHZOE

7,8,9,10,11

tHZCE

7,8,9,10,11

tAOE

7,8,9,10,11

tACE

7,8,9,10,11

Document #: 38-00086-C

3-85

CY7C268
CY7C269

CYPRESS
SEMICONDUCTOR

64K' Registered
Diagnostic PROM

Features

Functional Description

• CMOS for optimum speed!
power

The CY7C268 and CY7C269 are 64K
Registered Diagnostic PROMs. They
are both organized 8192 words by 8
bits wide, and have both a Pipeline
Output Register and an Onboard Diagnostic Shift Register. In addition, both
devices feature a Programmable Initialize Byte which may be loaded into the
Pipeline Register with the Initialize signal. The Programmable Initialize Byte
is the 8193rd byte in the PROM and its
value is programmed at time of use.

• High speed
- 40 ns max set-up
- 20 os clock to output
• Low power
- 550 mW (commercial)
- 660 mW (military)
• On-chip edge-triggered registers
- Ideal for pipelined
microprogrammed systems
• On-chip diagnostic shift register
- For serial observability and
controllability of the output
register
• EPROM technology
- 100% programmable
- Reprogrammable (7C269W)
• 5V ± 10% Vee, commercial and
military
• Capable of withstanding greater
than 2001V static discharge
• Slim, 300 mil 28 pin plastic or
hermetic DIP (7C269)

The 7C268 has 32 pins and features full
diagnostic capabilities while the 7C269
provides limited diagnostics and is
available in a space efficient 28 pin
package. This allows the designer to
optimize his design for either board
area efficiency with the 7C269, or combine the 7C268 with other diagnostic
products with the standard interface.

~10r256

~ --i

::::::

D[~ER

A,
A,

=>[

Pin Configurations
CY7C268

I

'"

10FJ2
COLUt.lN

~6 II 2~6

A,

8x I OF 32

MULTIPLEXER

DECODER

OAGHOJ-t~! ,r-nl
,----. -+I - I:~'"
It ~~7~~~U

'IT
(702 &0)

CLOCK
(702 ) CONTROL
PClK
lOGIC
(7C,~

CY7C269

PROGRAMIdABLE

A,A,:~[.J.HH..t~·~HHH
~,

When the MODE signal is LOW, the
PROM operates in a normal pipeline
mode. The contents of the addressed
memory location is loaded into the
Pipeline Register on the rising edge of
PCLK. The outputs are enabled with
the Em signal either synchronously
or asynchronously, depending on how
the device is configured when programmed. If programmed for asynchronous enable, ENA LOW enables

CY7C268: The 7C268 provides 13 address signals (Ao through A\2), 8 data
out signals (00 through 07), ENA (enable), PCLK (pipeline clock) and INIT
(initialize) for control. The full stan-

Logic Block Diagram
_r-,.....

A"
A,
A"

dard featured diagnostics of the 7C268
utilizes the SI and SO (shift in and shift
out), MODE and DCLK signals. These
signals allow serial data to be shifted
into and out of the Diagnostic Shift
Register at the same time the Pipeline
Register is used for normal operation.
The MODE signal is used to control
the transfer of the information in the
Diagnostic Register to the Pipeline
Register or the data on the Output Bus
into the Diagnostic Register. The data
on the Output Bus may be provided
from the Pipeline Register or an external source.

-+L

INITtALIZEWORD

'-BIT

EDGE-TRIGGERED

~ 26B}

PIPEUNEREGISTER

iNn'

'2

A"

'1".1

iNiT

NODE

sm

SDO

A"
501
500

B-BIT EDGE TRIGGERED
SHIFT REGISTER

CP(7C269)

Ao

E

,te,

+- (7C26B)

0,

0112-3

(702 68)

~
~7~7

~~~.t~~~

0112-2

~7~7'

A,3

A3 5

4 .3 2: 1 :32 31 30

A2 •

.~.

5

29

A2 •

A.'D

28 A'I
27 ENl

MODE 7
NC 8

0112-1

.4

.... .3.'.£.t~~~

CY7C268

OCLl(

•

PCLK

10

26

iNif

25

NC

A, 11

24 A'2
23 SOl

AD 12

22

00 13

21 07

3-86

IN C

o

l5

0')

0

"It

0

11'1

0

10

0

2: 1 :28 27 26
._.

7

CLOCK 8

25 AID

23

CY7C269

A'2

22 E/Es.I

A, •

21 SOl

20

Ao "

00 11

SDO

19 07
12131415161718

ocr!

rfo"cfc!

SDO

14 15 16 17 18 19 20

0"

t.40DE

.3

0112-4

0112-5

7C268/9-40

7C268/9-50

7C268/9-60

Maximum Set·up Time (ns)

40

50

60

Maximum Clock to Output (ns)

20

25

25

100

80

80

120

100

Maximum Operating
Current (mA)

Functional Description

I
I

Commercial
Military

(Continued)
Enable or the Initialize function. If the Ell pin is used for a
INIT (Asynchronous Initialize) function, the outputs are
permanently enabled and the Initialize Word is loaded into
the Pipeline Register on a High to LOW transition of the
mrr signal. The INIT LOW disables CLOCK and must
return high to re-enable CLOCK. If the Ell pin is used for
an enable signal, it may be programmed for either synchronous or asynchronous operation. This enable function then
operates exactly the same as the 7C268.

the outputs. If configured for synchronous enable, ENA
LOW during the rising edge of PCLK will enable the out·
puts synchronously with PCLK. RNA HIGH during the
rising edge of PCLK will synchronously disable the out·
puts. The asynchronous Initialize signal INIT transfers the
Initialize Byte into the Pipeline Register on a HIGH to
LOW transition. INIT LOW disables PCLK and needs to
transition back to a HIGH in order to enable PCLK.
DCLK shifts data into SI and out of SO on each rising
edge.

When the MODE signal is HIGH, the 7C269 operates in
the diagnostic mode. The ElI signal becomes a secondary
mode signal designating whether to shift the Diagnostic
Shift Register or to load either the Diagnostic Register or
the Pipeline Register. IfF;;I is HIGH, CLOCK performs
the function of DCLK, shifting SI into the least significant
location of the Diagnostic Register and all bits one location
toward the most significant location on each rising edge.
The contents of the most significant location in the Diagnostic Register are available on the SO pin.

When MODE is HIGH, the rising edge of the PCLK sig·
nalloads the Pipeline Register with the contents of the
Diagnostic Register. Similarly, DCLK, in this mode, loads
the Diagnostic Register with the information on the Data
Output Pins. The information loaded will be either the con·
tents of the Pipeline Register if the outputs are enabled, or
data on the bus, if the outputs are disabled (in a high impedance state).
CY7C269: This product is optimized for applications that
require diagnostics in a minimum amount of board area.
Packaged in 28 pins, the PROM has 13 Address Signals
(Ao through A12), 8 Data Out Signals (00 through <>7), Ell,
(Enable or Initialize) and CLOCK (pipeline and diagnostic
clock). Additional diagnostic signals consist of MODE, SI
(shift in) and SO (shift out). Normal pipelined operation
and Diagnostic operation are mutually exclusive.

If the ElI signal is LOW, SI becomes a direction signal;
transferring the contents of the Diagnostic Register into
the Pipeline Register when SI is LOW. When SI is HIGH,
the contents of the Output pins are transferred into the
Diagnostic Register. Both transfers occur on a LOW to
HIGH transition of the CLOCK. If the Outputs are enabled, the contents of the Pipeline Register are transferred
into the Diagnostic Register. If the Outputs are disabled,
an external source of data may be loaded into the Diagnostic Register. In this condition, the SO signal is internally
driven to be the same as the SI signal thus propagating the
"direction oftransfer information" to the next device in the
string.

When the MODE signal is LOW, the 7C269 operates in a
normal pipelined mode. CLOCK functions as a pipeline
clock,loading the contents of the addressed memory location into the Pipeline Register on each rising edge. The
data will appear on the Outputs if they are enabled. One
pin on the 7C269 is programmed to perform either the

3-87

II

&n~C'ONDUCI'OR.==========
.

CY7C268
CY7C269

. .

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... - 65°C to
Ambient Temperature with
Power Applied ......•............. - 55°C to

+ 150"C

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883, Method 3015)

+ 125°C
+ 7.0V

Latchup Current .......................... > 200 mA

Supply Voltage to Ground Potential .... -0.5V to

UV Exposure ........................... 7258 Wsec/c

DC Voltage Applied to Outputs
in High Z State ...................... - 0.5V to

Operating Range

DC Input Voltage ................... - 3.0V to

+ 7.0V
+ 7.0V

Range

DC Program Voltage .......................... 13.0V

Commercial

Ambient
Temperature

Vee

O"C to 70"C

SV ±1O%

- SS·C to

MilitaryUJ

+ 12S·C

SV ±1O%

Electrical Characteristics Over the Operating Range l2]
Parameters

Description

Min.
Output HIGH Voltage

Vee = Min.,loH = -2mA

VOL

Output LOW Voltage

Vee = Min., IOL = 12 mA
(IOL = 8 mA for Military)

VIH

Input HIGH Voltage

VOH

Military

COJDDIercial

Test Conditions

Max.

2.4

Min.

Units

Max.

2.4
0.4

2.0

V
0.4

V

2.0

V

VIL

Input LOW Voltage

0.8

0.8

V

IIX

Input Load Current

GND :;;: VIN :;;: Vee

10

10

""A

loz

Output Leakage
Current

GND :;;: VOUT :;;: Vee
Output Disabled

40

40

""A

los

Output Short Circuit
Current

Vee = Max., VOUT = GND

90

90

mA

Icc

Vee Operating Supply
Current

Vee = Max.
lOUT = OmA

mA

7C268/9-40

100

7C268/9-S0

80

120

7C268/9-60

80

100

Capacitance [3]
ParlllDeters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions

Max.

TA = 2S·C,f= 1 MHz
Vee = S.OV

5

Units
pF

8

Switching Characteristics Over the Operating Range[2]
Parameters

Description

7C268-40
7C269-40
Min.

Max.

7C268-50
7C269-SO
Min.

Max.

7C268-60
7C269-60
. Min.
Max.

Units

tAS

Address Set-Up to Clock

40

50

60

ns

tHA

Address Hold from Clock

0

0

0

ns

teo

Clock to Output Valid

tpw

Clock Pulse Width

15

20

20

ns

tSES

Es Set-Up to Clock (Sync Enable Only)

15

15

15

ns

tHES

'Es Hold from Clock

5

5

5

tDI

INff to Out Valid

tRI

INIT Recovery to Clock

20

25

25
20

3-88

25

35

25

ns
35

25

ns

ns
ns

lin

CY7C268
CY7C269

-..

~ ~U~R~==================================~

Switching Characteristics Over the Operating Range!3] (Continued)
Parameters

7C268-40
7C269·40

Description

Min.

7C268·50
7C269·50

Max.

Min.

7C268·60
7C269·60

Max.

Min.

Units

Max.

tpWI

Init Pulse Width

teos

Output Valid from Clock (Sync. Mode)

20

25

25

ns

tHZC

Output Inactive from Clock (Sync. Mode)

20

25

25

ns

tOOE

Output Valid from E Low (Async. Mode)

20

25

25

ns

tHZE

Output Inactive from E High (Async. Mode)

20

25

25

ns

25

35

35

ns

Diagnostic Mode Switching Characteristics Over the Operating Range!2]
Parameters

Military

Commercial

Description

Min.

Max.

Min.

Units

Max.

tSSDI

Set·Up SDI to Clock

30

35

tHSDI

SDI Hold from Clock

0

0

ns

tosoo

SDO Delay from Clock

tOCL

Minimum Clock Low

25

25

tocH

Minimum Clock High

25

25

ns

tSM

Set·Up to Mode Change

25

30

ns

tHM

Hold from Mode Change (7C269)

0

tMS

ModetoSDO

ns

40

30

ns
ns

0

ns

25

40

30

ns

45

ns

tss

SDIto SDO

tso

Data Set·Up to DCLK

25

30

ns

tHO

Data Hold from DCLK

10

15

ns

Notes:
1. T A is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.

3. Tested initially and after any design or process changes that may
affect these parameters.

AC Test Loads and Waveforms
R13380

5

A13380

v O----W'Y--,

OUTPUT

OUTPUT

R2
50pF

aov--------·~~------~

(&000 FOR MIL.)

0---"""1,.....-----+

I

ALL INPUT PULSES

5Vo------JV~-,

(5000 FOR MIL.)

2480
(3330 FOR MIL.)

INCLUDING
JIG AND
":" SCOPE
":"

0----,.....-----+

I
":"

:'n

5pF

GND

(3330 FOR MIL.)

INCLUDING

~~~~D

_

1430
(2000 FOR MIL.)
l.llY
OUTPUT ~ (2.OVFORMIL.)

0112-8

3·89

"'5 ns
0112-7

0112-6

•

·
fin
~U~========================================================~~
.

CY7C268
CY7C269

.

Switching Waveforms 7C268, 7C269
Pipeline Operation (Mode = 0)
ADDRESS

-----------------

SYNCHRONOUS ENABLE
(PROGRAMMABLE) _____"I

PCLK/CLOCK(7C269)

-----+.J[

OUTPUT~~~~~~~~----------J(:::::::::::)

ASYNCHRONOUS
ENABLE

el~

_ _ _ _1-------,.\.. _____4
,.-

l

tHZE

tDOE

_ _ __

0112-9

Notes on Testing:
Incoming test procedures on these devices should be carefully planned.
taking into account the high performance and output drive capabilities of
the parts. The following notes may be useful.
1. Ensure that adequate decoupling capacitance is employed across the
device Vcc and ground terminals. Multiple capacitors are recommended. including a 0.1 p.F or larger capacitor and a 0,01 p.F or
smaller capacitor placed aa close to the device terminals aa possible.
Inadequate decoupling may result in large variations of power supply
voltage. creating erroneous function or transient performance failures.
2. Do not leave any inputs disconnected (floating) during any tests.

3. Do not attempt to perform threshold tests under AC conditions.
Large amplitude. faat ground current transients normally occur aa the
device outputs discharge the load capacitances. These transients flowing through the parasitic inductance between the device ground pin
and the test system ground can create significant reductions in observable input noise immunity.
4. Output levels are measured at I.SV reference levels.
S. Transition is measured at steady state HIGH level - 500 mV or
steady state LOW level + 500 mV on the output from the l.SV level
on inputs with load shown in Figure lb.

7C268 Diagnostic Waveforms
DCLK

SOl

SDO

---"'1
__~____________J

___

~

__

-'I~

__________-+-J

MODE

PCLK

t
X,.------------

---....II

tHO
OUTPUT _____________________

0112-10

3·90

(;n

CY7C268
CY7C269
~~u~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Switching Waveforms (Continued)
.

7C269 Diagnostic Application (Shifting the Shadow Register)

CLOCK

--'""""I

MODE

SOO _ _

SOl

__

~

~

_ _~I'~_ _ _ _ _ _ _ _ _ _-+-J'~

II

_________________

__+-________- J I

fiT
0112-11

7C269 Diagnostic Application (Parallel Data Transfer)

CLOCK

MODE

SOl

SDO

---+'""""1

-""""'-"1
-""""'---+-+""1
_~_ _ _

+"L..__..JI

fiT

I:

teo
o0-o7 __________~OUT
0112-12

Notes:
6. Asynchronous enable mode only.

7. The mode transition to HIGH latches the asynchronous enable state.
If the enable state is changed and held before leaving the diagnostic
mode (mode H ~ L) then the output impedance change delay is

Device Programming

Programming Pinout

The CY7C268 and CY7C269 program identically. They
utilize an intelligent programming algorithm to assure consistent programming quality. These 64K PROMS use a
single ended memory cell design. In an unprogrammed
state, the memory contains all "O"s. During programming,
a "I" on a data-in pin causes the addressed location to be
programmed, and a "0" causes the location to remain unprogrammed.

The Programming Pinout of both devices is shown in Figures 3a and 3b. The programming mode is entered by putting 12.SV on the Vpp pin. The addressed 10cati00is profpymed and verified with the application ofa P M and
pulse. Entering and exiting the programming mode
should be done with care. Proper sequencing as described
in the dialog on the programming algorithm and shown in
the timing diagram and programming flow chart must be
implemented.

tMS.

3·91

CY7C268

~
CY7C269
~r~=================

0112-14

Figure 3b. 7C269 Programming Pinout
0112-13

Figure 3a. 7C268 Programming Pinout

Programming and Blankcheck (Memory Bits)
After all locations are programmed, they should be verified
at Vccp = S.OV.

Blankcheck
Blankcheck is accomplished by performing a verify cycle
(VF'Y toggles on each address), sequencing through all
memory address locations, where all the data read will be
"O"s. (Refer to mode table for pin states)

Programming Algorithm for the Architecture
Both the 7C268 and 7C269 offer a limited selection of programmed architecture. Programming these features should
be done with a single 10 ms wide pulse in place of the
.
intelligent algorithm mainly because these features are venfied operationally, not with the VFY pin. Architecture prograntming is implemented by applyin~ the supervoltage .to
two additional pins during programming. In programming
the 7C269 architecture Vpp is applied to pins 3, 9 and 22
while in programming the 7C268 architecture Vpp is applied to pins 3, 11, 26. Specific choice o.f a p~icular mode
will depend on the states of the other pinS during programming so it is important that the condition of the other pins
be met as set forth in the mode table. The same considerations with respect to power up and power down apply during architecture programming as during intelligent prograntming. Once the supervoltages have been estabhshed
and the correct logic states exist on the other device pins,
prograntming may begin. Programming is accomplished by
pulling PGM from HIGH to LOW and then back to
HIGH with a pulse width equal to 10 ms.

Programming Algorithm
Programming is accomplished with an intelligent algorithm. The sequence of operations is to enter the programming mode by placing 12.SV on Vpp. This should be done
after a minimum delay from power up, and be removed
prior to power down ~y th~ same delay.(see the ~g.
diagram and AC specdications for details). Once In this
mode, programming is accomplished by addressing a location as described above, placing the data to be programmed
into a location on the data pins, and clocking the P 2001V static discharge

Logic Block Diagram

Pin Configurations
CY7C271

CY7C274

A,.
A13

Vpp

"2

...

A13

'"

A'D
A,

A"

liE

As

'7
A,
A.
A.

A"

'---+--1.>1>--0.

CE

0,

0,

'----r.--c><>-O.

A.

'----+-I.>c>--02

A2
A,
AD

0,

0,

0102-2

11.6 5 4

3

2

;~! 32

31 3°29 AI2

o

A, •
A, 7
A, '

A, '

.. "

A, 10

0102-1

He 12

_

N CI

U

III

11. 5 6

27

A, 7

11.,4

26 Ne

25 CS,
24 CS 2
23

.,

11.6 5" 3 2

2S A'3

"A,10,

CE

AD 11

Ne 12

31 3°29 As
28 A,
27 A,t
26 Ne
25

OE

24 AID

23

CE

22 07

00 13
21 0&
1415 16 17 18 19 20
_

11'1

oOjizooo

:~!32

o

A, •

22 07

0 0 13
21 06
14 HI 16 17 18 19 20

NO

U

..,.

..

WI

o0i§zOOO

0102-3

3-99

0102-10

.r-~$-'£~;:;

~~.r~~~i

0102-11

n

.:.

CY7C271

CY7C274
~PRE&s
~~~OO~UaoR~==============================================================
Selection Guide

7C271-45
7C274-45
Maximum Access Time (ns)
Maximum Operating
Current (rnA)

45
120

Commercial
Military
Commercial
Military

Standby Current (rnA)

7C271-55
7C274-55
55
120
130

30

30
40

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 1500C

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883, Method 3015)

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latchup Current .......................... > 200 rnA

Supply Voltage to Ground Potential •... -0.5V to +7.0V

UV Exposure ........................ 7258 Wsec/cm2

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V

Operating Range

DC Input Voltage ................... - 3.0V to + 7.0V

Range

DC Program Voltage .......................... 13.0V

Commercial
Military!4]

Ambient
Temperature

Vee

O"Cto +70"C

5V ±10%

- 55°C to + 125·C

5V ±IO%

Electrical Characteristics Over the Operating Range!5]
Parameters

Description

7C271-45
7C274-45

Test Conditions

Min.
VOH

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee

= Min.,IOH = -2.0rnA
= Min., IOL = 8.0 rnA'

VIH

Input HIGH LevelU]

VIL

Input LOW Level[!]

IIX

Input Current

VCD

Input Diode Clamp
Voltage

loz

Output Leakage
Current

VOL';; VOUT ,;; VOH,
Output Disabled

los

Output Short
Circuit Current!3]

VCC

Icc

Power Supply
Current

Vce = Max., VIN
lOUT = ornA

ISB

Standby Supply
Current

Vec = Max., CS ~ VIH
lOUT = OmA

7C271-55
7C274-55
Min.

Max.

2.4

2.4
0.4

GND ,;; VIN ,;; Vee

= 2.0V

V
0.4

V

2.0

Vee
0.8

2.0

Vee
0.8

V

-10

+10

-10

+10

p,A

Note 2

= Max., VOUT = GND

Units

Max.

V

Note 2

-40

+40

-40

+40

p,A

-20

-90

-20

-90

rnA

120

rnA

130

rnA

30

rnA

40

rnA

Commercial

120

Military
Commercial

30

Military

*6.0 rnA military

Capacitance [6]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions
TA = 25·C, f
VCC = 5.0V

Notes:
1. These are absolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.
2. The CMOS process does not provide a clamp diode. However, the
CY7C271 and CY7C274 are insensitive to -3V dc input levels and
- 5V undershoot pulses ofless than 10 ns (measured at SO% point).

= I MHz

Max.
8

Units
pF

8

3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. TA is the "instant on" case temperature.
S. See the last page of this specification for Group A subgroup testing

information.

6. Tested initially and after any design or process changes that may

affect these parameters.

3-100

(;ji

CY7C271
CY7C274

~~U~==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
Switching Characteristics Over the Operating Range[S, 7]
Parameters

7C271·45
7C274-45
Min.
Max.
45
30
30

Description
Address to Output Valid
Chip Select Inactive to High ZIS] (CSI and CS2-7C27l Only)
Chip Select Active to Output Valid (C81 and CS2-7C271 Only)
Output Enable Inactive to High Z[s] (OI!- 7C274 Only)
Output Enable Active to Output Valid (OI!-7C274 Only)
Chip Enable Inactive to High Zls) (CE Only)

tAA
tHZCS
tACS
tHZOE
tOE
tHZCE
tACE
tpu

25
25
50
50

Chip Enable Active to Output Valid (eE Only)
Chip Enable Active to Power Up
Chip Enable Inactive to Power Down
Output Hold from Address Change

tPD
tOH

7C271·SS
7C274-SS
Min.
Max.
55
30
30

0

30
30
60
60

0
50

0

60

0

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

AC Test Loads and Waveforms
R1

R1

500Jl

500Jl

5v~(658Jl
hill)

5V;n(658Jl
hill)

OUTPUT

3.0V~lI:

OUTPUT
30 pr

INCLUDING
JIG AND
SCOPE

I
-= -=

~~3Jl

I
-= -=
5pr

(403Jl hill) INCLUDING
JIG AND
SCOPE

~~3Jl

GND

lOll:

~5ns

(403A hill)

~~
~5ns

lOll:

0102-6

Figure 2. Input Pulses

0102-4

Figure la
Figure Ib
THEVENIN EQUIVALENT

Equivalent to:

200.0.

OUTPUT ~ 2.00V COMMERCIAL

250.0.

OUTPUT ~ 1.90V MILITARY

0102-5

-

Vee

tpD

1"SOli:

SUPPLY
CURRENT

-

I'

tpu

r
1f

POWER DOWN CONTROLLED BY

CE

SOli:

Ao-A14

ADDRESS
CSz

[910E.CE.CS 1

~tAA-

~

PREVIOUS DATA VALDIXX

(tHZOE)
-tHZCS(E)-1
DATA VALID
I

I

(tOE)
I--tACS(E)--j
NOTE B
NOTE B

HIGH Z
0102-7

Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of I.SV. output loading of the specified Ior/loH and
loads shown in Figure la, lb.
S. tHZCS(E) and tHzOE are tested with the load shown in Figure lb.
Transition is measured at steady state High level - 500 mV or steady

state Low level + 500 mV on the output from the l.S level on the
input.
9. CS2 and CS, are used on the 7C271 only. m! is used on the 7C274
only.

Erasure Characteristics
intensity X exposure time) or 25 Wsec/cm2. For an ultra·
violet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 45 minutes. The 7C27l and
7C274 need to be within 1 inch of the lamp during erasure.
Permanent damage may result if the PROM is exposed to
high intensity UV light for an extended period of time.
72S8W X sec/cm2 is the recommended maximum dosage.

Wavelengths oflight less than 4000 Angstroms begin to
erase the 7C27l and 7C274 in the windowed package. For
this reason, an opaque label should be placed over the win·
dow if the PROM is exposed to sunlight or fluorescent
lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of2S37 Angstroms for a minimum dose (UV

3·101

•

~

CY7C271

W'r~ ====================CY=7C;;;;;;2;;;;7:;;;;4
Typical DC and AC Characteristics
NORM~SUPPLYCURRENT
VII.

1.6
1.4

0.8

/'

V

1.2~------~--------,

/

/

1.1 f - - - - - - t - - - - - - l

~

'"lE

~
8

..e

'"0z

Tt:J:X~
5.5

0.8~------~--------~

-55

6.0

~
~
II<
0
z

TEMPERATURE

'<

25

50

'"II

-

~

30

0

20

I!:
:>

10

:>

'"!5
0

0.6
25

TA =25OC

125

"'"

o

o

125

AMBIENT TEMPERATURE (OC)

1.0

,5.

J

25.0
20.0

/

15.0

;!:

-"

'"0

"

2.0

3.0

5.5

"

4.0

OUTPUT VOLTAGE (V)

10.0
5.0

V

V
o

o

V

/

/
TA -25"C
Vee = 4.5V

200

400

600

BOO

CAPACITANCE (pr)

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

VI.

175

!!Z
'"II'd1i

2 ~~! 32 31 3029

As 5" 3 2

A"
Z8
27 A,.
26 ALE

'u

0

:~!32

313°29 AI2

A, •
"
7
A, •

25 Ne
24 CP
23 'I;"
22

0,

00 13
21 0&
141516171B 19 20

27 "'4

0

A2 '
A, 10
. . 11
Ne 12

26 Ne
25 ALE

.-CS
23

00 13

,-4 15 16 17 18 1920
....

N CI

U

CE

22 07

I')

't

21 De

n

oOG z o o o

0136-5

0136-4

Selection Guide
7C279·45
Maximum Setup Time (ns)
Maximum Clock to Output (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)

7C277·40

Commercial

120

40
20
120

Military

30

Commercial
Military

7C279·55

7C277·50

55

45

Maximum Access Time (ns)

120
130

50
25
120
130
30
40

3·107

II

~

CY7C277
. .j~ =====================:;CY=7=:;C=:;2=79
Product Characteris~c$
The CY7C277 and cY7C279l/Ie high performance 32,768
word by 81* CMOS PROMs. When deselec~ed, the 7C279
automatically powers down into a low power standby
mode. The 7C277 and the 7C279 both are packaged in the
slim 28pjn 300 mil package. The ceramic package may be
equipped with an erasure window; when exposed to UV
light, the PROM ill erasc:d and can then be reprogrammed.
The memory cells utilize proven EPROM floating gate
technology and byte-wide algorithms.

asynchronous. When the asynchronous mode is selected,
the EIBs pin is sampled continuously and operates as an
outI'Ut enable. If the synchronous mode is selected, then
the EIBs pin is sampled only when CP is HIGH. Enablin£
the outputs in this mode is accomplished by bringing the Es
pin LOW and pulsing the CP InGH to latch the output
enable state. The 7C277 also provides a programmable bit
to enable the ADDRESS LATCH ENABLE (ALE) pin. If
this bit is not programmed, then the device will ignore the
ALE pin. If the ALE function is selected, the user may
define the polarity ofthe ALE signal with the default being
a positive ACTIVE signal.

The CY7C277 and CY7C279 otTer the advantages of lower
power, reprogrammability, superior performarice and high
programming yield. The EPROM cell requires only 12.SV
for the supervoltage and low current requirements alloW
for gang programming. Ttte EPROM cells allow for each
memory location to be 100% tested, as each location is
written into, erased, and repeatedly exercised prior to en·
capsulation. Eaoh PROM is also tested for AC perform·
ance to guarantee that ~ter customer programming the
project will meet DC and AC specification limits.

On the 7C279, address registers are provided to easily in·
terface with the Cypress 7COOl and other microprocessors
that clock their addresses. A programmable bit is provided
to select between Latched and Registered address inputs.
The default is registered inputs, which will sample the ad·
dress on the RISING EDGE of ALE and latch the address
into the address register. The Latched address option will
recognize any address changes while the ALE pin is
ACTIVE and latch the address into the address registers
on the FALLING EDGE of ALE. If the latched address
option is selected, then another programmable bit is pro·
vided for the user to select the polarity that will defme
ALE ACTIVE, with the default being positive polarity.

On the 7C277, the outputs are pipelined through a master·
slave register. On the rising edge ofCP, da~ is loaded into
the 8 bit edge triggered output register. The BIEs provides
a programmable bit to select between asynchronous and
synchronous operation. The default condition is

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
S~orage Temperature ............•.. -65°C to + lSO"C
Static Discharge Voltage ...... '" ............ >2001V
(Per MIL-STD·883 Method 3015)
Ambient Temperature with
Power Applied .................... - SsoC to + 125°C
Latchup Current .......................... > 200 mA
Supply Voltage to Qround PQtential
(Pin 24 to Pin 12) .................... -O.SV to +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to +7.0V

Range

DC Input Voltage ................... -3.0Vto +7.0V

Commercial
Military(2)

DC Program Voltage (Pins 7, 18,20) ............. l3.0V

Ambient
Temperature

Vee

O"Cto +70"C

5V ±lO%

- SSOC to + 12SOC

SV ±lO%

UV Erasure ...•..................... . 7258 Wsec/cm2

Electrical Characteristics Over Operating Range[3]
Parameters

Deserlption

Test Conditions

7C277·40
7C279·4S

Min.
VOH

Output HIGH Voltage

Vee

VOL

Output LOW Voltage

Vee

VIH

Input HIGH Level[4]

VIL

Input LOW Level[4]

IIX

Input Leakage CuiTent

VeD

Input Clamp Diode Voltage

= Min.,IOH = -2.0mA
= Min., IOL = 8.0 mA

2.4

Min.

-10

Vee
0.8

2.0

+10

-lO

Units

Max.

2.4
0.4

2.0
GND ~ VIN ~ Vee

Max.

7C277·50
7C279·55

V
0.4

V

Vee
0.8

V

+10

p.A

V

NoteS
VOL ~ VOUT ~ VOH, Output Disabled[6]

-40

+40

-40

+40

p.A

= Max., VOUT = 0.OV(7)
Vee = Max., VIH = 2.0V Commercial
lOUT = OmA
Military

-20

-90

-20

-90

mA

IOZ

Output Leakage Current

los

Output Short Circuit Current Vee

Icc

Power Supply Current

ISB[9]

Standby Supply Current

Vee = Max., ~ ~ VIH
lOUT = OmA
3·108

Commercial
Military

120

120

mA

130
30

30
40

mA

5n
.

CY7C277
CY7C279

~~==~~~~~~~~~~~~~~~~~~~~~~~~======~======

Capacitance [8]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Max.

Test Conditions
TA = 25°C,f
Vcc = 5.0V

Notes:
1. The 7C279 only has a standby mode.
2. T A is the "instant on" case temperature.

= 1 MHz

Units

8

pF

8

6. For devices using the synchronous enable,the device must be clocked

after applying these voltages to perform this measurement.
7. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
8. Tested initially and after any design or process changes that may
affect these parameters.

3. See the last page of this specification for Group A subgroup testing
information.
4. These are abaolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise. Do not at·
tempt to test these values without suitable equipment (see Notes on
Testing).
5. The CMOS process does not provide a clamp diode. However, the
CY7C277 and CY7C279 are insensitive to - 3V dc input levels and
- SV undershoot pulses ofless than 10 ns (measured at 50% point).

Switching Characteristics Over Operating Range!s)
Parameters

7C277·50

7C277·40

Description

Min.

Max.

Min.

Units

Max.

tAL

Address Setup to ALE Active

10

10

ns

tLA

Address Hold from ALE Inactive

10

15

ns

tLL

ALE Pulse Width

10

15

ns

tSA

Address Setup to Clock HIGH

40

50

ns

tHA

Address Hold from Clock HIGH

0

0

ns

IS

15

ns

tHES

Es Setup to Clock HIGH
Es Hold from Clock HIGH

10

10

tCO[J4]

Clock HIGH to Output Valid

tpwc

Clock Pulse Width

tLZC

Output Low Z from Clock HIGH

20

30

ns

tHZC[J4,9)

Output High Z from Clock HIGH

20

30

ns

tLZE
tHZE[J5,9]

Output Low Z from E LOW

20

30

ns

20

30

ns

tSES

20

Output High Z from E HIGH

3·109

ns
25

20
20

ns
ns

fin
.

CY7C277
CY7C279

~~=============================================================

Switching Characteristics Over Operating Rangel8)
Parameters

(Continued)
7C279-55

7C279-45

Description

Min.

Max.

Min.

Units

Max.

tAA[12]

Address Access to Output Valid

45

55

ns

tHZCS

Chip Select Inactive to High Z
Chip Select Inactive to Output Valid

30
30

ns

tACS

30
30

tAR

Address Register Setup to ALE Active

10

10

ns

tRA

Address Hold from ALE Active

10

10

ns

tADH

Data Hold from ALE Active

S

ns

tpu

Chip Enable Active to Power Up

5
0

tpD

Chip Enable Inactive to Power Down

tOH[12]

Output Hold from Address Change

tPWA

Address Register Pulse Width

0

ns

50
0

60

0

ns

ns

30

20

Notes:
9. tHZCS and tHZE are tested wtih the load shown in Figure lb. Transition is measured at steady state high level - 500 mV or steady state
low level + 500 m V on the output from the 1.5V level on the input.
10. These parameters apply to the 7C277 only.
II. These parameters apply to the 7C279 only.
12. tAA and toH apply only when the latched mode is selected.
13. Tests are performed with rise and fall times of 5 ns or less.

ns

ns

14. Applies only when the synchronous (Es) function is used.
15. Applies only when the asynchronous (E) function is used.
16. See Figure I a for all switching characteristics except tHZCS and
tHZE·
17. See the last page of this specification for Group A subgroup testing
information.
18. AU device test loads should be located within 2· of device outputs.

AC Test Loads and Waveforms[9, 16, 18]
Rl

Rl

500.n
(658.n t.lIL)

500.n
(658.0. t.lIL)

TINCLUDING
..L J1G AND
SCOPE

5pF

333.0.
(403.n t.lIL)

TINCLUDING
..LJIG AND
SCOPE

-=

333.n
(403.0. t.lIL)

-=
0136-8

Figure 1b

THEVENIN EQUIVALENT
200.0.

OUTPUT

o--"INv--O 2.00V

OUTPUT

o--"INv--O 1.90V

0136-6

Figure 2

0136-7

Figure 1a
Equivalent to:

GND

R2

R2

30pF

3.0V ---Jt-:=--~

COt.lt.lERCIAL

250.0.

t.lILlTARY
0136-14

3-110

fin

CY7C277
CY7C279
~NDU~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===

.

Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE

NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.2r-------r--------,

VS.

1.6

...

Jl

...

1.2

/

N

::::;

«~
II<

1.0

0

z
0.8

/'

/

/

1=

~
S
~

-

:!5
z

TA =25OC
f=IAAX.

0.8 '-------'---------'
-55
25
125

0.6

5.0

4.0

5.5

SUPPLY VOLTAGE (V)

AIABIENT TElA PERATURE (OC)

NORMALIZED ACCESS TIME
TEMPERATURE

OUTPUT SOURCE CURRENT
vs.VOLTAGE

VS.

1.6

1

1.4

60
50

<.>

.£'

...

1.2

~

1.0

Q

~
«

II<

-

~

0

z

30
20

0.8
0.6
-55

25

125

0.6
TA=25OC

0.4
4.0

4.5

5.0

'",-

/

...
,5.

20

J.

15

/

~

"

~

......

3.0

'"

4.0

OUTPUT VOLTAGE (V)

6.0

5.5

TYPICAL ACCESS TIME CHANGE
VS. OUTPUT LOADING
25

1.0

AIABIENT TElA PERATURE (OC)

0.8

30

10

o
o

1.0

SUPPLY VOLTAGE (V)

",

"

- r--

-

~

1.4
Q

NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE

1.2

1/

/"
10

5

V
TA =25OC
Vcc =4.5V

/

o
o

200

400

600

BOO 1000

CAPACITANCE (pF)

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

VS.

175

1....
...z
'"'"
:::l
U

""z

iii

....
:::l
....
:::l

150
125

/

100
75

/'

50

IL

0

25

V

o
o

/

/

Vcc =5.0VTA =25OC

1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)
0136-15

3-111

FAIL

FAIL
PASS
VCC= S.OV.Vpp= 12.SV.lst addr &: data

PASS

BLANK CHECK FAIL

0136-16

Figure 3. Programming Flowchart
Note:
For main array only. Sync. and ALE bits use 200 50 p.. pulses.

3-112

Timing Diagram (7C277)

ALE
ES _ _ _ _ __

II

CP

-.jtpwcttHzEi

E __________________________

=e

fO?l

HIGH

z~

I--tLZE--l
______
__

-J;---\~

0136-9

Timing Diagram (7C279)
VeeCURRENT
SUPPLY

~
CS

~

50 jl;

~

5~Ojl;

---------------------

dr-tACS
HIGH Z

C

X~

__~__

!r~
0136-10

Note:
ALE is shown with positive polarity.

All ofthe programming elements are EPROM cells and
are in an erased state when they are shipped. This erased
state manifests itself differently in each case. The erased
state for the synchronous function is ASYNCHRONOUS
mode. The erased state for the ALE function is: Registered
inputs on the 7C279 and no ALE function on the 7C277.
In the erased state, the memory location contains neither a
one nor a zero. The erased state of the device can be verified by using the BLANK CHECK ONES and BLANK
CHECK ZEROS function (see mode t~ble).
To choose the ALE function, the ALE bit must be programmed. This is done by raising A9 to Vpp, taking AI4
LOW and pulsing PGM LOW. When the ALE function is
chosen, it is active with positive polarity. To choose negative polarity, A9 must be at Vpp, AI4 must be raised
HIGH ~d PGM must be pulsed LOW. The 7C277 comes
with a synchronous option. To choose this option, the SYN
bit must be programmed. This is done by taking AI4 to
Vpp and pulsing PGM LOW.

Erasure Characteristics
Wavelengths oflight less than 4000 Angstroms begin to
erase the 7C277 and 7C279. For this reason, an opaque
label should be placed over the window if the PROM is
exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with
a wavelength of 2537 Angstroms for a minimum dose (UV
intensity X exposure time) of25 Wsec/cm2. For an ultraviolet lamp with a 12 mW Icm 2 power rating the exposure
time would be approximately 45 minutes. The 7C277 and
7C279 need to be within 1 inch of the lamp during erasure.
Permanent damage may result if the PROM is exposed to
high intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.

Device Programming
There are several independent programmable functions
contained in the 7C277 and 7C279 CMOS 32K x 8 registered PROM. Both devices have the 32K x 8 array and a
programmable ALE function. The 7C277_also contains a
programmable synchronous function  1500V static discharge

Product Characteristics
The CY7C281 and CY7C282 are high
performance 1024 word by 8 bit CMOS
PROMs. They are functionally identical, but are packaged in 300 mil and
600 mil wide packages respectively.
The CY7C281 is also available in a 28
pin leadless chip carrier. The memory
cells utilize proven EPROM floating
gate technology and byte-wide intelligent programming algorithms.
The CY7C281 and CY7C282 are plugin replacements for bipolar devices and
offer the advantages of lower power,
superior performance and programming yield. The EPROM cell requires
only 13.5V for the supervoltage and

Logic Block Diagram

low current requirements allow for
gang programming. The EPROM cells
allow for each memory location to be
tested 100%, as each location is written
into, erased, and repeatedly exercized
prior to encapsulation. Each PROM is
also tested for AC performance to
guarantee that after customer programming the product will meet DC and
AC specification limits.
Reading is accomplished by placing an
active LOW signal on CSI and CS2,
and active HIGH signals on CS3 and
CS4. The contents of the memory location addressed by the address lines
(Ao-A9) will become available on the
output lines (00-07).

Pin Configurations
Vee

A.,
A.
A,
A6
As

A.

Ag

ROW
DECOOER
10F64

64 x 128
PROGRAMMABLE
ARRAY

CS,
CS2

8x 1 OF 16

MULTIPLEXER

A.

CS3

CII4

L---f-l:>O-o.

COLUMN
DECODER
1 OF 16

t---------..J
t------------'

0,

00

o.

0,

Os

02

O.

GND

03
0009-2

L----Hl>_O,
00

Cs,=~I-_
CS2
CS3

}--------------------'

CII4---Ir---

A.

5

A3
A2
A,
AD

6
7

• 3 2111282726
w
25 ~,
2.
23

22
2'

CS2
CS3
CS.
Ne

He

10

20

07

00

"12'3"'5'6'7,';9

06

0009-'
_

('1,10 (,)

Iot)

.... . "

oOlSzOOO

Selection Guide
7C281-30
7C282-30
Maximum Access Time (ns)
Maximum Operating
Current (mA)

30

Commercial
Military
3-118

100

7C281-45
7C282-45
45
90
120

0009-3

5A
~ ~~DUCTOR ~========================================================================
CY7C281
CY7C282

...

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -6SoC to

+ ISO"C

Ambient Temperature with
Power Applied .................... - 55°C to

Static Discharge Voltage ..................... > IS00V
(per MIL-STD-883, Method 301S)

+ 125°C

Latch-up Current ..........................

Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -O.SV to
DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to
DC Input Voltage ................... - 3.0V to

> 200 rnA

Operating Range

+ 7.0V
+ 7.0V
+ 7.0V

Ambient
Temperature

Vee

Commercial

O°Cto + 70°C

5V ±IO%

-55°C to + 125°C

5V ±IO%

Military [1l

DC Program Voltage (Pins 18, 20) ............... 14.0V

II

Range

Electrical Characteristics Over the Operating Range[2)
Parameters

Description

7C281-30
7C282-30

Test Conditions

Min.
VOH

Output HIGH Voltage

Vec = Min., IOH = - 4.0 rnA

VOL

Output LOW Voltage

VCC = Min., IOL = 16.0 rnA

VIH

Input HIGH Level[3]

7C281-45
7C282-45

Max.

2.4

Min.

Units

Max.

2.4
0.4

V
0.4

2.0

V

2.0

V

VIL

Input LOW Level[3]

IIX

Input Current

VCD

Input Diode Clamp
Voltage

loz

Output Leakage Current

VOL :s; VOUT :s; VOH, Output Disabled

-40

+40

-40

+40

/LA

los

Output Short
Circuit Current[S]

Vcc = Max., VOUT = GND

-20

-90

-20

-90

rnA

ICC

Power Supply
Current

Vcc = Max.,
lOUT = OmA

90

rnA

120

rnA

0.8
-10

GND:S; VIN:S; Vcc

+10

Note 4

I Commercial
I Military

-10

0.8

V

+10

/LA

Note 4

100

Capacitance [6]
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions

Max.

TA = 25°C,f= 1 MHz
Vcc = 5.0V

5

Units
pF

8

Notes:
1. TA is the "instant on" case temperature.

4. The CMOS process does not provide a clamp diode.

2. See the last page of this specification for Group A subgroup testing

However, the CY7C28I & CY7C282 are insensitive to - 3V de input
levels and - SV undershoot pulses ofless than 10 ns (measured at
SO% point).
S. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
6. Tested initially and after any design or process changes that may

information.

3. These are absolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.

affect these parameters.

3-119

fin~aoR=============================================================
CY7C281
CY7C282

. .

Switching Characteristics Over the Operating Range[2. 71
Parameters

CY7C281-30
CY7C282-30

DeseriptiOD

CY7C281·45
CY7C282-45

Max.
30

Mm.
tAA

Address to Output Valid

tHzcs

Chip Select Inactive to High Z18]

20

tACS

Chip Select Active to Output Valid

20

Max.
45
25
25

Min.

Units
ns

ns
ns

AC Test Loads and Waveforms
R1250n

R1250n

5Vo---------~~~

5Vo-...............~~~

0-----_------1

OUTPUT o-----~------..

OUTPUT

INCLUDING
JIG AND
SCOPE

I

R2

30 pF

167n

INCLUDING
JIG AND
SCOPE

I

AI--

::: ---::If

';5ns~

R2

5 pF

90%

167n

0009-8

Figure 2. Input Pu1ses
0009-4

Figurela
Equivalent to:

Figurelb

THEVENIN EQUIVALENT

loon
OUTPUT 0 .....----0"1
..
""
...""
..,.....---0 2.0 V
0009-5

AD-A,O
ADDRESS

~~
1\

CBs.CS.

--------~--------1..,.-::::
-tAA

00-07

~(

~~
J

0'§1o~

!--tHzcs

Notes:
7. Test conditions assume signal transition times of 5 ns or less. timing
reference levels of 1.5V. output loading of the specified IOlJIoH and
loads shown in Figure I a, lb.

!---tAcs

0009-7

8. tHZCS is tested with load shown in Figure lb. Transition is measured
at steady state High level + 500 mV or steady state Low level + 500
mV on the output from the 1.5V level on the input.

3·120

Typical DC and AC Characteristics
NO~SUPPLYCURRENT

NORMALIZED SUPPLY CURRENT

va SUPPLY VOLTAGE

1.6
1.4

/

u

J:

c

 2001V static discharge

The CY7C285 and CY7C289 offer the
advantage oflow power, superior performance and programming yield. The
EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each
memory location to be 100% tested,
with each location being written into,
erased and repeatedly exercised prior
to encapsulation. Each PROM is also
tested for AC performance to guarantee that after customer programming
the product will meet DC and AC
specification limits.
Reading the CY7C285 is accomplished
by placing an active LOW signal on the
CS pin. Reading the CY7C289 is accomplished by placing an active LOW
signal on the CE pin and by placing
active HIGH signals on the CS, or CS2
pins as appropriate. The contents of the
memory location addressed by the address lines (AQ-A,s) will become available on the output lines (00-0,).

Pin Configurations

Logic Block Diagram

CY7C285

CY7C289

Ag

A,

....

A,

A.

"
"
"
A,

8

11I11I'\JT
BUffE.

HH~:»-',

GN'

0,

H-[)O--·,

"
HH:)o--',

0146-6

LCCPinout

..

A5 5" 3

'
"

7

....

Ne •
A,

10

.. "

GND

12

LCCPinout

.t::~~~1i
2

;~!32

:t~~.r~1;

313°29 A'2
11,5 5"

o

28 A'3
27 A'4

A.. Ii

26 A'5
25 Ne

CP/ALE 8

24 CS
23

WAIT

22 07
00 13
21 GND
14151617181920

"

7

....

AI 10

Ao

11

GND 12

3

2

t~! 32

o

Document #: 38-00097
3-127

0146-3

28

A13

27 A.'4
26 A.15
25 CE

24 CS1
23 WAIT

220,

00 13

21 GND
14 15 IS 17 18 19 20

OON~O....

0146-1

31 3°29 A12

ttcr/!
0146-7

•

CY7C286
CY7C287

ADVANCED INFORMATION

CYPRESS
SEMICONDUCTOR

65,536 X 8 PROM
Reprogrammable Registered

Features

Product Characteristics

• CMOS for optimum speed!
power

The CY7C286 and the CY7C287 are
high performance 65,536 by 8 bit
CMOS PROMs. The CY7C286 is configured in the JEDEC standard 512K
EPROM pinout. It is available in a 28pin, 600 mil package. Power consumption on the CY7C286 will be 120 rnA
in the active mode and 40 mA in the
standby mode. Access time is 60 ns;
The CY7C287 has registered outputs
and operates in the synchronous mode.
It is available in a 28-pin, 300 mil package. The address setup time is 55 ns
and the time from clock high to output
valid is 20 ns. Both the CY7C286 and
CY7C287 are available in a CERDIP
package equipped with an erasure window to provide reprogrammability.
When exposed to UV light, the PROM
is erased and can be reprogrammed.
The memory cells utilize proven
EPROM floating gate technology and
byte-wide intelligent programming algorithms.

• Windowed for reprogrammability
• High speed
- tsu = 55 ns (7C287)
- teo = 20 ns (7C287)
- tAA = 60 ns (7C286)
• Low power
- 120 mA active (7C286)
- 40 mA standby
• WAIT signal
• Chip Select Decoding
• EPROM technology, 100%
programmable
• 5V ± 10% Vce, commercial and
military
• TTL compatible I/O
• Slim 300 mil package (7C287)
• Capable of withstanding
> 2001 V static discharge

Logic Block Diagram

The CY7C286 and CY7C287 otTer the
advantage of low power, superior performance and programming yield. The
EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each
memory location to be 100% tested,
with each location being written into,
erased and repeatedly exercised prior
to encapsulation. Each PROM is also
tested for AC performance to guarantee that after customer programming
the product will meet DC and AC
specification limits.
Reading the CY7C286 is accomplished
by placing active LOW signals on the
UB and CE pins. Reading the
CY7C287 is accomplished by placing
an active low signal on EIBs. The contents ofthe memory location addressed
by the address line (Ao-A\s) will become available on the output lines
(00-07)·

Pin Configurations
CY7C286

A"
A,.
Au

CY7C287

8-BIT
EDGE-

A"

TRIGGERED

....

Au

AU

REGISTER

A,o

'"
A"
',.

.,...
A,

'----IH.~.....

A,
A,

o
o
o
o

A,
AO

A, •
CP

I..-.+-Doo-o,

...

;-----_.
I

'---+--D~o,

i____ . _______. ________ . . . ___.

CE

Efts

o,

0,

I

i_ .... ~ ___ ................. _........ _.. __ ...... ___ .... L~c:!~2~L!>.... _..............................:

0151-6

0151-2

LCCPinout
i/Es

LCCPinout

~~~!~];

CP

0151-1

As

5 4

A46

:~:
~

9

A,

10

3

As

As

54 3

28Ag

~

6

2 ~~! 32 31 3029

0 :

~I

25 Ne

24 A'0

Ao'1

23CE

GND 12

22 0,

0 0 13

21 GND

1-4- Hi 16 17 18 19 20

A, 7

~ 8

~9

"I

Ao

10

11
CND 12

21~:32

0

31 3029

"u

~ "13

27 "14
H "15
25NC
24 CP
23 flEs
22 0,

00 13
21 GND
14 15 16 17 18 19 20

ocr~ ~o"ol()rf

0151-7

Document #: 38-00103
3-128

0151-4

CY7C291
CY7C292

CYPRESS
SEMICONDUCTOR

Reprogrammable 2048 X 8
PROM

Features
• Capable of withstanding
static discharge

• Windowed for reprogrammability
• CMOS for optimum
speed/power

> 2000V

Product Characteristics

• High speed
- 35 ns (commercial)
- 35 ns (military)

The CY7C291 and CY7C292 are high
performance 2048 word by 8 bit CMOS
PROMs. They are functionally identical, but are packaged in 300 mil and
600 mil wide plastic and hermetic DIP
packages respectively. The 300 mil ceramic DIP package is equipped with an
erasure window; when exposed to UV
light the PROM is erased and can then
be reprogrammed. The memory cells
utilize proven EPROM floating gate
technology and byte-wide intelligent
programming algorithms.
The CY7C291 and CY7C292 are plugin replacements for bipolar devices and
offer the advantages of lower power,

• Low power
- 330 mW (commercial)
- 413 mW (military)
• EPROM technology 100%
programmable
• Slim 300 mil or standard 600
mil packaging available
• 5V ± 10% Vee, commercial and
military
• TTL compatible I/O
• Direct replacement for bipolar
PROMs

Logic Block Diagram

reprogrammability, superior performance and programming yield. The
EPROM cell requires only 13.5V for
the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each
memory location to be tested 100%, as
each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that
after customer programming the product will meet DC and AC specification
limits.
Reading is accomplished by placing an
active LOW signal on CSt, and active
HIGH signals on CS2 and CS3. The
contents of the memory location addressed by the address lines (Ao-AIO)
will become available on the output
lines (00-07).

Pin Configurations

AlO

0,

A9
As
A7
A6

ROW
DECODER
1 OF 128

128)( 128
PROGRAMMABLE
ARRAY

.f .,t'';: ~

As

0,

8}( 1 OF 16

A,

MULTIPLEXER

As
A,

0,

cs,
0,

A2

0,

5 43

,

A,
A,
A,

7
8

Ne

"

10

0,

11

" ,

.y,

-««l

2~28272625
2'
2'
22
2'
20

0

I.

A"

CS,

es,
es,
Ne
07
0.

12131415161718

a 0t§:zooo

0,

NO 0

,..,

'ot

If}

0008-3

0,
0,

cs,===~~}-

cs,

0008-2

Window available on
300 mil cerdip only

________________________________J

CS3--~""'''

0008-1

Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)

STD
L

Commercial
Military
Commercial

*7C291 only

3-129

7C291-35
7C292-35
35
90
120'
60

7C291-50
7C292-50
50
90
120
60

3

(in

CY7C291
CY7C292

~~NDUCTOR ==========================================================================

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65'C to + 150'C

Static Discharge Voltage ..................... >200IV
(per MIL-STD-883, Method 3015)

Ambient Temperature with
Power Applied .................... - 55'C to + 125'C

Latchup Current .......................... > 200 rnA

Supply Voltage to Ground Potential .... -0.5V to + 7.0V
(Pin 24 to Pin 12)

Operating Range

DC Voltage Applied to Outputs
inHighZState ...................... -0.5Vto +7.0V

Range

DC Input Voltage ................... - 3.OV to + 7.0V

Commercial

DC Program Voltage (Pins 18,20) ............... 13.0V

Military! 6]

Ambient
Temperature

VCC

O'Cto +70'C

5V ±10%

- 55'C to + 125'C

5V ±10%

UV Exposure ........................ 7258 Wsec/cm2

Electrical Characteristics Over the Operating Range[S]
Parameters

Description

7C291L-35, 50
7C292L-35, 50

Test Conditions

Min.

Max.

7C291-35,50
7C292-35, 50
Min.

2.4

Units

Max.

2.4

V

VOH

Output HIGH Voltage

VCC

=

Min., IOH

=

-

VOL
VIH[!]

Output LOW Voltage

Vcc

=

Min., IOL

=

16.0mA

VIL!l]

Input LOW Voltage

Ilx

Input Load Current

VCO

Input Diode Clamp
Voltage

loz

Output Leakage
Current

GND s VOUT s Vec,
Output Disabled

-40

+40

-40

+40

IJ-A

los

Output Short
Circuit Current!l]

Vcc = Max.,
VOUT = GND

-20

-90

-20

-90

rnA

Iec

Vcc Operating
Supply Current

Vec = Max.,
lOUT = OmA

90

rnA

120

rnA

4.0 rnA

0.4

Input HIGH Voltage
GND S VIN S Vce

0.4

V

2.0

Vcc
0.8

2.0

Vcc
0.8

V

-10

+10

-10

+10

IJ-A

Note 2

I Commercial
I Military·

V

Note 2

60

*-35:7C2910nly

Capacitance [41
Parameters

Description

CIN

Input Capacitance

COUT

Output Capacitance

Test Conditions
TA = 25'C, f
Vcc = 5.0V

=

1 MHz

Max.
5
8

Units
pF

Notes:
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may
affect these parameters.
5. See the last page of this specification for Group A subgroup testing
information.
6. TA is the Hinstant on" case temperature.

I. These are absolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.
2. The CMOS process does not provide a clamp diode. However, the
CY7C291 and CY7C292 are insensitive to -3V dc input levels and
- SV undershoot pulses of less than 10 ns (measured at 50% point).

3-130

Switching Characteristics Over the Operating Range[5, 7)
Parameters

7C291·50
7C292·50

7C291·35
7C292·35

Description

Min.
tAA

Address to Output Valid

tHZCS

Chip Select Inactive to High Z[s)

tACS

Chip Select Active to Output Valid

Min.

Max.

Units

Max.

50
25
25

35
25
25

ns
ns
ns

AC Test Loads and Waveforms
RI250n

R1250n

5Vo-------~~~

3.0 V----:I!::-:::::::---~_

5Vo-------~~~

OU~UTo-----~------~

OUTPUT
R2
187n

INCLUDINGI 30 pF
JIG AND
SCOPE

0---_---.. .

INCLUDING
JIG AND
SCOPE

I

GND--""';OiJ

s5 no
6 pF

~5ns

R2
167n

0008-6

Figure 2. Input Pulses
0008-4

Figure 18
Equivalent to:

Figure Ib

THEVENIN EQUIVALENT

loon

OUTPUT 0

£

.'t .
....

o

2.0V
0008-5

AD-AID
ADDRESS
CS 2 -CS 3

CS 1

°0-°7

t,~
XX

0008-7

Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, output loading of the specified IOlJIoH and
loads shown in Figures 1a. lb.

S. tHZCS is tested with load shown in Figure lb. Transition is measured
at steady state High level - 500 m V or steady state Low level + 500
m V on the output from the 1.5V level on the input.

3-131

&n~~NDUcrOR======================================================================
CY7C291
CY7C292

Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE

1.2.------r--------,

1.4

1.2

L

N

::;

«

~
z

1.0

O.S

O. 6

V

V

::!i

;=

/

!:!

::!i

~

o

«
~

5.0

0.S~55L....----2..l.5--------I125

6.0

5.5

~
W

::;

w

«

0

z

50

25.0

a:
a:

""

-

,...-

(J

w

::>
0

20

...

10

...'"::>

I-

::>
0

-55

25

30

(J

a:

O.S

0.6

40

::>

::!i

a:

30.0

I-

125

AMBIENT TEMPERATURE I'CI

o

o

!

"- r--....

"
1.0

<
!
I-

z

125

a:
a:

100

w

::>

,......--

150

/

"z

75

!5...

50

iii

25

o

Vee =5.0V
TA = 25'C

/

I-

::>
0

~

/

(J

/

0.0

L

1.0

2.0

3.0

/

$ 15.0

'"1""-

4.0

/

~ 10.0
5.0
0.0

V

TA = 25'C

Vee =4.5 V

/

o

200

400

A,

Vee

As

As

As

A9

A_

A,o

A3

Vpp (CS,I

A,

VFY ICS21

A,

PGM ICS31

Ao

D,

Do
D,

D6

D,

D5
D_

GND

D3

4.0

0008-9

Figure 3. Programming Pinout

OUTPUT VOLTAGE IVI
0008-8

3-132

600

CAPACITANCE IpFI

OUTPUT VOLTAGE IVI

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

6.0

/

20.0

«

3.0

5.5

..--

!:4

2.0

175

5.0

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING

60

Z

1.0

4.5

SUPPLY VOLTAGE IVI

OUTPUT SOURCE CURRENT
vs.VOLTAGE

1.4

0

N

0.4
4.0

AMBIENT TEMPERATURE I'CI

<
!

1.2

I
TA i25'C

I=MAX.
4.5

0.6

~

=25'C

~
(J

'-....

::;

1.6

w

~

O.S

W
N

TA

4.0

............

w

NORMALIZED ACCESS TIME
vs. TEMPERATURE

w
::!i

...............
1.0

~

SUPPLY VOLTAGE IV)

;=

1.2
w

u

Ii!

NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE

NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

1.6

SOO

1000

5n
.

CY7C291
CY7C292
~mruaoR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==

Programming Algorithm

•

DEVICE BAD

0008-10

The CY7C291 and CY7C292 programming algorithm allows significantly faster programming than the "worst case" specification of 10 msec.
Typical programming time for a byte is less than 2.5 msec. The use of EPROM cells allows factory testing of programmed cells, measurement of data
retention and erasure to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.
The algorithm utilizes two different pulse types: initial and overprogram. The duration of the PGM pulse (tpp) is 0.1 msec which will then be followed by a
longer overprogram pulse of 24 (0.1) (X) msec. X is an iteration counter and is equal to the NUMBER of the initial 0.1 msec pulses applied before
verification occurs. Up to four 0.1 msec pulses are provided before the overprogram pulse is applied.
The entire sequence of program pulses and byte verification is performed at Vccp = 5.0V. When all bytes have been programmed all bytes should be
compared (Read mode) to original data with V cc = 5.0V.

Figure 4. Programming Flowchart

3-133

Q. .

CY7C291
CY7C292

• CYPRESS

~~================~
The 7C29 I needs to be within I inch of the lamp during
erasure. Permanent damage may result ifthe PROM is
exposed to high intensity UV light for an extended period
oftime. 7258W X sec/cm2 is the recommended maximum
dosage.

Programming Information
The 7C29 I and 7C292 2K x 8 CMOS PROMs are implemented with a differential EPROM memory cell. The
PROMs are delivered in an erased state, containing neither
"Is" nor "Os". This erased condition ofthe array may be
assessed using the "BLANK CHECK ONES" and
"BLANK CHECK ZEROS" function, see below.

Blank Check
A virgin device contains neither ones nor zeros because of
the differential cell used for high speed. To verify that a
PROM is unprogrammed, use the two blank check modes
provided in Table 3. In each of these modes, the locations 0
thru 2047 should be addressed and read. A device is considered virgin if all locations are respectively" I s" and "Os"
when addressed in the "BLANK ONES AND ZEROS"
modes.
Because a virgin device contains neither ones nor zeros, it
is necessary to program both ones and zeros. It is recommended that a11locations be programmed to ensure that
ambiguous states do not exist.

Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to
erase the 7C291. For this reason, an opaque label should be
~1aced over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods oftime.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity X exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 30-35 minutes.

DC Programming Parameters TA

= 25°C

Table 1
Parameter
Vpp

Description
Programming Voltage li]

Vccp

Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage[2]
Output LOW Voltage[2]

VIHP
VILP
VOH
VOL
Ipp

Min.
12.0
4.75
3.0

0.4
2.4

=

Units

V
V
V
V
V
V

0.4
50

rnA

Min.

Max.

Units

100

10,000

jJ.s

Programming Supply Current

AC Programming Parameters TA

Max.
13.0
5.25

25°C
Table 2

Parameter
tpp

Description
Programming Pulse Width[3]

tAS

Address Setup Time

1.0

jJ.s

tos

Data Setup Time

1.0

jJ.s

tAH

Address Hold Time

1.0

jJ.s

tOH
tR, tF

Data Hold Time
Vpp Rise and Fall Time[3]

1.0

jJ.s

1.0

jJ.s

tvo
typ

Delay to Verify

1.0

jJ.s

Verify Pulse Width

2.0

jJ.s

tov

Verify Data Valid

1.0

jJ.s

toz

Verify to High Z

1.0

jJ.s

Notes.
1. Vccp must be applied prior to Vpp.
2. ~uring verify operation.

3. Measured 10% and 90% points.

3-134

Mode Selection
Table 3
Pin Function

CS3

CS:z

~1

PGM

VFY

Vpp

(18)

(19)

(20)

VIR

VIR

VIL

Data Out

X

X

VIR

HighZ

Output Disable[4]

X

VIL

X

HighZ

Output Disable[4]

VIL

X

X

HighZ

Program

VILP

VIRP

Vpp

Data In

Program VerifY

VIHP

VILP

Vpp

Data Out

Program Inhibit

VIHP

VIHP

Vpp

HighZ

Intelligent Program

VIHP

Vpp

Data In

Blank Check Ones

VILP
Vpp

VILP

VILP

Ones

Blank Check Zeros

Vpp

VILP

Zeros

Read or Output DIsable

Mode

Other
Pin Nnmber

Read

Output Disable[4]

Notes:
4. X = Don't care but not to exceed Vcc

VIHP

+ 5%.

Outputs
(9-11,13-17)

II

5. During programming and verification, all unspecified pins to be at
VILP·

Programming Sequence 2K x 8
location is programmed with a single pulse. Any location
that fails to verify causes the device to be rejected.

Power the device for normal read mode operation with pin
18, 19 and 20 at VIH. Per Figure 5 take pin 20 to Vpp. The
device is now in the program inhibit mode of operation
with the output lines in a high impedance state; see Table 3.
Again per Figure 5 address, program, and verify one byte
of data. Repeat this for each location to be programmed.

If the intelligent programming technique is used, the program pulse width should be 100 ,""S. Each location is ultimately programmed and verified until it verifies correctly
up to and including 4 times. When the location verifies, one
additional programming pulse should be applied of duration 24 x the sum of the previous programming pulses before advancing to the next address to repeat the process.

If the brute force programming method is used, the pulse
width of the program pulse should be 10 ms, and each

PROGRAM
OTHER BYTES
PROGRAM

r

VERIFY

~
,

VIHP - - -

ADDRESS STABLE

ADDRESS
VILP---

~'t!;;.::

VIHP---

-

DATA
VILP---

PROGRAMMING
VOLTAGE (PIN 20I

VILP---

\

tRI-f.--tAS_

\/pp---

VIHP---

,

'I

,..

-

DATA IN

VILP---

",

1/

DATA OUT

l4

r

II

\

~-.:l.-

~5

r

----:If-

_ t•• _

VIHP---

Pm\l

toH

-

,r
toVi-

L..J

,r 5

...
----tvD

tv.-

VIHP---

...,

VFY

...

r

VILP - - -

0008-11

Figure 5. Programming Waveforms
3-135

r;n
.
. .

CY7C291
CY7C292

~;;~~~~~~~~~~~~~~~~~~~~~~~~~~=======

Ordering Information
Ordering
Code

Speed

Icc

(DS)

(mA)

35

60

CY7C291L-35PC

P13

CY7C291L-35WC

W14

90

CY7C291-35PC

P13

120
50

60
90

120

Package

Type

CY7C291-358C

813

CY7C291-35WC

W14

CY7C291-35LC

L64

CY7C291-35WMB

W14

CY7C291-350MB

014

CY7C291L-SOPC

P13

CY7C291L-50WC

W14

CY7C291-50PC

P13

CY7C291-S08C

813

CY7C291-S0WC

W14

CY7C291-S0LC

L64

CY7C291-50WMB

W14

CY7C291-S00MB

014

CY7C291-50LMB

L64

CY7C291-SOQMB

Q64

Operating
. Range

Commercial

Speed

Icc

Ordering

Package

(us)

(mA)

Code

Type

Range

35

60

CY7C292L-3SPC

PH

Commercial

CY7C292L-3SDC

012

90

CY7C292-35PC

PH

CY7C292-350C

012

50
Military
Commercial

Military

60
90
120

CY7C292L-50PC .

PH

CY7C292L-SOOC

012

CY7C292-S0PC

PH

CY7C292-500C

012

CY7C292-500MB

012

Operating

Commercial

Military

fin~~===================
CY7C291
CY7C292

.

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

IOZ

1,2,3

Icc

1,2,3

•

Switching Characteristics
Parameters

Subgroups

tAA

7,8,9,10,11

tACS

7,8,9,10,11

Document"": 38-00007-C

3-137

CY7C291A
CY7C292A/CY7C293A

CYPRESS
SEMICONDUCTOR

Reprogrammable 2048 X 8
PROM

Features
• Windowed for reprogrammabiUty
• CMOS for optimum
speed/power

• Capable of withstanding
static discharge

> 2OO1V

Product Characteristics

• High speed
- 25 ns (commercial)
- 30 os (military)

• TIL compatible I/O

The CY7C291A, CY7C292A, and
CY7C293A are high performance 2048
word by 8 bit CMOS PROMs. They
are functionally identical, but are packaged in 300 mil (7C291A, 7C293A)
and 600 mil wide plastic and hermetic
DIP packages (7C292A). The
CY7C293A has an automatic power
down feature which reduces the power
consumption by over 70% when deselected. The 300 mil ceramic DIP package is equipped with an erasure window; when exposed to UV light the
PROM is erased and can then be reprogrammed. The memory cells utilize
proven EPROM floating gate technology and byte-wide intelligent programming algorithms.

• Direct replacement for bipolar
PROMs

The CY7C291A, CY7C292A, and
CY7C293A are plug-in replacements

• Low power
-

330 mW (commercial)

-

660 mW (military)

• Low standby power
- 165 mW (commercial)

-

220 mW (military)

• EPROM technology 100%
programmable
• Slim 300 mil or standard 600
mil packaging available
• 5V ± 10% Vee. commercial and

military

Logic Block Diagram

A1

Ae

As

Reading is accomplished by placing an
active LOW signal on CSl, and active
HIGH signals on CS2 and CS3. The
contents of the memory location addressed by the address lines (Ao-AIO)
will become available on the output
lines (00-07).

Pin Configurations

A,O

Ae
Ae

for bipolar devices and offer the advantages oflower power, reprogrammabiIity, superior performance and programming yield. The EPROM cell requires
only 12.5V for the supervoltage and
low current requirements allow for
gang programming. The EPROM cells
allow for each memory location to be
tested 100%, as each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Each PROM is
also tested for AC performance to
guarantee that after customer programming the product will meet DC and
AC specification limits.

0,
ROW
DECODER
1 OF 12B

121 x 128
PROGRAMMABLE
ARRAY

0,

A,

Vee

A,

Ae

A.

..r..t~~~~l'
15 '" 3

00

" •
1

A.

o.

A!
A!

0,

Au

0,

00

0,

'2

0,

.. 0

23
22
21
10
20
11
19
12131415161718

" ••

NC
00

o

0,

0,

.

2l!J28272~5 A,o
Cs,

C'lQ

0"'''

CS,

CS.

NC
0,
0,

II)

o~zooo

0120-3
0120-2

00

Window available on
7C29lA and 7C293A
only.

0120-1

Selection Guide

Maximum Access Time (ns)
Maximum Operating
Current (rnA)

STD
L

Stanqby Current (rnA)
7C293AOnly

Commercial
Military
Commercial
Commercial
Military

7C291A-25
7C292A-2S
7C293A-25
25
120

7C291A-30
7C292A-30
7C293A-30
30
120

30
40
3-138

7C291A-35
7C292A-35
7C293A-35
35
90
120
60
30
40

7C291A-50
7C292A-50
7C293A-50
50
90
120
60
30
40

&n
.

CY7C291A
CY7C292A1CY7C293A

~CKN~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature •.............. -6S·C to + lSO"C

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883, Method 3015)

Ambient Temperature with
Power Applied ......•............. - SS·C to + l2S·C

Latchup Current ..................•..•.... > 200 rnA

Supply Voltage to Ground Potential •... -O.SV to +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... - O.SV to + 7.0V

Ambient
Temperature

Range

DC Input Voltage .....•............. - 3.0V to + 7.0V

II

Vee

DC Program Voltage •......................... 13.0V

Commercial

OOCto +700C

5V ±10%

UV Exposure ........•.•..•.......... 7258 Wsec/cm2

Military[S]

- 55·C to + l25·C

SV ±10%

Electrical Characteristics Over the Operating Range[6]
Parameten

Description

7C291A-25 7C291A-30 7C291AL-35, 50
7C292A-25 7C191A-30 7C292AL-35, 50
7C293A-25 7C293A-30 7C293AL-35, 50

Test Conditions

Min. Max. Min. Max.

~OH

Output HIGH Voltage Vee = Min.,
IOH = -4.0mA

VOL

Output LOW Voltage

2.4

Vcc = Min.,
IOL = -16.0 mA

2.4
0.4

2.0

Min.

Min.

Max.
V

2.4

2.4
0.4

0.4

V

Vee

V

VIH

Input HIGH Voltage
Input LOW Voltage

hx

Input Load Current

VCD

Input Diode Clamp
Voltage

loz

Output Leakage
Current

GND ~ VOUT ~ Vee,
Output Disabled

-40 +40 -40 +40

-40

+40

-40

+40

IJ-A

los

Output Short
Circuit Current!!)

Vcc = Max.,
VOUT = GND

-20 -90 -20 -90

-20

-90

-20

-90

rnA

Icc

VCC Operating
Supply Current

Vcc = Max., Commercial
lOUT = OmA Military

120

90

rnA

120

rnA

Standby Supply
VCC = Max., Commercial
Current (7C293A Only) CSI ~ VIH
Military

30

ISB

GND

~

VIN

~

Vee

-10 +10 -10 +10

Vcc

Note 2

2.0

0.8

0.8

Note 2

Vcc

2.0

0.4

VIL

VCC

2.0

Max.

7C291A-35, 50
7C292A-35, 50
Units
7C293A-35, 50

0.8
-10

+10

Note 2

-10

0.8

V

+10

IJ-A

Note 2

60
120
30
40

30

rnA

40

rnA

Capacitance [4]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions
TA = 25·C, f
Vcc = 5.0V

Notes:
1. These are absolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment.
2. The CMOS process does not provide a clamp diode. However, the
CY7C29lA, CY7C292A and CY7C293A are insensitive to - 3V dc
input levels and - SV undershoot pulses ofless than 10 ns (meaaured
at 50% point).

=

1 MHz

Max.
5

Units
pF

8

3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may
affect these parameters.
S. TA is the uinstant on" case temperature.

6. See the last page of this specification for Group A subgroup testing
information.

3-139

fin~OO~=============================================================
CY7C291A
CY7C292AJCY7C293A

.

Switching Characteristics Over the Operating Range[6, 7)
Parameters

7C291A·25
7C292A·25
7C293A·25

Description

Min.

7C291A·30
7C292A·30
7C293A·30
Min.

Max.

7C291A-35
7C292A·35
7C293A·35

Max.

Min.

Max.

7C291A·50
7C292A·50
7C293A·50
Min.

Units

Max.

tAA

Address to Output Valid

25

30

35

50

ns

tHZCSI

Chip Select Inactive to High Z[S)

20

20

25

25

DS

tACSI

Chip Select Active to Output Valid

20

20

25

25

ns

tH~

Chip Select Inactive to High Z[9]
(7C293A CSI Only)

27

32

35

45

ns

tACS2

Chip Select Active to Output Valid
(7C293A CSI Only)[9]

27

32

35

45

DS

tpu

Chip Select Active to Power Up
(7C293A CSI Only)

tpD

Chip Select Inactive to Power Down
(7C293A CSI Only)

0

0

0

27

0

32

DS

45

35

DS

AC Test Loads and Waveforms
R12500

R12500

5Vo-...............~~~

5VO----~~~

OUTPUT 0-.........._

OUTPUTo---_---..

R2

'NCLUD'NGI 30 pF
JIG AND

1670

INCLUDING
JIG AND

SCOPE

I

90%

::: __...:I[A9O%

.........."'"

><5ns::l:l ~

R2

6 pF

]

r:: ~5ns
10%

0120-5

1670

Figure 2. InputPulses

SCOPE
0120-4

Figure Ib

Figure la
Equivalent to:

THEVENIN EQUIVALENT
10DO

---·y...,"'....................o 2.D V

OUTPUT O-.....

0120-6

-

VCC

SUPPLY
CURRENT

AO-A1D
ADDRESS

tpd

I50%

-

tpu

50%

~

~tAA

- tHZCS '

XX

NOTE 8
NOTE 8

- tACS

~

(
0120-7

Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, output loading of the specified IorlIOH and
loads shown in Figures 1a, lb.

S. tHZCS is tested with load shown in Figure lb. Transition is measured
at steady state High level - 500 mV or steady state Low level + 500
mV on the output from the I.SV level on the input.
9. tHZCS2 and tAcs2 refer to 7C293A CSI only.

3·140

&Ii
.

CY7C191A
CY7C191AlCY7C193A

~==========================================================;:;

Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE

VI.

11
c

1.2

N

:::;

":IEa:

1.0

~

0

Z

0.8

V

0.6
4.0

/

/

5.0

8.0

5.5

:::;

"a:

1.4

!i

30.0

...oS

50

26.0

III

a:
a:

40

III

30

"
- "
:::>

51
!5...

0.8

...:::>
0

0.6

-55

25

126

AMBIENT TEMPERATURE (·C)

20

10

o
o

1.0

" '"
2.0

OUTPUT SINK CURRENT
VI. OUTPUT VOLTAGE

...z~
III

a:

:::>

,.u

z

75

!5...

50

0

26

;;

...:::>

/

100

o

'/

"
Vee -5.0V
TA = 26·C

J
1.0

2.0

3.0

16.0

/

""

4.0

5.0
0.0

V

/
TA • 25·C
vee -4.SV

V

o

200

400

600

CAPACITANCE (pF)

Vee

As

As

As

At

Ao

A,o

A3

Vpp ICS,I

Az

vrv ICS,I

A,

iIlm

AD

D7

ICS31

D.

/

V

0.0

~

/

:!l10.0

A7

.,..~

125

a:

20.0

!:i

3.0

D,

D5

Dz

D,

GND

D3

4.0

0120-10

Figure 3. Programming Pinout

OUTPUT VOLTAGE (V)
0120-9

3-141

6.0

5.5

..--

OUTPUT VOLTAGE (V)

175
150

!

.

~

U

a:

5.0

4.6

I

i 26·C

TYPICAL ACCESS TIME CHANGE
VI. OUTPUT LOADING

60

:::>
u

-

0.4
4.0

II

~

SUPPLY VOLTAGE (V)

Z

:Ii

0.6

OUTPUT SOURCE CURRENT
VI. VOLTAGE
~

1.0

Ii

'"

AMBIENT TEMPERATURE (·C)

III

N

0.8

~ ............

TA

NORMALIZED ACCESS TIME
TEMPERATURE

III

I
OJO~=----~26~----~I26

VI.

~c

1.0

i

TA·26·C
'-MAX.
4.5

:IE
;::

~
:::;

1.6

1.2

1.2

c

SUPPLY VOLTAGE (V)

!...
12
III

VI.

1.2r------,r-------,

III

1.4

III

NORMAUZED ACCESS TIME
SUPPLY VOLTAGE

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VI.

1.6

800

1000

r;n
...

CY7C291A
CY7C292A/CY7C2?~A

~&NDUCfOR =================================

Programming Algorithm

0120-8

The CY7C291A, CY7C292A and CY7C293A programming algorithm allows significantly faster programming than the "worst case"· specification of 10
ms.
Typical programming time for a byte is less than 2.5 ms. The use of EPROM cells allows factory testing of programmed cells, measurement of data
retention and erasure to ensure reliable data retention and functional performance. A flowchart of the algorithm is shown in Figure 4.
The algorithm utilizes two different pulse types: initial and o.verprogram. The duration of the PGM pulse (tpp) is 0.1 ms which will then be followed by a
longer overprogram pulse of 24 (0.1) (X) ms. X is an iteration counter and is equal to the NUMBER of the initial 0.1 ms pulsee applied before verification
occurs. Up to four 0.1 ms pulses are provided before the overprogram pulse is applied.
The entire sequence of program pulses and byte verification is performed at Veep = 5.0V. When all bytes have been programmed all bytes should be
compared (Read mode) to original data with Vee = 5.0V.

Figure 4. Programming Flowchart

3-142

5n

- - . CYPRESS

~

SEMICONDUCTOR

CY7C291A

CY7C292A/CY7C293A

==============================~~==~~~
to sunlight or fluorescent lighting for extended periods of
time.

Programming Information
The 7C291A, 7C292A and 7C293A 2K x 8 CMOS
PROMs are implemented with a single ended EPROM
memory cell. The PROMs are delivered in an erased
state, containing "Os". To verify that a PROM is unprogrammed, use the verify mode provided in Table 3. The
locations 0 thru 2047 should be addressed and read.

The recommended dose of ultraviolet light for erasure is a
wavelength of2537 Angstroms for a minimum dose (UV
intensity X exposure time) of25 Wsec/cm 2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 30-35 minutes.
These PROMs need to be within 1 inch of the lamp during
erasure. Permanent damage may result if the PROM is
exposed to high intensity UV light for an extended period
of time. 7258W X sec/cm2 is the recommended maximum
dosage.

Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to
erase these PROMs. For this reason, an opaque label
should be placed over the window if the PROM is exposed

DC Programming Parameters TA

=

25°C
Table 1

Parameter

Description

Min.

Max.

Units

Vpp

Programming Voltage[l]

12.0

13.0

V

Vecp

Supply Voltage

4.75

5.25

VIHP

Input HIGH Voltage

3.0

VILP

Input LOW Voltage

VOH

Output HIGH Voltage[2]

VOL
Ipp

V
V

0.4

V

Output LOW Voltage[2]

0.4

V

Programming Supply Current

50

rnA

AC Programming Parameters TA

=

2.4

V

25°C
Table 2

Parameter

Description

Min.

Max.

Units

tpp

Programming Pulse Width[3]

100

10,000

fl-s

tAS

Address Setup Time

1.0

fl-s

tos

Data Setup Time

1.0

fl-s

tAH

Address Hold Time

1.0

fl-s

tOH

Data Hold Time

1.0

fl-s

tR, tF

Vpp Rise and Fall Timd3]

1.0

fl-s

tvo

Delay to Verify

1.0

fl-s

2.0

tvp

Verify Pulse Width

tov

Verify Data Valid

1.0

fl-s

toz

Verify to High Z

1.0

fl-s

Notes.
J. Veep must be applied prior to V pp.

fl-s

3. Measured 10% and 90% points.

2. During verify operation.

3-143

II

CY7C291A

~crPiIESS
CY7C292A/CY7C293A
~~OO~aoR================================================================
.

Mode Selection
Table 3
Pin Function
Read or Output Disable

Mode

Other

CS3

CS2

CSl

PGM

VFY

Vpp
(20)

Outputs
(9-11,13-17)

(18)

(19)

VIH

VIH

VIL

Data Out

Output Disable[4)

X

X

HighZ

Output Disable[4)

X

VIL

VIH
X

Output Disable[4)

VIL

X

X

HighZ
Data In
Data Out

Pin Number
Read

HighZ

Program

VILP

VIHP

Vpp

Program Verify

VIHP

VILP

Vpp

HighZ
Data In

Program Inhibit

VIHP

VIHP

Vpp

Intelligent Program

VILP

VIHP

Vpp

Notes:
4. X = Don't care but not to exceed Vcc

+ 5%.

5. During programming and verification, all unspecified pins to be at
VllP·

Programming Sequence 2K x 8
location is programmed with a single pulse. Any location
that fails to verify causes the device to be rejected.

Power the device for normal read mode operation with pin
18, 19 and 20 at VIH. Per Figure 5 take pin 20 to Vpp. The
device is now in the program inhibit mode of operation
with the output lines in a high impedance state; see Table 3.
Again per Figure 5 address, program, and verify one byte
of data. Repeat this for each location to be programmed.
If the brute force programming method is used, the pulse
width of the program pulse should be 10 ms, and each

If the intelligent programming technique is used, the program pulse width should be 200 p.s. Each location is ultimately programmed and verified until it verifies correctly
up to and including 10 times. When the location verifies,
one additional programming pulse should be applied of duration 4 x the surnof the previous programming pulses
before advancing to the next address to repeat the process.
PROGRAM

~rn~

VERIFV

PROGRAM

j-

,

ADDRESS STABLE

ADDRESS
VILP - - -

t+--tAS-

:cDS ....

VIHP---

DATA

.-. tR_

VILP - - -

\

_tAS~

Vpp---

PROGRAMMIN
VOLTAGE (PING201

DATA IN

-

-

tov

J.

\

DATA OUT

~

_ __

r

r

5

,r

5

"

~~-

toH

V

~r

VIHP---

VILP - - -

VIHP---

I'GM
VllP - - -

\

~

-tpp-..,,...
'---' j----tvo

tvp--

VIHP---

r

-r
VILP - - -

0120-11

Figure 5. Programming Waveforms

3-144

(;n
.

~7C291A
CY7C292A/~7C293A

~UaoR================================================================

Ordering Information
Speed

Icc

(ns)

(mA)

25

120

30

35

120

60

90

120

Ordering
Code

Package
Type

Operating
Range

CY7C291A-25PC

P13

Commercial

CY7C291A-25WC

W14

Speed Icc
(ns) (mA)
50

60

Ordering
Code

Package
Type

Operating
Range

CY7C291AL-50PC

P13

Commercial

CY7C291AL-50WC

W14

CY7C292A-25PC

PII

CY7C292AL-50PC

PII

CY7C292A-25DC

D12

CY7C293AL-50PC

P13

CY7C293A-25PC

P13

CY7C293AL-50WC

W14

CY7C291 A-50PC

P13

CY7C291 A-50DC

D14

W14

CY7C291 A-50WC

W14

L64

CY7C291 A-50LC

L64

CY7C291A-3OQMB

Q64

CY7C292A-50PC

PII

CY7C292A-30DMB

012

CY7C292A-50DC

012

CY7C293A-30DMB

D14

CY7C293A-50PC

P13

CY7C293A-30WMB

W14

CY7C293A-50DC

014

CY7C293A-30LMB

L64

CY7C293A-50WC

W14

CY7C293A-3OQMB

Q64

CY7C293A-50LC

L64

CY7C291A-50DMB

014
W14

CY7C293A-25WC

W14

CY7C291A-30DMB

014

CY7C291A-30WMB
CY7C291A-30LMB

90
Military

CY7C291AL-35PC

P13

Commercial

120

CY7C291AL-35WC

W14

CY7C291A-50WMB

CY7C292AL-35PC

pII

CY7C291A-50LMB

L64

CY7C293AL-35PC

P13

CY7C291A-5OQMB

Q64

CY7C293AL-35WC

W14

CY7C291A-35PC

P13

Commercial

CY7C292A-50DMB

D12

CY7C293A-50DMB

014
W14

CY7C291A-35DC

D14

CY7C293A-50WMB

CY7C291A-35WC

W14

CY7C293A-50LMB

L64

CY7C291A-35LC

L64

CY7C293A-50QMB

Q64

CY7C292A-35PC

PII

CY7C292A-35DC

D12

CY7C293A-35PC

P13

CY7C293A-35DC

D14

CY7C293A-35WC

W14

CY7C293A-35LC

L64

CY7C291A-35DMB

D14

CY7C291A-35WMB

W14

CY7C291A-35LMB

L64

CY7C291A-35QMB

Q64

CY7C292A-35DMB

012

CY7C293A-35DMB

014

CY7C293A-35WMB

W14

CY7C293A-35LMB

L64

CY7C293A-35QMB

Q64

Military

3-145

II
Commercial

Military

"
fin

CY7C291A
CY7C292A/CY7C293A

• CYPRESS

~oo~u~==========================================================~

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

Vrn

1,2,3

VIL

1,2,3

Irx

1,2,3

IOZ

1,2,3

Icc
ISBI2l

1,2,3
1,2,3

Switching Characteristics
Parameters

" tAA
tACSl lll
tAcs2 12l

Subgroups

7,8,9,10,11
7,8,9,10,11
7,8,9,10,11

Notes:
1. 7C29lA and 7C292A only.
2. 7C293A only.

Document IF: 38-OOO75-B

3-146

~
PROM Programming Information
~~~DUcroR============~============~====================================~
Introduction

with the control gate. The state of the floating gate,
charged or uncharged, is permanent because the gate is
isolated in an extremely pure oxide. The charge may be
removed if the device is irradiated with ultraviolet energy
in the form of light. This ultraviolet light allows the electrons on the gate to recombine and discharge the gate. This
process is repeatable and therefore can be used during the
processing of the device repeatedly if necessary to assure
programming function and performance.

PROMs or Programmable Read Only Memories have existed since the early 1970's and continue to provide the
highest speed non-volatile form of semiconductor memory
available. Until the introduction of CMOS PROMs from
Cypress, all PROMs were produced in bipolar technology,
because bipolar technology provided the highest possible
performance at an acceptable cost. level. All bipolar
PROMs use a fuse for the programming element. The fuses
are in tact when the product is delivered to the user; and
may be programmed or written once with a pattern and
used or read infinitely. The fuses are literally blown using a
high current supplied by a Programming System. Since the
fuses may only be blown or programmed once, they may
not be programmed during test. In addition, since they
may not be programmed until the user determines the pattern, they may not be completely tested prior to shipment
from the supplier. This inability to completely test, results
in less than 100% yield during programming and use by
the customer for two reasons. First, some percentage of the
product fails to program. These devices fall out during the
programming operation, and although a nuisance are easily
identified. Additional yield is lost because the device fails
to perform even though it programs correctly. This failure
is normally due to the device being too slow. This is a more
subtle failure, and can only be found by 100% post program AC testing, or even worse by trouble shooting an
assembled board or system.
Cypress CMOS PROMs use an EPROM programming
mechanism. This technology has been in use in MOS technologies since the early 19708. However, as with most
MOS technologies the emphasis has been on density, not
performance. CMOS at Cypress is as fast as or faster than
Bipolar and coupled with EPROM, becomes a viable. alternative to bipolar PROMs from a performance pomt-ofview. In the arena of programming, EPROM has some
significant advantages over fuse technology. EPROM cells
are programmed by injecting charge on an isolated gate
which permanently turns off the transistor. This mechanism can be reversed by irradiating the device with ultraviolet light. The fact that programming can be erased, totally
changes the testing and programming situation and philosophy. All cells can be programmed during the manufacturing process and then erased prior to packaging and subsequent shipment. While these cells are programmed, the
performance of each cell in the memory can be tes~ allowing the shipment of devices that program every time,
and will perform as specified when programmed. In addition when these devices are supplied in a windowed package they can be programmed and erased indefmitely providing the designer a RE-PROGRAMMABLE PROM for
development.

Two Transistor Cells
In order to provide an EPROM cell that is as fast as the
fuse technology employed in bipolar processes, Cypress
uses a two transistor EPROM cell. One transistor is optimized for reliable programming, and one transistor is optimized for high speed. The floating gates are connected
such that charge injected on the floating gate of the programming transistor is conducted to the read transistor,
biasing it off.

Differential Memory Cells
In the 4K (CY7C225); 8K (CY7C235, CY7C281,
CY7C282); and 16K (CY7C245, CY7C291, CY7C292)
CMOS PROMs, Cypress employs a differential memory
cell and sense amplifier technique. Higher density devices
such as the 7C261, 7C263, 7C264 or 7C269 64K PROMs
employ a single ended Cell and sense amplifier technique
similar to the approach used in more conventional
EPROMs.
In a conventional high density EPROM a single EPROM
transistor is used to switch the input to one side of a differential sense amplifier. The other side of the sense amplifier
is biased at an intermediate level with a dummy cell. An
unprogrammed EPROM transistor will conduct and drive
the sense amplifier to a logic "0". A programmed EPROM
transistor will not conduct, and consequently drives the
sense amplifier to a logic" 1". A conventional EPROM cell
therefore is delivered with a specific state "0" or "1" in it
depending on the number of inversions after the s~nse am~
plifier and can always be programmed to the OppoSite state.
Access time in this conventional approach is heavily dependent on the time the selected EPROM transistor takes to
move the input of the sense amplifier from a quiescent condition to the threshold that the dummy cell is biasing the
second input to the sense amplifier. This bias is several
volts, and requires a significant delay before· the sense amplifier begins to react.
Cypress PROMs employ a true differential cell approach,
with EPROM cells attached to both inputs of the sense
amplifier. As indicated above, the read transistor which is
optimized for speed is actually the transistor attached to
the sense amplifier. In the erased state, both EPROM transistors conduct when selected eccentrically biasing the input of the sense amplifier at the same level. If the inputs
were at identical levels, the output of the sense amplifier
would be in a mestastable condition or, neither a "1" nor
"0". In actual practice the natural bias and high gain of the
sense amplifier combine to cause the output to favor one or
the other stable conditions. The difference between the two
conditions is however only a few millivolts and the memory ceIl should be considered to contain neither a "1" nor a
"0". As a result of this design approach, the memory cell
must be programmed to either a "I" or a "0" depending on
the desired condition and the conventional BLANK

Programmable Technology
EPROM Process Technology
EPROM technology employs a floating or isolated gate
between the normal control gate and the source/drain region of a transistor. This gate may be charged with electrons during the programming operation and when
charged with electrons, the transistor is permanently
turned off. When uncharged (the transistor is unprogrammed) the device may be turned on and off normally
3-147

II

&r~c5toocrOR

====P==R==.==O==M===P==r==o;;;;::gr;;;a==m=m==i==D;;;;;g;;;;I==D==fi==o==r==m=a==t==io==D=(Co==n==tin;;;;;;;ued==)==

CHECK mechanism is invaliq. The benefit of the approach
however is that only a small differential signal from the cell
begins the sense amplifier switching and the access time of
the memory is extremely fast.

Single Ended Memory Cells
Although a more conventional· approach, single ended
memory cells and sensing techniques offer a superior tradeoff between die size and performance than the differential
cell for devices of64K densities and above. The Single
ended technique employed by Cypress uses a dummy cell
for the reference voltage thus providing a reference that
tracks the programmed cell in process related parameters,
power supply and temperature induced variations. The
Memory cell used is a second generation two transistor cell
derived from earlier work at the 16K density level. It has
an optimized READ transistor that is matched to the sense
amplifier, and a second transistor optimized for programming. The floating gates of the two transistors that make
up a memory cell are connected electrically so that the
charge programmed onto one device controls the threshold
of the second transistor.
Unlike the differential memory approach, the erased single
ended device contains all "O"s and on the the ones are
programmed. Therefore a "I" on the data pins during programming causes a "I" to be programmed into the addressed location.

Programming Algorithm
Byte Addressing and Programming
All Cypress CMOS PROMs are addressed and programmedon a byte basis unlike the bipolar products that
they replace. The address lines used to access the memory
in a read mode are the same for programming, and the
address map is identical. The information to be programmed into each byte is presented on the data out pins
during the programming operation and the data is read
from these same pins for verification that the byte has been
programmed.

Blank Check for Differential Cells
Since a differential cell contains neither a "1" nor a "0"
before it is programmed, the conventional BLANK
CHECK is not valid. For this reason, all Cypress CMOS
PROMs contain a special BLANK CHECK mode of operation. Blank check is performed by separately examining
the "0" and "1" sides of the differential memory cell to
determine whether either side has been independently programmed. This is accomplished in two passes one comparing the "0" side of the differential cell against a reference
voltage applied to the opposite side of the sense amplifier
and then repeating this operation for the. "1"s side of the
cell. The modes are called BLANK CHECK ONES, and
BLANK CHECK ZEROS. These modes are entered by
the application of a supervoltage to the device.

Blank Check for Single Ended Cells
Single ended cells BLANK CHECK in a conventional
manner. An erased device contains all "O"s and a programmed call will contain a "1". Cypress PROMs that use
the single ended approach provide a specific mode to perform the BLANK CHECK which also provides the verify

function. This makes the need to switch high voltages unnecessary during the program verify operation. See specific
data sheets for details.

Programming the Data Array
Programming is accomplished by applying a supervoltage
to one pin of the device causing it to enter the programming mode of operation. This also provides the programming voltage for the ceUs to be programmed. In this mode
of operation, the a4dress lines of the device are used to
address each location to be programmed, and the data is
presented on the pins normally used for reading the contents of the device. Each device has a READ and a
WRITE phi in the programming mode. These are active
low signals and cause the data on the output pins to be
written into the addressed memory location in the case of
the W~ITE signal or read out of the device in the case of
the READ signal. When both the READ.and WRITE signals are high, the outputs are disabled and in a high impedance state. Programming therefore is accomplished by
placing data on the output pins, and writing it into the
addressed location with the WRITE signal. Verification of
data is accompiished by reading the information on the
output pins while the READ signal is active.
The timing for actual programming is supplied in the
unique programming specification for each device.

Special Features
Depending on the specific CMOS PROM in question, additional features that require programming may be available to the designer. Two ofthese features are a Programmable INITIAL BYTE and Programmable SYNCHRONOUS/ASYNCHRONOUS ENABLE available in some
of the registered devices. Like programming the array,
these features make use of EPROM cells and are programmed in a similar manner, using supervoltages. The
specific timing and programming requirements are specified in the data sheet of the device employing the feature.

Programming Support
Programming support for Cypress CMOS PROMs is available from a number of programmer manufacturers, some
of which are listed below.
Data I/O Corporation
10525 Willows Rd. N.B.
P.O. Box 97046
Redmond, WA
98073-9746
(206) 881-6444
Data I/O 29B Unipak II
Cypress
Generic
Part Number
Part Number
CY7C225
CY7C235
CY7C245
CY7C261/3/4
CY7C281/2
CY7C291/2

27825
27835
27845A
27849
278281/181
278291/191

Faniily Code
and Pinout
FO
FO
FO

EF

BB
BB

B6
B5
BO

31
B4
AF

Revision
V12
V09
V09
Vll
V09
V09

~

PROM Programming Information (Continued)

~~~~D~R~~~~~~~~~~~~~~~~~~~~~~~~~~==~~==~~===
Stag Microsystems
1600 Wyatt Dr.
Santa Clara, CA 95054

Cypress Semiconductor, Inc.
3901 North First St.
San Jose, CA 95134

(408) 988-1118

(408) 943-2600

Stag PPZ Zm2000
Cypress
Part Number

Generic
Part Number

CY7C225
CY7C235
CY7C245
CY7C281/2
CY7C291/2

27S25
27S35
27S45A
27S281/181
27S291/191

Cypress CY3000 QuickPro Rev. PROM 2.10
Family Code
and Pinout

Revision

Menu
Driven

Rev 21
Rev 21
Rev 24
Rev 21
Rev 21

Cypress
Part Number
CY7C225
CY7C235
CY7C245
CY7C261/3/4
CY7C268
CY7C269
CY7C281/2
CY7C291/2

3-149

Generic
Part Number

Family Code
and Pinout

II
Menu
Driven

Menu
Driven

PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY

•f.
•
•
•
[II

BRIDGEMOS

III

QUICKPRO

"~I

APPLICATION BRIEFS

m
m
m

PACKAGES

IF'

PLDTOOLKIT
QUALITY AND
RELIABILITY

~
Section Contents
~~~~=============================================================
EPLDs (Eraseable Programmable Logic Devices)

Page Number

Introduction to EPLDs ................................................................................. .4-1

Device Number

Description

PAL® C 20 Series
16L8, 16R8, 16R6, 16R4 Reprogrammable CMOS PAL® Device ................... .4-7
PLD C 18G8
CMOS Generic 20 Pin Programmable Logic Device ............................. .4-26
PLD C 20G lOB
CMOS Generic 24 Pin Reprogrammable PLD .................................. .4-33
PLD C 20G 10
CMOS Generic 24 Pin Reprogrammable PLD .................................. .4-33
PLD C 20RAIO
Reprogrammable Asynchronous CMOS Programmable Logic Device ............... .4-52
PAL C 22VI0B
Reprogrammable CMOS PAL Device ......................................... .4-61
PAL C 22VIO
Reprogrammable CMOS PAL Device ......................................... .4-61
CY7C330
Synchronous State Machine ................................................. .4-80
CY7C331
Asynchronous Registered EPLD ............................................. .4-91
CY7C332
Combinatorial Registered EPLD ............................................. 4-103
CY7C340 EPLD Family
Multiple Array Matrix High Density EPLDs ................................... 4-112
CY7C361
Ultra High Speed State Machine ............................................. 4-123
PLD Programming Information ........... '.' ............................................................ 4-129

~~========In=t=ro=d=u=c=ti=on==to==C=~=O==S=E=P=L=D==s=======
Cypress EPLD Family Features
ability. The flexibility afforded by these EPLDs allows the
designer to quickly and effectively implement a number of
logic functions ranging from random logic gate replacement to complex combinatorial logic functions.
The EPLD family implements the familiar "sum of products" logic by using a programmable AND array whose
output terms feed a fixed OR array. The sum of these can
be expressed in a Boolean transfer function and is limited
only by the number of product terms available in the
AND-OR array. A variety of different sizes and architectures are available. This allows for more efficient logic optimization by matching input, output and product terms to
the desired application.

Cypress Semiconductor's EPLD family offers the user the
next generation in Erasable Programmable Logic Devices
(EPLD) based on our high performance 0.8,... CMOS process. These devices offer the user the power saving of a
CMOS-based process, with delay times equivalent to those
previously found only in bipolar devices. No fuses are used
in Cypress' EPLD family, rather all devices are based on
an EPROM cell to facilitate programming. By using an
EPROM cell instead of fuses, programming yields of 100%
can be expected since all devices are functionally tested and
erased prior to packaging. Therefore, no programming
yield loss can be expected by the user.
The EPROM cell used by Cypress serves the same purpose
as the fuse used in most bipolar PLD devices. Before programming, the AND gates or Product Terms are connected via the EPROM cells to both the true and complement
inputs. When the EPROM cell is programmed, the inputs
from a gate or Product Term are disconnected. Programming alters the transistor threshold of each cell so that no
conduction can occur, which is equivalent to disconnecting
the input from the gate or Product Terms. This is similar
to "blowing" the fuses of a bipolar device which disconnects the input gate from the Product Term. Selective programming of each of these EPROM cells enables the specific logic function to be implemented by the user.
The programmability of Cypress' EPLDs allows the users
to customize every device in a number of ways to implement their unique logic requirements. Using EPLDs in
place of SSI or MSI components results in more effective
utilization of boardspace, reduced cost and increased reli-

1=0-,·,·"

EPLD Notation
To reduce confusion and to have an orderly way of representing the complex logic networks, logic diagrams are
provided for the various part types. In order to be useful,
Cypress logic diagrams employ a common logic convention
that is easy to use. Figure 1 shows the adopted convention.
In Figure 1, an "x" represents an unprogrammed EPROM
cell that is used to perform the logical AND operation
upon the input terms. The convention adopted does not
imply that the input terms are connected on the common
line that is indicated. A further extension of this convention is shown in Figure 2 which shows the implementation
of a simple transfer function. The normal logic representation of the transfer function logic convention is shown in
Figure 3.

-m-o-,. ,
0024-1

Figure 1

0024-2

Figure 2

0024-3

Figure 3

4-1

II
•

r;r~ ==~In~t~r~od=u~c~t=io=n~t=o;;;;;;C;;;;M~O~S;;;;;;E;;;;;;P;;;;;;L=D;;;;;;S;;;;(Co;;;;;;n;;;;;;tin;;;;;;ued::;;;)====
with the register may still be used as a device input. The
proprietary CY7C330 Reprogrammable Synchronous State
Machine macrocell illustrates, in Figure 6, the use of buried registers with provision for saving the I/O pin for use
as an input. If the feedback path is selected by the feedback
multiplexer, the Q of the register is fed back to the array as
an input. The I/O pin can still be routed to the array as an
external input by use of a special multiplexer shown in
Figure 7 provided for that purpose for each of the six macrocell pairs. A special configuration bit, <:3, selects th~ input register output from one of the I/O pms of the parr of
macrocell I/O pins which is to be fed to the array as an
external input. By proper placement of buried register configured I/O macrocells adjacent to I/O macrocells used as
normal registered outputs without feedback, maximum use
of the buried macrocell I/O pins for inputs can be
achieved. The CY7C330 also contains four dedicated buried or hidden registers with no external output, illustrated
in Figure 8, which are used as additional state register resources for creation of high performance state machines.

PLD Circuit Configurations
Cypress EPtDs have several different output configurations that cover a wide spectrum of applications. The available· output configurations offer the user the benefits of
both lower package counts and reduced costs when used.
This approach allows the designer to select a PLD that best
fits the needs of his application. An example of some of the
configurations that are available are listed below.

Programmable I/O
Figure 4 illustrates the programmable I/O offered in t~e
Cypress EPLD family which allows product terms to directly control the outputs of the device. One product term
is used to directly control the three-state output buffer,
which then gates the summation of the remaining terms to
the output pin. The output of this slliniliation can be fed
back into the PLD as an input to the array. This programmable I/O feature allows the PLD to drive the output pin
when the three-state output is enabled or, the I/O pin can
be used as an input to the array when the three-state output
is disabled.

Asynchronous Register Control
Cypress also offers EPLDs which may be used in asynchronous systems in which register clock, set and reset are controlled by the outputs of the product term array. The clock
signal is created by the processing of external inputs
and/or internal feedback by the logic of the product term
array which is then routed to the register clock. The register set and reset are similarly controlled by product term
outputs and can be triggered at any time independent of
the register clock in response to external and/or feedback
inputs processed by the logic array. The proprietary
CY7C331 Asynchronous Registered EPLD, for which the
I/O macrocell is illustrated in Figure 9, is an example of
such a device. The register clock, set and reset functions of
the CY7C331 are all controlled by product terms and enable their respective functions dependent only on input signal timing and combinatorial delay through the device logic array.

Registered Outputs with Feedback
Figure 5 illustrates the registered output offered on a number of the Cypress EPLDs which allow any of these circuits
to function as a state sequencer. The summation of the
product terms is stored in the D-type output flip-flop on
the rising edge of the system clock. The Q output of the
flip-flop can then be gated to the output pin by enabling the
three-state output buffer. The output of the flip-flop can
also be fed back into the array as an input term. The output
feedback feature allows the PLD to remember and then
alter its function based upon that state. This circuit can be
used to execute such functions as counting, skip, shift and
branch.

Programmable Macro Cell
The Programmable Macro Cell, illustrated in Figure 10,
provides the capability of defining the architecture of each
output individually. Each of the potential outputs may be
specified to be "REGISTERED" or "COMBINATORIAL". Polarity of each output may also be individually selected allowing complete flexibility of output configuration.
Further configurability is provided through "ARRAY"
configurable "OUTPUT ENABLE" for each potential output. This feature allows the outputs to be reconfigure~ ~s
inputs on an individual basis or alternately used as a bIdIrectional I/O controlled by the programmable array.

Input Register Cell
Other Cypress EPLDs provide input register cells which
allow capture for processing of short duration inputs which
would not otherwise be present at the inputs for sufficient
time to allow the device to respond. Both the proprietary
CY7C330 Reprogrammable Synchronous State Machine
and the proprietary CY7C332 ~mbinatorial E~LD.pro­
vide these input register cells which are shown m Figure
11. The clock for the input register may be provided from
one of two external clock input pins selectable by a configuration bit, C4, dedicated for this purpose for each input
register. This choice of input register clock allows signals
to be captured and processed from two independent system
sources each controlled by its own independent clock.
These input register cells are provided within I/O macrocells, as well as, for dedicated input pins.

Buried Register Feedback
A number of Cypress EPLDs provide registers which may
be "buried" or "hidden" to create registers for state machine implementation without sacrificing the use of th.e associated device pin. The device pin normally associated

4-2

~

Introduction to CMOS EPLDs (Continued)

~~~~~~~~~~~~~~~~~~~~~~~~~~==~~~==~~~~
I/o

NPUTS, fEEDBACK, AND

I~

'1111 111111111111111111111111111'

~J:r

0024-4

Figure 4. Programmable I/O
INPUTS fEEDBACK AND

I/o

,

CLOCK

)- il"Q1-

-t::

...

r_

III

~

~1
0024-5

Figure 5. Registered Outputs with Feedback

GLOBAL
SYNCHRONOUS SET

INPUT OR FEEDBACK TO LOGIC ARRAY

TO SHARED
MACRO CELL
INPUT MUX

GLOBAL STATE
REGISTER CLOCK
CLK(PIN 1)

Figure 6. CY7C330 I/O Macro Cell

4-3

INPUT
CLOCKS CK2 CK1
(PIN 3)(PIN 2)
0024-7

(;r~ ===I;;::;;:nt;;::;;:r;:;:;o;;::;;:d;;::;;:uc;;::;;:t;;::;;:io;;::;;:n=to=C;;::;;:M=O;;::;;:S=E;:;:;P;;::;;:L;:;:;D=s<;:;:;Co;:;:;ntin;:;:;"u;:;:;ed;:;:;)=;;;;;:;;:;;;;;;
FROM

LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
INPUT TO
LOGIC
ARRAY

I.

FEEDBACK
TO LOGIC
ARRAY
FROM
LOGIC
ARRAY

0024-8

Figure 7. CY7C330 1/0 Macro Cell Pair Shared Input MUX

GLOBAL SYNCHRONOUS SET

FEEDBACK TO LOGIC ARRAY
GLOBAL STATE
REGISTER CLOCK
CLK(PIN 1)

Figure 8. CY7C330 Hidden State Register Macro Cell

4-4

0024-9

~

Introduction to CMOS EPLDs (Continued)

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
PIN 14

----I

OE
MUX

SET PRODUCT TERM

S
D

Q

OUTPUT
REGISTER

CLOCK PRODUCT TERM

II

R

RESET PRODUCT TERM

:==~:1-

______

S

--1FEEDBACK
MUX
Q

D
INPUT
REGISTER

TO SHARED
INPUT MUX
0024-10

Figure 9. CY7C331 Registered Asynchronous Macrocell
CLOCK AR
I

OE
0

··
3

./

S#

..

~11

J

r-W-

,....

t.lACROCELL

~

h

I/O

SP
0024-6

Figure 10. Programmable Macro Cell

4-5

~

Introduction to CMOS EPLDs (Continued)

~r~~==============~~~
r..,......--+- INPUT TO
....,o---+- LOGIC
ARRAY
REGISTER INITIALIZED ON POWER
UP TO Q EQUAL TO LOGIC LOW

CK 1 CK2
(PIN 2) (PIN 3)
0024-11

Figure 11. CY7C330 Dedicated Input Cell

4-6

P AL® C 20 Series

CYPRESS
SEMICONDUCTOR

Reprogrammable CMOS
PAL® C 16L8, 16R8, 16R6, 16R4

Features
• High reliability
- Proven EPROM technology
- > IS00V input protection
from electrostatic discharge
- 100% AC/DC tested
- 10% power supply tolerances
- High noise immunity
- Security feature prevents
pattern duplication
- 100% programming and
functional testing

• CMOS EPROM technology for
reprogrammability
• High performance at quarter
power
-tpn= 25ns
-ts=20ns
-teo = ISns
-Icc=4SmA
• High performance at military
temperature
-tpn=20ns
-ts = 20ns
-teo = 15ns
-ICC = 70mA

gram custom logic functions serving
unique requirements.
PALs are offered in 20-pin plastic and
ceramic DIP, Plastic SOJ, and ceramic
LCC packages. The ceramic package
can be equipped with an erasure window; when exposed to UV light, the
PAL is erased and can then be reprogrammed.
Before programming, AND gates or
PRODUCT TERMS are connected via
EPROM cells to both TRUE and
COMPLEMENT inputs. Programming an EPROM cell disconnects an
INPUT TERM from a PRODUCT
TERM. Selective programming of
these cells allows a specific logic function to be implemented in a PAL C device. PAL C devices are supplied in
four functional configurations, desig-

Functional Description
Cypress PAL C Series 20 devices are
high speed electrically programmable
and UV erasable logic devices produced in a proprietary "N" well CMOS
EPROM process. These devices utilize
the sum of products (AND-OR) structure providing users the ability to pro-

• Commercial and military
temperature range

Logic Symbols and DIP and SOJ Pinouts
16R8

16R6

16R4

16L8
Vee

H>-,-IlU

0038-1

0038-2

0038-3

1/0

0038-4

LCCPinouts
0
Il.
00
__ 0
>

Il.~
_0
>_

3 2

0
0
0
0
0

4
5
6
7

0
0
0
0

_>0

~2019"
18
17
16
15
14

8

0

~

~>~~

-

I/O

I/O
I/o
I/O
I/O
I/O

0
0
0
0

\.. 9 10111213,J

-

-

!Il1~ 0 0
>

0038-5

-

!Il1~~ 0
>

-

0038-6

PAL'" is a registered trademark of Monolithic Memories Inc.
CYPRESS SEMICONDUCTOR is a trademark of Cypress Semicondnctor Corporation.

4-7

>

!Il1~~~
--

0038-7

(1)(I)

>

00
~

0038-8

n

IiII

Functional Description (Continued)
functionally tested during manufacturing. An ability to
preload the registers of registered devices during the testing
operation makes the testing easier and more efficient. The
PHANTOM ARRAY and PHANTOM operating mode
allow the device to be tested for functionality and performance after it has been packaged. Combining these inherent
and designed-in features, an extremely high degree of functionality, programmability and assured AC performance
are provided and testing becomes an easy task.
The REGISTER PRELOAD allows the user to initialize
the registered devices to a known state prior to testing the
device, significantly simplifying and shortening the testing
procedure.
The PHANTOM MODE of operation provides a completely separate operating mode where the functionality of
the device along with its AC performance may be ascertained. The user need not be encumbered by programmed
cells in the normal operating mode. This PHANTOM
MODE of operation allows additional input lines to be programmed to operate the PAL C device, exercising the device functionally and allowing AC performance measurements to be made. The PHANTOM MODE of operation
acknowledges only the INPUT TERMS shown shaded in
the functional block diagrams. Likewise, the normal
PHANTOM INPUT TERMS do not exist in the normal
mode of operation. During the final stages of manufacturing, some cells in the PHANTOM ARRAY are programmed for fmal AC and functional testing. These cells
remain programmed, and may be used at incoming inspection to verify both functional and AC performance.

nated 16R8, 16R6, 16R4 and 16L8. These eight devices
have potentially 16 inputs and 8 outputs configurable by
the user. Output configurations of 8 registers, 8 combinatorial, 6 registers and 2 combinatorial as well as 4 registers
and 4 combinatorial are provided by the four functional
variations of the product family. All combinatorial outputs
on the 16R6 and 16R4 as well as 6 of the combinatorial
outputs on the 16L8 may be used as optional inputs. All
registered outputs have the Qbar side of the register fed
back into the main array. The registers are automatically
initialized on power up to Q output LOW and Qoutput
HIGH. All unused inputs should be tied to ground.
All PAL C devices feature a SECURITY function which
provides the user protection for the implementation of proprietary logic. When invoked, the contents of the normal
array may no longer be accessed in the verify mode. Because EPROM technology is used as a storage mechanism,
the content of the array is not visible under a microscope.
The PAL C device also contains a PHANTOM ARRAY
used for functional and performance testing. The content
of this array is always accessible, even when security is
invoked.
Cypress PAL C products are produced in an advanced 1.2
micron UN" well CMOS EPROM technology. The use of
this proven EPROM technology is the basis for a superior
product with inherent advantages in reliability, testability,
programming and functional yield. EPROM technology
has the inherent advantage that all programmable elements
may be programmed, tested and erased during the manufacturing process. This also allows the device to be 100%

Commercial and Industrial Selection Guide
Generic
Part

Logic

Number
16L8
16R8
16R6

16R4

(8) 7-wide
AND-OR-Invert
(8) 8-wide AND-OR
(6) 8-wide AND-OR
(2) 7-wide
AND-OR-Invert
(4) 8-wide AND-OR
(4)7-wide
AND-OR-Invert

Output
Enable

Outputs

Dedicated
Dedicated

(6) Bidirectional
(2) Dedicated
Registered Inverting
Registered Inverting

Programmable

Bidirectional

Dedicated

Registered Inverting

Programmable

Bidirectional

Programmable

Icc(mA)

tpn (ns)

ts (ns)

teo (us)

L

COM'L/IND

-25

-35

-25

-35

-25

-35

45

70

25

35

-

-

-

-

45

70

-

-

20

30

15

25

45

70

25

35

20

30

15

25

45

70

25

35

20

30

15

25

Military Selection Guide
Generic
Part
Number
16L8
16R8
16R6

16R4

Logic

Output
Enable

(8) 7-wide
Programmable
AND-OR-Invert
(8) 8-wide AND-OR Dedicated
(6) 8-wide AND-OR Dedicated
(2) 7-wide
Programmable
AND-OR-Invert
(4) 8-wide AND-OR Dedicated
(4) 7-wide
Programmable
AND-OR-Invert

Outputs
(6) Bidirectional
(2) Dedicated
Registered Inverting
Registered Inverting
Bidirectional

Icc
(mA)

teo (us)

ts (us)

tpn (ns)

-20

-3~

-40

-20

-3~

-40

-20

-3D

-40

70

20

30

40

-

-

-

-

-

-

70

-

-

-

20

25

35

15

20

25

70

20

30

40

20

25

35

15

20

25

70

20

30

40

20

25

35

15

20

25

Registered Inverting
Bidirectional
4-8

~

PAL®C20Series

~r~~====================
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
UV Exposure ........................ 7258 Wsec/cm2
Storage Temperature ............... -65°C to + 150°C
Ambient Temperature with
Static Discharge Voltage ..................... > 1500V
(per MIL-STD-883 Method 3015)
Power Applied .................... - 55°C to + 125°C
Latchup Current .......................... > 200 rnA
Supply Voltage to Ground Potential
(Pin 20 to Pin 10) .................... -0.5V to + 7.0V
Operating Range
DC Voltage Applied to Outputs
Ambient
in High Z State ...................... -0.5Vto +7.0V
Range
Vee
Temperature
DC Input Voltage ................... -3.0V to +7.0V
O"Cto
+7SoC
Commercial
SV ±IO%
Output Current into Outputs (Low) ............. 24 rnA
Military[7)
- 55°C to + 125°C
5V ±1O%
DC Programming Voltage ...................... 14.0V
5V ±1O%
-4O"C to + 8S'C
Industrial

Electrical Characteristics Over Operating Range (Unless Otherwise Noted)[6]
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = Min.
VIN = VIH or VIL

VIH

Input HIGH Level
Input LOW Level

VIL
IJX
Vpp

Input Leakage Current
Programming Voltage

IOH = -3.2mA
IOH= -2mA

Commercial/Industrial
IOL = 24mA
Military
IOL = 12mA
Guaranteed Input Logic HIGHU) Voltage for all Inputs
Guaranteed Input Logical LOW[I] Voltage for all Inputs

Output Short Circuit
Current

Vee = Max., VOUT = 0.5V[2]

ICC

Power Supply Current

All Inputs = GND,
Vee = Max.,
lOUT = 0 mA[S]

Max. Units

2.4

V
0.4

V

0.8

V

-10

10

13.0

14.0

p.A
V

-300

mA

"L"
COM'L/IND

45
70

mA

MIL

70

mA

100

p.A

Vss:'; VIN :,; Vee
Ipp = 50 mA Max.

Ise

Ioz

Min.

CommerciallIndustrial
Military

2.0

V

-100

Output Leakage Current Vee = Max., VSS :,; VOUT :,; Vee

mA

Table 1
Parameter
tpxz(-)

Vx
1.5V

tpxz(+)

2.6V

Output Waveform-Measurement Level
VOH

VOL

tpZX(+)

Vthc
Vx

tpzx(-)

Vthc

tER(-)

1.5V

tER(+)

2.6V

tEA(+)

Vx

+~

VOL

+

Vx

4-9

+7't

a.~v ~I:

Vthc

Vthc

~~

VOH

Vx

tEA(-)

+7'1:'
+

7'~

+7't

+~t

Vx 0038-26
Vx
0038-27
VOH
0038-28

VOL

0038-29

Vx 0038-26
Vx
0038-27
VOH
0038-28

VOL

0038-29

II

~
PAL®C20Series
,...,~~~============================================================~
Capacitance [3]
Parameters

Description

CIN

Input Capacitance

Com

Output Capacitance

Test Conditions

Max.

= 25°C, f = 1 MHz
VIN = 0, Vee = 5.0V

7

TA

Units
pF

7

Switching Characteristics PAL C 20 Series Over Operating Range[4, 6, S]
Military

Commerclal/Industrial
Parameters

-25

Description

Min.

Units
-30
-40
Max. Min. Max. Min. Max. Min. Max.

-20

-35

Max.

Min.

tpD

Input or Feedback to Non-Registered
Output 16L8, 16R6, 16R4

25

35

tEA

Input to Output Enable 16L8, 16R6, 16R4

25

tER

Input to Output Disable 16L8, 16R6, 16R4

25

tpzx

Pin 11 to Output Enable 16R8, 16R6, 16R4

tpxz

20

30

40

ns

35

20

30

40

ns

35

20

30

40

ns

20

25

20

25

25

ns

Pin 11 to Output Disable 16R8, 16R6, 16R4

20

25

20

25

25

ns

teo

Clock to Output 16R8, 16R6, 16R4

15

25

15

20

25

ns

ts

Input or Feedback Setup Time 16R8,
16R6,16R4

30

20

20

25

35

ns

tH

Hold Time 16R8, 16R6, 16R4

0

0

0

0

0

ns

tp

Clock Period

35

55

35

45

60

ns

tw

Clock Width

15

20

12

20

25

Maximum Frequency
fMAX
Notes:
1. These are absolute values with respect to device ground and aU overshoots due to system or tester noise are included.
2. Not more than one output should he tested at a time. Duration of the
short circuit should not be more than one second. VOUT = 0.5V has
been chosen to avoid test problems cauaed by tester ground degradation.
3. Tested initially and after any design or process changes that may
affect these parameters.
4. Figure latest load used for all parameters except tEA, tER tpzx and
tpxz. Figure 1b test load used for tEA, tER. tpzx and tPXZ'

28.5

18

28.5

22

ns
16.5

MHz

5. ICC(AC) = (0.6 mA/MHz) x (Operating Frequency in MHz) +
ICC(DC). ICC(DC) is measured with an unprogrammed device.
6. See the last page of this specification for Group A subgroup testing
information.
7. TA is the ''instant on" case temperature.
S. The parameters tER and tpxz are measured as the delay from the
input disable logic threshold transition to VOH - 0.5V for an enabled
HIGH output or VOL + O.SV for an enabled LOW output. Please see
Table I for waveforms and measurement reference levels.

AC Test Loads and Waveforms
R1176n

R1175n

5V~

5V~

OUTPUT

I

60 F

P

OUTPUT

R2

-= 133!l

I

5pF

"::"

Figure la. Commercial

Equivalent to:
THEVENIN EQUIVALENT COMMERCIAL

R2

75!l

133!l

OUTPUT~2.16V-VIt1c

':'

0038-10

Figure lb. Commercial

0038-11

Equivalent to:
THEVENIN EQUIVALENT MILITARY
143 !l
OUTPUT~

2.11V-V_

0038-12

Figure lc. Military

0038-9

Figure ld. Military

3.0 V-----::Jo::-=~-......,:L
GND---""

0038-13

Figure 2
4-10

~
PAL®C20Series
,..,~~~========================================================~
Switching Waveforms
INPUTS. 110.
REGISTERED
FEEDBACK

t.

,

.I

~

41I1IXYll
I--tw- _ t w _

tH-I

1---.

1---..

1-

CP

tp_

I
REGISTERED
OUTPUTS:

COMBINtJ~:J:;:

j4- tco..

f.-tP'z~

lilYI-;

,\
111111

\

~t~Z)(

1111

\

\\n

I--tER~

tpo

»..,...H

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,)
...) ...

~tEA

(y,«.u{__
0038-14

Figure 3

Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to
erase the PAL C device. For this reason, an opaque label
should be placed over the window if the device is exposed
to sunlight or fluorescent lighting for extended periods of
time. In addition, high ambient light levels can create holeelectron pairs which may cause "blank" check failures or
"verify errors" when programming "windowed" parts.
This phenomenon can be avoided by use of an opaque label
over the window during programming in high ambient
light environments.

12 inclusive). In the unprogrammed state, all inputs are
connected to product terms. A "1" on a data line causes a
cell to be programmed, disconnecting an INPUT TERM
from a PRODUCT TERM. During verify, an unprogrammed cell causes a "I" to appear on the output, while a
programmed cell will appear as a "0". Table 4 describes
the operating modes of the device and the programming
waveforms are described in Figures 6 through 9. The actual
sequence required to program a cell is described in Figure 5
and applies for programming either standard or phantom
portions of the array. The security bit should be programmed using a single 10 ms pulse, and verified per Fig-

The recommended dose for erasure is ultraviolet light with
a wavelength of 2537 Angstroms for a minimum dose (UV
intensity x exposure time) of25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating, the exposure
would be approximately 35 minutes. The PAL C device
needs to be placed within 1 inch of the lamp during erasure. Permanent damage may result if the device is exposed
to high intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.

ure 9.
Vpp

Vccp

Ao

Programming
PAL C devices are programmed a BYTE at a time using a
voltage to transfer electrons to a floating gate. The array
programmed is addressed as memory of 256 bytes, using
address Tables 5 and 6. These addresses are supplied to the
device over Pins 2 through 9. The data to be programmed
is supplied on data inputs DO through D7 (Pins 19 through

A,

Do
D,

Az

Dz

A3

D3

A4

D.

At;

Il&

At;

08

A7

D7
PGM/OE

Vas

0038-'5

Figure 4. Programming Pin Configuration

DC Programming Parameters Ambient Temperature =

25°C
Table 2

Parameter
Vpp

Programming Voltage

Min.
13.0

Max.
14.0

Vccp

Supply Voltage During Programming

4.75

5.25

VIHP

Programming Input High Voltage

3.0

Description

VILP

Programming Input Low Voltage

VOH

Output High Voltage

VOL
Ipp

Output Low Voltage
Programming Supply Current

Notes

V
V
V

0.4
2.4

4-11

Units

V
V

I

0.4

V

I

50

rnA

II

AC Programming Parameters Ambient Temperature =

25°C

Table 3
Description

Min.

Max.

Units

Notes

tpp

Programming Pulse :Width

100

10,000

p.s

2

ts

Setup Time

1.0

p.s

tH

Hold Time

1.0

p.s

tr, tr

Vpp Rise and Fall Time

1.0

p.s

tvn

Delay to Verify

1.0

p.s

tvP

Verify Pulse Width

2.0

p.s

tDV

Verify to Data Valid

20.0

tDZ

Verify to High Z

Parameter

2

p.s

1.0

p.s

Table 4
Pin Name

Vpp

PGM/OE

Al

A2

A3

A4

AS

D7-DO

Pin Number

(1)

(11)

(3)

(4)

(5)

(6)

(7)

(12-19)

Notes

Operating Modes

X

X

X

X

X

X

X

Programmed Function

3,4

Program PAL

Vpp

Vpp

X

X

X

X

X

Data In

3,5

Program Inhibit

Vpp

VIHP

X

X

X

X

X

HighZ

Program Verify/Blank Check

Vpp

VILP

X

X

X

X

X

Data Out
Programmed Function

PAL

3,5
3,5,11

X

X

X

X

X

Vpp

X

Program Phantom PAL

Vpp

Vpp

X

X

X

X

Vpp

Data In

3, 7

Phantom Program Inhibit

Vpp

VIHP

X

X

X

X

Vpp

HighZ

3,7

Phantom Program Verify

Vpp

VILP

X

X

X

X

Vpp

Data Out

3, 7

Program Security Bit

Vpp

Vpp

Vpp

X

X

X

X

HighZ

3,8

X

X

X

HighZ

3

Vpp

X

X

Data In

3,10

Phantom PAL

Verify Security Bit
Register Preload
Notes:
I. During verify operation
2. Measured at 10% and 90% points
3. Vss

X

X

Note 9

Vpp

X

X

X

X

3,6

is used to select the phantom mode of operation and must be taken to
Vpp before selecting phantom program operation with Vpp on Pin I.
8. See Figure 8 for security programming sequence.
9. The state of Pin 3 indicates if the security function has been invoked
or not. If Pin 3 = VOL security is in effect, if Pin 3 = VOH, the data
is unsecured and may be directly accessed. '
10. For testing purposes, the output latch on the l6R8, l6R6 and 16R4
may be preloaded with data from the appropriate associated output

< X < Vccp

4. All "X" inputs operational per normal PAL function.
5. Address inputs occupy Pins 2 thru 9 inclusive, for both programming
and verification see programming address Tables 5 and 6.
6. All "X" inputs operational per normal PAL function except that they
operate on the function that occupies the phantom array.
7. Address inputs occupy Pins 2 thru 9 inclusive, for both programming
and verification see programming address Tables 5 and 6. Pin 7

line.

11. It is necessary to toggle Pin 11 

VIHP

VILP

VILP

VIHP

VIHP

VILP

23
24

VIHP

VIHP

VILP

VILP

VILP

7
8

VILP

VILP

VIHP

VIHP

VIHP

25

VIHP

VIHP

VILP

VILP

VIHP

VILP

VIHP

VILP

VILP

VILP

VIHP

VILP

VIHP

VILP

VILP

VIHP

VILP

VILP

VIHP

VIHP

VIHP

VILP

VIHP

VIHP

10

VILP

VIHP

VILP

VIHP

VILP

26
27
28

VIHP

9

VIHP

VIHP

VIHP

VILP

VILP

11

VILP

VIHP

VILP

VIHP

VIHP

29

VIHP

VIHP

VIHP

VILP

VIHP

12

VILP

VIHP

VIHP

VILP

VILP

VIHP

VIHP

VIHP

VILP

VILP

VIHP

VIHP

VILP

VIHP

30
31

VIHP

13

VIHP

VIHP

VIHP

VIHP

VIHP

14
15

VILP

VIHP

VIHP

VIHP

VILP

PO

VILP

VILP

Vpp

X

X

VILP

VIHP

VIHP

VIHP

VIHP

PI

VILP

VIHP

Vpp

X

X

16

VIHP

VILP

VILP

VILP

VILP

P2

VIHP

VILP

Vpp

X

X

17

VIHP

VILP

VILP

VILP

VIHP

P3

VIHP

VIHP

Vpp

X

X

4-13

START
Vccp=5.0V
Vpp·13.5V

1
ADDR 1ST
LOCATION

1
M=O

1
PROGRAM
ONE PULSE
OFO.2msec

1
M-M"

1
M - 10?
YES

1

NO

FAIL

VERIFY
ONE BYTE?

1

PASS

PROGRAM
ONE PULSE
OF4 (0.2)
(M)msec

1
I

M = 101
YES

1

1

VERIFY
BYTE

1
I

FAIL

PASS

NO

I
I

INCREMENT
ADDR

1
I

NO

LAST
ADDRESS?

1

YES

READ
ALL BYTES?
Vecp ~ 5.SV

I

FAIL

1

1

REJECT
DEVICE

1
I

PASS

PROGRAM
COMPLETE
GOOD
DEVICE
0038-16

Figure 5. Programming Flowchart
4-14

~
PAL®C20Series
~~~~================================================================
PROGRAM
V'HP---ADDRESS
V'LP - - - -

1

ADDRESS Ao THRU

PROGRAM
INHIBIT

As

I---tASI-tos-

V'HP----

T

DATA

DATA IN Do THRU 0.,

-l.

VILP - - - -

_L

tr
IIpp - - - -

IIpp

V'LP - - - -

lr-

tAH

-

-

K-

-toz

-

DATA OUT Do THRU D7
~tAH

I - f-toH

tAS_

Y

V'HP----

tov-

VERIFY

tl

\

,- - ,

...;

I--tl

-

\Ipp----

PROGRAM

-tpp-

VIHP----

PGM/OE
V'LP----

j

VERIFY
tvp

!--tvo-

0038-17

Figure 6. Programming Waveforms Normal Array
PROGRAM
INHIBIT

PROGRAM

VERIFY
tAH

V'HP- ADDRESS

)

V'LP- -

r'---

ADDRESS Ao THRU A2. Ag AND A7
_tAS_

Vpp---

-i

-tr

V'LP- - VpP- - Vpp
VIHP- - -

V'LP- - -

DATA IN Do THRU 0.,

lr- H--~AS-

V

-'"

tr1Ipp---

-

,.-tos-

V'HP- - DATA

-

-toy

~tAH

i+-- tOH

- -

.-~

I--toz

DATA OUT Do THRU D7

.1

\

tl

>-

I--tl

PROGRAM

VIHP- - -

PGM/OE
V'LP- - -

-tpp-

~

...
VERIFY

!----tvo-

J

tvp
0038-18

Figure 7. Program Waveforms Phantom Array

4-15

tf

Vpp ___ _

VIH.----

A,
VILP----

"""---VIH•. ___ _

Vpp
VILP - - - -

Vpp----

VIH. - - - -

PGM/ot
VIL. - - - - _ _ _ _ _ _ _...;,;;;;!!

0038~19

Figure 8. Activating Program Security
VIHP - - - -

DATA
VIL. - - - -

----------------------~

DATA OUT A, (NOTE 1)

""f;....-----~...;,;;f"
tDZ

Vpp - - - -

VIH.----

A2
VIL. - - - -

-------------------..;;;;jf""
tf

0038-20

Figure 9. Verify Program Security

4-16

~

PAL®C20Series

~~~~==========================================~~==========~
Functional Logic Diagram PAL C 16L8

INPUTS (0 - 311
1

....
....

[3

~

19

2

-

••
,.
'1

II

1.....

.....

18

....

J.

17

~~

18

........

.....

4

---

5

J.

R.TV

15

6

~

14

...

7

J.

.....

./

13

~

8

...... .1....
9

•

..,

12

11

,.,

0038-21

4-17

•

Functional Logic Diagram PAL C 16R4
INPUTS (0 - 3'1

, ....
.....

••

rt!

2
3

••

I
7

'9

2

-

....
""'" J

18

r--

11
17
II

ftJl~

17

4
~
~

=

9

I

g

!ia:

..

l-

~

5

I

~

J

fE-Jl

8

""

t3l

J

-

7

J~

""Jv

16

Jv

15

~

14

13

-

8

..
II
.7

9
19'011

.2.3

"7 8'.

2.i"

4-18

'3 ....i.:

21213031

-

...J
~

12

~"
0038-22

Functional Logic Diagram PAL C 16R6
INPUTS (0 - 31)

1-1>

I.

,

'. '.'

0

.,....., ....J

2

,
•
3

2

:-.....

,.

"

I.l

iUl~

J

'3

r--J

"

II

,.

::J

17

18

~

iUl

J

4

-:J

i3I

~

5!

~

0:

....W

19

5

........

g

9

::J

80:

...

:I
....

6

.....

"I....

......

7

.,....,
~

......

8
•1

~~

57

5'

~

18

IJ....

17

IJ....

16

IJ....

~

CU]

15

IJ....

14

~

13

12

"1-"-4
9

--....
;

••• 7

I ... "

,

~ 11

117
0038-23

4-19

II

~CYPRFSS

PAL® C 20 Series

~r~CCJNDUCrOR==========~~
Functional Logic Diagram PAL C 16R8

'

.......

INPUTS (0
5

)1

2',31

',.

',.'

- 31)
~,

(0'

~22.3

!.2.:

~2~3,03.'

rJ

...
.J

3

.....

,.
17

M~
1....

q

I.l...

/""""1

,.

"'"

r9
~
- fUJl

20

2'
22
23

19

18

17

...

2.

rl

25

28
27
30
31

n I:l...

1--1

"'"
...

...

6
40
4'
42
43
44

/""""1

r---

"'"

.8
47

~
o

at--

~~~

r-1

~

16

15

14

~

ftJl
a

55
57
.8

...........

5'

80
8'
.2

....-

r--o

a

~~

:J....
I.l

13

12

...

l

~

~

i

1.0

0.8

o.6

V

V
4.0

v

V

NORMALIZED SUPPLY CURRENT

~ 1.21---'~--+------t
~

I

TA o25'C
loMAX.
5.6

6.0

4.6

NORMALIZED PROPAGATION
DELAY VB. SUPPLY VOLTAGE

VB. AMBIENT TEMPERATURE
1.6..-----,-----,

1.01------''k:-----l

1.2

Q

.

N

:::;

<
:IE

~

1.0

'"

II:

<>
Z

0.8~-----r--~~~

0·~=------:26!:-----".!,,26

6.0

, .............

1.

I!-

<>

SUPPLY VOLTAGE (VI

O. 9

O.8
4.0

AMBIENT TEMPERATURE ('CI

NORMALIZED PROPAGATION DELAY

16.0

10.0

irl
<>

V

0.0 0

200

AMBIENT TEMPERATURE ('CI

I'

V

L

V

I-

L

g
:::;

I

400

600

I"

1.

5l
N

600

'" '"

1.0

o.9
0.8
4.0

1000

CAPACITANCE (pfl

NORMALIZED SETUP TIME

4.6

5.0

~

5.5

6.0

SUPPL Y VOLTAGE (VI

NORMALIZED CLOCK
TO OUTPUT
TIME vs. TEMPERATURE

NORMALIZED CLOCK TO OUTPUT
TIME VB. SUPPLY VOLTAGE

VB. TEMPERATURE
1.3.-----.-----.,

8.0

1.2

!

6.0

6.6

NORMALIZED SETUP TIME
vs. SUPPLY VOLTAGE

20.0

..g

6.0

SUPPLY VOLTAGE (VI

DELTA PROPAGATION TIME
vs. OUTPUT LOADING

VB. TEMPERATURE
1.3r------r-----,

4.5

J'...

1.1r---r--..---r--,

1

Ar-----,-----,

1.3

§
<>

1.2

:IE

1.1

~
:::;

..
II:

0

Z

1.0

AMBIENT TEMPERATURE ('CI

SUPPLY VOLTAGE (VI

DELTA CLOCK TO OUTPUT TIME
OUTPUT LOADING

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

VB.

200

20.0

L

16.0

V~

!
E 10.0
I...

..

V

<>

5.0

V

0.00

./

1

.

Ii

125

u

100

:>

"z

1il

i
5

400

800

CAPACITANCE (pFI

800

1000

175
160

II:
II:

<>

200

AMBIENT TEMPERATURE ('CI

/

-

/

100

II:
II:

:>

80

II:

60

u
u

:>

/

~~o;:;~v-

II

~.o

120

z

.
.

~

60

1
I-

/

76

26

~

OUTPUT SOURCE CURRENT
VB. VOLTAGE
140

iii

~

40

r\.

'" ""-

l"'-.

20

0

1.0

2.0

3.0

OUTPUT VOLTAGE (VI

4.0

1.0

2.0

"t"-.... .......
3.0

4.0

OUTPUT VOLTAGE (VI

0038-25

4-21

~~=====================================P=A=L=®=C==2=o=s=en='=es
Ordering Information
tpn

ts

teo

(os)

(ns)

(os)

-

-

20

25

-

-

Icc

(rnA)
70

45

70

30

35

-

-

-

-

70

45

70

40

20

25

-

20

20

-

15

15

70

70

45

70

Package

Operating
Range

PAL C 16LS-200MB

06

Military

PAL C 16LS-20LMB

L61

Ordering Code

PAL C 16LS-20WMB

W6

PALC 16L8-20KMB

K71

PAL C 16LS-20QMB

Q61

PALC 16LSL-25PC

P5

PALC 16LSL-25VC

V5

PAL C 16LSL-25LC

L61

PAL C 16LSL-25WC

W6

PALC 16LS-25PC/PI

P5

PALC 16L8-25VC/vI

V5

PAL C 16LS-25LC

L61

PALC 16LS-25WC/WI

W6

PAL C 16LS-300MB

06

PALC 16LS-30LMB

L61

PAL C 16LS-30WMB

W6

PAL C 16LS-30KMB

K71

PAL C 16LS-3OQMB

Q61

PAL C 16LSL-35PC

P5

PAL C 16LSL-35VC

V5

PAL C 16LSL-35LC

L61

PALC 16LSL-35WC

W6

PAL C 16LS-35PC/PI

P5

PAL C 16LS-35VC/VI

V5

PAL C 16LS-35LC

L61

PAL C 16LS-35WC/wI

W6

PAL C 16LS-400MB

06

PAL C 16LS-4OLMB

L61

PAL C 16LS-4OWMB

W6

PAL C 16LS-4OKMB

K71

PAL C 16L8-4OQMB

Q61

PAL C 16R4-200MB

06

PAL C 16R4-20LMB

L61

PALC 16R4-20WMB

W6

PALC 16R4-20KMB

K71

PAL C 16R4-20QMB

Q61

PAL C 16R4L-25PC

P5

PAL C 16R4L-25VC

V5

PALC 16R4L-25LC

L61

PAL C 16R4L-25WC

W6

PALC 16R4-25PC/PI

P5

PAL C 16R4-25VC/VI

V5

PAL C 16R4-25LC

L61

PAL C 16R4-25WC/WI

W6

4-22

Commercial

Military

Commercial

Military

Military

Commercial

~
PAL®C20Series
~~~~=============================================================
Ordering Information (Continued)
ts

tpD
(ns)

(ns)

30

25

35

30

teo

Icc

(ns)

(mA)

20

70

25

45

70

40

20

25

35

20

20

25

15

15

70

70

45

70

30

35

25

30

20

25

70

45

Package

Operating
Range

PAL C 16R4·300MB

06

Military

PALC 16R4-30LMB

L61

Ordering Code

PAL C 16R4·30WMB

W6

PALC 16R4·30KMB
PAL C 16R4.3OQMB

K71
P5
V5

PAL C 16R4L-35LC

L61

PAL C 16R4L-35WC

W6

PAL C 16R4·35PCIPI

P5

PAL C 16R4-35VC/vI

V5

PAL C 16R4·35LC

L61

PAL C 16R4-35WC/wI

W6

PAL C 16R4-400MB

06

PALC 16R4-40LMB
PAL C 16R4-40WMB

L61

PAL C 16R4-4OKMB

K71

PALC 16R4-4OQMB

Q61
06

PAL C 16R6-20LMB

L61

PAL C 16R6·20WMB

W6

PALC 16R6·20KMB

K71

PALC 16R6.2OQMB

Q61

PAL C 16R6L-25PC

P5

PAL C 16R6L·25VC

V5

PAL C 16R6L·25LC

L61

PALC 16R6L·25WC

W6

PAL C 16R6·25PCIPI

P5

PAL C 16R6·25VC/VI

V5

PAL C 16R6·25LC
PALC 16R6-25WC/wI

L61
W6

PAL C 16R6·300MB

06

PAL C 16R6·30LMB

L61

PAL C 16R6·30WMB

W6

PAL C 16R6·30KMB
PALC 16R6.30QMB

K71

II
Military

Military

Commercial

Military

Q61

PAL C 16R6L·35PC

P5

PAL C 16R6L·35VC

V5

PAL C 16R6L·35LC

L61
W6

PAL C 16R6·35PC/PI

P5

PALC 16R6·35VC/VI

V5

PAL C 16R6·35LC

L61

PAL C 16R6·35WC/WI

W6

4·23

Commercial

W6

PAL C 16R6-200MB

PAL C 16R6L·35WC
70

Q61

PAL C 16R4L·35PC
PAL C 16R4L-35VC

Commercial

~

PAL®C20Series

~r~~===================
Ordering Information (Continued)
ts

tpD
(ns)

(os)

40

35

-

-

20

20

teo

Icc

(ns)

(IDA)

25

70

15

15

70

4S

70

-

-

25

30

20

2S

70

4S

70

-

35

25

70

Ordering Code

Package

PALC 16R6-40DMB

D6

PAL C 16R6-40LMB

L61

PALC 16R6-40WMB

W6

PAL C 16R6-40KMB

K71

PALC 16R6-4OQMB

Q61

PALC 16RS-20DMB

D6

PALC 16RS-20LMB

L61

PAL C 16RS-20WMB

W6

PAL C 16RS-20KMB

K71

PAL C 16RS-2OQMB

Q61

PAL C 16RSL-2SPC

P5

PAL C 16RSL-25VC

V5

PAL C 16RSL-25LC

L61

PAL C 16R8L-2SWC

W6

PAL C 16RS-25PC/PI

PS

PAL C 16RS-2SVCIVI

VS

PAL C 16RS-2SLC

L61

PAL C 16R8-2SWC!WI

W6

PAL C 16RS-30DMB

D6

PAL C 16RS-30LMB

L61

PAL C 16RS-30WMB

W6

PAL C 16RS-30KMB

K71

PAL C 16RS-3OQMB

Q61

PAL C 16RSL-3SPC

PS

PAL C 16R8L-35VC

V5

PAL C 16RSL-3SLC

L61

PALC 16RSL-3SWC

W6

PAL C 16RS-3SPC/PI

PS

PAL C 16RS-3SVC/vI

VS

PAL C 16RS-3SLC

L61

PAL C 16RS-3SWC/WI

W6

PALC 16R8-4ODMB

D6

PAL C 16RS-40LMB

L61

PAL C 16RS-40WMB

W6

PAL C 16RS-40KMB

K71

PALC 16RS-4OQMB

Q61

4-24

Operating
Range

Military

Military

Commercial

Military

Commercial

Military

~

PAL®C20Series
~~~aoR~~~~~~;=~~~~~~~~~~~~~~~~~~~~~==
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

Vpp

1,2,3

Icc

1,2,3

IOZ

1,2,3

Switching Characteristics
Parameters

Subgroups

tpD

9,10,11

tpzx

9,10,11

teo
ts

9,10,11
9,10,11

tH

9,10,11

Document #: 38-OOOO1-C

4·25

PRELIMINARY

CYPRESS
SEMICONDUCTOR

PLDC18G8

CMOS Generic 20 Pin
Programmable Logic Device

Features

• Low power
- ICC max.: 80 mA, commercial
- ICC max.: 110 mA, military

• Generic architecture to replace
standard logic functions
including: 10H8, 12H6, 14H4,
16M2, lOLa, 121.6, 141.4, 16L2,
10P8, 12P6, 14P4, 16P2, 16H8,
16L8, 16P8, 16R8, 16R6, 16R4,
16RP8, 16RP6, 16RP4, 18P8,
16V8

• Commercial and military
temperature range

• Eight product terms and one OE
product term per output

• User-programmable output cells
- Selectable for registered or
combinatorial operation
- Output polarity control
- Output enable source
selectable from pin 11 or
product term

• CMOS EPROM technology for
reprogrammabiUty

• Fast
-

Commercial: tpn = 12 ns,
teo = 10 ns, ts = 12 ns
MUitary: tpn = 15 ns,
teo = 12 ns, ts 15 ns

-

-

Security feature prevents
logic pattern dupUcation
> 2000V input protection for
electrostatic discharge

Functional Description
Cypress PLD devices are high speed
electrically programmable Logic Devices. These devices utilize the sum of
products (AND-OR) structure providing users the ability to program custom
logic functions for unique requirements.

• Highly reUable
- Uses proven EPROM
technology
- Fully AC and DC tested

In an unprogrammed state the AND
gates are connected via EPROM cells
to both the true and complement of every input. By selectively programming
the EPROM cells, AND gates may be

Logic Symbol, DIP and SOJ Pinout
18GS

Vee
0139-1

PLCCPinout

LCCPinout

--~~~
I/O

I

4

18

I/O
I/o

I

5

17

I

6

16

I/O
I/O

I

7

15

I

8

14

-

I/o
I/o
I/O
I/o
I/O

tl~ 0 0

>~~:::::.
0139-3

0139-2

4-26

~
PRELIMINARY PLDC18G8
~r~~=================
Selection Guide
Generic
Part
Number

Com

ISGS-12

SO

ISGS-IS

SO

Icc (mA)

tpn (ns)
Mil

ISGS-20

Com

Mil

110

15

Com

Mil

Com

12

12
110

teo

ts

15

12

20

Mil

10
15

12

12

20

15

providing the next state. T.he r«:gi~t~~ is.clocked by the
signal from Pin 1. The register IS initialized on power up to
Q output LOW and Q output HIGH.

Functional Description (Continued)
connected to either the true or complement or disconnected from both true and complement inputs.

In both the Combinatorial and Registered configurations,
the source of the "OUTPUT ENABLE" signal can be individually chosen with architecture bit 'C2'. The OE signal
may be generated within the array, or from the external
OE pin (Pin 11). The Pin 11 allows di!ect col?-trol of the
outputs, hence having faster enable/disable times.

Cypress PLD C IBGB uses an advanced O.B micron CMOS
technology and a proven EPROM cell as the programmable element. This technology and the inherent advantage of
being able to program and erase each cell enhances the
reliability and testability of the circuit. This reduces the
burden on the customer to test and to handle rejects.

Each output cell can be configured for "OUTPUT POLARITY". The output can be either Active HIGH or Active LOW. This option is controlled by architecture bit
'CO',

A preload function allows the registered outputs to be preset to any pattern during testing. Preload is imp~rtant for
testing the functionality of the Cypress PLD deVIce.

Along with this increase in functional density, the Cypress
PLD C 1BG8 provides lower power operation through the
use of CMOS technology, increased testability with a register preload feature and guaranteed AC performance
through the use of a phantom array. The phantom array
allows the 18GB to be programmed with a test pattern and
tested prior to shipment for full AC specifications without
using any of the functionality of the device specified for the
product application. In addition, this sa~e ph~t~m array
may be used to test the PLD C 18GB at incoming inSpection before committing the device to a specific function
through programming.

18G8 Functional Description
The PLD C 18G8 is a generic 20 pin device that can be
programmed to logic functions which include but are not
limited to: 10H8, 12H6, 14H4, 16H2, IOLB, 12L6, 14L4,
16L2, IOP8, 12P6, 14P4, 16P2, 16H8, 16LB, 16PB, 16RB,
16R6, 16R4, 16RP8, 16RP6, 16RP4, 18P8, 16V8. Thus,
the PLD C 18GB provides significant design, inventory and
programming flexibility over dedicated 20 pin devices.. It is
executed in a 20 pin 300 mil molded DIP and a 300 md
windowed Cerdip. It provides up to 1B inputs and B outputs. When the windowed CERDIP is exposed to UV
light, the 18GB is erased and then can be reprogrammed.

Programmable Output Cell

The Programmable Output Cell provides the capability of
defining the architecture of each output individually. Each
of the 10 output cells may be configured with "REGISTERED" or "COMBINATORIAL" outputs, "ACTIVE
HIGH" or "ACTIVE LOW" outputs, and "PRODUCT
TERM" or "PIN 11" generated output enables. Four Architecture Bits determine the configurations as shown in
Table 1. A total of sixteen different configurations are possible. The default or unprogrammed state is REGISTERED/ACTIVE/LOW/Pin 11 OE. The entire Programmable Output Cell is shown in Figure 1.

r-------------------------,
OE PRODUCT TERM

10

00

~~~ I-+-+-~>O-...,...
.ux

The architecture bit 'C1' controls the REGISTERED/
COMBINATORIAL option. In either "COMBINATORIAL" or "REGISTERED" configuration, the output can
serve as an I/O pin, or if the output is disabled, as an input
only. Any unused inputs should be tied to ground. In either
"REGISTERED" or "COMBINATORIAL" configuration, the output of the register may be fed back to th~
array. This allows the creation of control-state machines by

INPUTI

FEEDBACK

:~ ~'------------_+_+--~_t_;--~

C'@~~=L
L____________________ ___ _
C,
C,

~

PINt1

0139-4

Figure 1

4-27

~
PRELIMINARY PLD C 18G8
~~~~==========================================================
Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ....... , ............. >2001V
Storage Temperature .... , .......... -6SoC to + 1SO"C
(per MIL-STD-883 Method 301S)
Ambient Temperature with
Power Applied .................... - SsoC to + 12SoC

Latchup Current .......................... > 200 mA

Supply Voltage to Ground Potential .... -O.SVto +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to + 7.0V

Ambient
Temperature

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial
Military!7]

Output Current into Outputs (Low) ............. 24 mA
DC Programming Voltage ...................... 13.0V

Vee

O"Cto +7SOC

SV ±S%

-SS·Cto + 12S·C

SV ±1O%

Electrical Characteristics Over Operating Range (Unless Otherwise Noted)[7]
Parameters

Description

Test Conditions
Vee = Min.
VIN = VIH or VIL

Output HIGH Voltage

VOH

Vee = Min.
VIN = VIH or VIL

Output LOW Voltage

VOL

Min.

IOH = -3.2mA

Commercial

IOH=-2mA

Military

IOL = 24mA

Commercial

IOL = 12mA

Military

VIH

Input HIGH Level

Guaranteed Input Logical HIGH[l] Voltage for all Inputs

VIL

Input LOW Level

Guaranteed Input Logical LOW!!] Voltage for all Inputs

IIX

Input Leakage Current

Vss :::;; VIN :::;; Vee

Vpp

Max.

Units

2.4

V
0.5

V

2.0

V
0.8

V

-10

10

p.A

Programming Voltage @ Ipp = 50 rnA Max.

12.0

13.0

V

Ise

Output Short Circuit
Current

Vee = Max., VOUT = 0.SV!2]

-30

-90

rnA

lee

Power Supply Current

0:::;; VIN:::;; Vee
Vee = Max., lOUT = 0 mA

Output Leakage Current

loz

Commercial

80

Military

110

-40

Vee = Max., VSS :::;; VOUT :::;; Vee

mA

40

rnA

Capacitance [3]
Parameters

Description

Test Conditions

Max.

CIN

Input Capacitance

TA = 2S·C, f = 1 MHz

S

CoUT

Output Capacitance

VIN = 2.0V, Vee = S.OV

8

ft n

Units
pF

AC Test Loads and Waveforms (Commercial)
Rl 160.0.
(319.0. MIL)

OUTP~~

~~

INCLUDING
JIG AND
SCOPE

Rl 160.0.
(319.0. MIL)

R2

I

OUTP~~

12~

5~

(236.0. MIL)

I

R2
12~

.

(236.0. MIL)

0139-5

Figure2a
Equivalent to:

.

Figure2b

THEVENIN EQUIVALENT (Commercial)

Equivalent to:

THEVENIN EQUIVALENT (Military)
OUTPUT

0139-6

no---'
0139-7

4-28

Configuration Table[8]
Table 1
Configuration

C3

C2

Cl

Co

0

0

0

Active LOW, Registered Mode, Registered Feedback, Pin 11 OE

0

0
0

0

1

Active HIGH, Registered Mode, Registered Feedback, Pin 11 OE

0

0

1

0

Active LOW, Combinatorial Mode, Registered Feedback, Pin 11 OE

0

0

1

1

Active HIGH, Combinatorial Mode, Registered Feedback, Pin 11 OE

0

1

0

0

Active LOW, Registered Mode, Registered Feedback, Product Term OE

0

1

0

1

Active HIGH, Registered Mode, Registered Feedback, Product Term OE

0

1

1

0

Active LOW, Combinatorial Mode, Registered Feedback, Product Term OE

0

1

1

1

Active HIGH, Combinatorial Mode, Registered Feedback, Product Term OE

1

0

0

0

Active LOW, Registered Mode, Pin Feedback, Pin 11 OE

1

0

0

1

Active HIGH, Registered Mode, Pin Feedback, Pin 11 OE

1

0

1

0

Active LOW, Combinatorial Mode, Pin Feedback, Pin 11 OE

1

0

1

1

Active HIGH, Combinatorial Mode, Pin Feedback, Pin 11 OE

1

1

0

0

Active LOW, Registered Mode, Pin Feedback, Product Term OE

1

1

0

1

Active HIGH, Registered Mode, Pin Feedback, Product Term OE

1

1

1

0

Active LOW, Combinatorial Mode, Pin Feedback, Product Term OE

1

1

1

1

Active HIGH, Combinatorial Mode, Pin Feedback, Product Term OE

Switching Characteristics PLD C 18G8 Over Operating Range[4, 9]
Military

Commercial

Parameters

-12

Description
Min.

-15

Max.

Min.

-20

-15

Max.

Min.

Max.

Min.

Units

Max.

tpD

Input or Feedback to
Non-Registered Output

12

15

15

20

ns

tEA

Input to Output Enable

12

15

15

20

ns

tER

Input to Output Disable

12

IS

IS

20

ns

tpzx

Pin 11 to Output Enable

10

12

12

15

ns

tpxz

Pin 11 to Output Disable

10

10

10

15

ns

teo

Clock to Output

10

12

12

15

ns

t8

Input or Feedback Setup Time

12

12

15

20

ns

tH
tp[5]

Hold Time

0

0

0

0

ns

Clock Period

22

24

27

35

ns

tWH

Clock High Time

7

8

9

10

ns

tWL

Clock Low Time

8

9

10

11

ns

tMAx[6]

Maximum Frequency

37.0

28.6

MHz

41.6

45.5

Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
3. Tested initially and after any design or process changes that may
affect these parameters.
4. Figure 2a test load used for all parameters except tER, tpzx and tpxz.
Figure 2b test load used for tER, tpzx and tpxz.
5. tp, minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from tp = ts + teo. The minimum
guaranteed period for registered data path operation (no feedback)
can be calculated as the greater of (tWH + tWJJ or (ts + tWo

6. IMAX, minimum guaranteed operating frequency, is that guaranteed
for state machine operation and is calculated from fMAX = l/(ts +
teo). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower of l/(tWH + twu
or l/(ts + tH).
7. TA is the "instant on" case temperature.
8. In the virgin or unprogrammed state, a configuration bit location is in
the ''0'' state.
9. The parameters tER and tpxz are measured as the delay from the
input disable logic threshold transition to VOH - O.5V for an enabled
HIGH output or VOL + O.5V for an enabled LOW output.

4-29

II

~

PRELIMINARY

PLDC18G8

~r~===================
Switching Waveform
INPUTS. 110.

REGISTERED
FEEDBACK

-~
ts

InxnlX~
- t w _ !-o--tw-

tH-

\

CP

-

..1

tp_

J

I-tpxz~
"-n\

f4-tc;o ..

REGISTERED
OUTPUTS:

COMBINtJ~p~~

XIIIX~

LLL1ll

\

~tpzx

1111
\.\.\.\.

». )_H
.

~tER;:j

tpo

___________________
) ....

~tEA

(~(.«~_
..
0139-8

Note:
For more information regarding PLD devices, refer to the Application Brief in the Appendix.

4-30

~

PRELIMINARY

PLDC18G8

~~~U~==============================~~~~~~~~====~~~~
Functional Logic Diagram PLD C 18G8
INPUT LINES

-~

P, P3
Po P2

0

4

8

12

16

20

24

28

32

DE
0

~

·
~7

~

---

d-

DE
0

··
:-t:::

~

I-'

7

DE
0

··
3I....f"'::
-

CEL~

--

~

....

4......

""

OE
0

Vl

::!l

0:::
L.J

l-

t>::>

5,-I"::

c

o

0:::
Il.

·

~

~

~
~
::::::=
~
~

d- I>

~
~

·

~

OE
0

··
8 -I"::

CEL~

~
OUTPUT

-- ....

7

k

I>

CE~~

~
OUTPUT
CELL

~I>
I...--

7

__ ....

9-1"::

4-31

16

~

OUTPUT

I-'

OE
0

~

'=

d- I>

7

·
6i~7
7 .....

17

OUTPUT
CELL

I-'

OE
0

.....

I>

OUTPUT
CElL

--d....

7

18

OUTPUT

I-'

·

19

;:::::=
CEL~

OE
0

.....

CELL

6- I>

~

7

~

OUTPUT

---

-

2

=~
~
:=:
~

15

14

f---,

K;,

13

f--,

H:>oT 12
if

11
0139-9

~

PRELIMINARY

PLD C 18G8

~~~~~~~~~~~~~~~~~~==========~~~~~~~~~~~=
Ordering Information
Speed
(ns)

12

15

20

Package
Type

Operating
Range

PLD C ISGS-12PC

P5

Commercial

PLD C ISGS-12WC

W6

Ordering Code

PLD C ISGS-12VC

V5

PLD C ISGS-I2JC

J61

PLD C ISGS-15PC

P5

PLD C ISGS-15WC

W6

PLD C ISGS-15VC

V5

PLD C ISGS-15JC

J61

PLD C ISGS-15DMB

D6

PLD C ISGS-15WMB

W6

PLD C ISGS-15LMB

L61

PLD C ISG8-20DMB

D6

PLD C ISGS-20WMB

W6

PLD C ISGS-20LMB

L61

Commercial

Military

Military

Document #: 38-00080

4-32

PLD C 20GIOB/PLD C 20GIO

CYPRESS
SEMICONDUCTOR

CMOS Generic 24 Pin
Reprogrammable Logic Device
Functional Description

Features
• Fast
- Commercial: tpD
teo = 10 ns, ts
- Military: tpD =
teo = 15 ns, ts

= 15 os,

= 12 ns
20 ns,
= 17 ns

• Low power
- ICC max.: 70 mA,
Commercial
- ICC max.: 100 mA, Military
• Commercial and military
temperature range
• User-programmable output cells
- Selectable for registered or
combinatorial operation
- Output polarity control
- Output enable source
selectable from pin 13 or
product term

• Generic architecture to replace
standard logic functions
including: 20LlO, 20LS, 20R8,
20R6, 20R4, 12LlO, 14LS, 16L6,
18L4, 20L2 and 20V8
• Eight product terms and one OE
product term per output
• CMOS EPROM technology for
reprogrammability
• Highly reliable
- Uses proven EPROM
technology
- Fully AC and DC tested
- Security feature prevents
logic pattern duplication
- > 2000V input protection for
electrostatic discharge
- ± 10% power supply voltage
and higher noise immunity

Cypress PLD devices are high speed
electrically programmable Logic Devices. These devices utilize the sum of
products (AND-OR) structure providing users the ability to program custom
logic functions for unique requirements.
In an unprogrammed state the AND
gates are connected via EPROM cells
to both the true and complement of every input. By selectively programming
the EPROM cells, AND gates may be
connected to either the true or complement or disconnected from both true
and complement inputs.
Cypress PLD C 200 10 uses an advanced 0.8 micron CMOS technology
and a proven EPROM cell as the pro-

Logic Symbol
20GI0

0053-16

LCCPinout

STD PLCC Pinout

8 00
z __ ~
u>:::..:::..

u
I
I
I

I
NC

4 3 2111282728
S
U
25
8
24
7
23
8
20010
22
9
21
10
20
II
19
12131415181718

- - >:lI1'"
0 0 u
~:::..:::..z

JEDEC PLCC Pinout[16]

800
___ <:::.
I!s>:5-:5-

NC

I/o
I/o
I/o
I/o
I/o
I/o

NC
I

I/o
I/o
I/o
I/o
I/o
I/o

NC
I
Ne

0063-17

Ne

---~~oo

>_:5-:5-

4-33

0063-28

1/0 2
NC

CC7C323 - A
CG7C323B _ A

I

23
22
21
20

1\213141518171~9

I/oa
I/O,

Ne

I/Os
I/Oa
1/07

--~U-3~

>Z

:5-:5-

0053-41

4

~CiPRF13S

PLD C 20GI0B/PLD C 20GI0

~~~==========~~~~
Selection Guide
Generic

Icc

Part

ts

tpn

teo

Number

L

Com/Ind

2OGIOB-15

70

2ooI0B-20

-

70

100

2oo10B-25

-

-

100

20010-25

-

55

-

25

-

IS

-

80

-

30

-

20

55

-

35

-

30

-

-

80

-

40

-

35

20010-30
20010-35
20010-40

Functional Description

Mil

-

ComlInd

Mil

Com/Ind

Mil

Mil

Com/Ind

-

12

20

20

-

17

IS

-

25

-

18

IS

IS

10

15
20
25
25

signal from Pin 1. The register is initialized on power up to

(Continued)

Q output LOW and Q output HIGH.

grammable element. This technology and the inherent advantage of being able to program and erase each cell enhances the reliability and testability of the circuit. This reduces the burden on the customer to test and to handle
rejects.

In both the Combinatorial and Registered configurations,
the source of the "OUTPUT ENABLE" signal can be individually chosen with architecture bit 'C2'. The OE signal
may be generated within the array, or from the external
OB pin (Pin 13). The Pin 13 allows direct control of the
outputs, hence having faster enable/disable times.

A preload function allows the registered outputs to be preset to any pattern during testing. Preload is important for
testing the functionality of the Cypress PLD device.

Each output cell can be configured for "OUTPUT POLARITY". The output can be either Active HIGH or Active LOW. This option is controlled by architecture bit
'CO'.

20G10 Functional Description
The PLD C 20010 is a generic 24 pin device that can be
programmed to logic functions which include but are not
limited to: 20LlO, 20L8, 20R8, 20R6, 20R4, 12LlO, 14L8,
16L6, 18L4, 20L2 and 20V8. Thus, the PLD C 20010
provides significant design, inventory and programming
flexibility over dedicated 24 pin devices. It is executed in a
24 pin 300 mil molded DIP and a 300 mil windowed Cerdip. It provides up to 22 inputs and 10 outputs. When the
windowed CERDIP is exposed to UV light, the 20010 is
erased and then can be reprogrammed.

Along with this increase in functional density, the Cypress
PLD C 20G 10 provides lower power operation through the
use of CMOS technology, increased testability with a register preload feature and guaranteed AC performance
through the use of a phantom array. The phantom array
allows the 20G 10 to be programmed with a test pattern
and tested prior to shipment for full AC specifications
without using any ofthe functionality ofthe device specified for the product application. In addition, this same
phantom array may be used to test the PLD C 20G 10 at
incoming inspection before committing the device to a specific function through programming.

The Programmable Output Cell provides the capability of
defining the architecture of each output individually. Each
of the 10 output cells may be configured with "REGISTERED" or "COMBINATORIAL" outputs, "ACTIVE
HIGH" or "ACTIVE LOW" outputs, and "PRODUCT
TERM" or "PIN 13" generated output enables. Three Architecture Bits determine the configurations as shown in
Table 1 and in Figures 2 through 9. A total of eight different configurations are possible, with the two most common
shown in Figure 4 and Figure 6. The default or unprogrammed state is REGISTERED/ACTIVE LOW/
PRODUCT TERM OE as shown in Figure 2. The entire
Programmable Output Cell is shown in Figure 1.

Programmable Output Cell

r--------------------------,

I

I

DE PRODUCT TEll.

01

c:..~ 1-+-1--+1

""X

c,

The architecture bit 'Cl' controls the REGISTERED/
COMBINATORIAL option. In the "COMBINATORIAL" configuration, the output can serve as an VO pin, or
if the output is disabled, as an input only. Any unused
inputs should be tied to ground. In the "REGISTERED"
configuration, the output of the register is fed back to the
array. This allows the creation of control-state machines by
providing the next state. The register is clocked by the

Co

c,

!==~!=======~=I~
L ____________________ _

PIN13

Figure 1

4-34

0053-32

Configuration Table
Table 1
Figure

C2
0
0
0
0
1
1
1
1

2
3
6
7
4
5
g

9

Cl
0
0
1
1
0
0
1
1

Co

Configuration

0
1
0
1
0
1
0
1

Product Term OE/Registered/Active LOW
Product Term OE/Registered/Active HIGH
Product Term OE/Combinatorial!Active LOW
Product Term OE/Combinatorial!Active HIGH
Pin 13 OE/Registered/Active LOW
Pin 13 OE/Registered/Active HIGH
Pin 13 OE/Combinatorial!Active LOW
Pin 13 OE/Combinatorial/Active HIGH

II

Registered Output Configurations
Cz = 0
Cl = 0
Co = 0

C2 = 0
Cl = 0
Co = 1

0053-37

0053-38

Figure 3. Product Term OEIActive HIGH

Figure 2. Product Term OE/Active LOW
C2 = 1
Cl = 0

Co

=

C2 = 1
Cl = 0
Co = 1

0

CP

0053-39

0053-40

Figure 5. Pin 13 OEIActive HIGH

Figure 4. Pin 13 OE/Active LOW

Combinatorial Output Configurations [6]
C2 = 0
Cl = 1
Co = 0

C2 = 0
Cl = 1

Co

0053-33

1

0053-34

Figure 6. Product Term OEIActive LOW

Figure 7. Product Term OEIActive HIGH

~

C2 = 1
Cl = 1
Co= 0

PINt3

=

PINt3

0053-35

C2 = 1
Cl = 1

Co

0053-36

Figure 9. Pin 13 OEIActive HIGH

Figure 8. Pin 13 OEIActive LOW

4-35

=

1

~.
PLD C 20GIOBIPLD C20G-tO
'Wr~·============
Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ...... ; ........ - 65°C to + ISO"C
Ambient Temperature with
Power Applied ..........•......... - SSoC to + 12SoC

Static Discharge Voltage ..................... >2oo1V
(per MIL-STD-883 Method 3015)
.
Latchup Current .................•......... > 200 mA

Supply Voltage to Ground Potential .... -O.SV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ..........•..•........ -O.SV to +7.0V

Range

DC Input Voltage ................. : • - 3.0V to + 7.0V
Output Current into Outputs (Low) .........•... 16 mA
DC Programming Voltage
PAL C 22VlOB and CG7C323B-A ......•...... 13.0V
PAL C 22VI0 and CG7C323-A ............... 14.0V

Ambient
Temperature

Vee

Commercial
Military[8]

O"C to + 75°C

5V ±IO%

- 55°C to + 125°C

5V ±IO%

Industrial

-40"C to + 85°C

5V ±IO%

Electrical Characteristics Over Operating Range (Unless Otherwise Noted)[7]
Parameters

Description

Min.

Test Conditions

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIHorVIL

IoH = -3.2mA

COM'L/IND

IOH = -2mA

Military

VOL

Output LOW Voltage

Vee = Min.
VIN = VIH or VIL

IoL = 16mA

COM'LIIND

IOL = 12mA

Military

VIH

Input HIGH Level

Guaranteed Input Logical HIGH 111 Voltage for all Inputs

VIL

Input LOW Level

Guaranteed Input Logical LOW!t] Voltage for all Inputs

hx

Input Leakage Current

Vss S; VIN S; Vee

Ise

Output Short Circuit
Current

Vee = Max., VOUT = 0.5V[2]

2.4

V
0.5

2.0
-10

V
V

10

/LA

-90

mA

70

COM'LIIND -25, -35

55

OS; VIN S; Vee
Vee = Max., lOUT = OmA Military .20, -25

Power Supply Current

loz

Output Leakage Current Vee = Max., Vss S; VOUT S; Vee

100

Military ·30, -40

V

0.8

COM'LIIND -IS, -20
lee

4-36

Max. Units

mA

80
-100

100

/LA

~

PLD C 20GI0B/PLD C 20GI0

~~~NDU~======================================================================
Capacitance [3]
Parameters

Description

Test Conditions

Max.

CIN

Input Capacitance

TA = 25°C, f = 1 MHz

4

COUT

Output Capacitance

VIN = 0, VCC = 5.0V

7

Units
pF

Switching Characteristics PLD C 20GIO Over Operating Range[4, 7]
Commercial
Parameters

Description

B-15

B-20

Military

-25

-35

B-20

B-25

-30

-40

Unit!

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tpD

Input to Output
Propagation Delay[15]

15

20

25

35

20

25

30

40

ns

tEA

Input to Output
Enable Delay

15

20

25

35

20

25

30

40

ns

tER

Input to Output
Disable Delay[IO]

15

20

25

35

20

25

30

40

ns

tpzx

OE Input to Output
Enable Delay

12

15

20

25

17

20

25

25

ns

tpzx

OE Input to Output
Disable Delay

12

15

20

25

17

20

25

25

ns

tco

Clock to Output
Delay[15J

10

12

15

25

15

15

20

25

ns

ts

Input or Feedback
Setup Time

12

12

15

30

15

18

20

35

ns

tH

Input Hold Time

0

0

0

0

0

0

0

0

ns

tp

External Clock
Period (Tco + ts)

22

24

30

55

30

33

40

60

ns

tWH

Clock Width HIGH[3,9J

8

10

12

17

12

14

16

22

ns

tWL

Clock Width LOW [3,9J

8

10

12

17

12

14

16

22

ns

fMAXI

External Maximum
Frequency
(l!(tco + ts»[IIJ

45.4

41.6

33.3

IS.1

33.3

30.3

25.0

16.6

MHz

fMAX2

Data Path
Maximum Frequencr
(l!(twH + twL»[12

62.5

50.0

41.6

29.4

41.6

35.7

31.2

22.7

MHz

fMAX3

Internal Feedback
Maximum Fre?Uency
(l!(tCF + tS» 13J

66.6

45.4

35.7

20.8

33.3

32.2

2S.5

18.1

MHz

tCF

Register Clock to
Feedback Inpud l4J

3.0

10

13

Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = 0.5V has
been chosen to avoid test problems caused by tester ground degradation.
3. Tested initially and after any design or process changes that may
affect these parameters.
4. Figure lla test load used for all parameters except tER, tpzx and
tpxz. Figure lIb test load used for tER, tpzx and tpxz. See Figure 10
for waveforms.
5. Preliminary specifications.
6. BidirectionalllO configurations are possible only when the combinatorial output option is selected.
7. See the last page of this specification for Group A subgroup testing
information.
8. TA is the "instant on" case temperature.
9. Tested by periodically sampling production product.

IS

13

13

15

20

ns

10. This parameter is measured as the time after output disable input
that the previous output data state remains stable on the output. This
delay is measured to the point at which a previous high level has
fallen to 0.5 volts below VOH Min. or a previous low level has risen
to 0.5 volts above VOL Max. Please see Figure JOfor enable and
disable waveforms and measurement reference levels.
II. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feed back can
operate.
12. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
13. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feed back can
operate. This parameter is tested periodically by sampling production product.
14. This parameter is calculated from the clock period at fMAX internal
(fMAX3) as measured (see note 13 above) minus tS.
15. This specification is guaranteed for all device outputs changing state
in a given access cycle.

4-37

•

~

PLD C 20Gl0B/PLD C 20Gl0
~~~CKR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=
Parameter

Output Waveform-Measurement Level

Vx

tPXZ( -)

1.5V

tpXZ( +)

2.6V

at" ~r:

VOH

D.,V

VOL

Vthc

tpZX( +)

o.,v

Vx

tpZX( - )

Vthc

tER( -)

1.5V

Vthc

n n

rr

o.,v

rt

Vx

o·tv

rr

Vx

o.,v ~

Vthc

tEA( -)

0053-43
VOH
0053-44

VOL 0053-45

o.}v ~

VOH

VOL

tEA( +)

rr

otv ~

Vx

2.6V

tER( +)

Vx 0053-42
Vx

Vx 0053-42
Vx
0053-43
VOH
0053-44

VOL 0053-45

AC Test Loads and Waveforms (Commercial)
R1 23sn
(319n MIL)

R1 23s.n

(319n MIL)

OUTP~~

R2

50pF
INCLUDING
JIGAND
SCOPE

I

-=

-

5pF

I

3.0 V-----::.I!:-=--~:L
R2

170n
(236n MIL)

GND--"""'"I-

-=-=

:s;; 5ns

0053-6

0053-6

Figure 11a
Equivalent to:

OUTP~~

170n
(236n. MIL)

INPUT PULSES

Figure 12

Figure 11b
Equivalent to:

THEVENIN EQUIVALENT (Commercial)

OUTPUT

THEVENIN EQUIVALENT (Military)
13SD.

99D.
~2.08V=Vthc

OUTPUT

0053-7

~2.13V=Vthm

0053-24

Switching Waveforms
INPUTS, 110.
REGISTERED

FEEDBACK

cp

OUTPUTS:
REGISTERED

--..J~~~_--~--_ltttltt'-~tl.

_______~__~~___

-===============J~~~~~~l===========================JHH~rt~Ht=

OUTPUTS: _

COMBINATORIAL

Note:
For more information regarding PLD devices, refer to the Application Brief in the Appendix.

4-38

0053-9

~RESS

PLD C 20G10B/PLD C 20G10

~nEMlCONDUCTOR =======================~~~~~~~~
Functional Logic Diagram PLD C 20GIO

...v

INPUT LINES
P, pJ;
Po Pz

0

OE
0

,

•

12

"

20

2<

2.

32

3.

-

"
::B:I ")--

OUTPUT

CELL

~

-o-t

I-

A

I>
""'--

OE
0

3:E!J-2.~

~

)...~

OE
0

-o-t

"1-

OE
0

~

....,

,~

.A

m=;=

OE
0

6,~

A

:B::I

~

7.~

OUTPUT

OllTl'UT

I>

CELL

=
OUTPUT
CELL

I>

~
OUTPUT

I>

CELL.

OUTPUT

I>CELL

~

OE
0

rl

.....

r1

v-

I
I

11 I
rJ... I
.....

0

20

19

18

17

-

13

16

=I

o-t

~

A

I>

v

I

.....

J

15

'--

OE
0

OUTPUT

10 ~
~

21

14

OUTPUT

t:> CELL

OUTPUT
CELL

11

22

A

OE

9

I

23

~
==
rl
W~
J

IDs=I

8~

.....

I>

~

OE
0

~

== 11
-

3:Ef

7

~

CELL

A

:§:P4.-t:::

CELL

t1- I>

OE
0

3 ~.

OUTPUT

h1

:B=1

..
..

I> CELL

.A

-""-

~

0053-23

4-39

~

PLD C 20Gl0B/PLD C 20Gl0

~~~~=============================================================
The "TOP TEST" and "BOTTOM TEST" feature, allow
Erasure Characteristics

connection of all input terms to either pin 23 or 13. These
locations may be programmed and subsequently exercised
in the "TOP TEST" and "BOTTOM TEST" mode. Like
the Phantom array above, this feature has no effect in the
normal mode of operation. Cells in the PHANTOM ARRAY, TOP TEST, and BOTTOM TEST areas are programmed at Cypress during the manufacturing operation,
and they therefore will be programmed when received in a
non-windowed package by the user. Consequently, the user
will normally have no need to program these cells.
The architecture bits Co, C, and C2 are used to configure
each programmable output cell individually. Co selects output polarity, C, selects the combinatorial or registered
mode of operation and C2 selects the source of output enable. If the registered mode of operation is selected, the
feedback path is automatically selected to be from the register. In the combinatorial mode the feedback path is automatically selected to be from the I/O pin. In this combinatorial mode, the output from the array may be fed into the
array or if the output is deselected using the output enable
product term the pin may be used as an external input.
There is not a mode where the I/O pin may be used as a
combinatorial output or an input pin, while the register is
used as a state register. The architecture bits are programmed as a separate item during normal programming.
An I/O pin is configured to be an input by programming
the output cell into a combinatorial mode and disabling the
ouput with the output enable product term.

Wavelengths of light less than 4000 Angstroms begin to
erase the PLD C 20G 10. For this reason, an opaque label
should be placed over the window if the device is exposed
to sunlight or fluorescent lighting for extended periods of
time. In addition, high ambient light levels can create holeelectron pairs which may cause "blank" check failures or
"verify errors" when programming "windowed" parts.
This phenomenon can be avoided by use of an opaque label
over the window during programming in high ambient
light environments.
The recommended dose for erasure is ultraviolet light with
a wavelength of 2537 Angstroms for a minimum dose (UV
intensity X exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating, the exposure
would be approximately 35 minutes. The PLD C 200 10
needs to be placed within 1 inch of the lamp during erasure. Permanent damage may result if the device is exposed
to high intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.

Device Programming
The PLD C 20G 10 can be programmed on inexpensive
conventional PROM/EPROM programmers with appropriate personality or socket adapters and the CY3000
QuickPro programmer. Once the PLD device is programmed, one additional location can be programmed to
prohibit logic pattern verification. This security feature
gives the user additional protection to safeguard his proprietary logic. This feature is highly reliable and due to
EPROM technology it is impossible to visually read the
programmed cell locations.
The PLD C 20GI0 has multiple programmable functions.
In addition to the normal array, a "PHANTOM" array,
"TOP and BOTTOM TEST" and a "SECURITY" feature
are programmable. The PLD C 20GI0 security mechanism, when invoked, prevents access to the "NORMAL"
and "TOP/BOTTOM TEST" array. The "PHANTOM"
array feature is still accessible, allowing programming and
verification of the pattern in the "PHANTOM" array.
Functional operation of all other features is allowed regardless of the state of the "SECURITY BIT". In addition,
the device contains 10 programmable output cells which
are programmed to configure the device functionality for
each specific application.
The logic array is divided into a "NORMAL" array and a
"PHANTOM" array. The normal array is used to configure the device to perform a specific function as required by
the user, and the phantom array is provided as a test array
for Cypress' testing the device prior to user programming
thus assuring a reliable, thoroughly tested product. The
"PHANTOM" array contains four additional columns
connected to input pins 2 (TRUE), 7 (INVERTING), 10
(TRUE) and 11 (TRUE). These inputs may be programmed to be connected to all normal product terms.
This allows all sense amplifiers and programmable output
cells to be exercised for both functionality and performance
after assembly and prior to shipment. These features are in
addition to the normal array. They do not affect normal
operation, allowing the user full programming of the normal array, while allowing the device to be fully tested.

Pinout
The PLD C 20GI0 PROGRAMMING pinout is shown in
Figure 13. In the Programming pinout configuration, the
device may be programmed and verified for the NORMAL
mode of operation and also programmed, verified and operated in PHANTOM and TEST modes. These special
modes of operation are achieved through the use of supervoltages applied to certain pins. Care should be exercised
when entering and exiting these modes, paying specific attention to both the operating modes as specified in Table 1
and the sequencing of the supervoltages as shown in the
timing diagrams.

Programming Pinout
Vee

Vpp

AO

DO

A1

01
02
03
04
05
06
07
08
09

A2
A3

A4

A5

A9

PGM,/Vf
0053-27

Figure 13

4-40

~

PLD C 20GIOB/PLD C 20GIO

~~~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
These provide NORMAL operation, PHANTOM operation, TOP TEST, BOTTOM TEST and a register preload
feature for testing.

Programming Algorithm
With the exception of the Security bit, all arrays are programmed in a similar manner. The data to be programmed
is represented by a "I" or "0" on the I/O pins. A "I"
indicates that an unprogrammed location is to be programmed and a "0" indicates that an unprogrammed location is to remain unprogrammed. All locations to be programmed are addressed as row and column locations. Table 2 "Operating Modes" along with Tables 3 through 6
provide the specific address for each addressed location to
be programmed along with mode selection information for
both programming and operation in the "PHANTOM"
and "TEST" modes.
When programming the security bit, a supervoltage on pin
3 is used as data with a programming pulse on pin 13.
Verification is controlled with a supervoltage on pins 4 and
the data out on pin 3.

In the normal operating mode, all signals are TTL levels
and the device functions as it is internally programmed in
the NORMAL array. In the PHANTOM mode of operation, the device operates logically as a function of the contents of the PHANTOM array. In this mode pins 2,10 &
11 are non-inverting inputs and pin 7 is an inverting input.
The programmable output cells function as they are programmed for normal operation. If the programmable output celIs have not yet been programmed, they are in a registered inverting configuration. The PHANTOM mode is
invoked by placing a supervoltage Vpp on pin 6. Care
should be exercised when entering and leaving this mode
that the supervoltage is applied no sooner than 20 ms after
the Vee is stable, and removed a minimum of 20 ms before
Vee is removed.

20GIO JEDEC Map

TOP and BOTTOM TEST

The 200 10 JEDEC Map is organized as follows: the
EPROM fuses for the product terms and input lines are
located between 0000 and 3959 (decimal). The architecture
bits are located between locations 3960 and 3989. Location
3960 is the Polarity Bit (CO), location 3961 is the Registered/Combinatorial Bit (C1), and location 3962 is the
Output Enable Bit (C2) for output pin 23. Locations 3963,
3964, and 3965 are the architecture bit locations for output
pin 22. This pattern repeats for output pins 21, 20, 19, 18,
17, 16, 15, and 14.

The TOP TEST and BOTTOM TEST modes are entered
and exited in the same manner, with the same concern for
power sequencing, but the supervoltage is applied to pins 9
& 10 respectively. In these modes an extra product term
controls an output pin. TOP TEST controls pin 23, and
BOTTOM TEST controls pin 14. These product terms are
controlled by the normal device inputs, and allow testing of
all input structures.

Operating Modes

Finally for testing of programmed functions, a preload feature allows any or all of the registers to be loaded with an
initial value for testing. This is accomplished by raising pin
8 to a supervoltage Vpp, which puts the output drivers in a
high impedance state. The data to be loaded is then placed
on the I/O pins ofthe device and is loaded into the registers on the positive edge of the clock on pin 1. A "0" on the
I/O pin preloads the register with a "0" and a "1" preloads
the register with a "1". The actual signal on the output pin
will be the inversion of the input data. The data on the I/O
pins is then removed, and pin 8 returned to a normal TTL
voltage. Again care should be exercised to power sequence
the device properly.

Preload

Table 2 describes the operating and programming modes of
the PLD C 20G 10. The majority of the programming
modes function with a PROGRAM, PROGRAM INHIBIT and PROGRAM VERIFY sequence. The exception is
the Security Program operation, which shows no program
inhibit function. Two timing diagrams are provided for
these two different methodologies of programming in Figures 15 & 16. Tables 3 through 6 are used as indicated to
provide the individual addresses of the various arrays and
cells to be programmed. There are 5 operating modes in
addition to the programming modes for the PAL C 22VIO.

4-41

II
•

~

PLD C 20GIOB/PLD C 20GIO

~r~~====================
Operating Modes
Table 2
Operating Modes

Feature
Main
Array
Product

Pin

PIn

PIn

PIn

PIn

Pin

PIn

Pin

Pin

PIn

Pin

Pin

Pin

Pin

1

2

3

4

5

6

7

8

9

10

11

13

14

17

Pin
20

Function
Program

Vpp

Program Inhibit

Vpp

Data In

VIHP

HighZ

VILP

Data Out

Program

Vpp

VIHP VUIP VIHP Vpp Vpp

Program Inhibit

Vpp

Program Verify

Program
Top Test,
Bottom Test Program Inhibit
Notes
Program Verify

Architecture Bits

Security
Bit

PAL
Mode
Operation

Phantom
Array
Product
Terms
Phantom
Output
Enable
Product
Terms

Table 4

Vpp

Program Verify[3] Vpp

Output
Enable
Product
Terms

Table 3

Pins
15,16,18,
19,21&22

HighZ

Vpp

VIHP VUIP VUIP Vpp VILP

Data Out

Vpp

VIHP VIHP VIHP VIHP Vpp

Vpp

Data
In

Data
In

Data
In

VIHP VIHP VIHP VIHP VIHP HighZ HighZ HighZ

Table 3

Data
VIHP VIHP VIHP VIHP VILP
Out

Vpp

Data
Out

Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP

Program Inhibit

Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP

Program Verify

Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP

Program

Vpp VILP Vpp VILP VILP VILP VILP VILP VILP VILP VILP Vpp VILP

Verify

Data
Vpp VILP VILP VILP VILP VILP VILP VILP VILP
VILP VILP
Out

VILP

VILP

Driven Outputs

I

I

I

I

I

I

I

I

I

I

VO

NA

NA

NA

Vpp

I

NA

NA

I

I

NA

Output

Top Test

I

I

I

I

I

I

I

I

Vpp

I

I

I

Bottom Test

I

I

I

I

I

I

I

I

I

Vpp

I

I

NA

NA

NA

NA

NA

Reg Preload

Notes NA

Program

Vpp VILP VILP

Program Inhibit

Vpp VILP VILP

Program Verify

Vpp VILP VILP

VILP Vpp

Program

Vpp VILP VILP

VILP Vpp VIHP VIHP VIHP Vpp Vpp

Program Inhibit

Vpp VILP VILP

Program Verify

Vpp VILP VIL

Table 6

VILP

VILP

I

Table 4

Data
Out

HighZ

I

VILP Vpp

Driven

Data Out

CP/I

Table 6

HighZ

Vpp VILP

CP/I

NA Vpp

HighZ

Data In

Normal

NA

Data
In

Vpp VIHP

Phantom

VILP Vpp

VILP

Data
Out

Vpp Vpp

Program

TableS

NA
Out

Out
NA

NA VILP

Data In

Vpp

Data In

VIHP

HighZ

VILP

Data Out
Data In

VILP Vpp VIHP VIHP VIHP Vpp VIHP

HighZ

VILP Vpp VIHP VIHP VIHP Vpp VILP

Data Out

Notes:
I. DATA IN and DATA OUT for programming Synchronous Set,
Asynchronous Reset, TOP TEST and BOTTOM TEST is pro-

23

Data In

VIHP VUIP VIHP Vpp VIHP

Table 3

Pin

2. The preload clock on pin I loads the Registers on a LOW going
HIGH transition.
3. It is necessary to toggle OE (Pin 13) HIGH during all address transitions while in the program verify/blank check mode.

grammed and verified on the following pins.
Pin 14 = BOTTOM TEST
Pin 17 = Synchronous Set
Pin 20 = Asynchronous Reset
Pin 23 = TOP TEST

4-42

Input Term Addresses
It provides the addressing for the 44 normal input term
columns which are connected with an EPROM transistor
to the product terms.

Table 3 is used during the programming and verification of
the main array, output enable, asynchronous reset, synchronous preset, TOP and BOTTOM TEST as shown in
Table 2.

Input Term Addresses
Table 3
Input
Term

Pin
2

Pin

3

Pin
4

Pin
5

Pin
6

Pin
7

0
1
2
3
4
5
6
7
8
9

VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP

VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP

VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP

VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP

VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP

VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP

10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

41
42
43

4-43

01

~

PLD C 20GI0B/PLD C 20GI0

,..,~~~==========================================================
Pin 7 is inverted, and the remaining 3 are normal non-inverting. This PHANTOM array allows the output structures to be tested. They are only present in PHANTOM
modes of operation.

Product Term Addresses
Table 4 is used for the programming of the "PHANTOM"
and normal array. It provides the addressing for the 8
product terms associated with each input.

Phantom Input Term Addresses

Product Term Addresses

Table 6

Table 4
Product

Term

Pin
8

Pin
9

Pin
10

Pin
11

0
I
2
3
4
5
6
7

VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP

VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP

VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP

VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP

Phantom
Input
Term
PO
PI
P2
P3

TableS

Output
Polarity
CO

VILP

VILP

Register/
Combinatorial
OutputCI

VIHP

VILP

Product Term!
Pin 13
Output Enable
C2

VILP

VIHP

VILP
VIHP
VILP
VIHP

VILP
VILP
VIHP
VIHP

The logical sequence to program the device is described in
detail in the flow chart below, and should be followed exactly for optimum intelligent programming that both minimizes programming time and realizes reliable programming. Particular attention should be paid to the application
of Vee prior to Vpp, and removal ofVpp prior to Vee. See
Figure 14 and Table 8 for specific timing and AC requirements. Notice that all programming is accomplished without switching Vpp on pin 1 and that after programming
and verifying all locations individually, the programmed
locations should be verified one fmal time.

Architecture Bit Addressing
Pin
10

Pin
S

Programming Flow Chart

Architecture Bit Addressing

Pin
9

4

The programming flow chart describes the sequence of operations for programming the NORMAL and PHANTOM
arrays, the NORMAL and PHANTOM output enable
product terms, the set and preset product terms, the Top
Test product term, the Bottom Test product term, and the
architecture bits. The exact sequencing and timing of the
signals is shown in the "Array Programming Timing Diagram".

Table 5 provides the addressing for the architecture bits
used to control the configuration of the individual Programmable Output Cells. In the unprogrammed state, the
Programmable Output Cells are in a registered, active low
or inverting configuration with output enable controlled
from the product term. They are programmed with a "I"
on the pin associated with the Programmable Output Cells
and the appropriate address as shown in Table 5. Each
architecture bit that is not to be programmed, requires a
"0" on the I/O pin associated with the Programmable Output Cells.

Architecture
Bit

Pin

The normal word programming cycle, programs and verifies a word at a time as shown in the programming flowchart, Figure 13 and timing diagram Figure 14. After all
locations are programmed, the flowchart requires a verify
of all words. There is no independent timing diagram for
this operation, rather Figure 14 also provides the correct
timing information for this operation. When performing
this verify only operation, eliminate the program portion of
the cycle but maintain the setup and hold timing relative to
the verify pulse. Under no circumstances should the verify
signal be held low and the addresses toggled.
Note that the overprogram pulse in step 10 of the programming flowchart is a variable, "4" times the initial value
when programming the NORMAL, PHANTOM, TOP
TEST, BOTTOM TEST and OUTPUT ENABLE product
terms and "8" times the initial value when programming
the ARCHITECTURE BITS.

Phantom Input Term Addressing
Phantom input terms are addressed as columns PO thru P3
and represent inputs from pins 2,7,10 and 11 respectively.

4-44

Programming Flowchart
START
Vee = 5.0V

Vpp = SEE NOTE 2

ADDRESS rlRST LOCATION,

Notes:

..

PLACE DATA TO BE PROGRA.... ED
ON THE I/o PINS

I. This value is "4" for programming
the NORMAL array, PHANTOM
array TOP TEST, BOTTOM TEST

...

X=O

and OUTPUT ENABLE PRODucr TERMS. The value is "8"
when programmingARCHITECTUREBITS.
2. Vpp Programming Voltage:
For 7C323B and 200 lOB = 12.SV
For 7C323 and 20010 = 13.SV.

PROGRA.. ONE PULSE
OF 0.4ms

X= X+ 1

X = 5?
NO
VERIFY ONE WORD
PASS
PROGRA.. ONE PULSE OF
«NOTE 1) • 0.4 • x) ma
YES

X=5

NO
YES
VERIFY ALL WORDS AT
Vccp = 5.5 VOLTS
PASS
GOOD DEVICE

Vpp

=o.OV
=

Vee O.OV
STOP
0053-28

Figure 14

4-45

Timing Diagrams
Programming timing diagrams are provided for two cases,
programming of all cells except the SECURITY BIT allCi
programming the SECURITY BIT.

Array
Programming the NORMAL and PHANTOM arrays and
output enables, reset, preset, architecture bits and the top/
bottom test features uses the timing diagram in Figure 15.
ADDRESS refers to all applicable information in Tables 2
through 6 that is not specifically referenced in the timing
diagram. DATA IN is provided on the I/O pins and

DATA OUT is verified on the same pins. A "I" (VIHP) on
an I/O pin causes the addressed location to be programmed. A "0" on the I/O pin leaves the addressed location to be unprogrammed. All setup hold and delay times
must be met, and'in particular the sequence of operations
should be strictly followed. During verify only operation it
.. is not acceptable to hold PGMIVFY low and sequence
addresses, as it violates address setup and hold times. Proper sciquencing of all power and supervoltages is essential, to
reliable programming of the device as improper sequencing
could result in device damage.

Programming Waveforms
VCCP
24
NOTE 1 VSS -

vee PIN

Vpp_

VPP PIN 1

ADDRESS
NOTE 2

V1HP
V1LPV1HP

DATA

-

V1LP-

PGM/W'i'
PIN 13

VIHP V1LP-

- -.....-----~

0053-29

Notes:
1. Power, Vpp & Vcc should not be cycled for each program/verify
cycle, but may remain static during programming,

2. For programming OE Product Terms & Architecture bits, Pin II
(A9) must go to Vpp and satisfy TAS and TAN.

Figure 15

4-46

~

PLD C 20GIOB/PLD C 20GIO

~r~~===================
Security Cell
same pin. A "0" on pin 3 indicates that the security bit has
been programmed, and a "I" indicates that security bit has
not been programmed. Security is programmed with a single 50 ms pulse on pin 13. A supervoltage on pin 4 is used
to verify security after Vpp has been removed from pin 1.

The security cell is programmed independently per the timing diagram in Figure 16, and the information in Table 2.
Note again that proper sequencing of power and programming signals is required. Data in is represented as a supervoltage on pin 3 and verified as a TTL signal output on the

Programming Waveforms Security Cell
Vcc PIN 24

VccP

-

VSS -

-J

~"~

Tp

____________ TP ____________

~jf--~

Vpp_
Vpp PIN 1
VSS-

Top

Vpp _
DATA PIN 3

VIHP VILP-

Vpp_
PGt.l
PIN 13
VILP _
\+------TOV
Vpp_
SECURITY
VFY
PIN4
VILP -

0053-30

Figure 16

4-47

~~=========================P=L=D==C=2=OG==10=B=/P==L=D=C=2=O=G==10
DC Programming Parameters TA

= 2SoC

Table 7
Parameter

Description

Min.

Max.

Units

Vpp for PLD C 20GIOB
and for CG7C323B·A

Programming Voltage

12.0

13.0

Volts

Vpp for PLD C 20G 10
and for CG7C323·A

Programming Voltage

13.0

14.0

Volts

Veep

Supply Voltage
During Programming

4.75

5.25

Volts

VIHP

Input HIGH Voltage
During Programming

3.0

Veep

Volts

VILP

Input LOW Voltage
During Programming

-3.0

0.4

Volts

VOH

Output HIGH Voltage

2.4

VOL

Output LOW Voltage

0.4

Volts

Ipp

Programming
Supply Current

40

mA

Volts

AC Programming Parameters
TableS
Parameter

Description

Tp

Delay to Programming
Voltage

TOp

Min.

Max.

Units

20

ms

Delay to Program

I

p.s

THP

Hold from Program
or Verify

1

p.s

TR,F

Vpp Rise & Fall Time

50

ns

TAS

Address Setup Time

I

p.s

TAH

Address Hold Time

I

p.s

Tos

Data Setup Time

I

p.s

TOH

Data Hold Time

I

Tpp

Programming Pulsewidth

0.4

Tspp

Programming Pulsewidth
for Security

50

ms

Tov

Delay from Program
to Verify

2

p.s

Tvo

Delay to Data Out

Typ

Verify Pulse Width

Toz

Verify to High Z

p.s
10

I
2

p.s
p.s

I

4·48

ms

p.s

~

PLD C 20GIOB/PLD C 20GIO

~r~~===================
Typical DC and AC Characteristics
NORMAUZED SUPPLY CURRENT
SUPPLY VOLTAGE

NORMALIZED PROPAGATION
DELAY VI. SUPPLY VOLTAGE

NORMAUZED SUPPLY CURRENT
AMBIENT TEMPERATURE

VB.

VB.

!.2

j

til
N

~

ii
s.o

u

O··...
!:------:zsl.:-----::!.zs

'.0

SUPPLY VOLTAGE CVI

..• .............
1.0

NORMALIZED PROPAGATION DELAY
TEMPERATURE

0.8
4.0

s.o

NORMAUZED SETUP TIME
!.2

1'.0

!
C

.0.0

V

':;

l!l
5.0

V

0.00

...

V"""
./

.............

IDD

IDD

0.1
4.0

._

CAPACITANCE CpFI

U

"""

..........

5.5

5.0

6.0

IUP'LV VOLTAGE IV)

NORMAUZED CLOCK
TO OUTPUT
TIME VB. TEMPERATURE

NORMAUZED CLOCK TO OUTPUT
TIME VB. SUPPLY VOLTAGE

•.• ,--......--,....--r----,

1.3,----...,..------,

'-

0.'

«ID

200

..... ,ENT TEMI'IRATURE C'CI

NORMAUZED SETUP TIME
VB. TEMPERATURE

6.0

VB. SUPPLY VOLTAGE

20.0

j

5.5

SUfJPLYVOLTAGE (V)

DELTA PROPAGATION TIME
VB. OUTPUT LOADING

1.3

""""

0.9

AMBIENT TEMPERATURE C'CI

VB.

'-

!.4

1.3

§
0

'.2

:::;

...

~

c
:.
0:

i

..... ,ENT TEMPERATURE C"CI

.20

V ...

j

C

I

/

OM

0

s.o

L

./

.0.0

~

V

0.00

i

§

200

«ID

IDD

CAPACITANCE Coi'l

IDD

._

OUTPUT SOURCE CURRENT
VOLTAGE

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

VB.

20.0

1'.0

AMIII ENT TEMPERATURE I·C)

SUPPLY VOLTAGE IVI

DELTA CLOCK TO OUTPUT TIME
VB. OUTPUT LOADING

!

'.0

/
41
3D
II

/

/

-

'" I\.

"-

~!"..J;~V-

L

o II
0.0

L

VI.

• .0

2.0

OUTPUT VOLT AGE IVI

4.0

'""-I"

. . . r--..

!.D

2.0

3.0

.....
4.0

OUTPUT VOLTAGE IVI

0053-31

4·49

~ .
PLD C 20G10B/PLD C 20G10
~~~aoR================================================================
Ordering Information
tpn

ts

teo

Icc

(ns)

(ns)

(ns)

(mA)

15

12

10

70

20

20

25

25

30

35

40

12

15

15

18

20

30

35

12

15

15

15

20

25

25

70

100

55

100

80

55

80

Package

Ordering Code
PLO C 200 lOB-15PC/PI

P13

PLO C 20GlOB-15WC/WI

W14

PLO C 200 10B-15JC/JI'

J64

CG7C323B-AI5JC/JI[!6]

J64

PLO C 200 IOB-20PC/PI

P13

PLO C 200 IOB-20WC/WI

WI4

PLO C 200 lOB-20JC/JI

J64

CG7C323B-A2OJC/JI[16]

J64

PLO C 200 lOB-200MB

014

PLO C 20GlOB-20WMB

W14

PLO C 200 lOB-20LMB

L64

PLO C 20G 1O-25PC/PI

P13

PLO C 20G 1O-25WC/WI

WI4

PLO C 20GlO-25JC/Jl

J64

CG7C323-A25JC/Jl [!6]

J64

PLO C 20GlOB-250MB

014

PLO C 20GlOB-25WMB

W14

PLO C 20G lOB-25LMB

L64

PLO C 20Gl0-300MB

014

PLO C 20G 1O-30WMB

WI4

PLO C 200 1O-30LMB

L64

PLO C 20GI0-35PC/PI

P13

PLO C 20GlO-35WC/wI

WI4

PLO C 200 1O-35JC/JI

J64

CG7C323-A35JC/JI[16]

J64

PLO C 20G 10-400MB

014

PLO C 2oo10-40WMB

W14

PLO C 20G lO-40LMB

L64

Operating
Range
Commercial!
Industrial

Commercial!
Industrial

Military

Commercial!
Industrial

Military

Military

Commercial!
Industrial

Military

Note:
16. The CG7C323 is the PLDC20010 packaged in the JEDEC compatible 28 pin PLCC pioout. Pin function and
pin order is identical for both PLCC pinouts. The principle difference is io the location of the "no connect" or
NCpins.

4-50

~
PLD C 20Gl0B/PLD C 20Gl0
~~~~R~~~~~~~~~~~~~~~~~~~~~~~==~~~~~===
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

VIL

1,2,3

IIX

1,2,3

Vpp

1,2,3

Icc

1,2,3

Ioz

1,2,3

II

Switching Characteristics
Parameters

Subgroups

tpD

7,8,9,10,11

tpzx

7,8,9,10,11

teo

7,8,9,10,11

ts

7,8,9,10,11

tH

7,8,9,10,11

Document #: 38-00019-C

4-51

PRELIMINARY

CYPRESS
SEMICONDUCTOR

Fleprogrannnnable
Asynchronous CMOS
Logic Device

Features
• Advanced user programmable
macro cell
• CMOS EPROM technology for
reprogrammability
• Up to 20 input terms

• 10 programmable I/O macro
cells
• Output macro cell programmable
as combinatorial or
asynchronous D-type registered
output
• Product term control of register
clock, reset and set and output
enable
• Register preload and power-up
reset
• Four uncommitted product terms
per output macro cell

PLDC20RA10

Functional Description
• Fast
- Commercial
tpD = 20 ns

teo = 20 us

tsu
-

= 10 ns
Military
tpD = 2S us
teo = 25 us

tsu = 15 us
• Low power
- ICC max = 80 mA
Commercial
- Icc max = 100 mA
Military
• High reliability
- Proven EPROM technology
- > 2001V input protection
- 100% programming and
functional testing
• Windowed DIP, windowed LCC,
DIP, LCC, PLCC available

The Cypress PLD C 20RA1O is a high
performance, second generation programmable logic device employing a
flexible macro cell structure which allows any individual output to be configured independently as a combinatorial output or as a fully asynchronous
D-type registered output.
The Cypress PLD C 20RA1O provides
lower power operation with superior
speed performance than functionally
equivalent bipolar devices through the
use of high performance 0.8 micron
CMOS manufacturing technology.
The PLD C 20RA1O is packaged in a
24 pin 300 mil molded DIP, a 300 mil
windowed cerdip, and a 28 lead square
leadless chip carrier and provides up to
20 inputs and 10 outputs. When the
windowed device is exposed UV light,
the 20RAIO is erased and then can be
reprogrammed.

Block Diagram and DIP Pinout

PROGRAMWABLE
AND ARRAY
(BOX"')

Vee
D118-1

4-52

~
PRELIMINARY PLDC20RAIO
~r~========~=======
Macro Cell Architecture
Figure 1 illustrates the architecture of the 20RAI0 macro

mitted product terms of each programmable I/O macro
cell that has been configured as an output.

cell. The cell dedicates three product terms for fully asynchronous control of the register set, reset and clock functions, as well as, one term for control of the output enable
function.

An I/O cell is programmed as an input by tying the output
enable pin, pin 13, HIGH or by programming the output
enable product term to provide a LOW, thereby disabling
the output buffer, for all possible input combinations.

The output enable product term output is "AND'ed" with
the input from pin 13 to allow either product t~rm.or hard
wired external control of the output or a comblnatlon of
control from both sources. If product term only control is
selected it is automatically chosen for all outputs since, for
this cas~, the external output enable pin must be tied LOW.
The active polarity of each output may be programmed
independently for each output cell and is subsequently
fixed. Figure 2 illustrates the output enable options available.

When utilizing the I/O macro cell as an output, the input
path functions as a feedback path allowing the output signal to be fed back as an input to the product term array.
When the output cell is configured as a registered output,
this feed back path may be used to feed back the current
output state to the device inputs to provide current state
control of the next output state as required for state machine implementation.

Preload and Power-up Reset

When an I/O cell is configured as an output, combinatorial
only capability may be selected by forcing the set and reset
product term outputs to be HIGH under all input conditions. This is achieved by programming all input term programming cells for these two product terms. Figure 3 illustrates the available output configuration options.

Functional testability of programmed devices is enhanced
by inclusion of register preload capab!lity which ~Iows the
state of each register to be set by loading each regIster from
an external source prior to exercising the device. Testing of
complex state machine designs is simplified by the ability
to load an arbitrary state without cycling through long test
vector sequences to reach the desired state. Recovery from
illegal states can be verified by loadin.g illegal s~ates .and
observing recovery. Preload of a particular register IS !lCcomplished by impressing the desired state on the register
output pin and lowering the signal level on the prel?ad
control pin (pin 1) to a logic LOW level. If the speCified
preload set up, hold and pulse width minimums .have been
observed, the desired state is loaded into the regIster. To
insure predictable system initialization, all registers are .
preset to a logic LOW state upon power up, thereby setting
the active LOW outputs to a logic HIGH.

An additional four uncommitted product terms are provided in each output macro cell as resources for creation of
user defined logic functions.

Programmable I/O
Because any of the 10 I/O pins may be selected as a input,
the device input configuration programmed by the user
may vary from a total of nine programmable plus ten dedicated inputs (a total of nineteen inputs) and one output
down to a ten input, ten output configuration with all ten
programmable I/O cells configured as outputs. Each input
pin available in a given configuration is available as an
input to the four control product terms and four uncom-

I/O

o

S

PL

PIN

Q
P

R

PL

OE

Figure 1. PLD C 20RAI0 Macro Cell

4-53

0118-4

4

~

PRELIMINARY

PLDC20RA10

~r~~===================
Output Always Enabled

Programmable

0118-13

0118-14

Hard·Wired

Combination of
Programmable and Hard·Wired

0118-15

0118-16

Figure 2. Four Possible Output Enable Alternatives for tbe PLD C 2ORA10
Registered!Active LOW

Combinatorial!Active LOW

0116-16

0118-17

Registered!Active HIGH

CombinatoriaIIActive HIGH

0118-20

0118-19

Figure 3. Four Possible Macro Cell Configurations for the PLD C 2ORA10

4-54

~

PRELIMINARY

PLDC20RA10

~r~~===================
Selection Guide
Generic
Part Number

Com

tpDns

20RAIO-20

20

-

10

20RAIO-25

-

25

20RAIO-30

30

-

20RAIO-35

-

35

tsuns

Mil

Ice rnA

teons
Com

Mil

Com

-

20

-

80

-

-

15

-

25

-

100

15

-

30

-

80

-

-

20

-

35

-

100

Com

Mil

Mil

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150°C

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latchup Current .......................... > 200 rnA

Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -0.5Vto +7.0V

DC Programming Voltage ...................... l3.0V

Operating Range

DC Voltage Applied to Outputs

in High Z State ...................... -0.5V to + 7.0V

Range

DC Input Voltage ................... -3.0Vto +7.0V
Commercial

Output Current into Outputs (LOW) ............ 16 rnA

Military[S]

Ambient
Temperature

Vee

OOCto + 75°C

5V ±IO%

- 55°C to

+ 125°C

5V ±IO%

Electrical Characteristics Over Operating Range[6]
Description

Parameters
VOH

Output HIGH Voltage

Min.

Test Conditions
Vee = Min.,
VIN = VIH or VIL

IOH

=
=

IOL

= 8mA

IOH

-3.2mA

COM'L

-2mA

MIL

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs U]

VIL

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputs U]

IIX

Input Leakage Current

VSS

Ioz

Output Leakage Current

Vee

Ise

Output Short Circuit Current

Vee

VIN ~ Vee, Vee = Max.
= Max., Vss ~ VOUT ~ Vee
= Max., VOUT = 0.5V[2]

lee

Power Supply Current

Vee

= Max., VIN = GND Outputs Open

Max.

Units

2.4

V
0.5

V

0.8

V

-10

10

p.A

-40

40

p.A

-30

-90

rnA

COM'L

80

rnA

MIL

100

rnA

~

2.0

V

Capacitance [3]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions

= 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz

VIN

Min.

Max.
5
8

Units
pF

Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
3. Tested initially and after any design or process changes that may
affect these parameters.

4. Figure 4a test load used for all parameters except tEA, tER, tpzx and
tpxz. Figure 4b test load used for tEA. tER. tpzx and tpxz.
S. TA is the "instant on" case temperature.
6. See the last page of this specification for Group A subgroup testing
information.
7. The parameters tER and tpxz are measured as the delay from the
input disable logic threshold transition to VOH - O.SV for an enabled
HIGH output or VOL + O.SV for an enabled LOW output. Please see
Table 1 for waveforms and measurement reference levels.

4-55

~
PRELIMINARY PLDC20RA10
~~~~============================================================;
Switching Characteristics PLD C 20RA10 Over Operating Range[4, 6, 71
MUitary

Commercial
Parameters

-20

Description

Max.

Min.

-25

-30
Min.

Max.

Min.

-35

Max.

Min.

Units

Max.

tpD

Input or Feedback to
Non-Registered Output

20

30

25

35

ns

tEA

Input to Output Enable
Input to Output Disable

tpzx

Pin 13 to Output Enable

tpxz

Pin 13 to Output Disable

teo

Clock to Output

25
25
15
15
20

30
30
20
20
30

30
30
20
20
25

35
35
25
25
35

ns

tER

15
5
45
20
20
22.2

15
0

20
5
55
25
25
18.1

ns
ns

ns
ns

ns

tsu

Input or Feedback Setup Time

tH
tp

Hold Time
Clock Period

tWH

Clock Width HIGH

tWL

Clock Width LOW

fMAX

Maximum Frequency

ts

Input to Asynchronous Set

tR

Input to Asynchronous Reset

tAR

Asynchronous Set/Reset
Recovery Time

20

30

25

35

ns

twp

Preload Pulse Width
Preload Hold Time

35
25
25

30
30

ns

tHP

35
25
25

ns

Preload Setup Time

30
20
20

40

tsup

10

0
30
13
13
33.3
20
25

40

18
18
25.0
35

ns
ns
ns
ns
MHz

25
30

40

40
45

ns

ns

ns

AC Test Loads and Waveforms (Commercial)
Rl,4574

OUTP:::===:~{4:7"'0_NA~_m-:.I..,I)+

I

OUTP::~{470A

IS

R2
270A
_(3194 mil)

pF

_

--

-

Figure 4a
Equivalent to:

3~V------~~=-----~

mil)

R2
270A
(319A mil)

50 pF

Including Jig
and Scope _

INPUT PULSES

Rl,4S7A

GND---...:I,

0118-7

Figure 5

0118-6

Figure 4b
Equivalent to:

THEVENIN EQUIVALENT (Commercial)

THEVENIN EQUIVALENT (Military)

1904

1704

OUTPUT~1.86V=Vthc

OUTPUT~2.02V=Vthm

0118-8

0118-9

LCC and PLCC Pinouts
o _

go
.£'.r.9I... >~~
4' 3' 2' f'i:i8 27 28
... !l

: •• :

.!'.r.9I~ ,.!l~~

NC

5

25

1/02

13
14

24
23

1/03
1/04

~

6
7
8

Is

9

21
20

1/02
1/03
1/04
1/05
1/08

2~~5

10
NC 11

1/08

1/07
19 NC

I.

12 13 14 15 16 17 IS
~.!!'.!t'

1lI1~

>

1/07
NC

~

....

~~

0118-21

0118-22

4-'6

~

PRELIMINARY

PLDC20RAIO

~~~~R================================================================
Table 1
Parameter

Output Waveform-Measurement Level

Vx
1.5V

tpxz(-)

VOH

~t

o·tv

7't

2.6V

tpxz(+)

O'fV

VOL

tpzx(+)

Vthc
O}V

Vx

tpzx(-)

1:

0~5V ~t

Vthc
Vx

l.5V

tER(-)

~

o·tv

VOH

2.6V

tER(+)

tEA(+)

Vthc
O}V

Vx

tEA(-)

1:

O'fV

VOL

7't

o~~ ~t

Vthc
Vx

Vx 0118-23
Vx

0118-24
VOH

0118-25

VOL 0118-26

Vx 0118-23
Vx
0118-24
VOH

0118-25

VOL 0118-26

Switching Waveforms

_-'I'''''''__

INPUTS, REGISTERED -_~_-""'\1~~~""'-------""""\"""""""\"""--FEEDBACK
_ _ _ _ _ _ _....J'I'-....J'I'-_ __
-'fv.lool.lo'-lo~'''''

CP _ _ _-'1

ASYNCHRONOUS
sn

_ _ _ _+-___

_+~

ASYNCHRONOUS

REsn _ _ _ _+-____+--11------'1

REGISTERED ----~~---+-~~It_---~-~_Jmlr_..;.;.OUWUTS _ _ _ _.u~
_+-~~~---~--~

__

COMBINATORIAL
OUWUTS --------""""\mllW-----.....;;;;..~_JnIr_..;.;.________
_______
__
....J~~

~-~~

~

PIN 13 OUWUT
ENABLE (01:)

COMBINATORIAL
OUTPUTS
REOISTEREDAND

~PEzE~
:==============J-~-4e-t====:

- -------------------------

0118-10

Preload Switching Waveforms

~~~:~ _____X_X_[__ls_uPgt:
PIN 1
PRELOAD CLOCK (Pr)

------------

IWI'

4·57

0118-12

II

~

PRELIMINARY

PLDC20RAIO

~~~UcroR================================================
Functional Logic Diagram PLD C 20RAIO
I-.

....

0

•

~D-i

15

16

~D-i

"

,.

~cr.-i

5 ....

~D-.i

39

"

~D-.i

"
"

~D-i

"

"

~D-.i

"
....

20

PL

• p

19

PL

• p

18

PL

• p

17

PL

....

8 I-.

• p

16

PL

• p

A

"

~

71

....

~D-~

79

....

....

03478111215161920232427283132353639

15

PL

• p

A

72

11

• p

....

7-1':::

21

PL

....

6 ....

10

• p

A

"

22

PL

....

....

"

9

• p

....

3 I-.

23

PL

....

31-.

4

D~
D~
D~
D~
D~
D~
D~
D~
#rhi
D~
0~

~D-i

7

14

PL

•

P

4

13
0118-11

4-58

Ordering Information
Icc

tpD

tsu

(os)

(ns)

teo

(mA)

80

20

10

20

100

25

15

25

(ns)

80

30

15

30

100

35

20

35

Ordering Code
PLO C 20RAI0-20PC
PLO C 20RAI0-20WC

Package

Operating Range

P13
W14

Commercial

PLO C 20RAIO-20JC

J64

PLO C 20RAIO-250MB
PLO C 20RAIO-25WMB

014
W14

PLO C 20RAI0-25LMB
PLO C 20RAI0-25QMB

L64
Q64

PLO C 20RAI0-30PC
PLO C 20RAIO-30WC

P13
W14

PLO C 20RAI0-30JC

J64

PLO C 20RAIO-350MB
PLO C 20RAIO-35WMB

014
W14

PLO C 20RAIO-35LMB
PLO C 20RAIO-35QMB

Q64

4-59

L64

Military

Commercial

Military

•

~
PRELIMINARY
PLDC20RAIO
,..,~~~========================================================~
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

VIL

1,2,3

IIX

1,2,3

IOZ

1,2,3

Icc

1,2,3

Switching Characteristics
Parameters

Subgroups

tpn

9,10,11

tpzx

9,10,11

teo

9,10,11

tsu

9,10,11

1M

9,10,11

Document #: 38-00073-A

4-60

PAL C 22VIOB/PAL C 22VIO

CYPRESS
SEMICONDUCTOR

Reprogrammable CMOS
PAL® Device
Functional Description

Features
• Advanced second generation
PAL architecture
• Low power
- 55 mA max "L"
- 90 mA max standard
- 120 rnA max military
• CMOS EPROM technology for
reprogranunability
• Variable product terms
- 2 X (8 tbru 16) product
terms
• User programmable macro cell
- Output polarity control
- Individually selectable for
registered or combinatorial
operation
- "IS" commercial & industrial
10 ns teo
10 ns ts
15 ns tpD
50 MHz

-

"20" military
15 ns teo
17 ns ts
20 ns tpD
31 MHz

The Cypress PAL C 22VlO is a CMOS
second generation Programmable Logic Array device. It is implemented with
the familiar sum-of-products (ANDOR) logic structure and a new concept,
the "Programmable Macro Cell".

• Up to 22 input terms and 10
outputs
• Enhanced test features
- Phantom array
- Top Test
- Bottom Test
- Preload
• High reliability
- Proven EPROM technology
- > 2000V input protection
- 100% programming and
functional testing
• Windowed DIP, windowed LCC,
DIP, LCC, PLCC available

The PAL C 22VlO is executed in a 24
pin 300 mil molded DIP, a 300 mil
windowed Cerdip, a 28 lead square ceramic leadless chip carrier, a 28 lead
square plastic leaded chip carrier and
provides up to 22 inputs and 10 outputs. When the windowed CERDIP is
exposed to UV light, the 22VlO is
erased and then can be reprogrammed.
The Programmable Macro Cell provides the capability of defining the architecture of each output individually.
Each of the 10 potential outputs may
be specified to be "REGISTERED" or
"COMBINATORIAL". Polarity of

PAL" i. a registered trademark of Monolithic Memories Inc.

Logic Symbol and Pinout

0023-1

--~~~~~

Lee and PLee Pinout

15
16
I 7
NCB
I 9
I 10
I

4 3 21;1282726
-L,J
251/02
241/03
23 I/O..
22Ne
21 1/05
20 I/Os

1"213141516171~9

1/07

--;~-~~
0023-10

4-61

II

~
PAL C 22VIOB/PAL C22VIO
~~~~aoR================================================================
Functional Description (Continued)

each output may also be individually selected allowing
complete flexibility of output configuration. Further configurability is provided through " ARRAY" configurable
"OUTPUT ENABLE" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on
an individual basis or alternately used as a combination
VO controlled by the programmable array.

registered mode of operation, the output of the register is
fed back into the array providing current status information to the array. This information is available for establishing the next result in applications such as control-statemachines. In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present
on the I/O pin is made available to the array. The flexibility provided by both programmable macro cell product
term control of the outputs and variable product terms
allows a significant gain in functional density through the
use of programmable logic.

The PAL C 22VI0 features a "VARIABLE PRODUCT
TERM" architecture. There are 5 pairs of product terms
beginning at 8 product terms per output and incrementing
by 2 to 16 product terms per output. By providing this
variable structure the PAL C 22V1O is optimized to the
configurations found in a majority of applications without
creating devices that burden the product term structures
with unuseable product terms and lower performance.

Along with this increase in functional density, the Cypress
PAL C 22VI0 provides lower power operation thru the use
of CMOS technology, increased testability with a register
preload feature and guaranteed AC performance through
the use of a phantom array. This phantom array (PO-P3)
and the "TOP TEST" and "BOTTOM TEST" features allow the 22V1O to be programmed with a test pattern and
tested prior to shipment for full AC specifications without
using any of the functionality of the device specified for the
product application. In addition, this same phantom array
may be used to test the PAL C 22VI0 at incoming inspection before committing the device to a specific function
through programming. PRELOAD facilitates testing programmed devices by loading initial values into the registers.

Additional features of the Cypress PAL C 22VI0 include a
synchronous PRESET and an asynchronous RESET product term. These product terms are common to all MACRO
CELLS eliminating the need to dedicate standard product
terms for initialization functions. The device automatically
resets on power-up.
The PAL C 22V1O featuring programmable macro cells
and variable product terms provides a device with the flexibility to implement logic functions in the 500 to 800 gate
array complexity. Since each of the 10 output pins may be
individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a
single output down to 12 inputs and 10 outputs are possi"
ble. The 10 potential outputs are enabled through the use
of product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and
an input through the selective use of individual product
terms associated with each output. Each of these outputs is
achieved through an individual programmable macro cell.
These macro cells are programmable to provide a combinatorial or registered inverting or non-inverting output. In a

Configuration Table 1
Registered/Combinatorial
Configuration

Cl

Co

0

0

Registered/Active Low

0

1

Registered/Active High

1

0

Combinatorial/Active Low

1

1

Combinatorial/Active High

Macrocell
~---------------------,

I
I
I
I

I
I
I

AR
OUTPUT

QI------4

}4------------4-~D

SE~ECT

totux

CP

SP

INPUT!
FEEDBACK
totUX
51

C1-------r----~------------------------~
Co-------+--------------------------------~
totACROCE~~

~--------------------~
4-62

0023-2

~

PALC22VIOB/PALC22VIO
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Selection Guide
Generic
Part Number

"L"

22VIOB-IS

ICClmA
ComJInd
90

-

22VIOB-20
22VIO-20

-

22VIO-2S
22VI0-30
22VI0-35

55

90

SS

90

90

-

22VIO·4O

Mil
120

tpDns
Com/Ind
IS

20

Mil
20

100
100

-

25
30

-

35

100

-

25

tsns
Com/lnd
10

Mil

-

17

12

-

15

18

-

30

40

-

20
30

teons
Com/Ind
10

Mil

-

-

15

12
15

15

-

20

25

25

-

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... - 65°C to + lSO"C
Ambient Temperature with
Power Applied .................... - SSoC to + 12SoC

DC Programming Voltage
PAL C 22VlOB ............................. 13.0V
PAL C 22VlO .............................. 14.0V

Supply Voltage to Ground Potential
(Pin 24 to Pin 12) .................... -O.SV to + 7.0V

Static Discharge Voltage ..................... >2oo1V
(per MIL-STD-883 Method 301S)

DC Voltage Applied to Outputs
in High Z State ...................... -O.SV to + 7.0V

Latchup Current .......................... > 200 rnA

Operating Range

DCInputVoltage ................... -3.0Vto +7.0V
Output Current into Outputs (Low) ............. 16 rnA

Range

UV Exposure ........................ 72S8 Wsec/cm2

Commercial
Military[7)
Industrial

Ambient
Temperature
O"Cto +7SOC
- SSOC to + 12SOC
-4O"C to + 8SoC

Vee
SV ±10%
SV ±IO%
SV ±10%

Electrical Characteristics Over Operating Range[6)
Parameters

Description
Vee = Min.,
VIN = VIR or VIL

VOH!

Output HIGH Voltage

VOR2

HIGH Level CMOS
Output Voltage[3)

Vee = Min.,
VIN = VIR or VIL

VOL

Output LOW Voltage

Vee = Min.,
VIN = VIR or VIL

VIR
VIL

Input HIGH Level
Input LOW Level
Input Leakage Current

IIX
Ioz
Ise

Test Conditions
lOR = -3.2mA

COM'L/IND

Min.

lOR = -2mA

MIL

lOR = 100/LA

COM'L/IND
IOL=16rnA
MIL
10L = 12rnA
Guaranteed Input Logical HIGH Voltage for All Inputsfl)
Guaranteed Input Logical LOW Voltage for All Inputs[l)

Ieel

Vee = Max., VIN = GND Outputs Open

V

Vcc -1.0V

V

COM'L/IND
MIL
MIL-20

O.S

V

0.8

V
V

2.0

-40
-30
"L"

Standby Power
Supply Current

2.4

-10

Vss ,,; VIN ,,; Vee, Vee = Max.
Vee = Max., Vss ,,; VOUT ,,; Vee
Output Short Circuit Current Vee = Max., VOUT = 0.SV[2)

Output Leakage Current

Max. Units

10
40
-90

rnA

SS
90
100

rnA
rnA
rnA

120

rnA

/LA
/LA

Notes:
I. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
3. Tested initially and after any design or process changes that may
affect these parameters.

4. Figure I a test load used for all parameters except tEA, tER. tpzx and
tpxz. Figure I b test load used for tEA. tER. tpzx and tpxz.
5. Preliminary specifications.
6. See the last page of this specification for Group A subgroup testing
infonnation.
7. TA is the "instant on" case temperature.

4-63

Description

Parameters

Min.

Test Conditions

CIN

Input Capacitance

CoUT

Output Capacitance

Max.

Units

5
8

pF

VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz

pF

Switching Characteristics PAL C 22Vl0[4, 6]
Military

Commercial &: Industrial
lParameters

Description

B-15

-20

-25

B-20

-35

-25

-30

Units

-40

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tpD

Input to Output
Propagation Delay!14)

15

20

25

35

20

25

30

40

ns

tEA

Input to Output
Enable Delay

15

20

25

35

20

25

25

40

ns

tER

Input to Output
Disable Delay(9)

15

20

25

35

20

25

25

40

ns

tco

Clock to Output
Delay!15)

10

12

15

25

15

15

20

25

ns

t8

Input or Feedback
Setup Time

10

12

15

30

17

18

20

30

ns

tH

Input Hold Time

0

0

0

0

0

0

0

0

ns

tp

External Clock
Period (teo + t8)

20

24

30

55

32

33

40

55

ns

tWH

Clock Width HIGH(3)

10

12
12

17
17

12
12

14
14

16
16

22
22

ns

tWL

6
6

10

Clock Width LOW(3)

fMAXI

ExternaI Maximum
Frequency
(l/(tco + t8»[IO)

50.0

41.6

33.3

18.1

31.2

30.3

25.0

18.1

MHz

fMAX2

Data Path
Maximum Frequency
(l/(twH + twL»[3. 11)

83.3

50.0

41.6

29.4

41.6

35.7

31.2

22.7

MHz

fMAX3

Internal Feedback
Maximum Fr~uency
(l/(tCF + t8» 12)

80.0

45.4

35.7

20.8

33.3

32.2

28.5

20.0

MHz

tcF

Register Clock to
Feedback Input [13)

tAW

Asynchronous Reset
Width

15

20

25

35

20

25

30

40

ns

tAR

Asynchronous Reset
Recovery Time

10

20

25

35

20

25

30

40

ns

tAP

Asynchronous Reset to
Registered Output Delay

tSPR

Synchronous Preset
Recovery Time

10

20

25

35

20

25

30

40

ns

tpR

Power Up
Reset Time!16)

1.0

1.0

1.0

1.0

1.0

1.0

1.0

1.0

fl.s

2.5

10

20

13

25

18

35

25

4-64

13

13

25

15

20

30

25

ns

40

ns

ns

~

PAL C 22VIOB/PAL C 22VIO

~~~NDU~R
======================================================================
Notes:
8. This parameter is sample tested periodically with the device clocked
at fMAX external (fMAXI) with all registers cycling on each cycle and
outputs disabled (in high Z state).
9. This parameter is measured as the time after output disable input
that the previous output data state remains stable on the output. This
delay is measured to the point at which a previous high level has
fallen to 0.5 volts below VOH Min. or a previous low level has risen
to 0.5 volts above VOL Max. Please see Figure 4 for enable and
disable test waveforms and measurement reference levels.
10. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feed back can
operate.
11. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feed back can
operate. This parameter is tested periodically by sampling production product.

n

13. This parameter is calculated from the clock period at fMAX internal
(fMAX3) as measured (see note 12 above) minus ts.
14. This specification is guaranteed for all device outputs changing state
in a given access cycle. See Figure 3 for the minimum guaranteed
negative correction which may be subtracted from tpD for cases in
which fewer outputs are changing state per access cycle.
15. This specification is guaranteed for all device outputs changing state
in a given access cycle. See Figure 3 for the minimum guaranteed
negative correction which may be subtracted from tco for cases in
which fewer outputs are changing state per access cycle.
16. The registers in the PAL C 22V1O have been designed with the
capability to reset during system power-up. Following power-up, all
registers will be reset to a logic LOW state. The output state will
depend on the polarity of the output buffer. This feature is useful in
establishing state machine initialization. To insure proper operation,
the rise in Vcc must be monotonic and the timing constraints depicted in Figure 5 must be satisfied.

AC Test Loads and Waveforms (Commercial)
R1 238.0.
(319" "'L)

OUTP~~ft

R2

~~

INCLUDING

JIGAND

SCOPE

OUTP~~

1M"

I

5~

(23M "'L)

-=

-=

3.0 V -------::.I::-=-----::L
R2

I

1M"

GND----'. .

(236" "'L)

S;Sns

-=-=

Figure la
Equivalent to:

INPUT PULSES

R1 238.0.
(319<> "'L)

0023-12

Figure 2
0023-11

Figure Ib

THE-VENIN EQUIVALENT (Commercial)

Equivalent to:

THE-VENIN EQUIVALENT (Military)

99.(1

136.(1

OUTPUT~2.08V=Vthc

OUTPUT~2.13V=Vthm

0023-13

0023-14

Minimum Negative Correction to tpD and teo
vs. Number of Outputs Switching

v

~

13

-0.2

8 iE

-0.4

'"
in

V
V

~: -o.S
ffi
z S. -0.8

V

~~
O!
-1.0

IL V

i!E

::Ii

-1.2

1

2

3

4

5

6

7

8

9 10

NUMBER 0, DEVICE OUTPUTS
CHANGING STATE PER ACCESS CYCLE

0023-20

Figure 3
Parameter

Vx

tER(-)

1.5V

tER(+)

Output Waveform-Measurement Level
VOH

~.,~

+r
+r

2.6V
VOL

tEA(+)

Vthc
Vx

tEA(-)

Vthc

Vx

~

~.~~

~

Figure 4. Test Waveforms

4-65

Vx

0023-1e

Vx

0023-17
VOH

0023-1e

VOL

0023-19

n
y

~crF'FJJ3S
PAL C 22VIOB/PAL C 22VIO
"'~ICONDUCl'OR ==========================~~=~=~
Switching Waveforms

INPUTS I/O.
REGISTERED ----.Ir"-"""\~~'7\.I,r-----------.....,.
FEEDBACK

SYNCHRONOUS---~~---J~~~~----~---~---------~~-J~--------PRESET
CP

ASYNCHRONOUS
RESET _________+~------I-...I

t EA (9 )

REGISTERED
OUTPUTS:

:::::::::::~~~~::::~~:::l~~~C:::::::::::::~::i~~~1€r:::::
::::::::::::::::::::lQ~~::::::::::::::::::~~:j~~~-€r:::::
t EA(9 )

COMBINATORIAL
OUTPUTS:

0023-3

Power Up Reset Waveforms[t6]
POWER ______________4_V~~--------------------------------------------VCC

....

.

PR

REGISTERED
ACTIVE LOW
OUTPUT

/J.

~

\.'\

CLOCK

_ tWL 0023-21

Figure 5

4-66

~&S
PAL C 22VIOB/PAL C 22VIO
•
"~ICONDUcrOR ================~~~~~~~~~~~
Functional Logic Diagram PAL C 22VI0

...
'v ..

..

P, P,
PO'!

0

..

IHPUTUHn

"

"

"

,.

21

"

.. ..

0

-tbr

>-- ........

,

...

~

..

l>-~ll

Io.o-ro

0

>-2~

Jt

;66

0

>-

@to-

3~
"
0

>-

r~

4~

~

;66

~th
n

=th
n
em

I>

~

;*

~th
~ n

·

"

>-

6

"•

-th
-66

>- t>........
CELL

.....

~

I r""

"~

0

9

10

11

...

.
"
·,

>A

20

19

18

17

n

>-- t>........
em
~ ~

... ",

21

T-T

5~

8

II

22

Io.o-ro

"

7

23

-66
-66
..coo-

I>

CtLl

16

15

'-""

....

...
.....

>--

........

I>-c:tLI.

Jt

A

14

.....,.

13

0023-4

4-67

~

PALC22VIOB/PALC22VIO

~~~~~~~~~~~~~~~~~~==========~============~====
Typical DC and AC Characteristics
NORMALIZED STANDBY
SUPPLY CURRENT (Icctl
VB. SUPPLY VOLTAGE

NORMALIZED STANDBY
SUPPLY CURRENT Ucct>
VII. AMBIENT TEMPERATURE

1.4,-"'--'--"--71

NORMALIZED
PROPAGATION DELAY
VII. SUPPLY VOLTAGE
1.2

I

I,.

.............

OA~~~--;--+---i

~~=----~a~---~,.
SUPPLY VOLTAGE IV)

0.8
4.0

NORMAUZED PROPAGATION DELAY

.fai!

NORMAUZED SETUP TIME
SUPPLY VOLTAGE

VII.

I

1&.0

g

..

ii

8.0

20.0

~

./

10.0

V

1M
Q

&.0

""' "- ...........

V

:I

~

'"

5.5

IUPPLYVOLTAGE IV)

DELTA PROPAGATION TIME
VB. OUTPUT LOADING

I.3r-----.......- - - - . . . . ,

I'--

4.5

AMBIENT TEMPERATURE I'C)

VB. TEMPERATURE

"

I

200

AMBIENT TEMPERATURE I'CI

400

_

_

lOGO

OA

4.D

4.5

CAPACITANCE (pF)

NORMALIZED SETUP TIME

13,---,..-----,

'"

5.5

8.0

SUPPLY VOLTAGE IV)

NORMALIZED CLOCK TO OUTPUT
TIME VB. SUPPLY VOLTAGE

VII. TEMPERATURE

&.0

1.4

I.Ir--..,..-.....,--.,---,

NORMALIZED CLOCK
TO OUTPUT
TIME VII. TEMPERATURE

1.3

§

§

I

Q
1M

i

1.1

i

1.0

AMBIENT TEMPERATURE I'C)

SUPPLY VOLTAGE IVI

DELTA CLOCK TO OUTPUT TIME
VII. OUTPUT LOADING
28.0

OUTPUT SINK CURRENT
VB. OUTPUT VOLTAGE

AMBIENT TEMPERATURE I'C)

OUTPUT SOURCE CURRENT
VII. VOLTAGE

120
~

V

3:
10.0

/

~

is

V

V

~"

1&.0

!

1.2

J

I

200

"'

L
1/

./

400

_

CAPACITANCE IpF)

_

lOGO

I

!'I..

~~_z:;~V-

r'\.

"'1"'-

........

i/
OUTPUT VOLTAGE IV!

.......

OUTPUT VOLTAGE IV)

0023-15

4-68

~
PAL C22Vl0BIPAL C22Vl0
~~~~================================================================
Erasure Characteristics
normal mode of operation. Cells in the PHANTOM ARRAY, TOP TEST, and BOTTOM TEST areas are programmed at Cypress during the manufacturing operation,
and they therefore will be programmed when received in a
non-windowed package by the user. Consequently, the user
will normaI1y have no need to program these cells.

Wavelengths of light less than 4000 Angstroms begin to
erase the PAL C 22V1O. For this reason, an opaque label
should be placed over the window if the device is exposed
to sunlight or fluorescent lighting for extended periods of
time. In addition, high ambient light levels can create holeelectron pairs which may cause "blank" check failures or
"verify errors" when programming "windowed" parts.
This phenomenon can be avoided by use of an opaque label
over the window during programming in high ambient
light environments.

The Cypress PAL C 22V1O contains 10 identical MACROCELLS which may be individually configured. Each
MACROCELL is associated with a single I/O pin and
through the architecture bits, each associated pin may be
permanently configured as an input, an output or be used
as both input and output as a function of the logical function in the array. Each MACROCELL consists of a type
"0" latch, an output multiplexer, a feedback multiplexer
and a tristatable output driver that is controlled by a
unique product term. The clock is common to all MACROCELLS, and comes from pin 1 of the device. Each register also has an asynchronous reset and a synchronous
preset. These are each driven by product terms. These
product terms are common to all MACROCELLS allowing all registers to either be asynchronously reset or synchronously preset by a logical function in the array. The
device is automatically reset at power up. A preload feature
allows the registers to be preloaded with any state for testing.

The recommended dose for erasure is ultraviolet light with
a wavelength of 2537 Angstroms for a minimum dose (UV
intensity X exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 m W /cm2 power rating, the exposure
would be approximately 35 minutes. The PAL C 22VI0
needs to be placed within 1 inch of the lamp during erasure. Permanent damage may result ifthe device is exposed
to high intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.

Device Programming
The PAL C 22VI0 has multiple programmable functions.
In addition to the normal array, a "PHANTOM" array,
"TOP and BOTTOM TEST" and a "SECURITY" feature
are programmable. The PAL C 22VI0 security mechanism, when invoked, prevents access to the "NORMAL"
and "TOP/BOTTOM TEST" array. The "PHANTOM"
array feature is still accessible, allowing programming and
verification of the pattern in the "PHANTOM" array.
Functional operation of all other features is allowed regardless of the state of the "SECURITY BIT". In addition,
the device contains 10 MACROCELLS which are programmed to configure the device functionality for each
specific application.

The architecture bits CO and Cl are used to configure each
MACROCELL individually. CO selects the polarity of the
output and Cl selects the combinatorial or registered mode
of operation. If the registered mode of operation is selected,
the feedback path is automatically selected to be from the
register. In the combinatorial mode the feedback path is
automatically selected to be from the I/O pin. In this combinatorial mode, the output from the array may be fed into
the array or if the output is deselected using the output
enable product term the pin may be used as an external
input. There is not a mode where the I/O pin may be used
as a combinatorial output or an input pin, while the register is used as a state register. The architecture bits are
programmed as a separate item during normal programming. An I/O pin is configured to be an input by programming the MACROCELL into a combinatorial mode and
disabling the ouput with the output enable product term.

The logic array is divided into a "NORMAL" array and a
"PHANTOM" array. The normal array is used to configure the device to perform a specific function as required by
the user, and the phantom array is provided as a test array
for Cypress' testing the device prior to user programming
thus assuring a reliable, thoroughly tested product. The
"PHANTOM" array contains four additional columns
connected to input pins 2 (TRUE), 7 (INVERTING), 10
(TRUE) and 11 (TRUE). These inputs may be programmed to be connected to all normal product terms.
This allows all sense amplifiers and macrocells to be exercised for both functionality and performance after assembly and prior to shipment. These features are in addition to
the normal array. They do not affect normal operation,
allowing the user full programming of the normal array,
while allowing the device to be fully tested.

Pinout
The PAL C 22V1O PROGRAMMING pinout is shown in

Figure 6. In the Programming pinout configuration, the
device may be programmed and verified for the NORMAL
mode of operation and also programmed, verified and operated in PHANTOM and TEST modes. These special
modes of operation are achieved through the use of supervoltages applied to certain pins. Care should be exercised
when entering and exiting these modes, paying specific attention to both the operating modes as specified in Table 1
and the sequencing of the supervoltages as shown in the
timing diagrams.

The "TOP TEST" and "BOTTOM TEST" feature, allow
connection of all input terms to either pin 23 or 13. These
locations may be programmed and subsequently exercised
in the "TOP TEST" and "BOTTOM TEST" mode. Like
the Phantom array above, this feature has no effect in the

4-69

4

Wi!~

PAL C 22VIOB/PAL C 22VIO

SEMICONDUCTOR

Programming Pinout
vpp

vee

AO
A1
A2
A3
A4
AS
A6
A7
A8
A9

DO
01
02
03
04
05
06
07
08
09

Vss

provide the individual addresses of the various arrays and
cells to be programmed. There are 5 operating modes in
addition to the programming modes for the PAL C 22VlO.
These provide NORMAL operation, PHANTOM operation, TOP TEST, BOTTOM TEST and a register preload
feature for testing.
In the normal operating mode, all signals are TTL levels
and the device functions as it is internally programmed in
the NORMAL array. In the PHANTOM mode of operation, the device operates logically as a function of the contents of the PHANTOM array. In this mode pins 2,10 &
11 are non-inverting inputs and pin 7 is an inverting input.
The MACROCELLS function as they are programmed for
normal operation. If the MACROCELLS have not yet
been programmed, they are in a registered inverting configuration. The PHANTOM mode is invoked by placing a
supervoltage Vpp on pin 6. Care should be exercised when
entering and leaving this mode that the supervoltage is applied no sooner than 20 ms after the Vee is stable, and
removed a minimum of 20 ms before Vee is removed.

PGM/VF'
0023-6

Figure 6

Programming Algorithm

TOP and BOTTOM TEST

With the exception of the Security bit, all arrays are programmed in a similar manner. The data to be programmed
is represented by a "I" or "0" on the I/O pins. A "I"
indicates that an unprogrammed location is to be programmed and a "0" indicates that an unprogrammed location is to remain unprogrammed. All locations to be programmed are addressed as row and column locations. Table 1 "Operating Modes" along with Tables 2 through 5
provide the specific address for each addressed location to
be programmed along with mode selection information for
both programming and operation in the "PHANTOM"
and "TEST" modes.
When programming the security bit, a supervoltage on pin
3 is used as data with a programming pulse on pin 13.
Verification is controlled with a supervoltage on pins 4 and
the data out on pin 3.

The TOP TEST and BOTTOM TEST modes are entered
and exited in the same manner, with the same concern for
power sequencing, but the supervoltage is applied to pins 9
& 10 respectively. In these modes an extra product term
controls an output pin. TOP TEST controls pin 23, and
BOTTOM TEST controls pin 14. These product terms are
controlled by the normal device inputs, and allow testing of
all input structures.

Preload
Finally for testing of programmed functions, a preload feature allows any or all of the registers to be loaded with an
initial value for testing. This is accomplished by raising pin
8 to a supervoltage Vpp, which puts the output drivers in a
high impedance state. The data to be loaded is then placed
on the I/O pins of the device and is loaded into the registers on the positive edge of the clock on pin 1. A "0" on the
I/O pin preloads the register with a "0" and a "I" preloads
the register with a "I". The actual signal on the output pin
will depend on the output polarity selected when the
MACROCELL is programmed. The data on the I/O pins
is then removed, and pin 8 returned to a normal TTL voltage. Again care should be exercised to power sequence the
device properly.

Operating Modes
Table 1 describes the operating and programming modes of
the PAL C 22VlO. The majority of the programming
modes function with a PROGRAM, PROGRAM INHIBIT and PROGRAM VERIFY sequence. The exception is
the Security Program operation, which shows no program
inhibit function. Two timing diagrams are provided for
these two different methodologies of programming in Figures 8 & 9. Tables 2 through 5 are used as indicated to

4-70

~
PALC22VIOB/PALC22VIO
~~~~=============================================================
Operating Modes
Table 1
Operating Modes
Feature

Pin
1

Main
Array
Product

Vpp

Program Inhibit

Vpp

Output
Enable
Product
Terms

Program

Vpp

Program Inhibit

Vpp

Program Verify

PAL
Mode
Operation

Pin
4

Pin
5

Pin
6

Pin
7

Pin
8

Pin

9

Pin
10

Pin
11

Pin
13

Pin
14

Pin
17

Vpp
Table 2

Table 3

Program Verify [3] Vpp

Sync Set,
Program
Async
Reset,
Program Inhibit
Top Test.
Bottom Test Program Verify
Notes

Security
Bit

Pin
3

Pin
20

Function
Program

ArchitectureBits

Pin
2

Pins
15,16,18,
19,21 &: 22

Data In

VIHP

HighZ

VU.P

Data Out

VIHP VlHP VIHP Vpp Vpp

Data In

VIHP VIHP VIHP Vpp VIHP

HighZ

Vpp

VlHP VlHP VlHP Vpp VILP

Data Out

Vpp

VIHP VlHP VIHP VlHP Vpp

Table 2

Vpp

Table 2

Vpp

Data
in

Data
In

VIHP VlHP VIHP VIHP VlHP HighZ HighZ HighZ

HighZ

HighZ

Data
VIHP VIHP VIHP VIHP VILP
Out

Driven

Data
Out

VILP

VILP

Vpp VIHP VIHP VIHP VIHP VIHP VlHP VILP

Program Inhibit

Vpp VIHP VIHP VIHP VIHP VIHP VIHP VILP

Vpp Vpp

Program Verify

Vpp VlHP VIHP VlHP VIHP VIHP VIHP VILP

Program

Vpp VILP Vpp VILP VILP VILP VILP VILP VILP VILP VILP Vpp VILP

Verify

Data
Vpp VILP VILP VILP VILP VILP VILP VILP VILP
VILP VILP
Out

Table 4

Data
In

Data
Out

Data
In

Data
Out
Data In

Vpp VIHP

HighZ

Vpp VILP

Data Out
VILP VILP

Driven Outputs

Normal

CP/I

I

I

I

I

I

I

I

I

I

I

I

I/O

Phantom

NA

I

NA

NA

NA

Vpp

I

NA

NA

I

I

NA

Output

Top Test

I

I

I

I

I

I

I

I

Vpp

I

I

I

Bottom Test

I

I

I

I

I

I

I

I

I

Vpp

I

I

NA

NA

NA

NA

NA

NA

Reg Preload

Notes NA

II
VILP

Program

Phantom
Vpp VILP VILP
Program
VILP
Array
Program Inhibit Vpp VILP VILP Table 5 VILP
Product
Program Verify
Vpp VILP VILP
VILP
Terms
Phantom
Vpp VILP VILP
Program
VILP
Output
Enable
Program Inhibit Vpp VILP VILP Table 5 VILP
Product
Program Verify
Vpp VILP VIL
VILP
Terms
Notes:
I. DATA IN and DATA OUT for programming Synchronous Set,
Asynchronous Reset. TOP TEST and BOTTOM TEST is programmed and verified on the following pins.
Pin 14 = BOTTOM TEST
Pin 17 = Synchronous Set
Pin 20 = Asynchronous Reset
Pin 23 = TOP TEST

Pin
23

NA Vpp
Vpp
Vpp
Vpp

Table 3

NA
Out

Out
NA

NA VILP

Data In

Vpp

Data In

VIHP

HighZ

VILP

Data Out

Vpp VIHP VlHP VIHP Vpp Vpp

Data In

Vpp VIHP VIHP VlHP Vpp VlHP

HighZ

Vpp VIHP VlHP VIHP Vpp VILP

Data Out

2. The preload clock on pin 1 loads the Registers on a LOW going
HIGH transition.
3. It is necessary to toggle OE (Pin 13) HIGH during all address transitions while in the program verify/blank check mode.

4-71

~

PAL C 22V10B/PAL C22V10

. .r~UCI'OR===========
Input Term Addresses
It provides the addressing for the 44 normal input term
columns which are connected with an EPROM transistor
to the product terms.

Table 2 is used during the programming and verification of
the main array, output enable, asynchronous reset, synchronous preset, TOP and BOTTOM TEST as shown in
Table 1.

Input Term Addresses
Table 2
Input
Term
0
1
2
3
4
5
6
7
8
9
10

11
12
13

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

41
42
43

Pin
3

Pin

2

4

Pin
5

Pin
6

Pin
7

VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP

VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP

VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP

VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP

VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP

VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP

Pin

4-72

~

PALC22VIOB/PALC22VIO

~r~====================
Product Term Addresses

Phantom Input Term Addressing

Table 3 is used for the programming of the "PHANTOM"
and normal array. It provides the addressing for the up to
16 product terms associated with each input. Notice that
the number of product terms varies from 8 to 16 and back
to 8 from the top to the bottom output. In Table 3, product
term "0" refers to the top product term associated with the
MACROCELLS on pins 18 and 19, while address 15 refers
to the bottom or last product term associated with the
same pins. In the same manner, the 8 product terms associated with pins 14 and 23 are addressed as "0" through "7".
The balance of the product terms associated with the remaining I/O pins are addressed as "0" through "10", "12"
and "14".

Phantom input terms are addressed as columns PO thru P3
and represent inputs from pins 2, 7, 10 and 11 respectively.
Pin 7 is inverted, and the remaining 3 are normal non-inverting. This PHANTOM array allows the output structures to be tested. They are only present in PHANTOM
modes of operation.

Phantom Input Term Addresses
TableS

Product Term Addresses
Table 3
Product
Term

Pin
8

Pin

Pin

I)

10

Pin
11

0
1
2
3
4

VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP
VILP
VIHP

VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP
VILP
VILP
VIHP
VIHP

VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP

VILP
VILP
VILP
VILP
VILP
VILP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP

5
6
7
8
9
10

11

12
13
14
15

Architecture Bit Addresssing
Table 4
Pin
I)

Pin
10

Output
Polarity
CO

VILP

VILP

Register/
Non-Register
OutputCI

VIHP

VILP

Pin
5

PO
PI
P2
P3

VILP
VIHP
VILP
VIHP

VILP
VILP
VIHP
VIHP

Programming Flow Chart

Architecture Bit Addresssing

Bit

Pin
4

The programming flow chart describes the sequence of operations for programming the NORMAL and PHANTOM
arrays, the NORMAL and PHANTOM output enable
product terms, the set and preset product terms, the Top
Test product term, the Bottom Test product term, and the
architecture bits. The exact sequencing and timing of the
signals is shown in the "Array Programming Timing Diagram".
The logical sequence to program the device is described in
detail in the flow chart below, and should be followed exactly for optimum intelligent programming that both minimizes programming time and realizes reliable programming. Particular attention should be paid to the application
of Vcc prior to Vpp, and removal ofVpp prior to Vee. See
Figure 8 and Table 7 for specific timing and AC requirements. Notice that all programming is accomplished without switching Vpp on pin 1 and that after programming
and verifying all locations individually, the programmed
locations should be verified one final time.
The normal word programming cycle, programs and verifies a word at a time as shown in the programming flowchart, Figure 7 and timing diagram Figure 8. After alllocations are programmed, the flowchart requires a verify of all
words. There is no independent timing diagram for this
operation, rather Figure 8 also provides the correct timing
information for this operation. When performing this verify only operation, eliminate the program portion of the
cycle but maintain the setup and hold timing relative to the
verify pulse. Under no circumstances should the verify signal be held low and the addresses toggled.
Note that the overprogram pulse in step 10 of the programming flowchart is a variable, "4" times the initial value
when programming the NORMAL, PHANTOM, TOP
TEST, BOTTOM TEST and OUTPUT ENABLE product
terms and "8" times the initial value when programming
the ARCHITECTURE BITS.

Table 4 provides the addressing for the architecture bits
used to control the configuration of the individual MACROCELLS. In the unprogrammed state, the MACROCELLS are in a registered, active low or inverting configuration. They are programmed with a "I" on the pin associated with the MACROCELL and the appropriate address
as shown in Table 4. Each architecture bit that is not to be
programmed, requires a "0" on the I/O pin associated with
the MACROCELL.

Architecture

Phantom
Input
Term

4-73

II

~

PAL C 22VIOB/PAL C 22VIO

CYPRFSS

~~~==========~~~~
Programming Flowcltart
START
Vee
5.0V

=

Vpp

=SEE NOTE 2

ADDRESS FIRST LOCATION,

PLACE DATA TO BE PROGRAMMED
ON THE I/O PINS

x=o

Notes:
I. This value is "4" for program·
ming the NORMAL array,
PHANTOM array TOP TEST,
BOTTOM TEST and OUTPUT
ENABLE PRODUcr TERMS.
The value is "S" when program·
ming ARCHITEcruRE BITS.
2. V pp, Progranuuing Voltage:
For PAL C22VlOB = l2.SV
For PAL C 22VlO = 13.SV

PROGRAM ONE PULSE
OF 0.4ms

X=X+l
X=5
NO
VERIFY ONE WORD
PASS
PROGRAM ONE PULSE OF
«NOTE 1) • 0.4 • X) ms

X=5
NO~--------~----~--~
....._-...:..;.;..j
YES
VERIFY ALL WORDS AT
Veep
5.5 VOLTS

=

PASS
GOOD DEVICE

Vpp

=O.OV

Vee = O.OV
STOP
0023-7

Figure 7

4-74

~

PALC22VIOB/PALC22VIO

~~~~R==~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
Timing Diagrams
Programming timing diagrams are provided for two cases,
programming of all cells except the SECURITY BIT and
programming the SECURITY BIT.

DATA OUT is verified on the same pins. A "I" (VIHP) on
an I/O pin causes the addressed location to be programmed. A "0" on the I/O pin leaves the addressed location to be unprogrammed. All setup hold and delay times
must be met, and in particular the sequence of operations
should be strictly followed. During verify only operation it
is not acceptable to hold PGM!VFY low and sequence
addresses, as it violates address setup and hold times. Proper sequencing of all power and supervoltages is essential, to
reliable programming of the device as improper sequencing
could result in device damage.

Array
Programming the NORMAL and PHANTOM arrays and
output enables, reset, preset, architecture bits and the top/
bottom test features uses the timing diagram in Figure 8.
ADDRESS refers to all applicable information in Tables 1
through 5 that is not specifically referenced in the timing
diagram. DATA IN is provided on the I/O pins and

.

Programming Waveforms
VccP

Vee PIN 24
NOTE 1 VSS Vpp
Vpp PIN 1

ADDRESS
NOTE 2

V1HP
V1LP V1HP

DATA
V1LP -

PGM/VF'Y
PIN 13
V1HP V1LP -

--------~
0023-8

Notes:
1. Power, Vpp & Vee should not be cycled for each program/verify
cycle, but may remain static during programming.

2. For programming OE Product Terms & Architecture bits, Pin 11
(A9) must go to Vpp and satisfy TAS and TAN.

Figure 8

4-75

~

PALC22VIOB/PALC22VIO

~r~~===================
Security Cell
The security cell is programmed independently per the timing diagram in Figure 9, and the information in Table 1.
Note again that proper sequencing of power and programming signals is required. Data in is represented as a supervoltage on pin 3 and verified as a TTL signal output on the

same pin. A "0" on pin 3 indicates that the security bit has
been programmed, and a "1" indicates that security- bit has
not been programmed. Security is programmed with a sin- gle 50 ms pulse on pin 13. A supervoltage on pin 4 is used
to verify security after Vpp has been removed from pin 1.

Programming Waveforms Security Cell
vee PIN 24

Veep

-

VSS -

-J

~,.

Tp

______________ TP ____________

~jf--~

VPP_
VPP PIN 1
VSS-

Top

VPP_

TOZ

DATA PIN3 VIHP VILP -

Vpp_
PGIA
PIN 13
VILP _

I-------TOV
Vpp_

SECURIlY
VrY
PIN4
VILP -

0023-9

Figure 9

4-76

~

PAL C 22VI0B/PAL C 22VI0
~~~NDUcroR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DC Programming Parameters TA

= 25°C

Table 6
Parameter

Description

Min.

Max.

Units

Vpp for PAL C 22VIOB

Programming Voltage

12.0

13.0

Volts

Vpp for PAL C 22VIO

Programming Voltage

13.0

14.0

Volts

Veep

Supply Voltage
During Programming

4.75

5.25

Volts

VIHP

Input HIGH Voltage
During Programming

3.0

Veep

Volts

VILP

Input LOW Voltage
During Programming

-3.0

0.4

Volts

VOH

Output HIGH Voltage

2.4

VOL

Output LOW Voltage

0.4

Volts

Ipp

Programming
Supply Current

40

mA

Volts

AC Programming Parameters
Table 7
Parameter

Description

Tp

Delay to Programming
Voltage

Top

Min.

Max.

Units

20

ms

Delay to Program

1

J.l.s

THP

Hold from Program
or Verify

1

J.l.s

TR,F

Vpp Rise & Fall Time

50

ns

TAS

Address Setup Time

I

J.l.s

TAH

Address Hold Time

I

J.l.s

ToS

Data Setup Time

I

J.l.s

TOH

Data Hold Time

I

Tpp

Programming Pulsewidth

0.4

Tspp

Programming Pulsewidth
for Security

50

ms

Tov

Delay from Program
to Verify

2

J.l.s

Tvo

Delay to Data Out

Tvp

Verify Pulse Width

Toz

Verify to High Z

J.l.s

10

I
2

J.l.s
J.l.s

I

4-77

ms

J.l.s

•

~
PALC22VIOB/PALC22VIO
~~~~=============================================================
Ordering Information
Icc

tpD

ts

teo

(mA)

(os)

(os)

(ns)

90

15

10

10

90

120

55

90

100

100

55

90

100

20

20

25

25

25

30

35

35

40

12

17

15

15

18

20

30

30

30

12

15

15

15

15

20

25

25

25

Package

Operating Raage

PAL C 22VIOB-15PC/PI

P13

CommerciaVIndustrial

PAL C 22VIOB-15WC/WI

W14

Ordering Code

PAL C 22VIOB-15JC/JI

J64

PAL C 22VIO-20PC/PI

P13

PAL C 22VIO-20WC/WI

W14

PAL C 22VI0-20JC/JI

J64

PAL C 22VIOB-20DMB

014

PAL C 22VIOB-20WMB

W14

PAL C 22VIOB-20LMB

L64

PAL C 22VIOB-2OQMB

Q64

PAL C 22VIOB-20KMB

K73

PAL C 22VI0L-25PC

P13

PAL C 22VIOL-25WC

W14

PAL C 22VIOL-25JC

J64

PAL C 22VI0-25PC/PI

P13

PAL C 22VI0-25WC/WI

WI4

PAL C 22VIO-25JC/JI

J64

PAL C22VIO-25DMB

014

PAL C 22VIO-2SWMB

W14

PAL C 22VI0-25LMB

L64

PAL C 22VIO-25QMB

Q64

PAL C 22VIO-25KMB

K73

PAL C 22VIO-30DMB

014

PAL C 22VI0-30WMB

WI4

PAL C 22VIO-30LMB

L64

PAL C 22VIO-30QMB

Q64

PAL C 22VI0-30KMB

K73

PAL C 22VIOL-35PC

PI3

PAL C 22VIOL-35WC

W14

PAL C 22VIOL-35JC

J64

PAL C 22VI0-35PC/PI

P13

PAL C 22VIO-35WC/WI

WI4

PAL C 22VIO-35JC/JI

J64

PAL C 22VI0-4ODMB

014

PAL C 22VIO-40WMB

W14

PAL C 22VIO-40LMB

L64

PAL C 22VIO-40QMB

Q64

PAL C 22VI0-4OKMB

K73

4-78

Commercial/Industrial

Military

Commercial

Commercial/Industrial

Military

Military

Commercial

CommerciallIndustrial

Military

~

PALC22VIOB/PALC22VIO

~r~~====================
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

IOZ

1,2,3

Icc

1,2,3

Switching Characteristics
Parameters

Subgroups

tPD

7,8,9,lO,1l

teo

7,8,9,lO,1l

ts

7,8,9, lO, II

tH

7,8,9, lO, II

tw

7,8,9, lO, II

Document #: 38-00020-C

4-79

CY7C330

CYPRESS
SEMICONDUCTOR

CMOS Programmable
Synchronous State Machine

Features
• 256 product terms-32 per pair
of macro cells, variable
distribution
• Global, synchronous, product
term controlled, state register
set and reset-inputs to product
term are clocked by input clock
• 66 MHz operation
- 3 ns input setup and 12 ns
clock to output
- 15 ns input register clock to
state register clock
• Low power
-130 mA Icc
• 28 pin 300 mil DIP, LCC
• Erasable and reprogrammable

• 12 I/O macro cells each having:
- registered, three-state 110
pins
- input register clock select
multiplexer
- feed back multiplexer
- output enable (OE)
multiplexer
• All twelve macro cell state
registers can be hidden
• User configurable state
registers-JK, RS, T, or D
• Input multiplexer per pair of
I/O macro cells allows I/O pin
associated with a hidden macro
cell state register to be saved for
use as an input
• 4 dedicated hidden registers
• 11 dedicated, registered inputs
• 3 separate c1ocks-2 inputs,
1 output
• Common (PIN 14 controlled) or
product term controlled output
enable for each I/O pin

Product Characteristics
The CY7C330 is a high-performance,
eraseable, programmable, logic device
(EPLD) whose architecture has been
optimized to enable the user to easily
and efficiently construct very high performance synchronous state machines.

The unique architecture of the
CY7C330, consisting of the user-configurable output macrocell, bi-directional I/O capability, input registers,
and three separate clocks, enables the
user to design high performance state
machines that can communicate either
with each other or with microprocessors over bi-directional parallel busses
of user-definable widths.
The three separate clocks permit independent, synchronous state machines
to be synchronized to each other. The
two input clocks, Cl, C2, enable the
state machine to sample input signals
that may be generated by another system and that may be available on its
bus for a short period of time.
The user-configurable state register
flip-flops enable the designer to designate JK, RS, T, or D type devices, so
that the number of product terms required to implement the logic is minimized.
LCCPinout

Block Diagram and DIP Pinout

g - :.:

Q

-

...

:)1jd~~~
12

5

13
14

6
7

Vss
15

Ie
17

432:1,282726
25

h.

24
23
22
21
10
20
1\
19
12131415161118

PROGRAMMABLE AND ARRAY

:~~:
I/Os
Vee
Vss
1/°15
I/O,

0101-14

(258,66)

PLCCPinout

I/O.

1/07

Vss

Vee

1/05
0101-1

Selection Guide
Maximum Operating Frequency (MHz)
Power Supply Current ICC! (rnA)

CY7C330.66 CY7C330.50 CY7C330·40 CY7C330·33 CY7C330·28
50.0
33.3
66.6
28.5
50.0
40.0
130
130
130
Commercial
150
150
Military
150
Commercial
Military

4·80

~

CY7C330

~r~~===================
Macro Cell Input Multiplexer
Each pair of I/O macro cells share a Macro Cell Input
Multiplexer which selects the output of one or the other of
the pair's input registers to be fed to the input array. This
multiplexer is shown in Figure 2. The Macro Cell Input
Multiplexer allows the input pin of a macro cell, for which
the state register has been hidden by feeding back its input
to the input array, to be preserved for use as an input pin.
This is possible as long as the other macro cell of the pair is
not needed as a input or does not require State Register
feed back. The input pin input register output which would
normally be blocked by the hidden State Register feed back
can be routed to the array input path of the companion
macro cell for use as array input.
State Registers
By use of the exclusive or gate the State Register may be
configured as a JK, RS or T Register. The default is a
D-Type register. For the D-Type register, the exclusive or
function can be used to select the polarity or the register
output.
The set and reset of the State Register are global synchronous signals which are controlled by the logic of two global
product terms for which input signals are clocked through
the input registers by either of the input clocks, CKI or
CK2.
Hidden Registers
In addition to the twelve macro cells, which contain a total
of twenty-four registers, there are four hidden registers
whose outputs are not brought out to the device output
pins. The Hidden State Register Macro Cell is shown in
Figure 3.
The four hidden registers are clocked by the same clock as
the macroce1l state registers. All of the hidden register flipflops have a common, synchronous set, S, as well as a common, synchronous reset, R, which over-ride the data at the
D input. The S and R signals are PRODUCT TERMS that
are generated in the array and are the same signals used to
preset and reset the state register flip·flops.
Macrocell Product Term Distribution
Each pair of macrocells has a total of thirty-two product
terms. Two product terms of each macrocell pair are used
for the output enables (OEs) for the two output pins. Two
product terms are also used as one input to each of the two
exclusive OR gates in the macrocell pair. The number of
product terms available to the designer is then 32 - 4 =
28 for each macrocell pair. These product terms are divided between the macro cell state register flip-flops as shown
in Table 1.
Table 1. Product Term Distribution
Macro Cell Pin No. Product Terms

Product Characteristics (Continued)
The major functional blocks of the CY7C330 are (I) the
input registers and (input) clock multiplexers, (2) the
EPROM (AND) cell array, (3) the twelve I/O macrocells
and (4) the four hidden registers.
Input Registers and Clock Multiplexers
There are a total of eleven dedicated Input Registers. Each
Input Register consists of a D flip-flop and a clock multiplexer. The clock multiplexer is user-programmable to select either CKI or CK2 as the clock for the flip-flop. CK2
and <:rn can alternatively be used as inputs to the array.
The twenty-two outputs of the registers (i.e. the Q and Q
outputs of the input registers) drive the array of EPROM
cells.
An architecture configuration bit (C4) is reserved for each
Dedicated Input Register cell to allow selection of either
input clock CKI or CK2 as the input register clock for
each Dedicated Input Cell. If the CK2 clock is not needed
that input may also be used as a general purpose array
input. In this case the Input Register for this input can
only be clocked by input clock CK1. Figure 1 illustrates
the Dedicated Input Cell composed of input register, Input
Clock Multiplexer, and architecture configuration bit C4
which determines the input clock selected.
I/O Macro Cell
The logic diagram of the CY7C330 110 macro cell is
shown in Figure 2. There are a total of twelve indentical
macro cells.
Each macro cell consists of:
- An Output State Register which is clocked by the global
state counter clock, CLK (PIN 1). The State Register
can be configured as a D, JK, RS, or T flip-flop (default
is a D-type flip-flop). Polarity can be controlled in the
D flip-flop implementation by use of the exclusive or
function. Data is sampled on the LOW to HIGH clock
transition. All of the State Registers have a common
reset and set which are controlled synchronously by
Product Terms which are generated in the EPROM cell
array.
- A Macro Cell Input Register which may be clocked by
either the CKI or CK2 input clock as programmed by
the user by use of architecture configuration bit C2
which controls the 110 Macro Cell Input Clock Multiplexer. The Macro Cell Input Registers are initialized
on power up such that all of the Q outputs are at logic
LOW level and the Qoutputs are at a logic HIGH level.
- An Output Enable Multiplexer (OE), which is user-programmable, by architecture configuration bit CO, to select either the common OE signal from pin 14 or, for
each cell individually, the signal from the Output Enable product term associated with each macro cell. The
Output Enable input signal to the array product term is
clocked through the input register by the selected input
register clock, CKI or CK2.
- An input Feed Back Multiplexer which is user-programmable to select either the output ofthe State Register or the output of the Macro Cell Input Register to be
fed back into the array. This option is programmed by
architecture configuration bit C1. If the output of the
Macro Cell Input Register is selected by the Feed Back
Multiplexer, the 110 pin becomes bi-directional.

0
1
2
3

4
5
6
7
8

9
10
11

4-81

28
27
26
25
24
23
20
19
18
17
16
15

9
19
11
17
13
15
15
13
17
11
19
9

..
~

~
CY7C330
~r~====================
Product Characteristics (Continued)
Hidden State Register Product Term Distribution

Table 2. Hidden State Register Product Term Distnoution

Each pair of hidden registers also has a total of 32 product
terms. Two product terms are used as one input to each of
the exclusive OR gates. However, because the register outputs do not go to any output pins, output enable product
terms are not required. Therefore, 30 product terms are
available to the designer for each pair of hidden registers.
The product term distribution for the four hidden registers
are shown in Table 2.

Hidden Register Cell

Product Terms

0
I
2
3

19
11
17

13

Architecture Configuration Bits
The architecture configuration bits are used to program the
multiplexers. The function of the architecture bits is outlined below.

Table 3. Architecture Configuration Bits
Architecture
Configuration Bit
CO
CI

C2

C4

Function

Value

Output Enable
SelectMUX

12 Bits, I Per

0-Virgin State

Output Enable Controlled by Product Term

110 Macro Cell

I-Programmed

Output Enable Controlled by Pin 14

State Register
Feed Back MUX

12 Bits, I Per
I/O Macro Cell

0-Virgin State

State Register Output is Fed Back to Input Array

I-Programmed

I/O Macro Cell is Configured as an Input
and Output of Input Register is Fed to Array

110 Macro

12 Bits, I Per
I/O Macro Cell

0-Virgin State

CKI Input Register Clock (Pin 2) is Connected
to I/O Macro Cell Input Register Clock Input

I-Programmed

CK2 Input Register Clock (Pin 3) is Connected
to I/O Macro Cell Input Register Clock Input

0-Virgin State

Selects Data from 110 Macro Cell Input Register
of Macro Cell A of Macro Cell Pair

Cell Input
Register Clock
SelectMUX
C3

Number
of Bits

110 Macro Cell

6 Bits, 1 Per

Pair Input
SelectMUX

110 Macro Cell
Pair

I-Programmed

Selects Data from I/O Macro Cell Input Register
of Macro Cell B of Macro Cell Pair

Dedicated Input
Register Clock
SelectMUX

11 Bits, 1 Per
Dedicated Input
Cell

O-Virgin State

CKI Input Register Clock (Pin 2) is Connected
to Dedicated Input Register Clock Input

I-Programmed

CK2 Input Register Clock (Pin 3) is Connected
to Dedicated Input Register Clock Input

INPUT REGISTER

r+------~--~D
PIN 2: CK1
PIN 3: CK2

TO ARRAY

Q~_1_C~::

INPUT
1

C~~iK
C4
0101-5

Figure 1. Dedicated Input Cell

4-82

~PR£SS

'W'nEMICONDUCTOR

CY7C330

===================================
co
PIN 14:0E--~
OUTPUT ENABLE PRODUCT TERM
SET PRODUCT TERM

EX OR PRODUCT TERM

>------10 S

Q

------I:>

0

PIN 1: ClK

R

RESET PRODUCT TERM

o
TO ARRAY

INPUT REGISTER

.....+ - - - - - - - - 1 0
Cl

D

PIN 2:CKI
PIN 3:CK2

TO ARRAY

FROM ADJACENT MACRO CEll
C3

0101-6

Figure 2. I/O Macro Cell and Shared Input Multiplexer

SET PRODUCT TERM

)---JD
PIN l:ClK
RESET PRODUCT TERM

-+0

0

R

0I-

-r-

...

TO ARRAY
~

~

0101-8

Figure 3. Hidden State Register Macro Cell

4-83

~

CY7C330

~r~~====================
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -6S·C to + ISO·C
Static Discharge Voltage ..................... >2OO1V
(per MIL-STD-883 Method 301S)
Ambient Temperature with
Latchup Current .......................... > 200 mA
Power Applied .................... - SS·C to + 12S·C
DC
Programming Voltage ...................... 13.0V
Supply Voltage to Ground Potential
(Pin 22 to Pins 8 and 21) .............. -O.SV to +7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SVto +7.0V

Ambient
Temperature

Vee

Commercial

O"Cto +75°C

5V ±1O%

Military[51

- 55°C to + 125°C

5V ±1O%

Range

DC Input Voltage ................... -3.0Vto +7.0V
Output Current into Outputs (Low) ............. 12 mA

Electrical Characteristics Over Operating Range(6)
Description

Parameters
VOR

VOL

Output HIGH Voltage

Output LOW Voltage

Min. Max. Units

Test Conditions
Vee = Min.,
VIN = VIHorVIL
Vee = Min.,
VIN = VIR or VIL

lOR = -3.2rnA

COM'L

lOR = -2rnA

MIL

IOL = 12rnA

COM'L

IoL = 8 rnA

MIL

VIR

Input HIGH Level

Guaranteed Input Logical HIGH Voltage
for All Inputs !l1

VIL

Input LOW Level

Guaranteed Input Logical LOW Voltage
for All Inputs [11

2.4

V

0.5

V

2.2

V
0.8

V
/LA

IIX

Input Leakage Current

Vss ,,; VIN ,,; Vee, Vee = Max.

-10

10

loz

Output Leakage Current

Vee = Max. Vss ,,; VOUT"; Vee

-40

40

/LA

Ise

Output Short Circuit Current

Vee = Max., VOUT = 0.5V[21

-30

-90

rnA

Ieel

Standby Power Supply
Current

Vee = Max., VIN = GND
Outputs Open

COM'L

130

rnA

MIL

150

rnA

COM'L (-33 MHz & -50 MHz)

160

rnA

COM'L (-66 MHz) [151

180

rnA

MIL (-28 MHz & -40 MHz)

180

rnA

MIL (-50 MHz)[ I51

200

rnA

lee2

Power Supply Current
at Frequency [3,71

Vee = Max.
Outputs Disabled (in High Z State)
Device Operating at /MAX
External (/MAXI)

Capacitance [3]
Parameters
CIN

Description
Input Capacitance

Test Conditions
VIN = 2.0V @ f = I MHz

Min

Max
7

Units

pF
Output Capacitance
VOUT = 2.0V@f= I MHz
8
CoUT
Notes:
1. These are absolute values with respect to device ground and all over10. This difference parameter is designed to guarantee that any
shoots due to system or tester noise are included.
CY7C330 output fed back to its own inputs externally or internally
will satisfy the input register minimum input hold time. This param2. Not more than one output should be tested at a time. Duration of the
eter is guaranteed for a given individual device and is tested by a
short circuit should not be more than one second. VOUT = 0.5V has
periodic sampling of production product.
been chosen to avoid test problems caused by tester ground degradation.
11. This specification is intended to guarantee feeding of this signal to
another 33X family input register cycled by the same clock with
3. Tested iuitially and after any design or process changes that may
sufficient output data stable time to insure that the input hold time
affect these parameters.
minimum of the following input register is satisfied. This parameter
4. Figure 4a test load used for all parameters except tCEA, !eER. tpZX
difference specification is guaranteed by periodic sampling of prcr
and tpxz. Figure 4b test load for tcEA. teER. tpzx. tpxz.
duction product of CYC330 and CY7C332. This difference parameS. TA is the "instant on" case temperature.
ter is guaranteed to be met only for devices at the same ambient
6. See the last page of this specification for Group A subgroup testing
temperature and Vcc supply voltage.
information.
12. This specification indicates the guaranteed maximum frequency at
7. This parameter is sample tested periodically.
wbich a state macbine conftguration with external feed back can
operate.
8. This parameter is measured as the time after output register disable
input that the previous output data state remains stable on the output.
13. This specification indicates the guaranteed maximum frequency at
This delay is measured to the point at which a previous high level has
which an individual input or output register can be cycled.
fallen to O.SV below VOH Min or a previous low level has risen to
14. This specification indicates the guaranteed maximum frequency at
O.SVabove VOL Max. Please see Figure 6 for enable and disable test
which a state machine conftguration with only internal feedback can
waveforms and measurement reference levels.
operate. This parameter tested periodically on a sample basis.
9. This parameter is measured as the time after output register clock
15. Preliminary specifications.
input that the previous output data state remains stable on the output.

4-84

~
CY7C330
..,,-~~=======================================
Switching Characteristics Over the Operating Range[4. 6]
Military

Commercial
Parameters

Description

·66[15]

.50[15]

·33

·50

·40

Units

·28

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tiS

Input or Feedback Setup Time
to Input Register Clock

3

5

10

5

5

10

ns

tos

Input Register Clock to
Output Register Clock

15

20

30

20

25

35

ns

teo

Output Register Clock
to Output Delay

tIH

Input Register Hold Time

tCBA

Input Register Clock To
Output Enable Delay

15

20

30

20

25

35

ns

tCER

Input Register Clock to
Output Disable Delay[8]

15

20

30

20

25

35

ns

tpzx

Pin 14 Enable to Output
Enable Delay

15

20

30

20

25

35

ns

tpxz

Pin 14 Disable to Output
Disable Delay[8]

15

20

30

20

25

35

ns

12
5

15
5

20
5

15
5

20
5

25

ns
ns

5

tWH

Input or Output Clock Width High[3. 7]

6

8

12

8

10

15

ns

twx.

Input or Output Clock Width Low[3. 7]

6

8

12

8

10

15

ns

tp

External Clock Period (tco + tiS)
Input and Output Clock Common

15

20

30

20

25

35

ns

toH

Output Data Stable Time from
Synchronous Clock Input[9]

3

3

3

3

3

3

ns

toH-tIH

Output Data Stable Time
This Device Minus liP Reg
Hold Time Same Device[lO]

0

0

0

0

0

0

ns

toHtlH 33X

Output Data Stable Time Minus lIP
Reg Hold Time 7C330 & 7C332[1l]

0

0

0

0

0

0

ns

fMAXI

External Maximum Frequency
(1!(tco + tIS»[!2]

66.6

50.0

33.3

50.0

40.0

28.5

MHz

fMAX2

Data Path Maximum Frequency
(1!(tWH + twL»[7. 13]

83.3

62.5

41.6

62.5

50.0

33.3

MHz

/MAX3

Internal Maximum Frequency[14]

74.0

57.0

37.0

57.0

45.0

30.0

MHz

4·85

~

CY7C330

~r~~===================
AC Test Loads and Waveforms (Commercial)
R1
313A

INPUT PULSES

R1
313A

5v~(470AMIL)

3.0 v-----=..I~:::---:L

5V]1(470AMIL)

OUTPUT

OUTPUT

~~8A
I
-= -=
50pF

INCLUDING
JIG AND
SCOPE

I

(319A MIL)

5pF

~~8A

GND--....;;/I-

_

(319AMIL)
0101-10

FigureS

0101-9

Figure4a
Equivalent to:

Figure4b

THEVENIN EQUIVALENT (Commercial)
125A
OUTPUT

e>-JI/II'v-O

Switching Waveforms
I/O INPUTS. REGISTERED
fEEDBACK INPUTS

2.00V

Equivalent to:

THEVENIN EQUIVALENT (Military)
190D.

=Vthe

OUTPUT

e>-JI/II'v-O

2.02V

=Vthm

0101-11

0101-12

=t

_ _ _ __
tiS

INPUT CLOCK

-----1

OUTPUT CLOCK _ _ _ _ _ _ _-'1

OUTPUTS

::::~--$:::l~t::::J~----~~::=

tpxi811
PINM

~

~-----------------------

4-86

0101-13

L011mffi~ttmtffi~rmffW·H#3m#~4~4~~.5~~.6~R~~~~no~de'=~29~1

L66

9~

L1/U/r

~~

~
,,~~

V

L792.

~8(CO .. 3)

node =40

~2(CO .. 2)

L2178

~5(CO .• 3)

L[iH
node=39

L30361111111111111

LffH~~~"• • •
L5280•

~2(CO •• 3)

node=38

f{ffi6

•

(CO •• 2)

L6402

] node =34

) node =33

111111111111

111111

i . . - - - - - - - - - - T O LOWER SECTION _ _ _ _ _ _ _ _ _ _ _ _--1
0101-17

CY7C330 Block Diagram (Page 1 of 2)

4-87

~~================================~C~Y~7~O~30

I

r - - - - - - - - T O UPPER SECTION - - - - - - - - - -.....

"'''l 1111111111 111111111111111111

11111111 11111111 11111111

~

~,
L:..rI

~(CO .. 3)

~..-..

::
....

...

...i

~

nodt=37

.L

L963S._

F

I

~

17-rL

. . 1'

~) I• • • •
Lr"llG81!4'

113

mH~

:1-

.IIIIi

L13992

nodt=36

~~!§ lW~

Hi

~:
Ll.'"

I;'~ P;(~'J

Ll

AJ I

II
I 1111111IlItm~ ~ ~l\'TTI~'~I~(CO
R~A;1R.
!:

DE::-

m(CO .. 2)

A

~~

III

...>-===1
r-t )nod.=31

1111 n1f1l III 11111
~IIIIIII 111l1l1l1~1I1I

11111

IIImll IlIlIff

12~1I1I1I 3~1I111I1 ~ 1111111 ~

g

nod.=35

b

.. 2)

§

15~1I1I"· 6

SET

nodt=30

or
0101-18

CY7C330 Block Diagram (Page 2 of 2)

4-88

Parameter
tpxz(-)

V"
1.5V

tpxz(+)

2.6V

Output Waveform-Measurement Level

O.~V ~~

VOH

rt:
o·fv rt

o·rv

VOL

tpzx(+)

Vthc
Vx

tpzx(-)

Vthc
Vx
O}V

1.5V

tcER(-)

Vthc

o·fv

Vx

tcEA(-)

Vthc
Vx
O}V

rt
~t

Figure 6. Test Waveforms

Ordering Information
fllUl][(MHz)
66.6

Iccl (mA)
130

SO

150

50

130

40

150

33.3

130

28.5

150

Ordering Code
CY7C330-66PC
CY7C330-66WC
CY7C330-66JC
CY7C330-50DMB
CY7C330-50WMB
CY7C330-50LMB
CY7C330-50TMB
CY7C330-5OQMB
CY7C330-50PC
CY7C330-50WC
CY7C330-50JC
CY7C330-40DMB
CY7C330-40WMB
CY7C330-4OLMB
CY7C330-4OTMB
CY7C330-4OQMB
CY7C330-33PC
CY7C330-33WC
CY7C330-33JC
CY7C330-28DMB
CY7C330-28WMB
CY7C330-28LMB
CY7C330-28TMB
CY7C330-28QMB

Package
P21
W22
J64
D22
W22
L64
T74
Q64
P21
W22
J64
D22
W22
L64
T74
Q64
P21
W22
J64
D22
W22
L64
T74
Q64

Operating Range
Commercial

4-89

Military

Commercial

Military

Commercial

Military

0101-19

0101-20

VOH
0101-21

~t

o·rv r~

VOL

tcEA(+)

1.5V

VOL

O.~V ~~

VOH

2.6V

tcER(+)

Vx
Vx

Vx
1.5V

0101-22

0101-19

Vx
0101-20

VOH
0101-21

VOL

0101-22

~
CY7C330
~~~~~=============================================================
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VIL

1,2,3

IIX

1,2,3

Ioz

1,2,3

Icc

1,2,3

Switching Characteristics
Parameters

Subgroups

tISU

9,10,11

tosu
teo

9,10,11

1M

9,10,11

tCBA

9,10,11

tpzx

9,10,11

9,10,11

Document #: 38-00064-B

4-90

CY7C331

CYPRESS
SEMICONDUCTOR

Asynchronous Registered
EPLD

Features

Product Characteristics

• 12 I/O macrocells each having:
- One state Flip-Flop with an
XOR sum or products input
- One feedback Flip-Flop with
input coming from the I/O
pin
- Independent (product term)
set, reset, and clock inputs on
all registers
- Asynchronous bypass
capability on all registers,
under product term control

The CY7C33I is the most versatile
PLD available for asynchronous designs. Central resources include 12 full
D-type Flip-Flops with separate set, reset and clock capability. For increased
utility, XOR gates are provided at the
D-inputs and the product term allocation per Flip-Flop is variably distributed.

• 13 inputs, 12 feedback I/O pins,
plus 6 shared I/O macrocell
feedbacks for a total of 31 true
and complementary inputs
• High speed: 20 tpn ns maximum
• Security bit
• Space saving 28 pin slim-line
DIP package; also available in
28 pin PLCC

I/O Resources

• Low power
- 90 mA typical Icc quiescent
- 180 mA Icc maximum
- UV-Eraseable and
reprogrammable
- Programming and operation
100% testable

(r=s=l)
- Global or local output enable
on tristate I/O
- Feedback from either register
to the array
• 192 product terms with variable
distribution to macrocells

Pins I through 7 and 9 through 14
serve as array inputs; pin 14 may also
be used as a global output enable for
the I/O macrocell tristate outputs. Pins
15 through 20 and 23 through 28 are
connected to I/O macrocclls and may
be managed as inputs or outputs depending on the configuration and the
macrocell OE terms.

Block Diagram and DIP Pinout
PLCCPinout

o

"'C"oI

-

0

0. lID

:~~~~~g

0100-2

0100-1

Selection Guide
Generic
Part Number

Com

CY7C331-20[l9]

120

CY7C331-25

120

CY7C331-30
CY7C331-35
CY7C331-40

tpDns

IcclmA
Mil

Com
20

150[19]

Com

Mil

12
25[19]

25

150
120

tcons

tsns
Mil

12

30
35
40

4-91

Mil

20
15[19]

25

15
15

150

Com

25[19]
30

35
20

40

II
•

~
'CY7C331
,...,~~~=============================================================

I/O Resources (Continued)
It should be noted that there are two ground connections
(pins 8 and 21) which, together with Vee (pin 22) are
located centrally on the package. The reason for this placement and dual ground structure is to minimize the groundloop noise when the outputs are driving simultaneously
into a heavy capacitive load.

OUTPUT FROM
LOGIC ARRAY
FEEDBACK TO
LOGIC ARRAY
Q - OUTPUT FROM
INPUT REGISTER OF
I/o MACRO CELL A

INPUT TO
LOGIC ARRAY
Q - OUTPUT FROM
INPUT REGISTER OF
I/O MACRO CELL B

co
OUTPUT FROM
LOGIC ARRAY

I/O
PIN

MACRO CELL B
FEEDBACK TO
LOGIC ARRAY

0100-4

Figure 2. Shared Input Multiplexer
Shared Input Multiplexer
The input associated with each pair of macrocells may be
configured by the shared input multiplexer to come from
either macrocell; the 'Q' output of the Flip-Flop coming
from the I/O pin is used as the input signal source.

TO ARRAY

Product Term Distribution
The product terms are distributed to the macroce1ls such
that 32 product terms are distributed between two adjacent
macrocells. The pairing of macrocells is the same as it is for
the shared inputs. 8 of the product terms are used in each
macrocell for set, reset, clock, OE and the upper part of the
XOR gate. This leaves 16 product terms per pair of macrocells to be divided between the sum-of-product inputs to
the two state registers. The following table shows the I/O
pin pairing for shared inputs, and the product term
(p-Term) allocation to macrocells associated with the I/O
pins.
Table 2

INPUT REGISTER RESET PRODUCT TERM

TO ARRAY

FROM ADJACENT WACROCELL INPUT

0100-3

Figure 1. Macrocell
The CY7C331 has 12 macrocells. Each macrocell has two
D-type Flip-Flops. One is fed from the array, and one is fed
from the I/O pin. For each Flip-Flop there are 3 dedicated
product terms driving the R, S, and Clock inputs respectively. Each macrocell has one input to the array and for
each pair of macrocells there is one shared input to the
array. The macrocell input to the array may be configured
to come from the 'Q' output of either Flip-Flop.
The D-type Flip-Flop which is fed from the array (Le., the
state Flip-Flop) has a logical XOR function on its input
which combines a single product term with a sum (OR) of
a number of product terms. The single product term is used
to set the polarity of the output or to implement toggling
(by including the current output in the product term).
The R and S inputs to the Flip-Flops override the current
setting of the 'Q' output. The S input sets 'Q' true and the
R input 'resets' 'Q' (sets it false). If both R and S are asserted (true) at once, then the output will follow the input
('Q' = 'D').
S

Q

1
0
1

0
1
1

0
1
D

Pin Number

Product Terms

0
1
2
3
4
5
6
7

28
27
26
25
24
23
20
19
18
17
16
15

4
12
6
10
8

8

9
10
11

8

8
8
10
6
12
4

The CY7C331 is configured by three arrays of configuration bits (CO, CI, C2). For each macrocell, there is one CO
bit and one Cl bit. For each pair of macrocells, there is one
C2 bit.
There are 12 CO bits. If CO is programmed for a macrocell,
then the tristate enable (OE) will be controlled by pin 14
(the global OE). If CD is not programmed, then the OE
product term for that macrocell will be used.

Table 1
R

Macrocell

There is one Cl bit for each macrocell. The Cl bit selects
input for the product term (PT) array from either the state
register (if the bit is unprogrammed) or the input register.

R-S Truth Table
4-92

~

CY7C331

~r~~===================
I/O Resources

(Continued)

There are 6 C2 bits, providing one C2 bit for each pair of
macrocel1s. The C2 bit controls the shared input Multiplexer (Mux); if the C2 bit is not programmed, then the
input to the product term array comes from the upper macrocell (A). If the C2 bit is programmed, then the input
comes from the lower macrocell (B).

The timing diagrams for the CY7C331 cover state register,
input register, and various combinational delays. Since internal clocks are the outputs of product terms, all timing is
from the transition of inputs causing the clock transition.

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... - 65°C to + 150"C
Latchup Current .......................... > 200 mA
Ambient Temperature with
Power Applied .................... - 55°C to

DC Programming Voltage ...................... 13.0V

+ 125°C

Supply Voltage to Group Potential
(Pin 22 to Pins 8 or 21) ............... -0.5V to
DC Input Voltage ................... - 3.0V to

Operating Range

+ 7.0V
+ 7.0V

Ambient
Temperature

Range
Commercial
Military [5)

Output Current into Outputs (Low) ............. 12 mA
Static Discharge Voltage ..................... > 2001 V
(per MIL-STD-883 Method 3015)

Vee

+ 75°C
55°C to + 125'C

O"C to
-

5V ±IO%
5V ±IO%

Electrical Characteristics Over the Operating Range[61
Parameters
Vou
VOL

Description
Output HIGH Voltage
Output LOW Voltage

Min.

Test Conditions
Vee = Min.,
VIN = VIH or VIL

lOU = -3.2rnA

Commercial

lOU = -2rnA

Military

Vee = Min.,
VIN = VIH or VIL

10L = 12mA

Commercial

10L = SmA

Military

VIU

Input HIGH Level

Guaranteed HIGH Input, all Inputs[ll

VIL

Input LOW Level

Guaranteed LOW Input, all InputsU)

Max.

Units
V

2.4
0.5

V

O.S

V
p,A

2.2

< VIN < Vee, < Vee = Max.
< VOUT < Vee

V

IIX

Input Leakage Current

VSS

-10

10

IOZ

Output Leakage Current

Vee = Max., VSS

-40

40

p,A

Ise

Output Short Circuit Current

Vee = Max., VOUT = 0.5V[2)

-30

-90

mA

Ieel

Standby Power Supply
Current

Vee = Max., VIN = GND,
Outputs Open

Commercial

120

rnA

Military

150

mA

Power Supply Current
at FrequencyU9)

Vee = Max.
Outputs Disabled (in HIGH Z State)
Device Operating at !MAx
External (fMAXI)

Commercial

ISO

rnA

Military

200

mA

lee2

Capacitance [3]
Parameters

Description

Test Conditions

Min.

Max.

CIN

Input Capacitance

VIN = 2.0V @ f = 1 MHz

7

CoUT

Output Capacitance

VOUT=2.0V@f=IMHz

S

Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degrada-

Units
pF

3. Tested initially and after any design or process changes that may
affect these parameters.
4. Figure 3a test load used for all parameters except tpZXI, tpXZl, tpzx
and tPXZ. Figure 3b test load for tpZXI • tpXZI. tpzx and tpxz. Figure
3c shows test waveforms and meaaurement levels.
S. TA is the "instant on" case temperature.
6. See the last page of this specification for Group A subgroup testing
information.

tion.

4-93

II

~

CY7C331

~r~~====================
Switching Characteristics[6]
Military

Commercial
Parameters

Description

.20[19]

·25

.25[19]

·35

·40

·30

Units

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tpo

Input to Output Propagation Delay[7]

20

25

35

25

30

40

tlCO

Input Register Clock to Output Delay[S]

35

40

55

45

50

65

tlOH

Output Data Stable Time from Input Clock [S]

5

5

5

5

5

5

os

tiS

Input or Feedback Setut Time
to Input Register Clock S]

2

2

2

5

5

5

ns

tlH

Input Register Hold Time from Input Clock[S]

11

tlAR

Input to Input Register
Asynchronous Reset Delay[S]

13

13

15
40

35

55

15
45

20
50

ns
ns

ns
65

ns

tlRW

Input Register Reset Width[S]

35

40

55

45

50

65

ns

tlRR

Input Register Reset Recovery Time[S]

35

40

55

45

50

65

ns

tlAS

Input to Input Register
Asynchronous Set Delay[S]

tlSW

Input Register Set Width[8]

35

40

55

45

50

65

tlSR

Input Register Set Recovery TimdS]

35

40

55

45

50

65

ns

tWH

Input & Output Clock Width Righ[8, 9, 12]

12

15

20

IS

20

25

os

tWL

Input & Output Clock Width Low[S, 9, 12]

12

15

20

15

20

25

os

fMAXI

Maximum Frequency with Feedback in Input
Registered Mode (1/(tICO + tIS»[13]

27.0

23.8

17.5

20.0

18.1

14.2

MHz

fMAX2

Maximum Frequency Data Path in Input
Registered Mode (1/tICO)[8]

28.5

25.0

18.1

22.2

20.0

15.3

os

tlOHtlH33X

Output Data Stable from Input
Clock Minus Input Register Input Hold
Time for 7C330 and 7C332[!5, 18]

0

0

0

0

0

0

ns

teo

Output Register Clock to Output Delay [9]

tOH

Output Data Stable Time from Output Clock[9]

ts

Output Register Input Set Up Time to
Output Clock[9]

12

tH

Output Register Input Hold Time from
Output Clock[9]

8

toAR

Input to Output Register
Asynchronous Reset Delsy[9]

tORW

Output Register Reset Width[9]

20

25

35

25

30

40

ns

toRR

Output Register Reset Recovery Time[9]

20

25

35

25

30

40

ns

toAS

Input to Output Register
Asynchronous Reset Delay[9]

tosw

Output Register Set Width[9]

20

25

35

25

30

40

ns

tosR

Output Register Set Recovery Time[9]

20

25

35

25

30

40

os

40

35

20
3

45

55

25

35

50

25

65

ns

40

30

ns

ns

3

3

3

3

ns

12

15

15

15

20

ns

8

10

10

10

12

ns

3

25

20

20

35

25

25

25

3S

40

30

30

40

ns

ns

tEA

Input to Output Enable Delay[4, IOJ

20

25

35

25

30

40

ns

tER

Input to Output Disable Delay[4, 10]

20

25

35

2S

30

40

ns

tpzx

Pin 14 to Output Enable Delsy[4, 10]

17

20

30

20

25

35

ns

tpxz

Pin 14 to Output Disable Delsy[4, 10]

17

20

30

20

25

35

os

fMAX3

Maximum Frequency with Feedback in Output
Registered Mode (1/(too + ts» [!4J

31.2

27.0

20.0

25.0

22.2

16.6

MHz

fMAX4

Max. Frequency Data Path in Output Registered
41.6
Mode (Lower of 1/tco + 1/(twH + twL»[9)

33.3

25.0

33.3

25.0

20.0

MHz

toHtIH33X

Output Data Stable from Output
Clock Minus Input Register Input Hold
Time for 7C330 and 7C332[!6, 18]

0

0

0

0

0

0

ns

fMAX5

Maximum Frequency Pipelined Mode[!2, 17]

35.0

30.0

22.0

28.0

23.5

18.5

MHz

4-94

~
CY7C331
~~~~================================================================
Notes:
7.
8.
9.
10.
II.
12.
13.
14.
IS.
16.

Refer to Figure 5 configuration I.
Refer to Figure 5 configuration 2.
Refer to Figure 5 configuration 3.
Refer to Figure 5 configuration 4.
Refer to Figure 5 configuration 5.
Refer to Figure 5 configuration 6.
Refer to Figure 6 configuration 7.
Refer to Figure 6 configuration 8.
Refer to Figure 7 configuration 9.
Refer to Figure 7 configuration 10.

17. This specification is intended to guarantee that a state machine configuration created with internal or external feedback can be operated
with output register and input register clocks controlled by the same
source. These parameters are tested by periodic sampling of production product.
18. This specification is intended to guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C331. This
specification is met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling of production product.
19. Prelimiuary specifications.

AC Test Loads and Waveforms
Rl 313.0.
(470.0. MIL)

R1313.1l
(470.0. MIL)

OUTP~~n
50 pf

INCLUDING
JIG AND
SCOPE

OUTP~~

R2
208.1l
(319.1l MIL)

I
-

n

5 pf

INPUT PULSES

3.0 v----~~..,...--....,.!_

R2
208.0.
(319.0. MIL)

I

GND--.....;;;r

s: 5 ns

-

0100-6
0100-5

Figure3a

Figure3b

Equivalent to: THEVENIN EQUIVALENT (Commercial)
125.1l

OUTPUT G--JI/IIIr---O 2.00V

Parameters
tpxz(-)

=Vthc

Equivalent to: THEVENIN EQUIVALENT (Military)
190.0.
OUTPUT G--JI/IIIr---O 2.02V

0100-7

o.~v

2.6V

0~5V

VOL

tpZX(+)

Vthc

0~5V

Vx

tpZX(-)

Vthc
olv

1.5V

o.~V

VOH.

tER(+)

2.6V

0~5V

VOL

tEA(+)

Vthc
O}V

Vx

tEA(-)

Vthc

o.~V

Vx

Figure 3e. Test Waveforms

~

~
~

~

Vx

tER(-)

=Vthm

0100-8

Output Waveform-Measurement Level

Vx
1.5V
VOH

tpXZ(+)

Figure 4

~

r
~
~

and Measurement Levels

4-95

Vx

0100-16

Vx

0100-17
VOH

0100-18

VOL

0100-19

Vx

0100-16

Vx

0100-17
VOH

0100-18

VOL

0100-19

~

CY7C331

..,,-~~====================================~
Switching Waveforms
INPUT OR
I/O PIN
I/O INPUT
REGISTER
CLOCK [20]
OUTPUT
REGISTER
CLOCK [20]
OUTPUT

~-------~D------~

'oRR' tOSR [24]
SET AND
RESET
INPUTS [20]

QE PRODUCT
TERM INPUTl1 0, 20]

0100-9

---,

)(

f.-tEA-

L

PIN 14 AS QE[ll1

OUTPUT
OUTPUT
REGISTER
RESET INPUTl9,20]

- ~PXZI-\\

-

tpzx
I

fo- tER_

f--'oAR-

I--'oRW-

OUTPUT
REGISTER
CLOCK [9,20]

I-- to AS ___

OUTPUT
REGISTER
SET INPUTl9,20]
_
I/O INPUT
REGISTER
RESET INPUTlS,20]
I/O INPUT
REGISTER
CLOCK [S,20]
I/O INPUT
REGISTER
SET INPUTlS,20]

'oRR -

t

lAR

_

f--tosw -

~IosR"

-

_tIRW ___
tlRR _

----{~=itlAS

Notes:
20. Because these input signals are controlled by product terms, active
input polarity may be of either polarity. Internal active input polarity
has been shown for clarity.
21. Output register is set in Transparent Mode. Output register Set and
Reset inputs are in a HIGH state.
22. Dedicated input or input register set in Transparent Mode. Input
register Set and Reset inputs are in a HIGH state.
23. Combinatorial Mode. Reset and Set inputs of the in~ut and output
registers should remain in a HIGH state at least until the output
responds at tpD. When returning Set and Reset inputs to a LOW
state, one of these signals should go LOW a MINIMUM of tosa (Set
input) or toRR (Reset input) prior to the other. This guarantees
predictable register states upon exit from Combinatorial Mode.

t lSR ..

0100-10

24. When entering the Combinatorial Mode, input and output register
Set and Reset inputs must be stable in a HIGH state a MINIMUM
of tlsa/tlRR and tOsvtoRR respectively prior to application oflogic
input signals.
25. When returning to the input and/or output Registered Mode. register Set and Reset inputs must be stable in a LOW state a
MINIMUM of tlSRltlRR and tosRltoRR respectively prior to the
application of the register clock input.

4-96

(;r~ccwucroR

CY7C331

~PR~~~CTI

B

CONFIGURATION 1

~

ARRAY

INPUT OR I/O PIN

OE

I/O PIN
0100-11

CLOCK/SIR
INPUT

PIN
CONFIGURATION 2

UNREGISTERED
INPUT OR I/O PIN

PRODUCT
TERM
ARRAY

II
0100-12

PIN
CONFIGURATION 3

PRODUCT
TERM
ARRAY

UNREGISTERED
INPUT OR I/O PIN
CLOCK/SIR
INPUT

PIN
UNREGISTERED
INPUT OR I/o PIN

0100-13

PIN
CONFIGURATION 4

PRODUCT
TERM
ARRAY

INPUT OR I/O PIN
PIN
INPUT OR I/o PIN

I/O PIN
0100-14

CONFIGURATION 5

14
INPUT OR I/O PIN

PRODUCT
TERM
ARRAY

PIN
INPUT OR I/O PIN

0100-15

INPUT
REGISTER

CONFIGURATION 6
UNREGISTERED
INPUT OR I/o PIN

OUTPUT
REGISTER

CLOCK

PRODUCT
TERM
ARRAY

CLOCK

0100-20

Figure 5. Timing Configurations

4-97

~
CY7C331
~~~~==========================================================
DATA INPUT

INPUT REGISTER

PRODUCT
TERM
ARRAY
CONFIGURATION 7

0100-21

OUTPUT REGISTER

CONFIGURATION 8

0100-22

CONFIGURATION 9

0100-23

Figure 6

CONFIGURATION 10

PRODUCT
TERM
ARRAY

CLOCK
0100-26

Figure 7
4-98

~
CY7C331
~~~~u~================================================================
o
1

8

16

24

32

40

48

56

-=--

,....L.

LO

4 (CO •• l)

rrr= Mm
28

4:;

a

2
L806

node 34
L11906 ( C2)
7 (CO •• l)

4m

II

27

rTF:::

=I..r-

12-D-'

3
L1984

6::
4
L2852

'f
a

Hm

(CO •• l)

26

node 33
L11911 ( C2)

2 (CO •• l)

Km
25

10.....

....,

n=!===
=. .

5
L3968
24
~

4 (CO •• l)

'4a

6
L4960

node 32
L11916 ( C2)

7 (CO •• l)

8

-rJF~
=I...r....,

23
~

m
TO LOWER SECTION
0100-24

CY7C331 Logic Diagram (Upper Half)

4-99

TO UPPER SECTION

I
...L.

L5952

20
~

.~
9

node 31
L11921 (C2)

0

L69«

(CO •• l)

L11922 (CO •• l)

8

Hill

'-o--fT~

10
L7930

HID

(CO •• l)

18

10......
'-'

rFr

[J

11
L9052

6-o-ff=
12
L9920

i-

nod. 30
L11926 ( C2)

17
~

(CO •• l)

~

(CO•• l)

I
16

12

rFr

'D---

[J

(ill
L11160

4 ......
14

I

r.=1:::

i-r

nod. 29
L11931 ( C2)

15
~

(CO •• l)

1
0100-26

CY7C331 Logic Diagram (Lower Half)

4-100

~

CY7C331

~~~NDUcrOR ================================================================~
Ordering Information
ICCl
(rnA)

tpD
(ns)

ts
(ns)

tco
(ns)

120

20

12

20

150

180

200

180

200

25

25

30

35

40

15

12

15

15

20

25

25

30

35

40

Package
Type

Operating
Range

CY7C331-20PC

P21

Commercial

CY7C331-20WC

W22

Ordering Code

CY7C331-20JC

J64

CY7C331-25DMB

D22

CY7C331-25WMB

W22

CY7C331-25LMB

L64

CY7C331-25TMB

T74

CY7C331-25QMB

Q64

CY7C331-25PC

P21

CY7C331-25WC

W22

CY7C331-25JC

J64

CY7C331-30DMB

022

CY7C331-30WMB

W22

CY7C331-30LMB

L64

CY7C331-30TMB

T74

CY7C331-30QMB

Q64

CY7C331-35PC

P21

CY7C331-35WC

W22

CY7C331-35JC

J64

CY7C331-40DMB

022

CY7C331-40WMB

W22

CY7C331-40LMB

L64

CY7C331-40TMB

T74

CY7C331-40QMB

Q64

4-101

Military

III
Commercial

Military

Commercial

Military

~
CY7C331
~~~~aDR================================================================
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIR

1,2,3

VIL

1,2,3

IIX

1,2,3

IOZ

1,2,3

ICC!

1,2,3

Switching Characteristics
Parameters

Subgroups

tIS

9,10,11

tIR

9,10,11

tWH

9,10,11

tWL

9,10,11

tco

9,10,11

tPD

9,10,11

tIAR

9,10,11

tIAS

9,10,11

tpxz

9,10,11

tpzx

9,10,11

tER

9,10,11

tEA

9,10,11

ts

9,10,11

tH

9,10,11

Document #: 38-00066-B

4-102

CY7C332

CYPRESS
SEMICONDUCTOR

Registered Combinatorial
EPLD
Product Characteristics

Features
• 12 I/O macrocells each having:
- Registered, latched, or
transparent array input
- A choice of two clock sources
- Global or local output enable
(OE)
- Up to 19 product terms (PT)
per output
- Product term (PT) output
polarity control

• 192 product terms with variable
distribution to macrocells
- An average of 14 PT's per
macrocell sum node
- Up to 19 PT's maximum for
select nodes
• 2 clock inputs with configureable
polarity control

The CY7C332 is a versatile combinatorial PLD with I/O registers onboard.
There are 25 array inputs; each has a
macrocell which may be configured as
a register, latch or simple buffer. Outputs have polarity and tristate control
product terms. The allocation of product terms to I/O macrocells is varied so
that functions of up to 19 product
terms can be accommodated.

• 13 input macrocells, each having:
- Complementary input
- Register, latch, or transparent
access
- Two clock sources
• 20 ns max. delay
• Low power
- 120 rnA typical Icc quiescent
-180 mA max.
- Power saving "Miser Bit"
feature

I/O Resources

• Security fuse
• 28 pin slim-line package; also
available in 28 pin PLC

Pins 1 through 7 and 9 through 14
function as dedicated array inputs. Pins
1 and 2 function as input clocks as well
as normal inputs. Pin 14 functions as a
global output enable as well as a normal input.

• UV-Eraseable and
reprogrammable
• Programming and operation
100% testable

Block Diagram and Pinout
LCC and PLCC Pinout

O-N

-.:-

-

-OGleD

--00

I~ ~~~~
0134-2

0134-1

Selection Guide
Generic
Part Number

Com

7C332-20

120

7C332-25

120

7C332-30

4co/tpDns

IcclmA
Mil

Com

tIsns
Mil

20
150

25

4-103

Mil

3
25
30

150

Com
3

4
4

II
•

~
CY7C332
~~~NDUcrOR===================================================================
I/O Resources

If C3 is 1 (programmed), the clock will be falling edge
triggered (register mode) or low asserted (latch mode).

(Continued)

PINIDr---~-\[:rCKI

I/O Macrocell
There are 12 I/O macrocells corresponding to pins 15
through 20 and 23 through 28. Each macrocell has a tristate output control, an XOR product term to dynamically
control polarity, and a configureable feedback path.
For each I/O macrocell, the tristate control for the output
may be configured two ways. If the configuration bit, C4, is
a 1 (programmed), then the global OE signal is selected.
Otherwise, the OE product term is used.
For each I/O macrocell, the input/feedback path may be
configured as a register, latch, or shunt. There are two
configuration bits per I/O macrocell which configure the
feedback path. These are programmed in the same way as
for the input macrocells.
For each I/O macrocell, the input register clock (or Latch
Enable) which is used for the input/feedback path may be
selected as pin 1 (select bit, C2, not programmed) or pin 2
(select bit, C2, programmed).

PIN1.S0

r

PIN2 D I - - -""')[:rcK2
PIN2.S0

0134-3

Figure 1. CK1 and CK2
Pins 15 through 20 and 23 through 28 are connected to
I/O macrocells and may be combinatorial outputs as well
as registered or direct inputs.
Input Macrocell
INPUT REGISTER
IN~~TH

_ _ _ _ _ _ _ _ _-I

PIN l,CK1

Array Allocation to Output Macrocell
The number of product terms in each output macrocell
sum is position dependent. The table below summarizes the
allocation:
Table 1

PIN 2.CK2

C2

CO

C1

Figure 2. Input Macrocell

0134-4

C3

C2

Cl

CO

Input Register Option

X
X
0
0
1
1
0
0
1
1

X
X
0
1
0
1
0
1
0
1

0
0
I
1
1
1
1
1
1
1

0
I
1
1
1
1
0
0
0
0

Combinatorial
Illegal
Registered, CLKl, Rising Edge
Registered, CLK2, Rising Edge
Registered, CLKl, Fallling Edge
Registered, CLK2, Falling Edge
Latched, CLKl, High Asserted
Latched, CLK2, High Asserted
Latched, CLK I, Low Asserted
Latched, CLKl, Low Asserted

Macrocell

Pin Number

Product Terms

0

28
27
26
25
24
23
20
19
18
17
16
15

9
19

1
2
3
4
5
6
7
8
9
10
11

There are 13 input macrocells, corresponding to pins 1
through 7 and 9 through 14. Each macrocell has a clock
which is selected to come from either pin I or pin 2 by
configuration bit C2. Pins 1 and 2 are clocks as well as
normal inputs. There is no C2 configuration bit for either
of these two input macrocells. Macrocells connected to
pins I and 2 do not have a clock choice, but each has a
clock coming from the other pin.
Each input macrocell can be configured as a register, latch
or a simple buffer (transparent path) to the product term
array. For a register the configuration bit, CO, is 1 (programmed) and Cl is 1. For a Latch, CO is 0 and Cl is 1. If
both CO and Cl are 0 (unprogrammed) then the macrocell
is completely transparent.
Configuration bit C3 determines the clock edge on which
the register is triggered or the polarity for which the latch
is asserted. This clock polarity can be programmed independently for each input register. These configuration options are available on all inputs, including those in the I/O
macrocell.
If C3 is 0 (unprogrammed), the clock will be rising edge
triggered (register mode) or high asserted (latch mode).

11

17
13
15
15
13

17
11

19
9

PIN 14 INVERTED, i5E

C4

MACRO CELL
INPUT REGISTER
TO ARRAY

PIN 2,CK2
PIN I,CKI

0134-5

Figure 3. I/O Macrocell
4-104

~

CY7C332

~r~~===================

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... - 65°C to + 150"C

Latch-up Current .......................... > 200 mA

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

DC Programming Voltage ...................... 13.0V

Operating Range

Supply Voltage to Ground Potential
(Pin 22 to Pins 8 and 21) .............. -0.5V to + 7.0V

Range

DC Input Voltage ................... -3.0V to +7.0V
Output Current into Outputs (Low) ............. 12 rnA

Commercial

Static Discharge Voltage ..................... > 200 1V
(per MIL-STD-883, Method 3015)

Military [S)

Ambient
Temperature
O"C to

Vee

+ 75°C
+ 125°C

- 55°C to

5V ±1O%
5V ±1O%

Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL

Description
Output HIGH Voltage
Output LOW Voltage

Test Conditions

= -3.2mA
IOH = -2rnA
IOL = 12mA
IOL = 8mA

Vee = Min.,
VIN = VIH or VIL

IOH

Vee = Min.,
VIN = VIH or VIL

VIH

Input LOW Level

Guaranteed HIGH Input, all Inputs[!)

VIL

Input LOW Level

Guaranteed LOW Input, all Inputs[l)

IIX

Input Leakage Current

Vss

loz

Output Leakage Current

< VIN < Vee, Vee = Max.
Vee = Max., Vss < VOUT < Vee

Ise

Output Short Circuit Current

Vee

ICC!

Standby Power Supply
Current

Vee = Max., VIN
Outputs Open

Power Supply Current
at Frequency[6,8)

Vee = Max.
Outputs Disabled (In High Z State)
Device Operating at !MAX
External (fMAX!)

leC2

Min.
Commercial

Max.

Units

2.4

V

Military
Commercial

0.5

V

Military
V

2.2
0.8

V

10

p.A

-10
-40

40

p.A

= Max., VOUT = 0.5V[2)

-30

-90

mA

= GND

Commercial

120

mA

Military

150

rnA

Commercial

180

rnA

Military

200

rnA

Capacitance [3]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions

= 2.0V @ f = I MHz
VOUT = 2.0V@f= I MHz
VIN

Notes:
1. These are absolute values with respect to device ground and allover·
shoots due to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degrada·
tion.

Min.

Max.
7

Units
pF

8

3. Tested initially and after any design or process changes tha may affect
these parameters.
4. Figure 4a test load used for all parameters except tllA> tER, tpzx and
tpxz. Figure 4b test load for tEA, tER, tpzx, tpxz. Figure 4c shows
test waveforms and measurement reference levels.
S. TA is the "instant on" case temperature.
6. Tested by periodic sampling of production product.

4-105

II

Switching Characteristics Over the Operating Range U]
Military

Commercial
Parameters

-20

Description

-25

-25

Units

-30

Min. Max. Min. Max. Min. Max. Min. Max.
tPD

Input to Output Propagation Delay[7)

20

25

25

30

ns

tICO

Input Register Clock to Output Delay[S)

20

25

25

30

ns

tIS

Input or Feedback Setup Time
to Input Register Clock[S)

3

tIH

Input Register Hold Time[S)

3

tEA

Input to Output Enable Delay[4, 9)

20

25

25

30

ns

tER

Input to Output Disable Delay[4, 9)

20

25

25

30

ns

tpzx

Pin 14 Enable to Output Enable Delay[4, 10]

IS

20

20

25

ns

tpxz

Pin 14 Disable to Output Disable Delay[4, 10)

15

20

20

25

ns

tWH

Input Clock Width High[6, S)

10

10

10

12

ns

tWL

Input Clock Width Low[6, S)

10

10

10

12

ns

tlOH

Output Data Stable Time from
Input Register Clock Input[S, 14]

3

3

4

4

ns

0

0

0

0

ns

0

0

0

0

ns

23

28

29

34

ns

43.4

35.7

34.4

29.4

MHz

50.0

40.0

40.0

33.3

MHz

tIOH-tIH

Output Data Stable Time This Device
, Minus lIP Reg Hold Time Same Device [! I, 12, 14)

Output Data Stable Time Minus lIP Reg
tOH-tIH 33X Hold Time 7C330 & 7C332 Device[!3, 14)

+ tIS)[S)

tPE

External Clock Period (tICO

fMAXI

Maximum External Operatin~
Frequency (l/(tlCO + tIS»[S

Maximum Frequency Data Path[S)
fMAX2
Notes:
7. Refer to Figure 8 configuration I.
S. Refer to Figure 8 configuration 2.
9. Refer to Figure 8 configuration 3.
10. Refer to Figure 8 configuration 4.
II. Refer to Figure 8 configuration 5.

3

4

3

4

4

ns

ns

4

12. This specification is intended to guarantee that configuration 5 of
Figure 8 with input registered feedback can be operated with all
input register clocks controlled by the same source. These parameters are tested by periodic sampling of production product.
13. This specification is intended to guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C332. This
specification is met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling of production product.
14, Preliminary specifications.

Switching Waveforms
INPUT
OR 1/0[151

~

""""

tlS[Bl

tlH[Bl'l

INPUT

lk

CLOCK[16]

I--- t EA[9l_
PIN II
AS OE

- ~tpxz[10l

tw~

~tWH

I---

---I

3k

I t pZX[10l

-f-

I

tIOH[B]

1-

OUTPUT

JfXXXXXJQG
j.--tER[ 9 ] -

tlco[B]
t pO[7]
0134-10

Notes:
15. Because OE can be controlled by the OE product term, input sigual
polarity for control ofOE can be of either polarity. Interually the
product term OE signal is active high.

16. Since the input register clock polarity is programmable, the input
clock may be rising or falling edge triggered.

4-106

~~========================================C=Y=7=C=33=2
AC Test Loads and Waveforms (Commercial)

ft ft
Rl 3134
(4704 MIL)

OUTP~;

Rl 31lA
(4704 MIL)

OUTP~;

50 pF'
INCLUDING

I

~~~

SCOPE

R2
2084
(3194 MIL)

5 pF'

INPUT PULSES
3.0V-----::J,."..,.,..,---~

R2
2084
(3194 MIL)

I

GND--.....;;Ir
s; 5 ns

--

-

0134-7

Figure 5. Input Pulses

0134-6

Figure4a

Figure4b
Equivalent to: THEVENIN EQillVALENT (Military)

Equivalent to: THEVENIN EQillVALENT (Commercial)
1254
OUTPUT~2.00V

1904

=VTHC

OUTPUT~2.02V

=VTHM
0134-9

0134-8

Parameter

Vx

tpxz(-)

1.5V

Output Waveform-Measurement Level
VOH

tpxz(+)

o·t

o·rv

Vthc
OfV

Vx

tpzx(-)

Vthc
Vx

tER(-)

O;5V

1.5V
VOH
olv

tER(+)

o·rv

Vthc
OfV

Vx

tEA(-)

Vx

0134-12

1:
1:
~
~t

Vx

0134-13

VOH

0134-14

VOL

Vx

0134-15

0134-12

2.6V
VOL

tEA(+)

~

2.6V
VOL

tpzx(+)

v

Vthc
Vx
ol5V

1:
't'
~

Figure 4c. Test Waveforms and Measurement Levels

4-107

Vx

0134-13

VOH

0134-14

VOL

0134-15

m1~0

16

8

24

32

40

48

(CO, 1,3) ;

(CO .. 4)
~
~ 0) l-ffi]
9~6:0:0:LO]IIIIIIIIIIIIIIIIIILI9~7~10~)(~IM~BO~"1
L9650

:
&4h
(C~~I~~~

II

==:i

:

fi3 ~

L550~
::~

~972HMB1Ll"31)
E
E

~

::~

(CO..

~

(CO )
44) L9660

~~16~0~0!11'IIIIIIIIIIIIIIIL9t7~42(!~MB32" }-fill
11

17
~

3)

~ )-1-~~3~20~0~~~~~~
3)

13
0---1};

(CL9618
O.. 3)

4)

E;
E;

17
(CO..

(L9655
CO..

§E ~
_---.,',~
rv'
~~-=r"""==1
~

(CO.. 3)
L9606

J,

~950•

L9665
L }-!ill
(co .. 4)

L

;r

(L9670
CO..

4)

)--ml

•Ia3L9789(MB79"95)
11
L9675
15 ~~

,
"'------------TO
LOWER SECTION ------

J

"
0134-16

CY7C332 Logic Diagram (Upper HalO

~
.
CY7C332
~r~~===================
r-----------To UPPER SECTION

----------...,

~I_r5iFm~I#ImI==l:*#l~

~ ~~~r-:48:0:01111111111111111ILI98:0:6(~MB9J6L
. . 112) ~
L9680

("U>

"

;m
,,, 16 Hm
~ ~ rs650'1~11~1~IIIIIIIIILI982:3~~I:il~3"127)
L9685

(roH'>

~ )-t~r~64~0~0~~~~~F*~~~~~

~

L9690

(CO •• 3)

(CO •• 4)

Itz

,

........

lffij3) 0350

_9857(M~47.

J

(CO ••

lffij3)

(CO ••

11

~

(CO •• 4)

Hill

~. 180)
L9870(MBI60
L9700
19

,
.I

159) L9695

t;ooo

(CO •• 4)

I===IIL-.....r'"""'l}---lm

IL9891 (MB1'81 .191) L9705
l!::::::f
L9642 L9050111111111111111_lt:~311 .rn~

[ill-{

)-t.

~

(CO •• 3)

~
(CO
•• 3)

~~

~
0134-17

CY7C332 Logic Diagram (Lower Half)

4-109

~

CY7C332

CYm.SS

"nlCONDUCIOR ===============================~
CONFIGURATION 1

PIN

TERM
t-------C~==l PRODUCT
ARRAY

INPUT OR I/O PIN

INPUT REGISTER

......1:'"'""_-1 PRODUCT
TERM
ARRAY

CONFIGURATION 2

CLOCK 1 OR 2

PIN L

I

_____-I~~=::j

CONFIGURATION 3

t-------I~~=:::t

PIN
INPUT OR I/O PIN

CONFIGURATION"

PRODUCT
TERM
ARRAY

....._ _...

I/O PIN

~~~--------------~
L-------I~~=:::1 PRODUCT
TERM

PIN I

INPUT OR I/O PIN

ARRAY
0134-11

INPUT REGISTER
DATA
INPUT
CONFIGURATION 5

PRODUCT
TERM
ARRAY

CLOCK 1 OR 2

CLOCK 1 OR 2

Figure 6. Timing Configurations

4-110

0134-18

~
CY7C332
~~~~============================================================~
Ordering Information
Iccl (max)

tICO/tpD (os)

txs (os)

txH (os)

120

20

3

3

150

120

150

25

25

30

4

3

4

4

3

4

Package
Type

Operating
Range

CY7C332-20PC

P21

Commercial

CY7C332-20WC

W22

Ordering Code

CY7C332-2OJC

164

CY7C332-250MB

022

CY7C332-25WMB

W22

CY7C332-25LMB

L64

CY7C332-25TMB

T74

CY7C332-25QMB

Q64

CY7C332-25PC

P21

CY7C332-25WC

W22

CY7C332-251C

164

CY7C332-300MB

022

CY7C332-30WMB

W22

CY7C332-30LMB

L64

CY7C332-30TMB

T74

CY7C332-30QMB

Q64

4-111

Military

II
Commercial

Military

CY7C340
ADVANCED ·INFORMATION

CYPRESS
SEMICONDUCTOR

Multiple Array MatriX
High Density EPLDs

Features

General Description

• Erasable, user-configurable
CMOS EPLDs capable of
implementing high density
custom logic functions

The Cypress Multiple Array MatriX
(MAXTM) family of EPLDs provides a
user-configurable, high-density solution to general purpose logic integra.tion requirements. With the combination of innovative architecture and
state of the art process, the MAX
EPLDs offer LSI density, without sacrificing speed.
The MAX architecture makes it ideal
for replacing large amounts of TTL SSI
and MSI logic. For example, a 74161
counter utilizes only 3% of the 128
Macrocells available in the CY7C342.
Similarly, a 74151 8 to 1 multiplexer
consumes less than one percent of the
over 1,000 product terms in the
CY7C342. This allows the designer to
replace 50 or more TTL packages with
just one MAX EPLD. The family
comes in a range of densities, shown
below. By standardizing on a few
MAX building blocks, the designer can
replace hundreds of different 7400 series part numbers currently used in
most digital systems.
The family is based on an architecture
of flexible Macrocells grouped together
into Logic Array Blocks (LABs). Within the LAB is a group of additional
product terms called Expander Product Terms. These Expanders are used
and shared by the Macroce1ls, allowing
complex functions, up to 3S product
terms, to be easily implemented in a
single Macrocell. A Programmable Interconnect Array (PIA) globally

• Advanced O.S micron doublemetal CMOS EPROM
technology
• Multiple Array MatriX
Architecture optimized for speed,
density and straightforward
design implementation
- Typical clock frequency =

SO MHz
Programmable Interconnect
Array (PIA) simplifies
routing
- Flexible Macrocells increase
utilization
- Programmable clock control
- Expander product terms
implement complex logic
functions
• MAX + PLUSTM development
system eases design
- Runs on IBM PC/ATTM and
compatible machines
- Hierarchical schematic
capture with 7400 series TTL
and custom Macrofunctions
- State machine and Boolean
entry
- Graphical delay path
calculator
- Automatic error location
- Timing simulation
- Graphical interactive entry of
waveforms
-

EPLDFamily

routes all signals within devices containing more than one LAB. This architecture is fabricated on the Cypress
advanced 0.8 micron double layer metal CMOS EPROM process, yielding
devices with 3 times the integration
density at twice the system clock speed
of the largest current generation
EPLD.
The density and flexibility of the
CY7C340 family is accessed using the
MAX + PLUS development system. A
PC based design system,
MAX + PLUS is optimized specifically
for the CY7C340 family architecture,
providing efficient design processing
within the time it takes to erase an
EPLD. A hierarchical schematic entry
mechanism is used to capture the design. State Machine, Truth Table and
Boolean Equation entry mechanisms
are also supported, and may be mixed
with schematic capture. The powerful
Design Processor performs minimization and logic synthesis, then automatically fits the design into the desired
EPLD. Design verification is done using a timing simulator, which provides
full A.C. simulation, along with an interactive graphic waveform editor
package to speed waveform creation
and debugging. During design processing a sophisticated automatic error locator shows exactly where the error occurred by popping the designer back
into the schematic at the exact error
location.

MAX Family Members
Feature
Macrocells
MAX Flip-Flops
MAX Latches[1]
MAX Inputs[2]
MAX Outputs
Packages
Key: D--- DIP

I - I-Lead Chip Carrier

CY7C344
32
32
64
23
16
28D
28J'

CY7C343
64
64
128
35
28
44J

CY7C345
128
128
256
35
28
44J

40D

40D

G- Pin Grid Array

Notes:
1. When aU Expander Product Terms are used to implement latches.

2. With one output.

PAL4I> i. a registered trademark of Monolithic Memories Inc.
IBM4I> i. a registered trademark of Intemational Business Machines Corpcration.
IBM PCI ATTM is a trademark of International Busine.s Machines Corpcration.
MAXTM and MAX +PLUSTM are trademarks of Altera Corporation.
Drawings courtesy of A1tera Corporation.

4-112

CY7C342
128
128
256
59

S2
68J'
680

~

cr7~~

W'r~ =======A=D=VA=N<=C='E='D=1=N='F1='OR==M==:A=1:=10;'N==~E;P~L~D~F~am
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DEDICATED
INPUTS

/\

1%

~~~~

~

[rt>-D

-

'~
lOGIC. __
AR RAY
BlOCK
(LAB)

V V

/V

-H>
- rt

t.IUlTIPlE
ARRAYS
(LABS)

M
 I l-

VV

DUAL

~

I/O

EEDBACK

/

EXPA NDER
PRO DUCT
TER loiS

-\
.~

\

\

4

~

t.IACROCEllS

PROGRAt.lt.lABlE
INTERCONNECT
ARRAY (PIA)
0138-2

Figure 1. Key MAX Features

4-113

~

ADVANCED INFORMATION

CY7C340
EPLD Family

"~~OCTOR =============================
Functional Description

provided within an LAB, giving each functional block
complete access to the LAB resources. The LAB itself is
fed by the Programmable Interconnect Array and dedicated input bus. The feedbacks of the Macrocells and I/O pins
feed the PIA, providing access to them by other LABs in
the device. The CY7C340 family EPLDs having a single
LAB use a global bus, and a PIA is not needed.

The Logic Array Block
The Logic Array Block, shown in Figure 2, is the heart of
the MAX architecture. It consists of a Macrocell Array,
Expander Product Term Array, and an I/O Block. The
number of Macrocells, Expanders, and I/O vary, depending upon the device used. Global feedback of all signals is

~-------------------------vo-·
~~

I

ICI
ICI
ICI
I
N
P
U

T
S

•••

P
I
A

PROGRAMMABLE
INTERCONNECT
ARRAY

0136-3

Figure 2. LAB Block Diagram

4-114

(;n~~====================~~~~~~~~==~~~~~y
ADVANCED INFORMATION
EPLD Famil

CY7C340

• CYPRESS

Functional Description (Continued)
The MAX Macrocell
Traditionally, PLDs have been divided into either PLA
(programmable AND, programmable OR), or PALTM
(programmable AND, fixed OR) architectures. PLDs of
the latt~r typ~ provide faster input-to-output delays, but
can be lneffic1ent due to fixed allocation of product terms.
Statistical analysis of PLD logic designs has shown that
70% of a11logic functions (per Macrocell) require 3 product terms or less.
The Macrocell structure of MAX has been optimiZed to
handle variable product term requirements. As shown in
Figure 3, each Macrocell consists of a product term array
and a configurable register. In the Macrocell, combinatoriallogic is implemented with 3 product terms OR'ed together, which ~hen feeds an XOR gate. The second input to
!he XOR ~~te 1S also contro!led by a product term, providIng the ab1hty to control act1ve high or active low logic.
The MAX + PLUS software will also use this gate to implem~nt complex ~utually exclusive-OR arithmetic logic
funct10ns, or to do DeMorgan's Inversion, reducing the
number of product terms required to implement a function.

If more product terms are required to implement a given
function, they may be added to the Macrocell from the
Expander Product Term Array. These additional product
terms may be added to any Macrocell, allowing the designer to build gate intensive logic, such as address decoders,
ad~ers, comparators, and complex state machines, without
uSing extra Macrocells.
The register within the Macrocell may be programmed for
either, D, T, JK, or SR operation. It may alternately be
configured as a flow-through latch for minimum input to
output delays, or by-passed entirely for purely combinatorial logic. In addition, each register supports both asynchronous preset and clear, allowing asynchronous loading
of counters or shift registers, as found in many standard
TTL functions. These registers may be clocked with a synchronous system clock, or clocked independently from the
logic array.

OUTPUT
ENABLE

• PROGRAMMABLE FLIP
FLOP (0, T, JK, SR)
• REGISTERED OR FLOW
THROUGH LATCH
OPERATION
• PROGRAMMABLE CLOCK
• ASYNC CLEAR AND
PRESET

SYSTEM
CLOCK

PRESET

P

~

Qt--

r---

....

,"",IARRAY
CLOCK

C

I

CLEAR

~

4~

4~

~

A

4~
A

PROGRAMMABLE
8
DEDICATED INTERRCONNECT
INPUTS
SIGNALS

>

> 4~

A

...

I-

-

TO I/o
CONTROL
BLOCK

~

MACROCELL
FEEDBACK

A
NOTE: One system clock
per LAB

32 EXPANDER
16
PRODUCT MACROCELL
TERMS
FEEDBACKS

0138-4

Figure 3. Macrocell Block Diagram

4-115

4

~nVw.AA'UVV''-''
ADVANCED INFORMATION EPLD Family
~CYPRFSS_n~~~==================~~~~~~~~CY~7~~~~
_

Functional Description (Continued)
~y d~oupling the I/O pi~s from the flip-flops, all the reglsters m the LAB are "buned", allowing the I/O pins to be
used as dedicated outputs, Bi-directional outputs or as additional d~ca~ed inputs. Therefore, applications requiring
many buned flip-flops, such as counters, shift registers, and
~tate machines, no longer consume both the Macrocell reglster and the associated I/O pin, as in earlier devices.

Expander Product Terms.
The Expander Product Terms, as shown in Figure 4 are
fed by the Dedicated Input Bus, the Programmable interconnect Array, the Macrocell Feedback, Expanders themselves, and the I/O pin feedbacks. The outputs of the Expanders then go to each and every product term in the
Macrocell Array. This allows Expanders to be "shared" by
the product terms in the Logic Array Block. One Expander
may feed all Macrocells in the LAB, or even multiple product terms in the same Macrocell. Since these Expanders
feed the secondary product terms (preset, Clear, Clock,
a.nd Output Enable) of each Macrocell, complex logic functlons may be implemented without utilizing another Macroce11. Likewise, Expanders may feed and be shared by
other Expanders, to implement complex multi-level logic
and input latches.

I/o OUTPUT
ENABLE

rROM
MACROCELL
IN LAB

TRI-STATE
BUrrER

MACROCELL
P-TERMS

TO LAB AND PIA
0138-6

Figure 5. I/O Control
The Programmable Interconnect Array
A major problem which has limited PLD density and
speed has been signal routing, i.e. getting signals from one
Macroce11 to another. For smaller devices, a single array is
used and all signals are available to all Macrocells. But, as
the devices increase in density, the number of signals being
routed becomes very large, increasing the amount of silicon
used for interconnections. Also, because the signal must be
global, the added loading on the internal connection path
reduces the overall speed performance of the device. The
MAX architecture solves these problems. It is based on the
concept of small, flexible Logic Array Blocks, which, in the
larger devices, are interconnected by a Programmable Interconnect Array, or PIA.

•
•

EXPANDER
P-TERMS

The Programmable Interconnect Array solves interconnect
limitations by routing only the signals needed by each
LAB. The architecture is designed so that every signal on
t~e chip is within the PIA. The PIA is then programmed to
give each LAB access to the signals that it requires. Consequently, each LAB receives only the signals needed. This
effectively solves any routing problems that may arise in a
design, without degrading the performance of the device.
Unlike masked or programmable gate arrays, which induce
variable delays dependent on routing, the PIA has a fixed
from point to point. This eliminates undesired skews
among logic signals, which may cause glitches in internal
or external logic.

0138-5

Figure 4
The I/O Block
Separate from the Macroce11 Array is the I/O Control
Block of the LAB. Figure 5 shows the I/O block diagram.
The tristate buffer is controlled by a Macrocell product
term, and drives the I/O pad. The input of this buffer
comes from a Macroce11 within the associated LAB. The
feedback path from the I/O pin may feed other blocks
within the LAB, as well as PIA.

4-116

~

..

CY7C340

r~ =======A::;D=VA::;N::;C::;'E::;'D=IN=FO::;'R::;M=~::;T:::;10::;1V==E::;P::;L::;D::;F::;amil==
•y

Functional Description (Continued)
Family Members
The CY7C340 family is an entire set of modular building
blocks, optimized for high speed and high density. Listed
below are the 4 current members of the family.

The 128 Macrocells in the CY7C342 are divided into 8
Logic Array Blocks, 16 per LAB. There are 256 Expander
Product Terms, 32 per LAB, to be used and shared by the
Macrocells within each LAB. Each LAB is interconnected
with a Programmable Interconnect Array, allowing all signals to be routed throughout the chip.
The speed and density of the CY7C342 allows it to be used
in a wide range of applications, from replacement of large
amounts of 7400 series TTL logic, to complex controllers
and multi-function chips. With greater than 25 times the
functionality of 20-pin PLDs, the CY7C342 allows the replacement of over 50 TTL devices. By replacing large
amounts of logic, the CY7C342 reduces board space, part
count, and increases system reliability.

CY7C342
•
•
•
•

128 Macrocells in 8 LABs
8 dedicated inputs, 52 bi-directional I/O pins
Programmable Interconnect Array
Available in 68-pin JLCC, PLCC and PGA

I
2
32
34

~

(B6 ) INPUT/CLK (A6 )
(L4)
INPUT _
(L5 )

:~~~~

=
LAB A

4
5
6
7

8
9
10
II

A5
B4
A4
B3
A3
A2
B2
BI

r

(A7) 68
(AS) 66
(L6) 36
(K6) 35

LABH
B8l65
A9 64

:~Ol6~2
BID 61

-v

I~

r---v

I'r-

f-.-t\

P

r---v

I

~J,.

A

~F2
F
~

G
H2
H

:1
LABO!

'

LAB C

~' ;~
sj

15 1
14
16 1
17 1

P
I

,A-

~ACROCELLS

101-112

V-

..u.

A

LABF

~3°l27

29 26
28 25
27 24

IA.
37-48

~ACROCELLS

,

v

k

;1-

LABD!

..

1gl

>

.!. 7

r---v
ltt-rv-

\r52-64

85-96

!LABE

12624231232221

-"

A-

~ACROCELLS

~ACROCELLS

V-

IV

19
18 21
20 2

~40l37

39 36
38 35
37 34

-"
v

!l

32
31
30
28

LAB H

-"

A.

WACROCELLS 4-16

:~
::HI
r-v

(35)
(34)
(33)
(31)

-.l\
hi

13.33.(3.14.25.36) I:>-Vcc
9.29(10.21.32.43) I : > - GND

~ACROCELLS

68-80

() PERTAIN TO 44-PIN J-LEAD PACKAGE

0136-8

Figure 7. CY7C345 Block Diagram
Features
Inputs

VOPins

LABs

Macrocells
per LAB

Total
Macrocells

Expanders

PIA

8

28

8

16

128

256

Yes

4-118

5n
.

CY7C340
EPLDFarnily
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=

ADVANCED INFORMATION

Functional Description (Continued)
in the LABs, each I/O control block has 7 I/O pins.
Therefore, if each I/O pin was fed by a Macrocell, there
are still 9 buried Macrocells per LAB that may be used for
embedded logic. The signals generated within each LAB
are routed to every LAB through the Programmable Interconnect Array.
The CY7C343 is perfect for designs with large I/O requirements, along with healthy amounts of buried logic. Excellent for a wide range of applications, the CY7C343 can
reduce board space by absorbing large amounts of glue
logic. Due to the large number of I/O pins, l6-bit data
paths are no problem.

CY7C343
• 64 MAX Macrocells in 4 LABs
• 8 dedicated inputs, 28 tri-stateable,
bi-directional I/O pins
• Programmable Interconnect Array
• Available in 4O-pin CDIP, PDIP,
and 44-pin JLCC, PLCC
The CY7C343 block diagram is shown in Figure 8. It has
16 Macrocells and 32 Expander Product Terms in each of
its 4 Logic Array Blocks. Decoupled from the Macrocells

-

INP UTjCLK ; ;
INPUT ;;.
INPUT ::::::INPUT

=

~INPUT

LAB A
I-I-I-I--

I/O
PINS

I-I-I-I--

I/O
PINS

:;; INPUT
.;; INPUT
::::;INPUT

~

SYSTEM CLOCK

MACRO C LL 2
MAC Roc
3
MACRO C LL 4
MACR C LL:>
MACRO C LL 6
Io1ACROCELL 7

\r-

!Y

~

Io1ACROCELLS 8-16

!Y

Vt-

LAB B

I-I-I-I-I--

HJ
A.

...1\

P

LL 18
L Ll!
LL20
L 1
LL22
LL23

A.

Io1ACROCELLS 56-64

LAB C
A R
L
MACROCELL 38
MACRO ELL37
Io1ACROCELL 36
MACROCELL 35
MACRO ;ELL 34
MACROCELL 33

r----v

~

~

r-v'

----

I/O
PINS

--

..!J. !
...1\

["'r-

Io1ACROCELLS 24-32

r

I
A

l ..!J.

MACROC
MAC C
MACROC
MACROC
MACROC
MACROC

LABD
MACRC ;EL .:>:>
MACR
LL54
MA;RC ;EL .:>3
MACROCELL 52
MACROCELL51
MACRO EL.50
MACROCELL 49

i

I"'-"-t
I"'-"-t

I/O
PINS

r--t
I"'-"-t

r--t
MACROCELLS 40-48

C>--Vcc
C>--GND
0138-9

Figure 8. CY7C343 Block Diagram
Features
Inputs

I/OPiDs

LABs

Macrocells
per LAB

Total
Macrocells

Expanders

PIA

8

28

4

16

64

128

Yes

4-119

...
~

~

.,r~

CY7C340
y
=======A=D=VA=N=C='E='D=IN="FI=o.='R=M.=:4=1',=10=1V==E=P=L=D=F=8=m;;;;::;;;il

Functional Description (Continued)
Macrocells and 64 Expander Product Terms. Figure 9
shows that even if all of the I/O pins are being driven by
Macrocells, there are still 16 "buried" Macrocells available. All inputs, Macrocells and I/O pins are interconnected within the LAB.

CY7C344
• High performance, high density replacement
for TTL, 74HC, and custom logic
• 32 Macrocells, 64 Expander Product Terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• Small outline 28-pin 300 mil CDIP, PDIP,
or 28-pin JLCC, PLCC package

The speed and density of the CY7C344 makes it a natural
for all types of applications. With just this one device, the
designer can implement complex state machines, registered
logic, and combinatorial "glue" logic, without using multiple chips. This architectural flexibility allows the CY7C344
to replace multi-chip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three.

Available in a 28-pin 300 mil DIP or JLCC, the CY7C344
represents the densest EPLD of this size. 8 dedicated inputs and 16 bi-directional I/O pins communicate to one
Logic Array Block. In the CY7C344 LAB there are 32
INPUT c.:~~"---I

INPUT

INPUT C~~"----1

INPUT/ClK

INPUT C~.u.:::"----1

INPUT

INPUT

C~~~==I-+==.~"'<::J

INPUT
3(10)
4(11)

I/O
I/O

MACROCEll6
MACROCElL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18

5(12)
I/O
6(13)
I/O
9(16)
I/O
10(17)
11(18)

I/O
I/O

12(19)
I/O
17(24)
18(25)
19(26)
20(27)

I/O
I/O
I/O
I/O

23(2)
I/O
24(3)
I/O
25(4)
I/O
26(5)
I/O
0138-12

Figure 9. CY7C344 Block Diagram
Note:

Figures within ( ) pertain to I-leaded packages.

Features
Inputs

I/O Pins

LABs

Macrocells
per LAB

Total
Macrocells

Expanders

PIA

8

16

1

32

32

64

No

4-120

&Ii

CY7C340

.

ADVANCED INFORMATION

EPLD Family

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MAX + PLUSTM Development System
may be used in conjunction with the graphic editor, giving
added flexibility to the design environment.

General Description
The MAX + PLUS Development System represents a complete hardware and software solution for implementing designs in the Cypress CY7C340 family of EPLDs.
MAX + PLUS is a sophisticated Computer Aided Design
(CAD) system that includes design entry, design simulation, and device programming. Hosted on an IBM PCIAT
or compatible machine. MAX + PLUS gives the designer
the tools to quickly and efficiently implement complex logic designs. A block diagram is shown in Figure 10.

In addition to a hierarchical design environment,
MAX + PLUS has a sophisticated processing engine to exploit the CY7C340 family architecture. MAX + PLUS uses
an advanced logic synthesizer and heuristic rules to process
a design into a file for programming andlor simulation.
MAX + PLUS features a powerful event-driven simulator
which displays typical timing results in an interactive
waveform editor display. In this waveform editor, input
vector waveforms may be directly modified and a new simulation run immediately.
Unlike most design environments, MAX + PLUS is unified,with all sections controlled by the Supervisor and Data
Base Manager. By unifying the software, MAX + PLUS
can offer an automatic error locator. If a design rule has
been violated,the error processor will list an error message,
the probable cause, and pop the designer into the schematic
to the exact node where the mistake was made.

Designs are entered in MAX + PLUS using a hierarchical
graphic editor. This editor has such features as multiple
windows, multiple zoom levels, unlimited hierarchy levels,
symbol editing, and a library of 7400 series devices in addition to basic SSI gate and register primitives. Also available
is a Timing Calculator, in which the designer may pick two
places in the schematic, and the software will display typical timing between those two points. Boolean Equation,
Netlist, State Machine, and Truth Table entry mechanisms

DESIGN PROCESSOR

BOOLEAN
EQUATION
ENTRY
STATE
MACHINE
ENTRY
TRUTH
TABLE
ENTRY

0138-11

Figure 10. MAX + PLUS Block Diagram

4-121

..
~

fin
. .
.

CY7C340

ADVANCED INFORMATION

EPLDFamily

~aoR=============================================================

MAX + PLUS Development System (Continued)
Design Entry

resources. The synthesizer will also remove any unused
logic or registers from the design.

Design entry is easily accomplished with MAX + PLUS.
MAX + PLUS provides multiple entry mechanisms, including traditional Boolean equation entry. Also available
are State Machine and Truth Table entry, using a high-level state machine language. Because the CY7C340 family of
EPLDs offer the designer large amounts oflogic capability,
a Hierarchical Graphic Editor has been provided to ease
the design process.

The next module in the design processor is the fitter. Its
function is similar to a placement and router used in semicustom gate arrays. Using heuristic rules, it takes the synthesized design and optimally places it within the chosen
CY7C340 EPLD. With the larger devices, it also routes the
signals across the Programmable Interconnect Array, freeing the designer from interconnection issues.

Graphic Editor

Timing Simulator

The hierarchical design approach used by the graphic editor allows the designer to work with either a top-down or a
bottom-up approach. The top down method allows the designer to start with a high level block diagram, and then
move down and design each block individually. The bottom up method allows the simulation and verification of
small building blocks, which may then be pieced together
into a fmal design.

Rounding out the software offering is a powerful timing
simulator to aid in the verification and debugging of designs. The simulator is a graphical, event driven software
package that yields true, worst case timings based upon
user-defined input vectors.
Waveforms may be viewed using a Graphical Waveform
Editor, which allows graphical defmitions and editing of
input waveforms. The designer can define his input waveform using the mouse to draw the actual waveform as a
function of time. There are also powerful waveform editing
commands, all menu driven, to aid in the development of
the input vectors. Such options as pre-defining, copying
and repeating waveforms are all available to the user. If
graphical definition is not desired, there is a powerful vector description language for developing input vectors.

The Graphic Editor is mouse driven and uses pull down
menus or single keystrokes to enter commands. Aiding in
the design task is a library of7400 series MSI and SSI logic
gates. The designer may use these and/or create his own
custom symbols. Custom functions are easily created in the
hierarchy by first designing the function. Then a symbol is
made, which represents that schematic. In this way a custom function may be used in multiple places in the current
design, or saved and used in subsequent designs.

The simulator itself has all the capabilities one would expect from this type of design environment. Observing buried nodes, accessing flip-flop control inputs, and initializing
and forcing nodes to specified values are all available within the timing simulator. The user may also specify breakpoints during the simulation itself, and execute subroutines
dependent upon the breakpoints. All of these tools aid the
designer in verifying and debugging the design, even before
breadboarding.

The function of any symbol created may be defined using
graphic entry, state machine, Boolean, or truth table descriptions. This provides a wide range of flexibility for the
designer, allowing Boolean equations to be combined with
state machine entry in a hierarchical schematic.
The timing calculator within the graphic editor gives the
designer instant feedback concerning timing delays inherent in a path. By placing two probes on different parts of
the schematic, the designer immediately knows the worst
case timing of the processed design. This is a valuable addition for design debugging and documentation.

The simulator also has advanced A.C. timing detection.
The software will warn the user when setup and hold times
to flip flops are being violated, and when there is oscillation
present in the simulation. ·Also, the user may define a minimum pulse width, in which any pulse within the design
that is smaller than a certain size will be classified as a
glitch and the designer will be informed.

Design Processor
After the design is entered, a push of the mouse button
invokes the powerful MAX + PLUS processor. First a netlist is extracted from the comlete hierarchical design. During the extraction process, design rules are checked for any
errors, and if errors are found, the error processor leads the
designer directly to the schematic location where the error
occurred. The extracted design is placed in the database,
and the design is ready to be processed.

Supervisor and Error Processor
All facets of the MAX + PLUS system are overseen by the
Supervisor and Data Base Manager. By tying all of the
software together, the designer has a unified operational
environment. All the software has the same "look and
feel", so that complex commands and languages are not
needed.

The versatile MAX architecture, with its Expander Product Terms and mutual exclusivity, requires a dedicated
processor to take optimal advantage of the MAX features,
one that does much more than simplify logic. The logic
synthesizer in MAX + PLUS uses several knowledge-based
synthesis rules to factor and map logic onto the multi-level
MAX architecture. It will then choose the mapping
aproach that ensures the most efficient use of the silicon

Automatic error processing is an added benefit of this approach. If an error occurs during the processing of the
design, the software will automatically tell the user what
the error is, and the probable cause.
Then, by pressing a single key, the software will automatically go the schematic in the graphic editor and pinpoint
the location ofthe error.

4-122

ADVANCElJ INFORMATION

CYPRESS
SEMICONDUCTOR

CY7C361

Ultra High Speed State
Machine EPLD

Features
• High speed: 125 MHz internal
processing
- Multiple, concurrent
processes
- Multiway branch or join
- Full input field decode
• 32 synchronous macrocells
• Skew-controlled, OR output
array
- Outputs are sum of states
like PLA
- 3 ns skew overall
• Metastable hardened input
registers
- 10 year MTBF metastable
- Configurable as 0, 1 or 2
- Clock enables on all input
registers
• 8 to 12 inputs, 10 to 14 outputs,
1 clock
• Programmable clock doubler and
conditioner
- 'Squares up' input clock
• Security fuse

Block Diagram

.,

'7

• Space saving 28 pin slim-line
DIP package; also available in
28 pin PLCC
• Low power
- 140 rnA max at 125 MHz
• UV-eraseable and
reprogrammable
• Programming and operation
100% testable

Product Characteristics
The CY7C361 is a CMOS eraseable,
programmable logic device (EPLD)
with very high speed sequencing and
arbitration capabilities.
Applications include: cache and I/O
subsystem control for high speed microprocessor based systems, control of
high speed numeric processors, and
control of asynchronous systems including dataflow organizations.
An onboard clock doubler and conditioning circuit allows the device to operate at 125 MHz based on a 62.5 MHz
input reference. The same circuit
guards against asymmetric clock wave-

Vee

Input Macrocells
The CY7C361 has 12 input macrocells.
Each macrocell can be configured to
have 0, 1 or 2 registers in the path of
the input data. In the configuration

., .,

elK

Vee

"

"

forms and thus allows for the use of a
clock with an imperfect duty cycle. The
CY7C361 has two arrays which serve
in function similar to the arrays in a
PLA except that the registers are
placed between the two arrays and the
long feedback path of the PLA is eliminated.
In the CY7C361, the state information
is contained in 32 macrocells sandwiched between the input and output
arrays. The current state information is
fed back in time to keep up with the
125 MHz operating frequency.
The output array performs an OR
function over the state macrocell outputs. The signals from the output array
are connected to 14 outputs; in addition they are connected to 3 groups of
input macrocells to act as clock enables.

"

"

toi,

GNO

GNO

4-123

GND

M2

"

"

0165-1

II
~

~CWi 2001 V
(Per MIL-STD-883 Method 3015)

Storage Temperature ..••..•.•.•.•.. -6S·C to + ISO"C
Ambient Temperature with
Power Applied .......•.•..••...... - 5S·C to + 125·C

Latchup Current (Outputs) ....•............. > 200 rnA

Supply Voltage to Ground Potential
(Pin 10 to Pin 30) •............•...... -0.5V to + 7.0V

Operating Range
Ambient
Temperature

Vee

Commercial

OOCto +700C

SV ±10%

Military [1]

- SsoC to + 12S·C

SV ±IO%

DC Voltage Applied to Outputs
in HighZ State .....•...•.......•.... -0.5V to +7.0V

Range

DC Input Voltage ...•.••............ - 3.0V to + 7.0V
Output Current into Outputs (Low) ............. 30 rnA

Note:
1. TA is the "instant on" case temperature.

Pin Definitions
Signal

Name I/O

Signal

Description

Name I/O

These 4 address lines select one of the registers in
the stack and output its contents on the (internal)
Aport.
These 4 address lines select one of the registers in
the stack and output is contents on the (internal)
B port. This can also be the destination address
when data is written back into the register file.
These 9 instruction lines select the ALU data
10-18
sources (10, I, 2), the operation to be performed
(13, 4, 5) and what data is to be written into either
the Q register or the register file (16, 7, 8).
These are 4 data input lines that may be selected
by the 10, I, 2 lines as inputs to the ALU.
YO-Y3 0 These are three-state data output lines that, when
enabled, output either the output of the ALU or
the data in the A latches, as determined by the
code on the 16, 7, 8 lines.
Output Enable. This is an active LOW input that
controls the Y 0- Y 3 outputs. When this signal is
LOW the Y outputs are enabled and when it is
HIGH they are in the high impedance state.
Clock Input. The LOW level of the clock writes
CP
data to the 16 x 4 RAM. The HIGH level of the
clock writes data from the RAM to the A-port
and B-port latches. The operation of the Q
register is similar. Data is entered into the master
latch on the LOW level of the clock and
transferred from master to slave when the clock is
HIGH.
I/O These two lines are bidirectional and are
controlled by the 16, 7, 8 inputs. Electrically they
!II'e three-state output drivers connected to the
TTL compatible CMOS inputs.

Description

Q3
I/O Outputs: When the destination code on lines
RAM3
16, 7, 8 indicates a shift left (UP) operation the
(Cont.)
three-state outputs are enabled and the MSB of
the Q register is output on the Q3 pin and the
MSB of the ALU output (F3) is output on the
RAM 3 pin.
Inputs: When the destination code indicates a
shift right (DOWN) the pins are the data inputs
to the MSB of the Q register and the MSB of the
RAM.
Qo
I/O These two lines are bidirectional and function in a
RAMo
manner similar to the Q3 and RAM3 lines, except
that they are the LSB of the Q register and RAM.
I The carry-in to the internal ALU.
Cn +4 0 The carry-out from the internal ALU.
G, 'P
0 The carry generate and the carry propagate
outputs of the ALU, which may be used to
perform a carry look-ahead operation over the 4
bitsoftheALU.
OVR
0 Overflow. This signal is logically the exclusiveOR of the carry-in and the carry-out of the MSB
of the ALU. This pin indicates that the result of
the ALU operation has exceeded the capacity of
the machine. It is valid only for the sign bit and
assumes two's complement coding for negative
numbers.
F = 0 0 Open collector output that goes HIGH if the data
on the ALU outputs (Fo, 1,2,3) are all LOW. It
indicates that the result of an ALU operation is
zero (positive logic).
F3
0 The most significant bit of the ALU output.

en

5-2

CY2901C
~RESS
~nICONDUcrOR ;;;;;=====================================;;;;;

Electrical Characteristics Over Commercial and Military Operating Range!3]
Vee Min. = 4.5V, Vee Max. = 5.5V
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

Vee = Min.
IOH = -3.4mA

VOL

Output LOW Voltage

Vee = Min.
IOL = 20 rnA Commercial
IOL = 16 rnA Military

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

IIH

Input HIGH Current

Vee == Max.
VIN = Vee

IlL

Input LOW Current

Vee = Max.
VIN = GND

IOH

Output HIGH Current

Vee
VOH

IOL

Output LOW Current

= Min.
= 2.4V
Vee = Min.
VOL = O.4V

Min.

Max.

Units

2.4

V

0.4

V

2.0

Vee

V

-3.0

0.8

V

10

/LA

-10

/LA

-3.4

I
I

loz

Output Leakage Current

Vee = Max.
VOUT = GNDtoVee

Ise

Output Short Circuit Current[1]

Vee = Max.
VOUT = OV

lee

Supply Current

Vee = Max.

rnA

Commercial

20

rnA

Military

16

rnA
+40

/LA
/LA

-85

rnA

Commercial

140

rnA

Military

180

rnA

-40
-30

l

I

Capacitance [2]
Description

Test Conditions

Max.

Input Capacitance

TA = 25°C, f= 1 MHz
Vee = 5.0V

5

Parameters
CIN

Output Capacitance

COUT

Notes:
I. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
2. Tested initially and after any design or process changes that may
affect these parameters.

Units
pF

7

3. See the last page of this specification for Group A subgroup testing
information.

Output Loads used for AC Performance Characteristics

Ti

+5V

+SV

~

R1

I

CL

le

R2

Open drain (F = 0)

Notes:
I. eL = 50 pF includes scope probe, wiring and stray capacitance.
2. eL = 5 pF for output disable tests.
3. Loads shown above are for commercial (20 mA) IOL specifications
only.

Commercial

Military

2030.

2520.

R2

1480.

1740.

L

0007-4

0007-3

All outputs except open drain

Rj

270l!

vo~

VOUT

5-3

~
CY2901C
~~~~;=======================================================~
CY2901C Guaranteed Commercial .
Range AC Performance Characteristics

Cycle Time. and Clock Characteristics
CY2901·
Read-Modify-WriteCycle (from
selection of A, B registers to
end of cycle).
Maximum Clock Frequency to shift Q
(50% duty cycle, I = 432 or 632)
Minimum Clock LOW Time
Minimum Clock HIGH Time
Minimum Clock Period

The tables below specify the guaranteed AC performance
of these devices over the Commercial WC to 7fY'C) operating temperature range with Vee varying from 4.5V to
5.5V. All times are in nanoseconds and are measured between the 1.5V signal levels. The inputs switch between OV
and 3V with signal transition rates of 1V per nanosecond.
All outputs have maximum DC current loads. See previous
page for loading circuit information.
This data applies to parts with the following numbers:
CY290I CPC
CY290 I CDC
CY290lCLC

Combinational Propagation Delays.
To Output
From Input
A, BAddress
D

Cn
1012
1345
1678

A BypassALU
(I = 2XX)
Clock~

CL

=

C
31 ns

32 MHz
15 ns
15 ns
31 ns

For faster performance see CY7C901-23 specification.

50 pF

y

F3

en + 4

G,P

F=O

OVR

40
30
22
35
35
25

40
30
22
35
35

40
30
20
35
35

37
30

40
30
22
35
35

-

-

37
35
-

40
38
25
37
38

-

35

-

-

-

35

35

35

35

-

RAMo
RAM3

Qo
Q3
-

-

-

40
30
25
35
35
26

-

-

-

-

35

35

35

28

26

Set-up and Hold Times Relative to Clock (CP) Input
-----,

CP:
Input

r--

Set-upTime

BeforeH.~

A, B Source Address

15

B Destination Address
D

-

en
1012
1345

15

-

-

1678

to

RAMo, 3,Qo, 3

-

Set-upTime
Hold Time
Hold Time
L AfterH -+ L BeforeL -+ H AfterL -+ H
1
I
30,15 + tpWL
(Note 4)
(Note 3)
-+
Do Not Change
I
25
0
20
0
30
0
0
30
-+
Do Not Change
0
12
0
-

-

Output EnablelDisable Times
Output disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage level.

Notes:
L A dash indicates a propagation delay patb or set-up time constraint
does not exist.
2. Certain signals must be stable during tbe entire clock LOW time to
avoid erroneous operation. This is indicated by the phrase "do not
change".

3. Source addresses must be stable prior to tbe clock H -+ L transition
to allow time to access tbe source data before the latches close. The A
address may then be changed. The B address could be changed if it is
not a destination; i.e. if data is not being written back into the RAM.
Normally A and B are not changed during the clock LOW time.
4. The set-up time prior to the clock L -+ H transition is to allow time
for data to be accessed, passed through the ALD, and returned to tbe
RAM. It includes all the time from stable A and B addresses to the
clock L -+ H transition, regardless of when the clock H -+ L
transition QC(;urs.

~

CY2901C

~r~~====================
CY2901C Guaranteed Military
Range AC Performance Characteristics

Cycle Time and Clock Characteristics[S]
CY2901Read-Modify-Write Cycle (from
selection of A, B registers to
end of cycle).
Maximum Clock Frequency to shift Q
~O% duty~le, I = 432 or 63~
Minimum Clock LOW Time
Minimum Clock HIGH Time
Minimum Clock Period

The tables below specify the guaranteed AC performance
of these devices over the Military (- SsoC to + 12S°C) operating temperature range with Vee varying from 4.5V to
S.5V. All times are in nanoseconds and are measured between the l.SV signal levels. The inputs switch between OV
and 3V with signal transition rates of I V per nanosecond.
All outputs have maximum DC current loads. See "Electrical Characteristics" of this data sheet for loading circuit
information.

C
32ns
31 MHz
IS ns
IS ns
32ns

For faster performance see CY7C901-27 specification.

This data applies to parts with the following numbers:
CY2901 CDMB

Combinational Propagation Delays CL

=

so pp[5]

To Output
From Input
A, BAddress
D
Cn

y

F3

en + 4

G,P

F=O

OVR

RAMo
RAM3

Qo

48
37
25

48
37
25

48
37
21

44
34

48

-

48
37
28

-

1012
1345

40
40

40
40

40
40

44
40

28
44

48
37
25
40
40

40
40

-

40

1678

29

-

-

-

-

29

40

-

29

ABypassALU
(I = 2XX)
Clock.f""

-

-

-

40

40

40

40

40

40

40

33

40

Q3

-

Set-up and Hold Times Relative to Clock (CP) Input[S]
CP:

---.,

f--

Set-upTime
Hold Time
Set-upTime
Hold Time
Input
BeforeH L AfterH H AfterL L BeforeL H
IS
2
2
A, B Source Address
30,15 + tPWL
(Note 31
~{1'iotell
B Destination Address
15
Do Not Change
2
25
0
D
20
0
Co
30
0
1012
30
0
1345
0
10
Do Not Chan~e
1678
12
0
RAMo, 3,00, 3

-

Output Enable/Disable Times[S]
Output disable tests performed with CL =

-

S pP and measured to O.SV change of output voltage level.
3. Source addresses must be stable prior to the clock H --+ L transition
to allow time to access the source data before the latches close. The A
address may then be changed. The B address could be changed if it is
not a destination; i.e. if data is not being written back into the RAM.
Normally A and B are not changed during the clock LOW time.
4. The set-up time prior to the clock L --+ H transition is to allow time
for data to be accessed, passed through the ALU, and returned to the
RAM. It includes all the time from stable A and B addresses to the
clock L --+ H transition, regardless of when the clock H --+ L
transition occurs.
5. See the last page of this specification for Group A subgroup testing
information.

Notes:
I. A dash indicates a propagation delay path or set-up time constraint
does not exist.
2. Certain signals must be stable during the entire clock LOW time to
avoid erroneous operation. This is indicated by the phrase "do not
change".

5-S

~

~2901C

.Ordering
.,-~===================================
Information
Read
ModifyWrite
Cycle (ns)

Ordering Code

Package

Type

Operating
Range

31
31

CY2901CPC
CY2901CDC

P17
DIS

Commercial
Commercial

32

CY2901 CDMB

D1S

Military

5-6

~~~=========================================C=Y=2=9=Ol==C
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics

Combinational Propagation Delays

Parameters

Subgroups

VOH

1,2,3

Frome" toY

(Continued)

Subgroups

Parameters

7,8,9,10,11

VOL

1,2,3

FromCn toF3

7,8,9,10,11

VIH

1,2,3

From C n to C n + 4

7,8,9,10,11

VILMax.

1,2,3

From C n to F

IIH

1;2,3

From e" to OVR

IlL

1,2,3

From e" to RAMo, 3

7,8,9,10,11

IOH

1,2,3

From 1012 to Y

7,8,9,10,11
7,8,9,10,11

=

°

7,8,9,10,11
7,8,9,10,11

IOL

1,2,3

From 1012 to F3

IOZ

1,2,3

From 1012 to e" + 4

7,8,9,10,11

ISC

1,2,3

From 1012 to G, P

7,8,9,10,11

Icc

1,2,3

From 1012 to F =

Cycle Time and Clock Characteristics

°

7,8,9,10,11

From 1012 to OVR

7,8,9,10,11

From 1012 to RAMo, 3

7,8,9,10,11

Parameters

Subgroups

From 1345 to Y

7,8,9,10,11

Minimum Clock LOW Time

7,8,9,10,11

From 1345 to F3

7,8,9,10,11

Minimum Clock HIGH Time

7,8,9,10,11

From 1345 to C n + 4

7,8,9,10,11

From 1345 to G, P

7,8,9,10,11

Combinational Propagation Delays
Parameters
From A, B Address to Y

From 1345 to F =

°

7,8,9,10,11
7,8,9,10,11

Subgroups

From 1345 to OVR

7,8,9,10,11

From 1345 to RAMo, 3

7,8,9,10,11

From A, B Address to F3

7,8,9,10,11

From 1678 to Y

7,8,9,10, II

From A, B Address to e" + 4

7,8,9,10,11

From 1678 to RAMo, 3

7,8,9,10,11

From A, B Address to G, P

7,8,9,10,11

From 1678 to Qo, 3

7,8,9,10,11

7,8,9,10,11

From A Bypass ALU to Y
(I = 2XX)

7,8,9,10,11

From A, B Address to F =

°

From A, B Address to OVR

7,8,9,10,11

From A, B Address to RAMo, 3

7,8,9,10,11

FromDtoY

7,8,9,10,11

FromDto F3

7,8,9,10,11

From D to e" + 4

7,8,9,10,11

From DtoG, P

7,8,9,10,11

FromDtoF =

°

7,8,9,10,11

From D to RAMo, 3

7,8,9,10,11

7,8,9,10,11

From Clock f " to F3

7,8,9,10,11

From Clock f " to C n + 4

7,8,9,10,11

From Clock f " to G, P

7,8,9,10,11

From Clock f " to F

7,8,9,10,11

From Dto OVR

From Clock f " to Y

5-7

=

°

7,8,9,10,11

From Clock f " to OVR

7,8,9,10,11

From Clock f " to RAMo, 3

7,8,9,10,11

From Clock f " to 00, 3

7,8,9,10,11

III

Set-up and Hold Times Relative to Oock (CP) Input
Parameters
A, B Source Address
Set-up Time Before H _

Parameters

Subgroups

Subgroups

7,8,9,10,11

D Hold Time After L -

A, B Source Address
Hold Time After H L
A, B Source Address
Set-up Time Before L H
A, B Source Address
Hold Time After L - H

7,8,9,10,11

en Set-up Time Before L - H
en Hold Time After L - H

B Destination Address
Set-up Time Before H -

7,8,9,10,11

L

1012 Set-up Time Before L -

7,8,9,10,11

1012 Hold Time After L -

H

1345 Hold Time After L 1678 Hold Time After H -

B Destination Address
Hold Time After H - L
B Destination Address
Set-up Time Before L - H

7,8,9,10,11
7,8,9,10,11

1678 Hold Time After L -

B Destination Address
Hold Time After L - H

7,8,9,10,11

RAMo, RAM3, Qo, Q3
Set-up Time Before L -

D Set-up Time Before L -

7,8,9,10,11

Document #: 38-00008-B

5·8

7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11

H

RAMo, RAM3, Qo, Q3
Hold Time After L -

L

7,8,9,10,11

H
H

7,8,9,10,11
7,8,9,10,11

L

1678 Set-up Time Before L -

7,8,9,10,11

H
H

1678 Set-up Time Before H -

L

7,8,9,10,11

7,8,9,10,11

H

1345 Set-up Time Before L -

7,8,9,10,11

H

7,8,9,10,11

H

7,8,9,10,11
H

CY2909A
CY2911A

CYPRESS
SEMICONDUCTOR

CMOS Micro Program
Sequencers

Features
• ESD protection
Capable of withstanding greater
than 2000V static discharge
voltage
• Pin compatible and
functional equivalent to
AMD AM2909A/AM2911A

• Fast
- CY2909A/llA has a 40 ns
(min.) clock to output cycle
time; commercial
- CY2909/11 has a 40 ns
(min.) clock to output cycle
time; military
• Low power
- Icc (max.) = 70 mA
commercial
- Icc (max.) = 90 mA
military

Description
The CY2909A and CY2911A are high·
speed, four-bit wide address sequencers
intended for controlling the sequence
of execution of microinstructions contained in microprogram memory. They
may be connected in parallel to expand
the address width in 4 bit increments.
Both devices are implemented in high
performance CMOS for optimum
speed and power.
The CY2909A can select an address
from any of four sources. They are:

• Vee margin

-5V ±10%
- All parameters guaranteed
over commercial and military
operating temperature range

• Expandable
Infinitely expandable in 4·bit
increments

Logic Block Diagram
R(2909A ONl.y)

Pin Configurations
PUSH/POP

,.

FIL.E
ENASLE

~------

I

R~~~i~~
iiE)

I) a set offour external direct inputs
(Dj); 2) external data stored in an internal register (Ri); 3) a four word deep
push/pop stack; or 4) a program counter register (which usually contains the
last address plus one). The push/pop
stack includes control lines so that it
can efficiently execute nested subroutine linkages. Each of the four outputs
(Yj) can be OR'ed with an external input for conditional skip or branch instructions. A ZERO input line forces
the outputs to all zeros. The outputs
are three state, controlled by the
Output Enable (OE) input.
The CY2911A is an identical circuit to
the CY2909A, except the four OR inputs are removed and the D and R inputs are tied together. The CY2911A is
available in a 20-pin, 300-mil package.
The CY2909 is available in a 28-pin,
6OO-mil package.

Vcc
ep
pUP

I
I
Iv

FE
Cn+04-

en

DANDR
CONNECTED
4
ON 2911;.1
ONLY I
DIRECT
INPUTS

DE

I
I
I

CLOCK

Yo
5,

s. >---~
5,

>---~

1[-;,;.----'
I

Ya
Yz
Y,

1d~:TlPLEXER
Xo

CP

pUP

Vee

RE

FE
en ....

03

Cn

02
0,

Y3

DO
OND

Y2
Y,

OE

ZERO

Yo

So

5,

50

0086-3

ZERo

)(1

0066-2

OR2

OR, >-~f--h
lOR. } - - ; - - ,

I

"

_ _ _ONLY
_ _ .JI
IL _290iA

ffiO

4 3 2

RD
DRs
Os
OR Z
Oz
OR,

}----t-t-1rl--t-h

0,

5

tIl 28 27 26

25
24
8
7
23
22
2909A
21
10
20
11
19
12131415161718

I~ >u

e;

0.

~ I~

FE

eCnn+"

03

4

5

OE

02
0,

Ya
YZ
Y,

Do
GND

Cn+4

17

Cn

16
15
7
8
14
910111213

OE

6

2911A

Y3
Y2

10a:::V)(I)->-

OUTPUT
ENASLE

0

-

0

-

'"

N

iiE }-'CL::>--II-t--t-II-t-'
C.

0066-4
c".4

0066-1

5-9

0066-5

5

fin
.

CY2909A
CY2911A

~~================================================================

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + lSO"C

Static Discharge Voltage ..................... >2001V
(per MIL-STD-883 Method 3015)

Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latch-Up Current ......................... > 200 rnA

Supply Voltage to Ground Potential .... -0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
Output Current, into Outputs (Low) ............. 30 mA

~ge

Ambient
Temperature

Commercial
Military(3)

O"Cto +70"C
- 55°C to + 125°C

Vee
5V ±10%
5V ±1O%

Electrical Characteristics Over Operating Range f4]
Parameters

Description
Vee

Output HIGH Voltage

VOH

Vee

Test Conditions

Min.

= Min.,IOH = -2.6 rnA (Comm.)
= Min., IOH = -1.0 rnA (Mil.)
= Min.,IOL = l6.0mA

2.4

Max.

Units
V

2.4

VOL

Output LOW Voltage

VIH

Input High Voltage

2.0

VrL

Input Low Voltage

Irx

Input Load Current

GND

loz

V
0.4

V
V

-2.0

Vee
0.8

Vee

-10

+10

p.A

Output Leakage
Current

GND S; Vo S; Vee
Output Disabled

-20

+20

p.A

los

Output Short
Circuit Current!I)

Vee

-30

-85

mA

Icc

Vee Operating
Supply Current

Vee

S;

VI

S;

= Max.
Vee = Max.
lOUT = OmA

VOUT

I
I

= GND

Commercial
Military

V

70

mA

90

Capacitance [2]
Parameters

Description

Test Conditions

CIN

Input Capacitance

COUT

Output Capacitance

TA = 25°C, f
Vee = 5.0V

Notes:
1. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initiaUy and after any design or process changes that may
affect these parameters.

n

AC Test Loads and Waveforms
OUTPUT

50pf

I

INCLUDING
JIG AND SCOPE

n

Max.

1 MHz

5V

OUTPUT
R2

_

5pf

I

INCLUDING
JIG AND SCOPE

ALL INPUT PULSES
30V
•

_.

Military

Rl

2540

2580

R2

1870

2160

10%

5n.-1

I-

L'
I

10%

-I

1-5no
0066-7

-

5-10

I

~90%

GND

R2

Figure 2
0066-6

Commercial

pF

7

3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

Figure 1b

Figure 1a

Units

5

Rl

Rl

5V

=

riA
~ ~~DUcrOR;;=================================================================
CY2909A
CY2911A

...

Switching Characteristics Over Operating Range[4)
2909A
2911A

2909A
2911A

Units

Commercial

Military

Minimum Clock Low Time

20

20

ns

Minimum Clock High Time

20

20

ns

MAXIMUM COMBINATIONAL PROPAGATION DELAYS
17

CN + 4
22

20

CN + 4
25

ns

Di

So, SI

29

34

29

34

ns

ORi CY2909A

17

22

20

25

ns

-

14

-

16

ns

29

34

30

35

ns

25

-

25
25

-

ns

25
39

44

45

50

ns

39

44

45

50

ns

44

49

53

58

ns

From Input To:

Y

. CN
ZERO
OE Low to Output
OE High to High Z[5]
Clock High, So, SI
Clock High, So, SI
Clock High, So, SI

= LH
= LL
= HL

Y

ns

ns

MINIMUM SET-UP AND HOLD TIMES (All Times Relative to Clock LOW to HIGH Transition)
Set-up

Hold

Set-up

Hold

1rn

From Input

19

4

19

5

ns

Ri [6)

10

4

12

5

ns

PushlPop

25

4

27

5

ns

FE

25

4

27

5

CN

18

4

18

5

ns
ns

Di
ORi (CY2909A)

25

0

25

0

ns

25

0

25

0

ns

So, SI

25

0

29

0

ns

ZERO

25

0

29

0

ns

Notes:
5. Output Loading as in Figure 1h.

6. Ri and Di are internally connected on the CY2911A. Use Ri set-up
and hold times for Di inputs.

Switching Waveforms
MIN CLOCK LOW
CLOCK

_ _ _ _"""I ..~~

• TIMES)/C

0086-8

5-11

II

fin.
..

CY2909A
~lU

~~R================================================================

Ordering Information
Package
Type

Operating
Range

CY2909APC
CY2909ADC
CY2909ALC

P15
016
L64

Commercial

CY2909ADMB
CY2909ALMB

016
L64

Military

Ordering Code

Ordering Code

5-12

Package
Type

Operating
Range

CY2911APC
CY2911ADC
CY2911ALC

P5
D6
L61

Commercial

CY2911ADMB
CY2911ALMB

D6
L61

Military

~~
.
Jil

CYPRESS

,

SEMICONDUCTOR

CY2909A
CY2911A

=================================

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

lIx

1,2,3

IOZ

1,2,3

lOS

1,2,3

ICC

1,2,3

II

Switching Characteristics
Parameters

Subgroups

Minimum Clock Low Time 7,8,9,10,11
Minimum Clock High Time 7,8,9,10,11

Parameters

Subgroups

MINIMUM SET -UP
AND HOLD TIMES
7,8,9,10,11

MAXIMUM COMBINATIONAL
PROPAGATION DELAYS

RE Set-up Time
REHoldTime

7,8,9,10,11

DjtoY

7,8,9,10,11

Push/Pop Set-up Time

7,8,9,10,11

Dj to CN+4

7,8,9,10,11

Push/Pop Hold Time

7,8,9,10,11

So, SI to Y

7,8,9,10,11

FE Set-up Time

7,8,9,10,11

So, SI toCN+4

7,8,9,10,11

FE Hold Time

7,8,9,10,11

ORj (CY2909A) to Y

7,8,9,10,11

CN Set-up Time

7,8,9,10,11

ORj (CY2909A) to CN + 4

7,8,9,10,11

CNHoldTime

7,8,9,10,11

CNto CN+4

7,8,9,10,11

Dj Set-up Time

7,8,9,10,11

ZEROtoCN+4

7,8,9,10,11

DjHoldTime

7,8,9,10,11

Clock High, So, S 1 = LH
toY

7,8,9,10,11

ORj (CY2909A)
Set-upTime

7,8,9,10,11

Clock High, So, S 1= LH
toCN+4

7,8,9,10,11

ORj (CY2909A)
Hold Time

7,8,9,10,11

Clock High, So, S 1 = LL
toY

7,8,9,10,11

So, SI Set-up Time

7,8,9,10,11

Clock High, So, S 1= LL
toCN+4

7,8,9,10,11

Clock High, So, S 1= HL
toY

7,8,9,10,11

Clock High, So, S 1 = HL
toCN + 4

7,8,9,10,11

So, SI Hold Time

7,8,9,10,11

ZERO Set-up Time

7,8,9,10,11

ZERO Hold Time

7,8,9,10,11

Document #: 38-00009-B

5-13

CY29 lOA

CYPRESS
SEMICONDUCTOR

CMOS Microprogram
Controller

Features
• Fast
- CY2910AC has a 50 ns (min.)
clock cycle; commercial
- CY2910AM has a 51 ns
(min.) clock cycle; military

• 12-bit Internal loop counter

• Low power

• Pin compatible and functional
equivalent to Am2910A

-

ICC (max.)

= 170

rnA

• Vcc Margin 5V ± 10%
commercial and military
• Sixteen powerful
microinstructions
• Three output enable controls for
three-way branch
• Twelve-bit address word
• Four sources for addresses:
microprogram counter (MPC),
branch address bus, 9-word
stack, internal holding register
• Internal 9-word by 12-bit stack
The internal stack can be used
for subroutine return address or
data storage

• ESD protection
Capable of withstanding over
2000 volts static discharge
voltage

Functional Description
The CY29 lOA is a stand-alone microprogram controller that selects, stores
retrieves, manipulates and tests ad- '
dresses that control the sequence of execution of instructions stored in an external memory. All addresses are 12-bit
binary values that designate an absolute memory location.
The CY2910A, as illustrated in the
block diagram, consists of a 9-word by
12-bit LIFO (Last-In-First-Out) stack
and SP (Stack Pointer), a 12-bit RC
(Register/Counter), a 12-bit MPC (Microprogram Counter) and incrementer,
a 12-bit wide by 4-input multiplexer

and the required data manipUlation
and control logic.
The operation performed is determined
by four input instruction lines (10-13)
that in turn select the (internal) source
of the next micro-instruction to be
fetched. This address is output on the
YO-Yll pins'Jto additional inputs
(CC and CCE are provided that are
examined during certain instructions
and enable the user to make the execution of the instruction either unconditional or dependent upon an external
test.
The CY2910A is a pin compatible,
functional equivalent, improved performance replacement for the
Am29 lOA.
The CY29 lOA is fabricated using an
advanced 1.2 micron CMOS process
that eliminates latchup, results in ESD
protection of over 2000 volts and
achieves superior performance and low
power dissipation.

Logic Block Diagram

Pin Configuration
Y4
D.
Ys

03
Y3
O2

Os
VEer

Y2
0,

Pi:

Y,

MAP

DO

'3

Yo
el
ep

'2
Vee

I,
'0

GND

CCEN

cc

Y"

RLo

0"
Y,o

Or

rUlL

D,O
Y.

D.
Y6

D.
Ya

D7
Y7

~
0040-2

Da
0040-3

Top View

Selection Guide
Clock Cycle (Min.) in ns

StnckDepth

Operating Range

Part Number

50

9 words

51

9 words

Commercial
Military

CY2910AM

5-14

CY2910AC

~
CY2910A
~~~~~=============================================================
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C
Static Discharge Voltage ..................... >2001V
Ambient Temperature with
(Per MIL-STD-883 Method 3015)
Power Applied .................... - 55°C to + 125°C
Latchup Current (Outputs) .................. > 200 mA
Supply Voltage to Ground Potential
Operating Range
(Pin 10 to Pin 30) .................... -0.5V to + 7.0V
Ambient
DC Voltage Applied to Outputs
Range
Vee
Temperature
in High Z State ...................... -0.5Vto +7.0V
Commercial
O"Cto +70"C
5V +10%
DC Input Voltage ................... -3.0V to +7.0V
Military [3]
- 55°C to + 125°C
5V ±1O%
Output Current into Outputs (Low) ............. 30 mA

Electrical Characteristics Over Commercial and Military Operating Range[4)
Vee Min. = 4.5V, Vee Max. = 5.5V
Parameter

Description

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

IIH

Input HIGH Current

Test Condition

Min.

= Min., IOH = - 1.6 rnA
Vee = Min.,IOL = 8 rnA

2.4

Vee

IlL

Input LOW Current

IOH

Output HIGH Current

= Max., VIN = Vee
Vee = Max., VIN = GND
Vee = Min., VIH = 2.4V

IOL

Output LOW Current

Vee = Min., VOL = 0.5V

loz

Output Leakage Current

Vee = Max.,
VOUT = GND/Vee

Ise

Output Short Circuit Current

Icc

Supply Current

Max.

Units
V

0.5

V

2.0

Vee

V

-3.0

0.8

V

10

p.A

Vee

-10

p.A

-1.6

rnA

8

mA
+40

p.A
p.A

Vee = Max., VOUT = OV

-85

mA

Vee = Max.

170

mA

-40

Capacitance [2]
Parameters
CIN

Description
Input Capacitance
Output Capacitance

CoUT

Test Conditions
TA = 25°C, f = 1 MHz
Vee = 5.0V

Units
pF
pF

Max.
8

10

Notes:
I. Not more than one output should he tested at a time. Duration of the
short circuit should not exceed one second.
2. Tested initially and after any design or process changes that may
affect these parameters.

3. TA is the Uinstant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

Output Load for AC Performance
Characteristics

Switching Waveforms



~-----------------JI~----~II'--_

+5V

~ ' t"

....

3 . 0 V - - - - - - - - -... 
,.-----

INPUTS

All Outputs

3.0V
CLOCK
OV

i=

OUTPUTS

__________________

1.SV

-JI~------

__

0040-5

Notes:
0040-4
eL = 50 pF includes scope probe, writing and stray capacitance.
eL = 5 pF for output disable tests.

5-15

Guaranteed AC Performance Characteristics
The tables below specify the guaranteed AC performance
of the CY2910A over the commercial (O"C to + 70"C) and
the military (- SS·C to + 12S·C) temperature ranges with
VCC varying from 4.SV to s.sv. All times are in nanosec·
onds and are measured between the l.SV signal levels.

The inputs switch between OV and 3V with signal tran·
sition rates of 1 Volt per nanosecond. All outputs have
maximum DC current loads.

Clock Requirements[l, 41
Commerclal

Military

Minimum Clock LOW

20

25

Minimum Clock HIGH

20

25

SO

51

50

50

Minimum Clock Period I

= 14

Minimum Clock Period
I = 8,9, 15 (Note 2)

Combinational Propagation Delays. CL

so pp[4]

=

Commerclal

To Output

Military

From Input

Y

PI:, VECI', MAP

PUI:I

y

PI, VECI', MAP

FUII

00-011

20
35
30
30

30
-

-

25
40
36
36

3S
-

-

CP
I = 8,9, IS
(Note 2)

40

-

31

-

-

3S

CP
All Other I

40

-

31

46

-

3S

25
27

-

-

2S

-

-

IO-I3
~
~

ill:
(Note 3)

-

30

Minimum Set-up and Hold Times Relative to clock LOW to HIGH Transition. CL
Commerclal
Input

-

-

= 50 pp[4]

Military

Set·up

Hold

Set·up

Hold

0

16

0

DI -

RC

16

DI -

MPC

30

0

30

0

IO-I3

35

0

38

0

~

24

0

35

0

~

24

0

35

0

CI

18

0

18

0

R:Lij

19

0

20

0

Notes:
1. A dash indicates that a propagation delay path or set·up time does not
exist.
2. These instructions are dependent u,Pon the register!ccunter. Use the
shorter delay times if the previous Instruction either does not change
the repster!counter or could only decrement it. Use the longer delay
if the Instruction prior to the clock was 4 or 12 or ifl{Ilj was WW.

3. The enable/disable times are measured to a 0.5 Volt change on the
output voltage level with CL = 5 pF.
4. See the last page of this specification for Group A subgroup testing
information.

5·16

~

CY2910A

~jr;~u~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Table of Instructions
13-10 MNEMONIC

0
I
2
3
4
5
6
7

JZ
CJS
JMAP
CJP
PUSH
JSRP
CJV
JRP

8

RFCT

9

RPCT

NAME

Jump Zero
CondJSBPL
Jump Map
Cond Jump PL
Push/Cond LD CNTR
Cond JSB R/PL
Cond Jump Vector
Cond Jump R/PL
Repeat Loop,
CNTR;IoO
RepeatPL,
CNTR;IoO

10
11
12
13
14

CRTN
CJPP
LDCT
LOOP
CONT

CondRTN
Cond Jump PL & Pop
LD Cntr & Continue
Test End Loop
Continue

15

TWB

Three-Way Branch

REG!
CNTR
CONTENTS
X
X
X
X
X
X
X
X
;100
=0
;100
=0
X
X
X
X
X
;100
=0

FAIL
CCEN = Landre = H
y
STACK
0
Clear
PC
Hold
D
Hold
PC
Hold
PC
Push
R
Push
PC
Hold
R
Hold
F
Hold
PC
POP
D
Hold
PC
Hold
PC
Hold
Hold
PC
PC
Hold
F
Hold
PC
Hold
F
Hold
Pop
D

Notes:
I. IfCCEN = Land c:c = H, hold; else load.

H = HIGH

Ordering Information
Cock
Cycle

Package
Type

Operating
Range

CY29lOADC

018

Commercial

CY2910AJC

J67

CY29lOALC

L67

Ordering Code

(us)

50

51

CY2910APC

PI7

CY2910ADMB

018

CY2910ALMB

L67

Military

5-17

RESULT
PASS
CCEN = Horre = L
Y
STACK
0
Clear
D
Push
D
Hold
D
Hold
PC
Push
Push
D
D
Hold
D
Hold
F
Hold
Pop
PC
D
Hold
PC
Hold
F
Pop
D
Pop
PC
Hold
PC
Pop
PC
Hold
Pop
PC
Pop
PC
L=LOW

REG!
CNTR

ENABLE

Hold
Hold
Hold
Hold
(Note I)
Hold
Hold
Hold
Dec
Hold
Dec
Hold
Hold
Hold
Load
Hold
Hold
Dec
Hold

PL
PL
Map
PL
PL
PL
Vect
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL

X = Don't Care

II

MILITARY SPECIFICATIONS
Group A Sub~oup Testing
DC Characteristics

Minimum Set-up and Hold Times

Parameters

Subgroups

VOH

1,2,3

DI -

RC Set-up Time

7,8,9,10,11

VOL

1,2,3

DI -

RC Hold Time

7,8,9,10,11

VIH

1,2,3

DI -

MPC Set-up Time

7,8,9,10,11

VILMax.

1,2,3

DI -

MPC Hold Time

7,8,9,10,11

IIH

1,2,3

IO-I3 Set-up Time

IlL

1,2,3

IO-I3 Hold Time

7,8,9,10,11

IOH

1,2,3

CC Set~up Time

7,8,9,10,11

Parameters

Subgroups

7,8,9,10,11

IOL

1,2,3

CCHoidTime

7,8,9,10,11

loz

1,2,3

7,8,9,10,11

Isc

1,2,3

CCEN Set-up Time
CCEN Hold Time

Icc

1,2,3

CI Set-up Time

7,8,9,10,11

CI Hold Time

7,8,9,10,11

RLD Set-up Time

7,8,9;10,11

RLD Hold Time

7,8,9,10,11

Clock Requirements
Parameters

Subgroups

Minimum Clock LOW

7,8,9,10,11

Combinational Propagation Delays
Parameters

Subgroups

From DO-D11 to Y

7,8,9,10,11

From IO-I3 to Y

7,8,9,10,11

From IO-I3 to PL, VEC'f, MAP

7,8,9,10,11

FromCCtoY

7,8,9,10,11

From CCEN to Y

7,8,9,10,11

From CP (I = 8,9, IS) to FULL

7,8,9,10,11

From CP (Ail Other I) to Y

7,8,9,10,11

From CP (Ail Other I) to FULL

7,8,9,10,11

Document #: 38-OO01O-B

5-18

7,8,9,10,11

CY3341

CYPRESS
SEMICONDUCTOR

64

X

4 FIFO Serial Memory

Features

Data Input

• 1.2/2 MHz data rate

The four bits of data on the Do through
D3 inputs are entered into the first location when both Input Ready (IR)
and Shift In (SI) are HIGH. This causes IR to go LOW but data will stay
locked in the first bit location until
both IR and SI are LOW. Then data
will propagate to the second bit location, provided the location is empty.
When data is transferred, IR will go
HIGH indicating that the device is
ready to accept new data. If the memory is full, IR will stay LOW.

• Fully TIL compatible
• Independent asynchronous inputs
and outputs
• Direct replacement for PMOS

3341
• Expandable in word length and
width
• CMOS for optimum speed/
power
• Capable of withstanding greater
than 2000V electrostatic
discharge

Functional Description
The 3341 is a 64-word x 4-bit First-In
First-Out (FIFO) Serial Memory. The
inputs and outputs are completely independent (no common clocks) making
the 3341 ideal for asynchronous buffer
applications.
Control signals are provided for both
vertical and horizontal expansion.
The 3341 is manufactured using Cypress CMOS technology and is available in both ceramic and plastic packages.

Data Transfer
Once data is entered into the second
cell, the transfer of any full cell to the
adjacent (downstream) empty cell is
automatic, activated by an on-chip control. Thus, data will stack up at the end
of the device while empty locations will
"bubble" to the front. tBT defines the
time required for the first data to travel
from the input to the output of a previously empty device, or for the first
empty space to travel from the output
to the input of a previously full device.
Data Output
When data has been transferred into
the last cell, Output Ready (OR) goes

Logic Block Diagram

HIGH, indicating the presence of valid
data at the output pins Qo through Q3.
The transfer of data is initiated when
both the Output Ready output from
the device and the Shift Out (SO) input
to the device are HIGH. This causes
OR to go LOW; output data, however,
is maintained until both OR and SO
are LOW. Then the content of the adjacent (upstream) cell (provided it is full)
will be transferred into the last cell,
causing OR to go HIGH again. If the
memory has been emptied, OR will
stay LOW.
Input Ready and Output Ready may
also be used as status signals indicating
that the FIFO is completely full (Input
Ready stays LOW for at least tBT) or
completely empty (Output Ready stays
LOW for at least tBT).
Reset
When Master Reset (MR) goes LOW,
the control logic is cleared, and the
data outputs enter a LOW state. When
MR returns HIGH, Output Ready
(OR) stays LOW, and Input Ready
(IR) goes HIGH if Shift In (SI) was
LOW.

Pin Configuration

Sl
IR

vss

VGG*

WRITE POINTER

Do

0,
02
03

IR

so

SI

OR

Do

Co

0,

C,

O2

C2

03

C3

iiffi

voo

0004-2

*Internally not connected

SO

READ POINTER

OR

0004-1

Selection Guide
3341

3341-2

1.2 MHz

2.0 MHz

Commercial

45

45

Military

60

60

Maximum Operating Frequency
Maximum Operating
Current (rnA)

5-19

II

CY3341
~s
"~ICONDUcrOR =====================================
Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... > 2001V
(per MIL-STD-883 Method 3015)

Storage Temperature ............... -65°C to + 150°C
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latchup Current .......................... > 200 rnA

Supply Voltage to Ground Potential
(Pin 16 to Pin 8) ..................... -0.5V to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to + 7.0V

Range

Ambient
Temperature

Vss

VGG*

VDD

Commercial
O°C to + 70°C
5V ±10% GND
Military [3]
- 55°C to + 125°C 5V ±1O% GND

DC Input Voltage ................... -3.0V to +7.0V
Output Current, into Outputs (Low) ............. 20 rnA

NC
NC

'Internally Not Connected.

Electrical Characteristics Over the Operating Range[4]
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

VSS = Min.,IOH = -0.3 rnA

VOL

Output LOW Voltage

Vss = Min., IOL = 1.6 rnA

VIH

Input HIGH Voltage

Min.

Max.

V
0.4

V
V

-3.0

VSS
0.8

-10

+10

fLA

-90

rnA

2.0

VIL

Input LOW Voltage

IIX

Input Leakage Current

Voo S VI S VSS

los

Output Short
Circuit Current[I]

VSS = Max., VOUT = Voo

IDO

Power Supply Current

VSS = Max.,
lOUT = OmA

100

VooCurrent

I
I

Units

2.4

Commercial

45

Military

60

V

rnA

0

rnA

Capacitance [2]
Test Conditions

Max.

CIN

Input Capacitance

Description

TA = 25°C,f= 1 MHz

7

COUT

Output Capacitance

Vss = 5.0V

10

Parameters

Notes:
1. Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

Units
pF

3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

AC Test Loads and Waveforms
ALL INPUT PULSES

R1 2.42 Krl
5 v Q-----J'WI,.--,

3.0 V -----.z=~---i.

OUTPUTQ---~---~

GND

I-=

10 ns

R2
3.28 KH

30 pF

10 ns
0004-5

INCLUDING
JIG AND
SCOPE

-=
0004-3

Equivalent to:

THEVENIN EQUIVALENT
1.05 Krl
OUTPUT ~ 2.08 V
0004-4

5-20

~
CY3341
~~~aDR==============================================================~
Switching Characteristics Over the Operating Range[4, 5]
Parameters

Description

fMAX
tpHS1

Operating Frequency
SIHIGHTime

tpLS1

SILOWTime

too
tHS1

Data Setup to SI
Data Hold from SI

t1R+
t1R-

Delay, SI HIGH to IR LOW
Delay, SI LOW to IR HIGH

tPHSO
tpLSO

SO HIGH Time
SO LOW Time
Delay, SO HIGH to OR LOW
Delay, SO LOW to OR HIGH

toR +
toRtOA

Test
Conditions

3341
Min.

Min.

1.2

Note 6

80
80
0
200
20
20
80
80
20
20
0
75

Data Setup to OR HIGH

3341-2
Max.

tOH
tBT

Data Hold from OR LOW
Bubble through Time

tMRW
tOS1
tOOR

MR Pulse Width

400

MR HIGH to SI HIGH
MR LOW to OR LOW

30

torR

MR LOW to IR HIGH

350
450

370
450

Units

Max.

2
80
80
0
100
20
20
80
80
20
20
0
20

1000

ns

160
200

400

ns
ns
ns
ns
ns

160
200

500
200
30

400

MHz
ns
ns

ns
ns
ns
ns
ns
ns
ns

200
200

ns
ns

Notes:
5. Test conditions assume signal transitions of 10 ns or less. Timing
reference levels of l.5V and output loading of the specified 10r/IoH
and 30 pF load capacitance.

Switching Waveforms
Data In Timing Diagram

SHIFT IN

INPUT READY

DATA INPUT

0004-6

Data Out Timing Diagram

SHIFT OUT

OUTPUT READY

DATA OUTPUT

0004-7

5-21

~
CY3341
~~~~===========================================================
Switching Waveforms (Continued)

Master Reset Timing Diagram

.

tMRW

~r

MASTER RESET

J

~

telR

INPUT READY

j
fIIOR

OUTPUT READY

.

)

~"~ _ _ _---Ii
1.
tDSI

\

DATA OUTPUT

0004-8

Ordering Information
Ordering Code

Package
Type

Operating
Range

CY334iPC
CY334lDC

Pi
02

Commercial

CY334lDMB

02

Military

(1.2 MHz)

Ordering Code
(2 MHz)

5-22

Package
Type

Operating
Range

CY334i-2PC
CY334i-20C

Pi
02

Commercial

CY334i-20MB

02

Military

~
CY3341
~~~UcroR~~~~~~~~~~~~~~~~~~~~~~~==
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

100

1,2,3

Switching Characteristics
Parameters

Subgroups

fMAX

7,8,9,10,11

tpHSI

7,8,9,10,11

tpLSI

7,8,9,10,11

too

7,8,9,10,11

tHSI

7,8,9,10,11

tIR+

7,8,9,10,11

tIR-

7,8,9,10,11

tpHSO

7,8,9,10,11

tPLSO

7,8,9,10,11

toR +

7,8,9,10,11

toR-

7,8,9,10,11

tOA

7,8,9,10,11

tOH

7,8,9,10,11

tBT

7,8,9,10,11

tMRW

7,8,9,10,11

tOSI

7,8,9,10,11

tOOR

7,8,9,10,11

tDIR

7,8,9,10,11

Document #: 38-00011-B

5-23

CY7C401/CY7C403
CY7C402/CY7C404

CYPRESS
SEMICONDUCTOR

Cascadeable 64

X

4 FIFO and
64 x 5 FIFO

Features
• 64 x 4 (CY7C401 and CY7C403)
64 x 5 (CY7C402 and CY7C404)
High speed first-in first-out
memory (FIFO)
• Processed with high-speed
CMOS for optimum
speed/power
• 25 MHz data rates
• 50 ns bubble-through time25 MHz
• Expandable in word width
and/or length

• 5 volt power supply ± 10%
tolerance both commercial and
military
• Independent asynchronous inputs
and outputs
• TIL compatible interface
• Output enable function available
on CY7C403 and CY7C404
• Capable of withstanding greater
than 2001V electrostatic
discharge

• Pin compatible with MMI
67401A/67402A

Functional Description
The CY7C401 and CY7C403 are asynchronous first-in first-out memories
(FIFOs) organized as 64 four bit
words. The CY7C402 and CY7C404
are similar FIFOs organized as 64 five
bit words. Both the CY7C403 and
CY7C404 have an Output Enable (OE)
function.
The devices accept 4/5 bit words at the
data input (DIo-DIn) under the control of the Shift In (SI) input. The
stored words stack up at the output
(DOo-DOn) in the order they were entered. A read command on the Shift
Out (SO) input causes the next to last
word to move to the output and all
data shifts down once in the stack. The
Input Ready (IR) signal acts as a flag
to indicate when the input is ready to
accept new data (HIGH). to indicate
when the FIFO is full (LOW). and to
provide a signal for cascading. The

Logic Block Diagram

Pin Configurations
CY7C401 NC
CY7C4036E

SI
IR

DI.
DI,
DI.
DI,
IDI.I

Output Ready (OR) signal is a flag to
indicate the output contains valid data
(HIGH). to indicate the FIFO is empty
(LOW). and to provide a signal for cascading.
Parallel expansion for wider words is
accomplished by logically ANDing the
Input Ready (IR) and Output Ready
(OR) signals to form composite signals.
Serial expansion is accomplished by tying the data inputs of one device to the
data outputs of the previous device.
The Input Ready (IR) pin of the receiving device is connected to the Shift Out
(SO) pin of the sending device. and the
Output Ready (OR) pin of the sending
device is connected to the Shift In (SI)
pin of the receiving device.
Reading and writing operations are
completely asynchronous. allowing the
FIFO to be used as a buffer between
two digital machines of widely differing
operating frequencies. The 25 MHz operation makes these FIFOs ideal for
high speed communication and controller applications.

WRITE POINTER

1m)

DO.
DO,
DO,

MEMORY
ARRAY

DO,
ID041

IR

Vee
SO

51

OR

g~~=~
IR

Vee
SO

51

OR

DO.

DO,

01.
01,

DO,

01,

DO,

01,

003

013

003

GND

Mil

014

01.
01,
01,

DO.

GND

I.lII

DO,

DO.

-""_ _r

so

READ POINTER

MIl

0014-3

OR
3 2 1 2019
SI
DID
01,
01,
NC

0014-1

4

•
•
6
7

18
7C401
7C0403

'7
'6

,.,.

NC
DR
DOD

3 2 1 2019

SI
DID
01,
01,
013

DO,
DO,

910111213

i51')11~81')~

0014-16

4

•
6

7C402
7C404

'6
17
'6

,.

14
9 10111213

6"gI18'2001V
(per MIL-STD-883 Method 3015)
Latch-up Current .......................... > 200 mA

Supply Voltage to Ground Potential .... -O.SV to + 7.0V

Operating Range

DC Voltage Applied to Outputs
in High Z State ...................... -O.SVto +7.0V
DC Input Voltage ................... - 3.0V to + 7.0V
Power Dissipation ............................. 1.0W
Output Current, into Outputs (Low) ...•......•.. 20 mA

Range

Ambient
Temperature

Commercial
Military!3]

O"Cto +70"C
- SsoC to + 12SoC

Vee
SV ±10%
SV ±1O%

Electrical Characteristics Over Operating Range (Unless Otherwise Noted)[4]
Parameters

Description

Test Conditions

7C40X-I0, 15, 25
Min.

Units

Max.

VOH

Output HIGH Voltage

Vee = Min.,IoH = -4.0mA

VOL

Output LOW Voltage

Vee = Min., IOL = 8.0 rnA

0.4

V

VIH

Input HIGH Voltage

2.0

6.0

V

VIL

Input LOW Voltage

-3.0

0.8

V

Ilx
VeD[I]

Input Leakage Current

-10

+10

p.A

Input Diode Clamp Voltage[l]

loz

Output Leakage Current

GND ~ VOUT ~ Vee, Vee = S.5V
Output Disabled (CY7C403 and CY7C404)

-50

+50

p.A

los

Output Short Circuit Currend2]

Vee = Max., VOUT = GND

-90

mA

Power Supply Current

Vee = Max.,
lOUT = OmA

Icc

GND

~

VI

~

Vee

I
I

2.4

V

Commercial

75

mA

Military

90

rnA

Capacitance [5]
Test Conditions

Max.

CIN

Parameters

Input Capacitance

Description

TA = 25°C, f = 1 MHz

5

CoUT

Output Capacitance

Vee = 4.5V

7

Notes:
1. The eMOS process does not provide a clamp diode. However, the
FIFO is insensitive to - 3V dc input levels and - SV undershoot
pulses ofless than 10 ns (measured at 50% point).
2. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.

Units
pF

3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

5. Tested initially and after any design or process changes that may

affect these parameters.

Note:
For more information on FIFOs, please refer to the FIFO Application Brief in the Appendix of this book.

5-25

II

&n
.

CY7C40l/CY7C403
CY7C402/CY7C404
~~aoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=

AC Test Load and Waveform
R14370

ALL INPUT PULSES

R143711

5Vo-------~~_,

5v

o-------.J\I...........,

OUTPUT o---~,------+

OUTPUT

0----,-----......

3.0V------:::l~:---~

GND---.!.::.:;:;jr

I

30 pF

R2
27211

I

,NCLUD,NG
JIGP>ND
..,. SCOPE
..,.

R2
27211

5 pF

... 6nl

0014-5

,NCLUD,NG
_JIGP>NO _
- SCOPE
-

0014-4

Figure la
Equivalent to:

Figure Ib

THEVENIN EQUIVALENT
16m
OUTPUT

0---'1
..",
..£I\0'--""01.73V
0014-6

Switching Characteristics Over the Operating Range[4, 6)
Parameters

Description

7C401-5
7C402-5

Test
Conditions

Min.

7C4OX-I0

Max.

Min.

Max.

7C40X-15
Min.

Max.

7C40X-25 [12]
Min.

IS

Units

Max.

fo

Operating Frequency

tpHS!

SI HIGH Time

20

20

20

11

ns

tpLS!

SILOWTin1e

45

30

25

20

ns

tSS!

Data Setup to SI

Note 8

0

0

0

0

ns

tHS!

Data Hold from SI

Note 8

60

40

30

20

ns

Note 7

10

5

25

MHz

tOLlR

Delay, SI HIGH to IR LOW

75

40

35

21122

ns

tOH!R

Delay, SI LOW to IR HIGH

75

45

40

28/30

ns

tpHSO

SO HIGH Time

20

20

20

11

tpLSO

SO LOW Time

45

25

25

20

tOLOR

Delay, SO HIGH to OR LOW

75

40

35

19/21

ns

tDHOR

Delay, SO LOW to OR HIGH

80

55

40

34/37

ns

tSOR

Data Setup to OR HIGH

0

0

0

0

tHSO

Data Hold from SO LOW

5

5

5

5

tBT

Bubble through Time

tS!R

Data Setup to IR

Note 9

5

5

5

5

ns

tHIR

Data Hold from IR

Note 9

30

30

30

20

ns

tpiR

Input Ready Pulse HIGH

20

20

20

IS

ns

tPOR

Output Ready Pulse HIGH

20

20

20

IS

ns

tpMR

MR Pulse Width

40

30

25

25

ns

tOSI

MR HIGH to SI HIGH

40

35

25

10

tOOR

MR LOW to OR LOW

85

40

35

35

ns

tDlR

MR LOW to IR HIGH

85

40

35

35

ns

tLZMR

MR LOW to Output LOW

Note 10

50

40

35

25

ns

tOOE

Output Valid from OE LOW

35

30

20

ns

tHZOE

Output HIGH-Z from OE HIGH

Note 11

-

30

25

15

ns

200

Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing
reference levels of 1.5V and output loading of the specified 10VIoH
and 30 pF load capacitance, as in Figure 1a.
7. I/fo> tpHSI + tOHIR, lifo> tpHSO + tOHOR
8. tSSI and tHS! apply when memory is not full.
9. tSIR and tHIR apply when memory is full, SI is high and minin1um
bubble through (tBT) conditions exist.

10

95

10

65

10

ns
ns

ns
ns
50/60

ns

ns

10. All data outputs will be at LOW level after reset goes high until data
is entered into the FIFO.
11. HIGH-Z transitions are referenced to the steady-state VOH - 500
m V and VOL + 500 m V levels on the output. tHZOE is tested with 5
pF load capacitance as in Figure lb.
12. Commercial/Military

5-26

CY7C401/CY7C403
~
-=.
CY7C402/CY7C404
~~~====================
Operational Description
ified in a Datasheet, but necessary for reliable operation
under all conditions.
When an empty FIFO is filled with initial information, at
maximum \'shift in" SI frequency, followed by immediate
shifting out of the data also at maximum "shift out" SO
frequency, the designer must be aware of a window of time
which follows the initial rising edge of the "output Ready"
OR signal during which the SO signal is not recoginized.
This condition exists only at high speed operation where
more than one SO may be generated inside the prohibited
window. This condition does not inhibit the operation of
the FIFO at full frequency operation, but rather delays the
full 25 MHz operation until after the window has passed.
There are several implementation techniques to manage the
window so that all SO signals are recognized:
1. The first involves delaying SO operation such that it
does not occur in the critical window. This can be accomplished by causing a fixed delay of 40 ns "initiated
by the SI signal only when the FIFO is empty" to inhibit
or gate the SO activity. This however requires that the
SO operation at least temporarily be synchronized with
the input SI operation. In synchronous applications this
may well be possible and a valid solution.
2. Another solution not uncommon in synchronous applications is to only begin shifting data out of the FIFO
when it is greater than half full. This is a common method of FIFO application, as earlier FIFOs could not be
operated at maximum frequency when near full or empty. Although Cypress FIFOs do not have this limitation,
any system designed in this manner will not encounter
the window condition described above.
3. The window may also be managed by not allowing the
first SO signal to occur until the window in question has
passed. This can be accomplished by delaying the SO
40 ns from the rising edge of the initial OR "output
ready" signal. This however involves the requirement
that this only occurs on the first occurance of data being
loaded into the FIFO from an empty condition and
therefore requires the knowledge of "input ready" IR
and SI conditions as well as SO.
4. Handshaking with the OR signal can be a third method
of avoiding the window in question. With this technique
the rising edge of SO, or the fact that the SO signal is
HIGH, will cause the OR signal to go LOW. The SO
signal is not taken low again, advancing the internal
pointer to the next data, until the OR signal goes LOW.
This assures that the SO pulse that is initiated in the
window will be automatically extended sufficient time to
be recognized.
5. There remains the decision as to what signal will be used
to latch the data from the output of the FIFO into the
receiving source. The leading edge of the SO signal is
most appropriate because data is guaranteed to be stable
prior to and after the SO leading edge for each FIFO.
This is a solution for any number of FIFOs in parallel.
Any of the above solutions will provide a solution for correct operation of a Cypress FIFO at 25 MHz. The specific
implementation is left to the designer and dependent on the
specific application needs.

CONCEPT
Unlike traditional FIFOs these devices are designed using a
dual port memory, read and write pointer, and control logic. The read and write pointers are incremented by the
Shift Out (SO) and Shift In (SI) respectively. The availability of an empty space to shift in data is indicated by the
Input Ready (IR) signal, while the presence of data at the
output is indicated by the Output Ready (OR) signal. The
conventional concept of bubble through is absent. Instead,
the delay for input data to appear at the output is the time
required to move a pointer and pr~gate an Output Ready
(OR) signal. The Output Enable (OE) signal provides the
capability to OR tie multiple FIFOs together on a common
bus.
RESETTING THE FIFO
Upon power up, the FIFO must be reset with a Master
Reset (MR) signal. This causes the FIFO to enter an empty
condition signified by the Output Ready (OR) signal being
LOW at the same time the Input Ready (IR) signal is
HIGH. In this condition, the data outputs DOo-DOn) will
be in a LOW state.
SHIFfING DATA IN
Data is shifted in on the rising edge of the Shift In (SI)
signal. This loads input data into the first word location of
the FIFO. On the falling edge of the Shift In (SI) signal,
the write pointer is moved to the next word position and
the Input Ready (IR) signal goes HIGH indicating the
readiness to accept new data. If the FIFO is full, the Input
Ready (IR) will remain LOW until a word of data is shifted out.
SHIFfING DATA OUT
Data is shifted out of the FIFO on the falling edge of the
Shift Out (SO) signal. This causes the internal read pointer
to be advanced to the next word location. If data is present,
valid data will appear on the outputs and the Output
Ready (OR) signal will go HIGH. If data is not present,
the Output Ready (OR) signal will stay LOW indicating
the FIFO is empty. Upon the rising edge of Shift Out (SO),
the Output Ready (OR) signal goes LOW. The data outputs of the FIFO should be sampled with edge sensitive
type D flip-flop (or equivalent), using the SO signal as the
clock input to the flip-flop.
BUBBLE THROUGH
Two bubble through conditions exist. The first is when the
device is empty. After a word is shifted into an empty device, the data propagates to the output. After a delay, the
Output Ready (OR) flag goes HIGH indicating valid data
at the output.
The second bubble through condition occurs when the device is full. Shifting data out creates an empty location
which propagates to the input. After a delay, the Input
Ready (IR) flag goes HIGH. If the Shift In (SI) signal is
HIGH at this time, data on the input will be shifted in.
APPLICATION OF THE 7C403-25/7C404-25
AT 25 MHz
Application of the CY7C403 or CY7C404 Cypress CMOS
FIFO's requires attention to characteristics not easily spec-

5-27

Switching Waveforms
Data In Timing Diagram
t - - - - - - I / F O ' - - - - - _ . . j . . . - - -_ _ _ I/FO' _ _ _ _ _ _~

SHIFT IN

INPUT READY

DATA IN

0014-7

Data Out Timing Diagram
f-----I/FO-----+I-o>------llFo------l

SHIFT OUT

OUTPUT READY

DATA OUT

0014-8

Bubble Through, Data Out To Data In Diagram
SHIFTOUT

---.I,....---.--fl_~

_. J

t

\\.------

.1

'IT

-.~J

INPUTAEADV

DATA IN

-''''

"'IR

t
I

Note:
Interfacing to the FIFOPlease refer to the Interfacing to the FIFO applications brief in the Applications Section at the back of this data book.

5-28

0014-9

lin

•

CY7C401/CY7C403
CY7C402/CY7C404

. CYPRFSS

$W~DUaoR==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Switching Waveforms (Continued)
Bubble Through, Data In To Data Out Diagram

I----'OT----+---OUTPUT READY

DATA OUT

1...-------

--------E-~R--------------------

0014-10

Master Reset Timing Diagram
I-----'PMR_

~

MASTER RESET

jl
tDIR

INPUT READY

)

,

tDaR

OUTPUT READY

"'"
SHIFT IN
i o ! ' _ - - ' L Z M R ! -_ _
~

J

DATA OUT

0014-11

Output Enable Timing Diagram

OUTPUT ENABLE

DATA OUT

_~4HZOE); 'b_=<~_
-

-

NOTE 9

0014-12

5-29

.

fjn
.
.

CY7C40l/CY7C403
CY7C402/CY7C404

~UcroR~=================================================================

Typical DC and AC Characteristics
NO~SUPPLYCURRENT

NORMA~DSUPPLYCURRENT

VI

SUPPLY VOLTAGE

1.2

.M

1.0

~

..z

0.8

0.6

i

V

0.4
4.0

./

Vee -S.5V

V,N -5.0V
TA j25'C
4.5

5.0

VoN -5.0V

NORMALIZED FREQUENCY
SUPPLY VOLTAGE

.
z

0.9

51

20

5
~

1

V

~

-

-

~

~

-

j
z

0.8

0

o

4.5

5.0

5.5

6.0

.

/

1.3

N

.
C

1.2

z

1.1

:IE
0

1.0

/

o

..'".
a

120

!i

100

..

80

z

1.0t-------~o;::_--------_l

,,/

@ 1.4

...0
'"
::;

1

12~r-----_+----------~

iii

~

t--------+-----------I

TYPICAL FREQUENCY CHANGE
VI. OUTPUT WADING

> 1.5

I

--

0

/

80

40

/

20

If
o

800

800

/

'"

4.0

-"'" ~

Vee '5.0 V

J
1.0

0.0

TA -25'C

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

/

1.0

.LV

11
~

0.9

V

0.'

/

0.7

400

~

NORMALIZED Icc
1. 1 VI• FREQUENCY

I

V
200

3.0

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

AMBIENT TEMPERATURE ('C)

u
zw

2.0

1.0

140

SUPPLY VOLTAGE (V)

1.6

,,~

VI

1.4r-----+-------i

0.8

i"\..

OUTPUT VOLTAGE (V)

0.8 -66'=-------25~----------,-,!125

0.7

4.0

"'"

Vee -5.0V
TA ·25'C

0

NORMALIZED FREQUENCY
AMBffiNT TEMPERATURE

~

.
C

30

1.6

'" 1.1
a

:IE
0

~

VI.

VI

z

1.0

40

AMBIENT TEMPERATURE I'C)

> 1.2
u

'"...
0
'"N
::;

~

~~~~~------~25~--------~125

6.0

5.5

SUPPLY VOLTAGE IV)

1.3

"

50

&1

V

0

OUTPUT SOURCE CURRENT
VI OUTPUT VOLTAGE

80

/

/

0

-'
C
:IE

1.4 VI. AMBIENT TEMPERATURE

o0

1000

5

/
10

15

20

25

30

35

FREQUENCY (MHz)

CAPACITANCE (pF)

0014-13

5-30

5A~~NDUcroR===================================================================
CY7C40l/CY7C403
CY7C402/CY7C404

FIFO Expansion
128 x 4 Application
SHIFT IN

OR

SI

OR

OUTPUT READ~

INPUT READY

SO

IR

so

SHIFT OUT

DOD

DID

DOD

DO,

01,

DO,

002

01 2

003

01 3

Nmo---------~------

__________

..

}~ ~

002
MR

D03

~

00'4-'4

FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.

192 x 12 Application

so

IR
OR
r - - - SI
DOD
DID
DO,
01,
01,
DO,
0 13 MA 003

--

,..-,...\"j--

so

IR

OR
- - - - SI
DOD
- DID
- 01,
DO,
002
- 01 2
- 013 IIlR DD3

012
01 3 MA D03

-

IR
SI
DID
01,
0 12
0 13

so

OR
DOD
DO,
DO,

DI311lR 003

'J'

IR
SO
SI
OR
DID
DOD
01,
DO,
01,
002
0 13 IIlR D03

IR
OR
SI
DID
DOD
01,
DO,
01,
002
013 MA 003

so

so

IR
SI
DID

OR

DOD
DI,
DO,
DO,
0 12
01 3 MA D03

r

1

---

r-

rrr-

COMPOSITE
OUTPUT READY

~

~

Y

1

OR
DOD
DO,
002
Mi'i D03

SHIFT OUT

so

IR
SI
DID
01,
01,

T

I
SHIFT IN

OR
DOD
DO,
DO,

DI,

L

COMPOSITE
INPUT READY

so

IR
SI
DID

so I---

IR
SI
DID
01,
01,

OR

DOD
DO,
DO,
013 IIlR D03

'J'

f-

r-

rfMi'i
00'4-'5

FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite Input and Output
Ready flags. This need is due to the variation of delays of the FIFOs.
User Notes:
I. When the memory is empty the last word read will remain on the
outputs until the master reset is strobed or a new data word bubbles
through to the output. However, OR will remain LOW, indicating
data at the output is not valid.
2. When the output data changes as a result of a pulse on SO, the OR
signal always goes LOW before there is any change in output data and
stays LOW until the new data has appeared on the outputs. Anytime
OR is HIGH, there is valid stable data on the outputs.
3. If SO is held HIGH while the memory is empty and a word is written
into the input, that word will ripple through the memory to the output. OR will go HIGH for one internal cycle (at least tORd and then
go back LOW again. The stored word will remain on the outputs. If
more words are written into the FIFO, they will line up behind the
first word and will not appear on the outputs until SO has been
brought LOW.

4. When the master reset is brought LOW, the outputs are cleared to
LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the
master reset goes HIGH then the data on the inputs will be written
into the memory and IR will return to the LOW state until SI is
brought LOW. IfSI is LOW when the master reset is ended, then IR
will go HIGH, but the data on the inputs will not enter the memory
until SI goes HIGH.
5. All Cypress FIFOs will cascade with other Cypress FIFOs. However,
they may not cascade with pin-compatible FIFO's from other manufacturers.

5-31

fill

CY7C401/CY7C403
CY7C402/CY7C404

~~~~UaoR==============================================================~

Ordering Information
Ordering Code
(25 MHz)
CY7C401-25PC
CY7C402-25PC
CY7C403-25PC
CY7C404-25PC
CY7C401-25DC
CY7C402-25DC
CY7C403-25DC
CY7C404-25DC
CY7C401-25LC
CY7C402-25LC
CY7C403-25LC
CY7C404-25LC
CY7C401-25DMB
CY7C402-25DMB
CY7C403-25DMB
CY7C404-25DMB
CY7C40 1-25LMB
CY7C402-2SLMB
CY7C403-2SLMB
CY7C404-2SLMB

Package Operating
Type
Range
Pl
P3
Pl
P3
D2

Com.

D4
D2

D4
L61
L61
L61
L61
D2

D4
D2

D4
L61
L61
L61
L61

Mil.

Package 'Operating
Type
Range

Ordering Code
(15 MHz)
CY7C401-15PC
CY7C402-15PC
CY7C403-15PC
CY7C404-15PC
CY7C401-15DC
CY7C402-15DC
CY7C403-1SDC
CY7C404-15DC
CY7C401-15LC
CY7C402-15LC
CY7C403-15LC
CY7C404-1SLC
CY7C401-15DMB
CY7C402-15DMB
CY7C403-1SDMB
CY7C404-1SDMB
CY7C401-1SLMB
CY7C402-1SLMB
CY7C403-15LMB
CY7C404-1SLMB

Pl
P3
Pl
P3
D2

Com.

D4
D2

D4
L61
L61
L61
L61
D2

D4
D2

D4
L61
L61
L61
L61

5-32

Mil.

Ordering Code
(10 MHz)

Package Operating
Type
Range

CY7C401-lOPC
CY7C402-10PC
CY7C403-lOPC
CY7C404-10PC
CY7C401-lODC
CY7C402-lODC
CY7C403-10DC
CY7C404-10DC
CY7C401-lOLC
CY7C402-lOLC
CY7C403-lOLC
CY7C404-lOLC
CY7C401-lODMB
CY7C402-lODMB
CY7C403-10DMB
CY7C404-10DMB
CY7C401-lOLMB
CY7C402-lOLMB
CY7C403-10LMB
CY7C404-lOLMB

Pl
P3
Pl
P3
D2

Com.

D4
D2

D4
L61
L61
L61
L61
D2

Mil.

D4
D2

D4
L61
L61
L61
L61

Ordering Code
(5 MHz)

Package
Type

Operating
Range

CY7C401-SPC
CY7C402-SPC

Pl
P3

Com.

&'n

CY7C401/CY7C403
CY7C402/CY7C404

CYPRESS

~OO~UQOR~==================================================~====~

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

lIX

1,2,3

loz

1,2,3

los

1,2,3

Icc

1,2,3

Switching Characteristics
Parameters

Subgroups

Parameters

Subgroups

fo

7,8,9,10,11

tooE

7,8,9,10,11

tpHSI

7,8,9,10,11

tHZOE

7,8,9,10,11

tpLSI

7,8,9,10,11

tSSI

7,8,9,10,11

tHSI

7,8,9,10,11

tOLIR

7,8,9,10,11

tOHIR

7,8,9,10,11

tpHSO

7,8,9,10,11

tpLSO

7,8,9,10,11

tOLOR

7,8,9,10,11

tOHOR

7,8,9,10,11

tSOR

7,8,9,10,11

tHSO

7,8,9,10,11

tBT

7,8,9,10,11

tSIR

7,8,9,10,11

tHIR

7,8,9,10,11

tpIR

7,8,9,10,11

tPOR

7,8,9,10,11

tpMR

7,8,9,10,11

toS!

7,8,9,10,11

tOOR

7,8,9,10,11

tDiR

7,8,9,10,11

tLZMR

7,8,9,10,11

Document #: 38-00040-0

5-33

CY7C408A
CY7C409A

CYPRESS
SEMICONDUCTOR

Cascadeable 64
Cascadeable 64

X
X

8 FIFO
9 FIFO

Features
AFE is HIGH when the FIFO is almost full or almost empty, otherwise
AFE is LOW. HF is HIGH when the
FIFO is half full, otherwise HF is
LOW.
The CY7C408A has an Output Enable
(OE) function.
The memory accepts 8- or 9-bit parallel
words at its inputs (Dlo-Dls) under
the control of the Shift-In (SI) input
when the Input-Ready (IR) control signal is HIGH. The data is output, in the
same order as it was stored, on the
000-DOs output pins under the control of the Shift-Out (SO) input when
the Output-Ready (OR) control signal
is HIGH. If the FIFO is full (IR
LOW), pulses at the SI input are ignored: if the FIFO is empty (OR
LOW), pulses at the SO input are ignored.
The IR and OR signals are also used to
connect the FIFO's in parallel to make
a wider word, or in series to make a
deeper buffer, or both.
Parallel expansion for wider words is
implemented by logically ANDing the
IR and OR outputs (respectively) of
the individual FIFOs together (Figure
7). The AND operation insures that all
of the FIFOs are either ready to accept

• 64 x 8 and 64 x 9 rll'st-in firstout (FIFO) buffer memory
• 35 MHz shift-in and shift-out
rates
• Almost Full/Almost Empty and
Half Full flags
• Dual port RAM architecture
• Fast, 50 ns, bubblethrough
• Independent asynchronous inputs
and outputs
• Output Enable (CY7C408A)
• Expandable in word width and
FIFO depth
.
• 5V ± 10% supply
• TIL compatible
• Capable of withstanding greater
than 2000V electrostatic
discharge voltage
• 300 mil, 28-pin DIP

Functional Description
The CY7C408A and CY7C409A are
64-word deep by 8- or 9-bit wide fll'Stin fll'st-out (FIFO) buffer memories. In
addition to the industry standard handshaking signals, Almost FulVAlmost
Empty (AFE) and Half Full (HF) flags
are provided.

more data (IR HIGH) or are ready to
output data (OR HIGH) and thus
compensate for variations in propagation delay times between devices.
Serial expansion (cascading) for deeper
buffer memories is accomplished by
connecting the data outputs of the
FIFO closest to the data source (upstream device) to the data inputs ofthe
following (downstream) FIFO (Figure
6). In addition, to insure proper operation, the SO signal of the upstream
FIFO must be connected to the IR output of the downstream FIFO and the
SI signal of the downstream FIFO
must be connected to the OR output of
the upstream FIFO. In this serial expansion configuration, the IR and OR
signals are used to pass data through
theFIFOs.
Reading and writing operations are
completely asynchronous, allowing the
FIFO to be used as a buffer between
two digital machines of widely differing
operating frequencies. The high shift-in
and shift-out rates of these FIFOs, and
their high throughput rate due to the
fast bubblethrough time, which is due
to their dual port RAM architecture,
make them ideal for high speed communications and controllers.

Logic Block Diagram

Pin Configurations
'FE
WRITE POINTER
AFE

SI

IR

HF

WRITE MULTIPLEXER

0',
ru,

6

GND

~'.
017

MEMORY
ARRAY

(7C409A) 01.

00. (7C409A)
0E(7C40.A)
READ MULTIPLEXER
OR
READ POINTER

01,
01,
7C408A NC
7C409A Dla

L-_ _...I

SO

0065-2
in!!

0065-1

HF
L
L
H
H

Flag Definitions
AFE
Words Stored
H
0-8
L
9-31
L
32-55
H
56-64

01"

5" 3

01,

6

G~I~ ~

~

$ ~I~

&1

ilTI28272~5
24

;g:~

OR
00111

~: ~~

013
014

9
10

21
20

002
D0 3

Dis

1'1213141516171~9

00 4

U!~gU
z

5-34

10

0065-3

7C408A·15
7C409A·15

7C408A·35
7C409A·35

IS

25

Commercial

115

125

35
135

Military

140

ISO

N/A

Maximum Shift Rate (MHz)
Maximum Operating
Current (rnA)[21

7C408A·25
7C409A·25

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... >2001V
Storage Temperature ............... -65°C to + 150"C
Ambient Temperature with
(per MIL-STD·883 Method 3015)
Power Applied .................... - 55°C to + 125°C
Operating Range
Supply Voltage to Ground Potential .... -0.5V to + 7.0V
Ambient
Range
DC Voltage Applied to Outputs
Vee
Temperature
in High Z State (7C408A) ............. -0.5V to +7.0V
Commercial
O"Cto +70"C
SV ±IO%
DC Input Voltage ................... - 3.0V to + 7.0V
Military[41
- SS·C to + 12S·C
5V ±IO%
Power Dissipation ............................. l.OW
Output Current, into Outputs (Low) ............. 20 rnA

Electrical Characteristics Over Operating Range (Unless Otherwise Noted)!S]
Parameters

Description

CY7C408A
CY7C409A

Test Conditions

Min.
VOR

Output HIGH Voltage

Vee = Min., lOR = -4.0rnA

VOL

Output LOW Voltage

Vee = Min.,IOL = 8.0 rnA

VIR

Input HIGH Voltage

VIL

Input LOW Voltage

IIX

Input Leakage Current

GND::;; VI::;; Vee

-10

los

Output Short Circuit Currentl11

Vee = Max., VOUT = GND

leeQ

Quiescent Power Supply Current

Vee = Max., lOUT = OmA
VIN ::;; VIL, VIN ~ VIH

lee

Power Supply Current

lee = I~ + I rnA/MHz X (fSI + fso)/2

Unlta

Max.

2.4

V
0.4

V

2.2

Vee

V

-3.0

0.8

V

+10

",A

-90

rnA

Commercial

100

rnA

Military

125

rnA

Capacitance [3]
Test Conditions

Max.

CIN

Input Capacitance

TA = 25·C,f= I MHz

5

CoUT

Output Capacitance

Vee = 4.SV

7

Parameters

Description

Notes:
I. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
2. Icc = Ic~ + I mA/MHz X (fsl + fso)/2

Units
pF

3. Tested initially and after any design or process changes that may
affect these parameters.
4. TA is the "instant on" case temperature.
5. See the last page of this specification for Group A subgroup testing
information.

AC Test Load and Waveforms
Rl 48211

R1482Jl

5V:£j

5V:£1

OUTPUT

OUTPUT

CL

I

~~6Jl

30 pF

-=

INCLUDING
JIG AND
SCOPE

5 pF

-=

I-=

~~SJl
INCLUDING
JIG AND
SCOPE

Equivalent to:

-=
0065-21

0065-4

Figure Ib

Figure 18
THEVENIN EQUIVALENT

,..,,..,-_0

1870

OUTPUT

0_-",\..

3.0V---:::ll-.::::::---'"L

1.73V

0065-6

5·35

Figure 2. All Input Pulses

0065-5

fiA
.

CY7C408A
CY7C409A

~~u~=============================================================

Switching Characteristics Over the Operating Range[5, 6]
Parameters

Description

Test
Conditions

CY7C408A·15
CY7C409A·15

CY7C408A·25
CY7C409A·25

Min.

Min.

Max.
15

Max.
25

CY7C408A·35
CY7C409A·35
Min.
Max.
35

Units

fo

Operating Frequency

Note 7

tpHSI

SI HIGH Time

Note 7

23

11

9

ns

tpLSI

SILOWTime

Note 7

25

24

17

ns

tssI
tHSI

Data Setup to SI
Data Hold from SI

NoteS
NoteS

0
30

0
20

0
12

ns
ns

tOLIR

Delay, SI HIGH to IR LOW

35

21

15

ns

tOHIR
tpHSO

Delay, SI LOW to IR HIGH
SO HIGH Time

40

23

16

ns

tpLSO

SO LOW Time
Delay, SO HIGH to OR LOW

tOLOR
tOHOR

Note 7

23

11

9

Note 7

25

24

17

35

Delay, SO LOW to OR HIGH

21
23

40

MHz

ns
15

ns
ns

16

ns

tSOR

Data Setup to OR HIGH

0

0

0

ns

tHSO
tBT

Data Hold from SO LOW
Fa11through, Bubbleback Time

0
10

0
10

0
10

tSIR

Data Setup to IR

Note 9

ns
ns
ns

tHIR
tpIR

Data Hold from IR
Input Ready Pulse HIGH

Note 9
Note 10

Output Ready Pulse HIGH
OE LOW to LOW Z (7C408)

Note 11
Note 12

OE HIGH to HIGH Z (7C408)

Note 12

tpOR
tOLZOE
tOHZOE
tOHHF
tOLHF
tDLAFE

65

60

5
30

5
20

5
20

6

6

6

6

SI LOW to HF HIGH
SO LOW to HF LOW
SO or SI LOW to APE LOW

tOHAFE
tpMR

SO or SI LOW to AFE HIGH
MR Pulse Width

55

tOSI

MR HIGH to SI HIGH

25

tOOR
tDlR

MR LOW to OR LOW
MR LOW to IR HIGH

tLZMR
tAFE

MR LOW to Output LOW

6

ns
ns

35

30

25

ns
ns

35

30

25

ns

65

55

65
65

55
55

45
45

ns
ns

45

ns

45

ns
ns

65

Note 13

50

6

55
45

35

10

ns

10

55
55

45
45

35
35

ns
ns

55

45

35

ns

MR LOW to AFE HIGH

55

45

35

ns

MR LOW to HF LOW

55

45

35

ns

tHF
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing
reference levels of 1.5V and output loading of the specified IOL/IoH
and 30 pF load capacitance, as in Figure 1.
7. lifo:;' (tpHSI + tPLSI), lifo:;' (tpHSO + tpLSO)·
8. tSSI and tHSI apply when memory is not full.
9. tSIR and tHiR apply when memory is full, SI is HIGH and minimum
bubblethrough (tOT) conditions exist.
10. At any given operating condition tplR :;, (tPHSO required).

11 At any given operating condition tPOR :;, (tpHSI required).
12. tDHZOE and tDLZOE are specified with CL = 5 pF as in Figure 1h.

tDHZOE transition is measured ± 500 mV from steady state voltage.
tDLZOE transition is measured ± 100 mV from steady state voltage.
These parameters are guaranteed and not 100% tested.
13. All data outputs will be at LOW level after reset goes HIGH until
data is entered into the FIFO.

5-36

CY7C408A
CY7C409A

fir:~NDUCIOR
Switching Waveforms
Data In Timing Diagram
liFO

liFO

SHIFT IN

INPUTREADV

DATA IN

AFE

HF

(LOW)

0065-7

 FIFO Contains 56 Words

Bubbleback, Data Out to Data In Diagram

J
fr-------t+-------------------'"'I\"'_______

."'~~
SHIFTIN

.1

tiT

)~",J

INPUT READY

DATA IN

~"'R

tHIR

0065-9

CD FIFO Contains 64 Words

5-39

&n

CY7C408A
CY7~A

crm$

~l~~R======================================================~~~~~

Switching Waveforms (Continued)
Fallthrough, Data In to Data Out Diagram
SHIFT IN

SHIFT OUT

OUTPUT READY

DATA OUT

____________:'.=====_t8_T~~~-~~----~~___________
________________~~-~-R~----------------------0065-10

CI> FIFO Is Empty

Master Reset Timing Diagram
I----tPMR_

MASTER RESET

'r-

.,~
j
tDIA

INPUT READY

j
tOCR

\

OUTPUT READY
toS!

SHIFT IN

)

tLZMR

1\

DATA OUT

HF

AFE

tHF

tAFE

\
f
0065-11

5·40

CY7C408A
CY7C409A

~

~~~~R~===========================================================
Shifting Words In

Et.lPTY
1

SHIFT IN

2

SlI'l ...

8

9

10

31

32

33

55

56

57

F'Ull
64

_.n.

... ~_...- + - -..

HF' ______________~~------------~

AF'E
0065-18

Figure 3

Shifting Words Out
F'Ull
64

SHIFT OUT

63

SlI'l ...

56

55

54

32

31

30

9

8

7

Et.lPTY
1

...n.

HF'

AF'E
0065-19

Figure 4
through time when it is empty (or near empty) and by the
bubbleback time when it is full (or near full).

Architecture of the CY7C408A and
CY7C409A

The conventional definitions of fallthrough and bubbleback
do not apply to the CY7C408A and CY7C409A FIFOs
because the data is not physically propagated through the
memory. The read and write pointers are incremented instead of moving the data. However, the parameter is specified because it does represent the worst case propagation
delay for the control signals. That is, the time required to
increment the write pointer and propagate a signal from
the SI input to the OR output of an empty FIFO or the
time required to increment the read pointer and propagate
a signal from the SO input to the IR output of a full FIFO.

The CY7C408A and CY7C409A FIFOs consist of an array of 64 words of 8- or 9-bits each (which are implemented using a dual port RAM cell), a write pointer, a read
pointer and the control logic necessary to generate the
handshaking (SI/IR, SO/OR) signals as well as the Almost
Full!Almost Empty (AFE) and the Half Full (HF) flags.
The handshaking signals operate in a manner identical to
those of the industry standard CY7C40l/402I403/404
FIFOs.

Dual Port RAM

Resetting the FIFO

The dual port RAM architecture refers to the basic memory cell used in the RAM. The cell itself enables the read
and write operations to be independent of each other,
which is necessary to achieve truly asynchronous operation
of the inputs and outputs. A second benefit is that the time
required to increment the read and write pointers is much
less than the time that would be required for data to propagate through the memory, which would be the case if the
memory were implemented using the conventional register
array architecture.

Upon power up, the FIFO must be reset with a Master
Reset (MR) signal. This causes the device to enter the empty condition, which is signified by the OR signal being
LOW at the same time that the IR signal is HIGH. In this
condition, the data outputs (DOo-DOs) will be LOW. The
AFE flag will be HIGH and the HF flag will be LOW.

Shifting Data Into the FIFO
The availability of an empty location is indicated by the
HIGH state of the Input Ready (IR) signal. When IR is
HIGH a LOW to HIGH transition on the Shift-In (SI) pin
will load the data on the DID-DIs inputs into the FIFO.

Fallthrough and Bubbleback
The time required for data to propagate from the input to
the output of an initially empty FIFO is defined as the
Fallthrough time.

The IR output will then go LOW, indicating that the data
has been sampled. The HIGH to LOW transition of the SI
signal initiates the LOW to HIGH transition of the IR
signal if the FIFO is not full. If the FIFO is full, IR will
remain LOW.

The time required for an empty location to propagate from
the output to the input of an initially full FIFO is defined
as the Bubbleback time.
The maximum rate at which data can be passed through
the FIFO (called the throughput) is limited by the fall-

5-41

~

CY7C408A
CY7C409A

~~~PRESS

~, SEMICONDUCTOR =================================
must be inverted before being fed back to the interface SO
pin (Figure 5). Two things should be noted when this configuration is implemented.

Shifting Data Out of the FIFO

The availability of data at the outputs of the FIFO is indicated by the HIGH state of the Output Ready (OR) signal.
After the FIFO is reset all data outputs (DOo- DOg) will
be in the LOW state. As long as the FIFO remains empty
the OR signal will be LOW and all Shift Out (SO) pulses
applied to it will be ignored. After data is shifted into the
FIFO the OR signal will go HIGH. The external control
logic (designed by the user) should use the HIGH state of
the OR signal to generate a SO pulse. The data outputs of
the FIFO should be sampled with edge sensitive type D
flip-flops (or equivalent), using the SO signal as the clock
input to the flip-flop.

First, the capacity ofN cascaded FIFOs is decreased from
N X 64 to (N X 63) + I.
Secondly, the frequency at the cascade interface is less than
the 35 MHz rate at which the external clocks may operate.
Therefore, the first device has its data Shifted-In faster
than it is Shifted-Out and eventually this device becomes
momentarily full. When this occurs, the maximum sustainable external clock frequency changes from 35 MHz to the
cascade interface frequency.l14]
When data packets [15] are transmitted, this phenomenon
does not occur unless more than three FIFOs are depth
cascaded. For example, if two FIFOs are cascaded, a packet of 127 (= 2 X 63 + 1) words may be shifted-in at up to
35 MHz and then the entire packet may be shifted-out at
up to 35 MHz.
If data is to be shifted-out simultaneously with the data
being shifted-in, the concept of "virtual capacity" is introduced. Virtual capacity is simply how large a packet of
data can be shifted-in at a fixed frequency, e.g., 35 MHz,
simultaneously with data being shifted-out at any given frequency. Figure 8 is a graph of packet size[i6] vs. shift-out
frequency (fSOx) for two different values of Shift-In frequency (fSIx) when two FIFOs are cascaded.

Interfacing to the FIFO Application Brief
See the application brief in the back of this databook for
information regarding interfacing to the FIFO under asynchronous operating conditions.

AFE and HF Flags
Two flags, Almost Full/Almost Empty (AFE) and Half
Full (HF), describe how many words are stored in the
FIFO. AFE is HIGH when there are eight or less, or 56 or
more, words stored in the FIFO. Otherwise the AFE flag is
LOW. HF is HIGH when there are 32 or more words
stored in the FIFO, otherwise the HF flag is LOW. Flag
transitions occur relative to the falling edges of SI and SO
(Figures 3 and 4).

The exact complement of this occurs if the FIFOs initially
contain data and a high Shift-Out frequency is to be maintained, i.e., a 35 MHz fsox can be sustained when reading
data packets from devices cascaded two or three deep. If
data is shifted-in simultaneously, Figure 8 applies with fSIx
and fSOx interchanged.

Due to the asynchronous nature of the SI and SO signals, it
is possible to encounter specific timing relationships which
may cause short pulses on the AFE and HF flags. These
pulses are entirely due to the dynamic relationship of the SI
and SO signals. The flags, however, will always settle to
their correct state after the appropriate delay (tDHAFE,
tDLAFE, tDHHF or tDLHF)' Therefore, use oflevel-sensitive rather than edge-sensitive flag detection devices is recommended to avoid false flag encoding.

Notes:
14. Because the data throughput in

the cascade interface is dependent on
the inverter delay, it is recommended that the fastest available invert-

er be used.
15. Transmission of data packets assumes that up to the maximum cu-

mulative capacity of the FIFOs is Shifted-In without simultaneous
Shift-Out clocks occurring. The complement of this holds when data
is Shifted-Out as a packet.
16. These are typical packet sizes using an inverter whose delay is 4 ns.
17. Only devices with the same speed grade are specified to cascade
together.

Cascading the 7C408/9A-35 Above 25 MHz
If cascaded FIFOs are to be operated with an external
clock rate greater than 25 MHz, the interface IR signal

51

c

B

A
IR

IR

SO

51

OR

~

IR

SO

51

OR

r--o
u

V

zw
0

1.4

/

w

II:

u.

Q

w

1.3

N

::;

«

1.2

z

1.1

:IE
0:
0

1.0

o

/

/

--

/

/

40

/

20

'I
o

1.0

0.0

3.0

4.0

l/

1.0

/V

u

2

c

w

0.9

/

c(

0:

0.8

cz

/

0.7

800

2.0

vs. FREQUENCY

::;

800

Vee ·B.OV
TA -25'C

J

NORMALIZED Icc
1.1

:IE

400

I"

OUTPUT VOLTAGE (V)

N

/
200

"

4.0

"... ~

AMBIENT TEMPERATURE I'CI

TYPICAL FREQUENCY CHANGE
VB. OUTPUT WADING

:::l

•.

:::l

0 . 8 ' - - - - - - ' - - - - - -.....
-55
25
125

6.0

5.5

W

c
W

0.7
4.5

100

0:
0:

~

4.0

120

...z

!

«
~

3.0

140

C
1.41-----t-------I

::;

"

2.0

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

w

5

~

OUTPUT VOLTAGE IV)

NORMALIZED FREQUENCY
VB. AMBIENT TEMPERATURE

~

1.0

rc)

1.6

,,-

10

Vee '5.0V
TA = 25'C

0

0.6'-_ _ _ _-'-_ _ _ _ _-'

>

/'

20

:::l

1.1

«

'" "

30

0:

1.3

1.0

,

:::l

>
1.2
zuw

::;

40

U

NORMALIZED FREQUENCY

N

0:
0:

u

vs. SUPPLY VOLTAGE

cw

50

:::l

SUPPLY VOLTAGE (V)

:::l

...:IE
w

V,N =5.0V

4.5

60

/

TA j25'C

0.4
4.0

0
w
0:
u.

OUTPUT SOURCE CURRENT
VB. OUTPUT VOLTAGE

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

VB.

o0

1000

CAPACITANCE IpF)

5

/

10

15

20

25

30

35

FR EQUENCY IMHz)

0065-23

5-45

fin
.

CY7C408A
CY7C409A

~~;=~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==

Ordering Information
Frequency
(MHz)

35

25

15

Ordering Code

Package
Type

Operating
Range

Frequency

Commercial

35

(MHz)

Ordering Code

Package
Type

Operating
Range
Commercial

CY7C408A·35PC

P21

CY7C409A·35PC

P21

CY7C408A·350C

022

CY7C409A·350C

022

CY7C408A·35LC

L64

CY7C409A·35LC

L64

CY7C408A·35VC

V21

CY7C409A·35VC

V21

CY7C408A·25PC

P21

CY7C408A·250C

CY7C409A·25PC

P21

022

CY7C409A·250C

022

CY7C408A·25LC

L64

CY7C409A·25LC

L64

CY7C408A·25VC

V21

CY7C409A·25VC

V21

CY7C408A·250MB

022

CY7C409A·250MB

022

CY7C408A·25LMB

L64

CY7C409A·25LMB

L64

Commercial

25

Military

CY7C408A·15PC

P21

CY7C409A·15PC

P21

CY7C408A·150C

022

CY7C409A·15DC

022

CY7C408A·15LC

L64

CY7C409A·15LC

L64

CY7C408A·15VC

V21

CY7C408A·150MB

022

CY7C408A·15LMB

L64

Commercial

15

Military

5·46

CY7C409A·15VC

V21

CY7C409A·150MB

022

CY7C409A·15LMB

L64

Commercial

Military
Commercial

Military

&n

CY7C408A
CY7C409A
~~®UQOR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MILITARY SPECIFICATIONS
Group A Subgroup Testing

DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

los

1,2,3

IccQ

1,2,3

Switching Characteristics
Parameters

Subgroups

Parameters

Subgroups

fo

7,8,9,10,11

tOLAFE

7,8,9,10,11

tpHSI

7,8,9,10,11

tOHAFE

7,8,9,10,11

tpLSI

7,8,9,10,11

tB

7,8,9,10,11

tSSI

7,8,9,10,11

too

7,8,9,10,11

tHSI

7,8,9,10,11

tpMR

7,8,9,10,11

tOLIR

7,8,9,10,11

tOSI

7,8,9,10,11

tOHIR

7,8,9,10,11

tOOR

7,8,9,10,11

tpHSO

7,8,9,10,11

tDIR

7,8,9,10,11

tpLSO

7,8,9,10,11

tLZMR

7,8,9,10,11

tOLOR

7,8,9,10,11

tAFE

7,8,9,10,11

tOHOR

7,8,9,10,11

tHF

7,8,9,10,11

tSOR

7,8,9,10,11

tHSO

7,8,9,10,11

tBT

7,8,9,10,11

tSIR

7,8,9,10,11

tHlR

7,8,9,10,11

tpIR

7,8,9,10,11

tpOR

7,8,9,10,11

tSIIR

7,8,9,10,11

tSOOR

7,8,9,10,11

tOLZOE

7,8,9,10,11

tOHZOE

7,8,9,10,11

tOHHF

7,8,9,10,11

tOLHF

7,8,9,10,11

Document IF: 38-00059-C

5-47

CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429

CYPRESS
SEMICONDUCTOR

Cascadeable 512
Cascadeable 1024
Cascadeable 2048

X
X

X

9 FIFO
9 FIFO
9 FIFO

Features
• 512 x 9, 1024 x 9, 2048 x 9
FIFO buffer memory
• Dual port RAM cell
• Asynchronous read/write

when the Write (W) signal is LOW.
Read occurs when Read (l{) goes
LOW. The 9 data outputs go to the
high impedance state when R: is
HIGH.

• CY7C421 pin compatible and
functional equivalent to IDT7201

Functional Description

• High speed 25 MHz read/write
independent of depth/width
• Low operating power
Icc (max.) = 125 mA commercial
Icc (max.) = 140 mA mllitary
• Half full flag in standalone
• Empty and full flags
• Retransmit in standalone
• Expandable in width and depth
• Parallel Cascade minimizes
bubblethrougb
• 5V ± 10% supply
• 300 mil DIP packaging
• 300 mil SOJ (512 x 9)
packaging
• TIL compatible
• Three-state outputs

Logic Block Diagram

The (CY7C420, CY7C421,)
(CY7C424, CY7C425,) and
(CY7C428, CY7C429) are, respectively, 512, 1024 and 2048 words by 9-bit
wide first-in first-out (FIFO) memories
offered in 600 mil wide and 300 mil
wide packages, respectively. Each
FIFO memory is organized such that
the data is read in the same sequential
order that it was written. Full and
Empty flags are provided to prevent
over-run and under-run. Three additional pins are also provided to facilitate unlimited expansion in width,
depth, or both. The depth expansion
technique steers the control signals
from one device to another in parallel,
thus eliminating the serial addition of
propagation delays so that throughput
is not reduced. Data is steered in a similar manner.
The read and write operations may be
asynchronous; each can occur at a rate
of 25 MHz. The write operation occurs

A Half-Full (lIP) output flag is provided that is valid in the standalone and
width expansion configurations. In the
depth expansion configuration this pin
provides the expansion out (XO) information which is used to tell the next
FIFO that it will be activated.
In the standalone and width expansion
configurations a LOW on the Retransmit (lIT) input causes the FIFO's to
retransmit the data. Read Enable (R)
and Write Enable (W) must both be
HIGH during a retransmit cycle, and
then R is used to access the data.
The CY7C420, CY7C421, CY7C424,
CY7C425, CY7C428 and CY7C429
are fabricated using an advanced 0.8
micron N-well CMOS technology. Input ESD protection is greater than
2000V and latchup is prevented by
careful layout, guard rings and a substrate bias generator.

Pin Configurations
DATA INPUTS

DIP
Top View

PLCC/LCC
Top View

(DO-DB)

a !'ill> !;! Jll!! i!l

Vee

4 3 2111323130

025
01 6
DO

NC 12

2906
28 01
21 NC
26 FL/RT
25 M1i
24 El'
23 xo/iif
22 a1

Q2

21

L..I

Xi
ff 9

ao

10

alii
13

~

D4

03

05
06
01

FL/RT
M1i

Q6

al

14151611181920

::H!I"!;!'''~8

DB

a6
0081-3

a3

as

Q8

a4

eND

0081-2

0081-1

5-48

(;n
.

CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429

~~=============================================================

Selection Guide

Shaded area contains preliminary information.

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -6S·C to + ISO"C
Static Discharge Voltage ..................... >2001V
Ambient Temperature with
(per MIL-STD-883 Method 301S)
Latch-up Current .......................... > 200 rnA
Power Applied .................... - SS·C to + 12S·C
Supply Voltage to Ground Potential .... -O.SV to + 7.0V
Operating Range
DC Voltage Applied to Outputs
Ambient
in High Z State ...................... - O.SV to + 7.0V
Range
Vee
Temperature
DC Input Voltage ................... -3.0Vto +7.0V
O"Cto +70"C
SV ±10%
Commercial
Power Dissipation ............................. l.OW
Military[3)
- SsoC to + 12S·C
SV ±10%
Output Current, into Outputs (Low) ............. 20 rnA

Electrical Characteristics Over Operating Range[4]
Parameters

Description

Units

Test Conditions

ISB!

Standby Current

ISBZ

Power Down Current

lOS

Output Short Circuit
Currend1l

All Inputs
Vee -O.2V

Shaded area contains preliminary information.

Capacitance [2]
Parameters
CIN
CoUT

Description
Input Capacitance
Output Capacitance

Test Conditions
TA = 2S·C, f = I MHz
Vee = 4.SV

Notes:
1. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
alTect these parameters.
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

S. Icc (commercial)

Max.
S
7

= 100 mA + [(I' f~

Units
pF

12.S) • 2 mAlMHzl for

12.SMHz

where f = the larger of the write or read
operatinl! frequency.
6. Icc initiates a write cycle. Data appearing at the inputs
(D0-D8) tSD before and tHD after the rising edge ofW
will be stored sequentially in the FIFO.
The Empty flag (EF) LOW to HIGH transition occurs
twEF after the first LOW to HIGH transition on the write
clock of an empty FIFO. The Half-Full flag (HF) will go
LOW on the falling edge of the write clock following the
occurrence of half full. HF will remain LOW while less
than one half of the total memory of this device is available
for writing. The LOW to HIGH transition of the HF flag
occurs on the rising edge of Read (R). HF is available in
Single Device Mode only. The Full flag (FF) goes low on
the falling edge ofW during the cycle in which the last
available location in the FIFO is written, prohibiting overflow. FF goes HIGH tRFF after the completion of a valid
read of a full FIFO.

Depth Expansion Mode (Figure 3)
Depth Expansion Mode is entered when, during a MR cycle, Expansion Out (XO) of one device is connected to
Expansion In (XI) of the next device, with XO ofthe last
device connected to XI of the first device. In the Depth
Expansion Mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded. All
other devices must have this pin HIGH. To enable the
correct FIFO, XU is pulsed LOW when the last physical
location of the previous FIFO is written to and is pulsed
LOW again when the last physical location is read. Only
one FIFO is enabled for read and one is enabled for write
at any given time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and
width. Consequently, any depth or width FIFO can be created of word widths in increments of9. When expandi~in
depth, a composite FF must be created by OR-ing the FFs
together. Likewise, a composite:EP is created by OR-ing
the:EPs together. HF and lIT functions are not available in
Depth Expansion Mode.

Reading Data from the FIFO
The falling ~ of Read (R) initiates a read cycle if the
Empty flag (EP) is not LOW. Data outputs (QO-Q8) are in
a high impedance condition between read operations (R
HIGH), when the FIFO is empty, or when the FIFO is in
the Depth Expansion Mode but is not the active device.

5-54

fin

CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429

. CYPRF5S

S~OO~U~R~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Architecture

(Continued)

XCi

iii
F"F

,

9

I I

,

9

..
r

~

R

CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429

EF

T

I
I--

~

I

9

I.

..>
Vee

Xi

-

FULL

XCi
FF

9, ..

,

-.,

~

14 EF

CY7C420 I - CY7C421
CY7C424
CY7C425 I--CY7C428
CY7C429

f--<

EMPTY

-

~

r- :--

Xi

XCi

......
'---

FF

, -.,

9,1.

RS

• +w-

CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429

Xi

i-

~

-

+}• FIRST DEVICE
0081-17

Figure 3. Depth Expansion

5-55

1:1

5n

CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429

.

~OOaoR~~~~~~~~~~~~~~~~~~~~~~==~~~~==~~~=
Typical DC and AC Characteristics
NORMAUZED SUPPLY CURRENT
SUPPLY VOLTAGE

VI.

1.2

0

1.0

J?
Q

'"~

..:

0.8

/'

2

'"0z

/

0.6

/

V

/

NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE

8

1.0

'"oZ

0.8

0.6
5.0

55

-55

6.0

SUPPLY VOLTAGE (V)

~..:

'"~
..:

1.1

..............

2

'"0z

0.9
0.8

~

30

25

1.6

5

10 Vcc =5.0V
TA =25OC

o

o

125

-- ----

Q

'"~

..:
2

'"0Z

1.2
1.0

~
0.8

!

120

Z

100

0-

'"'"

~

'"

80

'"
'"'"

60

:I
U

5.0

55

-55

25

0
Z

1.2

!

/

L

1.1

1.0

4.0

-

"

I
Vcc =5.0V
TA=25OC
1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

vs. FREQUENCY

1.1

V

.$ 1.4
Q
1.3

'"

1.3

15

N

3.0

NORMALIZED Icc

TYPICAL tA CHANGE
VI. OUTPUT LOADING

'"

o

125

AMBIENT TEMPERATURE (OC)

1.6

::J

/

/
20
oV

0

Vcc= 5.0V

6.0

2.0

/

40

0:I
0..
0:I

0.6
SU PPLY VOLTAGE (V)

"r-..,

OUTPUT SINK CURRENT
VI. OUTPUT VOLTAGE

140

..,.

TA =25OC

45

1.0

"

OUTPUT VOLTAGE (V)

vs. AMBIENT TEMPERATURE

.$

0.7
4.0

""

20

o

1.4

1.0

40

NORMALIZED tA

vs. SUPPLY VOLTAGE

1.2
Q

Ii

AMBIENT TEMPERATURE (OC)

NORMALIZED tA
1.3

50

~
5

Vcc =5.5V
VIN =5.0V
f=20MHz

VIN =5.0V
TA=25OC
45

!

a

-

"-

~

60

~

~1.2

0.4

4n

OUTPUT SOURCE CURRENT
VI. OUTPUT VOLTAGE

VI.

1.4

o

/
400

,/
600

/

"",,/
600

V"

/

VCC=:;,OV
TA=25OC

/
200

/

/

~

Vcc= 5.0V
ITA=25"C

o

o

1000

10

15

20

25

30

35

FREQUENCY (MHz)

CAPACITANCE (pF)

0081-18

5-56

1m
.

CY7C420, CY7C421, CY7C424
CY7C42S, CY7C428, CY7C429

• CYPRFSS

~~~OR====================================================~~~~~~

Ordering Information

Military
65

Commercial

Military

Shaded area contains preliminary information.

Military

6S

Commercial

Military

5·57

fiJi

CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429

. CYPRESS

$W~~~========================================~========~==~

Ordering Information (Continued)

Shaded area contains preliminary information.

5-58

(;n

CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429

• CYPRESS

~oo~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

VIH

1,2,3

VILMax.

1,2,3

IIX

1,2,3

Icc

1,2,3

ISBI

1,2,3

ISB2

1,2,3

los

1,2,3

Switching Characteristics
Parameters

Subgroups

Parameters

Subgroups

tRC

9,10,11

tREF

9,10,11

tA

9,10,11

tRFF

9,10,11

tRR

9,10,11

tWEF

9,10,11

tPR

9,10,11

tWFF

9,10,11

tLZR

9,10,11

tWHF

9,10,11

tOVR

9,10,11

tRHF

9,10,11

tHZR

9,10,11

tRAE

9,10,11

twc

9,10,11

tRPE

9,10,11

tpw

9,10,11

tWAF

9,10,11

tHWZ

9,10,11

1wPF

9,10,11

tWR

9,10,11

tXOL

9,10,11

tso

9,10,11

tXOH

9,10,11

tHO

9,10,11

tMRSC

9,10,11

tpMR

9,10,11

tRMR

9,10,11

tRPW

9,10,11

twpw

9,10,11

tRTC

9,10,11

tpRT

9,10,11

tRTR

9,10,11

tEFL

9,10,11

tHFH

9,10,11

tFFH

9,10,11

Document #: 38-00079-C

5-59

CY7C510

CYPRESS
SEMICONDUCTOR

16

X

16 Multiplier
Accumulator

Features
• Two's complement or unsigned
magnitude operation

• Fast
- CY7C510·45 has a 45 os
(max.) clock cycle
(commercial)
- CY7C510·55 has a 55 os
(max.) clock cycle (military)

• ESD Protection
-

• Low Power
- Icc (max. at 10 MHz) =
100 mA (commercial)
- Icc (max. at 10 MHz) =
110 rnA (military)

Capable of withstanding
greater than 2000V static
discharge voltage

• Pin compatible and functionally
equivalent to Am29510 and
TMC2110

Functional Description

• Vee Margin
-5V ± 10%
- All parameters guaranteed
over commercial and military
operating temperature range

• 16 X 16 bit parallel
multiplication with accumulation
to 35·bit result

The CY7C51Ois a high-speed 16 X 16
parallel multiplier accumulator which
operates at 45 ns clocked multiply accumulate (MAC) time (22 MHz multiply accumulate rate). The operands
may be specified as either two's complement or unsigned magnitude l6-bit
numbers. The accumulator functions

include loading the accumulator with
the current product. adding or subtracting the accumulator contents and
the current product. or preloading the
accumulator from the external world.
All inputs (data and instructions) and
outputs are registered. These independently clocked registers are positive
edge triggered D-type flip-flops. The
35-bit accumulator/output register is
divided into a 3-bit extended product
(XTP). a l6-bit most significant product (MSP). and a 16-bit least significant product (LSP). The XTP and
MSP have dedicated ports for threestate output; the LSP is multiplexed
with the Y-input. The 35-bit accumulator/output register may be preloaded
through the bidirectional output ports.

Logic Block Diagram

CL"~S~
CLKY

>-----t-

TC
.ND

ACC

0057-1

Selection Guide
Maximum MultiplyAccumulate Time (ns)

Commercial

7C510·45

7C510·55

7C510·65

7C510·75

45

55

65

75

55

65

75

Military
5-60

~CYPRESS

CY7C510

~~~OO~~~==================================================~~~~
Maximum Ratings

Operating Range

(Above which the useful life may be impaired. For user
guidelines, not tested.)
Ambient Temperature Under Bias .... - 55°C to + 125°C

Range

Temperature

Vee

Commercial

OOCto +700C

5V ±JO%

- 55° to + 125°C

5V ±JO%

Military[l]

Supply Voltage to Ground Potential .... -0.5V to + 7.0V

Note:

DC Input Voltage ................... -0.5Vto +7.0V

1. TA is the "instant on" case temperature.

DC Voltage Applied to Outputs ..... -0.5V to Vee Max.
Output Current, into Outputs (low) .............. 10 rnA
Static Discharge Voltage ..................... > 200 I V
(per MIL-STD-883 Method 3015)

Pin Configurations
....

X7
Xs

on

x10
XII
X12

RNO
SUB
ACC
CLKX

X13

CLKY

X14

Vee
Vee
Vee
Vee

X15

Y2 ,P 2

OEl

Y3,P 3

RNO

Y4 ,P4

SUB

Y5,P 5

ACC

Y6 ,P 6
Y7 ,P 7

ClKX

Vee

Ys·Ps
Yg.Pg

TC

Y10·P 10
Y11 ,P l1

PREl
OE~

CLKP

Y13• P13

P34

Y14 ,P 14

P33

Y15 ,P 15

P32

P16

P31

P17

P30

PIS

P29

P 19

P2S

P20

P27

P21

P26

P22

P25

P23

P24

18
19
20
21
22
23
24

i

~6867666564636261
60
59
58
57
56
55
54
53
52
51
50

49
48
47
46

CLKP

I

~

~

P34

I

~

«

P2'Y2
P3'Y3
P4'Y4
ps·Ys
P6'Y6
P7'Y7
GND
GNO
Ps·Ys

Pg.Yg
Pl0'Yl0
P11 'Y11
P12'Y12
PI3'Y13
P14'Y14
P 15'Y15
P16

V~~~~~~M~~n~~~M~a

0057-3

OEX

Y12 ,P 12

14
15
16
17

TC
OEX
PREL
OEM

CLKY

GNO

9 8 7 6 5 4 3
10
11
12
13

XIS

Xg

Y1,P 1

~>=:

~N_C

-----~~~~~~~N_OO_

xxxxxxxxxxxxxxx~~

0057-2

5-61

II

(ij;~NDUCWR

CY7C510

Pin Configurations (Continued)
Pin Configuration for 68·Pin Grid Array

ee
e e 8 9 <3 e e e e e e
ee
ee
0 e
ee
G 0
ee
ee
0 0
ee
0 0
ee
G G
ee
e0
ee9 ee9 eeee e
<3 8 8 e 9 e e e e
eeeee

G 8
-42

-40

38

36

-41

39

37

35

3-4

5-4

32

33

57

56

30

31

59

58

2B

29

61

60

26

27

63

62

2-4

25

65

6-4

22

23

67

66

20

21

19

51

50

48

46

44

53

52

-49

-47

-45

-43

55

1

3

5

7

9

11

13

15

18

2

-4

6

8

10

12

1-4

16

17

0057-13

S·62

CY7C510

Signal
Name
XIS-O

YIS-O
(PIS-O)

I/O

Description

I

X-Input Data. This 16-bit number may be
interpreted as two's complement or
unsigned magnitude.

I/O

Y-Input Data/LSP Output Data. When
this port is used to input a Y value, the
16-bit number may be interpreted as two's
complement or unsigned magnitude. This
bidirectional port is multiplexed with the
LSP output (PIS-O), and can also be used
to preload the LSP register.

Signal
Name

I/O

Description

OEL

I

Output Enable Least. When LOW, the
LSP bidirectional port is enabled for
output. When HIGH, the output drivers
are disabled (high impedance) and the
MSP port may be used for preloading. See
Preload Function Table.

PREL

I

Preload. When HIGH, the three
bidirectional ports may be used to preload
data into the accumulator register at the
rising edge ofCLKP. The three-state
controls (OilX, OEM, OEL) must be
HIGH to preload data.
When LOW, the accumulated product is
loaded into the accumulator/output
register at the rising edge of CLKP. The
output drivers must be enabled (OEX,
OEM, OEL must be LOW) for the
accumulated product to be output.
Ordinarily, PREL, OEX, OEM, and OEL
are tied together. See accumulator
function table.

TC

I

Two's Complement Control. When
HIGH, the 7C51O is in two's complement
mode, where the input and output data
are interpreted as two's complement
numbers. The device is in unsigned
magnitude mode when TC is LOW. This
control is loaded into the instruction
register at the rising edge of CLKX +
CLKY.

P34-32

I/O

Extended Product (XTP) Output Data.
This port is bidirectional. The extended
product emerges through this port. The
XTP register may also be preloaded
through this port.

P31-16

I/O

MSP Output Data. This port is
bidirectional. The most significant
product emerges through this port. The
MSP register may also be preloaded
through this port.

PIS-O

I/O

LSP Output Data. This port is
bidirectional. The least significant
product emerges through this port. The
LSP register may also be preloaded
through this port.

CLKX

I

X-Register Clock. X-Input Data are
latched into the X-register at the rising
edge of CLKX.

CLKY

I

Y-Register Clock. Y-Input Data are
latched into the Y-register at the rising
edge ofCLKY.

RND

I

CLKP

I

Product Register Clock. XTP, MSP, and
LSP are latched into their respective
registers at the rising edge of CLKP. If
preload is selected, these registers are
loaded with the preload data at the output
pins via the bidirectional ports. If preload
is not selected, these registers are loaded
with the current accumulated product.

Round Control. When HIGH, rounding
is enabled and a "I" is added to the MSB
of the LSB (PIS). When LOW, the
product is unchanged. This control is
loaded into the instruction register at the
rising edge ofCLKX + CLKY.

ACC

I

Accumulate Control. When HIGH, the
accumulator/output register contents are
added to or subtracted from the current
product (XY) and this result is stored
back into the accumulator/output
register. When LOW, the product is
loaded into the accumulator register,
overwriting the current contents. This
control is loaded into the instruction
register at the rising edge of CLKX +
CLKY. See accumulator function table.

SUB

I

Subtract Control. When both ACC and
SUB are HIGH, the accumulator register
contents are subtracted from the current
product XY and this result is written back
into the accumulator register. When ACC
is HIGH and SUB is LOW, the
accumulator register contents and current
product are summed, then written back to
the accumulator register. This control is
loaded into the instruction register at the
rising edge of CLKX + CLKY. See
accumulator function table.

OEX

I

Output Enable Extended. When LOW,
the extended product bidirectional port is
enabled for output. When HIGH, the
outputs drivers are disabled (high
impedance) and the XTP port may be
used for preloading. See Preload Function
Table.

OEM

I

Output Enable Most. When LOW, the
MSP bidirectional port is enabled for
output. When HIGH, the output drivers
are disabled (high impedance) and the
MSP port may be used for preloading. See
Preload Function Table.

5-63

~
CY7C510
~~~aoR=============================================================
Functional Description

Preload Function Table

The CY7C510 is a high-speed 16 X 16-bit multiplier accumulator (MAC). It comprises a 16-bit parallel multiplier
followed by a 35-bit accumulator. All inputs (data and instructions) and outputs are registered. The 7C51O is divided into four sections: the input section, the 16 X 16 asynchronous multiplier array, the accumulator, and the output/preload section.
The input section has two 16-bit operand input registers for
the X and Y operands, clocked by the rising edge of CLKX
and CLKY, respectively. The four-bit instruction register
(TC, RND, ACC, SUB) is clocked by the rising edge of the
logical OR of CLKX, CLKY.
The 16 X 16 asynchronous multiplier array produces the
32-bit product of the input operands. Either two's complement or unsigned magnitude operation is selected, based on
control TC. If rounding is selected, (RND = 1), a "I" is
added to the MSB of the LSP (position PIS). The 32-bit
product is zero-filled or sign-extended as appropriate and
passed as a 35-bit number to the accumulator section.

PREL

<>EX

om

OEL

0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1

0
0
1

0
1
0
1
0
1
0
1
0

1

1
1
1
1
1
1

The accumulator function is controlled by ACC, SUB, and
PREL. Four functions may be selected: the accumulator
may be loaded with the current product; the product may
be added to the accumulator contents; the accumulator
contents may be subtracted from the current product; or
the accumulator may be preloaded from the bidirectional
ports.
The output/preload section contains the accumulator/output register and the bidirectiollal ports. This section is controlled by the signals PREL, OEX, OEM, and
When
PREL is HIGH, the output buffers are in high impedance
state. When the controls UEX, om, and OEL are also
high, data present at the output pins will be preloaded into
the appropriate accumulator register at the risin~ of
CLKP. When PREL is LOW, the signals OEX, OEM, and
OR are enable controls for their respective three-state
output ports.

1

0
0
1

1

1

0
0
0
0
1

0
0

XTP

MSP

LSP

Q
Q
Q
Q

Q
Q

Q

z

Z
Z
Z
Z
.Z
Z
Z

1

1

1
0
0
1

0
1
0
1
0

1

1

1

1

1

Output Register

PL
PL
PL
PL

z

z
z

Q

Q
Q

Q

z

z

z

Q

Z
Z
Z

Z
Z

PL

PL
PL

PL

Z
Z

PL

PL
PL

PL

Z
Z
Z

Z = Output buffers at High impedance (disabled.)

Q = Output buffers at Low impedance. Contents of output register
available through output ports.
PL = Output disabled. Preload data supplied to the output pins will be
loaded into the output register at the rising edge of CLKP.

Accumulator Function Table

om::.

5-64

PREL

ACC

SUB

P

OPERATION

L

L

X

H

L

L

H

H

Q
Q
Q

Load

L

Subtract

H

X

X

PL

Preload

Add

~
CY7C510
~~~d5kDUcroR======================================================================
CY7C510

Input Formats
Fractional Two's Complement Input
XIN

115 14 13 12 II

10

9

YIN

6

7

5

4

2

I

°

_20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-11 2-122-132-142-15
(Sign)

1

7 6
4
2
01
_20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-112-122-132-142-15
(Sign)

115

14 13

12

II

10

9

Integer Two's Complement Input
XIN

115

14 13

12 II

10

9

_215 214 213 212 211 210 29
(Sign)

8

YIN

7

6

2 8 27

4

2

2 6 2 5 24 2 3 22

21

7
01 115 14 13 12 II 10 9
_215214 213 212 211 210 29 2 8 27
20
(Sign)

6

5

4

2 6 2 5 24

3

2

2 3 22

01
21

20

Unsigned Fractional Input
XIN

YIN

4
2
7 6
01
2-12-22-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132-142-152-16

11-1_5_1_4_13_1_2_1_1_10_ _
9 _ _ _7_ _
6 _ _ _4_ _
3_2_ _1_ _
0-,1 115
2-12-22-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132-142-152-16

14 13

12

II

10

9

8

12

11

10

9

8

10

9

Unsigned Integer Input
XIN

YIN

11-1_5_1_4_13_1_2_1_1_10_ _
9 _ _ _7_ _
6 _ _ _4_ _
3_2_ _ _
0-,1115

14 13

7

6

4

2

01

7

6

4

2

°

CY7C510

Output Formats
Two's Complement Fractional Output
XTP

MSP

LSP

134333211313029 28 27 26 25 24 23 22 21 20
-2423 22

19

18

17

161115

21 202-12-22-32-42-52-62-72-82-92-10 2-11 2-122-132-14

14

13

12

11

1

2-152-162-172-182-192-202-21 2-222-232-242-252-262-272-282-292-30

(Sign)

Two's Complement Integer Output
XTP
134

MSP

33 321131

_234 233 232

LSP

30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115

231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216

14 13

12

11

10 9 8 7

6 5 4 3 2

I 0

I

215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20

(Sign)

Unsigned Fractional Output
XTP

MSP

LSP

134333211313029282726252423222120191817161115141312

1110

9

7

6

4

2

01

2221 20 2-12-22-32-42-52-62-72-82-92-102-112-122-132-14 2-15 2-16 2-172-182-192-202-212-222-232-242-252-262-272-28 2-29 2-30 2-31 2-32

Unsigned Integer Output
XTP

MSP

134 33 321 131
234 233 232

30 29 28 27 26 25 24 23 22 21

LSP
20 19 18 17 161115

231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216

5-65

14 13

12

11

10 9 8 7

6 5 4 3 2

I 0

215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20

I

~
CY7C510
•
~~~DUcroR======================================================================
Electrical Characteristics Over Operating Range[4]
Parameters

Test Conditions

Min.

= Min.,IOH = -0.4mA
= Min., 10L = 4.0 rnA

2.4

Description

VOH

Output HIGH Voltage

Vcc

VOL

Output LOW Voltage

VCC

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

10H

Output HIGH Current

10L

Output LOW Current

Vce

IIX

Input Leakage Current

GND,;;: VI';;: Vec

II

Input Current, Max. Input Voltage

Vce

lOS [1]

Output Short Circuit Current

10ZL

Output OFF (Hi-Z) Current

10ZH

Output OFF (Hi-Z) Current

Ice (QI)[2]

Supply Current (Quiescent)

Ice (Q2)[2]

Supply Current (Quiescent)

Ice (Max.)[2]

Max.

Units
V

0.4

V

2.0

V
V

0.8

I

Supply Current

Vce

= Min., VOH = 2.4V
= Min., VOL = 0.4V

-0.4
4.0

Commercial

Vce

I Military

~
~

rnA

-10

= Max., VIN = 7.0V
Vcc = Max., VOUT = 0.5V
Vcc = Max.,OE = 2.0V
V CC = Max., OE = 2.0V
Vce = Max.,
VIN = [GND to VIIJ or [VIH to veel
Commercial
Vce = Max

Vcc ~ VIN
O.4V ~ VIN

rnA

3.85V
GND

= Max., fCLK =

-3

+10

p.A

10

rnA

-30

rnA

-25

p.A

25

p.A
30

rnA

20

Military

rnA

25
100

10 MHz

rnA

110

Capacitance [3]
Parameters

Description

Max.

Test Conditions

CIN

Input Capacitance

CoUT

Output Capacitance

TA = 25°C, f
Vcc = 5.0V

Notes:
1. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
2. For Icc measurements, the outputs are three-stated. Two quiescent
figures are given for different input voltage ranges. To calculate ICC at
any given clock frequency, use 30 mA + Icc (A. c.), where Icc
(A.C.) = (7 mAlMHz) X Clock Frequency for the Commercial temperature range. Icc (A. C.) = (8 mAlMHz) X Clock Frequency for
Military temperature range.

=

I MHz

Units

8

pF

10

3. Tested initially and after any design or process changes that may
affect these parameters.
4. See the last page of this specification for Group A subgroup testing

information.

Output Loads Used for A.C. Performance Characteristics
Normal Load (Load 1)

n

Three·State Delay Load (Load 2)
R3

Rl

TO

1025.0.

5V
OUTPUT

F'I

40 P

OUTPUT~

PIN
817.0.

455.0.

o----JVIIv---O

..L

F'4

VX

0057-5

THEVENIN EQUIVALENT

OUTPUT

.~...L

5P

R2

0057-4

Equivalent to:

500.0.

2.22V
0057-6

5-66

~

CY7CSIO

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Switching Characteristics Over Operating Range(3)
Parameters

7C510-45

Description

Min.

Max.

7C510-65

7C510·55
Min.

Max.

Min.

Max.

7C510·75
Min.

tMA

Multiply Accumulate Time

t8

Setup Time

20

20

25

25

ns

tH

Hold Time

3

3

3

3

ns

tpw

Clock Pulse Width

25

25

30

30

tpDP

Output Clock to P

30

30

35

35

tPDY

Output Clock to Y

30

30

35

35

ns

OEX, OEM to P;
<{ts}:tHJXXX::v
TlIiIIHG______
IHPUT

------~~5V

0057-9

----------,---------ov

0067-8

Notes:
1. Diagram shown for HIGH data only. Output transition may be oppo-

3. See the last page of this specification for Group A subgroup testing
information.

site sense.
2. Cross hatched area is don't care condition.

5·67

CY7C510 Timing Diagram

CLKX
CL~

______________

~

~----------JMA----------~

CLKP

-----------------------------------------II~TPDP

OUT~~~ T'lXXX~"XX"X~X~X~XX-X"ft'X"ft'X"ft'Xft":Xft":XXX~"XX"X~X~X~XX-X"ft'X"ft'Xft":Xft":X-XX

TpDy

~~:::::::
0057-10

Preload Timing Diagram
1+----- TPW

---~

CLKP
PREL
OEX
OEM _ _ _ _-"I

OEL
OUTPUT~~~~~--------~~~~~~~~~~~~~~~~~~~~
PINS

~~~~'1\..

________..JI~~~~~~~~~~:lL:~:lL:~~~~~~
0057-11

Three-State Timing Diagram
3-STATE
CONTROL

VOH
1.SV
VOL

-tpHZ(DISABLE)
VOH-O.SV

(HIGH LEVEL)
3-STATE
OUTPUT

_ tpZH (ENABLE)

VOH
1.5V

(HIGH IMPEDANCE)
VOL +O.SV
(LOW LEVEL)

_ tpZL ENABLE

_ t pLZ (DISABLE) .

1.SV
VOL

0057-12

5-68

Typical AC and DC Characteristics
NORMALIZED SUPPLY CURRENT
1.2 vs.SUPPLYVOLTAGE

1l

1.0

Q

'
...0
...
...!:::!

.

TA = f50C
5.0

5.5

-55

....z
...0
...
...!:::!

~

/'

0

o

o

125

25

Q

TA = 250C

....

SUPPLY VOLTAGE (V)

V
o

2.5

lD

V
o

/

o

lD

/'

//

1l

...

1.2

.

lD

Q

'
25

'"

2.4

vs. OUTPUT VOLTAGE

20

::>

u

VCC =5.0V

-55

1.6

OUTPUT SINK CURRENT

vs. AMBIENT TEMPERATURE

0

5.5

4.0

0.8

OUTPUT VOLTAGE (V)

0.6

0.7
4.0

""'"

I'"

NORMALIZED FREQUENCY

vs. SUPPLY VOLTAGE

::Ii

z

...::>
......
::>

AMBIENT TEMPERATURE(OC)

1.1
1.0

15

VI

0.6 '--_ _ _J......::"--_ _ _..J

1.2

Q

.....
0

0.8 1------1----="""...."..-----1

NORMALIZED FREQUENCY

~
z

20

u
u

::>

SUPPLY VOLTAGE (V)

1.3

.

lD~------+_--------~

VCC =5.5V V1N =5.0V

4.5

l

Vee 5V
TA =25 OC--

25

:::>

0.4

4.0

]:...
...z.

1.2 1 - - - - - + - - - - - - - 1

OUTPUT SOURCE CURRENT
VS OUTPUT VOLTAGE

30

1000

o

5

10

20

FREQUENCY (14Hz)

CAPACITANCE (pF)

0057-14

5-69

~
CY7C510
~~~~=============================================================
Ordering Information
Speed (os)

Package Type

Operating Range

45

CY7C510-45 PC
CY7C51O-45 LC
CY7C510-451C
CY7C510-45 DC
CY7C51O-450C

P29
L81
181
D30
068

Commercial

55

CY7C510-55 PC
CY7C510-55 LC
CY7C510-551C
CY7C510-55 DC
CY7C510-550C

P29
L81
181
D30
068

Commercial

CY7C51O·55 LMB
CY7C510-55 DMB
CY7C51O·550MB

L81
030
068

Military

CY7C51O·65 PC
CY7C510-65 LC
CY7C51O·651C
CY7C510·65 DC
CY7C510-65 GC

P29
L81
181
D30
068

Commercial

CY7C510-65 LMB
CY7C510-65 DMB
CY7C510-650MB

LSI

Military

D30
068

CY7C510-75 PC
CY7C51O·75 LC
CY7C510-751C
CY7C510-75 DC
CY7C51O·750C

P29
L81
181
030
068

Commercial

CY7C510·75 LMB
CY7C51O·75 DMB
CY7C51O·750MB

L81
D30
068

Military

65

75

Ordering Code

5·70

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

Parameters

VOH

1,2,3

Icc (Ql)

1,2,3

VOL

1,2,3

ICC (Q2)

1,2,3

VIH

1,2,3

ICC (Max.)

1,2,3

VIL

1,2,3

IOH

1,2,3

IOL

1,2,3

IIX

1,2,3

II

1,2,3

los

1,2,3

IOZL

1,2,3

IOZH

1,2,3

Subgroups

Switching Characteristics
Parameters

Subgroups

tMA

7,8,9,10,11

ts

7,8,9,10,11

tH

7,8,9,10,11

tpw

7,8,9,10,11

tpDP

7,8,9,10,11

tpDY

7,8,9,10,11

tPHz

7,8,9,10,11

tPLZ

7,8,9,10,11

tpZH

7,8,9,10,11

tPZL

7,8,9,10,11

tHCL

7,8,9,10,11

Document #: 38-00014-B

5-71

CY7C516
CY7C517

CYPRESS
SEMICONDUCTOR

16

X

16 Multipliers

Features
• Fast
- 38 ns clock cycle
(commercial)
- 42 ns clock cycle (military)
• Low Power
- Icc (max. at 10 MHz) =
100 mA (commercial)
- ICC (max. at 10 MHz) =
110 mA (military)

• Vee Margin
-5V ±10%
-

All parameters guaranteed
over commercial and military
operating temperature range

• 16 x 16 bit parallel
multiplication with full precision
32-bit product output

as either two's complement or unsigned
magnitude numbers. Controls are provided for rounding and format adjustment of the full precision 32-bit product.
On the 7C516, individually clocked input and output registers are provided
to maximize throughput and to simplify bus interfacing. On the 7C517, a single clock (CLK) is provided, along
with three register enables. This facilitates the use of the 7C517 in microprogrammed systems. The input and output registers are positive edge triggered
D-type flip-flops. The output register
may be made transparent for asynchronous output.

• Two's complement, unsigned
magnitude, or mixed mode
multiplication
• CY7C516 pin compatible and
functionally equivalent to
Am29516, MPY016K,
MPY016H
• CY7C517 pin compatible and
functionally equivalent to
Am29517

Functional Description
The CY7C516/517 are high-speed 16 x
16 parallel multipliers which operate at
38 ns clocked multiply times (26 MHz
multiplication rate). The two input operands may be independently specified

Logic Block Diagrams
CY7C517

CY7C516
X-IN

Y-IN!LSP OUT

32

FA
IT
DW~.~.-

________~________-.~

0054-1

IIISP OUT/I..SP OUT

MSP OUT/LSP OUT

0054-12

Selection Guide
7C516-38
7C517-38
Maximum Multiply Time (ns)
ClockedlUnclocked

Commercial

7C516-42
7C517-42

38/58

Military

45/65
42/65

5-72

7C516-45
7C517-45

7C516-55
7C517-55

7C516-75
7C517-75

55/75

75/100

55/75

75/100

(;n

CY7C516
CY7C517

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~=
Functional Description (Continued)

Two output modes ma~ be selected by usinl! the output
multiplexer control, MSPSEL. Holding MSPSEt LOW
causes the most significant product (MSP) to be available
at the dedicated output port. The LSP is simultaneously
available at the bidirectional port shared with the Y-inputs.

The other mode of output involves toggling of the
MSPSEL control, allowing both the MSP and LSP to be
available for output through the dedicated 16-bit output
port.

Pin Configurations
X4

Xs

X3

X2

Xs
X7

X,

Xs

Xo
OEl

Xg

~

X,0

(ClK) ClKl

Xl1

(ENY) ClKY

X12

Yo,Po
Y P,
"

X,4

X13

Ys.Ps

TCX

Ys.p s

TCY

Y7,P7

vee
vee

P,S'P3,
P'4, P30
P 3, P29
' ,P
P ,2
28
P",P27
P ,0 • P2S
P9 'P2s
PS,P 24
P7 ,P 23

GNO
GNO

Ps. P21

Y2,P 2

x's

Y3, P3

ClKX (ENX)

Y4,P 4

RNO

Ys·Ps
Yg.Pg
Y, O·P , 0
Yl1 ,P l1

P S,P22

MSPSEl

Y12,P ,2

IT

Y13, P13
Y14,P ,4

FA
OEP

Y,S ,P , S

ClKM (ENP)

PO' P,S
P P17
"

II

:::I

o ::lIe;
zoo

P3, ·P,S
P3o,P '4

P2·P,S

P29,P13

P3 .P '9
P4·P20

P2B,P'2

PS,P21

P27' P "
P2S .P '0

PS,P22

P2S' Pg

P7 ,P23

P24' PS

P4,P20
P3,P'9
P2,P,S
P P '7
"
PO' P,S
NC

9 8 7 6 5 4 3 2 1 6867666564636261
10
60
11
59
12
58
13
57
56
14
15
55
16
54
17
53
18
52
7C516
19
51
(7C517)
20
50
21
49
48
22
23
47
24
46
45
25
26
44
2728293031323334353637383940414243

NC
X,2

X"
X,0
Xg
Xs
X7
Xs
Xs
X4
X3
X2

X,
Xo
OEl
ClK l (ClK)
ClK Y (ENY)

0054-3

0054-2

5-73

CY.7C~16

Wn~

CY7C517

SEMlCONoocroR

Pin Configurations (Continued)
Pin Configuration for 68·Pin Grid Array

8
53

eee8 ee8 e
e e @ e e e 8 0) @ G

G
51

50

52

49

48

46

44-

42

40

38

45

43

41

39

37

ENX

0 e
0 0
0 0
0 G

47

36

ENP

35

34

55

54

57

56

8 8
8 8

59

61

(0
63

e

32

33

30

31

58

8
28

29

60

26

27

24

e

25

22

23

20

21

18

19

0
62

67

G
®

G

1

65

@

e
ee
8 e

64

(CLK)

66

e
e
2

9 9 9 e 8
<3 e e 9 8 8

(3
3

5

7

9

11

13

4

6

8

10

12

14

e
e
15

16

8
8 8
8 e
G
17

0054-16

5·74

fin~~mNcroR ===================================================================
CY7C516
CY7C517

Maximum Ratings

Operating Range

(Above which the useful life may be impaired. For user
guidelines, not tested.)
Ambient Temperature Under Bias .... - 55°C to + 125°C
Supply Voltage to Ground Potential .... -O.SV to + 7.OV

Range

Temperature

Vee

Commercial
Military [I]

O"C to + 70"C

SV ±10%

- SsoC to + 12SoC

SV ±10%

Note:
1. TA is the "instant on" case temperature.

DC Input Voltage ................... -0.5V to +7.OV
DC Voltage Applied to Outputs ..... -0.5V to Vee Max.
Output Current, into Outputs (Jow) .............. 10 rnA
Static Discharge Voltage ..................... > lOOOV
(per MIL-STD-883 Method 3015)

Pin Definitions
Signal
Name I/O

Signal
Name

Description
X-Input Data. This 16-bit number may be
interpreted as two's complement or unsigned
magnitude.

X15-0

TCY

YI5-O I/O Y.lnput/LSPOutputData. This 16-bitnumber
may be interpreted as two's complement or
(P I 5-0)
unsigned magnitude. The V-input port may be
multiplexed with the LSP output (PI5-O).
P31-16
(PI5-0)

o

I/O

Description
Two's Complement Control Y. Y.Input data are
interpeted as two's complement when TCY is
HIGH. TCY LOW means the data are
interpreted as unsigned magnitude.
P31.161P1S-O Output Port Three-State Control.
When OEP is LOW, the output port is enabled;
when <:rnP is HIGH, the drivers are in a high
impedance state.

Output Data. This 16-bit port may carry either
the MSP (P31-16) or the LSP (PI5-0).

Y·in/P1S.0 Port Three State Control. When
OEL is LOW, the timeshared port is enabled
for LSP output. When OEL is HIGH, the
output drivers are in a high impedance state.
This is required for Y·input.

FT

The MSP and LSP registers are made
transparent (asynchronous operation) if FT is
HIGH.

FA

Format Adjust Control. If FA is HIGH, a full
32-bit product is output. If FA is LOW, a leftshifted product is output, with the sign bit
replicated in the LSP. FA must be HIGH for
two's complement integer, unsigned magnitude,
and mixed mode multiplication.

CY7CS16 Only
CLKX I X.Register Clock. X-input data and TCX are
latched in at the rising edge of CLKX.
CLKY

Y·Register Clock. V-input data and TCY are
latched in at the rising edge of CLKY.

Output Multiplexer Control. When MSPSEL is
LOW, the MSP is available for output at the
MSP output port, and the LSP is available at
the Y.input/LSP output port. When MSPSEL
is HIGH, the LSP is available at both ports
(above) and the MSP is not available.

CLKM

MSP Register Clock. The most significant
product (MSP) is latched in at the MSP
Register at the rising edge of CLKM.

CLKL

LSP Register Clock. The least significant
product (LSP) is latched in at the LSP Register
at the rising edge of CLKL.

MSPSEL

RND

TCX

I

Round Control. When RND is HIGH, a one is
added to the MSB of the LSP. This position is
dependent on the FA control; FA=HIGH
means RND adds to the 2- 15 bit (PI5),
FA = LOW means RND adds to the 2- 16 bit
(PI4).

CY7CS17 Only
CLK
I Clock. All enabled registers latch in their data
at the rising edge of CLK.
ENX

Two's Complement Control X. X-input data are
interpreted as two's complement when TCX is
HIGH. TCX LOW means the data are
interpreted as unsigned magnitude.

X·Register Enable. When ENX is LOW, the X·
Register is enabled. X-input data and TCX will
be latched in at the rising edge of CLK when
the register is enabled. When ENX is HIGH,
the X-Register is in hold mode.
X·Register Enable. ENY enables the
V-Register. (See ENX.)

ENP

5-75

Product Register Enable. ENP enables the
product register. Both the MSP and LSP
Sections are enabled by EN'P. (See ENX.)

II

5n~aoR=============================================================
CY7C516
CY7C517

.

Input Formats (All Devices)

Fractional Two'. Complement Input Format
TCX,TCY = 1
XIN

liS

I liS

14 13 12 11 10 9

YIN

I

8 7 6 5 4 3 2 1 0
_20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132-142-15

14 13 12 11 10 9

8 7 6 S 4 3 2 1 0
_202-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132-142-15

(Sign)

(Sign)

Integer Two's Complement Input Format
TCX,TCY = 1
XIN

115 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

I 115

_215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
(Sign)

YIN

14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

I

_215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
(Sign)

Unsigned Fractional Input Format
TCX,TCY = 0
XIN

I 115

115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-92-102-112-122-132-142-152-16

YIN

I

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2-1 2-2 2-3 2-42-5 2-6 2-7 2-8 2-92-102-112-122-132-142-152-16

Unsigned Integer Input Format
TCX,TCY = 0
XIN

115 14 13 12 11 10 9

8

7

YIN

6

5

4

3

2

1

0 I 1
...1_5_14_1_3_1_2_11_1o_ _
9 _8_7_6_ _
5_4_ _
3 _2_1_--,0I

5-76

5n
.

CY7C516
CY7C517

.

~OO~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Output Formats (All Devices)
Fractional Two's Complement (Shifted)· Format

FA =0
MSP

LSP

131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10
-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-112-122-132-142-15
(Sign)

9

8

7

6

5

4

3

2

0

I

-20 2-162-172-182-192-202-212-222-232-24 2-252-262-272-282-292-30
(Sign)

Fractional Two's Complement Output

FA= I
MSP

LSP

131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10
_21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-132-14

9

8

7

6

5

4

3

2

0

I

2-152-162-172-182-192-20 2-212-222-232-242-252-262-272-282-292-30

(Sign)

Integer Two's Complement Output

FA = 1
MSP

LSP

131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10
_231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216
(Sign)

9

8

7

6

5

4

3

2

0

I

215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20

Unsigned Fractional Output

FA = 1
LSP

MSP
131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-122-132-142-152-16

9

8

7

6

5

4

3

2

0

I

2-172-182-192-20 2-212-222-232-242-252-262-272-282-292-302-31 2-32

Unsigned Integer Output

FA = 1
MSP

LSP

131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161 115 14 13 12 11 10

9

8

7

6

5

4

3

2

0

231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
"In this fonnat an overflow occurs in the attempted multiplication of the two's complement number 1.000 ... (- 1) with itself, yielding a product of 1.000
... 0r-1.

5-77

I

I!II

a

&n
.

CY7CS16
CY7C517

~~===================

Electrical Characteristics Over Operating Range[4]
Parameters

Description

Min.

Test Conditions

VOH

Output HIGH Voltage

V CC= Min., IoH = -0.4 mA

VOL

Output LOW Voltage

Vee = Min., IOL=4.0mA

VIH

Input HIGH Voltage

VIL

Input LOWVoltage

IoH

Output HIGH Current

Vee = Min., VOH=2.4V

IoL

Output LOW Current

Vee= Min., VOL = 0.4V

IIX

Input Leakage Current

VSS

IosU]

Output Short Circuit Current

Vcc=Max., VOUT = OV

IOZL

Output OFF (Hi-Z) Current

Vee = Max., OO=2.0V

IOZH

Output OFF (Hi-Z) Current

Vee = Max., OO=2.0V

V
0.4

V
V

Military (-42)

:s: VIN :s: Vee, Vee

mA

-0.4

mA

4.0
= Max.

-10

10

""A

-3

-30

mA

-25

""A

25

""A

GND :s: VIN :s: VIL or
VIH:S: VIN:S: VCC;
OI! = HIGH

40

45

All Others
GND
3.85V

Military
Commercial

Supply Current

mA

30

Commercial

Supply Current
(Quiescent)

ICC (Max.)121

V

0.8

Supply Current
(Quiescent)

Icc (Q2)[21

Units

2.0

Commercial (-38)
lee (Q,)[21

Max.

2.4

:s: VIN :s: 0.4Vor
:s: VIN :s: VCC; OI! =

20
HIGH

Vcc=Max.,fcLK= 10 MHz;
OE= HIGH

Military

mA

25
100

mA

110

Capacitance [3]
Parameters

Description

CIN

Input Capacitance

CoUT

Output Capacitance

Test Conditions

Max.

TA = 25°C, f= 1 MHz
VCC = 5.0V

8

Notes:
1. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
2. Two quiescent figures are given for different input voltage ranges. To
calculate Icc at any given clock frequency, use 30 mA + Icc (A. C.),
where Icc (A. C.) = (7 mAlMHz) X Clock Frequency for the Commercial temperature range. Icc (A. C.) = (8 mA/MHz) X Clock
Frequency for the Military temperature range.

Units
pF

10

3. Tested initally and after any design or process changes that may affect
these parameters.
4. See the last page of this specification for Group A subgroup testing
information.

Output Loads Used for A.C. Performance Characteristics
Normal Load (Load 1)

Three-State Delay Load (Load 2)

Rl
1025A

TO

OUT:u~n

F'r

4O P

500A

OUTPUT~

PIN

F'4..L

_~ 1..

5P

R2

8174

VX

0054-5
0054-4

Equivalent to:

THEVENIN EQUIVALENT

455A
OUTPUT

~

2.22V
0054-6

5-78

5n
.. .

CY7CS16
CY7CS17
~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~=============

Switching Characteristics Over Operating Range[2]
7CSl6-38 7CSl6-42 7CS16·4S 7CS16·SS 7CSl6-7S
Test
7CS17·38 7CS17-42 7CS17·4S 7CS17·SS 7CS17·7S Unib
Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Description

Parameters
MUC

Undocked Multiply Time

58

65

65

75

100

MC

Clocked Multiply Time

38

42

45

55

75

S

Xi. Yj, RND, TCX, TCY Set·up Time

7

H

Xi, Yi, RND, TCX, TCY Hold Time

3

3

3

SE

ENX,"ENY, ENP Set·up Time (7C517 Only)

10

15

20

HE

ENX,"ENY, ENP Hold Time (7C517 Only)

3

3

3

10

10

20

Load 1

pWH,tpwL Clock Pulse Width (HIGH and LOW)

8

20

ns
ns

25

ns

3

3

ns

20

25

ns

3

3

ns

25

30

20

ns

PDSEL

MSPSEL to Product Out

18

21

25

25

30

ns

PDP

Output Clock to P

25

30

30

30

35

ns

PDY

Output Clock to Y

25

30

30

30

35

ns

15

17

25

25

30

ns

PHZ

OEP Disable Time

HIGHtoZ

PLZ

LOWtoZ

15

17

25

25

30

ns

PZH

ZtoHIGH

23

25

30

30

35

ns

PZL

ZtoLOW

23

25

30

30

35

ns

PHZ

HIGHtoZ

15

17

25

25

30

ns

om> Enable Time
OEL Disable Time

Load 2

PLZ

LOWtoZ

15

17

25

25

30

ns

PZH

ZtoHIGH

23

25

30

30

35

ns

ZtoLOW

23

25

30

30

35

ns

om:: Enable Time

PZL
HCL

Clock Low Hold Time CLKXY
Relative to CLKMLllI

0

Load 1

0

0

0

0

ns

Note.:
2. See the last page of this specification for Group A subgroup testing
information.

1. To ensure that the correct product is entered in the output registers,
new data may not be entered into the input registers before the output
registers have been clocked.

Test Waveforms (All Devices)
1[ST

Vx

ALL tpo's

Vee

VOH~
V
1.5V

o.ov

VOH~

tPHZ

tPLZ

2.6V

tPZH

om

\PZL

2.6V

OUTPUT WAVEFORM - totEASUREtotENT LEVEL

OL

O.OV

~2.6V
VOL

.SV

~VOH
1.5V
O.OV

2.6V~
1.5V

V

OL

0054-7

Pulse Width (All Devices)

Setup and Hold Time (All Devices)

1~~~~tS}:tH~!:V
-----.v::v

TIMING

INPUT-----

Notes:

0054-9
0054-8

2. Cross hatched area is don't care condition.

1. Diagram shown for HIGH data only. Output transition may be oppo·
site sense.

5·79

&n
.

CY7C516
CY7C517

• CYPRESS

~~R========================~~~

Three-State Timing Diagram
VOM
1.sV

(DI~iLEi

~IpzH:::"
(ENABLE)

VOH-O.5V

(HIGH LEVEL)

VOl.

VOH
1.5V

(HIGH IMPEDANCE)
VOL +O.5V

(LOW LEVEL)

~~~~
E)

I-::-\P~:::"

(DISABLE) .

1.5V
VOl.

0054-10

Timing Diagram
7CS16
cu
0

4.5

/

20

0.6 ' - - - - - - " - - - - - - - '
SUPPLY VOLTAGE(V}

2.4

30

!.
...

TA =2SOC

0.7

I'"

1.6

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

Vcc= 5.0V
0.8 1 - - - - - + - - - - - - - - 1

4.0

0.8

VI.

1.2 1-----"""""'-+--------1

0.8

'"""

3S

z

2

z

~

5

0

~

II<

0

TA =2SOC--

OUTPUT VOLTAGE (V)

1.41-------+--------1

V

vcc l5V

AMBIENT TEMPERATURE(OC)

1.2

0.9

10

0

1~

NORMAUZED FREQUENCY
VB. AMBIENT TEMPERATURE
1.6 r - - - - - - , - - - - - - - ,

~
00(

15

'":::>0

I!:
:::>

NORNUUXZEDFREQUENCY
SUPPLY VOLTAGE

1.0

...
...:::>

1.3

Q

20

0

VB.

...
...

II<
II<

:::>

l'O~-----+_--------~

SUPPLY VOLTAGE (V)

1.1

~

...

0.61----J....,;:::.....---~

is
:::>
S
II<

!.
...
z

0.4

~

~

VIN =5.0V
TA =~5OC
4.5

30

(1\

/'
4.0

OUTPUT SOURCE CURRENT
VI. OUTPUT VOLTAGE

VB.

v

1.2

o

/

/

/

V~

1.0
Vcc= 5.0V
TA=j5OC-

400

~/

1.2

600

800

/

0.8
0.6

200

/

1.4

./

1000

CAPACITANCE (pr)

o

~

Vcc= 5.5V
TA =25OC-

vror
5

10

20

FREQUENCY (MHz)
0054-17

5-81

(;n
.

CY7CS16
CY7CS17

. .~~;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;=;===;===

Ordering Information
Speed
(os)

38

42

45

Package
Type

Operating
Range

Speed

CY7C516-38PC
CY7C517-38PC

P29

Commercial

55

CY7C516-38LC
CY7C517-38LC

Ordering
Code

Package
Type·

Operating
Range

CY7C516-55PC
CY7C517-55PC

P29

Commercial

L81

CY7C516-55LC
CY7C517-55LC

L81

CY7C516-38JC
CY7C517-38JC

J81

CY7C516-55JC
CY7C517-55JC

J81

CY7C516-38DC
CY7C517-38DC

D30

CY7C516-55DC
CY7C517-55DC

D30

CY7C516-38GC
CY7C517-38GC

G68

CY7C516-55GC
CY7C517-55GC

068

CY7C516-42LMB
CY7C517-42LMB

L81

CY7C516-55LMB
CY7C517-55LMB

L81

CY7C516-42DMB
CY7C517-42DMB

D30

CY7C516-55DMB
CY7C517-55DMB

030

CY7C516-42GMB
CY7C517-42GMB

G68

CY7C516-55GMB
CY7C517-55GMB

G68

CY7C516-45PC
CY7C517-45PC

P29

CY7C516-75PC
CY7C517-75PC

P29

CY7C516-45LC
CY7C517-45LC

L81

CY7C516-75LC
CY7C517-75LC

L81

CY7C516-45JC
CY7C517-45JC

J81

CY7C516-75JC
CY7C517-75JC

J81

CY7C516-45DC
CY7C517-45DC

D30

CY7C516-75DC
CY7C517-75DC

D30

CY7C516-45GC
CY7C517-45GC

G68

CY7C516-75GC
CY7C517-75GC

G68

CY7C516-75LMB
CY7C517-75LMB

LSl

CY7C516-75DMB
CY7C517-75DMB

D30

CY7C516-75GMB
CY7C517-75GMB

G68

(os)

Military

75

Commercial

5-82

Ordering
Code

Military

Commercial

Military

fin~~UCKR================================================================
.

CY7CS16
CY7C517

.

MILITARY SPECIFICATIONS

Group A Subgroup Testing
DC Characteristics
Parameters

Subgroups

Parameters

Subgroups

VOH

1,2,3

Icc (Q2)

1,2,3

VOL

1,2,3

Icc (Max.)

1,2,3

VIH

1,2,3

VIL

1,2,3

10H

1,2,3

10L

1,2,3

IIX

1,2,3

los

1,2,3

IOZL

1,2,3

IOZH

1,2,3

Icc (Ql)

1,2,3

Switching Characteristics
Parameters

Subgroups

tMUC

7,8,9,10,11

!Mc

7,8,9,10,11

ts

7,8,9,10,11

tH

7,8,9,10,11

tSE

7,8,9,10,11

tHE

7,8,9,10,11

tpwH,tpwL

7,8,9,10,11

tpDsEL

7,8,9,10,11

tpDP

7,8,9,10,11

tpDY

7,8,9,10,11

tpHZ

7,8,9,10,11

tpLZ

7,8,9,10,11

tPZH

7,8,9,10,11

tPZL

7,8,9,10,11

tpHZ

7,8,9,10,11

tpLZ

7,8,9,10,11

tpZH

7,8,9,10,11

tpZL

7,8,9,10,11

iHCL

7,8,9,10,11

Document #: 38-00018-C

5-83

CY7C901

CYPRESS
SEMICONDUCTOR

CMOS Four-Bit Slice

Features
• Pin Compatible and Functional
Equivalent to Am2901B, C

• Fast
CY7C901-23 has a 23 DB
Read Modify-Write Cycle;
Commercial 25% Faster
than "C" Spec 2901
CY7C901-27 has a 27 ns
Read Modify-Write Cycle;
Military 15% Faster
than "C" Spec 2901

Functional Description
The CY7C901 is a high-speed, expandable, 4-bit wide ALU that can be used
to implement the arithmetic section of
a CPU, peripheral controller, or programmable controller. The instruction
set of the CY7C901 is basic but yet so
versatile that it can emulate the ALU
of almost any digital computer.
The CY7C901, as illustrated in the
block diagram, consists of a 16-word
by 4-bit dual-port RAM register file, a
4-bit ALU and the required data manipulation and control logic.
The operation performed is determined
by nine input control lines (10 to Is)

• Low Power
70 mA (commercial)
90 mA (military)
• Vee 5V ±10%
Commercial and military
• Eight Function ALU
• Infinitely expandable in 4-bit
increments
• Four Status Flags:
Carry, overflow, negative, zero

that are usually inputs from a microinstruction register.
The CY7C901 is expandable in 4-bit
increments, has three-state data outputs as well as flag output, and can use
either a full look ahead carry or a ripple carry.
The CY7C901 is a pin compatible,
functional equivalent, improved performance replacement for the Am2901.
The CY7C901 is fabricated using an
advanced 1.2 micron CMOS process
that eliminates latchup, results in ESD
protection over 2000V and achieves superior performance with low power
dissipation.

• Capable of withstanding
greater than 2000V static
discharge voltage

Logic Block Diagram

Pin Configuration
Top View
CLOCK

-~==n===-.,

'A' (READ)

ADDRESS

'e'

IREADIWRITE)

ADDRESS

CARRY IN

0030-2

OUTPUT
ENABLE

DATA OUT

5-84

0030-1

~
CY7C901
~~~R================================================================
Selection Guide See last page for ordering information.
Read Modify·Write Cycle (Min.) in os
23
27
31
32

Operating Icc (Max.) in mA
80
90
70
90

Operating Range
Commercial
Military
Commercial
Military

Part Number
CY7C901·23
CY7C901·27
CY7C901·31
CY7C901·32

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ..................... > 2001 V
(Per MIL·SID·883 Method 3015)

Storage Temperature ............... - 65°C to + 150"C
Ambient Temperature with
Power Applied .................... - 55°C to + 125°C

Latchup Current (Outputs) .................. > 200 rnA

Supply Voltage to Ground Potential
(Pin 10 to Pin 30) .................... -0.5V to + 7.0V

Operating Range
Ambient
Temperature

DC Voltage Applied to Outputs
in High Z State ...................... -0.5V to +7.0V

Range

DC Input Voltage ................... - 3.0V to + 7.0V

Commercial

O"Cto +70"C

5V

Output Current into Outputs (Low) ............. 30 rnA

Militarylil

- 55°C to + 125°C

5V

Vee

±
±

10%
10%

Note:
1. TA is the "instant onn case temperature.

Pin Definitions
Signal
Name I/O

Signal
Name I/O

Description

These 4 address lines select one of the registers in
the stack and output its contents on the (internal)
Aport.
80- B3
These 4 address lines select one of the registers in
the stack and output is contents on the (internal)
B port. This can also be the destination address
when data is written back into the register file.
10-18
These 9 instruction lines select the ALU data
sources (10, I, 2), the operation to be performed
(13, 4, 5) and what data is to be written into either
the Q register or the register file (16, 7, 8).
Do-D3
These are 4 data input lines that may be selected
by the 10, I, 2 lines as inputs to the ALU.
Y0- Y 3 0 These are three·state data output lines that, when
enabled, output either the output of the ALU or
the data in the A latches, as determined by the
code on the 16, 7, 8 lines.
OE
Output Enable. This is an active LOW input that
controls the Y0- Y 3 outputs. When this signal is
LOW the Y outputs are enabled and when it is
HIGH they are in the high impedance state.
CP
Clock Input. The LOW level of the clock write
data to the 16 x 4 RAM. The HIGH level of the
clock writes data from the RAM to the A·port
and B·port latches. The operation of the Q
register is similar. Data is entered into the master
latch on the LOW level of the clock and
transferred from master to slave when the clock is
HIGH.
I/O These two lines are bidirectional and are
controlled by the 16, 7, 8 inputs. !Electrically they
are three-state output drivers connected to the
TTL compatible CMOS inputs.
Ao-A3

I

Description

Q3
I/O Outputs: When the destination code on lines
16, 7, 8 indicates a shift left (UP) operation the
RAM3
(Cont.)
three·state outputs are enabled and the MSB of
the Q register is output on the Q3 pin and the
MSB of the ALU output (F3) is output on the
RAM 3 pin.
Inputs: When the destination code indicates a
shift right (DOWN) the pins are the data inputs
to the MSB of the Q register and the MSB of the
RAM.
Qo
I/O These two lines are bidirectional and function in a
RAMo
manner similar to the Q3 and RAM3 lines, except
that they are the LSB of the Q register and RAM.
Co
I The carry.in to the internal ALU.
C n +4 0 The carry·out from the internal ALU.
G, P 0 The carry generate and the carry propagate
outputs of the ALU, which may be used to
perform a carry look-ahead operation over the 4bits of the ALU.
OVR
0 Overflow. This signal is logically the exclusiveOR ofthe carry-in and the carry-out of the MSB
of the ALU. This pin indicates that the result of
the ALU operation has exceeded the capacity of
the machine. It is valid only for the sign bit and
assumes two's complement coding for negative
numbers.
F = 0 0 Open drain output that goes HIGH if the data on
the ALU outputs (Fo, I, 2, 3) are all LOW. It
indicates that the result of an ALU operation is
zero (positive logic).
F3
0 The most significant bit of the ALU output.

5-85

RAMO~

,

.-----I>--.--+<:RAM,

A WORD

B WORD

ADWf
t,

1!~E~L-======0=0=====~~==1
SJ
u,

CLOCK

Co

'"

DATA
DIRECT
INPUTS

0,

0,

OEN 1IIIIIIIIIDE~~~l;~ON

Q REGISTER

00

CP

lA

~

Q;

0,

0,

0,

I.
17
I.

{g';==~::j=t===t==;~tl
2

01

DO>--~+-+-r---'
ALU

10

SOURCE
OPERAND
DECODE

.,
12

G
ARITHMETIC LOGIC UNIT (ALUI

Fo

F,

P

Cn +

F2

~F'OIO/CI

F3

"

oe>--i>
Yo

Y,

Y,

4

OVR

NOTE; lSB IS NUMBERED "0"; MSB IS NUMBERED "3"
X BIDIRECTIONAL
~, 

"- -........

120

~

100

..,

80

""l!!:

60

~

«I

'"::>II

I!:
::>
-55

SUPPLY VOLTAGE(V)

25

'"

1.5

Q

::>

I!::
::>
0

1.4

/

1.3

Q

'"~

1.2

:::E
II<
0

1.1

00(

z

1.0

o

I

/

V

/

--

V

3.0

4.0

/

1.0

Jl
S

V

0.9

V

0.8

/

z

Vee = 5.0V
TA = 25°C

0.7

I
800

2.0

NORMALIZED Icc

~

600

1.0

OUTPUT VOLTAGE (V)

VI. FREQUENCY

:::E
II<
0

400

Vee =5.0V
TA =25OC-

1.1

/

200

1/

If

AMBIENT TEMPERATURE(OC)

1.6

~

J

;I'"

/

o
o

125

NORMALIZED OUTPUT DELAY
vs. OUTPUT LOADING

~

./

20

0

6.0

,.. ~

III

0.6
4.0

'" '"

1.0

AMBIENT TEMPERATURE (OC)

NORMALIZED FREQUENCY
SUPPLY VOLTAGE

Vcc =5.0V
TA =25OC-

""

30
20

VS.

r

I

1.2~------+_---------1

SUPPLY VOLTAGE(V)

1.0

60

50

0.4
4.0

OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE

AMBIENT TEMPERATURE

1.4.-----..,..-------,

1000

CAPACITANCE (pf)

o
o

/
5

10 15

Vee =5.5V
TA =25OC ' - V1N=OV OR 3V

I
I I
20 25 30 35

fREQUENCY (MHz)
0030-10

5-95

~
CY7C901
~~~~U~R==~============================================================
Ordering Information
Read
ModifyWrite
Cycle (os)
23

27
31

32

Pin Configuration

,
Top View

Package
Type

Operating
Range

CY7C901-23PC
CY7C901-23DC
CY7C901-23JC
CY7C901-23LC

P17
018
J67
L67

Commercial
Commercial
Commercial
Commercial

CY7C901-27DMB
CY7C901-27LMB

Dl8
L67

Military
Military

CY7C901-31PC
CY7C901-3IDC
CY7C901-3IJC
CY7C901-31LC

P17
Dl8
J67
L67

Commercial
Commercial
Commercial
Commercial

CY7C90l-32DMB
CY7C901-32LMB

018
L67

Military
Military

Ordering Code

!i:!

~.f <" .r.('I:::~~>~
HC

IS
17
RA~3
RA~o

Vee
F=O

10
11
12

CP
NC

P
9
10
11
12
13
14
15
16

37
36
35
34
33
32
31
30
17
29
1819202122232425262728

G mOm mN,;' d' Qt')~ 0' 8~

5-96

OVR

Cn +4

G
F3

GND
Cn
14
Is
13

0030-9

~

CY7C901

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

Combinational Propagation Delays

(Continued)

Parameters

Subgroups

VOH

1,2,3

From Co to Co+4

7,8,9,10,11

VOL

1,2,3

From Co to F = 0

7,8,9,10,11

VIH

1,2,3

From C n to OVR

7,8,9,10,11

VILMax.

1,2,3

From Cn to RAMo, 3

7,8,9,10,11

Parameters

Subgroups

IIX

1,2,3

From 1012 to Y

7,8,9,10,11

Ioz

1,2,3

From 1012 to F3

7,8,9,10,11

Isc

1,2,3

From 1012 to Cn + 4

7,8,9,10,11

ICC

1,2,3

From 1012 to G, P

7,8,9,10,11

Icci

1,2,3

From 1012 to F=O

7,8,9,10,11

Cycle Time and Clock Characteristics

From 1012 to OVR

7,8,9,10,11

From 1012 to RAMo, 3

7,8,9,10,11
7,8,9,10,11

Parameters

Subgroups

From 1345 to Y

Minimum Clock LOW Time

7,8,9,10,11

From 1345 to F3

7,8,9,10,11

Minimum Clock HIGH Time

7,8,9,10,11

From 1345 to C n +4

7,8,9,10,11

From 1345 to G, P

7,8,9,10,11

From 1345 to F = 0

7,8,9,10,11

From 1345 to OVR

7,8,9,10,11

Combinational Propagation Delays
Parameters
From A, B Address to Y
From A, B Address to F3

Subgroups
7,8,9,10,11
7,8,9,10,11

From A, B Address to C n + 4

7,8,9,10,11

From A, B Address to G, P

7,8,9,10,11

From 1J45 to RAMo, 3

7,8,9,10,11

From 1678 to Y

7,8,9,10,11

From 1678 to RAMo, 3

7,8,9,10,11

From 1678 to Qo, 3

7,8,9,10,11

From A, B Address to F = 0

7,8,9,10,11

From A, B Address to OVR

7,8,9,10,11

From A Bypass ALU to Y
(I = 2XX)

7,8,9,10,11
7,8,9,10,11

From A, B Address to RAMo, 3

7,8,9,10,11

From Clock ~ to Y

FromDtoY

7,8,9,10,11

From Clock ~ to F3

7,8,9,10,11

FromDtoF3

7,8,9,10,11

From Clock ~ to Co +4

7,8,9,10,11

FromDtoCn +4

7,8,9,10,11

From Clock ~ to G, P

7,8,9,10,11

FromDtoG, P

7,8,9,10,11

From Clock ~ to F = 0

7,8,9,10,11

FromDtoF = 0

7,8,9,10,11

From Clock ~ to OVR

7,8,9,10,11

FromDtoOVR

7,8,9,10,11

From Clock ~ to RAMo, 3

7,8,9,10,11

From D to RAMo, 3

7,8,9,10,11

From Clock ~ to Qo, 3

7,8,9,10,11

FromCotoY

7,8,9,10,11

From C n to F3

7,8,9,10,11

5-97

~

CY7C901

~~~~~=;~~=;~~~~==~==~==~~~~====~============~==
Set-up and Hold Times Relative to Clock (CP) Input
Parameters
A, B Source Address
Set-up Time Before H A, B Source Address
Hold Time After H A, B Source Address
Set-up Time Before L A, B Source Address
Hold Time After L B Destination Address
Set-up Time Before H B Destination Address
Hold Time After H B Destination Address
Set-up Time Before L B Destination Address
Hold Time After L -

Subgroups

Parameters

7,8,9,10,1 i

D Hold Time After L -

7,8,9,10,11

en Set-up Time Before L en Hold Time After L -

L
L

H

7,8,9,1Q,l1

1012 Hold Time After L -

H

1345 Hold Time After L 7,8,9,10,11
L
7,8,9,10,11

L
H
7,8,9,10,11
H
7,8,9,10,11

Document #: 38-00021-B

5-98

7,8,9,10,11
7,8,9,10,11

H
H

7,8,9,10,11
7,8,9,10,11

H

1678 Set-up Time Before H L
1678 Hold Time After H _ L

7,8,9,10,11

1678 Set-up Time Before L -

7,8,9,10,11

1678 Hold Time After L - H
RAMo, RAM3, Qo, Q3
Set-up Time Before L - H
RAMo, RAM3, Qo, Q3
lIold Time After L - H

7,8,9,10,11

7,8,9,10,11
7,8,9,10,11

H

1345 Set-up Time Before L -

7,8,9,10,11

H

H
H

1012 Set-up Time Before L -

H

D Set-up Time Before L -

Subgroups
7,8,9,10,11

H

7,8,9,10,11
7,8,9,10,11
7,8,9,10,11
7,8,9,10,11

CY7C909
CY7C911

CYPRESS
SEMICONDUCTOR

. CMOS Micro Program
Sequencers

Features

• Pin compatible and functional
equivalent to 2909A12911A

• Low Power
- lee (max.) = 55 mA;
commercial and military

Description
The CY7C909 and CY7C911 are highspeed, four-bit wide address sequencers
intended for controlling the sequence
of execution of microinstructions contained in microprogram memory. They
may be connected in parallel to expand
the address width in 4 bit increments.
Both devices are implemented in high
performance CMOS for optimum
speed and power.

• Vee margin
- 5 V ± 10%
-

I) a set offour external direct inputs
(Di); 2) external data stored in an internal register (Ri); 3) a four word deep
push/pop stack; or 4) a program counter register (which usually contains the
last address plus one). The push/pop
stack includes control lines so that it
can efficiently execute nested subroutine linkages. Each of the four outputs
(Yj) can be OR'ed with an external input for conditional skip or branch instructions. A ZERO input line forces
the outputs to all zeros. The outputs
are three state, controlled by the
Output Enable (OE) input.

• Capable of withstanding greater
than 2000V static discharge
voltage

• Fast
- CY7C909/11 has a 30 ns
(min.) clock to output cycle
time; commercial and military

All parameters guaranteed
over commercial and military
operating temperature range

• Expandable
Infinitely expandable in 4-bit
increments

The CY7C911 is an identical circuit to
the CY7C909, except the four OR inputs are removed and the D and R inputs are tied together. The CY7C911 is
available in a 20-pin, 300-mil package.

The CY7C909 can select an address
from any of four sources. They are:

Pin Configurations

Logic Block Diagram
R(7C909 ONLY)

PUSH/POP
F'ILE

r------I
REGISTER

ENI\BLE

Vee

ENABL.E

CP

FE

pUP

I
I

;tE,

:

DANDR

Iv

I
DIRECT
I
INPUTS
I
D)-_-;'::"""
So ) - - - . .

D3

Cn

en

D2
Dt

OE

Do
GND

Y2
Yt

ZERO

Yo

So

S1

Yo
S,

hI~npLEXER

1["0;.----'
OR2

en...

Y.
Y2
Y,

.....~I-.-_____ CLOCK

" ) - - -.. Xo

I

Cn• 4

O£

ON 7C911

FE

RE

FE

14DNlY I

CONNECTED

pUP

CP
Vee

Y3

So

0042-3

ZERO

x,

0042-2

)-......,r--h

lOR,
I ORo>--r-.....,
IL ______
7C909 ONLY .JI

o

"-

or rJJ:N rJJ:"'It! >ufi it
R0

5

4 3 2111282726
u
25

I~ >!:l!3 h~
FE

OR 3

24

Cn+ 4

03
OR2
02
OR l

23
22
21
20

Cn

8
9
10

7C909

Or
Y3
Y2

~ 1~213t415t6171~9 ~

III

20 19 'I
18
5
17
7C911
16
15
8
14
9 101112 t3
3 2

D3
D2
Dl
DO
GND

4

Cn + 4

Cn

OE
Y3
Y2

10...

0 - 0 ct:ClJCIJ>->-

OUTPUT
ENABLE

N

iii'

c.

0042-4

en • 4

0042-1

5-99

0042-5

•

CY7C909
....
r~~DUCTOR =======================;;;;C;;;;Y;;;;';;;;7C9==11
~

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C
Ambient Temperature ~ith
Power Applied ..............•..... - 55°C to + 125°C
Supply Voltage to Ground Potential .... -0.5V to + 7.0V

Static Discharge Voltage ..................... >2OO1V
(per MIL-STD-883 Method 3015)
Latch-Up Current ......................... > 200 mA

Operating Range

DC Voltage Applied to Outputs
in HighZ State ...................... -0.5Vto +7.0V

Ambient
Temperature
O"Cto +70"C
- 55°C to + 125°C

Range

DC Input Voltage ................... - 3.0V to + 7.0V
Output Current, into Outputs (Low) ............. 30 mA

Commercial
Military!3]

Vee
SV ±10%
SV ±10%

Electrical Characteristics Over Operating Range(4)
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

VOL
VIH
VIL
IIX

Icc

' Output LOW Voltage
Input High Voltage
Input Low Voltage
Input Load Current
Output Leakage
Current
Output ShortU]
Circuit Current
Vee Operating
Supply Current

Icc!

Vee Operating
Supply Current

Ioz
los

Vee
Vee
Vee

= Min., IOH = - 2.6 rnA (Corom.)
= Min.,IoH = -1.0 rnA (Mil.)
= Min.,IOL = 16.0rnA

= GND

Vee

VOUT

VIH

Commercial
Military
Commercial
Military

~

3.0V, VIL

~

0.4V

Max.

2.0
-2.0
-10

Vee
0.8
+10

Units
V
V
V
V
V
p.A

-20

+20

p.A

-30

-85

rnA

55
55
35
35

mA

0.4

GND ~ VI ~ Vee
GND ~ Vo ~Vee
Output Disabled

= Max.
Vee = Max.
lOUT = OrnA
Vee = Max.

Min.
2.4
2.4

mA

Capacitance [2]
Description
Input Capacitance
Output Capacitance

Parameters
CIN
COUT

Test Conditions
TA = 25°C, f = 1 MHz
Vee = 5.0V

Units

Max.
5

pF

7

Notes:
1. Not more than ! output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Tested initially and after any design or process changes that may
affect these parameters.

n

AC Test Loads and Waveforms
Rl

SV
OUTPUT

SOpf

INCLUDING
JIG AND
SCOPE

I

n

3. TA is the "instant on" ,case temperature.
4. See the last page of this specification for Group A subgroup testing
information.

OUTPUT
R2

_

Spf

I

INCLUDING
JIG AND SCOPE

3.0V
GND

I
I

Commercial

Military

R!

2540

2580

R2

1870

2160

Figure 2

-

5-100

~

10%
-

~ Sns
0042-7

_

Figure lb

10%

~Sns

R2

0042-6

Figure la

:::tE%

ALL INPUT PULSES

Rl

SV

Switching Characteristics Over Operating Range[4. 51
7C909-30
7C911-30

7C909-30
7C911-30

7C909-40
7C911-40

Commercial

Military

Commercial

7C909-40
7C911-40
Military

Minimum Clock Low Time

IS

15

20

20

ns

Minimum Clock High Time

15

15

20

20

ns

Units

MAXIMUM COMBINATIONAL PROPAGATION DELAYS
From Input To:

17

CN+4
18

18

CN+4
19

17

CN+4
22

20

CN+4
25

ns

Di

Y

SO. SI

18

18

20

20

29

34

29

34

ns

ORi(7C909)

16

16

17

17

17

22

20

25

ns

CN

-

13

-

15

-

14

-

16

ns

18

18

20

20

29

34

30

35

ns

OE Low to Output
OE HIGH to HIGH Z[5]

16

18

-

25

-

25

25

-

ns

18

-

25

16

-

Clock HIGH. S\, So

= LH
= LL
Clock HIGH. S\, So = HL

20

20

22

22

39

44

45

50

ns

Clock HIGH. SI. So

20

20

22

22

39

44

45

50

ns

20

20

22

22

44

49

53

58

ns

zmm

Y

Y

Y

MINIMUM SET-UP AND HOLD TIMES (All Times Relative to Clock LOW to HIGH Transition)
From Input
Set-up
Set-up
Set-up
Set-up
Hold
Hold
Hold
RE
11
0
12
0
19
0
19
Ri [6]
10
0
11
0
10
0
12
PushIPop
12
0
13
0
25
0
27
FE
12
0
13
0
25
0
27
10
0
11
18
0
18
0
CN
14
0
16
0
25
0
25
Di
14
25
ORi(7C909)
12
0
0
25
0
14
0
16
25
0
29
0
So.SI
ZERO
12
0
13
0
25
0
29

ns

ns

Hold
0

ns

0

ns

0

ns

0

ns

0

ns

0

ns

0

ns

0

ns

0

ns

Notes:
5. Output Loading as in Figure lb.
6. Rj and Dj are interna1ly connected on the CY7C911. Use Rj set-up
and hold times when Dj inputs are used to load register.

7. System clock cycle time (Clock Low Time and Clock High Time)
cannot be less than maximum propagation delay.

Switching Waveforms

-MIN CLOCK LOW
CLOCK

(EXCEP~~)

.I"~>k:
TIMES-

{XXXXXXXXX\.r
TO OUTPUi
i----CLOCK TO~INPUT
OUTPUT-----i
(Y. ~~T:~)XXXXXXXXXXXXXXXX
::::::::::::::::::::

~

0042-8

5-101

II

5A~===================
CY7C909
CY7C911

. ...

Functional Description
The tables below derme the control logic of the 7C909/911.
Table 1 contains the Multiplexer Control Logic which selects the address source to appear on the outputs.

Table 3 illustrates the Output Control Logic of the
7C909/911. The ZERO control forces the outputs to zero.
The OR inputs are OR'ed with the output of the multiplexer.
Table 3. Output Control

Table 1. Address Source Selection
OCI'AL
0
1
2
3

Sl
L
L
H
H

SOURCE FOR Y OUTPUTS
Microprogram Counter (jJ.PC)
Address/Holding Register (AR)
Push-Pop stack (STK)
Direct inputs (Dj)

So
L
H
L
H

ORI
X
X
H
L

Control of the Push/Pop Stack is contained in Table 2.
FILE ENABLE (FE) enables stack operations, while
Push/Pop (PUP) controls the stack.

PUP

L

L

PUSH·POP STACK CHANGE
No change
Push current PC into stack
increment stack pointer
pop stack, decrement stack pointer

X

H

OE
H
L
L
L

Yj

HighZ
L
H
Source selected by So SI

Table 4 defines the effect of So, SI, PE and PUP control
signals on the 7C909. It illustrates the Address Source on
the outputs and the contents of the Internal Registers for
every combination of these signals. The Internal Register
contents are illustrated before and after the Clock LOW to
HIGH edge.

Table 2. Synchronous Stack Control
FE
H
L

ZERO
X
L
H
H

Table 4
CYCLE Sl. So. FE. PUP
N
N+l
N
N + 1
N
N + 1
N
N + 1
N
N + 1
N
N + 1
N
N + 1
N
N + 1
N
N+l
N
N+l
N
N+l
N
N + 1

0000

-

0001

-

001 X

-

0100

0101
-

011 X

-

1000

-

1001

-

101 X

-

1100

-

1 10 1

-

111 X

-

jJ.PC
J
J + 1
J
J + 1
J
J + 1
J
K + 1
J
K + 1
J
K + 1
J
Ra + 1
J
Ra + 1
J
Ra + 1
J
D + 1
J
D+l
J
D + 1

REG STKO STKI STK2 STD YOUT
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K

Ra
Rb
Ra
J
Ra
Ra
Ra
Rb
Ra
J
Ra
Ra
Ra
Rb
Ra
J
Ra
Ra
Ra
Rb
Ra
J
Ra
Ra

Rb
Rc
Rb
Ra
Rb
Rb
Rb
Rc
Rb
Ra
Rb
Rb
Rb
Rc
Rb
Ra
Rb
Rb
Rb
Rc
Rb
Ra
Rb
Rb

Rc
Rd
Rc
Rb
Rc
Rc
Rc
Rd
Rc
Rb
Rc
Rc
Rc
Rd
Rc
Rb
Rc
Rc
Rc
Rd
Rc
Rb
Rc
Rc

J = Contents of Microprogram Counter
K = Contents of Address Register
Ra. Rh. Re. R

;-

.9

g

I

r;e~

~

o

Q

if
~

I I H=PUSH
r------------~r=============~============~IL--

..

0.

o

J:J

'2

"

~

PUP>----1-C>o----~----------_,

'3

FE~ENA8l.EST~,,=

~

j

TWO""

UP/DOWN COUNTER
CP

"'l(l

Co

00

-. S

~
...

..,

0

.,

Do

....

.. 8-

•ClIO
::s

ii£

a::n..... CLOO<
-...::

n

... n

.g~

't'

~

1-

>-bo

S'>-[>O--r--

CPr-.....

I I

1~ I I

1'"--' I

1~ I I

..

READ/WRfT[

LOGIC

~

'.

So

~

f

WO j-WI

i Wz i

W3

..

'/0 I
I
I
·--r--,--,--

0,

I
I
I __
.Vo
__ L._...l.-_..I

I/o I

I

I

.--~~~-I/o

~

I

ttl

~

f

~:::
DE

I

I

I
Y.

'. I
,

Y,

' I
I

Y2

I
i

M
Y.

c;,

~

.!.

aa

gg
~o

~

\C)

&n
.

CY7C909
CY7C911

~~R================================================================

Functional Description (Continued)

loaded with the same Y output (Y - > ,...PC) on the next
clock cycle.

Architecture
The CY7C909 and CY7C911 are CMOS microprogram sequencers for use in high speed processor applications. They
are cascadable in 4-bit increments. Two devices can address 256 words of microprogram, three can address up to
4K words, and so on. The architecture of the
CY7C909/911 is illustrated in the logic diagram in Figure
5. The various blocks are described below.

Stack
The Stack consists of a 4 x 4 memory array and a built-in
Stack Pointer (SP) which always points to the last word
written. The Stack is used to store return addresses when
executing microsubroutines.
The Stack Pointer is an up/down counter controlled by
Flle Enable (FE) and PushlPop (PUP) inputs. The Flle
Enable input allows stack operations only when it is LOW.
The Push!Pop input controls the stack pointer position.

Multiplexer
The Multiplexer is controlled by the So and S( inputs to
select the address source. It selects either the Direct Inputs
(OJ), the Address Register (AR), the Microprogram Counter (,...PC), or the stack (SP) as the source of the next microinstruction address.

The PUSH operation is initiated at the beginning of a microsubroutine. Push/Pop is set HIGH while File Enable is
kept LOW. The stack pointer is incremented and the memory array is written with the microinstruction address following the subroutine jump that initiated the push.

Direct Inputs
The Direct Inputs (OJ) allow addresses from an external
source to be output on the Y outputs. On the CY7C911,
the direct inputs are also the inputs to the Address Register.

The POP operation is initiated at the end of a microsubroutine to obtain the return address. Both Push/Pop and
File Enable are set LOW. The return address is already
available to the multiplexer. The stack pointer is decremented on the next LOW to HIGH clock transition, effectively removing old information from the top of the stack.
The stack is configured so that data will roll-over if more
than four POPs are performed, thus preventing data from
being lost.

Address Register
The Address Register (AR) consists offour D-lpe, edgetriggired.J"!!p-flops which are controlled by the egtster
Enab e (RE) input. When Register Enable is LOW, new
data is entered into the register on the LOW to HIGH
clock transition.

The contents of the memory position pointed to by the
Stack Pointer is always available to the multiplexer. Stack
reference operations can thus be performed without a push
or a pop. Since the stack is four words deep, up to four
microsubroutines can be nested.

Microprogram Counter
The Microprogram Counter (,...PC) is composed of a 4-bit
incrementer followed by a 4-bit register. The incrementer
has a Carry-in (CN) input and a Carry-out (CN + 4) output
to facilitate cascading. The Carry-in input controls the microprogram counter. When Carry-in is HIGH the incrementer counts sequentially. The counter register is loaded
with the current Y output plus one (Y + I - > ,...PC) on
the next clock cycle. When Carry-in is LOW the incrementer does not count. The microprogram counter register is

The ZERO input resets the four Y outputs to a binary zero
state. The OR inputs (7C909 only) are connected to the Y
outputs such that any output can be set to a logical one.
The Output Enable (OR) input controls the Y outputs. A
HIGH on OUtput Enable sets the outputs into a high impedance state.

Definition of Terms
Name
INPUTS
S[, So
FE
PUP

1m
ZERO

em
ORj

en
Ri
Dj
CP

Description
Multiplexer Control Lines, for Access Source Selection
File Enable, Enables Stack Operation, Active LOW
Push/Pop, Selects Stack Operation
R:egister Enable, Enables Address Register Active LOW
Forces Output to Logical Zero
Output Enable, Controls Three-State Outputs Active LOW
Logic OR Input to each Address Output Line (7C909 only)
Carry-In, Controls Microprogram Counter
Inputs to the Internal Address Register
Direct Inputs to the Multiplexer
Clock Input

5-105

•

CY7C909
.,r~~ ====================;::C;::Y;::7;::C9=11
~

Definition of 'ferms (Continued)
~ame

Description

OUTPUTS

Yj

Address Outputs

CN+4

Carry-Out from Incrementer

INTERNAL SIGNALS

,...pc

Contents of the Microprogram Counter

AR

Contents of the Address Register

STKOSTK3

Contents of the PushIPop Stack

SP

Contents of the Stack Pointer

EXTERNAL SIGNALS
A

Address to the Counter Memory

I(A)

Instruction in Control Memory at Address A

,...WR

Contents of the Microword Register at the
Output of the Control Memory

TN

Time Period (Cycle) n

5-106

Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE

NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

u

1.0

/

~

0

W

.

N

::;

0.8

:IE

a:
0

z
0.6

L

V

/'

0.4
4.0

II

...!:IE

1.2

o

..

::;

1.0 100::::-----\-------1

:IE

:>

a:

~

VIN
TA
5.0

~

6.0

25

-55

w
:>

z

zw

::;

:IE
a:
0

z

a

a

125

53
a:

...

~ r--

W
N
TA~2"C

..
::;

_

z

0.7
4.0

1.4
1.2
1.0

5.0

5.5

6.0

-55

25

1.5

V

1.4

V

0
0

w

~

:IE
II:
0

1.3
1.2

z

1.1
1.0

4.0

:>
Go

40

0

20

...
...
:>

60

J

L

.....-

---

Vee' 5.0 V
TA = 25'C

/

o

125

~

V

1.0

0.0

2.0

3.0

4.0

OUTPUT VOLTAGE IVI

NORMALIZED Icc
vs. FREQUENCY
1.1

1.6

S

..z

/

AMBIENT TEMPERATURE I'CI

NORMALIZED OUTPUT DELAY
vs. OUTPUT LOADING

w

100

BO

iii

= s.ov

0.8

5UPPL V VOLTAGE IVI

>-

a:
a:
:>
u

~
Vee

0.6
4.5

~

~

3.0

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

!
...z
w

a:
0

2.0

140

:IE

I

0.8

1.0

~

;( 120

0

.",.

0.9

""

OUTPUT VOLTAGE IVI

NORMALIZED FREQUENCY
AMBIENT TEMPERATURE

a 1.1

..

10

0

VI.

>
u

N

20

1.6

>
u 1.2

1.0

~

30

AMBIENT TEMPERATURE rCI

NORMALIZED FREQUENCY
vs. SUPPLY VOLTAGE

w

Vee = I.oV
TA ~ 25'C

40

Go

In

0.6'-_ _ _ _..L.._ _ _ _ _- '

5.5

50

0

...
...:>:>

r----t-....;:....o;:::---i

0.8

s.av

i ZS'C

1.3

0
w

w
a:
a:
:>
u
w
u
a:

w

N

SUPPLY VOLTAGE IVI

...a:

60

;(

/'

4.5

OUTPUT SOURCE CURRENT
vs OUTPUT VOLTAGE

1.4,-----y-------,

1.2

a

I

/

/

---

1.0

..,-V

u

~

fil

0.9

V~

N

::;

Vee = s.ov
TA =25'C

I

1

~
~

a:

-

0.8

/

0.7

200

400

600

800

0 0

1000

CAPACITANCE IpFI

6

Vee = UV
V", = a,IV
TA = arc

V
10

16

20

25

L

r--

30

36

FREQUENCV IMHzl
0042-12

5-107

(;A
..

cr7~~

CY7C911

~aoR===============================================================

Ordering Information
Oock
Cycle

Ordering Code

(os)

Package
Type

Operating
Range

Oock
Cycle

Ordering Code

(os)

Package
Type

Operating
Range

PS

30
40

CY7C909-30PC
CY7C909-40PC

PIS
PIS

Commercial
Commercial

30
40

CY7C911-30PC
CY7C911-40PC

P5

Commercial
Commercial

30
40

CY7C909-30JC
CY7C909-4OJC

J64
J64

Commercial
Commercial

30
40

CY7C911-3OJC
CY7C911-4OJC

J61
J61

Commercial
Commercial

30
40

CY7C909-300C
CY7C909-400C

016
016

Commercial
Commercial

30
40

CY7C911-300C
CY7C911-40DC

06
06

Commercial
Commercial

40

CY7C909-4OLC

L64

Commercial

40

CY7C911-4OLC

L61

Commercial

30
40

CY7C909-300MB
CY7C909-400MB

016
016

Military
Military

30
40

CY7C911-300MB
CY7C911-400MB

06
06

Military
Military

40

CY7C909-40LMB

L64

Military

40

CY7C911-40LMB

L61

Military

5-108

fin

CY7C909
CY7C911
~®U~R~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
MILITARY SPECIFICATIONS
Group A Subgroup Testing
.

DC Characteristics
Parameters

Subgroups

VOH

1,2,3

VOL

1,2,3

Vrn

1,2,3

VILMax.

1,2,3

IIX

1,2,3

IOZ

1,2,3

los

1,2,3

Icc

1,2,3

IcCI

1,2,3

Switching Characteristics
Parameters

Subgroups

Minimum Clock Low Time 7,8,9,10,11
Minimum Clock High Time 7,8,9,10,11

Parameters

Subgroups

MINIMUM SET-UP AND
HOLD TIMES

MAXIMUM COMBINATIONAL
PROPAGATION DELAYS

RE Set-up Time

7,8,9,1O,ll

RE Hold Time

7,8,9,10,11

DjtoY

7,8,9,10,11

Push/Pop Set-up Time

7,8,9,10,11
7,8,9,1O,ll

DjtoCN+4

7,8,9,10,11

PushlPop Hold Time

So, SI toY

7,8,9,10,11

FE Set-up Time

7,8,9,10,11

So,SltoCN+4

7,8,9,10,11

FE Hold Time

7,8,9,1O,ll

ORj (7C909) to Y

7,8,9,10,11

CN Set-up Time

7,8,9,10,11

ORj (7C909) to CN +4

7,8,9,10,11

CN Hold Time

7,8,9,IO,ll

CNto CN+4

7,8,9,10,11

Dj Set-up Time

7,8,9,10,11

ZEROtoCN+4

7,8,9,10,11

Dj Hold Time

7,8,9, 10, II

ORj (7C909) Set-up Time

7,8,9,10,11

ORj (7C909) Hold Time

7,8,9,1O,ll

So, SI Set-up Time

7,8,9,10,11

So, SI Hold Time

7,8,9,10,11

ZERO Set-up Time
ZERO Hold Time

7,8,9,IO,ll

Clock High, So, SI
toY

= LH

7,8,9,10,11

Clock High, So, SI
toCN+4

= LH

7,8,9,10,11

Clock High, So, SI
toY

= LL

7,8,9,10,11

Clock High, So, SI
to CN+4

= LL

7,8,9,10,11

Clock High, So, SI
toY

= HL

7,8,9,10,11

Clock High, So, SI
toCN+4

= HL

7,8,9,10,11

Document #: 38-OOO15-B

5-109

7,8,9,10,11

CY7C910

CYPRESS
SEMICONDUCTOR

CMOS Microprogram
Controller

Features
for subroutine return address or
data storage
• ESD protection
Capable of withstanding over
2000V static discharge voltage
• Pin compatible and functional
equivalent to AM2910A

• Fast
- CY7C910-40 has a 40 ns
(min.) clock cycle;
commercial
- CY7C910-46 has a 46 ns
(min.) clock cycle; military
• Low power
- ICC (max.) = 70 rnA

plexer and the required data manipulation and control logic.
The operation performed is determined
by four input instruction lines (10-13)
that in turn select the (internal) source
of the next micro-instruction to be
fetched. This address is output on the
YO-Yll P@mJ;wo additional inputs
(CC and C
are provided that are
examined during certain instructions
and enable the user to make the execution of the instruction either unconditional or dependent upon an external
test.
The CY7C91O is a pin compatible,
functional equivalent, improved performance replacement for the
AM29 lOA.
The CY7C91O is fabricated using an
advanced 1.2 micron CMOS process
that eliminates latchup, results in ESD
protection of over 2000 volts and
achieves superior performance and low
power dissipation.

Functional Description

• Vee margin SV ±10%
commercial and military
• Sixteen powerful
microinstructions
• Three output enable controls
for three-way branch
• Twelve-bit address word
• Four sources for addresses:
microprogram counter (MPC),
stack, branch address bus,
internal holding register
• 12-bit internal loop counter
• Internal 17-word by 12-bit stack
The internal stack can be used

The CY7C910 is a stand-alone microprogram controller that selects, stores,
retrieves, manipulates and tests addresses that control the sequence of execution of instructions stored in an external memory. All addresses are 12-bit
binary values that designate an absolute memory location.
The CY7C910, as illustrated in the
block diagram, consists of a 17-word
by 12-bit LIFO (Last-In-First-Out)
stack and SP (Stack Pointer), a 12-bit
RC (Register/Counter), a 12-bit MPC
(Microprogram Counter) and incrementer, a 12-bit wide by 4-input multi-

Logic Block Diagram

Pin Configurations

() Ig

I/')

It)

........

,.,

..,

~

N-

%>0)000)-0)-0)000

iiUi

Pi:
WAP

'3

'2
Vee
"

'0

CCEN

cc

RLD
NC

6 5 4 3 2 ~4443424140
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
1819202122232425262728

Y,
Do
Yo
NC
C,
CP
GND
NC

DE

y.

D.

D.

y.

Ys

O2
Y2

Os
VEeT

0,

Pc

Y,

"AP

Do

'.

Yo

e,
ep

'2

Vee

GND

"
'0
ceEN

Or

Y"

cc

0"

Yll

RLo

Y,o

0 11

FULL

0 '0

o.

Y.

Y.

D.

'7

Y.

Y7

D.

0041-8

~DATAP"TH

0041-2

-CONTROLLINES

Top View

0041-1

Selection Guide
Clock Cycle

(Min.lin ns
40
46
50
51
93
99

Stack
Depth
17 words
17 words
17 words
17 words
17 words
17 words

5-110

Operating Range

Part Number

Commercial
Military
Commercial
Military
Commercial
Military

CY7C91040
CY7C91O-46
CY7C91O-50
CY7C910-51
CY7C910-93
CY7C910-99

~
CY7C910
~~~~~~~~========================================================
Pin Definitions
Signal
Name

I/O

Description

Signal
Name

00-011

I

Direct inputs to the RC (Register/
Counter) and multiplexer. DO is LSB
and 011 is MSB.

RIJ)

I

Register load. Control input to RC that,
when LOW, loads data on the ~O-Oil
pins into RC on the LOW to HIGH
clock (CP) transition.

10-13

I

CC

I

Control input that, when
signifies that a test has passed.

CCEN

I

Enable for CC input. When HIGH CC
is ignored and a pass is forced. When
LOW the state of CC is examined.

CP

I

Clock input. All internal states are
changed on the LOW to HIGH clock
transitions.

LOW,

5-111

Description

I

Carry input to the LSB
incrementer for the MPC.

I

Control for YO-YII outputs. LOW to
enable; High to disable.

YO-Y11

a

Address output to microprogram
memory. YO is LSB and YII is MSB.

FULL

a
a

When LOW indicates the stack is full.

PL

MAP

a

When LOW selects the Mapping
PROM (or PLA) as the direct input
source.

a

When LOW selects the Interrupt
Vector as the direct input source.

CI

Instruction inputs that select one of
sixteen instructions to be performed by
the CY7C910.

I/O

of the

When LOW selects the pipeline register
as the direct input (00-011) source.

II

~

CY7C910

..,~~;:================================
Architecture of the CY7C910
This permits reference to the data on the top of the stack
without having to perform a POP operation.

Introduction
The CY7C91O is a high performance CMOS microprogram
controller that produces a sequence of 12-bit addresses that
control the execution of a microprogram. The addresses
are selected from one of four sources, depending upon the
(internal) instruction being executed (10-13), and other external inputs. The sources are (I) the (external) DO-DII
inputs, (2) the RC, (3) the stack and (4) the MPC. Twelve
bit lines from each of these four sources are the inputs to a
multiplexer, as shown in Figure 1, whose outputs are applied to the inputs of the YO-YII three-state output drivers.

The SP operates as an up/down couilter that is incremented when a PUSH operation (instructions 1,4 or 5) is performed or decremented when a POP operation (instructions 8, 10, II, 13 or IS) is performed. The PUSH operation writes the return address on the stack and the POP
operation effectively removes it. The actual operation occurs on the LOW to HIGH clock transition following the
instruction.
The stack is initialized by executing instruction zero
(JUMP TO LOCATION 0 or RESET). Every time a
"jump to subroutine" instruction (1,5) or a loop instruction (4) is executed, the return address is PUSHed onto the
stack; and every time a "return from subroutine (or loop)"
instruction is executed, the return address is POPed off the
stack.
When one subroutine calls another or a loop occurs within
a loop (or a combination), which is called nesting, the Logical depth of the stack increases. The physical stack depth
is 17 words. When this depth occurs, the F'iJLL signal goes
LOW on the next LOW to HIGH clock transition. Any
further PUSH operations on a full stack will cause the data
at that location to be over-written, but will not increment
the SP. Similarily, performing a POP operation on a empty
stack will not decrement the SP and may result in nonmeaningful data being available at the Y outputs.

External Inputs: DO-Dl1
The external inputs are used as the source for destination
addresses for the jump or branch type of instructions.
These are shown as Ds in the two columns in the Table of
Instructions. A second use of these inputs is to load the
RC.
Register Counter: RC
The RC is implemented as 12 D-type, edge-triggered llipflops that are synchronously clocked on the LOW to
HIGH transition of the clock, CPo The data on the D inputs is synchronously loaded into the RC when the load
control input, RLD, is LOW. The output of the RC is
available to the multiplexer as its R input and is output on
the Y outputs during certain instructions, as shown by R in
the Table of Instructions.
The RC is operated as a 12-bit down counter and its contents decremented and tested if zero during instructions 8,
9 and IS. This enables micro-instructions to be repeated up
to 4096 times. The RC is arranged such that if it is loaded
with a number, N, the sequence will be executed exactly
N+ I times.

The Microprocessor Counter: MPC
The MPC consists of a 12-bit incrementer followed by a
12-bit register. The register usually holds the address of the
instruction being fetched. When sequential instructions are
fetched, the carry input (CI) to the incrementer is HIGH
and one is added to the Y outputs of the multiplexer, which
is loaded into the MPC on the next LOW to HIGH clock
transition. When the CI input is LOW, the Y outputs of
the multiplexer are loaded directly into the MPC, so that
the same instruction is fetched and executed.

The Stack and Stack Pointer: SP
The 17-word by 12-bit stack is used to provide return addresses from micro-subroutines or from loops. Intergal to it
is a SP, which points to (addresses) the last word written.

5-112

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............... -65°C to + 150"C
Static Discharge Voltage ..................... >2001V
Ambient T~perature with
°
°
(per MIL-STD-883 Method 3015)
Power Applied .................... - 5S C to + 12S C
Operating Range
Supply Voltage to Ground Potential
(Pin 10 to Pin 30) .................... -0.5V to + 7.0V
Ambient
Range
Vee
DC Voltage Applied to Outputs
Temperature
in High Z State ...................... -O.SV to + 7.0V
Commercial
O'Cto +70'C
5V ±1O%
DC Input Voltage ................... -3.0Vto +7.0V
Military(3)
- SSOC to + 12S0C
5V ±1O%
Output Current into Outputs (Low) ............. 30 mA

Electrical Characteristics Over Commercial and Military Operating Range, Vcc Min.
Parameter

Description

Vee = Min.
IOH = -1.6mA
Vee = Min.
IOL = 12mA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH
VIL

Input HIGH Voltage

IiH

Input HIGH Current

IlL

Input LOW Current

IoH

Output HIGH Current

IOL

Output LOW Current

Ioz

Output Leakage Current

Ise

Output Short Circuit Current

lee

Supply Current

lee!

Supply Current

= 4.SV, Vcc Max. = 5.SV[4]

Min.

Test Condition

Max.

V

2.4

2.0
-3.0

Input LOW Voltage
Vee = Max.
VIN = Vee
Vee = Max.
VIN = Vss
Vee = Min.
VIH = 2.4V

= Min.
= OAV
Vee = Max.
VOUT = VssJVee
Vee = Max.
VOUT = OV

Military
Commercial

Military

Vee

V

Vee
0.8

V
V

10

/LA

-10

/LA
rnA

12

rnA

+40

/LA
/LA

-85

rnA

70
90

rnA

35
SO

rnA

-40

= Max.

ViH :'"
...

30

'"::>0

20

~------+-----------j

-~

SUPPLY VOLTAGE (V)

~

1.2
1.1

0

1.0

~
«

0.9

'"0z

0.8

...z
...
...'"
...

(I)

....
::>

10

I!:
::>
0

o
o

1~

NORMALIZED FREQUENCY

NORMALIZED FREQUENCY
vs. AMBIENT TEMPERATURE

~

...::>z
8
...'"

~

...!::!
...J

OUTPUT SINK CURRENT
OUTPUT VOLTAGE

1.2 i'..

-..........

1.0

'"0z

0.7

0.8

120

...z

100

--

'"'"::>

eo

'"z

60

....
::>

40

5.0

....
::>

20

V
o

I!:
::>
0

...!::!

NORMALIZED OUTPUT DELAY

NORMALIZED Icc

vs. FREQUENCY

1.5
1.4

/

1.3

0

...J

1.2

:2
0

1.1

«

'"z

1.0

/

o

1.0

/
I'

...

0.9

:2

0.8

0

~
«

'"0z

0.7

I
400

600

BOO

//

Jl

Vcc =5.0V
TA = 250C

200

4.0

/

1.0

V

I

3.0

1.1

---

r

2.0

OUTPUT VOLTAGE (V)

vs. OUTPUT LOADING

0

....
::>

o

1~

AMBIENT TEMPERATURE (OC)

1.6

...~

~

-~

SUPPLY VOLTAGE(V)

...--

Vcc= 5.0V
TA =25OC-

J

/

Il.

0

6.0

5.5

/

"",

/

iii

0.6
4.5

.....

0

Vcc =5.0V

:2

e-

.5....

1.4

«

:2

3.0

140

0

TA =25OC

2.0

~

VI.

1.6

4.0

1.0

'"

OUTPUT VOLTAGE (V)

vs. SUPPLY VOLTAGE

V

" "'"

AMBIENT TEMPERATURE (OC)

1.3

::>
0

40

0

0.6 '--_ _ _...J-.::.:.._ _ _- '

6.0

5.5

I
Vcc= 5.0V
TA =25OC-

50

...

0.8 I - - - - t - - =.......;:----j

VIN =5.0V
TA = ~5OC
4.5

60

e.5....z
0

0.4
4.0

OUTPUT SOURCE CURRENT
VI. OUTPUT VOLTAGE

1000

CAPACITANCE (pr)

o
o

/
/
5

/

10

Vcc =5.5V
TA =25OC __
VIN =OVor3V

15

20

I

I

~

30

35

FREQUENCY (MHz)
0041-10

5-118

~
CY7C910
~~~aoR============================;;===============================
Ordering Information
Clock
Cycle

Package
Type

Operating
Range

CY7C91O-40PC

P17

Commercial

CY7C910-4ODC

D18

Ordering Code

(ns)

40

46

50

51

93

99

CY7C910-4OJC

J67

CY7C910-4OLC

L67

CY7C91O-46DMB

D18

CY7C910-46LMB

L67

CY7C910-50PC

P17

CY7C910-50DC

DI8

CY7C910-5OJC

J67

CY7C91O-50LC

L67

CY7C91O-5IDMB

D18

CY7C910-51LMB

L67

CY7C910-93PC

P17

CY7C910-93DC

DI8

CY7C910-93JC

J67

CY7C910-93LC

L67

CY7C910-99DMB

DI8

CY7C910-99LMB

L67

Military

Commercial

II
Military

Commercial

Military

5-119

MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

Minimum Set-up and Hold Times

Parameters

Subgroups

VOH

1,2,3

DI -- RC Set-up Time

Parameters

VOL

1,2,3

DI -- RC Hold Time

7,8,9,10,11

VIH

1,2,3

DI -- MPC Set-up Time

7,8,9,10,11

VILMax.

1,2,3

IIH

1,2,3

DI -- MPC Hold Time
10-13 Set-up Time

7,8,9,10,11

IlL

1,2,3

10-13 Hold Time

7,8,9,10,11

IOH

1,2,3

CC Set-up Time

7,8,9,10,11

IOL

1,2,3

CC Hold Time

7,8,9,10,11

IOZ

1,2,3

CCEN Set-up Time

7,8,9,10,11

ISC

1,2,3

CCEN Hold Time

7,8,9,10,11

Icc

1,2,3

CI Set-up Time

7,8,9,10,11

ICC!

1,2,3

CIHoidTime

7,8,9,10,11

'RII> Set-up Time
'RII> Hold Time

7,8,9,10,11

Clock Requirements
Parameters

Subgroups

Minimum Clock LOW

7,8,9,10,11

Combinational Propagation Delays
Parameters
FromDO-D11 toY

Subgroups
7,8,9,10,11

From 10-13 to Y

7,8,9,10,11

From 10-13 to PL, VEcr, MAP

7,8,9,10,11

FromCCtoY

7,8,9,10,11

From CCEN to Y

7,8,9,10,11

From CP (I = 8,9,15) to FULL

7,8,9,10,11

From CP (All Other I) to Y

7,8,9,10,11

From CP (All Other I) to FUII

7,8,9,10,11

Document #: 38-00016-B

5-120

Subgroups
7,8,9,10,11

7,8,9,10,11

7,8,9,10,11

CY7C9101

CYPRESS
SEMICONDUCTOR

CMOS Sixteen-Bit Slice

Features
• Fast
- CY7C9101-30 has a 30 ns
(max.) clock cycle
(commercial)
- CY7C9101-35 has a 35 ns
(max.) clock cycle (military)

• Expandable
- Infinitely expandable in
16-bit increments

• Low Power
- Icc (max. at
10 MHz) = 60 mA
(commercial)
- Icc (max. at
10 MHz) = 85 mA
(military)

• ESD Protection
- Capable of withstanding
greater than 2000V static
discharge voltage

• Vee Margin
- 5V ±10%
• All parameters guaranteed over
commercial and military
operating temperature range
• Replaces four 2901's with carry
look·ahead logic
• Eight Function ALU
- Performs three arithmetic
and five logical operations
on two 16-bit operands

• Four Status Flags
- Carry, overflow, negative,
zero

• Pin compatible and functionally
equivalent to AM29C101

Functional Description
The CY7C9101 is a high·speed, expandable, l6-bit wide ALU slice which
can be used to implement the arithmetic section of a CPU, peripheral controller, or programmable controller.
The instruction set of the CY7C91Ol is
basic, yet so versatile that it can emulate the ALU of almost any digital
computer.

Logic Block Diagram

The CY7C91Ol, as shown in the block
diagram, consists of a l6-word by
l6-bit dual-port RAM register file, a
l6-bit ALU, and the necessary data
manipulation and control logic.
The function performed is determined
by the nine-bit instruction word (Is to
10) which is usually input via a microinstruction register.
The CY7C91Ol is expandable in l6-bit
increments, has three-state data outputs as well as flag outputs, and can
implement either a full look-ahead carry or a ripple carry.
The CY7C91Ol is a pin compatible,
functional equivalent ofthe Am29ClOl
with improVed performance. The
7C9l0l replaces four 2901's and includes on-chip carry look-ahead logic.
Fabricated in an advanced 1.2 micron
CMOS process, the 7C9l0l eliminates
latchup, has ESD protection greater
than 2000V, and achieves superior performance with low power dissipation.

Pin Configuration

18-0

Top View

"P

ii
e N• 16

0'"

'"

Y"

"0"
0,.
0"
0"

0"
D15-0
(DIRECT
DATA-IN)

0"

..
0,

Vee
0,
D.
0,
0,
0,

0,
0,
0,

r=o
c"

.,"
"

"C,
RAMo

0,

0079-1
0079-2

Figure 1

5-121

II

~
cY7C9101
~~~~=============================================================
Selection Guide

7C9101-30
7C9101-35

7C9101-40
7C9101-45

Minimum Clock
Cycle (ns)

Commercial

30

40

Military

35

45

Maximum Operating
Current at 10 MHz (mA)

Commercial

60

60

Military

85

85

Maximum Ratings
(Above which the useful life may be impaired. For user guidelines. not tested.)
Storage Temperature ............... -65'C to + 150"C
Static Discharge Voltage ..................... >200IV
(per MIL-STD-883 Method 3015)
Ambient Temperature with
Power Applied .................... -55'C to + 125'C

Latchup Current (Outputs) .................. > 200 mA

Supply Voltage to Ground
Potential .........................•. -0.5Vto +7.0V

Operating Range

DC Voltage Applied to Outputs

Range

in High Z State ...................... - 0.5V to + 7.0V
Commercial

DC Input Voltage ................... - 3.0V to + 7.0V

MilitaryU)

Output Current into Outputs (Low) ............. 30 mA

Ambient

Temperature
O"Cto +70"C
- 55'C to

+ 125'C

Vee
5V ±10%
SV ±IO%

Note:
1. TA is the "instsnt on" case temperature.

Pin Definitions
Signal I/O
Name

Signal 110
Name

Description

A3-0

RAM Address A. This 4-bit address word selects
one ofthe 16 registers in the register file for
output on the (internal) A-port.
B3-0
RAM Address B. This 4-bit address word selects
one of the 16 registers in the register file for
output on the (internal) B-port. When data is
written back to the register file. this is the
destination address.
18-0
Instruction Word. This nine-bit word is decoded
to determine the ALU data sources (10, I, 2). the
ALU operation (13, 4, 5), and the data to be
written to the Q-register or register file (16, 7, 8).
015-0
Direct Data Input. This 16-bit data word may be
selected by the 10, I, 2 lines as an input to the
ALU.
y 15-0
Data Output. These are three-state data output
lines which. when enabled. output either the
ALU result or the data in the A latch, as
determined by the code on 16, 7, 8.
OB
Output Enable. This is an active LOW input
which controls the Y 15-0 outputs. A HIGH level
on this signal places the output drivers at the high
impedance state.
CP
I Clock. The LOW level of CP is used to write data
to the RAM register file. A HIGH level of CP
writes data from the dual port RAM to the A and
B latches. The operation of the Q register is
similar; data is entered into the master latch on
the LOW level of CP and transferred from master
to slave during CP = HIGH.
Q15.
These two lines are bidirectional and are
RAMIS I/O controlled by 16, 7, 8. They are three-state output
drivers connected to the TTL compatible CMOS
inputs.

Description

Output Mode: When the destination code on lines
RAMIS I/O 16, 7, 8 indicates a left shift (UP) operation. the
three-state outputs are enabled and the MSB of
(Cont.)
the Q register is output on the QIS pin and
likewise. the MSB of the ALU output (FIs) is
output on the RAM IS pin.
Input Mode: When the destination code indicates
a right shift (DOWN). the pins are the data
inputs to the MSB of the Q register and the
RAM. respectively.
Qo.
These two lines are bidirectional and function
RAMo 110 similarly to the QIS and RAMls lines. The Qo
and RAMo lines are the LSB of the Q register
and the RAM.
I Carry In. The carry in to the internal ALU.
C n + 16 0 Carry Out. The carry out from the internal ALU.
<1. IS
0 Carry Generate. Carry Propagate. Outputs from
the ALU which may be used to perform a carry
look-ahead operation over the 16-bits of the
ALU.
OVR
0 Overflow. This signal is the logical exclusive-OR
of the carry-in and carry-out ofthe MSB of the
ALU. This indicates when the result of the ALU
operation exceeded the capacity of the machine's
two's complement number range. It is valid only
for the sign bit.
F = 0 0 Zero Detect. Open drain output which goes
HIGH when the data on outputs (PIS-O) are all
LOW. It indicates that the result of an ALU
operation is zero (positive logic assumed).
Fis
0 Sign. The MSB of the ALU output.

QIS.

en

5-122

Top View

88GG®GGGG
8 GGGG
8<9<9<9
40

36

36

39

37

35

51

50

53

52

49

55

5.

57

56

59

58

98
00

61

60

88

63

62

65

64

.7

8@
80
00
80
88
GG

45

34

99

r-------------,

32

33

30

31

28

29

26

27

24

25

22

23

(90

G8

L _ _ _ _ _ _ _ _ _ _ _ _ _ .1

0~

GG

888G)890 eeee
·00 0@@G- ~':noH ~t'~;'~W-;F".4;'''~1~W'"~:
~-----~!
OECOOE

t.lUX

I

t.lUX

t.lUX

t.lUX

t.lUX

t.lUX'

---T'---f<16:3:IN-t.lix)1----

CP

05
OEN

>-t>.

0 15

0 14
014

013

0 13
012

•••

O2

O-REGISTER
•••
03

01

02

DO

01

00
~

0079-5

Figure 3. Q·Register

5-126

~

CY7C9101

CYPRESS

~~I~ooaoR====================================================~~~~
Description of Architecture (Continued)
7C9101, using the ALU i!!puts carry in (CO> and the ALU
outputs carry propagate (P), carry generate (G), carry out
(Cn + 16), and overflow to implement carry lookahead
arithmetic and determine if arithmetic overflow has occurred. Note that the carry in (CO> signal affects the arithmetic result and internal flags; it has no effect on the logical operations.
Control signals 16, 7, 8 route the ALU data output (FI5-0)
to the RAM, the Q-register inputs, and the Y -outputs as
shown in Table 3. The ALU result MSB (FI5) is output so
the user may examine the sign bit without needing to enable the three-state outputs. The F = 0 output, used for
zero detection, is HIGH when all bits of the F output are
LOW. It is an open drain output which may be wire OR'ed
across multiple 7C9101 processor slices.

ALU (Arithmetic Logic Unit)
The ALU can perform three arithmetic and five logical
operations on the two 16-bit input operands, Rand S. The
R-input multiplexer selects between data from the RAM
A-port and data at the external data input, 015-0. The
S-input multiplexer selects between data from the RAM
A-port, the RAM B-port, and the Q-register. The Rand S
!llultiplexers are controlled by the 10, 1,2 inputs as shown
In Table 1. The Rand S input multiplexers each have an
"inhibit capability," offering a state where no data is
passed. This is equivalent to a source operand consisting of
all zeroes. The Rand S ALU source multiplexers are configured to allow eight pairs of combinations of A, B, 0, Q,
and "0" to be selected as ALU input operands.
The ALU functions, which are controlled by 13, 4, 5, are
shown in Table 2. Carry lookahead logic is resident on the

015

014

•••

01

DO

B15

B14

•••

Bl

BO
Q15

Q14

A15
A14

Al
AO

••
•

••
•

12
11
10
Rl

5 15

Ro

5 14

•••

51

16-BIT ARITHt.lETIC LOGIC UNIT(ALU)
FIS

F14

•••

Fl

Fo

18

•••

17
16

OE
YIS

Y14

•••
•••

Y1

Yo
0079-6

Figure 4. ALU

5-127

~

CY7C9101

~~~~R================================================================
Description of Architecture (Continued)
Table 6. ALU Arithmetic Mode Functions
Cn = o(Low)
= 1 (High)
1543,1210
Group
Function
Group
Function

Table 5. ALU Logic Mode Functions
Octal
1543,1210

40
41
45
46

Group

AND

30
31
35
36

OR

60
61
65
66

EX-OR

70
71
75
76

EX-NOR

72
73
74
77
62
63
64
67

Function
AAQ
AAB
DAA
DAQ

00
01
05
06

AVQ
AVB
DVA
DVQ
AVQ
AVB
DVA
DVQ

02
03
04
07
12
13
14
27
22
23
24
17

Decrement

10
11
15
16
20
21
25
26

Q-A-l
B-A-l
A-D-l
Q-D-l Subtract
Subtract
(l's Comp.) A-Q-l (2'sComp.)
A-B-l
D-A-l
D-Q-l

AV"Q
AVB
DVA
i'J"lTQ
Q
INVERT

PASS

32
33
34
37

PASS

42
43
44
47

"ZERO"

50
51
55
56

MASK

en

Octal

B
A
D
Q
B
A
D
Q
B
A
D
0
0
0
0

ADD

PASS

l'sComp.

A+Q
A+B
D+A
D+Q
Q
B
A
D
Q-l
B-1
A-I
D-l
-Q-l
-B-1
-A-l
-D-l

ADD plus
one

Increment

PASS

2'sComp.
(Negate)

A+Q+l
A+B+l
D+A+l
D+Q+l
Q+l
B+l
A+l
D+l
Q
B
A
D
-Q
-B
-A
-D
Q-A
B-A
A-D
Q-D
A-Q
A-B
D-A
D-Q

Conventional Addition and Pass-Increment/
Decrement
When the carry-in is HIGH and either a conventional addition or a PASS operation is performed, one (I) is added
to the result. If the DECREMENT operation is performed
when the carry-in is LOW, the value of the operand is
reduced by one. However, when the same operation is performed when the carry-in is HIGH, it nullifies the DECREMENT operation so that the result is equivalent to the
PASS operation. In logical operations, the carry-in (en)
will not affect the ALU output.
Subtraction
Recall that in two's complement integer coding - I is
equal to all ones and that in one's complement integer coding zero is equal to all ones. To convert a positive integer to
its two's complement (negative) equivalent, invert (complement) the number and add 1 to it; i.e., TWC = ONC + 1.
In Table 6 the symbol - Q represents the two's complement of Q so that the one's complement of Q is then
-Q -1.

AAQ
AAB
DAA
DAQ

5-128

~

CY7C9101

~~~U~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
Electrical Characteristics Over Commercial and Military Operating Range[4)
VccMin.

= 4.5V, VccMax. = 5.5V

Description

Parameters

Test Conditions

VOH

Output HIGH Voltage

Vee = Min.
IOH = -3.4mA

VOL

Output LOW Voltage

Vee = Min.
IOL = 16mA

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

Min.

Max.

2.4

V
0.4

V

2.0

Vee

V

-3.0

0.8

V

-10

10

/LA

-3.4

rnA

16

rnA

IIX

Input Leakage Current

Vss ~ VIN ,;;; Vee
Vee = Max.

IOH

Output HIGH Current

Vee = Min.
VOH = 2.4V

IOL

Output LOW Current

Vee
VOL

Ioz

Output Leakage Current

Ise

Output Short Circuit Current[!)

Iee(Q\)[2)

Supply Current
(Quiescent)

Commercial

VSS

Military

VIH ~ VIN ~ Vee; OE = HIGH

35

Supply Current
(Quiescent)

Commercial

VSS ~ VIN ~ O.4Vor
3.85V ,;;; VIN ~ Vee; OE

25

Supply Current

Commercial

Iec(Q2) [2)

Iec(Max.) [21

Military

Military

= Min.
= 0.4V
Vee = Max.
VOUT = Vss to Vee
Vee = Max.
VOUT = OV
~

=

+40

/LA
/LA

-85

rnA

-40

30

VIN ,;;; VIL or

Vee = Max., feLK
OE = HIGH

Units

=

HIGH

rnA

rnA

30

60

10 MHz;

rnA

85

Capacitance [3]
Parameters
CIN

CoUT

Description

Test Conditions

Max.

Input Capacitance

TA = 25"C, f= I MHz
Vee = 5.0V

5

Output Capacitance

Notes:
1. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
2. Two quiescent figures are given for different input voltage ranges. To
calculate Icc at any given frequency. use Icc(Qt) + Icc(A.C.) where
Icc(Qt) is shown above and Icc(A.e.) = (3 mAIMHz) X Clock
Frequency for the Commercial temperature range. Icc(A.C.) =
(S mAlMHz) X Clock Frequency for Military temperature range.

Units
pF

7

3. Tested initially and after any design or process changes that may

affect these parameters.
4. See the last page of this specification for Group A subgroup testing

information.

Output Loads used for AC Performance Characteristics
+5V

+5 V

~

2520

2701l

VO~

VOUT

J;CL

1710

0079-'0
0079-9

Open Drain (F = 0)

All Outputs except Open Drain
Notes:
1. CL = 50 pF includes scope probe. wiring and stray capacitance.
2. CL = 5 pF for output disable tests.

5·129

~

CY7C9101

~~~~u~================================================================
Table 7. Logic Functions for CARRY and OVERFLOW Conditions

I~

Function

0

R+S

1

S-R

2

R-S

3

RVS

4

RAS

5

R:AS

6

R¥S

7

R¥S

Defmitions:

+

P

G

c,,+ 16

OVR

--

GI5 + PISGI4 + PISPI4GI3 +
... + PI-IS GO

CI6

CI6 ¥ CIS

PO-PIS

--

Same as R + S equations, but substitute Rj for Rj in definitions
Same as R + S equations, but substitute Sj for Sj in definitions

HIGH

LOW

HIGH

LOW

= OR

PO-IS = PIS PI4 P13 PI2 PI I PIO P9 Ps P7 P6 Ps P4 P3 P2 PI Po
Po = Ro + So
PI = RI + S2
P2=R2+S2
P3 = R3 + S3, etc.
GO-IS = GI5 GI4 G13 GI2 Gil GIO G9 Gs G7 G6 Gs G4 G3 G2 GI Go
Go=RoSo
G1 = RI SI
G2 = R2S2
G3 = R3 S3, etc.
CI6 = GIS + PIS G14 + PIS PI4 G13 + ... + PO-IS C n
CIS = GI4 + PI4 GI3 + P14 PI3 GI2 + ... + PO-14 C n

CY7C9101·30 and CY7C9101·40 Guaranteed
Commercial Range AC Performance
Characteristics

Cycle Time and Clock Characteristics
CY7C9101·
Read-Modify-Write Cycle (from
selection of A, B registers to
end of cycle).
Maximum Clock Frequency to shift Q
(50% duty cycle, I = 432 or 632)
Minimum Clock LOW Time
Minimum Clock HIGH Time
Minimum Clock Period

The tables below specify the guaranteed AC performance
of these devices over the Commercial (O"C to 70"C) and
Military (- 55°C to + 12S°C) operating temperature range
with Vee varying from 4.SV to S.SV. All times are in
nanoseconds and are measured between the l.SV signal lev·
e1s. The inputs switch between OV and 3V with signal tran·
sition rates of 1V per nanosecond. All outputs have maxi·
mum DC current loads. See also loading circuit information.

30
30ns

40ns

33 MHz

25 MHz

20ns
iOns
30ns

25 ns
15 ns
40ns

40

This data applies to parts with the following numbers:
CY7C9101-30PC
CY7C9101·40PC

Combinational

CY7C9101-30DC CY7C9101-30LC
CY7C9101-40DC CY7C9101-40LC
Propagation Delays. CL = SO pF

CY7C9101·30JC
CY7C9101-40JC

CY7C9101-3OGC
CY7C9101-4OGC

To Output
From Input
CY7C9101·
A, BAddress
D
Cn
10,1,2

30
37
29
22
32

40

30

40

47
34
27
40

36
28
22
32

47
34
27
40

13,4, S

34

43

33

42

33

42

27

35

34

40

16,7, s
A Bypass ALU
(I = 2XX)
Clock-f"

19

22

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

30

39

30

38

27

34

28

37

Y

25

30

31

40

G,P

c" + 16

F15

30
35
25
20
30

40
44

32
25
38

30
32
25
28

S-130

OVR

F=O

40

41
30

36

30
35
29
22
34

40

46
36
26
42

30
32
21
22
26

RAMo
RAM15

Qo
Q15

30
32
27
24
27

40

30

40

42
26
26
32

40
33
30
35

-

-

32

42

29

-

-

22

-

-

27

34

40

-

38

-

-

26

22

26

-

-

-

-

27

35

20

23

-

~
CY7C9101
,..,~~~========================================================
Set-Up and Hold Times Relative to Clock (CP) Input[l]
CP:

-,-

""'r-

Input
Set-UpTime
BeforeH -+ L

Hold Time
AfterH -+ L

CY7C9101-

30

40

30

A, B Source Address

10

15

3[3]

40
3[3]

~

~-

Set-upTime
BeforeL -+ H

30
30[4]

40
40[4]

Do Not Change[2]

+-

Hold Time
AfterL -+ H

-+

30

40

0

0

B Destiuation Address

10

15

0

0

D

-

-

-

-

22

28

0

0

c"

-

-

-

16

22

0

0

26

35

0

0

-

-

-

29

37

0

0

0

0

0

0

13,4,5

-

16,7,8

10

12

RAMo, RAMIS, Qo, QIS

-

-

10, 1,2

-+

Do Not Change[2]

+-

-

-

11

14

Output EnablelDisable Times
Output disable tests perfonned with CL = 5 pF and measured to O.5V change of output voltage level.
3. Source addresses must be stable prior to the clock H
Input
Output
Device
Enable
Disable
CY7C9101-30
CY7C9101-4O

OR
OE

Y
Y

18
22

-4 L transition
to allow time to access the source data before the latches close. The A
address may then be changed. The B address could be changed if it is
not a destination; i.e. if data is not being written back into the RAM.
Normally A and B are not changed during the clock LOW time.
4. The set-up time prior to the clock L -4 H transition is to allow time
for data to be accessed, passed through the ALU, and returned to the
RAM. It includes all the time from stable A and B addresses to the
clock L - 4 H transition, regardless of when the clock H - 4 L
transition occurs.

16
19

Notes:
1. A dash indicates a propagation delay path or set-up time constraint
does not exist.
2. Certain signals must be stable during the entire clock LOW time to
avoid erroneous operation. This is indicated by the phrase "do not
change".

5-131

1:11

~
CY7C9101
~~~~==========================================================
Cycle Time and Clock Characteristics[5]

CY7C9101·35 and CY7C9101·45 Guaranteed
Military Range AC Performance
Characteristics

CY7C9101Read-Modify-Write Cycle (from
selection of A, B registers to
end of cycle).
Maximum Clock Frequency to shift Q
(50% duty cycle, I = 432 or 632)
Minimum Clock LOW Time
Minimum Clock HIGH Time
Minimum Clock Period

The tables below specify the guaranteed AC performance
of these devices over the Military (- 55°C to + 125°C) operating temperature range with Vee varying from 4.5V to
5.5V. All times are in nanoseconds and are measured between the 1.5V signal levels. The inputs switch between OV
and 3V with signal transition rates of IV per nanosecond.
All outputs have maximum DC current loads. See also
loading circuit information.

35
35 ns

45
45ns

28 MHz

22 MHz

23 ns
l2ns
35 ns

28ns
17ns
45 ns

This data applies to parts with the following numbers:
CY7C91Ol-35DMB
CY7C91Ol-45DMB

CY7C9l0l-35LMB
CY7C91Ol-45LMB

CY7C91Ol-35GMB
CY7C91Ol-45GMB

Combinational Propagation Delays CL
To Output
From Input
CY7C9101A, BAddress
D

Y
35

10, 1,2

45
52
37
30
44

13,4, S

38

16,7,8

21

A BypassALU
(I = 2XX)
Clock..r

c.. + 16

F15

35
41
31
25
36

c"

= 50 pF[5]

G,P

F=O
45
45
32

35
36
23
23
29

31
24
35

35
38
29
23
33

45
48
36
27
41

35
37
28
31

48

37

47

37

46

31

38

38

45

36

24

-

-

-

-

-

-

-

-

-

28

33

-

-

-

-

-

-

-

-

-

35

44

34

43

34

42

30

37

34

40

28

38

35

45
48

45
51
36
29
43

40

40

33
24
38

RAMo

OVR

40

29
46

Qo
Q15

RAM15

45
46
32
27
38

35
36
30
26
30

45
43
35
31
38

35

45

-

-

-

-

45

33

-

24

41

-

-

28

24

28

38

-

-

-

-

30

37

21

25

-

Set·Up and Hold Times Relative to Clock (CP) Input[l, 5]
CP:

..l

Input

CY7C9101A, B Source Address
B Destination Address
D

c"
10,1,2
13,4,5
16,7,8
RAMo, RAMIS, Qo, QIS

Set-UpTime
BeforeH L
35
45
12
17
12
17

.-

_.Hold Time
AfterH L
35
45
3[3]
3[3]

~

~-

Set-UpTime
BeforeL H
45
35
35[4]
45[4]

Do Not Change[2]

+-

-

-

-

-

-

-

-

-

12
-

16
-

-

25
19
30
33
Do Not Change[2]

+-

-

-

13

30
24
37
40

15

-

-

Hold Time
AfterL H
35
45
0
0
1
1
0
0
0
0
0
0
0
0
0
0
I
1

Output EnablelDisable Times[S]
Output disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage level.
Device
CY7C9101-35
CY7C9101-45

Input
OE
OE

Output
y

Y

Enable
20
23

3. Source addresses must be stable prior to the clock H --. L transition
to allow time to access the source data before the latches close. The A
address may then be changed. The B address could be changed if it is
not a destination; i.e. if data is not being written back into the RAM.
Normally A and B are not changed during the clock LOW time.
4. The set-up time prior to the clock L --. H transition is to allow time
for data to be accessed, passed through the ALU, and returned to the
RAM. It includes all the time from stable A and B addresses to the
clock L --. H transition, regardless of when the clock H --. L
transition occurs.
5. See the last page of this specification for Group A subgroup testing
information.

Disable
17
20

Notes:
1. A dash indicates a propagation delay path or set-up time constraint
does not exist.
2. Certain signals must be stable during the entire clock LOW time to
avoid erroneous operation. This is indicated by the phrase "do not
change".

5-132

~
CY7C9101
~~~~=============================================================
Applications

Minimum Cycle Time Calculations for 16·Bit Systems
Speeds used in calculations for parts other than CY7C9101 and CY7C91O are representative for available MSI parts.

F=O
CY7C9101

Cn+ 16
OVR

4

F 15

DATA

II

REGISTER

0079-15

Pipelined System, Add without Simultaneous Shift
CY7C245
CY7C901
Register

Data Loop
Clock to Output
A, B to Y, c,,+ 16, OVR
Setup

12
37
4

CY7C245
MUX
CY7C910
CY7C245

53 ns

Control Loop
Clock to Output
Select to Output
CC to Output

Access Time

12
12
22
20

66ns
Minimum Oock Period = 66 os

0079-13

Pipelined System, Simultaneous Add and Shift Down (RIGHT)
CY7C245
CY7C9101
XORand MUX
CY7C9101

Data Loop
Clock to Output
A, B to Y, c,,+ 16, OVR
Prop. Delay, Select
to Output
RAM1SSetuP

12
37
20

CY7C245

MUX
CY7C910
CY7C245

11

Control Loop
Clock to Output
Select to Output
cc to Output

Access Time

12
12
22
20

66ns

80ns
MiDimum Oock Period = 80 DS

5-133

~
CY7C9101
,..,~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
1.6 VII.SUPPLYVOLTAGE

NORMALIZED SUPPLY CURRENT
1.2 VII. AMBIENT TEMPERATIJRE

OUTPUT SOURCE CURRENT
VOLTAGE

eo VII

I

Vcc= 5.0V
T,,=25OC-

50

8

i

1.2
1.0

oz

0.8

/'

0.6

/

V

"-

/
20

s.o

0.8 '--_ _ _J...._ _ _ _...J

5.5

-55

6.0

SUPPLY VOLT"GE(V)

1z
...
=>
0

100

IX
IX
~

z

75

~

50

=>
D..
~
=>
0

25

NORMALIZED FREQUENCY
AMBIENT TEMPERATIJRE

/

oV
o

/

~=>
...f3

'1

~

!

...t:I
0

z

120

~
...

100

=>
0

eo
eo

IX
IX

Q

IX

~

Vcc= 5.0V

5

-ss

OUTPUT VOLT"GE (V)

25

~

1.4

0

1.3

8

~

IX

0

z

1.0

2.D

3.0

4.0

OUTPUT VOLTAGE (V)

VI.

I.,...-

V
./

0.8

/

o

Vcc=5.0V
T,,=25OC

I

0.7

I
200

~/

0.9

/

1.1

./

.

1.0

V"
./

1.2

1.0

o

1.1

1.5

=>

I!:
=>

/

NORMALIZED Icc
FREQUENCY

TYPICAL OUTPUT DELAY
CHANGE VII. OUTPUT LOADING

5

I

-----

Vcc= 5.0V
T,,=25OC-

I

o

125

",

/

"WBIENT TEWPERATURE(OC)

1.6

I!l

/

20

0

2.D

,

040

!5

0.8
0.6L----~-----J

1.0

3.0

OUTPUT SINK CURRENT
VII. OUTPUT VOLTAGE

1040

IX

Vcc= 5.0V
T,,=25OC_

'"'"

2.D

1.0

OUTPUT VOLTAGE (V)

VI.

)~

1/

o
o

125

1.6r----r-----~

.,. ~

iii

25
"WBIENT TEWPERATURE(OC)

OUTPUT SINK CURRENT
VII. OUTPUT VOLTAGE

150
125

~

~

10

f=10WHz
T,,=25OC

4.0

175

"' "-

«lO

600

600

1000

o
o

/

I'

V
Vcc "5.5V
T,,=25OC_
VIN =OVor3V

I
5

I

10 15 20 25 30 35
F'REQUENCY (WHz)

CAP"CITANCE (pF')

0079-14

5-134

~

CY7C9101

~~~aoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
Ordering Information
Speed
(os)

Ordering Code

Package
Type

Operating
Range
Commercial

30

CY7C9101-30 PC
CY7C9101-30 LC
CY7C9101-30 lC
CY7C9101-30 DC
CY7C9101-30 GC

P29
LSI
181
D30
068

40

CY7C9101-40 PC
CY7C9101-40 LC
CY7C9101-40 lC
CY7C9101-40 DC
CY7C9101-40 OC

P29
L81
181
D30
068

35

CY7C9101-35 LMB
CY7C9101-35 DMB
CY7C9101-350MB

L81
D30
068

45

CY7C9101-45 LMB
CY7C9101-45 DMB
CY7C9101-45 OMB

LSI
030
068

Military

5-135

~
CY7C9101
~~~U~================================================================
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics

Combinational Propagation Delays (Continued)

Parameters

Subgroups

VOH

1,2,3

VOL
VIH

Parameters

Subgroups

From Cn to F = 0

7,8,9,10,11

1,2,3

From Cn to OVR

7,8,9,10,11

1,2,3

From Cn to RAMo, IS

7,8,9,10,11

VILMax.

1,2,3

From 1012 to Y

7,8,9,10,11

IIX

1,2,3

From 1012 to FI5

7,8,9,10,11

loz

1,2,3

From 1012 to Cn + 16

7,8,9,10,11

Isc

1,2,3

From 1012 to <1, P

7,8,9,10,11

Icc (Ql)

1,2,3

From 1012 to F = 0

7,8,9,10,11

Icc (Q2)

1,2,3

From 1012 to OVR

7,8,9,10,11

IcC (Max.)

1,2,3

From 1012 to RAMo, 15

7,8,9,10,11

Combinational Propagation Delays

From 1345 to Y

7,8,9,10,11

From 1345 to FI5

7,8,9,10,11

Subgroups

From 1345 to C n + 16

7,8,9,10,11

From A, B Address to Y

7,8,9,10,11

From 1345 to <1, P

7,8,9,10,11

From A, B Address to FI5

7,8,9,10,11

From 1345 to F = 0

7,8,9,10,11

From A, B Address to Cn + 16

7,8,9,10,11

From 1345 to OVR

7,8,9,10,11

From A, B Address to G, P

7,8,9,10,11

From 1345 to RAMo, 15

7,8,9,10,11

Parameters

From A, B Address to F

=0

7,8,9,10,11

From 1678 to Y

7,8,9,10,11

From A, B Address to OVR

7,8,9,10,11

From 1678 to RAMo, 15

7,8,9,10,11

From 1678 to 00,15

7,8,9,10,11
7,8,9,10,11

From A, B Address to RAMo, 15

7,8,9,10,11

FromDtoY

7,8,9,10,11

FromDtoFI5

7,8,9,10,11

From A Bypass ALU to Y
(I = 2XX)

From D to Cn+ 16

7,8,9,10,11

From Clock...r to Y

7,8,9,10,11

From D to <1, P

7,8,9,10,11

From Clock...r to FI5

7,8,9,10,11

=0

7,8,9,10,11

From Clock...r to Cn+ 16

7,8,9,10,11

FromDtoOVR

7,8,9,10,11

From Clock...r to <1, P

7,8,9,10,11

From D to RAMO, 15

7,8,9,10,11

From Clock ...r to F = 0

7,8,9,10,11

FromCn toY

7,8,9,10,11

From Clock ...r to OVR

7,8,9,10,11

From Cn to FIS

7,8,9,10,11

From Clock...r to RAMo, IS

7,8,9,10,11

From Cn to Cn + 16

7,8,9,10,11

From Clock ...r to 00, 15

7,8,9,10,11

FromDtoF

5·136

~

CY7C9101

~r~~====================
Set-up and Hold Times Relative to Clock (CP) Input
Parameters

A, B Source Address
Hold Time After H -

7,8,9,10,11

B Destination Address
Hold Time After H -

-

H

1012 Hold Time After L -

H

7,8,9,10,11

H

1678 Hold Time After H 7,8,9,10,11

L

L
7,8,9,10,11

1678 Hold Time After L -

7,8,9,10,11

RAMo, RAMI5, 00, QI5
Set-up Time Before L -

7,8,9,10,11

RAMo, RAMI5, 00, QI5
Hold Time After L H

H
H

Document #: 38-00017-B

5-137

H
H

7,8,9,10,11
7,8,9,10,11

L

1678 Set-up Time Before L -

7,8,9,10,11
7,8,9,10,11

H

1678 Set-up Time Before H -

L

7,8,9,10,11
7,8,9,10,11

H

1345 Hold Time After L -

H

H

1345 Set-up Time Before L -

7,8,9,10,11
H

7,8,9,10,11
7,8,9,10,11

H

1012 Set-up Time Before L -

7,8,9,10,11

D Set-up Time Before L -

7,8,9,10,11

H

Cn Hold Time After L -

L

B Destination Address
Set-upTime Before L B Destination Address
Hold Time After L -

en Set-up Time Before L
7,8,9,10,11

B Destination Address
Set-upTime Before H -

Sublll'oups

D Hold Time After L -

L

A, B Source Address
Set-up Time Before L A, B Source Address
Hold Time After L -

Parameters

Sublll'oups

A, B Source Address
Set-up Time Before H -

7,8,9,10,11
7,8,9,10,11
7,8,9,10,11

H
7,8,9,10,11

II

PRELIMINARY

CYPRESS
SEMICONDUCTOR

CY7C9115
CY7C9116/CY7C9117

CMOS 16-Bit
Microprogrammed ALU

Features

• Low power CMOS
- Icc (max. at 10 MlIz)
145 mA (commercial)
- ICC (max. static) = 68 mA
(commercial)

•
•
•
•

• Vee margi!l
-

5V ±10%

-

All parameters guaranteed
over commercial and military
operating temperature range

• ESD protection
- Capable of withstanding
greater than 2001 V static
discharge voltage
• Pin compatible and functionally
equivalent to 29116, 29116A,
29C116, 29117, 29117A, 29C117

• CY7C9117 separate I/O
- One and two operand
arithmetic and logical
operations
- Bit manipulation, field
insertion/extraction
instructions
- Eleven types of instructions

• Fast
- 35 ns worst case propagation
delay, I to Y

• Instruction set and architecture
optimized for high speed
controller applications

Immediate instruction capability
16-bit barrel shifter capability
32-word x 16-bit register file
8-bit status register
- Four ALU status bits
- Link bit and three user
definable status bits

Functional Description
The CY7C9115, CY7C9116 and
CY7C9117 are high speed 16-bit microprogrammed Arithmetic and Logic
Units, (ALU).
The architecture and instruction set of
the devices are optimized for peripheral
controller applications such as disk
controllers, graphics controllers, communications controllers, and modems .

.--------+-i

$fiE

1:>-4--1

DE,

0085-4

0085-5

Figure 2. CY7C9117 Block Diagram

Figure 1. CY7C9115, CY7C9116 Block Diagram

Selection Guide
Worst Case I-Y
Propagation Delay (ns)

Commercial

Maximum Operating
Current @ 10 MHz (mA)

Commercial

7C911X-35

7C911X-40/45

7C911X-65

35

45

65

40

65

145

145

145

166

166

Military
Military

5-138

7C911X-79
79
166

(;n

PRELIMINAR Y

CY7C9115
CY7C9116/CY7C9117

~~NDU~R ==~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==

Functional Description (Continued)
instructions, prioritize, Cyclic Redundancy Check (CRC),
status, and NO-OP. Instruction execution occurs in a single clock cycle except for Immediate Instructions, which
require two clock cycles to execute.
The CY7C9116 and CY7C9117 are pin compatible, functional equivalent of the industry standard 29116, 29116A,
29Cl16, 29117, 29117A, 29CI17 with improved performance.
Fabricated in an advanced 1.2 micron, two-level metal
CMOS process, the CY7C9115, CY7C9116 and
CY7C9117 eliminates latchup, has ESD protection greater
than 2001V, and achieves superior performance with low
power dissipation.

When used with the CY7C517 multiplier, the CY7C9115,
CY7C9116 and CY7C9117 also support microprogrammed processor applications.
The CY7C9115, CY7C9116 and CY7C9117 are shown in
the block diagram, consists of a 32-word by 16-bit sing1eport RAM register file, a 16-bit arithmetic unit and logic
unit, an instruction latch and decoder, a data latch, an
accumulator register, a 16-bit barrel shifter, a priority encoder, a status register, a condition code generator and
multiplexer, and three-state output buffers.
The instruction set ofthe CY7C9115, CY7C9116 and
CY7C9117 can be divided into eleven instruction types:
single-operand, two-operand, single-bit shifts, rotate and
merge, rotate and compare, rotate by n-bits, bit oriented

Pin Configurations CY7C9115, CY7C9116
Top View

',5

Top View

Yo
~w

Y,

Y.
Y.

Y2

Y3

GNO

Y4

0Ey

Ys

Y7
Vee
Vee
YB
Y.
Y,0

Y.
GND

OEy
Y7
Vee

IU
GIll

Vee

Yl1

0

55 GND

Y7 17
Vee 18

7C911S

Vee 19

51 '2

00',

Va 20

•• 10

Yg 21

.. CP
47 iEiii

Y,O 22
OLE 23

0085-3

",SRi:
.. CT

V'Z 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 4' 42 4344 eEl

7C9115PLCC
7C9116LCC

GND

Y,3

57 '6
56 15
!4 Vee
53 14
52 13

V,I 25

CT

58~

O'E y 16

Yo

SRE

~~

Va 14

OND 2.4

Y
"
Y,2

.. '.

GND 15

Ya

DLE

21688766856463&261

Y" 12
Ys 13

Y, 0

i"EN

987654:S

Nt 11

0085-22

PLCC

Y,4
Y, s

NC}
NC
RESERVED

T,
0085-2

7C9116

DIP

5-139

fin~~~===============================================================
CY7C9115
CY7C9116/CY7C9117

PRELIMINARY

Pin Configurations CY7C9117
Top View
Y3 10

9 8 7

6

5 4

3

2

1 68 67 66 65 64 63 62 61
60 19

~ 11

59 Ie

Y4 12
Ys 13

58

Y6 14

56 Is

7

57 16

GND 15

55 GND

OEy 16

54 Vee

Y7 17

53 14

Vee 18

52 13

Vee 19
Ye 20

51 '2
50 "
49 10

Y9 21
Y10 22

48 CP

iEN

OLE 23

47

GND 24

46 SRE

Y,l 25

45 CT

Y,2 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4344 OET

~~~~~~J~~~~~2J;~~
0085-6

LCC/PLCC

NC = No Connect
Top View

GGeeeGee8
<9 8@C9G88ee88
~

ee
Ge
e 0)
53

55

~

~

Q

45

44

42

~

~

~

~

48

48

43

~

~

~

~

57

~

59

~

8@
@G
00

r-------------,

54

34

33

32

~

~

~

28

8G

00

®8

0<9

60

~

61

26

63

25

88
0)
~

G

U

08

-------------

65

27

0 0
~

23

G0GGC0C0eee00
·G8GGGGeee
68

1

3

5

7

9

12

14

16

18

4

6

8

10

11

13

15

17

19

0085-7

CY7C9117 Pin for 68 PGA

NC = No Connect
5-140

5n
.

PRELIMINAR Y

CY7C9115
CY7C9116/CY7C9117

~NOO~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Description of Architecture
The CY7C9115, CY7C9116 and CY7C9117 are 16-bit microprogrammed arithmetic and logic units comprised of
the following sections (see block diagram):
•
•
•
•
•
•
•
•
•
•

data at the clock LOW to HIGH transition. Word instructions write into all 16 bits of the accumulator, byte instructions write into the lower eight bits.

32 Word x 16-Bit Register File
Data Latch
Instruction Latch and Decoder
Accumulator
Logic Unit with a 16-bit Barrel Shift Capability
Arithmetic Unit
Priority Encoder
Condition Code Generator and Multiplexer
Status Register
Output Buffers

16-Bit Barrel Shifter
The barrel shifter can rotate data input to it from either the
register file, the accumulator, or the data latch from 0 to 15
bit positions. In word mode, the barrel shifter rotates a
16-bit word; in byte mode, it only affects the lower eight
bits. The barrel shifter is used as one of the ALU inputs.
Arithmetic and Logic Unit
The CY7C9115, CY7C9116 and the CY7C9117 have an
arithmetic unit and a logic unit. The arithmetic unit is capable of operating on one or two operands while the logic
unit is capable of operating on one, two or three operands.
The two units in parallel are able to execute the one and
two operand instructions such as pass, complement, two's
complement, add, subtract, AND, OR, EXOR, NAND,
NOR, and EXNOR. Three operand instructions include
rotate/merge and rotate/masked compare. There are three
data types supported by the CY7C9115, CY7C9116 and
CY7C9117; bit, byte, and 16-bit word.

32-Word x 16-Bit Register File
The 32-word x 16-bit register file is a single port RAM
with a 16-bit latch at the output. The latch is transparent
while CP is HIGH and latched when CP is LOW. If lEN is
LOW and the current instruction specifies the RAM at its
destination, data is written into the RAM while CP is
LOW. Word instructions write into all 16-bits of the RAM
word addressed; byte instructions write into only the lower
eight bits.

All arithmetic and logic unit operations can be performed
in either word or byte mode, with byte instructions performed only on the lower eight bits.

Use of an exterual multiplexer on five of the instruction
inputs makes it possible to select separate read and write
addresses for the same NON-IMMEDIATE instruction.
Immediate Instructions do not allow this two-address operation for the 7C9115 and 7C9116. The 7C9117 does support two-address Immediate Instructions.

Three status output are generated by the arithmetic unit:
carry (C), negative (N), and overt1ow (OVR). A zero flag
(Z) detects a zero condition, though this flag is not generated by the arithmetic unit or the logic unit. These flags are
generated in either word or byte mode, as appropriate.
The arithmetic unit uses full carry look-ahead across all 16
bits during arithmetic operations. The carry input to the
arithmetic unit comes from the carry multiplexer, which
can select either zero, one, or a stored carry bit (QC) from
the status register. Multiprecision arithmetic uses QC as
the carry input.

Data Latch
The data latch holds the 16-bit input to the CY7C9115,
CY7C9116 and CY7C9117 from the Y (bidirectional) bus
for the 7C9115 and 7C9116 and the data bus for the
7C9117. When DLE is HIGH, the latch is transparent, it is
latched when DLE is LOW.

Priority Encoder

Instruction Latch and Decoder

The priority encoder generates a binary-weighted code
based on the location ofthe highest order ONE in its input
word or byte. The operand to be prioritized may be
AND-ed with a mask to eliminate certain bits from the
priority encoding. This masking is performed by the logic
unit.

The 16-bit instruction latch is always transparent, except
when Immediate Instructions are executed. The Instruction Decoder decodes the instruction inputs into the internal signals which control the CY7C9115, CY7C9116 and
CY7C9117. All instructions other than Immediate Instructions execute in a single clock cycle.

In word mode, the output is a binary one ifbit 15 is the
first (unmasked) HIGH encountered, a binary two ifbit 14
is the first HIGH and so on. Ifbit 0 is the only HIGH, the
output of the priority encoder is binary 16. If no bits are
HIGH, a binary zero is output.

Execution ofImmediate Instructions takes two clock cycles. During the first clock cycle, the Instruction Decoder
identifies the instruction as an Immediate Instruction and
the Instruction Latch captures the instruction at the instruction inputs. For Immediate Instructions, the data at
the instruction inputs during the second clock cycle is used
as one of the operands for the Immediate Instruction specified during the first clock cycle. Upon completion of the
Immediate Instruction (the end of the second clock cycle),
the Instruction Latch again becomes transparent.

In byte mode, only bits 7 through 0 are examined. Bit 7
HIGH produces a binary one, bit 6 a binary two, and so
on. If bit 0 is the only HIGH, a binary eight is output; ifno
bits are HIGH, a binary zero is output.
Condition Code Generator and Multiplexer
The twelve condition code test signals are generated in this
section. The multiplexer selects one of these twelve and
places it at the CT output. The multiplexer is addressed by
either using the Test Instruction or by using the bidirec-

Accumulator
The accumulator is a 16-bit edge triggered register. If the
lEN is LOW and the current instruction specifies the accumulator as its destination, the accumulator accepts Y input
5-141

~
..

.t.

fin
.

PRELIMINARY

CY7C9115
CY7C9116/CY7C91l7

~~==========~==~==~

Description of Architecture (Continued)

Pin Definitions

tional T bus as an input. The test instruction specifies the
test condition to be placed at the CT output, but it does not
allow an ALU operation at the same time. Using the T bus
as input, the CY7C9115, CY7C9116 and CY7C9117 may
simultaneously test and execute an instruction. The test
instruction lines (4-0) take precedence over T 4-1 for testingstatus.

Signal I/O
Name

Description

Y 15-0 I/O Data Input/Output. These bidirectional lines are

used to directly load the 16-bit data latch when
OEy is HIGH. When OEy is LOW, the arithmetic unit or the logic unit output data is output on
YIS-O.

Status Register

Instruction Word. This 16-bit word selects the
functions performed by the 7C9116. These lines
are also used to input data when executing Immediate Instructions.
T 4-1 I/O Status Input/Output. These bidirectional pins are
used to output the lower four status bits (OVR,
N, C, and Z) when OET is HIGH. When OET is
LOW, these lines are used as inputs to generate
the conditional test (CT) output.
CT
0 Conditional Test. One of twelve condition code
signals is selected by the condition code multiplexer to be placed on the CT output.
CT = HIGH for a pass condition; CT = LOW
for a fail condition.
OLE
Data Latch Enable. The l6·bit data latch is trans·
parent when OLE is HIGH and latched when
OLE is LOW.
lEN
Instruction Enable. The following occurs with
lEN LOW: Data may be written into the RAM
when the clock is LOW, the Accumulator can
accept data during the clock LOW to HIGH
transition, and the Status Register can be updated
when strn is LOW. If lEN is HIGH, CT is disabled as a function of the instruction inputs. lEN
should be LOW during the fl1'St haIf of the first
cycle of Immediate Instructions.
strn
Status Register Enable. The Status Register is
updated at the end of all instructions except NO·
OP, Save Status, and Test Status when SRE and
lEN are both LOW. The Status Register is inhibited from changing when either strn or lEN are
HIGH.
 operating system is
to software. The UNIX system proves that operating systems can be both simple and useful. Hardware studies sug-

SPARCTM, Sun-4TM, and NFSTM are trademarks of Sun Microsystems, Inc.
UNIX® is a registered trademark of AT&T Bell Laboratories.
VAX@ is a registered trademark of Digital Equipment Corporation.

6-1

II
•

~

Introduction to RISe

~~~NDUcrOR================================================================~
tions for executing complex functions rather than the complex instructions themselves.
Simple, efficient instruction pipeline visible to compilers.
For example, branches take effect after execution of the
following instruction, permitting a fetch of the next instruction during execution of the current instruction.
The real keys to enhanced performance are single-cycle execution and keeping the cycle time as short as possible.
Many characteristics of RISC architectures, such as load/
store and register-to-register design, facilitate single-cycle
execution. Simple fixed-format instructions, on the other
hand, permit shorter cycles by reducing deooding time.
Note that some of these features, particularly pipelining
and high-performance memories, have been used in supercomputer designs for many years. The difference is that in
RISC architectures these ideas are integrated into a processor with a simple instruction set and no microcode.
Moving functionality from run time to compile time also
enhances performance. Functions calculated at compile
time do not require further calculating each time the program runs. Furthermore, optimizing compilers can rearrange pipelined instruction sequences and arrange registerto-register operations to reuse computational results.
A new set of simplified design criteria has emerged:
Instructions should be simple unless there is a good reason
for complexity. To be worthwhile, a new instruction that
increases cycle time by 10% must reduce the total number
of cycles executed by at least 10%.
Microcode is generally no faster than sequences of hardwired instructions. Moving software into microcode does
not make it better, it just makes it harder to modify.
Fixed-format instructions and pipelined execution are
more important than program size. As memory gets cheaper and faster, the space/time tradeoff resolves in favor of
time. Reducing space no longer decreases time.
Compiler technology should use simple instructions to generate more complex instructions. Instead of substituting a
complicated microcoded instruction for several simple instructions, which compilers did in the 1970s, optimizing
compilers can form sequences of simple, fast instructions
out of complex high-level code. Operands can be kept in
registers to increase speed even further.

P=---I

IXCX

S

Compiled programs on RISC machines are somewhat larger than compiled programs on traditional machines, because several simple instructions replace one complex instruction resulting in decreased code density. All SPARC
instructions are 32 bits wide, whereas some instructions on
traditional machines are narrower. But the number of instructions actually executed may not be as great as the
increased program size would indicate. A windowed register file, for example, often simplifies calVretum sequences
so that context switches become less expensive.

CY7C600 Architecture
The SPARC CPU is composed ofa CY7C601 Integer Unit
(IU) that performs basic processing and a CY7C60S Floating-Point Controller (FPC) interface to the CY7C609
Floating-Point Processor that performs floating-point calculations. The CY7C60S/CY7C609 combination acts as a
SPARC compatible Floating-Point Unit (FPU). CY7C600based computers typically have a memory management
unit (MMU), a large virtual-address cache for instructions
and data, and are organized around a 32-bit data and instruction bus.
The integer and floating-point units operate concurrently.
The FPU performs floating-point calculations with a set
number of floating-point arithmetic units. The CY7C600
architecture also specifies an interface for the connection of
an additional coprocessor.

Instruction Categories
The CY7C600 architecture has about 50 integer instructions. CY7C600 instructions fall into seven basic categories:
Load and store instructions (the only way to access memory). These instructions use two registers or a register and a
constant to calculate the memory address involved. Halfword accesses must be aligned on 2-byte boundaries, word
accesses on 4-byte boundaries, and double-word accesses
on S-byte boundaries. These alignment restrictions greatly
speed up memory access.
ArithmeticllogicaVshift instructions. These instructions
compute a result that is a function of two source operands
and then place the result in a register. They perform arithmetic, logical, or shift operations.
Floating-point and coprocessor instructions. These include
floating-point calculations, operations on floating-point
registers, and instructions involving the optional coprocessor. Floating-point operations execute concurrently with
IU instructions and with other floating-point operations
when necessary. This concurrency is transparent to the
progranuner.
Control-transfer instructions. These include jumps, calls,
traps, and branches. Control transfers are usually delayed
until after execution of the next instruction, so that the
pipeline is not emptied every time a control transfer occurs.
Thus, compilers can be optimized for delayed branching.

RISC's Speed Advantage
Using any given benchmark, the performance P of a particular computer is inversely proportional to the product of
the benchmark's instruction count (I), the average number
of clock cycles per instruction (C), and the inverse of the
clock speed (S). Assuming that a RISC machine runs at the
same clock speed as a corresponding traditional machine; S
is identical. The number of clock cycles per instruction (C),
is around 1.3 to 1.7 for RISC machines, and between 4 and
10 for traditional machines. This makes the instruction execution rate of RISC machines about 3 to 6 times faster
than traditional machines. But, because traditional machines have more powerful instructions, RISC machines
must execute more instructions for the same program, typically about 10% to 30% more. Since RISC machines execute 10% to 30% more instructions 3 to 6 times more
quickly, they are about 2 to 5 times faster than traditional
machines for executing typical large programs.
6-2

~

Introduction to RISe
~~~croR ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===

Read/write control register instructions. These include instructions to read and write the contents of various control
registers. Generally the source or destination is implied by
the instruction.
Artificial intelligence instructions. These include the
tagged arithmetic instructions Tagged Add and Tagged
Subtract. Tagged instructions are useful for implementing
artificial intelligence languages such as LISP, because tags
can automatically indicate to software interpreters the data
type of arithmetic operands.
Multiprocessing instructions. These include two instructions for implementing semaphores in memory: Atomic
Load/Store Unsigned Byte which loads a byte from memory then sets the location to all "l's" and SWAP which
exchanges the contents of a register and a memory location. Both of these instructions are "atomic" or uninterruptable.

standards allow users to acquire the most cost-effective
hardware and software in a competitive multi-vendor marketplace. Integrated circuits come from several competing
semiconductor vendors, while software is supplied by systems vendors. This advantage is lost when users are limited
by a processor with proprietary hardware and software.
RISC architectures, and the CY7C600 design in particular,
are easy to implement because they are relatively simple.
Since they have short design cycles, RISC machines can
absorb new technologies almost immediately, unlike more
complicated computer architectures.
CY7C600 systems were designed to support:
The C programming language and the UNIX operating
system,
Numerical applications (using FORTRAN), and
Artificial intelligence and expert system applications using Lisp and Prolog.
Supporting C is relatively easy; most modern hardware architectures are able to do so. The one essential feature is
byte addressability. However, numerical applications require fast floating-point operations and artificial intelligence applications require large address spaces and interchangeability of data types.
The floating-point processor, with pipelined floating-point
operation capabilities, achieves the high performance needed for numerical applications.
For artificial intelligence and expert system applications,
CY7C600 systems offer tagged instructions and word
alignment. Because languages such as Lisp and Prolog are
often interpreted, word alignment makes it easier for interpreters to manipulate and interchange integers and different types of pointers. In the tagged instructions, the two
low-order bits of an operand specify the type of operand. If
an operand is an integer, most of the time it is added to (or
subtracted from) a register. If an operand is a pointer, most
of the time a memory reference is involved. Language interpreters can leave operands in the appropriate registers,
greatly improving the performance of exploratory programming environments.
The CY7C600 architecture does not dictate a memory
management unit (MMU), although a high performance
unit has been specified for the SPARC architecture. The
same processor will be used in different types of machines.
For example, a single-user machine with embedded applications does not need an MMU. By contrast, a multitasking machine used for timesharing, such as a traditional
UNIX workstation, needs a paging MMU. Furthermore, a
multiprocessor such as a vector machine or hypercube requires specialized memory management facilities. The
CY7C600 architecture can be implemented with a different
MMU configuration for each of these purposes, without
affecting user software.

Register Windows
A unique feature contributing to the high performance of
the CY7C600 design is its overlapping register windows.
Results left in registers by a calling routine automatically
become available operands for the called routine, reducing
the need for load and store instructions to main memory.
According to the architectural specification, there may be
anywhere between 2 and 32 register windows, each window
having 24 working registers, plus 8 global registers. The
first implementation has 8 register windows with 24 registers each (but count only 16 since 8 overlap), plus 8 global
registers, for a total of 136 registers. Recent research suggests that register windows and tagged arithmetic, found in
CY7C600 systems, but not in other commercial RISC machines, are sufficient to provide excellent performance for
expert system development requiring AI languages such as
Lisp and Smalltalk.

Traps and Interrupts
The CY7C600 design supports a full set of traps and interrupts. They are handled by a table that supports 128 hardware and 128 software traps. Even though floating-point
instructions can execute concurrently with integer instructions, floating-point traps are precise because the FPU supplies (from the table) the address of the instruction that
failed.

Protection
Some CY7C600 instructions are privileged and can only be
executed while the processor is in supervisor mode. This
instruction execution protection ensures that user programs cannot accidentally alter the state of the machine
with respect to its peripherals.
The CY7C600 design also provides memory protection,
which is essential for smooth multitasking operation.
Memory protection makes it impossible for user programs
to corrupt the system, other user programs, or themselves.

CY7C600 Machines and Other RISC
Machines

An Open Architecture

The CY7C600 design has more similarities to Berkeley's
RISC-I1 architecture than to any other RISC architecture.
Like the RISC-II architecture, it uses register windows in
order to reduce the number of load/store instructions. The
CY7C600 architecture allows 32 register windows, but the

Advantages of Open Architecture
The CY7C600 design is the first open RISC architecture,
and one of the few open CPU architectures. Standard products are more beneficial than proprietary ones, because
6-3

6

~
Introduction to RISe
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~===
initial implementation has 8 windows. The tagged instructions are derived from SOAR, the "Smalltalk On A RISC"
processor developed at Berkeley after implementing
RISC-II.
CY7C600 systems are designed for optimal floating-point
performance, and support single-, double-, and extendedprecision operands and operations, as specified by the
ANSI/IEEE 754 floating-point standard. High floatingpoint performance results from concurrency of the IU and
FPU. The integer unit loads and stores floating-point operands, while the floating-point unit performs calculations. If
an error (such as a floating-point exception) occurs, the
floating-point unit specifies precisely where the trap took
place; execution is expediently resumed at the discretion of
the integer unit. Furthermore, the floating-point unit has
an internal instruction queue; it can operate while the integer unit is processing unrelated functions.
CY7C600 systems deliver very high levels of performance.
The flexibility of the architecture makes future systems capable of delivering performance many times greater than
the performance of the initial implementation. Moreover,
the openness of the architecture makes it possible to absorb
technological advances almost as soon as they occur.

CY7C600 Product Family
Since the CY7C600 has been designed to offer a complete
solution for the implementation of high performance computers and controllers, the family consists of several members including an Integer Unit, a Floating-Point Controller, a Floating-Point Processor, a Cache Controller and
Memory Management Unit, and a Cache Data RAM.
The SPARC processor family consists of a CY7C601 Integer Unit (IU) to perform all non-floating-point operations
and a CY7C608 Floating-Point Controller (FPC) which
interfaces to a CY7C609 Floating-Point Processor to perform floating-point arithmetic concurrent with the IU.
Support is also provided for a second generic coprocessor
interface. The IU communicates with external memory via
a 32-bit address bus and a 32-bit data/instruction bus. In
typical data processing applications, the IU and FPU are
combined with a high performance CY7C604 Cache Controller and Memory Management Unit and a cache memory implemented with CY7Cl57 Cache RAMs. In many
dedicated controller applications the IU can function by
itself with high speed local memory only.

CY7C601 Integer Unit
The IU is the basic processing engine which executes all of
the instruction set except for floating-point operations. The
CY7C601 IU contains a large 136 x 32 triple-port register
file which is divided into 8 windows. Each window contains 24 working registers and has access to the same 8
global registers. A current window pointer (CWP) field in
the Processor State Register keeps track of which window
is currently active. The CWP is decremented when the
processor calls a subroutine and is incremented when the
processor returns.
The registers in each window are divided into ins, outs, and
locals. Each window shares its ins and outs with adjacent
windows. The outs of the previous window are the ins of
the current window, and the outs of the current window
are the ins of the next window. The globals are equally
available to all windows and the locals are unique to each

window. The windows are joined together in a circular
stack where the outs of the last window are the ins of the
first window.
The IU supports a multitasking operating system by providing user and supervisor modes. Some instructions are
privileged and can only be executed while the processor is
in supervisor mode. Changing from' user to supervisor
mode requires taking a hardware interrupt or executing a
trap instruction.
The IU supports both asynchronous traps (interrupts) and
synchronous traps (error conditions and trap instructions).
Traps transfer control to an offset within a table. The base
address of the table is specified by a Trap Base Register
and the offset is a function of the trap type. Traps are taken
before the current instruction causes any changes visible to
the programmer and can therefore be considered to occur
between instructions.

CY7C608 Floating-Point Controller
The CY7C608 Floating-Point Controller (FPC), in combination with a CY7C609 Floating-Point Processor (FPP),
form a SPARC compatible Floating-Point Unit or FPU.
The FPU and CY7C601 IU operate concurrently. The
FPU recognizes floating-point instructions and places them
in a queue while the IU continues to execute non-floatingpoint instructions. If the FPU encounters an instruction
which will not fit in its queue, the FPU holds the IU until
the instruction can be stored.
The FPU contains its own set of registers on which it operates. The contents of these registers are transferred to and
from external memory under control of the IU via floatingpoint load/store instructions. Processor interlock hardware
provides floating-point concurrency which guarantees that
the programming model is preserved from the point of
view of the compiler or assembly language programmer. A
program containing floating-point computations generates
the same resnlts as if instructions were executed sequentially.

CY7C609 Floating-Point Processor
The CY7C609 combines a multiplier and an arithmetic
logic unit in a single microprogrammable VLSI device. The
CY7C609 is capable of operating at the same clock rate as
the Cypress IU and FPC and provides on the order of 4 to
4.9 Megaflops of double precision Linpack floating-point
performance when operated at 33 MHz with these devices.
The CY7C609 is fully compatible with the IEEE standard
for binary floating-point arithmetic, STD 754-1985. The
Floating-Point Processor performs both single and double
precision operations, including division and square root.

CY7C604 Cache Controller and Memory
Managem~nt Unit
The CY7C604 Cache Controller and Memory Management Unit (CMU) provides hardware support for a demand-paged virtual memory environment for the
CY7C601 processor. The CY7C604 conforms to the standard SPARC architecture definition for memory management. Page size is fixed at 4K bytes. The CMU translates
32-bit virtual addresses from the processor into 36-bit
physical addresses and provides both write-through and
buffered copy-back cache policies. The on-chip context register allows support of up to 4096 contexts.
6-4

~

Introduction to RISe
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
High speed address look-up is provided by an on-chip
translation lookaside buffer. Each entry contains the virtual to physical mapping of a 4K byte page. If a virtual address match is detected in one of the TLB entries, the physical address translation contained in that entry will be delivered to the outputs of the CMU. If the virtual address
from the processor has no corresponding entry in the
CMU, the CMU will automatically perform address translation for the virtual address using on-chip hardware to
access a main memory resident three-level page table. Each
"matched" TLB entry is checked for protection violation
automatically and violations are reported to the Integer
Unit as memory exceptions.
The CMU also provides storage for 2048 cache address
tags for a 64K byte cache with a 32 byte line size. The tag
entries can be directly written or read by the processor. In
normal operation, twelve low order bits 15-5 of the virtual
address from the processor are used to select one of the tag
entries in the CY7C604 and its 16-bit contents are compared on chip with the 16 high order processor address bits
to determine if the cache contains the required data or
instruction. This cache hit/miss comparison is then qualified by various built-in protection checks and the result is
output. Pipelined accesses are supported via on-chip registers which capture both address and data from the processor.

CY7C601
INTEGER UNIT

The CY7C604 also contains the logic required in a system
to implement the byte and half-word write capabilities provided in the SPARC instruction set. Cache tag update is
also simplified by an automatic tag update on miss feature
which eliminates the need for processor accesses during tag
update.

CY7C157 Cache Data RAM
The CY7Cl57 16K x 16 static RAMs are designed to interface easily to and provide maximum performance for the
CY7C600 processor. The RAM has registered address inputs and latched data inputs and outputs as well as a selftimed write pulse which greatly simplifies the design of
cache memories for the CY7C601 Integer Unit. The device
has a single clock that controls loading of the address register, data input latches, data output latches, pipeline control
latch, and chip enable register. The chip enable is clocked
into a register and pipelined through a control register to
condition the output enable. This pipelined design allows a
cache that works as an extension of the internal instruction
pipeline of the CY7C601 Integer Unit thereby maximizing
performance. The write enable is edge-activated and selftimed thereby eliminating the need for the user to generate
accurate write pulses in external logic. A separate asynchronous output enable is provided to disable outputs during a write or to allow other devices access to the bus.

CY7C60B
fLOATING-POINT
CONTROLLER

I

I

I

I

2
CY7C157.
CACHE
64K

-

CY7C609
fLOATING-POINT
PROCESSOR

CY7C604
MMU/CACHE
CONTROLLER

I
MAIN MEMORY
(OYNAMIC RAM)

0132-1

Full System Block Diagram

Copyright 1989 by Cypress Semiconductor Corporation and Sun Microsystems, Inc.

6-5

6

PRODUCT DESCRIPTION

CYPRESS
SEMICONDUCTOR

CY7C601

Very High Performance
32-Bit RISe Processor

Features

Overview

• Reduced Instruction Set
Computer (RISe) architecture
- Simple format instructions
- Most instructions execute in
single cycle

• Large virtual address space
- 32·bit virtual address bus
- 8·bit address space identifier
• Hardware Pipeline Interlocks
• Multitasking support
- User/supervisor modes
- Privileged instructions
• Parallel processing support
• Artificial intelligence support
• High performance coprocessor
interface
- Concurrent execution of
floating·point instructions

• Very high performance
- 25 ns instruction cycle with
4·stage pipeline
- 33 Million Instructions Per
Second (MIPS)
- 27 equivalent VAX® MIPS
- 150 ns Interrupt Response
• Large windowed register file
- 136 general purpose 32-bit
registers
- 8 overlapping windows of 24
registers each
- 4 separate register banks

• 0.8 micron CMOS technology
• 207 pin grid array package
• Power 3.3 watts maximum

Block Diagram

The CY7C601 Integer Unit is a high
speed CMOS implementation of the
SPARCTM 32-bit RISC architecture
processor. This architecture makes possible the creation of a processor which
can execute instructions at rates approaching one instruction per processor clock. The CY7C601 supports a
tightly-coupled floating-point coprocessor and a second implementation-definable coprocessor. The CY7C601
SPARC processor provides the following features:

Simple Instruction Format-All instructions are 32 bits wide and are
aligned on 32-bit boundaries in memory. There are only three basic instruction formats which feature uniform
placement of opcode and address fields.

Signal Diagram
DESTINATION

REGISTER FILE
136 X 32

CY7C601
SPARC
Integer Unft

ADDRESS

INSTRUCTION/DATA
0129-2

0129-1

Selection Guide
Maximum Operating
Current (rnA) ICC

I

I

Commercial
Military

7C601·40

7C601-33

7C601·25

650

600

500
500

SPARCTM and SunOS™ are trademarks of Sun Microsystems, Inc.
YAX'" is a registered trademark of Digital Equipment Corporation.
Unix'" is a registered trademark of AT&T.

6-6

PRODUCT DESCRIPTION
CY7C601
~PRESS
~;~MICONDUcrOR ====================================;;;;;;
computations generates the same results as if instructions
were executed sequentially.

Overview (Continued)
Register-Intensive Architecture-Most instructions operate on either two registers or one register and a constant,
and place the result in a third register. Only load and store
instructions access off chip memory.
A Large "Windowed" Register File-The processor has
136 on-chip 32-bit registers configured as 8 overlapping
sets of 24 registers each and 8 global registers. This scheme
allows compilers to cache local values across subroutine
calls, and provides a register-based parameter passing
mechanism.
Delayed Control Transfer-The processor always fetches
the next instruction after a control transfer, and either executes it or annuls it depending on the state of a bit in the
control transfer instruction. This feature allows compilers
to rearrange code to place a useful instruction after a delayed control transfer and thereby take better advantage of
the processor's pipeline.

Registers
The CY7C601 IV contains a large 136 X 32 triple port
register file which is divided into 8 windows, each with
twenty-four working registers, and each having access to
the same eight 32-bit global registers. A current window
pointer (CWP) field in the processor state register (PSR)
keeps track of which window is currently active.
The CWP is decremented when the processor executes a
call to a subroutine and is incremented when the processor
returns.
Previous Window

r(31)

··
··

INS

r(24)
r(23)

Concurrent Floating Point-Floating point instructions
can execute concurrently with each other and with nonfloating point instructions.

LOCALS

r(16)
r(15)

·

Fast Interrupt Response-Interrupt inputs are sampled on
every clock cycle and can be acknowledged in one to three
cycles. The first instruction of an interrupt service routine
can be executed within 6 to 8 cycles of receiving the interrupt request.

r(8)

ActIve Window

r{31 )
OUTS

··
·
··

INS

r(24)
r(23)
LOCALS

r(16)
r(15)

The 7C600 Family

Next Window

r{31 )
OUTS

r{8)

The SPARC processor family consists of a CY7C601 Integer Vnit (IV) to perform all non-floating point operations
and a CY7C608 Floating Point Controller (FPC) which
interfaces to a CY7C608 Floating Point Processor (FPP) to
perform floating point arithmetic concurrent with the IV.
Support is also provided for a second generic coprocessor
interface. The IV communicates with external memory via
a 32-bit address bus and a 32-bit data/instruction bus. In
typical data processing applications, the IV and FPC
(FPC/FPP) are combined with a high performance
CY7C604 Memory Management Vnit and Cache Controller and a cache memory implemented with CY7C157 16K
x 16 Cache RAMs. In many dedicated controller applications the IV can function by itself with high speed local
memory.

··
··
··

INS

r(24)
r(23)
LOCALS

r(16)
r(15)
OUTS

r(8)
r(7)

··

GLOBALS

r{O)

0129-3

The registers in each window are divided into ins, outs, and
locals. The eight global registers are shared by all windows
and appear as registers 0-7 in each window. Registers
8-15 serve as outs, registers 16-23 as locals, and 24-31 as
ins. Each window shares its ins and outs with adjacent
windows. The outs of a previous window are the ins of the
current window, and the outs of the current window are
the ins of the next window. The globals are equally available to all windows and the locals are unique to each window. The windows are joined together in a circular stack
where the outs of window 7 are the ins of window O.

Coprocessor Interface
The IV is the basic processing engine which executes all of
the instruction set except for floating point operations. The
FPC/FPP and IV operate concurrently. The FPC/FPP
recognizes floating point instructions and places them in a
queue while the IV continues to execute non-floating point
instructions. If the FPC/FPP encounters an instruction
which will not fit in its queue, the FPC/FPP holds the IV
until the instruction can be stored. The FPC/FPP contains
its own set of registers on which it operates. The contents
of these registers are transferred to and from external memory under control of the IV via floating point load/store
instructions. Processor interlock hardware hides floating
point concurrency from the compiler or assembly language
programmer. A program containing floating point

Multitasking Support
The IV supports a multitasking operating system by providing user and supervisor modes. Some instructions are
privileged and can only be executed while the processor is
in supervisor mode. Changing from user to supervisor
mode requires taking a hardware interrupt or executing a
trap instruction.

6-7

~

PRODUCT DESCRIPTION

CY7C601

~~~OO~================================================================
3. Control Transfer-Control transfer instructions include
jumps, calls, traps and branches. Control transfer is usually
delayed so that the instruction immediately following the
control transfer (called the delay instruction) is executed
before control is transferred to the target location. The delay instruction is always fetched, however a bit in the control transfer instruction can cause the delay instruction to
be nullified if the branch is not taken. This flexibility increases the likelihood that a useful instruction can be
placed after a control transfer instruction thereby filling an
otherwise unused hole in the processor's pipeline. Branch
and call instructions use program counter relative displacements. A jump and link instruction uses a register indirect
displacement: computing its target address as either the
sum of two registers, or the sum ofa register and a 13-bit
signed immediate value. The branch instruction provides a
displacement of plus or minus 8 megabytes, and the call
instructions 3D-bit displacement allows transfer to almost
any address.

Interrupts and Traps

The IU supports both asynchronous traps (interrupts) and
synchronous traps (error conditions and trap instructions).
Traps transfer control to an offset within a table. The base
address of the table is specified by a Trap Base Register
and the offset is a function of the type of trap. Traps are
taken before the current instruction causes any changes
visible to the programmer and therefore can be considered
to occur "between" instructions.

Instruction Set Summary
Instructions fall into five basic categories:

1. Load and Stolie Instructions-Load and store instructions are the only instructions which access external memory. They use two IU registers or one IU register and a
signed immediate value to generate the memory address.
The instructions destination field specifies either an IU register, a FPC register or a coprocessor register as the destination for a load or the source for a store. Integer load and
store instructions support 8, 16, 32, and 64 bit accesses
while floating point and coprocessor instructions support
32- and 64-bit accesses.

4. Read/Write Control Registers-The processor provides
instructions to read and write the contents of the various
control registers within the machine. These registers include the Multiply Step Register, Processor State Register,
Window Invalid Mask Register, and Trap Base Register.
An instruction is also provided to flush the processor's internal instruction cache.

2. Arithmetic/Logical/Shift-These instructions compute
a result that is a function of two source operands and write
the result into a destination register or discard it. They
perform arithmetic, tagged arithmetic, logical and shift operations. An instruction SETHI, useful in creating a 32-bit
constant in two instructions, writes a 22-bit constant into
the high order bits of a register and zeroes the remaining
bits. The contents of any register can be shifted left or right
any number of bits in one clock cycle as specified by the
instruction itself or by another register. The tagged arithmetic instructions are useful in artificial intelligence applications.

5. Floating Point and Coprocessor Operations-Floating
point operations include floating point calculations and operations on floating point registers. These operations execute concurrently with both IU instructions and with other
floating point instructions whenever possible. Coprocessor
operations are instructions which will be executed by an
optional coprocessor.
The Instruction set of the processor is summarized in Table
1.

Table 1. Instruction Set Summary
Name

Operation

Cycles

LDSB (LDSBA *)
LDSH (LDSHA *)
LDUB (LDUBA *)
LDUH (LDUHA *)
LD(LDA*)
LDD(LDDAO)

Load Signed Byte (from Alternate Space)
Load Signed Halfword (from Alternate Space)
Load Unsigned Byte (from Alternate Space)
Load Unsigned Halfword (from Alternate Space)
Load Word (from Alternate Space)
Load Doubleword (from Alternate Space)

2
2
2

LDP
LDDP
LDPSR

Load Floating Point
Load Double Floating Point
Load Floating Point State Register

2
3
2

LDC
LDDC
LDCSR

Load Coprocessor
Load Double Coprocessor
Load Coprocessor State Register

2
3
2

STB(STBA*)
STH(STHA*)
ST(STAO)
STD(STDA*)

Store Byte (into Alternate Space)
Store Halfword (into Alternate Space)
Store Word (into Alternate Space)
Store Doubleword (into Alternate Space)

3
3
3

6-8

2
2
3

4

Table 1. Instruction Set Summary (Continued)
Name

Operation

Cycles

STF
STDF
STFSR
STDFQ'

Store Floating Point
Store Double Floating Point
Store Floating Point State Register
Store Double Floating Point Queue

3
4
3
4

STC
STDC
STCSR
STDCQ'

Store Coprocessor
Store Double Coprocessor
Store Coprocessor State Register
Store Double Coprocessor Queue

3
4
3
4

LDSTUB (LDSTUBA')
SWAP (SWAPA ')

Atomic Load/Store Unsigned Byte (in Alternate Space)
Swap r Register with Memory (in Alternate Space)

4
4

ADD (ADDcc)
ADDX (ADDXcc)

Add (and modify icc)
Add with Carry (and modify icc)

1
1

TADDcc (TADDccTV)

Tagged Add and modify icc (and Trap on overflow)

I

SUB (SUBcc)
SUBX (SUBXcc)

Subtract (and modify icc)
Subtract with Carry (and modify icc)

1
1

TSUBcc (TSUBccTV)

Tagged Subtract and modify icc (and Trap on overflow)

1

MULScc

Multiply Step and modify icc

1

AND (ANDcc)
ANDN (ANDNcc)
OR (ORcc)
ORN(ORNcc)
XOR(XORcc)
XNOR (XNORcc)

And (and modify icc)
And Not (and modify icc)
Inclusive Or (and modify icc)
Inclusive Or Not (and modify icc)
Exclusive Or (and modify icc)
Exclusive Nor (and modify icc)

I
I
I
I
1
I

SLL
SRL
SRA

Shift Left Logical
Shift Right Logical
Shift Right Arithmetic

1
1
1

SETHI

Set High 22 Bits of r Register

I

SAVE
RESTORE

Save caller's window
Restore caller's window

I
I

Bicc
FBicc
CBccc

Branch on integer condition codes
Branch on floating point condition codes
Branch on coprocessor condition codes

1"
I"
I"

CALL

Call

I"

JMPL

Jump and Link

2"

RETT

Return from Trap

Ticc

Trap on integer condition codes

2"

RDY
RDPSR
RDWIM
RDTBR

Read Y Register
Read Processor State Register
Read Window Invalid Mask
Read Trap Base Register

I
I
1
1

WRY
WRPSR*
WRWIM'
WRTBR'

Write Y Register
Write Processor State Register
Write Window Invalid Mask
Write Trap Base Register

I
I
1
I

UNIMP

Unimplemented Instruction

1

IFLUSH

Instruction Cache Flush

FPop

Floating Point Unit Operations

I to Launch

CPop

Coprocessor Operations

1 to Launch

'privileged instruction
""assuming delay slot is filled with useful instruction

6-9

I (4 if Taken)

1

&:~1,DUcrOR ==========P~'R~O~V~U~C~T~V~E~S~C~'R~I~P~T~'f,~O~N~~C~Y~7~C~6~O~1
Table 2 Pin Table
Pin
Number

Pin Name

Ao

As
A6
A7
A8
A9
AlO
All
Al2
Al3
Al4
AIS
Al6
Al7
Al8
Al9
A20
A21
A22
A23
A24
A2S
A26
A27
A28
A29
A30
A3'

K2
KI
L3
LI
L2
M2
N2
MI
M3
PI
P2
NI
N3
R3
R2
R4
T4
T5
R6
T6
U5
U6
U7
T7
U8
T8
U9
R8
T9
R9
TlO
Ull

Do
D,
D2
D3
D4
Ds
D6
D7
D8
D9
DIO
Dll
D12
Dl3
DI4
D,s
D'6
D17
D'8
DI9
D20
D21
D22

RIO
TIl
Ul2
Tl2
U13
Tl3
Tl4
R13
Ul4
Ul5
RI5
PI5
NI5
MI5
MI6
NI6
Ll5
MI7
LI6
Ll7
KI6
Kl7
J16

Al
A2
A3

A4

Pin
Number

Pin Name
D23
D24
D2S
D26
D27
D28
D29
D30
D31

J17
HI7
HI5
G17
HI6
GI6
FI6
FI5
GI5

ASlo
ASII
ASh
ASI3
ASI4
ASIs
ASI6
ASI7
SIZEo
SIZE,

F3
F2
G2
GI
H2
HI
J1
E2
D2

MEXC
MHOLDA
MHOLDB
BHOLD
AOE
DOE
COE
MDS
MAO
1FT

D8
C8
B8
A7
P3
N17
C2
B7
E3
CI4

RD
WE
LDSTO
I NULL
LOCK
DXFER
WRT

A4
B4
C5
B5
D4

FP
FCCo
FCC,
FCCV
FHOLD
FEXC
CP
CCCa
CCC,
CCCV
CHOLD
CEXC
INST
FLUSH
FINS,
FINS2
FXACK
CINS,

G3

Pin
Number

Pin Name
CINS2
CXACK

C17
C13

1RLo
IRLI
IRL2
1RL3
INTACK
RESET
ERROR
TOE
FPSYN
CLK

AIO
Cll
DlO
BI2
AI3
A9
BI5
CI5
CI2
K3

Vsso

B16
BI7
C3
C4

D6
Dl4
FI
F4
FI4

FI7
H4
12
KI4
NI4
P4
P6
Pll
PI4

Vcco

Al5
AI6
AI7
DI
DI2
D17
EI
G4
K4
KI5

L4
MI4
N4
P8
PI2
PI6
PI7
RI6
R17

VSSI

C7
All
BII
CIO
A8
A5
B6
AI2
B13
BIO
C9
A6

A3
AI4
B2
B3
B9
CI
CI6
D13
EI5
HI4

13
Ll4
M4
P5
P7
RI
Rll
TI
Tl5
UI

VCC!

R7
Rl2
T2
T3
U3
U4

C6
Bl4
El7
Dl6
Dll
Dl5

A2
BI
D7
El4
EI6
Gl4
H3
J15
PIO

VSST

D9
J4

J14
P9

VCCT

D5

P13

D3

E4

6-10

R5
RI4
Tl6
Tl7
Ul6
Ul7

U2
UlO

~
PRODUCT DESCRIPTION
CY7C601
~~~~==========================================================
ABC D ErG H

J

K L MN P R T U

1 0000000000000000
200000000000000000
300000000000000000
400000000000000000
50000
0000
60000
0000
70000
0000
80000
0000
90000
BOTTOM VIEW
0000
100000
0000
110000
0000
120000
0000
130000
0000
1400000000000000000
1500000000000000000
1600000000000000000
1700000000000000000
0129-4

Ordering Information
Oock
Frequency

Ordering Code

(MHz)

Package
Type

Operating
Range
Commercial

40

CY7C601·40GC

G208

40

CY7C601-40BC

B208
G208

33

CY7C601·33GC

33

CY7C601·33BC

B208

25

CY7C601·25GC

G208

25

CY7C601·25BC

B208

25

CY7C601·25GMB

G208

6·11

Military

CY7C602

PRODUCT DESCRIPTION

CYPRESS
SEMICONDUCTOR

RIse Floating-Point Unit

Features
• CombiDes fuDctions of CY7C608
floating-point cODtroller and
CY7C609 floatiDg-point
processor iD a single package

• High performance coprocessor
interface
- CODcurreDt executioD of
integer and floating-point
instructions
- Hardware interlocks
sYDchronize integer and
floating-point operations

• Provides SPARCTM compatible
floatiDg-point arithmetic and
registers
• Very high performance
- 30 DS cycle
- Instructions launched in
single cycle
- 4.2 millioD double precisioD
liDpack floating-point
operations per secoDd

• Meets IEEE standard 754-1985
for single and double precision
formats
• 144 pin grid array package

• 3 deep floating-point queue
stores both iDstructioDs and
addresses to provide precise
exceptioDs

Overview
The CY7C602 Floating-Point Unit
(FPU) is designed to provide a single

ADDRESS

fP

DATA

I

fCCV

Instructlon/Addre.s Buffer
2 X 64

fHOlD
fEXC
TEST

I

INST
flUSH
F'XACK

CY7C602.

flNS 1

floating-Point
Unit

State Register 1
FPP Results

fCC(O_I)

FINS 2

1fP

!

t

chip floating-point solution for the
CY7C601 Integer Unit by integrating
the CY7C609 Floating-Point Processor
(FPP) and CY7C608 Floating-Point
Controller (FPC) into a single device.
The CY7C602 provides high performance SPARC compatible single and
double precision floating-point arithmetic. The FPU performs add, subtract, multiply, divide, square root,
compare, and convert as well as register to register move instructions, floating-point loads and stores, floatingpoint state register, and floating-point
queue store instructions. Instructions
which are unimplemented by the FPU
(extended precision operations) will
cause an Unimplemented FPop trap, in
which case the instruction will be emulated in software.

• 32 x 32 floating-point register
ille

!

!

Floating-Point Queue
3 X 64
ADDRESS INSTRUCTION

I

l

I

I

I

floating-Point
Data
Register File
32 X 32

64-blt
Plpellned
Floating-Point

Processor

H I
Regl.ter
File
Control

MHOlDA
MDS

I

BHOlD
DOE

!

I

fPP
.1
Instruction/Control
Unit

TOE

FP Operand.
fP Instruction

TJ

fP Control

fNUll

0159-1

T T T T
CHOlD CCCV ClK RESET

0159-2

Selection Guide
Maximum Operating
Current (rnA)

I

Commercial

SPARCTM is a trademark of Sun MicrosYitems. Inc.

6-12

7C602-33

7C602-25

TBD

TBD

PRODUCT DESCRIPTION

CYPRESS
SEMICONDUCTOR

CY7C604

Cache Controller and Memory
Management Unit (CMU)

Features

Introduction

• Fully conforms to the SPARCTM
reference Memory Management
Unit (MMU) architecture
• Supports 4096 contexts
• Fixed 4K-byte page size
• On-chip translation lookaside
buffer (TLB)
- 64 fully associative entries
- Multi level flush and probe
support
- Lockable entries
- Random replacement
algorithm

• Sparse address space support
with 3-level map
• 2048 direct mapped cache tag
entries
• Write through and copy-back
cache policies
- 1 32-byte read line buffer
- 1 32-byte write line buffer
•
•
•
•

• Page level protection
• Large address space support
- 32-bit virtual address
- 36-bit physical address

32 byte cache line size
Aliasing detection
Byte write generation
Scalable cache architecture
- Cascadeable
• 0.8 micron CMOS technology
• 244 pin grid array package and
196 plastic quad flatpack

• Hardware table walk

SPARCTM is a trademark of Sun Microsystems, Inc.

The CY7C604 comprises a Cache Tag
and a Memory Management Unit
(CMU). It is a high speed CMOS implementation of the SPARC reference
Memory Management architecture,
Cache Tag, and Cache Controller. The
CY7C604 directly connects to the
CY7C601 processor and CY7Cl57
cache data RAM without any external
circuitry.
The CMU, when combined with two
CY7Cl57 16K x 16 cache RAMs,
forms a complete 64K-byte direct
mapped cache. Cache size can be
scaled. The CMU translates 32-bit virtual addresses from the processor into
36-bit physical addresses. The on-chip
context register allows support of

Signal Diagram
t.AAD(0_63)

CLK

t.AAS

RESET
CSEL

IAERR

A(0-31)

t.ARDY

ASI(0_5)

t.ARTY

D(0-31)
SIZE(O_I)
RD
WE
LDSTO

CY7C604
Cache Controller and
t.Aemory t.Aanagement Unit

IABR
IABG
IABB

INULL

CBWE(0_3)

FNULL

COE

t.AHOLD
lADS
t.AEXC
IOE

Ct.AER
TOE

0157-1

Selection Guide
Maximum Operating
Current (rnA)

I
I

Commercial
Military

6-13

7C604-40

7C604-33

650

600

7C604-25
550

650

600

rI
•

~
PRODUCT DESCRIPTION
CY7C604
~~~OOaoR~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~==
Introduction

translation on the virtual address and store the new mapping into a TLB entry selected by a random replacement
algorithm.

(Continued)

up to 4096 contexts. High speed address translation is provided by a 64-entry fully associative Translation Lookaside
Buffer (TLB). If the CMU processes a virtual address that
matches one of the TLB entries, the physical address contained in that entry will be delivered to the outputs of the
CMU. If the virtual address from the processor has no
corresponding entry in the TLB, the CMU will perform
address translation for the virtual address using a three-level page table map.

TLB Entry Contents
Each entry in the TLB contains a 20-bit Virtual Address
Tag, a 12-bit context field (CXT 11-0), two shorted translation indicator bits (ST!, STO), a 24-bit Physical Page
Number (PPN), a cacheable bit (C), a Modified bit (M),
three access permission bits (ACC 2-0) and a Valid bit
(V).

The CMU supports lockable TLB entries and a random
replacement algorithm. Each matched TLB entry is
checked for protection and privilege violations. If violations occur, these are reported to the 7C60l Integer Unit as
memory exceptions. Each page can be declared as either
cacheable or non-cacheable by using the cacheable "c" bit.

During a TLB look-up, the upper 20 bits of the virtual
address and the context number of the access are compared
with the virtual address and context number fields of each
entry based on the short translation bits in each entry. The
short translation bits are included'in order to provide a
linear address mapping facility of 256K, 16M, or 4G bytes
with a single TLB entry.

The CMU provides 2048 direct mapped cache tag entries.
The cache tag entries and the TLB are searched concurrently for a match with the virtual address. Both writethrough and copy-back cache policies are supported with a
32-byte line size. Address aliasing is checked each time a
cache tag entry is replaced. If the new virtual address is
mapped to the cache line selected for replacement, the
CMU will ignore the main memory access and modify the
cache tag accordingly.

The 24-bit Physical Page Number field contains the higher
order bits of the physical address. This field, when concatenated with the 12-bit byte offset from the virtual address,
forms a complete 36-bit physical address.
The Modified (M) bit of an entry is set whenever the page
has been modified. During page replacement, the operating
system uses this bit to determine whether the selected page
must be copied to secondary storage or not.

The CMU provides on-chip buffer to enhance data transfers between cache memory and main memory: a 32-byte
read buffer and a set of write buffers. In copy-back mode,
the 32-byte write buffer is used to store the modified cache
line being replaced in the cache, allowing the main memory
read to proceed as soon as the memory bus is acquired. The
read buffer stores data from main memory temporarily before it is written into the cache memory. The write buffers
are used in the write through mode to capture address and
data from the IU during write accesses, and allow the IU
to continue processing while the buffer contents are transferred into main memory over the memory bus.

The Cacheable (C) bit determines whether an access associated with that page is cacheable or not. The state of the C
bit in a matched entry is available on the Mbus during the
address phase ofa transaction. If the cacheable bit is set
high, then the entry is cacheable. If this bit is cleared, the
data accessed by the IU will not be written into the cache.
The three Access Permission (ACC 2-0) bits indicate
whether access to the page is allowed for the current transaction. The Address Space Identifier (ASI) from the IU
specifies whether a given access is a data or instruction
reference, and whether it is performed in the supervisor or
user space. Read and write intormation is derived from the
RD and WE inputs.

The memory bus implements the 64-bit Mbus SPARC reference specification. Architecturally, up to 16 CMUs can
be used in the same system to expand the cache tag, cache
size and TLB storage. The CMU is fabricated with Cypress' 0.8 micron CMOS drawn process and is available in
a 196-pin plastic quad fiatpack and a 244-pin ceramic
PGA.

Multiple Contexts
4096 contexts are supported in the CMU via a 12-bit field
in the Context Register (CXR). The context is used by
both the cache tag and the TLB. For supervisor accesses,
if the "S" bit is set the context number comparison is
ignored.

Memory Management Unit
Translation Look-aside Buffer

Fault Reporting

The TLB contains 64 fully associative entries. All entries
are searched simultaneously when a virtual address is presented to the CMU. The virtual tag and the context field
from each entry are compared with the virtual address bits
from the processor and the current context in the Context
Register (CXR), respectively. Ifa match is found in one of
the entries, the physical address field of that entry will be
passed to the Physical Address outputs of the CMU. If no
match is found, the CMU will perform dynamic address

The CMU detects and reports the following faults:

VAT

CXT(ll-O)

PPN

Instruction access error
Data access error
Translation access error
Bus error
Privilege Violation
Protection Violation

M

C

ACC(2-0)

Figure 1. TLB Entry Format

6-14

ST(l-O)

V

EjJ'~
PRODUCT DESCRIPTION
CY7C604
•
.~~=========================
Write Buffer
The write buffers are used in the copy back mode to provide temporary storage for the dirty cache line being replaced while the new line is being transferred from main
memory. Buffering the dirty line speeds up cache miss processing because the IU can be released as soon as the cache
RAMs are updated. The line buffer contents are written
back to main memory only when free memory bus cycles
become available. When the line buffer is full, the cache
controller will wait for it to empty before processing the
cache miss. The same write buffers are used in the writethrough mode to store four double store data. The processor is allowed to continue without waiting for the main
memory update to complete. The buffer contents are written back to main memory whenever the memory bus becomes available.

Memory Management Unit (Continued)
Linear Address Mapping
The 7C604 CMU provides the ability to translate a contiguous virtual address space to a contiguous physical address
space of equal size with a single TLB entry. This function
is achieved by placing a page table entry (Entry Type = 2)
in a location nonnally occupied by a page pointer (Entry
Type = I) such as the context table, the first level page
table, or the second level page table. By replacing a page
pointer with a page entry, the table walk process stops as
soon as the page table entry is encountered. Depending on
where the PTE is placed, 4 mapping sizes are available:
PTE Location

Linear Map Size

Third Level Page Table
Second Level Page Table
First Level Page Table
Context Table

4Kb
256Kb
16Mb
4Gb

Read Buffer
The read buffer is 32 bytes. It is used to hold data being
retrieved from main memory. Since memory bus access begins as soon as a miss is detected, it is likely that the cache
memory will still be busy when the first data from memory
is returned. The read line buffer stores the information
temporarily until the cache RAM is ready to be updllted.

Flush and Probe Operations
Flushing causes the invalidation ofTLB entries while probing returns the phy~ical translation of virtual addresses
generated by the IU. A flush is accomplished by writing to
an alternate address space recognized by the CMU. Flushing can be perfonned on the entire TLB, on matching any
index level in the TLB, or on any context within the TLB.
A probe is accomplished by reading from the same alternate address space. Both flush and probe operation are
word accesses.

Cache Miss Processing
If the physical translation of the missed address is available
in the TLB, then miss processing will commence. Otherwise, the cache controller will wait for the memory management section to retrieve the physical address from the
page tables before starting its actions. The first step in miss
processing is the acquisition of the virtual bus by tri-stating
the IU outputs. Once the control ofthe virtual bus is
achieved, the cache controller is ready to process the cache
miss. If the cacheable (C) bit is set, the cache controller
will transfer data from main memory according to the programmed cache policy and update the cache. If the C bit is
cleared, the cache controller simply transfers data between
the IU and main memory without updating the cache.

Cache TAG and Controller
Cache Operations
The CMU supports both write-through with no write allocate and copy-back with write allocate modes. Two types
of buffers: write buffer and read buffer are provided onchip to enhance cache operations. In write-through mode,
the write buffer is used to store four double store data. In
copy-back mode, the same write buffer is used to hold the
dirty line from cache memory when a line is replaced. A
32-byte read buffer is provided to load data from main
memory.

Non-Cacheable Accesses
During a write operation the IU data will be written into
main memory over the Mbus. During a read operation the
requested data will be read from main memory and presented to the IU via the virtual data bus. The cache tag is
not updated.

Address Synonyms or Aliasing Detection
Virtual addressing allows multiple virtual addresses to map
into the same physical address. Any modification to a virtuallocation may cause data inconsistency in the cache
because the change is not reflected in other cache locations
mapped to the same physical address. Address aliasing is
checked by the CMU whenever a cache line is replaced in
the copy back mode and during read misses in the write
through mode. The physical address of the displaced line is
obtained by passing the virtual tag through the memory
management unit. An alias is detected if the new and the
displaced virtual addresses are mapped to the same physical location. If the miss was caused by a read, no cache
updating is required because the existing line will already
contain the correct data. In this case the tag is simply updated to reflect the new address. If the miss was caused by
a write, the location addressed by the IU will be modified
and the tag is updated to reflect the new address.

Cacheable Accesses
Two cache policies are supported in the CMU. They are
write-through with no write allocate and copy-back with
write allocate.
Write-Through with No Write Allocate
In this mode, all write hits must update both the cache and
main memory. In a write miss, only the main memory is
updated. No address alias checking is perfonned for write
accesses. Protection against aliasing is achieved by invalidating the selected cache line when a write miss is detected.
Upon write misses, the physical translation of the missed
address and the IU data are placed on the physical bus and
a write cycle is initiated. If the miss was caused by a read,
an alias check is perfonned. A new line will be loaded from
main memory if no alias is detected. The physical address

6-15

6

~

PRODUCT DESCRIPTION

CY7C604

~~~~NDUcroR===================================================================
Cache TAG and Controller (Continued)
of the first word in the new cache line is placed on the
Mbus and a burst read cycle is initiated. Each 64-bit word
returning from main memory is temporarily stored in the
read line buffer while the cache RAM is updated 32 bits at
a time. After the last word in the line has been stored in the
cache, the cache controller will drive the missed address on
the virtual address lines and initiate a read. Data returning
from the cache is strobed into the IU via MDS.

initiated. Each 64-bit word returning from main memory is
stored in the read line buffer and driven onto the virtual
data lines 32 bits at a time. Cache update is activated by
asserting the CWE3-CWEo outputs. When the last word
in the cache line is received, the cache controller will update the cache tag with the dirty bit cleared if the miss was
a read or update the cache tag with the dirty bit set if the
miss was a write.

Copy-Back with Write Allocate

Cache Tag

In this mode, a write hit only modifies the data in the
cache. Main memory is updated when a cache line is replaced. A write miss will cause the loading of a new line
from main memory into the cache RAMs. If the tag is
valid, the cache controller will check for aliasing between
the cache line to be replaced and the missed address by
comparing the physical translations of both virtual addresses. The virtual address of the displaced line is obtained by reading the cache tag. If the selected tag entry is
invalid, no alias checking is necessary. An alias is signaled
if both physical addresses match.

The CMU provides 2048 entries of cache tag and status
information. Tag selection is controlled by the 11 address
lines (As-A1S), from the IU. Each entry contains a 12-bit
context field, a 16-bit cache tag field, and a 3-bit status
field. The status field includes the valid (V) bit, the dirty
(0) bit, and a supervisor (8) bit.
The valid bit specifies the validity of the tag entry and the
dirty bit indicates whether the cache line has been modified
or not. The supervisor bit indicates that the tag entry can
only be accessed by the supervisor.
If a copy back cache policy is selected, the dirty bit in the
tag is used by the cache controller to determine whether a
cache line should be copied back to main memory when it
is replaced.

Alias Detected
When an alias is detected, no loading from main memory is
necessary because the cache line selected for replacement is
mapped to the missed address. If the miss was caused by a
read access, data originally requested by the IU is retrieved
from the cache by placing the missed address on the virtual
bus. Information returning on D31-Do is strobed into the
IU in the following clock by the assertion of the MDS
signal. The cache tag is updated to reflect the new address
assignment. If the old cache line was dirty, the tag will be
updated with the dirty bit set, otherwise the tag will be
updated with the dirty bit cleared. If the miss was caused
by a write, the cache location originally addressed by the
processor will be updated with the IU data. After the write
is completed, the cache is updated with the dirty bit set.

Main Memory Interface
The CMU supports a 64-bit synchronous interface with
multiplexed address and dr,ta for main memory access. The
main memory interface has 36 bits of address and 64 bits of
data. The interface is capable of bursting information to
support fast cache line fills.
Byte Write Generation
The CY7C601 processor is capable of accessing bytes, halfwords and words. The CMU decodes the size and access
direction information from the IU and generates the necessary cache write enable signals.

Alias Not Detected
If the two virtual addresses are not mapped to the same
physical location, the state of the dirty bit in the tag entry
selected for replacement will determine whether the cache
line should be copied back to main memory. Contents of
the line buffer are loaded back to main memory using the
burst write feature of the memory bus after the cache miss
has been processed.

Multiple CMU Support
Up to 16 CMUs can be used in a system to increase the
number of tags, TLB entries, and cache size. CMU configuration information is contained in the MMU Control
Register (MCR). Multi-chip address (MCA) field is a 4-bit
address that identifies a particular CMU. The Multi-chip
Mask (MCM) field is a 4-bit code specifying the number of
CMUs in the system. Five configurations: 1,2,4, 8, and 16
CMUs are supported. In order to initialize system configuration, the chip select input of each CMU must be connected to a different address line from the IU.

Loading the New Cache Line
The physical address of the first word in the new line is
placed on the physical bus and a burst read cycle is
Document #: 38-00091

6-16

PRODUCT DESCRIPTION

CYPRESS
SEMICONDUCTOR

CY7C605

Multiprocessor Cache
Controller and Memory
Management Unit (CMU-MP)

Features

Introduction

• Fully compatible with SPARCTM
reference Memory Management
Unit (MMU) architecture

• Scaleable cache architecture
- Cascadeable: 1-16
• Page level protection
• Sparse address space support
with 3-level map

• Multiprocessor support
- Direct data intervention with
and without reflectivity
- Dual cache tag architecture

• Supports write through and
copy-back cache policies
- 1 32-byte read line buffer
- 1 32-byte write line buffer

• Superset of CY7C604 CMU
• Direct mapped cache tag entries
- 2048 virtual tags
- 2048 physical tags

•
•
•
•
•

• Automatic miss processing via
hardware table walking
• On-chip 64 entry translation
lookaside buffer aLB)

Aliasing detection
Fixed 4K-byte page size
32 byte cache line size
0.8 micron CMOS technology
244 pin grid array package

• Supports 4096 contexts

The CY7C605 Multiprocessor Cache
Controller and Memory Management
Unit (CMU-MP) is a high speed
CMOS implementation of the SPARC
reference Memory Management architecture. The CY7C605 directly connects to the CY7C601 processor and
CY7C157 cache data RAM without
any external circuitry to form a complete memory management and cache
subsystem.
Multiple CY7C601, CY7C605 and
CY7C157 subsystems can be used together to achieve higher performance.
The CY7C605 supports a direct data
intervention protocol with and without
reflectivity via the SPARC reference
standard 64-bit Mbus.

Signal Diagram
MAD(0_53)

ClK
RESET
CSEl

MAS

40-31
ASI(0-5)

MRDY
MRTY

0(0-31)

MSH

SIZ~O_I)

MERR

MIH

CY7C605

RD
WE
LDSTO

MBR
MBG
MBB

INULL

CBWE(0_3)

FNULL

COE

tAHOlD
tAOS
tAEXC
IOE

CtAER
TOE

0156-1

Selection Guide
Maximum Operating
Current (mA)

I
1

Commercial
Military

SPARCTM is a trademark of Sun Microsystems, Inc.

Document #: 38-00092
6-17

7C605-25

7C605-40

7C605-33

650

600

550

650

600

6

PRODUCT DESCRIPTION

CYPRESS
SEMICONDUCTOR

CY7C608

RISC Floating-Point Controller

Features
• Provides interface between the
CY7C601 Integer Unit and
CY7C609 Floating-Point Unit
• Provides SPARCTM compatihle
Floating-Point Arithmetic and
registers
• Very high performance
- 30 ns cycle
- Instructions launched in
single· cycle
- 4.2 million double precision
linpack Floating-Point
operations per second
• 32 x 32 Floating-Point Register
File
• 3 deep floating-point queue
stores both instructions and
addresses to provide precise
exceptions

(FPP) to the CY7C601 Integer Unit
(IU). Together, the FPC and FPP provide high performance SPARC compatible single and double precision
floating-point arithmetic. The FPP performs add, subtract, multiply, divide,
square root, compare, and convert;
while the CY7C60SFPC performs register to register move instructions,
floating-point loads and stores, floating-point state register, and floatingpoint queue store instructions. Instructions which are unimplemented by the
FPC (extended precision operations)
will cause an UnimplementedFPop
trap, in which case the instruction will
be emulated in software.

• High performance coprocessor
interface
- Concurrent execution of
Integer and Floating-Point
Instructions
- Hardware Interlocks
synchronize Integer and
Floating-Point Operations

• 1.2 micron CMOS technology

• 299 pin grid array package
• Power 3.3 watts maximum

Overview
The CY7C608 Floating-Point Controller (FPC) is designed to interface the
CY7C609 Floating-Point Processor
SPARCTM is a trademark of Sun Microsystems, Inc.

Block Diagram

Signal Diagram
i - - - - fPP StatUI

ADDRESS

DATA

t

FP
fPP ResuRs

floating-Point
Octo
Register File
32 X 32

!

fCCV

TDA(0-31)
TDB(o-31)
TENR

fHOLD
·FEXC

T1NSTco-al
TSELOP(A_B)

CHAIN

TfAST
TROUND(O_1l

fC~o-I)

TSELMS
TSRCCM

INST
fLUSH
fXACK
fINS,
flNS 2

CY7C608
floating-Point
Controller

CSTAT(0_2)
OSTAT(o_a)

MDS
BHOLD

r - - : : - - ' - - - - - - + f P P Instruction

1Y(o-31)
TE

OOE
TOE

1-------~fPP Control

OlSI-I

TCONflG
TRESET
TOUT

MHOLDB
MHOLDA
'----oZ-.fPP Operands

THALT
TCCLK

T47

fNULL

T1PRES

TTTT

CHOLD CCCV CLK RESET

0131-2

Selection Guide
Maximum Operating Current (rnA)

Commercial
6-18

7C608-33

7C608-25

600

550

~.~
.

, . CYPRESS
,
SEMICONDUCTOR

PRODUCT DESCRIPTION

CY7C608

=================================
Table 1. Floating·Point Instruction Set Summary

Name

Operation

Cycles

LDF
LDDF
LDFSR

Load Floating-Point Register
Load Double Floating-Point Register
Load Floating-Point State Register

2
3
2

STF
STDF
STFSR
STDFQ*

Store Floating-Point
Store Double Floating-Point
Store Floating-Point State Register
Store Double Floating-Point Queue

3
4
3
4

FiTOs
FiTOd
FiTOx
FsTOi
FdTOi
FxTOi

Convert Integer to Single Precision
Convert Integer to Double Precision
Convert Integer to Extended Precision
Convert Single Precision to Integer
Convert Double Precision to Integer
Convert Extended Precision to Integer

8
8
#
8
8
#

FsTOd
FsTOx
FdTOs
FdTOx
FxTOs
FxTOd

Convert Single Precision to Double Precision
Convert Single Precision to Extended Precision
Convert Double Precision to Single Precision
Convert Double Precision to Extended Precision
Convert Extended Precision to Single Precision
Convert Extended Precision to Double Precision

8
#
8
#
#
#

FMOVs
FNEGs
FABSs

Move Single Precision
Negate Single Precision
Absolute Value Single Precision

8
8
8

FSQRTs
FSQRTd
FSQRTx

Square Root Single Precision
Square Root Double Precision
Square Root Extended Precision

15
22
#

FADDs
FADDd
FADDx

Add Single Precision
Add Double Precision
Add Extended Precision

8
8
#

FSUBs
FSUBd
FSUBx

Subtract Single Precision
Subtract Double Precision
Subtract Extended Precision

8
8
#

FMULs
FMULd
FMULx

Multiply Single Precision
Multiply Double Precision
Multiply Extended Precision

8
9
#

FDIVs
FDIVd
FDIVx

Divide Single Precision
Divide Double Precision
Divide Extended Precision

13
18
#

FCMPs
FCMPd
FCMPx
FCMPEs
FCMPEd
FCMPEx

Compare Single Precision
Compare Double Precision
Compare Extended Precision
Compare Single Precision with Exception if Unordered
Compare Double Precision with Exception if Unordered
Compare Extended Precision with Exception if Unordered

8
8
#
8
8
#

* privileged instruction
# currently supported via software emulation only

6-19

~
PRODUCT DESCRIPTION CY7C608
~~~~u~================================================================
Address Bus
8 __

1/0
4

3

2

~

28 27 28

1/0

5

25

o

6

24

1/0
0

VCCI

23

VC02

NC

22

NC

9

21

10

20

0
1/0

o
1/0

11

19
12 13 14 15 16 17 18

0301-1

0301-2

Seleer1on Guide
10E301-4
100E301-4

lOE301-6

3

4

6

-240

-240

10E301-3
100E301-3
Maximum Input to Output Propagation Delay (ns)
lEE (rnA)

I
I

Commercial

8-1

6
170

-240

Military

10E3011.r6
100E3011.r6

~ffiESS
•
W'
nEMlCONDUcrOR

ADVANCED INFORMATION

Maximum Ratings

Operating Range

(Above which the useful life may be impaired. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. For user guidelines, not tested.)
Storage Temperature .................... -65°C to + 150°C
Ambient Temperature with
Power Applied [IJ ••••••••••••••••••••••• -55°C to + USoC

Referenced to V CC at ground

Range

I/O

Temperature

VEE

Commercial
(Standard, "L")

10m

O°C to +75°C
Ambient

-5.2V ± 5%

Commercial
(Standard, "L")

lOOK

O°Cto +85°C
Ambient

-4.5V ± O.3V

Military

Supply Voltage VEE to VCC .............. -7.0 V to +0.5V

CYI0E301
CYIOOE301

10m

Input Voltage ............................. VEE to +0.5V

-55°C to+ 125°C -5.2V ± 5%
Case

Output Current ................................... -50 rnA

Electrical Characteristics
Parameters

Over Operating Range (2J

Description

Temperature [IJ

Test Conditions

TC = -55°C

VaH

'']A = O°C
10m, RL = 50.n to -2V
VIN = VIHMin. orVIL Max. 1A = +25°C
Output HIGH Voltage
1A = +75°C

"It = +l25°C

10E301
Min.

Max.

-1110
-1020
-980
-920
-830

-930

TC = -55°C

VaL

Output LOW Voltage

10m, RL = 50.n to -2V
VIN = VIH Min. or VIL Max.

lA = +75°C
TC = +USoC

-660
-1025

-1950
-1950
-1950
-1950
-1950

-1630
-1630
-1630
-1600
-1570

-1250
-1170
-1130
-1070
-1000

-930

TC= -55°C

\lH

Input HIGH Voltage

10m

lOOK

VIL

Input LOW Voltage

IIH

Input HIGH Current
Input LOW Current

10m

1A =

lOOK
IlL

lEE

Supply Current
(All inputs and outputs
open)

VIN = \lH Max.
VIN = VIL Min. (Except I/O pins)
Commercial "L" (Low Power)
Commercial (Standard Power)
Military

-880

-1620

mV

-1165

-880

mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV

-1810

-1475

mV

220

jJA

-170
-240

IlA
rnA
rnA
rnA

-840
-810
-735
-660
-1480
-1480
-1480
-1450
-1420

O°C to +85°(

220
0.5

0.5
-170
-240
-240

mV
mV
mV
mV
mV
mV

-1810

O°C
+25°C
+75°C
TC = +l25°C
lA = O°C to +85°(
-1950
TC = -55°C
-1950
1A = O°C
-1950
lA = +25°C
-1950
1A = +75°C
-1950
1C = +usoC

Units
mV
mV
mV
mV
mV

-810
-735

lOOK, RL = 50.n to -2V
VIN = VIH Min. or \lL Max. TA= O°Cto +85°C

1A =
1A =
1A =

Max.

-840

lOOK, RL = 50.n to -2V
TA = O°C to + 85°C
VIN = VIH Min. or \lL Max.
']A = O°C
']A = +25°C

100E301
Min.

Notes:
1. Commercial grade is specified asambient temperature with transverse air flow greater than 500 linear feet per minute. Military grade is specified as case
temperature.
2. See AC Test Loads and Waveforms for test conditions.

8-2

~CYPRESS
~nlCONDUCTOR

CYI0E301
CYI00E301

ADVANCED INFORMATION

Capacitance[31
Typ.

Max.

CrN

Input Capacitance

Description

4

10

pF

COUT

Output Capacitance

6

13

pF

Parameters

Min.

Units

Note:

3. Tested initially and after any design or process changes that may affect these parameters.

Switching Characteristics
Parameters

Over Operating Range [21

10E301-3
lOOE301-3

Description

Min.

lOE301-4
lOOE301-4

Max.

Min.

Max.

3.0

lOE301L-6
lOOE301L-6
Min.

Units

Max.

tpo

Input to Output Propagation Delay

6.0

ns

tr

Output Rise Time

0.7

1.5

0.7

1.5

0.7

1.5

ns

tf

Output Fall Time

0.7

1.5

0.7

1.5

0.7

1.5

ns

4.0

AC Test Loads and Waveforms [4.5. e, 7, e, 9]
GND

INPUT
V1H
Vcc. VCC1 • VCC2

Dour

INPUT

\1;E
O.01 IlFJ.

\1;E

RL

V1L

Ie

~~.

11
t,

tf

-2.OV

C301-4
C301-3

Figure 1

Figure 2

Notes:
4. VIL = VIL Min., 'fR = VIR Max. on lOKH version.
5. VIL = -1.7V,VIR = -0.9Von lOOK version.
6. RL = 50 n. C < 5 pF (includes fIxture and stray capacitance).
7. All coaxial cables should be 50 nwith equal lengths. Tbe delay of the
coaxial cables should be "nulled" out of the measurement.

8. t,= tf= 0.7ns.
9. All timing measurements are made from the 50% point of all
waveforms.

Switching Waveforms

INPUT

OUTPUT
0301-5

8-3

II

~CfPRFSS

ADVANCED INFORMATION

~nlcoNDucroR

CYI0E301
CYI00E301

Functional Logic Diagram
INCREMENT-

0

1

2

3

4

5

6

7

8

9

1

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

~~~+-~~+-~~+-~~4-4-~~~~~~~~___~~~----~~23

~>~HH-H~~n=~l=~l=~~~~llt==~<----~~

<

16

9

:>

<

15

10

:>

-<

14

11

:>

-<

13
0301-6

JEDEC fuse number = first fuse number

+ increment

8-4

5J:~NDUCTOR

ADVANCED INFORMATION

CY10E301
CYI00E301

Ordering Information
tpD

I/O

(ns)

lEE
(rnA)

10KH

3.0

240

4.0
6.0

6.0
100K

Ordering Code

CY1OE301-3DC
CYlOE301-3LC

Package
Type

Operating
Range

D14

Commercial

L64

240

CY10E301-4DC

D14
L64

150

CY1OE301-4LC
CY1OE301L-6JC

J64

CY10E301L-6PC

P13A

CY10E301L-6DC

D14

240

Commercial

CY1OE301-6DMB

D14

Military

CYIOE301-6LMB

1.64
D14
1.64

Commercial
Commercial

3.0

240

CYlOOE301-3DC
CYlOOE301-3LC

4.0

240

CYlOOE301-4DC

D14
L64

159

CYIOOE301-4LC
CYIOOE301L-6JC

6.0

Commercial

CYIOOE301L-6PC

J64
P13A

CYIOOE301L-6DC

D14

Document II: 38-A-OOOll

8-5

Commercial

CYIOE302
CYIOOE302

ADVANCED INFORMATION

CYPRESS
SEMICONDUCTOR

Combinatorial ECL 16P4
Programmable Logic Device

Features

Functional Description

• Standard l6P4 pinout and
architecture
- 16 inputs, 4 outputs
- User programmable output polarity
• Ultra high speed/standard power
- tPD = 2.5 ns (max)
- lEE = 220 mA (max)
• Low power version
- tPD
6 ns (max)

Cypress Semiconductor's Pill family
offers the user the highest level of performance in ECL Programmable Logic
Devices. These Pills are developed by
Aspen Semiconductor Corporation, a subsidiary of Cypress Semiconductor, using
an advanced process incorporating proven
Ti-Wfuses.
The CYlOE302 is 10KH compatible and
the CY1OOE302 is lOOK compatible.
These Pills implement the familiar sumof-products logic functions by selectively
programming cell elements to configure
the AND gates by disconnecting either
the true or complement input term. If all
inputs are disconnected from an AND
gate, then a logical true will exist at the
output of this AND gate. An output polarity fuse is also provided to allow an

=

- lEE = 170mA(max)

• Both 10KH and lOOK I/O compatible
versions available
• Enhanced test features
- Additional test input terms
- Additional test product terms
• Security fuse

active LOW to occur if this fuse is blown.
A security feature provides the user protection for the implementation of proprietary logic. When invoked by blowing the
security fuse, the contents of the array
cannot be accessed in the verify mode.
The CYlOE302 and CYIOOE302 can be
programmed using Cypress' QuickPro or
other industry standard programming
equipment. Programming support
information can be obtained from local
Cypress Semiconductor sales offices.

Logic Symbol and Pinout

LCC and PLCC Pinout
() g
z>--

o

VCC2

0

4

3

2

lj

28 27 26
2S

0

24

0

VCC1

23

VCC2

22

NC

9

21

0

10

20

NC

0

11

19
12 13 14 15 16 17 18

C302-1

0302-2

Selection Guide
10E302-2.5
100E302-2.5
Maximum Input to Output Propagation Delay (ns)
lEE (rnA)

I
I

Commercial

10E302-4
100E302-4

10E302-6

2.5

4

6

-220

-220

Military

6
-170

-220

8-6

10E302L-6
100E302L-6

CY10E302
CY100E302

~PRESS

ADVANCED INFORMATION

Maximum Ratings

Operating Range Referenced to Vee at ground

W'nEMICONDUCTOR

(Above which the useful life may be impaired. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. For user guidelines, not tested.)

1/0

Temperature

VEE

Commercial
(Standard, "L")

lOKH

O°C to +7S oC
Ambient

-S.2V ± 5%

Commercial
(Standard, "L")

lOOK

OOCto +85°C
Ambient

-4.SV ± 0.3V

Range

Storage Temperature .................... -6S o C to + 150°C
Ambient Temperature with
Power Applied [I) ••••••••••••••••••••••• -55°C to + 125°C

Military

Supply Voltage VEE to Vcc .............. -7.0 V to +O.SV

lOKH

-55°C to+ 125°C -S.2V ± 5%
Case

Input Voltage ............................. VEE to +O.SV
Output Current ................................... -50 rnA

Electrical Characteristics
Parameters

VOH

VOL

\l:H

Over Operating Range

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

(2)

Temperature [1]

Test Conditions

lOKH, RL = 50 n to -2V
VIN = VIH Min. or VIL Max.

lOOK, RL = 50 n to -2V
VIN = VIH Min. or \l:L Max.

TA = O·C to 8S·C

lOKH, RL = SO n to -2V
VIN = VIH Min. or VIL Max.

TC= -SS·C
TA= O·C
TA= +25·C
TA= +75·C
TC= +125·C

lOOK, RL = SO n to -2V
VIN = VIH Min. or \l:L Max.

TA = O·C to 8S·C
TC=
TA=
TA=
TA=
TC=
1A =
TC=
TA=
TA=
TA=
TC=
TA =

lOKH

lOOK

VIL

Input LOW Voltage

IIH

Input HIGH Current
Input LOW Current

10KH

lOOK
IlL
lEE

Supply Current
(All inputs and outputs
open)

Tr= -SS·C
TA= O·C
TA= +25·C
TA= +7S·C
TC= +125·C

VIN = \l:H Max.
VIN = VIL Min.
Commercial "L" (Low Power)
Commercial (Standard Power)
Military

-SS·C
O·C
+25·C
+7S·C
+l25·C
O·C to 8S·C

-SS·C
O·C
+25·C
+7S·C
+125·C
O·C to 85·C

10E302
Min.

Max.

-1110
-1020
-980
-920

-930
-840
-810

-830

-660

l00E302
Min.

-735

-880

-1810
-930
-840
-810

-1950
-1950
-1950
-1950
-1950

-1480
-1480
-1480
-1450
-1420

-1620

-735

-660
-1165

-880

mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV

-1810

220
0.5

mV
mV
mV
mV
mV
mV

-1630
-1630
-1630
-1600
-1570

-1250
-1170
-1130
-1070
-1000

Units
mV
mV
mV
mV
mV

-1025
-1950
-1950
-1950
-1950
-1950

Max.

-1475

mV

220

JlA
JlA
rnA
rnA
rnA

0.5
-170

-170

-220
-220

-220

Notes:
1. Commercial grade is specified as ambient temperature with transverse air flow greater than 500 linear feet per minute. Military grade is specified as case
temperature.
2. See AC Test Loads and Waveforms for test conditions.

8-7

.r~UCTOR

ADVANCED INFORMATION

CYI0E302
CYI00E302

Capacitance[3]
Typ.

Max.

Input Capacitance

4

10

pF

Output Capacitance

6

13

pF

Min.

Description

Parameters
CIN

COUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.

Switching Characteristics
Parameters
tpD

Units

Over Operating Range [2]

Description

lOE302-2.S
lOOE302-2.S

lOE302-4
lOOE302-4

Min.

Max.

Min.

25
1.5
1.5

0.7

Input to Output Propagation Delay

tr

Output Rise Time

0.7

tf

Output Fall Time

0.7

Max.

lOE302L-6
lOOE302L-6
Min.

4.0
0.7

1.5
1.5

0.7
0.7

Units

Max.

6.0

ns

1.5
1.5

ns
ns

AC Test Loads and Waveforms [4.5.6.7.8.9]
GND

INPUT

::: ----:J2t'---:-,....-----.. ~_~_%

__

-·IJ

INPUT

VeE

IJ~

0.01 ~FJ.

VeE

0302-4

0302-3

Figure 2

Figure!
Notes:
4. VlL = "IL Min., 'fH = "IH Max. on 10KH version.
5. "IL = -1.7V, VIH = -0.9Von lOOK version.
6. RL = 50 C, C < 5 pF (includes fixture and stray capacitance).
7. All coaxial cables should be 50 C with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.

8. tr= tf= 0.7ns.
9. All timing measurements are made from the 50% point of all
waveforms.

Switching Waveforms
V1H

INPUT

V1L
VOH

OUTPUT

VOL

r-,~=*
0302-5

8-8

~W£SS
~Ts~ICONDUcrOR

CYIOE302
CYIOOE302

ADVANCED INFORMATION

Functional Logic Diagram
INCREMENT _

0
1

3

5

6

7

9

10

11

12

13

14

15

16

17

18

~
2

:;>

3

>

4

2

FIRST __ 512
576
FUS E
640
NUMBERS
704

20

21

22

23

24

25

26

27

28

29

30

r--@J Vcc

31

<
<
<

23

22

21

~

544
60S

~~:

768
832 800
896 864
960

19

~o

D--\

~

:~~

1024
1088 1056
11521120
12161184
1248

H}] o

~1>- ~ o

§::l""

1280

2052

a::t

1344 1312
14081376
14721440
1504

~~
<

17

8

>

<

16

9

>

<

15

10

>

<

14

11

:>

<:

.

o

13

C302-6

JEDEC fuse number

~

first [use number

+ increment

8-9

~PR£SS
"'~ICONDUcroR

ADVANCED INFORMATION

CYI0E302
CYIOOE302

Ordering Information
tPD

I/O

(ns)

lEE
(rnA)

lOKH

2.5

220

4.0
6.0

6.0
lOOK

2.5
4.0
6.0

220
150

220
220
220
150

0111ering Code

Package
Type

CYlOE302-25DC

014

CYlOE302-25LC

1.64

CYlOE302-4DC

014

CYlOE302-4LC

1.64

CYlOE302-6JC

J64

CY10E302L-6PC

P13A

CYlOE302L-6DC

014

CY10E302-6DMB

01

CY10E302-6LMB

L64

CY100E302-2.5DC

014

CY100E302-25LC

L64

CY100E302-4DC

D14

CY1OOE302-4LC

L64

CY1OOE302L-6JC

J64

CY1OOE302L-6PC

P13A

CY1OOE302L-6DC

014

Docume\ll #: 38-A-00012

8-10

Operating
Range
Commercial
Commercial
Commercial

Military
Commercial
Commercial
Commercial

CYIOE422
CYIOOE422

ADVANCED INFORMATION

CYPRESS
SEMICONDUCTOR

256 X 4 EeL
Static RAM

• Open emitter output for ease of
memory expansion
• Industry standard pinout

Features
• 256 x 4 bits organization
• Ultra high speed/standard power
- tAA = 3 ns, tABS = 2 ns
- lEE = 220mA
• Low power version
-tAA=5ns
- lEE = ISOmA
• Both IOKH/IOK and lOOK compatible
I/O versions
• On chip voltage compensation for
improved noise margin

compatible. The CY100E422 is lOOK
compatible.
The four independent active LOW block
select (B) inputs control memory selection
and allow for memory expansion and reconfiguration. The read and write operations are controlled by the state of the active LOW write enable (W) input. With
Wand Ex LOW, the corresponding data
at Dx is written into the addressed location. To read W is held HIGH. while 13 is
held LOW. Open emitter outputs allow
for wired-OR connection to expand or
reconfigure the memory.

Functional Description
The Cypress CY10E422 and CY100E422
are 256 x 4 ECL RAMs designed for
scratch pad, control and Buffer Storage
applications. These RAMs are developed
by Aspen Semiconductor Corporation, a
subsidiary of Cypress Semiconductor.
Both parts are fully decoded random
access memories organized as 256 words
by 4 bits. The CYlOE422 is 1OKH/10K

Logic Block Diagram

Pin Configurations
D3
A4
A3
A2
A1
Ao
VEE

Ao

a:

A1

a:

A3
A4

W

~

0

~

A2

A7
A6
As

W

0

8
W

0

~

I

I

D2

I
I
I

«

08

MEMORY CELL ARRAY

I
I
I

I
I
I

tij t5 oJ; >

I
I
I

..,
d' 1£0

32t!J242322

O2
82
D1
D2

a:

21
20

7

19
18

W 8

17

As

W

4
S
6

9

16
1011 1213 141S

J'.t:W.£«

C422-1

LCe
TOP VIEW

C422-4

Selection Guide
Maximum Access Time (ns)
Commercial
lEE Max. (rnA)
"L" (Low Powe!l

I
I

lOE422-3
lOOE422-3
3
-220

IOE422-5
lOOE422-S
5

-220
-150

8-11

IOE422-7
lOOE422-7
7
-150

0422-3

·

~,~
. CYPRESS

ADVANCED INFORMATION

~ SEMICONDUCTOR
Maximum Ratings

Operating Range

(Above which the useful life may be impaired. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. For user guidelines, not tested.)

Range

referenced to VCC

I/O

Commercial
lOKH/lOK
(Standard, "L")

Storage Temperature .................... -65°C to + 150°C
Ambient Temperature with
Power Applied ......................... -55°C to + 125°C

Commercial
(Standard, "L")

CYIOE422
CYIOOE422

lOOK

Ambient
Temperature

VEE

O°C to 75°C

-5.2V ± 5%

O°C to 85°C

-4.5V ± O.3V

Supply Voltage VEE to VCC ............... -7.0 to +0.5V
Input Voltage ............................. VEE to +0.5V
Output Current ................................... -50 rnA

Electrical Characteristics
Parameters

VOH

VOL

VIH

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Temperature I']

Min.

Max.

Units

Th = O°C
lOEl2]RL = 50 n to -2V
TA = +25°C
VEE= -5.2V
VIN = VIHMax.orVILMin. TA = +75°C

-1000
-960
-900

-840
-810
-735

mV
mV
mV

WOK RL = 50 n to -2V
VEE= -4.5V
TA = O°C to 85°C
VIN = VIH Max. or VIL Min.

-1025

-880

mV

TA = O°C
WE RL = 50 n to -2V
VEE= -5.2V
TA = +25°C
VIN = VIH Max. or VIL Min. TA = +75°C

-1870
-1850
-1830

-1665
-1650
-1625

mV
mV
mV

WOK RL = 50 n to -2V
TA = O°C to 85°C
VEE= -4.5V
VIN = VIHMax.orVILMin.

-1810

-1620

mV

-1170
-1130
-1070
-1165
-1950
-1950
-1950
-1810

-840
-810
-720
-880
-1480
-1480
-1450
-1475
220
170

mV
mV
mV
mV
mV
mV
mV
mV

Test Conditions

TA =
TA =
TA =
TA =
TA =
TA=
1A =
TA =

WE
VEE = -5.2V
WOK VEE = -4.5V

VIL

Input LOW Voltage

WE
VEE = -5.2V

IIH

Input HIGH Current

lOOK VEE = -4.5V
VIN = VIH Max.

r---=="

O°C
+25°C
+75°C
O°C to 85°C
WC
+25°C
+75°C
O°C to 85°C

B inputs
All other inputs

IlL

Input LOW Current

lEE

Commercial "L" (Low Power)
Supply Current
(All inputs and outputs open) Commercial Standard

YiN = YiL Min.

0.5
-50

~A
~A
~A

-150
-220

rnA
rnA

Notes:
1. Commercial grade is specified as ambient Temperature with transverse air flow greater than 500 linear feet per minute.
2. 10E specifications support both 10K and 10KH compatibility.

Capaci tance IS]
Parameters

Description

Min.

Typ.

Max. 14]

Units

CIN

Input Capacitance

4

5

pF

COUT

Output Capacitance

6

8

pF

Notes:
3. Tested initially and after allY design or process changes that may affect these parameters.
4. For all packages except Cerdip (D40) which has maximums of C'N = 10 pF, COUT = 12 pF.

8-12

C!lPRE&"
~

CYIOE422
CYIOOE422

ADVANCED INFORMATION

SEMICONDUcrOR

AC Test Loads and Waveforms [5,6,7,8, g, 101
GND
INPUT
1H

Voo

V

1L

Dour

INPUT

-11--~80%

VeE
0.01 IlF

J.

•..;;2;,;,.0,;,,;%_ _

____

tr

tl
0422-6

VeE
Figure 2

Figurel
Notes:

5,

'k

6. "IL

=

8. All coaxial cables should be 50 n with equal lengths. The delay ofthe
coaxial cables should be "nulled" out of the measurement.
9. tr = tf = 0.7 os.
10. All timing measurements are made from the 50% point of all

"IL Min., '1H = "IH Max. on 10E version.

= -1.7V, "IH = -0.9Von lOOK version.

7. RL = 50 n, C < 5 pF (3 ns grade) or < 30 pF (5, 7 ns grade)
(includes fIXture and stray capacitance).

wavefonns.

Switching Characteristics
Parameters

Over Operating Range

Description

lOE422-3
lOOE422-3
Min.

Max.

10E422-5
lOOE422-5
Min.

Max.

lOE422-7
lOOE422-7
Min.

Units

Max.

tABS

Block Select to Output delay

20

3.0

4.0

ns

tRBS

Block Select Recovery

2.0

3.0

4.0

ns

tAA

Address Access Time

3.0

5.0

7.0

ns

tw
twSD

Write Pulse Width

3.0

3.0

5.0

ns

Data Setup to Write

0.5

1.0

1.0

ns

tWHD

Data Hold to Write

0.5

1.0

1.0

ns

tWSA

Address Setup/Write

0.5

1.0

1.0

ns

tWHA

Address Hold/Write

0.5

1.0

1.0

ns

twsBS

Block Select Setup/Write

0.5

1.0

1.0

ns

twHBS

Block Select Hold/Write

0.5

1.0

1.0

tws

Write Disable

2.0

3.0

4.0

twR

Write Recovery

3.5

tr

Output Rise Time

0.7

1.5

0.7

2.5

1.0

2.5

ns
ns
ns
ns

tf

Output Fall Time

0.7

1.5

0.7

2.5

1.0

2.5

ns

6.0

8-13

8.0

· .
fiA
.

ADVANCED INFORMATION

CYPRESS

_

SEMICONOUCfOR

CYIOE422
CYIOOE422

Switching Waveforms
Read Mode

P----------------

tABs;t

Q

20%

0%

t,
0422-7

ADDRESS

===~~~_-_-:_~
__L.l_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_t-AA~:-_:~-_:~-_:~-_:~-_:~-_:~-_:~-_:~-_:*~..-I-,...-_-~~~~~~~~~

Q

0422-8

Write Mode

-;;:;),
ADDRESS

D

)i~50%

50%~

'"

50%}

50%)

(

K

50%*

tWHD
t WSD

~ r50%

I---- tWSA
Q

tw

50%/ '{:
i---tWHA t WHBS

/~

t WSBS
~tws

tWR
0422-9

8-14

"-'~PRESS
f'EMICONDUCTOR

ADVANCED INFORMATION

Truth Table
Inputs

Bx
H
L
L
L

Outputs

w

n.

Q.

Mode

X
L
L
H

X
H
L
X

L
L
L
Out

Disabled
Write "H"
Write "L"
Read

Ordering Information
I/O

lEE
(mA)

10E[11]

220

lOE

lOOK

lOOK

150

220

150

tAA
(ns)

Ordering Code

Package
Type

Operating
Range

1.63
1.63

Commercial

3.0

CYlOE422-3LC

5.0

CYlOE422-SLC

5.0

CYlOE422-SDC

D40

5.0

CYI0E422L-SLC

1.63

5.0

CYlOE422L-SDC

D40

7.0

CYlOE422L-7LC

1.63

7.0

CYlOE422L-7DC

D40

3.0

CY100E422-3LC

1.63

5.0

CY100E422-SLC

L63

5.0

CY100E422-SDC

D40

5.0

CY100E422L-SLC

L63

5.0

CYlooE422L-SDC

D40

7.0

CY100E422L-7LC

1.63

7.0

CYl00E422L-7DC

D40

Commercial

Commercial

Commercial

Note:
11. 10E specifications support both 10K and 10KH compatibility.
Document #: 38-A-00002

8-15

CYI0E422
CYIOOE422

CYIOE474
CYIOOE474

ADVANCED INFORMATION

CYPRESS
SEMICONDUCTOR
Features
• 1024 lit 4 bits organization
• Ultra high speed/standard power
- tAA = 3 ns, tACS = 2 ns
- lEE
275mA
• Low power version
-tAA=5ns
- lEE = 190mA
• Both 10KH/IOK and lOOK compatible
I/O versions
• On chip voltage compensation for
improved noise margin

=

• Open emitter output for ease of
memory expansion
• Industry standard pinout

Functional Description
The Cypress CYlOE474 and CY1OOE474
are 1K x 4 ECL RAMs designed for
scratch pad, control and Buffer Storage
applications. These RAMs are developed
by Aspen Semiconductor Corporation, a
subsidiary of Cypress Semiconductor.
Both parts are fully decoded random
access memories organized as 1024 words

Logic Block Diagram
Ao

A1

1024 X 4 EeL
Static RAM
by 4 bits. The CY10E474 is lOKHJlOK
compatible. The CY100E474 is lOOK
compatible.
.
The active LOW chip select (8) input
controls memory selection and allows for
memory expansion. The read and write
operations are controlled by the state of
the active LOW write enable (W) input.
With Wand S LOW, the data at D(l-4)
is written into the addressed location. To
read W is held HIGH, while S is held
LOW. Open emitter outputs allow for
wired-OR connection to expand the
memory.

Pin Configurations
A2

VCCA

A3

Voo

0 3
0 4
Ao
A1
A2
A3
A4
As

O2
0 1
04
03
02
01

A6

VEE

A5

S
W
As
As
A7

VEE

0 3
0 4
Ao
A1
A2

W
Ag
As
A7

Q1

Vee
VCCA

S

NC

A4

O2
03
04
0 1
O2

As

NC
As
A4
A3

0474-2

0474-3

'"
ca~~O'o

As
A7

32!!l242322

As
As
0(1-4)

S

Ao
A1
A2
A3
A4
As

4

21

5

20

6
7
8

19
18
17
16

S

10 11 12 13 141S
CD w ,... co OJ
z

MODULES

~~~~~~~~~~.

MILITARY

~~~~~~~~~~.

BRIDGEMOS

II

-.::::IIIr ,

QUICKPRO

~~~~~~~~~~~~'iIl'.

PLD TOOLKIT §§§§§§§§§§§§§§§§§§~.fII
QUALITY AND
RELIABILITY

§§~~~~~~~~4I'DI

APPLICATION BRIEFS ~~~~~~~§§I9I

~

Section Contents

~~~~================================================================
BridgeMOS

Page Number

BridgeMOS Overview .................................................................................. 10-1

Device Number

Description

CY8C150
CY8C245
CY8C291
CY8C901
CY8C909
CY8C911

BridgeMOS 1024 x 4 Static RAM Separate I/O .................................. 10-1
BridgeMOS 2048 x 8 Reprogrammable Registered PROM ......................... 10-1
BridgeMOS Reprogrammable 2048 x 8 PROM .................................. 10-1
BridgeMOS 4-Bit Slice ....................................................... 10-1
BridgeMOS Microprogram Sequencer .......................................... 10-1
BridgeMOS Microprogram Sequencer .......................................... 10-1

BridgeMOS

CYPRESS
SEMICONDUCTOR
Features

Overview

• May be driven by CMOS or

The BridgeMOSTM product line from
Cypress Semiconductor provides an
electrical bridge between CMOS and
TTL or TTL and CMOS devices.
BridgeMOS devices may be driven by
either TTL or CMOS devices and in
turn can drive either fully loaded TTL
or CMOS to full input levels. As a result, any combination of TTL and/or
CMOS may be interfaced to Cypress
BridgeMOS products.
All devices in the BridgeMOS product
line are specified at a 2.0V (Vcd
standby mode of operation. This allows
the device to be powered at 2.0 volts
and maintain the integrity of the data
in any volatile storage element.

TIL

• Drives fully loaded TTL
- Inputs switch at 1.SV
• Can drive CMOS to full input
levels
- VOL = 0.2V @ IOL = 20
/kA
- VOH = 0.9 Vee @ IOH =
-20/kA
• SRAM, PROM, LOGIC
• 2.0V (Vee) Data Retention on
all devices

The output drivers in the 7CXXX Cypress products are designed for TTL
signals and pull up to 2.4 volts. For

BridgeMOS, Cypress has designed an
output driver which boosts the output
voltage sufficiently to drive the inputs
of a device to greater than 3.85 volts,
thus guaranteeing that the input converter will draw minimum power. The
output drivers source 20 microamps at
their rated BridgeMOS levels. They
will also source and drive normal TTL
loads. Therefore, they are capable of
driving other non-BridgeMOS loads
and normal TTL loads at the same
time.
Although the TTL to CMOS input
converters power down as described
above, they switch at TTL levels and
all timing is referenced to 1.5 volts. The
device will operate at normal TTL levels with no AC performance degradation.

CY8C150 Selection Guide
Maximum Access
Time (ns)
Maximum Operating
Current (mA)

Commercial

8C150-15

8C150-25

8C150-35

15

25

35

25

35

100

100

100

125

125

Military
Commercial
Military

CY8C245 Selection Guide
8C245-35
Maximum Access Time (ns)
Maximum Operating
Current (mA)

I
I

8C245·45

35

50

Commercial

45

45

Military

80

80

8C291·35

8C291·50

CY8C291 Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)

I
I

35

50

Commercial

45

45

Military

80

80

10-1

~

BridgeMOS

~~~~NOOaoR================================================================
CY8C901 Selection Guide
Part Number

Operating Icc (max.) in mA

Operating Range

31

26.5

Commercial

SC901·31

32

31.0

Military

8C901-32

Read Modify·Write Cycle (min.) in ns

CY8C909/8C911 Selection Guide
8C909·30
8C911·30

8C909·40
8C911·40

Minimum Clock to Output Cycle Time (ns)

30

40

Maximum Operating Current (mA)

15

15

10·2

PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS

,.
FII
•

LOGIC

III

RISC

[II

MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO
PLDTOOLKIT
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
PACKAGES

•
•

m

QuickPro
Page Number

Device Number

Description

CY3000

Combined PROM, PLD, and EPROM Programmer .............................. 11-1

CY3000

CYPRESS
SEMICONDUCTOR

QuickPro™

Features
• Combined PROM, PLD, and
EPROM programmer
• Programs Cypress CMOS PLDs
and PROMs
• Reads bipolar PLDs and
PROMs
• Easy to use, menu·driven
software
• New device updates via floppy

disk
• IBM·PO") plug.in card format,
external ZIF·DIP socket

Description
• Compatible with the IBM PC
family of computers and plug
compatibles
• Programs 24· and 2S·pin NMOS
and CMOS EPROMs
• One long slot and 256K bytes of
memory required
• Designed for present and future
NMOS and CMOS devices
• Optional LCC, PLCC, SOIC
socket adapters

QuickPro is a development tool for
present and future CMOS PROM and
PLD devices, and is used within the
IBM PC and compatible environment.
Older generation bipolar PLDs and
PROMs required special programming
voltages and current difficult to generate within the IBM PC.
QuickPro is designed for new generation of CMOS PLDs and PROMs
which obsolete the older technology,
and use a programming technique

m

QuickPro is a trademark of Cypress Semiconductor Corporation.
IBM and IBM PC are registered trademarks of International Business Machines Corporation.
ABELTM is a registered trademark of Data I/O Corporation.
CUPLTM is a registered trademark of Assisted Technology.
P ALASMTM is a registered trademark of Monolithic Memories Inc.
Intellec 86TM is a trademark of Intel Corporation.

11-1

0095-1

~

CY3000

~~~~======================================================~~
Memory
Description (Continued)

256K bytes oftotal memory is sufficient to operate QuickPro.

which is more compatible with low cost programming
methods.
QuickPro can also program standard NMOS and CMOS
EPROMs in packages up to 28 pins. And QuickPro is fast;
intelligent programming is used to reduce programming
time to a minimum.
QuickPro is future oriented. Each I/O pin is fully programmable, allowing the parameters and timing of each
device to be handled via software. As new devices become
available, they will be supported by QuickPro. Updates are
managed by a simple exchange of floppy disks.
QuickPro includes a comprehensive set of commands to
make programming PLOs and PROMs as easy as possible.
For PLOs, QuickPro uses the JEOEC standard data format, so present and future logic design tools such as
ABELTM, CUPLTM, and PALASMTM can be used.
QuickPro avoids serial download problems from a PC to a
stand-alone programmer. For PROMs, QuickPro reads
Intellec 86™, Motorola S, TEK and space format files.
QuickPro also reads and writes PROM PCOOS binary
files for use with assemblers and compilers. QuickPro is
low cost. Each workstation can have one, eliminating the
inconvenience of sharing one expensive programmer. All
actions are menu-driven, with complete explanations provided on-screen, in clear text. There is no need to look up
manufacturer's codes in a table.

Devices Supported
Cypress CMOS PROMs:
CY7C225, CY7C235, CY7C245, CY7C245A,
CY7C251, CY7C254, CY7C261, CY7C263,
CY7C264, CY7C268, CY7C269, CY7C271,
CY7C274, CY7C277, CY7C279, CY7C281,
CY7C282, CY7C291, CY7C291A, CY7C292,
CY7C292A, CY7C293A
Cypress CMOS PLOs:
PALCI6L8, PALCI6R4, PALCI6R6, PALCI6R8,
PALC22VI0, PLOC20GlO, PLOC20RAlO,CY7C330,
CY7C331, CY7C332
QuickPro can read 20 and 24 pin Bipolar PLOs, for conversion to Cypress PLOs.
EPROMs: (NMOS and CMOS)
2716,2732, 2732A, 2764, 2764A, 27128, 27256,27512

Ordering Information
CY3000
CY3001
CY3002
CY3003

QuickPro System ($995.00) contains:
QuickPro Board
QuickPro Pod
QuickPro System Disc
Quick Pro Manual
Optional QuickPro Package Adaptors Include:
CY3004 (CY3006) 28 Lead Square (P)LCC:*
7C225, 7C235, 7C245, 7C261, 7C263, 7C264, 7C281,
7C282, 7C291, 7C292, PALC22VI0
CY3005 (CY3007) 20 Lead Square (P)LCC:
16L8, 16R4, 16R6, 16R8
CY3008 (CY3009) 28 Lead Square (P)LCC:
7C269, 7C271, 7C330, 7C331, 7C332
CY3010 (CY3011) 28 Lead Square (P)LCC:
PLOC2OGI0
CY3012 (CY3013) 32 Lead Rectangular (P)LCC:
7C268

QuickPro Commands
Program device
Select device type
Edit memory
~isplay memory
Change PROM
memory location
Read device
Test PLO device
Read disk file

Write disk file
Verify device
Blank check device
Program security fuse
Fill memory
Convert PLO type
Summary display

Technical Information
Size

CY3014 28 Pin SOIC:
7C225, 7C235, 7C245, 7C251, 7C254, 7C261, 7C263,
7C264, 7C269, 7C271, 7C281, 7C282, 7C291, 7C292
CY3015 32 Pin SOIC:
7C268
CY3016 32 Pin DIP:
7C268
CY3017 (CY3018) 28 Lead Square (P)LCC:
7C251,7C254

IBM PC standard full length card. Selectable port addresses 300-31F, 320-33F, 340-35F, 360-37F hex.

Power
+5V
+ 12V
-12V

1.0 amp
1.0 amp (peak) 0.4 amp average
0.05 amp

SocltetPod
This is the external socket for connection to the device to
be programmed or read. It provides a 28-pin 300/600 mil
socket for compatibility with a wide range of devices. Other adapters for leadless packages are also available. Five
filter switches are located on the pod for bypass capacitors
according to manufacturers' published programming specifications.

·Switch Settings
A = PALC22VI0,B

11-2

= PROMs

PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO
PLDTOOLKIT
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
PACKAGES

,.

•
•
•
•
•,.

i .•

B

~

Section Contents

~~~~========================================================
PLDToolKit

CY3l0l

Page Number
Programmable Logic Design Tool ............................................. 12-1

CY3101

CYPRESS
SEMICONDUCTOR

PLD ToolKit

Features

Description

• Logic Assembler, Reverse
Assembler

The Cypress PLD ToolKit is a sophisticated programmable logic design tool
for supporting the Cypress family of
programmable logic products. The
ToolKit includes the ability to assemble a logic source file, interactively perform logic simulation on the result, and
write a standard JEDEC output file for
programming the PLD. In addition,
JEDEC files may be read, simulated
and reverse assembled, creating source
files that may be modified and reassembled.
The PLD ToolKit runs on any standard IBM PC®, AT®, 386 or compatible Personal Computer with a CGA,
EGA, VGA or Hercules display. The
ToolKit features mouse, keyboard or
command line interface and supports
Logitech™ and Microsoft® mouse

• Concise easy to use syntax
• JEDEC read/write capability
• Integrated Waveform Logic
Simulator
• Mouse Driven Simulation Editor
• Integrated menu oriented user
interface
• Mouse, keyboard, command line
interface
• CGA, EGA, VGA, Hercules
support
• Supports all Cypress PLDs

compatibility. Command line control is
provided for assembly from a source
file to JEDEC file or disassembly of a
JEDEC file to a source file.
The language contains syntax that allows the management of programmable
logic device macrocells in all possible
configurations, as well as default conditions that provide concise source files.
In addition, there are language constructs called connectives that provide
expressions for connecting any product
term to a macrocell.
The ToolKit Simulator features waveform entry, multiple views and multisegment simulation. The Simulator
provides the capability to specify initial
design conditions, and "View Nodes"
may be created and used to probe internal nodes in the device.

0160-1

IBM and IBM PC, AT are registered trademarks of International Business Machines Corporation.
LogitechTM is a trademark of Logitech, Inc.
Microsoft'" is a registered trademark of Microsoft Corporation.

12-1

..sfjiII"~

•

.

CY3101

~NDUcroR===================================================================

PLD ToolKit Command Menus
Options
Simulation Colors

Mouse Test
If no response, then check Provides the ability
mouse installation
to test Mouse Interface
Supports
Logitech and Microsoft
ESCAPE

Menu Colors
JEDEC Brief/Annotate
G Fuse (JEDEC Security):
ON/OFF
Working Directory Path 0

Command Menu

Assemble
Disassemble

Invokes Assembles
Invokes Disassembler

WriteJEDEC
ReadJEDEC

Writes JEDEC Output File
Reads JEDEC File into PLD
ToolKit
Invokes Simulator
Selects Option Menu
Selects System Information
Menu
Resets ToolKit

Simulate
Options
Information
Clear
ESCAPE
Information
Release Number
Release Date
Serial Number
Free Memory

Selects Simulation Colors
Menu
Selects Menu Color Menu
Toggles JEDEC Annotated or Brief Listing
Toggles Security Fuse
Sets Path to Working Directory

ESCAPE
Simulation Colors
Background
Input Trace
Output Trace
Name of Pin or Node
Pin or Node Background
Trace Selected
Selected Trace Background

Information about the PLD
ToolKit for registration purposes

Allows the selection of
colors for the Simulator
Display

Memory
512K bytes of total memory is required to operate the PLD
ToolKit.

Devices Supported

Screen Size
Colors
ESCAPE

CYPALl6R8, CYPALI6R6, CYPALl6R4, CYPALl6L8,
CYPAL22VIO, CYPLD2OGlO, CY7C330, CY7C33I

Ordering Information
CY3101 Cypress PLD ToolKit Levell contains:
Two 5'14" Floppy Disks
One 3 '/." Floppy Disk
One Manual
One Registration Card

12-2

PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO
PLDTOOLKIT
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
PACKAGES

•
,•.•
•
•
•
•
•III

I'.

~

Section Contents

~ fE~~~UaoR==========================================================

Quality and Reliability

Page Number

Quality, Reliability and Process Flows ..................................................................... 13-1

CYPRESS
SEMICONDUCTOR

Quality, Reliability and Process Flows
4) SMD (Standard Military Drawing) approved product;
Military operating range: - 55°C to + 125°C, electrically tested per the applicable Military Drawing.
5) JAN qualified product; Military operating range:
-55°C to + 125°C, electrically tested per MIL-M38510 slash sheet requirements.
Category I, 2, and 3 are available on all products offered
by Cypress Semiconductor. Category 4 and 5 are offered
on a more limited basis, dependent upon the specific part
type in question.

Corporate Views on Quality and
Reliability
Cypress believes in product excellence. Excellence can only
be defined by how the users perceive both our product
quality and reliability. If you, the user, are not satisfied
with every device that is shipped, then product excellence
has not been achieved.
Product excellence does not occur by following the industry norms. It begins by being better than one's competitors,
with better designs, processes, controls and materials.
Therefore, product quality and reliability are built into every Cypress product from the start.
Some of the techniques used to insure product excellence
are the following:
• Product Reliability starts at the initial design inception.
It is built into every product design from the very start.
• Product Quality is built into every step of the manufacturing process through stringent inspections of incoming materials and conformance checks after critical process steps.
• Stringent inspections and reliability conformance
checks are done on finished product to insure the finished product quality requirements are met.
• Field data test· results are encouraged and tracked so
that accelerated testing can be correlated to actual use
experiences.

Commercial Product Assurance Categories
Commercial grade devices are offered with two different
classes of product assurance. Every device shipped, as a
minimum, meets the processing and screening requirements of level 1.
Levell: For commercial or industrial systems where the
demand for quality and reliability is high, but
where field service and device replacement can be
reasonably accomplished.
Level 2: For enhanced reliability applications and commercial or industrial systems where maintenance is
difficult and/or expensive and reliability is paramount.
Devices are upgraded from Level 1 to Level 2 by
additional testing and a bum-in to MIL-STD-883,
Method 1015.
Table 1 lists the 100% screening and quality conformance
testing performed by Cypress Semiconductor in order to
meet the requirements of these programs.

Product Assurance Documents
Cypress Semiconductor uses MIL-STD-883C and MIL-M385IOH as baseline documents to determine our Test
Methods, Procedures and General Specifications for semiconductors.
Customers using our Commercial and Industrial grade
product receive the benefit of a military patterned process
flow at no additional charge.

Military Product Assurance Categories
Only one standard product assurance category exists for
JAN, SMD and Military grade products. Cypress' military
grade devices are processed per MIL-STD-883C using
methods 5004 and 5005 to define our screening and quality
conformance procedures. The processing performed by
Cypress results in a product that meets the class B screening requirements as called out by these methods. Every
device shipped, as a minimum, meets these requirements.
JAN, SMD and Military grade devices supplied by Cypress
are processed for applications where maintainance is difficult or expensive and reliability is paramount. Tables 2
through 6 list the screening and quality conformance testing that is performed in order to meet the processing requirements required by MIL-STD-883C and MIL-M38510.

Product Testing Categories
Five different testing categories are offered by Cypress:
1) Commercial operating range product: O"C to + 70"C.
2) Industrial operating range product: -4O"C to + 85°C.
3) Military Grade product processed to MIL-STD-883C;
Military operating range: - 55°C to + 125°C.

13-1

IJ

~

Quality, Reliability and Process Flows

~r~~============~=====
Table 1. Cypress Commercial and Industrial Product Screening F1ows-Components

Product Temperature Ranges
Screen

Commercial O"C to

MIL-STD-883 Method

+ 70"C; Industrial -

Plastic
VisuallMechanicai
• Internal Visual
• High Temperature Storage
• Temperature Cycle
• Constant Acceleration
• Hermeticity Check:
Fine/Gross Leak
Bum·in
• Pre·Bum·in Electrical
• Bum·in
• Post-Burn-In Electrical
• Percent Defective
Allowable (PDA)
Final Electrical
• Functional, Switching,
Dynamic (AC) and
Static (DC) Tests
Cypress Quality
Lot Acceptance
• External Visual
• Final Electrical
Conformance
• Fine & Gross Leak
Conformance

2010
0.4%AQL
1008, CondC
Not Performed
1010, CondC
Not Performed
2001, Cond E,Yl
Does Not Apply
Orientation
1014, Cond A & B; Fine Leak
Does Not Apply
Cond C; Gross Leak
Per Device Specification
1015
Per Device Specification

Per Device Specification
I) At 25·C and Power
Supply Extremes
2) At Hot Temperature and
Power Supply Extremes

+ 85"C

4O"C to

Levell

Level 2
Hermetic

Plastic

Hermetic

100%
100%
Not Performed

0.4%AQL
Not Performed
Not Performed

100%
100%
Not Performed

Not Performed
LTPD = 5;
77(1,2)

Does Not Apply Not Performed
Does Not Apply

LTPD = 5;
77(1,2)

Does Not Apply Does Not Apply
Does Not Apply Does Not Apply
Does Not Apply Does Not Apply

100%
100%[2]
100%

100%
100%[2]
100%

Does Not Apply Does Not Apply

5% (max)U]

5% (max)U]

Not Performed

Not Performed

100%[1]

100%[1]

100%

100%

100%

100%

2009

[3]

[3]

[3]

[3]

Cypress Method 17-00064

[3]

[3]

[3]

[3]

LTPD = 5;
77(1,2)

Does Not Apply

LTPD = 5;
77(1,2)

1014, Cond A & B; Fine Leak
Does Not Apply
Cond C; Gross Leak

Table la. Cypress Commercial and Industrial Product Screening Flows-Modules
Product Temperature Ranges
Screen
Bum·in
• Pre-Burn-in Electrical
• Bum-in
• Post-Bum-In Electrical
• Percent Defective
Allowable (PDA)
Final Electrical
• Functional, Switching,
Dynamic (AC) and
Static (DC) Tests
Cypress Quality
Lot Acceptance
• External Visual
• Final Electrical
Conformance
• Fine & Gross Leak
Conformance
Notes:

MIL·STD-883 Method

Commercial O·C to

- 4O"C to

+ 85·C

Level 2

Does Not Apply
Does Not Apply
Does Not Apply

100%
100%
100%

Does Not Apply

15%

Not Performed

100%

100%

100%

Per Cypress Module Specification

Per Cypress Module Specification

[3]

[3]

Does Not Apply

Does Not Apply

Per Device Specification
1015
Per Device Specification

Per Device Specification
1) At 25·C and Power
Supply Extremes
2) At Hot Temperature and
Power Supply Extremes

2009

+ 70"C; Industrial

Levell

Cypress Method 17-00064
1014; Cond A & B; Fine Leak
Cond C; Gross Leak

I) Electrical Test is performed after bum-in. Results oftbis are used to
determine PDA percentage.
2) Bum-in is performed as a standard for 12 hours at 150"C.

3) Lot acceptance testing is performed on every lot to guarantee 200
PPM average outgoing qUality.

13-2

Table 2. Cypress JAN/SMD/Military Product Screening Flows
Screen
VisuallMechanical
- Internal Visual
- Stabilization Bake
(No End Pt. Electricals)
- Temperature Cycling
- Constant Acceleration
- Hermeticity
-Fine Leak
-Gross Leak
Burn-in
- Initial (pre-Burn-in)
Electrical Parameters
- Bum-in Test

- Interim (post-Burn-in)
Electrical Parameters,
Percent Defective
Allowable (PDA)
Final Electrical Tests
-StaticTests

- Dynamic and Switching
Tests
- Functional Tests

Quality Conformance Tests
-GroupA
- GroupB
-GroupC
-GroupD

Product Temperature Range: -55°C to

Screening Per
Method 5004 of
MIL-STD-883C

+ 125"C

JAN

SMD/Military
Product

Militury Grade
Module

Method 2010, Cond B
Method 1008, 24 Hrs
Cond C, Minimum
Method 1010, Cond C
Method 2001, Cond E (Min),
Y1 Orientation Only

100%

100%

N/A

Method 1014, Cond A & B
Method 1014, Cond C

100%

100%

N/A

100%

100%

Optional

100%

100%

N/A

100%
100%

100%
100%

N/A
N/A

100%

100%

100%

100%

100%

100%
(48 Hours at 125°C)

100%

100%

100%
(PDA 10%)

Method 5005, Table 1,
Subgroups 1,2 and 3

100% Test to
Slash Sheet

Method 5005, Table 1,
Subgroups 4, 5, 6, 9,
10 and 11
Method 5005, Table 1,
Subgroups 7 and 8

100% Test to
Slash Sheet

100% Test to
Applicable Device
Specification
100% Test to
Applicable Device
Specification
100% Test to
Applicable Device
Specification

100% Test to
Applicable
Specification
100% Test to
Applicable
Specification
100% Test to
Applicable
Specification

Sample
Sample
Sample
Sample

Sample
Sample
Sample
Sample

Per Applicable Device
Specification
Method 1015, 160 Hrs
at 125°C Min or
80 hours at 150"C
Per Applicable Device
Specification
Maximum PDA, for
All Lots, 5%

100% Test to
Slash Sheet

Method 5005, See
Table 3-6 for
Details

Sample
Sample
Sample
Sample

13-3

~

Quality, Reliability and Process. Flows

CYPRESS

~~~~~========================================~~:;~~~~~

Group C tests for SMD and Military products are performed on one device type from one inspection lot representing each technology. Sample tests are performed per
MIL-STD-883 from each twelve months production of devices, which is based upon the lot inspection identification
(or date) codes.
End-point electrical tests and parameters are performed
per detailed device specification.

Table 3. Group A Test Descriptions
Cypress uses an LTPD sampling plan that was developed
by the Military to assure product quality. Testing is performed to the subgroups found to be appropriate for the
particular device type. All Military products have a Group
A sample test performed as outlined by the particular
screen flow.
Subgroup

Sample SizelAccept No.

Description

Components

1

Static Tests at 25°C

116/0

2

Static Tests at
Maximum Rated
Operating Temperature

116/0

77/1
55/1

1

55/1

2

Static Tests at
Minimum Rated
Operating Temperature

116/0

4

Dynamic Tests at 25°C

116/0

5

Dynamic Tests at
Minimum Rated
Operating Temperature

116/0

77/1
55/1

6

Dynamic Tests at
Minimum Rated
Operating Temperature

116/0

55/1

7

Functional Tests at 25°C

116/0

8

Functional Tests at
Minimum and Maximum
Temperatures

116/0

77/1
55/1

9

Switching Tests at 25°C

116/0

10

Switching Tests at
Maximum Temperature

116/0

Switching Tests at
Minimum Temperature

116/0

3

11

Subgroup

Modules

Description

77/1
55/1

Sub·
group

55/1

Modules

4/0

4/0

2

Resistance to Solvents,
Method 2015

3

Solderability,
Method 2003

10

10/0

5

Bond Strength,
Method 2011

15

NIA

Steady State Life Test, End
Point Electricals, Method 1005
Metbod
Temp Cycling
1010
Constant Acceleration 2001
Hermeticity Fine
1014
Visual Inspection
M+l
End Point Electrical
M+l

5

15/2

NIA

15/2

Table S. Group C Quality Tests
Group C tests for JAN product are performed on one device type from one inspection lot representing each technology. Sample tests are performed per MIL-M-38510
from each three months production of devices, which is
based upon the lot inspection identification (or date) codes.

134

Description

QuantityI Accept '"
orLTPD
Components

Modules

1

Physical Dimensions,
Method 2016

15

15/2

2

Lead Integrity, Seal:
Fine & Gross Leak,
Methods 2004 & 1014

15

15/2

3

Thermal Shock, Temp
Cycling, Moisture
Resistance, Seal: Fine
& Gross Leak, Visual
Examination, End-Point
Electricals, Methods
1011, 1010, 1004 & 1014

15

15/2

4

Mechanical Shock,
Vibration - Variable
Frequency, Constant
Acceleration, Seal:
Fine & Gross Leak,
Visual Examination,
End-Point Electricals,
Methods 2002, 2007,
2001 & 1014

15

15/2

QualityI Accept'" or LTPD
Components

Components Modules

Table 6. Group D Quality Tests (package Related)
Group D tests for JAN product are performed per MILM-38510 on each package type from each six months of
production, based on the lot inspection identification (or
date) codes.
Group D tests for SMD and Military product are performed per MIL-STD-883 on each package type from each
twelve months of production, based on the lot inspection
identification (or date) codes.
End-point electrical tests and parameters are performed
per detailed device specification.

Table 4. Group B Quality Tests
Group B testing is performed for each inspection lot. An
inspection lot is defined as a group of material of the same
device type, package type and lead finish built within a six
week seal period and submitted to Group B testing at the
same time.
Sub·
group

LTPD

Description

~
Quality, Reliability and Process Flows
~~~~==================================~============================
Table 6. Group D Quality Tests (Package Related)
(Continued)

Subgroup
5

6

Description
Salt Atmosphere,
Seal: Fine & Gross
Leak, Visual Examination, Methods
1009 & 1014
Internal Water-Vapor
Content; 5000 ppm
maximum @ l00"C.
Method 1018

Military Product

• Product processed per MIL-STD-883C, method 5004
product test flows
• Military grade devices electrically tested to:
- Cypress datasheet specifications
OR
- SMD (Standard Military Drawing) devices electrically tested to military drawing specifications
OR
- JAN devices electrically tested to slash sheet specifications
• All devices supplied in Hermetic packages
• Quality conformance assured: Method 5005, Groups A,
B, C and D performed as part of the standard process
flow
• Bum-in performed on all devices
- Cypress detailed circuit specification for non-JAN devices
OR
- Slash sheet requirements for JAN products
• AC, DC, Functionally and Dynamically tested at 25°C
as well as temperature and power supply extremes on
100% of the product in every lot
• JAN product manufactured in a DESC certified facility

Quantity/Accept #
orLTPD
Components Modules
15

15/2

3/0 or 5/1

N/A

7

Adhesion of Lead
Finish,H]
Method 2025

15

15/2

8

Lid Torque,
Method 2024[2)

5/0

N/A

Note.:
I) Does not apply to leadless chip carriers.
2) Applies only to packages with glass seals.

Product Screening Summary
Commercial and Industrial Product

Ordering Information

• Screened to either Levell or Level 2 product assurance
flows
• Hermetic and Molded packages available
• Incoming Mechanical and Electrical performance guaranteed:
- 0.1 % AQL Electrical Sample test performed on every
lot prior to shipment
- 0.65% AQL External Visual Sample inspection
• Electrically tested to Cypress datasheet

JAN Product:
• Order per Military document
• Marked per Military document
Ex: JM3851O/2890lBVA
SMD Product:
• Order per Military document
• Marked per Military document
Ex: 5962-868460lEA
Military Grade Product:
• Order per Cypress standard Military part number
• Marked the same as ordered part number
Ex: CY7C122-25DMB

Ordering Information
Product Assurance Grade: Level 1
• Order Standard Cypress part number
• Parts marked the same as ordered part number
Ex: CY7C122-l5PC, PALC22VlO-25PI
Product Assurance Grade: Level 2
• Bum-in performed on all devices to Cypress detailed circuit specification
• Add "B" Suffix to Cypress standard part number when
ordering to designate Bum-in option
• Parts marked the same as ordered part number
Ex: CY7C122-15PCB, PALC22Vl0-25PIB

Military Modules
• Military Temperature Grade Modules are designated
with a 'M' suffix only. These modules are screened to
standard combined flows and tested at both Military
temperature extremes.
• MIL-883C Equivalent Modules are processed to proposed JEDEC standard flows for MIL-883C compliant
modules. All 883C equivalent modules are fully compliant 883C components.

13-5

Il

Product Quality Assurance Flow-Components
AREA PROCESS

'"

PROCESS DETAILS

QC

INCOMING MATERIALS
INSPECTION

ALL INCOMING MATERIALS ARE INSPECTED TO DOCUMENTED PROCEDURES COVERING
THE HANDLING, INSPECTION, STORAGE, AND RELEASE OF RAW MATERIALS USED IN
THE MANUFACTURE OF CYPRESS PRODUCTS. MATERIALS INSPECTED ARE: WAFERS,
MASKS, LEADFRAMES, CERAMIC PACKAGES AND/OR PIECE PARTS, MOLDING
COMPOUNDS, GASES, CHEMICALS, ETC.

FAB

DIFFUSION/ION
IMPLANTATION

SHEET RESISTANCE, IMPLANT DOSE, SPECIES AND CV CHARACTERISTICS ARE
MEASURED FOR ALL CRITICAL IMPLANTS AND ON EVERY PRODUCT RUN. TEST
WAFERS MAY BE USED TO COLLECT THIS DATA INSTEAD OF ACTUAL PRODUCTION
WAFERS. IF THIS IS DONE, THEY ARE PROCESSED WITH THE STANDARD PRODUCT
PRIOR TO COLLECTING SPECIFIC DATA. THIS ASSURES ACCURATE CORRELATION
BETWEEN THE ACTUAL PRODUCT AND THE WAFERS USED TO MONITOR IMPLANTATION.

FAB

OXIDATION

SAMPLE WAFERS AND SAMPLE SITES ARE INSPECTED ON EACH RUN FROM VARIOUS
POSITIONS OF THE FURNACE LOAD TO INSPECT FOR OXIDE THICKNESS. AUTOMATED
EQUIPMENT IS USED TO MONITOR PIN HOLE COUNTS FOR VARIOUS OXIDATIONS IN
THE PROCESS. IN ADDITION, AN APPEARANCE INSPECTION IS PERFORMED BY THE
OPERATOR TO FURTHER MONITOR THE OXIDATION PROCESS.

FAB

PHOTOLITHOGRAPHY /
ETCHING

APPEARANCE OF RESIST IS CHECKED BY THE OPERATOR AFTER THE SPIN OPERATION.
ALSO, AFTER THE FILM IS DEVELOPED, BOTH DIMENSIONS AND APPEARANCE ARE
CHECKED BY THE OPERATOR ON A SAMPLE OF WAFERS AND LOCATIONS UPON EACH
WAFER. FINAL CD'S AND ALIGNMENT ARE ALSO SAMPLE INSPECTED ON SEVERAL
WAFERS AND SITES ON EACH WAFER ON EVERY PRODUCT RUN.

FAB

METALIZATION

FILM THICKNESS IS MONITORED ON EVERY RUN. STEP COVERAGE CROSS-SECTIONS
ARE PERFORMED ON A PERIODIC BASIS TO INSURE COVERAGE.

FAB

PASSIVATION

AN OUTGOING VISUAL INSPECTION IS PERFORMED ON 100% OF THE WAFERS IN A
LOT TO INSPECT FOR SCRATCHES, PARTICLES, BUBBLES, ETC. FILM THICKNESS IS
VERIFIED ON A SAMPLE OF WAFERS AND LOCATIONS WITHIN EACH GIVEN WAFER ON
EACH RUN. PINHOLES ARE MONITORED ON A SAMPLE BASIS WEEKLY.

FAB

QC VISUAL OF
WAFERS

FAB

E-TEST

SAMPLE ELECTRICAL TEST IS PERFORMED FOR FINAL PROCESS ELECTRICAL
CHARACTERISITICS ON EVERY RUN.

FAB

QC MONITOR OF
E-TEST DATA

WEEKLY REVIEW OF ALL DATA TRENDS; RUNNING AVERAGES, MINIMUMS,
MAXIMUMS, ETC. ARE REVIEWED WITH PROCESS CONTROL MANAGER

TEST

WAFER PROBE/SORT

VERIFY FUNCTIONALITY, ELECTRICAL
CHARACTERISTICS, STRESS TEST DEVICES

TEST

QC CHECK
PASS/FAIL LOT BASED ON YIELD,
PROBING AND
CORRECT PROBE PLACEMENT
ELECTRICAL TEST
RESULTS
TO ASSEMBLY
AND TEST

(Continued)

13-6

0032-1

~

Quality, Reliability and Process Flows

~~~~==================================~==========~~~~~==~
Product Quality Assurance Flow-Components (Continued)

PLASTIC
ASSEMBLY
FLOW

HERMETIC
ASSEMBLY
FLOW

WAFER PREP /MOUNT /SAW
INSPECT FOR ACCURATE SAWING OF
SCRIBELINE AND 100% SAW THRU
PERIODIC QC MONITOR - WAFER SAW
PERFORM MONITOR OF MOUNTING, SAWING
AND POST SAW CLEAN OPERATIONS
DIE VISUAL INSPECTION
INSPECT DIE PER CYPRESS EQUIVALENT TO
MIL-STD-883, METHOD 2010
QC VISUAL LOT ACCEPTANCE
SAMPLE INSPECT DIE; 1.0% AQL
DIE ATIACH
ATIACH PER CYPRESS DETAILED SPECIFICATION
QC PROCESS MONITOR
INSPECT FOR DIE POSITION, QUALITY AND
UNIFORMITY OF DIE ATIACH AND ATIACHMENT
STRENGTH, MIL-STD-883, METHOD 2010, CRITERIA
WIRE BOND
BOND PER CYPRESS DETAILED SPECIFICATION
QC PROCESS MONITOR - WIRE BONDING
MONITOR BOND STRENGTH AND
FAILURE MODE
INTERNAL VISUAL INSPECTION
LOW POWER (30X) INSPECTION OF WORKMANSHIP
MIL-STD-883, METHOD 2010, CRITERIA
QC LOT ACCEPTANCE
SAMPLE INSPECT LOT TO VERIFY WORKMANSHIP,
MIL-STD-883, METHOD 2010, CRITERIA; 0.4% AQL
DIE COAT
COATING APPLIED TO SELECTED PRODUCTS
MOLD / ENCAPSULATE PLASTIC DEVICES
SEAL HERMETIC DEVICES

PERIODIC QC MONITOR, LID-TORQUE
SHEAR STRENGTH OF GLASS-FRIT
SEAL TESTED TO MIL-STD-883, METHOD 2024

(Continued)

13-7

0032-2

~

Quality, Reliability and Process Flows

~~~==========~~=====
Product Quality Assurance Flow-Components (Continued)

POST MOLD CURE
PER CYPRESS METHOD
FOR MOLDING COMPOUND

STABILIZATION BAKE
METHOD 1008, COND C
TEMPERATURE CYCLE(I)
METHOD 1010, COND C
CENTRIFUGE(! )

METHOD 2001, COND E, Yl ORIENTATION
FINE AND GROSS LEAK TESr<2)
PER METHODS EQUIVALENT TO METHOD
1014, COND A OR B; FINE LEAK
METHOD 1014, COND C; GROSS LEAK
LEAD TRIM / FORM
LEAD TRIM AND FORM FOR PLASTIC DEVICES, LEAD
TRIM FOR HERMETIC DEVICES (WHERE APPLICABLE)
LOT 10 - PLASTIC DEVICES
MARK WAFER LOT ON DEVICES; LASER MARK ON
PLASTIC DEVICES
LEAD PREP / FINISH (SOLDER DIP)
PREPARE LEADS FOR SOLDER DIP, SOLDER DIP DEVICES
AND INSPECT FOR UNIFORM SOLDER COVERAGE
QC PROCESS MONITOR
VERIF'Y WORKMANSHIP AND SOLDER COVERAGE
LOT 10- HERMETIC DEVICES
MARK WAFER LOT ON DEVICES
FINE AND GROSS LEAK SAMPLE TESr<2)
METHOD 1014, COND A OR B; FINE LEAK
METHOD 1014, COND C; GROSS LEAK
EXTERNAL VISUAL INSPECTION
INSPECT FOR WORKMANSHIP, CONSTRUCTION, CRACKED
OR BROKEN DEVICES, BENT LEADS, CRAZING, CASTELLATION
ALIGNMENT AND SOLDER COVERAGE.
MIL-STD-883, METHOD 2009
0032-3

(Continued)

13-8

~
Quality, Reliability and Process Flows
~~~~==================================~======================~
Product Quality Assurance Flow-Components (Continued)
OPTIONAL BURNIN PROCESSING FOR LEVEL 2
(STANDARD FOR JAN/MILITARY DEVICES)

0,,

0,,

PRE - BURNIN ELECTRICAL TEST

,

,

0,,

0,,

BURNIN: METHOD 1015

,

0,,

,

0,,

QC MONITOR - BURNIN DOCUMENTS/RESULTS

,

,

0,,
,,
,

0,,

INTERIM (POST-BURN IN) ELECTRICALS
PER APPLICABLE DEVICE SPECIFICATION

k>
,,
,

QC INSPECTION
PDA VERIFIED WITHIN LIMITS

,,
,

~,,
:.

FINAL ELECTRICAL TEST
100% TEST LOT; DC, AC, FUNCTIONAL AND DYNAMIC
TESTS PERFORMED PER APPLICABLE DEVICE SPECIFICATION
FINAL DEVICE MARKING
FINAL VISUAL INSPECTION
INSPECT FOR BENT LEADS, MARKING,
SOLDER COVERAGE, ETC.

IQC LOT ACCEPTANCE I
VIS L SAMPLE INSPECTION
METHOD 2009 -0.65% AQL
ELECTRICAL SAMPLE TEST
TO GUARANTEE 200 PPM
INSPECTION - PRE-SHIPMENT
CONFIRM PART TYPE, COUNT, PACKAGE, CHECK
FOR COMPLETENESS OF PROCESSING
REQUIREMENTS, CONFIRM SUPPORTING
DOCUMENTATION IS SENT, IF REQUIRED
PACK / SHIP ORDER

0032-4

o
o
IQI

<>

Key
PRODUCTION PROCESS

II

TEST / INSPECTION
PRODUCTION PROCESS AND TEST INSPECTION
QC SAMPLE GATE AND INSPECTION
0032-5

Notes:
\. Temp Cycle and Centrifuge performed per Applicable Product Screening Flow.
2. JAN/SMDlMilitary grade products are 100% Fine and Gross Leak tested and sample tested after wafer lot I.D. Commercial grade devices received
sample test only. Sample size is per Commercial Product Screening Flow.

13-9

~

Quality, Reliability and Process Flows

~~~ocroR~~~~~~~~~~~~~~;;~~~;;~~~~====
Product Quality Assurance Flow-Modules
ALL INCOt.lING t.lATERIALS ARE INSPECTED TO DOCUt.lENTED PROCEDURES COVERING THE HANDLING, INSPECTION, STORAGE, AND
RELEASE OF RAW t.lATERIALS USED IN THE t.lANUFACTURE OF CYPRESS
PRODUCTS. t.lATERIALS INSPECTED ARE: SUBSTRATES, ACTIVE DEVICE
PACKAGES, CHIP CAPACITORS, LEAD F"RAt.lES, SOLDER PASTE, INKS,
CHEt.lICALS, ETC.

INCOt.lING t.lATERIALS
INSPECTION

KIT PICKED
COt.lPLIANCE VERIFIED, DOCUMENTED,
AND TRACEABILITY ESTABLISHED
CLEAN
PREASSEt.lBLEY CLEANING OF"
COt.lPONENTS
SOLDER PASTE DEPOSITION
SCREEN PRINTED AND/OR DISPENSED
PER DETAILED SPECIFICATION
COt.lPONENT PLACEMENT
ROBOTIC AND/OR t.lANUAL PER DETAILED
SPECIFICATION
SOLDER REFLOW
MICROPROCESSOR CONTROLLED INFRARED
REFLOW OVEN
DATA LOGGING
CLEAN
(OPTIONAL)

0

--

FLUX REt.lOVAL BY VAPOR PHASE PER
DETAILED SPECIFICATION
DOUBLE SIDED ASSEMBLY
REPEAT PROCESS FOR SIDE 2

--,
0

2-SIDED
AQL VISUAL

l-SIDED

0

COt.lPONENT PLACEt.lENT

I§J

I

I§J

SOLDER REFLOW

I

I

100~

VISUAL

l-SIDED

I

I

--!--

r--

SOLDER PASTE DEPOSITION

I

0
0

2-SIDED

0
0
I

CLEAN

-<>

AQL VISUAL

INSPECT

100~ VISUAL

0 --! -I

ELECTRICAL TEST
(PRE-BURNIN TEST)

0032-6

13-10

~
Quality, Reliability and Process Flows
~~~NDUcrOR ======================================================================
Product Quality Assurance Flow-Modules (Continued)

OPTIONAL BURNIN PROCESSING FOR
LEVEL 2 (STANDARD FOR MIL DEVICES)

o
o
o
I
I

BURNIN: METHOD 1015

I
I
I

QC MONITOR - BURNIN DOCUMENTS/RESULTS

I
I
I

INTERIM (POST - BURNIN) ELECTRICALS
PER APPLICABLE DEVICE SPECIFICATION

I
I

____ j---O

QC INSPECTION
PDA VERIFIED
WITHIN LIMITS

FINAL ELECTRICAL TEST
100% TEST LOT; DC, AC, FUNCTIONAL AND
DYNAMIC TESTS PERFORMED PER APPLICABLE
DEVICE SPECIFICATION
FINAL DEVICE MARKING

FINAL VISUAL INSPECTION
CONFIRM PART TYPE, COUNT, PACKAGE, CHECK
FOR COMPLETENESS OF PROCESSING REQUIREMENTS, CONFIRM SUPPORTING DOCUMENTATION IS SENT, IF REQUIRED
QA ELECTRICAL TEST
(ROOM TEMP)
INSPECTION - PRE-SHIPMENT

PACK/SHIP ORDER

0032-7

o
o
IQI

<>

Key:
PRODUCTION PROCESS
TEST / INSPECTION

II

PRODUCTION PROCESS AND TEST INSPECTION
QC SAMPLE GATE AND INSPECTION
0032-5

13-11

~

Quality, Reliability and Process Flows

~~~~~~~~~~~~~~~~~~~~~==~~~~==~~~~~~~
Reliability Monitor Program
The Reliability Monitor Program is a documented Cypress
procedure that is described in Cypress specification
#25-00008 which is available to Cypress customers upon
request. This specification describes a procedure that provides for periodic reliability monitors to insure that all
Cypress products comply with established goals for reliability improvement and to minimize reliability risks for

Cypress customers. The Reliability Monitor Program is designed to monitor key products within each generic process
family. This procedure requires that detailed failure analysis be performed on all test rejects and the corrective actions be taken as indicated by the analysis. A summary of
the Reliability Monitor Program test and sampling plan is
shown below.

Reliability Monitor Program Sampling Plan
Duration

Sample
Size

Frequency[l]

Early Failure Rate (EFR)
150"CHTOL
125°CHTOL

12 Hours
80 Hours

200
200

Weekly
Bi-weekly

Latent Failure Rate (LFR)
150"CHTOL
125°CHTOL

1000 Hours
2000 Hours

200
200

Monthly
Monthly

High Temp Steady State Life (HTSSL)
150"CHTOL
150"C HTOL (1 lot/quarter extended)

168 Hours
1000 Hours

100
100

Weekly
Quarterly

Plastic Package Data Retention (DRET)
165°C Bake

1000 Hours

55

Bi-weekly

Hermetic Package Data Retention (DRET)
250"C Bake

1000 Hours

55

Monthly

Pressure Cooker (PCT)
121°C/loo% R.H.

288 Hours

55

Weekly

Pre-conditioned Temperature-Humidity Life (PCTH)
96 Hrs. PCT + Biased 85°C/85% R.H.

1000 Hours

55

Every 6 Weeks

High-Acceleration Saturation (HAST)
Biased 121°C/85% R.H.

200 Hours

55

Every 6 Weeks

Temperature Cycle (T/C)
- 65°C to + 150"C
-65°C to + 150"C(llot/quarterextended)

15 Cycles
1000 Cycles

55
55

Weekly
Quarterly

Test Description

Note:
I) Maximum period between samples is listed. More frequent sampling may occur.

13-12

PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO
PLD TOOLKIT
QUALITY AND
RELIABILITY

~ APPLICATION BRIEFS
PACKAGES

,.
III

il.
•
•
,.•
DIll

B

~

Section Contents
~J'~~aoR==============================================================~
Application Briefs

Page Number

RAM Input and Output Characteristics .................................................................... 14-1
Power Characteristics of Cypress Products ................................................................. 14-8
Pin-Out Compatibility Considerations ofSRAMs and PROMs ......................... , ...................... 14-15

CYPRESS
SEMICONDUCTOR

Application Briefs
RAM Input Output Characteristics
Introduction to Cypress RAMs

PRODUCT DESCRIPTION

Cypress Semiconductor Corporation uses a speed optimized CMOS technology to manufacture high speed static
RAMs which meet and exceed the performance of competitive bipolar devices while consuming significantly less
power and providing superior reliability characteristics.
While providing identical functionality, these devices exhibit slightly differing input and output characteristics
which provide the designer opportunities to improve overall system performance. The balance of this application
note describes the devices, their functionality and specifically their 1/0 characteristics.

The five parts in Figure 1 constitute three basic devices of
64, 1024 and 4096 bits respectively. The 7CI89 and 7CI90
feature inverting and non-inverting outputs respectively in
a 16 x 4 bit organization. Four address lines address the 16
words, which are written to and read from over separate
input and output lines. Both of these 64 bit devices have
separate active LOW select and write enable signals. The
256 x 4 7C122 is packaged in a 22 pin DIP, and features
separate input and output lines, both active LOW and active HIGH select lines, eight address lines, an active LOW
output enable, and an active LOW write enable. Both the

r.:==:;--=~DO

r.:==:;--=~D.

I..--+- current is measured with the inputs to the IC at 0.4V or less. Under this
condition the input buffers and output buffers (unloaded
DC wise) draw only leakage currents. All other direct currents are due to the substrate bias generator, sense amplifiers, other internal voltage or current references and NMOS
memory circuits.

To reach these levels the input pins should be either driven
by a CMOS driver or by a TTL driver whose output does
not drive any other TTL inputs.
When the inputs are driven by the minimum TTL levels
(VIH = 2V, VIL = 0.8Y) each input buffer draws 20%
more ICC current than if it were driven rail to rail.

At VIN = 1.5V the input buffers draw maximum Icc current. The total current is measured and the quiescent current subtracted to fmd the total input buffer Icc current.
The current per input buffer is then calculated by dividing
the total input buffer current by the number of input buffers.

VOUT

INPUT BUFFERS
Three different types of input buffers are used in Cypress
products. For purposes of illustration they are referred to
as types A, Band C. Table 1 lists the maximum ICCs.

0059-3

Figure2A

Table 1. Types of Input Buffers

Icc

Buffer
Type
A

1.3

B

0.8

C

1.3

(max. in !IIA)

,

0.6

The schematics and input characteristics for the three
types of buffers are illustrated in Figure 2. A circle on the
gate of a transistor means that it is a P-channel device.
As can be seen from the figure, the input buffers draw
essentially zero IcC current when VIN is 0.4V or less or

o~--~----~---­

o

0.6

2.0

v,N (V)
0059-4

Figure2B
Type A

14-10

~

Power Characteristics

~~~~UcroR================================================================~
Power Dissipation Model (Continued)
DUTY CYCLE CONSIDERATIONS
0.6

The input characteristics ofthe type B (Figure 2D) and the
type C (Figure 2F) butTers may be approximated by triangles symmetric about the YIN = 1.5Y points, whose amplitudes are 0.8 mA and 0.6 mA, respectively. Therefore, between the YIN = 0.5Y and YIN = 3.5Y points the average
current is one-half the peak current, or 0.4 mA and
0.3 mA, respectively. In most systems the input signal slew
rates are two volts per nanosecond or greater so the input
transitions occur quickly. Under these conditions the duty
cycle of the input butTers must be considered.

o _""""_ _---1._ _--J..::_ _
o 0.5
1.5
3.5

vee

VIN (V)
0059-8

Figure2F
TypeC
For example, if the CY7C167-35 RAM were used with
input signals having a slew rate of two volts per nanosecond it would take
1
[3.5Y - 0.5Y] X - - = 1.5 ns
2Y/ns
for the input signals to go through the 3Y transition. During the transition each input butTer would be drawing
0.3 mA of current from the lee supply. However, this time
is only 1.5 ns/35 ns = 0.0429 or 4.29% of the access cycle.
Therefore, the actual input butTer transient current is only
0.0429 X 0.3 mA = 0.01287 mAo It will be shown that
this is insignificant in most power calculations.

0059-5

Figure2C
0.8

INPUT BUFFER FREQUENCY

DEPENDENT CURRENT
This is the current required to charge and discharge the
capacitance associated with each input butTer. The capacitance is typically 5 pF and the voltage swing is typically
4Y.
Using equation 3;
1= CYf
ledf) = 5 X 10- 12 X 4 X f.
ledf) = 20 X 10- 12f.

0 ....=..1..-_---'-_ _..10,..;:"""__....

o

0.5

1.5

3.5

4.0

VIN (V)
0059-6

Fignre2D
TypeB

CORE AND OUTPUT BUFFERS
The memory array will have a standby power dissipation
due to the substrate bias generator, reference generators,
sense amplifiers, and polyload RAM cells or EPROM
cells. This current is measured with YIN = OY, so that the
input butTers draw no current. Under these conditions the
output butTers will draw only leakage current and dissipate
essentially no power.
The output butTers have N-channel pullup devices that
cause the output voltage level to reach YOH = Yee - 1Y.
The capacitance of the output butTers, including stray capacitance, is typically 10 pF.
IfCL = lOpF, YOH ~ 4Y.
Again, using equation 3, ledf) = 40 X 1O- 12f for the
output butTers.

Vee

,.1
0059-7

Figure2E

14-11

II

Table 2 (Continued)

Current Measurement
INSTANTANEOUS CURRENT

No. CINT Icc(Q) 1cc(Max.)
Buffer No.
(mA)
Type Inpnts Outputs (pF) (mA)

Part No.

Figure 3 illustrates the instantaneous current drawn by a
Cypress RAM. The instantaneous power is calculated by
multiplying this current times the constant supply voltage,
V ce. Most of the power is dissipated in the time corresponding to the access time. This is also true for PROMs
and PALs.

B
B
B
C
C
B
B
B
B
B

CY7C161/162
CY7CI64
CY7CI66
CY7C167
CY7C168/169
~Y7C170

~Y7CI71/172
CY7C185/186
CY7CI87
CY7CI89/190

ADDRESS/DATA

22
20
21
17
18
18
18
25
19

4
4
4
I
4
4
4
8
I
4

10

300
300
300
75
75
50
100
330
ISO
21

13
13
13
25
50
33
27
13
7
32

70
70
70
70
70
90
70
100
100
90

PROMs
Table 3
Icc

Buffer No.
No." CINT Icc(Q) IcaMaxJ
(IDA)
Type Inputs Outputs (pF) (mA)

Part No.

~------~------~
~----------T~----------~

II

Quiescent Icc
h = Average Icc
i(t) = Instantaneous Icc

0059-2

=

Figure 3. RAM Ice

AVERAGE CURRENT
The current measurement unit in an automatic tester integrates the instantaneous current over the measurement cycle and arrives at an equivalent average current. In other
words, the average current, 12, during time TCY is equal to
the area between the instantaneous current, i (t), and the X
axis during TCY. Therefore, when the frequency is decreased, the "current pulse" is (figuratively) spread over a
longer time, so the average current is proportionately less.

CJNT

Icc(Q)

1cc(Max.)

(pF)

(mA)

(mA)

PALCI 6L8/R8/R6/R4
PLDC2OG1O
PALC22V1O
PLDCY7C330

40
50
50
300

25
30
40
42

45
55
80
120

Part No.
CY7C401
CY7C402
CY7C403
CY7C404
CY7C408
CY7C409
CY7C428/9
CY7C510
CY7C516
CY7C517
CY3341
CY7C601

Table 2

50
59
28
45
44

Part No.

Table 5

Buffer No.
No. CINT Icc(Q) Icc (Max.
(mA)
Type Inputs Outputs (pF) (mA)
24
27
34
32
20

90
90
90
100
100
100
100
100
100
100

LOGIC PRODUcrS

STATIC RAMs

4
8
I
I
4

35
35
50
9.5
35
45
60
60
35
50

Table 4

Product Characteristic Tables

16
14
IS
12
18

32
35
35
43
43
60
60
60
35
35

For the 16L8, 16R8, 16R6 and 16R4 the number of inputs
and outputs is, within limits, user configurable. All use
type B buffers.

The following tables are listed to enable the user to calculate the current requirements for Cypress products. CINT is
the equivalent device internal capacitance, Icc (Q) is the
quiescent or DC current and ICC(MAX) is the maximum
Icc current (as specified on the data sheet) for the commercial operating temperature range. Conditions are V CC
= SV and TA = 2SoC.

A
B
B
B
B

8
8
8
8
8
8
1/8
1/8
8
8

PALs

Note that the preceding calculations have not accounted
for any DC loads. The user must calculate these separately.

CY7C122/123
CY7C128
CY7C147
CY7C148/149
CY7C150

12
13
13
18
18
14
19
17
14
14

•!Bidirectional pins

DC Load Current

Part No.

B
B
B
C
C
C
C
C
B
B

CY7C225
CY7C235
CY7C245
CY7C251
CY7C254
CY7C261/3/4
CY7C268
CY7C269
CY7C281/282
CY7C291/292

90
120
90
90
90

14-12

No.· CJNT Icc(Q) lcC(Max.)
Buffer No.
(mA)
Type Inputs Outputs (pF) (mA)
B
B
B
B
B
B
C
C
C
C
B
C

6
7
7
8
11
11
14
24
28
28
6
25

6
7
6
7
12
13
12
19/16
16/16
16/16
6
19/64

53
53
53
53
100
100
190
60
60
60
53
950

30
30
30
30
42
42
18
30
30
30
30
89

75
75
75
75
135
135
80
100
100
100
45

600

~
Power Characteristics
~~~~mruaDR===================================================================
Output CVf Current
Product Characteristic Tables (Continued)

1= CVf
CoUT = 10pF
I = 1.15 rnA
V = 4V
f = 1/35 ns
Total = 4 X 1.15 = 4.6 rnA

Table 5 (Continued)
No.* CJNT Icc(Q) lc~1

100t.lHz

FREQUENCY IN HERTZ
0059-9

Figure 4. Typical Icc vs f

14-14

CYPRESS
SEMICONDUCTOR

Pin-Out Compatibility Considerations
of SRAMs and PROMs
When looking for pin compatible replacements for
PROMs, there are a number of key parameters that must
be met. This application brief discusses the non-electrical
parameters of pin-out and programming involved in finding socket compatible second sources for PROMs. Comparison with the selection of a socket compatible SRAM
second source is provided. Additionally, an example of a
verified conversion from the Motorola 68764 to the Cypress CY7C264, a PROM conversion that is not address
line compatible, is presented.
Ignoring the AC/DC characteristics, rmding a second
source for an SRAM is relatively simple. As long as the
power, ground, control (chip select, read, write), address,
and data lines are on the same pins the devices should be
compatible. Specifically, on SRAMs, the address and data
lines need not be numbered identically between the two
devices being compared for them to function identically in
the same socket. As an example, on several Cypress
SRAMs, the address pin numbering is not the same as
some of our competitors. Let's look at a simplified example
that illustrates why this is not a problem. Let's assume that
we have a new device, the 2 bit x 4 location SRAM:
Cypress
2x4

Brand "X"
2x4

101
013
2 A2
02 4

102
023
2 A1
01 4

Brand "X" Board
}LP---A2--------102
023--------02---}LP
}LP---A1--------2 A1
01 4--------01---}LP
0163-2

Brand "X" Board with Cypress 2 x 4
}LP---A2--------1D1
01 3--------02---}LP
}LP- - -A1-- - -- - - -2 A2
02 4-- -- - - - -01- --}LP
0163-3

Figure 2. Example System with 2 x 4 SRAMs
the same as data written to the same location earlier. With
the SRAM, any inconsistency between the Address and
Data line numbering does not really matter because the
data read will be the same as the data previously written.
This occasionally causes some concern with customers who
have not seen this before. To illustrate our point, suppose
that we write a value of 1 (,...P:D2,D1 = 0,1) at location 2
(,...P:A2,A1 = 1,0). If we read location 2, we will obtain
the value 1 that was written, because the address presented
to the SRAM during the read is the same as the address for
the previous write. Similarly, the data read will be in the
same bit order as presented during the previous write to the
location. As far as our system is concerned, the two SRAM
devices are compatible. The only difference, which is not
significant to our system, is where the data was physically
stored inside the SRAM. In the Cypress device, the
address of 2 (,...P:A2,A1 = 1,0) actually stored the data at
SRAM location 2 (Cypress:A2,A1 = 0,1). In the brand X
RAM, the data is physically stored in location 1. However,
the address translation is transparent to the ,...P. Since the
same location is accessed for the subsequent reads, the difference in address numbering between the two devices
doesn't really matter to our system. Similarly, any numbering difference on the data lines doesn't matter either. The
point that is of primary importance here is that for
SRAMs, all writes and reads are generated in your system,
and so long as the address and data lines are on the same
pins, differences in the numbering don't matter.
For PROMs, the scenario becomes slightly more complex.
Since PROMs are programmed using a programmer that is
separate from the system in which they are used, it becomes more difficult to substitute a PROM with a device
that does not have the same address and/or data pin

,...p

0163-1

Figure 1. Example 2 x 4 Simplified SRAMs
Note that the inferior pin-out chosen by the Brand "X" 2 x
4 assigns Address line 2 (A2) to pin 1 whereas the superior
pin-out used by the Cypress device has Al at pin 1, etc. It
is our assertion that these simplified devices are pin compatible. Let's assume that our engineering staff designed an
infrared scanning pattern recogni2ing toaster oven with the
Brand "X" data sheet. Just as your company is about to
ramp into volume production, Brand "X" sends out an
End Of Life notice on their 2 x 4, because they are converting all of their capacity to making DRAM memories. At
this point, you have no desire to layout a new PC board, so
let's take a look at how these devices would look in your
design.
In this case,
is a microprocessor interfacing to the
SRAM. What is of key importance is that the data read
from a given address generated by the microprocessor is

,...p

14-15

I

~

~

Pin-Out Compatibility Considerations of SRAMs and PROMs

~~~~~R================================================================

swapped again due to the difference in numbering between
the Cypress part and the board layout, and.the ,...p will get
the data in the correct order.
The second problem that exists is the difference in address
line numbering. This problem can be resolved in exactly
the same manner as the data swap problem. By simply
setting the programmer to the Cypress device type, reading
the Brand "X" part, then programming the Cypress part,
any addressing differences will be solved allowing the use
of the Cypress device. The difference here is that the location of data words will be swapped to allow for the difference in pin-outs, just as the bits were swapped in the data
line mismatch case.
Many programmers will allow you to read a device different than the part selected, complaining only during a program if the device types do not match. With such a programmer, carrying out the above procedures to convert a
PROM should not present a problem. However, there are
some programmers that will not allow the user to read a
device if it is different from the part selected. These programmers will prevent our method from working. Fortunately, the Cypress' CY3000 QuickPro programmer will
allow this approach to solving our problem. Cypress Field
Applications Engineers, Sales Offices and Distributors can
use their QuickPro to generate a Cypress master PROM
that can be used as a source for copying with un-cooperative programmers.
As an example of such a conversion, the Motorola 68764
8K x 8 PROM has a similar pin-out to the Cypress 7C264
with the exception of address lines 10, II, and 12.

numbering. Let's assume that our Hi-Tek toaster oven's 2 x
4 are now PROMs. If we programmed each location with
data, we would find that the Cypress device would not
work properly when used in the Brand "X" designed socket. In this case our programmer put the data at location 2,
and board would read this data when the microprocessor
requested the data at location 1. Additionally, the data bits
will be swapped on this read. What a messl It becomes
apparent that it is easiest to replace this PROM with a
. device that has the same address and data line numbering.
There are still methods that we can use that will allow us to
use the Cypress 2 x 4 PROM in this socket.
The objective in trying to make the Cypress PROM work
in the foreign pin-out socket is to have the data read by the
system be the same as the data read when the Brand "X"
device is used. In our 2 x 4 example, there are two problems-address line numbering mismatch and Data line
numbering mismatch. Let's first address the data line mismatch. As it stands, data that was written in as bitl,bit2 is
read as bit2,bitl or swapped. If we were able to change our
PC Board layout, we could fix this problem by swapping
the printed traces for Dl and D2. Unfortunately, this
would prevent the use of the Brand "X" device on our
board. We can internally swap the data bits in the Cypress
device, then they would be in the correct order. This swapping of the data bits in the Cypress device can be achieved
through several means. First, we might modify our programming adapter such that D2 and D 1 are swapped from
the normal order when programming the part. Then when
the device is read, we would get the bits in the same order
as presented by the Brand "X" device. This is not a recommended method of solving the problem, because modifying
programmers tends to make the manufacturer of the programmer unhappy. A second method of solving this problem is to alter the binary image of the PROM contents
such that bits D 1 and D2 are swapped in a file on your
computer's disk, then using this altered binary image file to
program the Cypress PROM. This is less likely to cause
damage than modifying a programmer, but requires some
skill in altering the binary file. Finally, the easiest solution
to this problem is to trick the PROM programmer into
swapping the bits for you. If you set your programmer for
the Cypress device type, read a programmed Brand "X"
device into memory, then program the Cypress part with
the image in programmer memory, the bits will have been
swapped for you. Let's look at how this works.
1) Brand "X" 2 x 4
2) Programmer (Cypress)
3) Cypress 2 x 4
4) System Board ,...p

Pin

Cypress 7el64

21
19

AlO
All

Motorola 68764
A12
AlO

A12
All
Figure 4. Cypress 7C264 vs. Motorola 68764 Pin-Out
The following procedure will program a Cypress 7C264
such that it will work properly in a socket designed to
accept Motorola device.
1) Invoke the Cypress QuickPro (or other usable programmer) and select the Cypress 7C264 as the device to be programmed.
2) Place the Motorola part in the programmer adapter
socket and read the device. Optionally write the device
contents to a disk file.
3) Place a Cypress 7C264 into the programmer adapter
socket and program the part. Optionally the contents of the
disk file may be read as the source for programming.
The programmed device will now work in the Motorola
designed socket.
18

:Bit 2, Bit 1
:Bit 1, Bit 2
:Bit I, Bit 2
:Bit 2, Bit 1

Figure 3. PROM Bit Swapping with Programmer
From the diagram above, we can see that the bits in the
Brand "X" device are stored in the order Bit2,Bit1. This is
the same order that the ,...p will read them on our board.
When we set the programmer to read the Cypress part, the
data lines are logically swapped from the Brand "X" ordering. Thus when we read the Brand "X" part, the data bits
will be swapped as shown. When the Brand "X" part is
removed from the socket, and the Cypress device is
plugged in and programmed, the bits will be programmed
into the Cypress part in this same 'reversed' order. When
we place the Cypress part into our board, the bits will be

Summary
If the pins used for power, ground, control, address, and
data line numbering are the same for two devices, they may
be used in the same socket if the other electrical parameters
are compatible. Differences in Address and Data line numbering are of no consequence in SRAM use. Differences in
Address and Data line numbering in a PROM device can
be compensated for by using a simple programming procedure.
14-16

PRODUCT
INFORMATION
STATIC RAMS
PROMS
EPLDS
LOGIC
RISC
MODULES
ECL
MILITARY
BRIDGEMOS
QUICKPRO
PLDTOOLKIT
QUALITY AND
RELIABILITY
APPLICATION BRIEFS
PACKAGES

•
•,.•
•
•
•
•
•

1[1

"I

~

Section Contents

""'~~aku~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Packages

Page Number

Thermal Management and Component Reliability ............................................. " ....... " ... 15-1
Package Diagrams ..................................................................................... 15-6

CYPRESS
SEMICONDUCTOR

Thermal Management and
Component Reliability
One of the key variables determining the long-term reliability of an integrated circuit is the junction temperature of
the device during operation. Long-term reliability of the
semiconductor chip degrades proportionally with increasing temperatures following an exponential function described by the Arrhenius equation of the kinetics of chem-

ical reactions. The slope of the logarithmic plots is given by
the activation energy of the failure mechanisms causing
thermally activated wear out of the device (Figure 1).
Typical activation energies for commonly observed failure
mechanism in CMOS devices are shown in Table 2.

,

I

I
~

~

I-

...-!J -

105

/
0"'"

.....:'/

,
/

j

~ 104
...J

,

iii

«

::::i

I

w

Q:

w

103

N

~

5

./'

':>~

O·

-

u

I /N

w

Q:

./

I(

102

,

I

11 L

101

~~

~ ~a;
til r-'
OIl/" . /

100

.,."..

250

./

O·~e"

.."

./

[L / "
Q:

II'/~

~e"
B-;7 07

N

~~

-

In -

In

01- 0 _ 0
9: :::E
:::E
flI'- Z -

U

200175 150 125 100

75

50

25

TEMPERATURE (C)
0064-1

Figure 1. Arrhenius plot, which assumes a failure rate proportional to EXP ( - E,VkT)
where EA is the activation energy for the particular failure mechanism

15-1

I

Table 2. Failure Mechanisms and
Activation Energies in CMOS Devices
Failure Mode

Thermal Performance Data of Cypress
Component Packages

Approximate
Activation Energy (EQ)

Oxide Defects

0.3eV

Silicon Defects

0.3eV

Electromigration

0.6eV
0.geV

Contact Metallurgy
Surface Charge

0.5-1.0 eV

Slow Trapping

1.0eV

Plastic Chemistry

1.0eV

Polarization

1.0eV

Microcracks

1.3eV

Contamination

1.4eV

The thermal performance of a semiconductor device in its
package is determined by many factors, including package
design and construction, packaging materials, chip size,
chip thickness, chip attachment process and materials,
package size, etc.

Thermal Resistance (8JA, 8Jd
For a packaged semiconductor device, heat generated near
the junction of the powered chip causes the junction temperature to rise above the ambient temperature. The total
thermal resistance is defined as,

oJA--- TJ -p-TA
and OJA physically represents the temperature differential
between the die junction and the surrounding ambient at a
power dissipation of 1 watt.
The junction temperature is given by the equation:

To reduce thermally-activated reliability failures, Cypress
Semiconductor has optimized both their low power generating 1.2J.L CMOS device fabrication process and their high
heat dissipation packaging capabilities. Table 3 demonstrates this optimized thermal performance by comparing
bipolar, NMOS and Cypress high speed lK SRAM CMOS
devices in their respective plastic packaging environments
under standard operating conditions.

TJ
where:

OJC

Device Number

Bipolar

NMOS

Cypress
CMOS
7CI22

93422

9122

Speed (ns)

30

25

25

Icc(mA)

150

110

60

Vcc(V)

5.0

5.0

5.0

PMAx(MW)
Package RTH (JA) rC/W)

750

550

300

120

120

70

Junction Temperature rC)
at Data Sheet PMAX'

160

136

91

TJ - Tc

= - - P - and OCA =

Tc - TA
~-P-':':

TA = Ambient temperature at which the device is operated;
Most common standard temperature of operation
equals 70"C
TJ = Junction temperature of the IC chip
Tc = Temperature of the case (package)
P = Power at which the device operates
OJC = Junction to case thermal resistance
OJA = Junction to ambient thermal resistance
OCA = Case to ambient thermal resistance
The junction-to-ambient environment is a still-air environment where the device is inserted into a low-cost standard
device socket and mounted on a standard .062" 010 PC
board. For junction-to-case measurements, the same assembly is immersed into a constant temperature liquid reservoir approaching infinite heat sinking for the heat dissipated from the package surface.
The thermal resistance values of Cypress standard packages are graphically illustrated in Figures 4 through 7.
Each envelope represents a spread of typical Cypress integrated circuit chip sizes (upper boundary = 5000 Mils2,
lower boundary = 30,000 Mils2) in their thermally optimized packaging environment.
All thermal characteristics are measured using the TSP
(Temperature Sensitive Parameter) test method described
in MIL STO 883C, Method 1012.1. A thermal silicon test
chip, containing a 250 diffused resistor to heat the chip
and a calibrated TSP diode to measure the junction temperature, is used for all characterizations.

Table 3. Thermal Performance of
Fast lK SRAMS in Plastic Packages
Technology

= TA + P [OJAI = TA + P [OJC + OCAI

'Tambient = 7rY'C

The Cypress 7C122 device, during its normal operation,
experiences a 91°C junction temperature, whereas competitive devices in their respective packaging environments see
a 45°C and 69°C higher junction temperature. In terms of
relative reliability life expectancy, assuming a 1.0 eV activation energy failure mechanisms, this translates into an
improvement in excess of two orders of magnitude (100X)
over the bipolar 93422 device and more than one order of
magnitude (30X) over the NMOS 9122 device.

15-2

fir~lCfOR

Thermal Management

,,-...
I-

~
3:
.........
u
0

"--"

UJ

u

z

«
l(/)

(/)

UJ

a:::

....J

«

::E

a:::

UJ

I:
I-

100
90
80
70
60
50
40
30
20
10
0

DIE SIZE
:-+--+--+--+ - - - 5,000 SO MILS.

--30,000 SO MILS .

JA

JC

16

t

20

24

28

32

36

40

LEAD COUNT---

0064-2

Figure 4. Thermal Resistance of Cypress Plastic DIP Packages

100
90

r-r-'-~~'-~~~D~I~E~S=IZ=E--'-'
f---+--+--+--+--+--+ - - - 5,000 SO MILS.

-30,000 SO MILS.

UJ

U

Z

~
(/)
(/)

UJ

a:::
....J

«

::E

a:::
UJ

I:
l-

t

80
70
60

1-----+--4----'

JA

50
40
30
20
10

JC

o
16

20

24

28

32

36

40

LEAD COUNT--0064-3

Figure S. Thermal Resistance of Cypress Cerdip Packages
15-3

~~
........

.~
3:

"u
0

.........
l.&J

u
z
«
.V')
V')

l.&J

e::::

.....J

«

~

e::::
l.&J

:::J:

.-

t

Thermal Management

100
90
80
70
60
50
40
30
20
10
0

1--+--+-+--+--+---+ - - - 5,000 SO MILS.

-30,000 SO MILS.

16

20

24

28

LEAD

32

36

40

COUNT~
0064-4

Figure 6. Thermal Resistance of Cypress Hermetic Chip Carriers (HLCC)

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