1989_Fujitsu_MOS_Memory_Products_Data_Book 1989 Fujitsu MOS Memory Products Data Book

User Manual: 1989_Fujitsu_MOS_Memory_Products_Data_Book

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marshall
San FrancilCO Dlvlelon
336 Los Cochea Street
Milpitas, Cel"omla 95035

Electronics Group
Claude Michael Group
FAX

(408) 942-4600
(408) 942-4700
(408) 262-1224

NMOS DRAMs
CMOS DRAMs
MOS Application-Specific RAMs
MOS RAM Modules
High-speed CMOS SRAMs
Low-Power CMOS SRAMs

III
Ell
Ell
Ell
III
II1II

Application-Specific Static Memories •

D
CMOS Erasable PROMs D
CMOS One-Time PROMs II!II
CMOS EEPROMs OJ
NMOS Non-'Volatile RAMs .111
NMOS Erasable PROMs

CMOS Mask ROMs

III

Quality and Reliability

III

Ordering Information
Sales Information

D
III

Price
$10.00

MOS Memory Products

1989 Data Book

Fujitsu Microelectronics, Inc.
Integrated Circuits Division
3545 North First Street, San Jose, CA 95134-1804
Phone: (408) 922-9000 FAX: (408) 432-9044
TELEX: 910-338-0190

Copyright@) 1988 Fujitsu Microelectronics, Inc., San Jose, California

All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are' InCluded as a means of illustrating typical semiconductor
applications. Complete Information sufficient for construotion purposes is not neoessarily given.
The Information oontalned In this dooume.nt has been oarefully cheoked and Is bl!lIeved to be reliable. However,
Fujitsu Mlcroeleotronlos, Inc. assumes no responsibility for Inaoouracles.
The Information conveyed In this document does not oonvey any 1I0ense under the copyrtghts, patent rights or
trademarks claimed and owned by:Fujltsu Limited, Its subsidiaries, or Fujitsu Mlcroeleotronios, Inc.
Fujitsu Microeleotronlcs, Inc. reserves the right to ohange produots or speolfloatlons without notloe.
No part of this publication may be copied or reproducl!d In any form or by any means, or transferred to any third
party without prior written consent of FUJitsu Microelectronics, Inc.
.
This document Is published by the Technical Publications Department, Fujitsu MicroelectroniCS, Inc.,

3545 North First Street, San Jose, California, U.S.A. 95134-1804; U.S.A., "
Printed in the U.S.A.
Edition 1.0

Ii

Contents
MOS Memory Products

Overview

0-1
Fujitsu's MOS Memory Products ", ..................................•••. 0-2
Alphanumeric Index of MOS Memory Products ........•....••.............. 0-5

Section 1 - NMOS DRAMs ....... .. , ....... , ............................. 1-1
MBS1256-101-12/-15
MBS1256-80
MB81257-101-12/-15
MBS1257-S0
MBS1464-101-12/-15

262144 x 1-bit Dynamic RAM ...•................... 1-3
262144 x 1-blt Dynamic RAM. " .....•.......•..... 1-25
262144 x 1-blt Dynamic RAM ...................... 1-45
262144 x l-bit Dynamic RAM
.......•...... , 1-69
65536 x 4-bit Dynamic RAM .........• " . . . . .. . . . . .. 1-93

Section 2 - CMOS DRAMs . .......... , .. , .............. , . '................ 2-1
MBS1C258-101-12/-15
MB81C466-101-12/-15

CMOS 262144 x 1-bitStatic Column Dynamic RAM .... 2-3
CMOS 65536 x 4-bit Static Column Dynamic RAM .... 2-25
MB81Cl000~701-801-101-12 CMOS 1048576 x 1-bit Fast Page Dynamic RAM .••. 2-41
MB81Cl001-701-801-10/~12 CMOS 1048576 x l-bit Nibble Dynamic RAM .•..... 2-61
MB81 Cl002-S5/-1 01-12
CMOS 1048576 x l-bit Static Column Dynamic RAM .• 2-S1
MBS1Cl003-85/-101-12 CMOS 1048576 Xl-bit
..........•............. 2-105
Serial Access Mode, Dynamic 'RAM
MB81C4256-85/-101-12
CMOS 262144 x 4-bit ..........•.....•.•..•.... 2-123
Fast Page Mode Dynamic RAM,
MBSl C4257-S5/-1 01-12
CMOS 262144 x 4-bit Nibble Mode Dynamic RAM .... 2-147
MBSl C4258-85/-1 01-12
CMOS 262144 x 4-bit Static Column Dynamic'RAM .. 2-175
CMOS 262144 x 4-bit Serial Access Dynamic RAM .. 2-199
MBSl C4259-'85/-1 01-12
MB814100-801-101-12
CMOS 4194304 Xl-bit ................ : . . . . .. .. 2-225
Fast Page Mode Dynamic RAM

Section 3 - MOS Application-Specific RAMs ................................... 3-1
MBS1461-12/-15
MBS1461B-12/-15
MB81C4251"-101-12/-15

65536 x 4-bit Dual-Port Dynamic RAM ..•..•......... 3-3
65536 x 4-bit Dual-Port Dynamic RAM .............. 3-35
262144 x 4-bit Dual Port CMOS Dynamic RAM'
3-67

Section 4 - MOS RAM Modules .......................................... 4-1
MB85225-12/-15
MBS5227-101-12/-15
MBS5230-1 01-12
MB85235-101-12
MBS5240-101-12

MOS 262144 x 8-bit ...........•.......•.. 4-3
Dynamic RAM Module
,'
MOS 262144 x 9~bit ...........•...• :.:. 4-17
Dynamic RAM Module
MOS 1048576 x 8-bit .•.........•..•...• 4-31
Dynamic RAM Module
1 M x 9-bit Dynamic RAM Module . . . . • . . .. 4-49
MOS 262144 x 9-bit ...•........•....•.. 4-65
Dynamic RAM Module

Contents (Continued)
MOS. Memory Products

Section 4- MOS RAM Modules (Continued)
MB85402-30/-40

CMOS 16384 W x 16-bit ................. 4-81
Static RAM Module
CMOS262144 W x 8"'"bit •.•....' ;.i •••• ~ ; •••,;4-89
Static RAM Module
CMOS 65536 W x8-bit ......•....••..... 4-97
High Speed Static RAM Module
,
CMOS 16384 W x 32~bit .••.....•....... 4-105
, Hig~ SReedStatic, RAM Mod~l<:! .'
CMOS 262144 Wx 8-bit ................ 4-113
High Speed Static RAM Module

MB85403A-401-50
MB8541 0-301-40
MB85414-30/-40
MB85420-401-50

Section 5 - High-Speed .CMOSSRAMs ... : ..............•.................. : ........... 5-1
, MB81C67-:-35/-:-451-:-55
MB81 C6SA-25/-301-35
MB81C69A..;.25/-301-35
MB81C71-45/-55
MB81 C71 A-25/-35
MB81 C74-25;:"35
MB81 C75-25/-35
MB81 C78A-35/-45
MB8l C79A~35/~45

MB8~B79':"15/-20

:

MB81C81A-351-45
MB81C84A-35/-45
MB81 C86-55/-70
MB8289-25/-35

CMOS 16384-bit ~tatlc' RAM
"
,
5-3
CMOS' 16384..,.bil. Static RAM ....•..:.• '... 0. 5-15
CMOS 16384-bit Static·RAM
5-27
CMOS 65536-bit Static RAM ' 0 ' •.•.•....• ,", • • • • 5-39
CMOS.6.5536-bit Static RAM ••• ,', •• ',0' •.•• 5-49
CMOS 65536-bit Static RAM
,",-,. '.'.,.;
5-61
CM9S, e553~-oit Static RAM ........ , ..... 5-71
'CMOS 65536-bit Static RAM
5-83
,CMOS 73728-blt Stat/cRAM ........ " ... , . 5-97
CMOS 73728-bit BiCMQS Statio RAM ...... 5-111
CMOS 262144-bit Static RAM ............ 5-121
,CM9~262144-bit Static RAM • • • • • • • • • • 0 , 5-133
CMOS 262144-bit Static RAM ............ 4-141
CMOS 262144-bit Static RAM
4-149

....

~ .~

.0,0.- • • •

0

... ....
••

..

.,',0-0

0

••••

0

.....

• • . • • '.;,' • • • • • •

•••••••

0.0

••

SectionS - Low-Power CMOS SRAMs .' ........................•.. ',' ;' ...... 6-1
M98464A-801-10/-t5/L1LL
MB84256-101-12/-15/L1LL
MB84256A-701-101-12/-15/L1LL
MB841 000-aO/-1 OIL
MB84F256-25

Iv

CMOS. 65536-blt Static RAM •••...•........ 8-3
CMOS 262144-oit Static RAM' .....•.••.... 6-15
CMOS 262144-bitStatic RAM ..•..•....... 6-25
1-Moit CMOS Static RAM with [Jata .•. ; ••.. r 6.,,35
Retention
,
CMOS 262144-01t Static RAM ..... : ....... 6-37

Contents (Continued)
MOS Memory Products

Section 7 - Application-Specific Static Memories. . . . . . . . . . . . . . . . . . . . . . . . .. 7-1
MB81C79B-35/-45
MB8287-25/-35
MB82T790-20/-25
MB81C51-2.5/-30
MB8421/22/-90/-12/L
MB8431/32/-90/-12/L

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

73728-bit Static RAM .......•.•....• 7-3
262144-bit Static RAM .•.......•.•. 7-15
73728-bit Static RAM •...... ;...... 7-27
TAG RAM .........•.......•...... 7-39
16384-bit Dual Port Static RAM .•.•.. 7-55
16384-bit Static RAM ....•.•...••.. 7-73

Sectlon-S - NMOS Erasable PROMs .......................... ; ........... 8-1
65536-bit UV Erasable ROM .............. .8-3
131072-bit UV Erasable ROM ............. 8-15
262144-bit UV Erasable ROM .........•... 8-27

MBM2764-20/-25/-30
MBM27128-20/-25/-30
MBM27256-171-20/-25

Section 9 - CMOS Erasable PROMs .......................... ;.,......... 9;:-1
MBM27C64-20/-25/-30
MBM27C128-171-20/-25
MBM27C256A-15/-171-20/-25
MBM27C256H-l0/-12
MBM27C512-15/-17
MBM27C512-20/-25/-30
MBM27Cl000-15/-20/-25
MBM27C1001-15/-20/-25
MBM27C1024-15/-20/-25
MBM27Cl028-15/-20/-25

Section 10 - CMOS One-Time PROMs

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

UV Erasable 65536-bit ROM . . . . . . . • .. 9,,3
UV Erasable 131072-bit ROM •.•• , . " 9-15
UV Erasable 262144-bit ROM ••....•• 9-27
UV Erasable 262144-bit ROM ..•..•.. 9-37
UV Erasable 524288-bit ROM ..... ; .. 9-47
UV Erasable 524288-bit ROM •.• , . • .• 9-59
1048576-bit UV Erasable ROM •...... 9-71
1048576-bit UV Erasable ROM .•...•. 9-83
1048576-bitUVErasable litOM . . • . • .. 9-95
1048576-bit UV Erasable ROM ..... , 9-107

10-1

One-Time Programmable Handling Recommendation ................•.....•.. 10-3
CMOS 131072-bit One Time PROM ................• 10-5
MBM27C128P-25
CMOS 262144-bit One Time PROM ..•............. 10-15
MBM27C256AP-25
MBM27C512P-25
CMOS 524288,...bit One Time PROM ......•....•.... 10-25

Section 11 - CMOS EEPROMs .............................. ,.. , .... " ,... 11-1
MBM28C64-25/-35
MBM28C65-25/-35
MBM28C256

CMOS 65536-blt EEPROM .•...••... i •• ••••• • i;.. ••• 11-3
CMOS 65536-bit EEPROM . . . . . . . . . . . • . . • . . . • . . . . . 11-11
CMOS 32768 x 8-bit EEPROM ....•.....•.••.•••.. 11'::19

Section 12 - NMOS Non-Volatile RAMs ..................... , ............ 12-1
MBM2212-20/-25

CMOS 1024-bit Non-Volatile RAM ......••.•....••• 12-3

·V

Contents (Continued)
MOS Memory Products

Section 13 - CMOS Mask ROMs .......... .,-'..... : .. ' ...... ; ............... 13:":1
MB83256
MB83512
MB831 000-15/-20
MB832000
MB834100
MB834000-20f'-25
MB834200
S~tion

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOs

2'62144-bit Mask-Programmable ROM ......... 13-3
524288-bit Mask-Programmable ROM ........ 13-11
l-Mbit Mask:"'ProgrammableROM' .. . . . . . . . .. 13-17
2-Mbit Mask-Programmable ROM ........... 13-25
4-Mbit Mask-Programmable ROM ..•........ 13-31
4-Mbit Mask-Programmable ROM ........... 13-37
~-Mbit Mlisk~Progra!11mable ROM ,.......... 13-43

14 - Qualityand,RQJiability , ..........•...... " ...•......... ;. ';' ....... 14-1
Quality Control at Fujitsu. . •. .. . . . . • .. . . . .. . . . . . . .. . . . .. . . • •• . . . •. . . . . . . .. 14-3
Quality COn'trolFlowchart ....•................. '. : ........ ; .. ; . " •. :'. .. . . .. 14-4

Section 15 ~ Ordering Information .. .................... : .... ;. . . . . . . . . . . ..

1'5:"'1

Prod.uct Marking ..•.... ;' :.. '.•.... '.' .•.........•......•.....••...••. : . . . . . •• 15-3
Ordering Codes ..... :........•..•.....................•' .. '.' ..... :' ....... 15-3
Package Cod~s. " ... ; ..... '.' •.......•.........•......... ; . . . . . . . . . . . . .. 15-3

,

,,)

Section 16 ::,'Sa1~s Information.'. • . . . . .. . . . . . . . • . . . . . . . . . . .... . • . .. . . . .. 16-1
Intr;o.c::\uctibn to :fujitsu' •••.. ,.•.. '.. , . . . . . . • . . . • . . . • . . . . . . . . . . . . . . .• .. . . . . . .. 16-3
Headquart~;I t.ocations - WorJdwide ,..................................... 16-7
SalesPf.,jce Locationll-· USA. . . . . . . . . . . • . . . . . . . .. . . . .. .. ... .. . . . . . . . . . . .. 16-8
Distributors - USA ..• . . . . . . • . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .• 16-9
Representatives .:..USA ......•.•........•................................ 16-12
Distribut.or,s. - Caflada •..•.....•.....•. ,";.; ...... ;,.: •... ; '.. ; .................. 16:-14
Representatlves - Canada .......•.........................•............ 16-14
Sales Office Locations -Europe' ~ ... ; ..................................... 16-15
Distributors -Europe ..•.;.;. " .'; .. :: ..•.. i .. . ':' .................. : ....... 16-15
Representatives,',:", E~rope· . c• • ':~, • • • • • • ~ ••, : . . .
• • • • • • • • ' • • • • '. ~ • • • ~ • • • • • • • •
16-16
Sales Office I:.ocatlons- Pacific Asia .........•................•.... :...... 16-17
,Distributors ,- f?acific;Asia ......... '.' .. ',' ..... 'L'.' ; • • . . • • • . . • . • • • . • '.' • • • . . . 16-17
Representatives - Pacific Asia . . . . .. . . . . • . . . . . .. • .. : .• v.' •• , '.' . . . . . . . . . . 16-18
Representatives": Mexico ...... ; ........... : ........ ;.: ... : ....... .' ..... 16-19
,.Representatives ... Puerto Rico .... _,' •.'..•... '.' , .. . . . . . •• . . . • . . . . . . . . • . . . .. 16-19

vi

- - - - - - - - - - - - - - - - Overview - - 1 - - - - - - -

Page
0-3
0-6

FuJltsu's MOS Memory Products
Alphanumeric Index of MOS Memory Products

0-1

0-2

Fujitsu's MOS Memory Products

Introduction
Fujitsu manufactures a wide range of Integrated circuits
that Includes linear products,microprocessors,
telecommunications circuits, ASICs, high-speed ECl
logic, power components' (consisting of both discrete
transistors and transistor arrays) , and both static and
'
dynamic memories.
The MOS memory product line offers devices for use in
a wide range of applications. These memories are
manufactured to meet the high standard of quality and
reliability that is found in ali Fujitsu products.
DRAMs
Fujitsu manufactures a complete family of leading
technology dynamic random access memories for the
data processing, telecom, and industrial markets; This
family consists of the highest density devices currently
available with a broad selection of organizations, access
modes, and packages.
'
MOS Application-Specific Memories
. Our application-specific memories inclu'de a CMOS
dual-port RAM that. has two separate I/O ports, a CMOS
cache buffer RAM that offers a two-byte width data path,
and.a CMOS TAG RAM that enhances memory
performance of cache-based systems.
MOS RAM Modules
Fujitsu manufacturers a complete family ~f reli~ble CMOS
dynamic and static RAM memory modules for those
applications requiring high density and large memory
storage capability. Fujitsu's family of memory modules
are pin compatible with Jedec standards.
High-speed CMOS SRAMs
Fujitsu's high-speed CMOS static RAMs offer the
advantages of low power dissipation, low cost, and high
performance. Features includes TTL compatibility and a
separate chip select pin that simplifies multi package
systems design.

0-3

Fujitsu's MOS Memory Products· (Continued)

Application-Specific Static Memories
To. address the sYstem needs. of cache memory chips,
Fujitsu's appliQatiol')-specific memory line includes both
cache TAG. RAM and !Jigh-speed static RAM, as well as
port· RAMS for ii'l,ultiprocessor systems. Additionally,
FujitsuwUl be offering contrql.chips for memory trans.fers
between CPU, main, and cache memories.
LOw-P()wer,5::I\IIOS$RAMs ..
. rtieselow-powerstatic randdm access memories are
IdeaHysuited for use in microprocessor systems and
other applications where fast access time and ease of
use are required. The memories utilize asynchronous
circuitry and may be maintained in any state for an
indefinite period of time.

J;ujitsucurrently. offers 64K le;,instandard DIPs and several are
offered in flat packages and leaded chip carriers.

0-4

Fujitsu's MOS Memory Products (Continued)

CMOS EEPROMs
These user-programmable, electrically erasable products
are used for systems that require in-system
reprogrammability. Such applications include digital
instrumentation, industrial controls, and systems such as
point-of-:sale terminals. The features include latched
addresses, self-timed write cycles, and write-protect
circuitry.
NMOS Non-Volatile RAMs
Fujitsu's NMOS non-volatile RAMs combine a high-speed
static RAM with an EEPROM to provide read and write
,
capability together with non-volatile storage. These RAMs
are used in systems that require volatile memory that
can be change at fast microprocessor speed. The
features include an unlimited recall endurance and a
10-year data retention store.
CMOS Mask ROMs
These factory-programmed devices are available In
densities from 25BK to 4BMbits and are ideal for
problem-free designs in high-volume production. These'
products are not reprogram mabie and come in .plalltiC
packages. New product development will increase the'
'
density offering to BMbits and beyond.

0-5

Alphanumeric Index of MOS Memory Products
MBS1C1000-70/-S0/-10/-12 •....... 2-41

MBS2T790-20/-25 .....•........... 7-27

MBS1C1001-70/-S0/-10/-12 ........ 2-61

MBS2S7-251-35 .........•......... 7-15

MBS1C1002...,S5/-10/-12 ............ 2-S1,;

MB8289-25/-35 •.. '..•.•........•. ,5~149

MBS1C1003-S5/-10/-12 ........... 2-105

MB831 000-15/-20

................ 3-17

MBS1C25S-10/-12/-15 .•............ 2-3

MB832000 ....................... 13-25

MBS1C4251-10/-12/-15 ........•... 3-67

MBS3256

MBS1C4256-S5/-101-12 ...•...•.•. 2-123

MB834000-201-25

.~;

MBS1C4257-S5/-10/-12:
MBS1 C4259-S5/....i 0/-1',2;

•..•.••..•..... 13,-37

...•... 2-147

MBS34100 ...................... , 13-31

'2~175

MB834200 ....................... 13-43

MBS1C425S-S5/".tO/-12 •.•.•... ' •• ;

MBS1C466-10/-12/;"15

...•....... ",' .....• " ,13-3

.• .. """ • .2-l99

MBe3512 .. : ..................... 13-11

.......•.... 2-25

MBS4F256-25 ..................... 6-37
~-35

MBS1C51-25/-30 .................. 7-39

MB841 OOO-SOH OIL • • • • • • • •••• .• •••

MBS1C67-35/-45/-55 •. , .........•.. 5-3

MBS421/22/-901-12/L .............. 7-55

','

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u

30

~ycb=5.5J
TA=25~C

i

::J

J:

'"

I

w

i;"

W

It
II.

20

a:

.nu

l10

V

"""'--

2
4.·
6
8.
10
l/tpCI CY<::LE RAT,E'(MHzl

Vcc. SUPPLY VOLTAGE (V)

Fig. 13 - PAG.E MODE CURRENT
..
VI SUPPLY VOLTAGE

,/'v

V

10

,'"

V
/'

V

/
;

.2

0
4.0

5.0 '

.... 6.0

Vcc'. ~UPPLY VOLTAGE (V)

0

·1

2

3

4

.5

Hi Rc • CYCLE, RATE (MHz)

MB 81256-10
MB 81256-12
MB 81256-15

:(

.§
N

....
z

w

T)250C

«
~

I

a:
a:

60

U

50

'"a:

~

w
LL

40

W

a:

,;,
u

.V

V
./

i-""

~~
>a.

1.0

ao

:>

Vee. SUPPL Y VOLTAGE (VI

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (VI

Fig. 17 - ADDRESS AND DATA INPUT
VOLTAGE vs AMBIENT TEMPERATURE

Fig. 18 - RAS. CAS AND WE INPUT
VOL TAGE vs SUPPLY VOLTAGE

~O

3.0

3.0

TA=125 oC

I~

Veb=5.0J

0

«~

V1H(Min.1

I'«(!l
"
u«

2.0

.>
:>a:
Oz
z-

1.0

1.0

o~

3.0
vee L5 .0V
~

..s
2.0

V 1H Min.!

~

I

:>

10

«
0
«

5



«
I
:>

:> a:
Oz
z-

.1---

W

I"'ccO
«-'
· ..
VIL(Max.1

z

I ~u«~
(/)-~
I «0
cc>
.:. ....

VIH(~in.!

z2.0

~~
00
«>

';'5

--

~ ~(Max.1

I

«
o
o
~~

>a.

...

z
«

30

~O

"'(!l
w«

a: ....

0-'
00

....

o~

20

'" W

~

"'(!l
w«

«>

2

«
....

T)25°C

«~
'" w 2.0

:l

:t:

3.0

o
~-

70 r- tRe=200ns

FUJITSU
1111111111111111111111111111111111111111111111111111

Fig. 16 - ADDRESS AND DATA INPUT
VOLTAGE vsSUPPLY VOLTAGE

Fig. 15 - REFRESH CURRENT 2
vs SUPPLY VOLTAGE
80

1111111111111111111111111111111111111111111111111111

-

-

I-- I--

~I--'

100 200 300 400 500
CL • LOAD CAPACITANCE (pFI

1·17

o

D

1llllmlllmllllllllllll~1111111II1II111111111 MB81256-10
FUJITSU MB 8125~J2'
1l lml l l l l l l ~l l l l l l m l l l li MB 8125~15

Fig; 22 ~ OUTPUT CURRENT
vs OUTPUT VO(TAGE

Fig. 21 -'OUTPUT CURRENT
vs OUTPUT VOL" AGE
TA225°C



o

.:.

.2

50

I

V

k::t:~

.s

U
I-

'''.<

/'

\

-125

-100

" '\'

"

'\'cc=5.5V

-75

::>
~
::>

-':50

J:

-25

o

Jcc74.5V

.2
I,
2
3
4
5
VOL. OUTPUT VOLTAGE (VI

o

Fig.23'~ CURRENT WAVEFORM

Fig.

. DURIN.G POWER

up

:l±lll! -,

i\\

'\ ~

1
2
3
4
5
VOH. OUTPUT VOLTAGE (VI

24 2. SUB$TRATE

VOL TAGE
. DURINGP<;lWEjl. UP

o ....-.
.

~

,
\+A=25l C

w

!;(:;

1

I-w
.gj CJ

-2

a:-

::><

"'~

"0

::»

::
SOIJs/Division

1-18

i\.

"

-3

5oIJs/Divisi"on

MB 81256-10
MB 81256-12
MB 81256-15

1IIIIIIIIIIIIIIIIIImllllllllllllllllllllllilimii

FUJITSU
1IIIIIIIImllllllllllllllllllllllllllllllllll!IIIII

PACKAGE DIMENSIONS
Standard 16·pin Ceramic DIP (Suffix: ·C)

DIP·16C·A03

16·DEAD CERAMIC (METAL SEAL)DUAL IN·L1NE PACKAGE
(CASE No.: DIP·1&C·A03)

R.050(1.2
REF

\

INDEX ARE

\~
0

[

]
.760(19.30)
.800(20.32)

.287t.29)
J.59)

.1

.290(7.37)

"[ll=::!==l==
.008(0.20)
.012(0.30)

5j

.2oo(5.0B)MAX

.120(3.05)
.150(3.81)

.090(2.29)
.110(2.79)

.020(0.51)
.043(1.10)
.015(0.38)
.023(0.58)

Dimensions in
inches (millimeters)

D

1llllmllllllllmllllllllllllllllmllllllllll~11 MB 81256-10
FUJITSU

D

1111111111111111111111111111111111111111111111111111

MB 81256-12'
MB 8l2:56-15

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Suffix: -C)

DIP-16C-A04

16~LEAD'SEAI\II WELD DIP PACKAGE
(CASE No.: DIP-16C·A04)
; .

R.0~0~~.761""" ~ '~
[:

INDEX AREA",
l'

'
",'

1=

:~

=

-.

,,-

== =

c:::::s
.760(19.301
.800(20.321

.043(1.09ITYP

.20015.,08)MAX

.120(3.05)
.1.50(3.8.1)
.090(2.291

.020(0.511

.110(2.791 f---+-----:;;;;;-;-;:~=:---o-_;tt-~

.050(1.271

.015(0.38)
.023(0.581

1-20'

Dimensions in
inches and (millimeters)

MB 81256~10
MB 81256-12
MB 81256-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111!!I!I!!!!!!!!!!!!!II!I!!!!II!!!I!!!!!!!

PACKAGE DIMENSIONS
Standard 16·pin Ceramic DIP (Suffix: ·Z)

DIP·16C·C04

16-LEAD CERAMIC (CERDIP) DUAL IN·LINE PACKAGE
(CASE No. : Dlp·16C·C04)

I

.284(7.211

~.671

.

~~~--"--';-=-::J--r--r-'

rn

.313(7.951

.325ru~==-_-+_.L

. 754(19.151
.788(20.021

--j

i ·050 (1.27)MAX
.200(5.08IMAX

.120(3.051
.150(3.81)
.090(2.291
.110(2.791

.020(0.511
.050(1.271
.013(0.331
.023(0.581

Dimensions in
jnches (millimeters)

1-21

MB 81256-10
MB81256-12
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIMB 81256-15
1111111111111111111111111111111111111111111111111

III

FUJITSU

PACKAGE DIMENSIONS
Standard l6-pin Plastic DIP (Sutfix: -PI
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M03)

:~:::l: ::, : ::19:::

.29017.37)
.31017.87)

.776119.7)

Dimensions in
inches (millimeters)

Standard l8-pin Plastic LCC (Suffix: -PVI
l8·LEAD PLASTIC CHIP CARRIER
(CASE No.: LCC-18P-M02)
.007(0.18)
.01010.25)
.030(0.76)

ri

TY?

nnn

0
]

.487112.37) [
.493112.52) [

r'

]

]

.522
.532

]

I
UUU]

.282(7.16) .
.288(7.32)
.31718.05)
.327(8.311

TY?

.020(0.511
MIN
.060(1.52)
MIN
.13213.35)
.14013.55)

Ii .05011.27)
TY?

Dimensions In
inches (mil!imeters)

1-22

, MB 81256-10 Illmllllmllllmlllllm~llllllllllmmllml
MB 81256-12 FUJITSU
MB 81256-15 Im~~llm~mllm~lllllllllmmlllm~1111

PACKAGE DIMENSIONS
Stan~ard 16·pin Plastic ZIP (Suffix: .PSZI

PIN ASSIGNMENT
,LEAD
No.1

16

ZIP·16P·M01

,
16 LEAD PLASTIC ZIG2;AG·IN·LINE PACKAGE
(CASE No.: ZIP·16P·M011
.785(19.95)
.813(20.65)

.104(2.65)
.120(3.05)

I

V

cr
INDEX

-

.050(1.27)

TYP

J

.250(6.35)

.327(8.3)
MAX

J6.85)

,

_1 ..

016(0.40)
.024(0.60)

~~ ~
~~'

"

.1183.0)MIN

.008(0.20)
.012(0.30)

~

I.

.

• 1.100(2.54)
TYP

@D D D ~nUnOnOnU~
Dimensions in
inches (millimetres)

1-23

III

•

1IIIIIIIImllllllllll.mllmm~mlll MB ;8125()';'10
FUJITSU . MB '8125fi,;.12

Ilmllmmlm~mlllllllmllllllllll~11111111 MB 81256..15

PACKAGE DIMENSIONS
Standard 18-pad Ceramic LCC (Suffix: -TV)

LCC-18C-F04

18-PAD CERAMIC (FRITSi!AL) LEADLESS CHtP CARRIER
(CASE No.: LCC'18C-F04)

n

.485(12.32)
.500(12.70)

.280(7.111
.295(7.49)

I.

.

.1.115(~.!!21
MAX

'Shape of PrA 1 index: Subject to change without notice

1·24

Dimension in
inches (millimeters).

MB81256-80
March 1987
Edition 1.0

262,144-811 DYNAMIC RANDOM ACCESS MEMORY
The Fujitsu MB 81256 is a fully decoded, dynamic NMOS random access
memory organized as 262,144 one-bit words. The design is optimized for highspeed, high performance applications such as mainframe memory, buffer
memory, peripheral storage and environments where low power dissipation and
compact layout is required.
""Multiplexed row and column address inputs permits the MB 81256 to be
housed in a standard 16 pin DIP/ZIP and 18 pad LCC. Pin'out conform to the
JEDEC approved pin out. Additionally, the MB 81256 offers new functional
enhancements that make it more versatile than previous dynamjc RAMs.
"CAS"-before·RA5" refresh provides an on·chip refresh capability. The
MB 81256 also features "page mode" which allows high speed random access
to up to 512 bits within a same row.
The MB 81256 is fabricated using silicon gate NMOS and Fujitsu's advanced
Triple-Layer Polysilicon process. This process, coupled with single-transistor
memory storage cells, permits maximum circuit density and minimal chip size.
Dynamic circuitry is employed in the design, including the sense amplifiers.

PLASTIC PACKAGE
DIP-16P.M03

PLASTIC PACKAGE
,LCC·18P·M02

(II

Clock timing requirements are noncritical, and power supply torelance" is very
wide. All inputs are TTL compatible.
• 262,144 x 1 RAM, 16 pin DIP
and ZIP/18 pad LCC
• Silicon-gate, Triple Poly NMOS,
single transistor celt
• Row access time (tRAC'),
80ns max. (MB 81256·80)
• Randam cycle time (tRct'
175ns min. (MB 81256·80)
• Page mode cycle time (tpcl,
lOOns min. (M881256-80)
• Single +5V supply, ±1 0% tolerance
• Lower power,
385mW max. (MB 81256-80)
25mW max. (standby)
• 256 refresh cycles every 4ms
• CAS-before-RAS, RAS-only,
Hidden refresh capability

• High speed Read·while-Write cycle
• tAR, tWCR, tOHR, tRWD, are
eliminated
• Output unlatched at cycle end
allows two-dimensional chip'select
• Common I/O capability using
Early Write operation
• On·chip latches for Addresses and
Data-in
• Standard 16-pin Plastic
DIP (Suffix: ·P)
• Standard 18-pin Plastic
LCC (Suffix: ·PD)
• Standard 16-pin Plastic
ZIP (Suffix: -PSZ)
• Standard 16·pin Ceramic
DIP (Suffix: -C)

PLASTIC PACKAGE
ZIP-16P·MOr
DIP·16C-A03: See Page 17
DIP-16C-A04: See Page 18

PIN ASSIGNMENT
A,

Vss

CAS

AO

A,

A,

A,

A,

A5

Vee

A,

o

"',

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Symbol

Rating
Voltage on any pin relative to vss
Voltage on Vee supply relative to Vss
Ceramic

Storage temperature

I

Plastic

Power dissipation
Short circuit output current

VIN, VO UT
VCC
TSTG

Po
-

Value
-1 to +7
-1 to +7
-55to +150
-55 to +125
1.0
50

Unit

;m •

18

DOUT

, . ,~5. A6
TtlPVJ~ 14 Nil.

V
V

'c
W
mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Pin assignment for ZIP: See Page 22

This device contains circuitry to protect· tne
inputs agains~. damage due to high -s.ta~~· volt·
ages or electric fields. However, it is, a~",ised
that normal precautions be tak~n to avoid
application of, any voltage higher than maxi·
mum rated voHages to this high" imped~nce
circuit.

1-25

II
""'.

D
Fig. 1 - MQ,S1256 BLO,,/( ,1),1,,AGRAI'o1

WAITE

CLOCK
GEN,

COLUMN
DECODER

SENSE AMPS
I/O GATING

DATA
OUT
BUFF,

DOUT

-Vss

,
Parameter

.>

,.

,.

Ma~

.Unit

C IN1

7

pF

CIN2

'10

pF

7

pF

SymbQI

Typ
..

,Input Capacl,timce RAS. CAS; WE"
',·Output Capa~itance

1.~2jf

OOUT'

COUT

Illm~~~~llmM~llm~~~~~m~m~11
FUJITSU
Im~~lmllm~III~~~~~m~~~m~I~~1

MB 81256-80

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vssl
Parameter

Symbol

Min

Typ

Max

Unit

Vcc

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High Voltage, all inputs

V IH

"2.4

6.5

V

Input Low Voltage, all inputs

V IL

-2.0

O.B

V

Supply Voltage

Operating
Temperature

O°C to +70°C

DC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
Value
Parameter

Symbol

Unit
Typ

Min
OPERATING CURRENT"
Average Power Supply Current
(RAS, CAS cycling; t RC = Min.)

MB B1256·aO

STANDBY CURRENT
Standby Power Supply Current (RAS, CAS = V IH )

Max
70 '

ICCI

,4:5

Icc2'
';",

MB B1256-BO

PA:GE MODE CURRENT"
Average Power Supply Current
(RAS = V IL , CAS cycling; tpc = Min.)

MBB1256-BO

REFRESH CURRENT 2"
Average Power Supply Current
(CAS-before-RAS; tRC = Min.)

MB B1256-BO

Icc3

mA

"

-'

"

,

REFRESH CURRENT l '
Average Power Supply Current
(RAS cycling, CAS = V IH ; t RC = Min.)

mA

60

mA

35

mA

65

mA

10

p.A

c,~~

Icc4
,

INPUT LEAKAGE CURRENT any input
(V IN = OV to 5.5V, Vcc = 4.5V to 5.5V, Vss
all other pins not under test = OV)

",

Icc5

"

= OV,

II(L)

-10

-,

OUTPUT LEAKAGE CURRENT
(Data is disabled, V OUT = OV to 5.5V)

10U_)

OUTPUT LEVEL
Output Low Voltage (loL

= 4.2mA)

VOL

OUTPUT LEVEL
Output High Voltage (loH

= -5.0mA)

V OH

-10

10

/loA

0.4

V

2.4

NOTE": Icc is depended on output loading and cycle rates. Specified values are obtained with the output open.

V

~~ill~~mi!li~~~llIlin

III

FUJITSU
~~I~m~~~mlli!MIII~OO~M ".';;/8.256';80

...

AC CHARACTERISTICS

(Recommended operating c.onditions ull.l.e~s o~erwise noted.) 1111111__".
'.

Parameter
..

Time between Refresh

Read-Write Cycle Time
,

Acce~s Time from

~

;

HAs

Access Time from CAS

IlI'i1
IlI'i1

175

t RWC

180

ns
ns

80

ns

t CAC '

45

ns

0

25

ns

50

ns

Transition Time

tT

3

RAS Precharge Time

tRP

80

RAS Pulse Width

t RAS

85

RAS Hold Time

t RsH

50

tCAS

50

.;:

ms

t RAC

tOFF

ns

100000

nS

100000

ns

ns

tCSH

85

tRcO

20

CAS to RAS Set up Ti!"8

tCRS

10

Row Address Set Up Time

tASR

0

Row Address Hold Time

tRAH

10

CoJumn'Address Set Up Time ,..

tASC

0

ns

tCAH

15

ns

tRCS

0

ns

CAS Hold Time

1111

RAS to CAS Delay Time'

:

Column:Address Hold Time
Read Command Set Up Time
Read Command Hold Time

Ref~renced

to' CAS

R.ead Command Hold Time Referenced to RAS
Write Command Set Up Time

,

4

t RC

Output Buffer Turn off Delay

CAS Pulse Width

Unit

Max

Min

tREF

Random Read/Write CVcle Time
>

Value
Symbol

tRCH

0

'. tl\RH

20

lID...

twcs

0

twp

15

ns

,
'.

II
II

Write Command Pulse Width

ns

35

ns
tis
ns

ns
;.

ns
ns

.

'its

Write Command Hold Time

tWCH

.15

ns·

Write Command to RAS lead Time

tl\WL

35

ns

Write Command to. CAS Le.ad Time

tcwL

35

ns

Data In Set Up "Dme

;

Data In.Hold Time:
CAS to WE Delay
Refresh Set Up Time for CAS Referenced to RAS
(CAS-before-RAS cycl~) .
.
Refresh Hold Time for CAS Referenced to RAS
(CAS'before-RAS cycle)

..

tos

0

ns

tOH

15

ns

tcwo

15

ns

tFCS

20

ns

tFCH

20

lis
..

<,.r"

1lllllllllllllllllllmmllllllllllllllllm~mll
FUJITSU
MB 81256.. 80 1lllllllllllllllllllllllllllmllllllllllm~mlll

AC CHARACTERISTICS

--

(Recommended operating conditions unless otherwise noted.)
Parameter
CAS Precharge Time (CAS·before-RAS cycle)

RAS Precharge to CAS Active Time (Refresh cycles)
Page Mode 'Read/Write Cycle Time

Value
Symbol

Unit
Min

Max

tCPR

20

ns

tRPC

20

ns
ns

tpc

100

Page Mode Read-Write Cycle Time

tpRwc

100

ns

Page Mode CAS Precharge Time

tcp

40

ns

t RTC

330

ns

tTRAS

230

t CPT

50

Refresh Counter Test Cycle Time
Refresh Counter Test RAS Pulse Width
Refresh Counter TestCAS p'recharge Time

m
m
m

'"

lPOOO

ns
ns

Notes:

D An

II Operation

II
I

m
m

initial pause of 200 fJ-S is required after power-up.
And then several cycle (to which any 8 cycle to per·
form refresh are adequate) are required before proper
device operation is achieved.
If internal refresh counter is to be effective, a minimum of 8 CAS before RAS refresh cycles are required.

•

II
iii

AC characteristics assume tT = 5 ns.
V 1H (min) and V 1L (max) are refrence levels for mea·
suring timing of input signals. Also, transition times
are measured between V 1H (min) and V 1L (max.).
Assumes that tRco ~ tRCO (max.) If tRco is greater
than the maximum recommended value shown in this
table, t RAC will increase by the amount that tRCO
exceeds the value shown.
Assumes that tRCO ::i; tRCO (max.).
Measured with a load equivalent to 2 TTL loads and
100pF.
'

within the tRCO (max) limit insures that
tRAC (max) can be met. tRCO (max) is specified as a
reference point only; if tRCO is greater than the
specified tRco (max) limit, then access time is controlled exclusively by t CAC '
tRCO (min)
(min).

= tRAH

(min) + 2tT (tT

= 5ns) +

tASC

Either t RRH , or tRCH must be satisfied for a read cycle.

III twcs

and t cwo are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs ::i; twcs (min),
the cycle is an early write cycle and the data out pin
will remain open circuitlhigh impedance) throughout
entire cycle.
If t cwo ::i; t cwo (min) the cycle is a read·write cycle
and data out will contain data read from the selected
celt: If neither of the above sets of conditi!?ns is satis·
fied the condition cif the data out is indeterminate.

II Test mode cycle only.

.....
FWlTStJ

1~IIIIMI!HIII!!lllliID~1 MB;'81256"80

Read cYcle

ADDREsses

VOHVOL ------~--------HIG~I·Z·------------~

DOUT

~...!::=-~

_Don'tCare
;.,

'

Write Cycle (Early Write)

DOUT

/

VOH-_____________________ H1GH.Z---------------------VOL_

1-30

Don't Care

m~~~mlm~mlmilmlllm~m~m~~~
FUJITSU

MB .81256-80 1IIIIImm~~mlm~mlllllmmlllmm~~

Read-Write/Read-'-ModifY-Write Cycle

ADDRESSES

~:~~ ""~~.:.221f"

VIVIH-----+---~=t:i--~======~~====~~
L- --,-t-----'
DOUT

DIN

•

Don't Care

Page Mode Read Cycle
~-------=~------~'RAS--~~~~-----------

•

Don't Care

1m! V.lid Dati
:1-.31

III

•

~moom~mWllw~mW~Mmlll
FWvrst1

mml~~m~m~m~~~lmm~IIIM~ MB·81256.. 80

-.,·Page MQde'Write Cycle:(Early Write)·'

.CAS

~ \

.'

Don't ear.

•

Page Mode Read-Write Cycle

ADDRESS

DOUT

•

1-32

Don't Care

~nly

NOTE: WE, DIN

Refresh cycle

=Don't care, As = V IH

or VIL

ADDRESSES
lAo to A7)

DOUT

VOH-:=====~
VOL-_ _ _ _ _ _

~

__";'-'___

IHIGli_Z _ _ _ _ _ _ _";'-'_

•

Don't Car.

CAS-before-RAS Refresh Cycle
NOTE: Address, M, DIN = Don't care

DOUT

VOH-----~
Vo
I)-----------HIGH-Z----....;..-----.Don'tCa..

III

al.IOOI~1
FUiilJ,-sU
.m~~.I~~~~ill.IMa.~:J256~.80

_Don·tCer.

CAS-before-RAS Refresh Counter Test Cvcle

.Oon't<;".re

·1~34

mM~~III!iOOnllnml
FUJITSU
MB 81256-80 ~~~~.M_i

DESCRIPTION
Simple Timing Requirement
The MB B1256 has improved circuitry
that 'eases timing requirements for high
speed access 'operations. The MB 81256
can operate under the condition of
tRCD (max) = tCAC thus providing
optimal timing for address multiplexing.
In addition, the MB 81256 has the
minimal hold time of Address (tCAH),
~, It WCH ) and DII~ It DH ). The
MB 81256 provides higher throughput in inter-leaved memory system
applications. Fujitsu has made timing
requirements that are referenced to
RAS nonrestrictive and deleted them
from the data sheet, these include tAR,
tWCR,'tDHR end tRWD' As a result,
the hold times of the Column Address,
DIN and WE as well as tCWD (CAS to
WE Delay) are not ristricted by tRCD'

CAS, DIN is' strobed by CAS, and the
set-up and hold times are referenced to
CAS. In a read-write cycle, WE can be
delayed after CAS has been low and
CAS to WE Delay Time ItCWD) has
been satisfied. Thus DIN is strobed by
WE:, and set-up and hold times are
referenced to WE:.

Data Output:
"
The output buffer is three-state TTL
compatible with a fan.out of two
standard TTL loads. Data out is the
same polarity as data-in. The output is
in a high impedance state until CAS is
brought low. In a read cycle, or readwrite cycle, the output is valid after
t RAC from transition of RAS when
tRCD (max) is satisfied, or after tCAC
from transition of CAS when the
,transition occurs after tR.IdL (max).
Data remain valid until CAS is reAddress Inputs:
A total of eighteen binary input address turned to a high level. In a write cycle
bits are required to decode any 1 of the identical sequence occurs,but data
262,144 cell locations within the is not.valid,
MB 81256. Nine row-address bits are
established on the input pins (Ao Fast Read-While-Write cycle
to As) and are latched with the Row The MB 81256 has a fast read while
Address Strobe (RAS). Nine column- write cycle which is achieved by precise
address bits are, established on the input control. of the three-state output buffer
pins and are latched with the Column as well as by the simplified timings
Address Strobe '(CAS). 'All· row ad- described in the previous section.
dresses must be stable on o~ before the The output buffer is controlled by the
falling edge of RAS. CAS is internally state of WE when CAS goes low. When
inhibited (or "gated") by RAS to WE is low during CAS transition to low,
permit triggering of CAS as soon as the the MB 81256 goes into the early write
Row Address Hold Time (tRAH) speci- mode in which the output floats and the
fication has been satisfied and the common I/O bus can be used on the
,address inputs have been changed from system, level. Whereas, when WE goes
. row-addresses to'column-address.
low after tCWD following CAS transition to low; the MB 81256 goes into the
delayed write mode. The output then
Write Enable:
contains the data from the cell selected
The read mode or write mode is selected and the data from DIN is written into
with the WE input. A high on WE the cell selected. Therefore, a very fast
selects read mode; low selects write
read write cycle is possible with the
mode. The data input is disable when
MB 81256.
read mode is selected.
Data input:
Data is written into the MB 81256 during a write or read-write cycle. The later
falling edge of WE or CAS is a strobe for
the Data In (DIN) register. In a write
cycle, if WE is brought low before

Page Mode:
Page-mode operation permits strobing
the row-address into the MB 81256
while maintaining RAS at a low throughout all successive memory operations
in which the row-address doesn't change. Thus the power dissipated by the

falling edge of RAS is saved. Access and
cycle times are decreasedbecal,lse the
time normally required to strobe a new
row address is eliminated.
Refresh:
Refresh of the dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row-addresses
(Ao to A7) ,at least every 4ms. The
MB 81256 offers the following 3 types
of refresh.,
RAS-only Refresh:
RAS-only refresh avoids any output
during refresh because the output
buffer is in the high impedance state
unless CAS is brought low.
Strobing each of 256 row-addresses
(Ao to A7) with ros;s will cause all bits
in each row to be refreshed. Further
RAS-only refresh results in a substantial
reduction in, power dissipation. During
RAS-only refresh cycle~ either V IH or
VIL is permitted to As.
CAS-before-RAS Refresh:
CAS-before-~ refreshing available on
the MB 81256 offers an alternate
refresh method. If CAS is held "low"
for the specified period (tFCS) before
RAS goes to "low", on-chip refresh
control clock generators and the refresh
address counter are enabled, and an
internal refresh operation takes place;
After the refresh operation is performed, the refresh address counter is
automatically incremented in preparation for the next CAS-before-RAS
refresh operation.
Hidden Refresh:
A hidden refresh cycle may takes place
while maintaining the latest valid data
at the output by extending CAS active
time.
For the MB 81256 a hidden refresh..ls
a CAS-before-RAS refresh cycle. ,The
internal refresh address counters provide the refresh addresses, as in a normal
CAS-before-RA8 refresh cycle.
CAI-before-~ Refresh Counter Test
Cycle:
A special timing sequence using CAS-

1·35

-

1~~I~~li~mOOI~~~oo~mlm
.~.JIIJ'$U

~1~~mil~m~~mU~~~.~~wm

'II'B. 81256-80

are defined by.thl! refresh;count~r.
The. bit As is set i)ighil1ternal[.y.
• A COLUMN ADDRESS~ .AII. the bits
Ao to As are defined by latching
levels on Ao t.o. As at'the secood
falling edge of CAS;

befQre.FtAS"couoter test cycle provides
a ·cbovehillnt method. of verifying the
f,unctiollaliw.of the CAS·before·RAS
refresh activated circuitry.
After the CAS·befor·RAS refresh opera·
tion, if CAS goes to high and then
goes to low again while FtAS" is held low,
the read and . wreite operations ani
enabled.
This isshown>in the CAS·before •.FtAS"
counter" test tycle timing diagram.
A memory cell address (consfsting of a
row address (9 bits) and column address
(9 bits) to be accessed can be defined
as follows:
.

column address, and keep RA!!
high.
\/\Irite "low'.' til all 256 row,ad·
dress· on the. same,column addr~ss
py using normal early write. cycles.
Read "low" written in step 3) and
"heck... and. simultaneously. write
"high" to the same address, by using
internal ·refresh counter test read·
write cycles. This step i~ repeated
256 times, ,with the addre.'ses being
generated by interna! refresh ad·
dress;c~unter.·· .
,
.Read"high" writter in step 4) and
che,ck by using normal re,ad cycle
for all, 256 l,ocation5.
Complement the test .pattern and
repeatstep 3), 4) and 5). .
,

(3)

(4)

Suggested CAS·before·RASCounter
Test Procedure
The timing as shown in the CAS·before·
RAS Counter Test cycles' is used. for
ti)e following operations:
(1) Initialize the internal refresh' ad·
dress counter QY uSingeightCA$·
before·RA$ r~fresh cycles. .
(~) Throughout ti:le test, use .thesame

*A ROW 'ADDRESS - BitsAo to A7

(5)

(6)

.. d=ig .. 2 - CURRENT WAVEFORM (Vee = 5.5\1, TA'" 25°CI

,

RAS/(l:AS(I:
'. vcI.••:

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.

.' ; "

..

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page Mode Cycle

only Ra rash Cye •

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res

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en

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'~I ~

.

I

,,'

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PUJITSU
MB 81256-80 1111111!llml~m~!llllllm~llm~mllm

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - NORMALIZED ACCESS TIME
vs SUPPLY VOLTAGE
w
:;
j::
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w
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Fig. 4 - NORMALIZED ACCESS TIME
vs AMBIENT TEMPERAUTRE

~

1.2

1. 1

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1.0

J

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0.9

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20
0
20
40
60
00 100
T A. AMBIENT TEMPERATURE 1°C)

4.0
5.0
6.0
VCC SUPPL Y VOLTAGE IV)

Fig. 5 - OPERATING CURRENT
vsCYCLE RATE

.s
~

z

50

w

II:
II:

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u
(!)

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w

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30
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0

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0

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w

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4.0
5.0
6.0
Vcc. SUPPLY VOLTAGE IV)

2
3
4
S
l/tAC. CYCLE RATE IMHz)

Fig.8 - STANDBY CURRENT
vs SUPPL Y VOLTAGE

oo~~---r--~~r-~--~

vcl=s.sJ
70 f- tAC= 175n5--+--+---+---i

60r---t--r-+-~~-+-,

T)2S0C

;(

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5

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z

w

II:
II:

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u

>-

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a
z

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.1-

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a:

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-

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w

-

a:
a:

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U

30

::J
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r- TA=25°C

V

In

LL
W

20

/

11:

1

M
0

V

./

W

11:

2

L

10

.!:?
0

'-20
0
20
40
60
80 100
TA. AMBIENT TEMPERATURE (OC)

1
2
3
4
5
I/IAh. CYCLE RATE (MHz)

Fig. 12 ... PAGE MODE .GURRENT
YlCYCLERATE

«
E
I-

60
50

. 1- .!

r-- ~cc~5,5V

Z

TA=25°C

w

a:
a:

40

::J

u

a
a:;

w

30

w

20

CJ

«
"-

~

..........
..........V

10

V

-

0

2OL-~4,~0--,L-~5~,0~'~!'~~6~,0~~

.!:?

0

.2
4
10
6
l/tPC. CYCLE RATE (MHz)

Vcc;,sUPPL Y'lfO.\.:j;AGE (V)

J'!ig'.J13 "':~AG.er MOllE, CURRENT
vsSUPPl:V VOltAGE

«
E
I-

.. tpJ100J
50

~

:
40

'~

3.0

z
w

a

~

:~

~

~
1-:38

60

«

,N

IZ

w

;.,

20
0

0,

-.
4.0

--

"

;

5.0
6,0
Vcc.SUPP(YV0I-TAGE (VI

a:
'a:
::J
cu.
::t:

REFRESH CU.RRENT 2

60

50 r-

VCb=5,SJ
TA =25°C

/.

40
30

,/.

In
W

~

..

14~

Vi CYCLE RATE

.§

'-TA-25°C

l'

Fig.

11:
..

LL

20

W

a:

,;,
0
.!:?

10
0

V

./

V
1
2
3
.4
5
l/tRC. CYCLE I'IATE.(MHz)

m~~~m~~~~m~~m~~II~I~~m~~
F'UJITSU

MB. 81256.-80 1~~I~im~I~I.~OO

Fig. 16 - REFRESH CURRENT 2
YS SUPPLY VOLTAGE

<
..5
'"
IZ

80

I

«

Fig. 16 - ADDRESS AND DATA INPUT
VOLTAGE ysSUPPLY VOLTAGE

o

a:
a:

SO

CIl w
CIlCl


2!;

fo""'"

>0..
O~
z

30

---

....................

1.0

.~

VIL(Max.l

«

J:

20

~O

~O

S~

>

4.0
5.0
S.O
Vcc. SUPPLY VOLTAGE (V)

Vcc •.sUPPL Y VOLTAGE (V)

Fig. 17 ..,. ADDRESS AND DATA INPUT
VOLTAGEvsAMBIENT TEMPERATURE
3.0

~
o

-

VIH(Min.)

2.0

00

.......... /

CIl

w

TA~5'C

~~

:J

a:
u.

3.0

~

T)25'C
70 r- tRC.,75ns

.Fig. 18 - RAS. CAS AND WE INPUT
, VOLTAGE YS SUPPLY VOLTAGE
3. 0

Vcb~5.0J

TA·~5'C

o
~~

~ ~2.0

0

VIH(JIiJin.l

a:«

I

o!:i

00

«>
2!:: 10
>;;:
.

VIL(Max.)

--

,t·
VIH(Min;l..

.:'

~

!-

VIL(Max.l

0

o~

~

J:

>

o

20
0
20
40
SO
80
100
TA • AMBIENT TEMPERATURE ('C)

Fig. 19 - RAS. CAS AND WE INPUT
VOLTAGE YS AMBIENT TEMPERATURE

4.0
5.0
S.O
Vcc. SUPPLY VOLTAGE (V)

Fig. 20 - ACCESS TIME
CAPACITANCE

YS

LOAD

3.0

I~

vcc L5 .0V

!

o

z«~

~ ~
I 

2.0

V IH Min.!

f:

I-

~

CIl..J

":'1-

:>~ 1.0

w
:;:


20
0
20
40
SO
80
100
TA • AMBIENT TEMPERATURE ('C)

-5

- --

~ I--

~

100 200 300 400 500
C L • LOAD CAPACITANCE (pF)

-

-

WMlmM~~mi~~ln!!
FUJITSU

~i~m~_~m!iill MB 8125(».;.80

'Fig. 21 - OUTPUT CURR~N I
vsOUTPUTVOLTAGE

2

TA 25°C

1

250

zw 2iJo

:;:)

u

b

150

:;:)

.:.

100
50

.2

...

I-

ffi

Vcc""·5V-

/'

!

a::
a::

::I

t.l

,0

t;:

"'w
-a::
ua::
2::1
u

'10

...;;;:::..

RAS=CAS=Vss

,,,,'f

"

\\

'\ ~

1
2
3
4
5
VOH. OUTPUi-VOLTAGE (V)

~>
a::-

1

'~~

-2

~~
~>

-3

,.-

\.t

A=25JC

,

",'
~

~
0

'"

5Ii!ts/Division

1-40

o

::Ie(

5

\

:mNGrr"ll
w

,,-,

JCCj4.5V

Fig; 24- SUBSTRATE VOLTAGE

:fEd· 11I. :1
15

I'" X

"x'CC=5.5V

-.75

~' -50

I

I,

o
:t -25
.2

Fig; 23 - CURRENT WAVEFORM
, DURINGPDWER UP

:;:)Z

-100

5

1
2
3
4
5
" VOL. OUTPUT VOLTAGE (V)

>- <
E

TA~25°C

<

..§ -125

V

I-

...

I::I
0

kt.:r/' ..'

I-

a::
a::

Fig/22- O,I:.ITPUTCURRENT
~sOt.iTPUT VOLTAGE

5O,us/Division

-

"

PACKAGE DIMENSIONS
(Suffix: -C)

DIP-16C-A03

16-LEAD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE
(CASE No_: DIP-16C-A03)

....r-=¢=-!:!!""~;:;=:=.:..,.l

.\

R.050(1.2
REF

.\ ~

INDEX ARE

0

[

l

]

0" to 9"

.300±,010
62'±0:25)
(7
J

I,

'--L,,;:::!:==l==
\'010±.002
(0.25±0.05)

~.

W

.2oo(5.08)MAX

.134±.014
(3.40±0.36)

.100±.010
(2.54±0.25)

.032±.012
(0.81±0.30)
.7oo(17.78)REF

.047::~~~(i .20:~:~~)

Dimensions in
inches (millimeters)

©1987 FUJITSU LIMITED D16035S·3C

.'1,-41

m...

~. . .unl
FUiBTSU

III

MI· .81256~80

PACKAGE DIMENSIONS
(SuffiK: -CI

DIP-16C-A04

161LEAD CERAMIC (METAL SEAL.I.DtJALHII-LlNE PACKAGE
:(CASE . No;: DIP-~,~,A041

R.030(O.76)",,TVP
INDEX AREA

'"

~
Ir;-1

I.

r!F='

(
==-

0:::=

=-=!i .

==

0:::=

.776+.024(19.71+0.61 )
-.016
-0.41

.050( 1.27)MAX

IT

)

1

__ ===:::>1 0° to 9°

I

.300±-010

-""~=::!!::::::jl::::;;;~]~1

c:::::a

t

.010 •. 002
(0.25'0.05)

.043(1.09)TVP
(X" PLCS)

U

.200(5,08)MAX,

.13"±.01" .
(3.40±0.36)

.035±.015
. (0.89iO.38)
Dimensions in
inches (millimeters)
©1987 FUJITSU LIMITED D16044S·2C

1-42

~llmlllm~mllllmlm~lmHllmlmml
FUJITSU

MB 81256-80 Ilmllllll~~llllllml~li~m~llllll~m

PACKAGE DIMENSIONS
(Suffix: .PI
l6·LEAD PLASTIC DUAL IN·LINE PACKAGE
(CASE No.: DIP·16P·M03)

.300±.010
(7.62±0.25)

.010~:gg~

.033~:~~

.047~0012

(0.85~~:~)

(1.2~g·3)

(O.25~~:~: )

.183(4.65)MAX

.118(3.0)MIN

.020(O.51)MIN

TYP

Dimensions in

Inches

(milllm.~.... )

(9'1987 FUJITSU LIMITED D16030S-2C

(Suffix: .PD)
l8·LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC·18P·M021

.008~:~~~ (0.20~~:~~)
A.030(0.76)TVP

n

o

.490±.003
(12.45±0.08)
.527±.005
(13.39±0.13)

TVP

'285±'003~

(7.24±0.08)

.322±.005
(8.18iO.13)
©1986 FUJITSU LIMITED C18016S-3C

.020(0.51)
MIN
.060(1.52)
MIN

J------1f-.134~:~~~(3.4~~:~~)

I ..050(1.27)
TYP

Dimensions in
inch.s (millimeters)

IIIUI• •W
FUJITSU

III

IIIIIIUII.IIIO MB" 81256-80

PACKAGE DIMENSIONS
(Suffix: ·PSZI
PIN ASSIGNMENT

LEAD
No.1

16

ZI,·16P-M01

~,

'=I;;N,D=E;;Xr=r;=;;=;;=;n=n=;;=;;=:;;=::;;::::;;::::;;:::;;!I~~t~)

IIrrF=n.

-

.050(1.27)

TYP

-

.000t.OO4
(0.50tO.l0)

fU ?wS.UJun, un g
U'O' U

©1987 FUJITSU LIMITED Z16001S.3C
J

Dimensions in
inches (millimeters)

Circuit diagrams utilizing
Fujitsu products are included as a means of illustrating
, typical semiconductor applications; consequently, complete information sufficient
for construction, purposes is
not necessarily given_ The
information hilS been carefully, checked 'ahd'is believed to be entirely refiable.
However, no responsibility
is assumed for inaccuracies.
Furthermore, such information does not convey to the
purchaser of the semiconductor devices described
herein any license under the
patent rights of Fujitsu
, Limited or others_ Fujitsu
Limited reserves the right to
change device specifications_

MB 81257-10
MB 81257-12
MB 81257-15
September 1986
Edition 4.0

262,144-BIT DYNAMIC RANDOM ACCESS MEMORY
The Fujitsu MB B1257 is a fully decoded,dynamic NMOS random access
memory organized as 262,144 one-bit words. The design is optimized for high·
speed, high performance applications such as mainframe memory, buffer
memory, peripheral storage and environments where low power diss·ipation and
compact layout is required.
Multiplexed row and column address inputs permit the MB 81257 to be
housed in a standard 16 pin DIP/ZIP and 18 pad LCC. Pin-outs conform to the
JEDEC approved pin out. Additionally, the MB 81257 offers new functional
enhancements that make it more versatile than previous dynamic RAMs.
"CAS·before-RAS"". refresh provides an on·chip refresh capability that is an
upward compatible version of MB. 8266A. The MB 81257 also features "Nibble
Mode" which allows high speed serial access to up to 4 bits of data.
The MB 81257 is fabricated using silicon gate NMOS and FuJitsu's advanced
Triple-Layer Polysilicon process. This process, coupled with single-transistor
memory storage cells, permits maximum circuit density and minimal chip size.
Dynamic circuitry is employed in the design, including the sense amplifiers.

PLASTIC PACKAGE
DIP·lloM03

PLASTIC PACKAGE
LCQ-I6P-M02

Clock timing requirements are non-critical, and power supply tolerance is very
wide. All inputs and output are TTL compatible.
•
•
•

•

•

•
•

•

262,144 x 1 RAM, 16 pin DIP and
ZIP/18 pad LCC
Silicon-gate, Triple Poly NMOS,
single transistor cell
Row access time,
100 ns max. (MB 81257-10)
120 ns max. (MB 81257-12)
150 ns max. (MB 81257-15)
Cycle time,
200 ns min. (MB 81257·10)
220 ns min. (MB 81257-12)
260 ns min. (MB 81257·15)
Nibble cycle time,
45 ns max. (MB 81257·10)
50 ns max. (MB 81257·12)
60 ns max. (MB 81257·15)
Single +5V Supply, ±10% tolerance
Low power,
385 mW max. (MB 81257·10)
358 mW max. (MB 81257·12)
314 mW max. (MB 81257·15)
25 mW max. (standby)
256 refresh cycles every 4ms

•
•
•
•
•
•
•

CAS·before·RAS, RAS·only,
Hidden refresh capability
High speed Read·white·Write cycle
tAR ,l'WCR' tOHR, tRwo are
eliminated.
Output unlatched at cycle end
allows two·dimensional chip select
Common I/O capability using
Early Write operation
On·chip latches for Addresses and
Data·in
·Standard 16·pin Ceramic (Seam Weld)
DIP (Suffix:·C)
Standard 16·pin Ceramic (Cerdip)
DIP (Suffix: ·Z)
Standard 16·pin Plastic
DIP (Suffix: ·P)
Standard 18·pad Ceramic
LCC (Suffix: ·TV)
Standard 18'pin Plastic
LCC (Suffix: ·PV)
Standard 16·piri Plastic
ZIP (Suffix: ·PSZ)

PLASTIC PACKAGE
ZIP-lIP-M01
DIP·16C-A03: See Pege 19
DIP·16C·A04: see Page 20
DIP·16C-C04: See Page. 21
LCC·18C-F04: Se~·Page 24

PIN ASSIGNMENT
As

AS
DIN

(vss CAS

~~tp~L']l
WE 3i

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Voltage on any pin relative to V""
Voltage on Vee supply relative to Vss
Ceramic
Storage temperature
I Plastic
Power dissipation
Short circuit output current

Symbol
V'N,VOllT
VCC
TSTG
Po

-

RAS

Value
-1 to +7
-1 to +7
-65 to +150
-65 to +125
1.0
50

Unit

V
V

°c
W
mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

!1

Ne ~~
Ao I!~
A2

!j

L'_6

DOUT

L',!i

As

'l'OP VIEW p'_4 Ne
~1~3 A3

t'J A4

f8~9·~O~;1~
-A1 \ A1'A5

Vee

Pin assignment for ZIP:

Se8 page

2.~

This device contains circuitry to ..pro.tecr~,,_the
inputs against damage due to hlgh·statiC: \i~lt·
ages or electric fields. However. ft'.s adV'ised
that normal precautions be taken"':. to .avoid
application of any voltage higher than:maxi·
mum rated voltages to this high impedance
circuit.

1·45

-

1IIIIIIIIm~llllllm.lllllm~ij, ,MB8125740,
J"UJITSU MB .81257-12

1IIImllllllllllllllllllllllllllllllllmllmll'NlB81257-1S

,Fig. 1 - MBS1257 BLOCK DIAGRAM

WRITE
CLOCK
GEN.

WE

a:
w

Cl

8w
Cl

262.144 BIT

STORAGE CELL

;:
0·'"
a:

~Vcc

-Vss

'"

.
"

f>arameter

Mal(

Unit

7

pF

C IN2 .

8

pF

,C OUT

7

pF

Symbol

CIN"

Inpur<;apa!:itance RAS. ,CAS. WE
.

".'.

- ,",

Output"Gapacitance'OO'lJT
-"'>"

1·46 .

'"

Typ

'

MB 81257-10
MB 81257-12 FUJrrBU
MB 81257-15 Ilmlllllllllllmlmllllml~IIII!lllmllll

1111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter

Symbol

Min

Typ

Max

Unit

Vcc

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High Voltage, all inputs

V 1H

2.4

6.5

V

Input Low Voltage, all inputs

V 1L

-2.0

0.8

V

Supply Voltage

Operating
Temperature

OoC to +70°C

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Value
Parameter
OPERATING CURRENT'
Average Power Supply Current
(RAS, CAS cycling; tRC = Min.)

Sy!,"bol

MB 81257-12

, 'ICCl

NIBBLE MODE CURRENT'
Average Power Supply Current
(RAS =V 1L , CAS cycling;tNc = Min.)

ICC2

4.5

Icc3

55

REFRESH CURRENT 2'
Average Power Supply' Current
(CAS-before-RAS; tRC = Min.)

mA

mA

50
22

MB 81257-10

20

Icc4

mA

18

MB 81257-15
MB 81257-10
MB 81257-12

mA

60

MB B1257-15
MB 81257-12

Unit

57

MB 81257-10

=Min.)

Max
65

MB 81257-15

MB 81257·12

Typ

' 70

MB81257-10

STANDBY CURRENT
Standby Power Supply Current
(RAS, CAS =V 1H )
REFRESH CURRENT 1"
Average Power Supply Current
(RAS cycling, CAS =V1H;tRC

Min

65
Iccs

MB 81257-15

60
55 '

mA

INPUT LEAKAGE CURRENT any input
(V 1N = OV to 5.5V, Vcc =5.5V, Vss =OV, all other pins
not under test =OV)

IIIL)

-10

10

p.A

OUTPUT LEAKAGE CURRENT
(Data is disabled; V OUT =OV to 5.5V)

'OlL)

-10

10

p.A

OUTPUT LEVEL Output Low Voltage
tlOL =4_2 mAl

VOL

0.4

V

OUTPUT LEVEL Output high Voltage
(lOH =-5.0 mAl

V OH

NOTE

2.4

V

' . Icc is depended on output loading and cycle rates. Specified values are obtained with the output open.

1-47,

III

1IIIIIIIIImlllllllllmmmm~mm~lII~ Ma

III

81257....

PWITSU .",t;\81U7...11

III~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

"'57..15,

,.,• •

AC CHARACTERISTICS, ",

(RacommancJedoperating conditions unl_ oth~rwiSl noted.)

MIN. .

MB 81257·12
MB B1257·10
MB8125H5
Symbol .I--'-~----:--I----r---II----r.......;--I Unit
Min
Max
Min
Max
Min
Max
Time between R'efresh

4

4

ms

Random Read/WrjteCycle time,

200

220

26.0

ns

Read-Wri:te CVpe 'Time

200

220

260

ns

Access Time from 1'IAS,

'"

lUI

.Access Time from. CAS

,

11m

tCAC

100

120

150

50

60

75

ns
ns

o

,25

0

25

0

30

ns

Transition Time,

3

50

3

50

3

50

ns

RASPrecharge Time

85

;O!ltPyt Buff~r Ty(o off Delay

tOFF

, RAS Pulse Width

105

RASHoIclTime

55

, CAS Pulse, Width
CAS Hold lime:':

III

'.,

100000

60
.120

20

22

o

o

"

10

Row Add~ Set Up Time

10

'..

; ColumnAddr~sSet_Up_Time

.0

ColumnAddres$}I~tdTime

15

II

Rea_d<;~mmanct Hold Time Referenced
';;1.;

II

to RAS

()

•

100000

.'

150

ns
100000

ns

75
100000

75

100000

ns

,150.
60

25
.

ns.
75

ns

10

ns·

o

ns

12

15 .

ns

o

o

ns

20

25

ns

o

tRCS

Read Command H?I~l;il)1e Referenced
to CAS
'

100

60

CAS to RAS Set-Up Time

Row Address Hoid rime

120

105

, tCSH

RAS to CAS D~'ff Time

100000

55

tCAS

'.

90

ns

o

o

20

20

ns

o

0'

15

20

25

Wrhjl Commarid ..Hold Time

15

20

25

ns

Write Command to RAS Lead Time

35

40

45

os

Write Command to CAS Lead Time

20

30

25

ns

Data,ln~e\ y.!?

o

o

o

ns

15

20

'. 25.

os

15

20

25

ns

20

20

20

ns

20

25

Write Command:'Set Up Time
Write Command Pu Ise Width

:Time

Data In Hold Time
CASto WE Delay

•

Refresh Set Up Time for CAS
Referenced to"RAS(CAS-before-RAS cycle)
Refresh HOldTimeforCAS"
Referenced to RAS (~-before-RAS cycle)

.l'
t FCH

I

n$

ns

, ns

MB 81257-10
MB 81257-12
MB 81257-15

...

1IIIIIIIIImlllllllllllllllllllllllllillmlllllili

FUJITSU
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImllllili

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

MB 81257·10

MB 81257·12

MB 81257·15

Min

Min

Min

Max

Max

Unit

Max

CAS Precharge Time (CAS·before·RAS cycle)

tCPR

20

25

30

ns

RAS Precharge to CAS Active Time
(Refresh cycles)

tRPC

20

20

20

ns

Nibble Mode ReadlWrite Cycle Time

tNC

45

50

60

ns

Nibble Mode Read·Write Cycle Time

tNRWC

45

50

60
25

tNCAC

Nibble Mode CAS Pulse Width

tNcAs

20

25

30

ns

Nibble Mode CAS Precharge Time

tNCP

1.5

15

20

ns

Nibble Mode Read RAS Hold TIme

tNRRSH

20

25

30

ns

Nibble Mode Write RAS Hold Time

tNWRSH

35

40

45

Nibble MOde CAS Hold Time ·Referenced
to RAS

tRNH

20

20

20

ns

Refresh Counter Test Cycle Time·

tRTe

330

375

430

ns

tTRAS

230

tCPT

50

Refresh Counter Test RAS Pulse Width
Refresh Counter Test CAS Precharge
Time

•
•
II

20

ns

Nibble Mode Access Time

10000

265
60

10000

30

320
70

10000

ns

ns
ns

Notes:

a
I
II
II

I

An initial pause of 200~s is required after power up.
And then several cycles (to which any 8 cycles to per·
form refresh are adequate) are required before proper
device operation is achieved.
If internal refresh counter. is to be effective, a mini·
mum of 8 CAS before RAS refresh cycles are required.
AC characteristics assume tT = 5 ns.
V 1H (min) and V1L (max) are reference levels for
measuring timing of input signals. Also, transition
times are measured between V1H (min) and V1L
(max.).
Assumes that tRCD ~ tRCD (max). If t RCD is greater
than the maximum recommended value shown in this
table, t RAC will increase by the amount that t RCD
exceeds the value shown.
Assumes that tRCD ;;;; t RCD (max).
Measured with a load equivalent to 2 TTL loads and
100 pF . .

m

•

I
III

Operation within the t Rco (max) limit insures that
t RAC (max) can be met. t RCD (max) is specified as a
reference point only; if t RCD is greater than the
specified t RCD (max) limit, then access time is con·
trolled exclusively by t cAC '
tRCD (min) = tRAH (min) '" 2h (h=5ns) '" t ASC (min)
Either tRRH or tRCH must be satisfied for a read cycle.
twcs and tCWD are not restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If twcs ';;;; twcs (min), the cycle
is an early write cycle and the data out pin will remain
open circuit (high impedance) throughout entire cycle.
If tCWD ;;;; tCWD (min), the cycle is a read-write cycle
and data out will contain data. read from the selected
cell. If neither of the above sets of conditions is satis·
fied the condition of the data out is indeterminate.
Test mode cycle only.

1-.49

III

1llllllllllllllllmlllllmlllllllllllllllmlll'Ma 81257-10

FUJITSU '. MI'81257-12

11111111111111111111111111111111111111~llllmll' MI. 812570.15"

,

Read Cycle

, API;lRESI!E:S

DqU,T

Write Cycle (Early Write)

VO H '_ _ _ _ _ _ _ _ _ _ _ HIGH_Z _ _ _ _ _ _ _ _ _ _ __
DOUT

VOL -

1-50

•

Don't Care

MB 81257-10 11111111111111111111111111111111111111111ill~111111
MB 81257-12 FUJITSU
MB 81257-15 1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIilli

Read-Write/Read-Modify-Write Cycle

•

Don't Car.

Nibble Mode Read Cycle

ADDRESSES Vv i
IL

DOUT

VOHVOL - - - - -

IGH-Z.-'~:':::"K:
• .Don'tCare

III

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIOOIIIIIIIIIIIIIIIIIII·MB 81257-10

FUJITSU MB 81257-12
illlllllllllllllllllllllllllllllllllllllllllllllliliMB 81257-15

Nibble MIId.e Write Cycle

ADDRESSES

DOUT

•

Don'tCaro

Nibble Mllde Read-Write Cycle

ADDRESSES.

DOUT

•

Don't Care

MB 81257-10 1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImll l l l l ili
MB 81257-12 FUJITSU
MB 81257-15 Imllmlm~m~m~~m~~m~m~lm~11

~-only Refresh Cycle

NOTE: WE:, DIN = Don't care,

As = V IH

or V IL

ADDRESSES

lAo to A7)

VOH------"""":!ol
DOUT

VOL-

-------'r
•

Don'tCa,.

CAS-before-RAS Refresh Cycle
=Don't care

NOTE: Address, WE, DIN

VOH-----"'\l
DOUT

VOL

~---------~IIG~I-Z--_-~------•

Don'tCa..

1·53

•

Imllmllm~lm~llmimlilm~ ~,,1257-lQ
FWITSU M8 8125~12

~lmll~I~I~t lAB 81257-15'

Hidden

~efreshCycle

_Don'tCa,.

:cAS-before-R'AS Refresh Counter Test Cycle

RAS,

CAS"
ADDRESSES

, WeIR.ad)

DOUT

We'(Write)

II Don't Care
1·54

MB 81257-10 1IIIIIIIIIIIIIIIIIIIImlllllllllm~III~1II1II
MB 81257-12 FUJITSU
.MB 81257';15 IIIIIIIIIIII~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

DESCRIPTION
Simple Timing Requirement
The MB 81257 has improved circuitry
that eases timing requirements for high
speed access operations. The MB 81257
can operate under the condition of
tRco (max) = t CAC thus providing
optimal timing for address multiplexing.
In addition, the MB 81257 has the
minimal hold times of Address (tCAH),
WE· (tWCH) and DIN (tDH)' The
MB 81257 provides higher throughput
in inter·leaved memory system applica'
tions. Fujitsu has made timing require·
ment that are referenced to RAS
non-restrictive and deleted them from
the data sheet. These include t AA ,
tWCA, tDH A and tAWD' As a result,
the hold times of the Column Address,
DIN and WE as well as tCWD (CAS
to WE Delay) are not ristricted by
tACO'
Address Inputs:
A total of eighteen binary input address
bits are' required to decode any 1 of
262,144 cell locations within the
MB 81257. Nine row-address bits are
established on the input pins (Ao
to Ae) and are latched with the Row
Address Strobe (RAS). Nine column·
address bits are established on the input
pi ns and are latched with the Column
Address Strobe (CAS). All row ad·
dresses must be stable on or before the
falling edge of RAS. CAS is internally
inhibited (or "gated") by RAS to
permit triggering of CAS as soon as the
Row Address Hold Time (tAAH) specification has been satisfied and the
address inputs have been changed from
row-addresses to column·addresses.
Write Enable:
The read mode or write mode is selected
with the ~ input. A high on WE
selects read mode, low selects write
mode. The data input is disabled when
read mode is selected.
Data Input:
Data is written into the MB 81257
during a write or read-write cycle. The
later falling edge of WE or CAS is a
strobe for the Dat~(DIN) register. In
a write cycle, if WE is brought low

before CAS, DIN is strobed by CAS,
and the set·up and hold times are referenced to CAS. In a read-write cycle,
WE" can be delayed after CAS has been
low and CAS to WE Delay Time (tewD)
has been satisfied. Thus D IN is strobed
by WE, and set-up and hold times are
referenced to WE.
Data Output:
The output buffer is three-state TTL
compatible with a fan-out of two
standard TTL loads. Data out is the
same polarity as data-in_ The output is
in a high impedance state ulltil CAS is
brought low. In II read cycle, or readwrite cycle, the. output is .,valid after
t AAC from transition of RASwhen
tACO (max) is satisfied, or .after tCAt:
from transition of CAS . when the
transition occurs after tAJaL (max.)
Data remain valid until CAS is returned to a high level. In a write cycle,
the identical sequence occurs, but data
is not valid.
.
.
Fast Read-While-Write cycle
The MB 81257 has .a fast read while
write cycle which is achieved by precise
control of the three-state output buffer
as well as by the simplified timings,
described in the previous section.
The output buffer is controlled by the
sate of WE when CAS goes low. When
WE is low during CAS transition to
low, the MB 81257 goes into the
early. write mode in which the output
floats and the common I/O bus can be
used on the system level. Whereas, when
WE goes low after tewD following CAS
transition to low, the M8 81257 goes
into. the delayed write mode. The
output then contains the data from the
cell selected and the data from DIN
is written into the cell selected. Therefore, a very fast read write cycle (tAwe
= tAc! is possible with the MB 81257.
Nibble Maile:
Nibble mode allows high speed serial
read, write or read-modify-write access
of 2, 3 or 4 bits of data. The bits of data
that may be accessed during nibble
mode are determined by the 8 row
addresses and the B column addresses.
The 2 bits of addresses (CAe, RAe) are

used to select 1 of the 4 nibble bits for
initial access. After the first' bit is
accessed by normal mode, the remaining
nibble bits may be accessed by toggl ing .
CAS high then low while RAS remains
low. Toggling CAS causes RAs and
CAs to be incremented internally while
all other address bits are held constant
and makes the next nibble bit available
for access. (See Table 1).
If more than 4 bits are accessed during
nibble mode, the address sequence will
begin to repeat. Ifahy' bit is written
during nibble mode, the new data will
be read on any subsequent access. If the
write operation is executed again
on subsequent access, the new data will
be written into the selected cell loea··
tion.
In nibble mode, the three-state control
of the DOUT pin is determined by the
first normal access cycle.
The data output is contrO.lled only by
the WE state referenced ~t' the' CAS
negative transiti6n of the normal cycle
(first nibble bit). That is, when twcs>
twcs (min) is met, the'data output will
remain high impedance state throughout
the succeeding nibble cycle regardless
of the WE state. Whereas, when tCWD >
tCWD (min) is met, the data output will
contain data from the cell selected
during the succeeding nibble cycle regardless of the WE state. The write
operation. is done during the period in
which the WE and CAS clocks are low.
Therefore, the write operation can be
performed bit by bit during each nibble
operation regardless of timing conditions of WE (twcs and tCWD) during
the normal cycle (first nibble bit).
See Fig. 2.
Refresh:
Refresh of the dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row-addresses
(Ao to A7) at least every 4 ms.
The MB 81257 offers the following 3
types of refresh.
RAS-only Refresh;
The RAS only refresh abo ids any output during refresh because the output
buffer is in the high impedance state unless CAS is brought low. Strobing each

1-55

D

D
of 256 rOIiV-II!!dlesses (AD ,to A7) w,ith
FiAS wilicauslltiJl bits in each row to
be. refreshed"Fui~her RAS-only refresh
results in a $Uboantial ~eduction in
power. diSSipUio!k During "FiAS-only
refresh cycle•..·.ei'herV1H or V IL is per'J
mitted to A.a""

Suggested CAS-before-RAS Counter Ta.t
Procedure '
,
The timing, as shown in the CAS-beforeR"AS Counter Test cycle, is used for
CA$-b.llfore-RAS Refresh Counter Test the following operations:
1) Initialize .the internal refresh address
Cycle:
counter ·by using eight CAS-beforeA special timing sequence using CASAAS refresh cycles.
before-RAS" counter test cycle provides
-','~"'.!\\: ..:'.
CAS-btrfore,RAS'''lIfresh;
a convenient method of verifying the 2) Throughout the. test, use the same
CA&before-FiAS 'refreshing avaUable on functionality of eAS-before-RAS recolumn address; and keep RAB high.
the, M.B aX2fj7 ofters an. al~ernate re- fresh activated circuitry. After the 3) Write "low" to all 256 row address
fresh method_, l,f:,eJIiS, is .!leld low CA5-before-R"AS refresh .operation, if
on the same column address by using
normal early write cycles.
forthespet:i~ie~r~e~ipd .(t~cs) before ~ goes to high and goes to low again
RASgo,es ',', :to I!)W" "Qn-chip" refr!!,h while Wis held Jow,. the read and 4). Read "low" written in 5tep3) and
check, and simultaneously write.
control ~Io,c~, getll!r,a,tors,a?d .the retresh . write operation are enabled. This is
address c.ou.nter are, en,!\:lled,and, ~n shown in theCAS-before-R"AS,counter
"high" to the same address by using
internal ,refresh o~atiOri. ta~es'J)lai;e. test cycle, timing. diagram. A memory
internal refresh counter test readAfter the refresh operl!til)l1 is perfor-,m- cell addreSs, consisting of a row address
write CYCles. This step is repeated
ed, the refresh address counter is auto- (9 bits) and a, column address (9, bits),
256 times, with ·the addresses \:leing
matically increm~~d in preparation to be accessed can. be defin/ld as folgenerated bY,i.nternal refresh address
for the next CAS,before-RAS refresh lows:
counter.
operation:
,,'
5) Read "high" written in step 4) and
• A' ROVV ADDFlESS~ Bits. Ao to A7 . check by using normal read cycle for
are defined by the refresh cOl,lnter.
Hidden R.fr8$h;. ..'
all 256 locations.
"
A hidden refresh cyCie may takes plaCI!
The bit Ae is set hrgh inte~nally.
. 6) Complement the test pattern and
while maintaining Illtestvaliq data at * A COLUMN ADDRESS - All the bits
repeat step 3), 4) and 5):
.
Ao to Ae are defined by latching
the output by extetiding the
active
time. For. the MS81257;' a hidden
levels. on Ao ,to Ae at the second
.
fal.li"g edge of CAS:
tefresh cycle is CAS-J;iefore~FiAS r!lfresh;
Th.e internal refr..sh address counters
provide the refresh addressas, as in a
normal CAS-before-FfAS refresh cycle.

m

Tabl. t -NIBBLE'fi4bD£ADDRE$S SEQUENCE EXAMPLE
SEQUENCE
;,':;;

NIBS\"E .BIT

RAS/CAS}norm~' m~del

RAe

ROW ADDRESS

CAe

o
o

o

10101010

toggle CAS (nibbhi mode'

2

1

10101010

toggle CAS (nibble mode)

3

o

toggle CAS (nibble mode)

4

1

10101010
10101010
10101010,

toiJgle ~(nibbkliino,del .

1-56

O.

1

o

COLUMN
ADDRESS

10101010

input addresses

10101010
10101
...010... }
10101010
10101010.

generated internally

sequence

repea~

MB 81257-10 ~llmllli!I~~IUlllllm.l~mmlllli
MB 81257-12 FUJITSU
MB 81257-15 Ilimlllilll~li~~I~llliMmlmlilli

Fig. 2 - Nibble Mode
1) The case of first nibble cycle is Early write
RM

-J'--

~~________________________________

I

WE~

,

I

~_ _ _ _ _ _ _ _ _ _~""'--_ __

DIN

DOUT : = > > - - - - - - - - - - - H I GH·Z'''·- - - - - - - - - - - -

LEar,v Write

1-

No Ope • •
(Add. Increment)

1.

Write,-_o-l-I_o--write--J
.:ValidDatll

2) The case of first nibble cycle is delyed write (ReadWrite)

RAS

~~

____________________________________

'~____--,I

Jr--

,'-------',

----~~----~---~----DOUT
l----Read-Write

, . I.

Read-Writa_-I-I_o-IRead
_

: Valid Datil

1·57

II

MB812S7..1O
FUJITSUMB81257-12
1llllllllllllllrnmlllllmllllmllllll~11111111 MB' 81257-15

1IIIIIIIIIIImllllllllllllilimilmlllllllllllili

D

Table-2 FUNCTIONAL TRUTH TABLE
RAS

CAS

WE

DIN

DouT

Read

Write

Refresh

H

H

Don't Care

Don't Care

High-Z

No

No

No

L

L

H

Don't Care ,Valid Qata

Yes

No

L

L

L

Valid Data

High-Z,

No

Yes,

L

L

L

VaHd Data

Valid Data'

Yes

Yes

L

H

Don't Care

Don't Care

High-Z

No

L

L

Don't Care

Don't Care

Valid Data,

H

L

Don't Care

Don't Care

High-Z

"

Note
Standby

.Y~s .

'

Read
Early Write

Yes

twcs~twcs (min)

'.

Yes

Delayed Write or Read-Write
(twcs ~ twcs (min) or
tC\NO ~ tcwD (min))

No

Yes

RAs'- only

No

No

Yes

CAS-before-RAS Refresh Valid
d,ata selected at previous Read
dr Read-Write cycle is held.

No

No

No

CAS disturb.

"'

Refresh

Fig. 3-:-~URRENT WAVEFORM (Vee = 5.5V, TA = 25°C)

Hidden Refresh .cycle

RAS/CAS Cycle

RAS-only Refresh Cycle

Nibble Mode Cycle

r----.

f-

,
160

40

"

~

120
80

-

~
J' \. W
A...

i\
J

1/\
\

I\J

ftt../~
V

\.. U

,

I"'-- :,......r

A

/

\J I'V

'-~

50 ns/Division

1-58

~

\
\

1111\

r-....

V

1\

\.

.A

A-

-

MB 81257-10 IIIlIIlIImlllMlllWllOOlmlllllWll1
MB 81257-12 FWI'I'SU
MB 81257-15. 1llIIIIIIOOIIMlllmllliliMlOOIli

TYPICAL CHARACTERISTICS CURVES
Fig. 4 - NORMALIZED ACCESS TIME
VI SUPPLY VOLTAGE
w
:E
j::

1. 1

e

w

N
:J

()

1. 1

~

:::;

1.0

~

o

0.9

z

0.8

o 0.8

«

~

20
0
20
40
60
80 100
T A. AMBIENT. TEMPERATURE (oCI

4.0
5.0
6.0
Vee SUPPLY VOLTAGE (VI

Fig. 6 - OPERATING. CURRENT
vs CYCLE. RATE
60

~z

50

~

40

l-~e~=5.5J

/

TA=2SoC

!!J

30

~

20

z

II:

...ow
•
o
2

Fig. 7 - .OPERATING CURRENT,
vsSUPPLY VOLTAGE

«

80

z~

70

.§

/V

w

a

V

V

«

~

«

V
./

e

I" I'..

~ 0.9

~

U

~

"

1.0

«

«

Ve6-5.0V
1.2

m

"-

()

~

w
:I
j::

T)25°C
1.2

m

Fig. 5 - NORMALIZED ACCESS TIME
VI AMBIENT TEMPERAUTRE

/V

II:
II:
::l

60

!!J

50

~
ex:

40

z

...0w

10 /

0

2

0
3

I

()

/

2

T)250C

r- tRe=200ns

w

4

V

I""

~

~

30
20

S

lItRe. CYCLE RATE (MHzl

4.0
5.'!
6.0
V ee. SUPPLY VOLTAGE (VI

Fig. 8 - OPERATING CURRENT
VI AMBIENT TEMPERATURE

Fig. 9 - STANDBY CURRENT
vs·SUPPLY VOLTAGE

«
.§

TA!25°C

5

~

zw

~

4

::l

()

>
III
e
z

3

~

2

'o"

1

2
T A. AMBIENT TEMPERATURE (OCI

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (VI

1·59

D

•
Fig. 11 .... REFRESH CURRENT 1
VI CYCLE RATE

Fig. 10 - STANDBY CURRENT
vs AMBIENT TEMPERATURE

1

«

, Vel-5 •5

6

E
~

I-

Z
w

a:
a:

a>

IZ

w

4

a:
a:

:J

I"'--

3

Q

Z

~

N

Jl

(.J

r-- --l-

III

:I:

a:

2

u.

.;
0

E
a:
a:

60

(.J

50

en
w

a:

u.

10

5

234

«

Fig.1!- NIBBLE MODE CURRENT
VI CYCLE RATE
60

1-5 5V..I,

l-yee- •
z· 50 TA=25°C;
w
a:
a: 40

I,

:J

(.J

:J

:I:

. .V

E

,

tRe~200ns

IZ

w

I

V

1ftRe\·CYCLE RATE (MHz)

~i".,12 - REFRESH ,CURRENT 1

25°C
70 _.A,

V

20

0

"

0
20
40
60
60 100
TA'. AMBIENT TEMPERATURE (oC)

1

/

.2

-20

T

T A =25°C

30

a:

1

80

l-~ee-5.5V

40

w

I,

vsSUPPLY VOLTAGE

.I'

1_

50

en
w

"

«

60

w

"<'

..".,

40

V

Q

~

0

a:

w

20

Z

10

...J
III
III

V

w

.; 30

•

0

.2

0

20

4.0

5.0

30

:t

6.0

.2

0

-

--- ---

~

.--

0
4
12
16
8
1ftNe., CYCLE RATE (MHz)

Vee.SUPPL Y VOLTAGE (V)

Fig. 15 .... REFRESH CURRENT 2
vs CYCLE· RATE

«

60

~

50

~

40

a

30

IZ

a:

:I:

ffl

20

-;
I'
0
4iO'

IEw

20

j

10

a:

10
5.0

6.0

Vee. SUPPLY VOLTAG"

1~60

I,

.I.

f-Vee=S.SV
TA=2SoC

o

/

V

V

l/

,--:C

,V
1

..
2

3

4

S

1itRe, CYCI:.ERATE (MHz)

MB 81257-10
MB 81257-12 FUJITSU
MB 81257-15

1111111111111111111111111111111111111111111111111111

11111111111111111111111111111111111111111111111001

«
.s
N

IZ

w

a:
a:
:;)
0
J:

'"u.a:w

80

3.0

~
o

T)25°C.

T)25°C'
70
I--tAe=200ns

0_

60

;! ;;:;

z>

50
40

w

a:
to
0
.!:!

Fig. 17 - ADDRESS AND DATA INPUT
VOLTAGE vs SUPPLY VOLTAGE

Fig. 16 - REFRESH CURRENT 2
v,SUPPLY VOLTAGE

V

,

,

./

.V

ffl~

-

2.0

.::2 i"'"

:5:;

.~ ~(Max.)

~&,

.:.5

:>~

1.0

0-

z

30

«

20
4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

Fig. 19 - RAS. CAS AND WE INPUT
VOLTAGEvsSUPPLVVOLTAGE

Fig. 18 - ADDRESS AND DATA INPUT
VOLTAGE VI AMBIENT TEMPERATURE
3.0

3.0

Ve~=5.0J

I~

TA=~5~C

0

--

z«~

V1H(Min.)

«el
I'0«
"
W

2.0

/""«0:;
V1L(Max.)

a:.>

-'I-

VIH(~in.)

~

--

VIL(Max.)

:>~ 1.0

Cz
z-

«

l:

:>

l:

->

o

-20
0
20
40
60
80
100
T A • AMBIENT TEMPERATURE ("C)

Fig. 20 - RAS. CAS AND WE INPUT
VOLTAGE vs AMBIENT TEMPERATURE
3.0

I~

..s

~~

fi
l:0«

V 1H Min.)

':'1-

VIL(Max.)

~ 2.0

en
en

~

Cz

W

0

1.0

Vel=4.5J
20 -TA=25°C

W

::;

i=

lui~~

:> ~

Fig. 21 - ACCESS TIME YS LOAD
CAPACITANCE

Vee~5.0V

c

4.0
5.0
6.0
vee. SUPPL Y VOLTAGE (V)

15
10

u

«
U

5



a:

OWERUP

M:Ef'1 IIII

:[371 1·111

>

>

.j>

>

~

-3

-

\

TA=25°C

\.

,

•

5oPS/Division

5O"./Division

.

MB 81257-10
MB 81257-12
MB 81257-015

1IIIIIIIIIIIIIIIillilimmmmlmlillilili

P'WlTSU
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllili

PACKAGE DIMENSIONS
Standard 16·pin Ceramic DIP (Suffix: -CI

DIP·16C·A03

16·DEAD CERAMIC (METAL SEALI DUAL IN·L1NE PACKAGE
. (CASE No.: DIP·16C·A031

A.05011.2
REF

\

INDEX ARE

\~
0

[

]

,.,1",

~________~.7~60~11~9.~30~)________
.800120.32)

J~'
~.~1 .

5]',

.2900.37)
.31017.87)

.00810.20)
.01210.30)

.20015.08)MAX

.

.09012.29)
.11012.79)

.12013.05)
.15013.81)

.02010.51)
.04311.10)
.01510.38)
.02310.68)

Dimensions in

inches Imillimeter.)

1-63

111111111111111111~illllllllllllllllllmlllllllll MB 81257-10 "
F.UJITSU1' MB81257-12
Illmlllllllllmllllllllllllllllllmmllllllllll

MB81257-15

"

PACKAGE DIMENSIONS

~

"

Standard 16-pin Ceramic DIP (Suffix: -Cl

DIP-16C-A04

" 1.6-LEAD SoEAM WELD DIP 'PACKAGE
(CA~E No.: OIP-16C,A04)

R.O'3O'IO.76 1",TYP
INDEX AREA

"..

~[~
......

I.

=

""'h

,

n
)]

.28717.291
'3O'T70)

...... ...... ...... ...... =
.760119.30'1

-

I

.800120.321

,04311.09ITYP

;2OO15.08JMAX

.1-2013.051
.15QI3,81!
.09012.291
,11012.791

f--+--~=:;-:;;;=~---1+---.06211.58)

.020'10.511
.05011.271

,01510.381
.02310.58)

Dimensions in
inches and (millimeters)

MB 81257-10 1111111111111111111111111111111111111111111111111
MB 81257-12 FUJITSU
MB 81257-15 1IIIIIill~mIIIIIIIWimillIIOO~OOIIIII

PACKAGE DIMENSIONS
Standard 1611in Ceramic DIP (Suffix: -Z)

DIP-16C-C04

16-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No_ : DIp.;16C-C04)

I

.284(7.21)

l"-r:::r--It::Ir-a::
.........
::r-............
:::3"..........
!I::Ii---a:
.........
::::IO,........
Cl!i--r:::r-"l

---j

r-.

.754(19.15)
.788(20.02)

·lOT

.67)

-I

050(t.27)MAX

.200(5.08)MAX

.120(3.05)
.150(3.81)
.090(2.29)
.110(2.79)

.020(0.51)
.050(1.27)
.013(0.33)
.023(0.58)

Dimensions in
inches (millimeters)

•

a

_1.1

~~OOIl• •~ MB 8t257-1O .
FUJITSU; MB812.-12
MB ·8'1257-15

PACKAGE DIMENSIONS
Standard 16-pin Plastic DIP (Suffix: -PI
16·LEAD PLASTIC DUAL IN· LINE PACKAGE
(CASE No.: Dlp·16p·M03)

:~~1::::: :E~
1~.

.748119.0)
.776119.7).

.29017.37)
.31017.87)

.1"

Dimensions in
1nches (millimeters)

Standard t80pin PlasticLCe {Sl!ffix: -PVI
18·LEAD PLASTIC CHIP CARRIER
(CASE No.: LCC·18P-M02)
••00710.18)
•.(11010.25)
.030«i.76)

n

TYP
nnn

0

~

.487112.37~ [
.493112:52) [

.522
.532

l1N~:

p

[

p

TVP

~ ~~J

.28217.16) ..
.28817.321
.31718.05)
.32718.311

.02010.511
MIN
.06011.52)
MIN
.. 13213.35)
.14013.551

-JI

.05011.27)

TYP

Dimensions in
inches (millimeters)

1-66

MB 81257-10 IllWllllllmllllllllllllllllllllmlllwlllllll1
MB 81257-12 FUJITSU
MB 81257-15 III~III~IIIIIIIII~I~IIII~~IIIIIIIIOOI

PACKAGE DIMENSIONS
Standard 16-Pin Plastic ZIP(Suffix: -PSZ)
PIN ASSIGNMENT
LEAD
No.1

16

ZIP-16P-M01

16 LEAD PLASTIC ZiGZAG-IN-LiNE PACKAGE
(CASE No_: ZIP-16P-M01)
785(1995)
.813(20.65)

.104(2.65)
.120(3.05)

I

~

INDEX

.250(6.35)

c5

J6.85)

J.
__ Mr

.327(8.3)

~~-t

~

.050(1.27)

TYP

-

.008(0.20)
:012(0.30)
.016(0.40)
.024(0.60)

n n 0 ?L O
U U U OJ U

.118(3.0)MIN

I. .

~

,.100(2.54)

TYP

Dimensions in
inches (millimetres)

1~6.7

1111111111111111111111111111111111111111111111111111

MB 81257-10

FUJITSU MB 81257-12
1111111111111111111111111111111111111111111111111111

MB 81257-15

PACKAGE DIMENSIONS
Standard 18-pin Ceramic LCC (Suffix: -TV)

LCC-18C-F04

lS-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
,
(CASE. No.: LCC·18C-F04)

~rl
.485(12.32)
,500(12.10)

.280(7.1U
295(1.491

'Shapeof Pin 1 index; Subject to <;h~n!le wi'houl nol;ce

Dlmenslon'n
inches (millimete'sl.

Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications; consequently, complete information sufficient for construction purposes is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, such in·
formation does not convey to,the purchase, of the semiconductor
deviGes described herein any license under the patent rights of
Fujitsu Limited or others. Fujitsu Limited reserves the right to
change device specifications.

1-68

MB 81257-80
Mlrch 1987
Edition 1.0

262,144-BIT DYNAMIC RANDOM ACCESS MEMORY
The Fujitsu MB 81257 is a fully decoded, dynamic NMOS random access
memory organized as 262,144 one-bit words_ The design is optimized for highspeed, high performanc:e applications such as mainframa memory, buffer
memory, peripheral storage and environments where low power dissipatiOn and
compact layout is required_
Multiplexed row and column address inputs permit the MB B1257 to be
housed in a standard 16 pin ,DIP/ZIP and 18 pad LCC. Pin-outs conform to the
JEDEC approved pin out. Additionally, the MB81257 offers new functional
enhancements that make it more versatile than previous dynamic RAMs.
"CAtbefore-RAS"". refresh provides an on-c:hip refresh capability that is an
upward compatible version of MB 8266A. The MB B1257 also feat\lres "Nibble
Mode" which allows high speed serial access to up to 4 bits of data.
The MB 81257 is fabricat~ using silicon gate NMOS and Fujitsu's advanced
Triple-Layer Polysilicon process. This process, coupled with single-transistor
memory storage cells, permits maximum circuit, den$lty and mi,(lim.1 chip size.
Dynamic circuitry is employed in the design, including the sense amplifiers.

PLASTIC PACKAGE
DIP-1IP...03

PLASTIC PACKAGE
LCC-1IPoMOZ

Clock timing requirements are non-critical, and power supply tolerance is very
wide. All inputs and output are 'TTL compatible.

• 262,144 x 1 RAM, 16 pin DIP
and ZIP/1B ped LCC
• Silicon-gate, Triple Poly NMOS;
single transistor cell
• Row access time (tRAC I,
80ns max. (MB Bl'257-801
• Randam cycle tiine h RC I,
175ns min. (MB 81257-801
• Nibble Mode cycle time !tNe!,
45ns min. (MB 81257-801
• Single +5V supply, ±IO%tolerance
• Lower power,
385mW max. (MB 81257·BOI
25mW max. (standby I
• 256 refresh cycles every 4ms
• CAS·before·RAS, RAS-only,
Hidden refresh capability

• High speed Read-white-Write cycle
• tAR, fwCR,tOHR, tRWO, are
eliminated
• Output unlatched at cyCle end
allows two·dimensional chIp select
• Common I/O capability using
Early' Write operation
• On-chip latches for Addresses and
Data·in
• Standard 16-pin Plastic
DIP (Suffix: -PI
• Standard 18-pin Plastic
LCC (Suffix: -POI
• Standard 16-pin Plastic
ZIP (Suffix: -PSZI
• Standard 16'pin Ceramic
DIP (Suffix: -CI

PLASTIC PACKAGE

ZI",.PoMOl

DIP·I8C-A03: See Page 19
DIP·I8C·A04: See Plge 20

PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (See NOTEI
Rating
Vollage on any pin relative 10 Vss
Voltage on V"" supply relative to Vss
C.ramie
Storage temperature
I Plastic
Power dissipation
Short circuit output current

Symbol
VIN, VOUT
V""
TSTG
Po

-

Value
-110 +7
-1 to +7
-5510 +150
-55'10 +125
1.0
50

Unit
V
V

DC
W
mA

NOTE: Permanent device damage may occur if ABSOLUTE' MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as' detailed in the operational ,sections of this data
sheet. Exposure to absolute ~aximum rating conditions for extended
p"p.ric th,' may at~~::r.t. d~V:C3 reliabilitv.

Pin IlSignment for ZIP: See pege 23
This device contlins' circuitry to proteCt" the
inputs' againlt, ~age due to high static voltages or illectrlc, fields. ,However, it i. IdVised
thlt norm.' p....:autions be, taken to avoi,d
application of Iny Voltage higher thin maxi·
mum rated voltages to this o,igh impedance
circuit.

1-69

_...

SLLiiIIiLM
P1i.Jrrau

FIg; 1 - MB 81267. BLOCK DIAGRAM

RAi--------------__~
CAS----~--------------4_~
REFRESH
CONTROL
CLOCK

.' ~".
26:2,;144 BIT
. !§TOfIAGE CELL

CAPACITANCE'ITA -26°C)
":,
,
Parameter
.

,·4

/'.

Typ

'. ;.

Mal('

Unit

7

pF

,'10

pF'

: ,. p·f,
1-70

•m ,-.•
rwrrsu

MB 81257·80

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss!
Symbol

Min

Typ

Max

Unit

Vcc

4.6

6.0

6.6

V

Vss

0

0

0

V

Input High Voltage. all inputs

V IH

2.4

6.6

V

Input Low Voltage. all inputs

V IL

-2.0

0.8

V

Parameter

Supply Voltage

Operating
Temperature

o°Cto +70°C

DC CHARACTERISTICS

(Recommended operating conditions unl_ otherwl.. noted)
Value
Parameter

Symbol

Unit
Min

OPERAT!NG CURRENTAverage Power Supply Current
(RAS. CAS cycling; tRc • Min.)
STANDBY CURRENT
Standby Power Supply Current

MB.81257·80
"

Max

70

Icc,

mA
,

(RAS. CAS· V IH !

REFRESH CURRENT 1Average Power Supply Current
(RAS cycling. CAS = V IH ; tRC· Min.!

MB 81257·80 '

NIB!JLE MODE CURRENTAverage Power Supply Current
(RAS· V IL • CMCycling; tNC • Min.)

MB 81257-80

REFRESH CURRENT 2Average Power Supply Current
(CAS·before-R'AS; tRc • Min.!

Typ

,

ICC2

4.5

mA

ICC3

60

mA

Ic~

22

mA

65

mA

10

p.A

10

p.A

0.4

V

,.

.'

MB 81257·80

Iccs

INPUT LEAKAGE CURRENT any Input
(V IN • OV to 5.5V. Vcc • 4.5V t05.5V. Vss· OV.
all other pins not under test· OVI

IUL)

-10

OUTPUT LEAKAGE CURRENT
(Data is disabled. V OUT • OV to 5.5VI

10(L"

-10.,

OUTPUT LEVEL
Output Low Volta~ UO L ., 4.2mAI

VOL

OUTPUT LEVEL
Output High Voltage UOH • -6.0mA)

V~H

"

.'

2.4

'V
"

..

NOTE -: Icc is depended on output loading and cycle rates. Specified values are obtained with the output open.

1-71

_am."

_._·.Ms

Fu.R'rSu ',,'

81257-80

AC CHARACTERISTICS

-

(Recommended 0l:'8r~tinl condition. unl... otherwise noted.)

....

.Parameter

..

Time between Refresh
Random ReadlWrite Cycle Time

•..

--

'.

4
180

tOFF

Transition Time

tT

3

RAS Precharge Time

tFlP

80

~ Pulse Width

tFlAS

85

"M.oJ

n.u."

,I.JIII.

~"SH

'"

;',r··"

,.

,

",

CAS Hold Time

.':

~ to CAS'Delay Tim.

II ..

CAS tb lfASSet !!IpTime
Row AddresS SetUp.Tiql.e

!

10

..

.tCAH.
tFlCS

0

tllCH
tFlFlH ......

0

Read'Command Hold Time Referenced to ~
Write Command Set Up ;l'ime .' ,.

'

:

."

Write Command Pulse Width'
Write Command .Hold Time

to ~·lead Tim.

...

Write Command toCAS'Leadfime

.J

Write Command
Dat~)J:I"Set

-

Oata tn. Hold Tima
,

for

RefreS!) Set Up Ti.me
CAS Referenced to fiAS
(CAS:l)e.fore;RA.S cycle)].
Refresl) Hold Time for ilAS Referenced .toRAS
lCAS.befor":RAS cycle)
,

1-72

..

. twcs_,:

,

,

Up Ii"",

CAS to. WE Delay

...
"

..

..

ns
ns
·ns~_

ns

,

-":,

..

lIS .

lis

ns

...

, .ns
~

:

20
.0

"

fti
100000

0

15

ens

. ,"

35

10

.

ns

20

0

to.m:

ils

85

tFlAH

Read Comm.;WHold Time ReferenCed

50

tFlCD

tASC
;

ns

tCSH

Row Address Hold. Time

Read Comm.nd Set Up Time

ns

25

,100000.•...

50

Column Address Set Up Time
Column AdctreSs I:f'lfd Time

ns

45

tcAS

... tASFI

,"

ns

50

tCIIS
.

'.

80

'0

CAS fulse Width

ms
ns

.

tFlAC
t CAC

e A r " u _ I ...... ~ __

Unit

175

tllC
t FlWC

:,,;'

Output 8uffer Turn off Delay

I'

Max

Min

tllEF ,.

1111
1111

Access Time from CM

Value

Symbol

Read-Write Cycle Time
Access Time from RAS

,

..

"

ns
ns
'ils
ns

twp

15

ns

,tWCH

15

tllWL

35

ns

tCWL

35

ns

~ps

0

tOH

15

lCWD

15

ns

tFCS

20

ns

tFCH

20

·ns

I.

,
..
.

ns

ns
,

ns

'r

IIMnl~~~M~~M~H
PUJITSU

MB 81257-80

AC CHARACTERISTICS

.-

_i~.~.

(Recommended operating conditions unless oth_lsa noted.)
Parameter
~ Precharge Time (CAS'before·RAS cyclel

Value
Unit

Symbol
Min

Max

t CPR

20

ns

ffAS Precharge to 00 Active Time (Refresh cyclesl

tRPC

20

ns

Nibble Mode ReadlWrite Cycle Time

tNC

45

ns

Nibble Mode Read·Write Cycle Time

t NRWC

45

ns

Nibble Mode Access Time

t NCAC

Nibble Mode 00 Pulse Width

18

ns

tNCAS

20

ns

tillCP

15

ns

Nibble Mode Read RAS Hold Time

t~RRSH

20

ns

Nibble MO!le WriteRAS Hold Time

tNWRSH

35

ns

Nibble Mode !:AS Hold Time Referenced to ~

t RNH .

20

ns
ns

Nibble Mode

00 Precharge Time

Refresh Counter Test Cycle Time

ID

tRTC

330

Refresh Counter Test RAS PulseWidth

ID

t TRAS

230

Refresh Counter Test CAS Precharge Time

ID

t CPT

50

Notes:

I

I

m

II

An initial pause of 200 IlS is required after power up.
And then several cycles (to which any Scycles to per·
form refresh are adequatel are required before proper
device operation is achieved.
If internal refresh counter is to be effective. a mini·
mum of S CASbefore RAS refresh cycles are required •
. , AC characteristics assume tT - 5 ns.
VIH (minI and V IL (maxI are 'reference levels for
measuring timing of input signals. Also. transition
times are measured between VIH (minI and V IL
(max.l .
. . Assumes that tRCO ~ tRCO (maxI. If tRCO is greater
than the maximum recommended value shown in this
table. t RAC will increase by the amount that tRCO
exceeds,tha.value shown. '
. . Assumes that tRco ~ tRCO (maxI.
Measured with a load equivalent to 2 TTL loads and
100 pF.
'

iii

•

•
.

III

10000

ns
ns

Operation within the tRCO (maxI limit insures that
t RAC (maxI can be met. tRCO (maxI is specified as a
reference point only; if tRco is greater than the
specified tRCO (maxI limit. then access time is can·
trolled exclusively by t CAC '
tRCO (minI" tRAH (mint +41::r(tT =5nsl + t ASC (minI
Either tRRH or tRCH must be satisfied for a read cycle.
twcs and tcwo are not restrictive operating para·
meters. They are included in the data sheet as electrical
characteristics ol)ly. If twcs ~ twcs (minI. the cycle
is an early write cycle and the data out pin will remain
open circuit (high impedance) throughout entire cycle.
If tcwo ~ tcwo (minI. th~ cycle is a read·write cycle
and data out will conta1n data read from the selected
cell. If neither of the above sets of conditions is satis·
fied the condition of the data out is indeterminate.
Test mode cycle only.

1-73

D

--,
PWlTSV

II IIIIRftII

MB 81257·80

Re..t Cycle

°OUT
. . Doll', c::-

Write Cycle (Early Writel

°OUT

VOH-___________________________ HIGH~:---------------------------VOL-

•

Don't ear.

-.-a.E
P WI'I'SV

M8 81257·80

Reed-Write/Reed-MocIify-Write Cycle

Nibble Mode Reed Cycle
~--------__---------tRASI--------------4---~~

H+--,j,

VIH-""_
..-:,
VIL- >.

DOUT

.... IM·teu.

1·75

III

Nibble Mode Write Cycle(E~rIY Write)

'ADDRE~~ES

DOUT

VOHVOL_---'O";'.....' O " ; ' - . . . . ; ; . - - - - - - - H I G H . Z - - - - - - - - - - - - - - -

CJ Don't C...
Nibble Mode Read-W,lte Cycle

~----------~-----------tAAS----------------------~

ADDRESSES

DOUT

[3 Don't Care
1-76

.lIIm~ill~I~!lli~imlm
FV.JI'I'SU

MB 81257-80

.11111.

~nly Ref....h cycI.
NOTE: ~,D'N" Don'teare, As" V'H or V ,L

~--------------'AC----------------~
V'H-

RAS

V 1L -

ADDRESSES
CAD .oA7'

l\oo-------""'IJ-------tAP--------i

V'H-.
V'LV,H-··
V'L-·

en

VOHVOL-

DOUT

o

Don't C...

CA$·before-RAS R.f....h Cyel.
NOTE.: Address,WE', D,N" Don't care
~------------'AC--------------~

RAS

V'HV ,L-

CAS

V'HV ,L-

,-';"'.,....--.,....-11.
'FCS

DOUT

VOHV OL -

f-o-----'AAS------t

J..------"L

'FCH

}--------------------HIGH~_----__-----------------

CJ Don" Ca..

1·77

---PU.nftl1

. . . MB 81257-80

Hidden Refresh Cycla
t------·RC------I

v,.;-----i 1 - - - V1L-

V'H
ADDRESSES

_, V,L

\WeRlIdl

"DOUT

•

Dod. eo..

•

Don"Core

CAl-befo....JiAi Ref....h Counter Test Cycle

1·78

.lnm~lllilllllm~~~lrulll
F'WI'I'SU

MB 81257-80 • •ilOOiWI

DESCRIPTION
Simple Timing Requirement
before CAS, DIN is strobed by CAS,
The MB B1257 has improved circuitry and the set·up and hold times are reo
thlt eases timing ,requirements for high ferenced to CAS: In a read·write cycle,
speed access operations. The MB 81257 WE" can be delayed after CAS has been
can operate under the condition of low and 00 to WE DelayTir'ne (tcwo)
tRco (max) - tCAc thus providing has been satisfied. Thus 0 IN is strobed
optimal timing for address multiplexing. by WE, and set·up and hold times are
In addition, the· MB 81257 'has the referenced to WE.
minimal hold times of Address (tCAH),
m (tWCH) and DIN lto H). The Data Output:
MB 81257 provides higher throughput The output buffer is three·state TTL
in inter-leaved memory systemapplica- compatible with a fan-out of two
tions. Fujitsu has made timing require- standard TTL loads. Data out is the
ment that are referenced to RAS same polarity as data-in. The output is
non-restrictive and deleted them from in a high impedance state until CAS is
the data sheet_ These include tAR, brought low. In a read cycle, or readtWCR' tOHR and tRWO' As a result, write cycle, the outPut is valid after
the hold times of the Column Address, t RAC from transition of RAS when
DIN and WE as well illS tCWD. (~tRCD (max) is satisfied, or after t CAC
to WE Delay) are not ristricted by from transition 01 ~. when the
tRCOtransition' occurs after t'f\£2... (max.)
Data remain valier until CAS is returned to a high level. In a write cycle,
Addreu Inputs:
A total of eighteen binary input address the identical sequence occurs, but data
bits are required to decode any 1 of is not valid.
262,144 cell locations within the
Fast Read-Whil.Write cycl.
MB 81257. Nine row-address bits are
established .on the input pins (Ao The, MB 81257, has a fast read while
to As) and are latched with the Row write cycle which is achieved by precise
Address Strobe (RAS). Nine column- comrol of the three-state output. buffer
address bits are established on the input as well as by the simplified timings,
pins and are latched with the Column described in the previous section.
Address Strobe (CAS). All row ad- The output buffer is comrolled by the
sate of WE when ~ goes low. When
dresses must be stable on or before the
falling edge of ro. CAS is internally WE is low during ~ transition to
inhibited (or "gated") by
to low, the MB 81257 goes into the
permit triggering of CAS IS soon IS the early write mode in which tlie outPut
Row Address Hold Time (tRAH) speci- floats Ind the common 110 bus can be
fication has been satisfied and the used on the system level. Whereas, when
address inputs have been changed from WE goes low after tcwo following CAS
transition to' low,the MB 81257 goes
row·addresses to column·addresses.
into the delayed write mode_ The
output then contains the data from the
Write Enable:
cell selected and the data from DIN
The read mode or write mode is selected is written into the cell selected. therewith the W£ input. A high on WE fore, a very fast reid write cycle is
selects read mode; low selects write possible with the MB 81257.
mode. The data input is disabled when
read mode is selected.
Nibble Mode:
Nibble mode allows high speed serial
Date Input:
read, write or read-modify-write IcceSS
Data is written into the MB 81257 of 2, 3 or 4 bits of date. The bits of data
'during a write or read-write cycle. The that may be accessed during nibble
later falling edge of WE or eAS is a mode ere determined by the 8 row
strobe for the Dat~ (DIN I register. In addresses and the 8 column addresses.
a write cycle, if WE is brought low The 2 bits of addresses (CAe, RAe) IIr.

m

used to select 1 of the 4 nibble bits for
initial access. After the first bit is
accessed by normal mode. the remaining
nibble bits may be accessed by toggling
eAS' high then low while RAS'remains
low_ Toggling CAS causes RAe and
CAe to be incremented internally while
all other address bits are held constant
and makes the next nibble bit available
for access_ (See Table 1).
If more than 4 bits are accessed during
nibble mode, the address sequence will
begin to repeat. If any bit is written
during nibble mode, the new data will
be read on any subsequent access. If the
write operation is executed again
on subsequent eccess, the new data will
be written into the selected cell location . . ,>
,
In n,ibble mode, thlt>. three>-state control
of, t.tie DouT pin is !:Ietermined by the
first norma'! aci:ess cycle.
The data output)s controlled only by
the ~ state referenced at the CAS
negative transition of the normal cycle
(first nibble bit). That .is, when twcs>
twes (min) is met, the data output will
remain high impedance state throughout
the succeeding nibble cycle regardless
of the WE state. Whereas. when tcwD >
tewo (min) is met, the data output will
contain data from the cell selected
during the succeeding nibble cycle reo
gardless of the WE state. The write
operation is done during the period in
which the WE Ind ~ clocks are low.
Therefore, the write'operation can be
performed bit by bit during each nibble
operation regardless of timing con·
ditions of WE (twes and tewo) during
the normal cycle (first nibble bit).
See Fig. 2.
Refresh:
Refresh of the dynamic memory cells is
accomplished by performing a memory
cycle It each of the 256 row-addresses
(Ao to A71at least every 4 ms.
The MB 81257 offers the following 3
types of refresh.
RAS-only Refresh;
The RAS' only refresh aboids any out·
put during refresh because the output
buffer is in the high impedance state unless CAS is brought low. Strobing each

1·79

III

_lUI. .
FWITSU

.lllIlliU MB 81257-80

of 256 row~lIiddresses ·(Auto A7) with
RAS will cause 1111 bits in each row to
berifieshed.Further RAS-only refresh
results in a substantial '. reduction in
power dissipation. During ~nly
refresh cycle, either V 11'1 or V IL is parmittedto At.
.

The internal refresh address .counters
provide the refresh addresses, ., ItI, a
normal·CAS.before.·RAS r,fresh cycle,

Suggested W-befo~'Irll Coul)1lr'J.rt

I'I:ocedure
..
The tir~ing, as shown in the.CAtbefore.

RAS CQunter Te~t Cycle, is used for
.
CAS-before,RAS. Refresh Counte.r Ten the foill/wing operations:
1) Initialize the .internal refresh address
Cycle:
counter by using eight mbefore·
A special timing sequence using CASRASrefresh cycles~ .
before· RAS counter test cycle provides
CAS-before-RAS ",afresh;
a convenient metho.d of verifying, the 2) Throughout the test"use. the~arne
CAS-before.: RAS refresh ing available on functionality,pf CAS-bef()re'RAS raC:\llumn.. address, and keep RAB high.
the r,IIBB1257 offers an alternate re·. ·fresh .activated circuitry.. After,the 3) Write. "low" :to .all 256' ~ow address
fresh' method. If ~. is held low W-before·l!ASrefresh operation, if
, . on the sam'.~lumn addr,.s by using
for' the specified' period . (t~c;s) bef,ore ~ goes to ,high and goes ,to low again
normal earlv write cycles. .'
RA~ goes ..to low,,' ()n-c;bip' ,refresh ""hil~,RAS is,he!d low, theread,.and 4) ReBd'"low''' Writtl," in steP. 3)aiid
control r,:1~k genllrators and the refresh writll,operetion,are e"abled. This is
Cheek', and simultaneously write
address counter ire enabled, and. an shown in the CM-before·RAS counter
"high" to the same addreSs by using
internal refresh operation takes plaCe. testeycle ,timing,d'iagram. Amemilry
internal refresh counter' test read·
,After the refresh operation is perform- cell .ddress, cilnsisting~f a row aditress
write'cycles. this' step' is repe.ted
the refresh address cOunter is auto- (lI.bitsi and column address (9 bits),
256 times, with the addresses being
matitally incremented in preparation to beacC~d can hi defil)ec! as, fol·
generated by internal refresh address
for the next CAS-before~ refresh . lows:
'
.
counter.
operation.
5) Read "high" written in step 41 and
• A ROW ADDRESS - Bits Au to A7
chei:kbv using ;no{malread,cycle for
Hidden RefreSh;
all 256,1ocation,s.
are defined by the refresh counter.
A hidden retresh·.cycle may takes place
The bit At is set high internally.
'61 COmplement tlJe'lest . pattern. and
while inai~tainihg latest valid data' at • A COLUMN ADDRESS ~AII ihe bits
repeat step 3),4) and 5).
the output byextendinll the ~ active
Ao· to At are defined by ,latching
time. For the MB 81257, .thidden
,levels on Au to At it the seclmd
refresh cycle is CAS-before· RAS rafre$h.
falling edge of ~.

ttl;

a

Table 1 ~NIBB.I.E MODE. ADDRESSSE,QUENCE !EXAMPLE
'SEOUENCE
.'.'

NIBB,LE Bll, RAe

ROW ADDRE$S

CAs

COLUMN
' ADDRESS

.-

0

10101010

0

10101010

input addresses

toggle CAS (nibble mode)

2

f

19t01010

0

CAS (nibble mode)

3

0

10101010

101010101
1010,010

generated internally

, touill! ~(nitibiemocie),

4

1.

10101010

1

10101010

0

'10101010

0

10101010

RAS/eAS' (normal mode)
toggle

toggleCASlnibble mode)

1·80

'------------IHIGH.Z-------------~EarlY Write
I. No Ope . I..._-Writ.""·--'_-I-oI__- W r i t . - - - J
--o....

'I

CAdef. Increment)

D:V"idDd8

2) The case of first nibble cycle is delved write (Read·Write)
RAS~

\~.

____ ____________________--J'

~

~

''--__
,'------,
x:::x:::x:::x_______x::x""-___
~r

D,N· _ _ _ _

DOUT

--l

l..--R..d.wrItO-_;+I_·.-R ••d.wrlte _ _
1 •_ _
R.Od-l--R..d.wrl ••

D:VeIIdDd8

1-81

Table-2 FUNCTIONAL TRUTH TABLE

RAS

CAS

WE

DIN

DOUT

Read.

Write

Refresh

H

H

Don't Care

Don't Care

High-Z

No

No

No

Standby

L

L

H

Don't Care

Valid Data

Ves

No

Ves

Read

L

L

L

Valid Data

High-Z

No

Ves

Ves

L!

L

L

Valid Pa.ta

Valid.Data

Ves

Ves

Ves

L

H

Don't Care . Don't care

Hlgh:Z

No

No'

Ves

ft'AS- only Refresh

L

L

Don't Care

Don't eare

Valid Data

No

No

Ves

CAS~before-RAs.Refresh Valid
data selected at previous Read
or' Read-Write cycle is held.

H

L

Don't Care

'Oon't Care

High-Z

No

No

No

CAS disturb.

,

"

".

Fig_ 3 -CURRENT WAVEFO'RM

RAS/CAS Cycle

RAS
CAS

Hidd en Refresh Cycle

---..

C
0

,g

1\

40

, 1.(

.,,"

1\

80

.. 1\ f\
~v \. ....J

(tewo ~ tewo (min))

N'bbl
d Cvco
I
I
• Mo.

RA$-only Refresh Cycle

I

l\J

".

\

~J~

v I\...

1\'
I \

U

nl"

\.)

,,r- J -

'in .

n

J

v 1'-II

50n./Di.IliSio" •

1-82'

Delayed Write on:tead-Wri'te

r- r

160
120

Early Write
twes~wcs (min)

Wee· 5_5V.TA· 25°C)

I"

.s

Note

\

./1 ~

rvv \..
'-

A

.A

-

.am~~!II!M!~m
FWiTSU

•

MB 81257-80 IIJIUI• •UII

TYPICAL CHARACTERISTICS CURVES
Fig. 4- NO(tMALIZED ACCESS TIME
VI SUPPLY VOLTAGE

w
j:

III
w

1.1

N

1.0

:;

j:

::E
0

~

"-

...........

0.9

~

:;

r-.....

::E

~
z

~

;:)

4.0
15.0
8.0
Vcc SUPPLY VOLTAGE (VI

-20
0
20
40
60
80 100
T A. AMBIENT TEMPERATURE (DCI

Fig.6,..... oPERATING CURRENT
VI CYCLE RATE

Fig. 7 - OPERATING CURRENT
vs SUPPL Y VOLTAGE

80

I

J

60 _~ce·6.6V
D

/

40

U

CI

z

~
II:
w

I!i

u
2

./

TA-26 C

w

II:
II:

0.9

/

~V

~

:/

~ 0.8

c

~

!2

1.0

C

U 0.8

<

~

1. 1

e

Z

!

1.2

m

'\.

C

II:

VC~·6.0J

::E

1.2

8
C

e
w

w

TA~26°C

::E

Fig. 5 - NORMALIZED ACCESS TIME
vs AMBIENT TEMPERAUTRE

30

20
10
0

,

/

/

't'

/

<

80

!
....

70

II:
II:

60

Z
w

I

T)260 C
r-tRc·176ns

;:)

.... V

U

CI

z

60

II:

40

j:
C

...0

~

V

./

W

U

2

30
20

3

4
15
l/tRC. CYCLE RATE (MHzl

4.0
6.0
8.0
Vcc. SUPPLY VOLTAGE (VI

Fig. 8 - OPERATING CURRENT
vs AMBIENT TEMPERATURE

Fig. 9 - STANDBY CURRENT
vsSUPPLY VOLTAGE

2

80

! ~r-~~~=~~~--~--r--+--,
~
~

TA!25D C
15

80r-~---+---r--~--r--;

4

~

6Or-~---+---r--~--r--;

3

~II:

40r-~---+---r--~--r--;

2

30r-~---+--~--+---r-~

I

i3

~

~

~~20~~0--~2*0~~4O~-6~0~~8~0~100
T A. AMBIENT TEMPERATURE (DCI

4.0
6.0
6.0
Vec. SUPPLY VOLTAGE (VI

1-83

PiI •.tO- STANDBY CURRENT
v.AMBIENT TEMPERATURE

1

! .I'

C(

!

vcc-s,sv

6

IZ

w

4

a
>
.,o

3

z

~

2

Jl

Z

.-.....,

ll!

r-- .....

rr:

;,

-l-

30

e:

20

..

10

Jl

I-

Z
w

rr:
rr:
u
:t
en
w
rr:

60

50
40
30

,g

20

;(

.s

I-

zw

rr:
rr:
;,
u
w

8
'::0
.,.,-'w
Z

.-u

,g

1·84

,
234
5
1ItRC, cYCLE RATE (MHz)

50 l-~cc=5.5V
TA-25°C

;,

,

o

;,/'

V

I-

rr:
rr:

:.

rr:

u

./

60

zw

60

W

.

V

;(

.s

I

'r)250 C
70
t-'-'Rc=175ns

;,

II.

./

Fig. 13 -NIBBLE MODE CURRENT
VI CYCl.E RATE

Fig. 12 - REFRESHCURRt:NT 1
. :' y."
.•.. SUPPLY VOLTAGE .'

~

TA-2SoC

ll!
I

O. 20 40
60
60 100
TA.AMBIE:NT TEMPERATURE; (OC)

.s

I .1

h-c ~cc-S.SV

40

CJ

:t
en
w

-20

«

60

I-

rr:
rr:

N

60

Fil. 11 .... REFRE.SH .CURRENT 1
RATE
vsCYCLE
.'

I

J
-

40

CJ

..,..

.

..

'

V
..,.".....

w

~

",.

.'

•

4.0
5.0
6.0
. vcc. SUPPLY VOLTAGE (V)

F.ig,14~ NIBBLE MOPE CURRENT
. : .lI..SUPPLY VOl.TAGE
60

tpJ'00n!

50 !--TA-25°C

c

30

.,.,-'

w

20

Z

10

0
2i

3
,g

0

-

-

4
8
12
16 .. 20
l/tpc. CYCLE RATE (MHz)

Fil: 15 - REFR.ESH CURRENT 2
vsCYCLE RATE
C(

.s

N
I-

60

I

.t

50 ~_.vcc=5.5V
TA-2SoC

Z

~40

w
rr:.
rr:

40

CJ

30

./

;,

30

:r
en

w

20

I':

...rr:w

20

rr:

.nu 10

10

.

./

t7

V

V

,g
'0

4.0
'. 5.0
6.0
Vj:C. Sl!PPLY VQ~ TAGE (V)

0

1
2
3
4
5
1ItRC. CyCLE .RATE (MHz)

IIlmm~lm!MI~llm~I~1
PUJITSU
MB 81257-80 .~~~Mm~~lm~I~~1

80

~

~

I

!

T)2S0C
70 rtRc ·17Sn.

N

I-

w

3.0

J

TA 25°C

0_

z>
0(-

Z

gj ~ 2.0

60

II:
II:

Fig. 17 - ADDRESS· AND DATA INPUT
VOLTAGE vsSUPPLY VOLTAGE

Fig. 16 - REFRESH CURRENT 2
v,SUPPLY VOLTAGE

::l

.--

wo(

U
:I:

11:1-

50

w
...'"II:
w

40

,;,
u

30

V

II:

2

......

V

,..".,..

20
4.0
5.0
6.0
Vcc. SUPPLY VOLTAGE (V)

86
0(>

.:.!;

:>~
0-

~
:z:
:>

3 .0

0(

o

z>

«;;;

o
~~

2 .0

V1H(Min.l

ffi~
II:..J

0 0

~>
• I:! ~

V1LlMax.l

I~Uo(~

0Z

VIH(~in.l

2.0

.~

~.~
III:,~
..JI-

:>::l
o~
z0(

1. 0

>z

TA c '2S0C

I~

0-

"'Cl

4.0
5.0
6.0
Vcc. SUPPLY VOLTAGE (V)

3.0

Vc~·s.oJ

0(

~Ma'.1

Fig. 19 - RAS. CAS AND WE INPUT
VOLTAGE VI SUPPLY VOLTAGE

Fig. 18- ADDRESS AND DATA .INPUT
VOLTAGE ysAMBIENT TEMPERATURE
I-

1.0

;:r

-

L--

VIL(Max.)
1.0

:z:

0(

:>

:z:

->

-20

0
20
40
60
80
100
TA. AMBIENT TEMPERATURE (OC)

o

Fig. 20 - RAS. CAS AND WE INPUT
VOLTAGE vs AMBIENT TEMPERATURE

4.0
S.O
6.0
Vec. SUPP.L Y VOLTAGE (V)

Fig, 21 - ACCESS TIME
CAPACITANCE

VI

LOAD

3.0
Vcc Ls .ov

~o

zo(:!

I~uo(~

vcJ...,.sJ
O-TA c 2SoC
V1HlMin.l

2.0

5

'I-

o·

'''
0( ..J

11:>
'

':'1-

VIL(Ma • .l

:>~ 1.0

Oz

z0(
:z:

->

-20

0
20
40
60
80
100
TA. AMBIENT TEMPERATURE (oC)

-S

-

---

i-""' .......

100 200 300 400 SOO
CL • LOAD CAPACITANCE IpF)

1-85

Ffg.22...,. OUTPUT C,UR.RENT
VI OUTPUT VOLTAGE

2

TA 25°C

«
260
!

V

I-

Z

III

a:
a:

200

//

a 160

~

I!::J

100

.:.

60

0

.9

~

k1:~
.......

V~C"4.5V

C

!

!z
III

a:
a:

:J
CJ

I

V

'/

V

Fig. 23 - OUTPU'f CURRENT
VI OUTPUT VOLTAGE

j

'.

1
2
3
4
5
'VOl.. OUTPUT VOLTAGE (V)

:cf:rrrr I
Fig; 24 -CURRENt,WAVEFORM

TAl 25"C
-125

I'

-100

I"

-75

-60

\'VCC- 5.5V

'\.'1\

"CC~4.5V

-25

o

~\

0-.

"

1
2
3
4
5
VOH. OUTPUT VOLTAGE (V)

Fig. 25.- SUBSTRATE,VOLTAGE
DURING POWER up, .

·:CFI11',I.'
o
1

-

\.t"''''25!C

l\.

i'-...
o
6OlIS/Divislon

1-86

6olis/Divilicin

','

.llfllIIWlllmll
F'U.JI"I"IIU

MB 81257-80 .1.millN~1

PACKAGE DIMENSIONS
(Suffix: .c)

DIP·1SC-A03

18·LEAD CERAMIC (METAL SEALIDUAL IN·LINE PACKAGE
(CASE No.: DIP·1SC·A03)

'\

R.050I1.2

REF

~
"\ tJ

INDEX ARE

[

J

008
.29JOlD

1
(7.49~.20
.25

..... ~

__:. .,,1 rfto9"

tJ
"i-==*='.']~I
.
.300±.OI0

.OI0±.OO2
(O.25±O.051

.047:::~:(1.20~:~:1
Cll1l87 FUJITSU LIMITED DIII035S.3C

Dimensions In

inches (millimetersl

III

~Imllllllllllllllllllllillmlllllillmlllill
FUJITSU

MB 81257-80

mllllillillllllllllllllllllllllllllillmllllill

PACKAGE DIMENSIONS

(Suffix: -C)

Dlp·16C·A04

16·LEAD CERAMIC (METAL SEAL) DUAL IN·LlNE PACKAGE
(CASE No.: DIP·16C·A04)
_ _ :=:,::::l

r-A.030(O.76)",
TVP
INDEX AREA

~

'"I.

Ir-1

[

)

J.

OOto9(

~

.300t.Ol0

--'-:::::!'=ll:::::;::::;=!]'"

== == == == == ==

·010'.002
1(O.25±0.OS)
.043(1.09)TVP
(x4 PLCS)
.2oo(S.08)MAX

.134 •. 014
(3.40.0.36)
.100'.010
(2.54'0.25)

.035'.015
(0.89.0.38)
.700(17.78)REF

.050~:~~: (1.27:g:~~)
©1987 FUJITSU LIMITEO 016044S·2C

1-88

.

Dimensions in
inches (millimeters)

_D. .m~1II
FUJITSU

MB 81257-80 _"I~

PACKAGE DIMENSIONS
(Suffix: ·PI
16-LEAD PLASTIC DUAL IN·L1NE PACKAGE
(CASE No.: DIP·16P·M031

INDEX·l

I

.260 •. 010

INDEX·2

!';::::;=;=:;::;;::::;:::;::::;::::;::::;:::;::::;:::::;:::::;::;::;~~0.25)
V LJ I
~

~

'---_ _ _ 766+.00811945+0.2)J
•
-.012
. -0.3

.033::g~;

.047:~'2

10.85:g:~)

11.2:g·3 )

.11813.0)MIN
.10012.54)

TYP

.02010.51)MIN

Dlmen,lons in
inch.. (millimeters)

e1987 FUJITSU LIMITED D16030S·2C

1-89

-

....
PWlTSU

_ _ MB 81257-80

PACKAGE DIMENSIONS
(Suffix: ·POI

.

no

008+·002'0 20+0.06)
,...O!l1·· -0.02

R.03010; 76)TVP

.4901.003
(12.4510.08)
.5271.005
113.3910.13)

'2851'0 3~: :J

17.2410.081" ..
.3221.005
18.18tO;I3)

.020(0.51)
MIN
.060(1.52)
MIN
......--1-.134+. 006 134+0.16)
-.002

• -'0.06 :

Dimensions in
4>1886 FUJITSU LIMITED C180111S-3C

1-90

inc .... (millimeters)

-_-I
F'WITSU

M8 81257-80

PACKAGE DIMENSIONS
(Suffix: -PSZ)
PIN ASSIGNMENT
LEAD
No. I

16

ZIP·16P-M01

16 LEAD PLASTIC ZIGZAG·IN·LlNE PACKAGE
(CASE No.: ZIP·16P-M01)
+008
+02
.803_:012 (20.4-0:31

112:t.OO8
(2.85±0.21

'I

I

~

INDEX

1,

.280±.008

d

J0.20

I

MAX

..... I~~

-

.060(1.271

TYP

-

.010±.002
0.25±0.051
.020±.004
(0.50±0.101

.118 3.01 MIN

,-

.100(2.541

TYP

fD n n n n n n

U U 0 0 U 0 U
OI .......lons In
Inch.. (mlilimete/ll

~1187

FUJITSU LIMITED Z11OO1S·3C

1-91

1-92

MB 81464-10
MB 81464-12
MB 81464-15

11111111111111111111111111111111111111111111111111111111111111111

June 1987
Edition 4.0

65,536 x 4 DYNAMIC RANDOM ACCESS MEMORY
The Fujitsu MB B1464 is fully decoded, dynamic random access memory
organized as 65,536 words by 4·bits. The design is optimized for high speed,
high performance applications such as mainframe memory, buffer memory,
peripheral storage and system memory for microprocessor unit where low
power dissipation and compact layout is required.
The multiplex row and column address inputs permit the MB 81464 to be
housed in a standard 18 pin DIP, 18 pin PLCC, and'20 pin ZIP. Additionally
the MB 81464 offers new functional enhancements that make it more versatile
than previous dynamic RAMs. The "~·before.RAS" refresh cycle is pro·
vided an on chip refresh capability. MB 81464 also features "page mode"
which allows high speed random access to up 256 bits within a same row.
The MB 81464 is fabricated using silicon gate NMOS and Fujitsu's advanced
"Triple Layer Polysilicon" process technology. This process, coupled with
single transistor memory storage cells, permits maximum circuit density and
minimal chip size. Dynamic circuitry is employed in the design, including the
sense amplifiers.
The clock timing requirements are non critical" and power supply tolerance is
. very wide. All inputs and outputs are TTL compatible.
• 65,536 x 4 DRAM, 18 pin Dip,
18 plnPLCC, and 20 pin ZIP.
• Silicon gate, Triple Poly NMOS,
single transistor cell.
• Row access time (tRAe),
100 ns max. (MB 81464·10)
120 ns max. (MB 81464·12)
150 ns max. (MB 81464·15)
• Cycle time (tRc\,
200 ns min. (M881464·10)
220 ns min. (MB 81464·12)
260 ns min. (MB 81464·15)
• Page cycle time (tpc\,
100 ns min. (MB 81464·10)
120 ns min. (MB 81464·12)
145 ns min. (MB 81464·15)
• Single +5V supply, 10% tolerance
Low power,
385 mW max. (MB 81464·10)
358 mW max. (MB 81464·12)
314 mW max. (MB 81464·15)
27.5 mW max. (Standby)
• On chip substrate bias generator
for high performance

• All inputs/outputs are TTL com·
patible
• 4 ms/256 refresh cycles
• Early write or OE controlled write
ca.E!£!ty
_ _ __
• "CAS·before·RAS", RAS-onlyand
hidden refresh capability
• Read write capability
• On chip latches for addresses and
DOs.
• Compatible with ~PD41254,
HM50464, and TM4464
• Stanadard 18'pin Ceramic
(Metal Seal) DIP (Suffix: ·C)
• Standard 18'pin Plastic
DIP: (Suffix: ·P)
• Standard 18 pin PLCC
(Suffix: ·PO)
• Standard 20 pin ZIP
(Suffix: ·PSZ)

ABSOLUTE MAXIMUM RATING (See NOTE)
Rating
Symbol
Voltage on any pin 'relative to vss
VIN, VOUT
Voltage on Vee supply relative to Vss
Vee
l Ceramic
Storage temperature
TSTG
I Plastic
Power dissipation
Po
Short circuit output current

-

Value
-1 to +7
-1 to +7
-55 to +150
-55 to +125
1.0
50

PLASTIC PACKAGE
DIP·18p·M03

PLASTIC PACKAGE
LCC·18P-M02

PLASTIC PACKAGE
ZIP·20P·M01-

DIP·18C·A01: See Page 22
PIN ASSIGNMENT

Unit
V
V
·C
W

mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Pin assignment for ZIP: See pege 21
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However. it is advised
that normal precautions be taken to avoid
application of :any voltage higher than maxi~
mum rated voltages to this high impedance
circuit.

I••IUIUIIIIIII i M !

81464-10

FUJITsu MB 81464~1~"
~~~lmllllillllln!11 MB '81464-15 '

Fig. 1 ~ MBc81464 BLOCK DIAGRAM

WRITE
CLOCK
GEN.

DATA
IN
BUFF.

SENS.E "'MPS
1/0 GATING

.

DQ1-DQ4.

262,l44BlT. .
STORAGE CELL

--Vee
·~Vss

CAPACITANCE

(TA = 25°C)

..
Valu~

Parameter

"Symbol'

'Uni!
Typ

. Input

..

Ca~acitanceAo.to. ~7

Data,lfOCapaci.tance.{DQ1 to·DQ4)

Max

i·

Coa

,'I~

7

pF

10

pF

7

pF

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)

Value
Parameter

Symbol

Vcc

Supply Voltage

Operating
Temperature

Unit
Min

Typ

Max

4.5

5.0

5.5

V

0

0

V

Vss

0

Input High Voltage, all inputs

V 1H

2.4

-

6.5

V

Input Low Voltage, all inputs except DO

V 1L

-2.0

-

0.8

V

Input Low Voltage, DO

V1LO'

-1.0

-

0.8

V

DoC to 70°C

" The device will withstand undershoots to the -2.0 V level with a maximum pulse width !:If 20 ns at the -1.5 V level.

DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
Parameter

Symbol

MB 81464-12

MB 81464-10

mA

mA

60

MB 81464-12

55

Icc3

MB 81464·15

50

MB 81464·10

40
35

Icc4

MB 81464-15

mA

mA

30

MB 81464-10

65

MB 81464·12

60

Icc5

MB 81464·15

INPUT LEAKAGE CURRENT any input
(OV ~ V 1N ~ 5.5V, 4.5V ~ Vcc ~ 5.5V, Vss
, all other pins not under test =OV)

"

5.0

Icc2

MB 81464-12

REFRESH CURRENT2"
Average Power Supply Current
(CA5-before-RAS; tRC = min)

Unit

57

STANDBY CURRENT
Power Supply Current (RAS = CAS =V IH)

=min)

Max

65

Icc1

MB 81464·15

REF.RESH CURRENT 1"
Average Power SuppJy Current
(CAS =V 1H , RAS cycling; tRC =min)

Typ

70

MB 81464·10

OPERATING CURRENT"
Average Power Supply Current
(RAS, CAS cycling; tRc = min)

PAGE MODE CURRENT"
Average Power Supply Current
(Fi"AS = V1L , CAS =cycling; tpc

Value
Min

mA

55

=OV,

IUL)

-10

10

p.A

OUTPUT LEAKAGE CURRENT
(Data out is disabled, 0 V ~ VOUT ~ 5.5 V)

IOQ(L)

-10

10

p.A

OUTPUT LEVEL
Output High Voltage (lOH = -5 mAl

VOH

OUTPUT LEVEL
Output Low Voltage (LOL

VOL

.

=4.2 mAl

V

2.4
0.4

V"

Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open.
Icc is dependent on input low voltage level V1LO , V1LO -0.5 V.

>

1·95

·\

MB 81464-10
MB 81464-12
MB 81464-15

AC CHARACTERISTICS

-

(At recommended operating conditions unless otherwise noted.)
Parameter
Time between Refresh

Symbol

1111111.

MB 81464-10

MB 81464-12

MB 81464-15

Min

Min

Min

Max

4

tREF

Max

4

Unit

Max

4

ms

tRC

200

220

260

ns

Read-Modify-Write Cycle Time

tRwc

270

305

345

ns

Page Mode Cycle Time

t pc

100

120

145

ns

Page Mode Read-Modify-Write Cycle
Time

tpRwC

170

195

225

ns

Random ReadlWrite Cycle Time

AccQ$s Time from RAS

~Ell

tRAC

Access Time from 'CAS

IiJIB

tCAC

100

120

50

75

ns

25

0

25

0

30

ns·

tT

3

50.

3

50

3

50

ns

tRP

80

tOFF

Transition Time
RAS Precharge· Time

RAS Pulse Width

tRAS

100

RAS Hold Time

tRSH

50

90
100000

120

100
100000

150

50

CAS Precharge Time
(All cycles except' page mode)

tCPN

30

32

35

CAS Pu Ise Width

tCAS

50

III

tCSH

100

tRCD

20

60

100000

120
50

ns

ns

40

>, .

.'

ns

tcp

RAS to CAS Delay Time

100000

75
60

100000

ns

60

CAS PrechargeTime (Page mode only)

CAS Hold Time

ns

0

Output Buffer Turn Off Delay

60

150

22

75

ns

100000
.

150
60

25

75

ns
ns
ns

CAS to RAS Set lip Time

tCRS

10

10

10

ns

Row Address SetUp Time

tAS R

0

0

0

ns

tRAH

10

12

15

ns

Column Address Se.tUP Time

tASC

0

0

0

ns

Column Address !;Iold Time

tCAH

15

20

25

ns

tRCS

0

0

0

ns

II

tRRH

10

15

20

II

tRCH

0

ID!

.,

Row Address Hol~ Time

Read

Comm~nd

Set Up Time

Read &mmand Hold Time
Referenced toRAS

ns
"

-"-

Read Command Hold Time
Referenced to CAS
Write Command Set Up Time

0

0

ns

twcs

-5

-5

-5

ns

Write Cominand Hold Time

tWCH

25

30

35

ns

Write Command Pulse Width

twp

25

30

35

ns

Write Command tC\RAS Lf/adT\rne: III

tflWL

35

40

45

ns,

1-96

MB 81464-10 111111~!~mll~mli~~lllllllm~I!I
MB 81464-12 F'UJI'I'SU
MB 81464-15 1~~lilm~II!I~III~~~Wl!!

AC CHARACTERISTICS (cont'd)

-

(At recommended operating conditions unless otherwise noted.)
Parameter

Write Command to CAS Lead Time
Data In Set Up Time
Data In Hold Time
Access Time from OE

MB 81464-10

MB 81464-12

MB81464-15

Min

Min

Min

Symbol

Unit
Max

Max

Max

tCWL

35

40

45

ns

tos

0

0

0

ns

tOH

25

35

30
27

'toEA

30

ns
40

ns

OE to Data In Delay Time

tOED

25

Output Buffer Turn Off Delay from OE

tOEZ

0

OE Hold Time Referenced to WE

tOEH

0

0

0

ns

CAS Set Up Time Referenced to RAS
(CAS-befor!l.-RAS refresh)

tFCS

20

2(l

29

ns

CAS Hold Time Referenced to RAS
(CAS-before-RAS refresh)

tFCH

20

25

30

ns

RAS Precharg!! to CAS Hold Time
(Refresh cycles)
.

tRPC

10

10

10

ns

CAS Precharll!1lme
(CAS-before-RAS cycles)

tCPI;1

30

30

30

ns

OE to RAS in active Set Up Time

tOEs

0

0

'0

ns

tozc

0

0

0

ns

tozo

0

0

0

ns

430

505

ns

DIN to OE Delay Time

m
m

Refresh Counter Test Cycle Time

III

tRTC

375

Refresh Counter Test Cycle
RAS Pulse Width

III

tTRAS

285

Refresh Counter Test CAS
Precharge Time

III

tCPT

50

DIN to CAS Delay Time

Notes:
•
An initial pause of 2oo/ls is required after power-up
followed by any 8 RAS cycles before proper device
operation .is achieved. In case of using internal refresh
counter. a minimum of 8 CAS-before-RAS initialization
cycles instead of 8 RAS cYcles are required.
iii AC characteristics assume tT = 5 ns.
II V IH (min) and V IL (max) are i"liference levels for measuring timing of input signals. Also. transition times are
measured between V IH(min) and V IL. (max).
,
II Assumes that tRco ~ tRCO (max). If tRco isgreate(
than the maximum recommended value shown in this
table, tRAC will be increase by the amount that tRco
exceeds the value shown.
II Assumes that tRCO ~ tRCO (max).

25
25

10000

0

330
60

iii

'fJ

II
II

D

III

III

30
25

10000

0

395
70

ns
30

10000

ns

ns
ns

Measured with a load equivalent to 2 TTL loads and
100pF.
Operation within the tRCO (max) limit insures that
tRAC (max) can be met. tRCO (max) is specified as a
reference point only; if tRco is greater than the specified tRCO (max) limit, then access time is controlled
exclusively by tCAC'
tRco (min) =tRAH (min) + 2tT ItT = 5 ns) + tASC (min)
Either tRRH or tRCH must be satisfied for a read cycle.
twcs is not restr-ictive operating parameter. It is included
in the data sheet as electrical characteristics only. Even if
twcs ~ twcs(min), the write cycle can be excuted by
satisfying tRWL or tcwL. specification.
Either tozc or tORO must be satisfied for all cycles.
Refresh Counter Test Cycle. only.

1-97

-,
IUII~~III~IIIIIW
PVJiTtJU

Read Cycle

ADDR~$SE$

OQ
{OUTPUT)

,

DO

(INPUT)

Write Cycle (E.rly Write)

OE: Don't care

''00

{OUTPUT)

1-98

VO.H -..,...-.....--..,..........,....----HIGH-Z:---------~--""':'""...,..-~
VOL-.

II D~n~t Care

Mil 81464-10 111111111~m!lllmlim~lmi~lm~ml
MB 81464-12 FUJITSU
MB 81464-15 1IIIIImm~llmlll!llm!mllll!m!1

OE Write Cycle

DO
(INPUT)

DO
(OUTPUT)

•

Don't ....

•

Don't ear.

Read-Modify-Write Cycle

ADDRESSES VIHVIL-

DO
(INPUT)

DO
(OUTPUT)

Note: 1) When

DE is kept high through a cycle, the DQ pins are kept high-Z state.

•

Im~MIII~imlmlmll~~lmllillllll MB 81464-10
FUJITSU

MB 81464c""12

~~m~~I~lillml~III~lm.l~m MB 81464-15

Page Mode Read Cycle

DO
(INPUT) ,

DO
(OUTPUT)

Page Mode Write Cycle
(OE=Don't Care)

,

V

ADDRESSES V IH -

IL-

DO
(INPUT)
DO
,,'
(OUTPu:r)

VOH------..........,......;......,..------HIIIGH.Z--:--1:i'-I_ _ _ _ _ _ _ _ _ _ __
,VOl::

. , Don't Ca,!

1-100

MB 81464-10
MB 81464-12
MB 81464-15

mllllllllmlllllllllllllllmllllm~llllmllll
FUJITSU
1llllllllm~lllllllllllmmlmimlmllllllll

Page Mode OE Write Cycle

ADDRESSES VVIHIL-

VIH-

-"'---++---,L

V 1L-

DO
(INPUT)

DO
(OUTPUT)

•

Don't Car.

1m! INVALID DATA
Note: 11 When OE is kept high through a cycle, the DQ pins are kept high-Z state.

1~101

.

III'
Page Mode Read Modify-Write Cycle

V

ADDRESSES

lW

VfL~

DO
(INPUT)

V,
V,

DO
(OUTPUT)

Of

V'HV'L-

'.,Don't care

RAS-Only Refresh Cycle
(WE, OE=Don't Care)

ADDRESSES V'HV'L-

DO
(OUTPUT)

------.1

VOH
VOL =====~---------HIGH-Z----------

III Oon"t Car.
1-102

MB B1464-10 Ilmlllm~illlll~~I~lllmlllll~I~!m~
MB B1464-12· FUJITSU
MB 81464-15 ~~~~~~~~~M~!~~IMim~~

CAS·before·RAS Refresh Cycle
NOTE: Addresses, WE, OE = Don't care

VOH-_____

DO

(OUlPUT)

~

__________________

vQ~

HIGH·Z:-------~---------------

III Don't care

Hidden Refresh Cycle

RAS

V1HVI~-

CAS

VIHVI~-

ADDRESSES VIHVI~ -

DO
(OUTPUT)

VOH-_ _ __
Vo~-

V1H-

VI~~-t=tO
DO
(INPUT)

~::_ _- - - - - - - - - - - - - - - - - - H I G H . Z - - - - - - - - - - - - - - - - - - - . . . . . . j

III Don't care
1-103

--

111~mIIIIIIMIIII~1I
FUJITSU,

Mllli~illlnl~III,

Refresh Counter Test Cycle

DQ
(INPUT)

,DQ,
(OUTPUT)

•

Don'tCa..

Write ,Enable:
!Je low after tozo to change the data
The rea4 mode or write mode is selected pins 'from input mode to output mode
Address Inputs:
with the Write Enable (WE) input. A and then OE, must be changed to low
A total of sixteen binary input address' ' high on WE seleCtsreaa m'otIe and low before tOED to return the data pins to
bits are required to decode parallel 4 selects write mode. The data in~uts ~re " input mode. In an early write cycle,'
bits of 262;14~hstorage ceiL, loC~tions, disabled when the~ead mode is selected. data, pins are in input mode regardless
within the MB814t;4'1';},' ' Whe!1:WEgoes I~v;, prior to,CAS,data- of. the status of OE.
E;ight row-address bits are established on ' outs will remain in',the high-impedance
Data Outputs;
the input pins (Ao through A'I) and, state all?wing a write ,Cycle.
, The three,state OUtput buffers provide
latched with the; RowAddre~r~~be
dir~ct TTL compatibility with afan out
(RAS).ihe ei!lht colurt1n-adi.lteit~biu Data Pint:
'pf two standard TTL loads. Data-out
are established on the input pins (AD Data Inputs;
are the same polarity as data-in. The
through A7) and latched.wi,tb~ the Data are written during a write or readoutputs are in the high-impedance state'
modify-write cycle. The ::Jater ,falling
Column Address Strobe (CAS),.
until CAS is brought low. In a read
The row and column atldress 'inpuuedge of CAS' WE strobesdata,into the
cycle, the, outputs go active after the
must be 'stable on 'or before the falling: on-chip data latches. In an early-write
access time interval tRAC and tOEA are
edge of RAS and CAS, respectively. ' cycle, WE is broughtJoW prior to CAS
CAS is internally inhibited (or "gated") and the data is strobed by CAS with slitisfie~. The outputs become va,lid
by RAS to', permit triggering ofrCAS as setup and hold times referenced to CAS. after'the access time has elapsed and re'mainvalid.while CAS and OEare low.
soon as the 'Row, Address HoldTime In a read-modify-write cycle, ,thus the
In a read operation, either OE or CAS
(tRAH I, specification has beel1"satisfied data will be strobed by WE with set-up
returning high brings the outputs into'
~nd ,the address inputs ,have ' been IJld hold times referenced to WE.
the high impedance state.
changed from row-addresses to column- In a read-modify-write cycle, OE must
addresses.

DESCRIPTION

or

1~104

MB 81464-10 11~~~~~li~ml~~~~mlmim~i~U~
MB 81464-12 FUJITSU
MB 81464-15 ~~~m~~~III~I~I~I~~I~11

Output Enable:
The OE controls the impedance of the
output buffers. In the high state on OE,
the output buffers are high impedance
state. In the low state on aE, the output buffers are low impedance state.
But in early write cycle, the output buffers are in high impedance state even if
OE is low. In the page mode read cycle,
DE can be allowed low through the
cycle. In the page mode early write
cycle, OE can be allowed high throughout the cycle. In the page mode readmodify-write or delayed write cycle,
OE must be changed from low to high
with toED'
Page Mode:
Page Mode operation permits· strobing
the row-address into the MB 81464
while maintaining RAS at a low throughout all suceessive memory operations in
which the row-address doesn't change.
Thus the power dissipated by the
falling edge of RAS is saved. Further,
aceess and cycle ti mes are decreased
because the time normally required to
strobe a new row-address is eliminated.
Refresh;
Refresh of the dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row-addresses
(Ao through A7) at least every four
milliseconds.
The MB 81464 offeres the following
three types of refresh.
RAS-Only Refresh:
RAS-only refresh avoids any output
during refresh because the output buffuers are in the high impedance state
unless CAS is brought low. Strobing

each of 256 row-addresses with RAS
will cause all bits in each row to be refreshed.
Further RAS-only refresh results in a
substantial reduction in power dissipation.
CAS-before-RAS Refresh;
CAS-before-RAS refreshing available on
the MB 81464 offers an alternate refresh method. If CAS is held low for
the specified period (tFCS) before RAS
goes to low, on ch ip refresh control
clock generators and the refresh address
counter are enabled, and a internal
refresh operation takes place.
After the refresh operation is performed, the refresh address counter is
automatically. incremented in preparation for the next CAS-before-RAS
refresh operation.
Hidden Refresh:
Hidden refresh cycle may take place
while maintaining latest valid data at
the output by extending CAS active
time.
In MB 81464, hidden refresh means
CAS-before-RAS refresh and the internal refresh addresses from the counter
are used to refresh addresses i.e., it
doesn't need to apply refresh addresses,
because CAS is always low when RAS
goes to low in the cycle.
CAS-before-RAS Refresh Counter Test
Cycle:
A special timing sequence using CASbefore-RAS counter test cycle provides
a convenient method of verifying the
functionality of CAS-before-RAS refresh activated circuitry. After the
CAS-before-RA!> refresh operation, if

CAS goes to high and goes to low again
while RAS is held low, the read and
write operation are enabled. This is
shown in the CAS-before-RAS counter
test cycle timing diagram. A memory
cell address, consisting of a row address
(9 bits) and a column address (9 bits),
to be accessed can be defined as follows:
*A ROW ADDRESS - All bits are
defined by the refresh counter.
• A COLUMN ADDRESS - All the bits
Ao to A7 are defined by latching
levels on Ao to A7 at the second
falling edge of CAS.
Suggested CAS-before-RAS Counter
Test Procedure
The timing, as shown in the CAS-beforeRAS Counter Test Cycle, is used for the
following operations:
1) Initialize the internal refresh address
counter by using eight CAS-beforeRAS refresh cycles.
2) Throughout the test, use the same
col um n address.
3f Wrhe "low" to all 256 row address
on the same column address by using
normal early write cycles.
4) Read "low" written in step 3) and
check, and simultaneously write
"high" to the same address by using
internal refresh counter test cycles.
This step is repeated 256 times, with
the addresses being generated by
internal refreSh address counter.
5) Read "high" written in step 4) and
check by using normal read cycle for
all 256 locations.
6) Complement the test pattern and
repeat step 3). 4) and 5).

1-.105

•
Fig. 2 - CURRENT WAVEFORM (Vee =5.5 V, TA = 25°C)

Read/WriteCvel'

LongCVele

I-- t- '

Ir- I1'-

' 't- t- f-'

J;:: 1=

o

V\

0

~,

,
rv
1/\

,,/

J

f\.
,

ll-l- t-

II
1'- I- kI

5Ons/Oivisio\,

,lIAS

I-

eM

I-

-

,r""'

6E
E
150

100
50

Ir- t- --:,

,

'"'

r- I-

"
I

"",

rv 1\ I\.

'\. IJ 1ft

ill

I

\

I\,
SOns/Division

1-106

CAS"-before-liAS Refresh Cycl.

,

200

1.ll

'.J 1\

.'

RAS' only Ref .... h Cycle

.--

n

f

r\

IJ

J \
\/

111

"'"" 1'- Iv- -

IA
I'-

1\

[l
J1\

V

MB 81464-10 li~~~I~mlllllllmlll~1111
MB 81464-12 FUJITSU
MB 81464-15 IMllillllllllllWUW

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - NORMALIZED ACCE.SS TIME
VS. SUPPLY VOLTAGE
w

::i:

i=
en

m

o

~

e
~
::;

1.3

i=

1. 1

8«

1. 1

~

1.0

1.0

.; O.B

«

60

I-

60

a:
a:

40

"'"

e

:::;

«

...

[j

10

a:

oz

o

«

;(

TA=26"C
Vee = 6.6V

/

I-

/

SO
40

...0

w

6

~

«
a:

z
i=

Z

...........

.......... ~

30

.!.' 20

4.0
6.0
5.0
Vee. SUPPLY VOLTAGE (V)

Fig. 8 - STANDBY CURRENT
VS. SUPPLY VOLTAGE
;(

,§
I-

~

60~~---r--+---r--+--~

~

50r-~---r--+---r-~--~

...ow

T A =26"C
tRe = 230ns

w

:J
0
I!l

[j
1
2
3
4
S
lItRe. CYCLE RATE (MHz)

70

Z

a:
a:

V

BO vee. 5.SV

BO

,§

/

70 tRe· 230 ns

~

O.B

Fig. 6 - OPERATING CURRENT
vI.SUPPL Y VOLTAGE

;(

i=

""

Fig. 5 - OPERATING CURRENT
VI. CYCLE RATE

~

a

~

-20 0
20
40
60
80 100
T A• AMBIENT TEMPERATURE (OC)

Fig. 7 - OPERATING CURRENT
VI. AMBIENT TEMPERATURE

w

~

,

1:

.!.'
0

0.9

4.0
S.O
6.0
Vee. SUPPLY VOLTAGE (V)

30

i=
« 20
a:
w

:;;

r--..... r--......

Z
w

0

1.2

w

1:

z

Vee !5.0V

!l!

~ 0.9

:J
0
I!l

1.3

1.2

oz

:(

w

::i:

T A =25·C

«

,§

Fig. 4 - NORMALIZED ACCESS TIME
VI. AMBIENT TEMPERATURE

40r-~---r--+---r-~--~
30r-~---r--+---r-~--~

[j

.!.' 20

-~~~~0--~2~0~4~0~~~~~B~0~1~00
TA, AMBIENT TEMPERATURE (OC)

Z

w

a:
a:

4r-~--~--+-~---+--~

a
>
CD
e

~

2~-+--4---+--4---+--~

N

Jl

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

1-107

II

II~M!llli~lmll~iH!lmll MB 81464-10
PU.JITSU M.B 81464-12
IIOOI!!~IIIII~llmlln~1111 MIS 81464-15

Fig. 10 - REFRESH CURRENT 1
VI CYCLE RATE

Fig. 9- STANDBY CURRENT
AMBIENT TEMPERATURE

VI

6

VCC

~ 5.SV

«
E

5

60

T A =25°C
VCC = 5.5V

50

I-

4

-

t-- to--

3

z·
w

2

0::
0::
::l
0

iliw
0::

IL
W

.. /

40
30

./

20

V

0::

1

cO

2

....

Fig.i1 _ REFRESI-ICURRENT 1
VI. SUPPLY VOLTAGE

«

80
70

TA = 25"C
tRC'! 230no

0

w

0::
0::
::l
0

60

IL

.

50

I-

50

0::
0::
::l

40

0

w

30

:E
w

20

-- -----

40

0::

cO 30

0

20

...

60

...0

c·

I-

50

a:0::.

40

::l

w

....

•
0

2

30

-

I-- ~

20

E
N

0::
0::
::l
0·
l:

r:l

a:

IL

w

0::'

10

Iii0

60

TA = 25°C
Vcc·5.5V

50

./

40

1/

30

V·

20

I

V

10

2

0 It
v

1~108

<.
I-

:t

W·

cr
0('

2
4. 6
8
10
I/tpc. CYCLE RATE (MHz)

Fig. 14 .,.. REFRESH CURRENT 2
v.s.CYCLE RATE.

w

0

~

V

2

Z

0

0,

10

0

.

TA = 25"c
tRC· 12000

... ~

0(

Fig. 13 - PAGEM.ODE CURRENT
YI •. CYCLE RATE.

«
E

~

Cl

4.. 0
5.0
6.0
Vec. SUPPLY VOLTAGE

Z
w

=

TA 25°C
Vcc=.5.5V

0

'<

W

2

60

0

iliw

It

1
2
3
4
5
I/tRC. CYCLE RATE (MHz)

Fig: 12 ...:: PAGE MODE CURREN"
VI CYCLE RATE

«
E
zw

I-

Z

10

0

-20
0
20
40
~
80 100
T A • AMEUENT TEMPERAtURE (Oc)

E

/'

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE IV)

o

.
2.3
4
5
I/tRc. CYCLE RATE (MHz)

Fig. 16 - ADDRESS AND DATA INPUT
VOLTAGE VI. SUPPLY VOLTAGE

Fig. 15 - REFRESH CURRENT 2
VI. SUPPLY VOLTAGE
;(

~
fZ
W
a:
a:

a

80

70

~

TA = 25°cl
tRe = 230 ns

l:!

en ~2.0 I - - V IH Min)

50
40

30

u
J}

20

on

..V

V

....

~ >
~~

~ .-v~ax)

>~

«

Fig. 17 - ADDRESS AND DATA INPUT
VOLTAGE VI. AMBIENT TEMPERATURE

~5.0V
VIH Min)

0

1.0

.-

0-

r

Vee

~

V~

z

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

0

~

ffia: ...J~

00

W

a:

TA = 25°C

~>
<-

60

i}i
u.

3.0

o

o

:>

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

Fig. 18 - RAS, CAS, WE AND OE INPUT
VOLTAGE VI. SUPPLY VOLTAGE

~
c
z

3.0
TA = 25°C

«
~~

~«~

.W

2.0

f-

V IH IMin)

~ t-""

• ...J

V IL /Max)

~

~~

j~

0

-

:>~

1.0
VILjMaX)

0-

z

«
r

0
-20
0
20
40
60
80
100
T A. AM81ENT TEMPERATURE (oC)

:>

r

:>

0

en,

I~

Fig. 19 - !flU.
WE AND OE" INPUT
VOLTAGE VI. AMBIENT TEMPERATURE
3.0

o
z

Vee

1m~ 2.0

vIIi

!
Min)

>~
0-

en
en

w

0

1.0

~

VIL tax)

z

r

U

25 T -2SoC
A
Vee =4.SV
20
15
10



w
::;

.i=

~~
~
I c5
a:>
~~

Fig. 20 - ACCESS TIME
LOAD CAPACITANCE

VI.

~ 5.0V

«

Iw>
~-

4.0
5.0.
6.0
Vee. SUPPLY VOLTAGE (V)

0

V

V

-5
0
20
40
60
80
100
TA. AMBIENT TEMPERATUAE (oC)

1 00 200 300 400 500 600
CL. LOAD CAPACITANCE (pF)

h109

MB 81464-10
MB 81464-12
MB 81464:'15

D

Fig. 22 -OUTPUT CURRENT
"VI. OUTPUT VOLTAGE

Fig. 21 -QUTPUT CURRENT
VI. OUTPUT VOLTAGE
300

-150

1

250

.§ -125

ffi

200

::I

150

I-

a:
a:

(.)

I::I

Vee = 5.5V

,.

I!:::I

100

.:.

50

~

.i V

-

iii-lOa

V

a -'-75

I-

:

23456

Fig:~3.:..sdBStRATEVOLTAGE
. OURING POWER UP

o
i

':'25

'.

r.
1

".

l\
..... TA = 25°C

....• I.······· \.

""
t\.:

_4
60

~ee=5.5V

o

\.

'" ,"
.....

"50
yee= 1:
,"-

0123456
V OH • OUTPUT VOLTAGE (V)

Fiil- '24";' CURRENT WAVEFORM
DURING POWER UP'

:LJ?t

,... --..,'.

1-110:

-50

::I

VOL. OUTPUT VOLTAGE (V)

o

~

.9

O·

\.

.a:
a:

:

a

\

'1-

/. :::.-.. VCc:· s4.5V

0

.9

~A = 25°~

;(

1~

150

200

~

250. 300

1·1·· 1

1

....

MB 81464-10 1II~.lIImllllllmlll
MB 81464-12 F'WI"I'BU
MB 81464-1$

PACKAGE DIMENSIONS

(Suffix: ·PI

18 LEAD PLASTIC DUAL·IN·LINE PACKAGE
(CASE No.: DIP·18P·M03)

I

"1f'=;;;;;;:==:=:1~16'

.260'.010
(6.60.0.25)

!{::;:::r;r==r=r=;r=;=r:;:~::;::;:::;:~~
1------.868::~~:(22.06:~:!~)-----.-i1
.049(1.26)
MAX

.047:~12(1.20:~·30)

MAX

.300'.010
(7.62'0.25)

(~~g;~g~)

.197(5.00)MAX

.118(3.0)MIN
.100(2.54)
TYP

I

© FUJITSU LIMITED1985 D18011S·2C

Dimensions in
inches (millimeters)

1-111

••

1IIIm~~llllli~IIIIIIII~lmm~illml~J' M. 8'M64-10"
PUJITSU' M.'1464-12
m.WIIIII.' MBM464-15

PACKAGE DIMENSIONS

(Suffix: ·PO)

1'B-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC'1BP·M02)
000 +. 002 (0 20+ 0 .05.)
.. "-.00.1 . -0.02.
. R.030(O.76)TVP

[lo

.49(t±:003'
(12.45.0.06)
.527 •. 005
(13.39±0.13)

~~.

I-....::===I=f==t:·n:::r.285±"'CT1:.003

.

(7.?4±0.1)8)

.322±.005
(8.18±0.13)

.

.1)20(0.511

MIN
.060(1.52)
MIN
,. "

-11

.050(1.271

rVp

J."o--~-+-.134+·006(3.4+0.151
. .,.0112
-0.05
©FUJIT~U

LIMITED 1986 C1801aS:aC
Dimensions in
inches (millimeters)

1·112

PACKAGE DIMENSIONS
(Suffix: ·PSZI

(TOP VIEW)

20-LEAD PLASTIC ZIGZAG·IN·LINE PACKAGE
(CASE NO.: ZIP·20P·M01)

C

.112 •. 008
(285.021

1--------l.019~:g~:(25.88~g:!~II------·-t1

d

IJo.25

INDEX

.260'.010
1

' .32sJ261MAX

~~.~
~~

.010'.002
(0.25'0.051

-

.050(1.27ITVP

-

.020<.004
(0.50'0.101

.118(3.0IMIN

---.i
.100(2.54ITVP

Lrr-. n n n n n n n n
L:]

U U U U U U U U

@FUJITSU LIMITEDlga6 Z20001S·3C

Dimensions in
inches (millimeters) .

Mil 81464.10
MB 81464.12 .
MB 81464.15

PACKAGE DIMENSIONS
(Suffix: -C)

DIP-1SC-A01

18-LEAD CERAMIC (METAL SEAL) DuAL IN-LINE PACKAGE
(CASE No.: DIP-1SC-AD1)

.100•. 010
(2.54'0.25)
.800(20.32)REF

@FUJITSU

LI~ITEO

1987 D18014S-4C

Dimen,sions in

inches (millimeters)

Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semic.onductorapplications; consequently, complete information sufficient for construction pur·
poses is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, such in·
formation does not convey to the purchaser of the semiconductor
devices described herein any license under the patent rights of
Fujitsu Limited or others. Fujitsu Limited reserves the right to
change device specifications.

--------------Section 2 --+------

CMOS DRAMs

Page

Device

Maximum
Access
Tlme(ns)
Capacity

2-3

MB81C258-10
MB81C258-12
MB81C258-15

100
120
150

262144 bits
(262144w X lb)

16-pln Plastic
18-pad Plastic

2-25

MB81C466-10
MB81C466-12
MB81C466-15

100
120
150

262144 bits
(65536w x 4b)

18-pln Ceramic DIP
DIP
18-pln Plastic
ZIP
20-pln Plastic

Metal
Plastic
Plastic

2-41

MB81Cl000-70
MB81Cl000-80
MB81Cl000-l0
MB81.Cl000-12
MB81Cl001-70
MB81Cl001-80
MB81Cl00l-10
MB81Cl001-12

70
80
100
120

1048576 bits
(1048576w x lb)

Metal
Plastic
Plastic
Plastic

1048576 bits
(1048576w x lb)

Ceramic
Plastic
Plastic
Plastic
Plastic
Ceramic
18~pln Plastic
26-pad Plastic

DIP
DIP
ZIP
LCC

70
80
100
120

18-pln
18-pln
20-pln
26-pad
20-pln
18-pln

ZIP
DIP
DIP
LCC

Plastic
Metal
Plastic
Plastic

2-81

MB81Cl002-85
MB81Cl002-10
MB81Cl002-12

85
100
120

1048576 bits
(1048576w x lb)

18-pln
18-pln
20-pln
26-pad

Ceramic
Plastic
Plastic
Plastic

DIP
DIP
DIP
LCC

Metal
Plastic
Plastic
Plastic

2-105

MB81Cl003-85
MB81Cl003-10
MB81Cl003-12

85
100
120

1048576 bits
(1048576w x lb)

18-pln
18-pln
20-pln
26-pad

Ceramic
Plastic
Plastic
Plastic

DIP
DIP
ZIP
LCC

Metal
Plastic
Plastic
Plastic

2-123

MB81C4256-85
MB81C4256-10
MB81C4256-12

85
100
120

1048576 bits
(262144w x 4b)

20-pln
20-pln
20-pln
26-pad

Ceramic
Plastic
Plastic
Plastic

DIP
DIP
ZIP
LCC

Metal
Plastic
Plastic
Plastic

2-147

MB81C4257-85
MB81C4257-10
MB81C4257-12

85
100
120

1048576 bits
(262144w x 4b)

20-pln
20-pln
20-pln
26-pad
26-pad

Ceramic
Plastic
Plastic
Plastic
Ceramic

DIP
DIP
ZIP
LCC
LCC

Metal
Plastic
Plastic
Plastic
Metal

2-61

Package
Options

Sealing
Method
DIP
LCC

Plastic
Plastic

2-1

CMOS DRAMs
(Continued)

Page
2-175

MB81C4258-85
'MB81C4258-10
MB61C4256-12

85
100
120

. 2-199

MB81C4259-85
t.l!B81 04259-10
,MB81C4259-12

85;
100
120

2-225

2·2.

Device

Maximum
Access
Tlme(ns) capacity

MB8141'6o-80
,MB8141.00-10
.. MB&1A 1·00-12

80
100
120<

Package
Options'

Sealing
Method

20'-pln Plastic
26.,pl!d Plastic
20-pln . Ceramic
20-pln Plastic

Plastic
Plastic
Metal
Plastic
Metal
Plastic
Plastic
Metal
Plastic
Plastic
Plastic
Plastic

ZIP
LCC
DIP
DIP
20-pln .ceramic DIP
1048576 bits
(262144w x 4b)
20-pln Plastic
DIP
ZIP
20-pln Plastic
26-pad ,Ceramic LCO
26-pad Plastic
LCC
DIP
4194304 bits
18-pinPlastlc
(4194304w x 1b.) .20.;pln ,Plastic
ZIP
. 26-pad .Plastlc
LCC
1048578 bit.
(262144w x 4b)

MB81C258-10
MB81C258-12
MB81C258-15

262,144 x 1 BIT CMOS STATIC COLUMN DYNAMIC RAM

October 1988
Edition 3.0

The Fujitsu MB 81 C258 is CMOS static column dynamic random access memory, SC-DRAM, which is organized as 262144 word by 1 bit_ This SG-DRAM is
designed for high speed, high performance applications such as main frame
memory, buffer'memory, and video memory, and,for applications to battery
backed-up systems wh~re very low power dissipation and compact layout is
required.
The advantage of SC-DRAM is achieving the static mode operation such as
read, write and read-modify-write cycles in spite of dynamic RAM and the
fast read and write operation can be performed by this mode.
The M881C258 is fabricated using silicon gate CMOS process. Since the
CMOS circuit dissipates very small power, it can be easily used in battery
backed-up application system such as hand held computer.
The MB 81 C258 is pin compatible with HM 51258.
Air inputs and outputs are TTL compatible.
•
•
•

•

•

•

262144 x 1 SC-DRAM, 16-pin
DIP/18-pin PLCC
Silicon-gate, CMOS, single
transistor cell
Row Access Time (tRAC),
100 ns max. (M881C258-10)
120 ns max. (MB81C258-12)
150 ns max. (MB 81C258-15)
Random Cycle Time (tRC),
200 ns min. (MB 81C258-10)
230 ns min. (MB 81C258-12)
260 ns min. (M881C258-15)
Address Access Time (tAA),
45 ns max. (MB 81C258-10)
55 ns max. (MB 81C258-12)
70 ns max. (M881C258-15)
Static Mode Cycle Time (tscl, '
50 ns min. (MB 81C258-10)
60 ns min. (MB 81C258-12)
75 ns min. (MB 81C258-15)

•

•
•
•
•
•

Low Power Dissipation
330 mW max. (M881C258-10)
275 mW max. (MB 81C258-12)
248 mW max. (MB81C258-15)
11 mW max. (TTL level input)
1.65 mW max. (CMOS level input)
Single 5V supply, ±1 0% tolerance
32 ms/256 refresh cycles
RAS-Only, CAS-before-RAS, and
Hidden refresh capability
Standard 16-pin Plastic DIf'
(Suffix: -PI
Standard 18-pin Plastic LCC
(Suffix: -PO)

PLASTIC PACKAGE
DIP-16P-M03

PLASTic PACKAGE
LCC-1SI>-M02

PIN ASSIGNMENT
Vss

CAS
DOUT
A6
A3
A4
A6

A7

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Voltage on any pin relative to Vss

V 1N , V OUT

-1 to +7

V

Voltage on Vcc relative to Vss

Vcc

-1 to +7

V

Storage Temperature

TSTG

-55 to +125

°c

Po

1.0

W

50

mA

Power Dissipation
Short Circuit output current

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to pro-tect ,the
inputs against damage due to high static' \/01.1-

ages or electric- fields. However, it. is ,qvised
that normal precautions be taken to wold
application of any voltage highe'r than "maximum rated voltage. to. tl)i, high impedance
circuit.

2·3

">IIMmiIIIMllml~I~':MB81C258;;10

f'V.JITSv. MB81C258-12
,llllm~~lmllmIIWI~~~~lllm~iml" "NUlflC258-15

Fig. 1 - BLOCK DIAGRAM

RAS

...-------1

CLOCK
GpN.2

)

,

DATA
IN
BUFFER

COLUMNJ:=:::~=~
ADD.

COLUMN
~__
D_EC_O_D~ER_'__~

1--l-l~+=r'

BUFFER

ROW
ADD.
BUFFER

262.144 BIT
STORAGE CELL •
DOUT

-Vee
-Vss

CAPACITANCE ITA = 25°C, f =1 MH:i!)
Parameter

Symbol

Typ

Max

,Unit

pF.
Input'Capacitance.RAS.
"

','

•.

,,'

",

cAs, WE

10

,>

COUT

pF

MB81C258-10 1111111111111111111111111111111111111111111111111111
MB81C258-12 FUJITSU
MB81C258-15 1IIIm~mlmmlllmmlmllllm~mlmllll

RECOMMENDED OPERATING CONDITIONS
(R eferenced to V ss)
Parameter

Symbol

Min

Typ

Max

Unit

Vcc
Vss

4.5
0

5.0
0

5.5
0

V

inpu~

V 1H

2.4

-

6.5

V

Input Low Voltage, all inputs

V 1L

-1.0

-

0.8

V

Supply Voltage
Input High Voltage, all

Operating
Temperature

O·C to +70·C

DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted)
Values
Parameter

Conditions
M881C258·10

Operating Current"
(Average power
supply current)

M881C258·12
MB81C258·15

Standby Current
(Power supply
current)

TTL level
CMOS level

CAS = V 1L or V 1H ,
RAS cycling;
t RC = min

Symbol

ICCl

RAS = CAS = V 1H
RAS = CAS~ V cc -0,2V

Icc2

MB81C258·10
Static Mode
Current"

MB81C258·12

RAS = CAS = V 1L ,
RAS cycling; tsc = min.

ICC3

MB81 C258· 15
CAS·before·RAS
Refresh Current*
(Average power
current)

MB81C258·10

Unit
Min

Max

-

60

-

50

-

45

-

2.0

-

0.3

-

40

-

35

-

30

-

55

-

45

-

40

-10

10

mA

RAS cycl ing,
CAS·before.RAS;
t RC = min

Icc4

OV ~ V 1N ~ 5.5V,
Vcc = 5.5V,
Vss = OV; pins not
under test = OV

IUL)

Output Leakage Current

OV ~ VOUT ~ 5.5V;
Data out disabled

10(L)

-10

Output High Voltage

10H = -5mA

V OH

2.4

-

Output Low Voltage

IOL =4.2mA

VOL

-

0.4

Input Leakage Current

MB81C258·12
MB81C258·15

mA

mA

mA

/lA
10

V

NOTE: *; Icc depends on the output load operating speed. The specified values are with the output pin open.

1IIIIIIImll l l l l l l l l l l l lilimilIDIIII

,MB81C258-1O

FUJITSU

M881C258~12

,.llllmmllllllmlllllm~llmlllllll~~~m~ ,M881C258-15

AC CHARACTERISTICS

-

(At Recommended operating conditions unless otherwise noted)
Parameter

MB 81C258-15

Min

Max

Min

Max

Min

32

-

tREF

-

t RC

200

Read-Modify-Write Cycle Time

t RWC

245

lUI

Access Time from RAS

t RAC

-

-

-

100

-

Unit
Max

32

-

32

230

-

260

,-

ns

285

-

325

-

ns

-

120

-

150

ns

30

-

35

ns
ns

ms

Access Time from CAS

t CAc

Output Buffer Turn off Delay Time

tOFF

0

25

0

25

0

30

Transition Time

tT

3

50

3

50

3

50

ns

45

-

55

70

ns

-

ns

35

ns

140

ns

-

ns

Ellil

Column Address Access Time

tAA

Output Hold Time from Column
Address Change

tAOH

Access Time from WE Precharge

t WPA '

Access Time Relati~eto last
Write

iii

tAl.W

25

-

-

5

-

25
90

5

-

Write Latched Data Hold Time

tWOH

0

-

0

RAS Precharge Time

tRP

90

-

100

30
110

-

5

0
100

ns

RAS Pulse Width

tRAS

65

100000

i5

RAS Hold Time'

tRSH

25

-

30

-

CAS Pulse Width (Read)

tCAS

,25:

100000

30

100000

35

100000

ns

CAS Pulse Width (Write)

teAS

'15

100000

20

100000

25

100000

ns

CAS Hold Time CRead)

tCSH

100

CAS Hold Time (Write)

tCSH

80

RAS to CAS Delay Time

tRCD

25

CAS to RAS Set Up Time ",

tCRS

20

tASR

0

Column Address Hol1l Time
F!AS to Column Address Delay
Time
Column AddreSs Hold Time
Reference to FfAS
Write Address Holcl,Time
Referenced to F!AS

-

75

.,.

25

90

120

25

-,
-

100000

35

150
115
30
30

ns
ns

115,

-

ns
ns
ns
ns

tRAH

15

tASC

0

-.,:

o"

tCAH

20

-

25

-

30

-

ns

lUI

tRAD

20

55

20

65

25

80

'ns

tAR

lOQ '

-

120

150

-

ns

tAWR

80

-

90

110

,-

ns

tRAL

45 ,,:

. ..:

55

tAHR

15

-

15

•

",

Read Address toRAS,Lead Time
Column Address Hold Time
ReferenC!id,to RAS F!i~in!l TIme'

95

95

fI
fI

Row Address Hold Time
Column AddreSS SetUp Time

-

100000

-

Row Address Set Up Time

.

MB 81C258-12

Symbol

Random Read/Write Cycle Time

Time Between Refresh

b1iliii&iEi

MB 81C258-10

IIIr

,

0
15

-

0
;20
0

70
20

~

-

ns
ns
ns

ns
ns

MB81C258-10
MB81C258-12 FUJITSU
MB81C258-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

AC CHARACTERISTICS (Cont'd)

--

(At Recommended operating conditions unless otherwise noted) 1~~~.1Il6
MB 81 C258-1 0

MB B1C258-12

MB 81C258-15

Min

Max

Min

Max

Min

Max

t LWAO

20

45

20

55

25

70

ns

Column Address Hold Time
Referenced to Last Write

tAHLW

90

-

110

-

140

-

. ns

Read Command Set Up Time
Referenced to CAS

tAcs

0

-

0

-

0

-

ns

-

ns

Parameter
Last Write to Col limn Address
Delay Time

III lEI

Symbol

Unit

Read Command Hold Time
Referenced to RAS

II

tAAH

10

-

10

-

10

Read Command Hold Time
Referenced to CAS

II

tACH

0

-

0

-

0

-

20

-

20

30
30

WE Pulse Width

25

-

25.

--'

twp

15

WE Inactive Time

tWI

15

Write Command Hold Time

t WCH

15

Write Command to RAS Lead
Time

tAWL

25

-

Write Command to CAS Lead
Time

tCWL

25

-

t AWO

100

-

120

-

35

RAS to WE Delay Time

III

20

I'· -

35

-

35

-

25

150

ns
ns
ns
ns

-

'ns
ns

-

ns

tcwo

25

-

30

Column Address to WE Delay
Time

tAWO

45

-

55

-

70

-

RAS to Second Write Delay
Time

tASWO

105

-

125

-

155.

-

ns

Write Command Hold Time
Referenced to RAS

tWCA

80

-

95

-

115

-

ns

RAS Precharge Time from Last
Write

t APLW

135

-

155

-

165

-

ns

tws

0

-

0

-

0

-

CAS to WE Delay Time

Write Set Up Time for Output
Disable
Write Hold Time for Output
Disable

III

ns
ns

ns '.'
..'

III

tWH

0

-

0

-

DIN Set Up Time

tos

0

DIN Hold Time

tOH

20

-

DIN Hold Time Reference to
RAS

tOHA

80

-

90

-

Refresh Set Up Time for CAS
Referenced to RAS
(CAS-before-RAS cycle)

tFcs

20

-

25

-

0
25

0
0
30
110

30

-

ns

-

ns

_.
-

ns

ns

ns

2·7

,mm~~~m~mlillmlmlllllillmlmim

'MB81C258-01O
MB81C258-12
111111111111~m~~~lwm~~lloollllmlllll ;MB81C258-15
FUJITSU

..

AC CHARACTERISTICS (Cont'd)

(At Recommended operating conditions unless otllerwisf noted) ,IIII.II~
Parameter
Refresh Hold Time for CAS
Referenced to RAS
'(~~l>efore.RAS cycle)

Symbol

t FCH

MB81C25B·l0

MB B1C25,B·12

MB 81C258·15

Min

Max

Min

Max

Min

Max

20

-

25

-

30

-

hS

Unit

,

,

CAS Precharge Time
(CAS·before·RAS cycle)

tCPR

20

-

25

-

30

-

ns

RAS Precharge Time to CAS
Active Time (Re~resh cycles)

tRPC

20

-

20

-

20

-

ns

Static Mode Read/Write Cycle
Time

tsc

50

-

60

-

75

-

ns

Static Mode, Read·rylodify.
Write Cycle Time

tSFiwc

95

-

115

-

145

-

ns

tcp

15

-

20

-

25

-

hS

St~ticM()deCAs Prech~rge
Time

"

I·

Refresh Couriter Test Cycil!'
Time

lIB.

tRTC

440

-

520

-

610

-

ns

Refresh Counter rest RAS
Pulse Width

lIB

,tTRAS

340

10000

410

10000

500

10000

ns

Refresh Counter Test CAS
.,
Precharge Time

II

' t CPT

50

-

60

-

70

-

ns

Refresh Counter Test CAS to
Col. AddresS: Delay Time

III

tCADT

-

100

-

120

-

150

ns,

Refresh Counter Test Accen
Time from CAS

IIiI

" tCACT

135

-

165

-

205

ns

lB.

tcwDT

-

165

-

205

-

ns

Refresh Counter Test
to WE D,lay Time

CAS:

:...

135

NOTES:
,
DAn Initialpausa (RAS m CA! =.Ylli) Of 200jlS is raquired after
,
power·up fOllowed bV any,B RAS-only cycles bafore propar
davica operation' is' achiavad. In case of' using Internal 'afresh
counter, a minimum of 8 CAS-befora·RAS initialization cycle,
instaad of 8 J!iAI eycla. are raqulred.
II AC characteristics assume tT" 5ns, VIN = OV to aV;:VIH = 2.4V,
VIL = O.8V,VoH- 2.4V,and VOL = O.4V.
'
'.'A.sume. tharlRAD oS tRAD (max). If tRAD i. greeter than the
,me~imum recommandad value shown in ,this teble, tRAC 'will be
increased by the amount that tRAD exceeds the value shown.
Assume. that tRAD 2:. tRAD (mex).
MI!",!~,red with a load equlvaleM to 2 TTL,loads and 100pF.
ASSumes that tLWAD oS tLWAD (max). If tLWAD is greater than
,
thamaximum racommendad velua shown in thistable, tALW will
be increasad by tha amount that t"':WAD .xceedi thavalua shown.
Write Cyela Only.
'
, Operation within :the tRAD (max) limit insures thet tRAC (maxi
can be' nist. tRAD (max) Is spaclfilld as a referanca point only;

I
I

I

I

if tRAD is greater than tha specified tRAD (max) limit, than
access tima is controlled by tAA'
tRAD (min) • tAAH (min) +tT itT· 5MS)
~iS specified to latch column addre.. by the ri.ing edge of

ID Operetion within the tLwAD (max) limit insures that tALW (max)
can be met. tLWAD (max) is specif,ied esa reference point only;
if tLWAD is greeter than the spacified tLWAD (max) limit, then
eccass tima is controlled by tAA'
,
'
tLWAD (min) = tCAH (min) + tT (tT = ,5ns).
Either tR Rli or tRCH must be satisfied tot e read cycle. "
tws, tWH, and tRWD are specified as a reference point only.
If tws :2:. tws (min) and tWH 2:. tWli (min), the deta output pin
will remain ,HiQh·Z state throughout e.MIire eyole. It tRWD 2:.
tRWD (min); The date' output wil' contein deta read from the
selected cell.
III CAS·before.RAS refresh counter. test eycle only.

I

MB81C258-10 mlllmmlllm~lmm~llllllmlmmllllm
MB81C258-12 FUJITSU
MB81C258-15 1IIIm~llm~mllllllllllm~lmmlll~~~11

Read Cycle
f---------tRc-------------t
1-------tRAS---------1
RAS

V IHV IL -

~

CAS

f-----tCSH--------!
_tRP_
-tRCO-----1r------ t RSH---t:---/

~

V IH- ----i-l-~,...._--!lr---tcAs------jJ~__tII_-----~
_
I--tAHR
V IL - - - . . I I
1-•....-'.1'--.-f+----t A R - - - - - - 1 f - - - I + - I
t
~ tRAO'
tRAL----+--I

Dt~R~O~W~-~t::===~C~O~L~UM~N~==::=:).II.II.

ADDRESSES V,H::: • • •
VIL I

_

l'--tRCS
tr -,

--ir- tRRH

tRCH----l

WE

VIHV IL-

DOUT

VOH-; . . . - - - -__.....,-HIGH-Z-----,-___-1=V~A~L~ID~:}----HIGH-Z--VOL

f---tCACf---tAA-----!
f----tRAC-----I

III Don't Care
'; If t RAO ~ tRAO (max)', access time is tAA'
Write Cycle (WE Controlled)

WE

VIH------~~~~~-twp--~r----+-------~

V IL -

DOUT

--------HHIGH-Z------<~IN~V~A~LI~D~i-------. . Don'tCa..

"; Write Cycle only,

ll~lllllllllillmllllllllll~mllllll~~~llil Mll1C258-10

PUJITSUM881C258-12

1IIIIIIIIIIIIIIIIm~llmIIIIMIIII~~11111 ,MI81C258';'15

Write Cycle (CAS Controlled)

VIH- - - - - o i l
VIL-

ff-----------.,..---fI

'VIH- -..,...-r--++.,.------.l.I----tC,AS--I~,......---------_+­
VIL---.(I

ADDRESSES VIf-t~Ij--

DIN

"I
VIL-

DOUT

VO H--------HIGH-Z·t-----------......,-Val..
•

Don't Car.

*1; If tws ~ tws (min) and tWH ~ tWH (min), DOUT is high-Z.
*2; Write Cycle only.
Read-Modify-Write Cycle

VIH_ -~--.,u
VI 1,,Ilt----......;.------......;.---'-~I
f------,.tRP-----I
VIH-----r-~--~t~--~C~-----_I~,......_r----~­
~IL--_JI

•••••••••

AD~RESSES~:~= • • •t~~)I(::=:§:~~:==:)
WE

VIH VIL-

DrN'

VIHVIL-

DOUT
•

*; Invalid Data

Don'tCa..

MB81C258-10 li~mllllln~~~llm~~~iim!!~lm
MB81C258-12 FWITSU
MB81C258-15 1IIIIIIIIImli~IIIIIII~I!IIII~m~~~~I~'

Static Mode Read Cycle·

RAS

VIH_

----il

V ILtCRS

I.,....------......I,'r--------~I

VIH.:..--~H1--~1

11---I--~

V IL -

VOH- _ __
DOUT

. VOL

Don't ear.

•

*; Invalid Data.

Static Mode Write Cycle

RAS

V IHV IL-

CAS

V IH VIL-

WE

V IH V IL -

DIN

DOUT

----+-....,jJ

f-'WCH--u.--"'.I-~-lr\

V IHV IL V OHVOL

-----------HIGH-Z·--------..,---•

Don'tCa..

*; If tws ~ tws (min) and tWH ~ tWH (min), DouT is high-Z.

2-11

1~11~11~~~m!mlm~11 MB81C258-10
FUJITSU MB81C258-12
1IIIm~lmmlmllmMlm~~II! .MB81C258"15

III
Static Mode Read,Modify'Write
r------------'tRC:--------------~

RAS

1.-----------tRAS'----------~
V 1H-

VIL-

1---+--------t CSH
CAS

WE

, DIN

VIH-

V1l-

VIHV 1L -

VIHVIL-

°OUT

•

Don'teare

ISS)

Invalid Dote

Static Mode Mixed Cycle "1
r--~~--------tRC-----

RAS

CAS

WE

__-------~

1~-------~tRAS----------~
VIHVIL-

I~---i

VIHV1L-

VIHV,~ -

D,N

°OUT

VOHVOL

_Don'tCare

cs:::s:J 'Invalid Data

"1; This is an example of static mode mixed cycle,
*2; If tLWAD is satisfied its min/max value, tALW = tsc (min) t:tAA (max)

MB81C258-10
MB81C258-12 FUJITSU
MB81C258-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

RA8-0nly Refresh Cycle
(Note; WE, DIN

= Don't Care, As = V IH

or Vld

V IH - -==~~------------l••••••••1
V
IL - ------'I

DOUT

~g:~=:===t--------HIGH-Z----------BDon"tCar.

CAS-before-RAS Refresh Cycle
(Note; Address, WE, DIN = Don't Care)

1------tRC:------r--_ _ _----ir----tRAs----I~--------.

tFCS If--------~I

DOUT VOH---==j----:---HIGH_Z_______________
VOL --

2-13

Ili~i~~llml~mlmoo~mll~~ ·M'81t25a..10

FVJITSUMB81t258·12

Illmlllllll~~llmIIIMi~~llmi~IMB81C258.'5

•

Hidden RefreshCyc/e

RAS

CAS

VIHVIL V1HVIL-

v,H..,-I
V1L- • • • • •i"11~;s:~---;•••••••••••••
DOUT

VOH-----.:....-.HI(lH-,~-.:....-~C====~£!£!~~=~===)
VOL
-:•

Don't Car.

CAS-before-RASRefresh Countllf Test Cycle

RAS

CAS

AODfi'essEs

V
1HVILVIHV1L1L -•....

ViH~

V

WE
(Read)

DOUT

WE
(Write)

BDon'tCer.

2·14

MB81C258-10 m~llllllllllllllllllllllllllllmlllllllllllllli
MB81C258-12 FWITSU
MB81C258-15 ~~~~~mlm~~m~~I~mlm~~mm

DESCRIPTION
Address Inputs:
A total of eighteen binary input address
bits are required to decode anyone of
the 262,144 storage cells within the
MB 81C258. Nine row address bits
are established on the address input pins
(Ao to As) and latched with the Row
Address Strobe (RAS). The nine column
address bits are establ ished on the address input pins (Ao to Ae) after the
Row Address Hold Time has been satisfied. In read cycle, the column address
are not latched by the Column Address
Strobe (CAS), so the column address
must be stable until the output becomes
valid. In write cycle, the column addresses are latched by the later falling
edge of CAS or WE.
Write Enable:
Read or Write cycle is selected with the
WE inputs. A high on WE selects read
·cycle and low selects write cycle. The
write operation is asserted on the later
falling edge of CAS or WE (Both CAS
and WE are low). The time period of
the write operation is determined by
internal circuit,. thus .next. write operation will be inhibited during the write
operation.
Data Input:
Data is written into the MB 81C258
during write or read-modify-write cycle.
The input data is strobed and latched by
the later falling edge of CAS or WE.
Data Output:
The output buffer is three state TTL
compatible with a fan out of two standard TTL loads. Data out has the same
porality as data in. The output is in high
impedance state until CAS is brought
low. In a read cycle, the access time is
determined by the following conditions:
1. tRAC from the falli~g edge of RAS.
2. tAA from the column address inputs.
3. t CAC from the falling edge of CAS.
When both tRCO and t RAO satisfy their
. maximum limits, tRAC=tRCO+tCAC or
tRAC=tRAO +tAA ·
Data output remains valid while the
column address inputs are kept constant. However, when CAS goes high,
the output returns to high impedance
state. In the static mode, the output

data is internally latched by the later
falling edge of CAS or WE and remains
valid internally until either returns to
high.
Static Mode:
The static mode operation allows continuous read, write, or read-modifywrite cycle within a row by applying
new column address. In the static mode,
CAS can be kept low throughout static
mode operation. The following four
cycles are allowed in the static mode.
1. Static mode read cycle;
In a static mode read cycle, the
access time is tRAC from the falling
edge of RAS or tAA from the
column address input. The data
remains valid for a time tAOH after
the column address is changed.
2. Static mode write cycle,
In a static mode write cycle, the
data is written into the cell triggered
by the later falling edge of CAS or
WE. If both tws and tWH are greater
than their minimum limits, the data
output pin is kept high impedance
state through the static mode write
cycle.
3. Static mode read-modify-write cycle;
In the static mode read-m'odify-write
cycle, WE goes low after tAwo from
the column address inputs and
tcwo from the falling edge of CAS.
The data and column address inputs
are strobed and latched by the falling
edge a of WE.
4. Static mode mixed cycle,
In the static mode, read, write, and
read-modify-write cycles can be
mixed in any order.
In the next read cycle of static mode
write cycle or read-modify-write cycle,
the access time is determined by the
following conditions.
1. tALW from the falling edge of
WE at previous write cycle.
2. tAA from the corumri address inputs.
3. tWPA from the rising edge of WE at
the read cycle.
4. tCAc from the falling edge of CAS .
Refresh:
Refresh of. dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row addresses
(Ao to A7) aUeast every 4ms.

The MB 81 C258 offers the following
three types of refresh.
1. I1AS" only refresh;
The RAS-only refresh avoids any
output during refresh because the
output buffer is high impedance state
due to CAS high. Strobing of each
256 row address (Ao to A7) with
RAS will cause all bits in each row
to be refreshed. During RAS-only
refresh cycle, (either V IH or V Id
is permitted to As.
2. CAS-before-RAS refresh;
CAS-before-RAS refreshing available
on the MB 81 C258 offers an alternate refresh method. If CAS is held
low for the specified period (tFCS)
before RAS goes low, on chip refresh
control clock generator and the
internal refresh address counter are
enabled, and an internal refresh
operation is executed. After the refresh operation, the refresh address
counter is automatically incremented
in preparation for the next CASbefore-RAS refresh.
3. Hidden refresh;
A hidden refresh cycle will be
executed while maintaining latest
valid data at the output pin by
extending the CAS low time. For the
MB 81C258, a hidden refresh cycle
is CAS-before-RAS refresh. The
internal refresh address counter provides the refresh address, as in a
normal
CAS-before-RAS refresh
cycle.
CAS-before-RAS refresh counter Test:
A special timing sequence using CASbefore-RAS refresh counter test cycle
provides a convenient method of verifying the function of CAS-before-RAS
refresh activated circuitry. After the
CAS-before -RAS refresh cycle, if CAS
goes to high and goes to low again while
RAS is held low, the read and readmodify-write cycles are enabled according to the state of WE. This is shown in
the CAS-before-RAS counter test cycle
timing diagram. A memory cell address,
consisting of a row address (9 bits) and
a column address (9 bits), to be accessed
is shown below.
ROW ADDRESS - Bits Ao to A7 are
provided by the refresh counter. The

2·15

1IIIIIIIIIIIIIImlllllllllllllllllillmllllllllili

"MB81C258-10

FUJITSU ,MB,8lC25a-12
1IIIm~~mlmllllm~IIIII~~llllllllmlllll ,MB~58-15

--

bits As is set,high internally.
COLUMN ADDRESS - All the bits ,11.0
to As are provided by ellternally
,
after tCADT'
The recommended procedure of ,CAS·
before·RAS rcefre,sh counter test cycle is
shown below. The timing of'CAS·
before-RAS refresh counter test cycle
should be used.
1) Initialize the internal refresh address

:i

counter by using eight, CAS.before·
RAS refresh cycles.
2) T,hroughout, the test, use the same
'
column address.
3) Using a write cycle, write Os to all
256 row addresses.
4) Using
CAS·before·RAS ' refresh
counter test cycle in read·modifywrite moc:le, read the 0 written, in
step 3). and simultaneously write II 1

,,' -

,: ..,'

","

,

,Fig. 2 -CURRENTWA"E~ORM

RAS/CAS Cycle

RAS--"

..

Hidden Refresh Cycle

e

]

15 0

',;

i,'
"

.

;.,

2-16

.1,

.,.I' "i •

,

fjV It

Static Column Mode Cycle

.,-

.l4
JI~l)~ '\..

,

i,.

..

";;"

Il

J\

,

,

/"
;,"

, J

C)

,.~

.

','

100
50

,

0

Nee '" 5.5", TA = 25

'RAS only Refresh 'Cycle

CAS

« 200

to the same cell. This step is repeated
256 row address generated by inter·
nal refresh address counter.
5) Using a normal read cycle, read back
the 1s written in step 4), from all
256 locations.
6) Complement the test pattern and
repeat step 3), 4), and 5).

'

'.,

Vt

A

J~
,

..

~Il

\ LtJ·ll N fV U ~

A

MB 81C258-10 m~~~~~m~m~~lm~~m~~im~
MB81C258-12 FUJITSU
MB81C258';15 mM~~~m~~IIIOO~~~~~

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - NORMALIZED ACCESS TIME ItRAC)
VI

w

:;;

i=

TA

a

SUPPLY VOLTAGE

w
:;;

250C

u

~ 1.1

ved=5.oJ

i=

12

m.

Fig. 4 - NORMALIZED ACCESS TIME ItRAcl
vi AMBIENT TEMPERATURE

:II 1.2

\.

y"j

w

u

~

Q

lI:l 1.0

:J

«

~ 0.9
": 0.8

o

«
If
4.0

~ 1.1

Q

"

/

lI:ll.0

V

:J

«
:;;0.9

'-

!§

z
0 0 .8
«
If

5.0

6.0

20

Vee SUPPLY VOLTAGE (V)

Fig. 5 -NORMALIZED ACCESS TIME ItAA)
VI

VI

100

"

,,-

V

~,.,.

./

.........

5.0

6.0

20

0

20

40

80

100

T A. AM81ENT TEMPERATURE (OC)

Fig. 7 - OPERATING CURRENT

Fig. 8 - OPERATING CURRENT

CYCLE RATE

VI

SUPPLY VOLTAGE

<60

Ve~ = 5.5~

g

5OI-TA = 25"C

TA L5Q C'

I- 50 f-. tRe = 200no
Z

Z
w

w

~

~40
::J
U

~

Cl3 0

Z

i=
~20

...0.

80

AMBIENT TEMPERATURE

./

Vee SUPPLY VOLTAGE (V)

I-

60

Vee a 5.0V·

""
1

40

Fig. 6 - NORMALIZED ACCESS TIME ItAA)

TA ~ 25"C

VI

20

TA. AM81ENT TEMPERATURe (OC)

SUPPLY VOLTAGE

4.0

V

w

10

/'

V

V

V

40

a

~ 30

~

a:20

~

V

V

~

...ow

'10

(j

(j

o

.!i 0
2

3

4

5

lItRe. CYCLE RATE (MHz)

-

0
4.0

5.0

8.0

Vee SUPPLY VOLTAGE (V)

2-17

~~m~~~llm~~mmm~~~~~~~I~~1M8i81C;~58..1O

FU-lI'l'SUI,t'lB81C'",,12

1IIIIIIIIIIIIImlllllll~~illlmmlmIIWI~1 MB'81',~~8~15

Fig. 9 - OPEr:tATiNGCURRENT
VI AMBIENT TEMPERATURE

_ 60

1

J

vc6-S.s
~
;:: 50 _ tRC=200no

iii

:

~ 40

TA

5

~ 30

a:

~

20

2

...J

~

~

• 10

U
2 0
-~

0.:

2,0

40

60

BO

100

1

'H- 0

~
4.0

, .TAr:AMBIE~:r TEMP~RATURE (OC)

w

a:

~400f:--+~~-4~-+--+--'4"
o

>-

VC~ -

«
.s S
...z

s.sV

~ 4

a:

~300f:--+-~~~-+--+---l

~

'"c

z

~200f:--+~~-4~-+--+---l

~
100 i"::t:;;;;;:;;t-""'I"'"""-t-jc-i

d
o

~2
~

6.0

~5,9

~,fig.13"'REFRESH

. -2()

~

CURRENT 1

«

/

E

- SO

...Z

"

~

a:
:l
o

./

30

,/

J:

'"a:w 20
.;10

o
2

,

5.0

80

~ 40

V
-"

6.0

Vce SUPPLY:W<)LTAGE (V)

o

"

V
./

a:

4.0

4060

_~cJ.S.st
TA=2S"C

11.
W

.'

20

100

Fig; 14 -REFRESH CURRENT 1
VI CYCLE RATE
_ 60

t

0

T A • AMBI.ENT TEMPERATURE (oC)

fJ. sUPPLY:VOL TAGE
TA 2SoC
I- tRc = 200no

"

"o 1
2

. Ol,-,--;J.:",.-...J,-.,...,.",JI::-..,...J.----,,.I::----I
4;O~

3

Vee;: §UPPL~ VOl:-TAGE (V)

~-18

6,0

S.O

:l

«

('-

.'

~

Fig. 12 .0. STANDBVCURRENT
VI AMBIENT TEMPERATURE:

;(

~ SO.O f:-T,-,-A+--1_2 5"_'C-tJ_"'-,-I_-+-_+---l

..-- ~

vcdlUPPLY VOLTAGE (V)

Fig. 11 . ..;:, CMOS: STANDBY CURR£NT
,,is.SUPPLY VOLTAGE

~

~ 25"CI

o
~ 3
c
z

i=
w

!zw

~ 4

a
;2

'Fig.10,-TTL STA.NDBYCURRE.NT
VI SUPPLY VOLTAGE

;
2

3

4

5

l/tRC. CYCLE RATE (MHz)

MB81C258-10
MB81C258-12
MB81C258-15

Fig. 15-STATIC COLUMN MODE
CURRENT VI CYCLE RATE
-60

1

!z 50
w
II

I

<60

i

..I.

Vee = 5.5V
TA = 25°C

t- 50

Z

w
II
II 40

~40

w

030

:;

~ 20

;t

r....- ~
.....
.. ~

,;10

o

4

8

12

16

030

o

-

:;
~20

«

Q.

.. 10

o
.E

20

o

l/tse, CYCLE RATE (MHz)

'" 50

t-

- 60
«
i

I J
Vee = 5.5V

N

TA = 25°C

6.0

5.0

I

TAL5°C
t- tRe = 200n.

Z

~ 40

::J

V

'"
l! 20

w
II
';10

~

o
.E

V

l:!
II

40

~

30

::J

loo-.

30

w

ffl

./

l!w

20

... ~ ~

-~

~ 10

j

.E
2

"

II

.. I '

o

3

4

o

5

4 .0

5.0

6.0

litRe, CYCLE RATE (MHz)

Vee SUPPLY VOLTAGE (V)

Fig. 19 - ADDRESS AND DATA INPUT
VOLTAGE vs SUPPLY VOLTAGE

Fig. 20 - ADDRESS AND DATA INPUT VOLTAGE
vs AMBIENT TEMPERATURE

«

3.0

~

TA

o

I

z>
«-

'" ~2.0

ffl «

II t-

...J

00

« >

~ ~1.0
> Q.
o ~
z

I

V 1H (Min.) .....

1/ ~

... ~ -

3eO

~

=1 250C

0_

«
J:
:>

50

t-

Z

o

4.0

--

I---

Fig. 18 - REFRESH CURRENT 2
vs SUPPL Y VOLTAGE

II

~

....

~

Vee SUPPLY VOLTAGE (V)

Fig. 17 - REFRESH CURRENT 2
vs CYCLE RATE
- 60

1

tse 50n.
TA=25°C

::J
U

o

1

FUJITSU
1111111111111111111111111111111111111111111111111111

Fig. 16 -STATIC COLUMN MODE
CURRENT vs SUPPLY VOLTAGE

u
w

o
.E

1111111111111111111111111111111111111111111111111111

V"

...
~

Vee l5.0V

0_

Z >

«gj ~ 2.0
w «
II t-

V 1H lMin.)

00

V 1L (Max.)

O

...J

« >

VIL(Max.)

~ ~
> Q.

1.0

o ~
z

0
4.0

5.0

6.0

Vee SUPPLY VOLTAGE (V)

«
J:
:>

-20
0
20
40
60
80
100
TA, AMBtENT TEMPERATURE (OC)

MB81C258-10
MB81C258-12
MB 81C258-15

1IIIIIIIIIIIIIIImllllllllllllllllllllllllllllllili

FUJITSU
1111111111111111111111111111111111111111111111111111

Fig. 21 - RAS, CAS AND WE INPUT VOLTAGE
vs SUPPLY VOLTAGE

Fig. 22 - RAS, CAS AND WE INPUT VOLTAGE
vs AMBIENT TEMPERATURE

3.0

I~

3.0
TA ~ 25°C

c
z..:: ->
I~

VIH (IMin.)

:;2.0

f!
..:: ..J
lII:ui
0

,

. >

~

-1 ~1.0
~ ~

c
z..::2:
-

V~

--' ~
V V IL (Max.)

~

u<.?

ve~1= 5.0V

I~
I-

I ~u

VIH lMin.)

w2.0
<.?

. ..::

I II:~

~
0
.>

VIL (Max.)

~ 5 1. 0
~ ~

..::

..::

J:

J:

:>

>

o

4.0

5.0

o

6.0

-20

Fig, 23 - ACCESS TIME (tRAC) vs LOAD
CAPACITANCE

20

w

~

gj
~ 10
u

V
/'

..::

U

5

~

CIlc(

.",
O...J

o....,q--I---1---1--+--l

00

»

5
o~ ~

3 TA

:1

f-- f--

I""'"

25°C
RAS= CAS· 5V
(CMOSV'H)

I

RAS -CAS -OV

If-- tM~sl V,d
If'

2001'S/Division

2001's/Division

FUNCTIONAL TRUTH TABLE
Clock Input

Address Input

Data

Operation Mode
RAS

CAS

WE

Row

Column

Input

Output

Standby

H

H

X

X

X

X

High-Z

Read Cycle

L

L

H

Valid

Valid

X

Valid

Write Cycle

L

L

L

Valid

Valid

Valid

High-Z' l

Static Mode Read Cycle

L

L

H

Valid*2

Valid

X

Valid

Static Mode Write Cycle

L

L

L

Valid*2

Valid

Valid

High-Z' l

Static Mode Mixed Cycle

L

L

L/H

Valid*2

Valid

Valid

High-Z or Valid

RAS-only Refresh Cycle

L

H

X

X

X

High-Z

Valid

X: Don't Care H: High level L: Low level
Note: • 1: If tws < tWS(min) and tWH < tWH (min), the data output become invalid.
*2: After first cycle, row address is not necessary.

m~OOlmm~mmlll~lm~ml~mll ;:2MB81C258.10
FUJIT$J1';:M8·81C258~12

ImOOlllllllmllml~mIIIIIOOlIIIII. ~:MB 81C258-15

-

PACKAGE DIMENSIONS
(Suffix: -PI
.16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No_: DIP-16P-M031
.
INDEX,-1

I

.260±.010
(6.60±0.25)

~:;=;=;==r==r=r=;:::;::=;=;~~
---,--.c-;.-~.766~:g~~(19.45~g:~)~

.300±.010
(7.62±0.25)

.047~i?12
(1.2~g·3)

.118(3.0)MtN

:020(0.51)MIN

, Dimensions In
Inches (millimeter,)

©'19B7 FUJITSU LlMITEDDI6030S-2C

MBB1C25B-10
MB81C258-12 FUJITSU
MB81C258-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
(Suffix: -PO)
18-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No_: LCC-18P-M02)

.008~:~~~ (0.20~~:~~)

no

R.030(0.7S)TYP

.490±.003
(12.45±0.08)
.527±.005
(13.39±0.13)

TYP

.285±.003~

(7.24±0.08)

.322±.005
(8.18±0.13)

.020(0.51)
MIN
.OSO(I.52)
MIN

.050(1.27)
TYP

1----t-.134~:~~~(3.4~~:~~)
Dimensions in

© 1986 FUJITSU LIMITED C18016S·3C

inches (millimete,,)

The information contained in this document does not convey any

given. The information contained in this document has been carefullv~

license under copyrights, patent rights, software rights or trademarks

checked and is believed to be reliable. However, Fujitsu assumes no

claimed by Fujitsu. Circuit diagrams utilizing Fujitsu products are

responsibility for inaccuracies. Fujitsu reserves the right to change

included as a means of illustrating typical applications. Complete

products or specifications without notice.

information sufficient for construction purposes is not necessarily

2·23 ·

2·24

MB 81C466-10
MB 81C466~12
MB 81C466-15
March 1987

Edition 2.0

65,536 x 4 BIT CMOS STATIC COLUMN DYNAMIC
RANDOM ACCESS MEMORY
The Fujitsu MB 81C466 is static column dynamic random access memory.
SC-DRAM. which is organized as 65536 word by 4 bits. This SC-DRAM is
designed for high speed. high performance' applications such as main frame
memory. buffer memory. and video memory. and for ,applications to battery
backed-up systems where very low power dissipation and compact layout is
required.

CERAMIC PACKAGE
DIP-18C-A01

The advantage of SC-DRAM is achieving the static mode operation such as
read. write and read-modify-write cycles in spite of dynamic RAM and the
fast read and write operation can be performed by this mode.
The MB 81 C466 is fabricated using silicon gate CMOS process. Since the
CMOS circuit dissipates very small power. it can be easily used in battery
backed-up application system such as hand h'eld computer.
The MB 81C466 is pin compatible with Intel's 51C259.
All inputs and outputs are TTL compatible.
•
•
•

•

•

•

65536 x 4 SC-DRAM. 18-pin DIP/
20-pin ZIP
Silicon-gate. CMOS. single transistor cell
Row Access Time (tRAe!.
100 ns max. (MB 81C466-10)
120 ns max. (MB 81C466-12)
150 ns max. (MB 81C466-15)
Random Cycle Time (tRe!.
200 ns min., (MB 81 C466-1 0)
230nsmin. (MB81C466-12)
260 ns min. (MB 81C41l6-15)
Address Access Time (tAA),
450s max. (MB 81C466-10)
55 ns max. (MB 81C466-12)
70 ns max. (MB 81<:466-15)
Static Mode Cycle Time (tse),
50 ns min. (MB'81C466:1O)
60 ns min~ (MB 81C466-12)
75 ns min. (MB 81C466-15)

•

PLASTIC PACKAGE
DIP-18P-M01

Low Power Dissipation
385 mW max. (M8 81C466-10)
330 mW max. (MB 81C466'12)
275mW max. (MB 81C466-15)
11 mW
at standby with
TTL level input
1".65 mW m,ax. "tstandby with
, CMOS,level inpui:
'
Single 5V supply ±10%'tolerance
Inte~nal write period control
On ch ip latches for address and
data inputs
32msi256 refresh cycle
RAS-Only. CAS-before-"RAS.and
Hidden'refresh capahil ity
Standard 18-pin ceramic (Metal
seal) DIP (Suffix: -C)
Standard IS-pin Plastic DIP
(Suffix: -P)
Standard 20-Pin Plastic ZIP
(Suffix: -PSi)

max.

•
•
•

•
•
•
•
•

,PLASTIC PACKAGE
ZIP-ZOP-M01

PIN ASSIGNMENT

Vss

RAS
As
As
A.

ABSOLUTE MAXIMUM RATINGS

Vee

Rating

Symbol

Value

Unit

Voltage on any pin relative to Vss

V 1N • V OUT

-1 to +7

V

Vee

-1 to +7

V

Voltage on Vce relative to Vss
Storage
Temperature

I

I

Ceramic
Plastic

Power Dissipation
Short Circuit output current

DC4
CAS
DQ3
Ao
A,
A2
A3
A7

TSTG
Po

-55 to +150
-55 to +125
1.0 '"
50

CAS
2

Vss DO,

4

6

we NC
8

10

As

A4

A7

A2

AD

12

14

16

18

20

'C
1

3

5

7

9

1113

16

17

19

W
mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to" prot~ct the

inputs against damage due to high static voltages or electric' fields. However, it" i~L fldvis~d
that normal precautions be .taken ,tb avoid
application cf any voltage higher than maxi-

mum. r.a.ted volta.ges tp this high .i'l1)pedance
circuit.

,2·25

III
BLOCK DIAGRAM

WRITE
CLOCK
GEN.

CLock
GEN.2

DATA
COLUMN

B~~~ER

t==~::::::)1

CQLUMN
,
DE90DE,R

IN
BUFFER,

t--:.';"'~""';'---1~+-+_-+---+,

DQ; to
DQ4
ROW
ADD.
BUFFER

262,144 BIT
,Sn)RA~ECELL

-Vee
-Vss

CAPACITANCE (TA • O°c to +70°C, Vee· 5V ± 10%, f Parameter
l':IputCapacitance,,~

to A7

.,
Ih~ut ~~pa,citance,

RAS,CAS,We; OE

.' '.
Input/Output CapaCitance, DO, t,oDClo!!
2-26

SVm,bol

1MHz)

Max

TVp

C IN1 .,

7

C IN2

10

CIO

'"""

7

Unit
pF
", pF

".

pF

MB 81C466-1O ~m~~.~~.i~l~m
MB 81C466-12 FUJITSU
MB 81C466-15 Illmm~I~~im~.~iWI~1

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)

Symbol

Min

Typ

Max

Unit

Supply Voltage

Vcc
Vss

4.5
0

5.0
0

5.5
0

V

Input High Voltage, all inputs

VIH

2.4

6.5

V

Input Low Voltege, all inputs

VIlli

-1.0

0.8

V

Parameter

Operating
Temperature

O·C to +70·C

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Value
Parameter

Symbol

Unit
Min

OPERATING/REFRESH CURRENT*
Average Power Supply Current
(RAS, CAS cycling; tRC= min)
STANDBY CURRENT
Standby Power Supply Current
(RAS, CAS .. V IH )

Max
70

MB81C466·10
MB 81C466·12.

Typ

60

ICCl

TTL Level

2
mA

Icc2
CMOS Level

0.3

STATIC MODE OPERATING CURRENT*
Average Power Supply Current
(FiAS = V IL , CAS, WE or Address = cycling;
tsc = min)

MB 81C466·10

MB 81C466·15

35

CAS-BEFORE-RAS REFRESH CURRENT"
Average Power Supply Current
(CAS·before-RAS; tRC = min)

MB 81C466·10

65

MB 81C466-12

MB 81C466·12

mA

50

MB 81C466·15

50
I CC3'

40

55

Icc4

MB 81C466·15

mA

mA

45

INPUT LEAKAGE CURRENT, ALL INPUTS
(V IN = OV to 5.5V, Vcc = 5V, Vss = OV, all other
inputs not under test = OV)

II(L)

-10

10

jJ.A

INPUT/OUTPUT LEAKAGE CURRENT
(Data is disabled, V OUT = OV to 5.5V)

IDQ(L)

-10

10

IlA

OUTPUT LEVEL, OUTPUT LOW VOLTAGE
(lOL = 4.2mA)

VOL

0.4

V

OUTPUT LEVEL, OUTPUT HIGH VOLTAGE
(lOH = -5.0 mA)

V OH

2.4

V

NOTE *; Icc is depended on the output loading and cycle rate. The specified values are obtained with the output open.

2-27·

~m~~~~lIlm~~I~~~~~, MB, 81C466-10
FUJITSU M8 81C466-12

m~~IM~~~~mllll~~~IIIIII~~~ MB 81C466-1'5'

ACCHARACTERISTICS

,:,>' '

~

"

(At Recommended operating conditions unless otherwise noted) 1~I.nlll

1&1

Parameter

' ~ <.

MB 81C466-10

MB 81C466-12

MB 81C466-15

Min

Min

Min

Symbol
Max

Max

32

32

Time Between Refresh

tREF

Random Read/Write Cycle Time:

t RC

200

" '230

260

Read-Modify-Write Cycle Time

t RWC

270

315

360

RAS

III

t RAC

Aceess Time from CAS

iii

t CAC

Access Time from

Output Buffer Turn off Delay TimE!'

Output Hold Time from Column
Address Ch ange

Access Time Relative to Last Write

II

RAS Precharge Time
RAS Pulse Width

,

RAS Hold Time
CAS Pulse Width (Read)
CAS Pulse Width (Write)

,

,

CAS Hold Time (Read)

CAS Hold Time (Write)

i

CAS toRAS Sel Up Time
Row Address set UpTime

,

Row Address' Hold Time
Column Address'Set ,UpTime
Column Address Hold Time
RAS to Column Address Delay
,
Time,
Column Address Hold Time
Referenced to RAS'

II
I

IlIiJ
,

Write Address Hold Time,
Refer,enced to RAS
Read Addr;ess to

RAS Lead Time

column Address Hold Time
Referimee to RAS Rising Time

'last Wi'ffeto'Column Address
Delay Time
Column ,Address Hold Time
Referenceto' Last,Write

••

0

50

3

50

3

55
5

t WPA

25

tALW

!l0,

"

tRAs

65

tFiSH

lZ5

100

t CAS

25

100000

t CAS

15

,JOOOOO

100000

tCSH
t Rco

25

75

t CRS

20

"

tASR

P

tRAH

15

t ASC --

0

tCAH

20

tRAD

20
100

t AWR

80

tAHLW,

20
90,_

)<-",>

100000

ns

25

100000

,hs

150 "

25

30

0,

15

20

65

ns

"

,ns

"',"

'"

ns

.0

ns"

30

ns,

25

Ii,

80

ns
"

1~0

"70 '

- 51),
c;:

i

ns
ns

110
,1,<

,

,','

' ;20

c,

25

70

1'110

ns

,.,

'"
'

110
:';"

0$ ,

,

I.'

15

2P \

"

hs '
,115

30

0

,

ns

115
90

.'

ns

100000

55

-

n~,

20

90

45

ns

,'ns

"

l5

35

HO

100,000

" 1,20

"

ns

35

'20

45

tAH~

tLWAD

,'"

ns

100000

25
"

50
70

30

'0

55

ns

35

'25

,

ns,

ns

95

100000

95

"

tAR

75

:120

80

35,
30

100

30

100

ns

ns

3q

90

1'50'

5

" "UO

t RP

tRAV

II!I

25

5

, tCSH

CAS Delay Time

0

45

tAA
t AOH

Access Time from WE Precharge

RAS to

3

tT

iii

Column Address Access Time

ns

30

25

ms

lis

120

25,
0

'tOFF

Transition Time

32

100

Unit

Max

,,1'15,

,

", ,",'I ,

i49

n~ '~,

MB 81C466-10 !m~mllm!llmlllll.IUmll

MB 81C466-12

PU.J'ITSU

MB 81C466-15 • •. 0

...

AC CHARACTERISTICS (Cont'd)
(At Recommended operating conditions unlen otherwise noted)
Parameter
Read Command Set Up Time
Referenced to CAS
Read Command Hold Time
Referenced to RAS
Read Command Hold Time
Referenced to CAS

WI: Pulse Width

•
•

Symbol

111 11111
0

MB 81C466-10

MB 81C466-12

MB 81C466-15

Min

Min

Min

Max

Max

Unit

Max

tRcs

0

0

0

ns

tRRH

10

10

10

ns

tRCH

0

0

0

ns

twp

15

20

25

ns

WE Inactive Time

tWI

15

20

25

ns

Write Command Hold Time

t WCH

15

20

25

ns

Write Command to RAS Lead Time

t RWL

25

30

35

ns

Write Command to CAS LeadTime

tCWL

25

30

35

ns

t RWO

125

150

185

ns

tcwo

50

60

70

ns

Column Address to WI: Delay Tim~

tAwo

70

B5

100

ns

RAS to Second Write Delay Time

t RSWO

105

125

155

ns

Write Command Hold Time
Referenced to RAS

t WCR

eo

95

115.

ns

RAS Precharge Time from Last Write

tRPLW

135

155

165

ns

tws

0

0

0

ns

tWH

0

0

0

ns

tos

0

0

0

ns

DIN Hold Time

tOH

20

25

30

ns

DIN Hold Time Referenced to RAS

tOHR

eo

90

110

Access Time from OE

tOEA

OE to Data In Delay Time

tOED

20

Output Buffer Turn off Delay Time
fromM

tOEz

0

tOEHR

20

20

20

ns

tOEHC

20

20

20

ns
ns

RAS to WE Delay Time
CAS to WE D~lay Time

Write Set Up Time for Output
Disable
Write Hold Time for Output Disable
DIN Set Up Time

DE Hold Time Referenced to RAS
OE Hold Time Referenced to CAS
Refresh Set Up Time for
Referenced to RAS
(CAS-before-RAS" cycle)

eAS

•

••
••

25

30
30

25
20

0

ns
35

25

0

ns
ns

30

ns

-.

tFcs

20

25

30·

Refresh Hold Time for CAS
Referenced to "RAS"
(CAS-before-RAS cycle)

t FCH

20

25

30

ns.

CAS Prechaige Time
(CAS-before-RAS cycle)

tCPR

20

25

30

its

~ Precharge Time to CAS" Active
Time (Refresh cycles)

tRPe

20

20

20

ns

~:

2-29

m~~lmlllll~~llllmloomm Ma81C466-10
PUJITSU MB"81C466-12
Ilmllml~lmlll!llmlmll M8 81C466.;.15

AC CHARACTERISTICS (Cont'd)

IAt Recommended operating conditions unless otherwise notiidt 1~I.nIIfJ
P,arameter

.1IiIDI

Symbol

MB 81C466-10
"'Min

Max

MB 81C461i:12

MB 81C466-15

Min

Min

Max

Max

Unit

Static Mode ReadlWrite Cycle Time

tsc

50

60

Static Mode Read-Modify-Write
Cycle Time

tSF!WC

120

145

Static Mode CAS Precharge Time

tcp

15

DE to RAS Inactive Set Up Time

tOEs

25

tozc

0

0

0

.tpzo

0

0

0

ns

tRTC

465

550

645

ns

tTRAS

36!;)

tCPT

50

DiN. to CAS Delay Time.

iii

OE Delay Time _

II!I

. DIN to

. Refresh Gouhter Test Gy.cle Time
'Refresh Couriter Test RAS Pulse
Width
. Refresh Counter Test CAS
Precllarge Time
Refresh Cqunter Test GAS to
Column Address Delay.Time
Refresh Counter T~st~ccess
Time fr~m CAS
Refresh Counter Test CAS to
WE Dell\Y Time

•
•
•
•
•

-.

tCAo,'

10000

75

ns

180

ns

20

25

ns

30

35

I

440
60

10000
•..

535

ns
..

10000

70

ns

ns
ns

100

120

150

ns

la5

165

205

ns

-,
tCAcT
tcwDT

135

165

205

ns

NOTES:
IItRAD (min) ;, t~AH (min) + tT (tT .. 5ns)
'An lilitial. pau~. (RAS=CAS=VIH I qf 200Jls is required
IlU tAH R is specified to latch column address, by the rising
after power-up followed by any 8 RAS-only cycles
edge of RAS.
'" befOre proper device operation is achieved, In case. of
•
Operation within the tLWAD (max) limit insures that
using -internal refre~. counter, a minimum of 8 CAStALW (max) can be met. tLWAD (max) is' specified as a
befor;e-RAS in'itialization cycles instead of 8 RAS
reference point only; if tLWAD is greater than the specicyclE!S are ¥jlquinid_
..
fied tLwAD(max) limit, then access time is controlled
PA AG characteristics assume ·tT = 5ns, VIN = OV to 3V.'
by tAA'
VIH = 2.4V, VI~ .. 0;8, VOH . =.2.4V, and VOL = O.4V.
11 Assumes tilat tR~~ ~ tRAD Imaxl. IftRAD is greater 01 tLWAD (min) = tCAH (min) + tT (tT = 5ns).
III Either tRRH or tRCH must be satisfied for a read cycle.
than the ,:maximum reco(T1mended .value'shoiNn in this
• . tws, tWH, and tRWD are specified as a reference point
table, tRA·C will be· increased by the amount that tRAD
only. If tws ~tws (min)'and· tWH~ tWH (min). the
. exceeds the value shown.
data output pin will rema.in High-Z~state throughout
II Assumes that t~;"D ~ tRADlmax).
entire ·cycle. It tRWD ~ tRwD(min). The data output
II Measured with, a load equivalent t02TTL loads and'
WIll contain data read from the selected cell.
loopF.
III Either tOEH R or tOEHC is satisfied, output is disabled.
'Assumes that tLwAD ;;l;' tLwAD Imaxl. If tLWAD is
Either tDzc or tDzo must be sati.sfied.
greater than t"l1l maximum recommended value shown in
CAS-before-RAS refresh counter test cycle only.
this 1I1ble,tAL~'; will be increased by the amount that'
tLwADexceeds the value shown .
• 'Write Cycle only.
Operation within the tRAD (max) limit in~ures that.
tRAC (max) can be met. tRAD (max) is specified as a
feference point only; if iRAD is greater than the specified ''tRAD(max) limit, then access lime is controlled
by tAA'
.

o

·m

;m

2~30

III
ID

MB 81C466-10 1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImllllili
MB 81C466-12 FUJITSU
MB 81C466-15 ~m~~~~llm~llmlm~rumll~~~~~m

Read Cycle

RAS

VIHVIL-

CAS

R

ADDRESSES VIH:
V 1L

WE

VIHVIL-

DO
(OUTPUT)

VOHVOL-

DO
(INPUT)

VIHVIL-

OE

VIHVIL-

Hjffij~=j=~~=1~=~t~~~}---HIGH-Z:----

_Don't Car.

'; If tRAD ~ tRAD (max), access time is tAA.

Write Cycle (WE Controlled)

DO
(INPUT)

VIHVIL-

DO
(OUTPUT)

VOir
VOL-

OE

V 1HVIL-

ISS]

Invalid Data

•

D.on't Car.

1l1l~~~~~mMln~~oo MB 81C466-1O
FUJITSU MB 81C466-12"
l!~illll~llmillmlllmlllll~I~llllml MB 81C466-15

Write Cycle (CAS Controlled)
OE; Don't Care

RAS

VIHVIL-

CAS

VI"
VI.L.-

DO

(INPUT)

00

(OUTPUT)

• VOH'::
VOL

~··'--:-~--:--------HIGH-Z"------------• .Don'tCara

'; If OEis kept high through a cycle or. tws ~ tws (min) and tWH ~ tWH (min) are met,
OQ pins are kept high impedance state.

Read-Modify-Writ' Cycle

AAS

VIHVIL-

CAS
ADDRESSES

VIH';"
VI'L"':'

WE

VIHVIL-

DO

VIH, VIL-

(INPUT)

00

(OUTPUT)

DE

VIH:VIL""

, •

Don't Car.
ISSllnvalid Date

2-32,

MB 81C466-10 m~~~oomoolm~m~~~m~~~~~1
MB 81C466-12 FWITSU
MB 81C466-15 1~~.~~m~~~~II~~

Static Mode Read Cycle

DO
(OUTPUT)
DO
(INPUT)

_Don'tCa ••

Static Mode Write Cycle

RAS

VIHVIL-

CAS

VIHVIL-

ADDRESSES VIf1
VIL-

WE

V 11+_
VIL-

DO
(INPUT)

VIH'VIL-

DO
(OUTPUT)

VOHVOL-

OE

VIHVIL-

ISSllnvalid data •

Don't Ca ••

2-33 !

1IIIIIIIIIImm~~mllm~~II~mmllm MB,81C466-10
FUJITSU MB 81C466-12

111111111~~llllmll~mmlm~~II~m~111 MB 81C466-15

•
I

Static Mode Raad-Modify-l/lIrite Cycle

____jp===========-;tRC:-==========i1==1
tRAS~

RAS

Vlti:-V U':-

r-t£~Ir========::;-;;:;;===:j'r-----'-~-tRP
tC"SH------'--'--:--------"1rH
tRCo--+-------tRsH-------~1

CAS

VIHV IL-

ADDRESSES VIH_
VIC

DO

(INPUT)

DO'
(OUTPUT)

V
- - ..-. HIGH-Z--+----{'~~-­
VOH
OL -

~ValidData

!SSIlnvalid Data " . Don't Car.

, Static Mode Mixed Cycle

RAS

VIHVIL-'

CAs

VIH"""
'VIL-

WE

VIHV IL-

DO

Vltr
VIL-

DO

V OHVOL-

OE

VIH_
V IL-

(INPUT)

(OUTPUT)

Write

2·34

Read

Read-Modify-Write
ISSIlnvalid Data •
Don't Care

MB 81C466-10
MB 81C466-12 FUJITSU
MB 81C466-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

RAS-Only Refresh Cycle
(Note; WE, OE, DIN = Don't Care)

V IH - - - - - . l l
VIL11-----------.>[1

V , H - . I I . r - - - - - - - - - - - - - l I l 1 l 1• • • • • •
V IL- .

OQ

(OUTPUT)

VOH-=::===t--------HIGH-Z----------VOL-Don'tCara

&I

CAS-before-RAS Refresh Cycle)
(Note; Address, WE, OE, DIN = Don't Care)

tRC
tRAS
RAS

V IH V IL-

~
-tCPR---i

CAS

OQ
(OUTPUT)

VIHV IL- ---1

VOH
VOL

-tR
f-tFCH

1

- tRPc

'I

~F

I
HIGH-Z

I

l1li Don't Care

2-35 I

~Hlilllll!IM.1II MB 81C466.1O
FUJlTSU. MB 81C466..12
IIIMII.~UI!nl~I.1 Mil .81C466-15

Hidden RefreshCy~le

V
H------.L1

V

1L
-

1'r=~H~------n..--'RI'-----I

i----1F'CH----t

DQ
(INPUT)

•

2-36

Don'tear.

MB 81C466-10 ~~~OOm~llm~~~~~~I~~
MB 81«%466-12 PWITSU
MB 81C466-15 Ilmllllllllllm~llm~mllll!~I~i~m~

CAS-before-RAS Refresh Counter Test Cycle

RAS

CAS

VIHADDRESSES VIL-

WE
(Read)

VIH_
VIL-

DO
(INPUT)
(Read)
DO
(OUTPUT)
(Read)

VOH..,
Vo L-'-

OE
(Read)

V1H_
VIL-

WE
(Write)

VIH_
VIL-

DO
(INPUT)
(Write)

VIHVIL ..,.

DO
(OUTPUT)
(Write)

OE
(Write)

VOHVo L-

VIH-

VIL_Don'tea ..

ISS) Invalid Data

~3'l

mmlillllli!!mlllllm~lloo~m MB81C466-10
FUJITSU MI. 81C466-12

mmllilllllliIIIIIMI~~I~lllllm~~ MB81C466-15

DESCRIPTION
Address Inputs:
stant. However, when either CAS or OE 4~ Static mode mixed cycie;
A total of sixteen binary input address goes high, the output returns to a high
In the static mode, read, write, and
bits are required to decode parallel 4 impedance st~te. In the static write
read-modify-write cycies can be
mixed in any order.
bits of the 262,144 storage cells within c;ycle (CAS controlled), if
both
the MB B1C466. Eight row address tws~ws(min) and tWH~wH(min) are In the next read cycle of static mode
bits are established on the address met, data pins are input mode regardless write. cycie or read-modify-write cycle,
. the access time is determined by the .
input pins (Ao to ,A,) and latched with of the state of OE.
follOWing conditions,
the Row Address Strobe (RAS). The
eight column address bits are established Output Enable:
1. tALW from the failing edge of WE
on the address input pins (Ao to A,) The OE controls ·the impedance of the
at previous write cycie.
after the Row Address Hold Time has output buffers. In the high state ali OE, 2. tAA from the column address inputs.
been satisfied. In read cycle;the column the output buffers are high impedance 3. tWPA from the rising edge of WE at .
the read cycle.
addresses are not latched by the ·Column state. In the low state on OE,the
Address Strobe (CAS), so the column olitput. buffers are low impedance 4. tCAC from the falling edge of CAS.
address must be stable until th~ jOUtP.ut state. In the write cycle (WE can· 5. tOEA from the falling edge of OE.
becomes valid: In write. cycle;' the .' trolled); the OE must be high ·before
column addresses are latched by the the data applied to DO pins. When WE Refresh:
controlled write .cycles is not used, OE
later fallin~ ~dge of CAS.!'~ WE.
Refresh of dynamic memory cells is
.can· be low throughout the operation.
accomplished by petforming ,3, tn'emory
Write Enable:
. cycle at each of the 256 row addresses ,
R.ead or Write cycle is selected withth.e StatiC Mode:
(Ao to A, ) at least every 4ms.
WE inputs. A high on WE selects read The static mode operation allows con- The MB 81C466 offers the following
cycle and 'Iow' selects write cycle: The tinuous read, write, or read-modify- three types of refresh,
write operation is as.serted on the iater write cycle within a row by applying 1. RAS only refresh;
falling edge of CAS or WE .. (Both CAS new column address. In the static mode,
The RAS-only refresh avoids any
and WEare low,). Theti1ri~ ~eriod of CAS can be kept low throughout static
outputs during refresh because the
the write' operatiqn, -i~' .(jet@rml~ed~.ll mode operation,. The following four
QutPlltsbuffers. are high imp!ldance
internal circuit, thus the next write cyclesare,allowed in the static mode.
state due to. CAS-high. Strobing of
each 256 row address (Ao to A,)
operation will be inhibited during the 1, Static tnqde read cycle;
write operation.
.
in ;a static mode. read cycle, the
with RAS will cause ail bits in each
row to be refreshed.
access time is tRAc .from the falling
Data Pins:
edge of flAS ort AA from. the column 2. CAS-before-RAS refresh;
Data Inputs;
CAS'before'RAS refreshing available
address input or tQ~A from the fallon the MB 81 C466 offers an alterData are written into the MB Bl C466
ing edge of OE. The' dilta 'temains
nate refresh method. If CAS is
during write or read~modify·write cycle.
valid for a ,time tAO H after the
held low for the specified period
The input data is strobed and I~tched
column ad-----

-'--f--

- !J\
-Iv'
ROW
DEC.

f(
REFRESH
ADDRESS
COUNTER

-

-

-

·
·
·

f--- DIN

I

SENSE AMP. &
1/0 GATE

...

1,048,576 BIT
STORAGE CELL

"-

DATA
OUT
BUFFER

r---- DOUT

_r-SUBSTRATE
BIAS GEN.

L-

2·42

DATA
IN
BUFFER

COLUMN
DECODER

I

-Vee
--Vss

MBB1Cl000·70
MBB1Cl000·BO

1IIIIIIIIIIIIImllllllllllllllllllllllllillmllili

FUJITSU

::::~::g:: ~ 1l l l l l l l l l l l l lm l l ml lml m~

CAPACITANCE
Value
Parameter

Symbol

Unit
Typ

Max

C IN1

5

pF

Input Capacitance, RAS CAS, WE

CIN2

5

pF

Output Capacitance,

COUT

5

pF

Input Capacitance, Ao to Ag ,

DIN

DOUT

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vssl

Value
Parameter

Symbol

Unit
Min

Typ

Max

5.0
0

5.5
0

V

Supply Voltage

Vee
Vss

4.5
0

I!'put High Voltage, All inputs

V IH

2.4

6.5

V

Input Low Voltage, All inputs

V IL

-2.0

0.8

V

Ambient
Operating.
Temperature

OOC to +70o C

2..43

1IIIIIIIIImlllmlllllllllllllllll~llllm~mll MBB1C1OOO..70"
FUJITSU MB81Cl000..1I0··

1I Imlm~I I I~I~l l ml~I I~I~I I ~ 1 ::~~~g:l~·

-

DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted)
Parameter.

Operating Current"
(Average power
Supply current)

Conditions

Symbol

Values
Min

75

MB81Cl000·70
M B81 C 1000·80

RAS & CAS cycling;
tRC.= min

70

ICCl

Refresh Current 1 *
(Average power
supply current

Fast Page Mode
Current·

c
Refresh Current 2·
(Average power
current)

TTL level
CMOS level

50
RAS = CAS = V IH
RAS = CAS ~ Vcc-0.2V

2.0
mA

Icc2

1.0
70

MB81Cl000·70
MB81Cl00Q·80

C~S = VII~' RAS
cycling; tRC = min

• ' ·l cc3 '

65

MB81Cl000·12

45

MB81Cl000·70

47
RAS = V IL , CAS
cycling; tpc = min

45

Icc4

MB81Cl000·10

40

MB81Cl00q·12

.33

MB81Cl0QO,70

70

MB81Cl000·80
MBB1Cl00Q·10

RAS cycling,
CAS·before·RAS;
tRC = min

mA

;

I

65

Icc5

mA

55
45

MB81Cl000·12
OV ~ VIN ~ 5.5V,
4.5V ~ Vcc ~ 5.5V,
Vss = OV; pins not
under test = OV

II(L)

Output Leakage Current

OV ~ V OUT ~ 5.5V;
Data out disabled

IO(L)

-10

Output High Voltage

IOH = -5mA

V OH

2.4

Output Low Voltaj18

IOL =4.2mA

VOL

Input Leakage Current

mA

55

MB81Cl00Q·10

MB81Cl000·80

mA

6b

M881Cl000·l0
MB81Cl000·12

Standby Current
(Power supply
current)

Unit

Max

-10

10
p.A
10

V
0.4

NOTE: .; Icc depends on the output load conditions and cycle rate. The specified values are obtained with the output open.
Icc depends on the number of address change as RAS = V IL and CAS = V IH.
ICC1' ICC3 and Iccs are specified at three time of address change during RAS = V IL and CAS = V IH .
ICC4 is specified at one time of address change during RAS = V IL and CAS = V IH.

2-44

MB81Cl000.70
MB81Cl000·80
MB81Cl000·l0
MB81Cl000·12

..

AC CHARACTERISTICS

1IIIIIIIIIIIIIImlllmlm~lllm~~~~mlml
FUJITSU
~~m~~m~IOOOO~~~~~~~m~i~11

la _ _

(At recommended opereting conditions unless otherwise noted.)

No.

Parameter

MB81Clooo-70

MBB1Cl0()()'BO

MBB1Cl00o-l0

MBB1Cl0()()'12

Symbol

Unit
Min

Max

Min

B.2

1

Time Between Refresh

tREF

2

Random Read/Wrlte Cycle Time

tRC

140

3

Read-Modify-Wrlte Cycle Time

tRWC

167

Max

Min

B.2

MIx
B.2

lBO

155
lB2

Min

Max
B.2

ms

210

ns

245

210

ns

4

Access Time from RAS

.. B

tRAC

70

5

Access Time from CAS

lUI

tCAC

25

25

30

35

ns

6

Access Time from
Colum n Address

iii II

tAA

43

45

50

BO

ns

7

Output Data Hold Time

tOH

7

7

7

7

ns

B

Output Buffer Turn on Delay
Time

tON

5

5

5

5

nl

9

Output B.uffer Turn Off
Delay Time

tOFF

10

II

.Transition Time

25

tT

3

50

BO

100

120

ns

25
3

50

25
3

50

70

ns

50

ns

11

RAS Precharge Time

tRP

60

12

RAS Pulse Width

tRAS

70

13

RAS Hold Time

tRSH

25

25

30

35

14

CAS to RAS Pracharga Time

tCRP

0

0

0

0

15

RAS to CAS
Delay Time

tRCO

20

16

CAS Pulse Width

tCAS

25

25

30

35

ns

17

CAS Hold Time

tcSH

70

80

100

120

ns

18

CAS Procharge Time
IC-B-R Cycle)

tCPN

15

15

15

15

ns

19

Row Address. Set Up Time

tASR

0

0

0

0

ns

20

Row Addrass Hold Time

tRAH

10

12

15

15

ns

21

Column Addres. Set Up Time

tASC

0

0

0

0

ns

22

Column Address Hold Time

tCAH

15

15

20

ns

23

RAS to Column Addra••
Delay Time

tRAo

15

24

Column Addr... to RAS
Lead Time

tRAL

43

45

50

60

ns

25

Read Command Set Up Time

tRCS

0

0

0

0

ns

11l1li

II

III

65

3

25

100000

45

80

22

100000

55

15
27

17

35

100

25

20

BO
100000

70

50

120

25

20

ns
100000

ns
I

ns
ns

85

60

nl

ns

2·45

mlmlllll~llllm~~mllllmllmlimllllll

MB8\C:l000~70

MB81ClOOO;;80
MB81C:1OOO.l0
1IIIIIIIImllmllllllmlllllllllllllllll~~mll MBS1C1OOO·l 2
FUJITSU·

AC CHARACTERISTICS (Cont'd)
(At r.ecommended operating conditions unless otherWise noted.)
MB81Cl0o.()'7o..

Parameter

No:

IDlI

II_f.
MB81Cl00()'8o.

MB81Clo.o.()'lo.

MB81Cl00()'12

SymbOl·

Unit
Min

Max'

Min

Max

Min

Max

Min

Max

26

Raad Command Hold Time
Referenced to RAS

IB

tRRH

0.

0.

0.

0.

27

Read Command Hold Time
Referenced to CAS

IB

tRCH

0.

0.

0.

0.

28

Write Command Set Up
Time

II!I

twcs

0.

0.

0.

0.

tWC·H·

15·

15

15

20.

ns

15

15

20.

ns

29

..

ns

ns
,

'WriteCommanCf Ho'id Tilli.'

ns

30.

WE Pulse Width

twp

15

31

Write Command to RAS
Lead Time

tRWL

22

22

25

30.

ns.

32

Write Commnd to CAS
Lead Time

tCWL .

17

17

20.

25

ns

33

D, N Set Up Time

tos

0.

0.

0.

0.

ns

34

DIN Hofdtime

tOH

15

15

15

20.

n~

35

RAS to

we Delay Time

II!I

tRWO

70.

80.

100

1'20.

ns

36

CAS to

we Delay Time

III

tewo.

25

25

30.

35

ns

37

Column Address to
Delay Time

we

III

tAWO

43

45

50.

60.

ns

38

RAS Precharge Time to CAS
Active Time (Refresh Cycles)

tRPC

0.

0.

0.

0.

39

CAS Set Up Time for
CAS-beforo-RAS Refresh

tCSR

0.

0.

0.

0.

ns

15

15

15

20.

ns

,

.,
.,

:

'.

ns

,

40.

CAS Hold Time for
CAS-beforo-RAS Refresh

41

Access Tillie from CAs
(Counter' Test Cyclii)

teAT

50.

Fast Page Mode Raad/Write
Cycle Time

tpc

53

55

60.

70..

ns

51.

Fast Page Mode Reacl-ModifyWrite' Cycle Time

tpRWC

75

77

85

100

ns

52

Access·Titne from CAS
Precharg,e

·~CPA

53

2·46

Fast Page Mode ,CAS
Prech~rge Tirpe

...

Bill·

tCHR

t~p,

43

53

15

50.

45

55

15

60.

60.

15

70.

15

ns

ns

ns

MB81C100o-70
MB81C1000-80
MB81C1000-10
MB81C1000-12

•

NOTES:
An initial pause (RAS = CAS = V IH) of 200 IlS is required
after power·up followed by any 8 RAS·only cycles
before proper device operation is achieved. In case of
using internal refresh counter, a minimum of 8 CAS·
before·RAS initialization cycles instead of 8 RAS cycles
are required.

~~~lm~~I~~~~~~~mlmmlllm~~m
FUJITSU

II~m~m~~~lm~~m~~~II~m~~m

•

tAco (min) = tRAH (min) + 2tT + tASC (min).

_

Operation within the tRAD (max) limit insures that
tA AC (max) can be met. tRAD (max) is specified as a
reference point only; if tAAD is greater than the speci·
fied tAAD (max) limit, access time is controlled exclu·
sively by tCAC or tAA .

III

Either tRRH or tACH must be satisfied for a read cycle.

. . AC characteristics assume tT = 5 ns.
_

V 1H (min) and V 1L (max) are reference levels for meas·
uring timing of input signals. Also, transition times are
measured between V 1H (min) and V 1L (max).

•

Assumes that tACO:;;;: tACO (max), tAAD :;;;: tAAD(ma
x). If tACO (or tAAD)iS greater than the maximum rec·
ommended value shown in this table, tAAC will be incre·
ased by the amount that tAco (or tAAD) exceeds the
value shown. Refer to Fig. 2 and 3.

•

If tAco ~ tACO (max), tAAD ~ tAAD (max), and
tASC ~ tAA·tCAC·tT, access time is tCAC.

•

If tAAD ~ tAAD (max) and tAsc :;;;: tAA ·tCAC·tT, access
time is tAA.

•

Measured with a load equivalent to two TTL loads and
100pF.

•

tOFF is specified that output buffer changes to. high
impedance state.

•

Operation within the tACO (max) limit insures that
tRAC (max) can be met. tACO (max) is specified as a
reference point only; if tAco is greater than the speci·
fied tAcO (max) limit, access time is controlled exclu·
sively by tCAC or tAA.

III twcs,

tCWD' tAWD and tAWD are not a restructive
operating parameter. They are included in the data sheet
as the electrical characteristics only. If twcs ~ twcs
(min), the cycle is an early write cycle and DOUT pin
will maintain high impedance state throughout the
entire cycle. If tCWD ~ tCWD (min), tRWD ~ tRWD
(min), and tAWD ~ tAWD (min), the cycle is a read·
modify·write cycle and data from the selected cell will
appear at the DOUT pin.
If neither of the above conditions is satisfied, the cycle is
a delayed write cycle and invalid data will appear at the
DOUT pin, and write operation can be executed by
satisfing t AWL, tCWL' and tAAL specificati.ons.

ID tCPA

is access time from the selectio~a new column
address (that is caused by changing CAS from "L" to
"H"). Therefore, if tcp is long, tCPA is longer than tePA
(max).

•

Assumes that ~·before·RAS refresh· and CAS-beforeRAS refresh counter test cycle only

2-47

m~~llllm~lml~llllm~mll~IIIII~~~~
PUJITSU

111111~III~illm~l~mli~OOI

MB81Cl000~70
MB81Cl000~80'
MB81Cl000~ 10
MB81Cl000~12

Fig. 2 .,.. tRAC vs tRCD

Fig. 3 - tRAC vs tRAD

140
]

140

120

u 100

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