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Harris Semiconductor Military & Aerospace Products
This data book contains detailed technical information on the extensive line of
military and aerospace digital products currently available from Harris
Semiconductor. A sister publication describing analog military and aerospace ICs
- "Analog Military Databook" - published in January 1989 is also available. Other
high reliability products available under the brand names of GE, RCA and Intersil
- now a part of the New Harris Semiconductor - can be found in the twovolume GE Solid State High-Reliability databook. Volume I contains information on
CMOS ICs and Volume II covers Analog ICs and Discrete Devices.

Copyright @ Harris Corporation 1989
(All Rights Reserved)
Printed in U.S.A.

Harris CMOS Digital Products
Harris Semiconductor is the eighth largest U.S. merchant semiconductor supplier and is a
sector of Harris Corporation. Harris acquired the solid state division of General Electric
(including RCA and Intersil semiconductor products) in December 1988. Harris is a pioneer
in developing and producing digital CMOS products including: CMOS RAMs, CMOS
PROMs, CMOS microprocessors, CMOS peripherals, CMOS data communications products and a full line of 80C286 and 80C86/S8 microprocessors and peripherals. .
This data book describes Harris Semiconductor's military line of CMOS digital products. It
includes a complete set of data sheets for product specifications, application notes with
design details for specific applications of Harris products, and a description of the Harris
quality and high reliability program.
'
If you need more information on these and other Harris products, please contact the nearest
Harris sales office listed in the back of this data book, or the Harris Semiconductor literature
department.

Harris Semiconductor products are sold by description only. All specifications in this data book are applicable only
to packaged products; specifications for dice are available upon request. Harris reserves the right to make
changes in circuit design, specifications and other Information at any time without prior notice. Accordingly, the
reader is cautioned to verify that data sheets and other information in this publication are current before placing
orders. Information contained in the application notes is Intended solely tor general guidance; use of the information
for user's specific application is at user's risk. Reference to products of other manufacturers are solely for
convenience of comparison and do not Imply total equivalency of design, performance or otherwise. Finally, without
the prior specific approval of an officer of Harris, the Harris products should not be used as critical components (i.e.,
failure of the Harris product is likely to cause failure of the system) In life support devices or systems (i.e., surgically
implantable devices or life-sustaining machines).

ii

General Information
Military Programs
CMOS Memory
CMOS Microprocessors
CMOS Peripherals
CMOS Data Communications
Harris Quality and Reliability
Appendices

iii

-

IEII

PAGE
ALPHA NUMERIC PRODUCT INDEX
HD-15530/883
Manchester Encoder-Decoder ...................................... .
HD-15531 1883
Manchester Encoder-Decoder ...................................... .
HD-4702/883
Programmable Bit Rate Generator ................................... .
HD-6402/883
Universal Asynchronous Receiver Transmitter ......................... .
Manchester Encoder-Decoder ...................................... .
HD-6409/883
HM-6504/883
4K x 1 Synchronous RAM .......................................... .
HM-6508/883
1 K x 1 Synchronous RAM .......................................... .
HM-6514/883
1 K x 4 Synchronous RAM .......................................... .
HM-6516/883
2K x 8 Synchronous RAM .......................................... .
HM-65162/883
2K x 8 Asynchronous RAM ......................................... .
1 K x 1 Synchronous RAM .......................................... .
HM-6518/883
HM-65262/883
16Kx 1 Asynchronous RAM ........................................ .
HM-6551/883
256 x 4 Synchronous RAM ......................................... .
HM-6561/883
256 x 4 Synchronous RAM ......................................... .
HM-6564
64K Synchronous RAM Module ..................................... .
HM-65642/883
8K x 8 Asynchronous RAM ......................................... .
HM-65642C/883
8K x 8 Asynchronous RAM ......................................... .
2K x 8 Fuse Link PROM ............................................ .
HM-6617/883
512 x 8 Fuse Link PROM ........................................... .
HM-6642/883
HM-8808/08A
8K x 8 Asynchronous RAM Modules ................................. .
16Kx 8 Asynchronous RAM Module ................................. .
HM-8816H
HM-8832
32K x 8 Asynchronous RAM Module ................................. .
HM-92560
256K Synchronous RAM Module .................................... .
256K Buffered Synchronous RAM Module ............................ .
HM-92570
1 M Bit Asynchronous RAM Module .................................. .
HM-91M2
Static 16-Bit Microprocessor ....................................... .
80C86/883
Static 8/16-Bit Microprocessor ..................................... .
80C88/883
Static 16-Bit Microprocessor ....................................... .
80C286/883
Clock Generator and Ready Interface for 80C286 Processors ........... .
82C284/883
Bus Controller for 80C286 Processors ............................... .
82C288/883
High Performance Programmable DMA Controller ..................... .
82C37A/883
Serial Controller Interface ........................................... .
82C52/883
Programmable Interval Timer ....................................... .
82C54/883
Programmable Peripheral Interface .................................. .
82C55A/883
Priority Interrupt Controller .......................................... .
82C59A/883
Octal Latching Bus Driver .......................................... .
82C82/883
Octal Latching Inverting Bus Driver .................................. .
82C83H/883
Clock Generator Driver ............................................. .
82C84A/883
Static Clock Controller/Generator ................................... .
82C85/883
Octal Bus Tranceiver ............................................... .
82C86H/883
Octal Bus Tranceiver ............................................... .
82C87H/883
Bus Controller .................................................... .
82C88/883
Bus Arbiter ....................................................... .
82C89/883

1-1

6-43
6-56
6-3
6-14
6-27
3-52
3-4
3-67
3-82
3-91
3-16
3-104
3-28
3-40
3-140
3-115
3-129
3-206
3-194
3-146
3-159
3-165
3-172
3-178
3-184
4-62
4-97
4-3
5-153
5-168
5-3
5-4
5-19
5-38
5-62
5-81
5-90
5-98
5-110
5-111
5-119
5-127
5-138

:z

.... !:!

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Za:

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Clu-

::::

CMOS Devices by Families
B/16-BIT MICROPROCESSORS
80C286/883
Static 16-Bit Microprocessor. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80C86/883
Static 16-Blt Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80C88/883
Static 8/16-Bit Microprocessor. ............. .'. . .. . . . . . . . . . . . . . . . . . . . . . . . . .
App Note 111
Harris 80C286 Performance Advantages Over the 80386 . . . . . . . . . . . . . . . . . . . ..
80C286/80386 Hardware Comparison. . . . . . . . . . . . . .. . . . . . . . . . . . . • . . . . . . . . .
App Note 112
App Note 120
Interfacing the 80C286-16 with the 80287-10 ..............................
BOCB6/BB PERiPHERAL CIRCUITS
82C37N883
High Performance Programmable DMA Controller.. . .. . ... .. . .. .. . ... . . . . . ..
82C52/883
Serial Controller Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
82C54/883
Programmable Interval Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82C55A/883
Programmable Peripheral Interface ........................................
82C59N883
Priority Interrupt Controller. . . . . . . . . . . . . . .. . •. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
App Note 109
82C59A Priority Interrupt Controller ...... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOCB6/BB BUS SUPPORT CIRCUITS
82C82/883
Octal Latching Bus Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82C83H/883
Octal latching Inverting Bus Driver .................. ... . . . . . . . . . . . . . . . . . . . .
82C84N883
Clock Generator Driver. . . . . . . . . . . . . . . . . . . . • . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
82C85/883
Static Clock Controller/Generator. . .. . .. . . . . . . . . .. . . . . . . . . . . . • . . . . . . . . . . . . .
Octal Bus Tranceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82C86H/883
82C87H/883
Octal Bus Tranceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82C88/883
Bus Controller. . . . . . . . . . .. . .. . .. . . .. ... .. . .. . . .. . .. . .. . .. . ... .. . .. .... . ..
82C89/883
Bus Arbiter .............................................................
BOC2B6 BUS SUPPORT CIRCUITS
82C284/883
Clock Generator and Ready Interface for 80C286 Processors. . . . . . . . . . . . . . . . .
82C288/883
Bus Controller for 80C286 Processors.. . ...... . .. . .. . . . . .. . .. . . . .. . . . ... . .
SERIAL COMMUNICATIONS CIRCUITS
HD-4702/883
Programmable Bit Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD-6402/883
Universal Asynchronous Receiver Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD-6409/883
Manchester Encoder-Decoder. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H 0-15530/883
Manchester Encoder-Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD-15531/883
Manchester Encoder-Decoder............................................
CMOS STATIC RAMs
1K - SYNCHRONOUS
HM-6508/883
1K x 1 Synchronous RAM ........................•.......................
HM-6518/883
1 K x 1 Synchronous RAM ...............•...........•....................
HM-6551/883
256 x 4 Synchronous RAM .............................................. .
HM-6561/883
256 x 4 Synchronous RAM ................................ .'............. .
4K - SYNCHRONOUS
HM-6504/883
4K x 1 Synchronous RAM ................................................
HM-6514/883
1K x 4 Synchronous RAM ................................................
16K - SYNCHRONOUS
HM-6516/883
2K x 8 Synchronous RAM ................................................
16K - ASYNCHRONOUS
HM-65162/883
2K x 8 Asynchronous RAM ....................... ,.......................
HM-65262/883
16K x 1 Asynchronous RAM ..............................................
64K - ASYNCHRONOUS
HM-65642/883
8K x 8 Asynchronous RAM ................•..............................
HM-65642C/883
8K x 8 Asynchronous RAM ...................................•......•....
CMOS RAM MODULE
HM-6564
64K Synchronous RAM Module ...................... . . . . . . . . . . . . . . . . . . . . .
HM-8808/08A
8K x 8 Asynchronous RAM Modules. . . . . . . . .. . . . . . . . . . . . . . . . . . .. . .. . . . . . ..
HM-8816H
16K x 8 Asynchronous RAM Module. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HM-8832
32K x 8 Asynchronous RAM Module. . .. . . . . . . . . . . . . . . .. . . . . •. . . . . . . . . . . . . .
HM-92560
256K Synchronous RAM Module. . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . .
HM-92570
256K Buffered Synchronous RAM Module. . . . . . . . . . . . . . . . . . . . . . . • • .. . . . • • ..
HM-91 M2
1 M Bit Asynchronous RAM Module. . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . .. • . . . . ..
CMOS FUSE lINK PROMs
HM-6642/883
512 x 8 Fuse Link PROM ...........................•.....•.•.....•.......
HM-6617/883
2K x 8 Fuse link PROM .•. . . • . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2

PAGE
4-3
4-62
4-97
'4-131
4-143
4-147
5-3
5-4
5-19
5-38
5-62
5-169
5-81
5-90
5-98
5-110
5-111
5-119
5-127
5-138
5-153
5-168
6-3
6-14
6-27
6-43
6-56

3-4
3-16
3-28
3-40
3-52
3-67
3-82
3-91
3-104
3-115
3-129
3-140
3-146
3-159
3-165
3-172
3-178
3-184
3-194
3-206

Ordering Information
Harris Semiconductor products are represented by
an extensive network of factory sales personnel, sales
representative, and authorized distributors throughout the world. Please contact your nearest sales
office, representative, or distributor for product information, pricing, ordering, or delivery details. A
complete list of sales offices is available by contacting
the Harris Semiconductor literature department at
(407) 724-3739. Headquarters are also listed at the
end of this book.

Product Code
Harris products are designated by a "Product Code".
This code includes designators for the product family,
device type, performance grade, temperature grade
and package style. Examples of the product codes
are shown below:

PRODUCT CODE EXAMPLE

H

1

M

8

PREFIX:~~

/883

I

H: Harris

FAMILY:
D: Digital
M: Memory

B:
C:
S:
Blank:

PACKAGE:
1: Ceramic DIP
1B: Ceramic Sidebrazed DIP
4: Leadless Chip Carrier (LCC)
5: Ceramic Substrate
6: Slim line DIP

TEMPERATURE GRADE:
-8: -550 C to +125 0 C
Harris Class B Equivalent
Devices For Use In
Military and Flight Systems
-Q: -550 C to +125 0 C
High Performance
Harris Class S Equivalent
Relaxed Specification
Devices For Use In
High Speed
Spacecraft or High-Rei
Standard
Applications
Performance
/883: Fully Compliant to
MIL-STD-883
-BXXX: Altered to Customer
Specifications. B Number
is Uniquely Assigned
to Specific Customer
Requirements

MICROPROCESSOR/PERIPHERAL PRODUCT CODE

M

~

TEMPERATURE
RANGE:
M: -55 0 C to +125 0 C

J
D

80C86

I

PART NUMBER
80CXXX: CMOS
Microprocessor
82CXXX: CMOS
Peripherals

PACKAGE:
D: Ceramic DIP
R: Leadless Chip Carrier (LCC)
G: Pin Grid Array

2

/883

I

TEMPERATURE/GRADE
/883: Fully Compliantto
MIL-STD-883

SPEED DESIGNATION:
PERIPHERALS
MICROPROCESSORS
Blank: 5MHz
5: 5MHz
Blank: 8MHz
2: 8MHz

1-3

Packaging Techniques
The chart indicates a 220% improvement in packaging area for the 18 lead LCC, and 542% improvement
for the 48 lead LCC. Obviously, sizeable savings in
circuit board area can be achieved with this packaging option. The second major advantage of the LCC is
in electrical performance. The package size and
geometry also dictates trace length and uniformity.
Figure 2 provides a comparison between the trace
lengths for various LCCs and side-braze DIPs. As pin
count goes up, trace lengths get longer, adding resistance and capacitance unequally around the package. As ICs get faster and more complex these factors
start to become a limiting factor on performance.
LCCs minimize this effect by maintaining, as close as
possible, uniform trace length so that the package is a
significantly smaller determinant of system performance.

Harris Semiconductor offers Leadless Chip Carriers
(LCC) as a packaging option on various Digital
integrated circuits. An LCC is a square or rectangular
package for an Integrated Circuit (I C) that is manufactured in the same manner as a conventional
side-braze dual-in-line package (DIP). The LCC is
comprised of the cavity and seal ring section of a
standard DIP and offers the user a means of achieving high density system configurations while retaining
the reliability benefits of hermetic IC Packaging.
Figure 1 provides a comparison of the construction of
an LCC and a conventional side-braze DIP.

FIGURE 1.

EXPLODED VIEW OF CHIP CARRIER AND DIP

The LCC's two principle advantages over conventional side-braze DIPs are packaging density and electrical performance. Packaging density is the number
one advantage to an LCC over a side-braze DIP. The
size of a DIP is governed primarily by the number of
leads required and not by the size of the IC. As pin
count increases, more and more of the DIP package
is used only to provide an electrical trace path to the
external leads. The size of an LCC is dependent on
the size of the die not on the numper of leads. As pin
count increases, overall size increases but at a much
slower rate. Table'1 'provides a comparison between
the areas of 18, 28 and 48 lead LCCs to 18, 28 and
48 lead side-braze DIPs.
TABLE 1
LEAD
COUNT

LCC
AREA

DIP
AREA

18
28
48

0.10
0.20
0.31

0.22
0.84
1.68

, DIPAREAvs.
LCCAREA
220%'
420%
542%

LEAD
COUNT

LONGEST TRACE DIP
LONGESTTRACELCC

LCC

DIP

18

2:1

1.5:1

6:1

24

4:1

1.5:1

3:1

40

5:1

1.5:1

6:1

54

6:1

1.5:1

7:1

FIGURE 2.

LONGEST TRACE
SHORTEST TRACE

ELECTRICAL PERFORMANCE
(RESISTANCE AND SPEED)

The LCC also offers environmental advantages over
"chip-and-wire'" manufacturing techniques used in
high density hybrid circuits. An IC can be fully tested,
burne,d-in and processed in an LCC, thereby guaranteeing its performance.
The IC is further protected by a small hermetic package in which internal vapor content dm be carefully,
controlled during production.
Harris Semiconductor Leadless Chip Carriers in both
Ceramic and Epoxy provide reliable, high density,
high performance packaging options for today's systems.
Consult the factory or your Harris sales representative
for pricing and availability.

(All Units in Square Inches)

1-4

Harris Digital

Ie Technologies

Self Aligned Junction Isolation (SAJI)
The most prevalent CMOS Technology was patented
by Harris (#4,135,955) and has been in production at
Harris since 1980. It incorporates self-aligned guard
ring techniques and more recently planarization prior
to first metal into the traditional complementary transistor structures.
The process begins on 1-0-0 N- type silicon,
although a process option is available with N epi over
N++ starting material to eliminate circuit latch-up due
to parasitic SCR action. A sequence of oxidation,
photo resist delineation, Boron implant and diffusion
create the P well for the N channel devices. A critical
feature of the diffusion causes all of the silicon crystal
defects to be annihilated, resulting in a defect free
zone for the transistors to be fabricated.
Next, silicon nitride is deposited and etched to define
the active NMOS and PMOS areas followed by
implants which create the self aligned guard ril'lgs
around the active devices. These guard rings provide
electrical isolation between transistors and also raise
the field thresholds of the parasitic MOS devices to
allow leakage-free circuit operation. The self aligning
of these guard rings allows a substantial reduction in
circuit area.
Following is the local oxidation and the conventional
formation of the poly gate MOS transistors. The electrical channel length of these all implanted devices is
1.5 micron.
The field oxide an~ metalization structure are based
on a time proved reflowed glass process with one
important improvement. Prior to metal deposition the
surface is planarized and the walls of the contacts
are· sloped which creates a final topography with
excellent interconnect step coverage. The aluminum
interconnect is silicon doped to prevent contact

SOURCE METAL

spiking and improved reliability. The passivation,
metalization and layout rules guarantee electromigration free operation at +125 0 C for over ten years.
The principal advantages of the process can be summarized as: • Low leakage operation
• Latch-up free option
• Good packing density
• Excellent step coverage
• Electromigration free designs
This process has been successfully applied to numerous designs including static RAMs, microprocessors,
peripherals, and custom ROM circuits.
Z

L7

..... S!

A newer, higher performance process, named L7,
builds on and enhances the basic CMOS technology.
This 1.5 micron process has several advantages over
the older 2.5 micron version. The epi over N++ starting material is standard with the epi thickness being
scaled down in concert with the P well and device
junctions. This brings even more latch-up immunity to
all circuits on this technology.

We
.......
25

Transistors achieve electrical channel lengths of 1.0Jl
typical with the N channel incorporating a double diffused LDD structure which eliminates susceptibility to
hot electron damage. Of greatest impact is the use of
a planarized double layer metal structure allowing
greater layout freedom without introducing step coverage or electroinigration concerns. The low stress
oxinitride passivation provides moisture protection in
plastic packages.
The L7 process with its added features has been successfully employed on numerous semicustom' and
standard cell designs as well as supplying production
quantities of the 80C286 microprocessor.

SILlCON-

DRAIN METAL

FIGURE 3. SILICON-GATE PFET STRUCTURE
CROSS-SECTION SHOWS THE HEAVILY DOPED SOURCE AND
DRAIN REGION. THEY ARE SEPARATED BY THE NARROW GAP
OVER WHICH LIES A THIN-GATE OXIDE AND GATE MATERIAL.

1-5

<2<
w::;:

Za:;

Ie

Handling Procedures ' - - - - - - - - - ,

Harris Digital IC processes are designed to produce
the most rugged products on the market. However, no
semiconductor is immune from damage resulting
from the sudden application of many thousands of
volts of static electricity. While the phenomenon of
catastrophic failure of devices containing MOS transistors or capacitors is well known, even bipolar
circuits can be damaged by static discharge, with
altered electrical properties and diminished reliability.
None of the common IC internal protection networks
operate quickly enough to positively prevent damage.
It is suggested that all semiconductors be handled,
tested, and installed using standard "MOShandling
techniques" of proper grounding of personnel and
equipment. Parts and subassemblies should not be in
contact with untreated plastic bags or wrapping material. High impedance IC inputs wired to a P.C.
connector should have a path to ground on the card.
Handling Rules
Since the introduction of integrated circuits with MOS
structures and high quality junctions, a safe and effective means of handling these devices has been' of
primary importance. One method employed to protect
gate oxide structures is to incorporate input protection diodes directly on the monolithic chip. However,
there is no completely foolproof ,system 'of chip input
protection in existence in the 'industry. In addition,
most compenl;lation networks in linear circuits are
located at high impedance nodes, where protectfon
networks would disturb normal circuit operation. If
static.d.ischarge occurs at sufficient magnitude (2kV
or more), 'some damage or degradation will usually
occur. It has been found that handling equipment and
personnel can generate static potentials in excess of
10kV in a low humidity environment. Thus it becomes
necessary foradditional measures to be implemented
to eliminate or reduce static charge. It is evident,
therefore, that proper handling procedures or rules
should be adopted.

Elimination or reduction of static charge ,can be
accomplished as follows:
• Use static-free work stations. Static-dissipative
mats on work benches and floor, connected to
common point ground through a 1 MO resistor,
help eliminate static build-up and discharge. Do
not use metallic surfaces.
• Ground ail handling equipment. '
• Ground all handling personnel with a conductive
. bracelet through 1 MO to ground (the 1MO resistor
will prevent electroshock', injury to personnel). Transient product ,personnel should wear grounding
heel straps when conductive ,flooring is present.
• Smocks and clothing ,of certain insulating materials (notably nylon) should not be worn in areas
where devices are handled. These materials, highly dielectric in nature, will hold, or aid in the, generation .of a static charge. Where they cannot be
eliminated, natura,1 materials sucta,as cotton should
be used to minimize charge generation capacity.
Conductive smocks are also available as an alternative,
.. Control relative humidity to as high a level as
practical. 50% is generally considered sufficient.
(Operations should cease if R.H. falls below 25%).
• lonize,d air blowers reduce charge build-up in
areas where grounding is not possible or practical.

1-6

• Devices should be in conductive static-shielded
containers during all phases of transport. Leads
may be shorted by, tubular metallic carriers,
cqnductive foam, or f O i l . '
,
• In automated handling equipment, the belts,
chutes, or other surfaces should be of conducting
non-metal material. If this is not possible, ionized
air blowers or ionizing bars may be a good alternative.

ESD Handling Procedures - - - - - - - - - - ,
Harris has developed a static control program that
enables employees to detect problems generated by
static electricity whether on site, in transit, or in the
field. Controlling the requirements, methods, materials, and training for static protection of our products is
ongoing and updated with new developments in
electrostatic prevention. Harris has responded with
controls and procedures as part of daily operations to
be followed in all are~s.
The challenge is to insure all electrostatic control procedures are followed throughout the system - from
manufacturing through end use. Unprotected integrated circuits can be destroyed or functionally altered
by merely passing them through the electrostatic field
of something as simple as styrofoam or human contact.
N

Measures of Protection and Prevention
When handling static sensitive devices, three standard procedures must be followed:
1. Prior to any handling of static-sensitive components, the individual must be properly grounded.
2. All static-sensitive components must be handled
at static safeguarded work stations.
3. Containers and packing materials that are staticprotective must be used when transporting all
static-sensitive components.
Special handling equipment (static-safeguarded
work stations, conductive wrist straps, static-protected packaging, ionized air blowers) should be
used to reduce damaging effects of electrostatic
fields and charges.
Static-safeguarded work station is an area that is
free from all damaging electricity, including people.
To accomplish this, static on conductors and
nonconductors must be controlled.

l

Controlling electrically conductive items can be
accomplished by bonding and grounding techniques.
The human body is considered a conductor of
electricity and is by far the greatest generator of static
electricity. Personnel handling ICs must use conductive wrist straps to ground themselves. Simple
body moves act like a variable capacitor, and
can create static charges. In addition, conductive
clothing is recommended for minimizing electrostatic
build up.
Static protective packaging prevents electric field
from influencing or damaging ICs. An effective staticprotective package exhibits three types of features:
1. Antistatic protection that prevents triboelectric or
frictional charging,
2. Dielectric protection that insulates discharging,
and
3. Shielding or Faraday cage protection that prevents
transient field penetration.
Harris uses only packaging that exhibits all three
features. Employees are required to adhere to the
same static-protective packaging techiques during
handling and shipment to assure device integrity is
maintained.
Ionized air blowers aid in neutralizing charges on
nonconductors such as synthetic clothing, plastics,
and Styrofoam The blowers are placed at the work
site and in close proximity to the IC handling area,
since nonconductors do not lose or drain charges
using normal grounding techniques.
N.

By using wrist straps, static-protected work stations
and static-protected containers, Harris product quality is maintained throughout the product cycle.

l

ESD PROTECTIVE
TRAYS.ETC.
(C)
ESD PROTECTIVE
TABE TOP
(A)

Y
CHAIR
WITH GND
(OPTIONAL)

Y

ESD PROTECTIVE

'I~"~_,J.R:"'J~(~O~P~TIO:AL)

FLOOR MATl
WORKBENCH

FIGURE 4. STATIC-SAFEGUARDED WORK STATION
NOTE 1. All electrical equipment on the conductive table top must be hard grounded and isolated from the table top.
2. Earth ground is not computer ground or RF ground or any other limited ground.
SlyrofoamT» is a trademark of Dow Chemical Corporation

1-7

Harris Product Specification Highlights
Harris Semiconductor is a leading supplier of high
reliability integrated circuits to the military and
aerospace community and takes pride in offering
products tailored to the most demanding applications
requirements. Our Manufacturing facilities are JANCertified to MIL-M-38510 and provide JAN-qu'alified
ilnd MIL-STD-'883 compliant products as standard
data book items. This Digital Military Products Data
Book contains detailed information on high-reliability
integrated circuits presently available from Harris
Semiconductor.

Absolute Maximum Ratings: These ratings are provided as maximum stress ratings and should be taken
into consideration during system design to prevent
conditions which may cause permanent damage to
the device. Operation of the device at or above the
"Absolute Maximum Ratings" is not intended, and extended exposure may affect the device reliability.
Reliability Information: Each /883 data sheet contains thermal informatio.n relating to the package and
die. This information is intended to be used in system
design for determining the expected device junction
temperatures for overall system reliability calculations..
.

The intent of the 1883 data sheet is to provide to our
customers a clear understanding of the·testing being
performed in conformance with MIL-STD-883 requirements. Additionaliy, it is our intent to provide the
most effective and comprehensive testing feasible.

Packaging: Harris utilizes MIL-M-38510, Appendix
C for packages used for /883 products. The mechanical dimensions and materials used are shown for
each individual product to complete each data sheet
as a self contained document.

This data book is organized in 8 different sections,
each being identified by the darkened tab Index
which is provided as a visual guide to the· reader.
Each section covers a specific topic or product line,
such as CMOS Memories, CMOS Microprocessors
and General Information. Section 7 emphasizes the
Harris commitment to Quality and Reliability in' all
levels of production, test and documentation, and
may be of special interest to military customers.'

D.C. and A.C. Electrical Parameters: Tables 1 and
2 define the D.C. and A.C. Electrical Parameters that
are 100% tested in production to guarantee compliance to MIL-STD-883. The subgroups used are
defined In MIL-STD-883, Method 5005 and designated under the provisions of Paragraph 1.2.1a. Test
Conditions and Test Circuits are provided for specific
parameter testing.

Document Control
Harris has I!lstablished each of the /883 data sheets
as an internally revision controlled document. Any
product revision or modification must be approved
and Signed-off throughout the manufacturing and
engineering sections. Harris has made every effort to
ensure accuracy of the information in this data book
through quality control methods. Harris reserves the
right to make changes to the products contained in
this data book to improve performance, reliability and
producibility. Each data sheet will use the printed date
as the revision control identification. Harris has also
established a Data Sheet Registration Program to
inform users of data sheet updates. Registration is
done through the sign-up card attached· to the back
of this data book. Otherwise, contact Harris .lor the
latest available specifications and performance data.

/883 Data Sheet Highlights
Each specific /883 data sheet documents the
features, description, pinouts, tested electrical parameters, test circuits, burn-in circuits, die characteristics, packaging and design information. The following
are notes and clarifications that will help in applying
the information provided in the data sheet.

Table 3 provides additional device limits that are guaranteed by characterization' of the device and are not
directly tested in production. Characterization takes
place at initial device design and after any major process or design changes. The characterization data is
on file and available demonstrating the test limits
established.
Table 4 provides a summary of the test requirements
and the applicable MIL-STD-883 subgroups.
Burn-in Circuits: The Burn-in circuits defined in the
individual data sheets are those used in the actual
production process. Burn-in is conducted per MILSTD-883, Method 1015.
Design Information Sections: Harris provides an
additionai Design Information Section in many of the
data sheets to assist in system application and
design. This. information may be in the form of
applications circuits, typical device parameters, or
additional device related user information such as
programming information. While this information cannot be guaranteed, it is based on actual
characterization of the product and is representative
of the data sheet device.

1-8

.--------- High Reliability Products Information - - - - - - ,
Harris' High Reliability Products are all produced in
accordance with military specifications and standards, primarily MIL-M-38510 (General Specifications
for Microcircuits) and MIL-STD-883 (Test Methods
and Procedures for Microelectronics).

sizes and specific tests performed depend upon the
particular product assurance class chosen. Electrical
test sampling is performed on all subgroups as defined in MIL-STD-883, Method 5005.
Group B inspection includes tests for marking permanency, internal visual and mechanical correctness,
bond strength, and solderability. It is intended to provide assurance of the absence of lot-to-Iot fabrication
and manufacturing variances. Group B tests are again
defined in test Method 5005.

MIL-M-38510 provides the ground rules for standardization in the manufacturing, testing and qualification of Integrated Circuits which are applicable to
all qualified suppliers. MIL-M-38510 delineates two
product assurance levels of screening, sampling, and
documentation control requirements (Class Sand
Class B).

Group C is oriented toward die integrity and consists
of operating life testing as defined in MIL-STD-883,
Method 5005.

Class S is intended for use in manned space flight or
extreme high reliability aerospace applications where
replacement is extremely difficult or impossible.

Group 0 environmental testing is provided to verify
die and package reliability. Among the Group D tests
are lead integrity, hermeticity, temperature cycling,
thermal and mechanical shock, and constant acceleration.

Class B is intended for use in unmanned space flight,
high reliability ground systems or commercial "hi-reliability use". These devices are the most frequently
procured military ICs.
MIL-STD-883 contains test methods and procedures
for various electrical, mechanical and environmental
tests as well as requirements for screening, qualification and quality conformance inspection. Method
5004 of MIL-STD-883 lists the 100% screening tests
which are required for each of the product assurance
classes defined above.
Following the device screening, samples are removed
from the production lot(s) for Quality Conformance
Inspection testing. This testing is divided into four inspection groups: A, B, C and D, which are performed
at prescribed intervals per MIL-M-38510 to assure
the processes are in control and to ensure the continued quality level of the product being produced.
Group A electrical inspection involves dynamic, static, functional and switching tests at maximum, minimum and ambient operating temperatures. Sample

MIL-M-38510 requires that Group A and Group B
inspection be performed on each lot, while Group C
inspection must be done every 3 months and Group
D every 6 months to be in compliance with MIL-M38510 JAN requirements. To limit the amount of
testing, MIL-M-38510 allows the multitude of microcircuits to be grouped by technology, commonly
known as '~generic families". Thus, one group C
performed will cover all parts included in that generic
family for three months. For Group D, which is package related, although there are some restrictions, one
Group D performed on a 24-pin ceramic dual-in-line
packaged part will cover all devices in the same package regardless of the technology group.
For MIL-STD-883 products, Groups A and Bare
required on each lot, Groups C and D are required
every 52 weeks by generic die family and package
fabricated and manufactured from the same plant as
the die and package represented.

1-9

Z

-09

~<
w:;;
Za:
WQ

"' ....~

. - - - - - - - - - - General Test Philosophy -----------..,
The general philosophy for test set development is to
supply test software that guarantees the high
performance and quality of the products being
designed and manufactured by Harris. The general
.final test set includes a guardbanded initial test program and a QA test program for the quality test step.•
Characterization software is an additional test program that parametrically measures and records the
performance of the device under test. This test set is
used to evaluate the performance of a product and to
determine the acceptability of non-standard Source
Control Drawings. BSPEC test programs are custom
final test programs written to conform to customer
specifications.
The general test development strategy is to develop
software using a "shell" programming technique
which creates standard test program flows, and
reduces test development and execution times.
Statistically derived guardbands are utilized in the
"shell" programs to null out test system variability.
High performance hardware interface designs are
incorporated for maximized test effectiveness, and
efficient fault graded vector sets are utilized for functional and AC testing.
The initial step in generating the test set is the test
vector generation. The test vectors are the binary
stimulus applied to the device under test to

functionally test the operation of the product. The vectors are developed against a behavioral model that is
a software representation of the device functionality.
The output of the behavioral model can be translated
directly to ATE test vectors or prepared for CAD
simulation.
The philosophy in the generation of test vectors is to
develop efficient fault graded patterns with a goal of
greater than 90% fault coverage. There is no intent to
generate a worst case or best case noise vector set.
The intent is to maximize fault coverage through efficient vector use. Generally only one vector set will be
required to enable complete test coverage within a
given test program. Exceptions to this would be vector generation to test certain identified critical AC
speed paths or DC vectors for testing VIHNIL parameters. These vector sets typically will not increase fault
coverage and can not be substituted for fault graded
vector sets.
The ultimate goal for testing all military 1883, SMD
and JAN products is data sheet compliancy, thoroughness, and quality of testing. By taking this
approach to test set generation, Harris is capable of
supplying high performance semiconductors of the
highest quality to the marketplace.

1-10

Harris Semiconductor
- ----- ----_.
- -=== --:= -==--=
===
---- --- -

No. 52

Harris Digital

February 1989

ELECTROSTATIC DISCHARGE CONTROL
A GUIDE TO HANDLING INTEGRATED CIRCUITS
This paper discusses methods and materials recommended
for protection of ICs against ESD damage or degradation
during manufacturing operations vulnerable to ESD exposure. Areas of concern Include dice prep and handling, dice
and package inspection, packing, shipping, receiVing,
testing, assembly and "all operations where ICs are involved.
All integrated circuits are sensitive to electrostatic discharge (ESD) to some degree. Since the introduction of
integrated circuits with MOS structures and high quality
junctions, safe and effective means of handling these devices have been of primary importance.
If static discharge occurs at a sufficient magnitude, 2kV or
greater, some damage or degradation will usually occur. It
has been found that handling equipment and personnel can
generate static potentials in excess of 10kV in a low humidity environment; thus it becomes necessary for additional
measures to be Implemented to eliminate or reduce static
charge. Avoiding any damage or degradation by ESD when
handling devices during the manufacturing flow is therefore
essential.

ESD Protection and
Prevention Measures
One method employed to protect gate oxide structures is to
incorporate input protection diodes directly on the monolithic chip. However, there is no completely foolproof system of
chip input protection in existence in the Industry.
In areas where ICs are being handled, certain equipment
should be utilized to reduce the damaging effects of ESD.
Typically, equipment such as grounded work stations,
conductive wrist straps, conductive floor mats, ionized air
blowers and conductive packaging materials are included
in the IC handling environment. Any time an individual Intends to handle an IC, in any way, they must Insure they
have been grounded to eliminate circuit damage.
Grounding personnel can, practically, be performed by two
methods. First, grounded wrist straps which are usually
made of a conductive material, such as Velostat or metal. A
resistor value of 1 megohm (1/2 watt) in series with the
strap to ground completes a discharge path for ESD when
the operator wears the strap in contact with the skin. Another method is to insure direct physical contact with a
grounded, conductive work"surface.
This consists of a conductive surface like Velostat, covering
the work area The surface Is connected to a 1 megohm
(1/2 watt) resistor In series with ground.

In addition to personnel grounding, areas where work is being performed with ICs, should be equipped with an ionized
air blower. Ionized air blowers force positive and negative
ions simultaneously over the work area so that any
nonconductors that are near the work surface would have
their static chargE! neutralized before it would cause device
damage or degradation.
Relative humidity in the work area should be maintained as
high as practical. When the work environment Is less than
40% RH, a static build-up condition can exist on
nonconductors allowing stored charges to remain near the
ICs causing possible static electricity discharge to ICs.
Integrated circuits that are being shipped or transported
require special handling and packaging materials to eliminate ESD damage. Dice or packaged devices should be in
conductive carriers during all phases of transport and handling. Leads of packaged devices can be shorted by
tubular metalic carriers, conductive foam or foil.

Do's and Don'ts for
Integrated Circuit Handling
Do's
Do keep paper, nonconductive plastic, plastic foams and
films or cardboard off the static controlled conductive
bench top. Placing devices, loaded sticks or loaded burn~in
boards on top of any of these materials effectively insulates
them from ground and defeats the purpose of the static controlled conductive surface.
Do keep hand creams and food away from static controlled
conductive work surfaces. If spilled on the bench top, these
materials will contaminate and increase the resistivity. of the
work area.
Do be especially careful when using soldering guns around
conductive work surfaces. Solder spills and heat from the
gun may melt and damage the conductive mat.
Do check the grounded wrist strap connections daily. Make
certain they are snugly fitted before starting work with the
product.
Do put on grounded wrist strap before touching any devices. This drains off any static build-up from the operator.
Do know the ESD caution symbols.
Do remove devices or loaded sticks from shielding bags
only when grounded via wrist strap at grounded work station. This also applies when loading or removing devices
from the antistatic sticks or the loading on or removing from
the burn-in boards.

Copyright @ Harris Corporation 1989

1-11

Tech Brief 52
Do wear grounded wrist straps in direct contact with the
bare skin - never over clothing.

driver circuits when not grounded. "This also applies to
bUrn-in programming cards containing ICs.

Do use the same ESD control with empty bUrn-in boards as
with loaded boards if boards contain permanently mounted
ICs as part of driver circuits.

Don't unload stick on a metal bench top allowing rapid discharge of charged devices.
Don't touch leads. Handle devices by their package even
though grounded.

Do insure electrical test equipment and solder irons at an
ESD control station are grounded and only uninsulated metal hand taols be used. Ordinary plastic solder suckers and
other plastic assembly aids shall not be used.

Don't allow plastic "snow or peanut" polystyrene foam or
other high dielectric materials to come in contact with devices or loaded sticks or loaded burn-in boards.

Do. use ionizing air blowers in static contralled areas when
the use of plastic (nanconductive) materials cannot be
avoided.

Don't allow rubber/plastic floor mats in front of static controlled work benches.
Don't solvent-clean devices when loaded in antistatic sticks
since this will remove antistatic inner coating from sticks.

Don'ls
Don't allow anyone not grounded to touch devices, loaded
sticks or loaded bUrn-in boards. To be grounded they must
be standing on a conductive floor mat with conductive heel
straps attached to foatwear or must wear a graunded wrist
strap.

Don't use antistatic sticks for more than one throughput
process. Used sticks should not be reused unless recoated.

Recommended Maintenance
Procedures
Daily:

Don't touch the devices by the pins or leads unless
grounded since most ESD damage is done at these points.

Perform visual inspection of ground wires and terminals
on floor mats, bench tops, and grounding receptacles to
ensure that proper electrical· connections via 1 megohm
resistor (1/2 watt) exist.

Don't handle devices or loaded sticks during transport from
work station to work station unless protected by shielding
bags. These items must never be directly handled by anyone not grounded~
.

Clean bench top mats with a soft cloth" or paper towel
dampened with a mild solution of detergent and water.

Don't use freon or chlorinated cleaners at a grounded work
area.

Weekly:

Don't wax grounded static controlled conductive flaor and
bench top mats. This would allow build-up of an insulating
layer and thus defeating the purpose af a conductive work
surface.

Damp mop conductive floor mats to remove any accumulated dirt layer which causes high resistivity.
Annually:
Replace nuclear elements for ionized air blowers.

Don't touch devices or loaded sticks or loaded bUrn-in
boards with clothing or textiles even though grounded wrist
strap is worn. This does not apply if conductive coats are
WOrn.

Review ESD protection procedures and" equipment for updating and adequacy.

Static Controlled Work Station

Don't allow personnel to be attached to hard graund. There
must "always be 1 megohm series resistance (1/2 watt
between the person and the ground).

The figure below shows an example of a work bench properly equipped to control electro-static discharge. Note that
the wrist strap is connected to a 1 megohm resistor. This
resistor can be omitted in the setup if the wrist strap has a
1 megohm assembled on the cable attached.

"Don't touch edge connectors of loaded bUrn-in boards or
empty bUrn-in boards containing. permanently mounted

R

WRIST STRAP GRaUND
LEAD IS ATTACHED TO.
caNDucTIVE BENCH Tap

-v::!v
ESD WARNING SYMBaLS

R

t::>

-

caNDucTIVE WRIST
STRAP

caNDucTIVE BENCH Tap
1/ /

/

/' /

/

/' /' /'

I'-r,-----:------,,-'
I I CONDUCTIVEFlaaR MAT

'\7

R

GRaUND. I.e. CaLD WATER
PIPE aR EQUIVALENT

R = 1 MEGaHM

1-12

PAGE
MILITARY GRADE PRODUCT OFFERINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .

2-3

HARRIS/883/JAN/DESC PART NUMBER LISTING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-4

MILITARY PRODUCT PROGRAM CONTROLS. ... . . . . . ... . ... .... . .... . .. . .... ... .... ..

2-7

PROGRAMS SERVED BY HARRIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-8

2-1

~------

Military Grade Product Offerings - - - - - - - - ,

Harris High Reliability Products are offered in the
following Military grades:

tions than those appearing on the MIL-M-38510
slash sheet or SMD describing the same generic
device. Harris recommends using our /883 data
sheets as the baseline for new military or aerospace
source control drawings.

• JAN (Joint Army Navy)
Registered trademark of the U.S. Government
indicating that a device is fully compliant to MIL-M38510. The Defense Electronics Supply Center
(DESC) maintains a continuing audit of manufacturing compliance. There are two product assurance
classes available for M38510 products (Class S
and B). Devices are defined and identified by their
particular detail specification or "slash sheet" number issued by DESC (eg. M38510/29104BJX). The
IC manufacturers who are qualified to supply products to a particular M38510 slash sheet are
identified in the Qualified Products List (QPL)
issued by DESC.

• Harris Class B "Equivalent"
These devices are processed and tested in a
manner equivalent to the MIL-STD-883 compliant
devices. They may not be classified as compliant
since government standards have not been established for processing these types of components
(eg. Ram Modules). The Class 8 "Equivalent"
products can be identified by the -8 suffix on the
Harris part number.
• Non-Standard Product Offerings

• SMD (Standard Military Drawing)
The SMD evolved from the DESC drawing program
which was viewed as a preliminary specification prior to JAN approval. SMDs were created to control
the proliferation of non-standard Source Control
Drawings. The Standard Military Drawing provides
standardized MIL-STD-883 processing in conjunction with non-JAN devices as specified in
paragraph 1.2.1 of MIL-STD-883. These devices
are defined and identified by their Standard Military
Drawing number issued by DESC (eg. 59628757701 RA). The manufacturers qualified to supply
a particular SMD device are listed in the back of the
individual Standard Military Drawing.
• Harris Class B Compliant
These devices are fully compliant to MIL-STD-883,
Class 8 and are identified by the /883 suffix on the
Harris part number. The parametric limits for an
/883 data sheet are controlled by the manufacturer
rather than a governmental agency, and therefore,
there may be differences in the test methodology
and actual limits for "similar" devices made by
different manufacturers.
This manufacturer control of the /883 specifications
allows the offering of 883-level products long before they might become available as MIL-M-38510
or SMD devices. In many cases, Harris actually
specifies /883 devices with more stringent condi-

2-3

Harris understands the need for customer generated Source Control Drawings with non-standard
parameter and/or screening requirements. A Customer Engineering Department is responsible for
efficiently expediting the SCDs through a comprehensive review process. Our Customer Engineering
Group compares the SCD to its closest equivalent
product grade and works closely with the Product
Engineer, Manufacturing Engineer, Design Engineer, or applicable individual to compare Harris'
screening ability against the customer's non-standard requirement(s). For products processed to
non-standard requirements, a unique part number
suffix is assigned.
Harris shares the military's objective to utilize standards wherever possible. We recommend using our
/883 data sheets as guidelines for generating new
Source Control Drawings. In instances where an
available military specification or Harris /883 data
sheet is inappropriate, it is Harris' sincerest wish to
work closely with the customer in establishing an
acceptable procurement document. For this reason,
the customer is requested to contact the nearest
Harris Sales Office or Representative before finalizing the Source Control Drawing. Harris looks forward to working with the customer prior to implementation of the formal drawing so that both parties
may create a mutually acceptable procurement
document.

, - - - - - Harris/883/JAN/DESC Part Number Listing -------,
HARRIS PART #

JAN PART #

SMD/DESC PART #

/883 PART #

MICROPROCESSOR PRODUCTS
MG80C286-12

MG80C286-12/883

MG80C286-10

MG80C286-10/883

MD82C284-12

MD82C284..,12/883

MD82C284-10

MD82C284-10/883

MD82C288-12

MD82C288-12/883

MD82C288-10

MD82C288-10/883

MD80C86

8405201QA

MD80C86/883

MR80C86

8405201XA

MR80C86/883

MD80C86-2

M D80C86-2/883

MR80C86-2

MR80C86-2/883

MD80C88

MD80C88/883

MR80C88

MR80C88/883

MD80C88-2

M D80C88-2/883

MR80C88-2

MR80C88-2/883

MD82C37A

MD82C37A/883

MR82C37A

MR82C37A/883

MD82C37A-5

. MD82C37A-5/883

MR82C37A-5

MR82C37A-5/883

MD82C52

8501501XA

MD82C52/883

MR82C52

85015013A

MR82C52/883

MD82C54

8406501JA

MD82C54/883

MR82C54

84065013A

MR82C54/883

MD82C55A

8406602QA

MD82C55A/883

MR82C55A

8406602XA

MR82C55A/883

MD82C55A-5

8406601QA

MD82C55A-5/883

MR82C55A-5

8406601XA

MR82C55A-5/883

MD82C59A

5962-8501602YA

MD82C59A/883

MR82C59A

5962-85016023A

MR82C59A/883

MD82C59A-5

5962-8501601YA

M D82C59A-5/883
MR82C59A-5/883

MR82C.59A-5

5962-85016013A

MD82C82

8406701RA

MD82C82/883

MR82C82

84067012A

MR82C82/883

MD82C83H

8406702RA

MD82C83H/883

MR82C83H

84067022A

MR82C83H/883

MD82C84A

8406801VA

MD82C84A/883

MR82C84A

84068012A

MD82C85

MR82C84A/883
MD82C85/883

MR82C85

MR82C85/883

MD82C86H-5

5962-8757701 RA

MD82C86H-5/883

MR82C86H-5

5962-87577012A

MR82C86H-5/883

MD82C87H-5

5962-8757702RA

MD82C87H-5/883

MR82C87H-5

5962-87577022A

MR82C87H-5/883

MD82C88

8406901RA

MD82C88/883

MR82C88

84069012A

MR82C88/883

MD82C89

5962-8552801 RA

MD82C89/883

MR82C89

5962-85528012A

MR82C89/883

2-4

,...------ Harris/883/JAN/DESC Part Number Listing -------,
HARRIS PART #

JAN PART #

SMD/DESC PART #

/883 PART #

DATA COMMUNICATION PRODUCTS
HD1-6409

HD1-6409/883

HD1-15530

7802901JA

HD1-15530/883

HD4-15530

78029013A

HD4-15530/883

HD1-15531

HD1-15531/883

HD1-15531 B

HD1-15531 B/883

HD1-4702

HD1-4702/883

HD1-6402

H D1-6402/883

CMOS MEMORY PRODUCTS
1K CMOS STATIC RAMs
HM1-6508

HM1-6508/883

HM1-6508B

HM1-6508B/883

HM1-6518

HM1-6518/883

HM1-6518B

HM1-6518B/883

HM1-6551

HM1-6551/883

HM1-6551B

HM1-6551B/883

HM1-6561

HM1-6561/883

HM1-6561B

HM1-6561 B/883

4K CMOS STATIC RAMs
HM1-6504

8102405VA

HM 1-6504/883

HM1-6504B

8102403VA

HM 1-6504B/883

8102406VA

HM1-6514/883

8102404VA

HM1-6514B/883

HM1-6504S

M38510/24501 BVA

HM1-6504S/883

HM1-6514
HM1-6514B
HM1-6514S

M38510/24502BVA

HM1-6514S/883

16K CMOS SYNCHRONOUS STATIC RAMs
HM1-6516

M38510/29102BJA

HM4-6516

M38510/29102BXA

HM1-6516/883
HM4-6516/883

HM1-6516B

8403607JA

HM1-6516B/883

HM4-6516B

8403607ZA

HM4-6516B/883

16K CMOS ASYNCHRONOUS STATIC RAMs
HM1-65162

M38510/29104BJA

HM1-65162/883

HM4-65162

M38510/29104BXA

HM4-65162/883

HM1-65162B

M38510/29110BJA

HM 1-65162B/883

HM4-65162B

M38510/29110BXA

HM4-65162B/883

HM1-65162C

8403603JA

HM1-65162C/883

HM4-65162C

8403603ZA

HM4-65162C/883

HM1-65262

M38510/29103BRA

HM4-65262

M38510/29103BYA

H M4-65262/883

HM1-65262B

M38510/29109BRA

HM1-65262B/883

HM4-65262B

M38510/29109BYA

HM4-65262B/883

HM1-65262/883

2-5

. - - - - - Harris/883/JAN/DESC Part Number Listing --------,
HARRIS PART #

JAN PART #

SMD/DESC PART #

/883 PART #

CMOS MEMORY PRODUCTS (CONTINUED)
64K CMOS STATIC RAMs
HM1-65642

HM1-65642/883

HM4-65642

HM4-65642/883

HM1-65642B

M38510/29205BXA

HM1-65642B/883

HM4-65642B

M38510/29205BYA

HM4-65642B/883

HM1-65642C

HM1-65642C/883

HM4-65642C

HM4-65642C/883

CMOS FUSE LINK PROMs
HM1-6617

HM1-6617/883

HM4-6617

HM4-6617/883

HM6-6617

HM6-6617/883

HM1-6617B

HM1-6617B/883

HM4-6617B

HM4-6617B/883

HM6-6617B

HM6-6617B/883

HM1-6642

HM1-6642/883

HM4-6642

HM4-6642/883

HM6-6642

HM6-6642/883

HM1-6642B

HM1-6642B/883

HM4-6642B

HM4-6642/883

HM6-6642B

H M6-6642B/883

CMOS STATIC RAM MODULES
HM5-6564
HM5-8808
HM5-8808B
HM5-8808S

Harris CMOS Static RAM Modules are available for military and high reliability
applications processed to our high-rei DASH 8 program flow. This includes
burn-in and value added processing (temperature cycling, SEM Inspection, etc.)
Please contact your local Harris sales office or representative for details.

HM5-8808A
HMS-8808AB
HMS-8808AS
HMS-8816H
HMS-8832
HMS-8832B
HMS-92S60
HM5-92S70

2-6

Military Product Program Controls
883
-8

REFERENCE

Product
Assurance Plan

1.2.1.B.21

Facility
Certification

1.2.1.B.28

RADC/DESC

HarrisQC

HarrisQC

Harris QC

Product
Certification

1.2.1.B.26

RADC/DESC

RADC/DESC

HarrisQA

Not Required

Detail
Specifications

1.2.1.A

Slash Sheet

DESCDWG/
SMD

Harris/883
Data Sheet

Harris Catalog

a:

Qualifying
Activity

1.2.1.B.1

RADC/DESC

Harris

Harris

Harris

0
0

Qualification
TestGPC

1.2.1.B.17

Required

Per Governing
Military Spec

Per Governing
Military Spec

Per
Harris Spec

::2E
W
l-

Qualification
TestGPD

1.2.1.B.17

Required

Per Governing
Military Spec

Per Governing
Military Spec

Per
Harris Spec

>-

QPLListing

MILM38510

None

None

None

t/)

..J

0

IZ

t/)
t/)

JAN

DESC/SMD

Per Appendix A of MIL M38510

Per Harris R&QA
Manual

Change
Controls

1.2.1.B.25

MILM38510
para 3.4.2

DoD 480

DoD 480

Harris Internal
ECN Controls

Change
Notification

1.2.1.B.25

DESC

DESC

Data Sheet
Registration

Catalog

Traceability

1.2.1.B.27

Wafer Lot

6 Week Seal

6 Week Seal

6 Week Seal

Deviations to
883

1.2.1

Per
Slash Sheet

PerDESC
DWG/SMD

None

Per
Harris Spec

Product
Construction

1.2.1.B.2-12

Compliant

Compliant

Compliant

MayBe
Non-Compliant

Fab

USA Only

US~

USA

USA

0

Assembly

USA Only

USA/Malaysia

USA/Malaysia

Malaysia

-'"
a::S

==~
=0
:sa:
a..
-CI

'Programs Served By Harris
Tube-Launched, Optically Tracked, Wire-Guided Missile

Field Support Tracked Vehicle

Angle Rate Bombing Set

Integrated Solar Sensor Assembly

Advanced Medium Range Air-To-Air Missile

Continuous Motion Gyro for ISSA

Advanced Capability (MK-48 Torpedo)

Advanced Warning and Control System

Position Location and Reporting System

Forward Looking Infrared

Joint Tactical Information Distribution System

Ring Laser Gyro Programs

Target Acquisition System (MK-23)

Tail Warning System

Miniature Vehicle Sensors

Space Telescope

Driver's Thermal Viewer

Mariner Series

Detecting and Ranging Set

MK 46 NEARTIP

Fighting Vehicle System (Bradley)

AV8B HARRIER

Helicopter (or Hughes) Night Vision System

F14/A6E SMS

Advanced Optic Adjunct

Bearclaw

Advanced Ught Weight Torpedo

CAINS II

Ground Launched Cruise Missile'

TAI/MK6

Air Launched Cruise Missile

B1

Medium Range Air-To-Surface Missile

F-16

Modular Universal Laser Equipment

Phalanx

Low Altitude Navigation and Targeting Infrared

Stinger

Anti-Submarine Warfare

Locust

Multiple Launch Rocket System

Sidearm

Advanced Self-Protection Jammer

Rattler

Global Positioning System

Pavetack

Distant Early Warning

Viking

High Speed Anti-Radar Missile

Skylab

Rolling Airframe Missile

Shuttle

Medium Depth Mine.

Intelsat

Terminal Guidance Small Missile

Spacelab

Time Division Multiple Access

Voyager

DistriJ;>uted Time Division Multiple Access

Mark 50

Long Range Search and Track

Captor

Glide Bomb Unit

Maverick

Divisional Air Defense

Phoenix

2-8

PAGE
LOW VOLTAGE DATA RETENTION ................................................... .

3-2

INDUSTRY CMOS RAM CROSS REFERENCE .......................................... .

3-3

1K CMOS RAM DATA SHEETS
HM-6508/883
1 K x 1 Synchronous RAM ........................................ .
1 K x 1 Synchronous RAM ........................................ .
HM-6518/883
HM-6551/883
256 x 4 Synchronous RAM ....................................... .
256 x 4 Synchronous RAM ....................................... .
HM-6561/883

3-4
3-16
3-28
3-40

4K CMOS RAM DATA SHEETS
HM-6504/883
4K x 1 Synchronous RAM ........................................ .
1 K x 4 Synchronous RAM ........................................ .
HM-6514/883

3-52
3-67

16K CMOS RAM DATA SHEETS
HM-6516/883
2K x 8 Synchronous RAM. '....................................... .
HM-65162/883
2K x 8 Asynchronous RAM ....................................... .
HM-65262/883
16K x 1 Asynchronous RAM ...................................... .

3-82
3-91
3-104

64K CMOS RAM DATA SHEETS
HM-65642/883
8K x 8 Asynchronous RAM ....................................... .

3-115

HM-65642C/883

>-

8K x 8 Asynchronous RAM ....................................... .

3-129

CMOS RAM MODULE DATA SHEETS
HM-6564
64K Synchronous RAM Module ................................... .

3-140

HM-8808/08A
HM-8816H
HM-8832
HM-92560
HM-92570
HM-91M2

8K x 8 Asynchronous RAM Modules ........."...................... .
16K x 8 Asynchronous RAM Module ............................... .
32K x 8 Asynchronous RAM Module .............................. .
256K Synchronous RAM Module ................................. .
256K Buffered Synchronous RAM Module ......................... .
1 M Bit Asynchronous RAM Module ............................... .

CMOS PROM DATA SHEETS
HM-6642/883
512 x 8 Fuse Link PROM ......................................... .
HM-6617/883
2K x 8 Fuse Link PROM ......................................... .

3-1

3-146
3-159
3-165
3-172
3-178
3-184
3-194
3-206

",0:
00

====
==

<.)w

Low

VoltageDataRe~ention""

HARRIS CMOS RA,.,s are designed with battery baCk~p in mind. Data retention voltage and supply curr~nt are
guaranteed over temperature. The "f~lIowing nIles insure data retenl:ltiol'): " "
. "
1. Chip Enable

IE) must be h:eldhi9h during data"rete~tidn; wit"hin VCC to vcc+o.av'

2. On RAMs which have selects or output enables (e.g. 8,G), one of the selects or output"enables should be
held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation .
•0

a.

All other inputs should be held either high (at CMOS VCC) or at ground to minimize ICCDR.

.4. Inputs which are to be held high (e.g. E) must be kept between VCC
power up and power down transitions.

+o.av and 70% of VCC during the

5. The RAM can begin operation one TEHEL (for synchronous RAMs) and> 5ns (for' asynchronous RAMs)
after VCC reaches the minimum operating voltage (4.5 volts).

DATA RETENTION TIMING
vcc

1------

-----_.1

DATA RETENTION MODE

vcc~

2.0V

i
VCC TO VCC

3-2

+ O.3V

-------I

Industry CMOS RAM Cross Reference

HARRIS CMOS RAMs

, FUJt-",
DESCRIPTION

HARRIS

AMD

EDI

ITSU '

HITACHI

IPT

MITSUBISHI

'MOT~

OR,aLA

NATIONAL

NEe

OKI

,,~

NMOS,
OTHER

6508
1821

5508

2125,4015

1822
5101

1>101

2101

"IARRISI
RCA

SMOS

lKCMOSRAMs
lkxl,16Pin
Synchronous

HM-6508

lKx 1, 18Pln
Synchronous

HM-6518

256 x 4, 22 Pin
Synchronous

HM-6551

256 x 4, 18 Pin
Synchronous

HM-6561

8401

6508

6508
74C929

6518

6518
74C930

443

6551
74C920

2111

4KCMOSRAMs
4Kx 1, 18Pin
Synchronous

HM-6504

1Kx4,18Pln
Synchronous

HM-6514

921.44

8404

4315
6147

911.14

8414 '

4334
6148

91t..24

58981

6504

6504

6514

6514

5104

6504

5504

2141,2147
3150,4104
4404

~4

5114
5115

5114

6514

5514

2114,2148
2149,4045
314A

446

5128

6116

2016

5611

4802,2116
2016,4016

16KCMOSRAMs

c.>
I
c.>

2Kx8,24Pln
Synchronous

HM-6516

2Kx8,24Pin
Asynchronous

HM-65162

8416

6116

' 6118

16Kx 1, 20Pln
Asynchronous

HM-65262

8181

6167

6167

8464

6264

7164
1Ma64
8M884

6516
5117

65118

6116

2267
2367

2167,8167
1400

64K CMOS RAMs
8Kx8,28Pin
Asynchronous

HM-65642
HM-880BA*
HM-8808*

99C88

8808A
8808

5164

8164

6164

4464

6264

2064
2264

5564
5565

128K CMOS RAM MODULE
16Kx8,28Pin
Asynchronous

HM-8816H

8816H

256K CMOS RAM MODULE
32Kx8/16Kx 16
48 Pin Module
Asynchronous

HM-92560
HM-92570

,

i

32Kx8
28 Pin Module
Asynchronous

HM-8832

8832
I

1M CMOS MODULE
128x8/64Kx16

HM-91M2

*r.MOH. RAM Mnrtlll~

CMOS
MEMORY

I

.fI)HARRIS

HM-6508/883
1024 x 1 CMOS RAM

June 1989

Features

Pinout

• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.

HM1-6508/883 (CERAMIC DIP)
TOP VIEW

• Low Power Standby ••• , •••••••••••••••••••••••••••••• , •• 50llW Max.

E

• Low Power Operation •••••.••••••••••••••••••••••• 20mW/MHz Max.

VCC

AO

D

A1

W

A2

A9

• High Output Drive,- 2 TTL Loads

A3

A8

• On-Chip Address Register

A4

A7

Q

A6

GND

A5

• FastAccessTime ••••••••• '•••••••••••••••••••••••••••••• 180nsMax.
• Data Retention •••••••••• : •••••••••• .'••••••••••••••••••••• 2.OV Min.
• TTL Compatible Input/Output

'Description
The HM-6508/883 is a 1024 x 1 static CMOS RAM fabricated using selfaligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.
.

PIN

On chip latches are provided for address allowing efficient interfacing with
microprocessor systems. The 'data output buffers can be forced to a high
impedance state for use in expanded memory arrays.

A

-E

. The HM-6508/883 is a fully static RAM and may be maintained in any state for
an indefinite period of time. Data retention supply voltage and supply current
are guaranteed over temperature.

DESCRIPTION
Address Input
Chip Enable

Vi

Write Enable

0

Data Input

Q

Data Output

Functional Diagram
A5
A6
A7
AS
A9

D

32.32
MATRIX

0 - - - - - - 1 ~-.......:._+-fGi~22t1MN"'1

Q

ALL LINES POSITIVE

LOGI~'

ACTIVE HIGH

THREE STATE BUFFERS:
A HIGH OUTPUT ACTIVE

AO

A1. A2

Copyright © Harris Corporation 1989

3-4

A3

A4

ADDRESS LATCHES AND GATED DECODERS: ,
LATCH ON FALLING EDGE OFE
GATE ON FALLING EDGE OF E

Specifications HM-6508B/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••••••••••••••••••••••••••••••• +7.0V
Input or Output Voltage Applied •••••••• GND-0.3V to VCC+0.3V
Storage Temperature Range ••••••••••••••••• -650C to +1500C
Junction Temperature ••••.••••••••••••••••••••••••••• +1750C
Lead Temperature (Soldering 10 sec) ••••••••••••••••••• +3000C
Typical Derating Factor ••••••••••• 1.5mNMHz Increase in ICCOP
ESD Classification •••••••.•••••••••••••.•••••••••••••• Class 1

Thermal Resistance
Oja
0jc
Ceramic DIP Package... ••••••••••.• ••• •. 750 C/W 150C/W
Maximum Package Power Dissipation at +1250C
Ceramic DIP Package ••••••••••••••••••••••••.•••• 0.67 Walt
Gate Count •.•••••••••.••••••••.••.•••••.••••••.. 1925 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operaUon
of the device at these or any other conditions above Ihose indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ••.••••••••••• : ••••.••• +4.5V to +5.5V
Operating Temperature Range ••.••••.••••••• -550C to +1250C
Input Low Voltage .•.•••••••••••.••••.•••. .-.••••.•• OV to +O.BV

Input High Voltage ••••••••••.••••••.•••..••• VCC-2.0V to VCC
Input Rise and Fall Time ••••...•..•.•......••.....•• 40ns Max.

TABLE 1. HM-650BB/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC=4.5V
IOL=3.2mA

1,2,3

-550C~TA~+1250C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
IOH=-0.4mA

1,2,3

-55°C ~TA:S +1250 C

2.4

-

V

VCC= 5.5V,
VI=GNDorVCC

1,2,3

-550C~TA~+1250C

-1.0

+1.0

~A

VCC = 5.5 V,
VO = GND orVCC

1,2,3

-55°C :S TA :S + 125°C

-1.0

+1.0

~

Input Leakage Current
Output Leakage
Current

II
10Z

Data Retention Supply
Current

ICCDR

VCC = 2.0V, E = VCC
10=OmA,
VI=VCCorGND

1,2,3

-550C~TA~+1250C

-

5

~A

Operating Supply
Current

ICCOP

VCC = 5.sv. (Note 3)
E= lMHz,IO=OmA

1,2,3

-550C :STA~ +1250 C

-

4

mA

Standby Supply
Current

ICCSB

VCC= 5.0V,
10 = OmA
VI = VCC or GND

1,2,3

-550C ~TA~ +125 0C

-

10

~

NOTES:

...

en a:

00

1. All voltages referenced to device GND.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: IOL =
3.2mA. IOH = -O.4mA, CL = 50pF (min) - for CL greater than 50pF, access time Is derated by 0.15ns per pF.
3. Typical derating 1.SmAlMHz Increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process paramelers and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-5

====
==

UW

Specifications HM-65088/883
TABLE 2. HM-6508B/883' A.C: ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS

SYMBOL

(NOTES 1,2)
CONDITIONS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Chip Enable Access
Time

(l)TELQV

vee = 4.5 and 5.5V

9,10,11

-550e~TA$.+1250e

-

180

ns

Address Access Time

(2)TAVQV

vee = 4.~ and 5.5V

9,10,11

-550e~TA~+1250e

-

180

ns

PARAMETER

Note 5
Chip Enable Output
Enable Time

(3)TELQX

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

5

-

ns

Write Enable Output
Disable Time

(4)TWLQZ

vee = 4.5 and 5.5V

9,10,11

-550e$.TA~+1250e

-

120

ns

Chip Enable Output
Disable Time

(5)TEHQZ

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

-

120

ns

Chip Enable Pulse
Negative Width

(6)TELEH

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

180

-

ns

Chip Enable Pulse
Positive Width

(7)TEHEL

vee = 4.5 and 5.5V

9,10,11

-550e:$.TA~+1250e

100

-

ns

Address Setup Time

(8)TAVEL

9,10,11

-550e~TA~+1250e

0

-

ns

Address Hold Time

(9)TELAX

9,10,11

-550e~TA~+1250e

40

-

ns

9,10,11

-550e~TA~+1250e

80

9,10,11

-550e~TA~+1250e

0

9;10,11

-550e$.TA~+1250e

100

-

Data Setup Time

(10)TDVWH

Data Hold Time

(ll)TWHDX

Chip Enable Write
Pulse Setup Time

(12)TWLEH

vee = 4.5 and 5.5V
vee = 4.5 and 5.5V
vee = 4.5 and 5.5V
vee = 4.5 and 5.5V
vee = 4.5 and 5.5V

Chip Enable Write
Pulse Hold Time

(13)TELWH

vee = 4.5 and 5.5V

9,10,11

-550 e ~ TA ~ +125 0e

100.

-

ns

.Write Enable Pulse
Width

(14)TWLWH

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

100

-

ns

(15)TELEL

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

280

-

ns.

Read or Write
Cycle Time
NOTES:

ns
ns
ns

1. All voltage. referenced to device GND.
2. Input pulse levels: O.8V to VCC-2.oVj Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
eqUivalent, CL

= 50pF (min) -

for CL greater than 50pF. access time Is derated by 0.15n8 per pF.

3. Typical derating 1.5mNMHzlncrea.e in ICCOP.
4. The parameters listed In Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

5. TAVQV - TELQV

+ TAVEL.

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.

3-6

Specifications HM-65088/883
TABLE 3. HM-650BB/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITIONS

NOTE

TEMPERATURE

MIN

MAX

UNITS

Input CapaCitance

CI

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

6

pF

Output Capacitance

CO

VCC=Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+25 0 C

-

10

pF

NOTES:

1. All voltage. referenced to device GND.
2. Input pulse levels: O.BV to VCC-2.QV; Input rise and fall times: Sns (max); Input and Qulput timing reference leval: 1.5V; Output load: 1 TIL gate
equivalent, CL = SOpF (min) -lor CL greater than SOpF, access time Is deraled by O.ISns per pF.
3. Typical derating SmAIMHz increase In ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100'lbl5004

-

Interim Test

100'1&/5004

1,7,9

PDA

100'1&/5004

-1

RnalTest

100'lb/5004

2,3,8A,8B,10,11

Group A

Samples/5005

1,2,3, 7, 8A, 8B, 9, 10, 11

GroupsC&D

Samples/5005

1,7,9

CAUTION: These davfce. are sensKlva 10 alactronlc discharge. Proper tC handling procedures should be followad.

3-7

Specifications HM-6508/883·
Absolute.ll!laxi.mum Ratln~s

Reliability Informatl.on

Supply Voltage ••.••. : •.•••••.••••••••••.•.•••••••••••• +7.0V
Input or Output Voltage Applied ••••.••• GND~0.3V to VCC+0.3V
Storage Temperature Range ...•••••.•••• c.. :. -650C to +1500C
Junction Temperature ••••••.••..• " ••••.•.•••••.•• , •. +1750 C
Lead Temperature (Soldering 10 sec) ••.•••••.•.•.•••..• +3000C
Typical Derating Factor •..•.•••••• 1.5mNMHz Increase in ICCOP
ESD Classification •.•••.••.•••••••.•.•.•.••••••••••••. Class 1

Thermal Resistance
eja
ejc
Ceramic DIP Package. . • • • . • . . • . • . . • . • • •• 750 C/W 150C/W
0
Maximum Package Power Dissipation at +125 C
Ceramic DIP Package ••••.•••.•.••.•..•.••.••••... 0.67 Wall
Gate Count •.••••••.......•.•.••.••••.••...•....• 1925 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other. conditions abOve those indicated in the operational sections of this specification is:not implied.

Operating Conditions
Operating Voltage Range ........................ +4.5V to +5.5V
Operating Temperature Range ••...••.•••••.• -550C to +1250 C
Input Low Voltage ••.••..••••••••.•••.•••••.•.•.•.• OV to +0.8V

Input High Voltage .......................... VCC-2.0V to VCC
Input Rise and Fall Time .•.....•....•.•..•.....•..•. 40ns Max.

. TABLE 1: HM-6508/883. D.C. ELECTRICAL PERFORMA~CE CHARACTE·RI~mCS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC=4.5V
IOL=3.2mA

1,2,3

-55°C :S TA :S + 125°C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
. IOH = -O.4mA

1,2,3

-55°C :S TA:S + 125°C

2.4

-

V

Input Leakage Current
Output Leakage
Current

II

VCC=5.5V,
VI=GNDorVCC

1,2,3

-550C:S TA:S +125 0C.

-1.0

+1.0

f1A

IOZ

VCC = 5,5 V,
VO = GND orVCC

1,2,3

-55°C :S TA :S + 125°C

-1.0

+1.0

f1A

VCC = 2.0V, E= VCC
IO=Oml\,
VI = VCC or GND ..

1,2,3

~550C:S TA:S +1250 C

-

10

~A

Data Retention Supply
Current

icc DR

Operating Supply
Current

ICCOP

VCC = 5.5V, (Note 3)· .
E=IMHz,IO=OmA

1,2,·3

-550C :S.TA:S +1250 C

-

4

rnA

Standby Supply
Current

ICCSB

VCC=5.5V,
IO=OmA
VI = VCC or GND

1,2,3

-55°C :S TA :S + 125°C

-

10

~A

NOTES:

...

1. All voltages referenced to device GNO.
2. Input pulse levels: a.BV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.SV; Output load: IOl =
3.2mA, IOH = -0.4mA, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. Typical derating 1.5mA/MHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters and are not direcllytested. These parameters are characterized
upon initial design and after major process andlor design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.

3-8

Specifications HM-6508/883
TABLE 2. HM-6S08/883 A,C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device' Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.SV

9,10,11

-550C~TA~+1250C

-

250

ns

Chip Enable Access
Time

(l)TELOV

VCC

Address Access Time

(2)TAVOV

vee 4.5 and S.SV
Note 5

=

9,10,11

-550e~TA ~ +12So e

-

250

ns

Chip Enable Output
Enable Time

(3)TELOX

vee

=4.5 and 5.SV

9,10,11

-55°C ~TA~ +1250 e

5

-

ns

Write Enable Output
Disable TIme

(4)TWLOZ

vee

=4.5 and 5.SV

9,10,11

-550e~TA~+1250e

-

160

ns

Chip Enable Output
Disable TIme

(5)TEHOZ

vee-= 4.5 and 5.SV

9,10,11

-550e~TA~+1250C

-

160

ns

Chip Enable Pulse
Negative Width

(6)TELEH

vce

=4.5 and 5.SV

9,10,11

-550C ~TA~ +1250 e

250

-

ns

Chip Enable Pulse
Positive Width

(7)TEHEL

vee

=4.5 and 5.SV

9,10,11

-55°C ,STA's +1250 e

100

-

ns

Address Setup Time

(8)TAVEL

vee

9,10,11

-55°C ~TA::5. +1250 e

0

-

ns

Address Hold Time

(9)TELAX

vee

9,10,11

-550 eoSTA's +1250 e

SO

-

ns

9,10,11

-550 e,STA,S+1250e

110

-

ns

9,10,11

-55°C oS TA's +125 0e

0

9,10,11

-55°C ,STA's +12Soe

Data Setup Time

(10)TDVWH

Data Hold Time

(ll)TWHDX

Chip Enable Write
Pulse Setup TIme

(12)TWLEH

=4.5 and 5.SV
=4.5 and 5.SV
vee =4.5 and 5.SV
vee =4.5 and 5.5V
vee =4.5 and 5.SV

Chip Enable Write
Pulse Hold Time

(13)TELWH

vee

=4.5 and 5.SV

9,10,11

Write Enable Pulse
Width

(14)TWLWH

vee

=4.5 and 5.SV

(15)TELEL

vee

=4.5 and 5.SV

Read or Write
Cycle Time
NOTES:

ns

130

-

-550e oS TA's +1250 e

130.

-

ns

9,10,11

-550e,STA's +1250 e

130

-

ns

9,10,11

-5S0eoSTA's +12So e

350

-

ns

ns

1. All voltages referenced to device GND.
2. Input pulse levels: O.BV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

3. Typical derating 1.SmNMHz increase in

Iceop.

4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.
5. TAVQV

= TELQV + TAVEL.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-9

Specifications HM-6508/883
TABLE 3. HM-6508/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

MAX

UNITS

CI

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

.6

pF

CO

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

.10

pF

Input Capacitance

Output Capacitance

NOTES:

..

CONDITIONS

NOTE

TEMPERATURE

MIN

1. All voltages referenced to device GNO.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15n5 per pF.
3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

FinalTest

100%/5004

2,3,8A,8B,10,11

Group A

Samples/5005

1,2,3,7, SA, SB, 9,10,11

GroupsC&D

Samples/5005

1,7,9

CAUTION: These devices are sensitive to electroniC discharge. Proper

Ie handling procedures should be followed.
3-10 .

HM-6508/883
Timing Waveforms
READ CYCLE

(6) TAVEL_
A

~ELA~-1(9)
VALID )IQ'

(6lrAVEL--l

~

f:::-

NEXT

(15)

TElEL

(7)

(7)

TEHEL_

THEH

r---TEHEl

(6)

I'---

---../
HIGH

!---TELOV_ (1)
(3)
TELQX

_TEHOt-(S)

r--

.h

'I

-

TEHQZ

(5)

VALID OUTPUT

_TAvav _ _
(3)

t t

TIME

AEFERENCE

4

•

TRUTH TABLE
TIME
REFERENCE

INPUTS
A

E

Vi

-1

H

0

"""'L

X
H
H
H
H
X
H

1
2

L
L

4

....r
H

5

"""'L

3

X

V
X
X
X
X

V

OUTPUTS
D

Q

FUNCTION

X
X
X
X
X
X
X

Z
Z
X

Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

V
V
Z
Z

In the HM-6508/883 Read Cycle, the address information
is latched into the on chip registers on the falling edge of
E (T = 0). Minimum address setup and hold time requirements must be met After the required hold time, the
addresses may change state without affecting device
operation. During time (T = 1) the data output becomes

enabled; however, the data is not valid until during time
(T = 2). W must remain high for the read cycle. After the
output data has been read, E may return high (T = 3). This

will disable the chip and force the output buffer to a high
impedance state. After the required E high time (TEHEL) the
RAM is ready for the next memory cycle (T = 4).

3-11

>",ee

00

====
==

UW

HM-6508/883
Timing Waveforms

(Continued)
(8)

(9)

TAVEL

WRITE CYCLE

,J

(7)
--TEHEL------

. - ---."- TELEH --

(6)
---TWLEH------

""k""""I---~(1~.TWLWH----lrT7.,-r:;.,""':-...-""':--.::-,

"7"T">"7"7""":l,...,..""......

W~~~~~~====~~~~

HIGH

TIME
REFERENCE

(10)

Z

f ,

-,

2

3

TRUTH TABLE
TIME
REFERENCE
-1
0
1
2

Vi

H

X
X

""L"
L
L

4

-H'

5

""L

3

OUTPUTS

INPUTS
A

E

""L

-H'
X
X

X
V
X
X
X
X
V

D

Q

X
X
X
V
X
X
X

Z
Z
Z
Z
Z
Z
Z

The write cycle is initiated by the falling edge of E which
latches the address information into the on chip registers.
The write portion of the cycle is defined as both E and W
being low simultaneously. W may go low anytime during the
cycle provided that the write enable pulse setup time
(TWLEH) is met. The write portion of the cycle is terminated
by the first rising edge of either E or W. Data setup and hold
times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed,
the W line may remain low until all desired locations have
been written. When this method is used, data setup and
hold times must be referenced to the rising edge of E. By
positioning the W pulse at different times within the E low

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
. Write Period Begins
Data is Written
Write Completed
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

time (TELEH), various types of write cycles may be
performed.
If the E low time (TELEH) is greater than the W pulse
(TWLWH) plus an output enable time (TELOX), a combination read write cycle is executed. Data may be modified an
indefinite number of times during any write cycle (TELEH).
The data input and data output pins may be tied together for
use with a common I/O data bus structure. When using the
RAM in this method allow a minimum of one output disable
time (TWLOZ) after W goes low before applying input data
to the bus. This will insure that the output buffers are not
active.

Test Load Circuit
r------------l

I
I
I

I
I
I
I
I
I

OUT"o--+-+-<

I
I
"'TEST HEAD
CAPACITANCE"
INCLUDES STRAY
AND JIG CAPACITANCE

I
EQUIVALENT CIRCUIT

I

,-------------

3-12

HM-6508/883

Burn-In Circuit
HM-6508/883 CERAMIC DIP

vee
FO --'lJVIr---I
F2

F3 --"<""'.---1

!--'lI\I'Ir--

F4

1--"<""'.--- F 1

--'1,..,.Ir-_

1---'\.fV\_- F 12

FS --"<""'--I
F 6--"<""'.---1

1--"<""'.--- F 11

F7 --"<""'..---1

!--'lI\I'II--

F 2 --'11\1'11-_

1--....I\fV\_- Fg

F 10

!--,\fV\,---FS

>-

"'c::
00

......::e
::e::e

NOTES:

All Resistors 47kll ± 5%

Fo = 'OOkHz ± '0%
F,= FO + 2. F2 = F, + 2. F3 = F2 + 2 ••• F'2 = F" + 2
vee = 5.5V ± 0.5V
VIH = 4.5V ± '0%
VIL = -0.2V to +0.4V
e, = 0.01 ~F Min.

3-13

HM-6508/883

Die Characteristics
DIE DIMENSIONS:
130 x 150 x 19 ± 1 mils
METALLIZATION:
Type: SI-AI
Thickness: 11 k.8. ± 2k.8.
GLASSIVATION:
Type: Si02
Thickness: ak.8. ± 1 k.8.
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
WORST CASE CURRENT DENSITY:
1.342 x 105 Ncm 2
LEAD TEMPERATURE (10 seconds soldering):
~3000C

Metallization Mask Layout
HM-6508/883

Q

GND

AS

NOTE: Pin Numbers Correspond to DIP Package Only.

3-14

HM-6508/883
Packaging t
16 PIN CERAMIC DIP

.005 MIN

~

.753
.785

t:==========::::::j
o·
15'
.100
BSC
• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER ANISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic. 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
Method: Furnace Seal

NOTE: AD Dimenslona are

~:.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-2

t MU-M-38510 Complianl MaI.rials, Finis",,". and Dimensions.

,Dimensions are In Inc",,".

3-15

m

HARRIS.

HM-6518/883
1024

June 1989

X

1 CMOS RAM

Pinout

Features
• This Circuit is Processed in Accordance to Mil-Std-S83 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.
• Low Power Standby ••••••••••••••••••••••••••••••••••••• 50flWMax.

HM1-6S18/883 (CERAMIC DIP)
TOP VIEW
81

VCC

• Low Power Operation ••••••••••••••••••••••••••••• 20J1lW/MHz Max.
• Fast Access Time ••••.••••••••••••••••••••••••.••••.•••• 180ns Max.

E

S2

• Data Retention •••••••••••••••••• ~ •••••••••••••••••••••• @ 2.0V Min.

AO

D

• TTL Compatible Input/Output

Al

W

A2

A9

A3

AS

A4

A7

Q

A6

GND

AS

• High Output Drive - 2 TTL Loads
• High Noise Immunity
• On-Chip Address Register
• Two-Chip Selects for Easy Array Expansion
• Three-State Output

Description
The HM-6518/883 is a 1024 x 1 static CMOS RAM fabricated using selfaligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.

PIN

On chip latches are provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output buffers can be
forced to a high impedance state for use in expanded memory arrays.

W

The HM-6518/883 is a fully static RAM and may be maintained in any state for
an indefinite period of time. Data retention supply voltage and supply current
are guaranteed over temperature.

DESCRIPTION
Address Input
Chip Enable
Write Enable
Chip Select
Data Input
Data Output

A

E
S
0

Q

Functional Diagram
A5
AS

32x32
MATRIX

A7
A8
A9

Q

ALL UNES POSITIVE LOGIC· ACTIVE HIGH
THREE STATE BUFFERS:
A HIGH _
OUTPUT ACTIVE

w

AO

At

A2

Copyright © Harris Corporation 1989

3-16

A3

A4

DATA LATCHES:
LHIGH Q= D
Q LATCHES ON RISING EDGE OF L
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FAWNG EDGE OFE
GATE ON FAWNG EDGE OFE

Specifications HM-6518/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••..••.•••••••••••••••.••••••••.••• +7.0V
Input or Output Voltage Applied ...••••• GND-0.3V to VCC+0.3V
Storage Temperature Range •..••.••••.•..•.• -650C to +150 0 C
Junction Temperature ...• , •.••••...•••••.....••••.•.• +175 0C
Lead Temperature (Soldering 10 sec) .••.••.•.••.•.••••. +300 0C
ESD Classification ...•.•••...••.•.••••.•.•.••••.•.•.•• Class 1

Thermal Resistance
0ja
0jc
Ceramic DIP Package. . . . . • . • . • . • • • . . . . .• 75 0 C/W 180C/W
0
Maximum Package Power Dissipation at +125 C
Ceramic DIP Package ...•..•••••••.......••....••. 0.67 Watt
Gate Count ..••.....••.••••.•••.•••.••••.•.•.•..• 1936 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ••.••.•.••••.••.••.•••• +4.5V to +5.5V
Operating Temperature Range .•..••••••..•.• -550C to +1250 C
Input Low Voltage ................................. OV to +O.8V

Input High Voltage •..•.•..•••...•.•.•.•.•..• VCC-2.0V to VCC
Input Rise and Fall Time ••.•.•.•.•...•.•.••.•.•.•••. 40ns Max.

TABLE 1. HM-6518/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC=4.5V
IOL=3.2mA

1,2,3

-550C~TA=::+1250C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
10H=-0.4mA

1,2,3

-550C~TA~+1250C

2.4

-

V

"

VCe=5.5V,
VI = GND orVCe

1,2,3

-550C ~TA =:: +125 0 C

-1.0

+1.0

~A

10Z.

VCC = 5.5 V,
VO = GND orVCC

1,2,3

-550C ~ TA~ +125 0 C

-1.0

+1.0

~A

vce = 2.0V, E = vec
10 = OmA,
VI=VCCorGND

1,2,3

-550C.s:TA.s:+1250e

-

10

~A

VCC = 5.5V, (Note 3)

1,2,3

-550C.s:TA~+1250C

-

4

mA

1,2,3

-550C~TA~+1250C

-

10

~

Input Leakage Current
Output Leakage
Current
Data Retention Supply
Current

ICCDR

Operating Supply
Current

ICCOP

Standby Supply
Current

ICCSB

>-

E= 1 MHz, 10 =OmA
VI=VCCorGND

NOTES:

VCC= 5.5V,
10=OmA
VI=VCCorGND

1. All voltages referenced to device GND.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.SV; Output load: IOL =
3.2mA,IOH = -O.4mA, CL· = 50pF (min) - for CL greater than 50pF, access time is derate~ by O.1f?ns per pF.

3. Typical derating 1.5R.'1A/MHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be foHowed.

3-17

."D:
00

:;;:;;

.., :;;....

Specifications HM-6518/883
TABLE 2. HM-6518/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranleed and 100% Tesled

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.5\1

9,10,11 '

-550C~TA~+1250C

-

250

ns

Chip Enable Access
Ti!'fle

(1)TELQV

VCC

Address Access Timit

(2)TAVQV

VCC 4.5 and 5.5\1
NoleS

=

9,10,11

-55OC~TA~+1250C

-

250

ns

Chip Select Output
Enable Time

(3)TSLQX

VCC

=4.5 and 5.5\1

9,10,11

~550C ~TA~ +125OC

5,

-

ns

Write Enable Output
Disable Time

(4)TWLQZ

vec = 4.5 and 5.5\1

9~

10, 11

-550C~TA~+125OC

-

160

ns

Chip Select Output
Disable Time

(5)TSHQZ

vee

=4.5 and 5.5\1

9,10,11

-550C~TA~+1250C

-

160

ns

Chip Enable Pulse
Negative Width

(6)TELEH

vec

=4.5 and 5.5\1

9,10,11

-550e~TA~ +1250C

250

-

ns

Chip Enable Pulse
Positive Width

(7)TEHEL

vee

=4.5 and 5.5\1

9,10,11

-550e~TA~ +1250 e

100

-

ns

Address Setup Time

(8)TAVEL

vec

=4.5 and 5.5\1

9,10,11

-550C~TA~+1250e

0

Address Hold Time

(9)TELAX

vec - 4.5 and 5.5\1

9,10,11

-550e~TA~ +1250C

50

Data Setup Time

(10)TDVWH

9,10,11

~550C~TA~ +1250C

110

Data Hold Time

(11)TWHDX

=4.5 and 5.5V
vce =4.5 and 5.5\1

9,10,11

-550e~TA~ +1250C

0

-

ns

Chip &ilect Write
Pulse Setup Time

(12)TWLSH

vec ~ 4.5 and 5.5\1

9,10,11

-550e~TA.s.+1250e

130

-

ns

Chip Enable Wrile
Pulse Setup Time

(13)TWLEH

vec

=4.5 and 5.5V

9,10,11

-550~~TA~ +1250 e

130

-

ns

Chip Select Write
Pulse Hold Time

(14)TSLWH

vee - 4.5 and 5.5\1

9,10,11

-55OC~TA~+125OC

130

-

n8

Chip Enable Write
Pulse Hold Time

(15)TElWH

vee

=4.5 and 5.5\1

9,10,11

-55OC~TA~+1250e

130

Wrile Ensble
Pulse Width

(16)TWLWH

vee

=4.5 and 5.5\1

9,10,11

-5SOC~TA~+125OC

130

ReadorWrile
Cycle Time

(17)TELEL

vec = 4.5 and 5.5\1

9,10,11

-5SOe ~TA~ +125OC

350

vce

-

'ns
ns
ns

-

ns
ns
ns

NOTES: 1. All voltages referenced to devtCa GND.
2. Input putaalavalo: D.BV to VCC-Z.DV; Input rtae and fall tlmal: 5n. (.....); Input and output liming referancalaval: 1.5V; OutpUt load: IOL-·
3.2mA, IOH - -o.4mA, CL - 50pF (mini - lot CL greater than SOpF, access tima Is daratact by 0.1Snl per pF.

3.

lYPlcaI derating 1.5mAlMHz Incraua In \CCOP.

4. Tha paramataro Iistad In Tobia 3
and/or design changaL

5. TAVQV - TELQV

CAUTION:

These davIcias are _

are controliad via design or procaoo peronl"aro are charactarlzad upon initial daslgn and _

+ TAVEL.

.... to aI_nle dlachaioe. Proper IC _dUnIl procedures.•hOuld be followed. '

3-18

major

procau

Specifications HM-6518/883
TABLE 3. HM-6518/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
SYMBOL

CONDITIONS

NOTE

TEMPERATURE

MIN

MAX

UNITS

Input Capacitance

CI

VCC = Open,
TA = +25 0 C, f = 1 MHz,
All Measurements
Referenced to
Device Ground

4

TA=+25 0 C

-

6

pF

Output Capacitance

CO

VCC = Open,
TA = +25 0 C, f = 1 MHz,
All Measurements
Referenced to
Device Ground

4

TA=+25 0 C

-

10

pF

PARAMETER

NOTES:

1. All voltages referenced to device GND.
2. Input pulse levels: C.SV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
3.2mA. IOH = -O.4mA, Cl = 50pF (min) - for Cl greater than 50pF, access lime is derated by 0.15ns per pF.

tal ==

3. Typical derating 1.5mA/MHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3,8A,8B, 10, 11

Group A

Samples/5005

1,2,3,7, 8A,8B,9, 10, 11

GroupsC&D

Samples/5005

1,7,9

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-19

Specifications HM-6578B/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••• ; ••••••••••••••••••••••••••••••••• +7.0V
Input or Output Voltage Applied •••••••• GND-o.3V to VCC+0.3V
'Storage Temperature Range ••••••••••••••••• -650C to +1500C
JunctlonTemperature •••••••••••••••••••••••••••••••• +1750 C
Lead Temperature (Soldering 10 sec) ••••••••••••.•••••• +3000 C
ESD Classification •••••••••••••••••••••••••••• , ••••••• Class 1

Thermal Resistance
Sja
Sjc
Ceramic DIP Package. • • • • • • . • • • • • • • • • • .• 750 C/W 1BoC/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ............................. 0.67 Wat!
Gate Count ...................................... 1936 Gates

CAUTION:· Stresses above lhose listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification ;s not implied.

Operating Conditions
Operating Voltage Range ....................... +4.5V to +5.5V
Operating Temperature Range ••••.•••••••••• -550C to +1250C
Input Low Voltage •••••••••••••.••••.•••••••••••••• OV to +O.BV

Input High Voltage .......................... VCC-2.0V to VCC
Input Rise and Fall Time ............................ 40ns Max.

TABLE 1. HM-651BB/BB3 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

SYMBOL

PARAMETER

(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS
V

Output Low Voltage

VOL

VCC= 4.5V
IOL=3.2mA

1,2,3

-550C!>TA~+1250C

-

0.4

Output High Voltage

VOH

VCC=4.5V
IOH=-0.4mA

1,2,3

-550C !>TA!> +1250 C

2.4

-

V

II

VCC= 5.5V,
VI = GND orVCC

1,2,3

-550C ~TA~ +1250 C

-1.0

+1.0

pA

IOZ

VCC = 5.5 V,
VO=GNDorVCC

1,2,3

-550C~TA~+1250C

-1.0

+1.0

pA

VCC = 2.0V, E = VCC
10 = OmA,
VI=VCCorGND

1,2,3

-550C~TA~+1250C

-

5

pA

VCC = 5.5V, (Note 3)
1MHz,lO =OmA
VI=VCCorGND

1,2,3

-550C:STA~

+1250 C

-

4

mA

VCC=5.sv,
10 = OmA
VI = VCC or GND

1,2,3

-550C~TA~+1250C

-

10

pA

Input Leakage Current
Output Leakage
Current
Data Retention Supply
Current

ICC DR .

Operating Supply
Current

ICCOP

Standby Supply
Current

ICCSB

NOTES:

E=

1. All voltages referenced to device GNO.
2. Input pulse levels: O.BV 10 VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: IOl
3.2mA, tOH -0.4mA, Cl 50pF (min) - for Cl greater than 50pF, access time Is derated by 0.15ns per pF.

=

=

=

3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tasted. These parameters are characterized
upon inHial deSign and after major process and/or design changes.

CAUTION: Thesa devices are sensitive to electronic discharge. Proper IC handling procedures should be followad~

.3-20

Specifications HM-65188/883
TABLE 2. HM-6518B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.S and S.SV

9,10,11

-ssoC.$ TA.$ +12So C

-

180

ns

Chip Enable Access
Time

(l)TELQV

VCC

Address Access Time

(2)TAVQV

VCC 4.S and 5.SV
NoteS

=

9,10,11

-S50 C.$ TA.$ +12So C

-

180

ns

Chip Select Output
Enable Time

(3)TSLQX

VCC

=4.S and S.SV

9,10,11

-SSOC.$ TA.$ + 12SoC

5

-

ns

Write Enable Output
Disable Time

(4)TWLQZ

VCC

=4.S and S.SV

9,10,11

-550C.$ TA.$ + 12SoC

-

120

ns

Chip Select Output
Disable Time

(S)TSHQZ

vee

=4.5 and 5.5V

9,10,11

-55 0 e.$TA.$ +1250 e

-

120

ns

Chip Enable Pulse
Negative Width

(S)TELEH

vee

=4.5 and 5.5V

9,10,11

-S5 0 e.$TA.$ +125 0 e

180

-

ns

Chip Enable Pulse
Positive Width

(7)TEHEL

vee

=4.5 and 5.SV

9,10,11

-550C .$TA.$ +12S o e

100

-

ns

Address Setup Time

(8)TAVEL

vee

9,10,11

-5So e .$ TA .$ + 12So e

0

Address Hold Time

(9)TELAX

vee

9,10,11

-550C .$ TA .$ + 1250C

40

-

9,10,11

-ssoe .$ TA .$ + 125°C

80

-

ns

9,10,11

-ssoe .$ TA.$ + 12So C

ns

9,10,11

-ssoe .$ TA.$ + 12Soe

°

-

100

-

ns

Data Setup Time

(10)TDVWH

Data Hold Time

(11)TWHDX

Chip Select Write
Pulse Setup Time

(12)TWLSH

=4.5 and 5.5V
=4.5 and 5.SV
vee =4.5 and 5.5V
vee =4.5 and S.SV
vee =4.5 and 5.5V

Chip Enable Write
Pulse Setup Time

(13)TWLEH

vee

=4.5 and S.5V

9,10,11

-550 e.$ TA.$ +1250 e

100

-

ns

Chip Select Write
Pulse Hold Time

(14)TSLWH

vee

=4.5 and S.SV

9,10,11

-5Soe .$ TA .$ + 12Soe

100

-

ns

Chip Enable Write
Pulse Hold Time

(lS)TELWH

vee

=4.5 and 5.5V

9,10,11

-S5 0 e .$ TA .$ + 1250C

100

-

ns

Write Enable
Pulse Width

(1S)TWLWH

vee

=4.5 and 5.SV

9,10,11

-550C .$TA.$ +1250 e

100

-

ns

Read or Write
Cycle Time

(17)TELEL

vee

=4.5 and 5.5V

9,10,11

-550 e .$ TA .$ + 1250C

280

-

ns

NOTES:

ns
ns

1. All voltages referenced to device GNO.

2. Input pulse levels: O.8V to VCC-2.0V; Inpul rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: IOL
3.2mA, IOH = -O.4rnA, CL = 50pF (min) - for Cl greater than 50pF. access time is derated by 0.15n5 per pF.

=

3. Typical derating 1.SmAlMHz increase in reCQP.
4. The parameters listed in Table 3 arB controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.
5. TAVQV = TELQV

+ TAVEL.

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.
3-21

Specifications HM-6578B/883
TABLE 3. HM-6518B/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITIONS

Input Capacitance

CI

Output Capacitance

CO

NOTES:

NOTE

TEMPERATURE

MIN

MAX

UNITS

VCC Open,
TA= +250C,f= 1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+2S0 C

-

6

pF

VCC = Open,
TA = +2S0 C,f = 1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+2S0 C

-

10

pF

=

1. All voltage. referenced to device GND.
2. Input pulse levels: O.8V to VCC-2.oV; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gale
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15n8 per pF.
3. Typical derating 1.SmAlMHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
andlor design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/S004

-

Interim Test

100%/S004

1,7,9

PDA

100%/S004

1

Final Test

100%/S004

2,3, BA, B8, 10, 11

Group A

Samples/SOOS

1,2.3,7. BA.B8,9,10,11

GroupsC&D

Samples/SOOS

1,7,9

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.

3-22

HM-6518/883
Timing Waveforms
READ CYCLE

191

181

TAVEL-

X

181

~TElA~.

lAVEd.

V'LlD~
TEHEl_

TELEH

161

171

=

NEXT

TELEL

t---TEHEL

A

171

1171
"-

HIGH

X
~~~~~'AU~

r----:~ELQV(8
-,"VQVI21---

HIGHZ

HIGH Z

T$Hoz'1--151

~,(j)~ 131

TSLOX

VALID OUTPUT LATCHED

l=

151

TSHOZ·~

~~

REFER:!~: -----III--+----+----+----'+-I-----fI-+I3
•
,
TRUTH TABLE
TIME
REFERENCE
-1
0
1
2

OUTPUT

INPUTS

E

51

Vi

A

D

Q

FUNCTION

H

H
X
L
L
L
H
X

X
H
H
H
H
X
H

X
V
X
X
X
X
V

X
X
X
X
X
X
X

Z
Z
X
V
V
Z
Z

Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Output Latched
Device Disabled, Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

"""'\...
L
L

3

....r

4

H

5

""L

NOTE: 1.

Device selected only if both 51 and

52 are low, and deselected if either 51 or 52 are high

In the HM-6518/883 read cycle the address information is
latched into the on chip registers on the falling edge of
E (T = 0). Minimum address setup and hold time requirements must be met. After the required hold time the
addresses may change state without affecting device operation. In order for the output to be read 51, 52 and E must

be low, W must be high. When E goes high the output data
Is latched into an on chip register. Taking either or both 51
or 52 high forces the output buffer to a high impedance
state. The output data may be re-enabled at any time by
taking 51 and 52 low. On the falling edge of E the data will
be unlatched.

3-23

>",a:
00

:::;::::;:
u'"
:::;:

HM-6518/883
Timing Waveforms

(Continued)
181

WRITE CYCLE

TAVE~

191

181

~TELA~,

TAVE~.

VALID

~EHEL

T£UL

TEUH

161

171
1151

TELWH

TWLEH

TEHEL-

.K
(131

171

~
NEXT

WI
I'-

lWLWH(161

IIDI~DvwH_
VALID DATA

. t::::.1WHDX 1111

xx::

HIGHZ

(1~11 I - - - (12ITWLSH
TSLWH

51,
ft

REFER:~~: -----+I--t--------l----+-+--t----t_
.,
mUTHTABLE
TIME
REFERENCE

-1
0
1
2
3
4
5

INPUTS

E

S1

W

A

0

H

\...

X
X

X
X

X
V

X
X

L
L

-F

L

L
L

X
X
X

X
X
X

-F
H
\...

X
X
X
X
V

OUTPUT
Q
Z
Z
Z
Z
Z
Z
Z

V
V

X
X
X

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Write Mode has Begun
Data is WriHen
Write Completed
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle BE?gins (Same as 0)

NOTE: 1. Device .elected only Wboth Si and 52 are low. and de.elected if either Si or 52 are high.

The write cycle is initiated by the falling edge of E which
latches the address information Into the on chip registers.
The write portion of the cycle is defined as E, iN, 51 and 82
being low simultaneously. iii may go low anytime du ring the
cycle provided that the write enable pulse setup time
(TWLEH) is met. The write portion of the cycle.ls terminated
by the first rising edge of either Eo W, 81 or 82. Data setup
and hold times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed,
the iN line may remain low until all desired locations have
been written. When this method Is used, data setup and
hold times must be referenced to the rising edge of E. By
positioning the iii pulse at different times within the E low

time (TELEH), various types of write cycles may be performed. If the E low time (TELEH) is greater ttlan the iN
pulse (TWLWH) plus an output enable time (T8l..QX), a combination read write cycle is executed. Data may be modified
an indefinite number of times during any write, cycle
(TELEH).
The ·data Input and data output pins may be tied together for
use with a common I/O data bus structure. When using the
RAM in this method allow a minimum of one output disable
time (TWLQZ) after iN goes low before applying input data
to the bus. This will insure that the output buffers are not
active.

Test Load Circuit

DUTo-_--r....

1.5V
"TEST HEAD
CAPACITANCE"

INCWDes STRAY
AND JIG CAPACrTANCE

EQUIVALENT CIRCUIT

3-24

HM-6518/883

Burn-In Circuit
HM1-6518/883 CERAMIC DIP
VCC Cl

E

51

FO

FO

FO
F3

AO

F2

F4

Al

Fl

Fs

A2

F12

F6

A3

F11

F7

A4

FlO

F2

a

Fg

GND

Fa

~

>",a:

00

::E::E

(.)w

::E

NOTES:
All Resistors 47kn ± 5%

= 100kHz ±

FO
F1

10%

= FO + 2. F2 = F1

+ 2. F3

= F2 + 2

• • • F12

= F11

+ 2

= S.SV ± O.SV
= 4.SV ± 10%

VCC
VIH

VIL = -0.2V to +O.4V
C1

= 0.Q1 ~F Min.

3-25

HM-6518/883
Die Characteristics
DIE DIMENSIONS:
130 x 150 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 11 kJ!. ± 2kA
GLASSIVATION:
Type: Si02
Thickness: akA ± 1kA
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
.. WORST CASE CURRENT DENSITY:
1.342 x 105 Ncm 2
LEAD TEMPERATURE (10 seconds soldering):
~3000C

Metallization Mask Layout·
HM-6518/883

AS
NOTE: Pin Numbers Correspond to DIP Package Only.

3-26

HM-6578/883
Packaging t
18 PIN CERAMIC DIP
.BB2

.005 MIN

!

~

'OOT:::: t

.915

.2B5

J05
1r=='tt
::::j1

it=========~

O'

.125
.1BO

15'
.100
BSC

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic. 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
Method: Furnace Seal

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-6

>-

",Ie

co co

::E::E
U'"
::E

NOTE: All Dimensions are

~:.

• Dimensions are In Inches.

tMU-M-38S10 Compliant Malerlal., finishes, and Dimensions.

3-27

fit HARRIS

HM-6551/883
256

June 1989

Features

X

4 CMOS RAM

Pinout

• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully'
Conformant Under the Provisions of Paragraph' 1.2.1.
'

HM1-6551/883 (CERAMIC DIP)
TOP VIEW

• Low Power Standby ...................................... 50llW Max.
• Low Power Operation ••••••••••••••••••••••••••••• 20mW/MHz.Max.
• Fast Access Time ••••••••••••••••••••••••••••••••••••••• 220n8 Max.

A3

VCC

A2

A4

A1

W

AO

S1

A5

E

• Internal Latched Chip Select

A6

S2

• High Noise Immunity

A7

Q3

• Data Retention ••••••••••••••••• '........................ @ 2.0V Min.
• TTL Compatible Input/Output
• High Output Drive- 1 TTL Load,

• On-Chip Addres's Register.
• Latched Outputs
• Three-State Output

Description

GNO

03

DO

02

QO

02

01

01

The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated using selfaligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.

PIN

On chip latches are provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output buffers can be
forced to a high impedance state for use in expanded memory arrays.

E

Chip Enable

W

Write Enable

5

Chip Select

DESCRIPTION
Address Input

A

The HM-6551/883 is a fully static RAM and may be maintained in any state for
an indefinite period of time. Data retention supply voltage and supply current
are guaranteed over temperature.

D

Data Input

Q

Data Output

Functional Diagram
ALL LINES POSITIVE LOGIC, ACTIVE HIGH
AD
Al
A5
A6
A7

GATED
ROW
DECODER

THREE STATE BUFFERS:
A HIGH _
OUTPUT ACTIVE

32x32
MATRIX

32

DATA LATCHES:
LHIGH -

0- 0

QO

DO

01

02

, - . - . . - - - Q2

03

Q3

A

w

LATCHED ADDRESS
REGISTER

SELECT LATCH:
LLOW-O=D
LATCHES ON RISING EDGE OF L

o

ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OFE
GATE ON FALLING EDGE OFE
A2

A3

Copyright © Harris Corporation 1989,

3-28

A4

Specifications HM-65518/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••••••••.•••.••••••••••••••••••••••••••• +7.0V
Input or Output Voltage Applied •••••••• GND-0.3V to VCC+0.3V
Storage Temperature Range ••••••••••••••••• -B50C to +1500 C
Junction Temperature •••••••••••••••••••••••••••••.•• +1750 C
Lead Temperature (Soldering 10 sec) ••••••••••••••••••• +300oC
ESD Classification •••••••••••••••••••••••••••••••••••• Class 1

Thermal Resistance
Dja
Djc
Ceramic DIP Package. • • • • • • ... • . • • • • • • • •• BOoC/W 150C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ••••••••••.•••••••••••••••••• 0.83 Watt
Gate Count ••••••••••••.•••.•••••••.••••••••••••• 1930 Gates

CAUTION: Stresses above those listed in ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only raling and operation
of the device at these or any other conditions above those indicated in the operational sections of 'his specification is not implied.

Operating Conditions
Operating Voltage Range ••••••••••••••••••••••• +4.5V to +5.5V
Operating Temperature Range ••••••••••••••• -550C to +1250 C
Input Low Voltage ••••••••••••••••.•••••••••••••••• OV to +O.BV

Input High Voltage •••••••••••••••••••••••.•• VCC-2.0V to VCC
Input Rise and Fall Time ••••••••••.••••••••••••••••• 40ns Max.

TABLE 1. HM-6551B/8D3 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

(NOTE 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC= 4.5V
IOL=I.BmA

1,2,3

-550C~TA~+1250C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
10H=-OAmA

1,2,3

-550 C ~TA ~ +1250 C

2.4

-

V

II

VCC=5.5V,
VI = GND orVCC

1,2,3

-550C~TA~+1250C

-1.0

+1.0

pA

10Z

VCC = 5.5 If,
VO = GND orVCC

1,2,3

-550C~TA~+1250C

-1.0

+1.0

pA

Input Leakage Current
Output Leakage
Current

SYMBOL

Data Retention Supply
Current

ICCDR

VCC = 2.0V, E= VCC
10 = OmA,
VI=VCCorGND

1,2,3

-550 C ~TA~ +12S oC

-

10

pA

Operating Supply
Current

ICCOP

VCC = 5.5V, (Note 3)
E= 1MHz, 10 =OmA
VI=VCCorGND

1,2,3

-S50 C ~TA!> +1250C

-

4

mA

Standby Supply
Current

ICCSB

VCC= 5.5V,
10=OmA
VI=VCCorGND

1,2,3

-550C~TA~+1250C

-

10

pA

NOTES:

en >a:
::;:::;:
UW
::;:

00

1. All voltages referenced to device GND.
2. Input pulse levels: O.BV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference lavel: 1.5V; Output load: IOL
1.6mA, IOH = -0.4mA, CL = 50pF (min) - for CL greater than 50pF, access time Is derated by 0.15ns per pF.

=

3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed in Table 3 arB controlled via design or process parameters and arB nol directly tested. These parameters are characterized
upon initial design and after-major process and/or design changes.

CAUTION: These devices ara sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-29

Specifications HM-65518/883
TABLE 2. HM-6551 B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.5V

9,10,11

-55°C STAS +1250 C

-

220

ns

Chip Enable Access
Time

(I)TELQV

VCC

Address Access Time

(2)TAVQV

VCC 4.5 and 5.5V
Note 5

=

9,10,11

-55°C STA!S +1250 C

-

220

ns

Chip Ssleet 1 Output
Enable Time

(3)TS1LQX

VCC

=4.5 and 5.5V

9,10,11

-550C !STAS +1250 C

5

-

ns

Write Enable Output
Disable Time

(4)TWLQZ

VCC

=4.5 and 5.5V

9,10,11

-550 CSTAS+1250C

-

130

ns

Chip Select 1 Output
Disable Time

(5)TS1HQZ

VCC

=4.5 and 5.5V

9,10,11

-550CSTAS+1250C

-

130

ns

Chip Enable Pulse
Negative Width

(6)TELEH

VCC

=4.5 and 5.5V

9,10,11

-550 CSTAS+1250C

220

-

ns

Chip Enable Pulse
Positive Width

(7)TEHEL

VCC

=4.5 and 5.5V

9,10,11

-550 C.:5 TAS+1250 C

100

-

ns

=4.5 and 5.5V
=4.5 and 5.5V

9,10,11

-55°C S TA.:5 +1250 C

0

-550 CSTAS+1250C

0

-

ns

9,10,11

=4.5 and 5.5V
=4.5 and 5.5V

9,10,11

-550 CSTAS+1250C

40

-

ns

9,10,11

-550 C!STAS+1250C

40

-

ns

100

-

ns
ns

(8)TAVEL

VCC

(9)TS2LEL

VCC

Address Hold Time

(10)TELAX

VCC

Chip Ssleet 2
Hold Time

(11)TELS2X

VCC

Data Sstup Time

(12)TDVWH

VCC

-550 CSTAS+1250C

(13)TWHDX

VCC

9,10,11

-550 CSTAS+1250 C

0

Chip Ssleet 1 Write
Pulse Setup lime

(14)TWLSIH

=4.5 and 5.5V
=4.5 and 5.5V
VCC =4.5 and 5.5V

9,10,11

Data Hold Time

9,10, II

-550 CSTAS+1250 C

120

-

Chip Enable Write
Pulse Setup lime

(15)TWLEH

VCC

=4.5 and 5.5V

9,10,11

-550 CSTAS+125 0 C

120

-

ns

Chip Ssleet I Write
. Pulse Hold Time

(16)TSILWH

VCC

=4.5 and 5.5V

9,10,11

-550C!STAS+1250C

120

-

ns

Chip Enable Write
Pulse Hold Time

(17)TELWH

VCC

=4.5 and 5.5V

9,10,11

-550 C!STAS+1250C

120

-

ns

Write Enable
Pulse Width

(18)TWLWH

VCC

=4.5 and 5.5V

9,10,11

-550 CSTAS+125 0 C

120

-

ns

Read or Wrile
Cycle Time

(19)TELEL

VCC

=4.5 and 5.5V

9,10,11

-55°C !STA S +1250 C

320

-

ns

Address Sstup Time
Chip Select 2
Setup Time

NOTES:

ns

ns

1. All voltage. referenced to device GND.
2. Input pulse levels: o.ev to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output liming reference level: 1.5V; Output load: IOL '"'"
1.6mA. IOH = -0.4mA. Cl = 50pF (min) - for Cl greater than 50pF. access time I. d01ated by 0.15n. per pF.
3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed In Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.
5. TAVQV = TElQV

+ TAVEl.

CAUTION: These devices arB sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-30

Specifications HM-65518/883
TABLE 3. HM-6551 B/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

MAX

UNITS

Input CapaCitance

CI

VCC=Open,
f= 1 MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

10

pF

Output Capacitance

CO

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

12

pF

NOTES:

CONDITIONS

NOTE

TEMPERATURE

MIN

1. All voltage. referenced to device GND.
2. Input pulse lovels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: IOL
1.6mA. IOH - -OAmA. CL - 50pF (mln)- for CL greater than 50pF. access time Is derated by 0.1505 per pF.

ca

3. Typical derating 1.5mA/MHz increase In ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

"'~

Initial Test

100%/5004

-

00

Interim Test

100%/5004

1,7,9

u ....

PDA

100%/5004

1

Final Test

100%/5004

2,3,8A,8B,10, 11'

Group A

Samples/5005

1,2,3,7,8A,8B,9,10,11

GroupsC&D

SampleS/5005

1,7,9

CAUTION: These deviceS ere sensHive to electronic discharge. Proper IC handling procedures should be followed.

3-31

::e::e
::e

Specifications' HM-6551 /883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •.••••••••.••••••••.•••••••.••.•••.••.•• +7.0V
Input or Output Voltage AppJied ••.•.••• GND-0.3VtoVCC+0.3V
Storage Temperature Range ....•• ~ •.••...••. -S50 C to +150 0C
Junction Temperature •••••.••••••.••.••.••••.•.•••••• +1750 C
Lead Temperature (Soldering 10 sec) ••.••.••••.•.••.••• +3000C
ESD Classification ..••••.....••••....•••••.•.•.••.•••. Class 1

Thermal Resistance
Sja
Sjc
Ceramic DIP Package.. • •• •• . ••••• .• •..•• SOoC/W 150C/W
Maximum Package Power. Dissipation at +1250 C
Ceramic DIP Package .•••.•.•••.•.•.•.•••••••.••.• 0.83 Watt
Gate Count •.••.••••••••••.•..••.•.•.•..••••••.•• 1930 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is nol implied.

Operating Conditions
Operating Voltage Range .•••••••••••••••.•.••.• +4.5V to +5.5V
-Operating Temperature Range •••.....•..•... -550C to +1250 C
Input Low Voltage .....••.•......•••••••••.••••.•.. OV to +0.8V

Input High Voltage ••••••..•.••.•.•....•••••• VCC-2.0V to VCC
Input Rise and Fall Time .•••.•.•.•.•.•••.•.•.•••.•.. 40ns Max.

TABLE 1. HM-6551/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS
V

Output Low Voltage

VOL

VCC=4.5V
IOL=1.SmA

1,2,3

-55°C ~.TA => +125 0C

-

0.4

Output High Voltage

VOH

VCC=4.5V
10H =-O.4mA

1,2,3

-550C =>TA=> +125 0C

2.4

-

V

II

VCC=5.5V,
VI = GNDorVCC

"1,2,3

-550C =>TA=> +125 0 C

-1.0

+1.0

f1A

10Z

VCC=5.51f,
VO=GNDorVCC

1,2,3

-55°C =>TA.:S +125 0 C

-1.0

+1.0

f1A

VCC = 2.0V, E = VCC
10 = OmA,
VI=VCCorGND

1,2,3

-550 C$TA=>+1250C

-

10

~A

VCC = 5.5V, (Note 3)
1 MHz, 10 =OmA
VI = VCC or GND

1,2,3

-550C5TA5+1250C

-

4

mA

VCC=5.5V,
10=OmA
VI = VCC or GND

1,2,3

-550C5TA5+1250C

-

10

f1A

Input Leakage Current"
Output Leakage
Current
Data Retention Supply
Current

ICCDR

Operating Supply
Current

ICCOP

Standby Supply
Current

ICCSB

NOTES:

E=

1. All voltages referenced to device GND.
2. Input pulse levels: O.BV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.SV; Output load: IOL
1.6mA, IOH = -O.4mA. CL ~ 50pF (min) - for CL greater than SOpF. access time Is derated by 0.15ns per pF.

=

3. Typical derating 1.SmA/MHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-32

Specifications HM-6551/883
TABLE 2. HM-6551/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS

SYMBOL

(NOTES 1,2)
CONDITIONS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Chip Enable Access
Time

(l)TELQV

vec = 4.S and S.SV

9,10,11

-550C~TA~+1250C

-

300

ns

Address Access Time

(2)TAVQV

VCC = 4.5 and 5.5V
NoteS

9,10,11

-550e~TA~+1250e

-

300.

ns

Chip Select 1 Output
EnebleTime

(3)TS1LQX

vce = 4.5 and 5.SV

9,10,11

-550e~TA~+12Soe

S

-

ns

Write Enable Output
Disable Time

(4)TWLQZ

vce = 4.5 and 5.SV

9,10,11

-550e~TA~+1250e

-

150

ns

Chip Select 1 Output
Disable Time

(5)TS1HQZ

vec = 4.5 and S.5V

9,10,11

-550C~TA~+1250C

-

150

ns

Chip Enable Pulse
Negative Width

(6)TELEH

vee = 4.S and 5.SV

9,10,11

-55 0C ~TA ~ +1250 C

300

-

ns

Chip Enable Pulse
Positive Width

(7)TEHEL

VCC = 4.5 and 5.5V

9,10,11

-550C~TA~

+1250 C

100

-

ns

PARAMETER

(8)TAVEL

vce = 4.5 and 5.5V

9,10,11

-550C~TA:S.+1250C

0

-

ns

(9)TS2LEL

VCC = 4.5 and 5.SV

9,10,11

-550e ~TA:S. +125 0e

0

-

ns

Address Hold Time

(10)TELAX

VCC = 4.5 and 5.5V

9,10,11

-S50e~TA~ +1250C

50

Chip Select 2
Hold Time

(11)TELS2X

VCC = 4.5 and 5.SV

9,10,11

-S50e~TA~+1250e

50

Data Setup Time

(12)TDVWH

VCC = 4.5 and 5.SV

9,10,11

-S50e~TA~+1250e

150

Data Hold Time

(13)TWHDX

vec = 4.5 and 5.5V

9,10,11

-550C ~TA.s +1250 C

Chip Select 1 Write
Pulse Setup Time

(14)TWLS1H

vec = 4.5 and 5.5V

9,10,11

-550C :S.TA.s+125 0C

Chip Enable Write
Pulse Setup Time

(15)TWLEH

VCC = 4.5 and 5.SV

9,10,11

-S50C.s TA So + 1250C

Chip Select 1 Write
Pulse Hold Time

(16)TS1LWH

vec = 4.5 and 5.5V

9,10,11

Chip Enable Write
Pulse Hold Time

(17)TELWH

vec = 4.5 and 5.5V

Write Enable
PulseWidlh

(18)TWLWH

Read or Write
Cycle Time

(19)TELEL

Address Setup Time
Chip Select 2
Setup Time

NOTES:

-

ns

ns

0

-

180

-

ns

180

-

ns.

-550C~TA~+1250C

180

-

ns

9,10,11

-550C~TA~+1250C

180

-

ns

vec = 4.5 and 5.5V

9,10,11

-550e~TA.s +125 0C

180

-

ns

vec = 4.5 and 5.5V

9,10,11

-S50e~TA~+1250C

400

-

ns

ns

ns

2. Input pulse levels: O.BV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 'l.5V; Output load: IOL =
1.6mA. IOH = -O.4mA. Cl = 50pF (min) - for CL greatef than 50pF, access time is derated by 0.15"5 per pF.

Iceop.

4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
andlor design changes.
5. TAVQV

= TELQV + TAVEL.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-33

c.>W

::;:

1. All voltages referenced to device GND.

3. Typical derating 1.5mAlMHz increase in

>-

",II:

00

::;:::;:

Specifications HM-6551/883
TABLE 3. HM-6551/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
CONDITIONS

MAX

UNITS

Input Capacitance

CI

VCC = Open,
f= 1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

10

pF,

Output Capacitance

CO

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

,12

pF

PARAMETER

NOTES:

SYMBOL

NOTE

TEMPERATURE

MIN

I. All voltage. referenced to device GND.
2. Input pulse levels: O.BV to vcc-:i.ov; Input rise and fall times: 5ns (max); Input and output liming reference level: 1.5V; Output load: IOL
I.6mA, IOH = -0.4mA, CL = 50pF (min) - for CL greater than 50pF, acce.. time is derated by 0.I5ns per pF.

=

3. Typical derating 1.5mNMHz increase in ICCOP.

.4. The parameters listed In Table 3 ara controlled via. design or process parameters are characterized upon initial design and after major
and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim'Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3,BA,BB,10,11

Group A

Samples/5005

1,2,3,7, BA, BB, 9, 10, 11

Samples/5005

1,7,9

_ GroupsC&D

CAUTION: These devices are sensitive to electroniC discharge. Proper Ie handling procedures should be followed.

3-34

pr~ess

HM-6551/883
Timing Waveforms
READ CYCLE

lSI TAVEL_

=-nLA~-lIIDI

ISh.vEL_

VALID

==NEXT

1191 TELEL

I-=::::TEHEL
f1I

TELEH

TEHEL-

161

191

r

'I

~
1111

n2LEL_

191
TS2LEL_

171

-

"-

1
~

_TEL::;;;!" I

121 r----TAVQV

f<99I'

131 Tmax

VALID OUTPUT

. !-TSlHQZ 151

w--~~-----------------------------------------------

I

TIME

-,

REFERENCE

TRUTH TABLE
TIME
REFERENCE
-1
0

1
2
3
4

5

INPUTS

OUTPUTS

E

51

52

W

A

D

Q

FUNCTION

H

H

X

X

"""'L

X

L

L
L
L
H

X
X
X
X

X

L

X
X
X
X
X
X
X

Z
Z

L
L

X
H
H
H
H

Memory Disabled
Addresses and 52 are Latched, Cycle Begins
Output Enabled But Undefined
Data Output Valid
Outputs Latched, Valid Data,52 Unlatches
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

....r
H

'-

X
H

V

X
X
X
X
V

The HM-6551/883 Read Cycle is initiated by the falling
edge of E. This signal latches the input address word and
52 into on chip registers providing the minimum setup and
hold times are met. After the required hold time, these inputs
may change state without affecting device operation. 52
acts as a high order address and simplifies decoding. For
the output to be read, E, 51 must be low and W must be
high. 52 must have been latched low on the falling edge of
Eo The output data will be valid at access time (TELaV).

X
V
V
Z
Z

The HM-6551/883 has output data latches that are controlled by E. On the rising edge of E the present data is
latched and remains in that state until E falls. Also on the rising edge of E, 52 unlatches and controls the outputs along
with 51. Either or both 51 or 52 may be used to force the
output buffers into a high impedance state.

3-35

HM-6557/883
Timing Waveforms

(Continued)

181

WRITE CYCLE

1101

181

~EL~

iAVE~

TAYEL---i

VAL1D~

r--

III

TEHEL_lll

151

191

191

TS2LE~

~.
1111

TS2LE~

==--

NEXT

1191TELEL
TELEH

t::=:.!EHEL

'-_

DATA VALID

1171

TELWH

,'"

TWLEHlr51-

_TWHDxIl31

~.TDvwHII21

' / / / / / / . , " ,,",","'\.

....

J--:-'li~j"115!ii--TSILWH
TWLS1H
~
1141

A:7/'/'/'., , , , "

I

REF~~MEENCE,------it--+----1f----------1'--+-----'f--+-I
TRUTH TABLE
TIME
REFERENCE

E

51

52

Vi

A

0

-1

H

H

\...

1
2

L
L

X
X
X

..F

X
L
L
X

X
X

X

0

H

H

\...

X

X
L
X
X
X·
X
.L

3
4
5

INPUTS

\...

..F
H

X
X

V

X
X
X
X
V

In the Write Cycle the falliog edge of E latches the
addresses and 52 into on chip registers_ 52 must be
latched in the low state to enable. the device. The write
portion of the cycle is defined as E, iN, 51 being 19w and 52
being latched simultaneously. The iN line may go low at anY
time during the cycle providing that the write pulse setup
times (TWLEH and TWLS1 H) are mel. The write portion of
the cycle is terminated on the first rising edge of either E, iN,
or 51.
If a series of consecutive write cycles are to be executed,
the iN line may be held low until all desired locations have
been written. If this method is used, data setup and hold
times must be referenced to the first rising edge of E or 81.

Test Load Circuit

V

X
X
X

OUTPUTS
Q

FUNCTION

Z
Z
Z
Z
Z
Z
Z

Memory Disabled
Cycle Begins, Addresses and 52 are Latched
Write Period Begins
Data in is Written
Write is Complet!1d
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

By positioning the write pulse at different times within the E
and 81 low time .(TELEH), various types of write cycles may
be performed. If the 81 low time (TS1 LS1 H) is greater than
the Wpulse plus an output enable time (TS1 LOX), a combination read-write cycle is executed. Data .may be modified
an indefinite number of times during any write cycle
(TELEH).
The HM-6551/883 be used on a common I/O bus structure
by tying "the input arid output pins together. The multiplexing
is accomplished Internally by the iN line. In the write cycle,
when iN goes low, the output buffers are forced to a high impedance state. One output disable time delay (TWLOZ)
must be allowed before applying input data to the bus.

r------------I
I
I
I
I
I
I
DUT D--t-j--

",II:
QQ

:;::;:
u'"
:;:

NOTES:
All Resistors 47kO ± 5%

FO = 100kHz ± 10%
F1= FO + 2. F2 = F1 + 2. F3 = F2 + 2 ••• F12 = F11 + 2
VCC = 5.5V ± 0.5V
VIH = 4.5V ± 10%
VIL = -0.2V to +0.4V
C1 = 0.D1 ~F Min.

3-37

HM-6551/883
Die Characteristics
DIE DIMENSIONS:
132 x 160 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 11kA ± 2kA

G LASS IVATION:
Type: 5102
Thickness: akA ± 1kA
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600C (Max)
WORST CASE CURRENT DENSITY:
1.337 x 105 Ncm 2
LEAD TEMPERATURE (10 seconds soldering):
:S3000 C

Metallization Mask Layout
HM-6551/883

AO

AS A6

NOTE: Pin Numbers Correspond to DIP Package Only.

3-38

A7 GND

HM-6551/883
Packaging t
22 PIN CERAMIC DIP

r------

.

I

1.055
1.085

.005 MIN-1

t

=j':::t

O'

.125
.180

15'

.100
SSC

.065

• INCREASE MAX LIMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-7

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 100 C
Method: Furnace Seal

cni:
QQ

:E:E
""W
:E

NOTE: All Dimensions are

~~

• Dimensions are in inches.

tMil-M-38510 Compliant Materials, Finishes. and Oinlensions.

3-39

HM~6561/883

:m·HARRIS

256 x 4 CMOS RAM

June 1989

Features

Pinout

• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.'2.1.

HM1-6561/663 (CERAMIC DIP)
TOP VIEW

• Low Power Standby ••••••••••••••••••••••••••••••••••••• 50"W Max.

A3

VCC

• Fast Access Time ....................................... 200ns Max.

A2

A4

• Data Retention ......................................... @ 2.0V Min.

Al

W

AO

51

• On-Chip Address Registers

AS

D03

• Common Data In/Out

A6

D02

A7

DOl

GND

DOD

• Low Power Operation ••••••••••••••••••••••••••••• 20mW/MHz Max.

• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load

• Three-State Output
• Easy Microprocessor Interfacing

Description

E

52

The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using selfaligned silicon gate technology. Synchronous circuit design techniques are
employed to achieve high performance and low power operation.
On chip latches are provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output buffers can be
forced to a high impedance state for use in expanded memory arrays. The data
inputs and outputs are multiplexed internally for common I/O bus compatibility.
The HM-6561/883 is a fully static RAM and may be maintained In any state for
an indefinite period of time. Data retention supply voltage and supply current
are guaranteed over temperature.

PIN
A

E

Chip Enable

W

WrileEnable

S

Chip Select

DO

Data In/Out

Functional Diagram
AOo-----I
A1 0 - - - - - 1
A50-----I
AS 0 - - - - - 1
A70-----I

ALL LINES POSITIVE LOGIC - ACTIVE HIGH

DOO

o---....-~

THREE - STATE BUFFERS:
A HIGH - - OUTPUT ACTIVE
DATA LATCHES:

DOl o---~+:<

LHIGH __ Q= D
Q LATCHES ON FAUING EDGE OF L
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OFE
GATE ON FALLING EDGE OF E

DQ3

o---....+:~

Wo-o:C>-......+_-----+-...J
EO-<~~>--+_-----~-~~~

51
52

3-40

DESCRIPTION
Address Input

Specifications HM-65618/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •.••..•••••..•.•......•.•............... +7.0V
Input or Output Voltage Applied •.••••.• GND-0.3V to VCC+0.3V
Storage Temperature Range ••••.••••.••••.•. -6S oC to +lS00C
Junction Temperature •..•.....•.•••...•.•••.•..•..•.. +17S oC
Lead Temperature (Soldering 10 sec) •••••••••.•••••.••. +3000C
ESD Classification •.•••.•.•••.•.••••••••.••••••••.••.• Class 1

Thermal Resistance
0ja
0jc
Ceramic DIP Package..... .•• .•••••• . •••• 74 0 C/W 180C/W
Maximum Package Power Dissipation at +12SoC
Ceramic DIP Package .••.•.••.•.••••••••••.••.•••• 0.68 Walt
Gate Count •.•••.••.••.••.•.••••.•••••••••.•••.•• 1944 Gates

CAUTION: Stresses above those listed In "Absolute Maximum Ratings" may cause permanent damage to the devics. This;s a stress only rating and operation
of the device al these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ....................... +4.SV to +S.SV
Operating Temperature Range •••.•...••••.•• -550C to +12S oC
Input Low Voltage ...............••.........•....•. O.OV to 0.8V

Input High Voltage ...••......•..•.•••.•.•.•. VCC-2.0V to VCC
Input Rise and Fall Time .••.•.••.•.•••...•••........ 40ns Max.

TABLE 1. HM-6561B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VClL

VCC=4.SV
IOL=1.6mA

1,2,3

-550C ::;TAS +12SoC

-

0.4

'V

Output High Voltage

VOH

VCC=4.5V
IOH =-OAmA

1,2,3

-550C ::::TA:::: +12S oC

2.4

-

V

VCC=5.SV,
VI = GND orVCC

1,2,3

-55 0C.$TA$ +1250C

-1.0

+1.0

pA

VCC = 5.5 V,
VIO = GND orVCC

1,2,3

-550 CSTA::; +1250 C

-1.0

+1.0

~A

PARAMETER

Input Leakage Current
InpuVOutput
Leakage Current

SYMBOL

II

IIOZ

Data Retention Supply
Current

ICCDR

VCC = 2.0V, E= VCC
IO=OmA,

1,2,3

-550C ::::TA::::+1250 C

-

10

~A

Operating Supply
Current

ICCOP

VCC = 5.SV, (Note 3)
E= lMHz,W=GND
VI = VCC or GND

1,2,3

-55°C ::;TA::; +1250 C

-

4

rnA

Standby Supply
Current

ICCSB

VCC = 5.SV,
IO=OmA
VI = VCC or GND

1,2,3

-550C STA:::: +125 0C

-

10

~A

NOTES:

1. All voltages referenced to device GND.

and

2. Input pulse levels: O.SV to VCC-2.0V; Input rise and fall times: 5ns (max); Input
output timing reference level: 1.5V; Output load:
IOL = , .SmA, IOH = -O.4mA. CL = 50pF (min) - for CL greater than SOpF, access time is derated by 0.15ns per pF.
3. Typical derating 1.SmA/MHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested; These parameters are characterized
upon initial design and after major process and/or design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.

'3-41

Specifications HM-6561 B/883
TABLE 2. HM-6561B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS

SYMBOL

(NOTES 1,2)
CONDITIONS

GROUP A
SUBGROUPS

TEMPERATURE

MIN'

MAX

UNITS

Chip Enable Access
Time

(1)TELQV

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

-

220

ns

Address Access Time

(2)TAVQV

vee = 4.5 and 5.5V
Note 5

9,10,11

-550e~TA~+1250e

-

220

ns

Chip Select Output
Enable Time

(3)TSLQX

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

5

-

ns

Chip Select Output
Disable lime

(4)TSHQZ

VCC = 4.5 and 5.5V

9,10,11

-550e~TA~ +1250 e

-

120

ns

Chip Enable Pulse
Negative Width

(5)TELEH

vee - 4.5 and 5.5V

9,10,11

-550C~TA~+1250e

220

-

ns

Chip Enable Pulse
Positive Width

(6)TEHEL

vee = 4.5 and 5.5V

9,10,11

-550e~TA=:: +1250 e

100

-

ns

,.

ns

PARAMETER

Address Setup Time

(7)TAVEL

vce = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

0

Address Hold Time

(8)TELAX

vec = 4.5 and 5.5V

9,10,11

-550 e ~ TA:S +1250 e

40

Date Setup Time

(9)TDVWH

vee = 4.5 and 5.5V

9,10,11

-550e~TA:S+1250e

.100

Date Hold Time

(10)TWHDX

vee = 4.5 and 5.5V

9,10,11

-550e~TA:S +1250e

Write Data Delay
Time

(11)TWLDV

vee = 4.5 and 5.5V

Chip Select Write
Pulse Setup Time

(12)TWLSH

Chip Enable Write
Pulse Setup Time

ns

0

-

9,10,11

-550e~TA~ +1250 e

20

-

ns

vee = 4.5 and 5.5V

9,10,11

-550e~TA:S +1250 e

120

-

ns

(1,3)TWLEH

vee = 4.5 and 5.5V

9; 10,11

-550e~TA:S+1250e

120

-

ns

Chip Select Write
Pulse Hold Time.

(14)TSLWH

vee '= 4.5 and 5.5V

9,10,11

-550e~TA:S +1250 C

120

-

ns

Chip Enable Write
Pulse Hold Time

(15)TELWH

vee = 4.5 end 5.5V

9,10,11

-550eSTA~+1250e

120

-

ns

Writs Enable
Pulse Width

(16)TWLWH

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+125OC

120

-

ns

Read or Write
eyelsTime

(17)TELEL

vee = 4.5 and 5.5V

9,10,11

-55OC~TA~+1250e

320.

-

ns

NOTES:

ns
ns

1, All voltages ralerenced to device GND.
2, Input pulse levels: O.8V to VCC-2.OV; Inpul rise and 18I111...s: 5ns (max); Input and oulput liming referenca leval: 1.SV; Oulpul load:
IOl - 1.6mA.IOH - -O.4mA. Cl - SOpF (min) -for Cl greater Ihan 5OpF. acee.. llme Is derated by O.ISns per pF.
3. Typical derating I.SmAlMHz increase In ICCOP.
4. The parameter. listed In Table 3 are controlled via design or proce.. parameters are characterized upon InHla1 deSign and aller major process
and/Or dasign changes.
5. TAVQV - TElQV

+ TAVEL.

CAUTtON: Those devlcas are sensHIYe to electronic discharge. Proper tc handling procedures,should be followed.'

3-42

Specifications HM-65618/883
TABLE 3. HM-6561B/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

MAX

UNITS

Input Capacitance

CI

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+25 0 C

-

8

pF

Output Capacitance

CO

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

10

pF

NOTES:

SYMBOL

CONDITIONS

NOTE

TEMPERATURE

MIN

1. All voltages referenced to device GND.

2. Input pulse levels: O.SV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference lavel: 1.5V; Output load:
IOL ~ 1.6mA. IOH = -0.4mA, CL = SOpF (min) - for CL greater than SOpF, access time is derated by 0.1Sns per pF.
3. Typical derating 1.SmAJMHz increase In ICCOP.
4. The parameters listed in Table 3 BrB controlled via design or process parameters are characterized upon initial design and after major process

and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
InitialTest

METHOD

SUBGROUPS

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

FinalTest

100%/5004

2,3,8A,8B,10,11

Group A

Samples/5005

1,2,3,7, 8A, 8B, 9,10,11

GroupsC&D

Samples/5005

1,7,9

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-43

>-

enD:
00

.......:;:

:;::;:

Specifications HM-6561/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••••••••••••••••••••••••••••••• +7.0V
Input or Output Voltage Applied ••••••• GND-O.3V to VCC+0.03V
Storage Temperature Range ••••••••••••••••• -650C to +1500C
Junction Temperature ................................ +1750C
Lead Temperature (Soldering 10 sec) ••••••••••.•••••••• +3000C
ESD Classification ••••••••••••••••••••••••••• ; •••••••• Class 1

Thermal Resistance
0ja
0jc
Ceramic DIP Package................ •••• 740 C/W 180C/W
Maximum Package Power Dissipation at +1250C
Ceramic DIP Package ••••••••••••••••••••••••••••• 0.68 Watt
Gala Count ......................... , ••••••••••••• 1944 Gates

CAUTION: Stresses above those listed in ''Absolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only rating and operation
of the device at these Of any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ....................... +4.5V to +5.5V
Operating Temperature Range ••••••••••••••• -550C to +1250 C
Input Low Voltage •••••••••••••••••••••••••••••• -0.3V to +0.8V

Input High Voltage ••••••••••••••••••••• VCC-2.0V to VCC+0.3V
Input Rise and Fall Time ••••••••••••• , •••••••.•••••• 40ns Max.

TABLE 1. HM-6561/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Teslad
(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC= 4.5V
IOL=1.6mA

1,2,3

-550C ~TA ~ +1250 C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
IOH=-0.4mA

1,2,3

-550C~TA~+1250C

2.4

-

V

VCC= 5.5V,
VI = GND orVCC

1,2,3

-550C ~TA~ +1250 C

-1.0

+1.0

JJA

VCC = 5.5 V,
VIO = GND or VCC

1,2,3

-550C~TA~+1250C

-1.0

+1.0

JJA

PARAMETER

Input Leakage Current
InpuVOutput
Leakage Current

SYMBOL

II
IIOZ

Data Retention Supply
Current

ICC DR

VCC = 2.0V, E = VCC
10 = OmA,

1,2,3

-550C~TA~+1250C

-

10

JJA

Operating Supply
Current

ICCOP

VCC = 5.5V, (Nola 3)
E= lMHz,W=GND
VI=VCCorGND

1,2,3

-55°C ~TA ~ +1250 C

-

4

mA

Standby Supply
Current

ICCSB

VCC= 5.5V,
10=OmA
VI=VCCorGND

1,2,3

-550C~TA~+1250C

-

10

JJA

NOTES:

I. All voltages referenced to device GND.
2. Inpul pulse levels: O.BV to VCC-2.0V; Input rise and !all lime.: 5n. (max); Input and output timing relerence level: 1.5V; Output load:
IOL = 1.6mA. IOH = -O.4mA. CL - 50pF (min) - for CL greater than 50pF. access time is derated by 0.15n. per pF.
3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed In Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial deSign and after major process and/or design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures ,should be followed.

3-44

Specifications HM-6561/883
TABLE 2. HM-6561/BB3 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.5V

9, la, 11

-55 0 C.::;.TA.::;.+1250C

-

300

ns

Chip Enable Access
Time

(1)TELQV

VCC

Address Access Time

(2)TAVQV

VCC 4.5 and 5.5V
Note 5

=

9, la, 11

-550 C.::;.TA'::;' +1250 C

-

300

ns

Chip Select Output
Enable Time

(3)TSLQX

VCC

=4.5 and 5.5V

9, la, 11

-550 C.::;.TA'::;' +1250 C

5

-

ns

Chip Select Output
Disable Time

(4)TSHQZ

VCC

=4.5 and 5.5V

9, la, 11

-55 0 C.::;.TA,S+1250C

-

150

ns

Chip Enable Pulse
Negative Width

(5)TELEH

VCC

=4.5 and 5.5V

9,10,11

-550C.::;. TA'::;' +1250 C

300

-

ns

Chip Enable Pulse
Positive Width

(S)TEHEL

VCC

=4.5 and 5.5V

9,

la, 11

-550 C.::;.TA.::;.+1250C

lOa

-

ns

Address Setup Time

(7)TAVEL

VCC

=4.5 and 5.5V

9, la, 11

-550 C.::;.TA.::;.+1250C

a

Address Hold Time

(B)TELAX

VCC - 4.5 and 5.5V

9, la, 11

-550C'::;'TA~+1250C

50

Data Setup Time

(9)TDVWH

VCC

9, la, 11

-550 C.::;.TA.::;.+1250C

150

Data Hold Time

(10)TWHDX

9,10,11

-550C~TA'::;'+1250C

a

Write Data Delay
Time

(11)TWLDV

=4.5 and 5.5V
VCC =4.5 and 5.5V
VCC =4.5 and 5.5V

-

9, la, 11

-55 0 C.::;.TA.::;.+1250C

30

-

ns

Chip Select Write
Pulse Setup Time

(12)TWLSH

VCC

=4.5 and 5.5V

9, la, 11

-550 C.::;.TA'::;' +1250 C

lao

-

ns

Chip Enable Write
Pulse Setup Time

(13)TWLEH

vce =4.5 and 5.5V

9, la, 11

-55°C '::;'TA:>' +1250 C

lao

-

ns

Chip Select Write·
Pulse Hold Time

(14)TSLWH

VCC

=4.5 and 5.5V

9, la, 11

-550 C.::;.TA'::;' +1250 C

lao

-

ns

Chip Enable Write
Pulse Hold Time

(15)TELWH

VCC

=4.5 and 5.5V

9,10,11

-550C:>. TA:>' +1250 C

lao

-

ns

Write Enable
PulseWidlh

(1S)TWLWH

VCC

=4.5 and 5.5V

9, la, 11

-550 C.::;.TA:>' +125 0 C

lao

-

ns

Read or Write
Cycle Time

(17)TELEL

VCC

=4.5 and 5.5V

9,10,11

-55 0 C:>.TA:>' +1250 C

400

-

ns

NOTES:

ns
ns
ns
ns

",I;:

00

1. An voltages referenced to device GND.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.SV; Output load:
IOL = I.SmA. IOH = -O.4mA, CL = 50pF (min) - for CL grealer than 50pF, acceso time is deraled by 0.15no per pF.
3. Typical derating 1.5mNMHz increase In ICeO?

4. The parameters listed in Table 3 are control/ed via design or process parameters are characterized upon initial design and afler major process
and/or design changes.
5. TAVQV

= TELQV + TAVEL.

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed:

3-45

====
==

c.>W

Specifications HM-6567/883.
TABLE 3. HM-6561/663 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MAX

UNITS

Input Capacitance

CI

VCC = Open,
f=1MHz,
All Measurementa
Referenced to
Device Ground

4

TA=+250C

-

8

pF

Output Capacitance

CO

VCC = Open,
f= 1MHz,
All Measurementa
Referenced to
Device Ground

4

TA=+250 C

-

10

pF

PARAMETER

NOTES:

SYMBOL

1. All voltages referenced

CONDITIONS

NOTE

TEMPERATURE

MIN

to device GND.

2. Input pulse levels: O.BV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
IOL - 1.6mA, IOH - -o.4mA, CL - 50pF (min) - for CL greater than 50pF. access lime Is derated by 0.15n8 par pF.
3.

tYPical derating 1.5mNMHz Increa8eln ICCOP.

4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/Or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%15004

-

Interim Test

100%15004

1,7,9

PDA

100'16/5004

1

Final Test

100%15004

2,3,8A,8B,10,11

Group A

Samples/5005

1,2,3, 7, SA, SB, 9,10. 11

GroupsC&D

Samples/5005

1,7,9

CAUTION: Thaae device. are sensitive to electronic discharge. Proper IC handling procedurel should be followed.

3-46

HM-6561/883
Timing Waveforms
READ CYCLE

'---TOLOV:=1 11 )
(2)r---TAVOV
HIGH

DO PREV110UST::::~(4)
,1,$;

I.

z

~i~r

j

VALID OATAL;::!HO' ~

JVZ/~~

HIGH Z

-¥//~

R,,!I:E~CE---+I--+-I----il'-----it'----+t--+t--+--t
.,

0

1

2

3

4

5

TRUTH TABLE
TIME
-REFERENCE
-1
0
1
2
3

4
5

INPUTS

E

S1

Vi

A

H

H
X
L
L
L
H

X
H
H
H
H
X
H

X
V
X
X

""L
L
L

J"""
H

""L
NOTES:

X

OUTPUT
DQ

FUNCTION

Z
Z
X
V
V
Z
Z

Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Output Latched
Device Disabled, Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

X
X
V

>",0:
00

::::::::
c.>W

::::

1. Device .elected only if both

iii

and

52 are low, and deselected if either iii

The HM-6561/883 Read Cycle is initiated on the falling
edge of E. This signal latches the input address word into
on chip registers. Minimum address setup and hold times
must be met. After the required hold time, the address lines
may change state without affecting device operation. In order to read the output data E, 51_and 52 must be low and VIi
must be high. The output data will be valid at access time

or

52 are high.

The HM-6561/883 has output data latches that are controlled by E. On the rising edge of E the present data is
latched and remains latched until E falls. Either or both 51
or 52 may be used to force the output buffers into a high impedance state.

(TELQV).

3-47

HM-6561/883
Timing .WaveformS(Continued)
WRITE CYCLE

(7)TAVE~

I- TELAX ~ (8)

(7)TAVE~

'-

VALlD~

NEXT

TELEl

'~TEHEL

(17)
TEHEL_

TELEH

(5)

(6)

(6)

'--

(13)

TWLEH

(15)

TELWH

TWLWH

(16)

! -TWLDV
, ( 1 1 h CDVWH
(9) DO

-. t.(\'8\x

VALID DATA

~'!'l~~

.1

TWUH

(12)

".S2ijJ'//////I4\"'\\\\\\\~

REF~::NCE-----'lI---+--+-------+--+---l~-+-1

TRUTH TABLE
TIMEREFERENCE

INPUTS

E

S1

'iN

A

DQ

H

H
X
L
L
X
H
X

X
X
L

X
V
X
X
X
X
V

X
X
X
V
X
X
X

-1
0
1
2
3

..F

4

H

5

"L-

"LL
L

NOTES:

..F
H
X
X

1. Device selected only if both 51 and

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Write Period Begins
Data In Is Written
Write Is Completed
Prepare for Next Cycie (Same as -1)
Cycle Ends, Next Cycle,Begins,(Same as 0)

52 are low, and deselected if either 51

The write cycle begins with the E falling' edge latching the
address. The write portion of the cycle Is defined by E, 51,
52 and W all being low simultaneously_ The write portion of
the cycle is terminated by the first rising edge of any control
line, E; 51, 52 or W. The data setup and data hold times
(TDVWH and TWHDX) must be referenced to the terminating signal. For example, if 52 rises first, data setup and hold
times become TDV52H and T52HDX; and-are numerically
equal to TDVWH and TWHDX.'
Data input/output multiplexing is controlled by_ W. Care
must be taken to avoid data bus conflicts, where the RAM
outputs become enabled when another device is driving the
data inputs. The following two examples illustrate the timing
required to avoid bus conflicts.

or 52 are high_

If one or both selects are high until W falls, the outputs are
guaranteed not to enable at the beginning of the cycle. This
eliminates the concern for data bus conflicts and simplifies
data input timing. Data input may be applied as early as
convenient, and TWLDV is ignored. 5ince W is not used to
disable the outputs It can be shorter than In Case 1;
TWLWH is the minimum write pulse. At the end of the write
period, if Wrises-before either select the outputs will enable,
reading the data just written. They will not disable until
either select goes high (T5HQZ).

CASE 1

IF

OBSERVE

IGNORE

Both Sl and S2 =Low
BeforeVi =Low

TWLQZ
TWLDV
TDVWH

TWLWH

Case 1: Both 51 and 82 Fall Before W Falls.
CASE 2
W =Low Before Both
TWLWH
TWLQZ
If both selects fall before W falls, the RAM outputs will
TDVWH
TWLDV
51 and S:i =Low
become enabled. W is used to disable the outputs, so a
disable time (TWLQZ '" TWLDV) must pass before any, If a series of consecutive write cycles are to be performed,
other device can begin to drive the data inputs. This method W may remain low until all desired locations are written.
of operation requires a wider write pulse, because This is an extension of Case 2.
TWLDV + TDVWH is greater than TWLWH. In this case
TWL5L and T5HWH are meaningless and can be ignored. Read-Modify-Write cycles and Read-Write-Read cycles
can be performed (extension of Case 1). In fact, data may be
modified as many times as desired with E remaining low.
Case 2: WFalls Before Both 51 and 52 Fall.

3-48

HM-6561/883

Test Load Circuit

--------------,
I
I
I
I

OUT o--t-t--41l

-TEST HEAD
CAPACITANCE.
INCWDES STRAY
AND JIG CAPACITANCE

I
I
I
I
I
I

CIRCUIT
I- - - -EQUIVALENT
----------

Burn-In Circuit
HMl-6561/883 CERAMIC DIP

VCC
F6-,"""M,..-~

F5-,"""M"'-~

F7

F4-,"""M"'-~

Fl'

F 3 -.JV'.II\I---I

FO

F8-,"""M,..-~

F2

Fg-"""""',..--t

F2

F 10 -"""""',..--t

F2
F2

F 0 --"''''''--i

FO

NOTES:

All Resistors 47kO ± 5%
FD = 100kHz ± 10%

Fl= FO + 2. F2 = Fl + 2. F3 = F2 + 2 ••• F12

~

Fll + 2

VCC = 5.5V ± 0.5V
VlH

=4.5V ± 10%

VIL

a

-0.2V to +0.4V

Cl = 0.Q1 ~F Min.

3-49'

~

HM-6561/883
Die Characteristics
DIE DIMENSIONS:
132 x 160 x 19 ± :1 mils
METALLIZATION:
Type: Si-AI
Thickness: llkA ± 2kA
GLASSIVATION:
Type: Si02
Thickness: 8kA ± 1kA
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
WORST CASE CURRENT DENSITY:
1.337 x 105Ncm2
LEAD TEMPERATURE (10 seconds soldering):
!>300o C

Metallization Mask Layout
HM-6561/883
D03D02
DOl

DOO

A4

vee
A3

A2

E
GND

Al

AO

AS

A6

A7

HM-6561/883
Packaging t
18 PIN CERAMIC DIP
.882
.005 MIN

t

~

'200~MAX'015
L

.915

.285

1r==.++305~1

rt==========l

.060.

O'

.125

15'

.180

.100
BSC

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 1QoC
Method: Furnace Seal

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
. SOLDER FINISH

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-6

>W

::::

NOTE: All Dimensions are

..M!!!....
. Dimensions are in inches.
Max

t Mil-M-38S10 Compliant Materials, Finishes, and Dimensions.
3-51

lit HARRIS

HM-6504/883
4096

June 1989

X

1 CMOS RAM

Pinout

Features

HM1-6S04/883 (CERAMIC DIP)
TOP VIEW

• This Circuit is Processed in Accordance to Mil-Std-8S3 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.
• Low Power Standby ••••••••••••••••••••••••••••••••••• 1251lWMax.

AD

VCC

• Data Retention ••••••••••.•••••••••••••••••••••••••••••• @ 2.0V Min.

A1

A6

• TTL Compatible Input/Output

A2

A7

A3

AS

A4

A9

AS

A10

Q

A11

• Low Power Operation ••••••••••••••••••••••••••••• 35mW/MHz Max.

• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time ••••••••••••••••••••••••••••••••••• 120/200ns Max.
.18 Pin Package for High Density
• On-Chip Address Register
• Gated Inputs - No Pull Up or Pull Down Resistors Required

Description

Vi

D

GND

E

The HM-6504/883 is a 4096 x 1 static CMOS RAM fabricated using selfaligned silicon gate technology. The device utilizes synchronous circuitry to
achieve high performance and low power operation.
On chip latches are provided for addresses, data input and data output
allowing efficient interfacing with microprocessor systems. The data output can
be forced to a high impedance state for use in expanded memory arrays.

PIN

Gated Inputs allow lower operating current and also eliminates the need for
pull-up or pull-down resistors. The HM-6504/883 Is a fully static RAM and
may be maintained in any state for an indefinite period of time.

E

Chip Enable

Vi

Write Enable

D

Data Input

Q

Data Output

A

Data retention supply voltage and supply current are guaranteed over
temperature.

DESCRIPTION
Address Input

Functional Diagram

_--=S-....

LSD AS .......
A7
A8

AO
At
A2 "'-_..L..;,.--....

D

o--t.:r~--cI

E

o--t-CI

64.64
84

MATRIX

Q

ALL UNES ACTIVE HIGH - POSITIVE LOGIC

>-+t---,.:--......- - - '

THREE .. STATE BUFFERS:
A HIGH __ OUTPUT ACTIVE

CONTROL ANO DATA LATCHES:
LLOW __ Q=D
Q LATCHES ON RISING EDGE OF L
ADDRESS LATCHES:
LATCH ON FALUNG EDGE OF E
GATED DECODERS:
GATE ON RISING EDGE OF G

LSBA11 ASA4A3A9A10

Copyright @) Harris Corporation 1989

3-52

Specifications HM-6504S/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ........................................ +7.0V
Input or Output Voltage Applied •••••••• GND-0.3V to VCC+0.3V
Storage Temperature Range ••.••••••••.•.••• -650C to +1500 C
Junction Temperature ................................ +175 0C
Lead Temperature (Soldering 10 sec) ••••••••••• , .••••••• 3000C
ESD Classification .................................... Class 1

Thermal Resistance
0ja
0jc
Ceramic DIP Package............... . .... 660 C/W 120 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package .......................... '" 0.75 Wall
Gate Count ....................................... 6910 Gates

CAUTION: Stresses above those listed in ·'Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational seclions of this specification ;s not implied.

Operating Conditions
Operating Voltage Range ....................... +4.5V to +5.5V
Operating Temperature Range •.•.•••••••••.• -550C fo +1250 C

Input Low Voltage .............................. -0.3V to +0.8V
Input High Voltage ••.•••••.••.•..••.••. VCC-2.0V to VCC+0.3V

TABLE 1. HM-6504S/883 D.C. ELECTRICAL PERFORMANCE CHARACTERtSTICS
Device Guaranteed and 100% Tested

PARAMETER

(NOTE 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC=4.5V
IOL=2mA

1,2,3

-55°C STAS +1250 C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
IOH=-1.0mA

1,2,3

-550CSTAS+1250C

2.4

-

V

II

VCC=5.5\f,
VI = GND orVCC

1,2,3

-55°C STAS +1250 C

-1.0

+1.0

flA

IOZ

VCC= 5.5\f,
VO=GNDorVCC

1,2,3

-550CSTAS+1250C

-1.0

+1.0

flA

Input Leakage Current
Output Leakage
Current

SYMBOL

Data Retention Supply
Current

ICCDR

VCC = 2.0V, E = VCC
IO=OmA

1,2,3

-550CSTAS+1250C

-

25

flA

Operating Supply
Current

ICCOP

VCC = 5.5\1, (Note 3)
E = 1 MHz ,10 =OmA

1,2.3

-550 CSTAS+1250C

-

7

rnA

Standby Supply
Current

ICCSB

VCC=5.5V,
E=VCC-0.3\f,
10=OmA

1,2,3

-55°C STA S +1250 C

-

50

flA

NOTES:

1. All vollage. referenced 10 VSS.
2. Input pulse levels: O.8V to VCC-2.0V: Input rise and fall times: 5ns (max); Input and output timing reference lavel: 1.5V Output load: 1 TTL gate
equivalent. Cl co 50pF (min) - for CL greater than 50pF, access time Is derated by 0.15ns per pF.

3. Typical derating 1.5mNMHz increase In IGGOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and afler major process
and/or design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-53

en

>a:

00

...,w
====

==

Specifications HM-6504S/883
TABLE 2. HM-6504S/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100,*, Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.5V

9,10,11

-55 0e.sTA:5: +1250 e

-

120

ns

ehip Enable Access
Time

TELOV

vee

Address Access Time

TAVOV

vee 4.5 and 5.5V
Note 5

=

9,10,11

-550 e :5 TA :5 + 125°C

-

120

ns

Chip Enable Pulse
Negative Width

TELEH

vee

=4.5 and 5.5V

9,10,11

-55 0e.:5TAS+1250e

120

-

ns

Chip Enable Pulse
Positive Width

TEHEL

vee

=4.5 and 5.5V

9,10,11

-550e.:5TA:5 +125 0e

50

-

ns
ns

Address Setup Time

TAVEL

vee

-550eSTA.:5+1250e

0

TElAX

vee

9,10,11

-550 e.:5 TA.:5+1250e

40

Write Enable Pulse
Width

TWLWH

=4.5 and 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V

9,10,11

Address Hold Time

9,10,11

-550e.:5 TA.:5 +1250 e

20

-

Write Enable Pulse
Setup Time

TWLEH

vee

=4.5 and 5.5V

9,10,11

-550e.:5TA:5 +125 0e

70

-

ns

Early Write Pulse
Setup Time

TWLEL

vee

=4.5 and 5.5V

9,10,11

-550 e:5TA.:5 +1250 e

0

-

ns

Early Write Pulse
Hold Time

TELWH

vee

=4.5 and 5.5V

9,10,11

-550 e.sTA:5 +1250e

40

-

ns

Data Setup Time

TDVWL

vee

-550 e:5 TA.:5+1250e

0

-

ns

TDVEL

vee

=4.5 and 5.5V
=4.5 and 5.5V

9,10,11

Early Write Data
Setup Time

9,10,11

-55°C S TA.:5 +125 0e

0

-

ns

Data Hold Time

TWLDX

vee

=4.5 and 5.5V

9,10,11

-550C STA:5 +1250e

25

TELDX

vee - 4.5 and 5.5V

9,10,11

-550e.:5TA.:5+1250e

25

-

ns

Early Write Data
Hold Time
Read or Write
eycleTime

TELEL

vee

=4.5 and 5.5V

9,10,11

-550eSTA:5+1250e

170

-

ns

NOTES:

ns
ns

ns

1. All voltage. referenced to VSS.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF. access time is derated by 0.1508 per pF.
3. Typical derating 1.5rnA/MHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters"are characterized upon initial design and after major process
and/or design changes.
5. TAVQV = TELQV

+ TAVEL.

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.

3-54

Specifications HM-6504S/883
TABLE 3. HM-6504S/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITIONS

NOTE

TEMPERATURE

MIN

MAX

UNITS
pF

Input Capacitance

CI

vce = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+2S0C

-

S

Output Capacitance

CO

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+2S0C

-

10

pF

Chip Enable Output
Enable Time

TELOX

VCC = 4.5V and S.SV

4

-SSOeSTAS +12So C

S

-

ns

Chip Enable Output
Disable Time

TEHOZ

VCC = 4.5V and S.SV

4

-SSOCSTA:5+12SOC

-

SO

ns

Write Enable Read
Mode Setup Time

TWHEL

vce = 4.5V and S.SV

4

-ssoe :5TAS +12So e

0

-

·ns

High Level Output
Voltage

VOHL

VCC=4.SV,
IO=-100pA

4

-SSoCSTA:5+12S0C

vce
-0.4

-

V

NOTES:

1. All voltage. referenced to VSS.
2. Input pulse levels: O.SV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL

= 50pF (min) -

for CL greater than 50pF, access time is derated by 0.15"8 per pF.

4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon Inillal design and after major process
and/or desIgn changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

>-

en":

00

3. Typical derating SmNMHz increase in tCCOP.

METHOD

SUBGROUPS

Initial Test

100%/S004

-

Interim Test

100%/S004

1,7,9

PDA

100%/S004

1

RnalTest

100%/S004

2,3, SA, SB, 10, 11

Group A

Samples/SOOS

1,2,3,7, SA, SB, 9,10,11

GroupsC&D

Samples/SOOS

1,7,9

CAUTION: These device. are .ensitive to electronic discharge. Proper IC handling procedure. should be followed.

3-55

::::
yw

::

Specifications HM-6504B/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ........................................ +7.0V
Input, Output or 1/0 Voltage Applied. • • •• GND-0.3V to VCC+0.3V
Storage Temperature Range ••••.•••••.••••• , -6S oC to +1500 C
Junction Temperature ................................ +1750 C
Lead Temperature (Soldering 10 sec) ................... +3000C
ESD Classification .................................... Class 1

Thermal Resistance
Sja
Sjc
Ceramic DIP Package •••••.•..••.••••• , •• 660 C/W 12 0 C{W
Maximum Package Power Dissipation at +12So C
Ceramic DIP Package ............................. 0.75 Wall
Gate Count ...................................... 6910 Gates

CAUTION: Stresses above those',isted in "Absolute Max/mum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated ;n the operational sections of this specification Is not implied.

Operating Conditions
Operating Voltage Range ....................... +4.SV to +S.5V
Operating Temperature Range ............... -5So C to +12So C

Input Low Voltage .............................. -0.3V to +0.8V
Input High Voltage ....•................ VCC-2.0V to VCC+0.3V

TABLE 1. HM-6504B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUP.S

TEMPERATURE

MIN

MAX

UNITS

VCC=4.SV
IOL=2mA

1,2,3

-SSoC ~TA~ +12SoC

-

0.4

V

VCC=4.SV
IOH=-1.0mA

1,2,3

-S50C~TA~+12S0C

2.4

-

V

II

VCC =S.Sv,
VI = GND orVCC

1,2,3

-550C~TA=:;+1250C

-1.0

+1.0

pA

10Z

VCC=5.SV,
VO=GNDorVCC

1,2,3

-550C~TA.s+1250C

-1.0

+1.0

pA

Data Retention Supply
Current

ICCDR

VCC=2.0V,
E=VCC,IO=OmA

1,2,3

-55°C .s TA .s + 125°C

-

25

pA

Operating Supply
Current

ICCOP

YCC ,;, 5.5V, (Note 3),
E= 1MHz, 10 = OmA

'1,2,3

-550C.sTA~ +125 0C

-

7

mA

Standby Supply
Current

ICCSB

VCC= 5.5V,
E= VCC-0.3V,
10=OmA

1,2,3

-550C'~ TA:S

-

SO

pA

, PARAMETER

SYMBOL

Output Low Voltage

VOL

Output High Vo~age

VOH

Input Leakage Current
Output Leakage
Current

NOTES:

+12SoC

I, All voltages referenced to VSS..
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V Output load: 1 TTL gate
equivalent, CL = SOpF (min) - for CL, greater than 50pF, access time is derated by O.1Sns per pF.

3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
"
and/or design changes.

,CAUTION: These devices. are sensitive to electronic discharge. Proper IC handling procedures should be followed.

3-56

Specifications HM-65048/883
TABLE 2. HM-6504B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.SV

9,10,11

-550C5TA5 +1250 e

-

200

ns

Chip Enable Access
Time

TELaV

VCC

Address Access Time

TAvav

vee 4.5 and 5.5V
Note 5

=

9,10,11

-550 e.::;TA:5 +125 0e

-

200

ns

Chip Enable Pulse
Negative Width

TELEH.

vee

=4.5 and 5.SV

9,10,11

-55 0 e:5 TA:5 +1250 e

200

-

ns

Chip Enable Pulse
Positive Width

TEHEL

vee - 4.5 and 5.5V

9,10,11

-550e.::;TA:5+1250e

90

-

ns

Address Setup Time

TAVEL

vee

9,10,11

-550C :5TA:5 +1250e

20

Address Hold Time

TELAX

9,10,11

-550e:5TA:5 +1250e

50

Write Enable Pulse
Width

TWLWH

=4.5 and 5.SV
vee =4.5 and 5.SV
vee =4.5 and 5.5V

9,10,11

-550 e :5TA:5 +1250 e

60

-

Write Enable Pulse
Setup Time

TWLEH

vee

=4.5 and 5.5V

9,10,11

-550 e,:5TA:5 +1250 e

150

-

ns

Early Write Pulse
Setup Time

TWLEL

vee

=4.5 and 5.5V

9,10,11

-550e:5TA5 +1250 e

0

-

ns

Early Write Pulse
Hold Time

TELWH

vee

=4.5 and 5.SV

9,10,11

-550 e :5 TA:5 + 1250e

60

-

ns

Data Setup Time

TDVWL

vee

-550e:5TA:5+1250e

0

-

ns

TDVEL.

vee

=4.5 and S.SV
=4.5 and 5.SV

9,10,11

Early Write Data
Setup Time

9,10,11

-550e:5TA:5+1250e

0

-

ns

Data Hold Time

TWLDX

vee

=4.5 and 5.5V,

9,10,11

-55 0e :5 TA:5 + 1250e

60

-

ns

Early Write Data
Hold Time

TELDX

vee - 4.5 and 5.5V

9,10,11

-550e:5TA5 +125 0e

60

-

ns

Read or Write
eycleTime

TELEL

vee

=4.5 and 5.SV

9,10,11

-550e :5 TA:5 + 1250e

290

-

ns

NOTES:

ns
ns
ns

1. All vollages referenced 10 VSS.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent. CL = 50pF (min) - for CL greater than 50pF, access tima is derated by 0.15ns per pF.

3. Typical derating 1.5mAJMHz increase in

Iceop.

4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.
5. TAVaV = TElaV

+ TAVEL

CAUTION: These devices arB sensitive to electronic discharge. Proper

Ie handling procedures should be followed.
·3-51'

Specifications HM-65048/883
TABLE 3. HM-6504B/883 ELECTRICAL'PERFORMANCE CHARACTERISTICS
LIMITS'
PARAMETER'

SYMBOL

Input Capacitance

CONDITIONS

NOTE

..

TEMPERATURE

MIN

MAX

UNITS

TA=+250C'

-

8

pF,

CI

VCC=Open,
1= 1 MHz,
All Measurements
Referenced to
Device Ground

4

Output Capacitance

CO

VCC = Open,
,1= 1MHz,
All Measurements
. Referenced to
Device Ground

4

TA=+250 C

-

10

pF

Chip Enable Output'
Enable Time

TELOX

VCC = 4.5V and 5.5V

4

-550C:s.TA~+1250C

5

-

ns

Chip Enable Output
Disable Time

TEHOZ

VCC = 4.5V and 5.5V

4

-550C~TA:s.+1250C

-

50

ns

Write Enable Read
Mode ~etup Time

TWHEL

VCC = 4.5Vand 5.5V

4

-550 C::;:TA::;:+125 0C

0

-

ns

High Level Output
Voltage

VOH2

VCC=4.5V,

4

-550C::;:TA::;:+125~C

VCC
-0.4

-

V

NOTES:

IOH=-100~A

1. All voltages referenced to VSS.
2. Input pulse levels: O.BV to VCC-2.oV; Input rise and fall times: 5ns (max); In'put and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time Is derated by 0.15n5 per pF.
3. Typical derating ·1.5mNMHz Increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon Initial design and after major process
and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%15004

1,7,9

100%

1

PDA
Final Test

100%

2,3, 8A, 8B,10,11

Group A

Samples/5005

1,2,3,7, BA,8B,9,10,11

GroupsC&D

Samples/5005

1,7,9

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.
3-58

Specifications HM-6504/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •.•.••••.•••..•••..••.•••..•.•..•..•.•.. +7.0V
Input, Output or I/O Voltage Applied ..••. GND-0.3V to VCC+0.3V
Storage Temperature Range ................. -650C to +150 0C
Junction Temperature ........•••............•..•..••. +175 0C
Lead Temperature (Soldering 10 sec) •..•.....•..•.••.•• +300 0 C
ESD Classification .......••.•............••..•...•.... Class 1

Thermal Resistance
0ja
0jc
Ceramic DIP Package. . . . . . . . . . . . . • • • • . .. 66 0 C/W 120 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package •.••.•.•............•.••••.•. 0.75 Wall
Gate Count •.•..•.•..•••...•....•••.............. 6910 Gates

CAUTION: Stresses above those listed;n "Absolute Maximum Ratings" may cause permanent damage to the device. This ;s a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Condition,s
Operating Voltage Range ••............•.....••. +4.5V to +5.5V
Operating Temperature Range ....••••..•..•. -550C to +125 0C

Input Low Voltage .•.••.............•••.•.•...•. -0.3V to +0.8V
Input High Voltage ..........•.•.•..•... VCC-2.0V to VCC+0.3V

TABLE 1. HM-6504/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

(NOTES 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC=4.5V
10=2mA

1,2,3

-550C~TA~+1250C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
10=-1.0mA

1,2,3

-55°C :STA:S +125 0 C

2.4

-

V

II

VCC=5.5V,
VI = GND orVCC

1,2,3

-550C:S TA ~ +125 0 C

-1.0

+1.0

~A

10Z

VCC=5.5V,
VI = GND orVCC

1,2,3

-550C:S TA ~ +125 0 C

-1.0

+1.0

~A

VCC= 2.0V,
E = VCC V,IO = OmA

1,2,3

-55°C :S TA :S + 125°C

-

25

~A

VCC = 5.5V, (Note 3),

1,2,3

-550C~TA~+1250C

-

7

rnA

1,2,3

-550C:STA~ +125 0 C

-

50

~A

Input Leakage Current
Output Leakage
Current

SYMBOL

Data Retention Supply
Current

ICCDR

Operating Supply
Current

ICCOP

Standby Supply
Current

ICCSS

>-

E = VeC-0.3V,
10=OmA

NOTES:

UW

::;;:

E = 1MHz,I0 = OmA
VCC= 5.5V,

rna:
::;;:::;;:

00

1. All voltages referenced to VSS.
2. Input pulse levels: O.BV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL grealer than 50pF, access time is derated by 0.15ns per pF.
3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed In Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.

3-59

Specifications HM-6504/883
TABLE 2. HM-6504/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.5V

9,10,11

-550e:S:TA:S,+1250e

-

300

ns

Chip Enable Access
Time

TELQV

vee

Address Access Time

TAVQV

vee 4.5 and 5.5V
Note 5

=

9,10,11

-55°C :S,TA:s' + 125°C

-

320

ns

Chip Enable Pulse
Negative Width

TELEH

vee

=4.5 and 5.5V

9,10,11

-550e:S,TA:S,+1250e

300

-

ns

Chip Enable Pulse
Positive Width

TEHEL

vee

=4.5 and 5.5V

9,10,11

-550 e.::;:TA':::+1250e

120

-

ns
ns

Address Setup Time

TAVEL

vee

-550e:S:TA.:::+1250C

20

TELAX

vee

9,10,11

-550 e:S,TA;:S:+1250e

50

Write Enable Pulse
Width

TWLWH

=4.5 and 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V

9,10,11

Address Hold Time

9,10,11

-550 e;:S:TA;:S:+1250e

80

-

Write Enable Pulse
Setup Time

TWLEH

vee

=4.5 and 5.5V

9,10,11

-550 e ;:s:TA;:S: +1250 e

200

-

ns

Early Write Pulse
Setup TIme

TWLEL

vee

=4.5 and 5.5V

9,10,11

-550 e ;:S:.TA;:S:. +1250 e

0

-

ns

Early Write Pulse
Hold Time

TELWH

vee

=4.5 and 5.5V

9,10,11

-550 e;:S:TA;:S:.+1250e

80

-

ns

=4.5 and 5.5V
=4.5 and 5.5V

9,10,11

-550e:S:TA;:S:.+1250e

0

-550 e;:S:.TA;:S:+1250e

0

-

ns

9,10,11

ns
ns

Data Setup Time

TDVWL

vee

Early Write Data
Setup Time

TDVEL

vee

Data Hold Time

TWLDX

vee - 4.5 and 5.5V

9,10,11

-550e;:S:.TA;:S:+1250e

80

-

ns

Early Write Data
Hold Time

TELDX

vee

=4.5 and 5.5V

9,10,11

-550 e;:S:TA;:S:+1250e

80

-

ns

Read or Write
eycleTime

TELEL

vee

=4.5 and 5.5V

9,10,11

-550 e ;:S:TA;:S: +1250 e

420

-

ns

NOTES:

ns

1. All voltages referenced 10 VSS.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: Sns (max); Input and output liming reference lavel: 1.5V; Output load: 1 TTL gate
equivalent, CL - 50pF (min) - for CL greater than 50pF, access time is derated by a.15ns per pF.
3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.
5. TAVQV = TElQV

+ TAVEL

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.
3-60

Specifications HM-6504/883
TABLE 3. HM-6504/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

MAX

UNITS

Input Capacitance

CI

VCC=Open,
f= 1MHz,
All Measurements
Referenced to
Device Ground

4

-550 C :: TA :: + 1250 C

-

8

pF

Output Capacitance

CO

VCC=4.5V,
f=lMHz,
All Measurements
Referenced to
Device Ground

4

-550 C ::TA ~+1250C

-

10

pF

Chip Enable Output
Enable Time

TELOX

VCC = 4.5V and 5.SV

4

-550C~TA~+1250C

5

-

ns

Chip Enable Output
Disable Time

TEHOZ

VCC = 4.SV and 5.SV

4

-550 C ~TA::+1250C

-

100

ns

Write Enable Read
Mode Setup Time

TWHEL

VCC = 4.SV and 5.SV

4

-550 C::;TA::;+1250C

0

-

ns

High Level Output
Voltage

VOH2

VCC = 4.5,
IOH =-100""

4

-550 C ::;TA ~ +12SoC

VCC
-0.4

-

V

NOTES:

SYMBOL

CONDITIONS

NOTE

TEMPERATURE

MIN

1. All voltages referenced to VSS.
2. Input pulse levels: O.8V to VCC-2.oV; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL

= 50pF (min) -

for CL greater than 50pF. access time Is derated by 0.1505 per pF.

3. Typical derating 1.5mNMHz increase in

:E:E
:E

c..>W

4. The parameters listed in Table 3 arB controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

5. TAVQV

> C>

rccop.

= TELQV + TAVEL
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3,8A,8B,10,ll

Group A

Samples/SOO5

l,2,3,7,8A,8B,9,10,11

GroupsC&D

Samples/500S

1,7,9

CAUTION: These devices are sensitive to electroniC discharge. Proper

Ie handling procedures should be followed.
3-61

HM-6504/883
Timing Waveforms
READ CYCLE

THEM

THUIl8)

151
II)

14) moz
VALID DATA OUTPUT

W__

~"~'G~"

________________________________________________

~

__

.

REF~I:EE"CE -----t---t------t--------------+-------------tl---II---t--,
TRUTH TABLE
TIME
REFERENCE

INPUTS

-1
0
1

W

A

Q

FUNCTION

H

X
H
H
H
H
X
H

X
V
X
X
X
X
V

Z
Z

Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as - 1 )
Cycle Ends, Next Cycle Begins (Same as 0)

\....
L
L

2
3

....r

4

H

5

OUTPUT

E

\....

X
V
V

Z
Z

The address information is latched in the on chip registers
on the falling edge of E (T = 0). Minimum address set up
and hold time requirements must be met. After the required
hold time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes

enabled but data is not valid until during time (T. = 2). Vi
must remain high until after time (T = 2). After the output
data has been read, E may return high (T = 3). This will disable the output buffer and all inputs and ready the RAM for
the next memory cycle (T = 4).

EARLY WRITE CYCLE

181

17)
TELEH

TElEl(181

15)

117)

TDVEL
NEXT DATA
HIGH-Z

HIGH-Z

I, I,

TIllE

A£FEIIENC(

TRUTH TABLE
TIME
REFERENCE
-1
0
1
2

3
4

INPUTS
A

E

Vi

H

X
L
X
X
X
L

\....
L

....r
H

\....

X
V
X
X
X
V

OUTPUT

0

Q

FUNCTION

X
V
X
X
X
V

Z
Z
Z
Z
Z
Z

Memory Disabled
Cycle Begins, Addresses are Latched
Write in Progress Internally
Write Completed
Prepare for Next Cycle (Same as - 1)
Cycle Ends, Next Cycle Begins (Same as 0)

The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of
E (T = a), the addresses, the write signal, and the data input
are latched in on chip registers. The logiC value of Vi at the
time E falls determines the state of the output buffer for that
cycle. Since Vii is low when E falls, the output buffer Is
latched into the high impedance state and will remain In that

state until E returns high (T .,; 2). For this cycle, the data input is latched by E going low; therefore data set up and hold
times should be referenced to E. When E (T = 2) returns to
the high state the output buffer and all inputs are disabled
and all signals are unlatched. The device is now ready for
the next cycle.

3-62

HM-6504/883
Timing Waveforms

(Continued)

LATE WRITE CYCLE

TRUTH TABLE
TIME
REFERENCE

E

INPUTS
iii
A

H

X

-1
0
1
2

""""'L

3
4
5

-.r
H
""""'-

X
V
X
X
X
X
V

H

""""'
H

L

H

X
H

OUTPUTS

0

Q

FUNCTION

X
X
V
X
X
X
X

Z
Z

Memory Disabled
Cycle Begins Addresses are Latched
Write Begins, Data is Latched
Write in Progress Internally
Write Completed
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

X
X
X

Z
Z

en >a:
QQ

The late write cycle is a cross between the early write cycle
and the read-modify-write cycle.
Recall that in the early write the output Is guaranteed to
remain high impedance, and in the read-modify-write the
output is guaranteed valid at access time. The late write Is

between these two cases. With this cycle the output may
become active, and may become valid data, or may remain
active but undefined. Valid data Is written Into the RAM if.
data setup, data hold, write setup and write pulse widths are
observed.

Test Load Circuit

1--------------'
1
1
1

OUT

0-""-+-<

1.SV

'TEST HEAD

1

CAPAcrrANcE 1

EQUIVAlENT CIRCUIT

3-63

::;:::;:
::;:

U W

·HM-6504/883

Burn-In Circuit
HM-6504/883 CERAMIC DIP

VCC C1

E

F3
F4

Fg

F5

F10

Fe

F11

F7

F12

Fa

F13

F2

F14
F2

F1

GND

FO

NOTES:

All Resistors 47k ± 5%
FO = 100kHz ± 10%
F1= FO + 2, F2 = F1 + 2, F3 = F2 + 2 ••• F12 = F" + 2
VCC = 5.5V ± 0.5V
VIH = 4.5V ± 10%
VIL = -0.2V to +0.4V
C1 = 0.01 pF Min.

3-64

¢

HM-6504/883
Die Characteristics
DIE DIMENSIONS:
136 x 169 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 11 k.8. ± 2k.8.
GLASSIVATION:
Type: Si02
Thickness: ak.8. ± 1k.8.
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
WORST CASE CURRENT DENSITY:
1.79 x 105 Ncm 2

Metallization Mask Layout
HM-6504/883

vee

AO

AS
A7
A8

>-

Cl)1C
C> C>

====
==

'-'Ow

A9

Al0
All

NOTE: Pin Numbers Correspond to DIP Package Only.

3-65

HM-6504/883
Packaging t
18 PIN CERAMIC DIP
.882
.005 MIN

I

~

'OOjM::: t

.915

~========~
o·

.125
.180

15·
.100
BSC

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic. 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 1QoC
Method: Furnace Seal

NOTE: All Djmensions are

.M!!!... . Dimensions are in inches.

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-6

t MiI-M-38510 Compliant Materials, Finishes, and Dimensions.

Max

3-66

mHARRIS

HM-6514/883
1024

June 1989

X

4 CMOS RAM

Pinout

Features
• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.

HMl-6Sl4/883 (CERAMIC DIP)
TOP VIEW

• Low Power Standby ......•........•........•....••••.•. 125f1W Max.
A6

VCC

• Data Retention ......................................... @ 2.0V Min.

AS

A7

• TTL Compatible Input/Output

A4

AS

A3

A9

• Low Power Operation ............•.............••• 35mW/MHz Max.

• Common Data Input/Output
• Three-State Output
• Standard JEDEC Pinout

AO

DQO

• Fast Access Time .... , .............................. 120/200ns Max.

Al

DQl

A2

DQ2

E

DQ3

• 18 Pin Package for High Density
• On-Chip Address Register
• Gated Inputs - No Pull Up or Pull Down Resistors Required

GND

Description

W

The HM-6514/883 is a 1024 x 4 static CMOS RAM fabricated using selfaligned silicon gate technology. The device utilizes synchronous circuitry to
achieve high performance and low power operation.

>-

enD:
00

::;:::;:
::;:

...,w

On chip latches are provided for addresses allowing efficient interfacing with
microprocessor systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.

PIN

DESCRIPTION

A

Address Input

Gated inputs allow lower operating current and also eliminates the need for
pull-up or pull-down resistors. The HM-6514/883 is a fully static RAM and
may be maintained in any state for an indefinite period of time.

W

Write Enable

D

Data Input

Data retention supply voltage and supply current are guaranteed over
temperature.

Q

Data Output

-E

Chip Enable

Functional Diagram
LSB A9 - - - - " . -...
AB-

A7AB-

A5A4-~L--"'--""

GATED
ROW
DECODER

LSB A2 _-lL--"'--'"
AlAOA3 _-1'-'1""'....

64.64
MATRIX

64

GATED COLUMN
I/O SELECT

G

4

10F4

.--z:.......L..-'-_DQ

L

Copyright © Harris Corporation 1989

3-67

Specifications HM-6514S/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••••••••••••••••.••••••••••••••••••••••• +7.0V
Input, Output or 110 Voltage Applied. • • •• GND-0.3V to VCC+0.3V
Storage Temperature Range ••••.•••••••••••• -650 C to +1500 C
Junction Temperature ••••.••••••••••••••••••••••••••• +1750 C
Lead Temperature (Soldering 10 sec) •••••••••••••••••••• 3000 C
ESD Classification •••••••••••••.••••••••••••• '••••••••• Class 1

Thermal Resistance
Sja
Sjc
Ceramic DIP Package... .••• ••• ••• •••.••• 660C/W 120C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ............................. 0.75 Wall
Gate Count ...................................... 6910 Gates

CAUTION: Stresses above those listed in "Absolute MBJCimum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operalional sections of this specification is not implied.

Operating Conditions
Operating Voltage Range •.•••••.•••.••••••.•••• +4.5V to +5.5V
Operating Temperature Range ............... -550C to +1250 C

Input low Voltage ................................. ov to +0.8V
Input High Voltage .......................... VCC-2.0V to VCC
Input Rise and Fall Time ............................. 40ns max

TABLE 1. HM-6514S/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC=4.5V
IOL=3.2mA

1,2,3

-550C ~TA~ +1.25 0C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
IOH=-1.0mA

1,2,3

-550 C ::>TA~ +1250 C

2.4

-

V

VCC= 5.5V,
VI = GND orVCC

1,2,3

-550C~TA:S.+1250C

-1.0

+1.0

pA

VCC = 5.5 V,
VIO= GND or VCC

1,2,3

-550C::>TA~+1250C

-1.0

+1.0

pA

Input Leakage Current

II

Inpul/Output Leakage
Current

1I0Z

Data Retention Supply
Current

ICCDR

VCC= 2.0V,
E=VCC-O.3V
10=OmA

1,2,3

-550C~TA~+1250C

-

25

pA

Operating Supply
Current

ICCOP

ycc = 5.5V, (Note 3)

1,2,3

-550C~TA~+1250C

-

7

mA

Standby Supply
Current

ICCSB

1,2,3

-550 C ::>TA:> +1250C

-

50

pA

NOTES:

E=1MHz
y'CC=5.5V,
E = VCC-0.3V,
10 = OmA

1. All voltages referenced to device GND.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.SV Output load: 1 TTL gate

equivalent. CL = SOpF (min) - for CL greater than SOpF. access lime is derated by O.ISns per pF.
3. Typical derating SmA/MHz increase in ICCOP.

4. The parameters listed In Table 3 are controlled via design ar process parameters are characterized upon Inilial design and after major process
and/or deSign changes.

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.

3-68

Specifications HM-6574S/883
TABLE 2. HM-6514S/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS

SYMBOL

(NOTES1,2)
CONDITIONS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

ehip Enable Access
Time

TELQV

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

-

120

ns

Address Access Time

TAVQV

vee = 4.5 and 5.5V
Nole5

9,10,11

-55 0 e ~TA~ +125 0 e

-

120

ns

ehip Enable Pulse
Negative Width

TELEH

vee = 4.5 and 5.5V

9,10,11

-550e~TA~ +125 0 e

120

-

ns

ehip Enable Pulse
Positive Width

TEHEL

vee = 4.5 and 5.5V

9,10,11

-550e~TA~ +125 0 e

50

-

ns

PARAMETER

Address Setup Time

TAVEL

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

0

TELAX

vee = 4.5 and 5.5V

9,10,11

-550e~TA.5,+1250e

40

-

ns

Address Hold Time
Write Enable Pulse
Width

TWLWH

vee = 4.5 and 5.5V

9,10,11

-550e.5,TA~+1250e

120

-

ns

Write Enable Pulse
Setup Time

TWLEH

vee = 4.5 and 5.5V

9,10,11

-55 0 e ~TA~ +125 0 e

120

-

ns

Write Enable Pulse
Hold Time

TELWH

vee = 4.5 and 5.5V

9,10,11

-550e.5,TA~ +1250 e

120

-

ns

ns

Data Setup Time

TDVWH

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

50

-

ns

Data Hold Time

TWHDX

vee = 4.5 and 5.5V

9,10,11

-550e.5,TA~ +125 0 e

0

-

ns

Write Data
Delay Time

TWLDV

vee = 4.5 and 5.5V

9,10,11

-550 e.5,TA.5,+1250e

70

-

ns

Early Output
High-ZTime

TWLEL

vee = 4.5 and 5.5V

9,10,11

-55 0 e.5,TA.5, +1250 e

0

-

ns

Late Output
High-ZTime

TEHWH

vee = 4.5 and 5.5V

9,10,11

-550e~TA~ +125 0 e

0

-

ns

Read or Write
eycleTime

TELEL

vee = 4.5 and 5.5V

9,10,11

-550e~TA~+1250e

170

-

ns

",,,,>00

NOTES:

1. All voltages referenced to device GND.

2. Input pulse levels: O.SV to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for Cl greater than 50pF. access time is derated by 0.15ns per pF.
3. Typical derating SmA/MHz increase in

lecop.

4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.
5. TAVQV = TELQV

+ TAVEL.

CAUTION: These devices are sensitive to electroniC discharge. Proper

Ie

handling procedures should be followed.

3-69

====
==

<.>w

Spe,:ifications HM-6514S/883
TABLE 3. HM-6514S/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

Input Capacitance

InpuVOutput
Capacitance

CONDITIONS

NOTE

TEMPERATURE

MIN

MAX

UNITS

-

8

pF

CI

VCC = Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

CIO

VCC = Open,
f= 1 MHz,
All Measurements
Referenced to
Device Ground

4

TA=+250 C

-

10

pF

Chip Enable Output
Enable Time

TElOX

VCC = 4.SV and 5.SV

4

-SSOC.s:TA.s:+12S 0 C

S

-

ns

Chip Enable Output
Disable lime

TEHOZ

VCC = 4.SV and S.SV

4

-SSOC.s:TA.s:+12S 0 C

-

SO

ns

VCC= 4.SV,

4

-SSOC.s:TA.s: +12S o C

VCC
-0.4

-

V

High level Output
Voltage
NOTES:

VOH2

IO=-100~A

1. All voltages referenced to device GND.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
equivalent, CL = 50pF (min) - for Cl greater than 50pF, access time Is derated by 0.15n8 psr pF.

1 TTL gate

3. Typical derating SmA/MHz increase in ICCOP.
4. The parameters listed In Table 3 are controlled via design or process parameters are characterized upon Initial design and after major process
and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/S004

-

Interim Test

100%/5004

1,7,9

PDA

100%/S004

1

Final Test

100%/S004

2,3,BA,BB,10,11

Group A

Samples/SOOS

1,2,3,7, BA, BB, 9,10,11

GroupsC&D

Samples/SOOS

1,7,9

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-70

Specifications HM-6514B/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •.•••••••.•••••.••••••••••.••••••.••.••• +7.0V
Input, Output or I/O Voltage Applied. • • •• GND-O.3V to VCC+O.3V
Storage Temperature Range •••.•••••••••..•• -650C to +150 0C
Junction Temperature •••••••••.••••••••••.••••••• : •.• +175 0C
Lead Temperature (Soldering 10 sec) ••••.••.•••.•.••••• +300 0C

Thermal Resistance
Bja
Bjc
Ceramic DIP Package.. ••. •• ••• •••••••• .• 660 C/W 120C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ••••.••••••.•••.••.•••••••••• 0.75 Wall
Gate Count ••••.•••••.••••.•••••••••••••••••••••. 6910 Gates

CAUTION: Stresses above those listed;n ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
01 the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range •••.••.•••••••.••.••••• +4.5V to +5.5V
Operating Temperature Range •..•...••.••... -550C to +125 0C

Input Low Voltage •.••••••••••••• '••.•••••••••••.•.• OV to +0.8V
Input High Voltage ...... '.................... VCC-2.0V to VCC

TABLE 1. HM-6514B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC=4.5V
IOL=3.2mA

1,2,3

-550C ~TA~ +125 0C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V
10H=-1.OmA

1,2,3

-550C~TA~+1250C

2.4

-

V

VCC= 5.5V,
VI = GND orVCC

1,2,3

-550C ~ TA ~ +1250 C

-1.0

+1.0

IlA

VCC = 5.5 V,
VIO=GNDorVCC

',2,3

-550C~TA~+1250C

-1.0

+1.0

JlA

Input Leakage Current

n

InpuVOutput Leakage
Current

noz·
ICCDR

VCC= 2.0V,
E = VCC, 10 = OmA

1,2,3

-550C~TA~ +125 0C

-

25

IlA

Operating Supply
Current

ICCOP

VCC = 5.5V; (Note 3)
1=1 MHz

1,2,3

-550C~TA~+1250C

-

7

mA

Standby Supply
Current

ICCSB

VCC= 5.5V,

1,2,3

-550C~TA~+1250C

-

50

IlA

10=OmA
NOTES:

1. All vollage. reterenced to device GND.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and o~tput timing reference level: 1.SV Output load: 1 TTL gate
equivalent. CL = 50pF (min) - for CL greater than 50pF, access time Is derated by 0.15ns per pF.
3. Typical derating 1.5mA/MHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
. '
and/or design changes.

CAUTION: These devices are sensitive to electroniC discharge. Proper IC handling procedures should be followed.

3-71

00

====
==

~w

Data Retention Supply
Current

E= VCC-0.3V,

>",a:

Specifications HM-6514B/883
TABLE 2. HM-6514B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

LIMITS

G'ROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.5V

9,10,11

-550e.=>TA'=> +1250e

-

200

ns

(NOTES 1,2)
CONDITIONS

Chip Enable Access
'Time

TELQV

vee

Address Access Time

TAVQV

vee 4.5 and 5.5V
Note 5

=

9,10,11

-550e.=>TA~+1250e

-

220

ns

Chip E!,able Pulse
Negative Width

TELEH

vee

=4.5 and 5.5V,

9,10,11

-55 0e.=>TA'=> +125 0e

200

-

ns

Chip Enable Pulse
Positive Width

TEHEL

vee

=4.5 and 5.5V

9,10,11

-550 e.=>TA.=>+1250e

90

-

ns
ns

Address Setup Time

TAVEL

vee

-550e.=>TA.=>+1250e

20

TELAX

vee

9,10,11

-550e.=>TA.=>+1250e

50

-

Write Enable Pulse
Width

TWLWH

=4.5 end 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V

9,10,11

Address Hold Time

9,10,11

-550e.=>TA.=>+1250e

'200

-

ns

Write Enable Pulse
Setup Time

TWLEH

vee

=4.5 and 5.5V

9,10,11

-55°C.=> TA5. +1250 e

200

-

ns

Write Enable Pulse
Hold Time

TELWH

vee

=4;5 and 5.5V

9,10,11

-550e.=>TA.=>+1250e

200

-

ns

Data Setup Time

TDVWH

' vee

-550e.=>TA5.+1250e

120

vee

9,10,11

-550e.=>TA'=> +1250e

0

-

ns

TWHDX

Write Data
Delay Time

TWLDV,

=4.5 and 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V

9,10,11

Data Hold Time

9,10,11

-550e.=>TA5.+1250e

80

-

ns

Early Output
High-ZTime

TWLEL

, vee

=4.5 and 5.5V

9,10,11

-550e.=>TA~ +1250 e

0

-

ns

Late Output
High-ZTime

TEHWH

vee

=4.5 and 5.5V

9,10,11

-550 e.s TA 5. +1250 e

0

-

ns

Read or Write
Cycle Time

TELEL

vee

=4.5 and 5.5V

9,10,11

-550 e.=> TA 5.+1250e

290

-

ns

NOTES:

ns

ns

I. All voltages referenced to device GND.
2. Input pulse levels: O.BV to VCC-2.oV; Input rise and fall time.: 5n. (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (mIn) - for CL greater than 50pF. access time is derated by 0.15ns per pF. .
3. Typical derating SmAIMHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.
.
,
5. TAVQV = TElQV

+ TAVEL

CAUTtON: Thase devices are sensitive to etactro~lc discharge. Proper IC handling procedures should be followed.

3-72

Specifications HM-65148/883
TABLE 3. HM-6514B/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

NOTE

TEMPERATURE

MIN

MAX

UNITS

CI

VCC=Open.
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+2S0C

-

8

pF

CIO

VCC=Open,
f=1MHz,
All Measurements
Referenced to
Device Ground

4

TA=+2S0C

-

10

pF

Input Capacitance

InpuVOutput
Capacitance

CONDITIONS

Chip Enable Output
Enable Time

TELQX

VCC = 4.5V and S.SV

4

-SSoC,:;;TA':;; +12S oC

S

-

ns

Chip Enable Output
Disable TIme

TEHQZ

VCC = 4.SV and S.SV

4

-SSOC,:;;TA':;; +12So C

-

80

ns

VCC=4.5V,
IO=-100pA

4

-SSOC,:;;TA,:;;+12S0C

VCC
-0.4

-

V

High Level Output
Voltage
NOTES:

VOHZ

1. All voltages referenced to devica GND.
2. Input pulse levels: O.BV to VCC-2.0V; Input rise and fall times: 50S (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF. access tima is derated by 0.1505 per pF.

3. Typical derating 1.5mNMHz increase in ICCOP.
4. The parameters listed In Table 3 are controlled via design or process parameters are characterized upon Initial design and after major process

>-

",lC

and/or design changes.

00

::::::
u'"
:::

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/S004

-

Interim Test

100%/S004

1,7,9

PDA

100%/S004

1

Final Test

100%/S004

2,3,8A,8B,10,11

Group A

Samples/SOOS

1,2,3,7,8A,8B,9,10,11

GroupsC&D

Samples/SOOS

1,7,9

CAUTION: Thesa devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-73'

Specifications HM-6514/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••••••••••••••••••.•••••••.••.• +7.0V
Input,.Output or I/O Voltage Applied •... GND-0.3Vto VCC+0.03V
Storage Temperature Range •.•..••.••••••••• -650C to +1500C
Junction Temperature •.•••••.•.•••.•••••••••••••••••• +1750C
Lead Temperature (Soldering 10 sec) •••.•..•.••.••••.•• +3000C

Thermal Resistance
aja
ajc
Ceramic DIP Package... •• .• . .. •• ••. ••••• 66 0C/W 12 0 C/W
0
Maximum Package Power Dissipation at +125 C
Ceramic DIP Package .••••••••.•.••.•.•••.•••••••• 0.75 Watt
Gate Count •..••••••.•....•••••....•.••••.••••... 6910 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification ;s not implied.

Operating Conditions
Operating Voltage Range ••••••••.•••••••.•••••• +4.5V to +5.5V
Operating Temperature Range .••••••••••.•.• -550C to +125 0C

InputLowVoltiig~ •.•.••••••••••••.••••••••.••••..• OVto +0.8V
Input High Voltage •••.•.•.....••••......•••• VCC-2.0V to VCC

TABLE 1. HM-6514/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Output Low Voltage

VOL

VCC=4.5V
10=3.2mA

1,2,3

-550 CSTAS+1250 C

-

0.4

V

Output High Voltage

VOH

VCC=4.5V

1,2,3

-550 CSTA:s.+1250 C

2.4

-

V

VCC= 5.5V,
VI = GND orVCC

1,2,3

-550 C STA:s. +1250 C

-1,0

+1.0

fJJ\

VCC=5.5V,
VIO = GND orVCC

1,2,3

-550 CSTAS+1250 C

'-1.0

+1.0

fJJ\

VCC= 2.0V,

1,2,3

-550CSTAS+1250C

-

25

fJJ\

VCC = 5.5V, (Note 2),
f=1MHz

1,2,3

-550 C STAS +1250 C

-

7

mA

VCC= 5.5V,

1,2,3

-55 0CSTAS+1250 C

-

50

fJJ\

10=~1.0mA

Input Leakage Current

II

InpuVOutput Leakage
Current

IJOZ

Data Retention Supply
Current

ICCDR

E= VCC-0.3V,
10=OmA

Operating Supply
Current

ICCOP

Standby Supply
Current

ICCSB

E= VCC-0.3V, .
10=OmA

NOTES:

1. All voltages referenced to device GND.
2. Input pulse levels: O.BV to VCC-2.0V; Input rise and fall limes: 5ns (max); Input and aulpulliming reference Jevel: 1.5V; Output load: 1 TTL gale
equivalent. CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15n5 per pF.

3. Typical derating 1.5mNMHz Increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be fOllowed.

3-74

Specifications HM-6514/883
TABLE 2. HM-6514/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Chip Enable Access
Time

TELQV

vee

= 4.5 and 5.5V

9,10,11

-550 e.::;TA'::; +125 0 e

-

300

ns

Address Access Time

TAVQV

vee = 4.5 and 5.5V
Note 5

9,10,11

-55 0 e.::;TA.::;+1250e

-

320

ns

Chip Enable Pulse
Negative Width

TELEH

vee

= 4.5 and 5.5V

9,10,11

-55 0 e.::;TA'::; +125 0 e

300

-

ns

Chip Enable Pulse
Positive Width

TEHEL

vee

= 4.5 and 5.5V

9,10,11

-55 0 e.::;TA'::; +125 0 e

120

-

ns
ns

Address Setup Time

TAVEL

vee

-55 0 e.::;TA'::;+1250e

20

TELAX

vee

9,10,11

-55 0 e.::;TA'::;+1250e

50

Write Enable Pulse
Width

TWLWH

= 4.5 and 5.5V
= 4.5 and 5.5V
vee = 4.5 and 5.5V

9,10,11

Address Hold Time

9,10,11

-55 0 e.::;TA'::; +125 0 e

300

-

Write Enable Pulse
Setup Time

TWlEH

vee = 4.5 and 5.5V

9,10,11

-550C.::; TA'::; +125 0 e

300

-

ns

Write Enable Pulse
Hold Time

TElWH

vee

= 4.5 and 5.5V

9,10,11

-55 0 e.::;TA'::; +125 0 e

300

-

ns

Data Setup Time

TDVWH

vee

-55 0 e.::;TA'::; +125 0 e

200

vee

9,10,11

-550 e.::;TA'::; +125 0 e

0

Write Data
Delay Time

TWlDV

9,10,11

-55 0 e.::;TA'::; +1250 e

100

-

ns

TWHDX

= 4.5 and 5.5V
= 4.5 and 5.5V
vee = 4.5 and 5.5V

9,10,11

Data Hold Time

Early Output
High-ZTime

TWlEl

vee

= 4.5 and 5.5V

9,10,11

-550 e.::;TA'::; +125 0 e

0

-

ns

late Output
High-ZTime

TEHWH

vee

= 4.5 and 5.5V

9,10,11

-55 0 e.::;TA'::; +1250 e

0

-

ns

Read or Write
eycleTime

TElEl

vee = 4.5 and 5.5V

9,10,11

-550 e.::;TA'::; +1250 e

420

-

ns

NOTES:

ns
ns

ns
ns

1. All voltages referenced to device GND.
2. Input pulse levels: O.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15n5 per pF.

3. Typical derating 1.5mA/MHz increase in ICCOP.
4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
andlor design changes.
5. TAVQV

~

TELQV

+ TAVEL

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.

3-75

>",a:
00
:E:E
c.:>W
:E

Specifications HM-6514/883
TABLE- 3. HM-6514/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

NOTE

TEMPERATURE

MIN

MAX

UNITS
pF

CI

VCy = Open,
f=lMHz,
All Measurements
Referenced to
Device Ground

4

TA=+2S0C

-

8

CIO

VCC=4.5V,
f=-lMHz,
All Measurements
Referenced to
Device Ground

4

TA=+2SoC

-

10

pF

Input Capacitance

InpuVOutput
Capacilance

CONDITIONS

Chip Enable Oulput
Enable Time

TELOX

VCC = 4.5V and S.SV

4

-SSOC.!>TA.!>+12S0C

-S

-

ns

Chip Enable Output
Disable Tome

TEHOZ

VCC = 4.SV and S.SV

4

-SSOC.!>TA.!>+12S0C

-

100

ns

VCC=4.S,
IO=-100(IA

4

-SSOC.!>TA5. +12So C

VCC
-0.4

-

V

High Level Output
Voltage
NOTES:

VOHZ

1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.oV; Input rise and fall times: 5ns (max); Input and outputtlmlng reference level: I.5V; Output load: 1 TTL gate
equivalent, CL = 50p~ (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. Typical derating 5mA/MHz increase in (CCOP.

4. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process
andlor design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

IniHalTest

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/S004

1

Final Test

100%/5004

2,3,8A,8B,10,ll

Group A

Samples/SOOS

1,2,3,7, 8A, 8B, 9, 10, 11

GroupsC&D

Samples/SOOS

1,7,9

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.

3-76

HM-6514/883
Timing Waveforms
READ CYCLE

w---------------------------------------------------t t

3

•

TRUTH TABLE

TIME
REFERENCE
-1
0
1

2
3
4
5

INPUTS

E

W

A

H

X

X

\....

H

V

L
L

....r

H
H
H

H

X

X
X
X
X

\....

H

V

DATA 110
DQ

X
V
V

Z
Z

The address information is latched in the on chip registers
on the falling edge of E (T = 0). Minimum address set up
and hold time requirements must be met. After the required
hold time, the addresses may change state without affecting
device operation. During time (T
1) the output becomes

=

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as - 1)
Cycle Ends, Next Cycle Begins (Same as 0)

Z
Z

enabled but data is not valid until during time (T = 2). W
must remain high throughout the read cycle. After the output data has been read, E may return high (T = 3). This will
disable the output buffer and all inputs and ready the RAM
for the next memory cycle (T = 4).

3-77

HM-6514/883
Timing Waveforms

(Continued)

-:\TEVEL

...:::=t~AVEL-l-TELA~

WRITE CYCLE

NEXT ADD

VALIOADD

TElH

~EHEl

-

w

rnWl

TWLEH

TWlWH

-

I--

TWHEH

: - - TWlDV-t

HIGHZ

DO

-

~I

TEHEl

THEH

HIGHZ

VALID DATA INPUT

_~TOVWH_

TWHDZ

TElWH

;~~~R~---1I-----+---------lt--!---I---+
TRUTH TABLE
TIME
REFERENCE

E

W

A

DQ

-1

H

0

"""'L

X
X
L

X
V
X
X
X
X
V

Z
Z
Z
V
Z
Z
Z

1

INPUTS

L
L

2
3
4
5

-H'
"""'L

-H'
X
X

Write Period Begins

Data In is Written
Write Completed
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

The write cycle is initiated by the falling edge of E (T = 0),
which 'latches the address information in the on-chip registers. There are two basic types of write cycles, which differ
in the control of the common data-in/data-out bus.
Case 1:

E falls before Wfalls

The output buffers may become enabled (reading) if E falls
before Wfalls. Wis used to disable (three-state) the outputs
so input data can be applied. TWLDV must be met to allow
the Wsignal time to disable the outputs before applying input data. Also, at the end of the cycle the outputs may become active if Wrises before E. The RAM outputs and all inputs will three-state after E rises (TEHQZ). In this type of
write cycle TWLEL and TEHWH may be ignored.
Case 2:

E falls equal to or after Wfalls,
before or equal to W rising

and

E rises

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched

This E and Wcontrol timing will guarantee that the data outputs will stay disabled throughout the cycle, thus simplifying the data input timing. TWLEL and TEHWH must be met,
but TWLDV becomes meaningless and can be ignored. In
this cycle TDVWH and TWHDX become TDVEH and
TEHDX. In other words, reference data setup and hold times
to the E rising edge.
OBSERVE

IF
E falls before W

TWLDV

TWLEL

Case 2

E falls after Wand
E rises before W

TWLEL
TEHWH

TWLDV
TWHDX

If a series of consecutive write cycles are to be performed,
be held low until all desired locations have been
written (an' extension of Case 2).

W may

Test Load Circuit

1- - - - - - - - - - - -

--I

1

1

1

1

1

1

DUT O-+--+-4l

1

1

1

15V
1

"'TEST HEAD
CAPACITANCE

IGNORE

Case 1

-

IOL

1
1

1

1

1

_ _ _ _EQUIVALENT
_ _ _ _ CIRCUIT
_ _ _ _ _ _ J1

3-78

HM-6514/883

Burn-In Circuit
HM-6514/883 CERAMIC DIP

vee
F9

A6

Fa

AS

F10

F7

A4

F11

F6

A3

F12

F3

AO

F4

A1

Fs

A2

FO

E

~

F2

GND

F1

,..

",a:
c:>C:>
:E:E
U W

:E

NOTES:
All Resistors 47kO ± 5%
FO = 100kHz ± 10%
F1= FO + 2, F2 = F1 + 2, F3 = F2 + 2 • • • F12 = F11 + 2
VCC = 5.5V ± 0.5V
VIH = 4.SV ± 10,*,
VIL = -0.2V to +0.4V
C1

a

0.01 pF Min.

3-79

HM-6514/883
Die Characteristics
DIE DIMENSIONS:
136 x 167 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 11 kA ± 2kA
GLASSIVATION:
Type: Si02
Thickness: akA ± 1kA
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600C (Max)
WORST CASE CURRENT DENSITY:
1.79 x'10 5 A/cm 2
LEAD TEMPERATURE (10 seconds soldering):
300°C

Metallization Mask Layout
HM-6514/883
AS

vee

A6

A7

AS
A9

000
001
002

E

GND

iii

003

NOTE: Pin Numbers Correspond to DIP Package Only.

3-80

HM-6514/883
Packaging t
18 PIN CERAMIC DIP
.882
.005 MIN

t

~

'''T:~:t

.915

~========~
o·
is'

.125
.180

.100
BSC

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± lOoC
Method: Furnace Seal

NOTE: All Dimensions are

~
Max

• Dimensions are in inches.

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
• SOLDER FINISH

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-6

tMiI-M-38510 Compliant Materials. Finishes, and Dimensions.

3-81

Ell HARRIS

HM-6516/883
2K

June 1989

Features

X

8 CMOS RAM

Pinouts
HM1-6516/883 (CERAMIC DIP)
TOP VIEW

• This Circuit is Processed in Accordance to Mil-Std-SS3 and is Fully
Conformant Under the
.
, Provisions of Paragraph 1.2.1. .
• Low Power Standby ••••••••••••••••••••••••••••••••••• 27511W Max.
• Low Power Operation ••••••••••••••••••••••••••••• 55mW/MHz Max.
• Fast Access ••••••••••.••••••••••••••••••••••••••••• 120/200ns Max.

-----'---. r-----,

A7

VCC

A6

A8

A5

A9

• Single Supply ••••••••••••••••••••••••••••••••••••••••• 5.0 Volt VCC

A4

W

• TTL Compatible

A3

G

• Static Memory Cells

A2

A10

• High Output Drive

A1

E

AO

007

• Industry Standard Pinout

• On-Chip Address Latches
• Easy Microprocessor Interfacing

Description
The HM-6516/883 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MaS
design techniques. This low power is further enhanced by the use of synchronous circuit techniques that keep the active (operating) power low, which also
gives fast access times. The pinout of the HM-6516/883 is the popular 24 pin,
8-bit wide JEDEC standard which allows easy memory board layouts, flexible
enough to accomodate a variety of PROMs, RAMS, EPROMs, and ROMs.
The HM-6516/883 is ideally suited for use in microprocessor based systems.
The byte wide organization simplifies the memory array deSign, and keeps
operating power down to a minimum because only one device is enabled at a
time. The address latches allow very simple interfacing to recent generation
microprocessors which employ a multiplexed address/data bus. The convenient output enable control also simplifies multiplexed bus interfacing by
allowing the data outputs to be controlled independent of the chip enable.

000

000

001

DOS

D02

DQ4

GND

DQ3

HM4-6516/883 (CERAMIC LCC)
TOP VIEW

-ow L~J

A6

!!J

A5

~l

A4

~J

A3
A2

Functional Diagram

....

L~': L~J

L!J ~2j L~1J L~ .. _

L~

AS

[~

A9

..-L~

~]
~]

NC

Vi
G

A1

19

A10

AO

1j]

E
D07

DOO

DOS

DQO

lllAU
DQ7

PIN

DESCRIPTION

NC

No Connect
Address Inputs
Chip Enable/Power Down
Ground
Data In/Data Out
Power (+SV)
Write Enable
Output Enable

AO-A1O
A3

A2

A1

E

AD

VSslGND
DOO-D0 7
VCC

W
G
Copyright @) Harris CorPoration 1989
. '

, >

•

3-82

Specifications HM-6516/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ........................................ +7.0V
Input or Output Voltage Applied for all grades .••.•. GND-0.3V to
Vee+0.3V
Storage Temperature Range •.•.•••.•.••.••.• -650C to +150 0 C
Junction Temperature ................•............... + 1750C
Lead Temperature (Soldering 10 sec) ....•....•.....••.. +300 0 C
ESD Classification ••...•.•.•.•.•••.•.•••••.••.•..••... Class 1

Thermal Resistance
0ja
Ceramic DIP Package.. ••. . . . •. •.• •
48 0 C/W
Ceramic LCC Package. • . . . . . . . • . • .
660 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ..........•.....•.•..•.•.......... I W
Ceramic LCC Package •.•......•...................•. 0.75W
Gate Count •.•.•.•..•..•.•.•.••................. 25953 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification ;s not implied.

Operating Conditions
Operating Temperature Range ..•.•.•.••..•.• -550C to +125 0 C
Operating Supply Voltage ..•..•.....•.••.••.•.....• 4.5V to 5.5V
tnput Low Voltage ...............••.......•.•..•..•. 0 to +0.8V

Input High Voltage ....•..•..•..................• +2.4V to VCC
Data Retention Supply Voltage .•.••...............• 2.0V to 4.5V
Input Rise and Fall Time ..•.••.•.•.••..•............. 40ns Max

TABLE I. HM-6S16/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested.

D.C. PARAMETERS

SYMBOL

vee =. 5.0V ± 10% Unless Otherwise Specified
LtMITS

(NOTE I)
CONDITIONS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=- 4.5V,10 = -1.0mA

1,2,3

-550e~TA~+1250C

2.4

-

V

High Level
Output Voltage

VOH

VCC

Low Level
Output Voltage

VOL

VCC = 4.5V,10 = 3.2mA

1,2,3

-550C~TA~+1250C

-

0.4

V

High Impedance
Output Leakage
Current

IIOZ

vce = G = 5.5V,
VIO=GNDorVCC

1,2,3

-550C~TA~+1250C

-1.0

1.0

~A

VCC = 5.5V, VI = GND orVCC

1,2,3

-550C:5,TA5+1250C

-1.0

1.0

~A

VCC = G = 5.5\1, (Note 2),
f= IMHz, VI= GNDorVCC

1,2,3

-550C~TA~+1250C

-

10

mA

VCC = 5.5V,

1,2,3

-55°C :5.TA =". +1250 C

-

100

~A

1,2,3

-55 0 C:5,TA:5,+1250C

-

50

~A

VCC = 2.0V,
HM-6516/883
E = VCC -0.3V,10 = OmA
VI =GNDorVCC

1,2,3

-550 C:5,TA=".+1250C

-

50

~

VCC = 2.0V,

1,2,3

-550 C,S,TA::;: +1250 e

-

25

~A

7,8A,88

-550C::;:TA:5.+1250C

-

-

Input Leakage
Current

II

Operating Supply
Current

ICCOP

Standby Supply
Current

ICCS81

>",a:

HM-6516/883

VI = GND orVeC
HM-65168/883

E = VCC -0.3V,10 = OmA
VI = GND orVCe
Data Retention
Supply Current

ICCDR

HM-65168/883

E = VCC -0.3V, 10 = OmA
VI=GNDorVeC
Functional Test

FT

:E:E
:E

<..:I W

E = VCC -0.3V,10 = OmA
VCC = 5.5V,

00

vec = 4.5V (Note 4)

CAUTION: These devices are sensitive to electrostatic discharge. Proper Ie handling procedures should be followed.

3-83

Specifications HM-6516/883
TABLE 2. HM-6516/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
vce = 5.0V ± 10% Unless Otherwise Specified

Devices Guaranteed and 100% Tested.
D.C.
PARAMETERS

(NOTES 1,5)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

vee = 4.5V and 5.5V HM-6516/883

9,10,11

-550 e.::; TA~ +125 0 e

280

-

ns

vee = 4.5Vand 5.5V HM-6516B/883

9,10,11

-550e~TA~+1250e

170

-

ns

9,10,11

-550 e ~ TA~ +1250 e

200

ns

9,10,11

-550 e ~TA'::; +125 0 e

120

ns

200

ns

120

ns

-

ns

-

ns

SYMBOL

Read/Writel
eycleTime

TELEL

Address Access
Time

TAVQV
(Note 6)

vee = 4.5V and 5.5V HM-6516/883

ehip Enable
Access Time

TELQV

vee = 4.5V and 5.5V HM-6516/883

9,10,11

-550 e .::;TA'::; +125 0 e

VCC = 4.5V and 5.5V HM-6516B/883

9,10,11

-550C  50pF, CL < 300pF, access time are derated by O.1Sns/pF.
6. TAVQV = TELQV

+ TAVEL.

3-84

= 1.SV; output load = CL > 50pF and 1 TTL
-

Specifications HM-6516/883
TABLE 3. HM-6516/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
(NOTE 1)
PARAMETERS
Input
Capacitance

InpuVOutput
Capacitance

CI

CliO

LIMITS
NOTES

TEMPERATURE

MIN

MAX

UNITS

VCC=Open
TA =+25 0C,f= lMHz,
All Measurements Referenced
to Device GND

1,2

TA =+250C

-

8

pF

VCC = Open
TA = +250 C,f= lMHz,
All Measurements Referenced
to Device GND

1,3

TA=+250C

-

12

pF

VCC = Open
TA = +250 C,f= lMHz,
All Measurements Referenced
to Device GND

1,2

TA =+250C

-

10

pF

VCC=Open
TA = +250C,f= lMHz
All Measurements Referenced
to Device GND

1,3

TA =+250C

-

14

pF

SYMBOL

CONDITIONS

Output Enable
To Output
Valid Time

TGLOX

vee = 4.5V and 5.5V

1

-550e~TA~+1250C

10

-

ns

Chip Enable
To Output
Valid Time

TELQX

vee = 4.5V and 5.5V

1

-550e~TA~+1250e

10

-

ns

Chip Enable
Output Disable
Time

TEHOZ

vee = 4.5V and 5.5V HM-6516/883

1

-550e~TA~+1250e

-

80

ns

vee = 4.5V and 5.5V HM-6516B/883

1

-550e~TA~+1250e

ns

TGHOZ

vee = 4.5Vand 5.5V HM-6516/883

1

-550e~TA~+1250e

-

50

Output Disable
Time

80

ns

vee = 4.5V and 5.5V HM-6516B/883

1

-ssoe ~TA~ +12Soe

-

50

ns

Write Enable
Output Disable
Time

TWLQZ

vee = 4.5V and 5.5V HM-6516/883

1

-55°C ~TA~ +1250 e

-

80

ns

vee = 4.5V and 5.5V HM-6516B/883

1

-550e~TA~+12soe

-

50

ns

Output Enable
Access Time

TGLOV

vee = 4.5V and 5.5V

1

-550e~TA~+1250e

-

80

ns

00

NOTES: 1. The parameters listed in table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
2. Applies to

Lee device types only.

3. Applies to DIP device types only.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

InlialTest

loo%/SOO4

-

Interim Test

loo%/S004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3, 8A, 8B, 10, 11

Group A

Samples/500S

1,2,3,7, 8A, 8B,9,10,11

GroupsC&D

Samples/5005

1,7,9

3-85

en=>:;::;:
.......
:;:

HM-6516/883
Timing Waveforms
READ CYCLE

HM-6516/883 and HM-6516B/883

E
W--~--~~----~------------r------f----------------

TIME-----------4------+-----------4---------~--_t------t_----_;-----­

REFERENCE

o.

-1

The address information is latched in the on chip registers
on the falling edge of E (T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1), the outputs become
enabled but data is not valid until time (T = 2), VIi must re-

WRITE CYCLE

5

2

main high throughout the read cycle. After the data has
been read, E may return high (T = 3). This will force the output buffers into a high impedance mode at time (T = 4). Gis
used to disable the output buffers when in a logical "1"
state (T = -1, 0, 3, 4, 5). After (T ='4) time, the memory is
ready for the next cycle.

HM-6516/883 and HM-6516B/883

A

E
W
DQ

TIME
REFERENCE

I
-1

I

I

I

0

2

3

The write cycle is initiated on the falling edge of E (T = 0),
which latches the address information in the on chip registers. If a write cycle is to be performed where the output is
not to become active, Gcan be held high (inactive). TDVWH
and TWHDX must be met for proper device operation regardless of G. If E and G fall before W falls (read mode), a
possible bus conflict may exist. If E rises before W rises, reference data setup and hold times to the E rising edge. The

I
4

I

5

write operation is terminated by the first rising edge of W (T
= 2) or E (T = 3). After the minimum Ehigh time (TEHEL), the
next cycle may begin. If a series of consecutive write cycles
are to be performed, the W line may be held low until all desired locations have been written. In this case, data setup
and hold times must be referenced to the rising of E.

3-86

HM-6516/883

Test Load Circuit

r------------,
I
I
I
OUT 0-"",,-+-<
I
I
I
I
I
I

Burn-In Circuits

HM-6516/883 CERAMIC DIP
I-~...-ovec

1---Nl1'v-- Fll
1---Nl1'v-- F12
t---'V\IV-- Fl
t---'V\IV-- FO
t---'V\IV-- F13
t---'V\IV-- FO

>-

W

:s

HM4-65162/883 (CERAMIC LCC)
TOP VIEW
000800
!:(zzz>zz
~2i ~1. ISO!
_" 141131121.1.
"_01 10_01 10_'" ~_.. ,,_"'
"_01 "_01 p.
A6 !.!l
t~ A8

~]

[~

A9

[~ NC
[~6 W
[~5 G

Functional Diagram

[~4 AtO

At
AI

A2
A3
A4
AS
AB

AT

NC

007

000

006

DOO

..-:r:..----'....... TilRU
I
I
I

8

.,...C\lCO(,)~lD

DC7

gg~zggg

I

I

PIN NAMES

J

PIN
NC
AO-AtO

E
NJ

AS A9A10

Copyright @ Harris Corporation 1989

3-91

DESCRIPTION
No Connect
Address Input
Chip Enable/Power Down

VSS/GND

Ground

DOO-D07
VCC

Data In/Data Out

Iii

Power (+SVj
Write Enable

G

Output Enable

Specifications HM-65162/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage '" ••••.•••••••••••••••••••••••••••••••• +7.0V
Input, Output or I/O Voltage Applied. • • •• GND-0.3V to VCC+0.3V
Storage Temperature Range •.••••••••••••••• -650C to +1500C
Lead Temperature (Soldering 10 sec) ••••••••••••••••••• +3000C
Junction Temperature •••••••••••••••.••••••••• '•.••••• +1750C
Typical Derating Factor •.•••••••••• 5mNMHz Increase in ICCOP
ESD Classification •••••••••••••••.••••••••••.••••••••• Class 1

Thermal Resistance
ala
°jc
4BoC/W
BOC/W
Ceramic DIP Package •••••••.•••••••••
Ceramic LCC Package •.•.••.•••••••.. B50C/W
400 C/W
Maximum Package Power Dissipation at +1250C
Ceramic DIP Package •••••••.••••.•••••••••••••.•••••• 1.0W
Ceramic LCC Package •••.••••••••••••••.•••••••••••• 0.5BW
Gate Count •.•••••.•••••••.••••••••••••.•••••••• 26000 Gates

CAUTION:

Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those Indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Supply Voltage (VCC) •••.•••••••••...•••• 4.5V to 5.5V
Operating Temperature Range (TA) .....•••••• -550C to +1250C
Input Low Voltage (VIL) •••••••.••.•••••.•..•••••••• OV to +O.BV

Input High Voltage (VIH) •.••.•.••••.••••••••• : • ", +2.2V to VCC
Data Retention Supply Voltage •••.••••••••••••••••• 2.0V to 4.5V
Input Rise and Fall Times ••••••.•.••••••••••.••.••.•• 40ns Max

TABLE 1. HM-65162/8B3 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

(NOTE 1)
CONDITIONS

SYMBOL

UMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX UNITS

High Level Output
Voltage

VOH1

VCC = 4.5V,10 = -1.0mA

1,2,3

-550 CSTAS+1250C

2.4

-

V

Low Level Output
Voltage

VOL

VCC = 4.5V,IO = 4.0mA

1,2,3

-550 C9A:::+1250C

-

0.4

V

High Impedance Output
Leakage Current

1I0Z

VCC = 5.SV, G= 2.2V, or E = 2.2V
VI/O = GND or VCC

1,2,3

-550 C9A:::+1250C

-1.0

1.0

~A

VCC = 5.5V, VI = GND or VCC

1,2,3

-550 CSTAS+1250C

-1.0

1.0

~

VCC = 5.5V,10 = mA,
E=VCC-0.3V

1,2,3

-550C9AS+1250C

-

100

~

Input Leakage Current

II

Standby Supply
Current

ICCSB1

Siandby Supply Current

ICCSB

VCC = 5.5V,10 = OmA,
E=2.2V

1,2,3

-550C9AS+125 0C

-

B

mA

Operating Supply
Current

ICCOP

VCC - 5.5V, G - 5.5V, (Nole 4),
f = 1 MHz, E = O.BV

1,2,3

-550 C9AS+1250C

-

70

mA

Enable Supply Current

ICCEN

VCC = 5.5V,10 = OmA, E = O.BV

1,2,3

-550 C9AS+1250C

mA

ICCDR

VCC = 2.0V,10 = OmA,
E=VCC-0.3V

1,2,3

-550 CSTAS+1250C

-

70

Data Retention
Supply Current

40

~

7,BA,BB

-550 C9AS+1250C

-

-

-

Funclional Test

VCC = 4.5V (Note 5)

FT

TABLE 2. HM-65162/BB3 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested.
LIMITS

SYMBOL

(NOTES 1, 2, 3)
CONDITIONS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Read/Write/Cycle Time

TAVAX

VCC = 4.SV and 5.5V

9,10,11

-550 CgAS+1250C

90

ns

Address Access Time

TAVQV

VCC = 4.SV and 5.5V

9,10,11

-55 0CSTAS+1250C

-

90

ns

Output Enable Access Time

TGLQV

VCC - 4.5V and 5.5V

9,10,11

-550C9AS+1250C

65

ns

Chip Enable Access Time

TELQV

VCC - 4.SV and 5.5V

9,10,11

-55 0 C:s,TAS+1250 C

-

90

ns

Write Enable Read Setup Time

TWHAX

VCC = 4.5V and 5.5V

9,10,11

-55 0 C9AS+1250C

10

ns

Address Setup Time

TAVWL

VCC = 4.5V and 5.5V

9,10,11

-550C9AS+1250C

10

Chip Selection to End of Write

TELWH

VCC = 4.5V and 5.5V

9,10,11

-550C9AS+1250C

55

-

Write Enable Pulse Setup Time

TWLEH

VCC = 4.SV and 5.5V

9,10,11

-550 CgAS+1250C

55

-

Chip Enable Data Setup Time

TDVEH

VCC = 4.SV and 5.5V

9,10,11

-550 CSTAS+1250 C

30

Address Valid to End of Write

TAVWH

VCC = 4.SV and 5.5V

9,10,11

-550 C;STAS+1250 C

65

Write Enable Pulse Write

TWLWH

VCC - 4.5V and 5.5V

9,10,11

-550 CgAS+125 0C

55

-

Data Setup Time

TDVWH

VCC = 4.SV and 5.5V

9,10,11

-550 CgAS+125 0C

30

Data Hold Time

TWHDX

VCC = 4.SV and 5.5V

9,10,11

-550 CSTAS+1250C

15

A.C. PARAMETERS

..

CAUTION: These deVices are sensItive

to electroniC discharge. Proper Ie

handling procedures should be followed .

3-92

-

ns
ns
ns
ns
ns
ns
ns
ns

Specifications HM-65162/883
TABLE 3. HM-65162/883 ELECTRICAL PERFORMANCE CHARACTERISTICS, A.C. AND D.C. (NOTE 6)
LIMITS
PARAMETERS
Input Capacitance

CONDITIONS

SYMBOL
CIN

CI/O

TEMPERATURE

MIN

MAX

UNITS

-

10

pF

=

=

6,6

+250C

=

=

6,9

+2SoC

-

8

pF

=

=

6,8

+250C

-

12

pF

=

=

6,9

+2SoC

-

10

pF

VCC Open, F 1 MHz,
All Measurements Referenced
To Device Grounds
VCC Open, F 1 MHz,
All Measurements Referenced
To Device Grounds

I/O Capacitance

NOTES

VCC Open, F 1 MHz,
All Measurements Referenced
To Device Grounds
VCC Open, F 1 MHz,
All Measurements Referenced
To Device Grounds

Write Enable to
Output in High Z

TWLOZ

VCC

=4.SV and S.SV

6

-5SoC ~TA!>+12S0C

-

SO

ns

Write Enable High
to Output ON

TWHOX

VCC

=4.5V and 5.5V

6

-SSoC !>TA!> +12SoC

0

-

ns

Chip Enable to
Output ON

TELOX

VCC

=4.SV and S.SV

6

-SSoC !>TA!>+12S0 C

0

-

ns

Output Enable to
Output ON

TGLOX

VCC

=4.SV and S.SV

6

-SSoC !>TA!>+12S0C

S

-

ns

Chip Enable High

TEHOZ

VCC

=4.SV and S.SV

6

-SSoC .:::TA'::: +12SoC

-

SO

ns

Output Disable to
Output in High Z

TGHOZ

VCC

=4.SV and S.SV

6

-SSoC .:::TA'::: +12SoC

-

40

ns

Output Hold from
Address Change

TAVOX

VCC

=4.SV and S.SV

6

-SSoC !>TA!> +12SoC

S

-

ns

Output High Voltage

VOH2

VCC

=4.SV,IO =-100pA

6

-SSoC !>TA!> +12SoC

VCC
-0.4V

-

V

NOTES:

1. All voltage. referenced to device GND.
2. AC measurements assume transition time < 5ns; input levels = O.OV to 3.0V; timing reference levels = 1.5V; output load ... 1 TIL equivalent load
and CL ~ 50pF; for CL > 50pF < 300pF,-;;cces.lIme. are derated O.15n./pF.
3. For timing waveforms, see Low Voltage Data Retention and Read/Write Cycles.
4. Typical derating = 5mNMHz Increase in ICCOP.
5. Tested as follows: f = 2MHz. VIH = 2.4V, VIL = O.4V,IOH = -4.0mA,IOL = 4.omA. VOH?: 1.5V, and VOL S 1.5V.
6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tasted. These parameters are characterized
upon initial design release and upon design changes which would affect thase characteristics.
7. This Is a "typical" value and not a "maximum" value.
8. Applies to DIP device types only.
9. Applies to

Lee device types only.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

>",a:
00

..,,,,

to Output ON

METHOD

SUBGROUPS

Initial Test

100%/S004

-

Interim Test

100%/S004

1,7,9

PDA

100%/5004

1

FinalTest

100%/S004

2,3, 8A, 8B, 10, 11

Group A

Samples/S004

l,2,3,7,8A,8B,9,10,ll

GroupsC&D

Samples/500S

1,7,9

3-93

:;::;:
:;:

Specifications HM-65162B/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••..........••.•..•.••.••..••.•.••.•.... +7.0V
Input or Output Voltage Applied for all grades ...... GND -0.3V to
VCC+0.3V
Storage Temperature Range .••.•..•..•..•.•. -650C to +150 0C
Lead Temperature (Soldering 10 sec) •..•......•..• : •... +300 0C
Junction Temperature •.•..•.............••..•..•.•••• +175 0C
Typical Derating Factor •....••••.•• 5mNMHz Increase in ICCOP
ESD Classification .........••.•.••..•.••.••••••••..... Class 1

Thermal Resistance
aja
Ceramic DIP Package. • • . . . . . . . . . • •
480 C/W
Ceramic LCC Package. • . . • • • • . . . • •
850 C/W .
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package .•. '.' ...•..........•.•.....••..•• 1.0W
Ceramic LCC Package ••...•.....••.................• 0.58W
Gate Count •.•••.....•.••.••.•.•••..•••.•.•••... 26000 Gates

CAUTION: Stresses above those listed in "Abso/ute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

.

Operating Temperature Range (TA) •.••.•..... -550C to +1250 C
Operating Supply Voltage (VCC) ...•................ 4.5V to 5.5V
Input Low Voltage (VIL) .•.••......•..•............. OV to +0.8V

Input High Voltag~ (VI H) .... : ..••....... , ...••... +2.2V to VCC
Data Retention Supply Voltage ..•...•.•.•.•....••.. 2.0V to 4.5V
Input Rise and Fall Times . • . • . . . . . . . • . • • • . . • . . . . • .• 40ns (Max)

TABLE 1. HM65162B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

High Level Output
Voltage

VOHl

VCC = 4.5V, 10 =-1.0mA

1,2,3

-550C :STA~ +125 0 C

2.4

-

V

Low Level Output
Voltage

VOL

VCC = 4.5V, 10 = 4.0mA

1,2,3

-55°C ~TA~ +1250 C

-

0.4

V

High Impedance
Output
Leakage Current
Input Leakage
Current
Standby Supply
Current
Standby Supply

IIOZ

vce - 5.5V, G - 2.2V,
orE= 2.2V
VI/O = GND orVCC
VCC=5.5V,
VI = GND orVCC

1,2,3

-550C ~TA ~ +1250 C

-1.0

1.0

f1A

1,2,3

-55°C ~TA.s +1250 C

-1.0

1.0

~A

VCC - 5.5V, 10 - OmA,
E=VCC-0.3V
VCC -5.5V,IO = OmA,
E=2.2V

1,2,3

-550C ~TA.s +1250 C

-

50

~A

1,2,3

-550C~TA.s+1250C

-

8

rnA

PARAMETER

CONDITIONS

SYMBOL

II
ICCSBl
ICCSB

Current

Operating Supply
Current

ICCOP

VCC - 5.5V, G = 5.5V, (Note 4),
f= 1 MHz, E= 0.8V

1,2,3

-550C~TA~+1250C

-

70

rnA

Enable Supply
Current

ICCEN

VCC - 5.5V, 10 - OmA,
E=0.8V

1,2,3,

-55°C .sTA..s +1250 C

-

70

rnA

Data Retention
Supply Current
Functional Test

ICCDR

VCC - 2.0V,10 - OmA,
E=VCC-0.3V
VCC - 4.5V (Note 5)

1,2,3

-550C.sTA~+1250C

20

f1A

7,8A,8B

-550 C..sTA..s+1250C

-

-

FT

-

TABLE 2. HM-6S162B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS

GROUPA

SYMBOL

(NOTES 1, 2, 3)
CONDITIONS

SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

TAVAX
TAVOV

VCC = 4.5V and 5.5V
VCC - 4.5V and 5.5V

9,10,11
9,10,11

70

-

ns
ns

Chip Enable Access Time

TGLOV
TELOV

VCC - 4.5V and 5.5V
vce - 4.5V and 5.5V

Write Enable Read Setup Time
Address Setup Time
ehip Selection to End of Write

TWHAX
TAVWL
TELWH

vce - 4.5V and 5.5V
VCC - 4.5V and 5.5V
vce = 4.5V and 5.5V

9,10,11
9,10,11
9,10,11

-55°C .sTA.s +1250 C
-550C  + 125°C

vec
-O.4V

-

V

to Output ON

NOTES:

1. All voltages referenced to device GND.
2. AC measurements assume transition time < 5"s; input levels = O.OV to 3.0V; timing referenca levels = 1.5V; output load = 1 TTL equivalent load
and CL ~ 50pF; for CL > 50pF < 300pF.~ccess times are derated O.15ns/pF.
3. For timing waveforms, see Low Voltage Data Retention and Read/Write Cycles.
4. Typical derating

= smA/MHz Increase in recop.
= 2.4V. VIL = O.4V. IOH =

. 5. Tested as follows: f = 2M Hz. VIH

-4.0mA. IOL = 4.omA. VOH 2:1.5V. and VOL::: 1.5V.

6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. Thase parameters are
characterized upon initial design release and upon design changes which would affect Ihese characteristics.
7. This is a "typical" value and not a "maximum" value.
B. Applies to DIP device types only.
9. Applies to LCC device types only.

TABLE 4.

CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Groupse&D

APPLICABLE SUBGROUPS

METHOD

100%/5004
100%/5004
100%/5004
100%/5004
Samples/500S
Samples/S005

3-95

SUBGROUPS
1,7,9
1
2,3,7, BA, BB, 10, 11
l,2,3,7,8A,8B,9,10,ll
1,7,9

>",a:
:;::;:
c.o'"
:;:

00

Specifications HM,..65762C/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ........................................ +7.0V
.Input or Output Voltage Applied for all grades •••••• G NO -0.3V to
VCC+0.3V
Storage Temperature Range ..••••••.•••••••• -650C to +1500C
Lead Temperature (Soldering 10 sec) ••••••••••••••••••• +3000 C
JunctionTemperature ................................ +1750 C
Typical Derating Factor ••.••••••••• 5mNMHz Increase in ICCOP
ESD Classification .................................... Class 1

Thermal Resistance
Bja
Ceramic DIP Package. • • • • • • • • • • • • •
480 C/W
Ceramic LCC Package. • • • • • • • • • • • •
85 0C/W
Maximum Package Power Dissipation at +1250C
Ceramic DIP Package ................................. : 1.0W
Ceramic LCC Package ............................... 0.58W
'Gate Count ..................................... 26000 Gates

to

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
OperatingTemperatureRange(TA) ........... -550Cto+1250C
Operating Supply Voltage (VCC) ••••••••••••••..•••• 4.5V to 5.5V
Input Low Voltage (VIL) •••••••••••••••••••••.•••••• OV to +0.8V

Input High Voltage (VIH) ......................... +2.2V to vee
Data Retention Supply Voltage ••••••••••••••••••••• 2.0V to 4.5V
Input Rise and Fall Times .......................... 40n8 (Max)

TABLE 1. HM-65162C/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

High Level Output
Voltage
Low Level Output
Voltage

VOHl

VCC = 4.5V, 10 = -1.0mA

1,2,3

-550C ~TA~ +125 0e

2.4

-

V

VOL

vce - 4.5V,10 - 4.0mA

1,2,3

-55°C ~TA ~ +1250 e

-

0.4

V

High Impedance
Output
Leakage Current

IIOZ

VCC - 5.5V, G - 2.2V,
orE=2.2V
Vl/O = GND orVCe

1,2,3

~550C ~TA ~ +1250 C

-5.0

5.0

pA

Input Leakage
Current
Standby Supply
Current
Standby Supply
Current
Operating Supply
Current
Enable Supply
Current

II

vee = 5.5V,
VI = GND orVCe

1,2,3

-550C~TA~+1250C

-5.0

5.0

pA

IceSBl

vee - 5.5V,10 - OmA,
E=VCC-0.3V

1,2,3

-550C~TA~+1250e

900

pA

leCSB

VCC - 5.5V,10 - OmA,
E=2.2V
VCC - 5.5V, G - 5.5V, (Note 4),
f = 1 MHz, E = 0.8V

1,2,3

-55°C ~TA ~ +1250 C

-

8

mA

1,2,~

-550C~TA~+1250C

-

70

mA

ICC EN

VCC - 5.5V, 10 - OmA,
E=0.8V'

',2,3,

-550C~TA~+1250C

-

70

mA

ICCDR

VCC - 2.0V, 10 - OmA,
E=VCC-0.3V
VCC - 4.5V (Note 5)

1,2,3

-550C~TA~+1250C

300

pA

7,8A,8B

-550C~TA~+1250C

-

-

PARAMETER

SYMBOL

ICCOP

Data Retention
Supply Current
Functional Test

FT

-

TABLE 2. HM-65162C/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

A.C. PARAMETERS

SYMBOL

(NOTES 1,2,3)
CONDITIONS

GROUP A
SUBGROUPS

LIMITS
TEMPERATURE

MIN

MAX

UNITS

9,10,11
9,10,11

-550C  50pF < 300pF. access times are derated O.15ns/pF.
3. For timing waveforms, see Low Voltage Data Retention and Read/Write Cycles.
4. Typical derating == 5mNMHz increase in leCOp.
5. Tesled as follows: f

= 2MHz, VIH = 2.41/, VIL = O.4V,IOH = -4.0mA.IOL =

4.0mA. VOH 2;l.SV. and VOL ~ 1.SV.

6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
7. This is a "typical" value and not a "maximum" value.
8. Applies to DIP device types only.
9. Applies to LCC device types only.

TABLE 4.

CONFORMANCE GROUPS

APPLICABLE SUBGROUPS

METHOD

SUBGROUPS

InilialTest

100%/5004

Interim Test

100%/S004

1,7,9

100%/5004
100%/S004
Samples/SOOS
Samples/500S

1
2,3,7,8A, 8B, 10, 11
1,2,3, 7,8A,8B, 9,10,11
1,7,9

PDA
Final Test
Group A
GroupsC&D

3-97'

HM-65162/883
Timing Waveforms
READ CYCLE

NOTE:

Vi is High lor a Read

Addresses must remain stable for the duration of the read
cycle. To read, G and E must be < VIL and W > VIH. The
output buffers can be controlled independently byG while E
is low. To execute consecutive read cycles, E

Cycle

may be tied low continuously until all desired locations are
accessed. When E is low, addresses must be driven by stable logic levels and must not be in the high impedance state.

WRITE CYCLE I

TAVAX

ADDRESS

- _.......f--_+----

TWHAX

Q

D
TWHDX

TDVWH
TAVWH
NOTE:

G Is Low Throughout Wr~e Cycle

To write, addresses must be stable, E low and Wfalling low
for a period no shorter than TWLWH. Data in is
referenced with the raising edge of W, (TDVWH and
TWHDX). While addresses are changing, W must be high.
When W falls low, the I/O pins are stili in the output state for

a period of TWLQZ and input data of the opposite phase to
the outputs must not be applied, (Bus contention). IfEtransitions low simultaneously with the W line transitioning low
or after the W transition, the output will remain in a high impedance state. G is held continuously low.

3-98

HM-65162/883
Timing Waveforms (Continued)
TAVAX

WRITE CYCLE II

In this write cycle 13 has control of the output after a period,
TGHOZ. 13 switching the output to a high impedance state
allows data in to be applied without bus contention after

TGHOZ. When W transitions high, the data in can change
after TWHDX to complete the write cycle.

:E:E
t.)UJ
:E

Low Voltage Data Retention
Harris eMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules insure data retention:
1.

2.

ehip Enable (E) must be held high during data
retention; within vee - 0.3V to vee + 0.3V.

3.

Inputs which are to be held high (e.g., E) must be kept
between vee + 0.3V and 70% of vee during the power
up and down transitions.

4.

The RAM can begin operation > 55ns after vee
reaches the minimum operating voltage (4.5 volts).

On RAMs which have selects or output enables (e.g., S,

G), one of the selects or output enables should be held
in the deselected state to keep the RAM outputs high
impedance, minimizing power dissipation.

DATA RETENTION TIMING

vee ------------~
4.5V

----

>-

 2.0V

vee - O.3V TO vee + O.3V

3-99

HM-65162/883

Test Circuit

r------------.,
1
1
1

D~

1
1
1

t

IOL

1

'TEST HEAD

:::~t~D~NCE.

1

1

I

~:~~~:;' , _ _ _ EQUIVALENT_CIRCUIT _ _ _

I
I

Burn-In Circuits
HM-65162/883 CERAMIC DIP

HM-65162/883 CERAMIC LCC

vce

vee

0

c

C~

0:

I-"'''-'IM-Fll~
P"-'lM-F12.

!C

oz 0z

zo 0z

I-"--'lM- Fl
r-M-FO
!-'-'=IIM-F13

AS

F9

A9

F8

Fll
F12

F7

!-=-M-FO
!-=::JIM-F2
I--"-~M,..F2

5t-'="""'''''''F2

F6

G

F5

Al0

F4

E

F3

DQ7

......'""'IM-F2
!-=::::IIM-F2

VIN

DaB

F2

Fl
FO
F13
FO
F2
F2

4.SVJLJ1SL
OV

NOTES:
All Resislors 47kO. 5%
FO = 100kHz ±10%

Fl =FO+2.F2=Fl +2.
F3 = F2 + 2 •... F13 = F12 + 2

NOTES:

vee = 5.5V ±0.5V

F3 = F2 + 2 •... F13 = F12 + 2

VIH - 4.5V ±10%
VIL = -0.2V to +D.4V

FO = 100kHz ±10%
All Resistors 47kO. 5%
= 0.01 ~F (Min)

Fl =FO+2.F2=Fl +2.

vee = 5.5V. ±0.5V

e = 0.01 iJF (Min)

VIH - 4.5V ±10%
VIL = -0.2V 10 +O.4V

3-100

e

HM-65162/883
Metal Topology
DIE DIMENSIONS:
186.2 x 200.1 x 19 ±1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11 k.8. ± 2k.8.
GLASSIVATION:
Type: Si02
Thickness: 8k.8. ± 1k.8.
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
1.7 x 105 Ncm 2

Metallization Mask Layout
HM-6S162/883
A3

A4

AS

A6

A7

VCCA8

A9

Vi

G

A2

"'~
====
==

00
c.>W

A1
AO
DOO

D04

D01 D02 GND D03

3-101

DOS D06

HM-65162/883
Packaging t
24 PIN CERAMIC DIP

..Q:.
15·

.. INCREASE MAX WAIT BY .003 !NCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 1QoC
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-3

32 PAD CERAMIC LCC

.540

.560

.045
.055

~------ :~~ ------~

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: GoldfTin (80/20)
Temperature: 320 0 C ± 1QoC
Method: Furnace Braze

NOTE: All Dimensions are

~
Max

• Dimensions are in inches.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-12

tMil-M-38510 Compliant Materials, Finishes, and Dimensions.

3-102

Em HARRIS

HM-65162

DESIGN INFORMATION

2K x 8 Asynchronous
CMOS Static RAM

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
TYPICAL ICCOR vs. TA
Vee = 2.0V
-3

-4

./

-5

-6

3'=::

...

-7

;:;;

-8

:l

-9
-10
-11
-12

V
./
-55

-35

V
-15

,.,

/

::

V

25

45

3-103

;/
./

65

. /"

85

105

125

HM-65262/883

fIIHARRIS

16K x 1 Asynchronous
CMOS Static RAM

June 1989

Pinouts

Features
• This Circuit is Processed in Accordance to Mil-Std-883 and is
Fully Conformant Under the Provisions of Paragraph 1.2.1.
• Fast Access Time •••••••••••••••••••••••••••••••• 70/8Sns Max
• Low Standby Current ••••••••••••••••••••••••••••••• SOIlA Max
• Low Operating Current ••••••••••••••••••••••••••••• SOmA Max
• Data Retention at 2.0 Volts. • • • • • • • • • • • • • • • • • • • • • • • •• 20llA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
• No Clocks or Strobes Required
,. Temperature Range ••••••••••••••••••••••••• -SSoC to +12S o C
• Equal Cycle and Access Time
• Single 5 Volt Supply
• Gated Inputs-No Pull-Up or 'Pull-Down Resistors Required

HM1-65262/883 (CERAMIC DIP)
TOP VIEW
AO

VCC

Al

A13

A2

A12
All

A4

Al0

AS

A9

A6

A8

Q

A7

Description
The HM-65262/883 is a CMOS 16384 x 1 bit Static Random Access
Memory manufactured using the Harris Advanced SAJI V process. The
device utilizes asynchronous circuit design for fast cycle times and
ease of use. The HM-65262/883 is available in both JEDEC standard
20 pin, 0.300 inch wide DIP and 20 pad LCC packages, providing high
board-level packing density. Gated inputs lower standby current, and
also elminate the need for pull-up or pull-down resistors.
The HM-65262/883, a full CMOS RAM, utilizes an array of six transistor
(6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this,
the high stability of the 6T RAM cell provides excellent protection
. against soft errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four transistor
(4T) devices.

Functional Diagram

W

0

GND

E

HM4-65262/883 (CERAMIC LCC)
TOP VIEW

L~.J LgJ
A3

1]

~]

a

AIJo----=r'-.r---,

t!J LtQi ~~.J

r-", r- .. r-., r-., r-.,

19 111011 111112111

[i8

A12

ff7

All

"[i6 Al0
[is A9
[[4 AS

I

MEMORY ARRAY
128 X 128

A,ao--+,')--,,__-,
D~-1~~---------t~

t---D_oo

PIN
AO-A13

E

Chip Enable/Power Dawn

Q

Data Out

D

Data In

VSS/GND

Ground

VCC

Vi

Copyright @ Harris Corporation 1989

3-104

DESCRIPTION
Address Input

Power (+5V)
Write Enable

Specifications HM-65262/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••.•••••.•.••••••••.•••••••••••••••••••• +7.0V
Input or Output Voltage Applied for all grades ••••••• GND-0.3V to
VCC+0.3V
Storage Temperature Range ••••••••••••••••• -650C to +150 0 C
Lead Temperature (Soldering 10 sec) •••.••••••••.•.•••• +300 0 C
JunctionTemperature •••••••••••••••••••••••••••••••• +1750 C
Typical Derating Factor ••••••••••.• 5mNMHz Increase in ICCOP
ESD Classification •••••.•.•••.••••.••••••••••••.•••••• Class 1

6jc
Thermal Resistance
°ja
Ceramic DIP Package •••••••••••••.•.•
660 C/W
130 C/W
Ceramic LCC Package ••••••••••••••••
850 C/W
40 0C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ••.•.••••••••••••••••••.•••••••.• 0.75W
Ceramic LCC Package ••••..••••••••••••.•.•••••••••• 0.58W
Gate Count '" •••••.••••••••.••••••••••.•••••••• 26256 Gates

CAUTION: Stresses above those Iisted;n ''Absolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating .Conditions
Operating Supply Voltage (VCC) ••••••.•••••••.••••• 4.5V to 5.5V
Operating Temperature Range (TA) .•••.•.•••. -55 0 C to +125 0 C
Input Low Voltage (VIL) ••••••••.••••••••.••.•••••.. OV to +0.8V

Input High Voltage (VIH) .•••••••••••••••••••••••. +2.2V to VCC
Data Retention Supply Voltage •••••••••••••••••••.• 2.0V to 4.5V
Input Rise and Fall Time ••.••••.••.••••••••.••••••••• 40ns Max

TABLE 1. HM-65262/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

TEMPERATURE

MIN

VCC = 4.511, 10 = -4.0mA

1,2,3

-550 CSTA<+1250C

2.4

VOL

VCC = 4.5V,10 = 8.0mA

1,2,3

-550 CSTAS+1250C

-

0.4

V

10Z

VCC = 5.5V, E = 5.5V,
VO=GNDorVCC

1,2,3

-550 CSTAS+1250C

-1.0

1.0

~A

VCC - 5.5V, VI = GNO or VCC

1,2,3

-550 CSTAS+1250C

-1.0

1.0

~A

VCC - 5.5V,IO - OmA,
E=VCC-o.3V

1,2,3

-55 0CSTAS+1250C

-

50

~

5

rnA

50

mA

20

~A

SYMBOL

High Level Output Voltage

VOHI

Low Level Output Voltage
High Impedance Output
Leakage Current
Input Leakage Current

II

Standby Supply
Current

ICCSBI

(NOTE 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

D.C. PARAMETER

MAX ~NITS

-

V

00

::;:::;:

Standby Supply Current

ICCSB

VCC = 5.5V,IO = OmA, E = 2.2V

1,2,3

-550CSTAS+ 1250C

Operating Supply

ICCOP

VCC - 5.5V, (Note 4),
f=IMHz,E=O.BV

1,2,3

-550CSTAS+ 1250C

Data Retention
Supply Current

ICCDR

VCC = 2.0V, 10 = OmA,
E=VCC-o.3V

1,2,3

-550CsrAS+1250C

Enable Supply Current

ICCEN

VCC - 5.5V,IO = OmA, E = O.BV

1,2,3

-550C:STAS+1250C

-

50

mA

7,BA,BB

-550 CSTAS+1250C

-

-

-

UNITS

Current

FT

Functional Test

VCC - 4.5V (Note 5)

TABLE 2. HM-65262/BB3 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested.

A.C. PARAMETERS

SYMBOL

(NOTES 1, 2, 3)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

-

ns

B5

ns

ReadIWrite/Cycle Time

(I)TAVAX

VCC = 4.5V and 5.5V

9,10,11

-55 0CSTAS+1250C

85

Address Access Time

(2)TAVQV

VCC = 4.SV and 5.5V

9,10,11

-55 0C",a:

-

ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns

c..>W

::;:

Specifications HM-65262/883
TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE CHARACTERISTICS, A.C. AND D.C. (NOTE 6)
LI·MITS
PARAMETERS

. SYMBOL
elN

Input.Capacitance

Output Capacitance

CO

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

vee = Open, f = 1 MHz,
All Measurements Referenced
To Device Grounds

6,7

TA=+250e

-

10

pF

vee = Open, f = 1 MHz,
All Measurements Referenced
To Device Grounds

6,8

TA=+250e

-

6

pF.

vee = Open, f = 1 MHz,
All Measurements Referenced
To Device Grounds

6,7

TA=+250e

-

12

pF

vee = Open, f = 1 MHz,
All Measurements Referenced
To Device Grounds

6,8

TA=+250e

-

8

pF

Write Enable to
Output in High Z

(18) TWLOZ

vee = 4.5V and 5.5V

6

-55oe S.TA~ +1250e

-

40

ns

Write Enable High
to Output ON

(19)TWHOX

vee = 4.5V and 5.5V

6

-550e.:sTA~+1250e

0

-

ns

Chip Enable to
Output ON

(20)TELOX

vee = 4.5V and 5.5V

6

-550e ~TA.:s +1250e

5

-

ns

Output Enable High
to Output in High Z

(21)TEHOZ

vee = 4.5V and 5.5V

6

-55oe ~TA.:s +1250e

-

40

ns

Chip Disable to
Output Hold Time

(22)TEHOX

vee = 4.5V and 5.5V

6

-550e~TA~+1250e

5

-

ns

Address Invalid
Output Hold Time

(23)TAXOX

vee = 4.5V and 5.5V

6

-550e~TA.:s+1250e

5

-

ns

vee = 4.5V,IO = -10011A

6

-550e ~TA.:s +1250e

vee
-OAV

-

v

High Level
Output Voltage
.NOTES:

VOH2

1. All voltages referenced to device GNO. Negative undershoots to a minimum of -O.3V are allowed with a maximum of 50ns pulse width.
2. AC measurements assume transition time ~ 5ns; input levels = O.OV to 3.0V; timing reference levels
and CL ~ 50pF; for CL > 50pF. access times are derated O.15ns/pF.

= 1.5V; output load = 1 TTL equivalent load

3. For timing waveforms. see Low Voltage Data Retention and Read/Write Cycles.
4. Typical derating

= 5mNMHz Increase in ICCOP.

5. Tested as follows: f

a

2MHz. VIH = 2.4V, VIL = O.4V,IOH = -4.0mA,IOL = 4.omA, VOH.2: 1.5V, and VOL

~ ~.5V.

6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon InHiai design release and upon design change~ which would affect these characteristics.
7. AppUe.to DIP device types only.
8. Applle.to Lce device type. only.

TABLE 4. APPLICABLE SUBGROUPS·
CONFORMANCE GROUPS

METliOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Teat

100%/5004

2,3, 8A, 8B, 10, 11

Group A

SampleS/5005·

1,2,3, 7,8A, 8B, 9,10,11

Groupse&D

SampleS/5005

1,7,9

3-106

Specifications HM-65262B/883
Reliability Information

Absolute Maximum Ratings

aja
ajc
Supply Voltage ........................................ +7.0V Thermal Resistance
Input or Output Voltage Applied for all grades ••••.••.••. -0.3V to
Ceramic DIP Package •••••••••••.•••••
660 C/W
130 C/W
0
Ceramic LCC Package •••••••••••••.••
VCC+0.3V
85 C/W 40 0 C/W
Storage Temperature Range ••••••••••••••••• -650C to +150 0 C
Maximum Package Power Dissipation at +1250 C
Lead Temperature (Soldering 10 sec) .••.•••.••••••••••• +300 0 C
Ceramic DIP Package ................................ 0.75W
Ceramic LCC Package ............................... 0.5BW
JunctionTemperature ................................ +175 0 C
Typical Derating Factor •••••••.•••. 5mNMHz Increase in ICCOP
Gate Count ..................................... 26256 Gates
ESD Classification .................................... Class 1
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the 'operational sections of this specification is not implied.

Operating Conditions
Operating Supply Voltage (VCC) .................... 4.5V to 5.5V
Operating Temperature Range (TA) ••••••••••• -550C to +125 0 C
Input Low Voltage (VIL) ............................ OV to +0.8V

Input High Voltage (VIH) ••••••••••••••••••.•.•••. +2.2V to VCC
Data Retention Supply Voltage ••.•••••.......•••••• 2.0V to 4.5V
Input Rise and Fall Time ............................. 40ns Max

TABLE 1. HM-65262B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

MIN

MAX

UNITS

VCC = 4.5V,IO = -4.0mA

1,2,3

-55 0C",a:

00

70

-

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns

:;::;:
UW
:;:

Specifications HM-65262B/883
TABLE 3. HM-65262B/883 ELECTRICAL PERFORMANCE CHARACTERISTICS, A.C. AND D.C. (NOTE 6)
LIMITS
PARAMETERS

NOTES

TEMPERATURE

MIN

MAX

UNITS

VCC = Open, f = 1 MHz,
All Measurements Referenced
To Device Grounds

6,7

TA=+25OC

-

8

pF

VCC = Open, f = 1 MHz,
All Measurements Referenced
To Device Grounds

6,8

TA=+25OC

-

6

pF

VCC = Open, f = 1 MHz,
All Measurements Referenced
To Device Grounds

6,7

TA=+250C

-

10

pF

VCC = Open, f = 1 MHz,
All Measurements Referenced
To Device Grounds

6,8

TA=+250C

-

8

pF

CONDITIONS

SYMBOL

Input Capacitance

CIN

VO Capacitsnce

ClIO

Writs Enable to
Output in High Z

(18)TWLQZ

VCC = 4.5V and 5.5V

6

-550C.!£TA~+1250C

-

40

ns

Writs Enable High

(19)TWHQX

VCC = 4.5V and 5.5V

6

-55OC.!£TA~+1250C

0

-

ns

Chip Enable to
Output ON

(20)TELQX

VCC = 4.5V and 5.5V

6

-55OC.!£TA~+1250C

5

-

ns

Output Enable High

(21)TEHQZ

VCC = 4.5Vand 5.5V

6

-550C~TA~+125OC

-

40

ns

Chip Disable to
Output Hold TIme

(22)TEHQX

VCC = 4.5V and 5.5V

6

-55OC~TA~+1250C

5

-

ns

Address Invalid
Output Hold TIme

(23)TAXQX

VCC = 4.5V and 5.5V

6

-550C~TA~+1250C

5

-

ns

VCC = 4.5V,IO = -100fIA

6

-55oC ~ TA~ +125OC

VCC
.,OAV

-

V

to Output ON

to Output In High Z

High Level
Output Voltage
NOTES:

VOH2

1. All ~Itages referenced to device GND. Negative undershoots

to a minimum of -O.3V are allowed with a maximum of 50ns pulse width.

2. AC measurements assume transition time < 5ns; input levels = o.OVte 3.0V; timing reference levels = 1.5V; output load = 1 TTL equivalent load
and Cl ~ 50pF; for CL > 50pF, access times are derated O.15ns/pF.

3. For timing waveforms, see Low Voltage Data Retention and Read/Write Cycles.
4. Typical

~erating

= 5mNMHz increase in ICCOP.

5. Tested as follows: f = 2M Hz, VIH = 2.4V, VIL

= O.4V,IOH = -4.0mA,IOL = 4.0mA, VOH ~ 1.5V, and VOL:s. 1.5V.

6. The parameters listed in ,Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon Initial design release and upon design changes which would affect these chara~teristlc"s.
7. Applies to DIP device types only.
B. Applies to LCC device types only.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROIJPS

InilialTest

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3, 8A, 8B, 10, 11

Group A

Samples/5005

1,2,3,7, 8A,8B, 9,10,11

GroupsC&D

Samples/5005

1,7,9

3-108

HM-65262/883
Timing Waveforms
READ CYCLE 1: CONTROLLED BYE

E----"""\.l
120)

TELQX

NOTE: Wls high for enllre cycle and 0 is Ignored. Address Is stable by the
time if goes low and remains valid until goes high.

E

READ CYCLE. 2: CONTROLLED BY ADDRESS
11)
~~---------TAVAX------~

A

-----~~------~~---------------~-------------------

>rna:
00
:E:E
c.>W
:E
Q

NOTE:

is ignored. E is stable prior to A
becoming valid and after A becomes invalid.

Vi is high for the entire cycle and 0

WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE)

NOTE: In this mode; if rises after Vi. The address must remain slable when
ever both E and Vi are low.

3-109

e

HM-65262/883
Timing Waveforms (Continued)
WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)
~)

\04----

TAVAX ----~_l

A ______~~------------------~~~----------t-.....,.---TAVEH (10)----1
t - o - - - - TELEH ~')-----;~

E---------I

1,.---------------

w--"""""............~. . . .........J

E.

E

NOTE: In this mode, Vi rises after "W falls before by a lime exceeding TWLQZ (Max) TELQX
(Min), and rises after by a lime exceeding TEHQZ (Max)-TWHQZ (Min), then Q will remain
in the high impedance state throughout the cycle.

E

Low Voltage Data Retention
Harris eMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules insure data retention:

1. ehip Enable tE) must be held high during data retention;
within vee to vee

+ 0.3V.

2. On RAMs which have selects or output enables (e.g., S,
G), one of the selects or output enables should be held in
the deselected state to keep the RAM outputs high
impedance, minimizing power dissipation.

3. Inputs which are to be held high (e.g., E) must be kept
between vee + 0.3V and 70% of vee during the power
up and down transitions.
4. The RAM can begin operation> 55ns after vee reaches
the minimum operating voltage (4.5 volts).

DATA RETENTION TIMING

____ DATA RETENTION _ _ _ool
MODE
v e e - - - - - -.....

vee> 2.0V

vee - O.3V TO vee

3-110

+ O.3V

HM-65262/883

Test Circuit

,------------l

I

I

I
I

I
I
I
I
I
II
I

DUT

1.SV
*TEST HEAD

~~L~C~~~CE.

~:~~~~~~

I

!___ ~aUJVAlENT

CIRCUIT_ _ _

J

Burn-In Circuits
HM-65262/883 CERAMIC DIP

HM-65262/883 CERAMIC LCC

vee

F3 -'\oM.----I

vee

e

~

CD

u:

~e

F4 -'\fV''''''--1

F16

F5 -'\oM.----I

F15

oJ\j""'.----t

F14

F6

t-"llVV'- F15

F7 -'\fV''''''--1

F13

F7

t-"llVV'- F14

Fa -'\oM.----I

F12

Fa

_""",fV'~F13.

F9

-'\1\1\_--04

Fll

F9

t-"llVV'- F12

F2 -'\oM,......-"-I

FlO

F2

t-"llVV'- Fl1

F1.J\M_--I

F2

F6

FO

NOTES:
All Resistors 47kO. 5'110
FO = 100kHz :1:10'lI0
Fl -FO+2.
F2 = Fl + 2 ••.. F16 = F15 + 2
vee = 5.5V. :l:0.5V
VIH = 4.5V :1:10%
VIL = -0.2V to +0.4V
e = O.ot pF (Min)

NOTES:
5.5V :l:0.5V
VIH = 4.5V :1:10'lI0
VIL = -0.2V to +0.4V
Fl =FO+2.F2=Fl +2.
F3 = F2 + 2 •••• F13 = F12 + 2
FO = 100kHz :1:10'lI0
All Resistors 47kO.
= 0.01 pF (Min)

vee =

e

3-111

HM-65262/883

Metal Topology
DIE DIMENSIONS:
186.2 x 200.1 x 19 ±1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11k)!. ± 2kA
GLASSIVATION:
Type: Si02
Thickness: 8kA ± 1kA
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600C (Max)
Ceramic LCC - 4200 C (Max)
WORST CASE CURRENT DENSITY:
1.2 x 105 Ncm 2

Metallization Mask Layout
HM-65262/883

A2

A1

vcc

AO

A13

A12

A3

A11

.A4

A10

..

A5

A9

A6

AS

3-112

HM-65262/883
Packaging t
20 PIN CERAMIC DIP
.285
305
1r==·tt
==i1

O·

15'

• INCREASE MAX W.tIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FlNISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-8

>cna::

00

:;::;:
..,w
:;:

20 PAD CERAMIC LCC

.05D

~

.045
.055

BSC

~

I

.358

.063

"..c=====::LI--..l:;:;:!J .077

II n n n n n I
.073n
.089

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 3200 C ± 1QoC
Method: Furnace Braze

NOTE: All Dimensions are

~

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-2

t MiI-M-38510 Compliant Malerials, Finishes, and Dimensions.

• Dimensions are in Inches.

3-113

m

HM-65262

HARRIS

16K x 1 Asynchronous
CMOS Static RAM

DESIGN INFORMATION.

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
TYPICAL .ICCDR VS. TA

Vee = 2.0V

-3
-4

-5

-6

~

J

<:; -7
~

:

~

iE

....

./

-8

0

-9
-10
-11

-12

L/
-55

V

-35

V
-15

~.

V

~

,

~

!~

5

25

. 45

TA (DC)

3-114

65

85

105

125

m

HM-65642/883

HARRIS

8K
June 1989

8 Asynchronous
CMOS Static RAM

X

Features

Description

• This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

The HM-65642/883 is a CMOS 8192 x 8-bit Static
Random Access Memory. The pinout is the JECEC 28 pin,
8-bit wide standard, which allows easy memory board
layouts which accommodate a variety of industry standard
ROM, PROM, EPROM, EEPROM and RAMs. The
HM-65642/883 Is Ideally suited for use in microprocessor
based systems. In particular, interfacing with the Harris
80C86 and 80C88 microprocessors is simplified by the
input.
convenient output enable

•
•
•
•
•
•
•
•
•
•
•

Full CMOS Design
Six Transistor Memory Cell
Low Standby Supply Current ••••.•••••.••••• lOOfIA
Low Operating Supply Current ••••••••••••••• 20mA
Fast Address Access Time •.••••••••••••••••• 150ns
Low Data Retention Supply Voltage •••••••••••• 2.0V
CMOS/TTL Compatible Inputs/Outputs
JECEC Approved Pinout
Equal Cycle and Access Times
No Clocks or Strobes Required
Gated Inputs No Pull-Up or Pull-Down Resistors Required
• Temperature Range ••.••••••••••• -55 0 C to +125 0 C
• Easy Microprocessor Interfacing
• Dual Chip Enable Control

(Gi

The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full
military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection
against soft errors due to noise and alpha particles. This
stability also improves the radiation tolerance of the RAM
over that of four transistor or MIX-MaS (4T) devices.

>
::>ea

....
0 ''"
"
W
U

COLUMN SELECT
(8 OF 256)

A

a:
0
0

5

c:(

Vi
G

E1
8
E2
1 OF 8

TRUTH TABLE

MODE
Standby (CMOS)
Standby (TTL)
Enable (High Z)
Write
Read

E1

E2

Vi

G

X
VIH
X
VIL
VIL
VIL

GND

X
X
X
VIH
VIL
VIH

X
X
X
VIH
X
VIL

3-116

X
VIL
VIH
VIH
VIH

on

Specifications HM-65642/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••••••••••••••••••••••••••••••• +7.0V
Input or Output Voltage Applied for all grades •••••• GND -0.3V 10
VCC +0.3V
Storage Temperature Range ••••••••••••••••• -650C 10 +150 0 C
Lead Temperature (Soldering Ten Seconds) ••••••••••••. +3000 C
Junction Temperature •••••••••.•••••••••••••••••••••• +1750 C
Typical Derating Factor •••••••••..•.• 5mNMHz Increase in ICCOP
ESD Classification ••••••••.•••••••••.•••.•••••••.•••••• Class 1

Thermal Impedance Junction-to-Case (Bjel
Ceramic DIP •••••••••••••••••••••••••••••••••••••• BOCIW
Ceramic LCC ••••••••.•••••••••••••••••••••.••••• 45 0 CIW
Thermal Impedance Junction-to-Ambient (Bjel
Ceramic DIP ••••••••••••••••••••••••••••••••••••• 450 CIW
Ceramic LCC •••••••••••••••••••••••••••••••••••• 550 CIW
Maximum Package Power Dissipation at +1250 C
Ceramic DIP •••••••••••••...•••••••••••••••••••• 1.1 Watts
Ceramic LCC ••••.•••••••.•.•••••••.••••••••••• 0.90 Watts
Gate Count ••••••••.••••••••••••••••••.•••.••• 101,OOOGates

CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and
operation 01 the device at these or any other condiUons above those indicated in the operationl sections of this specification is not implied.

Operating Conditions
Operating Supply Voltage (VCC) •••••.•••••••••••••• 4.5V to 5.5V
Operating Temperature (TAl .•......•.•......• -55°C to +125 0 C
Input Low Voltage (VIL) •••••••••••••••••••••••.• -0.3V to +0.8V

Input High Voltage (VIH) ••.•••••.•••••••••• +2.2V to VCC +0.3V
Data Retention Supply Voltage ••••••••••••••••••••••••••• 2.0V
Input Rise and Fall Time •••••••••••••••••••.•..•••..• 40ns Max

TABLE 1. HM-65642/883 D.C. ELECTRICAL PERFORMANCe-CHARACTERISTICS

D.C. PARAMETERS

(NOTE 1)
CONDITIONS

SYMBOL

UMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

1,2,3

-550C ~TA~ +1250 C

2.4

-

V

-

0.4

V

=4.5V, 10 =-1.OmA

High Level Output
Voltage

VOH1

Low Level Output

VOL

vec =4.5V, 10 =4.0rnA

1,2,3

-55°C ~TA

IIOZ

=5.5\1, G =2.2V
= GND orVCC
VCC =5.5V, VI =GND orVCC
vec =5.5V, 10 =OmA,
E1 =vec -O.3Vor E2 =GND +O.3V
vec =5.5V,10 =OmA,
E1 =2.2V or E2 =O.BV
VCC =5.5\1,10 =OmA,
E1 =0.8\1, E2 =2.2V
VCC =5.5\1, G =5.5\1, (Note 5),
f =1 MHz, E1 =0.8\1, E2 =2.2V
VCC =2.0\1,10 =OmA,
E1 =VCC -o.3V or E2 =GND +O.3V
VCC =4.5V (Note 4)

1,2,3

-550C~TA~+1250C

-1.0

1.0

pA

1,2,3

-550C5TA~+1250C

-1.0

1.0

pA

1,2,3

-55°C 5TA5+1250C

-

250

pA

1,2,3

-550C5 TAS:+1250C

-

5

rnA

1,2,3

-55°C ~TA S:+1250 C

-

5

mA

1,2,3

-55°C 5 TA

s: +1250C

-

20

mA

1,2,3

-55°C

s: TA s: +1250C

-

150

pA

7,8A,BB

-55°C

s: TAS: + 125°C

-

-

-

VCC

s: +1250C

>ena:

Voltage
High Impedance Output
Leakage Current
Input Leakage Current

II

Standby Supply Current

ICCSB1

Standby Supply Current

ICCSB

Enable Supply Current

ICCEN

Operating Supply
Current

ICCOP

Data Retention
Supply Current

ICCDR

Functional Test

FT

VCC
VIIO

NOTES: 1. All voltages referenced to device GND.

=

2. A.C. measurements assume transition time.:s 5ns; input levels O.OV
CL ~ 5OpF, for CL > 50pF. access times are derated O.15nS/pF.

to 3.0V; timing reference lavels

= 1.5Vj

output load = 1TTL equivalent load and

3. For timing waveforms see Low Voltage Data Retention and Read/Write Cycles.

= 2MHz, VlH = 2.4V. VIL = O.4V,IOH = -4.0mA,IOL = 4.0mA. VOH ~ 1.5V. and VOL..s 1.5V.
= SmNMHz increase in ICCOP.

4. Tested as follows: f
5. Typical derating

"
CAUTION: These deVICeS are sensitive
to electrostatic discharge. Proper Ie handling procedures should be followed.

3-117

QQ

::E::E
UW
::E

Specifications HM-65642/883
TABLE 2. HM-65642/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

A.C. PARAMETERS

(NOTES 1, 2,3)
CONDITIONS

SYMBOL

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

9,10,11

-55°C ::::TA:5 + 125°C

150

-

ns

TAVAX

vee = 4.5V and 5.5V

Address Access Time

TAVOV

vee = 4.5V and 5.5V

9,10,11

-550e:5TA:5+1250e

ns

TGLOV

vee = 4.5V and 5.5V

9,10,11

-550e:5TA:5+1250e

-

150

Output Enable
Access Time

70

ns

Chip Enable Access
Time

TE1LOV
TE2HOV

vee = 4.5Vand 5.5V

9,10,11

-550e:5TA:5+1250e

-

150

ns

Write Recovery
Time

TWHAX
TE1HAX
TE2LAX

vee = 4.5V and 5.5V

9,10,11

-550e:5TA:5+1250e

10

-

ns

Chip Enable to
End-ot-Write

TE1LE1H
TE2HE2L

vee = 4.5V and 5.5V

9,10,11

-550C :5TA:5+1250e

90

-

ns

Address Setup Tinie

TAVWL
TAVE1L
TAVE2H

vee = 4.5V and 5.5V

9,10,11

-550C :5TA:5 +125 0 e

0

-

ns

Write Enable Pulse
Width

TWLWH

vee = 4.5V and 5.5V

9,10,11

-550e:5TA:5+1250e

90

-

ns

Data Setup Time

TDVWH
TDVE1H
TDVE2L

vee = 4.5V and 5.5V

9,10,11

-550e:5TA:5+1250e

60

-

ns

-

ns

Read/Write/eycle
Time

Data Hold Time

TWHDX

vee = 4.5V and 5.5V

9,10,11

-55 0 e :5TA:5 +125 0 e

5

TE1HDX

vee = 4.5V and 5.5V

9,10,11

-550e:5TA:5+1250e

10

TE2LDX

vee = 4.5V and 5.5V

9,10,11

-550e:5TA:5+1250e

10

ns
ns

NOTES: 1. All voltages referenced to device GND.
2. A.C. measurements assume transition time 5 5ns; input levels = o.ov to 3.0V; timing reference levels
and CL 2::: SOpF. for CL > SOpF, access times are derated O.15ns/pF.

= 1.SV; output load =

3. For timing waveforms see Low Voltage Data Retention and Read/Write Cycles.
4. Tested as follows: f

= 2MHz. VIH = 2.4V, VIL = O.4V,IOH = -4.0mA,IOL = 4.0mA, VOH::

5. Typical derating = SmA/MHz increase in ICCOP.

3-118

1.SV, and VOL.::: 1.SV.

1TTL equivalent load

Specifications HM-65642/883
TABLE 3. HM-65642/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERS

SYMBOL

Output High Voltage

VOH2

Input Capacitance

elN

VO Capacitance

CliO

NOTES

TEMPERATURE

MIN

MAX

UNITS

1

-5S0 e=:'TA=:'+12S0 C

vce0.4

-

V

vee = Open, f = 1 MHz,
All Measurements
Referenced to Device Ground

1,2

TA=+2so e

-

12

pF

vec = Open, f = 1 MHz
All Measurements
Referenced to Device Ground

1,3

TA=+2S0 e

-

10

pF

VCC = Open, f = 1 MHz
All Measurements
Referenced to Device Ground

1,2

TA=+25 0 e

-

14

pF

vee = 4.5V, VI/O = GND or vee,
All Measurements
Referenced to Device Ground

1,3

TA=+2S0 e

-

12

pF

CONDITIONS
vee = 4.SV,IO = -1001lA

Write Enable to
Output in High Z

TWLOZ

vec = 4.5V and S.SV

1

-SSOe=:.TA=:'+12S0 e

-

SO

ns

Write Enable High
to Output ON

TWHOX

vec = 4.SV and S.SV

1

-SSOe=:.TA=:'+12S0 C

S

-

ns

Chip Enable to
Output ON

TE1LOX
TE2HOX

vec = 4.SV and S.SV

1

-5S oe=:.TA.=£.+125 0 C

10

-

ns

00

TGLOX

vee = 4.S and S.SV

1

-S50 C=:'TA=:'+12S0 C

S

-

ns

Chip Enable to
Output in High Z

TE1HOZ

vee = 4.5V and S.SV

1

-SSOe=:.TA=:'+12S0 C

-

SO

ns

1

-SSoC=:.TA=:.+1250 e

-

60

ns

Output Disable to
Output In High Z

TGHOZ

vee = 4.SV and S.SV

1

-SSOC=:.TA=:.+12S0 e

-

SO

ns

Output Hold from
Address Change

TAXOX

vee = 4.5V and S.SV

1

-SSOe=:.TA=:'+12S0 C

10

-

ns

TE2LOZ

NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design release and upon design changes which would affect these characteristics.
2. Applies to DIP device types only. For design purposes CIN = 6pF typical and CliO

= 7pF typical.

3. Applies to LCC device types only. For design purposes CIN = 4pF typical and CliO = 5pF typical.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

GROUPS METHOD

SUBGROUPS

Interim Test 1

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

100%/5004

2,3, SA, SB, 10,11

Group A

Samples/SOOS

1,2,3,7,SA,SB,9,10,11

Groups e and D

Samples/SOOS

1,7,9

3-119

====
==

c.:>W

Output Enable to
Output ON

Final Test 1

>",cr:

Specifications HM,..65642B/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ..•.••.•.•••••••••••••••••••••••••••••.• +7.0V
Input or Output Voltage Applied lor all grades •••••• GND -0.3V to
VCC +0.3V
Storage Temperature Range .•••.••••••..•••• -650C to +1500 C
Lead Temperature (Soldering Ten Seconds) ••.•.•.•••.•• +3000 C
Junction Temperature ....•.......•.••.•.••.•••..••••. +1750 C
Typical Derating Factor •••••••••.•• 5mNMHz Increase in ICCOP
ESD Classification .••"••.••.••••.••••••••.•.••••.••.••• Class 1

Thermal Impedance Junction-to-Case (Ojel
Ceramic DIP •.••.•••••••••.•••.•••••••.•.......••• BOCIW
Ceramic LCC .• "..••.•••..•.•.....•.••••••••.••.•• 45 0 CIW
Thermal Impedance Junction-to-Ambient (Ojal
Ceramic DIP •.••••••••••.••.•.•••••.••••••.•....• 450 CIW
Ceramic LCC •...........•.....••••.••••.•••••.•. 550 CIW
Maximum Package Power Dissipation
Ceramic DiP ••••••.••••••••••.•.••••••••.....•.• 1.1 Watts
Ceramic LCC •••••.••••.•••••..•••••••.•.•..••• 0.90 Watts
Gate Count •••••.•..•.•••••••.•••••.•••.•...•• 101,000 Gates

CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Supply Voltage (VCC) •.•••••••.••.••••••• 4.5V to 5.5V
Operating Temperature (TAl .•.......•.•....•. -550 C to +1250 C
Input Low Voltage (VIL) •.••••.••.••••.••.••••••• -0.3V to +O.BV

Input High Voltage (VIH) •.•.••••••.•.•••... +2.2V to VCC +0.3V
Data Retention Supply Voltage ••••.•••••.••••.•••...•.••. 2.0V
Input Rise and Fall Time •.•.••••••...•......••••••••• 40ns Max

TABLE 1. HM-65642B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

D.C. PARAMETERS

(NOTE 1)
CONDITIONS

SYMBOL"

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

High Level Output
Voltage

VOHl

VCC

=4.511,10 =-l.OmA

1,2,3

-550C~TA~+125OC

2.4

-

V

Low Level Output
Voltage

VOL

VCC

=4.511, 10 =4.omA

1,2,3

-55OC :STA:S +1250C

-

0.4

V

High Impedance Output
Leakage Current

IIOZ

VCC

=5.511, G =22.V

1,2,3

-55OC~TA:5.+1250C

-1.0

1.0

pA

1,2,3

-550 C :S TA:5. +1250C

-1.0

1.0

pA

1,2,3

-550C:S.TA:S+1250C

-

100

pA

1,2,3

-550C:S.TA:5.+1250C

-

5

mA

1,2,3

-550C :STA:S +1250 C

-

5

mA

1,2,3

-55°C :STA:S +1250 C

-

20

mA

1,2,3

-550C~TA:5.+1250C

-

75

pA

7,8A,B8

-550C :STA~+1250C

-

-

-

WO= GNDorVCC

Input Leakage Current

II

Standby Supply Current

ICCS81

Standby Supply Current

ICesB

Enable Supply Current

ICCEN

Operating Supply
Current

ICCOP

Data Retention
Supply Current

ICCDR

Functional Test

FT

NOTES: 1. All voltages referenced

=5.511, VI =GND orVCC
VCC =5.5V,10 =OmA,
E1 =vec -O.3V or E2 =GND +O.3V
VCC =5.5V,10 =OmA,
E'i =22.V or E2 =OJ!N
VCC =5.511,10 =OmA,
E'i =0.811, E2 =2.2V
VCC =5.511, G =5.5V, (Note 5),
I =1 MHz, E1 =0.811, E2 =2.2V
VCC =2.011,10 =OmA,
E1 =vec -O.3V or E2 =GND +O.3V
VCC =4.5V (Note 4)
VCC

to device GND.

2. AC. measurements assume transition time'S 5ns; input levels = O.OV to 3.OV; timing reference levels = 1.5V; output, load:::: 1TTL equivalent load and
CL ~ 50pF, for CL

> 5OpF, access times are derated O.15nS/pF.

3. For timing waveforms see Low Voltage Data Retention and Read/Writa Cycles.
4. Tested as follows: f

= 2MHz, V1H = 2.4V. VIL = O.4V, IOH = -4.0mA. IOL = 4.QmA. VOH

~

1.5V. and VOL::: 1.511.

5, Typical derating ... SmA/MHz increase in ICooP.

CAUTION: These devices are sensHive to electrostatic discharge. Proper IC handling procedures should be followed.

3-120

Specifications HM-65642B/883
TABLE 2.

HM-6S642B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

(NOTES 1, 2, 3)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

TAVAX

VCC

=4.5V and S.SV

9,10,11

-55°C 5.TA5.+12So e

150

-

ns

Address Access Time

TAVQV

vee

-550C SoTA5. +125 0 e

ns

vee

9,10,11

-550C 5.TA5. +125 0 e

-

150

TGLQV

=4.5V and S.5V
=4.5V and 5.5V

9,10,11

Output Enable
Access Time

70

ns

Chip Enable Access
Time

TE1LQV
TE2HQV

vee

=4.5V and 5.5V

9,10,11

-550C 5.TASo +125 0 e

-

150

ns

Write Recovery
Time

TWHAX
TE1HAX
TE2LAX

vee

=4.5V and 5.5V

9,10,11

-55°C s..TA So +125 0 e

10

-

ns

Chip Enable to
End-ol-Write

TE1LE1H
TE2HE2L

vee

=4.5V and 5.5V

9,10,11

-550e~TA5.+1250e

90

-

os

Address Setup Time

TAVWL
TAVE1L
TAVE2H

vee

=4.5V and 5.5V

9,10,11

-550es..TA5.+1250e

0

-

ns

Write Enable Pulse
Width

TWLWH

vee

=4.5V and 5.5V

9,10,11

-55°C 5. TASo +125 0 e

90

-

. os

Data Setup Time

TDVWH
TDVE1H
TDVE2L

vee

=4.5V and 5.5V

9,10,11

-550es..TA~+1250e

60

-

os

A.C. PARAMETERS

SYMBOL

Read/Write/eycle
Time

TWHDX

Data Hold Time

TE1HDX
TE2LDX

>",a::

=4.SV and 5.5V
=4.5V and 5.5V
vee =4.5V and 5.5V

00

vee

9,10,11

-55°C So TA So +1250 e

5

9,10,11

-550 e.sTASo +1250 e

10

-

ns

vee

9,10,11

-550e.sTA=::+1250e

10

-

ns

ns

NOTES: 1. All voltages referenced to device GND.

2. A.C. measurements assume transition time < 5ns; input levels = O.OV to 3.0V; timing reference levels
and CL ~ 50pF, for CL > 50pF. access tim;S are derated O.15ns/pF.

= 1.5V; output load = 1TTL equivalent load

3. For liming waveforms sea low Voltage Data Retention and Read/Write Cycles.
4. Tested as follows: f
5. Typical derating

= 2MHz, VIH = 2.4V, Vil = O.4V, IOH = -4.0mA, IOl = 4.0mA, VOH ~ 1.SV, and VOL So 1.SV.

= SmA/MHz

increase in ICCOP.

3-121

::::::
c..>W

:::

SpecificationsHM':'65642B/883
TABLE 3.

HM-65642B/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS

PARAMETERS
Oulpul High Voltage

SYMBOL
VOH2

Inpul Capacilance

CIN

I/O Capacitance

el/o

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

1

-S50C::;TA.!>.+1250 C

VCC0.4

-

V

vce = 4.5\1, 10 = -100flA

VCC = Open, f = 1MHz,
All Measuremenls
Referenced 10 Device Ground

1,2

TA=+250 e'

-

12

pF

vce = Open, f = 1MHz
All Measurements
Referenced 10 Device Ground

1,3

TA=+2S0 e

-

10

pF

vee = Open, f= 1MHz
All Measurements
Referenced 10 Device Ground

1,2

TA=+250 e

-

14

pF

vee = 4.5V, VI/O = GND or vee,
AII-Measuremenls
Referenced 10 Device Ground

1,3

TA=+25 0e

-

12

pF

SO

ns

..

Write Enablii 10
Oulpulln High Z

TWLOZ

vee = 4.5V and 5.SV

1

-S50 e ~TA~+1250e

-

Wrile Enable High
10 OuipulON

TWHOX'

vee = 4.5V.and 5.5V

1

-S50e~TA~+1250e

5

-

ns

Chip Enable 10
OuipulON

TE1LOX
TE2HOX

vee = 4.5V and 5.SV

1

-550 e ~TA.!>.+12S0e

10

-

ns

vee = 4.5 and 5.SV

1

-S50e.!>.TA~+1250e

5

-

ns

Oulpul Enable to
OuipulON

TGLOX

Chip Enable 10
Oulpul in High Z

TE1HOZ

vee = 4.5V and 5.5V

TE2LOZ

1

-550 e ::;TA::;+12S0e

-

SO

ns

1

-550e~TA::S:+12soe

-

60

ns

Oulpul Disable 10
Oulpul in High Z

TGHOZ

vee = 4.SV and 5.SV

1

-550 e ~TA::;+1250e

-

SO

ns

Output Hold from
Address Change

TAXOX

vee = 4.5V and 5.5V

1

~S50e::;TA::;+1250e

10

-

ns

NOTES: 1. The parameters listed In Tabla 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon Initial design release and upon design changes which would affect these characteristics.
2. Applies to DIP device types only. For design purposes CIN = 6pF typical and CliO = 7pF typical.
3. Applies to LCC device types only. For design purposes CIN = 4pF typical and CliO = 5pF typical.

TABLE 4.
CONFORMANCE GROUPS

APPLICABLE SUBGROUPS

GROUPS METHOD

SUBGROUPS

Interim Tesl1

100%/5004

-

Interim Tesl

100%/SOO4

1,7,9

PDA

100%/SOO4

1

Final Test 1

100%/5004

2,3, 8A, 8B,10,11

Group A

Samples/SOOS

1,2,3,7,8A,BB,9,10,11

Groups e and D

Samples/SOOS

1,7,9

3-122

HM-65642/883

Low Voltage Data Retention
Harris CMOS RAMs are designed with battery backup in mind. Data Retention voltage and supply current are guaranteed
over the operating temperature range. The following rules ensure data retention:
1. The RAM must be kept disabled during data retention. This is accomplished by holding the E2 pin between -0.3V and
GND.
2. During power-up and power-down transitions, E2 must be held between -0.3V and 10% of VCC.
3. The RAM can begin operating one TAVAX after VCC reaches the minimum operating voltage of 4.SV.

DATA RETENTION MODE

vee
4.5V
VIH

E2

veeDR
GNO

Read Cycles
READ CYCLE I:

Vi,

E2 HIGH;

G, E'i

LOW

>",a:

TAVAX

QQ

====
==

UIU

A

READ CYCLE II:

TAVAX

TGLQV
TGLQX

3-123

Vi HIGH

HM-65642/883

Write Cycles
WRITE CYCLE I: LATE WRITE

TAVAX

X:

A

e<.
TAVWl

.rWlWH

TWHAX

\\\\i

l//LUUUU//ULULil

'!f1f.f-

~\\\\\\\\\\\\\\\\W

E2

TWHQX
TWHOX

TOVWH

1

o

TWLQZ
Q

=

xxxxxxxxxxxxxwx
WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1

TAVAX
~

A

XJTAVE2H

Pi

TE2lA~

TE2HE2l

~

IIIIIIIIIIIIIIL

~

IIIIIIIIIIIIII!

...

E2

TE2l0X

TDVE2l

WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2

TAVAX

A

......

X:

~X

TAVEl L

TElHA~

TEl LEI H

w~

/ / / / / / /////////,
T

E2

~

\\\\\\\\\\\\\\'\

'1iiiI

TDVEIH

I
I

3-124

TElHO~

HM-65642/883

Test Circuit

OUT

r-----------.......,
I
I
I
I
I
I
t IOL I
I
I

~arrH~O
~~:~~~~I
~.:-;,:'~:'

I

1 _ _ _ EOUIVALENT_CIRCUIT _ _ _

I

Burn-In Circuits
HM-65642/883 CERAMIC DIP

HM-65642/883 CERAMIC LCC

C

F15

F9
FB

Fl
A7
A6
A5

F7

A4
A3

F4

1L 1L

A12

F6
F5

vee

co

1L 1L

NC

FlO

co

0

E-GND

A2
Al

:c

F16
F11
F9
F12

FB

F14

A6
A5

FS

F13

F5

FO

F4

F3

F2

F3

F2

F2

F2

F2

F2

F2

_.

13

>

51 L~J L~J LZJ L!~ L=!.

F7

FO

N

:(

DOS

F2
F2

::e::e
...
::e
~

HM-65642/883
Die Characteristics
DIE DIMENSIONS:
276.S x 305.5 x 19 ± 1 mils
METALLIZATION:
Type: 51 -AI
Thickness: 11 k.3. ±

2kA

GLASSIVATION:
Type: 5102
Thickness: skA to ± 1kA

DIE ATTACH:
Material: Gold/Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCe - 420 0 e (Max)
WORST CASE CURRENT DENSITY: 0.9 x 105 Amps/cm 2

Metallization Mask Layout
HM-65642/883

3-126

HM-65642/883
Packaging t
28 PIN CERAMIC DIP

1.440

~~1.47~0Ij:::

.--------.oo5
MIN

'~:'~'lil}

.125

JL~ ~

~

!! li

O'

15'

.098 MAX

.~~~

.:!!!!.

.180

MIN

.023

.050• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
• SOLDER ANISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Aluminum
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C to ±100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-10

32 PAD CERAMIC LCC

.540

.560

.055

.045

f - - - - - .442
.458

II
PAD MATERIAL: Type C
PAD FINISH: Type A .
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic 90% Alilminum
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 320 0 C ±100C
Method: Furnace Braze
NOTE: All Dimensions are

~:c

.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-12

t MiI-M-38510 Compliant Materials, Finishes, and Dimensions.

Dimensions are in inches.

3-127

HM-65642

mHARRIS

8K x 8 Asynchronous·
CMOS Static RAM

DESIGN INFORMATION

The information contained in this section has been deve/oped.through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

TYPICAL ICCDR

v~.

TA

Vcc = 2.0V

-3
-4

~

-5
-6

«

-::

~

-7
-.
t.l

./

i:5" -8
0

....

-9
-10
-11
-12

.L
-55

V

-35

V

",.

./

I

-15

V

~

",.

I

5

I

25

45
TA (DC)

3-128

65

85

105

125

m

HARRIS

HM-65642C/883
8K

June 1989

8 Asynchronous
CMOS Static RAM

X

Features

Description

• This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

The HM-65642C/883 is a CMOS 8192 x 8-bit Static
Random Access Memory. The pinout is the JEDEC 28 pin,
8-bit wide standard, which allows easy memory board
layouts which accommodate a variety of industry standard
ROM, PROM, EPROM, EEPROM and RAMs. The
HM-65642C/883 is ideally suited for use in microprocessor based systems. In particular, interfacing with the Harris
80C86 and 80C88 microprocessors is simplified by the
convenient output enable (<3) input.

•
•
•
•
•
•
•
•
•
•
•

Full CMOS Design
Six Transistor Memory Cell
Low Standby Supply Current ••••••.••••••••• 400"A
Low Operating Supply Current ••••••.•••••••• 20mA
Fast Address Access Time ••••••••••.•••••••• 200ns
Low Data Retention Supply Voltage •••••••••••• 2.0V
CMOS/TTL Compatible Inputs/Outputs
JEDEC Approvec;l Pinout
Equal Cycle and Access Times
No Clocks or Strobes Required
Gated Inputs No Pull-Up or Pull-Down Resistors Required
• Temperature Range •••••••••••••• -55 0 C to +125 0 C
• Easy Microprocessor Interfacing
• Dual Chip Enable Control

The HM-65642C/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full
military temperature range. In addition to this, the high
stability of the 6T RAM cell provides excellent protection
against soft errors due ·to noise and alpha particles. This
stability also improves the radiation tolerance of the RAM
over that of four transistor or MIX-MaS (4T) devices.

>",a:

00

====
==

UW

Pinouts
HMl-65642C/883 (CERAMIC DIP)
TOP VIEW

HM4-65642C/883 (CERAMIC LCC)
TOP VIEW

NC
A12

_" L~J L§J L~J t~J L=!~ L=!1J L=!
:::>'"

5

c ...
"a:

A

...

~

co
co

COLUMN SELECT
(8 OF 256)

5

cc

w

8
L - _ -......-4-f-OQ

E2

1 OF 8

TRUTH TABLE
MODE
Standby (CMOS)
Standby (TTL)
Enable (High Z)
Write
Read

E1

E2

X

GND

VIH

X

X

'VIL
VIH
VIH
VIH

VIL
'ViL
VlL

3-130

-

W

G

X
X
X

X
X
X

VlH
VIL
VlH

VIH

X
VIL

Specifications HM-65642C/883
Absolute Maximum Ratings

Reliability Information

SupplyVoitage •••••••••..•••••••.•.••.••••.•••••••...• +7.0V
Input or Output Voltage Applied for all grades ..•..• GND -0.3V to
VCC +0.3V
Storage Temperature Range ••.•••.•.•....... -650C to +150 0 C
Lead Temperature (Soldering Ten Seconds) .........•..•. 3000C
Junction Temperature •.•...•..•.•.•••.•.••.••••.•..••• +175 0C
ESD Classification ....••.•..........•...•.........•••• Class 1
Typical Derating Factor .•••.......• SmA/MHz Increase in ICCOP

Thermal Impedance Junction-to-Case (Oid
Ceramic DIP •....•.•••......•••••....•••....•••••• 8 0 C/W
Ceramic LCC ., ................................... 450 C/W
Thermal Impedance Junction-to-Ambient (Oja)
Ceramic DIP .••••••••.•.••.••.•.•.••••...••••.... 45 0 C/W
Ceramic LCC •.•.....•.•••.••.•..•.•.•••.•••.•.•• 550 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DiP .....•.•.•......••.......•.•...•••.•• 1.1 Watt
Ceramic LCC ••.••••••••.•.••.•••.•••......•.•.. 0.90 Watt
Gate Count .•.•.•.•......•.•.••.•..••.••.••.•• 101,000 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of Ihis specification is not implied.

Operating Conditions
Operating Supply Voltage (VCC) ••.•••••..•.••••.••• 4.5V to 5.5V
Operating Temperature (TJIl ...........•...... -55°C to +125 0 C
Input Low Voltage (VIL) ...••.••.......••••.•.•.. -0.3V to +0.8V

Input High Voltage (VI H) ••......•••••....•.•.•... +2.2VtoVCC
Data Retention Supply Voltage • . . . . • • • . • . . . . . • . • . . . . • • • .• 2.0V
Input Rise and Fall Time •••••.•.••.•••.••••.•.•••••.. 40ns Max

TABLE 1. HM-65642C/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

D.C. PARAMETERS

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

High Level Output
Voltage

VOH1

VCC = 4.5V,10 =-1.0mA

1,2,3

-55°C '::;TA ~ +12SoC

2.4

-

V

Low Level Output
Voltage

VOL

VCC = 4.51(,10 = 4.0mA

1,2,3

-55°C '::;TA ~ +12SoC

-

0.4

V

High Impedance Output
Leakage Current

1I0Z

VCC = 5.51(, G = 2.2V
VIIO = GNDorVCC

1,2,3

-55°C .::;TAS +12SoC

-2.0

2.0

pA

Input Leakage Current

II

Standby Supply Current

ICCSB1

Standby Supply Current

ICCSB

VCC = 5.51(, VI = GND orVCC

1,2,3

-55°C STAS +1250C

-2.0

2.0

pA

VCC = 5.S1(,10 = OmA,
Ei = VCC -O.3V or E2 = GND +O.3V

1,2,3

-S50C ::STAS:+12So C

-

400

pA

VCC = 5.S1(,10 = OmA,

1,2,3

-55°C s: TAS + 12SoC

-

5

mA

1,2,3

-S50C STAS +12SoC

-

5

mA

E1 = 2.2V or E2 = O.8V
Enable Supply Current

ICCEN

VCC = 5.51(,10 = OmA,

Ei = 8.0V, E2 = 2.2V
Operating Supply
Current

ICCOP

VCC = 5.51(, G = 5.SI(, (Note 5),
f = 1 MHz, E1 = O.8V, E2 = 2.2V

1,2,3

-5So C s:TAS+12S0 C

-

20

mA

Data Retention
Supply Current

ICCDR

vec = 2.01(,10 = OmA,
E1 = VCC -o.3Vor E2 = GND +O.3V

1,2,3

-5SoC s: TA s: +12SoC

-

250

pA

Functional Test

FT

s: +12SoC

-

-

-

VCC = 4.5V (Note 4)

7,8A,8B

-55°C S:TA

NOTES: 1. All vollages referenced 10 VSS.
2. AC. measurements assume transHion time ~ 5nsj input levels r:z ODV to 3.OVi timing reference levels = 1.5V; output load = 1TTL equivalent load and
CL 2: 5OpF, for CL > 5OpF, access times are derated O.1SnsJpF.

3. For timing waveforms see Low Voltage Data Retention and Read/Write Cycles.
4. Teslad as follows: f = 2MHz, V1H = 2.4V, VIL = O.4V,IOH = -4.DmA, IOL = 4.0mA, VOH
5. Typical derating

~

1.SV, and VOL.$. 1.SV.

= SmA/MHz increase in ICooP.

CAUTION: The.. dovicos are "nsHivelo electrostatic discharge. Proper Ie handling procedures should be followed.

3-131

Specifications HM-65642C/883
TABLE 2. HM-65642C/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

A.C. PARAMETERS

(NOTES 1, 2, 3)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

TAVAX

vee = 4.5V and 5.5V

9,10,11

-55°C ~TA S+1250e

200

-

ns

Address Access Time

TAVOV

vee = 4.5V and 5.5V

9,10,11

-550 eSTAS+1250e

ns

TGLOV

vee = 4.5V and 5.5V

9,10,11

-550 eSTAS+1250e

-

200

Output Enable
Access Time

70

ns

Read/Write/eycle
Time

SYMBOL

Chip Enable Access
Time

TE1LOV
TE2HOV

vee

= 4.5V and 5.5V

9,10,11

-550C :STA~+1250e

-

200

ns

Write Recovery
Time

TWHAX
TE1HAX
TE2LAX

vee

= 4.5V and 5.5V

9,10,11

-550C :STA:S +1250 e

10

-

ns

Chip Enable to
End-ol-Write

TE1LE1H
TE2HE2L

vee = 4.5V and 5.5V

9,10,11

-550C STA~+1250e

120

-

ns

Address Setup Time

TAVWL
TAVE1L
TAVE2H

vee

= 4.5V and 5.5V

9,10,11

-550e:s TA S +125 0 e

0

-

ns

Write Enable Pulse
Width

TWLWH

vee = 4.5V and 5.5V

9,10,11

-55°C STA~ +125 0 e

120

-

ns

Data Setup Time

TDVWH
TDVE1H
TDVE2L

vee = 4.5V and 5.5V

9,10,11

-550esTA~+1250e

80

-

ns

TWHDX

vee = 4.5V and 5.5V

9,10,11

-550C ~TA~ +1250 e

5

-

ns

TE1HDX

vee

= 4.5V and 5.5V
vee = 4.5V and 5.5V

9,10,11

-550C ~TA~ +1250 e

10

-

ns

9,10,11

c550 e  50pF. access times are derated O.15ns/pF.
3. For timing waveforms see low Voltage Data Retention and Read/Write Cycles.
4. Tested as follows: f = 2MHz. VIH = 2.4V, VIL = O.4V.IOH = -4.0mA.IOL = 4.0mA. VOH ~ 1.SV. and VOL S 1.SV.
5. Typical derating = SmNMHz increase In recop.

3-132

Specifications HM-65642C/883
TABLE 3. HM-65642C/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
UMITS
PARAMETERS

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

CIN

VCC = Open, All Measurements
f=1MHz,
Referenced to Device Ground

1,2

TA=+2S0 C

-

12

pF

VCC = Open, All Measurements
f=1MHz,
Referenced to Device Ground

1,3

TA=+2S0 C

-

10

pF

VCC = Open, All Measurements
f=lMHz,
Referenced to Device Ground

1,2

TA=+2So C

-

14

pF

VCC = Open, All Measurements
f=1MHz,
Referenced to Device Ground

1,3

TA=+2S0 C

-

12

pF

Input Capacitance

I/O Capacitance

CI/O

Write Enable to
Output in High Z

TWLQZ

VCC = 4.SV and S.SV

1

-SSoC S TA S + 12So C

-

70

ns

Write Enable High
to Output ON

TWHQX

VCC = 4.SV and S.SV

1

-SSoC STA S+12S0 C

S

-

ns

Chip Enable to
Output ON

TE1LQX
TE2HQX

VCC = 4.SV and S.SV

1

-SSoC ::; TA::; + 12SoC

10

-

ns

VCC = 4.S and S.SV

1

-SSoC STA:S+12S 0C

S

-

ns

VCC = 4.SV and S.SV

1

-SSOC::;TA:S +12S oC

-

70

ns

70

ns

Output Enable to
Output ON

TGLQX

Chip Enable to
Output in High Z

TE1HQZ
TE2LQZ

Output Disable to
Output in High Z

TGHQZ

VCC = 4.SV and S.SV

1

-SSoC STA:S +12So C

-

60

ns

Output Hold from
Address Change

TAXQX

VCC = 4.SV and S.SV

1

-SSoC :STA:S+12S 0C

10

-

ns

1

-SSoC S TAS + 12SoC

VCC
-0.4

-

V

Output High Voltage

VOH2

VCC = 4.SV, 10 =

-100~A

NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design release and upon design changes which would affect these characteristics.
2. Applies to DIP device types only. For design purposes CIN = 6pF typical and CItO = 7pF.
3. Applies to LCC device types only. For design purposes CIN = 4pF typical and CItO = 5pF typical.

TABLE 4. APPUCABLE SUBGROUPS
CONFORMANCE GROUPS

GROUPS METHOD

SUBGROUPS

Interim Test

100%/S004

-

Interim Test

100%/SOO4

1,7,9

PDA

100%/S004

1

Final Test

100%/SOO4

2,3, 8A, 8B, 10,11

Group A

Samples/SOOS

1,2,3,7,8A,8B,9,10,11

Groups C and D

Samples/SOOS

1,7,9

3-133

HM-65642C/883
Low Voltage Data Retention
Harris CMOS RAMs are designed with battery backup In mind. Data Retention voltage and supply current are guaranteed
over the operating temperature range. The following rules ensure dlila retention:
1. The RAM must be kept disabled during data retention. This is accomplished by holding the E2 pin between -0.3Vand
GND.
2. During power-up and power-down transitions, E2 must be held between -0.3V and 10% of VCC.
3. The RAM ,can begin operating 'one TAVAX after VCC reaches the minimum operating voltage of 4.5V.

DATA RETENTION MODE
vee
4.5V
VIH
E2
VeeDR

GND

Read Cycles
READ CYCLE I:

W, E2 HIGH; G, E1

LOW

TAVAX
A

)G

ADDRESS I
TAVOV

EX
J

ADDRESS 2
TAXOX

I
XXXX~

XX

J

I
)j;Xxyy'

DATA I

READ CYCLE II:

DATA 2

X'X'X'X'X'X'

W HIGH

TAVAX (I)

A
TAVOV

TEILOV
TEl LOX
E2
TE2HOV
TEZHOX

if

~~~~~~T~GL~OV~-+--~-----------------4~~~~~~~

TGLOX
Q

3-134

HM-65642C/883

Write Cycles
WRITE CYCLE I: LATE WRITE

TAVAX

B<

Xi

A

TAVWL

E2

TWHAX

TWLWH

~

////////////////////J

1fa

\\\\\\\\\\\\\\\\\\ \ \~
TWHQX
D'lHOX

TOVWH

I

o
TWLQZ.

=

xxxxxxxXXXXXXXXX

Q

WRITE CYCLE II: EARLY WRITE - CONTROLLED BY

E1

>-

TAVAX

A

"'..:
00

~X

X~
TAVEIL

TEIHAX

TEl LEIH

W~

IIUfllllllllll,

Ei

-'r

E2

-f-

\\\\\\\\\\\\\\'\

'J1U/

TElHDX

TOVEIH

I

o

I
WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2

TAVAX

A

)G'"

TAVE2H

TE2HE2L

TE2LAX

Px

Vi ~

1///1/////////1

~

IIIIIIIIIIIIII/'
-'

E2

TOVE2L

o

3-135

TE2LDX

::e::e
..,w
::e

HM-65642C/883
Test Circuit

.-------------.
I
I
I
OUT
I
I
I
tlOl
I
I
1
~A~tuC~:NCE. I
I
*TEST HEAD

~~::.~~~~~::' 1 _ _ _

EQUIVALENT_CIRCUIT _ _ _ I

Burn-In Circuits
HM-65642C/883 CERAMIC DIP

HM-65642C/883 CERAMIC LCC
C
E-GND

0

NC
F15

Fl

FlO

F16

F9

Fll

~

F8

F12

F9

F7

F14

F8

F6

FO

F5
F4

F13
Al

FO

F3

F2

F2

F2

F2

F7
F6
F5
F4
F3

F2

F2

~

:;:'"
A8

A5

A9

A4
A3
A2
Al
AO

71

All

8'

Ne

-"
-,
-"

~J

19-,
l}J

DOD

F2
F2

NOTES:

NOTES:

FO = 100kHz ±10%
All Resistors 47kO, 5%
e = 0.01 pF (Min)
vee = 5.5V, ±0.5V
VIN = 4.5V, ±10%
Vil = -0.2V to +0.4V

FO = 100kHz ±10%
All Resistors 47kO, 5%
e = 0.01 pF (Min)
vee = 5.5V ±0.5V
VIN = 4.5V ±10%
Vil = -0.2V to +0.4V

3-136

vee

u:: u::'"

A6

Ne 1~

DQl

F2

I/)

u:: u::

G
Al0
Et
007

DOS

F11
F12
F14

FO
Ft3
FO
F2
F2

HM-65642C/883
Die Characteristics
DIE DIMENSIONS:
276.a x 305.5 x 19 ± 1 mils
METALLIZATION:
Type: Si - AI
Thickness: 11k)!. ± 2kA
GLASSIVATION:
Type: Si02
Thickness: akA to,± 1kA
DIE ATTACH:
Material: Gold/Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE, CURRENT DENSITY: 0.9 x 105 Amps/cm 2

Metallization Mask Layout
HM-65642C/883

3-137

HM-65642C/883

Packaging t
28 PIN CERAMIC DIP

1.440

I

j"M

I

1.470

,-'"-1.--

.150

=~~~~~li~
:V VVJ¥LMI I~ ~ J~

.125

o·
15'

.098 MAX

..:2!!.

.180

.~~~

-

.023
.050·

_
• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER Of fLAT fOR SOLDER RNISH

.065

LEAD MATERIAL: Type B
_
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Aluminum
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C to ±100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 MilBonding Method: Ultrasonic·
COMPLIANT OUTLINE: 38510 D-lO

32 PAD CERAMIC LCC

.540
.560

.045
.055

~~
---l.1 _

fl

.442
.458

1

".r=======:::LI ----1::;:;:::!'s

n n n n n n n. II
.074
.088

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic 90% Aluminum
PACKAGE SEAL:
Material: GoldlTin (80/20)
Temperature: 3200 C ±100C
Method: Furnace Braze
NOTE: AU Dimensions are

~~x

.064 -

.076

Tl
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 3(3510 C-12

tMiI-M-3B510 Compliant Materials, Finishes, and Dimensions.

• Dimensions are in inches.

3-138

m

HM-65642C

HARRIS

DESIGN INFORMATION

8K x 8 Asynchronous
CMOS Static RAM

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

TYPICAL ICCDR vs. TA

Vee

-3

=

2.0V

-4

~

-5
-6

-<""

-7

'"

-8

""

0

~

..J

-9
-10
-11
-12

L/
-55

V

-35

V

./

./

~

~

fI'

fI'

>en'"
CJ CJ
::E::E
..,w
::E

I

-15

45

25

TA (OC)

3-139

65

85

105

125

til HARRIS

HM-6564-8
8K X 8, 16K X 4 CMOS RAM

June 1989

Features

Pinout

• Low Power Standby. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 4mW Maximum

TOP VIEW

,.---""1...-

• Low Power Operation ••••••••••••••••••••• .'. 280mW/MHz Maximum
• Data Retention •••••••••••••••••••••••••••••••••••••• 2.0V Minimum
•
•
•
•

TTL Compatible In/Out
Three State Outputs
Fast Access Time •••••••••••••••••••••.••••••••••••• 350ns Maximum
Operating Temperature Range •••••••••••••••••••• -55 0 C to +1250C

• On Chip Address Registers
• Organizable 8K x 8 or 16K x 4
• 40 Pin DIP Pinout - 2.000" x 0.900"

Description
The HM-6564-8 is a 64K bit CMOS RAM. It consists of 16 HM-6504 4K x 1
CMOS RAMs, in lead less carriers, mounted on a ceramic substrate. The HM6564-8 Is configured as an extra wide, standard length 40 pin DIP. The memo
ory appears to the system as an array of 16 4K x 1 static RAMs. The array Is
organized as two 8K by 4 blocks of RAM sharing only the address bus. The
data Inputs, data outputs, chip enables and write enables are separate for
each block of RAM. This allows the user to organize the HM-6564-8 RAM as
either an 8K by 8 or a 16K by 4 array.
This 64K memory provides a unique blend of low power CMOS
semiconductor technology and advanced packaging techniques. The HM6564-8 is Intended for use In any application where a large amount of RAM is
needed, and where power consumption and board space are prime concerns.
The guaranteed low voltage data retention characteristics allow easy imple·
mentation of non-volatile read/write memory by using very small batteries
mounted directly on the memory circuit board. Example applications include
digital avionic instrumentation, remote data acquisition, and portable or hand
held digital communications devices.

• NOTES:
Pins 20 and 40 (VCC) are Internally connected. Similarly pins 1 and 21 (Ground) are connected. The user
Is advised to connect all four VCC pins and Ground

pins to his board busses. This wUl improve power
distribution across the array and will enhance
decoupling.
Pin 10 is internally connected to pin 11, and pin 30 is
connected to pin 31.

Functional Diagram

D4 Q4

DS QS

DO

Q6

D/Q7

CAUTION: These devices are sensitive to alaCb'ostatlc-discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1989

3-140

Specifications HM-6564-8
Absolute Maximum Ratings
Supply Voltage •••••••••••••••••.•••••••••••••••.••••••.•••••••.••••••••••••••••.•••••••••••••.••••••••.•••••••• +7.0V
Input, Output or I/O Voltage Applied ••••••••••••••••••••••.••••••••••••••••••••••••.••••••••• ~ •••. GND -0.3V to VCC +0.3V
Storage Temperature. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • . • • • . • • • • • • • • • • • • • • • • • . • • • • • • • •• -650 C to +1500C
GiIte Count ••••••••••.••••.••••••••••••••••••••••.••.•••••••••••••••.•••.•••••••••••••••••••••••••••••.••••••• 112000
Junction Temperature ••••••••••••••••••••••••••.••.••.•••••••••••••••.•••.•••••••••••••••••.•••••••••••••••••• +1750C
lead Temperature (Soldering, Ten Seconds) ••..•..•••••..•..•..•......•..•••••••••••••••••••••.••••.•••..•••••••• +3000 C
CAUTION: Stresses above those listed in the Absolute Maximum Ratings" may cause permanent damage to the device. This ;s a stress only rating and

operation of the device at these or any other conditions above those indicated in the operational

s~ctions

of this specification ;s not implied.

Operating Conditions
Rise and Fall Time ...................................................................................... 40ns Maximum
Operating Voltage Range ................................................................................ +4.5V to +5.5V
Operating Temperature Range ................................................................ : ....... -55 0 C to +1250 C

D.C. Electrical Specifications vcc

± 10%; TA = HM-6564-8 -55 0 C to +125 0 C

PARAMETER

SYMBOL
ICCSB

= 5V

Standby Supply Current

ICCOPl

Operating Supply Current
(8K x 8) (Note 3)

ICCOP2

Operating Supply Current
(16K x 4) (Notes 2, 3)

MIN

MAX

UNITS

-

800

pA

10=0, V1=VCCorGND

56

mA

E= lMHz,IO= 0, VI = VCCorGND

-

28

mA

E= lMHz,IO=O, VI =VCCorGND
10 = 0, VCC = 2.0, VI = VCC or GND

ICCDR

Data Retention Supply Current

-

400

pA

VCCDR

Data Retention Supply Voltage

2.0

-

V

IIA

TEST CONDITIONS

Address Input Leakage

-20

+20

pA

VI=VCCorGND

1101

Data Input Leakage (8K x 8)

-3

+3

pA

VI=VCCorGND

1102

Data Input Leakage (16K x 4) (Note 2)

-5

+5

pA

VI=VCCorGND

IIEl

Enable Input Leakage (8K x 8)

-10

+10

pA

VI = VCC or GND

IIE2

Enable Input Leakage (16K x 4) (Note 2)

-5

+5

pA

VI=VCCorGND

IIW

Write Enable Input Leakage (Each)

-10

+10

VI=VCCorGND

10Zl

Output Leakage (8K x 8)

-5

+5

"A
pA

IOZ2

Output Leakage (16K x 4) (Note 2)

-10

+10

"A
V

VO=VCCorGND

VIL

Input Low Voltage

0

0.8

VO=VCCorGND

VIH

Input High Voltage

VCC-2.0

VCC

V

VOL

Output Low Voltage

-

0.4

V

10 = 2.0mA

VOHl

Output High Voltage

2.4

V

10=-1.0mA

VOH2

Output High Voltage (Note 2)

CIA

VCC-O.4

Address Input Capacitance (Note 2)

-

V

10 =-100pA

-

200

pF

f= lMHz, VI =VCCorGND

50

pF

f= 1 MHz, VI =VCC orGND

100

pF

f= lMHz, VI =VCC orGND

160

pF

f= lMHz, VI =VCCorGND

-

80

pF

f = 1 MHz, VI = VCC or GND

Write Enable Input CapaCitance
(Each) (Note 2)

-

100

pF

f= lMHz, VI =VCCorGND

COl

Output Capacitance (8K x 8) (Note 2)

pF

f = 1 MHz, VO = VCC or GND

Output Capacitance (16K x 4) (Note 2)

-

50

CO2

100

pF

f= 1 MHz, VO =VCCorGND

CIDl

Data Input Capacitance (8K x 8) (Note 2)

CID2

Data Input Capacitance (16K x 4) (Note 2)

CIEl

Enable Input Capacitance
(8K x 8) (Note 2)

CIE2

Enable Input Capacitance
(16K x 4)(Note 2)

CIW

NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns max; Input and output timing reference level: 1.5V; Output load: 1TTL gate
equivalent and CL = 50pF (Min) for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. ICCOP is proportional to operating frequency.
4.

vee = 4.5V and

5.5V

3-141

Specifications HM-656,4-:-B
A.C. Electrical Specifications (Note 1) VCC = 5V ± 10%, TA = -SsoC to +12SoC
SYMBOL

PARAMETER

MIN

MAX

UNITS

TEST CONDITIONS

350

ns

(Notes 1, 4)

400 .

ns

(Notes 1.' 4)

(1)TELQV

Chip Enable Access

(2)TAVQV

Address Access ffAVQV = TELQV + TAVEL)

-

(3)TELQX

Output Enable

S

-

ns

(Notes 2,4)

-

120

ns

. (Notes 2, 4)

ns

(Notes 1, 4)

ns

(Notes 1,4)

(4)TEHQZ

Output Disable

(S)TELEL

Read or Write Cycle

480

(6)TELEH

Chip Enable Low

3S0

-

(7)TEHEL

Chip Enable High'

130

-

ns

(Notes 1,4)

(8)TAVEL

Address Setup

SO

-

(9)TELAX

Address Hold

SO

Write Enable Low

150

. (10)TWLWH

ns

(Notes 1,4)

-

ns

(Notes 1,4)

ns

(Notes 1,4)

ns

(Notes 1, 4)

ns

(Notes 1,4) .

ns

(Notes 1,4)

ns

(Notes 1, 4)

ns

(Notes 1,4)

ns

(Notes 1, 4)

ns

(Notes 1, 4)

(12)TWLEL

Early Write Setup (Write Mode)

10

(13)TELWH

Early Write Hold (Write Mode)

100

-

(14)TDVWL

Data Setup

10

-

(11)TWLEH

Write Enable Setup

2S0

(1S)TDVEL

Early Write Data Setup

10

(16)TWLDX

Data Hold

100

-

(17)TELDX

Early Write Data Hold

100

-

.

NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise. and fall times: 5ns max; Input and output timing re~erence level: 1.5V; Outp!Jt,load: 1TTl gate equivalent
and CL = 50pF (Min) for CL greater than 50pF, access lime is derated by 0.15no per pF.
2. Tested at initial design and after major design changes.
3. ICCOP is proportional to frequency.
4. VCC

= 4.5V and 5.5V

Low Voltage Data Retention
HARRIS CMOS RAMs are designed with battery backup in mind; Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention:
1. Chip Enable (E) must be held high during data retention; within VCC +O.3V to VCC.
2. On RAMs which have selects or output enables (e.g. S, G), one of the selects or output enables should be held in the
deselected state to keep the RAM outputs high impedance. minimizing power dissipation.
3. All other inputs should be held either high (at CMOS VCC) or at ground to minimize ICCDR.
4. Inputs which are held high (e.g. E) must be kept between VCC +O.3V and 70% of VCC during the power up and power
down transitions..
5. The RAM can begin operation one TEHEL after VCC reaches the minimum operating voltage (4.5 volts).
DATA RETENTION TIMING

- - - -........1-0...-----,.- DATA RETENTION MODE - - - - - I " . . . - - - - - VCC~2.0V

vcc to VCC +O.3V

3-142

HM-6564-8
Read Cycle

A~~~~~
TElEH

TELELI51

161

141 TEHOZ
VALID DATA OUTPUT

Vi

HIGH

REF~~:NCE ----Itf--+----+--------+--------lt--+t--I-J

-1

4

TRUTH TABLE
TIME
REFERENCE

E

INPUTS

Vi

A

Q

-1

H

X

X

0

"""'\...

1

L
L

-F

H
H
H
H

H

X

X
X
X
X

Z
Z
X

"""'\...

H

V

2
3
4
5

OUTPUT

V

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same !IS -1)
Cycle Ends, Next Cycle Begins (Same as 0)

V
V
Z
Z

The address information is latched in the on chip registers
on the falling edge of E (T = 0). Minimum address set up
and hold time requirements must be met. After the required
hold time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes

enabled but data is not valid until during time (T = 2). VIi
must remain high until after time (T = 2). After the output
data has been read, E may return high (T = 3). This will
disable the output buffer and ready the RAM for the next
memory cycle (T = 4).

Early Write
Cycle

HIGH-Z

HIGH-l

TIME
REFERENCE

tt

.,

2

3

TRUTH TABLE
TIME
REFERENCE

-

E

Vi

-1

H
~
L

X

0
1

2
3
4

INPUTS
A

0

OUTPUT
Q

X

X

Z
Z
Z
Z
Z
Z

L

V

V

....r
H.

X
X
X

X
X
X

X
X
X

"""'\....

L

V

V

The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of E
(T = 0), the addresses, the write signal, and the data input
are latched in on chip registers. The logic value of VIi at the
time E falls determines the state of the output !Juffer for the
cycle. Since VIi is low when E falls, the output buffet .is

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Write in Progress Internally
Write Complete
Prepare for Next Cycle ISame as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

latched into the high impedance state and will remain in that
state until E returns high (T = 2). For this cycle, the data input is latched by E going low; therefore data set up and hold
times should be referenced to E. When E (T = 2) returns to
the high state the output buffer disables and all signals are
unlatched. The device is now ready for the next cycle.

3-143

>we:

00

::::
c.>W
::

HM-6564-8
Late Write
Cycle

TIME
REFERENCE

----+---j-----I---,-------+---+--I--+----

.,

TRUTH .TABLE
TIME
REFERENCE
-1
0
1

2
3

E
H

\...L
L

4

.-r
H

5

\...-

INPUTS
A
Vi

D

X
H

X
X

X
V

\...H
H
X
H

X
X
X
X

X
X
·X

V

X

OUTPUT
Q
Z
Z
X
X
X
Z
·Z

V

The late write cycle is a cross between the early write cycle
and the read-modify-write cycle.' Recall that in the early
write the output is guaranteed to remain high impedance,
and in the read-modify-write the output is guaranteed valid
at access time. The late write is between these two cases.

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Write Begins, Data is Latched
Write in Progress Internally
Write Completed'
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)

With this cycle the output.may become active, and may become valid data, or may remain active but undefined. Valid
data is written into the RAM if data set up, data hold, write
setup and write pulse widths are observed.

NOTES: In the above descriptions the numbers in parenthesis (T = n) refers to the respective timing diagrams. The numbers are located on the time reference

line below each diagram. The timing diagrams shown

~re

only examples and are not the only valid method of operation.

HM-6504 (One of Sixteen)
LSB AS
A7
A6

A
6
GATED
ROW
DECODER

AD
AI

A2

A
6

64x64
64

MATRIX

G

Q

E o---t-ct

>-++-__ ____.:....J

ALL UNEs ACTIVE HIGH - POSITIVE LOGIC
THREE - STATE BUFFERS:
A HIGH __ OUTPUT ACTIVE
CONTROL AND DATA LATCHES:
LLOW __ Q=D
Q LATCHES ON RISING EDGE OF L
. ADDRESS LATCHES:
LATCH ON RISING EDGE OF E
GATED DECODERS:
GATE ON RISING EDGE.OF G

~

LSBAII A5A4J\3A9AIO

3-144

HM-6564-8
Organization Guide
mode, use the chip enables as if there were only two, E1
and E2. In the 16K x 4 mode, all chip enables must be
treated separately. Transitions between chip enables must
be treated with the same timing constraints that apply to any
one chip enable. All chip enables must be high at least one
chip enable high time (TEHEL) before any chip enable can
fall. More than one chip enable low simultaneously, for
devices whose outputs are tied common either internally or
externally, is an illegal input condition and must be avoid.

To Organize 8K x 8:
Connect:

E1 with E3
E2with E4
W1 withW2

(Pins9+32)
(Pins 12 + 29)
(Pins 11 + 31)

To Organize 16K x 4:
Connect:

Optional

00 with 04
(Pins 2 + 39)
DO with D4
(Pins 3 + 38)
01 with 05
(Pins 4 + 37)
D1 with D5
(Pins 5 + 36)
D2 with D6
(Pins 16 + 25)
02 with 06
(Pins 17 + 24)
D3 with D7
(Pins 18 + 23)
03 with 07
(Pins 19 + 22)
W1 may be common with W2 (Pins 11 + 31)

Printed Circuit Board Mounting:

Concerns for Proper Operation of Chip Enables:
The transition between blocks of RAM requires a change in
the chip enable being used. When operating in the 8K x 8

The leadless chip carrier packages used in the HM-6564
have conductive lids. These lids are electrically floating, not
connected to VCC or GND. The designer should be aware
of the possiblity that the carriers on the bottom side could
short conductors below if pressed completely down against
the surface of the circuit board. The pins on the package are
designed with a standoff feature to help prevent the
lead less carriers from touching the circuit board' surface.

Board Size Tradeoffs
Printed circuit board real' estate is' a costly commodity.
Actual board costs depend on layout tolerances, density,
complexity, number of layers, choice of board material, and
other factors.

The following table compares board space for 16 standard'
DIP 4K RAMs to the HM-6564 RAM array. Both fine line,
close tolerance layout and standard "easy" layout board
sizes are shown in the comparison.

>-

enD:

CICI

64K ARRAY OR 16 4K RAMs ON A PC BOARD VS. THE HM-6564
PACKAGE

CIRCUIT SUBSTRATE

SIZE

18PinDIP

Standard Two Sided PCB

12 to 15 square inches

18 Pin DIP

Fine line or Multilayer PCB

9 to 11 square inches

18Pin
Leadless Carrier

Multilayer Alumina Substrate

3 to 5 square Inches

HM-6564

Two Sided Mounting Multilayer
Alumina Substrate

2 square inches

The cost of semiconductor circuits decline with time. If actual costs were included, they would be out of date in a very
short time. We urge you to contact your local Harris office of
sales representative for accurate pricing allowing cost
tradeoff analysis. In your cost analysis, also consider the

advantages of a lighter,>smaller overall package for your
system. Consider how much more valuable your system will
be when the memory array size is decreased to about 1/6 of
normal size.

3-145

:;::;:
c.>W
:;:

mHARRIS

HM-8808-8
HM-8808A-8
8K x 8 Asynchronous
: CMOS Static RAM Module

June 1989

Features

Pinouts
TOP VIEW

• Full, CMOS Design
• 6 Transistor Memory Cell
• Low Standby Current •••••••••••••• , •••••.•••••••••••••• 250/900flA
• Low Operating Current ••••••• , ••••••••• ': ••••••••••••••••••• 70mA
• , Fast Address Access Time ••••• '•••••••••••••••••••••
100/120/150ns
,
• CMOS/TTL Compatible Inputs/Outputs
• JEDEC Approved Pinout
• Equal Cycle and Access Time
• No Clocks or Strobes Required
• Single 5 Volt Supply
• Gated Inputs - No Pull-Up or Pull-Down Resistors Required
• Temperature Range •••••••••••••••••••••••••••••• -550C to +125 0 C
• Easy Microprocessor Interfacing
• Dual Chip Enable Contr,ol (HM-8808A)

Description
The HM-8808-8 and HM-8808A-8 are 8K x 8 Asynchronous CMOS Static
RAM Modules, based on multi-layered, co-fired, dual-in-line substrates.
Mounted on each substrate are four HM-65162 2K x 8 CMOS SRAMs, a high
speed CMOS decoder, and a ceramic decoupling capacitor, all packaged in
leadless chip carriers. The capacitor is added to reduce noise and the need
for external decoupling. The HM-65162 RAMs used in these modules are full
CMOS devices, utilizing arrays of six transistor (6T) memory cells for the most
stable and lowest possible standby supply current over the full military tem"
perature range. In addition to this, the high stability of the 6T cell providEis
excellent protection against soft errors due to noise and alpha particles. This
stability also improves the radiation tolerance of the RAM over that of four
transistor devices. The HM-8808-8 and HM-8808A-8 have gated inputs to
simplify system design for optimum standby supply current. The pinouts of
these modules conform to the JEDEC 28 pin 8 bit wide standard, which is
compatible ,with a variety of industry standard memories. The HM-8808A-8
is pin-compatible with many standard 8K x 8 RAMs, adding the advantage
of high performance over the full military temperature range. Also, because
of the second chip enable (E2), the HM-8808A-8 Simplifies the design of
low-power battery back-up memory systems.

Functional Diagram

PIN DESCRIPTION

AO-Al0------~----------------__,

DOO-D07 ____~~----------------~

Vi

TOP VIEW

---1'+t_-------,

G--~+t_------,

PIN

DESCRIPTION

A
DQ

Address Input
Data Input/Output
Chip Enable (HM-SS08-S)
Chip Enable (HM-SS08A-S)
Chip Enable (HM-SS08A-S)
Write Enable
Output Enable

E
Ei
E2

Iii

G

SELECTION GUIDE
PART NUMBER
HM-S80SS-S/HM-SSOSA5-S
HM-S80SB-S/HM-880SAB-S
HM-S80S-S/HM-SSOSA-S
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
Copyright @ Harris Corporation 1989

3-146

TELQV

ICCSB

lOOns
120ns
150ns

25011A
25011A
90011A

Specifications HM-8808S-8

HM-8808AS-8

Absolute Maximum Ratings
Supply Voltage. • • • • • . • • . • . . • . • . . . • . • . . • • • • . . . . • . • • . • • • • • . • • . . . . . . . • . . • . . • • . • . . • . . . . . . . . . . . . • . • . • • . . . . . . . . • . . . . .. 7.0V
Input or Output Voltage Applied •........•.••.•........••••.••..•••..•.....•..••.•.•..•........•. GND -0.3V to vcc +0.3V
Storage Temperature Range ••.••.•••••......•••.••...•••..•..••.•.••.••..•.....•••.•.•.•••......••.•• -650 C to +1500 C
Gate Count ..•.•.•••..••....•.••.•..•..•.••..••..•.••.•••.•.....••..••••.•.••........•••••.•.•....•..•••...•.. 105000
Junction Temperature .....•..•..•.........•..•.•........•.....••...•...•.......•..•••.•.•.......••.•.•••...... +1750 C
Lead Temperature (Soldering, Ten seconds) .....•...•............•.•..............•..•••.•.........••.•.•••...... +300oC
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Input Rise and Fall Time .•.•...............•..•................••.....•......•.••.•.••••.•...••..••.•••••..••. 40ns Max
Operating Supply Voltage .•..•••..•....•....••••..•••.•.•.....•.•.••.••..•.••.••••.••••.••••.••....•••.•.•• 4.SVto 5.SV
Operating Temperature .•.••...•••.•.•..••.•.•.•.••••.••.•.••..•.•.••.••..•.••.••••..•••.••.•.••..•.•• -55 0 C to +1250 C

D.C. Electrical Specifications vcc = 5V ± 10%; TA = -550 C to +1250 C
SYMBOL

MIN

MAX

UNITS

Standby Supply Current (CMOS)

-

250

~A

10 = 0, E = VCC-0.3V (Note 7),
E2 = 0.3V (Note 8)

ICCSB

Standby Supply Current (TTL)

-

35

rnA

10 = 0, E = VIH (Note 7),
E2 = VIL (Note 8)

ICCEN

Enabled Supply Current

-

60

rnA

10 = 0, E = VIL (Note 7),
E2 =VIH (Note 8)

ICCOP

Operating Supply Current

-

70

mA

10 = 0, f = 1 MHz, E = VIL (Note 7),
E2 =VIH (Notes 8, 2)

ICCDR

Data Retention Supply Current

-

125

~A

VCC = 2.0V, E = VCC-0.3V (Note 7),
E2 = 0.3V (Note 8)

ICCSBl

PARAMETER

TEST CONDITIONS

Input Leakage Current

-1.0

+1.0

~A

VI = GND orVCC

IIOZ

InpuVOutput Leakage Current

-1.0

+1.0

~

VIO

VCCDR

Data Retention Supply Voltage

2.0

-

V

VCC = 2.0V, E = VCC (Note 7),
E2 = GND (Note 8)

II

= GND or VCC

VOL

Output Low Voltage

-

0.4

V

10=4.0mA

VOHl

Output High Voltage

2.4

V

10=-1.0mA

VOH2

Output High Voltage

VCC-O.4

-

V

10 = -100~A (Note 3)

VIL

Input Low Voltage

0

0.8

V

VIH

Input High Voltage

2.4

VCC

V

Capacitance (Note 3)
SYMBOL

MIN

MAX

UNITS

TEST CONDITIONS

CE

Enable Input Capacitance

-

15

pF

VE = VCC orGND, f = 1 MHz (Note 3)

CW

Write Enable Capacitance

-

CI
CIO
NOTES: 1.
2.
3.
4.

PARAMETER

Input Capacitance: G, A
InpuVOutput Capacitance

-

48

pF

vw = VCC or GND, f =

35

pF

VI = VCC or GND, f = 1 MHz (Note 3)

43

pF

VIO

All devices tested at worst case temperature and supply voltage limits.
Typical derating = 5mNMHz Increase in leeOp, VI ~ vee or GND.
Guaranteed but not tested.
Input pulse levels: VIL = O.OV, VIH ~ 3.0V
Input rise and 'all limes: 5ns (max.) vee = 4.5V and 5.5V.
Input and output timing reference levels: 1.SV
Output load: 1 TTL gate equivalent and SOpF (min. including scope and iig).

3-147

1 MHz (Note 3)

=VCC or GND, f = 1 MHz (Note 3)

5. "EL" (enable input valid) equivalent to:
EL on the HM-SSOS-S. ElL and E2H on the HM-S80SA-S.
6. "EH" (enable input invalid) equivalent to:
EH on the HM-SSOS-S. EIH or E2L on the HM-SSOSA-S.

7. Relevant to the HM-SSOS-S only.
S. Relavantto the HM-8S0SA-8 only.

Specifications HM-8808S-8

HM-8808AS-8

A.C. Electrical Specifications vcc = 5V ± 10%; TA = -550 C to +1250 C
NO.

SYMBOL

PARAMETER

MIN

MAX

UNITS

ns

TEST CONDITIONS

READ CYCLE
(1)

TAVAX

Read Cycle Time

100

-

(2)

TAVOV

Address Access Time

-

100

ns

(3)

TELOV

Chip Enable Access Time

-

100

ns

(4)

TGLOV

Output Enable Access Time

-

50

ns

(5)

TELOX

Chip Enable Output Enable Time

TGLOX

Output Enable Output Enable Time

(NoteS)

(7)

TAXOX

Address Output Hold Time

5

-

(8)

TEHOZ

Chip Disable Output Disable Time

0

60

ns

(Notes 3,6)

(9)

TGHOZ

Output Disable Time

0

40

ns

(Note 3)

(6)

20
5

ns

(Notes 3,5)

ns

(Note 3)

ns

WRITE CYCLE
(10)

TAVAX

Write Cycle Time

100

(11)

TELWH

Chip Enable to End of Write

70

(12)

TWLWH

Write Enable Pulse Width

40

-

ns
ns

-

ns

-

' ns

(Note 5)

(13)

TELEH

En,able Pulse Width (Early Write)

40

(14)

TAVWL

Address Setup Time (Late Write)

15

(15)

TAVEL

Address Setup Time (Early Write)

(16)

TWHAX

Address Hold Time (Late Write)

(17)

TEHAX

Address Hold Time (Early Write)

30

(18)

TDVWH

Data Setup Time (Late Write)

30

(19)

TDVEH

Data Setup Time (Early Write)

, 30

(20)

TWHDX

Data Hold Time (Late Write)

10

-

ns

(21)

TEHDX'

Data Hold Time (Early Write)

30

-

ns

(Notes3,6)

(22)

TWLEH

Write Enable Pulse Setup Time

40

-

ns

(Note 6)

(23)

TWLOZ

Write Enable Output Disable Time

-

40

ns

(Note 3)

(24)

TWHOX

Write Disable Output Enable Time

0

-

ns

(Note 3)

0
,10

NOTES: 1. All devices tested at worst case temperature and supply vollage limits.
2. Typical derating

= 5mA/MHz increase In leeOp, VI = vee or GND.

3. Guaranteed but not tested.
4. Input pulse levels: VIL = O.OV, VIH = 3.0V
Input rise and fall times: 5ns (max.) vee = 4.5V and 5.5V.
Input and output timing reference levels: 1.5V
, Output load: ., nL gale equivalent and 50pF (min, including scope and Jig).
5. "EL" (enable input valid) equivalent to:
EL on Ihe HM-SSOS-S. ElL and E2H on Ihe HM-SSOSA-S .
. 6. "EH" ·(enable input invalid) equivalent to:
EH on Ihe HM-SSOS-S. EIH or E2L on Ihe HM-SSOSA-S.
7. Relevant to the HM-6808-B only.

, S. Releva.nl.lo Ihe HM-SS08A-S only.

3-148

ns

(Notes 3, 5, 6)

ns
ns

ns

(Notes 3,5)

(Note 3)

ns
ns

(Note 6)

Specifications HM-8808B-8

HM-8808AB-8

Absolute Maximum Ratings
Supply Voltage ••••••••••••••.•.•••.••••.••••..••..••••••••••••••••••••••••••••••••••••••••••••••••••.••••••••••• 7.0V
Input or Output Voltage Applied ••.•••••••.....••.•.••••••.••••••••••••.••••••••.••.•.••••••••••• GND -0.3V to vcc +0.3V
Storage Temperature Range ••••••••••••••••.••.••.•••••••.••••.•••••••••••••••••••••.•••••..••...•.•• -65 0C to +1500 C
Gate Count. " ••••••••••.•.••••••••••••••••••.••.••••••••••••.••.••••••••••••.••••••••••••.•••.••••••••••••••. 105000
Junction Tern perature .• • • • • . • . • • • • • • • • • • • • • • • • . • • . • • • • • • • • • • • • . • • . • • • • . • • • • • • • • . • • • • • . • • • • • • • • • . • • • • • • • • • • • • •• + 1750 C
Lead Temperature (Soldering, Ten seconds) ••••••••••••.••..•••••.••.•••••••••••••.•••••••••••.....•••••••••.•••• +3000 C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only rating and

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Input Rise and Fall Time •.••••••...•.•••••••.•••••...••••••••.•..••.•••••.••••.••••.•••.•...•••••.••••••••.••• 40ns Max
Operating Supply Voltage .•••••••......•••••.••.•••..•••••••.••...•••••••.....•..•.••••.•.....•••••••..•.•. 4.SV to 5.5V
Operating Temperature ••.••••.•••••.•••••••••.••.•••.•••••••.••••••••••••.•••••••.•••.•••••••••••••.. -550 C to +1250 C

D.C. Electrical Specifications vcc
SYMBOL

= 5V

PARAMETER

±

10%; TA = -550 C to +1250 C
MIN

MAX

UNITS

ICCSB1

Standby Supply Current (CMOS)

-

250

~A

10 = 0,E = VCC-O.3V (Note 7),
E2 = 0.3V (Note B)

ICCSB

Standby Supply Current (TTL)

-

35

rnA

10 = 0, E = VIH (Note 7),
E2 = VIL (Note B)

ICCEN

Enabled Supply Current

-

60

rnA

10 = 0, E = VIL (Note 7),
E2 =VIH (Note B)

ICCOP

Operating Supply Current

-

70

rnA

10 = 0, f = 1 MHz, E = VIL (Note 7),
E2 = VIH (Notes 8, 2)

ICCDR

Data Retention Supply Current

-

125

~

VCC = 2.0V, E = VCC-0.3V (Note 7),
E2 = O.3V (Note B)

TEST CONDITIONS

Input Leakage Current

-1.0

+1.0

~

VI = GND orVCC

II0Z

InpuVOutput Leakage Current

-1.0

+1.0

~A

VIO=GNDorVCC

VCCDR

Data Retention Supply Voltage

2.0

-

V

VCC = 2.0V, E = VCC (Note 7),
E2 = GND (Note B)

0.4

V

10 = 4.0mA

-

V

10=-1.0mA

V

10=-100~(Note3)

II

VOL

Output Low Voltage

-

VOHl

Output High Voltage

2.4

VOH2

Output High Voltage

VCC-O.4

VIL

Input Low Voltage

0

O.B

V

VIH

Input High Voltage

2.4

VCC

V

MIN

MAX

UNITS

TEST CONDITIONS

Capacitance
SYMBOL

(Note 3)
PARAMETER

CE

Enable Input Capacitance

CW

Write Enable Capacitance

CI
CIO
NOTES: 1.
2.
3.
4.

Input Capacitance: G, A
InpuVOutput Capacitance

-

15

pF

VE = VCC or GND, f = 1 MHz (Note 3)

4B

pF

VW = VCC or GND, f = 1 MHz (Note 3)

35

pF

VI = VCC or GND, f = 1 MHz (Note 3)

43

pF

VIO = VCC or GND, f = 1 MHz (Note 3)

All devices tested at worst case temperature and supply voltage limils.
Typical derating = SmA/MHz increase in recop, VI = vee or GND.
Guaranteed but not tested.
Input pulse levelo: VIL = O.OV, VIH = 3.0V
Input rise and fall times: Sno (max.) vee = 4.SV and S.SV.
Input and output timing reference levels: 1.SV
Output load: 1 TTL gate equivalent and SOpF (min, including scope and jig).

3-149

5. "El" (enable input valid) equivalent to:
EL on the HM-8808-8. ElL and E2H on the HM-8808A-8.
6. "EH" (enable input Invalid) equivalent to:
EH on the HM-8808-8. EIH or E2L on the HM-8808A-8.
7. Relevant to the HM-8808-8 only.
8. Relevant to the HM-8808A-8 only.

Specifications HM-8808B-8

HM-8808AB-8

A.C. Electrical Specifications vcc = sv ± 10%; TA = -SsoO to +12S0 0
NO.

PARAMETER

SYMBOL

MIN

MAX

UNITS

TEST CONDITIONS

READ CYCLE
(1)

TAVAX

Read Cycle lime

(2)

TAVQV

Address Access Time

(3)

TELQV

Chip Enable Access Time

(4)

TGLQV

Output Enable Access Time

120

-

-

ns

120

ns

120

ns

65

ns

(NoteS)

(5)

TELQX

Chip Enable Output Enable Time

20

-

ns

(Notes3,5)

(6)

TGLQX

Output Enable Output Enable Time

5

ns

(Note 3)

(7)

TAXQX

Address Output Hold lime

S

-

(8)

TEHQZ

Chip Disable Output Disable Time

0

70

ns

(Notes 3,6)

TGHQZ

Output Disable Time

0

40

ns

(Note 3)

(9)

ns

WRITE CYCLE
(10)

TAVAX

Write Cycle Time

120

-

ns

(11)

TELWH

Chip Enable to End of Write

80

ns

(12)

TWLWH

Write Enable Pulse Width

55

-

ns

(Note 5)

ns

(19)

TDVEH

Data Setup Time (Early Write)

30

(20)

TWHDX

Data Hold Time (Late Write)

15

(21)

TEHDX

Data Hold Time (Early Write)

30

(22)

TWLEH

Write Enable Pulse Setup lime

55

-

ns

(Note 6)

(23)

TWLOZ

Write Enable Output Disable Time

-

40

ns

(Note 3)

(24)

TWHOX

Write Disable Output Enable lime

0

-

ns

(Note 3)

(13)

TELEH

Enable Pulse Width (Early Write)

60

(14)

TAVWL

Address Setup lime (Late Write)

15

(15)

TAVEL

Address Setup Time (Early Write)

0

(16)

TWHAX

Address Hold Time (Late Write)

10

(17)

TEHAX

Address Hold Time (Early Write)

30

(18)

TDVWH

Date Setup Time (Late Write)

30

NOTES: 1. All devices tested at worst case temperature and supply voltage limits.
2. Typical derating = SmA/MHz Increase in ICCOP. VI - VCC or GND.
3. Guaranteed bul not tested.
4. Input pulse levels: VlL - O.OV. VIH - 3.0V
Input rise and fall times: 5ns (max.) vee - 4.SV and 5.5V.
Input and output timing reference levels: 1.5V
Oulput load: 1 TIL gate equivalent and SOpF (min. Including scope and jig).

5. IIEl" (enable input vaJid) equivalent to:
EL on the HM-BBOB-B. ElL and E2H on the HM-BBOBA-B.
6. "EH" (enable Inpullnvalldl equivalenl \0:
EH on Ihe HM-BBOB-B. EIH or E2L on the HM-BB08A-B.
7. Retevant to the HM-8808-8 onty.
8. Relevanllo the HM-8BOBA-8 only.

3-150

(Notes 3, 5, 6)

ns
ns

(Notes 3,5)

ns
ns

(Note 3)

ns
ns

(Note 6)

ns
ns

(Notes3,6)

Specifications HM-8808-8

HM-8808A-8

Absolute Maximum Ratings
Supply Voltage •••••••••••••••••.•••••.••••.•••.••••...•••••••.••.••••••••••••••••••.••••••••••••••••••••.•.••••. 7.0V
Input or OutputVollage Applied ••••••••.••••••.•••••••••••.••••••••••..•••.•.••.•••.••••.••.•••. GND -0.3V to VCC +0.3V
Storage Temperature Range ..•.•.••.••.•••••••••••••.•••••••••.••.•••••••••••••..•••..•••••..••••••.• -BSoC to +1S00 C
Gate Count ••••• , .••..••••.• , ••. " •••.••••••••••.••.•••••••••.••.•••..••••••••• , •••.•••••••.. '" •...••••..•••• 10S000
Junction Temperature •••••••••••.•••••.••••••.••.•••.••••.••••..••••.••••••.•••••• " •••.•..••••••••••..••••••• +17So C
Lead Temperature (Soldering, Ten seconds) •••.•••••••...••.•••••..•.••...••.••••••.••......•••...••.....••....•• +3000C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and

operation of the device at these or any other conditions above those indicated in the operational sections of this speciUcation is not implied.

Operating Conditions
Input Rise and Fall Time ..•.••.•••••....•••••.•••••..•••...••••..••••..•••...•.••.•.•••..••.•..•.•....••••..•• 40ns Max
Operating SupplyVollage .•••...•••••.•..••..••••.•...•..••.••..•.•....••....•.....•.....•......••......•.. 4.SV 10 S.SV
Operating Temperature ................................................................................ -SSoc to +12So C

D.C. Electrical Specifications
SYMBOL

vcc = sv ± 10%; TA = -SSoc to +12So C

PARAMETER

MIN

MAX

UNITS

TEST CONDITIONS

=0, E =VCC-0.3V (Note 7),
=0.3V (Note 8)
10 =0, E =VIH (Note 7),

ICCSB1

Standby Supply Current (CMOS)

-

900

fJJ\

ICCSB

Standby Supply Current (TTL)

-

3S

mA

ICCEN

Enabled Supply Current

-

70

mA

10 0, E VIL (Note 7),
E2 =VIH (Note 8)

ICCOP

Operating Supply Current

-

70

mA

10
E2

E2 = VIL (Note 8)

=

=

-

400

J.IA

=O. f =1 MHz, E =VlL (Note 7),
=VIH (Notes 8, ?)
VCC =2.0V, E =VCC-0.3V (Note 7),

Input Leakage Current

-S.O

+S.O

fJJ\

VI

IIOZ

InpuVOutput Leakage Current

-S.O

+S.O

fJJ\

VIO

VCCDR

Data Retention Supply Voltage

2.0

-

V

ICCDR

Data Retention Supply Current

10
E2

E2 = O.3V (Note 8)

VOL

Output Low Vollage

-

0.4

V

= GND orVCC
=GNDorVCC
VCC =2.0V, E =VCC (Note 7),
E2 =GND (Note 8)
10 =4.0mA

VOH1

Output High Vollage

2.4

-

V

10=-1'.OmA·

VOH2

Oulput High Vollage

VCC-0.4

10

II

-

V

VIL

Input Low Vollage

0

0.8

V

VIH

Input High Voltage

2.4

VCC

V

MIN

MAX

UNITS

TEST CONDITIONS

1S

pF

=VCC or GND, f =1 MHz (Note 3)
VW =VCC or GND, f = 1 MHz (Note 3)
VI =VCC or GND, f = 1 MHz (Note 3)
VIO =VCC or GND, f = 1 MHz (Note 3)

Capacitance
SYMBOL

(Note 3)
PARAMETER

CE

Enable Input Capacilance

CW

Write Enable Capacitance

CI
CIO
NOTES: 1.
2.
3.
4.

=-1 OOJ.lA (Note 3)

Input Capacitance: G, A
InpuVOutput Capacitance

-

48

pF

35

pF

43

pF

All devlcBs tested at worst case temperature and supply voltage limits.
Typical derating = SmA/MHz increaSB in recop, VI = vee or GND.
Guaranteed but not tesled.
Input pul.e level.: VIL = O.OV, VIH = 3.0V
Input rise and fall times: 5ns (max.) vee = 4.5V and 5.5V.
Input and output timing reference levels: 1.5V
Output load: 1 TTL gate equivalent and 50pF (min, including scope and jig).

3-151

VE

5. "EL" (enable input valid) equivalent to:
EL on the HM-BBOB-B. ElL and E2H on the HM-BBOBA-B.
6. "EH" (enable input invalid) equivalent to:
EH on the HM-BBOB-B. EIH or E2L on the HM-8B08A-8.

7. Relevant to the HM-B808-8 only.
B. Relevant to the HM-8808A-B only.

>",D:
CC

:s:s
.......:s

Specifications HM-8808-8, HM-8808A-8
A.C. Electrical Specifications vcc
NO.

SYMBOL

= 5V :I: 10%; TA = -550C to +1250C

PARAMETER

MIN

MAX

UNITS

TEST CONDITIONS

READ CYCLE

-

ns

150

ns

Chip Enable Access Time

-

150

ns

TGLQV

Output Enable Access Time

-

65

ns

(5)

TELQX

Chip Enable Output Enable Time

25

(Notes3,5)

TGLQX

Output Enable Output Enable Time

5

ns

(Note 3)

(7)

TAXQX

Address Output Hold Time

5

-

ns

(6)

(8)

TEHQZ

Chip Disable Output Disable Time

0

80

ns

(Notes 3,6)

(9)

TGHQZ

Output Disable Time

0

50

ns

(Note 3)

-

ns

(1)

TAVAX

Read Cycle Time

(2)

TAVQV

Address Access Time

(3)

TELQV

(4)

150

(Note 5)

ns

WRITE CYCLE
(10)

TAVAX

Write Cycle Time

150

(11)

TELWH

Chip Enable to End of Write

90

(12)

TWLWH

Write Enable Pulse Width

65

ns

(13)

TELEH

Enable Pulse Width (Early Write)

65

-

(14)

TAVWL

Address Setup Time (Late Write)

20

-

ns

-

ns

-

ns

Address Setup Time (Ea~y Write)

(15)

TAVEL

(16)

TWHAX

Address Hold Time (Late Write)

(17)

TEHAX

Address Hold Time (Early Write)

45

(18)

TDVWH

Data Setup Time (Late Write)

35

5
20

-

(19)

TDVEH

Data Setup Time (Ea~y Write)

35

(20)

TWHDX

Data Hold Time (Late Write)

20

(21)

TEHDX

Data Hold Time (Early Write)

45

(22)

TWLEH

Write Enable Pulse Setup Time

65

(23)

TWLQZ

Write Enable Output Disable Time

-

(24)

TWHQX

Write Disable Output Enable Time

0

-

NOTES:. 1. All devices tested at worst case temperature and supply voltage limits.
2. Typical deraling = SmA/MHz increase in leeOp, VI = vee or GND.
3. Guaranteed but not tested.
4. Input pulse levels: VIL = O.OV, VIH = 3.0V
Input rise and fall times: 5ns (max.) vee - 4.5V and 5.5V.
Input and output timing reference levels: 1.5V
Output load: 1 TTL gate equivalent and 50pF (min, including scope and jig).

5. "EL" (enable input valid) equivalent to:
EL on the HM-BBOB-B. ElL and E2H on the HM-BBOBA-B.
6. "EH" (enable input invalid) equivalent to:
EH on the HM-BBOB-B. EIH or E2L on the HM-BBOBA-B.
7. Relevant to the HM-8808-8 only.
B. Relevant to the HM-BBOBA-B,only.

3-152

-

(Note 5)

ns
ns

(Notes 3, 5, 6)

(Notes 3,5)

ns
(Note 3)

ns
ns

(Note 6)

ns
ns

(Notes 3,6)

-

ns

(Note 6)

50

ns

(Note 3)

ns

(Note 3)

HM-8808-8

HM-8808A-8

Truth Table

HM-S80S

HM-880SA

HM-SSOS/8S0SA

E

El

E2

W

Standby (CMOS)

VCC

X

GND

X

X

Standby (TTL)

VtH

VtH

VIL

X

X

Enabled (High Z)

VIL

VIL

VIH

VIH

VIH

Write

VIL

VIL

VtH

VIL

X

VIL

VIH

VIH

VIL

MODE

Read

VIL

G

HM-8808 Timing Diagram
READ CYCLE 1

(Notes 1,2)

TAVAX
III

A

X

ADDRESS 1
TAVQV

ADDRESS 2

I

171

DATA 1

X :XkJ:

NVVV'V\

(Note 1)

TAVAX
III

TAVQV
121

TELQV
TElQX

141

10(

TAXOX

I

121

Q

READ CYCLE 2

~

131
151

TGlQV
TGlQX
161

Q

NOTES: 1. In a read cycle, Vi is held high.
2. In read cycle 1, the module is kepi continuously enabled. G, and E are held at VIL.

3-153

DATA 2

.x .xxx

HM-8808-8

HM8808A-8

HM-8808 Timing Diagrams (Continued)
WRITE CYCLE 1

(Notes 1, 3, 4)

TAVAX
1101

A

X)

-

Vi

KX
TAVWL

TWLWH

TWHAX

1141

1121

1161

1//////////////////////////////////

1111

r

D

TELWH

TWHQX

TDVWH

TWHDX

1181

1201

1241

1

~

TWLQZ
1231

Q

I

~

~

WRITE CYCLE 2 . (Notes 2, 4)

TAVAX
1101

r:x

'X

A

TAVEL

TELEH

TEHAX

1151

1131

1171

Vi ~

E

1//////////////////&
k

I

TDVEH

TEHDX

1191

1211

D

NOTES: 1. In Write Cycle 1, the module is first enabled and then data is strobed into the RAM with a pulse on" Write Enable (vi). Because Vi becomes valid
after the part is enabled, this Is sometimes referred to as a "late Write" cycle.
2. In Write Cycle 2 • Address (A) and Write Enable (W) are first set UP. and then data is strobed into the RAM with a pulse on
before the module is enabled, this i~ sometimes referred to as an "Early Write" cycle.

E. Because Wis valid

3. Output Enable (G) is normally held stable throughout the enlire cycle.IIG is held high,then the oulputs (0) remain In the high Impedance state. II
G Is held low, then it may be necessary to lengthen the cycle to prevent bus contention. This would occur if TWlQZ and TDVWH overlapped.
4. Data Inputs (D) and Data Outputs (0) are connected internally at the DO pins.

3-154

HM-8808-8

HM8808A-8

HM-8808A Timing Diagrams
READ CYCLE 1

(Note 1. 2)

TAVAX
(II

X

A

ItX

ADDRESS 1
121

o

READ CYCLE 2

ADDRESS 2

'IX

TAXOX

TAVOV

I

~

171

DATA 1

~

DATA 2

Y'N'lW

(Note 1)

TAVAX
A

E2

o

NOTES: 1. In a read cycle,

Wis held high.

2. In read cycle 2, the module is kept continuously enabled:

ofE1.

Gand Ei

are held at VIL. E2 is held at VIH.

E1

3. The AC liming of E21s the same as that
Only the polarity is reversed. While
is active low, E2 is active high. Therefore AC parameters that
refer to the falling edge of enable, such as TELQV.
be applied to the rising edge of E2, and parameters that refer to the rising edge of enable,
such as TEHQZ, can be applied to the falling edge of E2.

can

3-155

HM-8808-8
HM-8808A Timing Diagrams
WRITE CYCLE 1:

HM-8808A-8

(Continued)

Controlled by iN (Notes 1, 3, 4)

(101
TAVAX

A

1

ax

(~

1141 TA vWLI

TWLWH
1121

iii

TWHAX--!1161

~

I
E2

TELWH

1111

1111
TELWH

l{f{

INOT

1181

TWHQX_ 1241
TWHoX.., 1201

r----- TOVWH

o
1231 .... TWLQZ..,

'
~

Q
WRITE CYCLE 2:

Controlled by

E1

(Notes 2, 4)

1101

X(. .

-------:AVAX -------;)-

Vi \m\.
Ei

•

TAVEL"
1151

E2 !/iU
IN oTE 51

WRITE CYCLE 3:

1191
TOVEH

E

Controlled by E2

.

EUH
1131

~

.. TEHAX
1171

121) '\\\\\\\\\\\\W
... TEHOX

1

(Notes 2, 4)

1101
TAVAX

\m\

X

AVEL.
1151

I

..

TELEH
1131

•

• TEHAX
1171

)x

~

E2
INOTE 5)

E

1191
ToVEH

, TEHOX

121)

1

NOTES: 1. In Write Cycle 1, the module is first enabled and then dala is strobed into the RAM with a pulse on Write Enable (W). Because
after the part is enabled, this is sometimes referred to as a "late Write" cycle.

Wbecomes valid

2. In Write Cycle 2 and 3, Address (A) and Write Enable <,W) are first set up, and then data is strobed into the RAM with a pulse on E1 or E2. Because
Wis valid before the module Is enabled, this is sometimes referred to as an "Early Write" cycle.
3. Output Enable «(3) is normally held stable throughout the entire cycle. If Gis held high, then the outputs (0) remain-in the high impedance state. If
G is held low, then it may be necessary to lengthen the cycle to prevent bus contention. This would occur if TWLQZ and TOVWH overlapped.
4. Data Inputs (D) and Data Outputs (Q) are connected Internally at the DQ pins.
5. The AC timing of E2 is the same as that of E1. Only the polarity is reversed. While E1 is active low, E2 is active high. Therefore AC parameters that
refer to the falling edge of enable, such as TELQV, can be applied to the rising edge of E2, and parameters that refer to the rising edge of enable,
such as TEHQZ, can be applied to the falling edge of E2.

3-156

HM-8808-8

HM-8808A-8

Low Voltage Data Retention
Harris CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention:

2. During power-up and power-down transitions, E (HM8808) must be held between 90% of VCC and VCC
+0.3V; E2 (HM-8808A) must be held above -0.3V and
below 10% of VCC.

1. The module must be kept disabled during data retention.
The Chip Enable (E) on the HM-8808 must be held between VCC-0.3V and VCC+0.3V. Chip Enable 2 (E2) on
the HM-8808A must be held between -0.3V and GND
+0.3V.

3. The RAM module can begin operation one TAVAX after
VCC reaches the minimum operating voltage (4.5V).

HM-8808 Data Retention Timing
DATA RETENTION MODE

111

TAVAX

vee -----___..
4.5V-- - - - VI H7T17TTTT:rTTT77TT"!rTm'Tr""-i

E

veeDR
VILu.u..U.t.U..u.u.J

GND- - - - - - - - _ - - _______ - - - - - - -

- - - - --

HM-8808A Data Retention Timing
DATA RETENTION MODE

vee------------~

4.5V - - - - VI H ",,"",,",,"""""",nTTI

-

111

TAVAX
E2

veeDR
GND~~~~~~~+_------------------------------------~~uu~

3-157

HM-8808-8

HM-880BA-8

Packaging
28 PIN MODULE

I.
•

NOTE: All Dimensions are

1.386
1.414

~
Max

.\

• Dimensions are in inches.

3-158

mHARRIS

HM-8816H-8
16K

X

June 1989

8 High Speed Asynchronous
CMOS Static RAM Module

Features

Pinout
TOP VIEW

• Low Standby Supply Current ••••••••••••••••••••••••••••• 8001JA,
• Low Operating Supply Current ••••••••••••••••••••••••••• .4OOmA
• Fast Access Time ••••••••••••••••••••••••••••••••••••••••••• 70ns
• Low Data Retention Supply Voltage ••••••••••••••••••••••••• 2.0V
• Wide Operating Temperature Range ••••••••••• -SSOC to +12S0C

NC
A12
A7

• CMOS/TTL Compatible Inputs/Outputs

A6

• JEDECApproved Pinout

AS

• Full CMOS - Six Transistor RAM Cells

A4

• No Clocks or Strobes Required
• Single SV Power Supply
• Standard DIP Size ••••••••..•••••••••••••••••••••••••• 0.6" x 1.5"

A3
A2

Al

• Easy Microprocessor Interfacing
• Gated Inputs

AO

Description

000

The HM-8816H-8 is a high speed, asynchronous CMOS static RAM
module, based on a multi-layer, co-fired, dual-in-line ceramic substrate
and eight HM-65262 16K x 1 asynchronous CMOS static RAMs
packaged in leadless chip carriers. The HM-8816H-8 uses on-substrate
decoupling capacitors packaged in leadless chip carriers to reduce
electrical noise and improve reliability. The pinout of the HM-8816H-8
conforms to the JEDEC 8-bit wide, 28 pin RAM standard, which allows the
system designer to design sockets that will accomodate a variety of
industry standard RAMs and EPROMs. The HM-8816H-8 also has gated
inputs to simplify system design for optimum standby supply current.

DOl

>-

enC:

00

002

====
==

c..>W

GND

The HM-65262 RAMs used in this module are full CMOS devices, utilizing
arrays of six transistor (6T) memory cells for the most stable and lowest
possible standby supply current over the full military temperature range. In
addition to this, the high stability of the 6T cell provides excellent protection
against soft errors due to electrical noise and alpha particles. This stability
also improves the radiation tolerance of the RAMs over that of four
transistor devices.

Functional Diagram
AOAIJ

14

TRUTH TABLE

14

AOAIJ

Iii

iii

E

E

0

DIl7
11

14 AOAIJ

-DIlS
-D1l5
-D1l4
-DIlJ
-D1l2
- Dill
D

Iii

MODE

E

W

Standby (CMOS)
Standby (rTL)
Read
Write

VCC
VIH
VIL
VIL

X
X
VIH
VIL

PIN DESCRIPTIONS
PIN

AO-A13
DOO-D07

DIlO
11

E
Vi
VCC
GND

CAUTION: These devices ate sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1989

3-159

FUNCTION
Address Inputs
Data Input/Outputs
Chip Enable
Write Enable
Power (+5V)
Ground

Specifications HM-8816H-8
Absolute Maximum Ratings·
SupplyVoltage ••.•....•..•..••.•..•.....•..•.•••.•.••.•.••.•.••••.•..•••.•.••••.••.•••.......•••••.••..•••••••• +7.0V
Input or Output Voltage Applied •.•.••••........••..•.••......••••.•.••.•.•.•..•••.••.••••....••• GND -0.3V to VCC +0.3V
Storage Temperature Range .•.••••..••••.•.••..•••••••.•.•••••••.•.••..•..•..•••.••.•.•.......•.•.•.• -65OC to +15QOC
Gate Count ..•.•.•••••.•••...••..••.•••.•..•..•.......•.••..•............•.•...............•••................ 210000
Junction Temperature ••.......•.•..••.•..•........••••.•.•....•.•••••••••••.•..•.••.••••.••••••.............•. +1750 C
Lead Temperature (Soldering, Ten Seconds) ........................•.•.••.•.•.....•••..••..•.••.......•.•.....•.. +3000 C
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devics. This;s a stress only rating

and functiona, operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not
implied.

Operating Conditions
Supply Voltage ........•••.•.•.•.•.......•...•..••.•.......•••.•.•..•.••.••.••.•..•.••.•.••.•••...........• 4.5V to 5.5V
Operating Temperature Range ......••.••..•.••.........•..•.••••...•......•..•••.••..•........•••.•.• -55 0 C to +1250 C

D.C. Electrical Specifications vcc = 5V ± 10%; TA = -550 C to +1250 C
MIN

MAX

UNITS

ICCSBI

Standby Supply Current (CMOS)

-

800

pA

10 = 0, E = VCC - 0.3V

ICCSB

Standby Supply Current (TTL)

-

40

mA

10=O,E=VIH

ICCEN

Enabled Supply Current

mA

10 = 0, E = VIL, VIN = VIH or VIL

Operating Supply Current (Note 3)

-

400

ICCOP

400

mA

10= 0, f= .1 MHz, E =VIL,
VIN=VCCorGND

SYMBOL

ICCDR

PARAMETER

-

320

pA

VCC = 2.0V, E = VCC· - 0.3V,10 = 0

-1

+1

pA

VIN = VCC or GND

IsO Leakage Current

-1

+1

pA

VIO = VCC or GND

Data Retention Supply Voltage

2.0

-

V

E=VCC

-

0.4

V

IOL=8.0mA

2.4

-

V

IOH=-4.0m~

V

IOH=100pA

Data Retention Supply Current
Input Leakage Current

II
1I0Z
VCCDR
VOL

TEST CONDITIONS

Output Voltage Low

VOH1

Output Voltage High

VOH2

Output Voltage High (Note 2)

VCC-0.4

VIL

Input Voltage Low

0

0.8

V

VIH

Input Voltage High

2.4

VCC

V

MAX

UNITS

Input Capacitance

70

pF

f= 1MHz, VIN =VCCorGND

InpuVOutput Capacitance

25

pF

f = 1 MHz, VIO = VCC or GND

CapaCitance (Note 2)
SYMBOL
CI
CIO

PARAMETER

TEST CONDITIONS

NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns max.; Input and output timing reference level: 1.5V; Output Load:
equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

2. Tested at initial design and after major design changes.

3. Typical'derallng: 40mAIMHz increase in leeop.
4. vee = 4.SV and S.SV.

3-160

1TTL gate

Specifications HM-8816H-8

= 5V ± 10%;

A.C. Electrical Specifications vcc

TA

= -55 0 C to +1250C
HM-8816HB

NO.

MIN

PARAMETER

SYMBOL

HM-8816H

MAX

MIN

70

-

85

70

5

MAX

UNITS

NOTES

READ CYCLE

-

ns

1,4

85

ns

1,4

85

ns

1,4

ns

2,4

5

-

40

0

(1)

TAVAX

tRC

Read Cycle Time

(2)

TAVQV

IAA

Address Access Time

(3)

TELQV

tCE

Chip Enable Access Time

-

(4)

TELQX

tLZ

Chip Enable Output Enable Time

5

(5)

TEHQX

Chip Enable Output Hold Time

5

(6)

TAXQX

tOH

Address Ouptut Hold Time

5

-

(7)

TEHQZ

tHZ

Chip Disable Output Disable Time

0

70

5

ns

2,4

ns

2,4

40

ns

2,4

1,4

WRITE CYCLE
(8)

TAVAX

tWC

70

-

85

-

ns

(9)

TELWH

tCW

Chip Enable to End of Write

WConlrolied

65

-

75

-

ns

1,4

(10)

TELEH

tCW

Chip Enable to End of Write

EControlied

65

-

75

-

ns

2,4

(11)

TWLWH

tWP

Write Pulse Width

55

-

60

-

ns

1,4

(12)

TAVWL

lAS

Address Setup Time

0

-

ns

1,4

-

ns

2,4

ns

1,4

>"'c:
cc

ns

2,4

c.>W

. Write Cycle Time

(13)

TAVEL

lAS

Address Setup Time

EControlied

0

(14)

TWHAX

tWR

Write Recovery Time

WConlrolied

10

(15)

TEHAX

tWR

Write Recovery Time

EControlied

10

-

(16)

TDVWH tOW

Data Setup Time

WConlrolied

30

-

(17)

TDVEH

tOW

Data Setup Time

EControlied

30

(18)

TWHDX

tDH

Data Hold Time

WConlrolied

(19)

TEHDX

tDH

Data Hold Time

EControlied

(20)

TWLQZ

tWZ

(21)

TWHQX tOW

WControlied

0

0

10

-

10

35

-

35

5

-

5

-

10

-

10

-

ns

1,4

Write Enable Low to Output Off

-

40

-

40

ns

2,4

Write Enable High to Output On

0

-

0

-

ns

2,4

NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 50S max.; Input and output timing reference level: 1.5V; Output
and CL = 50pF (min) - for CL grealer than 50pf. access lime is derated by 0.1505 per pF.
2. Tested at initial design and after major design changes.

3. Typical derating: 40mNMHz increase in

recop.

4. vee = 4.SV and S.SV.

3-161

ns

1,4

ns

2,4

ns

1,4

Load:l TTL gale equivalent

:;::;:
:;:

HM-8816H-8
Timing Diagrams
READ CYCLE 1: CONTROLLED BYE

E-----,'

NOTE:

WIs held high for entire cycle and 0

Is ignored. Address is stable by the time Egoes low and remains valid until Egoes high.

READ CYCLE 2: CONTROLLED BY ADDRESS

CD

TAVAX

A
~---TAvnv--~

®

Q
NOTE:

Vi is high for -,he enllre cycle and

0 Is Ignored. E Is stable prior to A. becomln.g valid and after A becomes invalid.

WRITE CYCLE 1: CONTROLLED BY Vi (LATE WRITE)

®

1 - - - - - TAVAX - - - - + - 1
A

®

__~~&"\.,~----TELWH--~1~~~~~_______

w
o
@
Q TELnX

NOTE: In this mode, E rises after W. The address must remain stable whenever both E and

3-162

Vi are Low.

HM-8816H-8
Timing Diagrams
WRITE CYCLE 2: CONTROLLED BYE (EARLY WRITE)

: @ TAVEL
E

~t:-"'I----

®

TAVAX

1!TEHAX
@

n---+--~~~-----t--~~~>-

",Ie

C> C>

iii

W

NOTE: In Ihis mode, rises after E. K falls before Eby a lime exceeding TWLQZ (Max) - TELQX (Min), and rises
after E by a tima exceeding TEHQZ (Max) - TWHQZ (Min), then a will remain in the high impedance state
throughout the cycle. The address must ramain stable whenever E and Vi are both low.

3-163

....
w
====

==

HM-8816H-8
Packaging
28 PIN MODULE

I

'I

1.490
1.520

•

j(JDE[Jlll

~.'Id~i~
T
f .035-~11I
~
I 1.I

--l l-

I

.048

,.100Hse

&!!

NOTE: All Dimensions are

t

.023

~
Max

• Dimensions are in Inches.

3-164

f

'009iL
.015

m

HM-8832-8

HARRIS

32K X 8 Asynchronous
CMOS Static RAM Module

June 1989

Features
•
•
•
•
•
•
•
•
•
•
•
•
•

Pinout
TOP VIEW

Full CMOS Six Transistor Memory Cell
Low Standby Supply Current •••••••••••••••• 250flA
Low Operating Supply Current •••••••••••••• 15mA
Fast Address Access Time ••••••••••••••••••• 180ns
Low Data Retention Supply Voltage •••••••••••• 2.0V
CMOSITTL Compatible Inputs/Outputs
JEDEC Approved Pinout
Equal Cycle and Access Times
No Clocks or Strobes Required
Single 5V Power Supply
Easy Microprocessor Interfacing
Operating Temperature Range ••• -55 0 C to +125 0 C
Standard DIP Size - 0.6" x 1.4"

Description
The HM-8832-8 is a 32K x 8 Bit Asynchronous CMOS
Static RAM Module based -on a multi-layered, co-fired,
dual-in-Iine ceramic substrate, four HM-65642 CMOS
Asynchronous Static RAMs, and an HCT-138 high-speed
CMOS decoder, all mounted in ceramic leadless chip carriers. In addition to this, each module is equipped with a
ceramic capacitor to minimize power supply noise and
reduce the need for external decoupling. Furthermore, this
capacitor is sealed in a ceramic leadiess carrier for maximum reliability, even in extreme environments. All inputs on
the HM-8832-8 are gated by the E input to simplify system
design requirements to obtain the minimum standby and
data retention supply current. The pinout of the HM-8832-8

conforms with the JEDEC standard for eight-bit wide, 28
pin RAMs, which allows the module to be pin compatible
with future generations of high density RAMs and EPROMs.
The HM-65642 RAMs used on the HM-8832-8 module are
full CMOS devices, utilizing arrays of six-transistor (6T)
memory cells for the most stable and lowest possible
standby and data retention supply current over the full military operating temperature range. In addition to this, the
high stability of the 6T cell provides excellent protection
against soft errors due to power supply noise and alpha
particles. This stability also improves the radiation tolerance
of the module over that of RAMs utilizing four transistor (4T)
Mix-MOS memory cells.

Functional Diagram

TRUTH TABLE
MODE

AO-A12------~------------------_,
DQO-DQ7-----1~----------------_,

W---1~+-------------~
G--~~-+------------~

E

W

G

Standby (CMOS)

VCC

X

X

Standby (TTL) .

VIH

X

X

Enabled (High Z)

VIL

VIH

VIH

Read

VIL

VIH

VIL

Write

VIL

VIL

X

PIN DESCRIPTION
PIN

Address Inputs

DOO-D07

Data Input/Output

E

Chip Enable

G

Output Enable

W

Write Enable

vec

Power (+SV)

GND

Ground

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be fOllowed.
Copyright © Har'ris Corporation 1989

3-165

FUNCTION

AO-A14

>",a:

00

:;;:;;
'-'w
:;;

Specifications HM-8832-8
Absolute Maximum Ratings
Supply Voltage •••••••••.•••.•.•••••••••••••••••.••.•••••••••.••.••.••.•.••••••••.••••.••.••••••••.•••••••.•••.• +7.0V
Input, Output or I/O Voltage Applied •••••••••.••••••••••••••••••••••••••.•••••••••••••••••.••••••.• GND -0.3V to VCC +O.3V
Storage Temperature Range •.••.•••••••••.••••••.••••••••••••••••••.••.....••••••••.••••..•••••••••••• -65 0C to +1500 C
Gate Count ••••••••••••••••••••••••••••.••.•••••••••••••••••.••.•••••.••••••.••.••.•••.••••.•••••••.•••• 405,230 Gates
Junction Temperature .••••••.••.•••••.•••••••••••••••.•••••••.••.••.••••••••••••.••••••••.••••••••••••••••••.•• +175OC
Lead Temperature (Soldering, Ten Seconds) •.•••.•••••••••••••••.••.•••••••••••••••.•••••••••••.•••••••••.••.••••• +3000C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device, This is a stress only rating and
operal/on of the devica at these or any other conditions above those indicated in the operation section of this speCification Is not implied.

Operating Conditions
Operating Voltage Range ••••••••••••.••••.•••••.••••.••••••••••.••••••••••••••••••••.•.••••.••••••.•••.•. +4.5V to +5.5V
Operating Temperature Range •••••••••••••••.••.••••••••••••.•••.•.•••••••••.••.•••..•••.•.••••..•••.• -550C to +125 0C

D.C. Electrical Specifications

(Note 4)

VCC = 5V:!: 10%; TA = -550 C to +125 0 C

PARAMETER

SYMBOL

MIN

ICCSBI

Standby Supply Current (CMOS)

-

ICCSB

Standby Supply Current (TTL)

-

MAX

UNITS

900

pA

10 = 0, E = VCC -0.3V

TEST CONDITIONS

10

mA

10=O,E=VlH

10

mA

10=O,E=VIL

15

mA

10 = 0, f= lMHz,E=VIL,
VI = VCC or GND
VCC = 2.0V, E = VCC -0.3V

ICCEN

Enable Supply Current

ICCOP

Operating Supply Current (Note 3)

ICCDR

Data Retention Supply Current

-

750

pA

VCCDR

Data Retention Supply Voltage

2.0

-

V

Input Leakage Current

-1.0

+1.0

pA

VI = VCC or GND

IIOZ

Inpul/Output Leakage Current

-1.0

+1.0

pA

VIO = VCC or GND

VIL

Input Low Voltage

0

0.8

V

II

E=VCC

VIH

Input High Voltage

2.4

VCC

V

VOL

Output Low Voltage

-

0.4

V

IOL=4.0mA

VOHI

Output High Voltage

2.4

V

10=-1.0mA

VOH2

Output High Voltage (Note 2)

-

V

10=-100pA

VCC-O.4

CapaCitance (Note 2)
SYMBOL

MAX

UNITS

Address Input Capacitance

40

pF

Data, Output Enable Capacitance

45

pF

VDO, VG = VCC or GND, f = 1 MHz

CEN

Chip Enable Capacitance

15

pF

VEN = VCC or GND, f = 1 MHz

CW

Write Enable Capacitance

60

pF

VW=VCCorGND,f= lMHz

CA
CDO,CG

PARAMETER

TEST CONDITIONS
VA=VCCorGND, f= lMHz

NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent
CL = 100pF (min) including scope and jig - for Cl graater than 100pF. access time is derated by 0.15ns per pF.
2. Guaranteed but nol tested.
3. Typical derating 5mNMHz Increase in ICCOP.
4. All devices tested at worst case temperature and supply voltage limits.

3-166

Specifications HM-8832-8
A. C. Electrical Specifications (Notes 1.4)

PIN NO.

SYMBOL

VCC

= 5V:I: 10%;

TA

= -550 C to +1250 C
-MIN

PARAMETER

MAX

UNITS

180

-

ns

-

180

ns

TEST CONDITIONS

READ CYCLE
(1)

TAVAX

IRC

Read Cycle Time

(2)

TAVOV

1M

Address Access Time

(3)

TELOV

tCE

Chip Enable Access Time

-

180

ns

(4)

TGLOV

tOE

Output Enable Access Time

-

75

ns

(5)

TELOX

ILZ

Chip Enable Output Enable lime

10

(6)

TGLOX

tOLZ

Output Enable Time

5

(7)

TAXOX

tOH

Address Output Hold Time

10

-

ns

(Note 2)

ns

(Note 2)

ns

(Note 2)

(8)

TEHOZ

tHZ

Chip Disable Output Disable lime

0

80

ns

(Note 2)

(9)

TGHOZ

IOZ

Output Disable Time

0

55

ns

(Note 2)

WRITE CYCLE
(10)

TAVAX

tWC

Write Cycle Time

180

-

ns

(11)

TWLWH

tWP

Write Pulse Width

95

-

ns

(12)

TELWH

tCW

Chip Enable to End 01 Write

WControiled

95

(13)

TELEH

tCW

Chip Enable to End 01 Write

EControiled

90

(14)

TAVWL

lAS

Address Setup Time

WControiled

(15)

TAVEL

lAS

Address Setup Time

EControiled

ns

30

-

30

-

ns
ns

(16)

TWHAX

tWR

Write Recovery Time

WControiled

10

(17)

TEHAX

tWR

Write Recovery Time

EControiled

40

(18)

TDVWH

tOW

Data Setup Time

WControiled

65

-

(19)

TDVEH

tOW

Data Setup Time

EControiled

65

-

(20)

TWHDX

tDH

Data Hold Time

WControiled

10

EControiled

ns

(Note 2)

ns

ns

>",cr:
(Note 2)

==

(Note 2)

ns
ns

(Note 2)

(21)

TEHDX

tOH

Data Hold Time

40

-

ns

(Note 2)

(22)

TWLOZ

tWZ

Write Enable Output Disable Time

-

55

ns

(Note 2)

(23)

TWHOX

tOW

Write Disable Output Enable lime

5

-

ns

(Note 2)

ns

NOTES:
1. Input pulse levels: 0 to 3.0Vj Input rise and fall limes: 5ns (rna,,); Input and output timing reference level: 1.5V; Output load: 1 TTL gata equivalent
CL =- 100pF (min) including scope and jig - for CL greater than 100pF, acCBSS time is derated by 0.15n8 per pF.
2. Guaranteed but not tested.
3. Typical derating SmA/MHz increase in ICCOP.
4. All devices tested at worst case temperature and supply voltage limits.

3-167

00

..,w
====

Specifications HM-8832B-8
Absolute Maximum Ratings
Supply Voltage •••••..•...•••••.......•.•••........•••......•...••.•••..•.••••..•••••...•••••••••••.•........... +7.0V
Input, Output or I/O Voltage Applied •••.••••••...••••.....•••.•.•.......•••••.••....•.••..•.•...... GND -0.3V to VCC +O.3V
Storage Temperature Range .•.......•.•••••.....•..••.........•.•..•.••.•..•..•••••••...••.•..•••••••• -65 0 C to +150 0 C .
Gate Count ......••..•.......•••. ; ........................................................................ 405,230 Gates
Junction Temperature .•...••••••••••.•..•••••.•.•••...••••..•.•.......••••.••..•......••.••.•••.......•••••.••• +1750 C
Lead Temperature (Soldering, Ten Seconds) •••••.....•••..•......•.••.••.........••.••.•....•.•••.•..•.•.•••••..•• +300 0 C
CAUTION: Stresses above those Iist8d in the "Absolute Maximum Ratings" may cause permanent damage to the device. This ;s a stress only rating and
operation.of the device at these or any other conditions above those indicated in the operation section of this specification ;s not implied.

Operating Conditions
Operating Voltage Range •..•.••.••••••.•••..••••••.••••••..••••••.••••••••••.••••••.••••.••••••••••••••••• +4.5V to +5.5V
Operating Temperature Range .••••..•.•.••.•••........•.•.•..•...••...••.••..•.•.•••..•......•.......•.-550 C to +125 0 C

D.C. Electrical Specifications (Note 4)

VCC = 5V

± 10%; TA = -55 0 C to +125 0 C

PARAMETER

MIN

MAX

-

250

f1A

2

mA

10=O,E=VIH

-

10

mA

10=O,E=VIL

15

mA

10 = 0, f = 1 MHz, E = VIL,
VI=VCCorGND

Data Retention Supply Current

-

200

f1A

VCC = 2.0V, E = VCC -0.3V

Data Retention Supply Voltage

2.0

-

V

Input Leakage Current

-1.0

+1.0

f1A

VI=VCCorGND

IIOZ

InpuVOutput Leakage Current

-1.0

+1.0

f1A

VIO = VCC or GND

VlL

Input Low Voltage

0

0.8

V

SYMBOL
ICCSBI

Standby Supply Current (CMOS)

ICCSB

Standby Supply Current (TIL)

ICCEN

Enable Supply Current

ICCOP

Operating Supply Current (Note 3)

ICCDR
VCCDR
II

UNITS

TEST CONDITIONS
10 = 0, E = VCC -0.3V

E=VCC

VIH

Input High Voltage

2.4

VCC

V

VOL

Output Low Voltage

-

0.4

V

IOL=4.0mA

VOH1

Output High Voltage

2.4

'V

10=-1.0mA

VOH2

Output High Voltage (Note 2)

-

V

10=-1OOI'A

VCC-O.4

Capacitance (Note 2)
SYMBOL

PARAMETER

MAX

UNITS

Address Input Capacitance

40

pF

Data, Output Enable Capacitance

45

pF

VDO, VG = VCC or GND, f = 1 MHz

CEN

Chip Enable Capacitance

15

pF

VEN = VCC or GND, f = 1 MHz

CW

Write Enable Capacitance

60

pF

VW=VCCorGND, f= 1MHz

CA
CDO,CG

TEST CONDITIONS
VA=VCCorGND, f= 1MHz

NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent
CL = 100pF (min) including scope and jig - for CL greater than 100pF, access time is derated by 0.15ns per pF.

2. Guaranteed but not tested.
3. Typical derating 5mAIMHz Increase in ICCOP.
4. All devices tested at worst case temperature and supply voltage limits.

3-168

Specifications HM-8832B-8
A. C. Electrical Specifications (Notes 1, 4)

PIN NO.

VCC.= 5V

± 10%; TA = -550C to +1250 C

PARAMETER

SYMBOL

MIN

MAX

UNITS

TEST CONDITIONS

180

-

ns

-

180

ns

180

ns

75

ns

10

-

ns

(Note 2)

READ CYCLE
(1)

TAVAX

IRC

Read Cycle Time

(2)

TAVQV

IAA

Address Access Time

(3)

TELQV

tCE

Chip Enable Access Time

(4)

TGLQV

tOE

, Output Enable Access Time

-

Chip Enable Output Enable Time

(5)

TELQX

tLZ

(6)

TGLQX

tOLZ

Output Enable Time

5

(Note 2)

TAXQX

tOH

Address Output Hold Time

10

-

ns

(7)

ns

(Note 2)

(8)

TEHQZ

tHZ

Chip Disable Output Disable Time

0

80

ns

(Note 2)

(9)

TGHQZ

tOZ

Output Disable Time

0

55

ns

(Note 2)

ns

WRITE CYCLE
(10)

TAVAX

tWC

Write Cycle Time

180

(11)

TWLWH

tWP

Write Pulse Width

95

-

(12)

TELWH

tCW

Chip Enable to End 01 Write

WControlied

95

-

ns

(13)

TELEH

tCW

Chip Enable to End 01 Write

EControlied

90

-

ns

(14)

TAVWL

lAS

Address Setup Time

WControlied

30

-

ns

(15)

TAVEL

lAS

Address Setup Time

EControlied

30

-

ns

(16)

TWHAX

tWR

Write Recovery Time

WControlied

10

-

ns

ns

(17)'

TEHAX

IWR

Write Recovery Time

EControlied

40

-

ns

(18)

TDVWH

lOW

Data Setup Time

WControlied

65'

-

ns

(19)

TDVEH

tDW

Data Setup Time

ECootrolied

65

-

ns

(20)

TWHDX

tDH

Data Hold Time

WControlied

10

ns

EControlied

(Note 2)

...

",Ie

(Note 2)

(Note 2)

(Note 2)

(21)

TEHDX

tDH

Data Hold Time

40

-

ns

(Note 2)

(22)

TWLQZ

tWZ

Write Enable Output Disable Time

-

55

ns

(Note 2)

(23)

TWHQX

tOW

Write Disable Output Enable Time

5

-

ns

(Note 2)

NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent
CL
100pF (min) including scope and jig - for CL greater than l00pF, access time is derated by 0.15n5 per pF.
2. Guaranteed but not tested.

=

3. Typical derating 5mNMHz increase in
4. All devices tested

at

recop.

worst case temperature and supply vollage limits.

3-169

00

::;;::;;

~

....::;;

HM-8832-8
Timing Diagrams
READ CYCLE I: ADDRESS CONmOLLED (Notes 1,2)

(1)
~----TAVAX----~

A

-:l~

X

ADDRESS 1 VALID

~Tl~hva xxxxxx

READ CYCLE II:

-:l~X

ADDRESS 2 VALID

xxx

I4-T~bx.
DATA 1 VALID

7X

DATA 2 VALID

X

E OR G CONTROLLED (Note 1)

(1)
TAVAX

(2)

1111

~x

TAvav

E 2k

.1-I--

s. .

(3) TElOV
(5) TELOX

...

G ..... s-s~s s,....~
.

(4)TGLOV~

(6)

TGLOX

a

(

READ CYCLE NOTES:

1 In a read cycle, W is held high.
2. In read cycle 1, the module Is kept continuously enabled: E and

G are held low.

3-170

~fu(:5?
'1
TEHOZ

f??????
,OJ ;j
TGHOZ

)~

HM-8832-8
Timing Diagrams
WRITE CYCLE I: Iii CONTROLLED (Note 1)

(10)
TAVAX

A
TAVWL' •

(11)
TWLWH

~ ~

"'Vk
I

(16)
TWHAX

///////
I

(12)
TELWH

XX)-

en":

CICI

::;:::;:

""w::;:

(19)1-- TDVEH

--1.1...- TEHDX -1(21)

o >OOOOOOO",a:

00

====
==

c.>W

Specifications HM-92560-8
Absolute Maximum Ratings
Supply Voltage •••.••.•••••••••••••••••••.•••••••••••••••••.••••••••••.•••••••••••••••••••••••••• +7.0V
Input, Output or I/O Voltage Applied •.•••••.•••••••••••••••••••••••••.••..•••••••• GND -0.3V to VCC +0.3V
Storage Temperature Range ••••.•••••••••••••••••••••••••••••••••••••••••••••••••.••••• -650C to + 1500C
Gate Count. • • • • • • • • • • • . • • . . • • • . • • • • . • • . • • • • • • • • • • • • . . • • • • • • • . • . • . • . • • • • • • • • • • • • • . • • • • • •• 415250 Gates
Junction Temperature ..•.•••••••.•••••••.•••••.••••.•••••••.••.••.•••••••••••• " •••••••••••••••. +1750 C
Lead Temperature (Soldering, Ten Seconds) ••.•••••••••••••••.••••••••.•..••••••••••••••••••••••• +3000C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this
specification is not implied.

Operating Conditions
Operating Voltage Range •••••.•.••••••••••••••••••.•••••••.•.••.•••••.••.••.••••.••••••• +4.5V to +5.5V
Operating Temperature Range •.•..•••••.•.•••••••...••.••••.••••.•...........•••••••••• -550 C to +12S0 C

D.C. Electrical Specifications vcc = SV :I: 10%; TA = -SSoc to +12S 0 C
SYMBOL

MIN

MAX

ICCSS

Standby Supply Current

PARAMETER

-

500

UNITS

ICCOP

Operating Supply Curren! 16K x 16
(Note 3)

30

mA

E = IMHz,lO =0, VI =VCCorGND
G=VCC

ICCOP

Operating Supply Current 32K x 8
(Note 3)

-

tu\

10 = 0, VI = VCC or GND

TEST CONDITIONS

IS

mA

E = 1 MHz,lO = 0, VI =VCCorGND
G=VCC

ICCDR

Data Retention Supply Current

-

350

pA

10=0, VCC = 2.0, VI =VCCorGND,
E=VCC

Data Retention Supply Voltage

2.0

-

V

Input Leakage Curren!

-5

+S

pA

VI=VCCorGND

IIOZ

InpuVOutput Leakage Curren!

-S

+5

pA

VIO=VCCorGND

VIL

Input Low VoHage

0

0.8

V

VCCDR
II

VIH

Input High Voltage

VCC-2.0

VCC

V

VOL

Output Low Voltage

-

0.4

V

10 = 3.2mA

VOHI

Output High Voltage

2.4

V

10=-1.0mA

VOH2

Output High Voltage (Note 2)

VCC-O.4

-

V

10=-I00pA

CapaCitance
SYMBOL

MIN

MAX

UNITS

CIA

Address Input Capacitance (Note 2)

PARAMETER

-

200

pF

VI =VCCorGND, f= IMHz

CIEI

Enable Input CapacHance 16K x 16
(Note 2)

-

100

pF

VI =VCCorGND, f= IMHz

CIE2

Enable Input CapacHance 32K x 8 (Note 2)

CIGI

Output Enable Input Capacitance 16K x 16
(Note 2)

CIG2

Output Enable Input CapaCitance 32K x 8
(Note 2)

CIOI

TEST CONDITIONS

50

pF

VI =VCCorGND,f= IMHz

ISO

pF

VI = VCC orGND, f = 1 MHz

-

100

pF

VI = VCC orGND, f = 1 MHz

InpuVOutput Capacitance 16K x 16
(Note 2)

-

150

pF

VI/O = VCC or GND, f = 1 MHz

CI02

InpuVOutput Capacitance 32K x 8
(Note 2)

2S0

pF

VI/O =VCC orGND, f = IMHz

CIW

Write Input CapaCitance (Note 2)

-

200

pF

VI =VCCorGND,f= IMHz

-

pF

f=IMHz

CVCC

Decoupling Capacitance

O.S

NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 10ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTl gate equivalent
CL = 50pF (min) - for CL greater than SOpF. access time is derated by 0.15ns per pF.
2.

Tested at Initial design and after major deSign changes.

3.

Typical derating SmA/MHz increase In leeop.

4.

vee

= 4.SV and S.SV.

3-174

Specifications HM-92560-8
A.C. Electrical Specifications

VCC =

sv ± 10%; TA = -SSoC to +12S oC
MAX

UNITS

TEST CONDITIONS

1S0

ns

(Notes 1, 4)

170

ns

(Notes 1,4)

10

-

ns

(Notes 2,4)

Chip Enable Output Disable Time

-

70

ns

(Notes 2,4)

(S)TGLQX

Output Enable Output Enable Time

10

(6)TGLQV

Output Enable Output Valid Time

(7)TGHQZ

Output Enable Output Disable Time

-

(8)TELEH

Chip Enable Pulse Negative Widlh

150

(9)TEHEL

Chip Enable Pulse Positive Width

80

(10) TAVEL

Address Setup Time

20

(11)TELAX

Address Hold Time

50

-

(12)TWLWH

Write Enable Pulse Widlh

150

(13)TWLEH

Write Enable Pulse Setup Time

(14)TELWH

PARAMETER

SYMBOL

MIN

Address Access Time

-

(3)TELQX

Chip Enable Output Enable Time

(4)TEHQZ

(1)TELQV

Chip Enable Access Time

(2)TAVQV

-

ns

(Notes 2,4)

70

ns

(Notes 1,4)

70

ns

(Notes 2,4)

-

ns

(Noles 1, 4)

ns

(Noles 1, 4)

ns

(Noles 1, 4)

ns

(Notes 1, 4)

_.

ns

(Noles 1, 4)

150

-

ns

(Notes 1, 4)

Write Enable Pulse Hold Time

150

-

ns

(Notes 1,4)

(15)TDVWH

Data Setup Time

80

ns

(Notes 1,4)

(16)TWHDX

Data Hold Time

20

-

(17)TWLDV

Wrile Data Delay Time

70

(18)TELEL

Read or Write Cycle Time

230

ns

(Notes 1, 4)

-

ns

(Notes 1, 4)

-

ns

(Notes 1, 4)

NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall limes: 10ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent
CL = 50pF (min) - for Cl grealer than 50pF, access lime is derated by 0.15"s per pF.

2. Tested at initial design and after major design changes.
3.

typical derating SmA/MHz increase in ICCOP.

4.

vee = 4.5V and 5.5V.

>.,,=
00
u
....
====

==

HM-92560-8
121

Read Cycle

_ TAVaV

- _ _ _ ------!

E
w--4---~~---4------------~~----~~------------

+ __---''--______+ ______+ __l--__-f__'---+-____

TIME _______
REFERENCE

-1

TRUTH TABLE
TIME'
REFERENCE

E

-,1

INPUTS

W

G

A

DO

FUNCTION

.H

X

X
X

X
V

Z
Z

L
L

H
H
H

, Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as - 1)
Cycle Ends, Next Cycle Begins (Same as 0)

0
1

2
3
4
5

H
X

H

H

X
X
X
X

L
L

X
X
X

V

X
V
V
Z
Z

The address information Is latched in the on chip registers
, on the falling edge of E(T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time' (T =' 1), the outputs become'

enabled but data is not valid until time (T =:2). W must-re:
main high throughout the read cycle. After the data has
been read, E may return high (T = 3). This will force the output buffers Into a high impedance mode at time (T = 4).

Write Cycle

TIME _ _ _ _ _- ' -____-1-________-+-____--:__-:::-__-:-____; -___
REFERENCE

-1

TRUTH TABLE
TIME
REFERENCE

E

Vi

G

A

DO

FUNCTION

-1

H

X
X

X

L
L

L

H
H
H
H
H
H
H

X
X
X

Memory Disabled
Cycle Begins, Addresses are Latched
Write Period Begins
Data In Is Written
Write Completed
Prepare For Next Cycle (Same As -1)
Cycle Ends. Next Cycle Begins (Same As 0)

0
1

2
3
4
5

INPUTS

-x.
f

H

"-

f

H

X
X

V

X
X
X
X
V

V

X
X
X

The write cycle is initiated on the falling edge of E (T = 0),
which' latches the address information in the on chip
registers. If a write cycle is to be performed where the
output is not to become active, Gcan be held high (inactive).
TWHDX and TDVWH must be met for proper device
operation regardless of G . If E and G fall before Iii falls
(read mode), a possible bus conflict may exist. If E rises
before Iii rises, reference data setup and hold times to the E

--

rising edge. The write operation is terminated by the first rising edge of W (T 2) or E(T 3). After the minimum E high
time (TEHEL), the next cycle may begin. If a series of
consecutive write cycles are to be' performed, the W line
may be held low until all desired locations have been written. In this case, data setup and hold times must be
referenced to the rising edge of E.

'

3-1713

=

=

HM-92560-8
Packaging
48 PIN MODULE

I

I

2.505
2.555

•

DDDo=rr

DDDD=[[
d

:ffi~175-

I
~O

T

.005
.050

~

~

==~Z1l: :~~~.:~~~

:~!:~II~--L

I,-r

ir;ooBSC

NOTE: All Dimensions are

.016---11.02l
~
Max

• Dimensions are in inches.

...

",0:

00

::E::E
c.>W
::E

3-177

mHARRIS

HM-92570-8,
256K Buffered Synchronous
CMOS RAM Module

June 1989

Features

Pinout
TOP VIEW

• Low Standby Current •••••••••••••••••••.•••••••••• 600JlA/3.5mA
• Fast Access Time •••••••••••••••••••••••••••••••••••••••••• 250ns
• Data Retention ••••••••••••••••••••••••••••••••••••. , ••••.•• 2.0V
• Three-State Outputs
• Organizable As 32K x 8 or 16K x 16 Array
• Buffered Address And Control Lines
• On Chip Address Registers

• 48 Pin DIP Pinout - 2.66w x 1.30w xO.29w
• Operating Temperature Range ••••••••••• .' ••••••• -55 0 C to +125 0 C

Description
The HM-92570-8 is a fully buffered 256K bit CMOS RAM Module
consisting of sixteen HM-6516 2K x 8 CMOS RAMs, two 82C82 CMOS
octal latching bus drivers, and two HCT-138 CMOS 3:8 decoders in
leadless chip carriers mounted on a multilayer ceramic sUbstrate. The
HM-9257D-8 RAM Module is organized as two 16K x 8 CMOS RAM arrays
sharing a common address bus. Separate data inpuVoutput buses allow the
user to format the HM-92570-8 as either a 16K x 16 or 32K x 8 array.
D",a:
00

====
c.>'"
==

Specifications HM-92570-8
Absolute Maximum Ratings
Supply Voltage •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.•••••••• +7.0V
Input, Output or 110 Voltage Applied •••••••••••••••••••••••••••.•••••••••••••••••• GND -0.3Vto vcc +0.3V
Storage Temperature Range ••••••••••••.••••••••••••••• : ••••••••••••••••••••••••••••••• -650 C to +1500C
Gate Count. •••••••••••••••.••••••••••••••••••.••••••••••••••••••••••••••••••••••••••••••• 417200 Gates
Junction Temperature ••••••••• : •••••••••••••••••• : ................................................. +1750 C
Lead Temperature (Soldering, Ten Seconds) .••••••••••••••••••••••••••••••••••••••••••••••••••••• +3000C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this
specification is not implJed.

Operating Conditions
Operating Voltage Range •••••••••••••.•••••••••••••••.•••••••••••••••••••••••••••••••••• +4.5V to +5.5V
Operating Temperature Range •••••.•••••••••••••••••••••••••••••••••.•••••••••••••••.•• -550 C to +12SOC

D.C. Electrical Specifications vcc = 5V:!: 10%; TA = -550C to +1250 C.
SYMBOL

PARAMETER

MIN

MAX

-

600

I!A

10 = 0, VI =VCC orGND

-

30

mA

E= 1MHz,I0 =0, VI =VCCorGND,
G=VCC

Operating Supply Current (Note 3)
32Kx8

-

15

mA

E= 1MHz,I0 =0, VI =VCCorGND,
G=VCC

Data Retention Supply VOI~age

-

450

I!A

licc = 2.0V,10 = 0, VI = VCC or GND
E=VCC
.
.

2.0

-

V

ICCSS

Standby Supply Current

ICCOP

Operating Supply Current (Note 3)
16Kx 16

ICCOP
ICCDR

UNITS

'.

VCCDR
II

Data Retention SupplyVoitage

TEST CONDITIONS

...

Input Leakage Current

-1.0

+1.0.

I!A

VI = VCC or.GND

IIOZ

Inpul/Output Leakage Current

-5.0

+5.0

pA

VO = VCC or GND

VIL

Input Low Voltage

0

0.8

V

VIH

Input High Voltage

3.5

VCC

V

0.4

V

10 = 3.2mA

V

10=-0.4mA

VCC-0.4

-

V

10=-100pA

MIN

MAX

UNITS

-

50

pF

VI =VCCorGND,f= 1MHz

50

pF

VI=VCC orGND, f= 1MHz

25

pF

VI=VCCorGND,f= 1MHz

50

pF

VI = VCCorGND, f= 1 MHz

VOL

Output Low Voltage

-

VOH1

Output High Voltage

2.4

VOH2

Output High Voltage (Note 2)

Capacitance
SYMBOL

PARAMETER

TEST CONDITIONS

CIA

Address Input Capacitance (Note 2)

CIE'

Decoder Enable Input Capacitance
16K x 16 (Note 2)

CIE2

Decoder Enable Input Capacitance
32K x 8 (Note 2)

CIG1

Output Enable Input Capacitance
16K x 16 (Note 2)

CIG2

Output Enable Input CapaCitance
32K x 8 (Note 2)

-

25

pF

VI=VCCorGND,f= 1MHz

CI01

Inpul/Output CapaCitance
16K x 16 (Note 2)

-

150

pF

VI/O =VCCorGND, f= 1MHz

CI02

InpullOutput CapaCitance
32K x 8 (Note 2)

-

250

pF

VI/O = VCC or GND, f = 1MHz

CIW

Write Input Capacitance (Note 2)

-

25

pF

VI =VCC orGND, f= 1 MHz

0.5

-

pF

f=1MHz

CVCC

Decoupling Capacitance

-

NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and (all lim as: 10ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent
CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

2. Tested at inllial design and after major design changes.
3. ICCOP is proportional to operating frequency.
4. VCC = 4.5V and 5.5V.

3-180

Specifications HM-92570-8
A.C. Electrical Specifications

vcc = sv ± 10%; TA = -SSoc 10 +12S oC

PARAMETER

SYMBOL
(l)TELQV

Chip Enable Access Time

MIN

MAX

UNITS

TEST CONDITIONS

-

250

ns

(Noles 1, 4)

(2)TAVQV

Address Access Time

-

270

ns

(Notes 1,4)

(3)TELQX

Chip Enable Output Enable Time

S

-

ns

(Noles 2,4)

(4)TEHQZ

Chip Enable Output Disable Time

-

lS0

ns

(Notes 2,4)

(S)TGLQX

Output Enable Output Enable Time

10

-

ns

(Notes 2,4)

(6)TGLQV

Output Enable Output Valid Time

120

ns

(Notes 1,4)

(7)TGHQZ

Output Enable Output Disable Time

150

ns

(Notes 2,4)

(8)TELEH

Chip Enable Pulse Negative Width

2S0

-

ns

(Notes 1,4)

(9)TEHEL

Chip Enable Pulse Positive Width

100

(10) TAVEL

Address Setup Time

20

(11)TELAX

Address Hold Time

120

(12)TWLWH

Write Enable Pulse Width

140

(13)TWLEH

Write Enable Pulse Setup Time

140

(14)TELWH

Write Enable Pulse Hold Time

250

(lS)TDVWH

Data Setup Time

(16)TWHDX

Data Hold Time

(17) TWLDV

Write Data Delay Time

120

(18)TELEL

Read or Write Cycle Time

350

(19)TAVAV

Enable Decoder Address Valid Time

270

-

ns

(Notes 1,4)

ns

(Notes 1,4, S)

ns

(Notes 1,4)

ns

(Notes 1, 4)

ns

(Notes 1, 4)

ns

(Notes 1, 4)

20

-

ns

(Notes 1, 4)

70

-

ns

(Notes 1, 4)

-

ns

(Notes 1, 4)

ns

(Notes 1, 4)

ns

(Applies OnlytoAll,A12, A13)

NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 10n5 (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent
CL

2.

= 50pF (min) -

for CL greater than 50pF, access time is derated by 0.15n5 per pF.

Tested at initial design and after major design changes.

3.

ICCOP is proportional to operating frequency.

4.

vee =

5.

Includes All, A12, A13.

4.5V and 5.5V.

3-181

HM-92570-8
~~TAvov.-#L-

Read Cycle

(10)

'E3A a"d ElBareoppo"lepol.flly 01 EIA

TAVEL

~LA~t:(11)

. : ::::::::'::~)K VALID

A

(9)~~~EL

-1
w
(4)---j

TELEL
TELEH

J

0].ill.E3A o

E1B.E2B,E38

. r;AVEL

TEHEL_

(8)

r------

-

(1 )
TELaV - - - (3) mox-( .........

.

GAo,Gij

"

__

(7)A000;

TAVAV

(19)

REFERENCE

I,

I

.,I

TIME

,

I

.

I

E

INPUTS
W
G

A

A11
A12
A13

H

X

X

X

X

H
H
H
H

X

V

L
L

L
L

X
X
X
X

V
V
V
V

H

X
X
X

X

H

DATA 1/0
DQ

V
V
Z
Z

V

The address information is latched in the on chip registers
on the falling edge of E (T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1), the outputs become
enabled but data is not valid until time (T = 2), IN must
(10~~

Write Cycle
.~d

remain high throughout the read cycle. After the data has
been read, E may return high (T = 3). This will force the
~tput buffers into a high impedance mode at time (T = 4).
G is used to disable the output buffers when in a logical "1"
state (T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is
ready for the next cycle.
,.;] TAVEL I- (10)

LtLAtI11)

~TAVEL

A
'E3A

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for next cycle (Same as -1)
Cycle ends, next cycle begins (Same as 0)

Z
Z
X

X

V

NEXT ADD

VALID ADD

~,lEL

E3Bareoppomepol.flly 01 EIA

THEH

E1A,E2A.EJA·

TELEl

TEHEl

.X.

(8)

E1B,E2A,ElB

(14)

~"""~""~ r(2)" A
rELWH

~

rOVWH

(18)

(9)

(13)

TWLEH

W

,I

I

3

2

TRUTH TABLE

2
3
4
5

(4)

TEHQZ

VALID DATA OUT
T(~)V

A"
A12
A13

-1
0
1

(18)
(9)

HIGH

TEHOZ

00--./

TIME
REFERENCE

(10)

ADD ~::::::-:-:-:.:-:.:::::: ::::::::::::::::::::-:-:.:-:-:~~ NEXT ADD

(15)

twHDX

(16)

VALID DATA IN

00

TAVAV

G HIGH

(19)

:~!~
A13

,I

.,I

TIME
REFERENCE

,I

I

I

2

3

.
I

I

s

TRUTH TABLE
TIME
REFERENCE
-1
0
1
2
3
4
5

E

INPUTS
W
G

H

X
X

L
L

L
H

H

X
X

H
H
H
H
H
H
H

A

A11
A12
A13

X

X

V

V
V
V
V

X
X
X
X

V

DATA 1/0

DO
X
X
X

V
X
X
X

X

V

The write cycle is initiated on the falling edge of E (T = 0),
which latches the address information in the on chip
registers. If a write cycle is to be performed where the
output is not to become active, G can be held high
(in-active). TDVWH and TWHD~ m~t be ...!!!et for proper
device operation regardless of G. If E and G fall be!2re W
falls (read mode), a possible bus conflict may exist. If E rise.!!.
before W rises, reference data setup and hold times to the E

FUNCTION
Memory Disabled
Cycle Begins, Addresses are Latched
Write Period Begins
Data In Is Written
Write Completed
Prepare For Next Cycle (Same As -1)
Cycle Ends, Next Cycle Begins (Same As 0)

rising edge. The write oper§!!ion is terminated by the fir~
rising edge of W (T = 2) or E (T = 3). After the minimum E
high time (TEHEL), the next cycle may begin. If a series of
consecutive write cycles are to be performed, the W line
may be held low until all desired locations have been
written. In this case, data setup and hold times must be
referenced to the riSing edge of E.

3-182

HM-92570-8
Packaging
48 PIN MODULE

I

I

ODoor--'oTr
D8DD~DUf
-iw=:~==~1~~~J ~:
2.556
2.608

•

•

L~J

~~~75

-----.

~.015

.048
.016
.02l

0--

·100 BSC

I 1

NOTE: All Dimensions are

~
Max

• Dimensions are in inches.

en >a:
::;;::;;
y ....
::;;

00

3-183

.;11

HARRIS
1 M Bit Asynchronous
CMOS Static RAM Module

June 1989

Features

Pinout
TOP VIEW

• Low Standby Current ............................................. 90011A
• Low Operating Supply Current ••••••••••••••••••••••••••••••••• 10/20mA
• Fast Address Access Time •••••••••••••••••••••••••••••••••••••••• 180ns
• Low Data Retention Supply Voltage •••••••••••••••••••••••••••••••••• 2.0V
• CMOSmL Compatible Inputs/Outputs
• Buffered Address and Control Lines
• 48 Pin DIP Pinout •••••••••••••••••••••••••••••••••••••••• 2.66 x 1.3 x 0.3"
• Operating Temperature Range ••••••••••••••••••••••••• ' -550 C to +125 0 C

EiA

Description
The HM-91 M2-8 is a fully buffered 1,048,572 bit CMOS RAM module consisting of
sixteen HM-65642 8K x 8 CMOS RAMs, two 82C82 CMOS octal buffers, and two
HCT-138 CMOS 3:8 decoders in leadless chip carriers mounled on a multi-layer,
co-fired, ceramic substrate. The HM-91 M2-8 CMOS RAM module Is organized as
two 64K x 8 RAM arrays sharing a common address bus and write enable input.
Separate data inpuVoulput buses allow the user to format1he HM-91 M2-8 as either
a 64K x 16 or 128K x 8 bit array.

DQI

DO>
DQn

, """

DO<

2

The on-substrate CMOS buffers and decoders on the HM-91 M2-8 reduce the
system package count and minimize the capacHive load on the system address and
control buses. In addition to this, the HM-91 M2-8 has on-substrate decoupling
capacitors mounted in leadless chip carriers to reduce power supply noise and
minimize the need for external decoupling while ensuring high reliability, even in
harsh environments.

2

PIN NAMES
PIN

DESCRIPTION
Address Input
. Data InpuVOutput
Output Enable
Chip Enable
Write Enable
No Connection
Module Select

A
DQ
GX
EXX

The HM-65642 RAMs used on the HM-91 M2-8 module are full CMOS devices,
utilizing arrays of six-transistor (6D memory cells for the most stable and lowest
possible standby and data retention supply current over full military operating temperature range. In addition to this, the high stability of the 6T cell provides excellent
protection against soft errors due to power supply noise and alpha particles. This
stability also improves the radiation tolerance of the module over that of RAMs
utilizing four transistor (4D Mix-MOS memory cells.

Vi

NC
S

Functional Diagram
Ii-----I
.. - - - - - - - 1

~--------~

--7:':"3--1
'

A11

A11

A1Z
A13

A1Z

HCT-13S

HCT-138

A13

E1A

ill

EZA

Fa

m

ill
DGO

DG,

DG8

DOtS

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1989

3-184

DOI5

v"" ____________..r'-GND

The HM-91 M2-8 is physically constructed as an extra wide 48 pin dual-in-line
package with standard 0.1" centers between pins to combine the high density of
CMOS and leadless chip carriers with the ease of use of DIP packaging.

AO-A10,A14.A15

0013

27 D014

OQ7

Specifications HM-91 M2-8
Absolute Maximum Ratings
Supply Voltage ........•.••••.•••.••••..•.•••••.•.•.•.•••..•.•..•.••• .'.••••......•..•.•••.•...•.•..•.••••••••••• +7.0V
Input, Output or I/O Voltage Applied .••.•..•.••.••.•...••......••............•.................... GND-0.3V to VCC +0.3V
Storage Temperature Range ••••••.••••...••••..........•...•••.••.••.••..•....•....••..•.•••••...•... -65 0C to +1500 C
Gate Count ••••.••••.••.••••.•...•..•..•...........•..•..••••.••.••••.•...•.••.••.••..••••••••.•..•...• 1619000 Gates
Junction Temperature .•......................••.•.•.•.••••.•••..•.••••.•.•••..•.••.••.•••••••••.•.••••••.••.•• +1750 C
Lead Temperature (Soldering, Ten Seconds) ......•.....•...••••••.••.••••.••.••.••.••.••.•••••••••.•.••••••••.... +3000 C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only rating
and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.

Operating Conditions
Operating Voltage Range •.•..•.•......•.•.....•...................................•.......•..........•.• +4.5V to +5.5V
Operating Temperature Range ..•.•••••••••.. ; ..•.••.•..•.....•••...•.......•.............•....•.•.•.• -550C to +1250 C

D.C. Electrical Specifications

vcc = 5V ± 10%; TA = -550C to +125 0 C
MIN

MAX

UNITS

Standby Supply Current (CMOS)

-

900

~A

10 = 0, E3 = S = 0.3V, VCC = 5.5V,
VIN = VCC or GND

ICCSB

Standby Supply Current (TTL)

-

2.0

mA

10=O,El =E2=VIH, E3=S=VIL,
VCC = 5.5V, VIN = VCC or GND

ICCEN

Enabled Supply Current

12BKxB
64Kx 16

-

5.0
10

mA
mA

10 = 0, El = E2 =VIL, E3 =VIH,S =VCC
-0.3V, VCC = 5.5V, VIN = VCC or GND

ICCOP

Operating Supply Current 12BKxB
{Note 2)
64Kx 16

-

10
20

mA
mA

10=0,1= lMHz,El =E2=VIL,S=VCC
E3 = VIH, VCC = 5.5V, VIN = VCC or GND

ICCDR

Data Retention Supply Current

-

750

~

E3 = S = 0.3V, VCC = 2.0V, VIN = VCC or GND

-1.0

+1.0

~

VIN = VCC or GND, VCC = 5.5V

Module Select Input Current

-5

+5

~

VIN = VCC or GND, VCe: = 5.5V

I/O Leakage Current

-5

+5

~

VIO = VCC or GND, VCC = 5.5V

Data Retention Supply Voltage

2.0

-

V

SYMBOL
ICCSBl

PARAMETER

Input Leakage Current (Except S)

II
liS
1I0Z
VCCDR

TEST CONDITIONS

VOL

Output Voltage Low

-

0.4

V

10L = 4.0mA, VCC = 4.5V

VOHl

Output Voltage High

2.4

-

V

10H = -l.OmA, VCC = 4.5V

VOH2

Output Voltage High (Note 3)

V

10H =

VCC-O.4

VIL

Input Voltage Low

-0.3

O.B

V

VIH

Input Voltage High

2.4

VCC+0.3

V.

~lOO~A, VCC

= 4.5V

Capacitance (Note 3)
SYMBOL
CI
CDa
CIS

PARAMETER

>en'"

00

MAX

UNITS

Input Capacitance (Except S)

25

pF

1= lMHz, VA=VCC orGND

TEST CONDITIONS

Data I/O Capacitance

150

pF

1= 1 MHz, VDa and VG = VCC or GND

Module Select Input Capacitance

150

.pF

1;:1 MHz, VEN = VCC or GND

NOTES:

1.

All devices tested at worst case temperature and supply voltage limits.

2.

Typical derating: 128K x 8: SmA/MHz increase in ICCOP; 64K x 16: 10mA/MHz.

3.

Guaranteed but not tested.

4.

Input pulse levels: 0 to 3.0V; Input rise and fall times: 10ns max; Input and output timing reference level: 1.5V; Output load: 1TTL gale equivalent
and CL = 100pF min including scope and jig - for CL greater than 100pF, access time is derated by 0.15ns/pF.

5.

Enable valid (EV) in a parameter is determined the last transition that resufts in the combination of E1 low, E2 low and E3 high. Enable invalid
'
(EX) in a parameter is determined by t~e first transition that results in any other combination than E1low, E2 low and E3 high.

3-185

.......::;:

::;:::;:

Specifications HM-91 M2-8,
A.C. Electrical Specifications
SYMBOL

PIN NO.

(Notes 1. 4)

VCC

= 5V ±10%;

TA

= -550C to +1250 C
MIN

PARAMETER

MAX

UNITS

TEST CONDITIONS

READ CYCLE.
(1)

TAVAX

IRC

Read Cycle Time

(2)

TAVQV

tAA

Address Access Time

(3)

TEVQV'

tCEl

200

-

Chip Enable Access Time

-

ns

200

ns

200

ns
ns

(4)

TSHQV

ICE2'

Module Select Access TIme

-

180

(5)

TGLQV

tOE

Output Enable Access Time

-

120

ns

(6)

TEVQX

tLZl

Chip Enable Output Enable TIme

30

-

ns

j7)

TSHQX

tLZ2

Module Select Output Enable Time

5

(8)

TGLQX

tOLZ

Output Enable TIme

5

(Note 5).

(Notes 3, 5) .

(9)

TAXQX

tOH

Address Output Hold .Time

30

-

ns

(Note":!)

(10)

TEXQZ

tHZl

Chip Disable Output Disable Time

0

85

ns

(Notes 3,5)

(11)

TSLQZ

tHZ2

Module Select Output Disable Time

0

60

ns

(Nole3)

(12)

TGHQZ

tOZ

Output Disable Time

0

70

ns

(Nole3)

ns

ns

(Note 3)

ns

(Note 3)

WRITE CYCLE'
(13)

TAVAX.

IWC

Write Cycle Time

200

(14)

TWLWH

'IWP

Write Pulse Widlh

100

-

(15)

TEVWH

ICW

Chip Enable to End of Write

WControlled

145

-

ns

(N!>te5)

(16)

TEVEX

tCW

Chip Enable 10 End of Write'

EControlied

120

-

ns

(Notes3,5)

(17)

TSHSL

tCW

Chip Enable to End of Write

SControlied

120· .

-

'ns

(Note 3)

(18)

TAVWL

lAS

Address Selup Time

WControlled

50

(19)

TAVEV

lAS

Address Setup Time

E Controlled.

20

~,

ns.

ns

-

ns

ns

(20)

TAVSH

lAS

Address Setup Time

SControlied

40

(21)

TWHAX

tWR

WrHe RecoveryTime

WControlied

10

(22)

TEXAX·

tWR

Write Recovery Time

EControlled

10

(23)

TSLAX

IWR

Write Recovery Time

SConlrolled

10

(24)

TDVWH

IDW

Data Setup TIme

WControlled

60

(25)

TDVEX

IDW

Data Setup Time

E Conlrolled'

55

-

(Notes3,5)

ns

(Note 3)

ns

;

ns

(Notes3,5)

ns

(Nole3)

ns

(Note3,5)'

(26)

TDVSL

tOW

Data Setup Time

SControlied

55

-

ns

(27)

TWHDX

tOH

Data Hold Time

WControlied

35.

ns

(28)

TEXDX

tDH

Data Hold Time

EControlied

35

(29)

TSLDX

IDH

Data Hold Time

SControlied

35

-

tWZ

WrHe Enable Output Di.sable Time

-

'95 .

ns'

(Nole3)

10

-

ns

. (Nole3)

(30)
(31)

TWLQZ
TWHQX

tOW

WrHe Disable Output Enable.TIme

(Note 3)

ns

(Notes3,5)

ns

(Nole3)

NOTES:
1.

All devices tested at worst case temperature and supply voltage limit••

2.

Typical derating: 12BK x B: 5mA/MHz increase In ICCOP; 64K x 16: 10mA/MHz.

3.

Guaranteed but not tested.

4.

Input pulse levels: 0 to 3.0V; Input risG and fall times: 10ns max; Input and output timing reference level: 1.5V; Output load: 1TTL gate equivalent
and CL - l00pF min including. scope a~d Jig - for CL greater than 100pF, access tima is derated by 9.15ns/pF.
.

5.

Enable valid (EV) in a parameter is determined the last transition that results in the combination of E1 low, E2 low and E3 high. Enable invalid
(EX) in a parameter is determined by the first transition that reauns in any other combination than E1 low. E2 low and E3 high.

3-186

-

Specifications HM-91 M2B-8
Absolute Maximum Ratings
Supply Voltage •..•.••....•..••••••••.••..••••••..•••••••••.......•....••...•.••.••.•.••.......•••••••....•••••• +7.0V
Input, Output or 1/0 Voltage Applied ••.••••.••.•...............•.•••..••..••..•••••.••.•••••.••.•• G ND-0.3V to VCC +0.3V
Storage Temperature Range •••••..•.••..••.••.•••.••••.••••....••..•..••.•••.••........••.•.•••••.... -65 0 C to +1500 C
Gate Count •.•.•...•....•.•••••.••..•..••..••..••••••.•.•.•...•..............••••.•.•••••••••..•••••••. 1619000 Gates
Junction Temperature •.•••...•...•..•.••....•••••.•••.••.••.•..••.••••.••...•.••.•..•..•••••.•.•.•.••••.•••••• +1750 C
Lead Temperature (Soldering, Ten Seconds) ........................•..............•..•........................... +3000 C
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage "to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.

Operating Conditions
Operating Voltage Range ..................••••.•..••••.••..•.•••..••..•..••.••.......•.•.•••••••.......• +4.5V to +5.5V
Operating Temperature Range ..•.••.....••••••.•..•.•.•.•..•.•...............•..............•..•••••• -55 0 C to +1250 C

D.C. Electrical Specifications

vcc = 5V ± 10%; TA = -550 C to +125 0 C

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

900

(JA

10 = 0, E3 = S = 0.3V, VCC = 5.5V,

2.0

rnA

10 =0, E1 = E2 =VIH, E3= S=VIL,
VCC = 5.5V, VIN=VCC orGND

5.0
10

rnA
rnA

10 =O,E1 = E2=VIL,E3=VIH,S=VCC
-0.3V, VCC = 5.5V, VIN = VCC or GND

ICCSS

Standby Supply Current (TTL)

-

ICCEN

Enabled Supply Current

-

ICCOP

Operating Supply Current 128Kx8
(Note 2)
64Kx 16

-

10
20

rnA
rnA

10=0,1= 1MHz,E1 =E2=VIL,S=VCC
E3 = VIH, VCC = 5.5V, VIN = VCC or GND

ICCDR

Data Retention Supply Current

-

750

(JA

E3 = S = 0.3V, VCC = 2.0V

-1.0

+1.0

(JA

VIN = VCC or GND, VCC = 5.5V

-5

+5

(JA

VIN = VCC or GND, VCC = 5.5V

I/O Leakage Current

-5

+5

(JA

VIO = VCC or GND, VCC = 5.5V

Data Retention Supply Voltage

2.0

-

V

ICCSS1

II

Standby Supply Current (CMOS)

128Kx8
64Kx 16

Input Leakage Current (Except S)
Module Select Input Current

liS
1I0Z
VCCDR
VOL

Output Voltage Low

-

0.4

V

10L = 4.0mA, VCC = 4.5V

VOH1

Output Voltage High

2.4

V

10H = -1.0mA, VCC = 4.5V

V

10H = -100(JA, VCC = 4.5V

VCC-O.4

-

VIL

Input Voltage Low

-0.3

0.8

V

VIH

Input Voltage High

2.4

VCC+0.3

V

VOH2

Output Voltage High (Note 3)

Capacitance (Note 3)
SYMBOL
CI
COO
CIS

MAX

UNITS

Input Capacitance (Except S)

PARAMETER

25

pF

1= 1MHz, VA=VCCorGND

TEST CONDITIONS

Data I/O Capacitance

150

pF

1= 1 MHz, VDO and VG = VCC or GND

Module Select Input Capacitance

150

pF

1=1 MHz, VEN = VCC or GND

NOTES:
1. All devices tested at worst case temperature and supply voltage limits.

2. Typical derating: 128K x 8: SmA/MHz increase in ICCOP; 64K x 16: 10mAlMHz.
3.

Guaranteed but not tasted.

4.

Input pulse lavels: 0 to 3.0V; Input rise and fall times: 10n8 max; Input and output timing reference level: 1.5V; Output load: 1TTL gate equivalent
and CL = 100pF min including scope and jig - for CL greater than 100pF, access time is derated by O.15ns/pF.

5.

Enable valid (EV) in a parameter Is determined the lasllransitlon that results in the combination of E1low, E2 low and E3 high. Enable invalid
(EX) in a parameter Is determined by the first transition that results in any other combination than E1 low, E2 low and E3 high.

3-187

>-

enD:
C> C>

::;:::;:

U W

::;:

Specifications HM-91 M2B-8
D.C. Electrical Specifications
PIN NO.

SYMBOL

(Notes 1,4)

VCC ~ 5V ±10%;

TA ~ -55 0 C to +125 0 C

PARAMETER

MIN

MAX

UNITS

180

-

ns

-

180

ns

180

ns

160

ns

120

ns
ns

(Notes 3, 5)

ns

(Note 3)

ns

(Note 3)

30

-

ns

(Note 3)
(Notes3,5)

TEST CONDITIONS

READ CYCLE
(1)

TAVAX

tRC

Read Cycle Time

(2)

TAVQV

tAA

Address Access Time

(3)

TEVQV

tCE1

Chip Enable Access Time

(4)

TSHQV

tCE2

Module Select Access Time

(5)

TGLQV

tOE

Output Enable Access Time

(6)

TEVQX

tLZ1

Chip Enable Output Enable Time

(7)

TSHQX

tLZ2

Module Select Output Enable Time

5

(8)

TGLQX

tOLZ

Output Enable Time

5

(9)

TAXQX

tOH

Address Output Hold Time

(10)

TEXQZ

tHZ1

Chip Disable Output Disable Time

0

75

ns

(11)

TSLQZ

tHZ2

Module Select Output Disable Time

0

50

ns

(Note 3)

(12)

TGHQZ

tOZ

Output Disable Time

0

60

ns

(Note 3)

ns

25

(Note 5)

WRITE CYCLE
(13)

TAVAX

tWC

Write Cycle Time

180

(14)

TWLWH

tWP

Write Pulse Width

100

(15)

TEVWH

tCW

Chip Enable to End of Write

WControlled

140

(16)

TEVEX

tCW

Chip Enable to End of Write

E Controlled

120

(17)

TSHSL

tCW

Chip Enable to End of Write

S Controlled

120

-

(18)

TAVWL

lAS

Address Setup Time

WControlled

40

-

ns

ns
ns

(Note 5)

ns

(Notes 3, 5)

ns

(Note 3)

(19)

TAVEV

lAS

Address Setup Time

E Controlled

0

-

ns

(Notes 3,5)

(20)

TAVSH

lAS

Address Setup Time

S Controlled

40

-

ns

(Note 3)

(21)

TWHAX

tWR

Write RecoveryTime

WControlled

10

-

ns

(22)

TEXAX

tWR

Write Recovery Time

EControlled

10

-

ns

(Notes 3, 5)

(23)

TSLAX

tWR

Write Recovery Time

S Controlled

10

-

ns

(Note 3)

(24)

TDVWH

tDW

Data Setup Time

W Controlled

60

-

ns

(25)

TDVEX

tDW

Data Setup Time

E Controlled

55

-

ns

(Note 3,5)

(26)

TDVSL

tDW

Data Setup Time

S Controlled

55

ns

(Note 3)

(27)

TWHDX

tDH

Data Hold Time

WControlled

35

(28)

TEXDX

tDH

Data Hold Time

EControlled

35

(29)

TSLDX

tDH

Data Hold Time

S Controlled

35

-

(30)

TWLQZ

tWZ

Write Enabl,e Output Disable Time

-

(31)

TWHQX

tOW

Write Disable Output Enable Time

10

ns
ns

(Notes 3, 5)

ns

(Note 3)

95

ns

(Note 3)

-

ns

(Note 3)

NOTES:
1.

All devices tested at worst case temperature and supply voltage limits.

2.

Typical derating: 128K x 8: SmA/MHz increase in ICCOP; 64K x 16: lOmA/MHz.

3.

Guaranteed but nol tested.

4.

Input pulse levels: 0 to 3.0V; Input rise and fall Urnes: 10ns max; Input and output timing reference level: 1.SV; Output load: 1"TTl gate equivalent
and Cl = 100pF min including scope and jig - for CL greater than 100pF, access time is derated by O.15ns/pF.

5.

Enable valid (EV) in a parameter is determined the last transition that results in the combination of
low,
low and E3 high. Enable invalid
(EX) in a parameter is determined by the first transition that results in any other combination than E1 low. E2 low and E3 high.

E1

3-188

E2

HM-91M2-8
Timing Diagrams
READ CYCLE 1: ADDRESS CONTROLLED

READ CYCLE 2: E, S, or G CONTROLLED

(NOTES 1, 2)

(NOTE 1)

III

~-------------------------TAVAX------------------------~

A

~~----------------------------~--------------------------------~~

E3

>-

",0:
00

:E:E
..,w
:E

READ CYCLE NOTES:

1.

jn a read cycle, Vi is held high.

2.

In read cycle 1. the module is kept continuously enabled:
El, E2 and G are held low; E3 and S are held high.

3-189

HM-91M2-8
Timing Diagrams
WRITE CYCLE 1:

Vi CONTROLLED

(NOTE 1)

,,3,
~------------------TAVAX----------------~~

A~~====~=="mm
TAVWL ---r-------·TW'

~~l___~"I~'____!_--------~':"'~--------~--~~~~~~~~~~~

fi.n~

WRITE CYCLE 2: E1, E2, or E3 CONTROLLED (NOTE 2)

113,

~------------------TAVAX------------------~

--+--------- TEVEX -------1-_-

fi.n

--------.::::..--"""'1

''''

,------------------------

E3 ____________~

wRL________L-~. . .

3-190

HM-91M2-8
Timing Diagrams
WRITE CYCLE 3: S CONTROLLED

(NOTE 3)

1131

~--------------------TAVAX--------------

____~

Amc========~=ammm
1111

12~

Ei,E2

~~-------r---------------+--~

El

wBL________~. . . .~
.r- TDVSL ---1--D~I"I

WRITE CYCLE NOTES:
1.

In Write Cycle 1, the module is first enabled, and than data is strobed into the RAM with a pulse on W.1f G is held high for the entire cycle,
the outputs will remain in the high impedance state. IIGis held low, it may be necessary to lengthen the cycle to prevent bus contention.
This would occur WTWLQZ and TOVWH overlapped.

2.

In Write Cycle 2, Address (A) and Write Enable (W) are first set up and then data is strobed into the RAM with a pulse on E.

3.

In Write Cycle 3, Addresses (A), Write Enable (W) and Iho Chip Enablo inpuls
Iho RAM with Ihe Module Selecl (S) input.

iEi, E2 and E3) aro firsl sol up and data is then slrobed inlo

TRUTH TABLE
INPUTS
S

E1A

E2A E3A E18

GND

X

X

GND

VIL

X

X

X

X

VIH

X

X

X

X

VIH

X

X

X
X

MODE

E28

E38

GA

G8

W

X

X

GND

X

X

X

Standby (CMOS) Sides A and B

X

X

X

X

X

X

Standby (TTL) Sides A and B

X

X

X

X

X

X

Standby (TTL) Side A

X

X

X

X

X

X

X

Standby (TTL) Side A

X

VIL

X

X

X

X

X

X

Standby (TTL) Side A

X

X

X

VIH

X

X

1<

X

X

Standby (TTL) Side B

X

X

X

X

V1H

X

X

X

X

Standby (TIL) Side B

X

X

X

X

X

X

VIL

X

X

X

VIH

VIL

VIL

VIH

X

X

X

VIH

X

VIH

Standby (TTL) Side B
Side A Enabled, Outputs High Impedance

VIH

X

X

X

V1L

VIL

VIH

X

VIH

VIH

Side B Enabled, Outputs High Impedance

VIH

V1L

VIL

VIH

X

X

X

V1L

X

VIH

ReadSideA

VIH

X

X

X

VIL

VIL

VIH

X

VIL

VIH

Read Side B

VIH

V1L

VIL

VIH

X

X·

X

X

X

VIL

Write Side A

VIH

X

X

X

VIL

VIL

VIH

X

X

VIL

WriteSideB

NOTE:
Side A refers to the half of the module that connects to 000 through 007 and side B refers to the half of the module that
connects to CaB through 0015. When the module is configured as a 64K x 16 array, side A and side B may be enabled either
simultaneously or separately. When the array is configured as a 128K x 8 array, side A and B should not be enabled
Simultaneously, as bus contention could result

3-191

HM-91M2-8
Organizational Guide
FOR 128K X 8 CONFIGURATION
CONNECT:

PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN

16 (000) to PIN 33 (008)
17 (001) to PIN 32 (009)
18 (002) to PIN 31 (0010)
19 (003) to PIN 30 (0011)
20 (004) to PIN 29 (0012)
21 (~OS) to PIN 28 (0013)
22 (006) to PIN 27 (0014)
23 (007) to PIN 26 (0015)

FOR 64K X 16 CONFIGURATION
CONNECT:

PIN
PIN
PIN
PIN

9 (El A) to PIN 40 (El B)
10 (E2A) to PIN 39 (E2B)
11 (E3A) to PIN 38 (E3B)
13 (GA) to PIN 36 (GB)

Concerns for Proper Operation of Chip Enables:

Printed Circuit Board 'Mounting:

The transition between blocks of RAM requires a change in
the chip enable being used. When operating in·the·64K x 16
mode use the chip enables as if there were only three.,
El thru E3. In the 128K x 8 mode all chip enables must be
treated separately. Transitions between chip enables must
be treated with the same constraints that apply to anyone
chip enable. More than one (internal) chip enable low
simultaneously. for devices whose outputs are tied together
either internally or externally. is an illegal input condition
and must be avoided.

The leadless chip carrieF packages used in the HM-91M2
have conductive. lids. These lids are electrically connected
to. GNO:rhe system designer should .be aware that the
carriers on the bottom side could short conductors below if
pressed completely. down against the surface of the circuit
board. The pins on the package are designed with a
standoff feature to help prevent the leadless carriers from
touching the circuit board surface..

Low Voltage Data Retention
Harris CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are
guaranteed over. temperature. The following rules insure
data retention:

2.

During power-up and power-down transitions. S must
be held between .-0.3V and 10% of VCC.

3.

The RAM 'module can begin operation one TAVAX after
VCC reaches the minimum operating voltage (4.5V).

1. The module must be kept. disabled during data··
retention. The Chip Enable (E3A and E3B) and module
select (S) must be between -0.3V and +0.3V..

~

-{
(VI

5.5
4.5

DATA RETENTION MDDE-

J

/

1\

2.0
0.0

-TA'VAX-

u,{
(VI

5.5
4.5

2.0
0.0

I

\.

\

/

V

\

3-192

HM-91M2-8
Packaging
HM-91 M2-8 48 PIN MODULE

I'

2.556
2.608

,

I

DDDD[QJDTr
D
D

LmU!!§.

DDDD~DIIT
~

Inii~175
~O

~.015
.060

-=-

T

I

---.

-,-I----r-

1-.;=2>f,~~j18:1:
<--

.048
.016.023

Il

·lo08se

NOTE: All Dimensions are

~
Max

,Dimensions are in inches.

3-193

m

HARRIS

HM-6642/883
512

June 1989

• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.
• Low Power Standby and Operating Power
ICCSS ••••••••••••.••••••.••••...•.••.••••..•••••.•••• 100flA

~

•
•
•
•
•
•

8 CMOS PROM

Pinouts

'Features

~

X

ICCOP .•••••••••••.•••••••••••.••••••.•••••.••• 20mAat 1MHz
FastAccessTime ••••.....•••...•••••••••.••••..•••••• 1201200ns
Wide Operating Temperature Range ••.••.••••• -55 0 C to +125 0 C
Industry Standard Pinout
• Synchronous Operation
Single 5.0 Volt Supply
• On-Chip Address Latches
• Separate Output Enable
CMOS/TTL Compatible Inputs
Field Programmable

Description
The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link Programmable
Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous
circuit design techniques combine with CMOS processing to give this
device high speed performance with very low power dissipation.

HM1-6642/883 (CERAMIC DIP)
TOP VIEW
A7

VCC

AS

AS

AS

61

A4

62

A3

63

A2

E

A1

P

AD

07

ao

OS

01

OS

02

04

On-chip address latches are provided, allowing easy interfacing with
recent generation microprocessors that use multiplexed addresss/data
bus structures, such as the 8085. The output enable controls, both
active low and active high, further simplify microprocessor system
interfacing by allowing output data bus control independent of the chip
enable control. The data output latches allow the use of the HM-6642/883
in high speed pipelined architecture systems, and also in synchronous
logic replacement functions.

6ND

03

Applications for the HM-6642/883 CMOS PROM include low power
handheld microprocessor based instrumentation and comunications
systems, remote data acquisition and processing systems, processor
control store, and synchronous logic replacement.

A4

S'
.01

.25
G2
L.

A3

f24
63
L_

All bits are manufactured storing a logical "0" and can be selectively
programmed for a logical "1" at any bit location.

AO

61
71
-,
_.
8'
-,

LATCHED

ADDRESS
REGISTER

_.. L~.J t~J tZ,J

A2
AI
NC

ao

Functional Diagram
AS
A7
A.
A.
M
A3

HM4-6642/883 (CERAMIC LCC)
TOP VIEW

l2J L~~ t~.J t~~ r-

_.
_.

.-

f23

_.

NC

19

07
06

.. ...

ALL LINES POSITIVE lOGIC - ACTIVE HGH

'tiREE STATE OUFFERS:
A HIGH _

OUTPUT ACTIVE

LHIGH_ Q= D
Q LATCHES ON R1SlHG EDGE Of E
ADDRESS LATCHES AND GATED DECODERS;
LATCH ON FALUNG EDGE Of E
GATE ON fAWNG EDGE OF
P SHOULD BE HARDWIRED TO GND EXCEPT
DURING PROGRAMMING

A2
A1
Nl

E

E

iii
G2
G3

PIN

DESCRIPTION

NC

No Connect

AO-AS

Address Inpuls

E

Chip Enable

0

Data Output

VCC

Power (+5V)

13

Output Enable

p.

Program Enable

* P Should be Hardwired to GND
Except During Programming.

Copyright

© Harris Corporation 1989

3-194

P

9'

MATRIX

DATA LATCHES:

E

Specifications HM-6642/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••••...•.•..•.....•••.....•.••••......•• +7.0V
Input, Output or 1/0 Voltage Applied.; •.. GND -0.3V to VCC +0.3V
Storage Temperature Range .•••.•..•••••.••• -650C to +150 0C
Junction Temperature •...•••.••••••••••.••.••..••.••. +1750C
Lead Temperature (Soldering 10 sec) ....•.••.•...•••••. +3000 C
ESD Classification •.•..•••.......•••.••.•...•.••...... Class 1
Typical Derating Factor •••........• 5mNMHz Increase in ICCOP

Thermal Resistance
eja
Ceramic DIP Package.. . •. .. . ••••. .
52 0 C/W
Ceramic LCC Package. • . • • • • • . • . • .
5BoC/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ••.•..•.••••...•.•.••••....•...• 0.96W
Ceramic LCC Package •.•.......•..•.•......•••.••••• 0.B6W
Gate Count ••....•.••.••.........•............•.. 16BO Gates

CAUTION: Stresses above those listed in ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range .••.•••.•••.•.. -550C to +1250 C
Operating Supply Voltage ••......•••.......•••.•....... ±4.5V

Input Low Voltage VIL ...••.•••.•...••.•.••.•..• -0.3V to +O.BV
Input High Voltage VIH •.••.......•.•....... +2.4 to VCC +0.3V

TABLE 1. HM-6642/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISnCS
Device Guaranteed and 100% Tested
LIMITS

SYMBOL

(NOTES 1,4)
CONDITIONS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

High Level Output
Voltage

VOH

VCC = 4.5V, 10 = -1.0mA

1,2,3

-55°C ::;TA~ +125 0C

2.4

-

V

Low Level Output
Voltage

VOL

VCC = 4.5V, 10 = +3.2mA

1,2,3

-55°C::; TA::; +125 0C

-

0.4

V

High Impedance Output
Leakage Current

IIOZ

VCC = 5.5V, G = 5.5V,
VI/O = GND or VCC

1,2,3

-550C ::;TA::; +125 0C

-1.0

1.0

flA

VCC = 5.5V, VI = GND or
VCC, P Not Tested

1,2,3

-550C ::;TA::;+1250C

-1.0

1.0

flA

D.C. PARAMETERS

Input Leakage Current

II

Standby Supply
Current

ICCSB

VI = VCC or GND
VCC = 5.5V, 10 = OmA

1,2,3

-550C ::;TA::; +125 0C

-

100

flA

Operating Supply
Current

ICCOP

VCC = 5.5V, G = GND,
G = VCC, (Note 3),
f= lMHz, 10 =OmA,
VI = VCC or GND

1,2,3

-55°C ~TA::; +1250C

-

20

mA

FT

VCC = 4.5V (Note 10)

7, BA,B8

-55°C ::;TA::; +125 0C

-

-

Functional Test

TABLE 2. HM-6642/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

A.C. PARAMETERS

SYMBOL

(NOTES 1,2,4)
CONDITIONS

GROUP A
SUBGROUPS

TEMPERATURE

LIMITS
MAX
MIN

UNITS

AddressAccess Time

TAVQV

VCC = 4.5V and 5.5V

9,10,11

-550C STA:> +1250 C

-

220

ns

Output Enable Access
Time

TGVQV

VCC = 4.5V and 5.5V

9,10,11

-550C ::;TA::; +125 0 C

-

150

ns

Chip Enable Access
Time

TELQV

VCC = 4.5V and 5.5V

9,10,11

-550C STA::; +1250 C

-

200

ns

Address Setup Time

TAVEL

VCC = 4.5V and 5.5V

9,10,11

-55°C ::;TA~ +1250 C

20

ns

Address Hold Time

TELAX

VCC = 4.5V and 5.5V

9,10,11

-550C.:s.TA::;+1250C

60

Chip Enable Low Width

TELEH

VCC = 4.5V and 5.5V

9,10,11

-550C ::;TA::; +125 0C

200

Chip Enable High Width

TEHEL

VCC = 4.5V and 5.5V

9,10,11

-550 C::;;TA::;+1250C

150

-

Read Cycle Time

TELEL

VCC = 4.5V and 5.5V

9,10,11

-550C::;TA~+1250C

350

-

NOTES:
1. All voltages referenced to VSS.

3. Typical derating

2. A.C. measurements assume transition time S 5n8; input levels = O.OV to
3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent load
and CL 5! 50pF.

4. All tests performed with P hardwired to GND.

= SmA/MHz

CAUTION:These deviCes are sensitive to electronic discharge. Proper IC handling procedures should be followed.

3-195

increase in ICCOP.

ns
ns
ns
ns

>"'c::
cc
::;:::;:
uw
::;:

Specifications HM-6642/883
TABLE 3. HM-6642/883 A.C. AND D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETERS

SYMBOL

Input Capacitance

CIN

cve

VO Capacitance

(NCrrE4)
CONDITIONS

LIMITS
MIN
MAX

NOTES

TEMPERATURE

VCC = Open, f = 1MHz
All Measurements Reference
Device Ground

5,7

TA=+250C

-

10

pF

VCC = Open, f = 1 MHz
All Measurements Reference
Device Ground

5,8

TA=+250 C

12

pF

5,9

TA=+250 C

5

pF

VCC = Open, f = 1MHz
All Measurements Reference
Device Ground

5,7

TA=+250 C

-

12

pF

VCC = Open, f = 1MHz
All Measurements Reference
Device Ground

5,8

TA=+250C

-

14

pF

UNITS

5,9

TA=+250C

8

pF

Output Enable Time

TGVQX

VCC = 4.5V and 5.5V

5

-550C :STA:S+125OC

5

150

ns

Output Disable Time

TGXQZ

VCC = 4.5V and 5.5V

5

-550C~TA~+1250C

-

150

ns

NOTES:
5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These
parameters are characterized upon Inllal de.lgn changes which would affect the.e characteristics.
B. Tested as follows: f = 2MHz, VIH = 2.4V, VlL = 0.4V,IOH - -4.0mA, VOH

:!: I.5V, and VOL.!: 1.5V.

7. Applies 10 .600 Inch Caramlc Dual-In-Llne (DIP) davlce types only.
8. Applies to .300 Inch Caramic Dual-In-Llne (DIP) davice types only.
9. Applies 10 Ceramic Leadles. Chip Carrier (LCC) device types only.
10. Tasted as follows: f - lMHz, VIH - 2.4V, VlL = 0.8V,IOH = -lmA, IOL - +lmA, VOH:: l.5V, VOL.!: 1.5V.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

InHiaiTest

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3,7, 8A, 8B, 10, 11

Group A

Samples/5005

1,2,3,7, 8A, 8B, 9,10,11

GroupsC&D

Samples/5005

1,7,9

3-196

Specifications HM-6642B/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••••.•••••••••••••••••••••.•••• +7.0V
Input, Output or I/O Voltage Applied ••••• GND -O.3V to VCC +0.3V
Storage Temperature Range ••••.•••••••••.•• -650C to +1500 C
Lead Temperature (Soldering 10 sec) ••••••••••.•••••••• +300 0 C
Junction Temperature •••••••••••••••.•••••••••••••.•• +175 0 C
ESD Classification ••••••••••••••••••••••••••••••••.••• Class 1
Typical Derating Factor •••••••••.•• 5mNMHz Increase in ICCOP

Thermal Resistance
eja
Ceramic DIP Package. • • • • • • • • • • • • •
52 0 C/W
Ceramic LCC Package. • • • • • • . • • • • •
580 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ••••••••••..••...•••• " ••••.••.• 0.96W
Ceramic LCC Package ••••••••••••••••••••••••••••••• 0.86W
Gate Count •••.•...•••••••••••..••••••••••••••••• 1680 Gates

CAUTION: Stresses above those listed in ''Absolute Maximum Ratings"may cause permanent damage to the device. This isa stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range ••••••••••••••• -550C to +1250 C
Operating Supply Voltage •••••••••••••••••.•••••••••••• ±4.5V

Input Low Voltage V1L •• • • • • • • • . . • • • • • • • • • • • • • •• -0.3V to +0.8V
Input High Voltage VIH ••••..•••••••••••.•.. +2.4 to VCC +0.3V

TABLE 1. HM-6642B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTfCS
Device Guaranteed and 100% Tested

D.C. PARAMETERS

SYMBOL

(NOTES 1,4)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

2.4

-

V

High Level Output
Voltage

VOH

VCC = 4.5V,10 = -1.0mA

1,2,3

-550 C:::;TA:::;+1250C

Low Level Output
Voltage

VOL

VCC = 4.5V, 10 = +3.2mA

1,2,3

-550 C.:::;TA:::;+1250C

-

0.4

V

High Impedance Output
Leakage Current

1I0Z

VCC = 5.5V, G = 5.5V,
VI/O = GNDorVCC

1,2,3

-550C ~TA~ +1250 C

-1.0

1.0

pA

VCC = 5.5V, VI = GND or
VCC, P NotTested

1,2,3

-550C ~TA~+1250C

-1.0

1.0

pA

Input Leakage Current

II

>-

Standby Supply
Current

ICCSB

VI = VCC or GND
VCC = 5.5V, 10 = OmA

1,2,3

-550C ~TA'::: +1250 C

-

100

pA

Operating Supply
Current

ICCOP

VCC = 5.5V, G = GND,
G = VCC, (Note 3),
1= 1 MHz, 10 = OmA,
V/=VCCorGND

1,2,3

-550CS.TA.:::+1250C

-

20

rnA

FT

VCC = 4.5V (Note 10)

7,8A,BB

-550C~TA~+1250C

-

-

Functional Test

TABLE 2. HM-6642B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
(NOTES 1,2,4)
A.C. PARAMETERS

SYMBOL

CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

140

ns

50

ns

Address Access Time

TAVQV

VCC = 4.5V and 5.5V

9,10,11

-550CS.TA~+1250C

Output Enable Access
lime

TGVQV

VCC = 4.5V and 5.5V

9,10,11

-55°C S. TA ~ +1250 C

-

Chip Enable Access
lime

TELQV

VCC = 4.5V and 5.5V

9,10,11

-550C~TA~+1250C

-

120

ns

Address Setup lime

TAVEL

VCC = 4.5V and 5.5V

9,10,11

-550 C.:::;TA:S +1250 C

20

Address Hold Time

TELAX

VCC = 4.5V and 5.5V

9,10,11

-55°C .::::TA':::: +1250 C

25

-

ns
ns

ns

Chip Enable Low Width

TELEH

VCC = 4.5V and 5.5V

9,10,11

-550C'::::TA~+1250C

120

-

Chip Enable High Width

TEHEL

VCC = 4.5V and 5.5V

9,10,11

-550C~TA~+1250C

40

-

ns

Read Cycle Time

TELEL

VCC = 4.5V and 5.5V

9,10,11

-55°C :STA~ +1250 C

160

-

ns

NOTES:

Iceop.

1. All voltages referenced to VSS.

3. Typical derating = 5mNMHz increase in

2. A.C. measurements assume transition time S 50S; inpullevels = O.OV to
3.0V; timing reference levels = 1.5Vj output load =- 1TTL equivalent load

4. All tests performed with P hardwired to GNO.

and CL 51 50pF.
CAUTION:These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

3-197

.,,0:
00

UW
====
==

Specifications HM-6642B/883
TABLE 3. HM-6642B/883 A.C. AND D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETERS

(NOTE 4)
CONDITIONS

Input Capacitance

elN

I/O Capacitance

CliO

LIMITS
MAX
MIN

NOTES

TEMPERATURE

vee = Open, f = 1 MHz
All Measurements Reference
Device Ground

5,7

TA=+250 e

-

10

pF

vee = Open, f= 1MHz
All Measurements Reference
Device Ground

5,.8

TA=+2S0 e

-

12

pF

SYMBOL

UNITS

5,9

TA=+2so e

-

S

pF

vee = Open, f = 1 MHz
All Measurements Reference
Device Ground

5,7

TA=+2S0 e

-

12

pF

vee = Open, f = 1 MHz
All Measurements Reference
Device Ground

S,8

TA=+2S0 e

14

pF

5,9

TA=+2S0 e

-

8

pF

Output Enable Time

TGVQX

vee = 4.SV and 5.SV

5

-ssoe :>.TA':> +125OC

5

SO

ns

Output Disable Time

TGXQZ

vee = 4.SV and 5.5V

S

-550 C :>.TA:>.+12S0 e

-

SO

ns

NOTES:

5. The parameters listed In Tabla 3 are controlled via design or process parameters and are not directly tested. These
parameters are characterized upon InRiaI design changes which would affect these characteristics.
6. Tested as follows: f

= 2MHz. VIH = 2.4V. VIL = 0.4V. IOH = -4.0mA. VOH ~ 1.5V. and VOL ~ 1.5V.

7. Applies to .600 Inch Ceramic Dual-In-Line (DIP) device types only.
a. Applies to .300 Inch Ceramic Dual-In-line (DIP) device types only.

9. Applies 10 Ceramic Leadle.s Chip Carrier (LCC) device Iypes only.
10. Tesled as follows: f - lMHz. VIH = 2.4V. VIL

= 0.8V.IOH = -lmA.IOL =

+lmA. VOH

~

1.5V. VOL ~ 1.5V.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3,7, 8A, 8B, 10, 11

Group A

Samples/5005

1,2,3,7,8A,8B,9,10,11

Groupse&D

Samples/SOO5

1,7,9

3-198

HM-6642/883
Switching Waveform
READ CYCLE

REFER:~~~------------tr-~t--------r-----+-----~-------4t4t4f------1

0

456

>",a::
• G Has the same timing as

00

...::;:::;:::;:'"

G except signal is inverted.

Test Load Circuit

1-------------,
1

1

1

1

om~+-~I•

1
1

1

1
1

1
·TEST HEAD
CAPACrTANCE

1_ _ _

1

~QUIVAlENT~RCU~ _ _ _ J

3-199

HM-6642/883

Burn-In Circuits

HM-6642/883 (.300 INCH) CERAMIC DIP
vee
F80--JV>,""'-I
F70--JV>,II,--I

I-""IIIV---o
I-""IIIV---O

F6 o--JW"v--I

F5 o--'Wor-i-il
F4 o--JW"v--I
F3

FlO
F11

!c'I---"M--O FI2

O--JW"v--I

1"'If-JV>,II,--oO Fa

I--""IIIV---o

F2 o--JW"v--I

GND

FI O--"'W"v--I

I--""IIIV-+--o vee /2

vee /2 o-+-JW"v--I

HM-6642/883 (.600 INCH) CERAMIC DIP

FlO --WI<--I

F9 - - ' l M - i

!-'WIr--F9

--WI<--I
F7 - - ' l M - i
F6 - - ' l M - j

!--'Vl>!V--- FlO

F8

l2"I-""IIIV--- F11
12O:I-""IIIV--- FI2

F5 --WI<--I

!--'Vl>!V---Fa

F4 - - W ' - - I

!--'Vl>!V--- GND

F3

--WI<--I
1--'Vl>!V-.....- vee /2

vee /2 -1I--WI<--I

HM-6642/883 CERAMIC LCC

0

r0

z

FS

~]

F4

~]

F3

~J

l~J t~J

tE..: t1J L~13 t~..: L~~

-

F12

F2 -A./VV-

_.
81

Fl

~J

[~1 NC

-,
-,

Fa

~~
rig

[~- "" '" ';' "'., '".:J

vCC

1.51<

FO = 100kHz ±10%

F11

[~4
[~3
[~2

~,~
1'1]

NOTES:

[~5

820

1.51<

820

I.SK

820

1.5K

820

Unless Otherwise Noted

1.5K

820

vee = S.SV ± 0.5V

1.5K

820

VIH = -4.5V ± 10%

1.5K

820

1.5K

820

Rl

R2

All Resistors = 47kO

VIL = -0.2V to O.4V

e=

0.01 ~F

Min

3-200

HM-6642/883

Metallization Topology
DIE DIMENSIONS:
136 x 168 x 19 ±1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11 kA to 15kA
GLASSIVATION:
Type: Si02
Thickness: 8kA ± 1 kA
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy
Temperature: Ceramic DIP - 460 0 C (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
1.7 x 10 5 A/cm 2

Metallization Mask Layout
HM-6642/883

>",a:
00

::;:::;:
::;:

<..)w

3-201

HM-6642/883
Packaging t
24 PIN (.300) CERAMIC DIP

,""

r=~=t
'L Jt! !

""~
~

.125

~

I.,;,.,.

k::::!..-.098 MAX

~~~

.016--..J

"3

.050·
.. INCREASE MAX UloIll BY .003 INOiES
MEASURED AT CENTtR Of Fl.AT FOR •

.065

SOLDER FINISH

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 100 C
Method: Furnace Seal
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-9

24 PIN (.600) CERAMIC DIP

,.
15"

.. INCREASE MAX Ut.4lT BY .003 INCHES
U("SURED AT CENTER OF' FUT FOR
SOLDER FINISH

LEAD MATERIAL: we B
. LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
Method: Furnace Seal
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-3

28 PAD CERAMIC LCC
PAD MATERIAL: Type C
PAD FINISH: Type A
PAD DIMINISION: Type A
PACKAGE MATERIAL: Ceramic AI203 90%
PACKAGE SEAL:
Material: Goldmn
Temperature: 3200 C ±lOoC
Method: Furnace Braze
INTERNAL LEAD WIRE:
. Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic Wedge
COMPLIANT OUTLlN!;: 38510 C-4

NOTE: All Dimensions are

~

tMiI-M-3B510 Compliant Materials, Finishes, and Dimensions.

• Dimensions are In inches.

3-202

m

HM-6642

HARRIS

DESIGN INFORMATION
512 x 8 CMOS PROM
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Programming
Introduction
The HM-6642 is a 512 word by a-bit field Programmable
Read Only Memory utilizing nicrome fusible links as programmable memory elements. Selected memory locations
are permanently changed from their manufactured state, of
all low (VOL) to a logical high (VOH), by the controlled
application of programming potentials and pulses. Careful
adherence to the following programming specifications will
result in high programming yield. Both high vee (6.0V) and
low vee (4.0V) verify cycles are specified to assure the
integrity of the programmed fuse. This programming
specification, although complete, does not preclude rapid
programming. The worst case programming time required
is 37.4 seconds, and typical programming time can be
approximately 4 seconds per device.

6. The data outputs are enabled, and read, to verify that the
bit was successfully programmed.

The chip (E) and output enable (G) are used during the
programming procedure. On PROMs which have more than
one output enable control G3 is to be used. The other output
enables must be held in the active, or enabled, state
throughout the entire programming sequence. The
programmer designer is advised that all pins of the
programmer's socket should be at ground potential when
the PROM is inserted into the socket vee must be applied
to the PROM before any input or output pin is allowed
to rise*.

1. The power supply for the device to be programmed must
be able to be set to three voltages: 4.0V, 6.0V, 12.5V.
This supply must be able to supply 500mA average, and
1A dynamic, currents to the PROM during programming.
The power supply rise fall times when switching between
voltages must be no quicker than 1 lis.

Overall Programming Procedure
1. The address of the first bit to be programmed is
presented, and latched by the chip enable (E) falling
edge. The output is disabled by taking the output
enable G Low: The programming pin is enabled by
taking (P) high.
2. vee is raised to the programming voltage level, 12.5\1.
3. All data output pins are pulled up to vee program. Then
the data output pin corresponding to the bit to be
programmed is pulled low for lOOIlS. Only one bit should
be programmed at a time.
4. The data output pin is returned to VCC, and the VCC pin
is returned to 6.0V.
5. The address of the bit is again presented, and latched by
a second chip enable falling edge.

a). If verified, the next bit to be programmed is
addressed and programmed.
b). If not verified, the programs verify sequence is
repeated up to a times total.
7. After all bits to be programmed have been verified at
6.0V, the vee is lowered to 4.0V and all bits are verified.
a). If all bits verify, the device is properly programmed.
b). If any bit fails to verify, the device is rejected.
Programming System Requirements

2. The address drivers must be able to supply a VIH of 4.0V
and 6.0V and VIL when the system is at programming
voltages.*
3. The control input buffers must be able to maintain input
voltage levels of ~ 70% and $. 20% vee for VIH and VIL
levels, respectively. Notice that chip enable (E) and G
does not require a pull up to programming voltage levels.
The program control (P) must switch from ground to VIH
and from VIH to the vee PGM level.*
4. The data input buffers must be able to sink up to 3mA
from the PROM's output pins without rising more than
0.7V above ground, be able to hold the other outputs
high with a current source capability of 0.5mA to 2.0mA,
and not interfere with the reading and verifying of the
data output of the PROM. Notice that a bit to be
programmed is changed from a low state (VOL) to high
(VOH) by pulling low on the output pin. A suggested
implementation is open collector TTL buffers (or
inverters) with 4.7kO pull up resistors to vee.*
• Never allow any input or output pin to
fall more than O.3V below ground.

3-203

rise more than O.3V above VCC. or

>",a:
C> 0

====
==

c..>W

HM-6642

DESIGN INFORMATION

(Continued)

The information contained in this section has been deveioped through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Background Information HM-6642 Programming
PROGRAMMING SPECIFICATIONS
SYMBOL
VCCPROG
VCCN
VCClV
ICC
ICC Peak

PARAMETER

MIN

TYP

MAX

UNITS

Programming VCC

12.0

12.0

12.5

V

Operating VCC

4.5

5.5

5.5

V

Special Verify VCC

4.0

System ICC Capability

500

Transient ICC Capability

1.0

-

6.0

-

V
mA
A

PROM INPUT PINS
VOL

Output Low Voltage
(To PROM)

-0.3

GND

20%VCC

V

VOH

Output High Voltage
(To PROM)

70%VCC

VCC

VCC+0.3

V

IOl

Output Sink Current
(At VOL)

0.01

-

-

mA

IOH

Output Source Current
(AtVOH)

0.Q1

mA

PROM DATA OUTPUT PINS
VOL

Output Low Voltage
(To PROM)

-0.3

GND

0.7

V

VOH

Output High Voltage
(To PROM)

70%VCC

VCC

VCC+0.3

V

IOl

Output Sink Current
(At VOL)

3.0

IOH

Output Source Current
(AtVOH)

0.5

td

DelayTime

1.0

1.0

-

~s

tr

Rise Time

1.0

10.0

10.0

~s

mA
1.0

2.0

mA

Fall Time

1.0

10.0

10.0

~s

TEHEL

Chip Enable Pulse Width

500

-

-

ns

TAVEL

Address Valid to Chip
Enable Low Time

500

-

-

ns

TELQV

Chip Enable Low to Output
Valid Time

-

-

500

ns

tf

tpw

Programming Pulse Width

90

100

110

~s

tiP

Input Leakage at
VCC = VCC PROG

-10

+1.0

10

~A

TA

AmbientTemperature

-

25

-

°c

3-204

HM-6642

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
HM-6642 PROGRAMMING CYCLE
PROGRAMMING

Vee PROG
VIH
VIL

A

VERIFV

I

:K

VALID

VALID

!-td_
VIH
VIL

E

~f-----

-

-td--l

f - td Vee PROG
VIH
VIL
Vee PROG
VIH
VIL
Vee PROG
Vee

Vee
GNO

I - td

D

VILIVOL

""""'\.

,

td_

-..............I.......................... ... .............................. .. ........................ ...................
/

td_
Vee PROG
. VIHIVOH

/

"J,-"
f-td--j_tpw---!-td_

"1

-

-tf

I'

>",a:

C> C>

\.....)

READ DATA

HM-6642 POST PROGRAMMING VERIFY CYCLE

A

VIH
VALID

VIL

TEHEL

TEHEL
VIH
VIL
TEHEL
6.0V
S.OV
4.0V
Vee

O.OV
TELDV

D

TELOV

VDH
VDL

READ

READ

3-205

READ

====
==

UW

m

HARRIS

HM-6617/883
2K

'June 1989

8 CMOS PROM

X

Pinouts

Features
• This Circuit Is Processed in Accordance to MIL-STD-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.
• Low Power Standby and Operating Power
• ICCSB •••••••••••••••••••••••••••••••••••••••••••••••••••• 100llA
• ICCOP •••••••••••••••••••••••••••••••••••••••••••• 20mA at 1MHz
• Fast Access Time ••••••••••••••••••••••••••••••••••••••••• 901120ns
• Industry Standard Pinout
• Single 5.0 Volt Supply
• CMOSITTL Compatible Inputs
• High Output Drive ••••••••••••••••••••••••••••••••• 12 LSTTL Loads
• Synchronous Operation
• On':'Chip Address Latches
• Separate Output Enable
• Operating Temperature Range •••••••••••••••••••• -SSoC to +12S o C

Description
The HM-6617/883 Is a 16,384 bit fuse link CMOS PROM in a 2K word by 8
bit/Word format with "Three-State" outputs. This PROM Is available in the
standard 0.600 inch wide 24 pin Ceramic DIP, the 0.300 inch wide slimline
Ceramic DIP, and the JEDEC standard 32 pad Ceramic LCC.

HMl-66l7/883 (CERAMIC DIP)
TOP VIEW

A7

VCC

A6

A8

AS

Ag

A4
A3

P
G

A2

Al0

Al

E

AO

07

00

06

01

Os

02

04

GND

03

The HM-6617/883 utilizes a synchronous design technique. This Includes
on-chip address latches and a separate output enable control which makes
this device ideal for applications utilizing recent generation microprocessors.
This design technique, combined with the Harris advanced seH-aligned silicon
gate CMOS process technology offers ultra-low standby current. Low ICCSB
Is ideal for battery applications or other systems with low power requirements.

HM4-66l7/883 (CERAMIC LCC)
TOP VIEW
.... 0

0

0

00

0

~z z
_. :'~J :'§J :'~J L!J !:!.~ Lt1J Lt.. p_
< z z

z

As 5'
-,
6.
_.
-,
A4 7'
-,
Aa ~J
-,
9.
_.

The Harris NiCr fuse link technology is utilized on this and other Harris CMOS
PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr
fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS EPROMs.

_"

A5

,

Ae

f2'
,-

Ag
NC

1;.

.-

-.

f2'

All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location.

AI

Ao
Ne

Functional Diagram

j>

G

A2

11!-,

AID

_.

E

II'

13

0]

00

Os

MSB
... N C O
C'? 'lit
an
aa~zaaa

...--D--oO°o
t-·C>-+~02

PIN

>--+--003

NC
An·Al0

A HIGH -

OUTPlJT ACTIVE

ADDRESS lATCHES AND GATED DECODERS:
LATCH ON FAlJ.1NG EDGE OF'!!
GATE ON FAWNG EDGE OF jj

it

Copyright @ Harris Corporation 1989

3-206

Address Inputs

E

Chip Enable

0

Data Input

VCC
ALl. LINES POSITIVE LOGIC: ACTIVE HIGH
lHREE· STATE euFfERS:

DESCRIPTION
No Connect

Power (+SV)

G

Output Enable

p.

Program Enable

P Should be Hardwired to VCC Except During
Programming

Specifications HM-6617/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage (All Voltages Reference to Device GND) ••••• + 7.0V
Input or Output Voltage Applied for all Grades ••••••• GND-0.3V to
VCC+0.3V
Storage Temperature Range •••.••.•••••••••• -650C to +1500 C
Lead Temperature (Soldering 10 sec) ••••.•.•••••••••••• +300 0 C
Junction Temperature .••••••••••.•••••.••••.••.•••••. +175 0 C
ESD Classification ....•..•..••••••••••••••.•••.•••••.• Class 1
Typical Derating Factor ••.••••••••• 5mNMHz Increase in ICCOP

Thermal Resistance
Bia
Ceramic DIP Package. • • • • . . . . • • • • •
48 0 C/W
Ceramic LCC Package. . • • . . • . • • • . •
58 0 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package •••••••••.•••••••••••.••••.•••••. 1.0W
Ceramic LCC Package •.•••.••••..•.•••••.•....•.••.. 0.86W
Gate Count •.••.•••.••.•.•••.•••••••••••••.•••••• 5473 Gates

CAUTION: Stresses above those listed in ''Absolute Maximum Ratings" may cause permanent damage to the devics. This iss stress only rating and operation
of the dellice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Supply Voltage (VCC) ••.••••••••••.••.••• 4.5V to 5.5V
Operating Temperature (TA)" •....••••••••••. -55°C to +1250 C

Input Low Voltage (VIL) •.•.•••.•••••.•.••.••...• -0.3V to +0.8V
Input High Voltage (VIH) ....•....••••...••• +2.4V to VCC +0.3V

TABLE 1. HM-6617/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

I

I

Hig!"a teve! OUtput

TEMPERATURE

MIN

VCC=4.5V,
10=-2.0mA

1,2,3

-550C ",a:

00

====
==

c.>W

Standby Supply
Current

Functional Test

Ell

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Address Access Time

TAvav

VCC = 4.SV and S.SV
(NoteS)

9,10,11

-SSoC S. TA S. +12SoC

-

140

ns

Output Enable Access
lime

TGLaV

V CC = 4.SV and 5.SV

9,10,11

-SSoC S. TAS. +12SoC.

-

SO

ns

Chip Enable Access
lime

TELaV

V CC - 4.SV and S.SV

9,10,11

-SSoC S. TAS. +12SoC

-

120

ns

Address Setup Time

TAVEL

V CC = 4.SV and S.SV

9,10,11

-SSoC S. TA S. +12SoC

20

Address Hold Time

TELAX

V CC = 4.SV and 5.5V

9,10,11

-55°C S. TAS. +125 0 C

25

Chip Enable Low Width

TELEH

V CC = 4.5V and 5.5V

9,10,11

-5SoC S.TA S. +1250 C

120

Chip Enable High Width

TEHEL

V CC = 4.5V and 5.5V

9,10,11

-55°C :5.TA:5. +125 0C

40

-

Read Cycle Time

TELEL

VCC = 4.5V and 5.5V

9,10,11

-55°C S.TA:5. +12SoC

160

-

NOTES: 1. All voltages referenced to Device GNO.
2. AC measurements assume transition time S. 5ns; input levels =
O.OV to 3.0V; timing reference levels"'" 1.5V; outpulload = 1TTL
equivalent load and CL '= 50pF.

3. Typical derating = 5mNMHz increase in ICCOP.
4. All tests performed with P hardwired to VCC'
5. TAVQV = TELQV + TAVEL

CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

3-207

ns
ns
ns
ns
ns

Specifications HM-6617/883
TABLE 3. HM-6617/883 A.C. AND D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

Input Capacitance

CIN

LIMITS

(NOTE 4)
CONDITIONS

SYMBOL

PARAMETERS

NOTES

TEMPERATURE

MIN

MAX

UNITS

-

10

pF

=

=

6,9

+25 0e

=

=

6,10

+250 e

-

12

pF

6,11

+25 0 e

-

10

pF

Vce Open, f = 1 MHz,
All Measurements Referenced
to Device GND

6,9

+25 0 e

-

12

pF

Vee = Open, f = 1 MHz,
All Measurements Referenced
to Device G ND

6,10

+25 0e

-

14

pF

6,11

+25 0 e

-

12

pF

5

-

ns

5

-

ns

50

iiS

50

no

-

V

Vce Open, f 1 MHz,
All Measurements Referenced
to Device G ND
Vce Open, f 1 MHz,
All Measurements Referenced
to Device G ND

VO CapaCitance

CliO

=

Chip Enable Time

TELQX

Vce =4.5Vand 5.5V

6

-55°C :5.TA:5. +125 0e

OutP'!t Enable Time

TGLQX

Vce = 4.5Vand 5.5V

6

-550e:5.TA:5.+1250e

TEHQZ

Vc;:c;: =4.5Vend 5.5V

6

-55°C :5.TA:5. +125 0C

Chip Dlsabi~ Time

I

Output Disable Time

TGHQZ

Output High Voltage

VOH2

NOTES:

Vee = 4.5V and 5.5V

6

-550e:5.TA:5.+1250e

Vee =4.5\1,10 = 100)lA

6

-550e:5.TA:5.+1250e

Vee 1V

,

6. The parameters listed in table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon Initial design and after design or process changes which 'would affect thesa characteristics.
7. Tested as follows: f ~ 2MHz. V1H ~ 2.4V. V 1L

= O.4V.I OH = -4.0mA. V OH .!: 1.5V. and VOL ~ 1.5V.

e. This is a "typical" value and not a "maximum" value.

9. Applies to .600 inch Ceramic Dual-In-line (DIP) device types only.
10. Applies to .300 inch Ceramic Dual-In-line (DIP) device types only.
11. Applies to Ceramic Leadless Chip Carrier (LCC) device types only.
12. Tostod as follows: f

= lMHz. V1H = 2.4V''V1L = O.8V.I OH = -1mA.I OL = +lmA. VOH ~ 1.5V. VOL ~ 1.5V.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

. METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3, BA, B8, 10, 11

Group A

Samples/5005

1,2,3,7, BA, BB, 9, 10, 11

Groupse&D

Samples/5005

1,7,9

3-208

Specifications HM-6617B/883
Absolute Maximum Ratings

Reliability Information

SupplyVollage (All Voltages Reference to Device GND) ..••• +7.0V
Input Dr Output Voltage Applied for all Grades ...••.. GND-O.3V to
VCC +O.3V
Storage Temperature Range ..•...••......•.• -65 0 C to +150 0 C
Lead Temperature (Soldering 10 sec) .••...••......•.•.• +300 0 C
Junction Temperature ................................ +175 0 C
ESD Classification .................................... Class 1
Typical Derating Factor ••••.•.•••.. 5mA/MHz Increase in ICCOP

Thermal Resistance
0ja
Ceramic DIP Package. . . . . . • . . . . . . •
4BoC/W
Ceramic LCC Package. . . . . • . . . . . . .
5BoC/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ................................. 1.0W
Ceramic LCC Package ............................... 0.B6W
Gate Count ...................................... 5473 Gates

CAUTION: Stresses above those listed in "Absolute M~jmum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
o( the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Supply Voltage (VCC) .••......•.......... 4.5V to 5.5V
Operating Temperature (TA)" ................ -55 0 C to +1250 C

Input Low Voltage (VIL) ......................... -0.3V to +O.BV
Input High Voltage (VI H) •.•.•.•••.•...•••.. +2.4V to VCC +0.3V

TABLE 1. HM-6617B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed arid 100% Tested

D.C. PARAMETERS

(NOTES 1,4)
CONDITIONS

SYMBOL

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

1,2,3

-550 C.s, TA.s, +i250C

2.4

-

V

High Level Output
Voltage

VOH1

V CC =4.5V,
10=-2.0mA

Low Level Output
Voltage

VOL

VCC=4.5V,
10=+4.BmA

1,2,3

-550 C S,TAs' +125 0 C

-

0.4

V

High Impedance Output
Leakage Current

IIOZ

V CC = 5.5V, G = 5.5V,
VI/O=GNDorV CC

1,2,3

-550 C.s,TAS,+125 0 C

-1.0

1.0

~A

VCC '=. 5.5V, VI = GND Dr
VCC, P NotTested

1,2,3

-550 C.s,TA$+125 0 C

-1.0

1.0

~

Input Leakage Current

>-

II

Standby Supply
Current

ICCSB -.-

10= Vee or GND,
VCC = 5.5V, 10 = OmA

1,2,3

-550 C .s,TA S, +125 0 C

-

100

~

Operating Supply
Current

ICCOP

VCC = 5.5V, G = GND,
(Note 3), f = 1 MHz, 10 =
OmA, VI = VCC or GND

1,2,3

-550 C.s,TA.s,+125 0 C

-

20

rnA

7,BA,BB

-550 C .s,TAs' +1250 C

-

-

FT

Functional Test

VCC = 4.5V (Note 12)

TABLE 2. HM-6617B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

A.C. PARAMETERS

(NOTES I, 2, 4)
CONDITIONS

SYMBOL

LIMITS

GROUPA'
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Address Access Time

TAVOV

VCC = 4.5V and 5.5V
(Note 5)

9,10,11

-550 C.s,TAS,+1250 C

-

105

ns

Output Enable Access
Time

TGLOV

VCC = 4.5V and 5.5V

9,10,11

-550 C.s,TA.s,+1250 C

-

40

ns

Chip Enable Access
Time

TELOV

VCC "" 4.5V and 5.5V

9,10,11

-550 C.s,TA.s,+1250C

-

90

ns
ns

Address Setup Time

TAVEL

VCC = 4.5V and 5.5V

9,10,11

-550 C .s,TA.s, +1250 C

15

-

Address Hold Time

TELAX

VCC = 4.5V and' 5.5V

9,10,11

-550 C.s,TA.s,+1250 C

20

-

ns

Chip Enable Low Width

TELEH

V CC = 4.5V and 5.5V

9,10,11

-550 C.s,TA.s, +1250 C

95

-

ns

Chip Enable High Width

TEHEL

VCC = 4.5V and 5.5V

9,10,11

-550 C.s,TA.s,+1250C

40

Read Cycle Time

TELEL

VCC = 4.5V and 5.5V

9,10,11

-550 C.s,TA.s,+1250C

136

NOTES: 1. All voltages referenced to Device GND.
2. AC measurements assume transition time

O.OV to 3.0V; timing reference levels
equivalent load and CL ~ 50pF.

.5. 5n8; input levels =
= 1.5V; output load = 1TTL

3. Typical derating = SmNMHz increase in rccop.
4. All tests performed with Phardwired to VCC'
5. TAVOV = TELOV + TAVEL

CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

3-209

-

ns
ns

enD:
00

:E:E
..... w
:E

Specifications HM-6617B/883
TABLE 3. HM-6617B/883 A.C. AND D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETERS
Input Capacitance

I/O Capacitance

CIN

CI/O

LIMITS

(NOTE 4)
CONDITIONS

SYMBOL

NOTES

TEMPERATURE

MIN

MAX

UNITS

VCC = Open, f = 1 MHz,
All Measurements Referenced
to Device G NO

6,9

+2SoC

-

10

pF

VCC = Open, f = 1 MHz,
All Measurements Referenced
to Device GND

6,10

+2SoC

12

pF

6,11

+2SoC

10

pF

VCC = Open, f = 1 MHz,
All Measurements Referenced
to Device GND

6,9

+2SoC

12

pF

VCC = Open, f= lMHz,
All Measurementa Referenced
to Device GND

6,10

+2SoC

14

pF

6,ri

+2SoC

-

12

pF

-

Chip Enable-Time

TElQX

VCC = 4.SVand S.SV

6

-550C!:. TA!:. +1250 C

5

Output Enable Time ..

TGlOX

VCC = 4.5Vand 5.5V

6

·-550C~TA!:. +1250 C

5

-

Chip Disable Time

TEHaZ

VCC = 4.5Vand 5.SV

6

-SSOC!:.TA!:.+12S0C

-

4S

ns

Output Disable Time

TGHOZ

VCC = 4.SV and S.SV

6

-SSoC !:.TA!:. +12SoC

-

40

ns

Output High Voltage

VO H2

VCC = 4.SV, 10 =.100pA

6

-ssoC!:. TA ::; +12SoC

VCC~

-

V

ns
ns

1V
NOTES:

6. The parameters listed in table 3 are controlled via design or process parameters and are nol direclly tested. These parameters are characterized
upon initial design changes which would affect these characteristics.
7. Tested as follows: f

= 2MHz. V tH = 2.4V. VIL = O.4V. tOH = -4.0mA. VOHZ- 1.5V. and VOL :0,1.5\1.

S.' This is a typical" value and not a maximum" value.

9. Applies to .600 inch Ceramic Dual-in-Line (DIP) device types only.
10. Applies to .300 inch Ceramic Oual-in-Line (DIP) device types only.

11. Applies to Ceramic Leadless Chip Carrier (LCC) device types only.
12. Tested as follows: f

= 1MHz. VIH = 2.4V. VIL = O.BV. IOH = -1mA, IOL = +1 mA, VOH Z- 1.5V, VOL ~ 1.5V.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/S004

-

Interim Test

lOO%/S004

1,7,9

PDA

lOO%/S004

1

Final Test

100%/S004

2,3, 6A, 8B, 10, 11

Group A

Samples/SOOS

1,2,3,7, 8A, 8B, 9,10,11

GroupsC&D

Samples/SOOS

1,7,9

3-210

HM-6617/883
Switching Waveforms
READ CYCLE

t - - - - - - TAVOV----~·~I

ADDRESSES

t - - - t - - - - - TELEL - t - - - - - - - - - - - 1 · 1

1

f

,...----""\ ....- - - - - - - - TELEH---'------.l.1 r - - - _ _ . I
30V
~1.5V OV.
'--________-+___.....J·I 1.5V
--+-_--TELOV

-rc:.:.

~

"I

j..-TEHOZ

I

G

------II----.,~ TGLOV

1.5V
TGLOX

--I

I
f,...---I~----3.0V

~~._ _ _-+:__...J I
I--

--I

DATA
OUTPUT - - - - - - - - - - - 00 - 07

I

I

1.5V

1

--f TGHOZ j..-~VA~L~ID~~~~I_ _ _ _ _ _
DATA

/'

Test Circuit

OUT 0-""",-+-<

t
EQUIVALENT CIRCUIT

3-211

OV

I

IOL

TS

HM-6617/883

Burn-In Circuits

HM-6617/683 (.300 INCH) CERAMIC DIP
vee

'a o---,\M-I
'70---,\M-I
'80---,\M-I

1-""'.,....-0'8
1-"",.,....-0 ',0

'50---'\M--t

1-""'''''''-0 vee

'40---,\M-I

l--oJ\I\J'--O

'30---'\M--t

l--oJ\I\J'--O 'II

'20---,\M-I

1-"",.,....-0'0

'12

'I o---,\M-I

GND

HM-6617/883 (.600) CERAMIC DIP
vee

,-=-"YY-"0

'12

Vee

"

"3
'0

GND

HM-6617/883 CERAMIC LCC

291--'IIW-- '11

r2lll--'lJVv--

NOTES:

'0 = 100kHz ± 10%

All resistor. = 47kO Unless Otherwise Noted
Vee = 5.5V ± 0.05V
e = O.ot"" min

3-212

"2

HM-6617/883
Metallization Topology
DIE DIMENSIONS:
140 x 232 x 19 ± 1mils
METALLIZATION:
Type: Si -AI
Thickness: 11 kA - 15kA
GLASSIVATION:
Type: Si02
Thickness: 7kA - 9kA

DIE ATTACH:
Material: Si - Au Eutectic
Temperature: Ceramic DIP - 46QOC (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
1.7 x 105 Ncm 2

Metallization Mask Layout
HM-66171883

3-213

HM-6617/883
Packaging t

r=--,--r::

24 PIN (.300) CERAMIC DIP

.200 MAX

:::~

1.

~

J~I

r

,1

I.,i,o"
bL
.:~jL,,, ..~~ .09'."
• INCREASE MAX UIAIT BY .DOl INQiES

MEASURED AT CENTER Of FLAT FOR
SOLDER FINISH

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
Method: Furnace Seal
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-9

24 PIN (.600) CERAMIC DIP

..

IN~EASE

t.lAX UWtT

ay

.00l IHQiES

MEASURED AT CENTIR OF' FLAT Fcm

SOLDER FINISH

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 1QoC
Method: Furnace Seal
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-3

32 PAD CERAMIC LCC
. PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Ceramic AI203 90%
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 320 0 C ± 100 C
Method: Furnace Braze
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-12

NOTE: All Dimensions are

..Mi!:L. • Dimensions are in
Max

t Mil-M-38S10 Compliant Materials, Finishes, and Dimensions.

inches.

3-214

mHARRIS

HM-6617

DESIGN INFORMATION
2K x 8 CMOS PROM
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Background Information HM-6617 Programming
PROGRAMMING SPECIFICATIONS
SYMBOL

MIN

PARAMETER

VIL

Input "0"

VIH

Voltage "1"

TYP

MAX

UNITS

NOTES

0.0

0.2

0.8

V

VCC-2

VCC

VCC+0.3

V

6

Programming VCC

12.0

12.0

12.5

V

2

VCC1

Operating V ce

4.5

5.5

5.5

V

VCC2

VCCPROG

Special Verify VCC

4.0

-

6.0

V

td

DelayTime

1.0

1.0

-

~s

tr

RiseTime

1.0

10.0

10.0

~s

tf

Fall Time

1.0

10.0

10.0

~s

TEHEL

Chip Enable Pulse Width

50

-

ns

TAVEL

Address Valid to Chip Enable Low Time

20

-

-

TELQV

Chip Enable Low to Output Valid Time

-

-

120

ns

Programming Pulse Width

90

100

110

~s

-10

+1.0

10

f1A.

tpw

ns

tiP

Input Leakage at Vce = VCCPROG

lOp

Data Output Current at VCC = VeCPROG

-

-5.0

-10

mA

Rn

Output Pull-Up Resistor

5

10

15

kO

AmbientTemperature

-

25

-

°C

TA
NOTES:

1. All inputs must track

Vee (pin

24) within these limits,

2. VCCPROG must be capable of supplying SOOmA.
3. See Sleps 22 through 29 of the Programming Algorithm.
4. See Step 11 of the Programming Algorithm.
5. All outputs should be pulled up to

Vee through a resistor of value Rn.

6. Except during programming (See Programming Cycle Waveforms).

3-215

3

4

5

HM-6617

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design aid only. These characteristics are not 100% tested and no product guarantee is implied.

Background Information Programming Algorithm
The HM-6617 CMOS PROM is manufactured with all bits
containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by
following the procedure shown below. To accomplish this, a
programmer can be built that meets the specifications
shown, or any of the approved commercial programmers
can be used.

17) Place the PROM in the post-programming verification
mode:
E = VIH, G= VIL, P = VIH, Vee (pin 24) = Vee1·
18) Apply the correct binary address of the word to be
verified to the PROM.
19) After a delay of td' apply a,voltage of VIL to E (pin 18).

PROGRAMMING SEQUENCE OF EVENTS
1) Apply a voltage of Vee1 to Vee of the PROM.
2) Read all fuse locations to verify that the PROM is blank
(output low).
3) Place the PROM in the initial state for programming:
E = VIH' P = VIH' G = VIL·
4) Apply the correct binary add ress for the word to be programmed. No inputs should be left open circuit.
5) After a delay of td' apply voltage of VIL to
access the addressed word.

POST-PROGRAMMING VERIFICATION

E(pin

18) to

20) After a delay of td, examine the outputs for correct data.
If any location fails to verify correctly, the PROM should
be considered a programming reject.
21) Repeat steps 17 through 20 for all possible programming locations.
POST-PROGRAMMING REP.D
22) Apply a voltage of VeC2 = 4.0V to VCC (pin 24).
23) After a delay of !ct, apply a voltage of VIH to E (pin 18).
24) Apply the correct binary address of the word to be read.

6) The address may be held through 'the cycle, but must , 25) After a delay of TAVEL, apply a voltage of VIL to E (pin
be held valid_at least for a time equal 'to td after the fail18).
Ing edge of E. None of the inputs should be allowed to
26)
After
a delay of TELQV, examine the outputs for correct
float to an invalid logic level.
data. If any location fails to verify correctly, the PROM
7) After a delay of tn, disable the outputs byapplyillg a
should be considered a programming reject.
voltage of VIH to G (pin 20).
27) Repeat steps 23 through 26 for all address locations.
8) After a delay of td' apply voltage of VIL to P (pin 21).
28) Apply a voltage of VCC2 = 6.0V to Vce (pin 24).
9) After delay of td' raise Vee (pin 24) to VeePROG with
a rise time of tf" All outputs at VIH should track Vee with 29) Repeat steps 23 through 26 for all address locations.
Vee-2.OV to Vee+0.3V. This could be accomplished
by pulling outputs at VIH to Vee through pull-up resistors of value Rn.
10) After a delay of td' pull the output which corresponds to
the bit to be programmed to VIL. Only one bit should be
programmed at a time.
11) After a delay of tpw' allow the output to be pulled to VIH
through pull-up resistor Rn.
12) After a delay oftd' reduce Vee (pin 24) to Vee1 with a
fall time of It. All outputs at VIH should track Vee with
Vee-2.OV to Vee+0.3V. This could be accomplished
by pulling outputs at VIH to Vee through pull-up resistors of value Rn.
13) Apply a voltage of VIH to

P (pin 21).,

14) After a delay of td, apply a voltage of VIL to

G(pin 20).

15) After a delay of td, examine the outputs for correct data.
If any location verifies incorrectly, repeat steps 4
through 14 (attempting to program only those bits in the
word which verified incorrectly) up to a maximum of
eight attempts for a given word. If a word does not program within eight attempts, it should be considered a
programming reject.
16) Repeat steps 3 through 15 for all other bits to be programmed In the PROM.

3-216

HM-6617

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is tor
use as application and design aid only. These characteristics are not 100% tested and no product guarantee is implied.
HM-6617 PROGRAMMING CYCLE

.-

PROGRAMMING

VERIFY

,.

Vee PROG
A

V,H
V,L

I

VALID

VALID

~

!--'d-

if

Vee PROG
V,H

.

VIL

.
Vee

Vee PROG
vee
GND

a

Vee PROG
V,HIVOH
V,LIVOL

I--'d--l

I-'d-

I"~

1/

I

I

I--'d/

I

I-'d-

I
- .............. ...........................

1/

"_

.-

..

.. .............................. " ....................... ...................
I-'d
'pw
'd- r--"
I'

-r- ----r-

Vn r

\.....)

READ DATA

HM-6617 POST PROGRAMMING VERIFY CYCLE

A

V,H
V,L

VALID
TEHEL

TEHEL
V,H
V,L

B.OV
5.0V
4.0V
Vee

o.ov

Q

,
..............................................................................................................................

VOH
VOL

READ

READ

3-217

READ

CMOS MICROPROCESSORS

PAGE

80C286/883

Static 16-Bit Microprocessor. .. .. ... ............ .. .... ... .... ... ..

4-3

80C86/883

Static 16-Bit Microprocessor. .. . . .. . . .. . . .. . . .. . . . .. . . . . . . .. . . . . . .

4-62

80C88/883

Static 8/16-Bit Microprocessor. . . .. . . .. . . .. . ... . . . .. . . .. . . . .. . . . . .

4-97

App Note 111

Harris 80C286 Performance Advantages Over the 80386 . . . . . . . . . . . . .

4-131

App Note 112

80C286/80386 Hardware Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-143

App Note 120

Interfacing the 80C286-16 with the 80287-10.. .. . . . .. . . .. . . ... . . . . .

4-147

4-1

80C286/883

mHARRIS
June 1989

High Performance Microprocessor
With Memory Management and Protection
Pin Configurations

Features
• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.
• Compatible with NMOS 80286/883

Component Pad Views
As viewed from underside of the component
when mounted on the board.
~a:;~CCDCO

• 10MHz Operation (80C286-10/883)
• 12.SMHz Operation (80C286-12/883)

o

• Static CMOS Design for Low Power Operation
.. ICCSB = SmA Maximum

.,

.,
'".,

.. ICCOP = 18SmA Maximum (80C286-10/883)

.."
@@@@

iiiiiQRNC

~~[J~~

@@
@@
@@
@@
@@

@@

®®

PGA

@@
@@
@@
@@@@®@(!)(!)0 2 @

@@@@®0@

3

NMI

Ne

PEREa

Vss

RUDV Vee

HLOA

HOLD

MliO

CODIi'NfA

Ne

,

• Integrated Memory Management, Four-Level Memory Protection
and Support for Virtual Memory and Operating Systems
• Two 80C86 Upward Compatible Operating Modes:
.. 80C286/883 Real Address Mode
.. Protected Virtual Address Mode
en

• Compatible with 80287 Numeric Data Co-processor
• Available In 68 Pin PGA (Pin Grid Array) Package
• Wide Operating Temperature Range ••••••••••• -SSoC to +12S 0 C

a:

o

P.C. Board Views
As viewed from the component side of the
p.e. board.
0

Description

I~

The Harris 80C286/883 is a static CMOS version of the NMOS 80286
microprocessor. The 80C286/883 is an advanced, high-performance
microprocessor with specially optimized capabilities for multiple user and
multi-tasking systems. The 80C286/883 has built-in memory protection
that supports operating system and task isolation as well as program and
data privacy within tasks. The 80C286/883 includes memory management
capabilities that map 230 (one gigabyte) of virtual address space per task
into 224 bytes (16 megabytes) of physical memory.

Ne EiiiiOii
.~,

"
"

Vss

The 80C286/883 provides special operations to support the efficient
Implementation and execution of operating systems. For example, one
instruction can end execution of one task, save its state, switch to a new
task, load its state, and start execution of the new task. The segment-notpresent exception and restartable instructions.
Copyright @.Harris Corporation 1989

4-3

PUI.EO

Vee iii'AiiY
HOLD

HLOA

CODli'NfA

wiO

COEiC

The 80C286/883 Is upwardly compatible with 80C86 and 80C88 software
(the 80C286/883 instruction set is a superset of the 80C86/80C88
instruction set). Using the 80C286/883 real address mode, the 80C286/
883 is object code compatible with existing 80C86 and 80C88 software. In
protected virtual address mode, the 80C286/883 is source code compatible with 80C86 and 80C88 software but may require upgrading to use
virtual address as supported by the 80C286/883's integrated memory
management and protection mechanism. Both modes operate at full
80C286/883 performance and execute a superset of the 80C86 and
80C88 instructions.

"
'M'

'''1A

"

PIN I INDICATOR

0

0

0

0 8 8

~

~

0

~

B B 0 8

.

ClIO I~

~ ~

••••
• •

I~ ~ 10 ~ ~ ~

~

o

a:

:5

@@@@)@@@)@®
@@@@®@@@@®® 0'
@@
@@ A'
@@
®@ '"
@@l
@@ RESET
PG'
@@ A.
@@
@@
@@ A'
@@ A.
@®
@@ A"
®®

@20®®®®®®@>@
3®0®®®®®

Ug:
u

~

0

en
en
en ....
0""
:;:0

AU

.,A'
'<0
A3

..
A.

A.

AU

A"

80C286/883
. Functional Diagram
r---------------------------,
ADDRESS UNIT (AU)

PEiCK

1--'---1-- PEREO

'----1--i-+--JiElliV,
~.

HOLD

SO. eooiIATA

~.HLDA

RESET
elK

Vss
Vee

INTR

4-4

80C286/883
Pin Description
The following pin function descriptions are for the 80C286/883 microprocessor:

SYMBOL

PIN
NUMBER

TYPE

DESCRIPTION

CLK

31

I

SYSTEM CLOCK: provides Ihe fundamental timing for Ihe 80C286/883 system. It is divided
by t\yo inside Ihe 80C286/883 10 genenerale Ihe processor clock. The inlernal divide-by-Iwo
circuilry can be synchronized to an external clock generator by a LOW to HIGH
transition on Ihe RESET input.

015-00

36-51

1/0

A23-AO

7-8
10-28
32-43

0

ADDRESS BUS: outpuls physical memory and 1/0 port addresses. A23-A 16 are LOW
during 1/0 Iransfers. AO is LOW when dala is 10 be Iransferred on pins 07-00 (see lable
below). The address bus is aclive High and floals 10 Ihree-stale off during bus hold
acknowledge.

BHE

1

0

BUS HIGH ENABLE: indicates transfer of data on Ihe upper byte of Ihe data bus,
015-08. Eighl-bil orienled devices assigned 10 Ihe upper byte of Ihe data bus would
normally use BHE to condilion chip selecl functions. BHE is active LOW and floals to
three-slale OFF during bus hold acknowledge.

DATA BUS: inpuls dala during memory,l/O, and inlerrupl acknowledge read cycles;
oulpuls dala during memory end I/O wrile cycles. The data bus is aclive HIGH and is
held al high impedance 10 Ihe lasl valid logic level during bus hold acknowledge.

EiHE and AO I=.ncodings
BHEValue

AOValue

0
0
1
1

0
1
0
1

Function
Word Iransfer
Byte transfer on upper half of data bus (DI5-08)
Byte transfer on lower half of data bus (07-00)
Reserved


a:

o
51,50

4,5

0

BUS CYCLE STATUS: indicates initiation of a bus cycle and along wilh MIlO and
CODIINTA, defines the type of bus cycle. The bus is in a TS stale whenever one or both
are LOW. 51 and SO are active LOW and are held al a high impedance logic one during
bus hold acknowledge.
80C286/883 Bus Cycle SIatus Definition

MIlO

67

0

Bus Cycle Initiated

CODIINTA

MilO

51

SO

O(LOW)
0
0
0
C
0
0
0
I(HIGH)
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

Interrupt" acknowledge
Reserved
Reserved
None; not a slatus cycle
If Al = 1 then halt; else shutdown
Memory data read
Memory data write
None; nol a status cycle
Reserved
I/O read
I/O write
None; not a stalus cycle
Reserved
Memory instruction read
Reserved

1

None, not a status cycle

MEMORY I/O SELECT: distinguishes memory access from 1/0 access. If HIGH during
TS, a memory cycle or a hallsshutdown cycle i~n progress. If LOW, an I/O cycle or an
interrupt acknowledge cycle is in progress. MIlO is held al high impedance to the last
valid logic slale during bus hold acknowledge.

4-5




W
0<'>

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o
a:
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iiE

80C286/883

Pin Description

(Continued)

SYMBOL

PIN
NUMBER

TYPE

COD/INTA

66

0

CODE/INTERRUPT ACKNOWLEDGE: distinguishes instruction fetch cycles from
memory data read cycles. Also distinguishes interrupt acknowledge cycles from I/O
cycles. COD/INTA Is held at high Impedan~ to the last valid logic state during bus hold
acknowledge. Its timing is the same as MilO.

LOCK

68

0

BUS LOCK: indicates that other system bus mas~ not to gain control of the system
bus for the current and following bus cycles. The LOCK signal may be activated explicitly
by the "LOCK" instruction prefix or automatically by 80C286/883 hardware during
memory XCHG instructions, interrupt acknowledge, or descriptor table access. LOCK
is active LOW and is held at a high impedance logic one during bus hold acknowledge.

READY

63

I

BUS READY: terminates a bus cycle. Bus cycles are extended without limit until
terminated by READY LOW. REi\i5Y is an active LOW synchronous input requiring setup
and hold times relative to the system clock be met for correct operation. READY is
ignored during bus hold acknowledge. (Note 1)

HOLD
HLDA

64
65

I

0

BUS HOLD REQUEST AND HOLD ACKNOWLEDGE: control ownership of the 80C286/883
local bus. The H OLD input allows another local bus master to request control of the local
bus. When control is granted, the 80C286/883 will float its bus drivers and then activate
HLDA, thus entering the bus hold acknowledge condition. The local bus will remain granted
to the requesting master until HOLD becomes inactive which results in the 80C286/883
deactivating HLDA and regaining control of the local bus. This terminates the bus hold
acknowledge condition. HOLD may be asynchronous to the system clock. These signals
are active HIGH. Note that HLDA never floats.

.INTR

57

I

INTERRUPT REQUEST: requires the 80C286/883 to suspend its current program execution
and service a pending external requesllnterrupt requests are masked whenever the interrupt
enable bit in the flag word is cleared. When the 80C286/883 responds to an interrupt
request, it performs two interrupt acknowledge bus cycles to read an 8-bit interrupt
vector that identifies the source of the interrupt. To ensure program interruption,lNTR
must remain active until an interrupt acknowledge bus cycle is initiated.INTR is sampled
at the beginning of each processor cycle and must be active HIGH at least two processor
cycles before the current instruction ends in order to interrupt before the next instruction.
INTR is level sensitive, active HIGH, and may be asynchronous to the system clock.

NMI

59

I

NON-MASKABLE INTERRUPT REQUEST: interrupts the 80C286/883 with an internally
supplied vector value of two. No·interrupt acknowledge cycles are performed. The
interrupt enable bit in the 80C286/883 flag word does not affect this inpul The NMI input
Is active HIGH, may be asynchronous to the system clock, and is edge triggered alter
internal synchronization. For proper recognition, the input must have been previously
LOW for atleastfour system clock cycles and remain HIGH for atleastfour system clock
cycles.

PEREQ

PEi\CK

61
6

I
0

PROCESSOR EXTENSION OPERAND REQUEST AND ACKNOWLEDGE: extend the
memory management and protection capabilities of the 80C286/883 to processor
extentions. The PEREQ input requests the 8OC286/883 to perform a data operand transfer
for a processor extension. The PEACK output signals the processor extension when the
requested operand is being transferred. PEREQ is active HIGH. PEACK is active LOW
and is held at a high impedance logic one during bus hold acknowledge. PEREa may be
asynchronous to the system clock.

BUSY
ERROR

54
53

I
I

PROCESSOR EXTENSION BUSY AND ERROR: indicates the operating condition of a
processor extension to the 80C286/883. An active BUSY input stops 80C286/883
program execution on WAIT and some ESC instructions until BUsY becomes inactive (HIGH).
The 80C286/883 may be interrupted while waiting for BUSY to become inactive. An active
ERROR input causes the 80C286/883 to perform a processor extension interrupt when
executing WAIT or some ESC instructions. These Inputs are active LOW and may be
asynchronous to the system clock.

DESCRIPTION

4-6

80C286/883
Pin Description

(Conllnued)

SYMBOL

PIN
NUMBER

TYPE

RESET

29

I

DESCRIPTION
SYSTEM RESET: clears the intemallogic of the 80C286/883 and is active HIGH. The
80C286/883 may be reinilialized at any time with a LOW to HIGH transition on RESET
which remains active for more than 16 system clock cycles. During RESET active, the
output pins of the 80C286/883 enter the state shown below.
80C286/883 Pin State During Reset
Pin Value

Pin Names

1 (HIGH)
a (LOW)

SO, S1, PEACK, A23-AO, BHE, LOCK
Miio, COD/INTA, HLDA (Note 2)
D15-DO

HIGH IMPEDANCE

Operation of the 80C286/883 begins after a HIGH to LOW transition on RESET. The HIGH to
LOW transition of RESET must be synchronous to the system clock. Approximately 50
system clock cycles are required by the 80C286/883 for internallnitializations before the
first bus cycle to fetch code from the power-on execution address is performed. A LOW to
HIGH transition of RESET synchronous to the system clock will end a processor cycle at
the second HIGH to LOW trensition olthe system clock. The LOW to HIGH transition of
RESET may be asynchronous to the system clock; however, in this case it cannot be
predetermined which phase of the processor clock will occur during the next system
clock period. Synchronous LOW to HIGH transitions of RESET are required only for
systems where the processor clock must be phase synchronous to another clock.

to system ground).

VSS

9,35,60

I

SYSTEM GROUND: are the ground pins (all must be connected

VCC

30,62

I

SYSTEM POWER: +5 volt power supply pins. A 0.1,.F capacitor between pins 60 and 62 is
recommended.

NOTES: 1. READY is an open-collector signal and should be pulled inactive with an 6200 resistor.

2. HLDA is only Low if HOLD is inactive (Low).
3. All unused inputs should be pulled to their inactive stale with pull up/down resislors.

""Ie

o

""
""

",,'"

0'"

:Eo

..,IE
o

..,Ie
~

4-7

Specifications 80C286/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••.•••••••••••••••••••••••••••• +8.0V
Input, Output or I/O Voltage Applied ••••• GND -1.oVto VCC +1.0V
Storage Temperature ~ang9 ••••.•••••••••••• -650C 10 +1500 C
.JunctionTemperature ••••••••••.••••••••••••••••••.•• +1750 C
lead Temperature (Soldering, 10 Seconds) ••••••••••••• +3000 C
ESD Classification ..................................... Class 2

alc .••••••••••.••••••••••.•••••.•.•••• 170 CIW (PGA Package)
ala .••••••••••••••••••••••••••••..•••• 41 0 CIW(PGAPackage)
Maximum Package Power Dissipation •••••••••••••••••••• 1.22W
Typical Derating Factor •.••••.•••• 17mNMHz Increase in ICCOP
Gate Count ..................................... 22,500 Gates

CAUTION: Stresses above those listed in the "Absolute Maximum RatingsH may cause permanent damage to the device. This is a stress only rating and operation of the c/eviice at these or any other conditions above those indicated in thl} operation section 01 this specification is not implied.

Operating Conditions
Operating Voltage Range •••• ; •••••••••••••••••• +4.5V 10 +5.5V
Operating Temperature Range ••••••• : .••.••• -550C 10 +1250 C
System Clock (ClK) RISE Time (From 1.0V 10 3.6V) ••.•• 8ns (Max)
System Clock (ClK) FALL Time (From 3.6V to 1.0V) ••••• 8ns (Max)
TABLE 1.

Input RISE/FALL Time (From O.8V to 2.0V)
80C286-10/883 •••••.••••••••••.•••••••.••.••. 10ns (Max)
80C286-12/883 .................................. 8ns (Max)

80C286/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Guaranteed and 100% Tested

PARAMETER
Input LOW Vollage

SYMBOL

CONDITIONS

UMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

VIL

VCC=4.5V

1,2,3

-55°C 5. TA 5. +12SOC

-0.5

0.8

V

Input HIGH Vollage

VIH

VCC= 5.5V

1,2,3

-550C ~o/'-lrV'V''''''/v"V'V'

OTHER
DEVICE
INPUT

'\(

O.UV
O.4V

/-f,'xEK>&CXX)(XX;>e
I

_

'DELAY (Max.)_

-'DELAY (Min.)-

~IL

2.OV

~~

DEVICE
OUTPUT

~ O.UV
I

NOTE:. For A.C. testing, input rise and fall times are driven at 1ns per volt.

4-12

80C286/883
Waveforms

WRITE CYCLE
ILLUSTRATED WITH ONE
WAIT STATE

{0
:..iJJ;" ~nlFJl~~~JllP
VD~@- ~
~

BUS CYCLE TYPE

CLK

READ CYCLE
ILLUSTRATED WITH ZERO
WAIT STATES

~

~

.

A23 - AO

~~'"

~

K

015 - DO

/

.@.H

-

~i

VALID CDNTR

----------------- ----

r@.i

-

w//4

VAliD CONHOL

)W/~

VALID ADDR ,SS

Mliii. COD INTA

....

~L

I~ ~VALID

VALID ADDIIESS

®-

I-

,.-e~

-@

'\\.\\\\\..

SRDY + SRDYE N

-I@ -

N
u

a

:z:

.,

AL F.

'""'

~@
~'\'\ ~\~

-

V- rL ~ ~V- ':~
:rr i\
L
-I@
~@I-~,~[
-~
@- - r--@t
"'"
,.
-I@ ,.
- -t®- ,.
,.
'-

~
K_~3,@-

-

nn

-@ r-

u
u

--

~

-®r
.-j.@) :-

r@
..:I®'-

ARDY + ARDYE N

X

VAlli WRITE DATA

l:l@)READY

TS

~':"""'-

r@1

@:.. r-

PCL

~J

I-

-

g

~

'0.;

~@.

READ
(TI DR TS)

:@.

--

I-

CMDL Y

MWT C

g

~

lr-

(SEE NOTE

-@I-

MRD C

DTIii

f- .~ -@

I-

@-

DE N

@

@r=.

MAJOR CYCLE TIMING
NOTES: 1. The modified timing is due to the CMDLY signal being active.

2. B2C284 and 62C288 timing waveforms are shown for reference only. and no guarantee is

4-13

-11

impli~d.

80C286/883
Waveforms

(Continued)
80C286/883 RESET INPUT TIMING AND
SUBSEQUENT PROCESSOR CYCLE PHASE

80C286/883 ASYNCHRONOUS INPUT SIGNAL TIMING

BUS CYCLE TYPE
CLK
PCLK
(SEE NOTE 11
INTR,NMI
HOLD, PE REQ 777TT1m771'lJr"'-hJm7n771rr7
(SE E NOTE 2) LU.LU.LL+I..LL'l':--+-'I'u.LLLL'uu'

0ERROR, BUSY. LU.I1'---+..JI'(J.J.I..LLUF1......._..J
(SEE NOTE 2)

NOTES: 1. PCLK indicates which processor cycle phase will occur on the
next eLK. PCLK may not indicate the correct phase until the first
cycle is performed.

NOTE: When RESET meets the setup time shown, the next elK will start or
repeat cp2 of a processor cycle.

2. These Inputs are asynchronous. The setup and hold times
shown assure recognition for testing purposes.

EXITING AND. ENTERING HOLD
BUS CYCLE TYPE
CLK
HLOA _ _ _+",1

....,

i

u
'":i!:

IF NPX TRANSFER

...J/

PCLK _ _ _

\ ___...J/

NOTES: 1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.
2. The data bus will be driven as shown if the last cycle before T,ln the diagram was a write TC'
3. The 80C286/883 puts its status pins in a high impedance logic one state during TH'
4. For HOLD request set up to HLDA, refer to Figure 29.
5.

"B"H'E and LOCK are driven at this time but will not become valid until TS.

6. The data bus will remain in a high impedance state if a read cycle Is performed.

4-14

80C286/883
Waveforms

(Continued)
80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY

MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER 110 PORT
ADDRESS OOFA(H) IF MEMORY TO PROC. EXT. TRANSFER

A23 - AO

M/iD, COO INTA

PEREO
ASSUMING WORD-ALIGNED MEMDRY OPERAND. IF ODD ALIGNED. BOCZB6/BB3 TRANSFERS TO/FROM MEMORY BYTE-AT-A-TIME WITH TWO MEMORY CYCLES.
NOTES: 1. PEACK always goes active during tho first bus operation of a processor extension data operand transfer sequence. The first bus operation will be
either a memory read at operand address or 1/0 rBad at port address OOFA(H).
2. To prevent a second processor extension data operand transfer, the worst caso maximum time.(Shown above) is 3 x CD - 12Amax. - @)min. The
actual, configuration dependent, maximum time is: 3 x CD - 12~max. -@min. +N x 2 x CD. N is the number of extra TC slates added to either the
first or second bus operation of the processor extension data operand transfer sequence.

'"a:o
'"
'"
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oc..>

INITIAL 80C286/883 PIN STATE DURING RESET

BUS CYCLE TYPE

~1~

VCH
ClK

RESET

rl

~~__~~~~~~~~__________+-____~____(_SE~E~:~QD
--~~----~--------t

~.so ----------------------------+-----------~~~~r_--------~j~--------

PifI\cK ____________~U~NK~N~O~W~N~____~~----------+_--_1

AZ3- AU ------------~~~~----_+----------_+----_r--~--~~~-------BIHE ____________~U~N_KN~O~W_N~____~~----------+_----+_--JI

M/W------------~~~------~--------_+----_r~

COD/lNTA ____________~U~N~K~NO~W~N~____~~----------+_----+_--~----~~---------

lOCK ____________~U~N~K~N~OW~N~____~~------------__1

HlOA

NOTES: 1. Setup time for RESET

UNKNOWN

t

SI

may be violaled with the consideration that cl>1 of the processor clock may begin one system elK period laler.

2. Setup and hold times for RESET

t

must be met for proper operation. but RESET

t

3. The data bus is only guaranteed to be in a high impedance state at the time shown.

4-15

may occur during 4»1 or 412.

::;:0
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a:
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:E

80C286/883
Burn-In Circuit
80C286/883 PGA
F5
F4
F3
VDD
VSS

RI
RI
RO
RO

RI

RI

AI

AI

RI

AI RI RI RI

AI

RI RI RI RI

AI

RII

52 5 1 50 49 4847 4645 44 43 42 41 40 39 38 37 363534

RO

53

33

RO

54
55

32

58
59

26

RO

60
61

25

RO

24

RO

62
63

23

RO

22

RO

56
AI

57

RI~
RI
~

RI
~

AI

RI~

64

~

RO

31
30
29
28
27

RO

65

RO

66

RO

67

RO

68

1

\.

2

3

4

5

6

7

8 9

RC
RI

Cl

21

RO

20

RO

19

RO

18
10 11 12 13 14 15 16 17

RO

VSS

:=

0

II:

NOTES: 1. Supply Vollage
VDD = 5.5V
VSS =O.OV
2. Input Voltage limits
VIL (Maximum) - O.BV
VIH (Minimum) = 2.0V

3. Component Values
RC = lkll ±5%
RI = 10kll ±5%
RO = Two Series 2.7kll ±5%
4. Capacitor Values
C1 = 0.1 Microfarads

0

II:

0

II:

0

II:

0

II:

0

II:

0

II:

0

II:

F7 RO
RO

GND
5.5V>--~

FO

0

II:

0

II:

0

II:

0

II:

0

II:

0

II:

0

II:

0

II:

VDD

5. Oven Type and Frequency Requirements

Wakefield Oven Board 10 = 100kHz, 13
14 = 6.25kHz, 15 - 3.125kHz, 17 - 7Bl.25Hz.

12.5kHz,

6. Special Requirements
(a) ELECTROSTATIC
DISCHARGE
SENSITIVE.
Proper
Precautions Must be Used When Handling Units.
(b) All Power Supplies Musl be al Zero Volts When the Boards

are Inserted Into the Ovens.
(c) When Powering Up, the Inputs Mustbe Held Below theVDD
Voltage.
(d) If an Excessive Current is Indicated at Final Inspection,
Check to See if a Part is Inserted Backwards or is Latched
,U~
.

4-16

80C286/883
Metallization Topology
DIE DIMENSIONS:
315 x 320 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 8kA

DIE ATTACH:
Material: Si-Au Eutectic Alloy
Temperature: Ceramic PGA - 420 0 C (Max)
WORST CASE CURRENT DENSITY: 2 x 105A/cm 2
LEAD TEMPERATURE (10 Seconds Soldering):

::s. 300 0 C

GLASSIVATION:
Type: Nitrox
Thickness: 10kA

Metallization Mask Layout
80C286/883

en

a:
o

en
en

W
en
0<..)

:=0
c..>g:
o

a:

~

:=

4-17

80C286/883
Packaging t
68 PIN GRID ARRAY (PGA)

r-----::::: ==LI
~
o @0

Bse

@ 0 0 0 0 lor+-+--,
@0000@00@
00
00
00
00
00
00
1.000
00
00
Bse
00
00
00
00
00
00
0@0000000@o

D

1.140
1.160

0.080 MAX

La.ool

LEAD MATERIAL: Type B
LEAD FINISH: Type C
PACKAGE MATERIAL: Multilayer Ceramic 90% Alumina
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 320 0 C ± 100 C
Method: Furnace Braze

NOTE: All Dimensions are

~

.090

I

Dimensions are in inches.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-5

tMil-M-38510 Compliant Materials, Finishes, and Dimensions.

4-18

Em HARRIS
DESIGN INFORMATION

80C286
High Performance Microprocessor
With Memory Management and Protection

The information contained in this section has been developed through characterization by Harris Semiconductor and is
for use as application and design data only. No guarantee is implied.

FuncuonalDescripuon
Introduction

Static Operation

The Harris 80C286 microprocessor is a static CMOS version
of the NMOS 80286 microprocessor. The 80C286 is an
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking
systems. Depending on the application, the 80C286·s
performance is up to fifteen times faster than the standard
5MHz 8086's, while providing complete upward software
compatibility with Harris 80C86 and 80C88 CPU family.

The 80C286 is comprised of completely static circuitry.
Internal registers, counters, and latches are static and
require no refresh as with dynamic circuit design. This
eliminates the minimum operating frequency restriction
typically placed on microprocessors. The CMOS 80C286
can operate from DC to the specified upperfrequency limit.
The clock to the processor may be stopped at any point
(either phase one or phase two of the processor clock
cycle) and held there indefinitely. There is, however, a
significant decrease in power requirement if the clock is
stopped in phase two ofthe processor clock cycle. Details
on the clock relationships will be discussed in the Bus
Operation section. The ability to stop the clock to the
processor is especially useful for system debug or power
critical applications.

The 80C286 operates in two modes: 80C286 real address
mode and protected virtual address mode. Both modes
execute a superset of the 80C86 and 80C88 instruction
set.
In 80C286 real address mode programs use real addresses
with up to one megabyte of address space. Programs use
virtual addresses in protected virtual address mode, also
called protected mode. In protected mode, the 80C286
CPU automatically maps 1 gigabyte of virtual addresses
pertask into a 16 megabyte real address space. This mode
also provides memory protection to isolate the operating
system and ensure privacy of each tasks' programs and
data. Both modes provide the same base instruction set,
registers and addressing modes.
The Functional Description describes the following: Static
operation, the base 80C286 architecture common to both
modes, 80C286 real address mode, and finally, protected
mode.

The 80C286 can be single-stepped using only the CPU
clock. This state can be maintained as long as necessary.
Single step clock information allows simple interface
circuitry to provide critical information for system debug.
Static design also allows very low frequency operation
(down to DC). In a power critical situation, this can provide
low power operation since 80C286 power dissipation is
directly related to operating frequency. As the system
frequency is reduced, so is the operating power until,
ultimately, with the clock stopped in phase two of the
processor clock cycle, the 80C286 power requirement is
the standby current (5mA maximum).

4-19

en
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o

en
en
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OU

:;;0

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::s

80C286

DeSIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

80C286 Base Architecture
The SOCS6. SOCSS. and' SOC2S6 CPU famiiy all contain
the same basic set of registers. instructions. and addressing modes. The SOC2S6 processor is upwardly compatible with the SOCS6 and SOCSS CPU·s.

GENERAL REGISTERS: Eight lEi-bit general purpose
registers used to contain arithmetic and logical operands.
Four of these (AX.
CX and DX) can be used either in
their entirety as 16-bit words or split into pairs of separate
S-bit registers.

ax.

Register Set
The SOC2S6 base architecture has fifteen registers as
shown in Figure 1. These registers are grouped into the
following four categories;

SPECIAL
REGISTER
FUNCTIONS

16·BIT
REGISTER
NAME
07

BYTE
ADDRESSABLE
(B·BIT
REGiSTER
NAMES
SHOWN)

AX

AH

AL

OX

DH

DL

cx

CH

CL

BX

BH

BL

1

SEGMENT REGISTERS: Four 16-bit special purpose
registers select. at any given time. the segments of
memory that are immediately addressable for code. stack
and data. (For usage. refer to Memory Organization.)

BP
Sl
01

O}
)

}
}
)

SP

15

MULTIPLY/DIVIDE
VO INSTRUCTIONS

cs
os

LOOPISHIFTIREPEAT COUNT

SS

0

~ CODE SEGMENT SELECTOR
DATA SEGMENT SELECTOR
STACK SEGMENT SELECTOR

ES

EXTRA SEGMENT SELECTOR

BASE REGISTERS
SEGMENT REGISTERS
15

INDEX REGISTERS

°

F§FLAGS
STACK POINTER

15

. IP

INSTRUCTION POINTER

MSW

MACHINE STATUS WORD

GENERAL
REGISTERS

STATUS AND CONTROL
REGISTERS

FIGURE 1. REGISTER SET

4-20

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

STATUS FLAGS.

C'RRY~~~n
z:,:~
I 1.

PARITY
AUXILIARY CARRY

OVERFLOW - - - - ,
15

14

13

FLAGS,I\\\\IJ NT I

hl 10 9
h 6
10"' I OF I DF I " I TF I SF I ZF I\\\\'J
12

II

J
..

AF

3

I\\\\'J PF I\\\\'J CF I

CONTROL FLAGS'

lJ::~TRAPFLAG
DIRECTION FLAG

INTERRUPT ENABLE

SPECIAL FIELDS'

L__~============

110
PRIVILEGE
LEVEL
NESTED
TASK FLAG

,

M~,~~~~~~~~\~~~~1\'~~~'~\\~~~1~~\~'~1~~~~\~~Y~~~S[~~TS~~IE~.~
I.~p~
Ip~EJI
TASK SWITCH

RESERVED

PROCESSOR
EXTENSIONEXTENSION
EMULATED
MONITOR PROCESSOR

~

I

====~~_J

PROTECTION ENABLE

FIGURE 2. STATUS AND CONTROL REGISTER BIT FUNCTIONS

BASE AND INDEX REGISTERS: Four of the general purpose
registers may also be used to determine offset addresses
of operands in memory. T~ese registers may contain base
addresses or indexes to particular locations within a
segment. The addressing mode' determines the specific
registers used for operand address calculations.
STATUS AND CONTROL REGISTERS: Three 16-bitspecial
purpose registers record or control certain aspects of the
80C286 processor state. These include the Flags register
and Machine Status Word register shown in Figure 2, and

the Instruction Pointer, which contains the offset address
of the next sequential instruction to be executed.
Flags Word Description
The Flags word (Flags) records specific characteristics of
the result of logical and arithmetic instrucitohs (bits 0, 2,
4, 6, 7 and 11) and controls the operation of the 80C286
within a given operating mode (bits 8 and 9). Flags is a 16bit register. The function of the flag bits is given in
Table A.

TABLE A. FLAGS WORD BIT FUNCTIONS

BIT POSITION

NAME

0

CF

Carry Flag -:- Set on high-order bit carry or borrow; cleared otherwise

2

PF

Parity Flag - Set if low-order 8-bits of result contain an even number of 1-bits;
cleared otherwise

4

AF

Set on carry from or borrow to the low order four bits of AL; cleared oth'eiwise

6

iF

Zero Flag -

Set if result is zero; cleared otherwise

7

SF

Sign Flag -

Set equal to high-order bit of result (0 if positive, 1 if negative)"

11

OF

Overflow Flag - Set if result'is a too-large positive number or a too-small negative
number (excluding sign-bit) to fit in destination operand; cleared otherwise

8

TF

Single Step Flag - Once set, a single step interrupt occurs after the next instruction
executes. TF is cleared by the single step interrupt.

9

IF

Interrupt-enable Flag - When set, maskable interrupts will cause the CPU to transfer
control to an interrupt vector specified location

10

DF

Direction Flag - Causes string instructions to auto' decrement the appropriate index
registers when set. Clearing DF causes auto increment.
.

FUNCTION

4-21

~

o

en
en
en'"
oc.>

:;;0
c.>g:
o
a:
c.>

:E

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Instruction Set
The instruction set is divided into seven categories: data
transfer, arithmetic, shiftsrotateslogical, string manipulation, control transfer, high level instructions, and processor control. These categories are summarized in
Figure 3.

Two-operand instructions (e.g. MOVand ADD) are usually
three to six bytes long. Memory to memory
operations are provided by a special class of string
instructions requiring one to three bytes. For detailed
instruction formats and encodings refer to the instruction
set summary at the end of this document.

An 80C286 instruction can reference zero, one, or two
operands; where an operand may reside in a register, in
the instruction itself. or in memory. Zero-operand instructions (e.g. NOP ane HlT) are usually one byte long. Oneoperand instructions (e.g. INC and DEC) are usually two
bytes long but some are encoded in only one byte. Oneoperand instructions may reference a register or memory
location. Two-operand instructions permit the following
six types of instruction operations:
•
•
•

Register to Register
Memory to Register
Immediate to Register

•
•
•

ADDITION
ADD
ADC
INC
AAA
DAA

Memory to Memory
Register to Memory
Immediate to Memory

Add byte or word
Add byte or word with carry
Increment byte or word by 1
ASCII adjust for addition
Decimal adjust for addition

SUBTRACTION
SUB

Subtract byte or word
Subtract byte or word with borrow
Decrement byte or word by 1
Negate byte or word

MOV

Move byte or word

SBB
DEC
NEG

PUSH

Push word onto stack
Pop word off stack

CMP
AAS -

Push all registers on stack
Pop all registers from stack

DAS

Compare byte or word
ASCII adjust for subtraction
Decimal adjust for subtraction

Exchange byte or word

MUL
IMUL

Multiply byte or word unsigned
Integer multiply byte or word

AAM

ASCII adjust for multiply

DtV

Divide byte or word unsigned

tDIV

tnteger divide byte or word
ASCII adjust for division

GENERAL PURPOSE

POP
PUSHA
POPA
XCHG
XLAT

MULTIPLICATION

Translate byte

INPUT/OUTPUT
IN

DIVISION

Input byte or word
Output byte or word

OUT

ADDRESS OBJECT
LEA
LDS
LES

I

AAD
CBW
CWD

Load effective address
Load pOinter using DS
Load pointer using ES

FLAG TRANSFER
-LAHF
SAHF
PUSHF
POPF

FIGURE 3B. ARITHMETIC INSTRUCTIONS

Load AH register from flags
Store AH register in flags
Push flags onto stack
Pop flags off stack

LOGICALS
NOT
AND

FIGURE 3A. DATA TRANSFER INSTRUCTIONS
MOVS
INS

Move byte or word string
Input bytes or word string

OUTS
CMPS
SCAS
LODS

Output bytes or word string

STOS

Repeat·
Repeat '!'hile equal/zero
Repeat while Dot equaUnot zero

"Exclusive or" byte or word
"Test" byte or word

SHIFTS
SHUSAL
SHR
SAR

L
l
I

Shift logical/arilhmetic left byte or word
Shift logical right byte or word
Shift arithmetic right bYte or word

ROTATES

Load byte or word string
Store byte or word string

REPElREPZ
REPNEIREPNZ

"Not" byte or word
"And" byte or word
"Inclusive or" byte or word

OR
XOR
TEST

Compare byte or word string
Scan byte or word string

REP

Convert byte to word
Convert word to doubleword

ROL
ROR
RCL
RCR

- FIGURE 3C. STRING INSTRUCTIONS-

Rotate left byte or word
Rotate right byte or word
Rotate through carry left byte or word
Rotate through carry right byte or word

FIGURE 3D. SHIFT/ROTATE LOGICAL INSTRUCTIONS

4-22

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

JAlJNBE
JAEIJNB

CONDITIONAL TRANSFERS
Jump If above/not below nor equal

UNCONDITIONAL TRANSFERS
Call procedure
Return from procedure
Jump

Jump If above or equaVnot below

CALL
RET

JBIJNAE
JBEIJNA

Jump If below/not above nor equal

JMP

JC
JEIJZ
JGIJNLE

Jump It carry
Jump If greater/not less nor equal

LOOP

Loop

JGElJNL

Jump if greater orequallnolless

Loop If equal/zero

JUJNGE
JLEIJNG

Jump If less/not greater nor equal

LOOPElLOOPZ
LOOPNEILOOPNZ

Jump it less or equallnot greater

JCXZ

Jump If register ex

JNC
JNElJNZ

Jump If not carry

JNO
JNPIJPO

Jump If not overflow

Jump il not panty/panty odd

tNT

Interrupt

JNS

Jump If not Sign

Interrupt If overfloW

JO
JP/JPE

Jump It overflow

INTO
IRET

JS

Jump if sign

Jump If below or equal/not above

ITERATION CONTROLS

Jump if equaVzero

Loop If not equal/not zero

-a

INTERRUPTS

Jump If not equaVnol zero

Interrupt relurn

Jump if parity/parity even

FIGURE 3E. PROGRAM TRANSFER INSTRUCTIONS

FLAG OPERATIONS
STC

Set carry lIag

CLC

Clear carry lIag

CMC

Complement carry lIag

STD

Set direction Ilag

CLD

Clear direction flag

STI

Set interrupt enable lIag

CLI

Clear interrupt enable lIag
EXTERNAL SYNCHRONIZATION

HLT

Halt until interrupt or reset
Wait lor TEST pin active

WAIT

ESC

Escape to extension processor
Lock bus during next instruction

LOCK

NO OPERATION
NOP

I

No operation

 limit
Data segment may not be wrlnen mto.
Data segment may, be wnnen mto.

3
2

Executable (E)
Conformmg (e)

E - 1
C ~ 1

1

Readable (A)

A ~O
A = 1

Code Segment DescrIptor type IS:
Code segment may only be executed
when CPL 2 DPL and CPL
remains unchanged.
Code segment may not be read
Code .segment may be read.

0

Accessed (A)

A-O

3
2

Type
Field
DefinitIOn

Segment priVilege attribute used In priVilege tests

Executable (E)
Expansion Dlrectlon(ED)
Wnteable (W)

4

A"'" 1

II

}

Data
Segment
(S ~ 1,
E ~ 0)

II
Code
Segment

1

(S ~ I,
E ~ 1)

Segment has not been accessed.
Segment selector ha& been loaded Into segment register
or used by selector test Instructions.

FIGURE 10.CODE AND DATA SEGMENT DESCRIPTOR FORMATS

4-30

7

tMust be set to 0 for compatablhty with future upgrades.

Function

Name

BASE 23-16

+3

ACCESS RIGHTS BYTE DEFINITION
BII

7
RESERVED-

+7

+6
+4

+2

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
.
SYSTEM SEGMENT DESCRIPTOR

Code and data (including stack data) are stored in two
types of segments: code segments and data segments.
Both types are identified and defined by segment descriptors
(S = 1). Code segments are identified by the executable (E)
bit setto 1 in the descriptor access rights byte. The access
rights byte of both code and data segment descriptor types
have three fields in common: present (P) bit, Descriptor
Privilege Level (DPL), and accessed (A) bit. If P = 0, any
attempted use of this segment will cause a not-present
exception. DPL specifies the privilege level of the segment
descriptor. DPLcontrols when the descriptor may be used by
a task (refer to privilege discussion below). The A bit shows
whether the segment has been previously accessed for usage
profiling, a necessity for virtual memory systems. The ·CPU
will always set this bit when accessing the descriptor.

o
+5

P

I II
OPL

A code segment (S = 1, E = 1) may be execute-only or
execute/read as determined by the Readable (R) bit. Code
segments may never be written into and execute-only
code segments (R = 0) may not be read. A code segment
may also have an attribute called conforming (C). A
conforming code segment may be shared by programs
that execute at different privilege levels. The DPL of a
conforming code segment defines the range of privilege
levels .at which the segment may be executed (refer to
privilege discussion below). The limit field identifies the
last byte of a code segment.
System Segment Descriptors (S

=

0, Type

=

1-3)

In addition to code and data segment descriptors, the protected mode SOC2S6 defines System Segment Descriptors.
These descriptors define special system data segments
which contain a table of descriptors (Local Descriptor
Table Descriptor) or segments which contain the execution
state of a task (Task State Segment Descriptor).
Figure 11 gives the formats for the special system data
segment descriptors. The descriptors contain a 24-bit
base address of the segment and a 16-bit limit. The
access byte defines the type of descriptor, its state and
privilege level. The descriptor contents are valid and the
segment is in physical memory if P = 1. If P = 0, the segment
is not valid. The DPL field is only used in Task State Segment
descriptors and indicates the privilege level at which the
descriptor may be used (see Privilege). Since the Local
DescriptorTable descriptor may only be used by a special
privileged instruction, the DPLfieid is not used. Sit4 ofthe
access byte is 0 to indicate that it is a system control
descriptor. The type field specifies the descriptor type as
indicated in Figure 11 .

I

TYPE

0

+6
BASE 23~16

+3

BASE 15-0

+1

LIMIT 15-0

•

15

+4
+2

7

-Must be set to 0 for compatabillty With future upgrades

SYSTEM SEGMENT DESCRIPTOR FIELDS
Name

Value

TYPE

,

Doscnplorcontentsaronolvalld
Ooscnplorcontantsaro\oahd

0-3

BASE
numbor

LIMIT

OelCrlptlon
Available Task Slale Segment (rss,
Local DascnplOfTabla
Bu!.)' Task Siaia Sogment (TSS)

0

DPL

Data segments (S = 1; E = 0) may be either read-only or
read-write as controlled by the W bit of the access rights
byte. Read-only (W= 0) data segments may not be written
into. Data segments may grow in two directions, as
determined by the Expansion Direction (ED) bit: upwards
(ED = 0) for data segments, and downwards (ED = 1) for a
segment containing a stack. The limit field for a data
segment descriptor is interpreted differently depending
on the ED bit (see Figure 10).

7

RESERVED-

+7

16·bIt
number

Doscnplor PrlVlloge Level
BasoAddf8SSofspoc,alsyslemdala
segment In loal momory

Otfselollaslbytomsogmonl

FIGURE 11. SYSTEM· SEGMENT DESCRIPTOR FORMAT

Gate Descriptors (S

=0, Type =4-7)

Gates are used to control access to entry points within the
target code segment. The gate descriptors are call gates,
task gates, interrupt gates and trap gates. Gates provide a
level of indirection between the source and destination of
the control transfer. This indirection allows the CPU to
automatically perform protection checks and control entry
point of the destination. Call gates are used to change
privilege levels (see Privilege), task gates are used to
perform a task switch, and interrupt and trap gates are
used to specify interrupt service routines .. The interrupt
gate disables interrupts (resets IF) while the trap gate
does not.
Figure 12 shows the format of the gate descriptors. The
descriptor contains a destination pointer that points to
the descriptor of the target segment and the entry point
offset. The destination selector in an interrupt gate, trap
gate, and call gate must referto a code segment descriptor.
These gate descriptors contain the entry point to prevent
a program from constructing and using an illegal entry
point. Task gates may only refer to a task state segment.
Since task gates invoke a task switch, the destination
offset is not used in the task gate.
Exception 13 is generated when the gate is used if a
destination selector does not refer to the correct descriptor
type. The word count field is used in the call gate descriptor
to indicate the number of parameters (0-31 words) to be
automatically copied from. the caller's stack to the stack of
the called routine when a control transfer changes privilege
levels. The word count field is not used by any other
gate descriptor.
The access byte format isthe sameforall descriptors. P= 1
indicates that the gate·contents are valid. P = 0 indicates
the contents are not valid and causes exception 11 if
referenced. DPL is the descriptor privilege level and
specifies when this descriptor may be used by a task

4-31

80C286

DESIGN INFORMATION

(Continued)

The Information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only.
guarantee is implied.

No

+6

Only ,segment descriptors may be loaded into segment
descriptor cache registers. Once loaded. all references to
that segment of memory use the cached. descriptor
information instead of reaccessing the descriptor. The
descriptor cache registers are not visible to programs. No
instructions exist to store their contents. They only change
when a segment register is loaded.
.

+4

Selector Fields,

(refer to privilege discussion below). Bit4 must equal 0 to
indicate a system control descriptor. The type field
specifies the descriptor type as indicated in Figure 12.
GATE DESCRIPTOR

a

7

RESERVEO*

+7

ploPLlal

+5

+3

TYPE

I ,I
X X

X

DESTINATION SELECTOR

+1

WORD
COUNT 4-0

15~O

Ix

X

+2

DESTINATION OFFSET 15-0

15

8 7

-Must be set to 0 for compatibility with future upgrades

GATE DESCRIPTOR FIELDS·
Name

Value

4

-call Gate
-Task Gate
-Interrupt Gats
-Trap Gate

5

TYPE

Description

A protected mode selector has three fields: descriptor
entry index. local or global descriptor table indicator (TI).
and selector privilege (RPL) as shown in Figure 14. These
fields select one of two memory based tables of descriptors.
select the appropriate table entry and allow high-speed
testing of the selector's privilege attribute (refer to privilege
discussion below).

6
7

REQUESTED

P

0

DPL'

0-3

Descriptor Privilege Level

0-31

Number 01 words to copy
from callers stack to ca!led
procedures stack. Only used
with call gate,

-Descriptor Contents are not
valid
-Descriptor Contents are
valid

1

WORD
COUNT

DESTINATION
SELECTOR

seleclor

DESTINATION
OFFSET

offset

16·bit

16·bit

Selector to Iha targs! code
segment (Call. Interrupt or
Trap Gate)
Selector to the target task
state segment (Task Gate)
Entry point within the target
code segment

FIGURE 12 .. GATE DESCRIPTOR FORMAT

Segment Descriptor Cache Registers
A segment descriptor cache register is assigned to each
oHhe four segment registers (CS. SS. OS. ES). Segment
descriptors are 'automatically loaded (cached) into a
segment descriptor cache register (Figure 13) whenever
the associated segment register is loaded with a selector:

PRIVILEGE
LEVEL
CRPL)

,n,

TI

IHOICATOR
TI

~ IIUSEGLOBALOESCRIPTORTASLE
(GOT)
- 1 USE LOCAL DESCRIPTOR TABLE
(LOT)

FIGURE 14. SELECTOR FIELDS

Local and Global Descriptor Tables
Two tables of descriptors. called descriptor tables. contain
all descriptors accessible by a task at any given'time. A
descriptortilble is a,lineararray of up to 8192 descriptors.
The upper 13 bits of the selector value are an index into a
descriptor table. Each table has a 24-bit base register to
locate the descriptor"table in physical memory and a 16bit limit register that confine descriptor access to the
defined limits of the table as shown in Figure 15. A restartable
exception (13) will occur if an attempt is made to reference
a descriptor outside the table limits.
MEMORV

:E:j
SEGMlEN'f SELECTORS

"'~
Sl.QMENT AIEGlSnRS

IU>AO£O BY PROGRAM)

r ----: - - - -,- -....oGA,;.~siLE - -: - - - - - - -,
I

ACCESS

1

RIGHTS

I
SEGMENT flHVSICAL BASE

J J.
I.
I

AODftESS

J.

SEGMENT SIlE

RGIIIENT DDCRIfITOR CoICHE REGIIRRS

I,.

I
I

L ______ ~~~~~ ________ J

FIGURE 13. DESCRIPTOR CACHE REGISTERS

FIGURE 15. LOCAL AND GLOBAL DESCRIPTOR TABLE
DEFINITION

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
One table. called the Global Descriptor table (GOT). contains
descriptors available to all tasks. The other table. called the
Local DescriptorTable (LOT). contains descriptors that can
be private to a task. Each task may have its own private LOT.
The GOT may contain all descriptor types except interrupt
and trap descriptors. The LOT may contain only segment.
task gate. and call gate descriptors. A segment cannot be
accessed by a task if its segment descriptor does not exist
in either descriptor table at the time of access.
The LGDT and LLDT instructions load the base and limit of
the global and local descriptor tables. LGDT and LLDTare
privileged. i.e. they may only be executed by trusted programs
operating at level O. The LGDT instruction loads a six byte
field containing the 16-bit table limit and 24-bit physical
base address of the Global Descriptor Table as shown in
Figure 16. The LOT instruction loads a selector which refers
to a Local DescriptorTable descriptor containing the base
address and limit for an LOT. as shown in Figure 11.
o

ENfORCED

+2

+3

BASE 15-0
LIMIT 15-0

•

'5

SOfTWARE
INTERFACES

+4

BASE 23-16

+'
·Must be set to

Tasks. descriptors. and selectors have a privilege level
attribute that determines whether the descriptor may be
used. Task privilege affects the use of instructions and
descriptors. Descriptor and selector privilege only affect
access to the descriptor.

""

7

I

RESERVEO·

+5

which controls the use of privileged instructions and access
to descriptors (and their associated segments) within a task.
Four-level privilege. as shown in Figure 18. is an extension
ofthe users supervisor mode commonly found in minicomputers. The privilege levels are numbered 0 through 3.
Level 0 is the most privileged level. Privilege levels provide
protection within a task. (Tasks are isolated by providing
private LOTs for each task.) Operating system routines.
interrupt handlers. and other system software can be included
and protected within the virtual address space of each task
using the four levels of privilege, Each task in the system
has a separate stack for each of its privilege levels.

tllGHSPHO
OPERATING
SYSlEM
INYUlfACE

7

a for compatabillty with future upgrades

FIGURE t6. GLOBAL DESCRIPTOR TABLE AND
INTERRUPT DESCRIPTOR TABLE DATA TYPE

Interrupt Descriptor Table

NOTE: PL becomes numerically lower as privilege level Increases

The protected mode 80C286 has a third descriptor table.
called the Interrupt DescriptorTable (lOT) (see Figure 17).
used to define up to 256 interrupts. It may contain only
task gates. interrupt gates and trap gates, The lOT
(Interrupt DescriptorTable) has a 24-bit physical base and
16-bit limit register in the CPU. The priviledged LlDT
instruction loads these registers with a six byte value of
identical form to that of the LG DT instruction (see Figure
16 and Protected Mode Initialization),
MEMORY

INTERRUPT#n

lNTERRUPT#n-l

"CPU

I

0

I

-~J

INTERRUPT

GATE FOR
INTERRUPT#l

TA8LE
(tDTI

GATE FOR
INTERRUPT#O

FIGURE 18. HIERARCHICAL PRIVILEGE LEVELS

Task Privilege
A task always executes at one of the four privilege levels.
The task privilege level at any specific instant is called the
Current Privilege Leve!" (CPL) and is defined by the lower
two bits of the CS register. CPL cannot change during
execution in a single code segment. A task's CPL may only
be changed by control transfers through gate descriptors
to a new code segment (See Control Transfer). Tasks
begin executing at the CPL value specified by the code
segment selector within TSS when the task is initiated via
a task switch operation (See Figure 19), A task executing
at Level 0 can access all data segments defined in the GOT
and the task's LOT and is considered the most trusted
level. A task executing a Level 3 has the most restricted
access to data and is considered the least trusted level.
Descriptor Privilege

lOT BASE

FIGURE 17. INTERRUPT DESCRIPTOR TABLE DEFINITION

References to lOT entries are made via INT instructions.
external interrupt vectors. or exceptions. The lOT must be at
least 256 bytes in size to allocate space for all reserved
interrupts,
Privilege
The 80C286 has a four-level hierarchical privilege system

4-33

Descriptor privilege is specified by the Descri ptor Privilege
Level (DPL) field of the descriptor access byte. DPL
specifies the least trusted task privilege level (CPL) at
which a task may access the descriptor, Descriptors with
DPL = 0 are the most protected. Only tasks executing at
privilege level 0 (CPL = 0) may access them. Descriptors
with DPL = 3 are the least protected (i.e. have the least
restricted access) since tasks can access them when
CPL = O. 1. 2. or 3), This rule applies to all descriptors.
except LOT descriptors.

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
TABLE I. DESCRIPTOR TYPES USED FOR CONTROL TRANSFER
CONTROL TRANSFER TYPES
Intersegment within the same privilege levels
Intersegment to the same or higher privilege
level Interrupt within task may change CPL.

. Intersegment to a lower privilege level
(changes task CPL)
Task Switch

NT (Nested Task bit of flag word) - 0

..

NT (Nested Task bit of flag word)

OPERATION TYPES

DESCRIPTOR
REFERENCED

DESCRIPTOR
TABLE

JMP. CALL. RET. IRET·

Code Segment

GDT/LOT

CALL

Call Gate

GOT/LOT

Interrupt Instruction,

Trap or Interrupt

lOT

Exception Extemal Interrupt
RET,IRET·

Gate
Code Segment

GOT/LOT

CALL, JMP

Task State Segment

GOT

CALL, JMP

Task Gate

GOT/LOT

IRET··
Interrupt Instruction,
Exception External Interrupt

Task Gate

lOT

1

Selector Privilege
Selector privilege is specified by the Requested Privilege
Level (RPL) field in the least significant two bits of a selector.
Selector RPL may establish a less trusted privilege level
than the current privilege level for the use of a selector.
This level is called the task's effective privilege level (EPL).
RPL can only reduce the scope of a task's access to data
with this selector. A task's effective privilege is the numeric
maximum of RPLand CPL. A selector with RPL=O imposes
no additional restriction on its use while a selector with
RPL = 3 can only refer to segments at privilege Level 3
regardless ofthe task's CPL. RPLis generally used to verify
that pointer parameters passed to a more trusted procedure
are not allowed to use data at a more privileged level than
the caller (refer to pointer testing instructions).
Descriptor Access and Privilege Validation
Determining the ability of a task to access a segment
involves the type of segmentto be accessed, the instruction
used, the type of descriptor used and CPL, RPL, and DPL.
The two basic types of segment accesses are control
transfer (selectors loaded into CS) and data (selectors
loaded into OS, ES or SS).
Data Segment Access
Instructions that load selectors into OS and ES must refer
to a data segment descriptor or readable code segment
descriptor. The CPL ofthe task and the RPL ofthe selector
must be the same as or more privileged (numerically equal
to or lower than) than the descriptor DPL. In general, a task
can only access data segments atthe same or less privileged
levels than the CPL or RPL. (whichever is numerically
higher) to prevent a program from accessing data it cannot
be trusted to use.
An exception to the rule is a readable conforming code
segment. This type of code segment can be read from any
privilege level.

If the privilege checks fail (e.g. DPL is numerically less
than the maximum of CPL and RPL) or an incorrect type of
descriptor is referenced (e.g. gate descriptor or execute
only code segment) exception 13 occurs. If the segment
is not present, exception 11 is generated.
Instructions that load selectors into SS must refer to data
segment descriptors for writable data segments. The
descriptor privilege (DPL) and RPL must equal CPL. All
other descriptor types or a privilege level violation will
cause exception 13. A not present ·fault causes exception 12.
Control Transfer
Four types of control transfer can occur when a selector is
loaded into CS by a control trimsfer operation (see Table
I). Each transfer type can only occur ifthe operation which
loaded the selector references the correct descriptor type.
Any violation of these descriptor usage rules (e.g. JMP
through a call gate or RET to a Task State Segment) will
cause exception 13.
The ability to reference a descriptor for control transfer is
also subjectto rules of privilege. A CALL or JUMP instruction
may only reference a code segment descriptor with DPL
equal to the task CPLor a conforming segment with DPLof
equal or greater privilege than CPL. The RPL of the selector
used to reference the code descriptor must have as much
privilege as CPL.
RET and IRET instructions may only reference code segment
descriptors with descriptor privilege equal to or less
privileged than the task CPL. The selector loaded into CS
is the return address from the stack. After the return, the
selector RPLis the task's new CPL. If CPL changes, the old
stack pointer is popped after the return address.
When a JMP or CALL references a Task State Segment
descriptor, the descriptor DPL must be the same or less
privileged than the task's CPL. Reference to a valid Task

4-34

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
State Segment descriptor causes a task switch (see Task
Switch Operation). Reference to a Task State Segment
descriptor at a more privileged level than the task's CPL
generates exception 13.
When an instruction or interrupt references a gate descriptor,
the gate DPL must have the same or less privilege than the
task CPL. If DPL is at a more privileged level than CPL.
exception 13 occurs. 1ft he destination selector contained
in the gate references a code segment descriptor, the
code segment descriptor DPL must be the same or more
privileged than the task CPL. If not, Exception 13 is issued.
After the control transfer, the code segment descriptors
DPL is the task's new CPL. Ifthe destination selector in the
gate references a task state segment, a task switch is
automatically performed (see Task Switch Operation).
The privilege rules on control transfer require:
~ JMP or CALL direct to a code segment (code segment
descriptor) can only be a conforming segment with
DPL of equal or greater privilege than CPL or a nonconforming segment at the same privilege level.
~ interrupts within the task, or calls that may change
privilege levels, can only transfer control through a
gate at the same or a less privileged level than CPL to a
code segment at the same or more privileged level
than CPL.
~ return instructions that don't switch tasks can only
return control to a code segment at the same or less
privileged level.
~ task switch can be performed by a call, jump or interrupt
which references either a task gate ortask state segment
at the same or less privileged level.
Privilege Level Changes

For subroutine calls that pass parameters on the stack and
cross privilege levels, a fixed number of words, as specified
in the gate, are copied from the previous stack to the
current stack. The inter-segment RET instruction with a
stack adjustment value will correctly restore the previous
stack pointer upon return.
Protection
The 80C286 includes mechanisms to protect critical
instructions that effect the CPU execution state (e.g. HLT)
and code or data segments from improper usage. These
protection mechanisms are grouped into three forms:
~

~
~

These checks are performed for all instructions and can be
split into three categories: segment load checks (Table J),
operand reference checks (Table K), and privileged
instruction checks (Table L). Any violation of the rules
shown will result in an exception. A not-present exception related to the stack segment causes exception 12.
The IRET and POPF instructions do not perform some of
their defined functions if CPL is not of sufficient privilege
(numerically small enough). Precisely these are:
~

Any control transfer that changes CPL within the task,
causes a change of stacks as part of the operation. Initial
values of SS:SP for privilege levels 0, 1 , and 2 are kept in
the task state segment (refer to Task Switch Operation).
During a JMP or CALL control transfer, the new stack
pointer is loaded into the SS and SP registers and the
previous stack pointer is pushed onto the new stack.

Restricted usage of segments (e.g. no write allowed to
read-only data segments). The only segments available
for use are defined by descriptors in the Local Descriptor
Table (LDT) and Global Descriptor Table (GDT).
Restricted access to segments via the rules of privilege
and descriptor usage.
Privileged instructions or operations that may only be
executed at certain privilege levels as determined by
the CPL and I/O Privilege Level (IOPL). The 10PL is
defined by bits 14 and 13 of the flag word.

~

The IF bit is not changed if CPL is greater than 10PL.
The 10PL field of the flag word is not changed if CPL is
greater than O.

No exceptions or other indication are given when these
conditions occur.

When returning to the original privilege level, its stack is
restored as part of the RET or IRET instruction operation.

TABLE K OPERAND REFERENCE CHECKS
ERROR DESCRIPTION

Write into code segment
Read from execute-only code segment

TABLE J. SEGMENT REGISTER LOAD CHECKS
ERROR DESCRIPTION
Descriptor table limit exceeded
Segment descriptor not-present
Privilege rules violated

Invalid descriptor/segment type segment
register load:
Read only data segment load to SS
Special control descriptor load to DS.ES,SS
- Execute only segment load to DS, ES. SS
Data segment load to CS
Read/Execute code segment load SS

-

EXCEPTION
NUMBER
13
11 or 12
13

Write to read-only data segment
Segment limit exceeded INote1)

EXCEPTION
NUMBER
13
13
13
12 or 13

NOTE 1. Carry out in offset calculations is ignored.

TABLE L. PRIVILEGED INSTRUCTION CHECKS
ERROR DESCRIPTION

EXCEPTION
NUMBER

CPL ~ D when executing the following
instructions:

LlDT. LLDT. LGDT. LTR. LMSW. CTS. HLT
CPT> IOPL when executing the following
instructions:
INS, IN. OUTS. OUT. STI. CLI. LOCK

13

4-35

13

13

a:
'"
o
'"
'"
"'w

==0
<..>g:
0<">

o

a:
<..>

:s

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
TABLE M. PROTECTED MODE EXCEPTIONS

INTERRUPT
VECTOR

8
9
10
11
12
13

RETURN ADDRESS
AT FALLING
INSTRUCTION?

FUNCTION
Double exception detected
Processor extension segment overrun
Invalid task state segment
Segment not present
Stack segment overrun or stack segment not present
General protection

Yes
No
Yes
Yes
Yes
Yes

ALWAYS
RESTARTABLE?
No (Note 2)
No (Note 2)
Yes
Yes
Yes (Note 1) .
No (Note 2)

ERROR CODE
ON STACK?
Yes
No
Yes
Yes
Yes
Yes

NOTES: 1. When a PUSHA or POPA Instruction attempts to wrap around the stack segment, the machine state after the exception will not be restartable because stack segment wrap around is
not permitted. This condition is identified bV the value of the saved SP being either OOOOIH). 0001 (H). FFFE(H). or FFFFIH).
2. These exceptions indicate a violation to privitege rules or usage rules has occurred. Restart is generally not attempted under tho'se conditions.

Exceptions
The 80C286 detects several types "of exceptions and
interrupts in protected mode (see Table M). Most are
restartable after the exceptional condition is removed.
Interrupt handlers for most exceptions can read an error
code. pushed on the stack after the return address. that
identifies the selector involved (0 if none). The retum
address normally points to the failing instruction. including
all leading prefixes. For a processor extension segment
overrun exception. the return address will not point at the
ESC instruction that caused the exception; however. the
processor extension registers may contain the address of
the failing instruction.
These exceptions indicate a violation to privilege rules or
usage rules has occurred. Restart is generally not attempted
under those conditions.
All these checks are performed for all instructions and can
be split into three categories: segment load checks (Table
J). operand reference checks (Table K). and privileged
instruction checks (Table L). Any violation of the rules
shown will result in an exception. A not-present exception
causes exception 11 or 12 and is restartable.
Special Operations
Task Switch Operation
The 80C286" provides a built-in task switch operation
which saves the entire 80C286 execution state (registers.
address space. and a link to the previous task). loads a
new execution state. and commences execution in the
new task. Like gates. the task switch operation is invoked
by executing an inter-segment JMP or CALL instruction
which refers to a Task State Segment (TSS) or task gate
descriptor in the GOT or LOT. An INT instruction. exception.
or external interrupt may also invoke the task switch
operation by selecting a task gate descriptor in the
associated lOT descriptor entry.
The TSS descriptor points at a segment (see Figure 19)
containing the entire 80C286 execution state while a task
gate descriptor contains a TSS selector. The limit field of
the descriptor must be greater than 002B(H).
Each task must have a TSS associated with it. The current
TSS is identified by a special register in the 80C286 called

the Task Register (TR). This register contains a selector
referring to the task state segment descriptor that defines
the currentTSS. A hidden base and limit register associated
with TR are loaded whenever TR is loaded with a new
selector. The IRET instruction is used to return control to
the task that called the current task or was interrupted. 8it
14 in the flag register is called the Nested Task (NT) bit. It
controls the function of the IRET instruction. If NT=O. the
IRET instruction performs the regular current task by popping
values off the stack; when NT = 1. IRET performs a task
switch operation back to the previous task.
When a CALL. JMP. or INT instruction initiates a task
switch. the old (except for case of JMP) and new TSS will
be marked busy and the back link field of the newTSS set
to the old TSS selector. The NT bit ofthe new task is set by
CALL or INT initiated task switches. An inferruptthat does
not cause a task switch will clear NT. NT may also be set or
cleared by POPF or IRET instructions.
The task state segment is marked busy by changing the
descriptor type field from Type 1 to Type 3. Use of a selector
that references a busy task state segment causes
Exception 13.
Processor Extension Context Switching
The context of a processor extension is not changed by
the task switch operation. A processor extension context
need only be changed when a different task attempts to
use the processor extension (which still contains the context of a previous task). The 80C286 detects the first use
of a processor extension after a task switch by causing the
processor extension not present exception (7). The interrupt handler may then decide whether a context change
is necessary.
Whenever the 80C286 switches tasks. it sets the Task
Switched (TS) bit ofthe MSW. TS indicates that a processor
extension context may belong to a different task than the
current one. The processor extension nut present exception
(7) will occur when attempting to execute an ESC orWAIT
instruction if TS = 1 and a processor extension is present
(MP = 1 in MSW).

4-36

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

CPU

RESERVED

TASK REGISTER

,_~RP==:
I

PROGRAM INVISIBLE

BASE,~·o

~li

123

a

1~:I

AN AVAILABLE TASK STATE
SEGMENT MAY BE USeD AS

THE DESTINATION Of A TASK
SWITCH OPERATION
A BUSY TASK STATE SEGMENT

I

:: I

BASE

p1r_l,ol"_P,EIL..-8'S_'''.''---1

I---

DESCRIPTION

CANNOT BE USED AS THE
DESTINATION OF A TASK

lIMIT,S n

SWITCH

_...J

I jiI

BYTE

rT::-.S"'KC"lO::TC":S::'l::'C=T::OR:---'i0 OFFSET
os SELECTOR

~S=S::S''''l::'C=TO=R:----'

40

P

DESCRIPTION
BASE AND LIMIT FIELDS ARE VALID
SEGMENT IS NOT PRESENT IN

MEMOAY. BASE AND tJMIT ARE NOT
DEFINED

CS SELECTOR

~S"-'- - - - - - - - j "
~s=p--------j
TASK

-STATE
SEGMENT

28

CURRENT

~~!~E

~:-------,::
FLAG WORD

IP(ENTRVPOINTI

Sf FORCPL2
~

_______

SP FOR CPL I

8

INITIAL

6

FOR CPL 0.1.2

~

~S~S::fO=RC":C::Pl~O--------'

STACKS

SPfORCPLO
BACK LINK SELECTOR TO TSS

FIGURE 19. TASK STATE SEGMENT AND TSS REGISTERS

Pointer Testing Instructions
The 80C286 provides several instructions to speed pointer
testing and consistency checks for maintaining system
integrity (see Table N). These instructions use the memory
management hardware to verify that a selector value

refers to an appropriate segment without risking an
exception. A condition flag (ZF) indicates whether use of
the selector or segment will cause an exception.

TABLE N. 80C286 POINTER TEST INSTRUCTIONS

INSTRUCTION OPERANDS
ARPL

Selector.
Register

VERR
VERW
LSL

Selector
Selector
Register.
Selector
Register.
Selector

LAR

FUNCTION
Adjust Requested Privilege Level: adjusts the RPL of the selector to the numeric
maximum of current selector RPL value and the RPL value in the register. Set zero
flag if selector RPL was changed by ARPL.
VERify for Read: sets the zero flag if the segment referred to by the selector can be read.
VERify for Write: sets the zero flag if the segment referred to by the selector can be written.
Load Segment Limit: reads the segment limit into the register if privilege rules and
descriptor type allow. Set zero flag if successful.
Load Access Rights: reads the descriptor access rights byte into the register if privilege
rules allow. Set zero flag if successful.

4-37

80C286

DESIGN INFORMATION

(Continued)

The information contained in this saction has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
Double Fault and Shutdown
If two separate exceptions are detected during a single
instruction- execution, the 80C286 performs the double
fault exception (8). If an exception occurs during processing
oHhe double fault exception, the 80C286 will enter shutdown. During shutdown no further instructions or exceptions
are processed. -Either NMI (CPU remains in protected
mode) or RESET (CPU exits protected mode) can force the
80C286 out of shutdown. Shutdown is externally signalled
via a HALT bus operation with A1 LOW.

mode will force A23-20 LOW whenever CS is used again.
The initial CS:IPvalue of FOOO:FFFO provides 64K bytes of
code space for initialization code without changing CS.
Protected mode operation requires several registers to be
initialized. The GDTand IDT base registers must refer to a
valid GDT and lOT. After executing the LMSW instruction
to set PE, the 80C286 must immediately execute an intrasegmentJMP instruction to clear the instruction queue of
instructions decoded in real address mode.

Protected Mode Initialization
The 80C286 initially executes in real address mode after
RESET. To allow initialization code to be placed at the top
of physical memory, A23-20will be HIGH when the 80C286
performs memory references relative to the CS register
until CS is changed. A23-20 will be zero for references to
the DS, ES, or SS segments. Changing CS in real address

To force the 80C286 CPU registers to match the initial
protected mode state assumed by software, execute a JMP
instruction with a selector referring to the initial TSS used
in the system. This will load the task register, local descriptor
table register, segment registers and initial general register
state. The TR should point at a valid TSS since any task
switch operation involves saving the current task state.

System Interface
The 80C286 system interface appears in two forms: a
local bus and a system bus. The local bus consists of
address, data, status, and control signals at the pins of the
CPU. A system bus is any buffered version of the local bus.
A system bus may also differ from the local bus in terms of
coding of status and control lines andsortiming and loading
of signals.
Bus Interface Signals and Timing
The 80C286 microsystems local bus interfaces the 80C286
to local memory and I/O components. The interface has
24 address lines, 16 data lines, and 8 status and control
signals.
The 80C286 CPU, 82C284 clock generator, 82C288 bus
controller, 82289 bus arbiter, 82C86H/87H tranceivers,
and 82C82/83H latches provide a buffered and decoded
system bus interface. The 82C284 generates the system
clock and synchronizes READY and RESET. The 82C288
converts bus operation status encoded by the 80C286
into command and bus control signals. The 82289 bus

arbiter generates Multibus bus arbitration signals. These
components can provide the critical timing required for
most system bus interfaces including the Multibus.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs
to CMOS devices, and to eliminate the need for pull-up/
down resistors, bus-hold" circuitry has been used on the
80C286 pins 4-6,36-51 and 66-68 (See Figure 20A and
20B). The circuit shown in Figure 20A will maintain the
last valid logicstate if no driving source is present (i.e. an
unconnected pin or a driving source which goes to a high
impedance state). The circuit shown in Figure 20B will
maintain a high impedance logic one state if no driving
source is present. To overdrive the bus-hold" circuits, an
external driver must be capable of sinking or sourcing
'approximately 400 microamps at valid input voltage levels.
Since this bus-hold" circuitry is active and not a resistive"
type element, the associated power supply current is
negligible, and power dissipation is significantly reduced
when compared to the use of passive pull-up resistors.

EXTERNAL
PIN

FIGURE 20A. BUS HOLD CIRCUITRY -

PINS 36-51, 66, 67

4-38

EXTERNAL

PIN

FIGURE 20B. BUS HOLD CIRCUITRY -

PINS 4-6, 68

80C286

.DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
Physical Memory and I/O'lnterface
A maximum of 16 megabytes of physical memory can be
addressed in protected mode. One megabyte can .be
addressed in real address mode. Memory is accessible as
bytes or words. Words consist of any two consecutive
bytes addressed with the least significant byte stored in
the lowest address. Byte transfers occur on either half of
the 16-bit local data bus. Even bytes are accessed over
07-0 while odd bytes are transferred over 015-8. Even
addressed words are transferred over 015-0 in one bus
. cycle. while odd addressed word require two bus operations.
The firsttransfers data on 015-8. and the second transfers
data on 07-0. Both byte data transfers occur automatically.
transparent to software.

rate of one word per two processor clock cycles.
The 80C286 bus has three· basic states: idle (TI). send
status (TS). and perform command (TC). The 80C286 CPU
also has a fourth local bus state called hold (TH). TH
indicates that the 80C286 has surrendered control of the
local bus to another bus master in response to a HOLD
request.
Each bus state is one processor clock long. Figure 22
shows the four 80C286 local bus states and allowed
transitions.
RESET

Two bus signals. AD and BH E. control transfers over the
lower and upper halves ofthe data bus. Even address byte
transfers are indicated by AD lOW and BHE HIGH. Odd
address byte transfers are indicated by AO HIGH and BHE
lOW. Both AD and BHE are lOW for even address
word transfers.
The I/O address space contains 64K addresses in both
modes. The I/O space is accessible as either bytes or
words. as is memory. Byte wide peripheral devices may be
attached to either the upper or lower byte of the data bus.
Byte-wide I/O devices attached to the upper data byte
(015-8) are accessed with odd I/O addresses. Devices on
the lower data byte are accessed with even I/O addresses.
An interrupt controller such as Harris's 82C59A must be
connected to the lower data byte (07-0) for proper return
of the interrupt vector.
Bus Operation
The 80C286 uses a double frequency system clock (ClK
input) to control bus timing. All signals on the local bus are
measured relative to the system ClK input. The CPU
divides the system clock by 2 to produce the internal processor clock. which determines bus state. Each processor
clock is composed of two system clock cycles named
phase 1 and phase 2. The 82C284 clock generator output
(PClK) identifies the next phase of the processor clock.
(See Figure 21.)

CLK

PCLK

ir
Y

FIGURE 22.BOC2B6 BUS STATES

Bus States
The idle (TI) state indicates that no data transfers are in
progress or requested. The first active state TS is signaled
by status line S1 orSogoing lOWand identifying phase 1
of the processor clock. During TS. the command encoding.
the address. and data (for a write operation) are available
on the 80C286 output pins. The 82C288 bus controller
decodes the status signals and generates Multibus compatible read/write command and local transceiver control
signals.
After TS" the perform command (TC) state is entered.
Memory or I/O devices respond·to the bus operation during
TC. either transferring read data to the CPU or accepting
write data. TC states may be repeated as often as
necessary to ensure sufficient time forthe memory or I/O
. device to respond. The READY signal determines whether
TC is repeated. A repeated TC state is called a wait
state.
During hold (TH) •. the 80C286 will float all address. data.
and status output drivers enabling another bus master to
use the local bus. The 80C286 HOLD input signal is used
to place the 80C286 into the TH state. The 80C286 HlDA
output signal indicates that the CPU has entered TH.

0NE SVSTEM-j
eLK CYCLE

\'--___-11

Pipelined Addressing

FIGURE 21. SYSTEM AND PROCESSOR CLOCK
RELATIONSHIPS

Six types of bus operations are supported; memory read.
memory write. I/O read. I/O write. interrupt acknowledge.
and halt/shutdown. Data can be transferred at a maximum

The 80C286 uses a local bus interface with pipelined timing
to allow as much time as possible for data access.
Pipe lined timing allows a new bus operation to be initiated
every two processor cycles. while allowing each individual
bus operation to last for three processor cycles.

4-39

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

DOl -

Do - - - - - - - - - - - - - - - - - - - - - - - - - -

Pipeling: valid address (N

~-- - - -

- - - - -- - -

YAUDAEAD •
DATAIH)

= 1) available in last phase of bus cycle ~Nl.

-_.--c::::>VAUOAEAD
DATACN+l)

FIGURE 23. BASIC BUS CYCLE

The timing of the address outputs is pipelined such that
the address of the next bus operation becomes available
during the current bus operation. Or. in other words. the
first clock ofthe next bus operation is overlapped with the
last clock of the current bus operation. Therefore. address
decode and routing logic can operate in advance of the
next bus operation.
External address latches may hold the address stable for
the entire bus operation. and provide additional AC and
DC buffering.
The 80C286 does not maintain the address of the current
bus operation during all TC states. Instead. the address for
the next bus operation may be emitted during phase 2 of
any TC. The address remains valid during phase 1 of the
first TC to guarantee hold time. relative to ALE. for the
address latch inputs.
Bus Control Signals

Command Timing Controls
Two system timing customization options. command
extension and command delay. are provided on the
80C286 local bus.
Command extension allows additional time for external ,
devices to respond to a command and is analogous to
inserting wait states on the 80C86. Extemallogic can control
the duration of any bus operation such that the operation
is only as long as necessary. The READY input signal can
extend any bus operation for as long as necessary.
Command delay allows an increase of address or write data
setup time to system bus command active for any bus
operation by delaying when the system bus command
becomes active. Command delay is controlled by the 82C288
CMDlY input. AfterTS. th~ bus controllersamples CMDlYat
each failing edgeofCLK.lfCMDlYis HIGH. the 82C288 will
not activate the command signal. When CMDlY is lOW. the
82C288 will activate the command signal. Afterthe command
becomes active. the CMDlY input is not sampled.

The 82C288 bus controller provides control signals; address ,
latch enable jtl.lE}. Read/Write commands. data transmit/ When a command is delayed. the available response time
receive (DT/R). and data enable (DEN) that control the from command active to return read data or accept write
address latches. data transceivers. write enable. and output data is less. To customize system bus timing. an address
enable for memory and I/O systems. The Address Latch decoder can determine which bus operations require
Enable (ALE) output determines when the address may be delaying the command. The CMDlY input does not affect
latched. ALE provides at least one system ClK period of the timing of ALE. DEN or DT/R.
address hold time from the end ofthe previous bus operation
until the address for the next bus operation appears at the Figure 24 illustrates four uses of CMDlY. Example 1
latch outputs.,This address hold time is required to support shows delaying the read command two system ClKs for
Multibus and common memory systems.
cycle N-1 and no delay for cycle N. and example 2 shows
delaying the read command one system ClK for cycle N-1
The data bus transceivers are controlled by 82C288 outputs and one system CLK delay for cycle N.
Data Enable (DEN) and Data Transmit/Receive (DT/R).
DEN enables the data transceivers; while DT/R controls Bus Cycle Termination
franceiver direction. DEN and DT/R are timed to prevent
bus contention between the bus master. data bus At maximum transfer rates. the 80C286 bus alternates
between the status and command states. The bus status
transceivers. and system data bus transceivers.

4-4q

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
READ CYCLE N-1

elK

PRoe
elK

ALE _ _ _J

EX1~:': ________-Jr-----~~--~,~ ~
____

a,~:

__________

~

______________

~ ~+-________~____
__

________________

en
Ie
o
en
en
en ....

.1-__---,

OU

:;:0

ug:
o

Ie

FIGURE 24. CMDLY CONTROLS THE LEADING EDGE OF COMMAND SIGNAL

signals become inactive afterTs so thatthey may correctly
signal the start ofthe next bus operation after the completion
ofthe current cycle. No external indication ofTC exists on
the 80C286 local bus. The bus master and bus controller
enter TC directly after TS and continue executing TC
cycles until terminated by the assertion of READY.
READY Operation
The current bus master and 82C288 bus controller terminate
each bus operation simultaneously to achieve maximum
bus operation bandwidth. Both are informed in advance
by READY active (open-collector output from 82C284)
which identifies the lastTc cycle ofihe current bus operation.
The bus master and bus controller must see the same
sense ofthe READY signal, thereby requiring READYto be
synchronous to the system clock.
Synchronous Ready
The 82C284 clock generator provides READY synchronization from both synchronous and asynchronous sources
(see Figure 25). The synchronous ready input (SRDY) of
the clock generator is sampled with the falling edge of
elK atthe end of phase 1 of each Te. The state ofSifi5Y' is
then broadcast to the bus master and bus controller via
the READY output line.

Asynchronous Ready
Many systems have devices or subsystems that are
asynchronous to the system clock. As a result, their ready
outputs cannot be guaranteed to meet the 82C284 SRDY
setup and hold time requirements. But the 82C284
asynchronous ready input (ARDY) is designed to accept
such signals. The ARDY input is sampled at the beginning
of each TC cycle by 82C284 synchronization logic. This
provides one system ClK cycle time to resolve its value
before broadcasting itto the bus master and bus controller.
ARDY or ARDYEN must be HIGH at the end of TS. ARDY
cannot be used to terminate the bus cycle with no wait
states.
Each ready input of the 82C284 has an enable pin
(SRDYEN and ARDYEN) to select whether the current bus
operation will be· terminated by the synchronous or
asynchronous ready. Either of the ready inputs may
terminate a bus operation. These enable inputs are active
low and have the same timing as their respective ready
inputs. Address decode logic usually selects whether the
current bus operation should be terminated by ARDY or
SRDY.

4-41

U

:E

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been deveioped through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is Implied.
Data Bus Control

Figures 26, 27, and 28 show how the DT/R, DEN, data bus,
and address signals operate for different combinations of
read, write, and idle bus operations. DT/R goes active
(LOW) for a read operation. DT/R remains HIGH before,
during, and between write operations.

the processor Reset operation is complete, no interrupts
should occur after the execution of HLT until 34 CLKs after
the trailing edge of the RESET pulse.

The data bus is driven with write data during the second
phase ofTS. The delay in write data timing allows the read
data drivers, from a previous read cycle, sufficient time to
enter three-state OFF before the 80C286 CPU begins driving
the local data bus for write operations. Write data will
always remain valid for one system clock past the last TC
to provide sufficient hold time for Multibus or other similar
memory or I/O systems. During write-read or write-idle
sequences the data bus enters a high impedance state
during the second phase of the processor cycle after the
last TC. In a write-write sequence the data bus does not
enter a high impedance state between TC and TS.

The CPU asserts an active lock signal during InterruptAcknowledge cycles, the XCHG instruction, and during
some descriptor accesses. Lock is also asserted when the
LOCK prefix is used. The LOCK prefix may be used with the
following ASM-286 assembly instructions; MOVS, INS
and OUTS. For bus cycles other than Interrupt-Acknowledge
cycles, Lock will be active for the first and subsequent
cycles of a series of cycles to be locked. Lock will not be
shown active during the last cycle to be locked. For the
next-to-Iast cycle, Lock will become inactive at the end of
the first TC regardless of the number of wait states inserted.
For Interrupt-Acknowledge cycles, Lock will be active for
each cycle, and will become inactive at the end ofthe first
TC for each cycle regardless of the number of waitstates inserted.

Bus Usage
The 80C286 local bus may be used for several functions:
instruction data transfers, data transfers by other bus masters,
instruction fetching, processor extension data transfers,
interrupt acknowledge, and halt/shutdown. This section
describes local bus activities which have special signals
or requirements. Note that I/O transfers take place in
exactly the same mann-er as memory transfers (i.e. to the
80C286 the timing, etc. of an I/O transfer is identical to a
memory transfer).
HOLD and HLDA
HOLD and H LDA allow another bus master to gain control
of the local bus by placing the 80C286 bus into the TH
state. The sequence of events required to pass control
between the 80C286 and another local bus master are
shown in Figure 29.
In this example, the 80C286 is initially in the TH state as
signaled by HLDA being active. Upon leaving TH, as
signaled by HLDAgoing inactive, a write operation is started.
During the write operation another local bus master requests
the local bus from the 80C286 as shown by the HOLD
signal. After completing the write operation, the 8cic286
performs one TI bus cycle, to guarantee write data hold
time, then enters TH as signaled by HLDA going active.
The CMDLY signal andAIID'Y ready are used to start and
stop the write bus command, respectively. Note that
SRDY must be inactive or disabled by SRDYEN to guarantee
ARDY will terminate the cycle.
.
HOLD must not be active during the time from the leading
edge of RESET until 34 CLKs following the trailing edge of
RESET unless the 80C286 is in the Halt condition. To
ensure thatthe 80C286 remains in the Halt condition until

LOCK

Instruction Fetching
The 80C286 Bus Unit (BU) will fetch instructions ahead of
the current instruction being executed. This activity is
called prefetching. It occurs when the local bus would
otherwise be idle and obeys the following rules:
A prefetch bus operation starts when at least two bytes of
the 6-byte prefetch queue are empty.
The prefetcher normally performs word prefetches
independent of the byte alignment of the code segment
base in physical memory,
The prefetcherwill perform only a byte code fetch operation
for control transfers to an instruction beginning on a
numerically odd physical address.
Prefetching stops whenever a control transfer or HLT
instruction is decoded by the IU and placed into the
instruction queue.
In real address mode. the prefetcher may fetch up to 6
bytes beyond the last control transfer or H LT instruction in
a code segment.
In protected mode. the prefetcher will never cause a
segment overrun exception. The prefetcher stops at the
last physical memory word of the code segment. Exception
13 will occur if the program attempts to execute beyond
the last full instruction in the code segment.
If the last byte of a code segment appears on an even
physical memory address. the prefetcher will read the
nt!xt physical byte of memory (perform a word code fetch).
The value of this byte is· ignored and any attempt to
execute it causes exception 13.

4-42

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
MEMORY CYCLE N-1

~.2lo4J
..

1~'>2

I

MEMORY CYCLE N

"'11"021"'11~':1.1'~11~'02

I

....--Tc--.~Ts-----....---TC--..~Tc-------.

ClK

PROCCLK

,,>, - Ao

---------------+~

RmlV

AIIlIV

\\\\\\\\\\\\\\\\\\\\\\\\\\~\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ ~/ll77l7100
(SEE NOTE 3.)

NOTES:
1. SRDYEN is active low
2. If SRDVEN is high. the state of SRDY will not effect READY
3. ARDYEN is active low

FIGURE 25. SYNCHRONOUS AND ASYNCHRONOUS READY

c:n
a:
o
c:n
c:n
c:n ....
0'"
::;;0

... g:
o

...:i5a:

ClK

~.

DEN

------------~----~

oljii

FIGURE 26. BACK TO BACK READ-WRITE CYCLE

4-43

80C286

DESIGN INFORMATION

(Continued)

The Information contained in this section has been developed through characterization by Harris Semiconductor and is for
.
use as application and design information only. No guarantee is implied.

WRITE CYCLE

READ CYCLE

ClK

015-00 - - - - - - - - - -

VALID WRITE DATA

DEN

D1i1!

FIGURE 27. BACK TO BACK WRITE-READ CYCLE

WRITE CYCLE N-1

WRITE CYCLE N

ClK

Au-Ao

---J''''.LLl....---__+-___-II-''\LW''-_f-___+-__ f-_..J'\Lj:.L,<; '<..LI.~LL2 of TC.

' .

.

.

3. BFi'E and LOCK maystartfloating afterthe end of anyTe depending on when intemal80C286 bus arbiter decides to release busto external HOLD. Thefloat
~rts~~~~
' .
4. The minimum HOLD to HLDA time is shown. Maximum is one T H longer.
5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
6. The minimum HOLD to HLOA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e., Interrupts, Waits,

Lock, ate.).
7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state is ignored after
ready is signaled via the asynchronous input.

FIGURE 29. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD

4-45

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Processor Extension Transfers

Local Bus Usage Priorities

The processor extension interface uses I/O port addresses
OOF8(H). and OOFC(H) which are part ofthe I/O port address
range reserved by Harris. An ESC instruction with Machine
Status Word bits EM = 0 and TS = 0 will perform I/O bus
operations to one or more of these I/O port addresses·
independent of the value of 10PL and CPL '

The 80C286 local bus is shared among several internal
units and external HOLD requests. In case of simultaneous
requests. their relative prioriti'es are:
(Highest)

ESC instructions with memory references enable the CPU
to accept PEREa inputs for processor extension operand
transfers. The CPU will determine the operand starting
address and read/write status of the instruction. For each
operand transfer. two orthree bus operations are performed.
one word transfer with I/O port address OOFA(H) and one
or two bus operations with memory. Three bus operations
are required for each word operand aligned on an odd
byte address.-

Any transfers which assert LOCK either
explicitly (via the LOCK instruction prefix) or
implicitly (i.e. some segment descriptor
accesses. an interrupt acknowledge sequence. or an XCHG with memory).
The second of the two byte bus operations
required for an odd aligned word operand.
The second or third cycle of a processor
extension data transfer.
Local bus request via HOLD input.

Interrupt Acknowledge- Sequence
Figure 30 illustrates an interrupt acknowledge sequence
performed by the 80C286 in response to an INTR input. An
interrupt acknowledge sequence consists of two INTA bus
operations. The first allows a master82C59A Programmable·
Interrupt Controller (pIC) to determine which if any of its
slaves should return the interrupt vector. An eight bit vector (Lowest)
is read on 00-07 of the 80C286 during the second INTA
bus operation to select an interrupt handler routine from
the interrupt table.
The Master Cascade Enable (MCE) signal of the 82C288 is
used to enable the cascade address drivers during INTA
bus operations (See Figure 30) onto the local address bus
for distribution to slave interrupt controllers via the system
address bus. The 80C286 emits the LOCK signal (active
LOW) during TS of the first INTA bus operation. A local bus
hold" request will not be honored until the end of the
second INTA bus operation.
Three idle processor clocks are provided by the 80C286
between INTA bus operations to allow for the minimum
INTA to INTA time and CAS (cascade address) out delay of
the 82C59A. The second INTA bus operation must always
have at least one extra TC state added via logic controlling
READY. A23-AQ are in three-state OFF until after the first
TC state of the second INTA bus operation. This prevents
bus contention between the cascade address drivers and
CPU address drivers. The extra TC state allows time forthe
80C286 to resume driving the address lines for subsequent
bus operations.

Processor extension data operand transfer
via PEREa input.
Data transfer performed by EU as part of
an instruction.
An instruction prefetch request from BU.
The EU will inhibit prefetching two processor
clocks in advance of any data transfers to
minimize waiting by the EU for a prefetch
to finish.

Halt or Shutdown Cycles
The 80C286 externally indicates halt or shutdown conditions
as a bus operation. These conditions occur due to a HLT'
instruction or multiple protection exceptions while
attempting to execute one instruction. A halt or shutdown
bus operation is signalled when S1. SO. and COD/INTA are
LOW and M!iO is HIGH. A1 HIGH indicates halt. and A1
LOW indicates shutdown. The 82C288 bus controller
does not issue ALE. nor is READY required to terminate a
halt or shutdown bus operation.
During halt or shutdown. the 80C286 may service PEREa
or HOLD,requests. A processor extension segment overrun
during shutdown will inhibit further service of PEREa.
Either NMI or RESET will force the 80C286 out of either
halt or shutdown. An INTR. if interrupts are enabled. or a
processor extension segment overrun exception will also
force the 80C286 out of halt.

4-46

80C286

DESIGN INFORMATION

(Continued)

The Information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee Is implied.

BUS CYCLE TYPE

I ,'"

~C .'02 I .~1

~INTA CYCLE 1

I

TIS .'02

,',I

~C ,'.2

I

----=---i
~C I ~I
.'.1

.'02

.'.1

.',2

I

,'.1

~' .'.2

ClK

MIRi. CODiINTA

~

An -

lIRE

0" -

(SEE NOTE 5.1

Ao LLLLLr - - - - - - - - - - -

Do

<\..___D_ON_·T_C_A_R_E_ _...J)- -

-

- -.- -

»»»>))>-------- --- -<_____

D_ON_·T_CA_RE_---J}- -

_-"w"'~"'~f...EV"'~O"'Va::"'~"'E...J

-- -

-

-

-

-

-

N

ill

-

-

-c=

{VECTOR}- -

-

(SEE NOTE 3.1

READY

NOT READY

,-

MCE

I~

1\

ALE

n

n
\

/
/

\

/
/

\

READV

r-

\

\

DEN

-

-0 -- -- - - - - -- - -- - - - -- - -

iN'\')(

Dl1R

-

S\\\\\\ 1///I!70/l/// \\\\\\ 1l/Ol//l//RIlRW//I//IIII////I/7 \\\\\\ f1T1177
NOT READY

.
..

- -

(SEE NOTE 1.)

.- -

(SEE NOTE 2.1
READV

(SEE NOTE 5 I
- - - -.-{\.._ _ __

'--

NOTES:

1. Data is ignored.
2. First INTA cycle should have at least one wait state inserted to meet 82C59A minimum INTA pulse width.
3. Second INTA cycle must have at least one wait state inserted since the CPU will not drive A23-Ao. 'BFft and LOCK until alter the first TC state.
The CPU imposed one/clock delay prevents bus contention between cascade address buffer being disabled by MCE j and address. outputs.
Withoutthe wait state. the80C286 address will not bevalidfora memory cycle started immediately alter the second INTAcycle. The82C59Aaiso '.
requires one wait state for minimum INTA·pulse width.
4. "meR' is active for the first INTA cycle to preventthe 82289 from releasing the bus between INTA cycles in a multi-master system. TI!CI< is also
active for the second INTA cycle.
5. A23-Ao exits three-state OFF during 2 of the second TC in the INTA cycle.

FIGURE 30.lNTERRUPT ACKNOWLEDGE SEQUENCE

4-47

80C286

DESIGN INFORMATION

(Continu'ed)

.. The information contained in this sec~ion has been developed through characterization by Harris Semiconductor and is for
use as 'applicatlon and design if1formation only. No guarantee is implied.
.
Vee

hrr;m;;;-~=~";;;l----~-----.

.-,1--.,1--, .

CMDL Y.

sol-+_----I~
51

AEA6Y

•

1'9 WRITE

ST
iiE'i"6"V

INTERRUPT ACK.N~~lEDGE

MCE

,..----.,

OEN

r' -

DT/li

r -

82C288 BUS
CONTROLLER

.'-_ _"'""1"0,-,
RESET

ENABLE

I

r-

I

I

f--.+H++---,

I

-I

-

- - ...... 1

rI

oJ

.DECODE

t- ...
t- ~

ADVANCED MEMORV

AJi

.

I'

.1

I

I

I

82C284

-

I,..
...I

·1

I'

A'R"fiV
UI'IWE'A

MEMORV WRITE .'

=~~~~'IOREAD

iOWC
iNTi
ALE

eLK I-~+-II-+~ CI,K

ASVNC READY .....----

MEMORY READ.

M'Wi"'e!

MB

ADDRESS BUS

I

CLOCK

I

• GENERATOR

I
I

r---J I

r,---J

i i~;===-=

I I r----- ~
I : I I I r - - - - PEREa'
111111

r

_J_~_L:_~_:_.,·

I
I

INTR

r--ttltt===::l

8OC28~

D~PU Do

I
PROCESSOR

I

~;~~~I~~

IL.

_______

l -L - - - f',r-- __

JI

DATA
BUS

FIGURE 31. BASIC 80C286 SYSTEM CONFIGURATION

System Configurations
The versatile bus structure of the BOC286 micro-system.
with a full complement of support chips. allows flexible
configuration of a wide range of systems. The basic
configuration. shown in Figure 31. is similar to an 80C86
maximum mode system. It includes the CPU plus an
82C59A interrupt ·controller•. 82C284 clock generator,
and the 82C288 8us Controller. The 80C86 latches (82C82
and 82C83H) and transceivers (82C8.61-\ and 82C87H)
may be used in an 80C286 microsystem.

.and data transfers concurrently with CPU program execution:
. Numerics code and data have the same integrity as all
other information protected by the 80C286 protection
mechanism.

The 80C286 can overlap chip select decoding and address
propagation during the data transfer for the previous bus
operation. This information is latched into the 82C82/83H's
by ALE during the middle of a TS cycle. The latched chip
select and address information remains stable during the
As indicated by the dashed lines in Figure 31. the abilityto bus operation while' the next cycle's address is being
add procies~or extensions is an integral feature of 80C286 . decoded and propagated into the system. Decode logic
based microsystems. The processor extension interface can be imple'!'ented with a high speed PROM or PAL.
allows external hardware to perform special functions and
transfer data concurrent with CPU execution of other The optional decode logic sh.own in Figure 31. takes'
instructions. Full system integrity is maintained because advantage of the overlap between address and data of the
the 80C286 supervises all data transfers and instruction 80C286 bus cycle to generate advanced memory'and 1/0execution for the processor extension.
select signals. This minimiz,,!s system performance
degradation caused by address pr.opagation and decode
An 80C286 system which indudes the 80287 numeric delays. In addition to selecting memory and I/O. the
processor extension (NPX)· uses this interface. The advanced selects may be' used with configurations
80C286/80287 system has all the instructions' and data supporting local and system buses to enable the ajPro- .
types of an 80C86 or 80C88 with 8087 numeric processOT priate bus interface for each bus cycle. T!1e COD INTA
extension. The 80287 NPXcan perform numeric calculations

4-48

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

_-+r-t SRESET
FIYESSBlRE,ESB BCLK
INIT -_

.--

Vee~ ~

)

iiiiEQ -

MULTIBUS
BUS ARBITRATION

- L. cmrrt:R BPRO -So
1iPRN_
, - - - !i1

BiJSY _ _

'--I--rH--o-liiEADv
~
CLK

CBRO - -

Ll!CR ____

r-i-+++-H AEN

M/iO -

82289
BUS ARBITER

Vee

AEN

MRDc I-+-+--------+-+--~
MW'fC I-+-+--------++-~
IORC

CMDLY

x,
-::

I

-

- -r

_

SYNC READY _
ENABLE _
ASYNC READY ENABLE _

-

I-+-t--.....-----++-~

MEMORY READ
MEMORY WRITE

vo READ

lowe I-+-t---+~----++-- va WRITE
iNTi I-+-t---++.,....---++-~ INTERRUPT ACKNOWLEDGE

x,
So'~-+-HH~ So
!li~-+-1++I !i1

PCLK
EFI

READY
CLK

H

ALE
MCE
READY
DEN 1-+-+---,
.....-+-+-t-<~ CLK
DT;;; 'I
82C2888US

F/C

CONTROLLER

I

lIIil5V

RESET

§iii5YElI
-.

liiI5ffi
82C284

GE~~~;'~OR

MIlO

H-li--+-++-I--,

t

I :
I I
I I
I

L.

I:

RESET

M,jl!

CLK

= -

-

!IT

A"-""I-_-,,.-,-,---.-.-""7<"---'_-'/

=:

82C83H

• ~r-_U_.TC_H_-..,
1---+++-1-+=1

r - __ ~I I - . .
NMI

jjH£

I r---J
: : :~~~
r------- EIIImii
I I I r _ _ _ _ _ __ BiJSY

CASO-'
INTR i - - - 1 H - I - - + - + - - - - - - I I N T

I I

: : I I r----I I I I I r - - - .....
IIIIII
I I I I

_+_+_1_1_'_1_,
I
I
PE~~~~~~g:
k1- (OPTIONAL)

~

PEACK
PEREO
80C286
CPU

r

:

~ ADDRESS BUS

- - . READY CODIINTAI-_ _-'--'-"-'-'_ _-'----'"

I I

I

C. STB

'---+ DE

015 -

:.r ----

L

Aol-

~ f4-

""

'-------0-1 lID

1<==

.------~SP~

DD

'"

- - -

L _ _ _ _ _ _ _ .1

CHIP SELECT

~ -8~~59A
Do

IRo - IR,

INTERRUPT
CONTROLLER

I----~

' - - - - - - ,__- - - - - - , ;

DE
82C87H
TRANSCEIVER

I<===>

DATA BUS

'-------~-IT

FIGURE 32. MULTI BUS SYSTEM BUS INTERFACE

and M!iO signals are applied to the decode logic to
distinguish between interrupt. I/O. code. and data bus
cycles.

write data setup times. This arrangement will add at least
one extra TC state to each bus operation which uses
the Multibus.

By adding the 82289 bus arbiter chip the 80C286 provides
a Multibus system bus interface as shown in Figure 32.
The ALE output of the 82C288 for the Multibus bus is
connected to its CMDlY input to delay the start of commands
one system ClK as required to meet Multibus address and

A second 82C288 bus controller and additional latches
and transceivers could be added to the local bus of Figure
32. This configuration allows the 80C286 to support an
on-board bus for local memory and peripherals. and the
Multibus for system bus interfacing.

4-49

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design Information only. No guarantee is· implied.

80C286 Instruction Set Summary
. Instruction Clock Count Assumptions

Instruction Timing Notes
The instruction clock counts listed below establish the
maximum execution rate ofthe 80C286. With no delays in
bus cycles, the actual clock count of an 80C286 program
will average 5% more than the calculated clock count, due
to instruction sequences which execute faster than they
can be fetched from memory.
To calculate elapsed times for instruction sequences,
multiply the sum of all instruction clock counts, as listed in
the table below, by the processor clock period. An
12.5MHz processor clock has a clock period of 80
nanoseconds and requires an 80C286 system clock (ClK
input) of 25M Hz.

BYTE 1

eYTE2

1. The instruction has been prefetched, decoded and is
ready for execution. Control transfer instruction clock
counts include all time required to fetch, decode, and
prepare the next instruction for execution.
2. Bus cycles do not require wait states.
3. There are no processor extension data transfer or local
bus HOLD requests.
4. No exceptions occur during instruction execution.

BYTE 3

BYTE 5

BYTE 4

BYTE 6

7654321076543210

I I I I I I I I I I I I I I 1- ~O: ~S~O:: ~ ~G~ O~P~~A- ~
H~~D::
I
Id/wlmodl
I rIm 1 _______ 1 _______ 1_______ ·l _______ ~
-

OPCODE

-

-

::O:A- -

reg

L

·f

REGISTER OPERAND/REGISTERS TO USE IN

OFF~ET

CALCULATION

REGISTER OPERAND/EXTENSION OF OPCODE
' - - - - - - - REGISTER MODE/MEMORY MODE WITH DISPLACEMENT LENGTH
' - - - - - - - - WORD/eYTE OPERATION
' - - - - - - - - - - DIRECTION IS TO REGISTER/DIRECTION IS FROM REGISTER
' - - - - - - - - - - - - - ·OPERATION (INSTRUCTION) CODE
A. SHORT OPCODE FORMAT EXAMPLE

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

B. LONG OPCODE FORMAT EXAMPLE

FIGURE 33. 80C286 INSTRUCTION FORMAT EXAMPLES

4-50

"'; -

-

-,

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Either Mode

Instruction Set Summary Notes
Addressing displacements selected by the MOD field are
not s!1own. If necessary they appear after the instruction
fields shown.

6. An exception may occur, depending on the value of
the ope~and.
7. LOCK is automatically asserted regardless of the
presence or absence of the LOCK instruction prefix.

Above/below refers to unsigned value
Greater refers to more positive signed values

8. LOCK does not reamain active between all operand
transfers.

Less refers to less positive (more negative) signed values
Protected Virtual Address Mode Only
if d

= 1, then ··to" register; if d = 0 then "from" register
9. A general protection exception (13) will occur if the

if w "= 1, then word instruction; if w
instruction
if s

= 0, then byte

=0, then 16-bit immediate data form the operand

if s = 1 then an immediate data byte is sign-extended to
form the 16-bit operand
x don't care

z used for string primitives for comparison with ZF

memory operand cannot be used due to either a
segment limit or access rights violation. If a stack
segment limit is violated, a stack segment overrun
exception (12) occurs.
10. For segment load operations, the CPL, RPL and DPL
must agree with privilege rules to avoid an exception.
The segment must be present to avoid a not-present
exception (11). If the SS register is the" destination
and a segmer:tt not-present violation occur:s, a stack
excepti,!n (12) occurs.

FLAG
If two clock counts are given, the smaller refers to a register
operand and the larger refers to a memory operand
add one clock ifoffsetcalculation requires summing
3 elements

=

11. All segment" descriptor accesses in the GOT or LOT
made by this instruction will automatically assert
LOCK to maintain descriptor integrity in multiprocessor systems.

number of times repeated
number of bytes of code in next instruction

13. A general protection exception (13) occurs if CPL #- O.

The following comments describe possible exceptions,
side effects and allowed usage for instructions in both
operating modes of the 80C286.
Real Address Mode Only
1. This is a protected mode instruction. Attempted
execution in real address mode will result in an
undefined opcode exception (6).
2. A segment overrun exception (13) will occur if a word
operand reference at offset FFFF(H) is attempted.
3. This instruction may be executed in real address mode
to initialize the CPU for protected mode.
4. The IOPL and NT fields will remain O.
5. Processor eXtension segment overrun interrupt (9) will
occur if the operand exceeds the segment limit.

OU

:;;0

ug:
o

Ie

12. JMP, CALL, INT, RET, IRET instructions referring to
another code segment will cause a general protection
exception (13) if any privilege rule is violated.

Level (L)-Lexical nesting level of the procedure

en
Ie
o
en
en
en ....

14. A general protection exception (13) occurs if CPL
IOPL.

>

15. The IF field" of the flag word is not updated if CPL >
IOPL. The IOPL field is updated only if CPL = O.
16. Any violation of privilege rules as applied to the
selector operand does not cause a protection
exception; rati)er, the instruction does not return a
result and the zero flag is cleared.
1 7. If the starting address of the memory operand violates a
segment limit. or an invalid access is attempted, a general
protection exception (13) will occur before the ESC
instruction is executed. A stack segment overrun
exception (12) will occur ifthe stack limit is violated by
the qperand's starting address. If a segment limit is
violated during an attempted data transfer than a processor extension segment overrun exception (9) occurs.
18. The destination of an INT, JMP, CALL, RET or IRET
instruction must be in tile defined limitot a code segment
or a general protection" exception (13) will occur.

U

55

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

80C286 Instruction Set Summary
CLOCK COUNT
UNCTION

Real

FORMAT

Addreaa

Protected

Virtual

Modo

Addre..
Mode

11000100W

mod reg

rIm

2.3'

2.3'

1000101w

mod reg

rIm

2,5'

2,5'

11000 11 w

mcdDDD rIm

data

2.3'

2.3'

1011 w reg

da1a

dataifw=1

1010000w

addr-low

addr-hlgh

1010001w

addr-Iow

addr·hlgh

10001110

mod oreg rIm

2,5'

17,19'

10001100

mod 0 reg rIm

2,3'

2,3'

5'

5'

1 1 111111 I mod 11 0 rIm

I

dataifw=1

COMMENTS

Real

Addr...
Mod.

Protected

Virtual

Addr."
Modo

9,10,11

I
I 000regl1 0 I
101010 reg

10001111 ImodOOO

I

01011

reg

11000011 W ImodrOg'
10010 reg

r/ml

I

3,5~·

r/ml

2,7

7,9

I
14

port

11110010wI

14

1111011'owl

1110011,wl

14

port

14

1110111 wi
11010111
EA = LOB:d EA to register.

10001101

DS= Load pointer to OS

11000101

ES= Load pointer to ES

Shad~d areas in,dicate instructio~5

I
I

mod reg

rIm!

3'

3'

mod reg

rIm!

(mod,, ,
,

",".

'••

0

,J"

- ~/.'

1101)1'000

~vI.. ~~·

.......

.<:.

.. ,

'

;

~.

1 t00100'.

~

':

1

INT-Interrupt:

Type specified

11001101

23+m

2,7,8

Type 3

11001100

23+m

2,7,8

INTO = Interrupt on overflow

11001110

24 +mor3
(3 Wno
interrupt)

type

Shaded areas indicate instructions not available in SOCS6/SS microsystems.

4-57

2,6,8
(3 ~no
Interrupl)

ug:
0
ua:

:ill

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

80C286 Instruction Set Summary (Continued)

_I

FORMAT

Add....
Mode

-

VIrtuII

A_
Mod.

RNI
AddrHa
Mode

4O+m
78+ m
187+m
11001111

17+m

31+m

-

Acid. . .
M_

7.8,11,12,18
7,8,11,12.18
7,8,11,12.1'8
2.4

8,9,11,12,15,18

55+m

11111000

2

2

11110101

2

11111001

2

11111100

2

11111101

2

11111010

3

14

2

14

11110100

2

13

10011011

3

11111011

2

-0

9-20·

Shaded areas indicate instructions not available in SOCB6/B8 microsystems.

4-58

14

0

5,8

8,17

80C286

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

80C286 Instruction Set Summary (Continued)
RNI

FORMAT

Shaded areas indicate instruc~ions not available in BOeS6/SS microsystems.

4-59

Protoc\od
ViItIW
Add....

RNI
Add....

1ii :;!

-

(b (b

LO

HI

0
1
2

3

t-

o

1

ADD
b.f.r/m

w.f.r/m

ADC
b.f.r/m

ADD

ADC

w.f.r/m
AND

AND
b.f.r/m

w.f.r/m

XOR
b.f.r/m

w.f.r/m

XOR

2

3

4

5

6

7

ADD

ADD

ADD
b.ia

ADD
w,ia

PUSH
ES

POP
ES

OR
OR
OR
b.f.r/m w.f.r/m b.t.r/m

ADC

ADC

b.ia

w,ia

PUSH
SS

AND

AND

b,ia

w,ia

XOR
b.ia

XOR

b.t.r/m w.t.r/m
ADC

b.t.r/m w.t.r/m
AND

XOR

XOR

b.t.r/m w.t.r/m

9

C

0

OR

OR
b.i

OR

w.t.r/m

POP
SS

SBB
SBB
SBB
SBB
b.f.r/m w.f.r/m b.t.r/m w.t.r/m

SBB
b.i

SBB

SEG
=ES

DAA

SUB
SUB
SUB
SUB
b.f.r/m w.f.r/m b.t.r/m w.t.r/m

SEG
=SS

AAA

w,ia

CMP
CMP
CMP
CMP
b.f.r/m w.f.r/m b.t.r/m w.t.r/in

A

w.i

,

E

F

PUSH PVAM n
CS

w.i

SUB
b.i

SUB
w,i

SEG
=CS

DAS

111

CMP
b.i

CMP

SEG
=DS

AAS

w.i

'~"

ex

INC
BP

INC
SI

INC
01

DEC
AX

DEC
CX

DEC
OX

DEC
BX

DEC
SP

DEC
BP

DEC
SI

DEC
01

PUSH
AX

PUSH
CX

PUSH
OX

PUSH
BX

PUSH
SP

PUSH
BP

PUSH
SI

PUSH
01

POP
AX

POP
CX

POP
OX

POP
BX

POP
SP

POP
BP

POP
SI

POP
,01

6

PUSHA

POPA

7

JO

JNO

5

BOUND ARPl

JBI

9

JNBI
JAE

Immed
b.r/m

Immed

w.r/m

Immed Immed
b.r/m
is.r/m

XCHG
AX

XCHG
CX

XCHG
OX

XCHG
BX

PUSH
IMUL PUS/-f
IMUL
w.i w,t.r/m.i
b.i
b.t.r/m.i
JE/
JZ

JNE/
JNZ

JBEI
JNA

JNBEI
JA

TEST
b.r/m

TEST

XCHG

w.r/m

XCHG
b.r/m

XCHG
SP

XCHG
BP

XCHG
SI

XCHG
01

A

MOV
m-AL

MOV
m-AX

MOV
AL-m

MOV
AX-m

B

MOV
i-AL

MOV
i-Cl

MOV
i-DL

MOV
i-Bl

MOV
i-AH

MOV
i-CH

Shift
b.i

Shift

RET
(i+SP)

RET

LES

LOS

C

0
E

F

Shift
b

w.i
Shift
w

LOOPNZI lOOPZI
lOOPNE lOOPE
LOCK

Shift
b.CL
LOOP

REP

Shift
b.Cl
JCXZ

REPZ

w.r/m

AAM

MOV
i-BH

XLAT

IN

HlT

CMC

w

g.

JNL/
JGE

'JlEI
JNG

JNLEI
JG

MOV
MOV
MOV
MOV
MOV
b.f.r/m w.f.r/m b.t.r/m w.t.r/m .r.f.r/m

LEA

MOV

POP

sr.t,r/m

rIm

SAHF

LAHF

JPI
JPE

CBW

MOV
i-AX

ESC

0
IN
b

~

JL/
JNGE

JNS

CWO

TEST
w.i.a
MOV
i-CX

CALL
i.d

ESC
1

JNPI
JPO

WAIT

PUSHF

POPF

MOV
i-OX

ESC,
2

.,.,

0

>t.,3
~r go!:::.

"0

0

Cl.

s· ::c

::. 0

~a

r5- s'
::. So
s· Ci)'
C3'

CIJ·

Q)

~

3~

::."0

-0-

'" CD
:;::CD

~ cs
Q1

0-

fi ~:
0~

§-g
"0""

&~

.,

fl.:;,.

.,g.~.
::.

MOV
i-BX

MOV
i-SP

MOV
i-BP

MOV
i-SI

MOV,
i-Ol

RET
I

INT
Type 3

INT
(any)

INTO

IRET I

,.,:t:

I

OJ'
C/)
(b

OUT
b

OUT
w

CAll
d

JMP
d

JMP
i.d

JMP

Grp 1
b.r/m

Grp 1

ClC

STC

Cli

w.r/m

.ESC

ESC

ESC

I

5

6

7

I

si,d

IN
DX.b

IN
DX;w

OUT
DX.b

OUT'
DX.w

. STI

Cll:!

STO

Grp2
b.r/m

w,r/m

Grp 2

==
:.:-

::!
0
:z

::. :;,.
o .,
::.

Cit

4

0

~
S·
CQ

;t
;C'

ESC

"T1

g. g. '0
0

OJ

3'

:z
:z

o

.,::. iil'::.

0

ESC

~

C)

., :i=o ::. .e
""g-

~-

!

CI

m

::s
~
~

O

STOSB STOSW LODSB LODSW SCASB SCASW

MOV
MOV ENTER lEAVE
RET
1.(i+SP)
b.i.r/m w.i,r/m

AAO

Si

INSW OUTSB OUTSW

MOVSB MOVSW CMPSB CMPSW TEST
b.i ••
MOV
i-DH

S·

INSB

JS

~
B-

POP
OS

INC
SP

INC

~
~
~

PUSH
OS

INC
BX

INC
AX

8

-

AND

b.t.r/m w.t.r/m

JNAE

-

ADC

B

8

INC
OX

4

O)

0

S'

Q)

0-

'<:

~

3

o·
0

::.

g-

o
...6'

.,::.

Cl.

1ii

0...

C

C1)

~

000
Q)

80C286

DESIGN INfORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use. as application and design information only. No guarantee is implied.

80C286 Machi"e Ins.truction Encoding Matrix

(Continued)

where:
000

001

010

011

100

101

110

111

Immed

ADD

OR

ADC

SBB

AND

SUB

XOR

CMP

f
i

-

SAR

ia
id

Shift

ROL

ROR

Grpl

TEST

-

Grp2

INC

DEC

RCL

RCR

SHLJSAL

SHR

NOT

NEG

MUL

IMUL

DlV

IDIV

CALL
id

CALL
I,id

JMP
id

JMP
I,id

PUSH

-

VERW

PVAMO

SLOT

STR

LLDT

LTR

VERR

PVAM 1

SGDT

SlOT

LGDT

LlDT

SMSW

PVAM2

-

PVAM3

LSL

PVAM6

CLTS

= is
= short intrasegment
sr = segment register
t = to CPU register

-

-

LMSW

v

w
Z

= variable
= word operation
= zero

Ie
'"
o
'"
'"
OU

",,,,

Segment Override Prefix

if mod = 11 then rim is treated as a REG field
if mod = 00 then OISP = 0', disp-Iow and disp-high are absent
ifmod=Ol then OISP=disp-lowsign extended to 16 bits, disphigh is absent
if mod = 10 then OISP = disp-high: disp-Iow

I

+ (SI) + OISP
(BX) + (01) + OISP
(BP) + (SI) + OISP
(BP) + (01) + DISP
(SI) + OISP
(01) + DISP
(BP) + OISp·
(BX) + DISP

001 then EA =
01 0 then EA =
011 then EA =
EA =
EA =
EA =
EA =

::;;0

ulE
o

0 0 1 reg 1 1 0

Ie

(.)

:E

reg is assigned according to the following:
SEGMENT REGISTER

REG

ES

00
01
10
11

000 then EA = (BX)

100 then
101 then
11 0 then
111 then

= immediate to p.y..
= indirect
=

is
immediate byte sign extension
I = long ie. intersegment
n = 2nd. byte of PVAM instruction
m = memory
rim
EA second byte

si

The Effective Address (EA) of the memory operand is
computed according to the mod and rim fields:

rim =
if rim =
if rim =
if rim =
if rim =
if rim =
if rim =
if rim =

= from CPU reg
= immediate

LAR

Footnotes

if

b = byte operation
d = direct

mod rIm

CS

ss

OS

REG is assigned according to the following table:
16-BIT(w= 1)
000
001
010
011
100
101
110
111

015P follows 2nd byte of instruction (before data is
required)
• except if mod =00 and rim = 110 then EQ=disp-high:
disp-Iow.

. AX

CX
OX
BX
SP
BP
SI

01

8-BIT(w=0)
000
001
010
011
100
1"01
110
111

Al
Cl
Ol

Bl
AH

CH
OH
BH

The physical addresses of all operands addressed by the
BP register are c'omputed using the 55 segment register,
The physical addresses of the destination operands ofthe
string primitive operations (those addressed by the 01
register) are computed using the E5 segment, which may
not be overridden.

4-61

m

80C~86/883

HARRIS

CMOS 16 Bit Microprocessor

June 1989

Features

Description

• .This Circuit Is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
.

The Harris 8DC86/883 high performance 16 bit CMOS
CPU is manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). Two modes of operation,
MINimum for small systems and MAXimum for larger
applications such as multi-processing, allow user configuration to achieve the highest performance level. Full TTL
compatibility (with the exception of CLOCK) and industry
standard operation allow use of existing NMOS 8086
hardware and software designs.

• Compatible with NMOS 8086
• 5MHz Operation ••••••••••••••••••••••••. 80C86/883
• 8M Hz Operation •••••••••••••••••••••• 80C86-2/883
• Low Power Operation
~ ICCSB •••••••••••••••••••••••••••••••• 500IiAMax
~

ICCOP ••••••••••••••••••••••••••• 10mA/MHz Max

• 1MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8 Bit and 16 Bit Signed/Unsigned Arithmetic
~ Binary, or Decimal
~ Multiply and Divide
• Operating Temperature Range •••• -550 C to +1250 C

Pinouts
80C86/883 (CERAMIC DIP)
TOP VIEW
MAX

.

(MINI

80C86/883 (CERAMIC LCC)
TOP VIEW

.
.c

..,

r - c c< c< cc
C

MAX MODE
80C86

or'

cC

MIN MOO';80(88

..c
c

..,

cc

8 • 15
4 I
..• _~
.. _~••10_"

3 I "_01
'2 I
"_,,
I

r-

<

r-

1 • 10_01
-44- "_01
'43' '42'
L_J
10_'" '41
,,_"'~ :40'
10_'"
•

ADI

16'

'30
L_

,ADO

ADO

.

p-

ADI

_
17'

L_

ADS

A08

A08

AD7

AD7

AD6

AD6

AD'

AD'

(OT/AI

AD'

AD'

(DENI

AD3

AD3

(AUCI

AD2

(WRI

(INTAI

"z "g

z,

co

c

AD2

ADS

(M/iOl

c

..C @.. ~ !!....
..C !!.:c.., '"..:c ...,!!:c
:c :c :c

.
..
"'_.
.",.
_.

A010

(HLOAI

"z "">

p-

AD10

(HOLDI

n-,

<

c

z
co

'3.
L_

NC

NC

p-

_

8 •

L _ A19/88 A19/88
"8

~J

L.

-,
-,

p-

'37

BHE/S

BHE 187

L
_
138
MN/MX

MN/MX

p-

_
-,
_

10'

p-

L
'35
_

-,

AD

AD

HOLD

Ra/GTO

HLDA

RO

p-

'34
L_

12'

-,

p-

-,
_

p-

_
13'

L
'33
_
L
_
'32

-

WR

p-

1~1

'31
L_

-,
_.
-,

r;g

M/iO

-

01 fA
DEN

1m

-

LOCK

52

S1
-SO

r-., r-, r-, r-, r-' r-, r-, r-, r-, r-, r-,
11811191120112111221123112411251126112711281

"z

:i
z

...;!;a:

"z

:i

...;!;a:

Copyright @ Harris Corporation 1989

4-62

z

~

"
~
"

tu

z
co

c

"z '"a:w

c

"z 'a:w"

z

co

tu

c>cw
a:
c>-

::ia:

I§ I~
I~

0;

a

, MljMODE)
..
...Cw !---< 60C86MAX MODE

~

a

~80C88

80C86/883
Functional Diagram
EXECUTION UNIT

I

REGISTER FilE

BUS INTERFACE UNIT
RELOCATION I
I I REGISTER
FILE
SEGMENT
REGISTERS &

OATA.
POINTER. &

INSTRUCTION

INDEX REGS

POINTER
(5 WORDS)

(BWORDS)

,-""""-'L~ BHEIS,
A'9 iS6
A'6ISJ

AD'5-AD O

FLAGS

L--rr---I----V

DTiR. ill. ALE. MilO

6-BYTE
INSTRUCTION
QUEUE

TEST - - - ' - - - - - - - : : " " ' - - - - - - ,
INTR
NMI
MIGTO.l
HalO
HlDA ~---,--,.----r--_._-__r-..".,,-I

ClK

RESET REAOY MNIMx GND
VCC

OSO. OS,

S2.S,.So

'"a::
'"
'"
0""
o

",'"

:;;0

...,g:
o

a::
...,

iii

BUS
INTERFACE
UNIT

SS
OS
lP
A-BUS

EXECUTION
UNIT

AH
BH
CH
DH

Al
Bl
Cl
Dl
SP
BP
SI
DI

4-63

80C86/883
Pin Description

"

The following pin function descriptions are for BOCB6/BB3
systems in either minimum or maximum mode. The "Local
Bus" in these descriptions is the direct multiplexell bus

interface connection to the BOCB6/BB3 (without regard to
additional bus buffers).

"

SYMBOL

PIN
NUMBER'

TYPE

AD15-AOO

2-16,39

I/O

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1)
and data (T2, T3, TW, T4) bus, AO Is analogous to BHE for the lower byte olthe data bus, pins
07-00. Ills lOW during n when a byte is to be transferred on the lower portion olthe bus in
memory or I/O operations, Eight-bit oriented devices tied to the lower half would normally
use AD to condition chip select functions (See BHE). These lines are active HIGH and are
held at high impedance to the last valid logic level during interrupt acknowledge and local
bus "hold acknowledge" or "grant sequence".

A19/S6
A18/S5
A17/S4
A16/S3

35-38

0

ADDRESS/STATUS: During n, these are the four most significant address lines for
memory operations. Dur.ing I/O operations these lines are LOYI/. During memory and I/O
operations, status information is avaiiablEi on these lines during T2, T3, TW, T4. S6 is always
LOW. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each
clock cycle. S4 and S3 are encoded as shown.

DESCRIPTION

This information indicates which segment register is presently being used for data
accessing.
These lines are held at high impedance to the last valid logic level during local bus "hold
acknowledge" or "grant sequence".

BHE/57

RD

34

32

0

0

S4

S3

0
0
1
1

0
1
0
1

CHARACTERISTICS
Alternate Data
Stack
Code or None
Data

BUS HIGH ENABLE/STATUS: During n the bus high enable signal (BHE) should be used
to enable data onto the most significant half of the data bus, pins D15 cD8, Eight bit oriented
devices tie~he upper half of the bus would normally use BHE to cOndition chip select
functions. BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a
byte is to be transferred on the high portion of the bus, The S7 status information is available
during T2, T3 and T4. The signal is active LOW, and is held at high Impedance to the last
valid logic level during interrupt acknowledge and local bus "hold acknowledge" or "grant
sequence"; it is LOW during n for the first interrupt acknowledge cycle.
BHE

AO

0
0

0
1

1

0

1

1

CHARACTERISTICS
Whole word
Upper Byte from/lo
odd address
Lower byte from/to
even address'
'None

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle,
depending on the state of the M/Io or 52 pin. This signal is used to read devices which reside
on the 80C86/883 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is,
guarl!nteed to remain HIGH in T2 until the 80C86/883 local bus has floated.
This line Is held at a high impedance logic one state during "hold acknowledge" or "grant
sequence".

READY

22

I

READY: is the acknowledgement from the addressed memory or I/O device that will complete the data transfer. The ROY signal from 'memory or'I/O is synchronized by the 82CB4A
Clock Generator to form READY. This signal is active HIGH. The BOC86/8B3 READY input is not
synchronized. Cor~t operation Is not guaranteed if the Setup and Hold Times are not mel

INTR

18

I

INTERRUPT REQUEST: is a level triggered Input which is sampled during the last clock
cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in
system memory. It can be intemally masked by software resetting the interrupt enable bil
INTR.is internally synchronized. This signal Is active HIGH.

--4:-64

.

80C86/883
Pin Description

(Continued)

The following pin function descriptions are for 80C86/883
systems in either minimum or maximum mode. The "Local
Bus" in these descriptions is the direct multiplexed bus

SYMBOL

PIN
NUMBER

TYPE

interface connection to the 80C86/883 (without regard to
additional bus buffers).

DESCRIPTION

TEST

23

I

TEST: input is examined by the "Wail" instruction. If the TEST input is LOW execution continues, otherwise the processor wails in an "Idle" state. This input is synchronized internally
during each clock cycle on the leading edge of CLK.

NMI

17

I

NON-MASKABLE INTERRUPT: 'is an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI
is not maskable internally by software. A transition from LOW to HIGH initiates the interrupt
at the end of the current instruction. This input is internally synchronized.

RESET

21

I

RESET: causes the processor to immediately terminate its present activity. The signal must
transition LOW to HIGH and remain active HIGH for at least four clock cycles. I! restarts
execution, as described in the Instruction Set description, when RESET returns LOW. RESET
is internally synchronized.

CLK

19

I

CLOCK: provides the basic timing for the processor and bus controller. I! is asymmetric with
a 33% duty cycle to provide optimized internal timing.

VCC

40

GND

1,20

MN/MX

33

VCC: +5V power supply pin. A 0.1 ~F capacitor between pins 20 and 40 is recommended for
decoupling.
GND: Ground. Note: both must be connected. A 0.1
recommended for decoupling.
I

~F

capacitor between pins 1 and 20 is

MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes
are discussed in the following sections.

The following pin function descriptions are for the 80C86/
883 in minimum mode (Le. MN/MX = VCC). Only the pin

functions which'are unique to minimum mode are described; all other pin functions are as described below.

a:
'"
o
'"
'"
"'w
0<">

::;:0

<..>g:

MINIMUM MODE SYSTEM

o

a:
<..>

SYMBOL

PIN
NUMBER

TYPE

M/IO

28

0

STATUS LINE: logically equivalent to S2 in the maximum mode. I! is used to distinguish
a memory access from an I/O access. MiiiS becomes valid in the T4 preceding a bus
cycle and remains valid until the finaIT4 of the cycle (M = HIGH,IO = LOW). M/iiS is held to
a high impedance logic One during local bus "hold acknowledge".

WR

29

0

WRITE: indicates that the processor is performing a write memory or write I/O cycle,
depending on the state of the M/TO signal. WR is active for T2, T3 and TWof any write
cycle. I! is active LOW, and is held tq high impedance logic one during local bus "hold
acknowledge".

INTA

24

0

INTERRUPT ACKNOWLEDGE: is used as 2 read strobe for interrupt acknowledge
cycles. I! is active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note
that INTA is never floated.

ALE

25

0

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the
82C82/82C83 address latch. It is a HIGH pulse active during clock LOW ofT1 of any bus
cycle. Note that ALE is never floated.

DT/R

27

0

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data
bus transceiver. It is used to control the direction of data flow through the transceiver.
Logically, DTiii is equivalent to 51 in maxim'um mode, and its timing is the same as for
M/iO (T = H'IGH, R = LOW). DTiRis held toa high impedance logic one during local bus
"hold acknowledge".

DEN

26

0

DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system
which uses the transceiver. DEN is active LOW during each memory and I/O access and
for INTA cycles. For a read or INTA cycle it is active from the middle of T2 until the middle
ofT4, while for a write cycle it is active from the beginning ofT2 until the middle ofT4.
DEN is held to a high impedance logic one during local bus "hold acknowledge".

DESCRIPTION

:E

80C86/883
Pin Description

(Continued)

The following pin function" descriptions are for the 80C8S1
883 in minimum mode (i.e. MN/MX = VCC). Only the pin

functions which are unique to minimum mode are
described; ali other pin functions are as "described below.

MINIMUM MODE SYSTEM (Continued)

SYMBOL

PIN
NUMBER

HOLD
HLDA

31,
30

TYPE
I

0

DESCRIPnON
HOLD: Indicates that another master Is requesting a'iocal bus "hold". To be a acknowledged, HOLD must be active HIGH. The processor receiving the "hold" will issue a "hold
acknowledge",(HLDA) In the middle of a T4 orTI clock cycle. Simulteneously wilh the
issuance of HLDA, the processor will float the local bus and control lines. After HOLD Is "
detected as being LOW, the processor will lower HLDA, and when the processor needs
10 run another cycle, It
again drive the iOeal bus and control lines.

will

HOLD is not an asynchronous Input. External synchronization should be provided if Ihe
system cannot otherwise guarantee the setup time.

The following pin function descriptions are for the 80C8S1
883 system in maximum mode (i.e., MN/MX '= GND). Only

the pin functions which are unique to maximum mode are
d!lscribed below:

MAXIMUM MODE SYSTEM

piN
SYMBOL

NUMBER

TYPE

SO

26
27
2B

0
0
0

51
52

DESCRIPnON
STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during
T3 or during TW when READY is HIGH. This status is used by the B2CBB Bus Conlroller to
generate all memory and I/O access control signals. Any changa by 52, 51 or SO during T 4 Is
used to indicate thE! beginning of a bus cycle, and the return to the passive state in T3 or TW
Is used to Indicate the end of a bus cycle.
These Signals are held at a high impedance logic one stete du~lng "grant sequence".
S2

S1

SO

0
0
0
0

0
0

0

1
1

0

1
1
1

0
0

0

1
1

0

1
RQ/GTO
RQ/GT1

31,30

I/O

1
1
1
1

CHARACTERISTICS
Interrupt Acknowledge
Read I/O Port
Write I/O Port
"
Halt
Code AcCess
" Read Memory
Write Memory
Passive

",

REQUEST/GRANT: pins are uSed by other local bus masters to force the processor to
release the local bus at thE! end of the processor's current bus cycle. Each pin is bi-directional
with RQ/GTO having higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold
device so it may be left unconnected. The requesVgrant sequence is as follows (see RQ/GT
Sequence Timing)

'"

1. A pulse of 1 CLK wide from another local bus master indicales a local bus request
("hold") to the BOCB6/BB3 (pulse 1).
""
2. During-a T4 or1l clock cycie, a pulse 1 CLK wide from the BOCB6tB831c? the requesting
master (pulse 2) indicates that the BOCB6/BB3 has allowed the local bus to f10al and that it
wni enter the "grant sequence" sti.te at the next eLK. The CPU's bus Interface unit is
disconnected logically from the local bus during "grant sequence".
3. A puise 1 CLK wide from the requesting master indicates to the BOCB6/BB3 (pulse 3) that
the "hold" request Is about to"end and that ihe BOCB6/BB3 can reclaim the local bus at the
n,ext CLK. The CPU then enters T 4 (or:1 if no bus cYcles pending),
Each Master-Master exchange of the local bus is a sequence of 3"pulses. There must
be one.ldle CLK cycle after each bus exchange. Pulses are active low.

4-66

80C86/883
Pin Description (Continued)
The following pin function descriptions are for the 80C86/
883 system in maximum mode (i.e., MN/MX = GND). Only

the pin functions which are unique to maximum mode are
described below.

MAXIMUM MODE SYSTEM (Continued)

SYMBOL

PIN
NUMBER

TYPE

DESCRIPTION
If the request is made while the CPU is performing a memory cycle, it will release the
local bus during T4 of the cycle when all the following conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next cycle.
2. A memory cycle will start within three clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

LOCK

29

0

LOCK: output indicates that other system bus masters are not to gain control of the system
bus while LOCK is active LOW. The LOCK Signal is activated by the "LOCK" prefix instruction and remains active until the completion of the next instruction. This signal is active
LOW, and is held at a high impedance logic one state during "grant sequence". In MAX
mode, LOCK is automatically generated during T2 of the first INTA cycle and removed during T2 of the second INTA cycle.

QS1,QSO

24,25

0

QUEUE STATUS: The queue status is valid during the ClK cycle after
which the queue operation is performed.
QS1 and QSO provide status to allow extemal tracking of the internal
80C86/883 instruction queue. Note that QS1, QSO never become high impedance.
aS1

aso

0
0

0
1

1
1

0
1

a:

'"
CI)

Cl)W

No Operation
First byte of op code
from queue
Emptythe Queue
Subsequent byte from
queue

4-67

CI)

o

0<'>
::0;0

c..>g:
o

a:
c..>

:E

Specifications 80C86/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •.••.••......•..••••.••••••••••••••••.•• +8.0V
Input, Output or I/O Voltage Applied. . . •. GND':O.SV to VCC+O.SV
Storage Temperatura Range .••.••••..••••.•• -6So C to +lS00 C
Junction Temperature •••.••.•.••.••..••••.•••.•.••••• +17So C
Lead Temperature (Soldering 10 sec) ••.•••..•...••...•• +3000 C
ESD Classification .•••••••.•••••••••••.••.••••••••..•• Class 1

Sjc
Thermal Resistance
Sja
Ceramic DIP Package ••••.•••.•..•...• 27.S0 C/W S.90C/W
Ceramic LCC Package. • . . • • • • • • • • • . •• 62.20 C/W 8.60 C/W
Maximum Package Power Dissipation at +12So C
Ceramic DIP Package ••••..•........•....•.••...... 620mW
Ceramic LCC Package •••.••.•••.•.••••.•..•••••••. 664mW
Gate Count .••...............................•... 97S0 Gates

CAUTION: Stresses above those listed in ''Absolute Maximum Ratings" may cause permanent damage to the devics. This is a stress only rating and operation
of the device at these
any other conditions above" those indicated in' the operational sections of this specification is not implied.

or

Operating Conditions
Operating Supply Voltage ••••••.•.••••••••••.•• +4.SV to +S.SV
80C86-2/883 ONLY. • . . • • • • • • • . • • • . • • • • •• +4.7SV to +S.2SV'

Operating Temperature Range .•.••••.•••••.• -SSoC to +12S oC

TABLE 1. 80C86/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested, 80C86/883: VCCL = 4.SV, VCCH = S.SV, fmax = SMHz;
80C86-2/883· VCCL - 47SV, VCCH - S 2SV fmax - 8M Hz

-

(NOTE 1)

GROUP A
SUBG'ROUPS

-

UMITS
TEMPERATURE

MIN

MAX

UNITS

Logical One Input
Voltage

VIH

VCC = VCCH, Note 2

1,2,3

-ssOCgA:5.+12SOC

2.2

-

V

Logical Zero Input
Voltage

VIL

Note 2

1,2,3

-SSoCSTA:5.+12SoC

-

0.8

V

VCC=VCCH

1,2,3

-SSOCSTA:5.+12S0C

VCC-0.8

-

V

1,2;3

-SSOC:5.TA:5.+ 12SoC

-

0.8

V

10H = -2.SmA, Note 3
10H = -100pA, Note 3

1,2,3
1,2,3

-SSOC:5.TA:5.+12S0C

3.0
VCC-O.4

-

-

V
V

PARAMETER

SYMBOL

CLK Logical One Input
Voltage

VIHC

CLK Logical Zero Input
Voltage

VILC

Output HIGH Voltage

VOH

Output LOW Voltage

VOL

Input Leakage Current

"

CONDITIONS

10L = +2.SmA, Note 3

1,2,3

-SSOC:5.TA:5.+12S0C

-

0.4

V

VCC=VCCH,
V1N = GND orVCC
DIP Pins: 17-19,21-23,
33

1,2,3

-ssoCgA:5.+12SOC

-1.0

+1.0

pA

Input Current Bus
Hold High

IBHH

VIN = 3.0V, Note 4
VCC = VCCL & VCCH

1,2,3

-SSOCSTA:5.+12S0C

-40

-400

pA

Input Current Bus
Hold Low

IBHL

VIN = O.8V, Note S
VCC = VCCL & VCCH

1,2,3

-ssoCgA:5.+12SOC

40

400

pA

VCC=VCCH,
VOUT = 0\1, Note 6

1,2,3

-ssoCgA:5.+12S0C

-

-10

pA

Output Leakage Current

10

Standby Power Supply
Current

ICCSB

VCC = VCCH, Note 7

1,2,3

-SSoC:5.TA!S.+12S0C

-

SOO

pA

Operating Power Supply
Current

ICCOP

VCC = VCCH, f = fmax,
VIN=VCCorGND,
Outputs Open

1,2,3

550 CgA:5.+12S0C

-

10

mNMHz

NOTES: 1. All voltages referenced to device GND, vee = VCCL unless otherwise specified.
2. MN/MX is a strap option and should be held to vee or GND.
3. Interchanging of force and sense conditions is permitted.
4. IBHH should be measured after raising VIN to vee and then lowering to valid input high level of 3.0V on the following pins: 2-16, 26-32, 34-39.
5. IBHL should be measured after lowering VIN to GND and then raising to valid input low level of O.8V on the following pins: 2-16, 34-39.
6. 10 should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29. 32.
7. leeSB tested during clock high time after HALT instruction execution. VIN = vee or GND, vec = VeCH, outputs unloaded.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

4-68

Specif.ications 80Ca6/883
TABLE' 2. SOCBS/SS3 A.C. ELECTRICAL PERFORII('IAI)ICE CHARACTERISTICS
Device Guaranteed and 100% Tested, 80C86/88S: VCCL = 4.5V, VCCH =.5.5V, . 80C86-2/88S: VCCL = 4.75V, VCCH = 5.25V

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

GROUP A
SUBGROUPS

SOCS6-2/SS3

SOCSS/SS3

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

200

-

ns

118

-

ns

69

-

ns

MINIMUM COMPLEXITY SYSTEM TIMING
CLK Cycle Period

(1)TCLCL

9',10,11

-550CgA!!O+ 1250C

125

CLKLowTime

(2)TCLCH

9,10,11

-550C~AS.+1250C

'68

CLK High lime

(S)TCHCL

9,10,11

-550C~A~+1250C

44

-

Data In Setup Time

(6)TDVCL

9,10,11 .

-550C~A~+1250C

20

-

30

-

ns

Data In Hold lime

(7)TCLDX1

9,10,11

-55OC9A~+1250C

10

-

10

-

ns

READY Setup Time
into 80C86/883

(10)TRYHCH

9,10,11 .

-550C~A~+1250C

68

-

118

-

¥IS

READY Hold lime
into 80C86/883

(11)TCHRYX

9,10,11

-550C~A~+1250C

20

-

30

-

ns

READY Inactive
toCLK

(12)'rRYLCL

Note 2

9,10,11

-550Cg~+1250C

-8

-

-8

-

ns

9,10,11

-550C~~+1250C

20

NoteS

9,10,11

-550C~~+1250C

15

-

SO

-

HOLO Setup lime

(1S)THVCH

INTR, NMI, TEST
Setup Time

(14)TINVCH

S5

ns
ns

Address Valid Delay

(17)TCLAV

9,10,11

-550C~~+1250C

10

60

10

110

ns

Address Hold lime

(18)TCLAX

9,10,11

-55OC9~+125OC

10

-

10

-

ns

ALE Width

(22)TLHLL

9,10,11

-55OC9A~+1250C

TCLCH
-10

TCLCH
-20

-

ns

ALE Active Delay

(2S)TCLLH

9,10,11

-55OC9A~+1250C

-

50

80

ns

ALE Inactive Delay

(24)TCHLL

9,10,11

-5f?oC9~+125OC

..,

55

Address Hold lime
to ALE Inactive

(25)TLLAX

9,10,11

~550C~~+1250C

TCHCL
-10

-

-

-

85

ns

TCHCL
-10

-

ns

(26)TCLDV

9,10,11

-550C9A~+1250C

10

60

10

110

ns

Control Active.
Delay 1

(29)TCVCTV

9,10,11

-550Cg~+1250C

10

70

10

110

ns

Conlrol Active
Delay 2

(SO)TCHCTV

9,10,11

-550CgA~+1250C

10

60

10

110

ns

Control Inactive
Delay

(31)TCVCTX

9,10,11

-550C~TA~+1250C

10

70

10

110

ns

Address Float to
RDActiv~ ..

(S2)TAZRL

9,10,11

-550C~TA~+1250C

0

-

0

-

ns

RD Active Delay

(SS)TCLRL

9,10,11

-550Cg~+1250C

10

100

10

165

ns

RD Inactive Delay

(S4)TCLRH

9,10,11

-550C9A~+1250C

10

80

10

150

ns

RD 'Inactive to Next
Address Active

(S5)TRHAV

9,10,11

-550Cg~+1250C

TCLCL
-40

TCLCL
-45

-

ns

160

ns

-

ns

-

ns

Data Valid Delay

-

HLDA Valid Delay

(S6)TCLHAV

9,10,11 .

-550CgAS.+.1250C

10

100

10

RDWidth

(37)TRLRH

9,10,11

-550C9~+1250C

2
TCLCL
-50

-

2
TCLCL
-75

WRWidlh

(S8)TWLWH

9,10,11

-550CgA~+1250C

2

-

TCLCL
-40
NOTES. 1. VCC VCCL, CL 100pF, f 1MHz
2. Applies only to T2 state (8ns into T3)
3. Setup requirement for asynchronous signal only to guarantee recognition at next clock.
CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

4-69

2
TLCL
-60

Specifications 80C86/883
TABLE 2. 80C86/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Device Guaranteed and 100% Tested , 80C86/883' VCCl = 45V., VCCH = 55V. 80C86-2/883' VCCl = 475V. VCCH = 525V

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

80C86-2/883

80C86/883

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

9,10,11

-55ocgA:S+1250C

TClCH
-40

-

TClCH
-60

-

ns

MINIMUM COMPLEXITY SYSTEM TIMING
Address Valid to
ALE low

(39)TAVAL

Output Rise Tome

(40)TOlOH

FromO.8V
102.0V

9,10,11

-55ocgA:S+1250C

-

15

-

20

ns

Output Fall Time

(41)TOHOl

From2.0V
100.8V

9,10,11

-55ocgA~+1250C

-

15

-

20

ns

NOTES: 1. VCC - VCCL. CL = 100pF. f - 1MHz
2. Applies only to T2 stale (8ns inlo T3)
3. Setup requirement for asynchronous signal only to guarantee recognition at next clock.

TABLE 3. 80C86/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
8OC86/883: VCCl = 4.5V, VCCH = 5.5\1, 8OC86-2/883: VCCl = 4.75\1, VCCH = 5.25V

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

80C86-2/883
NOTES

TEMPERATURE

1

TA=+25OC

1
1

80C86/883

MIN

MAX

MIN

MAX

UNITS

25

25

pF

TA=+25OC

-

25

pF

TA=+250C

-

25

25

pF

10

ns

MINIMUM COMPLEXITY SYSTEM TIMING

CLK Rise Tome

TCH1CH2
(4)

From 1.oV to 3.5V

1

-55ocgA~+1250C

-

10

-

ClK Fall Time

TCL2Cl1
(5)

From 3.5V to 1.0V

1

-550CgA~+1250C

-

10

-

10

ns

ROY Setup Tome
In1082C84A

TR1VCl
(8)

Cl= 100pF,
VCC=VCCl,
f=1MHz

1,2,3

-550CgA:S+1250C

35

-

35

-

ns

ROY Hold Time
InIo82C84A

TClR1X
(9)

Cl=100pF,
VCC=VCCl,
f=1MHz

1,2,3

-550CgA:S+12SOC

0

-

0

-

ns

Input Rise Time
(Except ClK)

TIUH
(15)

From 0.8VIo 2.oV

1

-550CgA:S+1250C

-

15

-

15

ns

Input Fall Tome
(Except ClK)

TIHll
(16)

From 2.0V to O.8V

1

-550CgA~+1250C

-

15

-

15

ns

CL= 100pF,
VCC=VCCl,
f= 1MHz

1

-550CgA:S+1250C

TCLAX

50

TCLAX

80

ns

Input Capacltsncs
Output Capacitancs

VO Capacitance

CIN
COUT
CVO

f= 1 MHz, All
measurements are
referenced
deviceGND

25

Address Float Delay

TCLAZ
(19)

Status Roat Delay

TCHSZ
(20)

1

-55ocgAS+1250 C

-

50

-

80

ns

Data Hold Time

TCLDX2
(27)

1

-550CgA:S+1250C

10

-

10

-

ns

Data Hold Time
AfterWR

TWHDX
(28)

1

-550CgA~+1250C

TClCl
-30

-

TClCl
-30

-

ns

NOTES: 1. The parameters listed in Table 3 ara controlled via design or process parameters and are not directly tested. Thesa parameters are characterized upon
inillal design and after major process andfor design changes.
2. Signal al 82C84A shown for referenca only.

3. Setup requirement for asynchronous Signal only to guarantee recognition at next clock.

CAUTION: Thase davieas are sensHive to electroniC discharge. Proper IC handling procadures should be followed.

4-70

-

Specifications 80C86/883
TABLE 4 APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

InilialTest

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3,BA,BB,10,ll

-

l,2,3,7,BA,BB,9,10,ll

Samples/5005

1,7,9

Group A
GroupsC&D

Waveforms
TW

~H rTCL2:r~

_TCLCL----+

-J
TCHC

Milo

~

r--"

CLK (82C84A OUTPUT!

T~x

"---'

1----+

TCH1CH2

TCHCL

-

l\

'-----.i

~

TCLCH

TCHCTV

-I
TCLAV

........

TCLOV
TCLAX

TCLLH....

I:

TLHLL=t

ROY (82C84A INPUT!

S7-53

1\

ALAX

tTCHLL~

ALE

........

I: :

BHE,A19-A 16

/

........

TR1VCL

~\\\~\\~ ~\\\\~ ~~\\~~~

1-

1

TR~~

.~"' ,.... ,~" {

L

~

V'7_~~
VIL

~TAVAL.

SEE NOTE 3

1

-

!+-TCLRIX

1 -

_TCHRYX

-=.j TRYHCH 1*-'
- - TCLAZ

1---

AOIS-AOO

~

TAZRL....

READ CYCLE

(WR, INTA

-,

~TCHCTV

=VOH)
DT/R

lrTCLRL I

TCVCTV-+

r--

X

n
t

j

TCLOXI

TOVCL
OATAIN
T;;;;A:J=

TCLRH

Jt
~

TRLRH

TCVCTX_

1-

f-TCHCTV

I

NOTES: 1. ROY is sampled near the end of T2, T3. Tw to determine if Tw machine states are to be inserted.
2. Two INTA cycles run back-la-back. The aOCa6/aa3 local AD DR/DATA bus is floaling during both INTA
cycles. Control Signals are shown for the second i'N'TA cycle.
3. Signals at 82C84A are shown for reference only.
4. All timing measurements are made at 1.5V unless otherwise noted ..

4-71

TCL AV

r

80C86/883
Waveforms

(Continued)

BUS TIMING - MINIMUM MODE SYSTEM (Continued)

T,

TW

ClK 182C84A OUTPUT)

AD,S-ADO

WRITE CYCLE
IRo'lNTA'j
DT/R· VDH)

liiiTA CYCLE
NOTE 2
IRD, Wii = VOH
BHE'VOl

SOFTWARE
HALTDEN,RD,
WR, iiiiTA· VOH
DT/R

DT/R

-4--~~--~----~---4~~--------~~--~*--------

+_1 ,_..,...__+ ___-+__-+ SOFTWARE HALT

AD'S-ADO _.&-_ _

= INDETERMINATE

NOTES: , •. ROY i. sampled naar tha and of T2. T3. Tw to datarmlna • Tw machlna statal are to balnsarted.
2. Two iNTA cycles run back-to-bsck. The 8OC86/883 local ADDR/DATA bus is flosting during both INTA
cycles. Control Signals are shown for the second INTA cycle.
3. Signals at 82C84A are shown for reference only.
4. All timing maasurements are mada at '.SV unlass otharwise noted.

4-72

Specifications 80C86/883
TABLE 2. 80C86/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested, 80C86/883: VCCL

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

= 4.5V, VCCH = 5.5V,

GROUP A
SUBGROUPS

80C86-2/883: VCCL

= 4.75V, VCCH = 5.25V

80C86-2/883
TEMPERATURE

MIN

80C86/883

MAX

MIN

MAX

UNITS

-

200

-

ns

MAXIMUM MODE SYSTEM TIMING (USING 82C88 BUS CONTROLLER)
CLK Cycle Period

(1)TCLCL

9,10,11

-550CsrA~+1250C

125

CLKLowTime

(2)TCLCH

9,10,11

-550CsrA~+1250C

68

CLK High Time

(3)tCHCL

9,10,11

-550C'::;TA~+1250C

44

Data In Setup Time

(6)TDVCL

9,10,11

-550 CsrA<+1250C

20

Data In Hold Time

(7)TCLDX1

9,10,11

-550CsrA~+1250C

10

READY Setup Time
into 80C86/883

(10)TRYHCH

9,10,11

-550C~TA~+1250C

READY Hold Time
into 80C86/883

(11)TCHRYX

9,10,11

READY Inactive
toCLK

(12)TRYLCL

Note 2

Setup Time For
Recognition (INTR,
NMI, TEST)

(13)TINVCH

Note 3

RO/GT Setup Delay

(14)TGVCH

'RO Hold Time Into
80C86/883

(15)TCHGX

READY Active to
Status Passive

(20)TRYHSH

-

68

-

118

-

-55OCsrA~+1250C

20

-

30

-

ns

9,10,11

-550CsrA~+1250C

-8

-

-8

-

ns

9,10,11

-550CsrA~+1250C

15

-

30

-

ns

118
69
30
10

ns
ns
ns
ns
ns

9,10,11

-550C'::;TA~+1250C

15

-

30

-

ns

Note 4

9,10,11

-550CsrA~+1250C

30

TCHCL
+10

40

TCHCL
+10

ns

Notes 2,5

9,10,11

-550C'::;TA~+1250C

-

65

-

110

ns

9,10,11

-550CsrA~+1250C

10

60

10

110

ns

9,10,11

-550CsrA:$.+1250 C

10

70

10

130

ns

(23)TCLAV

9,10,11

-550 CsrA:$.+1250 C

10

60

10

110

ns

(24)TCLAX

9,10,11

-550 C.::;TA:$.+1250C

10

-

10

-

ns

(33)TCLDV

9,10,11

-550 CsrA:$.+1250 C

10

60

10

110

ns

0

-

0

-

ns

Status Active Delay

(21)TCHSV

Status Inactive Delay

(22)TCLSH

Address Valid Delay
Address Hold Time
Data Valid Delay

Note 5

-

Address Floatto
Read Active

(37)TAZRL

9,10,11

-550 C.::;TA:$.+1250C

RD Active Delay

(38)TCLRL

9,10,11

-550 C.::;TA:$.+1250C

10

100

10

165

ns

RD Inactive Delay

(39)TCLRH

9,10,11

-550 C.::;TA:$.+1250C

10

80

10

150

ns

RD Inactive to Next
Address Active

(40)TRHAV

9,10,11

-550CsrA~+1250C

TCLCL
-40

-

TCLCL
-45

-

ns

GT Active Delay

(43)TCLGL

9,10,11

-550CsrA:$.+1250 C

0

50

10

85

ns

GT Inactive Delay

(44)TCLGH

9,10,11

-550 CsrA:$.+1250C

0

50

10

85

ns

RDWidth

(45)TRLRH

9,10,11

-550CsrA~+1250C

2
TCLCL
-50

-

2
TCLCL
-75

-

ns

Output Rise Time

(46)TOLOH

FromO.8V
t02.0V

9,10,11

-550 C.::;TA:$.+1250C

-

15

-

20

ns

Output Fall Time

(47)TOHOL

From2.0V
toO.8V

9,10,11

-550CsrA~+1250C

-

15

-

20

ns

NOTES: 1.
2.
3.
4.
5.

VCC = VCCL, CL = 100pF, f = 1MHz
Applies only to T2 stale (8ns Into T3)

Setup requirement for asynchronous signal only to guarantee recognition at next clock.
The BOeS6/8S3 actively pulls the RQ/GT pin to a logic ona on the following clock low time,
Status lines return to their inactive (logic one) state after elK gOBS low and READY goes high.

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

4-73

D:
'"
o

'"
'"
"'w

0<'>

::;:0

<.>g:
o
D:
<.>

:s

Specifications 80C86/883
TABLE 3., BOCB6/BB3 ELECTRICAL PERFORMANCE CHARACTERISTICS '
8OC86/883' VCCl = 4 511:, VCCH = 5 511:, 8OC86-2/883' VCCl = 47511:, VCCH = 5 25V

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

8OCB6-2/B83
NOTES

TEMPERATURE

MIN

8OC86/883

MAX

MIN

MAX

UNITS

25

-

25

pF

25

-

25

pF

25

25

pF

10

-

10

ns

MAXIMUM MODE SYSTEM TIMING (USING 82C88 BUS CONTROLLER)

CLK Rise Tome

TCH1CH2
(4)

From 1.0Vt03.5V

1

-550CgA:5+1250C

-

ClK Fall Time

TCl2Cl1
(5)

From 3.5V to 1.0V

1

-55OCSTA:5+1250C

-

10

-

10

ns

ROY Setup Tome
Into 82CB4A

TR1VCl
(8)

Cl=100pF,
VCC=VCCl,
f=1MHz

1,2,3

-550CgA:5+1250C

35

-

35

-

ns

ROY Hold Time
Into 82C84A

TCLR1X
(9)

CL=100pF,
VCC=VCCl,
f=1MHz

1,2,3

-550CSTA:5+1250C

0

-

0

-

ns

Input Rise Time
(Except ClK)

TIUH
(16)

From 0.8V to 2.0V

1

-550CSTA:5+1250C

-

15

-

15

ns

Input Fall Time
(Except ClK)

TIHll
(17)

From 2.0V to 0.8V

1

-55OCSTA:5+1250C

-

15

-

15

ns

1,2

-55OCSTA:5+1250C

5

35

5

35

ns

Input Capacitance
Output Capacitance
I/O CapaCitance

CIN
COUT
COO

f=1MHz,AII
measurements are
referenced
devlceGND

1

TA=+25OC

1

TA=+250C

1

TA=+250C

Command Active
Delay

TClMl
(18)

Cl=100pF,
VCC=VCCl
f=1MHz

Command Inactive
Delay

TClMH
(19)

1,2

-550CSTA~+1250C

5

35

5

35

ns

Address Float
Delay

TCLAZ
(25)

1

-550C:s.TA:5+12SOC

TCLAX

50

TCLAX

80

ns

80

ns

20

ns

(26)TCHSZ

1

-55OC:sTA$+1250C

Status Valid To
ALE High

TSVlH
(27)

1,2

-550C:sTA:5+1250C

-

Status Valid To
MCEHlgh

TSVMCH
(28)

1,2

-550CgA~+1250C

ClKlowTo
ALE Valid

TCllH
(29)

1,2

ClKlowTo
MCEHigh

TClMCH
(30)
(31)TCHLL

Status Float Delay

ALE Inaclive Delay

MCE Inaclive Delay (32)TClMCl

20

-

-

30

-

30

ns

-550CSTA:5.+125OC

-

20

-

20

ns

1,2

-55OCSTA:5.+125OC

-

25

-

25

ns

1,2

-550C9A:5.+1250C

4

18

4

18

ns

1,2

-550CgA:5+1250C

-

15

-

15

ns

50

Data Hold Time

(34)TClDX2

1

-550CgA:5.+1250C

10

-

10

-

ns

Control Active
Delay

TCVNV
(35)

1,2

-550CgA:5.+1250C

5

45

5

45

ns

Control Inactive
Delay

TCVNX
(36)

1,2

-55OC:5TA:5+1250C

10

45

10

45

ns

Direction Control
Active Delay

(41)TCHDTL

1,2

-550CgA:5.+1250C

-

50

-

50

ns

Direction Control
Inactive Delay

(42)TCHDTH

1,2

-550CgA~+1250C

-

30

-

30

ns

NOTES: 1. The parameters listed In Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon
initial design and after major process and/or design changes.
2. Signal aI 82C84A or 82C88 shown for reference only.
3. Setup requirement for asynchronous signal only to guarantee recognition at next clock.
CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.

4-74

Specifications 80C86/883
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3,8A, 8B, 10, 11

Group A

-

1,2,3, 7,8A,8B,9, 10, 11

Samples/500S

1,7,9

GroupsC&D

Waveforms
BUS TIMING - MAXIMUM MODE (USING 82C88)

"

52.51,SO (EXCEPT HAL TI

en

I

a:

o

ALE IB2eBS OUTPUT!

NOTE 4

en
en
W

en
oc..>
:eO
c..>g:
o
a:
c..>
~

ROY 182C84 INPUT!

READY,"OC'''N'""

I

DT/ii
82C88

OUTPUTS

Mii6C OR iOiiC

SEE NOTES
~,

NOTES: 1. ROY is sampled near the end of T2, T3. Tw to determine if Tw machine states are to be inserted.

iNTA

2. Cascade address is valid between first and second
cycles.
3. Two INTA cycles run back-to-back. The 80C86/883 local ADDR/DATA bus is floating during both INTA
cycles. Control for pointer address is shown for second INTA cycle.
4. Signals at 82C84A or 82C88 are shown for reference only.
5. The issuance of the 82C88 command and control signals (MADC, MWTC, AMWC, IORC, IOWC, AIOWC,
iNTii and DEN) lags the active high 82C88 CEN.
6. All timing measurements are made at 1.SV unless otherwise noted.
7. Status inactive in state just prior to T 4.

4-75

80C86/883
Waveforms

(Continued)

BUS TIMING - MAXIMUM MODE (USING 82C88) (Continued)
T,

r--'I

CLK

....J
(21)TCH SV

52.51. SO (EXCEPT HAL TI
WRITE CYCLE

---i

,!~~~-

2

r-".

r-'I

'----'

f----J

rT

~~I ~

TClSH

~

(34)1-----

lr-

DATA

r--

(36) TCVNX

-

~

::l

(191

t---

(10)TcLML_

'(~ ~~ ~=

TCLDX2 _

.

X

82C88
SEE NOTES

V'L{'-+JW$(SEENOTE7:

~gt~~::

(35)
NV

OUTPUTS

T4

3

TCLMH-

AMWC OR AIOWC

4.5

(10)TCLML-

t

!--

'{
T: (32)

Ii- ~'
I\f-

TCHDTL

(10)TCLML-

82C88 OUTPUTS

SEE NOTES 4, 5

I

(

POINTER

TCVNV-I\r,::.
(35)

Mii'Dc:. IORC, MWIT:. AMWC. i'OWC. AIQWC, INTA.SO.S, '" VOH
~----+-~IIr------r-----------

----~C

-- ---\-

142fTCHDTH

\

TCLMH(19)

_lSOFTWARE
HALT - RD,

(--TCLDX' (7)

/

/

g

-------C

---- ----

TCVNX ·(36)

~

INVALID ADDRESS

NOTES: 1. ROY is sampled near the end of T2, T3, Tw 10 determine if Tw machine states are to be inserted.
2. Cascade address is valid between first and second INTA cycles.
3. Two iNTA cycles run back-ta-back. The 80C86/883 local ADDR/DATA bus is floating during both INTA
cycles. Control for pointer address is shown for second INTA cycle.
4. Signals at 82C84A or 82~:.u are shown for reference only.
5. The issuance of the 82C88 command and control signals (MRDC, MWi'C, AMWC, IORC. IOWC, AIOWC.
INTA and DEN) 'lags the active high 82C88 CEN.
6. All timing measurements are made at 1.5V unless otherwise noted.
7. Status inactive in state just prior to T4.

4-76

80C86/883
Waveforms (Continued)
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLy)

CLK

AD15 - ADO

--------/

RD, LOCK

BHE/S7. A 1 9 / S 0 - A 1 6 / S 3 - - - - - - - - - - - - - - - . . . . : ; h J

82.Si.so·----------------..../1NOTE: The coprocessor may not drive the busses outside the region shown without risking contention

HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

10R2

1L
1L

CLK

THVCH

en

a:

o

113
HOLD

en
en
en .....
0""
::;;0

TCLHAVI361 ~TCLHAVI361
I
I
HLDA

""g:
o
a:

1191

""
~

TCLAZ

8OC_8_6_~~-4--'.,-----CO-P-R-OIC.-ES-S-O-R---Jr=~80C86

AD1a-ADD _ _ _ _ _

1201
BHE/S7.

A'9JS6-A16/S3---------f~.!:..H~~ ___ - - - - - - - - - - - -

RD.WR.M/iO.DT/R.DEN---------+-'I-- -- ----------- ----

ASYNCHRONOUS SIGNAL RECOGNITION

I:~~}

~

BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY)

CLAV

SIGNAI-L_ _ _J

F

_

1"_____---;

LOCK

TEST

NOTE: Setup requirements for asynchronous signals only to guarantee

recognition at next eLK

4-77

1231

~
1231

TCLAV

80C86/883
Waveforms

(Continued)

r--

RESET TIMING

2:

50/Jsec

vee
elK

RESET

A.C. Test Circuit

A.C. Testing Input, Output Waveform

I

OUTPUT FROM o--~...--- TEST
DEVICE UNDER TEST
POINT

Cl *

~

INPUT
VlH

+

OUTPUT

1.5V
Vll - !iO% Vll

"'Includes stay and jig capacitance

VOH

2O%VlH

~'-_ _ _ _ _ _ _ _~ 1.5V
VOL

A.C. Testing: All input signals (other than elK) must switch between
Vilma. -50% Vil and VIHmin +20% VIH. elK must switch
between O.4V and vee -0.4. Input rise and fall times are
driven at 1 ns/V.

4-78

80C86/883
Burn-In Circuits
80C86/883 CERAMIC DIP

C~GND
vec
RIO veL
RO VII

GND
GND
veL
GND
GND

RIO
RIO
RIO

RO

RIO

RO

VII
RO VII
RO
VII

RIO
veL
GND RIO
GND RIO
GND
VCL
VCL
VCL

GND

RIO

RO

RIO

RI

RIO

RO

RIO

RO

OPEN
OPEN
OPEN
GND
GND

VCL
VCL

RI

RC

RI

veL

0.5V, GND

a:

c->
c->
c->W

OU

::;:0

ug';

= OV

1. RI

= 10kn ± 5%, 1.4W (4)
= 1.2kn ± 5%, 114W (12)

2. RO

2. Input Voltage Limits:
VIL (Maximum) = OAV
VIH (Minimum) = 2.6V

3. RIO = 2.7kn ± 5%, 1/4W (16)

3. VII is external supply sel to 2.7V

5. C

4. RC = 1kn ± 5%, 1/4W (1)

4. Vel is generated on program card (Vee - 1.2V)

5. Pins 13 - 16 input sequenced instructions from internal hold devices.

4-79

= 0.01 ~F (Minimum) (1)

0

a:

u

:E

0

NODE
FROM
PROGRAM
CARD

COMPONENTS: (Per Card)

NOTES:

= 5.5V ±

c->
0

GND

GND

1. VCC

VII

VII
RO VII
RO
VII
RO
VII
RO
VII
RO
VII

OPEN

FO

VII

80C86/883
Burn-In Circuits

(Continued)
80C86/883 CERAMIC LCC
Vcc
VCL

II

~:

;'

O'

"~

'1:

q:
!:1:~!i! ~a:~

~~: ~ it. ~it~

a:~

,'!,I0

"R.,ro""
,'!.~

,~O""
~:'!.".-

.A~

it: ~it::
~

GND

@

fO

NOTES:
1. VCC

~: ~q~
"'?

(FROM PROGRAM CARD)

COMPONENTS: (Per Card)

= S.5V ±

O.SV. GND

= OV

2. Input Voltage Limits:
Vll (MaxImum) - O.4V
VlH (MinImum) = 2.6V
3. VII Is external supply set to 2.7V

1. RI = 10kn ± 5%. 1.4W (4)
2. RO = l.2kn ± 5%. 1/4W (12)
3. RIO

= 2.7kn ± 5%.

1I4W (16)

4. RC = lkn ± 5%.1/4W (1)
5. C - 0.01 pf (MInImum) (1)

4. VCl is generated on program card (VCC - 1.2Y)

4-80

VII

80C86/883
Metallization Topology
DIE DIMENSIONS:
249.2 x 290.9 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kA ± 2kA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA ± 2kA
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 D C (Max)
WORST CASE CURRENT DENSITY:
1.5 x 105 Ncm 2

Metallization Mask Layout
80C86/883
ADll

AD12

AD13 AD14

GND

VCC

AD15 A16/S3

A17/S4 A1B/S5

III!!!!!II!!JIII,I!II!!WII!!!!!!!III!!!
A19/S6
AD10
AD9
BHE/S7
MN/Mx

en

II:
0

en
en
en W

0<'>
::;;0

ADB
AD7

AD

AD6

Ra/GTO

ADS

Ra/GTi
AD4
AD3

i:OcK

52
AD2

51

ADl

SO

ADO
NMI INTR

CLK

GND

RESET READY

4-81

fEST

aSl

aso

<.>g:
0
II:
<.>
:ll

80C86/883
Packaging t

40 PIN CERAMIC DIP
2.035

~.

I

Z~6

~W

.225.-------t~::5
MINL~ ~j'""
I~ ]
r:--

J~ ~

I
.125

I II

.1;0 MIN

~.09B

.180~'

O·

15-

MAX

.~~~

.023
.050'
.065

• INCREASE MAX UlAIT BY .003 INCHES
MEASUREO AT CENTER OF FLAT FOR
SOLDER FlNISH

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 385100-5

44 PAD CERAMIC LCC
BOTTOM VIEW

.643
.662

.045
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PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic. 90% Alumina
PACKAGE SEAL:
.
Material: Goldfrin (80/20)
Temperature: 320 0 C ± 100 C
Method: Furnace Braze

NOTE: All Dimensions are

..M!!:!..
. Dimensions are In inchas.
Max

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-5

t MiI-M-38510 Compliant Materials. Finishes, and Dimensions.
4-82

m

80C86

HARRIS

DESIGN INFORMATION
CMOS 16 Bit Microprocessor
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Functional Description
Static Operation
All SOCS6 circuitry is of static design. Internal registers,
counters and latches are static and require no refresh as
with dynamic circuit design. This eliminates the minimum
placed on other
operating frequency restriction
microprocessors. The CMOS SOCS6 can operate from DC
to the specified upper frequency limit. The processor clock
may be stopped in either state (HIGH/LOW) and held there
indefinitely. This type of operation is especially useful for
system debug or power critical applications.
The SOCS6 can be single stepped using only the CPU
clock. This state can be maintained as long as is necessary.
Single step clock operation allows simple interface circuitry
to provide critical information for bringing up your system.
Static design also allows very low frequency operation
(down to DC). In a power critical situation, this can provide
extremely low power operation since SOCS6 power dissipation is directly related to operating frequency. As the system

frequency is reduced, so is the operating power until,
ultimately, at a DC input frequency, the SOCS6 power requirement is the standby current, (500MA maximum).
Internal Architecture
The internal functions of the SOCS6 processor are partitioned logically into two processing units. The first is the
Bus Interface Unit (BIU) and the second is the Execution
Unit (EU) as shown in the CPU functional diagram.
These units can interact directly but for the most part perform as separate asynchronous operational processors.
The bus interface unit provides the functions related to
instruction fetching and queuing, operand fetch and store,
and address relocation. This unit also provides the basic
bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance
through improved bus bandwidth utilization. Up to 6 bytes
of the instruction stream can be queued while waiting for
decoding and execution.

c::
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Functional Diagram

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EXECUTION UNIT

I

BHE/57

A1S/S6
A16/S J

BUS
INTERFACE
UNIT

SS
DS
IP

INTA,Ro,WR

A·BUS

DTtR, DEN, ALE, MIlO

EXECUTION
UNIT

TEST
tNTR

_...r-----''''''------,

NMI

HLDA

OSo. OS1

-<--t....._

eLK

...._ ..._

eL
DL

SP
BP
51
DI

LOCK

Sz.Si,SQ

HOLD

AL
Bl

AH
BH
eH
DH

....--:"""

RESET READY MN/Mx GND

Vee

4-S3

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

The instruction stream queuing mechanism allows the BIU
to keep the memory utilized very efficiently. Whenever there
is space. for at least 2 bytes in the queue, the BIU will
attempt a word fetch memory cycle. This greatly reduces
"dead-time" on the memory bus. The queue acts as a FirstIn-First-Out (FIFO) buffer, from which the EU extracts
instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the
queue immediately becomes available to the EU.
The execution unit receives pre-fetched instructions from
the BIU queue and provides un-relocated operand
addresses to the BIU. Memory operands are passed
through the BIU for processing by the EU, which passes
results to the BIU for storage.
Memory Organization
The processor provides a 20 bit address to memory, which
locates the byte being referenced. The memory is organized
as a linear array of up to 1 million bytes, addressed as
OOOOO(H) to FFFFF(H). The memory is logically divided into
code, data, extra and stack segments of up to 64K bytes
each, with each segment failing on 16-byte boundaries.
(See Figure 1).

types were chosen based on the addressing needs of
programs. The segment register to be selected is automatically chosen according to the specific rules of Table A. All
information in one segment type share the same logical attributes (e.g. code or data). By structuring memory into
relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter,
faster and more structured. (See Table A).
Word (16 bit) operands can be located on even or odd
address boundaries and are thus not constrained to even
boundaries as is the case in many 16-bit computers. For
address and data operands, the least significant byte of the
word is stored in the lower valued address location and the
most significant byte in the next higher address location. The
BIU automatically performs the proper number of memory
accesses, one if the word operand is on an even byte boundary and two if it is on an odd byte boundary. Except for the
performance penalty, this double access is transparent to the
software. The performance penalty does not 'occur for
instruction fetches; only word operands.
Physically, the memory is organized as a high bank (015-08)
and a low bank (07-00) of 512K bytes addressed in parallel
by the processor's address lines.

..r--.J. FFFfFH

,r,
·1

F---'

I

Byte data with even addresses is transferred on the 07-00
bus lines while odd addressed byte data (AO HIGH) is transferred on the 015-08 bus lines. The processor provides two
enable signals, BHE and AO, to selectively allow reading from
or writing into either an odd byte location, even byte
location, or both. The instruction stream is fetched from memoryas words and is addressed internally by the processor at
the byte level as necessary.

CDDESEG"'"
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.C=ISTACKSEGMENT

+ OFFSET

SEGMENT

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os
~~"~'ISI~:~"~"~'
"

In referencing word data, the BIU requires one or two memory
cycles depending on whether the starting byte of the word is
on an even or odd address, respectively. Consequently, in
referencing word operands performance can be optimized by
locating data on even address boundaries. This is an especially useful techniqu& for using the stack, since odd address
references to the stack may adversely affect the context
switching time for interrupt processing or task multiplexing.

DATA SEGMENT

l: I

"""EG.'"

~IHIOaolt

FIGURE 1. SOC86 MEMORY ORGANIZATION
TABLE A.

TYPE OF
MEMORY
REFERENCE
Instruction Fetch
Stack Operation
Variable (except
following)
String Source
String Destination
BP Used As Base
Register

DEFAULT
SEGMENT
BASE

ALTERNATE
SEGMENT
BASE

CS
SS
OS

None
None
CS,ES,SS

DS
ES
SS

CS,ES,SS
None
CS,DS,ES

OFFSET
IP
SP
Effective
Address
SI
DI
Effective
Address

All memory references are made relative to base addresses
contained in high speed segmen~ registers. The segment

Certain locations in memory are reserved for specific CPU
operations (See Figure 2). Locations from address FFFFOH
through FFFFFH are reserved for operations including a jump
to the initial program loading routine. Following RESET, the
CPU will always begin execution at location FFFFOH where
the jump must be located. Locations OOOOOH through
003FFH are reserved for interrupt operations. Each of the
256 possible interrupt service routines is accessed thru its
own pair of 16-bit pointers - segment address pointer and
offset address pointer. The first pointer, used as the offset
address, is loaded into the IP and the second pointer, which
designates the base address is loaded into the CS. At this
point program control is transferred to the interrupt routine.
The pointer elements are assumed to have been stored at the
respective places in reserved memory prior to occurrence of
interrupts.

4-84

80C86

DESIGN INFORMATION

(Continued)

The Information contained in this section has been developed through characterization by Harris Semiconductor and Is for·
use as application and design information only. No guarantee is implied.

FFFFFH

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TVPE 3l POINTER
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-

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TYPE 31 POINTER
(RESERVEO)

-

I-

TYPE 5 POINTER
(RESERVEDI

-

lFF H
JFC HI-

Moving the bus control to the 82C88 provides better source
and sink current capability to the control lines, and frees the
80C86 pins for extended large system features. Hardware
lock, queue status, and two request/grant interfaces
are provided by the 80C86 in maximum mode. These features allow coprocessors in local bus and remote bus configurations.

-

AVAILABlE

INTERRUPT
POINTERS
12241
DB4H

aaOH
OlFH

TYPE 32 POINTER

Bus Operation
The 80C86 has a combined address and data bus commonly referred to as a time multiplexed bus. This technique
provides the most efficient use of pins on the processor.
while permitting the use of a standard 40 lead package.
This "local bus" can be buffered directly and used throughout the system with address latching provided on memory
and I/O modules. In addition, the bus can also be
demultiplexed at the processor with a single set of 82C82
address latches if a standard non-multiplexed bus is
desired for the system.

RESERVED (
INTERRUPT
POINTERS
(211

014H

DEDICATED
INTERRUPT
POINTERS

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NON-MASKABLE

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TYPE 1 POINTER
SINGLE-STEP

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TYPE 0 POINTER
OIVIlfEERROR

004H

OODH

TVPE4'OINTER

OVERFLOW

TYPE 2 POINTER

-

-

r-lIiBITS~

FIGURE 2. RESERVED MEMORY LOCATIONS
Minimum and Maximum Operation Modes
The requirements for supporting minimum and maximum
80C86 systems are sufficiently different that they cannot be
met efficiently using 40 uniquely defined pins. Consequently, the 80C86 is equipped with a strap pin (MN/MX) which
defines the system configuration. The definition of a certain
subset of the pins changes, dependent on the condition of
the strap pin. When the MN/MX pin is strapped to GND, the
80C86 defines pins 24 through 31 and 34 in maximum
mode. When the MN/MX pin is strapped to VCC, the 80C86
generates bus control signals itself on pins 24 through 31
and 34.
The minimum mode 80C86 can be used with either a multiplexed or demultlplexed bus. This architecture provides the
80C86 processing power in a highly integrated form.

Each processor bus cycle consists of at least four ClK
cycles. These are referred to as T1, T2, T3 and T 4 (see
Figure 3). The address Is emitted from the processor during
T1 and data transfer occurs on the bus during T3 and T4. T2
is used primarily for changing the direction of the bus
during read operations. In the event that a "NOT READY"
indication is given by the addressed device, "Wait" states
(fW) are inserted between T3 and T4. Each inserted wait
state Is the same duration as a ClK cycle. Periods can
occur between 80C86 driven bus cycles. These are
referred to as idle" states (fl) or Inactive ClK cycles. The
processor uses these cycles for internal housekeeping and
processing.
During T1 of any bus cycle, the ALE (Address latch Enable)
signal Is emitted (by either the processor or the 82C88 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse,'a valid address and certain status
information for the cycle may be latched.
Status bits SO, 51 and 52 are used by the bus controlier, In
maximum mode, to identify the type of bus transaction
according to Table B.

The demultiplexed mode requites two 82C82 latches (for
64K addressability) or three 82C82 latches' (for a full
megabyte of addressing). An 82C86 or 82C87 transceiver
can also be used if data bus buffering is required. (See
Figure 6a.) The 80C86 provides DEN and DT/R to control
the transceiver, and ALE to latch the addresses. This configuration of the minimum mode provides the standard
demultiplexed bus structure with heavy bus buffering and
relaxed bus timing requirements.
The maximum mode employs the 82C88 bus controlier
(See Figure 6b). The 82C88 decodes status lines SO, 51
and 52, and provides the system with ali bus control
signals.

4-85

TABLEB.
S2

S1

SO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

CHARACTERISTICS
Interrupt
Read 1/0
Write 1/0
Halt
Inslruction Felch
Read Data from Memory
Write Dala to Memory
Passive (no bus cycle)

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
'use as application and design information only. No guarantee is implied.

I

(4 + NWAIT) = TCY
T2

I

Ta

I TWAIT I

T4

(4 + NWAIT)

•

T1

T2

Ta

= TCY - - - - - + 1

I TWAIT

T4'

I

elK
GOES INACTIVE IN THE STATE
{\

AlE~

JUST PRIOR TOT4

IL

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ADDRI
STATUS

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ADDR/OATA

.

DATA OUT (015- 0 0)

READY

READY

READY
WAIT

DT/R

-MEMORY ACCESS TIME-

\I...-_---If

WR

FIGURE 3. BASIC SYSTEM TIMING

4-86

'5 ~

a=

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Status bits S3 through S7 are time multiplexed with high
order address bits and the BHE signal, and are therefore
valid during T2 through T4. 53 and 54 indicate which segment
register (see Instruction Set Description) was used for this bus
cycle in forming the address, according to Table C.
TABLEC.
S4

S3

0
0
1
1

0
1
0
1

CHARACTERISTICS
Alternate Data (extra segment)
Stack
Code or None
Data

S5 is a reflection ,~of the PSW interrupt enable bit. S6 is
always zero and S7 is a spare status bit.
I/O Addressing
In the BOCB6, I/O operations can address up to a maximum
of 64K I/O byte registers or 32K I/O. word registers. The I/O
: address appears in the same format as the memory address
on bus lines A15-AO. The address lines A19-A16 are zero
in I/O operations. The variable I/O instructions which use
register DX as a pointer have full address capability while
the direct I/O instructions directly address one or two of the
256 I/O byte locations in page a of the I/O address space.

VO ports are addressed in the same manner as memory
locations. Even addressed bytes are transferred on the D7DO bus lines and odd addressed bytes on D15-DB. Care
. must be taken to ensure that each register within an B bit
'peripheral located on the lower portion, of the bus be
addressed as even.

External Interface
Processor RESET and Initialization
Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. The BOCB6 RESET is
required to be HIGH for greater than 4 ClK cycles. The
BOCB6 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is HIGH.
The low-going transition of RESET triggers an internal reset
sequence for approximately 7 clock cycles. After this interval, the BOCB6 operates normally beginning with the
instruction in absolute location FFFFOH. (See Figure 2). The
RESET input Is internally synchronized to the processor
clock. At Initialization, the HIGH-to-lOW transition of
RESET must occur no sooner than 50l-'S (or 4 ClK cycles,
whichever is greater) after power-up, to allow complete
Initialization of the BOCB6.
NMI will not be recognized prior to the second ClK cycle
following the end of RESET. If NMI is asserted sooner than
nine clock cycles after the end of RESET, the processor
may execute one instruction before responding to the interrupt.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs
to CMOS devices and to eliminate need for pull-up/down
resistors, "bus-hold" circuitry has been used on the BOCB6
pins 2-16, 26-32 and 34-39. (See Figure 4a and 4b). These
circuits will maintain the last valid logic state if no driving
source is present (i.e. an unconnected pin or a driving
source which goes to a high impedance state). To overdrive
the "bus hold" circuits, an external driver must be capable
of supplying approximately 4001JA minimum sink or source
current at valid Input voltage levels. Since this "bus hold"
circuitry is active and not a "resistive" type element, the
associated power supply current is negligible and power
dissipation is significantly reduced when compared to the
use of passive pull-up resistors.

FIGURE,4B. BUS HOLD CIRCUITRY PIN 26-32

FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39

4-87

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80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
Interrupt Operations

Maskable Interrupt (INTR)

Interrupt operations fall into two classes: software or hardware initiated. The software initiated Interrupts and software
aspects of hardware interrupts are specified in the Instruction Set Description. Hardware interrupts can be classified
as non-maskable or maskable.

The 80C86 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable flag (IF) status bit. The
interrupt request signal.is level triggered. It is internally
synchronized during each clock cycle on the high-going
edge of ClK. To be responded to, INTR must be present
(HIGH) during the clock'period preceding the end of the
current instruction or the end of a whole move for a block
type instruction. INTR may be removed anytime after the
falling edge of the first INTA signal. During the interrupt response sequence further interrupts are disabled. The
enable bit is reset as part of the response to any interrupt
(INTH, NMI, software interrupt or single-step), although the
FLAGS register which is automatically pushed onto the
stack reflects the state of the processor prior to the interrupt. Until the old FLAGS register'is restored the enable bit
will be zero unless specifically set by an instruction.

Interrupts result in a transfer of control to a new program location. A 256-element table containing address pointers to
the interrupt service program locations resides in absolute
locations 0 through 3FFH, which are reserved for this
purpose. Each element in the table is 4 bytes in size and
corresponds to an interrupt "type". An interrupting device
supplies an 8 bit type number during the interrupt acknowledge sequence, which is used to "vector" through the
appropriate element to the new interrupt service program
location. All flags and both the Code Segment and
Instruction Pointer register are saved as part of the INTA
sequence. These are restored upon execution of an Interrupt Return (IRET) instruction.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt
pin (NMI) which has higher priority than the maskable interrupt request pin (INTR). A typical use would be to activate a
power failure routine. The NMI is edge-triggered on a
lOW-to-HIGH transition. The activation of this pin causes a
type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two ClK cycles, but is not required to be
synchronized to the clock. Any positive transition of NMlls
latched on-chip and will be serviced at the end of the
current instruction or between whole moves of a block-type
instruction. Worst case response to NMI would be for multiply, divide, and variable shift instructions. There is no
specification on the occurrence of the low-going edge; it
may occur before, during or after the servicing of NMI.
Another positive edge triggers another response if it occurs
after the start of the NMI procedure. The signal must be free
of logical spikes in general and be free of bounces on the
low-going edge to avoid triggering extraneous responses.

During the response sequence (Figure 5) the processor
executes two successive (back-to-back) interrupt acknowledge cycles. The 80C86 emits the lOCK signal (Max mode
only) from T2 of the first bus cycle until T2 of the second. A
local bus "hold" request.will.not be honored until the end of
the second bus cycle. In the second bus cycle, a byte is
supplied to the 80C86 by the 82C59A Interupt
Controller, which identifies the source (type) of the interrupt.
This byte is multiplied by four and used as a pointer into the
interrupt vector look-up table. An INTR signal left HIGH will
be continually responded to within the limitations of the
enable bit and sample period. The INTERRUPT RETURN
instruction includes a FLAGS pop which returns the status
of the original interrupt enable bit when it restores the
FLAGS.
Halt
When a software "HALT" instruction is executed the
processor indicates that it is entering the "HALT" state in
one of two ways depending upon which mode is strapped.
In minimum mode, the processor issues one ALE with no
qualifying bus control signals. In maximum mode the
processor issues appropriate HALT status on S2, S1, SO

FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE

4-88

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
and the 82C88 bus controller issues one ALE. The 80C86
will not leave the "HALT" state when a local bus "hold" is
entered while in "HALT". In this case, the processor
reissues the HALT indicator at the end of the local bus hold.
An NMI or interrupt request (when interrupts enabled) or
RESET will force the 80C8,6 out of the "HALT" state.

Read/Modify/Write (Semaphore)
Operations Via Lock

N

The LOCK status information is provided by the processor
when consecutive bus cycles are required during the
execution of an instruction. This gives the processor the
capability of performing read/modify/write operations on
memory (via the Exchange Register With Memory instruction, for example) without another system bus master
receiving intervening memory cycles. This is useful in
multiprocessor system configurations to accomplish "test
and set lock" operations. the LOCK signal is activated
(forced LOW) in the clock cycle following decoding of the
software "LOCK" prefix instruction. It is deactivated at the
end of the last bus cycle of the instruction following the
"LOCK" prefix instructiori. While LOCK is active a request
on a RQ/GT pin will be recorded and then honored at the
end of the LOCK.
External Synchronization Via TEST
As an alternative to interrupts, the 80C86 provides a single
software-testable input pin (TEST). This input is utilized by
executing a WAIT instruction. The single WAIT instruction is
repeatedly executed until the TEST input goes active
(LOW). The execution of WAIT does not consume bus
cycles once the queue is full.
If a local bus request occurs during WAIT execution, the
80C86 three-states all output drivers while inputs and I/O
pins are held at valid logic levels by internal bus-hold
circuits. If interrupts are enabled, the 80C86 will recognize
interrupts and process them when it regains control of the
bus. The WAIT instruction is then refetched, and
reexecuted.
TABLE D.

aocas REGISTER MODEL
ACCUMULATOR

ax
ex
ox

Basic System Timing
Typical system configurations for the processor operating
in minimum mode and in maximum mode are shown in
Figures 6A and 6B, respectively. In minimum mode, the
MN/MX pin is strapped to VCC and the processor emits bus
control signals (e.g. RD, WR, etc.) directly. In maximum
mode, the MN/MX pin is strapped to GND and the processor emits coded status information which the 82C88 bus
compatible
controller uses to generate MULTIBUS
bus control signals. Figure 3 shows the signal timing
relationsh ips.

BASE

8H

COUfU

CH

DC

DATA

System Timing - Minimum System
The read cycle begins in T1 with the assertion of the
Address Latch Enable (ALE) signal. The trailing (low-going)
edge of this signal is used to latch the address information,
which is valid on the address/data bus (ADO-AD15) at this
time, into the 82C82/82C83 latch. The BHE and AO signals
address the low, high or both bytes. From T1 to T4 the M/iO
signal indicates a memory or I/O operation. At T2, the
address is removed from the address/data bus and the bus
is held at the last valid logic state by internal bus hold
devices. The read control signal is also asserted at T2. The
read (RD) signal causes the addressed device to enable its
data bus drivers to the local bus. Some time later, valid data
will be available on the bus and the addressed device will
drive the READY line HIGH. When the processor returns the
read signal to a HIGH level, the addressed device will again
three-state its bus drivers. If a transceiver (82C86/82C87)
is required to buffer the 80C86 local bus, signals DT/R and
DEN are provided by the 80C86.
A write cycle also begins with the assertion of ALE and the
emission of the address. The M/iO signal is again asserted
to indicate a memory or I/O write operation. In T2,
immediately following the address emission, the processor
emits the data to be written into the addressed location. This
data remains valid until at least the middle of T4. During T2,
T3 and'TW, the processor asserts the write control signal.
The write (WR) signal becomes active at the beginning of T2
as opposed to the read which is delayed somewhat into T2
to provide time for output drivers to become inactive.
The BHE and AO signals are used to select the proper
byte(s) of the memory/IO word to be read or written according to Table E.
TABLE E.

STACK POINTER

SP

{I

BASE POINTER
SOURCE INDEX
DESTINATION

DI

[I

If~DEX

IfjSTRUCTlONPOINTER

FlAGSL

FlAGSH

cs

STATUS FLAGS

AO

0
0
1
1

0
1
0
1

CHARACTERISTCS
Whole word
Upper byte from/to odd address
Lower byte from/lo even address
None

CODE SEGMENT

DATA SEGMENT

I

BHE

55

STACK SEGMENT

ES

EXTRA SEGMENT

I/O ports are addressed in the same manner as memory location. Even addressed bytes are transferred on the D7-DO
bus lines and odd address bytes on D15-D8.

4-89

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and Is for
use as application and design information only. No guarantee is implied.

VCC

rml
82CB4A/85
CLOCK
GENERATOR
RES
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20 GND

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lATCH
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: GENERATOR ~

GNO

+-VCC

ClK
MilO
READY . INTA
iiii
RESET

~

B2C86
II
TRANSCEIVER' I 8HE
1
(2)

L ___

DATA

JJ Jill

OPTIONAL
FOR INCREASED
DATA BUS DRIVE

W G
El
HM-6516
CMOS RAM

EH

2K ,8

r1~

;>

82C84A/85
CLOCK
GENERATOR

~ REs

ROY'

~

f r-l-,
GND

1
,

I

.

MN/~

ClK
READY
RESET .

So
SI
S2

lOCK

L ____ J GND

f

1
CI=f '.

2K,B.l2K,8

CS

ROWR
CMOS
B2CXX
PERIPHERALS

1
j4-GNO

ClK

MROC
MWTC
Si B2CBB AMWC t-N.C.
!2 BUS 10RC
DEN CTRlR IOWC
AIOWC t-N.C.
r - DT/R
ALE
INTA

So

.--

BDCB6
CPU

1
WAIT
I
STATE
GENERATOR ,

~

2K,8

E
G
HM-6616
CMOS PROM )2)

FIGURE 6A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION

0

VCC

1

hlIl 11

r-: N.C.

,----:1
STB

GND-

t---'

ADO-AOI5
A16- A19 ~ODR/OAp.....
jjjjf r--

DE

t----

B2CB2
LATCH
(2 OR 3)

1
I
I
~OOR

20 GND

-d:C2=F

Lt>:

40 VCC
CI = C2 = O.I"F

..

L-J,

T

DE

82CB6
TRANSCEIVER
)2)

DATA
8HE

111

W G
El
HM-65162
CMOS RAM
2K,8 I 2K,B

EH

hH 1

E
G
HM-6616
CMOS PROM (2)
2K,BI2K,B

FIGURE 6B. MAXIM'UM MODE 80C86 TYPICAL CONFIGURATION

4-90

CS

RO WR
CMOS
B2CXX
PERIPHERALS

BOCB6

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge
signal (INTA) is asserted in place of the read (RD) signal and
the add ress bus is held at the last valid logic state by internal bus hold devices. (See Figure 4). In the second of two
successive INTA cycles a byte of information is read from
the data bus (07-00) as supplied by the interrupt system
logic (Le. 82C59A Priority Interrupt Controller). This byte
identifies the source (type) of the interrupt. It is multiplied by
four and used as a pointer into an interrupt vector lookup
table, as described earlier.
Bus Timing - Medium Size Systems
For medium complexity systems the MN/MX pin is connected to GND and the 82C88 Bus Controller is added to
the system as well as an 82C82/82C83 latch for latching
the system address, and an 82C86/82C87 transceiver to
allow for bus loading greater than the 80C86 is capable of
handling. Signals ALE, DEN, and DTiR" are generated by the
82C88 instead of the processor in this configuration,
although their timing remains relatively the same. The 80C86

status outputs (S2, S1 and SO) provide type-of-cycle
information and become 82C88 inputs. This bus cycle information specifies read (code, data or I/O), write (data or I/O),
interrupt acknowledge, or software halt. The 82C88 issues
control signals specifying memory read or write, I/O read or
write, or interrupt acknowledge. The 82C88 provides two
types of write strobes, normal and advanced, to be applied
as required. The normal write strobes have data valid at the
leading edge of write. The advanced write strobes have the
same timing as read strobes, and hence, data is not valid at
the leading edge of write. The 82C86/82C87 transceiver
receives the usual T and OE inputs from the 82C88 DTiR"
and DEN signals.
The pointer into the interrupt vector table, which is passed
during the second INTA cycle, can be derived from an
82C59A located on either the local bus or the system bus. If
the master 82C59A Priority Interrupt Controller is positioned on the local bus, the 82C86/82C87 transceiver must
be disabled when reading from the master 82C59A during
the interrupt acknowledge sequence and software "poll".

en

a:

o

en
en

en W

0<->
:;;0

<->~
o
a:

<->

:E

4-91

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY
Mnemonic and
Description

J

Instruction Code

DATA TRANSFER
MOV = Move:
Register/Memory to/from Register

76543210

I

Immediate to Register/Memory
Immediate to Register

76543210

100010dw

mod

reg

rim

1100011 w

modOOO rim

1011 wreg

data

Memory to Accumulator

10tOOOOw

add-low

Accumulator to Memory

1010001w

addr·low

Register/Memory to Segment Register"

10001110

modO reg rim

Segment Register to Register/Memory

10001100

mod 0 reg rim

76543210

I
I
I
I
I
I
I

PUSH = Pueh:
Register/Memory
Register
Segment Register

I
I
I

11111111
01010reg
OOOreg 11 0

I
I
I

mod 110 rim

I

I
I
I

mod 0 0 0 rim

I

I
I

mod reg rim

I

POP = Pop:
Register/Memory
Register
Segment Register

I

I
I

10001111
01011 reg
OOOreglll

XCHG = Exchange:
Register/Memory with Register

I

1000011w

Register with Accumulator

I

10010reg

IN = Input from:
Fixed Port

I

111001 Ow

port

I

I

1110110w

I

I

Variable Port

I
I
I
I
I
I
I

1110011 w

I
I
I
I
I

port

I

mod reg rim

I
I
I

OUT = Output to:
Fixed Port
Variable Port
XLAT = Translate Byte to AL
LEA = Load EA to Register
LOS = Load Pointer to DS
LES = Load Pointer to ES
LAHF = Load AH with Flags

1110111 w
11010111
10001101
11000101
11000100
10011111

SAHF = Store AH into Flags

I

10011 110

PUSHF = Push Flags

I
I

10011100

POPF = Pop Flags

10011101

I

I
I
I
I

4-92

mod reg rim
mod reg rim

data
data Ifw 1
addr-high
addr-high

78543210

I
I
I
I

dataHw 1

I

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY (Continued)
Mnemonic and
DelCrlptlon

Instruction Code

765432tO

ARITHMETIC

76543210

76543210

78543210

ADD = Add:
Reg.lMemory with Register to Either

OOOOOOdw

mod reg rIm

Immediate to RegisterlMemory

100000sw

modOOOr/m

Immediate to Accumulator

0000010w

data

.~

ADC

data
data ifw

=

data if sow

= 01

data if sow

= 01

data if s:w

= 01

1

Add with Carry:

Reg.lMemory with Register to Either

000100dw

mod reg rIm

Immediate to RegisterlMemory

100000sw

modO 10 rIm

Immediate to Accumulator

0001010w

data

l111111w

modOOOrlm

data
dataifw

=1

= Increment:

INC

RegisterlMemory
Register

01000reg

0011011~

AAA = ASCII Adjust tor Add

= Decimal Adjust for Add
= Subtract:

DAA
SUB

0010011 i

Reg.lMemory and Register to Either

1001010dw

Immediate from RegisterlMemory
Immediate from Accumulator

I
mod reg rIm

I

100000sw

mod 101 rIm

[

0010110w

data

data
dataifw

=

1

SBB = Subtract with Borrow
Reg.lMemory and Register to Either

000110dw

mod reg rIm

Immediate from RegisterlMemory

100000sw

mod 0 11 rIm

Immediate from Accumulator

0001110w

data

DEC = DlCrement:
RegisterlMemory

Gl1111W

Register

I

01001 reg

[

1111011 w

NEG
CMP

= Change Sign
= Compare:

mod 0 11 rIm

RegisterlMemory and Register

001110dw

mod reg rIm

100000sw

mod 111 rIm

Immediate with Accumulator

0011110w

data

AAS = ASCII Adjust for Subtract

00111111

DAS

=

MUL

= Multiply (Unsigned)

1111011w

mod 1 OOrlm

IMUL = Integer Multiply (Signed)

1111011 w

mod 1 0 1 rIm

AAM

11010100

00001010

= Divide (Unsigned)

1111011 w

mod 11 Orlm

IDlY = Integer Divide (Signed)

1111011 w

mod 111 rIm

AAD = ASCII Adjust for Divide

11010101

00001010

DIY

=

00101111

ASCII Adjust for Multiply

CBW = Convert Byte to Word

110011000

CWD = Convert Word to Double Word

I

=1

modOOI rIm

Immediate with RegisterlMemory

Decimal Adjust for Subtract

data if sow = 01

data
dataifw

10011001

4-93

data
dataifw

data if s:w
=

1

= 01

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY (Continued)
Mnemonic and
Description
LOGIC

I

Instruction Code
76543210

76543210

1III01lw

modOIOr/m

SHLISAL = Shift LogicallArithmetic Left

110100vw

mod I OOr/m

SHR = Shift Logical Right

110100vw'

mod I 0 I rIm

SAR = Shift Arithmetic Right

110100vw

mod I I I rIm

ROL = Rotate Left

110100vw

mod OOOr/m

ROR = Rotate Right

110100vw

mod 00 trIm

RCL = Rotate Through Carry Flag Left

110100vw

modO I o rIm

RCR = Rotate Through Carry Right

110100vw

modOl1 rIm

NOT = Invert

76543210

76543210

data

dataifw = I

AND = And:
Reg.lMemory and Register to Either

001000dw

mod reg rIm

Immediate to RegisterlMemory

1000000w

mod 100 rIm

Immediate to Accumulator

OOIOOIOw

data

TEST = And Function to Flags, No Result:
RegisterlMemory and Register

I
I
I

dataifw = I

r------------r-----------,
mod reg rIm
IOOOOIOw

Immediate Data and RegisterlMemory

1111011w

modOOOr/m

data

Immediate Data and Accumulator

1010100w

data

dataifw = I

OR

datalfw = I

= Or:

Reg.lMemory and Register.to Either

OOOOIOdw

mod reg rIm

Immediate to Register/Memory

1000000w

modO 0 I rIm

data

Immediate to Accumulator

000011 Ow

data

datalfw= I

dataifw = I

XOR = Exclusive or:
Reg.lMemory and Register to Either

0011 OOdw

mod reg rIm

Immediate to RegisterlMemory

1000000w

modI I Or/m

data

Immediate to Accumulator

0011010w

data

dataifw = I

STRING MANIPULATION
REP = Repeat

111100lz

MOYS = Move BytelWord

1010010w

CMPS

=

SCAS

= Scan BytelWord

Compare BytelWord

10100 II w
1010111w

LODS = Load BytelWd to ALI AX

1010110w

STOS

1010101w

=

Star BytelWd from ALI A

CONTROL TRANSFER
CALL = Call:
Direct Within Segment

11101000

disp·low

Indirect Within Segment

11111111

modOIOr/m

Direct Intersegment

10011010

offset-low
seg-Iow

Indirect Intersegment

11111111

modO II rIm

4-94

I
I
I
I
I

disp-high

offset-high
seg-high

dataifw = I

BOCB6

DESIGN INFORMATION

(Continued)
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY (Continued)
Mnemonic and
Description

I

Instruction Code

JMP = Unconditional Jump:

76543210

76543210

76543210

Direct Within Segment

11101001

disp·low

disp-high

Direct Within Segment·Short
Indirect Within Segment
Direct Intersegment

disp

Llll0l0ll

I
I

11111111

mod tOO rIm

11101010

ollsel·low
seg-Iow

=

Return from CALL:

Within Segment

[

1 1000011

Within Seg Adding Immed to SP

I

11000010

Intersegment

~1011

Intersegment Adding Immediate to SP

11001010

JE/JZ = Jump on Equal/Zero

01110100

JL/JNGE = Jump on Less/Not Greater
or Equal
= Jump on Less or Equal/
Not Greater
JB/JNAE = Jump on Below/Not Above
or Equal
JBE/JNA = Jump on Below or Equal!
Not Above
JP/JPE = Jump on Parity/Parity Even

01111100

JO = Jump on Overflow

= Jump on Sign

JLE/JNG

JS

seg-hi~

mod 101 rIm

Indirect Intersegment
RET

ollset-high

JNE/JNZ = Jump on Not Equal/Not Zero
JNL/JGE

= Jump on Not Less/Greater

I
I

data-low

data-high

data·low

data-high

J
I
I
I

disp
disp

01111110

disp

01110010

disp

01110110

disp

01111010

disp

01110000

disp

01111000

disp

01110101

disp

01111101

disp

01111111

disp

01110011

disp

01110111

disp

01111011

disp

or Equal
JNLE/JG = Jump on Not Less or Equal/
Greater
JNB/JAE = Jump on Not Below/Above
or Equal
JNBE/JA = Jump on Not Below or
Equal/Above
JNP/JPO = Jump on Not Par/Par Odd
JNO = Jump on Not Overflow

01110001

disp

= Jump on Not Sign
LOOP = Loop ex Times

01111001

disp

11100010

disp

LOOPZ/LOOPE = Loop While Zero/Equal

11100001

disp

LOOPNZ/LOOPNE = Loop While Not
Zero/Equal
= Jump on ex Zero

11100000

disp

11100011

disp

Type Specified

11001101

type

Type 3

11001100

JNS

JCXZ

INT = Interrupt

INTO

=

IRET

= Interrupt Return

Interrupt on Overflow

11001110
11001111

4-95

a:
'"
o
'"
'"
"'W
0<->

:;:0
<->g:
o
a:
<->

:E

80C86

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY (Continued)
Mnemonic and
Deacrlptlon

I

Instruction Code

76543210

76543210

PROCESSOR CONTROL
CLC

= Clear Carry

11111000

CMC

= Complement Carry

11110101

= Set Carry

1111100 1

CLO = Clear Direction

11111100

= Set Direction
= Clear Interrupt
sn = Set Interrupt

11111101

HLT

11110100

STC

STO

CLI

=

Halt

= Wait
= Escape (to External Device)

WAIT
ESC

LOCK = Bus Lock Prefix

11111010
11111011

10011011
11011xxx

modxxxr/m

11110000

NOTES:
Al = B-bit accumulator
AX = 16-bit accumulator
CX = Count register
OS = Data segment
ES = Extra segment
Above/below refers to unsigned value.
Greater = more positive;
less = less positive (more negative) signed values
if d = 1 then "to" reg; if d = 0 then "from" reg
if w = 1 then word instruction; if w = 0 then byte instruction
if mod = 11 then rim is treated as a REG field
if mod = 00 then DISP = 0", disp-Iow and disp-high are
absent
if mod = 01 then DISP = disp-Iow sign-extended to
16 bits, disp-high is absent
if mod = 10 then DISP = disp-high: disp-Iow
if rim = 000 then EA = (BX) + (51) + DISP
if rim = 001 then EA = (BX) + (01) + DISP
if rim = 010 then EA = (BP) + (51) + DISP
if rim = 011 then EA = (BP) + (01) + DISP
if rim = 100 then EA = (51) + DISP
if rim = 101 then EA = (01) + DISP
if rim = 110 then EA = (BP) + DISP"
if rim = 111 then EA = (BX) + DISP
DISP follows 2nd byte of instruction (before data if required)
"except if mod = 00 and rim = 11() then EA = disphigh: disp-Iow.
"MOV CS, REG/MEMORY not allowed.

if s:w = 01 then 16 bits of immediate data form the operand.
if s:w = 11 then an immediate data byte is sign extended
to form the 16-bit operand.
if v = 0 then "count" = 1; if v = 1 then "count" in (Cl)
x = don't care
z is used for string primitives for comparison with ZF FLAG.

SEGMENT OVERRIDE PREFIX

I

001r99110

I

REG is assigned according to the following table:

16-Blt (w = 1)

000
001
010
011
100
101
110
111

a-Blt(w = 0)

AX

CX
OX
BX
SP
BP
SI
01

000
001
010
011
100
101
110
111

AL
CL
OL
BL
AH
CH
OH
BH

Segment

00
01
10
11

ES
CS
SS
OS

Instructions which reference the flag register file as a 16-bit
object use the symbol FLAGS to represent the file:
FLAGS =
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
Mnemonics ® Intel, 197B

4-96

m

80e88/883

HARRIS

CMOS 8/16 Bit Microprocessor

June 1989

Features

Description

• This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

The Harris 80C88/883 high performance 8116-bit CMOS
CPU is manufactured using a self-alligned silicon gate
CMOS process (Scaled SAJI IV). Two modes of operation,
MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to
achieve the highest performance level.

• Compatible with NMOS 8088
• Direct Software Compatibility with 80C86, 8086,
8088
• 8 Bit Data Bus Interface; 16 Bit Internal Architecture
• SMHz Operation ••••••.•••••••••.••••••• 80C88/883

Full TIL compatibility (with the exception of CLOCK) and
industry-standard operation allow use of existing NMOS
8088 hardware and Harris CMOS peripherals.

• 8M Hz Operation ••••••.••••••••••••••• 80C88-2/883
• Low Power Operation
~ ICCSB .••••••••••••••••••••••••• SOOIlA Maximum
~

Complete soltware compatibility with the 80C86, 8086, and
8088 microprocessors allows use of existing software in
new designs.

ICCOP •••••••.•••••••••••••• 10mA/MHz Maximum

• 1 Megabyte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
·8 and 16 Bit Signed/Unsigned Arithmetic
o Bus-Hold Circuitry Eliminates Pull·up Resistors

• Military Operating Temperature ••• -5S o C to +12S 0 C
Range

Pinouts
80C88/883 (CERAMIC DIP)
TOP VIEW
MIN
MODE

80C88/883 (CERAMIC LCC)
TOP VIEW
MAX
MODE

vcc
A15

A161 S3

(HIGH)

RD
(RO IGTO)

ADI

A.D

A.D

A9

A9

A8

A8

AD7

AD7

ADO

ADO

AD.

AD.

(RO IGT1)

AD.

AD.

WR

(LOCK)

ADS

ADS

10/i.!

(S2)

AD.

AD.

DT Iii

(Si)

AD.

AD.

DEN

(SO)

ADO

ADO

ADO

ALE

(OSO)

NMI

INTA

(OSI)

INTR

TEST

:;:

..:;:

:;:

:;:

N

.
.
:;:

:;:" :;:
:;:"

"z z 8 :;:" !!." :;:~... ~.."
:;:
:(
" " >
"
"
!!
~
z" z " :;:
" .. ... ~..
:(
:;: :;:
" " ">
r-

'3.
L_

-.

-.
'2J
-.
-.
'!J
-.':J
-.-.
':J
-.-.
'!SJ
'!J

'!.J

I~J

l~J

'------'---l

READY
RESET

Copyright ©Harris Corpol'alion 1989

4-97

NC
rL~8 A1B/S6
r-

'37

L_

SSD

r_
t~6 UN lUX
r-

'3.
L_

NC
A1B/Se

(HIGH)
UN/LeX

AD

AD

HOLD

ROIGTD

HLDA

na IGT1

WR

LOCK

loili

So

r-

'34
L_

r-

'33
L_
L_
'S'
r'3.
L_
r-

r-

t~o OT /R

S.

r-

So

'2.
L_

DEN

80C88/883
Functional Diagram
EXECUTION UNIT
REGISTER FILE

DATA,
POINTER, AND
INDEX REGS
(SWORDS)

BUS INTERFACE UNIT
RELOCATION
REGISTER fiLE

SEGMENT
REGISTERS

AND
INSTRUCTION
POINTER
(5 WORDS)

r-......::...::'-'-_~

SSo/HIGH

A19/S6

A1el53
AD 7 - AOO

FLAGS

DTtR, DEN, ALE,lOiM

4-BYTE
INSTRUCTION
QUEUE

TEST-~~----~~-----'
INT
NMI

ROIGTo.l
HOLD

HLDA~-~,,_-..-_. ._-..--.~~

eLK

REseT READY MN/MX

aND

Vee

C-BUS

INSTRUCTION
STREAM BYTE
nUEUE

BUS
INTERFACE
UNIT

SS
OS
IP
A-BUS

EXECUTION
UNIT

AH
BH
CH
OH

AL
BL
CL
OL
SP
BP
SI
01

4-98

aso, as,

80C88/883
Pin Description
The following pin function descriptions are for 80C88/883
systems in either minimum or maximum mode. The "local bus"
in these descriptions is the direct multiplexed bus interface

connection to the 80C88/883 (without regard to additional bus
buffers).

SYMBOL

PIN
NUMBER

TYPE

DESCRIPTION

AD7-ADO

9-16

va

ADDRESS DATA BUS: These lines constitute the time multiplexed memoryllO address (T1) and data
(T2, T3, Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last valid
level during interrupt acknowledge and local bus "hold acknowledge" or "grant sequence".

A15-A8

2-8,39

a

ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4). These
lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high
impedance to the last valid logic level during interrupt acknowledge and local bus "hold acknowledge"

A19/S6,
A18/S5,
A17/S4
A16/S3

35
36
37
38

a
a
a
a

or "grant sequence",
ADDRESS/STATUS: During T1, These are the four most significant address lines for memory operations. During I/O operations, these lines are LOW. During memory and
operations, status information is available on these lines during T2, T3,
Tw and T4. S6 is always LOW. The status of the
S4
S3
CHARACTERISTICS
interrupt enable flag bit (S5) is updated at the
0
0
Alternate Data
beginning of each clock cycle. S4 and S3 are
1
Stack
encoded as shown.
0
1
Code or None
0
1
This information indicates which segment register
1
Data
is presently being used for data accessing.

va

These lines are held at high impedance to the last valid logic level during local bus "hold acknowledge"

or "grant sequence".
RD

32

a

va

READ: Read strobe indicates that the processor is periorming a memory or
read cycle, depending
on the state of the 10/M pin or 82. This signal is used to read devices which reside on the SOC88/8S3
local bus. RD is active lOW during T2, T3 and Tw of any read cycle, and is guaranteed to remain HIGH
in T2 until the 80CSS/883 local bus has floated.
This line is held at a high impedance logic one state during "hold acknowledge" or "grant sequence".

READY

22

I

va

READY: is the acknowledgement from the addressed memory or
device that it will complete the
data transfer. The RDY signal from memory or I/O is synchronized by the 82CS4A clock generator to
form READY. This signal is active HIGH. The 80C8S/883 READY input is not synchronized. Correct
operation is not guaranteed if the set up and hold times are not met.

INTR

18

I

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknowlege operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally
masked by software reselling the interrupt enable bit.INTR is internally synchronized. This signal is
active HIGH.

TEST

23

I

TEST: input is examined by the "wait for test" instruction. If the TEST input is lOW, execution continues, otherwise the processor waits in an "idle" state. Thisjnput is synchronized internally during each
clock cycle on the leading edge of ClK.

NMI

17

I

NONMASKABlE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutin
is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a lOW to HIGH initiates the interrupt at the end of the current
instruction. This input is internally synchronized.

RESET

21

I

RESET: causes the processor to immediately terminate its present activity. The signal must transition
lOW to HIGH and remain active HIGH for at leastiour clock cycles. It restarts execution, as described
in the instruction set description, when RESET returns lOW. RESET is internally synchronized.

ClK

19

I

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide optimized internal timing.

VCC

40

GND

1,20

MN/MX

33

VCC: is the +5V power supply pin. A 0.1 ~F capacitor between pins 20 and 40 is recommended for
decoupling.
GND: are the ground pins (both pins must be connected to system ground). A 0.1 ~F capacitor between
pins 1 and 20 is recommended for decoupling.
I

MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are
discussed in the following sections.

4-99

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80C88/883
Pin Description
The following pin function descriptions are for the 80C881
883 minimum mode (i.e., MN/MX = VCC). Only the pin

functions which are unique to the minimum mode are
described; all other pin functions are as described above.

MINIMUM MODE SYSTEM

SYMBOL

PIN
NUMBER

TYPE

DESCRIPTION

28

0

STATUS LINE: is an inverted maximum mode S2.11 Is used to distinguish a memory access from an 1/0
access. 101M becomes valid in the T4 preceding a bus cycle and remains valid until the final T 4 of the
cycle (110 = HIGH, M = LOW). 101M is held to a high impedance logic one during local bus
"hold acknowledge".

WR

29

0

Write: strobe indicate~ that the processor is performing a write memory or write 1/0 cycle, depending
on the state of the 10/M signal. WR is active for T2, T3 and Tw of any write cycle. II is active LOW, and
is held to high impedance logic one during local bus "hold acknowledge".

INTA

24

0

INTA: is used as a read strobe for interrupt acknowledge cycles. II is active LOW during T2, T3 and Tw
of each interrupt acknowledge cycle. Note thatlNTA is never floated.

ALE

25

0

ADDRESS LATCH ENABLE: is provided by the ProClilssor to latch the address into the 82C82/82C83
address latch. It is a HIGH pulse active during clock low of Tl of any bus cycle. Note that ALE is never
floated.

DT/R

27

0

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87
data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to 51 in the maximum mode, and its timing is the same as for 101M (T = HIGH,
R = LOW). This signal is held to a high impedance logic one during local bus "hold acknowledge".

DEN

26

0

DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which
uses the transceiver. DEN is active LOW during each memory and 1/0 access, and for INTA cycles. For
a read or INTA cycle, it is active frorTi the middle of T2 until the middle of T 4, while for a write cycle, it
is active from the beginning of T2 until the middle of T 4. DEN is held to high impedance logic one during
local bus "hold acknowledge".

HOLD,
HLDA

31
30

I
0

HOLD: indicates that another master is requesting a local bus "hold". To be acknowledged, HOLD
must be active HIGH. The processor receiving the "hold" request will issue HLDA (HIGH) as an
acknowledgment, in the middle of a T4 orTI clock cycle. Simultaneous with the issuance of HLDA the
processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the
local bus and control lines.

101M

Hold is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the set up time.
SSO

34

0

STATUS LINE: is logically equivalent to SO in the
maximum mode. The combination of SSO, 10/M
and DT/R allows the system to completely
decode the current bus cycle status. SSO
is held to high impedance logic one during
local bus "hold acknowledge".

4-100

loiM

DT/R

SSO

CHARACTERISTICS

1
1
1
1
0
0
0
0

0
0

0

0

Interrupt Acknowledge
Read 1/0 Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory

1

Passive

1
1
0
0

1
1

1
0
1
0
1

80C88/883
Pin Description
The following pin descriptions are for the BOCBB/BB3
system in maximum mode (i.e., MN/MX = GND). Only the

pin functions which are unique to maximum mode are
described; all other pin functions are as described above.

MAXIMUM MODE SYSTEM
SYMBOL

PIN
NUMBER

TYPE

SO
S1
S2

26
27
28

0
0
0

DESCRIPTION
STATUS: is active during clock high of T4, T1
and T2, and is returned to the passive state
(1, 1, 1) during T3 or during Tw when READY
is HIGH. This status is used by the 82C88
bus controller to generate all memory and I/O
access control signals. Any change by S2, S1 or
SO during T4 is used to indicate the beginning of
a bus cycle, and the return to the passive state
in T3 or Tw is used to indicate the end of a bus
cycle.

S2

S1

SO

CHARACTERISTICS

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive

These signals are held at a high impedance logic
one state during "grant sequence".
RQ/GTO,
RQ/GT1

31
30

I/O

REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local
bus at the end of the processor's current bus cycle. Each pin is bidirectional with RQ/GTO having
higher priority than RQ/Gn. RQ/Gr has internal bus-hold high circuitry and, if unused, may be left
unconnected. The requesl!grant sequence is as follows (see RQ/GT Timing Sequence):
1. A pulse of one ClK wide from another local bus master indicates a local bus request ("hold") to the
80C88/883 (pulse 1).
2. During a T4 or TI clock cycle, a pulse one clock wide from the 80C88/883 to the requesting master
(pulse 2), indicates that the 80C88/883 has allowed the local bus to float and that it will enter the
"grant sequence" state at the next CLK. The CPUs bus Interface unit is disconnected logically from
the local bus during "grant sequence".
3. A pulse one ClK wide from the requesting master indicates to the 80C88/883 (pulse 3) that the
"hold" request is about to end and that the 80C88/883 can reclaim the local bus at the next ClK.
The CPU then enters T4 (or TI if no bus cycles pending).
.
Each master-master exchange of the local bus Is a sequence of three pulses. There must be one Idle
ClK cycle after bus exchange. Pulses are active lOW.

If the request is made while the CPU Is performing a memory cycle, it Will release the local bus during
T4 of the cycle when all the following conditions am met:
1.
2.
3.
4.

Request occurs on or before T2.
Current cycle is not the low bit of a word.
Current cycle is not the first acknowledge of an inlerrupt acknowledge sequence.
A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:
1. local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle
apply with condition number 1 already satisfied.
lOCK

29

o

lOCK: indicates that other system bus masters are not to gain control of the system bus while lOCK
is active (lOW). The lOCK signal is activated by the "lOCK" prefix instruction and remains active until
the completion of the next instruction. This signal is aclive lOW, and is held at a high.impedance logic
one state during "grant sequence". In Max Mode, lOCK is aulomatically generated during T2 of the
firstlNTA cycle and removed during T2 of the second INTA cycle.

QS1,
QSO

24,25

0

QUEUE STATUS: provide status to allow
external tracking of the Internal 80C88/883
instruction queue.
The queue status is valid during the ClK cycle
after which the queue operation is performed.
Note that the queue status never goes to a
high impedance state (floated).

-

34

0

aS1

aso

0
0

0
1

1
1

0
1

CHARACTERISTICS
No Operation
First Byte of Opcode From
Queue
Empty the Queue
Subsequent Byte From
Queue

Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during a
"grant sequence".

4-101

Specifications 80C88/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••..••••.•••••••.•••••••••.••••••••.••• +B.OV
Input, Output or I/O Voltage Applied. • • •• GND-0.5V to VCC+0.5V
Storage Temperature Range ••.••.•••.••.•.•• -650C to +1500C
Junction Temperature •••••.••••••....•.•••••••••••••. +1750 C
Lead Temperature (Soldering 10 sec) •.••.•••••••••••••• +3000 C
ESD Classification •.••.•••••••••.•••..••..••••••••••.• Class 1

Thermal Resistance
aja
ajc
Ceramic DIP Package •..••••..•.•••••• 27.50 C/W 5.90 CIW
Ceramic LCC Package. • . • • • . • • • • • • . •. 62.2 0 C/W B.60 CIW
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ••.•••.••••••.•.••.••.•••••••••. 1.B2W
Ceramic LCC Package ...••••••••••.•...•.......•.• B06mW
Gate Count ..•••••..•.•.•.•••....••.••.•••••••••. 9750 Gates

CAUTION:

Stresses above those listed;n "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a sf/ess only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Supply Voltage ••.••.•.•.••••.••••.•• +4.5V to +5.5V
BOCBB-2/BB3 ONLy •.•..•.••••••.•••••••• +4.75Vto +5.25V

Operating Temperature Range ••..••••••••••• -550C to +1250 C

TABLE 1. BOCSS/SS3 D.C. ELECTRICAL PERFORMAl'i:CE CHARACTERISTICS
Device Guaranteed and 100% Tested, BOCBB/BB3: VCCL = 4.5V, VCCH = 5.5V, fmax = 5MHz;
BOCBB-2/BB3' VCCL = 475V. VCCH = 5 25V. fmax = BMHz

PARAMETER

SYMBOL

(NOTE 1)
CONDInONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Logical One Input
Voltage

VIH

VCC = VCCH, Note 2

1,2,3

-550C9A5.+1250C

2.2

-

V

Logical Zero Input
Voltage

VIL

Note 2

1,2,3

-55 0C9A5.+125OC

-

O.B

V

VCC=VCCH

1,2,3

-550C9A5.+1250C

VCC-O.B

-

V

1,2,3

-550C9A:5.+1250C

-

O.B

V

10H = -2.5mA, Note 3
10H = -100~A, Note 3

1,2,3
1,2,3

-550C9A:5.+125OC

3.0
VCC-O.4

VOL

10L = +2.5mA, Note 3

1,2,3

-550C9A:5.+1250C

II

VCC=VCCH,
VIN = GND orVCC
DIP Pins: 17-19, 21-23,
33

1,2,3

-55 0C9A:5.+1250C

CLK Logical One Input
Voltage

VIHC

CLK Logical Zero Input
Voltage

VILC

Output HIGH Voltage

VOH

Output LOW Voltage
Input Leakage Current

-

V
V

-

0.4

V

-1.0

+1.0

~

Input Current Bus
Hold High

IBHH

VIN = 3.0V, Note 4
VCC = VCCL & VCCH

1,2,3

-550C9A:5.+1250C

-40

-400

~

Input Current Bus
Hold Low

IBHL

VIN = O.8V, Note 5
VCC = VCCL & VCCH

1,2,3

-550C9A:5.+1250C

40

400

~

VCC=VCCH,
VOUT = Ov, Note 6

1,2,3

-550C9A:5.+1250e

-

-10

~

Output Leakage Current

10

Standby Power Supply
Current

ICeSB

VCC = VCCH, Note 7

1,2,3

-55 0C5.TA:5.+1250C

-

500

~

Operating Power Supply
Current

ICCOP

vec = VCCH, f = fmax,
VIN = VCC or GND,
Outputs Open

1,2,3

550C5.TA:5.+1250C

-

10

mNMHz

NOTES: 1.
2.
3.
4.
5.
6.
7.

All voltages referenced to device GND, vee = VCCL unless otherwise specified.
MN/MX is a strap option and should be held to vee or GND.
Interchanging of forcs' and sense conditions is permitted.
IBHH should be measured after raising VIN to vee and then lowering to valid input high level of 3.0V on the following pins: 2-16, 26-32,34-39.
IBHL should be measured after lowering VIN to GND and then raising to valid input low level of O.SV on the following pins: 2-16, 35-39.
10 should be measured by putting the pin in a high impedance stale and then driving vour to GND on the following pins: 26-29. 32.
ICCSB tested during clock high time after HALT instruction execution. VIN = VCC or GND. VCC = VCCH, outputs unloaded.

CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.

4-102

Specifications 80C88/883
TABLE 2. BOCBB/BB3 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested, BOC88/B83: VCCL 4.5V, VCCH
5.5V,
80C88-2/883: VCCL = 4.75V, VCCH = 5.25V

=

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

=

80CB8-2/8B3

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

MIN

80CBB/883
MAX

UNITS

ns

MINIMUM COMPLEXITY SYSTEM TIMING
CLK Cycle Period

(l)TCLCL

9,10,11

-550CgA~+1250C

125

-

200

CLKLowTime

(2)TCLCH

9,10,11

-550C:S.TA~+1250C

68

118

CLK High Time

(3)TCHCL

9,10,11

-550C:S.TA~+1250C

44

-

Data In Setup Time

(6)TDVCL

9,10,11

-550 CgA:S.+1250C

20

-

30

Data In Hold Time

(7)TCLDXl

9,10,11

-550CgA:S.+1250 C

10

-

10

READY Setup Time
into BOC8B/883

(10)TRYHCH

9,10,11

-550C.:5.TA~+1250C

68

-

llB

-

READY Hold Time
into BOC88/883

(ll)TCHRYX

9,10,11

-550 C.:5.TA:S.+1250C

20

-

30

-

ns

READY Inactive
toCLK

(12)TRYLCL

9,10,11

-550C~.TA:S.+1250C

-8

-

-8

-

ns

9,10,11

-550 CgA:S.+1250C

20
15

30

-

ns

-550 CgA:S.+1250 C

-

35

9,10,11

-55 0CgA:S.+1250C

10

60

10

110

ns

10

-

10

-

ns

Note 2

HOLD Setup Time

(13)THVCH

INTR, NMI, TEST
Setup Time

(14)TINVCH

Address Valid Delay

(17)TCLAV

9,10,11

Address Hold Time

(lB)TCLAX

9,10,11

-550C~.TA:S.+1250C

ALE Width

(22)TLHLL

9,10,11

-550CgA:5.+1250C

TCLCH
-10

ALE Active Delay

(23)TCLLH

9,10,11

-550CgA:5.+125OC

(24)TCHLL

9,10,11

-550C:S.TA:5.+1250C

-

50

ALE Inactive Delay
Address Hold Time
to ALE Inactive

(25)TLLAX

9,10,11

-550C.:5.TA:5.+1250C

TCHCL
-10

-

Note 3

55

69

TCLCH
-20

ns
ns
ns
ns
ns

ns

ns

-

80

ns

85

ns

TCHCL
-10

-

ns

(26)TCLDV

9,10,11

-550C.:5.TA:S.+1250C

10

60

10

110

ns

Control Active
Delay 1

(29)TCVCTV

9,10,11

-550CgA:5.+1250C

10

70

10

110

ns

Control Active
Delay 2

(30)TCHCTV

9,10,11

-550 CgA:S.+1250C

10

60

10

110

ns

Control Inactive
Delay

(31)TCVCTX

9,10,11

-550CgA.:5.+1250C

10

70

10

110

ns

Data Valid Delay

RD Active Delay

(33)TCLRL

9,10,11

-550C.:5.TA.:5.+1250C

10

100

10

165

ns

RD Inactive Delay

(34)TCLRH

9,10,11

-550C.:5.TA:5.+1250C

10

BO

10

150

ns

RD Inactive to Next
Address Aclive

(35)TRHAV

9,10,11

-550CgA:S.+1250 C

TCLCL
-40

TCLCL
-45

-

ns

-

HLDA Valid Delay

(36)TCLHAV

9,10,11

-550 C.:5.TA.:5.+1250C

10

100

10

160

ns

RDWidth

(37)TRLRH

9,10,11

-550C.:5.TA.:5.+1250C

2
TCLCL
-50

-

2
TCLCL
-75

-

ns

WRWidth

(3B)TWLWH

9,10,11

-550C.:5.TA~+1250C

2
TCLCL
-40

-

2
TCLCL
-60

-

ns

(39)TAVAL

9,10,11

-550C::;,TA:5.+1250C

TCLCH
-40

-

TCLCH
-60

-

ns

Address Valid to
ALE Low
NOTES: 1. VCC

= VCCL, CL = 100pF, f = lMHz

3. Setup requirement for asynchronous signal only to guarantee
recognition at next clock.

2. Applies only to T2 state (8ns into T3)

CAUTION: These devices are sensitive to electronic discharge. Proper Ie handling procedures should be followed.

4-103

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Specifications 80C88/883
TABLE 3. BOCBB/BB3 ELECTRICAL PERFORMANCE CHARACTERISTICS
8OCSS/S83' VCCL = 4 5Y., VCCH = 5 5Y. SOCSS-2/SS3' VCCL = 475Y. VCCH = 5 25V
SOCSS/SS3

BOCBB-2/BB3
PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

1

TA=+250 C

-

25

-

25

pF

-

25

pF

25

pF

10

ns

MINIMUM COMPLEXITY SYSTEM TIMING
Input Capacitance
Output Capacitance

CIN
COUT

f=1MHz,AII
measurements are
referenced to GND

1

TA=+250 C

-

25

1

TA=+250 C

_.

25

CLK Rise Time

TCH1CH2
(4)

From 1.OV to 3.5V

1

-550 CS.TAS,+1250 C

-

10

-

CLKFallTime

TCL2CL1
(5)

From 3.5V to 1.OV

1

-550 CgAS,+1250 C

-

10

-

10

ns

RDY Setup Time
IntoS2C84A

TR1VCL
(S)

CL=100pF,
VCC=VCCL,
f=)MHz

1,2,3

-550 CgAS,+1250 C

35

-

35

-

ns

ROY Hold Time
IntoS2CS4A

TCLR1X
(9)

CL=100pF,
VCC=VCCL,
f=1MHz

1.2.3

-550 CgAS,+1250 C

0

-

0

-

ns

Input Rise Time
(Except CLK)

TILIH
(15)

From O.SV to 2.0V

1

-550 CS.TAS,+1250 C

-

15

-

15

ns

Input Fall Time
(Except CLK)

TIHIL
(16)

From 2.0V to O.SV

1

-550CgAS,+1250C

-

15

-

15

ns

CL=100pF,
VCC=VCCL,
f=1MHz

1

-550CgAS,+1250 C

TCLAX

50

TCLAX

SO

ns

I/O Capacitance

CI/O

Address Float Delay

TCLAZ
(19)

Status Float Delay

TCHSZ
(20)

1

-550 CgAS,+1250 C

-

50

-

SO

ns

Data Hold Time

TCLDX2
(27)

1

-55ocgA!S.+1250C

10

-

10

-

ns

Data Hold Time
AfterWR

TWHDX
(2S)

1

-55ocgAS,+1250 C

TCLCL
-30

TCLCL
-30

-

ns

Address Float To
RDActive

TAZRL
(32)

1

-550 CgA!S.+1250C

0

-

0

-

ns

Output Rise Time

TOLOH
(40)

From O.8V to 2.0V

1

-550 CgA!>.+1250 C

-

15

-

15

ns

Output Fall Time

TOHOL
(41)

From 2.0V to O.SV

1

-550 C!>.TA!>.+1250C

-

15

-

15

ns

-

NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon
initial design and after major process and/or design changes.
2. Signal at 82C84A shown for reference only,
3. Setup requirement for asynchronous signal only to guaranl~e recognition at next clock.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3, SA, SB, 10, 11

-

1,2,3,7, SA,SB, 9, 10, 11

Samples/5005

1,7,9

Group A
GroupsC&D

CAUTION: These deviCes are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.
4-104

80C88/883
Waveforms
BUS TIMING - MINIMUM MODE SYSTEM

~'b
141
T'A
151 T,
Tw
I ,---.-..I--TCL ~ TCH1CH2.j +- --J II-TCL2CL: .....

L

CLK (82C84AOutpUI) -J It

'~

_'-:hl;=-

I--

130lTCHCTV
sso

10M

~ If .. '~ ir-\

~

I+-Tt~CH!

TCHCLI31

--

~

A,!o-A a (Float during INTA)

TCLAH 1171 ~

+-

~
1301

1171
I4-T CLAY

,if

1""- 1171
1261 ~T~LDV
I+-TCLAY
--+
TCLAX. 1181 ro-,...,.I---t---+--+---~--t-..... lr-

-

___i_-----+--JI,~_+-A-,,-.A~,~,+_--J~'-_i_----_+------S-'+.S-'----~------_+----~---'I~
' -__
TCLLH-. 1+ -TLHLL=C 21
~TLLAXI251
I 1231
I,
ALE

/
-t---J~HLLJ ~'+f---+-+--+--1-81-i1-f--·T-R-'V-C-L+---t---+--....I.--1241

+-Ti;~L-+

ROY (82C84A Input)

SEE NOTE.

:~:~~LI_ ~"\~~~~~\\~~
1

I"::::;

!+-TCLR1X 191

TIR~R21-

'''"''~ '"'"'{

1

f-I"""+----I------

1111
11,...-_+",i-TCHRYX
1101
TRYHCH
_

--+ 1191

~TCLAZ

--i1---_ _ _ _'"_-_-_-_-_1-32=IT=A:Z_R-L=-~:~I:-~
1301

READ CYCLE

_ _ (NOTE I)
(WR. INTA

TCHCTV

= VOH )

r-TDV~L_~Td~bxl.
...............++- -- --~
DATA IN

f-- -+-IT'-1\

AD,.AD,'

ADrADo

-=:;

TCLRH_ 1341 _

f-T-:A7 -- 1351

I~~--II---------+-~I~

T~~kLI+---.l+-!--/+--Ti~nH

---+---+l1t

FCHCTV 1301

DTR

129ITCVCTV-+

~ ri
''+1250C

0

50

0

B5

ns

RDWidlh

(45)TRLRH

9,10,11

-550CgA:>.+1250C

2
TCLCL
-50

-

2
TCLCL
-75

-

ns

NOTES: 1.
2.
3.
4.
5.

tn

VCC = VCCL. CL = 100pF,f = 1MHz
Applies only 10 T2 slale (Bns inlo T31
Setup requirement for asynchronous signal only to guarantee recognition at next clock.
The BOCBS aclively pull. Ihe RQ/GT pin 10 a logic one on Ihe following clock low lime.
Status lines relum to their inactive (logic one) state after elK goes low and READY goes high.

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie handling procedures should be followed.
4-107

en
en'"
0 0

::Eo

og:

°u=
55

Specifications 80C88/883
TABLE 3. SOCSS/SS3 ELECTRICAL PERFORMANCE CHARACTERISTICS
eoC88/883' VCCL = 4 5V,, VCCH = 5 5V,, 80C88-2/883' VCCL = 475V,, VCCH = 525V
8OCSS~2/SS3

PARAMETER

SYMBOL

CONDmONS

NOTES

TEMPERATURE

.

·SOCSS/SS3

MIN

MAX

MIN

MAX

UNITS

-

25

-

25

pF

-

25

-

25

pF

25

pF

10

ns

.

MAXIMUM MODE SYSTEM TIMING (USING 82C88 BUS CONTROLLER)
Input Capacitance
Output Capacnance

CIN
COUT

f=1MHz,AII
measurements are
referenced to GND

1

TA=+25OC

1

TA=+25OC

1

TA=+25OC

CLKRiseTIme

TCH1CH2
(4)

From 1.0Vto 3.5V

1

-550C!0"ASo+1250 C

-

CLKFailTime

TCL2CL1
(5)

From 3.51/ to 1DV

1

-550C!0"ASo+1250 C

I/O Capacitance

CI/O

10

-

-

10

-

10

ns

25

ROY Setup TIme
Into 82C84A

TR1VCL
(8)

CL=100pF,
VCC=VCCL,
f=1MHz

1,2,3

-550C!0"ASo+1250C

35

-

35

-

ns

RDYHoldTIme
Into 82C84A

TCLR1X
(9)

CL=100pF,
VCC=VCCL,
f= 1MHz

1;2,3

-55OC!0"A~+1250C

0

-

0

-

ns

Input Rise Time
(Except CLK)

nUH
(16)

From O.8V to 2DV

1

-55ocgASo+1250 C

-

15

-

15

ns

Input Fall Time
(Except CLK)

TIHIL

From 2.0V to O.8V

1

-55ocgASo+1250 C

-

15

-

15

ns

1,2

-55OC!0"A~+1250C

5

35

5

35

ns

(m

Command Active
Delay

TCLML
(18)

Command Inactive
Delay

TCLMH
(19)

1,2

-550C!0"ASo+1250C

5

35

5

35

ns

Address Float
Delay

TCLAZ
(25)

1

-55OC!0"A....+1250C

TCLAX

50

TCLAX

eo

ns

Status Float Delay

TCHSZ
(26)

1

-55OC!0"ASo+1250 C

-

50

-

·eo

ns

Status Valid To
ALE High

TSVLH
(27)

1,2

-550C!0"A!>+1250 C

-

20

-

20

ns

Status Valid To
MCEHlgh

TSVMCH
(28)

1,2

-55OC!0"ASo+125o C

-

30

-

30

ns

CLKLowTo
AlEValic!

TCLLH
(29)

1,2

-550C!0"ASo+1250 C

-

20

-

20

ns

CLKLowTo
MCEHigh

TCLMCH
(30)

1,2

-550CgASo+1250C

-

25

-

25

ns

ALE Inactive Delay

TCHLL
(31)

1,2

-550C!0"A$.+1250 C

4

18

4

18

ns

MCE Inactive Delay

TCLMCL
(32)

1,2

-55OCSTA~+1250C

-

15

-

15

ns

Data Hold Time

TCLDX2
(34)

1

-550CgA~+1250C

10

-

10

-

ns

Control Active
Delay

TCVNV
(35)

1,2

-55OCgA~+12SOC

5

45

5

45

ns

Conlrollnactive
Detay

TCVNX
(36)

1,2

-55OC!0"ASo+1250C

10

45

10

45

ns

CL=100pF,
VCC=VCCL
f=1MHz

NOTES: 1. The parameters listed In Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon

initial design and after major process and/or design changes.
2. Signal at 82C84A or 82C88 shown lor reference only.
3. Setup requirement for asynchronous signal only to guarantee recognition at next clock.
CAUTION: These devices are .ensKlve to electroniC discharge. Proper IC handling procedures should be Iollowed.

4-108

Specifications 80C88/883
TABLE 3. SOC88/883 ELECTRICAL PERFORMANCE CHARACTERISTICS (Conllnued)
80C88/883: VCCL

= 4.5V, VCCH = 5.5V, 80C88-2/883: VCCL = 4.75V, VCCH =

5.25V
SOC88-2/SS3

PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

SOCSS/SS3

MIN

MAX

MIN

MAX

UNITS

MAXIMUM MODE SYSTEM TIMING (USING 82C88 BUS CONTROLLER, (Continued)
Address Float To
Read Active

TAZRL
(37)

Direction Control
Active Delay

TCHDTL
(41)

Direction Control
Inactive Delay

TCHDTH
(42)

Output Rise Time

TOLOH
(46)

Output Fall Time

TOHOL
(47)

1

-550C::;TA::+1250C

0

-

0

-

ns

1,2

-550C::;.TA::;'+1250C

-

50

-

50

ns

1,2

-550CgA:S+1250C

-

30

-

30

ns

From 0.8V to 2.0V

1

-550C:s:rA$..+1250C

-

15

-

15

ns

From 2.0V to 0.8V

1

-550C:s:rA::;'+1250C

-

15

-

15

ns

CL=100pF,
VCC=VCCL,
f=1MHz

NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are nol directly tested. These parameters are characterized upon
initial design and after major process and/or design changes.
2. Signal at 82CB4A or 82C88 shown for reference only.

TABLE 4. APPUCABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

FinalTest

100%

2,3,8A,8B,10,11

Group A

-

1,2,3,7, SA, 8B, 9, 10, 11

Samples/5005

1,7,9

'"oII:

'"
'"
"'::;:0
....
o~

~g:

o

GroupsC&D

CAUTION: These devices are sensitive to electronic discharge. Proper

Ie

handling procedures should be followed.

4-109

II:

~

:s

80C88/883
Waveforms
BUS TIMING - MAXIMUM MODE

di

141

T,

~ _TCLC~ TCH1CH4IH

~. 151T,
TCL2CL~~

T.

r---"

CLK
- ' 1231

I' - _ - I

.131

~,.C_H-t_ _+:-_

-

A,-·-+---+-

..,-t---:-tI+----. TCHSV 1211
5:.5;. S;; (EXC~PT HALT)

~

'-------",

TCLA~ ~ ~
-+

1221 j4-TCLSH

t--T-\-- - -

---..,+----+---+--+--+--tJ~-rij',.,.,.j
j,1jjf"1'r7'_r(-+SE-E-NO-TE-8-)
I~--~--r--~r-~~~

~

-~--I--~Ir~-~-~-~~~-~-~-~~rA, ..-As

1231
TCLAV I.....

I+-

1271TsvLH-+
129ITCLLH_
ALE ( 82C88 OUTPUT)

J+- _

1241

TCL~

LTCLD~VI331

TCL;w+ 1231 -

--~~~Ir~--~~Ir-+---~~-r--~--~--_+,,--

A,,·A..

I+-

I

-

)I(,-+__+-+__S_'I-.S_'_-+_ _ _+ __+-Jr_'-_

I+- TCHLLI311

,I

"

SEE NOTE 5 {

I

r--

~----~--~~--+---~----+---~---

TRI VCL 1-1.181 -

ROY (82C84 INPUT)

1121

~~.r-t--m'~~~~~~R~~19~~~~:\\\~~~~~~~~~~~~~~~~~~
l+-

TRYLC.=.:t!
I

\1
1111
_I '--+--+_-:-11-_'1
_
I-TCHRYX

1201 ----'
TRYHSH" t1r-f-=-t-.....d
1231
TCLAV---,-+

READ CYCLE
AD,-AD"

TC~

,I;::..

24

TCL~ 1251

1381

{

DEN

S.
6.
7.
8.

I:~:~NRHI+--_"*,H).I_;~:~~

~IV'\.-+1 _ _ _ _ _ _ _+-...Jj'l"\

!~\
~

1451

------TRLRH-------+----~I

1421
rTCHDTH

------------~-----H-----~11~91---+----~~\1\

1181 TCLML_

'.'\.-_H-,,_,..__-_-_-_-_-_T~C-L_-M_H-'_-_-__-:_-'. ,~,;IF,:. . .-.I.!\~\____

1351 TCVNV -

:;,--

J

-------------"
NOTES: 1.
2.
3.
4.

11'-----1-----17J.

161--TDVCL- +TCLDX1-.j

=====~~~~-~;II:~~~:-A-I-:-;-;A-T-:=:tRI-L=_=~j~~ ~ ~
~

8~~:SN~~VsUl.S6 MRDc OR IORC

--- TRYHCH -

I+-

1411
{I:CLR;I+TCHDTL-+
__________________
DTR

1101

.-~- I I J+-

1361
TCVNX_

F

All signals switch between VOH and VOL, unless otherwise specified.
ROY is sampled near the end of T2. T3, Tw to determine if,Tw machine states are to be inserted.
Cascade address is valid between first and second INTA cycles.
Two INTA cycles run back-to--back. The 80C88/883 local ADDR/DATA bus is floating during both INTA
cycles. Control for painter address is shown for second i"NTA. cycle.
Signals at 82C84A or 82C88 are shown for reference only.
The issuance of the 82C88 command and control signals (MRDC, MWTc, AMWC, )ORC, iOWC, AIOWC,
INTA and DEN) lags the active high B2CBB CEN.
All timing measurements are made at 1.SV unless otherwise noted.
Status Inactive in state just prior to T 4. .

4-110

80C88/883
Waveforms

(Continued)

BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)

T,

T,

T,

T.

ClK

5 2 .5" So (EXCEPT HALT)
WAITE CYCLE

AD,-AD o

82C88 OUTPUTS
SEE NOTES 5, 6

AMWC OR AiOwC

MWTC OR lowe

INTA CYCLE
A,~·All

(SEE NOTES 3. 4)

161
AD" AD o

TDVCL-+
POINTER

--c
---

MCE
PDEN

OTR

82C88 OUTPUTS
SEE NOTES 5. 6

iNiA

DeN

SOFJX'~R_ERo. MiiDc. i'ORc. MWTC. AMWC. lowe, AIOWC. TN'TA. SO. Si .: :

VOH

AD,-AO o. A,.,-A 8

TCHSV

NOTES: 1.
2.
3.
4.
5.
6.
7.
8.

TCLSH

All signals switch between VOH and VOL, unless otherwise specified.
ROY is sampled near the end of T2, T3. Tw to determine if Tw machine states are to be inserted.
Cascade address is valid between first and second iNTA cycles.
Two iNi'A cycles run back-to-back. The 80C88/883 local ADDR/DATA bus is floating during both INTA
cycles. Control for pointer address is shown for second INTA cycle.
Signals at 82C84A or 82C88 are shown for reference only.
The issuance of the 82C88 command and control signal. (MRDC, MWTC, AMWC. lORC, lOWC, AIOWC,
iiiiTA and DEN) lags the active high 82C88 CEN.
All timing measurements are made at 1.SV unless otherwise noted.
Status inactive in state just prior to T 4.

4-111

80C88/883
Waveforms (Continued)
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLy)

A,..A, _ _ _ _ _ _ _ _ _ _ _ _-<
AD..-ADg

A'~:~~;~
5,.5,,5,

------------------+""'1

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'1

NOTE: The coprocessor may not drive the busses outside the region shown without risking contention

HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

ClK

HOLD

HlOA

ADrADo

RD, WR, 10

,

ri~'::C ,--<, 1.,oR1CYClES{"\.-

~'-"
--

~

__...,_~-"
_

.k---

,-ifF
!::clHAV1361

',---=--(ClHAV 136)

'

I--T~~lz

----8-0C-8-8--..:. . .+-~*''_

____C_O_PR_O..CE..S-S-O-R----"1-= S

SOCS8

~_H~_+~-120J' =================~=t=~~

M. DT R. DEN. SSii ___________

NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next elK

ASYNCHRONOUS SIGNAL RECOGNITION

BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY)

ClK~
)13)

===X

NM'}
INfR

Any eLK CYCle+1

ClK

TlNVC" (see not.,)

signal

TEsT

NOTE: Setup requirements for asynchronous signals only to guarantee
recognition at next eLK

4-112

80C88/883
Waveforms (Continued)
RESET TIMING

VCC

ClK
(7)

RESET

T~~g~~~

(6)TD~

~ 4 ClK CYCLES

A. C. Test Circuit
OUTPUT FROM
DEVICE UNDER TEST

A.C. Testing Input, Output Waveform

CC---I+---CL*

~

·Includes stay and jig capacitance

TEST
POINT

INPUT

OUTPUT

VlH + 2O%VlH

VOH

1.5V~
VIL - !iO'lIoVIL

~1.5V
Val

AC. Testing: All input signals (other than elK) must switch between
Vilmax -50'l1> Vil and VIHmin +20'l1> VIH. elK muslswHch
belween O.4V and vee -O.4V. Input ri.e and fall times are

driven at 1nsN.

4-113

80C88/883
Burn-In Circuits

80C88/883 (CERAMIC DIP)

I-""'II"-R"IO,,- VCl
RO VII
RO VII
RO VII
RO VII
RO VII

l-""'II"-""-VlI
I-"",,,,,,R::.I_ VCl
I-"",,,,,,R,,,O,- VCl
RO VII

OPEN

RO VII

OPEN

RO VII

OPEN

RO VII

OPEN

RO VII
RO VII

GND----i
GND----i

i+----GND

I-"",,,,,,R:;,.I_ VCl
I-""'II"-R:;,.I- NODE
FROM

GND----i

0

PROGRAM
CARD

80C88/883 (CERAMIC LCC)

1 ' ._01
'44' ,,-;.II
'43" 142'
141' .-"'
'40'
"_of ".._2.. "L_J
.. ._;.11

' 6...
"5
" , ,-'"
'13
_ ...

RIO

~-

I

_~

+-1\II.t\r-l ~]
6-1-I...R"IO/\,.-I

[~9

RIO

"-1-1'\1\"'"--1

RD

[~81--vl1V'''''''

€] .
-..

r-

'!.J

.,.

~2A.

L~71--vl1V'''''''

"-1-I"':"::","--I1E]

L!ol--R-O-++'

6-I\IIRI"'01r--I1~~

!~5I--./I,N"""

6-1\II.t\r-l'.!'J

~~41-"'·",;~"AIV'A.___

+-I\IIRI",°1r--I1~]

[~31-"""~,,AI\J\.-+"

1~~

!~2I--./I,:/lPOI'' ..

1~~
1.!'J

~~1I--./I,R/l01'-"
L~OI-"",IV'''''''

[~9I--./I,R/l0I'-"

11]

r-' r-, r-, r-, r-, r-, r-, r-, r-., r-, r-.,

'181119112011211122.123112411251126112711281

a:
GND

a:~

l;1

l;1~

-JJ:======dbd:~~d:==:!:=~d=~:;======;:!j1
(3)
FO

NOTES:
1. VCC = 5.5V ± O.5V, GND = OV
2. Input Voltage Limits:
Vil (Maximum) = OAV
VIH (Minimum) = 2.6V
3. VII is external supply set to 2.7V
4. VCl is generated on program card (VCC - 1.2V)
5. Pins 13 - 16 input sequenced instructions from internal
hold devices, (DIP Only).

(FROM PROGRAM CARD)

COMPONENTS: (per card)
1. RI = 10kO ± 5%,1/4W (4)
2. RO = 1.2kO ± 5%, 1/4W (12)
3. RIO = 2.7kO ± 5%, 1/4W (16)
4. RC = 1kO ± 5%, 1/4W (1)

5. C

4-114

=:

O.Ol/-1F Minimum

VII

80C88/883
Metallization Topology
DIE DIMENSIONS:
249.2 x 290.9 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11 kA ± 2kA
GLASSIVATION:
Type: Si02
Thickness: BkA ± 1kA
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm 2

Metallization Mask Layout
80C88/883
A11

A12

A13

A14

vee

GND

A15 A16/53

A 17 /54

A 18/55

A19/S6
Ala

A9
ssa

MN/Mx

AB

en

a:

0

en
en
en W
ot.:>
::0

AD
AD7

uli:
0
a:

!::i!

::

HOLD
AD6

ADS

HLDA
AD4

AD3

AD2

10/M

ADl

ADO

NMI

INTR

elK

GND

RESET

4-115

READY TEST

lNTA

ALE

80C88/883
Packaging t
40 PIN CERAMIC DIP
2.035

~

I

2.096

.160

,....----

'J

~
.180

.016.
.023

.100
BSC

..Q:

.~~

15'

.050·
• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FlNISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
, Temperature: 450 0 C ± 100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 385100-5

44 PAD CERAMIC LCC
(BOnOM VIEW)

.643
.662

.045
.055

.050
BSC

.662
I

---.J~.077

.063

I

Ilnnnnnnnnnnnll
.073n
.089

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: GoldfTIn (80/20)
Temperature: 3200 C ± 100 C
Method: Furnace Braze

NOTE: All Dimonslons are

~

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-5

t MiI-M-38S10 Compliant Materials, Finishes, and Dimensions.

• Dimensions are in inches.

4-116

mHARRIS

80e88

DESIGN INFORMATION
CMOS 8/16 Bit Microprocessor
The information contained in this section has been developed through characterization by Harris Semiconductor and is tor
use as application and design information only. No guarantee is implied.

Functional Description

through the BIU for processing by the EU, which passes
results to the BIU for storage.

Static Operation
All SOCSS circuitry is static in design. Internal registers,
counters and latches are static and require no refresh as
with dynamic circuit design. This eliminates the minimum
operating frequency restriction
placed
on other
microprocessors. The CMOS SOCSS can operate from DC
to the specified upper frequency limit. The processor clock
may be stoped in either state (high/low) and held there
indefinitely. This type of operation is especially useful for
system debug or power critical applications.
The SOCSS can be single stepped using only the CPU
clock. This state can be maintained as long as is necessary.
Single step clock operation allows simple interface circuitry
to provide critical information for start-up.
Static design also allows very low frequency operation (as
low as DC). In a power critical situation, this can provide
extremely low power operation since SOCSS power dissipation is directly related to operation frequency. As the system
frequency is reduced, so is the operating power until, at a
DC input frequency, the power requirement is the SOCSS
standby current.
Internal Architecture
The internal functions of the SOCSS processor are partitioned logically into two processing units. The first is the
Bus Interface Unit (BIU) and the second is the Execution
Unit (EU) as shown in the CPU block diagram.

Memory Organization
The processor provides a 20 bit address to memory which
locates the byte being referenced. The memory is organized
as a linear array of up to 1 million bytes, addressed as
OOOOO(H) to FFFFF(H). The memory is logically divided into
code, data, extra, and stack segments of up to 64K bytes
each, with each segment falling on 16 byte boundaries.
(See Figure 1).
All memory references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of programs. The segment register to be selected is automatically
chosen according to specific rules as shown in Table A. All
information in one segment type share the same logical
attributes (e.g., code or data). By structuring memory into
relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter,
faster, and more structured.

en

a:

o

Word (16 bit) operands can be located on even or odd
address boundaries. For address and data operands, the
least significant byte of the word is stored in the lower
valued address location and the most significant byte in the
next higher address location.
7

-t----}

These units can interact directly but for the most part perform as separate asynchronous operational processors.
The bus interface unit provides the functions related to
instruction fetching and queuing, operand fetch and store,
and address relocation. This unit also provides the basic
bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance
through improved bus bandwidth utilization. Up to 4 bytes
of the instruction stream can be queued while waiting for
decoding and execution.
The instruction stream queuing mechanism allows the BIU
to keep the memory utilized very efficiently. Whenever there
is space for at least 1 byte in the queue, the BIU will attempt
a byte fetch memory cycle. This greatly reduces "dead
time" on the memory bus. The queue acts as a First-InFirst-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a
branch instruction, for example), the first byte into the queue
immediately becomes available to the EU.
The execution unit receives pre-fetched instructions from
the BIU queue and provides unrelocated operand
addresses to the BIU. Memory operands are passed

4-117

0

.r----:I.

6.tKe

-J"
I
+ OFt SET

SEGMENT
REGISTER FILE

l-_c,,;:S_-t~
ss
OS
ES

FFFFFH

CODE SEGMENT

XXXXOH

~

}

STACK SEGMENT

w,~{i ;:;: }

DATA SEGMENT

MSB

"'----l"'

OOOOOH

FIGURE 1. MEMORY ORGANIZATION

en
en

en W
0<->

::EO

<->ll:
o
a:
<->

:E

80C88

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
TABLE A.
SEGMENT REGISTER
USED

MEMORY
REFERENCE NEED

SEGMENT
SELECTION RULE

Instructions

CODE (CS)

Automatic with aU instruction prefetch.

Stack

STACK(SS)

All stack pushes and pops. Memory references relative to BP
base register except data references.

Local Data

DATA (DS)

Data references when: relative to slack, destination of string
operation, or expliciHy overridden.

External Data
(Global)

EXTRA (ES)

Destination of string operations: Explicitly selected using a
segment override.

is transferred to the interrupt routine. The pointer elements
are assumed to have been stored at their respective places
in reserved memory prior to the occurrence of interrupts.
Minimum and Maximum Modes
The requirements for supporting minimum and maximum
80C88 systems are sufficiently different that they cannot be
done efficiently with 40 uniquely defined pins. Consequently, the 80C88 is equipped with a strap pin (MN/MX) which
defines the system configu ration. The definition of a certain
subset of the pins changes, dependent on the condition of
the strap pin. When the MN/MX pin is strapped to GND, the
80Cee defines pins 24 through 31 and 34 in maximum
mode. When the MN/MX pin is strapped to VCC, the 80Cee
generates bus control signals itself on pins 24 through 31
and 34.

INTERRUPT

POINTERS
(2241

INTERRUPT
.ESERVE'
I

POINTERS

1271

DEDICATED
INTERRUPT
POINTERS

15'

mH -

Tr;::E~~:~~1I

Dl01t -

TY~!:::~:~ER

-

DOCH -1'BV~:~:: ~:~:~~TION
DOIH -

!~~~~=~~~~i~

11II4H -

T~~:~L'E~~!:R

-

DDDH -

TD~~~~:~~~~ERR

-

r--

l&IITS

The minimum mode 80C88 can be used with either a multiplexed or demultiplexed bus. This architecture provides the
80Ce8 processing power in a highly integrated form.

--1

FIGURE 2. RESERVED MEMORY LOCATIONS

The BIU will automatically execute two fetch or write cycles
for 16 bit operands.
Certain locations in memory are reserved for specific CPU
operations. (See Figure 2). Locations from addresses
FFFFOH through FFFFFH are reserved for operations
including a Jump to the Initial system initialization routine.
Following RESET, the CPU will always begin execution at
location FFFFOH where the Jump must be located. Locations OOOOOH through 003FFH are reserved for Interrupt
operations. Each of the 256 possible interrupt service
routines is accessed through its own pair of 16 bit pointers
- segment address pointer and offset address poInter. The
first poInter, used as the offset address, Is loaded into the IP,
and the second pointer, which desIgnates the base
address, is loaded Into the CS. At this point program control

The demultiplexed mode requires one latch (for 64K
addressability) or two latches (for a full megabyte of
addressing). An 82C86 or 82C87 transceiver can also be
used H data bus buffering is required. (See Figure 3). The
80C88 provides DEN and DTiR to control the transceiver,
and ALE to latch the addresses. This configuration of the
minimum mode provides the standard demultiplexed bus
structure with heavy bus buffering and relaxed bus timing
requirements.
The maxImum mode employs the 82C88 bus controller
(See Figure 4). The 82C88 decodes status lines SO, S1 and
S2, and provides the system with all bus control sIgnals.
MovIng the bus control to the 82C88 provides better source
and sink current capability to the control lines, and frees the
80C88 pIns for extended large system features. Hardware
lock, queue status, and two· request/grant interfaces
are provided by the 80C88 in maximum mode. These
features allow coprocessors in local bus and remote bus
configurations.

4-118

80C88

DESIGN INFORMATION

(Continued)

The information contained In this section has been developed through characterization by Harris Semiconductor and is for
use as application and design Information only. No guarantee is implied.

1ru'l
o

82C84A/8S

ill

r

RDY

G NO

f-o
f-o

ClK MNI"IIll f--- Vee
READY 101
RESET RD

t--

CLOCK
GENERATOR

\Vii

,

BOC8S INTA

CPU
GND

~

GND

Vcc~

Vee

r---,

OriA I - - DEN

ALE

t-GND

--.

iiE

ADo·AD,
A.-A I9 f-rADI~

~

('.20R3)

le:

ADDRESS

S2eD2

LATCH

INTR

C1 = C2 = 0.',..

I
I
I

STO

6E
T

DATA

B2eB6

TRANSCEIVER

F

n, IIJ n
I
L

EN
~

82C59A
V INTERRUPT
CONTROL
INT

~

HM-65162
CMOS RAM

HM-6616

JIT

OEnCS

CMOS PROM

RDW:j

82CXX

PERIPHERALS

~IR0.7·

FIGURE 3. DEMULTIPLEXED BUS CONFIGURATION

r--O::M:::NI-M.!t"L..-GND
ClK
If,"1-------I.. s.

82C84A/85 •

f+ill

.... READY

57

RESET

S2

-

GND
CPU
GND

--=C2 ;;;;;.

GND
AD.·AD,
Vee A.-A ul

":"'C1

Vee

DTill
ALE

aDe88

=.-----..-2__ .....
C1 = C2 = D.','"

iNTA

r---:-J

20

~

AMWC N.C.
I------.....------I-+----~e_---_-iOWc I-----.....-+------I-+----~e_---+_._AiiiWc r-- N.C.

5;: B2eBS IORC

r - - DEN

I-..;R.;;D;.;Y_...

£¥

ClK MRDC
MWTC I------------~H----~e_------

S,

I

STB

INT

GND-

---+

V'-=-d;f.y;-,II

~ODRrIDATA .

I

DE

t-~.....-~~--"A"'D~D,RE~S"S'--~-~ r--~-+---~~-

B2e82

('~:~RH3) ~

p.~

A
DATA

B2eB6

L...J., TRANSCEIVER

~

L~P=====~~~
V

82CS9A
'~bE,."r~'!,';.T

I:-

L-_--JI¢==

IR0.7

FIGURE 4. FULLY BUFFERED SYSTEM USING BUS CONTROLLER

4-119

80C88

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Bus Operation
The 80C88 address/data bus 15 broken into three parts: the
lower eight address/data bits (ADO-AD7), the middle eight
address bits (A8-A 15), and the upper four address bits
(A 16-A19). The address/data bits and the highest four
adddress bits are time multiplexed. This technique provides
the most efficient use of pins on the processor, permitting
the use of a standard 40 lead package. The middle eight
address bits are not multiplexed, i.e;, they remain valid
throughout each bus cycle. In addition, the bus can be
demultiplexed at the processor with a single address latch if
a standard, non multiplexed bus Is desired for the system.

Each processor bus cycle consists of at least four CLK
cycles. These are referred to as T1, T2, T3 and T4. (See
Figure 5). The address is emitted from the processor during
T1 and data transfer occurs on the bus during T3 and T4. T2
15 used primarily for changing the direction of the bus
during read operations. In the event that a "Not Ready"
indication is given by the addressed device, "wait" states
(Tw) are inserted between T3 and T4. Each inserted "wait"
state is of the same duration as a CLK cycle. Periods can
occur between 80C88 driven bus cycles. These are referred
to as "idle" states (Ti), or inactive CLK cycles. The processor uses these cycles for Internal housekeeping.

---:----<.+·1.0----,---(4 + NwAn) = TC'f---:----+J.!
T,

"

I

T,

I

T,

I TWA" I

T,

T,

elK

GOES INACTIVE IN THE STATE

JUSTPRIO~

.

OLE

\ - -_~_- - L.J. , response to any Interrupt (INTR, NMI, software interrupt, or
, single step). The FLAGS register, which Is automatically
program location.
pushed onto the stack, reflects the state of the processor
Non-maskable Interrupt (NMI)
prior to the interrupt. The enable bit will be zero until the old
The processor provides a single non-maskable Interrupt FLAGS register is restored, unless specifically set by an
(NMI) pin which has higher priority than the maskable Inter- Instruction.
rupt request (INTR) pin. A typical use would be to activate a
power failure routine. The NMI is edge-triggered on a lOW During'the'response sequence (see Figure 7), the procesto HIGH transition. The activation of this pin causes a type 2 sor executes two successive (back-to-back) interrupt
acknowledge cycles. The SOCSS emits the lOCK signal
interrupt.
(maximum'mode only) from T2 of the first bus cycle until T2
NMI is required. to have:a duration in the HIGH state'of , of the second. A local bus "hold" request will not be
greater than two ,clock cycles, but is not required,to ,be honored until the end of the second bus cycle. In the
synchronized to the clock. Any high going transition of NMI second bus cycle, a byte Is fetched from the external interis latched on-chip and will be serviced at the end of the rupt system (e.g., S2C59A PIC) which identifies the source
current instruction or between whole moves (2 bytes in the (type) of the interrupt. This byte is multiplied by four and
case of word moves) ofoa block, type instruction. Worst case used as a pointer into the interrupt vector lookup table.

I
ALE

T1

T2

J\~

__~n,--___
T3

T4

I

T1

I

T2

I

T3

\'--_ _ _-----J/
ADO-AD7

FIGURE 7. INTERRUPT ACKNOWLEDGE SEQUENCE

4-122

80C88

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

An INTR signal left HIGH will be continually responded to
within the limitations of the enable bit and sample period.
INTR may be removed anytime after the falling edge of the
first INTA signal. The interrupt return instruction includes a
flags pop which returns the status of the original interrupt
enable bit when it restores the flags.
Halt
When a software HALT instruction is executed, the processor indicates that it is entering the HALT state in one of two
ways, depending upon which mode is strapped. In minimum mode, the processor issues ALE, delayed by one
clock cycle, to allow the system to latch the halt status. Halt
status Is available on 10/M, DT/R, and SSO. In maximum
mode, the processor issues appropriate HALT status on S2,
S1 and SO, and the 82C88 bus controller issues one ALE.
The 80C88 will not leave the HALT state when a local bus
hold is entered while in HALT. In this case, the processor
reissues the HALT indicator at the end of the local bus hold.
An interrupt request or RESET will force the 80C88 out of
the HALT state.
Read/Modify/Write (Semaphore) Operations Via LOCK
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the
execution of an instruction. This allows the processor to
perform read/modify/write operations on memory (via the
"exchange register with memory" instruction), without
another system bus master receiving intervening memory
cycles. This Is useful in multiprocessor system configurations to accomplish "test and set lock" operations. The
LOCK signal is activated (LOW) in the clock cycle following
decoding of the LOCK prefix instruction. It is deactivated at
the end of the last bus cycle of the instruction following the
LOCK prefix. While LOCK is active, a request on a RQ/GT
pin will be recorded, and then honored at the end of the
LOCK.

System Timing - Minimum System
The read cycle begins in T1 with the assertion of the
address latch enable (ALE) signal (See Figure 5). The trailing (low going) edge of this signal is used to latch the
address information, which is valid on the address data bus
(ADO-AD7) at this time, into the 82C82/82C83 latch.
Address lines A8 through A15 do not need to be latched
because they remain valid throughout the bus cycle. From
T1 to T4 the 10/M signal Indicates a memory or I/O
operation. At T2 the address is removed from the address
data bus and the bus is held at the last valid logic state by.
internal bus-hold devices. The read control signal is also
asserted at T2. The read (RD). signal causes the addressed
device to enable its data bus drivers to the local bus. Some
time later, valid data will be available on the bus and the
addressed device will drive the READY line HIGH. When the
processor returns the read signal to a HIGH level, the
addressed device will again three-state its bus drivers. If a
transceiver (82C86/82C87) is required to buffer the local
bus, signals DTiFi and DEN are provided by the 80C88.
A write cycle also begins with the assertion of ALE and the
emission of the address. The 10/M signal is again asserted
to indicate a memory or I/O write operation. In T2, immediately following the address emission, the processor emits
the data to be written into the addressed location. This data
remains valid until at least the middle of T4. During T2, T3,
and Tw, the processor asserts the write control signal. The
write (WR) signal becomes active at the beginning of T2, as
opposed to the read, which is delayed somewhat into T2 to
provide time for output drivers to become inactive.

The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge
(INTA) signal is asserted in place of the read (RD) signal and
the address bus is held at the last valid logic state by internal bus-hold devices (see Figure 6). In the second of two
External Synchronization Via TEST
successive INTA cycles, a byte of information is read' from
As an alternative to interrupts, the 80C88 provides a single the data bus, as supplied by the interrupt system logic (i.e.,
software-testable input pin (TEST). This input is utilized by 82C59A priority interrupt controller). This byte identifies the
executing a WAIT instruction. The single WAIT instruction is source (type) of the interrupt It is multiplied by four and
repeatedly executed until the TEST input goes active· used as a pointer into the interrupt vector lookup table, as
(LOW). The execution of WAIT does not consume bus described earlier.
cycles once the queue is full.
Bus Timing - Medium Complexity Systems
If a local bus request occurs during WAIT execution, the
For
medium complexity systems, the MN/MX pin is
80C88 three-states all output drivers while Inputs and I/O
pins are held at valid logic levels by internal bus-hold connected to GND and the 82C88 bus controller is added
circuits. If interrupts are enabled, the 80C88 will recognize to the system, as well as an 82C82/82Ca3 latch for latching
interrupts and process them when it regains control of the the system address, and an 82C86/82C87 transceiver to
allow for bus loading greater than the aocaa is capable of
bus.
handling (see Figure a). Signals ALE, DEN, and DTiFi are
Basic System Timing
generated by the 82Caa instead of the processor in this
In minimum mode, the MN/MX pin is strapped to VCC and configuration, although their timing remains relatively the
the processor emits bus control signals (RD, WR, 10/M, same. The aocaa status outputs (S2, S1 and SO) provide
etc.) directly. In maximum mode, the MN/MX pin is strapped type of cycle information and become a2Caa inputs. This
to GND and the processor emits coded status information bus cycle Information specifies read (code, data or I/O),
. which the 82C88 bus controller uses to generate write (data or I/O), interrupt acknowledge, or software halt.·
MULTIBUS· compatible bus control signals.
The a2Ca8 thus issues control signals specifying memory

4-123

80C88

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed throuiJh characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

read or write, 1/0 read or write, or interrupt acknowledge.
The 82C88 provides two types of write strobes, normal and
advanced, to be applied as required. The normal write
strobes have data valid at the leading edge of write. The
advanced write strobes 'have the same timing as read
strobes, and hence, data is not valid at the leading edge of
write. The 82C86/82C87 tranceiver receives' the usual T
and OE Inputs from the 82(:88 DT/A and DEN.outputs.

80C88 handles the external bus the same way the 80C86
does with the distinction of handling only 8 bits at a time.
Sixteen-bit operands are fetched or written in two consecutive bus cycles. Botti processors will appear Identical to the
software engineer, with the exception of execution time. The
Internal register structure is identical and all instructions
have the same end result. Internally, there are three differences between the 80C88 and the 80C86. All changes are
related to the 8 bit bus interface.

The pointer into the Interrupt vector table, which is passed
during the second INTA cycle, can derive from an 82C59A
located on either the local bus or the system bus. If the
master 82C59A priority interrupt controller Is pOSitioned on
the . local bus, the 82C86/82C87 transceiver must be
_disabled when reading from the master 82C59A during the
interrupt acknowledge sequence and software "poll".

• The queue length -is 4 bytes in the 80C88, whereas the
80C86 queue contains 6 bytes, or three words. The
queue was shortened to prevent overuse of the bus by
the BIU when prefetching instructions. This was required
.because of the. additional time ·necesssary to fetch
Instructions 8 bits at a time.
• To further optimize the queue, the prefetching algorithm
was changed. The 80C88 BIU will fetch a new Instruction to load Into the queue each time there is a 1 byte
space available in the queue. The 80C86 waits until a 2
byte space is available.

The SOCSS Compared To The SOCS6
The 80C8S CPU Is an 8 bit processor designed around the
8086 internal structure. Most internal functions of the
80CSS are Identical to the equivalent SOCS6 functions. The

~ ~ 0~ ~
T.

eLK

~

x

051.050

X-

X

52,51. so

X

"~:

-

X

"-53

X

A'9-Al&

r-

r--\

ALE

12a.

'\

/////

A19 56· A16 53

{

X

X
:

x

1OCI8{:.~

QATAOUT

X

"'7-""

">

X

DEN

,
1<:

DA.TAIN

>

:::.:c:
~

A'S·AI

"D

12CII{~

----'\.

./

.,

'\
'\

/

'"

FIGURE 8. MEDIUM COMPLEXITY SYSTEM TIMING

4-124

80C88

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
• The internal execution time of the instruction set is affected by the S bit interface. All 16 bit fetches and writes
from/to memory take an additional four clock cycles. The
GPU is also limited by the speed of instruction fetches.
This latter problem only occurs when a series of simple
operations occur. When the more sophisticated instructions of the SOGSS are being used, the queue has time to
fill and the execution proceeds as fast as the execution
unit will allow.
The SOGSS and SOGS6 are completely software compatible
by virtue of their identical execution units. Software that is
system dependent may not be completely transferable, but
software that is not system dependent will operate equally
as well on an SOGSS or an SOGS6.
The hardware interface of the SOGSS contains the major
differences between the two GPUs. The pin assignments
are nearly identical, however, with the following functional
changes:

• AS-A15: These pins are only address outputs on the
80G8S. These address lines are latched internally and
remain valid throughout a bus cycle in a manner similar
to the SOS5 upper address lines.
• BHE has no meaning on the SOGSS and has been eliminated.
• SSO provides the SO status information in the minimum
mode. This output occurs on pin 34 in minimum mode
only. DTiFi', IOiM and SSO provide the complete bus status in minimum mode.
• loiriif has been inverted to be compatible with the 80S5
bus structure.
• ALE is delayed by one clock cycle in the minimum mode
when entering HALT, to allow the status to be latched
with ALE.

Ie
'"
o
'"
",,,,
'"
0""

:;;0
...,g:

o

Ie
...,

55

4-125

80C88

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and Is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY

Mnemonic and
Deecrlptlon
DATA TRANSFER

I

Instruction Code

MOV = Move:

78543210

78543210

Register/Memory to/from Register

100010dw

mod reg rim

Immediate to Register/Memory

1100011w
1011wreg

Immediate to Register

78543210

711543210

modOOOr/m

data

dataHwl

data

dataHwl

Memory to Accumulator

1010000w

add-low

addr-hlgh

Accumulator to Memory

1010001w

addr-Iow

addr-high

Register/Memory to Segment Register"

10001110

mod 0 reg r/m

Segment Register to Register/Memory

10001100

mod 0 reg r/m

11111111

modl10r/m

PUSH

= PUlh:

Register/Memory
Register

01010reg

Segment Register

OOOreg 11 0

pop = Pop:
Register/Memory

Segment Register
XCHG

=

10001111

modOOOr/m

01011 reg

Register

OOOreg 111

Exchange:

Register/Memory with Register
Register with Accumulator

1000011w

mod reg rim

10010reg

IN = Input trom:
Fixed Port

1110010w

Variable Port

1110110w

port

OUT = Output to:
Fixed Port

1110011 w

Variable Port

1110111w

XLAT = Translate Byte to AL

11010111

LEA

= Load EA to Register
= Load Pointer to OS

port

10001101

mod reg r/m

11000101

mod reg r/m

LES = Load Pointer to ES

11000100

mod reg rim

= Load AH with Flags
SAHF = Store AH Into Aags

10011111

PUSHF = Push Flags

10011100

POPF = Pop Flegs

10011101

LOS

LAHF

10011110

4-126

80C88

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design Information only. No guarantee is implied.
INSTRUCTION SET SUMMARY (Continued)
Mnemonic and
De.crlptlon
ARITHf!'IETIC

I

Instrucllon Code
76543210

76543210

78543210

78543210

ADD = Add:
Reg.lMemary with Register to Either

OOOOOOdw

mod reg rim

Immediate to Register/Memory

100000sw

madOOO rim

Immediate to Accumulator

0000010w

date

.~

ADC

date
dateifw

date Ifs:w

=

= 01

I

Add with Carry:

Reg.lMemory with Register to Either

000100dw

mod reg rim

Immediate to Reglster/Memory

100000sw

modO 1 0 rim

date

Immediate to Accumulator

0OO1010w

date

dateifw=1

l111111w

modOOOr/m

date ifs:w = 01

INC = Increment:
Register/Memory
Register
AAA = ASCII Adjust tor Add

= Decimal Adjust for Add

DAA

01000reg
00110111
00100111

SUB = Subtract:
Reg.lMemory and Register to Either

001010dw

mod reg rim

Immediale trom RegisterIMemory

100000sw

mod 10 I rim

date

date

dateitw = I

Immediate from Accumulator
SBB

~10110W

date Hs:w = 01

= Subtract with Borrow

Reg.lMemary and Register to Either

OOOllOdw

mod reg rim

Immediate from Register/Memory

100000sw

modOl1 rim

date

Immediate from Accumulator

0001110w

date

dateifw=1

DEC = Decrament:
Register/Memory

1IIIIIIw

modOO I rim

Register

01001 reg

NEG = Change Sign

1111011 w

data if s:w

= 01

modO 11 rim

CMP = Compare:
Register/Memory and Register

OOlllOdw

mod reg rim

Immediate with RegisterlMemory

100000sw

mod 111 rim

data

Immediate with Accumulator

0011110w

date

dataifw = I

AAS = ASCII Adjust for Subtract

00111111

= Decimal Adjust for Subtract
MUL = Multiply (Unsigned)
IMUL = Integer Multiply (Signed)

00101111

AAM = ASCII Adjust for Multiply

11010100

00001010

= Divide (Unsigned)

1111011w

mod II

IDlY = Integer Divide (Signed)

1111011w

mod 111 rim

AAD = ASCII Adjust for Divide

11010101

00001010

= Convert Byte to Word
CWD = Convert Word to Double Word

10011000

DAS

DIY

CBW

111101lw

mod 1 OOr/m

1111011w

mod I 0 I rim

1001100 I

4-127

orim

data it s:w = 01

80C88

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY (Continued)
Mnemonic and
Deacrlptlon
LOGIC

I

Instruction Code
76543210

76543210

NOT = Invert

111101lw

modO I

SHL/SAL = Shift LogicallArithmetic Left

110100vw

mod I OOr/m

110100vw

mod I 0 I rIm

SAR = ShiH Arithmetic Right

110100vw

mod 111

ROL = Rotate LeH

110100vw

modOOOr/m

SHR

'= ShiH Logical Right

76543210

76543210

dataHw = 1

orIm

rIm
rIm

ROR = Rotate Right

110100vw

mod 00 I

RCL = Rotate Through Carry Flag Left

110100vw

modO 10 rIm

RCR = Rotate Through Carry Right

110100vw

modOll rIm

AND = And:
Reg.lMemory and Register to Either

001000dw

mod reg rIm

Immediate to Register/Memory

1000000w

mod 1 00 rIm

data

Immediate to Accumulator

0010010w

data

dataifw = 1

TEST = And Function to Flags, No Result:
RegisterlMemory and Register

. - 1000010w
-----..,-- reg
---,
mod
rIm

Immediate Data end Register/Memory

1111011w

modOOOr/m

data

Immediate Data and Accumulator

1010100w

data

dataHw=1

dataHw = 1

OR = Or:
Reg.lMemory and Register to Either

000010dw

mod reg rIm

Immediate to Register IMemory

1000000w

modOO 1 rIm

data

Immediate to Accumulator

0000110",

data

dataHw=1

dataifw=1

XOR = Exclusive or:
Reg.lMemory and Register to Either

001100dw

mod reg rIm

Immediate to Register/Memory

1000000w

modllOr/m

data

Immediate to Accumulator

0011010w

data

dataHw=1

disp-high

STRING MANIPULATION
REP = Repeat

111100h

MOYS = Move Byte/Word

1010010w

CMPS = Compare Byte/Word

1010011 w

SCAS = Scan BytelWord

1010111 w

= Load Byte/Wd to ALIAX

1010110w

STOS = Stor Byte/Wd from ALI A

1010101w

LODS

CONTROL TRANSFER
CALL

= call:

Direct Within Segment

11101000

disp-Iow

Indirect Within Segment

11111111

modOl0r/m

Direct Intersegment

100 II 010

offset-low

offset-high

seg-Iow

seg-hlgh

Indirect Intersegment

11111111

modOll rIm

4-128

datalfw = I

BoeBB

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY (Continued)
Mnemonic and
Descrlptlon

I

Instruction Code

JMP = Unconditional Jump:

76543210

76543210

76543210

Direct Within Segment

11101001

disp.low

disp·high

Direct Within Segment-Short

11101011

disp

Indirect Within Segment

11111111

mod 1 OOr/m

Direct Intersegment

11101010

offset-tow

offset-high

seg-Iow

sag-high

Indirect Intersegment

11111111

mod 101 rIm

RET = Return from CALL:
Within Segment

11000011

Within Seg Adding Immed to SP

11000010

Intersegment

11001011

data-low

data-high

data-high

Intersegment Adding Immediate to SP

11001010

data-low

JE/JZ = Jump on Equal/Zero

01110100

disp

JLlJNGE = Jump on Less/Not Greater
or Equal
JLE/JNG = Jump on Less or Equal/
Not Greater
JB/JNAE = Jump on Below/Not Above
or Equal
JBE/JNA = Jump on Below or Equal/
Not Above
JP/JPE = Jump on Parity/Parity Even

01111100

disp

01111110

disp

01110010

disp

01110110

disp

01111010

disp

JO = Jump on Overflow

01110000

disp

JS = Jump on Sign

01111000

disp

JNE/JNZ = Jump on Not Equal/Not Zero.

01110101

disp

JNLlJGE = Jump on Not Less/Greater
or Equal
JNLE/JG = Jump on Not Less or Equal/
Greater.
JNB/JAE = Jump on Not Below/ Above
or Equal
JNBE/JA = Jump on Not Below or
Equal/Above
JNP/JPO = Jump on Not Par/Par Odd

01111101

disp

01111111

disp

01110011

dlsp

01110111

disp

01111011

disp

JNO = Jump on Not Overflow

01110001

disp

JNS = Jump on Not Sign

01111001

dlsp

LOOP = Loop CX Times

11100010

disp

LOOPZlLOOPE = Loop While Zero/Equal

11100001

disp

LOOPNZ/LOOPNE = Loop While Not
Zero/Equat
JCXZ = Jump on ex Zero

11100000

disp

l1tOOOll

disp

type

tNT = Interrupt
Type Specified

11001101

Type 3

11001100

INTO = Interrupt on Overflow

11001110

IRET = Interrupt Return

11001111

4-129

I

80C88

DESIGN INFORMATION

(Continued)

The Information contained In this section has been developed through characterization by Harris Semiconductor and Is for
use as application and design information only. No guarantee is implied.
INSTRUCTION SET SUMMARY (Conllnued)

Mnemonic and
De.crlpllon

I

Instruction Code

78543210

7854.3210

PROCESSOR CONTROL
CLC = Clear Carry
CMC
STC

= Complement Carry
= Set Carry

CLD = Clear Direction

11111000
11110101

11111001
11111100

STD = Set Direction

11111101

CLI = Clear Interrupt

11111010

sn =
HLT

Set Interrupt

= Halt

WAIT = Walt

ESC

= Escape (to External Device)

LOCK =

Bus Lock Prefix

11111011
11110100
10011011
11011xxx

modxxxr/m

11110000

NOTES:
AL = B-bit accumulator
AX = 16-bit accumulator
. CX = Count register
DS = Data segment
ES = Extra segment
Above/below refers to unsigned value.
Greater = more positive;
Less = less· positive (more negative) signed values
if d = 1 then "to" reg; if d = 0 then "from" reg
if w = 1 then. word instruction; if w = 0 then byte Instruction
·if mod = 11 then rIm is treated as a REG field
if mod = 00 then DISP = 0·, disp-Iow and disp-high are
absent
if mod = 01 then DISP = disp-Iow sign-extended to
16 bits, disp-high is absent
if mod = 10 then DISP = disp-high: disp-Iow
if rIm = 000 then EA = (BX) + (SI) + DISP
if rIm = 001 then EA = (BX) + (DI) + DISP
if rIm = 010 then EA = (BP) + (SI) + DlSP
if rIm = 011 then EA = (BP) + (DI) + DISP
if rIm = 100 then EA = (SI) + DISP
if rIm = 101 then EA = (DI) + DISP
if rIm = 110 then EA = (BP) + DISp·
if rIm = 111 then EA = (BX) + DISP
DISP follows 2nd byte of instruction (before data if required)
·except·if mod = 00 and rIm = 110 then EA = disphigh: disp-Iow.
• ·MOV CS, REG/MEMORY not allowed.

if s:w = 01 then 16 bits of immediate data form the operand.
if s:w = 11 then an immediate data byte is sign extended
to form the 16-bit operand.
if v = o· then "count" = 1; if v = 1 then "count" in (CL)
x = don't care
z is used for :string primitives for comparison with ZF FLAG.
SEGMENT OVERRIDE PREFIX

I

001reg110

I

. REG is assigned according to the following table:

16-Blt (w

= 1)

8-Blt(w

000 AX
001 CX
010 OX
011 BX
100 5P
101 BP
110 51
111 01

000
001
010
011
100
101
110
111

= 0)

AL
CL
OL
BL
AH
CH
OH
BH

Segment

00 E5
01
10
11

C5
55
OS

Instructions which. reference the flag register file as a 16-blt
object use the symbol FLAGS to represent the file:
FLAGS =
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
Mnemonics

4-130

@

Intel, 1976

Harris Semiconductor

== -=.
== ==
No. 111

------

Harris Digital

April1988

HARRIS 80C286 PERFORMANCE ADVANTAGES
OVER THE 80386
Author: Ted Dimbero
The Harris 800286, operating at the same frequency as the
80386, has performance advantages over the 80386 when
executing 16-bit industry standard 80086 or 800286
code. This is evident in the following areas:
(1)

InpuVOutput Handling

(2)

Interrupt Handling

(3)

Oontrol Transfer (Loop, Jump, Oall)

Architecture Background
The 800286 Harris' newest static OMOS microprocessor
combines low operating and standby power with high
performance. The Harris 800286 is available in speeds of
12.5MHz, 16MHz, and 20M Hz.

The 800286 evolved from the industry standard 80086
microprocessor. The 800286 has vast architectural
enhancements over Its predecessor that allow the 800286
(4) 286 Protected Mode Systems
to execute the same code with a significant performance
(5) Multi-Tasking and Task Switching Operations.
increase. Disregarding the clock speed increase, when
upgrading from an 80086 to an 800286, the 800286 can
This advantage is due to the 800286 requirement of fewer execute the same code with an increase in throughput of up
clock cycles to execute the same instructions. In addition to to 4 times that of the 80086. This increase is solely due to
. these areas, the 800286 executes many other instructions, the architectural enhancements.
In·the same number of clock cycles as the 80386.
It is a common belief that replacing an 800286 with the
This results in an 800286 performance advantage in areas
32-bit 80386 microprocessor will yield similar performincluding:
.' ance increases. This is not the case. The new architecture
gives the·80386 .32-bit capability and increased protection
• Multi-Tasking Systems.
features, but it does not significantly increase the through• Oontrol Applications - utilizing interrupt and I/O
put of 16-bit 8086 or 80286 code. In most cases, when
instructions.
. executing industry standard 8086 or 80286 code,
• Structured Software - utilizing many Oontrol transfer replacing the 800286 with an 80386 does not result in a
instructions.
.
significant performance increase. In some cases, such a
replacement will actually cause a performance degradation.
• Operating Systems that rely on interrupts to perform
functions.
Figure 1 illustrates a comparison of the number of clock
• Upgrading 16-bit 80C86 applications for Increased cycles needed to execute several instructions available on
all three microprocessors (80086, 800286, and 80386).
performance.
This illustrates the dramatic effect of 800286 architectural
The 800286 can be effectively used as a fast 80086. How- enhancements on performance when compared to the
ever, the 80386 is [lot a fast 800286. This study shows that . 80086 and the lack of similar performance improvement
software written for the 80086/800286 can execute more when executing 8086/80286 code on the 80386.
efficiently on the 800286 than on the .80386. There is no
significant performance advantage to be gained by simply With an 80086 to 800286 upgrade, system designers
moving a system design from an 800286 to:an 80386 at can execute existing 8086 code on the 800286 and
either 16MHz or 20M Hz. The 800286 is the processor best take advantage of an immediate performance upgrade.
suited for executing 16-bit 80086/800286 code, which This same benefit is not realized when switching from
represents the world's largest base of microprocessor an 800286 to an 80386. This comparison illustrates
software.
that changing from an 800286 to an 80386 does

4-131

Application Note 111

EiiJ MUL [BX]
II XOR AX, [BPI [511
II OUT PORT. AX

o NOT

o

[BX+ 101

CALL near

IS LOOP
!Sa INT 3
IlllIAAD
III ADD mem [BX] [011. AX
TOTAL (119)

(19)
(7)
(10) .

~~~~~~~I~
(33)
(19)

........................'-!:!:~...........................
FIGURE 1.

(7)

ARCHITECTURAL COMPARISON

not yield increased throughput when executing the same
industry standard 80C86/80C286 code (the world's largest
base of microprocessor software).

Instruction Comparison
The Appendix in this document illustrates a direct comparison of the number of clock cycles needed to execute the
same instructions on the 80C286 and the 80386. The table
includes examples of instruction timing for all instructions
available on both processors. Several addressing modes of
each instruction type .are included.

This is vasUy different than the previous 86-286 upgrade.
With that upgrade, the 80C286 exhibits equal or better performance than the 80C86 with 100% of the instructions.
This clearly indicates that the 80C286 is the processor best
suited for executing industry standard 8086 family code.
The following discussion groups each of the instructions
into one of several categories to analyze which applications
will benefit from utilizing the 80C286. The categories used
are:
• Jumps, Calls, Returns and Loops (Real Mode).
• I/O Instructions.

Ofthe 190 instruction examples analyzed, 740fthe instructions execute faster on the 80C286 than on the 80386; 66
of the instructions analyzed execute in the same number of
clock cycles on both processors. This leaves only 50 instructions with improved performance on the 80386 (See
Figure 2). Over 70% of the instructions analyzed execute as
fast or faster on the 80C286 than on the 80386.

• Logic, Arithmetic, Data Transfer, Shift and Rotate
Instructions.
• Interrupts.
• Miscellaneous Instructions.
• Protected Mode/Multi-Tasking Instructions.

Jumps, Calls and Loops

8OC2116
EQUAL TO

B0386

B0386
FASTER THAN

8OC2116

FIGURE 2. EXECUTION SPEED COMPARISON
(NUMBER OF INSTRUCTIONS)

In real mode, near calls, jumps, and conditional jumps
(transfers within the current code segment) all take the
same number of clock cycles to execute on the 80C286
and the 80386. Since the segment sizes are larger on the
80386, the near transfer instructions on the 80386 can
transfer a greater distance.
The far calls and jumps {transfers that switch to a new code
segment; i.e., a code segment context switch, are faster on
the 80C286: four clocks and one clock respectivley. The far
return instruction executes in three less clock cycles on the
80C286, and the near return takes one extra clock cycle.
The protected mode calls, jumps, and returns are all faster

4-132

Application Note 111
on the 80C286 and are discussed in the section on
Protected Mode.
The loop instruction is three clock cycles faster on the
80C286 than the 80386. Thus, the 80C286 would save 300
clock cycles over the 386 if a LOOP instruction were
executed 100 times.
-ADVANTAGEINSTRUCTION

80C286

Near JMP and CALL

NONE

80386

X

Far CALL, JMP and RET

X

LOOP

X

I/O Instructions
The 80C286 has a significant advantage with the I/O
instructions. The IN instruction is almost 2 1/2 times faster
on the 80C286; the 80386 takes 7 extra clock cycles to execute the same instruction. The OUT instruction is over 3
times faster on the 80C286; again the 80386 takes 7 extra
clock cycles to execute the same instruction. Executing the
I/O instructions on the 80386 is equivalent to executing on
the 80C286 with 7 wait states.
The string I/O instructions (INS and OUTS) are also significantly faster on the 80C286. The INS instruction is 10 clock
cycles faster on the 80C286, and the OUTS instruction is 9
clock cycles faster. This is particularly important if the string
operations are going to be used to input or output a large '
block of data using the REP prefix. Inputing 100 words of
data with the REP INS instruction is 208 clock cycles faster
on the 80C286. An even more significant difference can be
seen when outputing 100 words with the REP OUTS
instruction. In this case, the 80C286 is 800 clock cycles
faster than the 80386.

Most of the string manipulation instructions execute in the
same number of clock cycles on both processors. The
MOVS and STOS instructions are faster on the 80C286.
The divide instruction executes in the same number of clock
cycles on both processors. The number of clocks to
execute the multiply instruction on the 80386 is data
dependent; the number of clocks to execute the'same
instruction on the 80C286 is fixed. On average, the multiply
instruction is five clock cycles faster on the 80386, but
depending on the data, the 80386 could be as many as 4
clock cycles slower than the 80C286.
The rotate and shift instructions are faster on the 80386.
Unlike the 80C286, the 80386 rotate and shift instructions
do not depend on the number of bits to be shifted or rotated.
Thus, the 80386 has the advantage with multi-bit rotate and
shift instructions. The 80C286 does, however, execute
single bit rotate and shift instructions faster.
- ADVANTAGEINSTRUCTION

80C286

Most Logic and Arithmetic

NONE

'80386

X

Certain Operand
Combinations of Logic
and Arithmetic

X

Divide

X

Multiply

X

Single Bit Shift or Rotate

X

Multi-Bit Shift or Rotate

X

String Instructions

80C286

IN

X

OUT

X

INS

X

OUTS

X

NONE

Most forms of the logic, arithmetic, and data transfer
instructions execute in the same number of clock cycles on
both processors. Certain operand combinations of these
instructions (immediate to register for example) take one
extra clock cycle to execute on the 80C286.
In real mode, the segment register transfer instructions
execute as fast or faster on the 80C286 than they do on the
80386. For example, using the POP instruction to transfer
data into a segment register is 2 clock cycles faster on the
80C286.

-ADVANTAGEINSTRUCTION

80C286

INTn

X

INTO

X

BOUND (If Interrupt)

X

Break Point Interrupt

X

4-133

o

:ii1

Interrupts are serviced more quickly on the 80C286. The
INT instnuction, in real mode, executes 14 cycles faster on
the 80C286 than it does on the 80386. The INTO, BOUND,
and other instructions that can cause an interrupt all benefit
from the faster interrupt handling features of the 80C286.
The return from interrupt instruction (IRET) is 7 clock cycles
faster on the 80C286. The PUSHA and POPA instructions,
frequently used by interrupt handling procedures, are both
faster on the 80C286. Protected Mode interrupt handling is
discussed in the Protected Mode section.

Logic, Arithmetic, Data Transfer, Shift
and Rotate Instructions

ug:
a:

Interrupt Instructions

80386

:;:0
u

X

-ADVANTAGEINSTRUCTION

a:
'"
o
'"
en '"
....
OU

NONE

80386

Application Note 7 7 7
Miscellaneous Instructions
The BCD instructions, HLT, and CBW execute from 1 to 5
clock cycles faster on the 80C286. The instructions to set
and clear individual flags and the CWO instruction all
execute in the same number of cycles on both processors.
The ENTER, LEAVE, and BOUND instructions are from 1 to
3 cycles faster on the 80386. The BOUND instruction is
only faster if an interrupt is not caused by the instruction.
-ADVANTAGEINSTRUCTION

80C286

BCD Instructions

NONE

Most of the 80286 protected mode access checking
instructions operate as fast or faster on the 80C286 than on
the 80386. The LAR instruction is one clock cycle faster on
the 80C286 and the LSL instruction is 5 clock cycles faster.
The VERW instruction executes in the same speed on both
processors and the VERR is 5 cycles faster on the 80386.
The ARPL instruction used in protected mode procedures
for pointer validation is 10 clock cycles faster on the
80C286.

80386

-ADVANTAGE-

X

Data Conversion
(CBW,CWD)

INSTRUCTION

X

Flag Settling and Clearing

X

BOUND (If No Interrupt)

X

80C286

Task Switching

X

Segment Register Loading

X

Inter-Segment Transfer

X

Protected Mode/Multi- Tasking

System Register Instructions

When executing 80286 protected mode code, the 80C286
significantly out-performs the 80386. Task switching operations execute 100 to 113 clock cycles faster on the
80C286. The instruction to return from a called task is 63
clock cycles faster on the 80C286. This results in a very
significant performance increase for systems utilizing the
multi-tasking features.

Inter-Segment Transfers

Inter-segment JMP, CALL and segment loading instructions also operate faster on the 80C286. The 80C286 saves
anywhere from 4 to 11 clock' cycles depending on the
particular inter-segment transfer instruction. In protected
mode, the inter-segment return is also faster on the
80C286. The 80C286 is 7 clock cycles faster when executing an inter-segment return to the same privilege level and
is 13 cycles faster on inter-segment reiurns to a different
privilege level.
The instructions to initialize and check the protected mode
registers execute as fast or faster on the 80C286. The IDTR
access instructions are an exception to this in that they take
one extra clock cycle to execute on the 80C286. The
instruction to switch the processor to protected mode
(LMSW) is 7 cycles faster on the 80C286.
80C286
CLOCK CYCLES

80386
CLOCK CYCLES

3
3

4
2
12

-

EXAMPLE 1
This interrupt routine outputs a character to a terminal via a
UART. The AL register must contain the character to be
output. The routine first checks the status of the UART to
determine if it is busy. If it is busy, the routine loops until the
UART is free; when the UART is free, the character is output.
Following is a listing of the code and the clock clycle analysis for the OUT_CHAR routine.
This sample procedure executes about 25% faster on the
80C286 than on the 386. The advantage is realized through
the 80C286's faster interrupt' handling and faster I/O
instructions.

OUT_CHARACTER PROC NEAR

5

22
37

INTx

23

-

73

104

18

24

X

Subroutine Analysis

5

4
10

3

X

This section lists several subroutines and then compares
the number of clock cycles each subroutine will take to execute on the 80C286 and on the 80386.

17

5
317

80386

X

Access Checking
Instructions

PUSHF
PUSH AX
IN AL, PORT_STATUS
CMPAL,BUSY
JE CIC.STATUS
POP AX
OUT OUT_PORT, AL
POPF
IRET

5
6
317
5

NONE

CIC.STATUS:

; save callers flags.
; save data to be output.
; Input UART status.
; Check If UART Busy
; If busy go check again.
; If not busy restore AX
; and output data
; Restore Flags
; Return.
; Instruction to initiate OUTCHAR
; Interrupt.

Total cycles if UART not busy.
Number of cycles added for each loop while UART is busy.
EXAMPLE 1
4-134

Application Note 111
EXAMPLE 2
The second example outputs an entire string of characters
using the previous interrupt routine (denoted by "INT x" in
the code below). The DS:SI registers point to the beginning
80C288
CLOCK CYCLES

80388
CLOCK CYCLES

17
5
3

18
5
2

317

317

73
7
19
15

104
7
24
18

13

-

79+91/char

-

OUT_STRING PROC FAR
NEXT:

DONE:

17

91+121/char

of the string to be output. The string is variable in length and
must be terminated with the "$'" character.

PUSHA
LODSB
CMPAL,"$"
JEdone
INTx
JMPnext
POPA
RET

; save caller's registers.
; Load first char to be output.
; Check to see if End of string.
; If end then goto DONE.
; If not end output character.
; Go get next char to output.
; Restore Registers when done.
; Far Relum.

CallOUT_STRING

; Far Call to initiate
; OUT_STRING procedure.

Total number of clocks to start and end routine.
+Number of additional clocks to output each character In the output string

To output a string of 20 characters, the 80C286 would take
1,899 clock cycles; using the same routine, the 80386
would take 2,511 cycles. Each time a string of 20 characters is output, the 80C286 will save 612 clock cycles; an

8OC286 performance increase of almost 25%. The advantage is realized through the 80C286's faster interrupt handling, faster I/O instructions, faster FAA transfer instructions
and faster register saving and restoring instructions.

EXAMPLE 3
This example adds all the values of a source array in
memory to the values of a destination array in memory. The
result is stored in the destination array. Both arrays are
assumed to be in the current data segment. The count

(number of words in the array), offset of source array, and
offset of destination array are all assumed to be placed on
the stack (in that order) by the calling program. The source
code for the procedure is listed below:

8OC288
CLOCK CYCLES

80388
CLOCK CYCLES

17
2
5

18
2
4

PUSHA
MOVBP,SP
MOV CX,lbp+22)

5

4

MOV SI,lbp+201

5

4

MOV DI,lbp+18)

2
5
7
3
8/4

2
5
7
2
11

19
11

24
10

5

3

5
2

PUSH count
PUSH offset S....ARRAY

3

2

PUSH offset D....ARRAY

7

CALLADD....ARRAY

84+(25*CX)

Total number of clocks to start and end routine.
+Number of additional clocks for each item in array to be added.

ADD....ARRAY PROC NEAR

CLD
LODSW
ADDIDII,AX
ADD 01,02
LOOP NEXT

NEXT:

POPA
RET6

; Save caller's registers.
; Point SP to current stack
; Load array size from stack
;intoCX.
; Load offset of source array
; from stack into SI.
; Load offset of destination
; array from stack Into 01.
; Clear Direction Flag.
; Load the source word into AX.
; Add source to destination.
; Point 01 to next data.
; Continue to ADD all elements
; in the two arrays.
; Restore Registers
; Near retum.

; Following is the code necessary to set up and call the above procedure.

-

7

84+(23*CX)-4

-

Both processors take the same number of clock cycles for
initialization before the call and closing up after the call (84).
The loop that does the adding is faster on the 80C286. To
add two 100 word arrays, the 80C286 would take 2,380

; Put count parameter on stack
; Put offset of source array
;onstack.
; Put offset of destination
; array on stack.
; Near Call to initiate
; ADD....ARRAY procedure.

clock cycles; the 80386 takes 2,584 (an additional 204
clocks) to execute the same routine.·ln this example, the
LOOP instruction gives the 80C286 the performance
advantage over the 80386.

4-135

Application Note 111
EXAMPLE 4
This procedure is an example of an operating system
procedure developed for a protected mode multi-privilege
level system. The procedure INIT_SEGMENT is passed a
segment selector on the stack and will load that entire
segment with zero's. The procedure is designed to execute
at privilege level zero with a call gate at privilege level 3; this
80C286
CLOCK CYCLES

80386
CLOCK CYCLES

allows procedures executing at any level to utilize the
INIT_SEGMENT procedure. INIT_SEGMENT provides
protection checks to ensure that the procedure passing the
parameter has valid access to the segment that it is trying to
initialize. This prevents a procedure at privilege level three.
from initializing a segment at privilege level zero.

INIT_SEGMENT PROC FAR WC=1

17

18

PUSHA

; save caller's registers.

3

2

PUSHES

; save ES register.

2

2

MOVBP,SP

; Point BP to top of stack.

5

4

MOV AX, [BP+22]

; Load AX with segment selector

5

4

MOV BX, [BP+20]

; Load BX with return CS to

10

20

ARPLAX,BX

; Adjust the Privilege level of

; passed as parameter on stack.
; determine caller's CPL.
; the segment selector according
; to the caller's CPL.
16

16

3/7

VERWAX

; Test for valid wrne access

3/7

JNEERROR

; If no valid access goto error.

17

18

MOVES,AX

; LOAD ES with segment to be

14

20

LSLCX,AX

; Load segment size Into CX.

2

2

XOROI,OI

; Load zero into 01.

2

2

XORAX,AX

; Load zero into AX.

2

2

CLO

; Clear decrement flag.

REPSTOSB

; Init entire segment to 00.

; initialized.

4+3*cx

5+5*cx

2

2

; Clear carry to indicate segment

CLC

; initialized with no errors.
20

21

POPES

; Restore ES register.

19

24

POPA

; Restore Register

55

68

RET2

; Ret FAR to different privilege

2

2

STC

; SET carry to indicate error.

7

1.

3

2

82

86

DONE:

ERROR:

JMPOONE
; Code to push selector on stack and initiate INIT SEGMENT via call gate.

-

-

253

283

283+(3*S)

321+(5*S)

PUSH

OAT~SELECTOR

CALL INIT_SEGMENT_GATE

; Place Selector on stack.
; Instruction to initiate
; INIT SEGMENT procedure.

Total clocks if ERROR because segment not accessible.
Total number of clocks if segment is initialized to zeros. "S" represents size of segment
in bytes.

This example shows that when executing instructions used
for privilege verification and privilege level transitions the
80C286 is faster than the 80386. Without taking the LODS
instruction into account, the 80C286 is 38 clock cycles

faster when execuiing the same procedure. With the LODS
instruction, and assuming a segment size of 100 bytes, the
80C286 would execute this routine 238 clock cycles faster
than the 80386.

4-136

Application Note 111
EXAMPLE 5

This Procedure is a task dispatcher that is invoked via an
interrupt to cause a task switch to occur. This procedure
utilizes a circular linked list of the tasks that need to be
executed. A pointer called "CURRENT_TASK" points to
the data structure for the current task being executed. The
data structure contains the TSS for the task it is describing
and a NEXT field that points to the data structure of the next
task in the list to be executed. When the Task Dispatcher is
invoked it switches the current pointer to the next task in the

80C286
CLOCK CYCLES

5

80386
CLOCK CYCLES

4

3

2

178

279

-

7

193

7

--

list and then invokes the new task by jumping to the TSS for
that task. The data structure for the linked list is illustrated
below.
The task dispatcher is actually a separate task that is
invoked via an interrupt that signals that a new task should
be initiated. Following is a listing for the simple task
dispatcher.

TASK.J)ISPATCH PROC FAR
START:

MOV BX, CURRENT TASK + 2

MOV CURRENT TASK, BX
JMP DWORD PTR [BX-2)
JMPSTART

; Load BX with contents of next
; field of current TASK. BX will
; contain the address of the data
; structure for next task to run.
; Update Current Task to point to
; new task to be executed.
; Start new task by jumping to TSS'
; for new task.
; JUMP to start for next time the
; TASK dispatcher is invoked.

292

The advantage of the 80C286 in this case is in the faster
task switch instruction. The task switch instruction is 101
clock cycles faster on the 80C286 than on the 80386. This

performance increase makes the 80C286 the clear choice
for muti-tasking applications.

4-137

Application Note 111
Appendix
This appendix contains a table directly comparing the number of clock cycles necessary to execute all the instructions
available on both the 80C286 and the 80386. The table
includes several addressing modes of each instruction:
The table has five columns. The first column list the instruction being compared. The second column lists the number
of clock cycles that the 80C286 needs to execute, that
instruction. The third column lists the number of clock
cycles needed by the 80386 to execute the same instruc-

80C286 INSTRUCTION

AAA
AAD
AAM
AAS
ADC reg, reg
ADCmem,reg
ADC reg, immed
ADC mem, immed
ADD reg, reg
ADD mem, reg
ADD reg, immed
ADD mem, immed
AND reg, reg
AND mem, reg
AND reg , immed
AND mem, immed
ARPL reg, reg
ARPL mem, reg
BOUND (no interrupt)
CALL immed (near)
CALL immed (far real mode)
CALL immed (far PVAM)
CALL gate (same privilege PVAM)
CALL gate (different privilege PVAM)
CALL TSS (Task Switch PVAM)
CALL tasLgate (Task Switch PVAM)
CBW
CLC
CLD
CLI
CLTS
CMC
CMPreg,.reg
CMPmem, reg
CMP reg, immed
CMP mem, immed
CMPS
CWO

tion. The fourth column divides the number of cycles
needed by the 80386 by the number of cycles needed by
the 80C286. If this figure is greater than one, (see fifth
column) then the 8OC286 i!l faster than the 80386. For
example, a 2.0 would indicate the 80C286 executes the
same instruction· twice as fast as·the 80386. A 1.0 indicates
that both processors execute the instruction in the same
number of cycles. A number less than one indicates the
80386 is faster than the 80C286.

80C286
FASTER

NUMBER

NUMBER

CLOCKS TO

CLOCKS TO

EXECUTE
ON80C286

EXECUTE

803861

ON 80386

80C286

3
14
16
3
2
7
3
7
2
7
3
7
2
7
3
7
10
11
13
7
13
26
41
82
177
182
2
2
2
3
2
2
2
6
3
6
8
2

4
19
17
4
2
7
2
7
2
7
2
7
2
7
2
7
20
21
10
7
17
34
52
86
278
287
3
2
2
3
5
2
2
5
2
5
10
2

1.33
1.36
1.06
1.33
1.00
1.00
0.67
1.00
1.00
1.00
0.67
1.00
1.00
1.00
0.67
1.00
2.00
1.91
0.77
1.00
1.31
1.31
1.27
1.05
1.57
1.58
1.50
1.00
1.00
1.00
2.50
1.00
1.00
0.83
0.67
0.83
1.25
1.00

4-138

THAN OR
EQUAL.TO
80386·

v'
v'

v

v'
v'
v'

v
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'
v'

v'
v'

,

Application Note 111
Appendix

(Continued)

80C286 INSTRUCTION
DAA
DAS
DEC reg
DECmem
DIV word, reg
DIV word, mem
ENTER immed1, immed2 (immed 2 = 6)
HLT
IDIV word, reg
IMUL word, mem
IN
INC reg
INCmem
INS
INT 3 (real mode)
INT immed (real mode)
INT immed (PVAM same privilege)
INT immed (PVAM different privilege)
INTTASK-GATE(PVAMTaskSwitch)
INTO (No Jump)
INTO (Yes Jump real mode)
IRET (real mode)
IRET (PVAM same privilege)
IRET (PVAM different privilege)
IRET (PVAM task switch)
Jcond label (No jump)
Jcond label (Yes jump)
JMP near_label
JMP Far--'abel (real mode)
JMP FAR_LABEL (PVAM)
JMP CALL.GATE (PVAM same privilege)
JMP TASK-GATE (PVAM task switch)
JMP TSS (PVAM task switch)
LAHF
LARreg
LARmem
LDS (real mode)
LDS(PVAM)
LEA
LEAVE
LGDT
LlDT
LLDTreg
LLDTmem
LMSWreg
LMSWmem
LODS
LOOP (Jump)
LOOP (No Jump)

NUMBER
CLOCKS TO
EXECUTE
ON80C286

NUMBER
CLOCKS TO
EXECUTE
ON 80386

80386/
80C286

3
3
2
7
22
25
36
2
25
24
5
2
7
5
23
23
40
78
167
3
24
17
31
55
169
3
7
7
11
23
38
183
178
2
14
16
7
21
3
5
11
12
17
19
3
6
5
8
4

4
4
2
6
22
25
35
5
27
19
12
2
6
15
33
37
59
99
280
3
35
22
38
82
232
3
7
7
12
27
45
288
279
2
15
16
7
22
2
4
11
11
20
20
10
13
5
11
11

1.33
1.33
1.00
0.86
1.00
1.00
0.97
2.50
1.08
0.79
2.40
1.00
0.86
3.00
1.43
1.61
1.48
1.27
1.68
1.00
1.46
1.29
1.23
1.49
1.37
1.00
1.00
1.00
1.09
1.17
1.18
1.57
1.57
1.00
1.07
1.00
1.00
1.05
0.67
0.80
1.00
0.92
1.18
1.05
3.33
2.17
1.00
1.38
2.75

4-139

80C286
FASTER
THAN OR
EQUAL TO
80386

v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v

Application Note 111
Appendix

(Continued)

80C286 INSTRUCTION
LSLreg
LSLmem
LTR reg
LTRmem
MOVreg, reg
MOVmem, reg
MOV reg, immed
MOV mem, immed
MOV seg_reg, reg (real mode)
MOV seg_reg, mem (real mode)
MOV seg_reg, reg (PVAM)
MOV seg_reg, mem (PVAM)
MOVS
MULreg
NEG reg
NEGmem
NOP
NOT reg
NOTmem
OR reg, reg
OR mem, reg
.OR reg, immed
OR mem, immed
OUT
OUTS
POP reg
POPmem
POP seg_reg (real mode)
POP seg_reg (PVAM)
POPA
POPF
PUSH reg
PUSHmem
PUSH seg_reg
PUSHA
PUSHF
RCR or RCL reg, 1
RCR or RCL mem, 1
RCR or RCL reg, el (el = 4)
RCR or RCL mem, el (el = 4)
RCR or RCL reg, 4
RCR or RCL mem, 4
ROR or ROL reg, 1
ROR or ROL mem, 1
ROR or ROL reg, el (el = 4)
ROR or ROL mem, el (el = 4)
ROR or ROL reg, 4
ROR or ROL mem, 4

. NUMBER
CLOCKS TO
exECUTE
ON80C286
14
16
17
19
2
3
2
3
2
5
17
19
5
21
2
7
3
2
7
2
7
3
7
3
5
5
5
5
20
19
5
3
5
3
17
3
2
7
9
. 12
9
12
2
7
9
12
9
12

4-140

NUMBER
CLOCKS TO
EXECUTE
ON 80386
20
21
23
27
2
2
2
2
2
5
18
19
7
15
2
6
3
2
6
2
6
2
7
10
14
4
5
7
21
24
5
2
5
2
18
4
9
10
9
10
9
10
3
7
3
7
3
7

803861
80C286
1.43
1.31
1.35
1.42
1.00
0.67
1.00
0.67
1.00
1.00
1.06
1.00
1.40
0.71
1.00
0.86
1.00
1.00
0.86
1.00
0.86
0.67
1.00·
3.33
2.80
0.80
1.00
1.40
1.05
1.26
1.00
0.67
1.00
0.67
1.06
1.33
4.50
1.43
1.00
0.83
1.00
0.83
1.50
1.00
0.33
0.58
0.33
0.58

80C286
FASTER
THAN OR
EOUALTO
·80386

v
v
v
v
v
v
v
.v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v

Application Note 111
Appendix

(Continued)

80C286 INSTRUCTION
REP INS (ex = 100)
REP MOVS (ex 100)
REP OUTS (ex 100)
REP STOS (ex 100)
REP CMPS (ex 100)
REPE CMPS (N 100)
REPE SCAS (N 100)
RET (near)
RET (far real mode)
RET (far PVAM same privilege)
RET (far PVAM different privilege)
SAHF
SHIFT reg, 1 (SHIFT SAL, SAR, SHR)
SHIFTmem,1
SHIFT reg, el (el 4)
SHIFT mem, el (el 4)
SHIFT reg, 4
SHIFTmem,4
SBB reg, reg
SBBmem,reg
SBB reg, immed
SBB mem, immed
SCAS
SGDT
SIDT
SLDTreg
SLDTmem
SMSWreg
SMSWmem
STS
STD
STI
STOS
STR reg
STRmem
SUB reg, reg
SUB mem, reg
SUB reg, immed
SUB mem, immed
TEST reg, reg
TEST mem, reg
TEST reg, immed
TEST mem, immed
VERRreg
VERRmem
VERWreg
VERWreg

=
=
=
=
=
=

=

=
=

NUMBER
CLOCKS TO
EXECUTE
ON80C286

NUMBER
CLOCKS TO
EXECUTE
ON 80386

80386/
80C286

405
405
405
304
905
905
805
11
15
25
55
2
2
7
9
12
9
12
2
7
3
7
7
11
12
2
3
2
3
2
2
2
3
2
3
2
7
3
7
2
6
3
6
14
16
14
16

613
405
1205
505
905
905
805
10
18
32
68
3
3
7
3
7
3
7
2
6
2
7
7
9
9
2
2
2
2
2
2
3
4
23
27
2
6
2
7
2
5
2
5
10
11
15
16

1.51
1.00
2.98
1.66
1.00
1.00
1.00
0.91
1.20
1.28
1.24
1.50
1.50
1.00
0.33
0.58
0.33
0.58
1.00
0.86
0.67
1.00
1.00
0.82
0.75
1.00
0.67
1.00
0.67
1.00
1.00
1.50
1.33
11.50
9.00
1.00
0.86
0.67
1.00
1.00
0.83
0.67
0.83
0.71
0.69
1.07
1.00

4-141

80C286
FASTER
THAN OR
EQUAL TO
80386

v
v
v
v
v
v
v
v
v
v
v
v
v

v
v
v
v
v
v
v
v
v
v
v
v
v
v

v
v

Application Note " ,
Appendix

(Continued)

BOC288 INSTRUCTION
WAIT
XCHG reg, reg
XCHG reg, mem
XLAT
XORreg,reg
XORmem,reg
XOR reg,lmmed
XOR mem, immed
TOTAL number clockS to execute all Instructions
AVERAGE

NUMBER
CLOCKS TO
EXECUTE
ONBOC288

3
3
5
5
2
7

3
7

-6978

NUMBER
CLOCKS TO
EXECUTE
ONB0388
6

3
5
5
2
6
2
7

-9048

B0388/
BOC288
2.00
1.00
1.00
1.00
1.00
0.86
0.67
1.00

-1.24

Number of Instructions faster on 8OC286
Number of Instructions equal on both processors
Number of Instructions faster on 80386

74
66
50

--

Total Number of Instructions analyzed

190

4-142

80C288
FASTER
THAN OR
EQUAL TO
80388

v
v
v
v
v
v

Harris Semiconductor

=

No. 112

-----=

Harris Digital

March 1989

80C286/80386 HARDWARE COMPARISON
Author: Ted Schaufelberger
The Harris 80C286 static CMOS microprocessor, available
with maximum operating frequencies of 16-MHz and 20MHz, offers both performance and design advantages over
the 80386 when operating at the same frequency. When
both the 80C286 and 80386 are operated on a 16-bit data
bus, which fully supports industry standard 8086/80286
code, the 80C286 has better performance, and is significantly simpler to design with than the 80386. The 80C286
also uses significantly lower power than the 80386, leading
to less expensive, more reliable overall system design (see
Figure 1).
ICC (mA)
550

.. The 80C286 supports a fully pipelined mode of operation for maximum system performance (Ref. section on
Pipelined Operation on a 16-Bit Data Bus).
.. The 80C286 remains in a pipelined mode of operation
even when idle bus cycles occur (Ref. section on Idle
Cycles).
.. The 80C286 instruction prefetch takes one bus cycle to
execute, thereby minimizing the time that the processor
Execution Unit must wait should it need the bus (Ref.
section on InstructionPrefetching a 16-Bit Data Bus).
·80386

550mA

.. The 80386 requires five additional control lines to be
generated by external logic in order to implement a 16bit data bus (Ref. section on Control Signals
Required to Implement a 16-Bit Data Bus).

500

450
400

.. The 80386 does not support a fully plpelined mode of
operation. Some pipelining can be achieved, but to
accomplish this, external bus 'monitor' logic must be
added to the system (Ref. section on Pipelined Operation on a 16-Bit Data Bus).

350
300
250
200

.. The 80386's pipelining is disrupted by idle bus cycles.
A non-pipelined bus cycle, usually with an additional
wait state, must be executed before the 80386 can
return to pipe lined mode. Idle bus cycles occur an average of 9% of the time (Ref. section on Idle Cycles).

150
100

L

.. The 80386 instruction prefetch takes two bus cycles to
execute, which cim cause performance degradation by
forcing the Execution Unit of the processor to wait a full
bus cycle for use of the bus In order to complete an
Instruction (Ref. section on Instruction Prefetchlng on a
16-Bit Data Bus).

BD386

8OC286

20MHz

--.J

FIGURE 1. BOC2B6/803B6 POWER CONSUMPTION
COMPARISON

The following comparison highlights some of the performance advantages that exist on the 80C286:

16-Bit Data Bus Operation

Summary of 16-Bit Data Bus
Performance

This section will discuss the control signals required to Implement a 16-bit data bus, as well as plpelined operation,
idle cycles, and instruction prefetching on a 16-bit bus.

·80C286
.. The 80C286 already has all necessary control flnes
needed to Implement a 16-bit data bus (Ref. section on
Control Signals Required to Implement a 16-Bit Data
Bus).

Control Signals Required to Implement a
16-Blt Data Bus

The

80C286 microprocessor has an the control lines
needed to implement a 16-bit data bus resident on chip, no
further control lines are required.

4-143

Application Note 112
80386 SIGNALS
BE3#
H*
H
H
H
H
H* '
H
H
L*
L*
L*
L
L*
L
L:

BE2#

BE1#

H*
H
H
H
L
L*
L
L
H*
H*
H*
L
L*
L
L

H*
H
L
L
H
H*
L
L
H*
L*
L*
H
H*
L
L

16-BIT BUS SIGNALS
BEO#

A1

BHE#

BLE#(AO)

H*
L
H
L
H
L*
H
L
L*
H*
L*
H
L*
H
L'

X
L
L
L
H
X
L
L
X
X
X
H
X
L
L

X
H
L
L
H
X
L
L
X
X
X
L
X
L
L

X
L
H
L
L
X
H
L
X
X
X
L
X
H
L

COMMENTS
X-No Active Bytes

X-Not Contiguous Bytes

X-Not Contiguous Bytes
X-Not Contiguous Bytes
X-Not Contiguous Bytes
X-Not Contiguous Bytes

BLE# Asserted When 00-07 of 16-Bit Bus is Active.
BHE# Asserted When 08-015 of 16-Bit Bus is Active.
A1 Low For All Even Words; A1 High For All Odd Words.
Key:

X = Don't Care
H = High Voltage Level
L = Low Voltage Level
* = A Non-Occurring Pattern of Byte Enables; Either None are Asserted, or the Pattern has Byte Enables Asserted
for Non-Contiguous Bytes
FIGURE 2. A1, BLE#, AND BHE# SIGNAL GENERATION TABLE

In order to implement a 16-bit data bus with the 80386
microprocessor, it is necessary to create at least the following five additional control signals: Address Line 1 (A1), Bus
Low Enable (BLE#), Bus High Enable (BHE#), Bus 8ize
16-Bits (8816#), and Next Address (NA#).

eeo#
l

X

H

l

l

X

H

l

l

l

X

l

X

X

H

X

l

H
BE1#

l

l

l
H

The first of these signals, A 1, is an additional address line
required to convert the granularity of the 80386's address
space from'double-word size entities (32-bit) to word size
entities (16-bit). The second two signals, BLE# and BHE#,
primarily serve as chip selects which enable the appropriate
byte or bytes onto the 16-bit data bus. These three signals
are generated from the four B0386 byte enables (BEO#BE3#) as shown in Figure 2. The logic to implement these
signals is shown in Figure 3.

..

~~

13
ID

BE1#

H

l
K

~

MAP FOR A 1

SIGNA~

BEO#

H

l
l

l

Iix' Hi

l

H

l

X

l

In addition to these three control signals generated from
80386 signals as outputs, two input control signals to the
80386 must be generated by external logic (B816# and
NA#).
'
,

ll~

x

H

l

l

X

H

l

l

~

X

l

B~~~
~#

"13
ID

8E3#

l

l

K

BE1#

B816# is used to inform the 80386, on a cycle-by-cycle
basis, that a 16-bit bus size is to be used for data transfer.
NA# is used to request that the 80386 put the next cycle
address on the bus early, thereby pipelining that cycle.
The 80386, therefore, requires five additional control lines,
three outputs and two inputs, in order to implement a 16-bit
data bus. The generation of these control lines, in turn, requires additional 'glue' logic (which also introduces additional signal propagation delay, thereby reducing address
access time available to the system), and finally, there is additional bus cycle 'monitor' logic necessary if the 16-bit
data bus is to be pipelined for higher performance.

H

l

~

MAP FOR 16

~

BIT BHE# SIGNAL

BEO#

H

l
l

X

l

H

l

X

l

H

l

l

H

x

Irx

X

I~ 2-

l

l

"f1I

4-144

ID

H

l

H
BE1#

H

l

l
K • MAP FOR 16 • BIT BLE # SIGNAL

FIGURE 3. A1, BLE#, AND BHE# LOGIC

Application Note 112
Pipelined Operation on a 16-Bit Data Bus
At a given clock frequency, pipelined address operation increases a system's performance, while simultaneously allowing relatively slower memories and I/O devices to be used.
Pipelined address operation provides the system increased
address access time, and increased -address decoding time.
The 80C286 is optimized for, and directly supports, fully
pipelined bus operations on a 16-bit data bus. In other
words, the 80C286 performs all bus operations in a fully
pipelined mode.
The 80386 does not support fully pipelined operation on a
16- bit data bus. In order to pipeline a bus cycle on the
80386, the Next Address (NA#) signal must be asserted to
the processor. If the Next Address (NA#) signal and the Bus
Size 16-Bit (BS16#) signal are both asserted in the same
bus cycle, the NA# signal will not be recognized. Since the
BS16# signal must be asserted to the 80386 for many
patterns of 16-bit and 8-bit transfers to take place correctly,
the pipelining of transfers over a 16-bit bus is limited.
To allow pipelining of 16-bit data, external logic must be implemented to monitor the type of bus cycle taking place, decide if the cycle can be pipelined, and, if so, negate the
BS16# signal to the 80386 and assert the NA# signal. Pipelining is possible only if the bus cycle is one of the following
three types:
(1) A read operand cycle using only the lower half of the
data bus
(2) A write operand cycle using only the lower half of the
data bus
,(3) A write operand cycle using only the upper half of the
data bus
The 80386 will not allow 16-bit pipelining of read or write cycles that have byte alignments that do not conform to one of
the previously mentioned three types.
The 80C286, then, fully supports address pipelining, yielding
the highest possible system performance, while using relatively lower performance (and therefore cheaper) memories
and peripherals. The 80386, however, does not support fully
pipelined 16-bit bus operation, and, to support even partial
pipelining, requires external bus 'monitor' logic.
Idle Cycles
Another factor to consider when evaluating 80C286 and
80386 performance is the effect of idle cycles on pipelined
operation. Calculations have shown that, on average, bus idle
cycles occur in the system approximately 9% of the time. The
effect of idle cycles on pipelining is quite different on the
80C286 than on the 80386.

The 80C286 pipelined operation is not affected by idle cycles. When an idle cycle or cycles occur in a stream of pipelined bus cycles, the 80C286 returns to pipelining bus cycles
immediately after the last idle cycle. In this way, each device
on the bus (e.g. memory, peripheral) maintains a fixed timing
associated with that device, and therefore always uses the
minimum number of wait states required for that device:
On the other hand, the 80386 pipelined operation is
disrupted by idle cycles. With the 80386, an idle cycle or
cycles occurring in a pipelined stream of bus cycles breaks
the pipelining operation. Once an idle cycle has occurred, a
non-pipelined bus cycle must always be executed prior to
resuming pipelining. Since a non-pipelined bus cycle will
have different timing than a pipelined bus cycle (even to the
same device), an additional wait state must be added to this
bus cycle. This not only degrades performance, but requires
additional external logic to differentiate between a pipelined
bus cycle access, and a non-pipelined bus cycle access,
even to the same device with the same address.
From the preceding, it can be seen that when executing 16bit code, the 80C286 has a 9% performance increase
over the 80386, due to the manner in which each processor handles idle cycles alone. Note, that with the
80386, a pipelined stream of bus cycles will always be disrupted when an idle cycle occurs, whether using a 16-bit
data bus or a 32-bit data bus. In either case, a non-pipelined
bus cycle must be executed prior to resuming pipelined operation.
Instruction Prefetching on a 16-Bit Data Bus
One final factor needs to be considered in the evaluation of
80C286 and 80386 performance on a 16-bit data bus; the
effect that prefetching instructions has on instruction execution time. Prefetching of instructions is done by the processor
Bus Unit on both the 80C286 and 80386. The prefetch is
done when the bus would otherwise be idle for the upcoming
cycle, and the prefetch queue is not full.
The 80C286 does word size (16-bit) prefetching of instructions, and therefore completes it's prefetch activities in one
bus cycle. This minimizes the waiting period to gain access to
the bus by other processor entities, such as the Execution
Unit.
The 80386 does doubleword (32-bit) prefetching of instructions, even on a 16-bit bus. This means that once a prefetch
has begun execution, two bus cycles are required to complete the prefetch. If, for instance, the processor's Execution
Unit requires the bus for a data fetch or write in order to complete an executing instruction, it must wait for the two bus cycles of the prefetch to complete before it can access the bus.
This can substantially degrade instruction execution time.

4-145

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Application Note 712
32-Bit Data Bus Operation
This section discusses operating the 80386 on a 32-bit bus . In addition, in order to accommodate the additional 16 data
in order to overcome some of the handicaps it suffers on a lines of the 32-bit bus, twice as many memory devices are
16-bit bus. In addition, several advantages and dis- typically required with the 32-bit system as compared to a
advantages associated with the 80386 on a 32-bit bus are 16-bit system. This amounts to an Increase In DRAM, alone,
considered.
of from 18 devices in a typical 16-bit system to 36 devices In
a typical 32-bit system.
Hardware Advantages of the 80386 on a 32-Bit Data
Bus
The 16 additional data lines of the 32-bit bus Increase the
There are several· advantages to operating the 80386 on a EMI problems inherent in the system. The additional coupling
32-bit data bus as .0Pposed to a 16-blt data bus. Some of the and crosstalk between data lines must be taken Into considcontrol lines that were required for a 16-bit data bus are elim- eration when laying out the system PC board.
inated (A1, BlE#, BHE#, and B816#).·1t Is possible to come
closer to a fully plpelined mode of operation, although idle
cycles will still disrupt. the pipelining 9% of the time. Finally,
prefetching on a 32-bit bus executes in one bus cycle
instead' of .two. Offsetting these advantages, however are
several major disadvantages.

There is a Significant increase in the amount of board space
used as a result of the additional chips required to implement
a 32-bit bus, as well as the 16 additional data lines. This results in a larger, more complex (and more expensive) PC
board than with a 16-bit system, often requiring an increase
In the number of board layers.

Hardware Disadvantages of the 80386 on a 32-blt Data
Bus
When using a full 32-bit data,bus, the chip complexity of a
80386 based system Is Increased over a 16,.bit system.
Twice as many transceivers (four Instead of two) are required.

References
Intel Corporation. 1987.
80386 Hardware Reference Manual.

4-146

Harris Semiconductor

--------

No. 120

:= - =: ~= =- '=: ~= =.: =

Harris Digital

June 1989

INTERFACING THE 80C286-16 WITH THE 80287-10
Author: Ted Schaufelberger
An important requirement in many systems is the ability to
off-load numeric data processing. In an 80C286 system,
this can be accomplished with an 80287 numeric co-processor. However, as processor speeds increase, it may
become necessary to interface a high speed 80C286
processor with a lower speed 80287. This Document will
briefly describe the interface between a '16MHz .80C286
(80C286-16) and a 10MHz 80287 (80287-10).
InterfaCing the 80C286 with an 80287 can be broken down
into three main areas:
(1) Bus control lines and-data lines which coordinate and
implement the flow of data between the two processors
(i.e. the data lines, chip select lines, and read/write
lines).

Clock Lines
A system using a 16MHz 80C286 with a 10MHz 80287 reo
quires separate clock lines for the two processors. The
32MHz system clock used by the 80C286-16 is too fast for
the 80287 ± 10, necessitating a dedicated clock driver for
the 80287. This clock driver should supply a'10MHz clock
to the 80287 with a 1/3 duty cycle to allow the 80287-10 to
run at it's full 10MHz capability. One solution for providing
this clock is the 82C84A-l, which meets this specification
with either a 30MHz crystal at it's crystal inputs, or a
30MHz external frequency input to it's EFI pin. In either
case, a 10MHz 1/3 duty cycle clock is output to the 80287.
Note that when using a dedicated clock driver such as this,
the CKM pin of the 80287 must be pulled up.

(2) The clock line(s), which drive the two processors.

Status Lines
The 80C286 and 80287 communicate status information
(3) The four status lines through which the 80C286 and . with one another through four signals; the BUSY line, the
80287 directly communicate status information to one ERROR line, the peripheral request line (PEREQ), and the
another - comprised of the BUSY, ERROR, Peripheral PEACK line.
Request (PEREQ), and Peripheral Acknowledge
The BUSY and ERROR lines can be connected from the
(PEACK) lines.
Bus Control Lines
80287 to a 80C286-oriented chipset, or from the 80287
directly to a 80C286. In the case of the chipset interface, the
The various bus control and data lines in most systems signal timing between the 80287 and· 80C286 is coordi·
would be coordinated by either a bus controller (such as the nated by the chipset. In the case of the direct 80287 to
82C288), or a bus controller subsection of .an 80C286 80C286 interface, the signal timing is handled by the
oriented chip set. All requisite bus control timing between a' 80C286, and, since the signal flow direction is from the
16MHz 80C286, and a 10MHz 80287 would then be han· 80287 to the 80C286 (I.e. from the slower device to the
died by these devices (typically with one wait-state faster device), no additional hardware is required to achieve
inserted to allow for the slower 80287-10).
proper timing.
U174AC04
(FROM 82C284 OR RESET
EQUIVALENT)

--------1

4
U274ACl12
_P_EA_C_K_....._ _...._ _ _3--fr-~P~R-Q... 5 LPEACK
(FROM 8OC286)
J
(32MHz SYSTEM .:2;;:;8.;;6-=C.;;L;.:K-I-_ _ _ _ _~:t
CLOCK) 2 >C
6

U374AC08
1
3 GPEACK (TO 80287
PEACK)

......-JVIIIoI--·+ 5V
FIGURE 1. PEACK STRETCH CIRCUIT

4-147

Application Note 120
The peripheral request (PEREQ) line should be connected
directly from the 80287 to the 80C286, and again, since the
signal flow direction is from the 80287 to the 80C286, no
additional hardware is required.

The operation of the circuit shown in Figure 1 is as follows:

.The peripheral acknowledge (PEACK) line is normally
connected directly from the 80C286 to the 80287. In this
case the signal flow direction is from the 80C286 to the
80287 (i.e.- faster device to slower device), and the
PEACK active time is not guaranteed to meet the requirements of the slower 80287-1Q. Worst case timing for the
80C286-16 reveals that PEACK output could be as short as
45.5ns (I.e. PEACK (min)
45.5ns). The 80287-10 input
requirement is PEACK (min) = 60ns.

(2) When the 80C286 asserts the PEACK signal, the gated
version of this signal (GPEACK) is asserted with minimal
delay (7.9ns through the 'AC08).

(1) The RESET signal (which is also applied to the 80C286)
. is used to initialize the 'AC112 to a known inactive state
(Q = 1).

(3) On the falling edge of the 80C286 ClK at the beginning
of Phase 2 of the Ts.cycle, the low state of PEACK is
clocked into the 'AC112. This effectively holds GPEACK
low for an additional clock cycle longer than standard
PEACK timing.

=

(4) On the falling edge of the 80C286 ClK at the beginning
of phase 2 of the first TC cycle, the high state of PEACK
Is clocked into the 'AC112, which then causes GPEACi<
to go inactive.

The proper PEACK timing can be achieved using the Circuit
shown in Figure 1 comprised of a 74AC04, 74AC08, and a
74AC112. Referring to the timing diagram shown In
Figure 2, it can be seEm that this circuit effectively
'stretches' the 80C286's PEACK output (in the form of
GPEACK) to 72.7"s, which satisfies the 80287-10 requirement

The net effect of this circuit operation is to extend the
80C286's Peripheral Acknowledge signal to the 80287-10
sufficiently to meet it's .requirements.

I~·~----------TS----------~·~I~·~-----------TC~----------~·+1··-8OC286
CLK

t - - 31_2ns ~
(32 -Mi2)
1

1

I

11
PEACK

18

I~~~

1 3.2

25.9

TC(WAIT)

1

1

1

20

I//////$'"

1
I

4_9

17.3

GPEACK---:I~~~~~~S~~~~~S~~<~·=iI~~~~~7~~7~n~S~(~m~in~)~~~~~~.z~~~~~~h2~~~~~~~------------PEACK
@K

2.7

23.9.1

H////$

12 _7

25.9

%\\~"''''~

I
2.7 9.4

2.7

~
FIGURE 2. PEACK CYCLE TIMING

4-148

9.4

CMOS PERIPHERALS

PAGE

82C37N883

High Performance Programmable DMA Controller ................... .

5-3

82C52/883

Serial Controller Interface ........................................ .

5-4

82C54/883

Programmable Interval Timer ..................................... .

5-19

82C55N883

Programmable Peripheral Interface ................................ .

5-38

82C59N883

Priority Interrupt Controller ................•...............•.......

5-62

82C82/883

Octal Latching Bus Driver ........................................ .

5-81

82C83H/883

Octal Latching Inverting Bus Driver ................................ .

5-90

82C84A/883

Clock Generator Driver .......................................... .

5-98

82C85/883

Static Clock Controller/Generator ................................. .

5-110

82C86H/883

Octal Bus Tranceiver .•...........................................

5-111

82C87H/883

Octal Bus Tranceiver .........•...................................

5-119

82C88/883

Bus Controller ..........................•..........•..........•..

5-127

82C89/883

Bus Arbiter ......•........•............•.........................

5-138

82C284/883

Clock Generator and Ready Interface for 80C286 Processors ........ .

5-153

82C288/883

Bus Controller for 80C286 Processors ............................. .

5-168

App Note 109

82C59A Priority Interrupt Controller ............................... .

5-169

5-1

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Do.

1m HARRIS

82C37A/883
CMOS High Performance
Programmable DMA Controller

June 1989

Features

Pinouts

• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.

82C37A1883 (CERAMIC DIP)
TOP VIEW

• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitialization Capability
• Cascadable to any Number of Channels
• Special Mode Permits 16-Bit, Zero Wait State DMA Transfers
• High Speed Data Transfers:
~ Up to 4 MBytes/sec with 8MHz Clock in Normal Mode
~ Up to 8 MBytes/sec with 8MHz Clock in 16-Bit Mode
~ Up to 6.25 MBytes/sec with 12.5MHz Clock in Normal Mode
~ Up to 12.5 MBytes/sec with 12.5MHz Clock in 16-Bit Mode
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
~ ICCSB = 10flA Maximum
~ ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software

Description
The 82C37A/883 is an enhanced version of the Industry standard 8237A
Direct Memory Access (OMA) controller, fabricated using Harris' advanced
2 micron CMOS process. Pin compatible with NMOS designs, the 82C37A/
883 offers Increased functionality, Improved performance, and dramatically
reduced power consumption. The fully static design permits gated clock operation for even further reduction of power.

~

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The 82C37A/883 controller can improve system performance by allowing
external devices to transfer data directly to or from system memory. Memoryto-memory transfer capability is also provided, along with a memory block
initialization feature. A new feature allows each channel to be individually programmed for 8-bit data transfers or 16-bit data transfers. DMA requests may
be generated by either hardware or software, and each channel is independently programmable with a variety of features for flexible operation.
The 82C37A/883 is designed to be used with an external address latch, such
as the 82C82, to demultiplex the most significant 8 bits of address. An addit10nallatch Is required to temporarily store the most significant 8 bits of data If
l6-bit memory-to-memory transfers are desired. The 82C37A/883 can be
used with Industry standard microprocessors such as 80C286, 80286, 80C86,
80C88, 8088, 8085, 8086, Z80, NSC800, 80186 and others.
Multlmode programmability allows the user to select from three basic types of
DMA services, and reconflguration under program control Is possible even with
the dock to the controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize these registers
following DMA termination (end of process).

CAUTION: These devices are sensHive to electroslatlc discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris COlPoration 1989

5-3

a:

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82C37A1883 (CERAMIC LCC)
TOP VIEW

Do

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m

82C52/883

HARRIS

CMOS Serial Controller Interface

June 1989

Features

Pinouts
82C52/883 (CERAMIC DIP)

• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.

TOP VIEW

• Single Chip UART/BRG

eso

• 16MHz (1M Baud) Operation

vee
OR

• Crystal or External Clock Input

SOl

o On-Chip Baud Rate Generator - 72 Selectable Baud Rates

INTR

• Interrupt Mode With Mask Capability

RST

• Microprocessor Bus Oriented Interface

TBRE

• 80C86 Compatible

eo
RTS

• Single +5V Power Supply

OTR

• Low Power Operation ..••••••.•••••••..••..•.•.•.• 1mA/MHz typical

,OSR

• Modem Interface

eTS

• Line Break Generation and Detection

GNO

soo

• Military Operating Temperature Range .•..•••••.•• -55 0 C to +125 0 C

82C52/883 (CERAMIC LCe)

Description

TOP VIEW

The Harris 82C52/883 is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a
single chip. Utilizing the Harris advanced Scaled SAJIIV CMOS process, the
82C52/883 will support data rates up to 1 M baud asynchronously with a 16X
clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for anyone of 72
different baud rates using a single industry standard crystal or external
frequency source. A unique pre-scale divide circuit has been designed to
provide standard RS-232-C baud rates when using anyone of three industry
standard baud rate crystals (1.8432 MHz, 2.4576 MHz, or 3.072 MHz).
A programmable buffered clock output (CO) is available and can be
programmed to provide either a buffered oscillator or 16X baud rate clock for
general purpose system usage.

Copyright © Harris Corporation 1989

5-4

i5

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II:
0

02

SOl

03

INTR

04

RST

05

TBRE

06

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07

RTS

AO

ofR

:;: -x

x

0

0
0

(/)

~

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!~

82C52/883
Block Diagram

A

00-07

AD
Wii
AO
Al

<"

"

1
2
11'
12

28

IX

OX
CO

RST

"I"-

3-10
DATA
BUS
BUFFER

f+-

...

...

"

21

22
26

TBRE
DR

READ/WRITE
CONTROL
LOGIC

"...

+

TRANSMITTER
BUFFER
REGISTER

'" hRANSMITTER
;t REGISTER

.... 1

15

SDO

p--.s

1

13
14

UART
CONTROL &
STATUS
REGISTERS

PROGRAMMABLE
BAUD RATE
GENERATOR

t

RECEIVER
BUFFER
REGISTER

....

1 RECEIVER
REGISTER
I

25

P-S

23
CONTROL
LOGIC

24
INTR

....
INTERNAL
DATA
BUS

"
I..--

5-5

MODEM
CONTROL &
STATUS
REGISTERS

18
17
19
20

SOl

Pin Description 82C52/883
SYMBOL

PIN
NO.

TYPE

ACTIVE
LEVEL

RD

1

I

Low

WR

2

I

Low

00-07

3-10

I/O

High

DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of data,
control and status Information between the 82C52/883 and the CPU. For character formats of less
than 8 bita, the corresponding 07, 06 and 05 are considered "don't cares" for data WRITE operations
and are 0 for data READ operations. These lines are normally in a high impedance state except
during read operations. DO is the Least Significant Bit (LSB) and is the first serial data bit to be
received or transmitted.

AO,A1

11,12

I

High

ADDRESS INPUTS: The address lines select the various internal registers during CPU bus
operations.

IX,OX

13,14

I/O

SDO

15

0

GND

16

Low

GROUND: Power supply ground connection.

CTS

17

I

Low

CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem Status
Register. Any change of state in CTS causes INTR to be set true when INTEN and MIEN are true.
A false level on CTS .willinhibit transmission of data on the SDO output and will hold SDO In the
Mark (high) state. If CTS goes false during transmission, the current character being transmitted
will be completed. CTS does not affect Loop Mode operation.

DSR

18

I

Low

DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register. Any
change of state of DSR will causelNTR to be set if INTEN and MIEN are true. The state of this
signal does not affect any other circuitry within the 82C52/883.

DTR

19

0

Low

DATA TERMINAL READY: The DTR-signal can be set (low) by writing a logic 1 to the appropriate bit
in the Modem Control Register (MCR). This signal is cleared (high) by writing a logic 0 in the DTR
bit in the MCR or whenever a reset (RST = high) Is applied to the 82C52/883.

RTS

20

0

Low

REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate bit In
the MCR. This signal is cleared (high) by writing a logic 0 to the RTS bit In the MCR or whenever
a reset (RST = high) Is applied to the,82C52/883.

CO

21

0

TBRE

22

0

High

TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the
Transmitter Buffer Register (TBR) has transferred its data to the Transmit Register. Application
of a reset (RST) to the 82C52/883 will also set the TBRE output TBRE is cleared (low) whenever data
is written to the TBR.

RST

23

I

High

RESET: The RST Input forces the 82C52/883 Into en "Idle" mode in which all serial data activities are
suspended. The Modem Control Register (MCR) along with Its associated outputs are cleared. The
UART Ststus Register (USR) is cleared except for the TBRE and TC bits, which are set The
82C52/883 remains in an "Idle" state until programmed to resume serial data activities. The RST
input is a Schmitt triggered input•

INTR

24

0

High

. INTERRUPT REQUEST: ThelNTR output is enabled by thelNTEN bit in the Modem Control Register
(MCR). The MIEN bit selectively enables modem status changes to provide en Input to thelNTR logic.
Figure 9 in Design Information shows the overall relationship of these Interrupt control signals.

SOl

25

I

High

SERIAL DATA INPUT: Serial data Input to the 82C52/883 receiver circuits. A Mark (1) is high, and a
Space (0) is low. Data inputs on SOl are disabled when operating in the loop mode or when RST is true.

DR

26

0

High

DATA READY: A true level indicates that a character has been received, transferred to the RBR, and
is ready for transfer to the CPU. DR is reset on a data READ of the Receiver Buffer Register (RBR)
or when RST is true.

VCC

27

High

VCC: +5V postive powsrsupply pin. A 0.1 "F decoupllng capacitor from VCC (Pin 27) to GND
(Pin 16) is recommended.

CSO

28

Low

CHIP SELECT: The chip select Input acts as an enable signal for the RD and WR input signals.

I

DESCRIPTION
READ: The RD Input causes the 82C52/883 to output d!!!,to the data bus (00-07). The data output
depends upon the state of the address inputs (AO-A1). CSO enables the RD input
' WRITE: The WR input causes data from the data bus (00-07) to be Input to the 82C52/883.
Addressing and chip select action is the same as for read operations.

CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be used
as an external clock Input in which case OX should be left open.
High

SERIAL DATA OUTPUT: Serial data outputfrom the 82C52/883 transmitter Circuitry. A M~1) is a
logic one (high) and Space (0) Is logic zero Oow). SDO Is held in the Mark condition when CTS is
false, when RST is true, when the Transmitter Register is empty, or when in the Loop Mode.

CLOCK OUT: This output is user programmable to provide either a buffered IX output or a buffered
.Baud Rate Generator (16X) clock output The buflered IX (Crystal or external clock source) output
Is-provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero. Writing a logic one
to BRSR bit 7 causes the CO output to provide a buffered version of the internal Baud Rate
Generato. clock which operates at sixteen times the programmed baud rate; On reset 07 (CO select)
Is reset to O.

5-6

Specifications 82C52/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••••••.••••••••••.••••••••••••• +B.OV
Input, Output or 1/0 Voltage Applied. • • •• GND-0.5V to VCC+0.5V
Storage Temperature Range •••.••••••••••••. -650C to +150 0C
JunclionTemperature •••••••••••••••••••••••••••••••• +175 0C
Lead Temperature (Soldering 10 sec) ••.•••••.•••••••••• +3000C
ESD Classification ••••.•••••.•.••.••••••••••.••••••••• Class 1

Thermal Resistance
Bja
Ceramic DIP Package. • • • • • • • • • • • • •
450 C/W
Ceramic LCC Package. • • • • • • • . • • . • 5O.70 C/W
Maximum Package Power Dissipation at +1250C
CeramicDIPPackage ••••.••••.••.•••••.•••••••••••••• 1.1W
Ceramic LCC Package •••.•••••••.•••••.••••••••••• 9B6mW
Gate Count ••••••••••••.••.••••.••.•.•.....•..••• 1500 Gates

CAUTION: Stl9sses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range ••.•.•••••..•.• -550C to +1250 C
Operating Voltage Range ••.•••.••••••••••.••••• +4.5V to +5.5V
TABLE 1. B2C52/BB3 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

'(NOTE 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

1,2,3

-550C,!!;TA,!!;+125OC

.7VCC

-

V

1,2,3

-550C,!!;TA,!!;+125OC

-

O.B

V

-

V

GND+0.5

V

-

V

GND+0.5

V

Logical One Input
Voltage

V1H

VCC=5.5V

Logical Zero Input
Voltage

VIL

CLK Logical One
Input Voltage

V1H(CLK)

External Clock, VCC = 5.5V

1,2,3

-55OC ,!!;TA,!!; +1250C VCC-0.5

CLK Logical Zero
Input Voltage

VIL(CLK)

External Clock

1,2,3

-550C,!!;TA,!!; +1250 C

-

Schmitt Trigger
Logical One
Input Voltage

VTH

Reset Inpu~ VCC = 5.5V

1,2,3

-55°C,!!; TA 5. +1250 C VCC-0.5

Schmitt Trigger
Logical Zero
Input Voltage

VTL

Reset Input

1,2,3

-550C,!!;TA5. +1250 C

Output High Voltage

VOH

Input Leakage
Current
Output Leakage
Current

~

.,,;2
0'"

:;;=
10H = -2.5mA, Note 2
Except OX

1,2,3

-55°C 5.TA5. +125 0C

VOL

II

10

3.0

-

V

u!!:
Ie

'"
Do

IOH = -100"", Note 2
ForOX,IOH=-1.0mA
Note 2
Output Low Voltage

-

VCC-O.4

-

V

IOL = +2.5mA, Note 2
ForOX,IOL=+1.0mA
Note 2

1,2,3

-55 0C,!!;TA5. +1250C

-

0.4

V

VCC= 5.5V,
VIN = GND or VCC,
All inputs except IX

1,2,3

-550C5.TA,!!; +1250C

-1.0

+1.0

~A

VCC=5.5V,
VOUT=GNDorVCC

1,2,3

-55°C 5. TA 5. + 125°C

-10.0

+10.0

""

NOTE: 1. vee = 4.SV unless otherwise specified. All voltages referenced to device GND.
2 Interchanging of force and sense conditions is permitted.

CAUTION: These devices are sensitive to electronic discharge. Proper I.e. handling procedures should be followed.

5-7

Specifications 82C52/883
TABLE 2. 82C52/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

{NOTES 1,2)
CONDITIONS

SYMBOL

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

-

ns

Selee! Setup to Control
Leading Edge

{l)TSVCTL

9.10,11

-55°C S TA:S + 12SoC

30

Select Hold from Control
ll'ailing Edge

(2)TCTHSX·

9,10,11

-SSoC S TA :S + 12SoC

50

-

ns

Control Pulse Width

(3)TCTLCTH Control Consists of
RoorWR

9,10,11

-S50CSTAS+1250C

150

-

ns

Control Disable to
Control Enable

(4)TCTHCTL

9,10,11

-5S 0C:s TAS +125 0C

190

-

ns

120

ns

9,10,11

-55°C 

SELECT VALID

-

III

(3(

(21

TSVCTL

TCTLCTH

TCTHSX

{

~

r

(71

(BI

TOVWH

TWHOX

.1

VALID

(II

(31

_TSVCTL

(41

TCTLCTH

TCTHCTL_

RO
{

(51
TRLOV

~

:;

<"'

~::~ATlON

I

(

I

I

00-07

(6(
TRHOZ

~
"'C.X.Y

VALID

AC Test Circuit
V1

OUTPUT FROM
DEVICE UNDER 0-----....
TEST

------..------0

TEST
POINT

5-9

TEST CONDITION

V1

R1

R2

CL

1 1 Propagation Delay

1.7V

520

!!::

'"w
D..

Test Load Circuit
TEST CONDITION DEFINITION TABLE
R1
FROM OUTPUT
UNDER TEST

o---.....---~---o TEST
>

?R2

i

TEST
CONDITION

V1

R1

R2

C1

1.7V

S23

OPEN

1S0pF

2

VCC

2K

1.7K

SOpF

POINT

C1'

* Includes Stray and Jig Capacitance

A.C. Testing Input, Ouput Waveform
INPUT

OUTPUT

VlH +O.4V

VOH

1.5V

~'-_ _ _ _--'~ 1.5V
VOL

VlL· O.4V

A.C. Testing: All input signals must switch between VIL -D.4V and
VIH +O.4V. Input rise and fall times are driven at 1 nsN.
CAUTION: These devices are sensitive to electronic discharge. Proper

I.e. handling

procedures should be followed.

5-23

82C54/883
Timing Waveforms
WRITE

AO·l
(9)

IAW-

DATA BUS

----------------~

READ

AO·l

16)
~-----

lAD --------;._ _----{.

DATA BUS - ' - -

RECOVERY

iiii. WR

CLOCK AND GATE
MODE

COUNT"

WR

ClK

-----t----'rl

~

____

(27)

~,two

__________

~

5-24

tODGI26)

"lAST BYTE OF COUNT BEING WRITTEN

82C54/883
Burn-In Circuits
82C54/883 CERAMIC DIP

vee
01
02
vee

GND
F9
FlO
Fl1
F12
FO

el

Rl
Rl
Rl

Rl

Rl

Rl

Rl

Rl

Rl

Rl

Rl

R2

Rl

vee

GND
05

04
F2

vee

A

R2

Rl
R2

A

06

~

R1

Rl

GND

08
Fl

A

07
A

82C54/883 CERAMIC LCC

vee

()
~

ffi

8 0 !5

Rl Rl Rl

Rl
GND
Rl
F9
Rl
FlO
Rl
Fll
Rl
F12
R2
FO
OPEN

el

~~

Rl Rl

!5\---- OPEN
R1
't--VV\or-- GND
Rl
,1--"",,,,,- 05
Rl
I--JV\I\I- 04
R2
\-"V\I\r- F2
1\-"V\I\rR_5 VeC/2
Rl
It-oI\I\AI-- 08

vee = 5.5V ± 0.5V,
GND = ov
VIN = 4.5V ± 10%
VIL = -0.2V to 0.4V
Rl = 47kO ± 5%
R2 = 1.0kO ± 5%
R3 = 2.7kO ± 5%
R4 = 1.SkO ± 5%
R5 = 1.2kO ± 5%
C1 ... O.01/lF Minimum
fO = 100kHz ± 10%
f1 = 10/2, 12 = 11/2, ... 112 = 111/2

5-25

82C54/883
Packaging t
24 PIN CERAMIC DIP

o·

;s:

.. INCREASE MAX WAIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER ANISH

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0C ± 1QoC
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-3

28 PAD CERAMIC LCC
BOnOMVIEW

.442
.45B

.045
.055

.050
BSC

I

.064

1~·076

I

Ilnnnnnnnll
.074

Tl

.OBB

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 3200C ± 100C
Method: Furnace Braze
NOTE: All Dimensions are

~:'x

.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-4

tMiI-M-38510 Compliant Materials, Finishes, and Dimensions.

Dimensions are In Inches.

5-26

82C54/883
Metallization Topology
DIE DIMENSIONS:
183.5 x 215.7 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kA ± 2kA
GLASSIVATION:
Type: Si02
Thickness: 8kA ± 1kA
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy (LCC has Gold
Preform)
Temperature: Ceramic DIP - 460 0 C (Max)
Ceramic LeC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
0.26 x 105 A/cm 2

Metallization Mask Layout
82C54/883

04

A1

03
AO

.
~

a:
::E:l:
<..>!!::
a:
W
en

C> W

c..

02

01

00

CLKO

OUTO GATEO GNO

OUT1

5-27

GATE1

CLK1

Em HARRIS

82C54

DESIGN INFORMATION
CMOS Programmable Interval Timer
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
application and design information only. No guarantee is implied.
use

as

Functional Description
~ogic

General

Read/Write

The 82C54 is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.

The Read/Write Logic accepts inputs from the system bus
and generates control signals for the other functional blocks
of the 82C54. A 1 and AO select one of the three counters or
the Control Word Register to be read from/written into. A
"low" on the RD input tells the 82C54 that the CPU is reading one of the counters. A "low" on the WR Input tells the
82C54 that the CPU is writing either a Control Word or an
initial count. Both RD and WR are qualified by CS; RD and
WR are ignored unless the 82C54 has been selected by
holding CS low..

The 82C54 solves one of the most common problems in
any microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing
loops in software, the programmer configures the 82C54 to
match his requirements and programs one of the counters
for the desired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated.
Some of the other computer/timer functions common to
microcomputers which,can be implemented with the 82C54
are: • Real time clock
• Event counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller
Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to
interface the 82C54 to the system bus (see Figure 1).

Control Word Register
The Control Word Register (Figure 2) is selected by the
Read/Write Logic when A1, AO = 11. If the CPU then does a
write operation to the 82C54, the data is stored in the Control Word Register and is interpreted as a Control Word
used to define the Counter operation.
The Control Word Register can only be written to; status
Information is available with the Read-Back Command.
Counter 0, Counter 1;Counter 2
These three functional blocks are Idel;ltlcal in operation, so
only a single Counter will be described. The Internal block
diagram of a single counter is shown in Figure 3. The
counters are fully independent. Each Counter may operate
in a different Mode.

CLKO

CLKO
GATED

07-00

GATED

Dura

DUTO

eLK'

eLK1

GATE 1

GATE 1

DUT1

OUTl

os
elK!

elK!

GATU

GATE 2

OUTZ

OUTZ

FIGURE 2. CONTROL WORD REGISTER AND COUNTER
FUNCTIONS

FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC
FUNCTIONS

5-28

82C54

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

The Control Word Register is shown In the figure; it is not
part of the Counter itself, but its contents determine how the
Counter operates.

The Control logic is also shown in the diagram. ClK n,
GATE n, and OUT n are all con[lected to the outside world
through the Control logic.

The status register, shown in .the figure, when latched,
contains the current contents of the Control Word Register
and status of the output and null count nag. (See detailed
explanation of the Read-Back commal'!d.)

The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.

The actual counter is labeled CE (for Counting Element). It is
a 16 bit presettable sYnChronous down counter.
OlM and Oll are two 8-blt latches. Ol stands for "Output
latch"; the subscripts M and l for "Most significant byte"
and "least significant byte", respectively. Both are normally
referred to as one unit and called just OL. These latches
normally "follow" the CE; but if a suitable Counter latch
Command is sent to the 82C54, the latches "latch" the present count until read by the CPU and then return to
"following" the CEo One latch at a time is enabled by the
counter's Control logic to drive the Internal bus. This is how
the 16-bit Counter communicates over the 8-bit internal
bus. Note that the CE itself cannot be read; whenever you
read the count, It is the Ol that is being read.

82C54 System Interface

Basically, the select inputs AO, A1 connect to the AO, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method
or It can be connected to the output of a decoder, such as a
Harris HD-6440 for larger systems.

Operational Description
General
After power-up, the state of the 82C54 is undefined.
The Mode, count value, and output of all Counters are
undefined.
How each Counter operates is determined 'when it is
programmed. Each Counter must be programmed before it
can be used. Unused counters need not be programmed.
Programming The 82C54

Similarly, there are two 8-bit registers called CRM and CRl
(for "Count Register"). Both are normally referred to as one
unit and called just CR. When a new count is written to the
Counter, the count is stored in the CR and later transferred
to the CEo The Control logic allows one register at a time to
be loaded from the internal bus. Both bytes are transferred
to the CE simultaneously. CRM and CRl are cleared when
the Counter is programmed for one byte counts (either most
significant byte only or least significant byte only) the other
byte will be zero. Note that the CE cannot be written into;
whenever a count is written, it is written into the CR.

By contrast, initial counts are written into the Counters, not
the Control Word Register. The A 1, AO ·Inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.

FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM

FIGURE 4. 82C54 SYSTEM INTERFACE

Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register, which is selected when A1, AO =: 11. The Control Word
specifies which Counter is being programmed.

5-29

82C54

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is'implied.
Write Op'eratlons

A1

The programming procedure for the 82C54 is very flexible.
Only two conventions need to be remembered:
1. For each Counter, the Control Word must be written before the initial count is written.
2. The initial count mIJstfoliow the countformat specified in
the Control Word (least significant byte only, most significant byte only, or least significant byte and then most
significant byte).
Since the Control Word Register and the three Counters
have separate addresses (selected by the A1, AO Inputs),
and each Control Word specifies the Counter it applies to
(SCO, SC1 bits), no special instruction sequence is
required. Any programming sequence that follows the
conventions above is acceptable.
Control Word Format
A1, AO

= 11; CS = 0; AD = 1; WR = 0

SC - Select Counter:
SC1

SCO

0

0

Select Counter 0

.,

0

1

Select Counter 1

1

0

Seiect Counter 2

1

1

Read-Back Command (See Read Operations)

RW - Read/Write:
RW1

RWO

0

0

0

Counter Latch Command (See Read Operations)

1

Read/Write least significant byte only.

1

0

Read/Write most significant byte only.

1

1

Read/Write least significant byte first,
then most significant byte.

M-Mode:

AO

Control Word - Counter 0

'.. 1

1

LSB of Count - Counter 0

0

0
0

MSB of Count - Counter 0

0

Control Word - Counter 1

1

1

LSB of Count- Co'unter 1

0

'1
1

MSB of Count - Counter 1

0

Control Word - Counter 2

1

1'

LSB of Count- Counter 2

1

0

MSB of Count- Counter 2

1

0

A1

AO

Control Word - Counter 0

1

1

Control Word - Counter 1

1

1

Control Word - Counter 2

1

1
0

LSB of Count- Counter 2

1

LSB of Count - Counter 1

0

1

LSB of Count- Counter 0

0

0

MSB of Count - Counter 0

0

0

MSB of Count- Counter 1

0

1

MSB of Count- Counter 2

1

0

A1

AO

Control Word - Counter 2

1

1

Control Word - Counter 1

1

1

Control Word - Counter 0

1

1

LSB of Count - Counter 2

1

0

MSB of Count - Counter 2

1

0

LSB of Count- Counter 1

0

1

MSB of Count - Counter 1

0

1

LSB of Count- Counter 0

0

0

MSB of Count- Counter 0

0

0

A1

AO

M2

M1

MO

0

0

0

Mod~O

Control Word - Counter 1

1

1

0

0

1

Mode 1

Control Word - Counter 0

1

1

X

1

0

Mode 2

LSB.of Count- Counter 1

0

1

X

1

1

Mode 3

Control Word - Counter 2

1

1

1

0

0

Mode 4

LSB of Count - Counter 0

0

0

1

0

1

Mode 5

BCD - Binary Coded Decimal:
Binary Counter 16-bits
Binary Coded Decimal (BCD) Counter (4 Decades)
NOTE: Don't Care bits (X) should be 0 to insure compatibility with future

producls.

FIGURE 5. CONTROL WORD FORMAT

MSB of Count - Counter 1

0

1

LSB of Count - Counter 2

1

0

MSB of Count - Counter 0

0

0

MSB of Count - Counter 2

1

0

NOTE: In all four examples, all counters are programmed to Read/Wrila
two-byte counts. These are only four of many programming

sequences.
FIGURE 6. A FEW POSSIBLE PROGRAMMING SEQUENCES

5-30

82C54

DESIGN' INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

A new initial count may be written to a Counter at any time
without affecting the Counter's programmed Mode in any
way. Counting will be affected as described in the Mode
definitions. The new count must follow the programmed
count format.
If a Counter is programmed to read/write two-byte counts,
the following precaution applies: A program must not transfer control between writing the first and second byte to
another routine which also writes into that same Counter.
Otherwise, the Counter will be loaded with an incorrect
count.
Read Operations
It is often desirable to read the value of a Counter without
disturbing the count in progress. This is easily done in the
82C54.
There are three possible methods for reading the Counters.
The first is through the Read-Back command, which is
explained later. The second is a simple read operation of the
Counter, which is selected with the A1, AO inputs. The only
requirement is that the ClK input of the selected Counter
must be inhibited by using either the GATE input or external
logic. Otherwise, the count may be In process of changing
when it is read, giving an undefined result.
Counter latch Command
The other method for reading the Counters involves a
special software command called the "Counter latch
Command". Like a Control Word, this command is written to
the Control Word Register, which is selected when A1,.AO =
11. Also, like a Control Word, the SCO, SC1 bits select one
of the three Counters: but two other bits, 05 and 04, distinguish this command from a Control Word.

SCO

COUNTER

0
1
0
1

0
1
2
Read-Back Command

With either method, the count must be read according to the
programmed format; specifically, if the Counter is
programmed for two byte counts, two bytes must be read.
The two bytes do not have to be read one right after the
other; read or write or programming operations of other
Counters may be inserted between them.
Another feature of the 82C54 is that reads and writes of the
same Counter may be interleaved; for example, if the Counter is programmed for two byte .counts, the following
sequence is valid. 1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
4. Write new most signi,licant byte.
If a Counter is programmed ·to read or write two-byte
counts, the following precaution applies: A program MUST
NOT transfer control between reading the first and second
byte to another routine which also reads from that same
Counter. Otherwise, an incorrect count will be read.
Read-Back Command

The command is written into the Control Word Register and
has the format shown in Figure 8. The command applies to
the counters selected by setting their corresponding bits
03, 02, 01 = 1.

SC1, SCO.- specify counter to be latched

0
0
1
1

If a Counter is latched and then, some time later, latched
again before the count is read, the second Counter latch
Command is ignored. The count read will be the count at the
time the first Counter latch Command was issued.

The read-back command allows the user to check the
count value, programmed Mode, and current state of the
OUT pin and Null Count flag of the selected counter(sl.

A1, AO = 11; CS = 0; RO = 1; WR = 0

SCl

Counter is reprogrammed). The count is then unlatched
automatically and the Ol returns to "following" the counting
element (CE). This allows reading the contents of the Counters "on the fly" without affecting counting in progress.
Multiple Counter latch Commands may be used to latch
more than one Counter. Each latched Counter's Ol holds
its count until read. Counter latch Commands do not affect
the programmed Mode of the Counter in any way.

AO, A 1 = 11; CS = 0; RO = 1; WR = 0

OS, D4 - 00 designates Counter latch Command
X - Don't Care
NOTE: Don't Care bits (X) should be 0 to insure compatibility with future

products.

FIGURE 7. COUNTER LATCH COMMAND FORMAT

The selected Counter's output latch (Oll latches the count
when the Counter latch Command is received. This count
Is held In the latch until it is read by the CPU (or until the

5-31

D7

D6

1

1

D5

D4

D3

D2

COUNT STATUS CNT2 CNT1

D5:

0 = Latch count of selected Counter(s)

D4:
03:
D2:

0 Latch status of selected Counter(s)
1 = Select Counter 2
1 = Select Counter 1

D1:
DO:

1 = Select Counter 0
Reserved for future expansion; Must be 0

D1

DO

CNTO

0

=

FIGURE 8. READ-BACK COMMAND FORMAT

82C54

DESIGN INFORMATION

(Continued)

The Information contained in this section has been developed through characterization by Harris Semiconductor and Is for
.
use as application and design Information only. No guarantee.is implied.
The read-back command· may be used to latch multiple
counter output latches (Ol) by setting the COUNT bit
05
0 and selecting the desired counter(s). This single.
command is .functionally equivalent to several counter latch
com~ands, one for each counter latched. Each counter's
latched count Is Iield until It Is r~ad (or the counter Is
reprogrammed). That counter is automatically unlatched
when read, but other counters remain latched· until they are
read. If multiple count read-back commands are Issued to
the same counter without reading the count, all but the first
are ignored; I.e., the count"which will be read is the count at·
the time the first read-back command was Issued.

=

Definitions, but until the counter Is loaded into the counting
element (CE), it can't be read from the counter. If the count
Is latched or read before this time, the count value will not
reflect the new· count. just written. The operatiqn of Null
Count is shown in Figure 10.
THIS ACTION:

CAUSES:

A. Write to the control word register: (1) .•..•.... Null Count = 1

B. Wrlte to the count register (CR): (2) •.•••• , •••• Null Count';' 1
C. New count is loaded Into'CE (CR - CE) .....•• NuliCount=O

The read-back command may also be used to latch status
information of selected couriter(s) by setting STATUS bit 04
== O. Status must be latched to be read; status of a Counter Is
accessed by a read from that counter.

(1) Only the counter specified by the control word will have its null
count set to 1. Null count bits of other counters are unaffected.
(2) If the counter Is programmed for two-byte counts (least slgnifi·
cant byte then most significant byte) null count goes to 1 when
the second byte is wri!len.

The counter status format is shown in Figure 9. Bits 05
through DO co~taln the counter's programmed Mode exactIy as written in the last Mode Control Word. OUTPUT bit 07
contains the current state of the OUT pin. This allows. the
user to monitor the counter's output via software, 'pqssibly
eliminating some hardware from a system.

If multiple status latch operations of the counter(s) are
performed without reading the status, all but the first are
Ignored; Le., the status that will be read Is the status of the
counter at the time the first status read-back command was
issued.

07

06

OUTPUT

NUll
COUNT

05

04

RW1 RWO

03

02

01

00

M2

M1

MO

BCD

071 = Outpinls1
0=· OutpinisO
06 1 = 'Null count
o = Count.available for reading
OS-DO = Counter programmed mode (See Figure 5)
FIGURE 9. STATUS BYTE
'NUll COUNT bit 06 Indicates when the last count written
to the counter .register (CR) has been loaded into the counting element (CE). The exact time this happens depends on
the Mode of the counter and is described in the Mode

FIGURE 10. NULL COUNT OPERATION

Both count and status of the selected counter(s) 'may tie
latched simultaneously by setting both COUNT and
STATUS bits 05, 04
O. This is functionally the same as
Issuing two separate read-back commands at once, anc;!
the above discussions apply here also. Specifically, if multipie count andlor status read-back commands are issued to
the same counter(s) without allY Intervening reads, all but
the first are ignored. This is Illustrated in Figure 11. If both
count and status of a counter are latched, the first read
operation of that counter will return latched status, regardless of which was latched first. The next one.or two reads
(depending on whether the counter Is' programmed for one
or two type counts) return latched count. Subsequent reads
return unlatched count.

=

COMMAND
07

06

05

04

03

02

·01

00

1

1

0

0

0

0

1

0

Read Back Count and Status
of Counter 0

DESCRIPTION

Count and Status latched for
Counter 0

1

.1

1

0

0

1

0

0

Read-Back Status of Counter 1

Status latched for Counter 1

1

1

1

0

1

1

0

0

Read-Back Status of
Counters 2, 1

RESULT

"

Status latched tor Counter 2,
But·Not Counter 1

1

1

0

1

1

0

'0

0

Read-Back Count of Counter 2

Count Latched for Counter 2

1

1

0

0

0

1

0

0

Read-Back COUlJt and Status of
Counter 1

Count Latched for Counter 1
But Not Ststus

1

1

1

0

0

0

1

0

Read-Back Status of Counter 1

Command Ignored, Status
.Already latched for Counter 1

FIGURE 11. READ-BACK COMMANO EXAMPLE.

5:-32.

82C54

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

0

1

0

0

0

Write into Counter 0

This allows the counting sequence to be synchronized by
software. Again OUT does not go high until N + 1 elK
pulses after the new count of N is written.

0

1

0

0

1

Write into Counter 1

If an initial count is written while GATE = 0, it will still be

0

1

0

1

0

Write into Counter 2

0

1

0

1

1

Write Control Word

0

0

1

0

0

Read from Counter 0

Mode 1: Hardware Retrlggerable One-Shot

0

0

1

0

1

Read from Counter 1

0

0

1

1

q

Read from Counter 2

0

0

1

1

1

No-Operation (Three-State)

1

X

X

X

X

No-Operation (Three-State)

OUT will be initially high. OUT will go low on the ClK pulse
following a trigger to begin the one-shot pulse, and will
remain low until the Counter reaches zero. OUT will then
go high and rer:nain high until, the ClK pulse after the next
trigger.

0

1

1

X

X

No-Operation (Three-State)

CS

RD

WR

A1

AO

loaded on the next ClK pulse. When GATE goes high, OUT
will go high N ClK pulses later; no ClK pulse is needed to
load the counter as this has already been done.

FIGURE 12. READ/WRITE OPERATIONS SUMMARY

Mode Definitions
The following are defined for use in describing the operation
of the 82C54.
ClK PULSE:
A rising edge, then a falling edge, in that order, of a Counter's ClK input.
TRIGGER:
A rising edge of a Counter's Gate input.

After writing the Control Word and initial count, the Counter
is armed. A trigger results in loading the Counter and setting
OUT low on the next ClK pulse, thus starting the one-shot
pulse N ClK cycles in duration. The one-shot is
retriggerable, hence OUT will remain low for N ClK pulses
after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no
effect on OUT.
If a new count is written to the Counter during a one-shot
pulse, the current one-shot is not affected unless the Counter is retriggered. In that case, the Counter is loaded with the
new count and the one-shot pulse continues until the new
count expires.
Mode 2: Rate Generator

COUNTER LOADING:
The transfer of a count from the CR to the CE
(See "Functional Description")
Mode 0: Interrupt on Terminal Count
Mode 0 is typically used for event counting. After the
Control Word is written, OUT is initially low, and will remain
low until the Counter reaches zero. OUT then goes high and
remains high until a new count or a new Mode 0 Control
Word is written to the Counter.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.
After the Control Word and initial count are written to a
Counter, the initial count wi/l be loaded on the next ClK
pulse. This ClK pulse does not decrement the count, so for
an initial count of N, OUT does not go high until N + 1 ClK
pulses after the Initial count is written.
If a new count is written to the Counter it wi/l be loaded on
the next ClK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
(1) Writing the first byte disables counting. Out is set low
immediately (no clock pulse required).
(2) Writing the second byte allows the new count to be
loaded on next ClK pulse.

This Mode functions like a divide-by-N counter. It is typical'Iy used to generate a Real Time Clock interrupt. OUT will
initially be high. When the initial count has decremented to
'1, OUT goes low for one ClK pulse. OUT then goes high
again, the Counter reloads the initial count and the process
is repeated. Mode 2 is periodic; the same sequence is
repeated indefinitely. For an initial count of N, the sequence
repeats every N ClK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low during an output pulse, OUT is set high
immediately. A trigger reloads the Counter with the initial
count on the next ClK pulse; OUT goes low N ClK pulses
after the trigger. Thus the GATE input can be used to
synchronize the Counter.
After writing a Control Word and initial count, the Counter
will be loaded on the next ClK pulse. OUT goes low N ClK
pulses after the initial count is written. This allows the Counter to be synchronized by software also.
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after writing a new count but before the end of the current period, the
Counter will be loaded with the new count on the next ClK
pulse and counting will continue from the new count. Otherwise, the new count wi/l be loaded at the end of the current
counting cycle.

5-33

82C54

DESIGN INFORMATION

(Continued)

The Information contained In this section has been developed through characterization by Herrls Semiconductor and is for
use as application and design Information only. No guarantee Is Implied.

CW=10

CW=t2

LSB=4

WR~r-------~-------

elK

elK

GATE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OUT

LSB_3 ____________________________

Wii~

==--''-_______---'

I

N·I N

1N 1

CW = 10

N

GATE

I I I
FF

I

FF

------in---------~rc=

OUT

FF

FE

lSB. 3_________________________

WR~

CW=t2

WII

elK

lSB=3,-___________________________

LJl..J

elK
GATE

GATE

I ~ I~ I

OUT

-------;n ----1n---------=.:J

,'--------',I I

I I I I I I~ I I
N

N

N

N

N

g

0

elK
elK

GATE

OUT

=:J~

_______________~r__

GATE

-------;n--------irr-----

OUT

I I I

NOTE: The following convenUons apply to all mode timing diagrams.

FF
FF

1. Countara are programmed for binary (not BCD) counUog and for
readlngiwrftlng least slgnillcit.nt byte (LSB) only.
2. The counter Is always selected

(CS always low~
FIGURE 14. MODE 1

3. CW stands for "Control Word"; CW - 10 means a control word of
10, Hex Is wriften to the counter.
4. LSB .tands for Least sign Incant "byte" 01 count

5. Numbers below diagrams are count values. The lower number is
the least SignifICant byte. The upper number Is the most slgnKIcanI
byte. Sines the counter Is programmed to read/write LSB only, the

mast significant byte cannot be read.

e.

N stands for an undefined count.

7. Veliicallinas show lransHions between count values.

AGURE 13. MODE 0

5-34

FF
FE

82C54

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee Is implied.

Mode 3: Square Wave Mode
Mode 3 is typically used for Baud rate generation. Mode 3 is
similar to Mode 2 except for the duty cycle of OUT. OUT will
initially be high. When half the initial count has expired, OUT
goes low for the remainder of the count. Mode 3 is periodic;
the sequence above Is repeated Indefinitely. An initial count
of N results in a square wave with a period of N ClK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low while OUT Is low, OUT is set high
immediately; no ClK pulse Is required. A trigger reloads the
Counter with the initial count on the next ClK pulse. Thus
the GATE input can be used to synchronize the Counter.
After writing a Control Word and initial count, the Counter
will be loaded on the next ClK pulse. This allows the Counter to be synchronized by software also.

CW:::14

Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing
a new count but before the end of the current half-cycle of
the square wave, the Counter will be loaded with the new
count on the next ClK pulse and counting will continue
from the new count. Otherwise, the new count will be
loaded at the end of the current half-cycle.
Mode 3 Is Implemented as Follows:
EVEN COUNTS: OUT is initially high. The Initial count is
loaded on one ClK pulse and then is decremented by two
on succeeding ClK pulses. When the count expires, OUT
changes value and the Counter is reloaded with the initial
count The above process is repeated indefinitely.

LSB=3

~~-----------------

elK
CW .. 16

lSB=4

"R~

GATE - - - - - - - - - - - - - - - - -

aUT

ClK

G,UE - - - - - - - - - - - - - - - - - - OUT

CW",14

LSB.,3.-_ _ _ _ _ _ _ _ __ _

~~
CW=16

elK

LSB=5

r

_ _ _ _ _ _ _ _ _ _ _ _ __

w-.~

GATE

elK

aUT~

CW=16

WIi

"""""L.JU
ClK

elK

GATE

LSB=4r-_ _ _ _ _ _ _ _ _ _ _ __

-----------------

aUT~

I I I I I
N

N

N

N

U
I~ I ~ I~

OUT

IHIHINIHI:I~I:I~I~I~I

FIGURE 15. MODE 2

FIGURE 16. MODE 3

5-35

82C54

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

ODD COUNTS: OUT is Initially high. The Initial count is
loaded on one ClK pulse, decremented by one on the next
ClK pulse, and then decremented by two on succeeding
ClK pulses. When the count expires, OUT goes low and the
Counter is reloaded with the initial count. The count Is decremented by three on the next ClK pulse, and then by two
on sucCeeding ClK pulses. When the count expires, OUT
goes high again and the Counter is reloaded with the initial
count The above process is repeated Indefinitely. So for
odd counts, OUT will be high for (N + 1)/2 counts and low
for (N - 1)/2 counts.
Mode 4: Software Triggered Mode
OUT will be initially high. When the initial count ex'pires,
OUT will go 'low for one ClK pulse then go high again.
The counting sequence is "Triggered" by writing the initial
count.
GATE = 1 enables counting; GATE = 0 disables counting.
GATE has no effect on OUT.

CW=18

After writing a Control Word and Initial count, the Counter
will be loaded on the next ClK pulse. This ClK pulse does
not decrement the count, so for an initial count of N, OUT
does not strobe low until N + 1 ClK pulses after the initial
count is written.
If a new count is written during counting, it will be loaded on
the next ClK pulse and counting will continue from the new
count. If a two-byte count is written, the following happens:
(1) Writing the first byte has no effect on counting.
(2) Writing the second byte allows the new count to be
loaded on the next ClK pulse. '
This allows the sequence to be "retriggered" by software.
OUT strobes low N + 1 ClK pulses after the new count of N
is written.
Mode 5: Hardware Triggered Strobe (Retriggerabie)
OUT will initially be high. Counting is triggered by a rising
edge of GATE. When the initial count has expired, OUT will
go low for one ClK pulse and then go high again.
CW=1A

LSB",3

eLK

eLK

GATE
GATE

OUT

LSS=3j-_ _ _ _ _ _ _ _ __

WlILJU

Wl\~r---------

u

=.=J
o1
CW=18

-------1 rr--------lrc=

OUT

I I I I I
0
0

FF
FF

FF
FE

FF
FO

LS8=3_ _ _ _ _ _ _ _ _ _ __

CW=1A

WI!~

Lsa .. 3r-_ _ _ _ _ _ _ _ _ _ __

WiiLJU
eLK

eLK

GATE

GATE

OUT~

0

FF
FF

eLK
GATE

GATE - - - - - - - - - - - - - - - - -

OUT

ININININI:I~I:I~I

-------lfCl[\------------

INI" ININI"INI:I

I I I
0

-

OUT~

LJ
o1

-

I:I~~I

--------1n---------- 1,rc==
~

u

I " I NI " I NI " I : I : I : I ~ I ~~ I i~ I
FIGURE 18. MODE 5

FIGURE 17. MODE 4

5-36

82C54

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
After writing the Control Word and initial count, the counter counting, and continues counting. Modes 2 and 3 are
will not be loaded until the ClK pulse after a trigger. This. periodic; the Counter reloads itself with the initial count and
ClK pulse does not decrement the count, so for an initial continues counting from there.
count of N, OUT does not strobe low until N + 1 ClK pulses
after trigger.
SIGNAL
LOW
STATUS
OR GOING
A trigger results in the Counter being loaded with the initial
LOW
RISING
MODES
HIGH
count on the next ClK pulse. The counting sequence is
triggerable. OUT will not strobe low for N + 1 ClK pulses
Disables
0
Enables
after any trigger. GATE has no effect on OUT.
counting
counting
If a new count is written during counting, the current cou'nting sequence will not be affected. If a trigger occurs after
the new count is written but before the current count
expires, the Counter will be loaded with the new count on
the next ClK.pulse and counting will continue from there.

-

1

-

1) Initiates
counting
2) Resets output

after next clock
1) Disables

2

Operation Common to All Modes

counting

Initiates

Enables

2) Sets output

counting

counting

Initiates
counting

Enables
.counting

-

Enables
counling

Initiates
counting

-

immediately
high

Programming

1) Disables

3

When a Control Word is written to a Counter, all Control
logic is immediately reset and OUT goes to a known initial
state; no ClK pulses are required for this.

counting
2) Sets output

immediately
high

Gate

1) Disables

4

The GATE input is always sampled on the rising edge of
ClK. In Modes 0, 2, 3 and 4 the GATE input is level sensitive, and logic level is sampled on the rising edge of ClK. In
modes 1, 2, 3 and 5 the GATE input is rising-edge sensitive.
In these Modes, a rising edge of Gate (trigger) sets an
edge-sensitive flip-flop in the Counter. This flip-flop is then
sampled on the next rising edge of ClK. The flip-flop is
reset immediately after it is sampled. In this way, a trigger
will be detected no matter when it occurs - a high logic level
does not have to be maintained until the next rising edge of
ClK. Note that in Modes 2 and 3, the GATE input is both
edge-and level-sensitive.

counting

-

5

FIGURE 19. GATE PIN OPERATIONS SUMII.\ARY
~

",;:2

MIN
COUNT

MAX
COUNT

0

1

0

a..

Counter
New counts' are loaded and Counters are decremented on
the falling edge of ClK.
The largest possible initial count is 0; this is equivalent to
2 16 for binary counting and 104 for BCD counting.
The counter does not stop when it reaches zero. In Modes
0, 1, 4 and 5 the Counter "wraps around" to the highest
count, either FFFF hex for binary counting or 9999 for BCD

MODE

ow
:;:'"
<.>!!::
a:
w

NOTE: 0

5-37

1

1

0

2

2

0

3

2

0

4

1

0

5

1

0

is equivalent to 216 for binary counting and 104 for BCD counting.

FIGURE 20. MINIMUM AND MAXIMUM INITIAL COUNTS

Em HARRIS

82C55A/883
CMOS Programmable
Peripheral Interface'

June 1989

Description

Features

• This Circuit is Processed in Accordance. to Mil":Std- The Harris 82C55N883 is a high performance CMOS
883 and is fully Conformant Under the Provisions of. version, of the industry standard 8255A and is manufac·
tured using a self-aligned silicon gate CMOS process
Paragraph 1.2.1
(Scaled SAJI IV). It is a general purpose programmable I/O
• Pin Compatible with NMOS 8255A
device which may be used with many· different
• 24 Programmable I/O Pins
microprocessors. There are '24 ·1/0 pins which may be
• Fully TTL Compatible
Individually programmed In 2 groups of 12 and used in 3
• High Speed, No "Wait State" Operation with 5MHz major modes of operation. The high performance and
industry standard configuration of the 82C55N883 make it
and 8MHz 80C86 and 80C88
compatible with the 80C86, 80C88 and other
• Direct Bit Set/Reset Capability
microprocessors.
• Enhanced Control Word Read Capability
Static CMOS circuit design insures low operating power.
• Scaled SAJI IV CMOS Process
TIL compatibility over the 'full military temperature range
• 2.5mA Drive Capability on All 1/0.Ports
and bus hold circuitry eliminate the need for pull-up resis• Low Standby Power -ICCSB .••• , •.••••••••• _. lOIlA tors. The Harris advanced SAJI process results in perform• Military Operating Temperature ••• -550 C to +1250C ance equal to or greater than existing functionally equivalent products at a fraction of the power.
Range

Pinouts

82C55A1883 (CERAMIC DIP)
TOP VIEW

82C55A1883 (LCC)
TOP VIEW

~ ~ ~ ~ ~

i l

~ ~

t!J l~J l~J :.!,; L2J i.!j ~ ._
GNO

PA2

!]

NC

N.C ~l
A1 ~]
AD
PC7

PC6

RESET

DO

19]
(iJ
@

01

02
03

1~J
PC4 1~
PCO I~
PCl 101

04

PC2 171

NC

PC5

05

....

06
07

~ ~ ~ ~ ~

f

~ ~ ~ ~ ~

PIN NAMES
PIN
07-08
Reset
CS

AD

PBS.

WR
AO,A1
PA7-PAO
PB7-PBO
PC7-PCO
VCC'
GNO'

PB5
PB4
PB3

DESCRIPTION
Oata Bus (Bi-directional)
Reset Input
ChipSelecl
Read Input
Write Input
Port Address
PortAIBit)
Port B (Bit)
PortCIBit)
+5 Volts
oVolts

• A 0.1 pF decoupllng capacitor from Ihe VCC pIn 10
the GND pin is recommended.
Copyrighl

© Harris Corporalion 1989

5-38

82C55A/883
Pin Description
SYMBOL

DIPPIN
NUMBER

VCC

26

TYPE

DESCRIPTION
VCC: the +5V power supply pin. A 0.1 ~F capacitor between pins 26 and 7 is
recommended for decoupling.
GROUND

GND

7

DO-D7

27-34

1/0

RESET

35

I

RESET: A high on this input clears the control register and all ports CA, B, C) are set to
the input mode with the "Bus Hold" circuitry turned on.

CS

6

I

CHIP SELECT: Chip select is an active low input used to enable the 82C55N883 onto the
Data Bus for CPU communications.

RD

5

I

READ: Read is an active low input control signal used by the CPU to read status
Information or data via the data bus.

WR

36

I

WRITE: Write is an active low input control signal used by the CPU to load control words
and data into the 82C55N883.

AO-A1

8,9

I

ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the
selection of one of the three ports or the control word register. AO and A 1 are normally
connected to the least significant bits of the Address Bus AO, A 1).

PAO-PA7

1-4,37-40

I/O

PORT A: 8 Bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.

PBO-PB7

18-25

I/O

PORT B: 8 Bit input and output port. Bus hold high circuitry is.present on this port.

PCO-PC7

10-17

110

PORT C: 8 Bit input and output port. Bus hold high circuitry is present on this port.

DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.

Functional Description
POWER { _ ..v
_GNU

GROUP
A

SUPPLIES

GROUP

PORT

•

CONTROL I'v---~

A

t"

liD
I\r----r--./ PC7-PC4
BI-DIRECTIONSL
DATA BUS

07-00 """'--'1/1

DATA
8US
BUffER

8-BIT

INTERNAL
DATA BUS

liD
","~_--./PCl-

PCo

iiii
Wii

"

GROUP

CON~ROL J'v----,

GROUP
8
PORT

8

AD

t"

RESET

cs-----'

5-39

liD
1V----r-'1/PB1-PBQ

Specifications 82C55A/883
Absolute Maximum Ratings

Reliability Information

Sup"i,ly Voftage •••••...••••.•....••••••.•••...•••. :: ..• +8.0V
Input, Output or I/O Voltage Applied. • • •• GND-0.5V to VCC+0.5V
Storage Temperature Range •••••.•.••.•...•. -650C to +1500 C
Junction Temperature .•••••......••••.••.•..••.•••••• +1750 C
Lead Temperature (Soldering 10 sec) ••••.••••.• ,.•••.••• +3000C
ESD Classification
.•.••...•.•.•.•.•••••••••.••••••••••
Class 1
,
.

Thermal Resistance
0ja
Geramic DIP Package. • • . . • • • . • • • • • . • .
40 0CIW
, Ceramic LCC Package. • . • • • • • • • • • • . • .
700 CIW
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ..••••••.•.•••.••••••••.••••. ." •. 1.23W
Ceramic LCC Package .••.••••..•.••••...•........•. 718mW
Gate Count ...•••.••.•••••••..•••.•••••.••••..••• 1000 'Gates

CAUTION: Stresses above those listed in '''Absolute Maximum ffatings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any olher,condWons above those Indicated in,.,he operational seclion~ of this specification is not implied.
.

Operating .conditions' .
Operating Temperature Range •...•••.•••••. : -550C to +1250C
Operating Supply Voltage .....••••••.•••••.•••• +4.5V to +5.5V
TABLE 1. ' 82C55A!883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

Logical "1" Input Voltage

VIH
VIL

Logical "0" Input Voltage
Output HIG H Voltage

Output LOW Voltage

VOH

VOL

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

VCC=5.5V

1,2,3

-550C!£TA~+1250C

2.2

-

V

VCC=4.5V

1,2,3

-550C !£ TA !£ + 1250C

-

0.8

V

VCC=4.5V;
IOH=-2.5mA
10H = -100VA (Note 2)

1,2,3

-55°C ~ TA:S. +1'250 C

-

V

VCC=4.5V,
10L = 2.5mA (Note 2)

;1,2,3

-550C~TA~ +125 0C

-

0.4

V

CONDITIONS

'3.0
VCC-O.4

Input Leakage Current

II

VCC=5.5V,
VIN=GNDorVCC
DIP Pins: 5, 6, 8, 9,
35,36

1,2,3

-550 C!£TA:S.+1250C

-1.0

+1.0

vA

Output Leakage Current

10

VCC=5.5V,
VIN=GNDorVCC
DIP Pins: 27 - 34

1,2,3

-550C :S.TA!£ +1250C

-10

+10

vA

Bus Hold High Current

IBHH

VCC = 4.5V and 5.5V
VOUT= 3.0V,
PorisA,B,C

1,2,3

-550C~TA:S.+1250C

-50

-400

VA

Bus Hold Low Current

IBHL

VCC = 4.5V and 5.5V
VOUT=1.0V,
PortA Only

1,2,3

-550 C:S.TA:S.+1250C

+50

+400

pA

Darlington Drive
Current

IDAR

VCC = 4.5V, VIN = VCC
or GND, Outputs Open
VOUT=VCC,
Ports A, B, C (Note 3)

1,2,3

-550 C:S.TA:S.+1250C

-2.0

(Note 1)

mA

ICCSB

VCC = 5.5V, VIN = VCC
or GND, Outputs Open

1,2,3

-550C:S.TA:S.+1250C

-

10

vA

SiI1>ndby Power Supply
Current

NOTES: 1. No Internal current limiting resistor exists on Port Outputs. A resistor must be added externally to limit the current.
2. Interchanging of forca and sense condilians Is parmiHed.
3. Tested using Test Conditions 3 in Test Condition OefinKion Table.

CAUTION: These devices are sensilive to electronic discharge. Proper I.C. handling procedures should be followed.

5-40

Specifications 82C55A/883
TABLE 2. 82C55AJ883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
TIMING REQUIREMENTS
LIMITS

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

82C55A-5/883

82C55AJ883

READ TIMINGS
Address Stable
Before READ

TAR(1)

9.10,11

-550C :S.TA:S.+125 0 C

0

-

0

-

ns

Address Stable
After READ

TRA(2)

9,10,11

-55°C :S.TA~ +125 0 C

0

-

0

-

ns

9,10,11

-550C~TA

250

-

150

-

ns

9,10,11

-550C ----'1

(NOTE 1)

IBf

PERIPHERAl _ _ _ _ _ _ _ _ _ _
BUS

iiii
DATA FROM
PERIPHERAL TO 82C55A

DATA FROM
82C55A TO CPU

NOTE: 1. Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(INTR = IBF • MASK • STIi • iiD • 0ilF • MASK • AcK • WR)

WRITE TIMING

AO-l. CS

DATA BUS

READ TIMING

=::X

!:= WI

¥--=--i y-

-1

-----I

-------,t~

AO-1. Cs

1: ~~

=::::XE

Y

' - - - ,- R - - - - - - - - ' l l . : 'RA(2)

AD ______~1~_~1~~~------

P'DW-1-'WD:J,~

(4)'RD

------------~~

DATA BUS

IWW

r-

IMPEDANCE?

(9)

5-44

'Df(5)

~~~~~~~~~~V~~~LI~D~II~~
~ HIGH

82C55A/883
AC Test Circuit ,

ACTesting Input, Output Waveform
Vl

-+__.....__-o TEST

~1.5V

1.5V~

FROM OUTPUTo-_ _
UNDER TEST

OUTPUT
VOH

INPUT
V1H +0.4V

POINT

VOL

V1L -0.4V

AC Testing: All parametqrs tested as per test circuits. Input rise and fall
.
times are driven at 1 nsN

·Includes Stray and Jig Capacitance

TEST CONDITION DEFINITION TABLE
TEST CONDITIONS

Vl

Rl

R2

Cl

1

1.7V

5230

Open

150pF

2

vee

2kO

1.7kO

50pF

3

1.5V

7500

Open

50pF

Burn-In Circuits
82C55A1883 CERAMIC DIP

82C55A1883 CERAMIC; LCC

F7'-..JVIII.---l
Fe'-..JVIII.---l
F9'-..JVIII.---l
F4--,\fIh-l

t~8

GND

~!8
,-

F3,-..JVIII.---l
GND----t.:~

FO

l~7

fl
Fl-..JVIII.---l
F1D--J\fIh-i
Fe,-..JVIII.---l
F7-..JVIII.---l
Fa'-..JVVI.---l
F9-..JVVI.---l

'2J
1~]

Fe

-.
'1J
'3-,
-.
I!J

Fa

1~]

FlO
Fe

1

F7

FlO

1~1

Fe

I!]

-,

F1D--J\f\h--l
FB'-..JVIII.---l
F7'-..JVIII.---l

F91-..JVIII.---l
F1D--,\fIh-l

vee =5.5V :!: 0.5V
VIH = 4.5V :!: 10%
VIL = -0.2V 10 0.4V
GND = OV

C1 = O.01pF minimum
All resistor. are 47kO :!: 5'!b
10 - 100kHz:!: 10%
11 - fO + 2; 12 '. 11 + 2: •.. : 115 = 114 + 2

5-45

FS
FIS

i!a .

Fl1

[!5

F12

r,"

,-r;3

[!2

I!,
,'"
l!9

F13
F14
FIS
Fl1
F12 '

!3

mal!
....

0

::;;:C

... 2:

....
....

II:

82C55A/883
Metallization Topology
DIE DIMENSIONS:
131.4 X 167.7 X 19 ±1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kA ± 1kA
GLASSIVAnON:
Type: Si02
Thickness: 8kA ± 1kA
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy (LCC has Gold Preform)
Temperature: Ceramic DIP - 46()oC (Max)
Ceramic LCC - 4200 C (Max)
WORST CASE CURRENT DENSITY:
0.78 x 105 Alcm 2

Metallization Mask Layout
82C55A1883

RESET

cs

DO

GNO

Al

01

02
PC7
03

PC6
04
PAS
05

06

PCl

P03

PBO

PBl

PB2

PB3

5-46

PB4

PB6

PB7

80C55A/883
Packaging t
40 PIN CERAMIC DIP
2.035

~

I

2.096

.160

,..----

J

.125

o·
15'

.098 MAX

.180~'

.~~~

.023
.050'
• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FiNISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± lOoC
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-5

44 PAD CERAMIC LCC
BOTTOM VIEW

.643
.662

.045
.055

.050

sse

~
1 - - - - - - .662

.

-------1---1

.063

. ::!..I m7

Ilnnnnnnnnnnnll
.073n
.089

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic. 90% Alumina
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 320 0 C ± lOoC
Method: Furnace Braze

NOTE: All Dimensions are

..M!!!...
. Dimensions are in inches.
Max

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-5

tMiI-M-38510 Compliant Materials, Finishes, and Dimensions.

5-47

82C55A·

ml-lARRIS
DESIGN INFORMATION

CMOS Programmable
Peripheral Interface

The Information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design Information only. No guarantee is implied.

Functional Description
Data Bus Buffer
This three-state bi-directional 8 bit buffer is used to
interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or
output instructions by the CPU. Control words and status
information are also transferred through the data bus buffer.
Read/Wrlte and Control I.,oglc
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control
Groups.
(CS) Chip Select. A "low" on this input pin enables the
communication between the 82C55A and the CPU.
(RD) Read. A "low" on this input pin enables the 82C55A to
send the data or status information to the CPU on the data
bus. In essence, It allows the CPU to "read from" the
82C55A.
. (WR) Write. A "low" on this input pin enables the CPU to
write data or control words into the 82C55A.
(AO and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR Inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant bits of the address bus (AO and A 1).
82C55A BASIC OPERATION

A1

AO

RD

0

0

0

0
0

WR

CS

0

INPUT OPERATION
(READ)
PortA .. Data Bus

0

0

Port B .. Data Bus

0

0

Port' C .. Data Bus

0

0

Control Word .. Data Bus
OUTPUT OPERATION
(WRITE)

0

0

0
0

0

0

Data Bus .. Port A

0

0

Data Bus .. Port B

0

0

Data Bus .. Port C

0

0

Data Bus .. Control
DISABLE FUNCTION

X

Data Bus .. Three-State

X

Data Bus .. Three-State

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READIWRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS

(RESET) Reset. A "high" on this input clears the control
register and aU ports (A, B, C) are set to the input mode.
"Bus hold" devices internal to"the 82C55A will hold the I/O
port inputs to a logic "1 '~ state with a maximum hold current
of 400JlA.
Group A and Group B Controls
The functional configuration of each port is' programmed by
the systems software. In 'essence, the CPU "outputs" a
. control word to the 82C55A. The control word contains
information such as "mode", "bit set", "bit reset", etc., that
initializes the functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts
"commands" from the Read/Wrlte Control Logic, receives
"control words" from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port Clower (C3 - CO)
The control word register can be both written and read as
shown in the "Basic Operation" table. Figure 4 shows the
control word format for both· Read and Write operations ..
When the control word is read, bit 07 will always be a logic
"1", as this implies control word mode information.

5-48

82C55A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Ports A, Band C
The 82C55A contains three 8 bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has its own special
features or "personality" to further enhance the power and
flexibility of the 82C55A.

selected using a singie output instruction. This allows a
single 82C55A to service a variety of peripheral devices
with a simple software maintenance routine.
ADDRESS BUS
CONTROL BUS

Port A One 8 bit data output latch/buffer and one 8 bit data
input latch. Both "pull-up" and "pull-down" bus-hold devices are present on Port A. See Figure 2a.
Port BOne 8 bit data input/output latch/buffer and one 8
bit data input buffer. See Figure 2b.
Port COne 8 bit data output latch/buffer and one 8 bit data
input buffer (no latch for input). This port can be
divided into two 4 bit ports under the mode control. Each 4
bit port contains a 4 bit latch and it can be used for the control
signal outputs and status signal inputs in conjunction with
ports A and B. See Figure 2b.

a)

MODE'

---I.~o--~;o::::::!:=;~---..,~~
PB,-PSO

MODE 1

o~~J~~~3RDCONnIOL

PCl-PCO

:t.

~o

PBl-FHO

PC1-PC4

1
go
III!
A

1111

CONTROL
DR 110

CONTROL
OR 110

PA1·PAa

CHANGE

INTERNAL
DATA IN

~~~~R~~

EXTERNAL
PORT A PIN

MODE 2

----------1 ~()-----'

:r •
~o 111.1 1111
PB7-PBO

i

A

1

::t::).-OIRECTIDNAl
PA7-PAa

CONTROL

WD CONTROL

FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
CONTROL WonD

lO'jo. 0', d.' 0', 0', 0, ,0, ,

vcc

b)

~

L~

GROUPB

INTERNAL
EXTERNAL
DATA IN - -....-<>-----I
WR SIGNAL

PORT C (LOWER)
1 =INPUT
0- OUTPUT

'-

-

\

PORTB

I-INPUT
O=OUTPUT

MODE SELECTION
a"MOOEO

FIGURE 2. PORT A & B, PORT C BUS-HOLD CONFIGURATION

'=MODE I

Operational Description
Mode Selection
There are three basic modes of operation than can be
selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus
When the reset input goes "h igh", all ports will be set to the
input mode with all 24 port lines held at a logic "one" level
by internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional
initialization required. This eliminates the need to pullup or
pulldown resistors in all-CMOS designs. During the execution of the system program, any of the other modes may be

5-49

/

GROUP A

PDRTCiUPPEnl
1 = INPUT
D=OUTPUT

ponr A
I-INPUT
Q= OUTPUT

MODE SELECTION
OO=MODEO
Ol-MODE 1
lX=MODE2

MODE SET FLAG
'=ACTIVE

FIGURE 4. MODE DEFINITION FORMAT

en a:
OW
:;;:C
<->!!::
a:
W

Co.

82C55A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and Is for
use as application and design Information only. No guarantee Is implied.

The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be "tailored" to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display
computational results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis.
The mode definitions and possible mode conbinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach
will surface. The design of the 82C55A has taken into
account things such as efficient PC board layout, control
signal definition vs. PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the
available pins.
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single OUTput instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit SeVReset
operation just as if they were data output ports.

signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using
the bit seVreset function of port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition:
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is RESET - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode selection and
device Reset.

Operating Modes
Mode 0 (Basic InpuVOutput). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply
written to or read from a specific port.
Mode 0 Basic Functional Definitions:
• Two 8 bit ports and two 4 bit ports
• Any Port can be input or output
• Outputs are latched
• Input are not latched
• 16 different InpuVOutput configurations possible
MODE 0 PORT DEFINITION
A

B
D3

0

0

0

0

Output Output 0 Output Output

0

0

0

1

Output Output 1 Output

0

0

1

0

Output Output 2

0

0

1

1

Lr

BIT SET/RESET

'-5ET

0- RESET

BIT SELECT
0123.587
0101010180

o0

1 1 0 0 1 1

GROUPB

PORTC
PORTC
DO PORTA (Upper) # PORTB (Lower)

D4
CONTROL WORD

D1

GROUP A

8,1

Input

Input

Output

Output Output 3

Input

Input

Input

4

Output Output

0

1

0

0

Output

0

1

0

1

Output

Input

5

Output

Input

Input

6

Input

Output

Input

7

Input

Input

0

1

1

0

Output

0

1

1

1

Output

1

0

0

0

Input

Output 8 Output Output

0000""821

1

0

0

1

Input

Output 9

1

0

1

0

Input

Output 10 Input

1

0

1

1

Input

Output 11

1

1

0

0

Input

Input

12 Output

Interrupt Control Functions

1

1

0

1

Input

Input

13 Output

When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request

1

1

1

'0

Input

Input

14

Input

Output

1

1

1

1

Input

Input

15

Input

Input

L _ _ _ _ _ _ _ _ _ _ _ _ 11 BITSET/RESETFLAG
a-ACTIVE

I

FIGURE 5. BIT SET/RESET FORMAT

5-50

Output

Input

Input
Output
Input
Output
Input

82C55A

DESIGN INFORMATION

(ContInued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design Information only. No guarantee is implied.
MODE 0 (Basic Input)

_ _ _ _ _ _ _ _ _ _ _"\.~---IRR----I~L~----------'iiii

INPUT

CS.A1.AO

O---- -- - - --

01- D

IOF

MODE 0 (Basic Output)

..lr

WR

-

.,Ftwo

I---'OW
OJ-DO

twA

'AW
Cs,A1,AD

)(

OUTPUT

-twB------l

MODE 0 CONFIGURATIONS
CONTROL WORD _2

CONTROL WORD_O
~D.DsD4~D2D,DO

07

0

D.

Os

04

D3

DZ

D,

Do

I I I I I I I 11

I' I I I I I I I I

~

0

I

0

<1

,

pc,}

--I-

07 0, 05 D. OJ 02 D, Do

I

L.

. - 1· INPUT
O· OUTPut

r---

pc. s
'-INPUT
O-OUTPUT

RD-

P C , - O B Fa

Pea

PClr--INTA"

I, I· ':. ".:' , txl

110

pc. 5

r--f--

110

PB7PBa~
PC'I--- m"

INTRa

PQRT A· ISTROBEO INPUT!
PORT B . 'STROBED OUTPun

PORT A - !STR08EO OUTPUT!
PORT a -ISTR08ED INPUT!

FIGURE 10. COMBINATIONS OF MODE 1
Combinations of Mode 1: Port A and Port B can be individually
defined as input or output in Mode 1 to support a wide variety of
strobed 1/0 applications.

Operating Modes
Mode 2 (Strobed BI-dlrectlonal Bus I/O)

Output Operations

The functional configuration provides a means for communicating with a peripheral device or structure on a single a
bit bus for both transmitting and receiving data
(bi-directional bus I/O). "Hand shaking" signals are provided to maintain proper bus flow discipline similar to Mode 1.
Interrupt generation and enable/disable functions are also
available.

OBF (Output Buffer"Full). The OBF output will go "low" to
indicate that the CPU has written data out to port A.

Mode 2 Basic Functional Definitions:
• Used in Group A only
• One a bit, bl-directional bus Port (Port A) and a 5 bit
control Port (Port C)
• Both inputs and outputs are latched
• The 5 bit control port (Port C) is used for control and
status for the a-bit, bl-directional bus port (Port A)
BI-dlrectlonal Bus I/O Control Signal Definition
(Figures 11, 12, 13, 14)
INTR (Interrupt Request). A high on this output can be used
to interrupt the CPU for both input or output operations.

ACK (Acknowledge). A "low" on this input enables the
three-state output buffer of port A to send out the data.
Otherwise, the output buffer will be in the high impedance
state.
INTE 1 (The INTE flip-flop associated with OBF). Controlled by bit seVreset of PC4.
Input Operations
STB (Strobe Input). A "low" on this input loads data into the
input latch.
IBF (Input Buffer Full F/F). A "high" on this output indicates
that data has been loaded into the input latch.
INTE 2 (The INTE flip-flop associated with IBF). Controlled
by bit seVreset of PC4.

5-56

82C55A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

CONTROL WORD

"'"

l-INPUT
O-OUTPUT

PORTS
l-INPUT
0- OUTPUT

,,"---

' - - - - - GROUP B MODE
O-MOoEO
,-MOOE 1

iffi--_

FIGURE 11. MODE CONTROL WORD

I/O

FIGURE 12. MODE 2

WR

INTR

IB' ____________
PERIPHERAL
BUS

~----JI

----------

iiii
DATA fROM
82C55A TO CPU

FIGURE 13. MODE 2 (BI-DIRECTIONAL)

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(INTR = IBF • MASK • STB • Rli + OBF • MASK • ACK • WR)

5-57

82C55A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Ha"is Semiconductor and is for
use as application and design information only. No guarantee is Implied.

MODE 2 AND MODE 0 (lNPUTI

MODE 2 AND MODE 0 (OUTPUT!

INTRa

CONTROL WORD

0, D.

0.

CONTROL WORD

D.. 0, 02 Dt Do

0, O. 0, D, OJ 0, 0, Do

1• I•DTA:,>+1250C

Logical "0" Input Voltage

VIL

VCC=4.5V

1,2,3

-55°C ~TA:'> +1250 C

VCC=4.5V,
IOH=-2.5mA
10H = -l00pA(Note 2)

1,2,3

-550C.s TA .s + 125°C

VOL

VCC=4.5V,
10L = 2.5mA (Note 2)

1,2,3

-550C~TA~+1250C

-

0.4

V

Input Leakage Current

II

VCC=5.5V,
VIN = GND orVCC
DIP Pins: 1 - 3, 26, 27

1,2,3

-550C.sTA:'> +1250 C

-1.0

+1.0

pA

Output Leakage Current

10

VCC=5.5V,
VIN = GND orVCC
DIP Pins: 4 -13, 15, 16

1,2,3

-550C.sTA.s +125 0 C

-10

+10

pA

IR Input Load Current

ILiR

VCC = 5.5\(, VIN = OV
VIN=VCC,
DIP Pins: 18 - 25

1,2,3

-55 0C:,>TA.s+1250C

-

-500
10

pA
pA

Standby Power Supply
Current

ICCSB

VCC= 5.5\(,
VIN=VCCorGND
Outputs Open, (Note 1)

1,2,3

-55°C .s TAS. + 125°C

-

10

pA

Output HIG H Voltage

Output LOW Voltage

VOH

NOTES: 1. Excopt for IRO - IR7. whoro Vin = vee or OPEN.
2. Interchanging of force and sense conditions is permitted.

CAUTION: Thesa devices are sensitive to electroniC discharge. Proper I.C. handling procedures should be followed.

5-64

Specifications 82C59A/883
TABLE 2. 82C59A/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS
PARAMETER

SYMBOL

LIMITS

~2C59A-5/883 82C59A/883

(NOTE 1)

GROUPA

CONDITIONS

SUBGROUPS

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

TIMING REQUIREMENTS
AO/CS Setup to
RD/INTA

TAHRL
(1)

9,10,11

-550C~TA.:5:+1250C

10

-

10

-

ns

AO/CS Hold after
RD/INTA

TRHAX
(2)

9,10,11

-550C~TA.:5:.+1250C

5

-

5

-

ns

160

-

ns

0
5

-

ns

95

-

ns

RD/INTA Pulse Width

TRLRH(3)

9,10,11

-550C  1.5V,

2. This Is a low time required to clear the input latch in the edge triggered mode.

VOL

< 1.5V, VCC = 4.5V and 5.5\1.

- -

3. Worst case timing for TCHCL in an actual microprocessor system is typically much grealer than 400n& (i.e. BOSSA = 1.6~, 8085A-2 = 1pS, BOCB6 =
Ips).

4. Tested under Test Condition 1 in Test Condition Definition Table.
5. Tested under Test Condition 3 in Test CondHion Definition Table.

CAUTION: These devices are sensitive to electronic discharge. Proper

I.e. handling procedures should be followed.

5-65

Specifications 82C59A/883
TABLE 3. 82C59A/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Input Capacitance

Output Capacitance

I/O Capacitance

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

-

-.

15
7

pF
pF

-

15
7

pF.
pF

15
7

pF
pF

CIN

VCC = OPEN, f = 1 MHz,
All Measurements
Referenced to Device GND

.1,2
1,3

TA=+250 C
TA=+250 C

COUT

VCC = OPEN, f = 1 MHz,
All Measurements
Referenced to Device GND

1,2
1,3

TA=+250 C
TA=+250 C

ClIO

VCC = OPEN, f = 1MHz
All Measurements
Referenced to Device GND

1,2
1,3

TA=+25 0 C
TA=+25 0 C

82C59A-5/883
PARAMETER
Data Float After
RD/INTA

SYMBOL CONDITIONS

-

82C59A/883

NOTES

TEMPERATURE

MIN

MAX

MIN

MAX

UNITS

1,4

-550 C ~TA.$. +1250 C

10

100

10

85

ns

RHDZ(15)

NOTES: 1. The parameters listed In table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.
2. For Ceramic DIP package.
3. For Ceramic LCC package.
4. Tested as follows: f = 1 MHz, VIH = 2.SV, VIL = O.4V, CL = 50pF (unless otherwise specified), VOH > 1.5V, VOL < 1.5V, VCC = 4.5V and 5.5V, us·
ing Test Condition 2 in Test Condition Oefinltion Table.
-

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

SUBGROUPS

InHialTest

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

FlnalTest

100%

2,3,8A, 8B, 10, 11

-

1,2,3, 7, 8A,8B,9,10,11

Ssmples/5005

1,7,9

Group A
GroupsC&D

CAUTION:

METHOD

Thsse devices are sensHive

to electronic discharge. Proper I.C. hand6ng procedures should be followed.

5-66

82C59A/883
Timing Waveforms

t-'i~i"-jf

WRITE

--;1

IAHWL(41

cs

,'W_"_A_'(_5_1_ _ _ __

..

ADDRESS BUS

DATA BUS

READ/INTA

Jt- 'rj~" --=UrI

(181

1--'--"'--1
cs
ADDRESS BUS

)

-

A.

10"'H(191

10'"

I

1

III

-I

fAHRL

IOHAX(21

J(
I-

:-

TOLDV(141
IAHDV (201

DATA BUS

]

1

(151

_----=:J-~
-lRHUl -

+<:;...=

-

-

-

-

OTHER TIMING

iiii
INTA

iiii

r

I~A~
iiii
iNTA

'---------1 LTCHCL~
(131 ~

WR

_____J~

INTA SEQUENCE
t=11J"IH(161

10
,.,

~

~'LO
__.
in .... ]

Sn ••••

/11

_ _ _ _ _ _ _J.

I

iiii

I

.----~-=~'~J--==
T-o-_
cl
po~
TCVlAL

co·z

ICVlAl

- =-llv1Iv(1 71 11"cv

NOTES: I. Interrupt Request (IR) must remain HIGH until leading edge 01 first
2. During r...t INTA the Data Bus Is not active in BOCBe/BB mode.
3. BOCBe/BB mode.
4. B080/BOB5 mode.

5-67

iNTA.

82C59A/883
A. C. Test Circuit

V1

TEST CONDITION DEFINITION TABLE

R1
OUTPUT FROM
DEVICE UNDER 0---"""---",,,,---0 TEST
TEST
POINT
R2

TEST
CONDITION

V1

R1

R2

C1

1

1.7V

5230

Open

100pF

2

vee

1.8kO

1.8kO

50pF

3

1.7V

5230

Open

50pF

" Includes Stray and Jig Capacitance

A. C. Testing Input, Output Waveform
OUTPUT

INPUT
VIH - 0.4V

VOH

~

VIL - 0.4V

~

------~

VOL

A.C. Testing: All inputs signals must switch between VIL - O.4V and
VIH +O.4V. Input rise and fall times are driven at 1 nsN.

Burn-In Circuits
82C59A/883 CERAMIC DIP
GNO
WR
RO
07
06
05
04
03
02
01
DO
CAS 0
CAS 1

R1

~-----~-VCC

Rl

Rl

Rl

Rl

R1

R2

Rl

R2

Rl

R2

R1

R2

R1

R2

R1

R2

R1

R2

R1

R2

R3

R3

R3

NOTES:
VCC = S.SV ± O.SV
VIH = 4.SV ± 10%
VIL = -0.2V 10 0.4V
GND = OV
R1 = 47kO ± 5%
R2 = 5100 ± 5%
R3 = 10kO ± 5%
5%

;= 0.01 /IF min
FO = 100kHz ± 10%

C1

F1

IR7
IR6
IRS
IR4
IR3
IR2

VCC

IRl
IRQ
A

82C59A/883 CERAMIC LCC

= 1.2kO ±

~C1

INTA

AJR3

R3

GNO

R4

AO

= FOf2, F2 = F1f2, ... Fa = F7f2

5-68

SPfEN
CAS 2

i

R3

82C59A/883

Metallization Topology
DIE DIMENSIONS:
154.3 x 173.2 x 19 ± 1mils
METALLIZATION:
Type: Si -AL
Thickness: 11 k.8. ± 1k.8.
GLASSIVATION:
Type: Si02
Thickness: 8k.8. ± 1k.8.
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy (LCC has Gold Preform)
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
1.64 x 105 A/cm 2

Metallization Mask Layout
82C59A/883

07

RO

Wii

Cs"

vcc

AO

INTA

IR7
06

IR6
05

IR5

.

!3
en a:

ClW

04

:;::1:

u!!:
a:
W
IR4
03

IR3
02

IR2
01

IR1
DO

CASO CAS1 GNO CAS2

SP/EN

5-69

INT

IRO

"-

82C59A/883
Packaging t
28 PIN CERAMIC DIP

.005 MIN

t~~
I ]
JL
.
.L

.225 MAX

f
.125
.180

1.470

r-

~

~

j

I

1.440

~

I I

~~

I

.1~0

II

.150
.180

~.09a

016.
- '.023

MIN

o·

15'

MAX

.100
BSC

.050·
• INCREASE MAX LIMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
. SOLDER FINISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± lOoC
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-lO

28 PAD CERAMIC lCC
BOTTOM VIEW

n

.442

.458

.045

.055

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL:. Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: GoldfTin (80/20)
Temperature: 320 0 C ± lOoC
Method: Furnace Braze

NOTE: All Dimensions are

..!::!.!!!.... , Dimensions are in inches.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-4

tMil-M-38510 Compliant Materials, Finishes, and Dimensions.

Max

5-70

m

82C59A

HARRIS

DESIGN INFORMATION
CMOS Priority Interrupt Controller
The information contained in this section has been developed through characterization by Harris Semiconductpr and is for
use as application and design information only. No guarantee is implied.

Functional Description

being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however, the processor would resume exactly where it left off.

INTERRUPTS IN MICROCOMPUTER SYSTEMS

Microcomputers system design requires that I/O devices
such as keyboards, displays, sensors and other components receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.
The most common method of servicing such devices is the
Polled approach. This is where the processor must test
each device in sequence and in effect "ask" each one if it
needs servicing. It is easy to see that a large portion of the
main program is looping through this continuous polling cycle and that such a method would have a serious, detrimental effect on system through-put, thus limiting the tasks that
could be assumed by the microcomputer and reducing the
cost effectiveness of using such devices.
A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently

This is the interrupt-driven method. It is easy to see that
system throughput would drastically increase, and thus
more tasks could be assumed by the microcomputer to further enhance its cost effectiveness.
The Programmable Interrupt Controller (PIC) functions as
an overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which
of the incoming requests is of the highest importance (priority), ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or "routine" that is associated with its specific
functional or operational requirements; this is referred to as
a "service routine". The PIC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that
can "point" the Program Counter to the service routine
associated with the requesting device. This "pointer" is an
address in a vectoring table and will often be referred to, in
this document, as vectoring data.
~

"'"
::;:=

!!::
0::

w

"-

POLLED METHOD

INTERRUPT METHOD

5-71

82C59A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

82C59A Functional Description
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for
expandability to other 82C59As (up to 4 levels). It is
programmed by system software as an I/O peripheral. A
selection of priority modes is available to the programmer
so that the manner in which the requests are processed by
the 82C59A can be configured to match system requirements. The priority modes can be changed or reconfigured
dynamically at any time during main program' operation.
This means that the complete interrupt structure can be defined as required, based on the total system environment.

INTERRUPT (INn

This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible with
the 8080A, 8085A, 808 , 8088 and 80C8 , 80C88 input
levels.
INTERRUPT ACKNOWLEDGE (lNTA)

INTA pulses will cause the 82C59A to release vectoring
information onto the data bus. The format of this data
depends on the system mode ("PM) of the 80C59A.

INTERRUPT REQUEST REGISTER (IRR) AND
IN-SERVICE REGISTER (ISR)

The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Registers (IRR) and
the In-Service Register (ISR). The IRR is used to store all the
interrupt levels which are requesting service, and the ISR is
used to store all the interrupt levels which are currently
being serviced.
PRIORITY RESOLVER

This logic block determines the priorities of the bits set in
the IRR. The highest priority is selected and strobed into the
corresponding bit of the ISR during the INTA sequence.
INTERRUPT MASK REGISTER (IMR)

The IMR stores the bits which disable the interrupt lines to
be masked. The IMR operates on the output of the IRR.
Masking of a higher priority input will not affect the interrupt
request lines of lower priority.

.

SLAVE PROGRESS,
ENABLE BUFFER

INTERRUPT
REQUESTS

AD

IR.

A.

1",

IRI

I"

1R4

c;

82C59A FUNCTIONAL DIAGRAM

5-72

82C59A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
DATA BUS BUFFER

These events occur in an 8080A/8085 system:

This 3-state, bidirectional 8-bit buffer is used to interface
the 82C59A to the system Data Bus. Control words and status information are transferred through the Data Bus Buffer.

1. One or more of the INTERRUPT REQUEST lines (10-17)
are raised high, setting the corresponding IRR bits(s).

READ/WRITE CONTROL LOGIC

The function of this block is to accept OUTput commands
from the CPU. It contains the Intialization Command Word
(ICW) registers and Operation Command Word (OCW)
registers which store the various control formats for device
operation. This function block also allows the status of the
82C59A to be transferred onto the Data Bus.
CHIP SELECT (CS)

A LOW on this input enables the 82C59A. No reading or
writing of the device will occur unless the device is selected.
WRITE (WR)

A LOW on this input enables the CPU to write control words
(ICWs and OCWs) to the 82C59A.
READ (RD)

A LOW on this input enables the 82C59A to send the status
of the Interrupt Request Register (IRR), In-Service Register
(ISR), the Interrupt Mask Register (IMR), or the interrupt
level (in the poll mode) onto the Data Bus.
AO

This input signal is used in conjunction with WR and RD
signals to write commands into the various command registers, as well as reading the various status registers of the
chip. This line can be tied directly to one of the address
lines.
THE CASCADE BUFFER/COMPARATOR

This function block stores and compares the IDs of all
82C59As used in the system. The associated three I/O pins
(CASO-2) are outputs when the 82C59A is used as a master
and are inputs when the 82C59A is used as a slave. As a
master, the 82C59A sends the ID of the interrupting slave
device onto the CASO-2 lines. The slave thus selected will
send its preprogrammed subroutine address onto the Data
Bus during the next one or two consecutive iiii"'i'A pulses.
(See section "Cascading the 82C59A".)
INTERRUPT SEQUENCE

The powerful features of the 82C59A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specified interrupt routine requested without
any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of
CPU being used.

2. The 82C59A evaluates these requests in the priority
resolver and sends an interrupt (I NT) to the CPU, if
appropriate.
3. The CPU acknowledges the INT and responds with an
iNTA pulse.
4. Upon receiving an iNTA from the CPU group, the highest
priority ISR bit is set, and the corresponding IRR bit is
reset. The 82C59A will also release a CALL instruction
code (11001101) onto the 8-bit data bus through DOD7.
5. This CALL instruction will initiate two additional INTA
pulses to be sent to 82C59A from the CPU group.
6. These two INTA pulses allow the 82C59A to release its
preprogrammed subroutine address onto the data bus.
The lower 8-bit address is released at the first INTA
pulse and the higher 8-bit address is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released by
the 82C59A.ln the AEOI mode, the ISR bit is reset at the
end of the third INTA pulse. Otherwise, the ISR bit
remains set until an appropriate EOI command is issued
at the end of the interrupt sequence.
The events occurring in an 80C86 system are the same until
step 4.
4. Upon receiving an INTA from the CPU group, the highest
priority ISR bit is set and the corresponding IRR bit Is
reset. The 82C59A does not drive the data bus during
this cycle.
5. The 80C86 will initiate a second INTA pulse. During this
pulse, the 82C59A releases an 8-bit pointer onto the
data bus where it is read by the CPU.
6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI
command is issued at the end ofthe interrupt subroutine.
If no interrupt request is present at step 4 of either sequence
(i.e. the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave Is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.

5-73

82C59A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee Is implied.

Interrupt Sequence Outputs

CONTENT OF THIRD INTERRUPT VECTOR BYTE

BOBO,BOB5

07

This ~uence is timed by three INTA pulses. During the
first INTA pulse, the CALL opcode is enabled onto the data
bus.

A15

06

Call Code

05

04

o

o

03

02

01

00

o

During the second iN'iA pulse, the lower address of the appropriate service routine is enabled onto the data bus.
When interval = 4 bits, A5 - A7 are programmed, while AO
- A4 are automatically inserted by the 82C59A. When interval = 8, only A6 and A7 are programmed, while AO - A5 are
automatically inserted.
CONTENT OF SECONO INTERRUPT VECTOR BYTE ,

Interval =4

IR
07

06

05

7

A7

A6

A5

6

A7

A6

A5

04

03

5

A7

A6

A5

o

4

A7

A6

A5

o

3

A7

A6

A5

0

2

A7

A6

A5

0

A7

A6

A5

0

A7

A6

A5

0

o

07

06

7

A7

A6

6

'A7

A6

05

04

03

o

5

A7

A6

o

4

A7

A6

o

3

A7

A6

0

2

A7

A6

0

A7

A6

0

A7

A6

0

o
o

o

I 05 I 04

I I I
A14

A13

A12

03
A11

I 02 I 01 I 00

I I I
A10

A9

AS

80C86 mode is similar to 8080/85 mode except that only
two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sent to the processor. The first
interrupt acknowledge cycle is similar to that of 8080/85
systems in that the 82C59A uses it to internally freeze the
state of the interrupts for priority resolution and, as a master,
it issues the interrupt code on the cascade lines. On this
first cycle, it does not issue any data to the processor and
leaves its data bus buffers disabled. On the second interrupt acknowledge cycle in 80C86 mode, the master (or
slave if so programmed) will send a byte of data to the processor with the acknowledged interrupt code composed as
follows (note the state of the ADI mode control is ignored
and A5 - A11 are unused in 80C86 mode.)
CONTENT OF INTERRUPT
VECTOR BYTE FOR BOCB6 SYSTEM MODE

02

01

00

o

o

o

07

06

05

04

03

IR7

T7

T6

T5

T4

T3

o

o
o
o

o

o

o

IR6

T7

T6

T5

T4

T3

o
o

IR5

T7

T6

T5

T4

T3

o

o
o

IR4

T7

T6

T5

T4

T3

o

o

IR3

T7

T6

' T5

T4

T3

0

o

o

IR2

T7

T6

T5

T4

T3

0

IR1

T7

T6

T5

T4

T3

0

o

IRO

T7

T6

T5

T4

T3

0

o

o

Interval =8

IR

o

o
o

06

BOCB6, 80CBB INTERRUPT RESPONSE MODE

First Interrupt Vector Byte Data: Hex CD
07

I

02

01

00

o
o
o
o
o

o
o

o
o

o

o

o

o

o

o

o
o

o
o

o

o
o

o
o

o
o

02

01

00

o

o
o

o
o
o

PROGRAMMING THE B2C59A

The 82C59A accepts two types of command words generated by the CPU;
1. Initialization Command Words (ICWs): Before normal operation can begin, each 82C59A in the system must be
brought to a starting point - by a sequence of 2 to 4
bytes timed by WR pulses.
2. Operation Command Words (OCWs): These are the
command words which command the 82C59A to operate in various interrupt modes. Among these modes are:

a Fully nested mode
During the third INTA pulse, the higher address of the
appropriate service routine, which was programmed as byte
2 of the initialization sequence (AS - A 15), is enabled onto
the bus.

b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written Into the 82C59A anytime after
initialization.

5-74

82C59A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Initialization Command Words (ICWS)

leWI

A.

GENERAl

D,

D,

D,

D,

D,

D,

D,

D.

Whenever a command Is Issued with AO=O and 04=1, this
is interpreted as Initialization Command Word 1 (ICW1).
ICW1 starts the initialization sequence during which the following automatically occur.

I -,cwe NEEDED
a .. NO leW4 NEEDED
I·SINGLE

a.. CASCADE MODE

a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) input must
make a low-to-high transition to generate an interrupt.

CALL ADDRESS INTERVAL
I "INTERVAL Of 4
• "INTERVAL Of.

b. The Interrupt Mask Register Is cleared.

, .. lEVEL TRIGGERED 1I00E
0- EDGE TRIGGERED MODE

c. IR7 input is assigned priority 7.
d. Special Mask Mode is cleared and Status Read is set to
IRR.

41- AS OF INTERRUPT
VECTOR ADDRESS
(MCHGII5MODEONLY)

e. If IC4=O, then all functions selected in ICW4 are set to
zero. (Non-Buffered mode*, no Auto-EOI, 8080/85 system).

lewz

*NOTE: Master/Slave in ICW4 is only used in the buffered
mode.

AI5 - A8 Of INTERRUPT
VECTOR ADDRESS

(MCSlllaS MODEl
T1- T3 Of INTERRUPT
YECTOR ADDRESS

INITIALIZATION COMMAND WORDS 1 AND 2 (ICW1, ICW2)

(IOn/lOIIMODEI

AS - A15: Page starting address of service routines. In an
8080/85 system, the 8 request levels will generate CALLS to 8 locations equally spaced in
memory. These can be programmed to be
spaced at intervals of 4 or 8 memory locations,
thus the 8 routines will occupy a page of 32 or 64
bytes, respectively.

lewl (MASTER DEVICEI

D,

D,

1" IA INPUT HAS A SLAVE
0= IA INPUT DOES NOT HAVE
A SLAVE

!)

CI>~

ICW31SLAVE DEVICEI

A.

D,

D,

D,

D,

D,

D,

0'"

D,

::e=
u!!:

...

DD

II:
D..

SLAVEIOI1J

o

o

a

I
I
D

2

3

4

0
I

aDO

D

1

5

8

1

a

II
I

1

,

,cw,
'·8018/1611 .. 00£
0" MeS-IOIIS MODE
1" AUTO £01
O· NORMAL EOI

- NON BUFFERED MODE
- BUFFERED MOOElSlAVE
- IUFF,UED MOOEIMASTER
1" SPECIAL FULLY NESTED
MODE
O. NOT SPECIAL FULLY
NESTEOMOOE

82C59A INITIALIZATION SEQUENCE

82C59A INITIALIZATION COMMAND WORD FORMAT

5-75

7

1

82C59A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as applicatIon and design information only. No guarantee is implied.
The address format is 2 bytes long (AO - A15). when the
routine interval is 4, AO - A4 are automatically inserted by
the 82C59A, while A5 - A15 are programmed externally.
When the routine Interval is 8, AO - A5 are automatically
inserted by the 82C59A while A6 - A15 are programmed
externally. '
The 8-byte interval will maintain compatibility with current
software, while the 4-byte interval is best for a compact
jump table.
In an 80C86 system, A 15 - A 11 are inserted In the five most
significant bits of the vectoring byte and the 82C59A sets
the th rae least significant bits according to the interrupt
level. A1O-A5 are ignored and ADI (Address interval) has no
effect.

AEOI: If AEOI = 1, the automatic end of interrupt mode is
programmed.
",PM: Microprocessor mode: ",PM = 0 sets the 82C59A for
8080/85 system operation, ",PM = 1 sets the
82C59A for 80C86 system operation.
OPERATION COMMAND WORDS (OCWs)

After the Initialization Command Words (ICWs) are programmed Into the 82C59A, the device is ready to accept interrupt requests at its input lines. However, during the
82C59A operation a selection of algorithms can command
the 82C59A to operate in various modes through the Operation Command Words (OCWs).
OPERATION CONTROL WORDS (OCWs)

AO

LTIM: If LTIM = 1, then the 82C59A will operate in the level
interrupt mode. Edge detect logic on the interrupt
inputs will be disabled.

DO

MO

ADI: CALL address interval. ADI = 1 then interval = 4; ADI
= 0 then interval = 8.
SNGL: Single. Means that this Is the only 82C59A In the
system. If SNGL = 1, no ICW3 will be issued.

o

LO,

IC4: If this bit is set - ICW4 has to be issued. If ICW4 is not
needed, set IC4 = O.

o

RIS

INITIAUZATION COMMAND WORD 3 (ICW3)

This word Is read only when there Is more than one 82C59A
in the system and cascading is used, In which case SNGL
= O. It will load the 8-bit slave register. The functions of this
register are:

ocm

a. In the master mode (either when SP=1, or in buffered
mode when M/S=1 in ICW4) a "1" is set for each slave in
the bit corresponding to the appropriate IR line for the
slave. The master then will release byte 1 of the call
sequence (for 8080/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for 80C86,
only byte 2) through the cascade lines.
b. In the slave mode (either when SP=O, or if BUF = 1 and
MIS = 0 In ICW4), bits 2-0 identify the slave. The slave
compares its cascade input with these bits and if they
are equal, bytes 2 and 3 of the call sequence (or just byte
2 for 80C86) are released by it on the Data Bus (Note:
the slave address must correspond to the IR line it is
connected to In the master 10).

IALEVEL TO BE
ACTED UPON

•

•

1

1

1

·..
1

•
1
••

1

1

•

1

•

NON-sJ'ECIFICfOICOMMAND
• S'EClfIC EOI COMMAND

• ROTATE ON SPECIFIC EOI COMMAND
• SET PRIDIIITY COMMAND

BUF: If BUF = 1, the buffered mode is programmed. In
buffered mode, SP/EN becomes an enable output
and the masterlslave determination is by MIS.
MIS: If buffered mode is selected: MIS = 1 means the
82C59A Is programmed to be a master. MIS = 0
means the 82C59A is programmed to be a slave. If
BUF = 0, MIS has no function.

5-76

0

I

a

•

1
,

01

1

001

1

au

0

1

1

I

I

1

}--ENOOF1NTfRRUPT

}--SPECIFICIIOTATlDN

NOO.£IIATIOIII

oLO-LZARfUSED

IL

SFNM: If SFNM = 1, the special'fully nested mode Is programmed.

2345.

.,

ROTATE ON NON-SPECIFIC EOI COMMAIIID}.
ROTATE IN AUTOMATIC £01 MODE lSET!
AUTOMATIC ROTATION
ROTATE IN AUTOMATIC EOI MODE ICLEAR)

I • I D 1"·"i·M·1 • I 1 I p I OR I 'IS I

INITIAUZATION COMMAND WORD 4 (ICW4)

01

·· . .

READ REGISTER COMMAND

1

10 ACTION

1
1
1
READ
READ
IRREG
IIREG
DHIEXT DNItEXT
RDPULSf RDPULSE

''''OLLCOMMANO
D-IIO'OLLCOMMANO

·•

.

SPECIALMASICMODE
1
D
1
RESn
NOAI:TIOIII
S'ECIAL
MASK

1
1

snl

SPECIAL
MASK

82C59A OPERATION' COMMAND WORD FORMAT

82C59A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
OPERATION CONTROL WORD 1 (OCW1)

OCW1 sets and clears the mask bits in the Interrupt Mask
Register (IMR). M7 - MO represent the eight mask bits. M =
1 indicates the channel is masked (inhibited), M = 0 indicates the channel is enabled.
OPERATION CONTROL WORD 2 (OCW2)

R, SL, EOI - These three bits control the Rotate and End of
Interrupt modes and combinations of the two. A chart of
these combinations can be found on the Operation Command Word Format.
L2, L 1, LO - These bits determine the interrupt level acted
upon when the SL bit is active.
OPERATION CONTROL WORD 3 (OCW3)

ESMM - Enable Special Mask Mode. When this bit is set to
1 it enables the SMM bit to set or reset the Special Mask
Mode. When ESMM=O, the SMM bit becomes a "don't
care".
SMM - Special Mask Mode. If ESMM = 1 and SMM=1, the
82C59A will enter Special Mask Mode. If ESMM = 1 and
SMM = 0, the 82C59A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.
FULLY NESTED MODE

This mode is entered after initialization unless another mode
is programmed. The interrupt requests are ordered in priority from 0 through 7 (0 highest). When an interrupt is acknowledged the highest priority request is determined and
its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set. This bit remains set until
the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine,
or if AEOI (Automatic End of Interrupt) bit is set, until the
trailing edge of the last INTA. While the IS bit is set, all further interrupts of the same or lower priority are inhibited,
while higher levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal interrupt
enable flip-flop has been re-enabled through software).
After the initialization sequence, IRO has the highest priority
and IR7 the lowest. Priorities can be changed, as will be explained in the rotating priority mode or via the set priority
command.

IS bit to reset on EOI. When a Non-Specific command is
issued the 82C59A will automatially reset the highest IS bit
of those that are set, since in the fully nested mode the highest IS level was necessarily the last level acknowledged and
serviced. A non-specific EOI can be issued with OCW2
(EOI = 1, SL = 0, R = 0).
When a mode is used which may disturb the fully nested
structure, the 82C59A may no longer be able to determine
the last level acknowledged. In this case a Specific End of
Interrupt must be issued which includes as part of the command the IS level to be reset. A specific EOI can be issued
with OCW2 (EO I = 1, SL = 1, R = 0, and LO-L2 is the binary level of the IS bit to be reset).
An IRR bit that is masked by an IMR bit will not be cleared
by a non-specific EOI if the 82C59A is in the Special Mask
Mode.
AUTOMATIC END OF INTERRUPT (AEOI) MODE

If AEOI = 1 in ICW4, then the 82C59A will operate in AEOI
mode continuously until reprogrammed by ICW4. In this
mode the 82C59A will automatically perform a non-specific
EOI operation at the trailing edge of the last interrupt
acknowledge pulse (third pulse in 8080/85, second in
80C86). Note that from a system standpoint, this mode
should be used only when a nested multi-level interrupt
structure is not required within a single 82C59A.
AUTOMATIC ROTATION (Equal Priority Devices)

In some applications there are a number of interrupting
devices of equal priority. In this mode a device, after being
serviced, receives the lowest priority, so a device requesting
an interrupt will have to wait, in the worst case until each of
7 other devices are serviced at most once. For example, if
the priority and "in service" status is:
Before Rotate (IR4 the highest priority requiring service)

"IS"
STATUS
PRIORITY
STATUS

IS7

IS6

IS5

IS4

IS3

IS2

IS1

ISO

0

1

0

1

0

0

0

0

5

4

3

2

1

0

7_ 6
lowest'::::::'

~highest

END OF INTERRUPT (EOI)

The In Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA
pulse (when AEOI bit in ICW1 is set) or by a command word
that must be issued to the 82C59A before returning from a
service routine (EOI Command). An EOI command must be
issued twice if in the Cascade mode, once for the master
and once for the corresponding slave.
There are two forms of EOI command: Specific and NonSpecific. When the 82C59A is operated in modes which
preserve the fully nested structure, it can determine which

After Rotate (IR4 was serviced, all other priorities rotated
correspondingly)
IS7

IS6

IS5

IS4

IS3

IS2

IS1

ISO

0

1

0

0

0

0

0

0

2
1
highest

0

7

6

5

4
lowest

3

··IS"
STATUS

PRIORITY
STATUS

5-77

• •

~

",[2
OW

==:c
u!!::
a:
W

a..

82C59A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
There are two ways to accomplish Automatic Rotation using
OCW2, the Rotation on Non-Specific EOI Command (R =
1, SL = 0, EOI = 1) and the Rotate in Automatic EOI Mode
which is set by (R = 1, SL = 0, EOI = 0) and cleared by (R =
0, SL = 0, EOI = 0).
'SPECIFIC ROTATION (Specific Priority)

The programmer can change priorities by programming the
bottom priorities and thus fixing all other priorities; i.e., if IR5
is programmed:as the bottom priority device, then IR6 will
have the highest one.
The Set Priority command is issued in OCW2 where: R = 1,
SL = 1, LO-L2 is the binary priority level code of the code of
the bottom priority device.
Observe that in this mode internal status is updated by software control during OCW2. However, it is independent of
the End of Interrupt (EO I) command (also executed by
OCW2). Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI command in
OCW2 (R = 1, SL = 1, EOI = 1 and LO-L2 = IR level to
receive bottom priority).
INTERRUPT MASKS

Each Interrupt Request input can be masked individually by
the Interrupt Mask Register (IMR) programmed through
OCW1. Each bit in the IMR masks one interrupt channel if it
is set (1). Bit 0 masks IRO, Bit 1 masks IR1 and so forth.
Masking an IR channel does not affect the other channels
operation.
SPECIAL MASK MODE

Some applications may require an interrupt service routine
to dynamically alter the system priority structure during its
execution under software control. For example, the routine
may wish to inhibit lower priority requests for a portion of its
execution but enable some of them for another portion.
The difficulty here is that if an Interrupt Request is acknowledged and an End of Interrupt command did not reset its IS
bit (Le., while executing a service routine), the 82C59A
would have inhibited all lower priority requests with no easy
way for the routine to enable them.
That is where the Special Mask Mode comes in. In the special Mask Mode, when a mask bit is set in OCW1, it inhibits
further interrupts at that level and enables interrupts from all
other levels (lower as well as higher) that are not masked.
Thus, any interrupts may be selectively enabled by loading
the mask register.
The special Mask Mode is set by OCW3 where; ESSM
SMM = 1, and cleared where ESSM = 1, SMM = O.

= 1,

POLL COMMAND

In this mode, the INT output is not used or the microprocessor internal Interrupt Enable flip-flop is reset, disabling its
interrupt input. Service to devices is achieved by software
using a Poll command.
The Poll command is issued by setting P = 1 in OCW3. The
82C59A treats the next RD pulse to the 82C59A (Le., RD =
0, CS = 0) as an interrupt acknowledge, sets the appropriate IS bit if there is a request, and reads the priority level. Interrupt is frozen from WR to RD.
The word enabled onto the data bus during RD is:

I

D7

I

D6

I

05

I

04

I

03

I :: I :: I :~ I

WO-W2: Binary code of the highest priority level requesting service.
I: Equal to a "1" ifthere is an interrupt.
This mode is useful if there is a routine command common
to several levels so that the INTA sequence is not needed
(saves ROM space). Another application is to use the poll
mode to expand the number of priority levels to more than
64.
READING THE 82C59A STATUS

The input status of several internal registers can be read to
update the user information on the system. The following
registers can be read via OCW3 (IRR and ISR) or OCW1
(IMR).
In-Service Register (ISR): 8-bit register which contains the
priority levels that are being serviced. The ISR is updated
when an End of Interrupt Command is issued.
Interrupt Mask Register: 8-bit register which contains the
interrupt request lines which are masked.
The IRR can be read when, prior to the RD pulse, a Read
Register Command is issued with OCW3 (RR = 1, RIS = 0).
The ISR can be read when, prior to the RD pulse, a Read
Register Command is issued with OCW3 (RR = 1, RIS = 1).
There is no need to write an OCW3 before every status read
operation, as long as the status read corresponds with the
previous one: Le., the 82C59A "remembers" whether the
IRR or ISR has been previously selected by the OCW3. This
is not true when poll is used. In the poll mode, the 82C59A
treats the RD following a "poll write" operation as an INTA.
After initialization, the 82C59A is set to IRR.
For reading the IMR, no OCW3 is needed. The output data
bus will contain the IMR whenever RD is active and AO = 1
(OCW1). Polling overrides status read when P = 1, RR = 1
in OCW3.

5-78

82C59A

'.DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
EDGE AND LEVEL TRIGGERED MODES

This mode is programmed using bit 3 in ICW1.
If LTIM = ~'O", an interrupt request will be recognized by a
low to high transition on an IR input. The IR input can remain
high without generating another interrupt.
If LTIM = "1", an interrupt request will be recognized by a
"high" level on IR input, and there is no need for an edge
detection. The interrupt request must be removed before the
EOI command is issued or the CPU interrupt is enabled to
prevent a second interrupt from occuring.
The priority cell diagram shows a conceptual circuit of the
level sensitive and edge sensitive input circuitry of the
82C59A. Be sure to note that the request latch is a transparent D type latch.
LTlMBIT
EDGE
lfVEL

o

1

In both the edge and level triggered modes the IR inputs
must remain high until after the falling edge of the first INTA.
If the IR input goes low before this time a DEFAULT IR7 will
occur when the CPU acknowledges the interrupt. This can
be a useful safeguard for detecting interrupts caused by
spurious noise glitches on the IR inputs. To implement this
feature the IR7 routine is used for "clean up" simply executing a return instruction, thus ignoring the interrupt. If IR7 is
needed for other purposes a default IR7 can still be
detected by reading the ISR. A normal IR7 interrupt will set
the corresponding ISR bit, a default IR7 won't. If a default
IR7 routine occurs during a normal IR7 routine, however,
the ISR will remain set. In this case it is necessary to keep
track of whether or not the IR7 routine was previously entered. If another IR7 occurs it is a default.

TO OTHER PRIORITY CELLS

/r----------~"~----------~,
CLHISH
ISRBIT

L--+--+-((-,Hi---;;;:=;;;:;-il SElISR

PRIORITY
RESOLVER

CONTROL
LOGIC

IR

INTA

8080/85 {
MODE

FREEZE

NONMASKED

u=

REa

~gg~ { INTA~~OTES
FREEZE

WRITE MASK

1 MASTER CLEAR ACTIVE ONLY DURJNG ICWl

2. FREEZE IS ACTIVE
3 TRUTH TABLE FOR
C
0
01
X

DURING INTA,AND POLL SEOUENCE ONLY

DUTCH
Q

01

an-'

OPERATION
FOllOW
HOLD

PRIORITY CELL - SIMPUFIED LOGIC DIAGRAM

IR

IR TRIGGERING
TIMING
REQUIREMENTS

+-J

INT _______

IMTA

-----+---__.
LATCH"
ARMED

LATCH"

EARLIESTIR

ARMED

CAN BE REMQVED

5-79

"EDGE TRIGGERED MODE DHLY

82C59A

DESIGN INFORMATION- (Continued)
The information contained in this section has been. developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

In power sensitive applications, it is advisable to place the
82C59A in the edge-triggered mode with the IR lines normally high. This will minimize the current through the pullup resistors on the IR pins.
THE SPECIAL FULLY NESTED MODE

This mode will be used in the case of a big system where
cascading is used, and the priority has to be conserved
within each slave. In this case the special fully nested mode
will be programmed to the master (using ICW4). This mode
is similar to the normal nested mode with the following exceptions:
a. When an interrupt request from a certain slave Is in service, this slave is not locked out from the master's priority
logic and further interrupt requests from higher priority
IRs within the slave will be recognized by the master and
will initiate interrupts to the processor. (In the normal
nested mode a slave is masked out when its request is in
service and no higher requests from the same slave can
be serviced.
b. When exiting the Interrupt Service routine the software
has to check whether the interrupt serviced was the only
one from that slave. This is done by sending a non-specific End of Interrupt (EOI) command to the slave and
then reading its In-Service register and checking for
zero. If it is empty, a non-specified EOI can be sent to the
master, too. If not, no EOI should be sent.

whenever the 82C59A's data bus outputs are enabled, the
SP/EN output becomes active.
This modification forces the use of software programming
to determine whether the 82C59A is a master or a slave. Bit
3 in ICW4 programs the buffered mode, and bit 2 in ICW4
determines whether it is a master or a slave.
CASCADE MODE

The 82C59A can be easily interconnected in a system of
one master with up to eight slaves to handle up to 64 priority
levels.
The master controls the slaves through the 3 line cascade
bus. The cascade bus acts like chip selects to the slaves
during the INTA sequence.
In a cascade configuration, the slave interrupt outputs are
connected to the master interrupt request inputs. When a
slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave to
release the device routine address during bytes 2 and 3 of
INTA. (Byte 2 only for 80C86/80C88).

BUFFERED MODE

When the 82C59A is used in a large system where bus driving buffers are required on the data bus and the cascading
mode is used, there exists the problem of enabling buffers.
The buffered mode will structure the 82C59A to send an enable signal of SP/EN to enable the buffers. In this mode,

The cascade bus lines are normally low and will contain the
slave address code from the trailing edge of the first INTA
pulse to the trailing edge of the third pulse. Each 82C59A in
the system must follow a separate initialization sequence
and can be programmed to work in a different mode. An EOI
command must be Issued twice: once for the master and
once for the corresponding slave. Chip select decoding Is
required to activate each 82C59A. Note: Auto EOI Is supported in the slave mode for the 82C59A.
The cascade lines of the Master 82C59A are activated only
for slave inputs, non-slave Inputs leave the cascade line
inactive (low). Therefore, it is necessary. to use a slave
address of 0 (zero) only after all other addresses are used.

)

AUIIIIHSIUII1I1

"""'""

II

\.

)

II

II

IITREQ

1h\1J.8US!11

- - - -

- -- - - -- - -

- -- - -

- - - ----- -

- -

- --

r:,
,
""
~~ , , , , , , '~¥
""

I

...,

a

""

.!.

•

....

"'"

...

.

! ! ! ! 1!! !

,

- - - - - -----,
,., "'"
~~L
w,
,
, , , r:UI

~ 1::-:! !. ! .! ! ! ! !
.....

1

J.

CASCADING THE 82C59A

5-80

J r:,

..,

A.

""
I ""
If." ..

""

IUSTtAm:~

M&

M5

1M

10

M2

., : I

r ! 1. ! ! ,! ! !

,

m

82C82/883

HARRIS

CMOS Octal Latching Bus Driver

June 1989

Features

Pinouts
82C82/883 (CERAMIC DIP)
TOP VIEW

• This Circuit is Processed in Accordance to Mil-Std-883 and Is Fully
Conformant Under the Provisions of Paragraph 1.2.1.
• Full Eight-Bit Parallel Latching Buffer

DID

• Bipolar 8282 Compatible

Dl1

• Three-State Noninverting Outputs

Dl2

001

• Propagation Delay ••••••••••••••••••••••••••••••••••••• 35ns Max.

01 3

002

• Gated Inputs:

Dl4

003

DiS

004

~

Reduce Operating Power

~

Eliminate the Need for Pull-Up Resistors

• Single 5V Power Supply
• Low Power Operation - ICCSB

= 10llA

• Military Operating Temperature Range ••••••••• -55 0 C to +125 0 C

000

DiS

005

Dl7

DOs

OE

007

GND

STB

Description
The Harris 82C82/883 is a high performance CMOS Octal Latching Buffer
manufactured using a self-aligned silicon gate CMOS process (Scaled
SAJIIV). The 82C82/883 provides an eight-bit parallel latch/buffer In a 20
pin package. The active high strobe (8TB) input allows transparent transfer
of data and latches data on the negative transition of this signal. The active
low output enable (OE) permits simple interface to state-of-the-art
microprocessor systems.

Functional Diagram

82C82/883 (CERAMIC LCC)
TOP VIEW

c~ -=
c E
c 8
> 8
c
L~J L~J l~J L~ ~,!JJ

1]

Dl3

[fa 001

014

[f7 002

Dis

[fs 003

Dis

004

~]

017

r-.,

r-...

r-., r-, r-,

[f4 005

'9' '10! '11' '12' '1

TRUTH TABLE
STB

OE

01

DO

X
H
H
~

H
L
L
L

X
L
H
X

HI-Z
L
H

.

H = Logic One
Hi-Z = High Impedance
L = Logic Zero
Neg. Transition
X = Don't Care
• = L.alched 10 Value of lasl Oala

,=

PIN NAMES
PIN
D10-Dl7
000-007
STB
OE
Copyrighl @ Harris Corporalian 1989

5-81

DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output Enable

Specifications 82C82/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ........................................ +8.0V
Input, Output or I/O Voltage Applied. . . .. GND-0.5V to VCC+0.5V
Storage Temperature Range ...............•• -650C to +150 0 C
JunctionTemperature ................................ +175 0 C
Lead Temperature (Soldering 10 sec) •..•..•.•••........ +300 0 C
ESD Classification .................................... Class 1

Thermal Resistance
Bja
Ceramic DIP Package. . . . . . . • . . • . • .
79 0 C/W
Ceramic LCC Package. . • . . . • • . • • • .
76 0 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package .............................. 638mW
Ceramic LCC Package ............................. 664mW
Gate Count ........................................ 65 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may CBuse permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range .•..•.•.••.•.•• -550C to +125 0 C
Operating Supply Voltage ...............••.•... +4.5V to +5.5V
TABLE 1. 82C82/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

TEMPERATURE

MIN

MAX

UNITS

PARAMETER

SYMBOL

Logical One Input
Voltage

VIH

VCC = 5.5V, (Note 1)

1,2,3

-550C:5.TA:5.+1250C

2.2

-

V

Logical Zero Input
Voltage

VIL

VCC=4.5V

1,2,3

-55°C :5.TA:5. +125 0 C

-

0.8

V

VCC = 4.5V,IOH = -8.0mA,
10H = -100JIA,
OE = GND (Note 2)

1,2,3

-550C:5.TA:5.+1250C

2.9
VCC-O.4

-

-

V
'V

VCC = 4.5V, 10L = +8.0mA,
OE = GND (Note 2)

1,2,3

-550C:5.TA:5.+1250C

-

0.4

V

II

VCC = 5.5V, Pins 1-9,11,
VIN = GND or VCC

1,2,3

-55°C :5.TA:5. +125 0 C

-1.0

1.0

JIA

Output Leakage
Current

10

VCC=5.5V,
OE ~ VCC-0.5V,
VOUT = GND or VCC,
Pins 12-19

1,2,3

-550C:5.TA:5.+1250C

-10.0

+10.0

JIA

Standby Power
Supply Current

ICCSB

VCC = 5.5V, Outputs Open,
VIN = VCC or GND

1,2,3

-550C:5.TA:5. +125 0 C

-

10

JIA

Output High
Voltage

VOH

Output Low
Voltage

VOL

Input Leakage
Current

CONDITIONS

LIMITS

GROUPA
SUBGROUPS

NOTES: 1. VIH is measured by applying a pulse of magnitude = VIHmin to one data input at a time and checking the corresponding device output for a valid
logical "1" during valid input high time. Control pins (STB, OE) are tested separately with all device data inputs at VCC-O.4V.
2. Interchanging of force and sense conditions is permitted.

CAUTION: These devices are senSitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

5-82

Specifications 82C82/883
TABLE 2. 82C82/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

SYMBOL

PARAMETER

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

TIMING REQUIREMENTS
Propagation Delay,
Input to Oulput

TIVOV(l)

VCC = 4.5V and 5.5V

9,10,11

-55°C S. TAS. + 125°C

-

35

ns

Propagation Delay,
STB to Output

TSHOV(2)

vee = 4.5V and 5.5V

9,10,11

-550CS.TA S. +1250e

-

55

ns

Output Enable Time

TELOV(4)

vec = 4.5V and 5.5V

9,10,11

-55°C S. TAS. + 125°C

-

50

ns

Input to STB Set Up Time

T1VSL(5)

vce = 4.5V and 5.5V

9,10,11

-55°C S. TAS. + 125°C

0

TSLlX(6)

vee = 4.5V and 5.5V

9,10,11

-55°C STA S.+1250e

25

8TB High Time

TSHSL(7)

vee = 4.5V and 5.5V

9,10,11

-55°C S.TA S. +1250 e

25

-

ns

Input to STB Hold Time

ns
ns

NOTES: 1. All A.C. parameters tested as per test load circuits and definitions in Figures 1-4. Input rise and fall times area driven at lnsN.
2. Tested as follows: f = 1MHz, VIH = 2.6V (VIH for 8TB.2, vee - O.5V), VIL = O.4V. CL = sopt (unless otherwise specified), VOH~ 1.SV, VOL..s. 1.SV.

TABLE 3. 82C82/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

elN

VCC = Open, f = 1 MHz,
All Measurements
Referenced to GND

1,3

TA=+250C

-

13

pF

1,4

TA=+250C

-

12

pF

VCC = Open, f = 1 MHz,
All Measurements
Reference to GND

1,3

TA=+250C

-

20

pF

1,4

TA=+250e

-

15

pF

Input CapaCitance

Output Capacitance

COUT

Output Disable Time

TEHOZ

vce = 4.5V and 5.5V

1,2

-550 CS.TAS. +1250 C

-

35

ns

Input Rise/Fall Time

TR,TF

vce = 4.5V and 5.5V

1

-55°C S.TAS. +1250 C

-

20

ns

NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.

2. Tested as follows: f = 1MHz, VIH

= 2.6V(VIH forSTB~ VCC-O.5V), VIL =O.4V. CL = 50pF(unless otherwise specified). VOH~ 1.5V, VOLS.l.5V.

3. For Ceramic DIP package.
4. For Ceramic LCC package.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Inilial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3, 8A, 8B, 10, 11

-

1,2,3,7, BA, 8B, 9,10,11

samples/5005

1,7,9

Group A
GroupsC&D

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

5-83

82C82/883
Timing Waveform

INPUTS

STB

TEHOZ (3)
OUTPUTS

All timing measurements are made at 1.5V unless otherwise noted.

Test Load Circuits
1.7V

OUTPUT

so.n
~

300pP ¢.

TIVOV,TSHOV,TELOV

3.3V

O.6V

TEST
POINT

OUTPUT

~
P¢.

TEST
POINT

5OP

TEHOZ OUTPUT HIGH DISABLE

* Includes stray and

jig capacitance

5-84

OUTPUT

~
P¢.

TEST
POINT

5O P

TEHOZ OUTPUT LOW DISABLE

82C82/883
Burn-In Circuits
82C82/883 CERAMIC DIP

VCC
C1

~
A
A
A
A

VCC

A

R2

A
A
A

R1

R2

F1

82C82/883 CERAMIC Lec

VCC
F2 F2 F2

C1
VCC/2
R3

F2
F2
F2
F2
F2

~

V

R3

R3

R3

R3

R3
R3
R3

-._.
-._.
-._.

R3

6'

R3

7'

R3

8'
P-" P-" P-" P-" P-"

'9"10! '11"12"13'
R3

R3 R3 R3

NOTES:

vee = 5.5V ± O.5V, Gnd = OV
VIH = 4.5V ± 10%
VIL = -O.2V to O.4V
R1 = 47kO ± 5%
R2 = 2.0kO ± 5%
R3 = 4.2kO ± 5%
R4 = 470kO ± 5%
C1 = O.01pF minimum
FO = 100kHz ± 10%
F1 = FO/2, F2 = F1/2

5-85

~

VCC/2
VCC/2
VCC/2
VCC/2
VCC/2

",;2
0 ....

==:c
...
!!::

.......
II:

.82C82/883

Metallization Topology
DIE DIMENSIONS:
118.1 x 92.1 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11 k.8. ± 1 k.8.
GLASSIVATION:
Type: Si02
Thickness: 8k.8. ± 1 k.8.
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy (LCC has Gold Preform)
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 4200 C (Max)
WORST CASE CURRENT DENSITY:
2.00 x 105 Alcm 2

Metallization Mask Layout
82C82/883

5-86

82C82/883
Packaging t
20 PIN CERAMIC DIP

.005 MIN

~

.940
.970

,---~==========~

j::T

o·
15'
.100

.1BO

esc
... INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-8

20 PAD CERAMIC LCC
BOTTOM VIEW

!1

""

"'c:
OW
u!!:
==""

c:

W

"-

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: GoldfTin (80/20)
Temperature: 320 0 C ± 100 C
Method: Furnace Braze

NOTE: All Dimensions are

.M!!:!....
• Dimensions are in inches.
Max

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-2

t MiI-M-38510 Compliant Malerials, Finishes, and Dimensions.
5-87

m

82C82

HARRIS

DESIGN INFORMATION
CMOS Octal Latching Bus Driver
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Gated Inputs
During normal system operation of a latch, signals on the . D.C. input voltage levels can also cause an increase in ICC
bus at the device inputs will become high impedance or if these input levels approach the minimum VIH or maximum
make transitions unrelated to the operation of the latch. VIL conditions. This is due to the operation of the input
These unrelated input transitions switch the input circuitry circuitry in its 'linear operating region (partially conducting
and typically cause an increase in power dissipation in state). The 82C8X series gated inputs mean that this condiCMOS devices by creating a low resistance path between tion will occur only during the time the device is in the transVCC and GND when the signal is at or near the input parent mode (STB = logic one). ICC remains below the
switching threshold. Additionally, if the driving signal be- maximum ICC standby specification of lOrnA during the
comes high impedance ("float" condition), it could create an time ·inputs are disabled, thereby greatly reducing the
indeterminate·logic state at1he input and cause a disruption average power dissipation of the 82C8X series devices.
in device operation.
The Harris 82C8X series of bus drivers eliminates these Typical 82C82 System Example
conditions by turning off data inputs when data is latched
. (STB = logic zero for the 82C82/83H) and when the device In a typical 80CS6/88 system, the 82C82 is used to latch
is disabled (OE = logiC one for 82C86H/87H). These gated multiplexed addresses and the STB input is driven by ALE
inputs disconnect the input circuitry from the VCC and (Address Latch Enable) (see Figure 3). The high pulse width
ground power supply pins by turning off the upper of ALE is approximately lOOns with a bus cycle time of
P-channel and lower N-channel (see Figures 1,2). No new 800ns (80C86/88 @ 5MHz). The 82C82 inputs are active
current flow from VCC to GND occurs during input transi- only 12.5% of the bus cycle time. Average power dissipation
tions and invalid logic states from floating inputs are not . related to input transitioning is reduced by th is factor also.
transmitted. The next stage is held to a valid logic level
internal to the device.

vee

vee

5TB
DATAIN--~r--------------i

INTERNAL
DATA

DATA IN ---11--------...

FIGURE 1. 82C82183H

FIGURE 2. 82C86H/87H GATED INPUTS

5-88

INTERNAL
DATA

82C82

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Application Information
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C82 data sheet
is determined by
I = CL (dvldt)
Assuming that all outputs change state at the same time
and that dv/dt is constant;

This current spike may cause a large negative voltage spike
on VCC, which could cause improper operation of the
device. To filter out this noise, it is recommended that a
0.1 flF ceramic disc decoupling capacitor be placed
between VCC and GND at each device, with placement
being as near to the device as possible.

1= CL
(VCC

x 80%)

tR/tF
where tR
outputs.

= 20ns, VCC = 5.0V, CL = 300pF on each of eight

1= (8 x 300 x 10- 12) x (5.0V x 0.8)/(20 x 10-9 )
= 480mA

VCC

ALE
MULTIPLEXED
BUS

STBADDRESS

ICC--A~

DATA IN
____________________

~AL

__________

--1--------+

FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS

5-89

INTERNAL
DATA

Em HARRIS

82C83H/883
CMOS Octal latching
Inverting Bus Driver

June 1989

Pinouts

Features
• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1
• Full Eight-Bit Parallel Latching Buffer

82C83H/883 (CERAMIC DIP)
TOP VIEW

01 0

• Bipolar 8283 Compatible

Dll

000

• Three-State Inverting Outputs

01 2

DO,

01 3

002

01 4

003

01 5

004

• Single 5V Power Supply

016

005

• Low Power Operation -ICCSB ••••••••••••••••••••.••••••••• lOIlA

01 7

006

DE

007

GNO

STB

• Propagation Delay. • • • • • • • • • • • • • • • • • • • . • . • • • • • • • • . • • • •• 25ns Max
• Gated Inputs:
• Reduce Operating Power
• Eliminate the Need for Pull-Up Resistors

• Military Operating Temperature Range ••••••••• -55 0 C to +125 0 C

Description
The Harris 82C83H/883 is a high performance CMOS Octal Latching
Buffer manufactured using a self-aligned silicon gate CMOS process
(Scaled SAJI IV), The 82C83H/883 provides an eight-bit parallel latch/
buffer in a 20 pin package, The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this
signal, The active low output enable (OE) permits simple interface to
microprocessor systems, The 82C83H/883 provides Inverted data at the
outputs,

82C83H/883 (CERAMIC LCC)
TOP VIEW

c~:=
c cE 818
> c
L~J L~J l~J

10_-,

t!JJ

~]

ITa

mY,
002

Functional Diagram

003

D04

TRUTH TABLE
STB

OE

01

DO

X

H
L
L
L

X

Hi-Z
H
L

H
H
~

L
H

X

.

H = logic One
Hi-Z = High Impedance
L = logic Zero
~ = Neg. Transition
X = Don'l Care
• = Lalched 10 Value of Lasl Data

PIN NAMES
PIN

010-017
000-007
§lB
OE

Copyright lID Harris Corporation 1989

5-90

DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output Enable

Specifications 82C83H/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••.•••••••••••••••••••••••••••••.•• +8.0V
Input, Output or I/O Voltage Applied. • • .• GND-0.5V to VCC+0.5V
Storage Temperature Range ••••••.•••••••••• -650C to +1500C
Junction Temperature •.••••••••••.••••••••••••••••••. +1750C
Lead Temperature (Soldering 10 sec) ••••••••••••••••••.• 3000C
ESD Classification ••••.•••.•••••••••.•••••••••••••••.• Class 1

Thermal Resistance
Sja
Ceramic DIP Package. • • • • • • • • • . • . • • • • 700 C/W
Ceramic LCC Package. • • • • • • • • • . . • • • • 760 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ••••••••••••.•••......•••••.•• 720mW
Ceramic LCC Package ••.••••••••.•••.••.••••••.••• 664mW
Gate Count •••••••.••.••••.••.••••..••••••.•.••••• 265 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This;s a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range ••••.••.••.••.• -550C to +1250C
Operating Supply Voltage ..•.••••.••••.••••••• ± 4.5V to +5.5V
TABLE 1. 82C83H/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

LIMITS
TEMPERATURE

MIN

MAX

UNITS

VIH

VCC = 5.5 V, (Note 1)

1,2,3

-550C~TA~+1250C

2.2

-

V

logical "O"lnput
Voltage

VIL

VCC=4.5V

1,2,3

-550C~TA~+1250C

-

0.8

V

VCC=4.5V,
IOH=-8.0mA
10H = -100flA,
OE = GND (Note 2)

1,2,3

-550C~TA~ +1250 C

3.0
VCC-0.4

-

V
V

VCC= 4.5V,
10L = +15.0mA
OE = GND (Note 2)

1,2,3

-550C ~TA ~ +1250C

-

0.45

V

Output Low Voltage

VOH

VOL

CONDITIONS

GROUP A
SUBGROUPS

Logical "1" Input
Voltage

Output High Voltage

SYMBOL

Input Leakage Current

It

VCC = 5.5V, Pins 1-9,
11, VIN = GND orVCC

1,2,3

-550C ~TA~ +125 0C

-10.0

+10.0

flA

Output Leakage Current

10

VCC=5.5V,
OE~ VCC -0.5V
VOUT = GND orVCC,
Pins 12-19

1,2,3

-550C~TA~+1250C

-10.0

+10.0

flA

VCC=5.5V,
Outputs Open,
VIN=VCCorGND

1,2,3

-550C~TA~+1250C

-

10

flA

Standby Power Supply
Current

ICCSB

NOTES: 1. VIH is measured by applying a pulse of magnitude = VIHmin to one data input at a time and checking the corresponding device output for a valid
logical "'" during valid input high time. Control pins (STB, OE) are tested separately with all device data inputs at VCC-O.4V.
2. Interchanging of force and sense conditions is permitted.

CAUTION:

These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

5-91

Specifications 82C83H/883
TABLE 2. 82C83HJ883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

(NOTES 1,2)
CONDITIONS

SYMBOL

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

TIMING REQUIREMENTS
Propagation Delay,
Input to Output

TIVOV(1)

vee = 4.5 end 5.5V

9,10,11

-55°C 5: TA 5: +1250 e

-

25

ns

Propagation Delay,
STB to Output

TSHOV(2)

vee = 4.5 and 5.5V

9,10,11

-55°C 5: TA 5: +1250e

-

50

ns

Output Enable Time

TELOV(4)

vee = 4.5 and 5.5V

9,10,11

-550C 5: TA 5: + 125°C

-

45

ns

Input to STB Set Up
Time

TIVSL(5)

vee = 4.5 and 5.5V

9,10,11

-550 e5: TAS+1250e

0

-

ns

Inputto STB Hold
Time

TSLlX(6)

vee = 4.5 and 5.5V

9,10,11

-55°C 5: TA 5: + 125°C

30

-

ns

STB High Time

TXHSL(7)

vee = 4.5 and 5.5V

9,10,11

-550 e5:TAS+1250e

15

-

n8

NOTES: 1. All AC. parameters tested as per test load circuits and definitions in Test Load Circuits. Input rise and fall times area driven

2. Tested as follows: f = 1MHz, VIH
VOH~ 1.5V, VOl.s1.5V.

= 2.6V (VIH for STB ~ VCC -

0.5y), Vil

= OAV, Cl -

at 1nsN.

50pF (unless otherwise specified),

TABLE 3. 82C83H/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Input Capacitance

Output Capacitance

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

13

pF

12

pF

20

pF

TA=+250e

-

TA=+250e

-

15

pF

elN

vee = OPEN, f = 1 MHz,
Ali Measurements Referenced to Device GND

1,3

TA=+250e

1,4

COUT

vee = OPEN, f = 1 MHz,
All Measurements Referenced to Device GND

1,3

,

22

n8

-55°C 5: TA:$. +1250 e.

-

20

ns

1,2

-550C:$. TA:$. +1250 e

5

-

ns

vee = 4.5 and 5.5V

1,2

-55°C:$. TA S. +1250 e

10

-

ns

vee = 4.5 and 5.5V

1,2

-55°C :$.TA:$. +1250e

10

-

ns

1,4

TA=+250C

Output Disable Time

TEHOZ(3)

vee = 4.5 and 5.5V

1,2

-550e5:TA:$.+1250e

Input Rise/Fall Time

TR,TF(8)

vee = 4.5 and 5.5V

1

Propagation Deiay,
Input to Output

TIVOV(l)

vee = 4.5 and 5.5V

Propagation Delay,
STB to Output

TSHOV(2)

Output Enable Time

TELOV(4)

NOTES: 1. The parameters listed in table 3 are controlled via design or process parameters and are not directly tested. These pal'ameters are characterized
upon initial design and after major process and/or design changes.

2. Tested as lollows: I - 1MHz, VIH = 2.6V (VIH lor
VOL,:!; 1.5V.

STB~

VCC - O.5V), Vil - OAV, Cl

= 50pF (unless

otherwise specified), VOH.2: 1.5 V,

3. For Ceramic DIP package.
4. For Ceramic lCC package.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

SUBGROUPS

InHialTest

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3,8A,8B, 10, 11

-

1,2,3,7, 8A, 8B, 9, 10,11

Samples/5005

1,7,9

Group A
Groupse&D
CAUTION:

METHOD

..

These devices are sensitive

to electrOniC dl~charge. Proper I.C. handling procedures should

5-92

be followed .

82C83H/883
Timing Waveform

INPUTS

STB

TEHOZ(3) 3.0V
O.45V

OUTPUTS

All timing measurements are made at 1. 5V unless otherwise noted.

Test Load Circuits

OUTPUT

2.27V

1.5V

1.n
~

ao.n.
~

300PF*¢.

TEST
POINT

OUTPUT

3OOP

F*¢.

TEST
POINT

~
en

""a::

OW

::;::1:

u!!:
a::
W
TIVOV, TSHOV

OUTPUT

TELOV OUTPUT HIGH ENABLE

1.5V

2.27V

1.n
~

1.n.
~

3OOP

F*¢.

TEST
POINT

OUTPUT

5OpF* ¢.

TELOV OUTPUT LOW ENABLE

TEST
POINT

TEHOZ OUTPUT LOW/HIGH DISABLE

·Includes jig and stray capacitance

5-93

....

82C83H/883
Burn-In Circuits
82C83H1883 CERAMIC DIP

vee
F2
F2
F2
F2
F2
F2
F2
F2

el

Rl

~

Rl
Rl

A

Rl

A

Rl

A

Rl

vee

A

Rl

A

Rl

A
A

FO

Rl

A

Fl

82C83H/883 CERAMIC LCC

vee
F2 F2 F2

~

R4

R4

R4

R4

R4

R4

F2--"""-F2-....IV\J'V--I
F2-....IV\J'V--I

R4
F2--""Ir-_
R4

R4
R4

_~

F2--I\I\J\r--I ~J

P-" P-" r- .. p-", P-"
'9' 'lO! '11' '12' '13'

NOTES:
5.5V ± 0.5V GND = OV
VIH = 4.5V ± 10%
VIL = -0.2 to O.4V
Rl = 47kfl ± 5%
R2 = 2.okfl ± 5%
R3 = 1.0kfl ± 5%
R4 = 5.0kfl ± 5%
C1 = O.01/lF Minimum
FO = 100kHz ± 10%
Fl = FO/2. F2 F1/2. F3 F2/2

vee =

=

el

=

5-94

vee

~

82C83H/883

Metallization Topology
DIE DIMENSIONS:
138.6 x 155.5 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11 k.8. ± 2k.8.
GLASSIVATION:
Type: Si02
Thickness: 8k.8. ± 1 k.8.
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy (LCC has Gold
Preform)
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
2.0 x 105 Alcm 2

Metallization Mask Layout
82C83H/883

012

010

011

vee

000

~

002

<

",0:

0

....

::;::1:

<.>!!::

0:
....
D..

013
003
014

004

015

005

016

017

OE

GNO

STB

5-95

007

006

82C83H/883
Packaging t
20 PIN CERAMIC DIP

.005 MIN

~

t

'200~MAX'015
1.
.060

.940
.970

.285

P==================i

1

1r==':q:305==i

,

o·
is'

..:ill.

.100

.180

BSC
• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-8

20 PAD CERAMIC LCe
BOTTOM VIEW

.342
.358

.~~~ I
~~

.045
.055

I

.358

.063

".....r:======:I----I::;;~ .077

II n n n n n I

.onn
.089

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
..
Material: Gold/Tin (80/20)
Temperature: 3200 C ± 100C
Method: Furnace Braze

NOTE: All Dimensions are

~

• Dimensions are in inches.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPI,IANT OUTLINE: 38510 C-2

tMiI-M-38510 Compliant Materials, Finishes, and Dimensions.

5-96

Em HARRIS

82C83H

DESIGN INFORMATION

CMOS Octal Latching
Inverting Bus Driver

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
VCC and GND when the signal is at or near the input
switching threshold. Additionally, if the driving signal
becomes high impedance ("float" condition), it could create
an indeterminate logic state at the inputs and cause a
disruption in device operation.
The Harris 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(ST8 = logic zero for the 82C82/83H) and when the device
is disabled (DE = logic one for the 82C86H/87H). These
gated inputs disconnect the Input circuitry from the VCC
and ground power supply pins by turning off the upper
P-channel and lower N-channel (See Figures 1 and 2). No
current flow from VCC to GND occurs during Input transitions and invalid logic states from floating inputs are not
transmitted. The next stage Is held to a valid logIc level internal to the device.
D.C. input voltage levels can also cause an increase in ICC
if these Input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the Input
circuitry in its linear operating region (partIally conducting

state). The 82C8X series gated inputs mean that this
condition will occur only during the time the device is in the
transparent mode (ST8 = logic one). ICC remains below the
maximum ICC standby specification of 10llA during the
time inputs are disabled, thereby greatly reducing the
average power dissipation of the 82C8X series devices.

Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance speCified in the 82C83H data
sheet is determined by
I = CL (dv/dt)
Assuming that all outputs change state at the same time
and that dv/dt is constant;
(VCC x 80%)
I=CL
tR/tF
where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight
outputs.
I = (8 x 300 x 10- 12 ) x (5.0V x 0.8)/(20 x 10-9)
= 480mA
This current spike may cause a large negative voltage spike
on VCC which could cause improper operation of the
device. To filter out this noise, it is recommended that a
0.11lF ceramic-disc capacitor be placed between VCC and
GND at each device, with placement being as near to the
devIce as possible.

vee

vee

STB
INTERNAL

DATA I N - + - - - - - - i

DATA I N - - + - - - - - - +

DATA

FIGURE 1. 82C82/83H

IKTERNAL
DATA

FIGURE 2. 82C86H/87H GATED INPUTS
vee

STB

~~~
BUS
OATAIN--\-----4
~-A~-------A-----

FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS

5-97

INTERNAL
DATA

mlHARRIS

82C84A/883
CMOS Clock Generator Driver

June 1989

Pinouts

Features
• This Circuit is Processed in Accordance to Mil-Std-SS3 and is Fully
Conform ant Under the Provisions of Paragraph 1.2.1.

82C84A!883 (CERAMIC DIP)
TOP VIEW

• Generates the System Clock For CMOS or NMOS Microprocessors

VCC

• Up to 25M Hz Operation

Xl

• Uses a Parallel Mode Crystal Circuit or External Frequency Source

X2

• Provides Ready Synchronization
o

ASYNC

Generates System Reset Output From Schmitt Trigger Input

EA

• TTL Compatible Inputs/Outputs

FIC

• Very Low Power Consumption

OSC

• Single 5V Power Supply
o

RES

Military Operating Temperature Range .••.••...•.• -55oC to +125 o C

RESET

Description
82C84A!883 (CERAMIC LCC)
TOP VIEW

The Harris 82C84A/883 is a high performance CMOS Clock Generator-driver
which is designed to service the requirements of both CMOS and NMOS
microprocessors such as the 80C86, 80G88, 8086 and the 8088. The chip
contains a crystal controlled oscillator, a divide-by-three counter and complete "Ready" sychronization and reset logic.
Static CMOS circuit design permits operation with an external frequency
source from DC to 25MHz. Crystal controlled operation to 25M Hz is guaranteed with the use of a parallel, fundamental mode crystal and two small load
capacitors.
All inputs (except Xl and RES) are TTL compatible over temperature and
voltage ranges.

: ~ u$'0 u
Iw;c.:ca.u>x
U

CI)

c..>

.....

t~J L~J l~J a._OJ L!lJ

RDYl

1]

[ia

READY

X2

[f7 ASYNC

RDY2

EFI

AEN2

FIe

NC

~] r-., r-., ,,-"I r- .. r-", [f4
191 '10! 111111211

NC

I

Power consumption is a fraction of that of the equivalent bipolar circuits. This
speed-power characteristic of CMOS permits the designer to custom tailor
his system design with respect to power and/or speed requirements.

Functional Diagram
CONTROL
PIN

RES
XI
X2

F/C

PCLK

EFI

CLK

READV
ASYNC

Copyright

©

Harris Corporation 1989

5-98

LOGICAL 1

LOGICAL 0

FIG

External Clock

Crystal Drive

RES

Normal

Reset

ROYl
RDY2

Bus Ready

Bus Not Ready

AENl
AEN2

Address Disabled

Address Enable

1 Stage Ready
Synchronization

2 Stage Ready
Synchronization

ASYNC

82C84A/883
Pin Description
SYMBOL

DIPPIN
NUMBER

DESCRIPTION

TYPE

3,
7

I

AEN2.

ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective
Bus Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2
Two AEN signal inputs are useful in system configurations which permitthe processor
to access two Multi-Master System Busses. In non-Multi-Master configurations, the
AEN signal inputs are tied true (LOW).

RDY1,
RDY2

4,
6

I

BUS READY (Transfer Complete). ROY is an active HIGH signal which is an indication
from a device located on the system data bus that data has been received, or is available
RDY1 is qualified by AEN1 while RDY2 is qualified by AEN2.

ASYNC

15

I

READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization
mode of the READY logic. When ASYNC is low, two stages of READY synchronization are
provided. When AsYNc is left open or HIGH a single stage of READY synchronization is provided.

READY

5

0

X1,
X2

17,
16

0

FIe

13

I

FREQUENCY/CRYSTAL SELECT: FIe is a strapping option. ~hen strapped lOW. F/C permits
the processor's clock to be generated by the crystal. When F/C is strapped HIGH, ClK is
generated for the EFI input.

EFI

14

I

EXTERNAL FREQUENCY IN: When FIC is strapped HIGH, ClK is generated from the input
frequency appearing on this pin. The input signal is a square wave 3 times the frequency of
the desired CLK output.

ClK

8

0

PROCESSOR CLOCK: ClK is the clock output used by the processor and all devices which
directly connect to the processor's local bus. ClK has an output frequency which is 1/3
of the crystal or EFI input frequency and a 1/3 duty cycle.

PCLK

2

0

PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2
that of CLK and has a 50% duty cycle.

OSC

12

0

OSCilLATOR OUTPUT: OSC Is the output of the Internal oscillator circuitry. Its
frequency is equal to that of the crystal.

RES

11

I

RESET IN: RES is an active LOW signal which Is used to generate RESET. The 82C84A1883
provides a Schmitt trigger input so that an RC connection can be used to establish the
power-up reset of proper duration.

RESET

10

0

RESET: RESET is an active HIGH signal which is used to~et the 80C86 family
processors. its timing characteristics are determined by RES.

CSYNC

1

I

CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple
82C84As to be synchronized to provide clocks that are in phase. When CSYNC Is HIGH
the Internal counters are reset. When CSYNC goes lOW the internal counters are
allowed to resume counting. CSYNC needs to be externally synchronized to EFI. When
using the internal oscillator CSYNC should be hardwired to ground.

AEN1,

I

READY: READY is an active HIGH signal which is the synchronized ROY signal input.
READY is cleared after the guaranteed hold time to the processor has been met.
CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency
is 3 times the desired processor clock frequency."

GND

9

Ground

VCC

18

VCC: the +5V power supply pin. A 0.1 JlF capacitor between VCC and GND is
recommended for decoupling •
.. If the crystal inputs are not used X1 must be tied to

5-99

vee or GND and

X2 should be left open.

Specifications 82C84A/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •.••••••.•••••••.•.••••••.••..••.••••••. +8.0V
Input, Output or I/O Voltage Applied. • • •• GND-0.5V to VCC+0.5V
Storage Temperature Range •••••••••••••••.• -650C to +1500 C
JunctionTemperature •.•••••••••••••••••••.•••••••••• +1750 C
Lead Temperature (Soldering 10 sec) .•.••..•...•.•••••. +3000 C
ESD Classification ••.•.•••••••••••••••••.•.••••••••••• Class 1

Thermal Resistance
Sja
Ceramic DIP Package. • . • • • • • • • • . • •
860 C/W
Ceramic LCC Package. . • • • • . . • • • • •
730 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package .•.••••••••.•••.•..•.•••.••••• 580mW
Ceramic LCC Package •.•••••.•••••••.••.••••.•••.• 532mW
Gate Count •••••••••••••.•••••.•••.•••.•••••...•••• 50 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range ••.•••••••••••• -550C to + 1250C
Operating Voltage Range •••••••••••••••.••••.••• +4.5V to +5.5V
TABLE 1. 82C84A1883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

Logical One Input
Voltage

VIH

Logical Zero Input
Voltage

VIL

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

VCC = 5.5V (Notes 1, 2)

1,2,3

-55°C ;S TA ;S + 125°C

2.2

-

V

VCC = 4.5V (Notes 1, 2, 3)

1,2,3

-550C ;STA;S +1250 C

-

0.8

V

-

V

CONDITIONS

Reset Input High
Voltage

VIHR

VCC= 5.5V

1,2,3

-550C;S TA;S +1250 C VCC-0.8

Reset Input Low
Voltage

VlLR

VCC= 4.5V

1,2,3

-550 C;STA;S +1250 C

-

0.5

V

Reset Input
Hysteresis

VT+
VT-

VCC= 5.5V

1,2,3

-55°C ;STA;S +125 0 C

0.2VCC

-

V

Output High
Voltage

VOH

VCC = 4.5V, (Note 4)
10H = -4.0mA for CLK Output,
10H = -2.5mA for all others

1,2,3

-55°C ;STA;S +1250 C VCC-0.4

-

V

Output Low
Voltage

VOL

VCC = 4.5V, (Note 4)
10L = +4.0mA for CLK Output,
IOL = +2.5mA for all others

1,2,3

-550C ;STA::: +1250 C

-

0.4

V

II

VCC = 5.5V, VIN = GND orVCC
except ASYNC, X1 (Note 5)

.1,2,3

-55 0 C;STA$ +125 0 C

-1.0

+1.0

pA

1,2,3

-55°C '::;TA::: +125 0 C

-

40

mA

Input Leakage
Current
Operating Power
Supply Current

ICCOP

VCC = 5.5V, Ouputs Open,
Crystal Frequency = 25MHz,
(Note 6)

NOTES: 1. FIe is a strap option and should be held either ~ O.8V or ~ 2.2V. Does not apply to X1 or X2 pins.
2. Due to tast equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is guaranteed.
3. CSYNC pin Is tested with V1L

S o.av..

4. Interchanging of force and sense conditions is permitted.
5.

ASYNc pin includes an internal 17.5kfi nominal pull-up resistor. For ASYNC input at GND. ASYNc input leakage current = 300~ nominal.
X1 - crystat feedback Input.

6. f = 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

5-100

= 10M Hz.

Specifications 82C84A/883
TABLE 2. 82C84A/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and' 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
GROUP A
CONDITIONS SUBGROUPS

LIMITS
TEMPERATURE

MIN

MAX

UNITS

TIMING REQUIREMENTS
External Frequency
High Time

TEHEl(1)

9,10,11

-550 C:>.TA:>' +1250 C

13

-

ns

External Frequency
low Time

TELEH(2)

9,10,11

-55°C:>. TA:S +1250 C

13

-

ns

TElEl(3)

9,10,11

-55°C :S TA :S + 125°C

36

-

ns

TR1VCl(4)

9,10,11

-55°C => TA=>+ 1250C

35

-

ns

EFIPeriod
RDY1, RDY2 Active
Setup to ClK,
ASYNC=HIGH

9,10,11

-55°C => TA :S + 1250C

2.4

25

MHz

RDY1, RDY2 Active
Setup Time to ClK,
ASYNC=lOW

TR1VCH(5)

9,10,11

-55°C =>TA:;; +1250 C

35

-

ns

RDY1, RDY2 Inactive
Setup Time to ClK

TR1VCH(6)

9,10,11

-550C :;;TAS +1250 C

35

-

ns

RDY1, RDY2 Hold to ClK

TCLR1X(7)

9,10,11

-55°C :;;TA:;; +125 0C

0

-

ns

ASYNC Setup to ClK

TAYVCl(8)

9,10,11

-55°C :;;TAS +1250 C

50

-

ns

XTAl Frequency

(Note 2)

TCLAYX(9)

9,10,11

-55 0C:;;TA:>.+1250C

0

-

ns

TA1VR1V(10)

9,10,11

-55 0CSTAS +125 0 C

15

-

ns

AEN1,AEN2 HoldtoClK

TCLA1X(11)

9,10,11

-55°C :;;TAS +1250 C

0

-

ns

CSYNC Setup to EFI

TYHEH(12)

9,10,11

-550 C:;;TA:;;+1250C

20

-

ns

CSYNC Hold to EFI

TEHYl(13)

9,10,11

-55°C S TA:S +125 0C

20

-

ns

RES Setup to ClK

TI1HCl(15)

9,10,11

-550C STA S +1250 C

65

-

ns

ASYNC Hold to ClK
AEN1, AEN2 Setup to
RDY1,RDY2

(Note 3)

c.>!!::

RES Hold to ClK

TCLl1H(16)

(Note 3)

9,10,11

-55 0CSTA$.+1250C

20

-

ClK Cycle Period

TClCl(17)

(Note 6)

9,10,11

-550 CSTAS+1250C

125

ns

ClK High Time

TCHCl(18)

(Note 6)

9,10,11

-550 C:;;TAS+1250C

(1/3"
TClCl)
+2.0

-

ClKlowTime

TClCH(19)

(Note 6)

9,10,11

-550C:;;TA:;;+1250C

(2/3'
TClCl)
-15.0

-

ns

From 1.0Vto
3.0V

9,10,11

-55°C STA:;; +1250 C

-

10

ns

-

ns

-

ns

ClK Rise or Fall time

~

",;2
ow

:s::C

TIMING RESPONSES

TCH1CH2(20)
TCl2Cl1 (21)

PClK High Time

TPHPl(22)

(Note 6)

9,10,11

-550 CSTAS+1250C

TClCl
-20

PClK low Time

TPlPH(23)

(Note 6)

9,10,11

-550CSTA:;; +1250 C

TClCl
-20

Ready Inactive to ClK

TRYlCl(24)

(Note 4)

9,10,11

-550 CSTAS+1250C

-8

Ready Active to ClK

TRYHCH(25)

(Note 5)

9,10,11

-55°C STAS +1250 C

(2/3"
TClCl)
-15.0

CAUTION: These devices are sensitive to eleclronic discharge. Proper I.C. handli~g procedures should be followed.

5-101

-

ns

ns

ns
ns

II:

....w

Specifications 82C84A/883
TABLE 2. 82C84A1883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Device Guaranteed and 100% Tested

PARAMETER

GROUP A
(NOTE 1)
CONDITIONS SUBGROUPS

SYMBOL

LIMITS
TEMPERATURE

MIN

MAX

UNITS

TIMINIG RESPONSES (Continued)
ClK to Reset Delay

TCLll(26)

9,10,11

-550C5TA5+1250C

ClK to PClK High Delay

TClPH(27)

9,10,11

-550C5TA:S+1250C

ClK to PClK low Delay

TClPl(2S)

9,10,11

-550C5TA:S+1250C

OSC to ClK High Delay

TOlCH(29)

9,10,11

-550C :STA:S +1250 C

OSC to ClK low Delay

TOlCl(30)

9,10,11

-55°C :S TA :S + 125°C

-

40

ns

22

ns

22

ns

22

ns

35

ns

NOTES: 1. Tesled os follows: f = 2.4MHz. VIH = 2.611, VIL = O.4V. CL = 50pF. VOH = ~ 1.5V. VOL!f 1.5V. unless olherwise specified. REs and FIC musl
sw.ch belwoon 0.4V and VCC-0.4V. Inpul rise and fall limes driven al 1 nsN. VIL ~ VIL (max) - 0.4V for CSYNC pin. VCC = 4.5V and 5.5V.

2. Tested using EFI or X1 input pin.
3 .. Setup and hold necessary only to guarantee recognHion at next clock.
4. Applies only 10 T2 slates.
5. Applies only 10 T3 TW slales.

6. Tested with EFllnput frequency

= 4.2MHz.

TABLE 3 82C84A1883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

NOTES

TEMPERATURE

MIN

MAX

UNITS

-

10

pF

-

15

pF

CIN

VCC = OPEN, I = 1 MHz,
All Measurements
Relerenced to Device GND

1

TA=+25 0C

COUT

VCC = OPEN, I = 1 MHz,
All Measurements
Relerenced 10 Device GND

1

TA=+25 0 C

Input Capacitance

Output Capacitance

CONDITIONS

CSYNCWidlh

TYHYl(14)

1,2

-550C:S TA:S +1250 C

2'
TElEl

-

ns

OSCtoClK
High Delay

TOlCH(29)

1,2

-55°C :S TA :S + 125°C

-5

-

ns

OSC10 ClK
Low Delay

TO HCl(30)

1,2

-55 0C :STA S +1250 C

2

-

ns

NOTES: 1. The parameters listed In table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process andlor design changes.
2. Input lest signals must switch between VIL (max) - O.4V and VIH (min) + O.4V. RES and Fie must switch between O.4V and VCC-O.4V. Input rise
and fall limes driven al 1 nsN. VIL ~ VIL (max) - 0.4 V for CSYNC pin. VCC = 4.5V and 5.5V.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

InilialTest

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Tesl

100%

2,3, SA, S8, 10, 11

-

1,2,3,7,8A,S8,9,10,11

Samples/5005

1,7,9

Group A
GroupsC&D

CAUTION: These devices are sensitive to electroniC discharge. Proper I.C. handling procedures should be followed.

5-102

82C84A/883
Timing Waveforms
WAVEFORMS FOR CLOCKS AND RESET SIGNALS
NAME
EFI

CSC

ClK

PClK
tYHEH
(12)

CSYNC

----~~---------=~-~

RESET

NOTE: All liming measurements are made at 1.5 Volts, unless otherwise noled.

WAVEFORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVICES)
elK

RDY1.2 _ _ _--""'''-_"'1

READY

--------------~

WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES)

5-103

82C84A/883
Test Load Circuits
TEST LOAD MEASUREMENT CONDITIONS

-1

2.25V

OUTPUT FROM
DEVICE UNDER TEST

.

T

.

V

R = 740A· FOR ALL OUTPUTS
,EXCEPT CLK
463 A FOR CLK OUTPUT

CL

.

(SEE NOTE 3)

NOTES: 1. CL =100pF for CLK output
2. CL = 50pF for all outputs except CLK
3. CL tnetude. probe and jig capacHance

=

TCHCL, TCLCH LOAD CIRCUIT
CLK

Xl

Cl~

TCHCL, TCLCH LOAD CIRCUIT

X2

~C2

FIC
CSYNC

TRYLCL, TRYHCH LOAD CIRCUIT

TRYLCL, TRYHCH LOAD CIRCUIT

VCC

.....---1 EFl
AENl

ClK

CLK

Xl
24MHZC

FIC

READY

AENl
1----1 RDY2 READY

X2

AEN2
CSYNC

OSC

RDY2

FIC
AEN2
CSYNC

A.C. Testing Input, Output Waveform
INPUT

OUTPUT

+

VOH

VlH

OAY
1.5V

~'-_ _ _--J~ 1.5V

\IIl- 0.4'1

VOL

NOTE: Input test signals must swHch between VIL (maximum) -o.4V and vtH (minimum) +O.4V. REs and FIC must
swftch between O.4V and VCC -o.4Y. Input rise and fall times driven at 1noN. vtl < vtl (max) -O.4V for
CSYNC pin. VCC -4.5V and 5.5V.
-

5-104

82C84A/883

Burn-In Circuits
82C84A1883 CERAMIC DIP

vee

F9

R2

vee

R2

GND
F6
F5

R2

vee

R2

GND

F7
FB

R2

vee

R2

GND

82C84A1883 CERAMIC LCC

vee

F5

vee 12
F7
FB

el

R4
R4

OPEN
R4

R4

R4

R4

R4

ff4

OPEN

"-

NOTES:
vee = 5.5V ±0.5V. GND = OV
VIH =4.5V ±10%
VIL = -0.2 10 0.4V
Rl = 47kn. ±5%.
R2 = 10kn. ±5%.
R3 = 22kn. ±5%.
R4 = 1.2kn. ±5%.
el = om ~F (minimum)
FO = 100kHz ±10%
Fl = FO/2. F2 = F1/2 ••.• F12 = F11/2

5-105

OPEN

."

FlO
Fl
Fll

-'

.,,;2
oW

::;::C

c.>!!::

a:
w
a..

82C84A/883
Metallization Topology
DIE DIMENSIONS:
66.1 x 70.5 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11 kA ± 1 kA
GLASSIVATION:
Type: SI02
Thickness: akA ± 1kA
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy (LCC has Gold Preform)
Temperature: Ceramic DIP - 4600C (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
1.42 x 105 Ncm 2

Metallization Mask Layout
82C84A/883

X2
RDY1
ASYNC

READY

RDY2

EFI

AEN2

F/C

ClK

GND

RESET

5-106

:J

82C84A/883
Packaging t
18 PIN CERAMIC DIP

o·
15"

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
. SOLDER FINISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-6

20 PAD CERAMIC LCC
BOnOMVIEW

"050

~

.045
.055

sse

~
.358

.---J

"r:11=n=n=n=n=n II::!J
::t.::;;1

.073
.089

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 3200 C ± 100 C
Method: Furnace Braze

NOTE: All Dimensions are

~
Max

.063
.077

Tl
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-2

t MiI-M-38S10 Compliant Materials, Finishes, and Dimensions.

• Dimensions are in inches.

5-107

82C84A

mHARRIS
DESIGN INFORMATION

CMOS Clock Generator Drive
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Functional Description
Oscillator

Clock Generator

The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is derived.

The clock generator consists of a synchronous divide-bythree counter with a speCial clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to the EFI clock external to the 82C84A. This is
accomplished with two flip-flops. (See Figure 1). The counter output is a 33% duty cycle clock at one-third the input
frequency.

The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal Input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 '" C2) as
shown in the waveform figures are recommended. The output of the oscillator is buffered and brought out on OSC so
that other system timing signals can be derived from this
stable, crystal-controlled source.
TABLE A. CRYSTAL SPECIFICATIONS
PARAMETER
Frequency

TYPICAL CRYSTAL SPEC

Parallel

Unwanted Modes

-6dB (Minimum)

Load Capacitance

18-32pF

crystal oscillator or the EFI input as the clock for the + 3
counter. If the EFI input is selected as the clock source,
the oscillator section can be used independently for
another clock source. Output is taken from OSC.
Clock Oututs

2.4 - 25MHz, Fundamental, "AT" cut

Type of Operation

* The Fie input is a strapping pin that selects either the

The ClK output is a 33% duty cycle clock driver designed
to drive the 80C86, 80C88 processors directly. PClK is a
peripheral clock signal whose output frequency is 1/2 that
of ClK PClK has a 50% duty cycle.
Reset Logic

See Harris Publication T8-47 for recommended crystal specifications

CapaCitors C1, C2 are chosen such that their combined
capacitance
CT '" C1 x C2 (Including stray capacitance)
C1 + C2

The reset logic provides a Schmitt trigger input (RES) and a
synchronizing flip-flop to generate the reset timing. the
reset signal is synchronized to the falling edge of ClK. A
simple RC network can be used to provide power-on reset
by utilizing this function of the 82C84A.

matches the load capaCitance as specified by the crystal
manufacturer. This insures operation within the frequency
tolerance specified by the crystal manufacturer.

CLOCK
SYNCHRONIZE

>-+---+-1 0

o

Q

ER

FIGURE 1. CSYNC SYNCHRONIZATION
• NOTE: If EFllnpulis used, then cyrstal input X1 must be lied to VCC or GND and X2 should be left open. lithe cyrstal
i\puts are used, then EFI should be lied to vce or GND.

5-108

82C84A

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design Information only. No guarantee is Implied.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to accommodate two system busses. Each input has a qualifier (AENl
and AEN2, respectively). The AEN signals validate their
respective ROY signals. If a Multi-Master system is not
being used the AEN pin should be tied lOW.
Synchronization is required for all asynchronous active-going edges of either ROY input to guarantee that the ROY
setup and hold times are met. Inactive-going edges of ROY
in normally ready systems do not require synchronization
but must satisfy ROY setup and hold as a matter of proper
system design.
The ASvNc input defines two modes of READY synchronization operation.
When ASYNC is lOW, two stages of synchronization are
provided for active READY input signals. Positive-going
asynchronous READY inputs will first be synchronized to
flip-flop one a the rising edge of ClK (requiring a setup time
tR1VCH) and the synchronized to flip-flop two at the next

falling"edge of ClK, after which time the READY output will
go active (HIGH). Negative-going asynchronous READY
inputs will be synchronized directly to flip-flop two at the
falling edge of ClK, after which the READY output will go
inactive. This mode of operation is intended for use by
asynchronous (normally not ready) devices in the system
which cannot be guaranteed by design to meet the required
ROY setup timing, tR1VCl, on each bus cycle.
When ASYNC is high or left open, the first READY flip-flop
Is bypassed in the READY synchronization logic. READY
inputs are synchronized by flip-flop two on the falling edge
of ClK before they are presented to the processor. This
mode is available for synchronous devices that can be
guaranteed to meet the required ROY setup time.

ASYNc can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.

!3

",ill!
....

0

:IE:C

u!!::

~

5-109

82C85/883

alHARRIS
June 1989

CMOS Static Clock Controller/Generator
Pinouts

Features
• This Circuit is Processed in Accordance to Mil-Std-SS3 and is Fully
Conformant Under the Provisions of Paragraph .1.2.1.
.

82CB5/883 (CERAMIC DIP)
TOP VIEW

• Generates the System Clock For CMOS or NMOS Microprocessors
and Peripherals
• Complete Control Over System Operation for Very Low System
Power
~ Stop.,.Oscillator
~ Low Frequency
~ Stop-Clock
~ Full Speed Operation

VCC
XI
X2
ASYNC
EFI
RCY2

Fie

Cl.K

RES

OSC

• DC to 25MHz Operation (DC to SMHz System Clock)
• Generates 50% and 33% Duty Cycle Clocks (Synchronized) .

RESET

521 STOP

• Uses a Parallel Mode Crystal Circuit or External Frequency Source
START

• TTL Compatible Inputs/Outputs

SI

so

• 24 Pin Slimline Dual-In-Line or 28 Pad Square LCC Package
Options
• Single 5V Power Supply
o Military Operating Temperature Range ••••••••• -55 0 C to +125 0 C

82C85/883 (CERAMIC LCC)
TOP VIEW

Description
The Harris 82C851883 Static CMOS Clock Controller/Generator provides
complete control of static CMOS system operating modes and supports
full speed, slow, stop-clock and stop-oscillator operation .. While directly
compatible with the Harris 80C86 and 80C88 16-bit Static CMOS
Microprocessor Family, the 82C85/883 can also be used for
general system clock control.
For static system designs, separate signals are provided on the 82C85/
883 for stop (SO, S1 , S2/STOP) and start (START) control of the crystal
oscillator and system clocks. A single control line (SLO/FST) determines
82C85 fast (crystal/EFI frequency divided by 3) or slow (crystal/EFI
frequency divided by 768) mode operation. Automatic maximum mode
80C86 and 80C88 software HALT instruction decode logic in the 82C85/
883 enables software-based clock control. Restart logic insures valid
~Iock start-up and complete synchronization of system clocks.
h,e 82C85/883 is manufactured using the Harris advanced Scaled SAJIIV
CMOS process. In addition to clock control circuitry, the 82C85/883 also
contains a crystal controlled oscillator (up to 25M Hz), clock generation logic, complete "Ready" synchronization and reset logiC. This permits the
designer to tailor the system power-performance product to provide
optimum performance at low power levels.

Copyright @ Harris Corporation 1989

5-110

NC

RCY1

ASYNC
RDY2

!J

AEN2

~]

CLK ~]
GND 1~

FIC

mHARRIS

82C86H/883
CMOS Octal Bus Transceiver

June 1989

Features

Pinouts
82C8SH/883 (CERAMIC DIP)
TOP VIEW

• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the pr~visions of Paragraph 1.2.1.

VCC

• Full Eight Bit Bi-directional Bus Interface

AO

• Industry Standard 8286 Compatible Pinout

Al

Bo

• High Drive Capability:

A2

Bl

~

B Side IOL ••••••••••....••••••••.••••••••••••••••••.•••• 20mA

~

ASide IOL ••••••••••.•••••••••••••••••••••••.••••••••••• 12mA

B2

• Three-State Outputs

A4

Ba

A5

B4

• Propagation Delay ••••••••••••••••••••••••••• , •••••••.• 35ns Max.

B5

• Gated Inputs:
~ Reduce Operating Power
~

A7

Eliminate the Need for Pull-Up Resistors

B7

GND

o Single 5V Power Supply
o Low Power Operation - ICCSB

BS

OE

T

= 10llA

• Military Operating Temperature Range •..•.•••• -550 C to +125 0 C

82C8SH/883 (CERAMIC LCC)
TOP VIEW

Description
The Harris 82C86H/883 is a high performance CMOS Octal Transceiver
manufactured using a self-aligned silicon gate CMOS process (Scaled
SAJI IV). The 82C86H/8B3 provides a full eight-bit bi-directional bus
interface in a 20 pin package. The Transmit (T) control determines the data
direction. The active low output enable (OE) permits simple interface to the
BOC86, BOCB8.and other microprocessors. The 82CB6H/B83 has gated
inputs, eliminating the need for pull-up/pull-down resistors and reducing
overall system operating power dissipation.

C\I

..

0

tl
tl

0

< < < >

-..

L~J l~J l~J

Functional Diagram

Cl

I._q ~.!lJ

_
Aa 4'

r-

A4

rf7
B2
L_

A5

rfs
Ba
L_

AS

rf5
B4
L_

A7

rf4
B5
L_

L
.18
_

I-

,...

B1

(j)

Cl

Cl

TRUTH TABLE

=

H
L=
I=

T

OE

A

B

X
H
L

H
L
L

Hi-Z
I

Hi-Z

0

I

=

Output Mode
Don't Care
High Impedance

Logic One
Logic Zero
Input Mode

0
X=
Hi-Z =

0

PIN NAMES

Copyrigtlr@ Harris C-o.ojjNaliorr t989-

5-111

PIN

DESCRIPTION

AO-A7
BO-B7
T
OE

Local Bus Data I/O Pins
System Bus Data I/O Pins
Transmit Control Input
Active Low Output Enable

Specifications 82C86H/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ........................................ +8.0V
Input, Output or I/O Voltage Applied. • • •• GND-0.5V to VCC+0.5V
• Storage.Temperature Range ................. -650C to +1500C
Junction Temperature ................................ +1750C
Lead Temperature (Soldering 10 sec) ................... +3000C
ESD Classification .................................... Class 1

Thermal Resistance
eja
Ceramic DIP Package. • . . . • • • . • . . . • . • .
70 0C/W
Ceramic LCC Package. . • . • • • . • • • . • . • . 76 0C/W
Maximum Package Power Dissipation at +1250C
Ceramic DIP Package .............................. 720mW
Ceramic LCC Package ............................. 664mW
Gate Count ....................................... 265 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the devics. This is a stress only rating and operation
.of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range •.•.••.•••••••• -550C to +125 0 C
Operating Supply Voltage ...................... +4.5V to +5.5V
TABLE 1. 82C86H-S/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested
LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Logical One Input
Voltage

PARAMETER

SYMBOL
VIH

vec = 5.SV, (Note 1)

1,2,3

-550C:$. TA:;; +1250C

2.2

-

V

Logical Zero Input
Voltage

VIL

VCC=4.SV

1,2,3

-55°C :;;·TA:;; +1250C

-

0.8

V

VCC = 4.5V, OE = GND
IOH=-8.0mA
IOH=-4.0mA
10H = -10011A (Note 2)

1,2,3

-550C:$.TA:$.+12S0C
3.0
3.0
~CC-O.4

-

-

V
V
V

VCC = 4.5V, OE = GND
10L = +20.0mA
10L= +12.0mA(Note2)

'1,2,3

-

0.45
0.45

V
V

Output High Voltage
B Outputs
A Outputs
A and B Outputs

VOH

Output Low Voltage
B Outputs
A Outputs

VOL

CONDITIONS

-SSOC:$.TA:$.+1250C

-

Input Leakage Current

II

VCC=5.5V,
Pins9,11
VIN=GNDorVCC

1,2,3

-550 C:;;TA:$. +1250 C

-10.0

+10.0

IIA

Output Leakage Current

10

VCC=5.5V,
OE~ VCC -0.5V
VOUT = GND orVCC,
Pins 1-8, 12-19

1,2,3

-550 C:$.TA:$. +1250 C

-

10

IIA

VCC=5.5V,
Outputs Open,
VIN = VCC or GND

1,2,3

-550 C:$.TA:$.+1250C

-

10

IIA

Standby Power
Supply Current

ICCSB

NOTES: 1. VIH is measured by applying a pulse of magnitude = VIHmin to one data input at a lime and checking the corresponding device output for a valid
logical "1" during valid input high time. Control pins CT, OE) are tested separately with all device data inputs at VCC-O.4V.
2. Interchanging of force and sense conditions is permitted.

CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

5-112

Specifications 82C86H/883
TABLE 2. B2CB6H-5/BB3 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

Propagation Delay,
Input to Output

TIVOV(1)

Output Enable Time

TELOV(5)

(NOTES 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

VCC = 4.5 and 5.5V

9,10,11

-550 CsTAS+1250C

-

35

ns

VCC = 4.5 and 5.5V

9,10,11

-550C~TA:5. +125 0 C

-

65

ns

NOTES: 1. AC parameter lested as per test circuits and definitions in Timing Waveforms. Input rise and fall times are driven at lnsN.
2. Tested as follows: f = 1MHz, VIH = 2.6V, VIH for T (Transmit pin).?, vee

- O.SV. VIL = DAV, CL = 50pF (unless otherwise specified), VOH ~ 1.SV,

VOL.$. 1.SV.

TABLE 3. B2CB6H-5/BB3 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITIONS

CIN

VCC = OPEN, f = 1 MHz,
All Measurements
Referenced
to Device GND

Input Capacitance
B Inputs

NOTES

TEMPERATURE

MIN

MAX

UNITS

1,5

TA = +25 0 C

-

18

pF

-

15

pF

14

pF

10

pF

1,6

A Inputs

1,5
1,6

Input Capacitance
All Other Inputs

CIN

VCC = OPEN, f = 1 MHz,
All Measurements
Reference
to Device G ND

1,5

TA=+250e

-

13

pF

1,6

TA=+250C

-

7

pF

5

-

ns

Propagation Delay,
Input to Output

TIVOV(1)

vec = 4.5 and 5.5V

1,2,3

-550e~TA:5. +125 0 e

TransmiVReceive
Hold Time

TEHTV(2)

vee = 4.5 and 5.5V

1,2

-550e::;TA~ +125 0 e

5

-

ns

TransmiVReceive
Hold Time

TTVEL(3)

vee = 4.5 and 5.5V

1,2

-55 0 e :5.TA:5. +12Soe

10

-

ns

Output Disable Time

TEHOZ(4)

vec = 4.S and S.5V

1,2,3

-S50e~TA:5. +12Soe

S

35

ns

Input Rise/Fall Time

TR,TF(6)

VCC = 4.S and S.5V

1,2

-S5 0 C:5.TA:5. +12S o e

-

20

ns

Minimum Output

TEHEL(7)

vee = 4.S and S.SV

4

-SSoe:5.TA:5. +12SoC

3S

-

ns

TELOV(S)

vec = 4.S and S.SV

1,2,3

-ssoe < TA

S

-

ns

Enable High Time
Output Enable Time

~

,

< +12S o C

NOTES: 1. The parameters listed in table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.
2. AC parameter tested as per test circuits and definitions in Timing Waveforms. Input rise and fall times are driven at 1nsN.
3. Tested as follows: f
VOL~

= 1 MHz, VIH =

2.6V, VIH for T (Transmit

pjn)~

VCC

~

O.5V, VIL = O.4V, CL = 50pF (unless otherwise specified), VOH

1.SV.

4. A system limitation only when changing direction. Not a measured parameter.
5. For Ceramic DIP package.
6. For Ceramic LCC package.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

SUBGROUPS

100%/S004

-

Interim Test

100%/S004

1,7,9

PDA

100%

1

Final Test

100%

2,3, 8A, 8B, 10, 11

Group A

-

1,2,3,7, 8A, 8B,9, 10, 11

Samples/SOOS

1,7,9

Groupse&D
CAUTION:

METHOD

Initial Test

These devices are sensitive to electroniC discharge. Proper

I.e. handling
5-113

procedures should be followed.

~

1.5V,

""

",0:
OW
:::Ex
c..>!:::
0:
W

"-

82C86H/883
Timing Waveform
INPUTS

OUTPUTS

T

All timing measurments are made at 1.5V unless otherwise noted

Test Load Circuits
A SIDE OUTPUTS

J: J: J: J:
2.36V

1.5V

eo.n.

OUTPUT

TEST
POINT

100PF*~

75.n.

OUTPUT

so.n.

1.n.

TEST
POINT

OUTPUT

100PF*~

TIVOV
LOAD CIRCUIT

2.36V

1.5V

TEST
POINT

100PF*~

TELOV
OUTPUT HIGH ENABLE
LOAD CIRCUIT

OUTPUT

TEST
POINT

. 50pF* ~

TELOV
OUTPUT LOW ENABLE
LOAD CIRCUIT

TEHOZ
OUTPUT LOW/HIGH DISABLE
LOAD CIRCUIT

B SIDE OUTPUTS

J: J: J: J:
2.27V

1.5V

aon.

1.n.

OUTPUT

TEST
POINT

3OOPF*~

TIVOV
LOAD CIRCUIT

OUTPUT

2.27V

1.5V

1.n.

TEST
POINT

OUTPUT

3OOpF* ~

TEST
POINT

3OOPF*~

TELOV
OUTPUT HIGH ENABLE
LOAD CIRCUIT

TELOV
OUTPUT LOW ENABLE
LOAD CIRCUIT

.. Includes jig and stray capacitance

5-114

1.n.

OUTPUT

5OpF*

TEST
POINT

~

TEHOZ
OUTPUT LOW/HIGH DISABLE
LOAD CIRCUIT

82C86H/883
Burn-In Circuits
82C86H/883 CERAMIC DIP

vee
e1

~
A
A
A

vee

A
A
A
A

A

R1

vee

82C86H/883 CERAMIC LCC

e1

vee
F2 F2 F2

Rs Rs Rs

F3

Rs

~

!3
",;:2
QW

:;;:1:
... 2:

I--,\/VI_- F3

RS

RS

F2--,\/VI_-I

I--,\/VI_- F3

F2---'W"Ir---I

...........""',...,..-F3

RS

RS

RS

RS

I--,\/VI_- F3

F2---'\N"-~

RS

RS

I--'VV'V--

F2---'W"Ir---I

NOTES:

vee

= 5.5V ± O.5V GND = OV
VIH = 4.5V ± 10%
VIL = -0.2 to 0.4V
R1 = 47kfl ± 5%
R2 = 2.4kfl ± 5%
R3 = 1.5kfl ± 5%
R4 = 1kfl ± 5%
R5=5kfl±5%
C1

a:
W

RS

RS

F2--,\/VI_-I

= O.01pF minimum

FO = 100kHz ± 10%
F1 = FO/2, F2 = F1/2, F3 = F2/2

5-115

F3

....

82C86H/883

Metallization Topology
DIE DIMENSIONS:
138.6 x 155.5 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11 k~ ± 1 M
GLASSIVATION:
Type: Si0 2
Thickness:
± 1

8M

M

DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy (LCC has Gold Preform)
.
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 0 C (Max)

WORST CASE CURRENT DENSITY:
1.47 x 105 A/cm 2

Metallization Mask Layout
82C86H/883

A2

A1

AO

vee

BO

B1

82

B3

A7

DE

GND

T

5-116

B7

B6

82C86H/883
Packaging t
20 PIN CERAMIC DIP

--;
I

.285
.305

rI

o·

15'

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FlNISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 1QoC
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-8

20 PAD CERAMIC LCC

~

"'~

OW

::;;::C
<.>2:

II:
W

a..
.045
.055

.358

n

9L.~~g
--.l

I~I=n=n=n=n=n~III::U
.073
.089

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 320 0 C ± 1QoC
Method: Furnace Braze

NOTE: All Dimensions are

~
Max

I

~

1

• Dimensions are in inches.

.063

.077

Tl
INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-2

tMiI-M-38510 Compliant Malerials, Finishes, and Dimensions.

5-117

mHARRIS

82C86H

DESIGN INFORMATION
CMOS Octal Bus Transceiver
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
VCC and GND when the signal is at or near the input
switching threshold. Additionally, if the driving signal
becomes high impedance ("float" condit'ion), it could create
an indeterminate logiC state at the inputs and cause a
disruption in device operation.
The Harris 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device
is disabled (OE = logic one for the 82C86H/87H). These
gated inputs disconnect the input circuitry from the VCC
and ground power supply pins by turning off the upper
P-channel and lower N-channel (See Figures 1 and 2). No
current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not
transmitted. The next stage is held to a valid logic level internal to the device.
D.C. input voltage levels can also cause an increase in ICC
if these input levels approach the minimum VIH or maximum
VIL conditions. This is due to the operation of the input
circuitry in its linear operating region (partially conducting

state). The 82C8X series gated inputs mean that this
condition will occur only during the time the'device is in the
transparent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of lO~A during the
time inputs are disabled, thereby greatly reducing the
average power dissipation of the 82C8X series devices.

Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C86H/87H data
sheet is determined by
I = CL (dv/dt)
Assuming that all outputs change state at the same time
and that dv/dt is constant;
{VCC x 80%)
I=CL
tR/tF
where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight
outputs.
I = (8 x 300 x 10- 12 ) x (5.0V x 0.8)/{20 x 10- 9 )
= 480mA
This current spike may cause a large negative voltage spike
on VCC which could cause improper operation of the
device. To filter out this noise, it is recommended that a
0.1 ~F ceramic disc capaCitor be placed between VCC and
GND at each device, with placement being as near to the
device as possible.

vce

vcc

STB
DATAIN----+----------------+

INTERNAl
DATA

DATAIN----t----------------+

FIGURE 2. 82C86H/87H GATED INPUTS

FIGURE 1. 82C82/83H

5-118

INTERNAl
DATA

m

HARRIS

82C87H/883
CMOS Octal Inverting
Bus Transceiver

June 1989

Features

Pinouts
82C87H/883 (CERAMIC DIP)
TOP VIEW

• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.
• Full Eight Bit Bi-directional Bus Interface

AO

VCC

A1
A2

So
B1

A3

B2

• Three-State Inverting Outputs

A4

B3

• Propagation Delay ••.•••••••••••.•••••••••••••••••••••• 35ns Max.

As

B4

• Gated Inputs:
~ Reduce Operating I'ower

A6

BS

A7

B6

OE

B7

• Industry Standard 8287 Compatible Pinout
• High Drive Capability:
~ B Side IOL •••••••••••••••••••••••••••••••••••••••••••••• 20mA
~

~

ASide IOL •••••••••••••••••••.••••.••••••••••••••••••••• 12mA

Eliminate the Need for Pull-Up Resistors

o Single 5V Power Supply

• Low Power Operation - ICCSB
o

GND

= 10llA

Military Operating Temperature Range ••••••••• -55 0 C to +125 0 C

T

82C87H/883 (CERAMIC LCC)
TOP VIEW

Description
The Harris 82C87H/883 is a high performance CMOS Octal Transceiver
manufactured using a self-aligned silicon gate CMOS process (Scaled
SAJI IV). The 82C87H/883 provides a full eight-bit bi-directional bus'
interface in a 20 pin package. The Transmit (T) control determines the data
direction. The active low output enable (OE) permits simple interface to the
80C86, 80C88 and other microprocessors. The 82C87H/883 has gated
inputs, eliminating the need for pull-up/pull-down resistors and reducing
overall system operating power dissipation. The 82C87H/883 provides
inverted data at the outputs.

N

<

.

<<
0

t.)

~

1&

L~J 19J l~J .. _~ L~J

A3

L
riB
_
B1
ri7
B2
L_
ri6
B3
L_

_
41

A4
AS

r-

'15
L_

A6

r-

'14
L_

A7

Functional Diagram

B4

as

TRUTH TABLE
T

OE

A

B

X

H
L
L

Hi-Z
I

Hi-Z

0

I

H
L
H=
L=
I=

Logic One
Logic Zero
Input Mode

0 =
X=
Hi-Z =

0

Output Mode
Don't Care
High Impedance

PIN NAMES

Copyright @) HarriS Corporation 1989

5-119

PIN

DESCRIPTION

AO-A7
BO-B7
T
OE

Local Bus Data 1/0 Pins
System Bus Data 1/0 Pins
Transmit Control Input
Active Low Output Enable

Specifications 82C87H/883
Absolute MaxImum RatIngs

Reliability Infonnatlon

Supply Voltage .•...•.•.•..•.•....••.••.•••..•.•••••••• +s.ov
Input, Output or I/O Voltage Applied. • . •• GND-0.5V to VCC+0.5V
Storage Temperature Range •...•....•.•••.•• -650C to +1500 C
Junction Temperature ••••••••••••••••••.••••.•.•.•••• +175 0C
Lead Temperature (Soldering 10 sec) .••.••••••••••..••• +3000 C
ESD Classification •••..•.•.•••••••.•••••.••.••••••.•.. Class 1

Thermal Resistance
9ja
Ceramic DIP Package. • • • • • • . • . • • • . • • • 700 C/W
Ceramic LCC Package. . . • • . • • • • . • . . • • 76 0 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package .•••.•.••••••••••••••••.•..... 720mW
Ceramic LCC Package ••.••••.••••..•••••••.•••.... 664mW
Gate Count .....••.••.....•.••.......••••.••••.••. 265 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This ;s a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

OperatIng CondItIons
Operating Temperature Range •.•..•.••..•••. -550C to +1250C
Operating Supply Voltage ••.••••.•.••••••.••. :. +4.5V to +5.5V
TABLE 1. 82C87H-5/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Logical One Input
Voltage

VIH

VCC = 5.5V, (Note 1)

1,2,3

-550C~TA~+1250C

2.2

-

V

Logical Zero Input
Voltage

VlL

VCC=4.5V

1,2,3

-550C~TA~+1250C

-

O.S

V

VCC = 4.5V,OE= GND
10H=-S.OmA
IOH=-4.0mA
10H = -100pA (Note 2)

1,2,3

-550C~TA~+1250C

.-

V
V
V

VCC=4.5V,OE=GND
IOL = +20.OmA
10L = +12.0mA (Note 2)

1,2,3

-

0.45
0.45

VV

VCC= 5.5V,
Pins 9, 11
VlN = GND or vce

1,2,3

-550C~TA~+1250C

-10.0

+10.0

pA

VCC=5.5V,
OE~ VCC -0.5V,
VOUT=GNDorVCC,
Pins l-S, 12-19

1,2,3

-550C ~TA~ +1250 C

-

1Q

pA

VCC=5.5V,
Outputs Open,
VlN = VCC or GND

1,2,3

-550C~TA~+1250C

-

10

pA

Oulput High Voltage
B Outputs
A Outputs
A and B Outputs

VOH

Output Low Voltage
B Outputs
A Outputs

VOL

Input Leakage
Current

11

Output Leakage
Current

10

Standby Power
Supply Current

ICCSB

. CONDITIONS

3.0
3.0
~CC-0.4
-550C~TA~+1250C

NOTES: 1. VIH is measured by applying a pulse of magnitude = VIHmln to one data Input at a time and checking 'the corresponding device output for a valid
logical "1" during valid input high time. Control pins (T. OE) are tested separately with all device data inputs at VCC-O.4V.

2. Interchanging of force and sense condHions is permlHed.

CAUTION: These devices are sensHive 10 electronic discharge. Proper I.C. handling procedures should be followed.

5-120

Specifications 82C87H/883
TABLE 2. 82C87H-5/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTES 1,2)
CONDITIONS

Propagation Delay,
Input to Output

TIVOV(l)

Oulput Enable Time

TELOV(5)

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

VCC = 4.5 and 5.5V

9,10,11

-550C :5TA:5+1250C

-

35

ns

VCC = 4.5 and 5.5V

9,10,11

-55 0 C::::TA::::+1250C

-

65

ns

NOTES: 1. AC parameter tested as per test circuits and definitions in Timing Waveforms. Input rise and fall times are driven at 1 nsN.

= 1MHz, VIH = 2.6V, VIH for T (Transmft pin)? VCC - O.5V, VIL = O.4V, CL = 50pF (un lass otharwisa specified), VOH ?

2. Testad as follows: f
VOL ~ 1.5V.

1.5V,

TABLE 3. 82C87H-5/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITIONS

CIN

VCC = OPEN, f = 1 MHz,
All Measurements
Referenced
to Device GND

Input Capacitance
B Inputs

NOTES

TEMPERATURE

MIN

MAX

UNITS

1,5

TA=+250C

-

lB

pF

-

15

pF

14

pF

10

pF

-

13

pF

1,6

A Inputs

1,5
1,6

Input Capacitance
All Other Inputs

CIN

1,6

TA=+250C

-

7

pF

Propagation Delay,
Input to Output

TIVOV(l)

VCC = 4.5 and 5.5V

1,2,3

-550C ::::TA:::: +125 0 C

5

-

ns

TransmiVReceive
Hold Time

TEHTV(2)

VCC = 4.5 and 5.5V

1,2

-550 C::::TA::::+1250C

5

-

ns

TransmiVReceive
Hold Time

TTVEL(3)

VCC = 4.5 and 5.5V

1,2

-55 0 C:::TA:::+1250C

10

-

ns

VCC = OPEN, f = 1 MHz,
All Measurements
Reference
to Device GND

1,5

TA=+250C

Output Disable Time

TEHOZ(4)

VCC = 4.5 and 5.5V

1,2,3

-55°C ::::TA::: +1250 C

5

35

ns

Output Enable Time

TELOV(5)

VCC = 4.5 and 5.5V

1,2,3

-550C :5TA::; +1250 C

5

-

ns

tnput Rise/Fall Time

TR,TF(6)

VCC = 4.5 and S.SV

1,2

-55°C ::::TA::: +12S o C

-

20

ns

Minimum Output
Enable High Time

TEHEL(7)

VCC = 4.5 and S.SV

4

-550C ::::TA::: +125 0 C

35

-

ns

NOTES: 1. The parameters listed in lable 3 are controlled via design or process parameters and are nol directly tested. These parameters are characterized

upon initial design and after major process and/or design changes.
2. AC parameter tested as per test circuits and definitions in Timing Waveforms. Input rise and fall times are driven at 1 nsN.
3. Tested as follows: f

VOL

~

= 1 MHz. VIH = 2.6V. VIH for T (Transmit pin) ~ VCC - O.5V. VIL = O.4V. CL ... 50pF (unless otherwise specified). VOH

1.SV.

4. A syslem limitation only when changing direction. Not a measured parameter.
5. For Ceramic DIP package.
6. For Ceramic LCe package.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

SUBGROUPS

InitialTest

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3,BA,BB,10,11

-

1,2,3,7, BA, BB, 9,10,11

Samples/SOOS

1,7,9

Group A
GroupsC&D
CAUTION:

METHOD

These devices are senSitive to electrOnic discharge. Proper I.C. handling procedures should be followed.

5-121

~

1.5V.

82C87H/883·
Timing Waveform
INPUTS

OUTPUTS

T

All timing measurments are made at 1.5V unless otherwise noted

Test Load Circuits
A SIDE OUTPUTS

OUTPUT

J:
to5V

2036V

T.....

TEST

TpOINT

tOOPF*~

to5V

75.Q

OUTPUT

TEST
POINT

OUTPUT

TEST
POINT

TELOV
OUTPUT HIGH ENABLE
LOAD CIRCUIT

J:

ao.n.

OUTPUT

TEST
POINT

5OPF*~

tOOpF* ¢.

tOOPF*¢.

TIVOV
LOAD CIRCUIT

J:t.n.

2036V

TELOV
OUTPUT LOW ENABLE
LOAD CIRCUIT

TEHOZ
OUTPUT LOW/HIGH DISABLE
LOAD CIRCUIT

B SIDE OUTPUTS

to5V

2027V

OUTPUT

to5V

To,,, . J:80.n.
TEST

OUTPUT

±oPOINT
3OOpF*

~

TIVOV
LOAD CIRCUIT

300pF*

TEST
POINT

~

OUTPUT
.

TELOV
OUTPUT HIGH ENABLE
LOAD CIRCUIT

J:t.n.

300pF*

TEST
POINT

~

TELOV
OUTPUT LOW ENABLE
LOAD CIRCUIT

* Includes jig and stray capacitance

5-t22

J:t.n.
2027V

OUTPUT

5OpF*

TEST
POINT

~

TEHOZ
OUTPUT LOW/HIGH DISABLE
LOAD CIRCUIT

82C87H/883 CERAMIC LCC

C1

VCC

F2 F2 F2
R5 R5 R5

F3
R5

~
!3

F2
F2
F2
F2
F2

R5

R5

R5

R5

R5

R5

R5

R5

R5

R5

NOTES:

vee = 5.5V ± 0.5V. GND = OV
VIH = 4.5V ± 10'lb
VIL = -0.2 to 0.4V
R1 = 47kO ± 5%
R2 = 2.4kO ± 5%
R3 = 1.5kO ± 5%
R4=1kO±5%
R5 = 5kO ± 5%
C1 = O.01JlF minimum
FO = 100kHz ± 10%
F1 = FO/2, F2 = F1/2, F3 = F2/2

5-123

"'~
....

0

F3
F3
F3
F3
F3

::;::l:
c.>!!::
IX:
....
....

82C87H/883

Metallization Topology
DIE DIMENSIONS:
138.6 x 155.5 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kA ± 2kA
GLASSIVATION:
Type: Si02
Thickness: 8kA ± 1kA
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy (LeC has Gold Preform)
Temperature: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 0 C (Max)
WORST CASE CURRENT DENSITY:
1.47 x 105 A/cm 2

Metallization Mask Layout
82C87H/883

A2

A1

vee

AD

BO

B1

B2

A3
B3

A4

B4

A5
B5
A6

A7

OE

GND

T

5-124

B7

B6

82C87H/883
Packaging t
20 PIN CERAMIC DIP

----t

.285

t--

I

.305

I

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOUDER FINISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 1QoC
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter:. 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-8

20 PAD CERAMIC LCC
BOTTOM VIEW

~

",<2
C ...

::;::1:
... !!:

.......
II:

.050

~

.045
.055

BSC

~
.358

1

.063

,..r======-I~-:::!.J .077

II ~ ~ ~ ~ ~ II

.073T1
.089

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Gold/Tin (80/20)
Temperature: 3200 C ± 1QoC
Method: Furnace Braze

NOTE: AU Dimensions are

~
Max

• Dimensions are in inches.

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method. Ultrasonic
COMPLIANT OUTLINE: 38510 C-2

tMil-M-38510 Compliant Materials, Finishes, and Dimensions.

5-125

82C87H

mHARRIS
DESIGN INFORMATION

CMOS Octal Inverting
Bus Transceiver

The information contained in this section has been developed through characterization by Harris'Semiconductor and is for
use as application and design information only. No guarantee is implied.

Gated Inputs

state). The 82C8X series gated inputs mean that this'
condition will occur only during the time the device is in the
During normal system operation of a latch, signals on the
transparent mode (STB = logic one). ICC remains below the
bus at the device inputs will become high impedance 'or
maximum ICC standby specification of 10flA during the
make transitions unrelated to the operation of the latch.
time inputs are disabled, thereby greatly reducing the
These unrelated input transitions switch the input circuitry
average power dissipation of the 82C8X series devices.
and typically cause an increase in .power dissipation in
CMOS devices by creating a low resistance path between Decoupling Capacitors
VCC and GND when the signal is at or near the input
The transient current required to charge and discharge the
switching threshold. Additionally, if the driving signal
. 300pF load capacitance specified in the 82C86H/87H data
becomes high impedance ("float" condition), it could create
sheet is determined by
an indeterminate logic state at the Inputs and cause a
I = CL (dv/dt)
disruption in device operation.
..
Assuming that all outputs change state at the same time
The Harris 82C8X series of bus drivers eliminates these
and that dv/dt is constant;
.
conditions by turning off data inputs when data is latched
(VCC
x
80%)
(STB = logic zero for the 82C82/83H) and when the device
I=CL
is disabled (OE = logic one for the 82C86H/87H). These
tR/tF
gated inputs disconnect the input circuitry from the VCC
20ns, VCC 5.0\1, CL 300pF on each eight
and ground power supply pins by turning off the upper where tR
P-channel and lower N-channel (See Figures 1 and 2). No outputs.
current flow from VCC to GND occurs during input transi- I = (8 x 300 x 10- 12) x (5.0V x 0.8)/(20 x 10-9)
tions and invalid logic states from floating inputs are n9~
480mA
transmitted. The next stage is held to a valid logic level interThis current spike may cause a large negative voltage spike
nal to the device.
on VCC which could cause improper operation of the
D.C. input voltage levels can also cause an increase in ICC device. To filter out this noise, it is recommended that a
if these input levels approach the minimum VIH or maximum 0.1 flF ceramic disc capacitor be placed between VCC and
VIL conditions. This is due to the operation of the input GND at each device, with placement being as near to the
circuitry in its linear operating region (partially conducting device as possible.

=

=

=

=

VCC

VCC

STB
DATA IN

---.,1--------+

INTERNAL
DATA

DATA IN --"11---------+

FIGURE 1. 82C82/83H

FIGURE 2. 82C86Hi87H GATED JNPUTS

5-126

INTERNAL
DATA

82C88/883

(DHARRIS

CMOS Bus Controller

June 1989

Pinouts

Features
• This Circuit is Processed in Accordance to Mil-Std-883 and is Fully
Conformant Under the Provisions of Paragraph 1.2.1.

82C88/883 (CERAMIC DIP)
TOP VIEW

• Compatible with Bipolar 8288

so

• Performance Compatible with: 80C86/80C88, ....•..••. (S/8MHz)
80186/80188 •..•••••••• (G/8MHz)
8086/8088 •••...•••••••• (S/8MHz)
8089

MCE/PDEN

• Provides Advanced Commands for Multi-Master Busses

DEN

52

• Three-State Command Outputs

CEN

• Bipolar Drive Capability

INTA

• Scaled SAJI IV CMOS Process

IORC

• Single SV Power Supply

AIOWC

• Low Power Operation
.. ICCSB .••••••••••..•.••••••••••.•••••••••• '••••••..• 1 OflA (Max)
.. ICCOP ••••••••••••.••••••••••••••••••.•••••••• 1mAlMHz (Max)
• Military Operating Temperature Range ••.•••••• -SSoC to

IOWC

GND

82C88/883 (CERAMIC LCC)
TOP VIEW

+125 0 C

Ll
~ III
Ll
Ll Q > I~
L~J L~J t~J L~q: t!J.:

lUi

Description
The Harris 82C88/883 is a high performance CMOS Bus Controller
manufactured using a self-aligned silicon gate CMOS process (Scaled
SAJIIV). The 82C88/883 provides the control and command timing signals
for 80C86, 80C88, 8086, 8088, 8089, 80186, and 80188 based systems.
The high output drive capability of the 82C88/883 eliminates the need for
additional bus drivers.

DT/R

52

ALE

MCEt PDEN

AEN

DEN

MRDC
AMWC

Static CMOS circuit design insures low operating power. The Harris
advanced SAJI process results in performance equal to or greater than
existing equivalent products at a significant power savings.

-.-"

41

-.-"

81

r-., r-.,

r-"I

r-., r-.,

19 1110! 111111

I~

C

Z

(!)

I~

I~

.-

CEN

114
INTA
L_

'1

I~

Functional Diagram

-- r--r--- r---

CONTROL {
INPUT

CU<
AEN
CEN
lOB

-

--

-I>
-I>
-I>

STATUS
DECODER

I
CONTROL
LOGIC

-I>

I

©

CONTROL
SIGNAL
GENERATOR

DT/A
} ADDRESS LATCH
DEN _ _
DATA TRANSCEIVER,
MCEt PDEN
AND INTERRUPT
ALE
CONTROL SIGNALS

f

"OCT,"U.·
COMMAND
SIGNALS

I

VCC

Copyrighl

COMMAND
SIGNAL
GENERATOR

MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
INTA

I

I

GND

Harris Corporation 1989

5-127

™MULTIBUS IS AN INTEL CORP. TRADEMARK

en

-'

""a:
:;::X:
en

OW

c.>!!:
a:
W

...

··82C88/883
Pin Description
PIN
SYMBOL

NUMBER

VCG

20

TYPE

DESCRIPTION
VCG: The +5V power supply pin. A 0.1 ~F capacitor between pins 10 and 20 is
recom'"!1ended for decoupling.
GROUND.

GND

10

SO,S1

I

52

19,3
18

STATUS INPUT PINS: These pins are the input pins from the 80G86, 80G88,
8086/88,8089 processors. The 82C88/883 decodes these inputs to generate
command and control signals at the appropriate time. When Status pins are not in use
(passive), command outputs are held HIG H (See Table A in Design Information Section)

CLK

2

I

CLOCK: This is a CMOS compatible input which receives a clock signal from the
82C84A or 82G85 clock generator and serves to establish when command/control
signals are generated.

ALE

5

0

ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address
latches. This signal Is active HIG H and latching occurs on the falling (HIGH to LOW)
transition. ALE is intended for use with transparent 0 type latches, such as the
82C82 and 82C83H.

DEN

16

0

DATA ENABLE: This signal serves to enable data transceivers onto either the local or
system data bus. This signal is active HIGH.

DT/R

4

0

DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through
the transceivers. A HIGH on this line indicates Transmit (write to I/O or memory) and a
LOW indicates Receive (read from I/O or memory).

AEN

6

I

ADDRESS ENABLE: AEN enables command outputs of the 82C88/883 Bus Controller a
minimum of 110ns (250ns maximum) after it becomes active (LOW). AEN going inactive
immediately three-states the command output drivers. AEN does not affect the I/O
command lines if the 82C88/883 is in the I/O Bus mode (lOB tied HIGH).

CEN

15

I

COMMAND ENABLE: When this signal is LOW all 82C88/883 command outputs and the
DEN and PDEN control outputs are forced to their Inactive state. When this signal is
HIGH, these same outputs are enabled.

108

1

I

INPUT/OUTPUT BUS MODE: When the lOB pin is strapped HIGH, the 82C88/883 functions
in the I/O Bus mode. When it is strapped LOW, the 82C88/883 functions in the System Bus
mode (See I/O Bus and System Bus sections).

AIOWC

12

0

ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier
in the machine cycle to give I/O devices an early indication of a write instruction. Its
timing is the same as a read command signal. AIOWC is active LOW.

10WC

11

0

I/O WRITE COMMAND: This command line instructs an I/O device to read the data on
the data bus. The signal is active LOW.

10RC

13

0

I/O READ COMMAND: This command line instructs an I/O device to drive its data onto
the data bus. This signal is active LOW.

AMWC

8

0

ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command
earlier in the machine cycle to give memory devices an early indication of a write
instruction. Its timing is the same as a read command signal. AMWC is active LOW.

MWTC

9

0

MEMORY WRITE COMMAND: This comman,d line Instructs the memory to record the
data present on the data bus. This signal is active LOW.

MRDC

7

0

MEMORY READ COMMAND: This command line instructs the memory to drive its data
onto the data bus. MRDCis active LOW.

INTA

14

0

INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its
Interrupt has been acknowledged and that it should drive vectoring information onto the
data bus. This signal is active LOW.

MCE/PDEN

17

0

This Is a dual function pin. MCE (lOB IS TIED LOW) Master Cascade Enable occurs
during an interrupt sequence and serves to read a Cascade Address from a master
82C59A Priority Interrupt Controller onto the data bus. The MCE signal is active HIGH.
PDEN (lOB IS TIED HIGH): Peripheral Data Enable enables the data bus transceiver for
the IsO bus that DEN performs for the system bus. PDEN is active LOW.

5-128

Specifications 82C88/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ........................................ +8.0V
Input, Output or I/O Voltage Applied. • • .• GND-0.5V to VCC+0.5V
Storage Temperature Range .......••.••...•• -650 C to +150 0 C
Junction Temperature ................................ +175 0 C
lead Temperature (Soldering 10 sec) ••.•.......•....... +3000 C
ESD Classification .................................... Class 1

Thermal Resistance
0ja
Ojc
Ceramic DIP Package ..•.•..•......... 77.80 C/W 18.90 CIW
Ceramic lCC Package ...•.••......... 76.0 0CIW 19.0oCIW
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package .............................. 646mW
Ceramic lCC Package ............................. 664mW
Gate Count ....................................... 100 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range •..•..•.••••••• -550C to +1250 C
Operating Supply Voltage ....•................. +4.5V to +5.5V
TABLE 1. 82C88/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

LIMITS

(NOTE 1)

GROUPA

CONDITIONS

SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

1,2,3

-550C~TA~ +1250 C

2.2

-

V

1,2,3

-550C~TA.s. +1250 C

-

0.8

V

1,2,3

-55 0C ~ TA~ +1250 C VCC-0.8

-

V

1,2,3

-550C~TA.s.+1250C

-

0.8

V
V
V

Logical "1" Input
Voltage

VIH

Logical "0" Input
Voltage

Vil

ClK logical "1"
Input Voltage

VIHC

ClK logical "0"
Input Voltage

VllC

Output HIGH Voltage,
Command Outputs

VOH1

10H = -S.OmA, Note 2
10H = -2.5mA, Note 2

1,2,3

-550C~TA.s.+1250C

3.0
VCC-004

Output HIGH Voltage,
Control Outputs

VOH2

IOH = -4.0mA, Note 2
IOH = -2.5mA, Note 2

1,2,3

-550C~TA~

+1250 C

3.0
VCC-004

-

Output lOW Voltage,
Command Outputs

VOL1

10l = +12.0mA, Note 2

1,2,3

-550C~TA.s. +1250 C

-

0.5

V

Output lOW Voltage,
Control Outputs

VOl2

10l = +8.0mA, Note 2

1,2,3

-550C~TA.s. +1250 C

-

004

V

VCC = 5.5V, VIN = GND
or VCC, All Inputs
Except SO, 51,52

1,2,3

-55 0C..:s;TA..:s; +125 0C

-1.0

+1.0

flA

VlN = 2.0V, Note 3
VCC=5.5V

1,2,3

-550C~TA~+1250C

-50

-300

flA

10

VCC = 5.5V, VOUT =
GND or VCC,IOB =
GND,AEN=VCC

1,2,3

-550C~TA.s.+1250C

-10

+10

flA

Standby Power Supply
Current

ICCSS

VCC=5.5V,
VIN=GNDorVCC,
Outputs Open

1,2,3

-550C~TA~+1250C

-

10

flA

Operating Power
Supply Current

ICCOP

VCC = 5.5V, Note 4

1,2,3

-55 0C.!>.TA.!>. +125 0C

-

1

mNMHz

Input leakage Current

Input Current
Bus Hold High
Output Leakage Current

NOTES: 1.

"
IBHH

VCC=5.5V

VCC=5.5V

-

vee = 4.SV unless otherwise specified. All voltage referenced to device GND.

2. Interchanging of force and sense conditions is permitted.

SO, 51, S2 to VCC
vec or GND.

3. IBHH should be measured after raising VIN on
4. Frequency"'" 10MHz, outputs open, VIN

CAUTION:

=

and then lowering to valid input high level of 2.0V.

These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

5-129

V
V

~

",;2
OW
::::c
c..>!!::
II:
W

a..

Specifications 82C88/883
TABLE 2. 82C88/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1,2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS
ns

CLK Cycle Time

(l)TCLCL

9,10,11

-550C5TA5+1250C

125

CLKLowTime

(2)TCLCH

9,10,11

-55°C !!:
0:

LU

"-

82C89/883:

m.HARRIS

CMOS Bus Arbiter

June 1989

Pinouts

Features
• This Circuit is Processed in Accordance to MiI-Std~SS3 a~d is' Fully
Conformant Under the Provisions of Paragraph 1.2.1.

82C89/883 (CERAMIC DIP)
TOP VIEW

• Pin Compatible with Bipolar S2S9
81'

• Compatible with 5MHz and SMHz.SOCS6 and SOCS'S

so

SYSBI
RESB

• Provides Multi-Master System Bus Control and Arbitration

CLK

• Provides Simple Interface with S2CSS/S2SS Bus Controller
• Synchronizes SOCS6/S0S6, .SOCSS/SOSS Processors with MultiMaster Bus

LOCK
INIT

CROLCK
ANYROST.

• Bipolar Drive Capability
• Four Operating Modes for Flexible System. Configuration

BPRO

• Low Power Operation
~ ICeSB ••••••••••••••••••••••.• ~ •••••••••.•••••••• 1 OflA Maximum
~ IceoP .••••••••••••••••••••••••••••••••••• .' 1mA/MHzMaximum
• Military Operating Temperature Range ••••••••• -55 0 C to +125 0 C

82C89/883 (CERAMIC LeC)
TOP VIEW

inlffi

Description
The Harris 82C89/883 Bus Ariblter Is manufactured using a self-aligned .
silicon gate CMOS process (Scaled SAJI IV). This circuit, along with the
82C88 bus controller, provides full bus arbitration and control for multiprocessor systems. The 82C89/883 is typically used in medium to large
80C86 or 80C88 systems where access to the bus by several processors
must be coordinated. The 82C89/883 also provides high output current .
and capacitive drive to eliminate the need for additional bus buffering.
Static CMOS circuit design insures low operating power. The advanced
Harris SAJI CMOS process results in performance equal to or greater than
existing equivalent products at a significant power savings.

u

~ ll! I~ IV!

§1 lUi

_. L~': LgJ L~J .2.: t~J

RESB

BPRO

~~

~1

[f8

r-., r-., r-" r-., r-.,

CLK

[f6
[fs
[f4

LOCK

19 11 1011 111112111

Functional Diagram
INIT}
.
BCLK
BREO
MULTIBUS'"
BPRN
COMMAND
BPRO
SIGNALS
BUSY
CBRO
.

8OC86/{ .

80C88
STATUS

. .

S~~~~;I~'c{
OPTIONS

{

. LOCK
CLK
-CR-O-L-C-K
RESB
ANYROST

.

lOB

AEN

-r~L--,"!",-"'"

}

.SYSBI ~~~!~

~--~------------------i---RESB

.

GND

+5V

TMMUl"JIBU9 IS AN INTEL CORP. TRADEMARK

Copyrighl @ Harris Corporalion 1989

5-138

So

[f7

CROLCK
ANYROST

82C89/883
Pin Description
SYMBOL

PIN
NUMBER

VCC

20

TYPE

DESCRIPTION
VCC: The +5V Power supply pin. A 0.1 ~F capacitor between pins 10 and 20 is recommened
fordecoupllng.

GND

10

SO,S1,S2

1,1B-19

I

STATUS INPUT PINS: The status Input pins from an BOCB6, BOCBB or BOB9 processor. The
B2CB9/BB3 decodes these pins to initiate bus request and surrender actions. (See Table A in
Design Information.)

ClK

17

I

CLOCK: From the B2CB4A or B2C85 clock chip and serves to establish when bus arbiter
actions are Initiated.

lOCK

16

I

lOCK: A processor generated signal which when activated (low) prevents the arbiter from
surrendering the multi-master system bus to any other bus arbiter, regardless of its priority.

CRQLCK

15

I

COMMON REQUEST lOCK: An active low signal which prevents the arbiter from surrendering the multi-master system bus to any other bus arbiter requesting the bus through the
CBRQ input pin.

RESB

4

I

RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having
both a mUlti-master system bus and a Resident Bus. Strapped high, the multi-master system
bus is requested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the
SYSB/RESB input is ignored.

ANYRQST

14

I

ANY REQUEST: A strapping option which permits the multi-master system bus to be
surrendered to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when
a lower priority arbiter requests the use of the multi-master system bus, the bus is
surrendered as soon as it ill possible). When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Information. If ANYRQST Is strapped high and CBRQ is activated, the bus is surrendered at the end of the present bus cycle. Strapping CBRQ low and
ANYRQST high forces the B2CB9/BB3 arbiter to surrender the multi-master system bus alter
each transfer cycle. Note that when surrender occurs BREQ is driven false (high).

lOB

2

I

10 BUS: A strapping option which configures the B2CB9/BB3 Arbiter to operate in systems
having both an 10 Bus (Peripheral Bus) and a multi-master system bus. The arbiter requests
and surrenders the use of the multi-master system bus as a function of the status line, 52. The
multi-master system bus is permitted to be surrendered while the processor is performing 10
commands and is requested whenever the processor performs a memory command. Interrupt
cycles are assumed as coming from the peripheral bus and are treated as an 10 command.

AEN

13

a

ADDRESS ENABLE: The output of the B2CB9/BB3 Arbiter to the processor's address latches,
to the B2CBB Bus Controller and B2CB4A or B2CB5 Clock Generator. AEiii serves to instruct
the Bus Controller and address latches when to three-state their output drivers.

INIT

6

I

INITIALIZE: An active low multi-master system bus input signal used to reset all the bus
arbiters on the multi-master system bus. After initialization, no arbiters have the use of
the multi-master system bus.

SYSB/
RESB

3

I

SYSTEM BUS/RESIDENT BUS: An input signal when the arbiter is configured in the System/
Resident Mode (RESB is strapped high) which determines when the multi-master system bus
is requested and multi-master system bus surrendering is permitted. The Signal is intended to
originate from a form of address-mapping circuitry, such as a decoder or PROM attached to
the resident address bus. Signal transitions and glitches are permitted on this pin from $1
ofT4 to $ 1 ofT2 ofthe processor cycle. During the period from $ 1 ofT2 to $ 1 ofT4, only
clean transitions are permitted on this pin (no glitches). If a glitch occurs, the arbiter may
capture or miss it, and the multi-master system bus may be requested or surrendered,
depending upon the state of the glitch. The arbiter requests the multi-master system bus in
the System/Resident Mode when the state of the SYSB/RESB pin Is high and permits the bus
to be surrendered when this pin is low.

GROUND.

5-139

82C89/883
Pin Description

(Continued)

SYMBOL

PIN
NUMBER

TYPE

CBRQ

12

I/O

DESCRIPTION
COMMON BUS REQUEST: An Input signal which instructs the arbiter if there are any
other arbiters of lower priority requesting the use of the muill-master system bus.
The CBRQ pins (open-drain output) of all the 82C89/883 Bus Arbiters which surrender to the
multi-master system bus upon request are connected together.
The Bus Arbiter running the current transfer cycle will not itself pull the CBRQ line low. Any
other arbiter connected to the CBRQ line can request the multi-master system bus. The
arbiter presently running the current transfer cycle drops its BREQ signal and surrenders
the bus whenever the proper surrender conditions exist. Strapping CBRQ low and
ANYRQST high allows the multi-master system bus to be surrendered after each transfer
cycle. See the pin definition of ANYRQST.

BClK

5

I

BUS CLOCK: The multi-master system bus clock to which all multi-master system bus
interface signals are synchronized.

BREQ

7

0

BUS REQUEST: An active low output signal in the Parallel PI ,ority Resolving Scheme
which the arbiter activates to request the. use of the multi-master system bus.

BPRN

g

I

BUS PRIORITY IN: The active low signal returned to the arbiter ~ruct it that it may
acquire the multi-master system bus on the next falling edge of BClK. BPRN active
indicates to the arbiter that it is the highest priority requesting arbiter presently on the bus.
The loss of BPRN Instructs the arbiter that It has lost priority to a higher priority arbiter.

BPRO

8

0

BUS PRIORITY OUT: An active low output signal used in the serial priority resolving
scheme where BPRO is daisy-chained to iiPRN of the next lower priority arbiter.

BUSY

11

I/O

BUSY: An active low open-drain multi-master system bus interface signal used to instruct
all the arbiters on the bus when the multi-master system bus is available. When the
multi-master system bus~lIable the highest requesting arbiter (determined by BPRiii)
seizes the bus and pulls BUSY low to keep other arbiters off of the bus. When the arbiter is
done with the bus, it releases the BUSv signal, permitting it to go high and thereby allowing
another arbiter to acquire the multi-master system bus.

5-140

Specifications 82C89/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ................................•....... +B.OV
Input, Output or I/O Voltage Applied ..... GND-0.5V to VCC+0.5V
Storage Temperature Range ...............•. -650C to +150 0 C
Junction Temperature ................................ +175 0 C
Lead Temperature {Soldering 10 sec) .....•............. +300 0 C
ESD Classification .................................... Class 1

Thermal Resistance
0ja
Ceramic DIP Package.. . . . . . . .. .. . .. • .
BOoC/W
Ceramic LCC Package. . •. . . . .. .. . .. . .
76 0 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ........•..........•....•....• 620mW
Ceramic LCC Package .......... , .................. 664mW
Gate Count ....................................... 200 Gates

CAUTION: Stresses above those fisted in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Temperature Range ............. '.. -550C to +125 0 C
Operating Supply Voltage ...................... +4.5V to +5.5V
TABLE 1. B2C89/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

LIMITS

{NOTE 1)

GROUPA

CONDITIONS

SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Logical "1 " Input
Voltage

VIH

VCC = 5.5V, Note 2

1,2,3

-55°C::; TA::; +125 0 C

2.2

-

V

Logical "0" Input
Voltage

VIL

Note 2

1,2,3

-55 0 C::;TA::; +125 0 C

-

O.B

V

CLK Logical "1 "
Input Voltage

VIHC

VCC=5.5V

1,2,3

-55 0 C::;TA:o;. +125 0 C

70%
VCC

-

V

CLK Logical "0"
Input Voltage

VILC

1,2,3

-55°C :o;.TA:o;. +125 0 C

-

20%
VCC

V

Output HIGH Voltage,
BUSY,CBRQ

VOHI

Open Drain, Note 3
DIP Pins 11,12

1,2,3

-55 0 C::;TA::;+1250C

-

-

V

Output HIGH Voltage,
All Other Outputs

VOH2

10H = -2.5mA, Note 3
10H = -100~A, Note 3

1,2,3

-55°C :5 T A :5 + 125°C

3.0
VCC-O.4

-

V
V

Output LOW Voltage,
BUSY, CBRQ

VOLI

10L = 20mA, Note 3,
DIP Pins 11,12

1,2,3

-55°C::; TA:5 +125 0 C

-

0.45

V

Output LOW Voltage,
AEN

VOL2

10L = 16mA, Note 3,
DIP Pin 13

1,2,3

-55°C::; TA:5 +125 0 C

-

0.45

V

Output LOW Voltage,
BPRO,BREQ

VOL3

10L = BmA, Note 3,
DIPPins7,B

1,2,3

-55 0 C::;TA:o;. +125 0 C

-

0.45

V

:::;;'"
c.>!!:

Input Leakage Current

II

VCC=5.5V,
VIN = GND orVCC
DIP Pins 1-6,9, 14-19

1,2,3

-55 0 C:5 TA:5 +125 0 C

-1.0

+1.0

~A

Output Leakage Current

10

VCC=5.5V,
VOUT = GND orVCC
DIP Pins 11,12

1,2,3

-55 0 C::;TA:o;. +125 0 C

-10

+10

~A

Standby Power Supply
Current

ICCSB

VCC=5.5V,
VIN = GND orVCC
Outputs Open

1,2,3

-55°C :o;.TA:o;. +125 0 C

-

10

~A

Operating Power
Supply Current

ICCOP

VCC = 5.5V, f = 1 MHz,
Outputs Open, Note 4

1,2,3

-55°C :5TA:o;. +125 0 C

-

1

mNMHz

NOTES; 1.

vee = 4.5V unless

otherwise specified. All voltage referenced to device GND.

2. Does not apply to "iC5i3. RESB, or ANYRQST. These are strap options and should be held to
3. Interchanging of force and sense conditions is permitted.

vee

or GND.

4. Maximum current defined by elK or BClK, whichever has the highest operating frequency.

CAUTION:

~

"'c:
OW

These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

5-141

c:

W
D..

Specifications 82C89/883
TABLE 2. 82C89/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER
CLK Cycle Time

SYMBOL

(NOTE 1)
CONDITIONS

(1)TCLCL

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE,

MIN

MAX

UNITS

9,10,11

-55 0 C:$.TA:$.+1250 C

125

-

ns

CLKLowTime

(2)TCLCH

9,10,11

-55 0 C'::;TA5 +1250 C

55

-

ns

CLK High Time

(3)TCHCL

9,10,11

-55 0 C:$.TA5 +125 0 C

35

~

ns

Status Active Setup
Time

(4)TSVCH

Note 2

9,10,11

-550C5TA5+1250C

65

-

ns

Status Inactive Setup
Time

(5)TSHCL

Note 2

9,10,11

-55 0C5TA5+125 0 C

50

-

ns

Status Inactive Hold
Time

(6)THVCH

9,10,11

-55 0 C:$.TA:$. +125 0 C

10

-

ns

Status Active Hold
Time

(7)THVCL

9,10,11

-550 C5TA:$.+1250 C

10

-

ns

BUSY" Setup to
BCLK

(B)TBYSBL

Note 3

9,10,11

-550 C5TA:$.+1250 C

20

-

ns

CBRO" Setup to

(9)TCBSBL

Note 3

9,10,11

-550 C5TA5 +1250 C

20

-

ns

9,10,11

-550C5TA5+1250C

100

-

ns

9,10,11

-550 C:$.TA:$.+1250 C

30

BcLK
BCLK Cycle Time

(10)TBLBL

BCLK High Time

(11)TBHCL

LOCK Inactive Hold
Time

(12)TCLLL1

9,10,11

-55 0 C:$.TA:$. +125 0 C

LOCK Active Setup
Time

(13)TCLLL2

9,10,11

BPRN- to BCLK
Setup Time

(14)TPNBL

SYSB/RESB Setup
Time

ns

10

-

-55 0 C5; TA:$.,+125 0 C

40

-

ns

9,10,11

-550 C5 TA5;+1250 C

20

-

ns

(15)TCLSR1

9,10,11

-550C5;TA5+1250C

a

-

ns

SYSB/RESB Hold
Time

(16)TCLSR2

9,10,11

-550 C:$.TA:$. +125 0 C

30

-

ns

Initialization Pulse
Width

(17)TIVIH

9,10,11

-550C5;TA5 +1250 C

675

-

ns

Note 2

Note 3

ns

BCLK to BREO"
Delay Time

(1B)TBLBRL

Note 3

9,10,11

~550C5;TA5 +125 0 C

-

35

ns

BCLK to BPRO"

(19)TBLPOH

Notes3,4

9,10,11

-550 C5;TA"5+1250 C

ns

Notes3,4

9,10,11

-550 C:$.TA:$.+1250 C

-

35

(20)TPNPO

22

ns

60

ns

65

ns

40

ns

60

ns

BPRN" to BPRO"
DelayTime
BCLK to BUSY Low

(21)TBLBYL

9,10,11

-550 C5TA5;+1250C

CLKtoAEN High

(23)TCLAEH

9,10,11

-55 0 C :$.TA:> +1250 C

BCLKtoAEN Low

(24)TBLAEL

9,10,11

-550 C 5; TA:> +1250 C

BCLK to CBRO Low

(25)TBLCBL

9,10,11

-550 C5;TA:>+125 0 C

-

Output Rise Time

(27)TOLOH

From O.BV to 2.0V
Except BUSY and CBRO

9,10,11

-550 C:$. TA:$. +1250 C'

-

20

ns

Output Fall Time

(2B)TOHOL

From 2.0V to O.BV
Except BUSY and CBRO

9,10,11

-55 0 C:$.TA:$.+125 0 C

-

12

ns

NOTES: 1. VCC = 4,SV and S.SV unless otherwise specified. Tested as follows: f = 1 MHz, VIH = 2,6V, VIL = OAV, VIHC = VCC - OAV. VILC = 0,4V, Load per
appropriate A.C. test circuit, VOH 2 1.5V and VOL.s. 1.5V. Input rise and fall times are driven at 1 nsN.
2. Reference Table 3 for maximum limit.
3. Both transitions of the signal apply to parameters with asterisks (tit).
4. BCLK generates EiPR"O from arbiter #1 wherein subsequent BPRO changes lower in the chain afe generated from
of the next higher
priority arbiter.

B'PRO

CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

5-142

Specifications 82C89/883
TABLE 3. 82C89/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

Input Capacitance

CIN

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

1

TA=+25 0C

-

10

pF

1

TA=+25 0C

10

pF

f = 1 MHz, all measure·
ments are reference to

CIO

1

TA=+25 0C

Status Active Setup
Time

(4)TSVCH

1,2,3

-55 0C.$.TA.$.+125 0C

-

Status Inactive Setup
Time

(5)TSHCL

1.2,3

-550C.$.TA.$.+125 0C

-

BCLK High Time

(ll)TBHCL

1,2,3

-550C.$.TA.$. +125 0 C

-

BCLK to BUSY Float
Time

(22)TBLBYH

1,2

-550C.$.TA.$. +125 0 C

BCLK to CBRQ Float
Time

(26)TBLCBH

1,2

-550 C.$.TA.$.+1250 C

Output Capacitance

COUT

I/O Capacitance

deviceGND,
VCC = Open

Input Rise Time

(29)TILIH

1,2

-55 0 C.$.TA.$. +125 0 C

Input Fall Time

(30)TIHIL

1,2

-550 C..$.TA.$. +125 0 C

15

pF

TCLCL
-10

ns

TCLCL
-10

ns

0.65
TBLBL

ns

-

35

ns

-

40

ns

20

ns

20

ns

-

NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.

2. vee = 4.5V and 5.5V
3. Reference Table 2 for minimum limit.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

SUBGROUPS

./ METHOD

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3,BA,BB, 10, 11

Group A

-

1,2,3,7, BA, BB, 9, 10, 11

Samples/5005

1,7,9

GroupsC&D

.

!:3

",a:
OW
:;::1:
<.>!!:
a:
W
a..

A.C. Test Load Circuits
BUSY, CBRO LOAD CIRCUIT

.

POINT

OUTPUT FROM
DEVICE
UNDER TEST

2.9V

~57'2A

TEST
POINT

~ lOOp?

Includes Stray and Jig Capacitance

These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

5-143

FROM~49'6::ST

OUTPUT
DEVICE
UNDER TEST

~ lOOp?

'*

CAUTION:

BREci LOAD CIRCUIT

2.9V

FROM~ozn.TEST

OUTPUT
DEVICE
UNDER TEST

BPRO,

AEN LOAD CIRCUIT

2.5V

POINT

~ lOOp?

82C89/883
A.C. Testing Input, Output Waveform
INPUT

OUTPUT

VlH +O.4V

VOH

1.5V

~'-_ _ _-';~ 1.5V

A.C. Toaling: Inpul. are driven at VIH +O.4V for a logic "1" and Vil -o.4V for
a logic "0". The clock Is driven al VCC -0.4V and 0.4V. Timing measurements
are made at l.5V for both a logic "1" and "0".

VOL

VlL -O.4V

Timing Waveform
STATE
CLK

sHOD
[lIfK

ISEE NOTE 11

SYSBIU

ill
ISEE NOTE 31
PROCESSOR CLK RELATED
BUS CLK RELATED

BRED H2

BPRN H2
IBPRD Nil
BPRD H2
lim N31

NOTES:

1. LOCK active can occur during any state, as long as the relationships shown above with respect to the eLK are maintained. [(5'Ci( Inactive has no critical
time and can be asynchronous. CRQLCK has no critical timing and is considered an asynchronous input signal.
2. GIRching of SYSB/iiffi is permiHed during this lime. After 02 01 Tl, and before 01 0lT4, SYSB/RESe should be stable to maintain system efficiency.
3. AEiij.lesding edge is related to

iiCtK, trailing edge to ClK. Th. trailing edge of liEN occurs an.r bus priorRy i. lost.

ADDITIONAL NOTES:
The signals relat.d to.ClK are typical proc.ssor signals, and do not relate to the deplcled .equ.nce 01 event. 01 the .Ignal. rel.renced to BcLK. Th. signals
shown related to the iClK represent a hypothetical sequence of events for illustration. Assume 3 bus arbiters of priorities 1. 2 and 3 configured in serial priority resolving .ch.m. (as shown In D••lgn Informalion FJgure 3). Assume arbRer 1 has the bus and is holdingBiJsYlow. ArbRer #2 d.tects R. processor wants
the bu. and pulls low BREa #2.11 BPRrii #2 i. high (as shown), arbil.r #2 wil pull low CiiiiQllne. CBRQ .Ignals to the hlgh.r priorHy arbiter #1 that a lower
prlorRy arbft.r wants the bus.IA higher prlorRy arbRer would be granted iiPRN when R make. the bus request rather than having to waR for anoth.r arbR.r to
release the bus through CBRQ). ""Arbiter #1 will relinquish the multi-master system bus when H enters a state not requiring it (see Design Information
lllble A), by lowering its iiPiffi #1 (lied to BPRN #2) and releasing BUSY. Arbller #2 now •••• that I. has priorHy from BPiiiii #2 being low and r.leases
CBRQ. As .oon a. BUSY slgnlfie. the bus Is available (high), arbiter #2 pulls iiii8Y' low on next falling edge of BClK. Note that Warbller #2 didn't want the
bus at the tim. R rec.lv.d priorHy, H would pass priorRy to the n.xt low.r priority arbiter by lowering its BPRO #2 (TPNPOI.
"Note that .v.n a higher priorlly arbRer which Is acquiring the bus through BPRN wil momentarily drop CBRQ until R has acquired the bus.

5-144

82C89/883
Burn-In Circuits
82C89/883 CERAMIC DIP

VCC
F7

F13
F14
F12
FO
vee

Cl

R2

~

R2
R2

R2

R2

R2

R2

R2

Rl

R2

F5
FO
F9
FlO

R2

F11
VCC/2

FB

82C89/883 CERAMIC LCC

Cl

VCC
F14F13 F7
R2 R2 R2

F6
R2

~
!3

R2
R2
R2
R2
R2

FB

veC/2

NOTES:

I. vee = 5.5V ± 0.5V, GND = OV
2. VIH = 4.5V ± 10%, VIL = -0.2V 10 +0.4V
3. Components Vafues:
RI = 1.2kn,1/4W, 5%
R2 = 47kn, 1/4W, 5%
C1

= O.01pF minimum

FO = 100kHz ± 10%
FI = FO/2
F2=FI/2 ...
FI4 = FI3/2

5-145

"'~

0'"

F5
FO
F9
FlO
Fll

::;;:C
c.>!:

...a:

Do

82C89/883
Metallization Topology
DIE DIMENSIONS:
92.9 x 95.7 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kA ±2kA
GLASSIVATION:
Type: Nitrox
Thickness: 10kA ± 2kA
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy
Temperature: Ceramic Dlp·- 4600 C (Max)
Ceramic LCC - 4200 C (Max)
WORST CASE CURRENT DENSiTY:
1.8 x 105 Ncm 2

Metallization Mask Layout
82C89/883

Ita

I~

It:l

RESB

ClK

iCiii

LOCK

INIT
CRDlCK

ANYRDST
BRED

I~

I~

I~

5-146

I~

82C89/883
Packaging t
20 PIN CERAMIC DIP

O·

15-

• INCREASE !.tAX WAIT BY .003 INCHES
MEASURED AT CENTER OF FlAT FOR
SOLDER FlNISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 385100-8

20 PAD CERAMIC LCC

BOTTOM VIEW

~
.D5D

.045
.055

esc

~
.358

--1

=0=0=0=0=0 II ~

"cll

::t.::;:;"'

.063
.077

,mIl
.089
PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Goldrrin (80/20)
Temperature: 320 0 C ± l00C
Method: Furnace Braze

NOTE: All Dimensions are

~
Max

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-2

tMiI-M-38510 Compliant Materials, Finishes, and Dimensions.

• Dimensions are in inches.

5-147

mHARRIS

82C89

DESIGN INFORMATION
CMOS Bus Arbiter
The Information contained In this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Functional Description

Arbitration Between Bus Masters

The 82C89 Bus Arbiter operates in conjunction with the
82C88 Bus Controller to interface 80C86, 80C88 processors to a multi-master system bus (both the 80C86 and
80C88 are configured In their max mode). The processor is
unaware of the arbiter's existence and issues commands as
though it has exclusive use of the system bus. If the processor does not have the use of the multi-master system bus,
the arbiter prevents the Bus Controller (82C88), the data
transceivers and the address iatches from accessing the
system bus (e.g. all bus driver outputs are forced into the
high impedance state). Since the command sequence was
not issued by the 82C88, the system bus will appear as
"Not Ready" and the processor will enter walt states. The
processor will remain in Wait until the Bus Arbiter acquires
the use of the multi-master system bus whereupon the
arbiter will allow the bus controller, the data transceivers,
and the address latches to access the system. Typically,
once the command has been issued and a data transfer has
taken place, a transfer acknowledge (XACK) is returned to
the processor to indicate "READY" from the accessed slave
device. The processor then completes its transfer cycle.
Thus the arbiter serves to multiplex a processor (or bus
master) onto a multi-master system bus and avoid contention problems between bus masters.

In general, higher priority masters obtain the bus when a
lower priority master completes its present transfer cycle.
Lower priority bus masters obtain the bus when a higher
priority master is not accessing the system bus. A strapping
option (ANYRQST) is provided to allow the arbiter to
surrender the bus to a lower priority master as though it
were a master of higher priority. If there are no other bus
masters requesting the bus, the arbiter maintains the bus so
long as its processor has not entered the HALT State. The
arbiter will not voluntarily surrender the system bus and has
to be forced off by another master's bus request, the HALT
State being the only exception. Additional strapping options
permit other modes of operation wherein the multi-master
system bus is surrendered or requested under different sets
of conditions.
Priority Resolving Techniques
Since there can be many bus masters on a multi-master
system bus, some means of resolving priority between bus
masters simultaneously requesting the bus must be provided. The 82C89 Bus Arbiter provides several resolving
techniques. All the techniques are based on a priority concept that at a given time one bus master will have priority
above all the rest. There are provisions for using parallel
priority resolving techniques, serial priority resolving techniques, and rotating priority techniques.

Functional Diagram

MULTIBUS
INTERFACE

80C86/{
8OC88
STATUS

L-~~

{

CaNTRall
STRAPPING
OPTIONS

1--+--:1~ }

MULTIBUSTM
COMMAND
SIGNALS

I--t--BPRN
BPRO
I-+-BUSY

1-+_

__.J·~--CBRQ

~~

CROLCK
RESB
ANYRQST
.

lOB

AEN

~.---..--"P'-"'"

SYSBI

~----------------------i---RESB

+5V

}

~~~

.

GND
TM MULTIBUS IS AN INTEL CORP. TRADEMARK

5-148

82C89

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Parallel Priority Resolving
The parallel priority resolving technique uses a separate
bus request line BREa for each arbiter on the multi-master
system bus, see Figure 1. Each BREa line enters into a priority encoder which generates the binary address of the
highest priority BREa line which is active. The binary'
address is decoded by a decoder to select the corresponding BPRN (Bus Priority In) line to be returned to the highest
priority requesting arbiter. The arbiter receiving priority
(BPRN true) then allows its associated bus master onto the
multi-master system bus as soon as it becomes available
(I.e., the bus is no longer busy). When one bus arbiter gains
priority over another arbiter it cannot immediately seize the
bus, it must wait until the present bus transaction is
complete. Upon completing its transaction the present bus
occupant recognizes that it no longer has priority and
surrenders the bus by releasing BUSY. BUSY is an active
low "OR" tied signal line which goes to every bus arbiter on
the system bus. When BUSY goes inactive (high), the arbiter
which presently has bus priority (BPRN true) then seizes the
bus and pulls BUSY low to keep other arbiters off of the bus.
See waveform timing diagram, Figure 2. Note that all multimaster system bus transactions are synchronized to the
bus clock (BCLK). This allows the parallel priority resolving
circuitry or any other priority resolving scheme employed to
settle.
Serial Priority Resolving
The serial priority resolving technique eliminates the need
for the priority encoder-decoder arrangement by daisychaining the bus arbiters together, connecting the higher
priority bus arbiter's BPRO (Bus Priority Out) output to the
BPRN of the next lower priority. See Figure 3.

74HCI38
HOB
DECOII£R

FIGURE 1. PARALLEL PRIORITY RESOLVING TECHNIQUE

NOTES:
1. Higher priority bus arbiter requests the Multi-Master system bus.
2. Attains priority.
3. Lower priority bus arbiter releases BUSY.
4. Higher priority bus arbiter then acquires the bus and pulls BUSY down.

FIGURE 2. HIGHER PRIORITY ARBITER OBTAINING THE BUS
FROM A LOWER PRIORITY ARBITER

Rotating Priority Resolving
The rotating priority resolving technique'is similar to that of
the parallel priority resolving technique except that priority
is dynamically re-assigned. The priority encoder is replaced
by a more complex circuit which rotates priority between
requesting arbiters thus allowing each arbiter an equal
chance to use the multi-master system bus, over time.
Which Priority Resolving Technique To Use
There are advantages and disadvantages for each of the
techniques described above. The rotating priority resolving
technique requires substantial external logic to implement
while the serial technique uses no external logic but can
accommodate only a limited number of bus arbiters before
the daisy-chain propagation delay exceeds the multimaster's system bus clock (BCLK). The parallel priority
resolving technique is in general a good compromise
between the other two techniques. It allows for many arbiters to be present on the bus while not requiring too much
logic to implement.

NOTE:
The number of arbiters that may be daisy-chained together in the serial priority resolving scheme is a function of'B'CI'K and the propagation delay from
arbiter to arbiter. Normally. at 10MHz only 3 arbiters may be daisychained.

FIGURE 3. SERIAL PRIORITY RESOLVING

5-149

82C89

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.
82C89 Modes Of Operation
There are two types of processors for which the 82C89 will
provide support: An InpuVOutput processor (i.e. an NMOS
8089 lOP) and the 80C86, BOC88. Consequently, there are
two basic operating modes in the 82C89 bus
arbiter. One, the lOB (I/O,Peripheral Bus) mode, perm'its the
processor access to both an I/O Peripheral Bus and a
multi-master system bus. The second, the RESB (Resident
Bus mode), permits the processor to communicate over
both a Resident Bus and a multi-master system bus. An I/O
Peripheral Bus is a bus where all devices on that bus,
including memory, are treated as I/O devices and are
addressed by I/O commands. All memory commands are
directed to another bus, the multi-master system bus. A
Resident Bus can issue both memory and I/O commands,
but it is a distinct and separate bus from the multi-master
system bus. The distinction is that the Resident Bus has
only one master, providing full availability and being dedicated to that one master.

V

J

In the lOB mode, the processor communicates and controls
a host of peripherals over the Peripheral Bus. When the I/O
Processor needs to communicate with system memory, it
does so over the system memory bus. Figure 5 shows a
possible I/O Processor system configuration.
The 80C86 and 80C88 processors can communicate with a
Resident Bus and a multi-master system bus. Two bus
controllers and only one Bus Arbiter would be needed
in suc!] a configuration as shown in Figure 6. In such a system configuration the processor would have access
to memory and peripherals of both busses. Memory
mapping techniques are applied to select which bus is to be

XI
X2
VCC
RDY 2 82C84A/85U
CLDCK
GENERATDR
. AEN2
READY
~RD~Y~II
CLK
AENI

r------;;:::===;-------------B2CB9
BUS
ARBITER

READY CLK .,

..-- I

I

j
'-----~

+
CLK CDNL~~DL -

ALE
i D EIN
fiE
STB
ADDRESS

II.

)

MULTI·MASTER SYSTEM'

1-------------,/. CDMMAND BUS

lOB ~
DT/A

~

I"-J-

+
DTiR

DE

B~~::~/C:~~::HV----------------:------'\)
~

MULTI·MASTER SYSTEM

~~~

FIGURE 4. TYPICAL MEDIUM COMPLEXITY CPU SYSTEM

5-150

MUL TI.MASTER
SYSTEM BUS

1-----'---'--------------"") ~~DL:~S~A:J~R SYSTEM

i:riB~~

B2CB3H
L-....:12;;.;o;;,..,3::..1--'

'------>,J

AEN
82CBB
BUS

STATUS ISO. 81.821

1

fAULTI·MASTER
rv--------------./~ CDNTRDL BUS

SD·S2 ill RESB

-~SD,t_L-----''-::==i, ~

ADD·AD15 SI
A16·A19 S2
•

XACK MULTI·MASTER
SYSTEM BUS

CLK_ ANYR;1-1
...._ _ _ _ _ VCC

I

BDCB6
CPU

PRDCESSDR
LDCAL BUS

The lOB strapping option configures the 82C89 Bus Arbiter
into the lOB mode and the strapping option. RESB
configures it into the RESB mode. It might be noted at this
point that if both strapping options are strapped false, the
arbiter interfaces the processor to a multi-master system.
bus only (see Figure 4). With both options strapped true, the
arbiter interfaces the processor to a multi-master system
bus, a Resident Bus, and an I/o Bus.

82C89

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

MULTI MASTER
CONTROL
~~====:::J BU.

I::=====::j MULTI MASTER SYSTEM

..

CIIMMAHD BUS

MULTI-MASTER
SYSTEM BUS

110 BUS

ADDRESS
BU.

-MASTER SYSTEM
t-'"::==::::::!~======:j MULTI
AIIDRESSBUS

1/'
DATA
BUS

"'::===========~MULTI-MASTERSYSTEM
f\I
IAURUS

'"

FIGURE 5. TYPICAL MEDIUM COMPLEXITY lOB SYSTEM

~~~IU IUS

1

- - - - -....

~

I.I.CIMUlTIMASTERIYSnMaUS

",ill!
0 ....

:;:=

... !!:

a:
....
....

'"===~==~

IIUlTIMUTusysnMCOM • .lIIaIUS

caM
••• DIUS't
USIDEU

MUlT' •• $TER

sun.eus

RESIDlI'

IOURusaus

\0-------1

DATA
UlIDElIl
BUS

<:=====~

MULTI ••srulnuMADDRlSSIU$

"FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYSTEM - RESIDENT BUS CONFIGURATION
• By adding another B2C89 arbiter and connecting Us AEN to the 82C88 whose
processor could have access to two multi-master buses.

5-151

AEN is presently grounded, the

82C89

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

accessed. The SYSB/RESB input on the arbiter serves to
instruct the arbiter as to whether or not the system bus is
to be accessed. The signal connected to SYSB/RESB
also enables or disables commands from one of the bus
controllers.

A summary of the modes that the 82C89 has, along with its
response to its status lines inputs, is shown in Table A.

TABLE A. SUMMARY OF 82C89 MODES, REQUESTING AND REUNQUISHING THE MULTI-MASTER SYSTEM BUS
lOB MODE
ONLY
lOB = LOW
RESB=LOW

STATUS LINES FROM
80C86 OR 80C88 OR
8088

RESB MODE ONLY
lOB = HIGH, RESB = HIGH
SYSB/RESB=
HIGH

SYSB/RESB=
LOW

SiSB/RESB=
HIGH

v
v
v

x

x

x

X
X

X
X

X
X

X

X

X

X

X
X
X

v
v
v

X
X
X

v
v
v

X

X

X

X

S2

51

SO

I/O
Commands

0
0
0

0
0
1

0

x

l'

X
X

Halt

0

1

1

X

X

Memory
Commands

1
1
1

0
0
1

0
1
0

v
v
v

v
v
v

Idle

1

1

1

X

X

0

lOB MODE RESB MODE
lOB = LOW, RESB = HIGH

SINGLE
BUS MODE
10B=HIGH
RESB = LOW

SYSB/RESB=
LOW

v
v

V

NOTES: 1. X = Multi-Master System Bus is allowed to be Surrendered.
2.

v = Multi-Master System Bus is Requested.
MULTI-MASTER SYSTEM BUS
PIN
STRAPPING

MODE

REQUESTED"",

SURRENDERED"

t

Single Bus
Multi-Master Mode

10B=Hlgh
RESB=Low

Whenever the processor's
status lines go active

HLT + TI • CBRa + HPBRa

RESB Mode Only

lOB = High
RESB = High

SYSB/RESB + High·
ACTIVE STATUS

(SYSB/RESB = Low + TI) •
CBRa + HLT + HPBRa

lOB Mode Only

lOB = Low
RESB Low

Memory Commands

(I/O Status + TI) • CBRa +
HLT+HPBRa

(Memory Command) •
(SYSB/REsB = High)

((I/O S~ommands~
SYSB/RESB Low) • CBRa
+HPBRa t + HLT

lOB Mode RESB Mode

=
lOB =Low
RESB =High

=

NOTES: * "LciCi( prevents surrender of Bus to any other arbiter, CFi"QIC'i( prevents surrender of Bus to any lower priority arbiter.
UExcept for HALT and Passive or 10 LE Status.

t

HPBRQ. Higher priority Bus request or BPiiN

1.

loB Active Low.

= 1.

2. RESB Active High.
3.

+ Is read as "OR" and

4. TI

• as "ANO"

= Processor Idle Status 52, 51, So -

111

5. HLT = Processor Hall Status 52, Si, So = 011

5-152

mHARRIS

82C284/883
Clock Generator and Ready Interface
for 80C286 Processors

June 1989

Features

Pinout

• This Circuit is Processed in Accordance to Mil-Std-883 and is
Fully Conformant Under the Provisions of Paragraph 1.2.1.

82C284/883 (CERAMIC DIP)
TOP VIEW

• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt Trigger Input
~

VCC

Improved Hysteresis

SRDY

• Uses Crystal or External Signal for Frequency Source
~ Dynamically Switchable Between Two Input Frequencies
• Provides Local READY and MULTIBUS@ READY
Synchronization

ARDYEN

SRDYEN

S1

READY

so

• Static CMOS Technology

EFI

NC

F/C

PCLK

• Single +5V Power Supply

X1

RESET

• Available in 18 Lead Cerdip Package

X2

RES

GND

CLK

Description
The Harris 82C284/883 is a clock generator/driver which provides clock
signals for 80C286 processors and support components. It also contains
logic to supply READY to the CPU from either asynchronous or synchronous sources and synchronous RESET from an asynchronous input with
hysteresis.

Functional Diagram
!1

",j!2
RES

-+--.....

0'"

:::c

RESET

D
SYNCHRONIZER 1------,

RESET

X1

X2
EFI
F/C

~>-++-- CLK

_~

_ _ _ _ _ _ _-J

ARDYEN
ARDY
SRDYEN _'------.1,-----.....

L.~~~t-----t1:--

SRDY
S1
SO

Copyright

READY

-+--<,,-,
---1r--2 01 TS.

2. If SRDY

5-159

82C284/883
Waveforms (Continued)

CLK AS A FUNCTION OF FIC, PCLK, X1, AND EFI
DURING DYNAMIC FREQUENCY SWITCHING

CLK
PCLK

FiG
X1

CLK
PCLK

FiG
EFI

NOTE: This is an asynchronous Input. The setup and hold times are required to guarantee the response shown.

5-160

82C284/883
Burn-In Circuit
18 PIN CERAMIC DIP

VCC

F7

Rl

F5

Rl
F6

Rl

VCC/2

Rl

Fl

Rl

F12

Rl

FO

Rl

VCC/2

Rl

GND

NOTES: 1. Supply Voltage: vee - 5.5V, ±0.5V, GND ~ OV
Driver Volt.go: VIH ~ 4.5V ± 10%, VIL

~

OV

2. Input Voltage Limits: VIL (Max) ~ 0.4V,
VIH (Min) ~ 2.6V
3. Component Values: Rl
Cl

~
~

47kn
0.1 pF (Min)

4. Oven type and frequency requirements microtest.
FO through F12

5. Approximate current per unit. ICC = O.3mA
6. Special requirements:
(a) Electrostatic Discharge Sensitive. Proper precautions must
be used when handling units.
(b) All power supplies must be at zero volls when the boards are
inserted into the ovens. After insertion. apply vee first, then
activate the driver power supplies.
7. Oscilloscope measurements:
insertion into the oven.

To be on loaded boards before

5-161

Fa
F9
FlO
NC
VCC/2
VCC/2
Fll
VCC/2

82C284/883
Metallization Topology
DIE DIMENSIONS:
63 x 69 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: akA
GLASSIVATION:
Type: Nitrox
Thickness: 10k'&'
DIE ATTACH:
Material: Gold - Silicon Eutectic Alloy
Temperature: Ceramic DIP - 46QOC (Max)
WORST CASE CURRENT DENSITY:
2 x 105 Ncm 2
LEAD TEMPERATURE (10 Seconds Soldering): 5. 30QOC

Metallization Mask Layout
82C284/883

vcc

AFii5YEN

S1
Siii5YEN

So
READY

NC
EFI

PCLK

FIe

RESET

Xl

X2

GND

CLK

5-162

RES

82C284/883
Packaging t
18 PIN CERAMIC DIP
.882
.005 MIN

I

~

.20~~MAX.015
1.

.915

ct==============l

.060

o·

15'

.125

.100

.180

BSC

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 1QoC
Method: Furnace Seal

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
• SOLDER FINISH

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-6

!J

en:!

0'"

~=
u!!:

...
II:

a...

NOTE: All Dimensions are

~~

t MiI-M-38S10 Compliant Materials, Finishes, and Dimensions.

• Dimensions are in inches.

5-163

82C284

mHARRIS
DESIGN INFORMATION

Clock Generator and Ready Interface
for 80C286 Processors

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is Implied.

Functional Description
INTRODUCTION
The 82C284 generates the clock, ready, and reset signals
required for 80C286 processors and support components.
The 82C284 is packaged in an 18 pin DIP and contains a
crystal controlled oscillator, clock generator, peripheral
clock generator, MUlTIBUSI!> ready synchronization logic,
and system reset generation logic.
CLOCK GENERATOR
The ClK output provides the basic timing control for an
80C286 system. ClK has output characteristics sufficient
to drive CMOS devices. ClK is generated by either an
internal crystal oscillator, or an external source as selected
by the Fie input pin. When Fie is lOW, the crystal
oscillator drives the ClK output. When Fie is HIGH, the EFI
input drives the ClK output.
The Fie pin on the Harris 82C284 is dynamically
switchable. This allows the ClK frequency to the processor
to be changed from one frequency to another In a running system. With this feature, a system can be designed
which operates at maximum speed when needed, and
then dynamically switched to a lower frequency to
Implement a low-power mode. The lower frequency can be

anything down to, but excluding, D.C. The following 3
conditions apply when dynamically switching the Fie pin
(see Figure 1):
1) The C lK is stretched in the low portion of the <1>2
phase of it's cycle during transition from one ClK
frequency to the other (see Waveforms).
2) When switching ClK frequency sources, there is a
maximum transition latency of 2.5 clock cycles of
the frequency being switched to, from the time ClK
freezes low, until ClK restarts at the new frequency
(see Waveforms).
3) The maximum latency from the time Fie is
'dynamically switched,to the time ClK freezes low,
is 4 ClK cycles (see Waveforms)~
The following steps describe the sequence of events that
transpire when Fie is dynamically switched:
(A) Fie switched from high (using EFI input) to low (using
the crystal input Xl - see Figure lA).
1) The state of Fie is sampled when both ClK and
PClK are high until a change is detected.
2) On the second following falling edge of PClK, ClK
is frozen low.
3) ClK restarts at the crystal frequency on the rising
edge of Xl, after the second falling edge of Xl.

CLK
PCLK

Ftc
Xl
(A)

FiE SWITCHED FROM HIGH (USING ER INPUT) TO LOW (USING THE CRYSTAL INPUT Xl)
CLK
PCLK

EFI
(8)

FIE SWITCHED FROM LOW (USING THE CRYSTAL INPUT Xl) TO HIGH (USING
FIGURE 1. DYNAMICALLY SWITCHING THE

5-164

FiE PIN

THE EFI INPUT)

82C284

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and. is for
use as application and design information only. No guarantee is implied.
(B) FIG switched from low (using the crystal input X1) to
high (using the EFI input - see Figure 1B).
1) The state of FIG is sampled when both ClK and
PClK are high until a change is detected.
2) On the second following falling edge of PClK, ClK
is frozen low.
3) ClK restarts at the EFI input frequency on the falling
edge of EFI after the second rising edge of EFI.
The 82C284 provides a second clock output, PClK, for
peripheral devices. PClK is ClK divided by two. PClK has
a duty cycle of 50% and CMOS output drive
characteristics. PClK is normally synchronized to the internal processor clock.
After reset, the PClK signal may be out of phase with the
internal processor clock. The S1 and SO signals of the first
bus cycle are used to synchronize PClK to the internal
processor clock. The phase of the PClK output changes by
extending its HIGH time beyond one system clock (see
Waveforms). PClK is forced HIGH whenever either SO or
S1 were active (lOW) for the two previous ClK cycles.
PClK continues to oscillate when both SO and S1 are
HIGH.
Since the phase of the internal processor clock will not
change except during reset, the phase of PClK will not
change except during the first bus cycle after reset.
OSCillATOR

The oscillator circuit of the 82C284 is a linear Pierce
oscillator which requires an external parallel resonant,
fundamental mode, crystal. The output of the oscillator is
internally buffered. The crystal frequency chosen should be
twice the required internal processor clock frequency. The
crystal should have a typical load capacitance of 32pF.
X1 and X2 are the oscillator crystal connections. For stable
operation of the OSCillator, two loading capacitors are
recommended, as shown in Table A. The sum of the board
capacitance and loading capacitance should equal the
values shown. It is advisable to limit stray board capacitances (not including the effect of the loading capacitors or
crystal capacitance) to less than 10pF between the X1 and
X2 pins. Decouple VCC and GND as close to the 82C284
as possible with a 0.1 flF polycarbonate capacitor.

ClK TERMINATION

Due to the ClK output having a very fast rise and fall time, it
is recommended to properly terminate the ClK line at
frequencies above 10MHz to avoid signal reflections and
ringing. Termination is accomplished by inserting a small
resistor (typically 10-740) in series with the output, as
shown in Figure 2. This is known as series termination. The
resistor value plus the circuit output impedance (approximately 250) should be made equal to the impedance of the
transmission line.
CLK
OUT

R

___

)z

CLOSELY
PLACED
LOADS

/

RO ~ 25\

J

TRANSMISSION UNE

~)

>-I

z

CLOSELY
PLACED
LOADS

'-----'
FIGURE 2. SERIES TERMINATION

RESET OPERATION

The reset logic provides the RESET output to force the
system into a known, initial state. When the RES input is
active (lOW), the RESET output becomes active (HIGH),
RES is synchronized internally at the falling edge of ClK
before generating the RESET output (see Waveforms).
Synchronization of the RES input introduces a one or two
ClK delay before affecting the RESET Output.
At power up, a system does not have a stable VCC and
ClK. To prevent spurious activity, RES should be
asserted until VCC and ClK stabilize at their operating
values. 80C286 processors and support components also
require their RESET inputs be HIGH a minimum of 16 ClK
cycles. An RC network, as shown in Figure 3, will keep RES
lOW long enough to satisfy both needs.
A Schmitt trigger input with hysteresis on RES assures a
single transition of RESET with an RC circuit on RES. The
hysteresis separates the input voltage level at which the
circuit output switches from HIGH to lOW from the input
voltage level at which the circuit output switches from lOW
to HIGH. The RES HIGH to lOW input transition voltage is
lower than the RES lOW to HIGH input transition voltage.
VCC

TABLE A. 82C284 CRYSTAL LOADING CAPACITANCE
VALUES
C1
CAPACITANCE
(PIN 7)

C2
CAPACITANCE
(PIN 8)

1 to8MHz

60pF

40pF

8to20MHz

25pF

15pF

20to25MHz

15pF

15pF

CRYSTAL
FREQUENCY

1N914

*

82C284

10k-O.
11

,-4""'-.....---..-----1 RES

~

.m

FIGURE 3. TYPICAL RC RES TIMING CIRCUIT

5-165

.
~

",a:
OW

:;::r:

<..)~

a:
W

c...

82C284

DESIGN INFORMATION

(Continued)

The Information contained in this section has been developed through characterization by Harris Sem'iconductor and Is for
use as application and design information only. 'No guarantee is implied.
'

As long as the slope of the RES input voltage remains in the
same direction (increasing or decreasing) around the RES
input transition voltage, the RESET output will make a single
transition.
. READY OPERATION
The 82C284 accepts two ready sources for the system
ready signal which terminates'the current bus cycle. Either
a synchronous (SRDY) or asynchronous ready (ARDY)
source may be used. Each ready input has an enable
(SRDYEN and ARDYEN) for selecting the type of ready
source required to terminate the current bus cycle. An
address decoder would normally select one of the enable
Inputs.

7

...L

,~

~Cl ~C2
SEE TABLE 2
FOR CAPACITOR
. VAWES

6

Xl

READY is enabled (lOW), If either SRDY + SRDYEN = 0 or
ARDY + 'AR'i5'Y'EN = 0 when sampled by the 82C284
READY generation logic. READY will remain active for at
least two ClK cycles.
The READY output has an open-drain driver allowing
other ready circuits to be wire or'ed with it, as shown in
Figure 4. The READY signal of an 80C286 system
requires an external pull-up resistor. To force the READY
signal Inactive (HIGH) at the start of a bus cycle, the
READY output floats when either Sl or SO are
sampled lOW at the falling edge of ClK. Two system clock
periods are allowed for the pull-up resistor to pull the
READY signal to VIH. When RESET is active, READY is
forced active one ClK later (see Waveforms).

CLK

10

CLK

VCC
X2

82C284
-- 4
READY

~

8OC2B6
CPU OR
SUPPORT
COMPONENT
READY

18
VCC I---+- VCC
F/C
..._ _ _ _-11
DECOUPUNG
CAPACITOR

I.V

FIGURE 4. RECOMMENDED CRYSTAL AND READY C,ONDITIONS

5-166

82C284

DESIGN INFORMATIO"N

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design -information only. No guarantee is implied.

Figure 5 illustrates the operation ot"SRDY and SRDYEN.
These Inputs are sampled on the falling edge of ClK when
Sl and SO are inactive and PClK is HIGH. READY is forced
active when both SRDY and SRDYEN are sampled
as lOW..
Figure 6 shows the operation of ARDY and ARDYEN. These
inputs are sampled by an internal synchronizer at each
falling edge of ClK. The output of the synchronizer is then

TS

sampled when PClK is HIGH. If" the synchronizer
resolved both the ARDY and ARDYEN as active,-the SRDY
and SRDYEN inputs are ignored. Either ARDY or ARDYEN
must be HIGH at the end of TS, therefore-at least one wait
state is required when using the ARDY and ARDYEN inputs
as a basis for generating READY.
READY remains - active until either Sl or SO are
sampled lOW, or the ready inputs are sampled as inactive.

TC

TC

ClK

PClK

VIH
ARDYEN------------~~-------------r--------------------~------~---------

Siiiiffi
+
SRDY
READY _________________r
RGURE 5. SYNCHRONOUS-READY OPERATION

TS

TC

TC

ClK

PClK

51'so
VIH
SRDYEN--------~~--~-~-~--~-------+t------1~--

ARDY
+
ARDYEN '

R~DY------------------~~

FIGURE 6. ASYNCHRONOUS READY OPERATION

5-167

82C288/883

mHARRIS

Bus Controller For 80C286 Processors

June 1989

Features

Pinout

• Compatible with NMOS 82288

20 PIN CERAMIC DIP

TOP VIEW

• Fully Static CMOS Design for Low Power Operation
~
~

ICCSB
ICCOP

= 10llA Maximum
= 1mA/MHz

• Provides Commands and Control for Local and System Bus
• Flexible Command Timing
• Optional MULTIBUS'" Compatible Timing
• Control Drivers with 16mA 10L and 3-State Command Drivers with
32mAIOL
• Single +5V Supply
• Available In 20 Pin Cerdlp Package

Description
The Harris 82C288/883 ~us Controller is a 20 pin CMOS component for
use In 80C286 microsystems. The Bus Controller provides command and
control.outputs with flexible timing options. Separate: command outputs
are used 10r memory and 110 devices. The data bus is controlled with sepa7
rate data enable and direction control signals. .
Two modes of operatlon i!lte POsli!tile'via a strapping option: MULTIBUS
compatible bus cycies. and fllgh speed bus cycles.

Functional Diagram
3-STAlE
COMMAND
STATUS

SO

[

51

OUTPUTS

~ iiffl.]
Kiill
iOWC
iiiiIii!
II\m

MliD

CLK-+--......
CONTROL
INPUTS
CEN/AEN
.CENL
. CMDLY

iiEADv
MB

MULTIBUS N is an Inlel Corporalion Trademark
Copyrighl

©

Harris Corporation 1989

5-168

Harris Semiconductor

------No. 109

-----

---------- ---

------

----------

Harris Microprocessor

June 1989

82C59A PRIORITY INTERRUPT CONTROLLER
Author: J. A. Goss
PAGE
Introduction

5-170

1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11

Glossary of Terms For The 82C59A ....................................... .
Automatic End-ol-Interrupt .......................•.........................
Automatic Rotation ........................................................ .
Buffered Mode ........................................................... .
Cascade Mode ........................................................... .
End-ol-Interrupt .......................................................... .
Fully Nested Mode ........................................................ .
Master ................................................................... .
Slave .................................................................... .
Special Fully Nested Mode ................................................. .
Special Mask Mode ....................................................... .
Specific Rotation .......................................................... .

5-170
5-170
5-170
5-171
5-171
5-171
5-172
5-172
5-172
5-172
5-172
5-172

2.0
2.1
2.2
2.3
2.4

Initialization Control Words .............................................. .
ICW1 ..................................................................... .
ICW2 .................................................................... .
ICW3 .................................................................... .
ICW4 .................................................................... .

5-173
5-173
5-175
5-176
5-176

3.0
3.1
3.2
3.3

Operation Command Words ............................................. .
OCW1 ................................................................... .
OCW2 ................................................................... .
OCW3 ................................................................... .

5-177
5-177
5-177
5-178

4.0

Addressing the 82C59A .................................................. . 5-179

5.0
5.1
5.2

Programming the 82C59A ................................................ . 5-180
Example 1: Single 82C59A ................................................. . 5-180
Example 2: Cascaded 82C59As ............................................ . 5-181

6.0

Expansion Past 64 Interrupts ............................................. . 5-182
Program Listing, Example 1 .............................................. . 5-183
Program Listing, Example 2 .............................................. . 5-188

CAUTION: These devices are sensitive 10 electrostatic discharge. Proper I.C. handling procedures should be followed.

5-169

!3

",jill
OW

::;::X:

u!!:

a::
W

....

82C59ACMOS .PROGRAMMABLE INTERRUPT CONTROLLER
By J. A. Goss

Introduction

1.0 Giossary of Terms for the 82C59A'

The Harris 82C59A is a CMOS Priority Interrupt
Controller, designed to relieve the system CPU from the
task of polling in a (I1ulti~level priority interrupt system.
The 82C59A is compatible with microprocessors such as
the 80C86, 80C88, 8086, 8088, 8080/85 and NSC800.

1.1 Automatic End of Interrupt (AEOI):

In the following discussion, we will look at the
initialization and operation process for the 82C59A. We
will focus our attention on 80C86/80C88-b'ased systems.
However, the infi:l'rmation presented will also be
applicable to use of the 82C59A in 8080 or 8085-based
systems as welL
Let us look.at the sequence of events that occur with the
82C59A during an interrupt request and service. In an
8080/85 based system:
(1) One or more of the INTERRUPT REQUEST lines (IRO
- IR7) are raised high, setting the corresponding bits
in the Interrupt Request Register (IRR).
(2) The interrupt is eva I uated in the priority resolver. If
appropriate, an interrupt is sent to the CPU via the
INT line (pin 17).
(3) The CPU acknowledges the interrupt by sending a
pulse on the INTA line. Upon reception of this pulse,
the 82C59A responds by forcing the opcode for a call
instruction (OCDH) onto the data bus.
(4) A second iNTA pulse is sent from the CPU. At this
time, the device will respond by placing the lower
byte of the address of the appropriate service routine
onto the data bus. This address is derived from ICWI.
(5) A final (third) pulse of INTA occurs, and the 82C59A
responds by placing the upper byte of the address
onto the data bus. This address is taken from ICW2.
(6) The three byte call instruction is then complete. If the
AEOI mode has been chosen, the bit set during the
first INTA pulse in the ISR is reset at the end of the
third INTA pulse. Otherwise, it will not get reset until
an appropriate EOI command is issued to the
82C59A.
For 80C86- and 80C88-based systems:
(1) and (2) same as above.

(3) The CPU responds to the interrupt request by pulsing
the INTA line twice. The first pulse sets the
appropriate ISR bit and resets the IRR bit while the
second pulse causes the interrupt vector to be placed
on the data bus. This byte is composed of the
interrupt number in bits 0 through 2, and bits 3
through 7 are taken from bits 3 - 7 of ICW2.
(4) The interrupt sequence is complete. If using theAEOI
mode, the bit set earlier in the ISR will be reset.
Otherwise, the interrupt controller will await an
appropriate EOI command at the end of the interrupt
service routine.

When the 82C59A is programmed to operate in the
Automatic EOI mode, the device. will produce its own
End-of-Interrupt (EOI) at the trailing edge of the last
Interrupt Acknowledge pulse (INTA) from the CPU. Using
this mode of operation frees the software (service
routines) from needing to send an EOI manually to the
82C59A.
However, using the Automatic EOI mode will 'u'pset'the
'priority structure of the 82C59A. When the AEOI is
generated, the bit that was set in the In-Service Register
(ISR) to indicate which interrupt is being serviced, will be
cleared. Because of this, while an interrupt is being
serviced there,will be no record inthe ISR that it is being
serviced. Unle~s interrupts are disabled by the CPU, there
is a risk that interrupt requests of lower or equal priority,
will interrupt the current request being serviced. If this
mode of operation is not desired, interrupts should not be
re-enabled by the CPU when executing interrupt service
routines.
1.2 Automatic Rotation:
During normal operation of the 82C59A, we have an
assigned order of priorities for the IR lines. There are
however, instances when it might be useful to assign
equal priorities to all ,interrupts. Once a particular
interrupt has been serviced, all other equal priority
interrupts should have an opportunity to be serviced
before the original peripheral can be serviced again. This
priority equalization can be achieved through Automatic
Rotation of. priorities..
Assume, for example, that the assigned priorities of
interrupts has IRO as the highest priority interrupt and IR7
as the lowest. Figure lA shows interrupt requests
occuring on IR7 as well as IR3. Because IR3 is of higher
priority, it will be serviced first. Upon completion of the
servicing of IR3, rotation occurs and IR3 then becomes
the lowest priority interrupt. IR4 will now have the highest
priority (see Figure lB).
There are two methods in which Automatic Rotation can
be implemented. First, if the 82C59A is operating in the
AEOI mode as described above, the 82C59A can be
programmed for "Rotate in Automat,ic EOI mode". This is
done by writing a command word to OCW2. The second
method occurs when using normal EOls. When an EOI is
issued by the service routine, the software can specify
that rotation be performed.
IR7 IR6 IR5 IR4 IR3 IR2 IRI
IRO

P:~:~~~ I

IRR

5-170

I I~ I I I: I I I
0

LOWEST
PRIORITY
FIGURE tA.

4

3

0

0

HIGHEST
PRIORITY

IR PRIORITIES (BEFORE ROTATION)

Application Note 109
When in cascade mode, the determination of whether a
device is a master or a slave can take either of two forms.
The state of the SP/EN pin will select "master" or" "slave"
mode for a device when the buffered mode is not being
used. Should buffered mode be used, then it is necessary
that bit 02 (MIS) of ICW4 besetto indicate if the particular
B2C59A is being used as a "master" or "slave" interrupt
controller in the system.

IR7 IR6 IRS IR4 IR3 IR2 IRI IRO

ISRp:~::I~~ I~==~I==O=:I
=0==1~=0=:1===I~=O=:I=O=S=I~=::I
LOWEST
HIGHEST

PRIORITY

PRIORITY

FIGURE 1B.

IR PRIORITIES (AFTER ROTATION)

The CASO-2 pins on the interrupt controllers serve to
provide a private bus for the cascaded B2C59As. These
lines allow the "master" to inform the slaves which is to be
serviced for a particular interrupt.

1.3 Buffered Mode:
When using the B2C59A in a large system, it may be
necessary to use bus buffers to guarantee data integrity
and guard against bus contention.

1.5 End of Interrupt (EOI):

By selecting buffered mode when initializing the device,
the SP/EN pin (pin 16) will generate an enable signal for
the buffers whenever the data outputs from the B2C59A
are active. In this mode, the dual function SP/EN pin can
no longer be used for specifying whether a particular
B2C59A is being used as a master or a slave in the system.
This specification must be made through setting the
proper bit in ICW4 during the device initialization.

When an interrupt is recognized and acknowledged by
the CPU, its corresponding bit will be set in the In-Service
Register (ISR). If the AEOI mode is in use, the bit will be
cleared automatically through the interrupt acknowledge
signal from the CPU. However, if AEOI is not in effect, it is
the task of software to notify the B2C59A when servicing
of an interrupt is completed. This is done by issuing an
End-of-Interrupt (EOI).

1.4 Cascade Mode:

There are 2 different types of EOls that can be issued to
the device; non-specific EOI and specific EOI. In most
cases, when the device is operating in a mode that does
not disturb the fully nested mode such as Special Fully
Nested Mode, we will issue a non-specific EOI. This form
of the EOI will automatically reset the highest priority bit
set in the ISR. This is because for full nested operation,
the highest priority IS bit set is the last interrupt level
acknowledged and serviced.

More than one B2C59A can be used in a system to expand
the number of priority interrupts to a maximum of 64
levels without adding any additional hardware. This
method of expansion is known as "cascading". An
example of cascading B2C59As is shown in Figure 2.
In a cascaded interrupt scheme, a single B2C59A is
utilized as the "master" interrupt controller. As many as B
"slave" B2C59As can be connected to the IR inputs of the
"master" B2C59A. Each of these slaves can support up to
B interrupt inputs, yielding 64 possible prioritized
i nterru pts.

The "specific" EOI is used when the fully nested structure
has not been preserved. The B2C59A may not be able to
determine the last level acknowledged. Thus, the software
must specify which interrupt level is to be reset. This is
done by issuing a "specific" EOI.

~

ADDRESS IUS (16)

\

tONTIIOLBUS

)

J
INTRfO

~

)

DATA BUS t')

--- -- - -- -- - cs

-

,.,

~

82C5SA

-

,

0

,

.,

'"CAS 0

.

c,,,

2

,

CAS 2

! ! t ! ! ! I, !

,

- --

I--

--

r--

INTA
SLAV£A

sPEii

G:O

- - - - - -

-

-

r-

I-

I--

-

I-- -

I

cs

~

0.,

IN,

.,

CAS 0

SLAVES

12C59A

,

iPEN

GTo

~

tNTA

0

,

CAS'
CAS 2

2

, •

!I!!!!!!

I

"

~

IN,

INTA

00'

CAS.
MASTER B2CSiA

CAS'

cm
sp,fij Ml

.0

., •• .,

r, ! t. t I
0,

•

I

.2

CASCADING THE 82C59A

5-171

M'

,t ! !

INTERRUPTREDUESTS

FIGURE 2.

.,

I

Application Note 109
1.6 Fully Nested Mode:
By default, the 82C59A operates in the Fully Nested Mode.
It will remain in this mode until it is programmed
otherwise. In the Fully Nested Mode, interrupts are
ordered by priority from highest to lowest. Initially, the
highest priority level is IRa with IR7 having the lowest.
This ordering can be changed through the use of priority
rotation (see 1.2).
In the Fully Nested Mode, when an interrupt occurs, its
corresponding bit will get set in the Interrupt Request
Register (IRR). When the processor acknowledges the
interrupt, the 82C59A will look to the IRR to determine the
highest priority interrupt requesting service. The bit in the
In-service Register (ISR) corresponding to this interrupt
will then be set. This bit remains set until an EOI is sent to
the 82C59A.
While an interrupt is being serviced, only higher priority
interrupts will.be allowed to interrupt the current interrupt
being serviced. However, lower priority interrupts can be
allowed to interrupt higher priority requests if the 82C59A:
is programmed for operation in the Special Mask Mode.
When using the 82C59A in an 80C86- or 80C88-based
system, interrupts will automatically be disabled when the
processor begins servicing an interrupt request. The
current address and the state of the flags in the processor
will be pushed onto the stack. The interrupt-enable flag is
then cleared. To allow interrupts to occur at this point, the
STI instruction can be used. Upon exiting the service
routine using the IRET instruction, execution of the
program is resumed at the point where the interrupt
occured, and the flags are restored to their original values,
thus re-enabling interrupts.
A configuration in which the Fully Nested structure is not
preserved occurs when one or more of the following
conditions occur:
(a) The Automatic EOI mode is being used.
(b) The Special Mask Mode is in use.
(c) A slave 82C59A has a master that is not programmed
to the Special Fully Nested Mode.
Cases (a) and (b) differ from case (c) in that the 82C59A
would allow lower priority interrupt requests the
opportunity to be serviced before higher priority interrupt
requests.
1.7 Master:
When using multiple 82C59As in a system, one 82C59A
has control over all other 82C59As. This is known as the
"master" interrupt controller. Communication between
the master and the other (slave) 82C59As occurs via the
CASO - 2 lines. These lines form a private bus between the
multiple 82C59As. Also, the INT lines from the slaves are
routed to the master's IR input pints). See Figure 2.
1.8 Slave:
A "slave" 82C59A in a system is controlled by a master
82C59A. There is but one "master" in the system, but there
can be up to 8 slave 82C59As. The INT outputs from the
slaves act as inputs to the master through it's IR inputs.

Communications between the master and slaves occurs
via the CASO - 2 lines. See Figure 2.
1.9 Special Fully Nested Mode:
The Special Fully Nested Mode (SFNM) is used in a
system having multiple 82C59As where it is necessary to
preserve the priority of interrupts within a slave 82C59A.
Only the master is programmed for the Special Fully
Nested Mode through ICW4. This mode is similar to the
Fully Nested Mode with the following exceptions:
(a) When an interrupt from a particular slave is being
serviced, additional higher priority interrupts from
that slave can cause an interrupt to the master.
Normally, a slave is masked out when its request is in
service.
(b) When exiting the Interrupt Service routine, the
software should first iJsue a non-specific EOI to the
slave. The In-service Register (ISR) should then be
read and checked to see if its contents are zero. If the
i register is empty, the software should then write a
I
non-specific EOI to the master. Otherwise, a second
EOI need not be written because there are interrupts
from that slave still being processed.
NOTE: Because the Master 82C59A and its slave 82C59As must be In Fully
Nested Mode for thIs mode to be functional, we CQuid not utlhzeAutomatlc
EOls. These would disturb the Fully Nested structure, as described
in section 1.6.

1.10 Special Mask Mode:
The Special Mask Mode is utilized in order to allow
interrupts from all other levels (higher and lower as well)
to interrupt the IR level that is currently being serviced.
Invoking this mode of operation will disturb the fully
nested priority structure.
Generally, the Special Mask Mode is selected during the
servicing of an interrupt. The software should first set the
bit corresponding to the IR level being serviced, in the
Interrupt Mask Register (OCW1). The Special Mask Mode
and interrupts should then be enabled. This will allow any
of the IR levels except for those masked off by OCW1 to
interrupt the IR level currently being serviced.
Because this disturbs the Fully Nested Structure, it is
required that a Specific EOI be issued when servicing
interrupts while the Special Mask Mode is in effect. Before
exiting the original interrupt routine, the Special Mask
Mode should be disabled.
1.11 Specific Rotation:
By issuing the' proper command word to OCW2, the
priority structure of the 82C59A can be dynamically
altered. The command word written to OCW2 would
specify which is to be the lowest priority IR level.
This specific rotation can be accomplished one of two
ways. The first is through a specific EO!. The software can
specify that rotation is to be applied to the IR level
provided with the EO!. The second method is a simple "set
priority" command, in which the lowest priority level is
specified with the command word.

5-172

Application Note 109
2.0 Initialization Control Words
The following section gives a description of the Initialization
Control Words (ICW) used for configuring the 82C59A Interrupt controller. There are four (4) control words used for
initialization of the 82C59A. These ICWs must be programmed in the proper sequence beginning with ICW1.lf at
any time during the course of operation the configuration of
the 82C59A needs to be changed, the user must again write
out the control words to the device in their proper order. The
initialization sequence is shown in Figure 3.

ICW4: Issuance of this ICW Is selectable through the IC4
(~O) bit of ICW4. If ICW4 is to be written to the
82C59A, AO from the CPU must be high (1) when
writing to it. This word needs to be written only when
the 82C59A is operating in modes other than the default modes. Instances when we would want to write
to ICW4 are one or more of the following: An
80C86(80C88) processor is being used, buffered
outputs (00-07) are to be used, Automatic EOls are
desired, or the SpeCial Fully Nested mode is to be
used.
2.1ICW1:
ICW1 is the first control word that is written to the 82C59A
during the initialization process. To access this word, the
value of AO must be a zero (0) in the addressing, and bit 04
of ICW1 must be a one (1). The format of the command
word is as follows:

I -ICW4 NEEDED
0= NO ICW4 NEEDED

CALL ADDRESS INTERVAL

1 = INTERVAL OF 4
0" INTERVAL OF B
1· LEVEL TRIGGERED MODE
0" EDGE TRIGGERED MODE
A7 - AS OF INTERRUPT
VECTOR ADDRESS

IMC$-S0I85 MODE ONLY)

FIGURE 3. 82C59A INITIALIZATION SEQUENCE

* NOTE: This is an address bit, and not part of the ICW.

ICW1: The 82C59A recognizes the first Initialization
Control Word (ICW) written to it based on two criteria: (1) the AO line from the address bus must be a
zero, and (2) the 04 bit must be a one. If the 04 bit is
set to a zero, we would be programming either
OCW2 or OCW3 (these are explained later). The
function of ICW1 is to tell the 82C59A how it is being
used in'the system (i.e. Single or cascaded, edge or
level triggered interrupts etc.).
ICW2: This control word is always issued directly after
ICW1. When addressing this ICW, the AO line from
the address bus must be a one (high). ICW2 is utilized in providing the CPU with information on where
to vector to in memory when servicing an interrupt.
ICW3: This control word is issued only If the SNGL (01) bit
of ICW1 has been programmed with a zero. When
addressing this word, the AO line from the CPU must
be high (1). This control word is for cascaded
82C59A's. It allows the master and slave 82C59As
to communicate via the CASO-2Iines. With the master, this word indicates which IR lines have slaves
connected to them. For the slave 82C59A(s), this
word indicates to which IR line on the master it is
connected.

FIGURE 4. ICWl FORMAT

~

en a:
COW
:;;X

<.>2:

a:

....
W

07 thru 05 - A7, A6, A5: These bits are used in the 8080/
85 mode to form a portion of the low byte call address. Whim using the 4 byte address interval, all 3
bits are utilized. When using the 8 byte interval, only
bits A7 and A6 are used. Bit A5 becomes a "don't
care" bit. If using an 80C86(80C88) system, the value
of these bits can be set to either a one or zero.
03 - LTIM:
0: The 82C59A will operate in an edge triggered mode.
An interrupt request on one of the IR lines (IRO - IR7)
is recognized by a low to high transition on the pin.
The IR signal must remain high at least until the falling
edge of the first slNTA pulse. Subsequent interrupts
on the IR pints) will not occur until another low-tohigh transition occurs.

5-173

1: Sets up the 82C59A to operate in the level triggered
mode. Interrupts occur when a "high" level is detected on one or more of the IR pins. The interrupt request must be removed from this pin before the EOI
command is issued by the CPU. Otherwise, the
82C59A will see the IR line still in a high state, and
consider this to be another interrupt requesl

Application Note 109
leW] (SLAVE DEVICE)

0,

A,

0,

0,

1 = ICW4 NEEDED
0" NO ICW4 NEEDED

SLAVE lOll)
1 =SINGLE

o

O· CASCADE MODE

o
o
o

CAll ADDRESS INTERVAL
1 = INTERVAL OF 4
o"INTERVAL OF 8

1
1
0
0

2

3

0

0

4
0
0
1

5
1
0
1

6
0
1
1

7
1
1
1

1" LEVEL TRIGGERED MODE
0= EDGE TRIGGERED MODE

A7 - A5 OF INTERRUPT

,CW'

VECTOR ADDRESS

fMCs-aDl85 MODE ONLY)
AO

0,

0,

0,

1 .. aOB&/8088MOD£
D-MC5-a0I85MDD£

• AI5 - AI OF INTERRUPT
VECTOR ADDRESS
iMCSBDI85MODE)
17 - T3 OF INTERRUPT
VECTOR ADDRESS
IIOB5IaOBBMODE)

l-AUTO EOI
0= NORMAL EOI

1 "SPECIAL FULLY NESTED
MODE
D '" NOT SPECIAL FULLY
NESTED MODE

1 =IA INPUT HASA SLAVE
o-IA INPUT DOES NOT HAVE
A SLAVE

NOTE:

Slave 10 is equal to the corresponding master IR input

82C59A INITIALIZATION COMMAND WORD FORMAT

.ew,

,ow,
I • I • I"""ISM-I '1 ' I 1 1 "1
p

I • I • I SL £0,1 .1 01 ,;f ,,1,.1

J

.t.l

~~'
D~'
1~1

'~.
.~.

'~'

'~.
• L...!....

11

-[

00

f--

,,

IA LEVEL TO IE
ACTEDUPOR

•• ,, •z ,, • ,• •• ,,
•• •• •, , ••, •, ,, ,,
•

,

READ REGISTER COr.wANO

•

NO ACTION

r

t-

,

SPECIAL MASK MODE

•

NO ACTION

• LO ~ Lz ARE USED

82C59A OPERATION COMMAND WORD FORMAT

5-174

,•

,
,

READ
READ
IRRES
ISREG
01 NEXT ON NEXT
ROPULSE RDPULSE

1 • POLL COMMARO
a· 10 POLL cOMMAND

••

1-

NON-IPEClfIC EOI CDMMAIID
END OF INTERRUPT
SPECIFIC EOI COIlMAID
ROTATE 01 NON-IPECIFrC EOI COMMUD
ROTATE 'I AUTOMATIC EDf MODE ISEn
AUTOMATIC ROTATIOI
ROTATE 'I AUTollATIC E01110DE (CLEAR)
• ROTATE 01 SPECifiC EDI COMMAND
}--SPEClfIC
ROTATloR
• SET PRIORITY COMMAND
10 OPERATION

~

0

I L

ocwz

,•

RESET
SPECIAL
MASK

,
I

SET
SPECIAL
MAS'

Application Note 109
02 - AOI: Call Address Interval (for 8080/8085 use
only). If using the 82C59A in an 80C86/88 based
system, the value of this bit can be either a 0 or a 1.

1: Tells the 82C59A that it is being used'alone in the
system. Therefore, there will be no need to issue
ICW3 to the device.

0: The address interval generated by the 82C59A is 8
bytes. This option provides compatiblity with the
RST interrupt vectoring in 8080/8085 systems
since the vector locations are 8 bytes apart. This
vector will be combined with the values specified
in bits 07 and 06 of ICW1. The addresses
generated are shown in Table 1.

DO - IC4: Specifies to the 82C59A whether or not it
can expect to receive ICW4. If this device is being
used in an 80C86/ 80C88 system, ICW4 must be
issued.
0: ICW4 will not be issued. Therefore, all of the
parameters associated with ICW4 will default to
the zero (0) state. This should only be done when
using the 82C59A in an 8080 or 8085 based
system.

TABLE 1. ADDRESS INTERVAL (8 BYTES)
07

06

05

04

03

02

01

00

A7

A6

1

1

1

0

0

0

IR7

A7

A6

1

1

0

0

0

0

IR6

A7

A6

1

0

1

0

0

0

IR5

A7

A6

1

0

0

0

0

0

IR4

A7

A6

0

1

1

0

0

0

IR3

A7

A6

0

1

0

0

0

0

IR2

A7

A6

0

0

1

0

0

0

IR1

A7

A6

0

0

0

0

0

0

IRO

1: ICW4 will be issued to the 82C59A.

2.2

ICW2 is the second control word that must be sent to the
82C59A. This byte is used in one of two ways by the
82C59A, depending on whether it is being used in an
8080/85 or an 80C86/88 based system.
When used in conjunction with the 8080/85 microprocessor, the value given to this register is taken as being
the high byte of the address in the CALL instruction sent
to the CPU.

1: The address interval generated by the interrupt
controller will be 4 bytes. This provides the user
with a compact jump table for 8080/8085 systems.
The interrupt number is effectively multiplied by
four and combined with bits 07, 06and 05toform
the lower byte of the call instruction generated
and sent to the 8080 or 8085. Table 2 shows how
these addresses are generated for the various
Interrupt request (IR) levels.
TABLE 2.
06

05

04

A7

A6

AS

1

A7

A6

AS

1

03

02

02

00

1

1

0

0

IR7

1

0

0

0

IR6

A7

A6

AS

1

0

1

0

0

IR5

A7

A6

AS

1

0

0

0

0

IR4

A7

A6

A5

0

1

1

0

0

IR3

A7

A6

A5

0

1

0

0

0

IR2

A7

A6

A.5

0

0

1

0

0

IR1

A7

A6

A5

0

0

0

0

0

IRO

07

06

05

04

03

02

01

00

A15

A14

A13

A12

A11

A10

A9

AS

FIGURE 5.

ICW2 FORMAT

In an. 80C86- or 80C88-based system, ICW2 is used to
send the processor an interrupt vector. This vector is
formed by taking the value of bits 07 through 03 and
combining them with the interrupt request level to get an
eight bit number. The processor will multiply this number
by four and go to that absolute location in memory to find
a starting address for the interrupt service routine
corresponding to the interrupt request.

ADDRESS INTERVAL (4 BYTES)

07

ICW2:

For example, if we set ICW2 to "00011000" and an
interrupt is recognized on IR1, the vector sent to the
80C86(80C88) will be 00011001 (19H). The processor will
then look to the memory location 64H to find the starting
address of the corresponding interrupt service routine. It
is .the responsibility of the software to provide this address
in the' interrupt table.

01 - SNGL:
0: This tells the 82C59A that more than one 82CS9A
is being used in the system, and it should expect to
receive ICW3 following ICW2. How the particular
82C59A is being used in the system will be
determined either through ICW4 for buffered
mode, or through the SP/EN pin for non-buffered
mode operation.

5-175

07

06

05

04

03

02

01

00

A7

A6

AS

A4

A3

x

x

x

FIGURE 6.

ICW2 FORMAT (SOCS6 MODE)

Application Note 109
2.3

ICW3:

These bits are coded as follows:

ICW3 is only issued when the SNGL bit in ICW1 has been
set to zero. If not set, the next word written to the 82C59A
will be interpreted as ICW4 if AO = 1 and IC4 from ICW4
was set to one, or it could see it as one of the Operation
Command Words based upon the state of the AO line.

TABLE 3.

SLAVE 'IDENTIFICATION' WITH ICW3

MASTER IR number
IR7
IRS
IR5
IR4
IR3
IR2
IR1
IRa

Like ICW2, this control word can be interpreted in two
ways by the 82C59A. However the interpretation of this
word depends on whether the 82C59A is being used as a
"master" or a "slave" in the system. The definition of the
particular devices role in the system is assigned through
ICW4 (which will be discussed later), or through the state
of the SP/EN pin (pin 1S).

102
1
1
1
1
a
a
a
a

101
1
1
a
a
1
1
a
a

100
1
a
1
a
1
a
1
a

82C59A as a MASTER:
If the given 82C59A is being used as a master, the eight (8)
bits in this command word are used to indicate which of
the IR lines are being driven by a slave 82C59A.

07
87

06

05

04

03

02

01

00

I I I I I I I I
86

85

FIGURE 7.

84

83

82

81

For example, if the INT output of a "slave" 82C59,A. is
connected to the input pin IR5 on the "master" 82C59A,
ICW3 of the "slave" would be programmed with the value
00000101 b, or 05H. This informs the "slave" as to which
priority level it holds with the "master".
D7 thru D3: These bits must be set to zeros (0) for proper
operation of the device.

80

ICW3 FORMAT (MASTER)

D7 thru DO:
0: The corresponding IR line to this bit is not being
driven by a slave 82C59A. This line can however
then be connected to the interrupt output of
another interrupting device such as a UART. If
there are unused bits in this byte because not all
eight of the IR lines are used, set them to zero.

2.4

ICW4:

This control register is written to only when the IC4 bit is
set in ICW1. The purpose 0/ this command word is to set
up the 82C59A to operate in a mode other than the de/au It
mode of operation. The de/au It mode 0/ operation is the
same as i/ a value 0/ OOH wereto be written to ICW4 (i.e. all
bits set to zero).

1 : The corresponding IR line to this bit is being
driven by a slave 82C59A.
x

~

The bits in this command word are directly related to the
IR lines. For example, to tell the 82C59A that there is a
slave device connected to IR5 (pin 23), bit D5 of the
command word should be set to a one (1).

1
1

0
1·

1

When the device is being used as a slave device,we must
use ICW3 to inform itself as to which IR line it will be
connected to in the master. Therefore, only the three (3)
least significant bits of ICW3 will be used to specify this
value.

07

06

05

04

03

02

01

00

I

1 = AUTO EOI
0= NORMAL EOI

I

- NON BUFFERED MODE
- BUFFERED MODE/SLAVE
- BUFFERED MODE/MASTER

'-------~_tl

82C59A as a SLAVE device:

1 "8D86/8088 MOCE
0= MCS-BO/85 MODE

I

1 = SPECIAL FULL Y NESTED

MODE
0" NOT SPECIAL FULLY
NESTED MODE

I

NOTE: Slave 10 is equal to the corresponding master IR input

FIGURE 9.

ICW4 FORMAT

D7 thru D5: These bits must be set to zero for proper
operation.
.
D4 - SFNM: This bit is used in the selection of the Special
Fully Nested Mode (SFNM) 0/ operation. This
mode should only be used when multiple 82C59As
are cascaded in a system. It needs only to be
programmed in the Master 82C59A in the system.
0: Special Fully Nested Mode is not selected.

FIGURE 8.

1: Special Fully Nested Mode is selected.

ICW3 FORMAT (SLAVE)

5-176

Application Note 109
03 - BUF: This bit tells the 82C59A whether or not the
outputs from the data pins (DO - 07) will be
buffered. If they are buffered, this bit will cause the
SP/E"N pin to become an output signal that can be
used to control the "enable" pin on a buffering
device(s).
0: The device will be used in a non-buffered mode.
Therefore, (1) the M/S bit in ICW4 is a don't care,
and (2) theSP/EN pin becomes an input pin telling
the device if it is being used as a master (pin 16 ~
High) or a slave (pin 16 ~ Low). For systems using a
single 82C59A, the SP/EN input should be tied
high.

There are three different OCWs for the 82C59A. Each has
a different purpose. The first control word (OCW1) is used
for masking out interrupt lines that are to be inactive or
ignored during operation. OCW2 is used to select from
various priority resolution algorithms in the device.
Finally, OCW3 is used for (1) controlling the Special Mask
Mode, and (2) telling the 82C59A which Register will be
read on the next Ro pulse; the ISR (In-service Register) or
the IRR (Interrupt Request Register).
3.1 DeW1:

1: The device is used in buffered mode. An enable
output signal will be generated on pin 16, and the
M/S bit will be used for determining whether the
particular 82C59A is a "master" or a "slave".

This control word is used to set or clear the masking of the
eight (8) interrupt lines input to the 82C59A. This control
word performs this function via the Interrupt Mask
Register (IMR). In it's initial state, the value of this register
is OOH. In other words, all of the interrupt lines are
enabled. Therefore, we need only write this control word
when we wish to disable specific interrupt lines.

02 - M/S: This bit is of significance only when the BUF bit
is set (BUF ~ 1). The purpose of this bit is to
determine whether the particular 82C59A is being
used as a "master" or a "slave" in the target
system.

A direct mapping occurs between the bits in this control
word and the actual interrupt pins on the device. For
example bit 7 (07) controls interrupt line IR7 (pin 25), bit6
controls IR6, and so on.

0: The 82C59A is being used as a slave.
1 : The 82C59A is the master interrupt controller in
the system.

J

01 - AEOI: This bit is used to tell the 82C59A to
automatically perform a non-specific End-of-Interrupt on the trailing edge of the last Interrupt
Acknowledge pulse. Users should note that when
this is selected, the nested priority interrupt structure is lost.
0: Automatic End-of-Interrupt will not be generated.
1 : Automatic End-of-Interrupt will be generated on
the trailing edge of the last Interrupt Acknowledge
pulse.
DO - tlPM: This bit tells the Interrupt Controller which
microprocessor is being used in the system. An
8080/8085, or an 80C86/80C88.

l

FIGURE 10.

Once the Initialization Command Words, described in the
previous section, have been written to the 82C59A, the
device is ready to accept interrupt requests. While the
82C59A is operating, we have the ability to select various
options that will put the device in different operating
modes, by writing Operation Command Words (OCWs) to
the 82C59A. These OCWs can be sent atanytimeafterthe
device has been initialized and in any order. These words
can be changed at any time as well. Note: If AO ~ a and 04
of the command word ~ 1, the 82C59A will begin the ICW
initialization sequence.

OeWl FORMAT

07 thru DO:
0: When any of the bits in the control word are reset
(0), the corresponding interrupt is enabled.
1: By setting a bit(s) to a one in the control word, the
corresponding interrupt line(s) is disabled.

1 : 82C59A to be used in the 80C86/88 mode of
operation.

Operation Command Words

J

Even though the user can mask off any of the IR lines, any
interrupt occuring during that time will not be lost. The
request for an interrupt is retained in the IRR; therefore
when that IR is unmasked by issuing a new mask value to
OCW1, the interrupt will be generated when it becomes
the highest requesting priority.

0: The 82C59A will be used in an 8080/8085 based
system.

3.0

INTERRUPT MASK
1 "'MASK SET
0" MASK RESET

For example, if the value 34H (00110100b) were written to
OCW1, interrupts would be disabled from being serviced
on lines IR2, IR4 and IR5.
3.2 DeW2:
In ICW4 bit 01 was used to specify whether the 82C59A
should wait for an EOI (End of Interrupt) from the CPU, or
generate its own EOI (Automatic EOI) . If bit 01 of ICW4
had been programmed to be a zero, OCW2 would be used
for sending the EOI to the 82C59A. Conversely, if this bit
had been set to a one, OCW2 would be used for specifying
whether or not the 82C59A should perform a priority
rotation on the interrupts when the AEOI is detected.

5-177

Application Note 109
OCW2 has several EOI options. The EOI issued can be
either specific or non-specific. For each of these EOls, the
user can specify whether or not priority rotation should be
performed.
07
R

D6

05

SL 1 EOI

04

I· I·
0

03

02

0 1 L2

01

L1

status can be checked by looking at the ISR or IRR
registers, or by issuing a Poll Command to manually
identify the highest priority interrupt requesting service.

07

DO

o

LO

06

05

D7:

R, SL, and EOI:
These three bits are used for specifying how the device
should handle AEOls, or for issuing one of several
different EOls. They are programmed as shown in the
following table:
ROTATE AND EOI MODES

R

SL

EOI

0

0

1

0

1

1

1

0

1

Rotate on non-specific EOI command

1

0

0

Rotate in Automatic EOI mode (set)

0

0

0

Rotate in Automatic EOI mode (clear)

1

1

1

Rotate on specific EOI command

1

1

0

, Set priority command

0

1

0

, No operation

02

01

DO

P

RR

IRIS I

Must be set to zero for proper operation of the
82C59A.

D6 - ESMM: Enable Special Mask Mode - The ESMM bit
when enabled allows the SMM bit to set or clear
the Special Mask Mode. When disabled, this bit
causes the SMM bit to have no effect on the
82C59A.
a: Disables the effect of the SMM bit.
1: Enable the SMM bit to control the Special Mask
Mode.

Non-specific EOI command
, Specific EOI command

D5 - SMM: Special Mask Mode - The SMM bit is used to
enable or disable the Special Mask Mode. This bit
will only affect the 82C59A when the ESMM bit is
set to 1.
a: Disable the Special Mask Mode.
1: Put the 82C59A into the Special Mask Mode.

'LO - L2 are used

L2, L 1, and La:
These three bits of. the control word are used in
conjunction with the issuance of specific EOls or when
specifically establishing a different priority structure. The
bits tell the 82C59A which interrupt level is to be acted
upon. Therefore, the software needs to know which
interrupt is being serviced by the 82C59A.
TABLE 5.

03

FIGURE 12.

FIGURE 11.

TABLE 4.

04

I ESMM I SMM I 0

D4, D3: These bits· are used to differentiate between
OCW2, OCW3 and ICW1. To properly select
OCW3, D4 must be set to zero and D3 must be set
to one.
D2 - P: Poll Command - This bit is used to issue the poll
command to the~.a2C59A. The next read of the
82C59A will cause a poll word to be returned
which tells if an interrupt is pending, and if so,
which is the highest requesting level.

INTERRUPT LEVEL TO ACT UPON

NOTE:

Th~

poll command must be issued each time the poll op-

eration is desired.

L2

L1

La

a

a

a

IR level a

a

a

1

IR level 1

a

1

a

IR level 2

a: No

a

1

1

IR level 3

1

a

a

IR level 4

1

a

1

IR level 5

1

1

a

IR level 6

1

1

1

IR level 7

poll

command

issued

to

the 82C59A.

1: Issue the poll command.
D1 - RR: Read Register - This bit is used to execute the
"read register" command. When this bit is set, the
82C59A will look at the RIS bit to determine
whether the ISR or IRR registeristobe read. When
issuing this command, the next instruction
executed by the CPU should be an input from this
same port to get the contents of the specified
register.
a: No "Read Register" .command will be performed.

3.30CW3:
There are two main functions that OCW3 controls: (1)
Interrupt Status, and (2) Interrupt Masking. Interrupt

5-178

1: The next input instruction by the CPU will read
either the contents of the .ISR or the IRR as
specified by the RIS bit.

Application Note 109
DO - RIS: This bit is used in conjunction with the RR bit to
select which register is to be read when the "Read
Register" command is issued.
0: The next input instruction will read the contents of
the Interrupt Request Register (IRR).
1: The next input instruction will read the contents of
the In-Service Register (ISR).
The two registers that can be accessed through the Read
Register command are used to determine which
interrupts are requesting service, and which one(s) are
currently being serviced.
The IRR bits get set when corresponding Interrupt
requests are received. For instance, when IR4 is detected,
bit D4 of the IRR will get set. When an interrupt
acknowledge comes back from the CPU, the priority
resolution logic will determine which interrupt request
will be serviced. The corresponding bit in the In-service
Register (ISR) will then be set. Clearing of the correct bits
in the ISR occurs through out use of the AEOI, or by
issuing an EOI to the device.

4.0 Addressing the 82C59A
There are two factors that must be taken into account
when addressing the 82C59A in a system. To begin with,
the 82C59A is accessed only when the CS pin (chip
select) sees an active signal (low). This signal is
generated using control circuitry in the system. Secondly,
the various registers within the 82C59A are selected

based upon the state of the AD (address pin) as well as
specific bits in the command words (i.e for ICW1, OCW2,
and OCW3 AD must be a zero).
The circuit in Figure 13 shows that the CS signal is
generated using an HPL-82C338 Programmable Chip
Select Decoder (PCSD). This device is being used as a
3-to-8 decoder. Note that the G1 input is active high and
G2 thru G5 have been programmed to be active low. The
A, B, and C inputs to the B2C33B correspond to address
lines AD2, AD3 and AD4 respectively, from the BOC88.
The AD input to the 82C59A is also taken from the CPUs
address bus; ADO is used. It should be noted that address
line AD1 from the BOCBB is not being used in the
addressing of this particular peripheral. This is done to
allow other peripheral devices that require two address
inputs for internal register selection, to use address lines
ADO and AD1 from the processor.
Because the AD1 address line from the BOCBB is not being
used, the B2C59A will be addressed regardless of whether
AD1 is high or low (1 or 0). The remainder of the address
lines from the BOC8B can either be a zero or one when
addressing the B2C59A. For the examples to be
presented, it can be assumed that all unused address lines
will be set to zero when addressing the B2C59A.
In Figure 13, output V6 from the HPL-B2C33B is being
used as the CS input to the B2C59A. This line is enabled
when the inputs on A, B, and C are: A = 0, B = 1, and C = 1.
Combining this with the AD input to the B2C59A, we get
the addresses 1BH and 19H for accessing the B2C59A.

!3

80C88 DATA BUS

.,,02
0'"

:;;=

u!!:

...a:
Do

82C59A
00-07
INTA

INTA

iiD

iffi
WR
INTR

WR
INT

82C338

ALE
101M

CS

V&

AD

GND

ADO
80C88 ADDRESS BUS

FIGURE 13. ADDRESSING THE 82C59A

5-179

IR7
IR6
IR5
IR4
IR3
IR2
IRI
IRO

VCC
2Kll

SPIEN

Application Note 109
5.0

Programming the 82C59A

As described earlier, there are two different types of
command words that are used for controlling 82C59A
operation; the Initialization Command Words (ICWs) and
the Operation Command Words (OCWs). To properly
program the 82C59A, it is essential that the ICWs be
written first. When writing the ICWs to the 82C59A, they
must be written in the following sequence:
(1) Write ICWI to the 82C59A, AO

=

O.

EOls, reading of the ISR andsor IRR, etc. These OCWs
can be written to the 82C59A at any time during operation
of the 82C59A. The various command words are identified
by the state of selected bits in the words, rather than by
the sequence that they are written to the 82C59A; as with
the ICWs. Therefore, it is imperative that the fixed bit
values in the command words be written as such to insure
proper operation of the device(s).

(2) Write ICW2 to the 82C59A, AO = 1.

5.1 Example 1: Single B2C59A

(3) If using cascaded 82C59As in system, write ICW3 to
the 82C59A, AO = 1.

In Example 1, we are using a single 82C59A in a system to
handle the interrupts caused by an HO-6406 Programmable Asynchronous Communications Interface. The
system is driven using an 80C86 Microprocessor. The system configuration is shown in Figure 14. An assembly language listing for the software controlling this system can
be found in Program Listing, Example 1, on page 15.

(4) If IC4 bit was set in ICW1, write ICW4 to the 82C59A.
NOTE: When using multiple 82C59As in the system (cascaded). each
one must be initialized following the above sequence.

Once the 82C59A(s) has been configured through the
ICWs, the OCWs can be used to select from the various
operation mode options. These include: masking of
interrupt lines, selection of priority rotation, issuance of

Interrupts are initiated by the HO-6406 anytime it receives
data on its Serial Oata In pin (SOl), or when it is ready to
transmit more data via its Serial Oata Out pin (500).

00-07
ADO
ADZ
AD3
AD4

AD
A
B
C

IRZ

Y6

CS

Vi

HPL-82C338

Cs
AD
AI

ADO
ADI

INTR
00-07

HD-6406
80C88 ADDRESS BUS

80C88 DATA BUS

FIGURE 14.

EXAMPLE 1: SINGLE 82C59A

5-180

Application Note 109
5.2 Example 2: Cascaded 82C59As
by the HD-6406 PACI. Except for the fact that this system
is configured with a Master-Slave interrupt scheme, it is
the same as ,that in Example 1. The software for this system is given in Progra,rn Listing, Example 2, on Page 20.

Example 2 illustrates how we can use multiple 82C59As in
Cascade Mode. Figure 15 shows the interconnections
between the master and slave interrupt controllers. In this
example, only one interrupt can occur. This is generated

INTA--------~~--------------,

MASTER

AD
AI

ADO
IR214o---------1INTR
INT

CAS

SP/Eii~

L.C'TS-"'-'''''T'I:_..J_ _ _ _ _ _ _0,;s I 2

CS

12K!l
HD·6406

GND

Vii

Y5~----------------+-----------~
GND

YDt-------------------'

L-..._...I

82C338 PCSD

FIGURE 15.

EXAMPLE 2: CASCADED 82C59As

5-181

ADO

ADI

Application Note 109
6_0 Expansion Past 64 Interrupts
example). Because of this. no interrupts will break
In some instances. it may be desirable to expand the
number of available interrupts in a system past the
execution of the system software. Therefore. it is the task
of the software to poll the various 82C59As in the system
maximum of 64 imposed when using cascaded 82C59As.
The easiest way to accomplish this is through the use
to see if any interrupts are pending. Once it has been
of the Poll command with the 82C59A. Figure 16
established which interrupt requires servicing. the
software can take appropriate action.
illustrates one example of how this expansion can be
accomplished. Notice that we are using two 3-to-8
decoders (HPL-82C338 PCSDs) to address up to 16
There are disadvantages to using the poll mode for the
82C59As. Selection of which decoder is active takes place
systems interrupt structure: (1) the overhead of polling
using the G2 pin on the HPL-82C338. For one
each of the 82C59As reduces the systems efficiency. and
HPL-82C338. G2 has been programmed to be active low .(2) real-time interrupt servicing cannot be guaranteed.
(G2). while the other HPL-82C338 has been programmed for G2 to operate active high. This G2 input is
.' There are several advantages to using the poll mode in
driven by AD5 from the CPU's address bus.
this manner: (1) there can be more than 64 priority
interrupts in the system. and (2) memory in the system is
With this type of interrupt structure. we are not using the
INT and INTA lines from our processor (80C88 for this
freed because no interrupt vector table is required.

82C59A
AD

CS

82C338

101M
AD2-AD4
AD5

iii

82C59A

YO

AD

CS·

A.B.C

3

G2

G3-GS

IRO-IR1

8

IRO-IR1

V7

··

82C59A

S

IRO-IR1

82C59A
AD

, - - - - t - -..I ES .

j.--+'S:---IRO-IR1

u ., ,. .,"
S2C59A

~

iii/M---"'I

";' GND

ADO

··

FIGURE 16. EXPANDING PAST 64 INTERRUPTS

5-182

Application Note 109
PROGRAM LISTING, EXAMPLE 1

NAME

EXAl~PLE

1

**********~***~***~~*~*************~**************~*************************

HARRIS SEMICONDUCTOR
P.O. Box 883
Melbourne, FL 32901
!~icroprocessor

JAGoss

AUG 5,

19~5

Appl ications

EXAMPLE #1:

System with a single 82C59A

*******~**********************~*********************************************

The fo11owing are port addresses for tne devices used in our example
system. The devices that we ~ill look at are the HD-6406 PACI, and the
two 82C59A Interrupt Controller.
6406 Register Addresses
UCR
BRSR
MCR
USR
MSR
TaR

RBR

EQU
EQU
EQU
EQU
EQU
EQU
EQU

llH
13H
12H
11 H
13H
IOH
IOH

;UART control register;Baud Rate Select Register
;Modem Control Register
;UART Status Register
;Modem Status Register
;Transmit Buffer Register
;Receive Buffer Register

--------- 82C59A Addresses
lCWI
lCW2
lCW4
OCWI
OCW2

EQU
EQU
EQU
EQU
EQU

18H
19H
19H
19H
18H

CARRIAGE RETURN
LINE FEED
OR
TBRE

EQU
EQU
EQU
EQU

ODH
OAH
BOH
40H

ASSUME

CS:DRlVER 59A,
OS: BUFFER-AREA,
SS:STACK AREA

&
&

;i"ask for checki ng DATA READY
;Mask for checking TRANSMIT BUfFER
REGISTER EMPTY

5-183

Application Note 109
PROGRAM LISTING, EXAMPLE 1

DRIVER 59A

SEGMENT

PUBLIC

,. ****~**********************************************************
;*
MAIN
*
,. ***************************************************************

MAIN

PROC

SET UP:

MOV
MOV
MOV
MOV
MOV

NEAR
AX,BUFFER AREA ;Set up the data segment
DS,AX
' AX,STACK_AREA ;Set up the stack segment
SS,AX
;Set up the stack pointer
SP,OFFSET STACK_AREA:TOP_OF_STACK

Set up the interrupt vector table
MOV
MOV
MOV

AX,OFFSET INT SERVICE ROUTINE
ISR 34,AX
ISR=34[2J,CS

Initialize the pointer into the data buffer.
,.,OV
XOR

BX,OFFSET BUFFER
DI,DI
;Clear the index register

Initialize the 82C59A
CALL

INIT 82C59A

Initialize the HD-6406 PACI
CALL

INlT 6406

Wait for interrupts from the '59A •••
;Set the interrupt enable flag.

STl

I'IAIT LOOP:

NOP
JMP

MAIN

HLT
ENDP

WAIT LOOP

5-184

Application Note 109
PROGRAM LISTING, EXAMPLE 1

PROC
NEAR
82C5~A
***************************************************************
INIT 82C59A
,. *
*
***************************************************************
HIlT

We first want to write ICW1. This will oe used to set the
device for edge triggered interrupt detection and for use
in Single f40de.
BEGIN 59A:

MOV
OUT

AL,00010000B
ICW1,AL

;Edge triggered, and single mode

Now we will write out ICW2. This gives the 59A information
about where to branch to in the interrupt table.
MOV
OUT

AL,00100000B
ICW2,AL

The final control word that is written in this sequence is ICW4.
This is used to specify that the device is to operate in 80C86/S0C88
mode, with normal EOI's generated through software, and non-buffered
outputs are being fed back to the CPU.
r>10V
OUT

AL , 00000001 B
ICW4,AL

To insure that interrupts will only be issued by the HD-6406 PACI,
we will write out an interrupt mask to the register OCW1. This
mask will only allow interrupts from the specified lines. In this
case on IR2 only, all others will be disabled.

!l

",;2
0'"

:;::C
u!!::

a:

MOV
OUT
INIT S2C59A

AL, 11111 011 B
OCW1,AL

;A zero in a bit means that the
corresponding IR lines is enabled.

RET

ENOP

IN IT 6406
PROC
NEAR
***************************************************************
*
INIT 6406
*
***************************************************************
This routine sets up the HD-6406 to communicate with a dumb
terminal. The device will generate an interrupt whenever
a key is pressed at the terminal.

5-185

~

Application Note 109
PROGRAM LISTING, EXAMPLE 1

Set up for 8 data bits. 1 stop bit. and no parity.
BEGIN 6406:

MOV
OUT

AL •0011111 OB
UCR.AL

Set up BRSR for 9600 bps. assuming that the target system uses
a 2.4576 MHz clock crystal.
MOV
OUT

AL.OOOOOllOB
BRSR.AL· ,

Enable interrupts on the 6406. enable the receiver, and
select normal mode.
MOV
OUT
INIT 6406

AL,OOl 001 OOB
MCR,AL
;Return to the MAIN

RET
ENDP

INT SERVICE ROUTINE

PROC

!'lEAR

*~*******~*****************************************************

; *
IfH SERVICE ROUTINE
*
; *************************~*******~*****************************
ISR START:

IN
TEST'
IN'Z
TEST
JNZ

AL,USR
AL,DR .
READ DATA
AL,TlfRE
PRINT BUFFER

;Find out what caused the interrupt.
;Was it DATA READY ?
;Was it TRANSMIT BUFFER REG. EMPTY ?
;If so, then'print next character

If this condition was not detected, then we have an erroneous
interrupt from the ,HD-6406. Rather than servicing this, we will
simply return from the service routine to the MAIN.
ERROR:

JMP

ISR EXIT

; Read the data that is present in the Receive Buffer Register.
READ DATA:

IN
MOV
INC
CMP
JE

AL,RBR
,[BXJ(DI],AL

JMP

ISR EXIT

;Save the data in our buffer area.
;Increment the index into the buffer.
AL,CARRIAGE RETURN
PRINT LF 01

;Exit the service routine.

Set up for writing the data out to the Transmit Buffer •••
PRINT LF:

MOV
140V

AL,LlNE FEED
LBX] [DIJ.AL

;Add a line feed to the buffer.

5-186

Application Note 109
PROGRAM LISTING, EXAMPLE 1

INC
OUT
MOV
XOR

DI
TBR,AL
CX,DI
DI,DI

JMP

ISR EXIT

;Load tne buffer size into CX
;Set the index back to beginning
of the buffer.

Print out the contents of the buffer •••
PRINT BUFFER:
PRINT CHAR:

DONE PRI NTlNG:

CMP
JNE
JMP
MOV
OUT
INC
LOOP

CX,O
PRINT CHAR
ISR EX"IT
AL,LBX][DI]
TBR,AL
DI
PRINT CHAR

; Any thing to print?
;If so, then print it .••
;Else, ignore this interrupt •••
;Print the byte pointed to in buffer.

XOR

DI,DI

;Re-initialize pointer into buffer.

;Point to next character.
;Print til end-of-buffer.

Exit from the service routine, sending out a non-specific EOI first.
ISR EXIT:

MOV
OUT
OUT
IRET

INT SERVICE ROUTINE
DRIVER 59A -

BUFFER AREA

AL,OOlOOOOOB
OCW2 S,AL
OCW2:M,AL

;Send out an End-of-Interrupt
to both master and slave.

ENDP
ENDS

SEGMENT

PUBLIC

****~**********************************************************

BUFFER AREA
*
***************************************************************

*

ISR 34

ORG
DW

88H
4 DUP(?)

BUFFER
BUFfER AREA

ORG
DB
ENDS

lOOH
80 DUP(?)

STACK AREA
SEGMENT
PUBLIC
***************************************************************
;*
STACK AREA
*
,. ***************************************************************
STACK
TOP OF STACK
STAC"K AREA

DW
LABEL
ENDS
END

BOH DUP(?)
WORD

5-187

Application Note 109
PROGRAM LISTING, EXAMPLE 2

NAME

EXAl~PLE

2

*************.***************************************************************
AUG 27, 1985

HARR!S SEMICONDUCTOR
P.O. Box 883
Melbourne, FL 32901

Microprocessor Applications
JAGoss
EXAMPLE #2:
Configure the system for two 82C59As (MASTER/SLAVE).
generated for the slave by an HD-6406 PACI.

Interrupts are

****************************************************************************
The following are port addresses for the devices used in our example
system. The devices that we will look at are theHD-6406 PACI, and the
two 82C59A Interrupt Controllers.
6406 Register Addresses
UCR
BRSR
MCR
USR
MSR
TBR
RBR
;

EQU
EQU
EQU
EQU
EQU
EQU
EQU

;UA~T control register
;Baud Rate Select Register
;Modem 'Contro1 Register
;UART Status Register
;t~odem Status Regi ster.. .
;Transmit Buffer Register
;Receive Buffer Register

IlH
13H
12H
IlH
13H
10H
10H

--------- 82C59A Addresses ----------

ICW1 M
ICW2-M
ICW3"""'"M
ICW4-M
OCW1-M
OCW2-M

EQU
EQU
EQU
EQU
EQU
EQU

18H
19H
19H
19H
19H
18H

;MASTER Interrupt Controller

ICW1 S
ICW2-S
ICW3-S
ICW4-S
OCW1-S
OCW2-S

EQU
EQU
EQU
EQU
EQU
EQU

OH
1H
IH
lH
1H
OH

;SLAVE Interrupt Controller

CARRIAGE RETURN
LINE FEED
DR
TBRE

EQU
EQU
EQU
EQU

ODH
OAH
80H
40H

ASSUME

CS:DRIVER 59A,
DS : B~FF ER-AREA,
SS:STACK KREA

&
&

;Mask for checking DATA READY
;Mask for checking TRANSMIT BUFFER
; REGISTER EMPTY

5-188

Application Note 109
PROGRAM LISTING, EXAMPLE 2

SEGMENT
PUBLIC
DRIVER 5~A
***************************************************************
;*
MAIN
*
,. ***************************************************************
MAIl'J

PROC

l'JEAR

SET UP;

MOV
MOV
r10V
1v10V

AX, BUFFER_AREA ;Set up the data segment
DS,AX
AX, STACK_AREA ;Set up the stack segment
SS,AX
;Set up the stack pointer
SP,OFFSET STACK_AREA:TOP_OF_STACK

MOV

Set up the interrupt vector table
MOV
MOV
MOV

AX,OFFSET INT SERVICE ROUTIl'JE
ISR 34,AX
ISR=34[2],CS

Initialize the pointer into the data buffer.
(v10V
XOR

BX,OFFSET BUFFER
01,01

;Clear the index register

Initialize tile 82C59A
CALL

INIT 82C59A
!1

Initialize the HD-6406 PACI
CALL

",;2
c:>'"
::;::C

INIT 6406

..,!!:
a::

D..
'"

Wait for interrupts from the '59A •.•
;Set the interrupt enable flag.

STi

WAIT LOOP:

NOP
JMP

MAIN

HLT
ENDP

WAIT LOOP

5-189

Application Note 109
PROGRAM LISTING, EXAMPLE 2

INIT 82C59A
PROC
NEAR
***************************************************************
*
INIT 132C59A
*
***************************************************************
-------------------- Configure the MASTER -------------------We fi rst want to write ICWl. This wi 11 be used to set the
device for edge triggered interrupt detection and for use
in Cascade Mode.
BEGIN 59A:

MOV
OUT

AL,OOOlOOO1 B
ICW1.:.-M,AL

;Edge triggered, and cascade mode

Now we will write out ICW2. This gives the 59A information
about where to branch to in the interrupt table. In this example
however, this value is not used. Interrupts will only be generated
by the slave 82C59A.
MOV
OUT
"

AL,OOOOOOOOS
ICW2_M,AL

Write out ICW3 to the MASTER. This tells the master which IR lines
have slaves connected to them. I~ this case, interrupts come from
the slave only on IR5. All other lines are not used.
MOV
OUT

AL, 001 OOOOOS
ICW3_M,AL

;SLAVE is only on IR5.

The final control word that is written in this sequence is ICW4.
This is used to specify that the device is to operate in 80C86/88
mode, with normal EOI's generated through software, and non-buffered
outputs are being fed back to the CPU.
MOV
OUT

AL,OOOOOOOlB
ICW4_M,AL

-------------------- Configure the SLAVE -------------------First, set up the slave for edge triggered interrupts, cascade mode
, and tell it that ICW4 is to be issued.
MOV
OUT

AL,OOOl 0001 B
ICW1_S,AL

Write ICW2 to the slave. When an interrupt occurs, the 82C59A will take
this value, add to it the interrupt number (IR2 = 20H + 2 = 22H) and
sends it to the processor. The processor will then multiply this number
by four (4) to generate the address in the Interrupt table to look for
the address of the Interrupt Service Routine.
MOV
OUT

AL,20H
ICW2_S,AL

;IR2 from the slave will cause the
; CPU to vector 88H.

5-190

Application Note 109
PROGRAM LISTING, EXAMPLE 2 .

fell the slave which IR line on tile master it is connected to.
i~OV

OUT

AL,OOOOOlOlB
ICW3_S,AL

;It drives IR5 •••

Set up the slave for normal EOI's, and 80C86/88 mode.
MOV
OUT

AL,OOOOOOOIB
ICW4_S,AL

Set up the mask register for both the master and the slave ••.

INIT 82C59A

MOV
OUT

AL, 11 011111 B
OCW1_M,AL

;Interrupts recognized only on IR5

MOV
OUT

AL, 11111 011 B
OCW1_S,AL

;Interrupt recognized only on IR2

RET
ENDP

INIT 6406
PROC
NEAR
**w************************************************************
*
INIT 6406
*
***************************************************************
This routine sets up the HD-6406 to communicate with a dumo
terminal. The device will generate an interrupt· whenever
a key is pressed at the terminal.
Set up for 8 data bits, 1 stop bit, and no parity.
BEGIN 6406:

MOV
OUT

AL,OOI11111 B
UCR,AL

Set up BRSR for 9600 bps, assuming that the target· system uses
a 2.4576 MHz clock crystal.
MOV
OUT

AL,OOOOOllOB
BRSR,AL

Enable interrupts on the 6406, enable the receiver, and
select normal mode.
MOV
OUT
INIT 6406

RET

ENDP

AL,OOI 001 OOB
MCR,AL
;Return to the MAIN

5-191

Application Note 109
PROGRAM LISTING, EXAMPLE 2

DONE PRINTING:

XOR

;Re-initialize pointer into buffer.

01,01

Exit from the service routine, sending out a non-specific EOI first.
ISR EXIT:

MOV
OllT
OllT

AL,OOlOOOOOB
OCW2 S,AL
OCW2:M,AL

;Send out an End-of-Interrupt
to both master and slave.

I RET

INT SERVICE ROUTINE
DRIVER 59A BUFFER AREA

ENDP
ENDS

SEGMENT

PUBLIC

****7<*************************,*********************************

*

BUFFER AREA

*

********************************7<******************************

BUFFER

ORG
OW
ORG
DB

BUFFER AREA

ENDS

STACK' AREA

SEGMENT

ISR 34

.

88H

4 DUP(?)

100H
80 DUP(?)

PUBLIC

***~***********************************************************

;*

STACK AREA

*

,. *******************************"'1(*******************************

STACK
TOP OF STACK
STACK AREA

OW
LABEL
ENDS
END

SOH DUP( '/)
WORD

5-192

DATA COMMUNICATIONS FAMILY

PAGE

HD-4702/883

Programmable Bit Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-3

HD-6402/883

Universal Asynchronous Receiver Transmitter .... . .. .. . .... . ... ... . .

6-14

HD-6409/883

Manchester Encoder-Decoder .......•............................

6-27

HD-15530/883

Manchester Encoder-Decoder ....................................

6-43

HD-15531/883

Manchester Encoder-Decoder ....................................

6-56

6-1

Ell HARRIS

HD-4702/883
CMOS Programmable Bit Rate Generator

June 1989

Pinout

Features

HDl-4702/883 (CERAMIC DIP)
TOP VIEW

• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• HD-4702/883 Provides 13 Commonly Used Bit Rates
• Uses a 2.4576MHz Crystal/Input for Standard
Frequency Output (16 Times Bit Rate)
• Low Power Dissipation
• Conforms to EIA RS-404
• One HD-4702/883 Controls up to Eight Transmission
Channels
• Initialization Circuit Facilitates Diagnostic Fault
Isolation
• On-Chip Input Pull-Up Circuit

00

VCC
1M
50
51

CP

52

Ox

53

IX

Z

GND

CO

Description
The HD-4702/883 Bit Rate Generator provides the
necessary clock signals for digital data transmission
systems. such as a UART. It generates 13 commonly used
bit rates using an on-chip crystal oscillator or an external
input. For conventional operation generating 16 output
clock pulses per bit period. the input clock frequency must
be 2.4576MHz (i.e. 9600 Baud x 16 x16. since there is an
internal + 16 prescaler). A lower input frequency will result
in a proportionally lower output frequency.
The HD-4702/883 can provide multi-channel operation
with a minimum of external logic by having the clock
frequency CO and the + 8 prescaler outputs QO. Ql. Q2
available externally. All signals have a 50% duty cycle
except 1800 Baud. which has less than 0.39% distortion.
The four rate select inputs (SO-53) select which bit rate is at
the output (Z). See Truth Table for Rate Select Inputs for

select code and output bit rate. Two of the 16 select codes
for the HD-4702/883 do not select an internally generated
frequency. but select an input into which the user can feed
either a different frequency. or a static level (High or Low) to
generate "ZERO BAUD".
The bit rates most commonly used in modern data terminals
(110. 150.300. 1200. 2400 Baud) require that no more than
one input be grounded for the HD-4702/883. which is
easily achieved with a single 5-position switch.
The HD-4702/883 has an initialization circuit which
generates a master reset for the scan counter. This signal is
derived from a digital differentiator that senses the first high
level on the CP input after the ECp input goes low. When
ECp is high. selecting the crystal input. CP must be low. A
high level on CP would apply a continuous reset. See Clock
Modes and Initialization below.

Truth Tables
TRUTH TABLE FOR RATE SELECT INPUTS
(Using 2.4576MHz Crystal)

S3

S2

Sl

So

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

NOTE.

OUTPUT
RATE(Z)
MUX Input (1M)
MUX Input (1M)
50 Baud
75 Baud
134.5 Baud
200 Baud
600 Baud
2400 Baud
96oo Baud
4800 Baud
1800 Baud
1200 Baud
2400 Baud
300 Baud
150 Baud
110 Baud

CLOCK MODES AND INITIALIZATION
IX

ECp

CP

OPERATION

..I1..I1..

H
L
H
L

L

Clocked from Ix
Clocked from CP
Continuous Reset
Reset During 1st CP = High Time

X
X
X
NOTE:

J1JL
H

I"L

Actual output frequency i. 16 time. the indicated Output Rate,
assuming a clock frequency of 2.4576MHz.

H = HIGH Level
L= LOW Level
X = Don't Care

...rtr1..
.I'"1-

19200 Baud by connecting 02 to 1M

Copyrighl © Harri. Corporation 1989

6-3

= 1st HIGH Level Clock
Pulse after ECp goes LOW
= Clock Pulse

HD-4702/883

Pin Description
PIN
NUMBER

TYPE

SYMBOL

DESCRIPTION

16

VCC

VCC: Is the +5V power supply pin.AO.1 ~Fcapacitor between pins 16 and 8 is
recommended for decoupling

8

GND

GROUND

5

I

CP

4

I

ECp

EXTERNAL CLOCK INPUT
EXTERNAL CLOCK ENABLE: A low signal on this input allows the baud rate to be
generated from the CP input
CRYSTALINPUT

7

I

IX

6

0

Ox

CRYSTAL DRIVE OUTPUT

15

I

1M

MULTIPLEXED INPUT

11,12,13,14

I

SO-53

9

0

CO

1,2,3

0

00- 0 2

10

0

Z

BAUD RATE SELECT INPUTS
CLOCK OUTPUT
SCAN COUNTER OUTPUTS
BIT RATE OUTPUT

Block Diagram

HD-4702/883

r---------,

I

0)
@

I
I
I

OSCILLATOR
CIRCUIT

IX

ox-'------'

I
I

J

0. ECP - - , - - - - - - - - ; - .
® cP-t--j-------(

1800
'200

tttt======t~

13

'-r===::::;-t-114

L----iCP+22

a
MR

15

2400
300
150

'10

:

I
I

----------------~-------~

Vee = PIN 16
VSS = PIN 8
o = PIN NUMBER
* See Figure 4 In Design Information for Crystal SpeCifications.

6-4

Specifications HD-4702/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ..•......••.••....•.•••••...••••.••.•••• +8.0V
Input, Output or
1/0 Voltage Applied ••.........•••.. GND - O.SV to VCC + O.SV
Storage Temperature Range ..•..•..•.•..•.•• -6S oC to +1S0 0 C
JunctionTemperature ................................ +17S 0 C
Lead Temperature (Soldering, 10 Seconds) ...••.•....•• +3000 C
ESD Classification .................................... Class 1
Typical Derating Factor .•••.•.••••• 1mNMHz Increase in ICCOP

Thermal Resistance, Junction-to-Case (Ojel
Ceramic DIP Package ........................... +17.1 0 CIW
Thermal Resistance, Junction-to-Ambient (Oja)
Ceramic DIP Package ........................... +7S.7 0 CIW
Maximum Package Power Dissipation @ +12So C
Ceramic DIP Package .............................. 660mW
Gate Count ............................................. 720

CAUTION:

Stresses above those listed in the ''Absolute Maximum Ratings" may cause permanent damage 10 the device. This is

a stress only rating and

operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.

Operating Conditions
Operating Voltage Range ....................... +4.SV to +S.SV
Operating Temperature Range ••••...•••••..• -SSoC to +12So C
TABLE 1.

D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Guaranteed and 100% Tested

D.C. PARAMETERS SYMBOL

CONDITIONS

GROUPA
SUBGROUPS

TEMPERATURE

LIMITS
MIN
MAX

UNITS

Input High Vollage

VIH

Vee=4.SV

1,2.3

-ssoe . F1
FO/2. F2
R1 = 10kO. 1/4 W. ±10'll>
Vee = 5.5V ± O.5V. GND = OV
C1 = O.01pF minimum

= F1/2.···

6-,9

HD-4702/883
Metallization Topology
DIE DIMENSIONS:
100 x 97 x 19 mils
METALLIZATION:
Type: SI - AI
Thickness: 10k)!. - 12kA
GLASSIVATION:
Type: Si02
Thickness: 7kA - 9kA
DIE ATTACH:
Material: Gold/Silicon Eutectic Alloy
Temperature: Ceramic DIP·- 4600 C (Max)

WORST CASE CURRENT DENSITY:
7.1 x 104A/cm2

Metallization Mask Layout
HD-4702l883

Ox

IX

GND

CO

6-10

HD-4702/883
Packaging t
16 PIN CERAMIC DIP

--r
I

.265
.285

r-I

o·
15'

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
Method: Furnace Seal

NOTE:

All Dimensions are

~~x

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-2

t Mil-M-38510 Compliant MateriaJs, Finishes, and Dimensions.

• Dimensions are in inches.

6-11

HD-4702

mHARRIS
DESIGN INFORMATION

CMOS Programmable Bit Rate Generator
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Application Information
Single Channel Bit Rate Generator
Figure 1 shows the simplest application of the
HD-4702. This circuit generates one of five possible bit
rates as determined by the setting of a single pole,
5-position switch. The Bit Rate Output (Z) drives one
standard TTL load or four low power Schottky loads over
the full temperature range. The possible output frequencies
correspond to 110, 150, 300, 1200, and 2400 Baud. For
many low cost terminals, these five bit rates are adequate.

t

56pF

Simultaneous Generation of Several Bit Rates
Figure 2 shows a simple scheme that generates eight bit
rates on eight output lines, using one HD-4702 and one
93L34 Bit Addressable Latch. This and the following
applications take advantage of the built-in scan counter
(prescaler) outputs. As shown In the block diagram, these
outputs (00 to 02) go through a complete sequence of
eight states for every half-period of the highest output
frequency (9600 Baud). Feeding these Scan Counter
Outputs back to the Select Inputs of the multiplexer causes
the HD-4702 to interrogate sequentially eight different
frequency signals. The 93L34 8-bit addressable Latch,
addressed by the same Scan Counter Outputs, re-converts
the multiplexed single Output (Z) of the HD-4702 into eight
parallel output frequency signals. In the simple scheme of
Figure 2, input 53 is left open (HIGH) and the following bit
rates are generated:
00: 110Baud

01: 9600 Baud

02: 4800 Baud

03: 1800 Baud

04: 1200 Baud

05: 2400 Baud

06: 300 Baud

07: 150Baud

HD- 4702

6PF JO
2.4576 MHz
CRYSTAl

* See Figure 4

SWITCH POSITION

HD-4702 BIT RATE

1
2
3
4
5

110 Baud
150 Baud
300 Baud
1200 Baud
2400 Baud

FIGURE 1. SWITCH SELECTABLE BIT RATE GENERATOR
CONFIGURATION PROVIDING FIVE BIT RATES.

f

5SpF
SPF JO

Other bit rate combinations can be generated by changing
the Scan Counter to Selector interconnection or by inserting
logiC gates Into this path.

2.4576 MHz
CRYSTAl.

19200 Baud Operation
Though a 19200 Baud signal is not Internally routed to the
multiplexer, the HD-4702 can be used to generate this bit
rate by connecting the 02 output to 1M input and applying
select code. An additional2-input NOR gate can be used to
retain the "Zero Baud" feature on select code 1 for the
HD-4702 (See Figure 3).

FIGURE 2. BIT RATE GENERATOR CONFIGURATION WITH
EIGHT SIMULTANEOUS FREQUENCIES.

6-12

• See Figure 4

HD~4702

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

PARAMETERS
Frequency
Series Resistance (Max)

FIGURE 3. 19200 BAUD OPERATION

TYPICAL CRYSTAL SPEC
2.457SMHz "AT" Cut
250

Unwanted Modes

-S.OdB (Min)

Type of Operation

Parallel

Load Capacitance

32pF+0.5

FIGURE 4. CRYSTAL SPECIFICATIONS

* See Figure 4

6-13

HD-6402/883 ,

mHARRIS

CMOS Universal Asynchronous
Receiver Transmitter (UART)

June 1989

Features

Description

• This Circuit is Processed in Accordance to Mil-Std883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

The HD-6402/883 is. a CMOS UART for interfacing com·
puters or microprocessors to an asynchronous serial data
channel. The receiver converts serial start, data, parity and
stop bits. The transmitter converts parallel data into serial
form and automatically adds start, parity and stop bits. The
data word length can be 5, 6,7 or 8 bits. Parity"may be odd
or even. Parity checking and generation can be inhibited.
The stop bits may be one or two or one and one-half when
transmitting 5 bit code.

• 8.0MHz Operating Frequency (HD-6402B/883)
• 2.0MHz Operating Frequency (HD-6402R/883)
• Low Power CMOS Design
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation
• Compatible with Industry Standard UARTs
• Single +5V Power Supply
• CMOS/TTL Compatible Inputs

Pinout

The HD-6402/883 can be used in a wide range of applications including modems, printers, peripherals and remote
data acquisition systems. Utilizing the Harris advanced
scaled SAJI IV CMOS process permits operation clock
frequencies up to 8.0MHz(500K Baud). Power requirements, by comparison, are reduced from 300mW to 1OmW.
Status logic increases flexibility and simplifies the user
interface.

Control Definition
HD1-6402/883 (CERAMIC DIP)
TOP VIEW
VCC

CONTROL WORD

TRC
EPE

C
L
S
2

C
L
S
1

RBRl

TBR4

a
a
a
a
a
a
a
a
a
a
a
a

PE

TBR3

1

FE

TBR2

OE

TBRl

1
1

SFD

TRO

RRC

TRE

ORR

TBRl

DR

TBRE

RRI

MR

GND

CLSl
CLS2
SBS
PI
CRl
TBR8
TBR7

RBR3

TBR6

RBR2

TBRS

1

1
1
1
1
1
1
1
1

Copyright © Harris Corporation 1989

6-14

CHARACTER FORMAT

P
I

E
P
E

S
B
S

a
a
a
a
a
a

a
a
a
a

a
a

a

1

a

1

1

1

x a
x 1

1
1
1
1
1
1

a
a
a
a

a
a
a
a
a
a
1

a
a

a

1

a

1
1
1
1

1

a
a
a
a

1

1

1

1
1

1
1

X

a

1

X

1

1

1
1

1

1

START
BIT

DATA
BITS

PARITY
BIT

STOP
BITS

1
1
1
1
1
1
1
1

5
5
5
5
5
5
6
6
6
6
6
6
7
7
7

ODD

1
1.5

a
a

a

1
1
X
X

a

1

1

a
a
a
a

a
a

a
1

1
1
1
1
1

1
1

a

1

1

1

1

x a
x 1

1

1

1

1

1

a
1

1

7
7
7
8
8
8
8
8
8

ODD
EVEN

1

EVEN

1.5

NONE

1

NONE

1.5

ODD

1

ODD

2
1
2
1
2
1
2
1
2
1
2
1
2

EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN

1

EVEN

2
1
2

NONE
NONE

HD-6402/883
Functional Diagram'
(28)
TBRa

(28)
(27)

TBRl

1
(24) TRE

_>-1-----1
1

(22)' TBRE

----cr-~__,

1
(23) TBRl

--LI

(40) TRC ~

1

TRANSMITTER
TIMING AND
CONTROL

1

1

1

L-------------tI~·_(~)TRO

1

I·

1
(38) CLSl

CONTROL
REGISTER

(37) CLS2

(34) CRl

(36) SBS
(16) SFD

~------------------------------~------+-- (~)EPE

-1I---t----~I_--1-----r----J-~--------------------~-- (3~PI

(21) MR

,-------------.-1--Ir--

(20) RRI

(17) RRC
(18) ORR

(19) DR'

_o-'--,r-

----'\)'--e>----\r---'V-c-'

(4) RRD

(16) SFD -......!.-...

• THESE OUTPUTS ARE
THREE STATE

'OE
(15)

• FE

(14)

(5)

• PE
(13)

6-15

(6) (7)

(8)

(9) (10)(11) (12)

HD-6402/883
Pin Description
PIN TYPE SYMBOL
1
2
3
4

I

VCC'
NC
GND
RRD

5

0

RBRB

6
7
B
9
10
11
12
13

0
0
0
0
0
0
0
0

RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE

14

0

FE

15

0

OE

DESCRIPTION.

PIN TYPE SYMBOL

Positive Vollage Supply
No Connection
Ground
A high level on RECEIVER REGiSTER
DISABLE forces the receiver holding outputs RBR1-RBRB to high impedance slate.
The contents of the RECEIVER BUFFER
REGISTER appear on .these three-slate
outputs. Word formats less than B characters are right justified to RBR1.
See Pin 5-RBRB
See Pin 5-RBRB
See Pin 5-RBRB
See Pin 5-RBRB
See Pin 5-RBRB
See Pin 5-RBRB
See Pin 5-RBRB
A high level on PARITY ERROR indicates
received parity does not match parity
programmed by control bits. When parity
is inhlbHed this output Is low.
A high level on FRAMING ERROR Indicates the first stop bH was Invalid.
A high level on OVERRUN ERROR Indicates the dala received flag was not cleared
before the last character was transferred
to the receiver buffer register•

16

I

SFD

17

I

RRC

1B

I

ORR

19

0

DR

20

I

RRI

21

I

MR

22

0

TBRE

DESCRIPTION
A high level on STATUS FLAGS DISABLE
forces the outputs PE, FE, OE, DR, TBRE
to a high Impedance state.
The Receiver register clock Is 16X the
receivenlala rate.
A low level on DATA RECEIVED RESET
clears the dala received output DR to a
low level.
A high level on DATA'RECEIVED Indicates
a character has been received and transferred to the receiver buffer register.
Serial dala on RECEIVER REGISTER INPUT is clocked Into the receiver register.
A high level on MASTER RESET clears PE,
FE, OE and DR to a low level and sets the
transmitter register empty (rRE) to a
high level 18 clock cycles after MR falling
edge. MR does not clear the receiver buffer
register. This input must be pulsed at least
once after power up. The HD-6402/883
must be master reset after pOwer up. The
reset pulse should meel VIH and tMR' Wait
18 clock cycles after the falling edge of
MR before beginning operation.
A high level on TRANSMITTER BUFFER
REGISTER EMPTY indicates the transmitter buffer register has transferred Its
data to the transmitter register and is
ready for new dala.

• A 0.1 pF decoupling capacitor from the vee pin to the GND Is recommended.

PIN TYPE SYMBOL
23

I

TBRL

24

0

TRE

25

0

TRO

26

I

TRB1

27
28
29
30

I
I
I
I

TBR2
TBR3
TBR4
TBR5

DESCRIPTION

PIN TYPE SYMBOL

A low level on TRANSMITIER BUFFER
REGISTER LOAD transfers dala from
inputs TBR1-TBR8 into the transmitter
buffer register_ A low to high transition
on TBRL initiates dala transfer to the
transmitter register. If busy, transfer is
automatically delayed so that the two characters are transmitted end to end.
A high level on TRANSMITTER REGISTER
EMPTY indicates completed transmission
of a character Including stop bHs.
Character data, slar! dala and stop bits
appear serially at the TRANSMITTER REGISTER OUTPUT.
Character dala is loaded Into the TRANSMITTER BUFFER REGISTER via inputs
TBR1-TBR8. For character formats less
than 8 bits the TBR8, 7 and 6 Inputs are
ignored corresponding to their programmed word length.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.

31
32
34

I
I
I
I

TBR6
TBR7
TBR8
CRL

35

I

PI

36

I

SBS

37

I

CLS2

38
39

I
I

CLS1
EPE

40

I

TRC

33

6-16

DESCRIPTION
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
A high level on CONTROL REGISTER
LOAD loads the control register with the
control word. The control word is latched
on the falling edge of CRL
A high level on PARITY INHIBIT InhlbHs
parity generation, parity checking and
forces PE output low.
A high level on STOP BIT SELECT selects
1.5 stop bits for 5 character format and
2 stop bHs for other lengths.
These Inputs program the CHARACTER
LENGTH SELECTED (CLS1Iow CLS210w
5 bHs) (CLS1 high CLS210w 6 bHs)
(CLS1 low CLS2 high 7 bHs)(CLS1 high
CLS2 high B bits.)
See Pin 37-CLS2.
When PI is low, a high level on EVEN
PARITY ENABLE generates and checks
even parHy. A low level selects odd parity.
The TRANSMITTER REGISTER CLOCK Is
16X the transmH dala rate.

Specifications HD-6402R/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ••.•..••.••.•.•••.•.••..•.••.••••••.•••• +8.0V
Input, Output or I/O Voltage Applied. . . .• GND-O.SV to VCC+O.SV
Storage Temperature Range •••••.•.••..•.••. -6So C to +lS00C
JunctionTemperature ••••...•••••••..•••••.....•.•..• +17So C
Lead Temperature (Soldering 10 sec) •...••••.•...•••••• +3000 C
ESD Classification ••.••••.•••••••••••.••••.••..•••.••. Class 1
Typical Derating Factor •••••••.•••• 1 mNMHz Increase in ICCOP

Thermal Resistance
ala
ale
Ceramic DIP Package. • • . • . • • . • • • • • • •• 48.3 0 C/W 14.80 C/W
o
Maximum Package Power Dissipation at +12S C
Ceramic DIP Package .•.•..••••.•••••••••••••••.••••. 1.03W
Gate Count .•••••••.••.•..•..•••.••.•••••••••••.. 1643 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause pS/manent damage to the device. This is a stress only raling and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ••••...•.•.•••••••.••.. +4.SV to +S.SV
Operating Temperature Range •...•.••••..... -Ssoc to +12So C
TABLE 1. HD-6402R/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested.
LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

VCC=S.SV

1,2,3

-SSOC~TA~ +12SoC

VCC= 4.SV

1,2,3

-SSoC~TA~ +12SoC

II

VIN=GNDorVCC,
VCC=S.SV

1,2,3

Logical "1" Output
Voltage

VOH

10H = -2.SmA,
VCC = 4.SV, (Note 1)

Logical "1" Output
Voltage

VOH

Logical "0" Output
Voltage

VOL

D.C. PARAMETERS

SYMBOL

Logical "1 " Input Voltage

VIH

Logical "0" Input Voltage

VIL

Input Leakage Current

MAX

UNITS

2.3

-

V

-

0.8

V

-SSOC~TA~ +12So C

-1.0

1.0

pA

1,2,3

-SSOC~TA~ +12S oC

3.0

-

V

10H = -100pA,
VCC = 4.SV, (Note 1)

1,2,3

-SSOC~TA~ +12So C

VCC
-0.4

-

V

10L = +2.SmA,
VCC = 4.SV, (Note 1)

1,2,3

-SSOC~TA.$:

-

0.4

V

CONDITIONS

+12So C

Output Leakage Current

10

VO = GND orVCC,
VCC=S.SV

1,2,3

-SSoC.$: TA.$: +12SoC

-1.0

1.0

pA

Standby Supply Current

ICCSB

VIN = GND orVCC;
VCC=S.SV
Output Open

1,2,3

-SSoC.$:TA~+12SoC

-

100

pA

TABLE 2. HD-6402R/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

A.C. PARAMETERS

SYMBOL

(NOTE 2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

-SSOC~TA.$:+12S0C

-

2.0

MHz

Clock Frequency

(1) 'CLOCK

9,10,11

Pulse Widths,
CRL, ORR, TBRL

(2)tpW

9,10,11

-SSOC.$:TA.$:+12S0C

lS0

-

ns

VCC=4.SV
CL=SOpF

Pulse Width MR

(3)tMR

9,10,11

-SSoC.$:TA.$:+12S0C

150

-

ns

Input Data Setup Time

(4)tSET

9,10,11

-SSOC.$:TA.s. +12S oC

50

-

ns

(S)tHOLD

9,10,11

-SSOC.$:TA~ +12S oC

60

-

ns

9,10,11

-SSOC.$: TA~ +12S oC

-

160

ns

Input Data Hold Time
Output Enable Time
NOTES:

(6) tEN

1. Interchanging of force and sense conditions is permitted.

2. Tested with input levels of VIH = 2.76V and VIL = O.4V.
Rise and fall times are driven at 1 nsN.

CAUTION: This device Is sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

6-17

Specifications HD-6402R/883
TABLE 3. HD-6402R/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
A.C. PARAMETERS

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

CIN

f= 1MHz
All Measurements are
Referenced to Device GND

3

TA=+250C

pF

TA=+250C

25.0

pF

3

-55°C 5. TA 5. + 125°C

-

25.0

3

2.0

mA

Input Capacitance
Output Capacitance

CO
ICCOP

Operating Supply
Current

VCC=5.5V,
Clock Freq. = 2MHz
VIN = VCC or GND,
Outputs Open

NOTE: 3. The Parameters listed in Table 3 are controlled via daslgn or process parameters and Bre not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3, 8A, BB, 10, 11

-

1,2,3,7, BA, BB, 9, 10, 11

Samples/5OD5

1,7,9

Group A
GroupsC&D

CAUTION: This device Is sensHlve to electrostaUc discharge. Proper I.C. handling procedures should be followed.

6-18

Specifications HD-6402B/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage ....•.•....•.••....••..•........••.•..•• +8.0V
Input, Output or 1/0 Voltage Applied. • • .• GND-0.5V to VCC+0.5V
Storage Temperature Range •.•••••••.••••.•• -650C to +1500 C
Junction Temperature ••••.•••••••.•..•.••.•.••.••.••• +1750 C
Lead Temperature (Soldering 10 sec) ••••.••.•••.•••.••• +300 0C
ESD Classification ••••••••••••.•••••••.•••••••••••••.• Class 1
Typical Derating Factor .•••••••.••• 1 mNMHz Increase in ICCOP

Thermal Resistance
0ja
0jc
Ceramic DIP Package .•••......•..•... 48.30 C/W 14.80 C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ••••••...•.•.••••••••.••••.••.•• 1.03W
Gate Count •••.•••••.••.••••••••••.••••••••.•••.. 1643 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Operating Voltage Range ....................... +4.5V to +5.5V
Operating Temperature Range •.•••••.••••..• -550C to +1250 C
TABLE 1. HD-6402B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested.

D.C. PARAMETERS

SYMBOL

Logical "1" Input Voltage

VlH

Logical "O"lnput Voltage

VIL

Input Leakage Current

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

VCC=5.5V

1,2,3

-550 C.=>TA'=> +1250 C

2.3

-

V

VCC=4.5V

1,2,3

-550 C.=>TA'=> +1250 C

-

0.8

V

1,2,3

-55 0C.=>TA.=>+1250C

-1.0

1.0

pA

CONDITIONS

"

VIN = GND or VCC,
VCC=5.5V

Logical "'" Output
Voltage

VOH

10H = -2.5mA,
VCC = 4.5V, (Note 1)

1,2,3

-55 0C.=>TA.=>+1250C

3.0

-

V

Logical "1" Output
Voltage

VOH

10H = -100~A,
VCC = 4.5V, (Note 1)

"1,2,3

-55 0C.=>TA'=> +125 0C

VCC
-0.4

-

V

Logical "0" Output
Voltage

VOL

10L = +2.5mA,
VCC = 4.5V, (Note 1)

1,2,3

-55 0C.=>TA.=>+1250C

-

0.4

V

Output Leakage Current

10

VO = GND orVCC,
VCC=5.5V

1,2,3

-550 C.=>TA.=>+1250C

-1.0

1.0

pA

Standby Supply Current

ICCSB

VIN = GND orVCC;
VCC=5.5V
Output Open

1,2,3

-55°C.=> TA::;: +1250 C

-

100

~A

TABLE 2. HD-6402B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

A.C. PARAMETERS

(NOTE 2)
CONDITIONS

SYMBOL

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Clock Frequency

(1)fCLOCK

9,10,11

-55 0 C:O;TA:O; +1250 C

-

8.0

MHz

Pulse Widths,
CRL, DRR, TBRL

(2)tpW

9,10,11

-55 0C:O;TA::;:+1250C

75

-

ns

Pulse Width MR

(3)tMR

9,10,11

-550C:O;TA::;: +1250 C

150

(4)tSET

9,10,11

-550 C:O;TA:O; +1250 C

20

Input Data Hold Time

(5)tHOLD

9,10,11

-55°C.=> TA::;: +1250 C

20

-

ns

Input Data Setup Time

Output Enable Time

(6) tEN

9,10,11

-550C::;: TA::;: +1250 C

-

35

ns

NOTES:

VCC=4.5V
CL= 50pF

1. Interchanging of force and sense conditions is permitted.

2. Tested with input levels of VIH

= 2.76V

and VIL

= O.4V.

Rise and fall times are driven at 1nsN.

CAUTION: This device is sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

6-19

ns
ns

Specifications HD-6402B/883
TABLE 3. HD-6402B/S83 A.C; ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
A.C. PARAMETERS

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

CIN

f=1MHz
All Measurements are
Referenced to Device GND

3

TA=+2SoC

-

2S.0

pF

3

TA';'+2S0C

-

2S.0

pF

VCC=S.SV,
Clock Freq. = 2MHz
VIN = VCC or GND,
Outputs Open

3

-SSOC::;TA::; +12SoC

-

2.0

rnA

Input Capacitance
Output Capacitance

CO

Operating Supply
Current

ICCOP

NOTE: 3. The Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested, These parameters are characterized
upon initial design and after major process and/or design changes.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test _

100%/S004

-

Interim Test

100%/S004

1,7,9

PDA

100%

1

Final Test

100%

2,3,8A,8B,10,11

Group A

-

GroupsC&D

Samples/SOOS

- 1,2,3,7,8A,8B,9,10,11
1,7,9

CAUTION: This device Is sensftive 10 electrostallc discharge. Proper I.C. handling procedures should be followed.

6-20 .

HD-6402/883
Switching Waveforms
CLS1, CLS2, SBS, PI, EPE

SFD
RRD

STATUS OR

RBAI

DATA INPUT CYCLE

.RBR8 _ _-\-_ _- J

STATUS FLAG OUTPUT ENABLE TIME
OR DATA OUTPUT ENABLE TIME

CONTROL REGISTER LOAD CYCLE

A. C. Testing Input, Output Waveform
VlH

+

INPUT
20% VlH ---....,

VlL -50% VlL

OUTPUT
, . - - - - - VOH
1.5V
VOL

7(

1.5V~......_ _ _ _ _

A.C. Tesling: All input signals must switch between VIL - 50% VIL and VIH

20% VIH. Input rise and fall times are driven at 1nsN.

Test Circuit
OUT

00---1. . --c L*

~

* Includes stray and jig capacitance. CL

6-21

= 50pF

+

: HD-6402/883
Burn-In Circuits
HD-6402/883 CERAMIC DIP

DETAIL~

vee

vee

NOTE: One Per Output

FO
R1
R1
R1
R1
R1
R1
R1

DETAIL~

vee

R1
R1

NOTE: One Per Board

R1

~e

R1
R1
R1
R1

NOTES:
vee = 5.5V ± 0.5V
FO = 100kHz ± 10%
R1 = 47kO, 1/4W ± 10%

C = 0.01 F minimum
.... One socket par board should not be loaded,
but rather have pin 24 go the lie" oftha 4011.

6-22

vee
vee
vee
vee
GND
GND

vee
GND

vee
GND

vee
GND

vee
GND

HD-6402/883

Metallization Topology
DIE DIMENSIONS: 126.4 x 134.3 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 10kA - 12kA
GLASSIVATION:
Type: Si02
Thickness: 7kA - 9kA
DIE ATTACH:
Material: Gold/Silicon Eutectic Alloy
Temperature: Ceramic DIP - 460 0 C (Max)
WORST CASE CURRENT DENSITY: 1.42 x 105 A/cm 2

Metallization Mask Layout
HD-6402/883
RBR8

RRD GND NC VCC

TRC

EPE CLSl CLS2 SBS

PI
CRL
TBRS

TBR7

TBR6

TBRS
RBR3
TBR4

RBR2
RBRl

TBR3

z
'"

PE

<~

TBR2

t;t!;;:

CI U

",2:

FE

o~

OE

TBRl

SFO

TRO

:;::;:
u:;:
0
U

RRC

ORR

DR

MR

RRI

6-23

TBRE

TBiiI TRE

HD~6402/883

Packaging t
40 PIN CERAMIC DIP
2.035

Ij:

r-_1l====~2.09~6=====1
1

II

.1~0

lAIN

.

~.098IAAX

O·
15·

.100
BSC
• INCREASE MAX UIAIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
'
Material: Glass Frit
Temperature: 4500 C ± 100 C
Method: Furnace,Seal

NOTE: All Dimensions are

~!'x

I

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-5

t MiI-M-3B510 Compliant Materials, Finishes, and Dimensions.

Dimensions are In inches.

6-24

mHARRIS

HD-6402

DESIGN INFORMATION

CMOS Universal Asynchronous
Receiver Transmitter (UART)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Transmitter Operation
The transmitter section accepts parallel data, formats the
data and transmits the data in serial form on the Transmitter
Register Output (TRO) terminal (See serial data format).
Data is loaded from the inputs TBR1-TBR8 into the
Transmitter Buffer Register by applying a logic low on the
Transmitter Buffer Register load (TBRl) input (A). Valid
data must be present at least tset prior to and thold
following the rising edge of TBRL. If words less than 8 bits
are used, only the least significant bits are transmitted. The
character is right justified, so the least significant bit corresponds to TBR1 (B).

The riSing edge of TBRl clears Transmitter Buffer Register
Empty (TBRE). 0 to 1 Clock cycles later, data is transferred
to the transmitter register, the Transmitter Register Empty
(TRE) pin goes to a low state, TBRE is set high and serial
data information is transmitted. The output data is clocked
by Transmitter Register Clock (TRC) at a clock rate 16 times
the data rate. A second low level pulse on TBRl loads data
into the Transmitter Buffer Register (C). Data transfer to the
transmitter register is delayed until transmission of the current data is complete (D). Data is automatically transferred
to the transmitter register and transmission of that character
begins one clock cycle later.

:::~~ I ~~jl

TRANSMITTER TIMING
(NOT TO SCALE)

;;:

-:-11

I- 0 TO I CLOCK

o

: CDI ®I

t-- 112 CLOCK

DATA

rh

®C

rEND OF LAST STOP BIT

Receiver Operation
Data is received in serial form at the Receiver Register Input
(RRI). When no data is being received, RRI must remain
high. The data is clocked through the Receiver Register
Clock (RRC). The clock rate is 16 times the data rate. A low
level on Data Received Reset (ORR) clears the Data Receiver (DR) line (A). During the first stop bit data is transferred
from the Receiver Register to the Receiver Buffer Register
(RBR) (B). If the word is less than 8 bits, the unused most
significant bits will be a logic low. The output character is

right justified to the least significant bit RBR1. A logic high
on Overrun Error (OE) indicates overruns. An overrun occurs when DR has not been cleared before the present
character was transferred to the R SA. One clock cycle later
DR Is reset to a logic high, and Framing Error (FE) is evaluated (C). A logic high on FE indicates an invalid stop bit was
received, a framing error. A logic high on Parity Error (PE)
indicates a parity error.
"... BEGINNING OF FIRST STOP BIT

I

RRI

L

- I f- 7'1. CLOCK CYCLES

RBRI·B. DE. PE
RECEIVER TIMING
(NOT TO SCALE)

~f.l

ORR
OR

-CD®

FE

- I CLOCK CYCLE

o
SERIAL DATA
FORMAT

START BIT

5·8 DATA BITS

I. I';' OR 2 STOP BITS

/~\~~I_LS~81~~~~~~IM_SB~I'~~~
PARITY

6-25

'IF ENABLED

HD-6402

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Start Bit Detection
The receiver uses a 16X clock timing. The start bit could
have occurred as much as one clock cycle before It was detected, as Indicated by the shaded portion (A). The center of
the start bit is defined as clock count 7 1/2. H the receiver
clock Is a symmetrical· square wave, the center of the start

bit will be located within ±1/2 clock cycle, ±1/32 bit or
3.125% giving a receiver margin of 46.875%. The receiver
begins searching for the next start bit at the center of the
first stop bit.

CLOCK
' - - COUNT 7'hOEFINEO

RRIINPUT

!=A'1====-irY.i~S~T~AR~T:Yci:ES===:l-- CENTER OF START BIT

I

I.
7Y. CLOCK CYCLES
, . . . - - - - - - BY. CLOCK CYCLES - - - . o j

Interfacing With The HD-6402

RECEIVER

TRANSMITTER
TBRI
TBRB

RBI

TRO

RRI
CONTROL

DIGITAL
SYSTEM

HO·6402

HO·6402

CONTROL
RRI

TRO

TBRI
TBRB
TRANSMITTER

TYPICAL SERIAL DATA LINK

6-26

DIGITAL
SYSTEM

m

HARRIS

HD-6409/883
CMOS Manchester Encoder-Decoder

June 1989

Features

Pinouts

• This Circuit is Processed in Accordance to Mil-Std-SS3 and is Fully
Conform ant Under the Provisions of Paragraph 1.2.1.
• Converter or Repeater Mode
• Independent Manchester Encoder and Decoder Operation
• Static to One Megabit/sec Data Rate Guaranteed
• Low Bit Error Rate
• Digital PLL Clock Recovery
• On Chip OSCillator
• Low Operating Power: 50mW Typical at +5V
• Available in 20 Pin Dual-In-Line and 20 Pad LCC Package

,

HD1-64D9/883 (CERAMIC DIP)
TOP VIEW
VCC
BOO
BZO

SS
ECLK
CTS
MS

Description

ox

The HD-6409/883 Manchester Encoder-Decoder (MED) is a high speed,
low power device manufactured using self-aligned silicon gate
technology. The device is intended for use in serial data communication,
and can be operated in either of two modes. In the converter mode; the
MED converts Nonreturn-to-Zero code (NRZ) into Manchester code and
decodes Manchester code into Nonreturn-to-Zero code. For serial data
communication, Manchester code, does not have some of the deficiencies
inherent in Nonreturn-to-z'ero code. For instance, use of the MED on a
serial line eliminates DC components, provides clock recovery, and gives a
relatively high degree of noise immunity. Because the MED converts the
most commonly used code (NRZ) to Manchester code, the advantages of
using Manchester code are easily realized in a serial data link.

IX

HD4-64D9/883 (CERAMIC LCC)
TOP VIEW

t!l LZJ L~J LlLC! t1JJ
SO I CDS

-..

p-

1J

SRST

~l

NVM

Il

-

L~8 BZO

SDO ~l

In the Repeater mode, the MED accepts Manchester code input and reconstructs it with a recovered clock. This minimizes the effects of noise on a
serial data link. A digital,phase lock loop generates the recovered clock. A
maximum data rate 0.1 1MHz requires only 50mW of power.

[f7 SS

[fa
[{s

ECLK

CTS

p-

DCLK

Manchester code is used in magnetic'tape recording and in fiber optic
communication, and generally is used where data accuracy is imperative.
Because it frames blocks of data, the HD-6409/883 easily interfaces to
protocol controllers.

Block Diagram

co

GND

I1J r-" r-" r-.. 1'_"

1'_'1

19 1 11a! 1111 '121 11:j

I~

c 0
Z
0

C!l

~

Lt4 MS

en

~

z

<~
~!;;:

Q

en;;:

Q:::>

:;::;:
Co>:;:
Q
Co>

Logic Symbol
BDO

iMi
801

800

BZI

iiZO

UDI

en.

SS

CLOCK
GENERATOR

co
so-

13
12

19

CDS
ECLK
ENCODER

ox
IX

BOO
BZO
CTS

SRST

~
RST

~--------------------~--------~~
IX.....J"'---"'I

ox-,_ _--'

~==============ECLK
~

DCLK

co_----------.....J
Copyright @) Harris Corporation 1989

6-27

Co>

SDO
DCLK
NVM
SRST

CONTROL

5
8

7
6

3
DECODER

BOI
BZI
UDI

HD-64 09/883
Pin Description
PIN
NUMBER

TYPE

SYMBOL

1

I

BZI

Bipolar Zero Input

Used in con unction with pin 2, Bipolar One Input (BOI), to input
Manchester II encoded data to the decoder, BZI and BOI are logical
complements. When using pin 3, Unipolar Data Input (UDI) for data
input, BZI must be held high. ,

2

I

BOI

Bipolar One Input

Used in con unction with pin 1, Bipolar Zero Input (BZI), to input
Manchester II encoded data to the decoder, BOI and BZI are logical
complements. When using pin 3, Unipolar Data Input (UDI) for data
input, BOI must be h~ld low..

3

I

UDI

Unipolar Data Input

An alternate to bipolar input (BZI, BOI), Unipolar Data Input (UDI) is
used to input Manchester II encoded data to the decoder. When using
pin 1 (BZI) and pin 2 (BOI) for data input, UDI must be held low.

4

I/O

SO/CDS

Serial Data/Command
Data Sync

In the converter mode, SO/CDS is an input used to receive serial NRZ
data. NRZ data is accepted synchronously on the falling edge of
encoder clock output (EClK). In the repeater mode, SO/CDS is an
output indicating the status of last valid sync pattern received. A high
indicates a command sync and a low indicates a data sync pattern.

5

0

SDO

Serial Data Out

The decoded serial NRZ data is transmitted out synchronously with
the decoder clock (DClK). SDO is forced low when RST is low.

e

0

SRST

Serial Reset

In the converter mode, SRST follows RST.ln the repeater mode,
when RST goes low, SRST goes low and remains low after RST goes
high. SRST goes high only when FiST is high, the reset bit is zer!>, and
a valid synchronization sequence is reCeived.,

7

0

NVM

Nonvalid Manchester

A low on NVM indicates that the decoder has received invalid
Manchester data and present data on Serial Data Out (SDO) is invalid.
A high indicates that the sync pulse and data were valid and SDO is
valid. NVM is set low by a low on RST, and remains low after RST goes
high until valid sync pulse followed by two valid Manchester bits is
received.

8

0

DCLK

Decoder Clock

The decoder clock Is a 1 X clock recovered from BZI and BOI to
synchronously output received NRZ data (SDO).

9

I

RST

DESCRIPTION

NAME

Reset

In the converter mode, a low on RST forces SDO, DClK, NVM, and

SRST low. A high on FiST enables SDO and DCLK, and forcesSRST
high. NVM remains low after RST goes high until a valid sYnc pulse
followed by two Manchester bits is received, after which it goes high.
In the repeater mode, RST has the same effect on SDO, DClK and
NVM as In the converter mode. When RST goes 10w,SRST goes low
and remains low after RST goes high. SRST goes high only when
FiST Is high, the reset bit is zero and a valid synchronization sequence
Is received.

(I) Input

(0) Output

6-28

HD-6409/883
Pin Description

(Continued)

PIN
NUMBER

TYPE

SYMBOL

10

I

GND

11

0

Co

12

I

13

NAME

DESCRIPTION

Ground

Ground

Clock Output

Buffered output of clock input IX. May be used as clock signal for
other peripherals.

IX

Clock Input

IX is the input for an external clock or, if the internal oscillator is
used, IX and Ox are used for the connection of the crystal.

0

Ox

Clock Drive

If the internal oscillator is used, Ox and IX are used for the
connection of the crystal.

14

I

MS

Mode Select

MS must be held low for operation in the converter mode, and
high for operation in the repeater mode.

15

I

CTS

Clear to Send

In the converte~e, a high disables the encoder, forcing
outputs BOO, BZO high and ECLK low. A high to low transition of
CTS initiates transmission of a Command sync pulse. A Iowan
CTS enables BOO, BZ5, and ECLK.ln the repeater mode, the
function of CTS Is identical to that of the converter mode with the
exception that a transition of CTS does not initiate a synchronization sequence.

16

0

ECLK

Encoder Clock

In the converter mode, ECLK is a 1X clock output used to receive
serial NRZ data to SO/CDS. In the repeater mode, ECLK is a 2X
clock which is recovered from BZI and BOI data by the digital
phase locked loop.

17

I

SS

Speed Select

A logic high on SS sets the data rate at 1/32 times the clock
frequency while a low sets the data rate at 1/16 times the clock
frequency.

18

0

BZO

Bipolar Zero Output

BZO and its logical complement BOO are the Manchester data
outputs of the encoder. The inactive state for these outputs is in
the high state.

19

0

BOO

Bipolar One Out

See pin 18.

20

I

VCC

VCC

VCC is the +5V power supply pin. A 0.1 "F decoupling capacitor
from VCC (pin-20) to GND (pin-l0) is recommended.

(I) Input

(0) Output

6-29

Specifications HD-6409/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••.•••••••••••••••••••••.•.•••••• +7.0V
Input, Output or I/O Voltage Applied. • • .• GND-O.SV to VCC+O.SV
Storage Temperature Range •.•. .-............ -6So C to +1S00C
Junction Temperature •.••• , ..•.•••••••••••••.•••••••• +17S oC
Lead Temperature (Soldering 10 sec) .•.•••••••.•.•••••• +300 0C
ESD Classification •.••••••••••••••••••••.••••••••••••• Class 1

Thermal Resistance
Dja
Ceramic DIP Package. . • • • • • • • • • . . •
B3 0C/W
Ceramic LCC Package ••••••••.• ; • •
B4oC/W
Maximum Package Power Dissipation at +12S0 C
Ceramic DIP Package ••••••••••. , , •.••••••.••••••••• 602mW
Ceramic LCC Package •••.•••••••••••••••.••••••••• S9SmW
Gate Count .•••••••••••• ~ •.•••••••••••••••.••••••• 2S0 Gates

CAUTION.: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the devIce. This is a stress only rating and operation
of the device at these or any olher conditions above Ihose indicated in the operational sections of, this specification ;s not implied.

Operating Conditions
Operating Temperature Range •.••••••••.•••• -SSoC to +12So C . Sync. Transition Span it2) .•••••••..• 1.S DBPTypical, (Notes 1,2)
Operating Voltage Range •.•..•.•••••••••.•••.•• +4.5V to +S.5V Short Data Transition Span (t4) •.•••• O.S DBP Typical, (Notes 1, 2)
tnput Rise and Fall Times ••••••••••.••••••••••.••••••. SOns Max
Long Data Transition Span (tS) •..•.•• 1.0 DBP Typical, (Notes 1,2)
Zero Crossing Tolerance (ICDS) •.•.•••••••••.•.•••.••• (Note 3)
NOTES: 1. CBP-Cata Bft Period. Clock Rate = 1eX, one CBP

= 1e Clock Cycles; Clock Rate = 32X, one CBP = 32 Clock Cycles.

2. The input conditions specified are nominal values, the actual Input waveforms transition spans may vary by ± 21X clock cycles (16X mode) or ± 6
IX clock cycles (32X mode).
3. The maximum zero crossing tolerance is ± 2 IX clock cycles (16X mode) or ± 6 IX clock cycles (32 mode) from the nominal.

TABLE 1. HD-6409/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN
70%
VCC

Logic '1' tnput Voltage

VIH

VCC=4.5V

1,2,3

-550C~TA~+1250C

Logic 'O'input Voltage

VlL

VCC= 4.SV

1,2,3

-SSoC ~TA < +12So C

-

Logic '1'Input Voltage
(Reset)

VIHR

VCC=5.5V

1,2,3

-5S0C~TA~+i250C

VCC
-0.5

Logic 'O'input Voltage
(Reset)

VILR

VCC=4.5V

1,2,3

-5S0C~TA~+1250C

Logic '1' Input Voltage
(Clock)

VlHC

VCC=S.SV

1,2,3

Logic '0' Input Voltage
(Clock)

VILC

VCC=4.SV

Input Leakage Current
(Excepttx)

II

Input Leakage Current
(IX)

It

MAX

UNITS

-

V

20%VCC

V

-

V

-

GND
+O.S

-SSoC !::TA 5: +12SoC

VCC
-O.S

-

1,2,3

-S5 0C ~TA~ +125 0 C

-

VIN=VCCorGND
VCC=S.SV

1,2,3

-55°C :£TA'::; +1250 C

VIN=VCCorGND
VCC=S.SV

',2,3

V
V

GND
+O.S

V

-1.0

+1.0

JIA

-SSOC :£.TA ~ +12So C

-20

+20

JIA

VO Leakage Current

10

VOUT = VCC or GND
VCC=S.SV

1,2,3

-SSoC ~ TA'::; +12SoC

-10

+10

JIA

Output HIGH Voltage
(All except OX)

VOH

IOH=-2.0mA
VCC = 4.SV (Note 1)

1,2,3

-S50C:£TA'::;+1250C

VCC
-0.4

-

V

Output LOW Voltage
(All except OX)

VOL

IOL=+2.0mA
VCC = 4.SV (Note 1)

1,2,3

-SSOC.::;TA!::+1250C

-

0.4

V

Standby Power Supply
Current

ICeSB

VIN =VCC orGND,
VCC=S.SV,
Outputs Open

',2,3

-SSOC:£TA~+12S0C

-

100

JIA

Operating Power
Supply Current

ICCOP

f= 16.0MHz,
VIN=VCCorGND
VCC = S.5V, CL = SOpF

1,2,3

-SSOC!::TA:£+12S0C

-

1B.0

mA

7,8

-SSOC~TA:£+12S0C

-

-

-

Functional Test

FT

(Note 2)

NOTES: 1. Interchanging of force and sense conditions is permitted.
2. Tested as follows: f = 1eMHz, VIH = 70% VCC, VIL = 20% VCC, VOH

~

VCC12, and VOL

:s. VCC/2, VCC a

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

6-30

4.SV and S.SV.

Specifications HD-6409/883
TABLE 2. HD-6409/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 1)
CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Clock Frequency

fC

9.10.11

-SSOC.::;TA.$. +12So C

-

16

MHz

Clock Period

tc

9,10,11

-SSOC.::;TA'::;+12S0C

l/fC

sec

Bipolar Pulse Width

tl

9,10,11

-SSOC VCC/2, VOL < VCC/2, VCC = 4.5V and S.SV.
Input rise and fall times driven at 1nsN. Output load = 50pF.
.
-

TABLE 3. HD-6409/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

Input Capacitance

CIN

1,2

TA=+250C

-

10

pF

I/O Capacitance

ClIO

VCC = Open, f = 1 MHz
All Measurements
are referenced to
deviceGND

1,2

TA=+250C

-

12

pF

Output Rise Time
(All except Clock)

Ir

From 1.0 to 3.5V
CL=SOpF

1,2

-S5 0C.$.TA'::; +12So C

-

50

ns

Output Fall Time
(All except Clock)

If

From 3.S to 1.0V
CL= 50pF

1,2

-S50C.::;TA'::;+12S0C

-

SO

ns

Clock Output Rise Time

Ir

From 1.0 to 3.5V
CL=20pF

1,2

-550 C.::;TA'::;+1250C

-

11

ns

Clock Output Fall Time

tf

From 3.Slo 1.0V
CL=20pF

1,2

-S50C.::;TA'::;+1250C

-

11

ns

ECLK to BZO, BOO

tCE3

1,3

-5SoC.::;TA.::;+1250C

O.S

1.0

DBP

CTS Low 10 BZO
BOO Enabled

tCE4

1,3

-5S0C.::;TA.::;+1250C

O.S

1.5

DBP

CTS Low to ECLK
Enabled

ICES

1,3

-550 C.::;TA'::;+1250C

10.5

11.S

DBP

CTS High to ECLK
Disabled

ICE6

1,3

-550 C.::;TA'::;+12S0C

-

1.0

DBP

CTS High 10 BZO

ICE7

1,3

-S50C:5.TA:5.+12S0C

1.S

2.S

DBP

BOO Disabled
UDI to SDO, NVM

ICDl

1,3

-550 C.::;TA'::;+1250C

2.S

3.0

DBP

RST Low 10 DCLK,
SDO,NVMLow

ICD3

1,3

-S50C.::;TA.::;+1250C

O.S

1.5

DBP

RST High 10 DCLK,
Enabled

ICD4

1,3

-S50C:5.TA.::;+1250C

O.S

1.5

DBP

tRl

1,3

-550C.::;TA:5.+1250C

0.5

1.0

DBP

1R3

1,3

-5SoC.::;TA:5.+1250C

2.S

3.0

DBP

UDllo BZO, BOO
UDllo SDO, NVM
NOTES: 1. The parameters listed

In

table 3 are controlled via deSign or process parameters and are not directly tested.

2. Guaranteed via characteristics at initial device design and after major process and/or design changes.

3. CBP-Cata Bit Period, Clock Rate = 16X, one CBP = 16 Clock Cycle.; Clock Rate = 32X. one CBP = 32 Clock Cycle•.
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.e. handling procedures should be followed.

6-31

Specifications HD-6409/883
TABLE 4.

APPLICABLE SUBGROUPS

CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%

1

Final Test

100%

2,3, 8A, 8B, 10, 11

-

1,2,3,7, 8A,8B,9, 10, 11

Samples/5005

1,7,9

Group A
GroupsC&D

Timing Waveforms
NOTE: UDI

I---- BIT PERIOD

"

I'

= O.

FOR NEXT DIAGRAMS

"I'

BIT PERIOD

BOIJ=Tl~
1•

I

I'

COMMAND SYNC

I
I'

BOI

1-1---

--l I-F"Tl:j~

" 1 ...... T3

T2

I

BZI

BIT PERIOD-----l

I

T2

"'

I

I

.F~~~I

T2

I

BZI-FT1~

I

I

I'

I

DATA SYNC

--l I--

T3

f--

I

T4

I

--l I-- T3

T3

"I'

T5

"

I

ONE

I'

T5

I

ZERO

. NOTE: BOI
UDIJ ..

"

= 0;

BZI

---l I---

I

r

T3

---l l-- T3

FT1~

"

1•

T4

----i

I

ONE

= 1 FOR NEXT DIAGRAMS

.~

T2

I

i+=T3

,

FT1~

~

BZIL

T2

I

BOI.FT~~
~

COMMAND SYNC

I

T2

UDIJ.

1

DATA SYNC

I

·1·

UDlj04==.T4

I

T5

•I.

T5

I

ZERO

ONE

CLOCK TIMING

1'.-<
. ------

I

J--tr

1'-I

.1..

T4

..

I·

ONE

OUTPUT WAVEFORMS

te - - - - - -

11--

90'lIl

10%

T3

tCH

I

6-32

HD-6409/883
Timing Waveforms

(Continued)

ENCODER TIMING

ECLK _ _- I

SO/CDS

--------~

BZO ___- J
BOO ------,..

CTS

\\
BZO

\\~

BOO

\\..J'
ECLK

\\

BZO
BOO

6-33

;r

HD-6409/883
Timing Waveforms

(Continued)

DECODER TIMING

I
I
I
UOI

I
,
I
I
L----;-'--L.oJ
I MANCHESTER I MANCHESTER I MANCHESTER r MANCHESTER I
I LOGIC-' I LOGlC-O I LOGlC-O I LOGIC-, :
I
'CO,
~ f-- 'C02
1

~

SOD i

i\

I
:

I

I

i

-I1-'CD2

I

NVM:
rl

1'------:
NRZ
I LOGIC-1

I

-----T----~----~

1

NOTE: Manchester Data In is not synchronous with Decoder Clock.
Decoder Clock Is synchronous with decoded NRZ out of 500.

HST\6,",

RST

I

--.d,

I

I

HtI

~'-tc-O-3-+-1----

oCLK.~~~ -----.~'_5'"'_ _ __

CD4

oCLK~

REPEATER TIMING

Uol

MANCHESTER '"

MANCHESTER '0'

MANCHESTER '0'

MANCHESTER '"

ECLK

MANCHESTER '0"

soo

MANCHESTER '0'

~~~---..

-11

1....._ _ _ _ _ ••3 _ _ _ _ _ _

__________________~f~------------------

6-34

HD-6409/883

Test Load Circuit
DUT~

~·t
• INCLUDES STRAY AND JIG
CAPACITANCE

Burn-In Circuits
HD-S409/883 CERAMIC DIP

HM-S409/883 CERAMIC LCC

vee
A
A
R1

GND
A

R1
R1

GND

R1
L~J t~J L~J Lt-------------~--,

OUTPUT
INHIBrr

...

22>---~~~~--~--+-------_,

,

-----,

17

,.

{

..
,.

DECODER
UNIPOLAR

DATA IN
BIPOLAR
ONEtH
BIPOLAR
ZERO IN

BIPOLAR
ONE OUT
BIPOLAR

DECODER

CLK
MASTER
RESET

SERIAL

DATA IN

ENCODER

ENCODER

SHiff
elK

ENABLE

CHARACTER

IDENTIAER
10
" " " '_ _1"""01

COMMAND I DATA
SYNC
SERIAL
DATA OUT

ZEna OUT

SEND
DATA

TAKE DATA
TRANSITION
FINDER

SYNC
SELECT

Copyright @ Harris Corporation 1989

6-43

VALID
WORK

t---+--....;.... g~~DER
eLK

HD-15530/883
Pin Description
PIN
NUMBER TYPE

NAME

SECTION

DESCRIPTION

1

0

VAUDWORD

Decoder

Output high indicates receipt of a valid word, (valid parity and no Manchester
errors).

2

0

ENCODER SHIFT
CLOCK

Encoder

Output for shifting data into the Encoder. The Encoder samples SOlon the
low-ta-high transition of Encoder Shift Clock.

3

0

TAKE DATA

Decoder

Output is high during receipt of data after identification of a sync pulse and two
valid Manchester data bits.

4

0

SERIAL DATA OUT

Decoder

Delivers received data In correct NRZ formal.

5

I

DECODER CLOCK

Decoder

Input drives the trans~ion finder, and the synchronizer which in tum supplies
the clock to the balance of Ihe decoder, input a frequency equal to 12X the
data rate.

6

I

BIPOLAR ZERO IN

Decoder

A high input should be applied when the bus is in its negative state. This pin must
be held high when the Unipolar input is used.

7

I

BIPOLAR ONE IN

Decoder

A high input should be applied when the bus is in its positive state. This pin must
be held low when the Unipolar input is used.

8

I

UNIPOLAR DATA IN

Decoder

With pin 6 high and pin 7 low, this pin enters unipolar data into the transtition
finder circuit. If not used this input must be held low.

9

0

DECODER SHIFT
CLOCK

Decoder

Output which delivers a frequency (DECODER CLOCK + 12), synchronized by the
recovered serial data stream.

10

0

COMMAND SYNC

Decoder

Output of a high from this pin occurs during output of decoded data which was
preceded by a Command (or Status) synchronizing character. A low output
indicates a Data synchronizing character.

11

I

DECODER RESET

Decoder

A high input to this pin during a rising edge of DECODER SHIFT CLOCK resets
the decoder bit counting logic to a condition ready for a new word.

12

I

GROUND

Both

Ground Supply pin.

13

I

MASTER RESET

Both

A high on this pin clears 2:1 counters in both Encoder and Decoder, and resets the
+ 6 circuit.

14

0

+60UT

Encoder

Outputfrom 6:1 divider which is driven by the ENCODER CLOCK.

15

0

BIPOLAR ZERO

Encoder

An active low output designed to drive the zero or negative sense of a bipolar
line driver.

16

I

OUTPUT INHIBIT

Encoder

A low on this pin forces pin 15 and 17 high, the Inactive states.

17

0

BIPOLAR ONE OUT

Encoder

An active low output designed to drive the one or positive sense of a bipolar
line driver.

18

I

SERIAL DATA IN

Encoder

Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK.

19

I

ENCODER ENABLE

Encoder

A high on this pin initiates the encode cycle. (Subject to the preceeding cycle
being complete.)

20

I

SYNC SELECT

Encoder

Actuates a Command sync for,an Input high and Data sync for an input low.

21

0

SEND DATA

Encoder

An active high output which enables the external source of serial data.

22

I

SEND CLOCK IN

Encoder

Clock Input at a frequency equal to the data rate X2, usually driven by + 6 output.

23

I

ENCODER CLOCK

Encoder

Inputto the 6:1 divider, a frequency equal to the data rate X12 is usually Input here.

24

I

VCC

Both

vee is the +5V power supply pin. A 0.1 "F decoupling capacitor from VCC (pin 24)

OuT

to GROUND (pin 12) Is recommended.
1= Input

O=Oulput

6-44

Specifications HD-15530/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage .....•.•.••.•..•.••..•.•..•.•........... +7.0V
Input, Output or I/O Voltage Applied ....... GND-0.3V to VCC+0.3
Storage Temperature Range ................. -650C to +150 0 C
Junction Temperature .....•.•.••..•....•............. +175 0 C
Lead Temperature (Soldering 10 sec) ..•..•..........•.. +300 0 C
ESD Classification .................................... Class 1

ajc
aja
Thermal Resistance
Ceramic DIP Package.. . . . •. • .• .• . . 50.40 C/W
11.70 C/W
16.SoC/W
Ceramic LCC Package. . .. ... .. .. . .
71.1 0C/W
Maximum Package Power Dissipation at +1250 C
Ceramic DIP Package ................•.••....•.•.•• 992mW
Ceramic LCC Package ............................. 703mW
Gate Count .•..•.................................. 456 Gates

CAUTION: Stresses above those fisted in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions
Supply Voltage ...........•..•....•..•.......•• +4.5V 10 +5.5V
Ambient Operating Temperature Range (TN '" -550C 10 +125 0 C
Encoder/Decoder Clock Rise Time ..•..•.•........•... Sns Max
Encoder/Decoder Clock Fall Time ........•............ Sns Max

Sync Transition Span (TD2) •.•.••..•..... lS TDC Typical (Nolel)
Short Data Transition Span (TD4) ......•.. 6 TDC Typical (Notel)
Long Data Transition Span {TD5) .•••...•.. 12 TDCTypical (Notel)

TABLE 1. HD-15530/S83 D.C. ELECTRtCAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

CONDITIONS

LIMITS

GROUPA
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

Input LOW Voltage

VIL

VCC = 4.5V and 5.5V

1,2,3

-550C~:;:TA~+1250C

-

0.2VCC

V

Input HIGH Voltage

VIH

VCC = 4.5V and 5.5V

1,2,3

-550C~TA~+1250C

0.7VCC

-

V

Input LOW Clock
Voltage

VILC

VCC = 4.5V and 5.5V

1,2,3

-550C ::;TA::; +1250 C

-

GND+0.5

V

Input HIGH Clock
Voltage

VIHC

VCC = 4.5V and 5.5V

1,2,3

-550C::;TA5+1250C VCC-0.5

-

V

Output LOW Voltage

VOL

10L = 1.SmA (Note 2)
VCC=4.5V

1,2,3

-55 0 C::;TA::;+1250C

-

0.4

V

Output HIGH Voltage

VOH

10H =-3mA(Note2)
VCC=4.5V

1,2,3

-55°C ::;TA::; +1250 C

2.4

-

V

Input Leakage Current

II

VI = GNDorVCC
VCC=5.5V

1,2,3

-55 0 C::;TA::;+1250C

-1.0

+1.0

pA

ICCSB

VIN = VCC = 5.5V
OulputOpen

1,2,3

-550CSTA::;+1250C

-

2

mA

7,S

-550 C::;TA::;+1250C

-

-

-

Standby Supply
Current

FT

Funclion Test
NOTES: 1. TDC

= Decoder clock period =

(Note 3)
1/FDC

2. Interchanging of force and sense conditions is permiHed.
3. Tesled as follows: f

= lSMHz, VIH

= 70% VCC, VIL = 20% VCC, CL = SOpF, VOH~ 1.SV and VOLS 1.SV.

CAUTION: These devices are sensilive 10 electrostalic discharge. Proper I.C. handling procedures should b8 followed.

Specifications HD-15530/883
TABLE 2. HD-15530/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.5V

9,10,11

-550 C!>TA!5. +1250 C

-

15

MHz

VCC

=4.5 and 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V

9,10,11

-550C!>TA!> +1250 C

-

2.5

MHz

vce

9,10,11

-55°C!> TA!> + 1250C

-

1.25

MHz·

9,10,11

-550C!> TA!> + 125°C

150

-

ns

vee

9,10,11

-550 e!>TA!> +1250e

-

125

ns

vee

9,10,11

-550e~TA!> +1250 e

75

9,10,11

.-550 e ~ TA!> +1250e

75

9,10,11

-55°C!> TA !> + 1250C

90

9,10,11

-550C!> TA!> + 1250C

100

9,10,11

-550e!>TA~ +1250 e

55

9,10,11

-550e!>TA~ +1250 e

150

-

9,10,11

-55°C!> TA!> + 125°C

0

50

ns

9,10,11

-55°C!> TA!> + 1250C

-

130

na

9,10,11

-550 e!>TA!> +1250 e

10

9,10,11

-550 e!>TA!> +1250 e

95

-

ns

-

15

MHz

ENCODER TIMING
Encoder Clock
Frequency
Send Clock Frequency

FEC
FESC

Encoder Data Rate

FED

Master Reset Pulse
Widlh

TMR

Shift Clock Delay

TE1

Serial Dala Selup

TE2

Serial Dala Hold

TE3

Enable Selup

TE4

Enable Pulse Width

TE5

VCC

Sync Selup

TE6

Sync Pulse Widlh

TE7

Send Data Delay

TE8

Bipolar Output Delay

TE9

Enable Hold

TE10

Sync Hold

TE11

=4.5 and 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V
vce =4.5 and 5.SV
vce =4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V
vec =4.5 and 5.5V
vee =4.5 and 5.5V
vce =4.5 and 5.5V

FOe

vee

=4.5 and 5.5V

9,10,11

-550C~;TA~+1250e

Decoder Dala Rate

FDD

vee

-550C~TA!>+1250e

-

1.25

MHz

TOR

vee

=4.5 and 5.5V
=4.5 and 5.5V

9,10,11

Decoder Resel Pulse
Widlh

9,10,11

-55°C!> TA!> + 1250C

150

-

na

Decoder Resel Selup
Time

TORS

vce

=4.5 and 5.5V

9,10,11

-550C!> TA !> + 1250C

75

-

ns

Decoder Reset Hold
Time

TDRH

vee

=4.5 and 5.5V

9,10,11

-550C!> TA!> + 1250C

75

-

ns

Master Reset Pulse

TMR

vee

-55°C!> TA !> + 125°C

150

TD1

vce

=4.5 and 5.5V
=4.5 and 5.5V

9,10,11

Bipolar Dala Pulae
Widlh

9,10,11

-550e~TA!>+1250e

TDC+10
(Nole 1)

One Zero Overlap

TD3

vec

=4.5 and 5.5V

9,10,11

-55°C!> TA!> + 125°C

-

=4.5 and 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V

-

ns
ns
na
ns
ns
ns

ns

DECODER TIMING
Decoder Clock
Frequency

-

ns

TDC-10
(Nole1)

ns

ns

Sync Delay (ON)

TD6

VCC

9,10,11

-550C~TA!>+1250e

-20

110

na

Take Dala Delay (ON)

TD7

vee

9,10,11

-55°C!> TA!> + 125°C

0

110

ns

Serial Dala Oul Delay

TD8

9,10,11

-55°C !>TA!> +1250 e

-

80

ns

Sync Delay (OFF)

TD9

9,10,11

-550e~TA!>+1250e

0

110

ns

Take Dala Delay (OFF)

TD10

9,10,11

-550e~TA!> +1250 e

0

110

ns

Valid Word Delay

TD11

9,10,11

-55°C!> TA 5. + 125°C

0

110

ns

NOTES: 1. TDC = Decoder clock period = 1/FDC
2. A.C. Testing as follows: Input levels: VIH
load: CL = 50pF

= 70% vee, VIL = 20% vee; Input rise/falJ times driven at 1nsIY; Timing reference levels: 1.5V; Output

CAUTION: These devices are sensitive to electrostatiC discharge. Proper I.C. handling procedures should be followed.

6-46

Specifications HD-15530/883
TABLE 3. HD-15530/883 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

CI

VCC = OPEN, f = 1 MHz,
All Measurements
Referenced to Device GND

1

TA=+250C

-

15

pF

CIO

VCC= OPEN, f= lMHz,
All Measurements
Referenced to Device GND

1

TA=+25 0C

-

15

pF

1,2

-550C5TA5+250C

-

10

rnA

Inpul Capacitance

Input/Output
Capacitance

Operating Power
Supply Current

ICCOP

VCC = 5.5V, f = 1 MHz

NOTES: 1. The parameters listed in table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.

2. Guaranleed bul nol 100% tested.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3, 8A, 8B, 10, 11

Group A

Samples/5005

1,2,3,7, 8A,8B, 9, 10,11

GroupsC&D

Samples/5005

1,7,9

Test Load Circuit

'Includes Stray and Jig Capacitance

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

6-47

HD-15530/883
Timing Waveforms
ENCODER TIMING

SEND CLOCK
ENCODER SHIFT CLOCK
SERIAL DATA IN

--.J

I--TE1

~j-:-'T";;;E3"-------'
~

SEND CLOCK
ENCODER SHIFT CLOCK

----------!

ENCODER ENABLE
SVNCSELECT _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

ENCODERSHIFTCLOCK

--.J

SEND DATA _ _ _ _ _ _ _ _ _ _ _- J

SEND CLOCK

or

BIPOLAR ONE Oii'f
BIPOLAR fiiiO OUT

~
::::::::::~::::
-

DECODER TIMING

DECOOER SHIFT CLOCK
COMMANDIDATASVNC

SERIAL DATA OUT

DECDDER SHIFT CLOCK
COMMAND~SVNC

r-

I

TOO, ~r------------------------------------­
~1 ~---------------------- ------I

TAKE DATA

DECODER SHIFT CLOCK

I

~

--,!-,.--_ _ _ _ _......I

r-

......_ _ _ _ _ _......

=::::::OL
~~-------------~~--------DATA BIT
X'--_________
---'~""t:=~----...1
TD9-t

TAKE DATA TD1o=1

.....Ir--

L--_ _ _ _

________________________

I----

--:::11_~=

t--

LI_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

VALID WORD

6-48

HD-15530/883
Timing Waveforms

(Continued)

DECODER TIMING (Continued)

f--- BIT PERIOO

NOTE: UNIPOLAR IN = 0, FOR NEXT OIAGRAMS
• I•
BIT PERIOO
• 1•
BIT PERIOO---j

r-

BIPOLAR ONE IN .rTO'~///////////////////A;
I •
T02
• l.1:- Tol
-l I-- TOl
BIPOLAR ZERO IN -:-_ _ _ _ _ _ _ _-,-_ _~I-TO':v///ff/////////ft///////l

I--COMMAND SYNC

'1

T02

.,

,'

BIPOLAR ONE IN 1
:
F.To':v7///ff///////////~
I•
T02
• I t-- T03
. ; 1 - -T03
BIPOLAR ZERO IN -.FTo'~~/)z/A:
1

:

1•

i

r-

T02

•

1

OATASVNC

ONE

ZERO
NOTE: BIP?LAR ONE IN

UNIPOLAR IN

=

ONE

0; BIPOLAR ZERO IN = 1. FOR NEXT DIAGRAMS.

::Jj:.======iT~O;;2-=~'===:=;·:160·===~==..!Tgo2~=====:!:.~~:Z~~~~~~~2:~2:~2~2L
COMMAND SYNC

I

UNIPOLAR IN

=J~'~'=====::..!!TOQ!2t..=:::;====':fI=.===~==rToD:2i=====:::;'~~:2~:2~:2~:2~:2~:2~:2~:2:L

UNIPOLAR IN

.J--F:

DATA SYNC

:==T;To~4~:::;·11::':::::==::2T~o5C===·:lIF·;:::===-1T~O;;-5====·:J:I~.=..!T!:!:O!i4.::--+--::::l T04 ~

:

ONE

ZERO

6-49

ONE

ONE

HD-15530/883
Burn-In Circuits
HD1-15530/883 CERAMIC DIP

10------1
123If-....IIy'V'v-- FO

A - - - - - - il

_

-10------1
A--:R
:,,:,---i

I-t--:R:":,--

A

FO--'I/Io/v----i

I-+-'W.--

GND

Rl

I-HR",,"v-- vee
I-+-,W.,.....- GND

Rl
GND--'I/Io/V-++-I

Rl

A---+-H

I-+-,w\rf--

vee

:,,:,-+-H

A - - :R

GND--'I/Io/v-+-I--I
GND---++-I

I-'\M++- GND

Rl

Rl

vee

A~Rl
NOTES:

VCC

~

5.5V _:t O.5V

fRl

VIH = 4.5V :t 10'11>

GND

VIL = -O.2V to +O.4V

= 47KO:t 5'11>
FO = 100KHz :t 10'11>

Rl

Cl = O.olpF Min.

HD4-15530/883 CERAMIC LCC
R2

vce

GND
R2

GND

el

(

R2

GND
R2

~

GND

51..!, L!.. .1.. l!J Lt'll[!i i,2.J rz

FO
Ne
Ne

GND

-

<.

GND

!l

B
;;;

Ne

[~1

vee

<.

GND

~

...,

~

<•

9'

r:.

I!!

R2

1,j
[f~
-' 112Hi"" r1"r1~ 11 rr.;; ffa -

GND

IJvee

R2

NOTES:

VCC

VIL = -O.2V 10 +O.4V
R2 = I.BKO :t 5'11>
FO = 100KHz :t 10'11>
Cl

R2

= 5.5V :t O.5V

VIH = 4.5V :t 10'11>

R2

•

J1

-

~

R2

GND
GND
GND
GND

= O.OpF Min.

6-50

Ne
GND

HD-15530/883

Metallization Topology
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperalure: Ceramic DIP - 4600 C (Max)
Ceramic LCC - 420 0 C (Max)

DIE DIMENSIONS:
155 x 195 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 11 kA ± 2kA

WORST CASE CURRENT DENSITY:
1.a x 105A/cm2
LEAD TEMPERATURE (10 seconds soldering):
,S2750 C

GLASSIVATION:
Type: Si02
Thickness: akA ± 1kA

Metallization Mask Layout
HD-15530/883
ENCODER
SHIFT eLK

VALID

wonD vee

ENCODER elK

TAKE DATA

SERIAL DATA OUT

SEND DATA

UNIPOLAR DATA IN

DECODER SHIFT eLK

COMMAND/DATA SYNC

DECODER RESET

GND

MASTER
RESET

6-51

... 60UT

HD-15530/883
Packaging t
24 PIN (.600) CERAMIC DIP
1.240

M'N~m'=

'225~
.005

~~
Jaa

Ij:~

~ ~~li".
I~~J~ ~~

J

.016-

o·
15-

.~~~

.023

.050·
• INCREASE MAX WAIT BY .003 INCHES
MEASURED AT CENTER or FLAT FOR
SOlDER FlNISH

.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 4500 C ± 100C
Method: Furnace Seal

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 D-lO

28 PAD .CERAMIC LCC

.442

:45ii
.045

.050

asc

.055

'I

,

.064

,--1--.f Ji76

lin nn n n n nI I

&Z!Tl
.088

PAD MATERIAL: Type C
PAD FINISH: Type A
FINISH DIMENSION: Type A
PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina
PACKAGE SEAL:
Material: GoldfTin (80/20)
Temperature: 320 0C ± lOoC
Method: Furnace Braze

NOTE: All Dimensions are

~

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 C-4

t Mil-M-38S10 Compliant Materials, Rnishes, and Dimensions.

• Dimensions are in Inches.

6-52

Em HARRIS

HD-15530

DESIGN INFORMATION
CMOS Manchester Encoder-Decoder
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
Input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by
dividing the DECODER CLOCK.
The Encoder's cycle begins when ENCODER ENABLE Is
high during a falling edge of ENCODER SHIFT CLOCK CD.
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word ®. When the Encoder is ready to accept data,
the SEND DATA output will go high and remain high for
sixteen ENCODER SHIFT CLOCK periods @. During these
sixteen periods the data should be clocked into the SERIAL
DATA Input with every high-to-Iow transition of the

ENCODER SHIFT CLOCK so it can be sampled on the lowto-high transition @ - @. After the sync and Manchester II
coded data are transmitted through the BIPOLAR ONE and
BIPOLAR ZERO outputs, the Encoder adds on an additional bit which is the parity for that word @. If ENCODER
ENABLE is held high continuously, consecutive words will
be encoded without an interframe gap. ENCODER ENABLE
must go low by time @ as shown to prevent a consecutive
word from being encoded. At any time a low on OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
Internal counters and initializes the Encoder for a new word.

I 15 I 16 I 17 I 18 I 19 I

TIMING
SEND CLOCK
ENCODER
SHIFT CLOCK
ENCODER ENABLE

SVNCSELECT

~\\'SIVALI~\\\\\\\\\~ DON;T CARE~\\\\\\\\\~ }-\\\\\\\\\~\\\\\\\\.\.\\\\\\\\\\\\\\\\\W

s

SEND DATA

SERIAL DATA IN

15

14

13

12

11

110:

o

I

HD-15530

DESIGN INFORMATION

(Continued)

The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as applicatiop and design information only. No guarantee Is implied.

Decoder Operation
decoded data available at SERIAL DATA OUT is in NRZ
format. The DECODER SHIFT CLOCK is provided so that
the decoded bits can be shifted Into an external register on
every low-to-hlgh transition of this clock ® - @. Note that
DECODER SHIFT CLOCK may adjust its phase up until the
time that TAKE DATA goes high.

The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The BIPOLAR
ONE and BIPOLAR ZERO inputs will accept data from a
comparator sensed transformer coupled bus as specified in
Military Spec 1553. The UNIPOLAR DATA Input can only
accept non~inverted Manchester II coded data. (e.g. from
BIPOLAR ONE OUT of an Encoder through an inverter to
Unipolar Data Input).

After all sixteen decoded bits have been transmitted @
the data is checked for odd parity. A high on VALID WORD
output@) indicates a successful reception of a word without
any Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown -.;;MAS1:-:-;';::=ER~;.;.~"':.;;.=;;;.=Er;;...._.....--.

OUTPUT

u~~~:~~------., r-~~,

.......:'":;.":::'O:::IT-<28

~~~~~-.-+--+---~

__~~t-·5.

:~~

BIPOLAR
ZERO ,. ,.....",,______.....

D~O~:

DECODER

CLK SELECT
SYNCHRONOUS

Z8

29

SERIAL
DATA IN

so

II

COMMAND SYNC

ONE 1M

1-t.....--r:~~~'J..!.!!7. ::~
rt~

TAKE DATA

BIPOLAR

cue

B~~~

~

8YIfC
8Eu:cT

~~

....____...

....~__~.....: - ....TA SYNC

______.,

;~====~~
>'0''-_ _ _ _ _ _-'

5

SERIAL
DATAOUT
VALD WORK

.ARITV
SElECT

.--+-....:.;:.

:~'::~

>=••'---------:r~-L~-L..,

TAKE DATA

ENCODER
BHFT
eLK

ENCODER
ENABLE

ENCODER
PARity
SELECT

Copyright CI Harris Cotporatlon 1989

6-56

Pin Description HD-15531/883
PIN
NUMBER TYPE

NAME
VCC

1

SECTION

DESCRIPTION

Both

Positive supply pin. A 0.1 ~F decoupling capacilor from VCC (pin 1) to GROUND
(pin 21) Is recommended.
Output high Indicates receipt of a valid word, (valid parity and no Manchester errors).
A continuous, free running signal provided for host timing or data handling. When
data is present on the bus, this signal will be synchronized 10 the incoming data and
will be identical 10 take data.
Output is high during receipt of data after identification of a valid sync pulse and two
valid Manchester bils.
Delivers reCeived data in correct NRZ formal.
Input presenls Manchester data directiyto character identification logic.
SYNCHRONOUS DATA SELECT must be held high to use this inpul.lf not used this
pin must be held high.
In high state allows the synchronous data 10 enter the character identification logic.
Tie this input low for asynchronous data
Input provides externally synchronized clock to the decoder, for use when
receiving synchronous data. This Input must be tied high when not In use.
Input drives the transition finder, and the synchronizer which in turn supplies the
clock 10 the balance of the decoder. Input a frequency equal to 12X the data rate.
In high state direcls the SYNCHRONOUS CLOCK 10 control the decoder character
identification logic. A low state selec:1s the DECODER CLOCK.
A high Input should be applied when the bus is in ils negative state. This pin must be
held high when the unipolar input is used.
A high input should be applied when the bus is in ils positive state. This pin must be
held low when the unipolar input is used.
With pin 11 high and pin 12 low, this pin enters unipolar data into the transition finder
circuil. If not used this input must be held low.
Output which delivers a frequency (DECODER CLOCK + 12), synchronous by the
recovered serial data stream.
A high inputlo this pin causes the transition finder 10 synchronize on every transition
of input data A low input causes the transition finder to synchronize only on
mid-bit transitions.
Not connected.
Output of a high from this pin occurs during output of decoded data which was
preceded by a Command (or Status) synchronizing character.
An input for parity sense, ~lIing for even parity with input high and odd parity with
input low.
A high inputlo this p.in during a rising edge of DECODER SHIFT CLOCK resels the
decoder bit counting logic 10 a condition ready for a new word.
One of five binary inputs which establish the total bit count to be encoded or decoded.
Supply pin.
A high on this pin clears 2:1 counters in both encoder and decoder, and resels
the + 6 circuit.
See pin 20.
Output from 6:1 divider which is driven by the ENCODER CLOCK.
An active low output designed to drive the zero or negative sense of a bipolar line
driver.
A low on this pin forces pin 25 and 27 high, the inactive states.
An active low output designed 10 drive the one or positive sense of a bipolar line

3

0
0

VAUDWORD
TAKE DATA'

Decoder
Decoder

4

0

TAKE DATA

Decoder

5
6

0

SERIAL DATA OUT
SYNCHRONOUS
DATA

Decoder
Decoder

7

I

Decoder

8

I

9

I

10

I

11

I

SYNCHRONOUS
DATA SELECT
SYNCHRONOUS
CLOCK
DECODER
CLOCK
SYNCHRONOUS
CLOCKSELCT
BIPOLAR ZERO IN

12

I

BIPOLAR ONE IN

Decoder

13

I

Dec;oder

14

0

15

I

UNIPOLAR
DATA IN
DECODER SHIFT
CLOCK
TRANSITION
SELECT

16
17

0

N.C.
COMMAND SYNC

Blank
Decoder

DECODER
PARITY SELECT
DECODER RESET

Decoder

2

I

Decoder
Decoder
Decoder
Decoder

Decoder
Decoder

18

I

19

I

20
21
22

I

23
24
25

I
0
0

BiPcii:AR ZERO

Both
Encoder
Encoder

26
27

I
0

OUTPUT INHIBIT
BIPOLAR ONE

Encoder
Encoder

28
29

I
I

30
31

I
I

32
33
34

0
I
0

35
36
37
38

I
I
0

SERIAL DATA IN
ENCODER
ENABLE
SYNC SELECT
ENCODER
PARITY SELECT
SEND DATA
SEND CLOCK IN
ENCODER SHIFT
CLOCK
N.C.
COUNTC3
ENCODER CLOCK
DATA SYNC

39
40

I
I

COUNTC4
COUNTC1

I-Input

I

COUNT CO
GROUND
MASTER RESET
COUNTC2
+60UT

ffijf

Decoder
Both
Both
Both

ffijf

driver.
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Encoder
Blank
Both
Encoder
Decoder
Both
Both

Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK.
A high on this pin initiates the encode cycle. (Subjeclto the preceding cycle being
complete.)
Actuates a Command sync for an input high and Data sync \or an input low.
Sels transmit parity odd for a high input, even for a low inpul.
Is an active high output which enalbles the external source of serial data.
Clock input at a frequency equal to the data rate X2, usually driven by + 6 output.
Output for shifting data into the Encoder. The Encoder samples SDI pin-28 on the
low-io-high transition of ESC.
Not connected.
See pin 20.
Input to the 6:1 divider, a frequency equal to 12 times the data rate is usually input here.
Output of a high from this pin occurs during output of decoded data which was
preceded by a data synchronizing character.
See pin 20.
See pin 20.

0= Output

6-57

Specifications' HD-15531 /883,
Absolute Maximum Ratings

Reliability Information

f:jupplyVoltage- ••.•• ;: .... ~ '>~ ~""""" •••• ,; •••• :', ••••••• +7.0V, ..1hermai,R~sis~nce '.
,,'eja:
Input, Output or I/O Voltage Applied. • . .• GND-0.5V to VCC+0.5V· .. Ceramic Dlp'Package • . . . . . . . . . . • . • 34.S o C/W
0
Storage Temperature Range;.; ....• , .•.• : •..•• -650C to.+150 C
Maximum Package Power Dissipation at+1250C '
Junction Temperature· .:, •.•.•' .... '.••••• '.' ',' ••.•.•.• ',' .' +,175 0 C
Ceramic DIP Packa,ge •....•.••. '••.• ',' ., ... , .• '••••.••• lA4W
Lead Temperatu,e·(Soldering.l0 sec) ....', .................. c+3000 C .. Gate Count •..•...•..••. : ••••.••••..•••............• 250 Gates
ESD Classification .................•.•.•..••.••.•••.•• Class· 1
"'.
C

CAUTION: Stresses ~bove ~ho~e listed "Abso)uta Maximum Rtdings" may cause 'pe'man~':'t damage to the device. This is a stress on;y rat{ng and operation
of the device at these or any other conditions abo.v~ th~se indicated in the opera!j~.na/. s~ctioqs of this ~p~~jf;cat!On is not ;mpli~~.

in

Operating Conditions.

.'

. -,,'

Supplyvoltage .••.•••.•••••....•....••••.••.•• +4.5V to +5.5V
Ambient Operating Temperature' Range (TA) : : ..: ~550C to +1250 C
Encoder/Decoder Clock Rise Time (TECR, TDCR) ..•.... Sns MaX'
Encoder/Decoder Clock Fall time (TECF, ·T,?CF). : " . , ' .. ' • Sns Max
,

,,(-

Sync 'rra~s.ifi~~ Sp,m ,(TD2\ ..• , ••. : •.•.•. 1S TDC Typical (Notel;
Short Data Transition Span (TD4) .• :.: •• ~ '.:. 6 TDC Typical (Note1)
'Long b~ia Transitio!' Span (TD5) .• , .• :: .. , '12 TDCTypical (Note1)

.. TABLE 1. HD-15531/883 D.C.-ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

CONDITIONS

..

LIMITS

GROUPA:
SUBGROUPS

TEMPERATURE

MIN

. MJ!.X

UNITS

-55°C 5oTA5o +1250 C

-

0.2VCC

Y

-

V

GND+0.5

V

-

V

Input LOW VQltage

VIL

VCC = 4.5V and 5.5V

1,2,3

Input HIGH Voltage

VIH

VCC '=' 4.5V and 5.5V

.. 1,2,3

-550C 5oTA:$ +1250 C 0.7VCC

Input LOW Clock
Voltage

VILC

VCC = 4.5V and 5.5V

'. 1,2,.3.

-55°C 50TA 50 +1250 C

Input HIGH Clock
Voltage

,"

'VlHC

' VCC = 4.5V and 5.5V ..

Output LOW Voltage

VOL

.IOL,= 1.8mA (Note 2)
VCC=4.5V,

Output HIGH Voltage

VOW'

10H --3mA(Note2)'
VCC=4.5V

Input Leakage Current

"

Standby:.Su~pIY

Current
Function Test

-

.ICCS~

..

FT

VI = GND or VCC· .
VCC=5.5V
VIN=VCC=5.5V
Output Open "

..

(Note 3)

-55°C 50 TA 50 +1250 C VCC-0.5

1,2,3

-.
1,2,3

"

-550C 5oTA5o +1250 C

-

0.4

V

.-550 C.$TA:$+1250C

2.4

-

V

1,2,3

'-550 C .$ TA 50 + 125°C

-1.0

+1.0

pA

1,2,3

-55°C .$ TA 50 + 125°C

-

2

inA

7,S

-550C .$TA.$ :-1250 C

-

, -

'1,2,3. ,

".

'NOTES:, 1. TDC,,,; Decoder cloc~ period::, 1/FDC
2. Interchanging of force and sense conditions is permitled.
3. Tested as follows: f ,,; 1SMHz. VIH = 70% VCC. VIL

=' 20% VCC, CL =

SOpF. VOH ~ VCC/2 and VOL ~ V.CC/2.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

6-58

-

Specifications HD-15531/883
TABLE 2. HD-15531/883 A.C. ELECmlCAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

(NOTE 2)
CONDITIONS

SYMBOL

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

=4.5 and 5.5V

9,10,11

-550C.5TA!> +125 0C

-

15

MHz

ENCODER TIMING
Encoder Clock
Frequency

FEC

VCC

FESC

VCC

-550C.5 TA!> + 125°C

MHz

VCC

9,10,11

-550C.5 TA!> + 125°C

-

2.5

FED

1.25

MHz

Master Reset Pulse
Widlh

TMR

=4.5 and 5.5V
=4.5 and 5.5V
VCC =4.5 and 5.5V

9,10,11

Encoder Data Rate

9,10,11

-55°C .5 TA !> + 125°C

150

-

ns

VCC

9,10,11

-55°C!> TA.5 + 125°C

-

125

ns

VCC

9,10,11

-55°C .5 TA!> +1250 C

75

ns

9,10,11

-55°C!> TA.5 + 125°C

75

-

9,10,11

-550C!> TA!> + 1250C

90

-

ns

-

ns

Send Clock Frequency

ShiH Clock Delay

TE1

Serial Data Setup

TE2

Serial Data Hold

TE3

Enable Setup

TE4

=4.5 and 5.5V
=4.5 and 5.5V
VCC =4.5 and 5.5V
VCC =4.5 and 5.5V

Enable Pulse Width

TE5

VCC - 4.5 and 5.5V

9,10,11

-550 C:S.TA.5 +1250 C

100

Sync Setup

TE6

VCC

9,10,11

-550CSTA.5 +125 0C

55

Sync Pulse Width

TE7

9,10,11

-550 C:S.TA.5 +125 0C

150

-

Send Data Delay

TES

9,10,11

-550 C:S.TA:s' +125 0C

a

50

ns

Bipolar Output Delay

TEll

9,10,11

-550C.5TA:s' +125 0 C

-

130

ns

Enable Hold

TE10

9,10,11

-550C.5TA:s' +1250 C

10

Sync Hold

TE11

=4.5 and 5.5V
VCC =4.5 and 5.5V
VCC =4.5 and 5.5V
VCC =4.5 and 5.5V
VCC =4.5 and 5.5V
VCC =4.5 and 5.5V

9,10,11

-550 C!>TA:S.+1250C

95

-

FDC

VCC

=4.5 and 5.5V

9,10,11

-550C:S.TA:s' +1250C

-

15

MHz

Decoder Sync Clock

FDS

vce

-550 e.5TA.5 +1250e

MHz

vee

9,10,11

-550C !>TA:S. +1250C

-

2.5

FDD

1.25

MHz

Decoder Reset Pulse
Width

TOR

=4.5 and 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V

9,10,11

Decoder Data Rate

9,10,11

-550 e !>TA!> +1250e

150

-

ns

Decoder Reset Setup
Time

TORS

vee

=4.5 and 5.5V

9,10,11

-550 e :S.TA.5 +1250e

75

-

ns

Decoder Reset Hold
Time

TORH

vee

=4.5 and 5.5V

9,10,11

-550e:S.TA:S.+1250e

75

-

ns

150

ns

ns
ns

ns
ns

DECODER TIMING
Decoder Clock
Frequency

-

Master Reset Pulse

TMR

vee

-550 e !> TA !> + 1250 e

TDl

vee

=4.5 and 5.5V
=4.5 and 5.5V

9,10,11

Bipolar Data Pulse
Width

9,10,11

-550 e !> TA !> + 1250 e TDe+10
(Note 1)

One Zero Overlap

TD3

vee

=4.5 and 5.5V

9,10,11

-550e:S.TA:S.+1250e

-

TDe-l0
(Note 1)

ns

vce

9,10,11

-550e.5TA:s' +1250 e

-20

110

ns

vee

9,10,11

-550 e !> TA .5 +1250e

a

110

ns

9,10,11

-550 e:S.TA:S.+1250e

-

SO

ns

9,10,11

-550 e:S.TA:S.+1250e

110

ns

9,10,11

-550e.5TA:s' +1250 e

110

ns

9,10,11

-550eSTA.5+1250e

9,10,11

-550C !>TA:S. +1250e

a
a
a
-

9,10,11

-550 e:S.TA.5 +125 0e

75

Sync Delay (ON)

TD6

Take Data Delay (ON)

TD7

Serial Data Out Delay

TDS

Sync Delay (OFF)

T09

Take Data Delay (OFF)

TD10

Valid Word Delay

TOll

Sync Clock to ShiH
Clock Delay

TD12

=4.5 and 5.5V
=4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V
vee =4.5 and 5.5V

Sync Data Setup

TD13

vee

=4.5 and 5.5V

ns
ns

110

ns

75

ns

-

ns

NOTES: 1. TDC = Decoder clock period = l/FDC
2. A.C. Tesling as follows: Inpull..els: VIH
load: CL = 50pF

a

70% VCC, VIL = 20% VCC; Inpul rise/faillimes driven all nsN: Timing referencel..el.: VCC/2; Output

CAUTION: These devices are sensitive 10 electrostatic discharge. Proper I.C. handling procedures should be followed.

6-59

Specifications HD-15531/883
TABLE 3. HD-15531/BB3 ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

CONDITiONS

NOTES

. TEMPERATURE

MIN

MAX

UNITS

CI

VCC = OPEN, f = 1 MHz,
All Measurements
Referenced to Device GND

1

TA=+250 C

-

25

pF

CIO

VCC = OPEN, f = 1 MHz,
All Measurements
Referenced to Device GNO

1

TA=+250 C'

-

25

pF

1,2

-550 C .$.TA.$. +250 C

-

10

rnA

Input Capacitance

InpuVOutput
Capacitance

Operating Power
Supply Current

ICCOP

VCC = 5.5V, f = 1 MHz

NOTES: 1. The parameters listed in table 3 are controlled via design or process parameters are characterized upon initial design and after major process
and/or design changes.
2. Guaranteed but not 100'11> lested.

TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS

METHOD

SUBGROUPS

100'1&/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3, BA, BB, 10, 11

Group A

Samples/5005

1,2;3, 7,BA,BB,9, 10, 11

GroupsC&D

Samples/5005

1,7,9

Initial Test

CAUTION: These devices are sensKive

to electrostatic discharge. Proper I.C. handling' procedures should be followed.

6-60

Specifications HD-155318/883
Absolute Maximum Ratings

Reliability Information

Supply Voltage •••••••••••••••••••.•••••.•••••••••••••• +7.0V
Input, Output or I/O Voltage Applied. . • •• GND-O.SV to VCC+O.SV
Storage Temperature Range •••••••••••••••.• -6So C to +1S00 C
Junction Temperature •••.••••••...••...••••••.••••••• +17So C
Lead Temperature (Soldering 10 sec) ••••.•••••••••••••• +3000 C
ESD Classification ••••••.••••.••.•.•••••.••••••••••••• Class 1

Thermal Resistance
Sja
°jc
Ceramic DIP Package. . . • • • • • • . . • • • 34.80C/W
7.9 0C/W
0
Maximum Package Power Dissipation at +12S C
Ceramic DIP Package •••••••••••••.•••••••••••••••••• 1.44W
Gate Count ••••••••••.••••••••.•••••.••••••••••••. 2S0 Gates

CAUTION: Stresses above those listed in '~bsolute Maximum Ratings" may cause permanent damage to the devicB. This ;s a stress only rating and operation
of the del/ice at these or any other conditions above those indicated in the operational sections of this specification ;s not implied.

Operating Conditions
Supply Voltage •••••••••.•••••••••••••••.••.••• +4.5V to +5.5V
Ambient Operating Temperature Range (lAI ... -550C to +1250 C
Encoder/Decoder Clock Rise Time (lECR, TDCR) ••••••• 8ns Max
Encoder/Decoder Clock Fall Time (lECF, TDCFl ••••••••• 8ns Max

Sync Transition Span (lD2) •••••••••••••• 18 TDC Typical (Note1)
Short Data Transition Span (lD4) ••••••.•• 6 TOC Typical (Note1)
Long Data Transition Span (lOS) •.•••••.•• 12 TDC Typical (Note1)

TABLE 1. HD-15531B/883 D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

CONDITIONS

UMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

-

0.2VCC

V

Input LOW Voltage

VIL

VCC = 4.5Vand 5.5V

1,2,3

-5S0 C.!>TA.!> +1250C

Input HIGH Voltage

VIH

VCC = 4.5Vand 5.5V

1,2,3

-55 0C.!>TA.!> +1250C 0.7VCC

Input LOW Clock
Voltage

VILC

VCC = 4.5V and 5.5V

1,2,3

-550C~TA.!>+1250C

Input HIGH Clock
Voltage

VIHC

VCC = 4.5V and 5.5V

1,2,3

-550C ~TA ~ +1250C VCC-0.5

Oulput LOW Voltage

VOL

IOL = 1.8mA (Note 2)
VCC=4.5V

1,2,3

-550CSTA::5 +12SoC

Output HIGH Voltage

VOH

10H = -3mA (Note 2)
VCC=4.5V

1,2,3

Input Leakage Current

II

VI = GND or VCC
VCC=5.5V

ICesB

VIN = VCC = 5.5V
OulputOpen

Standby Supply
Current
Function Test

FT

(Note 3)

-

V

GND+0.5

V

-

V

-

0.4

V

-550 CSTA.!>+1250C

2.4

-

V

1,2,3

-550C .!>TA.!> +1250C

-1.0

+1.0

!IA

1,2,3

-550C.!>TA~+1250C

-

2

rnA

7,8

-550C ~TA.!> +1250C

-

-

-

NOTES: 1. TDC - Decoder clock period - l/FDC
2. Interchanging of force and sense conditions Is permitted.
3. Tested as follows: f - 15MHz, VIH

D

70'11> VCC, V1L - 20'1& VCC, CL - 50pF. VOH

~

VCC/2 and VOL.:: VCC/2.

CAUTION: These deviceS are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed •

.6-61

Specifications HD-15531 8/883
TABLE 2. HD-15531B/883 A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Guaranteed and 100% Tested

PARAMETER

SYMBOL

(NOTE 2)
CONDITIONS

LIMITS

GROUP A
SUBGROUPS

TEMPERATURE

MIN

MAX

UNITS

ENCODER TIMING
Encoder Clock
Frequency

FEe

vee

= 4.5V and 5.5V

9,10,11

-550C ~TA~ +1250 e

-

30

MHz

FEse

vee

= 4.5V and 5.5V

9,10,11

-550e.s TA.s +1250 e

MHz

FED

vee = 4.5V and 5.5V

9,10,11

-550C .sTA~ +125 0 e

-

5.0

Encoder Data Rate

2.5

MHz

Master Reset Pulse
Width

TMR

vee = 4.5V and 5.5V

9,10,11

-55°C ~TA:'O +125 0 e

150

-

ns

Shift Clock Delay

TE1

vee = 4.5V and 5.5V

9,10,11

-550C .sTA~ +125 0 e

-

80

ns

Serial Data Setup

TE2

vee = 4.5V and 5.5V

9,10,11

-550e.sTA~ +125 0 e

50

ns

Serial Data Hold

TE3

9,10,11

-550C ~TA~ +125 0 e

50

Enable Setup

TE4

9,10,11

-55°C .s TA .s + 125°C

90

-

Enable Pulse Width

TE5

9,10,11

-550e.sTA~

100

-

ns

Sync Setup

TE6

9,10,11

-550e.s TA .s + 125°C

55

ns

9,10,11

-550 e,.sTA.s +125 0 e

150

-

9,10,11

-55 0 e,.sTA.s +1250 e

ns

9,10,11

-550e:'OTA,.s+1250e

°-

50

9,10,11

-550 e,.sTA,.s +125 0 e

10

9,10,11

-550 e,.sTA ~ +125 0 e

Send Clock Frequency

Enable Hold

TE10

Sync Hold

TE11

= 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V

FDe

vee = 4.5V and 5.5V

9,10,11

-550 e,.sTA":;' +125 0 e

-

30

MHz

Decoder Sync Clock

FDS

vee = 4.5V and 5.5V

9,10,11

-550e,.sTA~

+1250 e

MHz

FDD

vee

9,10,11

-550e,.sTA~+1250e

2.5

MHz

Decoder Reset Pulse
Width

TOR

= 4.5V and 5.5V
vee = 4.5V and 5.5V

-

5.0

Decoder Data Rate

9,10,11

-55 0 e,.sTA":;' +1250 e

150

-

ns

= 4.5V and 5.5V

9,10,11

-550 e,.sTA:'O +1250 e

75

-

ns

Sync Pulse Width

TE7

Send Data Delay

TE8

Bipolar Output Delay

TE9

vee

+125 0 e

ns
ns

ns

130

ns
ns

95

-

ns

DECODER TIMING
Decoder Clock
Frequency

Decoder Reset Setup
Time

TDRS'

vee

Decoder Reset Hold
Time

TORH

vee = 4.5V and 5.5V .

9,10,11

-55 0 e,.s TA.s +125 0 e

75

-

ns

Master Reset Pulse

TMR

vee

9,10,11

-P50e.s TA.s +1250 e

150

-

ns

Bipolar Data Pulse
Width

TD1

= 4.5V and 5.5V
vee = 4.5V and 5.5V

9,10,11

-550C ":;'TA.s +1250 e TDe+10
(Note 1)

-

ns

One Zero Overlap

T03

vee = 4.5V and 5.5V

9,10,11

-550e.sTA~ +1250 e

-

TDe-10
(Note 1)

ns

-20

110

ns
ns

Sync Delay (ON)

TD6

vee

-550 e.sTA":;' +125 0 e

TD7

vee

9,10,11

-55°C .s TA .s + 125°C

T08

9,10,11

-550C ~ TA ~ +125 0 e

°-

110

Serial Data Out Delay

80

ns

Sync Delay (OFF)

T09

9,10,11

-55 0 e,.sTA,.s +1250 e

0

110

ns

Take Data Delay (OFF)

TD10

9,10,11

-550 e,.sTA.s +125 0 e

ns

TD11

9,10,11

-550e,.sTA~+1250e

110

ns

Sync Clock to Shift
Clock Delay

TD12

9,10,11

-55 0 e,.sTA,.s+1250e

°
°-

110

Valid Word Delay

= 4.5V and 5.5V
= 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V
vee = 4.5V and 5.5V

9,10,11

Take Data Delay (ON)

75

ns

Sync Data Setup

TD13

vee = 4.5V and 5.5V

9,10,11

-550e,.sTA~+1250e

75

-

ns

NOTES: 1. TOC = Decoder Clock Period

= 1/FDC

2. A.C. Testing as follows: Input levels: VIH = 70% vee, VIL = 20% vee; Input rise/faillimes driven at 1 nsN; Timing reference levels: VCC/2; Output
load: CL = SOpF
CAUTION: These devices are sensitive to electrostatic fdischarge. Proper

Ie

handling procedures should be followed.

6-62

-

Specifications HD-155318/883
TABLE 3. HD-15531B/883 ELECTRICAL PERFORMANCE CHARACTERISTICS'
LIMITS
PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

CI

VCC = OPEN, f = 1 MHz,
All Measurements
Referenced to Device GND

1

TA=+250 C

-

25

pF

vec = OPEN, f = 1 MHz,

1

TA=+250 C

-

25

pF

1,2

-550 C;S TA ~ +25 0 C

-

10

mA

Input Capacitance

Input/Output
Capacitance

Operating Power
Supply Current

CIO

All Measurements
Referenced to Device GND
ICCOP

VCC = 5.5V, f = 1 MHz

NOTES: 1. The parameters listed in table 3 are controlled via design or process parameters are-characterized upon inilial design and after major process
and/or design changes.
2. Guarenteed but not 100% tested.

TABLE 4. APPLICABLE SUBGROUPS'.
CONFORMANCE GROUPS

METHOD

SUBGROUPS·

Initial Test

100%/5004

-

Interim Test

100%/5004

1,7,9

PDA

100%/5004

1

Final Test

100%/5004

2,3,8A,88,10,ll

Group A

Samples/5005

1,2,3,7, 8A, 88,9; 10, 11

GroupsC&D

Samples/5005

1,7,9

Test Load Circuit
DUT~

~·t
"Includes Stray and Jig Capacitance

CAUTION: These devices are sensitive to electrostalic discharge. Proper I.C. handling procedures should be followed.

6-63

HD-15531/883
Timing Waveforms
ENCODER TIMING

,

---.l
I

SEND CLOCK

ENCODER SHIFT CLOCK

I

I
I--TEI

L

I

~i-:-TETE";;E;';333------'~

SERIALOATAIN~

--.-J

SEND CLOCK

---j

~

ENCODER SHIFT CLOCK
ENCODER ENABLE

I

I

=-l
\--TE10
I
--l TE' t--

I--TEI

I
--I I I-

~-----------!:TE5
~6-1

SYNCSELECT

L
TE11

I
_~ALlO ~
TE7=j

ENCODER SHIFT CLOCK
TES---/

SEND DATA

F---------L

I
---lb

SEND CLOCK

.T...;E;;::9e--_ _ _ _..., , . . - - - - -

X

BIPO~ARONEOUTor ~-------~~
BIPOLAR ZERO OUT - - - " - - - - - - - - - '

'------

, DECODER TIMING

I------- Bn PERIOD

NOTE: UNIPOLAR IN
•

1•

BIPOLAR ONE IN . F T 0 1 = e / / f f i ' l Z / / / / / / / / / / / / / / / I
1•
T02
•
BIPOLAR ZERO IN

_t-_______T

=0, FOR NEXT DIAGRAMS

BIT PERIOD

IJ:o- T03

•

!.

BIT PERIOO----j

I

i-I- - -

-I I-- T03

___,P:;r~O:.::I:t~~~h~~~~~~~~~~~~
~~~0~0~0~0~0~/h~~~~~~~~~~~0~~~%l......__
I·
T02
'1

COMMAND SYNC

BIPOLAR ONE IN
BIPOLAR ZERO IN

i
:
tt:0l~///H/////~
I·
T 0 2 , ' I--T03
' ;
I-T03
J=T0 1 = v l ' / / f f / / / / ; ' l / / / / / / f f//4
i
1
:

:

I•

~OI:w/b:

--II-T03

~ I-T03

•

"

~;rOl:WU///////7~

~ r--TD3'

,W//////////K

BIPOLAR ZERO IN

t--- T04

T02

•

I•

I

,

I

BIPOLAR ONE IN

i

DATA SYNC

,

ToS

ONE

•

1•

ZERO

i

TOS

•

r--

I.-T03
~T03
~T01:Vff);
1•
T04-----l

ONE

NOTE: BI,,?LAR ONE IN· 0; BIPOLAR ZERO IN· I, FOR NEXT DIAGRAMS.
UNIPOLAR IN

::Jj:;:"======TTiO;;2;-=~'====::..=lI~.====~=.!!TO!!;2!.======~..~V;;~~2:~2:~2~2~2~2~~L
I

COMMAND SYNC

:

UNIPOLARIN:::Jl::·============!T~02t===~======~'~I~';=======~==1T~022===========~'~e?~~~~~~2:~2~2~2~2~
:

DATASVNC:

UNIPOLARIN~F:;:=TT~04;:::'ll='======~T~~~S~====~.~IF.;:::::=TTO~5~::::::~.~I=·~2T~04~==.~!:.:::TT04~=~~
:

ONE

ZERO

6-64

ONE:

ONE

HD-75537/883
Timing Waveforms

(Continued)

DECODER TIMING (Continued)

DECODER SHIFT CLOCK - - - ,

TD61~~r--------------J

-:::::-::--:-i-...JI. _____________________ _

COMMAND/DATA SYNC

TD71

TAKE DATA

----,

DECODER SHIFT CLOCK

TDB"""
SERIAL DATA OUT

---,

DECODER SHIFT CLOCK

TD9 ......

I---

I

L..

r-==

>C

DATA BIT

L..

1===

I
i'D'iii=l I--I

COMMAND/DATA SYNC
TAKE DATA
VALID WORD

TDll--J

--,

DECODER SHIFT CLOCK

TDRS---I

f==

I

L-

I--

:-=fToiil=-=-

DECODER RESET

-j

I-TDRH

SYNCHRONOUS INPUT (WITH EXTERNAL BIT SVNCHRONIZATION)
SYNCHRONOUS
CLOCK IN

--==i TD12 I--- '--------'

-:-JL-___________--'

DECODE'::~~~: _ _ _ _

SYNCHRONOUS
CLOCK IN

----l

SVNCHRONOUS::::X~-~~----DATA IN

•

' - _ _ _ _ _ _J

6-65

'-_______

HD-15531/883
Burn-In Circuit
HD1-15531/883 CERAMIC DIP

R

vce

R
A
A
R'
A
A

vee
GND
vee
FO

GND

R
R

A

FO

GND
A

R
R

A

R

R

R

vee

A

Ne

R

R

GND

vee
vee

R

R

R

R

vee
GND
vee
GND
vee

Ne
A

GND
GND
vee

R

R

R

R

R

R

vee

~A

R

GND

NOTES:
vee = 5.5V :!: O.5V
VIH = 4.5V :!: 10'lf>
VIL = -O.2V to +O.4V
R=47kn:!:5'lf>
FO = 100kHz:!: 10'lf>

6-66

A

vee
GND
GND

HD-15531/883

Metallization Topology
. DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP'-" 460 0 C (Max)

DIE DIMENSIONS:
155 x 195 x 19 ± 1 mils
METALLIZATION:
Type: Si-AI
Thickness: 11 kA

' .

WORST CASE CURRENT DENSITY:
2.0 x 10 5A/cm 2

± 2kA

GLASSIVATION:
Type: Si02
Thickness: akA ± 1kA

Metallization Mask Layout
HD-15531/883

TAKE DATA'

COUNT C4

ENCODER CLK

TAKE DATA
SERIAL DATA OUT

ENCODER SHIFT CLK

SEND DATA

DECODER SHIFT CLK

COMMAND SYNC

6-67

HD~ 15531/883

Packaging t
40 PIN CERAMIC DIP
2.035

.:ill.
.180

J

.098 MAX

.~OO
SC

.016·
.023

.050·
.065

LEAD MATERIAL: Type B
LEAD FINISH: Type A
PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:
Material: Glass Frit
Temperature: 450 0 C ± 100 C
. Method: Furnace Seal

NOTE: All Dimensions are

.!:!!!!...
, Dimensions are in Inches.
Max

• INCREASE MAX UMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FlNISH

INTERNAL LEAD WIRE:
Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510 0-5

tMiI-M-38S10 Compliant Materials, Finishes. and Dimensions.

m

HD-15531

HARRIS

DESIGN INFORMATION
CMOS Manchester Encoder-Decoder
The information contained in this section has been developed through characterization by Harris Semiconductor and is for
use as application and design information only. No guarantee is implied.

Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by
dividing the DECODER CLOCK. The frame length is set
by programming the COUNT inputs. Parity is selected by
programming ENCODER PARITY SELECT high for odd
parity or low for even parity.
The Encoder's cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK -

c~

",-

Failure Rate Primer .................................................................... .

7-14

Failure Rate Calculations .............................................................. .

7-14

Acceleration Factors ..........................................•..•.....................

7-15

Activation Energy ................................................................•.....

7-15

Qualification Procedures .............................................................. .

7-16

7-1

--'

W
a: a:
a:
<011

:z:

, - - - - - - - - Harris Quality & Reliability - - - - - - - - - - ,
Introduction
Success in the integrated circuit industry means anticipating and accepting the challenges of the future.
Success results from a process of continuing
improvement and evolution, with perfection as the
constant goal.

Quality organization's role is changing from policing
quality to leadership and coordination of quality programs or procedures in other organizations - through
auditing, sampling, consulting, and managing Quality
Improvement projects.

Harris Semiconductor's commitment to supply only
top value integrated circuits has made quality improvement a mandate for every person in our work
force - from circuit designer to manufacturing operator, from hourly employee to corporate executive.
Price is no longer the only determinant in marketplace
competition. Quality, reliability, and performance
enjoy significantly increased importance as measures
of value in integrated circuits.

To support speCific market requirements, or to ensure
conformance to military or customer specifications,
the Quality organization still performs many of the
conventional quality functions (e.g., group testing for
military products or wafer lot acceptance). But, true to
the philosophy that quality is everyone's job, much of
the traditional on-line measurement and control of
quality characteristics is where it belongs - with the
people who make the product. The Quality organization is there to provide leadership and assistance in
the deployment of quality techniques, and to monitor
progress. (See Figure 3 and Table 4.)

Quality in integrated circuits cannot be added on or
considered after the fact. It begins with the development of capable process technology and product
design. It continues in manufacturing, through effective controls at each process or step. It culminates in
the delivery of products which meet or exceed the expectations of the customer.

The Role of the Quality Organization
The emphasis on building quality into the design and
manufacturing processes of a product has resulted in
a significant refocus of the role of the Quality organization. This group facilitates the development of
Statistical Process Control (SPC) and Design of
Experiments (DOX) programs and works with manufacturing to establish control charts. In addition, Quality professionals are involved in the measurement of
equipment capability, standardization of inspection
equipment and processes, procedures for chemical
controls, analysis of inspection data and feedback to
the manufacturing areas, coordination of efforts for
process and product improvement, optimization of
environmental or raw materials quality, and the
development of quality improvement programs with
vendors.
"Total Quality" at Harris requires ownership and
responsibility by each. person at every level of the
organization. At critical manufacturing operations,
process and product quality is analyzed through random statistical sampling and product monitors. The

The Improvement Process

I

STAGE IV

I

jl

PRODUCT
OPTIMIZATION

IMPACTON
PRO DUCT
QU ALITY

STAGE III
PROCESS
OPTIMIZATION
STAGE II
PROCESS
CONTROL

STAGE I
PRODUCT
SCREENING
SOPHISTICATION OF
QUALITY TECHNOLOGY

FIGURE 1. STAGES OF STATISTICAL QUALITY TECHNOLOGY

Harris Semiconductor's quality methodology is evolving through the stages shown in Figure 1. In 1981 we
embarked on a program to move beyond Stage I, and
we are currently in the transition from Stage II to Stage
III, as more and more of our people become involved in
quality activities. The traditional "quality" tasks of
screening, inspection, and testing are being replaced
by more effective' and efficient methods, putting' new
tools into the hands of all ernployees. Table 1 illustrates
how our quality systems'are changing to meet today's
needs.

7-3

!;:~
....
-

cc ....
::>aID

~:§
W
a:
a: a:

CCoil

:c

TABLE 1.
AREA

"

X
X

JAN,Self-Audit
Temperature/Humidity
ESD Controls
Temperature Test Calibration
Test System Calibration
Test Procedures
Control Unit Compliance
Lot Acceptsnce Conformance
Group A Lot Acceptsnce

•
•
•
•
•

JAN Self-Audit
Wafer Repest Correlation
Visual Requirements
Documentstion
Process Performance

X
X
X

X
X
'X
X
X

X
X,'
X
X

X
X
X
X

X

X
X

X
X

X
X
X
X

X

• JAN Self-Audit
• Envlronmentsl
- Room/Hood Particulates
- Temperature/Humidity
- Waler Quality
• Product
- Documentstion Check
- Dice Inspection
- Wire Bond Pull Strength/Controls
- Die Sear Controls
- Pre-Seal Visual
- Fine/Gross Leak
- PINDTest
- Lead finish Visuals, Thickness
- Die Shear
- Solderability
• Process
- Operator Quality Performance
- Saw Controls
- Die Attach Temperatures
- Seal Parameters
- Seal Temperature Profile
- Sta-Bake Profile
- Temp Cycle Chamber Temperature
- ESD Protsctlon
- Plating Bath Controls
- Mold Parameters
•
•
•
•
•
•
•
•
•

QA/QC MONITOR
AUDIT
X

• JAN Self-Audit
• Environmenlal
- Room/Hood Particulates
- Temperature/Humidity
- Water Quality'
• Product
- Junction Depth '
- Sheet Resistivities
- Defee! Density
- Critical Dimensions
- Visual Inspection
- Lot Acceptsnce
• Process
- Film Thickness
- Implant Dosages
- Capacitsnce Voltsge Changes
- Conformance to Specification
• Equipment
, - Repeatsbility
- Profiles
- Calibration
- Preventive Maintenance

Assembly

Probe

MANUFACTURING
CONTROLS

FUNCTION

WaferFab

Test

TYPICAL ON-LINE MANUFACTURING/QUALITY FUNCTIONS

X

X
X
X

X
X

X
X
X
X
X
X

X
X
X
X
X
X

X
X
X

"

X
X
X
X
X
X
X
X
X
X

X
X

X
X
X
X
','

X
X
X
X

X
X,

X
X
X
X
X
X
X
X
X

7-4

X
X
X

TABLE 1. TYPICAL ON-LINE MANUFACTURING/QUALITY FUNCTIONS (CONTINUED)

AREA
Bum-In

Brand

QCllnspection

MANUFACTURING
CONTROLS

FUNCTION

QAtQC MONITOR
AUDIT
X

•
•
•
•

JAN Self-Audit
Functionality Board Check
Oven Temperature Controls
Procedural Conformance

X
X

•
•
•
•
•

JAN Self-Audit
ESD Controls
Brand Permanency
Temperature/Humidity
Procedural Conformance

X
X
X

X
X
X
X
X
X
X
X
X

• JAN Self-Audit
• Group B Conformance
• Group C and D Conformance

Designing for Manufacturability

TABLE 2. APPROACH AND IMPACT OF STATISTICAL
QUALITY TECHNOLOGY

Assuring quality and reliability in integrated circuits
begins with good product and process design. This
has always been a strength in Harris Semiconductor's
quality approach. We have a very long lineage of high
reliability, high performance products that have
resulted from our commitment to design excellence.
All Harris products are designed to meet the stringent
quality and reliability requirements of the most
demanding end equipment applications, from military
and space to industrial and telecommunications. The
application of new tools and methods has allowed us
to continuously upgrade the design process.
Each new design is evaluated throughout the
development cycle to validate the capability of the
new product to meet the end market performance,
quality, and reliability objectives.
The validation process has four major components:
1. Design simulation/optimization
2. Layout verification
3. Product demonstration
4. Reliability assessment.
Harris designers have an extensive set of very
powerful Computer-Aided Design (CAD) tools to
create and optimize product designs (see Table 2).

STAGE
I

Product
Screening

(I

APPROACH

IMPACT

• Stress and Test
• Defective Prediction

• Limited Quality
• Costly
• Afler-The-Fact

Process
Control

• Statistical Process
Control
• Just-In-Time
Manufacturing

• Identifies Variability
• Reduces Costs
• RealTime

III

Process
Optimization

• DeSign of Experiments
• Process Simulation

• Minimizes Variability
• Before-The-Fact

IV

Product
Optimization

• Design for Producibility
• Product Simulation

• Insensitive to Variability
• Designed-In Quality
• Optimal Results

Special Testing
Harris Semiconductor offers several standard
screening flows to support a customer's need for
additional testing and reliability assurance. These flows
include environmental stress testing, burn-in, and
electrical testing at temperatures other than +250 C.
The flows shown on page 7-6 and 7-7 indicate the
Harris standard screening processes. In addition,
Harris can supply products tested to customer
speCification both for electrical requirements and for
non-standard environmental stress screening. Consult
your field sales representative for details.

7-5

Harris Semiconductor Standard Processing Flows
SMD

883
JAN CLASS B

PROBE/DICE
PREPARATION

HIGH/ROOM
TEMP
PROBE TEST

VISUAL
INSPECTION
PER
MIL-STD-883
METHOD 2010
CONDITION B
WITHQC
MONITOR

ASSEMBLY (1)

o

DIE ATTACH
CONTROL

WIRE BOND
CONTROL

*

OPERATION
QAMONITOR
LEAD FRAME CLEAN

YES

DIE AND FRAME ATTACH
CONTROL

YES

QA DIE ATTACH
f::ONTROL (SPC)

2-HOUR

*

WIRE BOND
PRE-SEAL
WASH IN
LAMINAR
FLOW

*

QA WIRE BOND
CONTROL

PRE-SEAL CLEAN
PRE-SEAL INSPECT

YES
2-HOUR
YES
PER
MIL-STD~883

PRE-SEAL
VISUAL
INSPECTION
IN CLASS 100
LAMINAR
FLOW

METHOD 2010
CONDITION B

*

QA PRE-SEAL INSPECT
GSI

YES
YES

CERDIP SEALING

YES

SEAL CONTROL

YES

TEMPERATURE CYCLE

YES

CENTRIFUGE

YES

TIN-PLATING

YES

*

PARTICLE
IMPACT NOISE
DETECTION
(PIND)
AS
REQUIRED

GSIINSPECTION

QA TIN-PLATING
INSPECT

YES

FINE LEAK TEST

YES

GROSS LEAK TEST

YES

PINDTEST

b

FRAME REMOVAL

AS
APPLICABLE
YES

LOAD SHIPPING TUBES

YES

QA FINAL INSPECT

YES

QA DOCUMENTATION
INSPECT

YES

*
*

(1) Example for a Cerdip Package Part

7-6

Harris Semiconductor Standard Processing Flows
(Continued)

SMD

883
JAN CLASS B

TEST (2)
0

*
AC/DC SINGLE
INSERTION TEST
CAPABILITY;
HIGH/LOW TEMP

OPERATION
QAMONITOR

ELECTRICAL TEST SORTING
OPERATION

-

SERIALIZE

YES

IF
APPLICABLE

BURN-IN
'-

QUALITY
CONFORMANCE
GROUPS A, B, C,
ANDDAS
REQUIRED

-

PRE BURN-IN ELECTRICAL
TEST
BURN-IN (3)

-

POST BURN-IN TEST

1-*
DELTAS PER
SLASH SHEET
REQUIREMENT
IF APPLICABLE

IN-HOUSE
MASS
SPEC
CAPABILITY

COMPUTERIZED
LOT
TRACEABILITY
MONITORING
SYSTEM

APPLY BURN-IN PDA
(AS APPLICABLE)

-

-

-

ALTERNATE GROUP A

YES

160-HOUR@
+125 0 C, OR
PER
SLASH SHEET
YES
YES
YES

SOLDERDIP

YES

FINE LEAK TEST

YES

GROSS LEAK TEST

YES

BRAND

YES

EXTERNAL VISUAL

YES

-*

QUALITY
CONFORMANCE
INSPECTION

FINAL DATA REVIEW

GROUPA, B,
C,D

~~

-

-'
"",-,

"'o~
YES

~~

a: a:

"",01:1

:I:

PACKAGE & SHIP
OR STOCK

(2) -55 0 C TO +125 0 C
(3) Burn-In test temperatures can be increased and time reduced per regression tables in Mil-Std-883, Method 1015.

7-7

TABLE 3. SUMMARIZING CONTROL APPLICATIONS
FAB
• Measurement Equipment
- Critical Dimension
- Film Thickness
- 4 Point Probe
- Ellipsometer

• Photo Resist
- Critical Dimension
- Resist Thickness
- Etch Rates

• Diffusion
- Junction Depth
- Sheet Resistivities
- Oxide Thickness
- Implant Dose Calibration
- Uniformity

• Thin Film
- Film Thickness
- Uniformity
- Refractive Index
- Film Composition

• Pre-Seal
- Die Prep Visuals
- Yields
- Die Attach Heater Block
- Ole Shear
- WirePuli
- Saw Blade Wear
- Pre-Cap Visuals

• Post-Seal
- Internal Package Moisture
- Tin Plate Thickness
- PINDDefectRate
- Solder Thickness
- LeakTests
- Module Rm. Solder Pot Temp.
- Seal
- Temperature Cycle

ASSEMBLY
• Measurement
-XRF
- Radiation Counter
- Thermocouples
- GM-Force Measurement

TEST
-

Handlers/Test Systems
Defect Pareto Charts
Lot % Defective
ESD Failures per Month

- Monitor Failures
- Lead Strengthening Quality
- After Burn-In PDA
OTHER

• IQC
- Vendor Performance
- Material Criteria
- Quality Levels

• IQC MeasuremenVAnalysls
-XRF
-ADE
- 4 Point Probe
- Chemical Analysis Equipment

• Environment
- Waler Quality
- Clean Room Control

Controlling and Improving the
Manufacturing Process - SPC/DOX
Statistical process control (SPC) is the basis for quality
control and improvement at Harris Semiconductor.
Harris manufacturing people use over 1,000 Shewhart
control charts to determine the normal variabilities in
processes, materials, and products. Critical process
variables are measured and control limits are plotted on
the control charts. Appropriate action is taken if the
charts show that an operation is outside the process
control limits or indicates a trend toward the limit.
These same control charts are powerful tools for use in
reducing variations in processing, materials, and products. Table 3 lists some typical manufacturing applications of control charts at Harris Semiconductor.

screening are limited in their ability to reduce product
defects to the levels expected by today's buyers. In addition, screening and inspection have an associated
expense, which raises product cost.
Harris engineers are, instead, using Design of Experiments (DOX), a scientifically diSCiplined mechanism for
evaluating and implementing improvements in product
processes, materials, equipment, and facilities. These
improvements are aimed at reducing the number of defects by studying the key variables controlling the process, and optimizing the procedures or design to yield
TABLE 4. HARRIS I.C. DESIGN TOOLS
PRODUCTS
DESIGN STEP

DIGITAL

ANALOG

SPC is important, but still considered only part of the
solution. Processes which operate in statistical control
are not always capable of meeting engineering
requirements. The conventional way of dealing with this
in the semiconductor industry has been to implement
100% screening or inspection steps to remove defects,
but these techniques are insufficient to meet today's
demands for the highest reliability and perfect quality
performance.

Functional
Simulation

Slice

Silos
Proteous
Socrates

Parametric
Simulation

Slice
Monte Carlo

Slice

Schematic
Capture

Note 1

Daisy
SDA-Mass Comp

Functional
Checking

Note 1

SDA-LVS

Harris still uses screening and inspection to "grade"
products and to satisfy specific customer requirements
for bum-in, multiple temperature test insertions,
environmental screening, and visual inspection as value-added testing options. However, inspection and

Rules
Checking

Calma-DRC

Harris Dash

Parasitic
Extraction

Note 1

SDA-LVS

NOTE 1. Tools are in Development.

7-8

the best result. This approach is a more time-consuming method of achieving quality perfection, but a
better product results from the efforts, and the basic
causes of product nonconformance can be eliminated.
SPC, DOX, and design for manufacturability, coupled
with our 100% test flows, combine in a product assurance program that delivers the quality and reliability
performance demanded for today and for the future.

Average Outgoing Ouality (ADO)
Average Outgoing Quality is a yardstick for our
success in quality manufacturing. The average outgoing electrical defective is determined by randomly
sampling units from each lot and is measured in parts
per million (PPM). The current procedures and sampling plans outlined in MIL-STD-883 and MIL-M38510

\

IIXI
7110

I'm
- ....

§...,

AOQ has decreased from 1,000 PPM to less than 100
PPM, and the goal is to continue improvement toward
o PPM.
Training
The basis of a successful transition from conventional
quality programs to more effective, total involvement
is training. Extensive training of personnel involved in
product manufacturing began in 1984 at Harris, with
a comprehensive development program in statistical
methods. Using the resources of the University of
Tennessee, private consultants, and internally developed programs. Training of over 2,000 engineers,
supervisors, and operators/technicians has been
completed.
Nearly 1,000 operators, 100 supervisors, and more
than 800 engineers have been trained in SPC methods, providing them with tools to improve the overall
level of uniformity of Harris products. Almost 300
engineers have received training in DOX methods:
learning to evaluate changes in process operations,
set up new processes, select or accept new equipment, evaluate materials, select vendors, compare
two or more pieces of equipment, and compare two or
more process techniques.

lOCO

IlOO

are used by our quality inspectors. The focus on this
quality parameter has resulted in a continuous
improvement over the past three years.

3QO

200
100
Q

01

Q2

Q3

FY88

Q4

01

Q2

Q3

Q4

01

FY87

Q3
02
FY88

Q4

FIGURE 2. DEFECTIVE PARTS PER MILLION

Over the past four years, Harris has also deployed a
comprehensive training program for hourly operators
and supervisors in job requirements and functional
skills. All hourly manufacturing employees participate
(see Table 5).

TABLE 5. SUMMARY OF TRAINING PROGRAMS
COURSE

AUDIENCE

LENGTH

TOPICS COVERED

SPC

Manufacturing Operators

8 Hours

Basic Philosophy, Statistical Calculations
Graphing Techniques. Pareto Charts. Control Charts

SPC

ManufactUring Supervisors

21 Hours

Basic Philosophy, Statistical Calculations
Graphing Techniques, Pareto Charts, Control Charts,
Testing for Inspector Agreement, Cause & Effect Diagrams,
1 & 2 Sample Methods

SPC

Engineers and Managers

48 Hours

Basic Philosophy, Graphical Methods, Control Charts,
Rational Subgrouping, Varianca Components, 1 & 2
Sample Methods, Pareto Charts, Cause & Effect Diagrams

DOX
(Design of
Experiments)

Engineers and Managers

88 Hours

Factorial Designs, Fractional Factorial Designs,
Blocking Designs, Variance Components,
Computer Usage, Normal Probability Plotting

RSM
(Response Surface
Methods)

Engineers and Managers

40 Hours

Steepest Ascent, Central Composite Designs,
Box-Behnken Designs, Computer Usage,
Contour Plotting, Second Order Response Surfaces

Continuous
Improvement
Methods

Manufacturing Supervisors

12 Hours

Basic Philosophy, Pareto Analysis, Imagineerlng,
Run Charts, Cause & Effect Diagrams, Histograms,
Ideas of Control Charts

SPCThe Essentials

Department-Level
WorkGroups

20 Hours

Basic Philosophy, of Continous Improvement, Imagineering
Pareto Charts, Cause & Effect Diagrams, Flow Charts,
Graphical Display, Control Charts, Ideas of Experiment

7-9

.

Incoming Materials.
Improving the quality and reducing the variability of
critical incoming materials is essential to product
quality enhancement, .yield improvement, and cost
control. With the use of statistical techniques, the
influence of silicon, chemicals, gases and other
materials on manufacturing is highly measurable.
Current measurements indicate that results are best
achieved when materials feeding a statistically controlled manufacturing line have also been produced
by statistically controlled vendor processes.
To assure optimum quality of all incoming materials,
Harris has initiated an 'a.ggressive program, linking
key suppliers with our manufacturing lines. This usersupplier network is the Harris Vendor Certification
process by which strategic vendors, who have performance histories of the highest quality, participate

with Harris in a lined network; the ven.dor's factory
acts as if it were a beginning of the Harris production
line. .
.
SPC seminars, development of open working relationships, understanding of Harris' manufacturing needs
and vendor capabilities, and continual improvement
programs are all part of the certification process. T~e
sole use of engineering limits no .longer is the only
quantitative requirement of incoming materials.
Specified requirements include centered means, statistical control limits, and the requirement that vendors deliver their products from their own statistically
evaluated, in-con'trol m~nufacturing processes.
In addition to the certification process, Harris has
worked to promote improved quality in the performance of all our qualified vendors who must meet
rigorous incoming inspection criteria (see Table 6).

TABLE 6. INCOMING QUALITY CONTROL MATERIAL QUALITY CONFORMANCE
MATERIAL
Silicon

Chemicals/Photoresists/
Gases

Thin Film Materials

INCOMING INSPECTIONS
•
•
•
•
•
•
•
•
•
•

• Equipment Capability Control Charts
- Oxygen
- Resistivity
• Control Charts Related to
- Enhanced Gettering
- Total Thickness Variation
- ToIallndicated Reading
- Particulates
• Certificate of Analysis for all CrHical Parameters
• Control Charts from On-Line Processing

Resistivity
Crystal Orientation
Dimensions
Edge Conditions
Taper
Thickness
Total Thickness Variation
Backside Criteria
Ol'ygen .
Carbon

• Certificate of Analysis on all Critical Parameters
• 'Control Charts from On-Line Processing
• Control Charts
- Assay
- Conteminants
- Water
- Selected Parameters
• Control Charts
-Assay'
- Ccintsmlnants
• Control' Charts on
- Photospeed
- Thickness
- UV Absorbance
- Filterability
- Water
- Contaminants

• Chemicals
- Assay
- Major Contaminants
• Molding Compounds
- Spiral Flow.
- Thermal Characteristics
• Gases
- Impurities
. • Photoreslsts
- Viscosity
- Film Thickness
- Solids
- Pinholes

• Assay

• Centrol Charts from On-Line Processing
• Control Charts
- Assay
- Contaminants
- Dimensional Characteristics
• Certificate of Analysis for all Critical Parameters

•
•
•
•
•
•
•
•
•
•
•

• Certificate 01 AnalYsis
• Process Control Charts on Outgoing Product
Checks and In-Line Process Controls

.. Selected Contaminants

Assembly Materials

VENDOR DATA REQUIREMENTS

Visuallnspeclion
Physical Dimension Checks
Lead Integrity
Glass ComposHlon
Bondabillty
Intermetallic Layer Adhesion
Ionic Contaminants
Thermal Charscteristlcs
Lead Coplanarity
Plating Thickness
Hermellclty

7-10

Manufacturing Science - CAM, JIT
In addition to SPC and DOX as key tools to control the
product and processes, Harris is deploying other
management mechanisms in the factory. On first
examination, these tools appear to be directed more
at schedules and capacity. However, they have a significant impact on quality results. .
Computer Aided Manufacturing (CAM)
CAM is a computer based inventory and productivity
management tool which allows personnel to quickly
identify production line problems and take corrective
action. In addition, CAM improves scheduling and
allows Harris to more quickly respond to changing
customer requirements and aids in managing work in
process (WIP) and inventories.
The use of CAM has resulted in significant improvements in many areas. Better wafer lot tracking has
facilitated a number of process improvements by correlating yields to process variables. In several places
CAM has greatly improved capacity utilization
through better planning and scheduling. Queues have
been reduced and cycle times have been shortened
- in some cases by as much as a factor of 2.
The most dramatic benefit has been the reduction of
WIP inventory levels, in one area by 500%. This results in fewer lots in the area and a resulting quality
improvement. In wafer fab, defect rates are lower because wafers spend less time in production areas
awaiting processing. Lower inventory also improves
morale and brings a more orderly flow to the area.
CAM facilitates all of these advantages.

Just In Time (JIT)
A key adjunct to the CAM activity is Just In Time (JIT)
material management. This is more than an inventory
reduction technique: in many cases it involves
reorganization of facilities and people. The essential
concept is to form work units that are responsible
or dOing the whole job rather than bits of it. An employee has control over equipment, maintenance,
cleanliness, scheduling, material, quality, and improvements.
In one Harris example, a photoresist flow consisting
of several steps was previously organized in the classical departmentalized way. The inspection and etch
areas were in different serial locations from the deposition and alignment areas. Work piled up at the
slowest operation (inspection), and quality problems
detected there were decoupled from the areas producing them by 20 to 30 feet and at least one day.
Rework rates were very high; scrap was
unacceptable.
When the area was reorganized into GT (group technology) cells (a basic concept of JIT), the inspection
and alignment areas were physically coupled and
people were organized into teams. The whole job (finished, defect-free wafers) was assigned to the GT cell
(see Figure 3). Rework rates decreased 70%, scrap
rates decreased 45%, and probe yields increased by
50%. This is only one of hundreds of examples of how
JIT has improved our factory performance.
The JIT program/system works. This cultural change
is vital and the benefits derived are impressive.
NO.2

NO.3
3 STEPPERS
3PE'S

PREINSPECT

DEY

o
o

9PE'S

COAT

c:::J
AUGN & STEP

c:::J 0

ENG

COAT

BEFORE

AFTER
FIGURE 3. GROUP TECHNOLOGY CELL

7-11

NO.1

Measurement
Analytical Services Laboratory
The Harris Analytical Laboratory is a company-wide
technical resource for the physical and chemical
characterization of microelectronic· materials and
products. Harris FaCilities, Engineering, Manufacturing, and Quality are supported by the laboratory. Organized as chemical or microbeam analysis
methodology, staff and instrumentation from both
areas cooperate in fully integrated approaches necessary to complete any analytical study.
The lab is widely staffed and equipped to provide all
manufacturing and operational functions with the
following:
• Real time materials and process analyses to support routine manufacturing and development.
• Cooperative planning of all analytical investigations.
• Development of new techniques and method refinements as necessary to support internal and
external customer requirements.
• Maintenance of awareness and accessibility to
outside plant capabilities at commercial and
univerSity laboratories.
• Materials analyses with ultimate concern for product yield, quality and reliability.
The Microbeam Laboratory equipment is engaged
prinCipally in high resolution imaging and localized
chemical analysis of microcircuits. The equipment
includes:
• Electron Beam Analysis - Scanning Auger
Microprobe, Scanning Electron Microscopes, and
Transmission Electron Microscope.
• Ion Beam Analysis - Ion Microprobe, Secondary
Ion Mass Spectrometer, and Ion Scattering Spectrometer.
• X-Ray Analysis - Energy Dispersive X-ray (SEM),
Wavelength Dispersive X-ray (SEM), X-ray
Photoelectron Spectrometer, X-ray Diffraction,
and X-ray Fluorescence.
The Chemistry Laboratory equipment affords a wide
variety of analyses, capable for solid, liquid, and
gaseous materials.
• Spectroscopy - Emission Spectrograph, Fourier
Transform Infrared Spectrophotometer, Ultraviolet-Visible Spectrophotometer, Organic Carbon
Analyzer, Mass Spectrometer, Atomic Absorption
Spectrophotometer (flame and graphite furnace)
and an Inductively Coupled Plasma Emission
Spectrophotometer.

• Thermal Analysis - Differential Scanning Colorimeter, Thermogravimetric Analyzer Thermomechanical Analyzer.
• Separation Methods - Gas Chromatograph, Ion
Chromatograph, Gas Chromatograph Mass Spectrometer, and Water, Oxygen, and Total Hydrocar~
bon Analyzers.
• Physical Testing - Profilometer, Microhardness
Measurement, and Viscometers.
• Wet Chemistry - Titrimetry, Gravimetry, specific
Ion 'Electrodes, Colorimeters, Bacteria Testing, and
other qualitative chemical testing.
Capability for all process/product Mil-Spec test
method methodology is maintained by the laboratory.
The department also maintains ongoing working
arrangements with commercial, university, and equipment manufacturers' technical service laboratories
and can obtain any material analysis in cases where
instrumental capabilities are not available in our own
facility.
Calibration Laboratory
Another important resource in the product assurance
system is Harris Semiconductor',s Calibration Lab.
This area is responsible for calibrating the electronic,
electrical, electro/mechanical, and optical equipment
used in both the production and engineering areas.
The accuracy of instruments used at Harris in calibration is traceable to the National Bureau of Standards.
The lab maintains a system which conforms to the
current revision of MIL-STD-4S662, "Calibration System Requirements."
Each instrument requiring calibration is given a calibration interval based upon stability, purpose, and
degree of use. The equipment is labeled with an identification tag on which is specified both the date of the
last calibration and of the next required calibration.
The Calibration Lab reports on a regular basis to each
user department. Equipment out of calibration is
taken out of service until calibration is performed. The
Quality organization performs periodic audits to
assure proper control in the using areas. Statistical
procedures are used where applicable in the calibration process.
Failure Analysis Laboratory
The Failure Analysis Laboratory's capabilities encompass the isolation and identification of all failure
modes/failure mechanisms, preparing comprehensive technical reports, and assigning appropriate
corrective actions. Research vital to understanding
the basic physics of the failure is also undertaken.

7-12

Failure analysis is a method of enhancing product reliability and determining corrective action. It is the final
and crucial step used to isolate potential reliability
problems that may have occurred during reliability
stressing. Accurate analysis results are imperative to
assess effective corrective actions. To ensure the
integrity of the analysis, correlation of the failure
mechanism to the initial electrical failure is essential.
A general failure analysis procedure has been established in accordance with the current revision of MILSTD-883, Section 5003. The analysis procedure was
designed on the premise that each step should provide information on the failure without destroying
information to be obtained from subsequent steps.
The exact steps for an analysis are determined as the
situation dictates. See Figures 4 and 5 that represent
the Failure Analysis Flow. Records are maintained by
laboratory personnel and contain data, the failure analyst's notes, and the formal Product Analysis Report.

Reliability
Reliability Assessment and Enhancement
At Harris Semiconductor, reliability is built into every
product by emphasizing quality throughout manufacturing. This starts by ensuring the excellence of the
design, layout, and manufacturing process. The quality of the raw materials and workmanship is monitored
using statistical process control (SPC) to preserve the
reliability of the product. The primary and ultimate
goal of these efforts is to provide full performance to
the product specification throughout its useful life.
Product reliability is maintained through the following
sources.

Qualifications
Qualifications at Harris de-emphasize the sole
dependence on production product which is only
available late in the development cycle. The focus is
primarily on the use of test vehicles to establish
design ground rules for the product and the process
that will eliminate any wearout mechanisms during
the useful life of the product. However, to comply with
the military requirements concerning reliability, product qualifications are performed.
In-line Reliability Monitors
In-line reliability monitors provide immediate feedback to manufacturing regarding the quality of
workmanship, quality of raw materials, and the
ultimate reliability implications. The rudimentary implementation of this monitoring is the "First Line of
Defense," which is a pass/fail acceptance procedure
based on control charts and trend analysiS. The second level of monitoring is referred to as the "Early
Warning System" and incorporates extensive diagnostic and characterization capabilities of various
components that may impact the device reliability or
stability. The quick feedback from these schemes
allows more accurate correlation to process steps
and corrective actions.

Reliability Fundamentals
Reliability, by its nature, is a mixture of engineering
and probability statistics. This combination has
derived a vocabulary of terms essential for describing
the reliability of a device or system. Since reliability
involves a measurement of time, it is necessary to
accelerate the failures which may occur. This, then,

FIGURE 4. NON-DESTRUCTIVE

FIGURE 5. DESTRUCTIVE

7-13

FIT =

introduces terms like "activation energy" and "acceleration factor," which are needed to relate results of
stressing to normal operating conditions (see Table
7). Also, to assess product reliability requires failures.
Therefore, only a statistical sample can be used to
determine the model of the failure distribution for the
entire population of product.

K
j=1

Failure Rate Primer

B=
K=

# of distinct possible failure mechanisms

Xi=

# of failures for a given failure mechanism
i = 1, 2, ... B

Failure Rate Calculations
Reliability data for products may be composed of several different failure mechanisms and requires careful
combining of diverse failure rates into one comprehensive failure rate. Calculating the failure rate is further complicated because failure mechanisms are
thermally accelerated at varying rates and thereby
have differing accelerating factors. Additionally, this
data is usually obtained from a variety of life tests at
unique stress temperatures. The equation (right) accounts for these considerations and then inserts a
statistical factor to obtain the confidence interval for
the failure rate.

xM

2:

# of life tests being combined

TDGj

=

Total
device
hours of
(unaccelerated) for Life Testj

AFij

=

Acceleration factor for appropriate failure
mechanism i = 1,2, ••• K

M

=

Statistical factor for calculating the upper
confidence limit (M is a function of the total
number of failures and an estimate of the
standard deviation of the failure rates)

test

In the failure rate calculation, Acceleration Factors (AFij)
are used to derate the failure rate from thermally accelerated Life Test conditions to a failure rate indicative of-

TABLE 7. FAILURE RATE PRIMER
GLOSSARY OF TERMS
TERMS/DEFINITION

UNITS/DESCRIPTION

FAILURE RATE>"

AT - Failure In Time

For Semiconductors, usually expressed in FITs.

1 FIT - 1 failure in 109 device hours.
Equivalent to 0.0001 %/1000 hours
ATs=
# Failures
x109 xm

Represents useful life failure rate (which implies a constant
failure rate).
ATs are not applicable for infant mortality orwearoutfailure
rate expressions.

# Devices x # hours stress x AF
m109 AF -

Factor to establish Confidence Interval
Establishes in terms of FITs
Acceleration Factor at temperature for a given failure
mechanism

MTTF - Mean Time To Failure

Mean Time' is measured usually in hours or years.

For semiconductors, MTTF is the average or mean life expectancy
of a device.

1 Year = 8760 hours

If an exponential distribution is assumed then the mean time to
fail of the population will be when 63% olthe parts have failed.

time

When working with a constanl failure rate the MTTF can be
calculated by taking the reciprocal of the failure rate.
MTTF = I"-{exponential model)Example: =10 FITs at +550 C
The MTTF is: MTTF = IA = 0.1 x 109 hours
=100Mhours

CONFIDENCE INTERVAL (C. I.)

Example:

Establishes a Confidence Interval for failure rate predictions.
Usually the upper limit is most significant In expressing failure
rates.

"10 FITs @ a 95% C.1. @ 550 C" means only that you are 95%
certain that the FITs <10 at +55?C use conditions.

7-14

use temperatures. Though no standards exist, a
temperature of +55 0 C has been popular and allows
some comparison of product failure rates. All Harris
Semiconductor Reliability Reports will derate to
+55 0 C at both the 60% and 95% confidence
intervals.

ture and/or voltage). The stresses will provide the time
to failure (Tt) for the populations which will allow the
simultaneous solution for the Activation Energy by
putting the experimental results into the following
equations.
In

Acceleration Factors
The Acceleration Factors (AF) are determined from
the Arrhenius Equation. This equation is used to describe physiochemical reaction rates and is an
appropriate model for expressing the thermal acceleration of semiconductor failure mechanisms.

[~(T~se

EXP

AF =

Acceleration Factor

Ea =

Thermal Activation Energy in eV from Table 8
Boltzmann's Constant (8.62 x 10- 5 eV/oK)

K=

- Tst:ess

1]

AF=

Ea
KT1

Then, by subtracting the two equations, the Activation
Energy becomes the only variable, as shown below.
In(tf1) - In(tf2) = Ea/k(1/T1-1 /T2)
Ea = K* ((In (tf1 ) - In(tf2»/(1 /T1-1 /T2»

Both Tuse and Tstress (in degrees Kelvin) include the
internal temperature rise of the device and therefore
represent the junction temperature. With the use of
the Arrhenius Equation, the thermal Activation Energy
(Ea) term is a major influence on the result. This term
is usually empirically derived and can vary widely.
Activation Energy
To determine the Activation Energy (Ea) of a
mechanism (see Table 8) you must run at least two
(preferably more) tests at different stresses (temperaTABLE 8.

(tf1) = C +

The Activation Energy may be estimated by graphical
analysis plots. Plotting In time and In temperature then
provides a convenient nomogram that solves (estimates) the Activation Energy.
Table 9 is a summary of military generiC groups by
process descriptions.
All Harris Reliability Reports from qualifications and
Group C1 (all high temperature operating life tests)
will provide the data on all factors necessary to calculate and verify the reported failure rate (in FITs) using
the methods outlined in this primer.

FAILURE MECHANISM

FAILURE
MECHANISM

ACTIVATION
ENERGY

SCREENING AND
TESTING METHODOLOGY

Oxide Defects

0.3 -0.5eV

High temperature operating life (HTOL) and
voltage stress. Defect density test vehicles.

Statistical Process Control of oxide parameters,
defect density control, and voltage stress testing.

Silicon
Defects (Bulk)

0.3 -0.5eV

HTOL & voltage stress screens.

Vendor Statistical Quality Control programs, and
Statistical Process Control on thermal processes.

Highly accelerated stress tesing (HAST)

Passivation dopant control, hermetic seal control,
improved mold compounds, and product handling.

Temperature cycling, temperature and
mechanical shock, and environmental
stressing.

Vendor Statistical Quality Control programs,
Statistcal Process Control of assembly processes
proper handling methods.

Test vehicle characterizations at highly
elevated temperatures.

Design ground rules, wafer process statistical
process steps, photoresist, metals and
passivation

Corrosion

0.45eV

Assembly
Defects

0.5 -0.7eV

Electromigration
- AI Line
- Contact

O.BeV
0.geV

Mask Defects/
Photoresist
Defects

0.7eV

Contamination

Charge
Injection

CONTROL METHODOLOGY

Mask FAB comparator, print checks, defect

Clean room control, clean mask, pellicles

density monitor in FAB, voltage stress test
and HTOL.

Statistical Process Control or photoresistfetch processes.

1.0eV

C-V stress at oxide/interconnect, wafer
FAB device stress test (EWS) and HTOL.

Statistical Process Control of C-V data, oxide/
interconnect cleans, high integrity glassivation .
and clean assembly processes.

1.3eV

HTOL & oxide characterization.

Design ground rules, wafer level Statistical

Process Control and critical dimensions for
oxides.

7-15

Qualification Procedures
New products are reliably introduced to market by the
proper use of design techniques and strict adherence
to process layout ground rules. Each design is reviewed from its conception through early production
to ensure compliance to minimum failure rate standards. Ongoing monitoring of reliability performance is
accomplished through compliance to MIL-STO-883
and standard Quality Conformance Inspection as defined in Method 5005.
New process/product qualifications have two major
requirements imposed. First is a check to verify the
proper use of process methodology, design techTABLE 9.

niques, and layout ground rules. Second is a series of
stress tests designed to accelerate .failure mechanisms and demonstrate the reliability of integrated circuits.
From the earliest stages of a new product's life, the
design phase, through layout, and in every step of the
manufacturing process, reliability is an integral part of
every Harris Semiconductor product. This kind of attention to detail ''from the ground up" is the reason
why our customers can expect the highest quality for
any application.

HIGH TEMPERATURE OPERATING UFE TEST SUMMARY

GROUP C

GENERIC
GROUP

GROUP NAME

PROCESS OESCRIPTION

qUANTITY

QUANTITY
FAILURE

HOURS
@1250 C

FAILURE
RATE FITs
@550 C60%CI
62

0-49-3

Op. Amplifiers

Std. Linear, 01 w/NiCr resistors

3462

6

3,215,708

0-49-4

Op. Amplifiers

Std. Linear, 01 w/NiCr resistors

324

1

429,945

17

0-53

High Voltage
Op. Amplifiers

High voltage 01

315

0

284,943

20
100

0-56

Oata Acquisition

High beta high frequency, 01, NICr

1022

5

1,868,349

F-103

Telecommunications

SAJIIVA

199

0

403,960

5

F-81-3

NO Converters

SAJIIVA

201

0

183,222

10

F-81-4

AID Converters

SAJIIVA

217

1

328,000

12

F-82

Switches & Mux

01 AI Gate & Si Gate MOS

121

0

82,836

23

F-99-3

Active Rlters

SAJIIVA

196

1

184,262

24

F-99-4

Active Rlters

SAJIIVA

407

1

470,324

9

G-85

Op. Amplifiers

Std. Linear, MOS, & High
Frequency J FET

532

1

535,728

11

G-86

Comparators

Combination, Std. Linear & MOS

154

0

153,400

25

G-94-3

Switches & Mux

01 AI & Si Gate Linear CMOS

4351

41

7,443,054

103

G-94-4

Switches & Mux

01 AI & Si Gate Linear CMOS

906

0

889,816

20

C-41-4

CMOS RAMs

SAJICMOS

2418

19

2,247,526

31

C-41-5

CMOS RAMs

SAJICMOS

1104

10

1,105,094

53

C-42-4

CMOS PROMs &
HPALs

SAJICMOS

2645

28

4,074,728

61

C-l05-4

Microprocessor and
Peripherals

SAJICMOS

3638

12

4,099,002

17

NOTE: All infant mortality failures (up to 168 hours or equivalent) have been removed from products sampled.

7-16

FLOW - PRODUCT DEVELOPMENT

RELIABILITY FOCUS

I

PRODUCT DEFINITION REVIEW

I

• Assumes Process Development Required

I

CONCEPT REVIEW

I

• Evaluate Reliability Risks Factors
• Attain Commitment for Test Vehicle (TIl.) Development

I

DESIGN REVIEW PART 1

l-

• Review Test Vehicle Development and Stress Test Plan
• Review Package Requirements
• Review Latent Failure Mechanism History for Design Sensitivity and Elimination
• Review Ground Rules for Design and Elimination of Wearout Mechanisms
• Review Process Characterization, Statistical Control & Capability which are Design
Considerations

I

DESIGN REVIEW PART 2

I

• Review Test Vehicle Stress Results
• Review Device Modeling & Simulations
• Review Process Variability & Producibility
• Define Wafer Reliability Monitor Vehicles, Application of Early Warning System

I

LAYOUT REVIEW PART 1

l-

• Verify Wearout Mechanisms are Eliminated by Design & Process Control
(Test Vehicle + SPC)
• Evaluate Design of Chip to Package Risk Factors
• Review Ground Rule Checks (ORCs)
• Establish Reliability Test, Stress and Failure Analysis Capabilities. Project Failure Rate
Based on TIl. Data.

I

LAYOUT REVIEW 2

I

• Review Burn-In Diagrams for Production and Qualification

I

EVALUATION REVIEW

I

• Review Product Characterization to Data Shee~ ESD, Latch-up & DPA Results &
Define Corrective Actions

• Review Overall Qualification Plan & Begin Balance of Life Test

• Review of Life Test Data & Failure Mechanisms. Define Corrective Actions
• Utilize Statistical DeSign of Experiments (DOX) if Required to Adjust Process or Design
• Define Necessary Changes to Eliminate Any Systematic Failure Mechanism
• If Mature Process - Grant Generic Release

I
rI

NEW PRODUCT TRANSFER

MANUFACTURE

I

• Qualification Requirements Complete and Presented. Meet FIT Rate Requirements

l-

• Reliabiltiy Monitors:

• Review Infant Mortality (I.M.) Burn-in Results. If Greater Than 1% at 1250 C
Determinel.M. Burn-in Requirements

~
~

Real Time Early Warning Wafer Level Reliability control
Real Time Reliability Control of Burn-in PDA wilh Control Charts

~

Add-On Life Testing:

- Mil Std Group C & 0
- Industrial/Commercial Life Testing

• Trend Analysis of Reliability Performance Used to Develop Product Improvements
• Special Studies

I
-I

SHIPMENT

CONTINUOUS IMPROVEMENT

I

• High Quality and Reliability Products to Harris Customers

r

• Failure Analysis - Determine Assignable Cause of Failure
• Closed Loop Corrective Action Process
• Continuous Improvement Objectives in Product Reliability & Quality

FIGURE 6. NEW PROCESS PRODUCT DEVELOPMENT AND LIFE CYCLE

7-17

PAGE
ANALOG PRODUCT LISTING .........................................................

8-3

HARRIS SALES LOCATIONS.... .... ....... ...... .. .. . . .. .. . . .... ... .. .. . . .. . .... .... .

8-7

8-1

. - - - - - - - - - Analog Product Listing
Analog-to-Digital Converters
HI-574N883
HI-674N883
HI-774/883

Fast, Complete 12-Bit ND Converter With Microprocessor Interface
Fast, Complete 12-Bit ND Converter With Microprocessor Interface
Fast, Complete 12-Bit ND Converter With Microprocessor Interface

Digital-to Analog Converters
HI-562N883
12-Bit High Speed Monolithic Digital-to-Analog Converter
HI-565N883
High Speed, Monolithic Digital-to-Analog Converter With Reference
HI-DAC87V/883 Wide Temperature Range Monolithic 12-Bit Digital-to-Analog Converter

Multiplexers
SINGLE a/DIFFERENTIAL 4 CHANNEL:

HI-508/883
HI-509/883
HI-518/883
HI-548/883
HI-549/883
HI-1818A/883
HI-1828A/883

Single 8 Channel CMOS Analog Multiplexer
Differential 4 Channel CMOS Analog Multiplexer
8 Channel/Differential 4 Channel CMOS High Speed Analog Multiplexer
. Single 8 Channel CMOS Analog Multiplexer With Active Overvoltage Protection
Differential 4 Channel CMOS Analog Multiplexer With Active Overvoltage Protection
Low Resistance Single 8 Channel CMOS Analog Multiplexer
Low Resistance Differential 4 Channel CMOS Analog Multiplexer

SINGLE 16/DIFFERENTIAL a CHANNEL:

HI-506/883
HI-507/883
HI-516/883
HI-546/883
HI-547/883

Single 16 Channel CMOS Analog Multiplexer
Differential 8 Channel CMOS Analog Multiplexer
16 Channel/Differential 8 Channel CMOS High Speed Analog Multiplexer
Single 16 Channel CMOS Analog Multiplexer With Active Overvoltage Protection
Differential 8 Channel CMOS Analog Multiplexer With Active Overvoltage Protection

4 CHANNEL:

HI-524/883

4 Channel Wideband Multiplexer

Operational Amplifiers: High Slew Rate
SINGLES:

HA-2500/883
HA-2502/883
HA-251 0/883
HA-2512/883
HA-2520/883
HA-2522/883
HA-2529/883
HA-2539/883
HA-2540/883
HA-2541/883
HA-2542/883
HA-2544/883
HA-2620/883
HA-2622/883
HA-5101/883
HA-5111/883
HA-5147/883
HA-5190/883

Precision High Slew Rate Operational Amplifier
Precision High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
Uncompensated, High Slew Rate Operational Amplifier
Uncompensated, High Slew Rate Operational Amplifier
Uncompensated, High Slew Rate High Output Current, Operational Amplifier
Very High Slew Rate Wideband Operational Amplifier
Wideband, Fast Settling Operational Amplifier
Wideband, Fast Settling, Unity Gain Stable, Operational Amplifier
Wideband, High Slew Rate, High Output Current, Operational Amplifier
Video Operational Amplifier
Very Wideband, High Impedance Uncompensated Operational Amplifier
Very Wideband, High Impedance Uncompensated Operational Amplifier
Low Noise, High Performance Operational Amplifier
Low Noise, High Performance Uncompensated Operational Amplifier
Ultra-Low, Precision High Slew Rate Wideband Operational Amplifier
Wideband, Fast Settling Operational Amplifier

8-3

r - - - - - - - - - Analog Product Listing

(Continued) - - - - - - - - - ,

Operational Amplifiers: High Slew-Rate: (Continued)
DUALS:

HA-5112/883

Dual, Low Noise, High Performance Uncompensated Operational Amplifier

QUADS:

HA-2400/883
HA-5114/883

PRAM Four Channel Programmable Operational Amplifier
Low Noise, High Performance Operational Amplifier

Operational Amplifiers: Wide Bandwidth
SINGLES:

HA-251 0/883
HA-2512/883
HA-2520/883
HA-2522/883
HA-2539/883
HA-2540/883
HA-2541/883
HA-2542/883
HA-2600/883
HA-2602/883
HA-2620/883
HA-2622/883
HA-5111/883
HA-5137/883
HA-5147/883
HA-5190/883

High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
Uncompensated, High Slew Rate Operational Amplifier
Uncompensated, High Slew Rate Operational Amplifier
,Very High Slew Rate Wideband Operational Amplifier
Wideband, Fast Settling Operational Amplifier
Wideband, Fast Settling, Unity Gain Stable, Operational Amplifier
Wideband, High Slew Rate, High Output Current, Operational Amplifier
Wideband, High Impedance Operational Amplifier
Wideband, High Impedance Operational Amplifier
Very Wideband, High Impedance Uncompensated Operational Amplifier
Very Wideband, High Impedance Uncompensated Operational Amplifier
Low Noise, High Performance Uncompensated Operational Amplifier
Ultra-Low Noise, Precision Wideband Operational Amplifier
Ultra-Low, Precision High Slew Rate Wideband Operational Amplifier
Wideband, Fast Settling Operational Amplifier

DUALS:

HA-5112/883

Dual, Low Noise, High Performance Uncompensated Operational Amplifier

QUADS:

HA-2400/883
HA-5114/883

PRAM Four Channel Programmable Operational Amplifier
Low Noise; High Performance Operational Amplifier

Operational Amplifiers: Precision
HA-5127/883
HA-5134/883
HA-5135/883
HA-5137/883
HA-5147/883
HA-5177/883

Ultra-Low Noise, Precision Operational Amplifier
Precision Quad Operational Amplifier
Precision Operational Amplifier
Ultra-Low Noise, Precision Wideband Operational Amplifier
Ultra-Low, Precision High Slew Rate Wideband Operational Amplifier
Ultra-Low Offset Voltage Operational Amplifier

Operational Amplifiers: Low Power
SINGLES:

HA-5141/883
HA-5151/883

Single, Ultra-Low Power Operational Amplifier
Single, Low Power Operational Amplifier

DUALS:

HA-5142/883
HA-5152/883

Dual, Ultra-Low Power Operational Amplifier
Dual, Low Power Operational Amplifier

QUADS:

HA-5144/883
HA-5154/883

Quad, Ultra-Low Power Operational Amplifier
Quad, Low Power Operational Amplifier

8-4

. - - - - - - - - - - Analog Product Listing

(Continued) - - - - - - - - - ,

Operational Amplifiers: General PurposeSINGLES:

HA-2S00/883
HA-2600/883
HA-2602/883
HA-S101/883
HA-S111/883

Precision High Slew Rate Operational Amplifier
Wideband, High Impedance Operational Amplifier
Wideband, High Impedance Operational Amplifier
Low Noise, High Performance Operational Amplifier
Low Noise, High Performance Uncompensated Operational Amplifier

DUALS:

HA-S102/883
HA-S112/883

Dual, Low Noise, High Performance Operational Amplifier
Dual, Low Noise, High Performance Uncompensated Operational Amplifier

QUADS:

HA-2400/883
HA-4741/883
HA-S104/883
HA -S114/883

PRAM Four Channel Programmable Operational Amplifier
Quad Operational Amplifier
Low Noise, High Performance, Quad Operational Amplifier
Low Noise, High Performance Operational Amplifier

Operational Amplifiers: High Voltage
HA-2640/883

High Voltage Operational Amplifier

Operational Amplifiers: Addressable
HA-2400/883

PRAM Four Channel Programmable Operational Amplifier

Operational Amplifiers: Current Buffers
HA-S002/883
HA-S033/883

Monolithic, Wideband, High Slew Rate, High Output Current Buffer
Video Buffer

Comparators
HA-4902/883

Precision Quad Comparator

Switches
SPST:

HI-S040/883

SPST CMOS Analog Switch

2 x SPST:
HI-200/883
HI-222/883
HI-300/883
HI-304/883
HI-381/883
HI-S041/883
HI-S048/883

Dual SPST CMOS Analog Switch
Dual SPST High Frequency/Video Switch
Dual SPST CMOS Analog Switch
Dual SPST CMOS Analog Switch
Dual SPST CMOS Analog Switch
Dual SPST CMOS Analog Switch
Dual SPST CMOS Analog Switch

a

4 x SPST:
HI-201/883
HI-201 HS/883

Quad SPST CMOS Analog Switch
High Speed Quad SPST CMOS Analog Switch

SPOT:

HI-301/883
HI-30S/883
HI-387/883
HI-5042/883
HI-50S0/883

en
w

<.)

SPDT CMOS Analog
SPDT CMOS Analog
SPDT CMOS Analog
SPDT CMOS Analog
SPDT CMOS Analog

Switch
Switch
Switch
Switch
Switch

8-5

:z
w
c..
c..

""

, - - - - - - - - - - Analog Product Listing

(Continued) - - - - - - - - - ,

Switches (Continued)
2x SPOT:

HI-303/883
HI-307/883
HI-390/883
HI-5043/883
HI-5051/883

Dual SPDT CMOS Analog Switch
Dual SPDT CMOS Analog Switch
Dual SPDT CMOS Analog Switch
Dual SPDT CMOS Analog Switch
Dual SPDT CMOS Analog Switch

OPST:

HI-5044/883

DPST CMOS Analog Switch

2x OPST:

HI-302/883
HI-306/883
HI-384/883
HI-5045/883
HI-5049/883

Dual DPST CMOS Analog
Dual DPST CMOS Analog
Dual DPST CMOS Analog
Dual DPST CMOS Analog
Dual DPST CMOS Analog

Switch
Switch
Switch
Switch
Switch

OPDT:

HI-5046/883
HI-5046N883

DPDT CMOS Analog Switch
DPDT CMOS Analog Switch

4PST:

HI-5047/883
HI-5047N883

4PST CMOS Analog Switch
4PST CMOS Analog Switch

Sample and Hold Amplifiers
HA-2420/883
HA-5330/883

Fast Sample and Hold
Very High Speed Precisio!,) Monolithic Sample and Hold Amplifier

Telecommunication Circuits
HC-55564/883

Continuously Variable Slope Delta-Modulator (CVSD)

8-6

SalesOffices---------------------------------------------------------U.S. HEADQUARTERS
Harris Semiconductor
1301 Woody Burke Road
Melbourne, Florida 32902
TEL: (407) 724-3739

EUROPEAN HEADQUARTERS
Harris Semiconductor
Mercure Centre
Rue de la Fusse 100
Brussels, Belgium 1130
TEL: (32) 246-2201

SOUTH ASIA
Harris Semiconductor H.K LId
13/F Fourseas Building
208-212 Nathan Road
Tslmshalsul, Kowloon
Hong Kong
TEL: (852) 3-723-6339

NORTH ASIA
Harris KK.
Shinjuku NS Bldg. Box 6153
2-4-1 Nlshi-Shinjuku
Shlnjuku-Ku, Tokyo 163 Japan
TEL: 81-3-345-8911

Clark-Hurman Associates
TEL: (416) 453-1118

Foster & Wager, Inc.
TEL: 016)385-7744

Oasis Sales
TEL: (414) 782-6660

Compass Marketing &
Sales, Inc.
TEL: (602) 995-0635

Glestlng & Associates
TEL: (513) 385-1105

Rep Associates Corp.
TEL: (319) 373-0152

Harris Marketing Inc~
TEL: (801) 974-5155

Trlonlc Associates, Inc.
TEL: (516) 466-2300

New Era Sales, Inc.
TEL: (301) 544-4100

Trllek, Inc.
TEL: (609) 429-1551

North American Representatives
Advanced Technical
Sales
TEL: (913) 782-8702
ATS
TEL: (508) 664-0888
Blakewood Electronic
Systems, Inc.
TEL: (604) 261-8099
CK Associates
TEL: (619) 279-0420

CSR Electronics
TEL: (404) 396-3720
EWing-Foley, Inc.
TEL: (916) 885-6591

Nova Marketing
TEL: (214) 750-6082

North American Distributors ----------------------------------------------Almac Electronics
TEL: (206) 643-9992

Falcon Electronics
TEL: (203) 878-5272

Hamilton/Avnet
TEL: (213) 558-2000

Schweber Electronics
TEL: (516) 334-7474

Anthem Electronics
TEL: (408) 452-2287

Gerber Electronics
TEL: (617) 769-6000

ITT MUllicomponents
TEL: (416) 736-1144

Wyle laboratories
TEL: (408) 727-2500

Electronics Marketing
Corporation
TEL: (614) 299-4161

Hall-Mark Electronics
TEL: (214) 343-5000

Newark Electronics
TEL: (312) 784-5100

mHARRIS
MILITARY AND AEROSPACE DIVISION

8-7

Notes
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